From 9f30e1773ba117f1082af87f723764b9216c25f9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E2=80=8BLaraib=20Khan?= <​laraib.khan@lampromellon.com> Date: Fri, 18 Dec 2020 10:53:24 +0500 Subject: [PATCH] AXI build --- quasar.anno.json | 140 +- quasar.fir | 10274 ++++----------- quasar.v | 6028 +++------ quasar_wrapper.anno.json | 2 +- quasar_wrapper.fir | 10890 ++++------------ quasar_wrapper.v | 6548 +++------- src/main/scala/lib/param.scala | 4 +- target/scala-2.12/classes/QUASAR$.class | Bin 0 -> 3815 bytes .../classes/QUASAR$delayedInit$body.class | Bin 0 -> 697 bytes target/scala-2.12/classes/QUASAR.class | Bin 0 -> 758 bytes target/scala-2.12/classes/lib/param.class | Bin 23339 -> 23339 bytes 11 files changed, 9353 insertions(+), 24533 deletions(-) create mode 100644 target/scala-2.12/classes/QUASAR$.class create mode 100644 target/scala-2.12/classes/QUASAR$delayedInit$body.class create mode 100644 target/scala-2.12/classes/QUASAR.class diff --git a/quasar.anno.json b/quasar.anno.json index 94b1f898..df7e208d 100644 --- a/quasar.anno.json +++ b/quasar.anno.json @@ -1,17 +1,4 @@ [ - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~quasar|quasar>io_ic_sel_premux_data", - "sources":[ - "~quasar|quasar>io_ic_rd_hit", - "~quasar|quasar>io_ifu_bus_clk_en", - "~quasar|quasar>io_mpc_reset_run_req", - "~quasar|quasar>io_dccm_rd_data_hi", - "~quasar|quasar>io_dccm_rd_data_lo", - "~quasar|quasar>io_core_id", - "~quasar|quasar>io_extintsrc_req" - ] - }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~quasar|quasar>io_dccm_rd_addr_lo", @@ -22,6 +9,25 @@ "~quasar|quasar>io_extintsrc_req" ] }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~quasar|quasar>io_iccm_wr_data", + "sources":[ + "~quasar|quasar>io_iccm_rd_data_ecc", + "~quasar|quasar>io_ic_rd_hit", + "~quasar|quasar>io_ic_rd_data", + "~quasar|quasar>io_ifu_axi_r_bits_id", + "~quasar|quasar>io_ifu_axi_r_valid", + "~quasar|quasar>io_ifu_bus_clk_en", + "~quasar|quasar>io_mpc_reset_run_req", + "~quasar|quasar>io_dccm_rd_data_hi", + "~quasar|quasar>io_dccm_rd_data_lo", + "~quasar|quasar>io_rst_vec", + "~quasar|quasar>io_nmi_vec", + "~quasar|quasar>io_core_id", + "~quasar|quasar>io_extintsrc_req" + ] + }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~quasar|quasar>io_iccm_rden", @@ -29,6 +35,8 @@ "~quasar|quasar>io_iccm_rd_data_ecc", "~quasar|quasar>io_ic_rd_hit", "~quasar|quasar>io_ic_rd_data", + "~quasar|quasar>io_ifu_axi_r_bits_id", + "~quasar|quasar>io_ifu_axi_r_valid", "~quasar|quasar>io_ifu_bus_clk_en", "~quasar|quasar>io_mpc_reset_run_req", "~quasar|quasar>io_rst_vec", @@ -39,6 +47,21 @@ "~quasar|quasar>io_extintsrc_req" ] }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~quasar|quasar>io_ic_sel_premux_data", + "sources":[ + "~quasar|quasar>io_ic_rd_hit", + "~quasar|quasar>io_ifu_axi_r_bits_id", + "~quasar|quasar>io_ifu_axi_r_valid", + "~quasar|quasar>io_ifu_bus_clk_en", + "~quasar|quasar>io_mpc_reset_run_req", + "~quasar|quasar>io_dccm_rd_data_hi", + "~quasar|quasar>io_dccm_rd_data_lo", + "~quasar|quasar>io_core_id", + "~quasar|quasar>io_extintsrc_req" + ] + }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~quasar|quasar>io_ic_rw_addr", @@ -55,11 +78,13 @@ }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~quasar|quasar>io_iccm_wr_data", + "sink":"~quasar|quasar>io_iccm_wr_size", "sources":[ "~quasar|quasar>io_iccm_rd_data_ecc", "~quasar|quasar>io_ic_rd_hit", "~quasar|quasar>io_ic_rd_data", + "~quasar|quasar>io_ifu_axi_r_bits_id", + "~quasar|quasar>io_ifu_axi_r_valid", "~quasar|quasar>io_ifu_bus_clk_en", "~quasar|quasar>io_mpc_reset_run_req", "~quasar|quasar>io_dccm_rd_data_hi", @@ -70,39 +95,6 @@ "~quasar|quasar>io_extintsrc_req" ] }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~quasar|quasar>io_iccm_rw_addr", - "sources":[ - "~quasar|quasar>io_iccm_rd_data_ecc", - "~quasar|quasar>io_ic_rd_hit", - "~quasar|quasar>io_ic_rd_data", - "~quasar|quasar>io_ifu_bus_clk_en", - "~quasar|quasar>io_mpc_reset_run_req", - "~quasar|quasar>io_rst_vec", - "~quasar|quasar>io_nmi_vec", - "~quasar|quasar>io_core_id", - "~quasar|quasar>io_dccm_rd_data_hi", - "~quasar|quasar>io_dccm_rd_data_lo", - "~quasar|quasar>io_extintsrc_req" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~quasar|quasar>io_ic_rd_en", - "sources":[ - "~quasar|quasar>io_ic_rd_hit", - "~quasar|quasar>io_ic_rd_data", - "~quasar|quasar>io_ifu_bus_clk_en", - "~quasar|quasar>io_mpc_reset_run_req", - "~quasar|quasar>io_rst_vec", - "~quasar|quasar>io_nmi_vec", - "~quasar|quasar>io_core_id", - "~quasar|quasar>io_dccm_rd_data_hi", - "~quasar|quasar>io_dccm_rd_data_lo", - "~quasar|quasar>io_extintsrc_req" - ] - }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~quasar|quasar>io_dccm_rd_addr_hi", @@ -115,18 +107,20 @@ }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~quasar|quasar>io_iccm_wren", + "sink":"~quasar|quasar>io_iccm_rw_addr", "sources":[ "~quasar|quasar>io_iccm_rd_data_ecc", "~quasar|quasar>io_ic_rd_hit", "~quasar|quasar>io_ic_rd_data", + "~quasar|quasar>io_ifu_axi_r_bits_id", + "~quasar|quasar>io_ifu_axi_r_valid", "~quasar|quasar>io_ifu_bus_clk_en", "~quasar|quasar>io_mpc_reset_run_req", - "~quasar|quasar>io_dccm_rd_data_hi", - "~quasar|quasar>io_dccm_rd_data_lo", "~quasar|quasar>io_rst_vec", "~quasar|quasar>io_nmi_vec", "~quasar|quasar>io_core_id", + "~quasar|quasar>io_dccm_rd_data_hi", + "~quasar|quasar>io_dccm_rd_data_lo", "~quasar|quasar>io_extintsrc_req" ] }, @@ -161,6 +155,25 @@ "~quasar|quasar>io_extintsrc_req" ] }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~quasar|quasar>io_iccm_wren", + "sources":[ + "~quasar|quasar>io_iccm_rd_data_ecc", + "~quasar|quasar>io_ic_rd_hit", + "~quasar|quasar>io_ic_rd_data", + "~quasar|quasar>io_ifu_axi_r_bits_id", + "~quasar|quasar>io_ifu_axi_r_valid", + "~quasar|quasar>io_ifu_bus_clk_en", + "~quasar|quasar>io_mpc_reset_run_req", + "~quasar|quasar>io_dccm_rd_data_hi", + "~quasar|quasar>io_dccm_rd_data_lo", + "~quasar|quasar>io_rst_vec", + "~quasar|quasar>io_nmi_vec", + "~quasar|quasar>io_core_id", + "~quasar|quasar>io_extintsrc_req" + ] + }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~quasar|quasar>io_dccm_rden", @@ -181,11 +194,19 @@ }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~quasar|quasar>io_dccm_wr_addr_hi", + "sink":"~quasar|quasar>io_ic_rd_en", "sources":[ + "~quasar|quasar>io_ic_rd_hit", + "~quasar|quasar>io_ic_rd_data", + "~quasar|quasar>io_ifu_axi_r_bits_id", + "~quasar|quasar>io_ifu_axi_r_valid", + "~quasar|quasar>io_ifu_bus_clk_en", + "~quasar|quasar>io_mpc_reset_run_req", + "~quasar|quasar>io_rst_vec", + "~quasar|quasar>io_nmi_vec", + "~quasar|quasar>io_core_id", "~quasar|quasar>io_dccm_rd_data_hi", "~quasar|quasar>io_dccm_rd_data_lo", - "~quasar|quasar>io_mpc_reset_run_req", "~quasar|quasar>io_extintsrc_req" ] }, @@ -195,6 +216,8 @@ "sources":[ "~quasar|quasar>io_iccm_rd_data", "~quasar|quasar>io_ic_rd_hit", + "~quasar|quasar>io_ifu_axi_r_bits_id", + "~quasar|quasar>io_ifu_axi_r_valid", "~quasar|quasar>io_ifu_bus_clk_en", "~quasar|quasar>io_mpc_reset_run_req", "~quasar|quasar>io_dccm_rd_data_hi", @@ -205,18 +228,11 @@ }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~quasar|quasar>io_iccm_wr_size", + "sink":"~quasar|quasar>io_dccm_wr_addr_hi", "sources":[ - "~quasar|quasar>io_iccm_rd_data_ecc", - "~quasar|quasar>io_ic_rd_hit", - "~quasar|quasar>io_ic_rd_data", - "~quasar|quasar>io_ifu_bus_clk_en", - "~quasar|quasar>io_mpc_reset_run_req", "~quasar|quasar>io_dccm_rd_data_hi", "~quasar|quasar>io_dccm_rd_data_lo", - "~quasar|quasar>io_rst_vec", - "~quasar|quasar>io_nmi_vec", - "~quasar|quasar>io_core_id", + "~quasar|quasar>io_mpc_reset_run_req", "~quasar|quasar>io_extintsrc_req" ] }, @@ -1223,7 +1239,7 @@ }, { "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~quasar|csr_tlu>_T_745" + "target":"~quasar|csr_tlu>_T_755" }, { "class":"firrtl.options.TargetDirAnnotation", diff --git a/quasar.fir b/quasar.fir index aad292bf..9b2c9ce8 100644 --- a/quasar.fir +++ b/quasar.fir @@ -73361,972 +73361,982 @@ circuit quasar : reg _T_339 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_339 <= mfdc_ns @[lib.scala 374:16] mfdc_int <= _T_339 @[dec_tlu_ctl.scala 1728:11] - node _T_340 = bits(io.dec_csr_wrdata_r, 18, 16) @[dec_tlu_ctl.scala 1737:39] - node _T_341 = not(_T_340) @[dec_tlu_ctl.scala 1737:19] - node _T_342 = bits(io.dec_csr_wrdata_r, 11, 0) @[dec_tlu_ctl.scala 1737:66] - node _T_343 = cat(_T_341, _T_342) @[Cat.scala 29:58] - mfdc_ns <= _T_343 @[dec_tlu_ctl.scala 1737:12] - node _T_344 = bits(mfdc_int, 14, 12) @[dec_tlu_ctl.scala 1738:28] - node _T_345 = not(_T_344) @[dec_tlu_ctl.scala 1738:19] - node _T_346 = bits(mfdc_int, 11, 0) @[dec_tlu_ctl.scala 1738:54] - node _T_347 = cat(_T_345, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_340 = bits(io.dec_csr_wrdata_r, 18, 16) @[dec_tlu_ctl.scala 1733:40] + node _T_341 = not(_T_340) @[dec_tlu_ctl.scala 1733:20] + node _T_342 = bits(io.dec_csr_wrdata_r, 11, 7) @[dec_tlu_ctl.scala 1733:67] + node _T_343 = bits(io.dec_csr_wrdata_r, 6, 6) @[dec_tlu_ctl.scala 1733:95] + node _T_344 = not(_T_343) @[dec_tlu_ctl.scala 1733:75] + node _T_345 = bits(io.dec_csr_wrdata_r, 5, 0) @[dec_tlu_ctl.scala 1733:119] + node _T_346 = cat(_T_344, _T_345) @[Cat.scala 29:58] + node _T_347 = cat(_T_341, _T_342) @[Cat.scala 29:58] node _T_348 = cat(_T_347, _T_346) @[Cat.scala 29:58] - mfdc <= _T_348 @[dec_tlu_ctl.scala 1738:12] - node _T_349 = bits(mfdc, 18, 16) @[dec_tlu_ctl.scala 1742:46] - io.dec_tlu_dma_qos_prty <= _T_349 @[dec_tlu_ctl.scala 1742:39] - node _T_350 = bits(mfdc, 11, 11) @[dec_tlu_ctl.scala 1743:46] - io.dec_tlu_external_ldfwd_disable <= _T_350 @[dec_tlu_ctl.scala 1743:39] - node _T_351 = bits(mfdc, 8, 8) @[dec_tlu_ctl.scala 1744:46] - io.dec_tlu_core_ecc_disable <= _T_351 @[dec_tlu_ctl.scala 1744:39] - node _T_352 = bits(mfdc, 6, 6) @[dec_tlu_ctl.scala 1745:46] - io.dec_tlu_sideeffect_posted_disable <= _T_352 @[dec_tlu_ctl.scala 1745:39] - node _T_353 = bits(mfdc, 3, 3) @[dec_tlu_ctl.scala 1746:46] - io.dec_tlu_bpred_disable <= _T_353 @[dec_tlu_ctl.scala 1746:39] - node _T_354 = bits(mfdc, 2, 2) @[dec_tlu_ctl.scala 1747:46] - io.dec_tlu_wb_coalescing_disable <= _T_354 @[dec_tlu_ctl.scala 1747:39] - node _T_355 = bits(mfdc, 0, 0) @[dec_tlu_ctl.scala 1748:46] - io.dec_tlu_pipelining_disable <= _T_355 @[dec_tlu_ctl.scala 1748:39] - node _T_356 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1757:70] - node _T_357 = eq(_T_356, UInt<12>("h07c2")) @[dec_tlu_ctl.scala 1757:77] - node _T_358 = and(io.dec_csr_wen_r_mod, _T_357) @[dec_tlu_ctl.scala 1757:48] - node _T_359 = not(io.interrupt_valid_r) @[dec_tlu_ctl.scala 1757:89] - node _T_360 = and(_T_358, _T_359) @[dec_tlu_ctl.scala 1757:87] - node _T_361 = not(io.take_ext_int_start) @[dec_tlu_ctl.scala 1757:113] - node _T_362 = and(_T_360, _T_361) @[dec_tlu_ctl.scala 1757:111] - io.dec_tlu_wr_pause_r <= _T_362 @[dec_tlu_ctl.scala 1757:24] - node _T_363 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1764:61] - node _T_364 = eq(_T_363, UInt<12>("h07c0")) @[dec_tlu_ctl.scala 1764:68] - node wr_mrac_r = and(io.dec_csr_wen_r_mod, _T_364) @[dec_tlu_ctl.scala 1764:39] - node _T_365 = bits(io.dec_csr_wrdata_r, 31, 31) @[dec_tlu_ctl.scala 1767:39] - node _T_366 = bits(io.dec_csr_wrdata_r, 30, 30) @[dec_tlu_ctl.scala 1767:64] - node _T_367 = bits(io.dec_csr_wrdata_r, 31, 31) @[dec_tlu_ctl.scala 1767:91] - node _T_368 = not(_T_367) @[dec_tlu_ctl.scala 1767:71] - node _T_369 = and(_T_366, _T_368) @[dec_tlu_ctl.scala 1767:69] - node _T_370 = bits(io.dec_csr_wrdata_r, 29, 29) @[dec_tlu_ctl.scala 1768:41] - node _T_371 = bits(io.dec_csr_wrdata_r, 28, 28) @[dec_tlu_ctl.scala 1768:66] - node _T_372 = bits(io.dec_csr_wrdata_r, 29, 29) @[dec_tlu_ctl.scala 1768:93] - node _T_373 = not(_T_372) @[dec_tlu_ctl.scala 1768:73] - node _T_374 = and(_T_371, _T_373) @[dec_tlu_ctl.scala 1768:71] - node _T_375 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 1769:41] - node _T_376 = bits(io.dec_csr_wrdata_r, 26, 26) @[dec_tlu_ctl.scala 1769:66] - node _T_377 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 1769:93] - node _T_378 = not(_T_377) @[dec_tlu_ctl.scala 1769:73] - node _T_379 = and(_T_376, _T_378) @[dec_tlu_ctl.scala 1769:71] - node _T_380 = bits(io.dec_csr_wrdata_r, 25, 25) @[dec_tlu_ctl.scala 1770:41] - node _T_381 = bits(io.dec_csr_wrdata_r, 24, 24) @[dec_tlu_ctl.scala 1770:66] - node _T_382 = bits(io.dec_csr_wrdata_r, 25, 25) @[dec_tlu_ctl.scala 1770:93] - node _T_383 = not(_T_382) @[dec_tlu_ctl.scala 1770:73] - node _T_384 = and(_T_381, _T_383) @[dec_tlu_ctl.scala 1770:71] - node _T_385 = bits(io.dec_csr_wrdata_r, 23, 23) @[dec_tlu_ctl.scala 1771:41] - node _T_386 = bits(io.dec_csr_wrdata_r, 22, 22) @[dec_tlu_ctl.scala 1771:66] - node _T_387 = bits(io.dec_csr_wrdata_r, 23, 23) @[dec_tlu_ctl.scala 1771:93] - node _T_388 = not(_T_387) @[dec_tlu_ctl.scala 1771:73] - node _T_389 = and(_T_386, _T_388) @[dec_tlu_ctl.scala 1771:71] - node _T_390 = bits(io.dec_csr_wrdata_r, 21, 21) @[dec_tlu_ctl.scala 1772:41] - node _T_391 = bits(io.dec_csr_wrdata_r, 20, 20) @[dec_tlu_ctl.scala 1772:66] - node _T_392 = bits(io.dec_csr_wrdata_r, 21, 21) @[dec_tlu_ctl.scala 1772:93] - node _T_393 = not(_T_392) @[dec_tlu_ctl.scala 1772:73] - node _T_394 = and(_T_391, _T_393) @[dec_tlu_ctl.scala 1772:71] - node _T_395 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 1773:41] - node _T_396 = bits(io.dec_csr_wrdata_r, 18, 18) @[dec_tlu_ctl.scala 1773:66] - node _T_397 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 1773:93] - node _T_398 = not(_T_397) @[dec_tlu_ctl.scala 1773:73] - node _T_399 = and(_T_396, _T_398) @[dec_tlu_ctl.scala 1773:71] - node _T_400 = bits(io.dec_csr_wrdata_r, 17, 17) @[dec_tlu_ctl.scala 1774:41] - node _T_401 = bits(io.dec_csr_wrdata_r, 16, 16) @[dec_tlu_ctl.scala 1774:66] - node _T_402 = bits(io.dec_csr_wrdata_r, 17, 17) @[dec_tlu_ctl.scala 1774:93] - node _T_403 = not(_T_402) @[dec_tlu_ctl.scala 1774:73] - node _T_404 = and(_T_401, _T_403) @[dec_tlu_ctl.scala 1774:71] - node _T_405 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 1775:41] - node _T_406 = bits(io.dec_csr_wrdata_r, 14, 14) @[dec_tlu_ctl.scala 1775:66] - node _T_407 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 1775:93] - node _T_408 = not(_T_407) @[dec_tlu_ctl.scala 1775:73] - node _T_409 = and(_T_406, _T_408) @[dec_tlu_ctl.scala 1775:71] - node _T_410 = bits(io.dec_csr_wrdata_r, 13, 13) @[dec_tlu_ctl.scala 1776:41] - node _T_411 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 1776:66] - node _T_412 = bits(io.dec_csr_wrdata_r, 13, 13) @[dec_tlu_ctl.scala 1776:93] - node _T_413 = not(_T_412) @[dec_tlu_ctl.scala 1776:73] - node _T_414 = and(_T_411, _T_413) @[dec_tlu_ctl.scala 1776:71] - node _T_415 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1777:41] - node _T_416 = bits(io.dec_csr_wrdata_r, 10, 10) @[dec_tlu_ctl.scala 1777:66] - node _T_417 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1777:93] - node _T_418 = not(_T_417) @[dec_tlu_ctl.scala 1777:73] - node _T_419 = and(_T_416, _T_418) @[dec_tlu_ctl.scala 1777:71] - node _T_420 = bits(io.dec_csr_wrdata_r, 9, 9) @[dec_tlu_ctl.scala 1778:41] - node _T_421 = bits(io.dec_csr_wrdata_r, 8, 8) @[dec_tlu_ctl.scala 1778:66] - node _T_422 = bits(io.dec_csr_wrdata_r, 9, 9) @[dec_tlu_ctl.scala 1778:93] - node _T_423 = not(_T_422) @[dec_tlu_ctl.scala 1778:73] - node _T_424 = and(_T_421, _T_423) @[dec_tlu_ctl.scala 1778:70] - node _T_425 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1779:41] - node _T_426 = bits(io.dec_csr_wrdata_r, 6, 6) @[dec_tlu_ctl.scala 1779:66] - node _T_427 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1779:93] - node _T_428 = not(_T_427) @[dec_tlu_ctl.scala 1779:73] - node _T_429 = and(_T_426, _T_428) @[dec_tlu_ctl.scala 1779:70] - node _T_430 = bits(io.dec_csr_wrdata_r, 5, 5) @[dec_tlu_ctl.scala 1780:41] - node _T_431 = bits(io.dec_csr_wrdata_r, 4, 4) @[dec_tlu_ctl.scala 1780:66] - node _T_432 = bits(io.dec_csr_wrdata_r, 5, 5) @[dec_tlu_ctl.scala 1780:93] - node _T_433 = not(_T_432) @[dec_tlu_ctl.scala 1780:73] - node _T_434 = and(_T_431, _T_433) @[dec_tlu_ctl.scala 1780:70] - node _T_435 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1781:41] - node _T_436 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 1781:66] - node _T_437 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1781:93] - node _T_438 = not(_T_437) @[dec_tlu_ctl.scala 1781:73] - node _T_439 = and(_T_436, _T_438) @[dec_tlu_ctl.scala 1781:70] - node _T_440 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1782:41] - node _T_441 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1782:66] - node _T_442 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1782:93] - node _T_443 = not(_T_442) @[dec_tlu_ctl.scala 1782:73] - node _T_444 = and(_T_441, _T_443) @[dec_tlu_ctl.scala 1782:70] - node _T_445 = cat(_T_440, _T_444) @[Cat.scala 29:58] - node _T_446 = cat(_T_435, _T_439) @[Cat.scala 29:58] - node _T_447 = cat(_T_446, _T_445) @[Cat.scala 29:58] - node _T_448 = cat(_T_430, _T_434) @[Cat.scala 29:58] - node _T_449 = cat(_T_425, _T_429) @[Cat.scala 29:58] - node _T_450 = cat(_T_449, _T_448) @[Cat.scala 29:58] - node _T_451 = cat(_T_450, _T_447) @[Cat.scala 29:58] - node _T_452 = cat(_T_420, _T_424) @[Cat.scala 29:58] - node _T_453 = cat(_T_415, _T_419) @[Cat.scala 29:58] - node _T_454 = cat(_T_453, _T_452) @[Cat.scala 29:58] - node _T_455 = cat(_T_410, _T_414) @[Cat.scala 29:58] - node _T_456 = cat(_T_405, _T_409) @[Cat.scala 29:58] + mfdc_ns <= _T_348 @[dec_tlu_ctl.scala 1733:13] + node _T_349 = bits(mfdc_int, 14, 12) @[dec_tlu_ctl.scala 1734:29] + node _T_350 = not(_T_349) @[dec_tlu_ctl.scala 1734:20] + node _T_351 = bits(mfdc_int, 11, 7) @[dec_tlu_ctl.scala 1734:55] + node _T_352 = bits(mfdc_int, 6, 6) @[dec_tlu_ctl.scala 1734:72] + node _T_353 = not(_T_352) @[dec_tlu_ctl.scala 1734:63] + node _T_354 = bits(mfdc_int, 5, 0) @[dec_tlu_ctl.scala 1734:85] + node _T_355 = cat(_T_353, _T_354) @[Cat.scala 29:58] + node _T_356 = cat(_T_350, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_357 = cat(_T_356, _T_351) @[Cat.scala 29:58] + node _T_358 = cat(_T_357, _T_355) @[Cat.scala 29:58] + mfdc <= _T_358 @[dec_tlu_ctl.scala 1734:13] + node _T_359 = bits(mfdc, 18, 16) @[dec_tlu_ctl.scala 1742:46] + io.dec_tlu_dma_qos_prty <= _T_359 @[dec_tlu_ctl.scala 1742:39] + node _T_360 = bits(mfdc, 11, 11) @[dec_tlu_ctl.scala 1743:46] + io.dec_tlu_external_ldfwd_disable <= _T_360 @[dec_tlu_ctl.scala 1743:39] + node _T_361 = bits(mfdc, 8, 8) @[dec_tlu_ctl.scala 1744:46] + io.dec_tlu_core_ecc_disable <= _T_361 @[dec_tlu_ctl.scala 1744:39] + node _T_362 = bits(mfdc, 6, 6) @[dec_tlu_ctl.scala 1745:46] + io.dec_tlu_sideeffect_posted_disable <= _T_362 @[dec_tlu_ctl.scala 1745:39] + node _T_363 = bits(mfdc, 3, 3) @[dec_tlu_ctl.scala 1746:46] + io.dec_tlu_bpred_disable <= _T_363 @[dec_tlu_ctl.scala 1746:39] + node _T_364 = bits(mfdc, 2, 2) @[dec_tlu_ctl.scala 1747:46] + io.dec_tlu_wb_coalescing_disable <= _T_364 @[dec_tlu_ctl.scala 1747:39] + node _T_365 = bits(mfdc, 0, 0) @[dec_tlu_ctl.scala 1748:46] + io.dec_tlu_pipelining_disable <= _T_365 @[dec_tlu_ctl.scala 1748:39] + node _T_366 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1757:70] + node _T_367 = eq(_T_366, UInt<12>("h07c2")) @[dec_tlu_ctl.scala 1757:77] + node _T_368 = and(io.dec_csr_wen_r_mod, _T_367) @[dec_tlu_ctl.scala 1757:48] + node _T_369 = not(io.interrupt_valid_r) @[dec_tlu_ctl.scala 1757:89] + node _T_370 = and(_T_368, _T_369) @[dec_tlu_ctl.scala 1757:87] + node _T_371 = not(io.take_ext_int_start) @[dec_tlu_ctl.scala 1757:113] + node _T_372 = and(_T_370, _T_371) @[dec_tlu_ctl.scala 1757:111] + io.dec_tlu_wr_pause_r <= _T_372 @[dec_tlu_ctl.scala 1757:24] + node _T_373 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1764:61] + node _T_374 = eq(_T_373, UInt<12>("h07c0")) @[dec_tlu_ctl.scala 1764:68] + node wr_mrac_r = and(io.dec_csr_wen_r_mod, _T_374) @[dec_tlu_ctl.scala 1764:39] + node _T_375 = bits(io.dec_csr_wrdata_r, 31, 31) @[dec_tlu_ctl.scala 1767:39] + node _T_376 = bits(io.dec_csr_wrdata_r, 30, 30) @[dec_tlu_ctl.scala 1767:64] + node _T_377 = bits(io.dec_csr_wrdata_r, 31, 31) @[dec_tlu_ctl.scala 1767:91] + node _T_378 = not(_T_377) @[dec_tlu_ctl.scala 1767:71] + node _T_379 = and(_T_376, _T_378) @[dec_tlu_ctl.scala 1767:69] + node _T_380 = bits(io.dec_csr_wrdata_r, 29, 29) @[dec_tlu_ctl.scala 1768:41] + node _T_381 = bits(io.dec_csr_wrdata_r, 28, 28) @[dec_tlu_ctl.scala 1768:66] + node _T_382 = bits(io.dec_csr_wrdata_r, 29, 29) @[dec_tlu_ctl.scala 1768:93] + node _T_383 = not(_T_382) @[dec_tlu_ctl.scala 1768:73] + node _T_384 = and(_T_381, _T_383) @[dec_tlu_ctl.scala 1768:71] + node _T_385 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 1769:41] + node _T_386 = bits(io.dec_csr_wrdata_r, 26, 26) @[dec_tlu_ctl.scala 1769:66] + node _T_387 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 1769:93] + node _T_388 = not(_T_387) @[dec_tlu_ctl.scala 1769:73] + node _T_389 = and(_T_386, _T_388) @[dec_tlu_ctl.scala 1769:71] + node _T_390 = bits(io.dec_csr_wrdata_r, 25, 25) @[dec_tlu_ctl.scala 1770:41] + node _T_391 = bits(io.dec_csr_wrdata_r, 24, 24) @[dec_tlu_ctl.scala 1770:66] + node _T_392 = bits(io.dec_csr_wrdata_r, 25, 25) @[dec_tlu_ctl.scala 1770:93] + node _T_393 = not(_T_392) @[dec_tlu_ctl.scala 1770:73] + node _T_394 = and(_T_391, _T_393) @[dec_tlu_ctl.scala 1770:71] + node _T_395 = bits(io.dec_csr_wrdata_r, 23, 23) @[dec_tlu_ctl.scala 1771:41] + node _T_396 = bits(io.dec_csr_wrdata_r, 22, 22) @[dec_tlu_ctl.scala 1771:66] + node _T_397 = bits(io.dec_csr_wrdata_r, 23, 23) @[dec_tlu_ctl.scala 1771:93] + node _T_398 = not(_T_397) @[dec_tlu_ctl.scala 1771:73] + node _T_399 = and(_T_396, _T_398) @[dec_tlu_ctl.scala 1771:71] + node _T_400 = bits(io.dec_csr_wrdata_r, 21, 21) @[dec_tlu_ctl.scala 1772:41] + node _T_401 = bits(io.dec_csr_wrdata_r, 20, 20) @[dec_tlu_ctl.scala 1772:66] + node _T_402 = bits(io.dec_csr_wrdata_r, 21, 21) @[dec_tlu_ctl.scala 1772:93] + node _T_403 = not(_T_402) @[dec_tlu_ctl.scala 1772:73] + node _T_404 = and(_T_401, _T_403) @[dec_tlu_ctl.scala 1772:71] + node _T_405 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 1773:41] + node _T_406 = bits(io.dec_csr_wrdata_r, 18, 18) @[dec_tlu_ctl.scala 1773:66] + node _T_407 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 1773:93] + node _T_408 = not(_T_407) @[dec_tlu_ctl.scala 1773:73] + node _T_409 = and(_T_406, _T_408) @[dec_tlu_ctl.scala 1773:71] + node _T_410 = bits(io.dec_csr_wrdata_r, 17, 17) @[dec_tlu_ctl.scala 1774:41] + node _T_411 = bits(io.dec_csr_wrdata_r, 16, 16) @[dec_tlu_ctl.scala 1774:66] + node _T_412 = bits(io.dec_csr_wrdata_r, 17, 17) @[dec_tlu_ctl.scala 1774:93] + node _T_413 = not(_T_412) @[dec_tlu_ctl.scala 1774:73] + node _T_414 = and(_T_411, _T_413) @[dec_tlu_ctl.scala 1774:71] + node _T_415 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 1775:41] + node _T_416 = bits(io.dec_csr_wrdata_r, 14, 14) @[dec_tlu_ctl.scala 1775:66] + node _T_417 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 1775:93] + node _T_418 = not(_T_417) @[dec_tlu_ctl.scala 1775:73] + node _T_419 = and(_T_416, _T_418) @[dec_tlu_ctl.scala 1775:71] + node _T_420 = bits(io.dec_csr_wrdata_r, 13, 13) @[dec_tlu_ctl.scala 1776:41] + node _T_421 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 1776:66] + node _T_422 = bits(io.dec_csr_wrdata_r, 13, 13) @[dec_tlu_ctl.scala 1776:93] + node _T_423 = not(_T_422) @[dec_tlu_ctl.scala 1776:73] + node _T_424 = and(_T_421, _T_423) @[dec_tlu_ctl.scala 1776:71] + node _T_425 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1777:41] + node _T_426 = bits(io.dec_csr_wrdata_r, 10, 10) @[dec_tlu_ctl.scala 1777:66] + node _T_427 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1777:93] + node _T_428 = not(_T_427) @[dec_tlu_ctl.scala 1777:73] + node _T_429 = and(_T_426, _T_428) @[dec_tlu_ctl.scala 1777:71] + node _T_430 = bits(io.dec_csr_wrdata_r, 9, 9) @[dec_tlu_ctl.scala 1778:41] + node _T_431 = bits(io.dec_csr_wrdata_r, 8, 8) @[dec_tlu_ctl.scala 1778:66] + node _T_432 = bits(io.dec_csr_wrdata_r, 9, 9) @[dec_tlu_ctl.scala 1778:93] + node _T_433 = not(_T_432) @[dec_tlu_ctl.scala 1778:73] + node _T_434 = and(_T_431, _T_433) @[dec_tlu_ctl.scala 1778:70] + node _T_435 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1779:41] + node _T_436 = bits(io.dec_csr_wrdata_r, 6, 6) @[dec_tlu_ctl.scala 1779:66] + node _T_437 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1779:93] + node _T_438 = not(_T_437) @[dec_tlu_ctl.scala 1779:73] + node _T_439 = and(_T_436, _T_438) @[dec_tlu_ctl.scala 1779:70] + node _T_440 = bits(io.dec_csr_wrdata_r, 5, 5) @[dec_tlu_ctl.scala 1780:41] + node _T_441 = bits(io.dec_csr_wrdata_r, 4, 4) @[dec_tlu_ctl.scala 1780:66] + node _T_442 = bits(io.dec_csr_wrdata_r, 5, 5) @[dec_tlu_ctl.scala 1780:93] + node _T_443 = not(_T_442) @[dec_tlu_ctl.scala 1780:73] + node _T_444 = and(_T_441, _T_443) @[dec_tlu_ctl.scala 1780:70] + node _T_445 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1781:41] + node _T_446 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 1781:66] + node _T_447 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1781:93] + node _T_448 = not(_T_447) @[dec_tlu_ctl.scala 1781:73] + node _T_449 = and(_T_446, _T_448) @[dec_tlu_ctl.scala 1781:70] + node _T_450 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1782:41] + node _T_451 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1782:66] + node _T_452 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1782:93] + node _T_453 = not(_T_452) @[dec_tlu_ctl.scala 1782:73] + node _T_454 = and(_T_451, _T_453) @[dec_tlu_ctl.scala 1782:70] + node _T_455 = cat(_T_450, _T_454) @[Cat.scala 29:58] + node _T_456 = cat(_T_445, _T_449) @[Cat.scala 29:58] node _T_457 = cat(_T_456, _T_455) @[Cat.scala 29:58] - node _T_458 = cat(_T_457, _T_454) @[Cat.scala 29:58] - node _T_459 = cat(_T_458, _T_451) @[Cat.scala 29:58] - node _T_460 = cat(_T_400, _T_404) @[Cat.scala 29:58] - node _T_461 = cat(_T_395, _T_399) @[Cat.scala 29:58] - node _T_462 = cat(_T_461, _T_460) @[Cat.scala 29:58] - node _T_463 = cat(_T_390, _T_394) @[Cat.scala 29:58] - node _T_464 = cat(_T_385, _T_389) @[Cat.scala 29:58] - node _T_465 = cat(_T_464, _T_463) @[Cat.scala 29:58] - node _T_466 = cat(_T_465, _T_462) @[Cat.scala 29:58] - node _T_467 = cat(_T_380, _T_384) @[Cat.scala 29:58] - node _T_468 = cat(_T_375, _T_379) @[Cat.scala 29:58] - node _T_469 = cat(_T_468, _T_467) @[Cat.scala 29:58] - node _T_470 = cat(_T_370, _T_374) @[Cat.scala 29:58] - node _T_471 = cat(_T_365, _T_369) @[Cat.scala 29:58] + node _T_458 = cat(_T_440, _T_444) @[Cat.scala 29:58] + node _T_459 = cat(_T_435, _T_439) @[Cat.scala 29:58] + node _T_460 = cat(_T_459, _T_458) @[Cat.scala 29:58] + node _T_461 = cat(_T_460, _T_457) @[Cat.scala 29:58] + node _T_462 = cat(_T_430, _T_434) @[Cat.scala 29:58] + node _T_463 = cat(_T_425, _T_429) @[Cat.scala 29:58] + node _T_464 = cat(_T_463, _T_462) @[Cat.scala 29:58] + node _T_465 = cat(_T_420, _T_424) @[Cat.scala 29:58] + node _T_466 = cat(_T_415, _T_419) @[Cat.scala 29:58] + node _T_467 = cat(_T_466, _T_465) @[Cat.scala 29:58] + node _T_468 = cat(_T_467, _T_464) @[Cat.scala 29:58] + node _T_469 = cat(_T_468, _T_461) @[Cat.scala 29:58] + node _T_470 = cat(_T_410, _T_414) @[Cat.scala 29:58] + node _T_471 = cat(_T_405, _T_409) @[Cat.scala 29:58] node _T_472 = cat(_T_471, _T_470) @[Cat.scala 29:58] - node _T_473 = cat(_T_472, _T_469) @[Cat.scala 29:58] - node _T_474 = cat(_T_473, _T_466) @[Cat.scala 29:58] - node mrac_in = cat(_T_474, _T_459) @[Cat.scala 29:58] - node _T_475 = bits(wr_mrac_r, 0, 0) @[dec_tlu_ctl.scala 1785:38] + node _T_473 = cat(_T_400, _T_404) @[Cat.scala 29:58] + node _T_474 = cat(_T_395, _T_399) @[Cat.scala 29:58] + node _T_475 = cat(_T_474, _T_473) @[Cat.scala 29:58] + node _T_476 = cat(_T_475, _T_472) @[Cat.scala 29:58] + node _T_477 = cat(_T_390, _T_394) @[Cat.scala 29:58] + node _T_478 = cat(_T_385, _T_389) @[Cat.scala 29:58] + node _T_479 = cat(_T_478, _T_477) @[Cat.scala 29:58] + node _T_480 = cat(_T_380, _T_384) @[Cat.scala 29:58] + node _T_481 = cat(_T_375, _T_379) @[Cat.scala 29:58] + node _T_482 = cat(_T_481, _T_480) @[Cat.scala 29:58] + node _T_483 = cat(_T_482, _T_479) @[Cat.scala 29:58] + node _T_484 = cat(_T_483, _T_476) @[Cat.scala 29:58] + node mrac_in = cat(_T_484, _T_469) @[Cat.scala 29:58] + node _T_485 = bits(wr_mrac_r, 0, 0) @[dec_tlu_ctl.scala 1785:38] inst rvclkhdr_10 of rvclkhdr_730 @[lib.scala 368:23] rvclkhdr_10.clock <= clock rvclkhdr_10.reset <= reset rvclkhdr_10.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_10.io.en <= _T_475 @[lib.scala 371:17] + rvclkhdr_10.io.en <= _T_485 @[lib.scala 371:17] rvclkhdr_10.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg mrac : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] mrac <= mrac_in @[lib.scala 374:16] io.dec_tlu_mrac_ff <= mrac @[dec_tlu_ctl.scala 1787:21] - node _T_476 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1795:62] - node _T_477 = eq(_T_476, UInt<12>("h0bc0")) @[dec_tlu_ctl.scala 1795:69] - node wr_mdeau_r = and(io.dec_csr_wen_r_mod, _T_477) @[dec_tlu_ctl.scala 1795:40] - node _T_478 = not(wr_mdeau_r) @[dec_tlu_ctl.scala 1805:59] - node _T_479 = and(io.mdseac_locked_f, _T_478) @[dec_tlu_ctl.scala 1805:57] - node _T_480 = or(mdseac_en, _T_479) @[dec_tlu_ctl.scala 1805:35] - io.mdseac_locked_ns <= _T_480 @[dec_tlu_ctl.scala 1805:22] - node _T_481 = or(io.lsu_imprecise_error_store_any, io.lsu_imprecise_error_load_any) @[dec_tlu_ctl.scala 1807:49] - node _T_482 = not(io.nmi_int_detected_f) @[dec_tlu_ctl.scala 1807:86] - node _T_483 = and(_T_481, _T_482) @[dec_tlu_ctl.scala 1807:84] - node _T_484 = not(io.mdseac_locked_f) @[dec_tlu_ctl.scala 1807:111] - node _T_485 = and(_T_483, _T_484) @[dec_tlu_ctl.scala 1807:109] - mdseac_en <= _T_485 @[dec_tlu_ctl.scala 1807:12] - node _T_486 = bits(mdseac_en, 0, 0) @[dec_tlu_ctl.scala 1809:64] + node _T_486 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1795:62] + node _T_487 = eq(_T_486, UInt<12>("h0bc0")) @[dec_tlu_ctl.scala 1795:69] + node wr_mdeau_r = and(io.dec_csr_wen_r_mod, _T_487) @[dec_tlu_ctl.scala 1795:40] + node _T_488 = not(wr_mdeau_r) @[dec_tlu_ctl.scala 1805:59] + node _T_489 = and(io.mdseac_locked_f, _T_488) @[dec_tlu_ctl.scala 1805:57] + node _T_490 = or(mdseac_en, _T_489) @[dec_tlu_ctl.scala 1805:35] + io.mdseac_locked_ns <= _T_490 @[dec_tlu_ctl.scala 1805:22] + node _T_491 = or(io.lsu_imprecise_error_store_any, io.lsu_imprecise_error_load_any) @[dec_tlu_ctl.scala 1807:49] + node _T_492 = not(io.nmi_int_detected_f) @[dec_tlu_ctl.scala 1807:86] + node _T_493 = and(_T_491, _T_492) @[dec_tlu_ctl.scala 1807:84] + node _T_494 = not(io.mdseac_locked_f) @[dec_tlu_ctl.scala 1807:111] + node _T_495 = and(_T_493, _T_494) @[dec_tlu_ctl.scala 1807:109] + mdseac_en <= _T_495 @[dec_tlu_ctl.scala 1807:12] + node _T_496 = bits(mdseac_en, 0, 0) @[dec_tlu_ctl.scala 1809:64] inst rvclkhdr_11 of rvclkhdr_731 @[lib.scala 368:23] rvclkhdr_11.clock <= clock rvclkhdr_11.reset <= reset rvclkhdr_11.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_11.io.en <= _T_486 @[lib.scala 371:17] + rvclkhdr_11.io.en <= _T_496 @[lib.scala 371:17] rvclkhdr_11.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg mdseac : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] mdseac <= io.lsu_imprecise_error_addr_any @[lib.scala 374:16] - node _T_487 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1818:61] - node _T_488 = eq(_T_487, UInt<12>("h07c6")) @[dec_tlu_ctl.scala 1818:68] - node wr_mpmc_r = and(io.dec_csr_wen_r_mod, _T_488) @[dec_tlu_ctl.scala 1818:39] - node _T_489 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1822:51] - node _T_490 = and(wr_mpmc_r, _T_489) @[dec_tlu_ctl.scala 1822:30] - node _T_491 = not(io.internal_dbg_halt_mode_f2) @[dec_tlu_ctl.scala 1822:57] - node _T_492 = and(_T_490, _T_491) @[dec_tlu_ctl.scala 1822:55] - node _T_493 = not(io.ext_int_freeze_d1) @[dec_tlu_ctl.scala 1822:89] - node _T_494 = and(_T_492, _T_493) @[dec_tlu_ctl.scala 1822:87] - io.fw_halt_req <= _T_494 @[dec_tlu_ctl.scala 1822:17] + node _T_497 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1818:61] + node _T_498 = eq(_T_497, UInt<12>("h07c6")) @[dec_tlu_ctl.scala 1818:68] + node wr_mpmc_r = and(io.dec_csr_wen_r_mod, _T_498) @[dec_tlu_ctl.scala 1818:39] + node _T_499 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1822:51] + node _T_500 = and(wr_mpmc_r, _T_499) @[dec_tlu_ctl.scala 1822:30] + node _T_501 = not(io.internal_dbg_halt_mode_f2) @[dec_tlu_ctl.scala 1822:57] + node _T_502 = and(_T_500, _T_501) @[dec_tlu_ctl.scala 1822:55] + node _T_503 = not(io.ext_int_freeze_d1) @[dec_tlu_ctl.scala 1822:89] + node _T_504 = and(_T_502, _T_503) @[dec_tlu_ctl.scala 1822:87] + io.fw_halt_req <= _T_504 @[dec_tlu_ctl.scala 1822:17] wire fw_halted_ns : UInt<1> fw_halted_ns <= UInt<1>("h00") reg fw_halted : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1824:48] fw_halted <= fw_halted_ns @[dec_tlu_ctl.scala 1824:48] - node _T_495 = or(io.fw_halt_req, fw_halted) @[dec_tlu_ctl.scala 1825:34] - node _T_496 = not(set_mie_pmu_fw_halt) @[dec_tlu_ctl.scala 1825:49] - node _T_497 = and(_T_495, _T_496) @[dec_tlu_ctl.scala 1825:47] - fw_halted_ns <= _T_497 @[dec_tlu_ctl.scala 1825:15] - node _T_498 = bits(wr_mpmc_r, 0, 0) @[dec_tlu_ctl.scala 1826:29] - node _T_499 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1826:57] - node _T_500 = not(_T_499) @[dec_tlu_ctl.scala 1826:37] - node _T_501 = not(mpmc) @[dec_tlu_ctl.scala 1826:62] - node _T_502 = mux(_T_498, _T_500, _T_501) @[dec_tlu_ctl.scala 1826:18] - mpmc_b_ns <= _T_502 @[dec_tlu_ctl.scala 1826:12] - reg _T_503 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1828:44] - _T_503 <= mpmc_b_ns @[dec_tlu_ctl.scala 1828:44] - mpmc_b <= _T_503 @[dec_tlu_ctl.scala 1828:9] - node _T_504 = not(mpmc_b) @[dec_tlu_ctl.scala 1831:10] - mpmc <= _T_504 @[dec_tlu_ctl.scala 1831:7] - node _T_505 = bits(io.dec_csr_wrdata_r, 31, 27) @[dec_tlu_ctl.scala 1840:40] - node _T_506 = gt(_T_505, UInt<5>("h01a")) @[dec_tlu_ctl.scala 1840:48] - node _T_507 = bits(io.dec_csr_wrdata_r, 31, 27) @[dec_tlu_ctl.scala 1840:92] - node csr_sat = mux(_T_506, UInt<5>("h01a"), _T_507) @[dec_tlu_ctl.scala 1840:19] - node _T_508 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1842:63] - node _T_509 = eq(_T_508, UInt<12>("h07f0")) @[dec_tlu_ctl.scala 1842:70] - node wr_micect_r = and(io.dec_csr_wen_r_mod, _T_509) @[dec_tlu_ctl.scala 1842:41] - node _T_510 = cat(UInt<26>("h00"), io.ic_perr_r_d1) @[Cat.scala 29:58] - node _T_511 = add(micect, _T_510) @[dec_tlu_ctl.scala 1843:23] - node _T_512 = tail(_T_511, 1) @[dec_tlu_ctl.scala 1843:23] - micect_inc <= _T_512 @[dec_tlu_ctl.scala 1843:13] - node _T_513 = bits(wr_micect_r, 0, 0) @[dec_tlu_ctl.scala 1844:35] - node _T_514 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1844:75] - node _T_515 = cat(csr_sat, _T_514) @[Cat.scala 29:58] - node _T_516 = bits(micect, 31, 27) @[dec_tlu_ctl.scala 1844:95] - node _T_517 = cat(_T_516, micect_inc) @[Cat.scala 29:58] - node micect_ns = mux(_T_513, _T_515, _T_517) @[dec_tlu_ctl.scala 1844:22] - node _T_518 = or(wr_micect_r, io.ic_perr_r_d1) @[dec_tlu_ctl.scala 1846:42] - node _T_519 = bits(_T_518, 0, 0) @[dec_tlu_ctl.scala 1846:61] + node _T_505 = or(io.fw_halt_req, fw_halted) @[dec_tlu_ctl.scala 1825:34] + node _T_506 = not(set_mie_pmu_fw_halt) @[dec_tlu_ctl.scala 1825:49] + node _T_507 = and(_T_505, _T_506) @[dec_tlu_ctl.scala 1825:47] + fw_halted_ns <= _T_507 @[dec_tlu_ctl.scala 1825:15] + node _T_508 = bits(wr_mpmc_r, 0, 0) @[dec_tlu_ctl.scala 1826:29] + node _T_509 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1826:57] + node _T_510 = not(_T_509) @[dec_tlu_ctl.scala 1826:37] + node _T_511 = not(mpmc) @[dec_tlu_ctl.scala 1826:62] + node _T_512 = mux(_T_508, _T_510, _T_511) @[dec_tlu_ctl.scala 1826:18] + mpmc_b_ns <= _T_512 @[dec_tlu_ctl.scala 1826:12] + reg _T_513 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1828:44] + _T_513 <= mpmc_b_ns @[dec_tlu_ctl.scala 1828:44] + mpmc_b <= _T_513 @[dec_tlu_ctl.scala 1828:9] + node _T_514 = not(mpmc_b) @[dec_tlu_ctl.scala 1831:10] + mpmc <= _T_514 @[dec_tlu_ctl.scala 1831:7] + node _T_515 = bits(io.dec_csr_wrdata_r, 31, 27) @[dec_tlu_ctl.scala 1840:40] + node _T_516 = gt(_T_515, UInt<5>("h01a")) @[dec_tlu_ctl.scala 1840:48] + node _T_517 = bits(io.dec_csr_wrdata_r, 31, 27) @[dec_tlu_ctl.scala 1840:92] + node csr_sat = mux(_T_516, UInt<5>("h01a"), _T_517) @[dec_tlu_ctl.scala 1840:19] + node _T_518 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1842:63] + node _T_519 = eq(_T_518, UInt<12>("h07f0")) @[dec_tlu_ctl.scala 1842:70] + node wr_micect_r = and(io.dec_csr_wen_r_mod, _T_519) @[dec_tlu_ctl.scala 1842:41] + node _T_520 = cat(UInt<26>("h00"), io.ic_perr_r_d1) @[Cat.scala 29:58] + node _T_521 = add(micect, _T_520) @[dec_tlu_ctl.scala 1843:23] + node _T_522 = tail(_T_521, 1) @[dec_tlu_ctl.scala 1843:23] + micect_inc <= _T_522 @[dec_tlu_ctl.scala 1843:13] + node _T_523 = bits(wr_micect_r, 0, 0) @[dec_tlu_ctl.scala 1844:35] + node _T_524 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1844:75] + node _T_525 = cat(csr_sat, _T_524) @[Cat.scala 29:58] + node _T_526 = bits(micect, 31, 27) @[dec_tlu_ctl.scala 1844:95] + node _T_527 = cat(_T_526, micect_inc) @[Cat.scala 29:58] + node micect_ns = mux(_T_523, _T_525, _T_527) @[dec_tlu_ctl.scala 1844:22] + node _T_528 = or(wr_micect_r, io.ic_perr_r_d1) @[dec_tlu_ctl.scala 1846:42] + node _T_529 = bits(_T_528, 0, 0) @[dec_tlu_ctl.scala 1846:61] inst rvclkhdr_12 of rvclkhdr_732 @[lib.scala 368:23] rvclkhdr_12.clock <= clock rvclkhdr_12.reset <= reset rvclkhdr_12.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_12.io.en <= _T_519 @[lib.scala 371:17] + rvclkhdr_12.io.en <= _T_529 @[lib.scala 371:17] rvclkhdr_12.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_520 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_520 <= micect_ns @[lib.scala 374:16] - micect <= _T_520 @[dec_tlu_ctl.scala 1846:9] - node _T_521 = bits(micect, 31, 27) @[dec_tlu_ctl.scala 1848:48] - node _T_522 = dshl(UInt<32>("h0ffffffff"), _T_521) @[dec_tlu_ctl.scala 1848:39] - node _T_523 = bits(micect, 26, 0) @[dec_tlu_ctl.scala 1848:79] - node _T_524 = cat(UInt<5>("h00"), _T_523) @[Cat.scala 29:58] - node _T_525 = and(_T_522, _T_524) @[dec_tlu_ctl.scala 1848:57] - node _T_526 = orr(_T_525) @[dec_tlu_ctl.scala 1848:88] - mice_ce_req <= _T_526 @[dec_tlu_ctl.scala 1848:14] - node _T_527 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1857:69] - node _T_528 = eq(_T_527, UInt<12>("h07f1")) @[dec_tlu_ctl.scala 1857:76] - node wr_miccmect_r = and(io.dec_csr_wen_r_mod, _T_528) @[dec_tlu_ctl.scala 1857:47] - node _T_529 = bits(miccmect, 26, 0) @[dec_tlu_ctl.scala 1858:26] - node _T_530 = or(io.iccm_sbecc_r_d1, io.iccm_dma_sb_error) @[dec_tlu_ctl.scala 1858:70] - node _T_531 = cat(UInt<26>("h00"), _T_530) @[Cat.scala 29:58] - node _T_532 = add(_T_529, _T_531) @[dec_tlu_ctl.scala 1858:33] - node _T_533 = tail(_T_532, 1) @[dec_tlu_ctl.scala 1858:33] - miccmect_inc <= _T_533 @[dec_tlu_ctl.scala 1858:15] - node _T_534 = bits(wr_miccmect_r, 0, 0) @[dec_tlu_ctl.scala 1859:45] - node _T_535 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1859:85] - node _T_536 = cat(csr_sat, _T_535) @[Cat.scala 29:58] - node _T_537 = bits(miccmect, 31, 27) @[dec_tlu_ctl.scala 1859:107] - node _T_538 = cat(_T_537, miccmect_inc) @[Cat.scala 29:58] - node miccmect_ns = mux(_T_534, _T_536, _T_538) @[dec_tlu_ctl.scala 1859:30] - node _T_539 = or(wr_miccmect_r, io.iccm_sbecc_r_d1) @[dec_tlu_ctl.scala 1861:48] - node _T_540 = or(_T_539, io.iccm_dma_sb_error) @[dec_tlu_ctl.scala 1861:69] - node _T_541 = bits(_T_540, 0, 0) @[dec_tlu_ctl.scala 1861:93] + reg _T_530 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_530 <= micect_ns @[lib.scala 374:16] + micect <= _T_530 @[dec_tlu_ctl.scala 1846:9] + node _T_531 = bits(micect, 31, 27) @[dec_tlu_ctl.scala 1848:48] + node _T_532 = dshl(UInt<32>("h0ffffffff"), _T_531) @[dec_tlu_ctl.scala 1848:39] + node _T_533 = bits(micect, 26, 0) @[dec_tlu_ctl.scala 1848:79] + node _T_534 = cat(UInt<5>("h00"), _T_533) @[Cat.scala 29:58] + node _T_535 = and(_T_532, _T_534) @[dec_tlu_ctl.scala 1848:57] + node _T_536 = orr(_T_535) @[dec_tlu_ctl.scala 1848:88] + mice_ce_req <= _T_536 @[dec_tlu_ctl.scala 1848:14] + node _T_537 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1857:69] + node _T_538 = eq(_T_537, UInt<12>("h07f1")) @[dec_tlu_ctl.scala 1857:76] + node wr_miccmect_r = and(io.dec_csr_wen_r_mod, _T_538) @[dec_tlu_ctl.scala 1857:47] + node _T_539 = bits(miccmect, 26, 0) @[dec_tlu_ctl.scala 1858:26] + node _T_540 = or(io.iccm_sbecc_r_d1, io.iccm_dma_sb_error) @[dec_tlu_ctl.scala 1858:70] + node _T_541 = cat(UInt<26>("h00"), _T_540) @[Cat.scala 29:58] + node _T_542 = add(_T_539, _T_541) @[dec_tlu_ctl.scala 1858:33] + node _T_543 = tail(_T_542, 1) @[dec_tlu_ctl.scala 1858:33] + miccmect_inc <= _T_543 @[dec_tlu_ctl.scala 1858:15] + node _T_544 = bits(wr_miccmect_r, 0, 0) @[dec_tlu_ctl.scala 1859:45] + node _T_545 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1859:85] + node _T_546 = cat(csr_sat, _T_545) @[Cat.scala 29:58] + node _T_547 = bits(miccmect, 31, 27) @[dec_tlu_ctl.scala 1859:107] + node _T_548 = cat(_T_547, miccmect_inc) @[Cat.scala 29:58] + node miccmect_ns = mux(_T_544, _T_546, _T_548) @[dec_tlu_ctl.scala 1859:30] + node _T_549 = or(wr_miccmect_r, io.iccm_sbecc_r_d1) @[dec_tlu_ctl.scala 1861:48] + node _T_550 = or(_T_549, io.iccm_dma_sb_error) @[dec_tlu_ctl.scala 1861:69] + node _T_551 = bits(_T_550, 0, 0) @[dec_tlu_ctl.scala 1861:93] inst rvclkhdr_13 of rvclkhdr_733 @[lib.scala 368:23] rvclkhdr_13.clock <= clock rvclkhdr_13.reset <= reset rvclkhdr_13.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_13.io.en <= _T_541 @[lib.scala 371:17] + rvclkhdr_13.io.en <= _T_551 @[lib.scala 371:17] rvclkhdr_13.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_542 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_542 <= miccmect_ns @[lib.scala 374:16] - miccmect <= _T_542 @[dec_tlu_ctl.scala 1861:11] - node _T_543 = bits(miccmect, 31, 27) @[dec_tlu_ctl.scala 1863:51] - node _T_544 = dshl(UInt<32>("h0ffffffff"), _T_543) @[dec_tlu_ctl.scala 1863:40] - node _T_545 = bits(miccmect, 26, 0) @[dec_tlu_ctl.scala 1863:84] - node _T_546 = cat(UInt<5>("h00"), _T_545) @[Cat.scala 29:58] - node _T_547 = and(_T_544, _T_546) @[dec_tlu_ctl.scala 1863:60] - node _T_548 = orr(_T_547) @[dec_tlu_ctl.scala 1863:93] - miccme_ce_req <= _T_548 @[dec_tlu_ctl.scala 1863:15] - node _T_549 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1872:69] - node _T_550 = eq(_T_549, UInt<12>("h07f2")) @[dec_tlu_ctl.scala 1872:76] - node wr_mdccmect_r = and(io.dec_csr_wen_r_mod, _T_550) @[dec_tlu_ctl.scala 1872:47] - node _T_551 = bits(mdccmect, 26, 0) @[dec_tlu_ctl.scala 1873:26] - node _T_552 = cat(UInt<26>("h00"), io.lsu_single_ecc_error_r_d1) @[Cat.scala 29:58] - node _T_553 = add(_T_551, _T_552) @[dec_tlu_ctl.scala 1873:33] - node _T_554 = tail(_T_553, 1) @[dec_tlu_ctl.scala 1873:33] - mdccmect_inc <= _T_554 @[dec_tlu_ctl.scala 1873:15] - node _T_555 = bits(wr_mdccmect_r, 0, 0) @[dec_tlu_ctl.scala 1874:45] - node _T_556 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1874:85] - node _T_557 = cat(csr_sat, _T_556) @[Cat.scala 29:58] - node _T_558 = bits(mdccmect, 31, 27) @[dec_tlu_ctl.scala 1874:107] - node _T_559 = cat(_T_558, mdccmect_inc) @[Cat.scala 29:58] - node mdccmect_ns = mux(_T_555, _T_557, _T_559) @[dec_tlu_ctl.scala 1874:30] - node _T_560 = or(wr_mdccmect_r, io.lsu_single_ecc_error_r_d1) @[dec_tlu_ctl.scala 1876:49] - node _T_561 = bits(_T_560, 0, 0) @[dec_tlu_ctl.scala 1876:81] + reg _T_552 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_552 <= miccmect_ns @[lib.scala 374:16] + miccmect <= _T_552 @[dec_tlu_ctl.scala 1861:11] + node _T_553 = bits(miccmect, 31, 27) @[dec_tlu_ctl.scala 1863:51] + node _T_554 = dshl(UInt<32>("h0ffffffff"), _T_553) @[dec_tlu_ctl.scala 1863:40] + node _T_555 = bits(miccmect, 26, 0) @[dec_tlu_ctl.scala 1863:84] + node _T_556 = cat(UInt<5>("h00"), _T_555) @[Cat.scala 29:58] + node _T_557 = and(_T_554, _T_556) @[dec_tlu_ctl.scala 1863:60] + node _T_558 = orr(_T_557) @[dec_tlu_ctl.scala 1863:93] + miccme_ce_req <= _T_558 @[dec_tlu_ctl.scala 1863:15] + node _T_559 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1872:69] + node _T_560 = eq(_T_559, UInt<12>("h07f2")) @[dec_tlu_ctl.scala 1872:76] + node wr_mdccmect_r = and(io.dec_csr_wen_r_mod, _T_560) @[dec_tlu_ctl.scala 1872:47] + node _T_561 = bits(mdccmect, 26, 0) @[dec_tlu_ctl.scala 1873:26] + node _T_562 = cat(UInt<26>("h00"), io.lsu_single_ecc_error_r_d1) @[Cat.scala 29:58] + node _T_563 = add(_T_561, _T_562) @[dec_tlu_ctl.scala 1873:33] + node _T_564 = tail(_T_563, 1) @[dec_tlu_ctl.scala 1873:33] + mdccmect_inc <= _T_564 @[dec_tlu_ctl.scala 1873:15] + node _T_565 = bits(wr_mdccmect_r, 0, 0) @[dec_tlu_ctl.scala 1874:45] + node _T_566 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1874:85] + node _T_567 = cat(csr_sat, _T_566) @[Cat.scala 29:58] + node _T_568 = bits(mdccmect, 31, 27) @[dec_tlu_ctl.scala 1874:107] + node _T_569 = cat(_T_568, mdccmect_inc) @[Cat.scala 29:58] + node mdccmect_ns = mux(_T_565, _T_567, _T_569) @[dec_tlu_ctl.scala 1874:30] + node _T_570 = or(wr_mdccmect_r, io.lsu_single_ecc_error_r_d1) @[dec_tlu_ctl.scala 1876:49] + node _T_571 = bits(_T_570, 0, 0) @[dec_tlu_ctl.scala 1876:81] inst rvclkhdr_14 of rvclkhdr_734 @[lib.scala 368:23] rvclkhdr_14.clock <= clock rvclkhdr_14.reset <= reset rvclkhdr_14.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_14.io.en <= _T_561 @[lib.scala 371:17] + rvclkhdr_14.io.en <= _T_571 @[lib.scala 371:17] rvclkhdr_14.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_562 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_562 <= mdccmect_ns @[lib.scala 374:16] - mdccmect <= _T_562 @[dec_tlu_ctl.scala 1876:11] - node _T_563 = bits(mdccmect, 31, 27) @[dec_tlu_ctl.scala 1878:52] - node _T_564 = dshl(UInt<32>("h0ffffffff"), _T_563) @[dec_tlu_ctl.scala 1878:41] - node _T_565 = bits(mdccmect, 26, 0) @[dec_tlu_ctl.scala 1878:85] - node _T_566 = cat(UInt<5>("h00"), _T_565) @[Cat.scala 29:58] - node _T_567 = and(_T_564, _T_566) @[dec_tlu_ctl.scala 1878:61] - node _T_568 = orr(_T_567) @[dec_tlu_ctl.scala 1878:94] - mdccme_ce_req <= _T_568 @[dec_tlu_ctl.scala 1878:16] - node _T_569 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1888:62] - node _T_570 = eq(_T_569, UInt<12>("h07ce")) @[dec_tlu_ctl.scala 1888:69] - node wr_mfdht_r = and(io.dec_csr_wen_r_mod, _T_570) @[dec_tlu_ctl.scala 1888:40] - node _T_571 = bits(wr_mfdht_r, 0, 0) @[dec_tlu_ctl.scala 1890:32] - node _T_572 = bits(io.dec_csr_wrdata_r, 5, 0) @[dec_tlu_ctl.scala 1890:59] - node mfdht_ns = mux(_T_571, _T_572, mfdht) @[dec_tlu_ctl.scala 1890:20] - reg _T_573 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1892:43] - _T_573 <= mfdht_ns @[dec_tlu_ctl.scala 1892:43] - mfdht <= _T_573 @[dec_tlu_ctl.scala 1892:8] - node _T_574 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1901:62] - node _T_575 = eq(_T_574, UInt<12>("h07cf")) @[dec_tlu_ctl.scala 1901:69] - node wr_mfdhs_r = and(io.dec_csr_wen_r_mod, _T_575) @[dec_tlu_ctl.scala 1901:40] - node _T_576 = bits(wr_mfdhs_r, 0, 0) @[dec_tlu_ctl.scala 1903:32] - node _T_577 = bits(io.dec_csr_wrdata_r, 1, 0) @[dec_tlu_ctl.scala 1903:60] - node _T_578 = not(io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 1904:43] - node _T_579 = and(io.dbg_tlu_halted, _T_578) @[dec_tlu_ctl.scala 1904:41] - node _T_580 = bits(_T_579, 0, 0) @[dec_tlu_ctl.scala 1904:65] - node _T_581 = not(io.lsu_idle_any_f) @[dec_tlu_ctl.scala 1904:78] - node _T_582 = not(io.ifu_miss_state_idle_f) @[dec_tlu_ctl.scala 1904:98] - node _T_583 = cat(_T_581, _T_582) @[Cat.scala 29:58] - node _T_584 = mux(_T_580, _T_583, mfdhs) @[dec_tlu_ctl.scala 1904:21] - node mfdhs_ns = mux(_T_576, _T_577, _T_584) @[dec_tlu_ctl.scala 1903:20] - node _T_585 = or(wr_mfdhs_r, io.dbg_tlu_halted) @[dec_tlu_ctl.scala 1906:71] - node _T_586 = bits(_T_585, 0, 0) @[dec_tlu_ctl.scala 1906:92] - reg _T_587 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_586 : @[Reg.scala 28:19] - _T_587 <= mfdhs_ns @[Reg.scala 28:23] + reg _T_572 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_572 <= mdccmect_ns @[lib.scala 374:16] + mdccmect <= _T_572 @[dec_tlu_ctl.scala 1876:11] + node _T_573 = bits(mdccmect, 31, 27) @[dec_tlu_ctl.scala 1878:52] + node _T_574 = dshl(UInt<32>("h0ffffffff"), _T_573) @[dec_tlu_ctl.scala 1878:41] + node _T_575 = bits(mdccmect, 26, 0) @[dec_tlu_ctl.scala 1878:85] + node _T_576 = cat(UInt<5>("h00"), _T_575) @[Cat.scala 29:58] + node _T_577 = and(_T_574, _T_576) @[dec_tlu_ctl.scala 1878:61] + node _T_578 = orr(_T_577) @[dec_tlu_ctl.scala 1878:94] + mdccme_ce_req <= _T_578 @[dec_tlu_ctl.scala 1878:16] + node _T_579 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1888:62] + node _T_580 = eq(_T_579, UInt<12>("h07ce")) @[dec_tlu_ctl.scala 1888:69] + node wr_mfdht_r = and(io.dec_csr_wen_r_mod, _T_580) @[dec_tlu_ctl.scala 1888:40] + node _T_581 = bits(wr_mfdht_r, 0, 0) @[dec_tlu_ctl.scala 1890:32] + node _T_582 = bits(io.dec_csr_wrdata_r, 5, 0) @[dec_tlu_ctl.scala 1890:59] + node mfdht_ns = mux(_T_581, _T_582, mfdht) @[dec_tlu_ctl.scala 1890:20] + reg _T_583 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1892:43] + _T_583 <= mfdht_ns @[dec_tlu_ctl.scala 1892:43] + mfdht <= _T_583 @[dec_tlu_ctl.scala 1892:8] + node _T_584 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1901:62] + node _T_585 = eq(_T_584, UInt<12>("h07cf")) @[dec_tlu_ctl.scala 1901:69] + node wr_mfdhs_r = and(io.dec_csr_wen_r_mod, _T_585) @[dec_tlu_ctl.scala 1901:40] + node _T_586 = bits(wr_mfdhs_r, 0, 0) @[dec_tlu_ctl.scala 1903:32] + node _T_587 = bits(io.dec_csr_wrdata_r, 1, 0) @[dec_tlu_ctl.scala 1903:60] + node _T_588 = not(io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 1904:43] + node _T_589 = and(io.dbg_tlu_halted, _T_588) @[dec_tlu_ctl.scala 1904:41] + node _T_590 = bits(_T_589, 0, 0) @[dec_tlu_ctl.scala 1904:65] + node _T_591 = not(io.lsu_idle_any_f) @[dec_tlu_ctl.scala 1904:78] + node _T_592 = not(io.ifu_miss_state_idle_f) @[dec_tlu_ctl.scala 1904:98] + node _T_593 = cat(_T_591, _T_592) @[Cat.scala 29:58] + node _T_594 = mux(_T_590, _T_593, mfdhs) @[dec_tlu_ctl.scala 1904:21] + node mfdhs_ns = mux(_T_586, _T_587, _T_594) @[dec_tlu_ctl.scala 1903:20] + node _T_595 = or(wr_mfdhs_r, io.dbg_tlu_halted) @[dec_tlu_ctl.scala 1906:71] + node _T_596 = bits(_T_595, 0, 0) @[dec_tlu_ctl.scala 1906:92] + reg _T_597 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_596 : @[Reg.scala 28:19] + _T_597 <= mfdhs_ns @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mfdhs <= _T_587 @[dec_tlu_ctl.scala 1906:8] - node _T_588 = bits(io.debug_halt_req_f, 0, 0) @[dec_tlu_ctl.scala 1908:47] - node _T_589 = add(force_halt_ctr_f, UInt<32>("h01")) @[dec_tlu_ctl.scala 1908:74] - node _T_590 = tail(_T_589, 1) @[dec_tlu_ctl.scala 1908:74] - node _T_591 = bits(io.dbg_tlu_halted_f, 0, 0) @[dec_tlu_ctl.scala 1909:48] - node _T_592 = mux(_T_591, UInt<32>("h00"), force_halt_ctr_f) @[dec_tlu_ctl.scala 1909:27] - node force_halt_ctr = mux(_T_588, _T_590, _T_592) @[dec_tlu_ctl.scala 1908:26] - node _T_593 = bits(mfdht, 0, 0) @[dec_tlu_ctl.scala 1911:81] - reg _T_594 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_593 : @[Reg.scala 28:19] - _T_594 <= force_halt_ctr @[Reg.scala 28:23] + mfdhs <= _T_597 @[dec_tlu_ctl.scala 1906:8] + node _T_598 = bits(io.debug_halt_req_f, 0, 0) @[dec_tlu_ctl.scala 1908:47] + node _T_599 = add(force_halt_ctr_f, UInt<32>("h01")) @[dec_tlu_ctl.scala 1908:74] + node _T_600 = tail(_T_599, 1) @[dec_tlu_ctl.scala 1908:74] + node _T_601 = bits(io.dbg_tlu_halted_f, 0, 0) @[dec_tlu_ctl.scala 1909:48] + node _T_602 = mux(_T_601, UInt<32>("h00"), force_halt_ctr_f) @[dec_tlu_ctl.scala 1909:27] + node force_halt_ctr = mux(_T_598, _T_600, _T_602) @[dec_tlu_ctl.scala 1908:26] + node _T_603 = bits(mfdht, 0, 0) @[dec_tlu_ctl.scala 1911:81] + reg _T_604 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_603 : @[Reg.scala 28:19] + _T_604 <= force_halt_ctr @[Reg.scala 28:23] skip @[Reg.scala 28:19] - force_halt_ctr_f <= _T_594 @[dec_tlu_ctl.scala 1911:19] - node _T_595 = bits(mfdht, 0, 0) @[dec_tlu_ctl.scala 1913:24] - node _T_596 = bits(mfdht, 5, 1) @[dec_tlu_ctl.scala 1913:79] - node _T_597 = dshl(UInt<32>("h0ffffffff"), _T_596) @[dec_tlu_ctl.scala 1913:71] - node _T_598 = and(force_halt_ctr_f, _T_597) @[dec_tlu_ctl.scala 1913:48] - node _T_599 = orr(_T_598) @[dec_tlu_ctl.scala 1913:87] - node _T_600 = and(_T_595, _T_599) @[dec_tlu_ctl.scala 1913:28] - io.force_halt <= _T_600 @[dec_tlu_ctl.scala 1913:16] - node _T_601 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1921:62] - node _T_602 = eq(_T_601, UInt<12>("h0bc8")) @[dec_tlu_ctl.scala 1921:69] - node wr_meivt_r = and(io.dec_csr_wen_r_mod, _T_602) @[dec_tlu_ctl.scala 1921:40] - node _T_603 = bits(io.dec_csr_wrdata_r, 31, 10) @[dec_tlu_ctl.scala 1923:40] - node _T_604 = bits(wr_meivt_r, 0, 0) @[dec_tlu_ctl.scala 1923:59] + force_halt_ctr_f <= _T_604 @[dec_tlu_ctl.scala 1911:19] + node _T_605 = bits(mfdht, 0, 0) @[dec_tlu_ctl.scala 1913:24] + node _T_606 = bits(mfdht, 5, 1) @[dec_tlu_ctl.scala 1913:79] + node _T_607 = dshl(UInt<32>("h0ffffffff"), _T_606) @[dec_tlu_ctl.scala 1913:71] + node _T_608 = and(force_halt_ctr_f, _T_607) @[dec_tlu_ctl.scala 1913:48] + node _T_609 = orr(_T_608) @[dec_tlu_ctl.scala 1913:87] + node _T_610 = and(_T_605, _T_609) @[dec_tlu_ctl.scala 1913:28] + io.force_halt <= _T_610 @[dec_tlu_ctl.scala 1913:16] + node _T_611 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1921:62] + node _T_612 = eq(_T_611, UInt<12>("h0bc8")) @[dec_tlu_ctl.scala 1921:69] + node wr_meivt_r = and(io.dec_csr_wen_r_mod, _T_612) @[dec_tlu_ctl.scala 1921:40] + node _T_613 = bits(io.dec_csr_wrdata_r, 31, 10) @[dec_tlu_ctl.scala 1923:40] + node _T_614 = bits(wr_meivt_r, 0, 0) @[dec_tlu_ctl.scala 1923:59] inst rvclkhdr_15 of rvclkhdr_735 @[lib.scala 368:23] rvclkhdr_15.clock <= clock rvclkhdr_15.reset <= reset rvclkhdr_15.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_15.io.en <= _T_604 @[lib.scala 371:17] + rvclkhdr_15.io.en <= _T_614 @[lib.scala 371:17] rvclkhdr_15.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg meivt : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - meivt <= _T_603 @[lib.scala 374:16] - node _T_605 = bits(wr_meicpct_r, 0, 0) @[dec_tlu_ctl.scala 1935:49] + meivt <= _T_613 @[lib.scala 374:16] + node _T_615 = bits(wr_meicpct_r, 0, 0) @[dec_tlu_ctl.scala 1935:49] inst rvclkhdr_16 of rvclkhdr_736 @[lib.scala 368:23] rvclkhdr_16.clock <= clock rvclkhdr_16.reset <= reset rvclkhdr_16.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_16.io.en <= _T_605 @[lib.scala 371:17] + rvclkhdr_16.io.en <= _T_615 @[lib.scala 371:17] rvclkhdr_16.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg meihap : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] meihap <= io.pic_claimid @[lib.scala 374:16] - node _T_606 = cat(meivt, meihap) @[Cat.scala 29:58] - io.dec_tlu_meihap <= _T_606 @[dec_tlu_ctl.scala 1936:20] - node _T_607 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1945:65] - node _T_608 = eq(_T_607, UInt<12>("h0bcc")) @[dec_tlu_ctl.scala 1945:72] - node wr_meicurpl_r = and(io.dec_csr_wen_r_mod, _T_608) @[dec_tlu_ctl.scala 1945:43] - node _T_609 = bits(wr_meicurpl_r, 0, 0) @[dec_tlu_ctl.scala 1946:38] - node _T_610 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1946:65] - node meicurpl_ns = mux(_T_609, _T_610, meicurpl) @[dec_tlu_ctl.scala 1946:23] - reg _T_611 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1948:46] - _T_611 <= meicurpl_ns @[dec_tlu_ctl.scala 1948:46] - meicurpl <= _T_611 @[dec_tlu_ctl.scala 1948:11] + node _T_616 = cat(meivt, meihap) @[Cat.scala 29:58] + io.dec_tlu_meihap <= _T_616 @[dec_tlu_ctl.scala 1936:20] + node _T_617 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1945:65] + node _T_618 = eq(_T_617, UInt<12>("h0bcc")) @[dec_tlu_ctl.scala 1945:72] + node wr_meicurpl_r = and(io.dec_csr_wen_r_mod, _T_618) @[dec_tlu_ctl.scala 1945:43] + node _T_619 = bits(wr_meicurpl_r, 0, 0) @[dec_tlu_ctl.scala 1946:38] + node _T_620 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1946:65] + node meicurpl_ns = mux(_T_619, _T_620, meicurpl) @[dec_tlu_ctl.scala 1946:23] + reg _T_621 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1948:46] + _T_621 <= meicurpl_ns @[dec_tlu_ctl.scala 1948:46] + meicurpl <= _T_621 @[dec_tlu_ctl.scala 1948:11] io.dec_tlu_meicurpl <= meicurpl @[dec_tlu_ctl.scala 1950:22] - node _T_612 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1960:66] - node _T_613 = eq(_T_612, UInt<12>("h0bcb")) @[dec_tlu_ctl.scala 1960:73] - node _T_614 = and(io.dec_csr_wen_r_mod, _T_613) @[dec_tlu_ctl.scala 1960:44] - node wr_meicidpl_r = or(_T_614, io.take_ext_int_start) @[dec_tlu_ctl.scala 1960:88] - node _T_615 = bits(wr_meicpct_r, 0, 0) @[dec_tlu_ctl.scala 1962:37] - node _T_616 = bits(wr_meicidpl_r, 0, 0) @[dec_tlu_ctl.scala 1963:38] - node _T_617 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1963:65] - node _T_618 = mux(_T_616, _T_617, meicidpl) @[dec_tlu_ctl.scala 1963:23] - node meicidpl_ns = mux(_T_615, io.pic_pl, _T_618) @[dec_tlu_ctl.scala 1962:23] - reg _T_619 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1965:44] - _T_619 <= meicidpl_ns @[dec_tlu_ctl.scala 1965:44] - meicidpl <= _T_619 @[dec_tlu_ctl.scala 1965:11] - node _T_620 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1972:62] - node _T_621 = eq(_T_620, UInt<12>("h0bca")) @[dec_tlu_ctl.scala 1972:69] - node _T_622 = and(io.dec_csr_wen_r_mod, _T_621) @[dec_tlu_ctl.scala 1972:40] - node _T_623 = or(_T_622, io.take_ext_int_start) @[dec_tlu_ctl.scala 1972:83] - wr_meicpct_r <= _T_623 @[dec_tlu_ctl.scala 1972:15] - node _T_624 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1981:62] - node _T_625 = eq(_T_624, UInt<12>("h0bc9")) @[dec_tlu_ctl.scala 1981:69] - node wr_meipt_r = and(io.dec_csr_wen_r_mod, _T_625) @[dec_tlu_ctl.scala 1981:40] - node _T_626 = bits(wr_meipt_r, 0, 0) @[dec_tlu_ctl.scala 1982:32] - node _T_627 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1982:59] - node meipt_ns = mux(_T_626, _T_627, meipt) @[dec_tlu_ctl.scala 1982:20] - reg _T_628 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1984:43] - _T_628 <= meipt_ns @[dec_tlu_ctl.scala 1984:43] - meipt <= _T_628 @[dec_tlu_ctl.scala 1984:8] + node _T_622 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1960:66] + node _T_623 = eq(_T_622, UInt<12>("h0bcb")) @[dec_tlu_ctl.scala 1960:73] + node _T_624 = and(io.dec_csr_wen_r_mod, _T_623) @[dec_tlu_ctl.scala 1960:44] + node wr_meicidpl_r = or(_T_624, io.take_ext_int_start) @[dec_tlu_ctl.scala 1960:88] + node _T_625 = bits(wr_meicpct_r, 0, 0) @[dec_tlu_ctl.scala 1962:37] + node _T_626 = bits(wr_meicidpl_r, 0, 0) @[dec_tlu_ctl.scala 1963:38] + node _T_627 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1963:65] + node _T_628 = mux(_T_626, _T_627, meicidpl) @[dec_tlu_ctl.scala 1963:23] + node meicidpl_ns = mux(_T_625, io.pic_pl, _T_628) @[dec_tlu_ctl.scala 1962:23] + reg _T_629 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1965:44] + _T_629 <= meicidpl_ns @[dec_tlu_ctl.scala 1965:44] + meicidpl <= _T_629 @[dec_tlu_ctl.scala 1965:11] + node _T_630 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1972:62] + node _T_631 = eq(_T_630, UInt<12>("h0bca")) @[dec_tlu_ctl.scala 1972:69] + node _T_632 = and(io.dec_csr_wen_r_mod, _T_631) @[dec_tlu_ctl.scala 1972:40] + node _T_633 = or(_T_632, io.take_ext_int_start) @[dec_tlu_ctl.scala 1972:83] + wr_meicpct_r <= _T_633 @[dec_tlu_ctl.scala 1972:15] + node _T_634 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1981:62] + node _T_635 = eq(_T_634, UInt<12>("h0bc9")) @[dec_tlu_ctl.scala 1981:69] + node wr_meipt_r = and(io.dec_csr_wen_r_mod, _T_635) @[dec_tlu_ctl.scala 1981:40] + node _T_636 = bits(wr_meipt_r, 0, 0) @[dec_tlu_ctl.scala 1982:32] + node _T_637 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1982:59] + node meipt_ns = mux(_T_636, _T_637, meipt) @[dec_tlu_ctl.scala 1982:20] + reg _T_638 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1984:43] + _T_638 <= meipt_ns @[dec_tlu_ctl.scala 1984:43] + meipt <= _T_638 @[dec_tlu_ctl.scala 1984:8] io.dec_tlu_meipt <= meipt @[dec_tlu_ctl.scala 1986:19] - node _T_629 = and(io.trigger_hit_r_d1, io.dcsr_single_step_done_f) @[dec_tlu_ctl.scala 2012:89] - node trigger_hit_for_dscr_cause_r_d1 = or(io.trigger_hit_dmode_r_d1, _T_629) @[dec_tlu_ctl.scala 2012:66] - node _T_630 = not(io.ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 2015:31] - node _T_631 = and(io.dcsr_single_step_done_f, _T_630) @[dec_tlu_ctl.scala 2015:29] - node _T_632 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2015:63] - node _T_633 = and(_T_631, _T_632) @[dec_tlu_ctl.scala 2015:61] - node _T_634 = not(io.debug_halt_req) @[dec_tlu_ctl.scala 2015:98] - node _T_635 = and(_T_633, _T_634) @[dec_tlu_ctl.scala 2015:96] - node _T_636 = bits(_T_635, 0, 0) @[dec_tlu_ctl.scala 2015:118] - node _T_637 = not(io.ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 2016:48] - node _T_638 = and(io.debug_halt_req, _T_637) @[dec_tlu_ctl.scala 2016:46] - node _T_639 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2016:80] - node _T_640 = and(_T_638, _T_639) @[dec_tlu_ctl.scala 2016:78] - node _T_641 = bits(_T_640, 0, 0) @[dec_tlu_ctl.scala 2016:114] - node _T_642 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2017:77] - node _T_643 = and(io.ebreak_to_debug_mode_r_d1, _T_642) @[dec_tlu_ctl.scala 2017:75] - node _T_644 = bits(_T_643, 0, 0) @[dec_tlu_ctl.scala 2017:111] - node _T_645 = bits(trigger_hit_for_dscr_cause_r_d1, 0, 0) @[dec_tlu_ctl.scala 2018:108] - node _T_646 = mux(_T_636, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_647 = mux(_T_641, UInt<3>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_648 = mux(_T_644, UInt<3>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_649 = mux(_T_645, UInt<3>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_650 = or(_T_646, _T_647) @[Mux.scala 27:72] - node _T_651 = or(_T_650, _T_648) @[Mux.scala 27:72] - node _T_652 = or(_T_651, _T_649) @[Mux.scala 27:72] + node _T_639 = and(io.trigger_hit_r_d1, io.dcsr_single_step_done_f) @[dec_tlu_ctl.scala 2012:89] + node trigger_hit_for_dscr_cause_r_d1 = or(io.trigger_hit_dmode_r_d1, _T_639) @[dec_tlu_ctl.scala 2012:66] + node _T_640 = not(io.ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 2015:31] + node _T_641 = and(io.dcsr_single_step_done_f, _T_640) @[dec_tlu_ctl.scala 2015:29] + node _T_642 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2015:63] + node _T_643 = and(_T_641, _T_642) @[dec_tlu_ctl.scala 2015:61] + node _T_644 = not(io.debug_halt_req) @[dec_tlu_ctl.scala 2015:98] + node _T_645 = and(_T_643, _T_644) @[dec_tlu_ctl.scala 2015:96] + node _T_646 = bits(_T_645, 0, 0) @[dec_tlu_ctl.scala 2015:118] + node _T_647 = not(io.ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 2016:48] + node _T_648 = and(io.debug_halt_req, _T_647) @[dec_tlu_ctl.scala 2016:46] + node _T_649 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2016:80] + node _T_650 = and(_T_648, _T_649) @[dec_tlu_ctl.scala 2016:78] + node _T_651 = bits(_T_650, 0, 0) @[dec_tlu_ctl.scala 2016:114] + node _T_652 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2017:77] + node _T_653 = and(io.ebreak_to_debug_mode_r_d1, _T_652) @[dec_tlu_ctl.scala 2017:75] + node _T_654 = bits(_T_653, 0, 0) @[dec_tlu_ctl.scala 2017:111] + node _T_655 = bits(trigger_hit_for_dscr_cause_r_d1, 0, 0) @[dec_tlu_ctl.scala 2018:108] + node _T_656 = mux(_T_646, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_657 = mux(_T_651, UInt<3>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_658 = mux(_T_654, UInt<3>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_659 = mux(_T_655, UInt<3>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_660 = or(_T_656, _T_657) @[Mux.scala 27:72] + node _T_661 = or(_T_660, _T_658) @[Mux.scala 27:72] + node _T_662 = or(_T_661, _T_659) @[Mux.scala 27:72] wire dcsr_cause : UInt<3> @[Mux.scala 27:72] - dcsr_cause <= _T_652 @[Mux.scala 27:72] - node _T_653 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2020:46] - node _T_654 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2020:91] - node _T_655 = eq(_T_654, UInt<12>("h07b0")) @[dec_tlu_ctl.scala 2020:98] - node wr_dcsr_r = and(_T_653, _T_655) @[dec_tlu_ctl.scala 2020:69] - node _T_656 = bits(io.dcsr, 8, 6) @[dec_tlu_ctl.scala 2026:69] - node _T_657 = eq(_T_656, UInt<3>("h03")) @[dec_tlu_ctl.scala 2026:75] - node dcsr_cause_upgradeable = and(io.internal_dbg_halt_mode_f, _T_657) @[dec_tlu_ctl.scala 2026:59] - node _T_658 = not(io.dbg_tlu_halted) @[dec_tlu_ctl.scala 2027:59] - node _T_659 = or(_T_658, dcsr_cause_upgradeable) @[dec_tlu_ctl.scala 2027:78] - node enter_debug_halt_req_le = and(io.enter_debug_halt_req, _T_659) @[dec_tlu_ctl.scala 2027:56] + dcsr_cause <= _T_662 @[Mux.scala 27:72] + node _T_663 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2020:46] + node _T_664 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2020:91] + node _T_665 = eq(_T_664, UInt<12>("h07b0")) @[dec_tlu_ctl.scala 2020:98] + node wr_dcsr_r = and(_T_663, _T_665) @[dec_tlu_ctl.scala 2020:69] + node _T_666 = bits(io.dcsr, 8, 6) @[dec_tlu_ctl.scala 2026:69] + node _T_667 = eq(_T_666, UInt<3>("h03")) @[dec_tlu_ctl.scala 2026:75] + node dcsr_cause_upgradeable = and(io.internal_dbg_halt_mode_f, _T_667) @[dec_tlu_ctl.scala 2026:59] + node _T_668 = not(io.dbg_tlu_halted) @[dec_tlu_ctl.scala 2027:59] + node _T_669 = or(_T_668, dcsr_cause_upgradeable) @[dec_tlu_ctl.scala 2027:78] + node enter_debug_halt_req_le = and(io.enter_debug_halt_req, _T_669) @[dec_tlu_ctl.scala 2027:56] node nmi_in_debug_mode = and(io.nmi_int_detected_f, io.internal_dbg_halt_mode_f) @[dec_tlu_ctl.scala 2029:48] - node _T_660 = bits(enter_debug_halt_req_le, 0, 0) @[dec_tlu_ctl.scala 2030:44] - node _T_661 = bits(io.dcsr, 15, 9) @[dec_tlu_ctl.scala 2030:64] - node _T_662 = bits(io.dcsr, 5, 2) @[dec_tlu_ctl.scala 2030:91] - node _T_663 = cat(_T_662, UInt<2>("h03")) @[Cat.scala 29:58] - node _T_664 = cat(_T_661, dcsr_cause) @[Cat.scala 29:58] - node _T_665 = cat(_T_664, _T_663) @[Cat.scala 29:58] - node _T_666 = bits(wr_dcsr_r, 0, 0) @[dec_tlu_ctl.scala 2031:18] - node _T_667 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 2031:49] - node _T_668 = bits(io.dec_csr_wrdata_r, 11, 10) @[dec_tlu_ctl.scala 2031:84] - node _T_669 = bits(io.dcsr, 8, 6) @[dec_tlu_ctl.scala 2031:110] - node _T_670 = bits(io.dcsr, 3, 3) @[dec_tlu_ctl.scala 2031:154] - node _T_671 = or(nmi_in_debug_mode, _T_670) @[dec_tlu_ctl.scala 2031:145] - node _T_672 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 2031:178] + node _T_670 = bits(enter_debug_halt_req_le, 0, 0) @[dec_tlu_ctl.scala 2030:44] + node _T_671 = bits(io.dcsr, 15, 9) @[dec_tlu_ctl.scala 2030:64] + node _T_672 = bits(io.dcsr, 5, 2) @[dec_tlu_ctl.scala 2030:91] node _T_673 = cat(_T_672, UInt<2>("h03")) @[Cat.scala 29:58] - node _T_674 = cat(UInt<2>("h00"), _T_671) @[Cat.scala 29:58] + node _T_674 = cat(_T_671, dcsr_cause) @[Cat.scala 29:58] node _T_675 = cat(_T_674, _T_673) @[Cat.scala 29:58] - node _T_676 = cat(UInt<1>("h00"), _T_669) @[Cat.scala 29:58] - node _T_677 = cat(_T_667, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_678 = cat(_T_677, _T_668) @[Cat.scala 29:58] - node _T_679 = cat(_T_678, _T_676) @[Cat.scala 29:58] - node _T_680 = cat(_T_679, _T_675) @[Cat.scala 29:58] - node _T_681 = bits(io.dcsr, 15, 4) @[dec_tlu_ctl.scala 2031:211] - node _T_682 = bits(io.dcsr, 2, 2) @[dec_tlu_ctl.scala 2031:245] + node _T_676 = bits(wr_dcsr_r, 0, 0) @[dec_tlu_ctl.scala 2031:18] + node _T_677 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 2031:49] + node _T_678 = bits(io.dec_csr_wrdata_r, 11, 10) @[dec_tlu_ctl.scala 2031:84] + node _T_679 = bits(io.dcsr, 8, 6) @[dec_tlu_ctl.scala 2031:110] + node _T_680 = bits(io.dcsr, 3, 3) @[dec_tlu_ctl.scala 2031:154] + node _T_681 = or(nmi_in_debug_mode, _T_680) @[dec_tlu_ctl.scala 2031:145] + node _T_682 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 2031:178] node _T_683 = cat(_T_682, UInt<2>("h03")) @[Cat.scala 29:58] - node _T_684 = cat(_T_681, nmi_in_debug_mode) @[Cat.scala 29:58] + node _T_684 = cat(UInt<2>("h00"), _T_681) @[Cat.scala 29:58] node _T_685 = cat(_T_684, _T_683) @[Cat.scala 29:58] - node _T_686 = mux(_T_666, _T_680, _T_685) @[dec_tlu_ctl.scala 2031:7] - node dcsr_ns = mux(_T_660, _T_665, _T_686) @[dec_tlu_ctl.scala 2030:19] - node _T_687 = or(enter_debug_halt_req_le, wr_dcsr_r) @[dec_tlu_ctl.scala 2033:54] - node _T_688 = or(_T_687, io.internal_dbg_halt_mode) @[dec_tlu_ctl.scala 2033:66] - node _T_689 = or(_T_688, io.take_nmi) @[dec_tlu_ctl.scala 2033:94] - node _T_690 = bits(_T_689, 0, 0) @[dec_tlu_ctl.scala 2033:109] + node _T_686 = cat(UInt<1>("h00"), _T_679) @[Cat.scala 29:58] + node _T_687 = cat(_T_677, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_688 = cat(_T_687, _T_678) @[Cat.scala 29:58] + node _T_689 = cat(_T_688, _T_686) @[Cat.scala 29:58] + node _T_690 = cat(_T_689, _T_685) @[Cat.scala 29:58] + node _T_691 = bits(io.dcsr, 15, 4) @[dec_tlu_ctl.scala 2031:211] + node _T_692 = bits(io.dcsr, 2, 2) @[dec_tlu_ctl.scala 2031:245] + node _T_693 = cat(_T_692, UInt<2>("h03")) @[Cat.scala 29:58] + node _T_694 = cat(_T_691, nmi_in_debug_mode) @[Cat.scala 29:58] + node _T_695 = cat(_T_694, _T_693) @[Cat.scala 29:58] + node _T_696 = mux(_T_676, _T_690, _T_695) @[dec_tlu_ctl.scala 2031:7] + node dcsr_ns = mux(_T_670, _T_675, _T_696) @[dec_tlu_ctl.scala 2030:19] + node _T_697 = or(enter_debug_halt_req_le, wr_dcsr_r) @[dec_tlu_ctl.scala 2033:54] + node _T_698 = or(_T_697, io.internal_dbg_halt_mode) @[dec_tlu_ctl.scala 2033:66] + node _T_699 = or(_T_698, io.take_nmi) @[dec_tlu_ctl.scala 2033:94] + node _T_700 = bits(_T_699, 0, 0) @[dec_tlu_ctl.scala 2033:109] inst rvclkhdr_17 of rvclkhdr_737 @[lib.scala 368:23] rvclkhdr_17.clock <= clock rvclkhdr_17.reset <= reset rvclkhdr_17.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_17.io.en <= _T_690 @[lib.scala 371:17] + rvclkhdr_17.io.en <= _T_700 @[lib.scala 371:17] rvclkhdr_17.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_691 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_691 <= dcsr_ns @[lib.scala 374:16] - io.dcsr <= _T_691 @[dec_tlu_ctl.scala 2033:10] - node _T_692 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2041:45] - node _T_693 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2041:90] - node _T_694 = eq(_T_693, UInt<12>("h07b1")) @[dec_tlu_ctl.scala 2041:97] - node wr_dpc_r = and(_T_692, _T_694) @[dec_tlu_ctl.scala 2041:68] - node _T_695 = not(io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2042:44] - node _T_696 = and(io.dbg_tlu_halted, _T_695) @[dec_tlu_ctl.scala 2042:42] - node _T_697 = not(io.request_debug_mode_done) @[dec_tlu_ctl.scala 2042:67] - node dpc_capture_npc = and(_T_696, _T_697) @[dec_tlu_ctl.scala 2042:65] - node _T_698 = not(io.request_debug_mode_r) @[dec_tlu_ctl.scala 2046:21] - node _T_699 = not(dpc_capture_npc) @[dec_tlu_ctl.scala 2046:39] - node _T_700 = and(_T_698, _T_699) @[dec_tlu_ctl.scala 2046:37] - node _T_701 = and(_T_700, wr_dpc_r) @[dec_tlu_ctl.scala 2046:56] - node _T_702 = bits(_T_701, 0, 0) @[dec_tlu_ctl.scala 2046:68] - node _T_703 = bits(io.dec_csr_wrdata_r, 31, 1) @[dec_tlu_ctl.scala 2046:97] - node _T_704 = bits(io.request_debug_mode_r, 0, 0) @[dec_tlu_ctl.scala 2047:68] - node _T_705 = not(io.request_debug_mode_r) @[dec_tlu_ctl.scala 2048:33] - node _T_706 = and(_T_705, dpc_capture_npc) @[dec_tlu_ctl.scala 2048:49] - node _T_707 = bits(_T_706, 0, 0) @[dec_tlu_ctl.scala 2048:68] - node _T_708 = mux(_T_702, _T_703, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_709 = mux(_T_704, pc_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_710 = mux(_T_707, io.npc_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_711 = or(_T_708, _T_709) @[Mux.scala 27:72] - node _T_712 = or(_T_711, _T_710) @[Mux.scala 27:72] + reg _T_701 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_701 <= dcsr_ns @[lib.scala 374:16] + io.dcsr <= _T_701 @[dec_tlu_ctl.scala 2033:10] + node _T_702 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2041:45] + node _T_703 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2041:90] + node _T_704 = eq(_T_703, UInt<12>("h07b1")) @[dec_tlu_ctl.scala 2041:97] + node wr_dpc_r = and(_T_702, _T_704) @[dec_tlu_ctl.scala 2041:68] + node _T_705 = not(io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2042:44] + node _T_706 = and(io.dbg_tlu_halted, _T_705) @[dec_tlu_ctl.scala 2042:42] + node _T_707 = not(io.request_debug_mode_done) @[dec_tlu_ctl.scala 2042:67] + node dpc_capture_npc = and(_T_706, _T_707) @[dec_tlu_ctl.scala 2042:65] + node _T_708 = not(io.request_debug_mode_r) @[dec_tlu_ctl.scala 2046:21] + node _T_709 = not(dpc_capture_npc) @[dec_tlu_ctl.scala 2046:39] + node _T_710 = and(_T_708, _T_709) @[dec_tlu_ctl.scala 2046:37] + node _T_711 = and(_T_710, wr_dpc_r) @[dec_tlu_ctl.scala 2046:56] + node _T_712 = bits(_T_711, 0, 0) @[dec_tlu_ctl.scala 2046:68] + node _T_713 = bits(io.dec_csr_wrdata_r, 31, 1) @[dec_tlu_ctl.scala 2046:97] + node _T_714 = bits(io.request_debug_mode_r, 0, 0) @[dec_tlu_ctl.scala 2047:68] + node _T_715 = not(io.request_debug_mode_r) @[dec_tlu_ctl.scala 2048:33] + node _T_716 = and(_T_715, dpc_capture_npc) @[dec_tlu_ctl.scala 2048:49] + node _T_717 = bits(_T_716, 0, 0) @[dec_tlu_ctl.scala 2048:68] + node _T_718 = mux(_T_712, _T_713, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_719 = mux(_T_714, pc_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_720 = mux(_T_717, io.npc_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_721 = or(_T_718, _T_719) @[Mux.scala 27:72] + node _T_722 = or(_T_721, _T_720) @[Mux.scala 27:72] wire dpc_ns : UInt<31> @[Mux.scala 27:72] - dpc_ns <= _T_712 @[Mux.scala 27:72] - node _T_713 = or(wr_dpc_r, io.request_debug_mode_r) @[dec_tlu_ctl.scala 2050:36] - node _T_714 = or(_T_713, dpc_capture_npc) @[dec_tlu_ctl.scala 2050:53] - node _T_715 = bits(_T_714, 0, 0) @[dec_tlu_ctl.scala 2050:72] + dpc_ns <= _T_722 @[Mux.scala 27:72] + node _T_723 = or(wr_dpc_r, io.request_debug_mode_r) @[dec_tlu_ctl.scala 2050:36] + node _T_724 = or(_T_723, dpc_capture_npc) @[dec_tlu_ctl.scala 2050:53] + node _T_725 = bits(_T_724, 0, 0) @[dec_tlu_ctl.scala 2050:72] inst rvclkhdr_18 of rvclkhdr_738 @[lib.scala 368:23] rvclkhdr_18.clock <= clock rvclkhdr_18.reset <= reset rvclkhdr_18.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_18.io.en <= _T_715 @[lib.scala 371:17] + rvclkhdr_18.io.en <= _T_725 @[lib.scala 371:17] rvclkhdr_18.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_716 : UInt, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_716 <= dpc_ns @[lib.scala 374:16] - io.dpc <= _T_716 @[dec_tlu_ctl.scala 2050:9] - node _T_717 = bits(io.dec_csr_wrdata_r, 24, 24) @[dec_tlu_ctl.scala 2064:43] - node _T_718 = bits(io.dec_csr_wrdata_r, 21, 20) @[dec_tlu_ctl.scala 2064:68] - node _T_719 = bits(io.dec_csr_wrdata_r, 16, 3) @[dec_tlu_ctl.scala 2064:96] - node _T_720 = cat(_T_717, _T_718) @[Cat.scala 29:58] - node dicawics_ns = cat(_T_720, _T_719) @[Cat.scala 29:58] - node _T_721 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2065:50] - node _T_722 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2065:95] - node _T_723 = eq(_T_722, UInt<12>("h07c8")) @[dec_tlu_ctl.scala 2065:102] - node wr_dicawics_r = and(_T_721, _T_723) @[dec_tlu_ctl.scala 2065:73] - node _T_724 = bits(wr_dicawics_r, 0, 0) @[dec_tlu_ctl.scala 2067:50] + reg _T_726 : UInt, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_726 <= dpc_ns @[lib.scala 374:16] + io.dpc <= _T_726 @[dec_tlu_ctl.scala 2050:9] + node _T_727 = bits(io.dec_csr_wrdata_r, 24, 24) @[dec_tlu_ctl.scala 2064:43] + node _T_728 = bits(io.dec_csr_wrdata_r, 21, 20) @[dec_tlu_ctl.scala 2064:68] + node _T_729 = bits(io.dec_csr_wrdata_r, 16, 3) @[dec_tlu_ctl.scala 2064:96] + node _T_730 = cat(_T_727, _T_728) @[Cat.scala 29:58] + node dicawics_ns = cat(_T_730, _T_729) @[Cat.scala 29:58] + node _T_731 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2065:50] + node _T_732 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2065:95] + node _T_733 = eq(_T_732, UInt<12>("h07c8")) @[dec_tlu_ctl.scala 2065:102] + node wr_dicawics_r = and(_T_731, _T_733) @[dec_tlu_ctl.scala 2065:73] + node _T_734 = bits(wr_dicawics_r, 0, 0) @[dec_tlu_ctl.scala 2067:50] inst rvclkhdr_19 of rvclkhdr_739 @[lib.scala 368:23] rvclkhdr_19.clock <= clock rvclkhdr_19.reset <= reset rvclkhdr_19.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_19.io.en <= _T_724 @[lib.scala 371:17] + rvclkhdr_19.io.en <= _T_734 @[lib.scala 371:17] rvclkhdr_19.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg dicawics : UInt, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] dicawics <= dicawics_ns @[lib.scala 374:16] - node _T_725 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2083:48] - node _T_726 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2083:93] - node _T_727 = eq(_T_726, UInt<12>("h07c9")) @[dec_tlu_ctl.scala 2083:100] - node wr_dicad0_r = and(_T_725, _T_727) @[dec_tlu_ctl.scala 2083:71] - node _T_728 = bits(wr_dicad0_r, 0, 0) @[dec_tlu_ctl.scala 2084:34] - node dicad0_ns = mux(_T_728, io.dec_csr_wrdata_r, io.ifu_ic_debug_rd_data) @[dec_tlu_ctl.scala 2084:21] - node _T_729 = or(wr_dicad0_r, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2086:46] - node _T_730 = bits(_T_729, 0, 0) @[dec_tlu_ctl.scala 2086:79] + node _T_735 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2083:48] + node _T_736 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2083:93] + node _T_737 = eq(_T_736, UInt<12>("h07c9")) @[dec_tlu_ctl.scala 2083:100] + node wr_dicad0_r = and(_T_735, _T_737) @[dec_tlu_ctl.scala 2083:71] + node _T_738 = bits(wr_dicad0_r, 0, 0) @[dec_tlu_ctl.scala 2084:34] + node dicad0_ns = mux(_T_738, io.dec_csr_wrdata_r, io.ifu_ic_debug_rd_data) @[dec_tlu_ctl.scala 2084:21] + node _T_739 = or(wr_dicad0_r, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2086:46] + node _T_740 = bits(_T_739, 0, 0) @[dec_tlu_ctl.scala 2086:79] inst rvclkhdr_20 of rvclkhdr_740 @[lib.scala 368:23] rvclkhdr_20.clock <= clock rvclkhdr_20.reset <= reset rvclkhdr_20.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_20.io.en <= _T_730 @[lib.scala 371:17] + rvclkhdr_20.io.en <= _T_740 @[lib.scala 371:17] rvclkhdr_20.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg dicad0 : UInt, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] dicad0 <= dicad0_ns @[lib.scala 374:16] - node _T_731 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2096:49] - node _T_732 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2096:94] - node _T_733 = eq(_T_732, UInt<12>("h07cc")) @[dec_tlu_ctl.scala 2096:101] - node wr_dicad0h_r = and(_T_731, _T_733) @[dec_tlu_ctl.scala 2096:72] - node _T_734 = bits(wr_dicad0h_r, 0, 0) @[dec_tlu_ctl.scala 2098:36] - node _T_735 = bits(io.ifu_ic_debug_rd_data, 63, 32) @[dec_tlu_ctl.scala 2098:88] - node dicad0h_ns = mux(_T_734, io.dec_csr_wrdata_r, _T_735) @[dec_tlu_ctl.scala 2098:22] - node _T_736 = or(wr_dicad0h_r, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2100:48] - node _T_737 = bits(_T_736, 0, 0) @[dec_tlu_ctl.scala 2100:81] + node _T_741 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2096:49] + node _T_742 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2096:94] + node _T_743 = eq(_T_742, UInt<12>("h07cc")) @[dec_tlu_ctl.scala 2096:101] + node wr_dicad0h_r = and(_T_741, _T_743) @[dec_tlu_ctl.scala 2096:72] + node _T_744 = bits(wr_dicad0h_r, 0, 0) @[dec_tlu_ctl.scala 2098:36] + node _T_745 = bits(io.ifu_ic_debug_rd_data, 63, 32) @[dec_tlu_ctl.scala 2098:88] + node dicad0h_ns = mux(_T_744, io.dec_csr_wrdata_r, _T_745) @[dec_tlu_ctl.scala 2098:22] + node _T_746 = or(wr_dicad0h_r, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2100:48] + node _T_747 = bits(_T_746, 0, 0) @[dec_tlu_ctl.scala 2100:81] inst rvclkhdr_21 of rvclkhdr_741 @[lib.scala 368:23] rvclkhdr_21.clock <= clock rvclkhdr_21.reset <= reset rvclkhdr_21.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_21.io.en <= _T_737 @[lib.scala 371:17] + rvclkhdr_21.io.en <= _T_747 @[lib.scala 371:17] rvclkhdr_21.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg dicad0h : UInt, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] dicad0h <= dicad0h_ns @[lib.scala 374:16] - wire _T_738 : UInt<7> - _T_738 <= UInt<1>("h00") - node _T_739 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2108:48] - node _T_740 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2108:93] - node _T_741 = eq(_T_740, UInt<12>("h07ca")) @[dec_tlu_ctl.scala 2108:100] - node _T_742 = and(_T_739, _T_741) @[dec_tlu_ctl.scala 2108:71] - node _T_743 = bits(_T_742, 0, 0) @[dec_tlu_ctl.scala 2110:34] - node _T_744 = bits(io.ifu_ic_debug_rd_data, 70, 64) @[dec_tlu_ctl.scala 2110:86] - node _T_745 = mux(_T_743, io.dec_csr_wrdata_r, _T_744) @[dec_tlu_ctl.scala 2110:21] - node _T_746 = or(_T_742, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2113:78] - node _T_747 = bits(_T_746, 0, 0) @[dec_tlu_ctl.scala 2113:111] - reg _T_748 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_747 : @[Reg.scala 28:19] - _T_748 <= _T_745 @[Reg.scala 28:23] + wire _T_748 : UInt<7> + _T_748 <= UInt<1>("h00") + node _T_749 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2108:48] + node _T_750 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2108:93] + node _T_751 = eq(_T_750, UInt<12>("h07ca")) @[dec_tlu_ctl.scala 2108:100] + node _T_752 = and(_T_749, _T_751) @[dec_tlu_ctl.scala 2108:71] + node _T_753 = bits(_T_752, 0, 0) @[dec_tlu_ctl.scala 2110:34] + node _T_754 = bits(io.ifu_ic_debug_rd_data, 70, 64) @[dec_tlu_ctl.scala 2110:86] + node _T_755 = mux(_T_753, io.dec_csr_wrdata_r, _T_754) @[dec_tlu_ctl.scala 2110:21] + node _T_756 = or(_T_752, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2113:78] + node _T_757 = bits(_T_756, 0, 0) @[dec_tlu_ctl.scala 2113:111] + reg _T_758 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_757 : @[Reg.scala 28:19] + _T_758 <= _T_755 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - _T_738 <= _T_748 @[dec_tlu_ctl.scala 2113:13] - node _T_749 = cat(UInt<25>("h00"), _T_738) @[Cat.scala 29:58] - dicad1 <= _T_749 @[dec_tlu_ctl.scala 2114:9] - node _T_750 = bits(dicad1, 6, 0) @[dec_tlu_ctl.scala 2136:69] - node _T_751 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2136:83] - node _T_752 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2136:97] - node _T_753 = cat(_T_750, _T_751) @[Cat.scala 29:58] - node _T_754 = cat(_T_753, _T_752) @[Cat.scala 29:58] - io.dec_tlu_ic_diag_pkt.icache_wrdata <= _T_754 @[dec_tlu_ctl.scala 2136:56] + _T_748 <= _T_758 @[dec_tlu_ctl.scala 2113:13] + node _T_759 = cat(UInt<25>("h00"), _T_748) @[Cat.scala 29:58] + dicad1 <= _T_759 @[dec_tlu_ctl.scala 2114:9] + node _T_760 = bits(dicad1, 6, 0) @[dec_tlu_ctl.scala 2136:69] + node _T_761 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2136:83] + node _T_762 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2136:97] + node _T_763 = cat(_T_760, _T_761) @[Cat.scala 29:58] + node _T_764 = cat(_T_763, _T_762) @[Cat.scala 29:58] + io.dec_tlu_ic_diag_pkt.icache_wrdata <= _T_764 @[dec_tlu_ctl.scala 2136:56] io.dec_tlu_ic_diag_pkt.icache_dicawics <= dicawics @[dec_tlu_ctl.scala 2139:41] - node _T_755 = and(io.allow_dbg_halt_csr_write, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 2141:52] - node _T_756 = and(_T_755, io.dec_i0_decode_d) @[dec_tlu_ctl.scala 2141:75] - node _T_757 = not(io.dec_csr_wen_unq_d) @[dec_tlu_ctl.scala 2141:98] - node _T_758 = and(_T_756, _T_757) @[dec_tlu_ctl.scala 2141:96] - node _T_759 = bits(io.dec_csr_rdaddr_d, 11, 0) @[dec_tlu_ctl.scala 2141:142] - node _T_760 = eq(_T_759, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2141:149] - node icache_rd_valid = and(_T_758, _T_760) @[dec_tlu_ctl.scala 2141:120] - node _T_761 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2142:52] - node _T_762 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2142:97] - node _T_763 = eq(_T_762, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2142:104] - node icache_wr_valid = and(_T_761, _T_763) @[dec_tlu_ctl.scala 2142:75] + node _T_765 = and(io.allow_dbg_halt_csr_write, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 2141:52] + node _T_766 = and(_T_765, io.dec_i0_decode_d) @[dec_tlu_ctl.scala 2141:75] + node _T_767 = not(io.dec_csr_wen_unq_d) @[dec_tlu_ctl.scala 2141:98] + node _T_768 = and(_T_766, _T_767) @[dec_tlu_ctl.scala 2141:96] + node _T_769 = bits(io.dec_csr_rdaddr_d, 11, 0) @[dec_tlu_ctl.scala 2141:142] + node _T_770 = eq(_T_769, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2141:149] + node icache_rd_valid = and(_T_768, _T_770) @[dec_tlu_ctl.scala 2141:120] + node _T_771 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2142:52] + node _T_772 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2142:97] + node _T_773 = eq(_T_772, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2142:104] + node icache_wr_valid = and(_T_771, _T_773) @[dec_tlu_ctl.scala 2142:75] reg icache_rd_valid_f : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2144:58] icache_rd_valid_f <= icache_rd_valid @[dec_tlu_ctl.scala 2144:58] reg icache_wr_valid_f : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2145:58] icache_wr_valid_f <= icache_wr_valid @[dec_tlu_ctl.scala 2145:58] io.dec_tlu_ic_diag_pkt.icache_rd_valid <= icache_rd_valid_f @[dec_tlu_ctl.scala 2147:41] io.dec_tlu_ic_diag_pkt.icache_wr_valid <= icache_wr_valid_f @[dec_tlu_ctl.scala 2148:41] - node _T_764 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2156:62] - node _T_765 = eq(_T_764, UInt<12>("h07a0")) @[dec_tlu_ctl.scala 2156:69] - node wr_mtsel_r = and(io.dec_csr_wen_r_mod, _T_765) @[dec_tlu_ctl.scala 2156:40] - node _T_766 = bits(wr_mtsel_r, 0, 0) @[dec_tlu_ctl.scala 2157:32] - node _T_767 = bits(io.dec_csr_wrdata_r, 1, 0) @[dec_tlu_ctl.scala 2157:59] - node mtsel_ns = mux(_T_766, _T_767, mtsel) @[dec_tlu_ctl.scala 2157:20] - reg _T_768 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2159:43] - _T_768 <= mtsel_ns @[dec_tlu_ctl.scala 2159:43] - mtsel <= _T_768 @[dec_tlu_ctl.scala 2159:8] - node _T_769 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2194:38] - node _T_770 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2194:64] - node _T_771 = not(_T_770) @[dec_tlu_ctl.scala 2194:44] - node tdata_load = and(_T_769, _T_771) @[dec_tlu_ctl.scala 2194:42] - node _T_772 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 2196:40] - node _T_773 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2196:66] - node _T_774 = not(_T_773) @[dec_tlu_ctl.scala 2196:46] - node tdata_opcode = and(_T_772, _T_774) @[dec_tlu_ctl.scala 2196:44] - node _T_775 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2198:41] - node _T_776 = and(_T_775, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2198:46] - node _T_777 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 2198:90] - node tdata_action = and(_T_776, _T_777) @[dec_tlu_ctl.scala 2198:69] - node _T_778 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2200:47] - node _T_779 = and(_T_778, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2200:52] - node _T_780 = bits(io.dec_csr_wrdata_r, 20, 19) @[dec_tlu_ctl.scala 2200:94] - node _T_781 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 2200:136] - node _T_782 = bits(io.dec_csr_wrdata_r, 7, 6) @[dec_tlu_ctl.scala 2201:43] - node _T_783 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 2201:83] - node _T_784 = cat(_T_783, tdata_load) @[Cat.scala 29:58] - node _T_785 = cat(_T_782, tdata_opcode) @[Cat.scala 29:58] - node _T_786 = cat(_T_785, _T_784) @[Cat.scala 29:58] - node _T_787 = cat(tdata_action, _T_781) @[Cat.scala 29:58] - node _T_788 = cat(_T_779, _T_780) @[Cat.scala 29:58] - node _T_789 = cat(_T_788, _T_787) @[Cat.scala 29:58] - node tdata_wrdata_r = cat(_T_789, _T_786) @[Cat.scala 29:58] - node _T_790 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2204:92] - node _T_791 = eq(_T_790, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2204:99] - node _T_792 = and(io.dec_csr_wen_r_mod, _T_791) @[dec_tlu_ctl.scala 2204:70] - node _T_793 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2204:121] - node _T_794 = and(_T_792, _T_793) @[dec_tlu_ctl.scala 2204:112] - node _T_795 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2204:154] - node _T_796 = not(_T_795) @[dec_tlu_ctl.scala 2204:138] - node _T_797 = or(_T_796, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2204:170] - node _T_798 = and(_T_794, _T_797) @[dec_tlu_ctl.scala 2204:135] - node _T_799 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2204:92] - node _T_800 = eq(_T_799, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2204:99] - node _T_801 = and(io.dec_csr_wen_r_mod, _T_800) @[dec_tlu_ctl.scala 2204:70] - node _T_802 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2204:121] - node _T_803 = and(_T_801, _T_802) @[dec_tlu_ctl.scala 2204:112] - node _T_804 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2204:154] - node _T_805 = not(_T_804) @[dec_tlu_ctl.scala 2204:138] - node _T_806 = or(_T_805, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2204:170] - node _T_807 = and(_T_803, _T_806) @[dec_tlu_ctl.scala 2204:135] - node _T_808 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2204:92] - node _T_809 = eq(_T_808, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2204:99] - node _T_810 = and(io.dec_csr_wen_r_mod, _T_809) @[dec_tlu_ctl.scala 2204:70] - node _T_811 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2204:121] - node _T_812 = and(_T_810, _T_811) @[dec_tlu_ctl.scala 2204:112] - node _T_813 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2204:154] - node _T_814 = not(_T_813) @[dec_tlu_ctl.scala 2204:138] - node _T_815 = or(_T_814, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2204:170] - node _T_816 = and(_T_812, _T_815) @[dec_tlu_ctl.scala 2204:135] - node _T_817 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2204:92] - node _T_818 = eq(_T_817, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2204:99] - node _T_819 = and(io.dec_csr_wen_r_mod, _T_818) @[dec_tlu_ctl.scala 2204:70] - node _T_820 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2204:121] - node _T_821 = and(_T_819, _T_820) @[dec_tlu_ctl.scala 2204:112] - node _T_822 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2204:154] - node _T_823 = not(_T_822) @[dec_tlu_ctl.scala 2204:138] - node _T_824 = or(_T_823, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2204:170] - node _T_825 = and(_T_821, _T_824) @[dec_tlu_ctl.scala 2204:135] + node _T_774 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2156:62] + node _T_775 = eq(_T_774, UInt<12>("h07a0")) @[dec_tlu_ctl.scala 2156:69] + node wr_mtsel_r = and(io.dec_csr_wen_r_mod, _T_775) @[dec_tlu_ctl.scala 2156:40] + node _T_776 = bits(wr_mtsel_r, 0, 0) @[dec_tlu_ctl.scala 2157:32] + node _T_777 = bits(io.dec_csr_wrdata_r, 1, 0) @[dec_tlu_ctl.scala 2157:59] + node mtsel_ns = mux(_T_776, _T_777, mtsel) @[dec_tlu_ctl.scala 2157:20] + reg _T_778 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2159:43] + _T_778 <= mtsel_ns @[dec_tlu_ctl.scala 2159:43] + mtsel <= _T_778 @[dec_tlu_ctl.scala 2159:8] + node _T_779 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2194:38] + node _T_780 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2194:64] + node _T_781 = not(_T_780) @[dec_tlu_ctl.scala 2194:44] + node tdata_load = and(_T_779, _T_781) @[dec_tlu_ctl.scala 2194:42] + node _T_782 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 2196:40] + node _T_783 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2196:66] + node _T_784 = not(_T_783) @[dec_tlu_ctl.scala 2196:46] + node tdata_opcode = and(_T_782, _T_784) @[dec_tlu_ctl.scala 2196:44] + node _T_785 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2198:41] + node _T_786 = and(_T_785, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2198:46] + node _T_787 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 2198:90] + node tdata_action = and(_T_786, _T_787) @[dec_tlu_ctl.scala 2198:69] + node _T_788 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2200:47] + node _T_789 = and(_T_788, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2200:52] + node _T_790 = bits(io.dec_csr_wrdata_r, 20, 19) @[dec_tlu_ctl.scala 2200:94] + node _T_791 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 2200:136] + node _T_792 = bits(io.dec_csr_wrdata_r, 7, 6) @[dec_tlu_ctl.scala 2201:43] + node _T_793 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 2201:83] + node _T_794 = cat(_T_793, tdata_load) @[Cat.scala 29:58] + node _T_795 = cat(_T_792, tdata_opcode) @[Cat.scala 29:58] + node _T_796 = cat(_T_795, _T_794) @[Cat.scala 29:58] + node _T_797 = cat(tdata_action, _T_791) @[Cat.scala 29:58] + node _T_798 = cat(_T_789, _T_790) @[Cat.scala 29:58] + node _T_799 = cat(_T_798, _T_797) @[Cat.scala 29:58] + node tdata_wrdata_r = cat(_T_799, _T_796) @[Cat.scala 29:58] + node _T_800 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2204:92] + node _T_801 = eq(_T_800, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2204:99] + node _T_802 = and(io.dec_csr_wen_r_mod, _T_801) @[dec_tlu_ctl.scala 2204:70] + node _T_803 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2204:121] + node _T_804 = and(_T_802, _T_803) @[dec_tlu_ctl.scala 2204:112] + node _T_805 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2204:154] + node _T_806 = not(_T_805) @[dec_tlu_ctl.scala 2204:138] + node _T_807 = or(_T_806, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2204:170] + node _T_808 = and(_T_804, _T_807) @[dec_tlu_ctl.scala 2204:135] + node _T_809 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2204:92] + node _T_810 = eq(_T_809, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2204:99] + node _T_811 = and(io.dec_csr_wen_r_mod, _T_810) @[dec_tlu_ctl.scala 2204:70] + node _T_812 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2204:121] + node _T_813 = and(_T_811, _T_812) @[dec_tlu_ctl.scala 2204:112] + node _T_814 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2204:154] + node _T_815 = not(_T_814) @[dec_tlu_ctl.scala 2204:138] + node _T_816 = or(_T_815, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2204:170] + node _T_817 = and(_T_813, _T_816) @[dec_tlu_ctl.scala 2204:135] + node _T_818 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2204:92] + node _T_819 = eq(_T_818, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2204:99] + node _T_820 = and(io.dec_csr_wen_r_mod, _T_819) @[dec_tlu_ctl.scala 2204:70] + node _T_821 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2204:121] + node _T_822 = and(_T_820, _T_821) @[dec_tlu_ctl.scala 2204:112] + node _T_823 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2204:154] + node _T_824 = not(_T_823) @[dec_tlu_ctl.scala 2204:138] + node _T_825 = or(_T_824, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2204:170] + node _T_826 = and(_T_822, _T_825) @[dec_tlu_ctl.scala 2204:135] + node _T_827 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2204:92] + node _T_828 = eq(_T_827, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2204:99] + node _T_829 = and(io.dec_csr_wen_r_mod, _T_828) @[dec_tlu_ctl.scala 2204:70] + node _T_830 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2204:121] + node _T_831 = and(_T_829, _T_830) @[dec_tlu_ctl.scala 2204:112] + node _T_832 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2204:154] + node _T_833 = not(_T_832) @[dec_tlu_ctl.scala 2204:138] + node _T_834 = or(_T_833, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2204:170] + node _T_835 = and(_T_831, _T_834) @[dec_tlu_ctl.scala 2204:135] wire wr_mtdata1_t_r : UInt<1>[4] @[dec_tlu_ctl.scala 2204:42] - wr_mtdata1_t_r[0] <= _T_798 @[dec_tlu_ctl.scala 2204:42] - wr_mtdata1_t_r[1] <= _T_807 @[dec_tlu_ctl.scala 2204:42] - wr_mtdata1_t_r[2] <= _T_816 @[dec_tlu_ctl.scala 2204:42] - wr_mtdata1_t_r[3] <= _T_825 @[dec_tlu_ctl.scala 2204:42] - node _T_826 = bits(wr_mtdata1_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2205:68] - node _T_827 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2205:111] - node _T_828 = bits(io.update_hit_bit_r, 0, 0) @[dec_tlu_ctl.scala 2205:135] - node _T_829 = bits(io.mtdata1_t[0], 8, 8) @[dec_tlu_ctl.scala 2205:156] - node _T_830 = or(_T_828, _T_829) @[dec_tlu_ctl.scala 2205:139] - node _T_831 = bits(io.mtdata1_t[0], 7, 0) @[dec_tlu_ctl.scala 2205:176] - node _T_832 = cat(_T_827, _T_830) @[Cat.scala 29:58] - node _T_833 = cat(_T_832, _T_831) @[Cat.scala 29:58] - node _T_834 = mux(_T_826, tdata_wrdata_r, _T_833) @[dec_tlu_ctl.scala 2205:49] - node _T_835 = bits(wr_mtdata1_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2205:68] - node _T_836 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2205:111] - node _T_837 = bits(io.update_hit_bit_r, 1, 1) @[dec_tlu_ctl.scala 2205:135] - node _T_838 = bits(io.mtdata1_t[1], 8, 8) @[dec_tlu_ctl.scala 2205:156] - node _T_839 = or(_T_837, _T_838) @[dec_tlu_ctl.scala 2205:139] - node _T_840 = bits(io.mtdata1_t[1], 7, 0) @[dec_tlu_ctl.scala 2205:176] - node _T_841 = cat(_T_836, _T_839) @[Cat.scala 29:58] - node _T_842 = cat(_T_841, _T_840) @[Cat.scala 29:58] - node _T_843 = mux(_T_835, tdata_wrdata_r, _T_842) @[dec_tlu_ctl.scala 2205:49] - node _T_844 = bits(wr_mtdata1_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2205:68] - node _T_845 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2205:111] - node _T_846 = bits(io.update_hit_bit_r, 2, 2) @[dec_tlu_ctl.scala 2205:135] - node _T_847 = bits(io.mtdata1_t[2], 8, 8) @[dec_tlu_ctl.scala 2205:156] - node _T_848 = or(_T_846, _T_847) @[dec_tlu_ctl.scala 2205:139] - node _T_849 = bits(io.mtdata1_t[2], 7, 0) @[dec_tlu_ctl.scala 2205:176] - node _T_850 = cat(_T_845, _T_848) @[Cat.scala 29:58] - node _T_851 = cat(_T_850, _T_849) @[Cat.scala 29:58] - node _T_852 = mux(_T_844, tdata_wrdata_r, _T_851) @[dec_tlu_ctl.scala 2205:49] - node _T_853 = bits(wr_mtdata1_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2205:68] - node _T_854 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2205:111] - node _T_855 = bits(io.update_hit_bit_r, 3, 3) @[dec_tlu_ctl.scala 2205:135] - node _T_856 = bits(io.mtdata1_t[3], 8, 8) @[dec_tlu_ctl.scala 2205:156] - node _T_857 = or(_T_855, _T_856) @[dec_tlu_ctl.scala 2205:139] - node _T_858 = bits(io.mtdata1_t[3], 7, 0) @[dec_tlu_ctl.scala 2205:176] - node _T_859 = cat(_T_854, _T_857) @[Cat.scala 29:58] - node _T_860 = cat(_T_859, _T_858) @[Cat.scala 29:58] - node _T_861 = mux(_T_853, tdata_wrdata_r, _T_860) @[dec_tlu_ctl.scala 2205:49] + wr_mtdata1_t_r[0] <= _T_808 @[dec_tlu_ctl.scala 2204:42] + wr_mtdata1_t_r[1] <= _T_817 @[dec_tlu_ctl.scala 2204:42] + wr_mtdata1_t_r[2] <= _T_826 @[dec_tlu_ctl.scala 2204:42] + wr_mtdata1_t_r[3] <= _T_835 @[dec_tlu_ctl.scala 2204:42] + node _T_836 = bits(wr_mtdata1_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2205:68] + node _T_837 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2205:111] + node _T_838 = bits(io.update_hit_bit_r, 0, 0) @[dec_tlu_ctl.scala 2205:135] + node _T_839 = bits(io.mtdata1_t[0], 8, 8) @[dec_tlu_ctl.scala 2205:156] + node _T_840 = or(_T_838, _T_839) @[dec_tlu_ctl.scala 2205:139] + node _T_841 = bits(io.mtdata1_t[0], 7, 0) @[dec_tlu_ctl.scala 2205:176] + node _T_842 = cat(_T_837, _T_840) @[Cat.scala 29:58] + node _T_843 = cat(_T_842, _T_841) @[Cat.scala 29:58] + node _T_844 = mux(_T_836, tdata_wrdata_r, _T_843) @[dec_tlu_ctl.scala 2205:49] + node _T_845 = bits(wr_mtdata1_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2205:68] + node _T_846 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2205:111] + node _T_847 = bits(io.update_hit_bit_r, 1, 1) @[dec_tlu_ctl.scala 2205:135] + node _T_848 = bits(io.mtdata1_t[1], 8, 8) @[dec_tlu_ctl.scala 2205:156] + node _T_849 = or(_T_847, _T_848) @[dec_tlu_ctl.scala 2205:139] + node _T_850 = bits(io.mtdata1_t[1], 7, 0) @[dec_tlu_ctl.scala 2205:176] + node _T_851 = cat(_T_846, _T_849) @[Cat.scala 29:58] + node _T_852 = cat(_T_851, _T_850) @[Cat.scala 29:58] + node _T_853 = mux(_T_845, tdata_wrdata_r, _T_852) @[dec_tlu_ctl.scala 2205:49] + node _T_854 = bits(wr_mtdata1_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2205:68] + node _T_855 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2205:111] + node _T_856 = bits(io.update_hit_bit_r, 2, 2) @[dec_tlu_ctl.scala 2205:135] + node _T_857 = bits(io.mtdata1_t[2], 8, 8) @[dec_tlu_ctl.scala 2205:156] + node _T_858 = or(_T_856, _T_857) @[dec_tlu_ctl.scala 2205:139] + node _T_859 = bits(io.mtdata1_t[2], 7, 0) @[dec_tlu_ctl.scala 2205:176] + node _T_860 = cat(_T_855, _T_858) @[Cat.scala 29:58] + node _T_861 = cat(_T_860, _T_859) @[Cat.scala 29:58] + node _T_862 = mux(_T_854, tdata_wrdata_r, _T_861) @[dec_tlu_ctl.scala 2205:49] + node _T_863 = bits(wr_mtdata1_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2205:68] + node _T_864 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2205:111] + node _T_865 = bits(io.update_hit_bit_r, 3, 3) @[dec_tlu_ctl.scala 2205:135] + node _T_866 = bits(io.mtdata1_t[3], 8, 8) @[dec_tlu_ctl.scala 2205:156] + node _T_867 = or(_T_865, _T_866) @[dec_tlu_ctl.scala 2205:139] + node _T_868 = bits(io.mtdata1_t[3], 7, 0) @[dec_tlu_ctl.scala 2205:176] + node _T_869 = cat(_T_864, _T_867) @[Cat.scala 29:58] + node _T_870 = cat(_T_869, _T_868) @[Cat.scala 29:58] + node _T_871 = mux(_T_863, tdata_wrdata_r, _T_870) @[dec_tlu_ctl.scala 2205:49] wire mtdata1_t_ns : UInt<10>[4] @[dec_tlu_ctl.scala 2205:40] - mtdata1_t_ns[0] <= _T_834 @[dec_tlu_ctl.scala 2205:40] - mtdata1_t_ns[1] <= _T_843 @[dec_tlu_ctl.scala 2205:40] - mtdata1_t_ns[2] <= _T_852 @[dec_tlu_ctl.scala 2205:40] - mtdata1_t_ns[3] <= _T_861 @[dec_tlu_ctl.scala 2205:40] - reg _T_862 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2207:74] - _T_862 <= mtdata1_t_ns[0] @[dec_tlu_ctl.scala 2207:74] - io.mtdata1_t[0] <= _T_862 @[dec_tlu_ctl.scala 2207:39] - reg _T_863 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2207:74] - _T_863 <= mtdata1_t_ns[1] @[dec_tlu_ctl.scala 2207:74] - io.mtdata1_t[1] <= _T_863 @[dec_tlu_ctl.scala 2207:39] - reg _T_864 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2207:74] - _T_864 <= mtdata1_t_ns[2] @[dec_tlu_ctl.scala 2207:74] - io.mtdata1_t[2] <= _T_864 @[dec_tlu_ctl.scala 2207:39] - reg _T_865 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2207:74] - _T_865 <= mtdata1_t_ns[3] @[dec_tlu_ctl.scala 2207:74] - io.mtdata1_t[3] <= _T_865 @[dec_tlu_ctl.scala 2207:39] - node _T_866 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2210:58] - node _T_867 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2210:104] - node _T_868 = bits(io.mtdata1_t[0], 8, 7) @[dec_tlu_ctl.scala 2210:142] - node _T_869 = bits(io.mtdata1_t[0], 6, 5) @[dec_tlu_ctl.scala 2210:174] - node _T_870 = bits(io.mtdata1_t[0], 4, 3) @[dec_tlu_ctl.scala 2210:206] - node _T_871 = bits(io.mtdata1_t[0], 2, 0) @[dec_tlu_ctl.scala 2210:238] - node _T_872 = cat(UInt<3>("h00"), _T_871) @[Cat.scala 29:58] - node _T_873 = cat(_T_869, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_874 = cat(_T_873, _T_870) @[Cat.scala 29:58] - node _T_875 = cat(_T_874, _T_872) @[Cat.scala 29:58] - node _T_876 = cat(_T_868, UInt<6>("h00")) @[Cat.scala 29:58] - node _T_877 = cat(UInt<4>("h02"), _T_867) @[Cat.scala 29:58] - node _T_878 = cat(_T_877, UInt<6>("h01f")) @[Cat.scala 29:58] - node _T_879 = cat(_T_878, _T_876) @[Cat.scala 29:58] - node _T_880 = cat(_T_879, _T_875) @[Cat.scala 29:58] - node _T_881 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2210:58] - node _T_882 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2210:104] - node _T_883 = bits(io.mtdata1_t[1], 8, 7) @[dec_tlu_ctl.scala 2210:142] - node _T_884 = bits(io.mtdata1_t[1], 6, 5) @[dec_tlu_ctl.scala 2210:174] - node _T_885 = bits(io.mtdata1_t[1], 4, 3) @[dec_tlu_ctl.scala 2210:206] - node _T_886 = bits(io.mtdata1_t[1], 2, 0) @[dec_tlu_ctl.scala 2210:238] - node _T_887 = cat(UInt<3>("h00"), _T_886) @[Cat.scala 29:58] - node _T_888 = cat(_T_884, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_889 = cat(_T_888, _T_885) @[Cat.scala 29:58] - node _T_890 = cat(_T_889, _T_887) @[Cat.scala 29:58] - node _T_891 = cat(_T_883, UInt<6>("h00")) @[Cat.scala 29:58] - node _T_892 = cat(UInt<4>("h02"), _T_882) @[Cat.scala 29:58] - node _T_893 = cat(_T_892, UInt<6>("h01f")) @[Cat.scala 29:58] - node _T_894 = cat(_T_893, _T_891) @[Cat.scala 29:58] - node _T_895 = cat(_T_894, _T_890) @[Cat.scala 29:58] - node _T_896 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2210:58] - node _T_897 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2210:104] - node _T_898 = bits(io.mtdata1_t[2], 8, 7) @[dec_tlu_ctl.scala 2210:142] - node _T_899 = bits(io.mtdata1_t[2], 6, 5) @[dec_tlu_ctl.scala 2210:174] - node _T_900 = bits(io.mtdata1_t[2], 4, 3) @[dec_tlu_ctl.scala 2210:206] - node _T_901 = bits(io.mtdata1_t[2], 2, 0) @[dec_tlu_ctl.scala 2210:238] - node _T_902 = cat(UInt<3>("h00"), _T_901) @[Cat.scala 29:58] - node _T_903 = cat(_T_899, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_904 = cat(_T_903, _T_900) @[Cat.scala 29:58] - node _T_905 = cat(_T_904, _T_902) @[Cat.scala 29:58] - node _T_906 = cat(_T_898, UInt<6>("h00")) @[Cat.scala 29:58] - node _T_907 = cat(UInt<4>("h02"), _T_897) @[Cat.scala 29:58] - node _T_908 = cat(_T_907, UInt<6>("h01f")) @[Cat.scala 29:58] - node _T_909 = cat(_T_908, _T_906) @[Cat.scala 29:58] - node _T_910 = cat(_T_909, _T_905) @[Cat.scala 29:58] - node _T_911 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2210:58] - node _T_912 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2210:104] - node _T_913 = bits(io.mtdata1_t[3], 8, 7) @[dec_tlu_ctl.scala 2210:142] - node _T_914 = bits(io.mtdata1_t[3], 6, 5) @[dec_tlu_ctl.scala 2210:174] - node _T_915 = bits(io.mtdata1_t[3], 4, 3) @[dec_tlu_ctl.scala 2210:206] - node _T_916 = bits(io.mtdata1_t[3], 2, 0) @[dec_tlu_ctl.scala 2210:238] - node _T_917 = cat(UInt<3>("h00"), _T_916) @[Cat.scala 29:58] - node _T_918 = cat(_T_914, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_919 = cat(_T_918, _T_915) @[Cat.scala 29:58] - node _T_920 = cat(_T_919, _T_917) @[Cat.scala 29:58] - node _T_921 = cat(_T_913, UInt<6>("h00")) @[Cat.scala 29:58] - node _T_922 = cat(UInt<4>("h02"), _T_912) @[Cat.scala 29:58] - node _T_923 = cat(_T_922, UInt<6>("h01f")) @[Cat.scala 29:58] - node _T_924 = cat(_T_923, _T_921) @[Cat.scala 29:58] - node _T_925 = cat(_T_924, _T_920) @[Cat.scala 29:58] - node _T_926 = mux(_T_866, _T_880, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_927 = mux(_T_881, _T_895, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_928 = mux(_T_896, _T_910, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_929 = mux(_T_911, _T_925, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_930 = or(_T_926, _T_927) @[Mux.scala 27:72] - node _T_931 = or(_T_930, _T_928) @[Mux.scala 27:72] - node _T_932 = or(_T_931, _T_929) @[Mux.scala 27:72] + mtdata1_t_ns[0] <= _T_844 @[dec_tlu_ctl.scala 2205:40] + mtdata1_t_ns[1] <= _T_853 @[dec_tlu_ctl.scala 2205:40] + mtdata1_t_ns[2] <= _T_862 @[dec_tlu_ctl.scala 2205:40] + mtdata1_t_ns[3] <= _T_871 @[dec_tlu_ctl.scala 2205:40] + reg _T_872 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2207:74] + _T_872 <= mtdata1_t_ns[0] @[dec_tlu_ctl.scala 2207:74] + io.mtdata1_t[0] <= _T_872 @[dec_tlu_ctl.scala 2207:39] + reg _T_873 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2207:74] + _T_873 <= mtdata1_t_ns[1] @[dec_tlu_ctl.scala 2207:74] + io.mtdata1_t[1] <= _T_873 @[dec_tlu_ctl.scala 2207:39] + reg _T_874 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2207:74] + _T_874 <= mtdata1_t_ns[2] @[dec_tlu_ctl.scala 2207:74] + io.mtdata1_t[2] <= _T_874 @[dec_tlu_ctl.scala 2207:39] + reg _T_875 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2207:74] + _T_875 <= mtdata1_t_ns[3] @[dec_tlu_ctl.scala 2207:74] + io.mtdata1_t[3] <= _T_875 @[dec_tlu_ctl.scala 2207:39] + node _T_876 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2210:58] + node _T_877 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2210:104] + node _T_878 = bits(io.mtdata1_t[0], 8, 7) @[dec_tlu_ctl.scala 2210:142] + node _T_879 = bits(io.mtdata1_t[0], 6, 5) @[dec_tlu_ctl.scala 2210:174] + node _T_880 = bits(io.mtdata1_t[0], 4, 3) @[dec_tlu_ctl.scala 2210:206] + node _T_881 = bits(io.mtdata1_t[0], 2, 0) @[dec_tlu_ctl.scala 2210:238] + node _T_882 = cat(UInt<3>("h00"), _T_881) @[Cat.scala 29:58] + node _T_883 = cat(_T_879, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_884 = cat(_T_883, _T_880) @[Cat.scala 29:58] + node _T_885 = cat(_T_884, _T_882) @[Cat.scala 29:58] + node _T_886 = cat(_T_878, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_887 = cat(UInt<4>("h02"), _T_877) @[Cat.scala 29:58] + node _T_888 = cat(_T_887, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_889 = cat(_T_888, _T_886) @[Cat.scala 29:58] + node _T_890 = cat(_T_889, _T_885) @[Cat.scala 29:58] + node _T_891 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2210:58] + node _T_892 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2210:104] + node _T_893 = bits(io.mtdata1_t[1], 8, 7) @[dec_tlu_ctl.scala 2210:142] + node _T_894 = bits(io.mtdata1_t[1], 6, 5) @[dec_tlu_ctl.scala 2210:174] + node _T_895 = bits(io.mtdata1_t[1], 4, 3) @[dec_tlu_ctl.scala 2210:206] + node _T_896 = bits(io.mtdata1_t[1], 2, 0) @[dec_tlu_ctl.scala 2210:238] + node _T_897 = cat(UInt<3>("h00"), _T_896) @[Cat.scala 29:58] + node _T_898 = cat(_T_894, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_899 = cat(_T_898, _T_895) @[Cat.scala 29:58] + node _T_900 = cat(_T_899, _T_897) @[Cat.scala 29:58] + node _T_901 = cat(_T_893, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_902 = cat(UInt<4>("h02"), _T_892) @[Cat.scala 29:58] + node _T_903 = cat(_T_902, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_904 = cat(_T_903, _T_901) @[Cat.scala 29:58] + node _T_905 = cat(_T_904, _T_900) @[Cat.scala 29:58] + node _T_906 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2210:58] + node _T_907 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2210:104] + node _T_908 = bits(io.mtdata1_t[2], 8, 7) @[dec_tlu_ctl.scala 2210:142] + node _T_909 = bits(io.mtdata1_t[2], 6, 5) @[dec_tlu_ctl.scala 2210:174] + node _T_910 = bits(io.mtdata1_t[2], 4, 3) @[dec_tlu_ctl.scala 2210:206] + node _T_911 = bits(io.mtdata1_t[2], 2, 0) @[dec_tlu_ctl.scala 2210:238] + node _T_912 = cat(UInt<3>("h00"), _T_911) @[Cat.scala 29:58] + node _T_913 = cat(_T_909, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_914 = cat(_T_913, _T_910) @[Cat.scala 29:58] + node _T_915 = cat(_T_914, _T_912) @[Cat.scala 29:58] + node _T_916 = cat(_T_908, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_917 = cat(UInt<4>("h02"), _T_907) @[Cat.scala 29:58] + node _T_918 = cat(_T_917, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_919 = cat(_T_918, _T_916) @[Cat.scala 29:58] + node _T_920 = cat(_T_919, _T_915) @[Cat.scala 29:58] + node _T_921 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2210:58] + node _T_922 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2210:104] + node _T_923 = bits(io.mtdata1_t[3], 8, 7) @[dec_tlu_ctl.scala 2210:142] + node _T_924 = bits(io.mtdata1_t[3], 6, 5) @[dec_tlu_ctl.scala 2210:174] + node _T_925 = bits(io.mtdata1_t[3], 4, 3) @[dec_tlu_ctl.scala 2210:206] + node _T_926 = bits(io.mtdata1_t[3], 2, 0) @[dec_tlu_ctl.scala 2210:238] + node _T_927 = cat(UInt<3>("h00"), _T_926) @[Cat.scala 29:58] + node _T_928 = cat(_T_924, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_929 = cat(_T_928, _T_925) @[Cat.scala 29:58] + node _T_930 = cat(_T_929, _T_927) @[Cat.scala 29:58] + node _T_931 = cat(_T_923, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_932 = cat(UInt<4>("h02"), _T_922) @[Cat.scala 29:58] + node _T_933 = cat(_T_932, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_934 = cat(_T_933, _T_931) @[Cat.scala 29:58] + node _T_935 = cat(_T_934, _T_930) @[Cat.scala 29:58] + node _T_936 = mux(_T_876, _T_890, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_937 = mux(_T_891, _T_905, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_938 = mux(_T_906, _T_920, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_939 = mux(_T_921, _T_935, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_940 = or(_T_936, _T_937) @[Mux.scala 27:72] + node _T_941 = or(_T_940, _T_938) @[Mux.scala 27:72] + node _T_942 = or(_T_941, _T_939) @[Mux.scala 27:72] wire mtdata1_tsel_out : UInt<32> @[Mux.scala 27:72] - mtdata1_tsel_out <= _T_932 @[Mux.scala 27:72] - node _T_933 = bits(io.mtdata1_t[0], 7, 7) @[dec_tlu_ctl.scala 2212:58] - io.trigger_pkt_any[0].select <= _T_933 @[dec_tlu_ctl.scala 2212:40] - node _T_934 = bits(io.mtdata1_t[0], 4, 4) @[dec_tlu_ctl.scala 2213:61] - io.trigger_pkt_any[0].match_pkt <= _T_934 @[dec_tlu_ctl.scala 2213:43] - node _T_935 = bits(io.mtdata1_t[0], 1, 1) @[dec_tlu_ctl.scala 2214:58] - io.trigger_pkt_any[0].store <= _T_935 @[dec_tlu_ctl.scala 2214:40] - node _T_936 = bits(io.mtdata1_t[0], 0, 0) @[dec_tlu_ctl.scala 2215:58] - io.trigger_pkt_any[0].load <= _T_936 @[dec_tlu_ctl.scala 2215:40] - node _T_937 = bits(io.mtdata1_t[0], 2, 2) @[dec_tlu_ctl.scala 2216:58] - io.trigger_pkt_any[0].execute <= _T_937 @[dec_tlu_ctl.scala 2216:40] - node _T_938 = bits(io.mtdata1_t[0], 3, 3) @[dec_tlu_ctl.scala 2217:58] - io.trigger_pkt_any[0].m <= _T_938 @[dec_tlu_ctl.scala 2217:40] - node _T_939 = bits(io.mtdata1_t[1], 7, 7) @[dec_tlu_ctl.scala 2212:58] - io.trigger_pkt_any[1].select <= _T_939 @[dec_tlu_ctl.scala 2212:40] - node _T_940 = bits(io.mtdata1_t[1], 4, 4) @[dec_tlu_ctl.scala 2213:61] - io.trigger_pkt_any[1].match_pkt <= _T_940 @[dec_tlu_ctl.scala 2213:43] - node _T_941 = bits(io.mtdata1_t[1], 1, 1) @[dec_tlu_ctl.scala 2214:58] - io.trigger_pkt_any[1].store <= _T_941 @[dec_tlu_ctl.scala 2214:40] - node _T_942 = bits(io.mtdata1_t[1], 0, 0) @[dec_tlu_ctl.scala 2215:58] - io.trigger_pkt_any[1].load <= _T_942 @[dec_tlu_ctl.scala 2215:40] - node _T_943 = bits(io.mtdata1_t[1], 2, 2) @[dec_tlu_ctl.scala 2216:58] - io.trigger_pkt_any[1].execute <= _T_943 @[dec_tlu_ctl.scala 2216:40] - node _T_944 = bits(io.mtdata1_t[1], 3, 3) @[dec_tlu_ctl.scala 2217:58] - io.trigger_pkt_any[1].m <= _T_944 @[dec_tlu_ctl.scala 2217:40] - node _T_945 = bits(io.mtdata1_t[2], 7, 7) @[dec_tlu_ctl.scala 2212:58] - io.trigger_pkt_any[2].select <= _T_945 @[dec_tlu_ctl.scala 2212:40] - node _T_946 = bits(io.mtdata1_t[2], 4, 4) @[dec_tlu_ctl.scala 2213:61] - io.trigger_pkt_any[2].match_pkt <= _T_946 @[dec_tlu_ctl.scala 2213:43] - node _T_947 = bits(io.mtdata1_t[2], 1, 1) @[dec_tlu_ctl.scala 2214:58] - io.trigger_pkt_any[2].store <= _T_947 @[dec_tlu_ctl.scala 2214:40] - node _T_948 = bits(io.mtdata1_t[2], 0, 0) @[dec_tlu_ctl.scala 2215:58] - io.trigger_pkt_any[2].load <= _T_948 @[dec_tlu_ctl.scala 2215:40] - node _T_949 = bits(io.mtdata1_t[2], 2, 2) @[dec_tlu_ctl.scala 2216:58] - io.trigger_pkt_any[2].execute <= _T_949 @[dec_tlu_ctl.scala 2216:40] - node _T_950 = bits(io.mtdata1_t[2], 3, 3) @[dec_tlu_ctl.scala 2217:58] - io.trigger_pkt_any[2].m <= _T_950 @[dec_tlu_ctl.scala 2217:40] - node _T_951 = bits(io.mtdata1_t[3], 7, 7) @[dec_tlu_ctl.scala 2212:58] - io.trigger_pkt_any[3].select <= _T_951 @[dec_tlu_ctl.scala 2212:40] - node _T_952 = bits(io.mtdata1_t[3], 4, 4) @[dec_tlu_ctl.scala 2213:61] - io.trigger_pkt_any[3].match_pkt <= _T_952 @[dec_tlu_ctl.scala 2213:43] - node _T_953 = bits(io.mtdata1_t[3], 1, 1) @[dec_tlu_ctl.scala 2214:58] - io.trigger_pkt_any[3].store <= _T_953 @[dec_tlu_ctl.scala 2214:40] - node _T_954 = bits(io.mtdata1_t[3], 0, 0) @[dec_tlu_ctl.scala 2215:58] - io.trigger_pkt_any[3].load <= _T_954 @[dec_tlu_ctl.scala 2215:40] - node _T_955 = bits(io.mtdata1_t[3], 2, 2) @[dec_tlu_ctl.scala 2216:58] - io.trigger_pkt_any[3].execute <= _T_955 @[dec_tlu_ctl.scala 2216:40] - node _T_956 = bits(io.mtdata1_t[3], 3, 3) @[dec_tlu_ctl.scala 2217:58] - io.trigger_pkt_any[3].m <= _T_956 @[dec_tlu_ctl.scala 2217:40] - node _T_957 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2224:91] - node _T_958 = eq(_T_957, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2224:98] - node _T_959 = and(io.dec_csr_wen_r_mod, _T_958) @[dec_tlu_ctl.scala 2224:69] - node _T_960 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2224:120] - node _T_961 = and(_T_959, _T_960) @[dec_tlu_ctl.scala 2224:111] - node _T_962 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2224:153] - node _T_963 = not(_T_962) @[dec_tlu_ctl.scala 2224:137] - node _T_964 = or(_T_963, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2224:169] - node _T_965 = and(_T_961, _T_964) @[dec_tlu_ctl.scala 2224:134] - node _T_966 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2224:91] - node _T_967 = eq(_T_966, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2224:98] - node _T_968 = and(io.dec_csr_wen_r_mod, _T_967) @[dec_tlu_ctl.scala 2224:69] - node _T_969 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2224:120] - node _T_970 = and(_T_968, _T_969) @[dec_tlu_ctl.scala 2224:111] - node _T_971 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2224:153] - node _T_972 = not(_T_971) @[dec_tlu_ctl.scala 2224:137] - node _T_973 = or(_T_972, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2224:169] - node _T_974 = and(_T_970, _T_973) @[dec_tlu_ctl.scala 2224:134] - node _T_975 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2224:91] - node _T_976 = eq(_T_975, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2224:98] - node _T_977 = and(io.dec_csr_wen_r_mod, _T_976) @[dec_tlu_ctl.scala 2224:69] - node _T_978 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2224:120] - node _T_979 = and(_T_977, _T_978) @[dec_tlu_ctl.scala 2224:111] - node _T_980 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2224:153] - node _T_981 = not(_T_980) @[dec_tlu_ctl.scala 2224:137] - node _T_982 = or(_T_981, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2224:169] - node _T_983 = and(_T_979, _T_982) @[dec_tlu_ctl.scala 2224:134] - node _T_984 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2224:91] - node _T_985 = eq(_T_984, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2224:98] - node _T_986 = and(io.dec_csr_wen_r_mod, _T_985) @[dec_tlu_ctl.scala 2224:69] - node _T_987 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2224:120] - node _T_988 = and(_T_986, _T_987) @[dec_tlu_ctl.scala 2224:111] - node _T_989 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2224:153] - node _T_990 = not(_T_989) @[dec_tlu_ctl.scala 2224:137] - node _T_991 = or(_T_990, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2224:169] - node _T_992 = and(_T_988, _T_991) @[dec_tlu_ctl.scala 2224:134] + mtdata1_tsel_out <= _T_942 @[Mux.scala 27:72] + node _T_943 = bits(io.mtdata1_t[0], 7, 7) @[dec_tlu_ctl.scala 2212:58] + io.trigger_pkt_any[0].select <= _T_943 @[dec_tlu_ctl.scala 2212:40] + node _T_944 = bits(io.mtdata1_t[0], 4, 4) @[dec_tlu_ctl.scala 2213:61] + io.trigger_pkt_any[0].match_pkt <= _T_944 @[dec_tlu_ctl.scala 2213:43] + node _T_945 = bits(io.mtdata1_t[0], 1, 1) @[dec_tlu_ctl.scala 2214:58] + io.trigger_pkt_any[0].store <= _T_945 @[dec_tlu_ctl.scala 2214:40] + node _T_946 = bits(io.mtdata1_t[0], 0, 0) @[dec_tlu_ctl.scala 2215:58] + io.trigger_pkt_any[0].load <= _T_946 @[dec_tlu_ctl.scala 2215:40] + node _T_947 = bits(io.mtdata1_t[0], 2, 2) @[dec_tlu_ctl.scala 2216:58] + io.trigger_pkt_any[0].execute <= _T_947 @[dec_tlu_ctl.scala 2216:40] + node _T_948 = bits(io.mtdata1_t[0], 3, 3) @[dec_tlu_ctl.scala 2217:58] + io.trigger_pkt_any[0].m <= _T_948 @[dec_tlu_ctl.scala 2217:40] + node _T_949 = bits(io.mtdata1_t[1], 7, 7) @[dec_tlu_ctl.scala 2212:58] + io.trigger_pkt_any[1].select <= _T_949 @[dec_tlu_ctl.scala 2212:40] + node _T_950 = bits(io.mtdata1_t[1], 4, 4) @[dec_tlu_ctl.scala 2213:61] + io.trigger_pkt_any[1].match_pkt <= _T_950 @[dec_tlu_ctl.scala 2213:43] + node _T_951 = bits(io.mtdata1_t[1], 1, 1) @[dec_tlu_ctl.scala 2214:58] + io.trigger_pkt_any[1].store <= _T_951 @[dec_tlu_ctl.scala 2214:40] + node _T_952 = bits(io.mtdata1_t[1], 0, 0) @[dec_tlu_ctl.scala 2215:58] + io.trigger_pkt_any[1].load <= _T_952 @[dec_tlu_ctl.scala 2215:40] + node _T_953 = bits(io.mtdata1_t[1], 2, 2) @[dec_tlu_ctl.scala 2216:58] + io.trigger_pkt_any[1].execute <= _T_953 @[dec_tlu_ctl.scala 2216:40] + node _T_954 = bits(io.mtdata1_t[1], 3, 3) @[dec_tlu_ctl.scala 2217:58] + io.trigger_pkt_any[1].m <= _T_954 @[dec_tlu_ctl.scala 2217:40] + node _T_955 = bits(io.mtdata1_t[2], 7, 7) @[dec_tlu_ctl.scala 2212:58] + io.trigger_pkt_any[2].select <= _T_955 @[dec_tlu_ctl.scala 2212:40] + node _T_956 = bits(io.mtdata1_t[2], 4, 4) @[dec_tlu_ctl.scala 2213:61] + io.trigger_pkt_any[2].match_pkt <= _T_956 @[dec_tlu_ctl.scala 2213:43] + node _T_957 = bits(io.mtdata1_t[2], 1, 1) @[dec_tlu_ctl.scala 2214:58] + io.trigger_pkt_any[2].store <= _T_957 @[dec_tlu_ctl.scala 2214:40] + node _T_958 = bits(io.mtdata1_t[2], 0, 0) @[dec_tlu_ctl.scala 2215:58] + io.trigger_pkt_any[2].load <= _T_958 @[dec_tlu_ctl.scala 2215:40] + node _T_959 = bits(io.mtdata1_t[2], 2, 2) @[dec_tlu_ctl.scala 2216:58] + io.trigger_pkt_any[2].execute <= _T_959 @[dec_tlu_ctl.scala 2216:40] + node _T_960 = bits(io.mtdata1_t[2], 3, 3) @[dec_tlu_ctl.scala 2217:58] + io.trigger_pkt_any[2].m <= _T_960 @[dec_tlu_ctl.scala 2217:40] + node _T_961 = bits(io.mtdata1_t[3], 7, 7) @[dec_tlu_ctl.scala 2212:58] + io.trigger_pkt_any[3].select <= _T_961 @[dec_tlu_ctl.scala 2212:40] + node _T_962 = bits(io.mtdata1_t[3], 4, 4) @[dec_tlu_ctl.scala 2213:61] + io.trigger_pkt_any[3].match_pkt <= _T_962 @[dec_tlu_ctl.scala 2213:43] + node _T_963 = bits(io.mtdata1_t[3], 1, 1) @[dec_tlu_ctl.scala 2214:58] + io.trigger_pkt_any[3].store <= _T_963 @[dec_tlu_ctl.scala 2214:40] + node _T_964 = bits(io.mtdata1_t[3], 0, 0) @[dec_tlu_ctl.scala 2215:58] + io.trigger_pkt_any[3].load <= _T_964 @[dec_tlu_ctl.scala 2215:40] + node _T_965 = bits(io.mtdata1_t[3], 2, 2) @[dec_tlu_ctl.scala 2216:58] + io.trigger_pkt_any[3].execute <= _T_965 @[dec_tlu_ctl.scala 2216:40] + node _T_966 = bits(io.mtdata1_t[3], 3, 3) @[dec_tlu_ctl.scala 2217:58] + io.trigger_pkt_any[3].m <= _T_966 @[dec_tlu_ctl.scala 2217:40] + node _T_967 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2224:91] + node _T_968 = eq(_T_967, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2224:98] + node _T_969 = and(io.dec_csr_wen_r_mod, _T_968) @[dec_tlu_ctl.scala 2224:69] + node _T_970 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2224:120] + node _T_971 = and(_T_969, _T_970) @[dec_tlu_ctl.scala 2224:111] + node _T_972 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2224:153] + node _T_973 = not(_T_972) @[dec_tlu_ctl.scala 2224:137] + node _T_974 = or(_T_973, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2224:169] + node _T_975 = and(_T_971, _T_974) @[dec_tlu_ctl.scala 2224:134] + node _T_976 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2224:91] + node _T_977 = eq(_T_976, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2224:98] + node _T_978 = and(io.dec_csr_wen_r_mod, _T_977) @[dec_tlu_ctl.scala 2224:69] + node _T_979 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2224:120] + node _T_980 = and(_T_978, _T_979) @[dec_tlu_ctl.scala 2224:111] + node _T_981 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2224:153] + node _T_982 = not(_T_981) @[dec_tlu_ctl.scala 2224:137] + node _T_983 = or(_T_982, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2224:169] + node _T_984 = and(_T_980, _T_983) @[dec_tlu_ctl.scala 2224:134] + node _T_985 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2224:91] + node _T_986 = eq(_T_985, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2224:98] + node _T_987 = and(io.dec_csr_wen_r_mod, _T_986) @[dec_tlu_ctl.scala 2224:69] + node _T_988 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2224:120] + node _T_989 = and(_T_987, _T_988) @[dec_tlu_ctl.scala 2224:111] + node _T_990 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2224:153] + node _T_991 = not(_T_990) @[dec_tlu_ctl.scala 2224:137] + node _T_992 = or(_T_991, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2224:169] + node _T_993 = and(_T_989, _T_992) @[dec_tlu_ctl.scala 2224:134] + node _T_994 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2224:91] + node _T_995 = eq(_T_994, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2224:98] + node _T_996 = and(io.dec_csr_wen_r_mod, _T_995) @[dec_tlu_ctl.scala 2224:69] + node _T_997 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2224:120] + node _T_998 = and(_T_996, _T_997) @[dec_tlu_ctl.scala 2224:111] + node _T_999 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2224:153] + node _T_1000 = not(_T_999) @[dec_tlu_ctl.scala 2224:137] + node _T_1001 = or(_T_1000, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2224:169] + node _T_1002 = and(_T_998, _T_1001) @[dec_tlu_ctl.scala 2224:134] wire wr_mtdata2_t_r : UInt<1>[4] @[dec_tlu_ctl.scala 2224:42] - wr_mtdata2_t_r[0] <= _T_965 @[dec_tlu_ctl.scala 2224:42] - wr_mtdata2_t_r[1] <= _T_974 @[dec_tlu_ctl.scala 2224:42] - wr_mtdata2_t_r[2] <= _T_983 @[dec_tlu_ctl.scala 2224:42] - wr_mtdata2_t_r[3] <= _T_992 @[dec_tlu_ctl.scala 2224:42] - node _T_993 = bits(wr_mtdata2_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2225:84] + wr_mtdata2_t_r[0] <= _T_975 @[dec_tlu_ctl.scala 2224:42] + wr_mtdata2_t_r[1] <= _T_984 @[dec_tlu_ctl.scala 2224:42] + wr_mtdata2_t_r[2] <= _T_993 @[dec_tlu_ctl.scala 2224:42] + wr_mtdata2_t_r[3] <= _T_1002 @[dec_tlu_ctl.scala 2224:42] + node _T_1003 = bits(wr_mtdata2_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2225:84] inst rvclkhdr_22 of rvclkhdr_742 @[lib.scala 368:23] rvclkhdr_22.clock <= clock rvclkhdr_22.reset <= reset rvclkhdr_22.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_22.io.en <= _T_993 @[lib.scala 371:17] + rvclkhdr_22.io.en <= _T_1003 @[lib.scala 371:17] rvclkhdr_22.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_994 : UInt, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_994 <= io.dec_csr_wrdata_r @[lib.scala 374:16] - mtdata2_t[0] <= _T_994 @[dec_tlu_ctl.scala 2225:36] - node _T_995 = bits(wr_mtdata2_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2225:84] + reg _T_1004 : UInt, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_1004 <= io.dec_csr_wrdata_r @[lib.scala 374:16] + mtdata2_t[0] <= _T_1004 @[dec_tlu_ctl.scala 2225:36] + node _T_1005 = bits(wr_mtdata2_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2225:84] inst rvclkhdr_23 of rvclkhdr_743 @[lib.scala 368:23] rvclkhdr_23.clock <= clock rvclkhdr_23.reset <= reset rvclkhdr_23.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_23.io.en <= _T_995 @[lib.scala 371:17] + rvclkhdr_23.io.en <= _T_1005 @[lib.scala 371:17] rvclkhdr_23.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_996 : UInt, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_996 <= io.dec_csr_wrdata_r @[lib.scala 374:16] - mtdata2_t[1] <= _T_996 @[dec_tlu_ctl.scala 2225:36] - node _T_997 = bits(wr_mtdata2_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2225:84] + reg _T_1006 : UInt, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_1006 <= io.dec_csr_wrdata_r @[lib.scala 374:16] + mtdata2_t[1] <= _T_1006 @[dec_tlu_ctl.scala 2225:36] + node _T_1007 = bits(wr_mtdata2_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2225:84] inst rvclkhdr_24 of rvclkhdr_744 @[lib.scala 368:23] rvclkhdr_24.clock <= clock rvclkhdr_24.reset <= reset rvclkhdr_24.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_24.io.en <= _T_997 @[lib.scala 371:17] + rvclkhdr_24.io.en <= _T_1007 @[lib.scala 371:17] rvclkhdr_24.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_998 : UInt, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_998 <= io.dec_csr_wrdata_r @[lib.scala 374:16] - mtdata2_t[2] <= _T_998 @[dec_tlu_ctl.scala 2225:36] - node _T_999 = bits(wr_mtdata2_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2225:84] + reg _T_1008 : UInt, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_1008 <= io.dec_csr_wrdata_r @[lib.scala 374:16] + mtdata2_t[2] <= _T_1008 @[dec_tlu_ctl.scala 2225:36] + node _T_1009 = bits(wr_mtdata2_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2225:84] inst rvclkhdr_25 of rvclkhdr_745 @[lib.scala 368:23] rvclkhdr_25.clock <= clock rvclkhdr_25.reset <= reset rvclkhdr_25.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_25.io.en <= _T_999 @[lib.scala 371:17] + rvclkhdr_25.io.en <= _T_1009 @[lib.scala 371:17] rvclkhdr_25.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_1000 : UInt, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_1000 <= io.dec_csr_wrdata_r @[lib.scala 374:16] - mtdata2_t[3] <= _T_1000 @[dec_tlu_ctl.scala 2225:36] - node _T_1001 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2229:57] - node _T_1002 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2229:57] - node _T_1003 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2229:57] - node _T_1004 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2229:57] - node _T_1005 = mux(_T_1001, mtdata2_t[0], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1006 = mux(_T_1002, mtdata2_t[1], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1007 = mux(_T_1003, mtdata2_t[2], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1008 = mux(_T_1004, mtdata2_t[3], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1009 = or(_T_1005, _T_1006) @[Mux.scala 27:72] - node _T_1010 = or(_T_1009, _T_1007) @[Mux.scala 27:72] - node _T_1011 = or(_T_1010, _T_1008) @[Mux.scala 27:72] + reg _T_1010 : UInt, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_1010 <= io.dec_csr_wrdata_r @[lib.scala 374:16] + mtdata2_t[3] <= _T_1010 @[dec_tlu_ctl.scala 2225:36] + node _T_1011 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2229:57] + node _T_1012 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2229:57] + node _T_1013 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2229:57] + node _T_1014 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2229:57] + node _T_1015 = mux(_T_1011, mtdata2_t[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1016 = mux(_T_1012, mtdata2_t[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1017 = mux(_T_1013, mtdata2_t[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1018 = mux(_T_1014, mtdata2_t[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1019 = or(_T_1015, _T_1016) @[Mux.scala 27:72] + node _T_1020 = or(_T_1019, _T_1017) @[Mux.scala 27:72] + node _T_1021 = or(_T_1020, _T_1018) @[Mux.scala 27:72] wire mtdata2_tsel_out : UInt<32> @[Mux.scala 27:72] - mtdata2_tsel_out <= _T_1011 @[Mux.scala 27:72] + mtdata2_tsel_out <= _T_1021 @[Mux.scala 27:72] io.trigger_pkt_any[0].tdata2 <= mtdata2_t[0] @[dec_tlu_ctl.scala 2230:51] io.trigger_pkt_any[1].tdata2 <= mtdata2_t[1] @[dec_tlu_ctl.scala 2230:51] io.trigger_pkt_any[2].tdata2 <= mtdata2_t[2] @[dec_tlu_ctl.scala 2230:51] @@ -74335,248 +74345,238 @@ circuit quasar : mhpme_vec[1] <= mhpme4 @[dec_tlu_ctl.scala 2241:15] mhpme_vec[2] <= mhpme5 @[dec_tlu_ctl.scala 2242:15] mhpme_vec[3] <= mhpme6 @[dec_tlu_ctl.scala 2243:15] - node _T_1012 = bits(io.tlu_i0_commit_cmt, 0, 0) @[Bitwise.scala 72:15] - node _T_1013 = mux(_T_1012, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node pmu_i0_itype_qual = and(io.dec_tlu_packet_r.pmu_i0_itype, _T_1013) @[dec_tlu_ctl.scala 2249:59] + node _T_1022 = bits(io.tlu_i0_commit_cmt, 0, 0) @[Bitwise.scala 72:15] + node _T_1023 = mux(_T_1022, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node pmu_i0_itype_qual = and(io.dec_tlu_packet_r.pmu_i0_itype, _T_1023) @[dec_tlu_ctl.scala 2249:59] wire mhpmc_inc_r : UInt<1>[4] @[dec_tlu_ctl.scala 2250:24] wire mhpmc_inc_r_d1 : UInt<1>[4] @[dec_tlu_ctl.scala 2251:27] - node _T_1014 = bits(mcountinhibit, 3, 3) @[dec_tlu_ctl.scala 2255:38] - node _T_1015 = not(_T_1014) @[dec_tlu_ctl.scala 2255:24] - node _T_1016 = eq(mhpme_vec[0], UInt<1>("h01")) @[dec_tlu_ctl.scala 2256:34] - node _T_1017 = bits(_T_1016, 0, 0) @[dec_tlu_ctl.scala 2256:62] - node _T_1018 = eq(mhpme_vec[0], UInt<2>("h02")) @[dec_tlu_ctl.scala 2257:34] - node _T_1019 = bits(_T_1018, 0, 0) @[dec_tlu_ctl.scala 2257:62] - node _T_1020 = eq(mhpme_vec[0], UInt<2>("h03")) @[dec_tlu_ctl.scala 2258:34] - node _T_1021 = bits(_T_1020, 0, 0) @[dec_tlu_ctl.scala 2258:62] - node _T_1022 = eq(mhpme_vec[0], UInt<3>("h04")) @[dec_tlu_ctl.scala 2259:34] - node _T_1023 = bits(_T_1022, 0, 0) @[dec_tlu_ctl.scala 2259:62] - node _T_1024 = not(io.illegal_r) @[dec_tlu_ctl.scala 2259:96] - node _T_1025 = and(io.tlu_i0_commit_cmt, _T_1024) @[dec_tlu_ctl.scala 2259:94] - node _T_1026 = eq(mhpme_vec[0], UInt<3>("h05")) @[dec_tlu_ctl.scala 2260:34] - node _T_1027 = bits(_T_1026, 0, 0) @[dec_tlu_ctl.scala 2260:62] - node _T_1028 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2260:96] - node _T_1029 = and(io.tlu_i0_commit_cmt, _T_1028) @[dec_tlu_ctl.scala 2260:94] - node _T_1030 = not(io.illegal_r) @[dec_tlu_ctl.scala 2260:117] - node _T_1031 = and(_T_1029, _T_1030) @[dec_tlu_ctl.scala 2260:115] - node _T_1032 = eq(mhpme_vec[0], UInt<3>("h06")) @[dec_tlu_ctl.scala 2261:34] - node _T_1033 = bits(_T_1032, 0, 0) @[dec_tlu_ctl.scala 2261:62] - node _T_1034 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2261:94] - node _T_1035 = not(io.illegal_r) @[dec_tlu_ctl.scala 2261:117] - node _T_1036 = and(_T_1034, _T_1035) @[dec_tlu_ctl.scala 2261:115] - node _T_1037 = eq(mhpme_vec[0], UInt<3>("h07")) @[dec_tlu_ctl.scala 2262:34] - node _T_1038 = bits(_T_1037, 0, 0) @[dec_tlu_ctl.scala 2262:62] - node _T_1039 = eq(mhpme_vec[0], UInt<4>("h08")) @[dec_tlu_ctl.scala 2263:34] - node _T_1040 = bits(_T_1039, 0, 0) @[dec_tlu_ctl.scala 2263:62] - node _T_1041 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2264:34] - node _T_1042 = bits(_T_1041, 0, 0) @[dec_tlu_ctl.scala 2264:62] - node _T_1043 = eq(mhpme_vec[0], UInt<4>("h09")) @[dec_tlu_ctl.scala 2265:34] - node _T_1044 = bits(_T_1043, 0, 0) @[dec_tlu_ctl.scala 2265:62] - node _T_1045 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2265:91] - node _T_1046 = eq(mhpme_vec[0], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2266:34] - node _T_1047 = bits(_T_1046, 0, 0) @[dec_tlu_ctl.scala 2266:62] - node _T_1048 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2266:105] - node _T_1049 = eq(mhpme_vec[0], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2267:34] - node _T_1050 = bits(_T_1049, 0, 0) @[dec_tlu_ctl.scala 2267:62] - node _T_1051 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2267:91] - node _T_1052 = eq(mhpme_vec[0], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2268:34] - node _T_1053 = bits(_T_1052, 0, 0) @[dec_tlu_ctl.scala 2268:62] - node _T_1054 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2268:91] - node _T_1055 = eq(mhpme_vec[0], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2269:34] - node _T_1056 = bits(_T_1055, 0, 0) @[dec_tlu_ctl.scala 2269:62] - node _T_1057 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2269:91] - node _T_1058 = and(_T_1057, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2269:100] - node _T_1059 = eq(mhpme_vec[0], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2270:34] - node _T_1060 = bits(_T_1059, 0, 0) @[dec_tlu_ctl.scala 2270:62] - node _T_1061 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2270:91] - node _T_1062 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2270:142] - node _T_1063 = and(_T_1061, _T_1062) @[dec_tlu_ctl.scala 2270:101] - node _T_1064 = eq(mhpme_vec[0], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2271:34] - node _T_1065 = bits(_T_1064, 0, 0) @[dec_tlu_ctl.scala 2271:59] - node _T_1066 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2271:89] - node _T_1067 = eq(mhpme_vec[0], UInt<5>("h010")) @[dec_tlu_ctl.scala 2272:34] - node _T_1068 = bits(_T_1067, 0, 0) @[dec_tlu_ctl.scala 2272:59] - node _T_1069 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2272:89] - node _T_1070 = eq(mhpme_vec[0], UInt<5>("h012")) @[dec_tlu_ctl.scala 2273:34] - node _T_1071 = bits(_T_1070, 0, 0) @[dec_tlu_ctl.scala 2273:59] - node _T_1072 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2273:89] - node _T_1073 = eq(mhpme_vec[0], UInt<5>("h011")) @[dec_tlu_ctl.scala 2274:34] - node _T_1074 = bits(_T_1073, 0, 0) @[dec_tlu_ctl.scala 2274:59] - node _T_1075 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2274:89] - node _T_1076 = eq(mhpme_vec[0], UInt<5>("h013")) @[dec_tlu_ctl.scala 2275:34] - node _T_1077 = bits(_T_1076, 0, 0) @[dec_tlu_ctl.scala 2275:59] - node _T_1078 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2275:89] - node _T_1079 = eq(mhpme_vec[0], UInt<5>("h014")) @[dec_tlu_ctl.scala 2276:34] - node _T_1080 = bits(_T_1079, 0, 0) @[dec_tlu_ctl.scala 2276:59] - node _T_1081 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2276:89] - node _T_1082 = eq(mhpme_vec[0], UInt<5>("h015")) @[dec_tlu_ctl.scala 2277:34] - node _T_1083 = bits(_T_1082, 0, 0) @[dec_tlu_ctl.scala 2277:59] - node _T_1084 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2277:89] - node _T_1085 = eq(mhpme_vec[0], UInt<5>("h016")) @[dec_tlu_ctl.scala 2278:34] - node _T_1086 = bits(_T_1085, 0, 0) @[dec_tlu_ctl.scala 2278:59] - node _T_1087 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2278:89] - node _T_1088 = eq(mhpme_vec[0], UInt<5>("h017")) @[dec_tlu_ctl.scala 2279:34] - node _T_1089 = bits(_T_1088, 0, 0) @[dec_tlu_ctl.scala 2279:59] - node _T_1090 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2279:89] - node _T_1091 = eq(mhpme_vec[0], UInt<5>("h018")) @[dec_tlu_ctl.scala 2280:34] - node _T_1092 = bits(_T_1091, 0, 0) @[dec_tlu_ctl.scala 2280:59] - node _T_1093 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2280:89] - node _T_1094 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2280:122] - node _T_1095 = or(_T_1093, _T_1094) @[dec_tlu_ctl.scala 2280:101] - node _T_1096 = eq(mhpme_vec[0], UInt<5>("h019")) @[dec_tlu_ctl.scala 2281:34] - node _T_1097 = bits(_T_1096, 0, 0) @[dec_tlu_ctl.scala 2281:62] - node _T_1098 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2281:95] - node _T_1099 = eq(mhpme_vec[0], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2282:34] - node _T_1100 = bits(_T_1099, 0, 0) @[dec_tlu_ctl.scala 2282:62] - node _T_1101 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2282:97] - node _T_1102 = eq(mhpme_vec[0], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2283:34] - node _T_1103 = bits(_T_1102, 0, 0) @[dec_tlu_ctl.scala 2283:62] - node _T_1104 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2283:110] - node _T_1105 = eq(mhpme_vec[0], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2284:34] - node _T_1106 = bits(_T_1105, 0, 0) @[dec_tlu_ctl.scala 2284:62] - node _T_1107 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2285:34] - node _T_1108 = bits(_T_1107, 0, 0) @[dec_tlu_ctl.scala 2285:62] - node _T_1109 = eq(mhpme_vec[0], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2286:34] - node _T_1110 = bits(_T_1109, 0, 0) @[dec_tlu_ctl.scala 2286:62] - node _T_1111 = eq(mhpme_vec[0], UInt<6>("h020")) @[dec_tlu_ctl.scala 2287:34] - node _T_1112 = bits(_T_1111, 0, 0) @[dec_tlu_ctl.scala 2287:62] - node _T_1113 = eq(mhpme_vec[0], UInt<6>("h022")) @[dec_tlu_ctl.scala 2288:34] - node _T_1114 = bits(_T_1113, 0, 0) @[dec_tlu_ctl.scala 2288:62] - node _T_1115 = eq(mhpme_vec[0], UInt<6>("h023")) @[dec_tlu_ctl.scala 2289:34] - node _T_1116 = bits(_T_1115, 0, 0) @[dec_tlu_ctl.scala 2289:62] - node _T_1117 = eq(mhpme_vec[0], UInt<6>("h024")) @[dec_tlu_ctl.scala 2290:34] - node _T_1118 = bits(_T_1117, 0, 0) @[dec_tlu_ctl.scala 2290:62] - node _T_1119 = eq(mhpme_vec[0], UInt<6>("h025")) @[dec_tlu_ctl.scala 2291:34] - node _T_1120 = bits(_T_1119, 0, 0) @[dec_tlu_ctl.scala 2291:62] - node _T_1121 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2291:98] - node _T_1122 = or(_T_1121, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2291:120] - node _T_1123 = eq(mhpme_vec[0], UInt<6>("h026")) @[dec_tlu_ctl.scala 2292:34] - node _T_1124 = bits(_T_1123, 0, 0) @[dec_tlu_ctl.scala 2292:62] - node _T_1125 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2292:92] - node _T_1126 = or(_T_1125, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2292:117] - node _T_1127 = eq(mhpme_vec[0], UInt<6>("h027")) @[dec_tlu_ctl.scala 2293:34] - node _T_1128 = bits(_T_1127, 0, 0) @[dec_tlu_ctl.scala 2293:62] - node _T_1129 = eq(mhpme_vec[0], UInt<6>("h028")) @[dec_tlu_ctl.scala 2294:34] - node _T_1130 = bits(_T_1129, 0, 0) @[dec_tlu_ctl.scala 2294:62] - node _T_1131 = eq(mhpme_vec[0], UInt<6>("h029")) @[dec_tlu_ctl.scala 2295:34] - node _T_1132 = bits(_T_1131, 0, 0) @[dec_tlu_ctl.scala 2295:62] - node _T_1133 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2295:97] - node _T_1134 = and(_T_1133, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2295:129] - node _T_1135 = eq(mhpme_vec[0], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2296:34] - node _T_1136 = bits(_T_1135, 0, 0) @[dec_tlu_ctl.scala 2296:62] - node _T_1137 = eq(mhpme_vec[0], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2297:34] - node _T_1138 = bits(_T_1137, 0, 0) @[dec_tlu_ctl.scala 2297:62] - node _T_1139 = eq(mhpme_vec[0], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2298:34] - node _T_1140 = bits(_T_1139, 0, 0) @[dec_tlu_ctl.scala 2298:62] - node _T_1141 = eq(mhpme_vec[0], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2299:34] - node _T_1142 = bits(_T_1141, 0, 0) @[dec_tlu_ctl.scala 2299:62] - node _T_1143 = eq(mhpme_vec[0], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2300:34] - node _T_1144 = bits(_T_1143, 0, 0) @[dec_tlu_ctl.scala 2300:62] - node _T_1145 = eq(mhpme_vec[0], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2301:34] - node _T_1146 = bits(_T_1145, 0, 0) @[dec_tlu_ctl.scala 2301:62] - node _T_1147 = eq(mhpme_vec[0], UInt<6>("h030")) @[dec_tlu_ctl.scala 2302:34] - node _T_1148 = bits(_T_1147, 0, 0) @[dec_tlu_ctl.scala 2302:62] - node _T_1149 = eq(mhpme_vec[0], UInt<6>("h031")) @[dec_tlu_ctl.scala 2303:34] - node _T_1150 = bits(_T_1149, 0, 0) @[dec_tlu_ctl.scala 2303:62] - node _T_1151 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2303:84] - node _T_1152 = bits(_T_1151, 0, 0) @[dec_tlu_ctl.scala 2303:84] - node _T_1153 = not(_T_1152) @[dec_tlu_ctl.scala 2303:73] - node _T_1154 = eq(mhpme_vec[0], UInt<6>("h032")) @[dec_tlu_ctl.scala 2304:34] - node _T_1155 = bits(_T_1154, 0, 0) @[dec_tlu_ctl.scala 2304:62] - node _T_1156 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2304:84] - node _T_1157 = bits(_T_1156, 0, 0) @[dec_tlu_ctl.scala 2304:84] - node _T_1158 = not(_T_1157) @[dec_tlu_ctl.scala 2304:73] - node _T_1159 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2304:107] - node _T_1160 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2304:118] - node _T_1161 = and(_T_1159, _T_1160) @[dec_tlu_ctl.scala 2304:113] - node _T_1162 = orr(_T_1161) @[dec_tlu_ctl.scala 2304:125] - node _T_1163 = and(_T_1158, _T_1162) @[dec_tlu_ctl.scala 2304:98] - node _T_1164 = eq(mhpme_vec[0], UInt<6>("h036")) @[dec_tlu_ctl.scala 2305:34] - node _T_1165 = bits(_T_1164, 0, 0) @[dec_tlu_ctl.scala 2305:62] - node _T_1166 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2305:91] - node _T_1167 = eq(mhpme_vec[0], UInt<6>("h037")) @[dec_tlu_ctl.scala 2306:34] - node _T_1168 = bits(_T_1167, 0, 0) @[dec_tlu_ctl.scala 2306:62] - node _T_1169 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2306:94] - node _T_1170 = eq(mhpme_vec[0], UInt<6>("h038")) @[dec_tlu_ctl.scala 2307:34] - node _T_1171 = bits(_T_1170, 0, 0) @[dec_tlu_ctl.scala 2307:62] - node _T_1172 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2307:94] - node _T_1173 = eq(mhpme_vec[0], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2309:34] - node _T_1174 = bits(_T_1173, 0, 0) @[dec_tlu_ctl.scala 2309:62] - node _T_1175 = eq(mhpme_vec[0], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2310:34] - node _T_1176 = bits(_T_1175, 0, 0) @[dec_tlu_ctl.scala 2310:62] - node _T_1177 = eq(mhpme_vec[0], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2311:34] - node _T_1178 = bits(_T_1177, 0, 0) @[dec_tlu_ctl.scala 2311:62] - node _T_1179 = eq(mhpme_vec[0], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2312:34] - node _T_1180 = bits(_T_1179, 0, 0) @[dec_tlu_ctl.scala 2312:62] - node _T_1181 = eq(mhpme_vec[0], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2313:34] - node _T_1182 = bits(_T_1181, 0, 0) @[dec_tlu_ctl.scala 2313:62] - node _T_1183 = mux(_T_1017, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1184 = mux(_T_1019, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1185 = mux(_T_1021, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1186 = mux(_T_1023, _T_1025, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1187 = mux(_T_1027, _T_1031, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1188 = mux(_T_1033, _T_1036, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1189 = mux(_T_1038, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1190 = mux(_T_1040, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1191 = mux(_T_1042, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1192 = mux(_T_1044, _T_1045, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1193 = mux(_T_1047, _T_1048, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1194 = mux(_T_1050, _T_1051, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1195 = mux(_T_1053, _T_1054, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1196 = mux(_T_1056, _T_1058, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1197 = mux(_T_1060, _T_1063, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1198 = mux(_T_1065, _T_1066, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1199 = mux(_T_1068, _T_1069, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1200 = mux(_T_1071, _T_1072, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1201 = mux(_T_1074, _T_1075, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1202 = mux(_T_1077, _T_1078, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1203 = mux(_T_1080, _T_1081, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1204 = mux(_T_1083, _T_1084, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1205 = mux(_T_1086, _T_1087, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1206 = mux(_T_1089, _T_1090, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1207 = mux(_T_1092, _T_1095, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1208 = mux(_T_1097, _T_1098, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1209 = mux(_T_1100, _T_1101, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1210 = mux(_T_1103, _T_1104, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1211 = mux(_T_1106, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1212 = mux(_T_1108, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1213 = mux(_T_1110, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1214 = mux(_T_1112, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1215 = mux(_T_1114, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1216 = mux(_T_1116, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1217 = mux(_T_1118, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1218 = mux(_T_1120, _T_1122, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1219 = mux(_T_1124, _T_1126, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1220 = mux(_T_1128, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1221 = mux(_T_1130, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1222 = mux(_T_1132, _T_1134, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1223 = mux(_T_1136, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1224 = mux(_T_1138, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1225 = mux(_T_1140, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1226 = mux(_T_1142, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1227 = mux(_T_1144, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1228 = mux(_T_1146, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1229 = mux(_T_1148, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1230 = mux(_T_1150, _T_1153, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1231 = mux(_T_1155, _T_1163, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1232 = mux(_T_1165, _T_1166, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1233 = mux(_T_1168, _T_1169, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1234 = mux(_T_1171, _T_1172, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1235 = mux(_T_1174, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1236 = mux(_T_1176, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1237 = mux(_T_1178, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1238 = mux(_T_1180, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1239 = mux(_T_1182, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1240 = or(_T_1183, _T_1184) @[Mux.scala 27:72] - node _T_1241 = or(_T_1240, _T_1185) @[Mux.scala 27:72] - node _T_1242 = or(_T_1241, _T_1186) @[Mux.scala 27:72] - node _T_1243 = or(_T_1242, _T_1187) @[Mux.scala 27:72] - node _T_1244 = or(_T_1243, _T_1188) @[Mux.scala 27:72] - node _T_1245 = or(_T_1244, _T_1189) @[Mux.scala 27:72] - node _T_1246 = or(_T_1245, _T_1190) @[Mux.scala 27:72] - node _T_1247 = or(_T_1246, _T_1191) @[Mux.scala 27:72] - node _T_1248 = or(_T_1247, _T_1192) @[Mux.scala 27:72] - node _T_1249 = or(_T_1248, _T_1193) @[Mux.scala 27:72] - node _T_1250 = or(_T_1249, _T_1194) @[Mux.scala 27:72] + node _T_1024 = bits(mcountinhibit, 3, 3) @[dec_tlu_ctl.scala 2255:38] + node _T_1025 = not(_T_1024) @[dec_tlu_ctl.scala 2255:24] + node _T_1026 = eq(mhpme_vec[0], UInt<1>("h01")) @[dec_tlu_ctl.scala 2256:34] + node _T_1027 = bits(_T_1026, 0, 0) @[dec_tlu_ctl.scala 2256:62] + node _T_1028 = eq(mhpme_vec[0], UInt<2>("h02")) @[dec_tlu_ctl.scala 2257:34] + node _T_1029 = bits(_T_1028, 0, 0) @[dec_tlu_ctl.scala 2257:62] + node _T_1030 = eq(mhpme_vec[0], UInt<2>("h03")) @[dec_tlu_ctl.scala 2258:34] + node _T_1031 = bits(_T_1030, 0, 0) @[dec_tlu_ctl.scala 2258:62] + node _T_1032 = eq(mhpme_vec[0], UInt<3>("h04")) @[dec_tlu_ctl.scala 2259:34] + node _T_1033 = bits(_T_1032, 0, 0) @[dec_tlu_ctl.scala 2259:62] + node _T_1034 = not(io.illegal_r) @[dec_tlu_ctl.scala 2259:96] + node _T_1035 = and(io.tlu_i0_commit_cmt, _T_1034) @[dec_tlu_ctl.scala 2259:94] + node _T_1036 = eq(mhpme_vec[0], UInt<3>("h05")) @[dec_tlu_ctl.scala 2260:34] + node _T_1037 = bits(_T_1036, 0, 0) @[dec_tlu_ctl.scala 2260:62] + node _T_1038 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2260:96] + node _T_1039 = and(io.tlu_i0_commit_cmt, _T_1038) @[dec_tlu_ctl.scala 2260:94] + node _T_1040 = not(io.illegal_r) @[dec_tlu_ctl.scala 2260:117] + node _T_1041 = and(_T_1039, _T_1040) @[dec_tlu_ctl.scala 2260:115] + node _T_1042 = eq(mhpme_vec[0], UInt<3>("h06")) @[dec_tlu_ctl.scala 2261:34] + node _T_1043 = bits(_T_1042, 0, 0) @[dec_tlu_ctl.scala 2261:62] + node _T_1044 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2261:94] + node _T_1045 = not(io.illegal_r) @[dec_tlu_ctl.scala 2261:117] + node _T_1046 = and(_T_1044, _T_1045) @[dec_tlu_ctl.scala 2261:115] + node _T_1047 = eq(mhpme_vec[0], UInt<3>("h07")) @[dec_tlu_ctl.scala 2262:34] + node _T_1048 = bits(_T_1047, 0, 0) @[dec_tlu_ctl.scala 2262:62] + node _T_1049 = eq(mhpme_vec[0], UInt<4>("h08")) @[dec_tlu_ctl.scala 2263:34] + node _T_1050 = bits(_T_1049, 0, 0) @[dec_tlu_ctl.scala 2263:62] + node _T_1051 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2264:34] + node _T_1052 = bits(_T_1051, 0, 0) @[dec_tlu_ctl.scala 2264:62] + node _T_1053 = eq(mhpme_vec[0], UInt<4>("h09")) @[dec_tlu_ctl.scala 2265:34] + node _T_1054 = bits(_T_1053, 0, 0) @[dec_tlu_ctl.scala 2265:62] + node _T_1055 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2265:91] + node _T_1056 = eq(mhpme_vec[0], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2266:34] + node _T_1057 = bits(_T_1056, 0, 0) @[dec_tlu_ctl.scala 2266:62] + node _T_1058 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2266:105] + node _T_1059 = eq(mhpme_vec[0], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2267:34] + node _T_1060 = bits(_T_1059, 0, 0) @[dec_tlu_ctl.scala 2267:62] + node _T_1061 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2267:91] + node _T_1062 = eq(mhpme_vec[0], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2268:34] + node _T_1063 = bits(_T_1062, 0, 0) @[dec_tlu_ctl.scala 2268:62] + node _T_1064 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2268:91] + node _T_1065 = eq(mhpme_vec[0], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2269:34] + node _T_1066 = bits(_T_1065, 0, 0) @[dec_tlu_ctl.scala 2269:62] + node _T_1067 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2269:91] + node _T_1068 = and(_T_1067, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2269:100] + node _T_1069 = eq(mhpme_vec[0], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2270:34] + node _T_1070 = bits(_T_1069, 0, 0) @[dec_tlu_ctl.scala 2270:62] + node _T_1071 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2270:91] + node _T_1072 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2270:142] + node _T_1073 = and(_T_1071, _T_1072) @[dec_tlu_ctl.scala 2270:101] + node _T_1074 = eq(mhpme_vec[0], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2271:34] + node _T_1075 = bits(_T_1074, 0, 0) @[dec_tlu_ctl.scala 2271:59] + node _T_1076 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2271:89] + node _T_1077 = eq(mhpme_vec[0], UInt<5>("h010")) @[dec_tlu_ctl.scala 2272:34] + node _T_1078 = bits(_T_1077, 0, 0) @[dec_tlu_ctl.scala 2272:59] + node _T_1079 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2272:89] + node _T_1080 = eq(mhpme_vec[0], UInt<5>("h012")) @[dec_tlu_ctl.scala 2273:34] + node _T_1081 = bits(_T_1080, 0, 0) @[dec_tlu_ctl.scala 2273:59] + node _T_1082 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2273:89] + node _T_1083 = eq(mhpme_vec[0], UInt<5>("h011")) @[dec_tlu_ctl.scala 2274:34] + node _T_1084 = bits(_T_1083, 0, 0) @[dec_tlu_ctl.scala 2274:59] + node _T_1085 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2274:89] + node _T_1086 = eq(mhpme_vec[0], UInt<5>("h013")) @[dec_tlu_ctl.scala 2275:34] + node _T_1087 = bits(_T_1086, 0, 0) @[dec_tlu_ctl.scala 2275:59] + node _T_1088 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2275:89] + node _T_1089 = eq(mhpme_vec[0], UInt<5>("h014")) @[dec_tlu_ctl.scala 2276:34] + node _T_1090 = bits(_T_1089, 0, 0) @[dec_tlu_ctl.scala 2276:59] + node _T_1091 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2276:89] + node _T_1092 = eq(mhpme_vec[0], UInt<5>("h015")) @[dec_tlu_ctl.scala 2277:34] + node _T_1093 = bits(_T_1092, 0, 0) @[dec_tlu_ctl.scala 2277:59] + node _T_1094 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2277:89] + node _T_1095 = eq(mhpme_vec[0], UInt<5>("h016")) @[dec_tlu_ctl.scala 2278:34] + node _T_1096 = bits(_T_1095, 0, 0) @[dec_tlu_ctl.scala 2278:59] + node _T_1097 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2278:89] + node _T_1098 = eq(mhpme_vec[0], UInt<5>("h017")) @[dec_tlu_ctl.scala 2279:34] + node _T_1099 = bits(_T_1098, 0, 0) @[dec_tlu_ctl.scala 2279:59] + node _T_1100 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2279:89] + node _T_1101 = eq(mhpme_vec[0], UInt<5>("h018")) @[dec_tlu_ctl.scala 2280:34] + node _T_1102 = bits(_T_1101, 0, 0) @[dec_tlu_ctl.scala 2280:59] + node _T_1103 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2280:89] + node _T_1104 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2280:122] + node _T_1105 = or(_T_1103, _T_1104) @[dec_tlu_ctl.scala 2280:101] + node _T_1106 = eq(mhpme_vec[0], UInt<5>("h019")) @[dec_tlu_ctl.scala 2281:34] + node _T_1107 = bits(_T_1106, 0, 0) @[dec_tlu_ctl.scala 2281:62] + node _T_1108 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2281:95] + node _T_1109 = eq(mhpme_vec[0], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2282:34] + node _T_1110 = bits(_T_1109, 0, 0) @[dec_tlu_ctl.scala 2282:62] + node _T_1111 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2282:97] + node _T_1112 = eq(mhpme_vec[0], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2283:34] + node _T_1113 = bits(_T_1112, 0, 0) @[dec_tlu_ctl.scala 2283:62] + node _T_1114 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2283:110] + node _T_1115 = eq(mhpme_vec[0], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2284:34] + node _T_1116 = bits(_T_1115, 0, 0) @[dec_tlu_ctl.scala 2284:62] + node _T_1117 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2285:34] + node _T_1118 = bits(_T_1117, 0, 0) @[dec_tlu_ctl.scala 2285:62] + node _T_1119 = eq(mhpme_vec[0], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2286:34] + node _T_1120 = bits(_T_1119, 0, 0) @[dec_tlu_ctl.scala 2286:62] + node _T_1121 = eq(mhpme_vec[0], UInt<6>("h020")) @[dec_tlu_ctl.scala 2287:34] + node _T_1122 = bits(_T_1121, 0, 0) @[dec_tlu_ctl.scala 2287:62] + node _T_1123 = eq(mhpme_vec[0], UInt<6>("h022")) @[dec_tlu_ctl.scala 2288:34] + node _T_1124 = bits(_T_1123, 0, 0) @[dec_tlu_ctl.scala 2288:62] + node _T_1125 = eq(mhpme_vec[0], UInt<6>("h023")) @[dec_tlu_ctl.scala 2289:34] + node _T_1126 = bits(_T_1125, 0, 0) @[dec_tlu_ctl.scala 2289:62] + node _T_1127 = eq(mhpme_vec[0], UInt<6>("h024")) @[dec_tlu_ctl.scala 2290:34] + node _T_1128 = bits(_T_1127, 0, 0) @[dec_tlu_ctl.scala 2290:62] + node _T_1129 = eq(mhpme_vec[0], UInt<6>("h025")) @[dec_tlu_ctl.scala 2291:34] + node _T_1130 = bits(_T_1129, 0, 0) @[dec_tlu_ctl.scala 2291:62] + node _T_1131 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2291:98] + node _T_1132 = or(_T_1131, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2291:120] + node _T_1133 = eq(mhpme_vec[0], UInt<6>("h026")) @[dec_tlu_ctl.scala 2292:34] + node _T_1134 = bits(_T_1133, 0, 0) @[dec_tlu_ctl.scala 2292:62] + node _T_1135 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2292:92] + node _T_1136 = or(_T_1135, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2292:117] + node _T_1137 = eq(mhpme_vec[0], UInt<6>("h027")) @[dec_tlu_ctl.scala 2293:34] + node _T_1138 = bits(_T_1137, 0, 0) @[dec_tlu_ctl.scala 2293:62] + node _T_1139 = eq(mhpme_vec[0], UInt<6>("h028")) @[dec_tlu_ctl.scala 2294:34] + node _T_1140 = bits(_T_1139, 0, 0) @[dec_tlu_ctl.scala 2294:62] + node _T_1141 = eq(mhpme_vec[0], UInt<6>("h029")) @[dec_tlu_ctl.scala 2295:34] + node _T_1142 = bits(_T_1141, 0, 0) @[dec_tlu_ctl.scala 2295:62] + node _T_1143 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2295:97] + node _T_1144 = and(_T_1143, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2295:129] + node _T_1145 = eq(mhpme_vec[0], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2296:34] + node _T_1146 = bits(_T_1145, 0, 0) @[dec_tlu_ctl.scala 2296:62] + node _T_1147 = eq(mhpme_vec[0], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2297:34] + node _T_1148 = bits(_T_1147, 0, 0) @[dec_tlu_ctl.scala 2297:62] + node _T_1149 = eq(mhpme_vec[0], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2298:34] + node _T_1150 = bits(_T_1149, 0, 0) @[dec_tlu_ctl.scala 2298:62] + node _T_1151 = eq(mhpme_vec[0], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2299:34] + node _T_1152 = bits(_T_1151, 0, 0) @[dec_tlu_ctl.scala 2299:62] + node _T_1153 = eq(mhpme_vec[0], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2300:34] + node _T_1154 = bits(_T_1153, 0, 0) @[dec_tlu_ctl.scala 2300:62] + node _T_1155 = eq(mhpme_vec[0], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2301:34] + node _T_1156 = bits(_T_1155, 0, 0) @[dec_tlu_ctl.scala 2301:62] + node _T_1157 = eq(mhpme_vec[0], UInt<6>("h030")) @[dec_tlu_ctl.scala 2302:34] + node _T_1158 = bits(_T_1157, 0, 0) @[dec_tlu_ctl.scala 2302:62] + node _T_1159 = eq(mhpme_vec[0], UInt<6>("h031")) @[dec_tlu_ctl.scala 2303:34] + node _T_1160 = bits(_T_1159, 0, 0) @[dec_tlu_ctl.scala 2303:62] + node _T_1161 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2303:84] + node _T_1162 = bits(_T_1161, 0, 0) @[dec_tlu_ctl.scala 2303:84] + node _T_1163 = not(_T_1162) @[dec_tlu_ctl.scala 2303:73] + node _T_1164 = eq(mhpme_vec[0], UInt<6>("h032")) @[dec_tlu_ctl.scala 2304:34] + node _T_1165 = bits(_T_1164, 0, 0) @[dec_tlu_ctl.scala 2304:62] + node _T_1166 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2304:84] + node _T_1167 = bits(_T_1166, 0, 0) @[dec_tlu_ctl.scala 2304:84] + node _T_1168 = not(_T_1167) @[dec_tlu_ctl.scala 2304:73] + node _T_1169 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2304:107] + node _T_1170 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2304:118] + node _T_1171 = and(_T_1169, _T_1170) @[dec_tlu_ctl.scala 2304:113] + node _T_1172 = orr(_T_1171) @[dec_tlu_ctl.scala 2304:125] + node _T_1173 = and(_T_1168, _T_1172) @[dec_tlu_ctl.scala 2304:98] + node _T_1174 = eq(mhpme_vec[0], UInt<6>("h036")) @[dec_tlu_ctl.scala 2305:34] + node _T_1175 = bits(_T_1174, 0, 0) @[dec_tlu_ctl.scala 2305:62] + node _T_1176 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2305:91] + node _T_1177 = eq(mhpme_vec[0], UInt<6>("h037")) @[dec_tlu_ctl.scala 2306:34] + node _T_1178 = bits(_T_1177, 0, 0) @[dec_tlu_ctl.scala 2306:62] + node _T_1179 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2306:94] + node _T_1180 = eq(mhpme_vec[0], UInt<6>("h038")) @[dec_tlu_ctl.scala 2307:34] + node _T_1181 = bits(_T_1180, 0, 0) @[dec_tlu_ctl.scala 2307:62] + node _T_1182 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2307:94] + node _T_1183 = eq(mhpme_vec[0], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2309:34] + node _T_1184 = bits(_T_1183, 0, 0) @[dec_tlu_ctl.scala 2309:62] + node _T_1185 = eq(mhpme_vec[0], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2310:34] + node _T_1186 = bits(_T_1185, 0, 0) @[dec_tlu_ctl.scala 2310:62] + node _T_1187 = eq(mhpme_vec[0], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2311:34] + node _T_1188 = bits(_T_1187, 0, 0) @[dec_tlu_ctl.scala 2311:62] + node _T_1189 = eq(mhpme_vec[0], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2312:34] + node _T_1190 = bits(_T_1189, 0, 0) @[dec_tlu_ctl.scala 2312:62] + node _T_1191 = eq(mhpme_vec[0], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2313:34] + node _T_1192 = bits(_T_1191, 0, 0) @[dec_tlu_ctl.scala 2313:62] + node _T_1193 = mux(_T_1027, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1194 = mux(_T_1029, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1195 = mux(_T_1031, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1196 = mux(_T_1033, _T_1035, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1197 = mux(_T_1037, _T_1041, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1198 = mux(_T_1043, _T_1046, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1199 = mux(_T_1048, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1200 = mux(_T_1050, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1201 = mux(_T_1052, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1202 = mux(_T_1054, _T_1055, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1203 = mux(_T_1057, _T_1058, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1204 = mux(_T_1060, _T_1061, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1205 = mux(_T_1063, _T_1064, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1206 = mux(_T_1066, _T_1068, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1207 = mux(_T_1070, _T_1073, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1208 = mux(_T_1075, _T_1076, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1209 = mux(_T_1078, _T_1079, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1210 = mux(_T_1081, _T_1082, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1211 = mux(_T_1084, _T_1085, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1212 = mux(_T_1087, _T_1088, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1213 = mux(_T_1090, _T_1091, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1214 = mux(_T_1093, _T_1094, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1215 = mux(_T_1096, _T_1097, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1216 = mux(_T_1099, _T_1100, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1217 = mux(_T_1102, _T_1105, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1218 = mux(_T_1107, _T_1108, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1219 = mux(_T_1110, _T_1111, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1220 = mux(_T_1113, _T_1114, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1221 = mux(_T_1116, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1222 = mux(_T_1118, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1223 = mux(_T_1120, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1224 = mux(_T_1122, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1225 = mux(_T_1124, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1226 = mux(_T_1126, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1227 = mux(_T_1128, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1228 = mux(_T_1130, _T_1132, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1229 = mux(_T_1134, _T_1136, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1230 = mux(_T_1138, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1231 = mux(_T_1140, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1232 = mux(_T_1142, _T_1144, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1233 = mux(_T_1146, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1234 = mux(_T_1148, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1235 = mux(_T_1150, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1236 = mux(_T_1152, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1237 = mux(_T_1154, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1238 = mux(_T_1156, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1239 = mux(_T_1158, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1240 = mux(_T_1160, _T_1163, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1241 = mux(_T_1165, _T_1173, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1242 = mux(_T_1175, _T_1176, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1243 = mux(_T_1178, _T_1179, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1244 = mux(_T_1181, _T_1182, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1245 = mux(_T_1184, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1246 = mux(_T_1186, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1247 = mux(_T_1188, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1248 = mux(_T_1190, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1249 = mux(_T_1192, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1250 = or(_T_1193, _T_1194) @[Mux.scala 27:72] node _T_1251 = or(_T_1250, _T_1195) @[Mux.scala 27:72] node _T_1252 = or(_T_1251, _T_1196) @[Mux.scala 27:72] node _T_1253 = or(_T_1252, _T_1197) @[Mux.scala 27:72] @@ -74622,247 +74622,247 @@ circuit quasar : node _T_1293 = or(_T_1292, _T_1237) @[Mux.scala 27:72] node _T_1294 = or(_T_1293, _T_1238) @[Mux.scala 27:72] node _T_1295 = or(_T_1294, _T_1239) @[Mux.scala 27:72] - wire _T_1296 : UInt<1> @[Mux.scala 27:72] - _T_1296 <= _T_1295 @[Mux.scala 27:72] - node _T_1297 = and(_T_1015, _T_1296) @[dec_tlu_ctl.scala 2255:44] - mhpmc_inc_r[0] <= _T_1297 @[dec_tlu_ctl.scala 2255:19] - node _T_1298 = bits(mcountinhibit, 4, 4) @[dec_tlu_ctl.scala 2255:38] - node _T_1299 = not(_T_1298) @[dec_tlu_ctl.scala 2255:24] - node _T_1300 = eq(mhpme_vec[1], UInt<1>("h01")) @[dec_tlu_ctl.scala 2256:34] - node _T_1301 = bits(_T_1300, 0, 0) @[dec_tlu_ctl.scala 2256:62] - node _T_1302 = eq(mhpme_vec[1], UInt<2>("h02")) @[dec_tlu_ctl.scala 2257:34] - node _T_1303 = bits(_T_1302, 0, 0) @[dec_tlu_ctl.scala 2257:62] - node _T_1304 = eq(mhpme_vec[1], UInt<2>("h03")) @[dec_tlu_ctl.scala 2258:34] - node _T_1305 = bits(_T_1304, 0, 0) @[dec_tlu_ctl.scala 2258:62] - node _T_1306 = eq(mhpme_vec[1], UInt<3>("h04")) @[dec_tlu_ctl.scala 2259:34] - node _T_1307 = bits(_T_1306, 0, 0) @[dec_tlu_ctl.scala 2259:62] - node _T_1308 = not(io.illegal_r) @[dec_tlu_ctl.scala 2259:96] - node _T_1309 = and(io.tlu_i0_commit_cmt, _T_1308) @[dec_tlu_ctl.scala 2259:94] - node _T_1310 = eq(mhpme_vec[1], UInt<3>("h05")) @[dec_tlu_ctl.scala 2260:34] - node _T_1311 = bits(_T_1310, 0, 0) @[dec_tlu_ctl.scala 2260:62] - node _T_1312 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2260:96] - node _T_1313 = and(io.tlu_i0_commit_cmt, _T_1312) @[dec_tlu_ctl.scala 2260:94] - node _T_1314 = not(io.illegal_r) @[dec_tlu_ctl.scala 2260:117] - node _T_1315 = and(_T_1313, _T_1314) @[dec_tlu_ctl.scala 2260:115] - node _T_1316 = eq(mhpme_vec[1], UInt<3>("h06")) @[dec_tlu_ctl.scala 2261:34] - node _T_1317 = bits(_T_1316, 0, 0) @[dec_tlu_ctl.scala 2261:62] - node _T_1318 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2261:94] - node _T_1319 = not(io.illegal_r) @[dec_tlu_ctl.scala 2261:117] - node _T_1320 = and(_T_1318, _T_1319) @[dec_tlu_ctl.scala 2261:115] - node _T_1321 = eq(mhpme_vec[1], UInt<3>("h07")) @[dec_tlu_ctl.scala 2262:34] - node _T_1322 = bits(_T_1321, 0, 0) @[dec_tlu_ctl.scala 2262:62] - node _T_1323 = eq(mhpme_vec[1], UInt<4>("h08")) @[dec_tlu_ctl.scala 2263:34] - node _T_1324 = bits(_T_1323, 0, 0) @[dec_tlu_ctl.scala 2263:62] - node _T_1325 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2264:34] - node _T_1326 = bits(_T_1325, 0, 0) @[dec_tlu_ctl.scala 2264:62] - node _T_1327 = eq(mhpme_vec[1], UInt<4>("h09")) @[dec_tlu_ctl.scala 2265:34] - node _T_1328 = bits(_T_1327, 0, 0) @[dec_tlu_ctl.scala 2265:62] - node _T_1329 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2265:91] - node _T_1330 = eq(mhpme_vec[1], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2266:34] - node _T_1331 = bits(_T_1330, 0, 0) @[dec_tlu_ctl.scala 2266:62] - node _T_1332 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2266:105] - node _T_1333 = eq(mhpme_vec[1], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2267:34] - node _T_1334 = bits(_T_1333, 0, 0) @[dec_tlu_ctl.scala 2267:62] - node _T_1335 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2267:91] - node _T_1336 = eq(mhpme_vec[1], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2268:34] - node _T_1337 = bits(_T_1336, 0, 0) @[dec_tlu_ctl.scala 2268:62] - node _T_1338 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2268:91] - node _T_1339 = eq(mhpme_vec[1], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2269:34] - node _T_1340 = bits(_T_1339, 0, 0) @[dec_tlu_ctl.scala 2269:62] - node _T_1341 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2269:91] - node _T_1342 = and(_T_1341, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2269:100] - node _T_1343 = eq(mhpme_vec[1], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2270:34] - node _T_1344 = bits(_T_1343, 0, 0) @[dec_tlu_ctl.scala 2270:62] - node _T_1345 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2270:91] - node _T_1346 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2270:142] - node _T_1347 = and(_T_1345, _T_1346) @[dec_tlu_ctl.scala 2270:101] - node _T_1348 = eq(mhpme_vec[1], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2271:34] - node _T_1349 = bits(_T_1348, 0, 0) @[dec_tlu_ctl.scala 2271:59] - node _T_1350 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2271:89] - node _T_1351 = eq(mhpme_vec[1], UInt<5>("h010")) @[dec_tlu_ctl.scala 2272:34] - node _T_1352 = bits(_T_1351, 0, 0) @[dec_tlu_ctl.scala 2272:59] - node _T_1353 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2272:89] - node _T_1354 = eq(mhpme_vec[1], UInt<5>("h012")) @[dec_tlu_ctl.scala 2273:34] - node _T_1355 = bits(_T_1354, 0, 0) @[dec_tlu_ctl.scala 2273:59] - node _T_1356 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2273:89] - node _T_1357 = eq(mhpme_vec[1], UInt<5>("h011")) @[dec_tlu_ctl.scala 2274:34] - node _T_1358 = bits(_T_1357, 0, 0) @[dec_tlu_ctl.scala 2274:59] - node _T_1359 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2274:89] - node _T_1360 = eq(mhpme_vec[1], UInt<5>("h013")) @[dec_tlu_ctl.scala 2275:34] - node _T_1361 = bits(_T_1360, 0, 0) @[dec_tlu_ctl.scala 2275:59] - node _T_1362 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2275:89] - node _T_1363 = eq(mhpme_vec[1], UInt<5>("h014")) @[dec_tlu_ctl.scala 2276:34] - node _T_1364 = bits(_T_1363, 0, 0) @[dec_tlu_ctl.scala 2276:59] - node _T_1365 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2276:89] - node _T_1366 = eq(mhpme_vec[1], UInt<5>("h015")) @[dec_tlu_ctl.scala 2277:34] - node _T_1367 = bits(_T_1366, 0, 0) @[dec_tlu_ctl.scala 2277:59] - node _T_1368 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2277:89] - node _T_1369 = eq(mhpme_vec[1], UInt<5>("h016")) @[dec_tlu_ctl.scala 2278:34] - node _T_1370 = bits(_T_1369, 0, 0) @[dec_tlu_ctl.scala 2278:59] - node _T_1371 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2278:89] - node _T_1372 = eq(mhpme_vec[1], UInt<5>("h017")) @[dec_tlu_ctl.scala 2279:34] - node _T_1373 = bits(_T_1372, 0, 0) @[dec_tlu_ctl.scala 2279:59] - node _T_1374 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2279:89] - node _T_1375 = eq(mhpme_vec[1], UInt<5>("h018")) @[dec_tlu_ctl.scala 2280:34] - node _T_1376 = bits(_T_1375, 0, 0) @[dec_tlu_ctl.scala 2280:59] - node _T_1377 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2280:89] - node _T_1378 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2280:122] - node _T_1379 = or(_T_1377, _T_1378) @[dec_tlu_ctl.scala 2280:101] - node _T_1380 = eq(mhpme_vec[1], UInt<5>("h019")) @[dec_tlu_ctl.scala 2281:34] - node _T_1381 = bits(_T_1380, 0, 0) @[dec_tlu_ctl.scala 2281:62] - node _T_1382 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2281:95] - node _T_1383 = eq(mhpme_vec[1], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2282:34] - node _T_1384 = bits(_T_1383, 0, 0) @[dec_tlu_ctl.scala 2282:62] - node _T_1385 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2282:97] - node _T_1386 = eq(mhpme_vec[1], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2283:34] - node _T_1387 = bits(_T_1386, 0, 0) @[dec_tlu_ctl.scala 2283:62] - node _T_1388 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2283:110] - node _T_1389 = eq(mhpme_vec[1], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2284:34] - node _T_1390 = bits(_T_1389, 0, 0) @[dec_tlu_ctl.scala 2284:62] - node _T_1391 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2285:34] - node _T_1392 = bits(_T_1391, 0, 0) @[dec_tlu_ctl.scala 2285:62] - node _T_1393 = eq(mhpme_vec[1], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2286:34] - node _T_1394 = bits(_T_1393, 0, 0) @[dec_tlu_ctl.scala 2286:62] - node _T_1395 = eq(mhpme_vec[1], UInt<6>("h020")) @[dec_tlu_ctl.scala 2287:34] - node _T_1396 = bits(_T_1395, 0, 0) @[dec_tlu_ctl.scala 2287:62] - node _T_1397 = eq(mhpme_vec[1], UInt<6>("h022")) @[dec_tlu_ctl.scala 2288:34] - node _T_1398 = bits(_T_1397, 0, 0) @[dec_tlu_ctl.scala 2288:62] - node _T_1399 = eq(mhpme_vec[1], UInt<6>("h023")) @[dec_tlu_ctl.scala 2289:34] - node _T_1400 = bits(_T_1399, 0, 0) @[dec_tlu_ctl.scala 2289:62] - node _T_1401 = eq(mhpme_vec[1], UInt<6>("h024")) @[dec_tlu_ctl.scala 2290:34] - node _T_1402 = bits(_T_1401, 0, 0) @[dec_tlu_ctl.scala 2290:62] - node _T_1403 = eq(mhpme_vec[1], UInt<6>("h025")) @[dec_tlu_ctl.scala 2291:34] - node _T_1404 = bits(_T_1403, 0, 0) @[dec_tlu_ctl.scala 2291:62] - node _T_1405 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2291:98] - node _T_1406 = or(_T_1405, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2291:120] - node _T_1407 = eq(mhpme_vec[1], UInt<6>("h026")) @[dec_tlu_ctl.scala 2292:34] - node _T_1408 = bits(_T_1407, 0, 0) @[dec_tlu_ctl.scala 2292:62] - node _T_1409 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2292:92] - node _T_1410 = or(_T_1409, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2292:117] - node _T_1411 = eq(mhpme_vec[1], UInt<6>("h027")) @[dec_tlu_ctl.scala 2293:34] - node _T_1412 = bits(_T_1411, 0, 0) @[dec_tlu_ctl.scala 2293:62] - node _T_1413 = eq(mhpme_vec[1], UInt<6>("h028")) @[dec_tlu_ctl.scala 2294:34] - node _T_1414 = bits(_T_1413, 0, 0) @[dec_tlu_ctl.scala 2294:62] - node _T_1415 = eq(mhpme_vec[1], UInt<6>("h029")) @[dec_tlu_ctl.scala 2295:34] - node _T_1416 = bits(_T_1415, 0, 0) @[dec_tlu_ctl.scala 2295:62] - node _T_1417 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2295:97] - node _T_1418 = and(_T_1417, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2295:129] - node _T_1419 = eq(mhpme_vec[1], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2296:34] - node _T_1420 = bits(_T_1419, 0, 0) @[dec_tlu_ctl.scala 2296:62] - node _T_1421 = eq(mhpme_vec[1], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2297:34] - node _T_1422 = bits(_T_1421, 0, 0) @[dec_tlu_ctl.scala 2297:62] - node _T_1423 = eq(mhpme_vec[1], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2298:34] - node _T_1424 = bits(_T_1423, 0, 0) @[dec_tlu_ctl.scala 2298:62] - node _T_1425 = eq(mhpme_vec[1], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2299:34] - node _T_1426 = bits(_T_1425, 0, 0) @[dec_tlu_ctl.scala 2299:62] - node _T_1427 = eq(mhpme_vec[1], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2300:34] - node _T_1428 = bits(_T_1427, 0, 0) @[dec_tlu_ctl.scala 2300:62] - node _T_1429 = eq(mhpme_vec[1], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2301:34] - node _T_1430 = bits(_T_1429, 0, 0) @[dec_tlu_ctl.scala 2301:62] - node _T_1431 = eq(mhpme_vec[1], UInt<6>("h030")) @[dec_tlu_ctl.scala 2302:34] - node _T_1432 = bits(_T_1431, 0, 0) @[dec_tlu_ctl.scala 2302:62] - node _T_1433 = eq(mhpme_vec[1], UInt<6>("h031")) @[dec_tlu_ctl.scala 2303:34] - node _T_1434 = bits(_T_1433, 0, 0) @[dec_tlu_ctl.scala 2303:62] - node _T_1435 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2303:84] - node _T_1436 = bits(_T_1435, 0, 0) @[dec_tlu_ctl.scala 2303:84] - node _T_1437 = not(_T_1436) @[dec_tlu_ctl.scala 2303:73] - node _T_1438 = eq(mhpme_vec[1], UInt<6>("h032")) @[dec_tlu_ctl.scala 2304:34] - node _T_1439 = bits(_T_1438, 0, 0) @[dec_tlu_ctl.scala 2304:62] - node _T_1440 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2304:84] - node _T_1441 = bits(_T_1440, 0, 0) @[dec_tlu_ctl.scala 2304:84] - node _T_1442 = not(_T_1441) @[dec_tlu_ctl.scala 2304:73] - node _T_1443 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2304:107] - node _T_1444 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2304:118] - node _T_1445 = and(_T_1443, _T_1444) @[dec_tlu_ctl.scala 2304:113] - node _T_1446 = orr(_T_1445) @[dec_tlu_ctl.scala 2304:125] - node _T_1447 = and(_T_1442, _T_1446) @[dec_tlu_ctl.scala 2304:98] - node _T_1448 = eq(mhpme_vec[1], UInt<6>("h036")) @[dec_tlu_ctl.scala 2305:34] - node _T_1449 = bits(_T_1448, 0, 0) @[dec_tlu_ctl.scala 2305:62] - node _T_1450 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2305:91] - node _T_1451 = eq(mhpme_vec[1], UInt<6>("h037")) @[dec_tlu_ctl.scala 2306:34] - node _T_1452 = bits(_T_1451, 0, 0) @[dec_tlu_ctl.scala 2306:62] - node _T_1453 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2306:94] - node _T_1454 = eq(mhpme_vec[1], UInt<6>("h038")) @[dec_tlu_ctl.scala 2307:34] - node _T_1455 = bits(_T_1454, 0, 0) @[dec_tlu_ctl.scala 2307:62] - node _T_1456 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2307:94] - node _T_1457 = eq(mhpme_vec[1], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2309:34] - node _T_1458 = bits(_T_1457, 0, 0) @[dec_tlu_ctl.scala 2309:62] - node _T_1459 = eq(mhpme_vec[1], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2310:34] - node _T_1460 = bits(_T_1459, 0, 0) @[dec_tlu_ctl.scala 2310:62] - node _T_1461 = eq(mhpme_vec[1], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2311:34] - node _T_1462 = bits(_T_1461, 0, 0) @[dec_tlu_ctl.scala 2311:62] - node _T_1463 = eq(mhpme_vec[1], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2312:34] - node _T_1464 = bits(_T_1463, 0, 0) @[dec_tlu_ctl.scala 2312:62] - node _T_1465 = eq(mhpme_vec[1], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2313:34] - node _T_1466 = bits(_T_1465, 0, 0) @[dec_tlu_ctl.scala 2313:62] - node _T_1467 = mux(_T_1301, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1468 = mux(_T_1303, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1469 = mux(_T_1305, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1470 = mux(_T_1307, _T_1309, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1471 = mux(_T_1311, _T_1315, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1472 = mux(_T_1317, _T_1320, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1473 = mux(_T_1322, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1474 = mux(_T_1324, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1475 = mux(_T_1326, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1476 = mux(_T_1328, _T_1329, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1477 = mux(_T_1331, _T_1332, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1478 = mux(_T_1334, _T_1335, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1479 = mux(_T_1337, _T_1338, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1480 = mux(_T_1340, _T_1342, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1481 = mux(_T_1344, _T_1347, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1482 = mux(_T_1349, _T_1350, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1483 = mux(_T_1352, _T_1353, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1484 = mux(_T_1355, _T_1356, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1485 = mux(_T_1358, _T_1359, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1486 = mux(_T_1361, _T_1362, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1487 = mux(_T_1364, _T_1365, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1488 = mux(_T_1367, _T_1368, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1489 = mux(_T_1370, _T_1371, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1490 = mux(_T_1373, _T_1374, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1491 = mux(_T_1376, _T_1379, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1492 = mux(_T_1381, _T_1382, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1493 = mux(_T_1384, _T_1385, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1494 = mux(_T_1387, _T_1388, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1495 = mux(_T_1390, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1496 = mux(_T_1392, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1497 = mux(_T_1394, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1498 = mux(_T_1396, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1499 = mux(_T_1398, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1500 = mux(_T_1400, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1501 = mux(_T_1402, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1502 = mux(_T_1404, _T_1406, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1503 = mux(_T_1408, _T_1410, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1504 = mux(_T_1412, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1505 = mux(_T_1414, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1506 = mux(_T_1416, _T_1418, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1507 = mux(_T_1420, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1508 = mux(_T_1422, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1509 = mux(_T_1424, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1510 = mux(_T_1426, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1511 = mux(_T_1428, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1512 = mux(_T_1430, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1513 = mux(_T_1432, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1514 = mux(_T_1434, _T_1437, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1515 = mux(_T_1439, _T_1447, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1516 = mux(_T_1449, _T_1450, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1517 = mux(_T_1452, _T_1453, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1518 = mux(_T_1455, _T_1456, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1519 = mux(_T_1458, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1520 = mux(_T_1460, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1521 = mux(_T_1462, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1522 = mux(_T_1464, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1523 = mux(_T_1466, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1524 = or(_T_1467, _T_1468) @[Mux.scala 27:72] - node _T_1525 = or(_T_1524, _T_1469) @[Mux.scala 27:72] - node _T_1526 = or(_T_1525, _T_1470) @[Mux.scala 27:72] - node _T_1527 = or(_T_1526, _T_1471) @[Mux.scala 27:72] - node _T_1528 = or(_T_1527, _T_1472) @[Mux.scala 27:72] - node _T_1529 = or(_T_1528, _T_1473) @[Mux.scala 27:72] - node _T_1530 = or(_T_1529, _T_1474) @[Mux.scala 27:72] - node _T_1531 = or(_T_1530, _T_1475) @[Mux.scala 27:72] - node _T_1532 = or(_T_1531, _T_1476) @[Mux.scala 27:72] - node _T_1533 = or(_T_1532, _T_1477) @[Mux.scala 27:72] - node _T_1534 = or(_T_1533, _T_1478) @[Mux.scala 27:72] + node _T_1296 = or(_T_1295, _T_1240) @[Mux.scala 27:72] + node _T_1297 = or(_T_1296, _T_1241) @[Mux.scala 27:72] + node _T_1298 = or(_T_1297, _T_1242) @[Mux.scala 27:72] + node _T_1299 = or(_T_1298, _T_1243) @[Mux.scala 27:72] + node _T_1300 = or(_T_1299, _T_1244) @[Mux.scala 27:72] + node _T_1301 = or(_T_1300, _T_1245) @[Mux.scala 27:72] + node _T_1302 = or(_T_1301, _T_1246) @[Mux.scala 27:72] + node _T_1303 = or(_T_1302, _T_1247) @[Mux.scala 27:72] + node _T_1304 = or(_T_1303, _T_1248) @[Mux.scala 27:72] + node _T_1305 = or(_T_1304, _T_1249) @[Mux.scala 27:72] + wire _T_1306 : UInt<1> @[Mux.scala 27:72] + _T_1306 <= _T_1305 @[Mux.scala 27:72] + node _T_1307 = and(_T_1025, _T_1306) @[dec_tlu_ctl.scala 2255:44] + mhpmc_inc_r[0] <= _T_1307 @[dec_tlu_ctl.scala 2255:19] + node _T_1308 = bits(mcountinhibit, 4, 4) @[dec_tlu_ctl.scala 2255:38] + node _T_1309 = not(_T_1308) @[dec_tlu_ctl.scala 2255:24] + node _T_1310 = eq(mhpme_vec[1], UInt<1>("h01")) @[dec_tlu_ctl.scala 2256:34] + node _T_1311 = bits(_T_1310, 0, 0) @[dec_tlu_ctl.scala 2256:62] + node _T_1312 = eq(mhpme_vec[1], UInt<2>("h02")) @[dec_tlu_ctl.scala 2257:34] + node _T_1313 = bits(_T_1312, 0, 0) @[dec_tlu_ctl.scala 2257:62] + node _T_1314 = eq(mhpme_vec[1], UInt<2>("h03")) @[dec_tlu_ctl.scala 2258:34] + node _T_1315 = bits(_T_1314, 0, 0) @[dec_tlu_ctl.scala 2258:62] + node _T_1316 = eq(mhpme_vec[1], UInt<3>("h04")) @[dec_tlu_ctl.scala 2259:34] + node _T_1317 = bits(_T_1316, 0, 0) @[dec_tlu_ctl.scala 2259:62] + node _T_1318 = not(io.illegal_r) @[dec_tlu_ctl.scala 2259:96] + node _T_1319 = and(io.tlu_i0_commit_cmt, _T_1318) @[dec_tlu_ctl.scala 2259:94] + node _T_1320 = eq(mhpme_vec[1], UInt<3>("h05")) @[dec_tlu_ctl.scala 2260:34] + node _T_1321 = bits(_T_1320, 0, 0) @[dec_tlu_ctl.scala 2260:62] + node _T_1322 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2260:96] + node _T_1323 = and(io.tlu_i0_commit_cmt, _T_1322) @[dec_tlu_ctl.scala 2260:94] + node _T_1324 = not(io.illegal_r) @[dec_tlu_ctl.scala 2260:117] + node _T_1325 = and(_T_1323, _T_1324) @[dec_tlu_ctl.scala 2260:115] + node _T_1326 = eq(mhpme_vec[1], UInt<3>("h06")) @[dec_tlu_ctl.scala 2261:34] + node _T_1327 = bits(_T_1326, 0, 0) @[dec_tlu_ctl.scala 2261:62] + node _T_1328 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2261:94] + node _T_1329 = not(io.illegal_r) @[dec_tlu_ctl.scala 2261:117] + node _T_1330 = and(_T_1328, _T_1329) @[dec_tlu_ctl.scala 2261:115] + node _T_1331 = eq(mhpme_vec[1], UInt<3>("h07")) @[dec_tlu_ctl.scala 2262:34] + node _T_1332 = bits(_T_1331, 0, 0) @[dec_tlu_ctl.scala 2262:62] + node _T_1333 = eq(mhpme_vec[1], UInt<4>("h08")) @[dec_tlu_ctl.scala 2263:34] + node _T_1334 = bits(_T_1333, 0, 0) @[dec_tlu_ctl.scala 2263:62] + node _T_1335 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2264:34] + node _T_1336 = bits(_T_1335, 0, 0) @[dec_tlu_ctl.scala 2264:62] + node _T_1337 = eq(mhpme_vec[1], UInt<4>("h09")) @[dec_tlu_ctl.scala 2265:34] + node _T_1338 = bits(_T_1337, 0, 0) @[dec_tlu_ctl.scala 2265:62] + node _T_1339 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2265:91] + node _T_1340 = eq(mhpme_vec[1], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2266:34] + node _T_1341 = bits(_T_1340, 0, 0) @[dec_tlu_ctl.scala 2266:62] + node _T_1342 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2266:105] + node _T_1343 = eq(mhpme_vec[1], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2267:34] + node _T_1344 = bits(_T_1343, 0, 0) @[dec_tlu_ctl.scala 2267:62] + node _T_1345 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2267:91] + node _T_1346 = eq(mhpme_vec[1], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2268:34] + node _T_1347 = bits(_T_1346, 0, 0) @[dec_tlu_ctl.scala 2268:62] + node _T_1348 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2268:91] + node _T_1349 = eq(mhpme_vec[1], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2269:34] + node _T_1350 = bits(_T_1349, 0, 0) @[dec_tlu_ctl.scala 2269:62] + node _T_1351 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2269:91] + node _T_1352 = and(_T_1351, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2269:100] + node _T_1353 = eq(mhpme_vec[1], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2270:34] + node _T_1354 = bits(_T_1353, 0, 0) @[dec_tlu_ctl.scala 2270:62] + node _T_1355 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2270:91] + node _T_1356 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2270:142] + node _T_1357 = and(_T_1355, _T_1356) @[dec_tlu_ctl.scala 2270:101] + node _T_1358 = eq(mhpme_vec[1], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2271:34] + node _T_1359 = bits(_T_1358, 0, 0) @[dec_tlu_ctl.scala 2271:59] + node _T_1360 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2271:89] + node _T_1361 = eq(mhpme_vec[1], UInt<5>("h010")) @[dec_tlu_ctl.scala 2272:34] + node _T_1362 = bits(_T_1361, 0, 0) @[dec_tlu_ctl.scala 2272:59] + node _T_1363 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2272:89] + node _T_1364 = eq(mhpme_vec[1], UInt<5>("h012")) @[dec_tlu_ctl.scala 2273:34] + node _T_1365 = bits(_T_1364, 0, 0) @[dec_tlu_ctl.scala 2273:59] + node _T_1366 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2273:89] + node _T_1367 = eq(mhpme_vec[1], UInt<5>("h011")) @[dec_tlu_ctl.scala 2274:34] + node _T_1368 = bits(_T_1367, 0, 0) @[dec_tlu_ctl.scala 2274:59] + node _T_1369 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2274:89] + node _T_1370 = eq(mhpme_vec[1], UInt<5>("h013")) @[dec_tlu_ctl.scala 2275:34] + node _T_1371 = bits(_T_1370, 0, 0) @[dec_tlu_ctl.scala 2275:59] + node _T_1372 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2275:89] + node _T_1373 = eq(mhpme_vec[1], UInt<5>("h014")) @[dec_tlu_ctl.scala 2276:34] + node _T_1374 = bits(_T_1373, 0, 0) @[dec_tlu_ctl.scala 2276:59] + node _T_1375 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2276:89] + node _T_1376 = eq(mhpme_vec[1], UInt<5>("h015")) @[dec_tlu_ctl.scala 2277:34] + node _T_1377 = bits(_T_1376, 0, 0) @[dec_tlu_ctl.scala 2277:59] + node _T_1378 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2277:89] + node _T_1379 = eq(mhpme_vec[1], UInt<5>("h016")) @[dec_tlu_ctl.scala 2278:34] + node _T_1380 = bits(_T_1379, 0, 0) @[dec_tlu_ctl.scala 2278:59] + node _T_1381 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2278:89] + node _T_1382 = eq(mhpme_vec[1], UInt<5>("h017")) @[dec_tlu_ctl.scala 2279:34] + node _T_1383 = bits(_T_1382, 0, 0) @[dec_tlu_ctl.scala 2279:59] + node _T_1384 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2279:89] + node _T_1385 = eq(mhpme_vec[1], UInt<5>("h018")) @[dec_tlu_ctl.scala 2280:34] + node _T_1386 = bits(_T_1385, 0, 0) @[dec_tlu_ctl.scala 2280:59] + node _T_1387 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2280:89] + node _T_1388 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2280:122] + node _T_1389 = or(_T_1387, _T_1388) @[dec_tlu_ctl.scala 2280:101] + node _T_1390 = eq(mhpme_vec[1], UInt<5>("h019")) @[dec_tlu_ctl.scala 2281:34] + node _T_1391 = bits(_T_1390, 0, 0) @[dec_tlu_ctl.scala 2281:62] + node _T_1392 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2281:95] + node _T_1393 = eq(mhpme_vec[1], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2282:34] + node _T_1394 = bits(_T_1393, 0, 0) @[dec_tlu_ctl.scala 2282:62] + node _T_1395 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2282:97] + node _T_1396 = eq(mhpme_vec[1], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2283:34] + node _T_1397 = bits(_T_1396, 0, 0) @[dec_tlu_ctl.scala 2283:62] + node _T_1398 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2283:110] + node _T_1399 = eq(mhpme_vec[1], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2284:34] + node _T_1400 = bits(_T_1399, 0, 0) @[dec_tlu_ctl.scala 2284:62] + node _T_1401 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2285:34] + node _T_1402 = bits(_T_1401, 0, 0) @[dec_tlu_ctl.scala 2285:62] + node _T_1403 = eq(mhpme_vec[1], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2286:34] + node _T_1404 = bits(_T_1403, 0, 0) @[dec_tlu_ctl.scala 2286:62] + node _T_1405 = eq(mhpme_vec[1], UInt<6>("h020")) @[dec_tlu_ctl.scala 2287:34] + node _T_1406 = bits(_T_1405, 0, 0) @[dec_tlu_ctl.scala 2287:62] + node _T_1407 = eq(mhpme_vec[1], UInt<6>("h022")) @[dec_tlu_ctl.scala 2288:34] + node _T_1408 = bits(_T_1407, 0, 0) @[dec_tlu_ctl.scala 2288:62] + node _T_1409 = eq(mhpme_vec[1], UInt<6>("h023")) @[dec_tlu_ctl.scala 2289:34] + node _T_1410 = bits(_T_1409, 0, 0) @[dec_tlu_ctl.scala 2289:62] + node _T_1411 = eq(mhpme_vec[1], UInt<6>("h024")) @[dec_tlu_ctl.scala 2290:34] + node _T_1412 = bits(_T_1411, 0, 0) @[dec_tlu_ctl.scala 2290:62] + node _T_1413 = eq(mhpme_vec[1], UInt<6>("h025")) @[dec_tlu_ctl.scala 2291:34] + node _T_1414 = bits(_T_1413, 0, 0) @[dec_tlu_ctl.scala 2291:62] + node _T_1415 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2291:98] + node _T_1416 = or(_T_1415, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2291:120] + node _T_1417 = eq(mhpme_vec[1], UInt<6>("h026")) @[dec_tlu_ctl.scala 2292:34] + node _T_1418 = bits(_T_1417, 0, 0) @[dec_tlu_ctl.scala 2292:62] + node _T_1419 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2292:92] + node _T_1420 = or(_T_1419, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2292:117] + node _T_1421 = eq(mhpme_vec[1], UInt<6>("h027")) @[dec_tlu_ctl.scala 2293:34] + node _T_1422 = bits(_T_1421, 0, 0) @[dec_tlu_ctl.scala 2293:62] + node _T_1423 = eq(mhpme_vec[1], UInt<6>("h028")) @[dec_tlu_ctl.scala 2294:34] + node _T_1424 = bits(_T_1423, 0, 0) @[dec_tlu_ctl.scala 2294:62] + node _T_1425 = eq(mhpme_vec[1], UInt<6>("h029")) @[dec_tlu_ctl.scala 2295:34] + node _T_1426 = bits(_T_1425, 0, 0) @[dec_tlu_ctl.scala 2295:62] + node _T_1427 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2295:97] + node _T_1428 = and(_T_1427, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2295:129] + node _T_1429 = eq(mhpme_vec[1], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2296:34] + node _T_1430 = bits(_T_1429, 0, 0) @[dec_tlu_ctl.scala 2296:62] + node _T_1431 = eq(mhpme_vec[1], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2297:34] + node _T_1432 = bits(_T_1431, 0, 0) @[dec_tlu_ctl.scala 2297:62] + node _T_1433 = eq(mhpme_vec[1], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2298:34] + node _T_1434 = bits(_T_1433, 0, 0) @[dec_tlu_ctl.scala 2298:62] + node _T_1435 = eq(mhpme_vec[1], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2299:34] + node _T_1436 = bits(_T_1435, 0, 0) @[dec_tlu_ctl.scala 2299:62] + node _T_1437 = eq(mhpme_vec[1], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2300:34] + node _T_1438 = bits(_T_1437, 0, 0) @[dec_tlu_ctl.scala 2300:62] + node _T_1439 = eq(mhpme_vec[1], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2301:34] + node _T_1440 = bits(_T_1439, 0, 0) @[dec_tlu_ctl.scala 2301:62] + node _T_1441 = eq(mhpme_vec[1], UInt<6>("h030")) @[dec_tlu_ctl.scala 2302:34] + node _T_1442 = bits(_T_1441, 0, 0) @[dec_tlu_ctl.scala 2302:62] + node _T_1443 = eq(mhpme_vec[1], UInt<6>("h031")) @[dec_tlu_ctl.scala 2303:34] + node _T_1444 = bits(_T_1443, 0, 0) @[dec_tlu_ctl.scala 2303:62] + node _T_1445 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2303:84] + node _T_1446 = bits(_T_1445, 0, 0) @[dec_tlu_ctl.scala 2303:84] + node _T_1447 = not(_T_1446) @[dec_tlu_ctl.scala 2303:73] + node _T_1448 = eq(mhpme_vec[1], UInt<6>("h032")) @[dec_tlu_ctl.scala 2304:34] + node _T_1449 = bits(_T_1448, 0, 0) @[dec_tlu_ctl.scala 2304:62] + node _T_1450 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2304:84] + node _T_1451 = bits(_T_1450, 0, 0) @[dec_tlu_ctl.scala 2304:84] + node _T_1452 = not(_T_1451) @[dec_tlu_ctl.scala 2304:73] + node _T_1453 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2304:107] + node _T_1454 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2304:118] + node _T_1455 = and(_T_1453, _T_1454) @[dec_tlu_ctl.scala 2304:113] + node _T_1456 = orr(_T_1455) @[dec_tlu_ctl.scala 2304:125] + node _T_1457 = and(_T_1452, _T_1456) @[dec_tlu_ctl.scala 2304:98] + node _T_1458 = eq(mhpme_vec[1], UInt<6>("h036")) @[dec_tlu_ctl.scala 2305:34] + node _T_1459 = bits(_T_1458, 0, 0) @[dec_tlu_ctl.scala 2305:62] + node _T_1460 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2305:91] + node _T_1461 = eq(mhpme_vec[1], UInt<6>("h037")) @[dec_tlu_ctl.scala 2306:34] + node _T_1462 = bits(_T_1461, 0, 0) @[dec_tlu_ctl.scala 2306:62] + node _T_1463 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2306:94] + node _T_1464 = eq(mhpme_vec[1], UInt<6>("h038")) @[dec_tlu_ctl.scala 2307:34] + node _T_1465 = bits(_T_1464, 0, 0) @[dec_tlu_ctl.scala 2307:62] + node _T_1466 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2307:94] + node _T_1467 = eq(mhpme_vec[1], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2309:34] + node _T_1468 = bits(_T_1467, 0, 0) @[dec_tlu_ctl.scala 2309:62] + node _T_1469 = eq(mhpme_vec[1], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2310:34] + node _T_1470 = bits(_T_1469, 0, 0) @[dec_tlu_ctl.scala 2310:62] + node _T_1471 = eq(mhpme_vec[1], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2311:34] + node _T_1472 = bits(_T_1471, 0, 0) @[dec_tlu_ctl.scala 2311:62] + node _T_1473 = eq(mhpme_vec[1], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2312:34] + node _T_1474 = bits(_T_1473, 0, 0) @[dec_tlu_ctl.scala 2312:62] + node _T_1475 = eq(mhpme_vec[1], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2313:34] + node _T_1476 = bits(_T_1475, 0, 0) @[dec_tlu_ctl.scala 2313:62] + node _T_1477 = mux(_T_1311, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1478 = mux(_T_1313, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1479 = mux(_T_1315, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1480 = mux(_T_1317, _T_1319, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1481 = mux(_T_1321, _T_1325, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1482 = mux(_T_1327, _T_1330, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1483 = mux(_T_1332, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1484 = mux(_T_1334, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1485 = mux(_T_1336, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1486 = mux(_T_1338, _T_1339, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1487 = mux(_T_1341, _T_1342, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1488 = mux(_T_1344, _T_1345, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1489 = mux(_T_1347, _T_1348, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1490 = mux(_T_1350, _T_1352, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1491 = mux(_T_1354, _T_1357, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1492 = mux(_T_1359, _T_1360, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1493 = mux(_T_1362, _T_1363, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1494 = mux(_T_1365, _T_1366, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1495 = mux(_T_1368, _T_1369, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1496 = mux(_T_1371, _T_1372, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1497 = mux(_T_1374, _T_1375, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1498 = mux(_T_1377, _T_1378, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1499 = mux(_T_1380, _T_1381, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1500 = mux(_T_1383, _T_1384, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1501 = mux(_T_1386, _T_1389, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1502 = mux(_T_1391, _T_1392, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1503 = mux(_T_1394, _T_1395, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1504 = mux(_T_1397, _T_1398, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1505 = mux(_T_1400, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1506 = mux(_T_1402, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1507 = mux(_T_1404, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1508 = mux(_T_1406, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1509 = mux(_T_1408, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1510 = mux(_T_1410, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1511 = mux(_T_1412, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1512 = mux(_T_1414, _T_1416, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1513 = mux(_T_1418, _T_1420, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1514 = mux(_T_1422, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1515 = mux(_T_1424, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1516 = mux(_T_1426, _T_1428, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1517 = mux(_T_1430, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1518 = mux(_T_1432, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1519 = mux(_T_1434, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1520 = mux(_T_1436, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1521 = mux(_T_1438, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1522 = mux(_T_1440, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1523 = mux(_T_1442, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1524 = mux(_T_1444, _T_1447, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1525 = mux(_T_1449, _T_1457, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1526 = mux(_T_1459, _T_1460, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1527 = mux(_T_1462, _T_1463, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1528 = mux(_T_1465, _T_1466, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1529 = mux(_T_1468, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1530 = mux(_T_1470, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1531 = mux(_T_1472, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1532 = mux(_T_1474, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1533 = mux(_T_1476, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1534 = or(_T_1477, _T_1478) @[Mux.scala 27:72] node _T_1535 = or(_T_1534, _T_1479) @[Mux.scala 27:72] node _T_1536 = or(_T_1535, _T_1480) @[Mux.scala 27:72] node _T_1537 = or(_T_1536, _T_1481) @[Mux.scala 27:72] @@ -74908,247 +74908,247 @@ circuit quasar : node _T_1577 = or(_T_1576, _T_1521) @[Mux.scala 27:72] node _T_1578 = or(_T_1577, _T_1522) @[Mux.scala 27:72] node _T_1579 = or(_T_1578, _T_1523) @[Mux.scala 27:72] - wire _T_1580 : UInt<1> @[Mux.scala 27:72] - _T_1580 <= _T_1579 @[Mux.scala 27:72] - node _T_1581 = and(_T_1299, _T_1580) @[dec_tlu_ctl.scala 2255:44] - mhpmc_inc_r[1] <= _T_1581 @[dec_tlu_ctl.scala 2255:19] - node _T_1582 = bits(mcountinhibit, 5, 5) @[dec_tlu_ctl.scala 2255:38] - node _T_1583 = not(_T_1582) @[dec_tlu_ctl.scala 2255:24] - node _T_1584 = eq(mhpme_vec[2], UInt<1>("h01")) @[dec_tlu_ctl.scala 2256:34] - node _T_1585 = bits(_T_1584, 0, 0) @[dec_tlu_ctl.scala 2256:62] - node _T_1586 = eq(mhpme_vec[2], UInt<2>("h02")) @[dec_tlu_ctl.scala 2257:34] - node _T_1587 = bits(_T_1586, 0, 0) @[dec_tlu_ctl.scala 2257:62] - node _T_1588 = eq(mhpme_vec[2], UInt<2>("h03")) @[dec_tlu_ctl.scala 2258:34] - node _T_1589 = bits(_T_1588, 0, 0) @[dec_tlu_ctl.scala 2258:62] - node _T_1590 = eq(mhpme_vec[2], UInt<3>("h04")) @[dec_tlu_ctl.scala 2259:34] - node _T_1591 = bits(_T_1590, 0, 0) @[dec_tlu_ctl.scala 2259:62] - node _T_1592 = not(io.illegal_r) @[dec_tlu_ctl.scala 2259:96] - node _T_1593 = and(io.tlu_i0_commit_cmt, _T_1592) @[dec_tlu_ctl.scala 2259:94] - node _T_1594 = eq(mhpme_vec[2], UInt<3>("h05")) @[dec_tlu_ctl.scala 2260:34] - node _T_1595 = bits(_T_1594, 0, 0) @[dec_tlu_ctl.scala 2260:62] - node _T_1596 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2260:96] - node _T_1597 = and(io.tlu_i0_commit_cmt, _T_1596) @[dec_tlu_ctl.scala 2260:94] - node _T_1598 = not(io.illegal_r) @[dec_tlu_ctl.scala 2260:117] - node _T_1599 = and(_T_1597, _T_1598) @[dec_tlu_ctl.scala 2260:115] - node _T_1600 = eq(mhpme_vec[2], UInt<3>("h06")) @[dec_tlu_ctl.scala 2261:34] - node _T_1601 = bits(_T_1600, 0, 0) @[dec_tlu_ctl.scala 2261:62] - node _T_1602 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2261:94] - node _T_1603 = not(io.illegal_r) @[dec_tlu_ctl.scala 2261:117] - node _T_1604 = and(_T_1602, _T_1603) @[dec_tlu_ctl.scala 2261:115] - node _T_1605 = eq(mhpme_vec[2], UInt<3>("h07")) @[dec_tlu_ctl.scala 2262:34] - node _T_1606 = bits(_T_1605, 0, 0) @[dec_tlu_ctl.scala 2262:62] - node _T_1607 = eq(mhpme_vec[2], UInt<4>("h08")) @[dec_tlu_ctl.scala 2263:34] - node _T_1608 = bits(_T_1607, 0, 0) @[dec_tlu_ctl.scala 2263:62] - node _T_1609 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2264:34] - node _T_1610 = bits(_T_1609, 0, 0) @[dec_tlu_ctl.scala 2264:62] - node _T_1611 = eq(mhpme_vec[2], UInt<4>("h09")) @[dec_tlu_ctl.scala 2265:34] - node _T_1612 = bits(_T_1611, 0, 0) @[dec_tlu_ctl.scala 2265:62] - node _T_1613 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2265:91] - node _T_1614 = eq(mhpme_vec[2], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2266:34] - node _T_1615 = bits(_T_1614, 0, 0) @[dec_tlu_ctl.scala 2266:62] - node _T_1616 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2266:105] - node _T_1617 = eq(mhpme_vec[2], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2267:34] - node _T_1618 = bits(_T_1617, 0, 0) @[dec_tlu_ctl.scala 2267:62] - node _T_1619 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2267:91] - node _T_1620 = eq(mhpme_vec[2], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2268:34] - node _T_1621 = bits(_T_1620, 0, 0) @[dec_tlu_ctl.scala 2268:62] - node _T_1622 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2268:91] - node _T_1623 = eq(mhpme_vec[2], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2269:34] - node _T_1624 = bits(_T_1623, 0, 0) @[dec_tlu_ctl.scala 2269:62] - node _T_1625 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2269:91] - node _T_1626 = and(_T_1625, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2269:100] - node _T_1627 = eq(mhpme_vec[2], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2270:34] - node _T_1628 = bits(_T_1627, 0, 0) @[dec_tlu_ctl.scala 2270:62] - node _T_1629 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2270:91] - node _T_1630 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2270:142] - node _T_1631 = and(_T_1629, _T_1630) @[dec_tlu_ctl.scala 2270:101] - node _T_1632 = eq(mhpme_vec[2], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2271:34] - node _T_1633 = bits(_T_1632, 0, 0) @[dec_tlu_ctl.scala 2271:59] - node _T_1634 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2271:89] - node _T_1635 = eq(mhpme_vec[2], UInt<5>("h010")) @[dec_tlu_ctl.scala 2272:34] - node _T_1636 = bits(_T_1635, 0, 0) @[dec_tlu_ctl.scala 2272:59] - node _T_1637 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2272:89] - node _T_1638 = eq(mhpme_vec[2], UInt<5>("h012")) @[dec_tlu_ctl.scala 2273:34] - node _T_1639 = bits(_T_1638, 0, 0) @[dec_tlu_ctl.scala 2273:59] - node _T_1640 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2273:89] - node _T_1641 = eq(mhpme_vec[2], UInt<5>("h011")) @[dec_tlu_ctl.scala 2274:34] - node _T_1642 = bits(_T_1641, 0, 0) @[dec_tlu_ctl.scala 2274:59] - node _T_1643 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2274:89] - node _T_1644 = eq(mhpme_vec[2], UInt<5>("h013")) @[dec_tlu_ctl.scala 2275:34] - node _T_1645 = bits(_T_1644, 0, 0) @[dec_tlu_ctl.scala 2275:59] - node _T_1646 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2275:89] - node _T_1647 = eq(mhpme_vec[2], UInt<5>("h014")) @[dec_tlu_ctl.scala 2276:34] - node _T_1648 = bits(_T_1647, 0, 0) @[dec_tlu_ctl.scala 2276:59] - node _T_1649 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2276:89] - node _T_1650 = eq(mhpme_vec[2], UInt<5>("h015")) @[dec_tlu_ctl.scala 2277:34] - node _T_1651 = bits(_T_1650, 0, 0) @[dec_tlu_ctl.scala 2277:59] - node _T_1652 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2277:89] - node _T_1653 = eq(mhpme_vec[2], UInt<5>("h016")) @[dec_tlu_ctl.scala 2278:34] - node _T_1654 = bits(_T_1653, 0, 0) @[dec_tlu_ctl.scala 2278:59] - node _T_1655 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2278:89] - node _T_1656 = eq(mhpme_vec[2], UInt<5>("h017")) @[dec_tlu_ctl.scala 2279:34] - node _T_1657 = bits(_T_1656, 0, 0) @[dec_tlu_ctl.scala 2279:59] - node _T_1658 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2279:89] - node _T_1659 = eq(mhpme_vec[2], UInt<5>("h018")) @[dec_tlu_ctl.scala 2280:34] - node _T_1660 = bits(_T_1659, 0, 0) @[dec_tlu_ctl.scala 2280:59] - node _T_1661 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2280:89] - node _T_1662 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2280:122] - node _T_1663 = or(_T_1661, _T_1662) @[dec_tlu_ctl.scala 2280:101] - node _T_1664 = eq(mhpme_vec[2], UInt<5>("h019")) @[dec_tlu_ctl.scala 2281:34] - node _T_1665 = bits(_T_1664, 0, 0) @[dec_tlu_ctl.scala 2281:62] - node _T_1666 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2281:95] - node _T_1667 = eq(mhpme_vec[2], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2282:34] - node _T_1668 = bits(_T_1667, 0, 0) @[dec_tlu_ctl.scala 2282:62] - node _T_1669 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2282:97] - node _T_1670 = eq(mhpme_vec[2], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2283:34] - node _T_1671 = bits(_T_1670, 0, 0) @[dec_tlu_ctl.scala 2283:62] - node _T_1672 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2283:110] - node _T_1673 = eq(mhpme_vec[2], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2284:34] - node _T_1674 = bits(_T_1673, 0, 0) @[dec_tlu_ctl.scala 2284:62] - node _T_1675 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2285:34] - node _T_1676 = bits(_T_1675, 0, 0) @[dec_tlu_ctl.scala 2285:62] - node _T_1677 = eq(mhpme_vec[2], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2286:34] - node _T_1678 = bits(_T_1677, 0, 0) @[dec_tlu_ctl.scala 2286:62] - node _T_1679 = eq(mhpme_vec[2], UInt<6>("h020")) @[dec_tlu_ctl.scala 2287:34] - node _T_1680 = bits(_T_1679, 0, 0) @[dec_tlu_ctl.scala 2287:62] - node _T_1681 = eq(mhpme_vec[2], UInt<6>("h022")) @[dec_tlu_ctl.scala 2288:34] - node _T_1682 = bits(_T_1681, 0, 0) @[dec_tlu_ctl.scala 2288:62] - node _T_1683 = eq(mhpme_vec[2], UInt<6>("h023")) @[dec_tlu_ctl.scala 2289:34] - node _T_1684 = bits(_T_1683, 0, 0) @[dec_tlu_ctl.scala 2289:62] - node _T_1685 = eq(mhpme_vec[2], UInt<6>("h024")) @[dec_tlu_ctl.scala 2290:34] - node _T_1686 = bits(_T_1685, 0, 0) @[dec_tlu_ctl.scala 2290:62] - node _T_1687 = eq(mhpme_vec[2], UInt<6>("h025")) @[dec_tlu_ctl.scala 2291:34] - node _T_1688 = bits(_T_1687, 0, 0) @[dec_tlu_ctl.scala 2291:62] - node _T_1689 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2291:98] - node _T_1690 = or(_T_1689, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2291:120] - node _T_1691 = eq(mhpme_vec[2], UInt<6>("h026")) @[dec_tlu_ctl.scala 2292:34] - node _T_1692 = bits(_T_1691, 0, 0) @[dec_tlu_ctl.scala 2292:62] - node _T_1693 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2292:92] - node _T_1694 = or(_T_1693, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2292:117] - node _T_1695 = eq(mhpme_vec[2], UInt<6>("h027")) @[dec_tlu_ctl.scala 2293:34] - node _T_1696 = bits(_T_1695, 0, 0) @[dec_tlu_ctl.scala 2293:62] - node _T_1697 = eq(mhpme_vec[2], UInt<6>("h028")) @[dec_tlu_ctl.scala 2294:34] - node _T_1698 = bits(_T_1697, 0, 0) @[dec_tlu_ctl.scala 2294:62] - node _T_1699 = eq(mhpme_vec[2], UInt<6>("h029")) @[dec_tlu_ctl.scala 2295:34] - node _T_1700 = bits(_T_1699, 0, 0) @[dec_tlu_ctl.scala 2295:62] - node _T_1701 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2295:97] - node _T_1702 = and(_T_1701, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2295:129] - node _T_1703 = eq(mhpme_vec[2], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2296:34] - node _T_1704 = bits(_T_1703, 0, 0) @[dec_tlu_ctl.scala 2296:62] - node _T_1705 = eq(mhpme_vec[2], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2297:34] - node _T_1706 = bits(_T_1705, 0, 0) @[dec_tlu_ctl.scala 2297:62] - node _T_1707 = eq(mhpme_vec[2], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2298:34] - node _T_1708 = bits(_T_1707, 0, 0) @[dec_tlu_ctl.scala 2298:62] - node _T_1709 = eq(mhpme_vec[2], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2299:34] - node _T_1710 = bits(_T_1709, 0, 0) @[dec_tlu_ctl.scala 2299:62] - node _T_1711 = eq(mhpme_vec[2], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2300:34] - node _T_1712 = bits(_T_1711, 0, 0) @[dec_tlu_ctl.scala 2300:62] - node _T_1713 = eq(mhpme_vec[2], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2301:34] - node _T_1714 = bits(_T_1713, 0, 0) @[dec_tlu_ctl.scala 2301:62] - node _T_1715 = eq(mhpme_vec[2], UInt<6>("h030")) @[dec_tlu_ctl.scala 2302:34] - node _T_1716 = bits(_T_1715, 0, 0) @[dec_tlu_ctl.scala 2302:62] - node _T_1717 = eq(mhpme_vec[2], UInt<6>("h031")) @[dec_tlu_ctl.scala 2303:34] - node _T_1718 = bits(_T_1717, 0, 0) @[dec_tlu_ctl.scala 2303:62] - node _T_1719 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2303:84] - node _T_1720 = bits(_T_1719, 0, 0) @[dec_tlu_ctl.scala 2303:84] - node _T_1721 = not(_T_1720) @[dec_tlu_ctl.scala 2303:73] - node _T_1722 = eq(mhpme_vec[2], UInt<6>("h032")) @[dec_tlu_ctl.scala 2304:34] - node _T_1723 = bits(_T_1722, 0, 0) @[dec_tlu_ctl.scala 2304:62] - node _T_1724 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2304:84] - node _T_1725 = bits(_T_1724, 0, 0) @[dec_tlu_ctl.scala 2304:84] - node _T_1726 = not(_T_1725) @[dec_tlu_ctl.scala 2304:73] - node _T_1727 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2304:107] - node _T_1728 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2304:118] - node _T_1729 = and(_T_1727, _T_1728) @[dec_tlu_ctl.scala 2304:113] - node _T_1730 = orr(_T_1729) @[dec_tlu_ctl.scala 2304:125] - node _T_1731 = and(_T_1726, _T_1730) @[dec_tlu_ctl.scala 2304:98] - node _T_1732 = eq(mhpme_vec[2], UInt<6>("h036")) @[dec_tlu_ctl.scala 2305:34] - node _T_1733 = bits(_T_1732, 0, 0) @[dec_tlu_ctl.scala 2305:62] - node _T_1734 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2305:91] - node _T_1735 = eq(mhpme_vec[2], UInt<6>("h037")) @[dec_tlu_ctl.scala 2306:34] - node _T_1736 = bits(_T_1735, 0, 0) @[dec_tlu_ctl.scala 2306:62] - node _T_1737 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2306:94] - node _T_1738 = eq(mhpme_vec[2], UInt<6>("h038")) @[dec_tlu_ctl.scala 2307:34] - node _T_1739 = bits(_T_1738, 0, 0) @[dec_tlu_ctl.scala 2307:62] - node _T_1740 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2307:94] - node _T_1741 = eq(mhpme_vec[2], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2309:34] - node _T_1742 = bits(_T_1741, 0, 0) @[dec_tlu_ctl.scala 2309:62] - node _T_1743 = eq(mhpme_vec[2], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2310:34] - node _T_1744 = bits(_T_1743, 0, 0) @[dec_tlu_ctl.scala 2310:62] - node _T_1745 = eq(mhpme_vec[2], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2311:34] - node _T_1746 = bits(_T_1745, 0, 0) @[dec_tlu_ctl.scala 2311:62] - node _T_1747 = eq(mhpme_vec[2], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2312:34] - node _T_1748 = bits(_T_1747, 0, 0) @[dec_tlu_ctl.scala 2312:62] - node _T_1749 = eq(mhpme_vec[2], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2313:34] - node _T_1750 = bits(_T_1749, 0, 0) @[dec_tlu_ctl.scala 2313:62] - node _T_1751 = mux(_T_1585, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1752 = mux(_T_1587, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1753 = mux(_T_1589, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1754 = mux(_T_1591, _T_1593, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1755 = mux(_T_1595, _T_1599, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1756 = mux(_T_1601, _T_1604, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1757 = mux(_T_1606, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1758 = mux(_T_1608, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1759 = mux(_T_1610, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1760 = mux(_T_1612, _T_1613, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1761 = mux(_T_1615, _T_1616, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1762 = mux(_T_1618, _T_1619, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1763 = mux(_T_1621, _T_1622, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1764 = mux(_T_1624, _T_1626, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1765 = mux(_T_1628, _T_1631, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1766 = mux(_T_1633, _T_1634, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1767 = mux(_T_1636, _T_1637, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1768 = mux(_T_1639, _T_1640, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1769 = mux(_T_1642, _T_1643, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1770 = mux(_T_1645, _T_1646, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1771 = mux(_T_1648, _T_1649, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1772 = mux(_T_1651, _T_1652, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1773 = mux(_T_1654, _T_1655, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1774 = mux(_T_1657, _T_1658, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1775 = mux(_T_1660, _T_1663, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1776 = mux(_T_1665, _T_1666, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1777 = mux(_T_1668, _T_1669, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1778 = mux(_T_1671, _T_1672, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1779 = mux(_T_1674, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1780 = mux(_T_1676, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1781 = mux(_T_1678, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1782 = mux(_T_1680, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1783 = mux(_T_1682, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1784 = mux(_T_1684, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1785 = mux(_T_1686, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1786 = mux(_T_1688, _T_1690, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1787 = mux(_T_1692, _T_1694, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1788 = mux(_T_1696, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1789 = mux(_T_1698, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1790 = mux(_T_1700, _T_1702, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1791 = mux(_T_1704, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1792 = mux(_T_1706, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1793 = mux(_T_1708, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1794 = mux(_T_1710, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1795 = mux(_T_1712, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1796 = mux(_T_1714, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1797 = mux(_T_1716, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1798 = mux(_T_1718, _T_1721, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1799 = mux(_T_1723, _T_1731, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1800 = mux(_T_1733, _T_1734, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1801 = mux(_T_1736, _T_1737, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1802 = mux(_T_1739, _T_1740, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1803 = mux(_T_1742, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1804 = mux(_T_1744, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1805 = mux(_T_1746, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1806 = mux(_T_1748, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1807 = mux(_T_1750, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1808 = or(_T_1751, _T_1752) @[Mux.scala 27:72] - node _T_1809 = or(_T_1808, _T_1753) @[Mux.scala 27:72] - node _T_1810 = or(_T_1809, _T_1754) @[Mux.scala 27:72] - node _T_1811 = or(_T_1810, _T_1755) @[Mux.scala 27:72] - node _T_1812 = or(_T_1811, _T_1756) @[Mux.scala 27:72] - node _T_1813 = or(_T_1812, _T_1757) @[Mux.scala 27:72] - node _T_1814 = or(_T_1813, _T_1758) @[Mux.scala 27:72] - node _T_1815 = or(_T_1814, _T_1759) @[Mux.scala 27:72] - node _T_1816 = or(_T_1815, _T_1760) @[Mux.scala 27:72] - node _T_1817 = or(_T_1816, _T_1761) @[Mux.scala 27:72] - node _T_1818 = or(_T_1817, _T_1762) @[Mux.scala 27:72] + node _T_1580 = or(_T_1579, _T_1524) @[Mux.scala 27:72] + node _T_1581 = or(_T_1580, _T_1525) @[Mux.scala 27:72] + node _T_1582 = or(_T_1581, _T_1526) @[Mux.scala 27:72] + node _T_1583 = or(_T_1582, _T_1527) @[Mux.scala 27:72] + node _T_1584 = or(_T_1583, _T_1528) @[Mux.scala 27:72] + node _T_1585 = or(_T_1584, _T_1529) @[Mux.scala 27:72] + node _T_1586 = or(_T_1585, _T_1530) @[Mux.scala 27:72] + node _T_1587 = or(_T_1586, _T_1531) @[Mux.scala 27:72] + node _T_1588 = or(_T_1587, _T_1532) @[Mux.scala 27:72] + node _T_1589 = or(_T_1588, _T_1533) @[Mux.scala 27:72] + wire _T_1590 : UInt<1> @[Mux.scala 27:72] + _T_1590 <= _T_1589 @[Mux.scala 27:72] + node _T_1591 = and(_T_1309, _T_1590) @[dec_tlu_ctl.scala 2255:44] + mhpmc_inc_r[1] <= _T_1591 @[dec_tlu_ctl.scala 2255:19] + node _T_1592 = bits(mcountinhibit, 5, 5) @[dec_tlu_ctl.scala 2255:38] + node _T_1593 = not(_T_1592) @[dec_tlu_ctl.scala 2255:24] + node _T_1594 = eq(mhpme_vec[2], UInt<1>("h01")) @[dec_tlu_ctl.scala 2256:34] + node _T_1595 = bits(_T_1594, 0, 0) @[dec_tlu_ctl.scala 2256:62] + node _T_1596 = eq(mhpme_vec[2], UInt<2>("h02")) @[dec_tlu_ctl.scala 2257:34] + node _T_1597 = bits(_T_1596, 0, 0) @[dec_tlu_ctl.scala 2257:62] + node _T_1598 = eq(mhpme_vec[2], UInt<2>("h03")) @[dec_tlu_ctl.scala 2258:34] + node _T_1599 = bits(_T_1598, 0, 0) @[dec_tlu_ctl.scala 2258:62] + node _T_1600 = eq(mhpme_vec[2], UInt<3>("h04")) @[dec_tlu_ctl.scala 2259:34] + node _T_1601 = bits(_T_1600, 0, 0) @[dec_tlu_ctl.scala 2259:62] + node _T_1602 = not(io.illegal_r) @[dec_tlu_ctl.scala 2259:96] + node _T_1603 = and(io.tlu_i0_commit_cmt, _T_1602) @[dec_tlu_ctl.scala 2259:94] + node _T_1604 = eq(mhpme_vec[2], UInt<3>("h05")) @[dec_tlu_ctl.scala 2260:34] + node _T_1605 = bits(_T_1604, 0, 0) @[dec_tlu_ctl.scala 2260:62] + node _T_1606 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2260:96] + node _T_1607 = and(io.tlu_i0_commit_cmt, _T_1606) @[dec_tlu_ctl.scala 2260:94] + node _T_1608 = not(io.illegal_r) @[dec_tlu_ctl.scala 2260:117] + node _T_1609 = and(_T_1607, _T_1608) @[dec_tlu_ctl.scala 2260:115] + node _T_1610 = eq(mhpme_vec[2], UInt<3>("h06")) @[dec_tlu_ctl.scala 2261:34] + node _T_1611 = bits(_T_1610, 0, 0) @[dec_tlu_ctl.scala 2261:62] + node _T_1612 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2261:94] + node _T_1613 = not(io.illegal_r) @[dec_tlu_ctl.scala 2261:117] + node _T_1614 = and(_T_1612, _T_1613) @[dec_tlu_ctl.scala 2261:115] + node _T_1615 = eq(mhpme_vec[2], UInt<3>("h07")) @[dec_tlu_ctl.scala 2262:34] + node _T_1616 = bits(_T_1615, 0, 0) @[dec_tlu_ctl.scala 2262:62] + node _T_1617 = eq(mhpme_vec[2], UInt<4>("h08")) @[dec_tlu_ctl.scala 2263:34] + node _T_1618 = bits(_T_1617, 0, 0) @[dec_tlu_ctl.scala 2263:62] + node _T_1619 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2264:34] + node _T_1620 = bits(_T_1619, 0, 0) @[dec_tlu_ctl.scala 2264:62] + node _T_1621 = eq(mhpme_vec[2], UInt<4>("h09")) @[dec_tlu_ctl.scala 2265:34] + node _T_1622 = bits(_T_1621, 0, 0) @[dec_tlu_ctl.scala 2265:62] + node _T_1623 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2265:91] + node _T_1624 = eq(mhpme_vec[2], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2266:34] + node _T_1625 = bits(_T_1624, 0, 0) @[dec_tlu_ctl.scala 2266:62] + node _T_1626 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2266:105] + node _T_1627 = eq(mhpme_vec[2], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2267:34] + node _T_1628 = bits(_T_1627, 0, 0) @[dec_tlu_ctl.scala 2267:62] + node _T_1629 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2267:91] + node _T_1630 = eq(mhpme_vec[2], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2268:34] + node _T_1631 = bits(_T_1630, 0, 0) @[dec_tlu_ctl.scala 2268:62] + node _T_1632 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2268:91] + node _T_1633 = eq(mhpme_vec[2], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2269:34] + node _T_1634 = bits(_T_1633, 0, 0) @[dec_tlu_ctl.scala 2269:62] + node _T_1635 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2269:91] + node _T_1636 = and(_T_1635, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2269:100] + node _T_1637 = eq(mhpme_vec[2], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2270:34] + node _T_1638 = bits(_T_1637, 0, 0) @[dec_tlu_ctl.scala 2270:62] + node _T_1639 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2270:91] + node _T_1640 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2270:142] + node _T_1641 = and(_T_1639, _T_1640) @[dec_tlu_ctl.scala 2270:101] + node _T_1642 = eq(mhpme_vec[2], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2271:34] + node _T_1643 = bits(_T_1642, 0, 0) @[dec_tlu_ctl.scala 2271:59] + node _T_1644 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2271:89] + node _T_1645 = eq(mhpme_vec[2], UInt<5>("h010")) @[dec_tlu_ctl.scala 2272:34] + node _T_1646 = bits(_T_1645, 0, 0) @[dec_tlu_ctl.scala 2272:59] + node _T_1647 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2272:89] + node _T_1648 = eq(mhpme_vec[2], UInt<5>("h012")) @[dec_tlu_ctl.scala 2273:34] + node _T_1649 = bits(_T_1648, 0, 0) @[dec_tlu_ctl.scala 2273:59] + node _T_1650 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2273:89] + node _T_1651 = eq(mhpme_vec[2], UInt<5>("h011")) @[dec_tlu_ctl.scala 2274:34] + node _T_1652 = bits(_T_1651, 0, 0) @[dec_tlu_ctl.scala 2274:59] + node _T_1653 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2274:89] + node _T_1654 = eq(mhpme_vec[2], UInt<5>("h013")) @[dec_tlu_ctl.scala 2275:34] + node _T_1655 = bits(_T_1654, 0, 0) @[dec_tlu_ctl.scala 2275:59] + node _T_1656 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2275:89] + node _T_1657 = eq(mhpme_vec[2], UInt<5>("h014")) @[dec_tlu_ctl.scala 2276:34] + node _T_1658 = bits(_T_1657, 0, 0) @[dec_tlu_ctl.scala 2276:59] + node _T_1659 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2276:89] + node _T_1660 = eq(mhpme_vec[2], UInt<5>("h015")) @[dec_tlu_ctl.scala 2277:34] + node _T_1661 = bits(_T_1660, 0, 0) @[dec_tlu_ctl.scala 2277:59] + node _T_1662 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2277:89] + node _T_1663 = eq(mhpme_vec[2], UInt<5>("h016")) @[dec_tlu_ctl.scala 2278:34] + node _T_1664 = bits(_T_1663, 0, 0) @[dec_tlu_ctl.scala 2278:59] + node _T_1665 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2278:89] + node _T_1666 = eq(mhpme_vec[2], UInt<5>("h017")) @[dec_tlu_ctl.scala 2279:34] + node _T_1667 = bits(_T_1666, 0, 0) @[dec_tlu_ctl.scala 2279:59] + node _T_1668 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2279:89] + node _T_1669 = eq(mhpme_vec[2], UInt<5>("h018")) @[dec_tlu_ctl.scala 2280:34] + node _T_1670 = bits(_T_1669, 0, 0) @[dec_tlu_ctl.scala 2280:59] + node _T_1671 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2280:89] + node _T_1672 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2280:122] + node _T_1673 = or(_T_1671, _T_1672) @[dec_tlu_ctl.scala 2280:101] + node _T_1674 = eq(mhpme_vec[2], UInt<5>("h019")) @[dec_tlu_ctl.scala 2281:34] + node _T_1675 = bits(_T_1674, 0, 0) @[dec_tlu_ctl.scala 2281:62] + node _T_1676 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2281:95] + node _T_1677 = eq(mhpme_vec[2], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2282:34] + node _T_1678 = bits(_T_1677, 0, 0) @[dec_tlu_ctl.scala 2282:62] + node _T_1679 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2282:97] + node _T_1680 = eq(mhpme_vec[2], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2283:34] + node _T_1681 = bits(_T_1680, 0, 0) @[dec_tlu_ctl.scala 2283:62] + node _T_1682 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2283:110] + node _T_1683 = eq(mhpme_vec[2], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2284:34] + node _T_1684 = bits(_T_1683, 0, 0) @[dec_tlu_ctl.scala 2284:62] + node _T_1685 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2285:34] + node _T_1686 = bits(_T_1685, 0, 0) @[dec_tlu_ctl.scala 2285:62] + node _T_1687 = eq(mhpme_vec[2], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2286:34] + node _T_1688 = bits(_T_1687, 0, 0) @[dec_tlu_ctl.scala 2286:62] + node _T_1689 = eq(mhpme_vec[2], UInt<6>("h020")) @[dec_tlu_ctl.scala 2287:34] + node _T_1690 = bits(_T_1689, 0, 0) @[dec_tlu_ctl.scala 2287:62] + node _T_1691 = eq(mhpme_vec[2], UInt<6>("h022")) @[dec_tlu_ctl.scala 2288:34] + node _T_1692 = bits(_T_1691, 0, 0) @[dec_tlu_ctl.scala 2288:62] + node _T_1693 = eq(mhpme_vec[2], UInt<6>("h023")) @[dec_tlu_ctl.scala 2289:34] + node _T_1694 = bits(_T_1693, 0, 0) @[dec_tlu_ctl.scala 2289:62] + node _T_1695 = eq(mhpme_vec[2], UInt<6>("h024")) @[dec_tlu_ctl.scala 2290:34] + node _T_1696 = bits(_T_1695, 0, 0) @[dec_tlu_ctl.scala 2290:62] + node _T_1697 = eq(mhpme_vec[2], UInt<6>("h025")) @[dec_tlu_ctl.scala 2291:34] + node _T_1698 = bits(_T_1697, 0, 0) @[dec_tlu_ctl.scala 2291:62] + node _T_1699 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2291:98] + node _T_1700 = or(_T_1699, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2291:120] + node _T_1701 = eq(mhpme_vec[2], UInt<6>("h026")) @[dec_tlu_ctl.scala 2292:34] + node _T_1702 = bits(_T_1701, 0, 0) @[dec_tlu_ctl.scala 2292:62] + node _T_1703 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2292:92] + node _T_1704 = or(_T_1703, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2292:117] + node _T_1705 = eq(mhpme_vec[2], UInt<6>("h027")) @[dec_tlu_ctl.scala 2293:34] + node _T_1706 = bits(_T_1705, 0, 0) @[dec_tlu_ctl.scala 2293:62] + node _T_1707 = eq(mhpme_vec[2], UInt<6>("h028")) @[dec_tlu_ctl.scala 2294:34] + node _T_1708 = bits(_T_1707, 0, 0) @[dec_tlu_ctl.scala 2294:62] + node _T_1709 = eq(mhpme_vec[2], UInt<6>("h029")) @[dec_tlu_ctl.scala 2295:34] + node _T_1710 = bits(_T_1709, 0, 0) @[dec_tlu_ctl.scala 2295:62] + node _T_1711 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2295:97] + node _T_1712 = and(_T_1711, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2295:129] + node _T_1713 = eq(mhpme_vec[2], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2296:34] + node _T_1714 = bits(_T_1713, 0, 0) @[dec_tlu_ctl.scala 2296:62] + node _T_1715 = eq(mhpme_vec[2], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2297:34] + node _T_1716 = bits(_T_1715, 0, 0) @[dec_tlu_ctl.scala 2297:62] + node _T_1717 = eq(mhpme_vec[2], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2298:34] + node _T_1718 = bits(_T_1717, 0, 0) @[dec_tlu_ctl.scala 2298:62] + node _T_1719 = eq(mhpme_vec[2], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2299:34] + node _T_1720 = bits(_T_1719, 0, 0) @[dec_tlu_ctl.scala 2299:62] + node _T_1721 = eq(mhpme_vec[2], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2300:34] + node _T_1722 = bits(_T_1721, 0, 0) @[dec_tlu_ctl.scala 2300:62] + node _T_1723 = eq(mhpme_vec[2], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2301:34] + node _T_1724 = bits(_T_1723, 0, 0) @[dec_tlu_ctl.scala 2301:62] + node _T_1725 = eq(mhpme_vec[2], UInt<6>("h030")) @[dec_tlu_ctl.scala 2302:34] + node _T_1726 = bits(_T_1725, 0, 0) @[dec_tlu_ctl.scala 2302:62] + node _T_1727 = eq(mhpme_vec[2], UInt<6>("h031")) @[dec_tlu_ctl.scala 2303:34] + node _T_1728 = bits(_T_1727, 0, 0) @[dec_tlu_ctl.scala 2303:62] + node _T_1729 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2303:84] + node _T_1730 = bits(_T_1729, 0, 0) @[dec_tlu_ctl.scala 2303:84] + node _T_1731 = not(_T_1730) @[dec_tlu_ctl.scala 2303:73] + node _T_1732 = eq(mhpme_vec[2], UInt<6>("h032")) @[dec_tlu_ctl.scala 2304:34] + node _T_1733 = bits(_T_1732, 0, 0) @[dec_tlu_ctl.scala 2304:62] + node _T_1734 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2304:84] + node _T_1735 = bits(_T_1734, 0, 0) @[dec_tlu_ctl.scala 2304:84] + node _T_1736 = not(_T_1735) @[dec_tlu_ctl.scala 2304:73] + node _T_1737 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2304:107] + node _T_1738 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2304:118] + node _T_1739 = and(_T_1737, _T_1738) @[dec_tlu_ctl.scala 2304:113] + node _T_1740 = orr(_T_1739) @[dec_tlu_ctl.scala 2304:125] + node _T_1741 = and(_T_1736, _T_1740) @[dec_tlu_ctl.scala 2304:98] + node _T_1742 = eq(mhpme_vec[2], UInt<6>("h036")) @[dec_tlu_ctl.scala 2305:34] + node _T_1743 = bits(_T_1742, 0, 0) @[dec_tlu_ctl.scala 2305:62] + node _T_1744 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2305:91] + node _T_1745 = eq(mhpme_vec[2], UInt<6>("h037")) @[dec_tlu_ctl.scala 2306:34] + node _T_1746 = bits(_T_1745, 0, 0) @[dec_tlu_ctl.scala 2306:62] + node _T_1747 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2306:94] + node _T_1748 = eq(mhpme_vec[2], UInt<6>("h038")) @[dec_tlu_ctl.scala 2307:34] + node _T_1749 = bits(_T_1748, 0, 0) @[dec_tlu_ctl.scala 2307:62] + node _T_1750 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2307:94] + node _T_1751 = eq(mhpme_vec[2], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2309:34] + node _T_1752 = bits(_T_1751, 0, 0) @[dec_tlu_ctl.scala 2309:62] + node _T_1753 = eq(mhpme_vec[2], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2310:34] + node _T_1754 = bits(_T_1753, 0, 0) @[dec_tlu_ctl.scala 2310:62] + node _T_1755 = eq(mhpme_vec[2], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2311:34] + node _T_1756 = bits(_T_1755, 0, 0) @[dec_tlu_ctl.scala 2311:62] + node _T_1757 = eq(mhpme_vec[2], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2312:34] + node _T_1758 = bits(_T_1757, 0, 0) @[dec_tlu_ctl.scala 2312:62] + node _T_1759 = eq(mhpme_vec[2], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2313:34] + node _T_1760 = bits(_T_1759, 0, 0) @[dec_tlu_ctl.scala 2313:62] + node _T_1761 = mux(_T_1595, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1762 = mux(_T_1597, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1763 = mux(_T_1599, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1764 = mux(_T_1601, _T_1603, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1765 = mux(_T_1605, _T_1609, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1766 = mux(_T_1611, _T_1614, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1767 = mux(_T_1616, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1768 = mux(_T_1618, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1769 = mux(_T_1620, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1770 = mux(_T_1622, _T_1623, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1771 = mux(_T_1625, _T_1626, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1772 = mux(_T_1628, _T_1629, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1773 = mux(_T_1631, _T_1632, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1774 = mux(_T_1634, _T_1636, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1775 = mux(_T_1638, _T_1641, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1776 = mux(_T_1643, _T_1644, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1777 = mux(_T_1646, _T_1647, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1778 = mux(_T_1649, _T_1650, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1779 = mux(_T_1652, _T_1653, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1780 = mux(_T_1655, _T_1656, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1781 = mux(_T_1658, _T_1659, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1782 = mux(_T_1661, _T_1662, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1783 = mux(_T_1664, _T_1665, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1784 = mux(_T_1667, _T_1668, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1785 = mux(_T_1670, _T_1673, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1786 = mux(_T_1675, _T_1676, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1787 = mux(_T_1678, _T_1679, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1788 = mux(_T_1681, _T_1682, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1789 = mux(_T_1684, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1790 = mux(_T_1686, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1791 = mux(_T_1688, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1792 = mux(_T_1690, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1793 = mux(_T_1692, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1794 = mux(_T_1694, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1795 = mux(_T_1696, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1796 = mux(_T_1698, _T_1700, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1797 = mux(_T_1702, _T_1704, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1798 = mux(_T_1706, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1799 = mux(_T_1708, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1800 = mux(_T_1710, _T_1712, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1801 = mux(_T_1714, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1802 = mux(_T_1716, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1803 = mux(_T_1718, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1804 = mux(_T_1720, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1805 = mux(_T_1722, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1806 = mux(_T_1724, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1807 = mux(_T_1726, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1808 = mux(_T_1728, _T_1731, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1809 = mux(_T_1733, _T_1741, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1810 = mux(_T_1743, _T_1744, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1811 = mux(_T_1746, _T_1747, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1812 = mux(_T_1749, _T_1750, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1813 = mux(_T_1752, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1814 = mux(_T_1754, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1815 = mux(_T_1756, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1816 = mux(_T_1758, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1817 = mux(_T_1760, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1818 = or(_T_1761, _T_1762) @[Mux.scala 27:72] node _T_1819 = or(_T_1818, _T_1763) @[Mux.scala 27:72] node _T_1820 = or(_T_1819, _T_1764) @[Mux.scala 27:72] node _T_1821 = or(_T_1820, _T_1765) @[Mux.scala 27:72] @@ -75194,247 +75194,247 @@ circuit quasar : node _T_1861 = or(_T_1860, _T_1805) @[Mux.scala 27:72] node _T_1862 = or(_T_1861, _T_1806) @[Mux.scala 27:72] node _T_1863 = or(_T_1862, _T_1807) @[Mux.scala 27:72] - wire _T_1864 : UInt<1> @[Mux.scala 27:72] - _T_1864 <= _T_1863 @[Mux.scala 27:72] - node _T_1865 = and(_T_1583, _T_1864) @[dec_tlu_ctl.scala 2255:44] - mhpmc_inc_r[2] <= _T_1865 @[dec_tlu_ctl.scala 2255:19] - node _T_1866 = bits(mcountinhibit, 6, 6) @[dec_tlu_ctl.scala 2255:38] - node _T_1867 = not(_T_1866) @[dec_tlu_ctl.scala 2255:24] - node _T_1868 = eq(mhpme_vec[3], UInt<1>("h01")) @[dec_tlu_ctl.scala 2256:34] - node _T_1869 = bits(_T_1868, 0, 0) @[dec_tlu_ctl.scala 2256:62] - node _T_1870 = eq(mhpme_vec[3], UInt<2>("h02")) @[dec_tlu_ctl.scala 2257:34] - node _T_1871 = bits(_T_1870, 0, 0) @[dec_tlu_ctl.scala 2257:62] - node _T_1872 = eq(mhpme_vec[3], UInt<2>("h03")) @[dec_tlu_ctl.scala 2258:34] - node _T_1873 = bits(_T_1872, 0, 0) @[dec_tlu_ctl.scala 2258:62] - node _T_1874 = eq(mhpme_vec[3], UInt<3>("h04")) @[dec_tlu_ctl.scala 2259:34] - node _T_1875 = bits(_T_1874, 0, 0) @[dec_tlu_ctl.scala 2259:62] - node _T_1876 = not(io.illegal_r) @[dec_tlu_ctl.scala 2259:96] - node _T_1877 = and(io.tlu_i0_commit_cmt, _T_1876) @[dec_tlu_ctl.scala 2259:94] - node _T_1878 = eq(mhpme_vec[3], UInt<3>("h05")) @[dec_tlu_ctl.scala 2260:34] - node _T_1879 = bits(_T_1878, 0, 0) @[dec_tlu_ctl.scala 2260:62] - node _T_1880 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2260:96] - node _T_1881 = and(io.tlu_i0_commit_cmt, _T_1880) @[dec_tlu_ctl.scala 2260:94] - node _T_1882 = not(io.illegal_r) @[dec_tlu_ctl.scala 2260:117] - node _T_1883 = and(_T_1881, _T_1882) @[dec_tlu_ctl.scala 2260:115] - node _T_1884 = eq(mhpme_vec[3], UInt<3>("h06")) @[dec_tlu_ctl.scala 2261:34] - node _T_1885 = bits(_T_1884, 0, 0) @[dec_tlu_ctl.scala 2261:62] - node _T_1886 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2261:94] - node _T_1887 = not(io.illegal_r) @[dec_tlu_ctl.scala 2261:117] - node _T_1888 = and(_T_1886, _T_1887) @[dec_tlu_ctl.scala 2261:115] - node _T_1889 = eq(mhpme_vec[3], UInt<3>("h07")) @[dec_tlu_ctl.scala 2262:34] - node _T_1890 = bits(_T_1889, 0, 0) @[dec_tlu_ctl.scala 2262:62] - node _T_1891 = eq(mhpme_vec[3], UInt<4>("h08")) @[dec_tlu_ctl.scala 2263:34] - node _T_1892 = bits(_T_1891, 0, 0) @[dec_tlu_ctl.scala 2263:62] - node _T_1893 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2264:34] - node _T_1894 = bits(_T_1893, 0, 0) @[dec_tlu_ctl.scala 2264:62] - node _T_1895 = eq(mhpme_vec[3], UInt<4>("h09")) @[dec_tlu_ctl.scala 2265:34] - node _T_1896 = bits(_T_1895, 0, 0) @[dec_tlu_ctl.scala 2265:62] - node _T_1897 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2265:91] - node _T_1898 = eq(mhpme_vec[3], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2266:34] - node _T_1899 = bits(_T_1898, 0, 0) @[dec_tlu_ctl.scala 2266:62] - node _T_1900 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2266:105] - node _T_1901 = eq(mhpme_vec[3], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2267:34] - node _T_1902 = bits(_T_1901, 0, 0) @[dec_tlu_ctl.scala 2267:62] - node _T_1903 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2267:91] - node _T_1904 = eq(mhpme_vec[3], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2268:34] - node _T_1905 = bits(_T_1904, 0, 0) @[dec_tlu_ctl.scala 2268:62] - node _T_1906 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2268:91] - node _T_1907 = eq(mhpme_vec[3], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2269:34] - node _T_1908 = bits(_T_1907, 0, 0) @[dec_tlu_ctl.scala 2269:62] - node _T_1909 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2269:91] - node _T_1910 = and(_T_1909, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2269:100] - node _T_1911 = eq(mhpme_vec[3], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2270:34] - node _T_1912 = bits(_T_1911, 0, 0) @[dec_tlu_ctl.scala 2270:62] - node _T_1913 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2270:91] - node _T_1914 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2270:142] - node _T_1915 = and(_T_1913, _T_1914) @[dec_tlu_ctl.scala 2270:101] - node _T_1916 = eq(mhpme_vec[3], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2271:34] - node _T_1917 = bits(_T_1916, 0, 0) @[dec_tlu_ctl.scala 2271:59] - node _T_1918 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2271:89] - node _T_1919 = eq(mhpme_vec[3], UInt<5>("h010")) @[dec_tlu_ctl.scala 2272:34] - node _T_1920 = bits(_T_1919, 0, 0) @[dec_tlu_ctl.scala 2272:59] - node _T_1921 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2272:89] - node _T_1922 = eq(mhpme_vec[3], UInt<5>("h012")) @[dec_tlu_ctl.scala 2273:34] - node _T_1923 = bits(_T_1922, 0, 0) @[dec_tlu_ctl.scala 2273:59] - node _T_1924 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2273:89] - node _T_1925 = eq(mhpme_vec[3], UInt<5>("h011")) @[dec_tlu_ctl.scala 2274:34] - node _T_1926 = bits(_T_1925, 0, 0) @[dec_tlu_ctl.scala 2274:59] - node _T_1927 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2274:89] - node _T_1928 = eq(mhpme_vec[3], UInt<5>("h013")) @[dec_tlu_ctl.scala 2275:34] - node _T_1929 = bits(_T_1928, 0, 0) @[dec_tlu_ctl.scala 2275:59] - node _T_1930 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2275:89] - node _T_1931 = eq(mhpme_vec[3], UInt<5>("h014")) @[dec_tlu_ctl.scala 2276:34] - node _T_1932 = bits(_T_1931, 0, 0) @[dec_tlu_ctl.scala 2276:59] - node _T_1933 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2276:89] - node _T_1934 = eq(mhpme_vec[3], UInt<5>("h015")) @[dec_tlu_ctl.scala 2277:34] - node _T_1935 = bits(_T_1934, 0, 0) @[dec_tlu_ctl.scala 2277:59] - node _T_1936 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2277:89] - node _T_1937 = eq(mhpme_vec[3], UInt<5>("h016")) @[dec_tlu_ctl.scala 2278:34] - node _T_1938 = bits(_T_1937, 0, 0) @[dec_tlu_ctl.scala 2278:59] - node _T_1939 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2278:89] - node _T_1940 = eq(mhpme_vec[3], UInt<5>("h017")) @[dec_tlu_ctl.scala 2279:34] - node _T_1941 = bits(_T_1940, 0, 0) @[dec_tlu_ctl.scala 2279:59] - node _T_1942 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2279:89] - node _T_1943 = eq(mhpme_vec[3], UInt<5>("h018")) @[dec_tlu_ctl.scala 2280:34] - node _T_1944 = bits(_T_1943, 0, 0) @[dec_tlu_ctl.scala 2280:59] - node _T_1945 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2280:89] - node _T_1946 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2280:122] - node _T_1947 = or(_T_1945, _T_1946) @[dec_tlu_ctl.scala 2280:101] - node _T_1948 = eq(mhpme_vec[3], UInt<5>("h019")) @[dec_tlu_ctl.scala 2281:34] - node _T_1949 = bits(_T_1948, 0, 0) @[dec_tlu_ctl.scala 2281:62] - node _T_1950 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2281:95] - node _T_1951 = eq(mhpme_vec[3], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2282:34] - node _T_1952 = bits(_T_1951, 0, 0) @[dec_tlu_ctl.scala 2282:62] - node _T_1953 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2282:97] - node _T_1954 = eq(mhpme_vec[3], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2283:34] - node _T_1955 = bits(_T_1954, 0, 0) @[dec_tlu_ctl.scala 2283:62] - node _T_1956 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2283:110] - node _T_1957 = eq(mhpme_vec[3], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2284:34] - node _T_1958 = bits(_T_1957, 0, 0) @[dec_tlu_ctl.scala 2284:62] - node _T_1959 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2285:34] - node _T_1960 = bits(_T_1959, 0, 0) @[dec_tlu_ctl.scala 2285:62] - node _T_1961 = eq(mhpme_vec[3], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2286:34] - node _T_1962 = bits(_T_1961, 0, 0) @[dec_tlu_ctl.scala 2286:62] - node _T_1963 = eq(mhpme_vec[3], UInt<6>("h020")) @[dec_tlu_ctl.scala 2287:34] - node _T_1964 = bits(_T_1963, 0, 0) @[dec_tlu_ctl.scala 2287:62] - node _T_1965 = eq(mhpme_vec[3], UInt<6>("h022")) @[dec_tlu_ctl.scala 2288:34] - node _T_1966 = bits(_T_1965, 0, 0) @[dec_tlu_ctl.scala 2288:62] - node _T_1967 = eq(mhpme_vec[3], UInt<6>("h023")) @[dec_tlu_ctl.scala 2289:34] - node _T_1968 = bits(_T_1967, 0, 0) @[dec_tlu_ctl.scala 2289:62] - node _T_1969 = eq(mhpme_vec[3], UInt<6>("h024")) @[dec_tlu_ctl.scala 2290:34] - node _T_1970 = bits(_T_1969, 0, 0) @[dec_tlu_ctl.scala 2290:62] - node _T_1971 = eq(mhpme_vec[3], UInt<6>("h025")) @[dec_tlu_ctl.scala 2291:34] - node _T_1972 = bits(_T_1971, 0, 0) @[dec_tlu_ctl.scala 2291:62] - node _T_1973 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2291:98] - node _T_1974 = or(_T_1973, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2291:120] - node _T_1975 = eq(mhpme_vec[3], UInt<6>("h026")) @[dec_tlu_ctl.scala 2292:34] - node _T_1976 = bits(_T_1975, 0, 0) @[dec_tlu_ctl.scala 2292:62] - node _T_1977 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2292:92] - node _T_1978 = or(_T_1977, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2292:117] - node _T_1979 = eq(mhpme_vec[3], UInt<6>("h027")) @[dec_tlu_ctl.scala 2293:34] - node _T_1980 = bits(_T_1979, 0, 0) @[dec_tlu_ctl.scala 2293:62] - node _T_1981 = eq(mhpme_vec[3], UInt<6>("h028")) @[dec_tlu_ctl.scala 2294:34] - node _T_1982 = bits(_T_1981, 0, 0) @[dec_tlu_ctl.scala 2294:62] - node _T_1983 = eq(mhpme_vec[3], UInt<6>("h029")) @[dec_tlu_ctl.scala 2295:34] - node _T_1984 = bits(_T_1983, 0, 0) @[dec_tlu_ctl.scala 2295:62] - node _T_1985 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2295:97] - node _T_1986 = and(_T_1985, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2295:129] - node _T_1987 = eq(mhpme_vec[3], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2296:34] - node _T_1988 = bits(_T_1987, 0, 0) @[dec_tlu_ctl.scala 2296:62] - node _T_1989 = eq(mhpme_vec[3], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2297:34] - node _T_1990 = bits(_T_1989, 0, 0) @[dec_tlu_ctl.scala 2297:62] - node _T_1991 = eq(mhpme_vec[3], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2298:34] - node _T_1992 = bits(_T_1991, 0, 0) @[dec_tlu_ctl.scala 2298:62] - node _T_1993 = eq(mhpme_vec[3], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2299:34] - node _T_1994 = bits(_T_1993, 0, 0) @[dec_tlu_ctl.scala 2299:62] - node _T_1995 = eq(mhpme_vec[3], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2300:34] - node _T_1996 = bits(_T_1995, 0, 0) @[dec_tlu_ctl.scala 2300:62] - node _T_1997 = eq(mhpme_vec[3], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2301:34] - node _T_1998 = bits(_T_1997, 0, 0) @[dec_tlu_ctl.scala 2301:62] - node _T_1999 = eq(mhpme_vec[3], UInt<6>("h030")) @[dec_tlu_ctl.scala 2302:34] - node _T_2000 = bits(_T_1999, 0, 0) @[dec_tlu_ctl.scala 2302:62] - node _T_2001 = eq(mhpme_vec[3], UInt<6>("h031")) @[dec_tlu_ctl.scala 2303:34] - node _T_2002 = bits(_T_2001, 0, 0) @[dec_tlu_ctl.scala 2303:62] - node _T_2003 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2303:84] - node _T_2004 = bits(_T_2003, 0, 0) @[dec_tlu_ctl.scala 2303:84] - node _T_2005 = not(_T_2004) @[dec_tlu_ctl.scala 2303:73] - node _T_2006 = eq(mhpme_vec[3], UInt<6>("h032")) @[dec_tlu_ctl.scala 2304:34] - node _T_2007 = bits(_T_2006, 0, 0) @[dec_tlu_ctl.scala 2304:62] - node _T_2008 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2304:84] - node _T_2009 = bits(_T_2008, 0, 0) @[dec_tlu_ctl.scala 2304:84] - node _T_2010 = not(_T_2009) @[dec_tlu_ctl.scala 2304:73] - node _T_2011 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2304:107] - node _T_2012 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2304:118] - node _T_2013 = and(_T_2011, _T_2012) @[dec_tlu_ctl.scala 2304:113] - node _T_2014 = orr(_T_2013) @[dec_tlu_ctl.scala 2304:125] - node _T_2015 = and(_T_2010, _T_2014) @[dec_tlu_ctl.scala 2304:98] - node _T_2016 = eq(mhpme_vec[3], UInt<6>("h036")) @[dec_tlu_ctl.scala 2305:34] - node _T_2017 = bits(_T_2016, 0, 0) @[dec_tlu_ctl.scala 2305:62] - node _T_2018 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2305:91] - node _T_2019 = eq(mhpme_vec[3], UInt<6>("h037")) @[dec_tlu_ctl.scala 2306:34] - node _T_2020 = bits(_T_2019, 0, 0) @[dec_tlu_ctl.scala 2306:62] - node _T_2021 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2306:94] - node _T_2022 = eq(mhpme_vec[3], UInt<6>("h038")) @[dec_tlu_ctl.scala 2307:34] - node _T_2023 = bits(_T_2022, 0, 0) @[dec_tlu_ctl.scala 2307:62] - node _T_2024 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2307:94] - node _T_2025 = eq(mhpme_vec[3], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2309:34] - node _T_2026 = bits(_T_2025, 0, 0) @[dec_tlu_ctl.scala 2309:62] - node _T_2027 = eq(mhpme_vec[3], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2310:34] - node _T_2028 = bits(_T_2027, 0, 0) @[dec_tlu_ctl.scala 2310:62] - node _T_2029 = eq(mhpme_vec[3], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2311:34] - node _T_2030 = bits(_T_2029, 0, 0) @[dec_tlu_ctl.scala 2311:62] - node _T_2031 = eq(mhpme_vec[3], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2312:34] - node _T_2032 = bits(_T_2031, 0, 0) @[dec_tlu_ctl.scala 2312:62] - node _T_2033 = eq(mhpme_vec[3], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2313:34] - node _T_2034 = bits(_T_2033, 0, 0) @[dec_tlu_ctl.scala 2313:62] - node _T_2035 = mux(_T_1869, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2036 = mux(_T_1871, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2037 = mux(_T_1873, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2038 = mux(_T_1875, _T_1877, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2039 = mux(_T_1879, _T_1883, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2040 = mux(_T_1885, _T_1888, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2041 = mux(_T_1890, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2042 = mux(_T_1892, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2043 = mux(_T_1894, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2044 = mux(_T_1896, _T_1897, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2045 = mux(_T_1899, _T_1900, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2046 = mux(_T_1902, _T_1903, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2047 = mux(_T_1905, _T_1906, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2048 = mux(_T_1908, _T_1910, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2049 = mux(_T_1912, _T_1915, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2050 = mux(_T_1917, _T_1918, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2051 = mux(_T_1920, _T_1921, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2052 = mux(_T_1923, _T_1924, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2053 = mux(_T_1926, _T_1927, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2054 = mux(_T_1929, _T_1930, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2055 = mux(_T_1932, _T_1933, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2056 = mux(_T_1935, _T_1936, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2057 = mux(_T_1938, _T_1939, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2058 = mux(_T_1941, _T_1942, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2059 = mux(_T_1944, _T_1947, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2060 = mux(_T_1949, _T_1950, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2061 = mux(_T_1952, _T_1953, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2062 = mux(_T_1955, _T_1956, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2063 = mux(_T_1958, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2064 = mux(_T_1960, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2065 = mux(_T_1962, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2066 = mux(_T_1964, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2067 = mux(_T_1966, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2068 = mux(_T_1968, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2069 = mux(_T_1970, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2070 = mux(_T_1972, _T_1974, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2071 = mux(_T_1976, _T_1978, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2072 = mux(_T_1980, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2073 = mux(_T_1982, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2074 = mux(_T_1984, _T_1986, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2075 = mux(_T_1988, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2076 = mux(_T_1990, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2077 = mux(_T_1992, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2078 = mux(_T_1994, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2079 = mux(_T_1996, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2080 = mux(_T_1998, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2081 = mux(_T_2000, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2082 = mux(_T_2002, _T_2005, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2083 = mux(_T_2007, _T_2015, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2084 = mux(_T_2017, _T_2018, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2085 = mux(_T_2020, _T_2021, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2086 = mux(_T_2023, _T_2024, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2087 = mux(_T_2026, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2088 = mux(_T_2028, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2089 = mux(_T_2030, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2090 = mux(_T_2032, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2091 = mux(_T_2034, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2092 = or(_T_2035, _T_2036) @[Mux.scala 27:72] - node _T_2093 = or(_T_2092, _T_2037) @[Mux.scala 27:72] - node _T_2094 = or(_T_2093, _T_2038) @[Mux.scala 27:72] - node _T_2095 = or(_T_2094, _T_2039) @[Mux.scala 27:72] - node _T_2096 = or(_T_2095, _T_2040) @[Mux.scala 27:72] - node _T_2097 = or(_T_2096, _T_2041) @[Mux.scala 27:72] - node _T_2098 = or(_T_2097, _T_2042) @[Mux.scala 27:72] - node _T_2099 = or(_T_2098, _T_2043) @[Mux.scala 27:72] - node _T_2100 = or(_T_2099, _T_2044) @[Mux.scala 27:72] - node _T_2101 = or(_T_2100, _T_2045) @[Mux.scala 27:72] - node _T_2102 = or(_T_2101, _T_2046) @[Mux.scala 27:72] + node _T_1864 = or(_T_1863, _T_1808) @[Mux.scala 27:72] + node _T_1865 = or(_T_1864, _T_1809) @[Mux.scala 27:72] + node _T_1866 = or(_T_1865, _T_1810) @[Mux.scala 27:72] + node _T_1867 = or(_T_1866, _T_1811) @[Mux.scala 27:72] + node _T_1868 = or(_T_1867, _T_1812) @[Mux.scala 27:72] + node _T_1869 = or(_T_1868, _T_1813) @[Mux.scala 27:72] + node _T_1870 = or(_T_1869, _T_1814) @[Mux.scala 27:72] + node _T_1871 = or(_T_1870, _T_1815) @[Mux.scala 27:72] + node _T_1872 = or(_T_1871, _T_1816) @[Mux.scala 27:72] + node _T_1873 = or(_T_1872, _T_1817) @[Mux.scala 27:72] + wire _T_1874 : UInt<1> @[Mux.scala 27:72] + _T_1874 <= _T_1873 @[Mux.scala 27:72] + node _T_1875 = and(_T_1593, _T_1874) @[dec_tlu_ctl.scala 2255:44] + mhpmc_inc_r[2] <= _T_1875 @[dec_tlu_ctl.scala 2255:19] + node _T_1876 = bits(mcountinhibit, 6, 6) @[dec_tlu_ctl.scala 2255:38] + node _T_1877 = not(_T_1876) @[dec_tlu_ctl.scala 2255:24] + node _T_1878 = eq(mhpme_vec[3], UInt<1>("h01")) @[dec_tlu_ctl.scala 2256:34] + node _T_1879 = bits(_T_1878, 0, 0) @[dec_tlu_ctl.scala 2256:62] + node _T_1880 = eq(mhpme_vec[3], UInt<2>("h02")) @[dec_tlu_ctl.scala 2257:34] + node _T_1881 = bits(_T_1880, 0, 0) @[dec_tlu_ctl.scala 2257:62] + node _T_1882 = eq(mhpme_vec[3], UInt<2>("h03")) @[dec_tlu_ctl.scala 2258:34] + node _T_1883 = bits(_T_1882, 0, 0) @[dec_tlu_ctl.scala 2258:62] + node _T_1884 = eq(mhpme_vec[3], UInt<3>("h04")) @[dec_tlu_ctl.scala 2259:34] + node _T_1885 = bits(_T_1884, 0, 0) @[dec_tlu_ctl.scala 2259:62] + node _T_1886 = not(io.illegal_r) @[dec_tlu_ctl.scala 2259:96] + node _T_1887 = and(io.tlu_i0_commit_cmt, _T_1886) @[dec_tlu_ctl.scala 2259:94] + node _T_1888 = eq(mhpme_vec[3], UInt<3>("h05")) @[dec_tlu_ctl.scala 2260:34] + node _T_1889 = bits(_T_1888, 0, 0) @[dec_tlu_ctl.scala 2260:62] + node _T_1890 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2260:96] + node _T_1891 = and(io.tlu_i0_commit_cmt, _T_1890) @[dec_tlu_ctl.scala 2260:94] + node _T_1892 = not(io.illegal_r) @[dec_tlu_ctl.scala 2260:117] + node _T_1893 = and(_T_1891, _T_1892) @[dec_tlu_ctl.scala 2260:115] + node _T_1894 = eq(mhpme_vec[3], UInt<3>("h06")) @[dec_tlu_ctl.scala 2261:34] + node _T_1895 = bits(_T_1894, 0, 0) @[dec_tlu_ctl.scala 2261:62] + node _T_1896 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2261:94] + node _T_1897 = not(io.illegal_r) @[dec_tlu_ctl.scala 2261:117] + node _T_1898 = and(_T_1896, _T_1897) @[dec_tlu_ctl.scala 2261:115] + node _T_1899 = eq(mhpme_vec[3], UInt<3>("h07")) @[dec_tlu_ctl.scala 2262:34] + node _T_1900 = bits(_T_1899, 0, 0) @[dec_tlu_ctl.scala 2262:62] + node _T_1901 = eq(mhpme_vec[3], UInt<4>("h08")) @[dec_tlu_ctl.scala 2263:34] + node _T_1902 = bits(_T_1901, 0, 0) @[dec_tlu_ctl.scala 2263:62] + node _T_1903 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2264:34] + node _T_1904 = bits(_T_1903, 0, 0) @[dec_tlu_ctl.scala 2264:62] + node _T_1905 = eq(mhpme_vec[3], UInt<4>("h09")) @[dec_tlu_ctl.scala 2265:34] + node _T_1906 = bits(_T_1905, 0, 0) @[dec_tlu_ctl.scala 2265:62] + node _T_1907 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2265:91] + node _T_1908 = eq(mhpme_vec[3], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2266:34] + node _T_1909 = bits(_T_1908, 0, 0) @[dec_tlu_ctl.scala 2266:62] + node _T_1910 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2266:105] + node _T_1911 = eq(mhpme_vec[3], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2267:34] + node _T_1912 = bits(_T_1911, 0, 0) @[dec_tlu_ctl.scala 2267:62] + node _T_1913 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2267:91] + node _T_1914 = eq(mhpme_vec[3], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2268:34] + node _T_1915 = bits(_T_1914, 0, 0) @[dec_tlu_ctl.scala 2268:62] + node _T_1916 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2268:91] + node _T_1917 = eq(mhpme_vec[3], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2269:34] + node _T_1918 = bits(_T_1917, 0, 0) @[dec_tlu_ctl.scala 2269:62] + node _T_1919 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2269:91] + node _T_1920 = and(_T_1919, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2269:100] + node _T_1921 = eq(mhpme_vec[3], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2270:34] + node _T_1922 = bits(_T_1921, 0, 0) @[dec_tlu_ctl.scala 2270:62] + node _T_1923 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2270:91] + node _T_1924 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2270:142] + node _T_1925 = and(_T_1923, _T_1924) @[dec_tlu_ctl.scala 2270:101] + node _T_1926 = eq(mhpme_vec[3], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2271:34] + node _T_1927 = bits(_T_1926, 0, 0) @[dec_tlu_ctl.scala 2271:59] + node _T_1928 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2271:89] + node _T_1929 = eq(mhpme_vec[3], UInt<5>("h010")) @[dec_tlu_ctl.scala 2272:34] + node _T_1930 = bits(_T_1929, 0, 0) @[dec_tlu_ctl.scala 2272:59] + node _T_1931 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2272:89] + node _T_1932 = eq(mhpme_vec[3], UInt<5>("h012")) @[dec_tlu_ctl.scala 2273:34] + node _T_1933 = bits(_T_1932, 0, 0) @[dec_tlu_ctl.scala 2273:59] + node _T_1934 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2273:89] + node _T_1935 = eq(mhpme_vec[3], UInt<5>("h011")) @[dec_tlu_ctl.scala 2274:34] + node _T_1936 = bits(_T_1935, 0, 0) @[dec_tlu_ctl.scala 2274:59] + node _T_1937 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2274:89] + node _T_1938 = eq(mhpme_vec[3], UInt<5>("h013")) @[dec_tlu_ctl.scala 2275:34] + node _T_1939 = bits(_T_1938, 0, 0) @[dec_tlu_ctl.scala 2275:59] + node _T_1940 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2275:89] + node _T_1941 = eq(mhpme_vec[3], UInt<5>("h014")) @[dec_tlu_ctl.scala 2276:34] + node _T_1942 = bits(_T_1941, 0, 0) @[dec_tlu_ctl.scala 2276:59] + node _T_1943 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2276:89] + node _T_1944 = eq(mhpme_vec[3], UInt<5>("h015")) @[dec_tlu_ctl.scala 2277:34] + node _T_1945 = bits(_T_1944, 0, 0) @[dec_tlu_ctl.scala 2277:59] + node _T_1946 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2277:89] + node _T_1947 = eq(mhpme_vec[3], UInt<5>("h016")) @[dec_tlu_ctl.scala 2278:34] + node _T_1948 = bits(_T_1947, 0, 0) @[dec_tlu_ctl.scala 2278:59] + node _T_1949 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2278:89] + node _T_1950 = eq(mhpme_vec[3], UInt<5>("h017")) @[dec_tlu_ctl.scala 2279:34] + node _T_1951 = bits(_T_1950, 0, 0) @[dec_tlu_ctl.scala 2279:59] + node _T_1952 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2279:89] + node _T_1953 = eq(mhpme_vec[3], UInt<5>("h018")) @[dec_tlu_ctl.scala 2280:34] + node _T_1954 = bits(_T_1953, 0, 0) @[dec_tlu_ctl.scala 2280:59] + node _T_1955 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2280:89] + node _T_1956 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2280:122] + node _T_1957 = or(_T_1955, _T_1956) @[dec_tlu_ctl.scala 2280:101] + node _T_1958 = eq(mhpme_vec[3], UInt<5>("h019")) @[dec_tlu_ctl.scala 2281:34] + node _T_1959 = bits(_T_1958, 0, 0) @[dec_tlu_ctl.scala 2281:62] + node _T_1960 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2281:95] + node _T_1961 = eq(mhpme_vec[3], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2282:34] + node _T_1962 = bits(_T_1961, 0, 0) @[dec_tlu_ctl.scala 2282:62] + node _T_1963 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2282:97] + node _T_1964 = eq(mhpme_vec[3], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2283:34] + node _T_1965 = bits(_T_1964, 0, 0) @[dec_tlu_ctl.scala 2283:62] + node _T_1966 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2283:110] + node _T_1967 = eq(mhpme_vec[3], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2284:34] + node _T_1968 = bits(_T_1967, 0, 0) @[dec_tlu_ctl.scala 2284:62] + node _T_1969 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2285:34] + node _T_1970 = bits(_T_1969, 0, 0) @[dec_tlu_ctl.scala 2285:62] + node _T_1971 = eq(mhpme_vec[3], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2286:34] + node _T_1972 = bits(_T_1971, 0, 0) @[dec_tlu_ctl.scala 2286:62] + node _T_1973 = eq(mhpme_vec[3], UInt<6>("h020")) @[dec_tlu_ctl.scala 2287:34] + node _T_1974 = bits(_T_1973, 0, 0) @[dec_tlu_ctl.scala 2287:62] + node _T_1975 = eq(mhpme_vec[3], UInt<6>("h022")) @[dec_tlu_ctl.scala 2288:34] + node _T_1976 = bits(_T_1975, 0, 0) @[dec_tlu_ctl.scala 2288:62] + node _T_1977 = eq(mhpme_vec[3], UInt<6>("h023")) @[dec_tlu_ctl.scala 2289:34] + node _T_1978 = bits(_T_1977, 0, 0) @[dec_tlu_ctl.scala 2289:62] + node _T_1979 = eq(mhpme_vec[3], UInt<6>("h024")) @[dec_tlu_ctl.scala 2290:34] + node _T_1980 = bits(_T_1979, 0, 0) @[dec_tlu_ctl.scala 2290:62] + node _T_1981 = eq(mhpme_vec[3], UInt<6>("h025")) @[dec_tlu_ctl.scala 2291:34] + node _T_1982 = bits(_T_1981, 0, 0) @[dec_tlu_ctl.scala 2291:62] + node _T_1983 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2291:98] + node _T_1984 = or(_T_1983, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2291:120] + node _T_1985 = eq(mhpme_vec[3], UInt<6>("h026")) @[dec_tlu_ctl.scala 2292:34] + node _T_1986 = bits(_T_1985, 0, 0) @[dec_tlu_ctl.scala 2292:62] + node _T_1987 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2292:92] + node _T_1988 = or(_T_1987, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2292:117] + node _T_1989 = eq(mhpme_vec[3], UInt<6>("h027")) @[dec_tlu_ctl.scala 2293:34] + node _T_1990 = bits(_T_1989, 0, 0) @[dec_tlu_ctl.scala 2293:62] + node _T_1991 = eq(mhpme_vec[3], UInt<6>("h028")) @[dec_tlu_ctl.scala 2294:34] + node _T_1992 = bits(_T_1991, 0, 0) @[dec_tlu_ctl.scala 2294:62] + node _T_1993 = eq(mhpme_vec[3], UInt<6>("h029")) @[dec_tlu_ctl.scala 2295:34] + node _T_1994 = bits(_T_1993, 0, 0) @[dec_tlu_ctl.scala 2295:62] + node _T_1995 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2295:97] + node _T_1996 = and(_T_1995, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2295:129] + node _T_1997 = eq(mhpme_vec[3], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2296:34] + node _T_1998 = bits(_T_1997, 0, 0) @[dec_tlu_ctl.scala 2296:62] + node _T_1999 = eq(mhpme_vec[3], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2297:34] + node _T_2000 = bits(_T_1999, 0, 0) @[dec_tlu_ctl.scala 2297:62] + node _T_2001 = eq(mhpme_vec[3], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2298:34] + node _T_2002 = bits(_T_2001, 0, 0) @[dec_tlu_ctl.scala 2298:62] + node _T_2003 = eq(mhpme_vec[3], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2299:34] + node _T_2004 = bits(_T_2003, 0, 0) @[dec_tlu_ctl.scala 2299:62] + node _T_2005 = eq(mhpme_vec[3], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2300:34] + node _T_2006 = bits(_T_2005, 0, 0) @[dec_tlu_ctl.scala 2300:62] + node _T_2007 = eq(mhpme_vec[3], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2301:34] + node _T_2008 = bits(_T_2007, 0, 0) @[dec_tlu_ctl.scala 2301:62] + node _T_2009 = eq(mhpme_vec[3], UInt<6>("h030")) @[dec_tlu_ctl.scala 2302:34] + node _T_2010 = bits(_T_2009, 0, 0) @[dec_tlu_ctl.scala 2302:62] + node _T_2011 = eq(mhpme_vec[3], UInt<6>("h031")) @[dec_tlu_ctl.scala 2303:34] + node _T_2012 = bits(_T_2011, 0, 0) @[dec_tlu_ctl.scala 2303:62] + node _T_2013 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2303:84] + node _T_2014 = bits(_T_2013, 0, 0) @[dec_tlu_ctl.scala 2303:84] + node _T_2015 = not(_T_2014) @[dec_tlu_ctl.scala 2303:73] + node _T_2016 = eq(mhpme_vec[3], UInt<6>("h032")) @[dec_tlu_ctl.scala 2304:34] + node _T_2017 = bits(_T_2016, 0, 0) @[dec_tlu_ctl.scala 2304:62] + node _T_2018 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2304:84] + node _T_2019 = bits(_T_2018, 0, 0) @[dec_tlu_ctl.scala 2304:84] + node _T_2020 = not(_T_2019) @[dec_tlu_ctl.scala 2304:73] + node _T_2021 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2304:107] + node _T_2022 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2304:118] + node _T_2023 = and(_T_2021, _T_2022) @[dec_tlu_ctl.scala 2304:113] + node _T_2024 = orr(_T_2023) @[dec_tlu_ctl.scala 2304:125] + node _T_2025 = and(_T_2020, _T_2024) @[dec_tlu_ctl.scala 2304:98] + node _T_2026 = eq(mhpme_vec[3], UInt<6>("h036")) @[dec_tlu_ctl.scala 2305:34] + node _T_2027 = bits(_T_2026, 0, 0) @[dec_tlu_ctl.scala 2305:62] + node _T_2028 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2305:91] + node _T_2029 = eq(mhpme_vec[3], UInt<6>("h037")) @[dec_tlu_ctl.scala 2306:34] + node _T_2030 = bits(_T_2029, 0, 0) @[dec_tlu_ctl.scala 2306:62] + node _T_2031 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2306:94] + node _T_2032 = eq(mhpme_vec[3], UInt<6>("h038")) @[dec_tlu_ctl.scala 2307:34] + node _T_2033 = bits(_T_2032, 0, 0) @[dec_tlu_ctl.scala 2307:62] + node _T_2034 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2307:94] + node _T_2035 = eq(mhpme_vec[3], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2309:34] + node _T_2036 = bits(_T_2035, 0, 0) @[dec_tlu_ctl.scala 2309:62] + node _T_2037 = eq(mhpme_vec[3], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2310:34] + node _T_2038 = bits(_T_2037, 0, 0) @[dec_tlu_ctl.scala 2310:62] + node _T_2039 = eq(mhpme_vec[3], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2311:34] + node _T_2040 = bits(_T_2039, 0, 0) @[dec_tlu_ctl.scala 2311:62] + node _T_2041 = eq(mhpme_vec[3], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2312:34] + node _T_2042 = bits(_T_2041, 0, 0) @[dec_tlu_ctl.scala 2312:62] + node _T_2043 = eq(mhpme_vec[3], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2313:34] + node _T_2044 = bits(_T_2043, 0, 0) @[dec_tlu_ctl.scala 2313:62] + node _T_2045 = mux(_T_1879, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2046 = mux(_T_1881, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2047 = mux(_T_1883, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2048 = mux(_T_1885, _T_1887, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2049 = mux(_T_1889, _T_1893, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2050 = mux(_T_1895, _T_1898, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2051 = mux(_T_1900, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2052 = mux(_T_1902, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2053 = mux(_T_1904, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2054 = mux(_T_1906, _T_1907, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2055 = mux(_T_1909, _T_1910, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2056 = mux(_T_1912, _T_1913, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2057 = mux(_T_1915, _T_1916, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2058 = mux(_T_1918, _T_1920, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2059 = mux(_T_1922, _T_1925, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2060 = mux(_T_1927, _T_1928, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2061 = mux(_T_1930, _T_1931, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2062 = mux(_T_1933, _T_1934, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2063 = mux(_T_1936, _T_1937, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2064 = mux(_T_1939, _T_1940, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2065 = mux(_T_1942, _T_1943, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2066 = mux(_T_1945, _T_1946, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2067 = mux(_T_1948, _T_1949, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2068 = mux(_T_1951, _T_1952, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2069 = mux(_T_1954, _T_1957, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2070 = mux(_T_1959, _T_1960, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2071 = mux(_T_1962, _T_1963, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2072 = mux(_T_1965, _T_1966, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2073 = mux(_T_1968, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2074 = mux(_T_1970, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2075 = mux(_T_1972, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2076 = mux(_T_1974, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2077 = mux(_T_1976, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2078 = mux(_T_1978, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2079 = mux(_T_1980, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2080 = mux(_T_1982, _T_1984, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2081 = mux(_T_1986, _T_1988, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2082 = mux(_T_1990, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2083 = mux(_T_1992, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2084 = mux(_T_1994, _T_1996, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2085 = mux(_T_1998, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2086 = mux(_T_2000, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2087 = mux(_T_2002, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2088 = mux(_T_2004, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2089 = mux(_T_2006, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2090 = mux(_T_2008, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2091 = mux(_T_2010, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2092 = mux(_T_2012, _T_2015, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2093 = mux(_T_2017, _T_2025, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2094 = mux(_T_2027, _T_2028, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2095 = mux(_T_2030, _T_2031, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2096 = mux(_T_2033, _T_2034, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2097 = mux(_T_2036, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2098 = mux(_T_2038, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2099 = mux(_T_2040, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2100 = mux(_T_2042, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2101 = mux(_T_2044, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2102 = or(_T_2045, _T_2046) @[Mux.scala 27:72] node _T_2103 = or(_T_2102, _T_2047) @[Mux.scala 27:72] node _T_2104 = or(_T_2103, _T_2048) @[Mux.scala 27:72] node _T_2105 = or(_T_2104, _T_2049) @[Mux.scala 27:72] @@ -75480,585 +75480,585 @@ circuit quasar : node _T_2145 = or(_T_2144, _T_2089) @[Mux.scala 27:72] node _T_2146 = or(_T_2145, _T_2090) @[Mux.scala 27:72] node _T_2147 = or(_T_2146, _T_2091) @[Mux.scala 27:72] - wire _T_2148 : UInt<1> @[Mux.scala 27:72] - _T_2148 <= _T_2147 @[Mux.scala 27:72] - node _T_2149 = and(_T_1867, _T_2148) @[dec_tlu_ctl.scala 2255:44] - mhpmc_inc_r[3] <= _T_2149 @[dec_tlu_ctl.scala 2255:19] - reg _T_2150 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2316:53] - _T_2150 <= mhpmc_inc_r[0] @[dec_tlu_ctl.scala 2316:53] - mhpmc_inc_r_d1[0] <= _T_2150 @[dec_tlu_ctl.scala 2316:20] - reg _T_2151 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2317:53] - _T_2151 <= mhpmc_inc_r[1] @[dec_tlu_ctl.scala 2317:53] - mhpmc_inc_r_d1[1] <= _T_2151 @[dec_tlu_ctl.scala 2317:20] - reg _T_2152 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2318:53] - _T_2152 <= mhpmc_inc_r[2] @[dec_tlu_ctl.scala 2318:53] - mhpmc_inc_r_d1[2] <= _T_2152 @[dec_tlu_ctl.scala 2318:20] - reg _T_2153 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2319:53] - _T_2153 <= mhpmc_inc_r[3] @[dec_tlu_ctl.scala 2319:53] - mhpmc_inc_r_d1[3] <= _T_2153 @[dec_tlu_ctl.scala 2319:20] + node _T_2148 = or(_T_2147, _T_2092) @[Mux.scala 27:72] + node _T_2149 = or(_T_2148, _T_2093) @[Mux.scala 27:72] + node _T_2150 = or(_T_2149, _T_2094) @[Mux.scala 27:72] + node _T_2151 = or(_T_2150, _T_2095) @[Mux.scala 27:72] + node _T_2152 = or(_T_2151, _T_2096) @[Mux.scala 27:72] + node _T_2153 = or(_T_2152, _T_2097) @[Mux.scala 27:72] + node _T_2154 = or(_T_2153, _T_2098) @[Mux.scala 27:72] + node _T_2155 = or(_T_2154, _T_2099) @[Mux.scala 27:72] + node _T_2156 = or(_T_2155, _T_2100) @[Mux.scala 27:72] + node _T_2157 = or(_T_2156, _T_2101) @[Mux.scala 27:72] + wire _T_2158 : UInt<1> @[Mux.scala 27:72] + _T_2158 <= _T_2157 @[Mux.scala 27:72] + node _T_2159 = and(_T_1877, _T_2158) @[dec_tlu_ctl.scala 2255:44] + mhpmc_inc_r[3] <= _T_2159 @[dec_tlu_ctl.scala 2255:19] + reg _T_2160 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2316:53] + _T_2160 <= mhpmc_inc_r[0] @[dec_tlu_ctl.scala 2316:53] + mhpmc_inc_r_d1[0] <= _T_2160 @[dec_tlu_ctl.scala 2316:20] + reg _T_2161 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2317:53] + _T_2161 <= mhpmc_inc_r[1] @[dec_tlu_ctl.scala 2317:53] + mhpmc_inc_r_d1[1] <= _T_2161 @[dec_tlu_ctl.scala 2317:20] + reg _T_2162 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2318:53] + _T_2162 <= mhpmc_inc_r[2] @[dec_tlu_ctl.scala 2318:53] + mhpmc_inc_r_d1[2] <= _T_2162 @[dec_tlu_ctl.scala 2318:20] + reg _T_2163 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2319:53] + _T_2163 <= mhpmc_inc_r[3] @[dec_tlu_ctl.scala 2319:53] + mhpmc_inc_r_d1[3] <= _T_2163 @[dec_tlu_ctl.scala 2319:20] reg perfcnt_halted_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2320:56] perfcnt_halted_d1 <= perfcnt_halted @[dec_tlu_ctl.scala 2320:56] - node _T_2154 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2323:53] - node _T_2155 = and(io.dec_tlu_dbg_halted, _T_2154) @[dec_tlu_ctl.scala 2323:44] - node _T_2156 = or(_T_2155, io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2323:67] - perfcnt_halted <= _T_2156 @[dec_tlu_ctl.scala 2323:17] - node _T_2157 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2324:70] - node _T_2158 = and(io.dec_tlu_dbg_halted, _T_2157) @[dec_tlu_ctl.scala 2324:61] - node _T_2159 = not(_T_2158) @[dec_tlu_ctl.scala 2324:37] - node _T_2160 = bits(_T_2159, 0, 0) @[Bitwise.scala 72:15] - node _T_2161 = mux(_T_2160, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_2162 = bits(mhpme_vec[3], 9, 9) @[dec_tlu_ctl.scala 2324:104] - node _T_2163 = bits(mhpme_vec[2], 9, 9) @[dec_tlu_ctl.scala 2324:120] - node _T_2164 = bits(mhpme_vec[1], 9, 9) @[dec_tlu_ctl.scala 2324:136] - node _T_2165 = bits(mhpme_vec[0], 9, 9) @[dec_tlu_ctl.scala 2324:152] - node _T_2166 = cat(_T_2164, _T_2165) @[Cat.scala 29:58] - node _T_2167 = cat(_T_2162, _T_2163) @[Cat.scala 29:58] - node _T_2168 = cat(_T_2167, _T_2166) @[Cat.scala 29:58] - node perfcnt_during_sleep = and(_T_2161, _T_2168) @[dec_tlu_ctl.scala 2324:86] - node _T_2169 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2326:88] - node _T_2170 = not(_T_2169) @[dec_tlu_ctl.scala 2326:67] - node _T_2171 = and(perfcnt_halted_d1, _T_2170) @[dec_tlu_ctl.scala 2326:65] - node _T_2172 = not(_T_2171) @[dec_tlu_ctl.scala 2326:45] - node _T_2173 = and(mhpmc_inc_r_d1[0], _T_2172) @[dec_tlu_ctl.scala 2326:43] - io.dec_tlu_perfcnt0 <= _T_2173 @[dec_tlu_ctl.scala 2326:22] - node _T_2174 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2327:88] - node _T_2175 = not(_T_2174) @[dec_tlu_ctl.scala 2327:67] - node _T_2176 = and(perfcnt_halted_d1, _T_2175) @[dec_tlu_ctl.scala 2327:65] - node _T_2177 = not(_T_2176) @[dec_tlu_ctl.scala 2327:45] - node _T_2178 = and(mhpmc_inc_r_d1[1], _T_2177) @[dec_tlu_ctl.scala 2327:43] - io.dec_tlu_perfcnt1 <= _T_2178 @[dec_tlu_ctl.scala 2327:22] - node _T_2179 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2328:88] - node _T_2180 = not(_T_2179) @[dec_tlu_ctl.scala 2328:67] - node _T_2181 = and(perfcnt_halted_d1, _T_2180) @[dec_tlu_ctl.scala 2328:65] - node _T_2182 = not(_T_2181) @[dec_tlu_ctl.scala 2328:45] - node _T_2183 = and(mhpmc_inc_r_d1[2], _T_2182) @[dec_tlu_ctl.scala 2328:43] - io.dec_tlu_perfcnt2 <= _T_2183 @[dec_tlu_ctl.scala 2328:22] - node _T_2184 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2329:88] - node _T_2185 = not(_T_2184) @[dec_tlu_ctl.scala 2329:67] - node _T_2186 = and(perfcnt_halted_d1, _T_2185) @[dec_tlu_ctl.scala 2329:65] - node _T_2187 = not(_T_2186) @[dec_tlu_ctl.scala 2329:45] - node _T_2188 = and(mhpmc_inc_r_d1[3], _T_2187) @[dec_tlu_ctl.scala 2329:43] - io.dec_tlu_perfcnt3 <= _T_2188 @[dec_tlu_ctl.scala 2329:22] - node _T_2189 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2335:65] - node _T_2190 = eq(_T_2189, UInt<12>("h0b03")) @[dec_tlu_ctl.scala 2335:72] - node mhpmc3_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2190) @[dec_tlu_ctl.scala 2335:43] - node _T_2191 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2336:23] - node _T_2192 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2336:61] - node _T_2193 = or(_T_2191, _T_2192) @[dec_tlu_ctl.scala 2336:39] - node _T_2194 = orr(mhpmc_inc_r[0]) @[dec_tlu_ctl.scala 2336:86] - node mhpmc3_wr_en1 = and(_T_2193, _T_2194) @[dec_tlu_ctl.scala 2336:66] + node _T_2164 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2323:53] + node _T_2165 = and(io.dec_tlu_dbg_halted, _T_2164) @[dec_tlu_ctl.scala 2323:44] + node _T_2166 = or(_T_2165, io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2323:67] + perfcnt_halted <= _T_2166 @[dec_tlu_ctl.scala 2323:17] + node _T_2167 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2324:70] + node _T_2168 = and(io.dec_tlu_dbg_halted, _T_2167) @[dec_tlu_ctl.scala 2324:61] + node _T_2169 = not(_T_2168) @[dec_tlu_ctl.scala 2324:37] + node _T_2170 = bits(_T_2169, 0, 0) @[Bitwise.scala 72:15] + node _T_2171 = mux(_T_2170, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_2172 = bits(mhpme_vec[3], 9, 9) @[dec_tlu_ctl.scala 2324:104] + node _T_2173 = bits(mhpme_vec[2], 9, 9) @[dec_tlu_ctl.scala 2324:120] + node _T_2174 = bits(mhpme_vec[1], 9, 9) @[dec_tlu_ctl.scala 2324:136] + node _T_2175 = bits(mhpme_vec[0], 9, 9) @[dec_tlu_ctl.scala 2324:152] + node _T_2176 = cat(_T_2174, _T_2175) @[Cat.scala 29:58] + node _T_2177 = cat(_T_2172, _T_2173) @[Cat.scala 29:58] + node _T_2178 = cat(_T_2177, _T_2176) @[Cat.scala 29:58] + node perfcnt_during_sleep = and(_T_2171, _T_2178) @[dec_tlu_ctl.scala 2324:86] + node _T_2179 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2326:88] + node _T_2180 = not(_T_2179) @[dec_tlu_ctl.scala 2326:67] + node _T_2181 = and(perfcnt_halted_d1, _T_2180) @[dec_tlu_ctl.scala 2326:65] + node _T_2182 = not(_T_2181) @[dec_tlu_ctl.scala 2326:45] + node _T_2183 = and(mhpmc_inc_r_d1[0], _T_2182) @[dec_tlu_ctl.scala 2326:43] + io.dec_tlu_perfcnt0 <= _T_2183 @[dec_tlu_ctl.scala 2326:22] + node _T_2184 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2327:88] + node _T_2185 = not(_T_2184) @[dec_tlu_ctl.scala 2327:67] + node _T_2186 = and(perfcnt_halted_d1, _T_2185) @[dec_tlu_ctl.scala 2327:65] + node _T_2187 = not(_T_2186) @[dec_tlu_ctl.scala 2327:45] + node _T_2188 = and(mhpmc_inc_r_d1[1], _T_2187) @[dec_tlu_ctl.scala 2327:43] + io.dec_tlu_perfcnt1 <= _T_2188 @[dec_tlu_ctl.scala 2327:22] + node _T_2189 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2328:88] + node _T_2190 = not(_T_2189) @[dec_tlu_ctl.scala 2328:67] + node _T_2191 = and(perfcnt_halted_d1, _T_2190) @[dec_tlu_ctl.scala 2328:65] + node _T_2192 = not(_T_2191) @[dec_tlu_ctl.scala 2328:45] + node _T_2193 = and(mhpmc_inc_r_d1[2], _T_2192) @[dec_tlu_ctl.scala 2328:43] + io.dec_tlu_perfcnt2 <= _T_2193 @[dec_tlu_ctl.scala 2328:22] + node _T_2194 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2329:88] + node _T_2195 = not(_T_2194) @[dec_tlu_ctl.scala 2329:67] + node _T_2196 = and(perfcnt_halted_d1, _T_2195) @[dec_tlu_ctl.scala 2329:65] + node _T_2197 = not(_T_2196) @[dec_tlu_ctl.scala 2329:45] + node _T_2198 = and(mhpmc_inc_r_d1[3], _T_2197) @[dec_tlu_ctl.scala 2329:43] + io.dec_tlu_perfcnt3 <= _T_2198 @[dec_tlu_ctl.scala 2329:22] + node _T_2199 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2335:65] + node _T_2200 = eq(_T_2199, UInt<12>("h0b03")) @[dec_tlu_ctl.scala 2335:72] + node mhpmc3_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2200) @[dec_tlu_ctl.scala 2335:43] + node _T_2201 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2336:23] + node _T_2202 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2336:61] + node _T_2203 = or(_T_2201, _T_2202) @[dec_tlu_ctl.scala 2336:39] + node _T_2204 = orr(mhpmc_inc_r[0]) @[dec_tlu_ctl.scala 2336:86] + node mhpmc3_wr_en1 = and(_T_2203, _T_2204) @[dec_tlu_ctl.scala 2336:66] node mhpmc3_wr_en = or(mhpmc3_wr_en0, mhpmc3_wr_en1) @[dec_tlu_ctl.scala 2337:36] - node _T_2195 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2340:28] - node _T_2196 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2340:41] - node _T_2197 = cat(_T_2195, _T_2196) @[Cat.scala 29:58] - node _T_2198 = cat(UInt<63>("h00"), mhpmc_inc_r[0]) @[Cat.scala 29:58] - node _T_2199 = add(_T_2197, _T_2198) @[dec_tlu_ctl.scala 2340:49] - node _T_2200 = tail(_T_2199, 1) @[dec_tlu_ctl.scala 2340:49] - mhpmc3_incr <= _T_2200 @[dec_tlu_ctl.scala 2340:14] - node _T_2201 = bits(mhpmc3_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2341:36] - node _T_2202 = bits(mhpmc3_incr, 31, 0) @[dec_tlu_ctl.scala 2341:76] - node mhpmc3_ns = mux(_T_2201, io.dec_csr_wrdata_r, _T_2202) @[dec_tlu_ctl.scala 2341:21] - node _T_2203 = bits(mhpmc3_wr_en, 0, 0) @[dec_tlu_ctl.scala 2343:42] + node _T_2205 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2340:28] + node _T_2206 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2340:41] + node _T_2207 = cat(_T_2205, _T_2206) @[Cat.scala 29:58] + node _T_2208 = cat(UInt<63>("h00"), mhpmc_inc_r[0]) @[Cat.scala 29:58] + node _T_2209 = add(_T_2207, _T_2208) @[dec_tlu_ctl.scala 2340:49] + node _T_2210 = tail(_T_2209, 1) @[dec_tlu_ctl.scala 2340:49] + mhpmc3_incr <= _T_2210 @[dec_tlu_ctl.scala 2340:14] + node _T_2211 = bits(mhpmc3_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2341:36] + node _T_2212 = bits(mhpmc3_incr, 31, 0) @[dec_tlu_ctl.scala 2341:76] + node mhpmc3_ns = mux(_T_2211, io.dec_csr_wrdata_r, _T_2212) @[dec_tlu_ctl.scala 2341:21] + node _T_2213 = bits(mhpmc3_wr_en, 0, 0) @[dec_tlu_ctl.scala 2343:42] inst rvclkhdr_26 of rvclkhdr_746 @[lib.scala 368:23] rvclkhdr_26.clock <= clock rvclkhdr_26.reset <= reset rvclkhdr_26.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_26.io.en <= _T_2203 @[lib.scala 371:17] + rvclkhdr_26.io.en <= _T_2213 @[lib.scala 371:17] rvclkhdr_26.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2204 : UInt, rvclkhdr_26.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2204 <= mhpmc3_ns @[lib.scala 374:16] - mhpmc3 <= _T_2204 @[dec_tlu_ctl.scala 2343:9] - node _T_2205 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2345:66] - node _T_2206 = eq(_T_2205, UInt<12>("h0b83")) @[dec_tlu_ctl.scala 2345:73] - node mhpmc3h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2206) @[dec_tlu_ctl.scala 2345:44] + reg _T_2214 : UInt, rvclkhdr_26.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2214 <= mhpmc3_ns @[lib.scala 374:16] + mhpmc3 <= _T_2214 @[dec_tlu_ctl.scala 2343:9] + node _T_2215 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2345:66] + node _T_2216 = eq(_T_2215, UInt<12>("h0b83")) @[dec_tlu_ctl.scala 2345:73] + node mhpmc3h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2216) @[dec_tlu_ctl.scala 2345:44] node mhpmc3h_wr_en = or(mhpmc3h_wr_en0, mhpmc3_wr_en1) @[dec_tlu_ctl.scala 2346:38] - node _T_2207 = bits(mhpmc3h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2347:38] - node _T_2208 = bits(mhpmc3_incr, 63, 32) @[dec_tlu_ctl.scala 2347:78] - node mhpmc3h_ns = mux(_T_2207, io.dec_csr_wrdata_r, _T_2208) @[dec_tlu_ctl.scala 2347:22] - node _T_2209 = bits(mhpmc3h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2349:46] + node _T_2217 = bits(mhpmc3h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2347:38] + node _T_2218 = bits(mhpmc3_incr, 63, 32) @[dec_tlu_ctl.scala 2347:78] + node mhpmc3h_ns = mux(_T_2217, io.dec_csr_wrdata_r, _T_2218) @[dec_tlu_ctl.scala 2347:22] + node _T_2219 = bits(mhpmc3h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2349:46] inst rvclkhdr_27 of rvclkhdr_747 @[lib.scala 368:23] rvclkhdr_27.clock <= clock rvclkhdr_27.reset <= reset rvclkhdr_27.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_27.io.en <= _T_2209 @[lib.scala 371:17] + rvclkhdr_27.io.en <= _T_2219 @[lib.scala 371:17] rvclkhdr_27.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2210 : UInt, rvclkhdr_27.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2210 <= mhpmc3h_ns @[lib.scala 374:16] - mhpmc3h <= _T_2210 @[dec_tlu_ctl.scala 2349:10] - node _T_2211 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2354:65] - node _T_2212 = eq(_T_2211, UInt<12>("h0b04")) @[dec_tlu_ctl.scala 2354:72] - node mhpmc4_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2212) @[dec_tlu_ctl.scala 2354:43] - node _T_2213 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2355:23] - node _T_2214 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2355:61] - node _T_2215 = or(_T_2213, _T_2214) @[dec_tlu_ctl.scala 2355:39] - node _T_2216 = orr(mhpmc_inc_r[1]) @[dec_tlu_ctl.scala 2355:86] - node mhpmc4_wr_en1 = and(_T_2215, _T_2216) @[dec_tlu_ctl.scala 2355:66] + reg _T_2220 : UInt, rvclkhdr_27.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2220 <= mhpmc3h_ns @[lib.scala 374:16] + mhpmc3h <= _T_2220 @[dec_tlu_ctl.scala 2349:10] + node _T_2221 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2354:65] + node _T_2222 = eq(_T_2221, UInt<12>("h0b04")) @[dec_tlu_ctl.scala 2354:72] + node mhpmc4_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2222) @[dec_tlu_ctl.scala 2354:43] + node _T_2223 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2355:23] + node _T_2224 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2355:61] + node _T_2225 = or(_T_2223, _T_2224) @[dec_tlu_ctl.scala 2355:39] + node _T_2226 = orr(mhpmc_inc_r[1]) @[dec_tlu_ctl.scala 2355:86] + node mhpmc4_wr_en1 = and(_T_2225, _T_2226) @[dec_tlu_ctl.scala 2355:66] node mhpmc4_wr_en = or(mhpmc4_wr_en0, mhpmc4_wr_en1) @[dec_tlu_ctl.scala 2356:36] - node _T_2217 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2360:28] - node _T_2218 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2360:41] - node _T_2219 = cat(_T_2217, _T_2218) @[Cat.scala 29:58] - node _T_2220 = cat(UInt<63>("h00"), mhpmc_inc_r[1]) @[Cat.scala 29:58] - node _T_2221 = add(_T_2219, _T_2220) @[dec_tlu_ctl.scala 2360:49] - node _T_2222 = tail(_T_2221, 1) @[dec_tlu_ctl.scala 2360:49] - mhpmc4_incr <= _T_2222 @[dec_tlu_ctl.scala 2360:14] - node _T_2223 = bits(mhpmc4_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2361:36] - node _T_2224 = bits(io.dec_csr_wrdata_r, 31, 0) @[dec_tlu_ctl.scala 2361:63] - node _T_2225 = bits(mhpmc4_incr, 31, 0) @[dec_tlu_ctl.scala 2361:82] - node mhpmc4_ns = mux(_T_2223, _T_2224, _T_2225) @[dec_tlu_ctl.scala 2361:21] - node _T_2226 = bits(mhpmc4_wr_en, 0, 0) @[dec_tlu_ctl.scala 2362:43] + node _T_2227 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2360:28] + node _T_2228 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2360:41] + node _T_2229 = cat(_T_2227, _T_2228) @[Cat.scala 29:58] + node _T_2230 = cat(UInt<63>("h00"), mhpmc_inc_r[1]) @[Cat.scala 29:58] + node _T_2231 = add(_T_2229, _T_2230) @[dec_tlu_ctl.scala 2360:49] + node _T_2232 = tail(_T_2231, 1) @[dec_tlu_ctl.scala 2360:49] + mhpmc4_incr <= _T_2232 @[dec_tlu_ctl.scala 2360:14] + node _T_2233 = bits(mhpmc4_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2361:36] + node _T_2234 = bits(io.dec_csr_wrdata_r, 31, 0) @[dec_tlu_ctl.scala 2361:63] + node _T_2235 = bits(mhpmc4_incr, 31, 0) @[dec_tlu_ctl.scala 2361:82] + node mhpmc4_ns = mux(_T_2233, _T_2234, _T_2235) @[dec_tlu_ctl.scala 2361:21] + node _T_2236 = bits(mhpmc4_wr_en, 0, 0) @[dec_tlu_ctl.scala 2362:43] inst rvclkhdr_28 of rvclkhdr_748 @[lib.scala 368:23] rvclkhdr_28.clock <= clock rvclkhdr_28.reset <= reset rvclkhdr_28.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_28.io.en <= _T_2226 @[lib.scala 371:17] + rvclkhdr_28.io.en <= _T_2236 @[lib.scala 371:17] rvclkhdr_28.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2227 : UInt, rvclkhdr_28.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2227 <= mhpmc4_ns @[lib.scala 374:16] - mhpmc4 <= _T_2227 @[dec_tlu_ctl.scala 2362:9] - node _T_2228 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2364:66] - node _T_2229 = eq(_T_2228, UInt<12>("h0b84")) @[dec_tlu_ctl.scala 2364:73] - node mhpmc4h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2229) @[dec_tlu_ctl.scala 2364:44] + reg _T_2237 : UInt, rvclkhdr_28.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2237 <= mhpmc4_ns @[lib.scala 374:16] + mhpmc4 <= _T_2237 @[dec_tlu_ctl.scala 2362:9] + node _T_2238 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2364:66] + node _T_2239 = eq(_T_2238, UInt<12>("h0b84")) @[dec_tlu_ctl.scala 2364:73] + node mhpmc4h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2239) @[dec_tlu_ctl.scala 2364:44] node mhpmc4h_wr_en = or(mhpmc4h_wr_en0, mhpmc4_wr_en1) @[dec_tlu_ctl.scala 2365:38] - node _T_2230 = bits(mhpmc4h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2366:38] - node _T_2231 = bits(mhpmc4_incr, 63, 32) @[dec_tlu_ctl.scala 2366:78] - node mhpmc4h_ns = mux(_T_2230, io.dec_csr_wrdata_r, _T_2231) @[dec_tlu_ctl.scala 2366:22] - node _T_2232 = bits(mhpmc4h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2367:46] + node _T_2240 = bits(mhpmc4h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2366:38] + node _T_2241 = bits(mhpmc4_incr, 63, 32) @[dec_tlu_ctl.scala 2366:78] + node mhpmc4h_ns = mux(_T_2240, io.dec_csr_wrdata_r, _T_2241) @[dec_tlu_ctl.scala 2366:22] + node _T_2242 = bits(mhpmc4h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2367:46] inst rvclkhdr_29 of rvclkhdr_749 @[lib.scala 368:23] rvclkhdr_29.clock <= clock rvclkhdr_29.reset <= reset rvclkhdr_29.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_29.io.en <= _T_2232 @[lib.scala 371:17] + rvclkhdr_29.io.en <= _T_2242 @[lib.scala 371:17] rvclkhdr_29.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2233 : UInt, rvclkhdr_29.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2233 <= mhpmc4h_ns @[lib.scala 374:16] - mhpmc4h <= _T_2233 @[dec_tlu_ctl.scala 2367:10] - node _T_2234 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2373:65] - node _T_2235 = eq(_T_2234, UInt<12>("h0b05")) @[dec_tlu_ctl.scala 2373:72] - node mhpmc5_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2235) @[dec_tlu_ctl.scala 2373:43] - node _T_2236 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2374:23] - node _T_2237 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2374:61] - node _T_2238 = or(_T_2236, _T_2237) @[dec_tlu_ctl.scala 2374:39] - node _T_2239 = orr(mhpmc_inc_r[2]) @[dec_tlu_ctl.scala 2374:86] - node mhpmc5_wr_en1 = and(_T_2238, _T_2239) @[dec_tlu_ctl.scala 2374:66] + reg _T_2243 : UInt, rvclkhdr_29.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2243 <= mhpmc4h_ns @[lib.scala 374:16] + mhpmc4h <= _T_2243 @[dec_tlu_ctl.scala 2367:10] + node _T_2244 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2373:65] + node _T_2245 = eq(_T_2244, UInt<12>("h0b05")) @[dec_tlu_ctl.scala 2373:72] + node mhpmc5_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2245) @[dec_tlu_ctl.scala 2373:43] + node _T_2246 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2374:23] + node _T_2247 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2374:61] + node _T_2248 = or(_T_2246, _T_2247) @[dec_tlu_ctl.scala 2374:39] + node _T_2249 = orr(mhpmc_inc_r[2]) @[dec_tlu_ctl.scala 2374:86] + node mhpmc5_wr_en1 = and(_T_2248, _T_2249) @[dec_tlu_ctl.scala 2374:66] node mhpmc5_wr_en = or(mhpmc5_wr_en0, mhpmc5_wr_en1) @[dec_tlu_ctl.scala 2375:36] - node _T_2240 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2377:28] - node _T_2241 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2377:41] - node _T_2242 = cat(_T_2240, _T_2241) @[Cat.scala 29:58] - node _T_2243 = cat(UInt<63>("h00"), mhpmc_inc_r[2]) @[Cat.scala 29:58] - node _T_2244 = add(_T_2242, _T_2243) @[dec_tlu_ctl.scala 2377:49] - node _T_2245 = tail(_T_2244, 1) @[dec_tlu_ctl.scala 2377:49] - mhpmc5_incr <= _T_2245 @[dec_tlu_ctl.scala 2377:14] - node _T_2246 = bits(mhpmc5_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2378:36] - node _T_2247 = bits(mhpmc5_incr, 31, 0) @[dec_tlu_ctl.scala 2378:76] - node mhpmc5_ns = mux(_T_2246, io.dec_csr_wrdata_r, _T_2247) @[dec_tlu_ctl.scala 2378:21] - node _T_2248 = bits(mhpmc5_wr_en, 0, 0) @[dec_tlu_ctl.scala 2380:43] + node _T_2250 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2377:28] + node _T_2251 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2377:41] + node _T_2252 = cat(_T_2250, _T_2251) @[Cat.scala 29:58] + node _T_2253 = cat(UInt<63>("h00"), mhpmc_inc_r[2]) @[Cat.scala 29:58] + node _T_2254 = add(_T_2252, _T_2253) @[dec_tlu_ctl.scala 2377:49] + node _T_2255 = tail(_T_2254, 1) @[dec_tlu_ctl.scala 2377:49] + mhpmc5_incr <= _T_2255 @[dec_tlu_ctl.scala 2377:14] + node _T_2256 = bits(mhpmc5_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2378:36] + node _T_2257 = bits(mhpmc5_incr, 31, 0) @[dec_tlu_ctl.scala 2378:76] + node mhpmc5_ns = mux(_T_2256, io.dec_csr_wrdata_r, _T_2257) @[dec_tlu_ctl.scala 2378:21] + node _T_2258 = bits(mhpmc5_wr_en, 0, 0) @[dec_tlu_ctl.scala 2380:43] inst rvclkhdr_30 of rvclkhdr_750 @[lib.scala 368:23] rvclkhdr_30.clock <= clock rvclkhdr_30.reset <= reset rvclkhdr_30.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_30.io.en <= _T_2248 @[lib.scala 371:17] + rvclkhdr_30.io.en <= _T_2258 @[lib.scala 371:17] rvclkhdr_30.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2249 : UInt, rvclkhdr_30.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2249 <= mhpmc5_ns @[lib.scala 374:16] - mhpmc5 <= _T_2249 @[dec_tlu_ctl.scala 2380:9] - node _T_2250 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2382:66] - node _T_2251 = eq(_T_2250, UInt<12>("h0b85")) @[dec_tlu_ctl.scala 2382:73] - node mhpmc5h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2251) @[dec_tlu_ctl.scala 2382:44] + reg _T_2259 : UInt, rvclkhdr_30.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2259 <= mhpmc5_ns @[lib.scala 374:16] + mhpmc5 <= _T_2259 @[dec_tlu_ctl.scala 2380:9] + node _T_2260 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2382:66] + node _T_2261 = eq(_T_2260, UInt<12>("h0b85")) @[dec_tlu_ctl.scala 2382:73] + node mhpmc5h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2261) @[dec_tlu_ctl.scala 2382:44] node mhpmc5h_wr_en = or(mhpmc5h_wr_en0, mhpmc5_wr_en1) @[dec_tlu_ctl.scala 2383:38] - node _T_2252 = bits(mhpmc5h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2384:38] - node _T_2253 = bits(mhpmc5_incr, 63, 32) @[dec_tlu_ctl.scala 2384:78] - node mhpmc5h_ns = mux(_T_2252, io.dec_csr_wrdata_r, _T_2253) @[dec_tlu_ctl.scala 2384:22] - node _T_2254 = bits(mhpmc5h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2386:46] + node _T_2262 = bits(mhpmc5h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2384:38] + node _T_2263 = bits(mhpmc5_incr, 63, 32) @[dec_tlu_ctl.scala 2384:78] + node mhpmc5h_ns = mux(_T_2262, io.dec_csr_wrdata_r, _T_2263) @[dec_tlu_ctl.scala 2384:22] + node _T_2264 = bits(mhpmc5h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2386:46] inst rvclkhdr_31 of rvclkhdr_751 @[lib.scala 368:23] rvclkhdr_31.clock <= clock rvclkhdr_31.reset <= reset rvclkhdr_31.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_31.io.en <= _T_2254 @[lib.scala 371:17] + rvclkhdr_31.io.en <= _T_2264 @[lib.scala 371:17] rvclkhdr_31.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2255 : UInt, rvclkhdr_31.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2255 <= mhpmc5h_ns @[lib.scala 374:16] - mhpmc5h <= _T_2255 @[dec_tlu_ctl.scala 2386:10] - node _T_2256 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2391:65] - node _T_2257 = eq(_T_2256, UInt<12>("h0b06")) @[dec_tlu_ctl.scala 2391:72] - node mhpmc6_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2257) @[dec_tlu_ctl.scala 2391:43] - node _T_2258 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2392:23] - node _T_2259 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2392:61] - node _T_2260 = or(_T_2258, _T_2259) @[dec_tlu_ctl.scala 2392:39] - node _T_2261 = orr(mhpmc_inc_r[3]) @[dec_tlu_ctl.scala 2392:86] - node mhpmc6_wr_en1 = and(_T_2260, _T_2261) @[dec_tlu_ctl.scala 2392:66] + reg _T_2265 : UInt, rvclkhdr_31.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2265 <= mhpmc5h_ns @[lib.scala 374:16] + mhpmc5h <= _T_2265 @[dec_tlu_ctl.scala 2386:10] + node _T_2266 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2391:65] + node _T_2267 = eq(_T_2266, UInt<12>("h0b06")) @[dec_tlu_ctl.scala 2391:72] + node mhpmc6_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2267) @[dec_tlu_ctl.scala 2391:43] + node _T_2268 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2392:23] + node _T_2269 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2392:61] + node _T_2270 = or(_T_2268, _T_2269) @[dec_tlu_ctl.scala 2392:39] + node _T_2271 = orr(mhpmc_inc_r[3]) @[dec_tlu_ctl.scala 2392:86] + node mhpmc6_wr_en1 = and(_T_2270, _T_2271) @[dec_tlu_ctl.scala 2392:66] node mhpmc6_wr_en = or(mhpmc6_wr_en0, mhpmc6_wr_en1) @[dec_tlu_ctl.scala 2393:36] - node _T_2262 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2395:28] - node _T_2263 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2395:41] - node _T_2264 = cat(_T_2262, _T_2263) @[Cat.scala 29:58] - node _T_2265 = cat(UInt<63>("h00"), mhpmc_inc_r[3]) @[Cat.scala 29:58] - node _T_2266 = add(_T_2264, _T_2265) @[dec_tlu_ctl.scala 2395:49] - node _T_2267 = tail(_T_2266, 1) @[dec_tlu_ctl.scala 2395:49] - mhpmc6_incr <= _T_2267 @[dec_tlu_ctl.scala 2395:14] - node _T_2268 = bits(mhpmc6_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2396:36] - node _T_2269 = bits(mhpmc6_incr, 31, 0) @[dec_tlu_ctl.scala 2396:76] - node mhpmc6_ns = mux(_T_2268, io.dec_csr_wrdata_r, _T_2269) @[dec_tlu_ctl.scala 2396:21] - node _T_2270 = bits(mhpmc6_wr_en, 0, 0) @[dec_tlu_ctl.scala 2398:43] + node _T_2272 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2395:28] + node _T_2273 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2395:41] + node _T_2274 = cat(_T_2272, _T_2273) @[Cat.scala 29:58] + node _T_2275 = cat(UInt<63>("h00"), mhpmc_inc_r[3]) @[Cat.scala 29:58] + node _T_2276 = add(_T_2274, _T_2275) @[dec_tlu_ctl.scala 2395:49] + node _T_2277 = tail(_T_2276, 1) @[dec_tlu_ctl.scala 2395:49] + mhpmc6_incr <= _T_2277 @[dec_tlu_ctl.scala 2395:14] + node _T_2278 = bits(mhpmc6_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2396:36] + node _T_2279 = bits(mhpmc6_incr, 31, 0) @[dec_tlu_ctl.scala 2396:76] + node mhpmc6_ns = mux(_T_2278, io.dec_csr_wrdata_r, _T_2279) @[dec_tlu_ctl.scala 2396:21] + node _T_2280 = bits(mhpmc6_wr_en, 0, 0) @[dec_tlu_ctl.scala 2398:43] inst rvclkhdr_32 of rvclkhdr_752 @[lib.scala 368:23] rvclkhdr_32.clock <= clock rvclkhdr_32.reset <= reset rvclkhdr_32.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_32.io.en <= _T_2270 @[lib.scala 371:17] + rvclkhdr_32.io.en <= _T_2280 @[lib.scala 371:17] rvclkhdr_32.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2271 : UInt, rvclkhdr_32.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2271 <= mhpmc6_ns @[lib.scala 374:16] - mhpmc6 <= _T_2271 @[dec_tlu_ctl.scala 2398:9] - node _T_2272 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2400:66] - node _T_2273 = eq(_T_2272, UInt<12>("h0b86")) @[dec_tlu_ctl.scala 2400:73] - node mhpmc6h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2273) @[dec_tlu_ctl.scala 2400:44] + reg _T_2281 : UInt, rvclkhdr_32.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2281 <= mhpmc6_ns @[lib.scala 374:16] + mhpmc6 <= _T_2281 @[dec_tlu_ctl.scala 2398:9] + node _T_2282 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2400:66] + node _T_2283 = eq(_T_2282, UInt<12>("h0b86")) @[dec_tlu_ctl.scala 2400:73] + node mhpmc6h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2283) @[dec_tlu_ctl.scala 2400:44] node mhpmc6h_wr_en = or(mhpmc6h_wr_en0, mhpmc6_wr_en1) @[dec_tlu_ctl.scala 2401:38] - node _T_2274 = bits(mhpmc6h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2402:38] - node _T_2275 = bits(mhpmc6_incr, 63, 32) @[dec_tlu_ctl.scala 2402:78] - node mhpmc6h_ns = mux(_T_2274, io.dec_csr_wrdata_r, _T_2275) @[dec_tlu_ctl.scala 2402:22] - node _T_2276 = bits(mhpmc6h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2404:46] + node _T_2284 = bits(mhpmc6h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2402:38] + node _T_2285 = bits(mhpmc6_incr, 63, 32) @[dec_tlu_ctl.scala 2402:78] + node mhpmc6h_ns = mux(_T_2284, io.dec_csr_wrdata_r, _T_2285) @[dec_tlu_ctl.scala 2402:22] + node _T_2286 = bits(mhpmc6h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2404:46] inst rvclkhdr_33 of rvclkhdr_753 @[lib.scala 368:23] rvclkhdr_33.clock <= clock rvclkhdr_33.reset <= reset rvclkhdr_33.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_33.io.en <= _T_2276 @[lib.scala 371:17] + rvclkhdr_33.io.en <= _T_2286 @[lib.scala 371:17] rvclkhdr_33.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2277 : UInt, rvclkhdr_33.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2277 <= mhpmc6h_ns @[lib.scala 374:16] - mhpmc6h <= _T_2277 @[dec_tlu_ctl.scala 2404:10] - node _T_2278 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2411:50] - node _T_2279 = gt(_T_2278, UInt<10>("h0204")) @[dec_tlu_ctl.scala 2411:56] - node _T_2280 = bits(io.dec_csr_wrdata_r, 31, 10) @[dec_tlu_ctl.scala 2411:93] - node _T_2281 = orr(_T_2280) @[dec_tlu_ctl.scala 2411:102] - node _T_2282 = or(_T_2279, _T_2281) @[dec_tlu_ctl.scala 2411:71] - node _T_2283 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2411:141] - node event_saturate_r = mux(_T_2282, UInt<10>("h0204"), _T_2283) @[dec_tlu_ctl.scala 2411:28] - node _T_2284 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2413:63] - node _T_2285 = eq(_T_2284, UInt<12>("h0323")) @[dec_tlu_ctl.scala 2413:70] - node wr_mhpme3_r = and(io.dec_csr_wen_r_mod, _T_2285) @[dec_tlu_ctl.scala 2413:41] - node _T_2286 = bits(wr_mhpme3_r, 0, 0) @[dec_tlu_ctl.scala 2415:80] - reg _T_2287 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2286 : @[Reg.scala 28:19] - _T_2287 <= event_saturate_r @[Reg.scala 28:23] + reg _T_2287 : UInt, rvclkhdr_33.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2287 <= mhpmc6h_ns @[lib.scala 374:16] + mhpmc6h <= _T_2287 @[dec_tlu_ctl.scala 2404:10] + node _T_2288 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2411:50] + node _T_2289 = gt(_T_2288, UInt<10>("h0204")) @[dec_tlu_ctl.scala 2411:56] + node _T_2290 = bits(io.dec_csr_wrdata_r, 31, 10) @[dec_tlu_ctl.scala 2411:93] + node _T_2291 = orr(_T_2290) @[dec_tlu_ctl.scala 2411:102] + node _T_2292 = or(_T_2289, _T_2291) @[dec_tlu_ctl.scala 2411:71] + node _T_2293 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2411:141] + node event_saturate_r = mux(_T_2292, UInt<10>("h0204"), _T_2293) @[dec_tlu_ctl.scala 2411:28] + node _T_2294 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2413:63] + node _T_2295 = eq(_T_2294, UInt<12>("h0323")) @[dec_tlu_ctl.scala 2413:70] + node wr_mhpme3_r = and(io.dec_csr_wen_r_mod, _T_2295) @[dec_tlu_ctl.scala 2413:41] + node _T_2296 = bits(wr_mhpme3_r, 0, 0) @[dec_tlu_ctl.scala 2415:80] + reg _T_2297 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2296 : @[Reg.scala 28:19] + _T_2297 <= event_saturate_r @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mhpme3 <= _T_2287 @[dec_tlu_ctl.scala 2415:9] - node _T_2288 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2420:63] - node _T_2289 = eq(_T_2288, UInt<12>("h0324")) @[dec_tlu_ctl.scala 2420:70] - node wr_mhpme4_r = and(io.dec_csr_wen_r_mod, _T_2289) @[dec_tlu_ctl.scala 2420:41] - node _T_2290 = bits(wr_mhpme4_r, 0, 0) @[dec_tlu_ctl.scala 2421:80] - reg _T_2291 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2290 : @[Reg.scala 28:19] - _T_2291 <= event_saturate_r @[Reg.scala 28:23] + mhpme3 <= _T_2297 @[dec_tlu_ctl.scala 2415:9] + node _T_2298 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2420:63] + node _T_2299 = eq(_T_2298, UInt<12>("h0324")) @[dec_tlu_ctl.scala 2420:70] + node wr_mhpme4_r = and(io.dec_csr_wen_r_mod, _T_2299) @[dec_tlu_ctl.scala 2420:41] + node _T_2300 = bits(wr_mhpme4_r, 0, 0) @[dec_tlu_ctl.scala 2421:80] + reg _T_2301 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2300 : @[Reg.scala 28:19] + _T_2301 <= event_saturate_r @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mhpme4 <= _T_2291 @[dec_tlu_ctl.scala 2421:9] - node _T_2292 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2427:63] - node _T_2293 = eq(_T_2292, UInt<12>("h0325")) @[dec_tlu_ctl.scala 2427:70] - node wr_mhpme5_r = and(io.dec_csr_wen_r_mod, _T_2293) @[dec_tlu_ctl.scala 2427:41] - node _T_2294 = bits(wr_mhpme5_r, 0, 0) @[dec_tlu_ctl.scala 2428:80] - reg _T_2295 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2294 : @[Reg.scala 28:19] - _T_2295 <= event_saturate_r @[Reg.scala 28:23] + mhpme4 <= _T_2301 @[dec_tlu_ctl.scala 2421:9] + node _T_2302 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2427:63] + node _T_2303 = eq(_T_2302, UInt<12>("h0325")) @[dec_tlu_ctl.scala 2427:70] + node wr_mhpme5_r = and(io.dec_csr_wen_r_mod, _T_2303) @[dec_tlu_ctl.scala 2427:41] + node _T_2304 = bits(wr_mhpme5_r, 0, 0) @[dec_tlu_ctl.scala 2428:80] + reg _T_2305 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2304 : @[Reg.scala 28:19] + _T_2305 <= event_saturate_r @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mhpme5 <= _T_2295 @[dec_tlu_ctl.scala 2428:9] - node _T_2296 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2434:63] - node _T_2297 = eq(_T_2296, UInt<12>("h0326")) @[dec_tlu_ctl.scala 2434:70] - node wr_mhpme6_r = and(io.dec_csr_wen_r_mod, _T_2297) @[dec_tlu_ctl.scala 2434:41] - node _T_2298 = bits(wr_mhpme6_r, 0, 0) @[dec_tlu_ctl.scala 2435:80] - reg _T_2299 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2298 : @[Reg.scala 28:19] - _T_2299 <= event_saturate_r @[Reg.scala 28:23] + mhpme5 <= _T_2305 @[dec_tlu_ctl.scala 2428:9] + node _T_2306 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2434:63] + node _T_2307 = eq(_T_2306, UInt<12>("h0326")) @[dec_tlu_ctl.scala 2434:70] + node wr_mhpme6_r = and(io.dec_csr_wen_r_mod, _T_2307) @[dec_tlu_ctl.scala 2434:41] + node _T_2308 = bits(wr_mhpme6_r, 0, 0) @[dec_tlu_ctl.scala 2435:80] + reg _T_2309 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2308 : @[Reg.scala 28:19] + _T_2309 <= event_saturate_r @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mhpme6 <= _T_2299 @[dec_tlu_ctl.scala 2435:9] - node _T_2300 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2451:70] - node _T_2301 = eq(_T_2300, UInt<12>("h0320")) @[dec_tlu_ctl.scala 2451:77] - node wr_mcountinhibit_r = and(io.dec_csr_wen_r_mod, _T_2301) @[dec_tlu_ctl.scala 2451:48] - node _T_2302 = bits(mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2453:54] + mhpme6 <= _T_2309 @[dec_tlu_ctl.scala 2435:9] + node _T_2310 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2451:70] + node _T_2311 = eq(_T_2310, UInt<12>("h0320")) @[dec_tlu_ctl.scala 2451:77] + node wr_mcountinhibit_r = and(io.dec_csr_wen_r_mod, _T_2311) @[dec_tlu_ctl.scala 2451:48] + node _T_2312 = bits(mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2453:54] wire temp_ncount0 : UInt<1> - temp_ncount0 <= _T_2302 - node _T_2303 = bits(mcountinhibit, 1, 1) @[dec_tlu_ctl.scala 2454:54] + temp_ncount0 <= _T_2312 + node _T_2313 = bits(mcountinhibit, 1, 1) @[dec_tlu_ctl.scala 2454:54] wire temp_ncount1 : UInt<1> - temp_ncount1 <= _T_2303 - node _T_2304 = bits(mcountinhibit, 6, 2) @[dec_tlu_ctl.scala 2455:55] + temp_ncount1 <= _T_2313 + node _T_2314 = bits(mcountinhibit, 6, 2) @[dec_tlu_ctl.scala 2455:55] wire temp_ncount6_2 : UInt<5> - temp_ncount6_2 <= _T_2304 - node _T_2305 = bits(io.dec_csr_wrdata_r, 6, 2) @[dec_tlu_ctl.scala 2456:74] - node _T_2306 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2456:103] - reg _T_2307 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2306 : @[Reg.scala 28:19] - _T_2307 <= _T_2305 @[Reg.scala 28:23] + temp_ncount6_2 <= _T_2314 + node _T_2315 = bits(io.dec_csr_wrdata_r, 6, 2) @[dec_tlu_ctl.scala 2456:74] + node _T_2316 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2456:103] + reg _T_2317 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2316 : @[Reg.scala 28:19] + _T_2317 <= _T_2315 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - temp_ncount6_2 <= _T_2307 @[dec_tlu_ctl.scala 2456:17] - node _T_2308 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2458:72] - node _T_2309 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2458:99] - reg _T_2310 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2309 : @[Reg.scala 28:19] - _T_2310 <= _T_2308 @[Reg.scala 28:23] + temp_ncount6_2 <= _T_2317 @[dec_tlu_ctl.scala 2456:17] + node _T_2318 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2458:72] + node _T_2319 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2458:99] + reg _T_2320 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2319 : @[Reg.scala 28:19] + _T_2320 <= _T_2318 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - temp_ncount0 <= _T_2310 @[dec_tlu_ctl.scala 2458:15] - node _T_2311 = cat(temp_ncount6_2, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2312 = cat(_T_2311, temp_ncount0) @[Cat.scala 29:58] - mcountinhibit <= _T_2312 @[dec_tlu_ctl.scala 2459:16] - node _T_2313 = or(io.i0_valid_wb, io.exc_or_int_valid_r_d1) @[dec_tlu_ctl.scala 2466:51] - node _T_2314 = or(_T_2313, io.interrupt_valid_r_d1) @[dec_tlu_ctl.scala 2466:78] - node _T_2315 = or(_T_2314, io.dec_tlu_i0_valid_wb1) @[dec_tlu_ctl.scala 2466:104] - node _T_2316 = or(_T_2315, io.dec_tlu_i0_exc_valid_wb1) @[dec_tlu_ctl.scala 2466:130] - node _T_2317 = or(_T_2316, io.dec_tlu_int_valid_wb1) @[dec_tlu_ctl.scala 2467:32] - node _T_2318 = or(_T_2317, io.clk_override) @[dec_tlu_ctl.scala 2467:59] - node _T_2319 = bits(_T_2318, 0, 0) @[dec_tlu_ctl.scala 2467:78] + temp_ncount0 <= _T_2320 @[dec_tlu_ctl.scala 2458:15] + node _T_2321 = cat(temp_ncount6_2, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2322 = cat(_T_2321, temp_ncount0) @[Cat.scala 29:58] + mcountinhibit <= _T_2322 @[dec_tlu_ctl.scala 2459:16] + node _T_2323 = or(io.i0_valid_wb, io.exc_or_int_valid_r_d1) @[dec_tlu_ctl.scala 2466:51] + node _T_2324 = or(_T_2323, io.interrupt_valid_r_d1) @[dec_tlu_ctl.scala 2466:78] + node _T_2325 = or(_T_2324, io.dec_tlu_i0_valid_wb1) @[dec_tlu_ctl.scala 2466:104] + node _T_2326 = or(_T_2325, io.dec_tlu_i0_exc_valid_wb1) @[dec_tlu_ctl.scala 2466:130] + node _T_2327 = or(_T_2326, io.dec_tlu_int_valid_wb1) @[dec_tlu_ctl.scala 2467:32] + node _T_2328 = or(_T_2327, io.clk_override) @[dec_tlu_ctl.scala 2467:59] + node _T_2329 = bits(_T_2328, 0, 0) @[dec_tlu_ctl.scala 2467:78] inst rvclkhdr_34 of rvclkhdr_754 @[lib.scala 343:22] rvclkhdr_34.clock <= clock rvclkhdr_34.reset <= reset rvclkhdr_34.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_34.io.en <= _T_2319 @[lib.scala 345:16] + rvclkhdr_34.io.en <= _T_2329 @[lib.scala 345:16] rvclkhdr_34.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - reg _T_2320 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2469:62] - _T_2320 <= io.i0_valid_wb @[dec_tlu_ctl.scala 2469:62] - io.dec_tlu_i0_valid_wb1 <= _T_2320 @[dec_tlu_ctl.scala 2469:30] - node _T_2321 = or(io.i0_exception_valid_r_d1, io.lsu_i0_exc_r_d1) @[dec_tlu_ctl.scala 2470:91] - node _T_2322 = not(io.trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 2470:137] - node _T_2323 = and(io.trigger_hit_r_d1, _T_2322) @[dec_tlu_ctl.scala 2470:135] - node _T_2324 = or(_T_2321, _T_2323) @[dec_tlu_ctl.scala 2470:112] - reg _T_2325 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2470:62] - _T_2325 <= _T_2324 @[dec_tlu_ctl.scala 2470:62] - io.dec_tlu_i0_exc_valid_wb1 <= _T_2325 @[dec_tlu_ctl.scala 2470:30] - reg _T_2326 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2471:62] - _T_2326 <= io.exc_cause_wb @[dec_tlu_ctl.scala 2471:62] - io.dec_tlu_exc_cause_wb1 <= _T_2326 @[dec_tlu_ctl.scala 2471:30] - reg _T_2327 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2472:62] - _T_2327 <= io.interrupt_valid_r_d1 @[dec_tlu_ctl.scala 2472:62] - io.dec_tlu_int_valid_wb1 <= _T_2327 @[dec_tlu_ctl.scala 2472:30] + reg _T_2330 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2469:62] + _T_2330 <= io.i0_valid_wb @[dec_tlu_ctl.scala 2469:62] + io.dec_tlu_i0_valid_wb1 <= _T_2330 @[dec_tlu_ctl.scala 2469:30] + node _T_2331 = or(io.i0_exception_valid_r_d1, io.lsu_i0_exc_r_d1) @[dec_tlu_ctl.scala 2470:91] + node _T_2332 = not(io.trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 2470:137] + node _T_2333 = and(io.trigger_hit_r_d1, _T_2332) @[dec_tlu_ctl.scala 2470:135] + node _T_2334 = or(_T_2331, _T_2333) @[dec_tlu_ctl.scala 2470:112] + reg _T_2335 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2470:62] + _T_2335 <= _T_2334 @[dec_tlu_ctl.scala 2470:62] + io.dec_tlu_i0_exc_valid_wb1 <= _T_2335 @[dec_tlu_ctl.scala 2470:30] + reg _T_2336 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2471:62] + _T_2336 <= io.exc_cause_wb @[dec_tlu_ctl.scala 2471:62] + io.dec_tlu_exc_cause_wb1 <= _T_2336 @[dec_tlu_ctl.scala 2471:30] + reg _T_2337 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2472:62] + _T_2337 <= io.interrupt_valid_r_d1 @[dec_tlu_ctl.scala 2472:62] + io.dec_tlu_int_valid_wb1 <= _T_2337 @[dec_tlu_ctl.scala 2472:30] io.dec_tlu_mtval_wb1 <= mtval @[dec_tlu_ctl.scala 2474:24] - node _T_2328 = bits(io.csr_pkt.csr_misa, 0, 0) @[dec_tlu_ctl.scala 2480:61] - node _T_2329 = bits(io.csr_pkt.csr_mvendorid, 0, 0) @[dec_tlu_ctl.scala 2481:42] - node _T_2330 = bits(io.csr_pkt.csr_marchid, 0, 0) @[dec_tlu_ctl.scala 2482:40] - node _T_2331 = bits(io.csr_pkt.csr_mimpid, 0, 0) @[dec_tlu_ctl.scala 2483:39] - node _T_2332 = bits(io.csr_pkt.csr_mhartid, 0, 0) @[dec_tlu_ctl.scala 2484:40] - node _T_2333 = cat(io.core_id, UInt<4>("h00")) @[Cat.scala 29:58] - node _T_2334 = bits(io.csr_pkt.csr_mstatus, 0, 0) @[dec_tlu_ctl.scala 2485:40] - node _T_2335 = bits(io.mstatus, 1, 1) @[dec_tlu_ctl.scala 2485:103] - node _T_2336 = bits(io.mstatus, 0, 0) @[dec_tlu_ctl.scala 2485:128] - node _T_2337 = cat(UInt<3>("h00"), _T_2336) @[Cat.scala 29:58] - node _T_2338 = cat(_T_2337, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2339 = cat(UInt<3>("h00"), _T_2335) @[Cat.scala 29:58] - node _T_2340 = cat(UInt<19>("h00"), UInt<2>("h03")) @[Cat.scala 29:58] - node _T_2341 = cat(_T_2340, _T_2339) @[Cat.scala 29:58] - node _T_2342 = cat(_T_2341, _T_2338) @[Cat.scala 29:58] - node _T_2343 = bits(io.csr_pkt.csr_mtvec, 0, 0) @[dec_tlu_ctl.scala 2486:38] - node _T_2344 = bits(io.mtvec, 30, 1) @[dec_tlu_ctl.scala 2486:70] - node _T_2345 = bits(io.mtvec, 0, 0) @[dec_tlu_ctl.scala 2486:96] - node _T_2346 = cat(_T_2344, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2347 = cat(_T_2346, _T_2345) @[Cat.scala 29:58] - node _T_2348 = bits(io.csr_pkt.csr_mip, 0, 0) @[dec_tlu_ctl.scala 2487:36] - node _T_2349 = bits(io.mip, 5, 3) @[dec_tlu_ctl.scala 2487:78] - node _T_2350 = bits(io.mip, 2, 2) @[dec_tlu_ctl.scala 2487:102] - node _T_2351 = bits(io.mip, 1, 1) @[dec_tlu_ctl.scala 2487:123] - node _T_2352 = bits(io.mip, 0, 0) @[dec_tlu_ctl.scala 2487:144] - node _T_2353 = cat(_T_2352, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2354 = cat(_T_2351, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2355 = cat(_T_2354, _T_2353) @[Cat.scala 29:58] - node _T_2356 = cat(_T_2350, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2357 = cat(UInt<1>("h00"), _T_2349) @[Cat.scala 29:58] - node _T_2358 = cat(_T_2357, UInt<16>("h00")) @[Cat.scala 29:58] - node _T_2359 = cat(_T_2358, _T_2356) @[Cat.scala 29:58] - node _T_2360 = cat(_T_2359, _T_2355) @[Cat.scala 29:58] - node _T_2361 = bits(io.csr_pkt.csr_mie, 0, 0) @[dec_tlu_ctl.scala 2488:36] - node _T_2362 = bits(mie, 5, 3) @[dec_tlu_ctl.scala 2488:75] - node _T_2363 = bits(mie, 2, 2) @[dec_tlu_ctl.scala 2488:96] - node _T_2364 = bits(mie, 1, 1) @[dec_tlu_ctl.scala 2488:114] - node _T_2365 = bits(mie, 0, 0) @[dec_tlu_ctl.scala 2488:132] - node _T_2366 = cat(_T_2365, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2367 = cat(_T_2364, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2368 = cat(_T_2367, _T_2366) @[Cat.scala 29:58] - node _T_2369 = cat(_T_2363, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2370 = cat(UInt<1>("h00"), _T_2362) @[Cat.scala 29:58] - node _T_2371 = cat(_T_2370, UInt<16>("h00")) @[Cat.scala 29:58] - node _T_2372 = cat(_T_2371, _T_2369) @[Cat.scala 29:58] - node _T_2373 = cat(_T_2372, _T_2368) @[Cat.scala 29:58] - node _T_2374 = bits(io.csr_pkt.csr_mcyclel, 0, 0) @[dec_tlu_ctl.scala 2489:40] - node _T_2375 = bits(mcyclel, 31, 0) @[dec_tlu_ctl.scala 2489:65] - node _T_2376 = bits(io.csr_pkt.csr_mcycleh, 0, 0) @[dec_tlu_ctl.scala 2490:40] - node _T_2377 = bits(mcycleh_inc, 31, 0) @[dec_tlu_ctl.scala 2490:69] - node _T_2378 = bits(io.csr_pkt.csr_minstretl, 0, 0) @[dec_tlu_ctl.scala 2491:42] - node _T_2379 = bits(minstretl, 31, 0) @[dec_tlu_ctl.scala 2491:72] - node _T_2380 = bits(io.csr_pkt.csr_minstreth, 0, 0) @[dec_tlu_ctl.scala 2492:42] - node _T_2381 = bits(minstreth_inc, 31, 0) @[dec_tlu_ctl.scala 2492:72] - node _T_2382 = bits(io.csr_pkt.csr_mscratch, 0, 0) @[dec_tlu_ctl.scala 2493:41] - node _T_2383 = bits(mscratch, 31, 0) @[dec_tlu_ctl.scala 2493:66] - node _T_2384 = bits(io.csr_pkt.csr_mepc, 0, 0) @[dec_tlu_ctl.scala 2494:37] - node _T_2385 = cat(io.mepc, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2386 = bits(io.csr_pkt.csr_mcause, 0, 0) @[dec_tlu_ctl.scala 2495:39] - node _T_2387 = bits(mcause, 31, 0) @[dec_tlu_ctl.scala 2495:64] - node _T_2388 = bits(io.csr_pkt.csr_mscause, 0, 0) @[dec_tlu_ctl.scala 2496:40] - node _T_2389 = bits(mscause, 3, 0) @[dec_tlu_ctl.scala 2496:80] - node _T_2390 = cat(UInt<28>("h00"), _T_2389) @[Cat.scala 29:58] - node _T_2391 = bits(io.csr_pkt.csr_mtval, 0, 0) @[dec_tlu_ctl.scala 2497:38] - node _T_2392 = bits(mtval, 31, 0) @[dec_tlu_ctl.scala 2497:63] - node _T_2393 = bits(io.csr_pkt.csr_mrac, 0, 0) @[dec_tlu_ctl.scala 2498:37] - node _T_2394 = bits(mrac, 31, 0) @[dec_tlu_ctl.scala 2498:62] - node _T_2395 = bits(io.csr_pkt.csr_mdseac, 0, 0) @[dec_tlu_ctl.scala 2499:39] - node _T_2396 = bits(mdseac, 31, 0) @[dec_tlu_ctl.scala 2499:64] - node _T_2397 = bits(io.csr_pkt.csr_meivt, 0, 0) @[dec_tlu_ctl.scala 2500:38] - node _T_2398 = cat(meivt, UInt<10>("h00")) @[Cat.scala 29:58] - node _T_2399 = bits(io.csr_pkt.csr_meihap, 0, 0) @[dec_tlu_ctl.scala 2501:39] - node _T_2400 = cat(meivt, meihap) @[Cat.scala 29:58] - node _T_2401 = cat(_T_2400, UInt<2>("h00")) @[Cat.scala 29:58] - node _T_2402 = bits(io.csr_pkt.csr_meicurpl, 0, 0) @[dec_tlu_ctl.scala 2502:41] - node _T_2403 = bits(meicurpl, 3, 0) @[dec_tlu_ctl.scala 2502:81] - node _T_2404 = cat(UInt<28>("h00"), _T_2403) @[Cat.scala 29:58] - node _T_2405 = bits(io.csr_pkt.csr_meicidpl, 0, 0) @[dec_tlu_ctl.scala 2503:41] - node _T_2406 = bits(meicidpl, 3, 0) @[dec_tlu_ctl.scala 2503:81] - node _T_2407 = cat(UInt<28>("h00"), _T_2406) @[Cat.scala 29:58] - node _T_2408 = bits(io.csr_pkt.csr_meipt, 0, 0) @[dec_tlu_ctl.scala 2504:38] - node _T_2409 = bits(meipt, 3, 0) @[dec_tlu_ctl.scala 2504:78] - node _T_2410 = cat(UInt<28>("h00"), _T_2409) @[Cat.scala 29:58] - node _T_2411 = bits(io.csr_pkt.csr_mcgc, 0, 0) @[dec_tlu_ctl.scala 2505:37] - node _T_2412 = bits(mcgc, 8, 0) @[dec_tlu_ctl.scala 2505:77] - node _T_2413 = cat(UInt<23>("h00"), _T_2412) @[Cat.scala 29:58] - node _T_2414 = bits(io.csr_pkt.csr_mfdc, 0, 0) @[dec_tlu_ctl.scala 2506:37] - node _T_2415 = bits(mfdc, 18, 0) @[dec_tlu_ctl.scala 2506:77] - node _T_2416 = cat(UInt<13>("h00"), _T_2415) @[Cat.scala 29:58] - node _T_2417 = bits(io.csr_pkt.csr_dcsr, 0, 0) @[dec_tlu_ctl.scala 2507:37] - node _T_2418 = bits(io.dcsr, 15, 2) @[dec_tlu_ctl.scala 2507:85] - node _T_2419 = cat(UInt<16>("h04000"), _T_2418) @[Cat.scala 29:58] - node _T_2420 = cat(_T_2419, UInt<2>("h03")) @[Cat.scala 29:58] - node _T_2421 = bits(io.csr_pkt.csr_dpc, 0, 0) @[dec_tlu_ctl.scala 2508:36] - node _T_2422 = cat(io.dpc, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2423 = bits(io.csr_pkt.csr_dicad0, 0, 0) @[dec_tlu_ctl.scala 2509:39] - node _T_2424 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2509:64] - node _T_2425 = bits(io.csr_pkt.csr_dicad0h, 0, 0) @[dec_tlu_ctl.scala 2510:40] - node _T_2426 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2510:65] - node _T_2427 = bits(io.csr_pkt.csr_dicad1, 0, 0) @[dec_tlu_ctl.scala 2511:39] - node _T_2428 = bits(dicad1, 31, 0) @[dec_tlu_ctl.scala 2511:64] - node _T_2429 = bits(io.csr_pkt.csr_dicawics, 0, 0) @[dec_tlu_ctl.scala 2512:41] - node _T_2430 = bits(dicawics, 16, 16) @[dec_tlu_ctl.scala 2512:80] - node _T_2431 = bits(dicawics, 15, 14) @[dec_tlu_ctl.scala 2512:104] - node _T_2432 = bits(dicawics, 13, 0) @[dec_tlu_ctl.scala 2512:131] - node _T_2433 = cat(UInt<3>("h00"), _T_2432) @[Cat.scala 29:58] - node _T_2434 = cat(_T_2433, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2435 = cat(UInt<2>("h00"), _T_2431) @[Cat.scala 29:58] - node _T_2436 = cat(UInt<7>("h00"), _T_2430) @[Cat.scala 29:58] - node _T_2437 = cat(_T_2436, _T_2435) @[Cat.scala 29:58] - node _T_2438 = cat(_T_2437, _T_2434) @[Cat.scala 29:58] - node _T_2439 = bits(io.csr_pkt.csr_mtsel, 0, 0) @[dec_tlu_ctl.scala 2513:38] - node _T_2440 = bits(mtsel, 1, 0) @[dec_tlu_ctl.scala 2513:78] - node _T_2441 = cat(UInt<30>("h00"), _T_2440) @[Cat.scala 29:58] - node _T_2442 = bits(io.csr_pkt.csr_mtdata1, 0, 0) @[dec_tlu_ctl.scala 2514:40] - node _T_2443 = bits(mtdata1_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2514:74] - node _T_2444 = bits(io.csr_pkt.csr_mtdata2, 0, 0) @[dec_tlu_ctl.scala 2515:40] - node _T_2445 = bits(mtdata2_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2515:74] - node _T_2446 = bits(io.csr_pkt.csr_micect, 0, 0) @[dec_tlu_ctl.scala 2516:39] - node _T_2447 = bits(micect, 31, 0) @[dec_tlu_ctl.scala 2516:64] - node _T_2448 = bits(io.csr_pkt.csr_miccmect, 0, 0) @[dec_tlu_ctl.scala 2517:41] - node _T_2449 = bits(miccmect, 31, 0) @[dec_tlu_ctl.scala 2517:66] - node _T_2450 = bits(io.csr_pkt.csr_mdccmect, 0, 0) @[dec_tlu_ctl.scala 2518:41] - node _T_2451 = bits(mdccmect, 31, 0) @[dec_tlu_ctl.scala 2518:66] - node _T_2452 = bits(io.csr_pkt.csr_mhpmc3, 0, 0) @[dec_tlu_ctl.scala 2519:39] - node _T_2453 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2519:64] - node _T_2454 = bits(io.csr_pkt.csr_mhpmc4, 0, 0) @[dec_tlu_ctl.scala 2520:39] - node _T_2455 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2520:64] - node _T_2456 = bits(io.csr_pkt.csr_mhpmc5, 0, 0) @[dec_tlu_ctl.scala 2521:39] - node _T_2457 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2521:64] - node _T_2458 = bits(io.csr_pkt.csr_mhpmc6, 0, 0) @[dec_tlu_ctl.scala 2522:39] - node _T_2459 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2522:64] - node _T_2460 = bits(io.csr_pkt.csr_mhpmc3h, 0, 0) @[dec_tlu_ctl.scala 2523:40] - node _T_2461 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2523:65] - node _T_2462 = bits(io.csr_pkt.csr_mhpmc4h, 0, 0) @[dec_tlu_ctl.scala 2524:40] - node _T_2463 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2524:65] - node _T_2464 = bits(io.csr_pkt.csr_mhpmc5h, 0, 0) @[dec_tlu_ctl.scala 2525:40] - node _T_2465 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2525:65] - node _T_2466 = bits(io.csr_pkt.csr_mhpmc6h, 0, 0) @[dec_tlu_ctl.scala 2526:40] - node _T_2467 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2526:65] - node _T_2468 = bits(io.csr_pkt.csr_mfdht, 0, 0) @[dec_tlu_ctl.scala 2527:38] - node _T_2469 = bits(mfdht, 5, 0) @[dec_tlu_ctl.scala 2527:78] - node _T_2470 = cat(UInt<26>("h00"), _T_2469) @[Cat.scala 29:58] - node _T_2471 = bits(io.csr_pkt.csr_mfdhs, 0, 0) @[dec_tlu_ctl.scala 2528:38] - node _T_2472 = bits(mfdhs, 1, 0) @[dec_tlu_ctl.scala 2528:78] - node _T_2473 = cat(UInt<30>("h00"), _T_2472) @[Cat.scala 29:58] - node _T_2474 = bits(io.csr_pkt.csr_mhpme3, 0, 0) @[dec_tlu_ctl.scala 2529:39] - node _T_2475 = bits(mhpme3, 9, 0) @[dec_tlu_ctl.scala 2529:79] - node _T_2476 = cat(UInt<22>("h00"), _T_2475) @[Cat.scala 29:58] - node _T_2477 = bits(io.csr_pkt.csr_mhpme4, 0, 0) @[dec_tlu_ctl.scala 2530:39] - node _T_2478 = bits(mhpme4, 9, 0) @[dec_tlu_ctl.scala 2530:79] - node _T_2479 = cat(UInt<22>("h00"), _T_2478) @[Cat.scala 29:58] - node _T_2480 = bits(io.csr_pkt.csr_mhpme5, 0, 0) @[dec_tlu_ctl.scala 2531:39] - node _T_2481 = bits(mhpme5, 9, 0) @[dec_tlu_ctl.scala 2531:78] - node _T_2482 = cat(UInt<22>("h00"), _T_2481) @[Cat.scala 29:58] - node _T_2483 = bits(io.csr_pkt.csr_mhpme6, 0, 0) @[dec_tlu_ctl.scala 2532:39] - node _T_2484 = bits(mhpme6, 9, 0) @[dec_tlu_ctl.scala 2532:78] - node _T_2485 = cat(UInt<22>("h00"), _T_2484) @[Cat.scala 29:58] - node _T_2486 = bits(io.csr_pkt.csr_mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2533:46] - node _T_2487 = bits(mcountinhibit, 6, 0) @[dec_tlu_ctl.scala 2533:86] - node _T_2488 = cat(UInt<25>("h00"), _T_2487) @[Cat.scala 29:58] - node _T_2489 = bits(io.csr_pkt.csr_mpmc, 0, 0) @[dec_tlu_ctl.scala 2534:37] - node _T_2490 = cat(UInt<30>("h00"), mpmc) @[Cat.scala 29:58] - node _T_2491 = cat(_T_2490, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2492 = bits(io.dec_timer_read_d, 0, 0) @[dec_tlu_ctl.scala 2535:37] - node _T_2493 = bits(io.dec_timer_rddata_d, 31, 0) @[dec_tlu_ctl.scala 2535:76] - node _T_2494 = mux(_T_2328, UInt<32>("h040001104"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2495 = mux(_T_2329, UInt<32>("h045"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2496 = mux(_T_2330, UInt<32>("h010"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2497 = mux(_T_2331, UInt<32>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2498 = mux(_T_2332, _T_2333, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2499 = mux(_T_2334, _T_2342, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2500 = mux(_T_2343, _T_2347, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2501 = mux(_T_2348, _T_2360, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2502 = mux(_T_2361, _T_2373, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2503 = mux(_T_2374, _T_2375, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2504 = mux(_T_2376, _T_2377, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2505 = mux(_T_2378, _T_2379, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2506 = mux(_T_2380, _T_2381, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2507 = mux(_T_2382, _T_2383, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2508 = mux(_T_2384, _T_2385, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2509 = mux(_T_2386, _T_2387, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2510 = mux(_T_2388, _T_2390, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2511 = mux(_T_2391, _T_2392, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2512 = mux(_T_2393, _T_2394, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2513 = mux(_T_2395, _T_2396, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2514 = mux(_T_2397, _T_2398, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2515 = mux(_T_2399, _T_2401, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2516 = mux(_T_2402, _T_2404, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2517 = mux(_T_2405, _T_2407, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2518 = mux(_T_2408, _T_2410, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2519 = mux(_T_2411, _T_2413, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2520 = mux(_T_2414, _T_2416, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2521 = mux(_T_2417, _T_2420, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2522 = mux(_T_2421, _T_2422, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2523 = mux(_T_2423, _T_2424, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2524 = mux(_T_2425, _T_2426, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2525 = mux(_T_2427, _T_2428, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2526 = mux(_T_2429, _T_2438, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2527 = mux(_T_2439, _T_2441, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2528 = mux(_T_2442, _T_2443, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2529 = mux(_T_2444, _T_2445, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2530 = mux(_T_2446, _T_2447, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2531 = mux(_T_2448, _T_2449, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2532 = mux(_T_2450, _T_2451, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2533 = mux(_T_2452, _T_2453, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2534 = mux(_T_2454, _T_2455, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2535 = mux(_T_2456, _T_2457, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2536 = mux(_T_2458, _T_2459, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2537 = mux(_T_2460, _T_2461, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2538 = mux(_T_2462, _T_2463, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2539 = mux(_T_2464, _T_2465, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2540 = mux(_T_2466, _T_2467, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2541 = mux(_T_2468, _T_2470, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2542 = mux(_T_2471, _T_2473, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2543 = mux(_T_2474, _T_2476, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2544 = mux(_T_2477, _T_2479, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2545 = mux(_T_2480, _T_2482, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2546 = mux(_T_2483, _T_2485, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2547 = mux(_T_2486, _T_2488, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2548 = mux(_T_2489, _T_2491, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2549 = mux(_T_2492, _T_2493, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2550 = or(_T_2494, _T_2495) @[Mux.scala 27:72] - node _T_2551 = or(_T_2550, _T_2496) @[Mux.scala 27:72] - node _T_2552 = or(_T_2551, _T_2497) @[Mux.scala 27:72] - node _T_2553 = or(_T_2552, _T_2498) @[Mux.scala 27:72] - node _T_2554 = or(_T_2553, _T_2499) @[Mux.scala 27:72] - node _T_2555 = or(_T_2554, _T_2500) @[Mux.scala 27:72] - node _T_2556 = or(_T_2555, _T_2501) @[Mux.scala 27:72] - node _T_2557 = or(_T_2556, _T_2502) @[Mux.scala 27:72] - node _T_2558 = or(_T_2557, _T_2503) @[Mux.scala 27:72] - node _T_2559 = or(_T_2558, _T_2504) @[Mux.scala 27:72] - node _T_2560 = or(_T_2559, _T_2505) @[Mux.scala 27:72] + node _T_2338 = bits(io.csr_pkt.csr_misa, 0, 0) @[dec_tlu_ctl.scala 2480:61] + node _T_2339 = bits(io.csr_pkt.csr_mvendorid, 0, 0) @[dec_tlu_ctl.scala 2481:42] + node _T_2340 = bits(io.csr_pkt.csr_marchid, 0, 0) @[dec_tlu_ctl.scala 2482:40] + node _T_2341 = bits(io.csr_pkt.csr_mimpid, 0, 0) @[dec_tlu_ctl.scala 2483:39] + node _T_2342 = bits(io.csr_pkt.csr_mhartid, 0, 0) @[dec_tlu_ctl.scala 2484:40] + node _T_2343 = cat(io.core_id, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_2344 = bits(io.csr_pkt.csr_mstatus, 0, 0) @[dec_tlu_ctl.scala 2485:40] + node _T_2345 = bits(io.mstatus, 1, 1) @[dec_tlu_ctl.scala 2485:103] + node _T_2346 = bits(io.mstatus, 0, 0) @[dec_tlu_ctl.scala 2485:128] + node _T_2347 = cat(UInt<3>("h00"), _T_2346) @[Cat.scala 29:58] + node _T_2348 = cat(_T_2347, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2349 = cat(UInt<3>("h00"), _T_2345) @[Cat.scala 29:58] + node _T_2350 = cat(UInt<19>("h00"), UInt<2>("h03")) @[Cat.scala 29:58] + node _T_2351 = cat(_T_2350, _T_2349) @[Cat.scala 29:58] + node _T_2352 = cat(_T_2351, _T_2348) @[Cat.scala 29:58] + node _T_2353 = bits(io.csr_pkt.csr_mtvec, 0, 0) @[dec_tlu_ctl.scala 2486:38] + node _T_2354 = bits(io.mtvec, 30, 1) @[dec_tlu_ctl.scala 2486:70] + node _T_2355 = bits(io.mtvec, 0, 0) @[dec_tlu_ctl.scala 2486:96] + node _T_2356 = cat(_T_2354, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2357 = cat(_T_2356, _T_2355) @[Cat.scala 29:58] + node _T_2358 = bits(io.csr_pkt.csr_mip, 0, 0) @[dec_tlu_ctl.scala 2487:36] + node _T_2359 = bits(io.mip, 5, 3) @[dec_tlu_ctl.scala 2487:78] + node _T_2360 = bits(io.mip, 2, 2) @[dec_tlu_ctl.scala 2487:102] + node _T_2361 = bits(io.mip, 1, 1) @[dec_tlu_ctl.scala 2487:123] + node _T_2362 = bits(io.mip, 0, 0) @[dec_tlu_ctl.scala 2487:144] + node _T_2363 = cat(_T_2362, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2364 = cat(_T_2361, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2365 = cat(_T_2364, _T_2363) @[Cat.scala 29:58] + node _T_2366 = cat(_T_2360, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2367 = cat(UInt<1>("h00"), _T_2359) @[Cat.scala 29:58] + node _T_2368 = cat(_T_2367, UInt<16>("h00")) @[Cat.scala 29:58] + node _T_2369 = cat(_T_2368, _T_2366) @[Cat.scala 29:58] + node _T_2370 = cat(_T_2369, _T_2365) @[Cat.scala 29:58] + node _T_2371 = bits(io.csr_pkt.csr_mie, 0, 0) @[dec_tlu_ctl.scala 2488:36] + node _T_2372 = bits(mie, 5, 3) @[dec_tlu_ctl.scala 2488:75] + node _T_2373 = bits(mie, 2, 2) @[dec_tlu_ctl.scala 2488:96] + node _T_2374 = bits(mie, 1, 1) @[dec_tlu_ctl.scala 2488:114] + node _T_2375 = bits(mie, 0, 0) @[dec_tlu_ctl.scala 2488:132] + node _T_2376 = cat(_T_2375, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2377 = cat(_T_2374, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2378 = cat(_T_2377, _T_2376) @[Cat.scala 29:58] + node _T_2379 = cat(_T_2373, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2380 = cat(UInt<1>("h00"), _T_2372) @[Cat.scala 29:58] + node _T_2381 = cat(_T_2380, UInt<16>("h00")) @[Cat.scala 29:58] + node _T_2382 = cat(_T_2381, _T_2379) @[Cat.scala 29:58] + node _T_2383 = cat(_T_2382, _T_2378) @[Cat.scala 29:58] + node _T_2384 = bits(io.csr_pkt.csr_mcyclel, 0, 0) @[dec_tlu_ctl.scala 2489:40] + node _T_2385 = bits(mcyclel, 31, 0) @[dec_tlu_ctl.scala 2489:65] + node _T_2386 = bits(io.csr_pkt.csr_mcycleh, 0, 0) @[dec_tlu_ctl.scala 2490:40] + node _T_2387 = bits(mcycleh_inc, 31, 0) @[dec_tlu_ctl.scala 2490:69] + node _T_2388 = bits(io.csr_pkt.csr_minstretl, 0, 0) @[dec_tlu_ctl.scala 2491:42] + node _T_2389 = bits(minstretl, 31, 0) @[dec_tlu_ctl.scala 2491:72] + node _T_2390 = bits(io.csr_pkt.csr_minstreth, 0, 0) @[dec_tlu_ctl.scala 2492:42] + node _T_2391 = bits(minstreth_inc, 31, 0) @[dec_tlu_ctl.scala 2492:72] + node _T_2392 = bits(io.csr_pkt.csr_mscratch, 0, 0) @[dec_tlu_ctl.scala 2493:41] + node _T_2393 = bits(mscratch, 31, 0) @[dec_tlu_ctl.scala 2493:66] + node _T_2394 = bits(io.csr_pkt.csr_mepc, 0, 0) @[dec_tlu_ctl.scala 2494:37] + node _T_2395 = cat(io.mepc, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2396 = bits(io.csr_pkt.csr_mcause, 0, 0) @[dec_tlu_ctl.scala 2495:39] + node _T_2397 = bits(mcause, 31, 0) @[dec_tlu_ctl.scala 2495:64] + node _T_2398 = bits(io.csr_pkt.csr_mscause, 0, 0) @[dec_tlu_ctl.scala 2496:40] + node _T_2399 = bits(mscause, 3, 0) @[dec_tlu_ctl.scala 2496:80] + node _T_2400 = cat(UInt<28>("h00"), _T_2399) @[Cat.scala 29:58] + node _T_2401 = bits(io.csr_pkt.csr_mtval, 0, 0) @[dec_tlu_ctl.scala 2497:38] + node _T_2402 = bits(mtval, 31, 0) @[dec_tlu_ctl.scala 2497:63] + node _T_2403 = bits(io.csr_pkt.csr_mrac, 0, 0) @[dec_tlu_ctl.scala 2498:37] + node _T_2404 = bits(mrac, 31, 0) @[dec_tlu_ctl.scala 2498:62] + node _T_2405 = bits(io.csr_pkt.csr_mdseac, 0, 0) @[dec_tlu_ctl.scala 2499:39] + node _T_2406 = bits(mdseac, 31, 0) @[dec_tlu_ctl.scala 2499:64] + node _T_2407 = bits(io.csr_pkt.csr_meivt, 0, 0) @[dec_tlu_ctl.scala 2500:38] + node _T_2408 = cat(meivt, UInt<10>("h00")) @[Cat.scala 29:58] + node _T_2409 = bits(io.csr_pkt.csr_meihap, 0, 0) @[dec_tlu_ctl.scala 2501:39] + node _T_2410 = cat(meivt, meihap) @[Cat.scala 29:58] + node _T_2411 = cat(_T_2410, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_2412 = bits(io.csr_pkt.csr_meicurpl, 0, 0) @[dec_tlu_ctl.scala 2502:41] + node _T_2413 = bits(meicurpl, 3, 0) @[dec_tlu_ctl.scala 2502:81] + node _T_2414 = cat(UInt<28>("h00"), _T_2413) @[Cat.scala 29:58] + node _T_2415 = bits(io.csr_pkt.csr_meicidpl, 0, 0) @[dec_tlu_ctl.scala 2503:41] + node _T_2416 = bits(meicidpl, 3, 0) @[dec_tlu_ctl.scala 2503:81] + node _T_2417 = cat(UInt<28>("h00"), _T_2416) @[Cat.scala 29:58] + node _T_2418 = bits(io.csr_pkt.csr_meipt, 0, 0) @[dec_tlu_ctl.scala 2504:38] + node _T_2419 = bits(meipt, 3, 0) @[dec_tlu_ctl.scala 2504:78] + node _T_2420 = cat(UInt<28>("h00"), _T_2419) @[Cat.scala 29:58] + node _T_2421 = bits(io.csr_pkt.csr_mcgc, 0, 0) @[dec_tlu_ctl.scala 2505:37] + node _T_2422 = bits(mcgc, 8, 0) @[dec_tlu_ctl.scala 2505:77] + node _T_2423 = cat(UInt<23>("h00"), _T_2422) @[Cat.scala 29:58] + node _T_2424 = bits(io.csr_pkt.csr_mfdc, 0, 0) @[dec_tlu_ctl.scala 2506:37] + node _T_2425 = bits(mfdc, 18, 0) @[dec_tlu_ctl.scala 2506:77] + node _T_2426 = cat(UInt<13>("h00"), _T_2425) @[Cat.scala 29:58] + node _T_2427 = bits(io.csr_pkt.csr_dcsr, 0, 0) @[dec_tlu_ctl.scala 2507:37] + node _T_2428 = bits(io.dcsr, 15, 2) @[dec_tlu_ctl.scala 2507:85] + node _T_2429 = cat(UInt<16>("h04000"), _T_2428) @[Cat.scala 29:58] + node _T_2430 = cat(_T_2429, UInt<2>("h03")) @[Cat.scala 29:58] + node _T_2431 = bits(io.csr_pkt.csr_dpc, 0, 0) @[dec_tlu_ctl.scala 2508:36] + node _T_2432 = cat(io.dpc, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2433 = bits(io.csr_pkt.csr_dicad0, 0, 0) @[dec_tlu_ctl.scala 2509:39] + node _T_2434 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2509:64] + node _T_2435 = bits(io.csr_pkt.csr_dicad0h, 0, 0) @[dec_tlu_ctl.scala 2510:40] + node _T_2436 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2510:65] + node _T_2437 = bits(io.csr_pkt.csr_dicad1, 0, 0) @[dec_tlu_ctl.scala 2511:39] + node _T_2438 = bits(dicad1, 31, 0) @[dec_tlu_ctl.scala 2511:64] + node _T_2439 = bits(io.csr_pkt.csr_dicawics, 0, 0) @[dec_tlu_ctl.scala 2512:41] + node _T_2440 = bits(dicawics, 16, 16) @[dec_tlu_ctl.scala 2512:80] + node _T_2441 = bits(dicawics, 15, 14) @[dec_tlu_ctl.scala 2512:104] + node _T_2442 = bits(dicawics, 13, 0) @[dec_tlu_ctl.scala 2512:131] + node _T_2443 = cat(UInt<3>("h00"), _T_2442) @[Cat.scala 29:58] + node _T_2444 = cat(_T_2443, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2445 = cat(UInt<2>("h00"), _T_2441) @[Cat.scala 29:58] + node _T_2446 = cat(UInt<7>("h00"), _T_2440) @[Cat.scala 29:58] + node _T_2447 = cat(_T_2446, _T_2445) @[Cat.scala 29:58] + node _T_2448 = cat(_T_2447, _T_2444) @[Cat.scala 29:58] + node _T_2449 = bits(io.csr_pkt.csr_mtsel, 0, 0) @[dec_tlu_ctl.scala 2513:38] + node _T_2450 = bits(mtsel, 1, 0) @[dec_tlu_ctl.scala 2513:78] + node _T_2451 = cat(UInt<30>("h00"), _T_2450) @[Cat.scala 29:58] + node _T_2452 = bits(io.csr_pkt.csr_mtdata1, 0, 0) @[dec_tlu_ctl.scala 2514:40] + node _T_2453 = bits(mtdata1_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2514:74] + node _T_2454 = bits(io.csr_pkt.csr_mtdata2, 0, 0) @[dec_tlu_ctl.scala 2515:40] + node _T_2455 = bits(mtdata2_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2515:74] + node _T_2456 = bits(io.csr_pkt.csr_micect, 0, 0) @[dec_tlu_ctl.scala 2516:39] + node _T_2457 = bits(micect, 31, 0) @[dec_tlu_ctl.scala 2516:64] + node _T_2458 = bits(io.csr_pkt.csr_miccmect, 0, 0) @[dec_tlu_ctl.scala 2517:41] + node _T_2459 = bits(miccmect, 31, 0) @[dec_tlu_ctl.scala 2517:66] + node _T_2460 = bits(io.csr_pkt.csr_mdccmect, 0, 0) @[dec_tlu_ctl.scala 2518:41] + node _T_2461 = bits(mdccmect, 31, 0) @[dec_tlu_ctl.scala 2518:66] + node _T_2462 = bits(io.csr_pkt.csr_mhpmc3, 0, 0) @[dec_tlu_ctl.scala 2519:39] + node _T_2463 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2519:64] + node _T_2464 = bits(io.csr_pkt.csr_mhpmc4, 0, 0) @[dec_tlu_ctl.scala 2520:39] + node _T_2465 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2520:64] + node _T_2466 = bits(io.csr_pkt.csr_mhpmc5, 0, 0) @[dec_tlu_ctl.scala 2521:39] + node _T_2467 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2521:64] + node _T_2468 = bits(io.csr_pkt.csr_mhpmc6, 0, 0) @[dec_tlu_ctl.scala 2522:39] + node _T_2469 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2522:64] + node _T_2470 = bits(io.csr_pkt.csr_mhpmc3h, 0, 0) @[dec_tlu_ctl.scala 2523:40] + node _T_2471 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2523:65] + node _T_2472 = bits(io.csr_pkt.csr_mhpmc4h, 0, 0) @[dec_tlu_ctl.scala 2524:40] + node _T_2473 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2524:65] + node _T_2474 = bits(io.csr_pkt.csr_mhpmc5h, 0, 0) @[dec_tlu_ctl.scala 2525:40] + node _T_2475 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2525:65] + node _T_2476 = bits(io.csr_pkt.csr_mhpmc6h, 0, 0) @[dec_tlu_ctl.scala 2526:40] + node _T_2477 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2526:65] + node _T_2478 = bits(io.csr_pkt.csr_mfdht, 0, 0) @[dec_tlu_ctl.scala 2527:38] + node _T_2479 = bits(mfdht, 5, 0) @[dec_tlu_ctl.scala 2527:78] + node _T_2480 = cat(UInt<26>("h00"), _T_2479) @[Cat.scala 29:58] + node _T_2481 = bits(io.csr_pkt.csr_mfdhs, 0, 0) @[dec_tlu_ctl.scala 2528:38] + node _T_2482 = bits(mfdhs, 1, 0) @[dec_tlu_ctl.scala 2528:78] + node _T_2483 = cat(UInt<30>("h00"), _T_2482) @[Cat.scala 29:58] + node _T_2484 = bits(io.csr_pkt.csr_mhpme3, 0, 0) @[dec_tlu_ctl.scala 2529:39] + node _T_2485 = bits(mhpme3, 9, 0) @[dec_tlu_ctl.scala 2529:79] + node _T_2486 = cat(UInt<22>("h00"), _T_2485) @[Cat.scala 29:58] + node _T_2487 = bits(io.csr_pkt.csr_mhpme4, 0, 0) @[dec_tlu_ctl.scala 2530:39] + node _T_2488 = bits(mhpme4, 9, 0) @[dec_tlu_ctl.scala 2530:79] + node _T_2489 = cat(UInt<22>("h00"), _T_2488) @[Cat.scala 29:58] + node _T_2490 = bits(io.csr_pkt.csr_mhpme5, 0, 0) @[dec_tlu_ctl.scala 2531:39] + node _T_2491 = bits(mhpme5, 9, 0) @[dec_tlu_ctl.scala 2531:78] + node _T_2492 = cat(UInt<22>("h00"), _T_2491) @[Cat.scala 29:58] + node _T_2493 = bits(io.csr_pkt.csr_mhpme6, 0, 0) @[dec_tlu_ctl.scala 2532:39] + node _T_2494 = bits(mhpme6, 9, 0) @[dec_tlu_ctl.scala 2532:78] + node _T_2495 = cat(UInt<22>("h00"), _T_2494) @[Cat.scala 29:58] + node _T_2496 = bits(io.csr_pkt.csr_mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2533:46] + node _T_2497 = bits(mcountinhibit, 6, 0) @[dec_tlu_ctl.scala 2533:86] + node _T_2498 = cat(UInt<25>("h00"), _T_2497) @[Cat.scala 29:58] + node _T_2499 = bits(io.csr_pkt.csr_mpmc, 0, 0) @[dec_tlu_ctl.scala 2534:37] + node _T_2500 = cat(UInt<30>("h00"), mpmc) @[Cat.scala 29:58] + node _T_2501 = cat(_T_2500, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2502 = bits(io.dec_timer_read_d, 0, 0) @[dec_tlu_ctl.scala 2535:37] + node _T_2503 = bits(io.dec_timer_rddata_d, 31, 0) @[dec_tlu_ctl.scala 2535:76] + node _T_2504 = mux(_T_2338, UInt<32>("h040001104"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2505 = mux(_T_2339, UInt<32>("h045"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2506 = mux(_T_2340, UInt<32>("h010"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2507 = mux(_T_2341, UInt<32>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2508 = mux(_T_2342, _T_2343, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2509 = mux(_T_2344, _T_2352, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2510 = mux(_T_2353, _T_2357, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2511 = mux(_T_2358, _T_2370, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2512 = mux(_T_2371, _T_2383, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2513 = mux(_T_2384, _T_2385, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2514 = mux(_T_2386, _T_2387, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2515 = mux(_T_2388, _T_2389, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2516 = mux(_T_2390, _T_2391, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2517 = mux(_T_2392, _T_2393, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2518 = mux(_T_2394, _T_2395, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2519 = mux(_T_2396, _T_2397, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2520 = mux(_T_2398, _T_2400, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2521 = mux(_T_2401, _T_2402, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2522 = mux(_T_2403, _T_2404, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2523 = mux(_T_2405, _T_2406, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2524 = mux(_T_2407, _T_2408, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2525 = mux(_T_2409, _T_2411, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2526 = mux(_T_2412, _T_2414, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2527 = mux(_T_2415, _T_2417, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2528 = mux(_T_2418, _T_2420, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2529 = mux(_T_2421, _T_2423, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2530 = mux(_T_2424, _T_2426, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2531 = mux(_T_2427, _T_2430, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2532 = mux(_T_2431, _T_2432, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2533 = mux(_T_2433, _T_2434, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2534 = mux(_T_2435, _T_2436, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2535 = mux(_T_2437, _T_2438, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2536 = mux(_T_2439, _T_2448, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2537 = mux(_T_2449, _T_2451, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2538 = mux(_T_2452, _T_2453, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2539 = mux(_T_2454, _T_2455, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2540 = mux(_T_2456, _T_2457, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2541 = mux(_T_2458, _T_2459, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2542 = mux(_T_2460, _T_2461, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2543 = mux(_T_2462, _T_2463, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2544 = mux(_T_2464, _T_2465, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2545 = mux(_T_2466, _T_2467, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2546 = mux(_T_2468, _T_2469, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2547 = mux(_T_2470, _T_2471, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2548 = mux(_T_2472, _T_2473, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2549 = mux(_T_2474, _T_2475, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2550 = mux(_T_2476, _T_2477, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2551 = mux(_T_2478, _T_2480, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2552 = mux(_T_2481, _T_2483, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2553 = mux(_T_2484, _T_2486, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2554 = mux(_T_2487, _T_2489, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2555 = mux(_T_2490, _T_2492, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2556 = mux(_T_2493, _T_2495, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2557 = mux(_T_2496, _T_2498, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2558 = mux(_T_2499, _T_2501, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2559 = mux(_T_2502, _T_2503, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2560 = or(_T_2504, _T_2505) @[Mux.scala 27:72] node _T_2561 = or(_T_2560, _T_2506) @[Mux.scala 27:72] node _T_2562 = or(_T_2561, _T_2507) @[Mux.scala 27:72] node _T_2563 = or(_T_2562, _T_2508) @[Mux.scala 27:72] @@ -76103,9 +76103,19 @@ circuit quasar : node _T_2602 = or(_T_2601, _T_2547) @[Mux.scala 27:72] node _T_2603 = or(_T_2602, _T_2548) @[Mux.scala 27:72] node _T_2604 = or(_T_2603, _T_2549) @[Mux.scala 27:72] - wire _T_2605 : UInt @[Mux.scala 27:72] - _T_2605 <= _T_2604 @[Mux.scala 27:72] - io.dec_csr_rddata_d <= _T_2605 @[dec_tlu_ctl.scala 2479:21] + node _T_2605 = or(_T_2604, _T_2550) @[Mux.scala 27:72] + node _T_2606 = or(_T_2605, _T_2551) @[Mux.scala 27:72] + node _T_2607 = or(_T_2606, _T_2552) @[Mux.scala 27:72] + node _T_2608 = or(_T_2607, _T_2553) @[Mux.scala 27:72] + node _T_2609 = or(_T_2608, _T_2554) @[Mux.scala 27:72] + node _T_2610 = or(_T_2609, _T_2555) @[Mux.scala 27:72] + node _T_2611 = or(_T_2610, _T_2556) @[Mux.scala 27:72] + node _T_2612 = or(_T_2611, _T_2557) @[Mux.scala 27:72] + node _T_2613 = or(_T_2612, _T_2558) @[Mux.scala 27:72] + node _T_2614 = or(_T_2613, _T_2559) @[Mux.scala 27:72] + wire _T_2615 : UInt @[Mux.scala 27:72] + _T_2615 <= _T_2614 @[Mux.scala 27:72] + io.dec_csr_rddata_d <= _T_2615 @[dec_tlu_ctl.scala 2479:21] module dec_decode_csr_read : input clock : Clock @@ -95823,7 +95833,7 @@ circuit quasar : node _T_748 = and(ld_fwddata_buf_hi_initial, ibuf_data) @[lsu_bus_buffer.scala 175:32] node _T_749 = or(_T_747, _T_748) @[lsu_bus_buffer.scala 174:103] io.ld_fwddata_buf_hi <= _T_749 @[lsu_bus_buffer.scala 171:24] - node bus_coalescing_disable = or(io.tlu_busbuff.dec_tlu_wb_coalescing_disable, UInt<1>("h01")) @[lsu_bus_buffer.scala 177:77] + node bus_coalescing_disable = or(io.tlu_busbuff.dec_tlu_wb_coalescing_disable, UInt<1>("h00")) @[lsu_bus_buffer.scala 177:77] node _T_750 = mux(io.lsu_pkt_r.bits.by, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_751 = mux(io.lsu_pkt_r.bits.half, UInt<4>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_752 = mux(io.lsu_pkt_r.bits.word, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72] @@ -108983,4831 +108993,6 @@ circuit quasar : clkhdr.EN <= io.en @[lib.scala 337:18] clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - extmodule gated_latch_849 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_849 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_849 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_850 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_850 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_850 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_851 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_851 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_851 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_852 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_852 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_852 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_853 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_853 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_853 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_854 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_854 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_854 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_855 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_855 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_855 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_856 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_856 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_856 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_857 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_857 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_857 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_858 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_858 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_858 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - module axi4_to_ahb : - input clock : Clock - input reset : AsyncReset - output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ahb : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}} - - wire buf_rst : UInt<1> - buf_rst <= UInt<1>("h00") - buf_rst <= UInt<1>("h00") @[axi4_to_ahb.scala 21:11] - io.ahb.out.htrans <= UInt<1>("h00") @[axi4_to_ahb.scala 22:21] - wire buf_state_en : UInt<1> - buf_state_en <= UInt<1>("h00") - wire ahbm_clk : Clock @[axi4_to_ahb.scala 24:22] - wire ahbm_addr_clk : Clock @[axi4_to_ahb.scala 25:27] - wire ahbm_data_clk : Clock @[axi4_to_ahb.scala 26:27] - wire buf_state : UInt<3> - buf_state <= UInt<3>("h00") - wire buf_nxtstate : UInt<3> - buf_nxtstate <= UInt<3>("h00") - node _T = bits(buf_state_en, 0, 0) @[axi4_to_ahb.scala 30:70] - node _T_1 = mux(_T, buf_nxtstate, buf_state) @[axi4_to_ahb.scala 30:50] - node _T_2 = eq(buf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 30:108] - node _T_3 = bits(_T_2, 0, 0) @[Bitwise.scala 72:15] - node _T_4 = mux(_T_3, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_5 = and(_T_1, _T_4) @[axi4_to_ahb.scala 30:98] - reg _T_6 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 30:45] - _T_6 <= _T_5 @[axi4_to_ahb.scala 30:45] - buf_state <= _T_6 @[axi4_to_ahb.scala 30:13] - wire slave_valid : UInt<1> - slave_valid <= UInt<1>("h00") - wire slave_ready : UInt<1> - slave_ready <= UInt<1>("h00") - wire slave_tag : UInt<1> - slave_tag <= UInt<1>("h00") - wire slave_rdata : UInt<64> - slave_rdata <= UInt<64>("h00") - wire slave_opc : UInt<4> - slave_opc <= UInt<4>("h00") - wire wrbuf_en : UInt<1> - wrbuf_en <= UInt<1>("h00") - wire wrbuf_data_en : UInt<1> - wrbuf_data_en <= UInt<1>("h00") - wire wrbuf_cmd_sent : UInt<1> - wrbuf_cmd_sent <= UInt<1>("h00") - wire wrbuf_rst : UInt<1> - wrbuf_rst <= UInt<1>("h00") - wire wrbuf_vld : UInt<1> - wrbuf_vld <= UInt<1>("h00") - wire wrbuf_data_vld : UInt<1> - wrbuf_data_vld <= UInt<1>("h00") - wire wrbuf_tag : UInt<1> - wrbuf_tag <= UInt<1>("h00") - wire wrbuf_size : UInt<3> - wrbuf_size <= UInt<3>("h00") - wire wrbuf_addr : UInt<32> - wrbuf_addr <= UInt<32>("h00") - wire wrbuf_data : UInt<64> - wrbuf_data <= UInt<64>("h00") - wire wrbuf_byteen : UInt<8> - wrbuf_byteen <= UInt<8>("h00") - wire bus_write_clk_en : UInt<1> - bus_write_clk_en <= UInt<1>("h00") - wire bus_clk : Clock @[axi4_to_ahb.scala 50:21] - wire bus_write_clk : Clock @[axi4_to_ahb.scala 51:27] - wire master_valid : UInt<1> - master_valid <= UInt<1>("h00") - wire master_ready : UInt<1> - master_ready <= UInt<1>("h00") - wire master_tag : UInt<1> - master_tag <= UInt<1>("h00") - wire master_addr : UInt<32> - master_addr <= UInt<32>("h00") - wire master_wdata : UInt<64> - master_wdata <= UInt<64>("h00") - wire master_size : UInt<3> - master_size <= UInt<3>("h00") - wire master_opc : UInt<3> - master_opc <= UInt<3>("h00") - wire master_byteen : UInt<8> - master_byteen <= UInt<8>("h00") - wire buf_addr : UInt<32> - buf_addr <= UInt<32>("h00") - wire buf_size : UInt<2> - buf_size <= UInt<2>("h00") - wire buf_write : UInt<1> - buf_write <= UInt<1>("h00") - wire buf_byteen : UInt<8> - buf_byteen <= UInt<8>("h00") - wire buf_aligned : UInt<1> - buf_aligned <= UInt<1>("h00") - wire buf_data : UInt<64> - buf_data <= UInt<64>("h00") - wire buf_tag : UInt<1> - buf_tag <= UInt<1>("h00") - wire buf_tag_in : UInt<1> - buf_tag_in <= UInt<1>("h00") - wire buf_addr_in : UInt<32> - buf_addr_in <= UInt<32>("h00") - wire buf_byteen_in : UInt<8> - buf_byteen_in <= UInt<8>("h00") - wire buf_data_in : UInt<64> - buf_data_in <= UInt<64>("h00") - wire buf_write_in : UInt<1> - buf_write_in <= UInt<1>("h00") - wire buf_aligned_in : UInt<1> - buf_aligned_in <= UInt<1>("h00") - wire buf_size_in : UInt<3> - buf_size_in <= UInt<3>("h00") - wire buf_wr_en : UInt<1> - buf_wr_en <= UInt<1>("h00") - wire buf_data_wr_en : UInt<1> - buf_data_wr_en <= UInt<1>("h00") - wire slvbuf_error_en : UInt<1> - slvbuf_error_en <= UInt<1>("h00") - wire wr_cmd_vld : UInt<1> - wr_cmd_vld <= UInt<1>("h00") - wire cmd_done_rst : UInt<1> - cmd_done_rst <= UInt<1>("h00") - wire cmd_done : UInt<1> - cmd_done <= UInt<1>("h00") - wire cmd_doneQ : UInt<1> - cmd_doneQ <= UInt<1>("h00") - wire trxn_done : UInt<1> - trxn_done <= UInt<1>("h00") - wire buf_cmd_byte_ptr : UInt<3> - buf_cmd_byte_ptr <= UInt<3>("h00") - wire buf_cmd_byte_ptrQ : UInt<3> - buf_cmd_byte_ptrQ <= UInt<3>("h00") - wire buf_cmd_nxtbyte_ptr : UInt<3> - buf_cmd_nxtbyte_ptr <= UInt<3>("h00") - wire buf_cmd_byte_ptr_en : UInt<1> - buf_cmd_byte_ptr_en <= UInt<1>("h00") - wire found : UInt<1> - found <= UInt<1>("h00") - wire slave_valid_pre : UInt<1> - slave_valid_pre <= UInt<1>("h00") - wire ahb_hready_q : UInt<1> - ahb_hready_q <= UInt<1>("h00") - wire ahb_hresp_q : UInt<1> - ahb_hresp_q <= UInt<1>("h00") - wire ahb_htrans_q : UInt<2> - ahb_htrans_q <= UInt<2>("h00") - wire ahb_hwrite_q : UInt<1> - ahb_hwrite_q <= UInt<1>("h00") - wire ahb_hrdata_q : UInt<64> - ahb_hrdata_q <= UInt<64>("h00") - wire slvbuf_write : UInt<1> - slvbuf_write <= UInt<1>("h00") - wire slvbuf_error : UInt<1> - slvbuf_error <= UInt<1>("h00") - wire slvbuf_tag : UInt<1> - slvbuf_tag <= UInt<1>("h00") - wire slvbuf_error_in : UInt<1> - slvbuf_error_in <= UInt<1>("h00") - wire slvbuf_wr_en : UInt<1> - slvbuf_wr_en <= UInt<1>("h00") - wire bypass_en : UInt<1> - bypass_en <= UInt<1>("h00") - wire rd_bypass_idle : UInt<1> - rd_bypass_idle <= UInt<1>("h00") - wire last_addr_en : UInt<1> - last_addr_en <= UInt<1>("h00") - wire last_bus_addr : UInt<32> - last_bus_addr <= UInt<32>("h00") - wire buf_clken : UInt<1> - buf_clken <= UInt<1>("h00") - wire slvbuf_clken : UInt<1> - slvbuf_clken <= UInt<1>("h00") - wire ahbm_addr_clken : UInt<1> - ahbm_addr_clken <= UInt<1>("h00") - wire ahbm_data_clken : UInt<1> - ahbm_data_clken <= UInt<1>("h00") - wire buf_clk : Clock @[axi4_to_ahb.scala 118:21] - node _T_7 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 139:27] - wr_cmd_vld <= _T_7 @[axi4_to_ahb.scala 139:14] - node _T_8 = or(wr_cmd_vld, io.axi.ar.valid) @[axi4_to_ahb.scala 140:30] - master_valid <= _T_8 @[axi4_to_ahb.scala 140:16] - node _T_9 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 141:38] - node _T_10 = bits(wrbuf_tag, 0, 0) @[axi4_to_ahb.scala 141:51] - node _T_11 = bits(io.axi.ar.bits.id, 0, 0) @[axi4_to_ahb.scala 141:82] - node _T_12 = mux(_T_9, _T_10, _T_11) @[axi4_to_ahb.scala 141:20] - master_tag <= _T_12 @[axi4_to_ahb.scala 141:14] - node _T_13 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 142:38] - node _T_14 = mux(_T_13, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 142:20] - master_opc <= _T_14 @[axi4_to_ahb.scala 142:14] - node _T_15 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 143:39] - node _T_16 = bits(wrbuf_addr, 31, 0) @[axi4_to_ahb.scala 143:53] - node _T_17 = bits(io.axi.ar.bits.addr, 31, 0) @[axi4_to_ahb.scala 143:81] - node _T_18 = mux(_T_15, _T_16, _T_17) @[axi4_to_ahb.scala 143:21] - master_addr <= _T_18 @[axi4_to_ahb.scala 143:15] - node _T_19 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 144:39] - node _T_20 = bits(wrbuf_size, 2, 0) @[axi4_to_ahb.scala 144:53] - node _T_21 = bits(io.axi.ar.bits.size, 2, 0) @[axi4_to_ahb.scala 144:80] - node _T_22 = mux(_T_19, _T_20, _T_21) @[axi4_to_ahb.scala 144:21] - master_size <= _T_22 @[axi4_to_ahb.scala 144:15] - node _T_23 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 145:32] - master_byteen <= _T_23 @[axi4_to_ahb.scala 145:17] - node _T_24 = bits(wrbuf_data, 63, 0) @[axi4_to_ahb.scala 146:29] - master_wdata <= _T_24 @[axi4_to_ahb.scala 146:16] - node _T_25 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 149:33] - node _T_26 = bits(slave_opc, 3, 3) @[axi4_to_ahb.scala 149:58] - node _T_27 = and(_T_25, _T_26) @[axi4_to_ahb.scala 149:47] - io.axi.b.valid <= _T_27 @[axi4_to_ahb.scala 149:18] - node _T_28 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 150:38] - node _T_29 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 150:65] - node _T_30 = mux(_T_29, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 150:55] - node _T_31 = mux(_T_28, UInt<2>("h02"), _T_30) @[axi4_to_ahb.scala 150:28] - io.axi.b.bits.resp <= _T_31 @[axi4_to_ahb.scala 150:22] - node _T_32 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 151:32] - io.axi.b.bits.id <= _T_32 @[axi4_to_ahb.scala 151:20] - node _T_33 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 153:33] - node _T_34 = bits(slave_opc, 3, 2) @[axi4_to_ahb.scala 153:59] - node _T_35 = eq(_T_34, UInt<1>("h00")) @[axi4_to_ahb.scala 153:66] - node _T_36 = and(_T_33, _T_35) @[axi4_to_ahb.scala 153:47] - io.axi.r.valid <= _T_36 @[axi4_to_ahb.scala 153:18] - node _T_37 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 154:38] - node _T_38 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 154:65] - node _T_39 = mux(_T_38, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 154:55] - node _T_40 = mux(_T_37, UInt<2>("h02"), _T_39) @[axi4_to_ahb.scala 154:28] - io.axi.r.bits.resp <= _T_40 @[axi4_to_ahb.scala 154:22] - node _T_41 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 155:32] - io.axi.r.bits.id <= _T_41 @[axi4_to_ahb.scala 155:20] - node _T_42 = bits(slave_rdata, 63, 0) @[axi4_to_ahb.scala 156:36] - io.axi.r.bits.data <= _T_42 @[axi4_to_ahb.scala 156:22] - node _T_43 = and(io.axi.b.ready, io.axi.r.ready) @[axi4_to_ahb.scala 157:33] - slave_ready <= _T_43 @[axi4_to_ahb.scala 157:15] - node _T_44 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 160:57] - node _T_45 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 160:94] - node _T_46 = or(_T_44, _T_45) @[axi4_to_ahb.scala 160:76] - node _T_47 = and(io.bus_clk_en, _T_46) @[axi4_to_ahb.scala 160:37] - bus_write_clk_en <= _T_47 @[axi4_to_ahb.scala 160:20] - inst rvclkhdr of rvclkhdr_849 @[lib.scala 343:22] - rvclkhdr.clock <= clock - rvclkhdr.reset <= reset - rvclkhdr.io.clk <= clock @[lib.scala 344:17] - rvclkhdr.io.en <= io.bus_clk_en @[lib.scala 345:16] - rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - bus_clk <= rvclkhdr.io.l1clk @[axi4_to_ahb.scala 162:11] - node _T_48 = bits(bus_write_clk_en, 0, 0) @[axi4_to_ahb.scala 163:59] - inst rvclkhdr_1 of rvclkhdr_850 @[lib.scala 343:22] - rvclkhdr_1.clock <= clock - rvclkhdr_1.reset <= reset - rvclkhdr_1.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_1.io.en <= _T_48 @[lib.scala 345:16] - rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - bus_write_clk <= rvclkhdr_1.io.l1clk @[axi4_to_ahb.scala 163:17] - node _T_49 = eq(UInt<3>("h00"), buf_state) @[Conditional.scala 37:30] - when _T_49 : @[Conditional.scala 40:58] - master_ready <= UInt<1>("h01") @[axi4_to_ahb.scala 167:20] - node _T_50 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 168:34] - node _T_51 = eq(_T_50, UInt<1>("h01")) @[axi4_to_ahb.scala 168:41] - buf_write_in <= _T_51 @[axi4_to_ahb.scala 168:20] - node _T_52 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 169:46] - node _T_53 = mux(_T_52, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 169:26] - buf_nxtstate <= _T_53 @[axi4_to_ahb.scala 169:20] - node _T_54 = and(master_valid, UInt<1>("h01")) @[axi4_to_ahb.scala 170:36] - buf_state_en <= _T_54 @[axi4_to_ahb.scala 170:20] - buf_wr_en <= buf_state_en @[axi4_to_ahb.scala 171:17] - node _T_55 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 172:54] - node _T_56 = and(buf_state_en, _T_55) @[axi4_to_ahb.scala 172:38] - buf_data_wr_en <= _T_56 @[axi4_to_ahb.scala 172:22] - buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 173:27] - node _T_57 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 175:50] - node _T_58 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 175:94] - node _T_59 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_60 = tail(_T_59, 1) @[axi4_to_ahb.scala 135:52] - node _T_61 = mux(UInt<1>("h00"), _T_60, UInt<3>("h00")) @[axi4_to_ahb.scala 135:24] - node _T_62 = bits(_T_58, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_63 = geq(UInt<1>("h00"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_64 = and(_T_62, _T_63) @[axi4_to_ahb.scala 136:48] - node _T_65 = bits(_T_58, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_66 = geq(UInt<1>("h01"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_67 = and(_T_65, _T_66) @[axi4_to_ahb.scala 136:48] - node _T_68 = bits(_T_58, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_69 = geq(UInt<2>("h02"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_70 = and(_T_68, _T_69) @[axi4_to_ahb.scala 136:48] - node _T_71 = bits(_T_58, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_72 = geq(UInt<2>("h03"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_73 = and(_T_71, _T_72) @[axi4_to_ahb.scala 136:48] - node _T_74 = bits(_T_58, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_75 = geq(UInt<3>("h04"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_76 = and(_T_74, _T_75) @[axi4_to_ahb.scala 136:48] - node _T_77 = bits(_T_58, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_78 = geq(UInt<3>("h05"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_79 = and(_T_77, _T_78) @[axi4_to_ahb.scala 136:48] - node _T_80 = bits(_T_58, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_81 = geq(UInt<3>("h06"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_82 = and(_T_80, _T_81) @[axi4_to_ahb.scala 136:48] - node _T_83 = bits(_T_58, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_84 = geq(UInt<3>("h07"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_85 = and(_T_83, _T_84) @[axi4_to_ahb.scala 136:48] - node _T_86 = mux(_T_85, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_87 = mux(_T_82, UInt<3>("h06"), _T_86) @[Mux.scala 98:16] - node _T_88 = mux(_T_79, UInt<3>("h05"), _T_87) @[Mux.scala 98:16] - node _T_89 = mux(_T_76, UInt<3>("h04"), _T_88) @[Mux.scala 98:16] - node _T_90 = mux(_T_73, UInt<2>("h03"), _T_89) @[Mux.scala 98:16] - node _T_91 = mux(_T_70, UInt<2>("h02"), _T_90) @[Mux.scala 98:16] - node _T_92 = mux(_T_67, UInt<1>("h01"), _T_91) @[Mux.scala 98:16] - node _T_93 = mux(_T_64, UInt<1>("h00"), _T_92) @[Mux.scala 98:16] - node _T_94 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 175:124] - node _T_95 = mux(_T_57, _T_93, _T_94) @[axi4_to_ahb.scala 175:30] - buf_cmd_byte_ptr <= _T_95 @[axi4_to_ahb.scala 175:24] - bypass_en <= buf_state_en @[axi4_to_ahb.scala 176:17] - node _T_96 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 177:51] - node _T_97 = and(bypass_en, _T_96) @[axi4_to_ahb.scala 177:35] - rd_bypass_idle <= _T_97 @[axi4_to_ahb.scala 177:22] - node _T_98 = bits(bypass_en, 0, 0) @[Bitwise.scala 72:15] - node _T_99 = mux(_T_98, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_100 = and(_T_99, UInt<2>("h02")) @[axi4_to_ahb.scala 178:49] - io.ahb.out.htrans <= _T_100 @[axi4_to_ahb.scala 178:25] - skip @[Conditional.scala 40:58] - else : @[Conditional.scala 39:67] - node _T_101 = eq(UInt<3>("h01"), buf_state) @[Conditional.scala 37:30] - when _T_101 : @[Conditional.scala 39:67] - node _T_102 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 182:54] - node _T_103 = eq(_T_102, UInt<1>("h00")) @[axi4_to_ahb.scala 182:61] - node _T_104 = and(master_valid, _T_103) @[axi4_to_ahb.scala 182:41] - node _T_105 = bits(_T_104, 0, 0) @[axi4_to_ahb.scala 182:82] - node _T_106 = mux(_T_105, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 182:26] - buf_nxtstate <= _T_106 @[axi4_to_ahb.scala 182:20] - node _T_107 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 183:51] - node _T_108 = neq(_T_107, UInt<1>("h00")) @[axi4_to_ahb.scala 183:58] - node _T_109 = and(ahb_hready_q, _T_108) @[axi4_to_ahb.scala 183:36] - node _T_110 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 183:72] - node _T_111 = and(_T_109, _T_110) @[axi4_to_ahb.scala 183:70] - buf_state_en <= _T_111 @[axi4_to_ahb.scala 183:20] - node _T_112 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 184:34] - node _T_113 = and(buf_state_en, _T_112) @[axi4_to_ahb.scala 184:32] - cmd_done <= _T_113 @[axi4_to_ahb.scala 184:16] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 185:20] - node _T_114 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 186:52] - node _T_115 = neq(_T_114, UInt<1>("h00")) @[axi4_to_ahb.scala 186:59] - node _T_116 = and(ahb_hready_q, _T_115) @[axi4_to_ahb.scala 186:37] - node _T_117 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 186:73] - node _T_118 = and(_T_116, _T_117) @[axi4_to_ahb.scala 186:71] - node _T_119 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 186:122] - node _T_120 = eq(_T_119, UInt<1>("h00")) @[axi4_to_ahb.scala 186:129] - node _T_121 = and(master_valid, _T_120) @[axi4_to_ahb.scala 186:109] - node _T_122 = bits(_T_121, 0, 0) @[axi4_to_ahb.scala 186:150] - node _T_123 = mux(_T_122, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 186:94] - node _T_124 = eq(_T_123, UInt<3>("h06")) @[axi4_to_ahb.scala 186:174] - node _T_125 = and(_T_118, _T_124) @[axi4_to_ahb.scala 186:88] - master_ready <= _T_125 @[axi4_to_ahb.scala 186:20] - buf_wr_en <= master_ready @[axi4_to_ahb.scala 187:17] - node _T_126 = and(master_ready, master_valid) @[axi4_to_ahb.scala 188:33] - bypass_en <= _T_126 @[axi4_to_ahb.scala 188:17] - node _T_127 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 189:47] - node _T_128 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 189:62] - node _T_129 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 189:78] - node _T_130 = mux(_T_127, _T_128, _T_129) @[axi4_to_ahb.scala 189:30] - buf_cmd_byte_ptr <= _T_130 @[axi4_to_ahb.scala 189:24] - node _T_131 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 190:48] - node _T_132 = or(_T_131, bypass_en) @[axi4_to_ahb.scala 190:62] - node _T_133 = bits(_T_132, 0, 0) @[Bitwise.scala 72:15] - node _T_134 = mux(_T_133, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_135 = and(UInt<2>("h02"), _T_134) @[axi4_to_ahb.scala 190:36] - io.ahb.out.htrans <= _T_135 @[axi4_to_ahb.scala 190:25] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_136 = eq(UInt<3>("h06"), buf_state) @[Conditional.scala 37:30] - when _T_136 : @[Conditional.scala 39:67] - node _T_137 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 194:39] - node _T_138 = and(ahb_hready_q, _T_137) @[axi4_to_ahb.scala 194:37] - node _T_139 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 194:82] - node _T_140 = eq(_T_139, UInt<1>("h01")) @[axi4_to_ahb.scala 194:89] - node _T_141 = and(master_valid, _T_140) @[axi4_to_ahb.scala 194:70] - node _T_142 = not(_T_141) @[axi4_to_ahb.scala 194:55] - node _T_143 = and(_T_138, _T_142) @[axi4_to_ahb.scala 194:53] - master_ready <= _T_143 @[axi4_to_ahb.scala 194:20] - node _T_144 = and(master_valid, master_ready) @[axi4_to_ahb.scala 195:34] - node _T_145 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 195:62] - node _T_146 = eq(_T_145, UInt<1>("h00")) @[axi4_to_ahb.scala 195:69] - node _T_147 = and(_T_144, _T_146) @[axi4_to_ahb.scala 195:49] - buf_wr_en <= _T_147 @[axi4_to_ahb.scala 195:17] - node _T_148 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 196:45] - node _T_149 = and(master_valid, master_ready) @[axi4_to_ahb.scala 196:82] - node _T_150 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 196:110] - node _T_151 = eq(_T_150, UInt<1>("h00")) @[axi4_to_ahb.scala 196:117] - node _T_152 = and(_T_149, _T_151) @[axi4_to_ahb.scala 196:97] - node _T_153 = bits(_T_152, 0, 0) @[axi4_to_ahb.scala 196:138] - node _T_154 = mux(_T_153, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 196:67] - node _T_155 = mux(_T_148, UInt<3>("h07"), _T_154) @[axi4_to_ahb.scala 196:26] - buf_nxtstate <= _T_155 @[axi4_to_ahb.scala 196:20] - node _T_156 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 197:37] - buf_state_en <= _T_156 @[axi4_to_ahb.scala 197:20] - buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 198:22] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 199:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 200:23] - node _T_157 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 201:41] - node _T_158 = and(buf_state_en, _T_157) @[axi4_to_ahb.scala 201:39] - slave_valid_pre <= _T_158 @[axi4_to_ahb.scala 201:23] - node _T_159 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 202:34] - node _T_160 = and(buf_state_en, _T_159) @[axi4_to_ahb.scala 202:32] - cmd_done <= _T_160 @[axi4_to_ahb.scala 202:16] - node _T_161 = and(master_ready, master_valid) @[axi4_to_ahb.scala 203:33] - node _T_162 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 203:64] - node _T_163 = and(_T_161, _T_162) @[axi4_to_ahb.scala 203:48] - node _T_164 = and(_T_163, buf_state_en) @[axi4_to_ahb.scala 203:79] - bypass_en <= _T_164 @[axi4_to_ahb.scala 203:17] - node _T_165 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 204:47] - node _T_166 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 204:62] - node _T_167 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 204:78] - node _T_168 = mux(_T_165, _T_166, _T_167) @[axi4_to_ahb.scala 204:30] - buf_cmd_byte_ptr <= _T_168 @[axi4_to_ahb.scala 204:24] - node _T_169 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 205:63] - node _T_170 = and(_T_169, buf_state_en) @[axi4_to_ahb.scala 205:78] - node _T_171 = eq(_T_170, UInt<1>("h00")) @[axi4_to_ahb.scala 205:47] - node _T_172 = bits(_T_171, 0, 0) @[Bitwise.scala 72:15] - node _T_173 = mux(_T_172, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_174 = and(UInt<2>("h02"), _T_173) @[axi4_to_ahb.scala 205:36] - io.ahb.out.htrans <= _T_174 @[axi4_to_ahb.scala 205:25] - slvbuf_wr_en <= buf_wr_en @[axi4_to_ahb.scala 206:20] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_175 = eq(UInt<3>("h07"), buf_state) @[Conditional.scala 37:30] - when _T_175 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h03") @[axi4_to_ahb.scala 210:20] - node _T_176 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 211:51] - node _T_177 = neq(_T_176, UInt<1>("h00")) @[axi4_to_ahb.scala 211:58] - node _T_178 = and(ahb_hready_q, _T_177) @[axi4_to_ahb.scala 211:36] - node _T_179 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 211:72] - node _T_180 = and(_T_178, _T_179) @[axi4_to_ahb.scala 211:70] - buf_state_en <= _T_180 @[axi4_to_ahb.scala 211:20] - slave_valid_pre <= buf_state_en @[axi4_to_ahb.scala 212:23] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 213:20] - node _T_181 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 214:35] - buf_cmd_byte_ptr <= _T_181 @[axi4_to_ahb.scala 214:24] - node _T_182 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 215:51] - node _T_183 = bits(_T_182, 0, 0) @[Bitwise.scala 72:15] - node _T_184 = mux(_T_183, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_185 = and(UInt<2>("h02"), _T_184) @[axi4_to_ahb.scala 215:41] - io.ahb.out.htrans <= _T_185 @[axi4_to_ahb.scala 215:25] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_186 = eq(UInt<3>("h03"), buf_state) @[Conditional.scala 37:30] - when _T_186 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h05") @[axi4_to_ahb.scala 219:20] - node _T_187 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 220:37] - buf_state_en <= _T_187 @[axi4_to_ahb.scala 220:20] - buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 221:22] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 222:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 223:23] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 224:20] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_188 = eq(UInt<3>("h02"), buf_state) @[Conditional.scala 37:30] - when _T_188 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h04") @[axi4_to_ahb.scala 228:20] - node _T_189 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 229:33] - node _T_190 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 229:63] - node _T_191 = neq(_T_190, UInt<1>("h00")) @[axi4_to_ahb.scala 229:70] - node _T_192 = and(_T_189, _T_191) @[axi4_to_ahb.scala 229:48] - trxn_done <= _T_192 @[axi4_to_ahb.scala 229:17] - buf_state_en <= trxn_done @[axi4_to_ahb.scala 230:20] - buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 231:27] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 232:20] - node _T_193 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 233:47] - node _T_194 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 233:85] - node _T_195 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 233:103] - node _T_196 = add(_T_194, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_197 = tail(_T_196, 1) @[axi4_to_ahb.scala 135:52] - node _T_198 = mux(UInt<1>("h01"), _T_197, _T_194) @[axi4_to_ahb.scala 135:24] - node _T_199 = bits(_T_195, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_200 = geq(UInt<1>("h00"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_201 = and(_T_199, _T_200) @[axi4_to_ahb.scala 136:48] - node _T_202 = bits(_T_195, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_203 = geq(UInt<1>("h01"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_204 = and(_T_202, _T_203) @[axi4_to_ahb.scala 136:48] - node _T_205 = bits(_T_195, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_206 = geq(UInt<2>("h02"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_207 = and(_T_205, _T_206) @[axi4_to_ahb.scala 136:48] - node _T_208 = bits(_T_195, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_209 = geq(UInt<2>("h03"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_210 = and(_T_208, _T_209) @[axi4_to_ahb.scala 136:48] - node _T_211 = bits(_T_195, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_212 = geq(UInt<3>("h04"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_213 = and(_T_211, _T_212) @[axi4_to_ahb.scala 136:48] - node _T_214 = bits(_T_195, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_215 = geq(UInt<3>("h05"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_216 = and(_T_214, _T_215) @[axi4_to_ahb.scala 136:48] - node _T_217 = bits(_T_195, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_218 = geq(UInt<3>("h06"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_219 = and(_T_217, _T_218) @[axi4_to_ahb.scala 136:48] - node _T_220 = bits(_T_195, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_221 = geq(UInt<3>("h07"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_222 = and(_T_220, _T_221) @[axi4_to_ahb.scala 136:48] - node _T_223 = mux(_T_222, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_224 = mux(_T_219, UInt<3>("h06"), _T_223) @[Mux.scala 98:16] - node _T_225 = mux(_T_216, UInt<3>("h05"), _T_224) @[Mux.scala 98:16] - node _T_226 = mux(_T_213, UInt<3>("h04"), _T_225) @[Mux.scala 98:16] - node _T_227 = mux(_T_210, UInt<2>("h03"), _T_226) @[Mux.scala 98:16] - node _T_228 = mux(_T_207, UInt<2>("h02"), _T_227) @[Mux.scala 98:16] - node _T_229 = mux(_T_204, UInt<1>("h01"), _T_228) @[Mux.scala 98:16] - node _T_230 = mux(_T_201, UInt<1>("h00"), _T_229) @[Mux.scala 98:16] - node _T_231 = mux(_T_193, _T_230, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 233:30] - buf_cmd_byte_ptr <= _T_231 @[axi4_to_ahb.scala 233:24] - node _T_232 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 234:65] - node _T_233 = or(buf_aligned, _T_232) @[axi4_to_ahb.scala 234:44] - node _T_234 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 234:127] - node _T_235 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 234:145] - node _T_236 = add(_T_234, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_237 = tail(_T_236, 1) @[axi4_to_ahb.scala 135:52] - node _T_238 = mux(UInt<1>("h01"), _T_237, _T_234) @[axi4_to_ahb.scala 135:24] - node _T_239 = bits(_T_235, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_240 = geq(UInt<1>("h00"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_241 = and(_T_239, _T_240) @[axi4_to_ahb.scala 136:48] - node _T_242 = bits(_T_235, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_243 = geq(UInt<1>("h01"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_244 = and(_T_242, _T_243) @[axi4_to_ahb.scala 136:48] - node _T_245 = bits(_T_235, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_246 = geq(UInt<2>("h02"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_247 = and(_T_245, _T_246) @[axi4_to_ahb.scala 136:48] - node _T_248 = bits(_T_235, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_249 = geq(UInt<2>("h03"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_250 = and(_T_248, _T_249) @[axi4_to_ahb.scala 136:48] - node _T_251 = bits(_T_235, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_252 = geq(UInt<3>("h04"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_253 = and(_T_251, _T_252) @[axi4_to_ahb.scala 136:48] - node _T_254 = bits(_T_235, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_255 = geq(UInt<3>("h05"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_256 = and(_T_254, _T_255) @[axi4_to_ahb.scala 136:48] - node _T_257 = bits(_T_235, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_258 = geq(UInt<3>("h06"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_259 = and(_T_257, _T_258) @[axi4_to_ahb.scala 136:48] - node _T_260 = bits(_T_235, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_261 = geq(UInt<3>("h07"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_262 = and(_T_260, _T_261) @[axi4_to_ahb.scala 136:48] - node _T_263 = mux(_T_262, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_264 = mux(_T_259, UInt<3>("h06"), _T_263) @[Mux.scala 98:16] - node _T_265 = mux(_T_256, UInt<3>("h05"), _T_264) @[Mux.scala 98:16] - node _T_266 = mux(_T_253, UInt<3>("h04"), _T_265) @[Mux.scala 98:16] - node _T_267 = mux(_T_250, UInt<2>("h03"), _T_266) @[Mux.scala 98:16] - node _T_268 = mux(_T_247, UInt<2>("h02"), _T_267) @[Mux.scala 98:16] - node _T_269 = mux(_T_244, UInt<1>("h01"), _T_268) @[Mux.scala 98:16] - node _T_270 = mux(_T_241, UInt<1>("h00"), _T_269) @[Mux.scala 98:16] - node _T_271 = dshr(buf_byteen, _T_270) @[axi4_to_ahb.scala 234:92] - node _T_272 = bits(_T_271, 0, 0) @[axi4_to_ahb.scala 234:92] - node _T_273 = eq(_T_272, UInt<1>("h00")) @[axi4_to_ahb.scala 234:163] - node _T_274 = or(_T_233, _T_273) @[axi4_to_ahb.scala 234:79] - node _T_275 = and(trxn_done, _T_274) @[axi4_to_ahb.scala 234:29] - cmd_done <= _T_275 @[axi4_to_ahb.scala 234:16] - node _T_276 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 235:47] - node _T_277 = eq(_T_276, UInt<1>("h00")) @[axi4_to_ahb.scala 235:36] - node _T_278 = bits(_T_277, 0, 0) @[Bitwise.scala 72:15] - node _T_279 = mux(_T_278, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_280 = and(_T_279, UInt<2>("h02")) @[axi4_to_ahb.scala 235:61] - io.ahb.out.htrans <= _T_280 @[axi4_to_ahb.scala 235:25] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_281 = eq(UInt<3>("h04"), buf_state) @[Conditional.scala 37:30] - when _T_281 : @[Conditional.scala 39:67] - node _T_282 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 239:34] - node _T_283 = or(_T_282, ahb_hresp_q) @[axi4_to_ahb.scala 239:50] - buf_state_en <= _T_283 @[axi4_to_ahb.scala 239:20] - node _T_284 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 240:38] - node _T_285 = and(buf_state_en, _T_284) @[axi4_to_ahb.scala 240:36] - node _T_286 = and(_T_285, slave_ready) @[axi4_to_ahb.scala 240:51] - master_ready <= _T_286 @[axi4_to_ahb.scala 240:20] - node _T_287 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 241:42] - node _T_288 = or(ahb_hresp_q, _T_287) @[axi4_to_ahb.scala 241:40] - node _T_289 = and(master_valid, master_valid) @[axi4_to_ahb.scala 241:80] - node _T_290 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 241:111] - node _T_291 = eq(_T_290, UInt<1>("h01")) @[axi4_to_ahb.scala 241:117] - node _T_292 = bits(_T_291, 0, 0) @[axi4_to_ahb.scala 241:132] - node _T_293 = mux(_T_292, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 241:99] - node _T_294 = mux(_T_289, _T_293, UInt<3>("h00")) @[axi4_to_ahb.scala 241:65] - node _T_295 = mux(_T_288, UInt<3>("h05"), _T_294) @[axi4_to_ahb.scala 241:26] - buf_nxtstate <= _T_295 @[axi4_to_ahb.scala 241:20] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 242:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 243:23] - node _T_296 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 244:33] - node _T_297 = eq(_T_296, UInt<1>("h01")) @[axi4_to_ahb.scala 244:39] - buf_write_in <= _T_297 @[axi4_to_ahb.scala 244:20] - node _T_298 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 245:50] - node _T_299 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 245:78] - node _T_300 = or(_T_298, _T_299) @[axi4_to_ahb.scala 245:62] - node _T_301 = and(buf_state_en, _T_300) @[axi4_to_ahb.scala 245:33] - buf_wr_en <= _T_301 @[axi4_to_ahb.scala 245:17] - buf_data_wr_en <= buf_wr_en @[axi4_to_ahb.scala 246:22] - node _T_302 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 247:65] - node _T_303 = neq(_T_302, UInt<1>("h00")) @[axi4_to_ahb.scala 247:71] - node _T_304 = and(ahb_hready_q, _T_303) @[axi4_to_ahb.scala 247:50] - node _T_305 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 248:29] - node _T_306 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 248:85] - node _T_307 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 248:101] - node _T_308 = add(_T_306, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_309 = tail(_T_308, 1) @[axi4_to_ahb.scala 135:52] - node _T_310 = mux(UInt<1>("h01"), _T_309, _T_306) @[axi4_to_ahb.scala 135:24] - node _T_311 = bits(_T_307, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_312 = geq(UInt<1>("h00"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_313 = and(_T_311, _T_312) @[axi4_to_ahb.scala 136:48] - node _T_314 = bits(_T_307, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_315 = geq(UInt<1>("h01"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_316 = and(_T_314, _T_315) @[axi4_to_ahb.scala 136:48] - node _T_317 = bits(_T_307, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_318 = geq(UInt<2>("h02"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_319 = and(_T_317, _T_318) @[axi4_to_ahb.scala 136:48] - node _T_320 = bits(_T_307, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_321 = geq(UInt<2>("h03"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_322 = and(_T_320, _T_321) @[axi4_to_ahb.scala 136:48] - node _T_323 = bits(_T_307, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_324 = geq(UInt<3>("h04"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_325 = and(_T_323, _T_324) @[axi4_to_ahb.scala 136:48] - node _T_326 = bits(_T_307, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_327 = geq(UInt<3>("h05"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_328 = and(_T_326, _T_327) @[axi4_to_ahb.scala 136:48] - node _T_329 = bits(_T_307, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_330 = geq(UInt<3>("h06"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_331 = and(_T_329, _T_330) @[axi4_to_ahb.scala 136:48] - node _T_332 = bits(_T_307, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_333 = geq(UInt<3>("h07"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_334 = and(_T_332, _T_333) @[axi4_to_ahb.scala 136:48] - node _T_335 = mux(_T_334, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_336 = mux(_T_331, UInt<3>("h06"), _T_335) @[Mux.scala 98:16] - node _T_337 = mux(_T_328, UInt<3>("h05"), _T_336) @[Mux.scala 98:16] - node _T_338 = mux(_T_325, UInt<3>("h04"), _T_337) @[Mux.scala 98:16] - node _T_339 = mux(_T_322, UInt<2>("h03"), _T_338) @[Mux.scala 98:16] - node _T_340 = mux(_T_319, UInt<2>("h02"), _T_339) @[Mux.scala 98:16] - node _T_341 = mux(_T_316, UInt<1>("h01"), _T_340) @[Mux.scala 98:16] - node _T_342 = mux(_T_313, UInt<1>("h00"), _T_341) @[Mux.scala 98:16] - node _T_343 = dshr(buf_byteen, _T_342) @[axi4_to_ahb.scala 248:51] - node _T_344 = bits(_T_343, 0, 0) @[axi4_to_ahb.scala 248:51] - node _T_345 = eq(_T_344, UInt<1>("h00")) @[axi4_to_ahb.scala 248:116] - node _T_346 = or(_T_305, _T_345) @[axi4_to_ahb.scala 248:38] - node _T_347 = and(_T_304, _T_346) @[axi4_to_ahb.scala 247:80] - node _T_348 = or(ahb_hresp_q, _T_347) @[axi4_to_ahb.scala 247:34] - cmd_done <= _T_348 @[axi4_to_ahb.scala 247:16] - node _T_349 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 249:33] - node _T_350 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 249:64] - node _T_351 = and(_T_349, _T_350) @[axi4_to_ahb.scala 249:48] - bypass_en <= _T_351 @[axi4_to_ahb.scala 249:17] - node _T_352 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 250:48] - node _T_353 = eq(_T_352, UInt<1>("h00")) @[axi4_to_ahb.scala 250:37] - node _T_354 = or(_T_353, bypass_en) @[axi4_to_ahb.scala 250:61] - node _T_355 = bits(_T_354, 0, 0) @[Bitwise.scala 72:15] - node _T_356 = mux(_T_355, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_357 = and(_T_356, UInt<2>("h02")) @[axi4_to_ahb.scala 250:75] - io.ahb.out.htrans <= _T_357 @[axi4_to_ahb.scala 250:25] - node _T_358 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 251:55] - node _T_359 = and(buf_state_en, _T_358) @[axi4_to_ahb.scala 251:39] - slave_valid_pre <= _T_359 @[axi4_to_ahb.scala 251:23] - node _T_360 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 252:33] - node _T_361 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 252:63] - node _T_362 = neq(_T_361, UInt<1>("h00")) @[axi4_to_ahb.scala 252:69] - node _T_363 = and(_T_360, _T_362) @[axi4_to_ahb.scala 252:48] - trxn_done <= _T_363 @[axi4_to_ahb.scala 252:17] - node _T_364 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 253:40] - buf_cmd_byte_ptr_en <= _T_364 @[axi4_to_ahb.scala 253:27] - node _T_365 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 254:79] - node _T_366 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_367 = tail(_T_366, 1) @[axi4_to_ahb.scala 135:52] - node _T_368 = mux(UInt<1>("h00"), _T_367, UInt<3>("h00")) @[axi4_to_ahb.scala 135:24] - node _T_369 = bits(_T_365, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_370 = geq(UInt<1>("h00"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_371 = and(_T_369, _T_370) @[axi4_to_ahb.scala 136:48] - node _T_372 = bits(_T_365, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_373 = geq(UInt<1>("h01"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_374 = and(_T_372, _T_373) @[axi4_to_ahb.scala 136:48] - node _T_375 = bits(_T_365, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_376 = geq(UInt<2>("h02"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_377 = and(_T_375, _T_376) @[axi4_to_ahb.scala 136:48] - node _T_378 = bits(_T_365, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_379 = geq(UInt<2>("h03"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_380 = and(_T_378, _T_379) @[axi4_to_ahb.scala 136:48] - node _T_381 = bits(_T_365, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_382 = geq(UInt<3>("h04"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_383 = and(_T_381, _T_382) @[axi4_to_ahb.scala 136:48] - node _T_384 = bits(_T_365, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_385 = geq(UInt<3>("h05"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_386 = and(_T_384, _T_385) @[axi4_to_ahb.scala 136:48] - node _T_387 = bits(_T_365, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_388 = geq(UInt<3>("h06"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_389 = and(_T_387, _T_388) @[axi4_to_ahb.scala 136:48] - node _T_390 = bits(_T_365, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_391 = geq(UInt<3>("h07"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_392 = and(_T_390, _T_391) @[axi4_to_ahb.scala 136:48] - node _T_393 = mux(_T_392, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_394 = mux(_T_389, UInt<3>("h06"), _T_393) @[Mux.scala 98:16] - node _T_395 = mux(_T_386, UInt<3>("h05"), _T_394) @[Mux.scala 98:16] - node _T_396 = mux(_T_383, UInt<3>("h04"), _T_395) @[Mux.scala 98:16] - node _T_397 = mux(_T_380, UInt<2>("h03"), _T_396) @[Mux.scala 98:16] - node _T_398 = mux(_T_377, UInt<2>("h02"), _T_397) @[Mux.scala 98:16] - node _T_399 = mux(_T_374, UInt<1>("h01"), _T_398) @[Mux.scala 98:16] - node _T_400 = mux(_T_371, UInt<1>("h00"), _T_399) @[Mux.scala 98:16] - node _T_401 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 254:141] - node _T_402 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 254:157] - node _T_403 = add(_T_401, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_404 = tail(_T_403, 1) @[axi4_to_ahb.scala 135:52] - node _T_405 = mux(UInt<1>("h01"), _T_404, _T_401) @[axi4_to_ahb.scala 135:24] - node _T_406 = bits(_T_402, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_407 = geq(UInt<1>("h00"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_408 = and(_T_406, _T_407) @[axi4_to_ahb.scala 136:48] - node _T_409 = bits(_T_402, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_410 = geq(UInt<1>("h01"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_411 = and(_T_409, _T_410) @[axi4_to_ahb.scala 136:48] - node _T_412 = bits(_T_402, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_413 = geq(UInt<2>("h02"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_414 = and(_T_412, _T_413) @[axi4_to_ahb.scala 136:48] - node _T_415 = bits(_T_402, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_416 = geq(UInt<2>("h03"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_417 = and(_T_415, _T_416) @[axi4_to_ahb.scala 136:48] - node _T_418 = bits(_T_402, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_419 = geq(UInt<3>("h04"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_420 = and(_T_418, _T_419) @[axi4_to_ahb.scala 136:48] - node _T_421 = bits(_T_402, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_422 = geq(UInt<3>("h05"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_423 = and(_T_421, _T_422) @[axi4_to_ahb.scala 136:48] - node _T_424 = bits(_T_402, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_425 = geq(UInt<3>("h06"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_426 = and(_T_424, _T_425) @[axi4_to_ahb.scala 136:48] - node _T_427 = bits(_T_402, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_428 = geq(UInt<3>("h07"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_429 = and(_T_427, _T_428) @[axi4_to_ahb.scala 136:48] - node _T_430 = mux(_T_429, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_431 = mux(_T_426, UInt<3>("h06"), _T_430) @[Mux.scala 98:16] - node _T_432 = mux(_T_423, UInt<3>("h05"), _T_431) @[Mux.scala 98:16] - node _T_433 = mux(_T_420, UInt<3>("h04"), _T_432) @[Mux.scala 98:16] - node _T_434 = mux(_T_417, UInt<2>("h03"), _T_433) @[Mux.scala 98:16] - node _T_435 = mux(_T_414, UInt<2>("h02"), _T_434) @[Mux.scala 98:16] - node _T_436 = mux(_T_411, UInt<1>("h01"), _T_435) @[Mux.scala 98:16] - node _T_437 = mux(_T_408, UInt<1>("h00"), _T_436) @[Mux.scala 98:16] - node _T_438 = mux(trxn_done, _T_437, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 254:97] - node _T_439 = mux(bypass_en, _T_400, _T_438) @[axi4_to_ahb.scala 254:30] - buf_cmd_byte_ptr <= _T_439 @[axi4_to_ahb.scala 254:24] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_440 = eq(UInt<3>("h05"), buf_state) @[Conditional.scala 37:30] - when _T_440 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 257:20] - buf_state_en <= slave_ready @[axi4_to_ahb.scala 258:20] - slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 259:23] - slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 260:23] - skip @[Conditional.scala 39:67] - cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 264:16] - node _T_441 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 265:33] - node _T_442 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 265:73] - node _T_443 = eq(_T_442, UInt<1>("h01")) @[axi4_to_ahb.scala 265:80] - node _T_444 = and(buf_aligned_in, _T_443) @[axi4_to_ahb.scala 265:60] - node _T_445 = bits(_T_444, 0, 0) @[axi4_to_ahb.scala 265:100] - node _T_446 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 265:132] - node _T_447 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 127:50] - node _T_448 = eq(_T_447, UInt<8>("h0ff")) @[axi4_to_ahb.scala 127:57] - node _T_449 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 127:81] - node _T_450 = eq(_T_449, UInt<8>("h0f")) @[axi4_to_ahb.scala 127:88] - node _T_451 = or(_T_448, _T_450) @[axi4_to_ahb.scala 127:70] - node _T_452 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 127:117] - node _T_453 = eq(_T_452, UInt<8>("h03")) @[axi4_to_ahb.scala 127:124] - node _T_454 = or(_T_451, _T_453) @[axi4_to_ahb.scala 127:106] - node _T_455 = bits(_T_454, 0, 0) @[Bitwise.scala 72:15] - node _T_456 = mux(_T_455, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_457 = and(UInt<3>("h00"), _T_456) @[axi4_to_ahb.scala 127:29] - node _T_458 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 128:35] - node _T_459 = eq(_T_458, UInt<8>("h0c")) @[axi4_to_ahb.scala 128:42] - node _T_460 = bits(_T_459, 0, 0) @[Bitwise.scala 72:15] - node _T_461 = mux(_T_460, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_462 = and(UInt<2>("h02"), _T_461) @[axi4_to_ahb.scala 128:15] - node _T_463 = or(_T_457, _T_462) @[axi4_to_ahb.scala 127:146] - node _T_464 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 129:36] - node _T_465 = eq(_T_464, UInt<8>("h0f0")) @[axi4_to_ahb.scala 129:43] - node _T_466 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 129:67] - node _T_467 = eq(_T_466, UInt<8>("h03")) @[axi4_to_ahb.scala 129:74] - node _T_468 = or(_T_465, _T_467) @[axi4_to_ahb.scala 129:56] - node _T_469 = bits(_T_468, 0, 0) @[Bitwise.scala 72:15] - node _T_470 = mux(_T_469, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_471 = and(UInt<3>("h04"), _T_470) @[axi4_to_ahb.scala 129:15] - node _T_472 = or(_T_463, _T_471) @[axi4_to_ahb.scala 128:63] - node _T_473 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 130:35] - node _T_474 = eq(_T_473, UInt<8>("h0c0")) @[axi4_to_ahb.scala 130:42] - node _T_475 = bits(_T_474, 0, 0) @[Bitwise.scala 72:15] - node _T_476 = mux(_T_475, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_477 = and(UInt<3>("h06"), _T_476) @[axi4_to_ahb.scala 130:15] - node _T_478 = or(_T_472, _T_477) @[axi4_to_ahb.scala 129:96] - node _T_479 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 131:33] - node _T_480 = eq(_T_479, UInt<8>("h0c0")) @[axi4_to_ahb.scala 131:40] - node _T_481 = bits(_T_480, 0, 0) @[Bitwise.scala 72:15] - node _T_482 = mux(_T_481, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_483 = and(UInt<3>("h06"), _T_482) @[axi4_to_ahb.scala 131:13] - node _T_484 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 265:152] - node _T_485 = mux(_T_445, _T_478, _T_484) @[axi4_to_ahb.scala 265:43] - node _T_486 = cat(_T_441, _T_485) @[Cat.scala 29:58] - buf_addr_in <= _T_486 @[axi4_to_ahb.scala 265:15] - node _T_487 = bits(master_tag, 0, 0) @[axi4_to_ahb.scala 266:27] - buf_tag_in <= _T_487 @[axi4_to_ahb.scala 266:14] - node _T_488 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 267:32] - buf_byteen_in <= _T_488 @[axi4_to_ahb.scala 267:17] - node _T_489 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 268:33] - node _T_490 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 268:59] - node _T_491 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 268:80] - node _T_492 = mux(_T_489, _T_490, _T_491) @[axi4_to_ahb.scala 268:21] - buf_data_in <= _T_492 @[axi4_to_ahb.scala 268:15] - node _T_493 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 269:52] - node _T_494 = eq(_T_493, UInt<2>("h03")) @[axi4_to_ahb.scala 269:58] - node _T_495 = and(buf_aligned_in, _T_494) @[axi4_to_ahb.scala 269:38] - node _T_496 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 269:84] - node _T_497 = eq(_T_496, UInt<1>("h01")) @[axi4_to_ahb.scala 269:91] - node _T_498 = and(_T_495, _T_497) @[axi4_to_ahb.scala 269:71] - node _T_499 = bits(_T_498, 0, 0) @[axi4_to_ahb.scala 269:111] - node _T_500 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 269:142] - node _T_501 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 121:42] - node _T_502 = eq(_T_501, UInt<8>("h0ff")) @[axi4_to_ahb.scala 121:49] - node _T_503 = bits(_T_502, 0, 0) @[Bitwise.scala 72:15] - node _T_504 = mux(_T_503, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_505 = and(UInt<2>("h03"), _T_504) @[axi4_to_ahb.scala 121:25] - node _T_506 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 122:35] - node _T_507 = eq(_T_506, UInt<8>("h0f0")) @[axi4_to_ahb.scala 122:42] - node _T_508 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 122:64] - node _T_509 = eq(_T_508, UInt<8>("h0f")) @[axi4_to_ahb.scala 122:71] - node _T_510 = or(_T_507, _T_509) @[axi4_to_ahb.scala 122:55] - node _T_511 = bits(_T_510, 0, 0) @[Bitwise.scala 72:15] - node _T_512 = mux(_T_511, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_513 = and(UInt<2>("h02"), _T_512) @[axi4_to_ahb.scala 122:16] - node _T_514 = or(_T_505, _T_513) @[axi4_to_ahb.scala 121:64] - node _T_515 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:40] - node _T_516 = eq(_T_515, UInt<8>("h0c0")) @[axi4_to_ahb.scala 123:47] - node _T_517 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:69] - node _T_518 = eq(_T_517, UInt<6>("h030")) @[axi4_to_ahb.scala 123:76] - node _T_519 = or(_T_516, _T_518) @[axi4_to_ahb.scala 123:60] - node _T_520 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:98] - node _T_521 = eq(_T_520, UInt<8>("h0c")) @[axi4_to_ahb.scala 123:105] - node _T_522 = or(_T_519, _T_521) @[axi4_to_ahb.scala 123:89] - node _T_523 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:132] - node _T_524 = eq(_T_523, UInt<8>("h03")) @[axi4_to_ahb.scala 123:139] - node _T_525 = or(_T_522, _T_524) @[axi4_to_ahb.scala 123:123] - node _T_526 = bits(_T_525, 0, 0) @[Bitwise.scala 72:15] - node _T_527 = mux(_T_526, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_528 = and(UInt<2>("h01"), _T_527) @[axi4_to_ahb.scala 123:21] - node _T_529 = or(_T_514, _T_528) @[axi4_to_ahb.scala 122:93] - node _T_530 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 269:161] - node _T_531 = mux(_T_499, _T_529, _T_530) @[axi4_to_ahb.scala 269:21] - buf_size_in <= _T_531 @[axi4_to_ahb.scala 269:15] - node _T_532 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 270:32] - node _T_533 = eq(_T_532, UInt<1>("h00")) @[axi4_to_ahb.scala 270:39] - node _T_534 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 271:17] - node _T_535 = eq(_T_534, UInt<1>("h00")) @[axi4_to_ahb.scala 271:24] - node _T_536 = or(_T_533, _T_535) @[axi4_to_ahb.scala 270:48] - node _T_537 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 271:47] - node _T_538 = eq(_T_537, UInt<2>("h01")) @[axi4_to_ahb.scala 271:54] - node _T_539 = or(_T_536, _T_538) @[axi4_to_ahb.scala 271:33] - node _T_540 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 271:86] - node _T_541 = eq(_T_540, UInt<2>("h02")) @[axi4_to_ahb.scala 271:93] - node _T_542 = or(_T_539, _T_541) @[axi4_to_ahb.scala 271:72] - node _T_543 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 272:18] - node _T_544 = eq(_T_543, UInt<2>("h03")) @[axi4_to_ahb.scala 272:25] - node _T_545 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:55] - node _T_546 = eq(_T_545, UInt<2>("h03")) @[axi4_to_ahb.scala 272:62] - node _T_547 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:90] - node _T_548 = eq(_T_547, UInt<4>("h0c")) @[axi4_to_ahb.scala 272:97] - node _T_549 = or(_T_546, _T_548) @[axi4_to_ahb.scala 272:74] - node _T_550 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:125] - node _T_551 = eq(_T_550, UInt<6>("h030")) @[axi4_to_ahb.scala 272:132] - node _T_552 = or(_T_549, _T_551) @[axi4_to_ahb.scala 272:109] - node _T_553 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:161] - node _T_554 = eq(_T_553, UInt<8>("h0c0")) @[axi4_to_ahb.scala 272:168] - node _T_555 = or(_T_552, _T_554) @[axi4_to_ahb.scala 272:145] - node _T_556 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 273:21] - node _T_557 = eq(_T_556, UInt<4>("h0f")) @[axi4_to_ahb.scala 273:28] - node _T_558 = or(_T_555, _T_557) @[axi4_to_ahb.scala 272:181] - node _T_559 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 273:56] - node _T_560 = eq(_T_559, UInt<8>("h0f0")) @[axi4_to_ahb.scala 273:63] - node _T_561 = or(_T_558, _T_560) @[axi4_to_ahb.scala 273:40] - node _T_562 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 273:92] - node _T_563 = eq(_T_562, UInt<8>("h0ff")) @[axi4_to_ahb.scala 273:99] - node _T_564 = or(_T_561, _T_563) @[axi4_to_ahb.scala 273:76] - node _T_565 = and(_T_544, _T_564) @[axi4_to_ahb.scala 272:38] - node _T_566 = or(_T_542, _T_565) @[axi4_to_ahb.scala 271:106] - buf_aligned_in <= _T_566 @[axi4_to_ahb.scala 270:18] - node _T_567 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 275:43] - node _T_568 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 275:62] - node _T_569 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 275:87] - node _T_570 = cat(_T_568, _T_569) @[Cat.scala 29:58] - node _T_571 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 275:108] - node _T_572 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 275:133] - node _T_573 = cat(_T_571, _T_572) @[Cat.scala 29:58] - node _T_574 = mux(_T_567, _T_570, _T_573) @[axi4_to_ahb.scala 275:26] - io.ahb.out.haddr <= _T_574 @[axi4_to_ahb.scala 275:20] - node _T_575 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 276:43] - node _T_576 = bits(buf_aligned_in, 0, 0) @[Bitwise.scala 72:15] - node _T_577 = mux(_T_576, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_578 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 276:94] - node _T_579 = and(_T_577, _T_578) @[axi4_to_ahb.scala 276:81] - node _T_580 = cat(UInt<1>("h00"), _T_579) @[Cat.scala 29:58] - node _T_581 = bits(buf_aligned, 0, 0) @[Bitwise.scala 72:15] - node _T_582 = mux(_T_581, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_583 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 276:148] - node _T_584 = and(_T_582, _T_583) @[axi4_to_ahb.scala 276:138] - node _T_585 = cat(UInt<1>("h00"), _T_584) @[Cat.scala 29:58] - node _T_586 = mux(_T_575, _T_580, _T_585) @[axi4_to_ahb.scala 276:26] - io.ahb.out.hsize <= _T_586 @[axi4_to_ahb.scala 276:20] - io.ahb.out.hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 278:21] - io.ahb.out.hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 279:24] - node _T_587 = bits(io.axi.ar.bits.prot, 2, 2) @[axi4_to_ahb.scala 280:57] - node _T_588 = eq(_T_587, UInt<1>("h00")) @[axi4_to_ahb.scala 280:37] - node _T_589 = cat(UInt<1>("h01"), _T_588) @[Cat.scala 29:58] - io.ahb.out.hprot <= _T_589 @[axi4_to_ahb.scala 280:20] - node _T_590 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 281:44] - node _T_591 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 281:59] - node _T_592 = eq(_T_591, UInt<1>("h01")) @[axi4_to_ahb.scala 281:66] - node _T_593 = mux(_T_590, _T_592, buf_write) @[axi4_to_ahb.scala 281:27] - io.ahb.out.hwrite <= _T_593 @[axi4_to_ahb.scala 281:21] - node _T_594 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 282:32] - io.ahb.out.hwdata <= _T_594 @[axi4_to_ahb.scala 282:21] - slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 284:15] - node _T_595 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 285:43] - node _T_596 = mux(_T_595, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 285:23] - node _T_597 = bits(slvbuf_error, 0, 0) @[Bitwise.scala 72:15] - node _T_598 = mux(_T_597, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_599 = and(_T_598, UInt<2>("h02")) @[axi4_to_ahb.scala 285:88] - node _T_600 = cat(_T_596, _T_599) @[Cat.scala 29:58] - slave_opc <= _T_600 @[axi4_to_ahb.scala 285:13] - node _T_601 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 286:41] - node _T_602 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 286:66] - node _T_603 = cat(_T_602, _T_602) @[Cat.scala 29:58] - node _T_604 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 286:91] - node _T_605 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 286:110] - node _T_606 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 286:131] - node _T_607 = mux(_T_604, _T_605, _T_606) @[axi4_to_ahb.scala 286:79] - node _T_608 = mux(_T_601, _T_603, _T_607) @[axi4_to_ahb.scala 286:21] - slave_rdata <= _T_608 @[axi4_to_ahb.scala 286:15] - node _T_609 = bits(slvbuf_tag, 0, 0) @[axi4_to_ahb.scala 287:26] - slave_tag <= _T_609 @[axi4_to_ahb.scala 287:13] - node _T_610 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 289:37] - node _T_611 = neq(_T_610, UInt<1>("h00")) @[axi4_to_ahb.scala 289:44] - node _T_612 = and(_T_611, io.ahb.in.hready) @[axi4_to_ahb.scala 289:56] - node _T_613 = and(_T_612, io.ahb.out.hwrite) @[axi4_to_ahb.scala 289:75] - last_addr_en <= _T_613 @[axi4_to_ahb.scala 289:16] - node _T_614 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 291:31] - node _T_615 = and(_T_614, master_ready) @[axi4_to_ahb.scala 291:49] - wrbuf_en <= _T_615 @[axi4_to_ahb.scala 291:12] - node _T_616 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 292:35] - node _T_617 = and(_T_616, master_ready) @[axi4_to_ahb.scala 292:52] - wrbuf_data_en <= _T_617 @[axi4_to_ahb.scala 292:17] - node _T_618 = and(master_valid, master_ready) @[axi4_to_ahb.scala 293:34] - node _T_619 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 293:62] - node _T_620 = eq(_T_619, UInt<1>("h01")) @[axi4_to_ahb.scala 293:69] - node _T_621 = and(_T_618, _T_620) @[axi4_to_ahb.scala 293:49] - wrbuf_cmd_sent <= _T_621 @[axi4_to_ahb.scala 293:18] - node _T_622 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 294:33] - node _T_623 = and(wrbuf_cmd_sent, _T_622) @[axi4_to_ahb.scala 294:31] - wrbuf_rst <= _T_623 @[axi4_to_ahb.scala 294:13] - node _T_624 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 296:36] - node _T_625 = and(wrbuf_vld, _T_624) @[axi4_to_ahb.scala 296:34] - node _T_626 = eq(_T_625, UInt<1>("h00")) @[axi4_to_ahb.scala 296:22] - node _T_627 = and(_T_626, master_ready) @[axi4_to_ahb.scala 296:53] - io.axi.aw.ready <= _T_627 @[axi4_to_ahb.scala 296:19] - node _T_628 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 297:40] - node _T_629 = and(wrbuf_data_vld, _T_628) @[axi4_to_ahb.scala 297:38] - node _T_630 = eq(_T_629, UInt<1>("h00")) @[axi4_to_ahb.scala 297:21] - node _T_631 = and(_T_630, master_ready) @[axi4_to_ahb.scala 297:57] - io.axi.w.ready <= _T_631 @[axi4_to_ahb.scala 297:18] - node _T_632 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 298:34] - node _T_633 = eq(_T_632, UInt<1>("h00")) @[axi4_to_ahb.scala 298:22] - node _T_634 = and(_T_633, master_ready) @[axi4_to_ahb.scala 298:52] - io.axi.ar.ready <= _T_634 @[axi4_to_ahb.scala 298:19] - io.axi.r.bits.last <= UInt<1>("h01") @[axi4_to_ahb.scala 299:22] - node _T_635 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 301:71] - node _T_636 = mux(_T_635, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 301:55] - node _T_637 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 301:91] - node _T_638 = and(_T_636, _T_637) @[axi4_to_ahb.scala 301:89] - reg _T_639 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 301:51] - _T_639 <= _T_638 @[axi4_to_ahb.scala 301:51] - wrbuf_vld <= _T_639 @[axi4_to_ahb.scala 301:21] - node _T_640 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 302:76] - node _T_641 = mux(_T_640, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 302:55] - node _T_642 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 302:102] - node _T_643 = and(_T_641, _T_642) @[axi4_to_ahb.scala 302:100] - reg _T_644 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 302:51] - _T_644 <= _T_643 @[axi4_to_ahb.scala 302:51] - wrbuf_data_vld <= _T_644 @[axi4_to_ahb.scala 302:21] - node _T_645 = bits(io.axi.aw.bits.id, 0, 0) @[axi4_to_ahb.scala 303:71] - node _T_646 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 303:105] - reg _T_647 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_646 : @[Reg.scala 28:19] - _T_647 <= _T_645 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - wrbuf_tag <= _T_647 @[axi4_to_ahb.scala 303:21] - node _T_648 = bits(io.axi.aw.bits.size, 2, 0) @[axi4_to_ahb.scala 304:73] - node _T_649 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 304:101] - reg _T_650 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_649 : @[Reg.scala 28:19] - _T_650 <= _T_648 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - wrbuf_size <= _T_650 @[axi4_to_ahb.scala 304:21] - node _T_651 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 305:61] - inst rvclkhdr_2 of rvclkhdr_851 @[lib.scala 368:23] - rvclkhdr_2.clock <= clock - rvclkhdr_2.reset <= reset - rvclkhdr_2.io.clk <= bus_clk @[lib.scala 370:18] - rvclkhdr_2.io.en <= _T_651 @[lib.scala 371:17] - rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_652 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_652 <= io.axi.aw.bits.addr @[lib.scala 374:16] - wrbuf_addr <= _T_652 @[axi4_to_ahb.scala 305:21] - node _T_653 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 306:65] - inst rvclkhdr_3 of rvclkhdr_852 @[lib.scala 368:23] - rvclkhdr_3.clock <= clock - rvclkhdr_3.reset <= reset - rvclkhdr_3.io.clk <= bus_clk @[lib.scala 370:18] - rvclkhdr_3.io.en <= _T_653 @[lib.scala 371:17] - rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_654 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_654 <= io.axi.w.bits.data @[lib.scala 374:16] - wrbuf_data <= _T_654 @[axi4_to_ahb.scala 306:21] - node _T_655 = bits(io.axi.w.bits.strb, 7, 0) @[axi4_to_ahb.scala 307:72] - node _T_656 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 307:105] - reg _T_657 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_656 : @[Reg.scala 28:19] - _T_657 <= _T_655 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - wrbuf_byteen <= _T_657 @[axi4_to_ahb.scala 307:21] - node _T_658 = bits(io.ahb.out.haddr, 31, 0) @[axi4_to_ahb.scala 308:71] - node _T_659 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 308:104] - reg _T_660 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_659 : @[Reg.scala 28:19] - _T_660 <= _T_658 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - last_bus_addr <= _T_660 @[axi4_to_ahb.scala 308:21] - node _T_661 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 309:89] - reg _T_662 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_661 : @[Reg.scala 28:19] - _T_662 <= buf_write_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_write <= _T_662 @[axi4_to_ahb.scala 309:21] - node _T_663 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 310:64] - node _T_664 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 310:99] - reg _T_665 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_664 : @[Reg.scala 28:19] - _T_665 <= _T_663 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_tag <= _T_665 @[axi4_to_ahb.scala 310:21] - node _T_666 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 311:42] - node _T_667 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 311:61] - node _T_668 = bits(_T_667, 0, 0) @[axi4_to_ahb.scala 311:78] - inst rvclkhdr_4 of rvclkhdr_853 @[lib.scala 368:23] - rvclkhdr_4.clock <= clock - rvclkhdr_4.reset <= reset - rvclkhdr_4.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_4.io.en <= _T_668 @[lib.scala 371:17] - rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_669 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_669 <= _T_666 @[lib.scala 374:16] - buf_addr <= _T_669 @[axi4_to_ahb.scala 311:21] - node _T_670 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 312:65] - node _T_671 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 312:94] - reg _T_672 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_671 : @[Reg.scala 28:19] - _T_672 <= _T_670 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_size <= _T_672 @[axi4_to_ahb.scala 312:21] - node _T_673 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 313:91] - reg _T_674 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_673 : @[Reg.scala 28:19] - _T_674 <= buf_aligned_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_aligned <= _T_674 @[axi4_to_ahb.scala 313:21] - node _T_675 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 314:67] - node _T_676 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 314:96] - reg _T_677 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_676 : @[Reg.scala 28:19] - _T_677 <= _T_675 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_byteen <= _T_677 @[axi4_to_ahb.scala 314:21] - node _T_678 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 315:42] - node _T_679 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 315:66] - node _T_680 = bits(_T_679, 0, 0) @[axi4_to_ahb.scala 315:89] - inst rvclkhdr_5 of rvclkhdr_854 @[lib.scala 368:23] - rvclkhdr_5.clock <= clock - rvclkhdr_5.reset <= reset - rvclkhdr_5.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_5.io.en <= _T_680 @[lib.scala 371:17] - rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_681 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_681 <= _T_678 @[lib.scala 374:16] - buf_data <= _T_681 @[axi4_to_ahb.scala 315:21] - node _T_682 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 316:89] - reg _T_683 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_682 : @[Reg.scala 28:19] - _T_683 <= buf_write @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - slvbuf_write <= _T_683 @[axi4_to_ahb.scala 316:21] - node _T_684 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 317:61] - node _T_685 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 317:99] - reg _T_686 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_685 : @[Reg.scala 28:19] - _T_686 <= _T_684 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - slvbuf_tag <= _T_686 @[axi4_to_ahb.scala 317:21] - node _T_687 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 318:99] - reg _T_688 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_687 : @[Reg.scala 28:19] - _T_688 <= slvbuf_error_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - slvbuf_error <= _T_688 @[axi4_to_ahb.scala 318:21] - node _T_689 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 319:72] - node _T_690 = mux(_T_689, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 319:56] - node _T_691 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 319:92] - node _T_692 = and(_T_690, _T_691) @[axi4_to_ahb.scala 319:90] - reg _T_693 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 319:52] - _T_693 <= _T_692 @[axi4_to_ahb.scala 319:52] - cmd_doneQ <= _T_693 @[axi4_to_ahb.scala 319:21] - node _T_694 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 320:71] - node _T_695 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 320:110] - reg _T_696 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_695 : @[Reg.scala 28:19] - _T_696 <= _T_694 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_cmd_byte_ptrQ <= _T_696 @[axi4_to_ahb.scala 320:21] - reg _T_697 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 321:52] - _T_697 <= io.ahb.in.hready @[axi4_to_ahb.scala 321:52] - ahb_hready_q <= _T_697 @[axi4_to_ahb.scala 321:21] - node _T_698 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 322:70] - reg _T_699 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 322:52] - _T_699 <= _T_698 @[axi4_to_ahb.scala 322:52] - ahb_htrans_q <= _T_699 @[axi4_to_ahb.scala 322:21] - reg _T_700 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 323:57] - _T_700 <= io.ahb.out.hwrite @[axi4_to_ahb.scala 323:57] - ahb_hwrite_q <= _T_700 @[axi4_to_ahb.scala 323:21] - reg _T_701 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 324:52] - _T_701 <= io.ahb.in.hresp @[axi4_to_ahb.scala 324:52] - ahb_hresp_q <= _T_701 @[axi4_to_ahb.scala 324:21] - node _T_702 = bits(io.ahb.in.hrdata, 63, 0) @[axi4_to_ahb.scala 325:74] - reg _T_703 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 325:57] - _T_703 <= _T_702 @[axi4_to_ahb.scala 325:57] - ahb_hrdata_q <= _T_703 @[axi4_to_ahb.scala 325:21] - node _T_704 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 327:43] - node _T_705 = or(_T_704, io.clk_override) @[axi4_to_ahb.scala 327:58] - node _T_706 = and(io.bus_clk_en, _T_705) @[axi4_to_ahb.scala 327:30] - buf_clken <= _T_706 @[axi4_to_ahb.scala 327:13] - node _T_707 = bits(io.ahb.out.htrans, 1, 1) @[axi4_to_ahb.scala 328:76] - node _T_708 = and(io.ahb.in.hready, _T_707) @[axi4_to_ahb.scala 328:57] - node _T_709 = or(_T_708, io.clk_override) @[axi4_to_ahb.scala 328:81] - node _T_710 = and(io.bus_clk_en, _T_709) @[axi4_to_ahb.scala 328:36] - ahbm_addr_clken <= _T_710 @[axi4_to_ahb.scala 328:19] - node _T_711 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 329:50] - node _T_712 = or(_T_711, io.clk_override) @[axi4_to_ahb.scala 329:60] - node _T_713 = and(io.bus_clk_en, _T_712) @[axi4_to_ahb.scala 329:36] - ahbm_data_clken <= _T_713 @[axi4_to_ahb.scala 329:19] - inst rvclkhdr_6 of rvclkhdr_855 @[lib.scala 343:22] - rvclkhdr_6.clock <= clock - rvclkhdr_6.reset <= reset - rvclkhdr_6.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_6.io.en <= buf_clken @[lib.scala 345:16] - rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - buf_clk <= rvclkhdr_6.io.l1clk @[axi4_to_ahb.scala 332:12] - inst rvclkhdr_7 of rvclkhdr_856 @[lib.scala 343:22] - rvclkhdr_7.clock <= clock - rvclkhdr_7.reset <= reset - rvclkhdr_7.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_7.io.en <= io.bus_clk_en @[lib.scala 345:16] - rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahbm_clk <= rvclkhdr_7.io.l1clk @[axi4_to_ahb.scala 333:12] - inst rvclkhdr_8 of rvclkhdr_857 @[lib.scala 343:22] - rvclkhdr_8.clock <= clock - rvclkhdr_8.reset <= reset - rvclkhdr_8.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_8.io.en <= ahbm_addr_clken @[lib.scala 345:16] - rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahbm_addr_clk <= rvclkhdr_8.io.l1clk @[axi4_to_ahb.scala 334:17] - inst rvclkhdr_9 of rvclkhdr_858 @[lib.scala 343:22] - rvclkhdr_9.clock <= clock - rvclkhdr_9.reset <= reset - rvclkhdr_9.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_9.io.en <= ahbm_data_clken @[lib.scala 345:16] - rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahbm_data_clk <= rvclkhdr_9.io.l1clk @[axi4_to_ahb.scala 335:17] - - extmodule gated_latch_859 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_859 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_859 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_860 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_860 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_860 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_861 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_861 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_861 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_862 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_862 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_862 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_863 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_863 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_863 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_864 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_864 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_864 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_865 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_865 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_865 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_866 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_866 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_866 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_867 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_867 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_867 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_868 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_868 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_868 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - module axi4_to_ahb_1 : - input clock : Clock - input reset : AsyncReset - output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ahb : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}} - - wire buf_rst : UInt<1> - buf_rst <= UInt<1>("h00") - buf_rst <= UInt<1>("h00") @[axi4_to_ahb.scala 21:11] - io.ahb.out.htrans <= UInt<1>("h00") @[axi4_to_ahb.scala 22:21] - wire buf_state_en : UInt<1> - buf_state_en <= UInt<1>("h00") - wire ahbm_clk : Clock @[axi4_to_ahb.scala 24:22] - wire ahbm_addr_clk : Clock @[axi4_to_ahb.scala 25:27] - wire ahbm_data_clk : Clock @[axi4_to_ahb.scala 26:27] - wire buf_state : UInt<3> - buf_state <= UInt<3>("h00") - wire buf_nxtstate : UInt<3> - buf_nxtstate <= UInt<3>("h00") - node _T = bits(buf_state_en, 0, 0) @[axi4_to_ahb.scala 30:70] - node _T_1 = mux(_T, buf_nxtstate, buf_state) @[axi4_to_ahb.scala 30:50] - node _T_2 = eq(buf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 30:108] - node _T_3 = bits(_T_2, 0, 0) @[Bitwise.scala 72:15] - node _T_4 = mux(_T_3, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_5 = and(_T_1, _T_4) @[axi4_to_ahb.scala 30:98] - reg _T_6 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 30:45] - _T_6 <= _T_5 @[axi4_to_ahb.scala 30:45] - buf_state <= _T_6 @[axi4_to_ahb.scala 30:13] - wire slave_valid : UInt<1> - slave_valid <= UInt<1>("h00") - wire slave_ready : UInt<1> - slave_ready <= UInt<1>("h00") - wire slave_tag : UInt<3> - slave_tag <= UInt<3>("h00") - wire slave_rdata : UInt<64> - slave_rdata <= UInt<64>("h00") - wire slave_opc : UInt<4> - slave_opc <= UInt<4>("h00") - wire wrbuf_en : UInt<1> - wrbuf_en <= UInt<1>("h00") - wire wrbuf_data_en : UInt<1> - wrbuf_data_en <= UInt<1>("h00") - wire wrbuf_cmd_sent : UInt<1> - wrbuf_cmd_sent <= UInt<1>("h00") - wire wrbuf_rst : UInt<1> - wrbuf_rst <= UInt<1>("h00") - wire wrbuf_vld : UInt<1> - wrbuf_vld <= UInt<1>("h00") - wire wrbuf_data_vld : UInt<1> - wrbuf_data_vld <= UInt<1>("h00") - wire wrbuf_tag : UInt<3> - wrbuf_tag <= UInt<3>("h00") - wire wrbuf_size : UInt<3> - wrbuf_size <= UInt<3>("h00") - wire wrbuf_addr : UInt<32> - wrbuf_addr <= UInt<32>("h00") - wire wrbuf_data : UInt<64> - wrbuf_data <= UInt<64>("h00") - wire wrbuf_byteen : UInt<8> - wrbuf_byteen <= UInt<8>("h00") - wire bus_write_clk_en : UInt<1> - bus_write_clk_en <= UInt<1>("h00") - wire bus_clk : Clock @[axi4_to_ahb.scala 50:21] - wire bus_write_clk : Clock @[axi4_to_ahb.scala 51:27] - wire master_valid : UInt<1> - master_valid <= UInt<1>("h00") - wire master_ready : UInt<1> - master_ready <= UInt<1>("h00") - wire master_tag : UInt<3> - master_tag <= UInt<3>("h00") - wire master_addr : UInt<32> - master_addr <= UInt<32>("h00") - wire master_wdata : UInt<64> - master_wdata <= UInt<64>("h00") - wire master_size : UInt<3> - master_size <= UInt<3>("h00") - wire master_opc : UInt<3> - master_opc <= UInt<3>("h00") - wire master_byteen : UInt<8> - master_byteen <= UInt<8>("h00") - wire buf_addr : UInt<32> - buf_addr <= UInt<32>("h00") - wire buf_size : UInt<2> - buf_size <= UInt<2>("h00") - wire buf_write : UInt<1> - buf_write <= UInt<1>("h00") - wire buf_byteen : UInt<8> - buf_byteen <= UInt<8>("h00") - wire buf_aligned : UInt<1> - buf_aligned <= UInt<1>("h00") - wire buf_data : UInt<64> - buf_data <= UInt<64>("h00") - wire buf_tag : UInt<3> - buf_tag <= UInt<3>("h00") - wire buf_tag_in : UInt<3> - buf_tag_in <= UInt<3>("h00") - wire buf_addr_in : UInt<32> - buf_addr_in <= UInt<32>("h00") - wire buf_byteen_in : UInt<8> - buf_byteen_in <= UInt<8>("h00") - wire buf_data_in : UInt<64> - buf_data_in <= UInt<64>("h00") - wire buf_write_in : UInt<1> - buf_write_in <= UInt<1>("h00") - wire buf_aligned_in : UInt<1> - buf_aligned_in <= UInt<1>("h00") - wire buf_size_in : UInt<3> - buf_size_in <= UInt<3>("h00") - wire buf_wr_en : UInt<1> - buf_wr_en <= UInt<1>("h00") - wire buf_data_wr_en : UInt<1> - buf_data_wr_en <= UInt<1>("h00") - wire slvbuf_error_en : UInt<1> - slvbuf_error_en <= UInt<1>("h00") - wire wr_cmd_vld : UInt<1> - wr_cmd_vld <= UInt<1>("h00") - wire cmd_done_rst : UInt<1> - cmd_done_rst <= UInt<1>("h00") - wire cmd_done : UInt<1> - cmd_done <= UInt<1>("h00") - wire cmd_doneQ : UInt<1> - cmd_doneQ <= UInt<1>("h00") - wire trxn_done : UInt<1> - trxn_done <= UInt<1>("h00") - wire buf_cmd_byte_ptr : UInt<3> - buf_cmd_byte_ptr <= UInt<3>("h00") - wire buf_cmd_byte_ptrQ : UInt<3> - buf_cmd_byte_ptrQ <= UInt<3>("h00") - wire buf_cmd_nxtbyte_ptr : UInt<3> - buf_cmd_nxtbyte_ptr <= UInt<3>("h00") - wire buf_cmd_byte_ptr_en : UInt<1> - buf_cmd_byte_ptr_en <= UInt<1>("h00") - wire found : UInt<1> - found <= UInt<1>("h00") - wire slave_valid_pre : UInt<1> - slave_valid_pre <= UInt<1>("h00") - wire ahb_hready_q : UInt<1> - ahb_hready_q <= UInt<1>("h00") - wire ahb_hresp_q : UInt<1> - ahb_hresp_q <= UInt<1>("h00") - wire ahb_htrans_q : UInt<2> - ahb_htrans_q <= UInt<2>("h00") - wire ahb_hwrite_q : UInt<1> - ahb_hwrite_q <= UInt<1>("h00") - wire ahb_hrdata_q : UInt<64> - ahb_hrdata_q <= UInt<64>("h00") - wire slvbuf_write : UInt<1> - slvbuf_write <= UInt<1>("h00") - wire slvbuf_error : UInt<1> - slvbuf_error <= UInt<1>("h00") - wire slvbuf_tag : UInt<3> - slvbuf_tag <= UInt<3>("h00") - wire slvbuf_error_in : UInt<1> - slvbuf_error_in <= UInt<1>("h00") - wire slvbuf_wr_en : UInt<1> - slvbuf_wr_en <= UInt<1>("h00") - wire bypass_en : UInt<1> - bypass_en <= UInt<1>("h00") - wire rd_bypass_idle : UInt<1> - rd_bypass_idle <= UInt<1>("h00") - wire last_addr_en : UInt<1> - last_addr_en <= UInt<1>("h00") - wire last_bus_addr : UInt<32> - last_bus_addr <= UInt<32>("h00") - wire buf_clken : UInt<1> - buf_clken <= UInt<1>("h00") - wire slvbuf_clken : UInt<1> - slvbuf_clken <= UInt<1>("h00") - wire ahbm_addr_clken : UInt<1> - ahbm_addr_clken <= UInt<1>("h00") - wire ahbm_data_clken : UInt<1> - ahbm_data_clken <= UInt<1>("h00") - wire buf_clk : Clock @[axi4_to_ahb.scala 118:21] - node _T_7 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 139:27] - wr_cmd_vld <= _T_7 @[axi4_to_ahb.scala 139:14] - node _T_8 = or(wr_cmd_vld, io.axi.ar.valid) @[axi4_to_ahb.scala 140:30] - master_valid <= _T_8 @[axi4_to_ahb.scala 140:16] - node _T_9 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 141:38] - node _T_10 = bits(wrbuf_tag, 2, 0) @[axi4_to_ahb.scala 141:51] - node _T_11 = bits(io.axi.ar.bits.id, 2, 0) @[axi4_to_ahb.scala 141:82] - node _T_12 = mux(_T_9, _T_10, _T_11) @[axi4_to_ahb.scala 141:20] - master_tag <= _T_12 @[axi4_to_ahb.scala 141:14] - node _T_13 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 142:38] - node _T_14 = mux(_T_13, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 142:20] - master_opc <= _T_14 @[axi4_to_ahb.scala 142:14] - node _T_15 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 143:39] - node _T_16 = bits(wrbuf_addr, 31, 0) @[axi4_to_ahb.scala 143:53] - node _T_17 = bits(io.axi.ar.bits.addr, 31, 0) @[axi4_to_ahb.scala 143:81] - node _T_18 = mux(_T_15, _T_16, _T_17) @[axi4_to_ahb.scala 143:21] - master_addr <= _T_18 @[axi4_to_ahb.scala 143:15] - node _T_19 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 144:39] - node _T_20 = bits(wrbuf_size, 2, 0) @[axi4_to_ahb.scala 144:53] - node _T_21 = bits(io.axi.ar.bits.size, 2, 0) @[axi4_to_ahb.scala 144:80] - node _T_22 = mux(_T_19, _T_20, _T_21) @[axi4_to_ahb.scala 144:21] - master_size <= _T_22 @[axi4_to_ahb.scala 144:15] - node _T_23 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 145:32] - master_byteen <= _T_23 @[axi4_to_ahb.scala 145:17] - node _T_24 = bits(wrbuf_data, 63, 0) @[axi4_to_ahb.scala 146:29] - master_wdata <= _T_24 @[axi4_to_ahb.scala 146:16] - node _T_25 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 149:33] - node _T_26 = bits(slave_opc, 3, 3) @[axi4_to_ahb.scala 149:58] - node _T_27 = and(_T_25, _T_26) @[axi4_to_ahb.scala 149:47] - io.axi.b.valid <= _T_27 @[axi4_to_ahb.scala 149:18] - node _T_28 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 150:38] - node _T_29 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 150:65] - node _T_30 = mux(_T_29, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 150:55] - node _T_31 = mux(_T_28, UInt<2>("h02"), _T_30) @[axi4_to_ahb.scala 150:28] - io.axi.b.bits.resp <= _T_31 @[axi4_to_ahb.scala 150:22] - node _T_32 = bits(slave_tag, 2, 0) @[axi4_to_ahb.scala 151:32] - io.axi.b.bits.id <= _T_32 @[axi4_to_ahb.scala 151:20] - node _T_33 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 153:33] - node _T_34 = bits(slave_opc, 3, 2) @[axi4_to_ahb.scala 153:59] - node _T_35 = eq(_T_34, UInt<1>("h00")) @[axi4_to_ahb.scala 153:66] - node _T_36 = and(_T_33, _T_35) @[axi4_to_ahb.scala 153:47] - io.axi.r.valid <= _T_36 @[axi4_to_ahb.scala 153:18] - node _T_37 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 154:38] - node _T_38 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 154:65] - node _T_39 = mux(_T_38, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 154:55] - node _T_40 = mux(_T_37, UInt<2>("h02"), _T_39) @[axi4_to_ahb.scala 154:28] - io.axi.r.bits.resp <= _T_40 @[axi4_to_ahb.scala 154:22] - node _T_41 = bits(slave_tag, 2, 0) @[axi4_to_ahb.scala 155:32] - io.axi.r.bits.id <= _T_41 @[axi4_to_ahb.scala 155:20] - node _T_42 = bits(slave_rdata, 63, 0) @[axi4_to_ahb.scala 156:36] - io.axi.r.bits.data <= _T_42 @[axi4_to_ahb.scala 156:22] - node _T_43 = and(io.axi.b.ready, io.axi.r.ready) @[axi4_to_ahb.scala 157:33] - slave_ready <= _T_43 @[axi4_to_ahb.scala 157:15] - node _T_44 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 160:57] - node _T_45 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 160:94] - node _T_46 = or(_T_44, _T_45) @[axi4_to_ahb.scala 160:76] - node _T_47 = and(io.bus_clk_en, _T_46) @[axi4_to_ahb.scala 160:37] - bus_write_clk_en <= _T_47 @[axi4_to_ahb.scala 160:20] - inst rvclkhdr of rvclkhdr_859 @[lib.scala 343:22] - rvclkhdr.clock <= clock - rvclkhdr.reset <= reset - rvclkhdr.io.clk <= clock @[lib.scala 344:17] - rvclkhdr.io.en <= io.bus_clk_en @[lib.scala 345:16] - rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - bus_clk <= rvclkhdr.io.l1clk @[axi4_to_ahb.scala 162:11] - node _T_48 = bits(bus_write_clk_en, 0, 0) @[axi4_to_ahb.scala 163:59] - inst rvclkhdr_1 of rvclkhdr_860 @[lib.scala 343:22] - rvclkhdr_1.clock <= clock - rvclkhdr_1.reset <= reset - rvclkhdr_1.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_1.io.en <= _T_48 @[lib.scala 345:16] - rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - bus_write_clk <= rvclkhdr_1.io.l1clk @[axi4_to_ahb.scala 163:17] - node _T_49 = eq(UInt<3>("h00"), buf_state) @[Conditional.scala 37:30] - when _T_49 : @[Conditional.scala 40:58] - master_ready <= UInt<1>("h01") @[axi4_to_ahb.scala 167:20] - node _T_50 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 168:34] - node _T_51 = eq(_T_50, UInt<1>("h01")) @[axi4_to_ahb.scala 168:41] - buf_write_in <= _T_51 @[axi4_to_ahb.scala 168:20] - node _T_52 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 169:46] - node _T_53 = mux(_T_52, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 169:26] - buf_nxtstate <= _T_53 @[axi4_to_ahb.scala 169:20] - node _T_54 = and(master_valid, UInt<1>("h01")) @[axi4_to_ahb.scala 170:36] - buf_state_en <= _T_54 @[axi4_to_ahb.scala 170:20] - buf_wr_en <= buf_state_en @[axi4_to_ahb.scala 171:17] - node _T_55 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 172:54] - node _T_56 = and(buf_state_en, _T_55) @[axi4_to_ahb.scala 172:38] - buf_data_wr_en <= _T_56 @[axi4_to_ahb.scala 172:22] - buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 173:27] - node _T_57 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 175:50] - node _T_58 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 175:94] - node _T_59 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_60 = tail(_T_59, 1) @[axi4_to_ahb.scala 135:52] - node _T_61 = mux(UInt<1>("h00"), _T_60, UInt<3>("h00")) @[axi4_to_ahb.scala 135:24] - node _T_62 = bits(_T_58, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_63 = geq(UInt<1>("h00"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_64 = and(_T_62, _T_63) @[axi4_to_ahb.scala 136:48] - node _T_65 = bits(_T_58, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_66 = geq(UInt<1>("h01"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_67 = and(_T_65, _T_66) @[axi4_to_ahb.scala 136:48] - node _T_68 = bits(_T_58, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_69 = geq(UInt<2>("h02"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_70 = and(_T_68, _T_69) @[axi4_to_ahb.scala 136:48] - node _T_71 = bits(_T_58, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_72 = geq(UInt<2>("h03"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_73 = and(_T_71, _T_72) @[axi4_to_ahb.scala 136:48] - node _T_74 = bits(_T_58, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_75 = geq(UInt<3>("h04"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_76 = and(_T_74, _T_75) @[axi4_to_ahb.scala 136:48] - node _T_77 = bits(_T_58, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_78 = geq(UInt<3>("h05"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_79 = and(_T_77, _T_78) @[axi4_to_ahb.scala 136:48] - node _T_80 = bits(_T_58, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_81 = geq(UInt<3>("h06"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_82 = and(_T_80, _T_81) @[axi4_to_ahb.scala 136:48] - node _T_83 = bits(_T_58, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_84 = geq(UInt<3>("h07"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_85 = and(_T_83, _T_84) @[axi4_to_ahb.scala 136:48] - node _T_86 = mux(_T_85, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_87 = mux(_T_82, UInt<3>("h06"), _T_86) @[Mux.scala 98:16] - node _T_88 = mux(_T_79, UInt<3>("h05"), _T_87) @[Mux.scala 98:16] - node _T_89 = mux(_T_76, UInt<3>("h04"), _T_88) @[Mux.scala 98:16] - node _T_90 = mux(_T_73, UInt<2>("h03"), _T_89) @[Mux.scala 98:16] - node _T_91 = mux(_T_70, UInt<2>("h02"), _T_90) @[Mux.scala 98:16] - node _T_92 = mux(_T_67, UInt<1>("h01"), _T_91) @[Mux.scala 98:16] - node _T_93 = mux(_T_64, UInt<1>("h00"), _T_92) @[Mux.scala 98:16] - node _T_94 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 175:124] - node _T_95 = mux(_T_57, _T_93, _T_94) @[axi4_to_ahb.scala 175:30] - buf_cmd_byte_ptr <= _T_95 @[axi4_to_ahb.scala 175:24] - bypass_en <= buf_state_en @[axi4_to_ahb.scala 176:17] - node _T_96 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 177:51] - node _T_97 = and(bypass_en, _T_96) @[axi4_to_ahb.scala 177:35] - rd_bypass_idle <= _T_97 @[axi4_to_ahb.scala 177:22] - node _T_98 = bits(bypass_en, 0, 0) @[Bitwise.scala 72:15] - node _T_99 = mux(_T_98, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_100 = and(_T_99, UInt<2>("h02")) @[axi4_to_ahb.scala 178:49] - io.ahb.out.htrans <= _T_100 @[axi4_to_ahb.scala 178:25] - skip @[Conditional.scala 40:58] - else : @[Conditional.scala 39:67] - node _T_101 = eq(UInt<3>("h01"), buf_state) @[Conditional.scala 37:30] - when _T_101 : @[Conditional.scala 39:67] - node _T_102 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 182:54] - node _T_103 = eq(_T_102, UInt<1>("h00")) @[axi4_to_ahb.scala 182:61] - node _T_104 = and(master_valid, _T_103) @[axi4_to_ahb.scala 182:41] - node _T_105 = bits(_T_104, 0, 0) @[axi4_to_ahb.scala 182:82] - node _T_106 = mux(_T_105, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 182:26] - buf_nxtstate <= _T_106 @[axi4_to_ahb.scala 182:20] - node _T_107 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 183:51] - node _T_108 = neq(_T_107, UInt<1>("h00")) @[axi4_to_ahb.scala 183:58] - node _T_109 = and(ahb_hready_q, _T_108) @[axi4_to_ahb.scala 183:36] - node _T_110 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 183:72] - node _T_111 = and(_T_109, _T_110) @[axi4_to_ahb.scala 183:70] - buf_state_en <= _T_111 @[axi4_to_ahb.scala 183:20] - node _T_112 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 184:34] - node _T_113 = and(buf_state_en, _T_112) @[axi4_to_ahb.scala 184:32] - cmd_done <= _T_113 @[axi4_to_ahb.scala 184:16] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 185:20] - node _T_114 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 186:52] - node _T_115 = neq(_T_114, UInt<1>("h00")) @[axi4_to_ahb.scala 186:59] - node _T_116 = and(ahb_hready_q, _T_115) @[axi4_to_ahb.scala 186:37] - node _T_117 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 186:73] - node _T_118 = and(_T_116, _T_117) @[axi4_to_ahb.scala 186:71] - node _T_119 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 186:122] - node _T_120 = eq(_T_119, UInt<1>("h00")) @[axi4_to_ahb.scala 186:129] - node _T_121 = and(master_valid, _T_120) @[axi4_to_ahb.scala 186:109] - node _T_122 = bits(_T_121, 0, 0) @[axi4_to_ahb.scala 186:150] - node _T_123 = mux(_T_122, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 186:94] - node _T_124 = eq(_T_123, UInt<3>("h06")) @[axi4_to_ahb.scala 186:174] - node _T_125 = and(_T_118, _T_124) @[axi4_to_ahb.scala 186:88] - master_ready <= _T_125 @[axi4_to_ahb.scala 186:20] - buf_wr_en <= master_ready @[axi4_to_ahb.scala 187:17] - node _T_126 = and(master_ready, master_valid) @[axi4_to_ahb.scala 188:33] - bypass_en <= _T_126 @[axi4_to_ahb.scala 188:17] - node _T_127 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 189:47] - node _T_128 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 189:62] - node _T_129 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 189:78] - node _T_130 = mux(_T_127, _T_128, _T_129) @[axi4_to_ahb.scala 189:30] - buf_cmd_byte_ptr <= _T_130 @[axi4_to_ahb.scala 189:24] - node _T_131 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 190:48] - node _T_132 = or(_T_131, bypass_en) @[axi4_to_ahb.scala 190:62] - node _T_133 = bits(_T_132, 0, 0) @[Bitwise.scala 72:15] - node _T_134 = mux(_T_133, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_135 = and(UInt<2>("h02"), _T_134) @[axi4_to_ahb.scala 190:36] - io.ahb.out.htrans <= _T_135 @[axi4_to_ahb.scala 190:25] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_136 = eq(UInt<3>("h06"), buf_state) @[Conditional.scala 37:30] - when _T_136 : @[Conditional.scala 39:67] - node _T_137 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 194:39] - node _T_138 = and(ahb_hready_q, _T_137) @[axi4_to_ahb.scala 194:37] - node _T_139 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 194:82] - node _T_140 = eq(_T_139, UInt<1>("h01")) @[axi4_to_ahb.scala 194:89] - node _T_141 = and(master_valid, _T_140) @[axi4_to_ahb.scala 194:70] - node _T_142 = not(_T_141) @[axi4_to_ahb.scala 194:55] - node _T_143 = and(_T_138, _T_142) @[axi4_to_ahb.scala 194:53] - master_ready <= _T_143 @[axi4_to_ahb.scala 194:20] - node _T_144 = and(master_valid, master_ready) @[axi4_to_ahb.scala 195:34] - node _T_145 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 195:62] - node _T_146 = eq(_T_145, UInt<1>("h00")) @[axi4_to_ahb.scala 195:69] - node _T_147 = and(_T_144, _T_146) @[axi4_to_ahb.scala 195:49] - buf_wr_en <= _T_147 @[axi4_to_ahb.scala 195:17] - node _T_148 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 196:45] - node _T_149 = and(master_valid, master_ready) @[axi4_to_ahb.scala 196:82] - node _T_150 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 196:110] - node _T_151 = eq(_T_150, UInt<1>("h00")) @[axi4_to_ahb.scala 196:117] - node _T_152 = and(_T_149, _T_151) @[axi4_to_ahb.scala 196:97] - node _T_153 = bits(_T_152, 0, 0) @[axi4_to_ahb.scala 196:138] - node _T_154 = mux(_T_153, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 196:67] - node _T_155 = mux(_T_148, UInt<3>("h07"), _T_154) @[axi4_to_ahb.scala 196:26] - buf_nxtstate <= _T_155 @[axi4_to_ahb.scala 196:20] - node _T_156 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 197:37] - buf_state_en <= _T_156 @[axi4_to_ahb.scala 197:20] - buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 198:22] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 199:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 200:23] - node _T_157 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 201:41] - node _T_158 = and(buf_state_en, _T_157) @[axi4_to_ahb.scala 201:39] - slave_valid_pre <= _T_158 @[axi4_to_ahb.scala 201:23] - node _T_159 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 202:34] - node _T_160 = and(buf_state_en, _T_159) @[axi4_to_ahb.scala 202:32] - cmd_done <= _T_160 @[axi4_to_ahb.scala 202:16] - node _T_161 = and(master_ready, master_valid) @[axi4_to_ahb.scala 203:33] - node _T_162 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 203:64] - node _T_163 = and(_T_161, _T_162) @[axi4_to_ahb.scala 203:48] - node _T_164 = and(_T_163, buf_state_en) @[axi4_to_ahb.scala 203:79] - bypass_en <= _T_164 @[axi4_to_ahb.scala 203:17] - node _T_165 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 204:47] - node _T_166 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 204:62] - node _T_167 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 204:78] - node _T_168 = mux(_T_165, _T_166, _T_167) @[axi4_to_ahb.scala 204:30] - buf_cmd_byte_ptr <= _T_168 @[axi4_to_ahb.scala 204:24] - node _T_169 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 205:63] - node _T_170 = and(_T_169, buf_state_en) @[axi4_to_ahb.scala 205:78] - node _T_171 = eq(_T_170, UInt<1>("h00")) @[axi4_to_ahb.scala 205:47] - node _T_172 = bits(_T_171, 0, 0) @[Bitwise.scala 72:15] - node _T_173 = mux(_T_172, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_174 = and(UInt<2>("h02"), _T_173) @[axi4_to_ahb.scala 205:36] - io.ahb.out.htrans <= _T_174 @[axi4_to_ahb.scala 205:25] - slvbuf_wr_en <= buf_wr_en @[axi4_to_ahb.scala 206:20] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_175 = eq(UInt<3>("h07"), buf_state) @[Conditional.scala 37:30] - when _T_175 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h03") @[axi4_to_ahb.scala 210:20] - node _T_176 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 211:51] - node _T_177 = neq(_T_176, UInt<1>("h00")) @[axi4_to_ahb.scala 211:58] - node _T_178 = and(ahb_hready_q, _T_177) @[axi4_to_ahb.scala 211:36] - node _T_179 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 211:72] - node _T_180 = and(_T_178, _T_179) @[axi4_to_ahb.scala 211:70] - buf_state_en <= _T_180 @[axi4_to_ahb.scala 211:20] - slave_valid_pre <= buf_state_en @[axi4_to_ahb.scala 212:23] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 213:20] - node _T_181 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 214:35] - buf_cmd_byte_ptr <= _T_181 @[axi4_to_ahb.scala 214:24] - node _T_182 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 215:51] - node _T_183 = bits(_T_182, 0, 0) @[Bitwise.scala 72:15] - node _T_184 = mux(_T_183, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_185 = and(UInt<2>("h02"), _T_184) @[axi4_to_ahb.scala 215:41] - io.ahb.out.htrans <= _T_185 @[axi4_to_ahb.scala 215:25] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_186 = eq(UInt<3>("h03"), buf_state) @[Conditional.scala 37:30] - when _T_186 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h05") @[axi4_to_ahb.scala 219:20] - node _T_187 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 220:37] - buf_state_en <= _T_187 @[axi4_to_ahb.scala 220:20] - buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 221:22] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 222:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 223:23] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 224:20] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_188 = eq(UInt<3>("h02"), buf_state) @[Conditional.scala 37:30] - when _T_188 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h04") @[axi4_to_ahb.scala 228:20] - node _T_189 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 229:33] - node _T_190 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 229:63] - node _T_191 = neq(_T_190, UInt<1>("h00")) @[axi4_to_ahb.scala 229:70] - node _T_192 = and(_T_189, _T_191) @[axi4_to_ahb.scala 229:48] - trxn_done <= _T_192 @[axi4_to_ahb.scala 229:17] - buf_state_en <= trxn_done @[axi4_to_ahb.scala 230:20] - buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 231:27] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 232:20] - node _T_193 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 233:47] - node _T_194 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 233:85] - node _T_195 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 233:103] - node _T_196 = add(_T_194, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_197 = tail(_T_196, 1) @[axi4_to_ahb.scala 135:52] - node _T_198 = mux(UInt<1>("h01"), _T_197, _T_194) @[axi4_to_ahb.scala 135:24] - node _T_199 = bits(_T_195, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_200 = geq(UInt<1>("h00"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_201 = and(_T_199, _T_200) @[axi4_to_ahb.scala 136:48] - node _T_202 = bits(_T_195, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_203 = geq(UInt<1>("h01"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_204 = and(_T_202, _T_203) @[axi4_to_ahb.scala 136:48] - node _T_205 = bits(_T_195, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_206 = geq(UInt<2>("h02"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_207 = and(_T_205, _T_206) @[axi4_to_ahb.scala 136:48] - node _T_208 = bits(_T_195, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_209 = geq(UInt<2>("h03"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_210 = and(_T_208, _T_209) @[axi4_to_ahb.scala 136:48] - node _T_211 = bits(_T_195, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_212 = geq(UInt<3>("h04"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_213 = and(_T_211, _T_212) @[axi4_to_ahb.scala 136:48] - node _T_214 = bits(_T_195, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_215 = geq(UInt<3>("h05"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_216 = and(_T_214, _T_215) @[axi4_to_ahb.scala 136:48] - node _T_217 = bits(_T_195, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_218 = geq(UInt<3>("h06"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_219 = and(_T_217, _T_218) @[axi4_to_ahb.scala 136:48] - node _T_220 = bits(_T_195, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_221 = geq(UInt<3>("h07"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_222 = and(_T_220, _T_221) @[axi4_to_ahb.scala 136:48] - node _T_223 = mux(_T_222, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_224 = mux(_T_219, UInt<3>("h06"), _T_223) @[Mux.scala 98:16] - node _T_225 = mux(_T_216, UInt<3>("h05"), _T_224) @[Mux.scala 98:16] - node _T_226 = mux(_T_213, UInt<3>("h04"), _T_225) @[Mux.scala 98:16] - node _T_227 = mux(_T_210, UInt<2>("h03"), _T_226) @[Mux.scala 98:16] - node _T_228 = mux(_T_207, UInt<2>("h02"), _T_227) @[Mux.scala 98:16] - node _T_229 = mux(_T_204, UInt<1>("h01"), _T_228) @[Mux.scala 98:16] - node _T_230 = mux(_T_201, UInt<1>("h00"), _T_229) @[Mux.scala 98:16] - node _T_231 = mux(_T_193, _T_230, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 233:30] - buf_cmd_byte_ptr <= _T_231 @[axi4_to_ahb.scala 233:24] - node _T_232 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 234:65] - node _T_233 = or(buf_aligned, _T_232) @[axi4_to_ahb.scala 234:44] - node _T_234 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 234:127] - node _T_235 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 234:145] - node _T_236 = add(_T_234, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_237 = tail(_T_236, 1) @[axi4_to_ahb.scala 135:52] - node _T_238 = mux(UInt<1>("h01"), _T_237, _T_234) @[axi4_to_ahb.scala 135:24] - node _T_239 = bits(_T_235, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_240 = geq(UInt<1>("h00"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_241 = and(_T_239, _T_240) @[axi4_to_ahb.scala 136:48] - node _T_242 = bits(_T_235, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_243 = geq(UInt<1>("h01"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_244 = and(_T_242, _T_243) @[axi4_to_ahb.scala 136:48] - node _T_245 = bits(_T_235, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_246 = geq(UInt<2>("h02"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_247 = and(_T_245, _T_246) @[axi4_to_ahb.scala 136:48] - node _T_248 = bits(_T_235, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_249 = geq(UInt<2>("h03"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_250 = and(_T_248, _T_249) @[axi4_to_ahb.scala 136:48] - node _T_251 = bits(_T_235, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_252 = geq(UInt<3>("h04"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_253 = and(_T_251, _T_252) @[axi4_to_ahb.scala 136:48] - node _T_254 = bits(_T_235, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_255 = geq(UInt<3>("h05"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_256 = and(_T_254, _T_255) @[axi4_to_ahb.scala 136:48] - node _T_257 = bits(_T_235, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_258 = geq(UInt<3>("h06"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_259 = and(_T_257, _T_258) @[axi4_to_ahb.scala 136:48] - node _T_260 = bits(_T_235, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_261 = geq(UInt<3>("h07"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_262 = and(_T_260, _T_261) @[axi4_to_ahb.scala 136:48] - node _T_263 = mux(_T_262, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_264 = mux(_T_259, UInt<3>("h06"), _T_263) @[Mux.scala 98:16] - node _T_265 = mux(_T_256, UInt<3>("h05"), _T_264) @[Mux.scala 98:16] - node _T_266 = mux(_T_253, UInt<3>("h04"), _T_265) @[Mux.scala 98:16] - node _T_267 = mux(_T_250, UInt<2>("h03"), _T_266) @[Mux.scala 98:16] - node _T_268 = mux(_T_247, UInt<2>("h02"), _T_267) @[Mux.scala 98:16] - node _T_269 = mux(_T_244, UInt<1>("h01"), _T_268) @[Mux.scala 98:16] - node _T_270 = mux(_T_241, UInt<1>("h00"), _T_269) @[Mux.scala 98:16] - node _T_271 = dshr(buf_byteen, _T_270) @[axi4_to_ahb.scala 234:92] - node _T_272 = bits(_T_271, 0, 0) @[axi4_to_ahb.scala 234:92] - node _T_273 = eq(_T_272, UInt<1>("h00")) @[axi4_to_ahb.scala 234:163] - node _T_274 = or(_T_233, _T_273) @[axi4_to_ahb.scala 234:79] - node _T_275 = and(trxn_done, _T_274) @[axi4_to_ahb.scala 234:29] - cmd_done <= _T_275 @[axi4_to_ahb.scala 234:16] - node _T_276 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 235:47] - node _T_277 = eq(_T_276, UInt<1>("h00")) @[axi4_to_ahb.scala 235:36] - node _T_278 = bits(_T_277, 0, 0) @[Bitwise.scala 72:15] - node _T_279 = mux(_T_278, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_280 = and(_T_279, UInt<2>("h02")) @[axi4_to_ahb.scala 235:61] - io.ahb.out.htrans <= _T_280 @[axi4_to_ahb.scala 235:25] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_281 = eq(UInt<3>("h04"), buf_state) @[Conditional.scala 37:30] - when _T_281 : @[Conditional.scala 39:67] - node _T_282 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 239:34] - node _T_283 = or(_T_282, ahb_hresp_q) @[axi4_to_ahb.scala 239:50] - buf_state_en <= _T_283 @[axi4_to_ahb.scala 239:20] - node _T_284 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 240:38] - node _T_285 = and(buf_state_en, _T_284) @[axi4_to_ahb.scala 240:36] - node _T_286 = and(_T_285, slave_ready) @[axi4_to_ahb.scala 240:51] - master_ready <= _T_286 @[axi4_to_ahb.scala 240:20] - node _T_287 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 241:42] - node _T_288 = or(ahb_hresp_q, _T_287) @[axi4_to_ahb.scala 241:40] - node _T_289 = and(master_valid, master_valid) @[axi4_to_ahb.scala 241:80] - node _T_290 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 241:111] - node _T_291 = eq(_T_290, UInt<1>("h01")) @[axi4_to_ahb.scala 241:117] - node _T_292 = bits(_T_291, 0, 0) @[axi4_to_ahb.scala 241:132] - node _T_293 = mux(_T_292, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 241:99] - node _T_294 = mux(_T_289, _T_293, UInt<3>("h00")) @[axi4_to_ahb.scala 241:65] - node _T_295 = mux(_T_288, UInt<3>("h05"), _T_294) @[axi4_to_ahb.scala 241:26] - buf_nxtstate <= _T_295 @[axi4_to_ahb.scala 241:20] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 242:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 243:23] - node _T_296 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 244:33] - node _T_297 = eq(_T_296, UInt<1>("h01")) @[axi4_to_ahb.scala 244:39] - buf_write_in <= _T_297 @[axi4_to_ahb.scala 244:20] - node _T_298 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 245:50] - node _T_299 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 245:78] - node _T_300 = or(_T_298, _T_299) @[axi4_to_ahb.scala 245:62] - node _T_301 = and(buf_state_en, _T_300) @[axi4_to_ahb.scala 245:33] - buf_wr_en <= _T_301 @[axi4_to_ahb.scala 245:17] - buf_data_wr_en <= buf_wr_en @[axi4_to_ahb.scala 246:22] - node _T_302 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 247:65] - node _T_303 = neq(_T_302, UInt<1>("h00")) @[axi4_to_ahb.scala 247:71] - node _T_304 = and(ahb_hready_q, _T_303) @[axi4_to_ahb.scala 247:50] - node _T_305 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 248:29] - node _T_306 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 248:85] - node _T_307 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 248:101] - node _T_308 = add(_T_306, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_309 = tail(_T_308, 1) @[axi4_to_ahb.scala 135:52] - node _T_310 = mux(UInt<1>("h01"), _T_309, _T_306) @[axi4_to_ahb.scala 135:24] - node _T_311 = bits(_T_307, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_312 = geq(UInt<1>("h00"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_313 = and(_T_311, _T_312) @[axi4_to_ahb.scala 136:48] - node _T_314 = bits(_T_307, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_315 = geq(UInt<1>("h01"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_316 = and(_T_314, _T_315) @[axi4_to_ahb.scala 136:48] - node _T_317 = bits(_T_307, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_318 = geq(UInt<2>("h02"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_319 = and(_T_317, _T_318) @[axi4_to_ahb.scala 136:48] - node _T_320 = bits(_T_307, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_321 = geq(UInt<2>("h03"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_322 = and(_T_320, _T_321) @[axi4_to_ahb.scala 136:48] - node _T_323 = bits(_T_307, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_324 = geq(UInt<3>("h04"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_325 = and(_T_323, _T_324) @[axi4_to_ahb.scala 136:48] - node _T_326 = bits(_T_307, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_327 = geq(UInt<3>("h05"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_328 = and(_T_326, _T_327) @[axi4_to_ahb.scala 136:48] - node _T_329 = bits(_T_307, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_330 = geq(UInt<3>("h06"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_331 = and(_T_329, _T_330) @[axi4_to_ahb.scala 136:48] - node _T_332 = bits(_T_307, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_333 = geq(UInt<3>("h07"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_334 = and(_T_332, _T_333) @[axi4_to_ahb.scala 136:48] - node _T_335 = mux(_T_334, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_336 = mux(_T_331, UInt<3>("h06"), _T_335) @[Mux.scala 98:16] - node _T_337 = mux(_T_328, UInt<3>("h05"), _T_336) @[Mux.scala 98:16] - node _T_338 = mux(_T_325, UInt<3>("h04"), _T_337) @[Mux.scala 98:16] - node _T_339 = mux(_T_322, UInt<2>("h03"), _T_338) @[Mux.scala 98:16] - node _T_340 = mux(_T_319, UInt<2>("h02"), _T_339) @[Mux.scala 98:16] - node _T_341 = mux(_T_316, UInt<1>("h01"), _T_340) @[Mux.scala 98:16] - node _T_342 = mux(_T_313, UInt<1>("h00"), _T_341) @[Mux.scala 98:16] - node _T_343 = dshr(buf_byteen, _T_342) @[axi4_to_ahb.scala 248:51] - node _T_344 = bits(_T_343, 0, 0) @[axi4_to_ahb.scala 248:51] - node _T_345 = eq(_T_344, UInt<1>("h00")) @[axi4_to_ahb.scala 248:116] - node _T_346 = or(_T_305, _T_345) @[axi4_to_ahb.scala 248:38] - node _T_347 = and(_T_304, _T_346) @[axi4_to_ahb.scala 247:80] - node _T_348 = or(ahb_hresp_q, _T_347) @[axi4_to_ahb.scala 247:34] - cmd_done <= _T_348 @[axi4_to_ahb.scala 247:16] - node _T_349 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 249:33] - node _T_350 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 249:64] - node _T_351 = and(_T_349, _T_350) @[axi4_to_ahb.scala 249:48] - bypass_en <= _T_351 @[axi4_to_ahb.scala 249:17] - node _T_352 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 250:48] - node _T_353 = eq(_T_352, UInt<1>("h00")) @[axi4_to_ahb.scala 250:37] - node _T_354 = or(_T_353, bypass_en) @[axi4_to_ahb.scala 250:61] - node _T_355 = bits(_T_354, 0, 0) @[Bitwise.scala 72:15] - node _T_356 = mux(_T_355, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_357 = and(_T_356, UInt<2>("h02")) @[axi4_to_ahb.scala 250:75] - io.ahb.out.htrans <= _T_357 @[axi4_to_ahb.scala 250:25] - node _T_358 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 251:55] - node _T_359 = and(buf_state_en, _T_358) @[axi4_to_ahb.scala 251:39] - slave_valid_pre <= _T_359 @[axi4_to_ahb.scala 251:23] - node _T_360 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 252:33] - node _T_361 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 252:63] - node _T_362 = neq(_T_361, UInt<1>("h00")) @[axi4_to_ahb.scala 252:69] - node _T_363 = and(_T_360, _T_362) @[axi4_to_ahb.scala 252:48] - trxn_done <= _T_363 @[axi4_to_ahb.scala 252:17] - node _T_364 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 253:40] - buf_cmd_byte_ptr_en <= _T_364 @[axi4_to_ahb.scala 253:27] - node _T_365 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 254:79] - node _T_366 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_367 = tail(_T_366, 1) @[axi4_to_ahb.scala 135:52] - node _T_368 = mux(UInt<1>("h00"), _T_367, UInt<3>("h00")) @[axi4_to_ahb.scala 135:24] - node _T_369 = bits(_T_365, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_370 = geq(UInt<1>("h00"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_371 = and(_T_369, _T_370) @[axi4_to_ahb.scala 136:48] - node _T_372 = bits(_T_365, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_373 = geq(UInt<1>("h01"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_374 = and(_T_372, _T_373) @[axi4_to_ahb.scala 136:48] - node _T_375 = bits(_T_365, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_376 = geq(UInt<2>("h02"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_377 = and(_T_375, _T_376) @[axi4_to_ahb.scala 136:48] - node _T_378 = bits(_T_365, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_379 = geq(UInt<2>("h03"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_380 = and(_T_378, _T_379) @[axi4_to_ahb.scala 136:48] - node _T_381 = bits(_T_365, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_382 = geq(UInt<3>("h04"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_383 = and(_T_381, _T_382) @[axi4_to_ahb.scala 136:48] - node _T_384 = bits(_T_365, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_385 = geq(UInt<3>("h05"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_386 = and(_T_384, _T_385) @[axi4_to_ahb.scala 136:48] - node _T_387 = bits(_T_365, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_388 = geq(UInt<3>("h06"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_389 = and(_T_387, _T_388) @[axi4_to_ahb.scala 136:48] - node _T_390 = bits(_T_365, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_391 = geq(UInt<3>("h07"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_392 = and(_T_390, _T_391) @[axi4_to_ahb.scala 136:48] - node _T_393 = mux(_T_392, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_394 = mux(_T_389, UInt<3>("h06"), _T_393) @[Mux.scala 98:16] - node _T_395 = mux(_T_386, UInt<3>("h05"), _T_394) @[Mux.scala 98:16] - node _T_396 = mux(_T_383, UInt<3>("h04"), _T_395) @[Mux.scala 98:16] - node _T_397 = mux(_T_380, UInt<2>("h03"), _T_396) @[Mux.scala 98:16] - node _T_398 = mux(_T_377, UInt<2>("h02"), _T_397) @[Mux.scala 98:16] - node _T_399 = mux(_T_374, UInt<1>("h01"), _T_398) @[Mux.scala 98:16] - node _T_400 = mux(_T_371, UInt<1>("h00"), _T_399) @[Mux.scala 98:16] - node _T_401 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 254:141] - node _T_402 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 254:157] - node _T_403 = add(_T_401, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_404 = tail(_T_403, 1) @[axi4_to_ahb.scala 135:52] - node _T_405 = mux(UInt<1>("h01"), _T_404, _T_401) @[axi4_to_ahb.scala 135:24] - node _T_406 = bits(_T_402, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_407 = geq(UInt<1>("h00"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_408 = and(_T_406, _T_407) @[axi4_to_ahb.scala 136:48] - node _T_409 = bits(_T_402, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_410 = geq(UInt<1>("h01"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_411 = and(_T_409, _T_410) @[axi4_to_ahb.scala 136:48] - node _T_412 = bits(_T_402, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_413 = geq(UInt<2>("h02"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_414 = and(_T_412, _T_413) @[axi4_to_ahb.scala 136:48] - node _T_415 = bits(_T_402, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_416 = geq(UInt<2>("h03"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_417 = and(_T_415, _T_416) @[axi4_to_ahb.scala 136:48] - node _T_418 = bits(_T_402, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_419 = geq(UInt<3>("h04"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_420 = and(_T_418, _T_419) @[axi4_to_ahb.scala 136:48] - node _T_421 = bits(_T_402, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_422 = geq(UInt<3>("h05"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_423 = and(_T_421, _T_422) @[axi4_to_ahb.scala 136:48] - node _T_424 = bits(_T_402, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_425 = geq(UInt<3>("h06"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_426 = and(_T_424, _T_425) @[axi4_to_ahb.scala 136:48] - node _T_427 = bits(_T_402, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_428 = geq(UInt<3>("h07"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_429 = and(_T_427, _T_428) @[axi4_to_ahb.scala 136:48] - node _T_430 = mux(_T_429, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_431 = mux(_T_426, UInt<3>("h06"), _T_430) @[Mux.scala 98:16] - node _T_432 = mux(_T_423, UInt<3>("h05"), _T_431) @[Mux.scala 98:16] - node _T_433 = mux(_T_420, UInt<3>("h04"), _T_432) @[Mux.scala 98:16] - node _T_434 = mux(_T_417, UInt<2>("h03"), _T_433) @[Mux.scala 98:16] - node _T_435 = mux(_T_414, UInt<2>("h02"), _T_434) @[Mux.scala 98:16] - node _T_436 = mux(_T_411, UInt<1>("h01"), _T_435) @[Mux.scala 98:16] - node _T_437 = mux(_T_408, UInt<1>("h00"), _T_436) @[Mux.scala 98:16] - node _T_438 = mux(trxn_done, _T_437, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 254:97] - node _T_439 = mux(bypass_en, _T_400, _T_438) @[axi4_to_ahb.scala 254:30] - buf_cmd_byte_ptr <= _T_439 @[axi4_to_ahb.scala 254:24] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_440 = eq(UInt<3>("h05"), buf_state) @[Conditional.scala 37:30] - when _T_440 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 257:20] - buf_state_en <= slave_ready @[axi4_to_ahb.scala 258:20] - slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 259:23] - slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 260:23] - skip @[Conditional.scala 39:67] - cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 264:16] - node _T_441 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 265:33] - node _T_442 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 265:73] - node _T_443 = eq(_T_442, UInt<1>("h01")) @[axi4_to_ahb.scala 265:80] - node _T_444 = and(buf_aligned_in, _T_443) @[axi4_to_ahb.scala 265:60] - node _T_445 = bits(_T_444, 0, 0) @[axi4_to_ahb.scala 265:100] - node _T_446 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 265:132] - node _T_447 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 127:50] - node _T_448 = eq(_T_447, UInt<8>("h0ff")) @[axi4_to_ahb.scala 127:57] - node _T_449 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 127:81] - node _T_450 = eq(_T_449, UInt<8>("h0f")) @[axi4_to_ahb.scala 127:88] - node _T_451 = or(_T_448, _T_450) @[axi4_to_ahb.scala 127:70] - node _T_452 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 127:117] - node _T_453 = eq(_T_452, UInt<8>("h03")) @[axi4_to_ahb.scala 127:124] - node _T_454 = or(_T_451, _T_453) @[axi4_to_ahb.scala 127:106] - node _T_455 = bits(_T_454, 0, 0) @[Bitwise.scala 72:15] - node _T_456 = mux(_T_455, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_457 = and(UInt<3>("h00"), _T_456) @[axi4_to_ahb.scala 127:29] - node _T_458 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 128:35] - node _T_459 = eq(_T_458, UInt<8>("h0c")) @[axi4_to_ahb.scala 128:42] - node _T_460 = bits(_T_459, 0, 0) @[Bitwise.scala 72:15] - node _T_461 = mux(_T_460, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_462 = and(UInt<2>("h02"), _T_461) @[axi4_to_ahb.scala 128:15] - node _T_463 = or(_T_457, _T_462) @[axi4_to_ahb.scala 127:146] - node _T_464 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 129:36] - node _T_465 = eq(_T_464, UInt<8>("h0f0")) @[axi4_to_ahb.scala 129:43] - node _T_466 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 129:67] - node _T_467 = eq(_T_466, UInt<8>("h03")) @[axi4_to_ahb.scala 129:74] - node _T_468 = or(_T_465, _T_467) @[axi4_to_ahb.scala 129:56] - node _T_469 = bits(_T_468, 0, 0) @[Bitwise.scala 72:15] - node _T_470 = mux(_T_469, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_471 = and(UInt<3>("h04"), _T_470) @[axi4_to_ahb.scala 129:15] - node _T_472 = or(_T_463, _T_471) @[axi4_to_ahb.scala 128:63] - node _T_473 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 130:35] - node _T_474 = eq(_T_473, UInt<8>("h0c0")) @[axi4_to_ahb.scala 130:42] - node _T_475 = bits(_T_474, 0, 0) @[Bitwise.scala 72:15] - node _T_476 = mux(_T_475, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_477 = and(UInt<3>("h06"), _T_476) @[axi4_to_ahb.scala 130:15] - node _T_478 = or(_T_472, _T_477) @[axi4_to_ahb.scala 129:96] - node _T_479 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 131:33] - node _T_480 = eq(_T_479, UInt<8>("h0c0")) @[axi4_to_ahb.scala 131:40] - node _T_481 = bits(_T_480, 0, 0) @[Bitwise.scala 72:15] - node _T_482 = mux(_T_481, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_483 = and(UInt<3>("h06"), _T_482) @[axi4_to_ahb.scala 131:13] - node _T_484 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 265:152] - node _T_485 = mux(_T_445, _T_478, _T_484) @[axi4_to_ahb.scala 265:43] - node _T_486 = cat(_T_441, _T_485) @[Cat.scala 29:58] - buf_addr_in <= _T_486 @[axi4_to_ahb.scala 265:15] - node _T_487 = bits(master_tag, 2, 0) @[axi4_to_ahb.scala 266:27] - buf_tag_in <= _T_487 @[axi4_to_ahb.scala 266:14] - node _T_488 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 267:32] - buf_byteen_in <= _T_488 @[axi4_to_ahb.scala 267:17] - node _T_489 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 268:33] - node _T_490 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 268:59] - node _T_491 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 268:80] - node _T_492 = mux(_T_489, _T_490, _T_491) @[axi4_to_ahb.scala 268:21] - buf_data_in <= _T_492 @[axi4_to_ahb.scala 268:15] - node _T_493 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 269:52] - node _T_494 = eq(_T_493, UInt<2>("h03")) @[axi4_to_ahb.scala 269:58] - node _T_495 = and(buf_aligned_in, _T_494) @[axi4_to_ahb.scala 269:38] - node _T_496 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 269:84] - node _T_497 = eq(_T_496, UInt<1>("h01")) @[axi4_to_ahb.scala 269:91] - node _T_498 = and(_T_495, _T_497) @[axi4_to_ahb.scala 269:71] - node _T_499 = bits(_T_498, 0, 0) @[axi4_to_ahb.scala 269:111] - node _T_500 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 269:142] - node _T_501 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 121:42] - node _T_502 = eq(_T_501, UInt<8>("h0ff")) @[axi4_to_ahb.scala 121:49] - node _T_503 = bits(_T_502, 0, 0) @[Bitwise.scala 72:15] - node _T_504 = mux(_T_503, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_505 = and(UInt<2>("h03"), _T_504) @[axi4_to_ahb.scala 121:25] - node _T_506 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 122:35] - node _T_507 = eq(_T_506, UInt<8>("h0f0")) @[axi4_to_ahb.scala 122:42] - node _T_508 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 122:64] - node _T_509 = eq(_T_508, UInt<8>("h0f")) @[axi4_to_ahb.scala 122:71] - node _T_510 = or(_T_507, _T_509) @[axi4_to_ahb.scala 122:55] - node _T_511 = bits(_T_510, 0, 0) @[Bitwise.scala 72:15] - node _T_512 = mux(_T_511, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_513 = and(UInt<2>("h02"), _T_512) @[axi4_to_ahb.scala 122:16] - node _T_514 = or(_T_505, _T_513) @[axi4_to_ahb.scala 121:64] - node _T_515 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:40] - node _T_516 = eq(_T_515, UInt<8>("h0c0")) @[axi4_to_ahb.scala 123:47] - node _T_517 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:69] - node _T_518 = eq(_T_517, UInt<6>("h030")) @[axi4_to_ahb.scala 123:76] - node _T_519 = or(_T_516, _T_518) @[axi4_to_ahb.scala 123:60] - node _T_520 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:98] - node _T_521 = eq(_T_520, UInt<8>("h0c")) @[axi4_to_ahb.scala 123:105] - node _T_522 = or(_T_519, _T_521) @[axi4_to_ahb.scala 123:89] - node _T_523 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:132] - node _T_524 = eq(_T_523, UInt<8>("h03")) @[axi4_to_ahb.scala 123:139] - node _T_525 = or(_T_522, _T_524) @[axi4_to_ahb.scala 123:123] - node _T_526 = bits(_T_525, 0, 0) @[Bitwise.scala 72:15] - node _T_527 = mux(_T_526, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_528 = and(UInt<2>("h01"), _T_527) @[axi4_to_ahb.scala 123:21] - node _T_529 = or(_T_514, _T_528) @[axi4_to_ahb.scala 122:93] - node _T_530 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 269:161] - node _T_531 = mux(_T_499, _T_529, _T_530) @[axi4_to_ahb.scala 269:21] - buf_size_in <= _T_531 @[axi4_to_ahb.scala 269:15] - node _T_532 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 270:32] - node _T_533 = eq(_T_532, UInt<1>("h00")) @[axi4_to_ahb.scala 270:39] - node _T_534 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 271:17] - node _T_535 = eq(_T_534, UInt<1>("h00")) @[axi4_to_ahb.scala 271:24] - node _T_536 = or(_T_533, _T_535) @[axi4_to_ahb.scala 270:48] - node _T_537 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 271:47] - node _T_538 = eq(_T_537, UInt<2>("h01")) @[axi4_to_ahb.scala 271:54] - node _T_539 = or(_T_536, _T_538) @[axi4_to_ahb.scala 271:33] - node _T_540 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 271:86] - node _T_541 = eq(_T_540, UInt<2>("h02")) @[axi4_to_ahb.scala 271:93] - node _T_542 = or(_T_539, _T_541) @[axi4_to_ahb.scala 271:72] - node _T_543 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 272:18] - node _T_544 = eq(_T_543, UInt<2>("h03")) @[axi4_to_ahb.scala 272:25] - node _T_545 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:55] - node _T_546 = eq(_T_545, UInt<2>("h03")) @[axi4_to_ahb.scala 272:62] - node _T_547 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:90] - node _T_548 = eq(_T_547, UInt<4>("h0c")) @[axi4_to_ahb.scala 272:97] - node _T_549 = or(_T_546, _T_548) @[axi4_to_ahb.scala 272:74] - node _T_550 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:125] - node _T_551 = eq(_T_550, UInt<6>("h030")) @[axi4_to_ahb.scala 272:132] - node _T_552 = or(_T_549, _T_551) @[axi4_to_ahb.scala 272:109] - node _T_553 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:161] - node _T_554 = eq(_T_553, UInt<8>("h0c0")) @[axi4_to_ahb.scala 272:168] - node _T_555 = or(_T_552, _T_554) @[axi4_to_ahb.scala 272:145] - node _T_556 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 273:21] - node _T_557 = eq(_T_556, UInt<4>("h0f")) @[axi4_to_ahb.scala 273:28] - node _T_558 = or(_T_555, _T_557) @[axi4_to_ahb.scala 272:181] - node _T_559 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 273:56] - node _T_560 = eq(_T_559, UInt<8>("h0f0")) @[axi4_to_ahb.scala 273:63] - node _T_561 = or(_T_558, _T_560) @[axi4_to_ahb.scala 273:40] - node _T_562 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 273:92] - node _T_563 = eq(_T_562, UInt<8>("h0ff")) @[axi4_to_ahb.scala 273:99] - node _T_564 = or(_T_561, _T_563) @[axi4_to_ahb.scala 273:76] - node _T_565 = and(_T_544, _T_564) @[axi4_to_ahb.scala 272:38] - node _T_566 = or(_T_542, _T_565) @[axi4_to_ahb.scala 271:106] - buf_aligned_in <= _T_566 @[axi4_to_ahb.scala 270:18] - node _T_567 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 275:43] - node _T_568 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 275:62] - node _T_569 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 275:87] - node _T_570 = cat(_T_568, _T_569) @[Cat.scala 29:58] - node _T_571 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 275:108] - node _T_572 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 275:133] - node _T_573 = cat(_T_571, _T_572) @[Cat.scala 29:58] - node _T_574 = mux(_T_567, _T_570, _T_573) @[axi4_to_ahb.scala 275:26] - io.ahb.out.haddr <= _T_574 @[axi4_to_ahb.scala 275:20] - node _T_575 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 276:43] - node _T_576 = bits(buf_aligned_in, 0, 0) @[Bitwise.scala 72:15] - node _T_577 = mux(_T_576, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_578 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 276:94] - node _T_579 = and(_T_577, _T_578) @[axi4_to_ahb.scala 276:81] - node _T_580 = cat(UInt<1>("h00"), _T_579) @[Cat.scala 29:58] - node _T_581 = bits(buf_aligned, 0, 0) @[Bitwise.scala 72:15] - node _T_582 = mux(_T_581, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_583 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 276:148] - node _T_584 = and(_T_582, _T_583) @[axi4_to_ahb.scala 276:138] - node _T_585 = cat(UInt<1>("h00"), _T_584) @[Cat.scala 29:58] - node _T_586 = mux(_T_575, _T_580, _T_585) @[axi4_to_ahb.scala 276:26] - io.ahb.out.hsize <= _T_586 @[axi4_to_ahb.scala 276:20] - io.ahb.out.hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 278:21] - io.ahb.out.hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 279:24] - node _T_587 = bits(io.axi.ar.bits.prot, 2, 2) @[axi4_to_ahb.scala 280:57] - node _T_588 = eq(_T_587, UInt<1>("h00")) @[axi4_to_ahb.scala 280:37] - node _T_589 = cat(UInt<1>("h01"), _T_588) @[Cat.scala 29:58] - io.ahb.out.hprot <= _T_589 @[axi4_to_ahb.scala 280:20] - node _T_590 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 281:44] - node _T_591 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 281:59] - node _T_592 = eq(_T_591, UInt<1>("h01")) @[axi4_to_ahb.scala 281:66] - node _T_593 = mux(_T_590, _T_592, buf_write) @[axi4_to_ahb.scala 281:27] - io.ahb.out.hwrite <= _T_593 @[axi4_to_ahb.scala 281:21] - node _T_594 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 282:32] - io.ahb.out.hwdata <= _T_594 @[axi4_to_ahb.scala 282:21] - slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 284:15] - node _T_595 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 285:43] - node _T_596 = mux(_T_595, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 285:23] - node _T_597 = bits(slvbuf_error, 0, 0) @[Bitwise.scala 72:15] - node _T_598 = mux(_T_597, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_599 = and(_T_598, UInt<2>("h02")) @[axi4_to_ahb.scala 285:88] - node _T_600 = cat(_T_596, _T_599) @[Cat.scala 29:58] - slave_opc <= _T_600 @[axi4_to_ahb.scala 285:13] - node _T_601 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 286:41] - node _T_602 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 286:66] - node _T_603 = cat(_T_602, _T_602) @[Cat.scala 29:58] - node _T_604 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 286:91] - node _T_605 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 286:110] - node _T_606 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 286:131] - node _T_607 = mux(_T_604, _T_605, _T_606) @[axi4_to_ahb.scala 286:79] - node _T_608 = mux(_T_601, _T_603, _T_607) @[axi4_to_ahb.scala 286:21] - slave_rdata <= _T_608 @[axi4_to_ahb.scala 286:15] - node _T_609 = bits(slvbuf_tag, 2, 0) @[axi4_to_ahb.scala 287:26] - slave_tag <= _T_609 @[axi4_to_ahb.scala 287:13] - node _T_610 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 289:37] - node _T_611 = neq(_T_610, UInt<1>("h00")) @[axi4_to_ahb.scala 289:44] - node _T_612 = and(_T_611, io.ahb.in.hready) @[axi4_to_ahb.scala 289:56] - node _T_613 = and(_T_612, io.ahb.out.hwrite) @[axi4_to_ahb.scala 289:75] - last_addr_en <= _T_613 @[axi4_to_ahb.scala 289:16] - node _T_614 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 291:31] - node _T_615 = and(_T_614, master_ready) @[axi4_to_ahb.scala 291:49] - wrbuf_en <= _T_615 @[axi4_to_ahb.scala 291:12] - node _T_616 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 292:35] - node _T_617 = and(_T_616, master_ready) @[axi4_to_ahb.scala 292:52] - wrbuf_data_en <= _T_617 @[axi4_to_ahb.scala 292:17] - node _T_618 = and(master_valid, master_ready) @[axi4_to_ahb.scala 293:34] - node _T_619 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 293:62] - node _T_620 = eq(_T_619, UInt<1>("h01")) @[axi4_to_ahb.scala 293:69] - node _T_621 = and(_T_618, _T_620) @[axi4_to_ahb.scala 293:49] - wrbuf_cmd_sent <= _T_621 @[axi4_to_ahb.scala 293:18] - node _T_622 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 294:33] - node _T_623 = and(wrbuf_cmd_sent, _T_622) @[axi4_to_ahb.scala 294:31] - wrbuf_rst <= _T_623 @[axi4_to_ahb.scala 294:13] - node _T_624 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 296:36] - node _T_625 = and(wrbuf_vld, _T_624) @[axi4_to_ahb.scala 296:34] - node _T_626 = eq(_T_625, UInt<1>("h00")) @[axi4_to_ahb.scala 296:22] - node _T_627 = and(_T_626, master_ready) @[axi4_to_ahb.scala 296:53] - io.axi.aw.ready <= _T_627 @[axi4_to_ahb.scala 296:19] - node _T_628 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 297:40] - node _T_629 = and(wrbuf_data_vld, _T_628) @[axi4_to_ahb.scala 297:38] - node _T_630 = eq(_T_629, UInt<1>("h00")) @[axi4_to_ahb.scala 297:21] - node _T_631 = and(_T_630, master_ready) @[axi4_to_ahb.scala 297:57] - io.axi.w.ready <= _T_631 @[axi4_to_ahb.scala 297:18] - node _T_632 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 298:34] - node _T_633 = eq(_T_632, UInt<1>("h00")) @[axi4_to_ahb.scala 298:22] - node _T_634 = and(_T_633, master_ready) @[axi4_to_ahb.scala 298:52] - io.axi.ar.ready <= _T_634 @[axi4_to_ahb.scala 298:19] - io.axi.r.bits.last <= UInt<1>("h01") @[axi4_to_ahb.scala 299:22] - node _T_635 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 301:71] - node _T_636 = mux(_T_635, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 301:55] - node _T_637 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 301:91] - node _T_638 = and(_T_636, _T_637) @[axi4_to_ahb.scala 301:89] - reg _T_639 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 301:51] - _T_639 <= _T_638 @[axi4_to_ahb.scala 301:51] - wrbuf_vld <= _T_639 @[axi4_to_ahb.scala 301:21] - node _T_640 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 302:76] - node _T_641 = mux(_T_640, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 302:55] - node _T_642 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 302:102] - node _T_643 = and(_T_641, _T_642) @[axi4_to_ahb.scala 302:100] - reg _T_644 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 302:51] - _T_644 <= _T_643 @[axi4_to_ahb.scala 302:51] - wrbuf_data_vld <= _T_644 @[axi4_to_ahb.scala 302:21] - node _T_645 = bits(io.axi.aw.bits.id, 2, 0) @[axi4_to_ahb.scala 303:71] - node _T_646 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 303:105] - reg _T_647 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_646 : @[Reg.scala 28:19] - _T_647 <= _T_645 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - wrbuf_tag <= _T_647 @[axi4_to_ahb.scala 303:21] - node _T_648 = bits(io.axi.aw.bits.size, 2, 0) @[axi4_to_ahb.scala 304:73] - node _T_649 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 304:101] - reg _T_650 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_649 : @[Reg.scala 28:19] - _T_650 <= _T_648 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - wrbuf_size <= _T_650 @[axi4_to_ahb.scala 304:21] - node _T_651 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 305:61] - inst rvclkhdr_2 of rvclkhdr_861 @[lib.scala 368:23] - rvclkhdr_2.clock <= clock - rvclkhdr_2.reset <= reset - rvclkhdr_2.io.clk <= bus_clk @[lib.scala 370:18] - rvclkhdr_2.io.en <= _T_651 @[lib.scala 371:17] - rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_652 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_652 <= io.axi.aw.bits.addr @[lib.scala 374:16] - wrbuf_addr <= _T_652 @[axi4_to_ahb.scala 305:21] - node _T_653 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 306:65] - inst rvclkhdr_3 of rvclkhdr_862 @[lib.scala 368:23] - rvclkhdr_3.clock <= clock - rvclkhdr_3.reset <= reset - rvclkhdr_3.io.clk <= bus_clk @[lib.scala 370:18] - rvclkhdr_3.io.en <= _T_653 @[lib.scala 371:17] - rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_654 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_654 <= io.axi.w.bits.data @[lib.scala 374:16] - wrbuf_data <= _T_654 @[axi4_to_ahb.scala 306:21] - node _T_655 = bits(io.axi.w.bits.strb, 7, 0) @[axi4_to_ahb.scala 307:72] - node _T_656 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 307:105] - reg _T_657 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_656 : @[Reg.scala 28:19] - _T_657 <= _T_655 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - wrbuf_byteen <= _T_657 @[axi4_to_ahb.scala 307:21] - node _T_658 = bits(io.ahb.out.haddr, 31, 0) @[axi4_to_ahb.scala 308:71] - node _T_659 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 308:104] - reg _T_660 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_659 : @[Reg.scala 28:19] - _T_660 <= _T_658 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - last_bus_addr <= _T_660 @[axi4_to_ahb.scala 308:21] - node _T_661 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 309:89] - reg _T_662 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_661 : @[Reg.scala 28:19] - _T_662 <= buf_write_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_write <= _T_662 @[axi4_to_ahb.scala 309:21] - node _T_663 = bits(buf_tag_in, 2, 0) @[axi4_to_ahb.scala 310:64] - node _T_664 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 310:99] - reg _T_665 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_664 : @[Reg.scala 28:19] - _T_665 <= _T_663 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_tag <= _T_665 @[axi4_to_ahb.scala 310:21] - node _T_666 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 311:42] - node _T_667 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 311:61] - node _T_668 = bits(_T_667, 0, 0) @[axi4_to_ahb.scala 311:78] - inst rvclkhdr_4 of rvclkhdr_863 @[lib.scala 368:23] - rvclkhdr_4.clock <= clock - rvclkhdr_4.reset <= reset - rvclkhdr_4.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_4.io.en <= _T_668 @[lib.scala 371:17] - rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_669 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_669 <= _T_666 @[lib.scala 374:16] - buf_addr <= _T_669 @[axi4_to_ahb.scala 311:21] - node _T_670 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 312:65] - node _T_671 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 312:94] - reg _T_672 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_671 : @[Reg.scala 28:19] - _T_672 <= _T_670 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_size <= _T_672 @[axi4_to_ahb.scala 312:21] - node _T_673 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 313:91] - reg _T_674 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_673 : @[Reg.scala 28:19] - _T_674 <= buf_aligned_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_aligned <= _T_674 @[axi4_to_ahb.scala 313:21] - node _T_675 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 314:67] - node _T_676 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 314:96] - reg _T_677 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_676 : @[Reg.scala 28:19] - _T_677 <= _T_675 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_byteen <= _T_677 @[axi4_to_ahb.scala 314:21] - node _T_678 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 315:42] - node _T_679 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 315:66] - node _T_680 = bits(_T_679, 0, 0) @[axi4_to_ahb.scala 315:89] - inst rvclkhdr_5 of rvclkhdr_864 @[lib.scala 368:23] - rvclkhdr_5.clock <= clock - rvclkhdr_5.reset <= reset - rvclkhdr_5.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_5.io.en <= _T_680 @[lib.scala 371:17] - rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_681 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_681 <= _T_678 @[lib.scala 374:16] - buf_data <= _T_681 @[axi4_to_ahb.scala 315:21] - node _T_682 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 316:89] - reg _T_683 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_682 : @[Reg.scala 28:19] - _T_683 <= buf_write @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - slvbuf_write <= _T_683 @[axi4_to_ahb.scala 316:21] - node _T_684 = bits(buf_tag, 2, 0) @[axi4_to_ahb.scala 317:61] - node _T_685 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 317:99] - reg _T_686 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_685 : @[Reg.scala 28:19] - _T_686 <= _T_684 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - slvbuf_tag <= _T_686 @[axi4_to_ahb.scala 317:21] - node _T_687 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 318:99] - reg _T_688 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_687 : @[Reg.scala 28:19] - _T_688 <= slvbuf_error_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - slvbuf_error <= _T_688 @[axi4_to_ahb.scala 318:21] - node _T_689 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 319:72] - node _T_690 = mux(_T_689, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 319:56] - node _T_691 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 319:92] - node _T_692 = and(_T_690, _T_691) @[axi4_to_ahb.scala 319:90] - reg _T_693 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 319:52] - _T_693 <= _T_692 @[axi4_to_ahb.scala 319:52] - cmd_doneQ <= _T_693 @[axi4_to_ahb.scala 319:21] - node _T_694 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 320:71] - node _T_695 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 320:110] - reg _T_696 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_695 : @[Reg.scala 28:19] - _T_696 <= _T_694 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_cmd_byte_ptrQ <= _T_696 @[axi4_to_ahb.scala 320:21] - reg _T_697 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 321:52] - _T_697 <= io.ahb.in.hready @[axi4_to_ahb.scala 321:52] - ahb_hready_q <= _T_697 @[axi4_to_ahb.scala 321:21] - node _T_698 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 322:70] - reg _T_699 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 322:52] - _T_699 <= _T_698 @[axi4_to_ahb.scala 322:52] - ahb_htrans_q <= _T_699 @[axi4_to_ahb.scala 322:21] - reg _T_700 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 323:57] - _T_700 <= io.ahb.out.hwrite @[axi4_to_ahb.scala 323:57] - ahb_hwrite_q <= _T_700 @[axi4_to_ahb.scala 323:21] - reg _T_701 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 324:52] - _T_701 <= io.ahb.in.hresp @[axi4_to_ahb.scala 324:52] - ahb_hresp_q <= _T_701 @[axi4_to_ahb.scala 324:21] - node _T_702 = bits(io.ahb.in.hrdata, 63, 0) @[axi4_to_ahb.scala 325:74] - reg _T_703 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 325:57] - _T_703 <= _T_702 @[axi4_to_ahb.scala 325:57] - ahb_hrdata_q <= _T_703 @[axi4_to_ahb.scala 325:21] - node _T_704 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 327:43] - node _T_705 = or(_T_704, io.clk_override) @[axi4_to_ahb.scala 327:58] - node _T_706 = and(io.bus_clk_en, _T_705) @[axi4_to_ahb.scala 327:30] - buf_clken <= _T_706 @[axi4_to_ahb.scala 327:13] - node _T_707 = bits(io.ahb.out.htrans, 1, 1) @[axi4_to_ahb.scala 328:76] - node _T_708 = and(io.ahb.in.hready, _T_707) @[axi4_to_ahb.scala 328:57] - node _T_709 = or(_T_708, io.clk_override) @[axi4_to_ahb.scala 328:81] - node _T_710 = and(io.bus_clk_en, _T_709) @[axi4_to_ahb.scala 328:36] - ahbm_addr_clken <= _T_710 @[axi4_to_ahb.scala 328:19] - node _T_711 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 329:50] - node _T_712 = or(_T_711, io.clk_override) @[axi4_to_ahb.scala 329:60] - node _T_713 = and(io.bus_clk_en, _T_712) @[axi4_to_ahb.scala 329:36] - ahbm_data_clken <= _T_713 @[axi4_to_ahb.scala 329:19] - inst rvclkhdr_6 of rvclkhdr_865 @[lib.scala 343:22] - rvclkhdr_6.clock <= clock - rvclkhdr_6.reset <= reset - rvclkhdr_6.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_6.io.en <= buf_clken @[lib.scala 345:16] - rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - buf_clk <= rvclkhdr_6.io.l1clk @[axi4_to_ahb.scala 332:12] - inst rvclkhdr_7 of rvclkhdr_866 @[lib.scala 343:22] - rvclkhdr_7.clock <= clock - rvclkhdr_7.reset <= reset - rvclkhdr_7.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_7.io.en <= io.bus_clk_en @[lib.scala 345:16] - rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahbm_clk <= rvclkhdr_7.io.l1clk @[axi4_to_ahb.scala 333:12] - inst rvclkhdr_8 of rvclkhdr_867 @[lib.scala 343:22] - rvclkhdr_8.clock <= clock - rvclkhdr_8.reset <= reset - rvclkhdr_8.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_8.io.en <= ahbm_addr_clken @[lib.scala 345:16] - rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahbm_addr_clk <= rvclkhdr_8.io.l1clk @[axi4_to_ahb.scala 334:17] - inst rvclkhdr_9 of rvclkhdr_868 @[lib.scala 343:22] - rvclkhdr_9.clock <= clock - rvclkhdr_9.reset <= reset - rvclkhdr_9.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_9.io.en <= ahbm_data_clken @[lib.scala 345:16] - rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahbm_data_clk <= rvclkhdr_9.io.l1clk @[axi4_to_ahb.scala 335:17] - - extmodule gated_latch_869 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_869 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_869 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_870 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_870 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_870 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_871 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_871 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_871 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_872 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_872 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_872 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_873 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_873 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_873 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_874 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_874 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_874 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_875 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_875 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_875 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_876 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_876 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_876 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_877 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_877 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_877 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_878 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_878 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_878 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - module axi4_to_ahb_2 : - input clock : Clock - input reset : AsyncReset - output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ahb : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}} - - wire buf_rst : UInt<1> - buf_rst <= UInt<1>("h00") - buf_rst <= UInt<1>("h00") @[axi4_to_ahb.scala 21:11] - io.ahb.out.htrans <= UInt<1>("h00") @[axi4_to_ahb.scala 22:21] - wire buf_state_en : UInt<1> - buf_state_en <= UInt<1>("h00") - wire ahbm_clk : Clock @[axi4_to_ahb.scala 24:22] - wire ahbm_addr_clk : Clock @[axi4_to_ahb.scala 25:27] - wire ahbm_data_clk : Clock @[axi4_to_ahb.scala 26:27] - wire buf_state : UInt<3> - buf_state <= UInt<3>("h00") - wire buf_nxtstate : UInt<3> - buf_nxtstate <= UInt<3>("h00") - node _T = bits(buf_state_en, 0, 0) @[axi4_to_ahb.scala 30:70] - node _T_1 = mux(_T, buf_nxtstate, buf_state) @[axi4_to_ahb.scala 30:50] - node _T_2 = eq(buf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 30:108] - node _T_3 = bits(_T_2, 0, 0) @[Bitwise.scala 72:15] - node _T_4 = mux(_T_3, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_5 = and(_T_1, _T_4) @[axi4_to_ahb.scala 30:98] - reg _T_6 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 30:45] - _T_6 <= _T_5 @[axi4_to_ahb.scala 30:45] - buf_state <= _T_6 @[axi4_to_ahb.scala 30:13] - wire slave_valid : UInt<1> - slave_valid <= UInt<1>("h00") - wire slave_ready : UInt<1> - slave_ready <= UInt<1>("h00") - wire slave_tag : UInt<3> - slave_tag <= UInt<3>("h00") - wire slave_rdata : UInt<64> - slave_rdata <= UInt<64>("h00") - wire slave_opc : UInt<4> - slave_opc <= UInt<4>("h00") - wire wrbuf_en : UInt<1> - wrbuf_en <= UInt<1>("h00") - wire wrbuf_data_en : UInt<1> - wrbuf_data_en <= UInt<1>("h00") - wire wrbuf_cmd_sent : UInt<1> - wrbuf_cmd_sent <= UInt<1>("h00") - wire wrbuf_rst : UInt<1> - wrbuf_rst <= UInt<1>("h00") - wire wrbuf_vld : UInt<1> - wrbuf_vld <= UInt<1>("h00") - wire wrbuf_data_vld : UInt<1> - wrbuf_data_vld <= UInt<1>("h00") - wire wrbuf_tag : UInt<3> - wrbuf_tag <= UInt<3>("h00") - wire wrbuf_size : UInt<3> - wrbuf_size <= UInt<3>("h00") - wire wrbuf_addr : UInt<32> - wrbuf_addr <= UInt<32>("h00") - wire wrbuf_data : UInt<64> - wrbuf_data <= UInt<64>("h00") - wire wrbuf_byteen : UInt<8> - wrbuf_byteen <= UInt<8>("h00") - wire bus_write_clk_en : UInt<1> - bus_write_clk_en <= UInt<1>("h00") - wire bus_clk : Clock @[axi4_to_ahb.scala 50:21] - wire bus_write_clk : Clock @[axi4_to_ahb.scala 51:27] - wire master_valid : UInt<1> - master_valid <= UInt<1>("h00") - wire master_ready : UInt<1> - master_ready <= UInt<1>("h00") - wire master_tag : UInt<3> - master_tag <= UInt<3>("h00") - wire master_addr : UInt<32> - master_addr <= UInt<32>("h00") - wire master_wdata : UInt<64> - master_wdata <= UInt<64>("h00") - wire master_size : UInt<3> - master_size <= UInt<3>("h00") - wire master_opc : UInt<3> - master_opc <= UInt<3>("h00") - wire master_byteen : UInt<8> - master_byteen <= UInt<8>("h00") - wire buf_addr : UInt<32> - buf_addr <= UInt<32>("h00") - wire buf_size : UInt<2> - buf_size <= UInt<2>("h00") - wire buf_write : UInt<1> - buf_write <= UInt<1>("h00") - wire buf_byteen : UInt<8> - buf_byteen <= UInt<8>("h00") - wire buf_aligned : UInt<1> - buf_aligned <= UInt<1>("h00") - wire buf_data : UInt<64> - buf_data <= UInt<64>("h00") - wire buf_tag : UInt<3> - buf_tag <= UInt<3>("h00") - wire buf_tag_in : UInt<3> - buf_tag_in <= UInt<3>("h00") - wire buf_addr_in : UInt<32> - buf_addr_in <= UInt<32>("h00") - wire buf_byteen_in : UInt<8> - buf_byteen_in <= UInt<8>("h00") - wire buf_data_in : UInt<64> - buf_data_in <= UInt<64>("h00") - wire buf_write_in : UInt<1> - buf_write_in <= UInt<1>("h00") - wire buf_aligned_in : UInt<1> - buf_aligned_in <= UInt<1>("h00") - wire buf_size_in : UInt<3> - buf_size_in <= UInt<3>("h00") - wire buf_wr_en : UInt<1> - buf_wr_en <= UInt<1>("h00") - wire buf_data_wr_en : UInt<1> - buf_data_wr_en <= UInt<1>("h00") - wire slvbuf_error_en : UInt<1> - slvbuf_error_en <= UInt<1>("h00") - wire wr_cmd_vld : UInt<1> - wr_cmd_vld <= UInt<1>("h00") - wire cmd_done_rst : UInt<1> - cmd_done_rst <= UInt<1>("h00") - wire cmd_done : UInt<1> - cmd_done <= UInt<1>("h00") - wire cmd_doneQ : UInt<1> - cmd_doneQ <= UInt<1>("h00") - wire trxn_done : UInt<1> - trxn_done <= UInt<1>("h00") - wire buf_cmd_byte_ptr : UInt<3> - buf_cmd_byte_ptr <= UInt<3>("h00") - wire buf_cmd_byte_ptrQ : UInt<3> - buf_cmd_byte_ptrQ <= UInt<3>("h00") - wire buf_cmd_nxtbyte_ptr : UInt<3> - buf_cmd_nxtbyte_ptr <= UInt<3>("h00") - wire buf_cmd_byte_ptr_en : UInt<1> - buf_cmd_byte_ptr_en <= UInt<1>("h00") - wire found : UInt<1> - found <= UInt<1>("h00") - wire slave_valid_pre : UInt<1> - slave_valid_pre <= UInt<1>("h00") - wire ahb_hready_q : UInt<1> - ahb_hready_q <= UInt<1>("h00") - wire ahb_hresp_q : UInt<1> - ahb_hresp_q <= UInt<1>("h00") - wire ahb_htrans_q : UInt<2> - ahb_htrans_q <= UInt<2>("h00") - wire ahb_hwrite_q : UInt<1> - ahb_hwrite_q <= UInt<1>("h00") - wire ahb_hrdata_q : UInt<64> - ahb_hrdata_q <= UInt<64>("h00") - wire slvbuf_write : UInt<1> - slvbuf_write <= UInt<1>("h00") - wire slvbuf_error : UInt<1> - slvbuf_error <= UInt<1>("h00") - wire slvbuf_tag : UInt<3> - slvbuf_tag <= UInt<3>("h00") - wire slvbuf_error_in : UInt<1> - slvbuf_error_in <= UInt<1>("h00") - wire slvbuf_wr_en : UInt<1> - slvbuf_wr_en <= UInt<1>("h00") - wire bypass_en : UInt<1> - bypass_en <= UInt<1>("h00") - wire rd_bypass_idle : UInt<1> - rd_bypass_idle <= UInt<1>("h00") - wire last_addr_en : UInt<1> - last_addr_en <= UInt<1>("h00") - wire last_bus_addr : UInt<32> - last_bus_addr <= UInt<32>("h00") - wire buf_clken : UInt<1> - buf_clken <= UInt<1>("h00") - wire slvbuf_clken : UInt<1> - slvbuf_clken <= UInt<1>("h00") - wire ahbm_addr_clken : UInt<1> - ahbm_addr_clken <= UInt<1>("h00") - wire ahbm_data_clken : UInt<1> - ahbm_data_clken <= UInt<1>("h00") - wire buf_clk : Clock @[axi4_to_ahb.scala 118:21] - node _T_7 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 139:27] - wr_cmd_vld <= _T_7 @[axi4_to_ahb.scala 139:14] - node _T_8 = or(wr_cmd_vld, io.axi.ar.valid) @[axi4_to_ahb.scala 140:30] - master_valid <= _T_8 @[axi4_to_ahb.scala 140:16] - node _T_9 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 141:38] - node _T_10 = bits(wrbuf_tag, 2, 0) @[axi4_to_ahb.scala 141:51] - node _T_11 = bits(io.axi.ar.bits.id, 2, 0) @[axi4_to_ahb.scala 141:82] - node _T_12 = mux(_T_9, _T_10, _T_11) @[axi4_to_ahb.scala 141:20] - master_tag <= _T_12 @[axi4_to_ahb.scala 141:14] - node _T_13 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 142:38] - node _T_14 = mux(_T_13, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 142:20] - master_opc <= _T_14 @[axi4_to_ahb.scala 142:14] - node _T_15 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 143:39] - node _T_16 = bits(wrbuf_addr, 31, 0) @[axi4_to_ahb.scala 143:53] - node _T_17 = bits(io.axi.ar.bits.addr, 31, 0) @[axi4_to_ahb.scala 143:81] - node _T_18 = mux(_T_15, _T_16, _T_17) @[axi4_to_ahb.scala 143:21] - master_addr <= _T_18 @[axi4_to_ahb.scala 143:15] - node _T_19 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 144:39] - node _T_20 = bits(wrbuf_size, 2, 0) @[axi4_to_ahb.scala 144:53] - node _T_21 = bits(io.axi.ar.bits.size, 2, 0) @[axi4_to_ahb.scala 144:80] - node _T_22 = mux(_T_19, _T_20, _T_21) @[axi4_to_ahb.scala 144:21] - master_size <= _T_22 @[axi4_to_ahb.scala 144:15] - node _T_23 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 145:32] - master_byteen <= _T_23 @[axi4_to_ahb.scala 145:17] - node _T_24 = bits(wrbuf_data, 63, 0) @[axi4_to_ahb.scala 146:29] - master_wdata <= _T_24 @[axi4_to_ahb.scala 146:16] - node _T_25 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 149:33] - node _T_26 = bits(slave_opc, 3, 3) @[axi4_to_ahb.scala 149:58] - node _T_27 = and(_T_25, _T_26) @[axi4_to_ahb.scala 149:47] - io.axi.b.valid <= _T_27 @[axi4_to_ahb.scala 149:18] - node _T_28 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 150:38] - node _T_29 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 150:65] - node _T_30 = mux(_T_29, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 150:55] - node _T_31 = mux(_T_28, UInt<2>("h02"), _T_30) @[axi4_to_ahb.scala 150:28] - io.axi.b.bits.resp <= _T_31 @[axi4_to_ahb.scala 150:22] - node _T_32 = bits(slave_tag, 2, 0) @[axi4_to_ahb.scala 151:32] - io.axi.b.bits.id <= _T_32 @[axi4_to_ahb.scala 151:20] - node _T_33 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 153:33] - node _T_34 = bits(slave_opc, 3, 2) @[axi4_to_ahb.scala 153:59] - node _T_35 = eq(_T_34, UInt<1>("h00")) @[axi4_to_ahb.scala 153:66] - node _T_36 = and(_T_33, _T_35) @[axi4_to_ahb.scala 153:47] - io.axi.r.valid <= _T_36 @[axi4_to_ahb.scala 153:18] - node _T_37 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 154:38] - node _T_38 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 154:65] - node _T_39 = mux(_T_38, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 154:55] - node _T_40 = mux(_T_37, UInt<2>("h02"), _T_39) @[axi4_to_ahb.scala 154:28] - io.axi.r.bits.resp <= _T_40 @[axi4_to_ahb.scala 154:22] - node _T_41 = bits(slave_tag, 2, 0) @[axi4_to_ahb.scala 155:32] - io.axi.r.bits.id <= _T_41 @[axi4_to_ahb.scala 155:20] - node _T_42 = bits(slave_rdata, 63, 0) @[axi4_to_ahb.scala 156:36] - io.axi.r.bits.data <= _T_42 @[axi4_to_ahb.scala 156:22] - node _T_43 = and(io.axi.b.ready, io.axi.r.ready) @[axi4_to_ahb.scala 157:33] - slave_ready <= _T_43 @[axi4_to_ahb.scala 157:15] - node _T_44 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 160:57] - node _T_45 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 160:94] - node _T_46 = or(_T_44, _T_45) @[axi4_to_ahb.scala 160:76] - node _T_47 = and(io.bus_clk_en, _T_46) @[axi4_to_ahb.scala 160:37] - bus_write_clk_en <= _T_47 @[axi4_to_ahb.scala 160:20] - inst rvclkhdr of rvclkhdr_869 @[lib.scala 343:22] - rvclkhdr.clock <= clock - rvclkhdr.reset <= reset - rvclkhdr.io.clk <= clock @[lib.scala 344:17] - rvclkhdr.io.en <= io.bus_clk_en @[lib.scala 345:16] - rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - bus_clk <= rvclkhdr.io.l1clk @[axi4_to_ahb.scala 162:11] - node _T_48 = bits(bus_write_clk_en, 0, 0) @[axi4_to_ahb.scala 163:59] - inst rvclkhdr_1 of rvclkhdr_870 @[lib.scala 343:22] - rvclkhdr_1.clock <= clock - rvclkhdr_1.reset <= reset - rvclkhdr_1.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_1.io.en <= _T_48 @[lib.scala 345:16] - rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - bus_write_clk <= rvclkhdr_1.io.l1clk @[axi4_to_ahb.scala 163:17] - node _T_49 = eq(UInt<3>("h00"), buf_state) @[Conditional.scala 37:30] - when _T_49 : @[Conditional.scala 40:58] - master_ready <= UInt<1>("h01") @[axi4_to_ahb.scala 167:20] - node _T_50 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 168:34] - node _T_51 = eq(_T_50, UInt<1>("h01")) @[axi4_to_ahb.scala 168:41] - buf_write_in <= _T_51 @[axi4_to_ahb.scala 168:20] - node _T_52 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 169:46] - node _T_53 = mux(_T_52, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 169:26] - buf_nxtstate <= _T_53 @[axi4_to_ahb.scala 169:20] - node _T_54 = and(master_valid, UInt<1>("h01")) @[axi4_to_ahb.scala 170:36] - buf_state_en <= _T_54 @[axi4_to_ahb.scala 170:20] - buf_wr_en <= buf_state_en @[axi4_to_ahb.scala 171:17] - node _T_55 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 172:54] - node _T_56 = and(buf_state_en, _T_55) @[axi4_to_ahb.scala 172:38] - buf_data_wr_en <= _T_56 @[axi4_to_ahb.scala 172:22] - buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 173:27] - node _T_57 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 175:50] - node _T_58 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 175:94] - node _T_59 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_60 = tail(_T_59, 1) @[axi4_to_ahb.scala 135:52] - node _T_61 = mux(UInt<1>("h00"), _T_60, UInt<3>("h00")) @[axi4_to_ahb.scala 135:24] - node _T_62 = bits(_T_58, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_63 = geq(UInt<1>("h00"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_64 = and(_T_62, _T_63) @[axi4_to_ahb.scala 136:48] - node _T_65 = bits(_T_58, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_66 = geq(UInt<1>("h01"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_67 = and(_T_65, _T_66) @[axi4_to_ahb.scala 136:48] - node _T_68 = bits(_T_58, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_69 = geq(UInt<2>("h02"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_70 = and(_T_68, _T_69) @[axi4_to_ahb.scala 136:48] - node _T_71 = bits(_T_58, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_72 = geq(UInt<2>("h03"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_73 = and(_T_71, _T_72) @[axi4_to_ahb.scala 136:48] - node _T_74 = bits(_T_58, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_75 = geq(UInt<3>("h04"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_76 = and(_T_74, _T_75) @[axi4_to_ahb.scala 136:48] - node _T_77 = bits(_T_58, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_78 = geq(UInt<3>("h05"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_79 = and(_T_77, _T_78) @[axi4_to_ahb.scala 136:48] - node _T_80 = bits(_T_58, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_81 = geq(UInt<3>("h06"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_82 = and(_T_80, _T_81) @[axi4_to_ahb.scala 136:48] - node _T_83 = bits(_T_58, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_84 = geq(UInt<3>("h07"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_85 = and(_T_83, _T_84) @[axi4_to_ahb.scala 136:48] - node _T_86 = mux(_T_85, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_87 = mux(_T_82, UInt<3>("h06"), _T_86) @[Mux.scala 98:16] - node _T_88 = mux(_T_79, UInt<3>("h05"), _T_87) @[Mux.scala 98:16] - node _T_89 = mux(_T_76, UInt<3>("h04"), _T_88) @[Mux.scala 98:16] - node _T_90 = mux(_T_73, UInt<2>("h03"), _T_89) @[Mux.scala 98:16] - node _T_91 = mux(_T_70, UInt<2>("h02"), _T_90) @[Mux.scala 98:16] - node _T_92 = mux(_T_67, UInt<1>("h01"), _T_91) @[Mux.scala 98:16] - node _T_93 = mux(_T_64, UInt<1>("h00"), _T_92) @[Mux.scala 98:16] - node _T_94 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 175:124] - node _T_95 = mux(_T_57, _T_93, _T_94) @[axi4_to_ahb.scala 175:30] - buf_cmd_byte_ptr <= _T_95 @[axi4_to_ahb.scala 175:24] - bypass_en <= buf_state_en @[axi4_to_ahb.scala 176:17] - node _T_96 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 177:51] - node _T_97 = and(bypass_en, _T_96) @[axi4_to_ahb.scala 177:35] - rd_bypass_idle <= _T_97 @[axi4_to_ahb.scala 177:22] - node _T_98 = bits(bypass_en, 0, 0) @[Bitwise.scala 72:15] - node _T_99 = mux(_T_98, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_100 = and(_T_99, UInt<2>("h02")) @[axi4_to_ahb.scala 178:49] - io.ahb.out.htrans <= _T_100 @[axi4_to_ahb.scala 178:25] - skip @[Conditional.scala 40:58] - else : @[Conditional.scala 39:67] - node _T_101 = eq(UInt<3>("h01"), buf_state) @[Conditional.scala 37:30] - when _T_101 : @[Conditional.scala 39:67] - node _T_102 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 182:54] - node _T_103 = eq(_T_102, UInt<1>("h00")) @[axi4_to_ahb.scala 182:61] - node _T_104 = and(master_valid, _T_103) @[axi4_to_ahb.scala 182:41] - node _T_105 = bits(_T_104, 0, 0) @[axi4_to_ahb.scala 182:82] - node _T_106 = mux(_T_105, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 182:26] - buf_nxtstate <= _T_106 @[axi4_to_ahb.scala 182:20] - node _T_107 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 183:51] - node _T_108 = neq(_T_107, UInt<1>("h00")) @[axi4_to_ahb.scala 183:58] - node _T_109 = and(ahb_hready_q, _T_108) @[axi4_to_ahb.scala 183:36] - node _T_110 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 183:72] - node _T_111 = and(_T_109, _T_110) @[axi4_to_ahb.scala 183:70] - buf_state_en <= _T_111 @[axi4_to_ahb.scala 183:20] - node _T_112 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 184:34] - node _T_113 = and(buf_state_en, _T_112) @[axi4_to_ahb.scala 184:32] - cmd_done <= _T_113 @[axi4_to_ahb.scala 184:16] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 185:20] - node _T_114 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 186:52] - node _T_115 = neq(_T_114, UInt<1>("h00")) @[axi4_to_ahb.scala 186:59] - node _T_116 = and(ahb_hready_q, _T_115) @[axi4_to_ahb.scala 186:37] - node _T_117 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 186:73] - node _T_118 = and(_T_116, _T_117) @[axi4_to_ahb.scala 186:71] - node _T_119 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 186:122] - node _T_120 = eq(_T_119, UInt<1>("h00")) @[axi4_to_ahb.scala 186:129] - node _T_121 = and(master_valid, _T_120) @[axi4_to_ahb.scala 186:109] - node _T_122 = bits(_T_121, 0, 0) @[axi4_to_ahb.scala 186:150] - node _T_123 = mux(_T_122, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 186:94] - node _T_124 = eq(_T_123, UInt<3>("h06")) @[axi4_to_ahb.scala 186:174] - node _T_125 = and(_T_118, _T_124) @[axi4_to_ahb.scala 186:88] - master_ready <= _T_125 @[axi4_to_ahb.scala 186:20] - buf_wr_en <= master_ready @[axi4_to_ahb.scala 187:17] - node _T_126 = and(master_ready, master_valid) @[axi4_to_ahb.scala 188:33] - bypass_en <= _T_126 @[axi4_to_ahb.scala 188:17] - node _T_127 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 189:47] - node _T_128 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 189:62] - node _T_129 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 189:78] - node _T_130 = mux(_T_127, _T_128, _T_129) @[axi4_to_ahb.scala 189:30] - buf_cmd_byte_ptr <= _T_130 @[axi4_to_ahb.scala 189:24] - node _T_131 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 190:48] - node _T_132 = or(_T_131, bypass_en) @[axi4_to_ahb.scala 190:62] - node _T_133 = bits(_T_132, 0, 0) @[Bitwise.scala 72:15] - node _T_134 = mux(_T_133, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_135 = and(UInt<2>("h02"), _T_134) @[axi4_to_ahb.scala 190:36] - io.ahb.out.htrans <= _T_135 @[axi4_to_ahb.scala 190:25] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_136 = eq(UInt<3>("h06"), buf_state) @[Conditional.scala 37:30] - when _T_136 : @[Conditional.scala 39:67] - node _T_137 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 194:39] - node _T_138 = and(ahb_hready_q, _T_137) @[axi4_to_ahb.scala 194:37] - node _T_139 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 194:82] - node _T_140 = eq(_T_139, UInt<1>("h01")) @[axi4_to_ahb.scala 194:89] - node _T_141 = and(master_valid, _T_140) @[axi4_to_ahb.scala 194:70] - node _T_142 = not(_T_141) @[axi4_to_ahb.scala 194:55] - node _T_143 = and(_T_138, _T_142) @[axi4_to_ahb.scala 194:53] - master_ready <= _T_143 @[axi4_to_ahb.scala 194:20] - node _T_144 = and(master_valid, master_ready) @[axi4_to_ahb.scala 195:34] - node _T_145 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 195:62] - node _T_146 = eq(_T_145, UInt<1>("h00")) @[axi4_to_ahb.scala 195:69] - node _T_147 = and(_T_144, _T_146) @[axi4_to_ahb.scala 195:49] - buf_wr_en <= _T_147 @[axi4_to_ahb.scala 195:17] - node _T_148 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 196:45] - node _T_149 = and(master_valid, master_ready) @[axi4_to_ahb.scala 196:82] - node _T_150 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 196:110] - node _T_151 = eq(_T_150, UInt<1>("h00")) @[axi4_to_ahb.scala 196:117] - node _T_152 = and(_T_149, _T_151) @[axi4_to_ahb.scala 196:97] - node _T_153 = bits(_T_152, 0, 0) @[axi4_to_ahb.scala 196:138] - node _T_154 = mux(_T_153, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 196:67] - node _T_155 = mux(_T_148, UInt<3>("h07"), _T_154) @[axi4_to_ahb.scala 196:26] - buf_nxtstate <= _T_155 @[axi4_to_ahb.scala 196:20] - node _T_156 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 197:37] - buf_state_en <= _T_156 @[axi4_to_ahb.scala 197:20] - buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 198:22] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 199:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 200:23] - node _T_157 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 201:41] - node _T_158 = and(buf_state_en, _T_157) @[axi4_to_ahb.scala 201:39] - slave_valid_pre <= _T_158 @[axi4_to_ahb.scala 201:23] - node _T_159 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 202:34] - node _T_160 = and(buf_state_en, _T_159) @[axi4_to_ahb.scala 202:32] - cmd_done <= _T_160 @[axi4_to_ahb.scala 202:16] - node _T_161 = and(master_ready, master_valid) @[axi4_to_ahb.scala 203:33] - node _T_162 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 203:64] - node _T_163 = and(_T_161, _T_162) @[axi4_to_ahb.scala 203:48] - node _T_164 = and(_T_163, buf_state_en) @[axi4_to_ahb.scala 203:79] - bypass_en <= _T_164 @[axi4_to_ahb.scala 203:17] - node _T_165 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 204:47] - node _T_166 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 204:62] - node _T_167 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 204:78] - node _T_168 = mux(_T_165, _T_166, _T_167) @[axi4_to_ahb.scala 204:30] - buf_cmd_byte_ptr <= _T_168 @[axi4_to_ahb.scala 204:24] - node _T_169 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 205:63] - node _T_170 = and(_T_169, buf_state_en) @[axi4_to_ahb.scala 205:78] - node _T_171 = eq(_T_170, UInt<1>("h00")) @[axi4_to_ahb.scala 205:47] - node _T_172 = bits(_T_171, 0, 0) @[Bitwise.scala 72:15] - node _T_173 = mux(_T_172, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_174 = and(UInt<2>("h02"), _T_173) @[axi4_to_ahb.scala 205:36] - io.ahb.out.htrans <= _T_174 @[axi4_to_ahb.scala 205:25] - slvbuf_wr_en <= buf_wr_en @[axi4_to_ahb.scala 206:20] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_175 = eq(UInt<3>("h07"), buf_state) @[Conditional.scala 37:30] - when _T_175 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h03") @[axi4_to_ahb.scala 210:20] - node _T_176 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 211:51] - node _T_177 = neq(_T_176, UInt<1>("h00")) @[axi4_to_ahb.scala 211:58] - node _T_178 = and(ahb_hready_q, _T_177) @[axi4_to_ahb.scala 211:36] - node _T_179 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 211:72] - node _T_180 = and(_T_178, _T_179) @[axi4_to_ahb.scala 211:70] - buf_state_en <= _T_180 @[axi4_to_ahb.scala 211:20] - slave_valid_pre <= buf_state_en @[axi4_to_ahb.scala 212:23] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 213:20] - node _T_181 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 214:35] - buf_cmd_byte_ptr <= _T_181 @[axi4_to_ahb.scala 214:24] - node _T_182 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 215:51] - node _T_183 = bits(_T_182, 0, 0) @[Bitwise.scala 72:15] - node _T_184 = mux(_T_183, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_185 = and(UInt<2>("h02"), _T_184) @[axi4_to_ahb.scala 215:41] - io.ahb.out.htrans <= _T_185 @[axi4_to_ahb.scala 215:25] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_186 = eq(UInt<3>("h03"), buf_state) @[Conditional.scala 37:30] - when _T_186 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h05") @[axi4_to_ahb.scala 219:20] - node _T_187 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 220:37] - buf_state_en <= _T_187 @[axi4_to_ahb.scala 220:20] - buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 221:22] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 222:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 223:23] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 224:20] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_188 = eq(UInt<3>("h02"), buf_state) @[Conditional.scala 37:30] - when _T_188 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h04") @[axi4_to_ahb.scala 228:20] - node _T_189 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 229:33] - node _T_190 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 229:63] - node _T_191 = neq(_T_190, UInt<1>("h00")) @[axi4_to_ahb.scala 229:70] - node _T_192 = and(_T_189, _T_191) @[axi4_to_ahb.scala 229:48] - trxn_done <= _T_192 @[axi4_to_ahb.scala 229:17] - buf_state_en <= trxn_done @[axi4_to_ahb.scala 230:20] - buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 231:27] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 232:20] - node _T_193 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 233:47] - node _T_194 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 233:85] - node _T_195 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 233:103] - node _T_196 = add(_T_194, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_197 = tail(_T_196, 1) @[axi4_to_ahb.scala 135:52] - node _T_198 = mux(UInt<1>("h01"), _T_197, _T_194) @[axi4_to_ahb.scala 135:24] - node _T_199 = bits(_T_195, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_200 = geq(UInt<1>("h00"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_201 = and(_T_199, _T_200) @[axi4_to_ahb.scala 136:48] - node _T_202 = bits(_T_195, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_203 = geq(UInt<1>("h01"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_204 = and(_T_202, _T_203) @[axi4_to_ahb.scala 136:48] - node _T_205 = bits(_T_195, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_206 = geq(UInt<2>("h02"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_207 = and(_T_205, _T_206) @[axi4_to_ahb.scala 136:48] - node _T_208 = bits(_T_195, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_209 = geq(UInt<2>("h03"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_210 = and(_T_208, _T_209) @[axi4_to_ahb.scala 136:48] - node _T_211 = bits(_T_195, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_212 = geq(UInt<3>("h04"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_213 = and(_T_211, _T_212) @[axi4_to_ahb.scala 136:48] - node _T_214 = bits(_T_195, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_215 = geq(UInt<3>("h05"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_216 = and(_T_214, _T_215) @[axi4_to_ahb.scala 136:48] - node _T_217 = bits(_T_195, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_218 = geq(UInt<3>("h06"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_219 = and(_T_217, _T_218) @[axi4_to_ahb.scala 136:48] - node _T_220 = bits(_T_195, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_221 = geq(UInt<3>("h07"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_222 = and(_T_220, _T_221) @[axi4_to_ahb.scala 136:48] - node _T_223 = mux(_T_222, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_224 = mux(_T_219, UInt<3>("h06"), _T_223) @[Mux.scala 98:16] - node _T_225 = mux(_T_216, UInt<3>("h05"), _T_224) @[Mux.scala 98:16] - node _T_226 = mux(_T_213, UInt<3>("h04"), _T_225) @[Mux.scala 98:16] - node _T_227 = mux(_T_210, UInt<2>("h03"), _T_226) @[Mux.scala 98:16] - node _T_228 = mux(_T_207, UInt<2>("h02"), _T_227) @[Mux.scala 98:16] - node _T_229 = mux(_T_204, UInt<1>("h01"), _T_228) @[Mux.scala 98:16] - node _T_230 = mux(_T_201, UInt<1>("h00"), _T_229) @[Mux.scala 98:16] - node _T_231 = mux(_T_193, _T_230, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 233:30] - buf_cmd_byte_ptr <= _T_231 @[axi4_to_ahb.scala 233:24] - node _T_232 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 234:65] - node _T_233 = or(buf_aligned, _T_232) @[axi4_to_ahb.scala 234:44] - node _T_234 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 234:127] - node _T_235 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 234:145] - node _T_236 = add(_T_234, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_237 = tail(_T_236, 1) @[axi4_to_ahb.scala 135:52] - node _T_238 = mux(UInt<1>("h01"), _T_237, _T_234) @[axi4_to_ahb.scala 135:24] - node _T_239 = bits(_T_235, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_240 = geq(UInt<1>("h00"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_241 = and(_T_239, _T_240) @[axi4_to_ahb.scala 136:48] - node _T_242 = bits(_T_235, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_243 = geq(UInt<1>("h01"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_244 = and(_T_242, _T_243) @[axi4_to_ahb.scala 136:48] - node _T_245 = bits(_T_235, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_246 = geq(UInt<2>("h02"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_247 = and(_T_245, _T_246) @[axi4_to_ahb.scala 136:48] - node _T_248 = bits(_T_235, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_249 = geq(UInt<2>("h03"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_250 = and(_T_248, _T_249) @[axi4_to_ahb.scala 136:48] - node _T_251 = bits(_T_235, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_252 = geq(UInt<3>("h04"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_253 = and(_T_251, _T_252) @[axi4_to_ahb.scala 136:48] - node _T_254 = bits(_T_235, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_255 = geq(UInt<3>("h05"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_256 = and(_T_254, _T_255) @[axi4_to_ahb.scala 136:48] - node _T_257 = bits(_T_235, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_258 = geq(UInt<3>("h06"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_259 = and(_T_257, _T_258) @[axi4_to_ahb.scala 136:48] - node _T_260 = bits(_T_235, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_261 = geq(UInt<3>("h07"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_262 = and(_T_260, _T_261) @[axi4_to_ahb.scala 136:48] - node _T_263 = mux(_T_262, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_264 = mux(_T_259, UInt<3>("h06"), _T_263) @[Mux.scala 98:16] - node _T_265 = mux(_T_256, UInt<3>("h05"), _T_264) @[Mux.scala 98:16] - node _T_266 = mux(_T_253, UInt<3>("h04"), _T_265) @[Mux.scala 98:16] - node _T_267 = mux(_T_250, UInt<2>("h03"), _T_266) @[Mux.scala 98:16] - node _T_268 = mux(_T_247, UInt<2>("h02"), _T_267) @[Mux.scala 98:16] - node _T_269 = mux(_T_244, UInt<1>("h01"), _T_268) @[Mux.scala 98:16] - node _T_270 = mux(_T_241, UInt<1>("h00"), _T_269) @[Mux.scala 98:16] - node _T_271 = dshr(buf_byteen, _T_270) @[axi4_to_ahb.scala 234:92] - node _T_272 = bits(_T_271, 0, 0) @[axi4_to_ahb.scala 234:92] - node _T_273 = eq(_T_272, UInt<1>("h00")) @[axi4_to_ahb.scala 234:163] - node _T_274 = or(_T_233, _T_273) @[axi4_to_ahb.scala 234:79] - node _T_275 = and(trxn_done, _T_274) @[axi4_to_ahb.scala 234:29] - cmd_done <= _T_275 @[axi4_to_ahb.scala 234:16] - node _T_276 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 235:47] - node _T_277 = eq(_T_276, UInt<1>("h00")) @[axi4_to_ahb.scala 235:36] - node _T_278 = bits(_T_277, 0, 0) @[Bitwise.scala 72:15] - node _T_279 = mux(_T_278, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_280 = and(_T_279, UInt<2>("h02")) @[axi4_to_ahb.scala 235:61] - io.ahb.out.htrans <= _T_280 @[axi4_to_ahb.scala 235:25] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_281 = eq(UInt<3>("h04"), buf_state) @[Conditional.scala 37:30] - when _T_281 : @[Conditional.scala 39:67] - node _T_282 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 239:34] - node _T_283 = or(_T_282, ahb_hresp_q) @[axi4_to_ahb.scala 239:50] - buf_state_en <= _T_283 @[axi4_to_ahb.scala 239:20] - node _T_284 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 240:38] - node _T_285 = and(buf_state_en, _T_284) @[axi4_to_ahb.scala 240:36] - node _T_286 = and(_T_285, slave_ready) @[axi4_to_ahb.scala 240:51] - master_ready <= _T_286 @[axi4_to_ahb.scala 240:20] - node _T_287 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 241:42] - node _T_288 = or(ahb_hresp_q, _T_287) @[axi4_to_ahb.scala 241:40] - node _T_289 = and(master_valid, master_valid) @[axi4_to_ahb.scala 241:80] - node _T_290 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 241:111] - node _T_291 = eq(_T_290, UInt<1>("h01")) @[axi4_to_ahb.scala 241:117] - node _T_292 = bits(_T_291, 0, 0) @[axi4_to_ahb.scala 241:132] - node _T_293 = mux(_T_292, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 241:99] - node _T_294 = mux(_T_289, _T_293, UInt<3>("h00")) @[axi4_to_ahb.scala 241:65] - node _T_295 = mux(_T_288, UInt<3>("h05"), _T_294) @[axi4_to_ahb.scala 241:26] - buf_nxtstate <= _T_295 @[axi4_to_ahb.scala 241:20] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 242:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 243:23] - node _T_296 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 244:33] - node _T_297 = eq(_T_296, UInt<1>("h01")) @[axi4_to_ahb.scala 244:39] - buf_write_in <= _T_297 @[axi4_to_ahb.scala 244:20] - node _T_298 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 245:50] - node _T_299 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 245:78] - node _T_300 = or(_T_298, _T_299) @[axi4_to_ahb.scala 245:62] - node _T_301 = and(buf_state_en, _T_300) @[axi4_to_ahb.scala 245:33] - buf_wr_en <= _T_301 @[axi4_to_ahb.scala 245:17] - buf_data_wr_en <= buf_wr_en @[axi4_to_ahb.scala 246:22] - node _T_302 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 247:65] - node _T_303 = neq(_T_302, UInt<1>("h00")) @[axi4_to_ahb.scala 247:71] - node _T_304 = and(ahb_hready_q, _T_303) @[axi4_to_ahb.scala 247:50] - node _T_305 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 248:29] - node _T_306 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 248:85] - node _T_307 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 248:101] - node _T_308 = add(_T_306, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_309 = tail(_T_308, 1) @[axi4_to_ahb.scala 135:52] - node _T_310 = mux(UInt<1>("h01"), _T_309, _T_306) @[axi4_to_ahb.scala 135:24] - node _T_311 = bits(_T_307, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_312 = geq(UInt<1>("h00"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_313 = and(_T_311, _T_312) @[axi4_to_ahb.scala 136:48] - node _T_314 = bits(_T_307, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_315 = geq(UInt<1>("h01"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_316 = and(_T_314, _T_315) @[axi4_to_ahb.scala 136:48] - node _T_317 = bits(_T_307, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_318 = geq(UInt<2>("h02"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_319 = and(_T_317, _T_318) @[axi4_to_ahb.scala 136:48] - node _T_320 = bits(_T_307, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_321 = geq(UInt<2>("h03"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_322 = and(_T_320, _T_321) @[axi4_to_ahb.scala 136:48] - node _T_323 = bits(_T_307, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_324 = geq(UInt<3>("h04"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_325 = and(_T_323, _T_324) @[axi4_to_ahb.scala 136:48] - node _T_326 = bits(_T_307, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_327 = geq(UInt<3>("h05"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_328 = and(_T_326, _T_327) @[axi4_to_ahb.scala 136:48] - node _T_329 = bits(_T_307, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_330 = geq(UInt<3>("h06"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_331 = and(_T_329, _T_330) @[axi4_to_ahb.scala 136:48] - node _T_332 = bits(_T_307, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_333 = geq(UInt<3>("h07"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_334 = and(_T_332, _T_333) @[axi4_to_ahb.scala 136:48] - node _T_335 = mux(_T_334, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_336 = mux(_T_331, UInt<3>("h06"), _T_335) @[Mux.scala 98:16] - node _T_337 = mux(_T_328, UInt<3>("h05"), _T_336) @[Mux.scala 98:16] - node _T_338 = mux(_T_325, UInt<3>("h04"), _T_337) @[Mux.scala 98:16] - node _T_339 = mux(_T_322, UInt<2>("h03"), _T_338) @[Mux.scala 98:16] - node _T_340 = mux(_T_319, UInt<2>("h02"), _T_339) @[Mux.scala 98:16] - node _T_341 = mux(_T_316, UInt<1>("h01"), _T_340) @[Mux.scala 98:16] - node _T_342 = mux(_T_313, UInt<1>("h00"), _T_341) @[Mux.scala 98:16] - node _T_343 = dshr(buf_byteen, _T_342) @[axi4_to_ahb.scala 248:51] - node _T_344 = bits(_T_343, 0, 0) @[axi4_to_ahb.scala 248:51] - node _T_345 = eq(_T_344, UInt<1>("h00")) @[axi4_to_ahb.scala 248:116] - node _T_346 = or(_T_305, _T_345) @[axi4_to_ahb.scala 248:38] - node _T_347 = and(_T_304, _T_346) @[axi4_to_ahb.scala 247:80] - node _T_348 = or(ahb_hresp_q, _T_347) @[axi4_to_ahb.scala 247:34] - cmd_done <= _T_348 @[axi4_to_ahb.scala 247:16] - node _T_349 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 249:33] - node _T_350 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 249:64] - node _T_351 = and(_T_349, _T_350) @[axi4_to_ahb.scala 249:48] - bypass_en <= _T_351 @[axi4_to_ahb.scala 249:17] - node _T_352 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 250:48] - node _T_353 = eq(_T_352, UInt<1>("h00")) @[axi4_to_ahb.scala 250:37] - node _T_354 = or(_T_353, bypass_en) @[axi4_to_ahb.scala 250:61] - node _T_355 = bits(_T_354, 0, 0) @[Bitwise.scala 72:15] - node _T_356 = mux(_T_355, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_357 = and(_T_356, UInt<2>("h02")) @[axi4_to_ahb.scala 250:75] - io.ahb.out.htrans <= _T_357 @[axi4_to_ahb.scala 250:25] - node _T_358 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 251:55] - node _T_359 = and(buf_state_en, _T_358) @[axi4_to_ahb.scala 251:39] - slave_valid_pre <= _T_359 @[axi4_to_ahb.scala 251:23] - node _T_360 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 252:33] - node _T_361 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 252:63] - node _T_362 = neq(_T_361, UInt<1>("h00")) @[axi4_to_ahb.scala 252:69] - node _T_363 = and(_T_360, _T_362) @[axi4_to_ahb.scala 252:48] - trxn_done <= _T_363 @[axi4_to_ahb.scala 252:17] - node _T_364 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 253:40] - buf_cmd_byte_ptr_en <= _T_364 @[axi4_to_ahb.scala 253:27] - node _T_365 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 254:79] - node _T_366 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_367 = tail(_T_366, 1) @[axi4_to_ahb.scala 135:52] - node _T_368 = mux(UInt<1>("h00"), _T_367, UInt<3>("h00")) @[axi4_to_ahb.scala 135:24] - node _T_369 = bits(_T_365, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_370 = geq(UInt<1>("h00"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_371 = and(_T_369, _T_370) @[axi4_to_ahb.scala 136:48] - node _T_372 = bits(_T_365, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_373 = geq(UInt<1>("h01"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_374 = and(_T_372, _T_373) @[axi4_to_ahb.scala 136:48] - node _T_375 = bits(_T_365, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_376 = geq(UInt<2>("h02"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_377 = and(_T_375, _T_376) @[axi4_to_ahb.scala 136:48] - node _T_378 = bits(_T_365, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_379 = geq(UInt<2>("h03"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_380 = and(_T_378, _T_379) @[axi4_to_ahb.scala 136:48] - node _T_381 = bits(_T_365, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_382 = geq(UInt<3>("h04"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_383 = and(_T_381, _T_382) @[axi4_to_ahb.scala 136:48] - node _T_384 = bits(_T_365, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_385 = geq(UInt<3>("h05"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_386 = and(_T_384, _T_385) @[axi4_to_ahb.scala 136:48] - node _T_387 = bits(_T_365, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_388 = geq(UInt<3>("h06"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_389 = and(_T_387, _T_388) @[axi4_to_ahb.scala 136:48] - node _T_390 = bits(_T_365, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_391 = geq(UInt<3>("h07"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_392 = and(_T_390, _T_391) @[axi4_to_ahb.scala 136:48] - node _T_393 = mux(_T_392, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_394 = mux(_T_389, UInt<3>("h06"), _T_393) @[Mux.scala 98:16] - node _T_395 = mux(_T_386, UInt<3>("h05"), _T_394) @[Mux.scala 98:16] - node _T_396 = mux(_T_383, UInt<3>("h04"), _T_395) @[Mux.scala 98:16] - node _T_397 = mux(_T_380, UInt<2>("h03"), _T_396) @[Mux.scala 98:16] - node _T_398 = mux(_T_377, UInt<2>("h02"), _T_397) @[Mux.scala 98:16] - node _T_399 = mux(_T_374, UInt<1>("h01"), _T_398) @[Mux.scala 98:16] - node _T_400 = mux(_T_371, UInt<1>("h00"), _T_399) @[Mux.scala 98:16] - node _T_401 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 254:141] - node _T_402 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 254:157] - node _T_403 = add(_T_401, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_404 = tail(_T_403, 1) @[axi4_to_ahb.scala 135:52] - node _T_405 = mux(UInt<1>("h01"), _T_404, _T_401) @[axi4_to_ahb.scala 135:24] - node _T_406 = bits(_T_402, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_407 = geq(UInt<1>("h00"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_408 = and(_T_406, _T_407) @[axi4_to_ahb.scala 136:48] - node _T_409 = bits(_T_402, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_410 = geq(UInt<1>("h01"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_411 = and(_T_409, _T_410) @[axi4_to_ahb.scala 136:48] - node _T_412 = bits(_T_402, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_413 = geq(UInt<2>("h02"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_414 = and(_T_412, _T_413) @[axi4_to_ahb.scala 136:48] - node _T_415 = bits(_T_402, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_416 = geq(UInt<2>("h03"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_417 = and(_T_415, _T_416) @[axi4_to_ahb.scala 136:48] - node _T_418 = bits(_T_402, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_419 = geq(UInt<3>("h04"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_420 = and(_T_418, _T_419) @[axi4_to_ahb.scala 136:48] - node _T_421 = bits(_T_402, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_422 = geq(UInt<3>("h05"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_423 = and(_T_421, _T_422) @[axi4_to_ahb.scala 136:48] - node _T_424 = bits(_T_402, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_425 = geq(UInt<3>("h06"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_426 = and(_T_424, _T_425) @[axi4_to_ahb.scala 136:48] - node _T_427 = bits(_T_402, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_428 = geq(UInt<3>("h07"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_429 = and(_T_427, _T_428) @[axi4_to_ahb.scala 136:48] - node _T_430 = mux(_T_429, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_431 = mux(_T_426, UInt<3>("h06"), _T_430) @[Mux.scala 98:16] - node _T_432 = mux(_T_423, UInt<3>("h05"), _T_431) @[Mux.scala 98:16] - node _T_433 = mux(_T_420, UInt<3>("h04"), _T_432) @[Mux.scala 98:16] - node _T_434 = mux(_T_417, UInt<2>("h03"), _T_433) @[Mux.scala 98:16] - node _T_435 = mux(_T_414, UInt<2>("h02"), _T_434) @[Mux.scala 98:16] - node _T_436 = mux(_T_411, UInt<1>("h01"), _T_435) @[Mux.scala 98:16] - node _T_437 = mux(_T_408, UInt<1>("h00"), _T_436) @[Mux.scala 98:16] - node _T_438 = mux(trxn_done, _T_437, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 254:97] - node _T_439 = mux(bypass_en, _T_400, _T_438) @[axi4_to_ahb.scala 254:30] - buf_cmd_byte_ptr <= _T_439 @[axi4_to_ahb.scala 254:24] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_440 = eq(UInt<3>("h05"), buf_state) @[Conditional.scala 37:30] - when _T_440 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 257:20] - buf_state_en <= slave_ready @[axi4_to_ahb.scala 258:20] - slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 259:23] - slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 260:23] - skip @[Conditional.scala 39:67] - cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 264:16] - node _T_441 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 265:33] - node _T_442 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 265:73] - node _T_443 = eq(_T_442, UInt<1>("h01")) @[axi4_to_ahb.scala 265:80] - node _T_444 = and(buf_aligned_in, _T_443) @[axi4_to_ahb.scala 265:60] - node _T_445 = bits(_T_444, 0, 0) @[axi4_to_ahb.scala 265:100] - node _T_446 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 265:132] - node _T_447 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 127:50] - node _T_448 = eq(_T_447, UInt<8>("h0ff")) @[axi4_to_ahb.scala 127:57] - node _T_449 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 127:81] - node _T_450 = eq(_T_449, UInt<8>("h0f")) @[axi4_to_ahb.scala 127:88] - node _T_451 = or(_T_448, _T_450) @[axi4_to_ahb.scala 127:70] - node _T_452 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 127:117] - node _T_453 = eq(_T_452, UInt<8>("h03")) @[axi4_to_ahb.scala 127:124] - node _T_454 = or(_T_451, _T_453) @[axi4_to_ahb.scala 127:106] - node _T_455 = bits(_T_454, 0, 0) @[Bitwise.scala 72:15] - node _T_456 = mux(_T_455, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_457 = and(UInt<3>("h00"), _T_456) @[axi4_to_ahb.scala 127:29] - node _T_458 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 128:35] - node _T_459 = eq(_T_458, UInt<8>("h0c")) @[axi4_to_ahb.scala 128:42] - node _T_460 = bits(_T_459, 0, 0) @[Bitwise.scala 72:15] - node _T_461 = mux(_T_460, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_462 = and(UInt<2>("h02"), _T_461) @[axi4_to_ahb.scala 128:15] - node _T_463 = or(_T_457, _T_462) @[axi4_to_ahb.scala 127:146] - node _T_464 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 129:36] - node _T_465 = eq(_T_464, UInt<8>("h0f0")) @[axi4_to_ahb.scala 129:43] - node _T_466 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 129:67] - node _T_467 = eq(_T_466, UInt<8>("h03")) @[axi4_to_ahb.scala 129:74] - node _T_468 = or(_T_465, _T_467) @[axi4_to_ahb.scala 129:56] - node _T_469 = bits(_T_468, 0, 0) @[Bitwise.scala 72:15] - node _T_470 = mux(_T_469, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_471 = and(UInt<3>("h04"), _T_470) @[axi4_to_ahb.scala 129:15] - node _T_472 = or(_T_463, _T_471) @[axi4_to_ahb.scala 128:63] - node _T_473 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 130:35] - node _T_474 = eq(_T_473, UInt<8>("h0c0")) @[axi4_to_ahb.scala 130:42] - node _T_475 = bits(_T_474, 0, 0) @[Bitwise.scala 72:15] - node _T_476 = mux(_T_475, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_477 = and(UInt<3>("h06"), _T_476) @[axi4_to_ahb.scala 130:15] - node _T_478 = or(_T_472, _T_477) @[axi4_to_ahb.scala 129:96] - node _T_479 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 131:33] - node _T_480 = eq(_T_479, UInt<8>("h0c0")) @[axi4_to_ahb.scala 131:40] - node _T_481 = bits(_T_480, 0, 0) @[Bitwise.scala 72:15] - node _T_482 = mux(_T_481, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_483 = and(UInt<3>("h06"), _T_482) @[axi4_to_ahb.scala 131:13] - node _T_484 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 265:152] - node _T_485 = mux(_T_445, _T_478, _T_484) @[axi4_to_ahb.scala 265:43] - node _T_486 = cat(_T_441, _T_485) @[Cat.scala 29:58] - buf_addr_in <= _T_486 @[axi4_to_ahb.scala 265:15] - node _T_487 = bits(master_tag, 2, 0) @[axi4_to_ahb.scala 266:27] - buf_tag_in <= _T_487 @[axi4_to_ahb.scala 266:14] - node _T_488 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 267:32] - buf_byteen_in <= _T_488 @[axi4_to_ahb.scala 267:17] - node _T_489 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 268:33] - node _T_490 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 268:59] - node _T_491 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 268:80] - node _T_492 = mux(_T_489, _T_490, _T_491) @[axi4_to_ahb.scala 268:21] - buf_data_in <= _T_492 @[axi4_to_ahb.scala 268:15] - node _T_493 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 269:52] - node _T_494 = eq(_T_493, UInt<2>("h03")) @[axi4_to_ahb.scala 269:58] - node _T_495 = and(buf_aligned_in, _T_494) @[axi4_to_ahb.scala 269:38] - node _T_496 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 269:84] - node _T_497 = eq(_T_496, UInt<1>("h01")) @[axi4_to_ahb.scala 269:91] - node _T_498 = and(_T_495, _T_497) @[axi4_to_ahb.scala 269:71] - node _T_499 = bits(_T_498, 0, 0) @[axi4_to_ahb.scala 269:111] - node _T_500 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 269:142] - node _T_501 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 121:42] - node _T_502 = eq(_T_501, UInt<8>("h0ff")) @[axi4_to_ahb.scala 121:49] - node _T_503 = bits(_T_502, 0, 0) @[Bitwise.scala 72:15] - node _T_504 = mux(_T_503, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_505 = and(UInt<2>("h03"), _T_504) @[axi4_to_ahb.scala 121:25] - node _T_506 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 122:35] - node _T_507 = eq(_T_506, UInt<8>("h0f0")) @[axi4_to_ahb.scala 122:42] - node _T_508 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 122:64] - node _T_509 = eq(_T_508, UInt<8>("h0f")) @[axi4_to_ahb.scala 122:71] - node _T_510 = or(_T_507, _T_509) @[axi4_to_ahb.scala 122:55] - node _T_511 = bits(_T_510, 0, 0) @[Bitwise.scala 72:15] - node _T_512 = mux(_T_511, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_513 = and(UInt<2>("h02"), _T_512) @[axi4_to_ahb.scala 122:16] - node _T_514 = or(_T_505, _T_513) @[axi4_to_ahb.scala 121:64] - node _T_515 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:40] - node _T_516 = eq(_T_515, UInt<8>("h0c0")) @[axi4_to_ahb.scala 123:47] - node _T_517 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:69] - node _T_518 = eq(_T_517, UInt<6>("h030")) @[axi4_to_ahb.scala 123:76] - node _T_519 = or(_T_516, _T_518) @[axi4_to_ahb.scala 123:60] - node _T_520 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:98] - node _T_521 = eq(_T_520, UInt<8>("h0c")) @[axi4_to_ahb.scala 123:105] - node _T_522 = or(_T_519, _T_521) @[axi4_to_ahb.scala 123:89] - node _T_523 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:132] - node _T_524 = eq(_T_523, UInt<8>("h03")) @[axi4_to_ahb.scala 123:139] - node _T_525 = or(_T_522, _T_524) @[axi4_to_ahb.scala 123:123] - node _T_526 = bits(_T_525, 0, 0) @[Bitwise.scala 72:15] - node _T_527 = mux(_T_526, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_528 = and(UInt<2>("h01"), _T_527) @[axi4_to_ahb.scala 123:21] - node _T_529 = or(_T_514, _T_528) @[axi4_to_ahb.scala 122:93] - node _T_530 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 269:161] - node _T_531 = mux(_T_499, _T_529, _T_530) @[axi4_to_ahb.scala 269:21] - buf_size_in <= _T_531 @[axi4_to_ahb.scala 269:15] - node _T_532 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 270:32] - node _T_533 = eq(_T_532, UInt<1>("h00")) @[axi4_to_ahb.scala 270:39] - node _T_534 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 271:17] - node _T_535 = eq(_T_534, UInt<1>("h00")) @[axi4_to_ahb.scala 271:24] - node _T_536 = or(_T_533, _T_535) @[axi4_to_ahb.scala 270:48] - node _T_537 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 271:47] - node _T_538 = eq(_T_537, UInt<2>("h01")) @[axi4_to_ahb.scala 271:54] - node _T_539 = or(_T_536, _T_538) @[axi4_to_ahb.scala 271:33] - node _T_540 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 271:86] - node _T_541 = eq(_T_540, UInt<2>("h02")) @[axi4_to_ahb.scala 271:93] - node _T_542 = or(_T_539, _T_541) @[axi4_to_ahb.scala 271:72] - node _T_543 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 272:18] - node _T_544 = eq(_T_543, UInt<2>("h03")) @[axi4_to_ahb.scala 272:25] - node _T_545 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:55] - node _T_546 = eq(_T_545, UInt<2>("h03")) @[axi4_to_ahb.scala 272:62] - node _T_547 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:90] - node _T_548 = eq(_T_547, UInt<4>("h0c")) @[axi4_to_ahb.scala 272:97] - node _T_549 = or(_T_546, _T_548) @[axi4_to_ahb.scala 272:74] - node _T_550 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:125] - node _T_551 = eq(_T_550, UInt<6>("h030")) @[axi4_to_ahb.scala 272:132] - node _T_552 = or(_T_549, _T_551) @[axi4_to_ahb.scala 272:109] - node _T_553 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:161] - node _T_554 = eq(_T_553, UInt<8>("h0c0")) @[axi4_to_ahb.scala 272:168] - node _T_555 = or(_T_552, _T_554) @[axi4_to_ahb.scala 272:145] - node _T_556 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 273:21] - node _T_557 = eq(_T_556, UInt<4>("h0f")) @[axi4_to_ahb.scala 273:28] - node _T_558 = or(_T_555, _T_557) @[axi4_to_ahb.scala 272:181] - node _T_559 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 273:56] - node _T_560 = eq(_T_559, UInt<8>("h0f0")) @[axi4_to_ahb.scala 273:63] - node _T_561 = or(_T_558, _T_560) @[axi4_to_ahb.scala 273:40] - node _T_562 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 273:92] - node _T_563 = eq(_T_562, UInt<8>("h0ff")) @[axi4_to_ahb.scala 273:99] - node _T_564 = or(_T_561, _T_563) @[axi4_to_ahb.scala 273:76] - node _T_565 = and(_T_544, _T_564) @[axi4_to_ahb.scala 272:38] - node _T_566 = or(_T_542, _T_565) @[axi4_to_ahb.scala 271:106] - buf_aligned_in <= _T_566 @[axi4_to_ahb.scala 270:18] - node _T_567 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 275:43] - node _T_568 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 275:62] - node _T_569 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 275:87] - node _T_570 = cat(_T_568, _T_569) @[Cat.scala 29:58] - node _T_571 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 275:108] - node _T_572 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 275:133] - node _T_573 = cat(_T_571, _T_572) @[Cat.scala 29:58] - node _T_574 = mux(_T_567, _T_570, _T_573) @[axi4_to_ahb.scala 275:26] - io.ahb.out.haddr <= _T_574 @[axi4_to_ahb.scala 275:20] - node _T_575 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 276:43] - node _T_576 = bits(buf_aligned_in, 0, 0) @[Bitwise.scala 72:15] - node _T_577 = mux(_T_576, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_578 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 276:94] - node _T_579 = and(_T_577, _T_578) @[axi4_to_ahb.scala 276:81] - node _T_580 = cat(UInt<1>("h00"), _T_579) @[Cat.scala 29:58] - node _T_581 = bits(buf_aligned, 0, 0) @[Bitwise.scala 72:15] - node _T_582 = mux(_T_581, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_583 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 276:148] - node _T_584 = and(_T_582, _T_583) @[axi4_to_ahb.scala 276:138] - node _T_585 = cat(UInt<1>("h00"), _T_584) @[Cat.scala 29:58] - node _T_586 = mux(_T_575, _T_580, _T_585) @[axi4_to_ahb.scala 276:26] - io.ahb.out.hsize <= _T_586 @[axi4_to_ahb.scala 276:20] - io.ahb.out.hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 278:21] - io.ahb.out.hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 279:24] - node _T_587 = bits(io.axi.ar.bits.prot, 2, 2) @[axi4_to_ahb.scala 280:57] - node _T_588 = eq(_T_587, UInt<1>("h00")) @[axi4_to_ahb.scala 280:37] - node _T_589 = cat(UInt<1>("h01"), _T_588) @[Cat.scala 29:58] - io.ahb.out.hprot <= _T_589 @[axi4_to_ahb.scala 280:20] - node _T_590 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 281:44] - node _T_591 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 281:59] - node _T_592 = eq(_T_591, UInt<1>("h01")) @[axi4_to_ahb.scala 281:66] - node _T_593 = mux(_T_590, _T_592, buf_write) @[axi4_to_ahb.scala 281:27] - io.ahb.out.hwrite <= _T_593 @[axi4_to_ahb.scala 281:21] - node _T_594 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 282:32] - io.ahb.out.hwdata <= _T_594 @[axi4_to_ahb.scala 282:21] - slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 284:15] - node _T_595 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 285:43] - node _T_596 = mux(_T_595, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 285:23] - node _T_597 = bits(slvbuf_error, 0, 0) @[Bitwise.scala 72:15] - node _T_598 = mux(_T_597, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_599 = and(_T_598, UInt<2>("h02")) @[axi4_to_ahb.scala 285:88] - node _T_600 = cat(_T_596, _T_599) @[Cat.scala 29:58] - slave_opc <= _T_600 @[axi4_to_ahb.scala 285:13] - node _T_601 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 286:41] - node _T_602 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 286:66] - node _T_603 = cat(_T_602, _T_602) @[Cat.scala 29:58] - node _T_604 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 286:91] - node _T_605 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 286:110] - node _T_606 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 286:131] - node _T_607 = mux(_T_604, _T_605, _T_606) @[axi4_to_ahb.scala 286:79] - node _T_608 = mux(_T_601, _T_603, _T_607) @[axi4_to_ahb.scala 286:21] - slave_rdata <= _T_608 @[axi4_to_ahb.scala 286:15] - node _T_609 = bits(slvbuf_tag, 2, 0) @[axi4_to_ahb.scala 287:26] - slave_tag <= _T_609 @[axi4_to_ahb.scala 287:13] - node _T_610 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 289:37] - node _T_611 = neq(_T_610, UInt<1>("h00")) @[axi4_to_ahb.scala 289:44] - node _T_612 = and(_T_611, io.ahb.in.hready) @[axi4_to_ahb.scala 289:56] - node _T_613 = and(_T_612, io.ahb.out.hwrite) @[axi4_to_ahb.scala 289:75] - last_addr_en <= _T_613 @[axi4_to_ahb.scala 289:16] - node _T_614 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 291:31] - node _T_615 = and(_T_614, master_ready) @[axi4_to_ahb.scala 291:49] - wrbuf_en <= _T_615 @[axi4_to_ahb.scala 291:12] - node _T_616 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 292:35] - node _T_617 = and(_T_616, master_ready) @[axi4_to_ahb.scala 292:52] - wrbuf_data_en <= _T_617 @[axi4_to_ahb.scala 292:17] - node _T_618 = and(master_valid, master_ready) @[axi4_to_ahb.scala 293:34] - node _T_619 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 293:62] - node _T_620 = eq(_T_619, UInt<1>("h01")) @[axi4_to_ahb.scala 293:69] - node _T_621 = and(_T_618, _T_620) @[axi4_to_ahb.scala 293:49] - wrbuf_cmd_sent <= _T_621 @[axi4_to_ahb.scala 293:18] - node _T_622 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 294:33] - node _T_623 = and(wrbuf_cmd_sent, _T_622) @[axi4_to_ahb.scala 294:31] - wrbuf_rst <= _T_623 @[axi4_to_ahb.scala 294:13] - node _T_624 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 296:36] - node _T_625 = and(wrbuf_vld, _T_624) @[axi4_to_ahb.scala 296:34] - node _T_626 = eq(_T_625, UInt<1>("h00")) @[axi4_to_ahb.scala 296:22] - node _T_627 = and(_T_626, master_ready) @[axi4_to_ahb.scala 296:53] - io.axi.aw.ready <= _T_627 @[axi4_to_ahb.scala 296:19] - node _T_628 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 297:40] - node _T_629 = and(wrbuf_data_vld, _T_628) @[axi4_to_ahb.scala 297:38] - node _T_630 = eq(_T_629, UInt<1>("h00")) @[axi4_to_ahb.scala 297:21] - node _T_631 = and(_T_630, master_ready) @[axi4_to_ahb.scala 297:57] - io.axi.w.ready <= _T_631 @[axi4_to_ahb.scala 297:18] - node _T_632 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 298:34] - node _T_633 = eq(_T_632, UInt<1>("h00")) @[axi4_to_ahb.scala 298:22] - node _T_634 = and(_T_633, master_ready) @[axi4_to_ahb.scala 298:52] - io.axi.ar.ready <= _T_634 @[axi4_to_ahb.scala 298:19] - io.axi.r.bits.last <= UInt<1>("h01") @[axi4_to_ahb.scala 299:22] - node _T_635 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 301:71] - node _T_636 = mux(_T_635, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 301:55] - node _T_637 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 301:91] - node _T_638 = and(_T_636, _T_637) @[axi4_to_ahb.scala 301:89] - reg _T_639 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 301:51] - _T_639 <= _T_638 @[axi4_to_ahb.scala 301:51] - wrbuf_vld <= _T_639 @[axi4_to_ahb.scala 301:21] - node _T_640 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 302:76] - node _T_641 = mux(_T_640, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 302:55] - node _T_642 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 302:102] - node _T_643 = and(_T_641, _T_642) @[axi4_to_ahb.scala 302:100] - reg _T_644 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 302:51] - _T_644 <= _T_643 @[axi4_to_ahb.scala 302:51] - wrbuf_data_vld <= _T_644 @[axi4_to_ahb.scala 302:21] - node _T_645 = bits(io.axi.aw.bits.id, 2, 0) @[axi4_to_ahb.scala 303:71] - node _T_646 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 303:105] - reg _T_647 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_646 : @[Reg.scala 28:19] - _T_647 <= _T_645 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - wrbuf_tag <= _T_647 @[axi4_to_ahb.scala 303:21] - node _T_648 = bits(io.axi.aw.bits.size, 2, 0) @[axi4_to_ahb.scala 304:73] - node _T_649 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 304:101] - reg _T_650 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_649 : @[Reg.scala 28:19] - _T_650 <= _T_648 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - wrbuf_size <= _T_650 @[axi4_to_ahb.scala 304:21] - node _T_651 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 305:61] - inst rvclkhdr_2 of rvclkhdr_871 @[lib.scala 368:23] - rvclkhdr_2.clock <= clock - rvclkhdr_2.reset <= reset - rvclkhdr_2.io.clk <= bus_clk @[lib.scala 370:18] - rvclkhdr_2.io.en <= _T_651 @[lib.scala 371:17] - rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_652 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_652 <= io.axi.aw.bits.addr @[lib.scala 374:16] - wrbuf_addr <= _T_652 @[axi4_to_ahb.scala 305:21] - node _T_653 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 306:65] - inst rvclkhdr_3 of rvclkhdr_872 @[lib.scala 368:23] - rvclkhdr_3.clock <= clock - rvclkhdr_3.reset <= reset - rvclkhdr_3.io.clk <= bus_clk @[lib.scala 370:18] - rvclkhdr_3.io.en <= _T_653 @[lib.scala 371:17] - rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_654 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_654 <= io.axi.w.bits.data @[lib.scala 374:16] - wrbuf_data <= _T_654 @[axi4_to_ahb.scala 306:21] - node _T_655 = bits(io.axi.w.bits.strb, 7, 0) @[axi4_to_ahb.scala 307:72] - node _T_656 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 307:105] - reg _T_657 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_656 : @[Reg.scala 28:19] - _T_657 <= _T_655 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - wrbuf_byteen <= _T_657 @[axi4_to_ahb.scala 307:21] - node _T_658 = bits(io.ahb.out.haddr, 31, 0) @[axi4_to_ahb.scala 308:71] - node _T_659 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 308:104] - reg _T_660 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_659 : @[Reg.scala 28:19] - _T_660 <= _T_658 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - last_bus_addr <= _T_660 @[axi4_to_ahb.scala 308:21] - node _T_661 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 309:89] - reg _T_662 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_661 : @[Reg.scala 28:19] - _T_662 <= buf_write_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_write <= _T_662 @[axi4_to_ahb.scala 309:21] - node _T_663 = bits(buf_tag_in, 2, 0) @[axi4_to_ahb.scala 310:64] - node _T_664 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 310:99] - reg _T_665 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_664 : @[Reg.scala 28:19] - _T_665 <= _T_663 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_tag <= _T_665 @[axi4_to_ahb.scala 310:21] - node _T_666 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 311:42] - node _T_667 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 311:61] - node _T_668 = bits(_T_667, 0, 0) @[axi4_to_ahb.scala 311:78] - inst rvclkhdr_4 of rvclkhdr_873 @[lib.scala 368:23] - rvclkhdr_4.clock <= clock - rvclkhdr_4.reset <= reset - rvclkhdr_4.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_4.io.en <= _T_668 @[lib.scala 371:17] - rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_669 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_669 <= _T_666 @[lib.scala 374:16] - buf_addr <= _T_669 @[axi4_to_ahb.scala 311:21] - node _T_670 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 312:65] - node _T_671 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 312:94] - reg _T_672 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_671 : @[Reg.scala 28:19] - _T_672 <= _T_670 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_size <= _T_672 @[axi4_to_ahb.scala 312:21] - node _T_673 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 313:91] - reg _T_674 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_673 : @[Reg.scala 28:19] - _T_674 <= buf_aligned_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_aligned <= _T_674 @[axi4_to_ahb.scala 313:21] - node _T_675 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 314:67] - node _T_676 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 314:96] - reg _T_677 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_676 : @[Reg.scala 28:19] - _T_677 <= _T_675 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_byteen <= _T_677 @[axi4_to_ahb.scala 314:21] - node _T_678 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 315:42] - node _T_679 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 315:66] - node _T_680 = bits(_T_679, 0, 0) @[axi4_to_ahb.scala 315:89] - inst rvclkhdr_5 of rvclkhdr_874 @[lib.scala 368:23] - rvclkhdr_5.clock <= clock - rvclkhdr_5.reset <= reset - rvclkhdr_5.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_5.io.en <= _T_680 @[lib.scala 371:17] - rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_681 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_681 <= _T_678 @[lib.scala 374:16] - buf_data <= _T_681 @[axi4_to_ahb.scala 315:21] - node _T_682 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 316:89] - reg _T_683 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_682 : @[Reg.scala 28:19] - _T_683 <= buf_write @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - slvbuf_write <= _T_683 @[axi4_to_ahb.scala 316:21] - node _T_684 = bits(buf_tag, 2, 0) @[axi4_to_ahb.scala 317:61] - node _T_685 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 317:99] - reg _T_686 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_685 : @[Reg.scala 28:19] - _T_686 <= _T_684 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - slvbuf_tag <= _T_686 @[axi4_to_ahb.scala 317:21] - node _T_687 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 318:99] - reg _T_688 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_687 : @[Reg.scala 28:19] - _T_688 <= slvbuf_error_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - slvbuf_error <= _T_688 @[axi4_to_ahb.scala 318:21] - node _T_689 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 319:72] - node _T_690 = mux(_T_689, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 319:56] - node _T_691 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 319:92] - node _T_692 = and(_T_690, _T_691) @[axi4_to_ahb.scala 319:90] - reg _T_693 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 319:52] - _T_693 <= _T_692 @[axi4_to_ahb.scala 319:52] - cmd_doneQ <= _T_693 @[axi4_to_ahb.scala 319:21] - node _T_694 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 320:71] - node _T_695 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 320:110] - reg _T_696 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_695 : @[Reg.scala 28:19] - _T_696 <= _T_694 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_cmd_byte_ptrQ <= _T_696 @[axi4_to_ahb.scala 320:21] - reg _T_697 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 321:52] - _T_697 <= io.ahb.in.hready @[axi4_to_ahb.scala 321:52] - ahb_hready_q <= _T_697 @[axi4_to_ahb.scala 321:21] - node _T_698 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 322:70] - reg _T_699 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 322:52] - _T_699 <= _T_698 @[axi4_to_ahb.scala 322:52] - ahb_htrans_q <= _T_699 @[axi4_to_ahb.scala 322:21] - reg _T_700 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 323:57] - _T_700 <= io.ahb.out.hwrite @[axi4_to_ahb.scala 323:57] - ahb_hwrite_q <= _T_700 @[axi4_to_ahb.scala 323:21] - reg _T_701 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 324:52] - _T_701 <= io.ahb.in.hresp @[axi4_to_ahb.scala 324:52] - ahb_hresp_q <= _T_701 @[axi4_to_ahb.scala 324:21] - node _T_702 = bits(io.ahb.in.hrdata, 63, 0) @[axi4_to_ahb.scala 325:74] - reg _T_703 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 325:57] - _T_703 <= _T_702 @[axi4_to_ahb.scala 325:57] - ahb_hrdata_q <= _T_703 @[axi4_to_ahb.scala 325:21] - node _T_704 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 327:43] - node _T_705 = or(_T_704, io.clk_override) @[axi4_to_ahb.scala 327:58] - node _T_706 = and(io.bus_clk_en, _T_705) @[axi4_to_ahb.scala 327:30] - buf_clken <= _T_706 @[axi4_to_ahb.scala 327:13] - node _T_707 = bits(io.ahb.out.htrans, 1, 1) @[axi4_to_ahb.scala 328:76] - node _T_708 = and(io.ahb.in.hready, _T_707) @[axi4_to_ahb.scala 328:57] - node _T_709 = or(_T_708, io.clk_override) @[axi4_to_ahb.scala 328:81] - node _T_710 = and(io.bus_clk_en, _T_709) @[axi4_to_ahb.scala 328:36] - ahbm_addr_clken <= _T_710 @[axi4_to_ahb.scala 328:19] - node _T_711 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 329:50] - node _T_712 = or(_T_711, io.clk_override) @[axi4_to_ahb.scala 329:60] - node _T_713 = and(io.bus_clk_en, _T_712) @[axi4_to_ahb.scala 329:36] - ahbm_data_clken <= _T_713 @[axi4_to_ahb.scala 329:19] - inst rvclkhdr_6 of rvclkhdr_875 @[lib.scala 343:22] - rvclkhdr_6.clock <= clock - rvclkhdr_6.reset <= reset - rvclkhdr_6.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_6.io.en <= buf_clken @[lib.scala 345:16] - rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - buf_clk <= rvclkhdr_6.io.l1clk @[axi4_to_ahb.scala 332:12] - inst rvclkhdr_7 of rvclkhdr_876 @[lib.scala 343:22] - rvclkhdr_7.clock <= clock - rvclkhdr_7.reset <= reset - rvclkhdr_7.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_7.io.en <= io.bus_clk_en @[lib.scala 345:16] - rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahbm_clk <= rvclkhdr_7.io.l1clk @[axi4_to_ahb.scala 333:12] - inst rvclkhdr_8 of rvclkhdr_877 @[lib.scala 343:22] - rvclkhdr_8.clock <= clock - rvclkhdr_8.reset <= reset - rvclkhdr_8.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_8.io.en <= ahbm_addr_clken @[lib.scala 345:16] - rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahbm_addr_clk <= rvclkhdr_8.io.l1clk @[axi4_to_ahb.scala 334:17] - inst rvclkhdr_9 of rvclkhdr_878 @[lib.scala 343:22] - rvclkhdr_9.clock <= clock - rvclkhdr_9.reset <= reset - rvclkhdr_9.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_9.io.en <= ahbm_data_clken @[lib.scala 345:16] - rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahbm_data_clk <= rvclkhdr_9.io.l1clk @[axi4_to_ahb.scala 335:17] - - extmodule gated_latch_879 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_879 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_879 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_880 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_880 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_880 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_881 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_881 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_881 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_882 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_882 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_882 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_883 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_883 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_883 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_884 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_884 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_884 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - module ahb_to_axi4 : - input clock : Clock - input reset : AsyncReset - output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ahb : {flip sig : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, flip hsel : UInt<1>, flip hreadyin : UInt<1>}} - - wire _T : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[ahb_to_axi4.scala 20:25] - _T.r.bits.last <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.r.bits.resp <= UInt<2>("h00") @[ahb_to_axi4.scala 20:25] - _T.r.bits.data <= UInt<64>("h00") @[ahb_to_axi4.scala 20:25] - _T.r.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.r.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.r.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.ar.bits.qos <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25] - _T.ar.bits.prot <= UInt<3>("h00") @[ahb_to_axi4.scala 20:25] - _T.ar.bits.cache <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25] - _T.ar.bits.lock <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.ar.bits.burst <= UInt<2>("h00") @[ahb_to_axi4.scala 20:25] - _T.ar.bits.size <= UInt<3>("h00") @[ahb_to_axi4.scala 20:25] - _T.ar.bits.len <= UInt<8>("h00") @[ahb_to_axi4.scala 20:25] - _T.ar.bits.region <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25] - _T.ar.bits.addr <= UInt<32>("h00") @[ahb_to_axi4.scala 20:25] - _T.ar.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.ar.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.ar.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.b.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.b.bits.resp <= UInt<2>("h00") @[ahb_to_axi4.scala 20:25] - _T.b.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.b.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.w.bits.last <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.w.bits.strb <= UInt<8>("h00") @[ahb_to_axi4.scala 20:25] - _T.w.bits.data <= UInt<64>("h00") @[ahb_to_axi4.scala 20:25] - _T.w.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.w.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.aw.bits.qos <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25] - _T.aw.bits.prot <= UInt<3>("h00") @[ahb_to_axi4.scala 20:25] - _T.aw.bits.cache <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25] - _T.aw.bits.lock <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.aw.bits.burst <= UInt<2>("h00") @[ahb_to_axi4.scala 20:25] - _T.aw.bits.size <= UInt<3>("h00") @[ahb_to_axi4.scala 20:25] - _T.aw.bits.len <= UInt<8>("h00") @[ahb_to_axi4.scala 20:25] - _T.aw.bits.region <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25] - _T.aw.bits.addr <= UInt<32>("h00") @[ahb_to_axi4.scala 20:25] - _T.aw.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.aw.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.aw.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.r.bits.last <= io.axi.r.bits.last @[ahb_to_axi4.scala 20:10] - _T.r.bits.resp <= io.axi.r.bits.resp @[ahb_to_axi4.scala 20:10] - _T.r.bits.data <= io.axi.r.bits.data @[ahb_to_axi4.scala 20:10] - _T.r.bits.id <= io.axi.r.bits.id @[ahb_to_axi4.scala 20:10] - _T.r.valid <= io.axi.r.valid @[ahb_to_axi4.scala 20:10] - io.axi.r.ready <= _T.r.ready @[ahb_to_axi4.scala 20:10] - io.axi.ar.bits.qos <= _T.ar.bits.qos @[ahb_to_axi4.scala 20:10] - io.axi.ar.bits.prot <= _T.ar.bits.prot @[ahb_to_axi4.scala 20:10] - io.axi.ar.bits.cache <= _T.ar.bits.cache @[ahb_to_axi4.scala 20:10] - io.axi.ar.bits.lock <= _T.ar.bits.lock @[ahb_to_axi4.scala 20:10] - io.axi.ar.bits.burst <= _T.ar.bits.burst @[ahb_to_axi4.scala 20:10] - io.axi.ar.bits.size <= _T.ar.bits.size @[ahb_to_axi4.scala 20:10] - io.axi.ar.bits.len <= _T.ar.bits.len @[ahb_to_axi4.scala 20:10] - io.axi.ar.bits.region <= _T.ar.bits.region @[ahb_to_axi4.scala 20:10] - io.axi.ar.bits.addr <= _T.ar.bits.addr @[ahb_to_axi4.scala 20:10] - io.axi.ar.bits.id <= _T.ar.bits.id @[ahb_to_axi4.scala 20:10] - io.axi.ar.valid <= _T.ar.valid @[ahb_to_axi4.scala 20:10] - _T.ar.ready <= io.axi.ar.ready @[ahb_to_axi4.scala 20:10] - _T.b.bits.id <= io.axi.b.bits.id @[ahb_to_axi4.scala 20:10] - _T.b.bits.resp <= io.axi.b.bits.resp @[ahb_to_axi4.scala 20:10] - _T.b.valid <= io.axi.b.valid @[ahb_to_axi4.scala 20:10] - io.axi.b.ready <= _T.b.ready @[ahb_to_axi4.scala 20:10] - io.axi.w.bits.last <= _T.w.bits.last @[ahb_to_axi4.scala 20:10] - io.axi.w.bits.strb <= _T.w.bits.strb @[ahb_to_axi4.scala 20:10] - io.axi.w.bits.data <= _T.w.bits.data @[ahb_to_axi4.scala 20:10] - io.axi.w.valid <= _T.w.valid @[ahb_to_axi4.scala 20:10] - _T.w.ready <= io.axi.w.ready @[ahb_to_axi4.scala 20:10] - io.axi.aw.bits.qos <= _T.aw.bits.qos @[ahb_to_axi4.scala 20:10] - io.axi.aw.bits.prot <= _T.aw.bits.prot @[ahb_to_axi4.scala 20:10] - io.axi.aw.bits.cache <= _T.aw.bits.cache @[ahb_to_axi4.scala 20:10] - io.axi.aw.bits.lock <= _T.aw.bits.lock @[ahb_to_axi4.scala 20:10] - io.axi.aw.bits.burst <= _T.aw.bits.burst @[ahb_to_axi4.scala 20:10] - io.axi.aw.bits.size <= _T.aw.bits.size @[ahb_to_axi4.scala 20:10] - io.axi.aw.bits.len <= _T.aw.bits.len @[ahb_to_axi4.scala 20:10] - io.axi.aw.bits.region <= _T.aw.bits.region @[ahb_to_axi4.scala 20:10] - io.axi.aw.bits.addr <= _T.aw.bits.addr @[ahb_to_axi4.scala 20:10] - io.axi.aw.bits.id <= _T.aw.bits.id @[ahb_to_axi4.scala 20:10] - io.axi.aw.valid <= _T.aw.valid @[ahb_to_axi4.scala 20:10] - _T.aw.ready <= io.axi.aw.ready @[ahb_to_axi4.scala 20:10] - wire master_wstrb : UInt<8> - master_wstrb <= UInt<8>("h00") - wire buf_state_en : UInt<1> - buf_state_en <= UInt<1>("h00") - wire buf_read_error_in : UInt<1> - buf_read_error_in <= UInt<1>("h00") - wire buf_read_error : UInt<1> - buf_read_error <= UInt<1>("h00") - wire buf_rdata : UInt<64> - buf_rdata <= UInt<64>("h00") - wire ahb_hready : UInt<1> - ahb_hready <= UInt<1>("h00") - wire ahb_hready_q : UInt<1> - ahb_hready_q <= UInt<1>("h00") - wire ahb_htrans_in : UInt<2> - ahb_htrans_in <= UInt<2>("h00") - wire ahb_htrans_q : UInt<2> - ahb_htrans_q <= UInt<2>("h00") - wire ahb_hsize_q : UInt<3> - ahb_hsize_q <= UInt<3>("h00") - wire ahb_hwrite_q : UInt<1> - ahb_hwrite_q <= UInt<1>("h00") - wire ahb_haddr_q : UInt<32> - ahb_haddr_q <= UInt<32>("h00") - wire ahb_hwdata_q : UInt<64> - ahb_hwdata_q <= UInt<64>("h00") - wire ahb_hresp_q : UInt<1> - ahb_hresp_q <= UInt<1>("h00") - wire buf_rdata_en : UInt<1> - buf_rdata_en <= UInt<1>("h00") - wire ahb_bus_addr_clk_en : UInt<1> - ahb_bus_addr_clk_en <= UInt<1>("h00") - wire buf_rdata_clk_en : UInt<1> - buf_rdata_clk_en <= UInt<1>("h00") - wire ahb_clk : Clock @[ahb_to_axi4.scala 43:33] - wire ahb_addr_clk : Clock @[ahb_to_axi4.scala 44:33] - wire buf_rdata_clk : Clock @[ahb_to_axi4.scala 45:33] - wire cmdbuf_wr_en : UInt<1> - cmdbuf_wr_en <= UInt<1>("h00") - wire cmdbuf_rst : UInt<1> - cmdbuf_rst <= UInt<1>("h00") - wire cmdbuf_full : UInt<1> - cmdbuf_full <= UInt<1>("h00") - wire cmdbuf_vld : UInt<1> - cmdbuf_vld <= UInt<1>("h00") - wire cmdbuf_write : UInt<1> - cmdbuf_write <= UInt<1>("h00") - wire cmdbuf_size : UInt<2> - cmdbuf_size <= UInt<2>("h00") - wire cmdbuf_wstrb : UInt<8> - cmdbuf_wstrb <= UInt<8>("h00") - wire cmdbuf_addr : UInt<32> - cmdbuf_addr <= UInt<32>("h00") - wire cmdbuf_wdata : UInt<64> - cmdbuf_wdata <= UInt<64>("h00") - wire bus_clk : Clock @[ahb_to_axi4.scala 57:33] - node _T_1 = bits(ahb_haddr_q, 31, 28) @[lib.scala 84:25] - node ahb_addr_in_dccm_region_nc = eq(_T_1, UInt<4>("h0f")) @[lib.scala 84:47] - node _T_2 = bits(ahb_haddr_q, 31, 16) @[lib.scala 87:14] - node ahb_addr_in_dccm = eq(_T_2, UInt<16>("h0f004")) @[lib.scala 87:29] - node _T_3 = bits(ahb_haddr_q, 31, 28) @[lib.scala 84:25] - node ahb_addr_in_iccm_region_nc = eq(_T_3, UInt<4>("h0e")) @[lib.scala 84:47] - node _T_4 = bits(ahb_haddr_q, 31, 16) @[lib.scala 87:14] - node ahb_addr_in_iccm = eq(_T_4, UInt<16>("h0ee00")) @[lib.scala 87:29] - node _T_5 = bits(ahb_haddr_q, 31, 28) @[lib.scala 84:25] - node ahb_addr_in_pic_region_nc = eq(_T_5, UInt<4>("h0f")) @[lib.scala 84:47] - node _T_6 = bits(ahb_haddr_q, 31, 15) @[lib.scala 87:14] - node ahb_addr_in_pic = eq(_T_6, UInt<17>("h01e018")) @[lib.scala 87:29] - wire buf_state : UInt<2> - buf_state <= UInt<2>("h00") - wire buf_nxtstate : UInt<2> - buf_nxtstate <= UInt<2>("h00") - buf_nxtstate <= UInt<2>("h00") @[ahb_to_axi4.scala 67:31] - buf_state_en <= UInt<1>("h00") @[ahb_to_axi4.scala 68:31] - buf_rdata_en <= UInt<1>("h00") @[ahb_to_axi4.scala 69:31] - buf_read_error_in <= UInt<1>("h00") @[ahb_to_axi4.scala 70:31] - cmdbuf_wr_en <= UInt<1>("h00") @[ahb_to_axi4.scala 71:31] - node _T_7 = eq(UInt<2>("h00"), buf_state) @[Conditional.scala 37:30] - when _T_7 : @[Conditional.scala 40:58] - node _T_8 = mux(io.ahb.sig.out.hwrite, UInt<2>("h01"), UInt<2>("h02")) @[ahb_to_axi4.scala 75:26] - buf_nxtstate <= _T_8 @[ahb_to_axi4.scala 75:20] - node _T_9 = bits(io.ahb.sig.out.htrans, 1, 1) @[ahb_to_axi4.scala 76:57] - node _T_10 = and(ahb_hready, _T_9) @[ahb_to_axi4.scala 76:34] - node _T_11 = and(_T_10, io.ahb.hsel) @[ahb_to_axi4.scala 76:61] - buf_state_en <= _T_11 @[ahb_to_axi4.scala 76:20] - skip @[Conditional.scala 40:58] - else : @[Conditional.scala 39:67] - node _T_12 = eq(UInt<2>("h01"), buf_state) @[Conditional.scala 37:30] - when _T_12 : @[Conditional.scala 39:67] - node _T_13 = bits(io.ahb.sig.out.htrans, 1, 0) @[ahb_to_axi4.scala 79:72] - node _T_14 = eq(_T_13, UInt<1>("h00")) @[ahb_to_axi4.scala 79:79] - node _T_15 = or(io.ahb.sig.in.hresp, _T_14) @[ahb_to_axi4.scala 79:48] - node _T_16 = eq(io.ahb.hsel, UInt<1>("h00")) @[ahb_to_axi4.scala 79:93] - node _T_17 = or(_T_15, _T_16) @[ahb_to_axi4.scala 79:91] - node _T_18 = bits(_T_17, 0, 0) @[ahb_to_axi4.scala 79:107] - node _T_19 = mux(io.ahb.sig.out.hwrite, UInt<2>("h01"), UInt<2>("h02")) @[ahb_to_axi4.scala 79:124] - node _T_20 = mux(_T_18, UInt<2>("h00"), _T_19) @[ahb_to_axi4.scala 79:26] - buf_nxtstate <= _T_20 @[ahb_to_axi4.scala 79:20] - node _T_21 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 80:24] - node _T_22 = or(_T_21, io.ahb.sig.in.hresp) @[ahb_to_axi4.scala 80:37] - buf_state_en <= _T_22 @[ahb_to_axi4.scala 80:20] - node _T_23 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 81:23] - node _T_24 = bits(io.ahb.sig.out.htrans, 1, 0) @[ahb_to_axi4.scala 81:85] - node _T_25 = eq(_T_24, UInt<2>("h01")) @[ahb_to_axi4.scala 81:92] - node _T_26 = and(_T_25, io.ahb.hsel) @[ahb_to_axi4.scala 81:110] - node _T_27 = or(io.ahb.sig.in.hresp, _T_26) @[ahb_to_axi4.scala 81:60] - node _T_28 = eq(_T_27, UInt<1>("h00")) @[ahb_to_axi4.scala 81:38] - node _T_29 = and(_T_23, _T_28) @[ahb_to_axi4.scala 81:36] - cmdbuf_wr_en <= _T_29 @[ahb_to_axi4.scala 81:20] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_30 = eq(UInt<2>("h02"), buf_state) @[Conditional.scala 37:30] - when _T_30 : @[Conditional.scala 39:67] - node _T_31 = mux(io.ahb.sig.in.hresp, UInt<2>("h00"), UInt<2>("h03")) @[ahb_to_axi4.scala 84:26] - buf_nxtstate <= _T_31 @[ahb_to_axi4.scala 84:20] - node _T_32 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 85:24] - node _T_33 = or(_T_32, io.ahb.sig.in.hresp) @[ahb_to_axi4.scala 85:37] - buf_state_en <= _T_33 @[ahb_to_axi4.scala 85:20] - node _T_34 = eq(io.ahb.sig.in.hresp, UInt<1>("h00")) @[ahb_to_axi4.scala 86:23] - node _T_35 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 86:46] - node _T_36 = and(_T_34, _T_35) @[ahb_to_axi4.scala 86:44] - cmdbuf_wr_en <= _T_36 @[ahb_to_axi4.scala 86:20] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_37 = eq(UInt<2>("h03"), buf_state) @[Conditional.scala 37:30] - when _T_37 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<2>("h00") @[ahb_to_axi4.scala 89:20] - node _T_38 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 90:40] - node _T_39 = and(io.axi.r.valid, _T_38) @[ahb_to_axi4.scala 90:38] - buf_state_en <= _T_39 @[ahb_to_axi4.scala 90:20] - buf_rdata_en <= buf_state_en @[ahb_to_axi4.scala 91:20] - node _T_40 = bits(io.axi.r.bits.resp, 1, 0) @[ahb_to_axi4.scala 92:61] - node _T_41 = orr(_T_40) @[ahb_to_axi4.scala 92:68] - node _T_42 = and(buf_state_en, _T_41) @[ahb_to_axi4.scala 92:41] - buf_read_error_in <= _T_42 @[ahb_to_axi4.scala 92:25] - skip @[Conditional.scala 39:67] - node _T_43 = bits(buf_state_en, 0, 0) @[ahb_to_axi4.scala 95:99] - reg _T_44 : UInt, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_43 : @[Reg.scala 28:19] - _T_44 <= buf_nxtstate @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_state <= _T_44 @[ahb_to_axi4.scala 95:31] - node _T_45 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 97:54] - node _T_46 = eq(_T_45, UInt<1>("h00")) @[ahb_to_axi4.scala 97:60] - node _T_47 = bits(_T_46, 0, 0) @[Bitwise.scala 72:15] - node _T_48 = mux(_T_47, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_49 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 97:92] - node _T_50 = dshl(UInt<1>("h01"), _T_49) @[ahb_to_axi4.scala 97:78] - node _T_51 = and(_T_48, _T_50) @[ahb_to_axi4.scala 97:70] - node _T_52 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 98:24] - node _T_53 = eq(_T_52, UInt<1>("h01")) @[ahb_to_axi4.scala 98:30] - node _T_54 = bits(_T_53, 0, 0) @[Bitwise.scala 72:15] - node _T_55 = mux(_T_54, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_56 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 98:62] - node _T_57 = dshl(UInt<2>("h03"), _T_56) @[ahb_to_axi4.scala 98:48] - node _T_58 = and(_T_55, _T_57) @[ahb_to_axi4.scala 98:40] - node _T_59 = or(_T_51, _T_58) @[ahb_to_axi4.scala 97:109] - node _T_60 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 99:24] - node _T_61 = eq(_T_60, UInt<2>("h02")) @[ahb_to_axi4.scala 99:30] - node _T_62 = bits(_T_61, 0, 0) @[Bitwise.scala 72:15] - node _T_63 = mux(_T_62, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_64 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 99:62] - node _T_65 = dshl(UInt<4>("h0f"), _T_64) @[ahb_to_axi4.scala 99:48] - node _T_66 = and(_T_63, _T_65) @[ahb_to_axi4.scala 99:40] - node _T_67 = or(_T_59, _T_66) @[ahb_to_axi4.scala 98:79] - node _T_68 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 100:24] - node _T_69 = eq(_T_68, UInt<2>("h03")) @[ahb_to_axi4.scala 100:30] - node _T_70 = bits(_T_69, 0, 0) @[Bitwise.scala 72:15] - node _T_71 = mux(_T_70, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_72 = and(_T_71, UInt<8>("h0ff")) @[ahb_to_axi4.scala 100:40] - node _T_73 = or(_T_67, _T_72) @[ahb_to_axi4.scala 99:79] - master_wstrb <= _T_73 @[ahb_to_axi4.scala 97:31] - node _T_74 = eq(ahb_hready_q, UInt<1>("h00")) @[ahb_to_axi4.scala 103:80] - node _T_75 = and(ahb_hresp_q, _T_74) @[ahb_to_axi4.scala 103:78] - node _T_76 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 103:98] - node _T_77 = eq(buf_state, UInt<2>("h00")) @[ahb_to_axi4.scala 103:124] - node _T_78 = or(_T_76, _T_77) @[ahb_to_axi4.scala 103:111] - node _T_79 = eq(buf_state, UInt<2>("h02")) @[ahb_to_axi4.scala 103:149] - node _T_80 = eq(buf_state, UInt<2>("h03")) @[ahb_to_axi4.scala 103:168] - node _T_81 = or(_T_79, _T_80) @[ahb_to_axi4.scala 103:156] - node _T_82 = eq(_T_81, UInt<1>("h00")) @[ahb_to_axi4.scala 103:137] - node _T_83 = and(_T_78, _T_82) @[ahb_to_axi4.scala 103:135] - node _T_84 = eq(buf_read_error, UInt<1>("h00")) @[ahb_to_axi4.scala 103:181] - node _T_85 = and(_T_83, _T_84) @[ahb_to_axi4.scala 103:179] - node _T_86 = mux(io.ahb.sig.in.hresp, _T_75, _T_85) @[ahb_to_axi4.scala 103:44] - io.ahb.sig.in.hready <= _T_86 @[ahb_to_axi4.scala 103:38] - node _T_87 = and(io.ahb.sig.in.hready, io.ahb.hreadyin) @[ahb_to_axi4.scala 104:55] - ahb_hready <= _T_87 @[ahb_to_axi4.scala 104:31] - node _T_88 = bits(io.ahb.hsel, 0, 0) @[Bitwise.scala 72:15] - node _T_89 = mux(_T_88, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_90 = bits(io.ahb.sig.out.htrans, 1, 0) @[ahb_to_axi4.scala 105:77] - node _T_91 = and(_T_89, _T_90) @[ahb_to_axi4.scala 105:54] - ahb_htrans_in <= _T_91 @[ahb_to_axi4.scala 105:31] - node _T_92 = bits(buf_rdata, 63, 0) @[ahb_to_axi4.scala 106:50] - io.ahb.sig.in.hrdata <= _T_92 @[ahb_to_axi4.scala 106:38] - node _T_93 = bits(ahb_htrans_q, 1, 0) @[ahb_to_axi4.scala 107:55] - node _T_94 = neq(_T_93, UInt<1>("h00")) @[ahb_to_axi4.scala 107:61] - node _T_95 = neq(buf_state, UInt<2>("h00")) @[ahb_to_axi4.scala 107:83] - node _T_96 = and(_T_94, _T_95) @[ahb_to_axi4.scala 107:70] - node _T_97 = or(ahb_addr_in_dccm, ahb_addr_in_iccm) @[ahb_to_axi4.scala 108:26] - node _T_98 = eq(_T_97, UInt<1>("h00")) @[ahb_to_axi4.scala 108:7] - node _T_99 = and(ahb_addr_in_dccm, ahb_hwrite_q) @[ahb_to_axi4.scala 109:46] - node _T_100 = or(ahb_addr_in_iccm, _T_99) @[ahb_to_axi4.scala 109:26] - node _T_101 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 109:80] - node _T_102 = eq(_T_101, UInt<2>("h02")) @[ahb_to_axi4.scala 109:86] - node _T_103 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 109:109] - node _T_104 = eq(_T_103, UInt<2>("h03")) @[ahb_to_axi4.scala 109:115] - node _T_105 = or(_T_102, _T_104) @[ahb_to_axi4.scala 109:95] - node _T_106 = eq(_T_105, UInt<1>("h00")) @[ahb_to_axi4.scala 109:66] - node _T_107 = and(_T_100, _T_106) @[ahb_to_axi4.scala 109:64] - node _T_108 = or(_T_98, _T_107) @[ahb_to_axi4.scala 108:47] - node _T_109 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 110:20] - node _T_110 = eq(_T_109, UInt<1>("h01")) @[ahb_to_axi4.scala 110:26] - node _T_111 = bits(ahb_haddr_q, 0, 0) @[ahb_to_axi4.scala 110:48] - node _T_112 = and(_T_110, _T_111) @[ahb_to_axi4.scala 110:35] - node _T_113 = or(_T_108, _T_112) @[ahb_to_axi4.scala 109:126] - node _T_114 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 111:20] - node _T_115 = eq(_T_114, UInt<2>("h02")) @[ahb_to_axi4.scala 111:26] - node _T_116 = bits(ahb_haddr_q, 1, 0) @[ahb_to_axi4.scala 111:49] - node _T_117 = orr(_T_116) @[ahb_to_axi4.scala 111:56] - node _T_118 = and(_T_115, _T_117) @[ahb_to_axi4.scala 111:35] - node _T_119 = or(_T_113, _T_118) @[ahb_to_axi4.scala 110:55] - node _T_120 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 112:20] - node _T_121 = eq(_T_120, UInt<2>("h03")) @[ahb_to_axi4.scala 112:26] - node _T_122 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 112:49] - node _T_123 = orr(_T_122) @[ahb_to_axi4.scala 112:56] - node _T_124 = and(_T_121, _T_123) @[ahb_to_axi4.scala 112:35] - node _T_125 = or(_T_119, _T_124) @[ahb_to_axi4.scala 111:61] - node _T_126 = and(_T_96, _T_125) @[ahb_to_axi4.scala 107:94] - node _T_127 = or(_T_126, buf_read_error) @[ahb_to_axi4.scala 112:63] - node _T_128 = eq(ahb_hready_q, UInt<1>("h00")) @[ahb_to_axi4.scala 114:20] - node _T_129 = and(ahb_hresp_q, _T_128) @[ahb_to_axi4.scala 114:18] - node _T_130 = or(_T_127, _T_129) @[ahb_to_axi4.scala 113:20] - io.ahb.sig.in.hresp <= _T_130 @[ahb_to_axi4.scala 107:38] - reg _T_131 : UInt, buf_rdata_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 117:66] - _T_131 <= io.axi.r.bits.data @[ahb_to_axi4.scala 117:66] - buf_rdata <= _T_131 @[ahb_to_axi4.scala 117:31] - reg _T_132 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 118:60] - _T_132 <= buf_read_error_in @[ahb_to_axi4.scala 118:60] - buf_read_error <= _T_132 @[ahb_to_axi4.scala 118:31] - reg _T_133 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 121:60] - _T_133 <= io.ahb.sig.in.hresp @[ahb_to_axi4.scala 121:60] - ahb_hresp_q <= _T_133 @[ahb_to_axi4.scala 121:31] - reg _T_134 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 122:60] - _T_134 <= ahb_hready @[ahb_to_axi4.scala 122:60] - ahb_hready_q <= _T_134 @[ahb_to_axi4.scala 122:31] - reg _T_135 : UInt, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 123:60] - _T_135 <= ahb_htrans_in @[ahb_to_axi4.scala 123:60] - ahb_htrans_q <= _T_135 @[ahb_to_axi4.scala 123:31] - reg _T_136 : UInt, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 124:65] - _T_136 <= io.ahb.sig.out.hsize @[ahb_to_axi4.scala 124:65] - ahb_hsize_q <= _T_136 @[ahb_to_axi4.scala 124:31] - reg _T_137 : UInt<1>, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 125:65] - _T_137 <= io.ahb.sig.out.hwrite @[ahb_to_axi4.scala 125:65] - ahb_hwrite_q <= _T_137 @[ahb_to_axi4.scala 125:31] - reg _T_138 : UInt, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 126:65] - _T_138 <= io.ahb.sig.out.haddr @[ahb_to_axi4.scala 126:65] - ahb_haddr_q <= _T_138 @[ahb_to_axi4.scala 126:31] - node _T_139 = bits(io.ahb.sig.out.htrans, 1, 1) @[ahb_to_axi4.scala 129:85] - node _T_140 = and(ahb_hready, _T_139) @[ahb_to_axi4.scala 129:62] - node _T_141 = and(io.bus_clk_en, _T_140) @[ahb_to_axi4.scala 129:48] - ahb_bus_addr_clk_en <= _T_141 @[ahb_to_axi4.scala 129:31] - node _T_142 = and(io.bus_clk_en, buf_rdata_en) @[ahb_to_axi4.scala 130:48] - buf_rdata_clk_en <= _T_142 @[ahb_to_axi4.scala 130:31] - inst rvclkhdr of rvclkhdr_879 @[lib.scala 343:22] - rvclkhdr.clock <= clock - rvclkhdr.reset <= reset - rvclkhdr.io.clk <= clock @[lib.scala 344:17] - rvclkhdr.io.en <= io.bus_clk_en @[lib.scala 345:16] - rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahb_clk <= rvclkhdr.io.l1clk @[ahb_to_axi4.scala 132:31] - inst rvclkhdr_1 of rvclkhdr_880 @[lib.scala 343:22] - rvclkhdr_1.clock <= clock - rvclkhdr_1.reset <= reset - rvclkhdr_1.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_1.io.en <= ahb_bus_addr_clk_en @[lib.scala 345:16] - rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahb_addr_clk <= rvclkhdr_1.io.l1clk @[ahb_to_axi4.scala 133:31] - inst rvclkhdr_2 of rvclkhdr_881 @[lib.scala 343:22] - rvclkhdr_2.clock <= clock - rvclkhdr_2.reset <= reset - rvclkhdr_2.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_2.io.en <= buf_rdata_clk_en @[lib.scala 345:16] - rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - buf_rdata_clk <= rvclkhdr_2.io.l1clk @[ahb_to_axi4.scala 134:31] - node _T_143 = and(io.axi.aw.valid, io.axi.aw.ready) @[ahb_to_axi4.scala 136:53] - node _T_144 = and(io.axi.ar.valid, io.axi.ar.ready) @[ahb_to_axi4.scala 136:91] - node _T_145 = or(_T_143, _T_144) @[ahb_to_axi4.scala 136:72] - node _T_146 = eq(cmdbuf_wr_en, UInt<1>("h00")) @[ahb_to_axi4.scala 136:113] - node _T_147 = and(_T_145, _T_146) @[ahb_to_axi4.scala 136:111] - node _T_148 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 136:153] - node _T_149 = and(io.ahb.sig.in.hresp, _T_148) @[ahb_to_axi4.scala 136:151] - node _T_150 = or(_T_147, _T_149) @[ahb_to_axi4.scala 136:128] - cmdbuf_rst <= _T_150 @[ahb_to_axi4.scala 136:31] - node _T_151 = and(io.axi.aw.valid, io.axi.aw.ready) @[ahb_to_axi4.scala 137:67] - node _T_152 = and(io.axi.ar.valid, io.axi.ar.ready) @[ahb_to_axi4.scala 137:105] - node _T_153 = or(_T_151, _T_152) @[ahb_to_axi4.scala 137:86] - node _T_154 = eq(_T_153, UInt<1>("h00")) @[ahb_to_axi4.scala 137:48] - node _T_155 = and(cmdbuf_vld, _T_154) @[ahb_to_axi4.scala 137:46] - cmdbuf_full <= _T_155 @[ahb_to_axi4.scala 137:31] - node _T_156 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 139:86] - node _T_157 = mux(_T_156, UInt<1>("h01"), cmdbuf_vld) @[ahb_to_axi4.scala 139:66] - node _T_158 = eq(cmdbuf_rst, UInt<1>("h00")) @[ahb_to_axi4.scala 139:110] - node _T_159 = and(_T_157, _T_158) @[ahb_to_axi4.scala 139:108] - reg _T_160 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 139:61] - _T_160 <= _T_159 @[ahb_to_axi4.scala 139:61] - cmdbuf_vld <= _T_160 @[ahb_to_axi4.scala 139:31] - node _T_161 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 143:53] - reg _T_162 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_161 : @[Reg.scala 28:19] - _T_162 <= ahb_hwrite_q @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - cmdbuf_write <= _T_162 @[ahb_to_axi4.scala 142:31] - node _T_163 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 146:52] - reg _T_164 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_163 : @[Reg.scala 28:19] - _T_164 <= ahb_hsize_q @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - cmdbuf_size <= _T_164 @[ahb_to_axi4.scala 145:31] - node _T_165 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 149:53] - reg _T_166 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_165 : @[Reg.scala 28:19] - _T_166 <= master_wstrb @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - cmdbuf_wstrb <= _T_166 @[ahb_to_axi4.scala 148:31] - node _T_167 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 152:57] - inst rvclkhdr_3 of rvclkhdr_882 @[lib.scala 368:23] - rvclkhdr_3.clock <= clock - rvclkhdr_3.reset <= reset - rvclkhdr_3.io.clk <= bus_clk @[lib.scala 370:18] - rvclkhdr_3.io.en <= _T_167 @[lib.scala 371:17] - rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_168 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_168 <= ahb_haddr_q @[lib.scala 374:16] - cmdbuf_addr <= _T_168 @[ahb_to_axi4.scala 152:15] - node _T_169 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 153:68] - inst rvclkhdr_4 of rvclkhdr_883 @[lib.scala 368:23] - rvclkhdr_4.clock <= clock - rvclkhdr_4.reset <= reset - rvclkhdr_4.io.clk <= bus_clk @[lib.scala 370:18] - rvclkhdr_4.io.en <= _T_169 @[lib.scala 371:17] - rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_170 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_170 <= io.ahb.sig.out.hwdata @[lib.scala 374:16] - cmdbuf_wdata <= _T_170 @[ahb_to_axi4.scala 153:16] - node _T_171 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 156:42] - io.axi.aw.valid <= _T_171 @[ahb_to_axi4.scala 156:28] - io.axi.aw.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 157:33] - io.axi.aw.bits.addr <= cmdbuf_addr @[ahb_to_axi4.scala 158:33] - node _T_172 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 159:59] - node _T_173 = cat(UInt<1>("h00"), _T_172) @[Cat.scala 29:58] - io.axi.aw.bits.size <= _T_173 @[ahb_to_axi4.scala 159:33] - node _T_174 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - io.axi.aw.bits.prot <= _T_174 @[ahb_to_axi4.scala 160:33] - node _T_175 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - io.axi.aw.bits.len <= _T_175 @[ahb_to_axi4.scala 161:33] - io.axi.aw.bits.burst <= UInt<1>("h01") @[ahb_to_axi4.scala 162:33] - node _T_176 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 164:42] - io.axi.w.valid <= _T_176 @[ahb_to_axi4.scala 164:28] - io.axi.w.bits.data <= cmdbuf_wdata @[ahb_to_axi4.scala 165:33] - io.axi.w.bits.strb <= cmdbuf_wstrb @[ahb_to_axi4.scala 166:33] - io.axi.w.bits.last <= UInt<1>("h01") @[ahb_to_axi4.scala 167:33] - io.axi.b.ready <= UInt<1>("h01") @[ahb_to_axi4.scala 169:28] - node _T_177 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 171:44] - node _T_178 = and(cmdbuf_vld, _T_177) @[ahb_to_axi4.scala 171:42] - io.axi.ar.valid <= _T_178 @[ahb_to_axi4.scala 171:28] - io.axi.ar.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 172:33] - io.axi.ar.bits.addr <= cmdbuf_addr @[ahb_to_axi4.scala 173:33] - node _T_179 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 174:59] - node _T_180 = cat(UInt<1>("h00"), _T_179) @[Cat.scala 29:58] - io.axi.ar.bits.size <= _T_180 @[ahb_to_axi4.scala 174:33] - node _T_181 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - io.axi.ar.bits.prot <= _T_181 @[ahb_to_axi4.scala 175:33] - node _T_182 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - io.axi.ar.bits.len <= _T_182 @[ahb_to_axi4.scala 176:33] - io.axi.ar.bits.burst <= UInt<1>("h01") @[ahb_to_axi4.scala 177:33] - io.axi.r.ready <= UInt<1>("h01") @[ahb_to_axi4.scala 179:28] - inst rvclkhdr_5 of rvclkhdr_884 @[lib.scala 343:22] - rvclkhdr_5.clock <= clock - rvclkhdr_5.reset <= reset - rvclkhdr_5.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_5.io.en <= io.bus_clk_en @[lib.scala 345:16] - rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - bus_clk <= rvclkhdr_5.io.l1clk @[ahb_to_axi4.scala 180:27] - module quasar : input clock : Clock input reset : AsyncReset @@ -114308,547 +109493,256 @@ circuit quasar : io.dccm.wr_addr_lo <= lsu.io.dccm.wr_addr_lo @[quasar.scala 238:11] io.dccm.rden <= lsu.io.dccm.rden @[quasar.scala 238:11] io.dccm.wren <= lsu.io.dccm.wren @[quasar.scala 238:11] - inst axi4_to_ahb of axi4_to_ahb @[quasar.scala 241:32] - axi4_to_ahb.clock <= clock - axi4_to_ahb.reset <= reset - inst axi4_to_ahb_1 of axi4_to_ahb_1 @[quasar.scala 242:33] - axi4_to_ahb_1.clock <= clock - axi4_to_ahb_1.reset <= reset - inst axi4_to_ahb_2 of axi4_to_ahb_2 @[quasar.scala 243:33] - axi4_to_ahb_2.clock <= clock - axi4_to_ahb_2.reset <= reset - inst ahb_to_axi4 of ahb_to_axi4 @[quasar.scala 244:33] - ahb_to_axi4.clock <= clock - ahb_to_axi4.reset <= reset - axi4_to_ahb_2.io.scan_mode <= io.scan_mode @[quasar.scala 246:34] - axi4_to_ahb_2.io.bus_clk_en <= io.lsu_bus_clk_en @[quasar.scala 247:35] - axi4_to_ahb_2.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 248:37] - lsu.io.axi.r.bits.last <= axi4_to_ahb_2.io.axi.r.bits.last @[quasar.scala 249:28] - lsu.io.axi.r.bits.resp <= axi4_to_ahb_2.io.axi.r.bits.resp @[quasar.scala 249:28] - lsu.io.axi.r.bits.data <= axi4_to_ahb_2.io.axi.r.bits.data @[quasar.scala 249:28] - lsu.io.axi.r.bits.id <= axi4_to_ahb_2.io.axi.r.bits.id @[quasar.scala 249:28] - lsu.io.axi.r.valid <= axi4_to_ahb_2.io.axi.r.valid @[quasar.scala 249:28] - axi4_to_ahb_2.io.axi.r.ready <= lsu.io.axi.r.ready @[quasar.scala 249:28] - axi4_to_ahb_2.io.axi.ar.bits.qos <= lsu.io.axi.ar.bits.qos @[quasar.scala 249:28] - axi4_to_ahb_2.io.axi.ar.bits.prot <= lsu.io.axi.ar.bits.prot @[quasar.scala 249:28] - axi4_to_ahb_2.io.axi.ar.bits.cache <= lsu.io.axi.ar.bits.cache @[quasar.scala 249:28] - axi4_to_ahb_2.io.axi.ar.bits.lock <= lsu.io.axi.ar.bits.lock @[quasar.scala 249:28] - axi4_to_ahb_2.io.axi.ar.bits.burst <= lsu.io.axi.ar.bits.burst @[quasar.scala 249:28] - axi4_to_ahb_2.io.axi.ar.bits.size <= lsu.io.axi.ar.bits.size @[quasar.scala 249:28] - axi4_to_ahb_2.io.axi.ar.bits.len <= lsu.io.axi.ar.bits.len @[quasar.scala 249:28] - axi4_to_ahb_2.io.axi.ar.bits.region <= lsu.io.axi.ar.bits.region @[quasar.scala 249:28] - axi4_to_ahb_2.io.axi.ar.bits.addr <= lsu.io.axi.ar.bits.addr @[quasar.scala 249:28] - axi4_to_ahb_2.io.axi.ar.bits.id <= lsu.io.axi.ar.bits.id @[quasar.scala 249:28] - axi4_to_ahb_2.io.axi.ar.valid <= lsu.io.axi.ar.valid @[quasar.scala 249:28] - lsu.io.axi.ar.ready <= axi4_to_ahb_2.io.axi.ar.ready @[quasar.scala 249:28] - lsu.io.axi.b.bits.id <= axi4_to_ahb_2.io.axi.b.bits.id @[quasar.scala 249:28] - lsu.io.axi.b.bits.resp <= axi4_to_ahb_2.io.axi.b.bits.resp @[quasar.scala 249:28] - lsu.io.axi.b.valid <= axi4_to_ahb_2.io.axi.b.valid @[quasar.scala 249:28] - axi4_to_ahb_2.io.axi.b.ready <= lsu.io.axi.b.ready @[quasar.scala 249:28] - axi4_to_ahb_2.io.axi.w.bits.last <= lsu.io.axi.w.bits.last @[quasar.scala 249:28] - axi4_to_ahb_2.io.axi.w.bits.strb <= lsu.io.axi.w.bits.strb @[quasar.scala 249:28] - axi4_to_ahb_2.io.axi.w.bits.data <= lsu.io.axi.w.bits.data @[quasar.scala 249:28] - axi4_to_ahb_2.io.axi.w.valid <= lsu.io.axi.w.valid @[quasar.scala 249:28] - lsu.io.axi.w.ready <= axi4_to_ahb_2.io.axi.w.ready @[quasar.scala 249:28] - axi4_to_ahb_2.io.axi.aw.bits.qos <= lsu.io.axi.aw.bits.qos @[quasar.scala 249:28] - axi4_to_ahb_2.io.axi.aw.bits.prot <= lsu.io.axi.aw.bits.prot @[quasar.scala 249:28] - axi4_to_ahb_2.io.axi.aw.bits.cache <= lsu.io.axi.aw.bits.cache @[quasar.scala 249:28] - axi4_to_ahb_2.io.axi.aw.bits.lock <= lsu.io.axi.aw.bits.lock @[quasar.scala 249:28] - axi4_to_ahb_2.io.axi.aw.bits.burst <= lsu.io.axi.aw.bits.burst @[quasar.scala 249:28] - axi4_to_ahb_2.io.axi.aw.bits.size <= lsu.io.axi.aw.bits.size @[quasar.scala 249:28] - axi4_to_ahb_2.io.axi.aw.bits.len <= lsu.io.axi.aw.bits.len @[quasar.scala 249:28] - axi4_to_ahb_2.io.axi.aw.bits.region <= lsu.io.axi.aw.bits.region @[quasar.scala 249:28] - axi4_to_ahb_2.io.axi.aw.bits.addr <= lsu.io.axi.aw.bits.addr @[quasar.scala 249:28] - axi4_to_ahb_2.io.axi.aw.bits.id <= lsu.io.axi.aw.bits.id @[quasar.scala 249:28] - axi4_to_ahb_2.io.axi.aw.valid <= lsu.io.axi.aw.valid @[quasar.scala 249:28] - lsu.io.axi.aw.ready <= axi4_to_ahb_2.io.axi.aw.ready @[quasar.scala 249:28] - io.lsu_ahb.out.hwdata <= axi4_to_ahb_2.io.ahb.out.hwdata @[quasar.scala 250:28] - io.lsu_ahb.out.hwrite <= axi4_to_ahb_2.io.ahb.out.hwrite @[quasar.scala 250:28] - io.lsu_ahb.out.htrans <= axi4_to_ahb_2.io.ahb.out.htrans @[quasar.scala 250:28] - io.lsu_ahb.out.hsize <= axi4_to_ahb_2.io.ahb.out.hsize @[quasar.scala 250:28] - io.lsu_ahb.out.hprot <= axi4_to_ahb_2.io.ahb.out.hprot @[quasar.scala 250:28] - io.lsu_ahb.out.hmastlock <= axi4_to_ahb_2.io.ahb.out.hmastlock @[quasar.scala 250:28] - io.lsu_ahb.out.hburst <= axi4_to_ahb_2.io.ahb.out.hburst @[quasar.scala 250:28] - io.lsu_ahb.out.haddr <= axi4_to_ahb_2.io.ahb.out.haddr @[quasar.scala 250:28] - axi4_to_ahb_2.io.ahb.in.hresp <= io.lsu_ahb.in.hresp @[quasar.scala 250:28] - axi4_to_ahb_2.io.ahb.in.hready <= io.lsu_ahb.in.hready @[quasar.scala 250:28] - axi4_to_ahb_2.io.ahb.in.hrdata <= io.lsu_ahb.in.hrdata @[quasar.scala 250:28] - axi4_to_ahb_1.io.scan_mode <= io.scan_mode @[quasar.scala 252:34] - axi4_to_ahb_1.io.bus_clk_en <= io.ifu_bus_clk_en @[quasar.scala 253:35] - axi4_to_ahb_1.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 254:37] - ifu.io.ifu.r.bits.last <= axi4_to_ahb_1.io.axi.r.bits.last @[quasar.scala 255:28] - ifu.io.ifu.r.bits.resp <= axi4_to_ahb_1.io.axi.r.bits.resp @[quasar.scala 255:28] - ifu.io.ifu.r.bits.data <= axi4_to_ahb_1.io.axi.r.bits.data @[quasar.scala 255:28] - ifu.io.ifu.r.bits.id <= axi4_to_ahb_1.io.axi.r.bits.id @[quasar.scala 255:28] - ifu.io.ifu.r.valid <= axi4_to_ahb_1.io.axi.r.valid @[quasar.scala 255:28] - axi4_to_ahb_1.io.axi.r.ready <= ifu.io.ifu.r.ready @[quasar.scala 255:28] - axi4_to_ahb_1.io.axi.ar.bits.qos <= ifu.io.ifu.ar.bits.qos @[quasar.scala 255:28] - axi4_to_ahb_1.io.axi.ar.bits.prot <= ifu.io.ifu.ar.bits.prot @[quasar.scala 255:28] - axi4_to_ahb_1.io.axi.ar.bits.cache <= ifu.io.ifu.ar.bits.cache @[quasar.scala 255:28] - axi4_to_ahb_1.io.axi.ar.bits.lock <= ifu.io.ifu.ar.bits.lock @[quasar.scala 255:28] - axi4_to_ahb_1.io.axi.ar.bits.burst <= ifu.io.ifu.ar.bits.burst @[quasar.scala 255:28] - axi4_to_ahb_1.io.axi.ar.bits.size <= ifu.io.ifu.ar.bits.size @[quasar.scala 255:28] - axi4_to_ahb_1.io.axi.ar.bits.len <= ifu.io.ifu.ar.bits.len @[quasar.scala 255:28] - axi4_to_ahb_1.io.axi.ar.bits.region <= ifu.io.ifu.ar.bits.region @[quasar.scala 255:28] - axi4_to_ahb_1.io.axi.ar.bits.addr <= ifu.io.ifu.ar.bits.addr @[quasar.scala 255:28] - axi4_to_ahb_1.io.axi.ar.bits.id <= ifu.io.ifu.ar.bits.id @[quasar.scala 255:28] - axi4_to_ahb_1.io.axi.ar.valid <= ifu.io.ifu.ar.valid @[quasar.scala 255:28] - ifu.io.ifu.ar.ready <= axi4_to_ahb_1.io.axi.ar.ready @[quasar.scala 255:28] - ifu.io.ifu.b.bits.id <= axi4_to_ahb_1.io.axi.b.bits.id @[quasar.scala 255:28] - ifu.io.ifu.b.bits.resp <= axi4_to_ahb_1.io.axi.b.bits.resp @[quasar.scala 255:28] - ifu.io.ifu.b.valid <= axi4_to_ahb_1.io.axi.b.valid @[quasar.scala 255:28] - axi4_to_ahb_1.io.axi.b.ready <= ifu.io.ifu.b.ready @[quasar.scala 255:28] - axi4_to_ahb_1.io.axi.w.bits.last <= ifu.io.ifu.w.bits.last @[quasar.scala 255:28] - axi4_to_ahb_1.io.axi.w.bits.strb <= ifu.io.ifu.w.bits.strb @[quasar.scala 255:28] - axi4_to_ahb_1.io.axi.w.bits.data <= ifu.io.ifu.w.bits.data @[quasar.scala 255:28] - axi4_to_ahb_1.io.axi.w.valid <= ifu.io.ifu.w.valid @[quasar.scala 255:28] - ifu.io.ifu.w.ready <= axi4_to_ahb_1.io.axi.w.ready @[quasar.scala 255:28] - axi4_to_ahb_1.io.axi.aw.bits.qos <= ifu.io.ifu.aw.bits.qos @[quasar.scala 255:28] - axi4_to_ahb_1.io.axi.aw.bits.prot <= ifu.io.ifu.aw.bits.prot @[quasar.scala 255:28] - axi4_to_ahb_1.io.axi.aw.bits.cache <= ifu.io.ifu.aw.bits.cache @[quasar.scala 255:28] - axi4_to_ahb_1.io.axi.aw.bits.lock <= ifu.io.ifu.aw.bits.lock @[quasar.scala 255:28] - axi4_to_ahb_1.io.axi.aw.bits.burst <= ifu.io.ifu.aw.bits.burst @[quasar.scala 255:28] - axi4_to_ahb_1.io.axi.aw.bits.size <= ifu.io.ifu.aw.bits.size @[quasar.scala 255:28] - axi4_to_ahb_1.io.axi.aw.bits.len <= ifu.io.ifu.aw.bits.len @[quasar.scala 255:28] - axi4_to_ahb_1.io.axi.aw.bits.region <= ifu.io.ifu.aw.bits.region @[quasar.scala 255:28] - axi4_to_ahb_1.io.axi.aw.bits.addr <= ifu.io.ifu.aw.bits.addr @[quasar.scala 255:28] - axi4_to_ahb_1.io.axi.aw.bits.id <= ifu.io.ifu.aw.bits.id @[quasar.scala 255:28] - axi4_to_ahb_1.io.axi.aw.valid <= ifu.io.ifu.aw.valid @[quasar.scala 255:28] - ifu.io.ifu.aw.ready <= axi4_to_ahb_1.io.axi.aw.ready @[quasar.scala 255:28] - io.ifu_ahb.out.hwdata <= axi4_to_ahb_1.io.ahb.out.hwdata @[quasar.scala 256:28] - io.ifu_ahb.out.hwrite <= axi4_to_ahb_1.io.ahb.out.hwrite @[quasar.scala 256:28] - io.ifu_ahb.out.htrans <= axi4_to_ahb_1.io.ahb.out.htrans @[quasar.scala 256:28] - io.ifu_ahb.out.hsize <= axi4_to_ahb_1.io.ahb.out.hsize @[quasar.scala 256:28] - io.ifu_ahb.out.hprot <= axi4_to_ahb_1.io.ahb.out.hprot @[quasar.scala 256:28] - io.ifu_ahb.out.hmastlock <= axi4_to_ahb_1.io.ahb.out.hmastlock @[quasar.scala 256:28] - io.ifu_ahb.out.hburst <= axi4_to_ahb_1.io.ahb.out.hburst @[quasar.scala 256:28] - io.ifu_ahb.out.haddr <= axi4_to_ahb_1.io.ahb.out.haddr @[quasar.scala 256:28] - axi4_to_ahb_1.io.ahb.in.hresp <= io.ifu_ahb.in.hresp @[quasar.scala 256:28] - axi4_to_ahb_1.io.ahb.in.hready <= io.ifu_ahb.in.hready @[quasar.scala 256:28] - axi4_to_ahb_1.io.ahb.in.hrdata <= io.ifu_ahb.in.hrdata @[quasar.scala 256:28] - axi4_to_ahb_1.io.axi.b.ready <= UInt<1>("h01") @[quasar.scala 257:36] - axi4_to_ahb.io.scan_mode <= io.scan_mode @[quasar.scala 259:33] - axi4_to_ahb.io.bus_clk_en <= io.dbg_bus_clk_en @[quasar.scala 260:34] - axi4_to_ahb.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 261:36] - dbg.io.sb_axi.r.bits.last <= axi4_to_ahb.io.axi.r.bits.last @[quasar.scala 262:27] - dbg.io.sb_axi.r.bits.resp <= axi4_to_ahb.io.axi.r.bits.resp @[quasar.scala 262:27] - dbg.io.sb_axi.r.bits.data <= axi4_to_ahb.io.axi.r.bits.data @[quasar.scala 262:27] - dbg.io.sb_axi.r.bits.id <= axi4_to_ahb.io.axi.r.bits.id @[quasar.scala 262:27] - dbg.io.sb_axi.r.valid <= axi4_to_ahb.io.axi.r.valid @[quasar.scala 262:27] - axi4_to_ahb.io.axi.r.ready <= dbg.io.sb_axi.r.ready @[quasar.scala 262:27] - axi4_to_ahb.io.axi.ar.bits.qos <= dbg.io.sb_axi.ar.bits.qos @[quasar.scala 262:27] - axi4_to_ahb.io.axi.ar.bits.prot <= dbg.io.sb_axi.ar.bits.prot @[quasar.scala 262:27] - axi4_to_ahb.io.axi.ar.bits.cache <= dbg.io.sb_axi.ar.bits.cache @[quasar.scala 262:27] - axi4_to_ahb.io.axi.ar.bits.lock <= dbg.io.sb_axi.ar.bits.lock @[quasar.scala 262:27] - axi4_to_ahb.io.axi.ar.bits.burst <= dbg.io.sb_axi.ar.bits.burst @[quasar.scala 262:27] - axi4_to_ahb.io.axi.ar.bits.size <= dbg.io.sb_axi.ar.bits.size @[quasar.scala 262:27] - axi4_to_ahb.io.axi.ar.bits.len <= dbg.io.sb_axi.ar.bits.len @[quasar.scala 262:27] - axi4_to_ahb.io.axi.ar.bits.region <= dbg.io.sb_axi.ar.bits.region @[quasar.scala 262:27] - axi4_to_ahb.io.axi.ar.bits.addr <= dbg.io.sb_axi.ar.bits.addr @[quasar.scala 262:27] - axi4_to_ahb.io.axi.ar.bits.id <= dbg.io.sb_axi.ar.bits.id @[quasar.scala 262:27] - axi4_to_ahb.io.axi.ar.valid <= dbg.io.sb_axi.ar.valid @[quasar.scala 262:27] - dbg.io.sb_axi.ar.ready <= axi4_to_ahb.io.axi.ar.ready @[quasar.scala 262:27] - dbg.io.sb_axi.b.bits.id <= axi4_to_ahb.io.axi.b.bits.id @[quasar.scala 262:27] - dbg.io.sb_axi.b.bits.resp <= axi4_to_ahb.io.axi.b.bits.resp @[quasar.scala 262:27] - dbg.io.sb_axi.b.valid <= axi4_to_ahb.io.axi.b.valid @[quasar.scala 262:27] - axi4_to_ahb.io.axi.b.ready <= dbg.io.sb_axi.b.ready @[quasar.scala 262:27] - axi4_to_ahb.io.axi.w.bits.last <= dbg.io.sb_axi.w.bits.last @[quasar.scala 262:27] - axi4_to_ahb.io.axi.w.bits.strb <= dbg.io.sb_axi.w.bits.strb @[quasar.scala 262:27] - axi4_to_ahb.io.axi.w.bits.data <= dbg.io.sb_axi.w.bits.data @[quasar.scala 262:27] - axi4_to_ahb.io.axi.w.valid <= dbg.io.sb_axi.w.valid @[quasar.scala 262:27] - dbg.io.sb_axi.w.ready <= axi4_to_ahb.io.axi.w.ready @[quasar.scala 262:27] - axi4_to_ahb.io.axi.aw.bits.qos <= dbg.io.sb_axi.aw.bits.qos @[quasar.scala 262:27] - axi4_to_ahb.io.axi.aw.bits.prot <= dbg.io.sb_axi.aw.bits.prot @[quasar.scala 262:27] - axi4_to_ahb.io.axi.aw.bits.cache <= dbg.io.sb_axi.aw.bits.cache @[quasar.scala 262:27] - axi4_to_ahb.io.axi.aw.bits.lock <= dbg.io.sb_axi.aw.bits.lock @[quasar.scala 262:27] - axi4_to_ahb.io.axi.aw.bits.burst <= dbg.io.sb_axi.aw.bits.burst @[quasar.scala 262:27] - axi4_to_ahb.io.axi.aw.bits.size <= dbg.io.sb_axi.aw.bits.size @[quasar.scala 262:27] - axi4_to_ahb.io.axi.aw.bits.len <= dbg.io.sb_axi.aw.bits.len @[quasar.scala 262:27] - axi4_to_ahb.io.axi.aw.bits.region <= dbg.io.sb_axi.aw.bits.region @[quasar.scala 262:27] - axi4_to_ahb.io.axi.aw.bits.addr <= dbg.io.sb_axi.aw.bits.addr @[quasar.scala 262:27] - axi4_to_ahb.io.axi.aw.bits.id <= dbg.io.sb_axi.aw.bits.id @[quasar.scala 262:27] - axi4_to_ahb.io.axi.aw.valid <= dbg.io.sb_axi.aw.valid @[quasar.scala 262:27] - dbg.io.sb_axi.aw.ready <= axi4_to_ahb.io.axi.aw.ready @[quasar.scala 262:27] - io.sb_ahb.out.hwdata <= axi4_to_ahb.io.ahb.out.hwdata @[quasar.scala 263:27] - io.sb_ahb.out.hwrite <= axi4_to_ahb.io.ahb.out.hwrite @[quasar.scala 263:27] - io.sb_ahb.out.htrans <= axi4_to_ahb.io.ahb.out.htrans @[quasar.scala 263:27] - io.sb_ahb.out.hsize <= axi4_to_ahb.io.ahb.out.hsize @[quasar.scala 263:27] - io.sb_ahb.out.hprot <= axi4_to_ahb.io.ahb.out.hprot @[quasar.scala 263:27] - io.sb_ahb.out.hmastlock <= axi4_to_ahb.io.ahb.out.hmastlock @[quasar.scala 263:27] - io.sb_ahb.out.hburst <= axi4_to_ahb.io.ahb.out.hburst @[quasar.scala 263:27] - io.sb_ahb.out.haddr <= axi4_to_ahb.io.ahb.out.haddr @[quasar.scala 263:27] - axi4_to_ahb.io.ahb.in.hresp <= io.sb_ahb.in.hresp @[quasar.scala 263:27] - axi4_to_ahb.io.ahb.in.hready <= io.sb_ahb.in.hready @[quasar.scala 263:27] - axi4_to_ahb.io.ahb.in.hrdata <= io.sb_ahb.in.hrdata @[quasar.scala 263:27] - ahb_to_axi4.io.scan_mode <= io.scan_mode @[quasar.scala 265:34] - ahb_to_axi4.io.bus_clk_en <= io.dma_bus_clk_en @[quasar.scala 266:35] - ahb_to_axi4.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 267:37] - ahb_to_axi4.io.axi.r.bits.last <= dma_ctrl.io.dma_axi.r.bits.last @[quasar.scala 268:28] - ahb_to_axi4.io.axi.r.bits.resp <= dma_ctrl.io.dma_axi.r.bits.resp @[quasar.scala 268:28] - ahb_to_axi4.io.axi.r.bits.data <= dma_ctrl.io.dma_axi.r.bits.data @[quasar.scala 268:28] - ahb_to_axi4.io.axi.r.bits.id <= dma_ctrl.io.dma_axi.r.bits.id @[quasar.scala 268:28] - ahb_to_axi4.io.axi.r.valid <= dma_ctrl.io.dma_axi.r.valid @[quasar.scala 268:28] - dma_ctrl.io.dma_axi.r.ready <= ahb_to_axi4.io.axi.r.ready @[quasar.scala 268:28] - dma_ctrl.io.dma_axi.ar.bits.qos <= ahb_to_axi4.io.axi.ar.bits.qos @[quasar.scala 268:28] - dma_ctrl.io.dma_axi.ar.bits.prot <= ahb_to_axi4.io.axi.ar.bits.prot @[quasar.scala 268:28] - dma_ctrl.io.dma_axi.ar.bits.cache <= ahb_to_axi4.io.axi.ar.bits.cache @[quasar.scala 268:28] - dma_ctrl.io.dma_axi.ar.bits.lock <= ahb_to_axi4.io.axi.ar.bits.lock @[quasar.scala 268:28] - dma_ctrl.io.dma_axi.ar.bits.burst <= ahb_to_axi4.io.axi.ar.bits.burst @[quasar.scala 268:28] - dma_ctrl.io.dma_axi.ar.bits.size <= ahb_to_axi4.io.axi.ar.bits.size @[quasar.scala 268:28] - dma_ctrl.io.dma_axi.ar.bits.len <= ahb_to_axi4.io.axi.ar.bits.len @[quasar.scala 268:28] - dma_ctrl.io.dma_axi.ar.bits.region <= ahb_to_axi4.io.axi.ar.bits.region @[quasar.scala 268:28] - dma_ctrl.io.dma_axi.ar.bits.addr <= ahb_to_axi4.io.axi.ar.bits.addr @[quasar.scala 268:28] - dma_ctrl.io.dma_axi.ar.bits.id <= ahb_to_axi4.io.axi.ar.bits.id @[quasar.scala 268:28] - dma_ctrl.io.dma_axi.ar.valid <= ahb_to_axi4.io.axi.ar.valid @[quasar.scala 268:28] - ahb_to_axi4.io.axi.ar.ready <= dma_ctrl.io.dma_axi.ar.ready @[quasar.scala 268:28] - ahb_to_axi4.io.axi.b.bits.id <= dma_ctrl.io.dma_axi.b.bits.id @[quasar.scala 268:28] - ahb_to_axi4.io.axi.b.bits.resp <= dma_ctrl.io.dma_axi.b.bits.resp @[quasar.scala 268:28] - ahb_to_axi4.io.axi.b.valid <= dma_ctrl.io.dma_axi.b.valid @[quasar.scala 268:28] - dma_ctrl.io.dma_axi.b.ready <= ahb_to_axi4.io.axi.b.ready @[quasar.scala 268:28] - dma_ctrl.io.dma_axi.w.bits.last <= ahb_to_axi4.io.axi.w.bits.last @[quasar.scala 268:28] - dma_ctrl.io.dma_axi.w.bits.strb <= ahb_to_axi4.io.axi.w.bits.strb @[quasar.scala 268:28] - dma_ctrl.io.dma_axi.w.bits.data <= ahb_to_axi4.io.axi.w.bits.data @[quasar.scala 268:28] - dma_ctrl.io.dma_axi.w.valid <= ahb_to_axi4.io.axi.w.valid @[quasar.scala 268:28] - ahb_to_axi4.io.axi.w.ready <= dma_ctrl.io.dma_axi.w.ready @[quasar.scala 268:28] - dma_ctrl.io.dma_axi.aw.bits.qos <= ahb_to_axi4.io.axi.aw.bits.qos @[quasar.scala 268:28] - dma_ctrl.io.dma_axi.aw.bits.prot <= ahb_to_axi4.io.axi.aw.bits.prot @[quasar.scala 268:28] - dma_ctrl.io.dma_axi.aw.bits.cache <= ahb_to_axi4.io.axi.aw.bits.cache @[quasar.scala 268:28] - dma_ctrl.io.dma_axi.aw.bits.lock <= ahb_to_axi4.io.axi.aw.bits.lock @[quasar.scala 268:28] - dma_ctrl.io.dma_axi.aw.bits.burst <= ahb_to_axi4.io.axi.aw.bits.burst @[quasar.scala 268:28] - dma_ctrl.io.dma_axi.aw.bits.size <= ahb_to_axi4.io.axi.aw.bits.size @[quasar.scala 268:28] - dma_ctrl.io.dma_axi.aw.bits.len <= ahb_to_axi4.io.axi.aw.bits.len @[quasar.scala 268:28] - dma_ctrl.io.dma_axi.aw.bits.region <= ahb_to_axi4.io.axi.aw.bits.region @[quasar.scala 268:28] - dma_ctrl.io.dma_axi.aw.bits.addr <= ahb_to_axi4.io.axi.aw.bits.addr @[quasar.scala 268:28] - dma_ctrl.io.dma_axi.aw.bits.id <= ahb_to_axi4.io.axi.aw.bits.id @[quasar.scala 268:28] - dma_ctrl.io.dma_axi.aw.valid <= ahb_to_axi4.io.axi.aw.valid @[quasar.scala 268:28] - ahb_to_axi4.io.axi.aw.ready <= dma_ctrl.io.dma_axi.aw.ready @[quasar.scala 268:28] - ahb_to_axi4.io.ahb.hreadyin <= io.dma_ahb.hreadyin @[quasar.scala 269:28] - ahb_to_axi4.io.ahb.hsel <= io.dma_ahb.hsel @[quasar.scala 269:28] - ahb_to_axi4.io.ahb.sig.out.hwdata <= io.dma_ahb.sig.out.hwdata @[quasar.scala 269:28] - ahb_to_axi4.io.ahb.sig.out.hwrite <= io.dma_ahb.sig.out.hwrite @[quasar.scala 269:28] - ahb_to_axi4.io.ahb.sig.out.htrans <= io.dma_ahb.sig.out.htrans @[quasar.scala 269:28] - ahb_to_axi4.io.ahb.sig.out.hsize <= io.dma_ahb.sig.out.hsize @[quasar.scala 269:28] - ahb_to_axi4.io.ahb.sig.out.hprot <= io.dma_ahb.sig.out.hprot @[quasar.scala 269:28] - ahb_to_axi4.io.ahb.sig.out.hmastlock <= io.dma_ahb.sig.out.hmastlock @[quasar.scala 269:28] - ahb_to_axi4.io.ahb.sig.out.hburst <= io.dma_ahb.sig.out.hburst @[quasar.scala 269:28] - ahb_to_axi4.io.ahb.sig.out.haddr <= io.dma_ahb.sig.out.haddr @[quasar.scala 269:28] - io.dma_ahb.sig.in.hresp <= ahb_to_axi4.io.ahb.sig.in.hresp @[quasar.scala 269:28] - io.dma_ahb.sig.in.hready <= ahb_to_axi4.io.ahb.sig.in.hready @[quasar.scala 269:28] - io.dma_ahb.sig.in.hrdata <= ahb_to_axi4.io.ahb.sig.in.hrdata @[quasar.scala 269:28] - wire _T_13 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar.scala 271:36] - _T_13.r.bits.last <= UInt<1>("h00") @[quasar.scala 271:36] - _T_13.r.bits.resp <= UInt<2>("h00") @[quasar.scala 271:36] - _T_13.r.bits.data <= UInt<64>("h00") @[quasar.scala 271:36] - _T_13.r.bits.id <= UInt<1>("h00") @[quasar.scala 271:36] - _T_13.r.valid <= UInt<1>("h00") @[quasar.scala 271:36] - _T_13.r.ready <= UInt<1>("h00") @[quasar.scala 271:36] - _T_13.ar.bits.qos <= UInt<4>("h00") @[quasar.scala 271:36] - _T_13.ar.bits.prot <= UInt<3>("h00") @[quasar.scala 271:36] - _T_13.ar.bits.cache <= UInt<4>("h00") @[quasar.scala 271:36] - _T_13.ar.bits.lock <= UInt<1>("h00") @[quasar.scala 271:36] - _T_13.ar.bits.burst <= UInt<2>("h00") @[quasar.scala 271:36] - _T_13.ar.bits.size <= UInt<3>("h00") @[quasar.scala 271:36] - _T_13.ar.bits.len <= UInt<8>("h00") @[quasar.scala 271:36] - _T_13.ar.bits.region <= UInt<4>("h00") @[quasar.scala 271:36] - _T_13.ar.bits.addr <= UInt<32>("h00") @[quasar.scala 271:36] - _T_13.ar.bits.id <= UInt<1>("h00") @[quasar.scala 271:36] - _T_13.ar.valid <= UInt<1>("h00") @[quasar.scala 271:36] - _T_13.ar.ready <= UInt<1>("h00") @[quasar.scala 271:36] - _T_13.b.bits.id <= UInt<1>("h00") @[quasar.scala 271:36] - _T_13.b.bits.resp <= UInt<2>("h00") @[quasar.scala 271:36] - _T_13.b.valid <= UInt<1>("h00") @[quasar.scala 271:36] - _T_13.b.ready <= UInt<1>("h00") @[quasar.scala 271:36] - _T_13.w.bits.last <= UInt<1>("h00") @[quasar.scala 271:36] - _T_13.w.bits.strb <= UInt<8>("h00") @[quasar.scala 271:36] - _T_13.w.bits.data <= UInt<64>("h00") @[quasar.scala 271:36] - _T_13.w.valid <= UInt<1>("h00") @[quasar.scala 271:36] - _T_13.w.ready <= UInt<1>("h00") @[quasar.scala 271:36] - _T_13.aw.bits.qos <= UInt<4>("h00") @[quasar.scala 271:36] - _T_13.aw.bits.prot <= UInt<3>("h00") @[quasar.scala 271:36] - _T_13.aw.bits.cache <= UInt<4>("h00") @[quasar.scala 271:36] - _T_13.aw.bits.lock <= UInt<1>("h00") @[quasar.scala 271:36] - _T_13.aw.bits.burst <= UInt<2>("h00") @[quasar.scala 271:36] - _T_13.aw.bits.size <= UInt<3>("h00") @[quasar.scala 271:36] - _T_13.aw.bits.len <= UInt<8>("h00") @[quasar.scala 271:36] - _T_13.aw.bits.region <= UInt<4>("h00") @[quasar.scala 271:36] - _T_13.aw.bits.addr <= UInt<32>("h00") @[quasar.scala 271:36] - _T_13.aw.bits.id <= UInt<1>("h00") @[quasar.scala 271:36] - _T_13.aw.valid <= UInt<1>("h00") @[quasar.scala 271:36] - _T_13.aw.ready <= UInt<1>("h00") @[quasar.scala 271:36] - io.dma_axi.r.bits.last <= _T_13.r.bits.last @[quasar.scala 271:21] - io.dma_axi.r.bits.resp <= _T_13.r.bits.resp @[quasar.scala 271:21] - io.dma_axi.r.bits.data <= _T_13.r.bits.data @[quasar.scala 271:21] - io.dma_axi.r.bits.id <= _T_13.r.bits.id @[quasar.scala 271:21] - io.dma_axi.r.valid <= _T_13.r.valid @[quasar.scala 271:21] - _T_13.r.ready <= io.dma_axi.r.ready @[quasar.scala 271:21] - _T_13.ar.bits.qos <= io.dma_axi.ar.bits.qos @[quasar.scala 271:21] - _T_13.ar.bits.prot <= io.dma_axi.ar.bits.prot @[quasar.scala 271:21] - _T_13.ar.bits.cache <= io.dma_axi.ar.bits.cache @[quasar.scala 271:21] - _T_13.ar.bits.lock <= io.dma_axi.ar.bits.lock @[quasar.scala 271:21] - _T_13.ar.bits.burst <= io.dma_axi.ar.bits.burst @[quasar.scala 271:21] - _T_13.ar.bits.size <= io.dma_axi.ar.bits.size @[quasar.scala 271:21] - _T_13.ar.bits.len <= io.dma_axi.ar.bits.len @[quasar.scala 271:21] - _T_13.ar.bits.region <= io.dma_axi.ar.bits.region @[quasar.scala 271:21] - _T_13.ar.bits.addr <= io.dma_axi.ar.bits.addr @[quasar.scala 271:21] - _T_13.ar.bits.id <= io.dma_axi.ar.bits.id @[quasar.scala 271:21] - _T_13.ar.valid <= io.dma_axi.ar.valid @[quasar.scala 271:21] - io.dma_axi.ar.ready <= _T_13.ar.ready @[quasar.scala 271:21] - io.dma_axi.b.bits.id <= _T_13.b.bits.id @[quasar.scala 271:21] - io.dma_axi.b.bits.resp <= _T_13.b.bits.resp @[quasar.scala 271:21] - io.dma_axi.b.valid <= _T_13.b.valid @[quasar.scala 271:21] - _T_13.b.ready <= io.dma_axi.b.ready @[quasar.scala 271:21] - _T_13.w.bits.last <= io.dma_axi.w.bits.last @[quasar.scala 271:21] - _T_13.w.bits.strb <= io.dma_axi.w.bits.strb @[quasar.scala 271:21] - _T_13.w.bits.data <= io.dma_axi.w.bits.data @[quasar.scala 271:21] - _T_13.w.valid <= io.dma_axi.w.valid @[quasar.scala 271:21] - io.dma_axi.w.ready <= _T_13.w.ready @[quasar.scala 271:21] - _T_13.aw.bits.qos <= io.dma_axi.aw.bits.qos @[quasar.scala 271:21] - _T_13.aw.bits.prot <= io.dma_axi.aw.bits.prot @[quasar.scala 271:21] - _T_13.aw.bits.cache <= io.dma_axi.aw.bits.cache @[quasar.scala 271:21] - _T_13.aw.bits.lock <= io.dma_axi.aw.bits.lock @[quasar.scala 271:21] - _T_13.aw.bits.burst <= io.dma_axi.aw.bits.burst @[quasar.scala 271:21] - _T_13.aw.bits.size <= io.dma_axi.aw.bits.size @[quasar.scala 271:21] - _T_13.aw.bits.len <= io.dma_axi.aw.bits.len @[quasar.scala 271:21] - _T_13.aw.bits.region <= io.dma_axi.aw.bits.region @[quasar.scala 271:21] - _T_13.aw.bits.addr <= io.dma_axi.aw.bits.addr @[quasar.scala 271:21] - _T_13.aw.bits.id <= io.dma_axi.aw.bits.id @[quasar.scala 271:21] - _T_13.aw.valid <= io.dma_axi.aw.valid @[quasar.scala 271:21] - io.dma_axi.aw.ready <= _T_13.aw.ready @[quasar.scala 271:21] - wire _T_14 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar.scala 272:36] - _T_14.r.bits.last <= UInt<1>("h00") @[quasar.scala 272:36] - _T_14.r.bits.resp <= UInt<2>("h00") @[quasar.scala 272:36] - _T_14.r.bits.data <= UInt<64>("h00") @[quasar.scala 272:36] - _T_14.r.bits.id <= UInt<1>("h00") @[quasar.scala 272:36] - _T_14.r.valid <= UInt<1>("h00") @[quasar.scala 272:36] - _T_14.r.ready <= UInt<1>("h00") @[quasar.scala 272:36] - _T_14.ar.bits.qos <= UInt<4>("h00") @[quasar.scala 272:36] - _T_14.ar.bits.prot <= UInt<3>("h00") @[quasar.scala 272:36] - _T_14.ar.bits.cache <= UInt<4>("h00") @[quasar.scala 272:36] - _T_14.ar.bits.lock <= UInt<1>("h00") @[quasar.scala 272:36] - _T_14.ar.bits.burst <= UInt<2>("h00") @[quasar.scala 272:36] - _T_14.ar.bits.size <= UInt<3>("h00") @[quasar.scala 272:36] - _T_14.ar.bits.len <= UInt<8>("h00") @[quasar.scala 272:36] - _T_14.ar.bits.region <= UInt<4>("h00") @[quasar.scala 272:36] - _T_14.ar.bits.addr <= UInt<32>("h00") @[quasar.scala 272:36] - _T_14.ar.bits.id <= UInt<1>("h00") @[quasar.scala 272:36] - _T_14.ar.valid <= UInt<1>("h00") @[quasar.scala 272:36] - _T_14.ar.ready <= UInt<1>("h00") @[quasar.scala 272:36] - _T_14.b.bits.id <= UInt<1>("h00") @[quasar.scala 272:36] - _T_14.b.bits.resp <= UInt<2>("h00") @[quasar.scala 272:36] - _T_14.b.valid <= UInt<1>("h00") @[quasar.scala 272:36] - _T_14.b.ready <= UInt<1>("h00") @[quasar.scala 272:36] - _T_14.w.bits.last <= UInt<1>("h00") @[quasar.scala 272:36] - _T_14.w.bits.strb <= UInt<8>("h00") @[quasar.scala 272:36] - _T_14.w.bits.data <= UInt<64>("h00") @[quasar.scala 272:36] - _T_14.w.valid <= UInt<1>("h00") @[quasar.scala 272:36] - _T_14.w.ready <= UInt<1>("h00") @[quasar.scala 272:36] - _T_14.aw.bits.qos <= UInt<4>("h00") @[quasar.scala 272:36] - _T_14.aw.bits.prot <= UInt<3>("h00") @[quasar.scala 272:36] - _T_14.aw.bits.cache <= UInt<4>("h00") @[quasar.scala 272:36] - _T_14.aw.bits.lock <= UInt<1>("h00") @[quasar.scala 272:36] - _T_14.aw.bits.burst <= UInt<2>("h00") @[quasar.scala 272:36] - _T_14.aw.bits.size <= UInt<3>("h00") @[quasar.scala 272:36] - _T_14.aw.bits.len <= UInt<8>("h00") @[quasar.scala 272:36] - _T_14.aw.bits.region <= UInt<4>("h00") @[quasar.scala 272:36] - _T_14.aw.bits.addr <= UInt<32>("h00") @[quasar.scala 272:36] - _T_14.aw.bits.id <= UInt<1>("h00") @[quasar.scala 272:36] - _T_14.aw.valid <= UInt<1>("h00") @[quasar.scala 272:36] - _T_14.aw.ready <= UInt<1>("h00") @[quasar.scala 272:36] - _T_14.r.bits.last <= io.sb_axi.r.bits.last @[quasar.scala 272:21] - _T_14.r.bits.resp <= io.sb_axi.r.bits.resp @[quasar.scala 272:21] - _T_14.r.bits.data <= io.sb_axi.r.bits.data @[quasar.scala 272:21] - _T_14.r.bits.id <= io.sb_axi.r.bits.id @[quasar.scala 272:21] - _T_14.r.valid <= io.sb_axi.r.valid @[quasar.scala 272:21] - io.sb_axi.r.ready <= _T_14.r.ready @[quasar.scala 272:21] - io.sb_axi.ar.bits.qos <= _T_14.ar.bits.qos @[quasar.scala 272:21] - io.sb_axi.ar.bits.prot <= _T_14.ar.bits.prot @[quasar.scala 272:21] - io.sb_axi.ar.bits.cache <= _T_14.ar.bits.cache @[quasar.scala 272:21] - io.sb_axi.ar.bits.lock <= _T_14.ar.bits.lock @[quasar.scala 272:21] - io.sb_axi.ar.bits.burst <= _T_14.ar.bits.burst @[quasar.scala 272:21] - io.sb_axi.ar.bits.size <= _T_14.ar.bits.size @[quasar.scala 272:21] - io.sb_axi.ar.bits.len <= _T_14.ar.bits.len @[quasar.scala 272:21] - io.sb_axi.ar.bits.region <= _T_14.ar.bits.region @[quasar.scala 272:21] - io.sb_axi.ar.bits.addr <= _T_14.ar.bits.addr @[quasar.scala 272:21] - io.sb_axi.ar.bits.id <= _T_14.ar.bits.id @[quasar.scala 272:21] - io.sb_axi.ar.valid <= _T_14.ar.valid @[quasar.scala 272:21] - _T_14.ar.ready <= io.sb_axi.ar.ready @[quasar.scala 272:21] - _T_14.b.bits.id <= io.sb_axi.b.bits.id @[quasar.scala 272:21] - _T_14.b.bits.resp <= io.sb_axi.b.bits.resp @[quasar.scala 272:21] - _T_14.b.valid <= io.sb_axi.b.valid @[quasar.scala 272:21] - io.sb_axi.b.ready <= _T_14.b.ready @[quasar.scala 272:21] - io.sb_axi.w.bits.last <= _T_14.w.bits.last @[quasar.scala 272:21] - io.sb_axi.w.bits.strb <= _T_14.w.bits.strb @[quasar.scala 272:21] - io.sb_axi.w.bits.data <= _T_14.w.bits.data @[quasar.scala 272:21] - io.sb_axi.w.valid <= _T_14.w.valid @[quasar.scala 272:21] - _T_14.w.ready <= io.sb_axi.w.ready @[quasar.scala 272:21] - io.sb_axi.aw.bits.qos <= _T_14.aw.bits.qos @[quasar.scala 272:21] - io.sb_axi.aw.bits.prot <= _T_14.aw.bits.prot @[quasar.scala 272:21] - io.sb_axi.aw.bits.cache <= _T_14.aw.bits.cache @[quasar.scala 272:21] - io.sb_axi.aw.bits.lock <= _T_14.aw.bits.lock @[quasar.scala 272:21] - io.sb_axi.aw.bits.burst <= _T_14.aw.bits.burst @[quasar.scala 272:21] - io.sb_axi.aw.bits.size <= _T_14.aw.bits.size @[quasar.scala 272:21] - io.sb_axi.aw.bits.len <= _T_14.aw.bits.len @[quasar.scala 272:21] - io.sb_axi.aw.bits.region <= _T_14.aw.bits.region @[quasar.scala 272:21] - io.sb_axi.aw.bits.addr <= _T_14.aw.bits.addr @[quasar.scala 272:21] - io.sb_axi.aw.bits.id <= _T_14.aw.bits.id @[quasar.scala 272:21] - io.sb_axi.aw.valid <= _T_14.aw.valid @[quasar.scala 272:21] - _T_14.aw.ready <= io.sb_axi.aw.ready @[quasar.scala 272:21] - wire _T_15 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar.scala 273:36] - _T_15.r.bits.last <= UInt<1>("h00") @[quasar.scala 273:36] - _T_15.r.bits.resp <= UInt<2>("h00") @[quasar.scala 273:36] - _T_15.r.bits.data <= UInt<64>("h00") @[quasar.scala 273:36] - _T_15.r.bits.id <= UInt<3>("h00") @[quasar.scala 273:36] - _T_15.r.valid <= UInt<1>("h00") @[quasar.scala 273:36] - _T_15.r.ready <= UInt<1>("h00") @[quasar.scala 273:36] - _T_15.ar.bits.qos <= UInt<4>("h00") @[quasar.scala 273:36] - _T_15.ar.bits.prot <= UInt<3>("h00") @[quasar.scala 273:36] - _T_15.ar.bits.cache <= UInt<4>("h00") @[quasar.scala 273:36] - _T_15.ar.bits.lock <= UInt<1>("h00") @[quasar.scala 273:36] - _T_15.ar.bits.burst <= UInt<2>("h00") @[quasar.scala 273:36] - _T_15.ar.bits.size <= UInt<3>("h00") @[quasar.scala 273:36] - _T_15.ar.bits.len <= UInt<8>("h00") @[quasar.scala 273:36] - _T_15.ar.bits.region <= UInt<4>("h00") @[quasar.scala 273:36] - _T_15.ar.bits.addr <= UInt<32>("h00") @[quasar.scala 273:36] - _T_15.ar.bits.id <= UInt<3>("h00") @[quasar.scala 273:36] - _T_15.ar.valid <= UInt<1>("h00") @[quasar.scala 273:36] - _T_15.ar.ready <= UInt<1>("h00") @[quasar.scala 273:36] - _T_15.b.bits.id <= UInt<3>("h00") @[quasar.scala 273:36] - _T_15.b.bits.resp <= UInt<2>("h00") @[quasar.scala 273:36] - _T_15.b.valid <= UInt<1>("h00") @[quasar.scala 273:36] - _T_15.b.ready <= UInt<1>("h00") @[quasar.scala 273:36] - _T_15.w.bits.last <= UInt<1>("h00") @[quasar.scala 273:36] - _T_15.w.bits.strb <= UInt<8>("h00") @[quasar.scala 273:36] - _T_15.w.bits.data <= UInt<64>("h00") @[quasar.scala 273:36] - _T_15.w.valid <= UInt<1>("h00") @[quasar.scala 273:36] - _T_15.w.ready <= UInt<1>("h00") @[quasar.scala 273:36] - _T_15.aw.bits.qos <= UInt<4>("h00") @[quasar.scala 273:36] - _T_15.aw.bits.prot <= UInt<3>("h00") @[quasar.scala 273:36] - _T_15.aw.bits.cache <= UInt<4>("h00") @[quasar.scala 273:36] - _T_15.aw.bits.lock <= UInt<1>("h00") @[quasar.scala 273:36] - _T_15.aw.bits.burst <= UInt<2>("h00") @[quasar.scala 273:36] - _T_15.aw.bits.size <= UInt<3>("h00") @[quasar.scala 273:36] - _T_15.aw.bits.len <= UInt<8>("h00") @[quasar.scala 273:36] - _T_15.aw.bits.region <= UInt<4>("h00") @[quasar.scala 273:36] - _T_15.aw.bits.addr <= UInt<32>("h00") @[quasar.scala 273:36] - _T_15.aw.bits.id <= UInt<3>("h00") @[quasar.scala 273:36] - _T_15.aw.valid <= UInt<1>("h00") @[quasar.scala 273:36] - _T_15.aw.ready <= UInt<1>("h00") @[quasar.scala 273:36] - _T_15.r.bits.last <= io.ifu_axi.r.bits.last @[quasar.scala 273:21] - _T_15.r.bits.resp <= io.ifu_axi.r.bits.resp @[quasar.scala 273:21] - _T_15.r.bits.data <= io.ifu_axi.r.bits.data @[quasar.scala 273:21] - _T_15.r.bits.id <= io.ifu_axi.r.bits.id @[quasar.scala 273:21] - _T_15.r.valid <= io.ifu_axi.r.valid @[quasar.scala 273:21] - io.ifu_axi.r.ready <= _T_15.r.ready @[quasar.scala 273:21] - io.ifu_axi.ar.bits.qos <= _T_15.ar.bits.qos @[quasar.scala 273:21] - io.ifu_axi.ar.bits.prot <= _T_15.ar.bits.prot @[quasar.scala 273:21] - io.ifu_axi.ar.bits.cache <= _T_15.ar.bits.cache @[quasar.scala 273:21] - io.ifu_axi.ar.bits.lock <= _T_15.ar.bits.lock @[quasar.scala 273:21] - io.ifu_axi.ar.bits.burst <= _T_15.ar.bits.burst @[quasar.scala 273:21] - io.ifu_axi.ar.bits.size <= _T_15.ar.bits.size @[quasar.scala 273:21] - io.ifu_axi.ar.bits.len <= _T_15.ar.bits.len @[quasar.scala 273:21] - io.ifu_axi.ar.bits.region <= _T_15.ar.bits.region @[quasar.scala 273:21] - io.ifu_axi.ar.bits.addr <= _T_15.ar.bits.addr @[quasar.scala 273:21] - io.ifu_axi.ar.bits.id <= _T_15.ar.bits.id @[quasar.scala 273:21] - io.ifu_axi.ar.valid <= _T_15.ar.valid @[quasar.scala 273:21] - _T_15.ar.ready <= io.ifu_axi.ar.ready @[quasar.scala 273:21] - _T_15.b.bits.id <= io.ifu_axi.b.bits.id @[quasar.scala 273:21] - _T_15.b.bits.resp <= io.ifu_axi.b.bits.resp @[quasar.scala 273:21] - _T_15.b.valid <= io.ifu_axi.b.valid @[quasar.scala 273:21] - io.ifu_axi.b.ready <= _T_15.b.ready @[quasar.scala 273:21] - io.ifu_axi.w.bits.last <= _T_15.w.bits.last @[quasar.scala 273:21] - io.ifu_axi.w.bits.strb <= _T_15.w.bits.strb @[quasar.scala 273:21] - io.ifu_axi.w.bits.data <= _T_15.w.bits.data @[quasar.scala 273:21] - io.ifu_axi.w.valid <= _T_15.w.valid @[quasar.scala 273:21] - _T_15.w.ready <= io.ifu_axi.w.ready @[quasar.scala 273:21] - io.ifu_axi.aw.bits.qos <= _T_15.aw.bits.qos @[quasar.scala 273:21] - io.ifu_axi.aw.bits.prot <= _T_15.aw.bits.prot @[quasar.scala 273:21] - io.ifu_axi.aw.bits.cache <= _T_15.aw.bits.cache @[quasar.scala 273:21] - io.ifu_axi.aw.bits.lock <= _T_15.aw.bits.lock @[quasar.scala 273:21] - io.ifu_axi.aw.bits.burst <= _T_15.aw.bits.burst @[quasar.scala 273:21] - io.ifu_axi.aw.bits.size <= _T_15.aw.bits.size @[quasar.scala 273:21] - io.ifu_axi.aw.bits.len <= _T_15.aw.bits.len @[quasar.scala 273:21] - io.ifu_axi.aw.bits.region <= _T_15.aw.bits.region @[quasar.scala 273:21] - io.ifu_axi.aw.bits.addr <= _T_15.aw.bits.addr @[quasar.scala 273:21] - io.ifu_axi.aw.bits.id <= _T_15.aw.bits.id @[quasar.scala 273:21] - io.ifu_axi.aw.valid <= _T_15.aw.valid @[quasar.scala 273:21] - _T_15.aw.ready <= io.ifu_axi.aw.ready @[quasar.scala 273:21] - wire _T_16 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar.scala 274:36] - _T_16.r.bits.last <= UInt<1>("h00") @[quasar.scala 274:36] - _T_16.r.bits.resp <= UInt<2>("h00") @[quasar.scala 274:36] - _T_16.r.bits.data <= UInt<64>("h00") @[quasar.scala 274:36] - _T_16.r.bits.id <= UInt<3>("h00") @[quasar.scala 274:36] - _T_16.r.valid <= UInt<1>("h00") @[quasar.scala 274:36] - _T_16.r.ready <= UInt<1>("h00") @[quasar.scala 274:36] - _T_16.ar.bits.qos <= UInt<4>("h00") @[quasar.scala 274:36] - _T_16.ar.bits.prot <= UInt<3>("h00") @[quasar.scala 274:36] - _T_16.ar.bits.cache <= UInt<4>("h00") @[quasar.scala 274:36] - _T_16.ar.bits.lock <= UInt<1>("h00") @[quasar.scala 274:36] - _T_16.ar.bits.burst <= UInt<2>("h00") @[quasar.scala 274:36] - _T_16.ar.bits.size <= UInt<3>("h00") @[quasar.scala 274:36] - _T_16.ar.bits.len <= UInt<8>("h00") @[quasar.scala 274:36] - _T_16.ar.bits.region <= UInt<4>("h00") @[quasar.scala 274:36] - _T_16.ar.bits.addr <= UInt<32>("h00") @[quasar.scala 274:36] - _T_16.ar.bits.id <= UInt<3>("h00") @[quasar.scala 274:36] - _T_16.ar.valid <= UInt<1>("h00") @[quasar.scala 274:36] - _T_16.ar.ready <= UInt<1>("h00") @[quasar.scala 274:36] - _T_16.b.bits.id <= UInt<3>("h00") @[quasar.scala 274:36] - _T_16.b.bits.resp <= UInt<2>("h00") @[quasar.scala 274:36] - _T_16.b.valid <= UInt<1>("h00") @[quasar.scala 274:36] - _T_16.b.ready <= UInt<1>("h00") @[quasar.scala 274:36] - _T_16.w.bits.last <= UInt<1>("h00") @[quasar.scala 274:36] - _T_16.w.bits.strb <= UInt<8>("h00") @[quasar.scala 274:36] - _T_16.w.bits.data <= UInt<64>("h00") @[quasar.scala 274:36] - _T_16.w.valid <= UInt<1>("h00") @[quasar.scala 274:36] - _T_16.w.ready <= UInt<1>("h00") @[quasar.scala 274:36] - _T_16.aw.bits.qos <= UInt<4>("h00") @[quasar.scala 274:36] - _T_16.aw.bits.prot <= UInt<3>("h00") @[quasar.scala 274:36] - _T_16.aw.bits.cache <= UInt<4>("h00") @[quasar.scala 274:36] - _T_16.aw.bits.lock <= UInt<1>("h00") @[quasar.scala 274:36] - _T_16.aw.bits.burst <= UInt<2>("h00") @[quasar.scala 274:36] - _T_16.aw.bits.size <= UInt<3>("h00") @[quasar.scala 274:36] - _T_16.aw.bits.len <= UInt<8>("h00") @[quasar.scala 274:36] - _T_16.aw.bits.region <= UInt<4>("h00") @[quasar.scala 274:36] - _T_16.aw.bits.addr <= UInt<32>("h00") @[quasar.scala 274:36] - _T_16.aw.bits.id <= UInt<3>("h00") @[quasar.scala 274:36] - _T_16.aw.valid <= UInt<1>("h00") @[quasar.scala 274:36] - _T_16.aw.ready <= UInt<1>("h00") @[quasar.scala 274:36] - _T_16.r.bits.last <= io.lsu_axi.r.bits.last @[quasar.scala 274:21] - _T_16.r.bits.resp <= io.lsu_axi.r.bits.resp @[quasar.scala 274:21] - _T_16.r.bits.data <= io.lsu_axi.r.bits.data @[quasar.scala 274:21] - _T_16.r.bits.id <= io.lsu_axi.r.bits.id @[quasar.scala 274:21] - _T_16.r.valid <= io.lsu_axi.r.valid @[quasar.scala 274:21] - io.lsu_axi.r.ready <= _T_16.r.ready @[quasar.scala 274:21] - io.lsu_axi.ar.bits.qos <= _T_16.ar.bits.qos @[quasar.scala 274:21] - io.lsu_axi.ar.bits.prot <= _T_16.ar.bits.prot @[quasar.scala 274:21] - io.lsu_axi.ar.bits.cache <= _T_16.ar.bits.cache @[quasar.scala 274:21] - io.lsu_axi.ar.bits.lock <= _T_16.ar.bits.lock @[quasar.scala 274:21] - io.lsu_axi.ar.bits.burst <= _T_16.ar.bits.burst @[quasar.scala 274:21] - io.lsu_axi.ar.bits.size <= _T_16.ar.bits.size @[quasar.scala 274:21] - io.lsu_axi.ar.bits.len <= _T_16.ar.bits.len @[quasar.scala 274:21] - io.lsu_axi.ar.bits.region <= _T_16.ar.bits.region @[quasar.scala 274:21] - io.lsu_axi.ar.bits.addr <= _T_16.ar.bits.addr @[quasar.scala 274:21] - io.lsu_axi.ar.bits.id <= _T_16.ar.bits.id @[quasar.scala 274:21] - io.lsu_axi.ar.valid <= _T_16.ar.valid @[quasar.scala 274:21] - _T_16.ar.ready <= io.lsu_axi.ar.ready @[quasar.scala 274:21] - _T_16.b.bits.id <= io.lsu_axi.b.bits.id @[quasar.scala 274:21] - _T_16.b.bits.resp <= io.lsu_axi.b.bits.resp @[quasar.scala 274:21] - _T_16.b.valid <= io.lsu_axi.b.valid @[quasar.scala 274:21] - io.lsu_axi.b.ready <= _T_16.b.ready @[quasar.scala 274:21] - io.lsu_axi.w.bits.last <= _T_16.w.bits.last @[quasar.scala 274:21] - io.lsu_axi.w.bits.strb <= _T_16.w.bits.strb @[quasar.scala 274:21] - io.lsu_axi.w.bits.data <= _T_16.w.bits.data @[quasar.scala 274:21] - io.lsu_axi.w.valid <= _T_16.w.valid @[quasar.scala 274:21] - _T_16.w.ready <= io.lsu_axi.w.ready @[quasar.scala 274:21] - io.lsu_axi.aw.bits.qos <= _T_16.aw.bits.qos @[quasar.scala 274:21] - io.lsu_axi.aw.bits.prot <= _T_16.aw.bits.prot @[quasar.scala 274:21] - io.lsu_axi.aw.bits.cache <= _T_16.aw.bits.cache @[quasar.scala 274:21] - io.lsu_axi.aw.bits.lock <= _T_16.aw.bits.lock @[quasar.scala 274:21] - io.lsu_axi.aw.bits.burst <= _T_16.aw.bits.burst @[quasar.scala 274:21] - io.lsu_axi.aw.bits.size <= _T_16.aw.bits.size @[quasar.scala 274:21] - io.lsu_axi.aw.bits.len <= _T_16.aw.bits.len @[quasar.scala 274:21] - io.lsu_axi.aw.bits.region <= _T_16.aw.bits.region @[quasar.scala 274:21] - io.lsu_axi.aw.bits.addr <= _T_16.aw.bits.addr @[quasar.scala 274:21] - io.lsu_axi.aw.bits.id <= _T_16.aw.bits.id @[quasar.scala 274:21] - io.lsu_axi.aw.valid <= _T_16.aw.valid @[quasar.scala 274:21] - _T_16.aw.ready <= io.lsu_axi.aw.ready @[quasar.scala 274:21] + wire _T_13 : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}} @[quasar.scala 277:42] + _T_13.out.hwdata <= UInt<64>("h00") @[quasar.scala 277:42] + _T_13.out.hwrite <= UInt<1>("h00") @[quasar.scala 277:42] + _T_13.out.htrans <= UInt<2>("h00") @[quasar.scala 277:42] + _T_13.out.hsize <= UInt<3>("h00") @[quasar.scala 277:42] + _T_13.out.hprot <= UInt<4>("h00") @[quasar.scala 277:42] + _T_13.out.hmastlock <= UInt<1>("h00") @[quasar.scala 277:42] + _T_13.out.hburst <= UInt<3>("h00") @[quasar.scala 277:42] + _T_13.out.haddr <= UInt<32>("h00") @[quasar.scala 277:42] + _T_13.in.hresp <= UInt<1>("h00") @[quasar.scala 277:42] + _T_13.in.hready <= UInt<1>("h00") @[quasar.scala 277:42] + _T_13.in.hrdata <= UInt<64>("h00") @[quasar.scala 277:42] + io.lsu_ahb.out.hwdata <= _T_13.out.hwdata @[quasar.scala 277:27] + io.lsu_ahb.out.hwrite <= _T_13.out.hwrite @[quasar.scala 277:27] + io.lsu_ahb.out.htrans <= _T_13.out.htrans @[quasar.scala 277:27] + io.lsu_ahb.out.hsize <= _T_13.out.hsize @[quasar.scala 277:27] + io.lsu_ahb.out.hprot <= _T_13.out.hprot @[quasar.scala 277:27] + io.lsu_ahb.out.hmastlock <= _T_13.out.hmastlock @[quasar.scala 277:27] + io.lsu_ahb.out.hburst <= _T_13.out.hburst @[quasar.scala 277:27] + io.lsu_ahb.out.haddr <= _T_13.out.haddr @[quasar.scala 277:27] + _T_13.in.hresp <= io.lsu_ahb.in.hresp @[quasar.scala 277:27] + _T_13.in.hready <= io.lsu_ahb.in.hready @[quasar.scala 277:27] + _T_13.in.hrdata <= io.lsu_ahb.in.hrdata @[quasar.scala 277:27] + wire _T_14 : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}} @[quasar.scala 278:42] + _T_14.out.hwdata <= UInt<64>("h00") @[quasar.scala 278:42] + _T_14.out.hwrite <= UInt<1>("h00") @[quasar.scala 278:42] + _T_14.out.htrans <= UInt<2>("h00") @[quasar.scala 278:42] + _T_14.out.hsize <= UInt<3>("h00") @[quasar.scala 278:42] + _T_14.out.hprot <= UInt<4>("h00") @[quasar.scala 278:42] + _T_14.out.hmastlock <= UInt<1>("h00") @[quasar.scala 278:42] + _T_14.out.hburst <= UInt<3>("h00") @[quasar.scala 278:42] + _T_14.out.haddr <= UInt<32>("h00") @[quasar.scala 278:42] + _T_14.in.hresp <= UInt<1>("h00") @[quasar.scala 278:42] + _T_14.in.hready <= UInt<1>("h00") @[quasar.scala 278:42] + _T_14.in.hrdata <= UInt<64>("h00") @[quasar.scala 278:42] + io.ifu_ahb.out.hwdata <= _T_14.out.hwdata @[quasar.scala 278:27] + io.ifu_ahb.out.hwrite <= _T_14.out.hwrite @[quasar.scala 278:27] + io.ifu_ahb.out.htrans <= _T_14.out.htrans @[quasar.scala 278:27] + io.ifu_ahb.out.hsize <= _T_14.out.hsize @[quasar.scala 278:27] + io.ifu_ahb.out.hprot <= _T_14.out.hprot @[quasar.scala 278:27] + io.ifu_ahb.out.hmastlock <= _T_14.out.hmastlock @[quasar.scala 278:27] + io.ifu_ahb.out.hburst <= _T_14.out.hburst @[quasar.scala 278:27] + io.ifu_ahb.out.haddr <= _T_14.out.haddr @[quasar.scala 278:27] + _T_14.in.hresp <= io.ifu_ahb.in.hresp @[quasar.scala 278:27] + _T_14.in.hready <= io.ifu_ahb.in.hready @[quasar.scala 278:27] + _T_14.in.hrdata <= io.ifu_ahb.in.hrdata @[quasar.scala 278:27] + wire _T_15 : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}} @[quasar.scala 279:42] + _T_15.out.hwdata <= UInt<64>("h00") @[quasar.scala 279:42] + _T_15.out.hwrite <= UInt<1>("h00") @[quasar.scala 279:42] + _T_15.out.htrans <= UInt<2>("h00") @[quasar.scala 279:42] + _T_15.out.hsize <= UInt<3>("h00") @[quasar.scala 279:42] + _T_15.out.hprot <= UInt<4>("h00") @[quasar.scala 279:42] + _T_15.out.hmastlock <= UInt<1>("h00") @[quasar.scala 279:42] + _T_15.out.hburst <= UInt<3>("h00") @[quasar.scala 279:42] + _T_15.out.haddr <= UInt<32>("h00") @[quasar.scala 279:42] + _T_15.in.hresp <= UInt<1>("h00") @[quasar.scala 279:42] + _T_15.in.hready <= UInt<1>("h00") @[quasar.scala 279:42] + _T_15.in.hrdata <= UInt<64>("h00") @[quasar.scala 279:42] + io.sb_ahb.out.hwdata <= _T_15.out.hwdata @[quasar.scala 279:27] + io.sb_ahb.out.hwrite <= _T_15.out.hwrite @[quasar.scala 279:27] + io.sb_ahb.out.htrans <= _T_15.out.htrans @[quasar.scala 279:27] + io.sb_ahb.out.hsize <= _T_15.out.hsize @[quasar.scala 279:27] + io.sb_ahb.out.hprot <= _T_15.out.hprot @[quasar.scala 279:27] + io.sb_ahb.out.hmastlock <= _T_15.out.hmastlock @[quasar.scala 279:27] + io.sb_ahb.out.hburst <= _T_15.out.hburst @[quasar.scala 279:27] + io.sb_ahb.out.haddr <= _T_15.out.haddr @[quasar.scala 279:27] + _T_15.in.hresp <= io.sb_ahb.in.hresp @[quasar.scala 279:27] + _T_15.in.hready <= io.sb_ahb.in.hready @[quasar.scala 279:27] + _T_15.in.hrdata <= io.sb_ahb.in.hrdata @[quasar.scala 279:27] + wire _T_16 : {flip sig : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, flip hsel : UInt<1>, flip hreadyin : UInt<1>} @[quasar.scala 280:42] + _T_16.hreadyin <= UInt<1>("h00") @[quasar.scala 280:42] + _T_16.hsel <= UInt<1>("h00") @[quasar.scala 280:42] + _T_16.sig.out.hwdata <= UInt<64>("h00") @[quasar.scala 280:42] + _T_16.sig.out.hwrite <= UInt<1>("h00") @[quasar.scala 280:42] + _T_16.sig.out.htrans <= UInt<2>("h00") @[quasar.scala 280:42] + _T_16.sig.out.hsize <= UInt<3>("h00") @[quasar.scala 280:42] + _T_16.sig.out.hprot <= UInt<4>("h00") @[quasar.scala 280:42] + _T_16.sig.out.hmastlock <= UInt<1>("h00") @[quasar.scala 280:42] + _T_16.sig.out.hburst <= UInt<3>("h00") @[quasar.scala 280:42] + _T_16.sig.out.haddr <= UInt<32>("h00") @[quasar.scala 280:42] + _T_16.sig.in.hresp <= UInt<1>("h00") @[quasar.scala 280:42] + _T_16.sig.in.hready <= UInt<1>("h00") @[quasar.scala 280:42] + _T_16.sig.in.hrdata <= UInt<64>("h00") @[quasar.scala 280:42] + _T_16.hreadyin <= io.dma_ahb.hreadyin @[quasar.scala 280:27] + _T_16.hsel <= io.dma_ahb.hsel @[quasar.scala 280:27] + _T_16.sig.out.hwdata <= io.dma_ahb.sig.out.hwdata @[quasar.scala 280:27] + _T_16.sig.out.hwrite <= io.dma_ahb.sig.out.hwrite @[quasar.scala 280:27] + _T_16.sig.out.htrans <= io.dma_ahb.sig.out.htrans @[quasar.scala 280:27] + _T_16.sig.out.hsize <= io.dma_ahb.sig.out.hsize @[quasar.scala 280:27] + _T_16.sig.out.hprot <= io.dma_ahb.sig.out.hprot @[quasar.scala 280:27] + _T_16.sig.out.hmastlock <= io.dma_ahb.sig.out.hmastlock @[quasar.scala 280:27] + _T_16.sig.out.hburst <= io.dma_ahb.sig.out.hburst @[quasar.scala 280:27] + _T_16.sig.out.haddr <= io.dma_ahb.sig.out.haddr @[quasar.scala 280:27] + io.dma_ahb.sig.in.hresp <= _T_16.sig.in.hresp @[quasar.scala 280:27] + io.dma_ahb.sig.in.hready <= _T_16.sig.in.hready @[quasar.scala 280:27] + io.dma_ahb.sig.in.hrdata <= _T_16.sig.in.hrdata @[quasar.scala 280:27] + io.dma_axi.r.bits.last <= dma_ctrl.io.dma_axi.r.bits.last @[quasar.scala 281:27] + io.dma_axi.r.bits.resp <= dma_ctrl.io.dma_axi.r.bits.resp @[quasar.scala 281:27] + io.dma_axi.r.bits.data <= dma_ctrl.io.dma_axi.r.bits.data @[quasar.scala 281:27] + io.dma_axi.r.bits.id <= dma_ctrl.io.dma_axi.r.bits.id @[quasar.scala 281:27] + io.dma_axi.r.valid <= dma_ctrl.io.dma_axi.r.valid @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.r.ready <= io.dma_axi.r.ready @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.ar.bits.qos <= io.dma_axi.ar.bits.qos @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.ar.bits.prot <= io.dma_axi.ar.bits.prot @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.ar.bits.cache <= io.dma_axi.ar.bits.cache @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.ar.bits.lock <= io.dma_axi.ar.bits.lock @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.ar.bits.burst <= io.dma_axi.ar.bits.burst @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.ar.bits.size <= io.dma_axi.ar.bits.size @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.ar.bits.len <= io.dma_axi.ar.bits.len @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.ar.bits.region <= io.dma_axi.ar.bits.region @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.ar.bits.addr <= io.dma_axi.ar.bits.addr @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.ar.bits.id <= io.dma_axi.ar.bits.id @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.ar.valid <= io.dma_axi.ar.valid @[quasar.scala 281:27] + io.dma_axi.ar.ready <= dma_ctrl.io.dma_axi.ar.ready @[quasar.scala 281:27] + io.dma_axi.b.bits.id <= dma_ctrl.io.dma_axi.b.bits.id @[quasar.scala 281:27] + io.dma_axi.b.bits.resp <= dma_ctrl.io.dma_axi.b.bits.resp @[quasar.scala 281:27] + io.dma_axi.b.valid <= dma_ctrl.io.dma_axi.b.valid @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.b.ready <= io.dma_axi.b.ready @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.w.bits.last <= io.dma_axi.w.bits.last @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.w.bits.strb <= io.dma_axi.w.bits.strb @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.w.bits.data <= io.dma_axi.w.bits.data @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.w.valid <= io.dma_axi.w.valid @[quasar.scala 281:27] + io.dma_axi.w.ready <= dma_ctrl.io.dma_axi.w.ready @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.aw.bits.qos <= io.dma_axi.aw.bits.qos @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.aw.bits.prot <= io.dma_axi.aw.bits.prot @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.aw.bits.cache <= io.dma_axi.aw.bits.cache @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.aw.bits.lock <= io.dma_axi.aw.bits.lock @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.aw.bits.burst <= io.dma_axi.aw.bits.burst @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.aw.bits.size <= io.dma_axi.aw.bits.size @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.aw.bits.len <= io.dma_axi.aw.bits.len @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.aw.bits.region <= io.dma_axi.aw.bits.region @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.aw.bits.addr <= io.dma_axi.aw.bits.addr @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.aw.bits.id <= io.dma_axi.aw.bits.id @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.aw.valid <= io.dma_axi.aw.valid @[quasar.scala 281:27] + io.dma_axi.aw.ready <= dma_ctrl.io.dma_axi.aw.ready @[quasar.scala 281:27] + dbg.io.sb_axi.r.bits.last <= io.sb_axi.r.bits.last @[quasar.scala 282:27] + dbg.io.sb_axi.r.bits.resp <= io.sb_axi.r.bits.resp @[quasar.scala 282:27] + dbg.io.sb_axi.r.bits.data <= io.sb_axi.r.bits.data @[quasar.scala 282:27] + dbg.io.sb_axi.r.bits.id <= io.sb_axi.r.bits.id @[quasar.scala 282:27] + dbg.io.sb_axi.r.valid <= io.sb_axi.r.valid @[quasar.scala 282:27] + io.sb_axi.r.ready <= dbg.io.sb_axi.r.ready @[quasar.scala 282:27] + io.sb_axi.ar.bits.qos <= dbg.io.sb_axi.ar.bits.qos @[quasar.scala 282:27] + io.sb_axi.ar.bits.prot <= dbg.io.sb_axi.ar.bits.prot @[quasar.scala 282:27] + io.sb_axi.ar.bits.cache <= dbg.io.sb_axi.ar.bits.cache @[quasar.scala 282:27] + io.sb_axi.ar.bits.lock <= dbg.io.sb_axi.ar.bits.lock @[quasar.scala 282:27] + io.sb_axi.ar.bits.burst <= dbg.io.sb_axi.ar.bits.burst @[quasar.scala 282:27] + io.sb_axi.ar.bits.size <= dbg.io.sb_axi.ar.bits.size @[quasar.scala 282:27] + io.sb_axi.ar.bits.len <= dbg.io.sb_axi.ar.bits.len @[quasar.scala 282:27] + io.sb_axi.ar.bits.region <= dbg.io.sb_axi.ar.bits.region @[quasar.scala 282:27] + io.sb_axi.ar.bits.addr <= dbg.io.sb_axi.ar.bits.addr @[quasar.scala 282:27] + io.sb_axi.ar.bits.id <= dbg.io.sb_axi.ar.bits.id @[quasar.scala 282:27] + io.sb_axi.ar.valid <= dbg.io.sb_axi.ar.valid @[quasar.scala 282:27] + dbg.io.sb_axi.ar.ready <= io.sb_axi.ar.ready @[quasar.scala 282:27] + dbg.io.sb_axi.b.bits.id <= io.sb_axi.b.bits.id @[quasar.scala 282:27] + dbg.io.sb_axi.b.bits.resp <= io.sb_axi.b.bits.resp @[quasar.scala 282:27] + dbg.io.sb_axi.b.valid <= io.sb_axi.b.valid @[quasar.scala 282:27] + io.sb_axi.b.ready <= dbg.io.sb_axi.b.ready @[quasar.scala 282:27] + io.sb_axi.w.bits.last <= dbg.io.sb_axi.w.bits.last @[quasar.scala 282:27] + io.sb_axi.w.bits.strb <= dbg.io.sb_axi.w.bits.strb @[quasar.scala 282:27] + io.sb_axi.w.bits.data <= dbg.io.sb_axi.w.bits.data @[quasar.scala 282:27] + io.sb_axi.w.valid <= dbg.io.sb_axi.w.valid @[quasar.scala 282:27] + dbg.io.sb_axi.w.ready <= io.sb_axi.w.ready @[quasar.scala 282:27] + io.sb_axi.aw.bits.qos <= dbg.io.sb_axi.aw.bits.qos @[quasar.scala 282:27] + io.sb_axi.aw.bits.prot <= dbg.io.sb_axi.aw.bits.prot @[quasar.scala 282:27] + io.sb_axi.aw.bits.cache <= dbg.io.sb_axi.aw.bits.cache @[quasar.scala 282:27] + io.sb_axi.aw.bits.lock <= dbg.io.sb_axi.aw.bits.lock @[quasar.scala 282:27] + io.sb_axi.aw.bits.burst <= dbg.io.sb_axi.aw.bits.burst @[quasar.scala 282:27] + io.sb_axi.aw.bits.size <= dbg.io.sb_axi.aw.bits.size @[quasar.scala 282:27] + io.sb_axi.aw.bits.len <= dbg.io.sb_axi.aw.bits.len @[quasar.scala 282:27] + io.sb_axi.aw.bits.region <= dbg.io.sb_axi.aw.bits.region @[quasar.scala 282:27] + io.sb_axi.aw.bits.addr <= dbg.io.sb_axi.aw.bits.addr @[quasar.scala 282:27] + io.sb_axi.aw.bits.id <= dbg.io.sb_axi.aw.bits.id @[quasar.scala 282:27] + io.sb_axi.aw.valid <= dbg.io.sb_axi.aw.valid @[quasar.scala 282:27] + dbg.io.sb_axi.aw.ready <= io.sb_axi.aw.ready @[quasar.scala 282:27] + ifu.io.ifu.r.bits.last <= io.ifu_axi.r.bits.last @[quasar.scala 283:27] + ifu.io.ifu.r.bits.resp <= io.ifu_axi.r.bits.resp @[quasar.scala 283:27] + ifu.io.ifu.r.bits.data <= io.ifu_axi.r.bits.data @[quasar.scala 283:27] + ifu.io.ifu.r.bits.id <= io.ifu_axi.r.bits.id @[quasar.scala 283:27] + ifu.io.ifu.r.valid <= io.ifu_axi.r.valid @[quasar.scala 283:27] + io.ifu_axi.r.ready <= ifu.io.ifu.r.ready @[quasar.scala 283:27] + io.ifu_axi.ar.bits.qos <= ifu.io.ifu.ar.bits.qos @[quasar.scala 283:27] + io.ifu_axi.ar.bits.prot <= ifu.io.ifu.ar.bits.prot @[quasar.scala 283:27] + io.ifu_axi.ar.bits.cache <= ifu.io.ifu.ar.bits.cache @[quasar.scala 283:27] + io.ifu_axi.ar.bits.lock <= ifu.io.ifu.ar.bits.lock @[quasar.scala 283:27] + io.ifu_axi.ar.bits.burst <= ifu.io.ifu.ar.bits.burst @[quasar.scala 283:27] + io.ifu_axi.ar.bits.size <= ifu.io.ifu.ar.bits.size @[quasar.scala 283:27] + io.ifu_axi.ar.bits.len <= ifu.io.ifu.ar.bits.len @[quasar.scala 283:27] + io.ifu_axi.ar.bits.region <= ifu.io.ifu.ar.bits.region @[quasar.scala 283:27] + io.ifu_axi.ar.bits.addr <= ifu.io.ifu.ar.bits.addr @[quasar.scala 283:27] + io.ifu_axi.ar.bits.id <= ifu.io.ifu.ar.bits.id @[quasar.scala 283:27] + io.ifu_axi.ar.valid <= ifu.io.ifu.ar.valid @[quasar.scala 283:27] + ifu.io.ifu.ar.ready <= io.ifu_axi.ar.ready @[quasar.scala 283:27] + ifu.io.ifu.b.bits.id <= io.ifu_axi.b.bits.id @[quasar.scala 283:27] + ifu.io.ifu.b.bits.resp <= io.ifu_axi.b.bits.resp @[quasar.scala 283:27] + ifu.io.ifu.b.valid <= io.ifu_axi.b.valid @[quasar.scala 283:27] + io.ifu_axi.b.ready <= ifu.io.ifu.b.ready @[quasar.scala 283:27] + io.ifu_axi.w.bits.last <= ifu.io.ifu.w.bits.last @[quasar.scala 283:27] + io.ifu_axi.w.bits.strb <= ifu.io.ifu.w.bits.strb @[quasar.scala 283:27] + io.ifu_axi.w.bits.data <= ifu.io.ifu.w.bits.data @[quasar.scala 283:27] + io.ifu_axi.w.valid <= ifu.io.ifu.w.valid @[quasar.scala 283:27] + ifu.io.ifu.w.ready <= io.ifu_axi.w.ready @[quasar.scala 283:27] + io.ifu_axi.aw.bits.qos <= ifu.io.ifu.aw.bits.qos @[quasar.scala 283:27] + io.ifu_axi.aw.bits.prot <= ifu.io.ifu.aw.bits.prot @[quasar.scala 283:27] + io.ifu_axi.aw.bits.cache <= ifu.io.ifu.aw.bits.cache @[quasar.scala 283:27] + io.ifu_axi.aw.bits.lock <= ifu.io.ifu.aw.bits.lock @[quasar.scala 283:27] + io.ifu_axi.aw.bits.burst <= ifu.io.ifu.aw.bits.burst @[quasar.scala 283:27] + io.ifu_axi.aw.bits.size <= ifu.io.ifu.aw.bits.size @[quasar.scala 283:27] + io.ifu_axi.aw.bits.len <= ifu.io.ifu.aw.bits.len @[quasar.scala 283:27] + io.ifu_axi.aw.bits.region <= ifu.io.ifu.aw.bits.region @[quasar.scala 283:27] + io.ifu_axi.aw.bits.addr <= ifu.io.ifu.aw.bits.addr @[quasar.scala 283:27] + io.ifu_axi.aw.bits.id <= ifu.io.ifu.aw.bits.id @[quasar.scala 283:27] + io.ifu_axi.aw.valid <= ifu.io.ifu.aw.valid @[quasar.scala 283:27] + ifu.io.ifu.aw.ready <= io.ifu_axi.aw.ready @[quasar.scala 283:27] + lsu.io.axi.r.bits.last <= io.lsu_axi.r.bits.last @[quasar.scala 284:27] + lsu.io.axi.r.bits.resp <= io.lsu_axi.r.bits.resp @[quasar.scala 284:27] + lsu.io.axi.r.bits.data <= io.lsu_axi.r.bits.data @[quasar.scala 284:27] + lsu.io.axi.r.bits.id <= io.lsu_axi.r.bits.id @[quasar.scala 284:27] + lsu.io.axi.r.valid <= io.lsu_axi.r.valid @[quasar.scala 284:27] + io.lsu_axi.r.ready <= lsu.io.axi.r.ready @[quasar.scala 284:27] + io.lsu_axi.ar.bits.qos <= lsu.io.axi.ar.bits.qos @[quasar.scala 284:27] + io.lsu_axi.ar.bits.prot <= lsu.io.axi.ar.bits.prot @[quasar.scala 284:27] + io.lsu_axi.ar.bits.cache <= lsu.io.axi.ar.bits.cache @[quasar.scala 284:27] + io.lsu_axi.ar.bits.lock <= lsu.io.axi.ar.bits.lock @[quasar.scala 284:27] + io.lsu_axi.ar.bits.burst <= lsu.io.axi.ar.bits.burst @[quasar.scala 284:27] + io.lsu_axi.ar.bits.size <= lsu.io.axi.ar.bits.size @[quasar.scala 284:27] + io.lsu_axi.ar.bits.len <= lsu.io.axi.ar.bits.len @[quasar.scala 284:27] + io.lsu_axi.ar.bits.region <= lsu.io.axi.ar.bits.region @[quasar.scala 284:27] + io.lsu_axi.ar.bits.addr <= lsu.io.axi.ar.bits.addr @[quasar.scala 284:27] + io.lsu_axi.ar.bits.id <= lsu.io.axi.ar.bits.id @[quasar.scala 284:27] + io.lsu_axi.ar.valid <= lsu.io.axi.ar.valid @[quasar.scala 284:27] + lsu.io.axi.ar.ready <= io.lsu_axi.ar.ready @[quasar.scala 284:27] + lsu.io.axi.b.bits.id <= io.lsu_axi.b.bits.id @[quasar.scala 284:27] + lsu.io.axi.b.bits.resp <= io.lsu_axi.b.bits.resp @[quasar.scala 284:27] + lsu.io.axi.b.valid <= io.lsu_axi.b.valid @[quasar.scala 284:27] + io.lsu_axi.b.ready <= lsu.io.axi.b.ready @[quasar.scala 284:27] + io.lsu_axi.w.bits.last <= lsu.io.axi.w.bits.last @[quasar.scala 284:27] + io.lsu_axi.w.bits.strb <= lsu.io.axi.w.bits.strb @[quasar.scala 284:27] + io.lsu_axi.w.bits.data <= lsu.io.axi.w.bits.data @[quasar.scala 284:27] + io.lsu_axi.w.valid <= lsu.io.axi.w.valid @[quasar.scala 284:27] + lsu.io.axi.w.ready <= io.lsu_axi.w.ready @[quasar.scala 284:27] + io.lsu_axi.aw.bits.qos <= lsu.io.axi.aw.bits.qos @[quasar.scala 284:27] + io.lsu_axi.aw.bits.prot <= lsu.io.axi.aw.bits.prot @[quasar.scala 284:27] + io.lsu_axi.aw.bits.cache <= lsu.io.axi.aw.bits.cache @[quasar.scala 284:27] + io.lsu_axi.aw.bits.lock <= lsu.io.axi.aw.bits.lock @[quasar.scala 284:27] + io.lsu_axi.aw.bits.burst <= lsu.io.axi.aw.bits.burst @[quasar.scala 284:27] + io.lsu_axi.aw.bits.size <= lsu.io.axi.aw.bits.size @[quasar.scala 284:27] + io.lsu_axi.aw.bits.len <= lsu.io.axi.aw.bits.len @[quasar.scala 284:27] + io.lsu_axi.aw.bits.region <= lsu.io.axi.aw.bits.region @[quasar.scala 284:27] + io.lsu_axi.aw.bits.addr <= lsu.io.axi.aw.bits.addr @[quasar.scala 284:27] + io.lsu_axi.aw.bits.id <= lsu.io.axi.aw.bits.id @[quasar.scala 284:27] + io.lsu_axi.aw.valid <= lsu.io.axi.aw.valid @[quasar.scala 284:27] + lsu.io.axi.aw.ready <= io.lsu_axi.aw.ready @[quasar.scala 284:27] diff --git a/quasar.v b/quasar.v index 21ee13de..81014d61 100644 --- a/quasar.v +++ b/quasar.v @@ -57,6 +57,7 @@ module ifu_mem_ctl( output io_ifu_axi_ar_valid, output [2:0] io_ifu_axi_ar_bits_id, output [31:0] io_ifu_axi_ar_bits_addr, + output [3:0] io_ifu_axi_ar_bits_region, output io_ifu_axi_r_ready, input io_ifu_axi_r_valid, input [2:0] io_ifu_axi_r_bits_id, @@ -1928,6 +1929,7 @@ module ifu_mem_ctl( wire _T_318 = ~stream_miss_f; // @[ifu_mem_ctl.scala 226:106] reg ifc_region_acc_fault_f; // @[ifu_mem_ctl.scala 232:68] reg [2:0] bus_rd_addr_count; // @[ifu_mem_ctl.scala 540:55] + wire [28:0] ifu_ic_req_addr_f = {miss_addr,bus_rd_addr_count}; // @[Cat.scala 29:58] wire _T_325 = _T_239 | _T_2268; // @[ifu_mem_ctl.scala 234:55] wire _T_328 = _T_325 & _T_56; // @[ifu_mem_ctl.scala 234:82] wire _T_2289 = ~ifu_bus_rid_ff[0]; // @[ifu_mem_ctl.scala 378:55] @@ -5660,6 +5662,7 @@ module ifu_mem_ctl( assign io_ifu_axi_ar_valid = ifu_bus_cmd_valid; // @[ifu_mem_ctl.scala 497:23] assign io_ifu_axi_ar_bits_id = bus_rd_addr_count & _T_2608; // @[ifu_mem_ctl.scala 498:25] assign io_ifu_axi_ar_bits_addr = _T_2610 & _T_2612; // @[ifu_mem_ctl.scala 499:27] + assign io_ifu_axi_ar_bits_region = ifu_ic_req_addr_f[28:25]; // @[ifu_mem_ctl.scala 502:29] assign io_ifu_axi_r_ready = 1'h1; // @[ifu_mem_ctl.scala 504:22] assign io_iccm_rw_addr = _T_3110 ? io_dma_mem_ctl_dma_mem_addr[15:1] : _T_3117; // @[ifu_mem_ctl.scala 599:19] assign io_iccm_buf_correct_ecc = iccm_correct_ecc & _T_2497; // @[ifu_mem_ctl.scala 395:27] @@ -44530,6 +44533,7 @@ module ifu( output io_ifu_ar_valid, output [2:0] io_ifu_ar_bits_id, output [31:0] io_ifu_ar_bits_addr, + output [3:0] io_ifu_ar_bits_region, input io_ifu_r_valid, input [2:0] io_ifu_r_bits_id, input [63:0] io_ifu_r_bits_data, @@ -44588,6 +44592,7 @@ module ifu( wire mem_ctl_io_ifu_axi_ar_valid; // @[ifu.scala 34:23] wire [2:0] mem_ctl_io_ifu_axi_ar_bits_id; // @[ifu.scala 34:23] wire [31:0] mem_ctl_io_ifu_axi_ar_bits_addr; // @[ifu.scala 34:23] + wire [3:0] mem_ctl_io_ifu_axi_ar_bits_region; // @[ifu.scala 34:23] wire mem_ctl_io_ifu_axi_r_ready; // @[ifu.scala 34:23] wire mem_ctl_io_ifu_axi_r_valid; // @[ifu.scala 34:23] wire [2:0] mem_ctl_io_ifu_axi_r_bits_id; // @[ifu.scala 34:23] @@ -44803,6 +44808,7 @@ module ifu( .io_ifu_axi_ar_valid(mem_ctl_io_ifu_axi_ar_valid), .io_ifu_axi_ar_bits_id(mem_ctl_io_ifu_axi_ar_bits_id), .io_ifu_axi_ar_bits_addr(mem_ctl_io_ifu_axi_ar_bits_addr), + .io_ifu_axi_ar_bits_region(mem_ctl_io_ifu_axi_ar_bits_region), .io_ifu_axi_r_ready(mem_ctl_io_ifu_axi_r_ready), .io_ifu_axi_r_valid(mem_ctl_io_ifu_axi_r_valid), .io_ifu_axi_r_bits_id(mem_ctl_io_ifu_axi_r_bits_id), @@ -45043,6 +45049,7 @@ module ifu( assign io_ifu_ar_valid = mem_ctl_io_ifu_axi_ar_valid; // @[ifu.scala 103:22] assign io_ifu_ar_bits_id = mem_ctl_io_ifu_axi_ar_bits_id; // @[ifu.scala 103:22] assign io_ifu_ar_bits_addr = mem_ctl_io_ifu_axi_ar_bits_addr; // @[ifu.scala 103:22] + assign io_ifu_ar_bits_region = mem_ctl_io_ifu_axi_ar_bits_region; // @[ifu.scala 103:22] assign io_iccm_dma_ecc_error = mem_ctl_io_iccm_dma_ecc_error; // @[ifu.scala 113:25] assign io_iccm_dma_rvalid = mem_ctl_io_iccm_dma_rvalid; // @[ifu.scala 114:22] assign io_iccm_dma_rdata = mem_ctl_io_iccm_dma_rdata; // @[ifu.scala 115:21] @@ -50517,7 +50524,6 @@ module csr_tlu( output io_dec_tlu_misc_clk_override, output io_dec_tlu_dec_clk_override, output io_dec_tlu_lsu_clk_override, - output io_dec_tlu_bus_clk_override, output io_dec_tlu_pic_clk_override, output io_dec_tlu_dccm_clk_override, output io_dec_tlu_icm_clk_override, @@ -50540,6 +50546,7 @@ module csr_tlu( input io_lsu_imprecise_error_load_any, input io_lsu_imprecise_error_store_any, output [31:0] io_dec_tlu_mrac_ff, + output io_dec_tlu_wb_coalescing_disable, output io_dec_tlu_bpred_disable, output io_dec_tlu_sideeffect_posted_disable, output io_dec_tlu_core_ecc_disable, @@ -50924,13 +50931,13 @@ module csr_tlu( wire _T_2 = ~io_rfpc_i0_r; // @[dec_tlu_ctl.scala 1431:68] wire _T_5 = io_dec_csr_wraddr_r == 12'h300; // @[dec_tlu_ctl.scala 1432:71] wire wr_mstatus_r = io_dec_csr_wen_r_mod & _T_5; // @[dec_tlu_ctl.scala 1432:42] - wire _T_488 = io_dec_csr_wraddr_r == 12'h7c6; // @[dec_tlu_ctl.scala 1818:68] - wire wr_mpmc_r = io_dec_csr_wen_r_mod & _T_488; // @[dec_tlu_ctl.scala 1818:39] - wire _T_500 = ~io_dec_csr_wrdata_r[1]; // @[dec_tlu_ctl.scala 1826:37] + wire _T_498 = io_dec_csr_wraddr_r == 12'h7c6; // @[dec_tlu_ctl.scala 1818:68] + wire wr_mpmc_r = io_dec_csr_wen_r_mod & _T_498; // @[dec_tlu_ctl.scala 1818:39] + wire _T_510 = ~io_dec_csr_wrdata_r[1]; // @[dec_tlu_ctl.scala 1826:37] reg mpmc_b; // @[dec_tlu_ctl.scala 1828:44] wire mpmc = ~mpmc_b; // @[dec_tlu_ctl.scala 1831:10] - wire _T_501 = ~mpmc; // @[dec_tlu_ctl.scala 1826:62] - wire mpmc_b_ns = wr_mpmc_r ? _T_500 : _T_501; // @[dec_tlu_ctl.scala 1826:18] + wire _T_511 = ~mpmc; // @[dec_tlu_ctl.scala 1826:62] + wire mpmc_b_ns = wr_mpmc_r ? _T_510 : _T_511; // @[dec_tlu_ctl.scala 1826:18] wire _T_6 = ~mpmc_b_ns; // @[dec_tlu_ctl.scala 1435:28] wire set_mie_pmu_fw_halt = _T_6 & io_fw_halt_req; // @[dec_tlu_ctl.scala 1435:39] wire _T_7 = ~wr_mstatus_r; // @[dec_tlu_ctl.scala 1438:5] @@ -50965,24 +50972,24 @@ module csr_tlu( wire _T_58 = io_dec_csr_wraddr_r == 12'h305; // @[dec_tlu_ctl.scala 1457:69] reg [30:0] _T_62; // @[lib.scala 374:16] reg [31:0] mdccmect; // @[lib.scala 374:16] - wire [62:0] _T_564 = 63'hffffffff << mdccmect[31:27]; // @[dec_tlu_ctl.scala 1878:41] - wire [31:0] _T_566 = {5'h0,mdccmect[26:0]}; // @[Cat.scala 29:58] - wire [62:0] _GEN_9 = {{31'd0}, _T_566}; // @[dec_tlu_ctl.scala 1878:61] - wire [62:0] _T_567 = _T_564 & _GEN_9; // @[dec_tlu_ctl.scala 1878:61] - wire mdccme_ce_req = |_T_567; // @[dec_tlu_ctl.scala 1878:94] + wire [62:0] _T_574 = 63'hffffffff << mdccmect[31:27]; // @[dec_tlu_ctl.scala 1878:41] + wire [31:0] _T_576 = {5'h0,mdccmect[26:0]}; // @[Cat.scala 29:58] + wire [62:0] _GEN_9 = {{31'd0}, _T_576}; // @[dec_tlu_ctl.scala 1878:61] + wire [62:0] _T_577 = _T_574 & _GEN_9; // @[dec_tlu_ctl.scala 1878:61] + wire mdccme_ce_req = |_T_577; // @[dec_tlu_ctl.scala 1878:94] reg [31:0] miccmect; // @[lib.scala 374:16] - wire [62:0] _T_544 = 63'hffffffff << miccmect[31:27]; // @[dec_tlu_ctl.scala 1863:40] - wire [31:0] _T_546 = {5'h0,miccmect[26:0]}; // @[Cat.scala 29:58] - wire [62:0] _GEN_10 = {{31'd0}, _T_546}; // @[dec_tlu_ctl.scala 1863:60] - wire [62:0] _T_547 = _T_544 & _GEN_10; // @[dec_tlu_ctl.scala 1863:60] - wire miccme_ce_req = |_T_547; // @[dec_tlu_ctl.scala 1863:93] + wire [62:0] _T_554 = 63'hffffffff << miccmect[31:27]; // @[dec_tlu_ctl.scala 1863:40] + wire [31:0] _T_556 = {5'h0,miccmect[26:0]}; // @[Cat.scala 29:58] + wire [62:0] _GEN_10 = {{31'd0}, _T_556}; // @[dec_tlu_ctl.scala 1863:60] + wire [62:0] _T_557 = _T_554 & _GEN_10; // @[dec_tlu_ctl.scala 1863:60] + wire miccme_ce_req = |_T_557; // @[dec_tlu_ctl.scala 1863:93] wire _T_63 = mdccme_ce_req | miccme_ce_req; // @[dec_tlu_ctl.scala 1471:30] reg [31:0] micect; // @[lib.scala 374:16] - wire [62:0] _T_522 = 63'hffffffff << micect[31:27]; // @[dec_tlu_ctl.scala 1848:39] - wire [31:0] _T_524 = {5'h0,micect[26:0]}; // @[Cat.scala 29:58] - wire [62:0] _GEN_11 = {{31'd0}, _T_524}; // @[dec_tlu_ctl.scala 1848:57] - wire [62:0] _T_525 = _T_522 & _GEN_11; // @[dec_tlu_ctl.scala 1848:57] - wire mice_ce_req = |_T_525; // @[dec_tlu_ctl.scala 1848:88] + wire [62:0] _T_532 = 63'hffffffff << micect[31:27]; // @[dec_tlu_ctl.scala 1848:39] + wire [31:0] _T_534 = {5'h0,micect[26:0]}; // @[Cat.scala 29:58] + wire [62:0] _GEN_11 = {{31'd0}, _T_534}; // @[dec_tlu_ctl.scala 1848:57] + wire [62:0] _T_535 = _T_532 & _GEN_11; // @[dec_tlu_ctl.scala 1848:57] + wire mice_ce_req = |_T_535; // @[dec_tlu_ctl.scala 1848:88] wire ce_int = _T_63 | mice_ce_req; // @[dec_tlu_ctl.scala 1471:46] wire [2:0] _T_65 = {io_mexintpend,io_timer_int_sync,io_soft_int_sync}; // @[Cat.scala 29:58] wire [2:0] _T_67 = {ce_int,io_dec_timer_t0_pulse,io_dec_timer_t1_pulse}; // @[Cat.scala 29:58] @@ -51174,430 +51181,424 @@ module csr_tlu( reg [8:0] mcgc; // @[lib.scala 374:16] wire _T_337 = io_dec_csr_wraddr_r == 12'h7f9; // @[dec_tlu_ctl.scala 1724:68] reg [14:0] mfdc_int; // @[lib.scala 374:16] - wire [2:0] _T_341 = ~io_dec_csr_wrdata_r[18:16]; // @[dec_tlu_ctl.scala 1737:19] - wire [2:0] _T_345 = ~mfdc_int[14:12]; // @[dec_tlu_ctl.scala 1738:19] - wire [18:0] mfdc = {_T_345,4'h0,mfdc_int[11:0]}; // @[Cat.scala 29:58] - wire _T_357 = io_dec_csr_wraddr_r == 12'h7c2; // @[dec_tlu_ctl.scala 1757:77] - wire _T_358 = io_dec_csr_wen_r_mod & _T_357; // @[dec_tlu_ctl.scala 1757:48] - wire _T_360 = _T_358 & _T_297; // @[dec_tlu_ctl.scala 1757:87] - wire _T_361 = ~io_take_ext_int_start; // @[dec_tlu_ctl.scala 1757:113] - wire _T_364 = io_dec_csr_wraddr_r == 12'h7c0; // @[dec_tlu_ctl.scala 1764:68] - wire _T_368 = ~io_dec_csr_wrdata_r[31]; // @[dec_tlu_ctl.scala 1767:71] - wire _T_369 = io_dec_csr_wrdata_r[30] & _T_368; // @[dec_tlu_ctl.scala 1767:69] - wire _T_373 = ~io_dec_csr_wrdata_r[29]; // @[dec_tlu_ctl.scala 1768:73] - wire _T_374 = io_dec_csr_wrdata_r[28] & _T_373; // @[dec_tlu_ctl.scala 1768:71] - wire _T_378 = ~io_dec_csr_wrdata_r[27]; // @[dec_tlu_ctl.scala 1769:73] - wire _T_379 = io_dec_csr_wrdata_r[26] & _T_378; // @[dec_tlu_ctl.scala 1769:71] - wire _T_383 = ~io_dec_csr_wrdata_r[25]; // @[dec_tlu_ctl.scala 1770:73] - wire _T_384 = io_dec_csr_wrdata_r[24] & _T_383; // @[dec_tlu_ctl.scala 1770:71] - wire _T_388 = ~io_dec_csr_wrdata_r[23]; // @[dec_tlu_ctl.scala 1771:73] - wire _T_389 = io_dec_csr_wrdata_r[22] & _T_388; // @[dec_tlu_ctl.scala 1771:71] - wire _T_393 = ~io_dec_csr_wrdata_r[21]; // @[dec_tlu_ctl.scala 1772:73] - wire _T_394 = io_dec_csr_wrdata_r[20] & _T_393; // @[dec_tlu_ctl.scala 1772:71] - wire _T_398 = ~io_dec_csr_wrdata_r[19]; // @[dec_tlu_ctl.scala 1773:73] - wire _T_399 = io_dec_csr_wrdata_r[18] & _T_398; // @[dec_tlu_ctl.scala 1773:71] - wire _T_403 = ~io_dec_csr_wrdata_r[17]; // @[dec_tlu_ctl.scala 1774:73] - wire _T_404 = io_dec_csr_wrdata_r[16] & _T_403; // @[dec_tlu_ctl.scala 1774:71] - wire _T_408 = ~io_dec_csr_wrdata_r[15]; // @[dec_tlu_ctl.scala 1775:73] - wire _T_409 = io_dec_csr_wrdata_r[14] & _T_408; // @[dec_tlu_ctl.scala 1775:71] - wire _T_413 = ~io_dec_csr_wrdata_r[13]; // @[dec_tlu_ctl.scala 1776:73] - wire _T_414 = io_dec_csr_wrdata_r[12] & _T_413; // @[dec_tlu_ctl.scala 1776:71] - wire _T_418 = ~io_dec_csr_wrdata_r[11]; // @[dec_tlu_ctl.scala 1777:73] - wire _T_419 = io_dec_csr_wrdata_r[10] & _T_418; // @[dec_tlu_ctl.scala 1777:71] - wire _T_423 = ~io_dec_csr_wrdata_r[9]; // @[dec_tlu_ctl.scala 1778:73] - wire _T_424 = io_dec_csr_wrdata_r[8] & _T_423; // @[dec_tlu_ctl.scala 1778:70] - wire _T_428 = ~io_dec_csr_wrdata_r[7]; // @[dec_tlu_ctl.scala 1779:73] - wire _T_429 = io_dec_csr_wrdata_r[6] & _T_428; // @[dec_tlu_ctl.scala 1779:70] - wire _T_433 = ~io_dec_csr_wrdata_r[5]; // @[dec_tlu_ctl.scala 1780:73] - wire _T_434 = io_dec_csr_wrdata_r[4] & _T_433; // @[dec_tlu_ctl.scala 1780:70] - wire _T_438 = ~io_dec_csr_wrdata_r[3]; // @[dec_tlu_ctl.scala 1781:73] - wire _T_439 = io_dec_csr_wrdata_r[2] & _T_438; // @[dec_tlu_ctl.scala 1781:70] - wire _T_444 = io_dec_csr_wrdata_r[0] & _T_500; // @[dec_tlu_ctl.scala 1782:70] - wire [7:0] _T_451 = {io_dec_csr_wrdata_r[7],_T_429,io_dec_csr_wrdata_r[5],_T_434,io_dec_csr_wrdata_r[3],_T_439,io_dec_csr_wrdata_r[1],_T_444}; // @[Cat.scala 29:58] - wire [15:0] _T_459 = {io_dec_csr_wrdata_r[15],_T_409,io_dec_csr_wrdata_r[13],_T_414,io_dec_csr_wrdata_r[11],_T_419,io_dec_csr_wrdata_r[9],_T_424,_T_451}; // @[Cat.scala 29:58] - wire [7:0] _T_466 = {io_dec_csr_wrdata_r[23],_T_389,io_dec_csr_wrdata_r[21],_T_394,io_dec_csr_wrdata_r[19],_T_399,io_dec_csr_wrdata_r[17],_T_404}; // @[Cat.scala 29:58] - wire [15:0] _T_474 = {io_dec_csr_wrdata_r[31],_T_369,io_dec_csr_wrdata_r[29],_T_374,io_dec_csr_wrdata_r[27],_T_379,io_dec_csr_wrdata_r[25],_T_384,_T_466}; // @[Cat.scala 29:58] + wire [2:0] _T_341 = ~io_dec_csr_wrdata_r[18:16]; // @[dec_tlu_ctl.scala 1733:20] + wire _T_344 = ~io_dec_csr_wrdata_r[6]; // @[dec_tlu_ctl.scala 1733:75] + wire [6:0] _T_346 = {_T_344,io_dec_csr_wrdata_r[5:0]}; // @[Cat.scala 29:58] + wire [7:0] _T_347 = {_T_341,io_dec_csr_wrdata_r[11:7]}; // @[Cat.scala 29:58] + wire [2:0] _T_350 = ~mfdc_int[14:12]; // @[dec_tlu_ctl.scala 1734:20] + wire _T_353 = ~mfdc_int[6]; // @[dec_tlu_ctl.scala 1734:63] + wire [18:0] mfdc = {_T_350,4'h0,mfdc_int[11:7],_T_353,mfdc_int[5:0]}; // @[Cat.scala 29:58] + wire _T_367 = io_dec_csr_wraddr_r == 12'h7c2; // @[dec_tlu_ctl.scala 1757:77] + wire _T_368 = io_dec_csr_wen_r_mod & _T_367; // @[dec_tlu_ctl.scala 1757:48] + wire _T_370 = _T_368 & _T_297; // @[dec_tlu_ctl.scala 1757:87] + wire _T_371 = ~io_take_ext_int_start; // @[dec_tlu_ctl.scala 1757:113] + wire _T_374 = io_dec_csr_wraddr_r == 12'h7c0; // @[dec_tlu_ctl.scala 1764:68] + wire _T_378 = ~io_dec_csr_wrdata_r[31]; // @[dec_tlu_ctl.scala 1767:71] + wire _T_379 = io_dec_csr_wrdata_r[30] & _T_378; // @[dec_tlu_ctl.scala 1767:69] + wire _T_383 = ~io_dec_csr_wrdata_r[29]; // @[dec_tlu_ctl.scala 1768:73] + wire _T_384 = io_dec_csr_wrdata_r[28] & _T_383; // @[dec_tlu_ctl.scala 1768:71] + wire _T_388 = ~io_dec_csr_wrdata_r[27]; // @[dec_tlu_ctl.scala 1769:73] + wire _T_389 = io_dec_csr_wrdata_r[26] & _T_388; // @[dec_tlu_ctl.scala 1769:71] + wire _T_393 = ~io_dec_csr_wrdata_r[25]; // @[dec_tlu_ctl.scala 1770:73] + wire _T_394 = io_dec_csr_wrdata_r[24] & _T_393; // @[dec_tlu_ctl.scala 1770:71] + wire _T_398 = ~io_dec_csr_wrdata_r[23]; // @[dec_tlu_ctl.scala 1771:73] + wire _T_399 = io_dec_csr_wrdata_r[22] & _T_398; // @[dec_tlu_ctl.scala 1771:71] + wire _T_403 = ~io_dec_csr_wrdata_r[21]; // @[dec_tlu_ctl.scala 1772:73] + wire _T_404 = io_dec_csr_wrdata_r[20] & _T_403; // @[dec_tlu_ctl.scala 1772:71] + wire _T_408 = ~io_dec_csr_wrdata_r[19]; // @[dec_tlu_ctl.scala 1773:73] + wire _T_409 = io_dec_csr_wrdata_r[18] & _T_408; // @[dec_tlu_ctl.scala 1773:71] + wire _T_413 = ~io_dec_csr_wrdata_r[17]; // @[dec_tlu_ctl.scala 1774:73] + wire _T_414 = io_dec_csr_wrdata_r[16] & _T_413; // @[dec_tlu_ctl.scala 1774:71] + wire _T_418 = ~io_dec_csr_wrdata_r[15]; // @[dec_tlu_ctl.scala 1775:73] + wire _T_419 = io_dec_csr_wrdata_r[14] & _T_418; // @[dec_tlu_ctl.scala 1775:71] + wire _T_423 = ~io_dec_csr_wrdata_r[13]; // @[dec_tlu_ctl.scala 1776:73] + wire _T_424 = io_dec_csr_wrdata_r[12] & _T_423; // @[dec_tlu_ctl.scala 1776:71] + wire _T_428 = ~io_dec_csr_wrdata_r[11]; // @[dec_tlu_ctl.scala 1777:73] + wire _T_429 = io_dec_csr_wrdata_r[10] & _T_428; // @[dec_tlu_ctl.scala 1777:71] + wire _T_433 = ~io_dec_csr_wrdata_r[9]; // @[dec_tlu_ctl.scala 1778:73] + wire _T_434 = io_dec_csr_wrdata_r[8] & _T_433; // @[dec_tlu_ctl.scala 1778:70] + wire _T_438 = ~io_dec_csr_wrdata_r[7]; // @[dec_tlu_ctl.scala 1779:73] + wire _T_439 = io_dec_csr_wrdata_r[6] & _T_438; // @[dec_tlu_ctl.scala 1779:70] + wire _T_443 = ~io_dec_csr_wrdata_r[5]; // @[dec_tlu_ctl.scala 1780:73] + wire _T_444 = io_dec_csr_wrdata_r[4] & _T_443; // @[dec_tlu_ctl.scala 1780:70] + wire _T_448 = ~io_dec_csr_wrdata_r[3]; // @[dec_tlu_ctl.scala 1781:73] + wire _T_449 = io_dec_csr_wrdata_r[2] & _T_448; // @[dec_tlu_ctl.scala 1781:70] + wire _T_454 = io_dec_csr_wrdata_r[0] & _T_510; // @[dec_tlu_ctl.scala 1782:70] + wire [7:0] _T_461 = {io_dec_csr_wrdata_r[7],_T_439,io_dec_csr_wrdata_r[5],_T_444,io_dec_csr_wrdata_r[3],_T_449,io_dec_csr_wrdata_r[1],_T_454}; // @[Cat.scala 29:58] + wire [15:0] _T_469 = {io_dec_csr_wrdata_r[15],_T_419,io_dec_csr_wrdata_r[13],_T_424,io_dec_csr_wrdata_r[11],_T_429,io_dec_csr_wrdata_r[9],_T_434,_T_461}; // @[Cat.scala 29:58] + wire [7:0] _T_476 = {io_dec_csr_wrdata_r[23],_T_399,io_dec_csr_wrdata_r[21],_T_404,io_dec_csr_wrdata_r[19],_T_409,io_dec_csr_wrdata_r[17],_T_414}; // @[Cat.scala 29:58] + wire [15:0] _T_484 = {io_dec_csr_wrdata_r[31],_T_379,io_dec_csr_wrdata_r[29],_T_384,io_dec_csr_wrdata_r[27],_T_389,io_dec_csr_wrdata_r[25],_T_394,_T_476}; // @[Cat.scala 29:58] reg [31:0] mrac; // @[lib.scala 374:16] - wire _T_477 = io_dec_csr_wraddr_r == 12'hbc0; // @[dec_tlu_ctl.scala 1795:69] - wire wr_mdeau_r = io_dec_csr_wen_r_mod & _T_477; // @[dec_tlu_ctl.scala 1795:40] - wire _T_478 = ~wr_mdeau_r; // @[dec_tlu_ctl.scala 1805:59] - wire _T_479 = io_mdseac_locked_f & _T_478; // @[dec_tlu_ctl.scala 1805:57] - wire _T_481 = io_lsu_imprecise_error_store_any | io_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 1807:49] - wire _T_482 = ~io_nmi_int_detected_f; // @[dec_tlu_ctl.scala 1807:86] - wire _T_483 = _T_481 & _T_482; // @[dec_tlu_ctl.scala 1807:84] - wire _T_484 = ~io_mdseac_locked_f; // @[dec_tlu_ctl.scala 1807:111] - wire mdseac_en = _T_483 & _T_484; // @[dec_tlu_ctl.scala 1807:109] + wire _T_487 = io_dec_csr_wraddr_r == 12'hbc0; // @[dec_tlu_ctl.scala 1795:69] + wire wr_mdeau_r = io_dec_csr_wen_r_mod & _T_487; // @[dec_tlu_ctl.scala 1795:40] + wire _T_488 = ~wr_mdeau_r; // @[dec_tlu_ctl.scala 1805:59] + wire _T_489 = io_mdseac_locked_f & _T_488; // @[dec_tlu_ctl.scala 1805:57] + wire _T_491 = io_lsu_imprecise_error_store_any | io_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 1807:49] + wire _T_492 = ~io_nmi_int_detected_f; // @[dec_tlu_ctl.scala 1807:86] + wire _T_493 = _T_491 & _T_492; // @[dec_tlu_ctl.scala 1807:84] + wire _T_494 = ~io_mdseac_locked_f; // @[dec_tlu_ctl.scala 1807:111] + wire mdseac_en = _T_493 & _T_494; // @[dec_tlu_ctl.scala 1807:109] reg [31:0] mdseac; // @[lib.scala 374:16] - wire _T_490 = wr_mpmc_r & io_dec_csr_wrdata_r[0]; // @[dec_tlu_ctl.scala 1822:30] - wire _T_491 = ~io_internal_dbg_halt_mode_f2; // @[dec_tlu_ctl.scala 1822:57] - wire _T_492 = _T_490 & _T_491; // @[dec_tlu_ctl.scala 1822:55] - wire _T_493 = ~io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 1822:89] - wire _T_506 = io_dec_csr_wrdata_r[31:27] > 5'h1a; // @[dec_tlu_ctl.scala 1840:48] - wire [4:0] csr_sat = _T_506 ? 5'h1a : io_dec_csr_wrdata_r[31:27]; // @[dec_tlu_ctl.scala 1840:19] - wire _T_509 = io_dec_csr_wraddr_r == 12'h7f0; // @[dec_tlu_ctl.scala 1842:70] - wire wr_micect_r = io_dec_csr_wen_r_mod & _T_509; // @[dec_tlu_ctl.scala 1842:41] - wire [26:0] _T_510 = {26'h0,io_ic_perr_r_d1}; // @[Cat.scala 29:58] - wire [31:0] _GEN_14 = {{5'd0}, _T_510}; // @[dec_tlu_ctl.scala 1843:23] - wire [31:0] _T_512 = micect + _GEN_14; // @[dec_tlu_ctl.scala 1843:23] - wire [31:0] _T_515 = {csr_sat,io_dec_csr_wrdata_r[26:0]}; // @[Cat.scala 29:58] - wire [26:0] micect_inc = _T_512[26:0]; // @[dec_tlu_ctl.scala 1843:13] - wire [31:0] _T_517 = {micect[31:27],micect_inc}; // @[Cat.scala 29:58] - wire _T_528 = io_dec_csr_wraddr_r == 12'h7f1; // @[dec_tlu_ctl.scala 1857:76] - wire wr_miccmect_r = io_dec_csr_wen_r_mod & _T_528; // @[dec_tlu_ctl.scala 1857:47] - wire _T_530 = io_iccm_sbecc_r_d1 | io_iccm_dma_sb_error; // @[dec_tlu_ctl.scala 1858:70] - wire [26:0] _T_531 = {26'h0,_T_530}; // @[Cat.scala 29:58] - wire [26:0] miccmect_inc = miccmect[26:0] + _T_531; // @[dec_tlu_ctl.scala 1858:33] - wire [31:0] _T_538 = {miccmect[31:27],miccmect_inc}; // @[Cat.scala 29:58] - wire _T_539 = wr_miccmect_r | io_iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 1861:48] - wire _T_550 = io_dec_csr_wraddr_r == 12'h7f2; // @[dec_tlu_ctl.scala 1872:76] - wire wr_mdccmect_r = io_dec_csr_wen_r_mod & _T_550; // @[dec_tlu_ctl.scala 1872:47] - wire [26:0] _T_552 = {26'h0,io_lsu_single_ecc_error_r_d1}; // @[Cat.scala 29:58] - wire [26:0] mdccmect_inc = mdccmect[26:0] + _T_552; // @[dec_tlu_ctl.scala 1873:33] - wire [31:0] _T_559 = {mdccmect[31:27],mdccmect_inc}; // @[Cat.scala 29:58] - wire _T_570 = io_dec_csr_wraddr_r == 12'h7ce; // @[dec_tlu_ctl.scala 1888:69] - wire wr_mfdht_r = io_dec_csr_wen_r_mod & _T_570; // @[dec_tlu_ctl.scala 1888:40] + wire _T_500 = wr_mpmc_r & io_dec_csr_wrdata_r[0]; // @[dec_tlu_ctl.scala 1822:30] + wire _T_501 = ~io_internal_dbg_halt_mode_f2; // @[dec_tlu_ctl.scala 1822:57] + wire _T_502 = _T_500 & _T_501; // @[dec_tlu_ctl.scala 1822:55] + wire _T_503 = ~io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 1822:89] + wire _T_516 = io_dec_csr_wrdata_r[31:27] > 5'h1a; // @[dec_tlu_ctl.scala 1840:48] + wire [4:0] csr_sat = _T_516 ? 5'h1a : io_dec_csr_wrdata_r[31:27]; // @[dec_tlu_ctl.scala 1840:19] + wire _T_519 = io_dec_csr_wraddr_r == 12'h7f0; // @[dec_tlu_ctl.scala 1842:70] + wire wr_micect_r = io_dec_csr_wen_r_mod & _T_519; // @[dec_tlu_ctl.scala 1842:41] + wire [26:0] _T_520 = {26'h0,io_ic_perr_r_d1}; // @[Cat.scala 29:58] + wire [31:0] _GEN_14 = {{5'd0}, _T_520}; // @[dec_tlu_ctl.scala 1843:23] + wire [31:0] _T_522 = micect + _GEN_14; // @[dec_tlu_ctl.scala 1843:23] + wire [31:0] _T_525 = {csr_sat,io_dec_csr_wrdata_r[26:0]}; // @[Cat.scala 29:58] + wire [26:0] micect_inc = _T_522[26:0]; // @[dec_tlu_ctl.scala 1843:13] + wire [31:0] _T_527 = {micect[31:27],micect_inc}; // @[Cat.scala 29:58] + wire _T_538 = io_dec_csr_wraddr_r == 12'h7f1; // @[dec_tlu_ctl.scala 1857:76] + wire wr_miccmect_r = io_dec_csr_wen_r_mod & _T_538; // @[dec_tlu_ctl.scala 1857:47] + wire _T_540 = io_iccm_sbecc_r_d1 | io_iccm_dma_sb_error; // @[dec_tlu_ctl.scala 1858:70] + wire [26:0] _T_541 = {26'h0,_T_540}; // @[Cat.scala 29:58] + wire [26:0] miccmect_inc = miccmect[26:0] + _T_541; // @[dec_tlu_ctl.scala 1858:33] + wire [31:0] _T_548 = {miccmect[31:27],miccmect_inc}; // @[Cat.scala 29:58] + wire _T_549 = wr_miccmect_r | io_iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 1861:48] + wire _T_560 = io_dec_csr_wraddr_r == 12'h7f2; // @[dec_tlu_ctl.scala 1872:76] + wire wr_mdccmect_r = io_dec_csr_wen_r_mod & _T_560; // @[dec_tlu_ctl.scala 1872:47] + wire [26:0] _T_562 = {26'h0,io_lsu_single_ecc_error_r_d1}; // @[Cat.scala 29:58] + wire [26:0] mdccmect_inc = mdccmect[26:0] + _T_562; // @[dec_tlu_ctl.scala 1873:33] + wire [31:0] _T_569 = {mdccmect[31:27],mdccmect_inc}; // @[Cat.scala 29:58] + wire _T_580 = io_dec_csr_wraddr_r == 12'h7ce; // @[dec_tlu_ctl.scala 1888:69] + wire wr_mfdht_r = io_dec_csr_wen_r_mod & _T_580; // @[dec_tlu_ctl.scala 1888:40] reg [5:0] mfdht; // @[dec_tlu_ctl.scala 1892:43] - wire _T_575 = io_dec_csr_wraddr_r == 12'h7cf; // @[dec_tlu_ctl.scala 1901:69] - wire wr_mfdhs_r = io_dec_csr_wen_r_mod & _T_575; // @[dec_tlu_ctl.scala 1901:40] - wire _T_578 = ~io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 1904:43] - wire _T_579 = io_dbg_tlu_halted & _T_578; // @[dec_tlu_ctl.scala 1904:41] - wire _T_581 = ~io_lsu_idle_any_f; // @[dec_tlu_ctl.scala 1904:78] - wire _T_582 = ~io_ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 1904:98] - wire [1:0] _T_583 = {_T_581,_T_582}; // @[Cat.scala 29:58] + wire _T_585 = io_dec_csr_wraddr_r == 12'h7cf; // @[dec_tlu_ctl.scala 1901:69] + wire wr_mfdhs_r = io_dec_csr_wen_r_mod & _T_585; // @[dec_tlu_ctl.scala 1901:40] + wire _T_588 = ~io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 1904:43] + wire _T_589 = io_dbg_tlu_halted & _T_588; // @[dec_tlu_ctl.scala 1904:41] + wire _T_591 = ~io_lsu_idle_any_f; // @[dec_tlu_ctl.scala 1904:78] + wire _T_592 = ~io_ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 1904:98] + wire [1:0] _T_593 = {_T_591,_T_592}; // @[Cat.scala 29:58] reg [1:0] mfdhs; // @[Reg.scala 27:20] - wire _T_585 = wr_mfdhs_r | io_dbg_tlu_halted; // @[dec_tlu_ctl.scala 1906:71] + wire _T_595 = wr_mfdhs_r | io_dbg_tlu_halted; // @[dec_tlu_ctl.scala 1906:71] reg [31:0] force_halt_ctr_f; // @[Reg.scala 27:20] - wire [31:0] _T_590 = force_halt_ctr_f + 32'h1; // @[dec_tlu_ctl.scala 1908:74] - wire [62:0] _T_597 = 63'hffffffff << mfdht[5:1]; // @[dec_tlu_ctl.scala 1913:71] + wire [31:0] _T_600 = force_halt_ctr_f + 32'h1; // @[dec_tlu_ctl.scala 1908:74] + wire [62:0] _T_607 = 63'hffffffff << mfdht[5:1]; // @[dec_tlu_ctl.scala 1913:71] wire [62:0] _GEN_15 = {{31'd0}, force_halt_ctr_f}; // @[dec_tlu_ctl.scala 1913:48] - wire [62:0] _T_598 = _GEN_15 & _T_597; // @[dec_tlu_ctl.scala 1913:48] - wire _T_599 = |_T_598; // @[dec_tlu_ctl.scala 1913:87] - wire _T_602 = io_dec_csr_wraddr_r == 12'hbc8; // @[dec_tlu_ctl.scala 1921:69] + wire [62:0] _T_608 = _GEN_15 & _T_607; // @[dec_tlu_ctl.scala 1913:48] + wire _T_609 = |_T_608; // @[dec_tlu_ctl.scala 1913:87] + wire _T_612 = io_dec_csr_wraddr_r == 12'hbc8; // @[dec_tlu_ctl.scala 1921:69] reg [21:0] meivt; // @[lib.scala 374:16] - wire _T_621 = io_dec_csr_wraddr_r == 12'hbca; // @[dec_tlu_ctl.scala 1972:69] - wire _T_622 = io_dec_csr_wen_r_mod & _T_621; // @[dec_tlu_ctl.scala 1972:40] - wire wr_meicpct_r = _T_622 | io_take_ext_int_start; // @[dec_tlu_ctl.scala 1972:83] + wire _T_631 = io_dec_csr_wraddr_r == 12'hbca; // @[dec_tlu_ctl.scala 1972:69] + wire _T_632 = io_dec_csr_wen_r_mod & _T_631; // @[dec_tlu_ctl.scala 1972:40] + wire wr_meicpct_r = _T_632 | io_take_ext_int_start; // @[dec_tlu_ctl.scala 1972:83] reg [7:0] meihap; // @[lib.scala 374:16] - wire _T_608 = io_dec_csr_wraddr_r == 12'hbcc; // @[dec_tlu_ctl.scala 1945:72] - wire wr_meicurpl_r = io_dec_csr_wen_r_mod & _T_608; // @[dec_tlu_ctl.scala 1945:43] + wire _T_618 = io_dec_csr_wraddr_r == 12'hbcc; // @[dec_tlu_ctl.scala 1945:72] + wire wr_meicurpl_r = io_dec_csr_wen_r_mod & _T_618; // @[dec_tlu_ctl.scala 1945:43] reg [3:0] meicurpl; // @[dec_tlu_ctl.scala 1948:46] - wire _T_613 = io_dec_csr_wraddr_r == 12'hbcb; // @[dec_tlu_ctl.scala 1960:73] - wire _T_614 = io_dec_csr_wen_r_mod & _T_613; // @[dec_tlu_ctl.scala 1960:44] - wire wr_meicidpl_r = _T_614 | io_take_ext_int_start; // @[dec_tlu_ctl.scala 1960:88] + wire _T_623 = io_dec_csr_wraddr_r == 12'hbcb; // @[dec_tlu_ctl.scala 1960:73] + wire _T_624 = io_dec_csr_wen_r_mod & _T_623; // @[dec_tlu_ctl.scala 1960:44] + wire wr_meicidpl_r = _T_624 | io_take_ext_int_start; // @[dec_tlu_ctl.scala 1960:88] reg [3:0] meicidpl; // @[dec_tlu_ctl.scala 1965:44] - wire _T_625 = io_dec_csr_wraddr_r == 12'hbc9; // @[dec_tlu_ctl.scala 1981:69] - wire wr_meipt_r = io_dec_csr_wen_r_mod & _T_625; // @[dec_tlu_ctl.scala 1981:40] + wire _T_635 = io_dec_csr_wraddr_r == 12'hbc9; // @[dec_tlu_ctl.scala 1981:69] + wire wr_meipt_r = io_dec_csr_wen_r_mod & _T_635; // @[dec_tlu_ctl.scala 1981:40] reg [3:0] meipt; // @[dec_tlu_ctl.scala 1984:43] - wire _T_629 = io_trigger_hit_r_d1 & io_dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 2012:89] - wire trigger_hit_for_dscr_cause_r_d1 = io_trigger_hit_dmode_r_d1 | _T_629; // @[dec_tlu_ctl.scala 2012:66] - wire _T_630 = ~io_ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 2015:31] - wire _T_631 = io_dcsr_single_step_done_f & _T_630; // @[dec_tlu_ctl.scala 2015:29] - wire _T_632 = ~trigger_hit_for_dscr_cause_r_d1; // @[dec_tlu_ctl.scala 2015:63] - wire _T_633 = _T_631 & _T_632; // @[dec_tlu_ctl.scala 2015:61] - wire _T_634 = ~io_debug_halt_req; // @[dec_tlu_ctl.scala 2015:98] - wire _T_635 = _T_633 & _T_634; // @[dec_tlu_ctl.scala 2015:96] - wire _T_638 = io_debug_halt_req & _T_630; // @[dec_tlu_ctl.scala 2016:46] - wire _T_640 = _T_638 & _T_632; // @[dec_tlu_ctl.scala 2016:78] - wire _T_643 = io_ebreak_to_debug_mode_r_d1 & _T_632; // @[dec_tlu_ctl.scala 2017:75] - wire [2:0] _T_646 = _T_635 ? 3'h4 : 3'h0; // @[Mux.scala 27:72] - wire [2:0] _T_647 = _T_640 ? 3'h3 : 3'h0; // @[Mux.scala 27:72] - wire [2:0] _T_648 = _T_643 ? 3'h1 : 3'h0; // @[Mux.scala 27:72] - wire [2:0] _T_649 = trigger_hit_for_dscr_cause_r_d1 ? 3'h2 : 3'h0; // @[Mux.scala 27:72] - wire [2:0] _T_650 = _T_646 | _T_647; // @[Mux.scala 27:72] - wire [2:0] _T_651 = _T_650 | _T_648; // @[Mux.scala 27:72] - wire [2:0] dcsr_cause = _T_651 | _T_649; // @[Mux.scala 27:72] - wire _T_653 = io_allow_dbg_halt_csr_write & io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 2020:46] - wire _T_655 = io_dec_csr_wraddr_r == 12'h7b0; // @[dec_tlu_ctl.scala 2020:98] - wire wr_dcsr_r = _T_653 & _T_655; // @[dec_tlu_ctl.scala 2020:69] - wire _T_657 = io_dcsr[8:6] == 3'h3; // @[dec_tlu_ctl.scala 2026:75] - wire dcsr_cause_upgradeable = io_internal_dbg_halt_mode_f & _T_657; // @[dec_tlu_ctl.scala 2026:59] - wire _T_658 = ~io_dbg_tlu_halted; // @[dec_tlu_ctl.scala 2027:59] - wire _T_659 = _T_658 | dcsr_cause_upgradeable; // @[dec_tlu_ctl.scala 2027:78] - wire enter_debug_halt_req_le = io_enter_debug_halt_req & _T_659; // @[dec_tlu_ctl.scala 2027:56] + wire _T_639 = io_trigger_hit_r_d1 & io_dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 2012:89] + wire trigger_hit_for_dscr_cause_r_d1 = io_trigger_hit_dmode_r_d1 | _T_639; // @[dec_tlu_ctl.scala 2012:66] + wire _T_640 = ~io_ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 2015:31] + wire _T_641 = io_dcsr_single_step_done_f & _T_640; // @[dec_tlu_ctl.scala 2015:29] + wire _T_642 = ~trigger_hit_for_dscr_cause_r_d1; // @[dec_tlu_ctl.scala 2015:63] + wire _T_643 = _T_641 & _T_642; // @[dec_tlu_ctl.scala 2015:61] + wire _T_644 = ~io_debug_halt_req; // @[dec_tlu_ctl.scala 2015:98] + wire _T_645 = _T_643 & _T_644; // @[dec_tlu_ctl.scala 2015:96] + wire _T_648 = io_debug_halt_req & _T_640; // @[dec_tlu_ctl.scala 2016:46] + wire _T_650 = _T_648 & _T_642; // @[dec_tlu_ctl.scala 2016:78] + wire _T_653 = io_ebreak_to_debug_mode_r_d1 & _T_642; // @[dec_tlu_ctl.scala 2017:75] + wire [2:0] _T_656 = _T_645 ? 3'h4 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_657 = _T_650 ? 3'h3 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_658 = _T_653 ? 3'h1 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_659 = trigger_hit_for_dscr_cause_r_d1 ? 3'h2 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_660 = _T_656 | _T_657; // @[Mux.scala 27:72] + wire [2:0] _T_661 = _T_660 | _T_658; // @[Mux.scala 27:72] + wire [2:0] dcsr_cause = _T_661 | _T_659; // @[Mux.scala 27:72] + wire _T_663 = io_allow_dbg_halt_csr_write & io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 2020:46] + wire _T_665 = io_dec_csr_wraddr_r == 12'h7b0; // @[dec_tlu_ctl.scala 2020:98] + wire wr_dcsr_r = _T_663 & _T_665; // @[dec_tlu_ctl.scala 2020:69] + wire _T_667 = io_dcsr[8:6] == 3'h3; // @[dec_tlu_ctl.scala 2026:75] + wire dcsr_cause_upgradeable = io_internal_dbg_halt_mode_f & _T_667; // @[dec_tlu_ctl.scala 2026:59] + wire _T_668 = ~io_dbg_tlu_halted; // @[dec_tlu_ctl.scala 2027:59] + wire _T_669 = _T_668 | dcsr_cause_upgradeable; // @[dec_tlu_ctl.scala 2027:78] + wire enter_debug_halt_req_le = io_enter_debug_halt_req & _T_669; // @[dec_tlu_ctl.scala 2027:56] wire nmi_in_debug_mode = io_nmi_int_detected_f & io_internal_dbg_halt_mode_f; // @[dec_tlu_ctl.scala 2029:48] - wire [15:0] _T_665 = {io_dcsr[15:9],dcsr_cause,io_dcsr[5:2],2'h3}; // @[Cat.scala 29:58] - wire _T_671 = nmi_in_debug_mode | io_dcsr[3]; // @[dec_tlu_ctl.scala 2031:145] - wire [15:0] _T_680 = {io_dec_csr_wrdata_r[15],3'h0,io_dec_csr_wrdata_r[11:10],1'h0,io_dcsr[8:6],2'h0,_T_671,io_dec_csr_wrdata_r[2],2'h3}; // @[Cat.scala 29:58] - wire [15:0] _T_685 = {io_dcsr[15:4],nmi_in_debug_mode,io_dcsr[2],2'h3}; // @[Cat.scala 29:58] - wire _T_687 = enter_debug_halt_req_le | wr_dcsr_r; // @[dec_tlu_ctl.scala 2033:54] - wire _T_688 = _T_687 | io_internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 2033:66] - reg [15:0] _T_691; // @[lib.scala 374:16] - wire _T_694 = io_dec_csr_wraddr_r == 12'h7b1; // @[dec_tlu_ctl.scala 2041:97] - wire wr_dpc_r = _T_653 & _T_694; // @[dec_tlu_ctl.scala 2041:68] - wire _T_697 = ~io_request_debug_mode_done; // @[dec_tlu_ctl.scala 2042:67] - wire dpc_capture_npc = _T_579 & _T_697; // @[dec_tlu_ctl.scala 2042:65] - wire _T_698 = ~io_request_debug_mode_r; // @[dec_tlu_ctl.scala 2046:21] - wire _T_699 = ~dpc_capture_npc; // @[dec_tlu_ctl.scala 2046:39] - wire _T_700 = _T_698 & _T_699; // @[dec_tlu_ctl.scala 2046:37] - wire _T_701 = _T_700 & wr_dpc_r; // @[dec_tlu_ctl.scala 2046:56] - wire _T_706 = _T_698 & dpc_capture_npc; // @[dec_tlu_ctl.scala 2048:49] - wire [30:0] _T_708 = _T_701 ? io_dec_csr_wrdata_r[31:1] : 31'h0; // @[Mux.scala 27:72] - wire [30:0] _T_709 = io_request_debug_mode_r ? pc_r : 31'h0; // @[Mux.scala 27:72] - wire [30:0] _T_710 = _T_706 ? io_npc_r : 31'h0; // @[Mux.scala 27:72] - wire [30:0] _T_711 = _T_708 | _T_709; // @[Mux.scala 27:72] - wire _T_713 = wr_dpc_r | io_request_debug_mode_r; // @[dec_tlu_ctl.scala 2050:36] - reg [30:0] _T_716; // @[lib.scala 374:16] - wire [2:0] _T_720 = {io_dec_csr_wrdata_r[24],io_dec_csr_wrdata_r[21:20]}; // @[Cat.scala 29:58] - wire _T_723 = io_dec_csr_wraddr_r == 12'h7c8; // @[dec_tlu_ctl.scala 2065:102] + wire [15:0] _T_675 = {io_dcsr[15:9],dcsr_cause,io_dcsr[5:2],2'h3}; // @[Cat.scala 29:58] + wire _T_681 = nmi_in_debug_mode | io_dcsr[3]; // @[dec_tlu_ctl.scala 2031:145] + wire [15:0] _T_690 = {io_dec_csr_wrdata_r[15],3'h0,io_dec_csr_wrdata_r[11:10],1'h0,io_dcsr[8:6],2'h0,_T_681,io_dec_csr_wrdata_r[2],2'h3}; // @[Cat.scala 29:58] + wire [15:0] _T_695 = {io_dcsr[15:4],nmi_in_debug_mode,io_dcsr[2],2'h3}; // @[Cat.scala 29:58] + wire _T_697 = enter_debug_halt_req_le | wr_dcsr_r; // @[dec_tlu_ctl.scala 2033:54] + wire _T_698 = _T_697 | io_internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 2033:66] + reg [15:0] _T_701; // @[lib.scala 374:16] + wire _T_704 = io_dec_csr_wraddr_r == 12'h7b1; // @[dec_tlu_ctl.scala 2041:97] + wire wr_dpc_r = _T_663 & _T_704; // @[dec_tlu_ctl.scala 2041:68] + wire _T_707 = ~io_request_debug_mode_done; // @[dec_tlu_ctl.scala 2042:67] + wire dpc_capture_npc = _T_589 & _T_707; // @[dec_tlu_ctl.scala 2042:65] + wire _T_708 = ~io_request_debug_mode_r; // @[dec_tlu_ctl.scala 2046:21] + wire _T_709 = ~dpc_capture_npc; // @[dec_tlu_ctl.scala 2046:39] + wire _T_710 = _T_708 & _T_709; // @[dec_tlu_ctl.scala 2046:37] + wire _T_711 = _T_710 & wr_dpc_r; // @[dec_tlu_ctl.scala 2046:56] + wire _T_716 = _T_708 & dpc_capture_npc; // @[dec_tlu_ctl.scala 2048:49] + wire [30:0] _T_718 = _T_711 ? io_dec_csr_wrdata_r[31:1] : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_719 = io_request_debug_mode_r ? pc_r : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_720 = _T_716 ? io_npc_r : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_721 = _T_718 | _T_719; // @[Mux.scala 27:72] + wire _T_723 = wr_dpc_r | io_request_debug_mode_r; // @[dec_tlu_ctl.scala 2050:36] + reg [30:0] _T_726; // @[lib.scala 374:16] + wire [2:0] _T_730 = {io_dec_csr_wrdata_r[24],io_dec_csr_wrdata_r[21:20]}; // @[Cat.scala 29:58] + wire _T_733 = io_dec_csr_wraddr_r == 12'h7c8; // @[dec_tlu_ctl.scala 2065:102] reg [16:0] dicawics; // @[lib.scala 374:16] - wire _T_727 = io_dec_csr_wraddr_r == 12'h7c9; // @[dec_tlu_ctl.scala 2083:100] - wire wr_dicad0_r = _T_653 & _T_727; // @[dec_tlu_ctl.scala 2083:71] + wire _T_737 = io_dec_csr_wraddr_r == 12'h7c9; // @[dec_tlu_ctl.scala 2083:100] + wire wr_dicad0_r = _T_663 & _T_737; // @[dec_tlu_ctl.scala 2083:71] reg [70:0] dicad0; // @[lib.scala 374:16] - wire _T_733 = io_dec_csr_wraddr_r == 12'h7cc; // @[dec_tlu_ctl.scala 2096:101] - wire wr_dicad0h_r = _T_653 & _T_733; // @[dec_tlu_ctl.scala 2096:72] + wire _T_743 = io_dec_csr_wraddr_r == 12'h7cc; // @[dec_tlu_ctl.scala 2096:101] + wire wr_dicad0h_r = _T_663 & _T_743; // @[dec_tlu_ctl.scala 2096:72] reg [31:0] dicad0h; // @[lib.scala 374:16] - wire _T_741 = io_dec_csr_wraddr_r == 12'h7ca; // @[dec_tlu_ctl.scala 2108:100] - wire _T_742 = _T_653 & _T_741; // @[dec_tlu_ctl.scala 2108:71] - wire [31:0] _T_745 = _T_742 ? io_dec_csr_wrdata_r : {{25'd0}, io_ifu_ic_debug_rd_data[70:64]}; // @[dec_tlu_ctl.scala 2110:21] - wire _T_746 = _T_742 | io_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 2113:78] - reg [31:0] _T_748; // @[Reg.scala 27:20] - wire [31:0] dicad1 = {25'h0,_T_748[6:0]}; // @[Cat.scala 29:58] - wire [38:0] _T_753 = {dicad1[6:0],dicad0h}; // @[Cat.scala 29:58] - wire _T_755 = io_allow_dbg_halt_csr_write & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 2141:52] - wire _T_756 = _T_755 & io_dec_i0_decode_d; // @[dec_tlu_ctl.scala 2141:75] - wire _T_757 = ~io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 2141:98] - wire _T_758 = _T_756 & _T_757; // @[dec_tlu_ctl.scala 2141:96] - wire _T_760 = io_dec_csr_rdaddr_d == 12'h7cb; // @[dec_tlu_ctl.scala 2141:149] - wire _T_763 = io_dec_csr_wraddr_r == 12'h7cb; // @[dec_tlu_ctl.scala 2142:104] + wire _T_751 = io_dec_csr_wraddr_r == 12'h7ca; // @[dec_tlu_ctl.scala 2108:100] + wire _T_752 = _T_663 & _T_751; // @[dec_tlu_ctl.scala 2108:71] + wire [31:0] _T_755 = _T_752 ? io_dec_csr_wrdata_r : {{25'd0}, io_ifu_ic_debug_rd_data[70:64]}; // @[dec_tlu_ctl.scala 2110:21] + wire _T_756 = _T_752 | io_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 2113:78] + reg [31:0] _T_758; // @[Reg.scala 27:20] + wire [31:0] dicad1 = {25'h0,_T_758[6:0]}; // @[Cat.scala 29:58] + wire [38:0] _T_763 = {dicad1[6:0],dicad0h}; // @[Cat.scala 29:58] + wire _T_765 = io_allow_dbg_halt_csr_write & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 2141:52] + wire _T_766 = _T_765 & io_dec_i0_decode_d; // @[dec_tlu_ctl.scala 2141:75] + wire _T_767 = ~io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 2141:98] + wire _T_768 = _T_766 & _T_767; // @[dec_tlu_ctl.scala 2141:96] + wire _T_770 = io_dec_csr_rdaddr_d == 12'h7cb; // @[dec_tlu_ctl.scala 2141:149] + wire _T_773 = io_dec_csr_wraddr_r == 12'h7cb; // @[dec_tlu_ctl.scala 2142:104] reg icache_rd_valid_f; // @[dec_tlu_ctl.scala 2144:58] reg icache_wr_valid_f; // @[dec_tlu_ctl.scala 2145:58] - wire _T_765 = io_dec_csr_wraddr_r == 12'h7a0; // @[dec_tlu_ctl.scala 2156:69] - wire wr_mtsel_r = io_dec_csr_wen_r_mod & _T_765; // @[dec_tlu_ctl.scala 2156:40] + wire _T_775 = io_dec_csr_wraddr_r == 12'h7a0; // @[dec_tlu_ctl.scala 2156:69] + wire wr_mtsel_r = io_dec_csr_wen_r_mod & _T_775; // @[dec_tlu_ctl.scala 2156:40] reg [1:0] mtsel; // @[dec_tlu_ctl.scala 2159:43] - wire tdata_load = io_dec_csr_wrdata_r[0] & _T_398; // @[dec_tlu_ctl.scala 2194:42] - wire tdata_opcode = io_dec_csr_wrdata_r[2] & _T_398; // @[dec_tlu_ctl.scala 2196:44] - wire _T_776 = io_dec_csr_wrdata_r[27] & io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2198:46] - wire tdata_action = _T_776 & io_dec_csr_wrdata_r[12]; // @[dec_tlu_ctl.scala 2198:69] - wire [9:0] tdata_wrdata_r = {_T_776,io_dec_csr_wrdata_r[20:19],tdata_action,io_dec_csr_wrdata_r[11],io_dec_csr_wrdata_r[7:6],tdata_opcode,io_dec_csr_wrdata_r[1],tdata_load}; // @[Cat.scala 29:58] - wire _T_791 = io_dec_csr_wraddr_r == 12'h7a1; // @[dec_tlu_ctl.scala 2204:99] - wire _T_792 = io_dec_csr_wen_r_mod & _T_791; // @[dec_tlu_ctl.scala 2204:70] - wire _T_793 = mtsel == 2'h0; // @[dec_tlu_ctl.scala 2204:121] - wire _T_794 = _T_792 & _T_793; // @[dec_tlu_ctl.scala 2204:112] - wire _T_796 = ~io_mtdata1_t_0[9]; // @[dec_tlu_ctl.scala 2204:138] - wire _T_797 = _T_796 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2204:170] - wire wr_mtdata1_t_r_0 = _T_794 & _T_797; // @[dec_tlu_ctl.scala 2204:135] - wire _T_802 = mtsel == 2'h1; // @[dec_tlu_ctl.scala 2204:121] - wire _T_803 = _T_792 & _T_802; // @[dec_tlu_ctl.scala 2204:112] - wire _T_805 = ~io_mtdata1_t_1[9]; // @[dec_tlu_ctl.scala 2204:138] - wire _T_806 = _T_805 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2204:170] - wire wr_mtdata1_t_r_1 = _T_803 & _T_806; // @[dec_tlu_ctl.scala 2204:135] - wire _T_811 = mtsel == 2'h2; // @[dec_tlu_ctl.scala 2204:121] - wire _T_812 = _T_792 & _T_811; // @[dec_tlu_ctl.scala 2204:112] - wire _T_814 = ~io_mtdata1_t_2[9]; // @[dec_tlu_ctl.scala 2204:138] - wire _T_815 = _T_814 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2204:170] - wire wr_mtdata1_t_r_2 = _T_812 & _T_815; // @[dec_tlu_ctl.scala 2204:135] - wire _T_820 = mtsel == 2'h3; // @[dec_tlu_ctl.scala 2204:121] - wire _T_821 = _T_792 & _T_820; // @[dec_tlu_ctl.scala 2204:112] - wire _T_823 = ~io_mtdata1_t_3[9]; // @[dec_tlu_ctl.scala 2204:138] - wire _T_824 = _T_823 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2204:170] - wire wr_mtdata1_t_r_3 = _T_821 & _T_824; // @[dec_tlu_ctl.scala 2204:135] - wire _T_830 = io_update_hit_bit_r[0] | io_mtdata1_t_0[8]; // @[dec_tlu_ctl.scala 2205:139] - wire [9:0] _T_833 = {io_mtdata1_t_0[9],_T_830,io_mtdata1_t_0[7:0]}; // @[Cat.scala 29:58] - wire _T_839 = io_update_hit_bit_r[1] | io_mtdata1_t_1[8]; // @[dec_tlu_ctl.scala 2205:139] - wire [9:0] _T_842 = {io_mtdata1_t_1[9],_T_839,io_mtdata1_t_1[7:0]}; // @[Cat.scala 29:58] - wire _T_848 = io_update_hit_bit_r[2] | io_mtdata1_t_2[8]; // @[dec_tlu_ctl.scala 2205:139] - wire [9:0] _T_851 = {io_mtdata1_t_2[9],_T_848,io_mtdata1_t_2[7:0]}; // @[Cat.scala 29:58] - wire _T_857 = io_update_hit_bit_r[3] | io_mtdata1_t_3[8]; // @[dec_tlu_ctl.scala 2205:139] - wire [9:0] _T_860 = {io_mtdata1_t_3[9],_T_857,io_mtdata1_t_3[7:0]}; // @[Cat.scala 29:58] - reg [9:0] _T_862; // @[dec_tlu_ctl.scala 2207:74] - reg [9:0] _T_863; // @[dec_tlu_ctl.scala 2207:74] - reg [9:0] _T_864; // @[dec_tlu_ctl.scala 2207:74] - reg [9:0] _T_865; // @[dec_tlu_ctl.scala 2207:74] - wire [31:0] _T_880 = {4'h2,io_mtdata1_t_0[9],6'h1f,io_mtdata1_t_0[8:7],6'h0,io_mtdata1_t_0[6:5],3'h0,io_mtdata1_t_0[4:3],3'h0,io_mtdata1_t_0[2:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_895 = {4'h2,io_mtdata1_t_1[9],6'h1f,io_mtdata1_t_1[8:7],6'h0,io_mtdata1_t_1[6:5],3'h0,io_mtdata1_t_1[4:3],3'h0,io_mtdata1_t_1[2:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_910 = {4'h2,io_mtdata1_t_2[9],6'h1f,io_mtdata1_t_2[8:7],6'h0,io_mtdata1_t_2[6:5],3'h0,io_mtdata1_t_2[4:3],3'h0,io_mtdata1_t_2[2:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_925 = {4'h2,io_mtdata1_t_3[9],6'h1f,io_mtdata1_t_3[8:7],6'h0,io_mtdata1_t_3[6:5],3'h0,io_mtdata1_t_3[4:3],3'h0,io_mtdata1_t_3[2:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_926 = _T_793 ? _T_880 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_927 = _T_802 ? _T_895 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_928 = _T_811 ? _T_910 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_929 = _T_820 ? _T_925 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_930 = _T_926 | _T_927; // @[Mux.scala 27:72] - wire [31:0] _T_931 = _T_930 | _T_928; // @[Mux.scala 27:72] - wire [31:0] mtdata1_tsel_out = _T_931 | _T_929; // @[Mux.scala 27:72] - wire _T_958 = io_dec_csr_wraddr_r == 12'h7a2; // @[dec_tlu_ctl.scala 2224:98] - wire _T_959 = io_dec_csr_wen_r_mod & _T_958; // @[dec_tlu_ctl.scala 2224:69] - wire _T_961 = _T_959 & _T_793; // @[dec_tlu_ctl.scala 2224:111] - wire _T_970 = _T_959 & _T_802; // @[dec_tlu_ctl.scala 2224:111] - wire _T_979 = _T_959 & _T_811; // @[dec_tlu_ctl.scala 2224:111] - wire _T_988 = _T_959 & _T_820; // @[dec_tlu_ctl.scala 2224:111] + wire tdata_load = io_dec_csr_wrdata_r[0] & _T_408; // @[dec_tlu_ctl.scala 2194:42] + wire tdata_opcode = io_dec_csr_wrdata_r[2] & _T_408; // @[dec_tlu_ctl.scala 2196:44] + wire _T_786 = io_dec_csr_wrdata_r[27] & io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2198:46] + wire tdata_action = _T_786 & io_dec_csr_wrdata_r[12]; // @[dec_tlu_ctl.scala 2198:69] + wire [9:0] tdata_wrdata_r = {_T_786,io_dec_csr_wrdata_r[20:19],tdata_action,io_dec_csr_wrdata_r[11],io_dec_csr_wrdata_r[7:6],tdata_opcode,io_dec_csr_wrdata_r[1],tdata_load}; // @[Cat.scala 29:58] + wire _T_801 = io_dec_csr_wraddr_r == 12'h7a1; // @[dec_tlu_ctl.scala 2204:99] + wire _T_802 = io_dec_csr_wen_r_mod & _T_801; // @[dec_tlu_ctl.scala 2204:70] + wire _T_803 = mtsel == 2'h0; // @[dec_tlu_ctl.scala 2204:121] + wire _T_804 = _T_802 & _T_803; // @[dec_tlu_ctl.scala 2204:112] + wire _T_806 = ~io_mtdata1_t_0[9]; // @[dec_tlu_ctl.scala 2204:138] + wire _T_807 = _T_806 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2204:170] + wire wr_mtdata1_t_r_0 = _T_804 & _T_807; // @[dec_tlu_ctl.scala 2204:135] + wire _T_812 = mtsel == 2'h1; // @[dec_tlu_ctl.scala 2204:121] + wire _T_813 = _T_802 & _T_812; // @[dec_tlu_ctl.scala 2204:112] + wire _T_815 = ~io_mtdata1_t_1[9]; // @[dec_tlu_ctl.scala 2204:138] + wire _T_816 = _T_815 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2204:170] + wire wr_mtdata1_t_r_1 = _T_813 & _T_816; // @[dec_tlu_ctl.scala 2204:135] + wire _T_821 = mtsel == 2'h2; // @[dec_tlu_ctl.scala 2204:121] + wire _T_822 = _T_802 & _T_821; // @[dec_tlu_ctl.scala 2204:112] + wire _T_824 = ~io_mtdata1_t_2[9]; // @[dec_tlu_ctl.scala 2204:138] + wire _T_825 = _T_824 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2204:170] + wire wr_mtdata1_t_r_2 = _T_822 & _T_825; // @[dec_tlu_ctl.scala 2204:135] + wire _T_830 = mtsel == 2'h3; // @[dec_tlu_ctl.scala 2204:121] + wire _T_831 = _T_802 & _T_830; // @[dec_tlu_ctl.scala 2204:112] + wire _T_833 = ~io_mtdata1_t_3[9]; // @[dec_tlu_ctl.scala 2204:138] + wire _T_834 = _T_833 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2204:170] + wire wr_mtdata1_t_r_3 = _T_831 & _T_834; // @[dec_tlu_ctl.scala 2204:135] + wire _T_840 = io_update_hit_bit_r[0] | io_mtdata1_t_0[8]; // @[dec_tlu_ctl.scala 2205:139] + wire [9:0] _T_843 = {io_mtdata1_t_0[9],_T_840,io_mtdata1_t_0[7:0]}; // @[Cat.scala 29:58] + wire _T_849 = io_update_hit_bit_r[1] | io_mtdata1_t_1[8]; // @[dec_tlu_ctl.scala 2205:139] + wire [9:0] _T_852 = {io_mtdata1_t_1[9],_T_849,io_mtdata1_t_1[7:0]}; // @[Cat.scala 29:58] + wire _T_858 = io_update_hit_bit_r[2] | io_mtdata1_t_2[8]; // @[dec_tlu_ctl.scala 2205:139] + wire [9:0] _T_861 = {io_mtdata1_t_2[9],_T_858,io_mtdata1_t_2[7:0]}; // @[Cat.scala 29:58] + wire _T_867 = io_update_hit_bit_r[3] | io_mtdata1_t_3[8]; // @[dec_tlu_ctl.scala 2205:139] + wire [9:0] _T_870 = {io_mtdata1_t_3[9],_T_867,io_mtdata1_t_3[7:0]}; // @[Cat.scala 29:58] + reg [9:0] _T_872; // @[dec_tlu_ctl.scala 2207:74] + reg [9:0] _T_873; // @[dec_tlu_ctl.scala 2207:74] + reg [9:0] _T_874; // @[dec_tlu_ctl.scala 2207:74] + reg [9:0] _T_875; // @[dec_tlu_ctl.scala 2207:74] + wire [31:0] _T_890 = {4'h2,io_mtdata1_t_0[9],6'h1f,io_mtdata1_t_0[8:7],6'h0,io_mtdata1_t_0[6:5],3'h0,io_mtdata1_t_0[4:3],3'h0,io_mtdata1_t_0[2:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_905 = {4'h2,io_mtdata1_t_1[9],6'h1f,io_mtdata1_t_1[8:7],6'h0,io_mtdata1_t_1[6:5],3'h0,io_mtdata1_t_1[4:3],3'h0,io_mtdata1_t_1[2:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_920 = {4'h2,io_mtdata1_t_2[9],6'h1f,io_mtdata1_t_2[8:7],6'h0,io_mtdata1_t_2[6:5],3'h0,io_mtdata1_t_2[4:3],3'h0,io_mtdata1_t_2[2:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_935 = {4'h2,io_mtdata1_t_3[9],6'h1f,io_mtdata1_t_3[8:7],6'h0,io_mtdata1_t_3[6:5],3'h0,io_mtdata1_t_3[4:3],3'h0,io_mtdata1_t_3[2:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_936 = _T_803 ? _T_890 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_937 = _T_812 ? _T_905 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_938 = _T_821 ? _T_920 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_939 = _T_830 ? _T_935 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_940 = _T_936 | _T_937; // @[Mux.scala 27:72] + wire [31:0] _T_941 = _T_940 | _T_938; // @[Mux.scala 27:72] + wire [31:0] mtdata1_tsel_out = _T_941 | _T_939; // @[Mux.scala 27:72] + wire _T_968 = io_dec_csr_wraddr_r == 12'h7a2; // @[dec_tlu_ctl.scala 2224:98] + wire _T_969 = io_dec_csr_wen_r_mod & _T_968; // @[dec_tlu_ctl.scala 2224:69] + wire _T_971 = _T_969 & _T_803; // @[dec_tlu_ctl.scala 2224:111] + wire _T_980 = _T_969 & _T_812; // @[dec_tlu_ctl.scala 2224:111] + wire _T_989 = _T_969 & _T_821; // @[dec_tlu_ctl.scala 2224:111] + wire _T_998 = _T_969 & _T_830; // @[dec_tlu_ctl.scala 2224:111] reg [31:0] mtdata2_t_0; // @[lib.scala 374:16] reg [31:0] mtdata2_t_1; // @[lib.scala 374:16] reg [31:0] mtdata2_t_2; // @[lib.scala 374:16] reg [31:0] mtdata2_t_3; // @[lib.scala 374:16] - wire [31:0] _T_1005 = _T_793 ? mtdata2_t_0 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_1006 = _T_802 ? mtdata2_t_1 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_1007 = _T_811 ? mtdata2_t_2 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_1008 = _T_820 ? mtdata2_t_3 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_1009 = _T_1005 | _T_1006; // @[Mux.scala 27:72] - wire [31:0] _T_1010 = _T_1009 | _T_1007; // @[Mux.scala 27:72] - wire [31:0] mtdata2_tsel_out = _T_1010 | _T_1008; // @[Mux.scala 27:72] - wire [3:0] _T_1013 = io_tlu_i0_commit_cmt ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] pmu_i0_itype_qual = io_dec_tlu_packet_r_pmu_i0_itype & _T_1013; // @[dec_tlu_ctl.scala 2249:59] - wire _T_1015 = ~mcountinhibit[3]; // @[dec_tlu_ctl.scala 2255:24] + wire [31:0] _T_1015 = _T_803 ? mtdata2_t_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1016 = _T_812 ? mtdata2_t_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1017 = _T_821 ? mtdata2_t_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1018 = _T_830 ? mtdata2_t_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1019 = _T_1015 | _T_1016; // @[Mux.scala 27:72] + wire [31:0] _T_1020 = _T_1019 | _T_1017; // @[Mux.scala 27:72] + wire [31:0] mtdata2_tsel_out = _T_1020 | _T_1018; // @[Mux.scala 27:72] + wire [3:0] _T_1023 = io_tlu_i0_commit_cmt ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] pmu_i0_itype_qual = io_dec_tlu_packet_r_pmu_i0_itype & _T_1023; // @[dec_tlu_ctl.scala 2249:59] + wire _T_1025 = ~mcountinhibit[3]; // @[dec_tlu_ctl.scala 2255:24] reg [9:0] mhpme3; // @[Reg.scala 27:20] - wire _T_1016 = mhpme3 == 10'h1; // @[dec_tlu_ctl.scala 2256:34] - wire _T_1018 = mhpme3 == 10'h2; // @[dec_tlu_ctl.scala 2257:34] - wire _T_1020 = mhpme3 == 10'h3; // @[dec_tlu_ctl.scala 2258:34] - wire _T_1022 = mhpme3 == 10'h4; // @[dec_tlu_ctl.scala 2259:34] - wire _T_1024 = ~io_illegal_r; // @[dec_tlu_ctl.scala 2259:96] - wire _T_1025 = io_tlu_i0_commit_cmt & _T_1024; // @[dec_tlu_ctl.scala 2259:94] - wire _T_1026 = mhpme3 == 10'h5; // @[dec_tlu_ctl.scala 2260:34] - wire _T_1028 = ~io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2260:96] - wire _T_1029 = io_tlu_i0_commit_cmt & _T_1028; // @[dec_tlu_ctl.scala 2260:94] - wire _T_1031 = _T_1029 & _T_1024; // @[dec_tlu_ctl.scala 2260:115] - wire _T_1032 = mhpme3 == 10'h6; // @[dec_tlu_ctl.scala 2261:34] - wire _T_1034 = io_tlu_i0_commit_cmt & io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2261:94] - wire _T_1036 = _T_1034 & _T_1024; // @[dec_tlu_ctl.scala 2261:115] - wire _T_1037 = mhpme3 == 10'h7; // @[dec_tlu_ctl.scala 2262:34] - wire _T_1039 = mhpme3 == 10'h8; // @[dec_tlu_ctl.scala 2263:34] - wire _T_1041 = mhpme3 == 10'h1e; // @[dec_tlu_ctl.scala 2264:34] - wire _T_1043 = mhpme3 == 10'h9; // @[dec_tlu_ctl.scala 2265:34] - wire _T_1045 = pmu_i0_itype_qual == 4'h1; // @[dec_tlu_ctl.scala 2265:91] - wire _T_1046 = mhpme3 == 10'ha; // @[dec_tlu_ctl.scala 2266:34] - wire _T_1048 = io_dec_tlu_packet_r_pmu_divide & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2266:105] - wire _T_1049 = mhpme3 == 10'hb; // @[dec_tlu_ctl.scala 2267:34] - wire _T_1051 = pmu_i0_itype_qual == 4'h2; // @[dec_tlu_ctl.scala 2267:91] - wire _T_1052 = mhpme3 == 10'hc; // @[dec_tlu_ctl.scala 2268:34] - wire _T_1054 = pmu_i0_itype_qual == 4'h3; // @[dec_tlu_ctl.scala 2268:91] - wire _T_1055 = mhpme3 == 10'hd; // @[dec_tlu_ctl.scala 2269:34] - wire _T_1058 = _T_1051 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2269:100] - wire _T_1059 = mhpme3 == 10'he; // @[dec_tlu_ctl.scala 2270:34] - wire _T_1063 = _T_1054 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2270:101] - wire _T_1064 = mhpme3 == 10'hf; // @[dec_tlu_ctl.scala 2271:34] - wire _T_1066 = pmu_i0_itype_qual == 4'h4; // @[dec_tlu_ctl.scala 2271:89] - wire _T_1067 = mhpme3 == 10'h10; // @[dec_tlu_ctl.scala 2272:34] - wire _T_1069 = pmu_i0_itype_qual == 4'h5; // @[dec_tlu_ctl.scala 2272:89] - wire _T_1070 = mhpme3 == 10'h12; // @[dec_tlu_ctl.scala 2273:34] - wire _T_1072 = pmu_i0_itype_qual == 4'h6; // @[dec_tlu_ctl.scala 2273:89] - wire _T_1073 = mhpme3 == 10'h11; // @[dec_tlu_ctl.scala 2274:34] - wire _T_1075 = pmu_i0_itype_qual == 4'h7; // @[dec_tlu_ctl.scala 2274:89] - wire _T_1076 = mhpme3 == 10'h13; // @[dec_tlu_ctl.scala 2275:34] - wire _T_1078 = pmu_i0_itype_qual == 4'h8; // @[dec_tlu_ctl.scala 2275:89] - wire _T_1079 = mhpme3 == 10'h14; // @[dec_tlu_ctl.scala 2276:34] - wire _T_1081 = pmu_i0_itype_qual == 4'h9; // @[dec_tlu_ctl.scala 2276:89] - wire _T_1082 = mhpme3 == 10'h15; // @[dec_tlu_ctl.scala 2277:34] - wire _T_1084 = pmu_i0_itype_qual == 4'ha; // @[dec_tlu_ctl.scala 2277:89] - wire _T_1085 = mhpme3 == 10'h16; // @[dec_tlu_ctl.scala 2278:34] - wire _T_1087 = pmu_i0_itype_qual == 4'hb; // @[dec_tlu_ctl.scala 2278:89] - wire _T_1088 = mhpme3 == 10'h17; // @[dec_tlu_ctl.scala 2279:34] - wire _T_1090 = pmu_i0_itype_qual == 4'hc; // @[dec_tlu_ctl.scala 2279:89] - wire _T_1091 = mhpme3 == 10'h18; // @[dec_tlu_ctl.scala 2280:34] - wire _T_1093 = pmu_i0_itype_qual == 4'hd; // @[dec_tlu_ctl.scala 2280:89] - wire _T_1094 = pmu_i0_itype_qual == 4'he; // @[dec_tlu_ctl.scala 2280:122] - wire _T_1095 = _T_1093 | _T_1094; // @[dec_tlu_ctl.scala 2280:101] - wire _T_1096 = mhpme3 == 10'h19; // @[dec_tlu_ctl.scala 2281:34] - wire _T_1098 = io_exu_pmu_i0_br_misp & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2281:95] - wire _T_1099 = mhpme3 == 10'h1a; // @[dec_tlu_ctl.scala 2282:34] - wire _T_1101 = io_exu_pmu_i0_br_ataken & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2282:97] - wire _T_1102 = mhpme3 == 10'h1b; // @[dec_tlu_ctl.scala 2283:34] - wire _T_1104 = io_dec_tlu_packet_r_pmu_i0_br_unpred & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2283:110] - wire _T_1105 = mhpme3 == 10'h1c; // @[dec_tlu_ctl.scala 2284:34] - wire _T_1109 = mhpme3 == 10'h1f; // @[dec_tlu_ctl.scala 2286:34] - wire _T_1111 = mhpme3 == 10'h20; // @[dec_tlu_ctl.scala 2287:34] - wire _T_1113 = mhpme3 == 10'h22; // @[dec_tlu_ctl.scala 2288:34] - wire _T_1115 = mhpme3 == 10'h23; // @[dec_tlu_ctl.scala 2289:34] - wire _T_1117 = mhpme3 == 10'h24; // @[dec_tlu_ctl.scala 2290:34] - wire _T_1119 = mhpme3 == 10'h25; // @[dec_tlu_ctl.scala 2291:34] - wire _T_1121 = io_i0_exception_valid_r | io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 2291:98] - wire _T_1122 = _T_1121 | io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 2291:120] - wire _T_1123 = mhpme3 == 10'h26; // @[dec_tlu_ctl.scala 2292:34] - wire _T_1125 = io_take_timer_int | io_take_int_timer0_int; // @[dec_tlu_ctl.scala 2292:92] - wire _T_1126 = _T_1125 | io_take_int_timer1_int; // @[dec_tlu_ctl.scala 2292:117] - wire _T_1127 = mhpme3 == 10'h27; // @[dec_tlu_ctl.scala 2293:34] - wire _T_1129 = mhpme3 == 10'h28; // @[dec_tlu_ctl.scala 2294:34] - wire _T_1131 = mhpme3 == 10'h29; // @[dec_tlu_ctl.scala 2295:34] - wire _T_1133 = io_dec_tlu_br0_error_r | io_dec_tlu_br0_start_error_r; // @[dec_tlu_ctl.scala 2295:97] - wire _T_1134 = _T_1133 & io_rfpc_i0_r; // @[dec_tlu_ctl.scala 2295:129] - wire _T_1135 = mhpme3 == 10'h2a; // @[dec_tlu_ctl.scala 2296:34] - wire _T_1137 = mhpme3 == 10'h2b; // @[dec_tlu_ctl.scala 2297:34] - wire _T_1139 = mhpme3 == 10'h2c; // @[dec_tlu_ctl.scala 2298:34] - wire _T_1141 = mhpme3 == 10'h2d; // @[dec_tlu_ctl.scala 2299:34] - wire _T_1143 = mhpme3 == 10'h2e; // @[dec_tlu_ctl.scala 2300:34] - wire _T_1145 = mhpme3 == 10'h2f; // @[dec_tlu_ctl.scala 2301:34] - wire _T_1147 = mhpme3 == 10'h30; // @[dec_tlu_ctl.scala 2302:34] - wire _T_1149 = mhpme3 == 10'h31; // @[dec_tlu_ctl.scala 2303:34] - wire _T_1153 = ~io_mstatus[0]; // @[dec_tlu_ctl.scala 2303:73] - wire _T_1154 = mhpme3 == 10'h32; // @[dec_tlu_ctl.scala 2304:34] - wire [5:0] _T_1161 = io_mip & mie; // @[dec_tlu_ctl.scala 2304:113] - wire _T_1162 = |_T_1161; // @[dec_tlu_ctl.scala 2304:125] - wire _T_1163 = _T_1153 & _T_1162; // @[dec_tlu_ctl.scala 2304:98] - wire _T_1164 = mhpme3 == 10'h36; // @[dec_tlu_ctl.scala 2305:34] - wire _T_1166 = pmu_i0_itype_qual == 4'hf; // @[dec_tlu_ctl.scala 2305:91] - wire _T_1167 = mhpme3 == 10'h37; // @[dec_tlu_ctl.scala 2306:34] - wire _T_1169 = io_tlu_i0_commit_cmt & io_lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 2306:94] - wire _T_1170 = mhpme3 == 10'h38; // @[dec_tlu_ctl.scala 2307:34] - wire _T_1172 = io_tlu_i0_commit_cmt & io_lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 2307:94] - wire _T_1173 = mhpme3 == 10'h200; // @[dec_tlu_ctl.scala 2309:34] - wire _T_1175 = mhpme3 == 10'h201; // @[dec_tlu_ctl.scala 2310:34] - wire _T_1177 = mhpme3 == 10'h202; // @[dec_tlu_ctl.scala 2311:34] - wire _T_1179 = mhpme3 == 10'h203; // @[dec_tlu_ctl.scala 2312:34] - wire _T_1181 = mhpme3 == 10'h204; // @[dec_tlu_ctl.scala 2313:34] - wire _T_1184 = _T_1018 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] - wire _T_1185 = _T_1020 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] - wire _T_1186 = _T_1022 & _T_1025; // @[Mux.scala 27:72] - wire _T_1187 = _T_1026 & _T_1031; // @[Mux.scala 27:72] - wire _T_1188 = _T_1032 & _T_1036; // @[Mux.scala 27:72] - wire _T_1189 = _T_1037 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] - wire _T_1190 = _T_1039 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] - wire _T_1191 = _T_1041 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] - wire _T_1192 = _T_1043 & _T_1045; // @[Mux.scala 27:72] - wire _T_1193 = _T_1046 & _T_1048; // @[Mux.scala 27:72] - wire _T_1194 = _T_1049 & _T_1051; // @[Mux.scala 27:72] - wire _T_1195 = _T_1052 & _T_1054; // @[Mux.scala 27:72] - wire _T_1196 = _T_1055 & _T_1058; // @[Mux.scala 27:72] - wire _T_1197 = _T_1059 & _T_1063; // @[Mux.scala 27:72] - wire _T_1198 = _T_1064 & _T_1066; // @[Mux.scala 27:72] - wire _T_1199 = _T_1067 & _T_1069; // @[Mux.scala 27:72] - wire _T_1200 = _T_1070 & _T_1072; // @[Mux.scala 27:72] - wire _T_1201 = _T_1073 & _T_1075; // @[Mux.scala 27:72] - wire _T_1202 = _T_1076 & _T_1078; // @[Mux.scala 27:72] - wire _T_1203 = _T_1079 & _T_1081; // @[Mux.scala 27:72] - wire _T_1204 = _T_1082 & _T_1084; // @[Mux.scala 27:72] - wire _T_1205 = _T_1085 & _T_1087; // @[Mux.scala 27:72] - wire _T_1206 = _T_1088 & _T_1090; // @[Mux.scala 27:72] - wire _T_1207 = _T_1091 & _T_1095; // @[Mux.scala 27:72] - wire _T_1208 = _T_1096 & _T_1098; // @[Mux.scala 27:72] - wire _T_1209 = _T_1099 & _T_1101; // @[Mux.scala 27:72] - wire _T_1210 = _T_1102 & _T_1104; // @[Mux.scala 27:72] - wire _T_1211 = _T_1105 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] - wire _T_1213 = _T_1109 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] - wire _T_1214 = _T_1111 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] - wire _T_1215 = _T_1113 & io_lsu_store_stall_any; // @[Mux.scala 27:72] - wire _T_1216 = _T_1115 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] - wire _T_1217 = _T_1117 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] - wire _T_1218 = _T_1119 & _T_1122; // @[Mux.scala 27:72] - wire _T_1219 = _T_1123 & _T_1126; // @[Mux.scala 27:72] - wire _T_1220 = _T_1127 & io_take_ext_int; // @[Mux.scala 27:72] - wire _T_1221 = _T_1129 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] - wire _T_1222 = _T_1131 & _T_1134; // @[Mux.scala 27:72] - wire _T_1223 = _T_1135 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1224 = _T_1137 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1225 = _T_1139 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] - wire _T_1226 = _T_1141 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1227 = _T_1143 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1228 = _T_1145 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1229 = _T_1147 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1230 = _T_1149 & _T_1153; // @[Mux.scala 27:72] - wire _T_1231 = _T_1154 & _T_1163; // @[Mux.scala 27:72] - wire _T_1232 = _T_1164 & _T_1166; // @[Mux.scala 27:72] - wire _T_1233 = _T_1167 & _T_1169; // @[Mux.scala 27:72] - wire _T_1234 = _T_1170 & _T_1172; // @[Mux.scala 27:72] - wire _T_1235 = _T_1173 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] - wire _T_1236 = _T_1175 & io_dma_pmu_any_read; // @[Mux.scala 27:72] - wire _T_1237 = _T_1177 & io_dma_pmu_any_write; // @[Mux.scala 27:72] - wire _T_1238 = _T_1179 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] - wire _T_1239 = _T_1181 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] - wire _T_1240 = _T_1016 | _T_1184; // @[Mux.scala 27:72] - wire _T_1241 = _T_1240 | _T_1185; // @[Mux.scala 27:72] - wire _T_1242 = _T_1241 | _T_1186; // @[Mux.scala 27:72] - wire _T_1243 = _T_1242 | _T_1187; // @[Mux.scala 27:72] - wire _T_1244 = _T_1243 | _T_1188; // @[Mux.scala 27:72] - wire _T_1245 = _T_1244 | _T_1189; // @[Mux.scala 27:72] - wire _T_1246 = _T_1245 | _T_1190; // @[Mux.scala 27:72] - wire _T_1247 = _T_1246 | _T_1191; // @[Mux.scala 27:72] - wire _T_1248 = _T_1247 | _T_1192; // @[Mux.scala 27:72] - wire _T_1249 = _T_1248 | _T_1193; // @[Mux.scala 27:72] - wire _T_1250 = _T_1249 | _T_1194; // @[Mux.scala 27:72] + wire _T_1026 = mhpme3 == 10'h1; // @[dec_tlu_ctl.scala 2256:34] + wire _T_1028 = mhpme3 == 10'h2; // @[dec_tlu_ctl.scala 2257:34] + wire _T_1030 = mhpme3 == 10'h3; // @[dec_tlu_ctl.scala 2258:34] + wire _T_1032 = mhpme3 == 10'h4; // @[dec_tlu_ctl.scala 2259:34] + wire _T_1034 = ~io_illegal_r; // @[dec_tlu_ctl.scala 2259:96] + wire _T_1035 = io_tlu_i0_commit_cmt & _T_1034; // @[dec_tlu_ctl.scala 2259:94] + wire _T_1036 = mhpme3 == 10'h5; // @[dec_tlu_ctl.scala 2260:34] + wire _T_1038 = ~io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2260:96] + wire _T_1039 = io_tlu_i0_commit_cmt & _T_1038; // @[dec_tlu_ctl.scala 2260:94] + wire _T_1041 = _T_1039 & _T_1034; // @[dec_tlu_ctl.scala 2260:115] + wire _T_1042 = mhpme3 == 10'h6; // @[dec_tlu_ctl.scala 2261:34] + wire _T_1044 = io_tlu_i0_commit_cmt & io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2261:94] + wire _T_1046 = _T_1044 & _T_1034; // @[dec_tlu_ctl.scala 2261:115] + wire _T_1047 = mhpme3 == 10'h7; // @[dec_tlu_ctl.scala 2262:34] + wire _T_1049 = mhpme3 == 10'h8; // @[dec_tlu_ctl.scala 2263:34] + wire _T_1051 = mhpme3 == 10'h1e; // @[dec_tlu_ctl.scala 2264:34] + wire _T_1053 = mhpme3 == 10'h9; // @[dec_tlu_ctl.scala 2265:34] + wire _T_1055 = pmu_i0_itype_qual == 4'h1; // @[dec_tlu_ctl.scala 2265:91] + wire _T_1056 = mhpme3 == 10'ha; // @[dec_tlu_ctl.scala 2266:34] + wire _T_1058 = io_dec_tlu_packet_r_pmu_divide & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2266:105] + wire _T_1059 = mhpme3 == 10'hb; // @[dec_tlu_ctl.scala 2267:34] + wire _T_1061 = pmu_i0_itype_qual == 4'h2; // @[dec_tlu_ctl.scala 2267:91] + wire _T_1062 = mhpme3 == 10'hc; // @[dec_tlu_ctl.scala 2268:34] + wire _T_1064 = pmu_i0_itype_qual == 4'h3; // @[dec_tlu_ctl.scala 2268:91] + wire _T_1065 = mhpme3 == 10'hd; // @[dec_tlu_ctl.scala 2269:34] + wire _T_1068 = _T_1061 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2269:100] + wire _T_1069 = mhpme3 == 10'he; // @[dec_tlu_ctl.scala 2270:34] + wire _T_1073 = _T_1064 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2270:101] + wire _T_1074 = mhpme3 == 10'hf; // @[dec_tlu_ctl.scala 2271:34] + wire _T_1076 = pmu_i0_itype_qual == 4'h4; // @[dec_tlu_ctl.scala 2271:89] + wire _T_1077 = mhpme3 == 10'h10; // @[dec_tlu_ctl.scala 2272:34] + wire _T_1079 = pmu_i0_itype_qual == 4'h5; // @[dec_tlu_ctl.scala 2272:89] + wire _T_1080 = mhpme3 == 10'h12; // @[dec_tlu_ctl.scala 2273:34] + wire _T_1082 = pmu_i0_itype_qual == 4'h6; // @[dec_tlu_ctl.scala 2273:89] + wire _T_1083 = mhpme3 == 10'h11; // @[dec_tlu_ctl.scala 2274:34] + wire _T_1085 = pmu_i0_itype_qual == 4'h7; // @[dec_tlu_ctl.scala 2274:89] + wire _T_1086 = mhpme3 == 10'h13; // @[dec_tlu_ctl.scala 2275:34] + wire _T_1088 = pmu_i0_itype_qual == 4'h8; // @[dec_tlu_ctl.scala 2275:89] + wire _T_1089 = mhpme3 == 10'h14; // @[dec_tlu_ctl.scala 2276:34] + wire _T_1091 = pmu_i0_itype_qual == 4'h9; // @[dec_tlu_ctl.scala 2276:89] + wire _T_1092 = mhpme3 == 10'h15; // @[dec_tlu_ctl.scala 2277:34] + wire _T_1094 = pmu_i0_itype_qual == 4'ha; // @[dec_tlu_ctl.scala 2277:89] + wire _T_1095 = mhpme3 == 10'h16; // @[dec_tlu_ctl.scala 2278:34] + wire _T_1097 = pmu_i0_itype_qual == 4'hb; // @[dec_tlu_ctl.scala 2278:89] + wire _T_1098 = mhpme3 == 10'h17; // @[dec_tlu_ctl.scala 2279:34] + wire _T_1100 = pmu_i0_itype_qual == 4'hc; // @[dec_tlu_ctl.scala 2279:89] + wire _T_1101 = mhpme3 == 10'h18; // @[dec_tlu_ctl.scala 2280:34] + wire _T_1103 = pmu_i0_itype_qual == 4'hd; // @[dec_tlu_ctl.scala 2280:89] + wire _T_1104 = pmu_i0_itype_qual == 4'he; // @[dec_tlu_ctl.scala 2280:122] + wire _T_1105 = _T_1103 | _T_1104; // @[dec_tlu_ctl.scala 2280:101] + wire _T_1106 = mhpme3 == 10'h19; // @[dec_tlu_ctl.scala 2281:34] + wire _T_1108 = io_exu_pmu_i0_br_misp & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2281:95] + wire _T_1109 = mhpme3 == 10'h1a; // @[dec_tlu_ctl.scala 2282:34] + wire _T_1111 = io_exu_pmu_i0_br_ataken & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2282:97] + wire _T_1112 = mhpme3 == 10'h1b; // @[dec_tlu_ctl.scala 2283:34] + wire _T_1114 = io_dec_tlu_packet_r_pmu_i0_br_unpred & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2283:110] + wire _T_1115 = mhpme3 == 10'h1c; // @[dec_tlu_ctl.scala 2284:34] + wire _T_1119 = mhpme3 == 10'h1f; // @[dec_tlu_ctl.scala 2286:34] + wire _T_1121 = mhpme3 == 10'h20; // @[dec_tlu_ctl.scala 2287:34] + wire _T_1123 = mhpme3 == 10'h22; // @[dec_tlu_ctl.scala 2288:34] + wire _T_1125 = mhpme3 == 10'h23; // @[dec_tlu_ctl.scala 2289:34] + wire _T_1127 = mhpme3 == 10'h24; // @[dec_tlu_ctl.scala 2290:34] + wire _T_1129 = mhpme3 == 10'h25; // @[dec_tlu_ctl.scala 2291:34] + wire _T_1131 = io_i0_exception_valid_r | io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 2291:98] + wire _T_1132 = _T_1131 | io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 2291:120] + wire _T_1133 = mhpme3 == 10'h26; // @[dec_tlu_ctl.scala 2292:34] + wire _T_1135 = io_take_timer_int | io_take_int_timer0_int; // @[dec_tlu_ctl.scala 2292:92] + wire _T_1136 = _T_1135 | io_take_int_timer1_int; // @[dec_tlu_ctl.scala 2292:117] + wire _T_1137 = mhpme3 == 10'h27; // @[dec_tlu_ctl.scala 2293:34] + wire _T_1139 = mhpme3 == 10'h28; // @[dec_tlu_ctl.scala 2294:34] + wire _T_1141 = mhpme3 == 10'h29; // @[dec_tlu_ctl.scala 2295:34] + wire _T_1143 = io_dec_tlu_br0_error_r | io_dec_tlu_br0_start_error_r; // @[dec_tlu_ctl.scala 2295:97] + wire _T_1144 = _T_1143 & io_rfpc_i0_r; // @[dec_tlu_ctl.scala 2295:129] + wire _T_1145 = mhpme3 == 10'h2a; // @[dec_tlu_ctl.scala 2296:34] + wire _T_1147 = mhpme3 == 10'h2b; // @[dec_tlu_ctl.scala 2297:34] + wire _T_1149 = mhpme3 == 10'h2c; // @[dec_tlu_ctl.scala 2298:34] + wire _T_1151 = mhpme3 == 10'h2d; // @[dec_tlu_ctl.scala 2299:34] + wire _T_1153 = mhpme3 == 10'h2e; // @[dec_tlu_ctl.scala 2300:34] + wire _T_1155 = mhpme3 == 10'h2f; // @[dec_tlu_ctl.scala 2301:34] + wire _T_1157 = mhpme3 == 10'h30; // @[dec_tlu_ctl.scala 2302:34] + wire _T_1159 = mhpme3 == 10'h31; // @[dec_tlu_ctl.scala 2303:34] + wire _T_1163 = ~io_mstatus[0]; // @[dec_tlu_ctl.scala 2303:73] + wire _T_1164 = mhpme3 == 10'h32; // @[dec_tlu_ctl.scala 2304:34] + wire [5:0] _T_1171 = io_mip & mie; // @[dec_tlu_ctl.scala 2304:113] + wire _T_1172 = |_T_1171; // @[dec_tlu_ctl.scala 2304:125] + wire _T_1173 = _T_1163 & _T_1172; // @[dec_tlu_ctl.scala 2304:98] + wire _T_1174 = mhpme3 == 10'h36; // @[dec_tlu_ctl.scala 2305:34] + wire _T_1176 = pmu_i0_itype_qual == 4'hf; // @[dec_tlu_ctl.scala 2305:91] + wire _T_1177 = mhpme3 == 10'h37; // @[dec_tlu_ctl.scala 2306:34] + wire _T_1179 = io_tlu_i0_commit_cmt & io_lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 2306:94] + wire _T_1180 = mhpme3 == 10'h38; // @[dec_tlu_ctl.scala 2307:34] + wire _T_1182 = io_tlu_i0_commit_cmt & io_lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 2307:94] + wire _T_1183 = mhpme3 == 10'h200; // @[dec_tlu_ctl.scala 2309:34] + wire _T_1185 = mhpme3 == 10'h201; // @[dec_tlu_ctl.scala 2310:34] + wire _T_1187 = mhpme3 == 10'h202; // @[dec_tlu_ctl.scala 2311:34] + wire _T_1189 = mhpme3 == 10'h203; // @[dec_tlu_ctl.scala 2312:34] + wire _T_1191 = mhpme3 == 10'h204; // @[dec_tlu_ctl.scala 2313:34] + wire _T_1194 = _T_1028 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_1195 = _T_1030 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_1196 = _T_1032 & _T_1035; // @[Mux.scala 27:72] + wire _T_1197 = _T_1036 & _T_1041; // @[Mux.scala 27:72] + wire _T_1198 = _T_1042 & _T_1046; // @[Mux.scala 27:72] + wire _T_1199 = _T_1047 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_1200 = _T_1049 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_1201 = _T_1051 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_1202 = _T_1053 & _T_1055; // @[Mux.scala 27:72] + wire _T_1203 = _T_1056 & _T_1058; // @[Mux.scala 27:72] + wire _T_1204 = _T_1059 & _T_1061; // @[Mux.scala 27:72] + wire _T_1205 = _T_1062 & _T_1064; // @[Mux.scala 27:72] + wire _T_1206 = _T_1065 & _T_1068; // @[Mux.scala 27:72] + wire _T_1207 = _T_1069 & _T_1073; // @[Mux.scala 27:72] + wire _T_1208 = _T_1074 & _T_1076; // @[Mux.scala 27:72] + wire _T_1209 = _T_1077 & _T_1079; // @[Mux.scala 27:72] + wire _T_1210 = _T_1080 & _T_1082; // @[Mux.scala 27:72] + wire _T_1211 = _T_1083 & _T_1085; // @[Mux.scala 27:72] + wire _T_1212 = _T_1086 & _T_1088; // @[Mux.scala 27:72] + wire _T_1213 = _T_1089 & _T_1091; // @[Mux.scala 27:72] + wire _T_1214 = _T_1092 & _T_1094; // @[Mux.scala 27:72] + wire _T_1215 = _T_1095 & _T_1097; // @[Mux.scala 27:72] + wire _T_1216 = _T_1098 & _T_1100; // @[Mux.scala 27:72] + wire _T_1217 = _T_1101 & _T_1105; // @[Mux.scala 27:72] + wire _T_1218 = _T_1106 & _T_1108; // @[Mux.scala 27:72] + wire _T_1219 = _T_1109 & _T_1111; // @[Mux.scala 27:72] + wire _T_1220 = _T_1112 & _T_1114; // @[Mux.scala 27:72] + wire _T_1221 = _T_1115 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_1223 = _T_1119 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_1224 = _T_1121 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_1225 = _T_1123 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_1226 = _T_1125 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_1227 = _T_1127 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_1228 = _T_1129 & _T_1132; // @[Mux.scala 27:72] + wire _T_1229 = _T_1133 & _T_1136; // @[Mux.scala 27:72] + wire _T_1230 = _T_1137 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_1231 = _T_1139 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_1232 = _T_1141 & _T_1144; // @[Mux.scala 27:72] + wire _T_1233 = _T_1145 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1234 = _T_1147 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1235 = _T_1149 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_1236 = _T_1151 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1237 = _T_1153 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1238 = _T_1155 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1239 = _T_1157 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1240 = _T_1159 & _T_1163; // @[Mux.scala 27:72] + wire _T_1241 = _T_1164 & _T_1173; // @[Mux.scala 27:72] + wire _T_1242 = _T_1174 & _T_1176; // @[Mux.scala 27:72] + wire _T_1243 = _T_1177 & _T_1179; // @[Mux.scala 27:72] + wire _T_1244 = _T_1180 & _T_1182; // @[Mux.scala 27:72] + wire _T_1245 = _T_1183 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_1246 = _T_1185 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_1247 = _T_1187 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_1248 = _T_1189 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_1249 = _T_1191 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_1250 = _T_1026 | _T_1194; // @[Mux.scala 27:72] wire _T_1251 = _T_1250 | _T_1195; // @[Mux.scala 27:72] wire _T_1252 = _T_1251 | _T_1196; // @[Mux.scala 27:72] wire _T_1253 = _T_1252 | _T_1197; // @[Mux.scala 27:72] @@ -51615,7 +51616,7 @@ module csr_tlu( wire _T_1265 = _T_1264 | _T_1209; // @[Mux.scala 27:72] wire _T_1266 = _T_1265 | _T_1210; // @[Mux.scala 27:72] wire _T_1267 = _T_1266 | _T_1211; // @[Mux.scala 27:72] - wire _T_1268 = _T_1267 | _T_1191; // @[Mux.scala 27:72] + wire _T_1268 = _T_1267 | _T_1212; // @[Mux.scala 27:72] wire _T_1269 = _T_1268 | _T_1213; // @[Mux.scala 27:72] wire _T_1270 = _T_1269 | _T_1214; // @[Mux.scala 27:72] wire _T_1271 = _T_1270 | _T_1215; // @[Mux.scala 27:72] @@ -51625,7 +51626,7 @@ module csr_tlu( wire _T_1275 = _T_1274 | _T_1219; // @[Mux.scala 27:72] wire _T_1276 = _T_1275 | _T_1220; // @[Mux.scala 27:72] wire _T_1277 = _T_1276 | _T_1221; // @[Mux.scala 27:72] - wire _T_1278 = _T_1277 | _T_1222; // @[Mux.scala 27:72] + wire _T_1278 = _T_1277 | _T_1201; // @[Mux.scala 27:72] wire _T_1279 = _T_1278 | _T_1223; // @[Mux.scala 27:72] wire _T_1280 = _T_1279 | _T_1224; // @[Mux.scala 27:72] wire _T_1281 = _T_1280 | _T_1225; // @[Mux.scala 27:72] @@ -51643,131 +51644,131 @@ module csr_tlu( wire _T_1293 = _T_1292 | _T_1237; // @[Mux.scala 27:72] wire _T_1294 = _T_1293 | _T_1238; // @[Mux.scala 27:72] wire _T_1295 = _T_1294 | _T_1239; // @[Mux.scala 27:72] - wire mhpmc_inc_r_0 = _T_1015 & _T_1295; // @[dec_tlu_ctl.scala 2255:44] - wire _T_1299 = ~mcountinhibit[4]; // @[dec_tlu_ctl.scala 2255:24] + wire _T_1296 = _T_1295 | _T_1240; // @[Mux.scala 27:72] + wire _T_1297 = _T_1296 | _T_1241; // @[Mux.scala 27:72] + wire _T_1298 = _T_1297 | _T_1242; // @[Mux.scala 27:72] + wire _T_1299 = _T_1298 | _T_1243; // @[Mux.scala 27:72] + wire _T_1300 = _T_1299 | _T_1244; // @[Mux.scala 27:72] + wire _T_1301 = _T_1300 | _T_1245; // @[Mux.scala 27:72] + wire _T_1302 = _T_1301 | _T_1246; // @[Mux.scala 27:72] + wire _T_1303 = _T_1302 | _T_1247; // @[Mux.scala 27:72] + wire _T_1304 = _T_1303 | _T_1248; // @[Mux.scala 27:72] + wire _T_1305 = _T_1304 | _T_1249; // @[Mux.scala 27:72] + wire mhpmc_inc_r_0 = _T_1025 & _T_1305; // @[dec_tlu_ctl.scala 2255:44] + wire _T_1309 = ~mcountinhibit[4]; // @[dec_tlu_ctl.scala 2255:24] reg [9:0] mhpme4; // @[Reg.scala 27:20] - wire _T_1300 = mhpme4 == 10'h1; // @[dec_tlu_ctl.scala 2256:34] - wire _T_1302 = mhpme4 == 10'h2; // @[dec_tlu_ctl.scala 2257:34] - wire _T_1304 = mhpme4 == 10'h3; // @[dec_tlu_ctl.scala 2258:34] - wire _T_1306 = mhpme4 == 10'h4; // @[dec_tlu_ctl.scala 2259:34] - wire _T_1310 = mhpme4 == 10'h5; // @[dec_tlu_ctl.scala 2260:34] - wire _T_1316 = mhpme4 == 10'h6; // @[dec_tlu_ctl.scala 2261:34] - wire _T_1321 = mhpme4 == 10'h7; // @[dec_tlu_ctl.scala 2262:34] - wire _T_1323 = mhpme4 == 10'h8; // @[dec_tlu_ctl.scala 2263:34] - wire _T_1325 = mhpme4 == 10'h1e; // @[dec_tlu_ctl.scala 2264:34] - wire _T_1327 = mhpme4 == 10'h9; // @[dec_tlu_ctl.scala 2265:34] - wire _T_1330 = mhpme4 == 10'ha; // @[dec_tlu_ctl.scala 2266:34] - wire _T_1333 = mhpme4 == 10'hb; // @[dec_tlu_ctl.scala 2267:34] - wire _T_1336 = mhpme4 == 10'hc; // @[dec_tlu_ctl.scala 2268:34] - wire _T_1339 = mhpme4 == 10'hd; // @[dec_tlu_ctl.scala 2269:34] - wire _T_1343 = mhpme4 == 10'he; // @[dec_tlu_ctl.scala 2270:34] - wire _T_1348 = mhpme4 == 10'hf; // @[dec_tlu_ctl.scala 2271:34] - wire _T_1351 = mhpme4 == 10'h10; // @[dec_tlu_ctl.scala 2272:34] - wire _T_1354 = mhpme4 == 10'h12; // @[dec_tlu_ctl.scala 2273:34] - wire _T_1357 = mhpme4 == 10'h11; // @[dec_tlu_ctl.scala 2274:34] - wire _T_1360 = mhpme4 == 10'h13; // @[dec_tlu_ctl.scala 2275:34] - wire _T_1363 = mhpme4 == 10'h14; // @[dec_tlu_ctl.scala 2276:34] - wire _T_1366 = mhpme4 == 10'h15; // @[dec_tlu_ctl.scala 2277:34] - wire _T_1369 = mhpme4 == 10'h16; // @[dec_tlu_ctl.scala 2278:34] - wire _T_1372 = mhpme4 == 10'h17; // @[dec_tlu_ctl.scala 2279:34] - wire _T_1375 = mhpme4 == 10'h18; // @[dec_tlu_ctl.scala 2280:34] - wire _T_1380 = mhpme4 == 10'h19; // @[dec_tlu_ctl.scala 2281:34] - wire _T_1383 = mhpme4 == 10'h1a; // @[dec_tlu_ctl.scala 2282:34] - wire _T_1386 = mhpme4 == 10'h1b; // @[dec_tlu_ctl.scala 2283:34] - wire _T_1389 = mhpme4 == 10'h1c; // @[dec_tlu_ctl.scala 2284:34] - wire _T_1393 = mhpme4 == 10'h1f; // @[dec_tlu_ctl.scala 2286:34] - wire _T_1395 = mhpme4 == 10'h20; // @[dec_tlu_ctl.scala 2287:34] - wire _T_1397 = mhpme4 == 10'h22; // @[dec_tlu_ctl.scala 2288:34] - wire _T_1399 = mhpme4 == 10'h23; // @[dec_tlu_ctl.scala 2289:34] - wire _T_1401 = mhpme4 == 10'h24; // @[dec_tlu_ctl.scala 2290:34] - wire _T_1403 = mhpme4 == 10'h25; // @[dec_tlu_ctl.scala 2291:34] - wire _T_1407 = mhpme4 == 10'h26; // @[dec_tlu_ctl.scala 2292:34] - wire _T_1411 = mhpme4 == 10'h27; // @[dec_tlu_ctl.scala 2293:34] - wire _T_1413 = mhpme4 == 10'h28; // @[dec_tlu_ctl.scala 2294:34] - wire _T_1415 = mhpme4 == 10'h29; // @[dec_tlu_ctl.scala 2295:34] - wire _T_1419 = mhpme4 == 10'h2a; // @[dec_tlu_ctl.scala 2296:34] - wire _T_1421 = mhpme4 == 10'h2b; // @[dec_tlu_ctl.scala 2297:34] - wire _T_1423 = mhpme4 == 10'h2c; // @[dec_tlu_ctl.scala 2298:34] - wire _T_1425 = mhpme4 == 10'h2d; // @[dec_tlu_ctl.scala 2299:34] - wire _T_1427 = mhpme4 == 10'h2e; // @[dec_tlu_ctl.scala 2300:34] - wire _T_1429 = mhpme4 == 10'h2f; // @[dec_tlu_ctl.scala 2301:34] - wire _T_1431 = mhpme4 == 10'h30; // @[dec_tlu_ctl.scala 2302:34] - wire _T_1433 = mhpme4 == 10'h31; // @[dec_tlu_ctl.scala 2303:34] - wire _T_1438 = mhpme4 == 10'h32; // @[dec_tlu_ctl.scala 2304:34] - wire _T_1448 = mhpme4 == 10'h36; // @[dec_tlu_ctl.scala 2305:34] - wire _T_1451 = mhpme4 == 10'h37; // @[dec_tlu_ctl.scala 2306:34] - wire _T_1454 = mhpme4 == 10'h38; // @[dec_tlu_ctl.scala 2307:34] - wire _T_1457 = mhpme4 == 10'h200; // @[dec_tlu_ctl.scala 2309:34] - wire _T_1459 = mhpme4 == 10'h201; // @[dec_tlu_ctl.scala 2310:34] - wire _T_1461 = mhpme4 == 10'h202; // @[dec_tlu_ctl.scala 2311:34] - wire _T_1463 = mhpme4 == 10'h203; // @[dec_tlu_ctl.scala 2312:34] - wire _T_1465 = mhpme4 == 10'h204; // @[dec_tlu_ctl.scala 2313:34] - wire _T_1468 = _T_1302 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] - wire _T_1469 = _T_1304 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] - wire _T_1470 = _T_1306 & _T_1025; // @[Mux.scala 27:72] - wire _T_1471 = _T_1310 & _T_1031; // @[Mux.scala 27:72] - wire _T_1472 = _T_1316 & _T_1036; // @[Mux.scala 27:72] - wire _T_1473 = _T_1321 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] - wire _T_1474 = _T_1323 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] - wire _T_1475 = _T_1325 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] - wire _T_1476 = _T_1327 & _T_1045; // @[Mux.scala 27:72] - wire _T_1477 = _T_1330 & _T_1048; // @[Mux.scala 27:72] - wire _T_1478 = _T_1333 & _T_1051; // @[Mux.scala 27:72] - wire _T_1479 = _T_1336 & _T_1054; // @[Mux.scala 27:72] - wire _T_1480 = _T_1339 & _T_1058; // @[Mux.scala 27:72] - wire _T_1481 = _T_1343 & _T_1063; // @[Mux.scala 27:72] - wire _T_1482 = _T_1348 & _T_1066; // @[Mux.scala 27:72] - wire _T_1483 = _T_1351 & _T_1069; // @[Mux.scala 27:72] - wire _T_1484 = _T_1354 & _T_1072; // @[Mux.scala 27:72] - wire _T_1485 = _T_1357 & _T_1075; // @[Mux.scala 27:72] - wire _T_1486 = _T_1360 & _T_1078; // @[Mux.scala 27:72] - wire _T_1487 = _T_1363 & _T_1081; // @[Mux.scala 27:72] - wire _T_1488 = _T_1366 & _T_1084; // @[Mux.scala 27:72] - wire _T_1489 = _T_1369 & _T_1087; // @[Mux.scala 27:72] - wire _T_1490 = _T_1372 & _T_1090; // @[Mux.scala 27:72] - wire _T_1491 = _T_1375 & _T_1095; // @[Mux.scala 27:72] - wire _T_1492 = _T_1380 & _T_1098; // @[Mux.scala 27:72] - wire _T_1493 = _T_1383 & _T_1101; // @[Mux.scala 27:72] - wire _T_1494 = _T_1386 & _T_1104; // @[Mux.scala 27:72] - wire _T_1495 = _T_1389 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] - wire _T_1497 = _T_1393 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] - wire _T_1498 = _T_1395 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] - wire _T_1499 = _T_1397 & io_lsu_store_stall_any; // @[Mux.scala 27:72] - wire _T_1500 = _T_1399 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] - wire _T_1501 = _T_1401 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] - wire _T_1502 = _T_1403 & _T_1122; // @[Mux.scala 27:72] - wire _T_1503 = _T_1407 & _T_1126; // @[Mux.scala 27:72] - wire _T_1504 = _T_1411 & io_take_ext_int; // @[Mux.scala 27:72] - wire _T_1505 = _T_1413 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] - wire _T_1506 = _T_1415 & _T_1134; // @[Mux.scala 27:72] - wire _T_1507 = _T_1419 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1508 = _T_1421 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1509 = _T_1423 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] - wire _T_1510 = _T_1425 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1511 = _T_1427 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1512 = _T_1429 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1513 = _T_1431 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1514 = _T_1433 & _T_1153; // @[Mux.scala 27:72] - wire _T_1515 = _T_1438 & _T_1163; // @[Mux.scala 27:72] - wire _T_1516 = _T_1448 & _T_1166; // @[Mux.scala 27:72] - wire _T_1517 = _T_1451 & _T_1169; // @[Mux.scala 27:72] - wire _T_1518 = _T_1454 & _T_1172; // @[Mux.scala 27:72] - wire _T_1519 = _T_1457 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] - wire _T_1520 = _T_1459 & io_dma_pmu_any_read; // @[Mux.scala 27:72] - wire _T_1521 = _T_1461 & io_dma_pmu_any_write; // @[Mux.scala 27:72] - wire _T_1522 = _T_1463 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] - wire _T_1523 = _T_1465 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] - wire _T_1524 = _T_1300 | _T_1468; // @[Mux.scala 27:72] - wire _T_1525 = _T_1524 | _T_1469; // @[Mux.scala 27:72] - wire _T_1526 = _T_1525 | _T_1470; // @[Mux.scala 27:72] - wire _T_1527 = _T_1526 | _T_1471; // @[Mux.scala 27:72] - wire _T_1528 = _T_1527 | _T_1472; // @[Mux.scala 27:72] - wire _T_1529 = _T_1528 | _T_1473; // @[Mux.scala 27:72] - wire _T_1530 = _T_1529 | _T_1474; // @[Mux.scala 27:72] - wire _T_1531 = _T_1530 | _T_1475; // @[Mux.scala 27:72] - wire _T_1532 = _T_1531 | _T_1476; // @[Mux.scala 27:72] - wire _T_1533 = _T_1532 | _T_1477; // @[Mux.scala 27:72] - wire _T_1534 = _T_1533 | _T_1478; // @[Mux.scala 27:72] + wire _T_1310 = mhpme4 == 10'h1; // @[dec_tlu_ctl.scala 2256:34] + wire _T_1312 = mhpme4 == 10'h2; // @[dec_tlu_ctl.scala 2257:34] + wire _T_1314 = mhpme4 == 10'h3; // @[dec_tlu_ctl.scala 2258:34] + wire _T_1316 = mhpme4 == 10'h4; // @[dec_tlu_ctl.scala 2259:34] + wire _T_1320 = mhpme4 == 10'h5; // @[dec_tlu_ctl.scala 2260:34] + wire _T_1326 = mhpme4 == 10'h6; // @[dec_tlu_ctl.scala 2261:34] + wire _T_1331 = mhpme4 == 10'h7; // @[dec_tlu_ctl.scala 2262:34] + wire _T_1333 = mhpme4 == 10'h8; // @[dec_tlu_ctl.scala 2263:34] + wire _T_1335 = mhpme4 == 10'h1e; // @[dec_tlu_ctl.scala 2264:34] + wire _T_1337 = mhpme4 == 10'h9; // @[dec_tlu_ctl.scala 2265:34] + wire _T_1340 = mhpme4 == 10'ha; // @[dec_tlu_ctl.scala 2266:34] + wire _T_1343 = mhpme4 == 10'hb; // @[dec_tlu_ctl.scala 2267:34] + wire _T_1346 = mhpme4 == 10'hc; // @[dec_tlu_ctl.scala 2268:34] + wire _T_1349 = mhpme4 == 10'hd; // @[dec_tlu_ctl.scala 2269:34] + wire _T_1353 = mhpme4 == 10'he; // @[dec_tlu_ctl.scala 2270:34] + wire _T_1358 = mhpme4 == 10'hf; // @[dec_tlu_ctl.scala 2271:34] + wire _T_1361 = mhpme4 == 10'h10; // @[dec_tlu_ctl.scala 2272:34] + wire _T_1364 = mhpme4 == 10'h12; // @[dec_tlu_ctl.scala 2273:34] + wire _T_1367 = mhpme4 == 10'h11; // @[dec_tlu_ctl.scala 2274:34] + wire _T_1370 = mhpme4 == 10'h13; // @[dec_tlu_ctl.scala 2275:34] + wire _T_1373 = mhpme4 == 10'h14; // @[dec_tlu_ctl.scala 2276:34] + wire _T_1376 = mhpme4 == 10'h15; // @[dec_tlu_ctl.scala 2277:34] + wire _T_1379 = mhpme4 == 10'h16; // @[dec_tlu_ctl.scala 2278:34] + wire _T_1382 = mhpme4 == 10'h17; // @[dec_tlu_ctl.scala 2279:34] + wire _T_1385 = mhpme4 == 10'h18; // @[dec_tlu_ctl.scala 2280:34] + wire _T_1390 = mhpme4 == 10'h19; // @[dec_tlu_ctl.scala 2281:34] + wire _T_1393 = mhpme4 == 10'h1a; // @[dec_tlu_ctl.scala 2282:34] + wire _T_1396 = mhpme4 == 10'h1b; // @[dec_tlu_ctl.scala 2283:34] + wire _T_1399 = mhpme4 == 10'h1c; // @[dec_tlu_ctl.scala 2284:34] + wire _T_1403 = mhpme4 == 10'h1f; // @[dec_tlu_ctl.scala 2286:34] + wire _T_1405 = mhpme4 == 10'h20; // @[dec_tlu_ctl.scala 2287:34] + wire _T_1407 = mhpme4 == 10'h22; // @[dec_tlu_ctl.scala 2288:34] + wire _T_1409 = mhpme4 == 10'h23; // @[dec_tlu_ctl.scala 2289:34] + wire _T_1411 = mhpme4 == 10'h24; // @[dec_tlu_ctl.scala 2290:34] + wire _T_1413 = mhpme4 == 10'h25; // @[dec_tlu_ctl.scala 2291:34] + wire _T_1417 = mhpme4 == 10'h26; // @[dec_tlu_ctl.scala 2292:34] + wire _T_1421 = mhpme4 == 10'h27; // @[dec_tlu_ctl.scala 2293:34] + wire _T_1423 = mhpme4 == 10'h28; // @[dec_tlu_ctl.scala 2294:34] + wire _T_1425 = mhpme4 == 10'h29; // @[dec_tlu_ctl.scala 2295:34] + wire _T_1429 = mhpme4 == 10'h2a; // @[dec_tlu_ctl.scala 2296:34] + wire _T_1431 = mhpme4 == 10'h2b; // @[dec_tlu_ctl.scala 2297:34] + wire _T_1433 = mhpme4 == 10'h2c; // @[dec_tlu_ctl.scala 2298:34] + wire _T_1435 = mhpme4 == 10'h2d; // @[dec_tlu_ctl.scala 2299:34] + wire _T_1437 = mhpme4 == 10'h2e; // @[dec_tlu_ctl.scala 2300:34] + wire _T_1439 = mhpme4 == 10'h2f; // @[dec_tlu_ctl.scala 2301:34] + wire _T_1441 = mhpme4 == 10'h30; // @[dec_tlu_ctl.scala 2302:34] + wire _T_1443 = mhpme4 == 10'h31; // @[dec_tlu_ctl.scala 2303:34] + wire _T_1448 = mhpme4 == 10'h32; // @[dec_tlu_ctl.scala 2304:34] + wire _T_1458 = mhpme4 == 10'h36; // @[dec_tlu_ctl.scala 2305:34] + wire _T_1461 = mhpme4 == 10'h37; // @[dec_tlu_ctl.scala 2306:34] + wire _T_1464 = mhpme4 == 10'h38; // @[dec_tlu_ctl.scala 2307:34] + wire _T_1467 = mhpme4 == 10'h200; // @[dec_tlu_ctl.scala 2309:34] + wire _T_1469 = mhpme4 == 10'h201; // @[dec_tlu_ctl.scala 2310:34] + wire _T_1471 = mhpme4 == 10'h202; // @[dec_tlu_ctl.scala 2311:34] + wire _T_1473 = mhpme4 == 10'h203; // @[dec_tlu_ctl.scala 2312:34] + wire _T_1475 = mhpme4 == 10'h204; // @[dec_tlu_ctl.scala 2313:34] + wire _T_1478 = _T_1312 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_1479 = _T_1314 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_1480 = _T_1316 & _T_1035; // @[Mux.scala 27:72] + wire _T_1481 = _T_1320 & _T_1041; // @[Mux.scala 27:72] + wire _T_1482 = _T_1326 & _T_1046; // @[Mux.scala 27:72] + wire _T_1483 = _T_1331 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_1484 = _T_1333 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_1485 = _T_1335 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_1486 = _T_1337 & _T_1055; // @[Mux.scala 27:72] + wire _T_1487 = _T_1340 & _T_1058; // @[Mux.scala 27:72] + wire _T_1488 = _T_1343 & _T_1061; // @[Mux.scala 27:72] + wire _T_1489 = _T_1346 & _T_1064; // @[Mux.scala 27:72] + wire _T_1490 = _T_1349 & _T_1068; // @[Mux.scala 27:72] + wire _T_1491 = _T_1353 & _T_1073; // @[Mux.scala 27:72] + wire _T_1492 = _T_1358 & _T_1076; // @[Mux.scala 27:72] + wire _T_1493 = _T_1361 & _T_1079; // @[Mux.scala 27:72] + wire _T_1494 = _T_1364 & _T_1082; // @[Mux.scala 27:72] + wire _T_1495 = _T_1367 & _T_1085; // @[Mux.scala 27:72] + wire _T_1496 = _T_1370 & _T_1088; // @[Mux.scala 27:72] + wire _T_1497 = _T_1373 & _T_1091; // @[Mux.scala 27:72] + wire _T_1498 = _T_1376 & _T_1094; // @[Mux.scala 27:72] + wire _T_1499 = _T_1379 & _T_1097; // @[Mux.scala 27:72] + wire _T_1500 = _T_1382 & _T_1100; // @[Mux.scala 27:72] + wire _T_1501 = _T_1385 & _T_1105; // @[Mux.scala 27:72] + wire _T_1502 = _T_1390 & _T_1108; // @[Mux.scala 27:72] + wire _T_1503 = _T_1393 & _T_1111; // @[Mux.scala 27:72] + wire _T_1504 = _T_1396 & _T_1114; // @[Mux.scala 27:72] + wire _T_1505 = _T_1399 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_1507 = _T_1403 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_1508 = _T_1405 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_1509 = _T_1407 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_1510 = _T_1409 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_1511 = _T_1411 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_1512 = _T_1413 & _T_1132; // @[Mux.scala 27:72] + wire _T_1513 = _T_1417 & _T_1136; // @[Mux.scala 27:72] + wire _T_1514 = _T_1421 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_1515 = _T_1423 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_1516 = _T_1425 & _T_1144; // @[Mux.scala 27:72] + wire _T_1517 = _T_1429 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1518 = _T_1431 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1519 = _T_1433 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_1520 = _T_1435 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1521 = _T_1437 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1522 = _T_1439 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1523 = _T_1441 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1524 = _T_1443 & _T_1163; // @[Mux.scala 27:72] + wire _T_1525 = _T_1448 & _T_1173; // @[Mux.scala 27:72] + wire _T_1526 = _T_1458 & _T_1176; // @[Mux.scala 27:72] + wire _T_1527 = _T_1461 & _T_1179; // @[Mux.scala 27:72] + wire _T_1528 = _T_1464 & _T_1182; // @[Mux.scala 27:72] + wire _T_1529 = _T_1467 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_1530 = _T_1469 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_1531 = _T_1471 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_1532 = _T_1473 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_1533 = _T_1475 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_1534 = _T_1310 | _T_1478; // @[Mux.scala 27:72] wire _T_1535 = _T_1534 | _T_1479; // @[Mux.scala 27:72] wire _T_1536 = _T_1535 | _T_1480; // @[Mux.scala 27:72] wire _T_1537 = _T_1536 | _T_1481; // @[Mux.scala 27:72] @@ -51785,7 +51786,7 @@ module csr_tlu( wire _T_1549 = _T_1548 | _T_1493; // @[Mux.scala 27:72] wire _T_1550 = _T_1549 | _T_1494; // @[Mux.scala 27:72] wire _T_1551 = _T_1550 | _T_1495; // @[Mux.scala 27:72] - wire _T_1552 = _T_1551 | _T_1475; // @[Mux.scala 27:72] + wire _T_1552 = _T_1551 | _T_1496; // @[Mux.scala 27:72] wire _T_1553 = _T_1552 | _T_1497; // @[Mux.scala 27:72] wire _T_1554 = _T_1553 | _T_1498; // @[Mux.scala 27:72] wire _T_1555 = _T_1554 | _T_1499; // @[Mux.scala 27:72] @@ -51795,7 +51796,7 @@ module csr_tlu( wire _T_1559 = _T_1558 | _T_1503; // @[Mux.scala 27:72] wire _T_1560 = _T_1559 | _T_1504; // @[Mux.scala 27:72] wire _T_1561 = _T_1560 | _T_1505; // @[Mux.scala 27:72] - wire _T_1562 = _T_1561 | _T_1506; // @[Mux.scala 27:72] + wire _T_1562 = _T_1561 | _T_1485; // @[Mux.scala 27:72] wire _T_1563 = _T_1562 | _T_1507; // @[Mux.scala 27:72] wire _T_1564 = _T_1563 | _T_1508; // @[Mux.scala 27:72] wire _T_1565 = _T_1564 | _T_1509; // @[Mux.scala 27:72] @@ -51813,131 +51814,131 @@ module csr_tlu( wire _T_1577 = _T_1576 | _T_1521; // @[Mux.scala 27:72] wire _T_1578 = _T_1577 | _T_1522; // @[Mux.scala 27:72] wire _T_1579 = _T_1578 | _T_1523; // @[Mux.scala 27:72] - wire mhpmc_inc_r_1 = _T_1299 & _T_1579; // @[dec_tlu_ctl.scala 2255:44] - wire _T_1583 = ~mcountinhibit[5]; // @[dec_tlu_ctl.scala 2255:24] + wire _T_1580 = _T_1579 | _T_1524; // @[Mux.scala 27:72] + wire _T_1581 = _T_1580 | _T_1525; // @[Mux.scala 27:72] + wire _T_1582 = _T_1581 | _T_1526; // @[Mux.scala 27:72] + wire _T_1583 = _T_1582 | _T_1527; // @[Mux.scala 27:72] + wire _T_1584 = _T_1583 | _T_1528; // @[Mux.scala 27:72] + wire _T_1585 = _T_1584 | _T_1529; // @[Mux.scala 27:72] + wire _T_1586 = _T_1585 | _T_1530; // @[Mux.scala 27:72] + wire _T_1587 = _T_1586 | _T_1531; // @[Mux.scala 27:72] + wire _T_1588 = _T_1587 | _T_1532; // @[Mux.scala 27:72] + wire _T_1589 = _T_1588 | _T_1533; // @[Mux.scala 27:72] + wire mhpmc_inc_r_1 = _T_1309 & _T_1589; // @[dec_tlu_ctl.scala 2255:44] + wire _T_1593 = ~mcountinhibit[5]; // @[dec_tlu_ctl.scala 2255:24] reg [9:0] mhpme5; // @[Reg.scala 27:20] - wire _T_1584 = mhpme5 == 10'h1; // @[dec_tlu_ctl.scala 2256:34] - wire _T_1586 = mhpme5 == 10'h2; // @[dec_tlu_ctl.scala 2257:34] - wire _T_1588 = mhpme5 == 10'h3; // @[dec_tlu_ctl.scala 2258:34] - wire _T_1590 = mhpme5 == 10'h4; // @[dec_tlu_ctl.scala 2259:34] - wire _T_1594 = mhpme5 == 10'h5; // @[dec_tlu_ctl.scala 2260:34] - wire _T_1600 = mhpme5 == 10'h6; // @[dec_tlu_ctl.scala 2261:34] - wire _T_1605 = mhpme5 == 10'h7; // @[dec_tlu_ctl.scala 2262:34] - wire _T_1607 = mhpme5 == 10'h8; // @[dec_tlu_ctl.scala 2263:34] - wire _T_1609 = mhpme5 == 10'h1e; // @[dec_tlu_ctl.scala 2264:34] - wire _T_1611 = mhpme5 == 10'h9; // @[dec_tlu_ctl.scala 2265:34] - wire _T_1614 = mhpme5 == 10'ha; // @[dec_tlu_ctl.scala 2266:34] - wire _T_1617 = mhpme5 == 10'hb; // @[dec_tlu_ctl.scala 2267:34] - wire _T_1620 = mhpme5 == 10'hc; // @[dec_tlu_ctl.scala 2268:34] - wire _T_1623 = mhpme5 == 10'hd; // @[dec_tlu_ctl.scala 2269:34] - wire _T_1627 = mhpme5 == 10'he; // @[dec_tlu_ctl.scala 2270:34] - wire _T_1632 = mhpme5 == 10'hf; // @[dec_tlu_ctl.scala 2271:34] - wire _T_1635 = mhpme5 == 10'h10; // @[dec_tlu_ctl.scala 2272:34] - wire _T_1638 = mhpme5 == 10'h12; // @[dec_tlu_ctl.scala 2273:34] - wire _T_1641 = mhpme5 == 10'h11; // @[dec_tlu_ctl.scala 2274:34] - wire _T_1644 = mhpme5 == 10'h13; // @[dec_tlu_ctl.scala 2275:34] - wire _T_1647 = mhpme5 == 10'h14; // @[dec_tlu_ctl.scala 2276:34] - wire _T_1650 = mhpme5 == 10'h15; // @[dec_tlu_ctl.scala 2277:34] - wire _T_1653 = mhpme5 == 10'h16; // @[dec_tlu_ctl.scala 2278:34] - wire _T_1656 = mhpme5 == 10'h17; // @[dec_tlu_ctl.scala 2279:34] - wire _T_1659 = mhpme5 == 10'h18; // @[dec_tlu_ctl.scala 2280:34] - wire _T_1664 = mhpme5 == 10'h19; // @[dec_tlu_ctl.scala 2281:34] - wire _T_1667 = mhpme5 == 10'h1a; // @[dec_tlu_ctl.scala 2282:34] - wire _T_1670 = mhpme5 == 10'h1b; // @[dec_tlu_ctl.scala 2283:34] - wire _T_1673 = mhpme5 == 10'h1c; // @[dec_tlu_ctl.scala 2284:34] - wire _T_1677 = mhpme5 == 10'h1f; // @[dec_tlu_ctl.scala 2286:34] - wire _T_1679 = mhpme5 == 10'h20; // @[dec_tlu_ctl.scala 2287:34] - wire _T_1681 = mhpme5 == 10'h22; // @[dec_tlu_ctl.scala 2288:34] - wire _T_1683 = mhpme5 == 10'h23; // @[dec_tlu_ctl.scala 2289:34] - wire _T_1685 = mhpme5 == 10'h24; // @[dec_tlu_ctl.scala 2290:34] - wire _T_1687 = mhpme5 == 10'h25; // @[dec_tlu_ctl.scala 2291:34] - wire _T_1691 = mhpme5 == 10'h26; // @[dec_tlu_ctl.scala 2292:34] - wire _T_1695 = mhpme5 == 10'h27; // @[dec_tlu_ctl.scala 2293:34] - wire _T_1697 = mhpme5 == 10'h28; // @[dec_tlu_ctl.scala 2294:34] - wire _T_1699 = mhpme5 == 10'h29; // @[dec_tlu_ctl.scala 2295:34] - wire _T_1703 = mhpme5 == 10'h2a; // @[dec_tlu_ctl.scala 2296:34] - wire _T_1705 = mhpme5 == 10'h2b; // @[dec_tlu_ctl.scala 2297:34] - wire _T_1707 = mhpme5 == 10'h2c; // @[dec_tlu_ctl.scala 2298:34] - wire _T_1709 = mhpme5 == 10'h2d; // @[dec_tlu_ctl.scala 2299:34] - wire _T_1711 = mhpme5 == 10'h2e; // @[dec_tlu_ctl.scala 2300:34] - wire _T_1713 = mhpme5 == 10'h2f; // @[dec_tlu_ctl.scala 2301:34] - wire _T_1715 = mhpme5 == 10'h30; // @[dec_tlu_ctl.scala 2302:34] - wire _T_1717 = mhpme5 == 10'h31; // @[dec_tlu_ctl.scala 2303:34] - wire _T_1722 = mhpme5 == 10'h32; // @[dec_tlu_ctl.scala 2304:34] - wire _T_1732 = mhpme5 == 10'h36; // @[dec_tlu_ctl.scala 2305:34] - wire _T_1735 = mhpme5 == 10'h37; // @[dec_tlu_ctl.scala 2306:34] - wire _T_1738 = mhpme5 == 10'h38; // @[dec_tlu_ctl.scala 2307:34] - wire _T_1741 = mhpme5 == 10'h200; // @[dec_tlu_ctl.scala 2309:34] - wire _T_1743 = mhpme5 == 10'h201; // @[dec_tlu_ctl.scala 2310:34] - wire _T_1745 = mhpme5 == 10'h202; // @[dec_tlu_ctl.scala 2311:34] - wire _T_1747 = mhpme5 == 10'h203; // @[dec_tlu_ctl.scala 2312:34] - wire _T_1749 = mhpme5 == 10'h204; // @[dec_tlu_ctl.scala 2313:34] - wire _T_1752 = _T_1586 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] - wire _T_1753 = _T_1588 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] - wire _T_1754 = _T_1590 & _T_1025; // @[Mux.scala 27:72] - wire _T_1755 = _T_1594 & _T_1031; // @[Mux.scala 27:72] - wire _T_1756 = _T_1600 & _T_1036; // @[Mux.scala 27:72] - wire _T_1757 = _T_1605 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] - wire _T_1758 = _T_1607 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] - wire _T_1759 = _T_1609 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] - wire _T_1760 = _T_1611 & _T_1045; // @[Mux.scala 27:72] - wire _T_1761 = _T_1614 & _T_1048; // @[Mux.scala 27:72] - wire _T_1762 = _T_1617 & _T_1051; // @[Mux.scala 27:72] - wire _T_1763 = _T_1620 & _T_1054; // @[Mux.scala 27:72] - wire _T_1764 = _T_1623 & _T_1058; // @[Mux.scala 27:72] - wire _T_1765 = _T_1627 & _T_1063; // @[Mux.scala 27:72] - wire _T_1766 = _T_1632 & _T_1066; // @[Mux.scala 27:72] - wire _T_1767 = _T_1635 & _T_1069; // @[Mux.scala 27:72] - wire _T_1768 = _T_1638 & _T_1072; // @[Mux.scala 27:72] - wire _T_1769 = _T_1641 & _T_1075; // @[Mux.scala 27:72] - wire _T_1770 = _T_1644 & _T_1078; // @[Mux.scala 27:72] - wire _T_1771 = _T_1647 & _T_1081; // @[Mux.scala 27:72] - wire _T_1772 = _T_1650 & _T_1084; // @[Mux.scala 27:72] - wire _T_1773 = _T_1653 & _T_1087; // @[Mux.scala 27:72] - wire _T_1774 = _T_1656 & _T_1090; // @[Mux.scala 27:72] - wire _T_1775 = _T_1659 & _T_1095; // @[Mux.scala 27:72] - wire _T_1776 = _T_1664 & _T_1098; // @[Mux.scala 27:72] - wire _T_1777 = _T_1667 & _T_1101; // @[Mux.scala 27:72] - wire _T_1778 = _T_1670 & _T_1104; // @[Mux.scala 27:72] - wire _T_1779 = _T_1673 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] - wire _T_1781 = _T_1677 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] - wire _T_1782 = _T_1679 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] - wire _T_1783 = _T_1681 & io_lsu_store_stall_any; // @[Mux.scala 27:72] - wire _T_1784 = _T_1683 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] - wire _T_1785 = _T_1685 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] - wire _T_1786 = _T_1687 & _T_1122; // @[Mux.scala 27:72] - wire _T_1787 = _T_1691 & _T_1126; // @[Mux.scala 27:72] - wire _T_1788 = _T_1695 & io_take_ext_int; // @[Mux.scala 27:72] - wire _T_1789 = _T_1697 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] - wire _T_1790 = _T_1699 & _T_1134; // @[Mux.scala 27:72] - wire _T_1791 = _T_1703 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1792 = _T_1705 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1793 = _T_1707 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] - wire _T_1794 = _T_1709 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1795 = _T_1711 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1796 = _T_1713 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1797 = _T_1715 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1798 = _T_1717 & _T_1153; // @[Mux.scala 27:72] - wire _T_1799 = _T_1722 & _T_1163; // @[Mux.scala 27:72] - wire _T_1800 = _T_1732 & _T_1166; // @[Mux.scala 27:72] - wire _T_1801 = _T_1735 & _T_1169; // @[Mux.scala 27:72] - wire _T_1802 = _T_1738 & _T_1172; // @[Mux.scala 27:72] - wire _T_1803 = _T_1741 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] - wire _T_1804 = _T_1743 & io_dma_pmu_any_read; // @[Mux.scala 27:72] - wire _T_1805 = _T_1745 & io_dma_pmu_any_write; // @[Mux.scala 27:72] - wire _T_1806 = _T_1747 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] - wire _T_1807 = _T_1749 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] - wire _T_1808 = _T_1584 | _T_1752; // @[Mux.scala 27:72] - wire _T_1809 = _T_1808 | _T_1753; // @[Mux.scala 27:72] - wire _T_1810 = _T_1809 | _T_1754; // @[Mux.scala 27:72] - wire _T_1811 = _T_1810 | _T_1755; // @[Mux.scala 27:72] - wire _T_1812 = _T_1811 | _T_1756; // @[Mux.scala 27:72] - wire _T_1813 = _T_1812 | _T_1757; // @[Mux.scala 27:72] - wire _T_1814 = _T_1813 | _T_1758; // @[Mux.scala 27:72] - wire _T_1815 = _T_1814 | _T_1759; // @[Mux.scala 27:72] - wire _T_1816 = _T_1815 | _T_1760; // @[Mux.scala 27:72] - wire _T_1817 = _T_1816 | _T_1761; // @[Mux.scala 27:72] - wire _T_1818 = _T_1817 | _T_1762; // @[Mux.scala 27:72] + wire _T_1594 = mhpme5 == 10'h1; // @[dec_tlu_ctl.scala 2256:34] + wire _T_1596 = mhpme5 == 10'h2; // @[dec_tlu_ctl.scala 2257:34] + wire _T_1598 = mhpme5 == 10'h3; // @[dec_tlu_ctl.scala 2258:34] + wire _T_1600 = mhpme5 == 10'h4; // @[dec_tlu_ctl.scala 2259:34] + wire _T_1604 = mhpme5 == 10'h5; // @[dec_tlu_ctl.scala 2260:34] + wire _T_1610 = mhpme5 == 10'h6; // @[dec_tlu_ctl.scala 2261:34] + wire _T_1615 = mhpme5 == 10'h7; // @[dec_tlu_ctl.scala 2262:34] + wire _T_1617 = mhpme5 == 10'h8; // @[dec_tlu_ctl.scala 2263:34] + wire _T_1619 = mhpme5 == 10'h1e; // @[dec_tlu_ctl.scala 2264:34] + wire _T_1621 = mhpme5 == 10'h9; // @[dec_tlu_ctl.scala 2265:34] + wire _T_1624 = mhpme5 == 10'ha; // @[dec_tlu_ctl.scala 2266:34] + wire _T_1627 = mhpme5 == 10'hb; // @[dec_tlu_ctl.scala 2267:34] + wire _T_1630 = mhpme5 == 10'hc; // @[dec_tlu_ctl.scala 2268:34] + wire _T_1633 = mhpme5 == 10'hd; // @[dec_tlu_ctl.scala 2269:34] + wire _T_1637 = mhpme5 == 10'he; // @[dec_tlu_ctl.scala 2270:34] + wire _T_1642 = mhpme5 == 10'hf; // @[dec_tlu_ctl.scala 2271:34] + wire _T_1645 = mhpme5 == 10'h10; // @[dec_tlu_ctl.scala 2272:34] + wire _T_1648 = mhpme5 == 10'h12; // @[dec_tlu_ctl.scala 2273:34] + wire _T_1651 = mhpme5 == 10'h11; // @[dec_tlu_ctl.scala 2274:34] + wire _T_1654 = mhpme5 == 10'h13; // @[dec_tlu_ctl.scala 2275:34] + wire _T_1657 = mhpme5 == 10'h14; // @[dec_tlu_ctl.scala 2276:34] + wire _T_1660 = mhpme5 == 10'h15; // @[dec_tlu_ctl.scala 2277:34] + wire _T_1663 = mhpme5 == 10'h16; // @[dec_tlu_ctl.scala 2278:34] + wire _T_1666 = mhpme5 == 10'h17; // @[dec_tlu_ctl.scala 2279:34] + wire _T_1669 = mhpme5 == 10'h18; // @[dec_tlu_ctl.scala 2280:34] + wire _T_1674 = mhpme5 == 10'h19; // @[dec_tlu_ctl.scala 2281:34] + wire _T_1677 = mhpme5 == 10'h1a; // @[dec_tlu_ctl.scala 2282:34] + wire _T_1680 = mhpme5 == 10'h1b; // @[dec_tlu_ctl.scala 2283:34] + wire _T_1683 = mhpme5 == 10'h1c; // @[dec_tlu_ctl.scala 2284:34] + wire _T_1687 = mhpme5 == 10'h1f; // @[dec_tlu_ctl.scala 2286:34] + wire _T_1689 = mhpme5 == 10'h20; // @[dec_tlu_ctl.scala 2287:34] + wire _T_1691 = mhpme5 == 10'h22; // @[dec_tlu_ctl.scala 2288:34] + wire _T_1693 = mhpme5 == 10'h23; // @[dec_tlu_ctl.scala 2289:34] + wire _T_1695 = mhpme5 == 10'h24; // @[dec_tlu_ctl.scala 2290:34] + wire _T_1697 = mhpme5 == 10'h25; // @[dec_tlu_ctl.scala 2291:34] + wire _T_1701 = mhpme5 == 10'h26; // @[dec_tlu_ctl.scala 2292:34] + wire _T_1705 = mhpme5 == 10'h27; // @[dec_tlu_ctl.scala 2293:34] + wire _T_1707 = mhpme5 == 10'h28; // @[dec_tlu_ctl.scala 2294:34] + wire _T_1709 = mhpme5 == 10'h29; // @[dec_tlu_ctl.scala 2295:34] + wire _T_1713 = mhpme5 == 10'h2a; // @[dec_tlu_ctl.scala 2296:34] + wire _T_1715 = mhpme5 == 10'h2b; // @[dec_tlu_ctl.scala 2297:34] + wire _T_1717 = mhpme5 == 10'h2c; // @[dec_tlu_ctl.scala 2298:34] + wire _T_1719 = mhpme5 == 10'h2d; // @[dec_tlu_ctl.scala 2299:34] + wire _T_1721 = mhpme5 == 10'h2e; // @[dec_tlu_ctl.scala 2300:34] + wire _T_1723 = mhpme5 == 10'h2f; // @[dec_tlu_ctl.scala 2301:34] + wire _T_1725 = mhpme5 == 10'h30; // @[dec_tlu_ctl.scala 2302:34] + wire _T_1727 = mhpme5 == 10'h31; // @[dec_tlu_ctl.scala 2303:34] + wire _T_1732 = mhpme5 == 10'h32; // @[dec_tlu_ctl.scala 2304:34] + wire _T_1742 = mhpme5 == 10'h36; // @[dec_tlu_ctl.scala 2305:34] + wire _T_1745 = mhpme5 == 10'h37; // @[dec_tlu_ctl.scala 2306:34] + wire _T_1748 = mhpme5 == 10'h38; // @[dec_tlu_ctl.scala 2307:34] + wire _T_1751 = mhpme5 == 10'h200; // @[dec_tlu_ctl.scala 2309:34] + wire _T_1753 = mhpme5 == 10'h201; // @[dec_tlu_ctl.scala 2310:34] + wire _T_1755 = mhpme5 == 10'h202; // @[dec_tlu_ctl.scala 2311:34] + wire _T_1757 = mhpme5 == 10'h203; // @[dec_tlu_ctl.scala 2312:34] + wire _T_1759 = mhpme5 == 10'h204; // @[dec_tlu_ctl.scala 2313:34] + wire _T_1762 = _T_1596 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_1763 = _T_1598 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_1764 = _T_1600 & _T_1035; // @[Mux.scala 27:72] + wire _T_1765 = _T_1604 & _T_1041; // @[Mux.scala 27:72] + wire _T_1766 = _T_1610 & _T_1046; // @[Mux.scala 27:72] + wire _T_1767 = _T_1615 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_1768 = _T_1617 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_1769 = _T_1619 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_1770 = _T_1621 & _T_1055; // @[Mux.scala 27:72] + wire _T_1771 = _T_1624 & _T_1058; // @[Mux.scala 27:72] + wire _T_1772 = _T_1627 & _T_1061; // @[Mux.scala 27:72] + wire _T_1773 = _T_1630 & _T_1064; // @[Mux.scala 27:72] + wire _T_1774 = _T_1633 & _T_1068; // @[Mux.scala 27:72] + wire _T_1775 = _T_1637 & _T_1073; // @[Mux.scala 27:72] + wire _T_1776 = _T_1642 & _T_1076; // @[Mux.scala 27:72] + wire _T_1777 = _T_1645 & _T_1079; // @[Mux.scala 27:72] + wire _T_1778 = _T_1648 & _T_1082; // @[Mux.scala 27:72] + wire _T_1779 = _T_1651 & _T_1085; // @[Mux.scala 27:72] + wire _T_1780 = _T_1654 & _T_1088; // @[Mux.scala 27:72] + wire _T_1781 = _T_1657 & _T_1091; // @[Mux.scala 27:72] + wire _T_1782 = _T_1660 & _T_1094; // @[Mux.scala 27:72] + wire _T_1783 = _T_1663 & _T_1097; // @[Mux.scala 27:72] + wire _T_1784 = _T_1666 & _T_1100; // @[Mux.scala 27:72] + wire _T_1785 = _T_1669 & _T_1105; // @[Mux.scala 27:72] + wire _T_1786 = _T_1674 & _T_1108; // @[Mux.scala 27:72] + wire _T_1787 = _T_1677 & _T_1111; // @[Mux.scala 27:72] + wire _T_1788 = _T_1680 & _T_1114; // @[Mux.scala 27:72] + wire _T_1789 = _T_1683 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_1791 = _T_1687 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_1792 = _T_1689 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_1793 = _T_1691 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_1794 = _T_1693 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_1795 = _T_1695 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_1796 = _T_1697 & _T_1132; // @[Mux.scala 27:72] + wire _T_1797 = _T_1701 & _T_1136; // @[Mux.scala 27:72] + wire _T_1798 = _T_1705 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_1799 = _T_1707 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_1800 = _T_1709 & _T_1144; // @[Mux.scala 27:72] + wire _T_1801 = _T_1713 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1802 = _T_1715 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1803 = _T_1717 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_1804 = _T_1719 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1805 = _T_1721 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1806 = _T_1723 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1807 = _T_1725 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1808 = _T_1727 & _T_1163; // @[Mux.scala 27:72] + wire _T_1809 = _T_1732 & _T_1173; // @[Mux.scala 27:72] + wire _T_1810 = _T_1742 & _T_1176; // @[Mux.scala 27:72] + wire _T_1811 = _T_1745 & _T_1179; // @[Mux.scala 27:72] + wire _T_1812 = _T_1748 & _T_1182; // @[Mux.scala 27:72] + wire _T_1813 = _T_1751 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_1814 = _T_1753 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_1815 = _T_1755 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_1816 = _T_1757 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_1817 = _T_1759 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_1818 = _T_1594 | _T_1762; // @[Mux.scala 27:72] wire _T_1819 = _T_1818 | _T_1763; // @[Mux.scala 27:72] wire _T_1820 = _T_1819 | _T_1764; // @[Mux.scala 27:72] wire _T_1821 = _T_1820 | _T_1765; // @[Mux.scala 27:72] @@ -51955,7 +51956,7 @@ module csr_tlu( wire _T_1833 = _T_1832 | _T_1777; // @[Mux.scala 27:72] wire _T_1834 = _T_1833 | _T_1778; // @[Mux.scala 27:72] wire _T_1835 = _T_1834 | _T_1779; // @[Mux.scala 27:72] - wire _T_1836 = _T_1835 | _T_1759; // @[Mux.scala 27:72] + wire _T_1836 = _T_1835 | _T_1780; // @[Mux.scala 27:72] wire _T_1837 = _T_1836 | _T_1781; // @[Mux.scala 27:72] wire _T_1838 = _T_1837 | _T_1782; // @[Mux.scala 27:72] wire _T_1839 = _T_1838 | _T_1783; // @[Mux.scala 27:72] @@ -51965,7 +51966,7 @@ module csr_tlu( wire _T_1843 = _T_1842 | _T_1787; // @[Mux.scala 27:72] wire _T_1844 = _T_1843 | _T_1788; // @[Mux.scala 27:72] wire _T_1845 = _T_1844 | _T_1789; // @[Mux.scala 27:72] - wire _T_1846 = _T_1845 | _T_1790; // @[Mux.scala 27:72] + wire _T_1846 = _T_1845 | _T_1769; // @[Mux.scala 27:72] wire _T_1847 = _T_1846 | _T_1791; // @[Mux.scala 27:72] wire _T_1848 = _T_1847 | _T_1792; // @[Mux.scala 27:72] wire _T_1849 = _T_1848 | _T_1793; // @[Mux.scala 27:72] @@ -51983,131 +51984,131 @@ module csr_tlu( wire _T_1861 = _T_1860 | _T_1805; // @[Mux.scala 27:72] wire _T_1862 = _T_1861 | _T_1806; // @[Mux.scala 27:72] wire _T_1863 = _T_1862 | _T_1807; // @[Mux.scala 27:72] - wire mhpmc_inc_r_2 = _T_1583 & _T_1863; // @[dec_tlu_ctl.scala 2255:44] - wire _T_1867 = ~mcountinhibit[6]; // @[dec_tlu_ctl.scala 2255:24] + wire _T_1864 = _T_1863 | _T_1808; // @[Mux.scala 27:72] + wire _T_1865 = _T_1864 | _T_1809; // @[Mux.scala 27:72] + wire _T_1866 = _T_1865 | _T_1810; // @[Mux.scala 27:72] + wire _T_1867 = _T_1866 | _T_1811; // @[Mux.scala 27:72] + wire _T_1868 = _T_1867 | _T_1812; // @[Mux.scala 27:72] + wire _T_1869 = _T_1868 | _T_1813; // @[Mux.scala 27:72] + wire _T_1870 = _T_1869 | _T_1814; // @[Mux.scala 27:72] + wire _T_1871 = _T_1870 | _T_1815; // @[Mux.scala 27:72] + wire _T_1872 = _T_1871 | _T_1816; // @[Mux.scala 27:72] + wire _T_1873 = _T_1872 | _T_1817; // @[Mux.scala 27:72] + wire mhpmc_inc_r_2 = _T_1593 & _T_1873; // @[dec_tlu_ctl.scala 2255:44] + wire _T_1877 = ~mcountinhibit[6]; // @[dec_tlu_ctl.scala 2255:24] reg [9:0] mhpme6; // @[Reg.scala 27:20] - wire _T_1868 = mhpme6 == 10'h1; // @[dec_tlu_ctl.scala 2256:34] - wire _T_1870 = mhpme6 == 10'h2; // @[dec_tlu_ctl.scala 2257:34] - wire _T_1872 = mhpme6 == 10'h3; // @[dec_tlu_ctl.scala 2258:34] - wire _T_1874 = mhpme6 == 10'h4; // @[dec_tlu_ctl.scala 2259:34] - wire _T_1878 = mhpme6 == 10'h5; // @[dec_tlu_ctl.scala 2260:34] - wire _T_1884 = mhpme6 == 10'h6; // @[dec_tlu_ctl.scala 2261:34] - wire _T_1889 = mhpme6 == 10'h7; // @[dec_tlu_ctl.scala 2262:34] - wire _T_1891 = mhpme6 == 10'h8; // @[dec_tlu_ctl.scala 2263:34] - wire _T_1893 = mhpme6 == 10'h1e; // @[dec_tlu_ctl.scala 2264:34] - wire _T_1895 = mhpme6 == 10'h9; // @[dec_tlu_ctl.scala 2265:34] - wire _T_1898 = mhpme6 == 10'ha; // @[dec_tlu_ctl.scala 2266:34] - wire _T_1901 = mhpme6 == 10'hb; // @[dec_tlu_ctl.scala 2267:34] - wire _T_1904 = mhpme6 == 10'hc; // @[dec_tlu_ctl.scala 2268:34] - wire _T_1907 = mhpme6 == 10'hd; // @[dec_tlu_ctl.scala 2269:34] - wire _T_1911 = mhpme6 == 10'he; // @[dec_tlu_ctl.scala 2270:34] - wire _T_1916 = mhpme6 == 10'hf; // @[dec_tlu_ctl.scala 2271:34] - wire _T_1919 = mhpme6 == 10'h10; // @[dec_tlu_ctl.scala 2272:34] - wire _T_1922 = mhpme6 == 10'h12; // @[dec_tlu_ctl.scala 2273:34] - wire _T_1925 = mhpme6 == 10'h11; // @[dec_tlu_ctl.scala 2274:34] - wire _T_1928 = mhpme6 == 10'h13; // @[dec_tlu_ctl.scala 2275:34] - wire _T_1931 = mhpme6 == 10'h14; // @[dec_tlu_ctl.scala 2276:34] - wire _T_1934 = mhpme6 == 10'h15; // @[dec_tlu_ctl.scala 2277:34] - wire _T_1937 = mhpme6 == 10'h16; // @[dec_tlu_ctl.scala 2278:34] - wire _T_1940 = mhpme6 == 10'h17; // @[dec_tlu_ctl.scala 2279:34] - wire _T_1943 = mhpme6 == 10'h18; // @[dec_tlu_ctl.scala 2280:34] - wire _T_1948 = mhpme6 == 10'h19; // @[dec_tlu_ctl.scala 2281:34] - wire _T_1951 = mhpme6 == 10'h1a; // @[dec_tlu_ctl.scala 2282:34] - wire _T_1954 = mhpme6 == 10'h1b; // @[dec_tlu_ctl.scala 2283:34] - wire _T_1957 = mhpme6 == 10'h1c; // @[dec_tlu_ctl.scala 2284:34] - wire _T_1961 = mhpme6 == 10'h1f; // @[dec_tlu_ctl.scala 2286:34] - wire _T_1963 = mhpme6 == 10'h20; // @[dec_tlu_ctl.scala 2287:34] - wire _T_1965 = mhpme6 == 10'h22; // @[dec_tlu_ctl.scala 2288:34] - wire _T_1967 = mhpme6 == 10'h23; // @[dec_tlu_ctl.scala 2289:34] - wire _T_1969 = mhpme6 == 10'h24; // @[dec_tlu_ctl.scala 2290:34] - wire _T_1971 = mhpme6 == 10'h25; // @[dec_tlu_ctl.scala 2291:34] - wire _T_1975 = mhpme6 == 10'h26; // @[dec_tlu_ctl.scala 2292:34] - wire _T_1979 = mhpme6 == 10'h27; // @[dec_tlu_ctl.scala 2293:34] - wire _T_1981 = mhpme6 == 10'h28; // @[dec_tlu_ctl.scala 2294:34] - wire _T_1983 = mhpme6 == 10'h29; // @[dec_tlu_ctl.scala 2295:34] - wire _T_1987 = mhpme6 == 10'h2a; // @[dec_tlu_ctl.scala 2296:34] - wire _T_1989 = mhpme6 == 10'h2b; // @[dec_tlu_ctl.scala 2297:34] - wire _T_1991 = mhpme6 == 10'h2c; // @[dec_tlu_ctl.scala 2298:34] - wire _T_1993 = mhpme6 == 10'h2d; // @[dec_tlu_ctl.scala 2299:34] - wire _T_1995 = mhpme6 == 10'h2e; // @[dec_tlu_ctl.scala 2300:34] - wire _T_1997 = mhpme6 == 10'h2f; // @[dec_tlu_ctl.scala 2301:34] - wire _T_1999 = mhpme6 == 10'h30; // @[dec_tlu_ctl.scala 2302:34] - wire _T_2001 = mhpme6 == 10'h31; // @[dec_tlu_ctl.scala 2303:34] - wire _T_2006 = mhpme6 == 10'h32; // @[dec_tlu_ctl.scala 2304:34] - wire _T_2016 = mhpme6 == 10'h36; // @[dec_tlu_ctl.scala 2305:34] - wire _T_2019 = mhpme6 == 10'h37; // @[dec_tlu_ctl.scala 2306:34] - wire _T_2022 = mhpme6 == 10'h38; // @[dec_tlu_ctl.scala 2307:34] - wire _T_2025 = mhpme6 == 10'h200; // @[dec_tlu_ctl.scala 2309:34] - wire _T_2027 = mhpme6 == 10'h201; // @[dec_tlu_ctl.scala 2310:34] - wire _T_2029 = mhpme6 == 10'h202; // @[dec_tlu_ctl.scala 2311:34] - wire _T_2031 = mhpme6 == 10'h203; // @[dec_tlu_ctl.scala 2312:34] - wire _T_2033 = mhpme6 == 10'h204; // @[dec_tlu_ctl.scala 2313:34] - wire _T_2036 = _T_1870 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] - wire _T_2037 = _T_1872 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] - wire _T_2038 = _T_1874 & _T_1025; // @[Mux.scala 27:72] - wire _T_2039 = _T_1878 & _T_1031; // @[Mux.scala 27:72] - wire _T_2040 = _T_1884 & _T_1036; // @[Mux.scala 27:72] - wire _T_2041 = _T_1889 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] - wire _T_2042 = _T_1891 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] - wire _T_2043 = _T_1893 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] - wire _T_2044 = _T_1895 & _T_1045; // @[Mux.scala 27:72] - wire _T_2045 = _T_1898 & _T_1048; // @[Mux.scala 27:72] - wire _T_2046 = _T_1901 & _T_1051; // @[Mux.scala 27:72] - wire _T_2047 = _T_1904 & _T_1054; // @[Mux.scala 27:72] - wire _T_2048 = _T_1907 & _T_1058; // @[Mux.scala 27:72] - wire _T_2049 = _T_1911 & _T_1063; // @[Mux.scala 27:72] - wire _T_2050 = _T_1916 & _T_1066; // @[Mux.scala 27:72] - wire _T_2051 = _T_1919 & _T_1069; // @[Mux.scala 27:72] - wire _T_2052 = _T_1922 & _T_1072; // @[Mux.scala 27:72] - wire _T_2053 = _T_1925 & _T_1075; // @[Mux.scala 27:72] - wire _T_2054 = _T_1928 & _T_1078; // @[Mux.scala 27:72] - wire _T_2055 = _T_1931 & _T_1081; // @[Mux.scala 27:72] - wire _T_2056 = _T_1934 & _T_1084; // @[Mux.scala 27:72] - wire _T_2057 = _T_1937 & _T_1087; // @[Mux.scala 27:72] - wire _T_2058 = _T_1940 & _T_1090; // @[Mux.scala 27:72] - wire _T_2059 = _T_1943 & _T_1095; // @[Mux.scala 27:72] - wire _T_2060 = _T_1948 & _T_1098; // @[Mux.scala 27:72] - wire _T_2061 = _T_1951 & _T_1101; // @[Mux.scala 27:72] - wire _T_2062 = _T_1954 & _T_1104; // @[Mux.scala 27:72] - wire _T_2063 = _T_1957 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] - wire _T_2065 = _T_1961 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] - wire _T_2066 = _T_1963 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] - wire _T_2067 = _T_1965 & io_lsu_store_stall_any; // @[Mux.scala 27:72] - wire _T_2068 = _T_1967 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] - wire _T_2069 = _T_1969 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] - wire _T_2070 = _T_1971 & _T_1122; // @[Mux.scala 27:72] - wire _T_2071 = _T_1975 & _T_1126; // @[Mux.scala 27:72] - wire _T_2072 = _T_1979 & io_take_ext_int; // @[Mux.scala 27:72] - wire _T_2073 = _T_1981 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] - wire _T_2074 = _T_1983 & _T_1134; // @[Mux.scala 27:72] - wire _T_2075 = _T_1987 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_2076 = _T_1989 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_2077 = _T_1991 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] - wire _T_2078 = _T_1993 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_2079 = _T_1995 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_2080 = _T_1997 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_2081 = _T_1999 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_2082 = _T_2001 & _T_1153; // @[Mux.scala 27:72] - wire _T_2083 = _T_2006 & _T_1163; // @[Mux.scala 27:72] - wire _T_2084 = _T_2016 & _T_1166; // @[Mux.scala 27:72] - wire _T_2085 = _T_2019 & _T_1169; // @[Mux.scala 27:72] - wire _T_2086 = _T_2022 & _T_1172; // @[Mux.scala 27:72] - wire _T_2087 = _T_2025 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] - wire _T_2088 = _T_2027 & io_dma_pmu_any_read; // @[Mux.scala 27:72] - wire _T_2089 = _T_2029 & io_dma_pmu_any_write; // @[Mux.scala 27:72] - wire _T_2090 = _T_2031 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] - wire _T_2091 = _T_2033 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] - wire _T_2092 = _T_1868 | _T_2036; // @[Mux.scala 27:72] - wire _T_2093 = _T_2092 | _T_2037; // @[Mux.scala 27:72] - wire _T_2094 = _T_2093 | _T_2038; // @[Mux.scala 27:72] - wire _T_2095 = _T_2094 | _T_2039; // @[Mux.scala 27:72] - wire _T_2096 = _T_2095 | _T_2040; // @[Mux.scala 27:72] - wire _T_2097 = _T_2096 | _T_2041; // @[Mux.scala 27:72] - wire _T_2098 = _T_2097 | _T_2042; // @[Mux.scala 27:72] - wire _T_2099 = _T_2098 | _T_2043; // @[Mux.scala 27:72] - wire _T_2100 = _T_2099 | _T_2044; // @[Mux.scala 27:72] - wire _T_2101 = _T_2100 | _T_2045; // @[Mux.scala 27:72] - wire _T_2102 = _T_2101 | _T_2046; // @[Mux.scala 27:72] + wire _T_1878 = mhpme6 == 10'h1; // @[dec_tlu_ctl.scala 2256:34] + wire _T_1880 = mhpme6 == 10'h2; // @[dec_tlu_ctl.scala 2257:34] + wire _T_1882 = mhpme6 == 10'h3; // @[dec_tlu_ctl.scala 2258:34] + wire _T_1884 = mhpme6 == 10'h4; // @[dec_tlu_ctl.scala 2259:34] + wire _T_1888 = mhpme6 == 10'h5; // @[dec_tlu_ctl.scala 2260:34] + wire _T_1894 = mhpme6 == 10'h6; // @[dec_tlu_ctl.scala 2261:34] + wire _T_1899 = mhpme6 == 10'h7; // @[dec_tlu_ctl.scala 2262:34] + wire _T_1901 = mhpme6 == 10'h8; // @[dec_tlu_ctl.scala 2263:34] + wire _T_1903 = mhpme6 == 10'h1e; // @[dec_tlu_ctl.scala 2264:34] + wire _T_1905 = mhpme6 == 10'h9; // @[dec_tlu_ctl.scala 2265:34] + wire _T_1908 = mhpme6 == 10'ha; // @[dec_tlu_ctl.scala 2266:34] + wire _T_1911 = mhpme6 == 10'hb; // @[dec_tlu_ctl.scala 2267:34] + wire _T_1914 = mhpme6 == 10'hc; // @[dec_tlu_ctl.scala 2268:34] + wire _T_1917 = mhpme6 == 10'hd; // @[dec_tlu_ctl.scala 2269:34] + wire _T_1921 = mhpme6 == 10'he; // @[dec_tlu_ctl.scala 2270:34] + wire _T_1926 = mhpme6 == 10'hf; // @[dec_tlu_ctl.scala 2271:34] + wire _T_1929 = mhpme6 == 10'h10; // @[dec_tlu_ctl.scala 2272:34] + wire _T_1932 = mhpme6 == 10'h12; // @[dec_tlu_ctl.scala 2273:34] + wire _T_1935 = mhpme6 == 10'h11; // @[dec_tlu_ctl.scala 2274:34] + wire _T_1938 = mhpme6 == 10'h13; // @[dec_tlu_ctl.scala 2275:34] + wire _T_1941 = mhpme6 == 10'h14; // @[dec_tlu_ctl.scala 2276:34] + wire _T_1944 = mhpme6 == 10'h15; // @[dec_tlu_ctl.scala 2277:34] + wire _T_1947 = mhpme6 == 10'h16; // @[dec_tlu_ctl.scala 2278:34] + wire _T_1950 = mhpme6 == 10'h17; // @[dec_tlu_ctl.scala 2279:34] + wire _T_1953 = mhpme6 == 10'h18; // @[dec_tlu_ctl.scala 2280:34] + wire _T_1958 = mhpme6 == 10'h19; // @[dec_tlu_ctl.scala 2281:34] + wire _T_1961 = mhpme6 == 10'h1a; // @[dec_tlu_ctl.scala 2282:34] + wire _T_1964 = mhpme6 == 10'h1b; // @[dec_tlu_ctl.scala 2283:34] + wire _T_1967 = mhpme6 == 10'h1c; // @[dec_tlu_ctl.scala 2284:34] + wire _T_1971 = mhpme6 == 10'h1f; // @[dec_tlu_ctl.scala 2286:34] + wire _T_1973 = mhpme6 == 10'h20; // @[dec_tlu_ctl.scala 2287:34] + wire _T_1975 = mhpme6 == 10'h22; // @[dec_tlu_ctl.scala 2288:34] + wire _T_1977 = mhpme6 == 10'h23; // @[dec_tlu_ctl.scala 2289:34] + wire _T_1979 = mhpme6 == 10'h24; // @[dec_tlu_ctl.scala 2290:34] + wire _T_1981 = mhpme6 == 10'h25; // @[dec_tlu_ctl.scala 2291:34] + wire _T_1985 = mhpme6 == 10'h26; // @[dec_tlu_ctl.scala 2292:34] + wire _T_1989 = mhpme6 == 10'h27; // @[dec_tlu_ctl.scala 2293:34] + wire _T_1991 = mhpme6 == 10'h28; // @[dec_tlu_ctl.scala 2294:34] + wire _T_1993 = mhpme6 == 10'h29; // @[dec_tlu_ctl.scala 2295:34] + wire _T_1997 = mhpme6 == 10'h2a; // @[dec_tlu_ctl.scala 2296:34] + wire _T_1999 = mhpme6 == 10'h2b; // @[dec_tlu_ctl.scala 2297:34] + wire _T_2001 = mhpme6 == 10'h2c; // @[dec_tlu_ctl.scala 2298:34] + wire _T_2003 = mhpme6 == 10'h2d; // @[dec_tlu_ctl.scala 2299:34] + wire _T_2005 = mhpme6 == 10'h2e; // @[dec_tlu_ctl.scala 2300:34] + wire _T_2007 = mhpme6 == 10'h2f; // @[dec_tlu_ctl.scala 2301:34] + wire _T_2009 = mhpme6 == 10'h30; // @[dec_tlu_ctl.scala 2302:34] + wire _T_2011 = mhpme6 == 10'h31; // @[dec_tlu_ctl.scala 2303:34] + wire _T_2016 = mhpme6 == 10'h32; // @[dec_tlu_ctl.scala 2304:34] + wire _T_2026 = mhpme6 == 10'h36; // @[dec_tlu_ctl.scala 2305:34] + wire _T_2029 = mhpme6 == 10'h37; // @[dec_tlu_ctl.scala 2306:34] + wire _T_2032 = mhpme6 == 10'h38; // @[dec_tlu_ctl.scala 2307:34] + wire _T_2035 = mhpme6 == 10'h200; // @[dec_tlu_ctl.scala 2309:34] + wire _T_2037 = mhpme6 == 10'h201; // @[dec_tlu_ctl.scala 2310:34] + wire _T_2039 = mhpme6 == 10'h202; // @[dec_tlu_ctl.scala 2311:34] + wire _T_2041 = mhpme6 == 10'h203; // @[dec_tlu_ctl.scala 2312:34] + wire _T_2043 = mhpme6 == 10'h204; // @[dec_tlu_ctl.scala 2313:34] + wire _T_2046 = _T_1880 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_2047 = _T_1882 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_2048 = _T_1884 & _T_1035; // @[Mux.scala 27:72] + wire _T_2049 = _T_1888 & _T_1041; // @[Mux.scala 27:72] + wire _T_2050 = _T_1894 & _T_1046; // @[Mux.scala 27:72] + wire _T_2051 = _T_1899 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_2052 = _T_1901 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_2053 = _T_1903 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_2054 = _T_1905 & _T_1055; // @[Mux.scala 27:72] + wire _T_2055 = _T_1908 & _T_1058; // @[Mux.scala 27:72] + wire _T_2056 = _T_1911 & _T_1061; // @[Mux.scala 27:72] + wire _T_2057 = _T_1914 & _T_1064; // @[Mux.scala 27:72] + wire _T_2058 = _T_1917 & _T_1068; // @[Mux.scala 27:72] + wire _T_2059 = _T_1921 & _T_1073; // @[Mux.scala 27:72] + wire _T_2060 = _T_1926 & _T_1076; // @[Mux.scala 27:72] + wire _T_2061 = _T_1929 & _T_1079; // @[Mux.scala 27:72] + wire _T_2062 = _T_1932 & _T_1082; // @[Mux.scala 27:72] + wire _T_2063 = _T_1935 & _T_1085; // @[Mux.scala 27:72] + wire _T_2064 = _T_1938 & _T_1088; // @[Mux.scala 27:72] + wire _T_2065 = _T_1941 & _T_1091; // @[Mux.scala 27:72] + wire _T_2066 = _T_1944 & _T_1094; // @[Mux.scala 27:72] + wire _T_2067 = _T_1947 & _T_1097; // @[Mux.scala 27:72] + wire _T_2068 = _T_1950 & _T_1100; // @[Mux.scala 27:72] + wire _T_2069 = _T_1953 & _T_1105; // @[Mux.scala 27:72] + wire _T_2070 = _T_1958 & _T_1108; // @[Mux.scala 27:72] + wire _T_2071 = _T_1961 & _T_1111; // @[Mux.scala 27:72] + wire _T_2072 = _T_1964 & _T_1114; // @[Mux.scala 27:72] + wire _T_2073 = _T_1967 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_2075 = _T_1971 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_2076 = _T_1973 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_2077 = _T_1975 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_2078 = _T_1977 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_2079 = _T_1979 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_2080 = _T_1981 & _T_1132; // @[Mux.scala 27:72] + wire _T_2081 = _T_1985 & _T_1136; // @[Mux.scala 27:72] + wire _T_2082 = _T_1989 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_2083 = _T_1991 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_2084 = _T_1993 & _T_1144; // @[Mux.scala 27:72] + wire _T_2085 = _T_1997 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_2086 = _T_1999 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_2087 = _T_2001 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_2088 = _T_2003 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_2089 = _T_2005 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_2090 = _T_2007 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_2091 = _T_2009 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_2092 = _T_2011 & _T_1163; // @[Mux.scala 27:72] + wire _T_2093 = _T_2016 & _T_1173; // @[Mux.scala 27:72] + wire _T_2094 = _T_2026 & _T_1176; // @[Mux.scala 27:72] + wire _T_2095 = _T_2029 & _T_1179; // @[Mux.scala 27:72] + wire _T_2096 = _T_2032 & _T_1182; // @[Mux.scala 27:72] + wire _T_2097 = _T_2035 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_2098 = _T_2037 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_2099 = _T_2039 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_2100 = _T_2041 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_2101 = _T_2043 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_2102 = _T_1878 | _T_2046; // @[Mux.scala 27:72] wire _T_2103 = _T_2102 | _T_2047; // @[Mux.scala 27:72] wire _T_2104 = _T_2103 | _T_2048; // @[Mux.scala 27:72] wire _T_2105 = _T_2104 | _T_2049; // @[Mux.scala 27:72] @@ -52125,7 +52126,7 @@ module csr_tlu( wire _T_2117 = _T_2116 | _T_2061; // @[Mux.scala 27:72] wire _T_2118 = _T_2117 | _T_2062; // @[Mux.scala 27:72] wire _T_2119 = _T_2118 | _T_2063; // @[Mux.scala 27:72] - wire _T_2120 = _T_2119 | _T_2043; // @[Mux.scala 27:72] + wire _T_2120 = _T_2119 | _T_2064; // @[Mux.scala 27:72] wire _T_2121 = _T_2120 | _T_2065; // @[Mux.scala 27:72] wire _T_2122 = _T_2121 | _T_2066; // @[Mux.scala 27:72] wire _T_2123 = _T_2122 | _T_2067; // @[Mux.scala 27:72] @@ -52135,7 +52136,7 @@ module csr_tlu( wire _T_2127 = _T_2126 | _T_2071; // @[Mux.scala 27:72] wire _T_2128 = _T_2127 | _T_2072; // @[Mux.scala 27:72] wire _T_2129 = _T_2128 | _T_2073; // @[Mux.scala 27:72] - wire _T_2130 = _T_2129 | _T_2074; // @[Mux.scala 27:72] + wire _T_2130 = _T_2129 | _T_2053; // @[Mux.scala 27:72] wire _T_2131 = _T_2130 | _T_2075; // @[Mux.scala 27:72] wire _T_2132 = _T_2131 | _T_2076; // @[Mux.scala 27:72] wire _T_2133 = _T_2132 | _T_2077; // @[Mux.scala 27:72] @@ -52153,196 +52154,196 @@ module csr_tlu( wire _T_2145 = _T_2144 | _T_2089; // @[Mux.scala 27:72] wire _T_2146 = _T_2145 | _T_2090; // @[Mux.scala 27:72] wire _T_2147 = _T_2146 | _T_2091; // @[Mux.scala 27:72] - wire mhpmc_inc_r_3 = _T_1867 & _T_2147; // @[dec_tlu_ctl.scala 2255:44] + wire _T_2148 = _T_2147 | _T_2092; // @[Mux.scala 27:72] + wire _T_2149 = _T_2148 | _T_2093; // @[Mux.scala 27:72] + wire _T_2150 = _T_2149 | _T_2094; // @[Mux.scala 27:72] + wire _T_2151 = _T_2150 | _T_2095; // @[Mux.scala 27:72] + wire _T_2152 = _T_2151 | _T_2096; // @[Mux.scala 27:72] + wire _T_2153 = _T_2152 | _T_2097; // @[Mux.scala 27:72] + wire _T_2154 = _T_2153 | _T_2098; // @[Mux.scala 27:72] + wire _T_2155 = _T_2154 | _T_2099; // @[Mux.scala 27:72] + wire _T_2156 = _T_2155 | _T_2100; // @[Mux.scala 27:72] + wire _T_2157 = _T_2156 | _T_2101; // @[Mux.scala 27:72] + wire mhpmc_inc_r_3 = _T_1877 & _T_2157; // @[dec_tlu_ctl.scala 2255:44] reg mhpmc_inc_r_d1_0; // @[dec_tlu_ctl.scala 2316:53] reg mhpmc_inc_r_d1_1; // @[dec_tlu_ctl.scala 2317:53] reg mhpmc_inc_r_d1_2; // @[dec_tlu_ctl.scala 2318:53] reg mhpmc_inc_r_d1_3; // @[dec_tlu_ctl.scala 2319:53] reg perfcnt_halted_d1; // @[dec_tlu_ctl.scala 2320:56] wire perfcnt_halted = _T_85 | io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 2323:67] - wire _T_2159 = ~_T_85; // @[dec_tlu_ctl.scala 2324:37] - wire [3:0] _T_2161 = _T_2159 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] _T_2168 = {mhpme6[9],mhpme5[9],mhpme4[9],mhpme3[9]}; // @[Cat.scala 29:58] - wire [3:0] perfcnt_during_sleep = _T_2161 & _T_2168; // @[dec_tlu_ctl.scala 2324:86] - wire _T_2170 = ~perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2326:67] - wire _T_2171 = perfcnt_halted_d1 & _T_2170; // @[dec_tlu_ctl.scala 2326:65] - wire _T_2172 = ~_T_2171; // @[dec_tlu_ctl.scala 2326:45] - wire _T_2175 = ~perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2327:67] - wire _T_2176 = perfcnt_halted_d1 & _T_2175; // @[dec_tlu_ctl.scala 2327:65] - wire _T_2177 = ~_T_2176; // @[dec_tlu_ctl.scala 2327:45] - wire _T_2180 = ~perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2328:67] - wire _T_2181 = perfcnt_halted_d1 & _T_2180; // @[dec_tlu_ctl.scala 2328:65] - wire _T_2182 = ~_T_2181; // @[dec_tlu_ctl.scala 2328:45] - wire _T_2185 = ~perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2329:67] - wire _T_2186 = perfcnt_halted_d1 & _T_2185; // @[dec_tlu_ctl.scala 2329:65] - wire _T_2187 = ~_T_2186; // @[dec_tlu_ctl.scala 2329:45] - wire _T_2190 = io_dec_csr_wraddr_r == 12'hb03; // @[dec_tlu_ctl.scala 2335:72] - wire mhpmc3_wr_en0 = io_dec_csr_wen_r_mod & _T_2190; // @[dec_tlu_ctl.scala 2335:43] - wire _T_2191 = ~perfcnt_halted; // @[dec_tlu_ctl.scala 2336:23] - wire _T_2193 = _T_2191 | perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2336:39] - wire _T_2194 = |mhpmc_inc_r_0; // @[dec_tlu_ctl.scala 2336:86] - wire mhpmc3_wr_en1 = _T_2193 & _T_2194; // @[dec_tlu_ctl.scala 2336:66] + wire _T_2169 = ~_T_85; // @[dec_tlu_ctl.scala 2324:37] + wire [3:0] _T_2171 = _T_2169 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_2178 = {mhpme6[9],mhpme5[9],mhpme4[9],mhpme3[9]}; // @[Cat.scala 29:58] + wire [3:0] perfcnt_during_sleep = _T_2171 & _T_2178; // @[dec_tlu_ctl.scala 2324:86] + wire _T_2180 = ~perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2326:67] + wire _T_2181 = perfcnt_halted_d1 & _T_2180; // @[dec_tlu_ctl.scala 2326:65] + wire _T_2182 = ~_T_2181; // @[dec_tlu_ctl.scala 2326:45] + wire _T_2185 = ~perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2327:67] + wire _T_2186 = perfcnt_halted_d1 & _T_2185; // @[dec_tlu_ctl.scala 2327:65] + wire _T_2187 = ~_T_2186; // @[dec_tlu_ctl.scala 2327:45] + wire _T_2190 = ~perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2328:67] + wire _T_2191 = perfcnt_halted_d1 & _T_2190; // @[dec_tlu_ctl.scala 2328:65] + wire _T_2192 = ~_T_2191; // @[dec_tlu_ctl.scala 2328:45] + wire _T_2195 = ~perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2329:67] + wire _T_2196 = perfcnt_halted_d1 & _T_2195; // @[dec_tlu_ctl.scala 2329:65] + wire _T_2197 = ~_T_2196; // @[dec_tlu_ctl.scala 2329:45] + wire _T_2200 = io_dec_csr_wraddr_r == 12'hb03; // @[dec_tlu_ctl.scala 2335:72] + wire mhpmc3_wr_en0 = io_dec_csr_wen_r_mod & _T_2200; // @[dec_tlu_ctl.scala 2335:43] + wire _T_2201 = ~perfcnt_halted; // @[dec_tlu_ctl.scala 2336:23] + wire _T_2203 = _T_2201 | perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2336:39] + wire _T_2204 = |mhpmc_inc_r_0; // @[dec_tlu_ctl.scala 2336:86] + wire mhpmc3_wr_en1 = _T_2203 & _T_2204; // @[dec_tlu_ctl.scala 2336:66] reg [31:0] mhpmc3h; // @[lib.scala 374:16] reg [31:0] mhpmc3; // @[lib.scala 374:16] - wire [63:0] _T_2197 = {mhpmc3h,mhpmc3}; // @[Cat.scala 29:58] - wire [63:0] _T_2198 = {63'h0,mhpmc_inc_r_0}; // @[Cat.scala 29:58] - wire [63:0] mhpmc3_incr = _T_2197 + _T_2198; // @[dec_tlu_ctl.scala 2340:49] - wire _T_2206 = io_dec_csr_wraddr_r == 12'hb83; // @[dec_tlu_ctl.scala 2345:73] - wire mhpmc3h_wr_en0 = io_dec_csr_wen_r_mod & _T_2206; // @[dec_tlu_ctl.scala 2345:44] - wire _T_2212 = io_dec_csr_wraddr_r == 12'hb04; // @[dec_tlu_ctl.scala 2354:72] - wire mhpmc4_wr_en0 = io_dec_csr_wen_r_mod & _T_2212; // @[dec_tlu_ctl.scala 2354:43] - wire _T_2215 = _T_2191 | perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2355:39] - wire _T_2216 = |mhpmc_inc_r_1; // @[dec_tlu_ctl.scala 2355:86] - wire mhpmc4_wr_en1 = _T_2215 & _T_2216; // @[dec_tlu_ctl.scala 2355:66] + wire [63:0] _T_2207 = {mhpmc3h,mhpmc3}; // @[Cat.scala 29:58] + wire [63:0] _T_2208 = {63'h0,mhpmc_inc_r_0}; // @[Cat.scala 29:58] + wire [63:0] mhpmc3_incr = _T_2207 + _T_2208; // @[dec_tlu_ctl.scala 2340:49] + wire _T_2216 = io_dec_csr_wraddr_r == 12'hb83; // @[dec_tlu_ctl.scala 2345:73] + wire mhpmc3h_wr_en0 = io_dec_csr_wen_r_mod & _T_2216; // @[dec_tlu_ctl.scala 2345:44] + wire _T_2222 = io_dec_csr_wraddr_r == 12'hb04; // @[dec_tlu_ctl.scala 2354:72] + wire mhpmc4_wr_en0 = io_dec_csr_wen_r_mod & _T_2222; // @[dec_tlu_ctl.scala 2354:43] + wire _T_2225 = _T_2201 | perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2355:39] + wire _T_2226 = |mhpmc_inc_r_1; // @[dec_tlu_ctl.scala 2355:86] + wire mhpmc4_wr_en1 = _T_2225 & _T_2226; // @[dec_tlu_ctl.scala 2355:66] reg [31:0] mhpmc4h; // @[lib.scala 374:16] reg [31:0] mhpmc4; // @[lib.scala 374:16] - wire [63:0] _T_2219 = {mhpmc4h,mhpmc4}; // @[Cat.scala 29:58] - wire [63:0] _T_2220 = {63'h0,mhpmc_inc_r_1}; // @[Cat.scala 29:58] - wire [63:0] mhpmc4_incr = _T_2219 + _T_2220; // @[dec_tlu_ctl.scala 2360:49] - wire _T_2229 = io_dec_csr_wraddr_r == 12'hb84; // @[dec_tlu_ctl.scala 2364:73] - wire mhpmc4h_wr_en0 = io_dec_csr_wen_r_mod & _T_2229; // @[dec_tlu_ctl.scala 2364:44] - wire _T_2235 = io_dec_csr_wraddr_r == 12'hb05; // @[dec_tlu_ctl.scala 2373:72] - wire mhpmc5_wr_en0 = io_dec_csr_wen_r_mod & _T_2235; // @[dec_tlu_ctl.scala 2373:43] - wire _T_2238 = _T_2191 | perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2374:39] - wire _T_2239 = |mhpmc_inc_r_2; // @[dec_tlu_ctl.scala 2374:86] - wire mhpmc5_wr_en1 = _T_2238 & _T_2239; // @[dec_tlu_ctl.scala 2374:66] + wire [63:0] _T_2229 = {mhpmc4h,mhpmc4}; // @[Cat.scala 29:58] + wire [63:0] _T_2230 = {63'h0,mhpmc_inc_r_1}; // @[Cat.scala 29:58] + wire [63:0] mhpmc4_incr = _T_2229 + _T_2230; // @[dec_tlu_ctl.scala 2360:49] + wire _T_2239 = io_dec_csr_wraddr_r == 12'hb84; // @[dec_tlu_ctl.scala 2364:73] + wire mhpmc4h_wr_en0 = io_dec_csr_wen_r_mod & _T_2239; // @[dec_tlu_ctl.scala 2364:44] + wire _T_2245 = io_dec_csr_wraddr_r == 12'hb05; // @[dec_tlu_ctl.scala 2373:72] + wire mhpmc5_wr_en0 = io_dec_csr_wen_r_mod & _T_2245; // @[dec_tlu_ctl.scala 2373:43] + wire _T_2248 = _T_2201 | perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2374:39] + wire _T_2249 = |mhpmc_inc_r_2; // @[dec_tlu_ctl.scala 2374:86] + wire mhpmc5_wr_en1 = _T_2248 & _T_2249; // @[dec_tlu_ctl.scala 2374:66] reg [31:0] mhpmc5h; // @[lib.scala 374:16] reg [31:0] mhpmc5; // @[lib.scala 374:16] - wire [63:0] _T_2242 = {mhpmc5h,mhpmc5}; // @[Cat.scala 29:58] - wire [63:0] _T_2243 = {63'h0,mhpmc_inc_r_2}; // @[Cat.scala 29:58] - wire [63:0] mhpmc5_incr = _T_2242 + _T_2243; // @[dec_tlu_ctl.scala 2377:49] - wire _T_2251 = io_dec_csr_wraddr_r == 12'hb85; // @[dec_tlu_ctl.scala 2382:73] - wire mhpmc5h_wr_en0 = io_dec_csr_wen_r_mod & _T_2251; // @[dec_tlu_ctl.scala 2382:44] - wire _T_2257 = io_dec_csr_wraddr_r == 12'hb06; // @[dec_tlu_ctl.scala 2391:72] - wire mhpmc6_wr_en0 = io_dec_csr_wen_r_mod & _T_2257; // @[dec_tlu_ctl.scala 2391:43] - wire _T_2260 = _T_2191 | perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2392:39] - wire _T_2261 = |mhpmc_inc_r_3; // @[dec_tlu_ctl.scala 2392:86] - wire mhpmc6_wr_en1 = _T_2260 & _T_2261; // @[dec_tlu_ctl.scala 2392:66] + wire [63:0] _T_2252 = {mhpmc5h,mhpmc5}; // @[Cat.scala 29:58] + wire [63:0] _T_2253 = {63'h0,mhpmc_inc_r_2}; // @[Cat.scala 29:58] + wire [63:0] mhpmc5_incr = _T_2252 + _T_2253; // @[dec_tlu_ctl.scala 2377:49] + wire _T_2261 = io_dec_csr_wraddr_r == 12'hb85; // @[dec_tlu_ctl.scala 2382:73] + wire mhpmc5h_wr_en0 = io_dec_csr_wen_r_mod & _T_2261; // @[dec_tlu_ctl.scala 2382:44] + wire _T_2267 = io_dec_csr_wraddr_r == 12'hb06; // @[dec_tlu_ctl.scala 2391:72] + wire mhpmc6_wr_en0 = io_dec_csr_wen_r_mod & _T_2267; // @[dec_tlu_ctl.scala 2391:43] + wire _T_2270 = _T_2201 | perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2392:39] + wire _T_2271 = |mhpmc_inc_r_3; // @[dec_tlu_ctl.scala 2392:86] + wire mhpmc6_wr_en1 = _T_2270 & _T_2271; // @[dec_tlu_ctl.scala 2392:66] reg [31:0] mhpmc6h; // @[lib.scala 374:16] reg [31:0] mhpmc6; // @[lib.scala 374:16] - wire [63:0] _T_2264 = {mhpmc6h,mhpmc6}; // @[Cat.scala 29:58] - wire [63:0] _T_2265 = {63'h0,mhpmc_inc_r_3}; // @[Cat.scala 29:58] - wire [63:0] mhpmc6_incr = _T_2264 + _T_2265; // @[dec_tlu_ctl.scala 2395:49] - wire _T_2273 = io_dec_csr_wraddr_r == 12'hb86; // @[dec_tlu_ctl.scala 2400:73] - wire mhpmc6h_wr_en0 = io_dec_csr_wen_r_mod & _T_2273; // @[dec_tlu_ctl.scala 2400:44] - wire _T_2279 = io_dec_csr_wrdata_r[9:0] > 10'h204; // @[dec_tlu_ctl.scala 2411:56] - wire _T_2281 = |io_dec_csr_wrdata_r[31:10]; // @[dec_tlu_ctl.scala 2411:102] - wire _T_2282 = _T_2279 | _T_2281; // @[dec_tlu_ctl.scala 2411:71] - wire _T_2285 = io_dec_csr_wraddr_r == 12'h323; // @[dec_tlu_ctl.scala 2413:70] - wire wr_mhpme3_r = io_dec_csr_wen_r_mod & _T_2285; // @[dec_tlu_ctl.scala 2413:41] - wire _T_2289 = io_dec_csr_wraddr_r == 12'h324; // @[dec_tlu_ctl.scala 2420:70] - wire wr_mhpme4_r = io_dec_csr_wen_r_mod & _T_2289; // @[dec_tlu_ctl.scala 2420:41] - wire _T_2293 = io_dec_csr_wraddr_r == 12'h325; // @[dec_tlu_ctl.scala 2427:70] - wire wr_mhpme5_r = io_dec_csr_wen_r_mod & _T_2293; // @[dec_tlu_ctl.scala 2427:41] - wire _T_2297 = io_dec_csr_wraddr_r == 12'h326; // @[dec_tlu_ctl.scala 2434:70] - wire wr_mhpme6_r = io_dec_csr_wen_r_mod & _T_2297; // @[dec_tlu_ctl.scala 2434:41] - wire _T_2301 = io_dec_csr_wraddr_r == 12'h320; // @[dec_tlu_ctl.scala 2451:77] - wire wr_mcountinhibit_r = io_dec_csr_wen_r_mod & _T_2301; // @[dec_tlu_ctl.scala 2451:48] - wire _T_2313 = io_i0_valid_wb | io_exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 2466:51] - wire _T_2314 = _T_2313 | io_interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 2466:78] - wire _T_2315 = _T_2314 | io_dec_tlu_i0_valid_wb1; // @[dec_tlu_ctl.scala 2466:104] - wire _T_2316 = _T_2315 | io_dec_tlu_i0_exc_valid_wb1; // @[dec_tlu_ctl.scala 2466:130] - wire _T_2317 = _T_2316 | io_dec_tlu_int_valid_wb1; // @[dec_tlu_ctl.scala 2467:32] - reg _T_2320; // @[dec_tlu_ctl.scala 2469:62] - wire _T_2321 = io_i0_exception_valid_r_d1 | io_lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 2470:91] - wire _T_2322 = ~io_trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 2470:137] - wire _T_2323 = io_trigger_hit_r_d1 & _T_2322; // @[dec_tlu_ctl.scala 2470:135] - reg _T_2325; // @[dec_tlu_ctl.scala 2470:62] - reg [4:0] _T_2326; // @[dec_tlu_ctl.scala 2471:62] - reg _T_2327; // @[dec_tlu_ctl.scala 2472:62] - wire [31:0] _T_2333 = {io_core_id,4'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2342 = {21'h3,3'h0,io_mstatus[1],3'h0,io_mstatus[0],3'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2347 = {io_mtvec[30:1],1'h0,io_mtvec[0]}; // @[Cat.scala 29:58] - wire [31:0] _T_2360 = {1'h0,io_mip[5:3],16'h0,io_mip[2],3'h0,io_mip[1],3'h0,io_mip[0],3'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2373 = {1'h0,mie[5:3],16'h0,mie[2],3'h0,mie[1],3'h0,mie[0],3'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2385 = {io_mepc,1'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2390 = {28'h0,mscause}; // @[Cat.scala 29:58] - wire [31:0] _T_2398 = {meivt,10'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2401 = {meivt,meihap,2'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2404 = {28'h0,meicurpl}; // @[Cat.scala 29:58] - wire [31:0] _T_2407 = {28'h0,meicidpl}; // @[Cat.scala 29:58] - wire [31:0] _T_2410 = {28'h0,meipt}; // @[Cat.scala 29:58] - wire [31:0] _T_2413 = {23'h0,mcgc}; // @[Cat.scala 29:58] - wire [31:0] _T_2416 = {13'h0,_T_345,4'h0,mfdc_int[11:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_2420 = {16'h4000,io_dcsr[15:2],2'h3}; // @[Cat.scala 29:58] - wire [31:0] _T_2422 = {io_dpc,1'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2438 = {7'h0,dicawics[16],2'h0,dicawics[15:14],3'h0,dicawics[13:0],3'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2441 = {30'h0,mtsel}; // @[Cat.scala 29:58] - wire [31:0] _T_2470 = {26'h0,mfdht}; // @[Cat.scala 29:58] - wire [31:0] _T_2473 = {30'h0,mfdhs}; // @[Cat.scala 29:58] - wire [31:0] _T_2476 = {22'h0,mhpme3}; // @[Cat.scala 29:58] - wire [31:0] _T_2479 = {22'h0,mhpme4}; // @[Cat.scala 29:58] - wire [31:0] _T_2482 = {22'h0,mhpme5}; // @[Cat.scala 29:58] - wire [31:0] _T_2485 = {22'h0,mhpme6}; // @[Cat.scala 29:58] - wire [31:0] _T_2488 = {25'h0,temp_ncount6_2,1'h0,temp_ncount0}; // @[Cat.scala 29:58] - wire [31:0] _T_2491 = {30'h0,mpmc,1'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2494 = io_csr_pkt_csr_misa ? 32'h40001104 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2495 = io_csr_pkt_csr_mvendorid ? 32'h45 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2496 = io_csr_pkt_csr_marchid ? 32'h10 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2497 = io_csr_pkt_csr_mimpid ? 32'h2 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2498 = io_csr_pkt_csr_mhartid ? _T_2333 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2499 = io_csr_pkt_csr_mstatus ? _T_2342 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2500 = io_csr_pkt_csr_mtvec ? _T_2347 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2501 = io_csr_pkt_csr_mip ? _T_2360 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2502 = io_csr_pkt_csr_mie ? _T_2373 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2503 = io_csr_pkt_csr_mcyclel ? mcyclel : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2504 = io_csr_pkt_csr_mcycleh ? mcycleh_inc : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2505 = io_csr_pkt_csr_minstretl ? minstretl : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2506 = io_csr_pkt_csr_minstreth ? minstreth_inc : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2507 = io_csr_pkt_csr_mscratch ? mscratch : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2508 = io_csr_pkt_csr_mepc ? _T_2385 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2509 = io_csr_pkt_csr_mcause ? mcause : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2510 = io_csr_pkt_csr_mscause ? _T_2390 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2511 = io_csr_pkt_csr_mtval ? mtval : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2512 = io_csr_pkt_csr_mrac ? mrac : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2513 = io_csr_pkt_csr_mdseac ? mdseac : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2514 = io_csr_pkt_csr_meivt ? _T_2398 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2515 = io_csr_pkt_csr_meihap ? _T_2401 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2516 = io_csr_pkt_csr_meicurpl ? _T_2404 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2517 = io_csr_pkt_csr_meicidpl ? _T_2407 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2518 = io_csr_pkt_csr_meipt ? _T_2410 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2519 = io_csr_pkt_csr_mcgc ? _T_2413 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2520 = io_csr_pkt_csr_mfdc ? _T_2416 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2521 = io_csr_pkt_csr_dcsr ? _T_2420 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2522 = io_csr_pkt_csr_dpc ? _T_2422 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2523 = io_csr_pkt_csr_dicad0 ? dicad0[31:0] : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2524 = io_csr_pkt_csr_dicad0h ? dicad0h : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2525 = io_csr_pkt_csr_dicad1 ? dicad1 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2526 = io_csr_pkt_csr_dicawics ? _T_2438 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2527 = io_csr_pkt_csr_mtsel ? _T_2441 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2528 = io_csr_pkt_csr_mtdata1 ? mtdata1_tsel_out : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2529 = io_csr_pkt_csr_mtdata2 ? mtdata2_tsel_out : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2530 = io_csr_pkt_csr_micect ? micect : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2531 = io_csr_pkt_csr_miccmect ? miccmect : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2532 = io_csr_pkt_csr_mdccmect ? mdccmect : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2533 = io_csr_pkt_csr_mhpmc3 ? mhpmc3 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2534 = io_csr_pkt_csr_mhpmc4 ? mhpmc4 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2535 = io_csr_pkt_csr_mhpmc5 ? mhpmc5 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2536 = io_csr_pkt_csr_mhpmc6 ? mhpmc6 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2537 = io_csr_pkt_csr_mhpmc3h ? mhpmc3h : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2538 = io_csr_pkt_csr_mhpmc4h ? mhpmc4h : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2539 = io_csr_pkt_csr_mhpmc5h ? mhpmc5h : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2540 = io_csr_pkt_csr_mhpmc6h ? mhpmc6h : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2541 = io_csr_pkt_csr_mfdht ? _T_2470 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2542 = io_csr_pkt_csr_mfdhs ? _T_2473 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2543 = io_csr_pkt_csr_mhpme3 ? _T_2476 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2544 = io_csr_pkt_csr_mhpme4 ? _T_2479 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2545 = io_csr_pkt_csr_mhpme5 ? _T_2482 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2546 = io_csr_pkt_csr_mhpme6 ? _T_2485 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2547 = io_csr_pkt_csr_mcountinhibit ? _T_2488 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2548 = io_csr_pkt_csr_mpmc ? _T_2491 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2549 = io_dec_timer_read_d ? io_dec_timer_rddata_d : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2550 = _T_2494 | _T_2495; // @[Mux.scala 27:72] - wire [31:0] _T_2551 = _T_2550 | _T_2496; // @[Mux.scala 27:72] - wire [31:0] _T_2552 = _T_2551 | _T_2497; // @[Mux.scala 27:72] - wire [31:0] _T_2553 = _T_2552 | _T_2498; // @[Mux.scala 27:72] - wire [31:0] _T_2554 = _T_2553 | _T_2499; // @[Mux.scala 27:72] - wire [31:0] _T_2555 = _T_2554 | _T_2500; // @[Mux.scala 27:72] - wire [31:0] _T_2556 = _T_2555 | _T_2501; // @[Mux.scala 27:72] - wire [31:0] _T_2557 = _T_2556 | _T_2502; // @[Mux.scala 27:72] - wire [31:0] _T_2558 = _T_2557 | _T_2503; // @[Mux.scala 27:72] - wire [31:0] _T_2559 = _T_2558 | _T_2504; // @[Mux.scala 27:72] - wire [31:0] _T_2560 = _T_2559 | _T_2505; // @[Mux.scala 27:72] + wire [63:0] _T_2274 = {mhpmc6h,mhpmc6}; // @[Cat.scala 29:58] + wire [63:0] _T_2275 = {63'h0,mhpmc_inc_r_3}; // @[Cat.scala 29:58] + wire [63:0] mhpmc6_incr = _T_2274 + _T_2275; // @[dec_tlu_ctl.scala 2395:49] + wire _T_2283 = io_dec_csr_wraddr_r == 12'hb86; // @[dec_tlu_ctl.scala 2400:73] + wire mhpmc6h_wr_en0 = io_dec_csr_wen_r_mod & _T_2283; // @[dec_tlu_ctl.scala 2400:44] + wire _T_2289 = io_dec_csr_wrdata_r[9:0] > 10'h204; // @[dec_tlu_ctl.scala 2411:56] + wire _T_2291 = |io_dec_csr_wrdata_r[31:10]; // @[dec_tlu_ctl.scala 2411:102] + wire _T_2292 = _T_2289 | _T_2291; // @[dec_tlu_ctl.scala 2411:71] + wire _T_2295 = io_dec_csr_wraddr_r == 12'h323; // @[dec_tlu_ctl.scala 2413:70] + wire wr_mhpme3_r = io_dec_csr_wen_r_mod & _T_2295; // @[dec_tlu_ctl.scala 2413:41] + wire _T_2299 = io_dec_csr_wraddr_r == 12'h324; // @[dec_tlu_ctl.scala 2420:70] + wire wr_mhpme4_r = io_dec_csr_wen_r_mod & _T_2299; // @[dec_tlu_ctl.scala 2420:41] + wire _T_2303 = io_dec_csr_wraddr_r == 12'h325; // @[dec_tlu_ctl.scala 2427:70] + wire wr_mhpme5_r = io_dec_csr_wen_r_mod & _T_2303; // @[dec_tlu_ctl.scala 2427:41] + wire _T_2307 = io_dec_csr_wraddr_r == 12'h326; // @[dec_tlu_ctl.scala 2434:70] + wire wr_mhpme6_r = io_dec_csr_wen_r_mod & _T_2307; // @[dec_tlu_ctl.scala 2434:41] + wire _T_2311 = io_dec_csr_wraddr_r == 12'h320; // @[dec_tlu_ctl.scala 2451:77] + wire wr_mcountinhibit_r = io_dec_csr_wen_r_mod & _T_2311; // @[dec_tlu_ctl.scala 2451:48] + wire _T_2323 = io_i0_valid_wb | io_exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 2466:51] + wire _T_2324 = _T_2323 | io_interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 2466:78] + wire _T_2325 = _T_2324 | io_dec_tlu_i0_valid_wb1; // @[dec_tlu_ctl.scala 2466:104] + wire _T_2326 = _T_2325 | io_dec_tlu_i0_exc_valid_wb1; // @[dec_tlu_ctl.scala 2466:130] + wire _T_2327 = _T_2326 | io_dec_tlu_int_valid_wb1; // @[dec_tlu_ctl.scala 2467:32] + reg _T_2330; // @[dec_tlu_ctl.scala 2469:62] + wire _T_2331 = io_i0_exception_valid_r_d1 | io_lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 2470:91] + wire _T_2332 = ~io_trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 2470:137] + wire _T_2333 = io_trigger_hit_r_d1 & _T_2332; // @[dec_tlu_ctl.scala 2470:135] + reg _T_2335; // @[dec_tlu_ctl.scala 2470:62] + reg [4:0] _T_2336; // @[dec_tlu_ctl.scala 2471:62] + reg _T_2337; // @[dec_tlu_ctl.scala 2472:62] + wire [31:0] _T_2343 = {io_core_id,4'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2352 = {21'h3,3'h0,io_mstatus[1],3'h0,io_mstatus[0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2357 = {io_mtvec[30:1],1'h0,io_mtvec[0]}; // @[Cat.scala 29:58] + wire [31:0] _T_2370 = {1'h0,io_mip[5:3],16'h0,io_mip[2],3'h0,io_mip[1],3'h0,io_mip[0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2383 = {1'h0,mie[5:3],16'h0,mie[2],3'h0,mie[1],3'h0,mie[0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2395 = {io_mepc,1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2400 = {28'h0,mscause}; // @[Cat.scala 29:58] + wire [31:0] _T_2408 = {meivt,10'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2411 = {meivt,meihap,2'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2414 = {28'h0,meicurpl}; // @[Cat.scala 29:58] + wire [31:0] _T_2417 = {28'h0,meicidpl}; // @[Cat.scala 29:58] + wire [31:0] _T_2420 = {28'h0,meipt}; // @[Cat.scala 29:58] + wire [31:0] _T_2423 = {23'h0,mcgc}; // @[Cat.scala 29:58] + wire [31:0] _T_2426 = {13'h0,_T_350,4'h0,mfdc_int[11:7],_T_353,mfdc_int[5:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_2430 = {16'h4000,io_dcsr[15:2],2'h3}; // @[Cat.scala 29:58] + wire [31:0] _T_2432 = {io_dpc,1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2448 = {7'h0,dicawics[16],2'h0,dicawics[15:14],3'h0,dicawics[13:0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2451 = {30'h0,mtsel}; // @[Cat.scala 29:58] + wire [31:0] _T_2480 = {26'h0,mfdht}; // @[Cat.scala 29:58] + wire [31:0] _T_2483 = {30'h0,mfdhs}; // @[Cat.scala 29:58] + wire [31:0] _T_2486 = {22'h0,mhpme3}; // @[Cat.scala 29:58] + wire [31:0] _T_2489 = {22'h0,mhpme4}; // @[Cat.scala 29:58] + wire [31:0] _T_2492 = {22'h0,mhpme5}; // @[Cat.scala 29:58] + wire [31:0] _T_2495 = {22'h0,mhpme6}; // @[Cat.scala 29:58] + wire [31:0] _T_2498 = {25'h0,temp_ncount6_2,1'h0,temp_ncount0}; // @[Cat.scala 29:58] + wire [31:0] _T_2501 = {30'h0,mpmc,1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2504 = io_csr_pkt_csr_misa ? 32'h40001104 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2505 = io_csr_pkt_csr_mvendorid ? 32'h45 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2506 = io_csr_pkt_csr_marchid ? 32'h10 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2507 = io_csr_pkt_csr_mimpid ? 32'h2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2508 = io_csr_pkt_csr_mhartid ? _T_2343 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2509 = io_csr_pkt_csr_mstatus ? _T_2352 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2510 = io_csr_pkt_csr_mtvec ? _T_2357 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2511 = io_csr_pkt_csr_mip ? _T_2370 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2512 = io_csr_pkt_csr_mie ? _T_2383 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2513 = io_csr_pkt_csr_mcyclel ? mcyclel : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2514 = io_csr_pkt_csr_mcycleh ? mcycleh_inc : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2515 = io_csr_pkt_csr_minstretl ? minstretl : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2516 = io_csr_pkt_csr_minstreth ? minstreth_inc : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2517 = io_csr_pkt_csr_mscratch ? mscratch : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2518 = io_csr_pkt_csr_mepc ? _T_2395 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2519 = io_csr_pkt_csr_mcause ? mcause : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2520 = io_csr_pkt_csr_mscause ? _T_2400 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2521 = io_csr_pkt_csr_mtval ? mtval : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2522 = io_csr_pkt_csr_mrac ? mrac : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2523 = io_csr_pkt_csr_mdseac ? mdseac : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2524 = io_csr_pkt_csr_meivt ? _T_2408 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2525 = io_csr_pkt_csr_meihap ? _T_2411 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2526 = io_csr_pkt_csr_meicurpl ? _T_2414 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2527 = io_csr_pkt_csr_meicidpl ? _T_2417 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2528 = io_csr_pkt_csr_meipt ? _T_2420 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2529 = io_csr_pkt_csr_mcgc ? _T_2423 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2530 = io_csr_pkt_csr_mfdc ? _T_2426 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2531 = io_csr_pkt_csr_dcsr ? _T_2430 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2532 = io_csr_pkt_csr_dpc ? _T_2432 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2533 = io_csr_pkt_csr_dicad0 ? dicad0[31:0] : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2534 = io_csr_pkt_csr_dicad0h ? dicad0h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2535 = io_csr_pkt_csr_dicad1 ? dicad1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2536 = io_csr_pkt_csr_dicawics ? _T_2448 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2537 = io_csr_pkt_csr_mtsel ? _T_2451 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2538 = io_csr_pkt_csr_mtdata1 ? mtdata1_tsel_out : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2539 = io_csr_pkt_csr_mtdata2 ? mtdata2_tsel_out : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2540 = io_csr_pkt_csr_micect ? micect : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2541 = io_csr_pkt_csr_miccmect ? miccmect : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2542 = io_csr_pkt_csr_mdccmect ? mdccmect : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2543 = io_csr_pkt_csr_mhpmc3 ? mhpmc3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2544 = io_csr_pkt_csr_mhpmc4 ? mhpmc4 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2545 = io_csr_pkt_csr_mhpmc5 ? mhpmc5 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2546 = io_csr_pkt_csr_mhpmc6 ? mhpmc6 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2547 = io_csr_pkt_csr_mhpmc3h ? mhpmc3h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2548 = io_csr_pkt_csr_mhpmc4h ? mhpmc4h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2549 = io_csr_pkt_csr_mhpmc5h ? mhpmc5h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2550 = io_csr_pkt_csr_mhpmc6h ? mhpmc6h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2551 = io_csr_pkt_csr_mfdht ? _T_2480 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2552 = io_csr_pkt_csr_mfdhs ? _T_2483 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2553 = io_csr_pkt_csr_mhpme3 ? _T_2486 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2554 = io_csr_pkt_csr_mhpme4 ? _T_2489 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2555 = io_csr_pkt_csr_mhpme5 ? _T_2492 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2556 = io_csr_pkt_csr_mhpme6 ? _T_2495 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2557 = io_csr_pkt_csr_mcountinhibit ? _T_2498 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2558 = io_csr_pkt_csr_mpmc ? _T_2501 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2559 = io_dec_timer_read_d ? io_dec_timer_rddata_d : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2560 = _T_2504 | _T_2505; // @[Mux.scala 27:72] wire [31:0] _T_2561 = _T_2560 | _T_2506; // @[Mux.scala 27:72] wire [31:0] _T_2562 = _T_2561 | _T_2507; // @[Mux.scala 27:72] wire [31:0] _T_2563 = _T_2562 | _T_2508; // @[Mux.scala 27:72] @@ -52386,6 +52387,16 @@ module csr_tlu( wire [31:0] _T_2601 = _T_2600 | _T_2546; // @[Mux.scala 27:72] wire [31:0] _T_2602 = _T_2601 | _T_2547; // @[Mux.scala 27:72] wire [31:0] _T_2603 = _T_2602 | _T_2548; // @[Mux.scala 27:72] + wire [31:0] _T_2604 = _T_2603 | _T_2549; // @[Mux.scala 27:72] + wire [31:0] _T_2605 = _T_2604 | _T_2550; // @[Mux.scala 27:72] + wire [31:0] _T_2606 = _T_2605 | _T_2551; // @[Mux.scala 27:72] + wire [31:0] _T_2607 = _T_2606 | _T_2552; // @[Mux.scala 27:72] + wire [31:0] _T_2608 = _T_2607 | _T_2553; // @[Mux.scala 27:72] + wire [31:0] _T_2609 = _T_2608 | _T_2554; // @[Mux.scala 27:72] + wire [31:0] _T_2610 = _T_2609 | _T_2555; // @[Mux.scala 27:72] + wire [31:0] _T_2611 = _T_2610 | _T_2556; // @[Mux.scala 27:72] + wire [31:0] _T_2612 = _T_2611 | _T_2557; // @[Mux.scala 27:72] + wire [31:0] _T_2613 = _T_2612 | _T_2558; // @[Mux.scala 27:72] rvclkhdr rvclkhdr ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), @@ -52596,7 +52607,7 @@ module csr_tlu( .io_en(rvclkhdr_34_io_en), .io_scan_mode(rvclkhdr_34_io_scan_mode) ); - assign io_dec_tlu_ic_diag_pkt_icache_wrdata = {_T_753,dicad0[31:0]}; // @[dec_tlu_ctl.scala 2136:56] + assign io_dec_tlu_ic_diag_pkt_icache_wrdata = {_T_763,dicad0[31:0]}; // @[dec_tlu_ctl.scala 2136:56] assign io_dec_tlu_ic_diag_pkt_icache_dicawics = dicawics; // @[dec_tlu_ctl.scala 2139:41] assign io_dec_tlu_ic_diag_pkt_icache_rd_valid = icache_rd_valid_f; // @[dec_tlu_ctl.scala 2147:41] assign io_dec_tlu_ic_diag_pkt_icache_wr_valid = icache_wr_valid_f; // @[dec_tlu_ctl.scala 2148:41] @@ -52628,52 +52639,52 @@ module csr_tlu( assign io_trigger_pkt_any_3_execute = io_mtdata1_t_3[2]; // @[dec_tlu_ctl.scala 2216:40] assign io_trigger_pkt_any_3_m = io_mtdata1_t_3[3]; // @[dec_tlu_ctl.scala 2217:40] assign io_trigger_pkt_any_3_tdata2 = mtdata2_t_3; // @[dec_tlu_ctl.scala 2230:51] - assign io_dec_tlu_int_valid_wb1 = _T_2327; // @[dec_tlu_ctl.scala 2472:30] - assign io_dec_tlu_i0_exc_valid_wb1 = _T_2325; // @[dec_tlu_ctl.scala 2470:30] - assign io_dec_tlu_i0_valid_wb1 = _T_2320; // @[dec_tlu_ctl.scala 2469:30] + assign io_dec_tlu_int_valid_wb1 = _T_2337; // @[dec_tlu_ctl.scala 2472:30] + assign io_dec_tlu_i0_exc_valid_wb1 = _T_2335; // @[dec_tlu_ctl.scala 2470:30] + assign io_dec_tlu_i0_valid_wb1 = _T_2330; // @[dec_tlu_ctl.scala 2469:30] assign io_dec_tlu_mtval_wb1 = mtval; // @[dec_tlu_ctl.scala 2474:24] - assign io_dec_tlu_exc_cause_wb1 = _T_2326; // @[dec_tlu_ctl.scala 2471:30] - assign io_dec_tlu_perfcnt0 = mhpmc_inc_r_d1_0 & _T_2172; // @[dec_tlu_ctl.scala 2326:22] - assign io_dec_tlu_perfcnt1 = mhpmc_inc_r_d1_1 & _T_2177; // @[dec_tlu_ctl.scala 2327:22] - assign io_dec_tlu_perfcnt2 = mhpmc_inc_r_d1_2 & _T_2182; // @[dec_tlu_ctl.scala 2328:22] - assign io_dec_tlu_perfcnt3 = mhpmc_inc_r_d1_3 & _T_2187; // @[dec_tlu_ctl.scala 2329:22] + assign io_dec_tlu_exc_cause_wb1 = _T_2336; // @[dec_tlu_ctl.scala 2471:30] + assign io_dec_tlu_perfcnt0 = mhpmc_inc_r_d1_0 & _T_2182; // @[dec_tlu_ctl.scala 2326:22] + assign io_dec_tlu_perfcnt1 = mhpmc_inc_r_d1_1 & _T_2187; // @[dec_tlu_ctl.scala 2327:22] + assign io_dec_tlu_perfcnt2 = mhpmc_inc_r_d1_2 & _T_2192; // @[dec_tlu_ctl.scala 2328:22] + assign io_dec_tlu_perfcnt3 = mhpmc_inc_r_d1_3 & _T_2197; // @[dec_tlu_ctl.scala 2329:22] assign io_dec_tlu_misc_clk_override = mcgc[8]; // @[dec_tlu_ctl.scala 1698:31] assign io_dec_tlu_dec_clk_override = mcgc[7]; // @[dec_tlu_ctl.scala 1699:31] assign io_dec_tlu_lsu_clk_override = mcgc[4]; // @[dec_tlu_ctl.scala 1701:31] - assign io_dec_tlu_bus_clk_override = mcgc[3]; // @[dec_tlu_ctl.scala 1702:31] assign io_dec_tlu_pic_clk_override = mcgc[2]; // @[dec_tlu_ctl.scala 1703:31] assign io_dec_tlu_dccm_clk_override = mcgc[1]; // @[dec_tlu_ctl.scala 1704:31] assign io_dec_tlu_icm_clk_override = mcgc[0]; // @[dec_tlu_ctl.scala 1705:31] - assign io_dec_csr_rddata_d = _T_2603 | _T_2549; // @[dec_tlu_ctl.scala 2479:21] + assign io_dec_csr_rddata_d = _T_2613 | _T_2559; // @[dec_tlu_ctl.scala 2479:21] assign io_dec_tlu_pipelining_disable = mfdc[0]; // @[dec_tlu_ctl.scala 1748:39] - assign io_dec_tlu_wr_pause_r = _T_360 & _T_361; // @[dec_tlu_ctl.scala 1757:24] + assign io_dec_tlu_wr_pause_r = _T_370 & _T_371; // @[dec_tlu_ctl.scala 1757:24] assign io_dec_tlu_meipt = meipt; // @[dec_tlu_ctl.scala 1986:19] assign io_dec_tlu_meicurpl = meicurpl; // @[dec_tlu_ctl.scala 1950:22] assign io_dec_tlu_meihap = {meivt,meihap}; // @[dec_tlu_ctl.scala 1936:20] assign io_dec_tlu_mrac_ff = mrac; // @[dec_tlu_ctl.scala 1787:21] + assign io_dec_tlu_wb_coalescing_disable = mfdc[2]; // @[dec_tlu_ctl.scala 1747:39] assign io_dec_tlu_bpred_disable = mfdc[3]; // @[dec_tlu_ctl.scala 1746:39] assign io_dec_tlu_sideeffect_posted_disable = mfdc[6]; // @[dec_tlu_ctl.scala 1745:39] assign io_dec_tlu_core_ecc_disable = mfdc[8]; // @[dec_tlu_ctl.scala 1744:39] assign io_dec_tlu_external_ldfwd_disable = mfdc[11]; // @[dec_tlu_ctl.scala 1743:39] assign io_dec_tlu_dma_qos_prty = mfdc[18:16]; // @[dec_tlu_ctl.scala 1742:39] assign io_dec_csr_wen_r_mod = _T_1 & _T_2; // @[dec_tlu_ctl.scala 1431:23] - assign io_fw_halt_req = _T_492 & _T_493; // @[dec_tlu_ctl.scala 1822:17] + assign io_fw_halt_req = _T_502 & _T_503; // @[dec_tlu_ctl.scala 1822:17] assign io_mstatus = _T_56; // @[dec_tlu_ctl.scala 1447:13] assign io_mstatus_mie_ns = io_mstatus[0] & _T_54; // @[dec_tlu_ctl.scala 1446:20] - assign io_dcsr = _T_691; // @[dec_tlu_ctl.scala 2033:10] + assign io_dcsr = _T_701; // @[dec_tlu_ctl.scala 2033:10] assign io_mtvec = _T_62; // @[dec_tlu_ctl.scala 1459:11] assign io_mip = _T_68; // @[dec_tlu_ctl.scala 1474:9] assign io_mie_ns = wr_mie_r ? _T_78 : mie; // @[dec_tlu_ctl.scala 1488:12] assign io_npc_r = _T_161 | _T_159; // @[dec_tlu_ctl.scala 1582:11] assign io_npc_r_d1 = _T_167; // @[dec_tlu_ctl.scala 1588:14] assign io_mepc = _T_196; // @[dec_tlu_ctl.scala 1607:10] - assign io_mdseac_locked_ns = mdseac_en | _T_479; // @[dec_tlu_ctl.scala 1805:22] - assign io_force_halt = mfdht[0] & _T_599; // @[dec_tlu_ctl.scala 1913:16] - assign io_dpc = _T_716; // @[dec_tlu_ctl.scala 2050:9] - assign io_mtdata1_t_0 = _T_862; // @[dec_tlu_ctl.scala 2207:39] - assign io_mtdata1_t_1 = _T_863; // @[dec_tlu_ctl.scala 2207:39] - assign io_mtdata1_t_2 = _T_864; // @[dec_tlu_ctl.scala 2207:39] - assign io_mtdata1_t_3 = _T_865; // @[dec_tlu_ctl.scala 2207:39] + assign io_mdseac_locked_ns = mdseac_en | _T_489; // @[dec_tlu_ctl.scala 1805:22] + assign io_force_halt = mfdht[0] & _T_609; // @[dec_tlu_ctl.scala 1913:16] + assign io_dpc = _T_726; // @[dec_tlu_ctl.scala 2050:9] + assign io_mtdata1_t_0 = _T_872; // @[dec_tlu_ctl.scala 2207:39] + assign io_mtdata1_t_1 = _T_873; // @[dec_tlu_ctl.scala 2207:39] + assign io_mtdata1_t_2 = _T_874; // @[dec_tlu_ctl.scala 2207:39] + assign io_mtdata1_t_3 = _T_875; // @[dec_tlu_ctl.scala 2207:39] assign rvclkhdr_io_clk = clock; // @[lib.scala 370:18] assign rvclkhdr_io_en = io_dec_csr_wen_r_mod & _T_58; // @[lib.scala 371:17] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] @@ -52705,34 +52716,34 @@ module csr_tlu( assign rvclkhdr_9_io_en = io_dec_csr_wen_r_mod & _T_337; // @[lib.scala 371:17] assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_10_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_10_io_en = io_dec_csr_wen_r_mod & _T_364; // @[lib.scala 371:17] + assign rvclkhdr_10_io_en = io_dec_csr_wen_r_mod & _T_374; // @[lib.scala 371:17] assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_11_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_11_io_en = _T_483 & _T_484; // @[lib.scala 371:17] + assign rvclkhdr_11_io_en = _T_493 & _T_494; // @[lib.scala 371:17] assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_12_io_clk = clock; // @[lib.scala 370:18] assign rvclkhdr_12_io_en = wr_micect_r | io_ic_perr_r_d1; // @[lib.scala 371:17] assign rvclkhdr_12_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_13_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_13_io_en = _T_539 | io_iccm_dma_sb_error; // @[lib.scala 371:17] + assign rvclkhdr_13_io_en = _T_549 | io_iccm_dma_sb_error; // @[lib.scala 371:17] assign rvclkhdr_13_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_14_io_clk = clock; // @[lib.scala 370:18] assign rvclkhdr_14_io_en = wr_mdccmect_r | io_lsu_single_ecc_error_r_d1; // @[lib.scala 371:17] assign rvclkhdr_14_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_15_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_15_io_en = io_dec_csr_wen_r_mod & _T_602; // @[lib.scala 371:17] + assign rvclkhdr_15_io_en = io_dec_csr_wen_r_mod & _T_612; // @[lib.scala 371:17] assign rvclkhdr_15_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_16_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_16_io_en = _T_622 | io_take_ext_int_start; // @[lib.scala 371:17] + assign rvclkhdr_16_io_en = _T_632 | io_take_ext_int_start; // @[lib.scala 371:17] assign rvclkhdr_16_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_17_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_17_io_en = _T_688 | io_take_nmi; // @[lib.scala 371:17] + assign rvclkhdr_17_io_en = _T_698 | io_take_nmi; // @[lib.scala 371:17] assign rvclkhdr_17_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_18_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_18_io_en = _T_713 | dpc_capture_npc; // @[lib.scala 371:17] + assign rvclkhdr_18_io_en = _T_723 | dpc_capture_npc; // @[lib.scala 371:17] assign rvclkhdr_18_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_19_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_19_io_en = _T_653 & _T_723; // @[lib.scala 371:17] + assign rvclkhdr_19_io_en = _T_663 & _T_733; // @[lib.scala 371:17] assign rvclkhdr_19_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_20_io_clk = clock; // @[lib.scala 370:18] assign rvclkhdr_20_io_en = wr_dicad0_r | io_ifu_ic_debug_rd_data_valid; // @[lib.scala 371:17] @@ -52741,16 +52752,16 @@ module csr_tlu( assign rvclkhdr_21_io_en = wr_dicad0h_r | io_ifu_ic_debug_rd_data_valid; // @[lib.scala 371:17] assign rvclkhdr_21_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_22_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_22_io_en = _T_961 & _T_797; // @[lib.scala 371:17] + assign rvclkhdr_22_io_en = _T_971 & _T_807; // @[lib.scala 371:17] assign rvclkhdr_22_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_23_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_23_io_en = _T_970 & _T_806; // @[lib.scala 371:17] + assign rvclkhdr_23_io_en = _T_980 & _T_816; // @[lib.scala 371:17] assign rvclkhdr_23_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_24_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_24_io_en = _T_979 & _T_815; // @[lib.scala 371:17] + assign rvclkhdr_24_io_en = _T_989 & _T_825; // @[lib.scala 371:17] assign rvclkhdr_24_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_25_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_25_io_en = _T_988 & _T_824; // @[lib.scala 371:17] + assign rvclkhdr_25_io_en = _T_998 & _T_834; // @[lib.scala 371:17] assign rvclkhdr_25_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_26_io_clk = clock; // @[lib.scala 370:18] assign rvclkhdr_26_io_en = mhpmc3_wr_en0 | mhpmc3_wr_en1; // @[lib.scala 371:17] @@ -52777,7 +52788,7 @@ module csr_tlu( assign rvclkhdr_33_io_en = mhpmc6h_wr_en0 | mhpmc6_wr_en1; // @[lib.scala 371:17] assign rvclkhdr_33_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_34_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_34_io_en = _T_2317 | io_clk_override; // @[lib.scala 345:16] + assign rvclkhdr_34_io_en = _T_2327 | io_clk_override; // @[lib.scala 345:16] assign rvclkhdr_34_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE @@ -52887,9 +52898,9 @@ initial begin _RAND_35 = {1{`RANDOM}}; meipt = _RAND_35[3:0]; _RAND_36 = {1{`RANDOM}}; - _T_691 = _RAND_36[15:0]; + _T_701 = _RAND_36[15:0]; _RAND_37 = {1{`RANDOM}}; - _T_716 = _RAND_37[30:0]; + _T_726 = _RAND_37[30:0]; _RAND_38 = {1{`RANDOM}}; dicawics = _RAND_38[16:0]; _RAND_39 = {3{`RANDOM}}; @@ -52897,7 +52908,7 @@ initial begin _RAND_40 = {1{`RANDOM}}; dicad0h = _RAND_40[31:0]; _RAND_41 = {1{`RANDOM}}; - _T_748 = _RAND_41[31:0]; + _T_758 = _RAND_41[31:0]; _RAND_42 = {1{`RANDOM}}; icache_rd_valid_f = _RAND_42[0:0]; _RAND_43 = {1{`RANDOM}}; @@ -52905,13 +52916,13 @@ initial begin _RAND_44 = {1{`RANDOM}}; mtsel = _RAND_44[1:0]; _RAND_45 = {1{`RANDOM}}; - _T_862 = _RAND_45[9:0]; + _T_872 = _RAND_45[9:0]; _RAND_46 = {1{`RANDOM}}; - _T_863 = _RAND_46[9:0]; + _T_873 = _RAND_46[9:0]; _RAND_47 = {1{`RANDOM}}; - _T_864 = _RAND_47[9:0]; + _T_874 = _RAND_47[9:0]; _RAND_48 = {1{`RANDOM}}; - _T_865 = _RAND_48[9:0]; + _T_875 = _RAND_48[9:0]; _RAND_49 = {1{`RANDOM}}; mtdata2_t_0 = _RAND_49[31:0]; _RAND_50 = {1{`RANDOM}}; @@ -52955,13 +52966,13 @@ initial begin _RAND_69 = {1{`RANDOM}}; mhpmc6 = _RAND_69[31:0]; _RAND_70 = {1{`RANDOM}}; - _T_2320 = _RAND_70[0:0]; + _T_2330 = _RAND_70[0:0]; _RAND_71 = {1{`RANDOM}}; - _T_2325 = _RAND_71[0:0]; + _T_2335 = _RAND_71[0:0]; _RAND_72 = {1{`RANDOM}}; - _T_2326 = _RAND_72[4:0]; + _T_2336 = _RAND_72[4:0]; _RAND_73 = {1{`RANDOM}}; - _T_2327 = _RAND_73[0:0]; + _T_2337 = _RAND_73[0:0]; `endif // RANDOMIZE_REG_INIT if (reset) begin mpmc_b = 1'h0; @@ -53072,10 +53083,10 @@ initial begin meipt = 4'h0; end if (reset) begin - _T_691 = 16'h0; + _T_701 = 16'h0; end if (reset) begin - _T_716 = 31'h0; + _T_726 = 31'h0; end if (reset) begin dicawics = 17'h0; @@ -53087,7 +53098,7 @@ initial begin dicad0h = 32'h0; end if (reset) begin - _T_748 = 32'h0; + _T_758 = 32'h0; end if (reset) begin icache_rd_valid_f = 1'h0; @@ -53099,16 +53110,16 @@ initial begin mtsel = 2'h0; end if (reset) begin - _T_862 = 10'h0; + _T_872 = 10'h0; end if (reset) begin - _T_863 = 10'h0; + _T_873 = 10'h0; end if (reset) begin - _T_864 = 10'h0; + _T_874 = 10'h0; end if (reset) begin - _T_865 = 10'h0; + _T_875 = 10'h0; end if (reset) begin mtdata2_t_0 = 32'h0; @@ -53174,16 +53185,16 @@ initial begin mhpmc6 = 32'h0; end if (reset) begin - _T_2320 = 1'h0; + _T_2330 = 1'h0; end if (reset) begin - _T_2325 = 1'h0; + _T_2335 = 1'h0; end if (reset) begin - _T_2326 = 5'h0; + _T_2336 = 5'h0; end if (reset) begin - _T_2327 = 1'h0; + _T_2337 = 1'h0; end `endif // RANDOMIZE end // initial @@ -53195,9 +53206,9 @@ end // initial if (reset) begin mpmc_b <= 1'h0; end else if (wr_mpmc_r) begin - mpmc_b <= _T_500; + mpmc_b <= _T_510; end else begin - mpmc_b <= _T_501; + mpmc_b <= _T_511; end end always @(posedge io_free_clk or posedge reset) begin @@ -53218,27 +53229,27 @@ end // initial if (reset) begin mdccmect <= 32'h0; end else if (wr_mdccmect_r) begin - mdccmect <= _T_515; + mdccmect <= _T_525; end else begin - mdccmect <= _T_559; + mdccmect <= _T_569; end end always @(posedge rvclkhdr_13_io_l1clk or posedge reset) begin if (reset) begin miccmect <= 32'h0; end else if (wr_miccmect_r) begin - miccmect <= _T_515; + miccmect <= _T_525; end else begin - miccmect <= _T_538; + miccmect <= _T_548; end end always @(posedge rvclkhdr_12_io_l1clk or posedge reset) begin if (reset) begin micect <= 32'h0; end else if (wr_micect_r) begin - micect <= _T_515; + micect <= _T_525; end else begin - micect <= _T_517; + micect <= _T_527; end end always @(posedge io_free_clk or posedge reset) begin @@ -53386,14 +53397,14 @@ end // initial if (reset) begin mfdc_int <= 15'h0; end else begin - mfdc_int <= {_T_341,io_dec_csr_wrdata_r[11:0]}; + mfdc_int <= {_T_347,_T_346}; end end always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin if (reset) begin mrac <= 32'h0; end else begin - mrac <= {_T_474,_T_459}; + mrac <= {_T_484,_T_469}; end end always @(posedge rvclkhdr_11_io_l1clk or posedge reset) begin @@ -53413,11 +53424,11 @@ end // initial always @(posedge io_active_clk or posedge reset) begin if (reset) begin mfdhs <= 2'h0; - end else if (_T_585) begin + end else if (_T_595) begin if (wr_mfdhs_r) begin mfdhs <= io_dec_csr_wrdata_r[1:0]; - end else if (_T_579) begin - mfdhs <= _T_583; + end else if (_T_589) begin + mfdhs <= _T_593; end end end @@ -53426,7 +53437,7 @@ end // initial force_halt_ctr_f <= 32'h0; end else if (mfdht[0]) begin if (io_debug_halt_req_f) begin - force_halt_ctr_f <= _T_590; + force_halt_ctr_f <= _T_600; end else if (io_dbg_tlu_halted_f) begin force_halt_ctr_f <= 32'h0; end @@ -53471,27 +53482,27 @@ end // initial end always @(posedge rvclkhdr_17_io_l1clk or posedge reset) begin if (reset) begin - _T_691 <= 16'h0; + _T_701 <= 16'h0; end else if (enter_debug_halt_req_le) begin - _T_691 <= _T_665; + _T_701 <= _T_675; end else if (wr_dcsr_r) begin - _T_691 <= _T_680; + _T_701 <= _T_690; end else begin - _T_691 <= _T_685; + _T_701 <= _T_695; end end always @(posedge rvclkhdr_18_io_l1clk or posedge reset) begin if (reset) begin - _T_716 <= 31'h0; + _T_726 <= 31'h0; end else begin - _T_716 <= _T_711 | _T_710; + _T_726 <= _T_721 | _T_720; end end always @(posedge rvclkhdr_19_io_l1clk or posedge reset) begin if (reset) begin dicawics <= 17'h0; end else begin - dicawics <= {_T_720,io_dec_csr_wrdata_r[16:3]}; + dicawics <= {_T_730,io_dec_csr_wrdata_r[16:3]}; end end always @(posedge rvclkhdr_20_io_l1clk or posedge reset) begin @@ -53514,12 +53525,12 @@ end // initial end always @(posedge io_active_clk or posedge reset) begin if (reset) begin - _T_748 <= 32'h0; - end else if (_T_746) begin - if (_T_742) begin - _T_748 <= io_dec_csr_wrdata_r; + _T_758 <= 32'h0; + end else if (_T_756) begin + if (_T_752) begin + _T_758 <= io_dec_csr_wrdata_r; end else begin - _T_748 <= {{25'd0}, io_ifu_ic_debug_rd_data[70:64]}; + _T_758 <= {{25'd0}, io_ifu_ic_debug_rd_data[70:64]}; end end end @@ -53527,14 +53538,14 @@ end // initial if (reset) begin icache_rd_valid_f <= 1'h0; end else begin - icache_rd_valid_f <= _T_758 & _T_760; + icache_rd_valid_f <= _T_768 & _T_770; end end always @(posedge io_active_clk or posedge reset) begin if (reset) begin icache_wr_valid_f <= 1'h0; end else begin - icache_wr_valid_f <= _T_653 & _T_763; + icache_wr_valid_f <= _T_663 & _T_773; end end always @(posedge io_csr_wr_clk or posedge reset) begin @@ -53546,38 +53557,38 @@ end // initial end always @(posedge io_active_clk or posedge reset) begin if (reset) begin - _T_862 <= 10'h0; + _T_872 <= 10'h0; end else if (wr_mtdata1_t_r_0) begin - _T_862 <= tdata_wrdata_r; + _T_872 <= tdata_wrdata_r; end else begin - _T_862 <= _T_833; + _T_872 <= _T_843; end end always @(posedge io_active_clk or posedge reset) begin if (reset) begin - _T_863 <= 10'h0; + _T_873 <= 10'h0; end else if (wr_mtdata1_t_r_1) begin - _T_863 <= tdata_wrdata_r; + _T_873 <= tdata_wrdata_r; end else begin - _T_863 <= _T_842; + _T_873 <= _T_852; end end always @(posedge io_active_clk or posedge reset) begin if (reset) begin - _T_864 <= 10'h0; + _T_874 <= 10'h0; end else if (wr_mtdata1_t_r_2) begin - _T_864 <= tdata_wrdata_r; + _T_874 <= tdata_wrdata_r; end else begin - _T_864 <= _T_851; + _T_874 <= _T_861; end end always @(posedge io_active_clk or posedge reset) begin if (reset) begin - _T_865 <= 10'h0; + _T_875 <= 10'h0; end else if (wr_mtdata1_t_r_3) begin - _T_865 <= tdata_wrdata_r; + _T_875 <= tdata_wrdata_r; end else begin - _T_865 <= _T_860; + _T_875 <= _T_870; end end always @(posedge rvclkhdr_22_io_l1clk or posedge reset) begin @@ -53612,7 +53623,7 @@ end // initial if (reset) begin mhpme3 <= 10'h0; end else if (wr_mhpme3_r) begin - if (_T_2282) begin + if (_T_2292) begin mhpme3 <= 10'h204; end else begin mhpme3 <= io_dec_csr_wrdata_r[9:0]; @@ -53623,7 +53634,7 @@ end // initial if (reset) begin mhpme4 <= 10'h0; end else if (wr_mhpme4_r) begin - if (_T_2282) begin + if (_T_2292) begin mhpme4 <= 10'h204; end else begin mhpme4 <= io_dec_csr_wrdata_r[9:0]; @@ -53634,7 +53645,7 @@ end // initial if (reset) begin mhpme5 <= 10'h0; end else if (wr_mhpme5_r) begin - if (_T_2282) begin + if (_T_2292) begin mhpme5 <= 10'h204; end else begin mhpme5 <= io_dec_csr_wrdata_r[9:0]; @@ -53645,7 +53656,7 @@ end // initial if (reset) begin mhpme6 <= 10'h0; end else if (wr_mhpme6_r) begin - if (_T_2282) begin + if (_T_2292) begin mhpme6 <= 10'h204; end else begin mhpme6 <= io_dec_csr_wrdata_r[9:0]; @@ -53656,28 +53667,28 @@ end // initial if (reset) begin mhpmc_inc_r_d1_0 <= 1'h0; end else begin - mhpmc_inc_r_d1_0 <= _T_1015 & _T_1295; + mhpmc_inc_r_d1_0 <= _T_1025 & _T_1305; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin mhpmc_inc_r_d1_1 <= 1'h0; end else begin - mhpmc_inc_r_d1_1 <= _T_1299 & _T_1579; + mhpmc_inc_r_d1_1 <= _T_1309 & _T_1589; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin mhpmc_inc_r_d1_2 <= 1'h0; end else begin - mhpmc_inc_r_d1_2 <= _T_1583 & _T_1863; + mhpmc_inc_r_d1_2 <= _T_1593 & _T_1873; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin mhpmc_inc_r_d1_3 <= 1'h0; end else begin - mhpmc_inc_r_d1_3 <= _T_1867 & _T_2147; + mhpmc_inc_r_d1_3 <= _T_1877 & _T_2157; end end always @(posedge io_free_clk or posedge reset) begin @@ -53761,30 +53772,30 @@ end // initial end always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin if (reset) begin - _T_2320 <= 1'h0; + _T_2330 <= 1'h0; end else begin - _T_2320 <= io_i0_valid_wb; + _T_2330 <= io_i0_valid_wb; end end always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin if (reset) begin - _T_2325 <= 1'h0; + _T_2335 <= 1'h0; end else begin - _T_2325 <= _T_2321 | _T_2323; + _T_2335 <= _T_2331 | _T_2333; end end always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin if (reset) begin - _T_2326 <= 5'h0; + _T_2336 <= 5'h0; end else begin - _T_2326 <= io_exc_cause_wb; + _T_2336 <= io_exc_cause_wb; end end always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin if (reset) begin - _T_2327 <= 1'h0; + _T_2337 <= 1'h0; end else begin - _T_2327 <= io_interrupt_valid_r_d1; + _T_2337 <= io_interrupt_valid_r_d1; end end endmodule @@ -54368,7 +54379,6 @@ module dec_tlu_ctl( output io_dec_tlu_misc_clk_override, output io_dec_tlu_dec_clk_override, output io_dec_tlu_lsu_clk_override, - output io_dec_tlu_bus_clk_override, output io_dec_tlu_pic_clk_override, output io_dec_tlu_dccm_clk_override, output io_dec_tlu_icm_clk_override, @@ -54409,6 +54419,7 @@ module dec_tlu_ctl( input io_tlu_busbuff_lsu_pmu_bus_error, input io_tlu_busbuff_lsu_pmu_bus_busy, output io_tlu_busbuff_dec_tlu_external_ldfwd_disable, + output io_tlu_busbuff_dec_tlu_wb_coalescing_disable, output io_tlu_busbuff_dec_tlu_sideeffect_posted_disable, input io_tlu_busbuff_lsu_imprecise_error_load_any, input io_tlu_busbuff_lsu_imprecise_error_store_any, @@ -54620,7 +54631,6 @@ module dec_tlu_ctl( wire csr_io_dec_tlu_misc_clk_override; // @[dec_tlu_ctl.scala 813:15] wire csr_io_dec_tlu_dec_clk_override; // @[dec_tlu_ctl.scala 813:15] wire csr_io_dec_tlu_lsu_clk_override; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_dec_tlu_bus_clk_override; // @[dec_tlu_ctl.scala 813:15] wire csr_io_dec_tlu_pic_clk_override; // @[dec_tlu_ctl.scala 813:15] wire csr_io_dec_tlu_dccm_clk_override; // @[dec_tlu_ctl.scala 813:15] wire csr_io_dec_tlu_icm_clk_override; // @[dec_tlu_ctl.scala 813:15] @@ -54643,6 +54653,7 @@ module dec_tlu_ctl( wire csr_io_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 813:15] wire csr_io_lsu_imprecise_error_store_any; // @[dec_tlu_ctl.scala 813:15] wire [31:0] csr_io_dec_tlu_mrac_ff; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_dec_tlu_wb_coalescing_disable; // @[dec_tlu_ctl.scala 813:15] wire csr_io_dec_tlu_bpred_disable; // @[dec_tlu_ctl.scala 813:15] wire csr_io_dec_tlu_sideeffect_posted_disable; // @[dec_tlu_ctl.scala 813:15] wire csr_io_dec_tlu_core_ecc_disable; // @[dec_tlu_ctl.scala 813:15] @@ -55708,7 +55719,6 @@ module dec_tlu_ctl( .io_dec_tlu_misc_clk_override(csr_io_dec_tlu_misc_clk_override), .io_dec_tlu_dec_clk_override(csr_io_dec_tlu_dec_clk_override), .io_dec_tlu_lsu_clk_override(csr_io_dec_tlu_lsu_clk_override), - .io_dec_tlu_bus_clk_override(csr_io_dec_tlu_bus_clk_override), .io_dec_tlu_pic_clk_override(csr_io_dec_tlu_pic_clk_override), .io_dec_tlu_dccm_clk_override(csr_io_dec_tlu_dccm_clk_override), .io_dec_tlu_icm_clk_override(csr_io_dec_tlu_icm_clk_override), @@ -55731,6 +55741,7 @@ module dec_tlu_ctl( .io_lsu_imprecise_error_load_any(csr_io_lsu_imprecise_error_load_any), .io_lsu_imprecise_error_store_any(csr_io_lsu_imprecise_error_store_any), .io_dec_tlu_mrac_ff(csr_io_dec_tlu_mrac_ff), + .io_dec_tlu_wb_coalescing_disable(csr_io_dec_tlu_wb_coalescing_disable), .io_dec_tlu_bpred_disable(csr_io_dec_tlu_bpred_disable), .io_dec_tlu_sideeffect_posted_disable(csr_io_dec_tlu_sideeffect_posted_disable), .io_dec_tlu_core_ecc_disable(csr_io_dec_tlu_core_ecc_disable), @@ -56032,7 +56043,6 @@ module dec_tlu_ctl( assign io_dec_tlu_misc_clk_override = csr_io_dec_tlu_misc_clk_override; // @[dec_tlu_ctl.scala 885:40] assign io_dec_tlu_dec_clk_override = csr_io_dec_tlu_dec_clk_override; // @[dec_tlu_ctl.scala 886:40] assign io_dec_tlu_lsu_clk_override = csr_io_dec_tlu_lsu_clk_override; // @[dec_tlu_ctl.scala 888:40] - assign io_dec_tlu_bus_clk_override = csr_io_dec_tlu_bus_clk_override; // @[dec_tlu_ctl.scala 889:40] assign io_dec_tlu_pic_clk_override = csr_io_dec_tlu_pic_clk_override; // @[dec_tlu_ctl.scala 890:40] assign io_dec_tlu_dccm_clk_override = csr_io_dec_tlu_dccm_clk_override; // @[dec_tlu_ctl.scala 891:40] assign io_dec_tlu_icm_clk_override = csr_io_dec_tlu_icm_clk_override; // @[dec_tlu_ctl.scala 892:40] @@ -56057,6 +56067,7 @@ module dec_tlu_ctl( assign io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wr_valid = csr_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[dec_tlu_ctl.scala 877:44] assign io_tlu_mem_dec_tlu_core_ecc_disable = csr_io_dec_tlu_core_ecc_disable; // @[dec_tlu_ctl.scala 900:48] assign io_tlu_busbuff_dec_tlu_external_ldfwd_disable = csr_io_dec_tlu_external_ldfwd_disable; // @[dec_tlu_ctl.scala 901:52] + assign io_tlu_busbuff_dec_tlu_wb_coalescing_disable = csr_io_dec_tlu_wb_coalescing_disable; // @[dec_tlu_ctl.scala 897:52] assign io_tlu_busbuff_dec_tlu_sideeffect_posted_disable = csr_io_dec_tlu_sideeffect_posted_disable; // @[dec_tlu_ctl.scala 899:52] assign io_dec_pic_dec_tlu_meicurpl = csr_io_dec_tlu_meicurpl; // @[dec_tlu_ctl.scala 871:44] assign io_dec_pic_dec_tlu_meipt = csr_io_dec_tlu_meipt; // @[dec_tlu_ctl.scala 873:44] @@ -57930,7 +57941,6 @@ module dec( output [31:0] io_rv_trace_pkt_rv_i_tval_ip, output io_dec_tlu_misc_clk_override, output io_dec_tlu_lsu_clk_override, - output io_dec_tlu_bus_clk_override, output io_dec_tlu_pic_clk_override, output io_dec_tlu_dccm_clk_override, output io_dec_tlu_icm_clk_override, @@ -58068,6 +58078,7 @@ module dec( input io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error, input io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy, output io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable, + output io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable, output io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable, input io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any, input io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any, @@ -58475,7 +58486,6 @@ module dec( wire tlu_io_dec_tlu_misc_clk_override; // @[dec.scala 120:19] wire tlu_io_dec_tlu_dec_clk_override; // @[dec.scala 120:19] wire tlu_io_dec_tlu_lsu_clk_override; // @[dec.scala 120:19] - wire tlu_io_dec_tlu_bus_clk_override; // @[dec.scala 120:19] wire tlu_io_dec_tlu_pic_clk_override; // @[dec.scala 120:19] wire tlu_io_dec_tlu_dccm_clk_override; // @[dec.scala 120:19] wire tlu_io_dec_tlu_icm_clk_override; // @[dec.scala 120:19] @@ -58516,6 +58526,7 @@ module dec( wire tlu_io_tlu_busbuff_lsu_pmu_bus_error; // @[dec.scala 120:19] wire tlu_io_tlu_busbuff_lsu_pmu_bus_busy; // @[dec.scala 120:19] wire tlu_io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[dec.scala 120:19] + wire tlu_io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[dec.scala 120:19] wire tlu_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[dec.scala 120:19] wire tlu_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[dec.scala 120:19] wire tlu_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[dec.scala 120:19] @@ -58931,7 +58942,6 @@ module dec( .io_dec_tlu_misc_clk_override(tlu_io_dec_tlu_misc_clk_override), .io_dec_tlu_dec_clk_override(tlu_io_dec_tlu_dec_clk_override), .io_dec_tlu_lsu_clk_override(tlu_io_dec_tlu_lsu_clk_override), - .io_dec_tlu_bus_clk_override(tlu_io_dec_tlu_bus_clk_override), .io_dec_tlu_pic_clk_override(tlu_io_dec_tlu_pic_clk_override), .io_dec_tlu_dccm_clk_override(tlu_io_dec_tlu_dccm_clk_override), .io_dec_tlu_icm_clk_override(tlu_io_dec_tlu_icm_clk_override), @@ -58972,6 +58982,7 @@ module dec( .io_tlu_busbuff_lsu_pmu_bus_error(tlu_io_tlu_busbuff_lsu_pmu_bus_error), .io_tlu_busbuff_lsu_pmu_bus_busy(tlu_io_tlu_busbuff_lsu_pmu_bus_busy), .io_tlu_busbuff_dec_tlu_external_ldfwd_disable(tlu_io_tlu_busbuff_dec_tlu_external_ldfwd_disable), + .io_tlu_busbuff_dec_tlu_wb_coalescing_disable(tlu_io_tlu_busbuff_dec_tlu_wb_coalescing_disable), .io_tlu_busbuff_dec_tlu_sideeffect_posted_disable(tlu_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable), .io_tlu_busbuff_lsu_imprecise_error_load_any(tlu_io_tlu_busbuff_lsu_imprecise_error_load_any), .io_tlu_busbuff_lsu_imprecise_error_store_any(tlu_io_tlu_busbuff_lsu_imprecise_error_store_any), @@ -59070,7 +59081,6 @@ module dec( assign io_rv_trace_pkt_rv_i_tval_ip = tlu_io_dec_tlu_mtval_wb1; // @[dec.scala 294:32] assign io_dec_tlu_misc_clk_override = tlu_io_dec_tlu_misc_clk_override; // @[dec.scala 278:35] assign io_dec_tlu_lsu_clk_override = tlu_io_dec_tlu_lsu_clk_override; // @[dec.scala 280:36] - assign io_dec_tlu_bus_clk_override = tlu_io_dec_tlu_bus_clk_override; // @[dec.scala 281:36] assign io_dec_tlu_pic_clk_override = tlu_io_dec_tlu_pic_clk_override; // @[dec.scala 282:36] assign io_dec_tlu_dccm_clk_override = tlu_io_dec_tlu_dccm_clk_override; // @[dec.scala 283:36] assign io_dec_tlu_icm_clk_override = tlu_io_dec_tlu_icm_clk_override; // @[dec.scala 284:36] @@ -59158,6 +59168,7 @@ module dec( assign io_dec_exu_gpr_exu_gpr_i0_rs1_d = gpr_io_gpr_exu_gpr_i0_rs1_d; // @[dec.scala 201:22] assign io_dec_exu_gpr_exu_gpr_i0_rs2_d = gpr_io_gpr_exu_gpr_i0_rs2_d; // @[dec.scala 201:22] assign io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable = tlu_io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[dec.scala 222:26] + assign io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable = tlu_io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[dec.scala 222:26] assign io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable = tlu_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[dec.scala 222:26] assign io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty = tlu_io_tlu_dma_dec_tlu_dma_qos_prty; // @[dec.scala 206:18] assign io_dec_pic_dec_tlu_meicurpl = tlu_io_dec_pic_dec_tlu_meicurpl; // @[dec.scala 224:14] @@ -59407,6 +59418,7 @@ module dbg( input io_sb_axi_aw_ready, output io_sb_axi_aw_valid, output [31:0] io_sb_axi_aw_bits_addr, + output [3:0] io_sb_axi_aw_bits_region, output [2:0] io_sb_axi_aw_bits_size, input io_sb_axi_w_ready, output io_sb_axi_w_valid, @@ -59418,6 +59430,7 @@ module dbg( input io_sb_axi_ar_ready, output io_sb_axi_ar_valid, output [31:0] io_sb_axi_ar_bits_addr, + output [3:0] io_sb_axi_ar_bits_region, output [2:0] io_sb_axi_ar_bits_size, output io_sb_axi_r_ready, input io_sb_axi_r_valid, @@ -60010,6 +60023,7 @@ module dbg( assign io_dmi_reg_rdata = _T_467; // @[dbg.scala 325:20] assign io_sb_axi_aw_valid = _T_558 | _T_559; // @[dbg.scala 412:22] assign io_sb_axi_aw_bits_addr = sbaddress0_reg; // @[dbg.scala 413:26] + assign io_sb_axi_aw_bits_region = sbaddress0_reg[31:28]; // @[dbg.scala 418:28] assign io_sb_axi_aw_bits_size = sbcs_reg[19:17]; // @[dbg.scala 415:26] assign io_sb_axi_w_valid = _T_558 | _T_565; // @[dbg.scala 423:21] assign io_sb_axi_w_bits_data = _T_593 | _T_601; // @[dbg.scala 424:25] @@ -60017,6 +60031,7 @@ module dbg( assign io_sb_axi_b_ready = 1'h1; // @[dbg.scala 444:21] assign io_sb_axi_ar_valid = sb_state == 4'h3; // @[dbg.scala 433:22] assign io_sb_axi_ar_bits_addr = sbaddress0_reg; // @[dbg.scala 434:26] + assign io_sb_axi_ar_bits_region = sbaddress0_reg[31:28]; // @[dbg.scala 439:28] assign io_sb_axi_ar_bits_size = sbcs_reg[19:17]; // @[dbg.scala 436:26] assign io_sb_axi_r_ready = 1'h1; // @[dbg.scala 445:21] assign io_dbg_dec_dbg_ib_dbg_cmd_valid = _T_480 & io_dbg_dma_io_dma_dbg_ready; // @[dbg.scala 331:35] @@ -68176,6 +68191,7 @@ module lsu_bus_buffer( output io_tlu_busbuff_lsu_pmu_bus_error, output io_tlu_busbuff_lsu_pmu_bus_busy, input io_tlu_busbuff_dec_tlu_external_ldfwd_disable, + input io_tlu_busbuff_dec_tlu_wb_coalescing_disable, input io_tlu_busbuff_dec_tlu_sideeffect_posted_disable, output io_tlu_busbuff_lsu_imprecise_error_load_any, output io_tlu_busbuff_lsu_imprecise_error_store_any, @@ -68225,7 +68241,9 @@ module lsu_bus_buffer( output io_lsu_axi_aw_valid, output [2:0] io_lsu_axi_aw_bits_id, output [31:0] io_lsu_axi_aw_bits_addr, + output [3:0] io_lsu_axi_aw_bits_region, output [2:0] io_lsu_axi_aw_bits_size, + output [3:0] io_lsu_axi_aw_bits_cache, input io_lsu_axi_w_ready, output io_lsu_axi_w_valid, output [63:0] io_lsu_axi_w_bits_data, @@ -68238,7 +68256,9 @@ module lsu_bus_buffer( output io_lsu_axi_ar_valid, output [2:0] io_lsu_axi_ar_bits_id, output [31:0] io_lsu_axi_ar_bits_addr, + output [3:0] io_lsu_axi_ar_bits_region, output [2:0] io_lsu_axi_ar_bits_size, + output [3:0] io_lsu_axi_ar_bits_cache, output io_lsu_axi_r_ready, input io_lsu_axi_r_valid, input [2:0] io_lsu_axi_r_bits_id, @@ -68334,9 +68354,9 @@ module lsu_bus_buffer( reg [31:0] _RAND_75; reg [31:0] _RAND_76; reg [31:0] _RAND_77; - reg [63:0] _RAND_78; + reg [31:0] _RAND_78; reg [31:0] _RAND_79; - reg [31:0] _RAND_80; + reg [63:0] _RAND_80; reg [31:0] _RAND_81; reg [31:0] _RAND_82; reg [31:0] _RAND_83; @@ -68361,6 +68381,8 @@ module lsu_bus_buffer( reg [31:0] _RAND_102; reg [31:0] _RAND_103; reg [31:0] _RAND_104; + reg [31:0] _RAND_105; + reg [31:0] _RAND_106; `endif // RANDOMIZE_REG_INIT wire rvclkhdr_io_l1clk; // @[lib.scala 368:23] wire rvclkhdr_io_clk; // @[lib.scala 368:23] @@ -69034,26 +69056,74 @@ module lsu_bus_buffer( wire _T_854 = ~ibuf_byp; // @[lsu_bus_buffer.scala 208:56] wire ibuf_wr_en = _T_853 & _T_854; // @[lsu_bus_buffer.scala 208:54] wire _T_855 = ~ibuf_wr_en; // @[lsu_bus_buffer.scala 210:36] + reg [2:0] ibuf_timer; // @[lsu_bus_buffer.scala 253:55] + wire _T_864 = ibuf_timer == 3'h7; // @[lsu_bus_buffer.scala 216:62] + wire _T_865 = ibuf_wr_en | _T_864; // @[lsu_bus_buffer.scala 216:48] + wire _T_929 = _T_853 & io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 235:54] + wire _T_930 = _T_929 & ibuf_valid; // @[lsu_bus_buffer.scala 235:80] + wire _T_931 = _T_930 & ibuf_write; // @[lsu_bus_buffer.scala 235:93] + wire _T_934 = io_lsu_addr_r[31:2] == ibuf_addr[31:2]; // @[lsu_bus_buffer.scala 235:129] + wire _T_935 = _T_931 & _T_934; // @[lsu_bus_buffer.scala 235:106] + wire _T_936 = ~io_is_sideeffects_r; // @[lsu_bus_buffer.scala 235:152] + wire _T_937 = _T_935 & _T_936; // @[lsu_bus_buffer.scala 235:150] + wire _T_938 = ~io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_buffer.scala 235:175] + wire ibuf_merge_en = _T_937 & _T_938; // @[lsu_bus_buffer.scala 235:173] + wire ibuf_merge_in = ~io_ldst_dual_r; // @[lsu_bus_buffer.scala 236:20] + wire _T_866 = ibuf_merge_en & ibuf_merge_in; // @[lsu_bus_buffer.scala 216:98] + wire _T_867 = ~_T_866; // @[lsu_bus_buffer.scala 216:82] + wire _T_868 = _T_865 & _T_867; // @[lsu_bus_buffer.scala 216:80] + wire _T_869 = _T_868 | ibuf_byp; // @[lsu_bus_buffer.scala 217:5] wire _T_857 = ~io_lsu_busreq_r; // @[lsu_bus_buffer.scala 211:44] wire _T_858 = io_lsu_busreq_m & _T_857; // @[lsu_bus_buffer.scala 211:42] wire _T_859 = _T_858 & ibuf_valid; // @[lsu_bus_buffer.scala 211:61] wire _T_862 = ibuf_addr[31:2] != io_lsu_addr_m[31:2]; // @[lsu_bus_buffer.scala 211:120] wire _T_863 = io_lsu_pkt_m_bits_load | _T_862; // @[lsu_bus_buffer.scala 211:100] wire ibuf_force_drain = _T_859 & _T_863; // @[lsu_bus_buffer.scala 211:74] + wire _T_870 = _T_869 | ibuf_force_drain; // @[lsu_bus_buffer.scala 217:16] reg ibuf_sideeffect; // @[Reg.scala 27:20] - wire _T_856 = ibuf_valid & _T_855; // @[lsu_bus_buffer.scala 210:34] + wire _T_871 = _T_870 | ibuf_sideeffect; // @[lsu_bus_buffer.scala 217:35] + wire _T_872 = ~ibuf_write; // @[lsu_bus_buffer.scala 217:55] + wire _T_873 = _T_871 | _T_872; // @[lsu_bus_buffer.scala 217:53] + wire _T_874 = _T_873 | io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_buffer.scala 217:67] + wire ibuf_drain_vld = ibuf_valid & _T_874; // @[lsu_bus_buffer.scala 216:32] + wire _T_856 = ibuf_drain_vld & _T_855; // @[lsu_bus_buffer.scala 210:34] wire ibuf_rst = _T_856 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 210:49] reg [1:0] WrPtr1_r; // @[lsu_bus_buffer.scala 616:49] reg [1:0] WrPtr0_r; // @[lsu_bus_buffer.scala 615:49] reg [1:0] ibuf_tag; // @[Reg.scala 27:20] wire [1:0] ibuf_sz_in = {io_lsu_pkt_r_bits_word,io_lsu_pkt_r_bits_half}; // @[Cat.scala 29:58] + wire [3:0] _T_881 = ibuf_byteen | ldst_byteen_lo_r; // @[lsu_bus_buffer.scala 226:77] + wire [7:0] _T_889 = ldst_byteen_lo_r[0] ? store_data_lo_r[7:0] : ibuf_data[7:0]; // @[lsu_bus_buffer.scala 231:8] wire [7:0] _T_892 = io_ldst_dual_r ? store_data_hi_r[7:0] : store_data_lo_r[7:0]; // @[lsu_bus_buffer.scala 232:8] + wire [7:0] _T_893 = _T_866 ? _T_889 : _T_892; // @[lsu_bus_buffer.scala 230:46] + wire [7:0] _T_898 = ldst_byteen_lo_r[1] ? store_data_lo_r[15:8] : ibuf_data[15:8]; // @[lsu_bus_buffer.scala 231:8] wire [7:0] _T_901 = io_ldst_dual_r ? store_data_hi_r[15:8] : store_data_lo_r[15:8]; // @[lsu_bus_buffer.scala 232:8] + wire [7:0] _T_902 = _T_866 ? _T_898 : _T_901; // @[lsu_bus_buffer.scala 230:46] + wire [7:0] _T_907 = ldst_byteen_lo_r[2] ? store_data_lo_r[23:16] : ibuf_data[23:16]; // @[lsu_bus_buffer.scala 231:8] wire [7:0] _T_910 = io_ldst_dual_r ? store_data_hi_r[23:16] : store_data_lo_r[23:16]; // @[lsu_bus_buffer.scala 232:8] + wire [7:0] _T_911 = _T_866 ? _T_907 : _T_910; // @[lsu_bus_buffer.scala 230:46] + wire [7:0] _T_916 = ldst_byteen_lo_r[3] ? store_data_lo_r[31:24] : ibuf_data[31:24]; // @[lsu_bus_buffer.scala 231:8] wire [7:0] _T_919 = io_ldst_dual_r ? store_data_hi_r[31:24] : store_data_lo_r[31:24]; // @[lsu_bus_buffer.scala 232:8] - wire [23:0] _T_922 = {_T_919,_T_910,_T_901}; // @[Cat.scala 29:58] - wire [3:0] ibuf_byteen_out = {ibuf_byteen[3],ibuf_byteen[2],ibuf_byteen[1],ibuf_byteen[0]}; // @[Cat.scala 29:58] - wire [31:0] ibuf_data_out = {ibuf_data[31:24],ibuf_data[23:16],ibuf_data[15:8],ibuf_data[7:0]}; // @[Cat.scala 29:58] + wire [7:0] _T_920 = _T_866 ? _T_916 : _T_919; // @[lsu_bus_buffer.scala 230:46] + wire [23:0] _T_922 = {_T_920,_T_911,_T_902}; // @[Cat.scala 29:58] + wire _T_923 = ibuf_timer < 3'h7; // @[lsu_bus_buffer.scala 233:59] + wire [2:0] _T_926 = ibuf_timer + 3'h1; // @[lsu_bus_buffer.scala 233:93] + wire _T_941 = ~ibuf_merge_in; // @[lsu_bus_buffer.scala 237:65] + wire _T_942 = ibuf_merge_en & _T_941; // @[lsu_bus_buffer.scala 237:63] + wire _T_945 = ibuf_byteen[0] | ldst_byteen_lo_r[0]; // @[lsu_bus_buffer.scala 237:96] + wire _T_947 = _T_942 ? _T_945 : ibuf_byteen[0]; // @[lsu_bus_buffer.scala 237:48] + wire _T_952 = ibuf_byteen[1] | ldst_byteen_lo_r[1]; // @[lsu_bus_buffer.scala 237:96] + wire _T_954 = _T_942 ? _T_952 : ibuf_byteen[1]; // @[lsu_bus_buffer.scala 237:48] + wire _T_959 = ibuf_byteen[2] | ldst_byteen_lo_r[2]; // @[lsu_bus_buffer.scala 237:96] + wire _T_961 = _T_942 ? _T_959 : ibuf_byteen[2]; // @[lsu_bus_buffer.scala 237:48] + wire _T_966 = ibuf_byteen[3] | ldst_byteen_lo_r[3]; // @[lsu_bus_buffer.scala 237:96] + wire _T_968 = _T_942 ? _T_966 : ibuf_byteen[3]; // @[lsu_bus_buffer.scala 237:48] + wire [3:0] ibuf_byteen_out = {_T_968,_T_961,_T_954,_T_947}; // @[Cat.scala 29:58] + wire [7:0] _T_978 = _T_942 ? _T_889 : ibuf_data[7:0]; // @[lsu_bus_buffer.scala 238:45] + wire [7:0] _T_986 = _T_942 ? _T_898 : ibuf_data[15:8]; // @[lsu_bus_buffer.scala 238:45] + wire [7:0] _T_994 = _T_942 ? _T_907 : ibuf_data[23:16]; // @[lsu_bus_buffer.scala 238:45] + wire [7:0] _T_1002 = _T_942 ? _T_916 : ibuf_data[31:24]; // @[lsu_bus_buffer.scala 238:45] + wire [31:0] ibuf_data_out = {_T_1002,_T_994,_T_986,_T_978}; // @[Cat.scala 29:58] wire _T_1005 = ibuf_wr_en | ibuf_valid; // @[lsu_bus_buffer.scala 240:58] wire _T_1006 = ~ibuf_rst; // @[lsu_bus_buffer.scala 240:93] reg [1:0] ibuf_dualtag; // @[Reg.scala 27:20] @@ -69062,10 +69132,24 @@ module lsu_bus_buffer( reg ibuf_nomerge; // @[Reg.scala 27:20] reg ibuf_unsign; // @[Reg.scala 27:20] reg [1:0] ibuf_sz; // @[Reg.scala 27:20] + wire _T_4446 = buf_write[3] & _T_2621; // @[lsu_bus_buffer.scala 522:64] wire _T_4447 = ~buf_cmd_state_bus_en_3; // @[lsu_bus_buffer.scala 522:91] + wire _T_4448 = _T_4446 & _T_4447; // @[lsu_bus_buffer.scala 522:89] + wire _T_4441 = buf_write[2] & _T_2616; // @[lsu_bus_buffer.scala 522:64] wire _T_4442 = ~buf_cmd_state_bus_en_2; // @[lsu_bus_buffer.scala 522:91] + wire _T_4443 = _T_4441 & _T_4442; // @[lsu_bus_buffer.scala 522:89] + wire [1:0] _T_4449 = _T_4448 + _T_4443; // @[lsu_bus_buffer.scala 522:142] + wire _T_4436 = buf_write[1] & _T_2611; // @[lsu_bus_buffer.scala 522:64] wire _T_4437 = ~buf_cmd_state_bus_en_1; // @[lsu_bus_buffer.scala 522:91] + wire _T_4438 = _T_4436 & _T_4437; // @[lsu_bus_buffer.scala 522:89] + wire [1:0] _GEN_362 = {{1'd0}, _T_4438}; // @[lsu_bus_buffer.scala 522:142] + wire [2:0] _T_4450 = _T_4449 + _GEN_362; // @[lsu_bus_buffer.scala 522:142] + wire _T_4431 = buf_write[0] & _T_2606; // @[lsu_bus_buffer.scala 522:64] wire _T_4432 = ~buf_cmd_state_bus_en_0; // @[lsu_bus_buffer.scala 522:91] + wire _T_4433 = _T_4431 & _T_4432; // @[lsu_bus_buffer.scala 522:89] + wire [2:0] _GEN_363 = {{2'd0}, _T_4433}; // @[lsu_bus_buffer.scala 522:142] + wire [3:0] buf_numvld_wrcmd_any = _T_4450 + _GEN_363; // @[lsu_bus_buffer.scala 522:142] + wire _T_1016 = buf_numvld_wrcmd_any == 4'h1; // @[lsu_bus_buffer.scala 263:43] wire _T_4463 = _T_2621 & _T_4447; // @[lsu_bus_buffer.scala 523:73] wire _T_4460 = _T_2616 & _T_4442; // @[lsu_bus_buffer.scala 523:73] wire [1:0] _T_4464 = _T_4463 + _T_4460; // @[lsu_bus_buffer.scala 523:126] @@ -69076,6 +69160,11 @@ module lsu_bus_buffer( wire [2:0] _GEN_365 = {{2'd0}, _T_4454}; // @[lsu_bus_buffer.scala 523:126] wire [3:0] buf_numvld_cmd_any = _T_4465 + _GEN_365; // @[lsu_bus_buffer.scala 523:126] wire _T_1017 = buf_numvld_cmd_any == 4'h1; // @[lsu_bus_buffer.scala 263:72] + wire _T_1018 = _T_1016 & _T_1017; // @[lsu_bus_buffer.scala 263:51] + reg [2:0] obuf_wr_timer; // @[lsu_bus_buffer.scala 361:54] + wire _T_1019 = obuf_wr_timer != 3'h7; // @[lsu_bus_buffer.scala 263:97] + wire _T_1020 = _T_1018 & _T_1019; // @[lsu_bus_buffer.scala 263:80] + wire _T_1022 = _T_1020 & _T_938; // @[lsu_bus_buffer.scala 263:114] wire _T_1979 = |buf_age_3; // @[lsu_bus_buffer.scala 378:58] wire _T_1980 = ~_T_1979; // @[lsu_bus_buffer.scala 378:45] wire _T_1982 = _T_1980 & _T_2621; // @[lsu_bus_buffer.scala 378:63] @@ -69110,9 +69199,18 @@ module lsu_bus_buffer( wire _T_1025 = CmdPtr0 == 2'h2; // @[lsu_bus_buffer.scala 264:114] wire _T_1026 = CmdPtr0 == 2'h3; // @[lsu_bus_buffer.scala 264:114] reg buf_nomerge_0; // @[Reg.scala 27:20] + wire _T_1027 = _T_1023 & buf_nomerge_0; // @[Mux.scala 27:72] reg buf_nomerge_1; // @[Reg.scala 27:20] + wire _T_1028 = _T_1024 & buf_nomerge_1; // @[Mux.scala 27:72] reg buf_nomerge_2; // @[Reg.scala 27:20] + wire _T_1029 = _T_1025 & buf_nomerge_2; // @[Mux.scala 27:72] reg buf_nomerge_3; // @[Reg.scala 27:20] + wire _T_1030 = _T_1026 & buf_nomerge_3; // @[Mux.scala 27:72] + wire _T_1031 = _T_1027 | _T_1028; // @[Mux.scala 27:72] + wire _T_1032 = _T_1031 | _T_1029; // @[Mux.scala 27:72] + wire _T_1033 = _T_1032 | _T_1030; // @[Mux.scala 27:72] + wire _T_1035 = ~_T_1033; // @[lsu_bus_buffer.scala 264:31] + wire _T_1036 = _T_1022 & _T_1035; // @[lsu_bus_buffer.scala 264:29] reg _T_4330; // @[Reg.scala 27:20] reg _T_4327; // @[Reg.scala 27:20] reg _T_4324; // @[Reg.scala 27:20] @@ -69126,6 +69224,7 @@ module lsu_bus_buffer( wire _T_1050 = _T_1049 | _T_1047; // @[Mux.scala 27:72] wire _T_1051 = _T_1050 | _T_1048; // @[Mux.scala 27:72] wire _T_1053 = ~_T_1051; // @[lsu_bus_buffer.scala 265:5] + wire _T_1054 = _T_1036 & _T_1053; // @[lsu_bus_buffer.scala 264:140] wire _T_1065 = _T_858 & _T_852; // @[lsu_bus_buffer.scala 267:58] wire _T_1067 = _T_1065 & _T_1017; // @[lsu_bus_buffer.scala 267:72] wire [29:0] _T_1077 = _T_1023 ? buf_addr_0[31:2] : 30'h0; // @[Mux.scala 27:72] @@ -69137,6 +69236,12 @@ module lsu_bus_buffer( wire [29:0] _T_1083 = _T_1082 | _T_1080; // @[Mux.scala 27:72] wire _T_1085 = io_lsu_addr_m[31:2] != _T_1083; // @[lsu_bus_buffer.scala 267:123] wire obuf_force_wr_en = _T_1067 & _T_1085; // @[lsu_bus_buffer.scala 267:101] + wire _T_1055 = ~obuf_force_wr_en; // @[lsu_bus_buffer.scala 265:119] + wire obuf_wr_wait = _T_1054 & _T_1055; // @[lsu_bus_buffer.scala 265:117] + wire _T_1056 = |buf_numvld_cmd_any; // @[lsu_bus_buffer.scala 266:75] + wire _T_1057 = obuf_wr_timer < 3'h7; // @[lsu_bus_buffer.scala 266:95] + wire _T_1058 = _T_1056 & _T_1057; // @[lsu_bus_buffer.scala 266:79] + wire [2:0] _T_1060 = obuf_wr_timer + 3'h1; // @[lsu_bus_buffer.scala 266:123] wire _T_4482 = buf_state_3 == 3'h1; // @[lsu_bus_buffer.scala 524:63] wire _T_4486 = _T_4482 | _T_4463; // @[lsu_bus_buffer.scala 524:74] wire _T_4477 = buf_state_2 == 3'h1; // @[lsu_bus_buffer.scala 524:63] @@ -69293,6 +69398,8 @@ module lsu_bus_buffer( reg obuf_nosend; // @[Reg.scala 27:20] wire _T_1233 = _T_1232 | obuf_nosend; // @[lsu_bus_buffer.scala 288:60] wire _T_1234 = _T_1230 & _T_1233; // @[lsu_bus_buffer.scala 288:29] + wire _T_1235 = ~obuf_wr_wait; // @[lsu_bus_buffer.scala 288:77] + wire _T_1236 = _T_1234 & _T_1235; // @[lsu_bus_buffer.scala 288:75] reg [31:0] obuf_addr; // @[lib.scala 374:16] wire _T_4804 = obuf_addr[31:3] == buf_addr_0[31:3]; // @[lsu_bus_buffer.scala 554:56] wire _T_4805 = obuf_valid & _T_4804; // @[lsu_bus_buffer.scala 554:38] @@ -69330,7 +69437,7 @@ module lsu_bus_buffer( wire _T_4851 = _T_4790 & _T_4847; // @[Mux.scala 27:72] wire bus_addr_match_pending = _T_4853 | _T_4851; // @[Mux.scala 27:72] wire _T_1239 = ~bus_addr_match_pending; // @[lsu_bus_buffer.scala 288:118] - wire _T_1240 = _T_1234 & _T_1239; // @[lsu_bus_buffer.scala 288:116] + wire _T_1240 = _T_1236 & _T_1239; // @[lsu_bus_buffer.scala 288:116] wire obuf_wr_en = _T_1240 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 288:142] wire _T_1242 = obuf_valid & obuf_nosend; // @[lsu_bus_buffer.scala 290:47] wire bus_wcmd_sent = io_lsu_axi_aw_valid & io_lsu_axi_aw_ready; // @[lsu_bus_buffer.scala 557:40] @@ -69586,7 +69693,6 @@ module lsu_bus_buffer( wire _T_1885 = _T_1875 & _T_1884; // @[lsu_bus_buffer.scala 364:76] wire _T_1886 = buf_state_3 == 3'h0; // @[lsu_bus_buffer.scala 364:65] wire _T_1887 = ibuf_tag == 2'h3; // @[lsu_bus_buffer.scala 365:30] - wire _T_1888 = ibuf_valid & _T_1887; // @[lsu_bus_buffer.scala 365:19] wire _T_1889 = WrPtr0_r == 2'h3; // @[lsu_bus_buffer.scala 366:18] wire _T_1890 = WrPtr1_r == 2'h3; // @[lsu_bus_buffer.scala 366:57] wire [1:0] _T_1898 = _T_1885 ? 2'h2 : 2'h3; // @[Mux.scala 98:16] @@ -69662,15 +69768,17 @@ module lsu_bus_buffer( wire _T_2125 = _T_2123 | _T_2104[7]; // @[lsu_bus_buffer.scala 386:104] wire [2:0] _T_2127 = {_T_2111,_T_2118,_T_2125}; // @[Cat.scala 29:58] wire _T_3532 = ibuf_byp | io_ldst_dual_r; // @[lsu_bus_buffer.scala 444:77] + wire _T_3533 = ~ibuf_merge_en; // @[lsu_bus_buffer.scala 444:97] + wire _T_3534 = _T_3532 & _T_3533; // @[lsu_bus_buffer.scala 444:95] wire _T_3535 = 2'h0 == WrPtr0_r; // @[lsu_bus_buffer.scala 444:117] - wire _T_3536 = _T_3532 & _T_3535; // @[lsu_bus_buffer.scala 444:112] + wire _T_3536 = _T_3534 & _T_3535; // @[lsu_bus_buffer.scala 444:112] wire _T_3537 = ibuf_byp & io_ldst_dual_r; // @[lsu_bus_buffer.scala 444:144] wire _T_3538 = 2'h0 == WrPtr1_r; // @[lsu_bus_buffer.scala 444:166] wire _T_3539 = _T_3537 & _T_3538; // @[lsu_bus_buffer.scala 444:161] wire _T_3540 = _T_3536 | _T_3539; // @[lsu_bus_buffer.scala 444:132] wire _T_3541 = _T_853 & _T_3540; // @[lsu_bus_buffer.scala 444:63] wire _T_3542 = 2'h0 == ibuf_tag; // @[lsu_bus_buffer.scala 444:206] - wire _T_3543 = ibuf_valid & _T_3542; // @[lsu_bus_buffer.scala 444:201] + wire _T_3543 = ibuf_drain_vld & _T_3542; // @[lsu_bus_buffer.scala 444:201] wire _T_3544 = _T_3541 | _T_3543; // @[lsu_bus_buffer.scala 444:183] wire _T_3554 = io_lsu_bus_clk_en | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 451:46] wire _T_3589 = 3'h3 == buf_state_0; // @[Conditional.scala 37:30] @@ -69738,7 +69846,7 @@ module lsu_bus_buffer( wire _GEN_64 = _T_3551 ? _T_3554 : _GEN_54; // @[Conditional.scala 39:67] wire buf_state_en_0 = _T_3528 ? _T_3544 : _GEN_64; // @[Conditional.scala 40:58] wire _T_2129 = _T_1853 & buf_state_en_0; // @[lsu_bus_buffer.scala 406:94] - wire _T_2135 = ibuf_valid & io_lsu_busreq_r; // @[lsu_bus_buffer.scala 408:23] + wire _T_2135 = ibuf_drain_vld & io_lsu_busreq_r; // @[lsu_bus_buffer.scala 408:23] wire _T_2137 = _T_2135 & _T_3532; // @[lsu_bus_buffer.scala 408:41] wire _T_2139 = _T_2137 & _T_1856; // @[lsu_bus_buffer.scala 408:71] wire _T_2141 = _T_2139 & _T_1854; // @[lsu_bus_buffer.scala 408:92] @@ -69770,13 +69878,13 @@ module lsu_bus_buffer( wire _T_2227 = _T_2225 | buf_age_0[3]; // @[lsu_bus_buffer.scala 409:97] wire [2:0] _T_2229 = {_T_2227,_T_2202,_T_2177}; // @[Cat.scala 29:58] wire _T_3728 = 2'h1 == WrPtr0_r; // @[lsu_bus_buffer.scala 444:117] - wire _T_3729 = _T_3532 & _T_3728; // @[lsu_bus_buffer.scala 444:112] + wire _T_3729 = _T_3534 & _T_3728; // @[lsu_bus_buffer.scala 444:112] wire _T_3731 = 2'h1 == WrPtr1_r; // @[lsu_bus_buffer.scala 444:166] wire _T_3732 = _T_3537 & _T_3731; // @[lsu_bus_buffer.scala 444:161] wire _T_3733 = _T_3729 | _T_3732; // @[lsu_bus_buffer.scala 444:132] wire _T_3734 = _T_853 & _T_3733; // @[lsu_bus_buffer.scala 444:63] wire _T_3735 = 2'h1 == ibuf_tag; // @[lsu_bus_buffer.scala 444:206] - wire _T_3736 = ibuf_valid & _T_3735; // @[lsu_bus_buffer.scala 444:201] + wire _T_3736 = ibuf_drain_vld & _T_3735; // @[lsu_bus_buffer.scala 444:201] wire _T_3737 = _T_3734 | _T_3736; // @[lsu_bus_buffer.scala 444:183] wire _T_3782 = 3'h3 == buf_state_1; // @[Conditional.scala 37:30] wire _T_3827 = io_lsu_axi_b_bits_id == 3'h1; // @[lsu_bus_buffer.scala 469:73] @@ -69860,13 +69968,13 @@ module lsu_bus_buffer( wire _T_2329 = _T_2327 | buf_age_1[3]; // @[lsu_bus_buffer.scala 409:97] wire [2:0] _T_2331 = {_T_2329,_T_2304,_T_2279}; // @[Cat.scala 29:58] wire _T_3921 = 2'h2 == WrPtr0_r; // @[lsu_bus_buffer.scala 444:117] - wire _T_3922 = _T_3532 & _T_3921; // @[lsu_bus_buffer.scala 444:112] + wire _T_3922 = _T_3534 & _T_3921; // @[lsu_bus_buffer.scala 444:112] wire _T_3924 = 2'h2 == WrPtr1_r; // @[lsu_bus_buffer.scala 444:166] wire _T_3925 = _T_3537 & _T_3924; // @[lsu_bus_buffer.scala 444:161] wire _T_3926 = _T_3922 | _T_3925; // @[lsu_bus_buffer.scala 444:132] wire _T_3927 = _T_853 & _T_3926; // @[lsu_bus_buffer.scala 444:63] wire _T_3928 = 2'h2 == ibuf_tag; // @[lsu_bus_buffer.scala 444:206] - wire _T_3929 = ibuf_valid & _T_3928; // @[lsu_bus_buffer.scala 444:201] + wire _T_3929 = ibuf_drain_vld & _T_3928; // @[lsu_bus_buffer.scala 444:201] wire _T_3930 = _T_3927 | _T_3929; // @[lsu_bus_buffer.scala 444:183] wire _T_3975 = 3'h3 == buf_state_2; // @[Conditional.scala 37:30] wire _T_4020 = io_lsu_axi_b_bits_id == 3'h2; // @[lsu_bus_buffer.scala 469:73] @@ -69950,13 +70058,13 @@ module lsu_bus_buffer( wire _T_2431 = _T_2429 | buf_age_2[3]; // @[lsu_bus_buffer.scala 409:97] wire [2:0] _T_2433 = {_T_2431,_T_2406,_T_2381}; // @[Cat.scala 29:58] wire _T_4114 = 2'h3 == WrPtr0_r; // @[lsu_bus_buffer.scala 444:117] - wire _T_4115 = _T_3532 & _T_4114; // @[lsu_bus_buffer.scala 444:112] + wire _T_4115 = _T_3534 & _T_4114; // @[lsu_bus_buffer.scala 444:112] wire _T_4117 = 2'h3 == WrPtr1_r; // @[lsu_bus_buffer.scala 444:166] wire _T_4118 = _T_3537 & _T_4117; // @[lsu_bus_buffer.scala 444:161] wire _T_4119 = _T_4115 | _T_4118; // @[lsu_bus_buffer.scala 444:132] wire _T_4120 = _T_853 & _T_4119; // @[lsu_bus_buffer.scala 444:63] wire _T_4121 = 2'h3 == ibuf_tag; // @[lsu_bus_buffer.scala 444:206] - wire _T_4122 = ibuf_valid & _T_4121; // @[lsu_bus_buffer.scala 444:201] + wire _T_4122 = ibuf_drain_vld & _T_4121; // @[lsu_bus_buffer.scala 444:201] wire _T_4123 = _T_4120 | _T_4122; // @[lsu_bus_buffer.scala 444:183] wire _T_4168 = 3'h3 == buf_state_3; // @[Conditional.scala 37:30] wire _T_4213 = io_lsu_axi_b_bits_id == 3'h3; // @[lsu_bus_buffer.scala 469:73] @@ -70151,7 +70259,11 @@ module lsu_bus_buffer( wire _T_3213 = buf_rspage_set_3[2] | buf_rspage_3[2]; // @[lsu_bus_buffer.scala 420:88] wire _T_3216 = buf_rspage_set_3[3] | buf_rspage_3[3]; // @[lsu_bus_buffer.scala 420:88] wire [2:0] _T_3218 = {_T_3216,_T_3213,_T_3210}; // @[Cat.scala 29:58] - wire [3:0] ibuf_drainvec_vld = {_T_1888,_T_1877,_T_1866,_T_1855}; // @[Cat.scala 29:58] + wire _T_3329 = ibuf_drain_vld & _T_1854; // @[lsu_bus_buffer.scala 426:63] + wire _T_3331 = ibuf_drain_vld & _T_1865; // @[lsu_bus_buffer.scala 426:63] + wire _T_3333 = ibuf_drain_vld & _T_1876; // @[lsu_bus_buffer.scala 426:63] + wire _T_3335 = ibuf_drain_vld & _T_1887; // @[lsu_bus_buffer.scala 426:63] + wire [3:0] ibuf_drainvec_vld = {_T_3335,_T_3333,_T_3331,_T_3329}; // @[Cat.scala 29:58] wire _T_3343 = _T_3537 & _T_1857; // @[lsu_bus_buffer.scala 428:35] wire _T_3352 = _T_3537 & _T_1868; // @[lsu_bus_buffer.scala 428:35] wire _T_3361 = _T_3537 & _T_1879; // @[lsu_bus_buffer.scala 428:35] @@ -70774,7 +70886,9 @@ module lsu_bus_buffer( assign io_lsu_axi_aw_valid = _T_4876 & _T_1239; // @[lsu_bus_buffer.scala 569:23] assign io_lsu_axi_aw_bits_id = {{1'd0}, _T_1848}; // @[lsu_bus_buffer.scala 570:25] assign io_lsu_axi_aw_bits_addr = obuf_sideeffect ? obuf_addr : _T_4880; // @[lsu_bus_buffer.scala 571:27] + assign io_lsu_axi_aw_bits_region = obuf_addr[31:28]; // @[lsu_bus_buffer.scala 575:29] assign io_lsu_axi_aw_bits_size = obuf_sideeffect ? _T_4882 : 3'h3; // @[lsu_bus_buffer.scala 572:27] + assign io_lsu_axi_aw_bits_cache = obuf_sideeffect ? 4'h0 : 4'hf; // @[lsu_bus_buffer.scala 574:28] assign io_lsu_axi_w_valid = _T_4888 & _T_1239; // @[lsu_bus_buffer.scala 581:22] assign io_lsu_axi_w_bits_data = obuf_data; // @[lsu_bus_buffer.scala 583:26] assign io_lsu_axi_w_bits_strb = obuf_byteen & _T_4892; // @[lsu_bus_buffer.scala 582:26] @@ -70782,7 +70896,9 @@ module lsu_bus_buffer( assign io_lsu_axi_ar_valid = _T_4897 & _T_1239; // @[lsu_bus_buffer.scala 586:23] assign io_lsu_axi_ar_bits_id = {{1'd0}, _T_1848}; // @[lsu_bus_buffer.scala 587:25] assign io_lsu_axi_ar_bits_addr = obuf_sideeffect ? obuf_addr : _T_4880; // @[lsu_bus_buffer.scala 588:27] + assign io_lsu_axi_ar_bits_region = obuf_addr[31:28]; // @[lsu_bus_buffer.scala 592:29] assign io_lsu_axi_ar_bits_size = obuf_sideeffect ? _T_4882 : 3'h3; // @[lsu_bus_buffer.scala 589:27] + assign io_lsu_axi_ar_bits_cache = obuf_sideeffect ? 4'h0 : 4'hf; // @[lsu_bus_buffer.scala 591:28] assign io_lsu_axi_r_ready = 1'h1; // @[lsu_bus_buffer.scala 598:22] assign io_lsu_busreq_r = _T_4987; // @[lsu_bus_buffer.scala 617:19] assign io_lsu_bus_buffer_pend_any = |buf_numvld_pend_any; // @[lsu_bus_buffer.scala 526:30] @@ -70932,147 +71048,151 @@ initial begin _RAND_33 = {1{`RANDOM}}; ibuf_data = _RAND_33[31:0]; _RAND_34 = {1{`RANDOM}}; - ibuf_sideeffect = _RAND_34[0:0]; + ibuf_timer = _RAND_34[2:0]; _RAND_35 = {1{`RANDOM}}; - WrPtr1_r = _RAND_35[1:0]; + ibuf_sideeffect = _RAND_35[0:0]; _RAND_36 = {1{`RANDOM}}; - WrPtr0_r = _RAND_36[1:0]; + WrPtr1_r = _RAND_36[1:0]; _RAND_37 = {1{`RANDOM}}; - ibuf_tag = _RAND_37[1:0]; + WrPtr0_r = _RAND_37[1:0]; _RAND_38 = {1{`RANDOM}}; - ibuf_dualtag = _RAND_38[1:0]; + ibuf_tag = _RAND_38[1:0]; _RAND_39 = {1{`RANDOM}}; - ibuf_dual = _RAND_39[0:0]; + ibuf_dualtag = _RAND_39[1:0]; _RAND_40 = {1{`RANDOM}}; - ibuf_samedw = _RAND_40[0:0]; + ibuf_dual = _RAND_40[0:0]; _RAND_41 = {1{`RANDOM}}; - ibuf_nomerge = _RAND_41[0:0]; + ibuf_samedw = _RAND_41[0:0]; _RAND_42 = {1{`RANDOM}}; - ibuf_unsign = _RAND_42[0:0]; + ibuf_nomerge = _RAND_42[0:0]; _RAND_43 = {1{`RANDOM}}; - ibuf_sz = _RAND_43[1:0]; + ibuf_unsign = _RAND_43[0:0]; _RAND_44 = {1{`RANDOM}}; - buf_nomerge_0 = _RAND_44[0:0]; + ibuf_sz = _RAND_44[1:0]; _RAND_45 = {1{`RANDOM}}; - buf_nomerge_1 = _RAND_45[0:0]; + obuf_wr_timer = _RAND_45[2:0]; _RAND_46 = {1{`RANDOM}}; - buf_nomerge_2 = _RAND_46[0:0]; + buf_nomerge_0 = _RAND_46[0:0]; _RAND_47 = {1{`RANDOM}}; - buf_nomerge_3 = _RAND_47[0:0]; + buf_nomerge_1 = _RAND_47[0:0]; _RAND_48 = {1{`RANDOM}}; - _T_4330 = _RAND_48[0:0]; + buf_nomerge_2 = _RAND_48[0:0]; _RAND_49 = {1{`RANDOM}}; - _T_4327 = _RAND_49[0:0]; + buf_nomerge_3 = _RAND_49[0:0]; _RAND_50 = {1{`RANDOM}}; - _T_4324 = _RAND_50[0:0]; + _T_4330 = _RAND_50[0:0]; _RAND_51 = {1{`RANDOM}}; - _T_4321 = _RAND_51[0:0]; + _T_4327 = _RAND_51[0:0]; _RAND_52 = {1{`RANDOM}}; - obuf_sideeffect = _RAND_52[0:0]; + _T_4324 = _RAND_52[0:0]; _RAND_53 = {1{`RANDOM}}; - buf_dual_3 = _RAND_53[0:0]; + _T_4321 = _RAND_53[0:0]; _RAND_54 = {1{`RANDOM}}; - buf_dual_2 = _RAND_54[0:0]; + obuf_sideeffect = _RAND_54[0:0]; _RAND_55 = {1{`RANDOM}}; - buf_dual_1 = _RAND_55[0:0]; + buf_dual_3 = _RAND_55[0:0]; _RAND_56 = {1{`RANDOM}}; - buf_dual_0 = _RAND_56[0:0]; + buf_dual_2 = _RAND_56[0:0]; _RAND_57 = {1{`RANDOM}}; - buf_samedw_3 = _RAND_57[0:0]; + buf_dual_1 = _RAND_57[0:0]; _RAND_58 = {1{`RANDOM}}; - buf_samedw_2 = _RAND_58[0:0]; + buf_dual_0 = _RAND_58[0:0]; _RAND_59 = {1{`RANDOM}}; - buf_samedw_1 = _RAND_59[0:0]; + buf_samedw_3 = _RAND_59[0:0]; _RAND_60 = {1{`RANDOM}}; - buf_samedw_0 = _RAND_60[0:0]; + buf_samedw_2 = _RAND_60[0:0]; _RAND_61 = {1{`RANDOM}}; - obuf_write = _RAND_61[0:0]; + buf_samedw_1 = _RAND_61[0:0]; _RAND_62 = {1{`RANDOM}}; - obuf_cmd_done = _RAND_62[0:0]; + buf_samedw_0 = _RAND_62[0:0]; _RAND_63 = {1{`RANDOM}}; - obuf_data_done = _RAND_63[0:0]; + obuf_write = _RAND_63[0:0]; _RAND_64 = {1{`RANDOM}}; - obuf_nosend = _RAND_64[0:0]; + obuf_cmd_done = _RAND_64[0:0]; _RAND_65 = {1{`RANDOM}}; - obuf_addr = _RAND_65[31:0]; + obuf_data_done = _RAND_65[0:0]; _RAND_66 = {1{`RANDOM}}; - buf_sz_0 = _RAND_66[1:0]; + obuf_nosend = _RAND_66[0:0]; _RAND_67 = {1{`RANDOM}}; - buf_sz_1 = _RAND_67[1:0]; + obuf_addr = _RAND_67[31:0]; _RAND_68 = {1{`RANDOM}}; - buf_sz_2 = _RAND_68[1:0]; + buf_sz_0 = _RAND_68[1:0]; _RAND_69 = {1{`RANDOM}}; - buf_sz_3 = _RAND_69[1:0]; + buf_sz_1 = _RAND_69[1:0]; _RAND_70 = {1{`RANDOM}}; - obuf_rdrsp_pend = _RAND_70[0:0]; + buf_sz_2 = _RAND_70[1:0]; _RAND_71 = {1{`RANDOM}}; - obuf_rdrsp_tag = _RAND_71[2:0]; + buf_sz_3 = _RAND_71[1:0]; _RAND_72 = {1{`RANDOM}}; - buf_dualhi_3 = _RAND_72[0:0]; + obuf_rdrsp_pend = _RAND_72[0:0]; _RAND_73 = {1{`RANDOM}}; - buf_dualhi_2 = _RAND_73[0:0]; + obuf_rdrsp_tag = _RAND_73[2:0]; _RAND_74 = {1{`RANDOM}}; - buf_dualhi_1 = _RAND_74[0:0]; + buf_dualhi_3 = _RAND_74[0:0]; _RAND_75 = {1{`RANDOM}}; - buf_dualhi_0 = _RAND_75[0:0]; + buf_dualhi_2 = _RAND_75[0:0]; _RAND_76 = {1{`RANDOM}}; - obuf_sz = _RAND_76[1:0]; + buf_dualhi_1 = _RAND_76[0:0]; _RAND_77 = {1{`RANDOM}}; - obuf_byteen = _RAND_77[7:0]; - _RAND_78 = {2{`RANDOM}}; - obuf_data = _RAND_78[63:0]; + buf_dualhi_0 = _RAND_77[0:0]; + _RAND_78 = {1{`RANDOM}}; + obuf_sz = _RAND_78[1:0]; _RAND_79 = {1{`RANDOM}}; - buf_rspageQ_0 = _RAND_79[3:0]; - _RAND_80 = {1{`RANDOM}}; - buf_rspageQ_1 = _RAND_80[3:0]; + obuf_byteen = _RAND_79[7:0]; + _RAND_80 = {2{`RANDOM}}; + obuf_data = _RAND_80[63:0]; _RAND_81 = {1{`RANDOM}}; - buf_rspageQ_2 = _RAND_81[3:0]; + buf_rspageQ_0 = _RAND_81[3:0]; _RAND_82 = {1{`RANDOM}}; - buf_rspageQ_3 = _RAND_82[3:0]; + buf_rspageQ_1 = _RAND_82[3:0]; _RAND_83 = {1{`RANDOM}}; - _T_4307 = _RAND_83[0:0]; + buf_rspageQ_2 = _RAND_83[3:0]; _RAND_84 = {1{`RANDOM}}; - _T_4305 = _RAND_84[0:0]; + buf_rspageQ_3 = _RAND_84[3:0]; _RAND_85 = {1{`RANDOM}}; - _T_4303 = _RAND_85[0:0]; + _T_4307 = _RAND_85[0:0]; _RAND_86 = {1{`RANDOM}}; - _T_4301 = _RAND_86[0:0]; + _T_4305 = _RAND_86[0:0]; _RAND_87 = {1{`RANDOM}}; - buf_ldfwdtag_0 = _RAND_87[1:0]; + _T_4303 = _RAND_87[0:0]; _RAND_88 = {1{`RANDOM}}; - buf_dualtag_0 = _RAND_88[1:0]; + _T_4301 = _RAND_88[0:0]; _RAND_89 = {1{`RANDOM}}; - buf_ldfwdtag_3 = _RAND_89[1:0]; + buf_ldfwdtag_0 = _RAND_89[1:0]; _RAND_90 = {1{`RANDOM}}; - buf_ldfwdtag_2 = _RAND_90[1:0]; + buf_dualtag_0 = _RAND_90[1:0]; _RAND_91 = {1{`RANDOM}}; - buf_ldfwdtag_1 = _RAND_91[1:0]; + buf_ldfwdtag_3 = _RAND_91[1:0]; _RAND_92 = {1{`RANDOM}}; - buf_dualtag_1 = _RAND_92[1:0]; + buf_ldfwdtag_2 = _RAND_92[1:0]; _RAND_93 = {1{`RANDOM}}; - buf_dualtag_2 = _RAND_93[1:0]; + buf_ldfwdtag_1 = _RAND_93[1:0]; _RAND_94 = {1{`RANDOM}}; - buf_dualtag_3 = _RAND_94[1:0]; + buf_dualtag_1 = _RAND_94[1:0]; _RAND_95 = {1{`RANDOM}}; - _T_4336 = _RAND_95[0:0]; + buf_dualtag_2 = _RAND_95[1:0]; _RAND_96 = {1{`RANDOM}}; - _T_4339 = _RAND_96[0:0]; + buf_dualtag_3 = _RAND_96[1:0]; _RAND_97 = {1{`RANDOM}}; - _T_4342 = _RAND_97[0:0]; + _T_4336 = _RAND_97[0:0]; _RAND_98 = {1{`RANDOM}}; - _T_4345 = _RAND_98[0:0]; + _T_4339 = _RAND_98[0:0]; _RAND_99 = {1{`RANDOM}}; - _T_4411 = _RAND_99[0:0]; + _T_4342 = _RAND_99[0:0]; _RAND_100 = {1{`RANDOM}}; - _T_4406 = _RAND_100[0:0]; + _T_4345 = _RAND_100[0:0]; _RAND_101 = {1{`RANDOM}}; - _T_4401 = _RAND_101[0:0]; + _T_4411 = _RAND_101[0:0]; _RAND_102 = {1{`RANDOM}}; - _T_4396 = _RAND_102[0:0]; + _T_4406 = _RAND_102[0:0]; _RAND_103 = {1{`RANDOM}}; - lsu_nonblock_load_valid_r = _RAND_103[0:0]; + _T_4401 = _RAND_103[0:0]; _RAND_104 = {1{`RANDOM}}; - _T_4987 = _RAND_104[0:0]; + _T_4396 = _RAND_104[0:0]; + _RAND_105 = {1{`RANDOM}}; + lsu_nonblock_load_valid_r = _RAND_105[0:0]; + _RAND_106 = {1{`RANDOM}}; + _T_4987 = _RAND_106[0:0]; `endif // RANDOMIZE_REG_INIT if (reset) begin buf_addr_0 = 32'h0; @@ -71176,6 +71296,9 @@ initial begin if (reset) begin ibuf_data = 32'h0; end + if (reset) begin + ibuf_timer = 3'h0; + end if (reset) begin ibuf_sideeffect = 1'h0; end @@ -71206,6 +71329,9 @@ initial begin if (reset) begin ibuf_sz = 2'h0; end + if (reset) begin + obuf_wr_timer = 3'h0; + end if (reset) begin buf_nomerge_0 = 1'h0; end @@ -71808,7 +71934,9 @@ end // initial if (reset) begin ibuf_byteen <= 4'h0; end else if (ibuf_wr_en) begin - if (io_ldst_dual_r) begin + if (_T_866) begin + ibuf_byteen <= _T_881; + end else if (io_ldst_dual_r) begin ibuf_byteen <= ldst_byteen_hi_r; end else begin ibuf_byteen <= ldst_byteen_lo_r; @@ -71972,7 +72100,16 @@ end // initial if (reset) begin ibuf_data <= 32'h0; end else begin - ibuf_data <= {_T_922,_T_892}; + ibuf_data <= {_T_922,_T_893}; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + ibuf_timer <= 3'h0; + end else if (ibuf_wr_en) begin + ibuf_timer <= 3'h0; + end else if (_T_923) begin + ibuf_timer <= _T_926; end end always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin @@ -72012,10 +72149,12 @@ end // initial if (reset) begin ibuf_tag <= 2'h0; end else if (ibuf_wr_en) begin - if (io_ldst_dual_r) begin - ibuf_tag <= WrPtr1_r; - end else begin - ibuf_tag <= WrPtr0_r; + if (!(_T_866)) begin + if (io_ldst_dual_r) begin + ibuf_tag <= WrPtr1_r; + end else begin + ibuf_tag <= WrPtr0_r; + end end end end @@ -72061,6 +72200,15 @@ end // initial ibuf_sz <= ibuf_sz_in; end end + always @(posedge io_lsu_busm_clk or posedge reset) begin + if (reset) begin + obuf_wr_timer <= 3'h0; + end else if (obuf_wr_en) begin + obuf_wr_timer <= 3'h0; + end else if (_T_1058) begin + obuf_wr_timer <= _T_1060; + end + end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin buf_nomerge_0 <= 1'h0; @@ -72608,6 +72756,7 @@ module lsu_bus_intf( output io_tlu_busbuff_lsu_pmu_bus_error, output io_tlu_busbuff_lsu_pmu_bus_busy, input io_tlu_busbuff_dec_tlu_external_ldfwd_disable, + input io_tlu_busbuff_dec_tlu_wb_coalescing_disable, input io_tlu_busbuff_dec_tlu_sideeffect_posted_disable, output io_tlu_busbuff_lsu_imprecise_error_load_any, output io_tlu_busbuff_lsu_imprecise_error_store_any, @@ -72625,7 +72774,9 @@ module lsu_bus_intf( output io_axi_aw_valid, output [2:0] io_axi_aw_bits_id, output [31:0] io_axi_aw_bits_addr, + output [3:0] io_axi_aw_bits_region, output [2:0] io_axi_aw_bits_size, + output [3:0] io_axi_aw_bits_cache, input io_axi_w_ready, output io_axi_w_valid, output [63:0] io_axi_w_bits_data, @@ -72637,7 +72788,9 @@ module lsu_bus_intf( output io_axi_ar_valid, output [2:0] io_axi_ar_bits_id, output [31:0] io_axi_ar_bits_addr, + output [3:0] io_axi_ar_bits_region, output [2:0] io_axi_ar_bits_size, + output [3:0] io_axi_ar_bits_cache, input io_axi_r_valid, input [2:0] io_axi_r_bits_id, input [63:0] io_axi_r_bits_data, @@ -72698,6 +72851,7 @@ module lsu_bus_intf( wire bus_buffer_io_tlu_busbuff_lsu_pmu_bus_error; // @[lsu_bus_intf.scala 100:39] wire bus_buffer_io_tlu_busbuff_lsu_pmu_bus_busy; // @[lsu_bus_intf.scala 100:39] wire bus_buffer_io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_intf.scala 100:39] wire bus_buffer_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_intf.scala 100:39] wire bus_buffer_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[lsu_bus_intf.scala 100:39] wire bus_buffer_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu_bus_intf.scala 100:39] @@ -72747,7 +72901,9 @@ module lsu_bus_intf( wire bus_buffer_io_lsu_axi_aw_valid; // @[lsu_bus_intf.scala 100:39] wire [2:0] bus_buffer_io_lsu_axi_aw_bits_id; // @[lsu_bus_intf.scala 100:39] wire [31:0] bus_buffer_io_lsu_axi_aw_bits_addr; // @[lsu_bus_intf.scala 100:39] + wire [3:0] bus_buffer_io_lsu_axi_aw_bits_region; // @[lsu_bus_intf.scala 100:39] wire [2:0] bus_buffer_io_lsu_axi_aw_bits_size; // @[lsu_bus_intf.scala 100:39] + wire [3:0] bus_buffer_io_lsu_axi_aw_bits_cache; // @[lsu_bus_intf.scala 100:39] wire bus_buffer_io_lsu_axi_w_ready; // @[lsu_bus_intf.scala 100:39] wire bus_buffer_io_lsu_axi_w_valid; // @[lsu_bus_intf.scala 100:39] wire [63:0] bus_buffer_io_lsu_axi_w_bits_data; // @[lsu_bus_intf.scala 100:39] @@ -72760,7 +72916,9 @@ module lsu_bus_intf( wire bus_buffer_io_lsu_axi_ar_valid; // @[lsu_bus_intf.scala 100:39] wire [2:0] bus_buffer_io_lsu_axi_ar_bits_id; // @[lsu_bus_intf.scala 100:39] wire [31:0] bus_buffer_io_lsu_axi_ar_bits_addr; // @[lsu_bus_intf.scala 100:39] + wire [3:0] bus_buffer_io_lsu_axi_ar_bits_region; // @[lsu_bus_intf.scala 100:39] wire [2:0] bus_buffer_io_lsu_axi_ar_bits_size; // @[lsu_bus_intf.scala 100:39] + wire [3:0] bus_buffer_io_lsu_axi_ar_bits_cache; // @[lsu_bus_intf.scala 100:39] wire bus_buffer_io_lsu_axi_r_ready; // @[lsu_bus_intf.scala 100:39] wire bus_buffer_io_lsu_axi_r_valid; // @[lsu_bus_intf.scala 100:39] wire [2:0] bus_buffer_io_lsu_axi_r_bits_id; // @[lsu_bus_intf.scala 100:39] @@ -72966,6 +73124,7 @@ module lsu_bus_intf( .io_tlu_busbuff_lsu_pmu_bus_error(bus_buffer_io_tlu_busbuff_lsu_pmu_bus_error), .io_tlu_busbuff_lsu_pmu_bus_busy(bus_buffer_io_tlu_busbuff_lsu_pmu_bus_busy), .io_tlu_busbuff_dec_tlu_external_ldfwd_disable(bus_buffer_io_tlu_busbuff_dec_tlu_external_ldfwd_disable), + .io_tlu_busbuff_dec_tlu_wb_coalescing_disable(bus_buffer_io_tlu_busbuff_dec_tlu_wb_coalescing_disable), .io_tlu_busbuff_dec_tlu_sideeffect_posted_disable(bus_buffer_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable), .io_tlu_busbuff_lsu_imprecise_error_load_any(bus_buffer_io_tlu_busbuff_lsu_imprecise_error_load_any), .io_tlu_busbuff_lsu_imprecise_error_store_any(bus_buffer_io_tlu_busbuff_lsu_imprecise_error_store_any), @@ -73015,7 +73174,9 @@ module lsu_bus_intf( .io_lsu_axi_aw_valid(bus_buffer_io_lsu_axi_aw_valid), .io_lsu_axi_aw_bits_id(bus_buffer_io_lsu_axi_aw_bits_id), .io_lsu_axi_aw_bits_addr(bus_buffer_io_lsu_axi_aw_bits_addr), + .io_lsu_axi_aw_bits_region(bus_buffer_io_lsu_axi_aw_bits_region), .io_lsu_axi_aw_bits_size(bus_buffer_io_lsu_axi_aw_bits_size), + .io_lsu_axi_aw_bits_cache(bus_buffer_io_lsu_axi_aw_bits_cache), .io_lsu_axi_w_ready(bus_buffer_io_lsu_axi_w_ready), .io_lsu_axi_w_valid(bus_buffer_io_lsu_axi_w_valid), .io_lsu_axi_w_bits_data(bus_buffer_io_lsu_axi_w_bits_data), @@ -73028,7 +73189,9 @@ module lsu_bus_intf( .io_lsu_axi_ar_valid(bus_buffer_io_lsu_axi_ar_valid), .io_lsu_axi_ar_bits_id(bus_buffer_io_lsu_axi_ar_bits_id), .io_lsu_axi_ar_bits_addr(bus_buffer_io_lsu_axi_ar_bits_addr), + .io_lsu_axi_ar_bits_region(bus_buffer_io_lsu_axi_ar_bits_region), .io_lsu_axi_ar_bits_size(bus_buffer_io_lsu_axi_ar_bits_size), + .io_lsu_axi_ar_bits_cache(bus_buffer_io_lsu_axi_ar_bits_cache), .io_lsu_axi_r_ready(bus_buffer_io_lsu_axi_r_ready), .io_lsu_axi_r_valid(bus_buffer_io_lsu_axi_r_valid), .io_lsu_axi_r_bits_id(bus_buffer_io_lsu_axi_r_bits_id), @@ -73055,14 +73218,18 @@ module lsu_bus_intf( assign io_axi_aw_valid = bus_buffer_io_lsu_axi_aw_valid; // @[lsu_bus_intf.scala 129:43] assign io_axi_aw_bits_id = bus_buffer_io_lsu_axi_aw_bits_id; // @[lsu_bus_intf.scala 129:43] assign io_axi_aw_bits_addr = bus_buffer_io_lsu_axi_aw_bits_addr; // @[lsu_bus_intf.scala 129:43] + assign io_axi_aw_bits_region = bus_buffer_io_lsu_axi_aw_bits_region; // @[lsu_bus_intf.scala 129:43] assign io_axi_aw_bits_size = bus_buffer_io_lsu_axi_aw_bits_size; // @[lsu_bus_intf.scala 129:43] + assign io_axi_aw_bits_cache = bus_buffer_io_lsu_axi_aw_bits_cache; // @[lsu_bus_intf.scala 129:43] assign io_axi_w_valid = bus_buffer_io_lsu_axi_w_valid; // @[lsu_bus_intf.scala 129:43] assign io_axi_w_bits_data = bus_buffer_io_lsu_axi_w_bits_data; // @[lsu_bus_intf.scala 129:43] assign io_axi_w_bits_strb = bus_buffer_io_lsu_axi_w_bits_strb; // @[lsu_bus_intf.scala 129:43] assign io_axi_ar_valid = bus_buffer_io_lsu_axi_ar_valid; // @[lsu_bus_intf.scala 129:43] assign io_axi_ar_bits_id = bus_buffer_io_lsu_axi_ar_bits_id; // @[lsu_bus_intf.scala 129:43] assign io_axi_ar_bits_addr = bus_buffer_io_lsu_axi_ar_bits_addr; // @[lsu_bus_intf.scala 129:43] + assign io_axi_ar_bits_region = bus_buffer_io_lsu_axi_ar_bits_region; // @[lsu_bus_intf.scala 129:43] assign io_axi_ar_bits_size = bus_buffer_io_lsu_axi_ar_bits_size; // @[lsu_bus_intf.scala 129:43] + assign io_axi_ar_bits_cache = bus_buffer_io_lsu_axi_ar_bits_cache; // @[lsu_bus_intf.scala 129:43] assign io_lsu_busreq_r = bus_buffer_io_lsu_busreq_r; // @[lsu_bus_intf.scala 132:38] assign io_lsu_bus_buffer_pend_any = bus_buffer_io_lsu_bus_buffer_pend_any; // @[lsu_bus_intf.scala 133:38] assign io_lsu_bus_buffer_full_any = bus_buffer_io_lsu_bus_buffer_full_any; // @[lsu_bus_intf.scala 134:38] @@ -73080,6 +73247,7 @@ module lsu_bus_intf( assign bus_buffer_reset = reset; assign bus_buffer_io_scan_mode = io_scan_mode; // @[lsu_bus_intf.scala 102:29] assign bus_buffer_io_tlu_busbuff_dec_tlu_external_ldfwd_disable = io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu_bus_intf.scala 103:18] + assign bus_buffer_io_tlu_busbuff_dec_tlu_wb_coalescing_disable = io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_intf.scala 103:18] assign bus_buffer_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable = io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_intf.scala 103:18] assign bus_buffer_io_dec_tlu_force_halt = io_dec_tlu_force_halt; // @[lsu_bus_intf.scala 105:51] assign bus_buffer_io_lsu_c2_r_clk = io_lsu_c2_r_clk; // @[lsu_bus_intf.scala 106:51] @@ -73260,6 +73428,7 @@ module lsu( output io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error, output io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy, input io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable, + input io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable, input io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable, output io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any, output io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any, @@ -73288,7 +73457,9 @@ module lsu( output io_axi_aw_valid, output [2:0] io_axi_aw_bits_id, output [31:0] io_axi_aw_bits_addr, + output [3:0] io_axi_aw_bits_region, output [2:0] io_axi_aw_bits_size, + output [3:0] io_axi_aw_bits_cache, input io_axi_w_ready, output io_axi_w_valid, output [63:0] io_axi_w_bits_data, @@ -73300,7 +73471,9 @@ module lsu( output io_axi_ar_valid, output [2:0] io_axi_ar_bits_id, output [31:0] io_axi_ar_bits_addr, + output [3:0] io_axi_ar_bits_region, output [2:0] io_axi_ar_bits_size, + output [3:0] io_axi_ar_bits_cache, input io_axi_r_valid, input [2:0] io_axi_r_bits_id, input [63:0] io_axi_r_bits_data, @@ -73725,6 +73898,7 @@ module lsu( wire bus_intf_io_tlu_busbuff_lsu_pmu_bus_error; // @[lsu.scala 68:30] wire bus_intf_io_tlu_busbuff_lsu_pmu_bus_busy; // @[lsu.scala 68:30] wire bus_intf_io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu.scala 68:30] + wire bus_intf_io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu.scala 68:30] wire bus_intf_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu.scala 68:30] wire bus_intf_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[lsu.scala 68:30] wire bus_intf_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu.scala 68:30] @@ -73742,7 +73916,9 @@ module lsu( wire bus_intf_io_axi_aw_valid; // @[lsu.scala 68:30] wire [2:0] bus_intf_io_axi_aw_bits_id; // @[lsu.scala 68:30] wire [31:0] bus_intf_io_axi_aw_bits_addr; // @[lsu.scala 68:30] + wire [3:0] bus_intf_io_axi_aw_bits_region; // @[lsu.scala 68:30] wire [2:0] bus_intf_io_axi_aw_bits_size; // @[lsu.scala 68:30] + wire [3:0] bus_intf_io_axi_aw_bits_cache; // @[lsu.scala 68:30] wire bus_intf_io_axi_w_ready; // @[lsu.scala 68:30] wire bus_intf_io_axi_w_valid; // @[lsu.scala 68:30] wire [63:0] bus_intf_io_axi_w_bits_data; // @[lsu.scala 68:30] @@ -73754,7 +73930,9 @@ module lsu( wire bus_intf_io_axi_ar_valid; // @[lsu.scala 68:30] wire [2:0] bus_intf_io_axi_ar_bits_id; // @[lsu.scala 68:30] wire [31:0] bus_intf_io_axi_ar_bits_addr; // @[lsu.scala 68:30] + wire [3:0] bus_intf_io_axi_ar_bits_region; // @[lsu.scala 68:30] wire [2:0] bus_intf_io_axi_ar_bits_size; // @[lsu.scala 68:30] + wire [3:0] bus_intf_io_axi_ar_bits_cache; // @[lsu.scala 68:30] wire bus_intf_io_axi_r_valid; // @[lsu.scala 68:30] wire [2:0] bus_intf_io_axi_r_bits_id; // @[lsu.scala 68:30] wire [63:0] bus_intf_io_axi_r_bits_data; // @[lsu.scala 68:30] @@ -74205,6 +74383,7 @@ module lsu( .io_tlu_busbuff_lsu_pmu_bus_error(bus_intf_io_tlu_busbuff_lsu_pmu_bus_error), .io_tlu_busbuff_lsu_pmu_bus_busy(bus_intf_io_tlu_busbuff_lsu_pmu_bus_busy), .io_tlu_busbuff_dec_tlu_external_ldfwd_disable(bus_intf_io_tlu_busbuff_dec_tlu_external_ldfwd_disable), + .io_tlu_busbuff_dec_tlu_wb_coalescing_disable(bus_intf_io_tlu_busbuff_dec_tlu_wb_coalescing_disable), .io_tlu_busbuff_dec_tlu_sideeffect_posted_disable(bus_intf_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable), .io_tlu_busbuff_lsu_imprecise_error_load_any(bus_intf_io_tlu_busbuff_lsu_imprecise_error_load_any), .io_tlu_busbuff_lsu_imprecise_error_store_any(bus_intf_io_tlu_busbuff_lsu_imprecise_error_store_any), @@ -74222,7 +74401,9 @@ module lsu( .io_axi_aw_valid(bus_intf_io_axi_aw_valid), .io_axi_aw_bits_id(bus_intf_io_axi_aw_bits_id), .io_axi_aw_bits_addr(bus_intf_io_axi_aw_bits_addr), + .io_axi_aw_bits_region(bus_intf_io_axi_aw_bits_region), .io_axi_aw_bits_size(bus_intf_io_axi_aw_bits_size), + .io_axi_aw_bits_cache(bus_intf_io_axi_aw_bits_cache), .io_axi_w_ready(bus_intf_io_axi_w_ready), .io_axi_w_valid(bus_intf_io_axi_w_valid), .io_axi_w_bits_data(bus_intf_io_axi_w_bits_data), @@ -74234,7 +74415,9 @@ module lsu( .io_axi_ar_valid(bus_intf_io_axi_ar_valid), .io_axi_ar_bits_id(bus_intf_io_axi_ar_bits_id), .io_axi_ar_bits_addr(bus_intf_io_axi_ar_bits_addr), + .io_axi_ar_bits_region(bus_intf_io_axi_ar_bits_region), .io_axi_ar_bits_size(bus_intf_io_axi_ar_bits_size), + .io_axi_ar_bits_cache(bus_intf_io_axi_ar_bits_cache), .io_axi_r_valid(bus_intf_io_axi_r_valid), .io_axi_r_bits_id(bus_intf_io_axi_r_bits_id), .io_axi_r_bits_data(bus_intf_io_axi_r_bits_data), @@ -74319,14 +74502,18 @@ module lsu( assign io_axi_aw_valid = bus_intf_io_axi_aw_valid; // @[lsu.scala 314:49] assign io_axi_aw_bits_id = bus_intf_io_axi_aw_bits_id; // @[lsu.scala 314:49] assign io_axi_aw_bits_addr = bus_intf_io_axi_aw_bits_addr; // @[lsu.scala 314:49] + assign io_axi_aw_bits_region = bus_intf_io_axi_aw_bits_region; // @[lsu.scala 314:49] assign io_axi_aw_bits_size = bus_intf_io_axi_aw_bits_size; // @[lsu.scala 314:49] + assign io_axi_aw_bits_cache = bus_intf_io_axi_aw_bits_cache; // @[lsu.scala 314:49] assign io_axi_w_valid = bus_intf_io_axi_w_valid; // @[lsu.scala 314:49] assign io_axi_w_bits_data = bus_intf_io_axi_w_bits_data; // @[lsu.scala 314:49] assign io_axi_w_bits_strb = bus_intf_io_axi_w_bits_strb; // @[lsu.scala 314:49] assign io_axi_ar_valid = bus_intf_io_axi_ar_valid; // @[lsu.scala 314:49] assign io_axi_ar_bits_id = bus_intf_io_axi_ar_bits_id; // @[lsu.scala 314:49] assign io_axi_ar_bits_addr = bus_intf_io_axi_ar_bits_addr; // @[lsu.scala 314:49] + assign io_axi_ar_bits_region = bus_intf_io_axi_ar_bits_region; // @[lsu.scala 314:49] assign io_axi_ar_bits_size = bus_intf_io_axi_ar_bits_size; // @[lsu.scala 314:49] + assign io_axi_ar_bits_cache = bus_intf_io_axi_ar_bits_cache; // @[lsu.scala 314:49] assign io_lsu_result_m = lsu_lsc_ctl_io_lsu_result_m; // @[lsu.scala 61:19] assign io_lsu_result_corr_r = lsu_lsc_ctl_io_lsu_result_corr_r; // @[lsu.scala 62:24] assign io_lsu_load_stall_any = bus_intf_io_lsu_bus_buffer_full_any | dccm_ctl_io_ld_single_ecc_error_r_ff; // @[lsu.scala 75:25] @@ -74561,6 +74748,7 @@ module lsu( assign bus_intf_reset = reset; assign bus_intf_io_scan_mode = io_scan_mode; // @[lsu.scala 285:49] assign bus_intf_io_tlu_busbuff_dec_tlu_external_ldfwd_disable = io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu.scala 286:26] + assign bus_intf_io_tlu_busbuff_dec_tlu_wb_coalescing_disable = io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu.scala 286:26] assign bus_intf_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable = io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu.scala 286:26] assign bus_intf_io_lsu_c1_m_clk = clkdomain_io_lsu_c1_m_clk; // @[lsu.scala 287:49] assign bus_intf_io_lsu_c1_r_clk = clkdomain_io_lsu_c1_r_clk; // @[lsu.scala 288:49] @@ -78346,18 +78534,25 @@ module dma_ctrl( input io_iccm_ready, output io_dma_axi_aw_ready, input io_dma_axi_aw_valid, + input io_dma_axi_aw_bits_id, input [31:0] io_dma_axi_aw_bits_addr, input [2:0] io_dma_axi_aw_bits_size, output io_dma_axi_w_ready, input io_dma_axi_w_valid, input [63:0] io_dma_axi_w_bits_data, input [7:0] io_dma_axi_w_bits_strb, + input io_dma_axi_b_ready, output io_dma_axi_b_valid, + output [1:0] io_dma_axi_b_bits_resp, + output io_dma_axi_b_bits_id, output io_dma_axi_ar_ready, input io_dma_axi_ar_valid, + input io_dma_axi_ar_bits_id, input [31:0] io_dma_axi_ar_bits_addr, input [2:0] io_dma_axi_ar_bits_size, + input io_dma_axi_r_ready, output io_dma_axi_r_valid, + output io_dma_axi_r_bits_id, output [63:0] io_dma_axi_r_bits_data, output [1:0] io_dma_axi_r_bits_resp, output io_lsu_dma_dma_lsc_ctl_dma_dccm_req, @@ -78454,6 +78649,13 @@ module dma_ctrl( reg [63:0] _RAND_69; reg [31:0] _RAND_70; reg [31:0] _RAND_71; + reg [31:0] _RAND_72; + reg [31:0] _RAND_73; + reg [31:0] _RAND_74; + reg [31:0] _RAND_75; + reg [31:0] _RAND_76; + reg [31:0] _RAND_77; + reg [31:0] _RAND_78; `endif // RANDOMIZE_REG_INIT wire rvclkhdr_io_l1clk; // @[lib.scala 368:23] wire rvclkhdr_io_clk; // @[lib.scala 368:23] @@ -78850,7 +79052,9 @@ module dma_ctrl( wire _T_399 = fifo_done_en[4] | fifo_done[4]; // @[dma_ctrl.scala 218:75] wire _T_400 = _T_399 & io_dma_bus_clk_en; // @[dma_ctrl.scala 218:91] wire [4:0] fifo_done_bus_en = {_T_400,_T_396,_T_392,_T_388,_T_384}; // @[Cat.scala 29:58] - wire bus_rsp_sent = io_dma_axi_b_valid | io_dma_axi_r_valid; // @[dma_ctrl.scala 489:83] + wire _T_1287 = io_dma_axi_b_valid & io_dma_axi_b_ready; // @[dma_ctrl.scala 489:61] + wire _T_1288 = io_dma_axi_r_valid & io_dma_axi_r_ready; // @[dma_ctrl.scala 489:105] + wire bus_rsp_sent = _T_1287 | _T_1288; // @[dma_ctrl.scala 489:83] wire _T_406 = bus_rsp_sent & io_dma_bus_clk_en; // @[dma_ctrl.scala 220:99] wire _T_407 = _T_406 | io_dma_dbg_cmd_done; // @[dma_ctrl.scala 220:120] reg [2:0] RspPtr; // @[Reg.scala 27:20] @@ -78932,6 +79136,14 @@ module dma_ctrl( reg [63:0] fifo_data_2; // @[lib.scala 374:16] reg [63:0] fifo_data_3; // @[lib.scala 374:16] reg [63:0] fifo_data_4; // @[lib.scala 374:16] + reg fifo_tag_0; // @[Reg.scala 27:20] + reg wrbuf_tag; // @[Reg.scala 27:20] + reg rdbuf_tag; // @[Reg.scala 27:20] + wire bus_cmd_tag = axi_mstr_sel ? wrbuf_tag : rdbuf_tag; // @[dma_ctrl.scala 454:43] + reg fifo_tag_1; // @[Reg.scala 27:20] + reg fifo_tag_2; // @[Reg.scala 27:20] + reg fifo_tag_3; // @[Reg.scala 27:20] + reg fifo_tag_4; // @[Reg.scala 27:20] wire _T_931 = WrPtr == 3'h4; // @[dma_ctrl.scala 260:30] wire [2:0] _T_934 = WrPtr + 3'h1; // @[dma_ctrl.scala 260:76] wire _T_936 = RdPtr == 3'h4; // @[dma_ctrl.scala 262:30] @@ -78998,7 +79210,8 @@ module dma_ctrl( reg dma_dbg_cmd_done_q; // @[dma_ctrl.scala 381:12] wire _T_1212 = bus_cmd_valid & io_dma_bus_clk_en; // @[dma_ctrl.scala 386:44] wire _T_1213 = _T_1212 | io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[dma_ctrl.scala 386:65] - wire _T_1214 = bus_cmd_valid | bus_rsp_sent; // @[dma_ctrl.scala 387:44] + wire bus_rsp_valid = io_dma_axi_b_valid | io_dma_axi_r_valid; // @[dma_ctrl.scala 488:60] + wire _T_1214 = bus_cmd_valid | bus_rsp_valid; // @[dma_ctrl.scala 387:44] wire _T_1215 = _T_1214 | io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[dma_ctrl.scala 387:60] wire _T_1216 = _T_1215 | io_dma_dbg_cmd_done; // @[dma_ctrl.scala 387:94] wire _T_1217 = _T_1216 | dma_dbg_cmd_done_q; // @[dma_ctrl.scala 387:116] @@ -79034,6 +79247,9 @@ module dma_ctrl( wire [4:0] _T_1277 = fifo_write >> RspPtr; // @[dma_ctrl.scala 470:39] wire axi_rsp_write = _T_1277[0]; // @[dma_ctrl.scala 470:39] wire [1:0] _T_1280 = _GEN_57[1] ? 2'h3 : 2'h0; // @[dma_ctrl.scala 471:64] + wire _GEN_86 = 3'h1 == RspPtr ? fifo_tag_1 : fifo_tag_0; // @[dma_ctrl.scala 479:33] + wire _GEN_87 = 3'h2 == RspPtr ? fifo_tag_2 : _GEN_86; // @[dma_ctrl.scala 479:33] + wire _GEN_88 = 3'h3 == RspPtr ? fifo_tag_3 : _GEN_87; // @[dma_ctrl.scala 479:33] wire _T_1283 = ~axi_rsp_write; // @[dma_ctrl.scala 481:46] rvclkhdr rvclkhdr ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_io_l1clk), @@ -79145,8 +79361,11 @@ module dma_ctrl( assign io_dma_axi_aw_ready = ~_T_1245; // @[dma_ctrl.scala 440:27] assign io_dma_axi_w_ready = ~_T_1248; // @[dma_ctrl.scala 441:27] assign io_dma_axi_b_valid = axi_rsp_valid & axi_rsp_write; // @[dma_ctrl.scala 477:27] + assign io_dma_axi_b_bits_resp = _GEN_57[0] ? 2'h2 : _T_1280; // @[dma_ctrl.scala 478:41] + assign io_dma_axi_b_bits_id = 3'h4 == RspPtr ? fifo_tag_4 : _GEN_88; // @[dma_ctrl.scala 479:33] assign io_dma_axi_ar_ready = ~_T_1251; // @[dma_ctrl.scala 442:27] assign io_dma_axi_r_valid = axi_rsp_valid & _T_1283; // @[dma_ctrl.scala 481:27] + assign io_dma_axi_r_bits_id = 3'h4 == RspPtr ? fifo_tag_4 : _GEN_88; // @[dma_ctrl.scala 485:37] assign io_dma_axi_r_bits_data = 3'h4 == RspPtr ? fifo_data_4 : _GEN_51; // @[dma_ctrl.scala 483:43] assign io_dma_axi_r_bits_resp = _GEN_57[0] ? 2'h2 : _T_1280; // @[dma_ctrl.scala 482:41] assign io_lsu_dma_dma_lsc_ctl_dma_dccm_req = _T_1137 & io_lsu_dma_dccm_ready; // @[dma_ctrl.scala 352:40] @@ -79388,9 +79607,23 @@ initial begin _RAND_69 = {2{`RANDOM}}; fifo_data_4 = _RAND_69[63:0]; _RAND_70 = {1{`RANDOM}}; - dma_nack_count = _RAND_70[2:0]; + fifo_tag_0 = _RAND_70[0:0]; _RAND_71 = {1{`RANDOM}}; - dma_dbg_cmd_done_q = _RAND_71[0:0]; + wrbuf_tag = _RAND_71[0:0]; + _RAND_72 = {1{`RANDOM}}; + rdbuf_tag = _RAND_72[0:0]; + _RAND_73 = {1{`RANDOM}}; + fifo_tag_1 = _RAND_73[0:0]; + _RAND_74 = {1{`RANDOM}}; + fifo_tag_2 = _RAND_74[0:0]; + _RAND_75 = {1{`RANDOM}}; + fifo_tag_3 = _RAND_75[0:0]; + _RAND_76 = {1{`RANDOM}}; + fifo_tag_4 = _RAND_76[0:0]; + _RAND_77 = {1{`RANDOM}}; + dma_nack_count = _RAND_77[2:0]; + _RAND_78 = {1{`RANDOM}}; + dma_dbg_cmd_done_q = _RAND_78[0:0]; `endif // RANDOMIZE_REG_INIT if (reset) begin RdPtr = 3'h0; @@ -79602,6 +79835,27 @@ initial begin if (reset) begin fifo_data_4 = 64'h0; end + if (reset) begin + fifo_tag_0 = 1'h0; + end + if (reset) begin + wrbuf_tag = 1'h0; + end + if (reset) begin + rdbuf_tag = 1'h0; + end + if (reset) begin + fifo_tag_1 = 1'h0; + end + if (reset) begin + fifo_tag_2 = 1'h0; + end + if (reset) begin + fifo_tag_3 = 1'h0; + end + if (reset) begin + fifo_tag_4 = 1'h0; + end if (reset) begin dma_nack_count = 3'h0; end @@ -80220,6 +80474,71 @@ end // initial fifo_data_4 <= _T_500; end end + always @(posedge dma_buffer_c1_clk or posedge reset) begin + if (reset) begin + fifo_tag_0 <= 1'h0; + end else if (fifo_cmd_en[0]) begin + if (axi_mstr_sel) begin + fifo_tag_0 <= wrbuf_tag; + end else begin + fifo_tag_0 <= rdbuf_tag; + end + end + end + always @(posedge dma_bus_clk or posedge reset) begin + if (reset) begin + wrbuf_tag <= 1'h0; + end else if (wrbuf_en) begin + wrbuf_tag <= io_dma_axi_aw_bits_id; + end + end + always @(posedge dma_bus_clk or posedge reset) begin + if (reset) begin + rdbuf_tag <= 1'h0; + end else if (rdbuf_en) begin + rdbuf_tag <= io_dma_axi_ar_bits_id; + end + end + always @(posedge dma_buffer_c1_clk or posedge reset) begin + if (reset) begin + fifo_tag_1 <= 1'h0; + end else if (fifo_cmd_en[1]) begin + if (axi_mstr_sel) begin + fifo_tag_1 <= wrbuf_tag; + end else begin + fifo_tag_1 <= rdbuf_tag; + end + end + end + always @(posedge dma_buffer_c1_clk or posedge reset) begin + if (reset) begin + fifo_tag_2 <= 1'h0; + end else if (fifo_cmd_en[2]) begin + if (axi_mstr_sel) begin + fifo_tag_2 <= wrbuf_tag; + end else begin + fifo_tag_2 <= rdbuf_tag; + end + end + end + always @(posedge dma_buffer_c1_clk or posedge reset) begin + if (reset) begin + fifo_tag_3 <= 1'h0; + end else if (fifo_cmd_en[3]) begin + if (axi_mstr_sel) begin + fifo_tag_3 <= wrbuf_tag; + end else begin + fifo_tag_3 <= rdbuf_tag; + end + end + end + always @(posedge dma_buffer_c1_clk or posedge reset) begin + if (reset) begin + fifo_tag_4 <= 1'h0; + end else if (fifo_cmd_en[4]) begin + fifo_tag_4 <= bus_cmd_tag; + end + end always @(posedge dma_free_clk or posedge reset) begin if (reset) begin dma_nack_count <= 3'h0; @@ -80241,2639 +80560,6 @@ end // initial end end endmodule -module axi4_to_ahb( - input clock, - input reset, - input io_scan_mode, - input io_bus_clk_en, - input io_clk_override, - output io_axi_aw_ready, - input io_axi_aw_valid, - input [31:0] io_axi_aw_bits_addr, - input [2:0] io_axi_aw_bits_size, - output io_axi_w_ready, - input io_axi_w_valid, - input [63:0] io_axi_w_bits_data, - input [7:0] io_axi_w_bits_strb, - output io_axi_b_valid, - output [1:0] io_axi_b_bits_resp, - output io_axi_ar_ready, - input io_axi_ar_valid, - input [31:0] io_axi_ar_bits_addr, - input [2:0] io_axi_ar_bits_size, - output io_axi_r_valid, - output [63:0] io_axi_r_bits_data, - output [1:0] io_axi_r_bits_resp, - input [63:0] io_ahb_in_hrdata, - input io_ahb_in_hready, - input io_ahb_in_hresp, - output [31:0] io_ahb_out_haddr, - output [2:0] io_ahb_out_hsize, - output [1:0] io_ahb_out_htrans, - output io_ahb_out_hwrite, - output [63:0] io_ahb_out_hwdata -); -`ifdef RANDOMIZE_REG_INIT - reg [31:0] _RAND_0; - reg [31:0] _RAND_1; - reg [31:0] _RAND_2; - reg [31:0] _RAND_3; - reg [31:0] _RAND_4; - reg [31:0] _RAND_5; - reg [31:0] _RAND_6; - reg [31:0] _RAND_7; - reg [31:0] _RAND_8; - reg [31:0] _RAND_9; - reg [31:0] _RAND_10; - reg [63:0] _RAND_11; - reg [31:0] _RAND_12; - reg [31:0] _RAND_13; - reg [31:0] _RAND_14; - reg [63:0] _RAND_15; - reg [63:0] _RAND_16; - reg [31:0] _RAND_17; - reg [31:0] _RAND_18; - reg [31:0] _RAND_19; - reg [31:0] _RAND_20; - reg [31:0] _RAND_21; - reg [31:0] _RAND_22; -`endif // RANDOMIZE_REG_INIT - wire rvclkhdr_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_io_en; // @[lib.scala 343:22] - wire rvclkhdr_io_scan_mode; // @[lib.scala 343:22] - wire rvclkhdr_1_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_1_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_1_io_en; // @[lib.scala 343:22] - wire rvclkhdr_1_io_scan_mode; // @[lib.scala 343:22] - wire rvclkhdr_2_io_l1clk; // @[lib.scala 368:23] - wire rvclkhdr_2_io_clk; // @[lib.scala 368:23] - wire rvclkhdr_2_io_en; // @[lib.scala 368:23] - wire rvclkhdr_2_io_scan_mode; // @[lib.scala 368:23] - wire rvclkhdr_3_io_l1clk; // @[lib.scala 368:23] - wire rvclkhdr_3_io_clk; // @[lib.scala 368:23] - wire rvclkhdr_3_io_en; // @[lib.scala 368:23] - wire rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23] - wire rvclkhdr_4_io_l1clk; // @[lib.scala 368:23] - wire rvclkhdr_4_io_clk; // @[lib.scala 368:23] - wire rvclkhdr_4_io_en; // @[lib.scala 368:23] - wire rvclkhdr_4_io_scan_mode; // @[lib.scala 368:23] - wire rvclkhdr_5_io_l1clk; // @[lib.scala 368:23] - wire rvclkhdr_5_io_clk; // @[lib.scala 368:23] - wire rvclkhdr_5_io_en; // @[lib.scala 368:23] - wire rvclkhdr_5_io_scan_mode; // @[lib.scala 368:23] - wire rvclkhdr_6_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_6_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_6_io_en; // @[lib.scala 343:22] - wire rvclkhdr_6_io_scan_mode; // @[lib.scala 343:22] - wire rvclkhdr_7_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_7_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_7_io_en; // @[lib.scala 343:22] - wire rvclkhdr_7_io_scan_mode; // @[lib.scala 343:22] - wire rvclkhdr_8_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_8_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_8_io_en; // @[lib.scala 343:22] - wire rvclkhdr_8_io_scan_mode; // @[lib.scala 343:22] - wire rvclkhdr_9_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_9_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_9_io_en; // @[lib.scala 343:22] - wire rvclkhdr_9_io_scan_mode; // @[lib.scala 343:22] - wire ahbm_clk = rvclkhdr_7_io_l1clk; // @[axi4_to_ahb.scala 24:22 axi4_to_ahb.scala 333:12] - reg [2:0] buf_state; // @[axi4_to_ahb.scala 30:45] - wire _T_49 = 3'h0 == buf_state; // @[Conditional.scala 37:30] - wire bus_clk = rvclkhdr_io_l1clk; // @[axi4_to_ahb.scala 50:21 axi4_to_ahb.scala 162:11] - reg wrbuf_vld; // @[axi4_to_ahb.scala 301:51] - reg wrbuf_data_vld; // @[axi4_to_ahb.scala 302:51] - wire wr_cmd_vld = wrbuf_vld & wrbuf_data_vld; // @[axi4_to_ahb.scala 139:27] - wire master_valid = wr_cmd_vld | io_axi_ar_valid; // @[axi4_to_ahb.scala 140:30] - wire _T_101 = 3'h1 == buf_state; // @[Conditional.scala 37:30] - reg ahb_hready_q; // @[axi4_to_ahb.scala 321:52] - reg [1:0] ahb_htrans_q; // @[axi4_to_ahb.scala 322:52] - wire _T_108 = ahb_htrans_q != 2'h0; // @[axi4_to_ahb.scala 183:58] - wire _T_109 = ahb_hready_q & _T_108; // @[axi4_to_ahb.scala 183:36] - wire ahbm_addr_clk = rvclkhdr_8_io_l1clk; // @[axi4_to_ahb.scala 25:27 axi4_to_ahb.scala 334:17] - reg ahb_hwrite_q; // @[axi4_to_ahb.scala 323:57] - wire _T_110 = ~ahb_hwrite_q; // @[axi4_to_ahb.scala 183:72] - wire _T_111 = _T_109 & _T_110; // @[axi4_to_ahb.scala 183:70] - wire _T_136 = 3'h6 == buf_state; // @[Conditional.scala 37:30] - reg ahb_hresp_q; // @[axi4_to_ahb.scala 324:52] - wire _T_156 = ahb_hready_q | ahb_hresp_q; // @[axi4_to_ahb.scala 197:37] - wire _T_175 = 3'h7 == buf_state; // @[Conditional.scala 37:30] - wire _T_186 = 3'h3 == buf_state; // @[Conditional.scala 37:30] - wire _T_188 = 3'h2 == buf_state; // @[Conditional.scala 37:30] - wire _T_189 = ahb_hready_q & ahb_hwrite_q; // @[axi4_to_ahb.scala 229:33] - wire _T_192 = _T_189 & _T_108; // @[axi4_to_ahb.scala 229:48] - wire _T_281 = 3'h4 == buf_state; // @[Conditional.scala 37:30] - wire _GEN_15 = _T_281 & _T_192; // @[Conditional.scala 39:67] - wire _GEN_19 = _T_188 ? _T_192 : _GEN_15; // @[Conditional.scala 39:67] - wire _GEN_40 = _T_186 ? 1'h0 : _GEN_19; // @[Conditional.scala 39:67] - wire _GEN_59 = _T_175 ? 1'h0 : _GEN_40; // @[Conditional.scala 39:67] - wire _GEN_79 = _T_136 ? 1'h0 : _GEN_59; // @[Conditional.scala 39:67] - wire _GEN_95 = _T_101 ? 1'h0 : _GEN_79; // @[Conditional.scala 39:67] - wire trxn_done = _T_49 ? 1'h0 : _GEN_95; // @[Conditional.scala 40:58] - reg cmd_doneQ; // @[axi4_to_ahb.scala 319:52] - wire _T_282 = cmd_doneQ & ahb_hready_q; // @[axi4_to_ahb.scala 239:34] - wire _T_283 = _T_282 | ahb_hresp_q; // @[axi4_to_ahb.scala 239:50] - wire _T_440 = 3'h5 == buf_state; // @[Conditional.scala 37:30] - wire _GEN_3 = _T_281 ? _T_283 : _T_440; // @[Conditional.scala 39:67] - wire _GEN_20 = _T_188 ? trxn_done : _GEN_3; // @[Conditional.scala 39:67] - wire _GEN_35 = _T_186 ? _T_156 : _GEN_20; // @[Conditional.scala 39:67] - wire _GEN_51 = _T_175 ? _T_111 : _GEN_35; // @[Conditional.scala 39:67] - wire _GEN_69 = _T_136 ? _T_156 : _GEN_51; // @[Conditional.scala 39:67] - wire _GEN_83 = _T_101 ? _T_111 : _GEN_69; // @[Conditional.scala 39:67] - wire buf_state_en = _T_49 ? master_valid : _GEN_83; // @[Conditional.scala 40:58] - wire [1:0] _T_14 = wr_cmd_vld ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 142:20] - wire [2:0] master_opc = {{1'd0}, _T_14}; // @[axi4_to_ahb.scala 142:14] - wire _T_51 = master_opc[2:1] == 2'h1; // @[axi4_to_ahb.scala 168:41] - wire _GEN_8 = _T_281 & _T_51; // @[Conditional.scala 39:67] - wire _GEN_29 = _T_188 ? 1'h0 : _GEN_8; // @[Conditional.scala 39:67] - wire _GEN_46 = _T_186 ? 1'h0 : _GEN_29; // @[Conditional.scala 39:67] - wire _GEN_63 = _T_175 ? 1'h0 : _GEN_46; // @[Conditional.scala 39:67] - wire _GEN_81 = _T_136 ? 1'h0 : _GEN_63; // @[Conditional.scala 39:67] - wire _GEN_97 = _T_101 ? 1'h0 : _GEN_81; // @[Conditional.scala 39:67] - wire buf_write_in = _T_49 ? _T_51 : _GEN_97; // @[Conditional.scala 40:58] - wire [2:0] _T_53 = buf_write_in ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 169:26] - wire _T_103 = master_opc == 3'h0; // @[axi4_to_ahb.scala 182:61] - wire _T_104 = master_valid & _T_103; // @[axi4_to_ahb.scala 182:41] - wire [2:0] _T_106 = _T_104 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 182:26] - wire _T_124 = _T_106 == 3'h6; // @[axi4_to_ahb.scala 186:174] - wire _T_125 = _T_111 & _T_124; // @[axi4_to_ahb.scala 186:88] - wire _T_137 = ~ahb_hresp_q; // @[axi4_to_ahb.scala 194:39] - wire _T_138 = ahb_hready_q & _T_137; // @[axi4_to_ahb.scala 194:37] - wire _T_141 = master_valid & _T_51; // @[axi4_to_ahb.scala 194:70] - wire _T_142 = ~_T_141; // @[axi4_to_ahb.scala 194:55] - wire _T_143 = _T_138 & _T_142; // @[axi4_to_ahb.scala 194:53] - wire _T_285 = buf_state_en & _T_137; // @[axi4_to_ahb.scala 240:36] - wire _GEN_4 = _T_281 & _T_285; // @[Conditional.scala 39:67] - wire _GEN_26 = _T_188 ? 1'h0 : _GEN_4; // @[Conditional.scala 39:67] - wire _GEN_45 = _T_186 ? 1'h0 : _GEN_26; // @[Conditional.scala 39:67] - wire _GEN_62 = _T_175 ? 1'h0 : _GEN_45; // @[Conditional.scala 39:67] - wire _GEN_66 = _T_136 ? _T_143 : _GEN_62; // @[Conditional.scala 39:67] - wire _GEN_86 = _T_101 ? _T_125 : _GEN_66; // @[Conditional.scala 39:67] - wire master_ready = _T_49 | _GEN_86; // @[Conditional.scala 40:58] - wire _T_149 = master_valid & master_ready; // @[axi4_to_ahb.scala 196:82] - wire _T_152 = _T_149 & _T_103; // @[axi4_to_ahb.scala 196:97] - wire [2:0] _T_154 = _T_152 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 196:67] - wire [2:0] _T_155 = ahb_hresp_q ? 3'h7 : _T_154; // @[axi4_to_ahb.scala 196:26] - wire [2:0] _T_293 = _T_51 ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 241:99] - wire [2:0] _T_294 = master_valid ? _T_293 : 3'h0; // @[axi4_to_ahb.scala 241:65] - wire [2:0] _T_295 = ahb_hresp_q ? 3'h5 : _T_294; // @[axi4_to_ahb.scala 241:26] - wire [2:0] _GEN_5 = _T_281 ? _T_295 : 3'h0; // @[Conditional.scala 39:67] - wire [2:0] _GEN_18 = _T_188 ? 3'h4 : _GEN_5; // @[Conditional.scala 39:67] - wire [2:0] _GEN_34 = _T_186 ? 3'h5 : _GEN_18; // @[Conditional.scala 39:67] - wire [2:0] _GEN_50 = _T_175 ? 3'h3 : _GEN_34; // @[Conditional.scala 39:67] - wire [2:0] _GEN_68 = _T_136 ? _T_155 : _GEN_50; // @[Conditional.scala 39:67] - wire [2:0] _GEN_82 = _T_101 ? _T_106 : _GEN_68; // @[Conditional.scala 39:67] - wire [2:0] buf_nxtstate = _T_49 ? _T_53 : _GEN_82; // @[Conditional.scala 40:58] - reg [31:0] wrbuf_addr; // @[lib.scala 374:16] - wire [31:0] master_addr = wr_cmd_vld ? wrbuf_addr : io_axi_ar_bits_addr; // @[axi4_to_ahb.scala 143:21] - reg [2:0] wrbuf_size; // @[Reg.scala 27:20] - wire [2:0] master_size = wr_cmd_vld ? wrbuf_size : io_axi_ar_bits_size; // @[axi4_to_ahb.scala 144:21] - reg [7:0] wrbuf_byteen; // @[Reg.scala 27:20] - reg [63:0] wrbuf_data; // @[lib.scala 374:16] - wire _T_358 = buf_nxtstate != 3'h5; // @[axi4_to_ahb.scala 251:55] - wire _T_359 = buf_state_en & _T_358; // @[axi4_to_ahb.scala 251:39] - wire _GEN_14 = _T_281 ? _T_359 : _T_440; // @[Conditional.scala 39:67] - wire _GEN_33 = _T_188 ? 1'h0 : _GEN_14; // @[Conditional.scala 39:67] - wire _GEN_49 = _T_186 ? 1'h0 : _GEN_33; // @[Conditional.scala 39:67] - wire _GEN_52 = _T_175 ? buf_state_en : _GEN_49; // @[Conditional.scala 39:67] - wire _GEN_73 = _T_136 ? _T_285 : _GEN_52; // @[Conditional.scala 39:67] - wire _GEN_94 = _T_101 ? 1'h0 : _GEN_73; // @[Conditional.scala 39:67] - wire slave_valid_pre = _T_49 ? 1'h0 : _GEN_94; // @[Conditional.scala 40:58] - wire buf_clk = rvclkhdr_6_io_l1clk; // @[axi4_to_ahb.scala 118:21 axi4_to_ahb.scala 332:12] - reg slvbuf_write; // @[Reg.scala 27:20] - wire [1:0] _T_596 = slvbuf_write ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 285:23] - reg slvbuf_error; // @[Reg.scala 27:20] - wire [1:0] _T_598 = slvbuf_error ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_599 = _T_598 & 2'h2; // @[axi4_to_ahb.scala 285:88] - wire [3:0] slave_opc = {_T_596,_T_599}; // @[Cat.scala 29:58] - wire [1:0] _T_30 = slave_opc[1] ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 150:55] - wire _T_35 = slave_opc[3:2] == 2'h0; // @[axi4_to_ahb.scala 153:66] - reg [31:0] last_bus_addr; // @[Reg.scala 27:20] - wire [63:0] _T_603 = {last_bus_addr,last_bus_addr}; // @[Cat.scala 29:58] - wire _T_604 = buf_state == 3'h5; // @[axi4_to_ahb.scala 286:91] - reg [63:0] buf_data; // @[lib.scala 374:16] - wire ahbm_data_clk = rvclkhdr_9_io_l1clk; // @[axi4_to_ahb.scala 26:27 axi4_to_ahb.scala 335:17] - reg [63:0] ahb_hrdata_q; // @[axi4_to_ahb.scala 325:57] - wire [63:0] _T_607 = _T_604 ? buf_data : ahb_hrdata_q; // @[axi4_to_ahb.scala 286:79] - wire _T_44 = io_axi_aw_valid & io_axi_aw_ready; // @[axi4_to_ahb.scala 160:57] - wire _T_45 = io_axi_w_valid & io_axi_w_ready; // @[axi4_to_ahb.scala 160:94] - wire _T_46 = _T_44 | _T_45; // @[axi4_to_ahb.scala 160:76] - wire _T_55 = buf_nxtstate == 3'h2; // @[axi4_to_ahb.scala 172:54] - wire _T_56 = buf_state_en & _T_55; // @[axi4_to_ahb.scala 172:38] - wire [2:0] _T_87 = wrbuf_byteen[6] ? 3'h6 : 3'h7; // @[Mux.scala 98:16] - wire [2:0] _T_88 = wrbuf_byteen[5] ? 3'h5 : _T_87; // @[Mux.scala 98:16] - wire [2:0] _T_89 = wrbuf_byteen[4] ? 3'h4 : _T_88; // @[Mux.scala 98:16] - wire [2:0] _T_90 = wrbuf_byteen[3] ? 3'h3 : _T_89; // @[Mux.scala 98:16] - wire [2:0] _T_91 = wrbuf_byteen[2] ? 3'h2 : _T_90; // @[Mux.scala 98:16] - wire [2:0] _T_92 = wrbuf_byteen[1] ? 3'h1 : _T_91; // @[Mux.scala 98:16] - wire [2:0] _T_93 = wrbuf_byteen[0] ? 3'h0 : _T_92; // @[Mux.scala 98:16] - wire [2:0] _T_95 = buf_write_in ? _T_93 : master_addr[2:0]; // @[axi4_to_ahb.scala 175:30] - wire _T_96 = buf_nxtstate == 3'h1; // @[axi4_to_ahb.scala 177:51] - wire _T_126 = master_ready & master_valid; // @[axi4_to_ahb.scala 188:33] - wire _T_162 = buf_nxtstate == 3'h6; // @[axi4_to_ahb.scala 203:64] - wire _T_163 = _T_126 & _T_162; // @[axi4_to_ahb.scala 203:48] - wire _T_164 = _T_163 & buf_state_en; // @[axi4_to_ahb.scala 203:79] - wire _T_349 = buf_state_en & buf_write_in; // @[axi4_to_ahb.scala 249:33] - wire _T_351 = _T_349 & _T_55; // @[axi4_to_ahb.scala 249:48] - wire _GEN_12 = _T_281 & _T_351; // @[Conditional.scala 39:67] - wire _GEN_32 = _T_188 ? 1'h0 : _GEN_12; // @[Conditional.scala 39:67] - wire _GEN_48 = _T_186 ? 1'h0 : _GEN_32; // @[Conditional.scala 39:67] - wire _GEN_65 = _T_175 ? 1'h0 : _GEN_48; // @[Conditional.scala 39:67] - wire _GEN_75 = _T_136 ? _T_164 : _GEN_65; // @[Conditional.scala 39:67] - wire _GEN_88 = _T_101 ? _T_126 : _GEN_75; // @[Conditional.scala 39:67] - wire bypass_en = _T_49 ? buf_state_en : _GEN_88; // @[Conditional.scala 40:58] - wire [1:0] _T_99 = bypass_en ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_100 = _T_99 & 2'h2; // @[axi4_to_ahb.scala 178:49] - wire _T_112 = ~master_valid; // @[axi4_to_ahb.scala 184:34] - wire _T_113 = buf_state_en & _T_112; // @[axi4_to_ahb.scala 184:32] - reg [31:0] buf_addr; // @[lib.scala 374:16] - wire [2:0] _T_130 = bypass_en ? master_addr[2:0] : buf_addr[2:0]; // @[axi4_to_ahb.scala 189:30] - wire _T_131 = ~buf_state_en; // @[axi4_to_ahb.scala 190:48] - wire _T_132 = _T_131 | bypass_en; // @[axi4_to_ahb.scala 190:62] - wire [1:0] _T_134 = _T_132 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_135 = 2'h2 & _T_134; // @[axi4_to_ahb.scala 190:36] - wire _T_169 = buf_nxtstate != 3'h6; // @[axi4_to_ahb.scala 205:63] - wire _T_170 = _T_169 & buf_state_en; // @[axi4_to_ahb.scala 205:78] - wire _T_171 = ~_T_170; // @[axi4_to_ahb.scala 205:47] - wire [1:0] _T_173 = _T_171 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_174 = 2'h2 & _T_173; // @[axi4_to_ahb.scala 205:36] - wire [1:0] _T_184 = _T_131 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_185 = 2'h2 & _T_184; // @[axi4_to_ahb.scala 215:41] - reg [2:0] buf_cmd_byte_ptrQ; // @[Reg.scala 27:20] - reg [7:0] buf_byteen; // @[Reg.scala 27:20] - wire [2:0] _T_197 = buf_cmd_byte_ptrQ + 3'h1; // @[axi4_to_ahb.scala 135:52] - wire _T_200 = 3'h0 >= _T_197; // @[axi4_to_ahb.scala 136:62] - wire _T_201 = buf_byteen[0] & _T_200; // @[axi4_to_ahb.scala 136:48] - wire _T_203 = 3'h1 >= _T_197; // @[axi4_to_ahb.scala 136:62] - wire _T_204 = buf_byteen[1] & _T_203; // @[axi4_to_ahb.scala 136:48] - wire _T_206 = 3'h2 >= _T_197; // @[axi4_to_ahb.scala 136:62] - wire _T_207 = buf_byteen[2] & _T_206; // @[axi4_to_ahb.scala 136:48] - wire _T_209 = 3'h3 >= _T_197; // @[axi4_to_ahb.scala 136:62] - wire _T_210 = buf_byteen[3] & _T_209; // @[axi4_to_ahb.scala 136:48] - wire _T_212 = 3'h4 >= _T_197; // @[axi4_to_ahb.scala 136:62] - wire _T_213 = buf_byteen[4] & _T_212; // @[axi4_to_ahb.scala 136:48] - wire _T_215 = 3'h5 >= _T_197; // @[axi4_to_ahb.scala 136:62] - wire _T_216 = buf_byteen[5] & _T_215; // @[axi4_to_ahb.scala 136:48] - wire _T_218 = 3'h6 >= _T_197; // @[axi4_to_ahb.scala 136:62] - wire _T_219 = buf_byteen[6] & _T_218; // @[axi4_to_ahb.scala 136:48] - wire [2:0] _T_224 = _T_219 ? 3'h6 : 3'h7; // @[Mux.scala 98:16] - wire [2:0] _T_225 = _T_216 ? 3'h5 : _T_224; // @[Mux.scala 98:16] - wire [2:0] _T_226 = _T_213 ? 3'h4 : _T_225; // @[Mux.scala 98:16] - wire [2:0] _T_227 = _T_210 ? 3'h3 : _T_226; // @[Mux.scala 98:16] - wire [2:0] _T_228 = _T_207 ? 3'h2 : _T_227; // @[Mux.scala 98:16] - wire [2:0] _T_229 = _T_204 ? 3'h1 : _T_228; // @[Mux.scala 98:16] - wire [2:0] _T_230 = _T_201 ? 3'h0 : _T_229; // @[Mux.scala 98:16] - wire [2:0] _T_231 = trxn_done ? _T_230 : buf_cmd_byte_ptrQ; // @[axi4_to_ahb.scala 233:30] - wire _T_232 = buf_cmd_byte_ptrQ == 3'h7; // @[axi4_to_ahb.scala 234:65] - reg buf_aligned; // @[Reg.scala 27:20] - wire _T_233 = buf_aligned | _T_232; // @[axi4_to_ahb.scala 234:44] - wire [7:0] _T_271 = buf_byteen >> _T_230; // @[axi4_to_ahb.scala 234:92] - wire _T_273 = ~_T_271[0]; // @[axi4_to_ahb.scala 234:163] - wire _T_274 = _T_233 | _T_273; // @[axi4_to_ahb.scala 234:79] - wire _T_275 = trxn_done & _T_274; // @[axi4_to_ahb.scala 234:29] - wire _T_346 = _T_232 | _T_273; // @[axi4_to_ahb.scala 248:38] - wire _T_347 = _T_109 & _T_346; // @[axi4_to_ahb.scala 247:80] - wire _T_348 = ahb_hresp_q | _T_347; // @[axi4_to_ahb.scala 247:34] - wire _GEN_11 = _T_281 & _T_348; // @[Conditional.scala 39:67] - wire _GEN_24 = _T_188 ? _T_275 : _GEN_11; // @[Conditional.scala 39:67] - wire _GEN_43 = _T_186 ? 1'h0 : _GEN_24; // @[Conditional.scala 39:67] - wire _GEN_61 = _T_175 ? 1'h0 : _GEN_43; // @[Conditional.scala 39:67] - wire _GEN_74 = _T_136 ? _T_113 : _GEN_61; // @[Conditional.scala 39:67] - wire _GEN_84 = _T_101 ? _T_113 : _GEN_74; // @[Conditional.scala 39:67] - wire cmd_done = _T_49 ? 1'h0 : _GEN_84; // @[Conditional.scala 40:58] - wire _T_276 = cmd_done | cmd_doneQ; // @[axi4_to_ahb.scala 235:47] - wire _T_277 = ~_T_276; // @[axi4_to_ahb.scala 235:36] - wire [1:0] _T_279 = _T_277 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_280 = _T_279 & 2'h2; // @[axi4_to_ahb.scala 235:61] - wire _T_300 = _T_55 | _T_96; // @[axi4_to_ahb.scala 245:62] - wire _T_301 = buf_state_en & _T_300; // @[axi4_to_ahb.scala 245:33] - wire _T_354 = _T_277 | bypass_en; // @[axi4_to_ahb.scala 250:61] - wire [1:0] _T_356 = _T_354 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_357 = _T_356 & 2'h2; // @[axi4_to_ahb.scala 250:75] - wire _T_364 = trxn_done | bypass_en; // @[axi4_to_ahb.scala 253:40] - wire [2:0] _T_439 = bypass_en ? _T_93 : _T_231; // @[axi4_to_ahb.scala 254:30] - wire _GEN_6 = _T_281 & ahb_hresp_q; // @[Conditional.scala 39:67] - wire _GEN_7 = _T_281 ? buf_state_en : _T_440; // @[Conditional.scala 39:67] - wire _GEN_9 = _T_281 & _T_301; // @[Conditional.scala 39:67] - wire _GEN_30 = _T_188 ? 1'h0 : _GEN_9; // @[Conditional.scala 39:67] - wire _GEN_47 = _T_186 ? 1'h0 : _GEN_30; // @[Conditional.scala 39:67] - wire _GEN_64 = _T_175 ? 1'h0 : _GEN_47; // @[Conditional.scala 39:67] - wire _GEN_67 = _T_136 ? _T_152 : _GEN_64; // @[Conditional.scala 39:67] - wire _GEN_87 = _T_101 ? master_ready : _GEN_67; // @[Conditional.scala 39:67] - wire buf_wr_en = _T_49 ? buf_state_en : _GEN_87; // @[Conditional.scala 40:58] - wire _GEN_10 = _T_281 & buf_wr_en; // @[Conditional.scala 39:67] - wire [1:0] _GEN_13 = _T_281 ? _T_357 : 2'h0; // @[Conditional.scala 39:67] - wire _GEN_16 = _T_281 & _T_364; // @[Conditional.scala 39:67] - wire [2:0] _GEN_17 = _T_281 ? _T_439 : 3'h0; // @[Conditional.scala 39:67] - wire _GEN_21 = _T_188 ? buf_state_en : _GEN_16; // @[Conditional.scala 39:67] - wire _GEN_22 = _T_188 & buf_state_en; // @[Conditional.scala 39:67] - wire [2:0] _GEN_23 = _T_188 ? _T_231 : _GEN_17; // @[Conditional.scala 39:67] - wire [1:0] _GEN_25 = _T_188 ? _T_280 : _GEN_13; // @[Conditional.scala 39:67] - wire _GEN_28 = _T_188 ? 1'h0 : _GEN_7; // @[Conditional.scala 39:67] - wire _GEN_31 = _T_188 ? 1'h0 : _GEN_10; // @[Conditional.scala 39:67] - wire _GEN_36 = _T_186 ? buf_state_en : _GEN_31; // @[Conditional.scala 39:67] - wire _GEN_38 = _T_186 ? buf_state_en : _GEN_28; // @[Conditional.scala 39:67] - wire _GEN_39 = _T_186 ? buf_state_en : _GEN_22; // @[Conditional.scala 39:67] - wire _GEN_41 = _T_186 ? 1'h0 : _GEN_21; // @[Conditional.scala 39:67] - wire [2:0] _GEN_42 = _T_186 ? 3'h0 : _GEN_23; // @[Conditional.scala 39:67] - wire [1:0] _GEN_44 = _T_186 ? 2'h0 : _GEN_25; // @[Conditional.scala 39:67] - wire _GEN_53 = _T_175 ? buf_state_en : _GEN_39; // @[Conditional.scala 39:67] - wire [2:0] _GEN_54 = _T_175 ? buf_addr[2:0] : _GEN_42; // @[Conditional.scala 39:67] - wire [1:0] _GEN_55 = _T_175 ? _T_185 : _GEN_44; // @[Conditional.scala 39:67] - wire _GEN_56 = _T_175 ? 1'h0 : _GEN_36; // @[Conditional.scala 39:67] - wire _GEN_58 = _T_175 ? 1'h0 : _GEN_38; // @[Conditional.scala 39:67] - wire _GEN_60 = _T_175 ? 1'h0 : _GEN_41; // @[Conditional.scala 39:67] - wire _GEN_70 = _T_136 ? buf_state_en : _GEN_56; // @[Conditional.scala 39:67] - wire _GEN_72 = _T_136 ? buf_state_en : _GEN_58; // @[Conditional.scala 39:67] - wire [2:0] _GEN_76 = _T_136 ? _T_130 : _GEN_54; // @[Conditional.scala 39:67] - wire [1:0] _GEN_77 = _T_136 ? _T_174 : _GEN_55; // @[Conditional.scala 39:67] - wire _GEN_78 = _T_136 ? buf_wr_en : _GEN_53; // @[Conditional.scala 39:67] - wire _GEN_80 = _T_136 ? 1'h0 : _GEN_60; // @[Conditional.scala 39:67] - wire _GEN_85 = _T_101 ? buf_state_en : _GEN_78; // @[Conditional.scala 39:67] - wire [2:0] _GEN_89 = _T_101 ? _T_130 : _GEN_76; // @[Conditional.scala 39:67] - wire [1:0] _GEN_90 = _T_101 ? _T_135 : _GEN_77; // @[Conditional.scala 39:67] - wire _GEN_91 = _T_101 ? 1'h0 : _GEN_70; // @[Conditional.scala 39:67] - wire _GEN_93 = _T_101 ? 1'h0 : _GEN_72; // @[Conditional.scala 39:67] - wire _GEN_96 = _T_101 ? 1'h0 : _GEN_80; // @[Conditional.scala 39:67] - wire buf_data_wr_en = _T_49 ? _T_56 : _GEN_91; // @[Conditional.scala 40:58] - wire buf_cmd_byte_ptr_en = _T_49 ? buf_state_en : _GEN_96; // @[Conditional.scala 40:58] - wire [2:0] buf_cmd_byte_ptr = _T_49 ? _T_95 : _GEN_89; // @[Conditional.scala 40:58] - wire slvbuf_wr_en = _T_49 ? 1'h0 : _GEN_85; // @[Conditional.scala 40:58] - wire slvbuf_error_en = _T_49 ? 1'h0 : _GEN_93; // @[Conditional.scala 40:58] - wire _T_535 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 271:24] - wire _T_536 = _T_103 | _T_535; // @[axi4_to_ahb.scala 270:48] - wire _T_538 = master_size[1:0] == 2'h1; // @[axi4_to_ahb.scala 271:54] - wire _T_539 = _T_536 | _T_538; // @[axi4_to_ahb.scala 271:33] - wire _T_541 = master_size[1:0] == 2'h2; // @[axi4_to_ahb.scala 271:93] - wire _T_542 = _T_539 | _T_541; // @[axi4_to_ahb.scala 271:72] - wire _T_544 = master_size[1:0] == 2'h3; // @[axi4_to_ahb.scala 272:25] - wire _T_546 = wrbuf_byteen == 8'h3; // @[axi4_to_ahb.scala 272:62] - wire _T_548 = wrbuf_byteen == 8'hc; // @[axi4_to_ahb.scala 272:97] - wire _T_549 = _T_546 | _T_548; // @[axi4_to_ahb.scala 272:74] - wire _T_551 = wrbuf_byteen == 8'h30; // @[axi4_to_ahb.scala 272:132] - wire _T_552 = _T_549 | _T_551; // @[axi4_to_ahb.scala 272:109] - wire _T_554 = wrbuf_byteen == 8'hc0; // @[axi4_to_ahb.scala 272:168] - wire _T_555 = _T_552 | _T_554; // @[axi4_to_ahb.scala 272:145] - wire _T_557 = wrbuf_byteen == 8'hf; // @[axi4_to_ahb.scala 273:28] - wire _T_558 = _T_555 | _T_557; // @[axi4_to_ahb.scala 272:181] - wire _T_560 = wrbuf_byteen == 8'hf0; // @[axi4_to_ahb.scala 273:63] - wire _T_561 = _T_558 | _T_560; // @[axi4_to_ahb.scala 273:40] - wire _T_563 = wrbuf_byteen == 8'hff; // @[axi4_to_ahb.scala 273:99] - wire _T_564 = _T_561 | _T_563; // @[axi4_to_ahb.scala 273:76] - wire _T_565 = _T_544 & _T_564; // @[axi4_to_ahb.scala 272:38] - wire buf_aligned_in = _T_542 | _T_565; // @[axi4_to_ahb.scala 271:106] - wire _T_444 = buf_aligned_in & _T_51; // @[axi4_to_ahb.scala 265:60] - wire [2:0] _T_461 = _T_548 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_462 = 3'h2 & _T_461; // @[axi4_to_ahb.scala 128:15] - wire _T_468 = _T_560 | _T_546; // @[axi4_to_ahb.scala 129:56] - wire [2:0] _T_470 = _T_468 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_471 = 3'h4 & _T_470; // @[axi4_to_ahb.scala 129:15] - wire [2:0] _T_472 = _T_462 | _T_471; // @[axi4_to_ahb.scala 128:63] - wire [2:0] _T_476 = _T_554 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_477 = 3'h6 & _T_476; // @[axi4_to_ahb.scala 130:15] - wire [2:0] _T_478 = _T_472 | _T_477; // @[axi4_to_ahb.scala 129:96] - wire [2:0] _T_485 = _T_444 ? _T_478 : master_addr[2:0]; // @[axi4_to_ahb.scala 265:43] - wire _T_489 = buf_state == 3'h3; // @[axi4_to_ahb.scala 268:33] - wire _T_495 = buf_aligned_in & _T_544; // @[axi4_to_ahb.scala 269:38] - wire _T_498 = _T_495 & _T_51; // @[axi4_to_ahb.scala 269:71] - wire [1:0] _T_504 = _T_563 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire _T_510 = _T_560 | _T_557; // @[axi4_to_ahb.scala 122:55] - wire [1:0] _T_512 = _T_510 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_513 = 2'h2 & _T_512; // @[axi4_to_ahb.scala 122:16] - wire [1:0] _T_514 = _T_504 | _T_513; // @[axi4_to_ahb.scala 121:64] - wire _T_519 = _T_554 | _T_551; // @[axi4_to_ahb.scala 123:60] - wire _T_522 = _T_519 | _T_548; // @[axi4_to_ahb.scala 123:89] - wire _T_525 = _T_522 | _T_546; // @[axi4_to_ahb.scala 123:123] - wire [1:0] _T_527 = _T_525 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_528 = 2'h1 & _T_527; // @[axi4_to_ahb.scala 123:21] - wire [1:0] _T_529 = _T_514 | _T_528; // @[axi4_to_ahb.scala 122:93] - wire [1:0] _T_531 = _T_498 ? _T_529 : master_size[1:0]; // @[axi4_to_ahb.scala 269:21] - wire [31:0] _T_570 = {master_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] - wire [31:0] _T_573 = {buf_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] - wire [1:0] _T_577 = buf_aligned_in ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [2:0] buf_size_in = {{1'd0}, _T_531}; // @[axi4_to_ahb.scala 269:15] - wire [1:0] _T_579 = _T_577 & buf_size_in[1:0]; // @[axi4_to_ahb.scala 276:81] - wire [2:0] _T_580 = {1'h0,_T_579}; // @[Cat.scala 29:58] - wire [1:0] _T_582 = buf_aligned ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - reg [1:0] buf_size; // @[Reg.scala 27:20] - wire [1:0] _T_584 = _T_582 & buf_size; // @[axi4_to_ahb.scala 276:138] - wire [2:0] _T_585 = {1'h0,_T_584}; // @[Cat.scala 29:58] - reg buf_write; // @[Reg.scala 27:20] - wire _T_611 = io_ahb_out_htrans != 2'h0; // @[axi4_to_ahb.scala 289:44] - wire _T_612 = _T_611 & io_ahb_in_hready; // @[axi4_to_ahb.scala 289:56] - wire last_addr_en = _T_612 & io_ahb_out_hwrite; // @[axi4_to_ahb.scala 289:75] - wire wrbuf_en = _T_44 & master_ready; // @[axi4_to_ahb.scala 291:49] - wire wrbuf_data_en = _T_45 & master_ready; // @[axi4_to_ahb.scala 292:52] - wire wrbuf_cmd_sent = _T_149 & _T_51; // @[axi4_to_ahb.scala 293:49] - wire _T_622 = ~wrbuf_en; // @[axi4_to_ahb.scala 294:33] - wire wrbuf_rst = wrbuf_cmd_sent & _T_622; // @[axi4_to_ahb.scala 294:31] - wire _T_624 = ~wrbuf_cmd_sent; // @[axi4_to_ahb.scala 296:36] - wire _T_625 = wrbuf_vld & _T_624; // @[axi4_to_ahb.scala 296:34] - wire _T_626 = ~_T_625; // @[axi4_to_ahb.scala 296:22] - wire _T_629 = wrbuf_data_vld & _T_624; // @[axi4_to_ahb.scala 297:38] - wire _T_630 = ~_T_629; // @[axi4_to_ahb.scala 297:21] - wire _T_633 = ~wr_cmd_vld; // @[axi4_to_ahb.scala 298:22] - wire _T_636 = wrbuf_en | wrbuf_vld; // @[axi4_to_ahb.scala 301:55] - wire _T_637 = ~wrbuf_rst; // @[axi4_to_ahb.scala 301:91] - wire _T_641 = wrbuf_data_en | wrbuf_data_vld; // @[axi4_to_ahb.scala 302:55] - wire _T_691 = ~slave_valid_pre; // @[axi4_to_ahb.scala 319:92] - wire _T_704 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 327:43] - wire _T_705 = _T_704 | io_clk_override; // @[axi4_to_ahb.scala 327:58] - wire _T_708 = io_ahb_in_hready & io_ahb_out_htrans[1]; // @[axi4_to_ahb.scala 328:57] - wire _T_709 = _T_708 | io_clk_override; // @[axi4_to_ahb.scala 328:81] - wire _T_711 = buf_state != 3'h0; // @[axi4_to_ahb.scala 329:50] - wire _T_712 = _T_711 | io_clk_override; // @[axi4_to_ahb.scala 329:60] - rvclkhdr rvclkhdr ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_io_l1clk), - .io_clk(rvclkhdr_io_clk), - .io_en(rvclkhdr_io_en), - .io_scan_mode(rvclkhdr_io_scan_mode) - ); - rvclkhdr rvclkhdr_1 ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_1_io_l1clk), - .io_clk(rvclkhdr_1_io_clk), - .io_en(rvclkhdr_1_io_en), - .io_scan_mode(rvclkhdr_1_io_scan_mode) - ); - rvclkhdr rvclkhdr_2 ( // @[lib.scala 368:23] - .io_l1clk(rvclkhdr_2_io_l1clk), - .io_clk(rvclkhdr_2_io_clk), - .io_en(rvclkhdr_2_io_en), - .io_scan_mode(rvclkhdr_2_io_scan_mode) - ); - rvclkhdr rvclkhdr_3 ( // @[lib.scala 368:23] - .io_l1clk(rvclkhdr_3_io_l1clk), - .io_clk(rvclkhdr_3_io_clk), - .io_en(rvclkhdr_3_io_en), - .io_scan_mode(rvclkhdr_3_io_scan_mode) - ); - rvclkhdr rvclkhdr_4 ( // @[lib.scala 368:23] - .io_l1clk(rvclkhdr_4_io_l1clk), - .io_clk(rvclkhdr_4_io_clk), - .io_en(rvclkhdr_4_io_en), - .io_scan_mode(rvclkhdr_4_io_scan_mode) - ); - rvclkhdr rvclkhdr_5 ( // @[lib.scala 368:23] - .io_l1clk(rvclkhdr_5_io_l1clk), - .io_clk(rvclkhdr_5_io_clk), - .io_en(rvclkhdr_5_io_en), - .io_scan_mode(rvclkhdr_5_io_scan_mode) - ); - rvclkhdr rvclkhdr_6 ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_6_io_l1clk), - .io_clk(rvclkhdr_6_io_clk), - .io_en(rvclkhdr_6_io_en), - .io_scan_mode(rvclkhdr_6_io_scan_mode) - ); - rvclkhdr rvclkhdr_7 ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_7_io_l1clk), - .io_clk(rvclkhdr_7_io_clk), - .io_en(rvclkhdr_7_io_en), - .io_scan_mode(rvclkhdr_7_io_scan_mode) - ); - rvclkhdr rvclkhdr_8 ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_8_io_l1clk), - .io_clk(rvclkhdr_8_io_clk), - .io_en(rvclkhdr_8_io_en), - .io_scan_mode(rvclkhdr_8_io_scan_mode) - ); - rvclkhdr rvclkhdr_9 ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_9_io_l1clk), - .io_clk(rvclkhdr_9_io_clk), - .io_en(rvclkhdr_9_io_en), - .io_scan_mode(rvclkhdr_9_io_scan_mode) - ); - assign io_axi_aw_ready = _T_626 & master_ready; // @[axi4_to_ahb.scala 296:19] - assign io_axi_w_ready = _T_630 & master_ready; // @[axi4_to_ahb.scala 297:18] - assign io_axi_b_valid = slave_valid_pre & slave_opc[3]; // @[axi4_to_ahb.scala 149:18] - assign io_axi_b_bits_resp = slave_opc[0] ? 2'h2 : _T_30; // @[axi4_to_ahb.scala 150:22] - assign io_axi_ar_ready = _T_633 & master_ready; // @[axi4_to_ahb.scala 298:19] - assign io_axi_r_valid = slave_valid_pre & _T_35; // @[axi4_to_ahb.scala 153:18] - assign io_axi_r_bits_data = slvbuf_error ? _T_603 : _T_607; // @[axi4_to_ahb.scala 156:22] - assign io_axi_r_bits_resp = slave_opc[0] ? 2'h2 : _T_30; // @[axi4_to_ahb.scala 154:22] - assign io_ahb_out_haddr = bypass_en ? _T_570 : _T_573; // @[axi4_to_ahb.scala 275:20] - assign io_ahb_out_hsize = bypass_en ? _T_580 : _T_585; // @[axi4_to_ahb.scala 276:20] - assign io_ahb_out_htrans = _T_49 ? _T_100 : _GEN_90; // @[axi4_to_ahb.scala 22:21 axi4_to_ahb.scala 178:25 axi4_to_ahb.scala 190:25 axi4_to_ahb.scala 205:25 axi4_to_ahb.scala 215:25 axi4_to_ahb.scala 235:25 axi4_to_ahb.scala 250:25] - assign io_ahb_out_hwrite = bypass_en ? _T_51 : buf_write; // @[axi4_to_ahb.scala 281:21] - assign io_ahb_out_hwdata = buf_data; // @[axi4_to_ahb.scala 282:21] - assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_io_en = io_bus_clk_en; // @[lib.scala 345:16] - assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign rvclkhdr_1_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_1_io_en = io_bus_clk_en & _T_46; // @[lib.scala 345:16] - assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign rvclkhdr_2_io_clk = rvclkhdr_io_l1clk; // @[lib.scala 370:18] - assign rvclkhdr_2_io_en = _T_44 & master_ready; // @[lib.scala 371:17] - assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] - assign rvclkhdr_3_io_clk = rvclkhdr_io_l1clk; // @[lib.scala 370:18] - assign rvclkhdr_3_io_en = _T_45 & master_ready; // @[lib.scala 371:17] - assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] - assign rvclkhdr_4_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_4_io_en = buf_wr_en & io_bus_clk_en; // @[lib.scala 371:17] - assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] - assign rvclkhdr_5_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_5_io_en = buf_data_wr_en & io_bus_clk_en; // @[lib.scala 371:17] - assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] - assign rvclkhdr_6_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_6_io_en = io_bus_clk_en & _T_705; // @[lib.scala 345:16] - assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign rvclkhdr_7_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_7_io_en = io_bus_clk_en; // @[lib.scala 345:16] - assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign rvclkhdr_8_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_8_io_en = io_bus_clk_en & _T_709; // @[lib.scala 345:16] - assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign rvclkhdr_9_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_9_io_en = io_bus_clk_en & _T_712; // @[lib.scala 345:16] - assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] -`ifdef RANDOMIZE_GARBAGE_ASSIGN -`define RANDOMIZE -`endif -`ifdef RANDOMIZE_INVALID_ASSIGN -`define RANDOMIZE -`endif -`ifdef RANDOMIZE_REG_INIT -`define RANDOMIZE -`endif -`ifdef RANDOMIZE_MEM_INIT -`define RANDOMIZE -`endif -`ifndef RANDOM -`define RANDOM $random -`endif -`ifdef RANDOMIZE_MEM_INIT - integer initvar; -`endif -`ifndef SYNTHESIS -`ifdef FIRRTL_BEFORE_INITIAL -`FIRRTL_BEFORE_INITIAL -`endif -initial begin - `ifdef RANDOMIZE - `ifdef INIT_RANDOM - `INIT_RANDOM - `endif - `ifndef VERILATOR - `ifdef RANDOMIZE_DELAY - #`RANDOMIZE_DELAY begin end - `else - #0.002 begin end - `endif - `endif -`ifdef RANDOMIZE_REG_INIT - _RAND_0 = {1{`RANDOM}}; - buf_state = _RAND_0[2:0]; - _RAND_1 = {1{`RANDOM}}; - wrbuf_vld = _RAND_1[0:0]; - _RAND_2 = {1{`RANDOM}}; - wrbuf_data_vld = _RAND_2[0:0]; - _RAND_3 = {1{`RANDOM}}; - ahb_hready_q = _RAND_3[0:0]; - _RAND_4 = {1{`RANDOM}}; - ahb_htrans_q = _RAND_4[1:0]; - _RAND_5 = {1{`RANDOM}}; - ahb_hwrite_q = _RAND_5[0:0]; - _RAND_6 = {1{`RANDOM}}; - ahb_hresp_q = _RAND_6[0:0]; - _RAND_7 = {1{`RANDOM}}; - cmd_doneQ = _RAND_7[0:0]; - _RAND_8 = {1{`RANDOM}}; - wrbuf_addr = _RAND_8[31:0]; - _RAND_9 = {1{`RANDOM}}; - wrbuf_size = _RAND_9[2:0]; - _RAND_10 = {1{`RANDOM}}; - wrbuf_byteen = _RAND_10[7:0]; - _RAND_11 = {2{`RANDOM}}; - wrbuf_data = _RAND_11[63:0]; - _RAND_12 = {1{`RANDOM}}; - slvbuf_write = _RAND_12[0:0]; - _RAND_13 = {1{`RANDOM}}; - slvbuf_error = _RAND_13[0:0]; - _RAND_14 = {1{`RANDOM}}; - last_bus_addr = _RAND_14[31:0]; - _RAND_15 = {2{`RANDOM}}; - buf_data = _RAND_15[63:0]; - _RAND_16 = {2{`RANDOM}}; - ahb_hrdata_q = _RAND_16[63:0]; - _RAND_17 = {1{`RANDOM}}; - buf_addr = _RAND_17[31:0]; - _RAND_18 = {1{`RANDOM}}; - buf_cmd_byte_ptrQ = _RAND_18[2:0]; - _RAND_19 = {1{`RANDOM}}; - buf_byteen = _RAND_19[7:0]; - _RAND_20 = {1{`RANDOM}}; - buf_aligned = _RAND_20[0:0]; - _RAND_21 = {1{`RANDOM}}; - buf_size = _RAND_21[1:0]; - _RAND_22 = {1{`RANDOM}}; - buf_write = _RAND_22[0:0]; -`endif // RANDOMIZE_REG_INIT - if (reset) begin - buf_state = 3'h0; - end - if (reset) begin - wrbuf_vld = 1'h0; - end - if (reset) begin - wrbuf_data_vld = 1'h0; - end - if (reset) begin - ahb_hready_q = 1'h0; - end - if (reset) begin - ahb_htrans_q = 2'h0; - end - if (reset) begin - ahb_hwrite_q = 1'h0; - end - if (reset) begin - ahb_hresp_q = 1'h0; - end - if (reset) begin - cmd_doneQ = 1'h0; - end - if (reset) begin - wrbuf_addr = 32'h0; - end - if (reset) begin - wrbuf_size = 3'h0; - end - if (reset) begin - wrbuf_byteen = 8'h0; - end - if (reset) begin - wrbuf_data = 64'h0; - end - if (reset) begin - slvbuf_write = 1'h0; - end - if (reset) begin - slvbuf_error = 1'h0; - end - if (reset) begin - last_bus_addr = 32'h0; - end - if (reset) begin - buf_data = 64'h0; - end - if (reset) begin - ahb_hrdata_q = 64'h0; - end - if (reset) begin - buf_addr = 32'h0; - end - if (reset) begin - buf_cmd_byte_ptrQ = 3'h0; - end - if (reset) begin - buf_byteen = 8'h0; - end - if (reset) begin - buf_aligned = 1'h0; - end - if (reset) begin - buf_size = 2'h0; - end - if (reset) begin - buf_write = 1'h0; - end - `endif // RANDOMIZE -end // initial -`ifdef FIRRTL_AFTER_INITIAL -`FIRRTL_AFTER_INITIAL -`endif -`endif // SYNTHESIS - always @(posedge ahbm_clk or posedge reset) begin - if (reset) begin - buf_state <= 3'h0; - end else if (buf_state_en) begin - if (_T_49) begin - if (buf_write_in) begin - buf_state <= 3'h2; - end else begin - buf_state <= 3'h1; - end - end else if (_T_101) begin - if (_T_104) begin - buf_state <= 3'h6; - end else begin - buf_state <= 3'h3; - end - end else if (_T_136) begin - if (ahb_hresp_q) begin - buf_state <= 3'h7; - end else if (_T_152) begin - buf_state <= 3'h6; - end else begin - buf_state <= 3'h3; - end - end else if (_T_175) begin - buf_state <= 3'h3; - end else if (_T_186) begin - buf_state <= 3'h5; - end else if (_T_188) begin - buf_state <= 3'h4; - end else if (_T_281) begin - if (ahb_hresp_q) begin - buf_state <= 3'h5; - end else if (master_valid) begin - if (_T_51) begin - buf_state <= 3'h2; - end else begin - buf_state <= 3'h1; - end - end else begin - buf_state <= 3'h0; - end - end else begin - buf_state <= 3'h0; - end - end - end - always @(posedge bus_clk or posedge reset) begin - if (reset) begin - wrbuf_vld <= 1'h0; - end else begin - wrbuf_vld <= _T_636 & _T_637; - end - end - always @(posedge bus_clk or posedge reset) begin - if (reset) begin - wrbuf_data_vld <= 1'h0; - end else begin - wrbuf_data_vld <= _T_641 & _T_637; - end - end - always @(posedge ahbm_clk or posedge reset) begin - if (reset) begin - ahb_hready_q <= 1'h0; - end else begin - ahb_hready_q <= io_ahb_in_hready; - end - end - always @(posedge ahbm_clk or posedge reset) begin - if (reset) begin - ahb_htrans_q <= 2'h0; - end else begin - ahb_htrans_q <= io_ahb_out_htrans; - end - end - always @(posedge ahbm_addr_clk or posedge reset) begin - if (reset) begin - ahb_hwrite_q <= 1'h0; - end else begin - ahb_hwrite_q <= io_ahb_out_hwrite; - end - end - always @(posedge ahbm_clk or posedge reset) begin - if (reset) begin - ahb_hresp_q <= 1'h0; - end else begin - ahb_hresp_q <= io_ahb_in_hresp; - end - end - always @(posedge ahbm_clk or posedge reset) begin - if (reset) begin - cmd_doneQ <= 1'h0; - end else begin - cmd_doneQ <= _T_276 & _T_691; - end - end - always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin - if (reset) begin - wrbuf_addr <= 32'h0; - end else begin - wrbuf_addr <= io_axi_aw_bits_addr; - end - end - always @(posedge bus_clk or posedge reset) begin - if (reset) begin - wrbuf_size <= 3'h0; - end else if (wrbuf_en) begin - wrbuf_size <= io_axi_aw_bits_size; - end - end - always @(posedge bus_clk or posedge reset) begin - if (reset) begin - wrbuf_byteen <= 8'h0; - end else if (wrbuf_data_en) begin - wrbuf_byteen <= io_axi_w_bits_strb; - end - end - always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin - if (reset) begin - wrbuf_data <= 64'h0; - end else begin - wrbuf_data <= io_axi_w_bits_data; - end - end - always @(posedge buf_clk or posedge reset) begin - if (reset) begin - slvbuf_write <= 1'h0; - end else if (slvbuf_wr_en) begin - slvbuf_write <= buf_write; - end - end - always @(posedge ahbm_clk or posedge reset) begin - if (reset) begin - slvbuf_error <= 1'h0; - end else if (slvbuf_error_en) begin - if (_T_49) begin - slvbuf_error <= 1'h0; - end else if (_T_101) begin - slvbuf_error <= 1'h0; - end else if (_T_136) begin - slvbuf_error <= ahb_hresp_q; - end else if (_T_175) begin - slvbuf_error <= 1'h0; - end else if (_T_186) begin - slvbuf_error <= ahb_hresp_q; - end else if (_T_188) begin - slvbuf_error <= 1'h0; - end else begin - slvbuf_error <= _GEN_6; - end - end - end - always @(posedge ahbm_clk or posedge reset) begin - if (reset) begin - last_bus_addr <= 32'h0; - end else if (last_addr_en) begin - last_bus_addr <= io_ahb_out_haddr; - end - end - always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin - if (reset) begin - buf_data <= 64'h0; - end else if (_T_489) begin - buf_data <= ahb_hrdata_q; - end else begin - buf_data <= wrbuf_data; - end - end - always @(posedge ahbm_data_clk or posedge reset) begin - if (reset) begin - ahb_hrdata_q <= 64'h0; - end else begin - ahb_hrdata_q <= io_ahb_in_hrdata; - end - end - always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin - if (reset) begin - buf_addr <= 32'h0; - end else begin - buf_addr <= {master_addr[31:3],_T_485}; - end - end - always @(posedge ahbm_clk or posedge reset) begin - if (reset) begin - buf_cmd_byte_ptrQ <= 3'h0; - end else if (buf_cmd_byte_ptr_en) begin - if (_T_49) begin - if (buf_write_in) begin - if (wrbuf_byteen[0]) begin - buf_cmd_byte_ptrQ <= 3'h0; - end else if (wrbuf_byteen[1]) begin - buf_cmd_byte_ptrQ <= 3'h1; - end else if (wrbuf_byteen[2]) begin - buf_cmd_byte_ptrQ <= 3'h2; - end else if (wrbuf_byteen[3]) begin - buf_cmd_byte_ptrQ <= 3'h3; - end else if (wrbuf_byteen[4]) begin - buf_cmd_byte_ptrQ <= 3'h4; - end else if (wrbuf_byteen[5]) begin - buf_cmd_byte_ptrQ <= 3'h5; - end else if (wrbuf_byteen[6]) begin - buf_cmd_byte_ptrQ <= 3'h6; - end else begin - buf_cmd_byte_ptrQ <= 3'h7; - end - end else begin - buf_cmd_byte_ptrQ <= master_addr[2:0]; - end - end else if (_T_101) begin - if (bypass_en) begin - buf_cmd_byte_ptrQ <= master_addr[2:0]; - end else begin - buf_cmd_byte_ptrQ <= buf_addr[2:0]; - end - end else if (_T_136) begin - if (bypass_en) begin - buf_cmd_byte_ptrQ <= master_addr[2:0]; - end else begin - buf_cmd_byte_ptrQ <= buf_addr[2:0]; - end - end else if (_T_175) begin - buf_cmd_byte_ptrQ <= buf_addr[2:0]; - end else if (_T_186) begin - buf_cmd_byte_ptrQ <= 3'h0; - end else if (_T_188) begin - if (trxn_done) begin - if (_T_201) begin - buf_cmd_byte_ptrQ <= 3'h0; - end else if (_T_204) begin - buf_cmd_byte_ptrQ <= 3'h1; - end else if (_T_207) begin - buf_cmd_byte_ptrQ <= 3'h2; - end else if (_T_210) begin - buf_cmd_byte_ptrQ <= 3'h3; - end else if (_T_213) begin - buf_cmd_byte_ptrQ <= 3'h4; - end else if (_T_216) begin - buf_cmd_byte_ptrQ <= 3'h5; - end else if (_T_219) begin - buf_cmd_byte_ptrQ <= 3'h6; - end else begin - buf_cmd_byte_ptrQ <= 3'h7; - end - end - end else if (_T_281) begin - if (bypass_en) begin - if (wrbuf_byteen[0]) begin - buf_cmd_byte_ptrQ <= 3'h0; - end else if (wrbuf_byteen[1]) begin - buf_cmd_byte_ptrQ <= 3'h1; - end else if (wrbuf_byteen[2]) begin - buf_cmd_byte_ptrQ <= 3'h2; - end else if (wrbuf_byteen[3]) begin - buf_cmd_byte_ptrQ <= 3'h3; - end else if (wrbuf_byteen[4]) begin - buf_cmd_byte_ptrQ <= 3'h4; - end else if (wrbuf_byteen[5]) begin - buf_cmd_byte_ptrQ <= 3'h5; - end else if (wrbuf_byteen[6]) begin - buf_cmd_byte_ptrQ <= 3'h6; - end else begin - buf_cmd_byte_ptrQ <= 3'h7; - end - end else if (trxn_done) begin - if (_T_201) begin - buf_cmd_byte_ptrQ <= 3'h0; - end else if (_T_204) begin - buf_cmd_byte_ptrQ <= 3'h1; - end else if (_T_207) begin - buf_cmd_byte_ptrQ <= 3'h2; - end else if (_T_210) begin - buf_cmd_byte_ptrQ <= 3'h3; - end else if (_T_213) begin - buf_cmd_byte_ptrQ <= 3'h4; - end else if (_T_216) begin - buf_cmd_byte_ptrQ <= 3'h5; - end else if (_T_219) begin - buf_cmd_byte_ptrQ <= 3'h6; - end else begin - buf_cmd_byte_ptrQ <= 3'h7; - end - end - end else begin - buf_cmd_byte_ptrQ <= 3'h0; - end - end - end - always @(posedge buf_clk or posedge reset) begin - if (reset) begin - buf_byteen <= 8'h0; - end else if (buf_wr_en) begin - buf_byteen <= wrbuf_byteen; - end - end - always @(posedge buf_clk or posedge reset) begin - if (reset) begin - buf_aligned <= 1'h0; - end else if (buf_wr_en) begin - buf_aligned <= buf_aligned_in; - end - end - always @(posedge buf_clk or posedge reset) begin - if (reset) begin - buf_size <= 2'h0; - end else if (buf_wr_en) begin - buf_size <= buf_size_in[1:0]; - end - end - always @(posedge buf_clk or posedge reset) begin - if (reset) begin - buf_write <= 1'h0; - end else if (buf_wr_en) begin - if (_T_49) begin - buf_write <= _T_51; - end else if (_T_101) begin - buf_write <= 1'h0; - end else if (_T_136) begin - buf_write <= 1'h0; - end else if (_T_175) begin - buf_write <= 1'h0; - end else if (_T_186) begin - buf_write <= 1'h0; - end else if (_T_188) begin - buf_write <= 1'h0; - end else begin - buf_write <= _GEN_8; - end - end - end -endmodule -module axi4_to_ahb_1( - input clock, - input reset, - input io_scan_mode, - input io_bus_clk_en, - input io_clk_override, - output io_axi_aw_ready, - input io_axi_aw_valid, - input [2:0] io_axi_aw_bits_id, - input [31:0] io_axi_aw_bits_addr, - input [2:0] io_axi_aw_bits_size, - output io_axi_w_ready, - input io_axi_w_valid, - input [63:0] io_axi_w_bits_data, - input [7:0] io_axi_w_bits_strb, - output io_axi_b_valid, - output [1:0] io_axi_b_bits_resp, - output [2:0] io_axi_b_bits_id, - output io_axi_ar_ready, - input io_axi_ar_valid, - input [2:0] io_axi_ar_bits_id, - input [31:0] io_axi_ar_bits_addr, - input [2:0] io_axi_ar_bits_size, - output io_axi_r_valid, - output [2:0] io_axi_r_bits_id, - output [63:0] io_axi_r_bits_data, - output [1:0] io_axi_r_bits_resp, - input [63:0] io_ahb_in_hrdata, - input io_ahb_in_hready, - input io_ahb_in_hresp, - output [31:0] io_ahb_out_haddr, - output [2:0] io_ahb_out_hsize, - output [1:0] io_ahb_out_htrans, - output io_ahb_out_hwrite, - output [63:0] io_ahb_out_hwdata -); -`ifdef RANDOMIZE_REG_INIT - reg [31:0] _RAND_0; - reg [31:0] _RAND_1; - reg [31:0] _RAND_2; - reg [31:0] _RAND_3; - reg [31:0] _RAND_4; - reg [31:0] _RAND_5; - reg [31:0] _RAND_6; - reg [31:0] _RAND_7; - reg [31:0] _RAND_8; - reg [31:0] _RAND_9; - reg [31:0] _RAND_10; - reg [31:0] _RAND_11; - reg [63:0] _RAND_12; - reg [31:0] _RAND_13; - reg [31:0] _RAND_14; - reg [31:0] _RAND_15; - reg [31:0] _RAND_16; - reg [63:0] _RAND_17; - reg [63:0] _RAND_18; - reg [31:0] _RAND_19; - reg [31:0] _RAND_20; - reg [31:0] _RAND_21; - reg [31:0] _RAND_22; - reg [31:0] _RAND_23; - reg [31:0] _RAND_24; - reg [31:0] _RAND_25; -`endif // RANDOMIZE_REG_INIT - wire rvclkhdr_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_io_en; // @[lib.scala 343:22] - wire rvclkhdr_io_scan_mode; // @[lib.scala 343:22] - wire rvclkhdr_1_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_1_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_1_io_en; // @[lib.scala 343:22] - wire rvclkhdr_1_io_scan_mode; // @[lib.scala 343:22] - wire rvclkhdr_2_io_l1clk; // @[lib.scala 368:23] - wire rvclkhdr_2_io_clk; // @[lib.scala 368:23] - wire rvclkhdr_2_io_en; // @[lib.scala 368:23] - wire rvclkhdr_2_io_scan_mode; // @[lib.scala 368:23] - wire rvclkhdr_3_io_l1clk; // @[lib.scala 368:23] - wire rvclkhdr_3_io_clk; // @[lib.scala 368:23] - wire rvclkhdr_3_io_en; // @[lib.scala 368:23] - wire rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23] - wire rvclkhdr_4_io_l1clk; // @[lib.scala 368:23] - wire rvclkhdr_4_io_clk; // @[lib.scala 368:23] - wire rvclkhdr_4_io_en; // @[lib.scala 368:23] - wire rvclkhdr_4_io_scan_mode; // @[lib.scala 368:23] - wire rvclkhdr_5_io_l1clk; // @[lib.scala 368:23] - wire rvclkhdr_5_io_clk; // @[lib.scala 368:23] - wire rvclkhdr_5_io_en; // @[lib.scala 368:23] - wire rvclkhdr_5_io_scan_mode; // @[lib.scala 368:23] - wire rvclkhdr_6_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_6_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_6_io_en; // @[lib.scala 343:22] - wire rvclkhdr_6_io_scan_mode; // @[lib.scala 343:22] - wire rvclkhdr_7_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_7_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_7_io_en; // @[lib.scala 343:22] - wire rvclkhdr_7_io_scan_mode; // @[lib.scala 343:22] - wire rvclkhdr_8_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_8_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_8_io_en; // @[lib.scala 343:22] - wire rvclkhdr_8_io_scan_mode; // @[lib.scala 343:22] - wire rvclkhdr_9_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_9_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_9_io_en; // @[lib.scala 343:22] - wire rvclkhdr_9_io_scan_mode; // @[lib.scala 343:22] - wire ahbm_clk = rvclkhdr_7_io_l1clk; // @[axi4_to_ahb.scala 24:22 axi4_to_ahb.scala 333:12] - reg [2:0] buf_state; // @[axi4_to_ahb.scala 30:45] - wire _T_49 = 3'h0 == buf_state; // @[Conditional.scala 37:30] - wire bus_clk = rvclkhdr_io_l1clk; // @[axi4_to_ahb.scala 50:21 axi4_to_ahb.scala 162:11] - reg wrbuf_vld; // @[axi4_to_ahb.scala 301:51] - reg wrbuf_data_vld; // @[axi4_to_ahb.scala 302:51] - wire wr_cmd_vld = wrbuf_vld & wrbuf_data_vld; // @[axi4_to_ahb.scala 139:27] - wire master_valid = wr_cmd_vld | io_axi_ar_valid; // @[axi4_to_ahb.scala 140:30] - wire _T_101 = 3'h1 == buf_state; // @[Conditional.scala 37:30] - reg ahb_hready_q; // @[axi4_to_ahb.scala 321:52] - reg [1:0] ahb_htrans_q; // @[axi4_to_ahb.scala 322:52] - wire _T_108 = ahb_htrans_q != 2'h0; // @[axi4_to_ahb.scala 183:58] - wire _T_109 = ahb_hready_q & _T_108; // @[axi4_to_ahb.scala 183:36] - wire ahbm_addr_clk = rvclkhdr_8_io_l1clk; // @[axi4_to_ahb.scala 25:27 axi4_to_ahb.scala 334:17] - reg ahb_hwrite_q; // @[axi4_to_ahb.scala 323:57] - wire _T_110 = ~ahb_hwrite_q; // @[axi4_to_ahb.scala 183:72] - wire _T_111 = _T_109 & _T_110; // @[axi4_to_ahb.scala 183:70] - wire _T_136 = 3'h6 == buf_state; // @[Conditional.scala 37:30] - reg ahb_hresp_q; // @[axi4_to_ahb.scala 324:52] - wire _T_156 = ahb_hready_q | ahb_hresp_q; // @[axi4_to_ahb.scala 197:37] - wire _T_175 = 3'h7 == buf_state; // @[Conditional.scala 37:30] - wire _T_186 = 3'h3 == buf_state; // @[Conditional.scala 37:30] - wire _T_188 = 3'h2 == buf_state; // @[Conditional.scala 37:30] - wire _T_189 = ahb_hready_q & ahb_hwrite_q; // @[axi4_to_ahb.scala 229:33] - wire _T_192 = _T_189 & _T_108; // @[axi4_to_ahb.scala 229:48] - wire _T_281 = 3'h4 == buf_state; // @[Conditional.scala 37:30] - wire _GEN_15 = _T_281 & _T_192; // @[Conditional.scala 39:67] - wire _GEN_19 = _T_188 ? _T_192 : _GEN_15; // @[Conditional.scala 39:67] - wire _GEN_40 = _T_186 ? 1'h0 : _GEN_19; // @[Conditional.scala 39:67] - wire _GEN_59 = _T_175 ? 1'h0 : _GEN_40; // @[Conditional.scala 39:67] - wire _GEN_79 = _T_136 ? 1'h0 : _GEN_59; // @[Conditional.scala 39:67] - wire _GEN_95 = _T_101 ? 1'h0 : _GEN_79; // @[Conditional.scala 39:67] - wire trxn_done = _T_49 ? 1'h0 : _GEN_95; // @[Conditional.scala 40:58] - reg cmd_doneQ; // @[axi4_to_ahb.scala 319:52] - wire _T_282 = cmd_doneQ & ahb_hready_q; // @[axi4_to_ahb.scala 239:34] - wire _T_283 = _T_282 | ahb_hresp_q; // @[axi4_to_ahb.scala 239:50] - wire _T_440 = 3'h5 == buf_state; // @[Conditional.scala 37:30] - wire _GEN_3 = _T_281 ? _T_283 : _T_440; // @[Conditional.scala 39:67] - wire _GEN_20 = _T_188 ? trxn_done : _GEN_3; // @[Conditional.scala 39:67] - wire _GEN_35 = _T_186 ? _T_156 : _GEN_20; // @[Conditional.scala 39:67] - wire _GEN_51 = _T_175 ? _T_111 : _GEN_35; // @[Conditional.scala 39:67] - wire _GEN_69 = _T_136 ? _T_156 : _GEN_51; // @[Conditional.scala 39:67] - wire _GEN_83 = _T_101 ? _T_111 : _GEN_69; // @[Conditional.scala 39:67] - wire buf_state_en = _T_49 ? master_valid : _GEN_83; // @[Conditional.scala 40:58] - wire [1:0] _T_14 = wr_cmd_vld ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 142:20] - wire [2:0] master_opc = {{1'd0}, _T_14}; // @[axi4_to_ahb.scala 142:14] - wire _T_51 = master_opc[2:1] == 2'h1; // @[axi4_to_ahb.scala 168:41] - wire _GEN_8 = _T_281 & _T_51; // @[Conditional.scala 39:67] - wire _GEN_29 = _T_188 ? 1'h0 : _GEN_8; // @[Conditional.scala 39:67] - wire _GEN_46 = _T_186 ? 1'h0 : _GEN_29; // @[Conditional.scala 39:67] - wire _GEN_63 = _T_175 ? 1'h0 : _GEN_46; // @[Conditional.scala 39:67] - wire _GEN_81 = _T_136 ? 1'h0 : _GEN_63; // @[Conditional.scala 39:67] - wire _GEN_97 = _T_101 ? 1'h0 : _GEN_81; // @[Conditional.scala 39:67] - wire buf_write_in = _T_49 ? _T_51 : _GEN_97; // @[Conditional.scala 40:58] - wire [2:0] _T_53 = buf_write_in ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 169:26] - wire _T_103 = master_opc == 3'h0; // @[axi4_to_ahb.scala 182:61] - wire _T_104 = master_valid & _T_103; // @[axi4_to_ahb.scala 182:41] - wire [2:0] _T_106 = _T_104 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 182:26] - wire _T_124 = _T_106 == 3'h6; // @[axi4_to_ahb.scala 186:174] - wire _T_125 = _T_111 & _T_124; // @[axi4_to_ahb.scala 186:88] - wire _T_137 = ~ahb_hresp_q; // @[axi4_to_ahb.scala 194:39] - wire _T_138 = ahb_hready_q & _T_137; // @[axi4_to_ahb.scala 194:37] - wire _T_141 = master_valid & _T_51; // @[axi4_to_ahb.scala 194:70] - wire _T_142 = ~_T_141; // @[axi4_to_ahb.scala 194:55] - wire _T_143 = _T_138 & _T_142; // @[axi4_to_ahb.scala 194:53] - wire _T_285 = buf_state_en & _T_137; // @[axi4_to_ahb.scala 240:36] - wire _GEN_4 = _T_281 & _T_285; // @[Conditional.scala 39:67] - wire _GEN_26 = _T_188 ? 1'h0 : _GEN_4; // @[Conditional.scala 39:67] - wire _GEN_45 = _T_186 ? 1'h0 : _GEN_26; // @[Conditional.scala 39:67] - wire _GEN_62 = _T_175 ? 1'h0 : _GEN_45; // @[Conditional.scala 39:67] - wire _GEN_66 = _T_136 ? _T_143 : _GEN_62; // @[Conditional.scala 39:67] - wire _GEN_86 = _T_101 ? _T_125 : _GEN_66; // @[Conditional.scala 39:67] - wire master_ready = _T_49 | _GEN_86; // @[Conditional.scala 40:58] - wire _T_149 = master_valid & master_ready; // @[axi4_to_ahb.scala 196:82] - wire _T_152 = _T_149 & _T_103; // @[axi4_to_ahb.scala 196:97] - wire [2:0] _T_154 = _T_152 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 196:67] - wire [2:0] _T_155 = ahb_hresp_q ? 3'h7 : _T_154; // @[axi4_to_ahb.scala 196:26] - wire [2:0] _T_293 = _T_51 ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 241:99] - wire [2:0] _T_294 = master_valid ? _T_293 : 3'h0; // @[axi4_to_ahb.scala 241:65] - wire [2:0] _T_295 = ahb_hresp_q ? 3'h5 : _T_294; // @[axi4_to_ahb.scala 241:26] - wire [2:0] _GEN_5 = _T_281 ? _T_295 : 3'h0; // @[Conditional.scala 39:67] - wire [2:0] _GEN_18 = _T_188 ? 3'h4 : _GEN_5; // @[Conditional.scala 39:67] - wire [2:0] _GEN_34 = _T_186 ? 3'h5 : _GEN_18; // @[Conditional.scala 39:67] - wire [2:0] _GEN_50 = _T_175 ? 3'h3 : _GEN_34; // @[Conditional.scala 39:67] - wire [2:0] _GEN_68 = _T_136 ? _T_155 : _GEN_50; // @[Conditional.scala 39:67] - wire [2:0] _GEN_82 = _T_101 ? _T_106 : _GEN_68; // @[Conditional.scala 39:67] - wire [2:0] buf_nxtstate = _T_49 ? _T_53 : _GEN_82; // @[Conditional.scala 40:58] - reg [2:0] wrbuf_tag; // @[Reg.scala 27:20] - reg [31:0] wrbuf_addr; // @[lib.scala 374:16] - wire [31:0] master_addr = wr_cmd_vld ? wrbuf_addr : io_axi_ar_bits_addr; // @[axi4_to_ahb.scala 143:21] - reg [2:0] wrbuf_size; // @[Reg.scala 27:20] - wire [2:0] master_size = wr_cmd_vld ? wrbuf_size : io_axi_ar_bits_size; // @[axi4_to_ahb.scala 144:21] - reg [7:0] wrbuf_byteen; // @[Reg.scala 27:20] - reg [63:0] wrbuf_data; // @[lib.scala 374:16] - wire _T_358 = buf_nxtstate != 3'h5; // @[axi4_to_ahb.scala 251:55] - wire _T_359 = buf_state_en & _T_358; // @[axi4_to_ahb.scala 251:39] - wire _GEN_14 = _T_281 ? _T_359 : _T_440; // @[Conditional.scala 39:67] - wire _GEN_33 = _T_188 ? 1'h0 : _GEN_14; // @[Conditional.scala 39:67] - wire _GEN_49 = _T_186 ? 1'h0 : _GEN_33; // @[Conditional.scala 39:67] - wire _GEN_52 = _T_175 ? buf_state_en : _GEN_49; // @[Conditional.scala 39:67] - wire _GEN_73 = _T_136 ? _T_285 : _GEN_52; // @[Conditional.scala 39:67] - wire _GEN_94 = _T_101 ? 1'h0 : _GEN_73; // @[Conditional.scala 39:67] - wire slave_valid_pre = _T_49 ? 1'h0 : _GEN_94; // @[Conditional.scala 40:58] - wire buf_clk = rvclkhdr_6_io_l1clk; // @[axi4_to_ahb.scala 118:21 axi4_to_ahb.scala 332:12] - reg slvbuf_write; // @[Reg.scala 27:20] - wire [1:0] _T_596 = slvbuf_write ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 285:23] - reg slvbuf_error; // @[Reg.scala 27:20] - wire [1:0] _T_598 = slvbuf_error ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_599 = _T_598 & 2'h2; // @[axi4_to_ahb.scala 285:88] - wire [3:0] slave_opc = {_T_596,_T_599}; // @[Cat.scala 29:58] - wire [1:0] _T_30 = slave_opc[1] ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 150:55] - reg [2:0] slvbuf_tag; // @[Reg.scala 27:20] - wire _T_35 = slave_opc[3:2] == 2'h0; // @[axi4_to_ahb.scala 153:66] - reg [31:0] last_bus_addr; // @[Reg.scala 27:20] - wire [63:0] _T_603 = {last_bus_addr,last_bus_addr}; // @[Cat.scala 29:58] - wire _T_604 = buf_state == 3'h5; // @[axi4_to_ahb.scala 286:91] - reg [63:0] buf_data; // @[lib.scala 374:16] - wire ahbm_data_clk = rvclkhdr_9_io_l1clk; // @[axi4_to_ahb.scala 26:27 axi4_to_ahb.scala 335:17] - reg [63:0] ahb_hrdata_q; // @[axi4_to_ahb.scala 325:57] - wire [63:0] _T_607 = _T_604 ? buf_data : ahb_hrdata_q; // @[axi4_to_ahb.scala 286:79] - wire _T_44 = io_axi_aw_valid & io_axi_aw_ready; // @[axi4_to_ahb.scala 160:57] - wire _T_45 = io_axi_w_valid & io_axi_w_ready; // @[axi4_to_ahb.scala 160:94] - wire _T_46 = _T_44 | _T_45; // @[axi4_to_ahb.scala 160:76] - wire _T_55 = buf_nxtstate == 3'h2; // @[axi4_to_ahb.scala 172:54] - wire _T_56 = buf_state_en & _T_55; // @[axi4_to_ahb.scala 172:38] - wire [2:0] _T_87 = wrbuf_byteen[6] ? 3'h6 : 3'h7; // @[Mux.scala 98:16] - wire [2:0] _T_88 = wrbuf_byteen[5] ? 3'h5 : _T_87; // @[Mux.scala 98:16] - wire [2:0] _T_89 = wrbuf_byteen[4] ? 3'h4 : _T_88; // @[Mux.scala 98:16] - wire [2:0] _T_90 = wrbuf_byteen[3] ? 3'h3 : _T_89; // @[Mux.scala 98:16] - wire [2:0] _T_91 = wrbuf_byteen[2] ? 3'h2 : _T_90; // @[Mux.scala 98:16] - wire [2:0] _T_92 = wrbuf_byteen[1] ? 3'h1 : _T_91; // @[Mux.scala 98:16] - wire [2:0] _T_93 = wrbuf_byteen[0] ? 3'h0 : _T_92; // @[Mux.scala 98:16] - wire [2:0] _T_95 = buf_write_in ? _T_93 : master_addr[2:0]; // @[axi4_to_ahb.scala 175:30] - wire _T_96 = buf_nxtstate == 3'h1; // @[axi4_to_ahb.scala 177:51] - wire _T_126 = master_ready & master_valid; // @[axi4_to_ahb.scala 188:33] - wire _T_162 = buf_nxtstate == 3'h6; // @[axi4_to_ahb.scala 203:64] - wire _T_163 = _T_126 & _T_162; // @[axi4_to_ahb.scala 203:48] - wire _T_164 = _T_163 & buf_state_en; // @[axi4_to_ahb.scala 203:79] - wire _T_349 = buf_state_en & buf_write_in; // @[axi4_to_ahb.scala 249:33] - wire _T_351 = _T_349 & _T_55; // @[axi4_to_ahb.scala 249:48] - wire _GEN_12 = _T_281 & _T_351; // @[Conditional.scala 39:67] - wire _GEN_32 = _T_188 ? 1'h0 : _GEN_12; // @[Conditional.scala 39:67] - wire _GEN_48 = _T_186 ? 1'h0 : _GEN_32; // @[Conditional.scala 39:67] - wire _GEN_65 = _T_175 ? 1'h0 : _GEN_48; // @[Conditional.scala 39:67] - wire _GEN_75 = _T_136 ? _T_164 : _GEN_65; // @[Conditional.scala 39:67] - wire _GEN_88 = _T_101 ? _T_126 : _GEN_75; // @[Conditional.scala 39:67] - wire bypass_en = _T_49 ? buf_state_en : _GEN_88; // @[Conditional.scala 40:58] - wire [1:0] _T_99 = bypass_en ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_100 = _T_99 & 2'h2; // @[axi4_to_ahb.scala 178:49] - wire _T_112 = ~master_valid; // @[axi4_to_ahb.scala 184:34] - wire _T_113 = buf_state_en & _T_112; // @[axi4_to_ahb.scala 184:32] - reg [31:0] buf_addr; // @[lib.scala 374:16] - wire [2:0] _T_130 = bypass_en ? master_addr[2:0] : buf_addr[2:0]; // @[axi4_to_ahb.scala 189:30] - wire _T_131 = ~buf_state_en; // @[axi4_to_ahb.scala 190:48] - wire _T_132 = _T_131 | bypass_en; // @[axi4_to_ahb.scala 190:62] - wire [1:0] _T_134 = _T_132 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_135 = 2'h2 & _T_134; // @[axi4_to_ahb.scala 190:36] - wire _T_169 = buf_nxtstate != 3'h6; // @[axi4_to_ahb.scala 205:63] - wire _T_170 = _T_169 & buf_state_en; // @[axi4_to_ahb.scala 205:78] - wire _T_171 = ~_T_170; // @[axi4_to_ahb.scala 205:47] - wire [1:0] _T_173 = _T_171 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_174 = 2'h2 & _T_173; // @[axi4_to_ahb.scala 205:36] - wire [1:0] _T_184 = _T_131 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_185 = 2'h2 & _T_184; // @[axi4_to_ahb.scala 215:41] - reg [2:0] buf_cmd_byte_ptrQ; // @[Reg.scala 27:20] - reg [7:0] buf_byteen; // @[Reg.scala 27:20] - wire [2:0] _T_197 = buf_cmd_byte_ptrQ + 3'h1; // @[axi4_to_ahb.scala 135:52] - wire _T_200 = 3'h0 >= _T_197; // @[axi4_to_ahb.scala 136:62] - wire _T_201 = buf_byteen[0] & _T_200; // @[axi4_to_ahb.scala 136:48] - wire _T_203 = 3'h1 >= _T_197; // @[axi4_to_ahb.scala 136:62] - wire _T_204 = buf_byteen[1] & _T_203; // @[axi4_to_ahb.scala 136:48] - wire _T_206 = 3'h2 >= _T_197; // @[axi4_to_ahb.scala 136:62] - wire _T_207 = buf_byteen[2] & _T_206; // @[axi4_to_ahb.scala 136:48] - wire _T_209 = 3'h3 >= _T_197; // @[axi4_to_ahb.scala 136:62] - wire _T_210 = buf_byteen[3] & _T_209; // @[axi4_to_ahb.scala 136:48] - wire _T_212 = 3'h4 >= _T_197; // @[axi4_to_ahb.scala 136:62] - wire _T_213 = buf_byteen[4] & _T_212; // @[axi4_to_ahb.scala 136:48] - wire _T_215 = 3'h5 >= _T_197; // @[axi4_to_ahb.scala 136:62] - wire _T_216 = buf_byteen[5] & _T_215; // @[axi4_to_ahb.scala 136:48] - wire _T_218 = 3'h6 >= _T_197; // @[axi4_to_ahb.scala 136:62] - wire _T_219 = buf_byteen[6] & _T_218; // @[axi4_to_ahb.scala 136:48] - wire [2:0] _T_224 = _T_219 ? 3'h6 : 3'h7; // @[Mux.scala 98:16] - wire [2:0] _T_225 = _T_216 ? 3'h5 : _T_224; // @[Mux.scala 98:16] - wire [2:0] _T_226 = _T_213 ? 3'h4 : _T_225; // @[Mux.scala 98:16] - wire [2:0] _T_227 = _T_210 ? 3'h3 : _T_226; // @[Mux.scala 98:16] - wire [2:0] _T_228 = _T_207 ? 3'h2 : _T_227; // @[Mux.scala 98:16] - wire [2:0] _T_229 = _T_204 ? 3'h1 : _T_228; // @[Mux.scala 98:16] - wire [2:0] _T_230 = _T_201 ? 3'h0 : _T_229; // @[Mux.scala 98:16] - wire [2:0] _T_231 = trxn_done ? _T_230 : buf_cmd_byte_ptrQ; // @[axi4_to_ahb.scala 233:30] - wire _T_232 = buf_cmd_byte_ptrQ == 3'h7; // @[axi4_to_ahb.scala 234:65] - reg buf_aligned; // @[Reg.scala 27:20] - wire _T_233 = buf_aligned | _T_232; // @[axi4_to_ahb.scala 234:44] - wire [7:0] _T_271 = buf_byteen >> _T_230; // @[axi4_to_ahb.scala 234:92] - wire _T_273 = ~_T_271[0]; // @[axi4_to_ahb.scala 234:163] - wire _T_274 = _T_233 | _T_273; // @[axi4_to_ahb.scala 234:79] - wire _T_275 = trxn_done & _T_274; // @[axi4_to_ahb.scala 234:29] - wire _T_346 = _T_232 | _T_273; // @[axi4_to_ahb.scala 248:38] - wire _T_347 = _T_109 & _T_346; // @[axi4_to_ahb.scala 247:80] - wire _T_348 = ahb_hresp_q | _T_347; // @[axi4_to_ahb.scala 247:34] - wire _GEN_11 = _T_281 & _T_348; // @[Conditional.scala 39:67] - wire _GEN_24 = _T_188 ? _T_275 : _GEN_11; // @[Conditional.scala 39:67] - wire _GEN_43 = _T_186 ? 1'h0 : _GEN_24; // @[Conditional.scala 39:67] - wire _GEN_61 = _T_175 ? 1'h0 : _GEN_43; // @[Conditional.scala 39:67] - wire _GEN_74 = _T_136 ? _T_113 : _GEN_61; // @[Conditional.scala 39:67] - wire _GEN_84 = _T_101 ? _T_113 : _GEN_74; // @[Conditional.scala 39:67] - wire cmd_done = _T_49 ? 1'h0 : _GEN_84; // @[Conditional.scala 40:58] - wire _T_276 = cmd_done | cmd_doneQ; // @[axi4_to_ahb.scala 235:47] - wire _T_277 = ~_T_276; // @[axi4_to_ahb.scala 235:36] - wire [1:0] _T_279 = _T_277 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_280 = _T_279 & 2'h2; // @[axi4_to_ahb.scala 235:61] - wire _T_300 = _T_55 | _T_96; // @[axi4_to_ahb.scala 245:62] - wire _T_301 = buf_state_en & _T_300; // @[axi4_to_ahb.scala 245:33] - wire _T_354 = _T_277 | bypass_en; // @[axi4_to_ahb.scala 250:61] - wire [1:0] _T_356 = _T_354 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_357 = _T_356 & 2'h2; // @[axi4_to_ahb.scala 250:75] - wire _T_364 = trxn_done | bypass_en; // @[axi4_to_ahb.scala 253:40] - wire [2:0] _T_439 = bypass_en ? _T_93 : _T_231; // @[axi4_to_ahb.scala 254:30] - wire _GEN_6 = _T_281 & ahb_hresp_q; // @[Conditional.scala 39:67] - wire _GEN_7 = _T_281 ? buf_state_en : _T_440; // @[Conditional.scala 39:67] - wire _GEN_9 = _T_281 & _T_301; // @[Conditional.scala 39:67] - wire _GEN_30 = _T_188 ? 1'h0 : _GEN_9; // @[Conditional.scala 39:67] - wire _GEN_47 = _T_186 ? 1'h0 : _GEN_30; // @[Conditional.scala 39:67] - wire _GEN_64 = _T_175 ? 1'h0 : _GEN_47; // @[Conditional.scala 39:67] - wire _GEN_67 = _T_136 ? _T_152 : _GEN_64; // @[Conditional.scala 39:67] - wire _GEN_87 = _T_101 ? master_ready : _GEN_67; // @[Conditional.scala 39:67] - wire buf_wr_en = _T_49 ? buf_state_en : _GEN_87; // @[Conditional.scala 40:58] - wire _GEN_10 = _T_281 & buf_wr_en; // @[Conditional.scala 39:67] - wire [1:0] _GEN_13 = _T_281 ? _T_357 : 2'h0; // @[Conditional.scala 39:67] - wire _GEN_16 = _T_281 & _T_364; // @[Conditional.scala 39:67] - wire [2:0] _GEN_17 = _T_281 ? _T_439 : 3'h0; // @[Conditional.scala 39:67] - wire _GEN_21 = _T_188 ? buf_state_en : _GEN_16; // @[Conditional.scala 39:67] - wire _GEN_22 = _T_188 & buf_state_en; // @[Conditional.scala 39:67] - wire [2:0] _GEN_23 = _T_188 ? _T_231 : _GEN_17; // @[Conditional.scala 39:67] - wire [1:0] _GEN_25 = _T_188 ? _T_280 : _GEN_13; // @[Conditional.scala 39:67] - wire _GEN_28 = _T_188 ? 1'h0 : _GEN_7; // @[Conditional.scala 39:67] - wire _GEN_31 = _T_188 ? 1'h0 : _GEN_10; // @[Conditional.scala 39:67] - wire _GEN_36 = _T_186 ? buf_state_en : _GEN_31; // @[Conditional.scala 39:67] - wire _GEN_38 = _T_186 ? buf_state_en : _GEN_28; // @[Conditional.scala 39:67] - wire _GEN_39 = _T_186 ? buf_state_en : _GEN_22; // @[Conditional.scala 39:67] - wire _GEN_41 = _T_186 ? 1'h0 : _GEN_21; // @[Conditional.scala 39:67] - wire [2:0] _GEN_42 = _T_186 ? 3'h0 : _GEN_23; // @[Conditional.scala 39:67] - wire [1:0] _GEN_44 = _T_186 ? 2'h0 : _GEN_25; // @[Conditional.scala 39:67] - wire _GEN_53 = _T_175 ? buf_state_en : _GEN_39; // @[Conditional.scala 39:67] - wire [2:0] _GEN_54 = _T_175 ? buf_addr[2:0] : _GEN_42; // @[Conditional.scala 39:67] - wire [1:0] _GEN_55 = _T_175 ? _T_185 : _GEN_44; // @[Conditional.scala 39:67] - wire _GEN_56 = _T_175 ? 1'h0 : _GEN_36; // @[Conditional.scala 39:67] - wire _GEN_58 = _T_175 ? 1'h0 : _GEN_38; // @[Conditional.scala 39:67] - wire _GEN_60 = _T_175 ? 1'h0 : _GEN_41; // @[Conditional.scala 39:67] - wire _GEN_70 = _T_136 ? buf_state_en : _GEN_56; // @[Conditional.scala 39:67] - wire _GEN_72 = _T_136 ? buf_state_en : _GEN_58; // @[Conditional.scala 39:67] - wire [2:0] _GEN_76 = _T_136 ? _T_130 : _GEN_54; // @[Conditional.scala 39:67] - wire [1:0] _GEN_77 = _T_136 ? _T_174 : _GEN_55; // @[Conditional.scala 39:67] - wire _GEN_78 = _T_136 ? buf_wr_en : _GEN_53; // @[Conditional.scala 39:67] - wire _GEN_80 = _T_136 ? 1'h0 : _GEN_60; // @[Conditional.scala 39:67] - wire _GEN_85 = _T_101 ? buf_state_en : _GEN_78; // @[Conditional.scala 39:67] - wire [2:0] _GEN_89 = _T_101 ? _T_130 : _GEN_76; // @[Conditional.scala 39:67] - wire [1:0] _GEN_90 = _T_101 ? _T_135 : _GEN_77; // @[Conditional.scala 39:67] - wire _GEN_91 = _T_101 ? 1'h0 : _GEN_70; // @[Conditional.scala 39:67] - wire _GEN_93 = _T_101 ? 1'h0 : _GEN_72; // @[Conditional.scala 39:67] - wire _GEN_96 = _T_101 ? 1'h0 : _GEN_80; // @[Conditional.scala 39:67] - wire buf_data_wr_en = _T_49 ? _T_56 : _GEN_91; // @[Conditional.scala 40:58] - wire buf_cmd_byte_ptr_en = _T_49 ? buf_state_en : _GEN_96; // @[Conditional.scala 40:58] - wire [2:0] buf_cmd_byte_ptr = _T_49 ? _T_95 : _GEN_89; // @[Conditional.scala 40:58] - wire slvbuf_wr_en = _T_49 ? 1'h0 : _GEN_85; // @[Conditional.scala 40:58] - wire slvbuf_error_en = _T_49 ? 1'h0 : _GEN_93; // @[Conditional.scala 40:58] - wire _T_535 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 271:24] - wire _T_536 = _T_103 | _T_535; // @[axi4_to_ahb.scala 270:48] - wire _T_538 = master_size[1:0] == 2'h1; // @[axi4_to_ahb.scala 271:54] - wire _T_539 = _T_536 | _T_538; // @[axi4_to_ahb.scala 271:33] - wire _T_541 = master_size[1:0] == 2'h2; // @[axi4_to_ahb.scala 271:93] - wire _T_542 = _T_539 | _T_541; // @[axi4_to_ahb.scala 271:72] - wire _T_544 = master_size[1:0] == 2'h3; // @[axi4_to_ahb.scala 272:25] - wire _T_546 = wrbuf_byteen == 8'h3; // @[axi4_to_ahb.scala 272:62] - wire _T_548 = wrbuf_byteen == 8'hc; // @[axi4_to_ahb.scala 272:97] - wire _T_549 = _T_546 | _T_548; // @[axi4_to_ahb.scala 272:74] - wire _T_551 = wrbuf_byteen == 8'h30; // @[axi4_to_ahb.scala 272:132] - wire _T_552 = _T_549 | _T_551; // @[axi4_to_ahb.scala 272:109] - wire _T_554 = wrbuf_byteen == 8'hc0; // @[axi4_to_ahb.scala 272:168] - wire _T_555 = _T_552 | _T_554; // @[axi4_to_ahb.scala 272:145] - wire _T_557 = wrbuf_byteen == 8'hf; // @[axi4_to_ahb.scala 273:28] - wire _T_558 = _T_555 | _T_557; // @[axi4_to_ahb.scala 272:181] - wire _T_560 = wrbuf_byteen == 8'hf0; // @[axi4_to_ahb.scala 273:63] - wire _T_561 = _T_558 | _T_560; // @[axi4_to_ahb.scala 273:40] - wire _T_563 = wrbuf_byteen == 8'hff; // @[axi4_to_ahb.scala 273:99] - wire _T_564 = _T_561 | _T_563; // @[axi4_to_ahb.scala 273:76] - wire _T_565 = _T_544 & _T_564; // @[axi4_to_ahb.scala 272:38] - wire buf_aligned_in = _T_542 | _T_565; // @[axi4_to_ahb.scala 271:106] - wire _T_444 = buf_aligned_in & _T_51; // @[axi4_to_ahb.scala 265:60] - wire [2:0] _T_461 = _T_548 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_462 = 3'h2 & _T_461; // @[axi4_to_ahb.scala 128:15] - wire _T_468 = _T_560 | _T_546; // @[axi4_to_ahb.scala 129:56] - wire [2:0] _T_470 = _T_468 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_471 = 3'h4 & _T_470; // @[axi4_to_ahb.scala 129:15] - wire [2:0] _T_472 = _T_462 | _T_471; // @[axi4_to_ahb.scala 128:63] - wire [2:0] _T_476 = _T_554 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_477 = 3'h6 & _T_476; // @[axi4_to_ahb.scala 130:15] - wire [2:0] _T_478 = _T_472 | _T_477; // @[axi4_to_ahb.scala 129:96] - wire [2:0] _T_485 = _T_444 ? _T_478 : master_addr[2:0]; // @[axi4_to_ahb.scala 265:43] - wire _T_489 = buf_state == 3'h3; // @[axi4_to_ahb.scala 268:33] - wire _T_495 = buf_aligned_in & _T_544; // @[axi4_to_ahb.scala 269:38] - wire _T_498 = _T_495 & _T_51; // @[axi4_to_ahb.scala 269:71] - wire [1:0] _T_504 = _T_563 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire _T_510 = _T_560 | _T_557; // @[axi4_to_ahb.scala 122:55] - wire [1:0] _T_512 = _T_510 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_513 = 2'h2 & _T_512; // @[axi4_to_ahb.scala 122:16] - wire [1:0] _T_514 = _T_504 | _T_513; // @[axi4_to_ahb.scala 121:64] - wire _T_519 = _T_554 | _T_551; // @[axi4_to_ahb.scala 123:60] - wire _T_522 = _T_519 | _T_548; // @[axi4_to_ahb.scala 123:89] - wire _T_525 = _T_522 | _T_546; // @[axi4_to_ahb.scala 123:123] - wire [1:0] _T_527 = _T_525 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_528 = 2'h1 & _T_527; // @[axi4_to_ahb.scala 123:21] - wire [1:0] _T_529 = _T_514 | _T_528; // @[axi4_to_ahb.scala 122:93] - wire [1:0] _T_531 = _T_498 ? _T_529 : master_size[1:0]; // @[axi4_to_ahb.scala 269:21] - wire [31:0] _T_570 = {master_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] - wire [31:0] _T_573 = {buf_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] - wire [1:0] _T_577 = buf_aligned_in ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [2:0] buf_size_in = {{1'd0}, _T_531}; // @[axi4_to_ahb.scala 269:15] - wire [1:0] _T_579 = _T_577 & buf_size_in[1:0]; // @[axi4_to_ahb.scala 276:81] - wire [2:0] _T_580 = {1'h0,_T_579}; // @[Cat.scala 29:58] - wire [1:0] _T_582 = buf_aligned ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - reg [1:0] buf_size; // @[Reg.scala 27:20] - wire [1:0] _T_584 = _T_582 & buf_size; // @[axi4_to_ahb.scala 276:138] - wire [2:0] _T_585 = {1'h0,_T_584}; // @[Cat.scala 29:58] - reg buf_write; // @[Reg.scala 27:20] - wire _T_611 = io_ahb_out_htrans != 2'h0; // @[axi4_to_ahb.scala 289:44] - wire _T_612 = _T_611 & io_ahb_in_hready; // @[axi4_to_ahb.scala 289:56] - wire last_addr_en = _T_612 & io_ahb_out_hwrite; // @[axi4_to_ahb.scala 289:75] - wire wrbuf_en = _T_44 & master_ready; // @[axi4_to_ahb.scala 291:49] - wire wrbuf_data_en = _T_45 & master_ready; // @[axi4_to_ahb.scala 292:52] - wire wrbuf_cmd_sent = _T_149 & _T_51; // @[axi4_to_ahb.scala 293:49] - wire _T_622 = ~wrbuf_en; // @[axi4_to_ahb.scala 294:33] - wire wrbuf_rst = wrbuf_cmd_sent & _T_622; // @[axi4_to_ahb.scala 294:31] - wire _T_624 = ~wrbuf_cmd_sent; // @[axi4_to_ahb.scala 296:36] - wire _T_625 = wrbuf_vld & _T_624; // @[axi4_to_ahb.scala 296:34] - wire _T_626 = ~_T_625; // @[axi4_to_ahb.scala 296:22] - wire _T_629 = wrbuf_data_vld & _T_624; // @[axi4_to_ahb.scala 297:38] - wire _T_630 = ~_T_629; // @[axi4_to_ahb.scala 297:21] - wire _T_633 = ~wr_cmd_vld; // @[axi4_to_ahb.scala 298:22] - wire _T_636 = wrbuf_en | wrbuf_vld; // @[axi4_to_ahb.scala 301:55] - wire _T_637 = ~wrbuf_rst; // @[axi4_to_ahb.scala 301:91] - wire _T_641 = wrbuf_data_en | wrbuf_data_vld; // @[axi4_to_ahb.scala 302:55] - reg [2:0] buf_tag; // @[Reg.scala 27:20] - wire _T_691 = ~slave_valid_pre; // @[axi4_to_ahb.scala 319:92] - wire _T_704 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 327:43] - wire _T_705 = _T_704 | io_clk_override; // @[axi4_to_ahb.scala 327:58] - wire _T_708 = io_ahb_in_hready & io_ahb_out_htrans[1]; // @[axi4_to_ahb.scala 328:57] - wire _T_709 = _T_708 | io_clk_override; // @[axi4_to_ahb.scala 328:81] - wire _T_711 = buf_state != 3'h0; // @[axi4_to_ahb.scala 329:50] - wire _T_712 = _T_711 | io_clk_override; // @[axi4_to_ahb.scala 329:60] - rvclkhdr rvclkhdr ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_io_l1clk), - .io_clk(rvclkhdr_io_clk), - .io_en(rvclkhdr_io_en), - .io_scan_mode(rvclkhdr_io_scan_mode) - ); - rvclkhdr rvclkhdr_1 ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_1_io_l1clk), - .io_clk(rvclkhdr_1_io_clk), - .io_en(rvclkhdr_1_io_en), - .io_scan_mode(rvclkhdr_1_io_scan_mode) - ); - rvclkhdr rvclkhdr_2 ( // @[lib.scala 368:23] - .io_l1clk(rvclkhdr_2_io_l1clk), - .io_clk(rvclkhdr_2_io_clk), - .io_en(rvclkhdr_2_io_en), - .io_scan_mode(rvclkhdr_2_io_scan_mode) - ); - rvclkhdr rvclkhdr_3 ( // @[lib.scala 368:23] - .io_l1clk(rvclkhdr_3_io_l1clk), - .io_clk(rvclkhdr_3_io_clk), - .io_en(rvclkhdr_3_io_en), - .io_scan_mode(rvclkhdr_3_io_scan_mode) - ); - rvclkhdr rvclkhdr_4 ( // @[lib.scala 368:23] - .io_l1clk(rvclkhdr_4_io_l1clk), - .io_clk(rvclkhdr_4_io_clk), - .io_en(rvclkhdr_4_io_en), - .io_scan_mode(rvclkhdr_4_io_scan_mode) - ); - rvclkhdr rvclkhdr_5 ( // @[lib.scala 368:23] - .io_l1clk(rvclkhdr_5_io_l1clk), - .io_clk(rvclkhdr_5_io_clk), - .io_en(rvclkhdr_5_io_en), - .io_scan_mode(rvclkhdr_5_io_scan_mode) - ); - rvclkhdr rvclkhdr_6 ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_6_io_l1clk), - .io_clk(rvclkhdr_6_io_clk), - .io_en(rvclkhdr_6_io_en), - .io_scan_mode(rvclkhdr_6_io_scan_mode) - ); - rvclkhdr rvclkhdr_7 ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_7_io_l1clk), - .io_clk(rvclkhdr_7_io_clk), - .io_en(rvclkhdr_7_io_en), - .io_scan_mode(rvclkhdr_7_io_scan_mode) - ); - rvclkhdr rvclkhdr_8 ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_8_io_l1clk), - .io_clk(rvclkhdr_8_io_clk), - .io_en(rvclkhdr_8_io_en), - .io_scan_mode(rvclkhdr_8_io_scan_mode) - ); - rvclkhdr rvclkhdr_9 ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_9_io_l1clk), - .io_clk(rvclkhdr_9_io_clk), - .io_en(rvclkhdr_9_io_en), - .io_scan_mode(rvclkhdr_9_io_scan_mode) - ); - assign io_axi_aw_ready = _T_626 & master_ready; // @[axi4_to_ahb.scala 296:19] - assign io_axi_w_ready = _T_630 & master_ready; // @[axi4_to_ahb.scala 297:18] - assign io_axi_b_valid = slave_valid_pre & slave_opc[3]; // @[axi4_to_ahb.scala 149:18] - assign io_axi_b_bits_resp = slave_opc[0] ? 2'h2 : _T_30; // @[axi4_to_ahb.scala 150:22] - assign io_axi_b_bits_id = slvbuf_tag; // @[axi4_to_ahb.scala 151:20] - assign io_axi_ar_ready = _T_633 & master_ready; // @[axi4_to_ahb.scala 298:19] - assign io_axi_r_valid = slave_valid_pre & _T_35; // @[axi4_to_ahb.scala 153:18] - assign io_axi_r_bits_id = slvbuf_tag; // @[axi4_to_ahb.scala 155:20] - assign io_axi_r_bits_data = slvbuf_error ? _T_603 : _T_607; // @[axi4_to_ahb.scala 156:22] - assign io_axi_r_bits_resp = slave_opc[0] ? 2'h2 : _T_30; // @[axi4_to_ahb.scala 154:22] - assign io_ahb_out_haddr = bypass_en ? _T_570 : _T_573; // @[axi4_to_ahb.scala 275:20] - assign io_ahb_out_hsize = bypass_en ? _T_580 : _T_585; // @[axi4_to_ahb.scala 276:20] - assign io_ahb_out_htrans = _T_49 ? _T_100 : _GEN_90; // @[axi4_to_ahb.scala 22:21 axi4_to_ahb.scala 178:25 axi4_to_ahb.scala 190:25 axi4_to_ahb.scala 205:25 axi4_to_ahb.scala 215:25 axi4_to_ahb.scala 235:25 axi4_to_ahb.scala 250:25] - assign io_ahb_out_hwrite = bypass_en ? _T_51 : buf_write; // @[axi4_to_ahb.scala 281:21] - assign io_ahb_out_hwdata = buf_data; // @[axi4_to_ahb.scala 282:21] - assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_io_en = io_bus_clk_en; // @[lib.scala 345:16] - assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign rvclkhdr_1_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_1_io_en = io_bus_clk_en & _T_46; // @[lib.scala 345:16] - assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign rvclkhdr_2_io_clk = rvclkhdr_io_l1clk; // @[lib.scala 370:18] - assign rvclkhdr_2_io_en = _T_44 & master_ready; // @[lib.scala 371:17] - assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] - assign rvclkhdr_3_io_clk = rvclkhdr_io_l1clk; // @[lib.scala 370:18] - assign rvclkhdr_3_io_en = _T_45 & master_ready; // @[lib.scala 371:17] - assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] - assign rvclkhdr_4_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_4_io_en = buf_wr_en & io_bus_clk_en; // @[lib.scala 371:17] - assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] - assign rvclkhdr_5_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_5_io_en = buf_data_wr_en & io_bus_clk_en; // @[lib.scala 371:17] - assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] - assign rvclkhdr_6_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_6_io_en = io_bus_clk_en & _T_705; // @[lib.scala 345:16] - assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign rvclkhdr_7_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_7_io_en = io_bus_clk_en; // @[lib.scala 345:16] - assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign rvclkhdr_8_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_8_io_en = io_bus_clk_en & _T_709; // @[lib.scala 345:16] - assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign rvclkhdr_9_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_9_io_en = io_bus_clk_en & _T_712; // @[lib.scala 345:16] - assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] -`ifdef RANDOMIZE_GARBAGE_ASSIGN -`define RANDOMIZE -`endif -`ifdef RANDOMIZE_INVALID_ASSIGN -`define RANDOMIZE -`endif -`ifdef RANDOMIZE_REG_INIT -`define RANDOMIZE -`endif -`ifdef RANDOMIZE_MEM_INIT -`define RANDOMIZE -`endif -`ifndef RANDOM -`define RANDOM $random -`endif -`ifdef RANDOMIZE_MEM_INIT - integer initvar; -`endif -`ifndef SYNTHESIS -`ifdef FIRRTL_BEFORE_INITIAL -`FIRRTL_BEFORE_INITIAL -`endif -initial begin - `ifdef RANDOMIZE - `ifdef INIT_RANDOM - `INIT_RANDOM - `endif - `ifndef VERILATOR - `ifdef RANDOMIZE_DELAY - #`RANDOMIZE_DELAY begin end - `else - #0.002 begin end - `endif - `endif -`ifdef RANDOMIZE_REG_INIT - _RAND_0 = {1{`RANDOM}}; - buf_state = _RAND_0[2:0]; - _RAND_1 = {1{`RANDOM}}; - wrbuf_vld = _RAND_1[0:0]; - _RAND_2 = {1{`RANDOM}}; - wrbuf_data_vld = _RAND_2[0:0]; - _RAND_3 = {1{`RANDOM}}; - ahb_hready_q = _RAND_3[0:0]; - _RAND_4 = {1{`RANDOM}}; - ahb_htrans_q = _RAND_4[1:0]; - _RAND_5 = {1{`RANDOM}}; - ahb_hwrite_q = _RAND_5[0:0]; - _RAND_6 = {1{`RANDOM}}; - ahb_hresp_q = _RAND_6[0:0]; - _RAND_7 = {1{`RANDOM}}; - cmd_doneQ = _RAND_7[0:0]; - _RAND_8 = {1{`RANDOM}}; - wrbuf_tag = _RAND_8[2:0]; - _RAND_9 = {1{`RANDOM}}; - wrbuf_addr = _RAND_9[31:0]; - _RAND_10 = {1{`RANDOM}}; - wrbuf_size = _RAND_10[2:0]; - _RAND_11 = {1{`RANDOM}}; - wrbuf_byteen = _RAND_11[7:0]; - _RAND_12 = {2{`RANDOM}}; - wrbuf_data = _RAND_12[63:0]; - _RAND_13 = {1{`RANDOM}}; - slvbuf_write = _RAND_13[0:0]; - _RAND_14 = {1{`RANDOM}}; - slvbuf_error = _RAND_14[0:0]; - _RAND_15 = {1{`RANDOM}}; - slvbuf_tag = _RAND_15[2:0]; - _RAND_16 = {1{`RANDOM}}; - last_bus_addr = _RAND_16[31:0]; - _RAND_17 = {2{`RANDOM}}; - buf_data = _RAND_17[63:0]; - _RAND_18 = {2{`RANDOM}}; - ahb_hrdata_q = _RAND_18[63:0]; - _RAND_19 = {1{`RANDOM}}; - buf_addr = _RAND_19[31:0]; - _RAND_20 = {1{`RANDOM}}; - buf_cmd_byte_ptrQ = _RAND_20[2:0]; - _RAND_21 = {1{`RANDOM}}; - buf_byteen = _RAND_21[7:0]; - _RAND_22 = {1{`RANDOM}}; - buf_aligned = _RAND_22[0:0]; - _RAND_23 = {1{`RANDOM}}; - buf_size = _RAND_23[1:0]; - _RAND_24 = {1{`RANDOM}}; - buf_write = _RAND_24[0:0]; - _RAND_25 = {1{`RANDOM}}; - buf_tag = _RAND_25[2:0]; -`endif // RANDOMIZE_REG_INIT - if (reset) begin - buf_state = 3'h0; - end - if (reset) begin - wrbuf_vld = 1'h0; - end - if (reset) begin - wrbuf_data_vld = 1'h0; - end - if (reset) begin - ahb_hready_q = 1'h0; - end - if (reset) begin - ahb_htrans_q = 2'h0; - end - if (reset) begin - ahb_hwrite_q = 1'h0; - end - if (reset) begin - ahb_hresp_q = 1'h0; - end - if (reset) begin - cmd_doneQ = 1'h0; - end - if (reset) begin - wrbuf_tag = 3'h0; - end - if (reset) begin - wrbuf_addr = 32'h0; - end - if (reset) begin - wrbuf_size = 3'h0; - end - if (reset) begin - wrbuf_byteen = 8'h0; - end - if (reset) begin - wrbuf_data = 64'h0; - end - if (reset) begin - slvbuf_write = 1'h0; - end - if (reset) begin - slvbuf_error = 1'h0; - end - if (reset) begin - slvbuf_tag = 3'h0; - end - if (reset) begin - last_bus_addr = 32'h0; - end - if (reset) begin - buf_data = 64'h0; - end - if (reset) begin - ahb_hrdata_q = 64'h0; - end - if (reset) begin - buf_addr = 32'h0; - end - if (reset) begin - buf_cmd_byte_ptrQ = 3'h0; - end - if (reset) begin - buf_byteen = 8'h0; - end - if (reset) begin - buf_aligned = 1'h0; - end - if (reset) begin - buf_size = 2'h0; - end - if (reset) begin - buf_write = 1'h0; - end - if (reset) begin - buf_tag = 3'h0; - end - `endif // RANDOMIZE -end // initial -`ifdef FIRRTL_AFTER_INITIAL -`FIRRTL_AFTER_INITIAL -`endif -`endif // SYNTHESIS - always @(posedge ahbm_clk or posedge reset) begin - if (reset) begin - buf_state <= 3'h0; - end else if (buf_state_en) begin - if (_T_49) begin - if (buf_write_in) begin - buf_state <= 3'h2; - end else begin - buf_state <= 3'h1; - end - end else if (_T_101) begin - if (_T_104) begin - buf_state <= 3'h6; - end else begin - buf_state <= 3'h3; - end - end else if (_T_136) begin - if (ahb_hresp_q) begin - buf_state <= 3'h7; - end else if (_T_152) begin - buf_state <= 3'h6; - end else begin - buf_state <= 3'h3; - end - end else if (_T_175) begin - buf_state <= 3'h3; - end else if (_T_186) begin - buf_state <= 3'h5; - end else if (_T_188) begin - buf_state <= 3'h4; - end else if (_T_281) begin - if (ahb_hresp_q) begin - buf_state <= 3'h5; - end else if (master_valid) begin - if (_T_51) begin - buf_state <= 3'h2; - end else begin - buf_state <= 3'h1; - end - end else begin - buf_state <= 3'h0; - end - end else begin - buf_state <= 3'h0; - end - end - end - always @(posedge bus_clk or posedge reset) begin - if (reset) begin - wrbuf_vld <= 1'h0; - end else begin - wrbuf_vld <= _T_636 & _T_637; - end - end - always @(posedge bus_clk or posedge reset) begin - if (reset) begin - wrbuf_data_vld <= 1'h0; - end else begin - wrbuf_data_vld <= _T_641 & _T_637; - end - end - always @(posedge ahbm_clk or posedge reset) begin - if (reset) begin - ahb_hready_q <= 1'h0; - end else begin - ahb_hready_q <= io_ahb_in_hready; - end - end - always @(posedge ahbm_clk or posedge reset) begin - if (reset) begin - ahb_htrans_q <= 2'h0; - end else begin - ahb_htrans_q <= io_ahb_out_htrans; - end - end - always @(posedge ahbm_addr_clk or posedge reset) begin - if (reset) begin - ahb_hwrite_q <= 1'h0; - end else begin - ahb_hwrite_q <= io_ahb_out_hwrite; - end - end - always @(posedge ahbm_clk or posedge reset) begin - if (reset) begin - ahb_hresp_q <= 1'h0; - end else begin - ahb_hresp_q <= io_ahb_in_hresp; - end - end - always @(posedge ahbm_clk or posedge reset) begin - if (reset) begin - cmd_doneQ <= 1'h0; - end else begin - cmd_doneQ <= _T_276 & _T_691; - end - end - always @(posedge bus_clk or posedge reset) begin - if (reset) begin - wrbuf_tag <= 3'h0; - end else if (wrbuf_en) begin - wrbuf_tag <= io_axi_aw_bits_id; - end - end - always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin - if (reset) begin - wrbuf_addr <= 32'h0; - end else begin - wrbuf_addr <= io_axi_aw_bits_addr; - end - end - always @(posedge bus_clk or posedge reset) begin - if (reset) begin - wrbuf_size <= 3'h0; - end else if (wrbuf_en) begin - wrbuf_size <= io_axi_aw_bits_size; - end - end - always @(posedge bus_clk or posedge reset) begin - if (reset) begin - wrbuf_byteen <= 8'h0; - end else if (wrbuf_data_en) begin - wrbuf_byteen <= io_axi_w_bits_strb; - end - end - always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin - if (reset) begin - wrbuf_data <= 64'h0; - end else begin - wrbuf_data <= io_axi_w_bits_data; - end - end - always @(posedge buf_clk or posedge reset) begin - if (reset) begin - slvbuf_write <= 1'h0; - end else if (slvbuf_wr_en) begin - slvbuf_write <= buf_write; - end - end - always @(posedge ahbm_clk or posedge reset) begin - if (reset) begin - slvbuf_error <= 1'h0; - end else if (slvbuf_error_en) begin - if (_T_49) begin - slvbuf_error <= 1'h0; - end else if (_T_101) begin - slvbuf_error <= 1'h0; - end else if (_T_136) begin - slvbuf_error <= ahb_hresp_q; - end else if (_T_175) begin - slvbuf_error <= 1'h0; - end else if (_T_186) begin - slvbuf_error <= ahb_hresp_q; - end else if (_T_188) begin - slvbuf_error <= 1'h0; - end else begin - slvbuf_error <= _GEN_6; - end - end - end - always @(posedge buf_clk or posedge reset) begin - if (reset) begin - slvbuf_tag <= 3'h0; - end else if (slvbuf_wr_en) begin - slvbuf_tag <= buf_tag; - end - end - always @(posedge ahbm_clk or posedge reset) begin - if (reset) begin - last_bus_addr <= 32'h0; - end else if (last_addr_en) begin - last_bus_addr <= io_ahb_out_haddr; - end - end - always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin - if (reset) begin - buf_data <= 64'h0; - end else if (_T_489) begin - buf_data <= ahb_hrdata_q; - end else begin - buf_data <= wrbuf_data; - end - end - always @(posedge ahbm_data_clk or posedge reset) begin - if (reset) begin - ahb_hrdata_q <= 64'h0; - end else begin - ahb_hrdata_q <= io_ahb_in_hrdata; - end - end - always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin - if (reset) begin - buf_addr <= 32'h0; - end else begin - buf_addr <= {master_addr[31:3],_T_485}; - end - end - always @(posedge ahbm_clk or posedge reset) begin - if (reset) begin - buf_cmd_byte_ptrQ <= 3'h0; - end else if (buf_cmd_byte_ptr_en) begin - if (_T_49) begin - if (buf_write_in) begin - if (wrbuf_byteen[0]) begin - buf_cmd_byte_ptrQ <= 3'h0; - end else if (wrbuf_byteen[1]) begin - buf_cmd_byte_ptrQ <= 3'h1; - end else if (wrbuf_byteen[2]) begin - buf_cmd_byte_ptrQ <= 3'h2; - end else if (wrbuf_byteen[3]) begin - buf_cmd_byte_ptrQ <= 3'h3; - end else if (wrbuf_byteen[4]) begin - buf_cmd_byte_ptrQ <= 3'h4; - end else if (wrbuf_byteen[5]) begin - buf_cmd_byte_ptrQ <= 3'h5; - end else if (wrbuf_byteen[6]) begin - buf_cmd_byte_ptrQ <= 3'h6; - end else begin - buf_cmd_byte_ptrQ <= 3'h7; - end - end else begin - buf_cmd_byte_ptrQ <= master_addr[2:0]; - end - end else if (_T_101) begin - if (bypass_en) begin - buf_cmd_byte_ptrQ <= master_addr[2:0]; - end else begin - buf_cmd_byte_ptrQ <= buf_addr[2:0]; - end - end else if (_T_136) begin - if (bypass_en) begin - buf_cmd_byte_ptrQ <= master_addr[2:0]; - end else begin - buf_cmd_byte_ptrQ <= buf_addr[2:0]; - end - end else if (_T_175) begin - buf_cmd_byte_ptrQ <= buf_addr[2:0]; - end else if (_T_186) begin - buf_cmd_byte_ptrQ <= 3'h0; - end else if (_T_188) begin - if (trxn_done) begin - if (_T_201) begin - buf_cmd_byte_ptrQ <= 3'h0; - end else if (_T_204) begin - buf_cmd_byte_ptrQ <= 3'h1; - end else if (_T_207) begin - buf_cmd_byte_ptrQ <= 3'h2; - end else if (_T_210) begin - buf_cmd_byte_ptrQ <= 3'h3; - end else if (_T_213) begin - buf_cmd_byte_ptrQ <= 3'h4; - end else if (_T_216) begin - buf_cmd_byte_ptrQ <= 3'h5; - end else if (_T_219) begin - buf_cmd_byte_ptrQ <= 3'h6; - end else begin - buf_cmd_byte_ptrQ <= 3'h7; - end - end - end else if (_T_281) begin - if (bypass_en) begin - if (wrbuf_byteen[0]) begin - buf_cmd_byte_ptrQ <= 3'h0; - end else if (wrbuf_byteen[1]) begin - buf_cmd_byte_ptrQ <= 3'h1; - end else if (wrbuf_byteen[2]) begin - buf_cmd_byte_ptrQ <= 3'h2; - end else if (wrbuf_byteen[3]) begin - buf_cmd_byte_ptrQ <= 3'h3; - end else if (wrbuf_byteen[4]) begin - buf_cmd_byte_ptrQ <= 3'h4; - end else if (wrbuf_byteen[5]) begin - buf_cmd_byte_ptrQ <= 3'h5; - end else if (wrbuf_byteen[6]) begin - buf_cmd_byte_ptrQ <= 3'h6; - end else begin - buf_cmd_byte_ptrQ <= 3'h7; - end - end else if (trxn_done) begin - if (_T_201) begin - buf_cmd_byte_ptrQ <= 3'h0; - end else if (_T_204) begin - buf_cmd_byte_ptrQ <= 3'h1; - end else if (_T_207) begin - buf_cmd_byte_ptrQ <= 3'h2; - end else if (_T_210) begin - buf_cmd_byte_ptrQ <= 3'h3; - end else if (_T_213) begin - buf_cmd_byte_ptrQ <= 3'h4; - end else if (_T_216) begin - buf_cmd_byte_ptrQ <= 3'h5; - end else if (_T_219) begin - buf_cmd_byte_ptrQ <= 3'h6; - end else begin - buf_cmd_byte_ptrQ <= 3'h7; - end - end - end else begin - buf_cmd_byte_ptrQ <= 3'h0; - end - end - end - always @(posedge buf_clk or posedge reset) begin - if (reset) begin - buf_byteen <= 8'h0; - end else if (buf_wr_en) begin - buf_byteen <= wrbuf_byteen; - end - end - always @(posedge buf_clk or posedge reset) begin - if (reset) begin - buf_aligned <= 1'h0; - end else if (buf_wr_en) begin - buf_aligned <= buf_aligned_in; - end - end - always @(posedge buf_clk or posedge reset) begin - if (reset) begin - buf_size <= 2'h0; - end else if (buf_wr_en) begin - buf_size <= buf_size_in[1:0]; - end - end - always @(posedge buf_clk or posedge reset) begin - if (reset) begin - buf_write <= 1'h0; - end else if (buf_wr_en) begin - if (_T_49) begin - buf_write <= _T_51; - end else if (_T_101) begin - buf_write <= 1'h0; - end else if (_T_136) begin - buf_write <= 1'h0; - end else if (_T_175) begin - buf_write <= 1'h0; - end else if (_T_186) begin - buf_write <= 1'h0; - end else if (_T_188) begin - buf_write <= 1'h0; - end else begin - buf_write <= _GEN_8; - end - end - end - always @(posedge buf_clk or posedge reset) begin - if (reset) begin - buf_tag <= 3'h0; - end else if (buf_wr_en) begin - if (wr_cmd_vld) begin - buf_tag <= wrbuf_tag; - end else begin - buf_tag <= io_axi_ar_bits_id; - end - end - end -endmodule -module ahb_to_axi4( - input clock, - input reset, - input io_scan_mode, - input io_bus_clk_en, - input io_axi_aw_ready, - output io_axi_aw_valid, - output [31:0] io_axi_aw_bits_addr, - output [2:0] io_axi_aw_bits_size, - output io_axi_w_valid, - output [63:0] io_axi_w_bits_data, - output [7:0] io_axi_w_bits_strb, - input io_axi_ar_ready, - output io_axi_ar_valid, - output [31:0] io_axi_ar_bits_addr, - output [2:0] io_axi_ar_bits_size, - input io_axi_r_valid, - input [63:0] io_axi_r_bits_data, - input [1:0] io_axi_r_bits_resp, - output [63:0] io_ahb_sig_in_hrdata, - output io_ahb_sig_in_hready, - output io_ahb_sig_in_hresp, - input [31:0] io_ahb_sig_out_haddr, - input [2:0] io_ahb_sig_out_hsize, - input [1:0] io_ahb_sig_out_htrans, - input io_ahb_sig_out_hwrite, - input [63:0] io_ahb_sig_out_hwdata, - input io_ahb_hsel, - input io_ahb_hreadyin -); -`ifdef RANDOMIZE_REG_INIT - reg [31:0] _RAND_0; - reg [31:0] _RAND_1; - reg [31:0] _RAND_2; - reg [31:0] _RAND_3; - reg [31:0] _RAND_4; - reg [31:0] _RAND_5; - reg [31:0] _RAND_6; - reg [31:0] _RAND_7; - reg [63:0] _RAND_8; - reg [31:0] _RAND_9; - reg [31:0] _RAND_10; - reg [31:0] _RAND_11; - reg [31:0] _RAND_12; - reg [31:0] _RAND_13; - reg [63:0] _RAND_14; -`endif // RANDOMIZE_REG_INIT - wire rvclkhdr_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_io_en; // @[lib.scala 343:22] - wire rvclkhdr_io_scan_mode; // @[lib.scala 343:22] - wire rvclkhdr_1_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_1_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_1_io_en; // @[lib.scala 343:22] - wire rvclkhdr_1_io_scan_mode; // @[lib.scala 343:22] - wire rvclkhdr_2_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_2_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_2_io_en; // @[lib.scala 343:22] - wire rvclkhdr_2_io_scan_mode; // @[lib.scala 343:22] - wire rvclkhdr_3_io_l1clk; // @[lib.scala 368:23] - wire rvclkhdr_3_io_clk; // @[lib.scala 368:23] - wire rvclkhdr_3_io_en; // @[lib.scala 368:23] - wire rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23] - wire rvclkhdr_4_io_l1clk; // @[lib.scala 368:23] - wire rvclkhdr_4_io_clk; // @[lib.scala 368:23] - wire rvclkhdr_4_io_en; // @[lib.scala 368:23] - wire rvclkhdr_4_io_scan_mode; // @[lib.scala 368:23] - wire rvclkhdr_5_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_5_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_5_io_en; // @[lib.scala 343:22] - wire rvclkhdr_5_io_scan_mode; // @[lib.scala 343:22] - wire ahb_addr_clk = rvclkhdr_1_io_l1clk; // @[ahb_to_axi4.scala 44:33 ahb_to_axi4.scala 133:31] - reg [31:0] ahb_haddr_q; // @[ahb_to_axi4.scala 126:65] - wire ahb_addr_in_dccm = ahb_haddr_q[31:16] == 16'hf004; // @[lib.scala 87:29] - wire ahb_addr_in_iccm = ahb_haddr_q[31:16] == 16'hee00; // @[lib.scala 87:29] - wire ahb_clk = rvclkhdr_io_l1clk; // @[ahb_to_axi4.scala 43:33 ahb_to_axi4.scala 132:31] - reg [1:0] buf_state; // @[Reg.scala 27:20] - wire _T_7 = 2'h0 == buf_state; // @[Conditional.scala 37:30] - wire ahb_hready = io_ahb_sig_in_hready & io_ahb_hreadyin; // @[ahb_to_axi4.scala 104:55] - wire _T_10 = ahb_hready & io_ahb_sig_out_htrans[1]; // @[ahb_to_axi4.scala 76:34] - wire _T_11 = _T_10 & io_ahb_hsel; // @[ahb_to_axi4.scala 76:61] - wire _T_12 = 2'h1 == buf_state; // @[Conditional.scala 37:30] - wire _T_14 = io_ahb_sig_out_htrans == 2'h0; // @[ahb_to_axi4.scala 79:79] - wire _T_15 = io_ahb_sig_in_hresp | _T_14; // @[ahb_to_axi4.scala 79:48] - wire _T_16 = ~io_ahb_hsel; // @[ahb_to_axi4.scala 79:93] - wire _T_17 = _T_15 | _T_16; // @[ahb_to_axi4.scala 79:91] - wire bus_clk = rvclkhdr_5_io_l1clk; // @[ahb_to_axi4.scala 57:33 ahb_to_axi4.scala 180:27] - reg cmdbuf_vld; // @[ahb_to_axi4.scala 139:61] - wire _T_151 = io_axi_aw_valid & io_axi_aw_ready; // @[ahb_to_axi4.scala 137:67] - wire _T_152 = io_axi_ar_valid & io_axi_ar_ready; // @[ahb_to_axi4.scala 137:105] - wire _T_153 = _T_151 | _T_152; // @[ahb_to_axi4.scala 137:86] - wire _T_154 = ~_T_153; // @[ahb_to_axi4.scala 137:48] - wire cmdbuf_full = cmdbuf_vld & _T_154; // @[ahb_to_axi4.scala 137:46] - wire _T_21 = ~cmdbuf_full; // @[ahb_to_axi4.scala 80:24] - wire _T_22 = _T_21 | io_ahb_sig_in_hresp; // @[ahb_to_axi4.scala 80:37] - wire _T_25 = io_ahb_sig_out_htrans == 2'h1; // @[ahb_to_axi4.scala 81:92] - wire _T_26 = _T_25 & io_ahb_hsel; // @[ahb_to_axi4.scala 81:110] - wire _T_27 = io_ahb_sig_in_hresp | _T_26; // @[ahb_to_axi4.scala 81:60] - wire _T_28 = ~_T_27; // @[ahb_to_axi4.scala 81:38] - wire _T_29 = _T_21 & _T_28; // @[ahb_to_axi4.scala 81:36] - wire _T_30 = 2'h2 == buf_state; // @[Conditional.scala 37:30] - wire _T_34 = ~io_ahb_sig_in_hresp; // @[ahb_to_axi4.scala 86:23] - wire _T_36 = _T_34 & _T_21; // @[ahb_to_axi4.scala 86:44] - wire _T_37 = 2'h3 == buf_state; // @[Conditional.scala 37:30] - reg cmdbuf_write; // @[Reg.scala 27:20] - wire _T_38 = ~cmdbuf_write; // @[ahb_to_axi4.scala 90:40] - wire _T_39 = io_axi_r_valid & _T_38; // @[ahb_to_axi4.scala 90:38] - wire _T_41 = |io_axi_r_bits_resp; // @[ahb_to_axi4.scala 92:68] - wire _GEN_1 = _T_37 & _T_39; // @[Conditional.scala 39:67] - wire _GEN_5 = _T_30 ? _T_22 : _GEN_1; // @[Conditional.scala 39:67] - wire _GEN_10 = _T_12 ? _T_22 : _GEN_5; // @[Conditional.scala 39:67] - wire buf_state_en = _T_7 ? _T_11 : _GEN_10; // @[Conditional.scala 40:58] - wire _T_42 = buf_state_en & _T_41; // @[ahb_to_axi4.scala 92:41] - wire _GEN_2 = _T_37 & buf_state_en; // @[Conditional.scala 39:67] - wire _GEN_3 = _T_37 & _T_42; // @[Conditional.scala 39:67] - wire _GEN_6 = _T_30 & _T_36; // @[Conditional.scala 39:67] - wire _GEN_7 = _T_30 ? 1'h0 : _GEN_2; // @[Conditional.scala 39:67] - wire _GEN_11 = _T_12 ? _T_29 : _GEN_6; // @[Conditional.scala 39:67] - wire _GEN_12 = _T_12 ? 1'h0 : _GEN_7; // @[Conditional.scala 39:67] - wire cmdbuf_wr_en = _T_7 ? 1'h0 : _GEN_11; // @[Conditional.scala 40:58] - wire buf_rdata_en = _T_7 ? 1'h0 : _GEN_12; // @[Conditional.scala 40:58] - reg [2:0] ahb_hsize_q; // @[ahb_to_axi4.scala 124:65] - wire _T_46 = ahb_hsize_q == 3'h0; // @[ahb_to_axi4.scala 97:60] - wire [7:0] _T_48 = _T_46 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_50 = 8'h1 << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 97:78] - wire [7:0] _T_51 = _T_48 & _T_50; // @[ahb_to_axi4.scala 97:70] - wire _T_53 = ahb_hsize_q == 3'h1; // @[ahb_to_axi4.scala 98:30] - wire [7:0] _T_55 = _T_53 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [8:0] _T_57 = 9'h3 << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 98:48] - wire [8:0] _GEN_23 = {{1'd0}, _T_55}; // @[ahb_to_axi4.scala 98:40] - wire [8:0] _T_58 = _GEN_23 & _T_57; // @[ahb_to_axi4.scala 98:40] - wire [8:0] _GEN_24 = {{1'd0}, _T_51}; // @[ahb_to_axi4.scala 97:109] - wire [8:0] _T_59 = _GEN_24 | _T_58; // @[ahb_to_axi4.scala 97:109] - wire _T_61 = ahb_hsize_q == 3'h2; // @[ahb_to_axi4.scala 99:30] - wire [7:0] _T_63 = _T_61 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [10:0] _T_65 = 11'hf << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 99:48] - wire [10:0] _GEN_25 = {{3'd0}, _T_63}; // @[ahb_to_axi4.scala 99:40] - wire [10:0] _T_66 = _GEN_25 & _T_65; // @[ahb_to_axi4.scala 99:40] - wire [10:0] _GEN_26 = {{2'd0}, _T_59}; // @[ahb_to_axi4.scala 98:79] - wire [10:0] _T_67 = _GEN_26 | _T_66; // @[ahb_to_axi4.scala 98:79] - wire _T_69 = ahb_hsize_q == 3'h3; // @[ahb_to_axi4.scala 100:30] - wire [7:0] _T_71 = _T_69 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [10:0] _GEN_27 = {{3'd0}, _T_71}; // @[ahb_to_axi4.scala 99:79] - wire [10:0] _T_73 = _T_67 | _GEN_27; // @[ahb_to_axi4.scala 99:79] - reg ahb_hready_q; // @[ahb_to_axi4.scala 122:60] - wire _T_74 = ~ahb_hready_q; // @[ahb_to_axi4.scala 103:80] - reg ahb_hresp_q; // @[ahb_to_axi4.scala 121:60] - wire _T_75 = ahb_hresp_q & _T_74; // @[ahb_to_axi4.scala 103:78] - wire _T_77 = buf_state == 2'h0; // @[ahb_to_axi4.scala 103:124] - wire _T_78 = _T_21 | _T_77; // @[ahb_to_axi4.scala 103:111] - wire _T_79 = buf_state == 2'h2; // @[ahb_to_axi4.scala 103:149] - wire _T_80 = buf_state == 2'h3; // @[ahb_to_axi4.scala 103:168] - wire _T_81 = _T_79 | _T_80; // @[ahb_to_axi4.scala 103:156] - wire _T_82 = ~_T_81; // @[ahb_to_axi4.scala 103:137] - wire _T_83 = _T_78 & _T_82; // @[ahb_to_axi4.scala 103:135] - reg buf_read_error; // @[ahb_to_axi4.scala 118:60] - wire _T_84 = ~buf_read_error; // @[ahb_to_axi4.scala 103:181] - wire _T_85 = _T_83 & _T_84; // @[ahb_to_axi4.scala 103:179] - wire [1:0] _T_89 = io_ahb_hsel ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire buf_rdata_clk = rvclkhdr_2_io_l1clk; // @[ahb_to_axi4.scala 45:33 ahb_to_axi4.scala 134:31] - reg [63:0] buf_rdata; // @[ahb_to_axi4.scala 117:66] - reg [1:0] ahb_htrans_q; // @[ahb_to_axi4.scala 123:60] - wire _T_94 = ahb_htrans_q != 2'h0; // @[ahb_to_axi4.scala 107:61] - wire _T_95 = buf_state != 2'h0; // @[ahb_to_axi4.scala 107:83] - wire _T_96 = _T_94 & _T_95; // @[ahb_to_axi4.scala 107:70] - wire _T_97 = ahb_addr_in_dccm | ahb_addr_in_iccm; // @[ahb_to_axi4.scala 108:26] - wire _T_98 = ~_T_97; // @[ahb_to_axi4.scala 108:7] - reg ahb_hwrite_q; // @[ahb_to_axi4.scala 125:65] - wire _T_99 = ahb_addr_in_dccm & ahb_hwrite_q; // @[ahb_to_axi4.scala 109:46] - wire _T_100 = ahb_addr_in_iccm | _T_99; // @[ahb_to_axi4.scala 109:26] - wire _T_102 = ahb_hsize_q[1:0] == 2'h2; // @[ahb_to_axi4.scala 109:86] - wire _T_104 = ahb_hsize_q[1:0] == 2'h3; // @[ahb_to_axi4.scala 109:115] - wire _T_105 = _T_102 | _T_104; // @[ahb_to_axi4.scala 109:95] - wire _T_106 = ~_T_105; // @[ahb_to_axi4.scala 109:66] - wire _T_107 = _T_100 & _T_106; // @[ahb_to_axi4.scala 109:64] - wire _T_108 = _T_98 | _T_107; // @[ahb_to_axi4.scala 108:47] - wire _T_112 = _T_53 & ahb_haddr_q[0]; // @[ahb_to_axi4.scala 110:35] - wire _T_113 = _T_108 | _T_112; // @[ahb_to_axi4.scala 109:126] - wire _T_117 = |ahb_haddr_q[1:0]; // @[ahb_to_axi4.scala 111:56] - wire _T_118 = _T_61 & _T_117; // @[ahb_to_axi4.scala 111:35] - wire _T_119 = _T_113 | _T_118; // @[ahb_to_axi4.scala 110:55] - wire _T_123 = |ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 112:56] - wire _T_124 = _T_69 & _T_123; // @[ahb_to_axi4.scala 112:35] - wire _T_125 = _T_119 | _T_124; // @[ahb_to_axi4.scala 111:61] - wire _T_126 = _T_96 & _T_125; // @[ahb_to_axi4.scala 107:94] - wire _T_127 = _T_126 | buf_read_error; // @[ahb_to_axi4.scala 112:63] - wire _T_146 = ~cmdbuf_wr_en; // @[ahb_to_axi4.scala 136:113] - wire _T_147 = _T_153 & _T_146; // @[ahb_to_axi4.scala 136:111] - wire _T_149 = io_ahb_sig_in_hresp & _T_38; // @[ahb_to_axi4.scala 136:151] - wire cmdbuf_rst = _T_147 | _T_149; // @[ahb_to_axi4.scala 136:128] - wire _T_157 = cmdbuf_wr_en | cmdbuf_vld; // @[ahb_to_axi4.scala 139:66] - wire _T_158 = ~cmdbuf_rst; // @[ahb_to_axi4.scala 139:110] - reg [2:0] _T_164; // @[Reg.scala 27:20] - reg [7:0] cmdbuf_wstrb; // @[Reg.scala 27:20] - wire [7:0] master_wstrb = _T_73[7:0]; // @[ahb_to_axi4.scala 97:31] - reg [31:0] cmdbuf_addr; // @[lib.scala 374:16] - reg [63:0] cmdbuf_wdata; // @[lib.scala 374:16] - wire [1:0] cmdbuf_size = _T_164[1:0]; // @[ahb_to_axi4.scala 145:31] - rvclkhdr rvclkhdr ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_io_l1clk), - .io_clk(rvclkhdr_io_clk), - .io_en(rvclkhdr_io_en), - .io_scan_mode(rvclkhdr_io_scan_mode) - ); - rvclkhdr rvclkhdr_1 ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_1_io_l1clk), - .io_clk(rvclkhdr_1_io_clk), - .io_en(rvclkhdr_1_io_en), - .io_scan_mode(rvclkhdr_1_io_scan_mode) - ); - rvclkhdr rvclkhdr_2 ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_2_io_l1clk), - .io_clk(rvclkhdr_2_io_clk), - .io_en(rvclkhdr_2_io_en), - .io_scan_mode(rvclkhdr_2_io_scan_mode) - ); - rvclkhdr rvclkhdr_3 ( // @[lib.scala 368:23] - .io_l1clk(rvclkhdr_3_io_l1clk), - .io_clk(rvclkhdr_3_io_clk), - .io_en(rvclkhdr_3_io_en), - .io_scan_mode(rvclkhdr_3_io_scan_mode) - ); - rvclkhdr rvclkhdr_4 ( // @[lib.scala 368:23] - .io_l1clk(rvclkhdr_4_io_l1clk), - .io_clk(rvclkhdr_4_io_clk), - .io_en(rvclkhdr_4_io_en), - .io_scan_mode(rvclkhdr_4_io_scan_mode) - ); - rvclkhdr rvclkhdr_5 ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_5_io_l1clk), - .io_clk(rvclkhdr_5_io_clk), - .io_en(rvclkhdr_5_io_en), - .io_scan_mode(rvclkhdr_5_io_scan_mode) - ); - assign io_axi_aw_valid = cmdbuf_vld & cmdbuf_write; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 156:28] - assign io_axi_aw_bits_addr = cmdbuf_addr; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 158:33] - assign io_axi_aw_bits_size = {1'h0,cmdbuf_size}; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 159:33] - assign io_axi_w_valid = cmdbuf_vld & cmdbuf_write; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 164:28] - assign io_axi_w_bits_data = cmdbuf_wdata; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 165:33] - assign io_axi_w_bits_strb = cmdbuf_wstrb; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 166:33] - assign io_axi_ar_valid = cmdbuf_vld & _T_38; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 171:28] - assign io_axi_ar_bits_addr = cmdbuf_addr; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 173:33] - assign io_axi_ar_bits_size = {1'h0,cmdbuf_size}; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 174:33] - assign io_ahb_sig_in_hrdata = buf_rdata; // @[ahb_to_axi4.scala 106:38] - assign io_ahb_sig_in_hready = io_ahb_sig_in_hresp ? _T_75 : _T_85; // @[ahb_to_axi4.scala 103:38] - assign io_ahb_sig_in_hresp = _T_127 | _T_75; // @[ahb_to_axi4.scala 107:38] - assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_io_en = io_bus_clk_en; // @[lib.scala 345:16] - assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign rvclkhdr_1_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_1_io_en = io_bus_clk_en & _T_10; // @[lib.scala 345:16] - assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign rvclkhdr_2_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_2_io_en = io_bus_clk_en & buf_rdata_en; // @[lib.scala 345:16] - assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign rvclkhdr_3_io_clk = rvclkhdr_5_io_l1clk; // @[lib.scala 370:18] - assign rvclkhdr_3_io_en = _T_7 ? 1'h0 : _GEN_11; // @[lib.scala 371:17] - assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] - assign rvclkhdr_4_io_clk = rvclkhdr_5_io_l1clk; // @[lib.scala 370:18] - assign rvclkhdr_4_io_en = _T_7 ? 1'h0 : _GEN_11; // @[lib.scala 371:17] - assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] - assign rvclkhdr_5_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_5_io_en = io_bus_clk_en; // @[lib.scala 345:16] - assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] -`ifdef RANDOMIZE_GARBAGE_ASSIGN -`define RANDOMIZE -`endif -`ifdef RANDOMIZE_INVALID_ASSIGN -`define RANDOMIZE -`endif -`ifdef RANDOMIZE_REG_INIT -`define RANDOMIZE -`endif -`ifdef RANDOMIZE_MEM_INIT -`define RANDOMIZE -`endif -`ifndef RANDOM -`define RANDOM $random -`endif -`ifdef RANDOMIZE_MEM_INIT - integer initvar; -`endif -`ifndef SYNTHESIS -`ifdef FIRRTL_BEFORE_INITIAL -`FIRRTL_BEFORE_INITIAL -`endif -initial begin - `ifdef RANDOMIZE - `ifdef INIT_RANDOM - `INIT_RANDOM - `endif - `ifndef VERILATOR - `ifdef RANDOMIZE_DELAY - #`RANDOMIZE_DELAY begin end - `else - #0.002 begin end - `endif - `endif -`ifdef RANDOMIZE_REG_INIT - _RAND_0 = {1{`RANDOM}}; - ahb_haddr_q = _RAND_0[31:0]; - _RAND_1 = {1{`RANDOM}}; - buf_state = _RAND_1[1:0]; - _RAND_2 = {1{`RANDOM}}; - cmdbuf_vld = _RAND_2[0:0]; - _RAND_3 = {1{`RANDOM}}; - cmdbuf_write = _RAND_3[0:0]; - _RAND_4 = {1{`RANDOM}}; - ahb_hsize_q = _RAND_4[2:0]; - _RAND_5 = {1{`RANDOM}}; - ahb_hready_q = _RAND_5[0:0]; - _RAND_6 = {1{`RANDOM}}; - ahb_hresp_q = _RAND_6[0:0]; - _RAND_7 = {1{`RANDOM}}; - buf_read_error = _RAND_7[0:0]; - _RAND_8 = {2{`RANDOM}}; - buf_rdata = _RAND_8[63:0]; - _RAND_9 = {1{`RANDOM}}; - ahb_htrans_q = _RAND_9[1:0]; - _RAND_10 = {1{`RANDOM}}; - ahb_hwrite_q = _RAND_10[0:0]; - _RAND_11 = {1{`RANDOM}}; - _T_164 = _RAND_11[2:0]; - _RAND_12 = {1{`RANDOM}}; - cmdbuf_wstrb = _RAND_12[7:0]; - _RAND_13 = {1{`RANDOM}}; - cmdbuf_addr = _RAND_13[31:0]; - _RAND_14 = {2{`RANDOM}}; - cmdbuf_wdata = _RAND_14[63:0]; -`endif // RANDOMIZE_REG_INIT - if (reset) begin - ahb_haddr_q = 32'h0; - end - if (reset) begin - buf_state = 2'h0; - end - if (reset) begin - cmdbuf_vld = 1'h0; - end - if (reset) begin - cmdbuf_write = 1'h0; - end - if (reset) begin - ahb_hsize_q = 3'h0; - end - if (reset) begin - ahb_hready_q = 1'h0; - end - if (reset) begin - ahb_hresp_q = 1'h0; - end - if (reset) begin - buf_read_error = 1'h0; - end - if (reset) begin - buf_rdata = 64'h0; - end - if (reset) begin - ahb_htrans_q = 2'h0; - end - if (reset) begin - ahb_hwrite_q = 1'h0; - end - if (reset) begin - _T_164 = 3'h0; - end - if (reset) begin - cmdbuf_wstrb = 8'h0; - end - if (reset) begin - cmdbuf_addr = 32'h0; - end - if (reset) begin - cmdbuf_wdata = 64'h0; - end - `endif // RANDOMIZE -end // initial -`ifdef FIRRTL_AFTER_INITIAL -`FIRRTL_AFTER_INITIAL -`endif -`endif // SYNTHESIS - always @(posedge ahb_addr_clk or posedge reset) begin - if (reset) begin - ahb_haddr_q <= 32'h0; - end else begin - ahb_haddr_q <= io_ahb_sig_out_haddr; - end - end - always @(posedge ahb_clk or posedge reset) begin - if (reset) begin - buf_state <= 2'h0; - end else if (buf_state_en) begin - if (_T_7) begin - if (io_ahb_sig_out_hwrite) begin - buf_state <= 2'h1; - end else begin - buf_state <= 2'h2; - end - end else if (_T_12) begin - if (_T_17) begin - buf_state <= 2'h0; - end else if (io_ahb_sig_out_hwrite) begin - buf_state <= 2'h1; - end else begin - buf_state <= 2'h2; - end - end else if (_T_30) begin - if (io_ahb_sig_in_hresp) begin - buf_state <= 2'h0; - end else begin - buf_state <= 2'h3; - end - end else begin - buf_state <= 2'h0; - end - end - end - always @(posedge bus_clk or posedge reset) begin - if (reset) begin - cmdbuf_vld <= 1'h0; - end else begin - cmdbuf_vld <= _T_157 & _T_158; - end - end - always @(posedge bus_clk or posedge reset) begin - if (reset) begin - cmdbuf_write <= 1'h0; - end else if (cmdbuf_wr_en) begin - cmdbuf_write <= ahb_hwrite_q; - end - end - always @(posedge ahb_addr_clk or posedge reset) begin - if (reset) begin - ahb_hsize_q <= 3'h0; - end else begin - ahb_hsize_q <= io_ahb_sig_out_hsize; - end - end - always @(posedge ahb_clk or posedge reset) begin - if (reset) begin - ahb_hready_q <= 1'h0; - end else begin - ahb_hready_q <= io_ahb_sig_in_hready & io_ahb_hreadyin; - end - end - always @(posedge ahb_clk or posedge reset) begin - if (reset) begin - ahb_hresp_q <= 1'h0; - end else begin - ahb_hresp_q <= io_ahb_sig_in_hresp; - end - end - always @(posedge ahb_clk or posedge reset) begin - if (reset) begin - buf_read_error <= 1'h0; - end else if (_T_7) begin - buf_read_error <= 1'h0; - end else if (_T_12) begin - buf_read_error <= 1'h0; - end else if (_T_30) begin - buf_read_error <= 1'h0; - end else begin - buf_read_error <= _GEN_3; - end - end - always @(posedge buf_rdata_clk or posedge reset) begin - if (reset) begin - buf_rdata <= 64'h0; - end else begin - buf_rdata <= io_axi_r_bits_data; - end - end - always @(posedge ahb_clk or posedge reset) begin - if (reset) begin - ahb_htrans_q <= 2'h0; - end else begin - ahb_htrans_q <= _T_89 & io_ahb_sig_out_htrans; - end - end - always @(posedge ahb_addr_clk or posedge reset) begin - if (reset) begin - ahb_hwrite_q <= 1'h0; - end else begin - ahb_hwrite_q <= io_ahb_sig_out_hwrite; - end - end - always @(posedge bus_clk or posedge reset) begin - if (reset) begin - _T_164 <= 3'h0; - end else if (cmdbuf_wr_en) begin - _T_164 <= ahb_hsize_q; - end - end - always @(posedge bus_clk or posedge reset) begin - if (reset) begin - cmdbuf_wstrb <= 8'h0; - end else if (cmdbuf_wr_en) begin - cmdbuf_wstrb <= master_wstrb; - end - end - always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin - if (reset) begin - cmdbuf_addr <= 32'h0; - end else begin - cmdbuf_addr <= ahb_haddr_q; - end - end - always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin - if (reset) begin - cmdbuf_wdata <= 64'h0; - end else begin - cmdbuf_wdata <= io_ahb_sig_out_hwdata; - end - end -endmodule module quasar( input clock, input reset, @@ -83273,6 +80959,7 @@ module quasar( wire ifu_io_ifu_ar_valid; // @[quasar.scala 74:19] wire [2:0] ifu_io_ifu_ar_bits_id; // @[quasar.scala 74:19] wire [31:0] ifu_io_ifu_ar_bits_addr; // @[quasar.scala 74:19] + wire [3:0] ifu_io_ifu_ar_bits_region; // @[quasar.scala 74:19] wire ifu_io_ifu_r_valid; // @[quasar.scala 74:19] wire [2:0] ifu_io_ifu_r_bits_id; // @[quasar.scala 74:19] wire [63:0] ifu_io_ifu_r_bits_data; // @[quasar.scala 74:19] @@ -83393,7 +81080,6 @@ module quasar( wire [31:0] dec_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar.scala 75:19] wire dec_io_dec_tlu_misc_clk_override; // @[quasar.scala 75:19] wire dec_io_dec_tlu_lsu_clk_override; // @[quasar.scala 75:19] - wire dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 75:19] wire dec_io_dec_tlu_pic_clk_override; // @[quasar.scala 75:19] wire dec_io_dec_tlu_dccm_clk_override; // @[quasar.scala 75:19] wire dec_io_dec_tlu_icm_clk_override; // @[quasar.scala 75:19] @@ -83531,6 +81217,7 @@ module quasar( wire dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[quasar.scala 75:19] wire dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[quasar.scala 75:19] wire dec_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 75:19] + wire dec_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[quasar.scala 75:19] wire dec_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 75:19] wire dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[quasar.scala 75:19] wire dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[quasar.scala 75:19] @@ -83585,6 +81272,7 @@ module quasar( wire dbg_io_sb_axi_aw_ready; // @[quasar.scala 76:19] wire dbg_io_sb_axi_aw_valid; // @[quasar.scala 76:19] wire [31:0] dbg_io_sb_axi_aw_bits_addr; // @[quasar.scala 76:19] + wire [3:0] dbg_io_sb_axi_aw_bits_region; // @[quasar.scala 76:19] wire [2:0] dbg_io_sb_axi_aw_bits_size; // @[quasar.scala 76:19] wire dbg_io_sb_axi_w_ready; // @[quasar.scala 76:19] wire dbg_io_sb_axi_w_valid; // @[quasar.scala 76:19] @@ -83596,6 +81284,7 @@ module quasar( wire dbg_io_sb_axi_ar_ready; // @[quasar.scala 76:19] wire dbg_io_sb_axi_ar_valid; // @[quasar.scala 76:19] wire [31:0] dbg_io_sb_axi_ar_bits_addr; // @[quasar.scala 76:19] + wire [3:0] dbg_io_sb_axi_ar_bits_region; // @[quasar.scala 76:19] wire [2:0] dbg_io_sb_axi_ar_bits_size; // @[quasar.scala 76:19] wire dbg_io_sb_axi_r_ready; // @[quasar.scala 76:19] wire dbg_io_sb_axi_r_valid; // @[quasar.scala 76:19] @@ -83750,6 +81439,7 @@ module quasar( wire lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[quasar.scala 78:19] wire lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[quasar.scala 78:19] wire lsu_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 78:19] + wire lsu_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[quasar.scala 78:19] wire lsu_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 78:19] wire lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[quasar.scala 78:19] wire lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[quasar.scala 78:19] @@ -83778,7 +81468,9 @@ module quasar( wire lsu_io_axi_aw_valid; // @[quasar.scala 78:19] wire [2:0] lsu_io_axi_aw_bits_id; // @[quasar.scala 78:19] wire [31:0] lsu_io_axi_aw_bits_addr; // @[quasar.scala 78:19] + wire [3:0] lsu_io_axi_aw_bits_region; // @[quasar.scala 78:19] wire [2:0] lsu_io_axi_aw_bits_size; // @[quasar.scala 78:19] + wire [3:0] lsu_io_axi_aw_bits_cache; // @[quasar.scala 78:19] wire lsu_io_axi_w_ready; // @[quasar.scala 78:19] wire lsu_io_axi_w_valid; // @[quasar.scala 78:19] wire [63:0] lsu_io_axi_w_bits_data; // @[quasar.scala 78:19] @@ -83790,7 +81482,9 @@ module quasar( wire lsu_io_axi_ar_valid; // @[quasar.scala 78:19] wire [2:0] lsu_io_axi_ar_bits_id; // @[quasar.scala 78:19] wire [31:0] lsu_io_axi_ar_bits_addr; // @[quasar.scala 78:19] + wire [3:0] lsu_io_axi_ar_bits_region; // @[quasar.scala 78:19] wire [2:0] lsu_io_axi_ar_bits_size; // @[quasar.scala 78:19] + wire [3:0] lsu_io_axi_ar_bits_cache; // @[quasar.scala 78:19] wire lsu_io_axi_r_valid; // @[quasar.scala 78:19] wire [2:0] lsu_io_axi_r_bits_id; // @[quasar.scala 78:19] wire [63:0] lsu_io_axi_r_bits_data; // @[quasar.scala 78:19] @@ -83904,18 +81598,25 @@ module quasar( wire dma_ctrl_io_iccm_ready; // @[quasar.scala 80:24] wire dma_ctrl_io_dma_axi_aw_ready; // @[quasar.scala 80:24] wire dma_ctrl_io_dma_axi_aw_valid; // @[quasar.scala 80:24] + wire dma_ctrl_io_dma_axi_aw_bits_id; // @[quasar.scala 80:24] wire [31:0] dma_ctrl_io_dma_axi_aw_bits_addr; // @[quasar.scala 80:24] wire [2:0] dma_ctrl_io_dma_axi_aw_bits_size; // @[quasar.scala 80:24] wire dma_ctrl_io_dma_axi_w_ready; // @[quasar.scala 80:24] wire dma_ctrl_io_dma_axi_w_valid; // @[quasar.scala 80:24] wire [63:0] dma_ctrl_io_dma_axi_w_bits_data; // @[quasar.scala 80:24] wire [7:0] dma_ctrl_io_dma_axi_w_bits_strb; // @[quasar.scala 80:24] + wire dma_ctrl_io_dma_axi_b_ready; // @[quasar.scala 80:24] wire dma_ctrl_io_dma_axi_b_valid; // @[quasar.scala 80:24] + wire [1:0] dma_ctrl_io_dma_axi_b_bits_resp; // @[quasar.scala 80:24] + wire dma_ctrl_io_dma_axi_b_bits_id; // @[quasar.scala 80:24] wire dma_ctrl_io_dma_axi_ar_ready; // @[quasar.scala 80:24] wire dma_ctrl_io_dma_axi_ar_valid; // @[quasar.scala 80:24] + wire dma_ctrl_io_dma_axi_ar_bits_id; // @[quasar.scala 80:24] wire [31:0] dma_ctrl_io_dma_axi_ar_bits_addr; // @[quasar.scala 80:24] wire [2:0] dma_ctrl_io_dma_axi_ar_bits_size; // @[quasar.scala 80:24] + wire dma_ctrl_io_dma_axi_r_ready; // @[quasar.scala 80:24] wire dma_ctrl_io_dma_axi_r_valid; // @[quasar.scala 80:24] + wire dma_ctrl_io_dma_axi_r_bits_id; // @[quasar.scala 80:24] wire [63:0] dma_ctrl_io_dma_axi_r_bits_data; // @[quasar.scala 80:24] wire [1:0] dma_ctrl_io_dma_axi_r_bits_resp; // @[quasar.scala 80:24] wire dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_dccm_req; // @[quasar.scala 80:24] @@ -83946,132 +81647,6 @@ module quasar( wire rvclkhdr_1_io_clk; // @[lib.scala 343:22] wire rvclkhdr_1_io_en; // @[lib.scala 343:22] wire rvclkhdr_1_io_scan_mode; // @[lib.scala 343:22] - wire axi4_to_ahb_clock; // @[quasar.scala 241:32] - wire axi4_to_ahb_reset; // @[quasar.scala 241:32] - wire axi4_to_ahb_io_scan_mode; // @[quasar.scala 241:32] - wire axi4_to_ahb_io_bus_clk_en; // @[quasar.scala 241:32] - wire axi4_to_ahb_io_clk_override; // @[quasar.scala 241:32] - wire axi4_to_ahb_io_axi_aw_ready; // @[quasar.scala 241:32] - wire axi4_to_ahb_io_axi_aw_valid; // @[quasar.scala 241:32] - wire [31:0] axi4_to_ahb_io_axi_aw_bits_addr; // @[quasar.scala 241:32] - wire [2:0] axi4_to_ahb_io_axi_aw_bits_size; // @[quasar.scala 241:32] - wire axi4_to_ahb_io_axi_w_ready; // @[quasar.scala 241:32] - wire axi4_to_ahb_io_axi_w_valid; // @[quasar.scala 241:32] - wire [63:0] axi4_to_ahb_io_axi_w_bits_data; // @[quasar.scala 241:32] - wire [7:0] axi4_to_ahb_io_axi_w_bits_strb; // @[quasar.scala 241:32] - wire axi4_to_ahb_io_axi_b_valid; // @[quasar.scala 241:32] - wire [1:0] axi4_to_ahb_io_axi_b_bits_resp; // @[quasar.scala 241:32] - wire axi4_to_ahb_io_axi_ar_ready; // @[quasar.scala 241:32] - wire axi4_to_ahb_io_axi_ar_valid; // @[quasar.scala 241:32] - wire [31:0] axi4_to_ahb_io_axi_ar_bits_addr; // @[quasar.scala 241:32] - wire [2:0] axi4_to_ahb_io_axi_ar_bits_size; // @[quasar.scala 241:32] - wire axi4_to_ahb_io_axi_r_valid; // @[quasar.scala 241:32] - wire [63:0] axi4_to_ahb_io_axi_r_bits_data; // @[quasar.scala 241:32] - wire [1:0] axi4_to_ahb_io_axi_r_bits_resp; // @[quasar.scala 241:32] - wire [63:0] axi4_to_ahb_io_ahb_in_hrdata; // @[quasar.scala 241:32] - wire axi4_to_ahb_io_ahb_in_hready; // @[quasar.scala 241:32] - wire axi4_to_ahb_io_ahb_in_hresp; // @[quasar.scala 241:32] - wire [31:0] axi4_to_ahb_io_ahb_out_haddr; // @[quasar.scala 241:32] - wire [2:0] axi4_to_ahb_io_ahb_out_hsize; // @[quasar.scala 241:32] - wire [1:0] axi4_to_ahb_io_ahb_out_htrans; // @[quasar.scala 241:32] - wire axi4_to_ahb_io_ahb_out_hwrite; // @[quasar.scala 241:32] - wire [63:0] axi4_to_ahb_io_ahb_out_hwdata; // @[quasar.scala 241:32] - wire axi4_to_ahb_1_clock; // @[quasar.scala 242:33] - wire axi4_to_ahb_1_reset; // @[quasar.scala 242:33] - wire axi4_to_ahb_1_io_scan_mode; // @[quasar.scala 242:33] - wire axi4_to_ahb_1_io_bus_clk_en; // @[quasar.scala 242:33] - wire axi4_to_ahb_1_io_clk_override; // @[quasar.scala 242:33] - wire axi4_to_ahb_1_io_axi_aw_ready; // @[quasar.scala 242:33] - wire axi4_to_ahb_1_io_axi_aw_valid; // @[quasar.scala 242:33] - wire [2:0] axi4_to_ahb_1_io_axi_aw_bits_id; // @[quasar.scala 242:33] - wire [31:0] axi4_to_ahb_1_io_axi_aw_bits_addr; // @[quasar.scala 242:33] - wire [2:0] axi4_to_ahb_1_io_axi_aw_bits_size; // @[quasar.scala 242:33] - wire axi4_to_ahb_1_io_axi_w_ready; // @[quasar.scala 242:33] - wire axi4_to_ahb_1_io_axi_w_valid; // @[quasar.scala 242:33] - wire [63:0] axi4_to_ahb_1_io_axi_w_bits_data; // @[quasar.scala 242:33] - wire [7:0] axi4_to_ahb_1_io_axi_w_bits_strb; // @[quasar.scala 242:33] - wire axi4_to_ahb_1_io_axi_b_valid; // @[quasar.scala 242:33] - wire [1:0] axi4_to_ahb_1_io_axi_b_bits_resp; // @[quasar.scala 242:33] - wire [2:0] axi4_to_ahb_1_io_axi_b_bits_id; // @[quasar.scala 242:33] - wire axi4_to_ahb_1_io_axi_ar_ready; // @[quasar.scala 242:33] - wire axi4_to_ahb_1_io_axi_ar_valid; // @[quasar.scala 242:33] - wire [2:0] axi4_to_ahb_1_io_axi_ar_bits_id; // @[quasar.scala 242:33] - wire [31:0] axi4_to_ahb_1_io_axi_ar_bits_addr; // @[quasar.scala 242:33] - wire [2:0] axi4_to_ahb_1_io_axi_ar_bits_size; // @[quasar.scala 242:33] - wire axi4_to_ahb_1_io_axi_r_valid; // @[quasar.scala 242:33] - wire [2:0] axi4_to_ahb_1_io_axi_r_bits_id; // @[quasar.scala 242:33] - wire [63:0] axi4_to_ahb_1_io_axi_r_bits_data; // @[quasar.scala 242:33] - wire [1:0] axi4_to_ahb_1_io_axi_r_bits_resp; // @[quasar.scala 242:33] - wire [63:0] axi4_to_ahb_1_io_ahb_in_hrdata; // @[quasar.scala 242:33] - wire axi4_to_ahb_1_io_ahb_in_hready; // @[quasar.scala 242:33] - wire axi4_to_ahb_1_io_ahb_in_hresp; // @[quasar.scala 242:33] - wire [31:0] axi4_to_ahb_1_io_ahb_out_haddr; // @[quasar.scala 242:33] - wire [2:0] axi4_to_ahb_1_io_ahb_out_hsize; // @[quasar.scala 242:33] - wire [1:0] axi4_to_ahb_1_io_ahb_out_htrans; // @[quasar.scala 242:33] - wire axi4_to_ahb_1_io_ahb_out_hwrite; // @[quasar.scala 242:33] - wire [63:0] axi4_to_ahb_1_io_ahb_out_hwdata; // @[quasar.scala 242:33] - wire axi4_to_ahb_2_clock; // @[quasar.scala 243:33] - wire axi4_to_ahb_2_reset; // @[quasar.scala 243:33] - wire axi4_to_ahb_2_io_scan_mode; // @[quasar.scala 243:33] - wire axi4_to_ahb_2_io_bus_clk_en; // @[quasar.scala 243:33] - wire axi4_to_ahb_2_io_clk_override; // @[quasar.scala 243:33] - wire axi4_to_ahb_2_io_axi_aw_ready; // @[quasar.scala 243:33] - wire axi4_to_ahb_2_io_axi_aw_valid; // @[quasar.scala 243:33] - wire [2:0] axi4_to_ahb_2_io_axi_aw_bits_id; // @[quasar.scala 243:33] - wire [31:0] axi4_to_ahb_2_io_axi_aw_bits_addr; // @[quasar.scala 243:33] - wire [2:0] axi4_to_ahb_2_io_axi_aw_bits_size; // @[quasar.scala 243:33] - wire axi4_to_ahb_2_io_axi_w_ready; // @[quasar.scala 243:33] - wire axi4_to_ahb_2_io_axi_w_valid; // @[quasar.scala 243:33] - wire [63:0] axi4_to_ahb_2_io_axi_w_bits_data; // @[quasar.scala 243:33] - wire [7:0] axi4_to_ahb_2_io_axi_w_bits_strb; // @[quasar.scala 243:33] - wire axi4_to_ahb_2_io_axi_b_valid; // @[quasar.scala 243:33] - wire [1:0] axi4_to_ahb_2_io_axi_b_bits_resp; // @[quasar.scala 243:33] - wire [2:0] axi4_to_ahb_2_io_axi_b_bits_id; // @[quasar.scala 243:33] - wire axi4_to_ahb_2_io_axi_ar_ready; // @[quasar.scala 243:33] - wire axi4_to_ahb_2_io_axi_ar_valid; // @[quasar.scala 243:33] - wire [2:0] axi4_to_ahb_2_io_axi_ar_bits_id; // @[quasar.scala 243:33] - wire [31:0] axi4_to_ahb_2_io_axi_ar_bits_addr; // @[quasar.scala 243:33] - wire [2:0] axi4_to_ahb_2_io_axi_ar_bits_size; // @[quasar.scala 243:33] - wire axi4_to_ahb_2_io_axi_r_valid; // @[quasar.scala 243:33] - wire [2:0] axi4_to_ahb_2_io_axi_r_bits_id; // @[quasar.scala 243:33] - wire [63:0] axi4_to_ahb_2_io_axi_r_bits_data; // @[quasar.scala 243:33] - wire [1:0] axi4_to_ahb_2_io_axi_r_bits_resp; // @[quasar.scala 243:33] - wire [63:0] axi4_to_ahb_2_io_ahb_in_hrdata; // @[quasar.scala 243:33] - wire axi4_to_ahb_2_io_ahb_in_hready; // @[quasar.scala 243:33] - wire axi4_to_ahb_2_io_ahb_in_hresp; // @[quasar.scala 243:33] - wire [31:0] axi4_to_ahb_2_io_ahb_out_haddr; // @[quasar.scala 243:33] - wire [2:0] axi4_to_ahb_2_io_ahb_out_hsize; // @[quasar.scala 243:33] - wire [1:0] axi4_to_ahb_2_io_ahb_out_htrans; // @[quasar.scala 243:33] - wire axi4_to_ahb_2_io_ahb_out_hwrite; // @[quasar.scala 243:33] - wire [63:0] axi4_to_ahb_2_io_ahb_out_hwdata; // @[quasar.scala 243:33] - wire ahb_to_axi4_clock; // @[quasar.scala 244:33] - wire ahb_to_axi4_reset; // @[quasar.scala 244:33] - wire ahb_to_axi4_io_scan_mode; // @[quasar.scala 244:33] - wire ahb_to_axi4_io_bus_clk_en; // @[quasar.scala 244:33] - wire ahb_to_axi4_io_axi_aw_ready; // @[quasar.scala 244:33] - wire ahb_to_axi4_io_axi_aw_valid; // @[quasar.scala 244:33] - wire [31:0] ahb_to_axi4_io_axi_aw_bits_addr; // @[quasar.scala 244:33] - wire [2:0] ahb_to_axi4_io_axi_aw_bits_size; // @[quasar.scala 244:33] - wire ahb_to_axi4_io_axi_w_valid; // @[quasar.scala 244:33] - wire [63:0] ahb_to_axi4_io_axi_w_bits_data; // @[quasar.scala 244:33] - wire [7:0] ahb_to_axi4_io_axi_w_bits_strb; // @[quasar.scala 244:33] - wire ahb_to_axi4_io_axi_ar_ready; // @[quasar.scala 244:33] - wire ahb_to_axi4_io_axi_ar_valid; // @[quasar.scala 244:33] - wire [31:0] ahb_to_axi4_io_axi_ar_bits_addr; // @[quasar.scala 244:33] - wire [2:0] ahb_to_axi4_io_axi_ar_bits_size; // @[quasar.scala 244:33] - wire ahb_to_axi4_io_axi_r_valid; // @[quasar.scala 244:33] - wire [63:0] ahb_to_axi4_io_axi_r_bits_data; // @[quasar.scala 244:33] - wire [1:0] ahb_to_axi4_io_axi_r_bits_resp; // @[quasar.scala 244:33] - wire [63:0] ahb_to_axi4_io_ahb_sig_in_hrdata; // @[quasar.scala 244:33] - wire ahb_to_axi4_io_ahb_sig_in_hready; // @[quasar.scala 244:33] - wire ahb_to_axi4_io_ahb_sig_in_hresp; // @[quasar.scala 244:33] - wire [31:0] ahb_to_axi4_io_ahb_sig_out_haddr; // @[quasar.scala 244:33] - wire [2:0] ahb_to_axi4_io_ahb_sig_out_hsize; // @[quasar.scala 244:33] - wire [1:0] ahb_to_axi4_io_ahb_sig_out_htrans; // @[quasar.scala 244:33] - wire ahb_to_axi4_io_ahb_sig_out_hwrite; // @[quasar.scala 244:33] - wire [63:0] ahb_to_axi4_io_ahb_sig_out_hwdata; // @[quasar.scala 244:33] - wire ahb_to_axi4_io_ahb_hsel; // @[quasar.scala 244:33] - wire ahb_to_axi4_io_ahb_hreadyin; // @[quasar.scala 244:33] wire _T_1 = dbg_io_dbg_core_rst_l; // @[quasar.scala 82:67] wire _T_2 = _T_1 | io_scan_mode; // @[quasar.scala 82:70] wire _T_5 = ~dec_io_dec_pause_state_cg; // @[quasar.scala 83:23] @@ -84184,6 +81759,7 @@ module quasar( .io_ifu_ar_valid(ifu_io_ifu_ar_valid), .io_ifu_ar_bits_id(ifu_io_ifu_ar_bits_id), .io_ifu_ar_bits_addr(ifu_io_ifu_ar_bits_addr), + .io_ifu_ar_bits_region(ifu_io_ifu_ar_bits_region), .io_ifu_r_valid(ifu_io_ifu_r_valid), .io_ifu_r_bits_id(ifu_io_ifu_r_bits_id), .io_ifu_r_bits_data(ifu_io_ifu_r_bits_data), @@ -84306,7 +81882,6 @@ module quasar( .io_rv_trace_pkt_rv_i_tval_ip(dec_io_rv_trace_pkt_rv_i_tval_ip), .io_dec_tlu_misc_clk_override(dec_io_dec_tlu_misc_clk_override), .io_dec_tlu_lsu_clk_override(dec_io_dec_tlu_lsu_clk_override), - .io_dec_tlu_bus_clk_override(dec_io_dec_tlu_bus_clk_override), .io_dec_tlu_pic_clk_override(dec_io_dec_tlu_pic_clk_override), .io_dec_tlu_dccm_clk_override(dec_io_dec_tlu_dccm_clk_override), .io_dec_tlu_icm_clk_override(dec_io_dec_tlu_icm_clk_override), @@ -84444,6 +82019,7 @@ module quasar( .io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error(dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error), .io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy(dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy), .io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable(dec_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable), + .io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable(dec_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable), .io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable(dec_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable), .io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any(dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any), .io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any(dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any), @@ -84500,6 +82076,7 @@ module quasar( .io_sb_axi_aw_ready(dbg_io_sb_axi_aw_ready), .io_sb_axi_aw_valid(dbg_io_sb_axi_aw_valid), .io_sb_axi_aw_bits_addr(dbg_io_sb_axi_aw_bits_addr), + .io_sb_axi_aw_bits_region(dbg_io_sb_axi_aw_bits_region), .io_sb_axi_aw_bits_size(dbg_io_sb_axi_aw_bits_size), .io_sb_axi_w_ready(dbg_io_sb_axi_w_ready), .io_sb_axi_w_valid(dbg_io_sb_axi_w_valid), @@ -84511,6 +82088,7 @@ module quasar( .io_sb_axi_ar_ready(dbg_io_sb_axi_ar_ready), .io_sb_axi_ar_valid(dbg_io_sb_axi_ar_valid), .io_sb_axi_ar_bits_addr(dbg_io_sb_axi_ar_bits_addr), + .io_sb_axi_ar_bits_region(dbg_io_sb_axi_ar_bits_region), .io_sb_axi_ar_bits_size(dbg_io_sb_axi_ar_bits_size), .io_sb_axi_r_ready(dbg_io_sb_axi_r_ready), .io_sb_axi_r_valid(dbg_io_sb_axi_r_valid), @@ -84669,6 +82247,7 @@ module quasar( .io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error(lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error), .io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy(lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy), .io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable(lsu_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable), + .io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable(lsu_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable), .io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable(lsu_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable), .io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any(lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any), .io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any(lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any), @@ -84697,7 +82276,9 @@ module quasar( .io_axi_aw_valid(lsu_io_axi_aw_valid), .io_axi_aw_bits_id(lsu_io_axi_aw_bits_id), .io_axi_aw_bits_addr(lsu_io_axi_aw_bits_addr), + .io_axi_aw_bits_region(lsu_io_axi_aw_bits_region), .io_axi_aw_bits_size(lsu_io_axi_aw_bits_size), + .io_axi_aw_bits_cache(lsu_io_axi_aw_bits_cache), .io_axi_w_ready(lsu_io_axi_w_ready), .io_axi_w_valid(lsu_io_axi_w_valid), .io_axi_w_bits_data(lsu_io_axi_w_bits_data), @@ -84709,7 +82290,9 @@ module quasar( .io_axi_ar_valid(lsu_io_axi_ar_valid), .io_axi_ar_bits_id(lsu_io_axi_ar_bits_id), .io_axi_ar_bits_addr(lsu_io_axi_ar_bits_addr), + .io_axi_ar_bits_region(lsu_io_axi_ar_bits_region), .io_axi_ar_bits_size(lsu_io_axi_ar_bits_size), + .io_axi_ar_bits_cache(lsu_io_axi_ar_bits_cache), .io_axi_r_valid(lsu_io_axi_r_valid), .io_axi_r_bits_id(lsu_io_axi_r_bits_id), .io_axi_r_bits_data(lsu_io_axi_r_bits_data), @@ -84827,18 +82410,25 @@ module quasar( .io_iccm_ready(dma_ctrl_io_iccm_ready), .io_dma_axi_aw_ready(dma_ctrl_io_dma_axi_aw_ready), .io_dma_axi_aw_valid(dma_ctrl_io_dma_axi_aw_valid), + .io_dma_axi_aw_bits_id(dma_ctrl_io_dma_axi_aw_bits_id), .io_dma_axi_aw_bits_addr(dma_ctrl_io_dma_axi_aw_bits_addr), .io_dma_axi_aw_bits_size(dma_ctrl_io_dma_axi_aw_bits_size), .io_dma_axi_w_ready(dma_ctrl_io_dma_axi_w_ready), .io_dma_axi_w_valid(dma_ctrl_io_dma_axi_w_valid), .io_dma_axi_w_bits_data(dma_ctrl_io_dma_axi_w_bits_data), .io_dma_axi_w_bits_strb(dma_ctrl_io_dma_axi_w_bits_strb), + .io_dma_axi_b_ready(dma_ctrl_io_dma_axi_b_ready), .io_dma_axi_b_valid(dma_ctrl_io_dma_axi_b_valid), + .io_dma_axi_b_bits_resp(dma_ctrl_io_dma_axi_b_bits_resp), + .io_dma_axi_b_bits_id(dma_ctrl_io_dma_axi_b_bits_id), .io_dma_axi_ar_ready(dma_ctrl_io_dma_axi_ar_ready), .io_dma_axi_ar_valid(dma_ctrl_io_dma_axi_ar_valid), + .io_dma_axi_ar_bits_id(dma_ctrl_io_dma_axi_ar_bits_id), .io_dma_axi_ar_bits_addr(dma_ctrl_io_dma_axi_ar_bits_addr), .io_dma_axi_ar_bits_size(dma_ctrl_io_dma_axi_ar_bits_size), + .io_dma_axi_r_ready(dma_ctrl_io_dma_axi_r_ready), .io_dma_axi_r_valid(dma_ctrl_io_dma_axi_r_valid), + .io_dma_axi_r_bits_id(dma_ctrl_io_dma_axi_r_bits_id), .io_dma_axi_r_bits_data(dma_ctrl_io_dma_axi_r_bits_data), .io_dma_axi_r_bits_resp(dma_ctrl_io_dma_axi_r_bits_resp), .io_lsu_dma_dma_lsc_ctl_dma_dccm_req(dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_dccm_req), @@ -84874,262 +82464,128 @@ module quasar( .io_en(rvclkhdr_1_io_en), .io_scan_mode(rvclkhdr_1_io_scan_mode) ); - axi4_to_ahb axi4_to_ahb ( // @[quasar.scala 241:32] - .clock(axi4_to_ahb_clock), - .reset(axi4_to_ahb_reset), - .io_scan_mode(axi4_to_ahb_io_scan_mode), - .io_bus_clk_en(axi4_to_ahb_io_bus_clk_en), - .io_clk_override(axi4_to_ahb_io_clk_override), - .io_axi_aw_ready(axi4_to_ahb_io_axi_aw_ready), - .io_axi_aw_valid(axi4_to_ahb_io_axi_aw_valid), - .io_axi_aw_bits_addr(axi4_to_ahb_io_axi_aw_bits_addr), - .io_axi_aw_bits_size(axi4_to_ahb_io_axi_aw_bits_size), - .io_axi_w_ready(axi4_to_ahb_io_axi_w_ready), - .io_axi_w_valid(axi4_to_ahb_io_axi_w_valid), - .io_axi_w_bits_data(axi4_to_ahb_io_axi_w_bits_data), - .io_axi_w_bits_strb(axi4_to_ahb_io_axi_w_bits_strb), - .io_axi_b_valid(axi4_to_ahb_io_axi_b_valid), - .io_axi_b_bits_resp(axi4_to_ahb_io_axi_b_bits_resp), - .io_axi_ar_ready(axi4_to_ahb_io_axi_ar_ready), - .io_axi_ar_valid(axi4_to_ahb_io_axi_ar_valid), - .io_axi_ar_bits_addr(axi4_to_ahb_io_axi_ar_bits_addr), - .io_axi_ar_bits_size(axi4_to_ahb_io_axi_ar_bits_size), - .io_axi_r_valid(axi4_to_ahb_io_axi_r_valid), - .io_axi_r_bits_data(axi4_to_ahb_io_axi_r_bits_data), - .io_axi_r_bits_resp(axi4_to_ahb_io_axi_r_bits_resp), - .io_ahb_in_hrdata(axi4_to_ahb_io_ahb_in_hrdata), - .io_ahb_in_hready(axi4_to_ahb_io_ahb_in_hready), - .io_ahb_in_hresp(axi4_to_ahb_io_ahb_in_hresp), - .io_ahb_out_haddr(axi4_to_ahb_io_ahb_out_haddr), - .io_ahb_out_hsize(axi4_to_ahb_io_ahb_out_hsize), - .io_ahb_out_htrans(axi4_to_ahb_io_ahb_out_htrans), - .io_ahb_out_hwrite(axi4_to_ahb_io_ahb_out_hwrite), - .io_ahb_out_hwdata(axi4_to_ahb_io_ahb_out_hwdata) - ); - axi4_to_ahb_1 axi4_to_ahb_1 ( // @[quasar.scala 242:33] - .clock(axi4_to_ahb_1_clock), - .reset(axi4_to_ahb_1_reset), - .io_scan_mode(axi4_to_ahb_1_io_scan_mode), - .io_bus_clk_en(axi4_to_ahb_1_io_bus_clk_en), - .io_clk_override(axi4_to_ahb_1_io_clk_override), - .io_axi_aw_ready(axi4_to_ahb_1_io_axi_aw_ready), - .io_axi_aw_valid(axi4_to_ahb_1_io_axi_aw_valid), - .io_axi_aw_bits_id(axi4_to_ahb_1_io_axi_aw_bits_id), - .io_axi_aw_bits_addr(axi4_to_ahb_1_io_axi_aw_bits_addr), - .io_axi_aw_bits_size(axi4_to_ahb_1_io_axi_aw_bits_size), - .io_axi_w_ready(axi4_to_ahb_1_io_axi_w_ready), - .io_axi_w_valid(axi4_to_ahb_1_io_axi_w_valid), - .io_axi_w_bits_data(axi4_to_ahb_1_io_axi_w_bits_data), - .io_axi_w_bits_strb(axi4_to_ahb_1_io_axi_w_bits_strb), - .io_axi_b_valid(axi4_to_ahb_1_io_axi_b_valid), - .io_axi_b_bits_resp(axi4_to_ahb_1_io_axi_b_bits_resp), - .io_axi_b_bits_id(axi4_to_ahb_1_io_axi_b_bits_id), - .io_axi_ar_ready(axi4_to_ahb_1_io_axi_ar_ready), - .io_axi_ar_valid(axi4_to_ahb_1_io_axi_ar_valid), - .io_axi_ar_bits_id(axi4_to_ahb_1_io_axi_ar_bits_id), - .io_axi_ar_bits_addr(axi4_to_ahb_1_io_axi_ar_bits_addr), - .io_axi_ar_bits_size(axi4_to_ahb_1_io_axi_ar_bits_size), - .io_axi_r_valid(axi4_to_ahb_1_io_axi_r_valid), - .io_axi_r_bits_id(axi4_to_ahb_1_io_axi_r_bits_id), - .io_axi_r_bits_data(axi4_to_ahb_1_io_axi_r_bits_data), - .io_axi_r_bits_resp(axi4_to_ahb_1_io_axi_r_bits_resp), - .io_ahb_in_hrdata(axi4_to_ahb_1_io_ahb_in_hrdata), - .io_ahb_in_hready(axi4_to_ahb_1_io_ahb_in_hready), - .io_ahb_in_hresp(axi4_to_ahb_1_io_ahb_in_hresp), - .io_ahb_out_haddr(axi4_to_ahb_1_io_ahb_out_haddr), - .io_ahb_out_hsize(axi4_to_ahb_1_io_ahb_out_hsize), - .io_ahb_out_htrans(axi4_to_ahb_1_io_ahb_out_htrans), - .io_ahb_out_hwrite(axi4_to_ahb_1_io_ahb_out_hwrite), - .io_ahb_out_hwdata(axi4_to_ahb_1_io_ahb_out_hwdata) - ); - axi4_to_ahb_1 axi4_to_ahb_2 ( // @[quasar.scala 243:33] - .clock(axi4_to_ahb_2_clock), - .reset(axi4_to_ahb_2_reset), - .io_scan_mode(axi4_to_ahb_2_io_scan_mode), - .io_bus_clk_en(axi4_to_ahb_2_io_bus_clk_en), - .io_clk_override(axi4_to_ahb_2_io_clk_override), - .io_axi_aw_ready(axi4_to_ahb_2_io_axi_aw_ready), - .io_axi_aw_valid(axi4_to_ahb_2_io_axi_aw_valid), - .io_axi_aw_bits_id(axi4_to_ahb_2_io_axi_aw_bits_id), - .io_axi_aw_bits_addr(axi4_to_ahb_2_io_axi_aw_bits_addr), - .io_axi_aw_bits_size(axi4_to_ahb_2_io_axi_aw_bits_size), - .io_axi_w_ready(axi4_to_ahb_2_io_axi_w_ready), - .io_axi_w_valid(axi4_to_ahb_2_io_axi_w_valid), - .io_axi_w_bits_data(axi4_to_ahb_2_io_axi_w_bits_data), - .io_axi_w_bits_strb(axi4_to_ahb_2_io_axi_w_bits_strb), - .io_axi_b_valid(axi4_to_ahb_2_io_axi_b_valid), - .io_axi_b_bits_resp(axi4_to_ahb_2_io_axi_b_bits_resp), - .io_axi_b_bits_id(axi4_to_ahb_2_io_axi_b_bits_id), - .io_axi_ar_ready(axi4_to_ahb_2_io_axi_ar_ready), - .io_axi_ar_valid(axi4_to_ahb_2_io_axi_ar_valid), - .io_axi_ar_bits_id(axi4_to_ahb_2_io_axi_ar_bits_id), - .io_axi_ar_bits_addr(axi4_to_ahb_2_io_axi_ar_bits_addr), - .io_axi_ar_bits_size(axi4_to_ahb_2_io_axi_ar_bits_size), - .io_axi_r_valid(axi4_to_ahb_2_io_axi_r_valid), - .io_axi_r_bits_id(axi4_to_ahb_2_io_axi_r_bits_id), - .io_axi_r_bits_data(axi4_to_ahb_2_io_axi_r_bits_data), - .io_axi_r_bits_resp(axi4_to_ahb_2_io_axi_r_bits_resp), - .io_ahb_in_hrdata(axi4_to_ahb_2_io_ahb_in_hrdata), - .io_ahb_in_hready(axi4_to_ahb_2_io_ahb_in_hready), - .io_ahb_in_hresp(axi4_to_ahb_2_io_ahb_in_hresp), - .io_ahb_out_haddr(axi4_to_ahb_2_io_ahb_out_haddr), - .io_ahb_out_hsize(axi4_to_ahb_2_io_ahb_out_hsize), - .io_ahb_out_htrans(axi4_to_ahb_2_io_ahb_out_htrans), - .io_ahb_out_hwrite(axi4_to_ahb_2_io_ahb_out_hwrite), - .io_ahb_out_hwdata(axi4_to_ahb_2_io_ahb_out_hwdata) - ); - ahb_to_axi4 ahb_to_axi4 ( // @[quasar.scala 244:33] - .clock(ahb_to_axi4_clock), - .reset(ahb_to_axi4_reset), - .io_scan_mode(ahb_to_axi4_io_scan_mode), - .io_bus_clk_en(ahb_to_axi4_io_bus_clk_en), - .io_axi_aw_ready(ahb_to_axi4_io_axi_aw_ready), - .io_axi_aw_valid(ahb_to_axi4_io_axi_aw_valid), - .io_axi_aw_bits_addr(ahb_to_axi4_io_axi_aw_bits_addr), - .io_axi_aw_bits_size(ahb_to_axi4_io_axi_aw_bits_size), - .io_axi_w_valid(ahb_to_axi4_io_axi_w_valid), - .io_axi_w_bits_data(ahb_to_axi4_io_axi_w_bits_data), - .io_axi_w_bits_strb(ahb_to_axi4_io_axi_w_bits_strb), - .io_axi_ar_ready(ahb_to_axi4_io_axi_ar_ready), - .io_axi_ar_valid(ahb_to_axi4_io_axi_ar_valid), - .io_axi_ar_bits_addr(ahb_to_axi4_io_axi_ar_bits_addr), - .io_axi_ar_bits_size(ahb_to_axi4_io_axi_ar_bits_size), - .io_axi_r_valid(ahb_to_axi4_io_axi_r_valid), - .io_axi_r_bits_data(ahb_to_axi4_io_axi_r_bits_data), - .io_axi_r_bits_resp(ahb_to_axi4_io_axi_r_bits_resp), - .io_ahb_sig_in_hrdata(ahb_to_axi4_io_ahb_sig_in_hrdata), - .io_ahb_sig_in_hready(ahb_to_axi4_io_ahb_sig_in_hready), - .io_ahb_sig_in_hresp(ahb_to_axi4_io_ahb_sig_in_hresp), - .io_ahb_sig_out_haddr(ahb_to_axi4_io_ahb_sig_out_haddr), - .io_ahb_sig_out_hsize(ahb_to_axi4_io_ahb_sig_out_hsize), - .io_ahb_sig_out_htrans(ahb_to_axi4_io_ahb_sig_out_htrans), - .io_ahb_sig_out_hwrite(ahb_to_axi4_io_ahb_sig_out_hwrite), - .io_ahb_sig_out_hwdata(ahb_to_axi4_io_ahb_sig_out_hwdata), - .io_ahb_hsel(ahb_to_axi4_io_ahb_hsel), - .io_ahb_hreadyin(ahb_to_axi4_io_ahb_hreadyin) - ); - assign io_lsu_axi_aw_valid = 1'h0; // @[quasar.scala 274:21] - assign io_lsu_axi_aw_bits_id = 3'h0; // @[quasar.scala 274:21] - assign io_lsu_axi_aw_bits_addr = 32'h0; // @[quasar.scala 274:21] - assign io_lsu_axi_aw_bits_region = 4'h0; // @[quasar.scala 274:21] - assign io_lsu_axi_aw_bits_len = 8'h0; // @[quasar.scala 274:21] - assign io_lsu_axi_aw_bits_size = 3'h0; // @[quasar.scala 274:21] - assign io_lsu_axi_aw_bits_burst = 2'h0; // @[quasar.scala 274:21] - assign io_lsu_axi_aw_bits_lock = 1'h0; // @[quasar.scala 274:21] - assign io_lsu_axi_aw_bits_cache = 4'h0; // @[quasar.scala 274:21] - assign io_lsu_axi_aw_bits_prot = 3'h0; // @[quasar.scala 274:21] - assign io_lsu_axi_aw_bits_qos = 4'h0; // @[quasar.scala 274:21] - assign io_lsu_axi_w_valid = 1'h0; // @[quasar.scala 274:21] - assign io_lsu_axi_w_bits_data = 64'h0; // @[quasar.scala 274:21] - assign io_lsu_axi_w_bits_strb = 8'h0; // @[quasar.scala 274:21] - assign io_lsu_axi_w_bits_last = 1'h0; // @[quasar.scala 274:21] - assign io_lsu_axi_b_ready = 1'h0; // @[quasar.scala 274:21] - assign io_lsu_axi_ar_valid = 1'h0; // @[quasar.scala 274:21] - assign io_lsu_axi_ar_bits_id = 3'h0; // @[quasar.scala 274:21] - assign io_lsu_axi_ar_bits_addr = 32'h0; // @[quasar.scala 274:21] - assign io_lsu_axi_ar_bits_region = 4'h0; // @[quasar.scala 274:21] - assign io_lsu_axi_ar_bits_len = 8'h0; // @[quasar.scala 274:21] - assign io_lsu_axi_ar_bits_size = 3'h0; // @[quasar.scala 274:21] - assign io_lsu_axi_ar_bits_burst = 2'h0; // @[quasar.scala 274:21] - assign io_lsu_axi_ar_bits_lock = 1'h0; // @[quasar.scala 274:21] - assign io_lsu_axi_ar_bits_cache = 4'h0; // @[quasar.scala 274:21] - assign io_lsu_axi_ar_bits_prot = 3'h0; // @[quasar.scala 274:21] - assign io_lsu_axi_ar_bits_qos = 4'h0; // @[quasar.scala 274:21] - assign io_lsu_axi_r_ready = 1'h0; // @[quasar.scala 274:21] - assign io_ifu_axi_aw_valid = 1'h0; // @[quasar.scala 273:21] - assign io_ifu_axi_aw_bits_id = 3'h0; // @[quasar.scala 273:21] - assign io_ifu_axi_aw_bits_addr = 32'h0; // @[quasar.scala 273:21] - assign io_ifu_axi_aw_bits_region = 4'h0; // @[quasar.scala 273:21] - assign io_ifu_axi_aw_bits_len = 8'h0; // @[quasar.scala 273:21] - assign io_ifu_axi_aw_bits_size = 3'h0; // @[quasar.scala 273:21] - assign io_ifu_axi_aw_bits_burst = 2'h0; // @[quasar.scala 273:21] - assign io_ifu_axi_aw_bits_lock = 1'h0; // @[quasar.scala 273:21] - assign io_ifu_axi_aw_bits_cache = 4'h0; // @[quasar.scala 273:21] - assign io_ifu_axi_aw_bits_prot = 3'h0; // @[quasar.scala 273:21] - assign io_ifu_axi_aw_bits_qos = 4'h0; // @[quasar.scala 273:21] - assign io_ifu_axi_w_valid = 1'h0; // @[quasar.scala 273:21] - assign io_ifu_axi_w_bits_data = 64'h0; // @[quasar.scala 273:21] - assign io_ifu_axi_w_bits_strb = 8'h0; // @[quasar.scala 273:21] - assign io_ifu_axi_w_bits_last = 1'h0; // @[quasar.scala 273:21] - assign io_ifu_axi_b_ready = 1'h0; // @[quasar.scala 273:21] - assign io_ifu_axi_ar_valid = 1'h0; // @[quasar.scala 273:21] - assign io_ifu_axi_ar_bits_id = 3'h0; // @[quasar.scala 273:21] - assign io_ifu_axi_ar_bits_addr = 32'h0; // @[quasar.scala 273:21] - assign io_ifu_axi_ar_bits_region = 4'h0; // @[quasar.scala 273:21] - assign io_ifu_axi_ar_bits_len = 8'h0; // @[quasar.scala 273:21] - assign io_ifu_axi_ar_bits_size = 3'h0; // @[quasar.scala 273:21] - assign io_ifu_axi_ar_bits_burst = 2'h0; // @[quasar.scala 273:21] - assign io_ifu_axi_ar_bits_lock = 1'h0; // @[quasar.scala 273:21] - assign io_ifu_axi_ar_bits_cache = 4'h0; // @[quasar.scala 273:21] - assign io_ifu_axi_ar_bits_prot = 3'h0; // @[quasar.scala 273:21] - assign io_ifu_axi_ar_bits_qos = 4'h0; // @[quasar.scala 273:21] - assign io_ifu_axi_r_ready = 1'h0; // @[quasar.scala 273:21] - assign io_sb_axi_aw_valid = 1'h0; // @[quasar.scala 272:21] - assign io_sb_axi_aw_bits_id = 1'h0; // @[quasar.scala 272:21] - assign io_sb_axi_aw_bits_addr = 32'h0; // @[quasar.scala 272:21] - assign io_sb_axi_aw_bits_region = 4'h0; // @[quasar.scala 272:21] - assign io_sb_axi_aw_bits_len = 8'h0; // @[quasar.scala 272:21] - assign io_sb_axi_aw_bits_size = 3'h0; // @[quasar.scala 272:21] - assign io_sb_axi_aw_bits_burst = 2'h0; // @[quasar.scala 272:21] - assign io_sb_axi_aw_bits_lock = 1'h0; // @[quasar.scala 272:21] - assign io_sb_axi_aw_bits_cache = 4'h0; // @[quasar.scala 272:21] - assign io_sb_axi_aw_bits_prot = 3'h0; // @[quasar.scala 272:21] - assign io_sb_axi_aw_bits_qos = 4'h0; // @[quasar.scala 272:21] - assign io_sb_axi_w_valid = 1'h0; // @[quasar.scala 272:21] - assign io_sb_axi_w_bits_data = 64'h0; // @[quasar.scala 272:21] - assign io_sb_axi_w_bits_strb = 8'h0; // @[quasar.scala 272:21] - assign io_sb_axi_w_bits_last = 1'h0; // @[quasar.scala 272:21] - assign io_sb_axi_b_ready = 1'h0; // @[quasar.scala 272:21] - assign io_sb_axi_ar_valid = 1'h0; // @[quasar.scala 272:21] - assign io_sb_axi_ar_bits_id = 1'h0; // @[quasar.scala 272:21] - assign io_sb_axi_ar_bits_addr = 32'h0; // @[quasar.scala 272:21] - assign io_sb_axi_ar_bits_region = 4'h0; // @[quasar.scala 272:21] - assign io_sb_axi_ar_bits_len = 8'h0; // @[quasar.scala 272:21] - assign io_sb_axi_ar_bits_size = 3'h0; // @[quasar.scala 272:21] - assign io_sb_axi_ar_bits_burst = 2'h0; // @[quasar.scala 272:21] - assign io_sb_axi_ar_bits_lock = 1'h0; // @[quasar.scala 272:21] - assign io_sb_axi_ar_bits_cache = 4'h0; // @[quasar.scala 272:21] - assign io_sb_axi_ar_bits_prot = 3'h0; // @[quasar.scala 272:21] - assign io_sb_axi_ar_bits_qos = 4'h0; // @[quasar.scala 272:21] - assign io_sb_axi_r_ready = 1'h0; // @[quasar.scala 272:21] - assign io_dma_axi_aw_ready = 1'h0; // @[quasar.scala 271:21] - assign io_dma_axi_w_ready = 1'h0; // @[quasar.scala 271:21] - assign io_dma_axi_b_valid = 1'h0; // @[quasar.scala 271:21] - assign io_dma_axi_b_bits_resp = 2'h0; // @[quasar.scala 271:21] - assign io_dma_axi_b_bits_id = 1'h0; // @[quasar.scala 271:21] - assign io_dma_axi_ar_ready = 1'h0; // @[quasar.scala 271:21] - assign io_dma_axi_r_valid = 1'h0; // @[quasar.scala 271:21] - assign io_dma_axi_r_bits_id = 1'h0; // @[quasar.scala 271:21] - assign io_dma_axi_r_bits_data = 64'h0; // @[quasar.scala 271:21] - assign io_dma_axi_r_bits_resp = 2'h0; // @[quasar.scala 271:21] - assign io_dma_axi_r_bits_last = 1'h0; // @[quasar.scala 271:21] - assign io_lsu_ahb_out_haddr = axi4_to_ahb_2_io_ahb_out_haddr; // @[quasar.scala 250:28] - assign io_lsu_ahb_out_hburst = 3'h0; // @[quasar.scala 250:28] - assign io_lsu_ahb_out_hmastlock = 1'h0; // @[quasar.scala 250:28] - assign io_lsu_ahb_out_hprot = 4'h3; // @[quasar.scala 250:28] - assign io_lsu_ahb_out_hsize = axi4_to_ahb_2_io_ahb_out_hsize; // @[quasar.scala 250:28] - assign io_lsu_ahb_out_htrans = axi4_to_ahb_2_io_ahb_out_htrans; // @[quasar.scala 250:28] - assign io_lsu_ahb_out_hwrite = axi4_to_ahb_2_io_ahb_out_hwrite; // @[quasar.scala 250:28] - assign io_lsu_ahb_out_hwdata = axi4_to_ahb_2_io_ahb_out_hwdata; // @[quasar.scala 250:28] - assign io_ifu_ahb_out_haddr = axi4_to_ahb_1_io_ahb_out_haddr; // @[quasar.scala 256:28] - assign io_ifu_ahb_out_hburst = 3'h0; // @[quasar.scala 256:28] - assign io_ifu_ahb_out_hmastlock = 1'h0; // @[quasar.scala 256:28] - assign io_ifu_ahb_out_hprot = 4'h3; // @[quasar.scala 256:28] - assign io_ifu_ahb_out_hsize = axi4_to_ahb_1_io_ahb_out_hsize; // @[quasar.scala 256:28] - assign io_ifu_ahb_out_htrans = axi4_to_ahb_1_io_ahb_out_htrans; // @[quasar.scala 256:28] - assign io_ifu_ahb_out_hwrite = axi4_to_ahb_1_io_ahb_out_hwrite; // @[quasar.scala 256:28] - assign io_ifu_ahb_out_hwdata = axi4_to_ahb_1_io_ahb_out_hwdata; // @[quasar.scala 256:28] - assign io_sb_ahb_out_haddr = axi4_to_ahb_io_ahb_out_haddr; // @[quasar.scala 263:27] - assign io_sb_ahb_out_hburst = 3'h0; // @[quasar.scala 263:27] - assign io_sb_ahb_out_hmastlock = 1'h0; // @[quasar.scala 263:27] - assign io_sb_ahb_out_hprot = 4'h3; // @[quasar.scala 263:27] - assign io_sb_ahb_out_hsize = axi4_to_ahb_io_ahb_out_hsize; // @[quasar.scala 263:27] - assign io_sb_ahb_out_htrans = axi4_to_ahb_io_ahb_out_htrans; // @[quasar.scala 263:27] - assign io_sb_ahb_out_hwrite = axi4_to_ahb_io_ahb_out_hwrite; // @[quasar.scala 263:27] - assign io_sb_ahb_out_hwdata = axi4_to_ahb_io_ahb_out_hwdata; // @[quasar.scala 263:27] - assign io_dma_ahb_sig_in_hrdata = ahb_to_axi4_io_ahb_sig_in_hrdata; // @[quasar.scala 269:28] - assign io_dma_ahb_sig_in_hready = ahb_to_axi4_io_ahb_sig_in_hready; // @[quasar.scala 269:28] - assign io_dma_ahb_sig_in_hresp = ahb_to_axi4_io_ahb_sig_in_hresp; // @[quasar.scala 269:28] + assign io_lsu_axi_aw_valid = lsu_io_axi_aw_valid; // @[quasar.scala 284:27] + assign io_lsu_axi_aw_bits_id = lsu_io_axi_aw_bits_id; // @[quasar.scala 284:27] + assign io_lsu_axi_aw_bits_addr = lsu_io_axi_aw_bits_addr; // @[quasar.scala 284:27] + assign io_lsu_axi_aw_bits_region = lsu_io_axi_aw_bits_region; // @[quasar.scala 284:27] + assign io_lsu_axi_aw_bits_len = 8'h0; // @[quasar.scala 284:27] + assign io_lsu_axi_aw_bits_size = lsu_io_axi_aw_bits_size; // @[quasar.scala 284:27] + assign io_lsu_axi_aw_bits_burst = 2'h1; // @[quasar.scala 284:27] + assign io_lsu_axi_aw_bits_lock = 1'h0; // @[quasar.scala 284:27] + assign io_lsu_axi_aw_bits_cache = lsu_io_axi_aw_bits_cache; // @[quasar.scala 284:27] + assign io_lsu_axi_aw_bits_prot = 3'h0; // @[quasar.scala 284:27] + assign io_lsu_axi_aw_bits_qos = 4'h0; // @[quasar.scala 284:27] + assign io_lsu_axi_w_valid = lsu_io_axi_w_valid; // @[quasar.scala 284:27] + assign io_lsu_axi_w_bits_data = lsu_io_axi_w_bits_data; // @[quasar.scala 284:27] + assign io_lsu_axi_w_bits_strb = lsu_io_axi_w_bits_strb; // @[quasar.scala 284:27] + assign io_lsu_axi_w_bits_last = 1'h1; // @[quasar.scala 284:27] + assign io_lsu_axi_b_ready = 1'h1; // @[quasar.scala 284:27] + assign io_lsu_axi_ar_valid = lsu_io_axi_ar_valid; // @[quasar.scala 284:27] + assign io_lsu_axi_ar_bits_id = lsu_io_axi_ar_bits_id; // @[quasar.scala 284:27] + assign io_lsu_axi_ar_bits_addr = lsu_io_axi_ar_bits_addr; // @[quasar.scala 284:27] + assign io_lsu_axi_ar_bits_region = lsu_io_axi_ar_bits_region; // @[quasar.scala 284:27] + assign io_lsu_axi_ar_bits_len = 8'h0; // @[quasar.scala 284:27] + assign io_lsu_axi_ar_bits_size = lsu_io_axi_ar_bits_size; // @[quasar.scala 284:27] + assign io_lsu_axi_ar_bits_burst = 2'h1; // @[quasar.scala 284:27] + assign io_lsu_axi_ar_bits_lock = 1'h0; // @[quasar.scala 284:27] + assign io_lsu_axi_ar_bits_cache = lsu_io_axi_ar_bits_cache; // @[quasar.scala 284:27] + assign io_lsu_axi_ar_bits_prot = 3'h0; // @[quasar.scala 284:27] + assign io_lsu_axi_ar_bits_qos = 4'h0; // @[quasar.scala 284:27] + assign io_lsu_axi_r_ready = 1'h1; // @[quasar.scala 284:27] + assign io_ifu_axi_aw_valid = 1'h0; // @[quasar.scala 283:27] + assign io_ifu_axi_aw_bits_id = 3'h0; // @[quasar.scala 283:27] + assign io_ifu_axi_aw_bits_addr = 32'h0; // @[quasar.scala 283:27] + assign io_ifu_axi_aw_bits_region = 4'h0; // @[quasar.scala 283:27] + assign io_ifu_axi_aw_bits_len = 8'h0; // @[quasar.scala 283:27] + assign io_ifu_axi_aw_bits_size = 3'h0; // @[quasar.scala 283:27] + assign io_ifu_axi_aw_bits_burst = 2'h0; // @[quasar.scala 283:27] + assign io_ifu_axi_aw_bits_lock = 1'h0; // @[quasar.scala 283:27] + assign io_ifu_axi_aw_bits_cache = 4'h0; // @[quasar.scala 283:27] + assign io_ifu_axi_aw_bits_prot = 3'h0; // @[quasar.scala 283:27] + assign io_ifu_axi_aw_bits_qos = 4'h0; // @[quasar.scala 283:27] + assign io_ifu_axi_w_valid = 1'h0; // @[quasar.scala 283:27] + assign io_ifu_axi_w_bits_data = 64'h0; // @[quasar.scala 283:27] + assign io_ifu_axi_w_bits_strb = 8'h0; // @[quasar.scala 283:27] + assign io_ifu_axi_w_bits_last = 1'h0; // @[quasar.scala 283:27] + assign io_ifu_axi_b_ready = 1'h0; // @[quasar.scala 283:27] + assign io_ifu_axi_ar_valid = ifu_io_ifu_ar_valid; // @[quasar.scala 283:27] + assign io_ifu_axi_ar_bits_id = ifu_io_ifu_ar_bits_id; // @[quasar.scala 283:27] + assign io_ifu_axi_ar_bits_addr = ifu_io_ifu_ar_bits_addr; // @[quasar.scala 283:27] + assign io_ifu_axi_ar_bits_region = ifu_io_ifu_ar_bits_region; // @[quasar.scala 283:27] + assign io_ifu_axi_ar_bits_len = 8'h0; // @[quasar.scala 283:27] + assign io_ifu_axi_ar_bits_size = 3'h3; // @[quasar.scala 283:27] + assign io_ifu_axi_ar_bits_burst = 2'h1; // @[quasar.scala 283:27] + assign io_ifu_axi_ar_bits_lock = 1'h0; // @[quasar.scala 283:27] + assign io_ifu_axi_ar_bits_cache = 4'hf; // @[quasar.scala 283:27] + assign io_ifu_axi_ar_bits_prot = 3'h0; // @[quasar.scala 283:27] + assign io_ifu_axi_ar_bits_qos = 4'h0; // @[quasar.scala 283:27] + assign io_ifu_axi_r_ready = 1'h1; // @[quasar.scala 283:27] + assign io_sb_axi_aw_valid = dbg_io_sb_axi_aw_valid; // @[quasar.scala 282:27] + assign io_sb_axi_aw_bits_id = 1'h0; // @[quasar.scala 282:27] + assign io_sb_axi_aw_bits_addr = dbg_io_sb_axi_aw_bits_addr; // @[quasar.scala 282:27] + assign io_sb_axi_aw_bits_region = dbg_io_sb_axi_aw_bits_region; // @[quasar.scala 282:27] + assign io_sb_axi_aw_bits_len = 8'h0; // @[quasar.scala 282:27] + assign io_sb_axi_aw_bits_size = dbg_io_sb_axi_aw_bits_size; // @[quasar.scala 282:27] + assign io_sb_axi_aw_bits_burst = 2'h1; // @[quasar.scala 282:27] + assign io_sb_axi_aw_bits_lock = 1'h0; // @[quasar.scala 282:27] + assign io_sb_axi_aw_bits_cache = 4'hf; // @[quasar.scala 282:27] + assign io_sb_axi_aw_bits_prot = 3'h0; // @[quasar.scala 282:27] + assign io_sb_axi_aw_bits_qos = 4'h0; // @[quasar.scala 282:27] + assign io_sb_axi_w_valid = dbg_io_sb_axi_w_valid; // @[quasar.scala 282:27] + assign io_sb_axi_w_bits_data = dbg_io_sb_axi_w_bits_data; // @[quasar.scala 282:27] + assign io_sb_axi_w_bits_strb = dbg_io_sb_axi_w_bits_strb; // @[quasar.scala 282:27] + assign io_sb_axi_w_bits_last = 1'h1; // @[quasar.scala 282:27] + assign io_sb_axi_b_ready = 1'h1; // @[quasar.scala 282:27] + assign io_sb_axi_ar_valid = dbg_io_sb_axi_ar_valid; // @[quasar.scala 282:27] + assign io_sb_axi_ar_bits_id = 1'h0; // @[quasar.scala 282:27] + assign io_sb_axi_ar_bits_addr = dbg_io_sb_axi_ar_bits_addr; // @[quasar.scala 282:27] + assign io_sb_axi_ar_bits_region = dbg_io_sb_axi_ar_bits_region; // @[quasar.scala 282:27] + assign io_sb_axi_ar_bits_len = 8'h0; // @[quasar.scala 282:27] + assign io_sb_axi_ar_bits_size = dbg_io_sb_axi_ar_bits_size; // @[quasar.scala 282:27] + assign io_sb_axi_ar_bits_burst = 2'h1; // @[quasar.scala 282:27] + assign io_sb_axi_ar_bits_lock = 1'h0; // @[quasar.scala 282:27] + assign io_sb_axi_ar_bits_cache = 4'h0; // @[quasar.scala 282:27] + assign io_sb_axi_ar_bits_prot = 3'h0; // @[quasar.scala 282:27] + assign io_sb_axi_ar_bits_qos = 4'h0; // @[quasar.scala 282:27] + assign io_sb_axi_r_ready = 1'h1; // @[quasar.scala 282:27] + assign io_dma_axi_aw_ready = dma_ctrl_io_dma_axi_aw_ready; // @[quasar.scala 281:27] + assign io_dma_axi_w_ready = dma_ctrl_io_dma_axi_w_ready; // @[quasar.scala 281:27] + assign io_dma_axi_b_valid = dma_ctrl_io_dma_axi_b_valid; // @[quasar.scala 281:27] + assign io_dma_axi_b_bits_resp = dma_ctrl_io_dma_axi_b_bits_resp; // @[quasar.scala 281:27] + assign io_dma_axi_b_bits_id = dma_ctrl_io_dma_axi_b_bits_id; // @[quasar.scala 281:27] + assign io_dma_axi_ar_ready = dma_ctrl_io_dma_axi_ar_ready; // @[quasar.scala 281:27] + assign io_dma_axi_r_valid = dma_ctrl_io_dma_axi_r_valid; // @[quasar.scala 281:27] + assign io_dma_axi_r_bits_id = dma_ctrl_io_dma_axi_r_bits_id; // @[quasar.scala 281:27] + assign io_dma_axi_r_bits_data = dma_ctrl_io_dma_axi_r_bits_data; // @[quasar.scala 281:27] + assign io_dma_axi_r_bits_resp = dma_ctrl_io_dma_axi_r_bits_resp; // @[quasar.scala 281:27] + assign io_dma_axi_r_bits_last = 1'h1; // @[quasar.scala 281:27] + assign io_lsu_ahb_out_haddr = 32'h0; // @[quasar.scala 277:27] + assign io_lsu_ahb_out_hburst = 3'h0; // @[quasar.scala 277:27] + assign io_lsu_ahb_out_hmastlock = 1'h0; // @[quasar.scala 277:27] + assign io_lsu_ahb_out_hprot = 4'h0; // @[quasar.scala 277:27] + assign io_lsu_ahb_out_hsize = 3'h0; // @[quasar.scala 277:27] + assign io_lsu_ahb_out_htrans = 2'h0; // @[quasar.scala 277:27] + assign io_lsu_ahb_out_hwrite = 1'h0; // @[quasar.scala 277:27] + assign io_lsu_ahb_out_hwdata = 64'h0; // @[quasar.scala 277:27] + assign io_ifu_ahb_out_haddr = 32'h0; // @[quasar.scala 278:27] + assign io_ifu_ahb_out_hburst = 3'h0; // @[quasar.scala 278:27] + assign io_ifu_ahb_out_hmastlock = 1'h0; // @[quasar.scala 278:27] + assign io_ifu_ahb_out_hprot = 4'h0; // @[quasar.scala 278:27] + assign io_ifu_ahb_out_hsize = 3'h0; // @[quasar.scala 278:27] + assign io_ifu_ahb_out_htrans = 2'h0; // @[quasar.scala 278:27] + assign io_ifu_ahb_out_hwrite = 1'h0; // @[quasar.scala 278:27] + assign io_ifu_ahb_out_hwdata = 64'h0; // @[quasar.scala 278:27] + assign io_sb_ahb_out_haddr = 32'h0; // @[quasar.scala 279:27] + assign io_sb_ahb_out_hburst = 3'h0; // @[quasar.scala 279:27] + assign io_sb_ahb_out_hmastlock = 1'h0; // @[quasar.scala 279:27] + assign io_sb_ahb_out_hprot = 4'h0; // @[quasar.scala 279:27] + assign io_sb_ahb_out_hsize = 3'h0; // @[quasar.scala 279:27] + assign io_sb_ahb_out_htrans = 2'h0; // @[quasar.scala 279:27] + assign io_sb_ahb_out_hwrite = 1'h0; // @[quasar.scala 279:27] + assign io_sb_ahb_out_hwdata = 64'h0; // @[quasar.scala 279:27] + assign io_dma_ahb_sig_in_hrdata = 64'h0; // @[quasar.scala 280:27] + assign io_dma_ahb_sig_in_hready = 1'h0; // @[quasar.scala 280:27] + assign io_dma_ahb_sig_in_hresp = 1'h0; // @[quasar.scala 280:27] assign io_core_rst_l = reset & _T_2; // @[quasar.scala 82:17] assign io_rv_trace_pkt_rv_i_valid_ip = dec_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar.scala 218:19] assign io_rv_trace_pkt_rv_i_insn_ip = dec_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar.scala 218:19] @@ -85232,11 +82688,11 @@ module quasar( assign ifu_io_ic_eccerr = io_ic_eccerr; // @[quasar.scala 100:13] assign ifu_io_ic_rd_hit = io_ic_rd_hit; // @[quasar.scala 100:13] assign ifu_io_ic_tag_perr = io_ic_tag_perr; // @[quasar.scala 100:13] - assign ifu_io_ifu_ar_ready = axi4_to_ahb_1_io_axi_ar_ready; // @[quasar.scala 255:28] - assign ifu_io_ifu_r_valid = axi4_to_ahb_1_io_axi_r_valid; // @[quasar.scala 255:28] - assign ifu_io_ifu_r_bits_id = axi4_to_ahb_1_io_axi_r_bits_id; // @[quasar.scala 255:28] - assign ifu_io_ifu_r_bits_data = axi4_to_ahb_1_io_axi_r_bits_data; // @[quasar.scala 255:28] - assign ifu_io_ifu_r_bits_resp = axi4_to_ahb_1_io_axi_r_bits_resp; // @[quasar.scala 255:28] + assign ifu_io_ifu_ar_ready = io_ifu_axi_ar_ready; // @[quasar.scala 283:27] + assign ifu_io_ifu_r_valid = io_ifu_axi_r_valid; // @[quasar.scala 283:27] + assign ifu_io_ifu_r_bits_id = io_ifu_axi_r_bits_id; // @[quasar.scala 283:27] + assign ifu_io_ifu_r_bits_data = io_ifu_axi_r_bits_data; // @[quasar.scala 283:27] + assign ifu_io_ifu_r_bits_resp = io_ifu_axi_r_bits_resp; // @[quasar.scala 283:27] assign ifu_io_ifu_bus_clk_en = io_ifu_bus_clk_en; // @[quasar.scala 98:25] assign ifu_io_ifu_dma_dma_ifc_dma_iccm_stall_any = dma_ctrl_io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[quasar.scala 99:18] assign ifu_io_ifu_dma_dma_mem_ctl_dma_iccm_req = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[quasar.scala 99:18] @@ -85378,14 +82834,14 @@ module quasar( assign dbg_io_dmi_reg_addr = io_dmi_reg_addr; // @[quasar.scala 184:23] assign dbg_io_dmi_reg_wr_en = io_dmi_reg_wr_en; // @[quasar.scala 185:24] assign dbg_io_dmi_reg_wdata = io_dmi_reg_wdata; // @[quasar.scala 186:24] - assign dbg_io_sb_axi_aw_ready = axi4_to_ahb_io_axi_aw_ready; // @[quasar.scala 262:27] - assign dbg_io_sb_axi_w_ready = axi4_to_ahb_io_axi_w_ready; // @[quasar.scala 262:27] - assign dbg_io_sb_axi_b_valid = axi4_to_ahb_io_axi_b_valid; // @[quasar.scala 262:27] - assign dbg_io_sb_axi_b_bits_resp = axi4_to_ahb_io_axi_b_bits_resp; // @[quasar.scala 262:27] - assign dbg_io_sb_axi_ar_ready = axi4_to_ahb_io_axi_ar_ready; // @[quasar.scala 262:27] - assign dbg_io_sb_axi_r_valid = axi4_to_ahb_io_axi_r_valid; // @[quasar.scala 262:27] - assign dbg_io_sb_axi_r_bits_data = axi4_to_ahb_io_axi_r_bits_data; // @[quasar.scala 262:27] - assign dbg_io_sb_axi_r_bits_resp = axi4_to_ahb_io_axi_r_bits_resp; // @[quasar.scala 262:27] + assign dbg_io_sb_axi_aw_ready = io_sb_axi_aw_ready; // @[quasar.scala 282:27] + assign dbg_io_sb_axi_w_ready = io_sb_axi_w_ready; // @[quasar.scala 282:27] + assign dbg_io_sb_axi_b_valid = io_sb_axi_b_valid; // @[quasar.scala 282:27] + assign dbg_io_sb_axi_b_bits_resp = io_sb_axi_b_bits_resp; // @[quasar.scala 282:27] + assign dbg_io_sb_axi_ar_ready = io_sb_axi_ar_ready; // @[quasar.scala 282:27] + assign dbg_io_sb_axi_r_valid = io_sb_axi_r_valid; // @[quasar.scala 282:27] + assign dbg_io_sb_axi_r_bits_data = io_sb_axi_r_bits_data; // @[quasar.scala 282:27] + assign dbg_io_sb_axi_r_bits_resp = io_sb_axi_r_bits_resp; // @[quasar.scala 282:27] assign dbg_io_dbg_dma_io_dma_dbg_ready = dma_ctrl_io_dbg_dma_io_dma_dbg_ready; // @[quasar.scala 200:26] assign dbg_io_dbg_bus_clk_en = io_dbg_bus_clk_en; // @[quasar.scala 187:25] assign dbg_io_dbg_rst_l = io_dbg_rst_l; // @[quasar.scala 188:20] @@ -85473,19 +82929,20 @@ module quasar( assign lsu_io_lsu_exu_exu_lsu_rs1_d = exu_io_lsu_exu_exu_lsu_rs1_d; // @[quasar.scala 163:18] assign lsu_io_lsu_exu_exu_lsu_rs2_d = exu_io_lsu_exu_exu_lsu_rs2_d; // @[quasar.scala 163:18] assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 122:18] + assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[quasar.scala 122:18] assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 122:18] assign lsu_io_dccm_rd_data_lo = io_dccm_rd_data_lo; // @[quasar.scala 238:11] assign lsu_io_dccm_rd_data_hi = io_dccm_rd_data_hi; // @[quasar.scala 238:11] - assign lsu_io_axi_aw_ready = axi4_to_ahb_2_io_axi_aw_ready; // @[quasar.scala 249:28] - assign lsu_io_axi_w_ready = axi4_to_ahb_2_io_axi_w_ready; // @[quasar.scala 249:28] - assign lsu_io_axi_b_valid = axi4_to_ahb_2_io_axi_b_valid; // @[quasar.scala 249:28] - assign lsu_io_axi_b_bits_resp = axi4_to_ahb_2_io_axi_b_bits_resp; // @[quasar.scala 249:28] - assign lsu_io_axi_b_bits_id = axi4_to_ahb_2_io_axi_b_bits_id; // @[quasar.scala 249:28] - assign lsu_io_axi_ar_ready = axi4_to_ahb_2_io_axi_ar_ready; // @[quasar.scala 249:28] - assign lsu_io_axi_r_valid = axi4_to_ahb_2_io_axi_r_valid; // @[quasar.scala 249:28] - assign lsu_io_axi_r_bits_id = axi4_to_ahb_2_io_axi_r_bits_id; // @[quasar.scala 249:28] - assign lsu_io_axi_r_bits_data = axi4_to_ahb_2_io_axi_r_bits_data; // @[quasar.scala 249:28] - assign lsu_io_axi_r_bits_resp = axi4_to_ahb_2_io_axi_r_bits_resp; // @[quasar.scala 249:28] + assign lsu_io_axi_aw_ready = io_lsu_axi_aw_ready; // @[quasar.scala 284:27] + assign lsu_io_axi_w_ready = io_lsu_axi_w_ready; // @[quasar.scala 284:27] + assign lsu_io_axi_b_valid = io_lsu_axi_b_valid; // @[quasar.scala 284:27] + assign lsu_io_axi_b_bits_resp = io_lsu_axi_b_bits_resp; // @[quasar.scala 284:27] + assign lsu_io_axi_b_bits_id = io_lsu_axi_b_bits_id; // @[quasar.scala 284:27] + assign lsu_io_axi_ar_ready = io_lsu_axi_ar_ready; // @[quasar.scala 284:27] + assign lsu_io_axi_r_valid = io_lsu_axi_r_valid; // @[quasar.scala 284:27] + assign lsu_io_axi_r_bits_id = io_lsu_axi_r_bits_id; // @[quasar.scala 284:27] + assign lsu_io_axi_r_bits_data = io_lsu_axi_r_bits_data; // @[quasar.scala 284:27] + assign lsu_io_axi_r_bits_resp = io_lsu_axi_r_bits_resp; // @[quasar.scala 284:27] assign lsu_io_dec_tlu_flush_lower_r = dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 159:32] assign lsu_io_dec_tlu_i0_kill_writeb_r = dec_io_dec_tlu_i0_kill_writeb_r; // @[quasar.scala 160:35] assign lsu_io_dec_tlu_force_halt = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 161:29] @@ -85560,15 +83017,19 @@ module quasar( assign dma_ctrl_io_iccm_dma_rtag = ifu_io_iccm_dma_rtag; // @[quasar.scala 203:29] assign dma_ctrl_io_iccm_dma_rdata = ifu_io_iccm_dma_rdata; // @[quasar.scala 204:30] assign dma_ctrl_io_iccm_ready = ifu_io_iccm_ready; // @[quasar.scala 205:26] - assign dma_ctrl_io_dma_axi_aw_valid = ahb_to_axi4_io_axi_aw_valid; // @[quasar.scala 268:28] - assign dma_ctrl_io_dma_axi_aw_bits_addr = ahb_to_axi4_io_axi_aw_bits_addr; // @[quasar.scala 268:28] - assign dma_ctrl_io_dma_axi_aw_bits_size = ahb_to_axi4_io_axi_aw_bits_size; // @[quasar.scala 268:28] - assign dma_ctrl_io_dma_axi_w_valid = ahb_to_axi4_io_axi_w_valid; // @[quasar.scala 268:28] - assign dma_ctrl_io_dma_axi_w_bits_data = ahb_to_axi4_io_axi_w_bits_data; // @[quasar.scala 268:28] - assign dma_ctrl_io_dma_axi_w_bits_strb = ahb_to_axi4_io_axi_w_bits_strb; // @[quasar.scala 268:28] - assign dma_ctrl_io_dma_axi_ar_valid = ahb_to_axi4_io_axi_ar_valid; // @[quasar.scala 268:28] - assign dma_ctrl_io_dma_axi_ar_bits_addr = ahb_to_axi4_io_axi_ar_bits_addr; // @[quasar.scala 268:28] - assign dma_ctrl_io_dma_axi_ar_bits_size = ahb_to_axi4_io_axi_ar_bits_size; // @[quasar.scala 268:28] + assign dma_ctrl_io_dma_axi_aw_valid = io_dma_axi_aw_valid; // @[quasar.scala 281:27] + assign dma_ctrl_io_dma_axi_aw_bits_id = io_dma_axi_aw_bits_id; // @[quasar.scala 281:27] + assign dma_ctrl_io_dma_axi_aw_bits_addr = io_dma_axi_aw_bits_addr; // @[quasar.scala 281:27] + assign dma_ctrl_io_dma_axi_aw_bits_size = io_dma_axi_aw_bits_size; // @[quasar.scala 281:27] + assign dma_ctrl_io_dma_axi_w_valid = io_dma_axi_w_valid; // @[quasar.scala 281:27] + assign dma_ctrl_io_dma_axi_w_bits_data = io_dma_axi_w_bits_data; // @[quasar.scala 281:27] + assign dma_ctrl_io_dma_axi_w_bits_strb = io_dma_axi_w_bits_strb; // @[quasar.scala 281:27] + assign dma_ctrl_io_dma_axi_b_ready = io_dma_axi_b_ready; // @[quasar.scala 281:27] + assign dma_ctrl_io_dma_axi_ar_valid = io_dma_axi_ar_valid; // @[quasar.scala 281:27] + assign dma_ctrl_io_dma_axi_ar_bits_id = io_dma_axi_ar_bits_id; // @[quasar.scala 281:27] + assign dma_ctrl_io_dma_axi_ar_bits_addr = io_dma_axi_ar_bits_addr; // @[quasar.scala 281:27] + assign dma_ctrl_io_dma_axi_ar_bits_size = io_dma_axi_ar_bits_size; // @[quasar.scala 281:27] + assign dma_ctrl_io_dma_axi_r_ready = io_dma_axi_r_ready; // @[quasar.scala 281:27] assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid; // @[quasar.scala 171:18] assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error; // @[quasar.scala 171:18] assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[quasar.scala 171:18] @@ -85580,75 +83041,4 @@ module quasar( assign rvclkhdr_1_io_clk = clock; // @[lib.scala 344:17] assign rvclkhdr_1_io_en = _T_6 | dec_io_dec_tlu_misc_clk_override; // @[lib.scala 345:16] assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign axi4_to_ahb_clock = clock; - assign axi4_to_ahb_reset = reset; - assign axi4_to_ahb_io_scan_mode = io_scan_mode; // @[quasar.scala 259:33] - assign axi4_to_ahb_io_bus_clk_en = io_dbg_bus_clk_en; // @[quasar.scala 260:34] - assign axi4_to_ahb_io_clk_override = dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 261:36] - assign axi4_to_ahb_io_axi_aw_valid = dbg_io_sb_axi_aw_valid; // @[quasar.scala 262:27] - assign axi4_to_ahb_io_axi_aw_bits_addr = dbg_io_sb_axi_aw_bits_addr; // @[quasar.scala 262:27] - assign axi4_to_ahb_io_axi_aw_bits_size = dbg_io_sb_axi_aw_bits_size; // @[quasar.scala 262:27] - assign axi4_to_ahb_io_axi_w_valid = dbg_io_sb_axi_w_valid; // @[quasar.scala 262:27] - assign axi4_to_ahb_io_axi_w_bits_data = dbg_io_sb_axi_w_bits_data; // @[quasar.scala 262:27] - assign axi4_to_ahb_io_axi_w_bits_strb = dbg_io_sb_axi_w_bits_strb; // @[quasar.scala 262:27] - assign axi4_to_ahb_io_axi_ar_valid = dbg_io_sb_axi_ar_valid; // @[quasar.scala 262:27] - assign axi4_to_ahb_io_axi_ar_bits_addr = dbg_io_sb_axi_ar_bits_addr; // @[quasar.scala 262:27] - assign axi4_to_ahb_io_axi_ar_bits_size = dbg_io_sb_axi_ar_bits_size; // @[quasar.scala 262:27] - assign axi4_to_ahb_io_ahb_in_hrdata = io_sb_ahb_in_hrdata; // @[quasar.scala 263:27] - assign axi4_to_ahb_io_ahb_in_hready = io_sb_ahb_in_hready; // @[quasar.scala 263:27] - assign axi4_to_ahb_io_ahb_in_hresp = io_sb_ahb_in_hresp; // @[quasar.scala 263:27] - assign axi4_to_ahb_1_clock = clock; - assign axi4_to_ahb_1_reset = reset; - assign axi4_to_ahb_1_io_scan_mode = io_scan_mode; // @[quasar.scala 252:34] - assign axi4_to_ahb_1_io_bus_clk_en = io_ifu_bus_clk_en; // @[quasar.scala 253:35] - assign axi4_to_ahb_1_io_clk_override = dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 254:37] - assign axi4_to_ahb_1_io_axi_aw_valid = 1'h0; // @[quasar.scala 255:28] - assign axi4_to_ahb_1_io_axi_aw_bits_id = 3'h0; // @[quasar.scala 255:28] - assign axi4_to_ahb_1_io_axi_aw_bits_addr = 32'h0; // @[quasar.scala 255:28] - assign axi4_to_ahb_1_io_axi_aw_bits_size = 3'h0; // @[quasar.scala 255:28] - assign axi4_to_ahb_1_io_axi_w_valid = 1'h0; // @[quasar.scala 255:28] - assign axi4_to_ahb_1_io_axi_w_bits_data = 64'h0; // @[quasar.scala 255:28] - assign axi4_to_ahb_1_io_axi_w_bits_strb = 8'h0; // @[quasar.scala 255:28] - assign axi4_to_ahb_1_io_axi_ar_valid = ifu_io_ifu_ar_valid; // @[quasar.scala 255:28] - assign axi4_to_ahb_1_io_axi_ar_bits_id = ifu_io_ifu_ar_bits_id; // @[quasar.scala 255:28] - assign axi4_to_ahb_1_io_axi_ar_bits_addr = ifu_io_ifu_ar_bits_addr; // @[quasar.scala 255:28] - assign axi4_to_ahb_1_io_axi_ar_bits_size = 3'h3; // @[quasar.scala 255:28] - assign axi4_to_ahb_1_io_ahb_in_hrdata = io_ifu_ahb_in_hrdata; // @[quasar.scala 256:28] - assign axi4_to_ahb_1_io_ahb_in_hready = io_ifu_ahb_in_hready; // @[quasar.scala 256:28] - assign axi4_to_ahb_1_io_ahb_in_hresp = io_ifu_ahb_in_hresp; // @[quasar.scala 256:28] - assign axi4_to_ahb_2_clock = clock; - assign axi4_to_ahb_2_reset = reset; - assign axi4_to_ahb_2_io_scan_mode = io_scan_mode; // @[quasar.scala 246:34] - assign axi4_to_ahb_2_io_bus_clk_en = io_lsu_bus_clk_en; // @[quasar.scala 247:35] - assign axi4_to_ahb_2_io_clk_override = dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 248:37] - assign axi4_to_ahb_2_io_axi_aw_valid = lsu_io_axi_aw_valid; // @[quasar.scala 249:28] - assign axi4_to_ahb_2_io_axi_aw_bits_id = lsu_io_axi_aw_bits_id; // @[quasar.scala 249:28] - assign axi4_to_ahb_2_io_axi_aw_bits_addr = lsu_io_axi_aw_bits_addr; // @[quasar.scala 249:28] - assign axi4_to_ahb_2_io_axi_aw_bits_size = lsu_io_axi_aw_bits_size; // @[quasar.scala 249:28] - assign axi4_to_ahb_2_io_axi_w_valid = lsu_io_axi_w_valid; // @[quasar.scala 249:28] - assign axi4_to_ahb_2_io_axi_w_bits_data = lsu_io_axi_w_bits_data; // @[quasar.scala 249:28] - assign axi4_to_ahb_2_io_axi_w_bits_strb = lsu_io_axi_w_bits_strb; // @[quasar.scala 249:28] - assign axi4_to_ahb_2_io_axi_ar_valid = lsu_io_axi_ar_valid; // @[quasar.scala 249:28] - assign axi4_to_ahb_2_io_axi_ar_bits_id = lsu_io_axi_ar_bits_id; // @[quasar.scala 249:28] - assign axi4_to_ahb_2_io_axi_ar_bits_addr = lsu_io_axi_ar_bits_addr; // @[quasar.scala 249:28] - assign axi4_to_ahb_2_io_axi_ar_bits_size = lsu_io_axi_ar_bits_size; // @[quasar.scala 249:28] - assign axi4_to_ahb_2_io_ahb_in_hrdata = io_lsu_ahb_in_hrdata; // @[quasar.scala 250:28] - assign axi4_to_ahb_2_io_ahb_in_hready = io_lsu_ahb_in_hready; // @[quasar.scala 250:28] - assign axi4_to_ahb_2_io_ahb_in_hresp = io_lsu_ahb_in_hresp; // @[quasar.scala 250:28] - assign ahb_to_axi4_clock = clock; - assign ahb_to_axi4_reset = reset; - assign ahb_to_axi4_io_scan_mode = io_scan_mode; // @[quasar.scala 265:34] - assign ahb_to_axi4_io_bus_clk_en = io_dma_bus_clk_en; // @[quasar.scala 266:35] - assign ahb_to_axi4_io_axi_aw_ready = dma_ctrl_io_dma_axi_aw_ready; // @[quasar.scala 268:28] - assign ahb_to_axi4_io_axi_ar_ready = dma_ctrl_io_dma_axi_ar_ready; // @[quasar.scala 268:28] - assign ahb_to_axi4_io_axi_r_valid = dma_ctrl_io_dma_axi_r_valid; // @[quasar.scala 268:28] - assign ahb_to_axi4_io_axi_r_bits_data = dma_ctrl_io_dma_axi_r_bits_data; // @[quasar.scala 268:28] - assign ahb_to_axi4_io_axi_r_bits_resp = dma_ctrl_io_dma_axi_r_bits_resp; // @[quasar.scala 268:28] - assign ahb_to_axi4_io_ahb_sig_out_haddr = io_dma_ahb_sig_out_haddr; // @[quasar.scala 269:28] - assign ahb_to_axi4_io_ahb_sig_out_hsize = io_dma_ahb_sig_out_hsize; // @[quasar.scala 269:28] - assign ahb_to_axi4_io_ahb_sig_out_htrans = io_dma_ahb_sig_out_htrans; // @[quasar.scala 269:28] - assign ahb_to_axi4_io_ahb_sig_out_hwrite = io_dma_ahb_sig_out_hwrite; // @[quasar.scala 269:28] - assign ahb_to_axi4_io_ahb_sig_out_hwdata = io_dma_ahb_sig_out_hwdata; // @[quasar.scala 269:28] - assign ahb_to_axi4_io_ahb_hsel = io_dma_ahb_hsel; // @[quasar.scala 269:28] - assign ahb_to_axi4_io_ahb_hreadyin = io_dma_ahb_hreadyin; // @[quasar.scala 269:28] endmodule diff --git a/quasar_wrapper.anno.json b/quasar_wrapper.anno.json index a35ecff7..a2c2bd61 100644 --- a/quasar_wrapper.anno.json +++ b/quasar_wrapper.anno.json @@ -982,7 +982,7 @@ }, { "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~quasar_wrapper|csr_tlu>_T_745" + "target":"~quasar_wrapper|csr_tlu>_T_755" }, { "class":"firrtl.transforms.BlackBoxResourceAnno", diff --git a/quasar_wrapper.fir b/quasar_wrapper.fir index 1d4125bd..271dd879 100644 --- a/quasar_wrapper.fir +++ b/quasar_wrapper.fir @@ -73424,972 +73424,982 @@ circuit quasar_wrapper : reg _T_339 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_339 <= mfdc_ns @[lib.scala 374:16] mfdc_int <= _T_339 @[dec_tlu_ctl.scala 1728:11] - node _T_340 = bits(io.dec_csr_wrdata_r, 18, 16) @[dec_tlu_ctl.scala 1737:39] - node _T_341 = not(_T_340) @[dec_tlu_ctl.scala 1737:19] - node _T_342 = bits(io.dec_csr_wrdata_r, 11, 0) @[dec_tlu_ctl.scala 1737:66] - node _T_343 = cat(_T_341, _T_342) @[Cat.scala 29:58] - mfdc_ns <= _T_343 @[dec_tlu_ctl.scala 1737:12] - node _T_344 = bits(mfdc_int, 14, 12) @[dec_tlu_ctl.scala 1738:28] - node _T_345 = not(_T_344) @[dec_tlu_ctl.scala 1738:19] - node _T_346 = bits(mfdc_int, 11, 0) @[dec_tlu_ctl.scala 1738:54] - node _T_347 = cat(_T_345, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_340 = bits(io.dec_csr_wrdata_r, 18, 16) @[dec_tlu_ctl.scala 1733:40] + node _T_341 = not(_T_340) @[dec_tlu_ctl.scala 1733:20] + node _T_342 = bits(io.dec_csr_wrdata_r, 11, 7) @[dec_tlu_ctl.scala 1733:67] + node _T_343 = bits(io.dec_csr_wrdata_r, 6, 6) @[dec_tlu_ctl.scala 1733:95] + node _T_344 = not(_T_343) @[dec_tlu_ctl.scala 1733:75] + node _T_345 = bits(io.dec_csr_wrdata_r, 5, 0) @[dec_tlu_ctl.scala 1733:119] + node _T_346 = cat(_T_344, _T_345) @[Cat.scala 29:58] + node _T_347 = cat(_T_341, _T_342) @[Cat.scala 29:58] node _T_348 = cat(_T_347, _T_346) @[Cat.scala 29:58] - mfdc <= _T_348 @[dec_tlu_ctl.scala 1738:12] - node _T_349 = bits(mfdc, 18, 16) @[dec_tlu_ctl.scala 1742:46] - io.dec_tlu_dma_qos_prty <= _T_349 @[dec_tlu_ctl.scala 1742:39] - node _T_350 = bits(mfdc, 11, 11) @[dec_tlu_ctl.scala 1743:46] - io.dec_tlu_external_ldfwd_disable <= _T_350 @[dec_tlu_ctl.scala 1743:39] - node _T_351 = bits(mfdc, 8, 8) @[dec_tlu_ctl.scala 1744:46] - io.dec_tlu_core_ecc_disable <= _T_351 @[dec_tlu_ctl.scala 1744:39] - node _T_352 = bits(mfdc, 6, 6) @[dec_tlu_ctl.scala 1745:46] - io.dec_tlu_sideeffect_posted_disable <= _T_352 @[dec_tlu_ctl.scala 1745:39] - node _T_353 = bits(mfdc, 3, 3) @[dec_tlu_ctl.scala 1746:46] - io.dec_tlu_bpred_disable <= _T_353 @[dec_tlu_ctl.scala 1746:39] - node _T_354 = bits(mfdc, 2, 2) @[dec_tlu_ctl.scala 1747:46] - io.dec_tlu_wb_coalescing_disable <= _T_354 @[dec_tlu_ctl.scala 1747:39] - node _T_355 = bits(mfdc, 0, 0) @[dec_tlu_ctl.scala 1748:46] - io.dec_tlu_pipelining_disable <= _T_355 @[dec_tlu_ctl.scala 1748:39] - node _T_356 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1757:70] - node _T_357 = eq(_T_356, UInt<12>("h07c2")) @[dec_tlu_ctl.scala 1757:77] - node _T_358 = and(io.dec_csr_wen_r_mod, _T_357) @[dec_tlu_ctl.scala 1757:48] - node _T_359 = not(io.interrupt_valid_r) @[dec_tlu_ctl.scala 1757:89] - node _T_360 = and(_T_358, _T_359) @[dec_tlu_ctl.scala 1757:87] - node _T_361 = not(io.take_ext_int_start) @[dec_tlu_ctl.scala 1757:113] - node _T_362 = and(_T_360, _T_361) @[dec_tlu_ctl.scala 1757:111] - io.dec_tlu_wr_pause_r <= _T_362 @[dec_tlu_ctl.scala 1757:24] - node _T_363 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1764:61] - node _T_364 = eq(_T_363, UInt<12>("h07c0")) @[dec_tlu_ctl.scala 1764:68] - node wr_mrac_r = and(io.dec_csr_wen_r_mod, _T_364) @[dec_tlu_ctl.scala 1764:39] - node _T_365 = bits(io.dec_csr_wrdata_r, 31, 31) @[dec_tlu_ctl.scala 1767:39] - node _T_366 = bits(io.dec_csr_wrdata_r, 30, 30) @[dec_tlu_ctl.scala 1767:64] - node _T_367 = bits(io.dec_csr_wrdata_r, 31, 31) @[dec_tlu_ctl.scala 1767:91] - node _T_368 = not(_T_367) @[dec_tlu_ctl.scala 1767:71] - node _T_369 = and(_T_366, _T_368) @[dec_tlu_ctl.scala 1767:69] - node _T_370 = bits(io.dec_csr_wrdata_r, 29, 29) @[dec_tlu_ctl.scala 1768:41] - node _T_371 = bits(io.dec_csr_wrdata_r, 28, 28) @[dec_tlu_ctl.scala 1768:66] - node _T_372 = bits(io.dec_csr_wrdata_r, 29, 29) @[dec_tlu_ctl.scala 1768:93] - node _T_373 = not(_T_372) @[dec_tlu_ctl.scala 1768:73] - node _T_374 = and(_T_371, _T_373) @[dec_tlu_ctl.scala 1768:71] - node _T_375 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 1769:41] - node _T_376 = bits(io.dec_csr_wrdata_r, 26, 26) @[dec_tlu_ctl.scala 1769:66] - node _T_377 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 1769:93] - node _T_378 = not(_T_377) @[dec_tlu_ctl.scala 1769:73] - node _T_379 = and(_T_376, _T_378) @[dec_tlu_ctl.scala 1769:71] - node _T_380 = bits(io.dec_csr_wrdata_r, 25, 25) @[dec_tlu_ctl.scala 1770:41] - node _T_381 = bits(io.dec_csr_wrdata_r, 24, 24) @[dec_tlu_ctl.scala 1770:66] - node _T_382 = bits(io.dec_csr_wrdata_r, 25, 25) @[dec_tlu_ctl.scala 1770:93] - node _T_383 = not(_T_382) @[dec_tlu_ctl.scala 1770:73] - node _T_384 = and(_T_381, _T_383) @[dec_tlu_ctl.scala 1770:71] - node _T_385 = bits(io.dec_csr_wrdata_r, 23, 23) @[dec_tlu_ctl.scala 1771:41] - node _T_386 = bits(io.dec_csr_wrdata_r, 22, 22) @[dec_tlu_ctl.scala 1771:66] - node _T_387 = bits(io.dec_csr_wrdata_r, 23, 23) @[dec_tlu_ctl.scala 1771:93] - node _T_388 = not(_T_387) @[dec_tlu_ctl.scala 1771:73] - node _T_389 = and(_T_386, _T_388) @[dec_tlu_ctl.scala 1771:71] - node _T_390 = bits(io.dec_csr_wrdata_r, 21, 21) @[dec_tlu_ctl.scala 1772:41] - node _T_391 = bits(io.dec_csr_wrdata_r, 20, 20) @[dec_tlu_ctl.scala 1772:66] - node _T_392 = bits(io.dec_csr_wrdata_r, 21, 21) @[dec_tlu_ctl.scala 1772:93] - node _T_393 = not(_T_392) @[dec_tlu_ctl.scala 1772:73] - node _T_394 = and(_T_391, _T_393) @[dec_tlu_ctl.scala 1772:71] - node _T_395 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 1773:41] - node _T_396 = bits(io.dec_csr_wrdata_r, 18, 18) @[dec_tlu_ctl.scala 1773:66] - node _T_397 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 1773:93] - node _T_398 = not(_T_397) @[dec_tlu_ctl.scala 1773:73] - node _T_399 = and(_T_396, _T_398) @[dec_tlu_ctl.scala 1773:71] - node _T_400 = bits(io.dec_csr_wrdata_r, 17, 17) @[dec_tlu_ctl.scala 1774:41] - node _T_401 = bits(io.dec_csr_wrdata_r, 16, 16) @[dec_tlu_ctl.scala 1774:66] - node _T_402 = bits(io.dec_csr_wrdata_r, 17, 17) @[dec_tlu_ctl.scala 1774:93] - node _T_403 = not(_T_402) @[dec_tlu_ctl.scala 1774:73] - node _T_404 = and(_T_401, _T_403) @[dec_tlu_ctl.scala 1774:71] - node _T_405 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 1775:41] - node _T_406 = bits(io.dec_csr_wrdata_r, 14, 14) @[dec_tlu_ctl.scala 1775:66] - node _T_407 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 1775:93] - node _T_408 = not(_T_407) @[dec_tlu_ctl.scala 1775:73] - node _T_409 = and(_T_406, _T_408) @[dec_tlu_ctl.scala 1775:71] - node _T_410 = bits(io.dec_csr_wrdata_r, 13, 13) @[dec_tlu_ctl.scala 1776:41] - node _T_411 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 1776:66] - node _T_412 = bits(io.dec_csr_wrdata_r, 13, 13) @[dec_tlu_ctl.scala 1776:93] - node _T_413 = not(_T_412) @[dec_tlu_ctl.scala 1776:73] - node _T_414 = and(_T_411, _T_413) @[dec_tlu_ctl.scala 1776:71] - node _T_415 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1777:41] - node _T_416 = bits(io.dec_csr_wrdata_r, 10, 10) @[dec_tlu_ctl.scala 1777:66] - node _T_417 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1777:93] - node _T_418 = not(_T_417) @[dec_tlu_ctl.scala 1777:73] - node _T_419 = and(_T_416, _T_418) @[dec_tlu_ctl.scala 1777:71] - node _T_420 = bits(io.dec_csr_wrdata_r, 9, 9) @[dec_tlu_ctl.scala 1778:41] - node _T_421 = bits(io.dec_csr_wrdata_r, 8, 8) @[dec_tlu_ctl.scala 1778:66] - node _T_422 = bits(io.dec_csr_wrdata_r, 9, 9) @[dec_tlu_ctl.scala 1778:93] - node _T_423 = not(_T_422) @[dec_tlu_ctl.scala 1778:73] - node _T_424 = and(_T_421, _T_423) @[dec_tlu_ctl.scala 1778:70] - node _T_425 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1779:41] - node _T_426 = bits(io.dec_csr_wrdata_r, 6, 6) @[dec_tlu_ctl.scala 1779:66] - node _T_427 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1779:93] - node _T_428 = not(_T_427) @[dec_tlu_ctl.scala 1779:73] - node _T_429 = and(_T_426, _T_428) @[dec_tlu_ctl.scala 1779:70] - node _T_430 = bits(io.dec_csr_wrdata_r, 5, 5) @[dec_tlu_ctl.scala 1780:41] - node _T_431 = bits(io.dec_csr_wrdata_r, 4, 4) @[dec_tlu_ctl.scala 1780:66] - node _T_432 = bits(io.dec_csr_wrdata_r, 5, 5) @[dec_tlu_ctl.scala 1780:93] - node _T_433 = not(_T_432) @[dec_tlu_ctl.scala 1780:73] - node _T_434 = and(_T_431, _T_433) @[dec_tlu_ctl.scala 1780:70] - node _T_435 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1781:41] - node _T_436 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 1781:66] - node _T_437 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1781:93] - node _T_438 = not(_T_437) @[dec_tlu_ctl.scala 1781:73] - node _T_439 = and(_T_436, _T_438) @[dec_tlu_ctl.scala 1781:70] - node _T_440 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1782:41] - node _T_441 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1782:66] - node _T_442 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1782:93] - node _T_443 = not(_T_442) @[dec_tlu_ctl.scala 1782:73] - node _T_444 = and(_T_441, _T_443) @[dec_tlu_ctl.scala 1782:70] - node _T_445 = cat(_T_440, _T_444) @[Cat.scala 29:58] - node _T_446 = cat(_T_435, _T_439) @[Cat.scala 29:58] - node _T_447 = cat(_T_446, _T_445) @[Cat.scala 29:58] - node _T_448 = cat(_T_430, _T_434) @[Cat.scala 29:58] - node _T_449 = cat(_T_425, _T_429) @[Cat.scala 29:58] - node _T_450 = cat(_T_449, _T_448) @[Cat.scala 29:58] - node _T_451 = cat(_T_450, _T_447) @[Cat.scala 29:58] - node _T_452 = cat(_T_420, _T_424) @[Cat.scala 29:58] - node _T_453 = cat(_T_415, _T_419) @[Cat.scala 29:58] - node _T_454 = cat(_T_453, _T_452) @[Cat.scala 29:58] - node _T_455 = cat(_T_410, _T_414) @[Cat.scala 29:58] - node _T_456 = cat(_T_405, _T_409) @[Cat.scala 29:58] + mfdc_ns <= _T_348 @[dec_tlu_ctl.scala 1733:13] + node _T_349 = bits(mfdc_int, 14, 12) @[dec_tlu_ctl.scala 1734:29] + node _T_350 = not(_T_349) @[dec_tlu_ctl.scala 1734:20] + node _T_351 = bits(mfdc_int, 11, 7) @[dec_tlu_ctl.scala 1734:55] + node _T_352 = bits(mfdc_int, 6, 6) @[dec_tlu_ctl.scala 1734:72] + node _T_353 = not(_T_352) @[dec_tlu_ctl.scala 1734:63] + node _T_354 = bits(mfdc_int, 5, 0) @[dec_tlu_ctl.scala 1734:85] + node _T_355 = cat(_T_353, _T_354) @[Cat.scala 29:58] + node _T_356 = cat(_T_350, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_357 = cat(_T_356, _T_351) @[Cat.scala 29:58] + node _T_358 = cat(_T_357, _T_355) @[Cat.scala 29:58] + mfdc <= _T_358 @[dec_tlu_ctl.scala 1734:13] + node _T_359 = bits(mfdc, 18, 16) @[dec_tlu_ctl.scala 1742:46] + io.dec_tlu_dma_qos_prty <= _T_359 @[dec_tlu_ctl.scala 1742:39] + node _T_360 = bits(mfdc, 11, 11) @[dec_tlu_ctl.scala 1743:46] + io.dec_tlu_external_ldfwd_disable <= _T_360 @[dec_tlu_ctl.scala 1743:39] + node _T_361 = bits(mfdc, 8, 8) @[dec_tlu_ctl.scala 1744:46] + io.dec_tlu_core_ecc_disable <= _T_361 @[dec_tlu_ctl.scala 1744:39] + node _T_362 = bits(mfdc, 6, 6) @[dec_tlu_ctl.scala 1745:46] + io.dec_tlu_sideeffect_posted_disable <= _T_362 @[dec_tlu_ctl.scala 1745:39] + node _T_363 = bits(mfdc, 3, 3) @[dec_tlu_ctl.scala 1746:46] + io.dec_tlu_bpred_disable <= _T_363 @[dec_tlu_ctl.scala 1746:39] + node _T_364 = bits(mfdc, 2, 2) @[dec_tlu_ctl.scala 1747:46] + io.dec_tlu_wb_coalescing_disable <= _T_364 @[dec_tlu_ctl.scala 1747:39] + node _T_365 = bits(mfdc, 0, 0) @[dec_tlu_ctl.scala 1748:46] + io.dec_tlu_pipelining_disable <= _T_365 @[dec_tlu_ctl.scala 1748:39] + node _T_366 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1757:70] + node _T_367 = eq(_T_366, UInt<12>("h07c2")) @[dec_tlu_ctl.scala 1757:77] + node _T_368 = and(io.dec_csr_wen_r_mod, _T_367) @[dec_tlu_ctl.scala 1757:48] + node _T_369 = not(io.interrupt_valid_r) @[dec_tlu_ctl.scala 1757:89] + node _T_370 = and(_T_368, _T_369) @[dec_tlu_ctl.scala 1757:87] + node _T_371 = not(io.take_ext_int_start) @[dec_tlu_ctl.scala 1757:113] + node _T_372 = and(_T_370, _T_371) @[dec_tlu_ctl.scala 1757:111] + io.dec_tlu_wr_pause_r <= _T_372 @[dec_tlu_ctl.scala 1757:24] + node _T_373 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1764:61] + node _T_374 = eq(_T_373, UInt<12>("h07c0")) @[dec_tlu_ctl.scala 1764:68] + node wr_mrac_r = and(io.dec_csr_wen_r_mod, _T_374) @[dec_tlu_ctl.scala 1764:39] + node _T_375 = bits(io.dec_csr_wrdata_r, 31, 31) @[dec_tlu_ctl.scala 1767:39] + node _T_376 = bits(io.dec_csr_wrdata_r, 30, 30) @[dec_tlu_ctl.scala 1767:64] + node _T_377 = bits(io.dec_csr_wrdata_r, 31, 31) @[dec_tlu_ctl.scala 1767:91] + node _T_378 = not(_T_377) @[dec_tlu_ctl.scala 1767:71] + node _T_379 = and(_T_376, _T_378) @[dec_tlu_ctl.scala 1767:69] + node _T_380 = bits(io.dec_csr_wrdata_r, 29, 29) @[dec_tlu_ctl.scala 1768:41] + node _T_381 = bits(io.dec_csr_wrdata_r, 28, 28) @[dec_tlu_ctl.scala 1768:66] + node _T_382 = bits(io.dec_csr_wrdata_r, 29, 29) @[dec_tlu_ctl.scala 1768:93] + node _T_383 = not(_T_382) @[dec_tlu_ctl.scala 1768:73] + node _T_384 = and(_T_381, _T_383) @[dec_tlu_ctl.scala 1768:71] + node _T_385 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 1769:41] + node _T_386 = bits(io.dec_csr_wrdata_r, 26, 26) @[dec_tlu_ctl.scala 1769:66] + node _T_387 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 1769:93] + node _T_388 = not(_T_387) @[dec_tlu_ctl.scala 1769:73] + node _T_389 = and(_T_386, _T_388) @[dec_tlu_ctl.scala 1769:71] + node _T_390 = bits(io.dec_csr_wrdata_r, 25, 25) @[dec_tlu_ctl.scala 1770:41] + node _T_391 = bits(io.dec_csr_wrdata_r, 24, 24) @[dec_tlu_ctl.scala 1770:66] + node _T_392 = bits(io.dec_csr_wrdata_r, 25, 25) @[dec_tlu_ctl.scala 1770:93] + node _T_393 = not(_T_392) @[dec_tlu_ctl.scala 1770:73] + node _T_394 = and(_T_391, _T_393) @[dec_tlu_ctl.scala 1770:71] + node _T_395 = bits(io.dec_csr_wrdata_r, 23, 23) @[dec_tlu_ctl.scala 1771:41] + node _T_396 = bits(io.dec_csr_wrdata_r, 22, 22) @[dec_tlu_ctl.scala 1771:66] + node _T_397 = bits(io.dec_csr_wrdata_r, 23, 23) @[dec_tlu_ctl.scala 1771:93] + node _T_398 = not(_T_397) @[dec_tlu_ctl.scala 1771:73] + node _T_399 = and(_T_396, _T_398) @[dec_tlu_ctl.scala 1771:71] + node _T_400 = bits(io.dec_csr_wrdata_r, 21, 21) @[dec_tlu_ctl.scala 1772:41] + node _T_401 = bits(io.dec_csr_wrdata_r, 20, 20) @[dec_tlu_ctl.scala 1772:66] + node _T_402 = bits(io.dec_csr_wrdata_r, 21, 21) @[dec_tlu_ctl.scala 1772:93] + node _T_403 = not(_T_402) @[dec_tlu_ctl.scala 1772:73] + node _T_404 = and(_T_401, _T_403) @[dec_tlu_ctl.scala 1772:71] + node _T_405 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 1773:41] + node _T_406 = bits(io.dec_csr_wrdata_r, 18, 18) @[dec_tlu_ctl.scala 1773:66] + node _T_407 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 1773:93] + node _T_408 = not(_T_407) @[dec_tlu_ctl.scala 1773:73] + node _T_409 = and(_T_406, _T_408) @[dec_tlu_ctl.scala 1773:71] + node _T_410 = bits(io.dec_csr_wrdata_r, 17, 17) @[dec_tlu_ctl.scala 1774:41] + node _T_411 = bits(io.dec_csr_wrdata_r, 16, 16) @[dec_tlu_ctl.scala 1774:66] + node _T_412 = bits(io.dec_csr_wrdata_r, 17, 17) @[dec_tlu_ctl.scala 1774:93] + node _T_413 = not(_T_412) @[dec_tlu_ctl.scala 1774:73] + node _T_414 = and(_T_411, _T_413) @[dec_tlu_ctl.scala 1774:71] + node _T_415 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 1775:41] + node _T_416 = bits(io.dec_csr_wrdata_r, 14, 14) @[dec_tlu_ctl.scala 1775:66] + node _T_417 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 1775:93] + node _T_418 = not(_T_417) @[dec_tlu_ctl.scala 1775:73] + node _T_419 = and(_T_416, _T_418) @[dec_tlu_ctl.scala 1775:71] + node _T_420 = bits(io.dec_csr_wrdata_r, 13, 13) @[dec_tlu_ctl.scala 1776:41] + node _T_421 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 1776:66] + node _T_422 = bits(io.dec_csr_wrdata_r, 13, 13) @[dec_tlu_ctl.scala 1776:93] + node _T_423 = not(_T_422) @[dec_tlu_ctl.scala 1776:73] + node _T_424 = and(_T_421, _T_423) @[dec_tlu_ctl.scala 1776:71] + node _T_425 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1777:41] + node _T_426 = bits(io.dec_csr_wrdata_r, 10, 10) @[dec_tlu_ctl.scala 1777:66] + node _T_427 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1777:93] + node _T_428 = not(_T_427) @[dec_tlu_ctl.scala 1777:73] + node _T_429 = and(_T_426, _T_428) @[dec_tlu_ctl.scala 1777:71] + node _T_430 = bits(io.dec_csr_wrdata_r, 9, 9) @[dec_tlu_ctl.scala 1778:41] + node _T_431 = bits(io.dec_csr_wrdata_r, 8, 8) @[dec_tlu_ctl.scala 1778:66] + node _T_432 = bits(io.dec_csr_wrdata_r, 9, 9) @[dec_tlu_ctl.scala 1778:93] + node _T_433 = not(_T_432) @[dec_tlu_ctl.scala 1778:73] + node _T_434 = and(_T_431, _T_433) @[dec_tlu_ctl.scala 1778:70] + node _T_435 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1779:41] + node _T_436 = bits(io.dec_csr_wrdata_r, 6, 6) @[dec_tlu_ctl.scala 1779:66] + node _T_437 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1779:93] + node _T_438 = not(_T_437) @[dec_tlu_ctl.scala 1779:73] + node _T_439 = and(_T_436, _T_438) @[dec_tlu_ctl.scala 1779:70] + node _T_440 = bits(io.dec_csr_wrdata_r, 5, 5) @[dec_tlu_ctl.scala 1780:41] + node _T_441 = bits(io.dec_csr_wrdata_r, 4, 4) @[dec_tlu_ctl.scala 1780:66] + node _T_442 = bits(io.dec_csr_wrdata_r, 5, 5) @[dec_tlu_ctl.scala 1780:93] + node _T_443 = not(_T_442) @[dec_tlu_ctl.scala 1780:73] + node _T_444 = and(_T_441, _T_443) @[dec_tlu_ctl.scala 1780:70] + node _T_445 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1781:41] + node _T_446 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 1781:66] + node _T_447 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1781:93] + node _T_448 = not(_T_447) @[dec_tlu_ctl.scala 1781:73] + node _T_449 = and(_T_446, _T_448) @[dec_tlu_ctl.scala 1781:70] + node _T_450 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1782:41] + node _T_451 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1782:66] + node _T_452 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1782:93] + node _T_453 = not(_T_452) @[dec_tlu_ctl.scala 1782:73] + node _T_454 = and(_T_451, _T_453) @[dec_tlu_ctl.scala 1782:70] + node _T_455 = cat(_T_450, _T_454) @[Cat.scala 29:58] + node _T_456 = cat(_T_445, _T_449) @[Cat.scala 29:58] node _T_457 = cat(_T_456, _T_455) @[Cat.scala 29:58] - node _T_458 = cat(_T_457, _T_454) @[Cat.scala 29:58] - node _T_459 = cat(_T_458, _T_451) @[Cat.scala 29:58] - node _T_460 = cat(_T_400, _T_404) @[Cat.scala 29:58] - node _T_461 = cat(_T_395, _T_399) @[Cat.scala 29:58] - node _T_462 = cat(_T_461, _T_460) @[Cat.scala 29:58] - node _T_463 = cat(_T_390, _T_394) @[Cat.scala 29:58] - node _T_464 = cat(_T_385, _T_389) @[Cat.scala 29:58] - node _T_465 = cat(_T_464, _T_463) @[Cat.scala 29:58] - node _T_466 = cat(_T_465, _T_462) @[Cat.scala 29:58] - node _T_467 = cat(_T_380, _T_384) @[Cat.scala 29:58] - node _T_468 = cat(_T_375, _T_379) @[Cat.scala 29:58] - node _T_469 = cat(_T_468, _T_467) @[Cat.scala 29:58] - node _T_470 = cat(_T_370, _T_374) @[Cat.scala 29:58] - node _T_471 = cat(_T_365, _T_369) @[Cat.scala 29:58] + node _T_458 = cat(_T_440, _T_444) @[Cat.scala 29:58] + node _T_459 = cat(_T_435, _T_439) @[Cat.scala 29:58] + node _T_460 = cat(_T_459, _T_458) @[Cat.scala 29:58] + node _T_461 = cat(_T_460, _T_457) @[Cat.scala 29:58] + node _T_462 = cat(_T_430, _T_434) @[Cat.scala 29:58] + node _T_463 = cat(_T_425, _T_429) @[Cat.scala 29:58] + node _T_464 = cat(_T_463, _T_462) @[Cat.scala 29:58] + node _T_465 = cat(_T_420, _T_424) @[Cat.scala 29:58] + node _T_466 = cat(_T_415, _T_419) @[Cat.scala 29:58] + node _T_467 = cat(_T_466, _T_465) @[Cat.scala 29:58] + node _T_468 = cat(_T_467, _T_464) @[Cat.scala 29:58] + node _T_469 = cat(_T_468, _T_461) @[Cat.scala 29:58] + node _T_470 = cat(_T_410, _T_414) @[Cat.scala 29:58] + node _T_471 = cat(_T_405, _T_409) @[Cat.scala 29:58] node _T_472 = cat(_T_471, _T_470) @[Cat.scala 29:58] - node _T_473 = cat(_T_472, _T_469) @[Cat.scala 29:58] - node _T_474 = cat(_T_473, _T_466) @[Cat.scala 29:58] - node mrac_in = cat(_T_474, _T_459) @[Cat.scala 29:58] - node _T_475 = bits(wr_mrac_r, 0, 0) @[dec_tlu_ctl.scala 1785:38] + node _T_473 = cat(_T_400, _T_404) @[Cat.scala 29:58] + node _T_474 = cat(_T_395, _T_399) @[Cat.scala 29:58] + node _T_475 = cat(_T_474, _T_473) @[Cat.scala 29:58] + node _T_476 = cat(_T_475, _T_472) @[Cat.scala 29:58] + node _T_477 = cat(_T_390, _T_394) @[Cat.scala 29:58] + node _T_478 = cat(_T_385, _T_389) @[Cat.scala 29:58] + node _T_479 = cat(_T_478, _T_477) @[Cat.scala 29:58] + node _T_480 = cat(_T_380, _T_384) @[Cat.scala 29:58] + node _T_481 = cat(_T_375, _T_379) @[Cat.scala 29:58] + node _T_482 = cat(_T_481, _T_480) @[Cat.scala 29:58] + node _T_483 = cat(_T_482, _T_479) @[Cat.scala 29:58] + node _T_484 = cat(_T_483, _T_476) @[Cat.scala 29:58] + node mrac_in = cat(_T_484, _T_469) @[Cat.scala 29:58] + node _T_485 = bits(wr_mrac_r, 0, 0) @[dec_tlu_ctl.scala 1785:38] inst rvclkhdr_10 of rvclkhdr_730 @[lib.scala 368:23] rvclkhdr_10.clock <= clock rvclkhdr_10.reset <= reset rvclkhdr_10.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_10.io.en <= _T_475 @[lib.scala 371:17] + rvclkhdr_10.io.en <= _T_485 @[lib.scala 371:17] rvclkhdr_10.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg mrac : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] mrac <= mrac_in @[lib.scala 374:16] io.dec_tlu_mrac_ff <= mrac @[dec_tlu_ctl.scala 1787:21] - node _T_476 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1795:62] - node _T_477 = eq(_T_476, UInt<12>("h0bc0")) @[dec_tlu_ctl.scala 1795:69] - node wr_mdeau_r = and(io.dec_csr_wen_r_mod, _T_477) @[dec_tlu_ctl.scala 1795:40] - node _T_478 = not(wr_mdeau_r) @[dec_tlu_ctl.scala 1805:59] - node _T_479 = and(io.mdseac_locked_f, _T_478) @[dec_tlu_ctl.scala 1805:57] - node _T_480 = or(mdseac_en, _T_479) @[dec_tlu_ctl.scala 1805:35] - io.mdseac_locked_ns <= _T_480 @[dec_tlu_ctl.scala 1805:22] - node _T_481 = or(io.lsu_imprecise_error_store_any, io.lsu_imprecise_error_load_any) @[dec_tlu_ctl.scala 1807:49] - node _T_482 = not(io.nmi_int_detected_f) @[dec_tlu_ctl.scala 1807:86] - node _T_483 = and(_T_481, _T_482) @[dec_tlu_ctl.scala 1807:84] - node _T_484 = not(io.mdseac_locked_f) @[dec_tlu_ctl.scala 1807:111] - node _T_485 = and(_T_483, _T_484) @[dec_tlu_ctl.scala 1807:109] - mdseac_en <= _T_485 @[dec_tlu_ctl.scala 1807:12] - node _T_486 = bits(mdseac_en, 0, 0) @[dec_tlu_ctl.scala 1809:64] + node _T_486 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1795:62] + node _T_487 = eq(_T_486, UInt<12>("h0bc0")) @[dec_tlu_ctl.scala 1795:69] + node wr_mdeau_r = and(io.dec_csr_wen_r_mod, _T_487) @[dec_tlu_ctl.scala 1795:40] + node _T_488 = not(wr_mdeau_r) @[dec_tlu_ctl.scala 1805:59] + node _T_489 = and(io.mdseac_locked_f, _T_488) @[dec_tlu_ctl.scala 1805:57] + node _T_490 = or(mdseac_en, _T_489) @[dec_tlu_ctl.scala 1805:35] + io.mdseac_locked_ns <= _T_490 @[dec_tlu_ctl.scala 1805:22] + node _T_491 = or(io.lsu_imprecise_error_store_any, io.lsu_imprecise_error_load_any) @[dec_tlu_ctl.scala 1807:49] + node _T_492 = not(io.nmi_int_detected_f) @[dec_tlu_ctl.scala 1807:86] + node _T_493 = and(_T_491, _T_492) @[dec_tlu_ctl.scala 1807:84] + node _T_494 = not(io.mdseac_locked_f) @[dec_tlu_ctl.scala 1807:111] + node _T_495 = and(_T_493, _T_494) @[dec_tlu_ctl.scala 1807:109] + mdseac_en <= _T_495 @[dec_tlu_ctl.scala 1807:12] + node _T_496 = bits(mdseac_en, 0, 0) @[dec_tlu_ctl.scala 1809:64] inst rvclkhdr_11 of rvclkhdr_731 @[lib.scala 368:23] rvclkhdr_11.clock <= clock rvclkhdr_11.reset <= reset rvclkhdr_11.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_11.io.en <= _T_486 @[lib.scala 371:17] + rvclkhdr_11.io.en <= _T_496 @[lib.scala 371:17] rvclkhdr_11.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg mdseac : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] mdseac <= io.lsu_imprecise_error_addr_any @[lib.scala 374:16] - node _T_487 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1818:61] - node _T_488 = eq(_T_487, UInt<12>("h07c6")) @[dec_tlu_ctl.scala 1818:68] - node wr_mpmc_r = and(io.dec_csr_wen_r_mod, _T_488) @[dec_tlu_ctl.scala 1818:39] - node _T_489 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1822:51] - node _T_490 = and(wr_mpmc_r, _T_489) @[dec_tlu_ctl.scala 1822:30] - node _T_491 = not(io.internal_dbg_halt_mode_f2) @[dec_tlu_ctl.scala 1822:57] - node _T_492 = and(_T_490, _T_491) @[dec_tlu_ctl.scala 1822:55] - node _T_493 = not(io.ext_int_freeze_d1) @[dec_tlu_ctl.scala 1822:89] - node _T_494 = and(_T_492, _T_493) @[dec_tlu_ctl.scala 1822:87] - io.fw_halt_req <= _T_494 @[dec_tlu_ctl.scala 1822:17] + node _T_497 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1818:61] + node _T_498 = eq(_T_497, UInt<12>("h07c6")) @[dec_tlu_ctl.scala 1818:68] + node wr_mpmc_r = and(io.dec_csr_wen_r_mod, _T_498) @[dec_tlu_ctl.scala 1818:39] + node _T_499 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1822:51] + node _T_500 = and(wr_mpmc_r, _T_499) @[dec_tlu_ctl.scala 1822:30] + node _T_501 = not(io.internal_dbg_halt_mode_f2) @[dec_tlu_ctl.scala 1822:57] + node _T_502 = and(_T_500, _T_501) @[dec_tlu_ctl.scala 1822:55] + node _T_503 = not(io.ext_int_freeze_d1) @[dec_tlu_ctl.scala 1822:89] + node _T_504 = and(_T_502, _T_503) @[dec_tlu_ctl.scala 1822:87] + io.fw_halt_req <= _T_504 @[dec_tlu_ctl.scala 1822:17] wire fw_halted_ns : UInt<1> fw_halted_ns <= UInt<1>("h00") reg fw_halted : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1824:48] fw_halted <= fw_halted_ns @[dec_tlu_ctl.scala 1824:48] - node _T_495 = or(io.fw_halt_req, fw_halted) @[dec_tlu_ctl.scala 1825:34] - node _T_496 = not(set_mie_pmu_fw_halt) @[dec_tlu_ctl.scala 1825:49] - node _T_497 = and(_T_495, _T_496) @[dec_tlu_ctl.scala 1825:47] - fw_halted_ns <= _T_497 @[dec_tlu_ctl.scala 1825:15] - node _T_498 = bits(wr_mpmc_r, 0, 0) @[dec_tlu_ctl.scala 1826:29] - node _T_499 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1826:57] - node _T_500 = not(_T_499) @[dec_tlu_ctl.scala 1826:37] - node _T_501 = not(mpmc) @[dec_tlu_ctl.scala 1826:62] - node _T_502 = mux(_T_498, _T_500, _T_501) @[dec_tlu_ctl.scala 1826:18] - mpmc_b_ns <= _T_502 @[dec_tlu_ctl.scala 1826:12] - reg _T_503 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1828:44] - _T_503 <= mpmc_b_ns @[dec_tlu_ctl.scala 1828:44] - mpmc_b <= _T_503 @[dec_tlu_ctl.scala 1828:9] - node _T_504 = not(mpmc_b) @[dec_tlu_ctl.scala 1831:10] - mpmc <= _T_504 @[dec_tlu_ctl.scala 1831:7] - node _T_505 = bits(io.dec_csr_wrdata_r, 31, 27) @[dec_tlu_ctl.scala 1840:40] - node _T_506 = gt(_T_505, UInt<5>("h01a")) @[dec_tlu_ctl.scala 1840:48] - node _T_507 = bits(io.dec_csr_wrdata_r, 31, 27) @[dec_tlu_ctl.scala 1840:92] - node csr_sat = mux(_T_506, UInt<5>("h01a"), _T_507) @[dec_tlu_ctl.scala 1840:19] - node _T_508 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1842:63] - node _T_509 = eq(_T_508, UInt<12>("h07f0")) @[dec_tlu_ctl.scala 1842:70] - node wr_micect_r = and(io.dec_csr_wen_r_mod, _T_509) @[dec_tlu_ctl.scala 1842:41] - node _T_510 = cat(UInt<26>("h00"), io.ic_perr_r_d1) @[Cat.scala 29:58] - node _T_511 = add(micect, _T_510) @[dec_tlu_ctl.scala 1843:23] - node _T_512 = tail(_T_511, 1) @[dec_tlu_ctl.scala 1843:23] - micect_inc <= _T_512 @[dec_tlu_ctl.scala 1843:13] - node _T_513 = bits(wr_micect_r, 0, 0) @[dec_tlu_ctl.scala 1844:35] - node _T_514 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1844:75] - node _T_515 = cat(csr_sat, _T_514) @[Cat.scala 29:58] - node _T_516 = bits(micect, 31, 27) @[dec_tlu_ctl.scala 1844:95] - node _T_517 = cat(_T_516, micect_inc) @[Cat.scala 29:58] - node micect_ns = mux(_T_513, _T_515, _T_517) @[dec_tlu_ctl.scala 1844:22] - node _T_518 = or(wr_micect_r, io.ic_perr_r_d1) @[dec_tlu_ctl.scala 1846:42] - node _T_519 = bits(_T_518, 0, 0) @[dec_tlu_ctl.scala 1846:61] + node _T_505 = or(io.fw_halt_req, fw_halted) @[dec_tlu_ctl.scala 1825:34] + node _T_506 = not(set_mie_pmu_fw_halt) @[dec_tlu_ctl.scala 1825:49] + node _T_507 = and(_T_505, _T_506) @[dec_tlu_ctl.scala 1825:47] + fw_halted_ns <= _T_507 @[dec_tlu_ctl.scala 1825:15] + node _T_508 = bits(wr_mpmc_r, 0, 0) @[dec_tlu_ctl.scala 1826:29] + node _T_509 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1826:57] + node _T_510 = not(_T_509) @[dec_tlu_ctl.scala 1826:37] + node _T_511 = not(mpmc) @[dec_tlu_ctl.scala 1826:62] + node _T_512 = mux(_T_508, _T_510, _T_511) @[dec_tlu_ctl.scala 1826:18] + mpmc_b_ns <= _T_512 @[dec_tlu_ctl.scala 1826:12] + reg _T_513 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1828:44] + _T_513 <= mpmc_b_ns @[dec_tlu_ctl.scala 1828:44] + mpmc_b <= _T_513 @[dec_tlu_ctl.scala 1828:9] + node _T_514 = not(mpmc_b) @[dec_tlu_ctl.scala 1831:10] + mpmc <= _T_514 @[dec_tlu_ctl.scala 1831:7] + node _T_515 = bits(io.dec_csr_wrdata_r, 31, 27) @[dec_tlu_ctl.scala 1840:40] + node _T_516 = gt(_T_515, UInt<5>("h01a")) @[dec_tlu_ctl.scala 1840:48] + node _T_517 = bits(io.dec_csr_wrdata_r, 31, 27) @[dec_tlu_ctl.scala 1840:92] + node csr_sat = mux(_T_516, UInt<5>("h01a"), _T_517) @[dec_tlu_ctl.scala 1840:19] + node _T_518 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1842:63] + node _T_519 = eq(_T_518, UInt<12>("h07f0")) @[dec_tlu_ctl.scala 1842:70] + node wr_micect_r = and(io.dec_csr_wen_r_mod, _T_519) @[dec_tlu_ctl.scala 1842:41] + node _T_520 = cat(UInt<26>("h00"), io.ic_perr_r_d1) @[Cat.scala 29:58] + node _T_521 = add(micect, _T_520) @[dec_tlu_ctl.scala 1843:23] + node _T_522 = tail(_T_521, 1) @[dec_tlu_ctl.scala 1843:23] + micect_inc <= _T_522 @[dec_tlu_ctl.scala 1843:13] + node _T_523 = bits(wr_micect_r, 0, 0) @[dec_tlu_ctl.scala 1844:35] + node _T_524 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1844:75] + node _T_525 = cat(csr_sat, _T_524) @[Cat.scala 29:58] + node _T_526 = bits(micect, 31, 27) @[dec_tlu_ctl.scala 1844:95] + node _T_527 = cat(_T_526, micect_inc) @[Cat.scala 29:58] + node micect_ns = mux(_T_523, _T_525, _T_527) @[dec_tlu_ctl.scala 1844:22] + node _T_528 = or(wr_micect_r, io.ic_perr_r_d1) @[dec_tlu_ctl.scala 1846:42] + node _T_529 = bits(_T_528, 0, 0) @[dec_tlu_ctl.scala 1846:61] inst rvclkhdr_12 of rvclkhdr_732 @[lib.scala 368:23] rvclkhdr_12.clock <= clock rvclkhdr_12.reset <= reset rvclkhdr_12.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_12.io.en <= _T_519 @[lib.scala 371:17] + rvclkhdr_12.io.en <= _T_529 @[lib.scala 371:17] rvclkhdr_12.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_520 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_520 <= micect_ns @[lib.scala 374:16] - micect <= _T_520 @[dec_tlu_ctl.scala 1846:9] - node _T_521 = bits(micect, 31, 27) @[dec_tlu_ctl.scala 1848:48] - node _T_522 = dshl(UInt<32>("h0ffffffff"), _T_521) @[dec_tlu_ctl.scala 1848:39] - node _T_523 = bits(micect, 26, 0) @[dec_tlu_ctl.scala 1848:79] - node _T_524 = cat(UInt<5>("h00"), _T_523) @[Cat.scala 29:58] - node _T_525 = and(_T_522, _T_524) @[dec_tlu_ctl.scala 1848:57] - node _T_526 = orr(_T_525) @[dec_tlu_ctl.scala 1848:88] - mice_ce_req <= _T_526 @[dec_tlu_ctl.scala 1848:14] - node _T_527 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1857:69] - node _T_528 = eq(_T_527, UInt<12>("h07f1")) @[dec_tlu_ctl.scala 1857:76] - node wr_miccmect_r = and(io.dec_csr_wen_r_mod, _T_528) @[dec_tlu_ctl.scala 1857:47] - node _T_529 = bits(miccmect, 26, 0) @[dec_tlu_ctl.scala 1858:26] - node _T_530 = or(io.iccm_sbecc_r_d1, io.iccm_dma_sb_error) @[dec_tlu_ctl.scala 1858:70] - node _T_531 = cat(UInt<26>("h00"), _T_530) @[Cat.scala 29:58] - node _T_532 = add(_T_529, _T_531) @[dec_tlu_ctl.scala 1858:33] - node _T_533 = tail(_T_532, 1) @[dec_tlu_ctl.scala 1858:33] - miccmect_inc <= _T_533 @[dec_tlu_ctl.scala 1858:15] - node _T_534 = bits(wr_miccmect_r, 0, 0) @[dec_tlu_ctl.scala 1859:45] - node _T_535 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1859:85] - node _T_536 = cat(csr_sat, _T_535) @[Cat.scala 29:58] - node _T_537 = bits(miccmect, 31, 27) @[dec_tlu_ctl.scala 1859:107] - node _T_538 = cat(_T_537, miccmect_inc) @[Cat.scala 29:58] - node miccmect_ns = mux(_T_534, _T_536, _T_538) @[dec_tlu_ctl.scala 1859:30] - node _T_539 = or(wr_miccmect_r, io.iccm_sbecc_r_d1) @[dec_tlu_ctl.scala 1861:48] - node _T_540 = or(_T_539, io.iccm_dma_sb_error) @[dec_tlu_ctl.scala 1861:69] - node _T_541 = bits(_T_540, 0, 0) @[dec_tlu_ctl.scala 1861:93] + reg _T_530 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_530 <= micect_ns @[lib.scala 374:16] + micect <= _T_530 @[dec_tlu_ctl.scala 1846:9] + node _T_531 = bits(micect, 31, 27) @[dec_tlu_ctl.scala 1848:48] + node _T_532 = dshl(UInt<32>("h0ffffffff"), _T_531) @[dec_tlu_ctl.scala 1848:39] + node _T_533 = bits(micect, 26, 0) @[dec_tlu_ctl.scala 1848:79] + node _T_534 = cat(UInt<5>("h00"), _T_533) @[Cat.scala 29:58] + node _T_535 = and(_T_532, _T_534) @[dec_tlu_ctl.scala 1848:57] + node _T_536 = orr(_T_535) @[dec_tlu_ctl.scala 1848:88] + mice_ce_req <= _T_536 @[dec_tlu_ctl.scala 1848:14] + node _T_537 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1857:69] + node _T_538 = eq(_T_537, UInt<12>("h07f1")) @[dec_tlu_ctl.scala 1857:76] + node wr_miccmect_r = and(io.dec_csr_wen_r_mod, _T_538) @[dec_tlu_ctl.scala 1857:47] + node _T_539 = bits(miccmect, 26, 0) @[dec_tlu_ctl.scala 1858:26] + node _T_540 = or(io.iccm_sbecc_r_d1, io.iccm_dma_sb_error) @[dec_tlu_ctl.scala 1858:70] + node _T_541 = cat(UInt<26>("h00"), _T_540) @[Cat.scala 29:58] + node _T_542 = add(_T_539, _T_541) @[dec_tlu_ctl.scala 1858:33] + node _T_543 = tail(_T_542, 1) @[dec_tlu_ctl.scala 1858:33] + miccmect_inc <= _T_543 @[dec_tlu_ctl.scala 1858:15] + node _T_544 = bits(wr_miccmect_r, 0, 0) @[dec_tlu_ctl.scala 1859:45] + node _T_545 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1859:85] + node _T_546 = cat(csr_sat, _T_545) @[Cat.scala 29:58] + node _T_547 = bits(miccmect, 31, 27) @[dec_tlu_ctl.scala 1859:107] + node _T_548 = cat(_T_547, miccmect_inc) @[Cat.scala 29:58] + node miccmect_ns = mux(_T_544, _T_546, _T_548) @[dec_tlu_ctl.scala 1859:30] + node _T_549 = or(wr_miccmect_r, io.iccm_sbecc_r_d1) @[dec_tlu_ctl.scala 1861:48] + node _T_550 = or(_T_549, io.iccm_dma_sb_error) @[dec_tlu_ctl.scala 1861:69] + node _T_551 = bits(_T_550, 0, 0) @[dec_tlu_ctl.scala 1861:93] inst rvclkhdr_13 of rvclkhdr_733 @[lib.scala 368:23] rvclkhdr_13.clock <= clock rvclkhdr_13.reset <= reset rvclkhdr_13.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_13.io.en <= _T_541 @[lib.scala 371:17] + rvclkhdr_13.io.en <= _T_551 @[lib.scala 371:17] rvclkhdr_13.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_542 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_542 <= miccmect_ns @[lib.scala 374:16] - miccmect <= _T_542 @[dec_tlu_ctl.scala 1861:11] - node _T_543 = bits(miccmect, 31, 27) @[dec_tlu_ctl.scala 1863:51] - node _T_544 = dshl(UInt<32>("h0ffffffff"), _T_543) @[dec_tlu_ctl.scala 1863:40] - node _T_545 = bits(miccmect, 26, 0) @[dec_tlu_ctl.scala 1863:84] - node _T_546 = cat(UInt<5>("h00"), _T_545) @[Cat.scala 29:58] - node _T_547 = and(_T_544, _T_546) @[dec_tlu_ctl.scala 1863:60] - node _T_548 = orr(_T_547) @[dec_tlu_ctl.scala 1863:93] - miccme_ce_req <= _T_548 @[dec_tlu_ctl.scala 1863:15] - node _T_549 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1872:69] - node _T_550 = eq(_T_549, UInt<12>("h07f2")) @[dec_tlu_ctl.scala 1872:76] - node wr_mdccmect_r = and(io.dec_csr_wen_r_mod, _T_550) @[dec_tlu_ctl.scala 1872:47] - node _T_551 = bits(mdccmect, 26, 0) @[dec_tlu_ctl.scala 1873:26] - node _T_552 = cat(UInt<26>("h00"), io.lsu_single_ecc_error_r_d1) @[Cat.scala 29:58] - node _T_553 = add(_T_551, _T_552) @[dec_tlu_ctl.scala 1873:33] - node _T_554 = tail(_T_553, 1) @[dec_tlu_ctl.scala 1873:33] - mdccmect_inc <= _T_554 @[dec_tlu_ctl.scala 1873:15] - node _T_555 = bits(wr_mdccmect_r, 0, 0) @[dec_tlu_ctl.scala 1874:45] - node _T_556 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1874:85] - node _T_557 = cat(csr_sat, _T_556) @[Cat.scala 29:58] - node _T_558 = bits(mdccmect, 31, 27) @[dec_tlu_ctl.scala 1874:107] - node _T_559 = cat(_T_558, mdccmect_inc) @[Cat.scala 29:58] - node mdccmect_ns = mux(_T_555, _T_557, _T_559) @[dec_tlu_ctl.scala 1874:30] - node _T_560 = or(wr_mdccmect_r, io.lsu_single_ecc_error_r_d1) @[dec_tlu_ctl.scala 1876:49] - node _T_561 = bits(_T_560, 0, 0) @[dec_tlu_ctl.scala 1876:81] + reg _T_552 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_552 <= miccmect_ns @[lib.scala 374:16] + miccmect <= _T_552 @[dec_tlu_ctl.scala 1861:11] + node _T_553 = bits(miccmect, 31, 27) @[dec_tlu_ctl.scala 1863:51] + node _T_554 = dshl(UInt<32>("h0ffffffff"), _T_553) @[dec_tlu_ctl.scala 1863:40] + node _T_555 = bits(miccmect, 26, 0) @[dec_tlu_ctl.scala 1863:84] + node _T_556 = cat(UInt<5>("h00"), _T_555) @[Cat.scala 29:58] + node _T_557 = and(_T_554, _T_556) @[dec_tlu_ctl.scala 1863:60] + node _T_558 = orr(_T_557) @[dec_tlu_ctl.scala 1863:93] + miccme_ce_req <= _T_558 @[dec_tlu_ctl.scala 1863:15] + node _T_559 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1872:69] + node _T_560 = eq(_T_559, UInt<12>("h07f2")) @[dec_tlu_ctl.scala 1872:76] + node wr_mdccmect_r = and(io.dec_csr_wen_r_mod, _T_560) @[dec_tlu_ctl.scala 1872:47] + node _T_561 = bits(mdccmect, 26, 0) @[dec_tlu_ctl.scala 1873:26] + node _T_562 = cat(UInt<26>("h00"), io.lsu_single_ecc_error_r_d1) @[Cat.scala 29:58] + node _T_563 = add(_T_561, _T_562) @[dec_tlu_ctl.scala 1873:33] + node _T_564 = tail(_T_563, 1) @[dec_tlu_ctl.scala 1873:33] + mdccmect_inc <= _T_564 @[dec_tlu_ctl.scala 1873:15] + node _T_565 = bits(wr_mdccmect_r, 0, 0) @[dec_tlu_ctl.scala 1874:45] + node _T_566 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1874:85] + node _T_567 = cat(csr_sat, _T_566) @[Cat.scala 29:58] + node _T_568 = bits(mdccmect, 31, 27) @[dec_tlu_ctl.scala 1874:107] + node _T_569 = cat(_T_568, mdccmect_inc) @[Cat.scala 29:58] + node mdccmect_ns = mux(_T_565, _T_567, _T_569) @[dec_tlu_ctl.scala 1874:30] + node _T_570 = or(wr_mdccmect_r, io.lsu_single_ecc_error_r_d1) @[dec_tlu_ctl.scala 1876:49] + node _T_571 = bits(_T_570, 0, 0) @[dec_tlu_ctl.scala 1876:81] inst rvclkhdr_14 of rvclkhdr_734 @[lib.scala 368:23] rvclkhdr_14.clock <= clock rvclkhdr_14.reset <= reset rvclkhdr_14.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_14.io.en <= _T_561 @[lib.scala 371:17] + rvclkhdr_14.io.en <= _T_571 @[lib.scala 371:17] rvclkhdr_14.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_562 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_562 <= mdccmect_ns @[lib.scala 374:16] - mdccmect <= _T_562 @[dec_tlu_ctl.scala 1876:11] - node _T_563 = bits(mdccmect, 31, 27) @[dec_tlu_ctl.scala 1878:52] - node _T_564 = dshl(UInt<32>("h0ffffffff"), _T_563) @[dec_tlu_ctl.scala 1878:41] - node _T_565 = bits(mdccmect, 26, 0) @[dec_tlu_ctl.scala 1878:85] - node _T_566 = cat(UInt<5>("h00"), _T_565) @[Cat.scala 29:58] - node _T_567 = and(_T_564, _T_566) @[dec_tlu_ctl.scala 1878:61] - node _T_568 = orr(_T_567) @[dec_tlu_ctl.scala 1878:94] - mdccme_ce_req <= _T_568 @[dec_tlu_ctl.scala 1878:16] - node _T_569 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1888:62] - node _T_570 = eq(_T_569, UInt<12>("h07ce")) @[dec_tlu_ctl.scala 1888:69] - node wr_mfdht_r = and(io.dec_csr_wen_r_mod, _T_570) @[dec_tlu_ctl.scala 1888:40] - node _T_571 = bits(wr_mfdht_r, 0, 0) @[dec_tlu_ctl.scala 1890:32] - node _T_572 = bits(io.dec_csr_wrdata_r, 5, 0) @[dec_tlu_ctl.scala 1890:59] - node mfdht_ns = mux(_T_571, _T_572, mfdht) @[dec_tlu_ctl.scala 1890:20] - reg _T_573 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1892:43] - _T_573 <= mfdht_ns @[dec_tlu_ctl.scala 1892:43] - mfdht <= _T_573 @[dec_tlu_ctl.scala 1892:8] - node _T_574 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1901:62] - node _T_575 = eq(_T_574, UInt<12>("h07cf")) @[dec_tlu_ctl.scala 1901:69] - node wr_mfdhs_r = and(io.dec_csr_wen_r_mod, _T_575) @[dec_tlu_ctl.scala 1901:40] - node _T_576 = bits(wr_mfdhs_r, 0, 0) @[dec_tlu_ctl.scala 1903:32] - node _T_577 = bits(io.dec_csr_wrdata_r, 1, 0) @[dec_tlu_ctl.scala 1903:60] - node _T_578 = not(io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 1904:43] - node _T_579 = and(io.dbg_tlu_halted, _T_578) @[dec_tlu_ctl.scala 1904:41] - node _T_580 = bits(_T_579, 0, 0) @[dec_tlu_ctl.scala 1904:65] - node _T_581 = not(io.lsu_idle_any_f) @[dec_tlu_ctl.scala 1904:78] - node _T_582 = not(io.ifu_miss_state_idle_f) @[dec_tlu_ctl.scala 1904:98] - node _T_583 = cat(_T_581, _T_582) @[Cat.scala 29:58] - node _T_584 = mux(_T_580, _T_583, mfdhs) @[dec_tlu_ctl.scala 1904:21] - node mfdhs_ns = mux(_T_576, _T_577, _T_584) @[dec_tlu_ctl.scala 1903:20] - node _T_585 = or(wr_mfdhs_r, io.dbg_tlu_halted) @[dec_tlu_ctl.scala 1906:71] - node _T_586 = bits(_T_585, 0, 0) @[dec_tlu_ctl.scala 1906:92] - reg _T_587 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_586 : @[Reg.scala 28:19] - _T_587 <= mfdhs_ns @[Reg.scala 28:23] + reg _T_572 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_572 <= mdccmect_ns @[lib.scala 374:16] + mdccmect <= _T_572 @[dec_tlu_ctl.scala 1876:11] + node _T_573 = bits(mdccmect, 31, 27) @[dec_tlu_ctl.scala 1878:52] + node _T_574 = dshl(UInt<32>("h0ffffffff"), _T_573) @[dec_tlu_ctl.scala 1878:41] + node _T_575 = bits(mdccmect, 26, 0) @[dec_tlu_ctl.scala 1878:85] + node _T_576 = cat(UInt<5>("h00"), _T_575) @[Cat.scala 29:58] + node _T_577 = and(_T_574, _T_576) @[dec_tlu_ctl.scala 1878:61] + node _T_578 = orr(_T_577) @[dec_tlu_ctl.scala 1878:94] + mdccme_ce_req <= _T_578 @[dec_tlu_ctl.scala 1878:16] + node _T_579 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1888:62] + node _T_580 = eq(_T_579, UInt<12>("h07ce")) @[dec_tlu_ctl.scala 1888:69] + node wr_mfdht_r = and(io.dec_csr_wen_r_mod, _T_580) @[dec_tlu_ctl.scala 1888:40] + node _T_581 = bits(wr_mfdht_r, 0, 0) @[dec_tlu_ctl.scala 1890:32] + node _T_582 = bits(io.dec_csr_wrdata_r, 5, 0) @[dec_tlu_ctl.scala 1890:59] + node mfdht_ns = mux(_T_581, _T_582, mfdht) @[dec_tlu_ctl.scala 1890:20] + reg _T_583 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1892:43] + _T_583 <= mfdht_ns @[dec_tlu_ctl.scala 1892:43] + mfdht <= _T_583 @[dec_tlu_ctl.scala 1892:8] + node _T_584 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1901:62] + node _T_585 = eq(_T_584, UInt<12>("h07cf")) @[dec_tlu_ctl.scala 1901:69] + node wr_mfdhs_r = and(io.dec_csr_wen_r_mod, _T_585) @[dec_tlu_ctl.scala 1901:40] + node _T_586 = bits(wr_mfdhs_r, 0, 0) @[dec_tlu_ctl.scala 1903:32] + node _T_587 = bits(io.dec_csr_wrdata_r, 1, 0) @[dec_tlu_ctl.scala 1903:60] + node _T_588 = not(io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 1904:43] + node _T_589 = and(io.dbg_tlu_halted, _T_588) @[dec_tlu_ctl.scala 1904:41] + node _T_590 = bits(_T_589, 0, 0) @[dec_tlu_ctl.scala 1904:65] + node _T_591 = not(io.lsu_idle_any_f) @[dec_tlu_ctl.scala 1904:78] + node _T_592 = not(io.ifu_miss_state_idle_f) @[dec_tlu_ctl.scala 1904:98] + node _T_593 = cat(_T_591, _T_592) @[Cat.scala 29:58] + node _T_594 = mux(_T_590, _T_593, mfdhs) @[dec_tlu_ctl.scala 1904:21] + node mfdhs_ns = mux(_T_586, _T_587, _T_594) @[dec_tlu_ctl.scala 1903:20] + node _T_595 = or(wr_mfdhs_r, io.dbg_tlu_halted) @[dec_tlu_ctl.scala 1906:71] + node _T_596 = bits(_T_595, 0, 0) @[dec_tlu_ctl.scala 1906:92] + reg _T_597 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_596 : @[Reg.scala 28:19] + _T_597 <= mfdhs_ns @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mfdhs <= _T_587 @[dec_tlu_ctl.scala 1906:8] - node _T_588 = bits(io.debug_halt_req_f, 0, 0) @[dec_tlu_ctl.scala 1908:47] - node _T_589 = add(force_halt_ctr_f, UInt<32>("h01")) @[dec_tlu_ctl.scala 1908:74] - node _T_590 = tail(_T_589, 1) @[dec_tlu_ctl.scala 1908:74] - node _T_591 = bits(io.dbg_tlu_halted_f, 0, 0) @[dec_tlu_ctl.scala 1909:48] - node _T_592 = mux(_T_591, UInt<32>("h00"), force_halt_ctr_f) @[dec_tlu_ctl.scala 1909:27] - node force_halt_ctr = mux(_T_588, _T_590, _T_592) @[dec_tlu_ctl.scala 1908:26] - node _T_593 = bits(mfdht, 0, 0) @[dec_tlu_ctl.scala 1911:81] - reg _T_594 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_593 : @[Reg.scala 28:19] - _T_594 <= force_halt_ctr @[Reg.scala 28:23] + mfdhs <= _T_597 @[dec_tlu_ctl.scala 1906:8] + node _T_598 = bits(io.debug_halt_req_f, 0, 0) @[dec_tlu_ctl.scala 1908:47] + node _T_599 = add(force_halt_ctr_f, UInt<32>("h01")) @[dec_tlu_ctl.scala 1908:74] + node _T_600 = tail(_T_599, 1) @[dec_tlu_ctl.scala 1908:74] + node _T_601 = bits(io.dbg_tlu_halted_f, 0, 0) @[dec_tlu_ctl.scala 1909:48] + node _T_602 = mux(_T_601, UInt<32>("h00"), force_halt_ctr_f) @[dec_tlu_ctl.scala 1909:27] + node force_halt_ctr = mux(_T_598, _T_600, _T_602) @[dec_tlu_ctl.scala 1908:26] + node _T_603 = bits(mfdht, 0, 0) @[dec_tlu_ctl.scala 1911:81] + reg _T_604 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_603 : @[Reg.scala 28:19] + _T_604 <= force_halt_ctr @[Reg.scala 28:23] skip @[Reg.scala 28:19] - force_halt_ctr_f <= _T_594 @[dec_tlu_ctl.scala 1911:19] - node _T_595 = bits(mfdht, 0, 0) @[dec_tlu_ctl.scala 1913:24] - node _T_596 = bits(mfdht, 5, 1) @[dec_tlu_ctl.scala 1913:79] - node _T_597 = dshl(UInt<32>("h0ffffffff"), _T_596) @[dec_tlu_ctl.scala 1913:71] - node _T_598 = and(force_halt_ctr_f, _T_597) @[dec_tlu_ctl.scala 1913:48] - node _T_599 = orr(_T_598) @[dec_tlu_ctl.scala 1913:87] - node _T_600 = and(_T_595, _T_599) @[dec_tlu_ctl.scala 1913:28] - io.force_halt <= _T_600 @[dec_tlu_ctl.scala 1913:16] - node _T_601 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1921:62] - node _T_602 = eq(_T_601, UInt<12>("h0bc8")) @[dec_tlu_ctl.scala 1921:69] - node wr_meivt_r = and(io.dec_csr_wen_r_mod, _T_602) @[dec_tlu_ctl.scala 1921:40] - node _T_603 = bits(io.dec_csr_wrdata_r, 31, 10) @[dec_tlu_ctl.scala 1923:40] - node _T_604 = bits(wr_meivt_r, 0, 0) @[dec_tlu_ctl.scala 1923:59] + force_halt_ctr_f <= _T_604 @[dec_tlu_ctl.scala 1911:19] + node _T_605 = bits(mfdht, 0, 0) @[dec_tlu_ctl.scala 1913:24] + node _T_606 = bits(mfdht, 5, 1) @[dec_tlu_ctl.scala 1913:79] + node _T_607 = dshl(UInt<32>("h0ffffffff"), _T_606) @[dec_tlu_ctl.scala 1913:71] + node _T_608 = and(force_halt_ctr_f, _T_607) @[dec_tlu_ctl.scala 1913:48] + node _T_609 = orr(_T_608) @[dec_tlu_ctl.scala 1913:87] + node _T_610 = and(_T_605, _T_609) @[dec_tlu_ctl.scala 1913:28] + io.force_halt <= _T_610 @[dec_tlu_ctl.scala 1913:16] + node _T_611 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1921:62] + node _T_612 = eq(_T_611, UInt<12>("h0bc8")) @[dec_tlu_ctl.scala 1921:69] + node wr_meivt_r = and(io.dec_csr_wen_r_mod, _T_612) @[dec_tlu_ctl.scala 1921:40] + node _T_613 = bits(io.dec_csr_wrdata_r, 31, 10) @[dec_tlu_ctl.scala 1923:40] + node _T_614 = bits(wr_meivt_r, 0, 0) @[dec_tlu_ctl.scala 1923:59] inst rvclkhdr_15 of rvclkhdr_735 @[lib.scala 368:23] rvclkhdr_15.clock <= clock rvclkhdr_15.reset <= reset rvclkhdr_15.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_15.io.en <= _T_604 @[lib.scala 371:17] + rvclkhdr_15.io.en <= _T_614 @[lib.scala 371:17] rvclkhdr_15.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg meivt : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - meivt <= _T_603 @[lib.scala 374:16] - node _T_605 = bits(wr_meicpct_r, 0, 0) @[dec_tlu_ctl.scala 1935:49] + meivt <= _T_613 @[lib.scala 374:16] + node _T_615 = bits(wr_meicpct_r, 0, 0) @[dec_tlu_ctl.scala 1935:49] inst rvclkhdr_16 of rvclkhdr_736 @[lib.scala 368:23] rvclkhdr_16.clock <= clock rvclkhdr_16.reset <= reset rvclkhdr_16.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_16.io.en <= _T_605 @[lib.scala 371:17] + rvclkhdr_16.io.en <= _T_615 @[lib.scala 371:17] rvclkhdr_16.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg meihap : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] meihap <= io.pic_claimid @[lib.scala 374:16] - node _T_606 = cat(meivt, meihap) @[Cat.scala 29:58] - io.dec_tlu_meihap <= _T_606 @[dec_tlu_ctl.scala 1936:20] - node _T_607 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1945:65] - node _T_608 = eq(_T_607, UInt<12>("h0bcc")) @[dec_tlu_ctl.scala 1945:72] - node wr_meicurpl_r = and(io.dec_csr_wen_r_mod, _T_608) @[dec_tlu_ctl.scala 1945:43] - node _T_609 = bits(wr_meicurpl_r, 0, 0) @[dec_tlu_ctl.scala 1946:38] - node _T_610 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1946:65] - node meicurpl_ns = mux(_T_609, _T_610, meicurpl) @[dec_tlu_ctl.scala 1946:23] - reg _T_611 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1948:46] - _T_611 <= meicurpl_ns @[dec_tlu_ctl.scala 1948:46] - meicurpl <= _T_611 @[dec_tlu_ctl.scala 1948:11] + node _T_616 = cat(meivt, meihap) @[Cat.scala 29:58] + io.dec_tlu_meihap <= _T_616 @[dec_tlu_ctl.scala 1936:20] + node _T_617 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1945:65] + node _T_618 = eq(_T_617, UInt<12>("h0bcc")) @[dec_tlu_ctl.scala 1945:72] + node wr_meicurpl_r = and(io.dec_csr_wen_r_mod, _T_618) @[dec_tlu_ctl.scala 1945:43] + node _T_619 = bits(wr_meicurpl_r, 0, 0) @[dec_tlu_ctl.scala 1946:38] + node _T_620 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1946:65] + node meicurpl_ns = mux(_T_619, _T_620, meicurpl) @[dec_tlu_ctl.scala 1946:23] + reg _T_621 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1948:46] + _T_621 <= meicurpl_ns @[dec_tlu_ctl.scala 1948:46] + meicurpl <= _T_621 @[dec_tlu_ctl.scala 1948:11] io.dec_tlu_meicurpl <= meicurpl @[dec_tlu_ctl.scala 1950:22] - node _T_612 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1960:66] - node _T_613 = eq(_T_612, UInt<12>("h0bcb")) @[dec_tlu_ctl.scala 1960:73] - node _T_614 = and(io.dec_csr_wen_r_mod, _T_613) @[dec_tlu_ctl.scala 1960:44] - node wr_meicidpl_r = or(_T_614, io.take_ext_int_start) @[dec_tlu_ctl.scala 1960:88] - node _T_615 = bits(wr_meicpct_r, 0, 0) @[dec_tlu_ctl.scala 1962:37] - node _T_616 = bits(wr_meicidpl_r, 0, 0) @[dec_tlu_ctl.scala 1963:38] - node _T_617 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1963:65] - node _T_618 = mux(_T_616, _T_617, meicidpl) @[dec_tlu_ctl.scala 1963:23] - node meicidpl_ns = mux(_T_615, io.pic_pl, _T_618) @[dec_tlu_ctl.scala 1962:23] - reg _T_619 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1965:44] - _T_619 <= meicidpl_ns @[dec_tlu_ctl.scala 1965:44] - meicidpl <= _T_619 @[dec_tlu_ctl.scala 1965:11] - node _T_620 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1972:62] - node _T_621 = eq(_T_620, UInt<12>("h0bca")) @[dec_tlu_ctl.scala 1972:69] - node _T_622 = and(io.dec_csr_wen_r_mod, _T_621) @[dec_tlu_ctl.scala 1972:40] - node _T_623 = or(_T_622, io.take_ext_int_start) @[dec_tlu_ctl.scala 1972:83] - wr_meicpct_r <= _T_623 @[dec_tlu_ctl.scala 1972:15] - node _T_624 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1981:62] - node _T_625 = eq(_T_624, UInt<12>("h0bc9")) @[dec_tlu_ctl.scala 1981:69] - node wr_meipt_r = and(io.dec_csr_wen_r_mod, _T_625) @[dec_tlu_ctl.scala 1981:40] - node _T_626 = bits(wr_meipt_r, 0, 0) @[dec_tlu_ctl.scala 1982:32] - node _T_627 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1982:59] - node meipt_ns = mux(_T_626, _T_627, meipt) @[dec_tlu_ctl.scala 1982:20] - reg _T_628 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1984:43] - _T_628 <= meipt_ns @[dec_tlu_ctl.scala 1984:43] - meipt <= _T_628 @[dec_tlu_ctl.scala 1984:8] + node _T_622 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1960:66] + node _T_623 = eq(_T_622, UInt<12>("h0bcb")) @[dec_tlu_ctl.scala 1960:73] + node _T_624 = and(io.dec_csr_wen_r_mod, _T_623) @[dec_tlu_ctl.scala 1960:44] + node wr_meicidpl_r = or(_T_624, io.take_ext_int_start) @[dec_tlu_ctl.scala 1960:88] + node _T_625 = bits(wr_meicpct_r, 0, 0) @[dec_tlu_ctl.scala 1962:37] + node _T_626 = bits(wr_meicidpl_r, 0, 0) @[dec_tlu_ctl.scala 1963:38] + node _T_627 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1963:65] + node _T_628 = mux(_T_626, _T_627, meicidpl) @[dec_tlu_ctl.scala 1963:23] + node meicidpl_ns = mux(_T_625, io.pic_pl, _T_628) @[dec_tlu_ctl.scala 1962:23] + reg _T_629 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1965:44] + _T_629 <= meicidpl_ns @[dec_tlu_ctl.scala 1965:44] + meicidpl <= _T_629 @[dec_tlu_ctl.scala 1965:11] + node _T_630 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1972:62] + node _T_631 = eq(_T_630, UInt<12>("h0bca")) @[dec_tlu_ctl.scala 1972:69] + node _T_632 = and(io.dec_csr_wen_r_mod, _T_631) @[dec_tlu_ctl.scala 1972:40] + node _T_633 = or(_T_632, io.take_ext_int_start) @[dec_tlu_ctl.scala 1972:83] + wr_meicpct_r <= _T_633 @[dec_tlu_ctl.scala 1972:15] + node _T_634 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1981:62] + node _T_635 = eq(_T_634, UInt<12>("h0bc9")) @[dec_tlu_ctl.scala 1981:69] + node wr_meipt_r = and(io.dec_csr_wen_r_mod, _T_635) @[dec_tlu_ctl.scala 1981:40] + node _T_636 = bits(wr_meipt_r, 0, 0) @[dec_tlu_ctl.scala 1982:32] + node _T_637 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1982:59] + node meipt_ns = mux(_T_636, _T_637, meipt) @[dec_tlu_ctl.scala 1982:20] + reg _T_638 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1984:43] + _T_638 <= meipt_ns @[dec_tlu_ctl.scala 1984:43] + meipt <= _T_638 @[dec_tlu_ctl.scala 1984:8] io.dec_tlu_meipt <= meipt @[dec_tlu_ctl.scala 1986:19] - node _T_629 = and(io.trigger_hit_r_d1, io.dcsr_single_step_done_f) @[dec_tlu_ctl.scala 2012:89] - node trigger_hit_for_dscr_cause_r_d1 = or(io.trigger_hit_dmode_r_d1, _T_629) @[dec_tlu_ctl.scala 2012:66] - node _T_630 = not(io.ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 2015:31] - node _T_631 = and(io.dcsr_single_step_done_f, _T_630) @[dec_tlu_ctl.scala 2015:29] - node _T_632 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2015:63] - node _T_633 = and(_T_631, _T_632) @[dec_tlu_ctl.scala 2015:61] - node _T_634 = not(io.debug_halt_req) @[dec_tlu_ctl.scala 2015:98] - node _T_635 = and(_T_633, _T_634) @[dec_tlu_ctl.scala 2015:96] - node _T_636 = bits(_T_635, 0, 0) @[dec_tlu_ctl.scala 2015:118] - node _T_637 = not(io.ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 2016:48] - node _T_638 = and(io.debug_halt_req, _T_637) @[dec_tlu_ctl.scala 2016:46] - node _T_639 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2016:80] - node _T_640 = and(_T_638, _T_639) @[dec_tlu_ctl.scala 2016:78] - node _T_641 = bits(_T_640, 0, 0) @[dec_tlu_ctl.scala 2016:114] - node _T_642 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2017:77] - node _T_643 = and(io.ebreak_to_debug_mode_r_d1, _T_642) @[dec_tlu_ctl.scala 2017:75] - node _T_644 = bits(_T_643, 0, 0) @[dec_tlu_ctl.scala 2017:111] - node _T_645 = bits(trigger_hit_for_dscr_cause_r_d1, 0, 0) @[dec_tlu_ctl.scala 2018:108] - node _T_646 = mux(_T_636, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_647 = mux(_T_641, UInt<3>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_648 = mux(_T_644, UInt<3>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_649 = mux(_T_645, UInt<3>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_650 = or(_T_646, _T_647) @[Mux.scala 27:72] - node _T_651 = or(_T_650, _T_648) @[Mux.scala 27:72] - node _T_652 = or(_T_651, _T_649) @[Mux.scala 27:72] + node _T_639 = and(io.trigger_hit_r_d1, io.dcsr_single_step_done_f) @[dec_tlu_ctl.scala 2012:89] + node trigger_hit_for_dscr_cause_r_d1 = or(io.trigger_hit_dmode_r_d1, _T_639) @[dec_tlu_ctl.scala 2012:66] + node _T_640 = not(io.ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 2015:31] + node _T_641 = and(io.dcsr_single_step_done_f, _T_640) @[dec_tlu_ctl.scala 2015:29] + node _T_642 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2015:63] + node _T_643 = and(_T_641, _T_642) @[dec_tlu_ctl.scala 2015:61] + node _T_644 = not(io.debug_halt_req) @[dec_tlu_ctl.scala 2015:98] + node _T_645 = and(_T_643, _T_644) @[dec_tlu_ctl.scala 2015:96] + node _T_646 = bits(_T_645, 0, 0) @[dec_tlu_ctl.scala 2015:118] + node _T_647 = not(io.ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 2016:48] + node _T_648 = and(io.debug_halt_req, _T_647) @[dec_tlu_ctl.scala 2016:46] + node _T_649 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2016:80] + node _T_650 = and(_T_648, _T_649) @[dec_tlu_ctl.scala 2016:78] + node _T_651 = bits(_T_650, 0, 0) @[dec_tlu_ctl.scala 2016:114] + node _T_652 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2017:77] + node _T_653 = and(io.ebreak_to_debug_mode_r_d1, _T_652) @[dec_tlu_ctl.scala 2017:75] + node _T_654 = bits(_T_653, 0, 0) @[dec_tlu_ctl.scala 2017:111] + node _T_655 = bits(trigger_hit_for_dscr_cause_r_d1, 0, 0) @[dec_tlu_ctl.scala 2018:108] + node _T_656 = mux(_T_646, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_657 = mux(_T_651, UInt<3>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_658 = mux(_T_654, UInt<3>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_659 = mux(_T_655, UInt<3>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_660 = or(_T_656, _T_657) @[Mux.scala 27:72] + node _T_661 = or(_T_660, _T_658) @[Mux.scala 27:72] + node _T_662 = or(_T_661, _T_659) @[Mux.scala 27:72] wire dcsr_cause : UInt<3> @[Mux.scala 27:72] - dcsr_cause <= _T_652 @[Mux.scala 27:72] - node _T_653 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2020:46] - node _T_654 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2020:91] - node _T_655 = eq(_T_654, UInt<12>("h07b0")) @[dec_tlu_ctl.scala 2020:98] - node wr_dcsr_r = and(_T_653, _T_655) @[dec_tlu_ctl.scala 2020:69] - node _T_656 = bits(io.dcsr, 8, 6) @[dec_tlu_ctl.scala 2026:69] - node _T_657 = eq(_T_656, UInt<3>("h03")) @[dec_tlu_ctl.scala 2026:75] - node dcsr_cause_upgradeable = and(io.internal_dbg_halt_mode_f, _T_657) @[dec_tlu_ctl.scala 2026:59] - node _T_658 = not(io.dbg_tlu_halted) @[dec_tlu_ctl.scala 2027:59] - node _T_659 = or(_T_658, dcsr_cause_upgradeable) @[dec_tlu_ctl.scala 2027:78] - node enter_debug_halt_req_le = and(io.enter_debug_halt_req, _T_659) @[dec_tlu_ctl.scala 2027:56] + dcsr_cause <= _T_662 @[Mux.scala 27:72] + node _T_663 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2020:46] + node _T_664 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2020:91] + node _T_665 = eq(_T_664, UInt<12>("h07b0")) @[dec_tlu_ctl.scala 2020:98] + node wr_dcsr_r = and(_T_663, _T_665) @[dec_tlu_ctl.scala 2020:69] + node _T_666 = bits(io.dcsr, 8, 6) @[dec_tlu_ctl.scala 2026:69] + node _T_667 = eq(_T_666, UInt<3>("h03")) @[dec_tlu_ctl.scala 2026:75] + node dcsr_cause_upgradeable = and(io.internal_dbg_halt_mode_f, _T_667) @[dec_tlu_ctl.scala 2026:59] + node _T_668 = not(io.dbg_tlu_halted) @[dec_tlu_ctl.scala 2027:59] + node _T_669 = or(_T_668, dcsr_cause_upgradeable) @[dec_tlu_ctl.scala 2027:78] + node enter_debug_halt_req_le = and(io.enter_debug_halt_req, _T_669) @[dec_tlu_ctl.scala 2027:56] node nmi_in_debug_mode = and(io.nmi_int_detected_f, io.internal_dbg_halt_mode_f) @[dec_tlu_ctl.scala 2029:48] - node _T_660 = bits(enter_debug_halt_req_le, 0, 0) @[dec_tlu_ctl.scala 2030:44] - node _T_661 = bits(io.dcsr, 15, 9) @[dec_tlu_ctl.scala 2030:64] - node _T_662 = bits(io.dcsr, 5, 2) @[dec_tlu_ctl.scala 2030:91] - node _T_663 = cat(_T_662, UInt<2>("h03")) @[Cat.scala 29:58] - node _T_664 = cat(_T_661, dcsr_cause) @[Cat.scala 29:58] - node _T_665 = cat(_T_664, _T_663) @[Cat.scala 29:58] - node _T_666 = bits(wr_dcsr_r, 0, 0) @[dec_tlu_ctl.scala 2031:18] - node _T_667 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 2031:49] - node _T_668 = bits(io.dec_csr_wrdata_r, 11, 10) @[dec_tlu_ctl.scala 2031:84] - node _T_669 = bits(io.dcsr, 8, 6) @[dec_tlu_ctl.scala 2031:110] - node _T_670 = bits(io.dcsr, 3, 3) @[dec_tlu_ctl.scala 2031:154] - node _T_671 = or(nmi_in_debug_mode, _T_670) @[dec_tlu_ctl.scala 2031:145] - node _T_672 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 2031:178] + node _T_670 = bits(enter_debug_halt_req_le, 0, 0) @[dec_tlu_ctl.scala 2030:44] + node _T_671 = bits(io.dcsr, 15, 9) @[dec_tlu_ctl.scala 2030:64] + node _T_672 = bits(io.dcsr, 5, 2) @[dec_tlu_ctl.scala 2030:91] node _T_673 = cat(_T_672, UInt<2>("h03")) @[Cat.scala 29:58] - node _T_674 = cat(UInt<2>("h00"), _T_671) @[Cat.scala 29:58] + node _T_674 = cat(_T_671, dcsr_cause) @[Cat.scala 29:58] node _T_675 = cat(_T_674, _T_673) @[Cat.scala 29:58] - node _T_676 = cat(UInt<1>("h00"), _T_669) @[Cat.scala 29:58] - node _T_677 = cat(_T_667, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_678 = cat(_T_677, _T_668) @[Cat.scala 29:58] - node _T_679 = cat(_T_678, _T_676) @[Cat.scala 29:58] - node _T_680 = cat(_T_679, _T_675) @[Cat.scala 29:58] - node _T_681 = bits(io.dcsr, 15, 4) @[dec_tlu_ctl.scala 2031:211] - node _T_682 = bits(io.dcsr, 2, 2) @[dec_tlu_ctl.scala 2031:245] + node _T_676 = bits(wr_dcsr_r, 0, 0) @[dec_tlu_ctl.scala 2031:18] + node _T_677 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 2031:49] + node _T_678 = bits(io.dec_csr_wrdata_r, 11, 10) @[dec_tlu_ctl.scala 2031:84] + node _T_679 = bits(io.dcsr, 8, 6) @[dec_tlu_ctl.scala 2031:110] + node _T_680 = bits(io.dcsr, 3, 3) @[dec_tlu_ctl.scala 2031:154] + node _T_681 = or(nmi_in_debug_mode, _T_680) @[dec_tlu_ctl.scala 2031:145] + node _T_682 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 2031:178] node _T_683 = cat(_T_682, UInt<2>("h03")) @[Cat.scala 29:58] - node _T_684 = cat(_T_681, nmi_in_debug_mode) @[Cat.scala 29:58] + node _T_684 = cat(UInt<2>("h00"), _T_681) @[Cat.scala 29:58] node _T_685 = cat(_T_684, _T_683) @[Cat.scala 29:58] - node _T_686 = mux(_T_666, _T_680, _T_685) @[dec_tlu_ctl.scala 2031:7] - node dcsr_ns = mux(_T_660, _T_665, _T_686) @[dec_tlu_ctl.scala 2030:19] - node _T_687 = or(enter_debug_halt_req_le, wr_dcsr_r) @[dec_tlu_ctl.scala 2033:54] - node _T_688 = or(_T_687, io.internal_dbg_halt_mode) @[dec_tlu_ctl.scala 2033:66] - node _T_689 = or(_T_688, io.take_nmi) @[dec_tlu_ctl.scala 2033:94] - node _T_690 = bits(_T_689, 0, 0) @[dec_tlu_ctl.scala 2033:109] + node _T_686 = cat(UInt<1>("h00"), _T_679) @[Cat.scala 29:58] + node _T_687 = cat(_T_677, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_688 = cat(_T_687, _T_678) @[Cat.scala 29:58] + node _T_689 = cat(_T_688, _T_686) @[Cat.scala 29:58] + node _T_690 = cat(_T_689, _T_685) @[Cat.scala 29:58] + node _T_691 = bits(io.dcsr, 15, 4) @[dec_tlu_ctl.scala 2031:211] + node _T_692 = bits(io.dcsr, 2, 2) @[dec_tlu_ctl.scala 2031:245] + node _T_693 = cat(_T_692, UInt<2>("h03")) @[Cat.scala 29:58] + node _T_694 = cat(_T_691, nmi_in_debug_mode) @[Cat.scala 29:58] + node _T_695 = cat(_T_694, _T_693) @[Cat.scala 29:58] + node _T_696 = mux(_T_676, _T_690, _T_695) @[dec_tlu_ctl.scala 2031:7] + node dcsr_ns = mux(_T_670, _T_675, _T_696) @[dec_tlu_ctl.scala 2030:19] + node _T_697 = or(enter_debug_halt_req_le, wr_dcsr_r) @[dec_tlu_ctl.scala 2033:54] + node _T_698 = or(_T_697, io.internal_dbg_halt_mode) @[dec_tlu_ctl.scala 2033:66] + node _T_699 = or(_T_698, io.take_nmi) @[dec_tlu_ctl.scala 2033:94] + node _T_700 = bits(_T_699, 0, 0) @[dec_tlu_ctl.scala 2033:109] inst rvclkhdr_17 of rvclkhdr_737 @[lib.scala 368:23] rvclkhdr_17.clock <= clock rvclkhdr_17.reset <= reset rvclkhdr_17.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_17.io.en <= _T_690 @[lib.scala 371:17] + rvclkhdr_17.io.en <= _T_700 @[lib.scala 371:17] rvclkhdr_17.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_691 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_691 <= dcsr_ns @[lib.scala 374:16] - io.dcsr <= _T_691 @[dec_tlu_ctl.scala 2033:10] - node _T_692 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2041:45] - node _T_693 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2041:90] - node _T_694 = eq(_T_693, UInt<12>("h07b1")) @[dec_tlu_ctl.scala 2041:97] - node wr_dpc_r = and(_T_692, _T_694) @[dec_tlu_ctl.scala 2041:68] - node _T_695 = not(io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2042:44] - node _T_696 = and(io.dbg_tlu_halted, _T_695) @[dec_tlu_ctl.scala 2042:42] - node _T_697 = not(io.request_debug_mode_done) @[dec_tlu_ctl.scala 2042:67] - node dpc_capture_npc = and(_T_696, _T_697) @[dec_tlu_ctl.scala 2042:65] - node _T_698 = not(io.request_debug_mode_r) @[dec_tlu_ctl.scala 2046:21] - node _T_699 = not(dpc_capture_npc) @[dec_tlu_ctl.scala 2046:39] - node _T_700 = and(_T_698, _T_699) @[dec_tlu_ctl.scala 2046:37] - node _T_701 = and(_T_700, wr_dpc_r) @[dec_tlu_ctl.scala 2046:56] - node _T_702 = bits(_T_701, 0, 0) @[dec_tlu_ctl.scala 2046:68] - node _T_703 = bits(io.dec_csr_wrdata_r, 31, 1) @[dec_tlu_ctl.scala 2046:97] - node _T_704 = bits(io.request_debug_mode_r, 0, 0) @[dec_tlu_ctl.scala 2047:68] - node _T_705 = not(io.request_debug_mode_r) @[dec_tlu_ctl.scala 2048:33] - node _T_706 = and(_T_705, dpc_capture_npc) @[dec_tlu_ctl.scala 2048:49] - node _T_707 = bits(_T_706, 0, 0) @[dec_tlu_ctl.scala 2048:68] - node _T_708 = mux(_T_702, _T_703, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_709 = mux(_T_704, pc_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_710 = mux(_T_707, io.npc_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_711 = or(_T_708, _T_709) @[Mux.scala 27:72] - node _T_712 = or(_T_711, _T_710) @[Mux.scala 27:72] + reg _T_701 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_701 <= dcsr_ns @[lib.scala 374:16] + io.dcsr <= _T_701 @[dec_tlu_ctl.scala 2033:10] + node _T_702 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2041:45] + node _T_703 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2041:90] + node _T_704 = eq(_T_703, UInt<12>("h07b1")) @[dec_tlu_ctl.scala 2041:97] + node wr_dpc_r = and(_T_702, _T_704) @[dec_tlu_ctl.scala 2041:68] + node _T_705 = not(io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2042:44] + node _T_706 = and(io.dbg_tlu_halted, _T_705) @[dec_tlu_ctl.scala 2042:42] + node _T_707 = not(io.request_debug_mode_done) @[dec_tlu_ctl.scala 2042:67] + node dpc_capture_npc = and(_T_706, _T_707) @[dec_tlu_ctl.scala 2042:65] + node _T_708 = not(io.request_debug_mode_r) @[dec_tlu_ctl.scala 2046:21] + node _T_709 = not(dpc_capture_npc) @[dec_tlu_ctl.scala 2046:39] + node _T_710 = and(_T_708, _T_709) @[dec_tlu_ctl.scala 2046:37] + node _T_711 = and(_T_710, wr_dpc_r) @[dec_tlu_ctl.scala 2046:56] + node _T_712 = bits(_T_711, 0, 0) @[dec_tlu_ctl.scala 2046:68] + node _T_713 = bits(io.dec_csr_wrdata_r, 31, 1) @[dec_tlu_ctl.scala 2046:97] + node _T_714 = bits(io.request_debug_mode_r, 0, 0) @[dec_tlu_ctl.scala 2047:68] + node _T_715 = not(io.request_debug_mode_r) @[dec_tlu_ctl.scala 2048:33] + node _T_716 = and(_T_715, dpc_capture_npc) @[dec_tlu_ctl.scala 2048:49] + node _T_717 = bits(_T_716, 0, 0) @[dec_tlu_ctl.scala 2048:68] + node _T_718 = mux(_T_712, _T_713, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_719 = mux(_T_714, pc_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_720 = mux(_T_717, io.npc_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_721 = or(_T_718, _T_719) @[Mux.scala 27:72] + node _T_722 = or(_T_721, _T_720) @[Mux.scala 27:72] wire dpc_ns : UInt<31> @[Mux.scala 27:72] - dpc_ns <= _T_712 @[Mux.scala 27:72] - node _T_713 = or(wr_dpc_r, io.request_debug_mode_r) @[dec_tlu_ctl.scala 2050:36] - node _T_714 = or(_T_713, dpc_capture_npc) @[dec_tlu_ctl.scala 2050:53] - node _T_715 = bits(_T_714, 0, 0) @[dec_tlu_ctl.scala 2050:72] + dpc_ns <= _T_722 @[Mux.scala 27:72] + node _T_723 = or(wr_dpc_r, io.request_debug_mode_r) @[dec_tlu_ctl.scala 2050:36] + node _T_724 = or(_T_723, dpc_capture_npc) @[dec_tlu_ctl.scala 2050:53] + node _T_725 = bits(_T_724, 0, 0) @[dec_tlu_ctl.scala 2050:72] inst rvclkhdr_18 of rvclkhdr_738 @[lib.scala 368:23] rvclkhdr_18.clock <= clock rvclkhdr_18.reset <= reset rvclkhdr_18.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_18.io.en <= _T_715 @[lib.scala 371:17] + rvclkhdr_18.io.en <= _T_725 @[lib.scala 371:17] rvclkhdr_18.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_716 : UInt, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_716 <= dpc_ns @[lib.scala 374:16] - io.dpc <= _T_716 @[dec_tlu_ctl.scala 2050:9] - node _T_717 = bits(io.dec_csr_wrdata_r, 24, 24) @[dec_tlu_ctl.scala 2064:43] - node _T_718 = bits(io.dec_csr_wrdata_r, 21, 20) @[dec_tlu_ctl.scala 2064:68] - node _T_719 = bits(io.dec_csr_wrdata_r, 16, 3) @[dec_tlu_ctl.scala 2064:96] - node _T_720 = cat(_T_717, _T_718) @[Cat.scala 29:58] - node dicawics_ns = cat(_T_720, _T_719) @[Cat.scala 29:58] - node _T_721 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2065:50] - node _T_722 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2065:95] - node _T_723 = eq(_T_722, UInt<12>("h07c8")) @[dec_tlu_ctl.scala 2065:102] - node wr_dicawics_r = and(_T_721, _T_723) @[dec_tlu_ctl.scala 2065:73] - node _T_724 = bits(wr_dicawics_r, 0, 0) @[dec_tlu_ctl.scala 2067:50] + reg _T_726 : UInt, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_726 <= dpc_ns @[lib.scala 374:16] + io.dpc <= _T_726 @[dec_tlu_ctl.scala 2050:9] + node _T_727 = bits(io.dec_csr_wrdata_r, 24, 24) @[dec_tlu_ctl.scala 2064:43] + node _T_728 = bits(io.dec_csr_wrdata_r, 21, 20) @[dec_tlu_ctl.scala 2064:68] + node _T_729 = bits(io.dec_csr_wrdata_r, 16, 3) @[dec_tlu_ctl.scala 2064:96] + node _T_730 = cat(_T_727, _T_728) @[Cat.scala 29:58] + node dicawics_ns = cat(_T_730, _T_729) @[Cat.scala 29:58] + node _T_731 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2065:50] + node _T_732 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2065:95] + node _T_733 = eq(_T_732, UInt<12>("h07c8")) @[dec_tlu_ctl.scala 2065:102] + node wr_dicawics_r = and(_T_731, _T_733) @[dec_tlu_ctl.scala 2065:73] + node _T_734 = bits(wr_dicawics_r, 0, 0) @[dec_tlu_ctl.scala 2067:50] inst rvclkhdr_19 of rvclkhdr_739 @[lib.scala 368:23] rvclkhdr_19.clock <= clock rvclkhdr_19.reset <= reset rvclkhdr_19.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_19.io.en <= _T_724 @[lib.scala 371:17] + rvclkhdr_19.io.en <= _T_734 @[lib.scala 371:17] rvclkhdr_19.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg dicawics : UInt, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] dicawics <= dicawics_ns @[lib.scala 374:16] - node _T_725 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2083:48] - node _T_726 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2083:93] - node _T_727 = eq(_T_726, UInt<12>("h07c9")) @[dec_tlu_ctl.scala 2083:100] - node wr_dicad0_r = and(_T_725, _T_727) @[dec_tlu_ctl.scala 2083:71] - node _T_728 = bits(wr_dicad0_r, 0, 0) @[dec_tlu_ctl.scala 2084:34] - node dicad0_ns = mux(_T_728, io.dec_csr_wrdata_r, io.ifu_ic_debug_rd_data) @[dec_tlu_ctl.scala 2084:21] - node _T_729 = or(wr_dicad0_r, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2086:46] - node _T_730 = bits(_T_729, 0, 0) @[dec_tlu_ctl.scala 2086:79] + node _T_735 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2083:48] + node _T_736 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2083:93] + node _T_737 = eq(_T_736, UInt<12>("h07c9")) @[dec_tlu_ctl.scala 2083:100] + node wr_dicad0_r = and(_T_735, _T_737) @[dec_tlu_ctl.scala 2083:71] + node _T_738 = bits(wr_dicad0_r, 0, 0) @[dec_tlu_ctl.scala 2084:34] + node dicad0_ns = mux(_T_738, io.dec_csr_wrdata_r, io.ifu_ic_debug_rd_data) @[dec_tlu_ctl.scala 2084:21] + node _T_739 = or(wr_dicad0_r, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2086:46] + node _T_740 = bits(_T_739, 0, 0) @[dec_tlu_ctl.scala 2086:79] inst rvclkhdr_20 of rvclkhdr_740 @[lib.scala 368:23] rvclkhdr_20.clock <= clock rvclkhdr_20.reset <= reset rvclkhdr_20.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_20.io.en <= _T_730 @[lib.scala 371:17] + rvclkhdr_20.io.en <= _T_740 @[lib.scala 371:17] rvclkhdr_20.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg dicad0 : UInt, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] dicad0 <= dicad0_ns @[lib.scala 374:16] - node _T_731 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2096:49] - node _T_732 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2096:94] - node _T_733 = eq(_T_732, UInt<12>("h07cc")) @[dec_tlu_ctl.scala 2096:101] - node wr_dicad0h_r = and(_T_731, _T_733) @[dec_tlu_ctl.scala 2096:72] - node _T_734 = bits(wr_dicad0h_r, 0, 0) @[dec_tlu_ctl.scala 2098:36] - node _T_735 = bits(io.ifu_ic_debug_rd_data, 63, 32) @[dec_tlu_ctl.scala 2098:88] - node dicad0h_ns = mux(_T_734, io.dec_csr_wrdata_r, _T_735) @[dec_tlu_ctl.scala 2098:22] - node _T_736 = or(wr_dicad0h_r, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2100:48] - node _T_737 = bits(_T_736, 0, 0) @[dec_tlu_ctl.scala 2100:81] + node _T_741 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2096:49] + node _T_742 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2096:94] + node _T_743 = eq(_T_742, UInt<12>("h07cc")) @[dec_tlu_ctl.scala 2096:101] + node wr_dicad0h_r = and(_T_741, _T_743) @[dec_tlu_ctl.scala 2096:72] + node _T_744 = bits(wr_dicad0h_r, 0, 0) @[dec_tlu_ctl.scala 2098:36] + node _T_745 = bits(io.ifu_ic_debug_rd_data, 63, 32) @[dec_tlu_ctl.scala 2098:88] + node dicad0h_ns = mux(_T_744, io.dec_csr_wrdata_r, _T_745) @[dec_tlu_ctl.scala 2098:22] + node _T_746 = or(wr_dicad0h_r, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2100:48] + node _T_747 = bits(_T_746, 0, 0) @[dec_tlu_ctl.scala 2100:81] inst rvclkhdr_21 of rvclkhdr_741 @[lib.scala 368:23] rvclkhdr_21.clock <= clock rvclkhdr_21.reset <= reset rvclkhdr_21.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_21.io.en <= _T_737 @[lib.scala 371:17] + rvclkhdr_21.io.en <= _T_747 @[lib.scala 371:17] rvclkhdr_21.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg dicad0h : UInt, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] dicad0h <= dicad0h_ns @[lib.scala 374:16] - wire _T_738 : UInt<7> - _T_738 <= UInt<1>("h00") - node _T_739 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2108:48] - node _T_740 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2108:93] - node _T_741 = eq(_T_740, UInt<12>("h07ca")) @[dec_tlu_ctl.scala 2108:100] - node _T_742 = and(_T_739, _T_741) @[dec_tlu_ctl.scala 2108:71] - node _T_743 = bits(_T_742, 0, 0) @[dec_tlu_ctl.scala 2110:34] - node _T_744 = bits(io.ifu_ic_debug_rd_data, 70, 64) @[dec_tlu_ctl.scala 2110:86] - node _T_745 = mux(_T_743, io.dec_csr_wrdata_r, _T_744) @[dec_tlu_ctl.scala 2110:21] - node _T_746 = or(_T_742, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2113:78] - node _T_747 = bits(_T_746, 0, 0) @[dec_tlu_ctl.scala 2113:111] - reg _T_748 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_747 : @[Reg.scala 28:19] - _T_748 <= _T_745 @[Reg.scala 28:23] + wire _T_748 : UInt<7> + _T_748 <= UInt<1>("h00") + node _T_749 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2108:48] + node _T_750 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2108:93] + node _T_751 = eq(_T_750, UInt<12>("h07ca")) @[dec_tlu_ctl.scala 2108:100] + node _T_752 = and(_T_749, _T_751) @[dec_tlu_ctl.scala 2108:71] + node _T_753 = bits(_T_752, 0, 0) @[dec_tlu_ctl.scala 2110:34] + node _T_754 = bits(io.ifu_ic_debug_rd_data, 70, 64) @[dec_tlu_ctl.scala 2110:86] + node _T_755 = mux(_T_753, io.dec_csr_wrdata_r, _T_754) @[dec_tlu_ctl.scala 2110:21] + node _T_756 = or(_T_752, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2113:78] + node _T_757 = bits(_T_756, 0, 0) @[dec_tlu_ctl.scala 2113:111] + reg _T_758 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_757 : @[Reg.scala 28:19] + _T_758 <= _T_755 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - _T_738 <= _T_748 @[dec_tlu_ctl.scala 2113:13] - node _T_749 = cat(UInt<25>("h00"), _T_738) @[Cat.scala 29:58] - dicad1 <= _T_749 @[dec_tlu_ctl.scala 2114:9] - node _T_750 = bits(dicad1, 6, 0) @[dec_tlu_ctl.scala 2136:69] - node _T_751 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2136:83] - node _T_752 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2136:97] - node _T_753 = cat(_T_750, _T_751) @[Cat.scala 29:58] - node _T_754 = cat(_T_753, _T_752) @[Cat.scala 29:58] - io.dec_tlu_ic_diag_pkt.icache_wrdata <= _T_754 @[dec_tlu_ctl.scala 2136:56] + _T_748 <= _T_758 @[dec_tlu_ctl.scala 2113:13] + node _T_759 = cat(UInt<25>("h00"), _T_748) @[Cat.scala 29:58] + dicad1 <= _T_759 @[dec_tlu_ctl.scala 2114:9] + node _T_760 = bits(dicad1, 6, 0) @[dec_tlu_ctl.scala 2136:69] + node _T_761 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2136:83] + node _T_762 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2136:97] + node _T_763 = cat(_T_760, _T_761) @[Cat.scala 29:58] + node _T_764 = cat(_T_763, _T_762) @[Cat.scala 29:58] + io.dec_tlu_ic_diag_pkt.icache_wrdata <= _T_764 @[dec_tlu_ctl.scala 2136:56] io.dec_tlu_ic_diag_pkt.icache_dicawics <= dicawics @[dec_tlu_ctl.scala 2139:41] - node _T_755 = and(io.allow_dbg_halt_csr_write, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 2141:52] - node _T_756 = and(_T_755, io.dec_i0_decode_d) @[dec_tlu_ctl.scala 2141:75] - node _T_757 = not(io.dec_csr_wen_unq_d) @[dec_tlu_ctl.scala 2141:98] - node _T_758 = and(_T_756, _T_757) @[dec_tlu_ctl.scala 2141:96] - node _T_759 = bits(io.dec_csr_rdaddr_d, 11, 0) @[dec_tlu_ctl.scala 2141:142] - node _T_760 = eq(_T_759, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2141:149] - node icache_rd_valid = and(_T_758, _T_760) @[dec_tlu_ctl.scala 2141:120] - node _T_761 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2142:52] - node _T_762 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2142:97] - node _T_763 = eq(_T_762, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2142:104] - node icache_wr_valid = and(_T_761, _T_763) @[dec_tlu_ctl.scala 2142:75] + node _T_765 = and(io.allow_dbg_halt_csr_write, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 2141:52] + node _T_766 = and(_T_765, io.dec_i0_decode_d) @[dec_tlu_ctl.scala 2141:75] + node _T_767 = not(io.dec_csr_wen_unq_d) @[dec_tlu_ctl.scala 2141:98] + node _T_768 = and(_T_766, _T_767) @[dec_tlu_ctl.scala 2141:96] + node _T_769 = bits(io.dec_csr_rdaddr_d, 11, 0) @[dec_tlu_ctl.scala 2141:142] + node _T_770 = eq(_T_769, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2141:149] + node icache_rd_valid = and(_T_768, _T_770) @[dec_tlu_ctl.scala 2141:120] + node _T_771 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2142:52] + node _T_772 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2142:97] + node _T_773 = eq(_T_772, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2142:104] + node icache_wr_valid = and(_T_771, _T_773) @[dec_tlu_ctl.scala 2142:75] reg icache_rd_valid_f : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2144:58] icache_rd_valid_f <= icache_rd_valid @[dec_tlu_ctl.scala 2144:58] reg icache_wr_valid_f : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2145:58] icache_wr_valid_f <= icache_wr_valid @[dec_tlu_ctl.scala 2145:58] io.dec_tlu_ic_diag_pkt.icache_rd_valid <= icache_rd_valid_f @[dec_tlu_ctl.scala 2147:41] io.dec_tlu_ic_diag_pkt.icache_wr_valid <= icache_wr_valid_f @[dec_tlu_ctl.scala 2148:41] - node _T_764 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2156:62] - node _T_765 = eq(_T_764, UInt<12>("h07a0")) @[dec_tlu_ctl.scala 2156:69] - node wr_mtsel_r = and(io.dec_csr_wen_r_mod, _T_765) @[dec_tlu_ctl.scala 2156:40] - node _T_766 = bits(wr_mtsel_r, 0, 0) @[dec_tlu_ctl.scala 2157:32] - node _T_767 = bits(io.dec_csr_wrdata_r, 1, 0) @[dec_tlu_ctl.scala 2157:59] - node mtsel_ns = mux(_T_766, _T_767, mtsel) @[dec_tlu_ctl.scala 2157:20] - reg _T_768 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2159:43] - _T_768 <= mtsel_ns @[dec_tlu_ctl.scala 2159:43] - mtsel <= _T_768 @[dec_tlu_ctl.scala 2159:8] - node _T_769 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2194:38] - node _T_770 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2194:64] - node _T_771 = not(_T_770) @[dec_tlu_ctl.scala 2194:44] - node tdata_load = and(_T_769, _T_771) @[dec_tlu_ctl.scala 2194:42] - node _T_772 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 2196:40] - node _T_773 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2196:66] - node _T_774 = not(_T_773) @[dec_tlu_ctl.scala 2196:46] - node tdata_opcode = and(_T_772, _T_774) @[dec_tlu_ctl.scala 2196:44] - node _T_775 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2198:41] - node _T_776 = and(_T_775, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2198:46] - node _T_777 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 2198:90] - node tdata_action = and(_T_776, _T_777) @[dec_tlu_ctl.scala 2198:69] - node _T_778 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2200:47] - node _T_779 = and(_T_778, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2200:52] - node _T_780 = bits(io.dec_csr_wrdata_r, 20, 19) @[dec_tlu_ctl.scala 2200:94] - node _T_781 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 2200:136] - node _T_782 = bits(io.dec_csr_wrdata_r, 7, 6) @[dec_tlu_ctl.scala 2201:43] - node _T_783 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 2201:83] - node _T_784 = cat(_T_783, tdata_load) @[Cat.scala 29:58] - node _T_785 = cat(_T_782, tdata_opcode) @[Cat.scala 29:58] - node _T_786 = cat(_T_785, _T_784) @[Cat.scala 29:58] - node _T_787 = cat(tdata_action, _T_781) @[Cat.scala 29:58] - node _T_788 = cat(_T_779, _T_780) @[Cat.scala 29:58] - node _T_789 = cat(_T_788, _T_787) @[Cat.scala 29:58] - node tdata_wrdata_r = cat(_T_789, _T_786) @[Cat.scala 29:58] - node _T_790 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2204:92] - node _T_791 = eq(_T_790, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2204:99] - node _T_792 = and(io.dec_csr_wen_r_mod, _T_791) @[dec_tlu_ctl.scala 2204:70] - node _T_793 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2204:121] - node _T_794 = and(_T_792, _T_793) @[dec_tlu_ctl.scala 2204:112] - node _T_795 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2204:154] - node _T_796 = not(_T_795) @[dec_tlu_ctl.scala 2204:138] - node _T_797 = or(_T_796, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2204:170] - node _T_798 = and(_T_794, _T_797) @[dec_tlu_ctl.scala 2204:135] - node _T_799 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2204:92] - node _T_800 = eq(_T_799, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2204:99] - node _T_801 = and(io.dec_csr_wen_r_mod, _T_800) @[dec_tlu_ctl.scala 2204:70] - node _T_802 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2204:121] - node _T_803 = and(_T_801, _T_802) @[dec_tlu_ctl.scala 2204:112] - node _T_804 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2204:154] - node _T_805 = not(_T_804) @[dec_tlu_ctl.scala 2204:138] - node _T_806 = or(_T_805, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2204:170] - node _T_807 = and(_T_803, _T_806) @[dec_tlu_ctl.scala 2204:135] - node _T_808 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2204:92] - node _T_809 = eq(_T_808, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2204:99] - node _T_810 = and(io.dec_csr_wen_r_mod, _T_809) @[dec_tlu_ctl.scala 2204:70] - node _T_811 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2204:121] - node _T_812 = and(_T_810, _T_811) @[dec_tlu_ctl.scala 2204:112] - node _T_813 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2204:154] - node _T_814 = not(_T_813) @[dec_tlu_ctl.scala 2204:138] - node _T_815 = or(_T_814, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2204:170] - node _T_816 = and(_T_812, _T_815) @[dec_tlu_ctl.scala 2204:135] - node _T_817 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2204:92] - node _T_818 = eq(_T_817, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2204:99] - node _T_819 = and(io.dec_csr_wen_r_mod, _T_818) @[dec_tlu_ctl.scala 2204:70] - node _T_820 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2204:121] - node _T_821 = and(_T_819, _T_820) @[dec_tlu_ctl.scala 2204:112] - node _T_822 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2204:154] - node _T_823 = not(_T_822) @[dec_tlu_ctl.scala 2204:138] - node _T_824 = or(_T_823, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2204:170] - node _T_825 = and(_T_821, _T_824) @[dec_tlu_ctl.scala 2204:135] + node _T_774 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2156:62] + node _T_775 = eq(_T_774, UInt<12>("h07a0")) @[dec_tlu_ctl.scala 2156:69] + node wr_mtsel_r = and(io.dec_csr_wen_r_mod, _T_775) @[dec_tlu_ctl.scala 2156:40] + node _T_776 = bits(wr_mtsel_r, 0, 0) @[dec_tlu_ctl.scala 2157:32] + node _T_777 = bits(io.dec_csr_wrdata_r, 1, 0) @[dec_tlu_ctl.scala 2157:59] + node mtsel_ns = mux(_T_776, _T_777, mtsel) @[dec_tlu_ctl.scala 2157:20] + reg _T_778 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2159:43] + _T_778 <= mtsel_ns @[dec_tlu_ctl.scala 2159:43] + mtsel <= _T_778 @[dec_tlu_ctl.scala 2159:8] + node _T_779 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2194:38] + node _T_780 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2194:64] + node _T_781 = not(_T_780) @[dec_tlu_ctl.scala 2194:44] + node tdata_load = and(_T_779, _T_781) @[dec_tlu_ctl.scala 2194:42] + node _T_782 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 2196:40] + node _T_783 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2196:66] + node _T_784 = not(_T_783) @[dec_tlu_ctl.scala 2196:46] + node tdata_opcode = and(_T_782, _T_784) @[dec_tlu_ctl.scala 2196:44] + node _T_785 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2198:41] + node _T_786 = and(_T_785, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2198:46] + node _T_787 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 2198:90] + node tdata_action = and(_T_786, _T_787) @[dec_tlu_ctl.scala 2198:69] + node _T_788 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2200:47] + node _T_789 = and(_T_788, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2200:52] + node _T_790 = bits(io.dec_csr_wrdata_r, 20, 19) @[dec_tlu_ctl.scala 2200:94] + node _T_791 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 2200:136] + node _T_792 = bits(io.dec_csr_wrdata_r, 7, 6) @[dec_tlu_ctl.scala 2201:43] + node _T_793 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 2201:83] + node _T_794 = cat(_T_793, tdata_load) @[Cat.scala 29:58] + node _T_795 = cat(_T_792, tdata_opcode) @[Cat.scala 29:58] + node _T_796 = cat(_T_795, _T_794) @[Cat.scala 29:58] + node _T_797 = cat(tdata_action, _T_791) @[Cat.scala 29:58] + node _T_798 = cat(_T_789, _T_790) @[Cat.scala 29:58] + node _T_799 = cat(_T_798, _T_797) @[Cat.scala 29:58] + node tdata_wrdata_r = cat(_T_799, _T_796) @[Cat.scala 29:58] + node _T_800 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2204:92] + node _T_801 = eq(_T_800, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2204:99] + node _T_802 = and(io.dec_csr_wen_r_mod, _T_801) @[dec_tlu_ctl.scala 2204:70] + node _T_803 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2204:121] + node _T_804 = and(_T_802, _T_803) @[dec_tlu_ctl.scala 2204:112] + node _T_805 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2204:154] + node _T_806 = not(_T_805) @[dec_tlu_ctl.scala 2204:138] + node _T_807 = or(_T_806, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2204:170] + node _T_808 = and(_T_804, _T_807) @[dec_tlu_ctl.scala 2204:135] + node _T_809 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2204:92] + node _T_810 = eq(_T_809, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2204:99] + node _T_811 = and(io.dec_csr_wen_r_mod, _T_810) @[dec_tlu_ctl.scala 2204:70] + node _T_812 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2204:121] + node _T_813 = and(_T_811, _T_812) @[dec_tlu_ctl.scala 2204:112] + node _T_814 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2204:154] + node _T_815 = not(_T_814) @[dec_tlu_ctl.scala 2204:138] + node _T_816 = or(_T_815, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2204:170] + node _T_817 = and(_T_813, _T_816) @[dec_tlu_ctl.scala 2204:135] + node _T_818 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2204:92] + node _T_819 = eq(_T_818, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2204:99] + node _T_820 = and(io.dec_csr_wen_r_mod, _T_819) @[dec_tlu_ctl.scala 2204:70] + node _T_821 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2204:121] + node _T_822 = and(_T_820, _T_821) @[dec_tlu_ctl.scala 2204:112] + node _T_823 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2204:154] + node _T_824 = not(_T_823) @[dec_tlu_ctl.scala 2204:138] + node _T_825 = or(_T_824, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2204:170] + node _T_826 = and(_T_822, _T_825) @[dec_tlu_ctl.scala 2204:135] + node _T_827 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2204:92] + node _T_828 = eq(_T_827, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2204:99] + node _T_829 = and(io.dec_csr_wen_r_mod, _T_828) @[dec_tlu_ctl.scala 2204:70] + node _T_830 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2204:121] + node _T_831 = and(_T_829, _T_830) @[dec_tlu_ctl.scala 2204:112] + node _T_832 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2204:154] + node _T_833 = not(_T_832) @[dec_tlu_ctl.scala 2204:138] + node _T_834 = or(_T_833, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2204:170] + node _T_835 = and(_T_831, _T_834) @[dec_tlu_ctl.scala 2204:135] wire wr_mtdata1_t_r : UInt<1>[4] @[dec_tlu_ctl.scala 2204:42] - wr_mtdata1_t_r[0] <= _T_798 @[dec_tlu_ctl.scala 2204:42] - wr_mtdata1_t_r[1] <= _T_807 @[dec_tlu_ctl.scala 2204:42] - wr_mtdata1_t_r[2] <= _T_816 @[dec_tlu_ctl.scala 2204:42] - wr_mtdata1_t_r[3] <= _T_825 @[dec_tlu_ctl.scala 2204:42] - node _T_826 = bits(wr_mtdata1_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2205:68] - node _T_827 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2205:111] - node _T_828 = bits(io.update_hit_bit_r, 0, 0) @[dec_tlu_ctl.scala 2205:135] - node _T_829 = bits(io.mtdata1_t[0], 8, 8) @[dec_tlu_ctl.scala 2205:156] - node _T_830 = or(_T_828, _T_829) @[dec_tlu_ctl.scala 2205:139] - node _T_831 = bits(io.mtdata1_t[0], 7, 0) @[dec_tlu_ctl.scala 2205:176] - node _T_832 = cat(_T_827, _T_830) @[Cat.scala 29:58] - node _T_833 = cat(_T_832, _T_831) @[Cat.scala 29:58] - node _T_834 = mux(_T_826, tdata_wrdata_r, _T_833) @[dec_tlu_ctl.scala 2205:49] - node _T_835 = bits(wr_mtdata1_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2205:68] - node _T_836 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2205:111] - node _T_837 = bits(io.update_hit_bit_r, 1, 1) @[dec_tlu_ctl.scala 2205:135] - node _T_838 = bits(io.mtdata1_t[1], 8, 8) @[dec_tlu_ctl.scala 2205:156] - node _T_839 = or(_T_837, _T_838) @[dec_tlu_ctl.scala 2205:139] - node _T_840 = bits(io.mtdata1_t[1], 7, 0) @[dec_tlu_ctl.scala 2205:176] - node _T_841 = cat(_T_836, _T_839) @[Cat.scala 29:58] - node _T_842 = cat(_T_841, _T_840) @[Cat.scala 29:58] - node _T_843 = mux(_T_835, tdata_wrdata_r, _T_842) @[dec_tlu_ctl.scala 2205:49] - node _T_844 = bits(wr_mtdata1_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2205:68] - node _T_845 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2205:111] - node _T_846 = bits(io.update_hit_bit_r, 2, 2) @[dec_tlu_ctl.scala 2205:135] - node _T_847 = bits(io.mtdata1_t[2], 8, 8) @[dec_tlu_ctl.scala 2205:156] - node _T_848 = or(_T_846, _T_847) @[dec_tlu_ctl.scala 2205:139] - node _T_849 = bits(io.mtdata1_t[2], 7, 0) @[dec_tlu_ctl.scala 2205:176] - node _T_850 = cat(_T_845, _T_848) @[Cat.scala 29:58] - node _T_851 = cat(_T_850, _T_849) @[Cat.scala 29:58] - node _T_852 = mux(_T_844, tdata_wrdata_r, _T_851) @[dec_tlu_ctl.scala 2205:49] - node _T_853 = bits(wr_mtdata1_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2205:68] - node _T_854 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2205:111] - node _T_855 = bits(io.update_hit_bit_r, 3, 3) @[dec_tlu_ctl.scala 2205:135] - node _T_856 = bits(io.mtdata1_t[3], 8, 8) @[dec_tlu_ctl.scala 2205:156] - node _T_857 = or(_T_855, _T_856) @[dec_tlu_ctl.scala 2205:139] - node _T_858 = bits(io.mtdata1_t[3], 7, 0) @[dec_tlu_ctl.scala 2205:176] - node _T_859 = cat(_T_854, _T_857) @[Cat.scala 29:58] - node _T_860 = cat(_T_859, _T_858) @[Cat.scala 29:58] - node _T_861 = mux(_T_853, tdata_wrdata_r, _T_860) @[dec_tlu_ctl.scala 2205:49] + wr_mtdata1_t_r[0] <= _T_808 @[dec_tlu_ctl.scala 2204:42] + wr_mtdata1_t_r[1] <= _T_817 @[dec_tlu_ctl.scala 2204:42] + wr_mtdata1_t_r[2] <= _T_826 @[dec_tlu_ctl.scala 2204:42] + wr_mtdata1_t_r[3] <= _T_835 @[dec_tlu_ctl.scala 2204:42] + node _T_836 = bits(wr_mtdata1_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2205:68] + node _T_837 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2205:111] + node _T_838 = bits(io.update_hit_bit_r, 0, 0) @[dec_tlu_ctl.scala 2205:135] + node _T_839 = bits(io.mtdata1_t[0], 8, 8) @[dec_tlu_ctl.scala 2205:156] + node _T_840 = or(_T_838, _T_839) @[dec_tlu_ctl.scala 2205:139] + node _T_841 = bits(io.mtdata1_t[0], 7, 0) @[dec_tlu_ctl.scala 2205:176] + node _T_842 = cat(_T_837, _T_840) @[Cat.scala 29:58] + node _T_843 = cat(_T_842, _T_841) @[Cat.scala 29:58] + node _T_844 = mux(_T_836, tdata_wrdata_r, _T_843) @[dec_tlu_ctl.scala 2205:49] + node _T_845 = bits(wr_mtdata1_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2205:68] + node _T_846 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2205:111] + node _T_847 = bits(io.update_hit_bit_r, 1, 1) @[dec_tlu_ctl.scala 2205:135] + node _T_848 = bits(io.mtdata1_t[1], 8, 8) @[dec_tlu_ctl.scala 2205:156] + node _T_849 = or(_T_847, _T_848) @[dec_tlu_ctl.scala 2205:139] + node _T_850 = bits(io.mtdata1_t[1], 7, 0) @[dec_tlu_ctl.scala 2205:176] + node _T_851 = cat(_T_846, _T_849) @[Cat.scala 29:58] + node _T_852 = cat(_T_851, _T_850) @[Cat.scala 29:58] + node _T_853 = mux(_T_845, tdata_wrdata_r, _T_852) @[dec_tlu_ctl.scala 2205:49] + node _T_854 = bits(wr_mtdata1_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2205:68] + node _T_855 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2205:111] + node _T_856 = bits(io.update_hit_bit_r, 2, 2) @[dec_tlu_ctl.scala 2205:135] + node _T_857 = bits(io.mtdata1_t[2], 8, 8) @[dec_tlu_ctl.scala 2205:156] + node _T_858 = or(_T_856, _T_857) @[dec_tlu_ctl.scala 2205:139] + node _T_859 = bits(io.mtdata1_t[2], 7, 0) @[dec_tlu_ctl.scala 2205:176] + node _T_860 = cat(_T_855, _T_858) @[Cat.scala 29:58] + node _T_861 = cat(_T_860, _T_859) @[Cat.scala 29:58] + node _T_862 = mux(_T_854, tdata_wrdata_r, _T_861) @[dec_tlu_ctl.scala 2205:49] + node _T_863 = bits(wr_mtdata1_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2205:68] + node _T_864 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2205:111] + node _T_865 = bits(io.update_hit_bit_r, 3, 3) @[dec_tlu_ctl.scala 2205:135] + node _T_866 = bits(io.mtdata1_t[3], 8, 8) @[dec_tlu_ctl.scala 2205:156] + node _T_867 = or(_T_865, _T_866) @[dec_tlu_ctl.scala 2205:139] + node _T_868 = bits(io.mtdata1_t[3], 7, 0) @[dec_tlu_ctl.scala 2205:176] + node _T_869 = cat(_T_864, _T_867) @[Cat.scala 29:58] + node _T_870 = cat(_T_869, _T_868) @[Cat.scala 29:58] + node _T_871 = mux(_T_863, tdata_wrdata_r, _T_870) @[dec_tlu_ctl.scala 2205:49] wire mtdata1_t_ns : UInt<10>[4] @[dec_tlu_ctl.scala 2205:40] - mtdata1_t_ns[0] <= _T_834 @[dec_tlu_ctl.scala 2205:40] - mtdata1_t_ns[1] <= _T_843 @[dec_tlu_ctl.scala 2205:40] - mtdata1_t_ns[2] <= _T_852 @[dec_tlu_ctl.scala 2205:40] - mtdata1_t_ns[3] <= _T_861 @[dec_tlu_ctl.scala 2205:40] - reg _T_862 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2207:74] - _T_862 <= mtdata1_t_ns[0] @[dec_tlu_ctl.scala 2207:74] - io.mtdata1_t[0] <= _T_862 @[dec_tlu_ctl.scala 2207:39] - reg _T_863 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2207:74] - _T_863 <= mtdata1_t_ns[1] @[dec_tlu_ctl.scala 2207:74] - io.mtdata1_t[1] <= _T_863 @[dec_tlu_ctl.scala 2207:39] - reg _T_864 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2207:74] - _T_864 <= mtdata1_t_ns[2] @[dec_tlu_ctl.scala 2207:74] - io.mtdata1_t[2] <= _T_864 @[dec_tlu_ctl.scala 2207:39] - reg _T_865 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2207:74] - _T_865 <= mtdata1_t_ns[3] @[dec_tlu_ctl.scala 2207:74] - io.mtdata1_t[3] <= _T_865 @[dec_tlu_ctl.scala 2207:39] - node _T_866 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2210:58] - node _T_867 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2210:104] - node _T_868 = bits(io.mtdata1_t[0], 8, 7) @[dec_tlu_ctl.scala 2210:142] - node _T_869 = bits(io.mtdata1_t[0], 6, 5) @[dec_tlu_ctl.scala 2210:174] - node _T_870 = bits(io.mtdata1_t[0], 4, 3) @[dec_tlu_ctl.scala 2210:206] - node _T_871 = bits(io.mtdata1_t[0], 2, 0) @[dec_tlu_ctl.scala 2210:238] - node _T_872 = cat(UInt<3>("h00"), _T_871) @[Cat.scala 29:58] - node _T_873 = cat(_T_869, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_874 = cat(_T_873, _T_870) @[Cat.scala 29:58] - node _T_875 = cat(_T_874, _T_872) @[Cat.scala 29:58] - node _T_876 = cat(_T_868, UInt<6>("h00")) @[Cat.scala 29:58] - node _T_877 = cat(UInt<4>("h02"), _T_867) @[Cat.scala 29:58] - node _T_878 = cat(_T_877, UInt<6>("h01f")) @[Cat.scala 29:58] - node _T_879 = cat(_T_878, _T_876) @[Cat.scala 29:58] - node _T_880 = cat(_T_879, _T_875) @[Cat.scala 29:58] - node _T_881 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2210:58] - node _T_882 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2210:104] - node _T_883 = bits(io.mtdata1_t[1], 8, 7) @[dec_tlu_ctl.scala 2210:142] - node _T_884 = bits(io.mtdata1_t[1], 6, 5) @[dec_tlu_ctl.scala 2210:174] - node _T_885 = bits(io.mtdata1_t[1], 4, 3) @[dec_tlu_ctl.scala 2210:206] - node _T_886 = bits(io.mtdata1_t[1], 2, 0) @[dec_tlu_ctl.scala 2210:238] - node _T_887 = cat(UInt<3>("h00"), _T_886) @[Cat.scala 29:58] - node _T_888 = cat(_T_884, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_889 = cat(_T_888, _T_885) @[Cat.scala 29:58] - node _T_890 = cat(_T_889, _T_887) @[Cat.scala 29:58] - node _T_891 = cat(_T_883, UInt<6>("h00")) @[Cat.scala 29:58] - node _T_892 = cat(UInt<4>("h02"), _T_882) @[Cat.scala 29:58] - node _T_893 = cat(_T_892, UInt<6>("h01f")) @[Cat.scala 29:58] - node _T_894 = cat(_T_893, _T_891) @[Cat.scala 29:58] - node _T_895 = cat(_T_894, _T_890) @[Cat.scala 29:58] - node _T_896 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2210:58] - node _T_897 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2210:104] - node _T_898 = bits(io.mtdata1_t[2], 8, 7) @[dec_tlu_ctl.scala 2210:142] - node _T_899 = bits(io.mtdata1_t[2], 6, 5) @[dec_tlu_ctl.scala 2210:174] - node _T_900 = bits(io.mtdata1_t[2], 4, 3) @[dec_tlu_ctl.scala 2210:206] - node _T_901 = bits(io.mtdata1_t[2], 2, 0) @[dec_tlu_ctl.scala 2210:238] - node _T_902 = cat(UInt<3>("h00"), _T_901) @[Cat.scala 29:58] - node _T_903 = cat(_T_899, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_904 = cat(_T_903, _T_900) @[Cat.scala 29:58] - node _T_905 = cat(_T_904, _T_902) @[Cat.scala 29:58] - node _T_906 = cat(_T_898, UInt<6>("h00")) @[Cat.scala 29:58] - node _T_907 = cat(UInt<4>("h02"), _T_897) @[Cat.scala 29:58] - node _T_908 = cat(_T_907, UInt<6>("h01f")) @[Cat.scala 29:58] - node _T_909 = cat(_T_908, _T_906) @[Cat.scala 29:58] - node _T_910 = cat(_T_909, _T_905) @[Cat.scala 29:58] - node _T_911 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2210:58] - node _T_912 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2210:104] - node _T_913 = bits(io.mtdata1_t[3], 8, 7) @[dec_tlu_ctl.scala 2210:142] - node _T_914 = bits(io.mtdata1_t[3], 6, 5) @[dec_tlu_ctl.scala 2210:174] - node _T_915 = bits(io.mtdata1_t[3], 4, 3) @[dec_tlu_ctl.scala 2210:206] - node _T_916 = bits(io.mtdata1_t[3], 2, 0) @[dec_tlu_ctl.scala 2210:238] - node _T_917 = cat(UInt<3>("h00"), _T_916) @[Cat.scala 29:58] - node _T_918 = cat(_T_914, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_919 = cat(_T_918, _T_915) @[Cat.scala 29:58] - node _T_920 = cat(_T_919, _T_917) @[Cat.scala 29:58] - node _T_921 = cat(_T_913, UInt<6>("h00")) @[Cat.scala 29:58] - node _T_922 = cat(UInt<4>("h02"), _T_912) @[Cat.scala 29:58] - node _T_923 = cat(_T_922, UInt<6>("h01f")) @[Cat.scala 29:58] - node _T_924 = cat(_T_923, _T_921) @[Cat.scala 29:58] - node _T_925 = cat(_T_924, _T_920) @[Cat.scala 29:58] - node _T_926 = mux(_T_866, _T_880, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_927 = mux(_T_881, _T_895, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_928 = mux(_T_896, _T_910, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_929 = mux(_T_911, _T_925, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_930 = or(_T_926, _T_927) @[Mux.scala 27:72] - node _T_931 = or(_T_930, _T_928) @[Mux.scala 27:72] - node _T_932 = or(_T_931, _T_929) @[Mux.scala 27:72] + mtdata1_t_ns[0] <= _T_844 @[dec_tlu_ctl.scala 2205:40] + mtdata1_t_ns[1] <= _T_853 @[dec_tlu_ctl.scala 2205:40] + mtdata1_t_ns[2] <= _T_862 @[dec_tlu_ctl.scala 2205:40] + mtdata1_t_ns[3] <= _T_871 @[dec_tlu_ctl.scala 2205:40] + reg _T_872 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2207:74] + _T_872 <= mtdata1_t_ns[0] @[dec_tlu_ctl.scala 2207:74] + io.mtdata1_t[0] <= _T_872 @[dec_tlu_ctl.scala 2207:39] + reg _T_873 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2207:74] + _T_873 <= mtdata1_t_ns[1] @[dec_tlu_ctl.scala 2207:74] + io.mtdata1_t[1] <= _T_873 @[dec_tlu_ctl.scala 2207:39] + reg _T_874 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2207:74] + _T_874 <= mtdata1_t_ns[2] @[dec_tlu_ctl.scala 2207:74] + io.mtdata1_t[2] <= _T_874 @[dec_tlu_ctl.scala 2207:39] + reg _T_875 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2207:74] + _T_875 <= mtdata1_t_ns[3] @[dec_tlu_ctl.scala 2207:74] + io.mtdata1_t[3] <= _T_875 @[dec_tlu_ctl.scala 2207:39] + node _T_876 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2210:58] + node _T_877 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2210:104] + node _T_878 = bits(io.mtdata1_t[0], 8, 7) @[dec_tlu_ctl.scala 2210:142] + node _T_879 = bits(io.mtdata1_t[0], 6, 5) @[dec_tlu_ctl.scala 2210:174] + node _T_880 = bits(io.mtdata1_t[0], 4, 3) @[dec_tlu_ctl.scala 2210:206] + node _T_881 = bits(io.mtdata1_t[0], 2, 0) @[dec_tlu_ctl.scala 2210:238] + node _T_882 = cat(UInt<3>("h00"), _T_881) @[Cat.scala 29:58] + node _T_883 = cat(_T_879, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_884 = cat(_T_883, _T_880) @[Cat.scala 29:58] + node _T_885 = cat(_T_884, _T_882) @[Cat.scala 29:58] + node _T_886 = cat(_T_878, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_887 = cat(UInt<4>("h02"), _T_877) @[Cat.scala 29:58] + node _T_888 = cat(_T_887, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_889 = cat(_T_888, _T_886) @[Cat.scala 29:58] + node _T_890 = cat(_T_889, _T_885) @[Cat.scala 29:58] + node _T_891 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2210:58] + node _T_892 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2210:104] + node _T_893 = bits(io.mtdata1_t[1], 8, 7) @[dec_tlu_ctl.scala 2210:142] + node _T_894 = bits(io.mtdata1_t[1], 6, 5) @[dec_tlu_ctl.scala 2210:174] + node _T_895 = bits(io.mtdata1_t[1], 4, 3) @[dec_tlu_ctl.scala 2210:206] + node _T_896 = bits(io.mtdata1_t[1], 2, 0) @[dec_tlu_ctl.scala 2210:238] + node _T_897 = cat(UInt<3>("h00"), _T_896) @[Cat.scala 29:58] + node _T_898 = cat(_T_894, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_899 = cat(_T_898, _T_895) @[Cat.scala 29:58] + node _T_900 = cat(_T_899, _T_897) @[Cat.scala 29:58] + node _T_901 = cat(_T_893, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_902 = cat(UInt<4>("h02"), _T_892) @[Cat.scala 29:58] + node _T_903 = cat(_T_902, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_904 = cat(_T_903, _T_901) @[Cat.scala 29:58] + node _T_905 = cat(_T_904, _T_900) @[Cat.scala 29:58] + node _T_906 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2210:58] + node _T_907 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2210:104] + node _T_908 = bits(io.mtdata1_t[2], 8, 7) @[dec_tlu_ctl.scala 2210:142] + node _T_909 = bits(io.mtdata1_t[2], 6, 5) @[dec_tlu_ctl.scala 2210:174] + node _T_910 = bits(io.mtdata1_t[2], 4, 3) @[dec_tlu_ctl.scala 2210:206] + node _T_911 = bits(io.mtdata1_t[2], 2, 0) @[dec_tlu_ctl.scala 2210:238] + node _T_912 = cat(UInt<3>("h00"), _T_911) @[Cat.scala 29:58] + node _T_913 = cat(_T_909, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_914 = cat(_T_913, _T_910) @[Cat.scala 29:58] + node _T_915 = cat(_T_914, _T_912) @[Cat.scala 29:58] + node _T_916 = cat(_T_908, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_917 = cat(UInt<4>("h02"), _T_907) @[Cat.scala 29:58] + node _T_918 = cat(_T_917, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_919 = cat(_T_918, _T_916) @[Cat.scala 29:58] + node _T_920 = cat(_T_919, _T_915) @[Cat.scala 29:58] + node _T_921 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2210:58] + node _T_922 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2210:104] + node _T_923 = bits(io.mtdata1_t[3], 8, 7) @[dec_tlu_ctl.scala 2210:142] + node _T_924 = bits(io.mtdata1_t[3], 6, 5) @[dec_tlu_ctl.scala 2210:174] + node _T_925 = bits(io.mtdata1_t[3], 4, 3) @[dec_tlu_ctl.scala 2210:206] + node _T_926 = bits(io.mtdata1_t[3], 2, 0) @[dec_tlu_ctl.scala 2210:238] + node _T_927 = cat(UInt<3>("h00"), _T_926) @[Cat.scala 29:58] + node _T_928 = cat(_T_924, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_929 = cat(_T_928, _T_925) @[Cat.scala 29:58] + node _T_930 = cat(_T_929, _T_927) @[Cat.scala 29:58] + node _T_931 = cat(_T_923, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_932 = cat(UInt<4>("h02"), _T_922) @[Cat.scala 29:58] + node _T_933 = cat(_T_932, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_934 = cat(_T_933, _T_931) @[Cat.scala 29:58] + node _T_935 = cat(_T_934, _T_930) @[Cat.scala 29:58] + node _T_936 = mux(_T_876, _T_890, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_937 = mux(_T_891, _T_905, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_938 = mux(_T_906, _T_920, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_939 = mux(_T_921, _T_935, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_940 = or(_T_936, _T_937) @[Mux.scala 27:72] + node _T_941 = or(_T_940, _T_938) @[Mux.scala 27:72] + node _T_942 = or(_T_941, _T_939) @[Mux.scala 27:72] wire mtdata1_tsel_out : UInt<32> @[Mux.scala 27:72] - mtdata1_tsel_out <= _T_932 @[Mux.scala 27:72] - node _T_933 = bits(io.mtdata1_t[0], 7, 7) @[dec_tlu_ctl.scala 2212:58] - io.trigger_pkt_any[0].select <= _T_933 @[dec_tlu_ctl.scala 2212:40] - node _T_934 = bits(io.mtdata1_t[0], 4, 4) @[dec_tlu_ctl.scala 2213:61] - io.trigger_pkt_any[0].match_pkt <= _T_934 @[dec_tlu_ctl.scala 2213:43] - node _T_935 = bits(io.mtdata1_t[0], 1, 1) @[dec_tlu_ctl.scala 2214:58] - io.trigger_pkt_any[0].store <= _T_935 @[dec_tlu_ctl.scala 2214:40] - node _T_936 = bits(io.mtdata1_t[0], 0, 0) @[dec_tlu_ctl.scala 2215:58] - io.trigger_pkt_any[0].load <= _T_936 @[dec_tlu_ctl.scala 2215:40] - node _T_937 = bits(io.mtdata1_t[0], 2, 2) @[dec_tlu_ctl.scala 2216:58] - io.trigger_pkt_any[0].execute <= _T_937 @[dec_tlu_ctl.scala 2216:40] - node _T_938 = bits(io.mtdata1_t[0], 3, 3) @[dec_tlu_ctl.scala 2217:58] - io.trigger_pkt_any[0].m <= _T_938 @[dec_tlu_ctl.scala 2217:40] - node _T_939 = bits(io.mtdata1_t[1], 7, 7) @[dec_tlu_ctl.scala 2212:58] - io.trigger_pkt_any[1].select <= _T_939 @[dec_tlu_ctl.scala 2212:40] - node _T_940 = bits(io.mtdata1_t[1], 4, 4) @[dec_tlu_ctl.scala 2213:61] - io.trigger_pkt_any[1].match_pkt <= _T_940 @[dec_tlu_ctl.scala 2213:43] - node _T_941 = bits(io.mtdata1_t[1], 1, 1) @[dec_tlu_ctl.scala 2214:58] - io.trigger_pkt_any[1].store <= _T_941 @[dec_tlu_ctl.scala 2214:40] - node _T_942 = bits(io.mtdata1_t[1], 0, 0) @[dec_tlu_ctl.scala 2215:58] - io.trigger_pkt_any[1].load <= _T_942 @[dec_tlu_ctl.scala 2215:40] - node _T_943 = bits(io.mtdata1_t[1], 2, 2) @[dec_tlu_ctl.scala 2216:58] - io.trigger_pkt_any[1].execute <= _T_943 @[dec_tlu_ctl.scala 2216:40] - node _T_944 = bits(io.mtdata1_t[1], 3, 3) @[dec_tlu_ctl.scala 2217:58] - io.trigger_pkt_any[1].m <= _T_944 @[dec_tlu_ctl.scala 2217:40] - node _T_945 = bits(io.mtdata1_t[2], 7, 7) @[dec_tlu_ctl.scala 2212:58] - io.trigger_pkt_any[2].select <= _T_945 @[dec_tlu_ctl.scala 2212:40] - node _T_946 = bits(io.mtdata1_t[2], 4, 4) @[dec_tlu_ctl.scala 2213:61] - io.trigger_pkt_any[2].match_pkt <= _T_946 @[dec_tlu_ctl.scala 2213:43] - node _T_947 = bits(io.mtdata1_t[2], 1, 1) @[dec_tlu_ctl.scala 2214:58] - io.trigger_pkt_any[2].store <= _T_947 @[dec_tlu_ctl.scala 2214:40] - node _T_948 = bits(io.mtdata1_t[2], 0, 0) @[dec_tlu_ctl.scala 2215:58] - io.trigger_pkt_any[2].load <= _T_948 @[dec_tlu_ctl.scala 2215:40] - node _T_949 = bits(io.mtdata1_t[2], 2, 2) @[dec_tlu_ctl.scala 2216:58] - io.trigger_pkt_any[2].execute <= _T_949 @[dec_tlu_ctl.scala 2216:40] - node _T_950 = bits(io.mtdata1_t[2], 3, 3) @[dec_tlu_ctl.scala 2217:58] - io.trigger_pkt_any[2].m <= _T_950 @[dec_tlu_ctl.scala 2217:40] - node _T_951 = bits(io.mtdata1_t[3], 7, 7) @[dec_tlu_ctl.scala 2212:58] - io.trigger_pkt_any[3].select <= _T_951 @[dec_tlu_ctl.scala 2212:40] - node _T_952 = bits(io.mtdata1_t[3], 4, 4) @[dec_tlu_ctl.scala 2213:61] - io.trigger_pkt_any[3].match_pkt <= _T_952 @[dec_tlu_ctl.scala 2213:43] - node _T_953 = bits(io.mtdata1_t[3], 1, 1) @[dec_tlu_ctl.scala 2214:58] - io.trigger_pkt_any[3].store <= _T_953 @[dec_tlu_ctl.scala 2214:40] - node _T_954 = bits(io.mtdata1_t[3], 0, 0) @[dec_tlu_ctl.scala 2215:58] - io.trigger_pkt_any[3].load <= _T_954 @[dec_tlu_ctl.scala 2215:40] - node _T_955 = bits(io.mtdata1_t[3], 2, 2) @[dec_tlu_ctl.scala 2216:58] - io.trigger_pkt_any[3].execute <= _T_955 @[dec_tlu_ctl.scala 2216:40] - node _T_956 = bits(io.mtdata1_t[3], 3, 3) @[dec_tlu_ctl.scala 2217:58] - io.trigger_pkt_any[3].m <= _T_956 @[dec_tlu_ctl.scala 2217:40] - node _T_957 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2224:91] - node _T_958 = eq(_T_957, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2224:98] - node _T_959 = and(io.dec_csr_wen_r_mod, _T_958) @[dec_tlu_ctl.scala 2224:69] - node _T_960 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2224:120] - node _T_961 = and(_T_959, _T_960) @[dec_tlu_ctl.scala 2224:111] - node _T_962 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2224:153] - node _T_963 = not(_T_962) @[dec_tlu_ctl.scala 2224:137] - node _T_964 = or(_T_963, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2224:169] - node _T_965 = and(_T_961, _T_964) @[dec_tlu_ctl.scala 2224:134] - node _T_966 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2224:91] - node _T_967 = eq(_T_966, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2224:98] - node _T_968 = and(io.dec_csr_wen_r_mod, _T_967) @[dec_tlu_ctl.scala 2224:69] - node _T_969 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2224:120] - node _T_970 = and(_T_968, _T_969) @[dec_tlu_ctl.scala 2224:111] - node _T_971 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2224:153] - node _T_972 = not(_T_971) @[dec_tlu_ctl.scala 2224:137] - node _T_973 = or(_T_972, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2224:169] - node _T_974 = and(_T_970, _T_973) @[dec_tlu_ctl.scala 2224:134] - node _T_975 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2224:91] - node _T_976 = eq(_T_975, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2224:98] - node _T_977 = and(io.dec_csr_wen_r_mod, _T_976) @[dec_tlu_ctl.scala 2224:69] - node _T_978 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2224:120] - node _T_979 = and(_T_977, _T_978) @[dec_tlu_ctl.scala 2224:111] - node _T_980 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2224:153] - node _T_981 = not(_T_980) @[dec_tlu_ctl.scala 2224:137] - node _T_982 = or(_T_981, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2224:169] - node _T_983 = and(_T_979, _T_982) @[dec_tlu_ctl.scala 2224:134] - node _T_984 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2224:91] - node _T_985 = eq(_T_984, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2224:98] - node _T_986 = and(io.dec_csr_wen_r_mod, _T_985) @[dec_tlu_ctl.scala 2224:69] - node _T_987 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2224:120] - node _T_988 = and(_T_986, _T_987) @[dec_tlu_ctl.scala 2224:111] - node _T_989 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2224:153] - node _T_990 = not(_T_989) @[dec_tlu_ctl.scala 2224:137] - node _T_991 = or(_T_990, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2224:169] - node _T_992 = and(_T_988, _T_991) @[dec_tlu_ctl.scala 2224:134] + mtdata1_tsel_out <= _T_942 @[Mux.scala 27:72] + node _T_943 = bits(io.mtdata1_t[0], 7, 7) @[dec_tlu_ctl.scala 2212:58] + io.trigger_pkt_any[0].select <= _T_943 @[dec_tlu_ctl.scala 2212:40] + node _T_944 = bits(io.mtdata1_t[0], 4, 4) @[dec_tlu_ctl.scala 2213:61] + io.trigger_pkt_any[0].match_pkt <= _T_944 @[dec_tlu_ctl.scala 2213:43] + node _T_945 = bits(io.mtdata1_t[0], 1, 1) @[dec_tlu_ctl.scala 2214:58] + io.trigger_pkt_any[0].store <= _T_945 @[dec_tlu_ctl.scala 2214:40] + node _T_946 = bits(io.mtdata1_t[0], 0, 0) @[dec_tlu_ctl.scala 2215:58] + io.trigger_pkt_any[0].load <= _T_946 @[dec_tlu_ctl.scala 2215:40] + node _T_947 = bits(io.mtdata1_t[0], 2, 2) @[dec_tlu_ctl.scala 2216:58] + io.trigger_pkt_any[0].execute <= _T_947 @[dec_tlu_ctl.scala 2216:40] + node _T_948 = bits(io.mtdata1_t[0], 3, 3) @[dec_tlu_ctl.scala 2217:58] + io.trigger_pkt_any[0].m <= _T_948 @[dec_tlu_ctl.scala 2217:40] + node _T_949 = bits(io.mtdata1_t[1], 7, 7) @[dec_tlu_ctl.scala 2212:58] + io.trigger_pkt_any[1].select <= _T_949 @[dec_tlu_ctl.scala 2212:40] + node _T_950 = bits(io.mtdata1_t[1], 4, 4) @[dec_tlu_ctl.scala 2213:61] + io.trigger_pkt_any[1].match_pkt <= _T_950 @[dec_tlu_ctl.scala 2213:43] + node _T_951 = bits(io.mtdata1_t[1], 1, 1) @[dec_tlu_ctl.scala 2214:58] + io.trigger_pkt_any[1].store <= _T_951 @[dec_tlu_ctl.scala 2214:40] + node _T_952 = bits(io.mtdata1_t[1], 0, 0) @[dec_tlu_ctl.scala 2215:58] + io.trigger_pkt_any[1].load <= _T_952 @[dec_tlu_ctl.scala 2215:40] + node _T_953 = bits(io.mtdata1_t[1], 2, 2) @[dec_tlu_ctl.scala 2216:58] + io.trigger_pkt_any[1].execute <= _T_953 @[dec_tlu_ctl.scala 2216:40] + node _T_954 = bits(io.mtdata1_t[1], 3, 3) @[dec_tlu_ctl.scala 2217:58] + io.trigger_pkt_any[1].m <= _T_954 @[dec_tlu_ctl.scala 2217:40] + node _T_955 = bits(io.mtdata1_t[2], 7, 7) @[dec_tlu_ctl.scala 2212:58] + io.trigger_pkt_any[2].select <= _T_955 @[dec_tlu_ctl.scala 2212:40] + node _T_956 = bits(io.mtdata1_t[2], 4, 4) @[dec_tlu_ctl.scala 2213:61] + io.trigger_pkt_any[2].match_pkt <= _T_956 @[dec_tlu_ctl.scala 2213:43] + node _T_957 = bits(io.mtdata1_t[2], 1, 1) @[dec_tlu_ctl.scala 2214:58] + io.trigger_pkt_any[2].store <= _T_957 @[dec_tlu_ctl.scala 2214:40] + node _T_958 = bits(io.mtdata1_t[2], 0, 0) @[dec_tlu_ctl.scala 2215:58] + io.trigger_pkt_any[2].load <= _T_958 @[dec_tlu_ctl.scala 2215:40] + node _T_959 = bits(io.mtdata1_t[2], 2, 2) @[dec_tlu_ctl.scala 2216:58] + io.trigger_pkt_any[2].execute <= _T_959 @[dec_tlu_ctl.scala 2216:40] + node _T_960 = bits(io.mtdata1_t[2], 3, 3) @[dec_tlu_ctl.scala 2217:58] + io.trigger_pkt_any[2].m <= _T_960 @[dec_tlu_ctl.scala 2217:40] + node _T_961 = bits(io.mtdata1_t[3], 7, 7) @[dec_tlu_ctl.scala 2212:58] + io.trigger_pkt_any[3].select <= _T_961 @[dec_tlu_ctl.scala 2212:40] + node _T_962 = bits(io.mtdata1_t[3], 4, 4) @[dec_tlu_ctl.scala 2213:61] + io.trigger_pkt_any[3].match_pkt <= _T_962 @[dec_tlu_ctl.scala 2213:43] + node _T_963 = bits(io.mtdata1_t[3], 1, 1) @[dec_tlu_ctl.scala 2214:58] + io.trigger_pkt_any[3].store <= _T_963 @[dec_tlu_ctl.scala 2214:40] + node _T_964 = bits(io.mtdata1_t[3], 0, 0) @[dec_tlu_ctl.scala 2215:58] + io.trigger_pkt_any[3].load <= _T_964 @[dec_tlu_ctl.scala 2215:40] + node _T_965 = bits(io.mtdata1_t[3], 2, 2) @[dec_tlu_ctl.scala 2216:58] + io.trigger_pkt_any[3].execute <= _T_965 @[dec_tlu_ctl.scala 2216:40] + node _T_966 = bits(io.mtdata1_t[3], 3, 3) @[dec_tlu_ctl.scala 2217:58] + io.trigger_pkt_any[3].m <= _T_966 @[dec_tlu_ctl.scala 2217:40] + node _T_967 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2224:91] + node _T_968 = eq(_T_967, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2224:98] + node _T_969 = and(io.dec_csr_wen_r_mod, _T_968) @[dec_tlu_ctl.scala 2224:69] + node _T_970 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2224:120] + node _T_971 = and(_T_969, _T_970) @[dec_tlu_ctl.scala 2224:111] + node _T_972 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2224:153] + node _T_973 = not(_T_972) @[dec_tlu_ctl.scala 2224:137] + node _T_974 = or(_T_973, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2224:169] + node _T_975 = and(_T_971, _T_974) @[dec_tlu_ctl.scala 2224:134] + node _T_976 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2224:91] + node _T_977 = eq(_T_976, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2224:98] + node _T_978 = and(io.dec_csr_wen_r_mod, _T_977) @[dec_tlu_ctl.scala 2224:69] + node _T_979 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2224:120] + node _T_980 = and(_T_978, _T_979) @[dec_tlu_ctl.scala 2224:111] + node _T_981 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2224:153] + node _T_982 = not(_T_981) @[dec_tlu_ctl.scala 2224:137] + node _T_983 = or(_T_982, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2224:169] + node _T_984 = and(_T_980, _T_983) @[dec_tlu_ctl.scala 2224:134] + node _T_985 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2224:91] + node _T_986 = eq(_T_985, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2224:98] + node _T_987 = and(io.dec_csr_wen_r_mod, _T_986) @[dec_tlu_ctl.scala 2224:69] + node _T_988 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2224:120] + node _T_989 = and(_T_987, _T_988) @[dec_tlu_ctl.scala 2224:111] + node _T_990 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2224:153] + node _T_991 = not(_T_990) @[dec_tlu_ctl.scala 2224:137] + node _T_992 = or(_T_991, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2224:169] + node _T_993 = and(_T_989, _T_992) @[dec_tlu_ctl.scala 2224:134] + node _T_994 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2224:91] + node _T_995 = eq(_T_994, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2224:98] + node _T_996 = and(io.dec_csr_wen_r_mod, _T_995) @[dec_tlu_ctl.scala 2224:69] + node _T_997 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2224:120] + node _T_998 = and(_T_996, _T_997) @[dec_tlu_ctl.scala 2224:111] + node _T_999 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2224:153] + node _T_1000 = not(_T_999) @[dec_tlu_ctl.scala 2224:137] + node _T_1001 = or(_T_1000, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2224:169] + node _T_1002 = and(_T_998, _T_1001) @[dec_tlu_ctl.scala 2224:134] wire wr_mtdata2_t_r : UInt<1>[4] @[dec_tlu_ctl.scala 2224:42] - wr_mtdata2_t_r[0] <= _T_965 @[dec_tlu_ctl.scala 2224:42] - wr_mtdata2_t_r[1] <= _T_974 @[dec_tlu_ctl.scala 2224:42] - wr_mtdata2_t_r[2] <= _T_983 @[dec_tlu_ctl.scala 2224:42] - wr_mtdata2_t_r[3] <= _T_992 @[dec_tlu_ctl.scala 2224:42] - node _T_993 = bits(wr_mtdata2_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2225:84] + wr_mtdata2_t_r[0] <= _T_975 @[dec_tlu_ctl.scala 2224:42] + wr_mtdata2_t_r[1] <= _T_984 @[dec_tlu_ctl.scala 2224:42] + wr_mtdata2_t_r[2] <= _T_993 @[dec_tlu_ctl.scala 2224:42] + wr_mtdata2_t_r[3] <= _T_1002 @[dec_tlu_ctl.scala 2224:42] + node _T_1003 = bits(wr_mtdata2_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2225:84] inst rvclkhdr_22 of rvclkhdr_742 @[lib.scala 368:23] rvclkhdr_22.clock <= clock rvclkhdr_22.reset <= reset rvclkhdr_22.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_22.io.en <= _T_993 @[lib.scala 371:17] + rvclkhdr_22.io.en <= _T_1003 @[lib.scala 371:17] rvclkhdr_22.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_994 : UInt, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_994 <= io.dec_csr_wrdata_r @[lib.scala 374:16] - mtdata2_t[0] <= _T_994 @[dec_tlu_ctl.scala 2225:36] - node _T_995 = bits(wr_mtdata2_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2225:84] + reg _T_1004 : UInt, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_1004 <= io.dec_csr_wrdata_r @[lib.scala 374:16] + mtdata2_t[0] <= _T_1004 @[dec_tlu_ctl.scala 2225:36] + node _T_1005 = bits(wr_mtdata2_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2225:84] inst rvclkhdr_23 of rvclkhdr_743 @[lib.scala 368:23] rvclkhdr_23.clock <= clock rvclkhdr_23.reset <= reset rvclkhdr_23.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_23.io.en <= _T_995 @[lib.scala 371:17] + rvclkhdr_23.io.en <= _T_1005 @[lib.scala 371:17] rvclkhdr_23.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_996 : UInt, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_996 <= io.dec_csr_wrdata_r @[lib.scala 374:16] - mtdata2_t[1] <= _T_996 @[dec_tlu_ctl.scala 2225:36] - node _T_997 = bits(wr_mtdata2_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2225:84] + reg _T_1006 : UInt, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_1006 <= io.dec_csr_wrdata_r @[lib.scala 374:16] + mtdata2_t[1] <= _T_1006 @[dec_tlu_ctl.scala 2225:36] + node _T_1007 = bits(wr_mtdata2_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2225:84] inst rvclkhdr_24 of rvclkhdr_744 @[lib.scala 368:23] rvclkhdr_24.clock <= clock rvclkhdr_24.reset <= reset rvclkhdr_24.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_24.io.en <= _T_997 @[lib.scala 371:17] + rvclkhdr_24.io.en <= _T_1007 @[lib.scala 371:17] rvclkhdr_24.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_998 : UInt, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_998 <= io.dec_csr_wrdata_r @[lib.scala 374:16] - mtdata2_t[2] <= _T_998 @[dec_tlu_ctl.scala 2225:36] - node _T_999 = bits(wr_mtdata2_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2225:84] + reg _T_1008 : UInt, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_1008 <= io.dec_csr_wrdata_r @[lib.scala 374:16] + mtdata2_t[2] <= _T_1008 @[dec_tlu_ctl.scala 2225:36] + node _T_1009 = bits(wr_mtdata2_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2225:84] inst rvclkhdr_25 of rvclkhdr_745 @[lib.scala 368:23] rvclkhdr_25.clock <= clock rvclkhdr_25.reset <= reset rvclkhdr_25.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_25.io.en <= _T_999 @[lib.scala 371:17] + rvclkhdr_25.io.en <= _T_1009 @[lib.scala 371:17] rvclkhdr_25.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_1000 : UInt, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_1000 <= io.dec_csr_wrdata_r @[lib.scala 374:16] - mtdata2_t[3] <= _T_1000 @[dec_tlu_ctl.scala 2225:36] - node _T_1001 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2229:57] - node _T_1002 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2229:57] - node _T_1003 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2229:57] - node _T_1004 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2229:57] - node _T_1005 = mux(_T_1001, mtdata2_t[0], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1006 = mux(_T_1002, mtdata2_t[1], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1007 = mux(_T_1003, mtdata2_t[2], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1008 = mux(_T_1004, mtdata2_t[3], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1009 = or(_T_1005, _T_1006) @[Mux.scala 27:72] - node _T_1010 = or(_T_1009, _T_1007) @[Mux.scala 27:72] - node _T_1011 = or(_T_1010, _T_1008) @[Mux.scala 27:72] + reg _T_1010 : UInt, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_1010 <= io.dec_csr_wrdata_r @[lib.scala 374:16] + mtdata2_t[3] <= _T_1010 @[dec_tlu_ctl.scala 2225:36] + node _T_1011 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2229:57] + node _T_1012 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2229:57] + node _T_1013 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2229:57] + node _T_1014 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2229:57] + node _T_1015 = mux(_T_1011, mtdata2_t[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1016 = mux(_T_1012, mtdata2_t[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1017 = mux(_T_1013, mtdata2_t[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1018 = mux(_T_1014, mtdata2_t[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1019 = or(_T_1015, _T_1016) @[Mux.scala 27:72] + node _T_1020 = or(_T_1019, _T_1017) @[Mux.scala 27:72] + node _T_1021 = or(_T_1020, _T_1018) @[Mux.scala 27:72] wire mtdata2_tsel_out : UInt<32> @[Mux.scala 27:72] - mtdata2_tsel_out <= _T_1011 @[Mux.scala 27:72] + mtdata2_tsel_out <= _T_1021 @[Mux.scala 27:72] io.trigger_pkt_any[0].tdata2 <= mtdata2_t[0] @[dec_tlu_ctl.scala 2230:51] io.trigger_pkt_any[1].tdata2 <= mtdata2_t[1] @[dec_tlu_ctl.scala 2230:51] io.trigger_pkt_any[2].tdata2 <= mtdata2_t[2] @[dec_tlu_ctl.scala 2230:51] @@ -74398,248 +74408,238 @@ circuit quasar_wrapper : mhpme_vec[1] <= mhpme4 @[dec_tlu_ctl.scala 2241:15] mhpme_vec[2] <= mhpme5 @[dec_tlu_ctl.scala 2242:15] mhpme_vec[3] <= mhpme6 @[dec_tlu_ctl.scala 2243:15] - node _T_1012 = bits(io.tlu_i0_commit_cmt, 0, 0) @[Bitwise.scala 72:15] - node _T_1013 = mux(_T_1012, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node pmu_i0_itype_qual = and(io.dec_tlu_packet_r.pmu_i0_itype, _T_1013) @[dec_tlu_ctl.scala 2249:59] + node _T_1022 = bits(io.tlu_i0_commit_cmt, 0, 0) @[Bitwise.scala 72:15] + node _T_1023 = mux(_T_1022, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node pmu_i0_itype_qual = and(io.dec_tlu_packet_r.pmu_i0_itype, _T_1023) @[dec_tlu_ctl.scala 2249:59] wire mhpmc_inc_r : UInt<1>[4] @[dec_tlu_ctl.scala 2250:24] wire mhpmc_inc_r_d1 : UInt<1>[4] @[dec_tlu_ctl.scala 2251:27] - node _T_1014 = bits(mcountinhibit, 3, 3) @[dec_tlu_ctl.scala 2255:38] - node _T_1015 = not(_T_1014) @[dec_tlu_ctl.scala 2255:24] - node _T_1016 = eq(mhpme_vec[0], UInt<1>("h01")) @[dec_tlu_ctl.scala 2256:34] - node _T_1017 = bits(_T_1016, 0, 0) @[dec_tlu_ctl.scala 2256:62] - node _T_1018 = eq(mhpme_vec[0], UInt<2>("h02")) @[dec_tlu_ctl.scala 2257:34] - node _T_1019 = bits(_T_1018, 0, 0) @[dec_tlu_ctl.scala 2257:62] - node _T_1020 = eq(mhpme_vec[0], UInt<2>("h03")) @[dec_tlu_ctl.scala 2258:34] - node _T_1021 = bits(_T_1020, 0, 0) @[dec_tlu_ctl.scala 2258:62] - node _T_1022 = eq(mhpme_vec[0], UInt<3>("h04")) @[dec_tlu_ctl.scala 2259:34] - node _T_1023 = bits(_T_1022, 0, 0) @[dec_tlu_ctl.scala 2259:62] - node _T_1024 = not(io.illegal_r) @[dec_tlu_ctl.scala 2259:96] - node _T_1025 = and(io.tlu_i0_commit_cmt, _T_1024) @[dec_tlu_ctl.scala 2259:94] - node _T_1026 = eq(mhpme_vec[0], UInt<3>("h05")) @[dec_tlu_ctl.scala 2260:34] - node _T_1027 = bits(_T_1026, 0, 0) @[dec_tlu_ctl.scala 2260:62] - node _T_1028 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2260:96] - node _T_1029 = and(io.tlu_i0_commit_cmt, _T_1028) @[dec_tlu_ctl.scala 2260:94] - node _T_1030 = not(io.illegal_r) @[dec_tlu_ctl.scala 2260:117] - node _T_1031 = and(_T_1029, _T_1030) @[dec_tlu_ctl.scala 2260:115] - node _T_1032 = eq(mhpme_vec[0], UInt<3>("h06")) @[dec_tlu_ctl.scala 2261:34] - node _T_1033 = bits(_T_1032, 0, 0) @[dec_tlu_ctl.scala 2261:62] - node _T_1034 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2261:94] - node _T_1035 = not(io.illegal_r) @[dec_tlu_ctl.scala 2261:117] - node _T_1036 = and(_T_1034, _T_1035) @[dec_tlu_ctl.scala 2261:115] - node _T_1037 = eq(mhpme_vec[0], UInt<3>("h07")) @[dec_tlu_ctl.scala 2262:34] - node _T_1038 = bits(_T_1037, 0, 0) @[dec_tlu_ctl.scala 2262:62] - node _T_1039 = eq(mhpme_vec[0], UInt<4>("h08")) @[dec_tlu_ctl.scala 2263:34] - node _T_1040 = bits(_T_1039, 0, 0) @[dec_tlu_ctl.scala 2263:62] - node _T_1041 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2264:34] - node _T_1042 = bits(_T_1041, 0, 0) @[dec_tlu_ctl.scala 2264:62] - node _T_1043 = eq(mhpme_vec[0], UInt<4>("h09")) @[dec_tlu_ctl.scala 2265:34] - node _T_1044 = bits(_T_1043, 0, 0) @[dec_tlu_ctl.scala 2265:62] - node _T_1045 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2265:91] - node _T_1046 = eq(mhpme_vec[0], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2266:34] - node _T_1047 = bits(_T_1046, 0, 0) @[dec_tlu_ctl.scala 2266:62] - node _T_1048 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2266:105] - node _T_1049 = eq(mhpme_vec[0], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2267:34] - node _T_1050 = bits(_T_1049, 0, 0) @[dec_tlu_ctl.scala 2267:62] - node _T_1051 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2267:91] - node _T_1052 = eq(mhpme_vec[0], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2268:34] - node _T_1053 = bits(_T_1052, 0, 0) @[dec_tlu_ctl.scala 2268:62] - node _T_1054 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2268:91] - node _T_1055 = eq(mhpme_vec[0], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2269:34] - node _T_1056 = bits(_T_1055, 0, 0) @[dec_tlu_ctl.scala 2269:62] - node _T_1057 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2269:91] - node _T_1058 = and(_T_1057, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2269:100] - node _T_1059 = eq(mhpme_vec[0], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2270:34] - node _T_1060 = bits(_T_1059, 0, 0) @[dec_tlu_ctl.scala 2270:62] - node _T_1061 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2270:91] - node _T_1062 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2270:142] - node _T_1063 = and(_T_1061, _T_1062) @[dec_tlu_ctl.scala 2270:101] - node _T_1064 = eq(mhpme_vec[0], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2271:34] - node _T_1065 = bits(_T_1064, 0, 0) @[dec_tlu_ctl.scala 2271:59] - node _T_1066 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2271:89] - node _T_1067 = eq(mhpme_vec[0], UInt<5>("h010")) @[dec_tlu_ctl.scala 2272:34] - node _T_1068 = bits(_T_1067, 0, 0) @[dec_tlu_ctl.scala 2272:59] - node _T_1069 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2272:89] - node _T_1070 = eq(mhpme_vec[0], UInt<5>("h012")) @[dec_tlu_ctl.scala 2273:34] - node _T_1071 = bits(_T_1070, 0, 0) @[dec_tlu_ctl.scala 2273:59] - node _T_1072 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2273:89] - node _T_1073 = eq(mhpme_vec[0], UInt<5>("h011")) @[dec_tlu_ctl.scala 2274:34] - node _T_1074 = bits(_T_1073, 0, 0) @[dec_tlu_ctl.scala 2274:59] - node _T_1075 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2274:89] - node _T_1076 = eq(mhpme_vec[0], UInt<5>("h013")) @[dec_tlu_ctl.scala 2275:34] - node _T_1077 = bits(_T_1076, 0, 0) @[dec_tlu_ctl.scala 2275:59] - node _T_1078 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2275:89] - node _T_1079 = eq(mhpme_vec[0], UInt<5>("h014")) @[dec_tlu_ctl.scala 2276:34] - node _T_1080 = bits(_T_1079, 0, 0) @[dec_tlu_ctl.scala 2276:59] - node _T_1081 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2276:89] - node _T_1082 = eq(mhpme_vec[0], UInt<5>("h015")) @[dec_tlu_ctl.scala 2277:34] - node _T_1083 = bits(_T_1082, 0, 0) @[dec_tlu_ctl.scala 2277:59] - node _T_1084 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2277:89] - node _T_1085 = eq(mhpme_vec[0], UInt<5>("h016")) @[dec_tlu_ctl.scala 2278:34] - node _T_1086 = bits(_T_1085, 0, 0) @[dec_tlu_ctl.scala 2278:59] - node _T_1087 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2278:89] - node _T_1088 = eq(mhpme_vec[0], UInt<5>("h017")) @[dec_tlu_ctl.scala 2279:34] - node _T_1089 = bits(_T_1088, 0, 0) @[dec_tlu_ctl.scala 2279:59] - node _T_1090 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2279:89] - node _T_1091 = eq(mhpme_vec[0], UInt<5>("h018")) @[dec_tlu_ctl.scala 2280:34] - node _T_1092 = bits(_T_1091, 0, 0) @[dec_tlu_ctl.scala 2280:59] - node _T_1093 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2280:89] - node _T_1094 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2280:122] - node _T_1095 = or(_T_1093, _T_1094) @[dec_tlu_ctl.scala 2280:101] - node _T_1096 = eq(mhpme_vec[0], UInt<5>("h019")) @[dec_tlu_ctl.scala 2281:34] - node _T_1097 = bits(_T_1096, 0, 0) @[dec_tlu_ctl.scala 2281:62] - node _T_1098 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2281:95] - node _T_1099 = eq(mhpme_vec[0], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2282:34] - node _T_1100 = bits(_T_1099, 0, 0) @[dec_tlu_ctl.scala 2282:62] - node _T_1101 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2282:97] - node _T_1102 = eq(mhpme_vec[0], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2283:34] - node _T_1103 = bits(_T_1102, 0, 0) @[dec_tlu_ctl.scala 2283:62] - node _T_1104 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2283:110] - node _T_1105 = eq(mhpme_vec[0], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2284:34] - node _T_1106 = bits(_T_1105, 0, 0) @[dec_tlu_ctl.scala 2284:62] - node _T_1107 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2285:34] - node _T_1108 = bits(_T_1107, 0, 0) @[dec_tlu_ctl.scala 2285:62] - node _T_1109 = eq(mhpme_vec[0], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2286:34] - node _T_1110 = bits(_T_1109, 0, 0) @[dec_tlu_ctl.scala 2286:62] - node _T_1111 = eq(mhpme_vec[0], UInt<6>("h020")) @[dec_tlu_ctl.scala 2287:34] - node _T_1112 = bits(_T_1111, 0, 0) @[dec_tlu_ctl.scala 2287:62] - node _T_1113 = eq(mhpme_vec[0], UInt<6>("h022")) @[dec_tlu_ctl.scala 2288:34] - node _T_1114 = bits(_T_1113, 0, 0) @[dec_tlu_ctl.scala 2288:62] - node _T_1115 = eq(mhpme_vec[0], UInt<6>("h023")) @[dec_tlu_ctl.scala 2289:34] - node _T_1116 = bits(_T_1115, 0, 0) @[dec_tlu_ctl.scala 2289:62] - node _T_1117 = eq(mhpme_vec[0], UInt<6>("h024")) @[dec_tlu_ctl.scala 2290:34] - node _T_1118 = bits(_T_1117, 0, 0) @[dec_tlu_ctl.scala 2290:62] - node _T_1119 = eq(mhpme_vec[0], UInt<6>("h025")) @[dec_tlu_ctl.scala 2291:34] - node _T_1120 = bits(_T_1119, 0, 0) @[dec_tlu_ctl.scala 2291:62] - node _T_1121 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2291:98] - node _T_1122 = or(_T_1121, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2291:120] - node _T_1123 = eq(mhpme_vec[0], UInt<6>("h026")) @[dec_tlu_ctl.scala 2292:34] - node _T_1124 = bits(_T_1123, 0, 0) @[dec_tlu_ctl.scala 2292:62] - node _T_1125 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2292:92] - node _T_1126 = or(_T_1125, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2292:117] - node _T_1127 = eq(mhpme_vec[0], UInt<6>("h027")) @[dec_tlu_ctl.scala 2293:34] - node _T_1128 = bits(_T_1127, 0, 0) @[dec_tlu_ctl.scala 2293:62] - node _T_1129 = eq(mhpme_vec[0], UInt<6>("h028")) @[dec_tlu_ctl.scala 2294:34] - node _T_1130 = bits(_T_1129, 0, 0) @[dec_tlu_ctl.scala 2294:62] - node _T_1131 = eq(mhpme_vec[0], UInt<6>("h029")) @[dec_tlu_ctl.scala 2295:34] - node _T_1132 = bits(_T_1131, 0, 0) @[dec_tlu_ctl.scala 2295:62] - node _T_1133 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2295:97] - node _T_1134 = and(_T_1133, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2295:129] - node _T_1135 = eq(mhpme_vec[0], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2296:34] - node _T_1136 = bits(_T_1135, 0, 0) @[dec_tlu_ctl.scala 2296:62] - node _T_1137 = eq(mhpme_vec[0], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2297:34] - node _T_1138 = bits(_T_1137, 0, 0) @[dec_tlu_ctl.scala 2297:62] - node _T_1139 = eq(mhpme_vec[0], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2298:34] - node _T_1140 = bits(_T_1139, 0, 0) @[dec_tlu_ctl.scala 2298:62] - node _T_1141 = eq(mhpme_vec[0], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2299:34] - node _T_1142 = bits(_T_1141, 0, 0) @[dec_tlu_ctl.scala 2299:62] - node _T_1143 = eq(mhpme_vec[0], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2300:34] - node _T_1144 = bits(_T_1143, 0, 0) @[dec_tlu_ctl.scala 2300:62] - node _T_1145 = eq(mhpme_vec[0], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2301:34] - node _T_1146 = bits(_T_1145, 0, 0) @[dec_tlu_ctl.scala 2301:62] - node _T_1147 = eq(mhpme_vec[0], UInt<6>("h030")) @[dec_tlu_ctl.scala 2302:34] - node _T_1148 = bits(_T_1147, 0, 0) @[dec_tlu_ctl.scala 2302:62] - node _T_1149 = eq(mhpme_vec[0], UInt<6>("h031")) @[dec_tlu_ctl.scala 2303:34] - node _T_1150 = bits(_T_1149, 0, 0) @[dec_tlu_ctl.scala 2303:62] - node _T_1151 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2303:84] - node _T_1152 = bits(_T_1151, 0, 0) @[dec_tlu_ctl.scala 2303:84] - node _T_1153 = not(_T_1152) @[dec_tlu_ctl.scala 2303:73] - node _T_1154 = eq(mhpme_vec[0], UInt<6>("h032")) @[dec_tlu_ctl.scala 2304:34] - node _T_1155 = bits(_T_1154, 0, 0) @[dec_tlu_ctl.scala 2304:62] - node _T_1156 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2304:84] - node _T_1157 = bits(_T_1156, 0, 0) @[dec_tlu_ctl.scala 2304:84] - node _T_1158 = not(_T_1157) @[dec_tlu_ctl.scala 2304:73] - node _T_1159 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2304:107] - node _T_1160 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2304:118] - node _T_1161 = and(_T_1159, _T_1160) @[dec_tlu_ctl.scala 2304:113] - node _T_1162 = orr(_T_1161) @[dec_tlu_ctl.scala 2304:125] - node _T_1163 = and(_T_1158, _T_1162) @[dec_tlu_ctl.scala 2304:98] - node _T_1164 = eq(mhpme_vec[0], UInt<6>("h036")) @[dec_tlu_ctl.scala 2305:34] - node _T_1165 = bits(_T_1164, 0, 0) @[dec_tlu_ctl.scala 2305:62] - node _T_1166 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2305:91] - node _T_1167 = eq(mhpme_vec[0], UInt<6>("h037")) @[dec_tlu_ctl.scala 2306:34] - node _T_1168 = bits(_T_1167, 0, 0) @[dec_tlu_ctl.scala 2306:62] - node _T_1169 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2306:94] - node _T_1170 = eq(mhpme_vec[0], UInt<6>("h038")) @[dec_tlu_ctl.scala 2307:34] - node _T_1171 = bits(_T_1170, 0, 0) @[dec_tlu_ctl.scala 2307:62] - node _T_1172 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2307:94] - node _T_1173 = eq(mhpme_vec[0], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2309:34] - node _T_1174 = bits(_T_1173, 0, 0) @[dec_tlu_ctl.scala 2309:62] - node _T_1175 = eq(mhpme_vec[0], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2310:34] - node _T_1176 = bits(_T_1175, 0, 0) @[dec_tlu_ctl.scala 2310:62] - node _T_1177 = eq(mhpme_vec[0], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2311:34] - node _T_1178 = bits(_T_1177, 0, 0) @[dec_tlu_ctl.scala 2311:62] - node _T_1179 = eq(mhpme_vec[0], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2312:34] - node _T_1180 = bits(_T_1179, 0, 0) @[dec_tlu_ctl.scala 2312:62] - node _T_1181 = eq(mhpme_vec[0], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2313:34] - node _T_1182 = bits(_T_1181, 0, 0) @[dec_tlu_ctl.scala 2313:62] - node _T_1183 = mux(_T_1017, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1184 = mux(_T_1019, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1185 = mux(_T_1021, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1186 = mux(_T_1023, _T_1025, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1187 = mux(_T_1027, _T_1031, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1188 = mux(_T_1033, _T_1036, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1189 = mux(_T_1038, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1190 = mux(_T_1040, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1191 = mux(_T_1042, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1192 = mux(_T_1044, _T_1045, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1193 = mux(_T_1047, _T_1048, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1194 = mux(_T_1050, _T_1051, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1195 = mux(_T_1053, _T_1054, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1196 = mux(_T_1056, _T_1058, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1197 = mux(_T_1060, _T_1063, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1198 = mux(_T_1065, _T_1066, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1199 = mux(_T_1068, _T_1069, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1200 = mux(_T_1071, _T_1072, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1201 = mux(_T_1074, _T_1075, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1202 = mux(_T_1077, _T_1078, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1203 = mux(_T_1080, _T_1081, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1204 = mux(_T_1083, _T_1084, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1205 = mux(_T_1086, _T_1087, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1206 = mux(_T_1089, _T_1090, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1207 = mux(_T_1092, _T_1095, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1208 = mux(_T_1097, _T_1098, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1209 = mux(_T_1100, _T_1101, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1210 = mux(_T_1103, _T_1104, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1211 = mux(_T_1106, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1212 = mux(_T_1108, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1213 = mux(_T_1110, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1214 = mux(_T_1112, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1215 = mux(_T_1114, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1216 = mux(_T_1116, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1217 = mux(_T_1118, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1218 = mux(_T_1120, _T_1122, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1219 = mux(_T_1124, _T_1126, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1220 = mux(_T_1128, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1221 = mux(_T_1130, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1222 = mux(_T_1132, _T_1134, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1223 = mux(_T_1136, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1224 = mux(_T_1138, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1225 = mux(_T_1140, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1226 = mux(_T_1142, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1227 = mux(_T_1144, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1228 = mux(_T_1146, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1229 = mux(_T_1148, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1230 = mux(_T_1150, _T_1153, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1231 = mux(_T_1155, _T_1163, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1232 = mux(_T_1165, _T_1166, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1233 = mux(_T_1168, _T_1169, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1234 = mux(_T_1171, _T_1172, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1235 = mux(_T_1174, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1236 = mux(_T_1176, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1237 = mux(_T_1178, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1238 = mux(_T_1180, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1239 = mux(_T_1182, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1240 = or(_T_1183, _T_1184) @[Mux.scala 27:72] - node _T_1241 = or(_T_1240, _T_1185) @[Mux.scala 27:72] - node _T_1242 = or(_T_1241, _T_1186) @[Mux.scala 27:72] - node _T_1243 = or(_T_1242, _T_1187) @[Mux.scala 27:72] - node _T_1244 = or(_T_1243, _T_1188) @[Mux.scala 27:72] - node _T_1245 = or(_T_1244, _T_1189) @[Mux.scala 27:72] - node _T_1246 = or(_T_1245, _T_1190) @[Mux.scala 27:72] - node _T_1247 = or(_T_1246, _T_1191) @[Mux.scala 27:72] - node _T_1248 = or(_T_1247, _T_1192) @[Mux.scala 27:72] - node _T_1249 = or(_T_1248, _T_1193) @[Mux.scala 27:72] - node _T_1250 = or(_T_1249, _T_1194) @[Mux.scala 27:72] + node _T_1024 = bits(mcountinhibit, 3, 3) @[dec_tlu_ctl.scala 2255:38] + node _T_1025 = not(_T_1024) @[dec_tlu_ctl.scala 2255:24] + node _T_1026 = eq(mhpme_vec[0], UInt<1>("h01")) @[dec_tlu_ctl.scala 2256:34] + node _T_1027 = bits(_T_1026, 0, 0) @[dec_tlu_ctl.scala 2256:62] + node _T_1028 = eq(mhpme_vec[0], UInt<2>("h02")) @[dec_tlu_ctl.scala 2257:34] + node _T_1029 = bits(_T_1028, 0, 0) @[dec_tlu_ctl.scala 2257:62] + node _T_1030 = eq(mhpme_vec[0], UInt<2>("h03")) @[dec_tlu_ctl.scala 2258:34] + node _T_1031 = bits(_T_1030, 0, 0) @[dec_tlu_ctl.scala 2258:62] + node _T_1032 = eq(mhpme_vec[0], UInt<3>("h04")) @[dec_tlu_ctl.scala 2259:34] + node _T_1033 = bits(_T_1032, 0, 0) @[dec_tlu_ctl.scala 2259:62] + node _T_1034 = not(io.illegal_r) @[dec_tlu_ctl.scala 2259:96] + node _T_1035 = and(io.tlu_i0_commit_cmt, _T_1034) @[dec_tlu_ctl.scala 2259:94] + node _T_1036 = eq(mhpme_vec[0], UInt<3>("h05")) @[dec_tlu_ctl.scala 2260:34] + node _T_1037 = bits(_T_1036, 0, 0) @[dec_tlu_ctl.scala 2260:62] + node _T_1038 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2260:96] + node _T_1039 = and(io.tlu_i0_commit_cmt, _T_1038) @[dec_tlu_ctl.scala 2260:94] + node _T_1040 = not(io.illegal_r) @[dec_tlu_ctl.scala 2260:117] + node _T_1041 = and(_T_1039, _T_1040) @[dec_tlu_ctl.scala 2260:115] + node _T_1042 = eq(mhpme_vec[0], UInt<3>("h06")) @[dec_tlu_ctl.scala 2261:34] + node _T_1043 = bits(_T_1042, 0, 0) @[dec_tlu_ctl.scala 2261:62] + node _T_1044 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2261:94] + node _T_1045 = not(io.illegal_r) @[dec_tlu_ctl.scala 2261:117] + node _T_1046 = and(_T_1044, _T_1045) @[dec_tlu_ctl.scala 2261:115] + node _T_1047 = eq(mhpme_vec[0], UInt<3>("h07")) @[dec_tlu_ctl.scala 2262:34] + node _T_1048 = bits(_T_1047, 0, 0) @[dec_tlu_ctl.scala 2262:62] + node _T_1049 = eq(mhpme_vec[0], UInt<4>("h08")) @[dec_tlu_ctl.scala 2263:34] + node _T_1050 = bits(_T_1049, 0, 0) @[dec_tlu_ctl.scala 2263:62] + node _T_1051 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2264:34] + node _T_1052 = bits(_T_1051, 0, 0) @[dec_tlu_ctl.scala 2264:62] + node _T_1053 = eq(mhpme_vec[0], UInt<4>("h09")) @[dec_tlu_ctl.scala 2265:34] + node _T_1054 = bits(_T_1053, 0, 0) @[dec_tlu_ctl.scala 2265:62] + node _T_1055 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2265:91] + node _T_1056 = eq(mhpme_vec[0], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2266:34] + node _T_1057 = bits(_T_1056, 0, 0) @[dec_tlu_ctl.scala 2266:62] + node _T_1058 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2266:105] + node _T_1059 = eq(mhpme_vec[0], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2267:34] + node _T_1060 = bits(_T_1059, 0, 0) @[dec_tlu_ctl.scala 2267:62] + node _T_1061 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2267:91] + node _T_1062 = eq(mhpme_vec[0], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2268:34] + node _T_1063 = bits(_T_1062, 0, 0) @[dec_tlu_ctl.scala 2268:62] + node _T_1064 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2268:91] + node _T_1065 = eq(mhpme_vec[0], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2269:34] + node _T_1066 = bits(_T_1065, 0, 0) @[dec_tlu_ctl.scala 2269:62] + node _T_1067 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2269:91] + node _T_1068 = and(_T_1067, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2269:100] + node _T_1069 = eq(mhpme_vec[0], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2270:34] + node _T_1070 = bits(_T_1069, 0, 0) @[dec_tlu_ctl.scala 2270:62] + node _T_1071 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2270:91] + node _T_1072 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2270:142] + node _T_1073 = and(_T_1071, _T_1072) @[dec_tlu_ctl.scala 2270:101] + node _T_1074 = eq(mhpme_vec[0], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2271:34] + node _T_1075 = bits(_T_1074, 0, 0) @[dec_tlu_ctl.scala 2271:59] + node _T_1076 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2271:89] + node _T_1077 = eq(mhpme_vec[0], UInt<5>("h010")) @[dec_tlu_ctl.scala 2272:34] + node _T_1078 = bits(_T_1077, 0, 0) @[dec_tlu_ctl.scala 2272:59] + node _T_1079 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2272:89] + node _T_1080 = eq(mhpme_vec[0], UInt<5>("h012")) @[dec_tlu_ctl.scala 2273:34] + node _T_1081 = bits(_T_1080, 0, 0) @[dec_tlu_ctl.scala 2273:59] + node _T_1082 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2273:89] + node _T_1083 = eq(mhpme_vec[0], UInt<5>("h011")) @[dec_tlu_ctl.scala 2274:34] + node _T_1084 = bits(_T_1083, 0, 0) @[dec_tlu_ctl.scala 2274:59] + node _T_1085 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2274:89] + node _T_1086 = eq(mhpme_vec[0], UInt<5>("h013")) @[dec_tlu_ctl.scala 2275:34] + node _T_1087 = bits(_T_1086, 0, 0) @[dec_tlu_ctl.scala 2275:59] + node _T_1088 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2275:89] + node _T_1089 = eq(mhpme_vec[0], UInt<5>("h014")) @[dec_tlu_ctl.scala 2276:34] + node _T_1090 = bits(_T_1089, 0, 0) @[dec_tlu_ctl.scala 2276:59] + node _T_1091 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2276:89] + node _T_1092 = eq(mhpme_vec[0], UInt<5>("h015")) @[dec_tlu_ctl.scala 2277:34] + node _T_1093 = bits(_T_1092, 0, 0) @[dec_tlu_ctl.scala 2277:59] + node _T_1094 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2277:89] + node _T_1095 = eq(mhpme_vec[0], UInt<5>("h016")) @[dec_tlu_ctl.scala 2278:34] + node _T_1096 = bits(_T_1095, 0, 0) @[dec_tlu_ctl.scala 2278:59] + node _T_1097 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2278:89] + node _T_1098 = eq(mhpme_vec[0], UInt<5>("h017")) @[dec_tlu_ctl.scala 2279:34] + node _T_1099 = bits(_T_1098, 0, 0) @[dec_tlu_ctl.scala 2279:59] + node _T_1100 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2279:89] + node _T_1101 = eq(mhpme_vec[0], UInt<5>("h018")) @[dec_tlu_ctl.scala 2280:34] + node _T_1102 = bits(_T_1101, 0, 0) @[dec_tlu_ctl.scala 2280:59] + node _T_1103 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2280:89] + node _T_1104 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2280:122] + node _T_1105 = or(_T_1103, _T_1104) @[dec_tlu_ctl.scala 2280:101] + node _T_1106 = eq(mhpme_vec[0], UInt<5>("h019")) @[dec_tlu_ctl.scala 2281:34] + node _T_1107 = bits(_T_1106, 0, 0) @[dec_tlu_ctl.scala 2281:62] + node _T_1108 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2281:95] + node _T_1109 = eq(mhpme_vec[0], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2282:34] + node _T_1110 = bits(_T_1109, 0, 0) @[dec_tlu_ctl.scala 2282:62] + node _T_1111 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2282:97] + node _T_1112 = eq(mhpme_vec[0], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2283:34] + node _T_1113 = bits(_T_1112, 0, 0) @[dec_tlu_ctl.scala 2283:62] + node _T_1114 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2283:110] + node _T_1115 = eq(mhpme_vec[0], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2284:34] + node _T_1116 = bits(_T_1115, 0, 0) @[dec_tlu_ctl.scala 2284:62] + node _T_1117 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2285:34] + node _T_1118 = bits(_T_1117, 0, 0) @[dec_tlu_ctl.scala 2285:62] + node _T_1119 = eq(mhpme_vec[0], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2286:34] + node _T_1120 = bits(_T_1119, 0, 0) @[dec_tlu_ctl.scala 2286:62] + node _T_1121 = eq(mhpme_vec[0], UInt<6>("h020")) @[dec_tlu_ctl.scala 2287:34] + node _T_1122 = bits(_T_1121, 0, 0) @[dec_tlu_ctl.scala 2287:62] + node _T_1123 = eq(mhpme_vec[0], UInt<6>("h022")) @[dec_tlu_ctl.scala 2288:34] + node _T_1124 = bits(_T_1123, 0, 0) @[dec_tlu_ctl.scala 2288:62] + node _T_1125 = eq(mhpme_vec[0], UInt<6>("h023")) @[dec_tlu_ctl.scala 2289:34] + node _T_1126 = bits(_T_1125, 0, 0) @[dec_tlu_ctl.scala 2289:62] + node _T_1127 = eq(mhpme_vec[0], UInt<6>("h024")) @[dec_tlu_ctl.scala 2290:34] + node _T_1128 = bits(_T_1127, 0, 0) @[dec_tlu_ctl.scala 2290:62] + node _T_1129 = eq(mhpme_vec[0], UInt<6>("h025")) @[dec_tlu_ctl.scala 2291:34] + node _T_1130 = bits(_T_1129, 0, 0) @[dec_tlu_ctl.scala 2291:62] + node _T_1131 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2291:98] + node _T_1132 = or(_T_1131, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2291:120] + node _T_1133 = eq(mhpme_vec[0], UInt<6>("h026")) @[dec_tlu_ctl.scala 2292:34] + node _T_1134 = bits(_T_1133, 0, 0) @[dec_tlu_ctl.scala 2292:62] + node _T_1135 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2292:92] + node _T_1136 = or(_T_1135, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2292:117] + node _T_1137 = eq(mhpme_vec[0], UInt<6>("h027")) @[dec_tlu_ctl.scala 2293:34] + node _T_1138 = bits(_T_1137, 0, 0) @[dec_tlu_ctl.scala 2293:62] + node _T_1139 = eq(mhpme_vec[0], UInt<6>("h028")) @[dec_tlu_ctl.scala 2294:34] + node _T_1140 = bits(_T_1139, 0, 0) @[dec_tlu_ctl.scala 2294:62] + node _T_1141 = eq(mhpme_vec[0], UInt<6>("h029")) @[dec_tlu_ctl.scala 2295:34] + node _T_1142 = bits(_T_1141, 0, 0) @[dec_tlu_ctl.scala 2295:62] + node _T_1143 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2295:97] + node _T_1144 = and(_T_1143, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2295:129] + node _T_1145 = eq(mhpme_vec[0], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2296:34] + node _T_1146 = bits(_T_1145, 0, 0) @[dec_tlu_ctl.scala 2296:62] + node _T_1147 = eq(mhpme_vec[0], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2297:34] + node _T_1148 = bits(_T_1147, 0, 0) @[dec_tlu_ctl.scala 2297:62] + node _T_1149 = eq(mhpme_vec[0], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2298:34] + node _T_1150 = bits(_T_1149, 0, 0) @[dec_tlu_ctl.scala 2298:62] + node _T_1151 = eq(mhpme_vec[0], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2299:34] + node _T_1152 = bits(_T_1151, 0, 0) @[dec_tlu_ctl.scala 2299:62] + node _T_1153 = eq(mhpme_vec[0], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2300:34] + node _T_1154 = bits(_T_1153, 0, 0) @[dec_tlu_ctl.scala 2300:62] + node _T_1155 = eq(mhpme_vec[0], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2301:34] + node _T_1156 = bits(_T_1155, 0, 0) @[dec_tlu_ctl.scala 2301:62] + node _T_1157 = eq(mhpme_vec[0], UInt<6>("h030")) @[dec_tlu_ctl.scala 2302:34] + node _T_1158 = bits(_T_1157, 0, 0) @[dec_tlu_ctl.scala 2302:62] + node _T_1159 = eq(mhpme_vec[0], UInt<6>("h031")) @[dec_tlu_ctl.scala 2303:34] + node _T_1160 = bits(_T_1159, 0, 0) @[dec_tlu_ctl.scala 2303:62] + node _T_1161 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2303:84] + node _T_1162 = bits(_T_1161, 0, 0) @[dec_tlu_ctl.scala 2303:84] + node _T_1163 = not(_T_1162) @[dec_tlu_ctl.scala 2303:73] + node _T_1164 = eq(mhpme_vec[0], UInt<6>("h032")) @[dec_tlu_ctl.scala 2304:34] + node _T_1165 = bits(_T_1164, 0, 0) @[dec_tlu_ctl.scala 2304:62] + node _T_1166 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2304:84] + node _T_1167 = bits(_T_1166, 0, 0) @[dec_tlu_ctl.scala 2304:84] + node _T_1168 = not(_T_1167) @[dec_tlu_ctl.scala 2304:73] + node _T_1169 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2304:107] + node _T_1170 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2304:118] + node _T_1171 = and(_T_1169, _T_1170) @[dec_tlu_ctl.scala 2304:113] + node _T_1172 = orr(_T_1171) @[dec_tlu_ctl.scala 2304:125] + node _T_1173 = and(_T_1168, _T_1172) @[dec_tlu_ctl.scala 2304:98] + node _T_1174 = eq(mhpme_vec[0], UInt<6>("h036")) @[dec_tlu_ctl.scala 2305:34] + node _T_1175 = bits(_T_1174, 0, 0) @[dec_tlu_ctl.scala 2305:62] + node _T_1176 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2305:91] + node _T_1177 = eq(mhpme_vec[0], UInt<6>("h037")) @[dec_tlu_ctl.scala 2306:34] + node _T_1178 = bits(_T_1177, 0, 0) @[dec_tlu_ctl.scala 2306:62] + node _T_1179 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2306:94] + node _T_1180 = eq(mhpme_vec[0], UInt<6>("h038")) @[dec_tlu_ctl.scala 2307:34] + node _T_1181 = bits(_T_1180, 0, 0) @[dec_tlu_ctl.scala 2307:62] + node _T_1182 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2307:94] + node _T_1183 = eq(mhpme_vec[0], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2309:34] + node _T_1184 = bits(_T_1183, 0, 0) @[dec_tlu_ctl.scala 2309:62] + node _T_1185 = eq(mhpme_vec[0], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2310:34] + node _T_1186 = bits(_T_1185, 0, 0) @[dec_tlu_ctl.scala 2310:62] + node _T_1187 = eq(mhpme_vec[0], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2311:34] + node _T_1188 = bits(_T_1187, 0, 0) @[dec_tlu_ctl.scala 2311:62] + node _T_1189 = eq(mhpme_vec[0], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2312:34] + node _T_1190 = bits(_T_1189, 0, 0) @[dec_tlu_ctl.scala 2312:62] + node _T_1191 = eq(mhpme_vec[0], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2313:34] + node _T_1192 = bits(_T_1191, 0, 0) @[dec_tlu_ctl.scala 2313:62] + node _T_1193 = mux(_T_1027, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1194 = mux(_T_1029, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1195 = mux(_T_1031, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1196 = mux(_T_1033, _T_1035, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1197 = mux(_T_1037, _T_1041, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1198 = mux(_T_1043, _T_1046, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1199 = mux(_T_1048, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1200 = mux(_T_1050, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1201 = mux(_T_1052, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1202 = mux(_T_1054, _T_1055, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1203 = mux(_T_1057, _T_1058, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1204 = mux(_T_1060, _T_1061, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1205 = mux(_T_1063, _T_1064, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1206 = mux(_T_1066, _T_1068, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1207 = mux(_T_1070, _T_1073, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1208 = mux(_T_1075, _T_1076, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1209 = mux(_T_1078, _T_1079, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1210 = mux(_T_1081, _T_1082, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1211 = mux(_T_1084, _T_1085, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1212 = mux(_T_1087, _T_1088, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1213 = mux(_T_1090, _T_1091, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1214 = mux(_T_1093, _T_1094, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1215 = mux(_T_1096, _T_1097, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1216 = mux(_T_1099, _T_1100, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1217 = mux(_T_1102, _T_1105, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1218 = mux(_T_1107, _T_1108, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1219 = mux(_T_1110, _T_1111, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1220 = mux(_T_1113, _T_1114, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1221 = mux(_T_1116, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1222 = mux(_T_1118, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1223 = mux(_T_1120, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1224 = mux(_T_1122, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1225 = mux(_T_1124, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1226 = mux(_T_1126, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1227 = mux(_T_1128, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1228 = mux(_T_1130, _T_1132, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1229 = mux(_T_1134, _T_1136, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1230 = mux(_T_1138, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1231 = mux(_T_1140, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1232 = mux(_T_1142, _T_1144, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1233 = mux(_T_1146, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1234 = mux(_T_1148, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1235 = mux(_T_1150, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1236 = mux(_T_1152, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1237 = mux(_T_1154, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1238 = mux(_T_1156, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1239 = mux(_T_1158, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1240 = mux(_T_1160, _T_1163, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1241 = mux(_T_1165, _T_1173, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1242 = mux(_T_1175, _T_1176, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1243 = mux(_T_1178, _T_1179, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1244 = mux(_T_1181, _T_1182, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1245 = mux(_T_1184, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1246 = mux(_T_1186, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1247 = mux(_T_1188, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1248 = mux(_T_1190, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1249 = mux(_T_1192, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1250 = or(_T_1193, _T_1194) @[Mux.scala 27:72] node _T_1251 = or(_T_1250, _T_1195) @[Mux.scala 27:72] node _T_1252 = or(_T_1251, _T_1196) @[Mux.scala 27:72] node _T_1253 = or(_T_1252, _T_1197) @[Mux.scala 27:72] @@ -74685,247 +74685,247 @@ circuit quasar_wrapper : node _T_1293 = or(_T_1292, _T_1237) @[Mux.scala 27:72] node _T_1294 = or(_T_1293, _T_1238) @[Mux.scala 27:72] node _T_1295 = or(_T_1294, _T_1239) @[Mux.scala 27:72] - wire _T_1296 : UInt<1> @[Mux.scala 27:72] - _T_1296 <= _T_1295 @[Mux.scala 27:72] - node _T_1297 = and(_T_1015, _T_1296) @[dec_tlu_ctl.scala 2255:44] - mhpmc_inc_r[0] <= _T_1297 @[dec_tlu_ctl.scala 2255:19] - node _T_1298 = bits(mcountinhibit, 4, 4) @[dec_tlu_ctl.scala 2255:38] - node _T_1299 = not(_T_1298) @[dec_tlu_ctl.scala 2255:24] - node _T_1300 = eq(mhpme_vec[1], UInt<1>("h01")) @[dec_tlu_ctl.scala 2256:34] - node _T_1301 = bits(_T_1300, 0, 0) @[dec_tlu_ctl.scala 2256:62] - node _T_1302 = eq(mhpme_vec[1], UInt<2>("h02")) @[dec_tlu_ctl.scala 2257:34] - node _T_1303 = bits(_T_1302, 0, 0) @[dec_tlu_ctl.scala 2257:62] - node _T_1304 = eq(mhpme_vec[1], UInt<2>("h03")) @[dec_tlu_ctl.scala 2258:34] - node _T_1305 = bits(_T_1304, 0, 0) @[dec_tlu_ctl.scala 2258:62] - node _T_1306 = eq(mhpme_vec[1], UInt<3>("h04")) @[dec_tlu_ctl.scala 2259:34] - node _T_1307 = bits(_T_1306, 0, 0) @[dec_tlu_ctl.scala 2259:62] - node _T_1308 = not(io.illegal_r) @[dec_tlu_ctl.scala 2259:96] - node _T_1309 = and(io.tlu_i0_commit_cmt, _T_1308) @[dec_tlu_ctl.scala 2259:94] - node _T_1310 = eq(mhpme_vec[1], UInt<3>("h05")) @[dec_tlu_ctl.scala 2260:34] - node _T_1311 = bits(_T_1310, 0, 0) @[dec_tlu_ctl.scala 2260:62] - node _T_1312 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2260:96] - node _T_1313 = and(io.tlu_i0_commit_cmt, _T_1312) @[dec_tlu_ctl.scala 2260:94] - node _T_1314 = not(io.illegal_r) @[dec_tlu_ctl.scala 2260:117] - node _T_1315 = and(_T_1313, _T_1314) @[dec_tlu_ctl.scala 2260:115] - node _T_1316 = eq(mhpme_vec[1], UInt<3>("h06")) @[dec_tlu_ctl.scala 2261:34] - node _T_1317 = bits(_T_1316, 0, 0) @[dec_tlu_ctl.scala 2261:62] - node _T_1318 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2261:94] - node _T_1319 = not(io.illegal_r) @[dec_tlu_ctl.scala 2261:117] - node _T_1320 = and(_T_1318, _T_1319) @[dec_tlu_ctl.scala 2261:115] - node _T_1321 = eq(mhpme_vec[1], UInt<3>("h07")) @[dec_tlu_ctl.scala 2262:34] - node _T_1322 = bits(_T_1321, 0, 0) @[dec_tlu_ctl.scala 2262:62] - node _T_1323 = eq(mhpme_vec[1], UInt<4>("h08")) @[dec_tlu_ctl.scala 2263:34] - node _T_1324 = bits(_T_1323, 0, 0) @[dec_tlu_ctl.scala 2263:62] - node _T_1325 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2264:34] - node _T_1326 = bits(_T_1325, 0, 0) @[dec_tlu_ctl.scala 2264:62] - node _T_1327 = eq(mhpme_vec[1], UInt<4>("h09")) @[dec_tlu_ctl.scala 2265:34] - node _T_1328 = bits(_T_1327, 0, 0) @[dec_tlu_ctl.scala 2265:62] - node _T_1329 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2265:91] - node _T_1330 = eq(mhpme_vec[1], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2266:34] - node _T_1331 = bits(_T_1330, 0, 0) @[dec_tlu_ctl.scala 2266:62] - node _T_1332 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2266:105] - node _T_1333 = eq(mhpme_vec[1], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2267:34] - node _T_1334 = bits(_T_1333, 0, 0) @[dec_tlu_ctl.scala 2267:62] - node _T_1335 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2267:91] - node _T_1336 = eq(mhpme_vec[1], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2268:34] - node _T_1337 = bits(_T_1336, 0, 0) @[dec_tlu_ctl.scala 2268:62] - node _T_1338 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2268:91] - node _T_1339 = eq(mhpme_vec[1], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2269:34] - node _T_1340 = bits(_T_1339, 0, 0) @[dec_tlu_ctl.scala 2269:62] - node _T_1341 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2269:91] - node _T_1342 = and(_T_1341, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2269:100] - node _T_1343 = eq(mhpme_vec[1], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2270:34] - node _T_1344 = bits(_T_1343, 0, 0) @[dec_tlu_ctl.scala 2270:62] - node _T_1345 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2270:91] - node _T_1346 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2270:142] - node _T_1347 = and(_T_1345, _T_1346) @[dec_tlu_ctl.scala 2270:101] - node _T_1348 = eq(mhpme_vec[1], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2271:34] - node _T_1349 = bits(_T_1348, 0, 0) @[dec_tlu_ctl.scala 2271:59] - node _T_1350 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2271:89] - node _T_1351 = eq(mhpme_vec[1], UInt<5>("h010")) @[dec_tlu_ctl.scala 2272:34] - node _T_1352 = bits(_T_1351, 0, 0) @[dec_tlu_ctl.scala 2272:59] - node _T_1353 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2272:89] - node _T_1354 = eq(mhpme_vec[1], UInt<5>("h012")) @[dec_tlu_ctl.scala 2273:34] - node _T_1355 = bits(_T_1354, 0, 0) @[dec_tlu_ctl.scala 2273:59] - node _T_1356 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2273:89] - node _T_1357 = eq(mhpme_vec[1], UInt<5>("h011")) @[dec_tlu_ctl.scala 2274:34] - node _T_1358 = bits(_T_1357, 0, 0) @[dec_tlu_ctl.scala 2274:59] - node _T_1359 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2274:89] - node _T_1360 = eq(mhpme_vec[1], UInt<5>("h013")) @[dec_tlu_ctl.scala 2275:34] - node _T_1361 = bits(_T_1360, 0, 0) @[dec_tlu_ctl.scala 2275:59] - node _T_1362 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2275:89] - node _T_1363 = eq(mhpme_vec[1], UInt<5>("h014")) @[dec_tlu_ctl.scala 2276:34] - node _T_1364 = bits(_T_1363, 0, 0) @[dec_tlu_ctl.scala 2276:59] - node _T_1365 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2276:89] - node _T_1366 = eq(mhpme_vec[1], UInt<5>("h015")) @[dec_tlu_ctl.scala 2277:34] - node _T_1367 = bits(_T_1366, 0, 0) @[dec_tlu_ctl.scala 2277:59] - node _T_1368 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2277:89] - node _T_1369 = eq(mhpme_vec[1], UInt<5>("h016")) @[dec_tlu_ctl.scala 2278:34] - node _T_1370 = bits(_T_1369, 0, 0) @[dec_tlu_ctl.scala 2278:59] - node _T_1371 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2278:89] - node _T_1372 = eq(mhpme_vec[1], UInt<5>("h017")) @[dec_tlu_ctl.scala 2279:34] - node _T_1373 = bits(_T_1372, 0, 0) @[dec_tlu_ctl.scala 2279:59] - node _T_1374 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2279:89] - node _T_1375 = eq(mhpme_vec[1], UInt<5>("h018")) @[dec_tlu_ctl.scala 2280:34] - node _T_1376 = bits(_T_1375, 0, 0) @[dec_tlu_ctl.scala 2280:59] - node _T_1377 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2280:89] - node _T_1378 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2280:122] - node _T_1379 = or(_T_1377, _T_1378) @[dec_tlu_ctl.scala 2280:101] - node _T_1380 = eq(mhpme_vec[1], UInt<5>("h019")) @[dec_tlu_ctl.scala 2281:34] - node _T_1381 = bits(_T_1380, 0, 0) @[dec_tlu_ctl.scala 2281:62] - node _T_1382 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2281:95] - node _T_1383 = eq(mhpme_vec[1], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2282:34] - node _T_1384 = bits(_T_1383, 0, 0) @[dec_tlu_ctl.scala 2282:62] - node _T_1385 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2282:97] - node _T_1386 = eq(mhpme_vec[1], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2283:34] - node _T_1387 = bits(_T_1386, 0, 0) @[dec_tlu_ctl.scala 2283:62] - node _T_1388 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2283:110] - node _T_1389 = eq(mhpme_vec[1], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2284:34] - node _T_1390 = bits(_T_1389, 0, 0) @[dec_tlu_ctl.scala 2284:62] - node _T_1391 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2285:34] - node _T_1392 = bits(_T_1391, 0, 0) @[dec_tlu_ctl.scala 2285:62] - node _T_1393 = eq(mhpme_vec[1], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2286:34] - node _T_1394 = bits(_T_1393, 0, 0) @[dec_tlu_ctl.scala 2286:62] - node _T_1395 = eq(mhpme_vec[1], UInt<6>("h020")) @[dec_tlu_ctl.scala 2287:34] - node _T_1396 = bits(_T_1395, 0, 0) @[dec_tlu_ctl.scala 2287:62] - node _T_1397 = eq(mhpme_vec[1], UInt<6>("h022")) @[dec_tlu_ctl.scala 2288:34] - node _T_1398 = bits(_T_1397, 0, 0) @[dec_tlu_ctl.scala 2288:62] - node _T_1399 = eq(mhpme_vec[1], UInt<6>("h023")) @[dec_tlu_ctl.scala 2289:34] - node _T_1400 = bits(_T_1399, 0, 0) @[dec_tlu_ctl.scala 2289:62] - node _T_1401 = eq(mhpme_vec[1], UInt<6>("h024")) @[dec_tlu_ctl.scala 2290:34] - node _T_1402 = bits(_T_1401, 0, 0) @[dec_tlu_ctl.scala 2290:62] - node _T_1403 = eq(mhpme_vec[1], UInt<6>("h025")) @[dec_tlu_ctl.scala 2291:34] - node _T_1404 = bits(_T_1403, 0, 0) @[dec_tlu_ctl.scala 2291:62] - node _T_1405 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2291:98] - node _T_1406 = or(_T_1405, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2291:120] - node _T_1407 = eq(mhpme_vec[1], UInt<6>("h026")) @[dec_tlu_ctl.scala 2292:34] - node _T_1408 = bits(_T_1407, 0, 0) @[dec_tlu_ctl.scala 2292:62] - node _T_1409 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2292:92] - node _T_1410 = or(_T_1409, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2292:117] - node _T_1411 = eq(mhpme_vec[1], UInt<6>("h027")) @[dec_tlu_ctl.scala 2293:34] - node _T_1412 = bits(_T_1411, 0, 0) @[dec_tlu_ctl.scala 2293:62] - node _T_1413 = eq(mhpme_vec[1], UInt<6>("h028")) @[dec_tlu_ctl.scala 2294:34] - node _T_1414 = bits(_T_1413, 0, 0) @[dec_tlu_ctl.scala 2294:62] - node _T_1415 = eq(mhpme_vec[1], UInt<6>("h029")) @[dec_tlu_ctl.scala 2295:34] - node _T_1416 = bits(_T_1415, 0, 0) @[dec_tlu_ctl.scala 2295:62] - node _T_1417 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2295:97] - node _T_1418 = and(_T_1417, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2295:129] - node _T_1419 = eq(mhpme_vec[1], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2296:34] - node _T_1420 = bits(_T_1419, 0, 0) @[dec_tlu_ctl.scala 2296:62] - node _T_1421 = eq(mhpme_vec[1], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2297:34] - node _T_1422 = bits(_T_1421, 0, 0) @[dec_tlu_ctl.scala 2297:62] - node _T_1423 = eq(mhpme_vec[1], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2298:34] - node _T_1424 = bits(_T_1423, 0, 0) @[dec_tlu_ctl.scala 2298:62] - node _T_1425 = eq(mhpme_vec[1], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2299:34] - node _T_1426 = bits(_T_1425, 0, 0) @[dec_tlu_ctl.scala 2299:62] - node _T_1427 = eq(mhpme_vec[1], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2300:34] - node _T_1428 = bits(_T_1427, 0, 0) @[dec_tlu_ctl.scala 2300:62] - node _T_1429 = eq(mhpme_vec[1], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2301:34] - node _T_1430 = bits(_T_1429, 0, 0) @[dec_tlu_ctl.scala 2301:62] - node _T_1431 = eq(mhpme_vec[1], UInt<6>("h030")) @[dec_tlu_ctl.scala 2302:34] - node _T_1432 = bits(_T_1431, 0, 0) @[dec_tlu_ctl.scala 2302:62] - node _T_1433 = eq(mhpme_vec[1], UInt<6>("h031")) @[dec_tlu_ctl.scala 2303:34] - node _T_1434 = bits(_T_1433, 0, 0) @[dec_tlu_ctl.scala 2303:62] - node _T_1435 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2303:84] - node _T_1436 = bits(_T_1435, 0, 0) @[dec_tlu_ctl.scala 2303:84] - node _T_1437 = not(_T_1436) @[dec_tlu_ctl.scala 2303:73] - node _T_1438 = eq(mhpme_vec[1], UInt<6>("h032")) @[dec_tlu_ctl.scala 2304:34] - node _T_1439 = bits(_T_1438, 0, 0) @[dec_tlu_ctl.scala 2304:62] - node _T_1440 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2304:84] - node _T_1441 = bits(_T_1440, 0, 0) @[dec_tlu_ctl.scala 2304:84] - node _T_1442 = not(_T_1441) @[dec_tlu_ctl.scala 2304:73] - node _T_1443 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2304:107] - node _T_1444 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2304:118] - node _T_1445 = and(_T_1443, _T_1444) @[dec_tlu_ctl.scala 2304:113] - node _T_1446 = orr(_T_1445) @[dec_tlu_ctl.scala 2304:125] - node _T_1447 = and(_T_1442, _T_1446) @[dec_tlu_ctl.scala 2304:98] - node _T_1448 = eq(mhpme_vec[1], UInt<6>("h036")) @[dec_tlu_ctl.scala 2305:34] - node _T_1449 = bits(_T_1448, 0, 0) @[dec_tlu_ctl.scala 2305:62] - node _T_1450 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2305:91] - node _T_1451 = eq(mhpme_vec[1], UInt<6>("h037")) @[dec_tlu_ctl.scala 2306:34] - node _T_1452 = bits(_T_1451, 0, 0) @[dec_tlu_ctl.scala 2306:62] - node _T_1453 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2306:94] - node _T_1454 = eq(mhpme_vec[1], UInt<6>("h038")) @[dec_tlu_ctl.scala 2307:34] - node _T_1455 = bits(_T_1454, 0, 0) @[dec_tlu_ctl.scala 2307:62] - node _T_1456 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2307:94] - node _T_1457 = eq(mhpme_vec[1], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2309:34] - node _T_1458 = bits(_T_1457, 0, 0) @[dec_tlu_ctl.scala 2309:62] - node _T_1459 = eq(mhpme_vec[1], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2310:34] - node _T_1460 = bits(_T_1459, 0, 0) @[dec_tlu_ctl.scala 2310:62] - node _T_1461 = eq(mhpme_vec[1], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2311:34] - node _T_1462 = bits(_T_1461, 0, 0) @[dec_tlu_ctl.scala 2311:62] - node _T_1463 = eq(mhpme_vec[1], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2312:34] - node _T_1464 = bits(_T_1463, 0, 0) @[dec_tlu_ctl.scala 2312:62] - node _T_1465 = eq(mhpme_vec[1], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2313:34] - node _T_1466 = bits(_T_1465, 0, 0) @[dec_tlu_ctl.scala 2313:62] - node _T_1467 = mux(_T_1301, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1468 = mux(_T_1303, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1469 = mux(_T_1305, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1470 = mux(_T_1307, _T_1309, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1471 = mux(_T_1311, _T_1315, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1472 = mux(_T_1317, _T_1320, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1473 = mux(_T_1322, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1474 = mux(_T_1324, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1475 = mux(_T_1326, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1476 = mux(_T_1328, _T_1329, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1477 = mux(_T_1331, _T_1332, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1478 = mux(_T_1334, _T_1335, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1479 = mux(_T_1337, _T_1338, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1480 = mux(_T_1340, _T_1342, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1481 = mux(_T_1344, _T_1347, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1482 = mux(_T_1349, _T_1350, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1483 = mux(_T_1352, _T_1353, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1484 = mux(_T_1355, _T_1356, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1485 = mux(_T_1358, _T_1359, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1486 = mux(_T_1361, _T_1362, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1487 = mux(_T_1364, _T_1365, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1488 = mux(_T_1367, _T_1368, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1489 = mux(_T_1370, _T_1371, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1490 = mux(_T_1373, _T_1374, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1491 = mux(_T_1376, _T_1379, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1492 = mux(_T_1381, _T_1382, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1493 = mux(_T_1384, _T_1385, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1494 = mux(_T_1387, _T_1388, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1495 = mux(_T_1390, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1496 = mux(_T_1392, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1497 = mux(_T_1394, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1498 = mux(_T_1396, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1499 = mux(_T_1398, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1500 = mux(_T_1400, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1501 = mux(_T_1402, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1502 = mux(_T_1404, _T_1406, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1503 = mux(_T_1408, _T_1410, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1504 = mux(_T_1412, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1505 = mux(_T_1414, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1506 = mux(_T_1416, _T_1418, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1507 = mux(_T_1420, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1508 = mux(_T_1422, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1509 = mux(_T_1424, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1510 = mux(_T_1426, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1511 = mux(_T_1428, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1512 = mux(_T_1430, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1513 = mux(_T_1432, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1514 = mux(_T_1434, _T_1437, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1515 = mux(_T_1439, _T_1447, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1516 = mux(_T_1449, _T_1450, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1517 = mux(_T_1452, _T_1453, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1518 = mux(_T_1455, _T_1456, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1519 = mux(_T_1458, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1520 = mux(_T_1460, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1521 = mux(_T_1462, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1522 = mux(_T_1464, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1523 = mux(_T_1466, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1524 = or(_T_1467, _T_1468) @[Mux.scala 27:72] - node _T_1525 = or(_T_1524, _T_1469) @[Mux.scala 27:72] - node _T_1526 = or(_T_1525, _T_1470) @[Mux.scala 27:72] - node _T_1527 = or(_T_1526, _T_1471) @[Mux.scala 27:72] - node _T_1528 = or(_T_1527, _T_1472) @[Mux.scala 27:72] - node _T_1529 = or(_T_1528, _T_1473) @[Mux.scala 27:72] - node _T_1530 = or(_T_1529, _T_1474) @[Mux.scala 27:72] - node _T_1531 = or(_T_1530, _T_1475) @[Mux.scala 27:72] - node _T_1532 = or(_T_1531, _T_1476) @[Mux.scala 27:72] - node _T_1533 = or(_T_1532, _T_1477) @[Mux.scala 27:72] - node _T_1534 = or(_T_1533, _T_1478) @[Mux.scala 27:72] + node _T_1296 = or(_T_1295, _T_1240) @[Mux.scala 27:72] + node _T_1297 = or(_T_1296, _T_1241) @[Mux.scala 27:72] + node _T_1298 = or(_T_1297, _T_1242) @[Mux.scala 27:72] + node _T_1299 = or(_T_1298, _T_1243) @[Mux.scala 27:72] + node _T_1300 = or(_T_1299, _T_1244) @[Mux.scala 27:72] + node _T_1301 = or(_T_1300, _T_1245) @[Mux.scala 27:72] + node _T_1302 = or(_T_1301, _T_1246) @[Mux.scala 27:72] + node _T_1303 = or(_T_1302, _T_1247) @[Mux.scala 27:72] + node _T_1304 = or(_T_1303, _T_1248) @[Mux.scala 27:72] + node _T_1305 = or(_T_1304, _T_1249) @[Mux.scala 27:72] + wire _T_1306 : UInt<1> @[Mux.scala 27:72] + _T_1306 <= _T_1305 @[Mux.scala 27:72] + node _T_1307 = and(_T_1025, _T_1306) @[dec_tlu_ctl.scala 2255:44] + mhpmc_inc_r[0] <= _T_1307 @[dec_tlu_ctl.scala 2255:19] + node _T_1308 = bits(mcountinhibit, 4, 4) @[dec_tlu_ctl.scala 2255:38] + node _T_1309 = not(_T_1308) @[dec_tlu_ctl.scala 2255:24] + node _T_1310 = eq(mhpme_vec[1], UInt<1>("h01")) @[dec_tlu_ctl.scala 2256:34] + node _T_1311 = bits(_T_1310, 0, 0) @[dec_tlu_ctl.scala 2256:62] + node _T_1312 = eq(mhpme_vec[1], UInt<2>("h02")) @[dec_tlu_ctl.scala 2257:34] + node _T_1313 = bits(_T_1312, 0, 0) @[dec_tlu_ctl.scala 2257:62] + node _T_1314 = eq(mhpme_vec[1], UInt<2>("h03")) @[dec_tlu_ctl.scala 2258:34] + node _T_1315 = bits(_T_1314, 0, 0) @[dec_tlu_ctl.scala 2258:62] + node _T_1316 = eq(mhpme_vec[1], UInt<3>("h04")) @[dec_tlu_ctl.scala 2259:34] + node _T_1317 = bits(_T_1316, 0, 0) @[dec_tlu_ctl.scala 2259:62] + node _T_1318 = not(io.illegal_r) @[dec_tlu_ctl.scala 2259:96] + node _T_1319 = and(io.tlu_i0_commit_cmt, _T_1318) @[dec_tlu_ctl.scala 2259:94] + node _T_1320 = eq(mhpme_vec[1], UInt<3>("h05")) @[dec_tlu_ctl.scala 2260:34] + node _T_1321 = bits(_T_1320, 0, 0) @[dec_tlu_ctl.scala 2260:62] + node _T_1322 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2260:96] + node _T_1323 = and(io.tlu_i0_commit_cmt, _T_1322) @[dec_tlu_ctl.scala 2260:94] + node _T_1324 = not(io.illegal_r) @[dec_tlu_ctl.scala 2260:117] + node _T_1325 = and(_T_1323, _T_1324) @[dec_tlu_ctl.scala 2260:115] + node _T_1326 = eq(mhpme_vec[1], UInt<3>("h06")) @[dec_tlu_ctl.scala 2261:34] + node _T_1327 = bits(_T_1326, 0, 0) @[dec_tlu_ctl.scala 2261:62] + node _T_1328 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2261:94] + node _T_1329 = not(io.illegal_r) @[dec_tlu_ctl.scala 2261:117] + node _T_1330 = and(_T_1328, _T_1329) @[dec_tlu_ctl.scala 2261:115] + node _T_1331 = eq(mhpme_vec[1], UInt<3>("h07")) @[dec_tlu_ctl.scala 2262:34] + node _T_1332 = bits(_T_1331, 0, 0) @[dec_tlu_ctl.scala 2262:62] + node _T_1333 = eq(mhpme_vec[1], UInt<4>("h08")) @[dec_tlu_ctl.scala 2263:34] + node _T_1334 = bits(_T_1333, 0, 0) @[dec_tlu_ctl.scala 2263:62] + node _T_1335 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2264:34] + node _T_1336 = bits(_T_1335, 0, 0) @[dec_tlu_ctl.scala 2264:62] + node _T_1337 = eq(mhpme_vec[1], UInt<4>("h09")) @[dec_tlu_ctl.scala 2265:34] + node _T_1338 = bits(_T_1337, 0, 0) @[dec_tlu_ctl.scala 2265:62] + node _T_1339 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2265:91] + node _T_1340 = eq(mhpme_vec[1], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2266:34] + node _T_1341 = bits(_T_1340, 0, 0) @[dec_tlu_ctl.scala 2266:62] + node _T_1342 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2266:105] + node _T_1343 = eq(mhpme_vec[1], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2267:34] + node _T_1344 = bits(_T_1343, 0, 0) @[dec_tlu_ctl.scala 2267:62] + node _T_1345 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2267:91] + node _T_1346 = eq(mhpme_vec[1], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2268:34] + node _T_1347 = bits(_T_1346, 0, 0) @[dec_tlu_ctl.scala 2268:62] + node _T_1348 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2268:91] + node _T_1349 = eq(mhpme_vec[1], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2269:34] + node _T_1350 = bits(_T_1349, 0, 0) @[dec_tlu_ctl.scala 2269:62] + node _T_1351 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2269:91] + node _T_1352 = and(_T_1351, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2269:100] + node _T_1353 = eq(mhpme_vec[1], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2270:34] + node _T_1354 = bits(_T_1353, 0, 0) @[dec_tlu_ctl.scala 2270:62] + node _T_1355 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2270:91] + node _T_1356 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2270:142] + node _T_1357 = and(_T_1355, _T_1356) @[dec_tlu_ctl.scala 2270:101] + node _T_1358 = eq(mhpme_vec[1], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2271:34] + node _T_1359 = bits(_T_1358, 0, 0) @[dec_tlu_ctl.scala 2271:59] + node _T_1360 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2271:89] + node _T_1361 = eq(mhpme_vec[1], UInt<5>("h010")) @[dec_tlu_ctl.scala 2272:34] + node _T_1362 = bits(_T_1361, 0, 0) @[dec_tlu_ctl.scala 2272:59] + node _T_1363 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2272:89] + node _T_1364 = eq(mhpme_vec[1], UInt<5>("h012")) @[dec_tlu_ctl.scala 2273:34] + node _T_1365 = bits(_T_1364, 0, 0) @[dec_tlu_ctl.scala 2273:59] + node _T_1366 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2273:89] + node _T_1367 = eq(mhpme_vec[1], UInt<5>("h011")) @[dec_tlu_ctl.scala 2274:34] + node _T_1368 = bits(_T_1367, 0, 0) @[dec_tlu_ctl.scala 2274:59] + node _T_1369 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2274:89] + node _T_1370 = eq(mhpme_vec[1], UInt<5>("h013")) @[dec_tlu_ctl.scala 2275:34] + node _T_1371 = bits(_T_1370, 0, 0) @[dec_tlu_ctl.scala 2275:59] + node _T_1372 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2275:89] + node _T_1373 = eq(mhpme_vec[1], UInt<5>("h014")) @[dec_tlu_ctl.scala 2276:34] + node _T_1374 = bits(_T_1373, 0, 0) @[dec_tlu_ctl.scala 2276:59] + node _T_1375 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2276:89] + node _T_1376 = eq(mhpme_vec[1], UInt<5>("h015")) @[dec_tlu_ctl.scala 2277:34] + node _T_1377 = bits(_T_1376, 0, 0) @[dec_tlu_ctl.scala 2277:59] + node _T_1378 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2277:89] + node _T_1379 = eq(mhpme_vec[1], UInt<5>("h016")) @[dec_tlu_ctl.scala 2278:34] + node _T_1380 = bits(_T_1379, 0, 0) @[dec_tlu_ctl.scala 2278:59] + node _T_1381 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2278:89] + node _T_1382 = eq(mhpme_vec[1], UInt<5>("h017")) @[dec_tlu_ctl.scala 2279:34] + node _T_1383 = bits(_T_1382, 0, 0) @[dec_tlu_ctl.scala 2279:59] + node _T_1384 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2279:89] + node _T_1385 = eq(mhpme_vec[1], UInt<5>("h018")) @[dec_tlu_ctl.scala 2280:34] + node _T_1386 = bits(_T_1385, 0, 0) @[dec_tlu_ctl.scala 2280:59] + node _T_1387 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2280:89] + node _T_1388 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2280:122] + node _T_1389 = or(_T_1387, _T_1388) @[dec_tlu_ctl.scala 2280:101] + node _T_1390 = eq(mhpme_vec[1], UInt<5>("h019")) @[dec_tlu_ctl.scala 2281:34] + node _T_1391 = bits(_T_1390, 0, 0) @[dec_tlu_ctl.scala 2281:62] + node _T_1392 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2281:95] + node _T_1393 = eq(mhpme_vec[1], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2282:34] + node _T_1394 = bits(_T_1393, 0, 0) @[dec_tlu_ctl.scala 2282:62] + node _T_1395 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2282:97] + node _T_1396 = eq(mhpme_vec[1], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2283:34] + node _T_1397 = bits(_T_1396, 0, 0) @[dec_tlu_ctl.scala 2283:62] + node _T_1398 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2283:110] + node _T_1399 = eq(mhpme_vec[1], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2284:34] + node _T_1400 = bits(_T_1399, 0, 0) @[dec_tlu_ctl.scala 2284:62] + node _T_1401 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2285:34] + node _T_1402 = bits(_T_1401, 0, 0) @[dec_tlu_ctl.scala 2285:62] + node _T_1403 = eq(mhpme_vec[1], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2286:34] + node _T_1404 = bits(_T_1403, 0, 0) @[dec_tlu_ctl.scala 2286:62] + node _T_1405 = eq(mhpme_vec[1], UInt<6>("h020")) @[dec_tlu_ctl.scala 2287:34] + node _T_1406 = bits(_T_1405, 0, 0) @[dec_tlu_ctl.scala 2287:62] + node _T_1407 = eq(mhpme_vec[1], UInt<6>("h022")) @[dec_tlu_ctl.scala 2288:34] + node _T_1408 = bits(_T_1407, 0, 0) @[dec_tlu_ctl.scala 2288:62] + node _T_1409 = eq(mhpme_vec[1], UInt<6>("h023")) @[dec_tlu_ctl.scala 2289:34] + node _T_1410 = bits(_T_1409, 0, 0) @[dec_tlu_ctl.scala 2289:62] + node _T_1411 = eq(mhpme_vec[1], UInt<6>("h024")) @[dec_tlu_ctl.scala 2290:34] + node _T_1412 = bits(_T_1411, 0, 0) @[dec_tlu_ctl.scala 2290:62] + node _T_1413 = eq(mhpme_vec[1], UInt<6>("h025")) @[dec_tlu_ctl.scala 2291:34] + node _T_1414 = bits(_T_1413, 0, 0) @[dec_tlu_ctl.scala 2291:62] + node _T_1415 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2291:98] + node _T_1416 = or(_T_1415, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2291:120] + node _T_1417 = eq(mhpme_vec[1], UInt<6>("h026")) @[dec_tlu_ctl.scala 2292:34] + node _T_1418 = bits(_T_1417, 0, 0) @[dec_tlu_ctl.scala 2292:62] + node _T_1419 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2292:92] + node _T_1420 = or(_T_1419, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2292:117] + node _T_1421 = eq(mhpme_vec[1], UInt<6>("h027")) @[dec_tlu_ctl.scala 2293:34] + node _T_1422 = bits(_T_1421, 0, 0) @[dec_tlu_ctl.scala 2293:62] + node _T_1423 = eq(mhpme_vec[1], UInt<6>("h028")) @[dec_tlu_ctl.scala 2294:34] + node _T_1424 = bits(_T_1423, 0, 0) @[dec_tlu_ctl.scala 2294:62] + node _T_1425 = eq(mhpme_vec[1], UInt<6>("h029")) @[dec_tlu_ctl.scala 2295:34] + node _T_1426 = bits(_T_1425, 0, 0) @[dec_tlu_ctl.scala 2295:62] + node _T_1427 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2295:97] + node _T_1428 = and(_T_1427, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2295:129] + node _T_1429 = eq(mhpme_vec[1], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2296:34] + node _T_1430 = bits(_T_1429, 0, 0) @[dec_tlu_ctl.scala 2296:62] + node _T_1431 = eq(mhpme_vec[1], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2297:34] + node _T_1432 = bits(_T_1431, 0, 0) @[dec_tlu_ctl.scala 2297:62] + node _T_1433 = eq(mhpme_vec[1], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2298:34] + node _T_1434 = bits(_T_1433, 0, 0) @[dec_tlu_ctl.scala 2298:62] + node _T_1435 = eq(mhpme_vec[1], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2299:34] + node _T_1436 = bits(_T_1435, 0, 0) @[dec_tlu_ctl.scala 2299:62] + node _T_1437 = eq(mhpme_vec[1], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2300:34] + node _T_1438 = bits(_T_1437, 0, 0) @[dec_tlu_ctl.scala 2300:62] + node _T_1439 = eq(mhpme_vec[1], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2301:34] + node _T_1440 = bits(_T_1439, 0, 0) @[dec_tlu_ctl.scala 2301:62] + node _T_1441 = eq(mhpme_vec[1], UInt<6>("h030")) @[dec_tlu_ctl.scala 2302:34] + node _T_1442 = bits(_T_1441, 0, 0) @[dec_tlu_ctl.scala 2302:62] + node _T_1443 = eq(mhpme_vec[1], UInt<6>("h031")) @[dec_tlu_ctl.scala 2303:34] + node _T_1444 = bits(_T_1443, 0, 0) @[dec_tlu_ctl.scala 2303:62] + node _T_1445 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2303:84] + node _T_1446 = bits(_T_1445, 0, 0) @[dec_tlu_ctl.scala 2303:84] + node _T_1447 = not(_T_1446) @[dec_tlu_ctl.scala 2303:73] + node _T_1448 = eq(mhpme_vec[1], UInt<6>("h032")) @[dec_tlu_ctl.scala 2304:34] + node _T_1449 = bits(_T_1448, 0, 0) @[dec_tlu_ctl.scala 2304:62] + node _T_1450 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2304:84] + node _T_1451 = bits(_T_1450, 0, 0) @[dec_tlu_ctl.scala 2304:84] + node _T_1452 = not(_T_1451) @[dec_tlu_ctl.scala 2304:73] + node _T_1453 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2304:107] + node _T_1454 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2304:118] + node _T_1455 = and(_T_1453, _T_1454) @[dec_tlu_ctl.scala 2304:113] + node _T_1456 = orr(_T_1455) @[dec_tlu_ctl.scala 2304:125] + node _T_1457 = and(_T_1452, _T_1456) @[dec_tlu_ctl.scala 2304:98] + node _T_1458 = eq(mhpme_vec[1], UInt<6>("h036")) @[dec_tlu_ctl.scala 2305:34] + node _T_1459 = bits(_T_1458, 0, 0) @[dec_tlu_ctl.scala 2305:62] + node _T_1460 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2305:91] + node _T_1461 = eq(mhpme_vec[1], UInt<6>("h037")) @[dec_tlu_ctl.scala 2306:34] + node _T_1462 = bits(_T_1461, 0, 0) @[dec_tlu_ctl.scala 2306:62] + node _T_1463 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2306:94] + node _T_1464 = eq(mhpme_vec[1], UInt<6>("h038")) @[dec_tlu_ctl.scala 2307:34] + node _T_1465 = bits(_T_1464, 0, 0) @[dec_tlu_ctl.scala 2307:62] + node _T_1466 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2307:94] + node _T_1467 = eq(mhpme_vec[1], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2309:34] + node _T_1468 = bits(_T_1467, 0, 0) @[dec_tlu_ctl.scala 2309:62] + node _T_1469 = eq(mhpme_vec[1], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2310:34] + node _T_1470 = bits(_T_1469, 0, 0) @[dec_tlu_ctl.scala 2310:62] + node _T_1471 = eq(mhpme_vec[1], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2311:34] + node _T_1472 = bits(_T_1471, 0, 0) @[dec_tlu_ctl.scala 2311:62] + node _T_1473 = eq(mhpme_vec[1], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2312:34] + node _T_1474 = bits(_T_1473, 0, 0) @[dec_tlu_ctl.scala 2312:62] + node _T_1475 = eq(mhpme_vec[1], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2313:34] + node _T_1476 = bits(_T_1475, 0, 0) @[dec_tlu_ctl.scala 2313:62] + node _T_1477 = mux(_T_1311, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1478 = mux(_T_1313, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1479 = mux(_T_1315, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1480 = mux(_T_1317, _T_1319, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1481 = mux(_T_1321, _T_1325, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1482 = mux(_T_1327, _T_1330, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1483 = mux(_T_1332, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1484 = mux(_T_1334, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1485 = mux(_T_1336, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1486 = mux(_T_1338, _T_1339, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1487 = mux(_T_1341, _T_1342, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1488 = mux(_T_1344, _T_1345, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1489 = mux(_T_1347, _T_1348, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1490 = mux(_T_1350, _T_1352, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1491 = mux(_T_1354, _T_1357, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1492 = mux(_T_1359, _T_1360, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1493 = mux(_T_1362, _T_1363, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1494 = mux(_T_1365, _T_1366, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1495 = mux(_T_1368, _T_1369, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1496 = mux(_T_1371, _T_1372, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1497 = mux(_T_1374, _T_1375, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1498 = mux(_T_1377, _T_1378, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1499 = mux(_T_1380, _T_1381, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1500 = mux(_T_1383, _T_1384, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1501 = mux(_T_1386, _T_1389, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1502 = mux(_T_1391, _T_1392, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1503 = mux(_T_1394, _T_1395, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1504 = mux(_T_1397, _T_1398, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1505 = mux(_T_1400, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1506 = mux(_T_1402, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1507 = mux(_T_1404, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1508 = mux(_T_1406, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1509 = mux(_T_1408, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1510 = mux(_T_1410, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1511 = mux(_T_1412, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1512 = mux(_T_1414, _T_1416, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1513 = mux(_T_1418, _T_1420, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1514 = mux(_T_1422, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1515 = mux(_T_1424, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1516 = mux(_T_1426, _T_1428, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1517 = mux(_T_1430, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1518 = mux(_T_1432, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1519 = mux(_T_1434, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1520 = mux(_T_1436, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1521 = mux(_T_1438, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1522 = mux(_T_1440, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1523 = mux(_T_1442, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1524 = mux(_T_1444, _T_1447, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1525 = mux(_T_1449, _T_1457, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1526 = mux(_T_1459, _T_1460, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1527 = mux(_T_1462, _T_1463, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1528 = mux(_T_1465, _T_1466, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1529 = mux(_T_1468, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1530 = mux(_T_1470, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1531 = mux(_T_1472, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1532 = mux(_T_1474, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1533 = mux(_T_1476, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1534 = or(_T_1477, _T_1478) @[Mux.scala 27:72] node _T_1535 = or(_T_1534, _T_1479) @[Mux.scala 27:72] node _T_1536 = or(_T_1535, _T_1480) @[Mux.scala 27:72] node _T_1537 = or(_T_1536, _T_1481) @[Mux.scala 27:72] @@ -74971,247 +74971,247 @@ circuit quasar_wrapper : node _T_1577 = or(_T_1576, _T_1521) @[Mux.scala 27:72] node _T_1578 = or(_T_1577, _T_1522) @[Mux.scala 27:72] node _T_1579 = or(_T_1578, _T_1523) @[Mux.scala 27:72] - wire _T_1580 : UInt<1> @[Mux.scala 27:72] - _T_1580 <= _T_1579 @[Mux.scala 27:72] - node _T_1581 = and(_T_1299, _T_1580) @[dec_tlu_ctl.scala 2255:44] - mhpmc_inc_r[1] <= _T_1581 @[dec_tlu_ctl.scala 2255:19] - node _T_1582 = bits(mcountinhibit, 5, 5) @[dec_tlu_ctl.scala 2255:38] - node _T_1583 = not(_T_1582) @[dec_tlu_ctl.scala 2255:24] - node _T_1584 = eq(mhpme_vec[2], UInt<1>("h01")) @[dec_tlu_ctl.scala 2256:34] - node _T_1585 = bits(_T_1584, 0, 0) @[dec_tlu_ctl.scala 2256:62] - node _T_1586 = eq(mhpme_vec[2], UInt<2>("h02")) @[dec_tlu_ctl.scala 2257:34] - node _T_1587 = bits(_T_1586, 0, 0) @[dec_tlu_ctl.scala 2257:62] - node _T_1588 = eq(mhpme_vec[2], UInt<2>("h03")) @[dec_tlu_ctl.scala 2258:34] - node _T_1589 = bits(_T_1588, 0, 0) @[dec_tlu_ctl.scala 2258:62] - node _T_1590 = eq(mhpme_vec[2], UInt<3>("h04")) @[dec_tlu_ctl.scala 2259:34] - node _T_1591 = bits(_T_1590, 0, 0) @[dec_tlu_ctl.scala 2259:62] - node _T_1592 = not(io.illegal_r) @[dec_tlu_ctl.scala 2259:96] - node _T_1593 = and(io.tlu_i0_commit_cmt, _T_1592) @[dec_tlu_ctl.scala 2259:94] - node _T_1594 = eq(mhpme_vec[2], UInt<3>("h05")) @[dec_tlu_ctl.scala 2260:34] - node _T_1595 = bits(_T_1594, 0, 0) @[dec_tlu_ctl.scala 2260:62] - node _T_1596 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2260:96] - node _T_1597 = and(io.tlu_i0_commit_cmt, _T_1596) @[dec_tlu_ctl.scala 2260:94] - node _T_1598 = not(io.illegal_r) @[dec_tlu_ctl.scala 2260:117] - node _T_1599 = and(_T_1597, _T_1598) @[dec_tlu_ctl.scala 2260:115] - node _T_1600 = eq(mhpme_vec[2], UInt<3>("h06")) @[dec_tlu_ctl.scala 2261:34] - node _T_1601 = bits(_T_1600, 0, 0) @[dec_tlu_ctl.scala 2261:62] - node _T_1602 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2261:94] - node _T_1603 = not(io.illegal_r) @[dec_tlu_ctl.scala 2261:117] - node _T_1604 = and(_T_1602, _T_1603) @[dec_tlu_ctl.scala 2261:115] - node _T_1605 = eq(mhpme_vec[2], UInt<3>("h07")) @[dec_tlu_ctl.scala 2262:34] - node _T_1606 = bits(_T_1605, 0, 0) @[dec_tlu_ctl.scala 2262:62] - node _T_1607 = eq(mhpme_vec[2], UInt<4>("h08")) @[dec_tlu_ctl.scala 2263:34] - node _T_1608 = bits(_T_1607, 0, 0) @[dec_tlu_ctl.scala 2263:62] - node _T_1609 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2264:34] - node _T_1610 = bits(_T_1609, 0, 0) @[dec_tlu_ctl.scala 2264:62] - node _T_1611 = eq(mhpme_vec[2], UInt<4>("h09")) @[dec_tlu_ctl.scala 2265:34] - node _T_1612 = bits(_T_1611, 0, 0) @[dec_tlu_ctl.scala 2265:62] - node _T_1613 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2265:91] - node _T_1614 = eq(mhpme_vec[2], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2266:34] - node _T_1615 = bits(_T_1614, 0, 0) @[dec_tlu_ctl.scala 2266:62] - node _T_1616 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2266:105] - node _T_1617 = eq(mhpme_vec[2], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2267:34] - node _T_1618 = bits(_T_1617, 0, 0) @[dec_tlu_ctl.scala 2267:62] - node _T_1619 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2267:91] - node _T_1620 = eq(mhpme_vec[2], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2268:34] - node _T_1621 = bits(_T_1620, 0, 0) @[dec_tlu_ctl.scala 2268:62] - node _T_1622 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2268:91] - node _T_1623 = eq(mhpme_vec[2], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2269:34] - node _T_1624 = bits(_T_1623, 0, 0) @[dec_tlu_ctl.scala 2269:62] - node _T_1625 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2269:91] - node _T_1626 = and(_T_1625, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2269:100] - node _T_1627 = eq(mhpme_vec[2], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2270:34] - node _T_1628 = bits(_T_1627, 0, 0) @[dec_tlu_ctl.scala 2270:62] - node _T_1629 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2270:91] - node _T_1630 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2270:142] - node _T_1631 = and(_T_1629, _T_1630) @[dec_tlu_ctl.scala 2270:101] - node _T_1632 = eq(mhpme_vec[2], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2271:34] - node _T_1633 = bits(_T_1632, 0, 0) @[dec_tlu_ctl.scala 2271:59] - node _T_1634 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2271:89] - node _T_1635 = eq(mhpme_vec[2], UInt<5>("h010")) @[dec_tlu_ctl.scala 2272:34] - node _T_1636 = bits(_T_1635, 0, 0) @[dec_tlu_ctl.scala 2272:59] - node _T_1637 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2272:89] - node _T_1638 = eq(mhpme_vec[2], UInt<5>("h012")) @[dec_tlu_ctl.scala 2273:34] - node _T_1639 = bits(_T_1638, 0, 0) @[dec_tlu_ctl.scala 2273:59] - node _T_1640 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2273:89] - node _T_1641 = eq(mhpme_vec[2], UInt<5>("h011")) @[dec_tlu_ctl.scala 2274:34] - node _T_1642 = bits(_T_1641, 0, 0) @[dec_tlu_ctl.scala 2274:59] - node _T_1643 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2274:89] - node _T_1644 = eq(mhpme_vec[2], UInt<5>("h013")) @[dec_tlu_ctl.scala 2275:34] - node _T_1645 = bits(_T_1644, 0, 0) @[dec_tlu_ctl.scala 2275:59] - node _T_1646 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2275:89] - node _T_1647 = eq(mhpme_vec[2], UInt<5>("h014")) @[dec_tlu_ctl.scala 2276:34] - node _T_1648 = bits(_T_1647, 0, 0) @[dec_tlu_ctl.scala 2276:59] - node _T_1649 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2276:89] - node _T_1650 = eq(mhpme_vec[2], UInt<5>("h015")) @[dec_tlu_ctl.scala 2277:34] - node _T_1651 = bits(_T_1650, 0, 0) @[dec_tlu_ctl.scala 2277:59] - node _T_1652 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2277:89] - node _T_1653 = eq(mhpme_vec[2], UInt<5>("h016")) @[dec_tlu_ctl.scala 2278:34] - node _T_1654 = bits(_T_1653, 0, 0) @[dec_tlu_ctl.scala 2278:59] - node _T_1655 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2278:89] - node _T_1656 = eq(mhpme_vec[2], UInt<5>("h017")) @[dec_tlu_ctl.scala 2279:34] - node _T_1657 = bits(_T_1656, 0, 0) @[dec_tlu_ctl.scala 2279:59] - node _T_1658 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2279:89] - node _T_1659 = eq(mhpme_vec[2], UInt<5>("h018")) @[dec_tlu_ctl.scala 2280:34] - node _T_1660 = bits(_T_1659, 0, 0) @[dec_tlu_ctl.scala 2280:59] - node _T_1661 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2280:89] - node _T_1662 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2280:122] - node _T_1663 = or(_T_1661, _T_1662) @[dec_tlu_ctl.scala 2280:101] - node _T_1664 = eq(mhpme_vec[2], UInt<5>("h019")) @[dec_tlu_ctl.scala 2281:34] - node _T_1665 = bits(_T_1664, 0, 0) @[dec_tlu_ctl.scala 2281:62] - node _T_1666 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2281:95] - node _T_1667 = eq(mhpme_vec[2], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2282:34] - node _T_1668 = bits(_T_1667, 0, 0) @[dec_tlu_ctl.scala 2282:62] - node _T_1669 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2282:97] - node _T_1670 = eq(mhpme_vec[2], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2283:34] - node _T_1671 = bits(_T_1670, 0, 0) @[dec_tlu_ctl.scala 2283:62] - node _T_1672 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2283:110] - node _T_1673 = eq(mhpme_vec[2], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2284:34] - node _T_1674 = bits(_T_1673, 0, 0) @[dec_tlu_ctl.scala 2284:62] - node _T_1675 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2285:34] - node _T_1676 = bits(_T_1675, 0, 0) @[dec_tlu_ctl.scala 2285:62] - node _T_1677 = eq(mhpme_vec[2], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2286:34] - node _T_1678 = bits(_T_1677, 0, 0) @[dec_tlu_ctl.scala 2286:62] - node _T_1679 = eq(mhpme_vec[2], UInt<6>("h020")) @[dec_tlu_ctl.scala 2287:34] - node _T_1680 = bits(_T_1679, 0, 0) @[dec_tlu_ctl.scala 2287:62] - node _T_1681 = eq(mhpme_vec[2], UInt<6>("h022")) @[dec_tlu_ctl.scala 2288:34] - node _T_1682 = bits(_T_1681, 0, 0) @[dec_tlu_ctl.scala 2288:62] - node _T_1683 = eq(mhpme_vec[2], UInt<6>("h023")) @[dec_tlu_ctl.scala 2289:34] - node _T_1684 = bits(_T_1683, 0, 0) @[dec_tlu_ctl.scala 2289:62] - node _T_1685 = eq(mhpme_vec[2], UInt<6>("h024")) @[dec_tlu_ctl.scala 2290:34] - node _T_1686 = bits(_T_1685, 0, 0) @[dec_tlu_ctl.scala 2290:62] - node _T_1687 = eq(mhpme_vec[2], UInt<6>("h025")) @[dec_tlu_ctl.scala 2291:34] - node _T_1688 = bits(_T_1687, 0, 0) @[dec_tlu_ctl.scala 2291:62] - node _T_1689 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2291:98] - node _T_1690 = or(_T_1689, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2291:120] - node _T_1691 = eq(mhpme_vec[2], UInt<6>("h026")) @[dec_tlu_ctl.scala 2292:34] - node _T_1692 = bits(_T_1691, 0, 0) @[dec_tlu_ctl.scala 2292:62] - node _T_1693 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2292:92] - node _T_1694 = or(_T_1693, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2292:117] - node _T_1695 = eq(mhpme_vec[2], UInt<6>("h027")) @[dec_tlu_ctl.scala 2293:34] - node _T_1696 = bits(_T_1695, 0, 0) @[dec_tlu_ctl.scala 2293:62] - node _T_1697 = eq(mhpme_vec[2], UInt<6>("h028")) @[dec_tlu_ctl.scala 2294:34] - node _T_1698 = bits(_T_1697, 0, 0) @[dec_tlu_ctl.scala 2294:62] - node _T_1699 = eq(mhpme_vec[2], UInt<6>("h029")) @[dec_tlu_ctl.scala 2295:34] - node _T_1700 = bits(_T_1699, 0, 0) @[dec_tlu_ctl.scala 2295:62] - node _T_1701 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2295:97] - node _T_1702 = and(_T_1701, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2295:129] - node _T_1703 = eq(mhpme_vec[2], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2296:34] - node _T_1704 = bits(_T_1703, 0, 0) @[dec_tlu_ctl.scala 2296:62] - node _T_1705 = eq(mhpme_vec[2], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2297:34] - node _T_1706 = bits(_T_1705, 0, 0) @[dec_tlu_ctl.scala 2297:62] - node _T_1707 = eq(mhpme_vec[2], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2298:34] - node _T_1708 = bits(_T_1707, 0, 0) @[dec_tlu_ctl.scala 2298:62] - node _T_1709 = eq(mhpme_vec[2], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2299:34] - node _T_1710 = bits(_T_1709, 0, 0) @[dec_tlu_ctl.scala 2299:62] - node _T_1711 = eq(mhpme_vec[2], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2300:34] - node _T_1712 = bits(_T_1711, 0, 0) @[dec_tlu_ctl.scala 2300:62] - node _T_1713 = eq(mhpme_vec[2], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2301:34] - node _T_1714 = bits(_T_1713, 0, 0) @[dec_tlu_ctl.scala 2301:62] - node _T_1715 = eq(mhpme_vec[2], UInt<6>("h030")) @[dec_tlu_ctl.scala 2302:34] - node _T_1716 = bits(_T_1715, 0, 0) @[dec_tlu_ctl.scala 2302:62] - node _T_1717 = eq(mhpme_vec[2], UInt<6>("h031")) @[dec_tlu_ctl.scala 2303:34] - node _T_1718 = bits(_T_1717, 0, 0) @[dec_tlu_ctl.scala 2303:62] - node _T_1719 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2303:84] - node _T_1720 = bits(_T_1719, 0, 0) @[dec_tlu_ctl.scala 2303:84] - node _T_1721 = not(_T_1720) @[dec_tlu_ctl.scala 2303:73] - node _T_1722 = eq(mhpme_vec[2], UInt<6>("h032")) @[dec_tlu_ctl.scala 2304:34] - node _T_1723 = bits(_T_1722, 0, 0) @[dec_tlu_ctl.scala 2304:62] - node _T_1724 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2304:84] - node _T_1725 = bits(_T_1724, 0, 0) @[dec_tlu_ctl.scala 2304:84] - node _T_1726 = not(_T_1725) @[dec_tlu_ctl.scala 2304:73] - node _T_1727 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2304:107] - node _T_1728 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2304:118] - node _T_1729 = and(_T_1727, _T_1728) @[dec_tlu_ctl.scala 2304:113] - node _T_1730 = orr(_T_1729) @[dec_tlu_ctl.scala 2304:125] - node _T_1731 = and(_T_1726, _T_1730) @[dec_tlu_ctl.scala 2304:98] - node _T_1732 = eq(mhpme_vec[2], UInt<6>("h036")) @[dec_tlu_ctl.scala 2305:34] - node _T_1733 = bits(_T_1732, 0, 0) @[dec_tlu_ctl.scala 2305:62] - node _T_1734 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2305:91] - node _T_1735 = eq(mhpme_vec[2], UInt<6>("h037")) @[dec_tlu_ctl.scala 2306:34] - node _T_1736 = bits(_T_1735, 0, 0) @[dec_tlu_ctl.scala 2306:62] - node _T_1737 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2306:94] - node _T_1738 = eq(mhpme_vec[2], UInt<6>("h038")) @[dec_tlu_ctl.scala 2307:34] - node _T_1739 = bits(_T_1738, 0, 0) @[dec_tlu_ctl.scala 2307:62] - node _T_1740 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2307:94] - node _T_1741 = eq(mhpme_vec[2], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2309:34] - node _T_1742 = bits(_T_1741, 0, 0) @[dec_tlu_ctl.scala 2309:62] - node _T_1743 = eq(mhpme_vec[2], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2310:34] - node _T_1744 = bits(_T_1743, 0, 0) @[dec_tlu_ctl.scala 2310:62] - node _T_1745 = eq(mhpme_vec[2], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2311:34] - node _T_1746 = bits(_T_1745, 0, 0) @[dec_tlu_ctl.scala 2311:62] - node _T_1747 = eq(mhpme_vec[2], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2312:34] - node _T_1748 = bits(_T_1747, 0, 0) @[dec_tlu_ctl.scala 2312:62] - node _T_1749 = eq(mhpme_vec[2], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2313:34] - node _T_1750 = bits(_T_1749, 0, 0) @[dec_tlu_ctl.scala 2313:62] - node _T_1751 = mux(_T_1585, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1752 = mux(_T_1587, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1753 = mux(_T_1589, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1754 = mux(_T_1591, _T_1593, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1755 = mux(_T_1595, _T_1599, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1756 = mux(_T_1601, _T_1604, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1757 = mux(_T_1606, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1758 = mux(_T_1608, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1759 = mux(_T_1610, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1760 = mux(_T_1612, _T_1613, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1761 = mux(_T_1615, _T_1616, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1762 = mux(_T_1618, _T_1619, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1763 = mux(_T_1621, _T_1622, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1764 = mux(_T_1624, _T_1626, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1765 = mux(_T_1628, _T_1631, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1766 = mux(_T_1633, _T_1634, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1767 = mux(_T_1636, _T_1637, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1768 = mux(_T_1639, _T_1640, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1769 = mux(_T_1642, _T_1643, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1770 = mux(_T_1645, _T_1646, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1771 = mux(_T_1648, _T_1649, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1772 = mux(_T_1651, _T_1652, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1773 = mux(_T_1654, _T_1655, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1774 = mux(_T_1657, _T_1658, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1775 = mux(_T_1660, _T_1663, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1776 = mux(_T_1665, _T_1666, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1777 = mux(_T_1668, _T_1669, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1778 = mux(_T_1671, _T_1672, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1779 = mux(_T_1674, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1780 = mux(_T_1676, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1781 = mux(_T_1678, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1782 = mux(_T_1680, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1783 = mux(_T_1682, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1784 = mux(_T_1684, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1785 = mux(_T_1686, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1786 = mux(_T_1688, _T_1690, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1787 = mux(_T_1692, _T_1694, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1788 = mux(_T_1696, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1789 = mux(_T_1698, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1790 = mux(_T_1700, _T_1702, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1791 = mux(_T_1704, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1792 = mux(_T_1706, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1793 = mux(_T_1708, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1794 = mux(_T_1710, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1795 = mux(_T_1712, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1796 = mux(_T_1714, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1797 = mux(_T_1716, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1798 = mux(_T_1718, _T_1721, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1799 = mux(_T_1723, _T_1731, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1800 = mux(_T_1733, _T_1734, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1801 = mux(_T_1736, _T_1737, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1802 = mux(_T_1739, _T_1740, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1803 = mux(_T_1742, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1804 = mux(_T_1744, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1805 = mux(_T_1746, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1806 = mux(_T_1748, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1807 = mux(_T_1750, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1808 = or(_T_1751, _T_1752) @[Mux.scala 27:72] - node _T_1809 = or(_T_1808, _T_1753) @[Mux.scala 27:72] - node _T_1810 = or(_T_1809, _T_1754) @[Mux.scala 27:72] - node _T_1811 = or(_T_1810, _T_1755) @[Mux.scala 27:72] - node _T_1812 = or(_T_1811, _T_1756) @[Mux.scala 27:72] - node _T_1813 = or(_T_1812, _T_1757) @[Mux.scala 27:72] - node _T_1814 = or(_T_1813, _T_1758) @[Mux.scala 27:72] - node _T_1815 = or(_T_1814, _T_1759) @[Mux.scala 27:72] - node _T_1816 = or(_T_1815, _T_1760) @[Mux.scala 27:72] - node _T_1817 = or(_T_1816, _T_1761) @[Mux.scala 27:72] - node _T_1818 = or(_T_1817, _T_1762) @[Mux.scala 27:72] + node _T_1580 = or(_T_1579, _T_1524) @[Mux.scala 27:72] + node _T_1581 = or(_T_1580, _T_1525) @[Mux.scala 27:72] + node _T_1582 = or(_T_1581, _T_1526) @[Mux.scala 27:72] + node _T_1583 = or(_T_1582, _T_1527) @[Mux.scala 27:72] + node _T_1584 = or(_T_1583, _T_1528) @[Mux.scala 27:72] + node _T_1585 = or(_T_1584, _T_1529) @[Mux.scala 27:72] + node _T_1586 = or(_T_1585, _T_1530) @[Mux.scala 27:72] + node _T_1587 = or(_T_1586, _T_1531) @[Mux.scala 27:72] + node _T_1588 = or(_T_1587, _T_1532) @[Mux.scala 27:72] + node _T_1589 = or(_T_1588, _T_1533) @[Mux.scala 27:72] + wire _T_1590 : UInt<1> @[Mux.scala 27:72] + _T_1590 <= _T_1589 @[Mux.scala 27:72] + node _T_1591 = and(_T_1309, _T_1590) @[dec_tlu_ctl.scala 2255:44] + mhpmc_inc_r[1] <= _T_1591 @[dec_tlu_ctl.scala 2255:19] + node _T_1592 = bits(mcountinhibit, 5, 5) @[dec_tlu_ctl.scala 2255:38] + node _T_1593 = not(_T_1592) @[dec_tlu_ctl.scala 2255:24] + node _T_1594 = eq(mhpme_vec[2], UInt<1>("h01")) @[dec_tlu_ctl.scala 2256:34] + node _T_1595 = bits(_T_1594, 0, 0) @[dec_tlu_ctl.scala 2256:62] + node _T_1596 = eq(mhpme_vec[2], UInt<2>("h02")) @[dec_tlu_ctl.scala 2257:34] + node _T_1597 = bits(_T_1596, 0, 0) @[dec_tlu_ctl.scala 2257:62] + node _T_1598 = eq(mhpme_vec[2], UInt<2>("h03")) @[dec_tlu_ctl.scala 2258:34] + node _T_1599 = bits(_T_1598, 0, 0) @[dec_tlu_ctl.scala 2258:62] + node _T_1600 = eq(mhpme_vec[2], UInt<3>("h04")) @[dec_tlu_ctl.scala 2259:34] + node _T_1601 = bits(_T_1600, 0, 0) @[dec_tlu_ctl.scala 2259:62] + node _T_1602 = not(io.illegal_r) @[dec_tlu_ctl.scala 2259:96] + node _T_1603 = and(io.tlu_i0_commit_cmt, _T_1602) @[dec_tlu_ctl.scala 2259:94] + node _T_1604 = eq(mhpme_vec[2], UInt<3>("h05")) @[dec_tlu_ctl.scala 2260:34] + node _T_1605 = bits(_T_1604, 0, 0) @[dec_tlu_ctl.scala 2260:62] + node _T_1606 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2260:96] + node _T_1607 = and(io.tlu_i0_commit_cmt, _T_1606) @[dec_tlu_ctl.scala 2260:94] + node _T_1608 = not(io.illegal_r) @[dec_tlu_ctl.scala 2260:117] + node _T_1609 = and(_T_1607, _T_1608) @[dec_tlu_ctl.scala 2260:115] + node _T_1610 = eq(mhpme_vec[2], UInt<3>("h06")) @[dec_tlu_ctl.scala 2261:34] + node _T_1611 = bits(_T_1610, 0, 0) @[dec_tlu_ctl.scala 2261:62] + node _T_1612 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2261:94] + node _T_1613 = not(io.illegal_r) @[dec_tlu_ctl.scala 2261:117] + node _T_1614 = and(_T_1612, _T_1613) @[dec_tlu_ctl.scala 2261:115] + node _T_1615 = eq(mhpme_vec[2], UInt<3>("h07")) @[dec_tlu_ctl.scala 2262:34] + node _T_1616 = bits(_T_1615, 0, 0) @[dec_tlu_ctl.scala 2262:62] + node _T_1617 = eq(mhpme_vec[2], UInt<4>("h08")) @[dec_tlu_ctl.scala 2263:34] + node _T_1618 = bits(_T_1617, 0, 0) @[dec_tlu_ctl.scala 2263:62] + node _T_1619 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2264:34] + node _T_1620 = bits(_T_1619, 0, 0) @[dec_tlu_ctl.scala 2264:62] + node _T_1621 = eq(mhpme_vec[2], UInt<4>("h09")) @[dec_tlu_ctl.scala 2265:34] + node _T_1622 = bits(_T_1621, 0, 0) @[dec_tlu_ctl.scala 2265:62] + node _T_1623 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2265:91] + node _T_1624 = eq(mhpme_vec[2], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2266:34] + node _T_1625 = bits(_T_1624, 0, 0) @[dec_tlu_ctl.scala 2266:62] + node _T_1626 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2266:105] + node _T_1627 = eq(mhpme_vec[2], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2267:34] + node _T_1628 = bits(_T_1627, 0, 0) @[dec_tlu_ctl.scala 2267:62] + node _T_1629 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2267:91] + node _T_1630 = eq(mhpme_vec[2], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2268:34] + node _T_1631 = bits(_T_1630, 0, 0) @[dec_tlu_ctl.scala 2268:62] + node _T_1632 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2268:91] + node _T_1633 = eq(mhpme_vec[2], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2269:34] + node _T_1634 = bits(_T_1633, 0, 0) @[dec_tlu_ctl.scala 2269:62] + node _T_1635 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2269:91] + node _T_1636 = and(_T_1635, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2269:100] + node _T_1637 = eq(mhpme_vec[2], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2270:34] + node _T_1638 = bits(_T_1637, 0, 0) @[dec_tlu_ctl.scala 2270:62] + node _T_1639 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2270:91] + node _T_1640 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2270:142] + node _T_1641 = and(_T_1639, _T_1640) @[dec_tlu_ctl.scala 2270:101] + node _T_1642 = eq(mhpme_vec[2], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2271:34] + node _T_1643 = bits(_T_1642, 0, 0) @[dec_tlu_ctl.scala 2271:59] + node _T_1644 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2271:89] + node _T_1645 = eq(mhpme_vec[2], UInt<5>("h010")) @[dec_tlu_ctl.scala 2272:34] + node _T_1646 = bits(_T_1645, 0, 0) @[dec_tlu_ctl.scala 2272:59] + node _T_1647 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2272:89] + node _T_1648 = eq(mhpme_vec[2], UInt<5>("h012")) @[dec_tlu_ctl.scala 2273:34] + node _T_1649 = bits(_T_1648, 0, 0) @[dec_tlu_ctl.scala 2273:59] + node _T_1650 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2273:89] + node _T_1651 = eq(mhpme_vec[2], UInt<5>("h011")) @[dec_tlu_ctl.scala 2274:34] + node _T_1652 = bits(_T_1651, 0, 0) @[dec_tlu_ctl.scala 2274:59] + node _T_1653 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2274:89] + node _T_1654 = eq(mhpme_vec[2], UInt<5>("h013")) @[dec_tlu_ctl.scala 2275:34] + node _T_1655 = bits(_T_1654, 0, 0) @[dec_tlu_ctl.scala 2275:59] + node _T_1656 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2275:89] + node _T_1657 = eq(mhpme_vec[2], UInt<5>("h014")) @[dec_tlu_ctl.scala 2276:34] + node _T_1658 = bits(_T_1657, 0, 0) @[dec_tlu_ctl.scala 2276:59] + node _T_1659 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2276:89] + node _T_1660 = eq(mhpme_vec[2], UInt<5>("h015")) @[dec_tlu_ctl.scala 2277:34] + node _T_1661 = bits(_T_1660, 0, 0) @[dec_tlu_ctl.scala 2277:59] + node _T_1662 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2277:89] + node _T_1663 = eq(mhpme_vec[2], UInt<5>("h016")) @[dec_tlu_ctl.scala 2278:34] + node _T_1664 = bits(_T_1663, 0, 0) @[dec_tlu_ctl.scala 2278:59] + node _T_1665 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2278:89] + node _T_1666 = eq(mhpme_vec[2], UInt<5>("h017")) @[dec_tlu_ctl.scala 2279:34] + node _T_1667 = bits(_T_1666, 0, 0) @[dec_tlu_ctl.scala 2279:59] + node _T_1668 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2279:89] + node _T_1669 = eq(mhpme_vec[2], UInt<5>("h018")) @[dec_tlu_ctl.scala 2280:34] + node _T_1670 = bits(_T_1669, 0, 0) @[dec_tlu_ctl.scala 2280:59] + node _T_1671 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2280:89] + node _T_1672 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2280:122] + node _T_1673 = or(_T_1671, _T_1672) @[dec_tlu_ctl.scala 2280:101] + node _T_1674 = eq(mhpme_vec[2], UInt<5>("h019")) @[dec_tlu_ctl.scala 2281:34] + node _T_1675 = bits(_T_1674, 0, 0) @[dec_tlu_ctl.scala 2281:62] + node _T_1676 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2281:95] + node _T_1677 = eq(mhpme_vec[2], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2282:34] + node _T_1678 = bits(_T_1677, 0, 0) @[dec_tlu_ctl.scala 2282:62] + node _T_1679 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2282:97] + node _T_1680 = eq(mhpme_vec[2], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2283:34] + node _T_1681 = bits(_T_1680, 0, 0) @[dec_tlu_ctl.scala 2283:62] + node _T_1682 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2283:110] + node _T_1683 = eq(mhpme_vec[2], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2284:34] + node _T_1684 = bits(_T_1683, 0, 0) @[dec_tlu_ctl.scala 2284:62] + node _T_1685 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2285:34] + node _T_1686 = bits(_T_1685, 0, 0) @[dec_tlu_ctl.scala 2285:62] + node _T_1687 = eq(mhpme_vec[2], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2286:34] + node _T_1688 = bits(_T_1687, 0, 0) @[dec_tlu_ctl.scala 2286:62] + node _T_1689 = eq(mhpme_vec[2], UInt<6>("h020")) @[dec_tlu_ctl.scala 2287:34] + node _T_1690 = bits(_T_1689, 0, 0) @[dec_tlu_ctl.scala 2287:62] + node _T_1691 = eq(mhpme_vec[2], UInt<6>("h022")) @[dec_tlu_ctl.scala 2288:34] + node _T_1692 = bits(_T_1691, 0, 0) @[dec_tlu_ctl.scala 2288:62] + node _T_1693 = eq(mhpme_vec[2], UInt<6>("h023")) @[dec_tlu_ctl.scala 2289:34] + node _T_1694 = bits(_T_1693, 0, 0) @[dec_tlu_ctl.scala 2289:62] + node _T_1695 = eq(mhpme_vec[2], UInt<6>("h024")) @[dec_tlu_ctl.scala 2290:34] + node _T_1696 = bits(_T_1695, 0, 0) @[dec_tlu_ctl.scala 2290:62] + node _T_1697 = eq(mhpme_vec[2], UInt<6>("h025")) @[dec_tlu_ctl.scala 2291:34] + node _T_1698 = bits(_T_1697, 0, 0) @[dec_tlu_ctl.scala 2291:62] + node _T_1699 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2291:98] + node _T_1700 = or(_T_1699, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2291:120] + node _T_1701 = eq(mhpme_vec[2], UInt<6>("h026")) @[dec_tlu_ctl.scala 2292:34] + node _T_1702 = bits(_T_1701, 0, 0) @[dec_tlu_ctl.scala 2292:62] + node _T_1703 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2292:92] + node _T_1704 = or(_T_1703, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2292:117] + node _T_1705 = eq(mhpme_vec[2], UInt<6>("h027")) @[dec_tlu_ctl.scala 2293:34] + node _T_1706 = bits(_T_1705, 0, 0) @[dec_tlu_ctl.scala 2293:62] + node _T_1707 = eq(mhpme_vec[2], UInt<6>("h028")) @[dec_tlu_ctl.scala 2294:34] + node _T_1708 = bits(_T_1707, 0, 0) @[dec_tlu_ctl.scala 2294:62] + node _T_1709 = eq(mhpme_vec[2], UInt<6>("h029")) @[dec_tlu_ctl.scala 2295:34] + node _T_1710 = bits(_T_1709, 0, 0) @[dec_tlu_ctl.scala 2295:62] + node _T_1711 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2295:97] + node _T_1712 = and(_T_1711, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2295:129] + node _T_1713 = eq(mhpme_vec[2], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2296:34] + node _T_1714 = bits(_T_1713, 0, 0) @[dec_tlu_ctl.scala 2296:62] + node _T_1715 = eq(mhpme_vec[2], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2297:34] + node _T_1716 = bits(_T_1715, 0, 0) @[dec_tlu_ctl.scala 2297:62] + node _T_1717 = eq(mhpme_vec[2], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2298:34] + node _T_1718 = bits(_T_1717, 0, 0) @[dec_tlu_ctl.scala 2298:62] + node _T_1719 = eq(mhpme_vec[2], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2299:34] + node _T_1720 = bits(_T_1719, 0, 0) @[dec_tlu_ctl.scala 2299:62] + node _T_1721 = eq(mhpme_vec[2], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2300:34] + node _T_1722 = bits(_T_1721, 0, 0) @[dec_tlu_ctl.scala 2300:62] + node _T_1723 = eq(mhpme_vec[2], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2301:34] + node _T_1724 = bits(_T_1723, 0, 0) @[dec_tlu_ctl.scala 2301:62] + node _T_1725 = eq(mhpme_vec[2], UInt<6>("h030")) @[dec_tlu_ctl.scala 2302:34] + node _T_1726 = bits(_T_1725, 0, 0) @[dec_tlu_ctl.scala 2302:62] + node _T_1727 = eq(mhpme_vec[2], UInt<6>("h031")) @[dec_tlu_ctl.scala 2303:34] + node _T_1728 = bits(_T_1727, 0, 0) @[dec_tlu_ctl.scala 2303:62] + node _T_1729 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2303:84] + node _T_1730 = bits(_T_1729, 0, 0) @[dec_tlu_ctl.scala 2303:84] + node _T_1731 = not(_T_1730) @[dec_tlu_ctl.scala 2303:73] + node _T_1732 = eq(mhpme_vec[2], UInt<6>("h032")) @[dec_tlu_ctl.scala 2304:34] + node _T_1733 = bits(_T_1732, 0, 0) @[dec_tlu_ctl.scala 2304:62] + node _T_1734 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2304:84] + node _T_1735 = bits(_T_1734, 0, 0) @[dec_tlu_ctl.scala 2304:84] + node _T_1736 = not(_T_1735) @[dec_tlu_ctl.scala 2304:73] + node _T_1737 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2304:107] + node _T_1738 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2304:118] + node _T_1739 = and(_T_1737, _T_1738) @[dec_tlu_ctl.scala 2304:113] + node _T_1740 = orr(_T_1739) @[dec_tlu_ctl.scala 2304:125] + node _T_1741 = and(_T_1736, _T_1740) @[dec_tlu_ctl.scala 2304:98] + node _T_1742 = eq(mhpme_vec[2], UInt<6>("h036")) @[dec_tlu_ctl.scala 2305:34] + node _T_1743 = bits(_T_1742, 0, 0) @[dec_tlu_ctl.scala 2305:62] + node _T_1744 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2305:91] + node _T_1745 = eq(mhpme_vec[2], UInt<6>("h037")) @[dec_tlu_ctl.scala 2306:34] + node _T_1746 = bits(_T_1745, 0, 0) @[dec_tlu_ctl.scala 2306:62] + node _T_1747 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2306:94] + node _T_1748 = eq(mhpme_vec[2], UInt<6>("h038")) @[dec_tlu_ctl.scala 2307:34] + node _T_1749 = bits(_T_1748, 0, 0) @[dec_tlu_ctl.scala 2307:62] + node _T_1750 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2307:94] + node _T_1751 = eq(mhpme_vec[2], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2309:34] + node _T_1752 = bits(_T_1751, 0, 0) @[dec_tlu_ctl.scala 2309:62] + node _T_1753 = eq(mhpme_vec[2], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2310:34] + node _T_1754 = bits(_T_1753, 0, 0) @[dec_tlu_ctl.scala 2310:62] + node _T_1755 = eq(mhpme_vec[2], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2311:34] + node _T_1756 = bits(_T_1755, 0, 0) @[dec_tlu_ctl.scala 2311:62] + node _T_1757 = eq(mhpme_vec[2], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2312:34] + node _T_1758 = bits(_T_1757, 0, 0) @[dec_tlu_ctl.scala 2312:62] + node _T_1759 = eq(mhpme_vec[2], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2313:34] + node _T_1760 = bits(_T_1759, 0, 0) @[dec_tlu_ctl.scala 2313:62] + node _T_1761 = mux(_T_1595, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1762 = mux(_T_1597, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1763 = mux(_T_1599, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1764 = mux(_T_1601, _T_1603, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1765 = mux(_T_1605, _T_1609, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1766 = mux(_T_1611, _T_1614, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1767 = mux(_T_1616, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1768 = mux(_T_1618, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1769 = mux(_T_1620, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1770 = mux(_T_1622, _T_1623, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1771 = mux(_T_1625, _T_1626, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1772 = mux(_T_1628, _T_1629, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1773 = mux(_T_1631, _T_1632, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1774 = mux(_T_1634, _T_1636, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1775 = mux(_T_1638, _T_1641, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1776 = mux(_T_1643, _T_1644, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1777 = mux(_T_1646, _T_1647, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1778 = mux(_T_1649, _T_1650, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1779 = mux(_T_1652, _T_1653, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1780 = mux(_T_1655, _T_1656, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1781 = mux(_T_1658, _T_1659, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1782 = mux(_T_1661, _T_1662, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1783 = mux(_T_1664, _T_1665, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1784 = mux(_T_1667, _T_1668, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1785 = mux(_T_1670, _T_1673, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1786 = mux(_T_1675, _T_1676, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1787 = mux(_T_1678, _T_1679, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1788 = mux(_T_1681, _T_1682, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1789 = mux(_T_1684, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1790 = mux(_T_1686, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1791 = mux(_T_1688, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1792 = mux(_T_1690, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1793 = mux(_T_1692, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1794 = mux(_T_1694, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1795 = mux(_T_1696, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1796 = mux(_T_1698, _T_1700, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1797 = mux(_T_1702, _T_1704, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1798 = mux(_T_1706, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1799 = mux(_T_1708, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1800 = mux(_T_1710, _T_1712, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1801 = mux(_T_1714, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1802 = mux(_T_1716, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1803 = mux(_T_1718, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1804 = mux(_T_1720, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1805 = mux(_T_1722, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1806 = mux(_T_1724, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1807 = mux(_T_1726, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1808 = mux(_T_1728, _T_1731, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1809 = mux(_T_1733, _T_1741, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1810 = mux(_T_1743, _T_1744, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1811 = mux(_T_1746, _T_1747, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1812 = mux(_T_1749, _T_1750, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1813 = mux(_T_1752, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1814 = mux(_T_1754, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1815 = mux(_T_1756, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1816 = mux(_T_1758, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1817 = mux(_T_1760, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1818 = or(_T_1761, _T_1762) @[Mux.scala 27:72] node _T_1819 = or(_T_1818, _T_1763) @[Mux.scala 27:72] node _T_1820 = or(_T_1819, _T_1764) @[Mux.scala 27:72] node _T_1821 = or(_T_1820, _T_1765) @[Mux.scala 27:72] @@ -75257,247 +75257,247 @@ circuit quasar_wrapper : node _T_1861 = or(_T_1860, _T_1805) @[Mux.scala 27:72] node _T_1862 = or(_T_1861, _T_1806) @[Mux.scala 27:72] node _T_1863 = or(_T_1862, _T_1807) @[Mux.scala 27:72] - wire _T_1864 : UInt<1> @[Mux.scala 27:72] - _T_1864 <= _T_1863 @[Mux.scala 27:72] - node _T_1865 = and(_T_1583, _T_1864) @[dec_tlu_ctl.scala 2255:44] - mhpmc_inc_r[2] <= _T_1865 @[dec_tlu_ctl.scala 2255:19] - node _T_1866 = bits(mcountinhibit, 6, 6) @[dec_tlu_ctl.scala 2255:38] - node _T_1867 = not(_T_1866) @[dec_tlu_ctl.scala 2255:24] - node _T_1868 = eq(mhpme_vec[3], UInt<1>("h01")) @[dec_tlu_ctl.scala 2256:34] - node _T_1869 = bits(_T_1868, 0, 0) @[dec_tlu_ctl.scala 2256:62] - node _T_1870 = eq(mhpme_vec[3], UInt<2>("h02")) @[dec_tlu_ctl.scala 2257:34] - node _T_1871 = bits(_T_1870, 0, 0) @[dec_tlu_ctl.scala 2257:62] - node _T_1872 = eq(mhpme_vec[3], UInt<2>("h03")) @[dec_tlu_ctl.scala 2258:34] - node _T_1873 = bits(_T_1872, 0, 0) @[dec_tlu_ctl.scala 2258:62] - node _T_1874 = eq(mhpme_vec[3], UInt<3>("h04")) @[dec_tlu_ctl.scala 2259:34] - node _T_1875 = bits(_T_1874, 0, 0) @[dec_tlu_ctl.scala 2259:62] - node _T_1876 = not(io.illegal_r) @[dec_tlu_ctl.scala 2259:96] - node _T_1877 = and(io.tlu_i0_commit_cmt, _T_1876) @[dec_tlu_ctl.scala 2259:94] - node _T_1878 = eq(mhpme_vec[3], UInt<3>("h05")) @[dec_tlu_ctl.scala 2260:34] - node _T_1879 = bits(_T_1878, 0, 0) @[dec_tlu_ctl.scala 2260:62] - node _T_1880 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2260:96] - node _T_1881 = and(io.tlu_i0_commit_cmt, _T_1880) @[dec_tlu_ctl.scala 2260:94] - node _T_1882 = not(io.illegal_r) @[dec_tlu_ctl.scala 2260:117] - node _T_1883 = and(_T_1881, _T_1882) @[dec_tlu_ctl.scala 2260:115] - node _T_1884 = eq(mhpme_vec[3], UInt<3>("h06")) @[dec_tlu_ctl.scala 2261:34] - node _T_1885 = bits(_T_1884, 0, 0) @[dec_tlu_ctl.scala 2261:62] - node _T_1886 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2261:94] - node _T_1887 = not(io.illegal_r) @[dec_tlu_ctl.scala 2261:117] - node _T_1888 = and(_T_1886, _T_1887) @[dec_tlu_ctl.scala 2261:115] - node _T_1889 = eq(mhpme_vec[3], UInt<3>("h07")) @[dec_tlu_ctl.scala 2262:34] - node _T_1890 = bits(_T_1889, 0, 0) @[dec_tlu_ctl.scala 2262:62] - node _T_1891 = eq(mhpme_vec[3], UInt<4>("h08")) @[dec_tlu_ctl.scala 2263:34] - node _T_1892 = bits(_T_1891, 0, 0) @[dec_tlu_ctl.scala 2263:62] - node _T_1893 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2264:34] - node _T_1894 = bits(_T_1893, 0, 0) @[dec_tlu_ctl.scala 2264:62] - node _T_1895 = eq(mhpme_vec[3], UInt<4>("h09")) @[dec_tlu_ctl.scala 2265:34] - node _T_1896 = bits(_T_1895, 0, 0) @[dec_tlu_ctl.scala 2265:62] - node _T_1897 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2265:91] - node _T_1898 = eq(mhpme_vec[3], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2266:34] - node _T_1899 = bits(_T_1898, 0, 0) @[dec_tlu_ctl.scala 2266:62] - node _T_1900 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2266:105] - node _T_1901 = eq(mhpme_vec[3], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2267:34] - node _T_1902 = bits(_T_1901, 0, 0) @[dec_tlu_ctl.scala 2267:62] - node _T_1903 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2267:91] - node _T_1904 = eq(mhpme_vec[3], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2268:34] - node _T_1905 = bits(_T_1904, 0, 0) @[dec_tlu_ctl.scala 2268:62] - node _T_1906 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2268:91] - node _T_1907 = eq(mhpme_vec[3], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2269:34] - node _T_1908 = bits(_T_1907, 0, 0) @[dec_tlu_ctl.scala 2269:62] - node _T_1909 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2269:91] - node _T_1910 = and(_T_1909, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2269:100] - node _T_1911 = eq(mhpme_vec[3], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2270:34] - node _T_1912 = bits(_T_1911, 0, 0) @[dec_tlu_ctl.scala 2270:62] - node _T_1913 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2270:91] - node _T_1914 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2270:142] - node _T_1915 = and(_T_1913, _T_1914) @[dec_tlu_ctl.scala 2270:101] - node _T_1916 = eq(mhpme_vec[3], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2271:34] - node _T_1917 = bits(_T_1916, 0, 0) @[dec_tlu_ctl.scala 2271:59] - node _T_1918 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2271:89] - node _T_1919 = eq(mhpme_vec[3], UInt<5>("h010")) @[dec_tlu_ctl.scala 2272:34] - node _T_1920 = bits(_T_1919, 0, 0) @[dec_tlu_ctl.scala 2272:59] - node _T_1921 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2272:89] - node _T_1922 = eq(mhpme_vec[3], UInt<5>("h012")) @[dec_tlu_ctl.scala 2273:34] - node _T_1923 = bits(_T_1922, 0, 0) @[dec_tlu_ctl.scala 2273:59] - node _T_1924 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2273:89] - node _T_1925 = eq(mhpme_vec[3], UInt<5>("h011")) @[dec_tlu_ctl.scala 2274:34] - node _T_1926 = bits(_T_1925, 0, 0) @[dec_tlu_ctl.scala 2274:59] - node _T_1927 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2274:89] - node _T_1928 = eq(mhpme_vec[3], UInt<5>("h013")) @[dec_tlu_ctl.scala 2275:34] - node _T_1929 = bits(_T_1928, 0, 0) @[dec_tlu_ctl.scala 2275:59] - node _T_1930 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2275:89] - node _T_1931 = eq(mhpme_vec[3], UInt<5>("h014")) @[dec_tlu_ctl.scala 2276:34] - node _T_1932 = bits(_T_1931, 0, 0) @[dec_tlu_ctl.scala 2276:59] - node _T_1933 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2276:89] - node _T_1934 = eq(mhpme_vec[3], UInt<5>("h015")) @[dec_tlu_ctl.scala 2277:34] - node _T_1935 = bits(_T_1934, 0, 0) @[dec_tlu_ctl.scala 2277:59] - node _T_1936 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2277:89] - node _T_1937 = eq(mhpme_vec[3], UInt<5>("h016")) @[dec_tlu_ctl.scala 2278:34] - node _T_1938 = bits(_T_1937, 0, 0) @[dec_tlu_ctl.scala 2278:59] - node _T_1939 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2278:89] - node _T_1940 = eq(mhpme_vec[3], UInt<5>("h017")) @[dec_tlu_ctl.scala 2279:34] - node _T_1941 = bits(_T_1940, 0, 0) @[dec_tlu_ctl.scala 2279:59] - node _T_1942 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2279:89] - node _T_1943 = eq(mhpme_vec[3], UInt<5>("h018")) @[dec_tlu_ctl.scala 2280:34] - node _T_1944 = bits(_T_1943, 0, 0) @[dec_tlu_ctl.scala 2280:59] - node _T_1945 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2280:89] - node _T_1946 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2280:122] - node _T_1947 = or(_T_1945, _T_1946) @[dec_tlu_ctl.scala 2280:101] - node _T_1948 = eq(mhpme_vec[3], UInt<5>("h019")) @[dec_tlu_ctl.scala 2281:34] - node _T_1949 = bits(_T_1948, 0, 0) @[dec_tlu_ctl.scala 2281:62] - node _T_1950 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2281:95] - node _T_1951 = eq(mhpme_vec[3], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2282:34] - node _T_1952 = bits(_T_1951, 0, 0) @[dec_tlu_ctl.scala 2282:62] - node _T_1953 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2282:97] - node _T_1954 = eq(mhpme_vec[3], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2283:34] - node _T_1955 = bits(_T_1954, 0, 0) @[dec_tlu_ctl.scala 2283:62] - node _T_1956 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2283:110] - node _T_1957 = eq(mhpme_vec[3], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2284:34] - node _T_1958 = bits(_T_1957, 0, 0) @[dec_tlu_ctl.scala 2284:62] - node _T_1959 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2285:34] - node _T_1960 = bits(_T_1959, 0, 0) @[dec_tlu_ctl.scala 2285:62] - node _T_1961 = eq(mhpme_vec[3], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2286:34] - node _T_1962 = bits(_T_1961, 0, 0) @[dec_tlu_ctl.scala 2286:62] - node _T_1963 = eq(mhpme_vec[3], UInt<6>("h020")) @[dec_tlu_ctl.scala 2287:34] - node _T_1964 = bits(_T_1963, 0, 0) @[dec_tlu_ctl.scala 2287:62] - node _T_1965 = eq(mhpme_vec[3], UInt<6>("h022")) @[dec_tlu_ctl.scala 2288:34] - node _T_1966 = bits(_T_1965, 0, 0) @[dec_tlu_ctl.scala 2288:62] - node _T_1967 = eq(mhpme_vec[3], UInt<6>("h023")) @[dec_tlu_ctl.scala 2289:34] - node _T_1968 = bits(_T_1967, 0, 0) @[dec_tlu_ctl.scala 2289:62] - node _T_1969 = eq(mhpme_vec[3], UInt<6>("h024")) @[dec_tlu_ctl.scala 2290:34] - node _T_1970 = bits(_T_1969, 0, 0) @[dec_tlu_ctl.scala 2290:62] - node _T_1971 = eq(mhpme_vec[3], UInt<6>("h025")) @[dec_tlu_ctl.scala 2291:34] - node _T_1972 = bits(_T_1971, 0, 0) @[dec_tlu_ctl.scala 2291:62] - node _T_1973 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2291:98] - node _T_1974 = or(_T_1973, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2291:120] - node _T_1975 = eq(mhpme_vec[3], UInt<6>("h026")) @[dec_tlu_ctl.scala 2292:34] - node _T_1976 = bits(_T_1975, 0, 0) @[dec_tlu_ctl.scala 2292:62] - node _T_1977 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2292:92] - node _T_1978 = or(_T_1977, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2292:117] - node _T_1979 = eq(mhpme_vec[3], UInt<6>("h027")) @[dec_tlu_ctl.scala 2293:34] - node _T_1980 = bits(_T_1979, 0, 0) @[dec_tlu_ctl.scala 2293:62] - node _T_1981 = eq(mhpme_vec[3], UInt<6>("h028")) @[dec_tlu_ctl.scala 2294:34] - node _T_1982 = bits(_T_1981, 0, 0) @[dec_tlu_ctl.scala 2294:62] - node _T_1983 = eq(mhpme_vec[3], UInt<6>("h029")) @[dec_tlu_ctl.scala 2295:34] - node _T_1984 = bits(_T_1983, 0, 0) @[dec_tlu_ctl.scala 2295:62] - node _T_1985 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2295:97] - node _T_1986 = and(_T_1985, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2295:129] - node _T_1987 = eq(mhpme_vec[3], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2296:34] - node _T_1988 = bits(_T_1987, 0, 0) @[dec_tlu_ctl.scala 2296:62] - node _T_1989 = eq(mhpme_vec[3], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2297:34] - node _T_1990 = bits(_T_1989, 0, 0) @[dec_tlu_ctl.scala 2297:62] - node _T_1991 = eq(mhpme_vec[3], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2298:34] - node _T_1992 = bits(_T_1991, 0, 0) @[dec_tlu_ctl.scala 2298:62] - node _T_1993 = eq(mhpme_vec[3], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2299:34] - node _T_1994 = bits(_T_1993, 0, 0) @[dec_tlu_ctl.scala 2299:62] - node _T_1995 = eq(mhpme_vec[3], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2300:34] - node _T_1996 = bits(_T_1995, 0, 0) @[dec_tlu_ctl.scala 2300:62] - node _T_1997 = eq(mhpme_vec[3], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2301:34] - node _T_1998 = bits(_T_1997, 0, 0) @[dec_tlu_ctl.scala 2301:62] - node _T_1999 = eq(mhpme_vec[3], UInt<6>("h030")) @[dec_tlu_ctl.scala 2302:34] - node _T_2000 = bits(_T_1999, 0, 0) @[dec_tlu_ctl.scala 2302:62] - node _T_2001 = eq(mhpme_vec[3], UInt<6>("h031")) @[dec_tlu_ctl.scala 2303:34] - node _T_2002 = bits(_T_2001, 0, 0) @[dec_tlu_ctl.scala 2303:62] - node _T_2003 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2303:84] - node _T_2004 = bits(_T_2003, 0, 0) @[dec_tlu_ctl.scala 2303:84] - node _T_2005 = not(_T_2004) @[dec_tlu_ctl.scala 2303:73] - node _T_2006 = eq(mhpme_vec[3], UInt<6>("h032")) @[dec_tlu_ctl.scala 2304:34] - node _T_2007 = bits(_T_2006, 0, 0) @[dec_tlu_ctl.scala 2304:62] - node _T_2008 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2304:84] - node _T_2009 = bits(_T_2008, 0, 0) @[dec_tlu_ctl.scala 2304:84] - node _T_2010 = not(_T_2009) @[dec_tlu_ctl.scala 2304:73] - node _T_2011 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2304:107] - node _T_2012 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2304:118] - node _T_2013 = and(_T_2011, _T_2012) @[dec_tlu_ctl.scala 2304:113] - node _T_2014 = orr(_T_2013) @[dec_tlu_ctl.scala 2304:125] - node _T_2015 = and(_T_2010, _T_2014) @[dec_tlu_ctl.scala 2304:98] - node _T_2016 = eq(mhpme_vec[3], UInt<6>("h036")) @[dec_tlu_ctl.scala 2305:34] - node _T_2017 = bits(_T_2016, 0, 0) @[dec_tlu_ctl.scala 2305:62] - node _T_2018 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2305:91] - node _T_2019 = eq(mhpme_vec[3], UInt<6>("h037")) @[dec_tlu_ctl.scala 2306:34] - node _T_2020 = bits(_T_2019, 0, 0) @[dec_tlu_ctl.scala 2306:62] - node _T_2021 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2306:94] - node _T_2022 = eq(mhpme_vec[3], UInt<6>("h038")) @[dec_tlu_ctl.scala 2307:34] - node _T_2023 = bits(_T_2022, 0, 0) @[dec_tlu_ctl.scala 2307:62] - node _T_2024 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2307:94] - node _T_2025 = eq(mhpme_vec[3], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2309:34] - node _T_2026 = bits(_T_2025, 0, 0) @[dec_tlu_ctl.scala 2309:62] - node _T_2027 = eq(mhpme_vec[3], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2310:34] - node _T_2028 = bits(_T_2027, 0, 0) @[dec_tlu_ctl.scala 2310:62] - node _T_2029 = eq(mhpme_vec[3], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2311:34] - node _T_2030 = bits(_T_2029, 0, 0) @[dec_tlu_ctl.scala 2311:62] - node _T_2031 = eq(mhpme_vec[3], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2312:34] - node _T_2032 = bits(_T_2031, 0, 0) @[dec_tlu_ctl.scala 2312:62] - node _T_2033 = eq(mhpme_vec[3], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2313:34] - node _T_2034 = bits(_T_2033, 0, 0) @[dec_tlu_ctl.scala 2313:62] - node _T_2035 = mux(_T_1869, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2036 = mux(_T_1871, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2037 = mux(_T_1873, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2038 = mux(_T_1875, _T_1877, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2039 = mux(_T_1879, _T_1883, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2040 = mux(_T_1885, _T_1888, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2041 = mux(_T_1890, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2042 = mux(_T_1892, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2043 = mux(_T_1894, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2044 = mux(_T_1896, _T_1897, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2045 = mux(_T_1899, _T_1900, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2046 = mux(_T_1902, _T_1903, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2047 = mux(_T_1905, _T_1906, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2048 = mux(_T_1908, _T_1910, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2049 = mux(_T_1912, _T_1915, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2050 = mux(_T_1917, _T_1918, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2051 = mux(_T_1920, _T_1921, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2052 = mux(_T_1923, _T_1924, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2053 = mux(_T_1926, _T_1927, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2054 = mux(_T_1929, _T_1930, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2055 = mux(_T_1932, _T_1933, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2056 = mux(_T_1935, _T_1936, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2057 = mux(_T_1938, _T_1939, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2058 = mux(_T_1941, _T_1942, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2059 = mux(_T_1944, _T_1947, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2060 = mux(_T_1949, _T_1950, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2061 = mux(_T_1952, _T_1953, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2062 = mux(_T_1955, _T_1956, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2063 = mux(_T_1958, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2064 = mux(_T_1960, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2065 = mux(_T_1962, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2066 = mux(_T_1964, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2067 = mux(_T_1966, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2068 = mux(_T_1968, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2069 = mux(_T_1970, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2070 = mux(_T_1972, _T_1974, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2071 = mux(_T_1976, _T_1978, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2072 = mux(_T_1980, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2073 = mux(_T_1982, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2074 = mux(_T_1984, _T_1986, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2075 = mux(_T_1988, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2076 = mux(_T_1990, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2077 = mux(_T_1992, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2078 = mux(_T_1994, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2079 = mux(_T_1996, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2080 = mux(_T_1998, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2081 = mux(_T_2000, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2082 = mux(_T_2002, _T_2005, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2083 = mux(_T_2007, _T_2015, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2084 = mux(_T_2017, _T_2018, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2085 = mux(_T_2020, _T_2021, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2086 = mux(_T_2023, _T_2024, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2087 = mux(_T_2026, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2088 = mux(_T_2028, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2089 = mux(_T_2030, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2090 = mux(_T_2032, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2091 = mux(_T_2034, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2092 = or(_T_2035, _T_2036) @[Mux.scala 27:72] - node _T_2093 = or(_T_2092, _T_2037) @[Mux.scala 27:72] - node _T_2094 = or(_T_2093, _T_2038) @[Mux.scala 27:72] - node _T_2095 = or(_T_2094, _T_2039) @[Mux.scala 27:72] - node _T_2096 = or(_T_2095, _T_2040) @[Mux.scala 27:72] - node _T_2097 = or(_T_2096, _T_2041) @[Mux.scala 27:72] - node _T_2098 = or(_T_2097, _T_2042) @[Mux.scala 27:72] - node _T_2099 = or(_T_2098, _T_2043) @[Mux.scala 27:72] - node _T_2100 = or(_T_2099, _T_2044) @[Mux.scala 27:72] - node _T_2101 = or(_T_2100, _T_2045) @[Mux.scala 27:72] - node _T_2102 = or(_T_2101, _T_2046) @[Mux.scala 27:72] + node _T_1864 = or(_T_1863, _T_1808) @[Mux.scala 27:72] + node _T_1865 = or(_T_1864, _T_1809) @[Mux.scala 27:72] + node _T_1866 = or(_T_1865, _T_1810) @[Mux.scala 27:72] + node _T_1867 = or(_T_1866, _T_1811) @[Mux.scala 27:72] + node _T_1868 = or(_T_1867, _T_1812) @[Mux.scala 27:72] + node _T_1869 = or(_T_1868, _T_1813) @[Mux.scala 27:72] + node _T_1870 = or(_T_1869, _T_1814) @[Mux.scala 27:72] + node _T_1871 = or(_T_1870, _T_1815) @[Mux.scala 27:72] + node _T_1872 = or(_T_1871, _T_1816) @[Mux.scala 27:72] + node _T_1873 = or(_T_1872, _T_1817) @[Mux.scala 27:72] + wire _T_1874 : UInt<1> @[Mux.scala 27:72] + _T_1874 <= _T_1873 @[Mux.scala 27:72] + node _T_1875 = and(_T_1593, _T_1874) @[dec_tlu_ctl.scala 2255:44] + mhpmc_inc_r[2] <= _T_1875 @[dec_tlu_ctl.scala 2255:19] + node _T_1876 = bits(mcountinhibit, 6, 6) @[dec_tlu_ctl.scala 2255:38] + node _T_1877 = not(_T_1876) @[dec_tlu_ctl.scala 2255:24] + node _T_1878 = eq(mhpme_vec[3], UInt<1>("h01")) @[dec_tlu_ctl.scala 2256:34] + node _T_1879 = bits(_T_1878, 0, 0) @[dec_tlu_ctl.scala 2256:62] + node _T_1880 = eq(mhpme_vec[3], UInt<2>("h02")) @[dec_tlu_ctl.scala 2257:34] + node _T_1881 = bits(_T_1880, 0, 0) @[dec_tlu_ctl.scala 2257:62] + node _T_1882 = eq(mhpme_vec[3], UInt<2>("h03")) @[dec_tlu_ctl.scala 2258:34] + node _T_1883 = bits(_T_1882, 0, 0) @[dec_tlu_ctl.scala 2258:62] + node _T_1884 = eq(mhpme_vec[3], UInt<3>("h04")) @[dec_tlu_ctl.scala 2259:34] + node _T_1885 = bits(_T_1884, 0, 0) @[dec_tlu_ctl.scala 2259:62] + node _T_1886 = not(io.illegal_r) @[dec_tlu_ctl.scala 2259:96] + node _T_1887 = and(io.tlu_i0_commit_cmt, _T_1886) @[dec_tlu_ctl.scala 2259:94] + node _T_1888 = eq(mhpme_vec[3], UInt<3>("h05")) @[dec_tlu_ctl.scala 2260:34] + node _T_1889 = bits(_T_1888, 0, 0) @[dec_tlu_ctl.scala 2260:62] + node _T_1890 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2260:96] + node _T_1891 = and(io.tlu_i0_commit_cmt, _T_1890) @[dec_tlu_ctl.scala 2260:94] + node _T_1892 = not(io.illegal_r) @[dec_tlu_ctl.scala 2260:117] + node _T_1893 = and(_T_1891, _T_1892) @[dec_tlu_ctl.scala 2260:115] + node _T_1894 = eq(mhpme_vec[3], UInt<3>("h06")) @[dec_tlu_ctl.scala 2261:34] + node _T_1895 = bits(_T_1894, 0, 0) @[dec_tlu_ctl.scala 2261:62] + node _T_1896 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2261:94] + node _T_1897 = not(io.illegal_r) @[dec_tlu_ctl.scala 2261:117] + node _T_1898 = and(_T_1896, _T_1897) @[dec_tlu_ctl.scala 2261:115] + node _T_1899 = eq(mhpme_vec[3], UInt<3>("h07")) @[dec_tlu_ctl.scala 2262:34] + node _T_1900 = bits(_T_1899, 0, 0) @[dec_tlu_ctl.scala 2262:62] + node _T_1901 = eq(mhpme_vec[3], UInt<4>("h08")) @[dec_tlu_ctl.scala 2263:34] + node _T_1902 = bits(_T_1901, 0, 0) @[dec_tlu_ctl.scala 2263:62] + node _T_1903 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2264:34] + node _T_1904 = bits(_T_1903, 0, 0) @[dec_tlu_ctl.scala 2264:62] + node _T_1905 = eq(mhpme_vec[3], UInt<4>("h09")) @[dec_tlu_ctl.scala 2265:34] + node _T_1906 = bits(_T_1905, 0, 0) @[dec_tlu_ctl.scala 2265:62] + node _T_1907 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2265:91] + node _T_1908 = eq(mhpme_vec[3], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2266:34] + node _T_1909 = bits(_T_1908, 0, 0) @[dec_tlu_ctl.scala 2266:62] + node _T_1910 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2266:105] + node _T_1911 = eq(mhpme_vec[3], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2267:34] + node _T_1912 = bits(_T_1911, 0, 0) @[dec_tlu_ctl.scala 2267:62] + node _T_1913 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2267:91] + node _T_1914 = eq(mhpme_vec[3], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2268:34] + node _T_1915 = bits(_T_1914, 0, 0) @[dec_tlu_ctl.scala 2268:62] + node _T_1916 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2268:91] + node _T_1917 = eq(mhpme_vec[3], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2269:34] + node _T_1918 = bits(_T_1917, 0, 0) @[dec_tlu_ctl.scala 2269:62] + node _T_1919 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2269:91] + node _T_1920 = and(_T_1919, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2269:100] + node _T_1921 = eq(mhpme_vec[3], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2270:34] + node _T_1922 = bits(_T_1921, 0, 0) @[dec_tlu_ctl.scala 2270:62] + node _T_1923 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2270:91] + node _T_1924 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2270:142] + node _T_1925 = and(_T_1923, _T_1924) @[dec_tlu_ctl.scala 2270:101] + node _T_1926 = eq(mhpme_vec[3], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2271:34] + node _T_1927 = bits(_T_1926, 0, 0) @[dec_tlu_ctl.scala 2271:59] + node _T_1928 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2271:89] + node _T_1929 = eq(mhpme_vec[3], UInt<5>("h010")) @[dec_tlu_ctl.scala 2272:34] + node _T_1930 = bits(_T_1929, 0, 0) @[dec_tlu_ctl.scala 2272:59] + node _T_1931 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2272:89] + node _T_1932 = eq(mhpme_vec[3], UInt<5>("h012")) @[dec_tlu_ctl.scala 2273:34] + node _T_1933 = bits(_T_1932, 0, 0) @[dec_tlu_ctl.scala 2273:59] + node _T_1934 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2273:89] + node _T_1935 = eq(mhpme_vec[3], UInt<5>("h011")) @[dec_tlu_ctl.scala 2274:34] + node _T_1936 = bits(_T_1935, 0, 0) @[dec_tlu_ctl.scala 2274:59] + node _T_1937 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2274:89] + node _T_1938 = eq(mhpme_vec[3], UInt<5>("h013")) @[dec_tlu_ctl.scala 2275:34] + node _T_1939 = bits(_T_1938, 0, 0) @[dec_tlu_ctl.scala 2275:59] + node _T_1940 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2275:89] + node _T_1941 = eq(mhpme_vec[3], UInt<5>("h014")) @[dec_tlu_ctl.scala 2276:34] + node _T_1942 = bits(_T_1941, 0, 0) @[dec_tlu_ctl.scala 2276:59] + node _T_1943 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2276:89] + node _T_1944 = eq(mhpme_vec[3], UInt<5>("h015")) @[dec_tlu_ctl.scala 2277:34] + node _T_1945 = bits(_T_1944, 0, 0) @[dec_tlu_ctl.scala 2277:59] + node _T_1946 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2277:89] + node _T_1947 = eq(mhpme_vec[3], UInt<5>("h016")) @[dec_tlu_ctl.scala 2278:34] + node _T_1948 = bits(_T_1947, 0, 0) @[dec_tlu_ctl.scala 2278:59] + node _T_1949 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2278:89] + node _T_1950 = eq(mhpme_vec[3], UInt<5>("h017")) @[dec_tlu_ctl.scala 2279:34] + node _T_1951 = bits(_T_1950, 0, 0) @[dec_tlu_ctl.scala 2279:59] + node _T_1952 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2279:89] + node _T_1953 = eq(mhpme_vec[3], UInt<5>("h018")) @[dec_tlu_ctl.scala 2280:34] + node _T_1954 = bits(_T_1953, 0, 0) @[dec_tlu_ctl.scala 2280:59] + node _T_1955 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2280:89] + node _T_1956 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2280:122] + node _T_1957 = or(_T_1955, _T_1956) @[dec_tlu_ctl.scala 2280:101] + node _T_1958 = eq(mhpme_vec[3], UInt<5>("h019")) @[dec_tlu_ctl.scala 2281:34] + node _T_1959 = bits(_T_1958, 0, 0) @[dec_tlu_ctl.scala 2281:62] + node _T_1960 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2281:95] + node _T_1961 = eq(mhpme_vec[3], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2282:34] + node _T_1962 = bits(_T_1961, 0, 0) @[dec_tlu_ctl.scala 2282:62] + node _T_1963 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2282:97] + node _T_1964 = eq(mhpme_vec[3], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2283:34] + node _T_1965 = bits(_T_1964, 0, 0) @[dec_tlu_ctl.scala 2283:62] + node _T_1966 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2283:110] + node _T_1967 = eq(mhpme_vec[3], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2284:34] + node _T_1968 = bits(_T_1967, 0, 0) @[dec_tlu_ctl.scala 2284:62] + node _T_1969 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2285:34] + node _T_1970 = bits(_T_1969, 0, 0) @[dec_tlu_ctl.scala 2285:62] + node _T_1971 = eq(mhpme_vec[3], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2286:34] + node _T_1972 = bits(_T_1971, 0, 0) @[dec_tlu_ctl.scala 2286:62] + node _T_1973 = eq(mhpme_vec[3], UInt<6>("h020")) @[dec_tlu_ctl.scala 2287:34] + node _T_1974 = bits(_T_1973, 0, 0) @[dec_tlu_ctl.scala 2287:62] + node _T_1975 = eq(mhpme_vec[3], UInt<6>("h022")) @[dec_tlu_ctl.scala 2288:34] + node _T_1976 = bits(_T_1975, 0, 0) @[dec_tlu_ctl.scala 2288:62] + node _T_1977 = eq(mhpme_vec[3], UInt<6>("h023")) @[dec_tlu_ctl.scala 2289:34] + node _T_1978 = bits(_T_1977, 0, 0) @[dec_tlu_ctl.scala 2289:62] + node _T_1979 = eq(mhpme_vec[3], UInt<6>("h024")) @[dec_tlu_ctl.scala 2290:34] + node _T_1980 = bits(_T_1979, 0, 0) @[dec_tlu_ctl.scala 2290:62] + node _T_1981 = eq(mhpme_vec[3], UInt<6>("h025")) @[dec_tlu_ctl.scala 2291:34] + node _T_1982 = bits(_T_1981, 0, 0) @[dec_tlu_ctl.scala 2291:62] + node _T_1983 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2291:98] + node _T_1984 = or(_T_1983, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2291:120] + node _T_1985 = eq(mhpme_vec[3], UInt<6>("h026")) @[dec_tlu_ctl.scala 2292:34] + node _T_1986 = bits(_T_1985, 0, 0) @[dec_tlu_ctl.scala 2292:62] + node _T_1987 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2292:92] + node _T_1988 = or(_T_1987, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2292:117] + node _T_1989 = eq(mhpme_vec[3], UInt<6>("h027")) @[dec_tlu_ctl.scala 2293:34] + node _T_1990 = bits(_T_1989, 0, 0) @[dec_tlu_ctl.scala 2293:62] + node _T_1991 = eq(mhpme_vec[3], UInt<6>("h028")) @[dec_tlu_ctl.scala 2294:34] + node _T_1992 = bits(_T_1991, 0, 0) @[dec_tlu_ctl.scala 2294:62] + node _T_1993 = eq(mhpme_vec[3], UInt<6>("h029")) @[dec_tlu_ctl.scala 2295:34] + node _T_1994 = bits(_T_1993, 0, 0) @[dec_tlu_ctl.scala 2295:62] + node _T_1995 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2295:97] + node _T_1996 = and(_T_1995, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2295:129] + node _T_1997 = eq(mhpme_vec[3], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2296:34] + node _T_1998 = bits(_T_1997, 0, 0) @[dec_tlu_ctl.scala 2296:62] + node _T_1999 = eq(mhpme_vec[3], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2297:34] + node _T_2000 = bits(_T_1999, 0, 0) @[dec_tlu_ctl.scala 2297:62] + node _T_2001 = eq(mhpme_vec[3], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2298:34] + node _T_2002 = bits(_T_2001, 0, 0) @[dec_tlu_ctl.scala 2298:62] + node _T_2003 = eq(mhpme_vec[3], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2299:34] + node _T_2004 = bits(_T_2003, 0, 0) @[dec_tlu_ctl.scala 2299:62] + node _T_2005 = eq(mhpme_vec[3], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2300:34] + node _T_2006 = bits(_T_2005, 0, 0) @[dec_tlu_ctl.scala 2300:62] + node _T_2007 = eq(mhpme_vec[3], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2301:34] + node _T_2008 = bits(_T_2007, 0, 0) @[dec_tlu_ctl.scala 2301:62] + node _T_2009 = eq(mhpme_vec[3], UInt<6>("h030")) @[dec_tlu_ctl.scala 2302:34] + node _T_2010 = bits(_T_2009, 0, 0) @[dec_tlu_ctl.scala 2302:62] + node _T_2011 = eq(mhpme_vec[3], UInt<6>("h031")) @[dec_tlu_ctl.scala 2303:34] + node _T_2012 = bits(_T_2011, 0, 0) @[dec_tlu_ctl.scala 2303:62] + node _T_2013 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2303:84] + node _T_2014 = bits(_T_2013, 0, 0) @[dec_tlu_ctl.scala 2303:84] + node _T_2015 = not(_T_2014) @[dec_tlu_ctl.scala 2303:73] + node _T_2016 = eq(mhpme_vec[3], UInt<6>("h032")) @[dec_tlu_ctl.scala 2304:34] + node _T_2017 = bits(_T_2016, 0, 0) @[dec_tlu_ctl.scala 2304:62] + node _T_2018 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2304:84] + node _T_2019 = bits(_T_2018, 0, 0) @[dec_tlu_ctl.scala 2304:84] + node _T_2020 = not(_T_2019) @[dec_tlu_ctl.scala 2304:73] + node _T_2021 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2304:107] + node _T_2022 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2304:118] + node _T_2023 = and(_T_2021, _T_2022) @[dec_tlu_ctl.scala 2304:113] + node _T_2024 = orr(_T_2023) @[dec_tlu_ctl.scala 2304:125] + node _T_2025 = and(_T_2020, _T_2024) @[dec_tlu_ctl.scala 2304:98] + node _T_2026 = eq(mhpme_vec[3], UInt<6>("h036")) @[dec_tlu_ctl.scala 2305:34] + node _T_2027 = bits(_T_2026, 0, 0) @[dec_tlu_ctl.scala 2305:62] + node _T_2028 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2305:91] + node _T_2029 = eq(mhpme_vec[3], UInt<6>("h037")) @[dec_tlu_ctl.scala 2306:34] + node _T_2030 = bits(_T_2029, 0, 0) @[dec_tlu_ctl.scala 2306:62] + node _T_2031 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2306:94] + node _T_2032 = eq(mhpme_vec[3], UInt<6>("h038")) @[dec_tlu_ctl.scala 2307:34] + node _T_2033 = bits(_T_2032, 0, 0) @[dec_tlu_ctl.scala 2307:62] + node _T_2034 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2307:94] + node _T_2035 = eq(mhpme_vec[3], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2309:34] + node _T_2036 = bits(_T_2035, 0, 0) @[dec_tlu_ctl.scala 2309:62] + node _T_2037 = eq(mhpme_vec[3], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2310:34] + node _T_2038 = bits(_T_2037, 0, 0) @[dec_tlu_ctl.scala 2310:62] + node _T_2039 = eq(mhpme_vec[3], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2311:34] + node _T_2040 = bits(_T_2039, 0, 0) @[dec_tlu_ctl.scala 2311:62] + node _T_2041 = eq(mhpme_vec[3], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2312:34] + node _T_2042 = bits(_T_2041, 0, 0) @[dec_tlu_ctl.scala 2312:62] + node _T_2043 = eq(mhpme_vec[3], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2313:34] + node _T_2044 = bits(_T_2043, 0, 0) @[dec_tlu_ctl.scala 2313:62] + node _T_2045 = mux(_T_1879, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2046 = mux(_T_1881, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2047 = mux(_T_1883, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2048 = mux(_T_1885, _T_1887, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2049 = mux(_T_1889, _T_1893, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2050 = mux(_T_1895, _T_1898, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2051 = mux(_T_1900, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2052 = mux(_T_1902, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2053 = mux(_T_1904, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2054 = mux(_T_1906, _T_1907, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2055 = mux(_T_1909, _T_1910, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2056 = mux(_T_1912, _T_1913, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2057 = mux(_T_1915, _T_1916, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2058 = mux(_T_1918, _T_1920, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2059 = mux(_T_1922, _T_1925, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2060 = mux(_T_1927, _T_1928, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2061 = mux(_T_1930, _T_1931, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2062 = mux(_T_1933, _T_1934, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2063 = mux(_T_1936, _T_1937, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2064 = mux(_T_1939, _T_1940, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2065 = mux(_T_1942, _T_1943, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2066 = mux(_T_1945, _T_1946, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2067 = mux(_T_1948, _T_1949, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2068 = mux(_T_1951, _T_1952, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2069 = mux(_T_1954, _T_1957, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2070 = mux(_T_1959, _T_1960, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2071 = mux(_T_1962, _T_1963, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2072 = mux(_T_1965, _T_1966, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2073 = mux(_T_1968, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2074 = mux(_T_1970, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2075 = mux(_T_1972, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2076 = mux(_T_1974, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2077 = mux(_T_1976, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2078 = mux(_T_1978, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2079 = mux(_T_1980, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2080 = mux(_T_1982, _T_1984, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2081 = mux(_T_1986, _T_1988, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2082 = mux(_T_1990, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2083 = mux(_T_1992, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2084 = mux(_T_1994, _T_1996, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2085 = mux(_T_1998, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2086 = mux(_T_2000, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2087 = mux(_T_2002, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2088 = mux(_T_2004, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2089 = mux(_T_2006, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2090 = mux(_T_2008, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2091 = mux(_T_2010, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2092 = mux(_T_2012, _T_2015, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2093 = mux(_T_2017, _T_2025, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2094 = mux(_T_2027, _T_2028, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2095 = mux(_T_2030, _T_2031, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2096 = mux(_T_2033, _T_2034, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2097 = mux(_T_2036, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2098 = mux(_T_2038, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2099 = mux(_T_2040, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2100 = mux(_T_2042, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2101 = mux(_T_2044, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2102 = or(_T_2045, _T_2046) @[Mux.scala 27:72] node _T_2103 = or(_T_2102, _T_2047) @[Mux.scala 27:72] node _T_2104 = or(_T_2103, _T_2048) @[Mux.scala 27:72] node _T_2105 = or(_T_2104, _T_2049) @[Mux.scala 27:72] @@ -75543,585 +75543,585 @@ circuit quasar_wrapper : node _T_2145 = or(_T_2144, _T_2089) @[Mux.scala 27:72] node _T_2146 = or(_T_2145, _T_2090) @[Mux.scala 27:72] node _T_2147 = or(_T_2146, _T_2091) @[Mux.scala 27:72] - wire _T_2148 : UInt<1> @[Mux.scala 27:72] - _T_2148 <= _T_2147 @[Mux.scala 27:72] - node _T_2149 = and(_T_1867, _T_2148) @[dec_tlu_ctl.scala 2255:44] - mhpmc_inc_r[3] <= _T_2149 @[dec_tlu_ctl.scala 2255:19] - reg _T_2150 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2316:53] - _T_2150 <= mhpmc_inc_r[0] @[dec_tlu_ctl.scala 2316:53] - mhpmc_inc_r_d1[0] <= _T_2150 @[dec_tlu_ctl.scala 2316:20] - reg _T_2151 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2317:53] - _T_2151 <= mhpmc_inc_r[1] @[dec_tlu_ctl.scala 2317:53] - mhpmc_inc_r_d1[1] <= _T_2151 @[dec_tlu_ctl.scala 2317:20] - reg _T_2152 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2318:53] - _T_2152 <= mhpmc_inc_r[2] @[dec_tlu_ctl.scala 2318:53] - mhpmc_inc_r_d1[2] <= _T_2152 @[dec_tlu_ctl.scala 2318:20] - reg _T_2153 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2319:53] - _T_2153 <= mhpmc_inc_r[3] @[dec_tlu_ctl.scala 2319:53] - mhpmc_inc_r_d1[3] <= _T_2153 @[dec_tlu_ctl.scala 2319:20] + node _T_2148 = or(_T_2147, _T_2092) @[Mux.scala 27:72] + node _T_2149 = or(_T_2148, _T_2093) @[Mux.scala 27:72] + node _T_2150 = or(_T_2149, _T_2094) @[Mux.scala 27:72] + node _T_2151 = or(_T_2150, _T_2095) @[Mux.scala 27:72] + node _T_2152 = or(_T_2151, _T_2096) @[Mux.scala 27:72] + node _T_2153 = or(_T_2152, _T_2097) @[Mux.scala 27:72] + node _T_2154 = or(_T_2153, _T_2098) @[Mux.scala 27:72] + node _T_2155 = or(_T_2154, _T_2099) @[Mux.scala 27:72] + node _T_2156 = or(_T_2155, _T_2100) @[Mux.scala 27:72] + node _T_2157 = or(_T_2156, _T_2101) @[Mux.scala 27:72] + wire _T_2158 : UInt<1> @[Mux.scala 27:72] + _T_2158 <= _T_2157 @[Mux.scala 27:72] + node _T_2159 = and(_T_1877, _T_2158) @[dec_tlu_ctl.scala 2255:44] + mhpmc_inc_r[3] <= _T_2159 @[dec_tlu_ctl.scala 2255:19] + reg _T_2160 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2316:53] + _T_2160 <= mhpmc_inc_r[0] @[dec_tlu_ctl.scala 2316:53] + mhpmc_inc_r_d1[0] <= _T_2160 @[dec_tlu_ctl.scala 2316:20] + reg _T_2161 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2317:53] + _T_2161 <= mhpmc_inc_r[1] @[dec_tlu_ctl.scala 2317:53] + mhpmc_inc_r_d1[1] <= _T_2161 @[dec_tlu_ctl.scala 2317:20] + reg _T_2162 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2318:53] + _T_2162 <= mhpmc_inc_r[2] @[dec_tlu_ctl.scala 2318:53] + mhpmc_inc_r_d1[2] <= _T_2162 @[dec_tlu_ctl.scala 2318:20] + reg _T_2163 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2319:53] + _T_2163 <= mhpmc_inc_r[3] @[dec_tlu_ctl.scala 2319:53] + mhpmc_inc_r_d1[3] <= _T_2163 @[dec_tlu_ctl.scala 2319:20] reg perfcnt_halted_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2320:56] perfcnt_halted_d1 <= perfcnt_halted @[dec_tlu_ctl.scala 2320:56] - node _T_2154 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2323:53] - node _T_2155 = and(io.dec_tlu_dbg_halted, _T_2154) @[dec_tlu_ctl.scala 2323:44] - node _T_2156 = or(_T_2155, io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2323:67] - perfcnt_halted <= _T_2156 @[dec_tlu_ctl.scala 2323:17] - node _T_2157 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2324:70] - node _T_2158 = and(io.dec_tlu_dbg_halted, _T_2157) @[dec_tlu_ctl.scala 2324:61] - node _T_2159 = not(_T_2158) @[dec_tlu_ctl.scala 2324:37] - node _T_2160 = bits(_T_2159, 0, 0) @[Bitwise.scala 72:15] - node _T_2161 = mux(_T_2160, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_2162 = bits(mhpme_vec[3], 9, 9) @[dec_tlu_ctl.scala 2324:104] - node _T_2163 = bits(mhpme_vec[2], 9, 9) @[dec_tlu_ctl.scala 2324:120] - node _T_2164 = bits(mhpme_vec[1], 9, 9) @[dec_tlu_ctl.scala 2324:136] - node _T_2165 = bits(mhpme_vec[0], 9, 9) @[dec_tlu_ctl.scala 2324:152] - node _T_2166 = cat(_T_2164, _T_2165) @[Cat.scala 29:58] - node _T_2167 = cat(_T_2162, _T_2163) @[Cat.scala 29:58] - node _T_2168 = cat(_T_2167, _T_2166) @[Cat.scala 29:58] - node perfcnt_during_sleep = and(_T_2161, _T_2168) @[dec_tlu_ctl.scala 2324:86] - node _T_2169 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2326:88] - node _T_2170 = not(_T_2169) @[dec_tlu_ctl.scala 2326:67] - node _T_2171 = and(perfcnt_halted_d1, _T_2170) @[dec_tlu_ctl.scala 2326:65] - node _T_2172 = not(_T_2171) @[dec_tlu_ctl.scala 2326:45] - node _T_2173 = and(mhpmc_inc_r_d1[0], _T_2172) @[dec_tlu_ctl.scala 2326:43] - io.dec_tlu_perfcnt0 <= _T_2173 @[dec_tlu_ctl.scala 2326:22] - node _T_2174 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2327:88] - node _T_2175 = not(_T_2174) @[dec_tlu_ctl.scala 2327:67] - node _T_2176 = and(perfcnt_halted_d1, _T_2175) @[dec_tlu_ctl.scala 2327:65] - node _T_2177 = not(_T_2176) @[dec_tlu_ctl.scala 2327:45] - node _T_2178 = and(mhpmc_inc_r_d1[1], _T_2177) @[dec_tlu_ctl.scala 2327:43] - io.dec_tlu_perfcnt1 <= _T_2178 @[dec_tlu_ctl.scala 2327:22] - node _T_2179 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2328:88] - node _T_2180 = not(_T_2179) @[dec_tlu_ctl.scala 2328:67] - node _T_2181 = and(perfcnt_halted_d1, _T_2180) @[dec_tlu_ctl.scala 2328:65] - node _T_2182 = not(_T_2181) @[dec_tlu_ctl.scala 2328:45] - node _T_2183 = and(mhpmc_inc_r_d1[2], _T_2182) @[dec_tlu_ctl.scala 2328:43] - io.dec_tlu_perfcnt2 <= _T_2183 @[dec_tlu_ctl.scala 2328:22] - node _T_2184 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2329:88] - node _T_2185 = not(_T_2184) @[dec_tlu_ctl.scala 2329:67] - node _T_2186 = and(perfcnt_halted_d1, _T_2185) @[dec_tlu_ctl.scala 2329:65] - node _T_2187 = not(_T_2186) @[dec_tlu_ctl.scala 2329:45] - node _T_2188 = and(mhpmc_inc_r_d1[3], _T_2187) @[dec_tlu_ctl.scala 2329:43] - io.dec_tlu_perfcnt3 <= _T_2188 @[dec_tlu_ctl.scala 2329:22] - node _T_2189 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2335:65] - node _T_2190 = eq(_T_2189, UInt<12>("h0b03")) @[dec_tlu_ctl.scala 2335:72] - node mhpmc3_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2190) @[dec_tlu_ctl.scala 2335:43] - node _T_2191 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2336:23] - node _T_2192 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2336:61] - node _T_2193 = or(_T_2191, _T_2192) @[dec_tlu_ctl.scala 2336:39] - node _T_2194 = orr(mhpmc_inc_r[0]) @[dec_tlu_ctl.scala 2336:86] - node mhpmc3_wr_en1 = and(_T_2193, _T_2194) @[dec_tlu_ctl.scala 2336:66] + node _T_2164 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2323:53] + node _T_2165 = and(io.dec_tlu_dbg_halted, _T_2164) @[dec_tlu_ctl.scala 2323:44] + node _T_2166 = or(_T_2165, io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2323:67] + perfcnt_halted <= _T_2166 @[dec_tlu_ctl.scala 2323:17] + node _T_2167 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2324:70] + node _T_2168 = and(io.dec_tlu_dbg_halted, _T_2167) @[dec_tlu_ctl.scala 2324:61] + node _T_2169 = not(_T_2168) @[dec_tlu_ctl.scala 2324:37] + node _T_2170 = bits(_T_2169, 0, 0) @[Bitwise.scala 72:15] + node _T_2171 = mux(_T_2170, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_2172 = bits(mhpme_vec[3], 9, 9) @[dec_tlu_ctl.scala 2324:104] + node _T_2173 = bits(mhpme_vec[2], 9, 9) @[dec_tlu_ctl.scala 2324:120] + node _T_2174 = bits(mhpme_vec[1], 9, 9) @[dec_tlu_ctl.scala 2324:136] + node _T_2175 = bits(mhpme_vec[0], 9, 9) @[dec_tlu_ctl.scala 2324:152] + node _T_2176 = cat(_T_2174, _T_2175) @[Cat.scala 29:58] + node _T_2177 = cat(_T_2172, _T_2173) @[Cat.scala 29:58] + node _T_2178 = cat(_T_2177, _T_2176) @[Cat.scala 29:58] + node perfcnt_during_sleep = and(_T_2171, _T_2178) @[dec_tlu_ctl.scala 2324:86] + node _T_2179 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2326:88] + node _T_2180 = not(_T_2179) @[dec_tlu_ctl.scala 2326:67] + node _T_2181 = and(perfcnt_halted_d1, _T_2180) @[dec_tlu_ctl.scala 2326:65] + node _T_2182 = not(_T_2181) @[dec_tlu_ctl.scala 2326:45] + node _T_2183 = and(mhpmc_inc_r_d1[0], _T_2182) @[dec_tlu_ctl.scala 2326:43] + io.dec_tlu_perfcnt0 <= _T_2183 @[dec_tlu_ctl.scala 2326:22] + node _T_2184 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2327:88] + node _T_2185 = not(_T_2184) @[dec_tlu_ctl.scala 2327:67] + node _T_2186 = and(perfcnt_halted_d1, _T_2185) @[dec_tlu_ctl.scala 2327:65] + node _T_2187 = not(_T_2186) @[dec_tlu_ctl.scala 2327:45] + node _T_2188 = and(mhpmc_inc_r_d1[1], _T_2187) @[dec_tlu_ctl.scala 2327:43] + io.dec_tlu_perfcnt1 <= _T_2188 @[dec_tlu_ctl.scala 2327:22] + node _T_2189 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2328:88] + node _T_2190 = not(_T_2189) @[dec_tlu_ctl.scala 2328:67] + node _T_2191 = and(perfcnt_halted_d1, _T_2190) @[dec_tlu_ctl.scala 2328:65] + node _T_2192 = not(_T_2191) @[dec_tlu_ctl.scala 2328:45] + node _T_2193 = and(mhpmc_inc_r_d1[2], _T_2192) @[dec_tlu_ctl.scala 2328:43] + io.dec_tlu_perfcnt2 <= _T_2193 @[dec_tlu_ctl.scala 2328:22] + node _T_2194 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2329:88] + node _T_2195 = not(_T_2194) @[dec_tlu_ctl.scala 2329:67] + node _T_2196 = and(perfcnt_halted_d1, _T_2195) @[dec_tlu_ctl.scala 2329:65] + node _T_2197 = not(_T_2196) @[dec_tlu_ctl.scala 2329:45] + node _T_2198 = and(mhpmc_inc_r_d1[3], _T_2197) @[dec_tlu_ctl.scala 2329:43] + io.dec_tlu_perfcnt3 <= _T_2198 @[dec_tlu_ctl.scala 2329:22] + node _T_2199 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2335:65] + node _T_2200 = eq(_T_2199, UInt<12>("h0b03")) @[dec_tlu_ctl.scala 2335:72] + node mhpmc3_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2200) @[dec_tlu_ctl.scala 2335:43] + node _T_2201 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2336:23] + node _T_2202 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2336:61] + node _T_2203 = or(_T_2201, _T_2202) @[dec_tlu_ctl.scala 2336:39] + node _T_2204 = orr(mhpmc_inc_r[0]) @[dec_tlu_ctl.scala 2336:86] + node mhpmc3_wr_en1 = and(_T_2203, _T_2204) @[dec_tlu_ctl.scala 2336:66] node mhpmc3_wr_en = or(mhpmc3_wr_en0, mhpmc3_wr_en1) @[dec_tlu_ctl.scala 2337:36] - node _T_2195 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2340:28] - node _T_2196 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2340:41] - node _T_2197 = cat(_T_2195, _T_2196) @[Cat.scala 29:58] - node _T_2198 = cat(UInt<63>("h00"), mhpmc_inc_r[0]) @[Cat.scala 29:58] - node _T_2199 = add(_T_2197, _T_2198) @[dec_tlu_ctl.scala 2340:49] - node _T_2200 = tail(_T_2199, 1) @[dec_tlu_ctl.scala 2340:49] - mhpmc3_incr <= _T_2200 @[dec_tlu_ctl.scala 2340:14] - node _T_2201 = bits(mhpmc3_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2341:36] - node _T_2202 = bits(mhpmc3_incr, 31, 0) @[dec_tlu_ctl.scala 2341:76] - node mhpmc3_ns = mux(_T_2201, io.dec_csr_wrdata_r, _T_2202) @[dec_tlu_ctl.scala 2341:21] - node _T_2203 = bits(mhpmc3_wr_en, 0, 0) @[dec_tlu_ctl.scala 2343:42] + node _T_2205 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2340:28] + node _T_2206 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2340:41] + node _T_2207 = cat(_T_2205, _T_2206) @[Cat.scala 29:58] + node _T_2208 = cat(UInt<63>("h00"), mhpmc_inc_r[0]) @[Cat.scala 29:58] + node _T_2209 = add(_T_2207, _T_2208) @[dec_tlu_ctl.scala 2340:49] + node _T_2210 = tail(_T_2209, 1) @[dec_tlu_ctl.scala 2340:49] + mhpmc3_incr <= _T_2210 @[dec_tlu_ctl.scala 2340:14] + node _T_2211 = bits(mhpmc3_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2341:36] + node _T_2212 = bits(mhpmc3_incr, 31, 0) @[dec_tlu_ctl.scala 2341:76] + node mhpmc3_ns = mux(_T_2211, io.dec_csr_wrdata_r, _T_2212) @[dec_tlu_ctl.scala 2341:21] + node _T_2213 = bits(mhpmc3_wr_en, 0, 0) @[dec_tlu_ctl.scala 2343:42] inst rvclkhdr_26 of rvclkhdr_746 @[lib.scala 368:23] rvclkhdr_26.clock <= clock rvclkhdr_26.reset <= reset rvclkhdr_26.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_26.io.en <= _T_2203 @[lib.scala 371:17] + rvclkhdr_26.io.en <= _T_2213 @[lib.scala 371:17] rvclkhdr_26.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2204 : UInt, rvclkhdr_26.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2204 <= mhpmc3_ns @[lib.scala 374:16] - mhpmc3 <= _T_2204 @[dec_tlu_ctl.scala 2343:9] - node _T_2205 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2345:66] - node _T_2206 = eq(_T_2205, UInt<12>("h0b83")) @[dec_tlu_ctl.scala 2345:73] - node mhpmc3h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2206) @[dec_tlu_ctl.scala 2345:44] + reg _T_2214 : UInt, rvclkhdr_26.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2214 <= mhpmc3_ns @[lib.scala 374:16] + mhpmc3 <= _T_2214 @[dec_tlu_ctl.scala 2343:9] + node _T_2215 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2345:66] + node _T_2216 = eq(_T_2215, UInt<12>("h0b83")) @[dec_tlu_ctl.scala 2345:73] + node mhpmc3h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2216) @[dec_tlu_ctl.scala 2345:44] node mhpmc3h_wr_en = or(mhpmc3h_wr_en0, mhpmc3_wr_en1) @[dec_tlu_ctl.scala 2346:38] - node _T_2207 = bits(mhpmc3h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2347:38] - node _T_2208 = bits(mhpmc3_incr, 63, 32) @[dec_tlu_ctl.scala 2347:78] - node mhpmc3h_ns = mux(_T_2207, io.dec_csr_wrdata_r, _T_2208) @[dec_tlu_ctl.scala 2347:22] - node _T_2209 = bits(mhpmc3h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2349:46] + node _T_2217 = bits(mhpmc3h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2347:38] + node _T_2218 = bits(mhpmc3_incr, 63, 32) @[dec_tlu_ctl.scala 2347:78] + node mhpmc3h_ns = mux(_T_2217, io.dec_csr_wrdata_r, _T_2218) @[dec_tlu_ctl.scala 2347:22] + node _T_2219 = bits(mhpmc3h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2349:46] inst rvclkhdr_27 of rvclkhdr_747 @[lib.scala 368:23] rvclkhdr_27.clock <= clock rvclkhdr_27.reset <= reset rvclkhdr_27.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_27.io.en <= _T_2209 @[lib.scala 371:17] + rvclkhdr_27.io.en <= _T_2219 @[lib.scala 371:17] rvclkhdr_27.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2210 : UInt, rvclkhdr_27.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2210 <= mhpmc3h_ns @[lib.scala 374:16] - mhpmc3h <= _T_2210 @[dec_tlu_ctl.scala 2349:10] - node _T_2211 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2354:65] - node _T_2212 = eq(_T_2211, UInt<12>("h0b04")) @[dec_tlu_ctl.scala 2354:72] - node mhpmc4_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2212) @[dec_tlu_ctl.scala 2354:43] - node _T_2213 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2355:23] - node _T_2214 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2355:61] - node _T_2215 = or(_T_2213, _T_2214) @[dec_tlu_ctl.scala 2355:39] - node _T_2216 = orr(mhpmc_inc_r[1]) @[dec_tlu_ctl.scala 2355:86] - node mhpmc4_wr_en1 = and(_T_2215, _T_2216) @[dec_tlu_ctl.scala 2355:66] + reg _T_2220 : UInt, rvclkhdr_27.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2220 <= mhpmc3h_ns @[lib.scala 374:16] + mhpmc3h <= _T_2220 @[dec_tlu_ctl.scala 2349:10] + node _T_2221 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2354:65] + node _T_2222 = eq(_T_2221, UInt<12>("h0b04")) @[dec_tlu_ctl.scala 2354:72] + node mhpmc4_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2222) @[dec_tlu_ctl.scala 2354:43] + node _T_2223 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2355:23] + node _T_2224 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2355:61] + node _T_2225 = or(_T_2223, _T_2224) @[dec_tlu_ctl.scala 2355:39] + node _T_2226 = orr(mhpmc_inc_r[1]) @[dec_tlu_ctl.scala 2355:86] + node mhpmc4_wr_en1 = and(_T_2225, _T_2226) @[dec_tlu_ctl.scala 2355:66] node mhpmc4_wr_en = or(mhpmc4_wr_en0, mhpmc4_wr_en1) @[dec_tlu_ctl.scala 2356:36] - node _T_2217 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2360:28] - node _T_2218 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2360:41] - node _T_2219 = cat(_T_2217, _T_2218) @[Cat.scala 29:58] - node _T_2220 = cat(UInt<63>("h00"), mhpmc_inc_r[1]) @[Cat.scala 29:58] - node _T_2221 = add(_T_2219, _T_2220) @[dec_tlu_ctl.scala 2360:49] - node _T_2222 = tail(_T_2221, 1) @[dec_tlu_ctl.scala 2360:49] - mhpmc4_incr <= _T_2222 @[dec_tlu_ctl.scala 2360:14] - node _T_2223 = bits(mhpmc4_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2361:36] - node _T_2224 = bits(io.dec_csr_wrdata_r, 31, 0) @[dec_tlu_ctl.scala 2361:63] - node _T_2225 = bits(mhpmc4_incr, 31, 0) @[dec_tlu_ctl.scala 2361:82] - node mhpmc4_ns = mux(_T_2223, _T_2224, _T_2225) @[dec_tlu_ctl.scala 2361:21] - node _T_2226 = bits(mhpmc4_wr_en, 0, 0) @[dec_tlu_ctl.scala 2362:43] + node _T_2227 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2360:28] + node _T_2228 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2360:41] + node _T_2229 = cat(_T_2227, _T_2228) @[Cat.scala 29:58] + node _T_2230 = cat(UInt<63>("h00"), mhpmc_inc_r[1]) @[Cat.scala 29:58] + node _T_2231 = add(_T_2229, _T_2230) @[dec_tlu_ctl.scala 2360:49] + node _T_2232 = tail(_T_2231, 1) @[dec_tlu_ctl.scala 2360:49] + mhpmc4_incr <= _T_2232 @[dec_tlu_ctl.scala 2360:14] + node _T_2233 = bits(mhpmc4_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2361:36] + node _T_2234 = bits(io.dec_csr_wrdata_r, 31, 0) @[dec_tlu_ctl.scala 2361:63] + node _T_2235 = bits(mhpmc4_incr, 31, 0) @[dec_tlu_ctl.scala 2361:82] + node mhpmc4_ns = mux(_T_2233, _T_2234, _T_2235) @[dec_tlu_ctl.scala 2361:21] + node _T_2236 = bits(mhpmc4_wr_en, 0, 0) @[dec_tlu_ctl.scala 2362:43] inst rvclkhdr_28 of rvclkhdr_748 @[lib.scala 368:23] rvclkhdr_28.clock <= clock rvclkhdr_28.reset <= reset rvclkhdr_28.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_28.io.en <= _T_2226 @[lib.scala 371:17] + rvclkhdr_28.io.en <= _T_2236 @[lib.scala 371:17] rvclkhdr_28.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2227 : UInt, rvclkhdr_28.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2227 <= mhpmc4_ns @[lib.scala 374:16] - mhpmc4 <= _T_2227 @[dec_tlu_ctl.scala 2362:9] - node _T_2228 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2364:66] - node _T_2229 = eq(_T_2228, UInt<12>("h0b84")) @[dec_tlu_ctl.scala 2364:73] - node mhpmc4h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2229) @[dec_tlu_ctl.scala 2364:44] + reg _T_2237 : UInt, rvclkhdr_28.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2237 <= mhpmc4_ns @[lib.scala 374:16] + mhpmc4 <= _T_2237 @[dec_tlu_ctl.scala 2362:9] + node _T_2238 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2364:66] + node _T_2239 = eq(_T_2238, UInt<12>("h0b84")) @[dec_tlu_ctl.scala 2364:73] + node mhpmc4h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2239) @[dec_tlu_ctl.scala 2364:44] node mhpmc4h_wr_en = or(mhpmc4h_wr_en0, mhpmc4_wr_en1) @[dec_tlu_ctl.scala 2365:38] - node _T_2230 = bits(mhpmc4h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2366:38] - node _T_2231 = bits(mhpmc4_incr, 63, 32) @[dec_tlu_ctl.scala 2366:78] - node mhpmc4h_ns = mux(_T_2230, io.dec_csr_wrdata_r, _T_2231) @[dec_tlu_ctl.scala 2366:22] - node _T_2232 = bits(mhpmc4h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2367:46] + node _T_2240 = bits(mhpmc4h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2366:38] + node _T_2241 = bits(mhpmc4_incr, 63, 32) @[dec_tlu_ctl.scala 2366:78] + node mhpmc4h_ns = mux(_T_2240, io.dec_csr_wrdata_r, _T_2241) @[dec_tlu_ctl.scala 2366:22] + node _T_2242 = bits(mhpmc4h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2367:46] inst rvclkhdr_29 of rvclkhdr_749 @[lib.scala 368:23] rvclkhdr_29.clock <= clock rvclkhdr_29.reset <= reset rvclkhdr_29.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_29.io.en <= _T_2232 @[lib.scala 371:17] + rvclkhdr_29.io.en <= _T_2242 @[lib.scala 371:17] rvclkhdr_29.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2233 : UInt, rvclkhdr_29.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2233 <= mhpmc4h_ns @[lib.scala 374:16] - mhpmc4h <= _T_2233 @[dec_tlu_ctl.scala 2367:10] - node _T_2234 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2373:65] - node _T_2235 = eq(_T_2234, UInt<12>("h0b05")) @[dec_tlu_ctl.scala 2373:72] - node mhpmc5_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2235) @[dec_tlu_ctl.scala 2373:43] - node _T_2236 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2374:23] - node _T_2237 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2374:61] - node _T_2238 = or(_T_2236, _T_2237) @[dec_tlu_ctl.scala 2374:39] - node _T_2239 = orr(mhpmc_inc_r[2]) @[dec_tlu_ctl.scala 2374:86] - node mhpmc5_wr_en1 = and(_T_2238, _T_2239) @[dec_tlu_ctl.scala 2374:66] + reg _T_2243 : UInt, rvclkhdr_29.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2243 <= mhpmc4h_ns @[lib.scala 374:16] + mhpmc4h <= _T_2243 @[dec_tlu_ctl.scala 2367:10] + node _T_2244 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2373:65] + node _T_2245 = eq(_T_2244, UInt<12>("h0b05")) @[dec_tlu_ctl.scala 2373:72] + node mhpmc5_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2245) @[dec_tlu_ctl.scala 2373:43] + node _T_2246 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2374:23] + node _T_2247 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2374:61] + node _T_2248 = or(_T_2246, _T_2247) @[dec_tlu_ctl.scala 2374:39] + node _T_2249 = orr(mhpmc_inc_r[2]) @[dec_tlu_ctl.scala 2374:86] + node mhpmc5_wr_en1 = and(_T_2248, _T_2249) @[dec_tlu_ctl.scala 2374:66] node mhpmc5_wr_en = or(mhpmc5_wr_en0, mhpmc5_wr_en1) @[dec_tlu_ctl.scala 2375:36] - node _T_2240 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2377:28] - node _T_2241 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2377:41] - node _T_2242 = cat(_T_2240, _T_2241) @[Cat.scala 29:58] - node _T_2243 = cat(UInt<63>("h00"), mhpmc_inc_r[2]) @[Cat.scala 29:58] - node _T_2244 = add(_T_2242, _T_2243) @[dec_tlu_ctl.scala 2377:49] - node _T_2245 = tail(_T_2244, 1) @[dec_tlu_ctl.scala 2377:49] - mhpmc5_incr <= _T_2245 @[dec_tlu_ctl.scala 2377:14] - node _T_2246 = bits(mhpmc5_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2378:36] - node _T_2247 = bits(mhpmc5_incr, 31, 0) @[dec_tlu_ctl.scala 2378:76] - node mhpmc5_ns = mux(_T_2246, io.dec_csr_wrdata_r, _T_2247) @[dec_tlu_ctl.scala 2378:21] - node _T_2248 = bits(mhpmc5_wr_en, 0, 0) @[dec_tlu_ctl.scala 2380:43] + node _T_2250 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2377:28] + node _T_2251 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2377:41] + node _T_2252 = cat(_T_2250, _T_2251) @[Cat.scala 29:58] + node _T_2253 = cat(UInt<63>("h00"), mhpmc_inc_r[2]) @[Cat.scala 29:58] + node _T_2254 = add(_T_2252, _T_2253) @[dec_tlu_ctl.scala 2377:49] + node _T_2255 = tail(_T_2254, 1) @[dec_tlu_ctl.scala 2377:49] + mhpmc5_incr <= _T_2255 @[dec_tlu_ctl.scala 2377:14] + node _T_2256 = bits(mhpmc5_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2378:36] + node _T_2257 = bits(mhpmc5_incr, 31, 0) @[dec_tlu_ctl.scala 2378:76] + node mhpmc5_ns = mux(_T_2256, io.dec_csr_wrdata_r, _T_2257) @[dec_tlu_ctl.scala 2378:21] + node _T_2258 = bits(mhpmc5_wr_en, 0, 0) @[dec_tlu_ctl.scala 2380:43] inst rvclkhdr_30 of rvclkhdr_750 @[lib.scala 368:23] rvclkhdr_30.clock <= clock rvclkhdr_30.reset <= reset rvclkhdr_30.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_30.io.en <= _T_2248 @[lib.scala 371:17] + rvclkhdr_30.io.en <= _T_2258 @[lib.scala 371:17] rvclkhdr_30.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2249 : UInt, rvclkhdr_30.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2249 <= mhpmc5_ns @[lib.scala 374:16] - mhpmc5 <= _T_2249 @[dec_tlu_ctl.scala 2380:9] - node _T_2250 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2382:66] - node _T_2251 = eq(_T_2250, UInt<12>("h0b85")) @[dec_tlu_ctl.scala 2382:73] - node mhpmc5h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2251) @[dec_tlu_ctl.scala 2382:44] + reg _T_2259 : UInt, rvclkhdr_30.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2259 <= mhpmc5_ns @[lib.scala 374:16] + mhpmc5 <= _T_2259 @[dec_tlu_ctl.scala 2380:9] + node _T_2260 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2382:66] + node _T_2261 = eq(_T_2260, UInt<12>("h0b85")) @[dec_tlu_ctl.scala 2382:73] + node mhpmc5h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2261) @[dec_tlu_ctl.scala 2382:44] node mhpmc5h_wr_en = or(mhpmc5h_wr_en0, mhpmc5_wr_en1) @[dec_tlu_ctl.scala 2383:38] - node _T_2252 = bits(mhpmc5h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2384:38] - node _T_2253 = bits(mhpmc5_incr, 63, 32) @[dec_tlu_ctl.scala 2384:78] - node mhpmc5h_ns = mux(_T_2252, io.dec_csr_wrdata_r, _T_2253) @[dec_tlu_ctl.scala 2384:22] - node _T_2254 = bits(mhpmc5h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2386:46] + node _T_2262 = bits(mhpmc5h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2384:38] + node _T_2263 = bits(mhpmc5_incr, 63, 32) @[dec_tlu_ctl.scala 2384:78] + node mhpmc5h_ns = mux(_T_2262, io.dec_csr_wrdata_r, _T_2263) @[dec_tlu_ctl.scala 2384:22] + node _T_2264 = bits(mhpmc5h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2386:46] inst rvclkhdr_31 of rvclkhdr_751 @[lib.scala 368:23] rvclkhdr_31.clock <= clock rvclkhdr_31.reset <= reset rvclkhdr_31.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_31.io.en <= _T_2254 @[lib.scala 371:17] + rvclkhdr_31.io.en <= _T_2264 @[lib.scala 371:17] rvclkhdr_31.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2255 : UInt, rvclkhdr_31.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2255 <= mhpmc5h_ns @[lib.scala 374:16] - mhpmc5h <= _T_2255 @[dec_tlu_ctl.scala 2386:10] - node _T_2256 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2391:65] - node _T_2257 = eq(_T_2256, UInt<12>("h0b06")) @[dec_tlu_ctl.scala 2391:72] - node mhpmc6_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2257) @[dec_tlu_ctl.scala 2391:43] - node _T_2258 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2392:23] - node _T_2259 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2392:61] - node _T_2260 = or(_T_2258, _T_2259) @[dec_tlu_ctl.scala 2392:39] - node _T_2261 = orr(mhpmc_inc_r[3]) @[dec_tlu_ctl.scala 2392:86] - node mhpmc6_wr_en1 = and(_T_2260, _T_2261) @[dec_tlu_ctl.scala 2392:66] + reg _T_2265 : UInt, rvclkhdr_31.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2265 <= mhpmc5h_ns @[lib.scala 374:16] + mhpmc5h <= _T_2265 @[dec_tlu_ctl.scala 2386:10] + node _T_2266 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2391:65] + node _T_2267 = eq(_T_2266, UInt<12>("h0b06")) @[dec_tlu_ctl.scala 2391:72] + node mhpmc6_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2267) @[dec_tlu_ctl.scala 2391:43] + node _T_2268 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2392:23] + node _T_2269 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2392:61] + node _T_2270 = or(_T_2268, _T_2269) @[dec_tlu_ctl.scala 2392:39] + node _T_2271 = orr(mhpmc_inc_r[3]) @[dec_tlu_ctl.scala 2392:86] + node mhpmc6_wr_en1 = and(_T_2270, _T_2271) @[dec_tlu_ctl.scala 2392:66] node mhpmc6_wr_en = or(mhpmc6_wr_en0, mhpmc6_wr_en1) @[dec_tlu_ctl.scala 2393:36] - node _T_2262 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2395:28] - node _T_2263 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2395:41] - node _T_2264 = cat(_T_2262, _T_2263) @[Cat.scala 29:58] - node _T_2265 = cat(UInt<63>("h00"), mhpmc_inc_r[3]) @[Cat.scala 29:58] - node _T_2266 = add(_T_2264, _T_2265) @[dec_tlu_ctl.scala 2395:49] - node _T_2267 = tail(_T_2266, 1) @[dec_tlu_ctl.scala 2395:49] - mhpmc6_incr <= _T_2267 @[dec_tlu_ctl.scala 2395:14] - node _T_2268 = bits(mhpmc6_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2396:36] - node _T_2269 = bits(mhpmc6_incr, 31, 0) @[dec_tlu_ctl.scala 2396:76] - node mhpmc6_ns = mux(_T_2268, io.dec_csr_wrdata_r, _T_2269) @[dec_tlu_ctl.scala 2396:21] - node _T_2270 = bits(mhpmc6_wr_en, 0, 0) @[dec_tlu_ctl.scala 2398:43] + node _T_2272 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2395:28] + node _T_2273 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2395:41] + node _T_2274 = cat(_T_2272, _T_2273) @[Cat.scala 29:58] + node _T_2275 = cat(UInt<63>("h00"), mhpmc_inc_r[3]) @[Cat.scala 29:58] + node _T_2276 = add(_T_2274, _T_2275) @[dec_tlu_ctl.scala 2395:49] + node _T_2277 = tail(_T_2276, 1) @[dec_tlu_ctl.scala 2395:49] + mhpmc6_incr <= _T_2277 @[dec_tlu_ctl.scala 2395:14] + node _T_2278 = bits(mhpmc6_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2396:36] + node _T_2279 = bits(mhpmc6_incr, 31, 0) @[dec_tlu_ctl.scala 2396:76] + node mhpmc6_ns = mux(_T_2278, io.dec_csr_wrdata_r, _T_2279) @[dec_tlu_ctl.scala 2396:21] + node _T_2280 = bits(mhpmc6_wr_en, 0, 0) @[dec_tlu_ctl.scala 2398:43] inst rvclkhdr_32 of rvclkhdr_752 @[lib.scala 368:23] rvclkhdr_32.clock <= clock rvclkhdr_32.reset <= reset rvclkhdr_32.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_32.io.en <= _T_2270 @[lib.scala 371:17] + rvclkhdr_32.io.en <= _T_2280 @[lib.scala 371:17] rvclkhdr_32.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2271 : UInt, rvclkhdr_32.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2271 <= mhpmc6_ns @[lib.scala 374:16] - mhpmc6 <= _T_2271 @[dec_tlu_ctl.scala 2398:9] - node _T_2272 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2400:66] - node _T_2273 = eq(_T_2272, UInt<12>("h0b86")) @[dec_tlu_ctl.scala 2400:73] - node mhpmc6h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2273) @[dec_tlu_ctl.scala 2400:44] + reg _T_2281 : UInt, rvclkhdr_32.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2281 <= mhpmc6_ns @[lib.scala 374:16] + mhpmc6 <= _T_2281 @[dec_tlu_ctl.scala 2398:9] + node _T_2282 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2400:66] + node _T_2283 = eq(_T_2282, UInt<12>("h0b86")) @[dec_tlu_ctl.scala 2400:73] + node mhpmc6h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2283) @[dec_tlu_ctl.scala 2400:44] node mhpmc6h_wr_en = or(mhpmc6h_wr_en0, mhpmc6_wr_en1) @[dec_tlu_ctl.scala 2401:38] - node _T_2274 = bits(mhpmc6h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2402:38] - node _T_2275 = bits(mhpmc6_incr, 63, 32) @[dec_tlu_ctl.scala 2402:78] - node mhpmc6h_ns = mux(_T_2274, io.dec_csr_wrdata_r, _T_2275) @[dec_tlu_ctl.scala 2402:22] - node _T_2276 = bits(mhpmc6h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2404:46] + node _T_2284 = bits(mhpmc6h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2402:38] + node _T_2285 = bits(mhpmc6_incr, 63, 32) @[dec_tlu_ctl.scala 2402:78] + node mhpmc6h_ns = mux(_T_2284, io.dec_csr_wrdata_r, _T_2285) @[dec_tlu_ctl.scala 2402:22] + node _T_2286 = bits(mhpmc6h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2404:46] inst rvclkhdr_33 of rvclkhdr_753 @[lib.scala 368:23] rvclkhdr_33.clock <= clock rvclkhdr_33.reset <= reset rvclkhdr_33.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_33.io.en <= _T_2276 @[lib.scala 371:17] + rvclkhdr_33.io.en <= _T_2286 @[lib.scala 371:17] rvclkhdr_33.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2277 : UInt, rvclkhdr_33.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2277 <= mhpmc6h_ns @[lib.scala 374:16] - mhpmc6h <= _T_2277 @[dec_tlu_ctl.scala 2404:10] - node _T_2278 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2411:50] - node _T_2279 = gt(_T_2278, UInt<10>("h0204")) @[dec_tlu_ctl.scala 2411:56] - node _T_2280 = bits(io.dec_csr_wrdata_r, 31, 10) @[dec_tlu_ctl.scala 2411:93] - node _T_2281 = orr(_T_2280) @[dec_tlu_ctl.scala 2411:102] - node _T_2282 = or(_T_2279, _T_2281) @[dec_tlu_ctl.scala 2411:71] - node _T_2283 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2411:141] - node event_saturate_r = mux(_T_2282, UInt<10>("h0204"), _T_2283) @[dec_tlu_ctl.scala 2411:28] - node _T_2284 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2413:63] - node _T_2285 = eq(_T_2284, UInt<12>("h0323")) @[dec_tlu_ctl.scala 2413:70] - node wr_mhpme3_r = and(io.dec_csr_wen_r_mod, _T_2285) @[dec_tlu_ctl.scala 2413:41] - node _T_2286 = bits(wr_mhpme3_r, 0, 0) @[dec_tlu_ctl.scala 2415:80] - reg _T_2287 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2286 : @[Reg.scala 28:19] - _T_2287 <= event_saturate_r @[Reg.scala 28:23] + reg _T_2287 : UInt, rvclkhdr_33.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2287 <= mhpmc6h_ns @[lib.scala 374:16] + mhpmc6h <= _T_2287 @[dec_tlu_ctl.scala 2404:10] + node _T_2288 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2411:50] + node _T_2289 = gt(_T_2288, UInt<10>("h0204")) @[dec_tlu_ctl.scala 2411:56] + node _T_2290 = bits(io.dec_csr_wrdata_r, 31, 10) @[dec_tlu_ctl.scala 2411:93] + node _T_2291 = orr(_T_2290) @[dec_tlu_ctl.scala 2411:102] + node _T_2292 = or(_T_2289, _T_2291) @[dec_tlu_ctl.scala 2411:71] + node _T_2293 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2411:141] + node event_saturate_r = mux(_T_2292, UInt<10>("h0204"), _T_2293) @[dec_tlu_ctl.scala 2411:28] + node _T_2294 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2413:63] + node _T_2295 = eq(_T_2294, UInt<12>("h0323")) @[dec_tlu_ctl.scala 2413:70] + node wr_mhpme3_r = and(io.dec_csr_wen_r_mod, _T_2295) @[dec_tlu_ctl.scala 2413:41] + node _T_2296 = bits(wr_mhpme3_r, 0, 0) @[dec_tlu_ctl.scala 2415:80] + reg _T_2297 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2296 : @[Reg.scala 28:19] + _T_2297 <= event_saturate_r @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mhpme3 <= _T_2287 @[dec_tlu_ctl.scala 2415:9] - node _T_2288 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2420:63] - node _T_2289 = eq(_T_2288, UInt<12>("h0324")) @[dec_tlu_ctl.scala 2420:70] - node wr_mhpme4_r = and(io.dec_csr_wen_r_mod, _T_2289) @[dec_tlu_ctl.scala 2420:41] - node _T_2290 = bits(wr_mhpme4_r, 0, 0) @[dec_tlu_ctl.scala 2421:80] - reg _T_2291 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2290 : @[Reg.scala 28:19] - _T_2291 <= event_saturate_r @[Reg.scala 28:23] + mhpme3 <= _T_2297 @[dec_tlu_ctl.scala 2415:9] + node _T_2298 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2420:63] + node _T_2299 = eq(_T_2298, UInt<12>("h0324")) @[dec_tlu_ctl.scala 2420:70] + node wr_mhpme4_r = and(io.dec_csr_wen_r_mod, _T_2299) @[dec_tlu_ctl.scala 2420:41] + node _T_2300 = bits(wr_mhpme4_r, 0, 0) @[dec_tlu_ctl.scala 2421:80] + reg _T_2301 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2300 : @[Reg.scala 28:19] + _T_2301 <= event_saturate_r @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mhpme4 <= _T_2291 @[dec_tlu_ctl.scala 2421:9] - node _T_2292 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2427:63] - node _T_2293 = eq(_T_2292, UInt<12>("h0325")) @[dec_tlu_ctl.scala 2427:70] - node wr_mhpme5_r = and(io.dec_csr_wen_r_mod, _T_2293) @[dec_tlu_ctl.scala 2427:41] - node _T_2294 = bits(wr_mhpme5_r, 0, 0) @[dec_tlu_ctl.scala 2428:80] - reg _T_2295 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2294 : @[Reg.scala 28:19] - _T_2295 <= event_saturate_r @[Reg.scala 28:23] + mhpme4 <= _T_2301 @[dec_tlu_ctl.scala 2421:9] + node _T_2302 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2427:63] + node _T_2303 = eq(_T_2302, UInt<12>("h0325")) @[dec_tlu_ctl.scala 2427:70] + node wr_mhpme5_r = and(io.dec_csr_wen_r_mod, _T_2303) @[dec_tlu_ctl.scala 2427:41] + node _T_2304 = bits(wr_mhpme5_r, 0, 0) @[dec_tlu_ctl.scala 2428:80] + reg _T_2305 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2304 : @[Reg.scala 28:19] + _T_2305 <= event_saturate_r @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mhpme5 <= _T_2295 @[dec_tlu_ctl.scala 2428:9] - node _T_2296 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2434:63] - node _T_2297 = eq(_T_2296, UInt<12>("h0326")) @[dec_tlu_ctl.scala 2434:70] - node wr_mhpme6_r = and(io.dec_csr_wen_r_mod, _T_2297) @[dec_tlu_ctl.scala 2434:41] - node _T_2298 = bits(wr_mhpme6_r, 0, 0) @[dec_tlu_ctl.scala 2435:80] - reg _T_2299 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2298 : @[Reg.scala 28:19] - _T_2299 <= event_saturate_r @[Reg.scala 28:23] + mhpme5 <= _T_2305 @[dec_tlu_ctl.scala 2428:9] + node _T_2306 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2434:63] + node _T_2307 = eq(_T_2306, UInt<12>("h0326")) @[dec_tlu_ctl.scala 2434:70] + node wr_mhpme6_r = and(io.dec_csr_wen_r_mod, _T_2307) @[dec_tlu_ctl.scala 2434:41] + node _T_2308 = bits(wr_mhpme6_r, 0, 0) @[dec_tlu_ctl.scala 2435:80] + reg _T_2309 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2308 : @[Reg.scala 28:19] + _T_2309 <= event_saturate_r @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mhpme6 <= _T_2299 @[dec_tlu_ctl.scala 2435:9] - node _T_2300 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2451:70] - node _T_2301 = eq(_T_2300, UInt<12>("h0320")) @[dec_tlu_ctl.scala 2451:77] - node wr_mcountinhibit_r = and(io.dec_csr_wen_r_mod, _T_2301) @[dec_tlu_ctl.scala 2451:48] - node _T_2302 = bits(mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2453:54] + mhpme6 <= _T_2309 @[dec_tlu_ctl.scala 2435:9] + node _T_2310 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2451:70] + node _T_2311 = eq(_T_2310, UInt<12>("h0320")) @[dec_tlu_ctl.scala 2451:77] + node wr_mcountinhibit_r = and(io.dec_csr_wen_r_mod, _T_2311) @[dec_tlu_ctl.scala 2451:48] + node _T_2312 = bits(mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2453:54] wire temp_ncount0 : UInt<1> - temp_ncount0 <= _T_2302 - node _T_2303 = bits(mcountinhibit, 1, 1) @[dec_tlu_ctl.scala 2454:54] + temp_ncount0 <= _T_2312 + node _T_2313 = bits(mcountinhibit, 1, 1) @[dec_tlu_ctl.scala 2454:54] wire temp_ncount1 : UInt<1> - temp_ncount1 <= _T_2303 - node _T_2304 = bits(mcountinhibit, 6, 2) @[dec_tlu_ctl.scala 2455:55] + temp_ncount1 <= _T_2313 + node _T_2314 = bits(mcountinhibit, 6, 2) @[dec_tlu_ctl.scala 2455:55] wire temp_ncount6_2 : UInt<5> - temp_ncount6_2 <= _T_2304 - node _T_2305 = bits(io.dec_csr_wrdata_r, 6, 2) @[dec_tlu_ctl.scala 2456:74] - node _T_2306 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2456:103] - reg _T_2307 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2306 : @[Reg.scala 28:19] - _T_2307 <= _T_2305 @[Reg.scala 28:23] + temp_ncount6_2 <= _T_2314 + node _T_2315 = bits(io.dec_csr_wrdata_r, 6, 2) @[dec_tlu_ctl.scala 2456:74] + node _T_2316 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2456:103] + reg _T_2317 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2316 : @[Reg.scala 28:19] + _T_2317 <= _T_2315 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - temp_ncount6_2 <= _T_2307 @[dec_tlu_ctl.scala 2456:17] - node _T_2308 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2458:72] - node _T_2309 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2458:99] - reg _T_2310 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2309 : @[Reg.scala 28:19] - _T_2310 <= _T_2308 @[Reg.scala 28:23] + temp_ncount6_2 <= _T_2317 @[dec_tlu_ctl.scala 2456:17] + node _T_2318 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2458:72] + node _T_2319 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2458:99] + reg _T_2320 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2319 : @[Reg.scala 28:19] + _T_2320 <= _T_2318 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - temp_ncount0 <= _T_2310 @[dec_tlu_ctl.scala 2458:15] - node _T_2311 = cat(temp_ncount6_2, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2312 = cat(_T_2311, temp_ncount0) @[Cat.scala 29:58] - mcountinhibit <= _T_2312 @[dec_tlu_ctl.scala 2459:16] - node _T_2313 = or(io.i0_valid_wb, io.exc_or_int_valid_r_d1) @[dec_tlu_ctl.scala 2466:51] - node _T_2314 = or(_T_2313, io.interrupt_valid_r_d1) @[dec_tlu_ctl.scala 2466:78] - node _T_2315 = or(_T_2314, io.dec_tlu_i0_valid_wb1) @[dec_tlu_ctl.scala 2466:104] - node _T_2316 = or(_T_2315, io.dec_tlu_i0_exc_valid_wb1) @[dec_tlu_ctl.scala 2466:130] - node _T_2317 = or(_T_2316, io.dec_tlu_int_valid_wb1) @[dec_tlu_ctl.scala 2467:32] - node _T_2318 = or(_T_2317, io.clk_override) @[dec_tlu_ctl.scala 2467:59] - node _T_2319 = bits(_T_2318, 0, 0) @[dec_tlu_ctl.scala 2467:78] + temp_ncount0 <= _T_2320 @[dec_tlu_ctl.scala 2458:15] + node _T_2321 = cat(temp_ncount6_2, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2322 = cat(_T_2321, temp_ncount0) @[Cat.scala 29:58] + mcountinhibit <= _T_2322 @[dec_tlu_ctl.scala 2459:16] + node _T_2323 = or(io.i0_valid_wb, io.exc_or_int_valid_r_d1) @[dec_tlu_ctl.scala 2466:51] + node _T_2324 = or(_T_2323, io.interrupt_valid_r_d1) @[dec_tlu_ctl.scala 2466:78] + node _T_2325 = or(_T_2324, io.dec_tlu_i0_valid_wb1) @[dec_tlu_ctl.scala 2466:104] + node _T_2326 = or(_T_2325, io.dec_tlu_i0_exc_valid_wb1) @[dec_tlu_ctl.scala 2466:130] + node _T_2327 = or(_T_2326, io.dec_tlu_int_valid_wb1) @[dec_tlu_ctl.scala 2467:32] + node _T_2328 = or(_T_2327, io.clk_override) @[dec_tlu_ctl.scala 2467:59] + node _T_2329 = bits(_T_2328, 0, 0) @[dec_tlu_ctl.scala 2467:78] inst rvclkhdr_34 of rvclkhdr_754 @[lib.scala 343:22] rvclkhdr_34.clock <= clock rvclkhdr_34.reset <= reset rvclkhdr_34.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_34.io.en <= _T_2319 @[lib.scala 345:16] + rvclkhdr_34.io.en <= _T_2329 @[lib.scala 345:16] rvclkhdr_34.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - reg _T_2320 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2469:62] - _T_2320 <= io.i0_valid_wb @[dec_tlu_ctl.scala 2469:62] - io.dec_tlu_i0_valid_wb1 <= _T_2320 @[dec_tlu_ctl.scala 2469:30] - node _T_2321 = or(io.i0_exception_valid_r_d1, io.lsu_i0_exc_r_d1) @[dec_tlu_ctl.scala 2470:91] - node _T_2322 = not(io.trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 2470:137] - node _T_2323 = and(io.trigger_hit_r_d1, _T_2322) @[dec_tlu_ctl.scala 2470:135] - node _T_2324 = or(_T_2321, _T_2323) @[dec_tlu_ctl.scala 2470:112] - reg _T_2325 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2470:62] - _T_2325 <= _T_2324 @[dec_tlu_ctl.scala 2470:62] - io.dec_tlu_i0_exc_valid_wb1 <= _T_2325 @[dec_tlu_ctl.scala 2470:30] - reg _T_2326 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2471:62] - _T_2326 <= io.exc_cause_wb @[dec_tlu_ctl.scala 2471:62] - io.dec_tlu_exc_cause_wb1 <= _T_2326 @[dec_tlu_ctl.scala 2471:30] - reg _T_2327 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2472:62] - _T_2327 <= io.interrupt_valid_r_d1 @[dec_tlu_ctl.scala 2472:62] - io.dec_tlu_int_valid_wb1 <= _T_2327 @[dec_tlu_ctl.scala 2472:30] + reg _T_2330 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2469:62] + _T_2330 <= io.i0_valid_wb @[dec_tlu_ctl.scala 2469:62] + io.dec_tlu_i0_valid_wb1 <= _T_2330 @[dec_tlu_ctl.scala 2469:30] + node _T_2331 = or(io.i0_exception_valid_r_d1, io.lsu_i0_exc_r_d1) @[dec_tlu_ctl.scala 2470:91] + node _T_2332 = not(io.trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 2470:137] + node _T_2333 = and(io.trigger_hit_r_d1, _T_2332) @[dec_tlu_ctl.scala 2470:135] + node _T_2334 = or(_T_2331, _T_2333) @[dec_tlu_ctl.scala 2470:112] + reg _T_2335 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2470:62] + _T_2335 <= _T_2334 @[dec_tlu_ctl.scala 2470:62] + io.dec_tlu_i0_exc_valid_wb1 <= _T_2335 @[dec_tlu_ctl.scala 2470:30] + reg _T_2336 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2471:62] + _T_2336 <= io.exc_cause_wb @[dec_tlu_ctl.scala 2471:62] + io.dec_tlu_exc_cause_wb1 <= _T_2336 @[dec_tlu_ctl.scala 2471:30] + reg _T_2337 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2472:62] + _T_2337 <= io.interrupt_valid_r_d1 @[dec_tlu_ctl.scala 2472:62] + io.dec_tlu_int_valid_wb1 <= _T_2337 @[dec_tlu_ctl.scala 2472:30] io.dec_tlu_mtval_wb1 <= mtval @[dec_tlu_ctl.scala 2474:24] - node _T_2328 = bits(io.csr_pkt.csr_misa, 0, 0) @[dec_tlu_ctl.scala 2480:61] - node _T_2329 = bits(io.csr_pkt.csr_mvendorid, 0, 0) @[dec_tlu_ctl.scala 2481:42] - node _T_2330 = bits(io.csr_pkt.csr_marchid, 0, 0) @[dec_tlu_ctl.scala 2482:40] - node _T_2331 = bits(io.csr_pkt.csr_mimpid, 0, 0) @[dec_tlu_ctl.scala 2483:39] - node _T_2332 = bits(io.csr_pkt.csr_mhartid, 0, 0) @[dec_tlu_ctl.scala 2484:40] - node _T_2333 = cat(io.core_id, UInt<4>("h00")) @[Cat.scala 29:58] - node _T_2334 = bits(io.csr_pkt.csr_mstatus, 0, 0) @[dec_tlu_ctl.scala 2485:40] - node _T_2335 = bits(io.mstatus, 1, 1) @[dec_tlu_ctl.scala 2485:103] - node _T_2336 = bits(io.mstatus, 0, 0) @[dec_tlu_ctl.scala 2485:128] - node _T_2337 = cat(UInt<3>("h00"), _T_2336) @[Cat.scala 29:58] - node _T_2338 = cat(_T_2337, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2339 = cat(UInt<3>("h00"), _T_2335) @[Cat.scala 29:58] - node _T_2340 = cat(UInt<19>("h00"), UInt<2>("h03")) @[Cat.scala 29:58] - node _T_2341 = cat(_T_2340, _T_2339) @[Cat.scala 29:58] - node _T_2342 = cat(_T_2341, _T_2338) @[Cat.scala 29:58] - node _T_2343 = bits(io.csr_pkt.csr_mtvec, 0, 0) @[dec_tlu_ctl.scala 2486:38] - node _T_2344 = bits(io.mtvec, 30, 1) @[dec_tlu_ctl.scala 2486:70] - node _T_2345 = bits(io.mtvec, 0, 0) @[dec_tlu_ctl.scala 2486:96] - node _T_2346 = cat(_T_2344, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2347 = cat(_T_2346, _T_2345) @[Cat.scala 29:58] - node _T_2348 = bits(io.csr_pkt.csr_mip, 0, 0) @[dec_tlu_ctl.scala 2487:36] - node _T_2349 = bits(io.mip, 5, 3) @[dec_tlu_ctl.scala 2487:78] - node _T_2350 = bits(io.mip, 2, 2) @[dec_tlu_ctl.scala 2487:102] - node _T_2351 = bits(io.mip, 1, 1) @[dec_tlu_ctl.scala 2487:123] - node _T_2352 = bits(io.mip, 0, 0) @[dec_tlu_ctl.scala 2487:144] - node _T_2353 = cat(_T_2352, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2354 = cat(_T_2351, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2355 = cat(_T_2354, _T_2353) @[Cat.scala 29:58] - node _T_2356 = cat(_T_2350, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2357 = cat(UInt<1>("h00"), _T_2349) @[Cat.scala 29:58] - node _T_2358 = cat(_T_2357, UInt<16>("h00")) @[Cat.scala 29:58] - node _T_2359 = cat(_T_2358, _T_2356) @[Cat.scala 29:58] - node _T_2360 = cat(_T_2359, _T_2355) @[Cat.scala 29:58] - node _T_2361 = bits(io.csr_pkt.csr_mie, 0, 0) @[dec_tlu_ctl.scala 2488:36] - node _T_2362 = bits(mie, 5, 3) @[dec_tlu_ctl.scala 2488:75] - node _T_2363 = bits(mie, 2, 2) @[dec_tlu_ctl.scala 2488:96] - node _T_2364 = bits(mie, 1, 1) @[dec_tlu_ctl.scala 2488:114] - node _T_2365 = bits(mie, 0, 0) @[dec_tlu_ctl.scala 2488:132] - node _T_2366 = cat(_T_2365, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2367 = cat(_T_2364, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2368 = cat(_T_2367, _T_2366) @[Cat.scala 29:58] - node _T_2369 = cat(_T_2363, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2370 = cat(UInt<1>("h00"), _T_2362) @[Cat.scala 29:58] - node _T_2371 = cat(_T_2370, UInt<16>("h00")) @[Cat.scala 29:58] - node _T_2372 = cat(_T_2371, _T_2369) @[Cat.scala 29:58] - node _T_2373 = cat(_T_2372, _T_2368) @[Cat.scala 29:58] - node _T_2374 = bits(io.csr_pkt.csr_mcyclel, 0, 0) @[dec_tlu_ctl.scala 2489:40] - node _T_2375 = bits(mcyclel, 31, 0) @[dec_tlu_ctl.scala 2489:65] - node _T_2376 = bits(io.csr_pkt.csr_mcycleh, 0, 0) @[dec_tlu_ctl.scala 2490:40] - node _T_2377 = bits(mcycleh_inc, 31, 0) @[dec_tlu_ctl.scala 2490:69] - node _T_2378 = bits(io.csr_pkt.csr_minstretl, 0, 0) @[dec_tlu_ctl.scala 2491:42] - node _T_2379 = bits(minstretl, 31, 0) @[dec_tlu_ctl.scala 2491:72] - node _T_2380 = bits(io.csr_pkt.csr_minstreth, 0, 0) @[dec_tlu_ctl.scala 2492:42] - node _T_2381 = bits(minstreth_inc, 31, 0) @[dec_tlu_ctl.scala 2492:72] - node _T_2382 = bits(io.csr_pkt.csr_mscratch, 0, 0) @[dec_tlu_ctl.scala 2493:41] - node _T_2383 = bits(mscratch, 31, 0) @[dec_tlu_ctl.scala 2493:66] - node _T_2384 = bits(io.csr_pkt.csr_mepc, 0, 0) @[dec_tlu_ctl.scala 2494:37] - node _T_2385 = cat(io.mepc, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2386 = bits(io.csr_pkt.csr_mcause, 0, 0) @[dec_tlu_ctl.scala 2495:39] - node _T_2387 = bits(mcause, 31, 0) @[dec_tlu_ctl.scala 2495:64] - node _T_2388 = bits(io.csr_pkt.csr_mscause, 0, 0) @[dec_tlu_ctl.scala 2496:40] - node _T_2389 = bits(mscause, 3, 0) @[dec_tlu_ctl.scala 2496:80] - node _T_2390 = cat(UInt<28>("h00"), _T_2389) @[Cat.scala 29:58] - node _T_2391 = bits(io.csr_pkt.csr_mtval, 0, 0) @[dec_tlu_ctl.scala 2497:38] - node _T_2392 = bits(mtval, 31, 0) @[dec_tlu_ctl.scala 2497:63] - node _T_2393 = bits(io.csr_pkt.csr_mrac, 0, 0) @[dec_tlu_ctl.scala 2498:37] - node _T_2394 = bits(mrac, 31, 0) @[dec_tlu_ctl.scala 2498:62] - node _T_2395 = bits(io.csr_pkt.csr_mdseac, 0, 0) @[dec_tlu_ctl.scala 2499:39] - node _T_2396 = bits(mdseac, 31, 0) @[dec_tlu_ctl.scala 2499:64] - node _T_2397 = bits(io.csr_pkt.csr_meivt, 0, 0) @[dec_tlu_ctl.scala 2500:38] - node _T_2398 = cat(meivt, UInt<10>("h00")) @[Cat.scala 29:58] - node _T_2399 = bits(io.csr_pkt.csr_meihap, 0, 0) @[dec_tlu_ctl.scala 2501:39] - node _T_2400 = cat(meivt, meihap) @[Cat.scala 29:58] - node _T_2401 = cat(_T_2400, UInt<2>("h00")) @[Cat.scala 29:58] - node _T_2402 = bits(io.csr_pkt.csr_meicurpl, 0, 0) @[dec_tlu_ctl.scala 2502:41] - node _T_2403 = bits(meicurpl, 3, 0) @[dec_tlu_ctl.scala 2502:81] - node _T_2404 = cat(UInt<28>("h00"), _T_2403) @[Cat.scala 29:58] - node _T_2405 = bits(io.csr_pkt.csr_meicidpl, 0, 0) @[dec_tlu_ctl.scala 2503:41] - node _T_2406 = bits(meicidpl, 3, 0) @[dec_tlu_ctl.scala 2503:81] - node _T_2407 = cat(UInt<28>("h00"), _T_2406) @[Cat.scala 29:58] - node _T_2408 = bits(io.csr_pkt.csr_meipt, 0, 0) @[dec_tlu_ctl.scala 2504:38] - node _T_2409 = bits(meipt, 3, 0) @[dec_tlu_ctl.scala 2504:78] - node _T_2410 = cat(UInt<28>("h00"), _T_2409) @[Cat.scala 29:58] - node _T_2411 = bits(io.csr_pkt.csr_mcgc, 0, 0) @[dec_tlu_ctl.scala 2505:37] - node _T_2412 = bits(mcgc, 8, 0) @[dec_tlu_ctl.scala 2505:77] - node _T_2413 = cat(UInt<23>("h00"), _T_2412) @[Cat.scala 29:58] - node _T_2414 = bits(io.csr_pkt.csr_mfdc, 0, 0) @[dec_tlu_ctl.scala 2506:37] - node _T_2415 = bits(mfdc, 18, 0) @[dec_tlu_ctl.scala 2506:77] - node _T_2416 = cat(UInt<13>("h00"), _T_2415) @[Cat.scala 29:58] - node _T_2417 = bits(io.csr_pkt.csr_dcsr, 0, 0) @[dec_tlu_ctl.scala 2507:37] - node _T_2418 = bits(io.dcsr, 15, 2) @[dec_tlu_ctl.scala 2507:85] - node _T_2419 = cat(UInt<16>("h04000"), _T_2418) @[Cat.scala 29:58] - node _T_2420 = cat(_T_2419, UInt<2>("h03")) @[Cat.scala 29:58] - node _T_2421 = bits(io.csr_pkt.csr_dpc, 0, 0) @[dec_tlu_ctl.scala 2508:36] - node _T_2422 = cat(io.dpc, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2423 = bits(io.csr_pkt.csr_dicad0, 0, 0) @[dec_tlu_ctl.scala 2509:39] - node _T_2424 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2509:64] - node _T_2425 = bits(io.csr_pkt.csr_dicad0h, 0, 0) @[dec_tlu_ctl.scala 2510:40] - node _T_2426 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2510:65] - node _T_2427 = bits(io.csr_pkt.csr_dicad1, 0, 0) @[dec_tlu_ctl.scala 2511:39] - node _T_2428 = bits(dicad1, 31, 0) @[dec_tlu_ctl.scala 2511:64] - node _T_2429 = bits(io.csr_pkt.csr_dicawics, 0, 0) @[dec_tlu_ctl.scala 2512:41] - node _T_2430 = bits(dicawics, 16, 16) @[dec_tlu_ctl.scala 2512:80] - node _T_2431 = bits(dicawics, 15, 14) @[dec_tlu_ctl.scala 2512:104] - node _T_2432 = bits(dicawics, 13, 0) @[dec_tlu_ctl.scala 2512:131] - node _T_2433 = cat(UInt<3>("h00"), _T_2432) @[Cat.scala 29:58] - node _T_2434 = cat(_T_2433, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2435 = cat(UInt<2>("h00"), _T_2431) @[Cat.scala 29:58] - node _T_2436 = cat(UInt<7>("h00"), _T_2430) @[Cat.scala 29:58] - node _T_2437 = cat(_T_2436, _T_2435) @[Cat.scala 29:58] - node _T_2438 = cat(_T_2437, _T_2434) @[Cat.scala 29:58] - node _T_2439 = bits(io.csr_pkt.csr_mtsel, 0, 0) @[dec_tlu_ctl.scala 2513:38] - node _T_2440 = bits(mtsel, 1, 0) @[dec_tlu_ctl.scala 2513:78] - node _T_2441 = cat(UInt<30>("h00"), _T_2440) @[Cat.scala 29:58] - node _T_2442 = bits(io.csr_pkt.csr_mtdata1, 0, 0) @[dec_tlu_ctl.scala 2514:40] - node _T_2443 = bits(mtdata1_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2514:74] - node _T_2444 = bits(io.csr_pkt.csr_mtdata2, 0, 0) @[dec_tlu_ctl.scala 2515:40] - node _T_2445 = bits(mtdata2_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2515:74] - node _T_2446 = bits(io.csr_pkt.csr_micect, 0, 0) @[dec_tlu_ctl.scala 2516:39] - node _T_2447 = bits(micect, 31, 0) @[dec_tlu_ctl.scala 2516:64] - node _T_2448 = bits(io.csr_pkt.csr_miccmect, 0, 0) @[dec_tlu_ctl.scala 2517:41] - node _T_2449 = bits(miccmect, 31, 0) @[dec_tlu_ctl.scala 2517:66] - node _T_2450 = bits(io.csr_pkt.csr_mdccmect, 0, 0) @[dec_tlu_ctl.scala 2518:41] - node _T_2451 = bits(mdccmect, 31, 0) @[dec_tlu_ctl.scala 2518:66] - node _T_2452 = bits(io.csr_pkt.csr_mhpmc3, 0, 0) @[dec_tlu_ctl.scala 2519:39] - node _T_2453 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2519:64] - node _T_2454 = bits(io.csr_pkt.csr_mhpmc4, 0, 0) @[dec_tlu_ctl.scala 2520:39] - node _T_2455 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2520:64] - node _T_2456 = bits(io.csr_pkt.csr_mhpmc5, 0, 0) @[dec_tlu_ctl.scala 2521:39] - node _T_2457 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2521:64] - node _T_2458 = bits(io.csr_pkt.csr_mhpmc6, 0, 0) @[dec_tlu_ctl.scala 2522:39] - node _T_2459 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2522:64] - node _T_2460 = bits(io.csr_pkt.csr_mhpmc3h, 0, 0) @[dec_tlu_ctl.scala 2523:40] - node _T_2461 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2523:65] - node _T_2462 = bits(io.csr_pkt.csr_mhpmc4h, 0, 0) @[dec_tlu_ctl.scala 2524:40] - node _T_2463 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2524:65] - node _T_2464 = bits(io.csr_pkt.csr_mhpmc5h, 0, 0) @[dec_tlu_ctl.scala 2525:40] - node _T_2465 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2525:65] - node _T_2466 = bits(io.csr_pkt.csr_mhpmc6h, 0, 0) @[dec_tlu_ctl.scala 2526:40] - node _T_2467 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2526:65] - node _T_2468 = bits(io.csr_pkt.csr_mfdht, 0, 0) @[dec_tlu_ctl.scala 2527:38] - node _T_2469 = bits(mfdht, 5, 0) @[dec_tlu_ctl.scala 2527:78] - node _T_2470 = cat(UInt<26>("h00"), _T_2469) @[Cat.scala 29:58] - node _T_2471 = bits(io.csr_pkt.csr_mfdhs, 0, 0) @[dec_tlu_ctl.scala 2528:38] - node _T_2472 = bits(mfdhs, 1, 0) @[dec_tlu_ctl.scala 2528:78] - node _T_2473 = cat(UInt<30>("h00"), _T_2472) @[Cat.scala 29:58] - node _T_2474 = bits(io.csr_pkt.csr_mhpme3, 0, 0) @[dec_tlu_ctl.scala 2529:39] - node _T_2475 = bits(mhpme3, 9, 0) @[dec_tlu_ctl.scala 2529:79] - node _T_2476 = cat(UInt<22>("h00"), _T_2475) @[Cat.scala 29:58] - node _T_2477 = bits(io.csr_pkt.csr_mhpme4, 0, 0) @[dec_tlu_ctl.scala 2530:39] - node _T_2478 = bits(mhpme4, 9, 0) @[dec_tlu_ctl.scala 2530:79] - node _T_2479 = cat(UInt<22>("h00"), _T_2478) @[Cat.scala 29:58] - node _T_2480 = bits(io.csr_pkt.csr_mhpme5, 0, 0) @[dec_tlu_ctl.scala 2531:39] - node _T_2481 = bits(mhpme5, 9, 0) @[dec_tlu_ctl.scala 2531:78] - node _T_2482 = cat(UInt<22>("h00"), _T_2481) @[Cat.scala 29:58] - node _T_2483 = bits(io.csr_pkt.csr_mhpme6, 0, 0) @[dec_tlu_ctl.scala 2532:39] - node _T_2484 = bits(mhpme6, 9, 0) @[dec_tlu_ctl.scala 2532:78] - node _T_2485 = cat(UInt<22>("h00"), _T_2484) @[Cat.scala 29:58] - node _T_2486 = bits(io.csr_pkt.csr_mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2533:46] - node _T_2487 = bits(mcountinhibit, 6, 0) @[dec_tlu_ctl.scala 2533:86] - node _T_2488 = cat(UInt<25>("h00"), _T_2487) @[Cat.scala 29:58] - node _T_2489 = bits(io.csr_pkt.csr_mpmc, 0, 0) @[dec_tlu_ctl.scala 2534:37] - node _T_2490 = cat(UInt<30>("h00"), mpmc) @[Cat.scala 29:58] - node _T_2491 = cat(_T_2490, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2492 = bits(io.dec_timer_read_d, 0, 0) @[dec_tlu_ctl.scala 2535:37] - node _T_2493 = bits(io.dec_timer_rddata_d, 31, 0) @[dec_tlu_ctl.scala 2535:76] - node _T_2494 = mux(_T_2328, UInt<32>("h040001104"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2495 = mux(_T_2329, UInt<32>("h045"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2496 = mux(_T_2330, UInt<32>("h010"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2497 = mux(_T_2331, UInt<32>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2498 = mux(_T_2332, _T_2333, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2499 = mux(_T_2334, _T_2342, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2500 = mux(_T_2343, _T_2347, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2501 = mux(_T_2348, _T_2360, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2502 = mux(_T_2361, _T_2373, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2503 = mux(_T_2374, _T_2375, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2504 = mux(_T_2376, _T_2377, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2505 = mux(_T_2378, _T_2379, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2506 = mux(_T_2380, _T_2381, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2507 = mux(_T_2382, _T_2383, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2508 = mux(_T_2384, _T_2385, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2509 = mux(_T_2386, _T_2387, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2510 = mux(_T_2388, _T_2390, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2511 = mux(_T_2391, _T_2392, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2512 = mux(_T_2393, _T_2394, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2513 = mux(_T_2395, _T_2396, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2514 = mux(_T_2397, _T_2398, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2515 = mux(_T_2399, _T_2401, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2516 = mux(_T_2402, _T_2404, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2517 = mux(_T_2405, _T_2407, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2518 = mux(_T_2408, _T_2410, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2519 = mux(_T_2411, _T_2413, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2520 = mux(_T_2414, _T_2416, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2521 = mux(_T_2417, _T_2420, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2522 = mux(_T_2421, _T_2422, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2523 = mux(_T_2423, _T_2424, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2524 = mux(_T_2425, _T_2426, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2525 = mux(_T_2427, _T_2428, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2526 = mux(_T_2429, _T_2438, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2527 = mux(_T_2439, _T_2441, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2528 = mux(_T_2442, _T_2443, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2529 = mux(_T_2444, _T_2445, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2530 = mux(_T_2446, _T_2447, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2531 = mux(_T_2448, _T_2449, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2532 = mux(_T_2450, _T_2451, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2533 = mux(_T_2452, _T_2453, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2534 = mux(_T_2454, _T_2455, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2535 = mux(_T_2456, _T_2457, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2536 = mux(_T_2458, _T_2459, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2537 = mux(_T_2460, _T_2461, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2538 = mux(_T_2462, _T_2463, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2539 = mux(_T_2464, _T_2465, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2540 = mux(_T_2466, _T_2467, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2541 = mux(_T_2468, _T_2470, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2542 = mux(_T_2471, _T_2473, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2543 = mux(_T_2474, _T_2476, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2544 = mux(_T_2477, _T_2479, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2545 = mux(_T_2480, _T_2482, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2546 = mux(_T_2483, _T_2485, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2547 = mux(_T_2486, _T_2488, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2548 = mux(_T_2489, _T_2491, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2549 = mux(_T_2492, _T_2493, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2550 = or(_T_2494, _T_2495) @[Mux.scala 27:72] - node _T_2551 = or(_T_2550, _T_2496) @[Mux.scala 27:72] - node _T_2552 = or(_T_2551, _T_2497) @[Mux.scala 27:72] - node _T_2553 = or(_T_2552, _T_2498) @[Mux.scala 27:72] - node _T_2554 = or(_T_2553, _T_2499) @[Mux.scala 27:72] - node _T_2555 = or(_T_2554, _T_2500) @[Mux.scala 27:72] - node _T_2556 = or(_T_2555, _T_2501) @[Mux.scala 27:72] - node _T_2557 = or(_T_2556, _T_2502) @[Mux.scala 27:72] - node _T_2558 = or(_T_2557, _T_2503) @[Mux.scala 27:72] - node _T_2559 = or(_T_2558, _T_2504) @[Mux.scala 27:72] - node _T_2560 = or(_T_2559, _T_2505) @[Mux.scala 27:72] + node _T_2338 = bits(io.csr_pkt.csr_misa, 0, 0) @[dec_tlu_ctl.scala 2480:61] + node _T_2339 = bits(io.csr_pkt.csr_mvendorid, 0, 0) @[dec_tlu_ctl.scala 2481:42] + node _T_2340 = bits(io.csr_pkt.csr_marchid, 0, 0) @[dec_tlu_ctl.scala 2482:40] + node _T_2341 = bits(io.csr_pkt.csr_mimpid, 0, 0) @[dec_tlu_ctl.scala 2483:39] + node _T_2342 = bits(io.csr_pkt.csr_mhartid, 0, 0) @[dec_tlu_ctl.scala 2484:40] + node _T_2343 = cat(io.core_id, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_2344 = bits(io.csr_pkt.csr_mstatus, 0, 0) @[dec_tlu_ctl.scala 2485:40] + node _T_2345 = bits(io.mstatus, 1, 1) @[dec_tlu_ctl.scala 2485:103] + node _T_2346 = bits(io.mstatus, 0, 0) @[dec_tlu_ctl.scala 2485:128] + node _T_2347 = cat(UInt<3>("h00"), _T_2346) @[Cat.scala 29:58] + node _T_2348 = cat(_T_2347, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2349 = cat(UInt<3>("h00"), _T_2345) @[Cat.scala 29:58] + node _T_2350 = cat(UInt<19>("h00"), UInt<2>("h03")) @[Cat.scala 29:58] + node _T_2351 = cat(_T_2350, _T_2349) @[Cat.scala 29:58] + node _T_2352 = cat(_T_2351, _T_2348) @[Cat.scala 29:58] + node _T_2353 = bits(io.csr_pkt.csr_mtvec, 0, 0) @[dec_tlu_ctl.scala 2486:38] + node _T_2354 = bits(io.mtvec, 30, 1) @[dec_tlu_ctl.scala 2486:70] + node _T_2355 = bits(io.mtvec, 0, 0) @[dec_tlu_ctl.scala 2486:96] + node _T_2356 = cat(_T_2354, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2357 = cat(_T_2356, _T_2355) @[Cat.scala 29:58] + node _T_2358 = bits(io.csr_pkt.csr_mip, 0, 0) @[dec_tlu_ctl.scala 2487:36] + node _T_2359 = bits(io.mip, 5, 3) @[dec_tlu_ctl.scala 2487:78] + node _T_2360 = bits(io.mip, 2, 2) @[dec_tlu_ctl.scala 2487:102] + node _T_2361 = bits(io.mip, 1, 1) @[dec_tlu_ctl.scala 2487:123] + node _T_2362 = bits(io.mip, 0, 0) @[dec_tlu_ctl.scala 2487:144] + node _T_2363 = cat(_T_2362, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2364 = cat(_T_2361, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2365 = cat(_T_2364, _T_2363) @[Cat.scala 29:58] + node _T_2366 = cat(_T_2360, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2367 = cat(UInt<1>("h00"), _T_2359) @[Cat.scala 29:58] + node _T_2368 = cat(_T_2367, UInt<16>("h00")) @[Cat.scala 29:58] + node _T_2369 = cat(_T_2368, _T_2366) @[Cat.scala 29:58] + node _T_2370 = cat(_T_2369, _T_2365) @[Cat.scala 29:58] + node _T_2371 = bits(io.csr_pkt.csr_mie, 0, 0) @[dec_tlu_ctl.scala 2488:36] + node _T_2372 = bits(mie, 5, 3) @[dec_tlu_ctl.scala 2488:75] + node _T_2373 = bits(mie, 2, 2) @[dec_tlu_ctl.scala 2488:96] + node _T_2374 = bits(mie, 1, 1) @[dec_tlu_ctl.scala 2488:114] + node _T_2375 = bits(mie, 0, 0) @[dec_tlu_ctl.scala 2488:132] + node _T_2376 = cat(_T_2375, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2377 = cat(_T_2374, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2378 = cat(_T_2377, _T_2376) @[Cat.scala 29:58] + node _T_2379 = cat(_T_2373, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2380 = cat(UInt<1>("h00"), _T_2372) @[Cat.scala 29:58] + node _T_2381 = cat(_T_2380, UInt<16>("h00")) @[Cat.scala 29:58] + node _T_2382 = cat(_T_2381, _T_2379) @[Cat.scala 29:58] + node _T_2383 = cat(_T_2382, _T_2378) @[Cat.scala 29:58] + node _T_2384 = bits(io.csr_pkt.csr_mcyclel, 0, 0) @[dec_tlu_ctl.scala 2489:40] + node _T_2385 = bits(mcyclel, 31, 0) @[dec_tlu_ctl.scala 2489:65] + node _T_2386 = bits(io.csr_pkt.csr_mcycleh, 0, 0) @[dec_tlu_ctl.scala 2490:40] + node _T_2387 = bits(mcycleh_inc, 31, 0) @[dec_tlu_ctl.scala 2490:69] + node _T_2388 = bits(io.csr_pkt.csr_minstretl, 0, 0) @[dec_tlu_ctl.scala 2491:42] + node _T_2389 = bits(minstretl, 31, 0) @[dec_tlu_ctl.scala 2491:72] + node _T_2390 = bits(io.csr_pkt.csr_minstreth, 0, 0) @[dec_tlu_ctl.scala 2492:42] + node _T_2391 = bits(minstreth_inc, 31, 0) @[dec_tlu_ctl.scala 2492:72] + node _T_2392 = bits(io.csr_pkt.csr_mscratch, 0, 0) @[dec_tlu_ctl.scala 2493:41] + node _T_2393 = bits(mscratch, 31, 0) @[dec_tlu_ctl.scala 2493:66] + node _T_2394 = bits(io.csr_pkt.csr_mepc, 0, 0) @[dec_tlu_ctl.scala 2494:37] + node _T_2395 = cat(io.mepc, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2396 = bits(io.csr_pkt.csr_mcause, 0, 0) @[dec_tlu_ctl.scala 2495:39] + node _T_2397 = bits(mcause, 31, 0) @[dec_tlu_ctl.scala 2495:64] + node _T_2398 = bits(io.csr_pkt.csr_mscause, 0, 0) @[dec_tlu_ctl.scala 2496:40] + node _T_2399 = bits(mscause, 3, 0) @[dec_tlu_ctl.scala 2496:80] + node _T_2400 = cat(UInt<28>("h00"), _T_2399) @[Cat.scala 29:58] + node _T_2401 = bits(io.csr_pkt.csr_mtval, 0, 0) @[dec_tlu_ctl.scala 2497:38] + node _T_2402 = bits(mtval, 31, 0) @[dec_tlu_ctl.scala 2497:63] + node _T_2403 = bits(io.csr_pkt.csr_mrac, 0, 0) @[dec_tlu_ctl.scala 2498:37] + node _T_2404 = bits(mrac, 31, 0) @[dec_tlu_ctl.scala 2498:62] + node _T_2405 = bits(io.csr_pkt.csr_mdseac, 0, 0) @[dec_tlu_ctl.scala 2499:39] + node _T_2406 = bits(mdseac, 31, 0) @[dec_tlu_ctl.scala 2499:64] + node _T_2407 = bits(io.csr_pkt.csr_meivt, 0, 0) @[dec_tlu_ctl.scala 2500:38] + node _T_2408 = cat(meivt, UInt<10>("h00")) @[Cat.scala 29:58] + node _T_2409 = bits(io.csr_pkt.csr_meihap, 0, 0) @[dec_tlu_ctl.scala 2501:39] + node _T_2410 = cat(meivt, meihap) @[Cat.scala 29:58] + node _T_2411 = cat(_T_2410, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_2412 = bits(io.csr_pkt.csr_meicurpl, 0, 0) @[dec_tlu_ctl.scala 2502:41] + node _T_2413 = bits(meicurpl, 3, 0) @[dec_tlu_ctl.scala 2502:81] + node _T_2414 = cat(UInt<28>("h00"), _T_2413) @[Cat.scala 29:58] + node _T_2415 = bits(io.csr_pkt.csr_meicidpl, 0, 0) @[dec_tlu_ctl.scala 2503:41] + node _T_2416 = bits(meicidpl, 3, 0) @[dec_tlu_ctl.scala 2503:81] + node _T_2417 = cat(UInt<28>("h00"), _T_2416) @[Cat.scala 29:58] + node _T_2418 = bits(io.csr_pkt.csr_meipt, 0, 0) @[dec_tlu_ctl.scala 2504:38] + node _T_2419 = bits(meipt, 3, 0) @[dec_tlu_ctl.scala 2504:78] + node _T_2420 = cat(UInt<28>("h00"), _T_2419) @[Cat.scala 29:58] + node _T_2421 = bits(io.csr_pkt.csr_mcgc, 0, 0) @[dec_tlu_ctl.scala 2505:37] + node _T_2422 = bits(mcgc, 8, 0) @[dec_tlu_ctl.scala 2505:77] + node _T_2423 = cat(UInt<23>("h00"), _T_2422) @[Cat.scala 29:58] + node _T_2424 = bits(io.csr_pkt.csr_mfdc, 0, 0) @[dec_tlu_ctl.scala 2506:37] + node _T_2425 = bits(mfdc, 18, 0) @[dec_tlu_ctl.scala 2506:77] + node _T_2426 = cat(UInt<13>("h00"), _T_2425) @[Cat.scala 29:58] + node _T_2427 = bits(io.csr_pkt.csr_dcsr, 0, 0) @[dec_tlu_ctl.scala 2507:37] + node _T_2428 = bits(io.dcsr, 15, 2) @[dec_tlu_ctl.scala 2507:85] + node _T_2429 = cat(UInt<16>("h04000"), _T_2428) @[Cat.scala 29:58] + node _T_2430 = cat(_T_2429, UInt<2>("h03")) @[Cat.scala 29:58] + node _T_2431 = bits(io.csr_pkt.csr_dpc, 0, 0) @[dec_tlu_ctl.scala 2508:36] + node _T_2432 = cat(io.dpc, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2433 = bits(io.csr_pkt.csr_dicad0, 0, 0) @[dec_tlu_ctl.scala 2509:39] + node _T_2434 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2509:64] + node _T_2435 = bits(io.csr_pkt.csr_dicad0h, 0, 0) @[dec_tlu_ctl.scala 2510:40] + node _T_2436 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2510:65] + node _T_2437 = bits(io.csr_pkt.csr_dicad1, 0, 0) @[dec_tlu_ctl.scala 2511:39] + node _T_2438 = bits(dicad1, 31, 0) @[dec_tlu_ctl.scala 2511:64] + node _T_2439 = bits(io.csr_pkt.csr_dicawics, 0, 0) @[dec_tlu_ctl.scala 2512:41] + node _T_2440 = bits(dicawics, 16, 16) @[dec_tlu_ctl.scala 2512:80] + node _T_2441 = bits(dicawics, 15, 14) @[dec_tlu_ctl.scala 2512:104] + node _T_2442 = bits(dicawics, 13, 0) @[dec_tlu_ctl.scala 2512:131] + node _T_2443 = cat(UInt<3>("h00"), _T_2442) @[Cat.scala 29:58] + node _T_2444 = cat(_T_2443, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2445 = cat(UInt<2>("h00"), _T_2441) @[Cat.scala 29:58] + node _T_2446 = cat(UInt<7>("h00"), _T_2440) @[Cat.scala 29:58] + node _T_2447 = cat(_T_2446, _T_2445) @[Cat.scala 29:58] + node _T_2448 = cat(_T_2447, _T_2444) @[Cat.scala 29:58] + node _T_2449 = bits(io.csr_pkt.csr_mtsel, 0, 0) @[dec_tlu_ctl.scala 2513:38] + node _T_2450 = bits(mtsel, 1, 0) @[dec_tlu_ctl.scala 2513:78] + node _T_2451 = cat(UInt<30>("h00"), _T_2450) @[Cat.scala 29:58] + node _T_2452 = bits(io.csr_pkt.csr_mtdata1, 0, 0) @[dec_tlu_ctl.scala 2514:40] + node _T_2453 = bits(mtdata1_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2514:74] + node _T_2454 = bits(io.csr_pkt.csr_mtdata2, 0, 0) @[dec_tlu_ctl.scala 2515:40] + node _T_2455 = bits(mtdata2_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2515:74] + node _T_2456 = bits(io.csr_pkt.csr_micect, 0, 0) @[dec_tlu_ctl.scala 2516:39] + node _T_2457 = bits(micect, 31, 0) @[dec_tlu_ctl.scala 2516:64] + node _T_2458 = bits(io.csr_pkt.csr_miccmect, 0, 0) @[dec_tlu_ctl.scala 2517:41] + node _T_2459 = bits(miccmect, 31, 0) @[dec_tlu_ctl.scala 2517:66] + node _T_2460 = bits(io.csr_pkt.csr_mdccmect, 0, 0) @[dec_tlu_ctl.scala 2518:41] + node _T_2461 = bits(mdccmect, 31, 0) @[dec_tlu_ctl.scala 2518:66] + node _T_2462 = bits(io.csr_pkt.csr_mhpmc3, 0, 0) @[dec_tlu_ctl.scala 2519:39] + node _T_2463 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2519:64] + node _T_2464 = bits(io.csr_pkt.csr_mhpmc4, 0, 0) @[dec_tlu_ctl.scala 2520:39] + node _T_2465 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2520:64] + node _T_2466 = bits(io.csr_pkt.csr_mhpmc5, 0, 0) @[dec_tlu_ctl.scala 2521:39] + node _T_2467 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2521:64] + node _T_2468 = bits(io.csr_pkt.csr_mhpmc6, 0, 0) @[dec_tlu_ctl.scala 2522:39] + node _T_2469 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2522:64] + node _T_2470 = bits(io.csr_pkt.csr_mhpmc3h, 0, 0) @[dec_tlu_ctl.scala 2523:40] + node _T_2471 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2523:65] + node _T_2472 = bits(io.csr_pkt.csr_mhpmc4h, 0, 0) @[dec_tlu_ctl.scala 2524:40] + node _T_2473 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2524:65] + node _T_2474 = bits(io.csr_pkt.csr_mhpmc5h, 0, 0) @[dec_tlu_ctl.scala 2525:40] + node _T_2475 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2525:65] + node _T_2476 = bits(io.csr_pkt.csr_mhpmc6h, 0, 0) @[dec_tlu_ctl.scala 2526:40] + node _T_2477 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2526:65] + node _T_2478 = bits(io.csr_pkt.csr_mfdht, 0, 0) @[dec_tlu_ctl.scala 2527:38] + node _T_2479 = bits(mfdht, 5, 0) @[dec_tlu_ctl.scala 2527:78] + node _T_2480 = cat(UInt<26>("h00"), _T_2479) @[Cat.scala 29:58] + node _T_2481 = bits(io.csr_pkt.csr_mfdhs, 0, 0) @[dec_tlu_ctl.scala 2528:38] + node _T_2482 = bits(mfdhs, 1, 0) @[dec_tlu_ctl.scala 2528:78] + node _T_2483 = cat(UInt<30>("h00"), _T_2482) @[Cat.scala 29:58] + node _T_2484 = bits(io.csr_pkt.csr_mhpme3, 0, 0) @[dec_tlu_ctl.scala 2529:39] + node _T_2485 = bits(mhpme3, 9, 0) @[dec_tlu_ctl.scala 2529:79] + node _T_2486 = cat(UInt<22>("h00"), _T_2485) @[Cat.scala 29:58] + node _T_2487 = bits(io.csr_pkt.csr_mhpme4, 0, 0) @[dec_tlu_ctl.scala 2530:39] + node _T_2488 = bits(mhpme4, 9, 0) @[dec_tlu_ctl.scala 2530:79] + node _T_2489 = cat(UInt<22>("h00"), _T_2488) @[Cat.scala 29:58] + node _T_2490 = bits(io.csr_pkt.csr_mhpme5, 0, 0) @[dec_tlu_ctl.scala 2531:39] + node _T_2491 = bits(mhpme5, 9, 0) @[dec_tlu_ctl.scala 2531:78] + node _T_2492 = cat(UInt<22>("h00"), _T_2491) @[Cat.scala 29:58] + node _T_2493 = bits(io.csr_pkt.csr_mhpme6, 0, 0) @[dec_tlu_ctl.scala 2532:39] + node _T_2494 = bits(mhpme6, 9, 0) @[dec_tlu_ctl.scala 2532:78] + node _T_2495 = cat(UInt<22>("h00"), _T_2494) @[Cat.scala 29:58] + node _T_2496 = bits(io.csr_pkt.csr_mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2533:46] + node _T_2497 = bits(mcountinhibit, 6, 0) @[dec_tlu_ctl.scala 2533:86] + node _T_2498 = cat(UInt<25>("h00"), _T_2497) @[Cat.scala 29:58] + node _T_2499 = bits(io.csr_pkt.csr_mpmc, 0, 0) @[dec_tlu_ctl.scala 2534:37] + node _T_2500 = cat(UInt<30>("h00"), mpmc) @[Cat.scala 29:58] + node _T_2501 = cat(_T_2500, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2502 = bits(io.dec_timer_read_d, 0, 0) @[dec_tlu_ctl.scala 2535:37] + node _T_2503 = bits(io.dec_timer_rddata_d, 31, 0) @[dec_tlu_ctl.scala 2535:76] + node _T_2504 = mux(_T_2338, UInt<32>("h040001104"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2505 = mux(_T_2339, UInt<32>("h045"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2506 = mux(_T_2340, UInt<32>("h010"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2507 = mux(_T_2341, UInt<32>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2508 = mux(_T_2342, _T_2343, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2509 = mux(_T_2344, _T_2352, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2510 = mux(_T_2353, _T_2357, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2511 = mux(_T_2358, _T_2370, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2512 = mux(_T_2371, _T_2383, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2513 = mux(_T_2384, _T_2385, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2514 = mux(_T_2386, _T_2387, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2515 = mux(_T_2388, _T_2389, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2516 = mux(_T_2390, _T_2391, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2517 = mux(_T_2392, _T_2393, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2518 = mux(_T_2394, _T_2395, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2519 = mux(_T_2396, _T_2397, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2520 = mux(_T_2398, _T_2400, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2521 = mux(_T_2401, _T_2402, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2522 = mux(_T_2403, _T_2404, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2523 = mux(_T_2405, _T_2406, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2524 = mux(_T_2407, _T_2408, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2525 = mux(_T_2409, _T_2411, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2526 = mux(_T_2412, _T_2414, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2527 = mux(_T_2415, _T_2417, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2528 = mux(_T_2418, _T_2420, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2529 = mux(_T_2421, _T_2423, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2530 = mux(_T_2424, _T_2426, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2531 = mux(_T_2427, _T_2430, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2532 = mux(_T_2431, _T_2432, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2533 = mux(_T_2433, _T_2434, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2534 = mux(_T_2435, _T_2436, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2535 = mux(_T_2437, _T_2438, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2536 = mux(_T_2439, _T_2448, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2537 = mux(_T_2449, _T_2451, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2538 = mux(_T_2452, _T_2453, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2539 = mux(_T_2454, _T_2455, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2540 = mux(_T_2456, _T_2457, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2541 = mux(_T_2458, _T_2459, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2542 = mux(_T_2460, _T_2461, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2543 = mux(_T_2462, _T_2463, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2544 = mux(_T_2464, _T_2465, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2545 = mux(_T_2466, _T_2467, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2546 = mux(_T_2468, _T_2469, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2547 = mux(_T_2470, _T_2471, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2548 = mux(_T_2472, _T_2473, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2549 = mux(_T_2474, _T_2475, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2550 = mux(_T_2476, _T_2477, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2551 = mux(_T_2478, _T_2480, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2552 = mux(_T_2481, _T_2483, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2553 = mux(_T_2484, _T_2486, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2554 = mux(_T_2487, _T_2489, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2555 = mux(_T_2490, _T_2492, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2556 = mux(_T_2493, _T_2495, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2557 = mux(_T_2496, _T_2498, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2558 = mux(_T_2499, _T_2501, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2559 = mux(_T_2502, _T_2503, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2560 = or(_T_2504, _T_2505) @[Mux.scala 27:72] node _T_2561 = or(_T_2560, _T_2506) @[Mux.scala 27:72] node _T_2562 = or(_T_2561, _T_2507) @[Mux.scala 27:72] node _T_2563 = or(_T_2562, _T_2508) @[Mux.scala 27:72] @@ -76166,9 +76166,19 @@ circuit quasar_wrapper : node _T_2602 = or(_T_2601, _T_2547) @[Mux.scala 27:72] node _T_2603 = or(_T_2602, _T_2548) @[Mux.scala 27:72] node _T_2604 = or(_T_2603, _T_2549) @[Mux.scala 27:72] - wire _T_2605 : UInt @[Mux.scala 27:72] - _T_2605 <= _T_2604 @[Mux.scala 27:72] - io.dec_csr_rddata_d <= _T_2605 @[dec_tlu_ctl.scala 2479:21] + node _T_2605 = or(_T_2604, _T_2550) @[Mux.scala 27:72] + node _T_2606 = or(_T_2605, _T_2551) @[Mux.scala 27:72] + node _T_2607 = or(_T_2606, _T_2552) @[Mux.scala 27:72] + node _T_2608 = or(_T_2607, _T_2553) @[Mux.scala 27:72] + node _T_2609 = or(_T_2608, _T_2554) @[Mux.scala 27:72] + node _T_2610 = or(_T_2609, _T_2555) @[Mux.scala 27:72] + node _T_2611 = or(_T_2610, _T_2556) @[Mux.scala 27:72] + node _T_2612 = or(_T_2611, _T_2557) @[Mux.scala 27:72] + node _T_2613 = or(_T_2612, _T_2558) @[Mux.scala 27:72] + node _T_2614 = or(_T_2613, _T_2559) @[Mux.scala 27:72] + wire _T_2615 : UInt @[Mux.scala 27:72] + _T_2615 <= _T_2614 @[Mux.scala 27:72] + io.dec_csr_rddata_d <= _T_2615 @[dec_tlu_ctl.scala 2479:21] module dec_decode_csr_read : input clock : Clock @@ -95886,7 +95896,7 @@ circuit quasar_wrapper : node _T_748 = and(ld_fwddata_buf_hi_initial, ibuf_data) @[lsu_bus_buffer.scala 175:32] node _T_749 = or(_T_747, _T_748) @[lsu_bus_buffer.scala 174:103] io.ld_fwddata_buf_hi <= _T_749 @[lsu_bus_buffer.scala 171:24] - node bus_coalescing_disable = or(io.tlu_busbuff.dec_tlu_wb_coalescing_disable, UInt<1>("h01")) @[lsu_bus_buffer.scala 177:77] + node bus_coalescing_disable = or(io.tlu_busbuff.dec_tlu_wb_coalescing_disable, UInt<1>("h00")) @[lsu_bus_buffer.scala 177:77] node _T_750 = mux(io.lsu_pkt_r.bits.by, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_751 = mux(io.lsu_pkt_r.bits.half, UInt<4>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_752 = mux(io.lsu_pkt_r.bits.word, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72] @@ -109046,4831 +109056,6 @@ circuit quasar_wrapper : clkhdr.EN <= io.en @[lib.scala 337:18] clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - extmodule gated_latch_849 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_849 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_849 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_850 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_850 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_850 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_851 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_851 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_851 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_852 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_852 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_852 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_853 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_853 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_853 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_854 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_854 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_854 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_855 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_855 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_855 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_856 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_856 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_856 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_857 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_857 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_857 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_858 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_858 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_858 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - module axi4_to_ahb : - input clock : Clock - input reset : AsyncReset - output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ahb : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}} - - wire buf_rst : UInt<1> - buf_rst <= UInt<1>("h00") - buf_rst <= UInt<1>("h00") @[axi4_to_ahb.scala 21:11] - io.ahb.out.htrans <= UInt<1>("h00") @[axi4_to_ahb.scala 22:21] - wire buf_state_en : UInt<1> - buf_state_en <= UInt<1>("h00") - wire ahbm_clk : Clock @[axi4_to_ahb.scala 24:22] - wire ahbm_addr_clk : Clock @[axi4_to_ahb.scala 25:27] - wire ahbm_data_clk : Clock @[axi4_to_ahb.scala 26:27] - wire buf_state : UInt<3> - buf_state <= UInt<3>("h00") - wire buf_nxtstate : UInt<3> - buf_nxtstate <= UInt<3>("h00") - node _T = bits(buf_state_en, 0, 0) @[axi4_to_ahb.scala 30:70] - node _T_1 = mux(_T, buf_nxtstate, buf_state) @[axi4_to_ahb.scala 30:50] - node _T_2 = eq(buf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 30:108] - node _T_3 = bits(_T_2, 0, 0) @[Bitwise.scala 72:15] - node _T_4 = mux(_T_3, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_5 = and(_T_1, _T_4) @[axi4_to_ahb.scala 30:98] - reg _T_6 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 30:45] - _T_6 <= _T_5 @[axi4_to_ahb.scala 30:45] - buf_state <= _T_6 @[axi4_to_ahb.scala 30:13] - wire slave_valid : UInt<1> - slave_valid <= UInt<1>("h00") - wire slave_ready : UInt<1> - slave_ready <= UInt<1>("h00") - wire slave_tag : UInt<1> - slave_tag <= UInt<1>("h00") - wire slave_rdata : UInt<64> - slave_rdata <= UInt<64>("h00") - wire slave_opc : UInt<4> - slave_opc <= UInt<4>("h00") - wire wrbuf_en : UInt<1> - wrbuf_en <= UInt<1>("h00") - wire wrbuf_data_en : UInt<1> - wrbuf_data_en <= UInt<1>("h00") - wire wrbuf_cmd_sent : UInt<1> - wrbuf_cmd_sent <= UInt<1>("h00") - wire wrbuf_rst : UInt<1> - wrbuf_rst <= UInt<1>("h00") - wire wrbuf_vld : UInt<1> - wrbuf_vld <= UInt<1>("h00") - wire wrbuf_data_vld : UInt<1> - wrbuf_data_vld <= UInt<1>("h00") - wire wrbuf_tag : UInt<1> - wrbuf_tag <= UInt<1>("h00") - wire wrbuf_size : UInt<3> - wrbuf_size <= UInt<3>("h00") - wire wrbuf_addr : UInt<32> - wrbuf_addr <= UInt<32>("h00") - wire wrbuf_data : UInt<64> - wrbuf_data <= UInt<64>("h00") - wire wrbuf_byteen : UInt<8> - wrbuf_byteen <= UInt<8>("h00") - wire bus_write_clk_en : UInt<1> - bus_write_clk_en <= UInt<1>("h00") - wire bus_clk : Clock @[axi4_to_ahb.scala 50:21] - wire bus_write_clk : Clock @[axi4_to_ahb.scala 51:27] - wire master_valid : UInt<1> - master_valid <= UInt<1>("h00") - wire master_ready : UInt<1> - master_ready <= UInt<1>("h00") - wire master_tag : UInt<1> - master_tag <= UInt<1>("h00") - wire master_addr : UInt<32> - master_addr <= UInt<32>("h00") - wire master_wdata : UInt<64> - master_wdata <= UInt<64>("h00") - wire master_size : UInt<3> - master_size <= UInt<3>("h00") - wire master_opc : UInt<3> - master_opc <= UInt<3>("h00") - wire master_byteen : UInt<8> - master_byteen <= UInt<8>("h00") - wire buf_addr : UInt<32> - buf_addr <= UInt<32>("h00") - wire buf_size : UInt<2> - buf_size <= UInt<2>("h00") - wire buf_write : UInt<1> - buf_write <= UInt<1>("h00") - wire buf_byteen : UInt<8> - buf_byteen <= UInt<8>("h00") - wire buf_aligned : UInt<1> - buf_aligned <= UInt<1>("h00") - wire buf_data : UInt<64> - buf_data <= UInt<64>("h00") - wire buf_tag : UInt<1> - buf_tag <= UInt<1>("h00") - wire buf_tag_in : UInt<1> - buf_tag_in <= UInt<1>("h00") - wire buf_addr_in : UInt<32> - buf_addr_in <= UInt<32>("h00") - wire buf_byteen_in : UInt<8> - buf_byteen_in <= UInt<8>("h00") - wire buf_data_in : UInt<64> - buf_data_in <= UInt<64>("h00") - wire buf_write_in : UInt<1> - buf_write_in <= UInt<1>("h00") - wire buf_aligned_in : UInt<1> - buf_aligned_in <= UInt<1>("h00") - wire buf_size_in : UInt<3> - buf_size_in <= UInt<3>("h00") - wire buf_wr_en : UInt<1> - buf_wr_en <= UInt<1>("h00") - wire buf_data_wr_en : UInt<1> - buf_data_wr_en <= UInt<1>("h00") - wire slvbuf_error_en : UInt<1> - slvbuf_error_en <= UInt<1>("h00") - wire wr_cmd_vld : UInt<1> - wr_cmd_vld <= UInt<1>("h00") - wire cmd_done_rst : UInt<1> - cmd_done_rst <= UInt<1>("h00") - wire cmd_done : UInt<1> - cmd_done <= UInt<1>("h00") - wire cmd_doneQ : UInt<1> - cmd_doneQ <= UInt<1>("h00") - wire trxn_done : UInt<1> - trxn_done <= UInt<1>("h00") - wire buf_cmd_byte_ptr : UInt<3> - buf_cmd_byte_ptr <= UInt<3>("h00") - wire buf_cmd_byte_ptrQ : UInt<3> - buf_cmd_byte_ptrQ <= UInt<3>("h00") - wire buf_cmd_nxtbyte_ptr : UInt<3> - buf_cmd_nxtbyte_ptr <= UInt<3>("h00") - wire buf_cmd_byte_ptr_en : UInt<1> - buf_cmd_byte_ptr_en <= UInt<1>("h00") - wire found : UInt<1> - found <= UInt<1>("h00") - wire slave_valid_pre : UInt<1> - slave_valid_pre <= UInt<1>("h00") - wire ahb_hready_q : UInt<1> - ahb_hready_q <= UInt<1>("h00") - wire ahb_hresp_q : UInt<1> - ahb_hresp_q <= UInt<1>("h00") - wire ahb_htrans_q : UInt<2> - ahb_htrans_q <= UInt<2>("h00") - wire ahb_hwrite_q : UInt<1> - ahb_hwrite_q <= UInt<1>("h00") - wire ahb_hrdata_q : UInt<64> - ahb_hrdata_q <= UInt<64>("h00") - wire slvbuf_write : UInt<1> - slvbuf_write <= UInt<1>("h00") - wire slvbuf_error : UInt<1> - slvbuf_error <= UInt<1>("h00") - wire slvbuf_tag : UInt<1> - slvbuf_tag <= UInt<1>("h00") - wire slvbuf_error_in : UInt<1> - slvbuf_error_in <= UInt<1>("h00") - wire slvbuf_wr_en : UInt<1> - slvbuf_wr_en <= UInt<1>("h00") - wire bypass_en : UInt<1> - bypass_en <= UInt<1>("h00") - wire rd_bypass_idle : UInt<1> - rd_bypass_idle <= UInt<1>("h00") - wire last_addr_en : UInt<1> - last_addr_en <= UInt<1>("h00") - wire last_bus_addr : UInt<32> - last_bus_addr <= UInt<32>("h00") - wire buf_clken : UInt<1> - buf_clken <= UInt<1>("h00") - wire slvbuf_clken : UInt<1> - slvbuf_clken <= UInt<1>("h00") - wire ahbm_addr_clken : UInt<1> - ahbm_addr_clken <= UInt<1>("h00") - wire ahbm_data_clken : UInt<1> - ahbm_data_clken <= UInt<1>("h00") - wire buf_clk : Clock @[axi4_to_ahb.scala 118:21] - node _T_7 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 139:27] - wr_cmd_vld <= _T_7 @[axi4_to_ahb.scala 139:14] - node _T_8 = or(wr_cmd_vld, io.axi.ar.valid) @[axi4_to_ahb.scala 140:30] - master_valid <= _T_8 @[axi4_to_ahb.scala 140:16] - node _T_9 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 141:38] - node _T_10 = bits(wrbuf_tag, 0, 0) @[axi4_to_ahb.scala 141:51] - node _T_11 = bits(io.axi.ar.bits.id, 0, 0) @[axi4_to_ahb.scala 141:82] - node _T_12 = mux(_T_9, _T_10, _T_11) @[axi4_to_ahb.scala 141:20] - master_tag <= _T_12 @[axi4_to_ahb.scala 141:14] - node _T_13 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 142:38] - node _T_14 = mux(_T_13, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 142:20] - master_opc <= _T_14 @[axi4_to_ahb.scala 142:14] - node _T_15 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 143:39] - node _T_16 = bits(wrbuf_addr, 31, 0) @[axi4_to_ahb.scala 143:53] - node _T_17 = bits(io.axi.ar.bits.addr, 31, 0) @[axi4_to_ahb.scala 143:81] - node _T_18 = mux(_T_15, _T_16, _T_17) @[axi4_to_ahb.scala 143:21] - master_addr <= _T_18 @[axi4_to_ahb.scala 143:15] - node _T_19 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 144:39] - node _T_20 = bits(wrbuf_size, 2, 0) @[axi4_to_ahb.scala 144:53] - node _T_21 = bits(io.axi.ar.bits.size, 2, 0) @[axi4_to_ahb.scala 144:80] - node _T_22 = mux(_T_19, _T_20, _T_21) @[axi4_to_ahb.scala 144:21] - master_size <= _T_22 @[axi4_to_ahb.scala 144:15] - node _T_23 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 145:32] - master_byteen <= _T_23 @[axi4_to_ahb.scala 145:17] - node _T_24 = bits(wrbuf_data, 63, 0) @[axi4_to_ahb.scala 146:29] - master_wdata <= _T_24 @[axi4_to_ahb.scala 146:16] - node _T_25 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 149:33] - node _T_26 = bits(slave_opc, 3, 3) @[axi4_to_ahb.scala 149:58] - node _T_27 = and(_T_25, _T_26) @[axi4_to_ahb.scala 149:47] - io.axi.b.valid <= _T_27 @[axi4_to_ahb.scala 149:18] - node _T_28 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 150:38] - node _T_29 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 150:65] - node _T_30 = mux(_T_29, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 150:55] - node _T_31 = mux(_T_28, UInt<2>("h02"), _T_30) @[axi4_to_ahb.scala 150:28] - io.axi.b.bits.resp <= _T_31 @[axi4_to_ahb.scala 150:22] - node _T_32 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 151:32] - io.axi.b.bits.id <= _T_32 @[axi4_to_ahb.scala 151:20] - node _T_33 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 153:33] - node _T_34 = bits(slave_opc, 3, 2) @[axi4_to_ahb.scala 153:59] - node _T_35 = eq(_T_34, UInt<1>("h00")) @[axi4_to_ahb.scala 153:66] - node _T_36 = and(_T_33, _T_35) @[axi4_to_ahb.scala 153:47] - io.axi.r.valid <= _T_36 @[axi4_to_ahb.scala 153:18] - node _T_37 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 154:38] - node _T_38 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 154:65] - node _T_39 = mux(_T_38, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 154:55] - node _T_40 = mux(_T_37, UInt<2>("h02"), _T_39) @[axi4_to_ahb.scala 154:28] - io.axi.r.bits.resp <= _T_40 @[axi4_to_ahb.scala 154:22] - node _T_41 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 155:32] - io.axi.r.bits.id <= _T_41 @[axi4_to_ahb.scala 155:20] - node _T_42 = bits(slave_rdata, 63, 0) @[axi4_to_ahb.scala 156:36] - io.axi.r.bits.data <= _T_42 @[axi4_to_ahb.scala 156:22] - node _T_43 = and(io.axi.b.ready, io.axi.r.ready) @[axi4_to_ahb.scala 157:33] - slave_ready <= _T_43 @[axi4_to_ahb.scala 157:15] - node _T_44 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 160:57] - node _T_45 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 160:94] - node _T_46 = or(_T_44, _T_45) @[axi4_to_ahb.scala 160:76] - node _T_47 = and(io.bus_clk_en, _T_46) @[axi4_to_ahb.scala 160:37] - bus_write_clk_en <= _T_47 @[axi4_to_ahb.scala 160:20] - inst rvclkhdr of rvclkhdr_849 @[lib.scala 343:22] - rvclkhdr.clock <= clock - rvclkhdr.reset <= reset - rvclkhdr.io.clk <= clock @[lib.scala 344:17] - rvclkhdr.io.en <= io.bus_clk_en @[lib.scala 345:16] - rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - bus_clk <= rvclkhdr.io.l1clk @[axi4_to_ahb.scala 162:11] - node _T_48 = bits(bus_write_clk_en, 0, 0) @[axi4_to_ahb.scala 163:59] - inst rvclkhdr_1 of rvclkhdr_850 @[lib.scala 343:22] - rvclkhdr_1.clock <= clock - rvclkhdr_1.reset <= reset - rvclkhdr_1.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_1.io.en <= _T_48 @[lib.scala 345:16] - rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - bus_write_clk <= rvclkhdr_1.io.l1clk @[axi4_to_ahb.scala 163:17] - node _T_49 = eq(UInt<3>("h00"), buf_state) @[Conditional.scala 37:30] - when _T_49 : @[Conditional.scala 40:58] - master_ready <= UInt<1>("h01") @[axi4_to_ahb.scala 167:20] - node _T_50 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 168:34] - node _T_51 = eq(_T_50, UInt<1>("h01")) @[axi4_to_ahb.scala 168:41] - buf_write_in <= _T_51 @[axi4_to_ahb.scala 168:20] - node _T_52 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 169:46] - node _T_53 = mux(_T_52, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 169:26] - buf_nxtstate <= _T_53 @[axi4_to_ahb.scala 169:20] - node _T_54 = and(master_valid, UInt<1>("h01")) @[axi4_to_ahb.scala 170:36] - buf_state_en <= _T_54 @[axi4_to_ahb.scala 170:20] - buf_wr_en <= buf_state_en @[axi4_to_ahb.scala 171:17] - node _T_55 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 172:54] - node _T_56 = and(buf_state_en, _T_55) @[axi4_to_ahb.scala 172:38] - buf_data_wr_en <= _T_56 @[axi4_to_ahb.scala 172:22] - buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 173:27] - node _T_57 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 175:50] - node _T_58 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 175:94] - node _T_59 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_60 = tail(_T_59, 1) @[axi4_to_ahb.scala 135:52] - node _T_61 = mux(UInt<1>("h00"), _T_60, UInt<3>("h00")) @[axi4_to_ahb.scala 135:24] - node _T_62 = bits(_T_58, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_63 = geq(UInt<1>("h00"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_64 = and(_T_62, _T_63) @[axi4_to_ahb.scala 136:48] - node _T_65 = bits(_T_58, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_66 = geq(UInt<1>("h01"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_67 = and(_T_65, _T_66) @[axi4_to_ahb.scala 136:48] - node _T_68 = bits(_T_58, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_69 = geq(UInt<2>("h02"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_70 = and(_T_68, _T_69) @[axi4_to_ahb.scala 136:48] - node _T_71 = bits(_T_58, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_72 = geq(UInt<2>("h03"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_73 = and(_T_71, _T_72) @[axi4_to_ahb.scala 136:48] - node _T_74 = bits(_T_58, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_75 = geq(UInt<3>("h04"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_76 = and(_T_74, _T_75) @[axi4_to_ahb.scala 136:48] - node _T_77 = bits(_T_58, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_78 = geq(UInt<3>("h05"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_79 = and(_T_77, _T_78) @[axi4_to_ahb.scala 136:48] - node _T_80 = bits(_T_58, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_81 = geq(UInt<3>("h06"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_82 = and(_T_80, _T_81) @[axi4_to_ahb.scala 136:48] - node _T_83 = bits(_T_58, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_84 = geq(UInt<3>("h07"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_85 = and(_T_83, _T_84) @[axi4_to_ahb.scala 136:48] - node _T_86 = mux(_T_85, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_87 = mux(_T_82, UInt<3>("h06"), _T_86) @[Mux.scala 98:16] - node _T_88 = mux(_T_79, UInt<3>("h05"), _T_87) @[Mux.scala 98:16] - node _T_89 = mux(_T_76, UInt<3>("h04"), _T_88) @[Mux.scala 98:16] - node _T_90 = mux(_T_73, UInt<2>("h03"), _T_89) @[Mux.scala 98:16] - node _T_91 = mux(_T_70, UInt<2>("h02"), _T_90) @[Mux.scala 98:16] - node _T_92 = mux(_T_67, UInt<1>("h01"), _T_91) @[Mux.scala 98:16] - node _T_93 = mux(_T_64, UInt<1>("h00"), _T_92) @[Mux.scala 98:16] - node _T_94 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 175:124] - node _T_95 = mux(_T_57, _T_93, _T_94) @[axi4_to_ahb.scala 175:30] - buf_cmd_byte_ptr <= _T_95 @[axi4_to_ahb.scala 175:24] - bypass_en <= buf_state_en @[axi4_to_ahb.scala 176:17] - node _T_96 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 177:51] - node _T_97 = and(bypass_en, _T_96) @[axi4_to_ahb.scala 177:35] - rd_bypass_idle <= _T_97 @[axi4_to_ahb.scala 177:22] - node _T_98 = bits(bypass_en, 0, 0) @[Bitwise.scala 72:15] - node _T_99 = mux(_T_98, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_100 = and(_T_99, UInt<2>("h02")) @[axi4_to_ahb.scala 178:49] - io.ahb.out.htrans <= _T_100 @[axi4_to_ahb.scala 178:25] - skip @[Conditional.scala 40:58] - else : @[Conditional.scala 39:67] - node _T_101 = eq(UInt<3>("h01"), buf_state) @[Conditional.scala 37:30] - when _T_101 : @[Conditional.scala 39:67] - node _T_102 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 182:54] - node _T_103 = eq(_T_102, UInt<1>("h00")) @[axi4_to_ahb.scala 182:61] - node _T_104 = and(master_valid, _T_103) @[axi4_to_ahb.scala 182:41] - node _T_105 = bits(_T_104, 0, 0) @[axi4_to_ahb.scala 182:82] - node _T_106 = mux(_T_105, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 182:26] - buf_nxtstate <= _T_106 @[axi4_to_ahb.scala 182:20] - node _T_107 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 183:51] - node _T_108 = neq(_T_107, UInt<1>("h00")) @[axi4_to_ahb.scala 183:58] - node _T_109 = and(ahb_hready_q, _T_108) @[axi4_to_ahb.scala 183:36] - node _T_110 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 183:72] - node _T_111 = and(_T_109, _T_110) @[axi4_to_ahb.scala 183:70] - buf_state_en <= _T_111 @[axi4_to_ahb.scala 183:20] - node _T_112 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 184:34] - node _T_113 = and(buf_state_en, _T_112) @[axi4_to_ahb.scala 184:32] - cmd_done <= _T_113 @[axi4_to_ahb.scala 184:16] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 185:20] - node _T_114 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 186:52] - node _T_115 = neq(_T_114, UInt<1>("h00")) @[axi4_to_ahb.scala 186:59] - node _T_116 = and(ahb_hready_q, _T_115) @[axi4_to_ahb.scala 186:37] - node _T_117 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 186:73] - node _T_118 = and(_T_116, _T_117) @[axi4_to_ahb.scala 186:71] - node _T_119 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 186:122] - node _T_120 = eq(_T_119, UInt<1>("h00")) @[axi4_to_ahb.scala 186:129] - node _T_121 = and(master_valid, _T_120) @[axi4_to_ahb.scala 186:109] - node _T_122 = bits(_T_121, 0, 0) @[axi4_to_ahb.scala 186:150] - node _T_123 = mux(_T_122, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 186:94] - node _T_124 = eq(_T_123, UInt<3>("h06")) @[axi4_to_ahb.scala 186:174] - node _T_125 = and(_T_118, _T_124) @[axi4_to_ahb.scala 186:88] - master_ready <= _T_125 @[axi4_to_ahb.scala 186:20] - buf_wr_en <= master_ready @[axi4_to_ahb.scala 187:17] - node _T_126 = and(master_ready, master_valid) @[axi4_to_ahb.scala 188:33] - bypass_en <= _T_126 @[axi4_to_ahb.scala 188:17] - node _T_127 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 189:47] - node _T_128 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 189:62] - node _T_129 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 189:78] - node _T_130 = mux(_T_127, _T_128, _T_129) @[axi4_to_ahb.scala 189:30] - buf_cmd_byte_ptr <= _T_130 @[axi4_to_ahb.scala 189:24] - node _T_131 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 190:48] - node _T_132 = or(_T_131, bypass_en) @[axi4_to_ahb.scala 190:62] - node _T_133 = bits(_T_132, 0, 0) @[Bitwise.scala 72:15] - node _T_134 = mux(_T_133, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_135 = and(UInt<2>("h02"), _T_134) @[axi4_to_ahb.scala 190:36] - io.ahb.out.htrans <= _T_135 @[axi4_to_ahb.scala 190:25] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_136 = eq(UInt<3>("h06"), buf_state) @[Conditional.scala 37:30] - when _T_136 : @[Conditional.scala 39:67] - node _T_137 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 194:39] - node _T_138 = and(ahb_hready_q, _T_137) @[axi4_to_ahb.scala 194:37] - node _T_139 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 194:82] - node _T_140 = eq(_T_139, UInt<1>("h01")) @[axi4_to_ahb.scala 194:89] - node _T_141 = and(master_valid, _T_140) @[axi4_to_ahb.scala 194:70] - node _T_142 = not(_T_141) @[axi4_to_ahb.scala 194:55] - node _T_143 = and(_T_138, _T_142) @[axi4_to_ahb.scala 194:53] - master_ready <= _T_143 @[axi4_to_ahb.scala 194:20] - node _T_144 = and(master_valid, master_ready) @[axi4_to_ahb.scala 195:34] - node _T_145 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 195:62] - node _T_146 = eq(_T_145, UInt<1>("h00")) @[axi4_to_ahb.scala 195:69] - node _T_147 = and(_T_144, _T_146) @[axi4_to_ahb.scala 195:49] - buf_wr_en <= _T_147 @[axi4_to_ahb.scala 195:17] - node _T_148 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 196:45] - node _T_149 = and(master_valid, master_ready) @[axi4_to_ahb.scala 196:82] - node _T_150 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 196:110] - node _T_151 = eq(_T_150, UInt<1>("h00")) @[axi4_to_ahb.scala 196:117] - node _T_152 = and(_T_149, _T_151) @[axi4_to_ahb.scala 196:97] - node _T_153 = bits(_T_152, 0, 0) @[axi4_to_ahb.scala 196:138] - node _T_154 = mux(_T_153, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 196:67] - node _T_155 = mux(_T_148, UInt<3>("h07"), _T_154) @[axi4_to_ahb.scala 196:26] - buf_nxtstate <= _T_155 @[axi4_to_ahb.scala 196:20] - node _T_156 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 197:37] - buf_state_en <= _T_156 @[axi4_to_ahb.scala 197:20] - buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 198:22] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 199:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 200:23] - node _T_157 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 201:41] - node _T_158 = and(buf_state_en, _T_157) @[axi4_to_ahb.scala 201:39] - slave_valid_pre <= _T_158 @[axi4_to_ahb.scala 201:23] - node _T_159 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 202:34] - node _T_160 = and(buf_state_en, _T_159) @[axi4_to_ahb.scala 202:32] - cmd_done <= _T_160 @[axi4_to_ahb.scala 202:16] - node _T_161 = and(master_ready, master_valid) @[axi4_to_ahb.scala 203:33] - node _T_162 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 203:64] - node _T_163 = and(_T_161, _T_162) @[axi4_to_ahb.scala 203:48] - node _T_164 = and(_T_163, buf_state_en) @[axi4_to_ahb.scala 203:79] - bypass_en <= _T_164 @[axi4_to_ahb.scala 203:17] - node _T_165 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 204:47] - node _T_166 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 204:62] - node _T_167 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 204:78] - node _T_168 = mux(_T_165, _T_166, _T_167) @[axi4_to_ahb.scala 204:30] - buf_cmd_byte_ptr <= _T_168 @[axi4_to_ahb.scala 204:24] - node _T_169 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 205:63] - node _T_170 = and(_T_169, buf_state_en) @[axi4_to_ahb.scala 205:78] - node _T_171 = eq(_T_170, UInt<1>("h00")) @[axi4_to_ahb.scala 205:47] - node _T_172 = bits(_T_171, 0, 0) @[Bitwise.scala 72:15] - node _T_173 = mux(_T_172, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_174 = and(UInt<2>("h02"), _T_173) @[axi4_to_ahb.scala 205:36] - io.ahb.out.htrans <= _T_174 @[axi4_to_ahb.scala 205:25] - slvbuf_wr_en <= buf_wr_en @[axi4_to_ahb.scala 206:20] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_175 = eq(UInt<3>("h07"), buf_state) @[Conditional.scala 37:30] - when _T_175 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h03") @[axi4_to_ahb.scala 210:20] - node _T_176 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 211:51] - node _T_177 = neq(_T_176, UInt<1>("h00")) @[axi4_to_ahb.scala 211:58] - node _T_178 = and(ahb_hready_q, _T_177) @[axi4_to_ahb.scala 211:36] - node _T_179 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 211:72] - node _T_180 = and(_T_178, _T_179) @[axi4_to_ahb.scala 211:70] - buf_state_en <= _T_180 @[axi4_to_ahb.scala 211:20] - slave_valid_pre <= buf_state_en @[axi4_to_ahb.scala 212:23] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 213:20] - node _T_181 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 214:35] - buf_cmd_byte_ptr <= _T_181 @[axi4_to_ahb.scala 214:24] - node _T_182 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 215:51] - node _T_183 = bits(_T_182, 0, 0) @[Bitwise.scala 72:15] - node _T_184 = mux(_T_183, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_185 = and(UInt<2>("h02"), _T_184) @[axi4_to_ahb.scala 215:41] - io.ahb.out.htrans <= _T_185 @[axi4_to_ahb.scala 215:25] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_186 = eq(UInt<3>("h03"), buf_state) @[Conditional.scala 37:30] - when _T_186 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h05") @[axi4_to_ahb.scala 219:20] - node _T_187 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 220:37] - buf_state_en <= _T_187 @[axi4_to_ahb.scala 220:20] - buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 221:22] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 222:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 223:23] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 224:20] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_188 = eq(UInt<3>("h02"), buf_state) @[Conditional.scala 37:30] - when _T_188 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h04") @[axi4_to_ahb.scala 228:20] - node _T_189 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 229:33] - node _T_190 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 229:63] - node _T_191 = neq(_T_190, UInt<1>("h00")) @[axi4_to_ahb.scala 229:70] - node _T_192 = and(_T_189, _T_191) @[axi4_to_ahb.scala 229:48] - trxn_done <= _T_192 @[axi4_to_ahb.scala 229:17] - buf_state_en <= trxn_done @[axi4_to_ahb.scala 230:20] - buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 231:27] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 232:20] - node _T_193 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 233:47] - node _T_194 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 233:85] - node _T_195 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 233:103] - node _T_196 = add(_T_194, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_197 = tail(_T_196, 1) @[axi4_to_ahb.scala 135:52] - node _T_198 = mux(UInt<1>("h01"), _T_197, _T_194) @[axi4_to_ahb.scala 135:24] - node _T_199 = bits(_T_195, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_200 = geq(UInt<1>("h00"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_201 = and(_T_199, _T_200) @[axi4_to_ahb.scala 136:48] - node _T_202 = bits(_T_195, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_203 = geq(UInt<1>("h01"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_204 = and(_T_202, _T_203) @[axi4_to_ahb.scala 136:48] - node _T_205 = bits(_T_195, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_206 = geq(UInt<2>("h02"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_207 = and(_T_205, _T_206) @[axi4_to_ahb.scala 136:48] - node _T_208 = bits(_T_195, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_209 = geq(UInt<2>("h03"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_210 = and(_T_208, _T_209) @[axi4_to_ahb.scala 136:48] - node _T_211 = bits(_T_195, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_212 = geq(UInt<3>("h04"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_213 = and(_T_211, _T_212) @[axi4_to_ahb.scala 136:48] - node _T_214 = bits(_T_195, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_215 = geq(UInt<3>("h05"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_216 = and(_T_214, _T_215) @[axi4_to_ahb.scala 136:48] - node _T_217 = bits(_T_195, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_218 = geq(UInt<3>("h06"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_219 = and(_T_217, _T_218) @[axi4_to_ahb.scala 136:48] - node _T_220 = bits(_T_195, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_221 = geq(UInt<3>("h07"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_222 = and(_T_220, _T_221) @[axi4_to_ahb.scala 136:48] - node _T_223 = mux(_T_222, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_224 = mux(_T_219, UInt<3>("h06"), _T_223) @[Mux.scala 98:16] - node _T_225 = mux(_T_216, UInt<3>("h05"), _T_224) @[Mux.scala 98:16] - node _T_226 = mux(_T_213, UInt<3>("h04"), _T_225) @[Mux.scala 98:16] - node _T_227 = mux(_T_210, UInt<2>("h03"), _T_226) @[Mux.scala 98:16] - node _T_228 = mux(_T_207, UInt<2>("h02"), _T_227) @[Mux.scala 98:16] - node _T_229 = mux(_T_204, UInt<1>("h01"), _T_228) @[Mux.scala 98:16] - node _T_230 = mux(_T_201, UInt<1>("h00"), _T_229) @[Mux.scala 98:16] - node _T_231 = mux(_T_193, _T_230, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 233:30] - buf_cmd_byte_ptr <= _T_231 @[axi4_to_ahb.scala 233:24] - node _T_232 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 234:65] - node _T_233 = or(buf_aligned, _T_232) @[axi4_to_ahb.scala 234:44] - node _T_234 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 234:127] - node _T_235 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 234:145] - node _T_236 = add(_T_234, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_237 = tail(_T_236, 1) @[axi4_to_ahb.scala 135:52] - node _T_238 = mux(UInt<1>("h01"), _T_237, _T_234) @[axi4_to_ahb.scala 135:24] - node _T_239 = bits(_T_235, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_240 = geq(UInt<1>("h00"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_241 = and(_T_239, _T_240) @[axi4_to_ahb.scala 136:48] - node _T_242 = bits(_T_235, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_243 = geq(UInt<1>("h01"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_244 = and(_T_242, _T_243) @[axi4_to_ahb.scala 136:48] - node _T_245 = bits(_T_235, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_246 = geq(UInt<2>("h02"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_247 = and(_T_245, _T_246) @[axi4_to_ahb.scala 136:48] - node _T_248 = bits(_T_235, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_249 = geq(UInt<2>("h03"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_250 = and(_T_248, _T_249) @[axi4_to_ahb.scala 136:48] - node _T_251 = bits(_T_235, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_252 = geq(UInt<3>("h04"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_253 = and(_T_251, _T_252) @[axi4_to_ahb.scala 136:48] - node _T_254 = bits(_T_235, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_255 = geq(UInt<3>("h05"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_256 = and(_T_254, _T_255) @[axi4_to_ahb.scala 136:48] - node _T_257 = bits(_T_235, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_258 = geq(UInt<3>("h06"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_259 = and(_T_257, _T_258) @[axi4_to_ahb.scala 136:48] - node _T_260 = bits(_T_235, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_261 = geq(UInt<3>("h07"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_262 = and(_T_260, _T_261) @[axi4_to_ahb.scala 136:48] - node _T_263 = mux(_T_262, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_264 = mux(_T_259, UInt<3>("h06"), _T_263) @[Mux.scala 98:16] - node _T_265 = mux(_T_256, UInt<3>("h05"), _T_264) @[Mux.scala 98:16] - node _T_266 = mux(_T_253, UInt<3>("h04"), _T_265) @[Mux.scala 98:16] - node _T_267 = mux(_T_250, UInt<2>("h03"), _T_266) @[Mux.scala 98:16] - node _T_268 = mux(_T_247, UInt<2>("h02"), _T_267) @[Mux.scala 98:16] - node _T_269 = mux(_T_244, UInt<1>("h01"), _T_268) @[Mux.scala 98:16] - node _T_270 = mux(_T_241, UInt<1>("h00"), _T_269) @[Mux.scala 98:16] - node _T_271 = dshr(buf_byteen, _T_270) @[axi4_to_ahb.scala 234:92] - node _T_272 = bits(_T_271, 0, 0) @[axi4_to_ahb.scala 234:92] - node _T_273 = eq(_T_272, UInt<1>("h00")) @[axi4_to_ahb.scala 234:163] - node _T_274 = or(_T_233, _T_273) @[axi4_to_ahb.scala 234:79] - node _T_275 = and(trxn_done, _T_274) @[axi4_to_ahb.scala 234:29] - cmd_done <= _T_275 @[axi4_to_ahb.scala 234:16] - node _T_276 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 235:47] - node _T_277 = eq(_T_276, UInt<1>("h00")) @[axi4_to_ahb.scala 235:36] - node _T_278 = bits(_T_277, 0, 0) @[Bitwise.scala 72:15] - node _T_279 = mux(_T_278, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_280 = and(_T_279, UInt<2>("h02")) @[axi4_to_ahb.scala 235:61] - io.ahb.out.htrans <= _T_280 @[axi4_to_ahb.scala 235:25] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_281 = eq(UInt<3>("h04"), buf_state) @[Conditional.scala 37:30] - when _T_281 : @[Conditional.scala 39:67] - node _T_282 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 239:34] - node _T_283 = or(_T_282, ahb_hresp_q) @[axi4_to_ahb.scala 239:50] - buf_state_en <= _T_283 @[axi4_to_ahb.scala 239:20] - node _T_284 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 240:38] - node _T_285 = and(buf_state_en, _T_284) @[axi4_to_ahb.scala 240:36] - node _T_286 = and(_T_285, slave_ready) @[axi4_to_ahb.scala 240:51] - master_ready <= _T_286 @[axi4_to_ahb.scala 240:20] - node _T_287 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 241:42] - node _T_288 = or(ahb_hresp_q, _T_287) @[axi4_to_ahb.scala 241:40] - node _T_289 = and(master_valid, master_valid) @[axi4_to_ahb.scala 241:80] - node _T_290 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 241:111] - node _T_291 = eq(_T_290, UInt<1>("h01")) @[axi4_to_ahb.scala 241:117] - node _T_292 = bits(_T_291, 0, 0) @[axi4_to_ahb.scala 241:132] - node _T_293 = mux(_T_292, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 241:99] - node _T_294 = mux(_T_289, _T_293, UInt<3>("h00")) @[axi4_to_ahb.scala 241:65] - node _T_295 = mux(_T_288, UInt<3>("h05"), _T_294) @[axi4_to_ahb.scala 241:26] - buf_nxtstate <= _T_295 @[axi4_to_ahb.scala 241:20] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 242:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 243:23] - node _T_296 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 244:33] - node _T_297 = eq(_T_296, UInt<1>("h01")) @[axi4_to_ahb.scala 244:39] - buf_write_in <= _T_297 @[axi4_to_ahb.scala 244:20] - node _T_298 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 245:50] - node _T_299 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 245:78] - node _T_300 = or(_T_298, _T_299) @[axi4_to_ahb.scala 245:62] - node _T_301 = and(buf_state_en, _T_300) @[axi4_to_ahb.scala 245:33] - buf_wr_en <= _T_301 @[axi4_to_ahb.scala 245:17] - buf_data_wr_en <= buf_wr_en @[axi4_to_ahb.scala 246:22] - node _T_302 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 247:65] - node _T_303 = neq(_T_302, UInt<1>("h00")) @[axi4_to_ahb.scala 247:71] - node _T_304 = and(ahb_hready_q, _T_303) @[axi4_to_ahb.scala 247:50] - node _T_305 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 248:29] - node _T_306 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 248:85] - node _T_307 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 248:101] - node _T_308 = add(_T_306, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_309 = tail(_T_308, 1) @[axi4_to_ahb.scala 135:52] - node _T_310 = mux(UInt<1>("h01"), _T_309, _T_306) @[axi4_to_ahb.scala 135:24] - node _T_311 = bits(_T_307, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_312 = geq(UInt<1>("h00"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_313 = and(_T_311, _T_312) @[axi4_to_ahb.scala 136:48] - node _T_314 = bits(_T_307, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_315 = geq(UInt<1>("h01"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_316 = and(_T_314, _T_315) @[axi4_to_ahb.scala 136:48] - node _T_317 = bits(_T_307, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_318 = geq(UInt<2>("h02"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_319 = and(_T_317, _T_318) @[axi4_to_ahb.scala 136:48] - node _T_320 = bits(_T_307, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_321 = geq(UInt<2>("h03"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_322 = and(_T_320, _T_321) @[axi4_to_ahb.scala 136:48] - node _T_323 = bits(_T_307, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_324 = geq(UInt<3>("h04"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_325 = and(_T_323, _T_324) @[axi4_to_ahb.scala 136:48] - node _T_326 = bits(_T_307, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_327 = geq(UInt<3>("h05"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_328 = and(_T_326, _T_327) @[axi4_to_ahb.scala 136:48] - node _T_329 = bits(_T_307, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_330 = geq(UInt<3>("h06"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_331 = and(_T_329, _T_330) @[axi4_to_ahb.scala 136:48] - node _T_332 = bits(_T_307, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_333 = geq(UInt<3>("h07"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_334 = and(_T_332, _T_333) @[axi4_to_ahb.scala 136:48] - node _T_335 = mux(_T_334, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_336 = mux(_T_331, UInt<3>("h06"), _T_335) @[Mux.scala 98:16] - node _T_337 = mux(_T_328, UInt<3>("h05"), _T_336) @[Mux.scala 98:16] - node _T_338 = mux(_T_325, UInt<3>("h04"), _T_337) @[Mux.scala 98:16] - node _T_339 = mux(_T_322, UInt<2>("h03"), _T_338) @[Mux.scala 98:16] - node _T_340 = mux(_T_319, UInt<2>("h02"), _T_339) @[Mux.scala 98:16] - node _T_341 = mux(_T_316, UInt<1>("h01"), _T_340) @[Mux.scala 98:16] - node _T_342 = mux(_T_313, UInt<1>("h00"), _T_341) @[Mux.scala 98:16] - node _T_343 = dshr(buf_byteen, _T_342) @[axi4_to_ahb.scala 248:51] - node _T_344 = bits(_T_343, 0, 0) @[axi4_to_ahb.scala 248:51] - node _T_345 = eq(_T_344, UInt<1>("h00")) @[axi4_to_ahb.scala 248:116] - node _T_346 = or(_T_305, _T_345) @[axi4_to_ahb.scala 248:38] - node _T_347 = and(_T_304, _T_346) @[axi4_to_ahb.scala 247:80] - node _T_348 = or(ahb_hresp_q, _T_347) @[axi4_to_ahb.scala 247:34] - cmd_done <= _T_348 @[axi4_to_ahb.scala 247:16] - node _T_349 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 249:33] - node _T_350 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 249:64] - node _T_351 = and(_T_349, _T_350) @[axi4_to_ahb.scala 249:48] - bypass_en <= _T_351 @[axi4_to_ahb.scala 249:17] - node _T_352 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 250:48] - node _T_353 = eq(_T_352, UInt<1>("h00")) @[axi4_to_ahb.scala 250:37] - node _T_354 = or(_T_353, bypass_en) @[axi4_to_ahb.scala 250:61] - node _T_355 = bits(_T_354, 0, 0) @[Bitwise.scala 72:15] - node _T_356 = mux(_T_355, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_357 = and(_T_356, UInt<2>("h02")) @[axi4_to_ahb.scala 250:75] - io.ahb.out.htrans <= _T_357 @[axi4_to_ahb.scala 250:25] - node _T_358 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 251:55] - node _T_359 = and(buf_state_en, _T_358) @[axi4_to_ahb.scala 251:39] - slave_valid_pre <= _T_359 @[axi4_to_ahb.scala 251:23] - node _T_360 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 252:33] - node _T_361 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 252:63] - node _T_362 = neq(_T_361, UInt<1>("h00")) @[axi4_to_ahb.scala 252:69] - node _T_363 = and(_T_360, _T_362) @[axi4_to_ahb.scala 252:48] - trxn_done <= _T_363 @[axi4_to_ahb.scala 252:17] - node _T_364 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 253:40] - buf_cmd_byte_ptr_en <= _T_364 @[axi4_to_ahb.scala 253:27] - node _T_365 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 254:79] - node _T_366 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_367 = tail(_T_366, 1) @[axi4_to_ahb.scala 135:52] - node _T_368 = mux(UInt<1>("h00"), _T_367, UInt<3>("h00")) @[axi4_to_ahb.scala 135:24] - node _T_369 = bits(_T_365, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_370 = geq(UInt<1>("h00"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_371 = and(_T_369, _T_370) @[axi4_to_ahb.scala 136:48] - node _T_372 = bits(_T_365, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_373 = geq(UInt<1>("h01"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_374 = and(_T_372, _T_373) @[axi4_to_ahb.scala 136:48] - node _T_375 = bits(_T_365, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_376 = geq(UInt<2>("h02"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_377 = and(_T_375, _T_376) @[axi4_to_ahb.scala 136:48] - node _T_378 = bits(_T_365, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_379 = geq(UInt<2>("h03"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_380 = and(_T_378, _T_379) @[axi4_to_ahb.scala 136:48] - node _T_381 = bits(_T_365, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_382 = geq(UInt<3>("h04"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_383 = and(_T_381, _T_382) @[axi4_to_ahb.scala 136:48] - node _T_384 = bits(_T_365, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_385 = geq(UInt<3>("h05"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_386 = and(_T_384, _T_385) @[axi4_to_ahb.scala 136:48] - node _T_387 = bits(_T_365, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_388 = geq(UInt<3>("h06"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_389 = and(_T_387, _T_388) @[axi4_to_ahb.scala 136:48] - node _T_390 = bits(_T_365, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_391 = geq(UInt<3>("h07"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_392 = and(_T_390, _T_391) @[axi4_to_ahb.scala 136:48] - node _T_393 = mux(_T_392, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_394 = mux(_T_389, UInt<3>("h06"), _T_393) @[Mux.scala 98:16] - node _T_395 = mux(_T_386, UInt<3>("h05"), _T_394) @[Mux.scala 98:16] - node _T_396 = mux(_T_383, UInt<3>("h04"), _T_395) @[Mux.scala 98:16] - node _T_397 = mux(_T_380, UInt<2>("h03"), _T_396) @[Mux.scala 98:16] - node _T_398 = mux(_T_377, UInt<2>("h02"), _T_397) @[Mux.scala 98:16] - node _T_399 = mux(_T_374, UInt<1>("h01"), _T_398) @[Mux.scala 98:16] - node _T_400 = mux(_T_371, UInt<1>("h00"), _T_399) @[Mux.scala 98:16] - node _T_401 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 254:141] - node _T_402 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 254:157] - node _T_403 = add(_T_401, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_404 = tail(_T_403, 1) @[axi4_to_ahb.scala 135:52] - node _T_405 = mux(UInt<1>("h01"), _T_404, _T_401) @[axi4_to_ahb.scala 135:24] - node _T_406 = bits(_T_402, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_407 = geq(UInt<1>("h00"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_408 = and(_T_406, _T_407) @[axi4_to_ahb.scala 136:48] - node _T_409 = bits(_T_402, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_410 = geq(UInt<1>("h01"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_411 = and(_T_409, _T_410) @[axi4_to_ahb.scala 136:48] - node _T_412 = bits(_T_402, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_413 = geq(UInt<2>("h02"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_414 = and(_T_412, _T_413) @[axi4_to_ahb.scala 136:48] - node _T_415 = bits(_T_402, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_416 = geq(UInt<2>("h03"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_417 = and(_T_415, _T_416) @[axi4_to_ahb.scala 136:48] - node _T_418 = bits(_T_402, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_419 = geq(UInt<3>("h04"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_420 = and(_T_418, _T_419) @[axi4_to_ahb.scala 136:48] - node _T_421 = bits(_T_402, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_422 = geq(UInt<3>("h05"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_423 = and(_T_421, _T_422) @[axi4_to_ahb.scala 136:48] - node _T_424 = bits(_T_402, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_425 = geq(UInt<3>("h06"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_426 = and(_T_424, _T_425) @[axi4_to_ahb.scala 136:48] - node _T_427 = bits(_T_402, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_428 = geq(UInt<3>("h07"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_429 = and(_T_427, _T_428) @[axi4_to_ahb.scala 136:48] - node _T_430 = mux(_T_429, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_431 = mux(_T_426, UInt<3>("h06"), _T_430) @[Mux.scala 98:16] - node _T_432 = mux(_T_423, UInt<3>("h05"), _T_431) @[Mux.scala 98:16] - node _T_433 = mux(_T_420, UInt<3>("h04"), _T_432) @[Mux.scala 98:16] - node _T_434 = mux(_T_417, UInt<2>("h03"), _T_433) @[Mux.scala 98:16] - node _T_435 = mux(_T_414, UInt<2>("h02"), _T_434) @[Mux.scala 98:16] - node _T_436 = mux(_T_411, UInt<1>("h01"), _T_435) @[Mux.scala 98:16] - node _T_437 = mux(_T_408, UInt<1>("h00"), _T_436) @[Mux.scala 98:16] - node _T_438 = mux(trxn_done, _T_437, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 254:97] - node _T_439 = mux(bypass_en, _T_400, _T_438) @[axi4_to_ahb.scala 254:30] - buf_cmd_byte_ptr <= _T_439 @[axi4_to_ahb.scala 254:24] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_440 = eq(UInt<3>("h05"), buf_state) @[Conditional.scala 37:30] - when _T_440 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 257:20] - buf_state_en <= slave_ready @[axi4_to_ahb.scala 258:20] - slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 259:23] - slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 260:23] - skip @[Conditional.scala 39:67] - cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 264:16] - node _T_441 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 265:33] - node _T_442 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 265:73] - node _T_443 = eq(_T_442, UInt<1>("h01")) @[axi4_to_ahb.scala 265:80] - node _T_444 = and(buf_aligned_in, _T_443) @[axi4_to_ahb.scala 265:60] - node _T_445 = bits(_T_444, 0, 0) @[axi4_to_ahb.scala 265:100] - node _T_446 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 265:132] - node _T_447 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 127:50] - node _T_448 = eq(_T_447, UInt<8>("h0ff")) @[axi4_to_ahb.scala 127:57] - node _T_449 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 127:81] - node _T_450 = eq(_T_449, UInt<8>("h0f")) @[axi4_to_ahb.scala 127:88] - node _T_451 = or(_T_448, _T_450) @[axi4_to_ahb.scala 127:70] - node _T_452 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 127:117] - node _T_453 = eq(_T_452, UInt<8>("h03")) @[axi4_to_ahb.scala 127:124] - node _T_454 = or(_T_451, _T_453) @[axi4_to_ahb.scala 127:106] - node _T_455 = bits(_T_454, 0, 0) @[Bitwise.scala 72:15] - node _T_456 = mux(_T_455, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_457 = and(UInt<3>("h00"), _T_456) @[axi4_to_ahb.scala 127:29] - node _T_458 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 128:35] - node _T_459 = eq(_T_458, UInt<8>("h0c")) @[axi4_to_ahb.scala 128:42] - node _T_460 = bits(_T_459, 0, 0) @[Bitwise.scala 72:15] - node _T_461 = mux(_T_460, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_462 = and(UInt<2>("h02"), _T_461) @[axi4_to_ahb.scala 128:15] - node _T_463 = or(_T_457, _T_462) @[axi4_to_ahb.scala 127:146] - node _T_464 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 129:36] - node _T_465 = eq(_T_464, UInt<8>("h0f0")) @[axi4_to_ahb.scala 129:43] - node _T_466 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 129:67] - node _T_467 = eq(_T_466, UInt<8>("h03")) @[axi4_to_ahb.scala 129:74] - node _T_468 = or(_T_465, _T_467) @[axi4_to_ahb.scala 129:56] - node _T_469 = bits(_T_468, 0, 0) @[Bitwise.scala 72:15] - node _T_470 = mux(_T_469, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_471 = and(UInt<3>("h04"), _T_470) @[axi4_to_ahb.scala 129:15] - node _T_472 = or(_T_463, _T_471) @[axi4_to_ahb.scala 128:63] - node _T_473 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 130:35] - node _T_474 = eq(_T_473, UInt<8>("h0c0")) @[axi4_to_ahb.scala 130:42] - node _T_475 = bits(_T_474, 0, 0) @[Bitwise.scala 72:15] - node _T_476 = mux(_T_475, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_477 = and(UInt<3>("h06"), _T_476) @[axi4_to_ahb.scala 130:15] - node _T_478 = or(_T_472, _T_477) @[axi4_to_ahb.scala 129:96] - node _T_479 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 131:33] - node _T_480 = eq(_T_479, UInt<8>("h0c0")) @[axi4_to_ahb.scala 131:40] - node _T_481 = bits(_T_480, 0, 0) @[Bitwise.scala 72:15] - node _T_482 = mux(_T_481, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_483 = and(UInt<3>("h06"), _T_482) @[axi4_to_ahb.scala 131:13] - node _T_484 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 265:152] - node _T_485 = mux(_T_445, _T_478, _T_484) @[axi4_to_ahb.scala 265:43] - node _T_486 = cat(_T_441, _T_485) @[Cat.scala 29:58] - buf_addr_in <= _T_486 @[axi4_to_ahb.scala 265:15] - node _T_487 = bits(master_tag, 0, 0) @[axi4_to_ahb.scala 266:27] - buf_tag_in <= _T_487 @[axi4_to_ahb.scala 266:14] - node _T_488 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 267:32] - buf_byteen_in <= _T_488 @[axi4_to_ahb.scala 267:17] - node _T_489 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 268:33] - node _T_490 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 268:59] - node _T_491 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 268:80] - node _T_492 = mux(_T_489, _T_490, _T_491) @[axi4_to_ahb.scala 268:21] - buf_data_in <= _T_492 @[axi4_to_ahb.scala 268:15] - node _T_493 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 269:52] - node _T_494 = eq(_T_493, UInt<2>("h03")) @[axi4_to_ahb.scala 269:58] - node _T_495 = and(buf_aligned_in, _T_494) @[axi4_to_ahb.scala 269:38] - node _T_496 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 269:84] - node _T_497 = eq(_T_496, UInt<1>("h01")) @[axi4_to_ahb.scala 269:91] - node _T_498 = and(_T_495, _T_497) @[axi4_to_ahb.scala 269:71] - node _T_499 = bits(_T_498, 0, 0) @[axi4_to_ahb.scala 269:111] - node _T_500 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 269:142] - node _T_501 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 121:42] - node _T_502 = eq(_T_501, UInt<8>("h0ff")) @[axi4_to_ahb.scala 121:49] - node _T_503 = bits(_T_502, 0, 0) @[Bitwise.scala 72:15] - node _T_504 = mux(_T_503, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_505 = and(UInt<2>("h03"), _T_504) @[axi4_to_ahb.scala 121:25] - node _T_506 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 122:35] - node _T_507 = eq(_T_506, UInt<8>("h0f0")) @[axi4_to_ahb.scala 122:42] - node _T_508 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 122:64] - node _T_509 = eq(_T_508, UInt<8>("h0f")) @[axi4_to_ahb.scala 122:71] - node _T_510 = or(_T_507, _T_509) @[axi4_to_ahb.scala 122:55] - node _T_511 = bits(_T_510, 0, 0) @[Bitwise.scala 72:15] - node _T_512 = mux(_T_511, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_513 = and(UInt<2>("h02"), _T_512) @[axi4_to_ahb.scala 122:16] - node _T_514 = or(_T_505, _T_513) @[axi4_to_ahb.scala 121:64] - node _T_515 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:40] - node _T_516 = eq(_T_515, UInt<8>("h0c0")) @[axi4_to_ahb.scala 123:47] - node _T_517 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:69] - node _T_518 = eq(_T_517, UInt<6>("h030")) @[axi4_to_ahb.scala 123:76] - node _T_519 = or(_T_516, _T_518) @[axi4_to_ahb.scala 123:60] - node _T_520 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:98] - node _T_521 = eq(_T_520, UInt<8>("h0c")) @[axi4_to_ahb.scala 123:105] - node _T_522 = or(_T_519, _T_521) @[axi4_to_ahb.scala 123:89] - node _T_523 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:132] - node _T_524 = eq(_T_523, UInt<8>("h03")) @[axi4_to_ahb.scala 123:139] - node _T_525 = or(_T_522, _T_524) @[axi4_to_ahb.scala 123:123] - node _T_526 = bits(_T_525, 0, 0) @[Bitwise.scala 72:15] - node _T_527 = mux(_T_526, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_528 = and(UInt<2>("h01"), _T_527) @[axi4_to_ahb.scala 123:21] - node _T_529 = or(_T_514, _T_528) @[axi4_to_ahb.scala 122:93] - node _T_530 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 269:161] - node _T_531 = mux(_T_499, _T_529, _T_530) @[axi4_to_ahb.scala 269:21] - buf_size_in <= _T_531 @[axi4_to_ahb.scala 269:15] - node _T_532 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 270:32] - node _T_533 = eq(_T_532, UInt<1>("h00")) @[axi4_to_ahb.scala 270:39] - node _T_534 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 271:17] - node _T_535 = eq(_T_534, UInt<1>("h00")) @[axi4_to_ahb.scala 271:24] - node _T_536 = or(_T_533, _T_535) @[axi4_to_ahb.scala 270:48] - node _T_537 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 271:47] - node _T_538 = eq(_T_537, UInt<2>("h01")) @[axi4_to_ahb.scala 271:54] - node _T_539 = or(_T_536, _T_538) @[axi4_to_ahb.scala 271:33] - node _T_540 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 271:86] - node _T_541 = eq(_T_540, UInt<2>("h02")) @[axi4_to_ahb.scala 271:93] - node _T_542 = or(_T_539, _T_541) @[axi4_to_ahb.scala 271:72] - node _T_543 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 272:18] - node _T_544 = eq(_T_543, UInt<2>("h03")) @[axi4_to_ahb.scala 272:25] - node _T_545 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:55] - node _T_546 = eq(_T_545, UInt<2>("h03")) @[axi4_to_ahb.scala 272:62] - node _T_547 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:90] - node _T_548 = eq(_T_547, UInt<4>("h0c")) @[axi4_to_ahb.scala 272:97] - node _T_549 = or(_T_546, _T_548) @[axi4_to_ahb.scala 272:74] - node _T_550 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:125] - node _T_551 = eq(_T_550, UInt<6>("h030")) @[axi4_to_ahb.scala 272:132] - node _T_552 = or(_T_549, _T_551) @[axi4_to_ahb.scala 272:109] - node _T_553 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:161] - node _T_554 = eq(_T_553, UInt<8>("h0c0")) @[axi4_to_ahb.scala 272:168] - node _T_555 = or(_T_552, _T_554) @[axi4_to_ahb.scala 272:145] - node _T_556 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 273:21] - node _T_557 = eq(_T_556, UInt<4>("h0f")) @[axi4_to_ahb.scala 273:28] - node _T_558 = or(_T_555, _T_557) @[axi4_to_ahb.scala 272:181] - node _T_559 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 273:56] - node _T_560 = eq(_T_559, UInt<8>("h0f0")) @[axi4_to_ahb.scala 273:63] - node _T_561 = or(_T_558, _T_560) @[axi4_to_ahb.scala 273:40] - node _T_562 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 273:92] - node _T_563 = eq(_T_562, UInt<8>("h0ff")) @[axi4_to_ahb.scala 273:99] - node _T_564 = or(_T_561, _T_563) @[axi4_to_ahb.scala 273:76] - node _T_565 = and(_T_544, _T_564) @[axi4_to_ahb.scala 272:38] - node _T_566 = or(_T_542, _T_565) @[axi4_to_ahb.scala 271:106] - buf_aligned_in <= _T_566 @[axi4_to_ahb.scala 270:18] - node _T_567 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 275:43] - node _T_568 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 275:62] - node _T_569 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 275:87] - node _T_570 = cat(_T_568, _T_569) @[Cat.scala 29:58] - node _T_571 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 275:108] - node _T_572 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 275:133] - node _T_573 = cat(_T_571, _T_572) @[Cat.scala 29:58] - node _T_574 = mux(_T_567, _T_570, _T_573) @[axi4_to_ahb.scala 275:26] - io.ahb.out.haddr <= _T_574 @[axi4_to_ahb.scala 275:20] - node _T_575 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 276:43] - node _T_576 = bits(buf_aligned_in, 0, 0) @[Bitwise.scala 72:15] - node _T_577 = mux(_T_576, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_578 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 276:94] - node _T_579 = and(_T_577, _T_578) @[axi4_to_ahb.scala 276:81] - node _T_580 = cat(UInt<1>("h00"), _T_579) @[Cat.scala 29:58] - node _T_581 = bits(buf_aligned, 0, 0) @[Bitwise.scala 72:15] - node _T_582 = mux(_T_581, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_583 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 276:148] - node _T_584 = and(_T_582, _T_583) @[axi4_to_ahb.scala 276:138] - node _T_585 = cat(UInt<1>("h00"), _T_584) @[Cat.scala 29:58] - node _T_586 = mux(_T_575, _T_580, _T_585) @[axi4_to_ahb.scala 276:26] - io.ahb.out.hsize <= _T_586 @[axi4_to_ahb.scala 276:20] - io.ahb.out.hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 278:21] - io.ahb.out.hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 279:24] - node _T_587 = bits(io.axi.ar.bits.prot, 2, 2) @[axi4_to_ahb.scala 280:57] - node _T_588 = eq(_T_587, UInt<1>("h00")) @[axi4_to_ahb.scala 280:37] - node _T_589 = cat(UInt<1>("h01"), _T_588) @[Cat.scala 29:58] - io.ahb.out.hprot <= _T_589 @[axi4_to_ahb.scala 280:20] - node _T_590 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 281:44] - node _T_591 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 281:59] - node _T_592 = eq(_T_591, UInt<1>("h01")) @[axi4_to_ahb.scala 281:66] - node _T_593 = mux(_T_590, _T_592, buf_write) @[axi4_to_ahb.scala 281:27] - io.ahb.out.hwrite <= _T_593 @[axi4_to_ahb.scala 281:21] - node _T_594 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 282:32] - io.ahb.out.hwdata <= _T_594 @[axi4_to_ahb.scala 282:21] - slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 284:15] - node _T_595 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 285:43] - node _T_596 = mux(_T_595, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 285:23] - node _T_597 = bits(slvbuf_error, 0, 0) @[Bitwise.scala 72:15] - node _T_598 = mux(_T_597, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_599 = and(_T_598, UInt<2>("h02")) @[axi4_to_ahb.scala 285:88] - node _T_600 = cat(_T_596, _T_599) @[Cat.scala 29:58] - slave_opc <= _T_600 @[axi4_to_ahb.scala 285:13] - node _T_601 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 286:41] - node _T_602 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 286:66] - node _T_603 = cat(_T_602, _T_602) @[Cat.scala 29:58] - node _T_604 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 286:91] - node _T_605 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 286:110] - node _T_606 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 286:131] - node _T_607 = mux(_T_604, _T_605, _T_606) @[axi4_to_ahb.scala 286:79] - node _T_608 = mux(_T_601, _T_603, _T_607) @[axi4_to_ahb.scala 286:21] - slave_rdata <= _T_608 @[axi4_to_ahb.scala 286:15] - node _T_609 = bits(slvbuf_tag, 0, 0) @[axi4_to_ahb.scala 287:26] - slave_tag <= _T_609 @[axi4_to_ahb.scala 287:13] - node _T_610 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 289:37] - node _T_611 = neq(_T_610, UInt<1>("h00")) @[axi4_to_ahb.scala 289:44] - node _T_612 = and(_T_611, io.ahb.in.hready) @[axi4_to_ahb.scala 289:56] - node _T_613 = and(_T_612, io.ahb.out.hwrite) @[axi4_to_ahb.scala 289:75] - last_addr_en <= _T_613 @[axi4_to_ahb.scala 289:16] - node _T_614 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 291:31] - node _T_615 = and(_T_614, master_ready) @[axi4_to_ahb.scala 291:49] - wrbuf_en <= _T_615 @[axi4_to_ahb.scala 291:12] - node _T_616 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 292:35] - node _T_617 = and(_T_616, master_ready) @[axi4_to_ahb.scala 292:52] - wrbuf_data_en <= _T_617 @[axi4_to_ahb.scala 292:17] - node _T_618 = and(master_valid, master_ready) @[axi4_to_ahb.scala 293:34] - node _T_619 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 293:62] - node _T_620 = eq(_T_619, UInt<1>("h01")) @[axi4_to_ahb.scala 293:69] - node _T_621 = and(_T_618, _T_620) @[axi4_to_ahb.scala 293:49] - wrbuf_cmd_sent <= _T_621 @[axi4_to_ahb.scala 293:18] - node _T_622 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 294:33] - node _T_623 = and(wrbuf_cmd_sent, _T_622) @[axi4_to_ahb.scala 294:31] - wrbuf_rst <= _T_623 @[axi4_to_ahb.scala 294:13] - node _T_624 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 296:36] - node _T_625 = and(wrbuf_vld, _T_624) @[axi4_to_ahb.scala 296:34] - node _T_626 = eq(_T_625, UInt<1>("h00")) @[axi4_to_ahb.scala 296:22] - node _T_627 = and(_T_626, master_ready) @[axi4_to_ahb.scala 296:53] - io.axi.aw.ready <= _T_627 @[axi4_to_ahb.scala 296:19] - node _T_628 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 297:40] - node _T_629 = and(wrbuf_data_vld, _T_628) @[axi4_to_ahb.scala 297:38] - node _T_630 = eq(_T_629, UInt<1>("h00")) @[axi4_to_ahb.scala 297:21] - node _T_631 = and(_T_630, master_ready) @[axi4_to_ahb.scala 297:57] - io.axi.w.ready <= _T_631 @[axi4_to_ahb.scala 297:18] - node _T_632 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 298:34] - node _T_633 = eq(_T_632, UInt<1>("h00")) @[axi4_to_ahb.scala 298:22] - node _T_634 = and(_T_633, master_ready) @[axi4_to_ahb.scala 298:52] - io.axi.ar.ready <= _T_634 @[axi4_to_ahb.scala 298:19] - io.axi.r.bits.last <= UInt<1>("h01") @[axi4_to_ahb.scala 299:22] - node _T_635 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 301:71] - node _T_636 = mux(_T_635, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 301:55] - node _T_637 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 301:91] - node _T_638 = and(_T_636, _T_637) @[axi4_to_ahb.scala 301:89] - reg _T_639 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 301:51] - _T_639 <= _T_638 @[axi4_to_ahb.scala 301:51] - wrbuf_vld <= _T_639 @[axi4_to_ahb.scala 301:21] - node _T_640 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 302:76] - node _T_641 = mux(_T_640, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 302:55] - node _T_642 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 302:102] - node _T_643 = and(_T_641, _T_642) @[axi4_to_ahb.scala 302:100] - reg _T_644 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 302:51] - _T_644 <= _T_643 @[axi4_to_ahb.scala 302:51] - wrbuf_data_vld <= _T_644 @[axi4_to_ahb.scala 302:21] - node _T_645 = bits(io.axi.aw.bits.id, 0, 0) @[axi4_to_ahb.scala 303:71] - node _T_646 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 303:105] - reg _T_647 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_646 : @[Reg.scala 28:19] - _T_647 <= _T_645 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - wrbuf_tag <= _T_647 @[axi4_to_ahb.scala 303:21] - node _T_648 = bits(io.axi.aw.bits.size, 2, 0) @[axi4_to_ahb.scala 304:73] - node _T_649 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 304:101] - reg _T_650 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_649 : @[Reg.scala 28:19] - _T_650 <= _T_648 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - wrbuf_size <= _T_650 @[axi4_to_ahb.scala 304:21] - node _T_651 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 305:61] - inst rvclkhdr_2 of rvclkhdr_851 @[lib.scala 368:23] - rvclkhdr_2.clock <= clock - rvclkhdr_2.reset <= reset - rvclkhdr_2.io.clk <= bus_clk @[lib.scala 370:18] - rvclkhdr_2.io.en <= _T_651 @[lib.scala 371:17] - rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_652 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_652 <= io.axi.aw.bits.addr @[lib.scala 374:16] - wrbuf_addr <= _T_652 @[axi4_to_ahb.scala 305:21] - node _T_653 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 306:65] - inst rvclkhdr_3 of rvclkhdr_852 @[lib.scala 368:23] - rvclkhdr_3.clock <= clock - rvclkhdr_3.reset <= reset - rvclkhdr_3.io.clk <= bus_clk @[lib.scala 370:18] - rvclkhdr_3.io.en <= _T_653 @[lib.scala 371:17] - rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_654 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_654 <= io.axi.w.bits.data @[lib.scala 374:16] - wrbuf_data <= _T_654 @[axi4_to_ahb.scala 306:21] - node _T_655 = bits(io.axi.w.bits.strb, 7, 0) @[axi4_to_ahb.scala 307:72] - node _T_656 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 307:105] - reg _T_657 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_656 : @[Reg.scala 28:19] - _T_657 <= _T_655 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - wrbuf_byteen <= _T_657 @[axi4_to_ahb.scala 307:21] - node _T_658 = bits(io.ahb.out.haddr, 31, 0) @[axi4_to_ahb.scala 308:71] - node _T_659 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 308:104] - reg _T_660 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_659 : @[Reg.scala 28:19] - _T_660 <= _T_658 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - last_bus_addr <= _T_660 @[axi4_to_ahb.scala 308:21] - node _T_661 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 309:89] - reg _T_662 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_661 : @[Reg.scala 28:19] - _T_662 <= buf_write_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_write <= _T_662 @[axi4_to_ahb.scala 309:21] - node _T_663 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 310:64] - node _T_664 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 310:99] - reg _T_665 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_664 : @[Reg.scala 28:19] - _T_665 <= _T_663 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_tag <= _T_665 @[axi4_to_ahb.scala 310:21] - node _T_666 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 311:42] - node _T_667 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 311:61] - node _T_668 = bits(_T_667, 0, 0) @[axi4_to_ahb.scala 311:78] - inst rvclkhdr_4 of rvclkhdr_853 @[lib.scala 368:23] - rvclkhdr_4.clock <= clock - rvclkhdr_4.reset <= reset - rvclkhdr_4.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_4.io.en <= _T_668 @[lib.scala 371:17] - rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_669 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_669 <= _T_666 @[lib.scala 374:16] - buf_addr <= _T_669 @[axi4_to_ahb.scala 311:21] - node _T_670 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 312:65] - node _T_671 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 312:94] - reg _T_672 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_671 : @[Reg.scala 28:19] - _T_672 <= _T_670 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_size <= _T_672 @[axi4_to_ahb.scala 312:21] - node _T_673 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 313:91] - reg _T_674 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_673 : @[Reg.scala 28:19] - _T_674 <= buf_aligned_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_aligned <= _T_674 @[axi4_to_ahb.scala 313:21] - node _T_675 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 314:67] - node _T_676 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 314:96] - reg _T_677 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_676 : @[Reg.scala 28:19] - _T_677 <= _T_675 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_byteen <= _T_677 @[axi4_to_ahb.scala 314:21] - node _T_678 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 315:42] - node _T_679 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 315:66] - node _T_680 = bits(_T_679, 0, 0) @[axi4_to_ahb.scala 315:89] - inst rvclkhdr_5 of rvclkhdr_854 @[lib.scala 368:23] - rvclkhdr_5.clock <= clock - rvclkhdr_5.reset <= reset - rvclkhdr_5.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_5.io.en <= _T_680 @[lib.scala 371:17] - rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_681 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_681 <= _T_678 @[lib.scala 374:16] - buf_data <= _T_681 @[axi4_to_ahb.scala 315:21] - node _T_682 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 316:89] - reg _T_683 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_682 : @[Reg.scala 28:19] - _T_683 <= buf_write @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - slvbuf_write <= _T_683 @[axi4_to_ahb.scala 316:21] - node _T_684 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 317:61] - node _T_685 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 317:99] - reg _T_686 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_685 : @[Reg.scala 28:19] - _T_686 <= _T_684 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - slvbuf_tag <= _T_686 @[axi4_to_ahb.scala 317:21] - node _T_687 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 318:99] - reg _T_688 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_687 : @[Reg.scala 28:19] - _T_688 <= slvbuf_error_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - slvbuf_error <= _T_688 @[axi4_to_ahb.scala 318:21] - node _T_689 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 319:72] - node _T_690 = mux(_T_689, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 319:56] - node _T_691 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 319:92] - node _T_692 = and(_T_690, _T_691) @[axi4_to_ahb.scala 319:90] - reg _T_693 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 319:52] - _T_693 <= _T_692 @[axi4_to_ahb.scala 319:52] - cmd_doneQ <= _T_693 @[axi4_to_ahb.scala 319:21] - node _T_694 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 320:71] - node _T_695 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 320:110] - reg _T_696 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_695 : @[Reg.scala 28:19] - _T_696 <= _T_694 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_cmd_byte_ptrQ <= _T_696 @[axi4_to_ahb.scala 320:21] - reg _T_697 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 321:52] - _T_697 <= io.ahb.in.hready @[axi4_to_ahb.scala 321:52] - ahb_hready_q <= _T_697 @[axi4_to_ahb.scala 321:21] - node _T_698 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 322:70] - reg _T_699 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 322:52] - _T_699 <= _T_698 @[axi4_to_ahb.scala 322:52] - ahb_htrans_q <= _T_699 @[axi4_to_ahb.scala 322:21] - reg _T_700 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 323:57] - _T_700 <= io.ahb.out.hwrite @[axi4_to_ahb.scala 323:57] - ahb_hwrite_q <= _T_700 @[axi4_to_ahb.scala 323:21] - reg _T_701 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 324:52] - _T_701 <= io.ahb.in.hresp @[axi4_to_ahb.scala 324:52] - ahb_hresp_q <= _T_701 @[axi4_to_ahb.scala 324:21] - node _T_702 = bits(io.ahb.in.hrdata, 63, 0) @[axi4_to_ahb.scala 325:74] - reg _T_703 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 325:57] - _T_703 <= _T_702 @[axi4_to_ahb.scala 325:57] - ahb_hrdata_q <= _T_703 @[axi4_to_ahb.scala 325:21] - node _T_704 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 327:43] - node _T_705 = or(_T_704, io.clk_override) @[axi4_to_ahb.scala 327:58] - node _T_706 = and(io.bus_clk_en, _T_705) @[axi4_to_ahb.scala 327:30] - buf_clken <= _T_706 @[axi4_to_ahb.scala 327:13] - node _T_707 = bits(io.ahb.out.htrans, 1, 1) @[axi4_to_ahb.scala 328:76] - node _T_708 = and(io.ahb.in.hready, _T_707) @[axi4_to_ahb.scala 328:57] - node _T_709 = or(_T_708, io.clk_override) @[axi4_to_ahb.scala 328:81] - node _T_710 = and(io.bus_clk_en, _T_709) @[axi4_to_ahb.scala 328:36] - ahbm_addr_clken <= _T_710 @[axi4_to_ahb.scala 328:19] - node _T_711 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 329:50] - node _T_712 = or(_T_711, io.clk_override) @[axi4_to_ahb.scala 329:60] - node _T_713 = and(io.bus_clk_en, _T_712) @[axi4_to_ahb.scala 329:36] - ahbm_data_clken <= _T_713 @[axi4_to_ahb.scala 329:19] - inst rvclkhdr_6 of rvclkhdr_855 @[lib.scala 343:22] - rvclkhdr_6.clock <= clock - rvclkhdr_6.reset <= reset - rvclkhdr_6.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_6.io.en <= buf_clken @[lib.scala 345:16] - rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - buf_clk <= rvclkhdr_6.io.l1clk @[axi4_to_ahb.scala 332:12] - inst rvclkhdr_7 of rvclkhdr_856 @[lib.scala 343:22] - rvclkhdr_7.clock <= clock - rvclkhdr_7.reset <= reset - rvclkhdr_7.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_7.io.en <= io.bus_clk_en @[lib.scala 345:16] - rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahbm_clk <= rvclkhdr_7.io.l1clk @[axi4_to_ahb.scala 333:12] - inst rvclkhdr_8 of rvclkhdr_857 @[lib.scala 343:22] - rvclkhdr_8.clock <= clock - rvclkhdr_8.reset <= reset - rvclkhdr_8.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_8.io.en <= ahbm_addr_clken @[lib.scala 345:16] - rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahbm_addr_clk <= rvclkhdr_8.io.l1clk @[axi4_to_ahb.scala 334:17] - inst rvclkhdr_9 of rvclkhdr_858 @[lib.scala 343:22] - rvclkhdr_9.clock <= clock - rvclkhdr_9.reset <= reset - rvclkhdr_9.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_9.io.en <= ahbm_data_clken @[lib.scala 345:16] - rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahbm_data_clk <= rvclkhdr_9.io.l1clk @[axi4_to_ahb.scala 335:17] - - extmodule gated_latch_859 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_859 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_859 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_860 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_860 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_860 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_861 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_861 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_861 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_862 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_862 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_862 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_863 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_863 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_863 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_864 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_864 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_864 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_865 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_865 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_865 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_866 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_866 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_866 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_867 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_867 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_867 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_868 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_868 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_868 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - module axi4_to_ahb_1 : - input clock : Clock - input reset : AsyncReset - output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ahb : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}} - - wire buf_rst : UInt<1> - buf_rst <= UInt<1>("h00") - buf_rst <= UInt<1>("h00") @[axi4_to_ahb.scala 21:11] - io.ahb.out.htrans <= UInt<1>("h00") @[axi4_to_ahb.scala 22:21] - wire buf_state_en : UInt<1> - buf_state_en <= UInt<1>("h00") - wire ahbm_clk : Clock @[axi4_to_ahb.scala 24:22] - wire ahbm_addr_clk : Clock @[axi4_to_ahb.scala 25:27] - wire ahbm_data_clk : Clock @[axi4_to_ahb.scala 26:27] - wire buf_state : UInt<3> - buf_state <= UInt<3>("h00") - wire buf_nxtstate : UInt<3> - buf_nxtstate <= UInt<3>("h00") - node _T = bits(buf_state_en, 0, 0) @[axi4_to_ahb.scala 30:70] - node _T_1 = mux(_T, buf_nxtstate, buf_state) @[axi4_to_ahb.scala 30:50] - node _T_2 = eq(buf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 30:108] - node _T_3 = bits(_T_2, 0, 0) @[Bitwise.scala 72:15] - node _T_4 = mux(_T_3, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_5 = and(_T_1, _T_4) @[axi4_to_ahb.scala 30:98] - reg _T_6 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 30:45] - _T_6 <= _T_5 @[axi4_to_ahb.scala 30:45] - buf_state <= _T_6 @[axi4_to_ahb.scala 30:13] - wire slave_valid : UInt<1> - slave_valid <= UInt<1>("h00") - wire slave_ready : UInt<1> - slave_ready <= UInt<1>("h00") - wire slave_tag : UInt<3> - slave_tag <= UInt<3>("h00") - wire slave_rdata : UInt<64> - slave_rdata <= UInt<64>("h00") - wire slave_opc : UInt<4> - slave_opc <= UInt<4>("h00") - wire wrbuf_en : UInt<1> - wrbuf_en <= UInt<1>("h00") - wire wrbuf_data_en : UInt<1> - wrbuf_data_en <= UInt<1>("h00") - wire wrbuf_cmd_sent : UInt<1> - wrbuf_cmd_sent <= UInt<1>("h00") - wire wrbuf_rst : UInt<1> - wrbuf_rst <= UInt<1>("h00") - wire wrbuf_vld : UInt<1> - wrbuf_vld <= UInt<1>("h00") - wire wrbuf_data_vld : UInt<1> - wrbuf_data_vld <= UInt<1>("h00") - wire wrbuf_tag : UInt<3> - wrbuf_tag <= UInt<3>("h00") - wire wrbuf_size : UInt<3> - wrbuf_size <= UInt<3>("h00") - wire wrbuf_addr : UInt<32> - wrbuf_addr <= UInt<32>("h00") - wire wrbuf_data : UInt<64> - wrbuf_data <= UInt<64>("h00") - wire wrbuf_byteen : UInt<8> - wrbuf_byteen <= UInt<8>("h00") - wire bus_write_clk_en : UInt<1> - bus_write_clk_en <= UInt<1>("h00") - wire bus_clk : Clock @[axi4_to_ahb.scala 50:21] - wire bus_write_clk : Clock @[axi4_to_ahb.scala 51:27] - wire master_valid : UInt<1> - master_valid <= UInt<1>("h00") - wire master_ready : UInt<1> - master_ready <= UInt<1>("h00") - wire master_tag : UInt<3> - master_tag <= UInt<3>("h00") - wire master_addr : UInt<32> - master_addr <= UInt<32>("h00") - wire master_wdata : UInt<64> - master_wdata <= UInt<64>("h00") - wire master_size : UInt<3> - master_size <= UInt<3>("h00") - wire master_opc : UInt<3> - master_opc <= UInt<3>("h00") - wire master_byteen : UInt<8> - master_byteen <= UInt<8>("h00") - wire buf_addr : UInt<32> - buf_addr <= UInt<32>("h00") - wire buf_size : UInt<2> - buf_size <= UInt<2>("h00") - wire buf_write : UInt<1> - buf_write <= UInt<1>("h00") - wire buf_byteen : UInt<8> - buf_byteen <= UInt<8>("h00") - wire buf_aligned : UInt<1> - buf_aligned <= UInt<1>("h00") - wire buf_data : UInt<64> - buf_data <= UInt<64>("h00") - wire buf_tag : UInt<3> - buf_tag <= UInt<3>("h00") - wire buf_tag_in : UInt<3> - buf_tag_in <= UInt<3>("h00") - wire buf_addr_in : UInt<32> - buf_addr_in <= UInt<32>("h00") - wire buf_byteen_in : UInt<8> - buf_byteen_in <= UInt<8>("h00") - wire buf_data_in : UInt<64> - buf_data_in <= UInt<64>("h00") - wire buf_write_in : UInt<1> - buf_write_in <= UInt<1>("h00") - wire buf_aligned_in : UInt<1> - buf_aligned_in <= UInt<1>("h00") - wire buf_size_in : UInt<3> - buf_size_in <= UInt<3>("h00") - wire buf_wr_en : UInt<1> - buf_wr_en <= UInt<1>("h00") - wire buf_data_wr_en : UInt<1> - buf_data_wr_en <= UInt<1>("h00") - wire slvbuf_error_en : UInt<1> - slvbuf_error_en <= UInt<1>("h00") - wire wr_cmd_vld : UInt<1> - wr_cmd_vld <= UInt<1>("h00") - wire cmd_done_rst : UInt<1> - cmd_done_rst <= UInt<1>("h00") - wire cmd_done : UInt<1> - cmd_done <= UInt<1>("h00") - wire cmd_doneQ : UInt<1> - cmd_doneQ <= UInt<1>("h00") - wire trxn_done : UInt<1> - trxn_done <= UInt<1>("h00") - wire buf_cmd_byte_ptr : UInt<3> - buf_cmd_byte_ptr <= UInt<3>("h00") - wire buf_cmd_byte_ptrQ : UInt<3> - buf_cmd_byte_ptrQ <= UInt<3>("h00") - wire buf_cmd_nxtbyte_ptr : UInt<3> - buf_cmd_nxtbyte_ptr <= UInt<3>("h00") - wire buf_cmd_byte_ptr_en : UInt<1> - buf_cmd_byte_ptr_en <= UInt<1>("h00") - wire found : UInt<1> - found <= UInt<1>("h00") - wire slave_valid_pre : UInt<1> - slave_valid_pre <= UInt<1>("h00") - wire ahb_hready_q : UInt<1> - ahb_hready_q <= UInt<1>("h00") - wire ahb_hresp_q : UInt<1> - ahb_hresp_q <= UInt<1>("h00") - wire ahb_htrans_q : UInt<2> - ahb_htrans_q <= UInt<2>("h00") - wire ahb_hwrite_q : UInt<1> - ahb_hwrite_q <= UInt<1>("h00") - wire ahb_hrdata_q : UInt<64> - ahb_hrdata_q <= UInt<64>("h00") - wire slvbuf_write : UInt<1> - slvbuf_write <= UInt<1>("h00") - wire slvbuf_error : UInt<1> - slvbuf_error <= UInt<1>("h00") - wire slvbuf_tag : UInt<3> - slvbuf_tag <= UInt<3>("h00") - wire slvbuf_error_in : UInt<1> - slvbuf_error_in <= UInt<1>("h00") - wire slvbuf_wr_en : UInt<1> - slvbuf_wr_en <= UInt<1>("h00") - wire bypass_en : UInt<1> - bypass_en <= UInt<1>("h00") - wire rd_bypass_idle : UInt<1> - rd_bypass_idle <= UInt<1>("h00") - wire last_addr_en : UInt<1> - last_addr_en <= UInt<1>("h00") - wire last_bus_addr : UInt<32> - last_bus_addr <= UInt<32>("h00") - wire buf_clken : UInt<1> - buf_clken <= UInt<1>("h00") - wire slvbuf_clken : UInt<1> - slvbuf_clken <= UInt<1>("h00") - wire ahbm_addr_clken : UInt<1> - ahbm_addr_clken <= UInt<1>("h00") - wire ahbm_data_clken : UInt<1> - ahbm_data_clken <= UInt<1>("h00") - wire buf_clk : Clock @[axi4_to_ahb.scala 118:21] - node _T_7 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 139:27] - wr_cmd_vld <= _T_7 @[axi4_to_ahb.scala 139:14] - node _T_8 = or(wr_cmd_vld, io.axi.ar.valid) @[axi4_to_ahb.scala 140:30] - master_valid <= _T_8 @[axi4_to_ahb.scala 140:16] - node _T_9 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 141:38] - node _T_10 = bits(wrbuf_tag, 2, 0) @[axi4_to_ahb.scala 141:51] - node _T_11 = bits(io.axi.ar.bits.id, 2, 0) @[axi4_to_ahb.scala 141:82] - node _T_12 = mux(_T_9, _T_10, _T_11) @[axi4_to_ahb.scala 141:20] - master_tag <= _T_12 @[axi4_to_ahb.scala 141:14] - node _T_13 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 142:38] - node _T_14 = mux(_T_13, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 142:20] - master_opc <= _T_14 @[axi4_to_ahb.scala 142:14] - node _T_15 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 143:39] - node _T_16 = bits(wrbuf_addr, 31, 0) @[axi4_to_ahb.scala 143:53] - node _T_17 = bits(io.axi.ar.bits.addr, 31, 0) @[axi4_to_ahb.scala 143:81] - node _T_18 = mux(_T_15, _T_16, _T_17) @[axi4_to_ahb.scala 143:21] - master_addr <= _T_18 @[axi4_to_ahb.scala 143:15] - node _T_19 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 144:39] - node _T_20 = bits(wrbuf_size, 2, 0) @[axi4_to_ahb.scala 144:53] - node _T_21 = bits(io.axi.ar.bits.size, 2, 0) @[axi4_to_ahb.scala 144:80] - node _T_22 = mux(_T_19, _T_20, _T_21) @[axi4_to_ahb.scala 144:21] - master_size <= _T_22 @[axi4_to_ahb.scala 144:15] - node _T_23 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 145:32] - master_byteen <= _T_23 @[axi4_to_ahb.scala 145:17] - node _T_24 = bits(wrbuf_data, 63, 0) @[axi4_to_ahb.scala 146:29] - master_wdata <= _T_24 @[axi4_to_ahb.scala 146:16] - node _T_25 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 149:33] - node _T_26 = bits(slave_opc, 3, 3) @[axi4_to_ahb.scala 149:58] - node _T_27 = and(_T_25, _T_26) @[axi4_to_ahb.scala 149:47] - io.axi.b.valid <= _T_27 @[axi4_to_ahb.scala 149:18] - node _T_28 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 150:38] - node _T_29 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 150:65] - node _T_30 = mux(_T_29, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 150:55] - node _T_31 = mux(_T_28, UInt<2>("h02"), _T_30) @[axi4_to_ahb.scala 150:28] - io.axi.b.bits.resp <= _T_31 @[axi4_to_ahb.scala 150:22] - node _T_32 = bits(slave_tag, 2, 0) @[axi4_to_ahb.scala 151:32] - io.axi.b.bits.id <= _T_32 @[axi4_to_ahb.scala 151:20] - node _T_33 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 153:33] - node _T_34 = bits(slave_opc, 3, 2) @[axi4_to_ahb.scala 153:59] - node _T_35 = eq(_T_34, UInt<1>("h00")) @[axi4_to_ahb.scala 153:66] - node _T_36 = and(_T_33, _T_35) @[axi4_to_ahb.scala 153:47] - io.axi.r.valid <= _T_36 @[axi4_to_ahb.scala 153:18] - node _T_37 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 154:38] - node _T_38 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 154:65] - node _T_39 = mux(_T_38, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 154:55] - node _T_40 = mux(_T_37, UInt<2>("h02"), _T_39) @[axi4_to_ahb.scala 154:28] - io.axi.r.bits.resp <= _T_40 @[axi4_to_ahb.scala 154:22] - node _T_41 = bits(slave_tag, 2, 0) @[axi4_to_ahb.scala 155:32] - io.axi.r.bits.id <= _T_41 @[axi4_to_ahb.scala 155:20] - node _T_42 = bits(slave_rdata, 63, 0) @[axi4_to_ahb.scala 156:36] - io.axi.r.bits.data <= _T_42 @[axi4_to_ahb.scala 156:22] - node _T_43 = and(io.axi.b.ready, io.axi.r.ready) @[axi4_to_ahb.scala 157:33] - slave_ready <= _T_43 @[axi4_to_ahb.scala 157:15] - node _T_44 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 160:57] - node _T_45 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 160:94] - node _T_46 = or(_T_44, _T_45) @[axi4_to_ahb.scala 160:76] - node _T_47 = and(io.bus_clk_en, _T_46) @[axi4_to_ahb.scala 160:37] - bus_write_clk_en <= _T_47 @[axi4_to_ahb.scala 160:20] - inst rvclkhdr of rvclkhdr_859 @[lib.scala 343:22] - rvclkhdr.clock <= clock - rvclkhdr.reset <= reset - rvclkhdr.io.clk <= clock @[lib.scala 344:17] - rvclkhdr.io.en <= io.bus_clk_en @[lib.scala 345:16] - rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - bus_clk <= rvclkhdr.io.l1clk @[axi4_to_ahb.scala 162:11] - node _T_48 = bits(bus_write_clk_en, 0, 0) @[axi4_to_ahb.scala 163:59] - inst rvclkhdr_1 of rvclkhdr_860 @[lib.scala 343:22] - rvclkhdr_1.clock <= clock - rvclkhdr_1.reset <= reset - rvclkhdr_1.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_1.io.en <= _T_48 @[lib.scala 345:16] - rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - bus_write_clk <= rvclkhdr_1.io.l1clk @[axi4_to_ahb.scala 163:17] - node _T_49 = eq(UInt<3>("h00"), buf_state) @[Conditional.scala 37:30] - when _T_49 : @[Conditional.scala 40:58] - master_ready <= UInt<1>("h01") @[axi4_to_ahb.scala 167:20] - node _T_50 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 168:34] - node _T_51 = eq(_T_50, UInt<1>("h01")) @[axi4_to_ahb.scala 168:41] - buf_write_in <= _T_51 @[axi4_to_ahb.scala 168:20] - node _T_52 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 169:46] - node _T_53 = mux(_T_52, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 169:26] - buf_nxtstate <= _T_53 @[axi4_to_ahb.scala 169:20] - node _T_54 = and(master_valid, UInt<1>("h01")) @[axi4_to_ahb.scala 170:36] - buf_state_en <= _T_54 @[axi4_to_ahb.scala 170:20] - buf_wr_en <= buf_state_en @[axi4_to_ahb.scala 171:17] - node _T_55 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 172:54] - node _T_56 = and(buf_state_en, _T_55) @[axi4_to_ahb.scala 172:38] - buf_data_wr_en <= _T_56 @[axi4_to_ahb.scala 172:22] - buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 173:27] - node _T_57 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 175:50] - node _T_58 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 175:94] - node _T_59 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_60 = tail(_T_59, 1) @[axi4_to_ahb.scala 135:52] - node _T_61 = mux(UInt<1>("h00"), _T_60, UInt<3>("h00")) @[axi4_to_ahb.scala 135:24] - node _T_62 = bits(_T_58, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_63 = geq(UInt<1>("h00"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_64 = and(_T_62, _T_63) @[axi4_to_ahb.scala 136:48] - node _T_65 = bits(_T_58, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_66 = geq(UInt<1>("h01"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_67 = and(_T_65, _T_66) @[axi4_to_ahb.scala 136:48] - node _T_68 = bits(_T_58, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_69 = geq(UInt<2>("h02"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_70 = and(_T_68, _T_69) @[axi4_to_ahb.scala 136:48] - node _T_71 = bits(_T_58, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_72 = geq(UInt<2>("h03"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_73 = and(_T_71, _T_72) @[axi4_to_ahb.scala 136:48] - node _T_74 = bits(_T_58, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_75 = geq(UInt<3>("h04"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_76 = and(_T_74, _T_75) @[axi4_to_ahb.scala 136:48] - node _T_77 = bits(_T_58, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_78 = geq(UInt<3>("h05"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_79 = and(_T_77, _T_78) @[axi4_to_ahb.scala 136:48] - node _T_80 = bits(_T_58, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_81 = geq(UInt<3>("h06"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_82 = and(_T_80, _T_81) @[axi4_to_ahb.scala 136:48] - node _T_83 = bits(_T_58, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_84 = geq(UInt<3>("h07"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_85 = and(_T_83, _T_84) @[axi4_to_ahb.scala 136:48] - node _T_86 = mux(_T_85, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_87 = mux(_T_82, UInt<3>("h06"), _T_86) @[Mux.scala 98:16] - node _T_88 = mux(_T_79, UInt<3>("h05"), _T_87) @[Mux.scala 98:16] - node _T_89 = mux(_T_76, UInt<3>("h04"), _T_88) @[Mux.scala 98:16] - node _T_90 = mux(_T_73, UInt<2>("h03"), _T_89) @[Mux.scala 98:16] - node _T_91 = mux(_T_70, UInt<2>("h02"), _T_90) @[Mux.scala 98:16] - node _T_92 = mux(_T_67, UInt<1>("h01"), _T_91) @[Mux.scala 98:16] - node _T_93 = mux(_T_64, UInt<1>("h00"), _T_92) @[Mux.scala 98:16] - node _T_94 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 175:124] - node _T_95 = mux(_T_57, _T_93, _T_94) @[axi4_to_ahb.scala 175:30] - buf_cmd_byte_ptr <= _T_95 @[axi4_to_ahb.scala 175:24] - bypass_en <= buf_state_en @[axi4_to_ahb.scala 176:17] - node _T_96 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 177:51] - node _T_97 = and(bypass_en, _T_96) @[axi4_to_ahb.scala 177:35] - rd_bypass_idle <= _T_97 @[axi4_to_ahb.scala 177:22] - node _T_98 = bits(bypass_en, 0, 0) @[Bitwise.scala 72:15] - node _T_99 = mux(_T_98, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_100 = and(_T_99, UInt<2>("h02")) @[axi4_to_ahb.scala 178:49] - io.ahb.out.htrans <= _T_100 @[axi4_to_ahb.scala 178:25] - skip @[Conditional.scala 40:58] - else : @[Conditional.scala 39:67] - node _T_101 = eq(UInt<3>("h01"), buf_state) @[Conditional.scala 37:30] - when _T_101 : @[Conditional.scala 39:67] - node _T_102 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 182:54] - node _T_103 = eq(_T_102, UInt<1>("h00")) @[axi4_to_ahb.scala 182:61] - node _T_104 = and(master_valid, _T_103) @[axi4_to_ahb.scala 182:41] - node _T_105 = bits(_T_104, 0, 0) @[axi4_to_ahb.scala 182:82] - node _T_106 = mux(_T_105, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 182:26] - buf_nxtstate <= _T_106 @[axi4_to_ahb.scala 182:20] - node _T_107 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 183:51] - node _T_108 = neq(_T_107, UInt<1>("h00")) @[axi4_to_ahb.scala 183:58] - node _T_109 = and(ahb_hready_q, _T_108) @[axi4_to_ahb.scala 183:36] - node _T_110 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 183:72] - node _T_111 = and(_T_109, _T_110) @[axi4_to_ahb.scala 183:70] - buf_state_en <= _T_111 @[axi4_to_ahb.scala 183:20] - node _T_112 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 184:34] - node _T_113 = and(buf_state_en, _T_112) @[axi4_to_ahb.scala 184:32] - cmd_done <= _T_113 @[axi4_to_ahb.scala 184:16] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 185:20] - node _T_114 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 186:52] - node _T_115 = neq(_T_114, UInt<1>("h00")) @[axi4_to_ahb.scala 186:59] - node _T_116 = and(ahb_hready_q, _T_115) @[axi4_to_ahb.scala 186:37] - node _T_117 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 186:73] - node _T_118 = and(_T_116, _T_117) @[axi4_to_ahb.scala 186:71] - node _T_119 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 186:122] - node _T_120 = eq(_T_119, UInt<1>("h00")) @[axi4_to_ahb.scala 186:129] - node _T_121 = and(master_valid, _T_120) @[axi4_to_ahb.scala 186:109] - node _T_122 = bits(_T_121, 0, 0) @[axi4_to_ahb.scala 186:150] - node _T_123 = mux(_T_122, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 186:94] - node _T_124 = eq(_T_123, UInt<3>("h06")) @[axi4_to_ahb.scala 186:174] - node _T_125 = and(_T_118, _T_124) @[axi4_to_ahb.scala 186:88] - master_ready <= _T_125 @[axi4_to_ahb.scala 186:20] - buf_wr_en <= master_ready @[axi4_to_ahb.scala 187:17] - node _T_126 = and(master_ready, master_valid) @[axi4_to_ahb.scala 188:33] - bypass_en <= _T_126 @[axi4_to_ahb.scala 188:17] - node _T_127 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 189:47] - node _T_128 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 189:62] - node _T_129 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 189:78] - node _T_130 = mux(_T_127, _T_128, _T_129) @[axi4_to_ahb.scala 189:30] - buf_cmd_byte_ptr <= _T_130 @[axi4_to_ahb.scala 189:24] - node _T_131 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 190:48] - node _T_132 = or(_T_131, bypass_en) @[axi4_to_ahb.scala 190:62] - node _T_133 = bits(_T_132, 0, 0) @[Bitwise.scala 72:15] - node _T_134 = mux(_T_133, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_135 = and(UInt<2>("h02"), _T_134) @[axi4_to_ahb.scala 190:36] - io.ahb.out.htrans <= _T_135 @[axi4_to_ahb.scala 190:25] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_136 = eq(UInt<3>("h06"), buf_state) @[Conditional.scala 37:30] - when _T_136 : @[Conditional.scala 39:67] - node _T_137 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 194:39] - node _T_138 = and(ahb_hready_q, _T_137) @[axi4_to_ahb.scala 194:37] - node _T_139 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 194:82] - node _T_140 = eq(_T_139, UInt<1>("h01")) @[axi4_to_ahb.scala 194:89] - node _T_141 = and(master_valid, _T_140) @[axi4_to_ahb.scala 194:70] - node _T_142 = not(_T_141) @[axi4_to_ahb.scala 194:55] - node _T_143 = and(_T_138, _T_142) @[axi4_to_ahb.scala 194:53] - master_ready <= _T_143 @[axi4_to_ahb.scala 194:20] - node _T_144 = and(master_valid, master_ready) @[axi4_to_ahb.scala 195:34] - node _T_145 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 195:62] - node _T_146 = eq(_T_145, UInt<1>("h00")) @[axi4_to_ahb.scala 195:69] - node _T_147 = and(_T_144, _T_146) @[axi4_to_ahb.scala 195:49] - buf_wr_en <= _T_147 @[axi4_to_ahb.scala 195:17] - node _T_148 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 196:45] - node _T_149 = and(master_valid, master_ready) @[axi4_to_ahb.scala 196:82] - node _T_150 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 196:110] - node _T_151 = eq(_T_150, UInt<1>("h00")) @[axi4_to_ahb.scala 196:117] - node _T_152 = and(_T_149, _T_151) @[axi4_to_ahb.scala 196:97] - node _T_153 = bits(_T_152, 0, 0) @[axi4_to_ahb.scala 196:138] - node _T_154 = mux(_T_153, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 196:67] - node _T_155 = mux(_T_148, UInt<3>("h07"), _T_154) @[axi4_to_ahb.scala 196:26] - buf_nxtstate <= _T_155 @[axi4_to_ahb.scala 196:20] - node _T_156 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 197:37] - buf_state_en <= _T_156 @[axi4_to_ahb.scala 197:20] - buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 198:22] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 199:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 200:23] - node _T_157 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 201:41] - node _T_158 = and(buf_state_en, _T_157) @[axi4_to_ahb.scala 201:39] - slave_valid_pre <= _T_158 @[axi4_to_ahb.scala 201:23] - node _T_159 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 202:34] - node _T_160 = and(buf_state_en, _T_159) @[axi4_to_ahb.scala 202:32] - cmd_done <= _T_160 @[axi4_to_ahb.scala 202:16] - node _T_161 = and(master_ready, master_valid) @[axi4_to_ahb.scala 203:33] - node _T_162 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 203:64] - node _T_163 = and(_T_161, _T_162) @[axi4_to_ahb.scala 203:48] - node _T_164 = and(_T_163, buf_state_en) @[axi4_to_ahb.scala 203:79] - bypass_en <= _T_164 @[axi4_to_ahb.scala 203:17] - node _T_165 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 204:47] - node _T_166 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 204:62] - node _T_167 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 204:78] - node _T_168 = mux(_T_165, _T_166, _T_167) @[axi4_to_ahb.scala 204:30] - buf_cmd_byte_ptr <= _T_168 @[axi4_to_ahb.scala 204:24] - node _T_169 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 205:63] - node _T_170 = and(_T_169, buf_state_en) @[axi4_to_ahb.scala 205:78] - node _T_171 = eq(_T_170, UInt<1>("h00")) @[axi4_to_ahb.scala 205:47] - node _T_172 = bits(_T_171, 0, 0) @[Bitwise.scala 72:15] - node _T_173 = mux(_T_172, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_174 = and(UInt<2>("h02"), _T_173) @[axi4_to_ahb.scala 205:36] - io.ahb.out.htrans <= _T_174 @[axi4_to_ahb.scala 205:25] - slvbuf_wr_en <= buf_wr_en @[axi4_to_ahb.scala 206:20] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_175 = eq(UInt<3>("h07"), buf_state) @[Conditional.scala 37:30] - when _T_175 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h03") @[axi4_to_ahb.scala 210:20] - node _T_176 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 211:51] - node _T_177 = neq(_T_176, UInt<1>("h00")) @[axi4_to_ahb.scala 211:58] - node _T_178 = and(ahb_hready_q, _T_177) @[axi4_to_ahb.scala 211:36] - node _T_179 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 211:72] - node _T_180 = and(_T_178, _T_179) @[axi4_to_ahb.scala 211:70] - buf_state_en <= _T_180 @[axi4_to_ahb.scala 211:20] - slave_valid_pre <= buf_state_en @[axi4_to_ahb.scala 212:23] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 213:20] - node _T_181 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 214:35] - buf_cmd_byte_ptr <= _T_181 @[axi4_to_ahb.scala 214:24] - node _T_182 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 215:51] - node _T_183 = bits(_T_182, 0, 0) @[Bitwise.scala 72:15] - node _T_184 = mux(_T_183, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_185 = and(UInt<2>("h02"), _T_184) @[axi4_to_ahb.scala 215:41] - io.ahb.out.htrans <= _T_185 @[axi4_to_ahb.scala 215:25] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_186 = eq(UInt<3>("h03"), buf_state) @[Conditional.scala 37:30] - when _T_186 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h05") @[axi4_to_ahb.scala 219:20] - node _T_187 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 220:37] - buf_state_en <= _T_187 @[axi4_to_ahb.scala 220:20] - buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 221:22] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 222:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 223:23] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 224:20] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_188 = eq(UInt<3>("h02"), buf_state) @[Conditional.scala 37:30] - when _T_188 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h04") @[axi4_to_ahb.scala 228:20] - node _T_189 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 229:33] - node _T_190 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 229:63] - node _T_191 = neq(_T_190, UInt<1>("h00")) @[axi4_to_ahb.scala 229:70] - node _T_192 = and(_T_189, _T_191) @[axi4_to_ahb.scala 229:48] - trxn_done <= _T_192 @[axi4_to_ahb.scala 229:17] - buf_state_en <= trxn_done @[axi4_to_ahb.scala 230:20] - buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 231:27] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 232:20] - node _T_193 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 233:47] - node _T_194 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 233:85] - node _T_195 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 233:103] - node _T_196 = add(_T_194, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_197 = tail(_T_196, 1) @[axi4_to_ahb.scala 135:52] - node _T_198 = mux(UInt<1>("h01"), _T_197, _T_194) @[axi4_to_ahb.scala 135:24] - node _T_199 = bits(_T_195, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_200 = geq(UInt<1>("h00"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_201 = and(_T_199, _T_200) @[axi4_to_ahb.scala 136:48] - node _T_202 = bits(_T_195, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_203 = geq(UInt<1>("h01"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_204 = and(_T_202, _T_203) @[axi4_to_ahb.scala 136:48] - node _T_205 = bits(_T_195, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_206 = geq(UInt<2>("h02"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_207 = and(_T_205, _T_206) @[axi4_to_ahb.scala 136:48] - node _T_208 = bits(_T_195, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_209 = geq(UInt<2>("h03"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_210 = and(_T_208, _T_209) @[axi4_to_ahb.scala 136:48] - node _T_211 = bits(_T_195, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_212 = geq(UInt<3>("h04"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_213 = and(_T_211, _T_212) @[axi4_to_ahb.scala 136:48] - node _T_214 = bits(_T_195, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_215 = geq(UInt<3>("h05"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_216 = and(_T_214, _T_215) @[axi4_to_ahb.scala 136:48] - node _T_217 = bits(_T_195, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_218 = geq(UInt<3>("h06"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_219 = and(_T_217, _T_218) @[axi4_to_ahb.scala 136:48] - node _T_220 = bits(_T_195, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_221 = geq(UInt<3>("h07"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_222 = and(_T_220, _T_221) @[axi4_to_ahb.scala 136:48] - node _T_223 = mux(_T_222, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_224 = mux(_T_219, UInt<3>("h06"), _T_223) @[Mux.scala 98:16] - node _T_225 = mux(_T_216, UInt<3>("h05"), _T_224) @[Mux.scala 98:16] - node _T_226 = mux(_T_213, UInt<3>("h04"), _T_225) @[Mux.scala 98:16] - node _T_227 = mux(_T_210, UInt<2>("h03"), _T_226) @[Mux.scala 98:16] - node _T_228 = mux(_T_207, UInt<2>("h02"), _T_227) @[Mux.scala 98:16] - node _T_229 = mux(_T_204, UInt<1>("h01"), _T_228) @[Mux.scala 98:16] - node _T_230 = mux(_T_201, UInt<1>("h00"), _T_229) @[Mux.scala 98:16] - node _T_231 = mux(_T_193, _T_230, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 233:30] - buf_cmd_byte_ptr <= _T_231 @[axi4_to_ahb.scala 233:24] - node _T_232 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 234:65] - node _T_233 = or(buf_aligned, _T_232) @[axi4_to_ahb.scala 234:44] - node _T_234 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 234:127] - node _T_235 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 234:145] - node _T_236 = add(_T_234, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_237 = tail(_T_236, 1) @[axi4_to_ahb.scala 135:52] - node _T_238 = mux(UInt<1>("h01"), _T_237, _T_234) @[axi4_to_ahb.scala 135:24] - node _T_239 = bits(_T_235, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_240 = geq(UInt<1>("h00"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_241 = and(_T_239, _T_240) @[axi4_to_ahb.scala 136:48] - node _T_242 = bits(_T_235, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_243 = geq(UInt<1>("h01"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_244 = and(_T_242, _T_243) @[axi4_to_ahb.scala 136:48] - node _T_245 = bits(_T_235, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_246 = geq(UInt<2>("h02"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_247 = and(_T_245, _T_246) @[axi4_to_ahb.scala 136:48] - node _T_248 = bits(_T_235, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_249 = geq(UInt<2>("h03"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_250 = and(_T_248, _T_249) @[axi4_to_ahb.scala 136:48] - node _T_251 = bits(_T_235, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_252 = geq(UInt<3>("h04"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_253 = and(_T_251, _T_252) @[axi4_to_ahb.scala 136:48] - node _T_254 = bits(_T_235, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_255 = geq(UInt<3>("h05"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_256 = and(_T_254, _T_255) @[axi4_to_ahb.scala 136:48] - node _T_257 = bits(_T_235, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_258 = geq(UInt<3>("h06"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_259 = and(_T_257, _T_258) @[axi4_to_ahb.scala 136:48] - node _T_260 = bits(_T_235, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_261 = geq(UInt<3>("h07"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_262 = and(_T_260, _T_261) @[axi4_to_ahb.scala 136:48] - node _T_263 = mux(_T_262, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_264 = mux(_T_259, UInt<3>("h06"), _T_263) @[Mux.scala 98:16] - node _T_265 = mux(_T_256, UInt<3>("h05"), _T_264) @[Mux.scala 98:16] - node _T_266 = mux(_T_253, UInt<3>("h04"), _T_265) @[Mux.scala 98:16] - node _T_267 = mux(_T_250, UInt<2>("h03"), _T_266) @[Mux.scala 98:16] - node _T_268 = mux(_T_247, UInt<2>("h02"), _T_267) @[Mux.scala 98:16] - node _T_269 = mux(_T_244, UInt<1>("h01"), _T_268) @[Mux.scala 98:16] - node _T_270 = mux(_T_241, UInt<1>("h00"), _T_269) @[Mux.scala 98:16] - node _T_271 = dshr(buf_byteen, _T_270) @[axi4_to_ahb.scala 234:92] - node _T_272 = bits(_T_271, 0, 0) @[axi4_to_ahb.scala 234:92] - node _T_273 = eq(_T_272, UInt<1>("h00")) @[axi4_to_ahb.scala 234:163] - node _T_274 = or(_T_233, _T_273) @[axi4_to_ahb.scala 234:79] - node _T_275 = and(trxn_done, _T_274) @[axi4_to_ahb.scala 234:29] - cmd_done <= _T_275 @[axi4_to_ahb.scala 234:16] - node _T_276 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 235:47] - node _T_277 = eq(_T_276, UInt<1>("h00")) @[axi4_to_ahb.scala 235:36] - node _T_278 = bits(_T_277, 0, 0) @[Bitwise.scala 72:15] - node _T_279 = mux(_T_278, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_280 = and(_T_279, UInt<2>("h02")) @[axi4_to_ahb.scala 235:61] - io.ahb.out.htrans <= _T_280 @[axi4_to_ahb.scala 235:25] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_281 = eq(UInt<3>("h04"), buf_state) @[Conditional.scala 37:30] - when _T_281 : @[Conditional.scala 39:67] - node _T_282 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 239:34] - node _T_283 = or(_T_282, ahb_hresp_q) @[axi4_to_ahb.scala 239:50] - buf_state_en <= _T_283 @[axi4_to_ahb.scala 239:20] - node _T_284 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 240:38] - node _T_285 = and(buf_state_en, _T_284) @[axi4_to_ahb.scala 240:36] - node _T_286 = and(_T_285, slave_ready) @[axi4_to_ahb.scala 240:51] - master_ready <= _T_286 @[axi4_to_ahb.scala 240:20] - node _T_287 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 241:42] - node _T_288 = or(ahb_hresp_q, _T_287) @[axi4_to_ahb.scala 241:40] - node _T_289 = and(master_valid, master_valid) @[axi4_to_ahb.scala 241:80] - node _T_290 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 241:111] - node _T_291 = eq(_T_290, UInt<1>("h01")) @[axi4_to_ahb.scala 241:117] - node _T_292 = bits(_T_291, 0, 0) @[axi4_to_ahb.scala 241:132] - node _T_293 = mux(_T_292, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 241:99] - node _T_294 = mux(_T_289, _T_293, UInt<3>("h00")) @[axi4_to_ahb.scala 241:65] - node _T_295 = mux(_T_288, UInt<3>("h05"), _T_294) @[axi4_to_ahb.scala 241:26] - buf_nxtstate <= _T_295 @[axi4_to_ahb.scala 241:20] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 242:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 243:23] - node _T_296 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 244:33] - node _T_297 = eq(_T_296, UInt<1>("h01")) @[axi4_to_ahb.scala 244:39] - buf_write_in <= _T_297 @[axi4_to_ahb.scala 244:20] - node _T_298 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 245:50] - node _T_299 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 245:78] - node _T_300 = or(_T_298, _T_299) @[axi4_to_ahb.scala 245:62] - node _T_301 = and(buf_state_en, _T_300) @[axi4_to_ahb.scala 245:33] - buf_wr_en <= _T_301 @[axi4_to_ahb.scala 245:17] - buf_data_wr_en <= buf_wr_en @[axi4_to_ahb.scala 246:22] - node _T_302 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 247:65] - node _T_303 = neq(_T_302, UInt<1>("h00")) @[axi4_to_ahb.scala 247:71] - node _T_304 = and(ahb_hready_q, _T_303) @[axi4_to_ahb.scala 247:50] - node _T_305 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 248:29] - node _T_306 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 248:85] - node _T_307 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 248:101] - node _T_308 = add(_T_306, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_309 = tail(_T_308, 1) @[axi4_to_ahb.scala 135:52] - node _T_310 = mux(UInt<1>("h01"), _T_309, _T_306) @[axi4_to_ahb.scala 135:24] - node _T_311 = bits(_T_307, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_312 = geq(UInt<1>("h00"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_313 = and(_T_311, _T_312) @[axi4_to_ahb.scala 136:48] - node _T_314 = bits(_T_307, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_315 = geq(UInt<1>("h01"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_316 = and(_T_314, _T_315) @[axi4_to_ahb.scala 136:48] - node _T_317 = bits(_T_307, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_318 = geq(UInt<2>("h02"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_319 = and(_T_317, _T_318) @[axi4_to_ahb.scala 136:48] - node _T_320 = bits(_T_307, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_321 = geq(UInt<2>("h03"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_322 = and(_T_320, _T_321) @[axi4_to_ahb.scala 136:48] - node _T_323 = bits(_T_307, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_324 = geq(UInt<3>("h04"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_325 = and(_T_323, _T_324) @[axi4_to_ahb.scala 136:48] - node _T_326 = bits(_T_307, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_327 = geq(UInt<3>("h05"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_328 = and(_T_326, _T_327) @[axi4_to_ahb.scala 136:48] - node _T_329 = bits(_T_307, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_330 = geq(UInt<3>("h06"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_331 = and(_T_329, _T_330) @[axi4_to_ahb.scala 136:48] - node _T_332 = bits(_T_307, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_333 = geq(UInt<3>("h07"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_334 = and(_T_332, _T_333) @[axi4_to_ahb.scala 136:48] - node _T_335 = mux(_T_334, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_336 = mux(_T_331, UInt<3>("h06"), _T_335) @[Mux.scala 98:16] - node _T_337 = mux(_T_328, UInt<3>("h05"), _T_336) @[Mux.scala 98:16] - node _T_338 = mux(_T_325, UInt<3>("h04"), _T_337) @[Mux.scala 98:16] - node _T_339 = mux(_T_322, UInt<2>("h03"), _T_338) @[Mux.scala 98:16] - node _T_340 = mux(_T_319, UInt<2>("h02"), _T_339) @[Mux.scala 98:16] - node _T_341 = mux(_T_316, UInt<1>("h01"), _T_340) @[Mux.scala 98:16] - node _T_342 = mux(_T_313, UInt<1>("h00"), _T_341) @[Mux.scala 98:16] - node _T_343 = dshr(buf_byteen, _T_342) @[axi4_to_ahb.scala 248:51] - node _T_344 = bits(_T_343, 0, 0) @[axi4_to_ahb.scala 248:51] - node _T_345 = eq(_T_344, UInt<1>("h00")) @[axi4_to_ahb.scala 248:116] - node _T_346 = or(_T_305, _T_345) @[axi4_to_ahb.scala 248:38] - node _T_347 = and(_T_304, _T_346) @[axi4_to_ahb.scala 247:80] - node _T_348 = or(ahb_hresp_q, _T_347) @[axi4_to_ahb.scala 247:34] - cmd_done <= _T_348 @[axi4_to_ahb.scala 247:16] - node _T_349 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 249:33] - node _T_350 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 249:64] - node _T_351 = and(_T_349, _T_350) @[axi4_to_ahb.scala 249:48] - bypass_en <= _T_351 @[axi4_to_ahb.scala 249:17] - node _T_352 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 250:48] - node _T_353 = eq(_T_352, UInt<1>("h00")) @[axi4_to_ahb.scala 250:37] - node _T_354 = or(_T_353, bypass_en) @[axi4_to_ahb.scala 250:61] - node _T_355 = bits(_T_354, 0, 0) @[Bitwise.scala 72:15] - node _T_356 = mux(_T_355, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_357 = and(_T_356, UInt<2>("h02")) @[axi4_to_ahb.scala 250:75] - io.ahb.out.htrans <= _T_357 @[axi4_to_ahb.scala 250:25] - node _T_358 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 251:55] - node _T_359 = and(buf_state_en, _T_358) @[axi4_to_ahb.scala 251:39] - slave_valid_pre <= _T_359 @[axi4_to_ahb.scala 251:23] - node _T_360 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 252:33] - node _T_361 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 252:63] - node _T_362 = neq(_T_361, UInt<1>("h00")) @[axi4_to_ahb.scala 252:69] - node _T_363 = and(_T_360, _T_362) @[axi4_to_ahb.scala 252:48] - trxn_done <= _T_363 @[axi4_to_ahb.scala 252:17] - node _T_364 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 253:40] - buf_cmd_byte_ptr_en <= _T_364 @[axi4_to_ahb.scala 253:27] - node _T_365 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 254:79] - node _T_366 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_367 = tail(_T_366, 1) @[axi4_to_ahb.scala 135:52] - node _T_368 = mux(UInt<1>("h00"), _T_367, UInt<3>("h00")) @[axi4_to_ahb.scala 135:24] - node _T_369 = bits(_T_365, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_370 = geq(UInt<1>("h00"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_371 = and(_T_369, _T_370) @[axi4_to_ahb.scala 136:48] - node _T_372 = bits(_T_365, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_373 = geq(UInt<1>("h01"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_374 = and(_T_372, _T_373) @[axi4_to_ahb.scala 136:48] - node _T_375 = bits(_T_365, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_376 = geq(UInt<2>("h02"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_377 = and(_T_375, _T_376) @[axi4_to_ahb.scala 136:48] - node _T_378 = bits(_T_365, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_379 = geq(UInt<2>("h03"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_380 = and(_T_378, _T_379) @[axi4_to_ahb.scala 136:48] - node _T_381 = bits(_T_365, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_382 = geq(UInt<3>("h04"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_383 = and(_T_381, _T_382) @[axi4_to_ahb.scala 136:48] - node _T_384 = bits(_T_365, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_385 = geq(UInt<3>("h05"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_386 = and(_T_384, _T_385) @[axi4_to_ahb.scala 136:48] - node _T_387 = bits(_T_365, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_388 = geq(UInt<3>("h06"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_389 = and(_T_387, _T_388) @[axi4_to_ahb.scala 136:48] - node _T_390 = bits(_T_365, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_391 = geq(UInt<3>("h07"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_392 = and(_T_390, _T_391) @[axi4_to_ahb.scala 136:48] - node _T_393 = mux(_T_392, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_394 = mux(_T_389, UInt<3>("h06"), _T_393) @[Mux.scala 98:16] - node _T_395 = mux(_T_386, UInt<3>("h05"), _T_394) @[Mux.scala 98:16] - node _T_396 = mux(_T_383, UInt<3>("h04"), _T_395) @[Mux.scala 98:16] - node _T_397 = mux(_T_380, UInt<2>("h03"), _T_396) @[Mux.scala 98:16] - node _T_398 = mux(_T_377, UInt<2>("h02"), _T_397) @[Mux.scala 98:16] - node _T_399 = mux(_T_374, UInt<1>("h01"), _T_398) @[Mux.scala 98:16] - node _T_400 = mux(_T_371, UInt<1>("h00"), _T_399) @[Mux.scala 98:16] - node _T_401 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 254:141] - node _T_402 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 254:157] - node _T_403 = add(_T_401, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_404 = tail(_T_403, 1) @[axi4_to_ahb.scala 135:52] - node _T_405 = mux(UInt<1>("h01"), _T_404, _T_401) @[axi4_to_ahb.scala 135:24] - node _T_406 = bits(_T_402, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_407 = geq(UInt<1>("h00"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_408 = and(_T_406, _T_407) @[axi4_to_ahb.scala 136:48] - node _T_409 = bits(_T_402, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_410 = geq(UInt<1>("h01"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_411 = and(_T_409, _T_410) @[axi4_to_ahb.scala 136:48] - node _T_412 = bits(_T_402, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_413 = geq(UInt<2>("h02"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_414 = and(_T_412, _T_413) @[axi4_to_ahb.scala 136:48] - node _T_415 = bits(_T_402, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_416 = geq(UInt<2>("h03"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_417 = and(_T_415, _T_416) @[axi4_to_ahb.scala 136:48] - node _T_418 = bits(_T_402, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_419 = geq(UInt<3>("h04"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_420 = and(_T_418, _T_419) @[axi4_to_ahb.scala 136:48] - node _T_421 = bits(_T_402, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_422 = geq(UInt<3>("h05"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_423 = and(_T_421, _T_422) @[axi4_to_ahb.scala 136:48] - node _T_424 = bits(_T_402, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_425 = geq(UInt<3>("h06"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_426 = and(_T_424, _T_425) @[axi4_to_ahb.scala 136:48] - node _T_427 = bits(_T_402, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_428 = geq(UInt<3>("h07"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_429 = and(_T_427, _T_428) @[axi4_to_ahb.scala 136:48] - node _T_430 = mux(_T_429, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_431 = mux(_T_426, UInt<3>("h06"), _T_430) @[Mux.scala 98:16] - node _T_432 = mux(_T_423, UInt<3>("h05"), _T_431) @[Mux.scala 98:16] - node _T_433 = mux(_T_420, UInt<3>("h04"), _T_432) @[Mux.scala 98:16] - node _T_434 = mux(_T_417, UInt<2>("h03"), _T_433) @[Mux.scala 98:16] - node _T_435 = mux(_T_414, UInt<2>("h02"), _T_434) @[Mux.scala 98:16] - node _T_436 = mux(_T_411, UInt<1>("h01"), _T_435) @[Mux.scala 98:16] - node _T_437 = mux(_T_408, UInt<1>("h00"), _T_436) @[Mux.scala 98:16] - node _T_438 = mux(trxn_done, _T_437, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 254:97] - node _T_439 = mux(bypass_en, _T_400, _T_438) @[axi4_to_ahb.scala 254:30] - buf_cmd_byte_ptr <= _T_439 @[axi4_to_ahb.scala 254:24] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_440 = eq(UInt<3>("h05"), buf_state) @[Conditional.scala 37:30] - when _T_440 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 257:20] - buf_state_en <= slave_ready @[axi4_to_ahb.scala 258:20] - slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 259:23] - slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 260:23] - skip @[Conditional.scala 39:67] - cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 264:16] - node _T_441 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 265:33] - node _T_442 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 265:73] - node _T_443 = eq(_T_442, UInt<1>("h01")) @[axi4_to_ahb.scala 265:80] - node _T_444 = and(buf_aligned_in, _T_443) @[axi4_to_ahb.scala 265:60] - node _T_445 = bits(_T_444, 0, 0) @[axi4_to_ahb.scala 265:100] - node _T_446 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 265:132] - node _T_447 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 127:50] - node _T_448 = eq(_T_447, UInt<8>("h0ff")) @[axi4_to_ahb.scala 127:57] - node _T_449 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 127:81] - node _T_450 = eq(_T_449, UInt<8>("h0f")) @[axi4_to_ahb.scala 127:88] - node _T_451 = or(_T_448, _T_450) @[axi4_to_ahb.scala 127:70] - node _T_452 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 127:117] - node _T_453 = eq(_T_452, UInt<8>("h03")) @[axi4_to_ahb.scala 127:124] - node _T_454 = or(_T_451, _T_453) @[axi4_to_ahb.scala 127:106] - node _T_455 = bits(_T_454, 0, 0) @[Bitwise.scala 72:15] - node _T_456 = mux(_T_455, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_457 = and(UInt<3>("h00"), _T_456) @[axi4_to_ahb.scala 127:29] - node _T_458 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 128:35] - node _T_459 = eq(_T_458, UInt<8>("h0c")) @[axi4_to_ahb.scala 128:42] - node _T_460 = bits(_T_459, 0, 0) @[Bitwise.scala 72:15] - node _T_461 = mux(_T_460, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_462 = and(UInt<2>("h02"), _T_461) @[axi4_to_ahb.scala 128:15] - node _T_463 = or(_T_457, _T_462) @[axi4_to_ahb.scala 127:146] - node _T_464 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 129:36] - node _T_465 = eq(_T_464, UInt<8>("h0f0")) @[axi4_to_ahb.scala 129:43] - node _T_466 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 129:67] - node _T_467 = eq(_T_466, UInt<8>("h03")) @[axi4_to_ahb.scala 129:74] - node _T_468 = or(_T_465, _T_467) @[axi4_to_ahb.scala 129:56] - node _T_469 = bits(_T_468, 0, 0) @[Bitwise.scala 72:15] - node _T_470 = mux(_T_469, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_471 = and(UInt<3>("h04"), _T_470) @[axi4_to_ahb.scala 129:15] - node _T_472 = or(_T_463, _T_471) @[axi4_to_ahb.scala 128:63] - node _T_473 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 130:35] - node _T_474 = eq(_T_473, UInt<8>("h0c0")) @[axi4_to_ahb.scala 130:42] - node _T_475 = bits(_T_474, 0, 0) @[Bitwise.scala 72:15] - node _T_476 = mux(_T_475, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_477 = and(UInt<3>("h06"), _T_476) @[axi4_to_ahb.scala 130:15] - node _T_478 = or(_T_472, _T_477) @[axi4_to_ahb.scala 129:96] - node _T_479 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 131:33] - node _T_480 = eq(_T_479, UInt<8>("h0c0")) @[axi4_to_ahb.scala 131:40] - node _T_481 = bits(_T_480, 0, 0) @[Bitwise.scala 72:15] - node _T_482 = mux(_T_481, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_483 = and(UInt<3>("h06"), _T_482) @[axi4_to_ahb.scala 131:13] - node _T_484 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 265:152] - node _T_485 = mux(_T_445, _T_478, _T_484) @[axi4_to_ahb.scala 265:43] - node _T_486 = cat(_T_441, _T_485) @[Cat.scala 29:58] - buf_addr_in <= _T_486 @[axi4_to_ahb.scala 265:15] - node _T_487 = bits(master_tag, 2, 0) @[axi4_to_ahb.scala 266:27] - buf_tag_in <= _T_487 @[axi4_to_ahb.scala 266:14] - node _T_488 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 267:32] - buf_byteen_in <= _T_488 @[axi4_to_ahb.scala 267:17] - node _T_489 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 268:33] - node _T_490 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 268:59] - node _T_491 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 268:80] - node _T_492 = mux(_T_489, _T_490, _T_491) @[axi4_to_ahb.scala 268:21] - buf_data_in <= _T_492 @[axi4_to_ahb.scala 268:15] - node _T_493 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 269:52] - node _T_494 = eq(_T_493, UInt<2>("h03")) @[axi4_to_ahb.scala 269:58] - node _T_495 = and(buf_aligned_in, _T_494) @[axi4_to_ahb.scala 269:38] - node _T_496 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 269:84] - node _T_497 = eq(_T_496, UInt<1>("h01")) @[axi4_to_ahb.scala 269:91] - node _T_498 = and(_T_495, _T_497) @[axi4_to_ahb.scala 269:71] - node _T_499 = bits(_T_498, 0, 0) @[axi4_to_ahb.scala 269:111] - node _T_500 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 269:142] - node _T_501 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 121:42] - node _T_502 = eq(_T_501, UInt<8>("h0ff")) @[axi4_to_ahb.scala 121:49] - node _T_503 = bits(_T_502, 0, 0) @[Bitwise.scala 72:15] - node _T_504 = mux(_T_503, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_505 = and(UInt<2>("h03"), _T_504) @[axi4_to_ahb.scala 121:25] - node _T_506 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 122:35] - node _T_507 = eq(_T_506, UInt<8>("h0f0")) @[axi4_to_ahb.scala 122:42] - node _T_508 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 122:64] - node _T_509 = eq(_T_508, UInt<8>("h0f")) @[axi4_to_ahb.scala 122:71] - node _T_510 = or(_T_507, _T_509) @[axi4_to_ahb.scala 122:55] - node _T_511 = bits(_T_510, 0, 0) @[Bitwise.scala 72:15] - node _T_512 = mux(_T_511, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_513 = and(UInt<2>("h02"), _T_512) @[axi4_to_ahb.scala 122:16] - node _T_514 = or(_T_505, _T_513) @[axi4_to_ahb.scala 121:64] - node _T_515 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:40] - node _T_516 = eq(_T_515, UInt<8>("h0c0")) @[axi4_to_ahb.scala 123:47] - node _T_517 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:69] - node _T_518 = eq(_T_517, UInt<6>("h030")) @[axi4_to_ahb.scala 123:76] - node _T_519 = or(_T_516, _T_518) @[axi4_to_ahb.scala 123:60] - node _T_520 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:98] - node _T_521 = eq(_T_520, UInt<8>("h0c")) @[axi4_to_ahb.scala 123:105] - node _T_522 = or(_T_519, _T_521) @[axi4_to_ahb.scala 123:89] - node _T_523 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:132] - node _T_524 = eq(_T_523, UInt<8>("h03")) @[axi4_to_ahb.scala 123:139] - node _T_525 = or(_T_522, _T_524) @[axi4_to_ahb.scala 123:123] - node _T_526 = bits(_T_525, 0, 0) @[Bitwise.scala 72:15] - node _T_527 = mux(_T_526, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_528 = and(UInt<2>("h01"), _T_527) @[axi4_to_ahb.scala 123:21] - node _T_529 = or(_T_514, _T_528) @[axi4_to_ahb.scala 122:93] - node _T_530 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 269:161] - node _T_531 = mux(_T_499, _T_529, _T_530) @[axi4_to_ahb.scala 269:21] - buf_size_in <= _T_531 @[axi4_to_ahb.scala 269:15] - node _T_532 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 270:32] - node _T_533 = eq(_T_532, UInt<1>("h00")) @[axi4_to_ahb.scala 270:39] - node _T_534 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 271:17] - node _T_535 = eq(_T_534, UInt<1>("h00")) @[axi4_to_ahb.scala 271:24] - node _T_536 = or(_T_533, _T_535) @[axi4_to_ahb.scala 270:48] - node _T_537 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 271:47] - node _T_538 = eq(_T_537, UInt<2>("h01")) @[axi4_to_ahb.scala 271:54] - node _T_539 = or(_T_536, _T_538) @[axi4_to_ahb.scala 271:33] - node _T_540 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 271:86] - node _T_541 = eq(_T_540, UInt<2>("h02")) @[axi4_to_ahb.scala 271:93] - node _T_542 = or(_T_539, _T_541) @[axi4_to_ahb.scala 271:72] - node _T_543 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 272:18] - node _T_544 = eq(_T_543, UInt<2>("h03")) @[axi4_to_ahb.scala 272:25] - node _T_545 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:55] - node _T_546 = eq(_T_545, UInt<2>("h03")) @[axi4_to_ahb.scala 272:62] - node _T_547 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:90] - node _T_548 = eq(_T_547, UInt<4>("h0c")) @[axi4_to_ahb.scala 272:97] - node _T_549 = or(_T_546, _T_548) @[axi4_to_ahb.scala 272:74] - node _T_550 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:125] - node _T_551 = eq(_T_550, UInt<6>("h030")) @[axi4_to_ahb.scala 272:132] - node _T_552 = or(_T_549, _T_551) @[axi4_to_ahb.scala 272:109] - node _T_553 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:161] - node _T_554 = eq(_T_553, UInt<8>("h0c0")) @[axi4_to_ahb.scala 272:168] - node _T_555 = or(_T_552, _T_554) @[axi4_to_ahb.scala 272:145] - node _T_556 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 273:21] - node _T_557 = eq(_T_556, UInt<4>("h0f")) @[axi4_to_ahb.scala 273:28] - node _T_558 = or(_T_555, _T_557) @[axi4_to_ahb.scala 272:181] - node _T_559 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 273:56] - node _T_560 = eq(_T_559, UInt<8>("h0f0")) @[axi4_to_ahb.scala 273:63] - node _T_561 = or(_T_558, _T_560) @[axi4_to_ahb.scala 273:40] - node _T_562 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 273:92] - node _T_563 = eq(_T_562, UInt<8>("h0ff")) @[axi4_to_ahb.scala 273:99] - node _T_564 = or(_T_561, _T_563) @[axi4_to_ahb.scala 273:76] - node _T_565 = and(_T_544, _T_564) @[axi4_to_ahb.scala 272:38] - node _T_566 = or(_T_542, _T_565) @[axi4_to_ahb.scala 271:106] - buf_aligned_in <= _T_566 @[axi4_to_ahb.scala 270:18] - node _T_567 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 275:43] - node _T_568 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 275:62] - node _T_569 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 275:87] - node _T_570 = cat(_T_568, _T_569) @[Cat.scala 29:58] - node _T_571 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 275:108] - node _T_572 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 275:133] - node _T_573 = cat(_T_571, _T_572) @[Cat.scala 29:58] - node _T_574 = mux(_T_567, _T_570, _T_573) @[axi4_to_ahb.scala 275:26] - io.ahb.out.haddr <= _T_574 @[axi4_to_ahb.scala 275:20] - node _T_575 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 276:43] - node _T_576 = bits(buf_aligned_in, 0, 0) @[Bitwise.scala 72:15] - node _T_577 = mux(_T_576, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_578 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 276:94] - node _T_579 = and(_T_577, _T_578) @[axi4_to_ahb.scala 276:81] - node _T_580 = cat(UInt<1>("h00"), _T_579) @[Cat.scala 29:58] - node _T_581 = bits(buf_aligned, 0, 0) @[Bitwise.scala 72:15] - node _T_582 = mux(_T_581, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_583 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 276:148] - node _T_584 = and(_T_582, _T_583) @[axi4_to_ahb.scala 276:138] - node _T_585 = cat(UInt<1>("h00"), _T_584) @[Cat.scala 29:58] - node _T_586 = mux(_T_575, _T_580, _T_585) @[axi4_to_ahb.scala 276:26] - io.ahb.out.hsize <= _T_586 @[axi4_to_ahb.scala 276:20] - io.ahb.out.hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 278:21] - io.ahb.out.hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 279:24] - node _T_587 = bits(io.axi.ar.bits.prot, 2, 2) @[axi4_to_ahb.scala 280:57] - node _T_588 = eq(_T_587, UInt<1>("h00")) @[axi4_to_ahb.scala 280:37] - node _T_589 = cat(UInt<1>("h01"), _T_588) @[Cat.scala 29:58] - io.ahb.out.hprot <= _T_589 @[axi4_to_ahb.scala 280:20] - node _T_590 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 281:44] - node _T_591 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 281:59] - node _T_592 = eq(_T_591, UInt<1>("h01")) @[axi4_to_ahb.scala 281:66] - node _T_593 = mux(_T_590, _T_592, buf_write) @[axi4_to_ahb.scala 281:27] - io.ahb.out.hwrite <= _T_593 @[axi4_to_ahb.scala 281:21] - node _T_594 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 282:32] - io.ahb.out.hwdata <= _T_594 @[axi4_to_ahb.scala 282:21] - slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 284:15] - node _T_595 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 285:43] - node _T_596 = mux(_T_595, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 285:23] - node _T_597 = bits(slvbuf_error, 0, 0) @[Bitwise.scala 72:15] - node _T_598 = mux(_T_597, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_599 = and(_T_598, UInt<2>("h02")) @[axi4_to_ahb.scala 285:88] - node _T_600 = cat(_T_596, _T_599) @[Cat.scala 29:58] - slave_opc <= _T_600 @[axi4_to_ahb.scala 285:13] - node _T_601 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 286:41] - node _T_602 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 286:66] - node _T_603 = cat(_T_602, _T_602) @[Cat.scala 29:58] - node _T_604 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 286:91] - node _T_605 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 286:110] - node _T_606 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 286:131] - node _T_607 = mux(_T_604, _T_605, _T_606) @[axi4_to_ahb.scala 286:79] - node _T_608 = mux(_T_601, _T_603, _T_607) @[axi4_to_ahb.scala 286:21] - slave_rdata <= _T_608 @[axi4_to_ahb.scala 286:15] - node _T_609 = bits(slvbuf_tag, 2, 0) @[axi4_to_ahb.scala 287:26] - slave_tag <= _T_609 @[axi4_to_ahb.scala 287:13] - node _T_610 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 289:37] - node _T_611 = neq(_T_610, UInt<1>("h00")) @[axi4_to_ahb.scala 289:44] - node _T_612 = and(_T_611, io.ahb.in.hready) @[axi4_to_ahb.scala 289:56] - node _T_613 = and(_T_612, io.ahb.out.hwrite) @[axi4_to_ahb.scala 289:75] - last_addr_en <= _T_613 @[axi4_to_ahb.scala 289:16] - node _T_614 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 291:31] - node _T_615 = and(_T_614, master_ready) @[axi4_to_ahb.scala 291:49] - wrbuf_en <= _T_615 @[axi4_to_ahb.scala 291:12] - node _T_616 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 292:35] - node _T_617 = and(_T_616, master_ready) @[axi4_to_ahb.scala 292:52] - wrbuf_data_en <= _T_617 @[axi4_to_ahb.scala 292:17] - node _T_618 = and(master_valid, master_ready) @[axi4_to_ahb.scala 293:34] - node _T_619 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 293:62] - node _T_620 = eq(_T_619, UInt<1>("h01")) @[axi4_to_ahb.scala 293:69] - node _T_621 = and(_T_618, _T_620) @[axi4_to_ahb.scala 293:49] - wrbuf_cmd_sent <= _T_621 @[axi4_to_ahb.scala 293:18] - node _T_622 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 294:33] - node _T_623 = and(wrbuf_cmd_sent, _T_622) @[axi4_to_ahb.scala 294:31] - wrbuf_rst <= _T_623 @[axi4_to_ahb.scala 294:13] - node _T_624 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 296:36] - node _T_625 = and(wrbuf_vld, _T_624) @[axi4_to_ahb.scala 296:34] - node _T_626 = eq(_T_625, UInt<1>("h00")) @[axi4_to_ahb.scala 296:22] - node _T_627 = and(_T_626, master_ready) @[axi4_to_ahb.scala 296:53] - io.axi.aw.ready <= _T_627 @[axi4_to_ahb.scala 296:19] - node _T_628 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 297:40] - node _T_629 = and(wrbuf_data_vld, _T_628) @[axi4_to_ahb.scala 297:38] - node _T_630 = eq(_T_629, UInt<1>("h00")) @[axi4_to_ahb.scala 297:21] - node _T_631 = and(_T_630, master_ready) @[axi4_to_ahb.scala 297:57] - io.axi.w.ready <= _T_631 @[axi4_to_ahb.scala 297:18] - node _T_632 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 298:34] - node _T_633 = eq(_T_632, UInt<1>("h00")) @[axi4_to_ahb.scala 298:22] - node _T_634 = and(_T_633, master_ready) @[axi4_to_ahb.scala 298:52] - io.axi.ar.ready <= _T_634 @[axi4_to_ahb.scala 298:19] - io.axi.r.bits.last <= UInt<1>("h01") @[axi4_to_ahb.scala 299:22] - node _T_635 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 301:71] - node _T_636 = mux(_T_635, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 301:55] - node _T_637 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 301:91] - node _T_638 = and(_T_636, _T_637) @[axi4_to_ahb.scala 301:89] - reg _T_639 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 301:51] - _T_639 <= _T_638 @[axi4_to_ahb.scala 301:51] - wrbuf_vld <= _T_639 @[axi4_to_ahb.scala 301:21] - node _T_640 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 302:76] - node _T_641 = mux(_T_640, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 302:55] - node _T_642 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 302:102] - node _T_643 = and(_T_641, _T_642) @[axi4_to_ahb.scala 302:100] - reg _T_644 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 302:51] - _T_644 <= _T_643 @[axi4_to_ahb.scala 302:51] - wrbuf_data_vld <= _T_644 @[axi4_to_ahb.scala 302:21] - node _T_645 = bits(io.axi.aw.bits.id, 2, 0) @[axi4_to_ahb.scala 303:71] - node _T_646 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 303:105] - reg _T_647 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_646 : @[Reg.scala 28:19] - _T_647 <= _T_645 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - wrbuf_tag <= _T_647 @[axi4_to_ahb.scala 303:21] - node _T_648 = bits(io.axi.aw.bits.size, 2, 0) @[axi4_to_ahb.scala 304:73] - node _T_649 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 304:101] - reg _T_650 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_649 : @[Reg.scala 28:19] - _T_650 <= _T_648 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - wrbuf_size <= _T_650 @[axi4_to_ahb.scala 304:21] - node _T_651 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 305:61] - inst rvclkhdr_2 of rvclkhdr_861 @[lib.scala 368:23] - rvclkhdr_2.clock <= clock - rvclkhdr_2.reset <= reset - rvclkhdr_2.io.clk <= bus_clk @[lib.scala 370:18] - rvclkhdr_2.io.en <= _T_651 @[lib.scala 371:17] - rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_652 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_652 <= io.axi.aw.bits.addr @[lib.scala 374:16] - wrbuf_addr <= _T_652 @[axi4_to_ahb.scala 305:21] - node _T_653 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 306:65] - inst rvclkhdr_3 of rvclkhdr_862 @[lib.scala 368:23] - rvclkhdr_3.clock <= clock - rvclkhdr_3.reset <= reset - rvclkhdr_3.io.clk <= bus_clk @[lib.scala 370:18] - rvclkhdr_3.io.en <= _T_653 @[lib.scala 371:17] - rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_654 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_654 <= io.axi.w.bits.data @[lib.scala 374:16] - wrbuf_data <= _T_654 @[axi4_to_ahb.scala 306:21] - node _T_655 = bits(io.axi.w.bits.strb, 7, 0) @[axi4_to_ahb.scala 307:72] - node _T_656 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 307:105] - reg _T_657 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_656 : @[Reg.scala 28:19] - _T_657 <= _T_655 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - wrbuf_byteen <= _T_657 @[axi4_to_ahb.scala 307:21] - node _T_658 = bits(io.ahb.out.haddr, 31, 0) @[axi4_to_ahb.scala 308:71] - node _T_659 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 308:104] - reg _T_660 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_659 : @[Reg.scala 28:19] - _T_660 <= _T_658 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - last_bus_addr <= _T_660 @[axi4_to_ahb.scala 308:21] - node _T_661 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 309:89] - reg _T_662 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_661 : @[Reg.scala 28:19] - _T_662 <= buf_write_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_write <= _T_662 @[axi4_to_ahb.scala 309:21] - node _T_663 = bits(buf_tag_in, 2, 0) @[axi4_to_ahb.scala 310:64] - node _T_664 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 310:99] - reg _T_665 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_664 : @[Reg.scala 28:19] - _T_665 <= _T_663 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_tag <= _T_665 @[axi4_to_ahb.scala 310:21] - node _T_666 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 311:42] - node _T_667 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 311:61] - node _T_668 = bits(_T_667, 0, 0) @[axi4_to_ahb.scala 311:78] - inst rvclkhdr_4 of rvclkhdr_863 @[lib.scala 368:23] - rvclkhdr_4.clock <= clock - rvclkhdr_4.reset <= reset - rvclkhdr_4.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_4.io.en <= _T_668 @[lib.scala 371:17] - rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_669 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_669 <= _T_666 @[lib.scala 374:16] - buf_addr <= _T_669 @[axi4_to_ahb.scala 311:21] - node _T_670 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 312:65] - node _T_671 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 312:94] - reg _T_672 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_671 : @[Reg.scala 28:19] - _T_672 <= _T_670 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_size <= _T_672 @[axi4_to_ahb.scala 312:21] - node _T_673 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 313:91] - reg _T_674 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_673 : @[Reg.scala 28:19] - _T_674 <= buf_aligned_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_aligned <= _T_674 @[axi4_to_ahb.scala 313:21] - node _T_675 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 314:67] - node _T_676 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 314:96] - reg _T_677 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_676 : @[Reg.scala 28:19] - _T_677 <= _T_675 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_byteen <= _T_677 @[axi4_to_ahb.scala 314:21] - node _T_678 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 315:42] - node _T_679 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 315:66] - node _T_680 = bits(_T_679, 0, 0) @[axi4_to_ahb.scala 315:89] - inst rvclkhdr_5 of rvclkhdr_864 @[lib.scala 368:23] - rvclkhdr_5.clock <= clock - rvclkhdr_5.reset <= reset - rvclkhdr_5.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_5.io.en <= _T_680 @[lib.scala 371:17] - rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_681 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_681 <= _T_678 @[lib.scala 374:16] - buf_data <= _T_681 @[axi4_to_ahb.scala 315:21] - node _T_682 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 316:89] - reg _T_683 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_682 : @[Reg.scala 28:19] - _T_683 <= buf_write @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - slvbuf_write <= _T_683 @[axi4_to_ahb.scala 316:21] - node _T_684 = bits(buf_tag, 2, 0) @[axi4_to_ahb.scala 317:61] - node _T_685 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 317:99] - reg _T_686 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_685 : @[Reg.scala 28:19] - _T_686 <= _T_684 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - slvbuf_tag <= _T_686 @[axi4_to_ahb.scala 317:21] - node _T_687 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 318:99] - reg _T_688 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_687 : @[Reg.scala 28:19] - _T_688 <= slvbuf_error_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - slvbuf_error <= _T_688 @[axi4_to_ahb.scala 318:21] - node _T_689 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 319:72] - node _T_690 = mux(_T_689, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 319:56] - node _T_691 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 319:92] - node _T_692 = and(_T_690, _T_691) @[axi4_to_ahb.scala 319:90] - reg _T_693 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 319:52] - _T_693 <= _T_692 @[axi4_to_ahb.scala 319:52] - cmd_doneQ <= _T_693 @[axi4_to_ahb.scala 319:21] - node _T_694 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 320:71] - node _T_695 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 320:110] - reg _T_696 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_695 : @[Reg.scala 28:19] - _T_696 <= _T_694 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_cmd_byte_ptrQ <= _T_696 @[axi4_to_ahb.scala 320:21] - reg _T_697 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 321:52] - _T_697 <= io.ahb.in.hready @[axi4_to_ahb.scala 321:52] - ahb_hready_q <= _T_697 @[axi4_to_ahb.scala 321:21] - node _T_698 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 322:70] - reg _T_699 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 322:52] - _T_699 <= _T_698 @[axi4_to_ahb.scala 322:52] - ahb_htrans_q <= _T_699 @[axi4_to_ahb.scala 322:21] - reg _T_700 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 323:57] - _T_700 <= io.ahb.out.hwrite @[axi4_to_ahb.scala 323:57] - ahb_hwrite_q <= _T_700 @[axi4_to_ahb.scala 323:21] - reg _T_701 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 324:52] - _T_701 <= io.ahb.in.hresp @[axi4_to_ahb.scala 324:52] - ahb_hresp_q <= _T_701 @[axi4_to_ahb.scala 324:21] - node _T_702 = bits(io.ahb.in.hrdata, 63, 0) @[axi4_to_ahb.scala 325:74] - reg _T_703 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 325:57] - _T_703 <= _T_702 @[axi4_to_ahb.scala 325:57] - ahb_hrdata_q <= _T_703 @[axi4_to_ahb.scala 325:21] - node _T_704 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 327:43] - node _T_705 = or(_T_704, io.clk_override) @[axi4_to_ahb.scala 327:58] - node _T_706 = and(io.bus_clk_en, _T_705) @[axi4_to_ahb.scala 327:30] - buf_clken <= _T_706 @[axi4_to_ahb.scala 327:13] - node _T_707 = bits(io.ahb.out.htrans, 1, 1) @[axi4_to_ahb.scala 328:76] - node _T_708 = and(io.ahb.in.hready, _T_707) @[axi4_to_ahb.scala 328:57] - node _T_709 = or(_T_708, io.clk_override) @[axi4_to_ahb.scala 328:81] - node _T_710 = and(io.bus_clk_en, _T_709) @[axi4_to_ahb.scala 328:36] - ahbm_addr_clken <= _T_710 @[axi4_to_ahb.scala 328:19] - node _T_711 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 329:50] - node _T_712 = or(_T_711, io.clk_override) @[axi4_to_ahb.scala 329:60] - node _T_713 = and(io.bus_clk_en, _T_712) @[axi4_to_ahb.scala 329:36] - ahbm_data_clken <= _T_713 @[axi4_to_ahb.scala 329:19] - inst rvclkhdr_6 of rvclkhdr_865 @[lib.scala 343:22] - rvclkhdr_6.clock <= clock - rvclkhdr_6.reset <= reset - rvclkhdr_6.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_6.io.en <= buf_clken @[lib.scala 345:16] - rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - buf_clk <= rvclkhdr_6.io.l1clk @[axi4_to_ahb.scala 332:12] - inst rvclkhdr_7 of rvclkhdr_866 @[lib.scala 343:22] - rvclkhdr_7.clock <= clock - rvclkhdr_7.reset <= reset - rvclkhdr_7.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_7.io.en <= io.bus_clk_en @[lib.scala 345:16] - rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahbm_clk <= rvclkhdr_7.io.l1clk @[axi4_to_ahb.scala 333:12] - inst rvclkhdr_8 of rvclkhdr_867 @[lib.scala 343:22] - rvclkhdr_8.clock <= clock - rvclkhdr_8.reset <= reset - rvclkhdr_8.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_8.io.en <= ahbm_addr_clken @[lib.scala 345:16] - rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahbm_addr_clk <= rvclkhdr_8.io.l1clk @[axi4_to_ahb.scala 334:17] - inst rvclkhdr_9 of rvclkhdr_868 @[lib.scala 343:22] - rvclkhdr_9.clock <= clock - rvclkhdr_9.reset <= reset - rvclkhdr_9.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_9.io.en <= ahbm_data_clken @[lib.scala 345:16] - rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahbm_data_clk <= rvclkhdr_9.io.l1clk @[axi4_to_ahb.scala 335:17] - - extmodule gated_latch_869 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_869 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_869 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_870 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_870 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_870 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_871 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_871 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_871 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_872 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_872 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_872 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_873 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_873 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_873 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_874 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_874 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_874 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_875 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_875 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_875 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_876 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_876 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_876 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_877 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_877 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_877 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_878 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_878 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_878 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - module axi4_to_ahb_2 : - input clock : Clock - input reset : AsyncReset - output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ahb : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}} - - wire buf_rst : UInt<1> - buf_rst <= UInt<1>("h00") - buf_rst <= UInt<1>("h00") @[axi4_to_ahb.scala 21:11] - io.ahb.out.htrans <= UInt<1>("h00") @[axi4_to_ahb.scala 22:21] - wire buf_state_en : UInt<1> - buf_state_en <= UInt<1>("h00") - wire ahbm_clk : Clock @[axi4_to_ahb.scala 24:22] - wire ahbm_addr_clk : Clock @[axi4_to_ahb.scala 25:27] - wire ahbm_data_clk : Clock @[axi4_to_ahb.scala 26:27] - wire buf_state : UInt<3> - buf_state <= UInt<3>("h00") - wire buf_nxtstate : UInt<3> - buf_nxtstate <= UInt<3>("h00") - node _T = bits(buf_state_en, 0, 0) @[axi4_to_ahb.scala 30:70] - node _T_1 = mux(_T, buf_nxtstate, buf_state) @[axi4_to_ahb.scala 30:50] - node _T_2 = eq(buf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 30:108] - node _T_3 = bits(_T_2, 0, 0) @[Bitwise.scala 72:15] - node _T_4 = mux(_T_3, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_5 = and(_T_1, _T_4) @[axi4_to_ahb.scala 30:98] - reg _T_6 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 30:45] - _T_6 <= _T_5 @[axi4_to_ahb.scala 30:45] - buf_state <= _T_6 @[axi4_to_ahb.scala 30:13] - wire slave_valid : UInt<1> - slave_valid <= UInt<1>("h00") - wire slave_ready : UInt<1> - slave_ready <= UInt<1>("h00") - wire slave_tag : UInt<3> - slave_tag <= UInt<3>("h00") - wire slave_rdata : UInt<64> - slave_rdata <= UInt<64>("h00") - wire slave_opc : UInt<4> - slave_opc <= UInt<4>("h00") - wire wrbuf_en : UInt<1> - wrbuf_en <= UInt<1>("h00") - wire wrbuf_data_en : UInt<1> - wrbuf_data_en <= UInt<1>("h00") - wire wrbuf_cmd_sent : UInt<1> - wrbuf_cmd_sent <= UInt<1>("h00") - wire wrbuf_rst : UInt<1> - wrbuf_rst <= UInt<1>("h00") - wire wrbuf_vld : UInt<1> - wrbuf_vld <= UInt<1>("h00") - wire wrbuf_data_vld : UInt<1> - wrbuf_data_vld <= UInt<1>("h00") - wire wrbuf_tag : UInt<3> - wrbuf_tag <= UInt<3>("h00") - wire wrbuf_size : UInt<3> - wrbuf_size <= UInt<3>("h00") - wire wrbuf_addr : UInt<32> - wrbuf_addr <= UInt<32>("h00") - wire wrbuf_data : UInt<64> - wrbuf_data <= UInt<64>("h00") - wire wrbuf_byteen : UInt<8> - wrbuf_byteen <= UInt<8>("h00") - wire bus_write_clk_en : UInt<1> - bus_write_clk_en <= UInt<1>("h00") - wire bus_clk : Clock @[axi4_to_ahb.scala 50:21] - wire bus_write_clk : Clock @[axi4_to_ahb.scala 51:27] - wire master_valid : UInt<1> - master_valid <= UInt<1>("h00") - wire master_ready : UInt<1> - master_ready <= UInt<1>("h00") - wire master_tag : UInt<3> - master_tag <= UInt<3>("h00") - wire master_addr : UInt<32> - master_addr <= UInt<32>("h00") - wire master_wdata : UInt<64> - master_wdata <= UInt<64>("h00") - wire master_size : UInt<3> - master_size <= UInt<3>("h00") - wire master_opc : UInt<3> - master_opc <= UInt<3>("h00") - wire master_byteen : UInt<8> - master_byteen <= UInt<8>("h00") - wire buf_addr : UInt<32> - buf_addr <= UInt<32>("h00") - wire buf_size : UInt<2> - buf_size <= UInt<2>("h00") - wire buf_write : UInt<1> - buf_write <= UInt<1>("h00") - wire buf_byteen : UInt<8> - buf_byteen <= UInt<8>("h00") - wire buf_aligned : UInt<1> - buf_aligned <= UInt<1>("h00") - wire buf_data : UInt<64> - buf_data <= UInt<64>("h00") - wire buf_tag : UInt<3> - buf_tag <= UInt<3>("h00") - wire buf_tag_in : UInt<3> - buf_tag_in <= UInt<3>("h00") - wire buf_addr_in : UInt<32> - buf_addr_in <= UInt<32>("h00") - wire buf_byteen_in : UInt<8> - buf_byteen_in <= UInt<8>("h00") - wire buf_data_in : UInt<64> - buf_data_in <= UInt<64>("h00") - wire buf_write_in : UInt<1> - buf_write_in <= UInt<1>("h00") - wire buf_aligned_in : UInt<1> - buf_aligned_in <= UInt<1>("h00") - wire buf_size_in : UInt<3> - buf_size_in <= UInt<3>("h00") - wire buf_wr_en : UInt<1> - buf_wr_en <= UInt<1>("h00") - wire buf_data_wr_en : UInt<1> - buf_data_wr_en <= UInt<1>("h00") - wire slvbuf_error_en : UInt<1> - slvbuf_error_en <= UInt<1>("h00") - wire wr_cmd_vld : UInt<1> - wr_cmd_vld <= UInt<1>("h00") - wire cmd_done_rst : UInt<1> - cmd_done_rst <= UInt<1>("h00") - wire cmd_done : UInt<1> - cmd_done <= UInt<1>("h00") - wire cmd_doneQ : UInt<1> - cmd_doneQ <= UInt<1>("h00") - wire trxn_done : UInt<1> - trxn_done <= UInt<1>("h00") - wire buf_cmd_byte_ptr : UInt<3> - buf_cmd_byte_ptr <= UInt<3>("h00") - wire buf_cmd_byte_ptrQ : UInt<3> - buf_cmd_byte_ptrQ <= UInt<3>("h00") - wire buf_cmd_nxtbyte_ptr : UInt<3> - buf_cmd_nxtbyte_ptr <= UInt<3>("h00") - wire buf_cmd_byte_ptr_en : UInt<1> - buf_cmd_byte_ptr_en <= UInt<1>("h00") - wire found : UInt<1> - found <= UInt<1>("h00") - wire slave_valid_pre : UInt<1> - slave_valid_pre <= UInt<1>("h00") - wire ahb_hready_q : UInt<1> - ahb_hready_q <= UInt<1>("h00") - wire ahb_hresp_q : UInt<1> - ahb_hresp_q <= UInt<1>("h00") - wire ahb_htrans_q : UInt<2> - ahb_htrans_q <= UInt<2>("h00") - wire ahb_hwrite_q : UInt<1> - ahb_hwrite_q <= UInt<1>("h00") - wire ahb_hrdata_q : UInt<64> - ahb_hrdata_q <= UInt<64>("h00") - wire slvbuf_write : UInt<1> - slvbuf_write <= UInt<1>("h00") - wire slvbuf_error : UInt<1> - slvbuf_error <= UInt<1>("h00") - wire slvbuf_tag : UInt<3> - slvbuf_tag <= UInt<3>("h00") - wire slvbuf_error_in : UInt<1> - slvbuf_error_in <= UInt<1>("h00") - wire slvbuf_wr_en : UInt<1> - slvbuf_wr_en <= UInt<1>("h00") - wire bypass_en : UInt<1> - bypass_en <= UInt<1>("h00") - wire rd_bypass_idle : UInt<1> - rd_bypass_idle <= UInt<1>("h00") - wire last_addr_en : UInt<1> - last_addr_en <= UInt<1>("h00") - wire last_bus_addr : UInt<32> - last_bus_addr <= UInt<32>("h00") - wire buf_clken : UInt<1> - buf_clken <= UInt<1>("h00") - wire slvbuf_clken : UInt<1> - slvbuf_clken <= UInt<1>("h00") - wire ahbm_addr_clken : UInt<1> - ahbm_addr_clken <= UInt<1>("h00") - wire ahbm_data_clken : UInt<1> - ahbm_data_clken <= UInt<1>("h00") - wire buf_clk : Clock @[axi4_to_ahb.scala 118:21] - node _T_7 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 139:27] - wr_cmd_vld <= _T_7 @[axi4_to_ahb.scala 139:14] - node _T_8 = or(wr_cmd_vld, io.axi.ar.valid) @[axi4_to_ahb.scala 140:30] - master_valid <= _T_8 @[axi4_to_ahb.scala 140:16] - node _T_9 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 141:38] - node _T_10 = bits(wrbuf_tag, 2, 0) @[axi4_to_ahb.scala 141:51] - node _T_11 = bits(io.axi.ar.bits.id, 2, 0) @[axi4_to_ahb.scala 141:82] - node _T_12 = mux(_T_9, _T_10, _T_11) @[axi4_to_ahb.scala 141:20] - master_tag <= _T_12 @[axi4_to_ahb.scala 141:14] - node _T_13 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 142:38] - node _T_14 = mux(_T_13, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 142:20] - master_opc <= _T_14 @[axi4_to_ahb.scala 142:14] - node _T_15 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 143:39] - node _T_16 = bits(wrbuf_addr, 31, 0) @[axi4_to_ahb.scala 143:53] - node _T_17 = bits(io.axi.ar.bits.addr, 31, 0) @[axi4_to_ahb.scala 143:81] - node _T_18 = mux(_T_15, _T_16, _T_17) @[axi4_to_ahb.scala 143:21] - master_addr <= _T_18 @[axi4_to_ahb.scala 143:15] - node _T_19 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 144:39] - node _T_20 = bits(wrbuf_size, 2, 0) @[axi4_to_ahb.scala 144:53] - node _T_21 = bits(io.axi.ar.bits.size, 2, 0) @[axi4_to_ahb.scala 144:80] - node _T_22 = mux(_T_19, _T_20, _T_21) @[axi4_to_ahb.scala 144:21] - master_size <= _T_22 @[axi4_to_ahb.scala 144:15] - node _T_23 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 145:32] - master_byteen <= _T_23 @[axi4_to_ahb.scala 145:17] - node _T_24 = bits(wrbuf_data, 63, 0) @[axi4_to_ahb.scala 146:29] - master_wdata <= _T_24 @[axi4_to_ahb.scala 146:16] - node _T_25 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 149:33] - node _T_26 = bits(slave_opc, 3, 3) @[axi4_to_ahb.scala 149:58] - node _T_27 = and(_T_25, _T_26) @[axi4_to_ahb.scala 149:47] - io.axi.b.valid <= _T_27 @[axi4_to_ahb.scala 149:18] - node _T_28 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 150:38] - node _T_29 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 150:65] - node _T_30 = mux(_T_29, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 150:55] - node _T_31 = mux(_T_28, UInt<2>("h02"), _T_30) @[axi4_to_ahb.scala 150:28] - io.axi.b.bits.resp <= _T_31 @[axi4_to_ahb.scala 150:22] - node _T_32 = bits(slave_tag, 2, 0) @[axi4_to_ahb.scala 151:32] - io.axi.b.bits.id <= _T_32 @[axi4_to_ahb.scala 151:20] - node _T_33 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 153:33] - node _T_34 = bits(slave_opc, 3, 2) @[axi4_to_ahb.scala 153:59] - node _T_35 = eq(_T_34, UInt<1>("h00")) @[axi4_to_ahb.scala 153:66] - node _T_36 = and(_T_33, _T_35) @[axi4_to_ahb.scala 153:47] - io.axi.r.valid <= _T_36 @[axi4_to_ahb.scala 153:18] - node _T_37 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 154:38] - node _T_38 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 154:65] - node _T_39 = mux(_T_38, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 154:55] - node _T_40 = mux(_T_37, UInt<2>("h02"), _T_39) @[axi4_to_ahb.scala 154:28] - io.axi.r.bits.resp <= _T_40 @[axi4_to_ahb.scala 154:22] - node _T_41 = bits(slave_tag, 2, 0) @[axi4_to_ahb.scala 155:32] - io.axi.r.bits.id <= _T_41 @[axi4_to_ahb.scala 155:20] - node _T_42 = bits(slave_rdata, 63, 0) @[axi4_to_ahb.scala 156:36] - io.axi.r.bits.data <= _T_42 @[axi4_to_ahb.scala 156:22] - node _T_43 = and(io.axi.b.ready, io.axi.r.ready) @[axi4_to_ahb.scala 157:33] - slave_ready <= _T_43 @[axi4_to_ahb.scala 157:15] - node _T_44 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 160:57] - node _T_45 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 160:94] - node _T_46 = or(_T_44, _T_45) @[axi4_to_ahb.scala 160:76] - node _T_47 = and(io.bus_clk_en, _T_46) @[axi4_to_ahb.scala 160:37] - bus_write_clk_en <= _T_47 @[axi4_to_ahb.scala 160:20] - inst rvclkhdr of rvclkhdr_869 @[lib.scala 343:22] - rvclkhdr.clock <= clock - rvclkhdr.reset <= reset - rvclkhdr.io.clk <= clock @[lib.scala 344:17] - rvclkhdr.io.en <= io.bus_clk_en @[lib.scala 345:16] - rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - bus_clk <= rvclkhdr.io.l1clk @[axi4_to_ahb.scala 162:11] - node _T_48 = bits(bus_write_clk_en, 0, 0) @[axi4_to_ahb.scala 163:59] - inst rvclkhdr_1 of rvclkhdr_870 @[lib.scala 343:22] - rvclkhdr_1.clock <= clock - rvclkhdr_1.reset <= reset - rvclkhdr_1.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_1.io.en <= _T_48 @[lib.scala 345:16] - rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - bus_write_clk <= rvclkhdr_1.io.l1clk @[axi4_to_ahb.scala 163:17] - node _T_49 = eq(UInt<3>("h00"), buf_state) @[Conditional.scala 37:30] - when _T_49 : @[Conditional.scala 40:58] - master_ready <= UInt<1>("h01") @[axi4_to_ahb.scala 167:20] - node _T_50 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 168:34] - node _T_51 = eq(_T_50, UInt<1>("h01")) @[axi4_to_ahb.scala 168:41] - buf_write_in <= _T_51 @[axi4_to_ahb.scala 168:20] - node _T_52 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 169:46] - node _T_53 = mux(_T_52, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 169:26] - buf_nxtstate <= _T_53 @[axi4_to_ahb.scala 169:20] - node _T_54 = and(master_valid, UInt<1>("h01")) @[axi4_to_ahb.scala 170:36] - buf_state_en <= _T_54 @[axi4_to_ahb.scala 170:20] - buf_wr_en <= buf_state_en @[axi4_to_ahb.scala 171:17] - node _T_55 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 172:54] - node _T_56 = and(buf_state_en, _T_55) @[axi4_to_ahb.scala 172:38] - buf_data_wr_en <= _T_56 @[axi4_to_ahb.scala 172:22] - buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 173:27] - node _T_57 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 175:50] - node _T_58 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 175:94] - node _T_59 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_60 = tail(_T_59, 1) @[axi4_to_ahb.scala 135:52] - node _T_61 = mux(UInt<1>("h00"), _T_60, UInt<3>("h00")) @[axi4_to_ahb.scala 135:24] - node _T_62 = bits(_T_58, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_63 = geq(UInt<1>("h00"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_64 = and(_T_62, _T_63) @[axi4_to_ahb.scala 136:48] - node _T_65 = bits(_T_58, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_66 = geq(UInt<1>("h01"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_67 = and(_T_65, _T_66) @[axi4_to_ahb.scala 136:48] - node _T_68 = bits(_T_58, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_69 = geq(UInt<2>("h02"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_70 = and(_T_68, _T_69) @[axi4_to_ahb.scala 136:48] - node _T_71 = bits(_T_58, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_72 = geq(UInt<2>("h03"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_73 = and(_T_71, _T_72) @[axi4_to_ahb.scala 136:48] - node _T_74 = bits(_T_58, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_75 = geq(UInt<3>("h04"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_76 = and(_T_74, _T_75) @[axi4_to_ahb.scala 136:48] - node _T_77 = bits(_T_58, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_78 = geq(UInt<3>("h05"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_79 = and(_T_77, _T_78) @[axi4_to_ahb.scala 136:48] - node _T_80 = bits(_T_58, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_81 = geq(UInt<3>("h06"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_82 = and(_T_80, _T_81) @[axi4_to_ahb.scala 136:48] - node _T_83 = bits(_T_58, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_84 = geq(UInt<3>("h07"), _T_61) @[axi4_to_ahb.scala 136:62] - node _T_85 = and(_T_83, _T_84) @[axi4_to_ahb.scala 136:48] - node _T_86 = mux(_T_85, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_87 = mux(_T_82, UInt<3>("h06"), _T_86) @[Mux.scala 98:16] - node _T_88 = mux(_T_79, UInt<3>("h05"), _T_87) @[Mux.scala 98:16] - node _T_89 = mux(_T_76, UInt<3>("h04"), _T_88) @[Mux.scala 98:16] - node _T_90 = mux(_T_73, UInt<2>("h03"), _T_89) @[Mux.scala 98:16] - node _T_91 = mux(_T_70, UInt<2>("h02"), _T_90) @[Mux.scala 98:16] - node _T_92 = mux(_T_67, UInt<1>("h01"), _T_91) @[Mux.scala 98:16] - node _T_93 = mux(_T_64, UInt<1>("h00"), _T_92) @[Mux.scala 98:16] - node _T_94 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 175:124] - node _T_95 = mux(_T_57, _T_93, _T_94) @[axi4_to_ahb.scala 175:30] - buf_cmd_byte_ptr <= _T_95 @[axi4_to_ahb.scala 175:24] - bypass_en <= buf_state_en @[axi4_to_ahb.scala 176:17] - node _T_96 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 177:51] - node _T_97 = and(bypass_en, _T_96) @[axi4_to_ahb.scala 177:35] - rd_bypass_idle <= _T_97 @[axi4_to_ahb.scala 177:22] - node _T_98 = bits(bypass_en, 0, 0) @[Bitwise.scala 72:15] - node _T_99 = mux(_T_98, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_100 = and(_T_99, UInt<2>("h02")) @[axi4_to_ahb.scala 178:49] - io.ahb.out.htrans <= _T_100 @[axi4_to_ahb.scala 178:25] - skip @[Conditional.scala 40:58] - else : @[Conditional.scala 39:67] - node _T_101 = eq(UInt<3>("h01"), buf_state) @[Conditional.scala 37:30] - when _T_101 : @[Conditional.scala 39:67] - node _T_102 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 182:54] - node _T_103 = eq(_T_102, UInt<1>("h00")) @[axi4_to_ahb.scala 182:61] - node _T_104 = and(master_valid, _T_103) @[axi4_to_ahb.scala 182:41] - node _T_105 = bits(_T_104, 0, 0) @[axi4_to_ahb.scala 182:82] - node _T_106 = mux(_T_105, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 182:26] - buf_nxtstate <= _T_106 @[axi4_to_ahb.scala 182:20] - node _T_107 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 183:51] - node _T_108 = neq(_T_107, UInt<1>("h00")) @[axi4_to_ahb.scala 183:58] - node _T_109 = and(ahb_hready_q, _T_108) @[axi4_to_ahb.scala 183:36] - node _T_110 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 183:72] - node _T_111 = and(_T_109, _T_110) @[axi4_to_ahb.scala 183:70] - buf_state_en <= _T_111 @[axi4_to_ahb.scala 183:20] - node _T_112 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 184:34] - node _T_113 = and(buf_state_en, _T_112) @[axi4_to_ahb.scala 184:32] - cmd_done <= _T_113 @[axi4_to_ahb.scala 184:16] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 185:20] - node _T_114 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 186:52] - node _T_115 = neq(_T_114, UInt<1>("h00")) @[axi4_to_ahb.scala 186:59] - node _T_116 = and(ahb_hready_q, _T_115) @[axi4_to_ahb.scala 186:37] - node _T_117 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 186:73] - node _T_118 = and(_T_116, _T_117) @[axi4_to_ahb.scala 186:71] - node _T_119 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 186:122] - node _T_120 = eq(_T_119, UInt<1>("h00")) @[axi4_to_ahb.scala 186:129] - node _T_121 = and(master_valid, _T_120) @[axi4_to_ahb.scala 186:109] - node _T_122 = bits(_T_121, 0, 0) @[axi4_to_ahb.scala 186:150] - node _T_123 = mux(_T_122, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 186:94] - node _T_124 = eq(_T_123, UInt<3>("h06")) @[axi4_to_ahb.scala 186:174] - node _T_125 = and(_T_118, _T_124) @[axi4_to_ahb.scala 186:88] - master_ready <= _T_125 @[axi4_to_ahb.scala 186:20] - buf_wr_en <= master_ready @[axi4_to_ahb.scala 187:17] - node _T_126 = and(master_ready, master_valid) @[axi4_to_ahb.scala 188:33] - bypass_en <= _T_126 @[axi4_to_ahb.scala 188:17] - node _T_127 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 189:47] - node _T_128 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 189:62] - node _T_129 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 189:78] - node _T_130 = mux(_T_127, _T_128, _T_129) @[axi4_to_ahb.scala 189:30] - buf_cmd_byte_ptr <= _T_130 @[axi4_to_ahb.scala 189:24] - node _T_131 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 190:48] - node _T_132 = or(_T_131, bypass_en) @[axi4_to_ahb.scala 190:62] - node _T_133 = bits(_T_132, 0, 0) @[Bitwise.scala 72:15] - node _T_134 = mux(_T_133, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_135 = and(UInt<2>("h02"), _T_134) @[axi4_to_ahb.scala 190:36] - io.ahb.out.htrans <= _T_135 @[axi4_to_ahb.scala 190:25] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_136 = eq(UInt<3>("h06"), buf_state) @[Conditional.scala 37:30] - when _T_136 : @[Conditional.scala 39:67] - node _T_137 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 194:39] - node _T_138 = and(ahb_hready_q, _T_137) @[axi4_to_ahb.scala 194:37] - node _T_139 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 194:82] - node _T_140 = eq(_T_139, UInt<1>("h01")) @[axi4_to_ahb.scala 194:89] - node _T_141 = and(master_valid, _T_140) @[axi4_to_ahb.scala 194:70] - node _T_142 = not(_T_141) @[axi4_to_ahb.scala 194:55] - node _T_143 = and(_T_138, _T_142) @[axi4_to_ahb.scala 194:53] - master_ready <= _T_143 @[axi4_to_ahb.scala 194:20] - node _T_144 = and(master_valid, master_ready) @[axi4_to_ahb.scala 195:34] - node _T_145 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 195:62] - node _T_146 = eq(_T_145, UInt<1>("h00")) @[axi4_to_ahb.scala 195:69] - node _T_147 = and(_T_144, _T_146) @[axi4_to_ahb.scala 195:49] - buf_wr_en <= _T_147 @[axi4_to_ahb.scala 195:17] - node _T_148 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 196:45] - node _T_149 = and(master_valid, master_ready) @[axi4_to_ahb.scala 196:82] - node _T_150 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 196:110] - node _T_151 = eq(_T_150, UInt<1>("h00")) @[axi4_to_ahb.scala 196:117] - node _T_152 = and(_T_149, _T_151) @[axi4_to_ahb.scala 196:97] - node _T_153 = bits(_T_152, 0, 0) @[axi4_to_ahb.scala 196:138] - node _T_154 = mux(_T_153, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 196:67] - node _T_155 = mux(_T_148, UInt<3>("h07"), _T_154) @[axi4_to_ahb.scala 196:26] - buf_nxtstate <= _T_155 @[axi4_to_ahb.scala 196:20] - node _T_156 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 197:37] - buf_state_en <= _T_156 @[axi4_to_ahb.scala 197:20] - buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 198:22] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 199:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 200:23] - node _T_157 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 201:41] - node _T_158 = and(buf_state_en, _T_157) @[axi4_to_ahb.scala 201:39] - slave_valid_pre <= _T_158 @[axi4_to_ahb.scala 201:23] - node _T_159 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 202:34] - node _T_160 = and(buf_state_en, _T_159) @[axi4_to_ahb.scala 202:32] - cmd_done <= _T_160 @[axi4_to_ahb.scala 202:16] - node _T_161 = and(master_ready, master_valid) @[axi4_to_ahb.scala 203:33] - node _T_162 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 203:64] - node _T_163 = and(_T_161, _T_162) @[axi4_to_ahb.scala 203:48] - node _T_164 = and(_T_163, buf_state_en) @[axi4_to_ahb.scala 203:79] - bypass_en <= _T_164 @[axi4_to_ahb.scala 203:17] - node _T_165 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 204:47] - node _T_166 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 204:62] - node _T_167 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 204:78] - node _T_168 = mux(_T_165, _T_166, _T_167) @[axi4_to_ahb.scala 204:30] - buf_cmd_byte_ptr <= _T_168 @[axi4_to_ahb.scala 204:24] - node _T_169 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 205:63] - node _T_170 = and(_T_169, buf_state_en) @[axi4_to_ahb.scala 205:78] - node _T_171 = eq(_T_170, UInt<1>("h00")) @[axi4_to_ahb.scala 205:47] - node _T_172 = bits(_T_171, 0, 0) @[Bitwise.scala 72:15] - node _T_173 = mux(_T_172, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_174 = and(UInt<2>("h02"), _T_173) @[axi4_to_ahb.scala 205:36] - io.ahb.out.htrans <= _T_174 @[axi4_to_ahb.scala 205:25] - slvbuf_wr_en <= buf_wr_en @[axi4_to_ahb.scala 206:20] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_175 = eq(UInt<3>("h07"), buf_state) @[Conditional.scala 37:30] - when _T_175 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h03") @[axi4_to_ahb.scala 210:20] - node _T_176 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 211:51] - node _T_177 = neq(_T_176, UInt<1>("h00")) @[axi4_to_ahb.scala 211:58] - node _T_178 = and(ahb_hready_q, _T_177) @[axi4_to_ahb.scala 211:36] - node _T_179 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 211:72] - node _T_180 = and(_T_178, _T_179) @[axi4_to_ahb.scala 211:70] - buf_state_en <= _T_180 @[axi4_to_ahb.scala 211:20] - slave_valid_pre <= buf_state_en @[axi4_to_ahb.scala 212:23] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 213:20] - node _T_181 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 214:35] - buf_cmd_byte_ptr <= _T_181 @[axi4_to_ahb.scala 214:24] - node _T_182 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 215:51] - node _T_183 = bits(_T_182, 0, 0) @[Bitwise.scala 72:15] - node _T_184 = mux(_T_183, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_185 = and(UInt<2>("h02"), _T_184) @[axi4_to_ahb.scala 215:41] - io.ahb.out.htrans <= _T_185 @[axi4_to_ahb.scala 215:25] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_186 = eq(UInt<3>("h03"), buf_state) @[Conditional.scala 37:30] - when _T_186 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h05") @[axi4_to_ahb.scala 219:20] - node _T_187 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 220:37] - buf_state_en <= _T_187 @[axi4_to_ahb.scala 220:20] - buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 221:22] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 222:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 223:23] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 224:20] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_188 = eq(UInt<3>("h02"), buf_state) @[Conditional.scala 37:30] - when _T_188 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h04") @[axi4_to_ahb.scala 228:20] - node _T_189 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 229:33] - node _T_190 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 229:63] - node _T_191 = neq(_T_190, UInt<1>("h00")) @[axi4_to_ahb.scala 229:70] - node _T_192 = and(_T_189, _T_191) @[axi4_to_ahb.scala 229:48] - trxn_done <= _T_192 @[axi4_to_ahb.scala 229:17] - buf_state_en <= trxn_done @[axi4_to_ahb.scala 230:20] - buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 231:27] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 232:20] - node _T_193 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 233:47] - node _T_194 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 233:85] - node _T_195 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 233:103] - node _T_196 = add(_T_194, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_197 = tail(_T_196, 1) @[axi4_to_ahb.scala 135:52] - node _T_198 = mux(UInt<1>("h01"), _T_197, _T_194) @[axi4_to_ahb.scala 135:24] - node _T_199 = bits(_T_195, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_200 = geq(UInt<1>("h00"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_201 = and(_T_199, _T_200) @[axi4_to_ahb.scala 136:48] - node _T_202 = bits(_T_195, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_203 = geq(UInt<1>("h01"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_204 = and(_T_202, _T_203) @[axi4_to_ahb.scala 136:48] - node _T_205 = bits(_T_195, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_206 = geq(UInt<2>("h02"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_207 = and(_T_205, _T_206) @[axi4_to_ahb.scala 136:48] - node _T_208 = bits(_T_195, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_209 = geq(UInt<2>("h03"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_210 = and(_T_208, _T_209) @[axi4_to_ahb.scala 136:48] - node _T_211 = bits(_T_195, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_212 = geq(UInt<3>("h04"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_213 = and(_T_211, _T_212) @[axi4_to_ahb.scala 136:48] - node _T_214 = bits(_T_195, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_215 = geq(UInt<3>("h05"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_216 = and(_T_214, _T_215) @[axi4_to_ahb.scala 136:48] - node _T_217 = bits(_T_195, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_218 = geq(UInt<3>("h06"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_219 = and(_T_217, _T_218) @[axi4_to_ahb.scala 136:48] - node _T_220 = bits(_T_195, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_221 = geq(UInt<3>("h07"), _T_198) @[axi4_to_ahb.scala 136:62] - node _T_222 = and(_T_220, _T_221) @[axi4_to_ahb.scala 136:48] - node _T_223 = mux(_T_222, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_224 = mux(_T_219, UInt<3>("h06"), _T_223) @[Mux.scala 98:16] - node _T_225 = mux(_T_216, UInt<3>("h05"), _T_224) @[Mux.scala 98:16] - node _T_226 = mux(_T_213, UInt<3>("h04"), _T_225) @[Mux.scala 98:16] - node _T_227 = mux(_T_210, UInt<2>("h03"), _T_226) @[Mux.scala 98:16] - node _T_228 = mux(_T_207, UInt<2>("h02"), _T_227) @[Mux.scala 98:16] - node _T_229 = mux(_T_204, UInt<1>("h01"), _T_228) @[Mux.scala 98:16] - node _T_230 = mux(_T_201, UInt<1>("h00"), _T_229) @[Mux.scala 98:16] - node _T_231 = mux(_T_193, _T_230, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 233:30] - buf_cmd_byte_ptr <= _T_231 @[axi4_to_ahb.scala 233:24] - node _T_232 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 234:65] - node _T_233 = or(buf_aligned, _T_232) @[axi4_to_ahb.scala 234:44] - node _T_234 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 234:127] - node _T_235 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 234:145] - node _T_236 = add(_T_234, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_237 = tail(_T_236, 1) @[axi4_to_ahb.scala 135:52] - node _T_238 = mux(UInt<1>("h01"), _T_237, _T_234) @[axi4_to_ahb.scala 135:24] - node _T_239 = bits(_T_235, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_240 = geq(UInt<1>("h00"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_241 = and(_T_239, _T_240) @[axi4_to_ahb.scala 136:48] - node _T_242 = bits(_T_235, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_243 = geq(UInt<1>("h01"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_244 = and(_T_242, _T_243) @[axi4_to_ahb.scala 136:48] - node _T_245 = bits(_T_235, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_246 = geq(UInt<2>("h02"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_247 = and(_T_245, _T_246) @[axi4_to_ahb.scala 136:48] - node _T_248 = bits(_T_235, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_249 = geq(UInt<2>("h03"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_250 = and(_T_248, _T_249) @[axi4_to_ahb.scala 136:48] - node _T_251 = bits(_T_235, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_252 = geq(UInt<3>("h04"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_253 = and(_T_251, _T_252) @[axi4_to_ahb.scala 136:48] - node _T_254 = bits(_T_235, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_255 = geq(UInt<3>("h05"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_256 = and(_T_254, _T_255) @[axi4_to_ahb.scala 136:48] - node _T_257 = bits(_T_235, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_258 = geq(UInt<3>("h06"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_259 = and(_T_257, _T_258) @[axi4_to_ahb.scala 136:48] - node _T_260 = bits(_T_235, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_261 = geq(UInt<3>("h07"), _T_238) @[axi4_to_ahb.scala 136:62] - node _T_262 = and(_T_260, _T_261) @[axi4_to_ahb.scala 136:48] - node _T_263 = mux(_T_262, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_264 = mux(_T_259, UInt<3>("h06"), _T_263) @[Mux.scala 98:16] - node _T_265 = mux(_T_256, UInt<3>("h05"), _T_264) @[Mux.scala 98:16] - node _T_266 = mux(_T_253, UInt<3>("h04"), _T_265) @[Mux.scala 98:16] - node _T_267 = mux(_T_250, UInt<2>("h03"), _T_266) @[Mux.scala 98:16] - node _T_268 = mux(_T_247, UInt<2>("h02"), _T_267) @[Mux.scala 98:16] - node _T_269 = mux(_T_244, UInt<1>("h01"), _T_268) @[Mux.scala 98:16] - node _T_270 = mux(_T_241, UInt<1>("h00"), _T_269) @[Mux.scala 98:16] - node _T_271 = dshr(buf_byteen, _T_270) @[axi4_to_ahb.scala 234:92] - node _T_272 = bits(_T_271, 0, 0) @[axi4_to_ahb.scala 234:92] - node _T_273 = eq(_T_272, UInt<1>("h00")) @[axi4_to_ahb.scala 234:163] - node _T_274 = or(_T_233, _T_273) @[axi4_to_ahb.scala 234:79] - node _T_275 = and(trxn_done, _T_274) @[axi4_to_ahb.scala 234:29] - cmd_done <= _T_275 @[axi4_to_ahb.scala 234:16] - node _T_276 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 235:47] - node _T_277 = eq(_T_276, UInt<1>("h00")) @[axi4_to_ahb.scala 235:36] - node _T_278 = bits(_T_277, 0, 0) @[Bitwise.scala 72:15] - node _T_279 = mux(_T_278, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_280 = and(_T_279, UInt<2>("h02")) @[axi4_to_ahb.scala 235:61] - io.ahb.out.htrans <= _T_280 @[axi4_to_ahb.scala 235:25] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_281 = eq(UInt<3>("h04"), buf_state) @[Conditional.scala 37:30] - when _T_281 : @[Conditional.scala 39:67] - node _T_282 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 239:34] - node _T_283 = or(_T_282, ahb_hresp_q) @[axi4_to_ahb.scala 239:50] - buf_state_en <= _T_283 @[axi4_to_ahb.scala 239:20] - node _T_284 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 240:38] - node _T_285 = and(buf_state_en, _T_284) @[axi4_to_ahb.scala 240:36] - node _T_286 = and(_T_285, slave_ready) @[axi4_to_ahb.scala 240:51] - master_ready <= _T_286 @[axi4_to_ahb.scala 240:20] - node _T_287 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 241:42] - node _T_288 = or(ahb_hresp_q, _T_287) @[axi4_to_ahb.scala 241:40] - node _T_289 = and(master_valid, master_valid) @[axi4_to_ahb.scala 241:80] - node _T_290 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 241:111] - node _T_291 = eq(_T_290, UInt<1>("h01")) @[axi4_to_ahb.scala 241:117] - node _T_292 = bits(_T_291, 0, 0) @[axi4_to_ahb.scala 241:132] - node _T_293 = mux(_T_292, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 241:99] - node _T_294 = mux(_T_289, _T_293, UInt<3>("h00")) @[axi4_to_ahb.scala 241:65] - node _T_295 = mux(_T_288, UInt<3>("h05"), _T_294) @[axi4_to_ahb.scala 241:26] - buf_nxtstate <= _T_295 @[axi4_to_ahb.scala 241:20] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 242:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 243:23] - node _T_296 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 244:33] - node _T_297 = eq(_T_296, UInt<1>("h01")) @[axi4_to_ahb.scala 244:39] - buf_write_in <= _T_297 @[axi4_to_ahb.scala 244:20] - node _T_298 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 245:50] - node _T_299 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 245:78] - node _T_300 = or(_T_298, _T_299) @[axi4_to_ahb.scala 245:62] - node _T_301 = and(buf_state_en, _T_300) @[axi4_to_ahb.scala 245:33] - buf_wr_en <= _T_301 @[axi4_to_ahb.scala 245:17] - buf_data_wr_en <= buf_wr_en @[axi4_to_ahb.scala 246:22] - node _T_302 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 247:65] - node _T_303 = neq(_T_302, UInt<1>("h00")) @[axi4_to_ahb.scala 247:71] - node _T_304 = and(ahb_hready_q, _T_303) @[axi4_to_ahb.scala 247:50] - node _T_305 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 248:29] - node _T_306 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 248:85] - node _T_307 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 248:101] - node _T_308 = add(_T_306, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_309 = tail(_T_308, 1) @[axi4_to_ahb.scala 135:52] - node _T_310 = mux(UInt<1>("h01"), _T_309, _T_306) @[axi4_to_ahb.scala 135:24] - node _T_311 = bits(_T_307, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_312 = geq(UInt<1>("h00"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_313 = and(_T_311, _T_312) @[axi4_to_ahb.scala 136:48] - node _T_314 = bits(_T_307, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_315 = geq(UInt<1>("h01"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_316 = and(_T_314, _T_315) @[axi4_to_ahb.scala 136:48] - node _T_317 = bits(_T_307, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_318 = geq(UInt<2>("h02"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_319 = and(_T_317, _T_318) @[axi4_to_ahb.scala 136:48] - node _T_320 = bits(_T_307, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_321 = geq(UInt<2>("h03"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_322 = and(_T_320, _T_321) @[axi4_to_ahb.scala 136:48] - node _T_323 = bits(_T_307, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_324 = geq(UInt<3>("h04"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_325 = and(_T_323, _T_324) @[axi4_to_ahb.scala 136:48] - node _T_326 = bits(_T_307, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_327 = geq(UInt<3>("h05"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_328 = and(_T_326, _T_327) @[axi4_to_ahb.scala 136:48] - node _T_329 = bits(_T_307, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_330 = geq(UInt<3>("h06"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_331 = and(_T_329, _T_330) @[axi4_to_ahb.scala 136:48] - node _T_332 = bits(_T_307, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_333 = geq(UInt<3>("h07"), _T_310) @[axi4_to_ahb.scala 136:62] - node _T_334 = and(_T_332, _T_333) @[axi4_to_ahb.scala 136:48] - node _T_335 = mux(_T_334, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_336 = mux(_T_331, UInt<3>("h06"), _T_335) @[Mux.scala 98:16] - node _T_337 = mux(_T_328, UInt<3>("h05"), _T_336) @[Mux.scala 98:16] - node _T_338 = mux(_T_325, UInt<3>("h04"), _T_337) @[Mux.scala 98:16] - node _T_339 = mux(_T_322, UInt<2>("h03"), _T_338) @[Mux.scala 98:16] - node _T_340 = mux(_T_319, UInt<2>("h02"), _T_339) @[Mux.scala 98:16] - node _T_341 = mux(_T_316, UInt<1>("h01"), _T_340) @[Mux.scala 98:16] - node _T_342 = mux(_T_313, UInt<1>("h00"), _T_341) @[Mux.scala 98:16] - node _T_343 = dshr(buf_byteen, _T_342) @[axi4_to_ahb.scala 248:51] - node _T_344 = bits(_T_343, 0, 0) @[axi4_to_ahb.scala 248:51] - node _T_345 = eq(_T_344, UInt<1>("h00")) @[axi4_to_ahb.scala 248:116] - node _T_346 = or(_T_305, _T_345) @[axi4_to_ahb.scala 248:38] - node _T_347 = and(_T_304, _T_346) @[axi4_to_ahb.scala 247:80] - node _T_348 = or(ahb_hresp_q, _T_347) @[axi4_to_ahb.scala 247:34] - cmd_done <= _T_348 @[axi4_to_ahb.scala 247:16] - node _T_349 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 249:33] - node _T_350 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 249:64] - node _T_351 = and(_T_349, _T_350) @[axi4_to_ahb.scala 249:48] - bypass_en <= _T_351 @[axi4_to_ahb.scala 249:17] - node _T_352 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 250:48] - node _T_353 = eq(_T_352, UInt<1>("h00")) @[axi4_to_ahb.scala 250:37] - node _T_354 = or(_T_353, bypass_en) @[axi4_to_ahb.scala 250:61] - node _T_355 = bits(_T_354, 0, 0) @[Bitwise.scala 72:15] - node _T_356 = mux(_T_355, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_357 = and(_T_356, UInt<2>("h02")) @[axi4_to_ahb.scala 250:75] - io.ahb.out.htrans <= _T_357 @[axi4_to_ahb.scala 250:25] - node _T_358 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 251:55] - node _T_359 = and(buf_state_en, _T_358) @[axi4_to_ahb.scala 251:39] - slave_valid_pre <= _T_359 @[axi4_to_ahb.scala 251:23] - node _T_360 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 252:33] - node _T_361 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 252:63] - node _T_362 = neq(_T_361, UInt<1>("h00")) @[axi4_to_ahb.scala 252:69] - node _T_363 = and(_T_360, _T_362) @[axi4_to_ahb.scala 252:48] - trxn_done <= _T_363 @[axi4_to_ahb.scala 252:17] - node _T_364 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 253:40] - buf_cmd_byte_ptr_en <= _T_364 @[axi4_to_ahb.scala 253:27] - node _T_365 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 254:79] - node _T_366 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_367 = tail(_T_366, 1) @[axi4_to_ahb.scala 135:52] - node _T_368 = mux(UInt<1>("h00"), _T_367, UInt<3>("h00")) @[axi4_to_ahb.scala 135:24] - node _T_369 = bits(_T_365, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_370 = geq(UInt<1>("h00"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_371 = and(_T_369, _T_370) @[axi4_to_ahb.scala 136:48] - node _T_372 = bits(_T_365, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_373 = geq(UInt<1>("h01"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_374 = and(_T_372, _T_373) @[axi4_to_ahb.scala 136:48] - node _T_375 = bits(_T_365, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_376 = geq(UInt<2>("h02"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_377 = and(_T_375, _T_376) @[axi4_to_ahb.scala 136:48] - node _T_378 = bits(_T_365, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_379 = geq(UInt<2>("h03"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_380 = and(_T_378, _T_379) @[axi4_to_ahb.scala 136:48] - node _T_381 = bits(_T_365, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_382 = geq(UInt<3>("h04"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_383 = and(_T_381, _T_382) @[axi4_to_ahb.scala 136:48] - node _T_384 = bits(_T_365, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_385 = geq(UInt<3>("h05"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_386 = and(_T_384, _T_385) @[axi4_to_ahb.scala 136:48] - node _T_387 = bits(_T_365, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_388 = geq(UInt<3>("h06"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_389 = and(_T_387, _T_388) @[axi4_to_ahb.scala 136:48] - node _T_390 = bits(_T_365, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_391 = geq(UInt<3>("h07"), _T_368) @[axi4_to_ahb.scala 136:62] - node _T_392 = and(_T_390, _T_391) @[axi4_to_ahb.scala 136:48] - node _T_393 = mux(_T_392, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_394 = mux(_T_389, UInt<3>("h06"), _T_393) @[Mux.scala 98:16] - node _T_395 = mux(_T_386, UInt<3>("h05"), _T_394) @[Mux.scala 98:16] - node _T_396 = mux(_T_383, UInt<3>("h04"), _T_395) @[Mux.scala 98:16] - node _T_397 = mux(_T_380, UInt<2>("h03"), _T_396) @[Mux.scala 98:16] - node _T_398 = mux(_T_377, UInt<2>("h02"), _T_397) @[Mux.scala 98:16] - node _T_399 = mux(_T_374, UInt<1>("h01"), _T_398) @[Mux.scala 98:16] - node _T_400 = mux(_T_371, UInt<1>("h00"), _T_399) @[Mux.scala 98:16] - node _T_401 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 254:141] - node _T_402 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 254:157] - node _T_403 = add(_T_401, UInt<1>("h01")) @[axi4_to_ahb.scala 135:52] - node _T_404 = tail(_T_403, 1) @[axi4_to_ahb.scala 135:52] - node _T_405 = mux(UInt<1>("h01"), _T_404, _T_401) @[axi4_to_ahb.scala 135:24] - node _T_406 = bits(_T_402, 0, 0) @[axi4_to_ahb.scala 136:44] - node _T_407 = geq(UInt<1>("h00"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_408 = and(_T_406, _T_407) @[axi4_to_ahb.scala 136:48] - node _T_409 = bits(_T_402, 1, 1) @[axi4_to_ahb.scala 136:44] - node _T_410 = geq(UInt<1>("h01"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_411 = and(_T_409, _T_410) @[axi4_to_ahb.scala 136:48] - node _T_412 = bits(_T_402, 2, 2) @[axi4_to_ahb.scala 136:44] - node _T_413 = geq(UInt<2>("h02"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_414 = and(_T_412, _T_413) @[axi4_to_ahb.scala 136:48] - node _T_415 = bits(_T_402, 3, 3) @[axi4_to_ahb.scala 136:44] - node _T_416 = geq(UInt<2>("h03"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_417 = and(_T_415, _T_416) @[axi4_to_ahb.scala 136:48] - node _T_418 = bits(_T_402, 4, 4) @[axi4_to_ahb.scala 136:44] - node _T_419 = geq(UInt<3>("h04"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_420 = and(_T_418, _T_419) @[axi4_to_ahb.scala 136:48] - node _T_421 = bits(_T_402, 5, 5) @[axi4_to_ahb.scala 136:44] - node _T_422 = geq(UInt<3>("h05"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_423 = and(_T_421, _T_422) @[axi4_to_ahb.scala 136:48] - node _T_424 = bits(_T_402, 6, 6) @[axi4_to_ahb.scala 136:44] - node _T_425 = geq(UInt<3>("h06"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_426 = and(_T_424, _T_425) @[axi4_to_ahb.scala 136:48] - node _T_427 = bits(_T_402, 7, 7) @[axi4_to_ahb.scala 136:44] - node _T_428 = geq(UInt<3>("h07"), _T_405) @[axi4_to_ahb.scala 136:62] - node _T_429 = and(_T_427, _T_428) @[axi4_to_ahb.scala 136:48] - node _T_430 = mux(_T_429, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_431 = mux(_T_426, UInt<3>("h06"), _T_430) @[Mux.scala 98:16] - node _T_432 = mux(_T_423, UInt<3>("h05"), _T_431) @[Mux.scala 98:16] - node _T_433 = mux(_T_420, UInt<3>("h04"), _T_432) @[Mux.scala 98:16] - node _T_434 = mux(_T_417, UInt<2>("h03"), _T_433) @[Mux.scala 98:16] - node _T_435 = mux(_T_414, UInt<2>("h02"), _T_434) @[Mux.scala 98:16] - node _T_436 = mux(_T_411, UInt<1>("h01"), _T_435) @[Mux.scala 98:16] - node _T_437 = mux(_T_408, UInt<1>("h00"), _T_436) @[Mux.scala 98:16] - node _T_438 = mux(trxn_done, _T_437, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 254:97] - node _T_439 = mux(bypass_en, _T_400, _T_438) @[axi4_to_ahb.scala 254:30] - buf_cmd_byte_ptr <= _T_439 @[axi4_to_ahb.scala 254:24] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_440 = eq(UInt<3>("h05"), buf_state) @[Conditional.scala 37:30] - when _T_440 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 257:20] - buf_state_en <= slave_ready @[axi4_to_ahb.scala 258:20] - slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 259:23] - slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 260:23] - skip @[Conditional.scala 39:67] - cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 264:16] - node _T_441 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 265:33] - node _T_442 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 265:73] - node _T_443 = eq(_T_442, UInt<1>("h01")) @[axi4_to_ahb.scala 265:80] - node _T_444 = and(buf_aligned_in, _T_443) @[axi4_to_ahb.scala 265:60] - node _T_445 = bits(_T_444, 0, 0) @[axi4_to_ahb.scala 265:100] - node _T_446 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 265:132] - node _T_447 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 127:50] - node _T_448 = eq(_T_447, UInt<8>("h0ff")) @[axi4_to_ahb.scala 127:57] - node _T_449 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 127:81] - node _T_450 = eq(_T_449, UInt<8>("h0f")) @[axi4_to_ahb.scala 127:88] - node _T_451 = or(_T_448, _T_450) @[axi4_to_ahb.scala 127:70] - node _T_452 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 127:117] - node _T_453 = eq(_T_452, UInt<8>("h03")) @[axi4_to_ahb.scala 127:124] - node _T_454 = or(_T_451, _T_453) @[axi4_to_ahb.scala 127:106] - node _T_455 = bits(_T_454, 0, 0) @[Bitwise.scala 72:15] - node _T_456 = mux(_T_455, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_457 = and(UInt<3>("h00"), _T_456) @[axi4_to_ahb.scala 127:29] - node _T_458 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 128:35] - node _T_459 = eq(_T_458, UInt<8>("h0c")) @[axi4_to_ahb.scala 128:42] - node _T_460 = bits(_T_459, 0, 0) @[Bitwise.scala 72:15] - node _T_461 = mux(_T_460, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_462 = and(UInt<2>("h02"), _T_461) @[axi4_to_ahb.scala 128:15] - node _T_463 = or(_T_457, _T_462) @[axi4_to_ahb.scala 127:146] - node _T_464 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 129:36] - node _T_465 = eq(_T_464, UInt<8>("h0f0")) @[axi4_to_ahb.scala 129:43] - node _T_466 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 129:67] - node _T_467 = eq(_T_466, UInt<8>("h03")) @[axi4_to_ahb.scala 129:74] - node _T_468 = or(_T_465, _T_467) @[axi4_to_ahb.scala 129:56] - node _T_469 = bits(_T_468, 0, 0) @[Bitwise.scala 72:15] - node _T_470 = mux(_T_469, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_471 = and(UInt<3>("h04"), _T_470) @[axi4_to_ahb.scala 129:15] - node _T_472 = or(_T_463, _T_471) @[axi4_to_ahb.scala 128:63] - node _T_473 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 130:35] - node _T_474 = eq(_T_473, UInt<8>("h0c0")) @[axi4_to_ahb.scala 130:42] - node _T_475 = bits(_T_474, 0, 0) @[Bitwise.scala 72:15] - node _T_476 = mux(_T_475, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_477 = and(UInt<3>("h06"), _T_476) @[axi4_to_ahb.scala 130:15] - node _T_478 = or(_T_472, _T_477) @[axi4_to_ahb.scala 129:96] - node _T_479 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 131:33] - node _T_480 = eq(_T_479, UInt<8>("h0c0")) @[axi4_to_ahb.scala 131:40] - node _T_481 = bits(_T_480, 0, 0) @[Bitwise.scala 72:15] - node _T_482 = mux(_T_481, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_483 = and(UInt<3>("h06"), _T_482) @[axi4_to_ahb.scala 131:13] - node _T_484 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 265:152] - node _T_485 = mux(_T_445, _T_478, _T_484) @[axi4_to_ahb.scala 265:43] - node _T_486 = cat(_T_441, _T_485) @[Cat.scala 29:58] - buf_addr_in <= _T_486 @[axi4_to_ahb.scala 265:15] - node _T_487 = bits(master_tag, 2, 0) @[axi4_to_ahb.scala 266:27] - buf_tag_in <= _T_487 @[axi4_to_ahb.scala 266:14] - node _T_488 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 267:32] - buf_byteen_in <= _T_488 @[axi4_to_ahb.scala 267:17] - node _T_489 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 268:33] - node _T_490 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 268:59] - node _T_491 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 268:80] - node _T_492 = mux(_T_489, _T_490, _T_491) @[axi4_to_ahb.scala 268:21] - buf_data_in <= _T_492 @[axi4_to_ahb.scala 268:15] - node _T_493 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 269:52] - node _T_494 = eq(_T_493, UInt<2>("h03")) @[axi4_to_ahb.scala 269:58] - node _T_495 = and(buf_aligned_in, _T_494) @[axi4_to_ahb.scala 269:38] - node _T_496 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 269:84] - node _T_497 = eq(_T_496, UInt<1>("h01")) @[axi4_to_ahb.scala 269:91] - node _T_498 = and(_T_495, _T_497) @[axi4_to_ahb.scala 269:71] - node _T_499 = bits(_T_498, 0, 0) @[axi4_to_ahb.scala 269:111] - node _T_500 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 269:142] - node _T_501 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 121:42] - node _T_502 = eq(_T_501, UInt<8>("h0ff")) @[axi4_to_ahb.scala 121:49] - node _T_503 = bits(_T_502, 0, 0) @[Bitwise.scala 72:15] - node _T_504 = mux(_T_503, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_505 = and(UInt<2>("h03"), _T_504) @[axi4_to_ahb.scala 121:25] - node _T_506 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 122:35] - node _T_507 = eq(_T_506, UInt<8>("h0f0")) @[axi4_to_ahb.scala 122:42] - node _T_508 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 122:64] - node _T_509 = eq(_T_508, UInt<8>("h0f")) @[axi4_to_ahb.scala 122:71] - node _T_510 = or(_T_507, _T_509) @[axi4_to_ahb.scala 122:55] - node _T_511 = bits(_T_510, 0, 0) @[Bitwise.scala 72:15] - node _T_512 = mux(_T_511, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_513 = and(UInt<2>("h02"), _T_512) @[axi4_to_ahb.scala 122:16] - node _T_514 = or(_T_505, _T_513) @[axi4_to_ahb.scala 121:64] - node _T_515 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:40] - node _T_516 = eq(_T_515, UInt<8>("h0c0")) @[axi4_to_ahb.scala 123:47] - node _T_517 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:69] - node _T_518 = eq(_T_517, UInt<6>("h030")) @[axi4_to_ahb.scala 123:76] - node _T_519 = or(_T_516, _T_518) @[axi4_to_ahb.scala 123:60] - node _T_520 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:98] - node _T_521 = eq(_T_520, UInt<8>("h0c")) @[axi4_to_ahb.scala 123:105] - node _T_522 = or(_T_519, _T_521) @[axi4_to_ahb.scala 123:89] - node _T_523 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 123:132] - node _T_524 = eq(_T_523, UInt<8>("h03")) @[axi4_to_ahb.scala 123:139] - node _T_525 = or(_T_522, _T_524) @[axi4_to_ahb.scala 123:123] - node _T_526 = bits(_T_525, 0, 0) @[Bitwise.scala 72:15] - node _T_527 = mux(_T_526, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_528 = and(UInt<2>("h01"), _T_527) @[axi4_to_ahb.scala 123:21] - node _T_529 = or(_T_514, _T_528) @[axi4_to_ahb.scala 122:93] - node _T_530 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 269:161] - node _T_531 = mux(_T_499, _T_529, _T_530) @[axi4_to_ahb.scala 269:21] - buf_size_in <= _T_531 @[axi4_to_ahb.scala 269:15] - node _T_532 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 270:32] - node _T_533 = eq(_T_532, UInt<1>("h00")) @[axi4_to_ahb.scala 270:39] - node _T_534 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 271:17] - node _T_535 = eq(_T_534, UInt<1>("h00")) @[axi4_to_ahb.scala 271:24] - node _T_536 = or(_T_533, _T_535) @[axi4_to_ahb.scala 270:48] - node _T_537 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 271:47] - node _T_538 = eq(_T_537, UInt<2>("h01")) @[axi4_to_ahb.scala 271:54] - node _T_539 = or(_T_536, _T_538) @[axi4_to_ahb.scala 271:33] - node _T_540 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 271:86] - node _T_541 = eq(_T_540, UInt<2>("h02")) @[axi4_to_ahb.scala 271:93] - node _T_542 = or(_T_539, _T_541) @[axi4_to_ahb.scala 271:72] - node _T_543 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 272:18] - node _T_544 = eq(_T_543, UInt<2>("h03")) @[axi4_to_ahb.scala 272:25] - node _T_545 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:55] - node _T_546 = eq(_T_545, UInt<2>("h03")) @[axi4_to_ahb.scala 272:62] - node _T_547 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:90] - node _T_548 = eq(_T_547, UInt<4>("h0c")) @[axi4_to_ahb.scala 272:97] - node _T_549 = or(_T_546, _T_548) @[axi4_to_ahb.scala 272:74] - node _T_550 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:125] - node _T_551 = eq(_T_550, UInt<6>("h030")) @[axi4_to_ahb.scala 272:132] - node _T_552 = or(_T_549, _T_551) @[axi4_to_ahb.scala 272:109] - node _T_553 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:161] - node _T_554 = eq(_T_553, UInt<8>("h0c0")) @[axi4_to_ahb.scala 272:168] - node _T_555 = or(_T_552, _T_554) @[axi4_to_ahb.scala 272:145] - node _T_556 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 273:21] - node _T_557 = eq(_T_556, UInt<4>("h0f")) @[axi4_to_ahb.scala 273:28] - node _T_558 = or(_T_555, _T_557) @[axi4_to_ahb.scala 272:181] - node _T_559 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 273:56] - node _T_560 = eq(_T_559, UInt<8>("h0f0")) @[axi4_to_ahb.scala 273:63] - node _T_561 = or(_T_558, _T_560) @[axi4_to_ahb.scala 273:40] - node _T_562 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 273:92] - node _T_563 = eq(_T_562, UInt<8>("h0ff")) @[axi4_to_ahb.scala 273:99] - node _T_564 = or(_T_561, _T_563) @[axi4_to_ahb.scala 273:76] - node _T_565 = and(_T_544, _T_564) @[axi4_to_ahb.scala 272:38] - node _T_566 = or(_T_542, _T_565) @[axi4_to_ahb.scala 271:106] - buf_aligned_in <= _T_566 @[axi4_to_ahb.scala 270:18] - node _T_567 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 275:43] - node _T_568 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 275:62] - node _T_569 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 275:87] - node _T_570 = cat(_T_568, _T_569) @[Cat.scala 29:58] - node _T_571 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 275:108] - node _T_572 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 275:133] - node _T_573 = cat(_T_571, _T_572) @[Cat.scala 29:58] - node _T_574 = mux(_T_567, _T_570, _T_573) @[axi4_to_ahb.scala 275:26] - io.ahb.out.haddr <= _T_574 @[axi4_to_ahb.scala 275:20] - node _T_575 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 276:43] - node _T_576 = bits(buf_aligned_in, 0, 0) @[Bitwise.scala 72:15] - node _T_577 = mux(_T_576, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_578 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 276:94] - node _T_579 = and(_T_577, _T_578) @[axi4_to_ahb.scala 276:81] - node _T_580 = cat(UInt<1>("h00"), _T_579) @[Cat.scala 29:58] - node _T_581 = bits(buf_aligned, 0, 0) @[Bitwise.scala 72:15] - node _T_582 = mux(_T_581, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_583 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 276:148] - node _T_584 = and(_T_582, _T_583) @[axi4_to_ahb.scala 276:138] - node _T_585 = cat(UInt<1>("h00"), _T_584) @[Cat.scala 29:58] - node _T_586 = mux(_T_575, _T_580, _T_585) @[axi4_to_ahb.scala 276:26] - io.ahb.out.hsize <= _T_586 @[axi4_to_ahb.scala 276:20] - io.ahb.out.hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 278:21] - io.ahb.out.hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 279:24] - node _T_587 = bits(io.axi.ar.bits.prot, 2, 2) @[axi4_to_ahb.scala 280:57] - node _T_588 = eq(_T_587, UInt<1>("h00")) @[axi4_to_ahb.scala 280:37] - node _T_589 = cat(UInt<1>("h01"), _T_588) @[Cat.scala 29:58] - io.ahb.out.hprot <= _T_589 @[axi4_to_ahb.scala 280:20] - node _T_590 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 281:44] - node _T_591 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 281:59] - node _T_592 = eq(_T_591, UInt<1>("h01")) @[axi4_to_ahb.scala 281:66] - node _T_593 = mux(_T_590, _T_592, buf_write) @[axi4_to_ahb.scala 281:27] - io.ahb.out.hwrite <= _T_593 @[axi4_to_ahb.scala 281:21] - node _T_594 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 282:32] - io.ahb.out.hwdata <= _T_594 @[axi4_to_ahb.scala 282:21] - slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 284:15] - node _T_595 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 285:43] - node _T_596 = mux(_T_595, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 285:23] - node _T_597 = bits(slvbuf_error, 0, 0) @[Bitwise.scala 72:15] - node _T_598 = mux(_T_597, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_599 = and(_T_598, UInt<2>("h02")) @[axi4_to_ahb.scala 285:88] - node _T_600 = cat(_T_596, _T_599) @[Cat.scala 29:58] - slave_opc <= _T_600 @[axi4_to_ahb.scala 285:13] - node _T_601 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 286:41] - node _T_602 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 286:66] - node _T_603 = cat(_T_602, _T_602) @[Cat.scala 29:58] - node _T_604 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 286:91] - node _T_605 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 286:110] - node _T_606 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 286:131] - node _T_607 = mux(_T_604, _T_605, _T_606) @[axi4_to_ahb.scala 286:79] - node _T_608 = mux(_T_601, _T_603, _T_607) @[axi4_to_ahb.scala 286:21] - slave_rdata <= _T_608 @[axi4_to_ahb.scala 286:15] - node _T_609 = bits(slvbuf_tag, 2, 0) @[axi4_to_ahb.scala 287:26] - slave_tag <= _T_609 @[axi4_to_ahb.scala 287:13] - node _T_610 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 289:37] - node _T_611 = neq(_T_610, UInt<1>("h00")) @[axi4_to_ahb.scala 289:44] - node _T_612 = and(_T_611, io.ahb.in.hready) @[axi4_to_ahb.scala 289:56] - node _T_613 = and(_T_612, io.ahb.out.hwrite) @[axi4_to_ahb.scala 289:75] - last_addr_en <= _T_613 @[axi4_to_ahb.scala 289:16] - node _T_614 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 291:31] - node _T_615 = and(_T_614, master_ready) @[axi4_to_ahb.scala 291:49] - wrbuf_en <= _T_615 @[axi4_to_ahb.scala 291:12] - node _T_616 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 292:35] - node _T_617 = and(_T_616, master_ready) @[axi4_to_ahb.scala 292:52] - wrbuf_data_en <= _T_617 @[axi4_to_ahb.scala 292:17] - node _T_618 = and(master_valid, master_ready) @[axi4_to_ahb.scala 293:34] - node _T_619 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 293:62] - node _T_620 = eq(_T_619, UInt<1>("h01")) @[axi4_to_ahb.scala 293:69] - node _T_621 = and(_T_618, _T_620) @[axi4_to_ahb.scala 293:49] - wrbuf_cmd_sent <= _T_621 @[axi4_to_ahb.scala 293:18] - node _T_622 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 294:33] - node _T_623 = and(wrbuf_cmd_sent, _T_622) @[axi4_to_ahb.scala 294:31] - wrbuf_rst <= _T_623 @[axi4_to_ahb.scala 294:13] - node _T_624 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 296:36] - node _T_625 = and(wrbuf_vld, _T_624) @[axi4_to_ahb.scala 296:34] - node _T_626 = eq(_T_625, UInt<1>("h00")) @[axi4_to_ahb.scala 296:22] - node _T_627 = and(_T_626, master_ready) @[axi4_to_ahb.scala 296:53] - io.axi.aw.ready <= _T_627 @[axi4_to_ahb.scala 296:19] - node _T_628 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 297:40] - node _T_629 = and(wrbuf_data_vld, _T_628) @[axi4_to_ahb.scala 297:38] - node _T_630 = eq(_T_629, UInt<1>("h00")) @[axi4_to_ahb.scala 297:21] - node _T_631 = and(_T_630, master_ready) @[axi4_to_ahb.scala 297:57] - io.axi.w.ready <= _T_631 @[axi4_to_ahb.scala 297:18] - node _T_632 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 298:34] - node _T_633 = eq(_T_632, UInt<1>("h00")) @[axi4_to_ahb.scala 298:22] - node _T_634 = and(_T_633, master_ready) @[axi4_to_ahb.scala 298:52] - io.axi.ar.ready <= _T_634 @[axi4_to_ahb.scala 298:19] - io.axi.r.bits.last <= UInt<1>("h01") @[axi4_to_ahb.scala 299:22] - node _T_635 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 301:71] - node _T_636 = mux(_T_635, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 301:55] - node _T_637 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 301:91] - node _T_638 = and(_T_636, _T_637) @[axi4_to_ahb.scala 301:89] - reg _T_639 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 301:51] - _T_639 <= _T_638 @[axi4_to_ahb.scala 301:51] - wrbuf_vld <= _T_639 @[axi4_to_ahb.scala 301:21] - node _T_640 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 302:76] - node _T_641 = mux(_T_640, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 302:55] - node _T_642 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 302:102] - node _T_643 = and(_T_641, _T_642) @[axi4_to_ahb.scala 302:100] - reg _T_644 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 302:51] - _T_644 <= _T_643 @[axi4_to_ahb.scala 302:51] - wrbuf_data_vld <= _T_644 @[axi4_to_ahb.scala 302:21] - node _T_645 = bits(io.axi.aw.bits.id, 2, 0) @[axi4_to_ahb.scala 303:71] - node _T_646 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 303:105] - reg _T_647 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_646 : @[Reg.scala 28:19] - _T_647 <= _T_645 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - wrbuf_tag <= _T_647 @[axi4_to_ahb.scala 303:21] - node _T_648 = bits(io.axi.aw.bits.size, 2, 0) @[axi4_to_ahb.scala 304:73] - node _T_649 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 304:101] - reg _T_650 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_649 : @[Reg.scala 28:19] - _T_650 <= _T_648 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - wrbuf_size <= _T_650 @[axi4_to_ahb.scala 304:21] - node _T_651 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 305:61] - inst rvclkhdr_2 of rvclkhdr_871 @[lib.scala 368:23] - rvclkhdr_2.clock <= clock - rvclkhdr_2.reset <= reset - rvclkhdr_2.io.clk <= bus_clk @[lib.scala 370:18] - rvclkhdr_2.io.en <= _T_651 @[lib.scala 371:17] - rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_652 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_652 <= io.axi.aw.bits.addr @[lib.scala 374:16] - wrbuf_addr <= _T_652 @[axi4_to_ahb.scala 305:21] - node _T_653 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 306:65] - inst rvclkhdr_3 of rvclkhdr_872 @[lib.scala 368:23] - rvclkhdr_3.clock <= clock - rvclkhdr_3.reset <= reset - rvclkhdr_3.io.clk <= bus_clk @[lib.scala 370:18] - rvclkhdr_3.io.en <= _T_653 @[lib.scala 371:17] - rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_654 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_654 <= io.axi.w.bits.data @[lib.scala 374:16] - wrbuf_data <= _T_654 @[axi4_to_ahb.scala 306:21] - node _T_655 = bits(io.axi.w.bits.strb, 7, 0) @[axi4_to_ahb.scala 307:72] - node _T_656 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 307:105] - reg _T_657 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_656 : @[Reg.scala 28:19] - _T_657 <= _T_655 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - wrbuf_byteen <= _T_657 @[axi4_to_ahb.scala 307:21] - node _T_658 = bits(io.ahb.out.haddr, 31, 0) @[axi4_to_ahb.scala 308:71] - node _T_659 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 308:104] - reg _T_660 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_659 : @[Reg.scala 28:19] - _T_660 <= _T_658 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - last_bus_addr <= _T_660 @[axi4_to_ahb.scala 308:21] - node _T_661 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 309:89] - reg _T_662 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_661 : @[Reg.scala 28:19] - _T_662 <= buf_write_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_write <= _T_662 @[axi4_to_ahb.scala 309:21] - node _T_663 = bits(buf_tag_in, 2, 0) @[axi4_to_ahb.scala 310:64] - node _T_664 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 310:99] - reg _T_665 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_664 : @[Reg.scala 28:19] - _T_665 <= _T_663 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_tag <= _T_665 @[axi4_to_ahb.scala 310:21] - node _T_666 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 311:42] - node _T_667 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 311:61] - node _T_668 = bits(_T_667, 0, 0) @[axi4_to_ahb.scala 311:78] - inst rvclkhdr_4 of rvclkhdr_873 @[lib.scala 368:23] - rvclkhdr_4.clock <= clock - rvclkhdr_4.reset <= reset - rvclkhdr_4.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_4.io.en <= _T_668 @[lib.scala 371:17] - rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_669 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_669 <= _T_666 @[lib.scala 374:16] - buf_addr <= _T_669 @[axi4_to_ahb.scala 311:21] - node _T_670 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 312:65] - node _T_671 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 312:94] - reg _T_672 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_671 : @[Reg.scala 28:19] - _T_672 <= _T_670 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_size <= _T_672 @[axi4_to_ahb.scala 312:21] - node _T_673 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 313:91] - reg _T_674 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_673 : @[Reg.scala 28:19] - _T_674 <= buf_aligned_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_aligned <= _T_674 @[axi4_to_ahb.scala 313:21] - node _T_675 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 314:67] - node _T_676 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 314:96] - reg _T_677 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_676 : @[Reg.scala 28:19] - _T_677 <= _T_675 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_byteen <= _T_677 @[axi4_to_ahb.scala 314:21] - node _T_678 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 315:42] - node _T_679 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 315:66] - node _T_680 = bits(_T_679, 0, 0) @[axi4_to_ahb.scala 315:89] - inst rvclkhdr_5 of rvclkhdr_874 @[lib.scala 368:23] - rvclkhdr_5.clock <= clock - rvclkhdr_5.reset <= reset - rvclkhdr_5.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_5.io.en <= _T_680 @[lib.scala 371:17] - rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_681 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_681 <= _T_678 @[lib.scala 374:16] - buf_data <= _T_681 @[axi4_to_ahb.scala 315:21] - node _T_682 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 316:89] - reg _T_683 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_682 : @[Reg.scala 28:19] - _T_683 <= buf_write @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - slvbuf_write <= _T_683 @[axi4_to_ahb.scala 316:21] - node _T_684 = bits(buf_tag, 2, 0) @[axi4_to_ahb.scala 317:61] - node _T_685 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 317:99] - reg _T_686 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_685 : @[Reg.scala 28:19] - _T_686 <= _T_684 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - slvbuf_tag <= _T_686 @[axi4_to_ahb.scala 317:21] - node _T_687 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 318:99] - reg _T_688 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_687 : @[Reg.scala 28:19] - _T_688 <= slvbuf_error_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - slvbuf_error <= _T_688 @[axi4_to_ahb.scala 318:21] - node _T_689 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 319:72] - node _T_690 = mux(_T_689, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 319:56] - node _T_691 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 319:92] - node _T_692 = and(_T_690, _T_691) @[axi4_to_ahb.scala 319:90] - reg _T_693 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 319:52] - _T_693 <= _T_692 @[axi4_to_ahb.scala 319:52] - cmd_doneQ <= _T_693 @[axi4_to_ahb.scala 319:21] - node _T_694 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 320:71] - node _T_695 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 320:110] - reg _T_696 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_695 : @[Reg.scala 28:19] - _T_696 <= _T_694 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_cmd_byte_ptrQ <= _T_696 @[axi4_to_ahb.scala 320:21] - reg _T_697 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 321:52] - _T_697 <= io.ahb.in.hready @[axi4_to_ahb.scala 321:52] - ahb_hready_q <= _T_697 @[axi4_to_ahb.scala 321:21] - node _T_698 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 322:70] - reg _T_699 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 322:52] - _T_699 <= _T_698 @[axi4_to_ahb.scala 322:52] - ahb_htrans_q <= _T_699 @[axi4_to_ahb.scala 322:21] - reg _T_700 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 323:57] - _T_700 <= io.ahb.out.hwrite @[axi4_to_ahb.scala 323:57] - ahb_hwrite_q <= _T_700 @[axi4_to_ahb.scala 323:21] - reg _T_701 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 324:52] - _T_701 <= io.ahb.in.hresp @[axi4_to_ahb.scala 324:52] - ahb_hresp_q <= _T_701 @[axi4_to_ahb.scala 324:21] - node _T_702 = bits(io.ahb.in.hrdata, 63, 0) @[axi4_to_ahb.scala 325:74] - reg _T_703 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 325:57] - _T_703 <= _T_702 @[axi4_to_ahb.scala 325:57] - ahb_hrdata_q <= _T_703 @[axi4_to_ahb.scala 325:21] - node _T_704 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 327:43] - node _T_705 = or(_T_704, io.clk_override) @[axi4_to_ahb.scala 327:58] - node _T_706 = and(io.bus_clk_en, _T_705) @[axi4_to_ahb.scala 327:30] - buf_clken <= _T_706 @[axi4_to_ahb.scala 327:13] - node _T_707 = bits(io.ahb.out.htrans, 1, 1) @[axi4_to_ahb.scala 328:76] - node _T_708 = and(io.ahb.in.hready, _T_707) @[axi4_to_ahb.scala 328:57] - node _T_709 = or(_T_708, io.clk_override) @[axi4_to_ahb.scala 328:81] - node _T_710 = and(io.bus_clk_en, _T_709) @[axi4_to_ahb.scala 328:36] - ahbm_addr_clken <= _T_710 @[axi4_to_ahb.scala 328:19] - node _T_711 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 329:50] - node _T_712 = or(_T_711, io.clk_override) @[axi4_to_ahb.scala 329:60] - node _T_713 = and(io.bus_clk_en, _T_712) @[axi4_to_ahb.scala 329:36] - ahbm_data_clken <= _T_713 @[axi4_to_ahb.scala 329:19] - inst rvclkhdr_6 of rvclkhdr_875 @[lib.scala 343:22] - rvclkhdr_6.clock <= clock - rvclkhdr_6.reset <= reset - rvclkhdr_6.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_6.io.en <= buf_clken @[lib.scala 345:16] - rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - buf_clk <= rvclkhdr_6.io.l1clk @[axi4_to_ahb.scala 332:12] - inst rvclkhdr_7 of rvclkhdr_876 @[lib.scala 343:22] - rvclkhdr_7.clock <= clock - rvclkhdr_7.reset <= reset - rvclkhdr_7.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_7.io.en <= io.bus_clk_en @[lib.scala 345:16] - rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahbm_clk <= rvclkhdr_7.io.l1clk @[axi4_to_ahb.scala 333:12] - inst rvclkhdr_8 of rvclkhdr_877 @[lib.scala 343:22] - rvclkhdr_8.clock <= clock - rvclkhdr_8.reset <= reset - rvclkhdr_8.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_8.io.en <= ahbm_addr_clken @[lib.scala 345:16] - rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahbm_addr_clk <= rvclkhdr_8.io.l1clk @[axi4_to_ahb.scala 334:17] - inst rvclkhdr_9 of rvclkhdr_878 @[lib.scala 343:22] - rvclkhdr_9.clock <= clock - rvclkhdr_9.reset <= reset - rvclkhdr_9.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_9.io.en <= ahbm_data_clken @[lib.scala 345:16] - rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahbm_data_clk <= rvclkhdr_9.io.l1clk @[axi4_to_ahb.scala 335:17] - - extmodule gated_latch_879 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_879 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_879 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_880 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_880 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_880 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_881 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_881 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_881 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_882 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_882 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_882 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_883 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_883 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_883 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_884 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_884 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_884 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - module ahb_to_axi4 : - input clock : Clock - input reset : AsyncReset - output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ahb : {flip sig : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, flip hsel : UInt<1>, flip hreadyin : UInt<1>}} - - wire _T : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[ahb_to_axi4.scala 20:25] - _T.r.bits.last <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.r.bits.resp <= UInt<2>("h00") @[ahb_to_axi4.scala 20:25] - _T.r.bits.data <= UInt<64>("h00") @[ahb_to_axi4.scala 20:25] - _T.r.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.r.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.r.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.ar.bits.qos <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25] - _T.ar.bits.prot <= UInt<3>("h00") @[ahb_to_axi4.scala 20:25] - _T.ar.bits.cache <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25] - _T.ar.bits.lock <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.ar.bits.burst <= UInt<2>("h00") @[ahb_to_axi4.scala 20:25] - _T.ar.bits.size <= UInt<3>("h00") @[ahb_to_axi4.scala 20:25] - _T.ar.bits.len <= UInt<8>("h00") @[ahb_to_axi4.scala 20:25] - _T.ar.bits.region <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25] - _T.ar.bits.addr <= UInt<32>("h00") @[ahb_to_axi4.scala 20:25] - _T.ar.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.ar.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.ar.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.b.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.b.bits.resp <= UInt<2>("h00") @[ahb_to_axi4.scala 20:25] - _T.b.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.b.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.w.bits.last <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.w.bits.strb <= UInt<8>("h00") @[ahb_to_axi4.scala 20:25] - _T.w.bits.data <= UInt<64>("h00") @[ahb_to_axi4.scala 20:25] - _T.w.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.w.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.aw.bits.qos <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25] - _T.aw.bits.prot <= UInt<3>("h00") @[ahb_to_axi4.scala 20:25] - _T.aw.bits.cache <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25] - _T.aw.bits.lock <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.aw.bits.burst <= UInt<2>("h00") @[ahb_to_axi4.scala 20:25] - _T.aw.bits.size <= UInt<3>("h00") @[ahb_to_axi4.scala 20:25] - _T.aw.bits.len <= UInt<8>("h00") @[ahb_to_axi4.scala 20:25] - _T.aw.bits.region <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25] - _T.aw.bits.addr <= UInt<32>("h00") @[ahb_to_axi4.scala 20:25] - _T.aw.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.aw.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.aw.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] - _T.r.bits.last <= io.axi.r.bits.last @[ahb_to_axi4.scala 20:10] - _T.r.bits.resp <= io.axi.r.bits.resp @[ahb_to_axi4.scala 20:10] - _T.r.bits.data <= io.axi.r.bits.data @[ahb_to_axi4.scala 20:10] - _T.r.bits.id <= io.axi.r.bits.id @[ahb_to_axi4.scala 20:10] - _T.r.valid <= io.axi.r.valid @[ahb_to_axi4.scala 20:10] - io.axi.r.ready <= _T.r.ready @[ahb_to_axi4.scala 20:10] - io.axi.ar.bits.qos <= _T.ar.bits.qos @[ahb_to_axi4.scala 20:10] - io.axi.ar.bits.prot <= _T.ar.bits.prot @[ahb_to_axi4.scala 20:10] - io.axi.ar.bits.cache <= _T.ar.bits.cache @[ahb_to_axi4.scala 20:10] - io.axi.ar.bits.lock <= _T.ar.bits.lock @[ahb_to_axi4.scala 20:10] - io.axi.ar.bits.burst <= _T.ar.bits.burst @[ahb_to_axi4.scala 20:10] - io.axi.ar.bits.size <= _T.ar.bits.size @[ahb_to_axi4.scala 20:10] - io.axi.ar.bits.len <= _T.ar.bits.len @[ahb_to_axi4.scala 20:10] - io.axi.ar.bits.region <= _T.ar.bits.region @[ahb_to_axi4.scala 20:10] - io.axi.ar.bits.addr <= _T.ar.bits.addr @[ahb_to_axi4.scala 20:10] - io.axi.ar.bits.id <= _T.ar.bits.id @[ahb_to_axi4.scala 20:10] - io.axi.ar.valid <= _T.ar.valid @[ahb_to_axi4.scala 20:10] - _T.ar.ready <= io.axi.ar.ready @[ahb_to_axi4.scala 20:10] - _T.b.bits.id <= io.axi.b.bits.id @[ahb_to_axi4.scala 20:10] - _T.b.bits.resp <= io.axi.b.bits.resp @[ahb_to_axi4.scala 20:10] - _T.b.valid <= io.axi.b.valid @[ahb_to_axi4.scala 20:10] - io.axi.b.ready <= _T.b.ready @[ahb_to_axi4.scala 20:10] - io.axi.w.bits.last <= _T.w.bits.last @[ahb_to_axi4.scala 20:10] - io.axi.w.bits.strb <= _T.w.bits.strb @[ahb_to_axi4.scala 20:10] - io.axi.w.bits.data <= _T.w.bits.data @[ahb_to_axi4.scala 20:10] - io.axi.w.valid <= _T.w.valid @[ahb_to_axi4.scala 20:10] - _T.w.ready <= io.axi.w.ready @[ahb_to_axi4.scala 20:10] - io.axi.aw.bits.qos <= _T.aw.bits.qos @[ahb_to_axi4.scala 20:10] - io.axi.aw.bits.prot <= _T.aw.bits.prot @[ahb_to_axi4.scala 20:10] - io.axi.aw.bits.cache <= _T.aw.bits.cache @[ahb_to_axi4.scala 20:10] - io.axi.aw.bits.lock <= _T.aw.bits.lock @[ahb_to_axi4.scala 20:10] - io.axi.aw.bits.burst <= _T.aw.bits.burst @[ahb_to_axi4.scala 20:10] - io.axi.aw.bits.size <= _T.aw.bits.size @[ahb_to_axi4.scala 20:10] - io.axi.aw.bits.len <= _T.aw.bits.len @[ahb_to_axi4.scala 20:10] - io.axi.aw.bits.region <= _T.aw.bits.region @[ahb_to_axi4.scala 20:10] - io.axi.aw.bits.addr <= _T.aw.bits.addr @[ahb_to_axi4.scala 20:10] - io.axi.aw.bits.id <= _T.aw.bits.id @[ahb_to_axi4.scala 20:10] - io.axi.aw.valid <= _T.aw.valid @[ahb_to_axi4.scala 20:10] - _T.aw.ready <= io.axi.aw.ready @[ahb_to_axi4.scala 20:10] - wire master_wstrb : UInt<8> - master_wstrb <= UInt<8>("h00") - wire buf_state_en : UInt<1> - buf_state_en <= UInt<1>("h00") - wire buf_read_error_in : UInt<1> - buf_read_error_in <= UInt<1>("h00") - wire buf_read_error : UInt<1> - buf_read_error <= UInt<1>("h00") - wire buf_rdata : UInt<64> - buf_rdata <= UInt<64>("h00") - wire ahb_hready : UInt<1> - ahb_hready <= UInt<1>("h00") - wire ahb_hready_q : UInt<1> - ahb_hready_q <= UInt<1>("h00") - wire ahb_htrans_in : UInt<2> - ahb_htrans_in <= UInt<2>("h00") - wire ahb_htrans_q : UInt<2> - ahb_htrans_q <= UInt<2>("h00") - wire ahb_hsize_q : UInt<3> - ahb_hsize_q <= UInt<3>("h00") - wire ahb_hwrite_q : UInt<1> - ahb_hwrite_q <= UInt<1>("h00") - wire ahb_haddr_q : UInt<32> - ahb_haddr_q <= UInt<32>("h00") - wire ahb_hwdata_q : UInt<64> - ahb_hwdata_q <= UInt<64>("h00") - wire ahb_hresp_q : UInt<1> - ahb_hresp_q <= UInt<1>("h00") - wire buf_rdata_en : UInt<1> - buf_rdata_en <= UInt<1>("h00") - wire ahb_bus_addr_clk_en : UInt<1> - ahb_bus_addr_clk_en <= UInt<1>("h00") - wire buf_rdata_clk_en : UInt<1> - buf_rdata_clk_en <= UInt<1>("h00") - wire ahb_clk : Clock @[ahb_to_axi4.scala 43:33] - wire ahb_addr_clk : Clock @[ahb_to_axi4.scala 44:33] - wire buf_rdata_clk : Clock @[ahb_to_axi4.scala 45:33] - wire cmdbuf_wr_en : UInt<1> - cmdbuf_wr_en <= UInt<1>("h00") - wire cmdbuf_rst : UInt<1> - cmdbuf_rst <= UInt<1>("h00") - wire cmdbuf_full : UInt<1> - cmdbuf_full <= UInt<1>("h00") - wire cmdbuf_vld : UInt<1> - cmdbuf_vld <= UInt<1>("h00") - wire cmdbuf_write : UInt<1> - cmdbuf_write <= UInt<1>("h00") - wire cmdbuf_size : UInt<2> - cmdbuf_size <= UInt<2>("h00") - wire cmdbuf_wstrb : UInt<8> - cmdbuf_wstrb <= UInt<8>("h00") - wire cmdbuf_addr : UInt<32> - cmdbuf_addr <= UInt<32>("h00") - wire cmdbuf_wdata : UInt<64> - cmdbuf_wdata <= UInt<64>("h00") - wire bus_clk : Clock @[ahb_to_axi4.scala 57:33] - node _T_1 = bits(ahb_haddr_q, 31, 28) @[lib.scala 84:25] - node ahb_addr_in_dccm_region_nc = eq(_T_1, UInt<4>("h0f")) @[lib.scala 84:47] - node _T_2 = bits(ahb_haddr_q, 31, 16) @[lib.scala 87:14] - node ahb_addr_in_dccm = eq(_T_2, UInt<16>("h0f004")) @[lib.scala 87:29] - node _T_3 = bits(ahb_haddr_q, 31, 28) @[lib.scala 84:25] - node ahb_addr_in_iccm_region_nc = eq(_T_3, UInt<4>("h0e")) @[lib.scala 84:47] - node _T_4 = bits(ahb_haddr_q, 31, 16) @[lib.scala 87:14] - node ahb_addr_in_iccm = eq(_T_4, UInt<16>("h0ee00")) @[lib.scala 87:29] - node _T_5 = bits(ahb_haddr_q, 31, 28) @[lib.scala 84:25] - node ahb_addr_in_pic_region_nc = eq(_T_5, UInt<4>("h0f")) @[lib.scala 84:47] - node _T_6 = bits(ahb_haddr_q, 31, 15) @[lib.scala 87:14] - node ahb_addr_in_pic = eq(_T_6, UInt<17>("h01e018")) @[lib.scala 87:29] - wire buf_state : UInt<2> - buf_state <= UInt<2>("h00") - wire buf_nxtstate : UInt<2> - buf_nxtstate <= UInt<2>("h00") - buf_nxtstate <= UInt<2>("h00") @[ahb_to_axi4.scala 67:31] - buf_state_en <= UInt<1>("h00") @[ahb_to_axi4.scala 68:31] - buf_rdata_en <= UInt<1>("h00") @[ahb_to_axi4.scala 69:31] - buf_read_error_in <= UInt<1>("h00") @[ahb_to_axi4.scala 70:31] - cmdbuf_wr_en <= UInt<1>("h00") @[ahb_to_axi4.scala 71:31] - node _T_7 = eq(UInt<2>("h00"), buf_state) @[Conditional.scala 37:30] - when _T_7 : @[Conditional.scala 40:58] - node _T_8 = mux(io.ahb.sig.out.hwrite, UInt<2>("h01"), UInt<2>("h02")) @[ahb_to_axi4.scala 75:26] - buf_nxtstate <= _T_8 @[ahb_to_axi4.scala 75:20] - node _T_9 = bits(io.ahb.sig.out.htrans, 1, 1) @[ahb_to_axi4.scala 76:57] - node _T_10 = and(ahb_hready, _T_9) @[ahb_to_axi4.scala 76:34] - node _T_11 = and(_T_10, io.ahb.hsel) @[ahb_to_axi4.scala 76:61] - buf_state_en <= _T_11 @[ahb_to_axi4.scala 76:20] - skip @[Conditional.scala 40:58] - else : @[Conditional.scala 39:67] - node _T_12 = eq(UInt<2>("h01"), buf_state) @[Conditional.scala 37:30] - when _T_12 : @[Conditional.scala 39:67] - node _T_13 = bits(io.ahb.sig.out.htrans, 1, 0) @[ahb_to_axi4.scala 79:72] - node _T_14 = eq(_T_13, UInt<1>("h00")) @[ahb_to_axi4.scala 79:79] - node _T_15 = or(io.ahb.sig.in.hresp, _T_14) @[ahb_to_axi4.scala 79:48] - node _T_16 = eq(io.ahb.hsel, UInt<1>("h00")) @[ahb_to_axi4.scala 79:93] - node _T_17 = or(_T_15, _T_16) @[ahb_to_axi4.scala 79:91] - node _T_18 = bits(_T_17, 0, 0) @[ahb_to_axi4.scala 79:107] - node _T_19 = mux(io.ahb.sig.out.hwrite, UInt<2>("h01"), UInt<2>("h02")) @[ahb_to_axi4.scala 79:124] - node _T_20 = mux(_T_18, UInt<2>("h00"), _T_19) @[ahb_to_axi4.scala 79:26] - buf_nxtstate <= _T_20 @[ahb_to_axi4.scala 79:20] - node _T_21 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 80:24] - node _T_22 = or(_T_21, io.ahb.sig.in.hresp) @[ahb_to_axi4.scala 80:37] - buf_state_en <= _T_22 @[ahb_to_axi4.scala 80:20] - node _T_23 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 81:23] - node _T_24 = bits(io.ahb.sig.out.htrans, 1, 0) @[ahb_to_axi4.scala 81:85] - node _T_25 = eq(_T_24, UInt<2>("h01")) @[ahb_to_axi4.scala 81:92] - node _T_26 = and(_T_25, io.ahb.hsel) @[ahb_to_axi4.scala 81:110] - node _T_27 = or(io.ahb.sig.in.hresp, _T_26) @[ahb_to_axi4.scala 81:60] - node _T_28 = eq(_T_27, UInt<1>("h00")) @[ahb_to_axi4.scala 81:38] - node _T_29 = and(_T_23, _T_28) @[ahb_to_axi4.scala 81:36] - cmdbuf_wr_en <= _T_29 @[ahb_to_axi4.scala 81:20] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_30 = eq(UInt<2>("h02"), buf_state) @[Conditional.scala 37:30] - when _T_30 : @[Conditional.scala 39:67] - node _T_31 = mux(io.ahb.sig.in.hresp, UInt<2>("h00"), UInt<2>("h03")) @[ahb_to_axi4.scala 84:26] - buf_nxtstate <= _T_31 @[ahb_to_axi4.scala 84:20] - node _T_32 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 85:24] - node _T_33 = or(_T_32, io.ahb.sig.in.hresp) @[ahb_to_axi4.scala 85:37] - buf_state_en <= _T_33 @[ahb_to_axi4.scala 85:20] - node _T_34 = eq(io.ahb.sig.in.hresp, UInt<1>("h00")) @[ahb_to_axi4.scala 86:23] - node _T_35 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 86:46] - node _T_36 = and(_T_34, _T_35) @[ahb_to_axi4.scala 86:44] - cmdbuf_wr_en <= _T_36 @[ahb_to_axi4.scala 86:20] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_37 = eq(UInt<2>("h03"), buf_state) @[Conditional.scala 37:30] - when _T_37 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<2>("h00") @[ahb_to_axi4.scala 89:20] - node _T_38 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 90:40] - node _T_39 = and(io.axi.r.valid, _T_38) @[ahb_to_axi4.scala 90:38] - buf_state_en <= _T_39 @[ahb_to_axi4.scala 90:20] - buf_rdata_en <= buf_state_en @[ahb_to_axi4.scala 91:20] - node _T_40 = bits(io.axi.r.bits.resp, 1, 0) @[ahb_to_axi4.scala 92:61] - node _T_41 = orr(_T_40) @[ahb_to_axi4.scala 92:68] - node _T_42 = and(buf_state_en, _T_41) @[ahb_to_axi4.scala 92:41] - buf_read_error_in <= _T_42 @[ahb_to_axi4.scala 92:25] - skip @[Conditional.scala 39:67] - node _T_43 = bits(buf_state_en, 0, 0) @[ahb_to_axi4.scala 95:99] - reg _T_44 : UInt, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_43 : @[Reg.scala 28:19] - _T_44 <= buf_nxtstate @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_state <= _T_44 @[ahb_to_axi4.scala 95:31] - node _T_45 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 97:54] - node _T_46 = eq(_T_45, UInt<1>("h00")) @[ahb_to_axi4.scala 97:60] - node _T_47 = bits(_T_46, 0, 0) @[Bitwise.scala 72:15] - node _T_48 = mux(_T_47, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_49 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 97:92] - node _T_50 = dshl(UInt<1>("h01"), _T_49) @[ahb_to_axi4.scala 97:78] - node _T_51 = and(_T_48, _T_50) @[ahb_to_axi4.scala 97:70] - node _T_52 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 98:24] - node _T_53 = eq(_T_52, UInt<1>("h01")) @[ahb_to_axi4.scala 98:30] - node _T_54 = bits(_T_53, 0, 0) @[Bitwise.scala 72:15] - node _T_55 = mux(_T_54, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_56 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 98:62] - node _T_57 = dshl(UInt<2>("h03"), _T_56) @[ahb_to_axi4.scala 98:48] - node _T_58 = and(_T_55, _T_57) @[ahb_to_axi4.scala 98:40] - node _T_59 = or(_T_51, _T_58) @[ahb_to_axi4.scala 97:109] - node _T_60 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 99:24] - node _T_61 = eq(_T_60, UInt<2>("h02")) @[ahb_to_axi4.scala 99:30] - node _T_62 = bits(_T_61, 0, 0) @[Bitwise.scala 72:15] - node _T_63 = mux(_T_62, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_64 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 99:62] - node _T_65 = dshl(UInt<4>("h0f"), _T_64) @[ahb_to_axi4.scala 99:48] - node _T_66 = and(_T_63, _T_65) @[ahb_to_axi4.scala 99:40] - node _T_67 = or(_T_59, _T_66) @[ahb_to_axi4.scala 98:79] - node _T_68 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 100:24] - node _T_69 = eq(_T_68, UInt<2>("h03")) @[ahb_to_axi4.scala 100:30] - node _T_70 = bits(_T_69, 0, 0) @[Bitwise.scala 72:15] - node _T_71 = mux(_T_70, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_72 = and(_T_71, UInt<8>("h0ff")) @[ahb_to_axi4.scala 100:40] - node _T_73 = or(_T_67, _T_72) @[ahb_to_axi4.scala 99:79] - master_wstrb <= _T_73 @[ahb_to_axi4.scala 97:31] - node _T_74 = eq(ahb_hready_q, UInt<1>("h00")) @[ahb_to_axi4.scala 103:80] - node _T_75 = and(ahb_hresp_q, _T_74) @[ahb_to_axi4.scala 103:78] - node _T_76 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 103:98] - node _T_77 = eq(buf_state, UInt<2>("h00")) @[ahb_to_axi4.scala 103:124] - node _T_78 = or(_T_76, _T_77) @[ahb_to_axi4.scala 103:111] - node _T_79 = eq(buf_state, UInt<2>("h02")) @[ahb_to_axi4.scala 103:149] - node _T_80 = eq(buf_state, UInt<2>("h03")) @[ahb_to_axi4.scala 103:168] - node _T_81 = or(_T_79, _T_80) @[ahb_to_axi4.scala 103:156] - node _T_82 = eq(_T_81, UInt<1>("h00")) @[ahb_to_axi4.scala 103:137] - node _T_83 = and(_T_78, _T_82) @[ahb_to_axi4.scala 103:135] - node _T_84 = eq(buf_read_error, UInt<1>("h00")) @[ahb_to_axi4.scala 103:181] - node _T_85 = and(_T_83, _T_84) @[ahb_to_axi4.scala 103:179] - node _T_86 = mux(io.ahb.sig.in.hresp, _T_75, _T_85) @[ahb_to_axi4.scala 103:44] - io.ahb.sig.in.hready <= _T_86 @[ahb_to_axi4.scala 103:38] - node _T_87 = and(io.ahb.sig.in.hready, io.ahb.hreadyin) @[ahb_to_axi4.scala 104:55] - ahb_hready <= _T_87 @[ahb_to_axi4.scala 104:31] - node _T_88 = bits(io.ahb.hsel, 0, 0) @[Bitwise.scala 72:15] - node _T_89 = mux(_T_88, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_90 = bits(io.ahb.sig.out.htrans, 1, 0) @[ahb_to_axi4.scala 105:77] - node _T_91 = and(_T_89, _T_90) @[ahb_to_axi4.scala 105:54] - ahb_htrans_in <= _T_91 @[ahb_to_axi4.scala 105:31] - node _T_92 = bits(buf_rdata, 63, 0) @[ahb_to_axi4.scala 106:50] - io.ahb.sig.in.hrdata <= _T_92 @[ahb_to_axi4.scala 106:38] - node _T_93 = bits(ahb_htrans_q, 1, 0) @[ahb_to_axi4.scala 107:55] - node _T_94 = neq(_T_93, UInt<1>("h00")) @[ahb_to_axi4.scala 107:61] - node _T_95 = neq(buf_state, UInt<2>("h00")) @[ahb_to_axi4.scala 107:83] - node _T_96 = and(_T_94, _T_95) @[ahb_to_axi4.scala 107:70] - node _T_97 = or(ahb_addr_in_dccm, ahb_addr_in_iccm) @[ahb_to_axi4.scala 108:26] - node _T_98 = eq(_T_97, UInt<1>("h00")) @[ahb_to_axi4.scala 108:7] - node _T_99 = and(ahb_addr_in_dccm, ahb_hwrite_q) @[ahb_to_axi4.scala 109:46] - node _T_100 = or(ahb_addr_in_iccm, _T_99) @[ahb_to_axi4.scala 109:26] - node _T_101 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 109:80] - node _T_102 = eq(_T_101, UInt<2>("h02")) @[ahb_to_axi4.scala 109:86] - node _T_103 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 109:109] - node _T_104 = eq(_T_103, UInt<2>("h03")) @[ahb_to_axi4.scala 109:115] - node _T_105 = or(_T_102, _T_104) @[ahb_to_axi4.scala 109:95] - node _T_106 = eq(_T_105, UInt<1>("h00")) @[ahb_to_axi4.scala 109:66] - node _T_107 = and(_T_100, _T_106) @[ahb_to_axi4.scala 109:64] - node _T_108 = or(_T_98, _T_107) @[ahb_to_axi4.scala 108:47] - node _T_109 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 110:20] - node _T_110 = eq(_T_109, UInt<1>("h01")) @[ahb_to_axi4.scala 110:26] - node _T_111 = bits(ahb_haddr_q, 0, 0) @[ahb_to_axi4.scala 110:48] - node _T_112 = and(_T_110, _T_111) @[ahb_to_axi4.scala 110:35] - node _T_113 = or(_T_108, _T_112) @[ahb_to_axi4.scala 109:126] - node _T_114 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 111:20] - node _T_115 = eq(_T_114, UInt<2>("h02")) @[ahb_to_axi4.scala 111:26] - node _T_116 = bits(ahb_haddr_q, 1, 0) @[ahb_to_axi4.scala 111:49] - node _T_117 = orr(_T_116) @[ahb_to_axi4.scala 111:56] - node _T_118 = and(_T_115, _T_117) @[ahb_to_axi4.scala 111:35] - node _T_119 = or(_T_113, _T_118) @[ahb_to_axi4.scala 110:55] - node _T_120 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 112:20] - node _T_121 = eq(_T_120, UInt<2>("h03")) @[ahb_to_axi4.scala 112:26] - node _T_122 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 112:49] - node _T_123 = orr(_T_122) @[ahb_to_axi4.scala 112:56] - node _T_124 = and(_T_121, _T_123) @[ahb_to_axi4.scala 112:35] - node _T_125 = or(_T_119, _T_124) @[ahb_to_axi4.scala 111:61] - node _T_126 = and(_T_96, _T_125) @[ahb_to_axi4.scala 107:94] - node _T_127 = or(_T_126, buf_read_error) @[ahb_to_axi4.scala 112:63] - node _T_128 = eq(ahb_hready_q, UInt<1>("h00")) @[ahb_to_axi4.scala 114:20] - node _T_129 = and(ahb_hresp_q, _T_128) @[ahb_to_axi4.scala 114:18] - node _T_130 = or(_T_127, _T_129) @[ahb_to_axi4.scala 113:20] - io.ahb.sig.in.hresp <= _T_130 @[ahb_to_axi4.scala 107:38] - reg _T_131 : UInt, buf_rdata_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 117:66] - _T_131 <= io.axi.r.bits.data @[ahb_to_axi4.scala 117:66] - buf_rdata <= _T_131 @[ahb_to_axi4.scala 117:31] - reg _T_132 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 118:60] - _T_132 <= buf_read_error_in @[ahb_to_axi4.scala 118:60] - buf_read_error <= _T_132 @[ahb_to_axi4.scala 118:31] - reg _T_133 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 121:60] - _T_133 <= io.ahb.sig.in.hresp @[ahb_to_axi4.scala 121:60] - ahb_hresp_q <= _T_133 @[ahb_to_axi4.scala 121:31] - reg _T_134 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 122:60] - _T_134 <= ahb_hready @[ahb_to_axi4.scala 122:60] - ahb_hready_q <= _T_134 @[ahb_to_axi4.scala 122:31] - reg _T_135 : UInt, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 123:60] - _T_135 <= ahb_htrans_in @[ahb_to_axi4.scala 123:60] - ahb_htrans_q <= _T_135 @[ahb_to_axi4.scala 123:31] - reg _T_136 : UInt, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 124:65] - _T_136 <= io.ahb.sig.out.hsize @[ahb_to_axi4.scala 124:65] - ahb_hsize_q <= _T_136 @[ahb_to_axi4.scala 124:31] - reg _T_137 : UInt<1>, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 125:65] - _T_137 <= io.ahb.sig.out.hwrite @[ahb_to_axi4.scala 125:65] - ahb_hwrite_q <= _T_137 @[ahb_to_axi4.scala 125:31] - reg _T_138 : UInt, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 126:65] - _T_138 <= io.ahb.sig.out.haddr @[ahb_to_axi4.scala 126:65] - ahb_haddr_q <= _T_138 @[ahb_to_axi4.scala 126:31] - node _T_139 = bits(io.ahb.sig.out.htrans, 1, 1) @[ahb_to_axi4.scala 129:85] - node _T_140 = and(ahb_hready, _T_139) @[ahb_to_axi4.scala 129:62] - node _T_141 = and(io.bus_clk_en, _T_140) @[ahb_to_axi4.scala 129:48] - ahb_bus_addr_clk_en <= _T_141 @[ahb_to_axi4.scala 129:31] - node _T_142 = and(io.bus_clk_en, buf_rdata_en) @[ahb_to_axi4.scala 130:48] - buf_rdata_clk_en <= _T_142 @[ahb_to_axi4.scala 130:31] - inst rvclkhdr of rvclkhdr_879 @[lib.scala 343:22] - rvclkhdr.clock <= clock - rvclkhdr.reset <= reset - rvclkhdr.io.clk <= clock @[lib.scala 344:17] - rvclkhdr.io.en <= io.bus_clk_en @[lib.scala 345:16] - rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahb_clk <= rvclkhdr.io.l1clk @[ahb_to_axi4.scala 132:31] - inst rvclkhdr_1 of rvclkhdr_880 @[lib.scala 343:22] - rvclkhdr_1.clock <= clock - rvclkhdr_1.reset <= reset - rvclkhdr_1.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_1.io.en <= ahb_bus_addr_clk_en @[lib.scala 345:16] - rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahb_addr_clk <= rvclkhdr_1.io.l1clk @[ahb_to_axi4.scala 133:31] - inst rvclkhdr_2 of rvclkhdr_881 @[lib.scala 343:22] - rvclkhdr_2.clock <= clock - rvclkhdr_2.reset <= reset - rvclkhdr_2.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_2.io.en <= buf_rdata_clk_en @[lib.scala 345:16] - rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - buf_rdata_clk <= rvclkhdr_2.io.l1clk @[ahb_to_axi4.scala 134:31] - node _T_143 = and(io.axi.aw.valid, io.axi.aw.ready) @[ahb_to_axi4.scala 136:53] - node _T_144 = and(io.axi.ar.valid, io.axi.ar.ready) @[ahb_to_axi4.scala 136:91] - node _T_145 = or(_T_143, _T_144) @[ahb_to_axi4.scala 136:72] - node _T_146 = eq(cmdbuf_wr_en, UInt<1>("h00")) @[ahb_to_axi4.scala 136:113] - node _T_147 = and(_T_145, _T_146) @[ahb_to_axi4.scala 136:111] - node _T_148 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 136:153] - node _T_149 = and(io.ahb.sig.in.hresp, _T_148) @[ahb_to_axi4.scala 136:151] - node _T_150 = or(_T_147, _T_149) @[ahb_to_axi4.scala 136:128] - cmdbuf_rst <= _T_150 @[ahb_to_axi4.scala 136:31] - node _T_151 = and(io.axi.aw.valid, io.axi.aw.ready) @[ahb_to_axi4.scala 137:67] - node _T_152 = and(io.axi.ar.valid, io.axi.ar.ready) @[ahb_to_axi4.scala 137:105] - node _T_153 = or(_T_151, _T_152) @[ahb_to_axi4.scala 137:86] - node _T_154 = eq(_T_153, UInt<1>("h00")) @[ahb_to_axi4.scala 137:48] - node _T_155 = and(cmdbuf_vld, _T_154) @[ahb_to_axi4.scala 137:46] - cmdbuf_full <= _T_155 @[ahb_to_axi4.scala 137:31] - node _T_156 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 139:86] - node _T_157 = mux(_T_156, UInt<1>("h01"), cmdbuf_vld) @[ahb_to_axi4.scala 139:66] - node _T_158 = eq(cmdbuf_rst, UInt<1>("h00")) @[ahb_to_axi4.scala 139:110] - node _T_159 = and(_T_157, _T_158) @[ahb_to_axi4.scala 139:108] - reg _T_160 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 139:61] - _T_160 <= _T_159 @[ahb_to_axi4.scala 139:61] - cmdbuf_vld <= _T_160 @[ahb_to_axi4.scala 139:31] - node _T_161 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 143:53] - reg _T_162 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_161 : @[Reg.scala 28:19] - _T_162 <= ahb_hwrite_q @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - cmdbuf_write <= _T_162 @[ahb_to_axi4.scala 142:31] - node _T_163 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 146:52] - reg _T_164 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_163 : @[Reg.scala 28:19] - _T_164 <= ahb_hsize_q @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - cmdbuf_size <= _T_164 @[ahb_to_axi4.scala 145:31] - node _T_165 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 149:53] - reg _T_166 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_165 : @[Reg.scala 28:19] - _T_166 <= master_wstrb @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - cmdbuf_wstrb <= _T_166 @[ahb_to_axi4.scala 148:31] - node _T_167 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 152:57] - inst rvclkhdr_3 of rvclkhdr_882 @[lib.scala 368:23] - rvclkhdr_3.clock <= clock - rvclkhdr_3.reset <= reset - rvclkhdr_3.io.clk <= bus_clk @[lib.scala 370:18] - rvclkhdr_3.io.en <= _T_167 @[lib.scala 371:17] - rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_168 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_168 <= ahb_haddr_q @[lib.scala 374:16] - cmdbuf_addr <= _T_168 @[ahb_to_axi4.scala 152:15] - node _T_169 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 153:68] - inst rvclkhdr_4 of rvclkhdr_883 @[lib.scala 368:23] - rvclkhdr_4.clock <= clock - rvclkhdr_4.reset <= reset - rvclkhdr_4.io.clk <= bus_clk @[lib.scala 370:18] - rvclkhdr_4.io.en <= _T_169 @[lib.scala 371:17] - rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_170 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_170 <= io.ahb.sig.out.hwdata @[lib.scala 374:16] - cmdbuf_wdata <= _T_170 @[ahb_to_axi4.scala 153:16] - node _T_171 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 156:42] - io.axi.aw.valid <= _T_171 @[ahb_to_axi4.scala 156:28] - io.axi.aw.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 157:33] - io.axi.aw.bits.addr <= cmdbuf_addr @[ahb_to_axi4.scala 158:33] - node _T_172 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 159:59] - node _T_173 = cat(UInt<1>("h00"), _T_172) @[Cat.scala 29:58] - io.axi.aw.bits.size <= _T_173 @[ahb_to_axi4.scala 159:33] - node _T_174 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - io.axi.aw.bits.prot <= _T_174 @[ahb_to_axi4.scala 160:33] - node _T_175 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - io.axi.aw.bits.len <= _T_175 @[ahb_to_axi4.scala 161:33] - io.axi.aw.bits.burst <= UInt<1>("h01") @[ahb_to_axi4.scala 162:33] - node _T_176 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 164:42] - io.axi.w.valid <= _T_176 @[ahb_to_axi4.scala 164:28] - io.axi.w.bits.data <= cmdbuf_wdata @[ahb_to_axi4.scala 165:33] - io.axi.w.bits.strb <= cmdbuf_wstrb @[ahb_to_axi4.scala 166:33] - io.axi.w.bits.last <= UInt<1>("h01") @[ahb_to_axi4.scala 167:33] - io.axi.b.ready <= UInt<1>("h01") @[ahb_to_axi4.scala 169:28] - node _T_177 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 171:44] - node _T_178 = and(cmdbuf_vld, _T_177) @[ahb_to_axi4.scala 171:42] - io.axi.ar.valid <= _T_178 @[ahb_to_axi4.scala 171:28] - io.axi.ar.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 172:33] - io.axi.ar.bits.addr <= cmdbuf_addr @[ahb_to_axi4.scala 173:33] - node _T_179 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 174:59] - node _T_180 = cat(UInt<1>("h00"), _T_179) @[Cat.scala 29:58] - io.axi.ar.bits.size <= _T_180 @[ahb_to_axi4.scala 174:33] - node _T_181 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - io.axi.ar.bits.prot <= _T_181 @[ahb_to_axi4.scala 175:33] - node _T_182 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - io.axi.ar.bits.len <= _T_182 @[ahb_to_axi4.scala 176:33] - io.axi.ar.bits.burst <= UInt<1>("h01") @[ahb_to_axi4.scala 177:33] - io.axi.r.ready <= UInt<1>("h01") @[ahb_to_axi4.scala 179:28] - inst rvclkhdr_5 of rvclkhdr_884 @[lib.scala 343:22] - rvclkhdr_5.clock <= clock - rvclkhdr_5.reset <= reset - rvclkhdr_5.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_5.io.en <= io.bus_clk_en @[lib.scala 345:16] - rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - bus_clk <= rvclkhdr_5.io.l1clk @[ahb_to_axi4.scala 180:27] - module quasar : input clock : Clock input reset : AsyncReset @@ -114371,554 +109556,263 @@ circuit quasar_wrapper : io.dccm.wr_addr_lo <= lsu.io.dccm.wr_addr_lo @[quasar.scala 238:11] io.dccm.rden <= lsu.io.dccm.rden @[quasar.scala 238:11] io.dccm.wren <= lsu.io.dccm.wren @[quasar.scala 238:11] - inst axi4_to_ahb of axi4_to_ahb @[quasar.scala 241:32] - axi4_to_ahb.clock <= clock - axi4_to_ahb.reset <= reset - inst axi4_to_ahb_1 of axi4_to_ahb_1 @[quasar.scala 242:33] - axi4_to_ahb_1.clock <= clock - axi4_to_ahb_1.reset <= reset - inst axi4_to_ahb_2 of axi4_to_ahb_2 @[quasar.scala 243:33] - axi4_to_ahb_2.clock <= clock - axi4_to_ahb_2.reset <= reset - inst ahb_to_axi4 of ahb_to_axi4 @[quasar.scala 244:33] - ahb_to_axi4.clock <= clock - ahb_to_axi4.reset <= reset - axi4_to_ahb_2.io.scan_mode <= io.scan_mode @[quasar.scala 246:34] - axi4_to_ahb_2.io.bus_clk_en <= io.lsu_bus_clk_en @[quasar.scala 247:35] - axi4_to_ahb_2.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 248:37] - lsu.io.axi.r.bits.last <= axi4_to_ahb_2.io.axi.r.bits.last @[quasar.scala 249:28] - lsu.io.axi.r.bits.resp <= axi4_to_ahb_2.io.axi.r.bits.resp @[quasar.scala 249:28] - lsu.io.axi.r.bits.data <= axi4_to_ahb_2.io.axi.r.bits.data @[quasar.scala 249:28] - lsu.io.axi.r.bits.id <= axi4_to_ahb_2.io.axi.r.bits.id @[quasar.scala 249:28] - lsu.io.axi.r.valid <= axi4_to_ahb_2.io.axi.r.valid @[quasar.scala 249:28] - axi4_to_ahb_2.io.axi.r.ready <= lsu.io.axi.r.ready @[quasar.scala 249:28] - axi4_to_ahb_2.io.axi.ar.bits.qos <= lsu.io.axi.ar.bits.qos @[quasar.scala 249:28] - axi4_to_ahb_2.io.axi.ar.bits.prot <= lsu.io.axi.ar.bits.prot @[quasar.scala 249:28] - axi4_to_ahb_2.io.axi.ar.bits.cache <= lsu.io.axi.ar.bits.cache @[quasar.scala 249:28] - axi4_to_ahb_2.io.axi.ar.bits.lock <= lsu.io.axi.ar.bits.lock @[quasar.scala 249:28] - axi4_to_ahb_2.io.axi.ar.bits.burst <= lsu.io.axi.ar.bits.burst @[quasar.scala 249:28] - axi4_to_ahb_2.io.axi.ar.bits.size <= lsu.io.axi.ar.bits.size @[quasar.scala 249:28] - axi4_to_ahb_2.io.axi.ar.bits.len <= lsu.io.axi.ar.bits.len @[quasar.scala 249:28] - axi4_to_ahb_2.io.axi.ar.bits.region <= lsu.io.axi.ar.bits.region @[quasar.scala 249:28] - axi4_to_ahb_2.io.axi.ar.bits.addr <= lsu.io.axi.ar.bits.addr @[quasar.scala 249:28] - axi4_to_ahb_2.io.axi.ar.bits.id <= lsu.io.axi.ar.bits.id @[quasar.scala 249:28] - axi4_to_ahb_2.io.axi.ar.valid <= lsu.io.axi.ar.valid @[quasar.scala 249:28] - lsu.io.axi.ar.ready <= axi4_to_ahb_2.io.axi.ar.ready @[quasar.scala 249:28] - lsu.io.axi.b.bits.id <= axi4_to_ahb_2.io.axi.b.bits.id @[quasar.scala 249:28] - lsu.io.axi.b.bits.resp <= axi4_to_ahb_2.io.axi.b.bits.resp @[quasar.scala 249:28] - lsu.io.axi.b.valid <= axi4_to_ahb_2.io.axi.b.valid @[quasar.scala 249:28] - axi4_to_ahb_2.io.axi.b.ready <= lsu.io.axi.b.ready @[quasar.scala 249:28] - axi4_to_ahb_2.io.axi.w.bits.last <= lsu.io.axi.w.bits.last @[quasar.scala 249:28] - axi4_to_ahb_2.io.axi.w.bits.strb <= lsu.io.axi.w.bits.strb @[quasar.scala 249:28] - axi4_to_ahb_2.io.axi.w.bits.data <= lsu.io.axi.w.bits.data @[quasar.scala 249:28] - axi4_to_ahb_2.io.axi.w.valid <= lsu.io.axi.w.valid @[quasar.scala 249:28] - lsu.io.axi.w.ready <= axi4_to_ahb_2.io.axi.w.ready @[quasar.scala 249:28] - axi4_to_ahb_2.io.axi.aw.bits.qos <= lsu.io.axi.aw.bits.qos @[quasar.scala 249:28] - axi4_to_ahb_2.io.axi.aw.bits.prot <= lsu.io.axi.aw.bits.prot @[quasar.scala 249:28] - axi4_to_ahb_2.io.axi.aw.bits.cache <= lsu.io.axi.aw.bits.cache @[quasar.scala 249:28] - axi4_to_ahb_2.io.axi.aw.bits.lock <= lsu.io.axi.aw.bits.lock @[quasar.scala 249:28] - axi4_to_ahb_2.io.axi.aw.bits.burst <= lsu.io.axi.aw.bits.burst @[quasar.scala 249:28] - axi4_to_ahb_2.io.axi.aw.bits.size <= lsu.io.axi.aw.bits.size @[quasar.scala 249:28] - axi4_to_ahb_2.io.axi.aw.bits.len <= lsu.io.axi.aw.bits.len @[quasar.scala 249:28] - axi4_to_ahb_2.io.axi.aw.bits.region <= lsu.io.axi.aw.bits.region @[quasar.scala 249:28] - axi4_to_ahb_2.io.axi.aw.bits.addr <= lsu.io.axi.aw.bits.addr @[quasar.scala 249:28] - axi4_to_ahb_2.io.axi.aw.bits.id <= lsu.io.axi.aw.bits.id @[quasar.scala 249:28] - axi4_to_ahb_2.io.axi.aw.valid <= lsu.io.axi.aw.valid @[quasar.scala 249:28] - lsu.io.axi.aw.ready <= axi4_to_ahb_2.io.axi.aw.ready @[quasar.scala 249:28] - io.lsu_ahb.out.hwdata <= axi4_to_ahb_2.io.ahb.out.hwdata @[quasar.scala 250:28] - io.lsu_ahb.out.hwrite <= axi4_to_ahb_2.io.ahb.out.hwrite @[quasar.scala 250:28] - io.lsu_ahb.out.htrans <= axi4_to_ahb_2.io.ahb.out.htrans @[quasar.scala 250:28] - io.lsu_ahb.out.hsize <= axi4_to_ahb_2.io.ahb.out.hsize @[quasar.scala 250:28] - io.lsu_ahb.out.hprot <= axi4_to_ahb_2.io.ahb.out.hprot @[quasar.scala 250:28] - io.lsu_ahb.out.hmastlock <= axi4_to_ahb_2.io.ahb.out.hmastlock @[quasar.scala 250:28] - io.lsu_ahb.out.hburst <= axi4_to_ahb_2.io.ahb.out.hburst @[quasar.scala 250:28] - io.lsu_ahb.out.haddr <= axi4_to_ahb_2.io.ahb.out.haddr @[quasar.scala 250:28] - axi4_to_ahb_2.io.ahb.in.hresp <= io.lsu_ahb.in.hresp @[quasar.scala 250:28] - axi4_to_ahb_2.io.ahb.in.hready <= io.lsu_ahb.in.hready @[quasar.scala 250:28] - axi4_to_ahb_2.io.ahb.in.hrdata <= io.lsu_ahb.in.hrdata @[quasar.scala 250:28] - axi4_to_ahb_1.io.scan_mode <= io.scan_mode @[quasar.scala 252:34] - axi4_to_ahb_1.io.bus_clk_en <= io.ifu_bus_clk_en @[quasar.scala 253:35] - axi4_to_ahb_1.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 254:37] - ifu.io.ifu.r.bits.last <= axi4_to_ahb_1.io.axi.r.bits.last @[quasar.scala 255:28] - ifu.io.ifu.r.bits.resp <= axi4_to_ahb_1.io.axi.r.bits.resp @[quasar.scala 255:28] - ifu.io.ifu.r.bits.data <= axi4_to_ahb_1.io.axi.r.bits.data @[quasar.scala 255:28] - ifu.io.ifu.r.bits.id <= axi4_to_ahb_1.io.axi.r.bits.id @[quasar.scala 255:28] - ifu.io.ifu.r.valid <= axi4_to_ahb_1.io.axi.r.valid @[quasar.scala 255:28] - axi4_to_ahb_1.io.axi.r.ready <= ifu.io.ifu.r.ready @[quasar.scala 255:28] - axi4_to_ahb_1.io.axi.ar.bits.qos <= ifu.io.ifu.ar.bits.qos @[quasar.scala 255:28] - axi4_to_ahb_1.io.axi.ar.bits.prot <= ifu.io.ifu.ar.bits.prot @[quasar.scala 255:28] - axi4_to_ahb_1.io.axi.ar.bits.cache <= ifu.io.ifu.ar.bits.cache @[quasar.scala 255:28] - axi4_to_ahb_1.io.axi.ar.bits.lock <= ifu.io.ifu.ar.bits.lock @[quasar.scala 255:28] - axi4_to_ahb_1.io.axi.ar.bits.burst <= ifu.io.ifu.ar.bits.burst @[quasar.scala 255:28] - axi4_to_ahb_1.io.axi.ar.bits.size <= ifu.io.ifu.ar.bits.size @[quasar.scala 255:28] - axi4_to_ahb_1.io.axi.ar.bits.len <= ifu.io.ifu.ar.bits.len @[quasar.scala 255:28] - axi4_to_ahb_1.io.axi.ar.bits.region <= ifu.io.ifu.ar.bits.region @[quasar.scala 255:28] - axi4_to_ahb_1.io.axi.ar.bits.addr <= ifu.io.ifu.ar.bits.addr @[quasar.scala 255:28] - axi4_to_ahb_1.io.axi.ar.bits.id <= ifu.io.ifu.ar.bits.id @[quasar.scala 255:28] - axi4_to_ahb_1.io.axi.ar.valid <= ifu.io.ifu.ar.valid @[quasar.scala 255:28] - ifu.io.ifu.ar.ready <= axi4_to_ahb_1.io.axi.ar.ready @[quasar.scala 255:28] - ifu.io.ifu.b.bits.id <= axi4_to_ahb_1.io.axi.b.bits.id @[quasar.scala 255:28] - ifu.io.ifu.b.bits.resp <= axi4_to_ahb_1.io.axi.b.bits.resp @[quasar.scala 255:28] - ifu.io.ifu.b.valid <= axi4_to_ahb_1.io.axi.b.valid @[quasar.scala 255:28] - axi4_to_ahb_1.io.axi.b.ready <= ifu.io.ifu.b.ready @[quasar.scala 255:28] - axi4_to_ahb_1.io.axi.w.bits.last <= ifu.io.ifu.w.bits.last @[quasar.scala 255:28] - axi4_to_ahb_1.io.axi.w.bits.strb <= ifu.io.ifu.w.bits.strb @[quasar.scala 255:28] - axi4_to_ahb_1.io.axi.w.bits.data <= ifu.io.ifu.w.bits.data @[quasar.scala 255:28] - axi4_to_ahb_1.io.axi.w.valid <= ifu.io.ifu.w.valid @[quasar.scala 255:28] - ifu.io.ifu.w.ready <= axi4_to_ahb_1.io.axi.w.ready @[quasar.scala 255:28] - axi4_to_ahb_1.io.axi.aw.bits.qos <= ifu.io.ifu.aw.bits.qos @[quasar.scala 255:28] - axi4_to_ahb_1.io.axi.aw.bits.prot <= ifu.io.ifu.aw.bits.prot @[quasar.scala 255:28] - axi4_to_ahb_1.io.axi.aw.bits.cache <= ifu.io.ifu.aw.bits.cache @[quasar.scala 255:28] - axi4_to_ahb_1.io.axi.aw.bits.lock <= ifu.io.ifu.aw.bits.lock @[quasar.scala 255:28] - axi4_to_ahb_1.io.axi.aw.bits.burst <= ifu.io.ifu.aw.bits.burst @[quasar.scala 255:28] - axi4_to_ahb_1.io.axi.aw.bits.size <= ifu.io.ifu.aw.bits.size @[quasar.scala 255:28] - axi4_to_ahb_1.io.axi.aw.bits.len <= ifu.io.ifu.aw.bits.len @[quasar.scala 255:28] - axi4_to_ahb_1.io.axi.aw.bits.region <= ifu.io.ifu.aw.bits.region @[quasar.scala 255:28] - axi4_to_ahb_1.io.axi.aw.bits.addr <= ifu.io.ifu.aw.bits.addr @[quasar.scala 255:28] - axi4_to_ahb_1.io.axi.aw.bits.id <= ifu.io.ifu.aw.bits.id @[quasar.scala 255:28] - axi4_to_ahb_1.io.axi.aw.valid <= ifu.io.ifu.aw.valid @[quasar.scala 255:28] - ifu.io.ifu.aw.ready <= axi4_to_ahb_1.io.axi.aw.ready @[quasar.scala 255:28] - io.ifu_ahb.out.hwdata <= axi4_to_ahb_1.io.ahb.out.hwdata @[quasar.scala 256:28] - io.ifu_ahb.out.hwrite <= axi4_to_ahb_1.io.ahb.out.hwrite @[quasar.scala 256:28] - io.ifu_ahb.out.htrans <= axi4_to_ahb_1.io.ahb.out.htrans @[quasar.scala 256:28] - io.ifu_ahb.out.hsize <= axi4_to_ahb_1.io.ahb.out.hsize @[quasar.scala 256:28] - io.ifu_ahb.out.hprot <= axi4_to_ahb_1.io.ahb.out.hprot @[quasar.scala 256:28] - io.ifu_ahb.out.hmastlock <= axi4_to_ahb_1.io.ahb.out.hmastlock @[quasar.scala 256:28] - io.ifu_ahb.out.hburst <= axi4_to_ahb_1.io.ahb.out.hburst @[quasar.scala 256:28] - io.ifu_ahb.out.haddr <= axi4_to_ahb_1.io.ahb.out.haddr @[quasar.scala 256:28] - axi4_to_ahb_1.io.ahb.in.hresp <= io.ifu_ahb.in.hresp @[quasar.scala 256:28] - axi4_to_ahb_1.io.ahb.in.hready <= io.ifu_ahb.in.hready @[quasar.scala 256:28] - axi4_to_ahb_1.io.ahb.in.hrdata <= io.ifu_ahb.in.hrdata @[quasar.scala 256:28] - axi4_to_ahb_1.io.axi.b.ready <= UInt<1>("h01") @[quasar.scala 257:36] - axi4_to_ahb.io.scan_mode <= io.scan_mode @[quasar.scala 259:33] - axi4_to_ahb.io.bus_clk_en <= io.dbg_bus_clk_en @[quasar.scala 260:34] - axi4_to_ahb.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 261:36] - dbg.io.sb_axi.r.bits.last <= axi4_to_ahb.io.axi.r.bits.last @[quasar.scala 262:27] - dbg.io.sb_axi.r.bits.resp <= axi4_to_ahb.io.axi.r.bits.resp @[quasar.scala 262:27] - dbg.io.sb_axi.r.bits.data <= axi4_to_ahb.io.axi.r.bits.data @[quasar.scala 262:27] - dbg.io.sb_axi.r.bits.id <= axi4_to_ahb.io.axi.r.bits.id @[quasar.scala 262:27] - dbg.io.sb_axi.r.valid <= axi4_to_ahb.io.axi.r.valid @[quasar.scala 262:27] - axi4_to_ahb.io.axi.r.ready <= dbg.io.sb_axi.r.ready @[quasar.scala 262:27] - axi4_to_ahb.io.axi.ar.bits.qos <= dbg.io.sb_axi.ar.bits.qos @[quasar.scala 262:27] - axi4_to_ahb.io.axi.ar.bits.prot <= dbg.io.sb_axi.ar.bits.prot @[quasar.scala 262:27] - axi4_to_ahb.io.axi.ar.bits.cache <= dbg.io.sb_axi.ar.bits.cache @[quasar.scala 262:27] - axi4_to_ahb.io.axi.ar.bits.lock <= dbg.io.sb_axi.ar.bits.lock @[quasar.scala 262:27] - axi4_to_ahb.io.axi.ar.bits.burst <= dbg.io.sb_axi.ar.bits.burst @[quasar.scala 262:27] - axi4_to_ahb.io.axi.ar.bits.size <= dbg.io.sb_axi.ar.bits.size @[quasar.scala 262:27] - axi4_to_ahb.io.axi.ar.bits.len <= dbg.io.sb_axi.ar.bits.len @[quasar.scala 262:27] - axi4_to_ahb.io.axi.ar.bits.region <= dbg.io.sb_axi.ar.bits.region @[quasar.scala 262:27] - axi4_to_ahb.io.axi.ar.bits.addr <= dbg.io.sb_axi.ar.bits.addr @[quasar.scala 262:27] - axi4_to_ahb.io.axi.ar.bits.id <= dbg.io.sb_axi.ar.bits.id @[quasar.scala 262:27] - axi4_to_ahb.io.axi.ar.valid <= dbg.io.sb_axi.ar.valid @[quasar.scala 262:27] - dbg.io.sb_axi.ar.ready <= axi4_to_ahb.io.axi.ar.ready @[quasar.scala 262:27] - dbg.io.sb_axi.b.bits.id <= axi4_to_ahb.io.axi.b.bits.id @[quasar.scala 262:27] - dbg.io.sb_axi.b.bits.resp <= axi4_to_ahb.io.axi.b.bits.resp @[quasar.scala 262:27] - dbg.io.sb_axi.b.valid <= axi4_to_ahb.io.axi.b.valid @[quasar.scala 262:27] - axi4_to_ahb.io.axi.b.ready <= dbg.io.sb_axi.b.ready @[quasar.scala 262:27] - axi4_to_ahb.io.axi.w.bits.last <= dbg.io.sb_axi.w.bits.last @[quasar.scala 262:27] - axi4_to_ahb.io.axi.w.bits.strb <= dbg.io.sb_axi.w.bits.strb @[quasar.scala 262:27] - axi4_to_ahb.io.axi.w.bits.data <= dbg.io.sb_axi.w.bits.data @[quasar.scala 262:27] - axi4_to_ahb.io.axi.w.valid <= dbg.io.sb_axi.w.valid @[quasar.scala 262:27] - dbg.io.sb_axi.w.ready <= axi4_to_ahb.io.axi.w.ready @[quasar.scala 262:27] - axi4_to_ahb.io.axi.aw.bits.qos <= dbg.io.sb_axi.aw.bits.qos @[quasar.scala 262:27] - axi4_to_ahb.io.axi.aw.bits.prot <= dbg.io.sb_axi.aw.bits.prot @[quasar.scala 262:27] - axi4_to_ahb.io.axi.aw.bits.cache <= dbg.io.sb_axi.aw.bits.cache @[quasar.scala 262:27] - axi4_to_ahb.io.axi.aw.bits.lock <= dbg.io.sb_axi.aw.bits.lock @[quasar.scala 262:27] - axi4_to_ahb.io.axi.aw.bits.burst <= dbg.io.sb_axi.aw.bits.burst @[quasar.scala 262:27] - axi4_to_ahb.io.axi.aw.bits.size <= dbg.io.sb_axi.aw.bits.size @[quasar.scala 262:27] - axi4_to_ahb.io.axi.aw.bits.len <= dbg.io.sb_axi.aw.bits.len @[quasar.scala 262:27] - axi4_to_ahb.io.axi.aw.bits.region <= dbg.io.sb_axi.aw.bits.region @[quasar.scala 262:27] - axi4_to_ahb.io.axi.aw.bits.addr <= dbg.io.sb_axi.aw.bits.addr @[quasar.scala 262:27] - axi4_to_ahb.io.axi.aw.bits.id <= dbg.io.sb_axi.aw.bits.id @[quasar.scala 262:27] - axi4_to_ahb.io.axi.aw.valid <= dbg.io.sb_axi.aw.valid @[quasar.scala 262:27] - dbg.io.sb_axi.aw.ready <= axi4_to_ahb.io.axi.aw.ready @[quasar.scala 262:27] - io.sb_ahb.out.hwdata <= axi4_to_ahb.io.ahb.out.hwdata @[quasar.scala 263:27] - io.sb_ahb.out.hwrite <= axi4_to_ahb.io.ahb.out.hwrite @[quasar.scala 263:27] - io.sb_ahb.out.htrans <= axi4_to_ahb.io.ahb.out.htrans @[quasar.scala 263:27] - io.sb_ahb.out.hsize <= axi4_to_ahb.io.ahb.out.hsize @[quasar.scala 263:27] - io.sb_ahb.out.hprot <= axi4_to_ahb.io.ahb.out.hprot @[quasar.scala 263:27] - io.sb_ahb.out.hmastlock <= axi4_to_ahb.io.ahb.out.hmastlock @[quasar.scala 263:27] - io.sb_ahb.out.hburst <= axi4_to_ahb.io.ahb.out.hburst @[quasar.scala 263:27] - io.sb_ahb.out.haddr <= axi4_to_ahb.io.ahb.out.haddr @[quasar.scala 263:27] - axi4_to_ahb.io.ahb.in.hresp <= io.sb_ahb.in.hresp @[quasar.scala 263:27] - axi4_to_ahb.io.ahb.in.hready <= io.sb_ahb.in.hready @[quasar.scala 263:27] - axi4_to_ahb.io.ahb.in.hrdata <= io.sb_ahb.in.hrdata @[quasar.scala 263:27] - ahb_to_axi4.io.scan_mode <= io.scan_mode @[quasar.scala 265:34] - ahb_to_axi4.io.bus_clk_en <= io.dma_bus_clk_en @[quasar.scala 266:35] - ahb_to_axi4.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 267:37] - ahb_to_axi4.io.axi.r.bits.last <= dma_ctrl.io.dma_axi.r.bits.last @[quasar.scala 268:28] - ahb_to_axi4.io.axi.r.bits.resp <= dma_ctrl.io.dma_axi.r.bits.resp @[quasar.scala 268:28] - ahb_to_axi4.io.axi.r.bits.data <= dma_ctrl.io.dma_axi.r.bits.data @[quasar.scala 268:28] - ahb_to_axi4.io.axi.r.bits.id <= dma_ctrl.io.dma_axi.r.bits.id @[quasar.scala 268:28] - ahb_to_axi4.io.axi.r.valid <= dma_ctrl.io.dma_axi.r.valid @[quasar.scala 268:28] - dma_ctrl.io.dma_axi.r.ready <= ahb_to_axi4.io.axi.r.ready @[quasar.scala 268:28] - dma_ctrl.io.dma_axi.ar.bits.qos <= ahb_to_axi4.io.axi.ar.bits.qos @[quasar.scala 268:28] - dma_ctrl.io.dma_axi.ar.bits.prot <= ahb_to_axi4.io.axi.ar.bits.prot @[quasar.scala 268:28] - dma_ctrl.io.dma_axi.ar.bits.cache <= ahb_to_axi4.io.axi.ar.bits.cache @[quasar.scala 268:28] - dma_ctrl.io.dma_axi.ar.bits.lock <= ahb_to_axi4.io.axi.ar.bits.lock @[quasar.scala 268:28] - dma_ctrl.io.dma_axi.ar.bits.burst <= ahb_to_axi4.io.axi.ar.bits.burst @[quasar.scala 268:28] - dma_ctrl.io.dma_axi.ar.bits.size <= ahb_to_axi4.io.axi.ar.bits.size @[quasar.scala 268:28] - dma_ctrl.io.dma_axi.ar.bits.len <= ahb_to_axi4.io.axi.ar.bits.len @[quasar.scala 268:28] - dma_ctrl.io.dma_axi.ar.bits.region <= ahb_to_axi4.io.axi.ar.bits.region @[quasar.scala 268:28] - dma_ctrl.io.dma_axi.ar.bits.addr <= ahb_to_axi4.io.axi.ar.bits.addr @[quasar.scala 268:28] - dma_ctrl.io.dma_axi.ar.bits.id <= ahb_to_axi4.io.axi.ar.bits.id @[quasar.scala 268:28] - dma_ctrl.io.dma_axi.ar.valid <= ahb_to_axi4.io.axi.ar.valid @[quasar.scala 268:28] - ahb_to_axi4.io.axi.ar.ready <= dma_ctrl.io.dma_axi.ar.ready @[quasar.scala 268:28] - ahb_to_axi4.io.axi.b.bits.id <= dma_ctrl.io.dma_axi.b.bits.id @[quasar.scala 268:28] - ahb_to_axi4.io.axi.b.bits.resp <= dma_ctrl.io.dma_axi.b.bits.resp @[quasar.scala 268:28] - ahb_to_axi4.io.axi.b.valid <= dma_ctrl.io.dma_axi.b.valid @[quasar.scala 268:28] - dma_ctrl.io.dma_axi.b.ready <= ahb_to_axi4.io.axi.b.ready @[quasar.scala 268:28] - dma_ctrl.io.dma_axi.w.bits.last <= ahb_to_axi4.io.axi.w.bits.last @[quasar.scala 268:28] - dma_ctrl.io.dma_axi.w.bits.strb <= ahb_to_axi4.io.axi.w.bits.strb @[quasar.scala 268:28] - dma_ctrl.io.dma_axi.w.bits.data <= ahb_to_axi4.io.axi.w.bits.data @[quasar.scala 268:28] - dma_ctrl.io.dma_axi.w.valid <= ahb_to_axi4.io.axi.w.valid @[quasar.scala 268:28] - ahb_to_axi4.io.axi.w.ready <= dma_ctrl.io.dma_axi.w.ready @[quasar.scala 268:28] - dma_ctrl.io.dma_axi.aw.bits.qos <= ahb_to_axi4.io.axi.aw.bits.qos @[quasar.scala 268:28] - dma_ctrl.io.dma_axi.aw.bits.prot <= ahb_to_axi4.io.axi.aw.bits.prot @[quasar.scala 268:28] - dma_ctrl.io.dma_axi.aw.bits.cache <= ahb_to_axi4.io.axi.aw.bits.cache @[quasar.scala 268:28] - dma_ctrl.io.dma_axi.aw.bits.lock <= ahb_to_axi4.io.axi.aw.bits.lock @[quasar.scala 268:28] - dma_ctrl.io.dma_axi.aw.bits.burst <= ahb_to_axi4.io.axi.aw.bits.burst @[quasar.scala 268:28] - dma_ctrl.io.dma_axi.aw.bits.size <= ahb_to_axi4.io.axi.aw.bits.size @[quasar.scala 268:28] - dma_ctrl.io.dma_axi.aw.bits.len <= ahb_to_axi4.io.axi.aw.bits.len @[quasar.scala 268:28] - dma_ctrl.io.dma_axi.aw.bits.region <= ahb_to_axi4.io.axi.aw.bits.region @[quasar.scala 268:28] - dma_ctrl.io.dma_axi.aw.bits.addr <= ahb_to_axi4.io.axi.aw.bits.addr @[quasar.scala 268:28] - dma_ctrl.io.dma_axi.aw.bits.id <= ahb_to_axi4.io.axi.aw.bits.id @[quasar.scala 268:28] - dma_ctrl.io.dma_axi.aw.valid <= ahb_to_axi4.io.axi.aw.valid @[quasar.scala 268:28] - ahb_to_axi4.io.axi.aw.ready <= dma_ctrl.io.dma_axi.aw.ready @[quasar.scala 268:28] - ahb_to_axi4.io.ahb.hreadyin <= io.dma_ahb.hreadyin @[quasar.scala 269:28] - ahb_to_axi4.io.ahb.hsel <= io.dma_ahb.hsel @[quasar.scala 269:28] - ahb_to_axi4.io.ahb.sig.out.hwdata <= io.dma_ahb.sig.out.hwdata @[quasar.scala 269:28] - ahb_to_axi4.io.ahb.sig.out.hwrite <= io.dma_ahb.sig.out.hwrite @[quasar.scala 269:28] - ahb_to_axi4.io.ahb.sig.out.htrans <= io.dma_ahb.sig.out.htrans @[quasar.scala 269:28] - ahb_to_axi4.io.ahb.sig.out.hsize <= io.dma_ahb.sig.out.hsize @[quasar.scala 269:28] - ahb_to_axi4.io.ahb.sig.out.hprot <= io.dma_ahb.sig.out.hprot @[quasar.scala 269:28] - ahb_to_axi4.io.ahb.sig.out.hmastlock <= io.dma_ahb.sig.out.hmastlock @[quasar.scala 269:28] - ahb_to_axi4.io.ahb.sig.out.hburst <= io.dma_ahb.sig.out.hburst @[quasar.scala 269:28] - ahb_to_axi4.io.ahb.sig.out.haddr <= io.dma_ahb.sig.out.haddr @[quasar.scala 269:28] - io.dma_ahb.sig.in.hresp <= ahb_to_axi4.io.ahb.sig.in.hresp @[quasar.scala 269:28] - io.dma_ahb.sig.in.hready <= ahb_to_axi4.io.ahb.sig.in.hready @[quasar.scala 269:28] - io.dma_ahb.sig.in.hrdata <= ahb_to_axi4.io.ahb.sig.in.hrdata @[quasar.scala 269:28] - wire _T_13 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar.scala 271:36] - _T_13.r.bits.last <= UInt<1>("h00") @[quasar.scala 271:36] - _T_13.r.bits.resp <= UInt<2>("h00") @[quasar.scala 271:36] - _T_13.r.bits.data <= UInt<64>("h00") @[quasar.scala 271:36] - _T_13.r.bits.id <= UInt<1>("h00") @[quasar.scala 271:36] - _T_13.r.valid <= UInt<1>("h00") @[quasar.scala 271:36] - _T_13.r.ready <= UInt<1>("h00") @[quasar.scala 271:36] - _T_13.ar.bits.qos <= UInt<4>("h00") @[quasar.scala 271:36] - _T_13.ar.bits.prot <= UInt<3>("h00") @[quasar.scala 271:36] - _T_13.ar.bits.cache <= UInt<4>("h00") @[quasar.scala 271:36] - _T_13.ar.bits.lock <= UInt<1>("h00") @[quasar.scala 271:36] - _T_13.ar.bits.burst <= UInt<2>("h00") @[quasar.scala 271:36] - _T_13.ar.bits.size <= UInt<3>("h00") @[quasar.scala 271:36] - _T_13.ar.bits.len <= UInt<8>("h00") @[quasar.scala 271:36] - _T_13.ar.bits.region <= UInt<4>("h00") @[quasar.scala 271:36] - _T_13.ar.bits.addr <= UInt<32>("h00") @[quasar.scala 271:36] - _T_13.ar.bits.id <= UInt<1>("h00") @[quasar.scala 271:36] - _T_13.ar.valid <= UInt<1>("h00") @[quasar.scala 271:36] - _T_13.ar.ready <= UInt<1>("h00") @[quasar.scala 271:36] - _T_13.b.bits.id <= UInt<1>("h00") @[quasar.scala 271:36] - _T_13.b.bits.resp <= UInt<2>("h00") @[quasar.scala 271:36] - _T_13.b.valid <= UInt<1>("h00") @[quasar.scala 271:36] - _T_13.b.ready <= UInt<1>("h00") @[quasar.scala 271:36] - _T_13.w.bits.last <= UInt<1>("h00") @[quasar.scala 271:36] - _T_13.w.bits.strb <= UInt<8>("h00") @[quasar.scala 271:36] - _T_13.w.bits.data <= UInt<64>("h00") @[quasar.scala 271:36] - _T_13.w.valid <= UInt<1>("h00") @[quasar.scala 271:36] - _T_13.w.ready <= UInt<1>("h00") @[quasar.scala 271:36] - _T_13.aw.bits.qos <= UInt<4>("h00") @[quasar.scala 271:36] - _T_13.aw.bits.prot <= UInt<3>("h00") @[quasar.scala 271:36] - _T_13.aw.bits.cache <= UInt<4>("h00") @[quasar.scala 271:36] - _T_13.aw.bits.lock <= UInt<1>("h00") @[quasar.scala 271:36] - _T_13.aw.bits.burst <= UInt<2>("h00") @[quasar.scala 271:36] - _T_13.aw.bits.size <= UInt<3>("h00") @[quasar.scala 271:36] - _T_13.aw.bits.len <= UInt<8>("h00") @[quasar.scala 271:36] - _T_13.aw.bits.region <= UInt<4>("h00") @[quasar.scala 271:36] - _T_13.aw.bits.addr <= UInt<32>("h00") @[quasar.scala 271:36] - _T_13.aw.bits.id <= UInt<1>("h00") @[quasar.scala 271:36] - _T_13.aw.valid <= UInt<1>("h00") @[quasar.scala 271:36] - _T_13.aw.ready <= UInt<1>("h00") @[quasar.scala 271:36] - io.dma_axi.r.bits.last <= _T_13.r.bits.last @[quasar.scala 271:21] - io.dma_axi.r.bits.resp <= _T_13.r.bits.resp @[quasar.scala 271:21] - io.dma_axi.r.bits.data <= _T_13.r.bits.data @[quasar.scala 271:21] - io.dma_axi.r.bits.id <= _T_13.r.bits.id @[quasar.scala 271:21] - io.dma_axi.r.valid <= _T_13.r.valid @[quasar.scala 271:21] - _T_13.r.ready <= io.dma_axi.r.ready @[quasar.scala 271:21] - _T_13.ar.bits.qos <= io.dma_axi.ar.bits.qos @[quasar.scala 271:21] - _T_13.ar.bits.prot <= io.dma_axi.ar.bits.prot @[quasar.scala 271:21] - _T_13.ar.bits.cache <= io.dma_axi.ar.bits.cache @[quasar.scala 271:21] - _T_13.ar.bits.lock <= io.dma_axi.ar.bits.lock @[quasar.scala 271:21] - _T_13.ar.bits.burst <= io.dma_axi.ar.bits.burst @[quasar.scala 271:21] - _T_13.ar.bits.size <= io.dma_axi.ar.bits.size @[quasar.scala 271:21] - _T_13.ar.bits.len <= io.dma_axi.ar.bits.len @[quasar.scala 271:21] - _T_13.ar.bits.region <= io.dma_axi.ar.bits.region @[quasar.scala 271:21] - _T_13.ar.bits.addr <= io.dma_axi.ar.bits.addr @[quasar.scala 271:21] - _T_13.ar.bits.id <= io.dma_axi.ar.bits.id @[quasar.scala 271:21] - _T_13.ar.valid <= io.dma_axi.ar.valid @[quasar.scala 271:21] - io.dma_axi.ar.ready <= _T_13.ar.ready @[quasar.scala 271:21] - io.dma_axi.b.bits.id <= _T_13.b.bits.id @[quasar.scala 271:21] - io.dma_axi.b.bits.resp <= _T_13.b.bits.resp @[quasar.scala 271:21] - io.dma_axi.b.valid <= _T_13.b.valid @[quasar.scala 271:21] - _T_13.b.ready <= io.dma_axi.b.ready @[quasar.scala 271:21] - _T_13.w.bits.last <= io.dma_axi.w.bits.last @[quasar.scala 271:21] - _T_13.w.bits.strb <= io.dma_axi.w.bits.strb @[quasar.scala 271:21] - _T_13.w.bits.data <= io.dma_axi.w.bits.data @[quasar.scala 271:21] - _T_13.w.valid <= io.dma_axi.w.valid @[quasar.scala 271:21] - io.dma_axi.w.ready <= _T_13.w.ready @[quasar.scala 271:21] - _T_13.aw.bits.qos <= io.dma_axi.aw.bits.qos @[quasar.scala 271:21] - _T_13.aw.bits.prot <= io.dma_axi.aw.bits.prot @[quasar.scala 271:21] - _T_13.aw.bits.cache <= io.dma_axi.aw.bits.cache @[quasar.scala 271:21] - _T_13.aw.bits.lock <= io.dma_axi.aw.bits.lock @[quasar.scala 271:21] - _T_13.aw.bits.burst <= io.dma_axi.aw.bits.burst @[quasar.scala 271:21] - _T_13.aw.bits.size <= io.dma_axi.aw.bits.size @[quasar.scala 271:21] - _T_13.aw.bits.len <= io.dma_axi.aw.bits.len @[quasar.scala 271:21] - _T_13.aw.bits.region <= io.dma_axi.aw.bits.region @[quasar.scala 271:21] - _T_13.aw.bits.addr <= io.dma_axi.aw.bits.addr @[quasar.scala 271:21] - _T_13.aw.bits.id <= io.dma_axi.aw.bits.id @[quasar.scala 271:21] - _T_13.aw.valid <= io.dma_axi.aw.valid @[quasar.scala 271:21] - io.dma_axi.aw.ready <= _T_13.aw.ready @[quasar.scala 271:21] - wire _T_14 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar.scala 272:36] - _T_14.r.bits.last <= UInt<1>("h00") @[quasar.scala 272:36] - _T_14.r.bits.resp <= UInt<2>("h00") @[quasar.scala 272:36] - _T_14.r.bits.data <= UInt<64>("h00") @[quasar.scala 272:36] - _T_14.r.bits.id <= UInt<1>("h00") @[quasar.scala 272:36] - _T_14.r.valid <= UInt<1>("h00") @[quasar.scala 272:36] - _T_14.r.ready <= UInt<1>("h00") @[quasar.scala 272:36] - _T_14.ar.bits.qos <= UInt<4>("h00") @[quasar.scala 272:36] - _T_14.ar.bits.prot <= UInt<3>("h00") @[quasar.scala 272:36] - _T_14.ar.bits.cache <= UInt<4>("h00") @[quasar.scala 272:36] - _T_14.ar.bits.lock <= UInt<1>("h00") @[quasar.scala 272:36] - _T_14.ar.bits.burst <= UInt<2>("h00") @[quasar.scala 272:36] - _T_14.ar.bits.size <= UInt<3>("h00") @[quasar.scala 272:36] - _T_14.ar.bits.len <= UInt<8>("h00") @[quasar.scala 272:36] - _T_14.ar.bits.region <= UInt<4>("h00") @[quasar.scala 272:36] - _T_14.ar.bits.addr <= UInt<32>("h00") @[quasar.scala 272:36] - _T_14.ar.bits.id <= UInt<1>("h00") @[quasar.scala 272:36] - _T_14.ar.valid <= UInt<1>("h00") @[quasar.scala 272:36] - _T_14.ar.ready <= UInt<1>("h00") @[quasar.scala 272:36] - _T_14.b.bits.id <= UInt<1>("h00") @[quasar.scala 272:36] - _T_14.b.bits.resp <= UInt<2>("h00") @[quasar.scala 272:36] - _T_14.b.valid <= UInt<1>("h00") @[quasar.scala 272:36] - _T_14.b.ready <= UInt<1>("h00") @[quasar.scala 272:36] - _T_14.w.bits.last <= UInt<1>("h00") @[quasar.scala 272:36] - _T_14.w.bits.strb <= UInt<8>("h00") @[quasar.scala 272:36] - _T_14.w.bits.data <= UInt<64>("h00") @[quasar.scala 272:36] - _T_14.w.valid <= UInt<1>("h00") @[quasar.scala 272:36] - _T_14.w.ready <= UInt<1>("h00") @[quasar.scala 272:36] - _T_14.aw.bits.qos <= UInt<4>("h00") @[quasar.scala 272:36] - _T_14.aw.bits.prot <= UInt<3>("h00") @[quasar.scala 272:36] - _T_14.aw.bits.cache <= UInt<4>("h00") @[quasar.scala 272:36] - _T_14.aw.bits.lock <= UInt<1>("h00") @[quasar.scala 272:36] - _T_14.aw.bits.burst <= UInt<2>("h00") @[quasar.scala 272:36] - _T_14.aw.bits.size <= UInt<3>("h00") @[quasar.scala 272:36] - _T_14.aw.bits.len <= UInt<8>("h00") @[quasar.scala 272:36] - _T_14.aw.bits.region <= UInt<4>("h00") @[quasar.scala 272:36] - _T_14.aw.bits.addr <= UInt<32>("h00") @[quasar.scala 272:36] - _T_14.aw.bits.id <= UInt<1>("h00") @[quasar.scala 272:36] - _T_14.aw.valid <= UInt<1>("h00") @[quasar.scala 272:36] - _T_14.aw.ready <= UInt<1>("h00") @[quasar.scala 272:36] - _T_14.r.bits.last <= io.sb_axi.r.bits.last @[quasar.scala 272:21] - _T_14.r.bits.resp <= io.sb_axi.r.bits.resp @[quasar.scala 272:21] - _T_14.r.bits.data <= io.sb_axi.r.bits.data @[quasar.scala 272:21] - _T_14.r.bits.id <= io.sb_axi.r.bits.id @[quasar.scala 272:21] - _T_14.r.valid <= io.sb_axi.r.valid @[quasar.scala 272:21] - io.sb_axi.r.ready <= _T_14.r.ready @[quasar.scala 272:21] - io.sb_axi.ar.bits.qos <= _T_14.ar.bits.qos @[quasar.scala 272:21] - io.sb_axi.ar.bits.prot <= _T_14.ar.bits.prot @[quasar.scala 272:21] - io.sb_axi.ar.bits.cache <= _T_14.ar.bits.cache @[quasar.scala 272:21] - io.sb_axi.ar.bits.lock <= _T_14.ar.bits.lock @[quasar.scala 272:21] - io.sb_axi.ar.bits.burst <= _T_14.ar.bits.burst @[quasar.scala 272:21] - io.sb_axi.ar.bits.size <= _T_14.ar.bits.size @[quasar.scala 272:21] - io.sb_axi.ar.bits.len <= _T_14.ar.bits.len @[quasar.scala 272:21] - io.sb_axi.ar.bits.region <= _T_14.ar.bits.region @[quasar.scala 272:21] - io.sb_axi.ar.bits.addr <= _T_14.ar.bits.addr @[quasar.scala 272:21] - io.sb_axi.ar.bits.id <= _T_14.ar.bits.id @[quasar.scala 272:21] - io.sb_axi.ar.valid <= _T_14.ar.valid @[quasar.scala 272:21] - _T_14.ar.ready <= io.sb_axi.ar.ready @[quasar.scala 272:21] - _T_14.b.bits.id <= io.sb_axi.b.bits.id @[quasar.scala 272:21] - _T_14.b.bits.resp <= io.sb_axi.b.bits.resp @[quasar.scala 272:21] - _T_14.b.valid <= io.sb_axi.b.valid @[quasar.scala 272:21] - io.sb_axi.b.ready <= _T_14.b.ready @[quasar.scala 272:21] - io.sb_axi.w.bits.last <= _T_14.w.bits.last @[quasar.scala 272:21] - io.sb_axi.w.bits.strb <= _T_14.w.bits.strb @[quasar.scala 272:21] - io.sb_axi.w.bits.data <= _T_14.w.bits.data @[quasar.scala 272:21] - io.sb_axi.w.valid <= _T_14.w.valid @[quasar.scala 272:21] - _T_14.w.ready <= io.sb_axi.w.ready @[quasar.scala 272:21] - io.sb_axi.aw.bits.qos <= _T_14.aw.bits.qos @[quasar.scala 272:21] - io.sb_axi.aw.bits.prot <= _T_14.aw.bits.prot @[quasar.scala 272:21] - io.sb_axi.aw.bits.cache <= _T_14.aw.bits.cache @[quasar.scala 272:21] - io.sb_axi.aw.bits.lock <= _T_14.aw.bits.lock @[quasar.scala 272:21] - io.sb_axi.aw.bits.burst <= _T_14.aw.bits.burst @[quasar.scala 272:21] - io.sb_axi.aw.bits.size <= _T_14.aw.bits.size @[quasar.scala 272:21] - io.sb_axi.aw.bits.len <= _T_14.aw.bits.len @[quasar.scala 272:21] - io.sb_axi.aw.bits.region <= _T_14.aw.bits.region @[quasar.scala 272:21] - io.sb_axi.aw.bits.addr <= _T_14.aw.bits.addr @[quasar.scala 272:21] - io.sb_axi.aw.bits.id <= _T_14.aw.bits.id @[quasar.scala 272:21] - io.sb_axi.aw.valid <= _T_14.aw.valid @[quasar.scala 272:21] - _T_14.aw.ready <= io.sb_axi.aw.ready @[quasar.scala 272:21] - wire _T_15 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar.scala 273:36] - _T_15.r.bits.last <= UInt<1>("h00") @[quasar.scala 273:36] - _T_15.r.bits.resp <= UInt<2>("h00") @[quasar.scala 273:36] - _T_15.r.bits.data <= UInt<64>("h00") @[quasar.scala 273:36] - _T_15.r.bits.id <= UInt<3>("h00") @[quasar.scala 273:36] - _T_15.r.valid <= UInt<1>("h00") @[quasar.scala 273:36] - _T_15.r.ready <= UInt<1>("h00") @[quasar.scala 273:36] - _T_15.ar.bits.qos <= UInt<4>("h00") @[quasar.scala 273:36] - _T_15.ar.bits.prot <= UInt<3>("h00") @[quasar.scala 273:36] - _T_15.ar.bits.cache <= UInt<4>("h00") @[quasar.scala 273:36] - _T_15.ar.bits.lock <= UInt<1>("h00") @[quasar.scala 273:36] - _T_15.ar.bits.burst <= UInt<2>("h00") @[quasar.scala 273:36] - _T_15.ar.bits.size <= UInt<3>("h00") @[quasar.scala 273:36] - _T_15.ar.bits.len <= UInt<8>("h00") @[quasar.scala 273:36] - _T_15.ar.bits.region <= UInt<4>("h00") @[quasar.scala 273:36] - _T_15.ar.bits.addr <= UInt<32>("h00") @[quasar.scala 273:36] - _T_15.ar.bits.id <= UInt<3>("h00") @[quasar.scala 273:36] - _T_15.ar.valid <= UInt<1>("h00") @[quasar.scala 273:36] - _T_15.ar.ready <= UInt<1>("h00") @[quasar.scala 273:36] - _T_15.b.bits.id <= UInt<3>("h00") @[quasar.scala 273:36] - _T_15.b.bits.resp <= UInt<2>("h00") @[quasar.scala 273:36] - _T_15.b.valid <= UInt<1>("h00") @[quasar.scala 273:36] - _T_15.b.ready <= UInt<1>("h00") @[quasar.scala 273:36] - _T_15.w.bits.last <= UInt<1>("h00") @[quasar.scala 273:36] - _T_15.w.bits.strb <= UInt<8>("h00") @[quasar.scala 273:36] - _T_15.w.bits.data <= UInt<64>("h00") @[quasar.scala 273:36] - _T_15.w.valid <= UInt<1>("h00") @[quasar.scala 273:36] - _T_15.w.ready <= UInt<1>("h00") @[quasar.scala 273:36] - _T_15.aw.bits.qos <= UInt<4>("h00") @[quasar.scala 273:36] - _T_15.aw.bits.prot <= UInt<3>("h00") @[quasar.scala 273:36] - _T_15.aw.bits.cache <= UInt<4>("h00") @[quasar.scala 273:36] - _T_15.aw.bits.lock <= UInt<1>("h00") @[quasar.scala 273:36] - _T_15.aw.bits.burst <= UInt<2>("h00") @[quasar.scala 273:36] - _T_15.aw.bits.size <= UInt<3>("h00") @[quasar.scala 273:36] - _T_15.aw.bits.len <= UInt<8>("h00") @[quasar.scala 273:36] - _T_15.aw.bits.region <= UInt<4>("h00") @[quasar.scala 273:36] - _T_15.aw.bits.addr <= UInt<32>("h00") @[quasar.scala 273:36] - _T_15.aw.bits.id <= UInt<3>("h00") @[quasar.scala 273:36] - _T_15.aw.valid <= UInt<1>("h00") @[quasar.scala 273:36] - _T_15.aw.ready <= UInt<1>("h00") @[quasar.scala 273:36] - _T_15.r.bits.last <= io.ifu_axi.r.bits.last @[quasar.scala 273:21] - _T_15.r.bits.resp <= io.ifu_axi.r.bits.resp @[quasar.scala 273:21] - _T_15.r.bits.data <= io.ifu_axi.r.bits.data @[quasar.scala 273:21] - _T_15.r.bits.id <= io.ifu_axi.r.bits.id @[quasar.scala 273:21] - _T_15.r.valid <= io.ifu_axi.r.valid @[quasar.scala 273:21] - io.ifu_axi.r.ready <= _T_15.r.ready @[quasar.scala 273:21] - io.ifu_axi.ar.bits.qos <= _T_15.ar.bits.qos @[quasar.scala 273:21] - io.ifu_axi.ar.bits.prot <= _T_15.ar.bits.prot @[quasar.scala 273:21] - io.ifu_axi.ar.bits.cache <= _T_15.ar.bits.cache @[quasar.scala 273:21] - io.ifu_axi.ar.bits.lock <= _T_15.ar.bits.lock @[quasar.scala 273:21] - io.ifu_axi.ar.bits.burst <= _T_15.ar.bits.burst @[quasar.scala 273:21] - io.ifu_axi.ar.bits.size <= _T_15.ar.bits.size @[quasar.scala 273:21] - io.ifu_axi.ar.bits.len <= _T_15.ar.bits.len @[quasar.scala 273:21] - io.ifu_axi.ar.bits.region <= _T_15.ar.bits.region @[quasar.scala 273:21] - io.ifu_axi.ar.bits.addr <= _T_15.ar.bits.addr @[quasar.scala 273:21] - io.ifu_axi.ar.bits.id <= _T_15.ar.bits.id @[quasar.scala 273:21] - io.ifu_axi.ar.valid <= _T_15.ar.valid @[quasar.scala 273:21] - _T_15.ar.ready <= io.ifu_axi.ar.ready @[quasar.scala 273:21] - _T_15.b.bits.id <= io.ifu_axi.b.bits.id @[quasar.scala 273:21] - _T_15.b.bits.resp <= io.ifu_axi.b.bits.resp @[quasar.scala 273:21] - _T_15.b.valid <= io.ifu_axi.b.valid @[quasar.scala 273:21] - io.ifu_axi.b.ready <= _T_15.b.ready @[quasar.scala 273:21] - io.ifu_axi.w.bits.last <= _T_15.w.bits.last @[quasar.scala 273:21] - io.ifu_axi.w.bits.strb <= _T_15.w.bits.strb @[quasar.scala 273:21] - io.ifu_axi.w.bits.data <= _T_15.w.bits.data @[quasar.scala 273:21] - io.ifu_axi.w.valid <= _T_15.w.valid @[quasar.scala 273:21] - _T_15.w.ready <= io.ifu_axi.w.ready @[quasar.scala 273:21] - io.ifu_axi.aw.bits.qos <= _T_15.aw.bits.qos @[quasar.scala 273:21] - io.ifu_axi.aw.bits.prot <= _T_15.aw.bits.prot @[quasar.scala 273:21] - io.ifu_axi.aw.bits.cache <= _T_15.aw.bits.cache @[quasar.scala 273:21] - io.ifu_axi.aw.bits.lock <= _T_15.aw.bits.lock @[quasar.scala 273:21] - io.ifu_axi.aw.bits.burst <= _T_15.aw.bits.burst @[quasar.scala 273:21] - io.ifu_axi.aw.bits.size <= _T_15.aw.bits.size @[quasar.scala 273:21] - io.ifu_axi.aw.bits.len <= _T_15.aw.bits.len @[quasar.scala 273:21] - io.ifu_axi.aw.bits.region <= _T_15.aw.bits.region @[quasar.scala 273:21] - io.ifu_axi.aw.bits.addr <= _T_15.aw.bits.addr @[quasar.scala 273:21] - io.ifu_axi.aw.bits.id <= _T_15.aw.bits.id @[quasar.scala 273:21] - io.ifu_axi.aw.valid <= _T_15.aw.valid @[quasar.scala 273:21] - _T_15.aw.ready <= io.ifu_axi.aw.ready @[quasar.scala 273:21] - wire _T_16 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar.scala 274:36] - _T_16.r.bits.last <= UInt<1>("h00") @[quasar.scala 274:36] - _T_16.r.bits.resp <= UInt<2>("h00") @[quasar.scala 274:36] - _T_16.r.bits.data <= UInt<64>("h00") @[quasar.scala 274:36] - _T_16.r.bits.id <= UInt<3>("h00") @[quasar.scala 274:36] - _T_16.r.valid <= UInt<1>("h00") @[quasar.scala 274:36] - _T_16.r.ready <= UInt<1>("h00") @[quasar.scala 274:36] - _T_16.ar.bits.qos <= UInt<4>("h00") @[quasar.scala 274:36] - _T_16.ar.bits.prot <= UInt<3>("h00") @[quasar.scala 274:36] - _T_16.ar.bits.cache <= UInt<4>("h00") @[quasar.scala 274:36] - _T_16.ar.bits.lock <= UInt<1>("h00") @[quasar.scala 274:36] - _T_16.ar.bits.burst <= UInt<2>("h00") @[quasar.scala 274:36] - _T_16.ar.bits.size <= UInt<3>("h00") @[quasar.scala 274:36] - _T_16.ar.bits.len <= UInt<8>("h00") @[quasar.scala 274:36] - _T_16.ar.bits.region <= UInt<4>("h00") @[quasar.scala 274:36] - _T_16.ar.bits.addr <= UInt<32>("h00") @[quasar.scala 274:36] - _T_16.ar.bits.id <= UInt<3>("h00") @[quasar.scala 274:36] - _T_16.ar.valid <= UInt<1>("h00") @[quasar.scala 274:36] - _T_16.ar.ready <= UInt<1>("h00") @[quasar.scala 274:36] - _T_16.b.bits.id <= UInt<3>("h00") @[quasar.scala 274:36] - _T_16.b.bits.resp <= UInt<2>("h00") @[quasar.scala 274:36] - _T_16.b.valid <= UInt<1>("h00") @[quasar.scala 274:36] - _T_16.b.ready <= UInt<1>("h00") @[quasar.scala 274:36] - _T_16.w.bits.last <= UInt<1>("h00") @[quasar.scala 274:36] - _T_16.w.bits.strb <= UInt<8>("h00") @[quasar.scala 274:36] - _T_16.w.bits.data <= UInt<64>("h00") @[quasar.scala 274:36] - _T_16.w.valid <= UInt<1>("h00") @[quasar.scala 274:36] - _T_16.w.ready <= UInt<1>("h00") @[quasar.scala 274:36] - _T_16.aw.bits.qos <= UInt<4>("h00") @[quasar.scala 274:36] - _T_16.aw.bits.prot <= UInt<3>("h00") @[quasar.scala 274:36] - _T_16.aw.bits.cache <= UInt<4>("h00") @[quasar.scala 274:36] - _T_16.aw.bits.lock <= UInt<1>("h00") @[quasar.scala 274:36] - _T_16.aw.bits.burst <= UInt<2>("h00") @[quasar.scala 274:36] - _T_16.aw.bits.size <= UInt<3>("h00") @[quasar.scala 274:36] - _T_16.aw.bits.len <= UInt<8>("h00") @[quasar.scala 274:36] - _T_16.aw.bits.region <= UInt<4>("h00") @[quasar.scala 274:36] - _T_16.aw.bits.addr <= UInt<32>("h00") @[quasar.scala 274:36] - _T_16.aw.bits.id <= UInt<3>("h00") @[quasar.scala 274:36] - _T_16.aw.valid <= UInt<1>("h00") @[quasar.scala 274:36] - _T_16.aw.ready <= UInt<1>("h00") @[quasar.scala 274:36] - _T_16.r.bits.last <= io.lsu_axi.r.bits.last @[quasar.scala 274:21] - _T_16.r.bits.resp <= io.lsu_axi.r.bits.resp @[quasar.scala 274:21] - _T_16.r.bits.data <= io.lsu_axi.r.bits.data @[quasar.scala 274:21] - _T_16.r.bits.id <= io.lsu_axi.r.bits.id @[quasar.scala 274:21] - _T_16.r.valid <= io.lsu_axi.r.valid @[quasar.scala 274:21] - io.lsu_axi.r.ready <= _T_16.r.ready @[quasar.scala 274:21] - io.lsu_axi.ar.bits.qos <= _T_16.ar.bits.qos @[quasar.scala 274:21] - io.lsu_axi.ar.bits.prot <= _T_16.ar.bits.prot @[quasar.scala 274:21] - io.lsu_axi.ar.bits.cache <= _T_16.ar.bits.cache @[quasar.scala 274:21] - io.lsu_axi.ar.bits.lock <= _T_16.ar.bits.lock @[quasar.scala 274:21] - io.lsu_axi.ar.bits.burst <= _T_16.ar.bits.burst @[quasar.scala 274:21] - io.lsu_axi.ar.bits.size <= _T_16.ar.bits.size @[quasar.scala 274:21] - io.lsu_axi.ar.bits.len <= _T_16.ar.bits.len @[quasar.scala 274:21] - io.lsu_axi.ar.bits.region <= _T_16.ar.bits.region @[quasar.scala 274:21] - io.lsu_axi.ar.bits.addr <= _T_16.ar.bits.addr @[quasar.scala 274:21] - io.lsu_axi.ar.bits.id <= _T_16.ar.bits.id @[quasar.scala 274:21] - io.lsu_axi.ar.valid <= _T_16.ar.valid @[quasar.scala 274:21] - _T_16.ar.ready <= io.lsu_axi.ar.ready @[quasar.scala 274:21] - _T_16.b.bits.id <= io.lsu_axi.b.bits.id @[quasar.scala 274:21] - _T_16.b.bits.resp <= io.lsu_axi.b.bits.resp @[quasar.scala 274:21] - _T_16.b.valid <= io.lsu_axi.b.valid @[quasar.scala 274:21] - io.lsu_axi.b.ready <= _T_16.b.ready @[quasar.scala 274:21] - io.lsu_axi.w.bits.last <= _T_16.w.bits.last @[quasar.scala 274:21] - io.lsu_axi.w.bits.strb <= _T_16.w.bits.strb @[quasar.scala 274:21] - io.lsu_axi.w.bits.data <= _T_16.w.bits.data @[quasar.scala 274:21] - io.lsu_axi.w.valid <= _T_16.w.valid @[quasar.scala 274:21] - _T_16.w.ready <= io.lsu_axi.w.ready @[quasar.scala 274:21] - io.lsu_axi.aw.bits.qos <= _T_16.aw.bits.qos @[quasar.scala 274:21] - io.lsu_axi.aw.bits.prot <= _T_16.aw.bits.prot @[quasar.scala 274:21] - io.lsu_axi.aw.bits.cache <= _T_16.aw.bits.cache @[quasar.scala 274:21] - io.lsu_axi.aw.bits.lock <= _T_16.aw.bits.lock @[quasar.scala 274:21] - io.lsu_axi.aw.bits.burst <= _T_16.aw.bits.burst @[quasar.scala 274:21] - io.lsu_axi.aw.bits.size <= _T_16.aw.bits.size @[quasar.scala 274:21] - io.lsu_axi.aw.bits.len <= _T_16.aw.bits.len @[quasar.scala 274:21] - io.lsu_axi.aw.bits.region <= _T_16.aw.bits.region @[quasar.scala 274:21] - io.lsu_axi.aw.bits.addr <= _T_16.aw.bits.addr @[quasar.scala 274:21] - io.lsu_axi.aw.bits.id <= _T_16.aw.bits.id @[quasar.scala 274:21] - io.lsu_axi.aw.valid <= _T_16.aw.valid @[quasar.scala 274:21] - _T_16.aw.ready <= io.lsu_axi.aw.ready @[quasar.scala 274:21] + wire _T_13 : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}} @[quasar.scala 277:42] + _T_13.out.hwdata <= UInt<64>("h00") @[quasar.scala 277:42] + _T_13.out.hwrite <= UInt<1>("h00") @[quasar.scala 277:42] + _T_13.out.htrans <= UInt<2>("h00") @[quasar.scala 277:42] + _T_13.out.hsize <= UInt<3>("h00") @[quasar.scala 277:42] + _T_13.out.hprot <= UInt<4>("h00") @[quasar.scala 277:42] + _T_13.out.hmastlock <= UInt<1>("h00") @[quasar.scala 277:42] + _T_13.out.hburst <= UInt<3>("h00") @[quasar.scala 277:42] + _T_13.out.haddr <= UInt<32>("h00") @[quasar.scala 277:42] + _T_13.in.hresp <= UInt<1>("h00") @[quasar.scala 277:42] + _T_13.in.hready <= UInt<1>("h00") @[quasar.scala 277:42] + _T_13.in.hrdata <= UInt<64>("h00") @[quasar.scala 277:42] + io.lsu_ahb.out.hwdata <= _T_13.out.hwdata @[quasar.scala 277:27] + io.lsu_ahb.out.hwrite <= _T_13.out.hwrite @[quasar.scala 277:27] + io.lsu_ahb.out.htrans <= _T_13.out.htrans @[quasar.scala 277:27] + io.lsu_ahb.out.hsize <= _T_13.out.hsize @[quasar.scala 277:27] + io.lsu_ahb.out.hprot <= _T_13.out.hprot @[quasar.scala 277:27] + io.lsu_ahb.out.hmastlock <= _T_13.out.hmastlock @[quasar.scala 277:27] + io.lsu_ahb.out.hburst <= _T_13.out.hburst @[quasar.scala 277:27] + io.lsu_ahb.out.haddr <= _T_13.out.haddr @[quasar.scala 277:27] + _T_13.in.hresp <= io.lsu_ahb.in.hresp @[quasar.scala 277:27] + _T_13.in.hready <= io.lsu_ahb.in.hready @[quasar.scala 277:27] + _T_13.in.hrdata <= io.lsu_ahb.in.hrdata @[quasar.scala 277:27] + wire _T_14 : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}} @[quasar.scala 278:42] + _T_14.out.hwdata <= UInt<64>("h00") @[quasar.scala 278:42] + _T_14.out.hwrite <= UInt<1>("h00") @[quasar.scala 278:42] + _T_14.out.htrans <= UInt<2>("h00") @[quasar.scala 278:42] + _T_14.out.hsize <= UInt<3>("h00") @[quasar.scala 278:42] + _T_14.out.hprot <= UInt<4>("h00") @[quasar.scala 278:42] + _T_14.out.hmastlock <= UInt<1>("h00") @[quasar.scala 278:42] + _T_14.out.hburst <= UInt<3>("h00") @[quasar.scala 278:42] + _T_14.out.haddr <= UInt<32>("h00") @[quasar.scala 278:42] + _T_14.in.hresp <= UInt<1>("h00") @[quasar.scala 278:42] + _T_14.in.hready <= UInt<1>("h00") @[quasar.scala 278:42] + _T_14.in.hrdata <= UInt<64>("h00") @[quasar.scala 278:42] + io.ifu_ahb.out.hwdata <= _T_14.out.hwdata @[quasar.scala 278:27] + io.ifu_ahb.out.hwrite <= _T_14.out.hwrite @[quasar.scala 278:27] + io.ifu_ahb.out.htrans <= _T_14.out.htrans @[quasar.scala 278:27] + io.ifu_ahb.out.hsize <= _T_14.out.hsize @[quasar.scala 278:27] + io.ifu_ahb.out.hprot <= _T_14.out.hprot @[quasar.scala 278:27] + io.ifu_ahb.out.hmastlock <= _T_14.out.hmastlock @[quasar.scala 278:27] + io.ifu_ahb.out.hburst <= _T_14.out.hburst @[quasar.scala 278:27] + io.ifu_ahb.out.haddr <= _T_14.out.haddr @[quasar.scala 278:27] + _T_14.in.hresp <= io.ifu_ahb.in.hresp @[quasar.scala 278:27] + _T_14.in.hready <= io.ifu_ahb.in.hready @[quasar.scala 278:27] + _T_14.in.hrdata <= io.ifu_ahb.in.hrdata @[quasar.scala 278:27] + wire _T_15 : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}} @[quasar.scala 279:42] + _T_15.out.hwdata <= UInt<64>("h00") @[quasar.scala 279:42] + _T_15.out.hwrite <= UInt<1>("h00") @[quasar.scala 279:42] + _T_15.out.htrans <= UInt<2>("h00") @[quasar.scala 279:42] + _T_15.out.hsize <= UInt<3>("h00") @[quasar.scala 279:42] + _T_15.out.hprot <= UInt<4>("h00") @[quasar.scala 279:42] + _T_15.out.hmastlock <= UInt<1>("h00") @[quasar.scala 279:42] + _T_15.out.hburst <= UInt<3>("h00") @[quasar.scala 279:42] + _T_15.out.haddr <= UInt<32>("h00") @[quasar.scala 279:42] + _T_15.in.hresp <= UInt<1>("h00") @[quasar.scala 279:42] + _T_15.in.hready <= UInt<1>("h00") @[quasar.scala 279:42] + _T_15.in.hrdata <= UInt<64>("h00") @[quasar.scala 279:42] + io.sb_ahb.out.hwdata <= _T_15.out.hwdata @[quasar.scala 279:27] + io.sb_ahb.out.hwrite <= _T_15.out.hwrite @[quasar.scala 279:27] + io.sb_ahb.out.htrans <= _T_15.out.htrans @[quasar.scala 279:27] + io.sb_ahb.out.hsize <= _T_15.out.hsize @[quasar.scala 279:27] + io.sb_ahb.out.hprot <= _T_15.out.hprot @[quasar.scala 279:27] + io.sb_ahb.out.hmastlock <= _T_15.out.hmastlock @[quasar.scala 279:27] + io.sb_ahb.out.hburst <= _T_15.out.hburst @[quasar.scala 279:27] + io.sb_ahb.out.haddr <= _T_15.out.haddr @[quasar.scala 279:27] + _T_15.in.hresp <= io.sb_ahb.in.hresp @[quasar.scala 279:27] + _T_15.in.hready <= io.sb_ahb.in.hready @[quasar.scala 279:27] + _T_15.in.hrdata <= io.sb_ahb.in.hrdata @[quasar.scala 279:27] + wire _T_16 : {flip sig : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, flip hsel : UInt<1>, flip hreadyin : UInt<1>} @[quasar.scala 280:42] + _T_16.hreadyin <= UInt<1>("h00") @[quasar.scala 280:42] + _T_16.hsel <= UInt<1>("h00") @[quasar.scala 280:42] + _T_16.sig.out.hwdata <= UInt<64>("h00") @[quasar.scala 280:42] + _T_16.sig.out.hwrite <= UInt<1>("h00") @[quasar.scala 280:42] + _T_16.sig.out.htrans <= UInt<2>("h00") @[quasar.scala 280:42] + _T_16.sig.out.hsize <= UInt<3>("h00") @[quasar.scala 280:42] + _T_16.sig.out.hprot <= UInt<4>("h00") @[quasar.scala 280:42] + _T_16.sig.out.hmastlock <= UInt<1>("h00") @[quasar.scala 280:42] + _T_16.sig.out.hburst <= UInt<3>("h00") @[quasar.scala 280:42] + _T_16.sig.out.haddr <= UInt<32>("h00") @[quasar.scala 280:42] + _T_16.sig.in.hresp <= UInt<1>("h00") @[quasar.scala 280:42] + _T_16.sig.in.hready <= UInt<1>("h00") @[quasar.scala 280:42] + _T_16.sig.in.hrdata <= UInt<64>("h00") @[quasar.scala 280:42] + _T_16.hreadyin <= io.dma_ahb.hreadyin @[quasar.scala 280:27] + _T_16.hsel <= io.dma_ahb.hsel @[quasar.scala 280:27] + _T_16.sig.out.hwdata <= io.dma_ahb.sig.out.hwdata @[quasar.scala 280:27] + _T_16.sig.out.hwrite <= io.dma_ahb.sig.out.hwrite @[quasar.scala 280:27] + _T_16.sig.out.htrans <= io.dma_ahb.sig.out.htrans @[quasar.scala 280:27] + _T_16.sig.out.hsize <= io.dma_ahb.sig.out.hsize @[quasar.scala 280:27] + _T_16.sig.out.hprot <= io.dma_ahb.sig.out.hprot @[quasar.scala 280:27] + _T_16.sig.out.hmastlock <= io.dma_ahb.sig.out.hmastlock @[quasar.scala 280:27] + _T_16.sig.out.hburst <= io.dma_ahb.sig.out.hburst @[quasar.scala 280:27] + _T_16.sig.out.haddr <= io.dma_ahb.sig.out.haddr @[quasar.scala 280:27] + io.dma_ahb.sig.in.hresp <= _T_16.sig.in.hresp @[quasar.scala 280:27] + io.dma_ahb.sig.in.hready <= _T_16.sig.in.hready @[quasar.scala 280:27] + io.dma_ahb.sig.in.hrdata <= _T_16.sig.in.hrdata @[quasar.scala 280:27] + io.dma_axi.r.bits.last <= dma_ctrl.io.dma_axi.r.bits.last @[quasar.scala 281:27] + io.dma_axi.r.bits.resp <= dma_ctrl.io.dma_axi.r.bits.resp @[quasar.scala 281:27] + io.dma_axi.r.bits.data <= dma_ctrl.io.dma_axi.r.bits.data @[quasar.scala 281:27] + io.dma_axi.r.bits.id <= dma_ctrl.io.dma_axi.r.bits.id @[quasar.scala 281:27] + io.dma_axi.r.valid <= dma_ctrl.io.dma_axi.r.valid @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.r.ready <= io.dma_axi.r.ready @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.ar.bits.qos <= io.dma_axi.ar.bits.qos @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.ar.bits.prot <= io.dma_axi.ar.bits.prot @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.ar.bits.cache <= io.dma_axi.ar.bits.cache @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.ar.bits.lock <= io.dma_axi.ar.bits.lock @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.ar.bits.burst <= io.dma_axi.ar.bits.burst @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.ar.bits.size <= io.dma_axi.ar.bits.size @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.ar.bits.len <= io.dma_axi.ar.bits.len @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.ar.bits.region <= io.dma_axi.ar.bits.region @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.ar.bits.addr <= io.dma_axi.ar.bits.addr @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.ar.bits.id <= io.dma_axi.ar.bits.id @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.ar.valid <= io.dma_axi.ar.valid @[quasar.scala 281:27] + io.dma_axi.ar.ready <= dma_ctrl.io.dma_axi.ar.ready @[quasar.scala 281:27] + io.dma_axi.b.bits.id <= dma_ctrl.io.dma_axi.b.bits.id @[quasar.scala 281:27] + io.dma_axi.b.bits.resp <= dma_ctrl.io.dma_axi.b.bits.resp @[quasar.scala 281:27] + io.dma_axi.b.valid <= dma_ctrl.io.dma_axi.b.valid @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.b.ready <= io.dma_axi.b.ready @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.w.bits.last <= io.dma_axi.w.bits.last @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.w.bits.strb <= io.dma_axi.w.bits.strb @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.w.bits.data <= io.dma_axi.w.bits.data @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.w.valid <= io.dma_axi.w.valid @[quasar.scala 281:27] + io.dma_axi.w.ready <= dma_ctrl.io.dma_axi.w.ready @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.aw.bits.qos <= io.dma_axi.aw.bits.qos @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.aw.bits.prot <= io.dma_axi.aw.bits.prot @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.aw.bits.cache <= io.dma_axi.aw.bits.cache @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.aw.bits.lock <= io.dma_axi.aw.bits.lock @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.aw.bits.burst <= io.dma_axi.aw.bits.burst @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.aw.bits.size <= io.dma_axi.aw.bits.size @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.aw.bits.len <= io.dma_axi.aw.bits.len @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.aw.bits.region <= io.dma_axi.aw.bits.region @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.aw.bits.addr <= io.dma_axi.aw.bits.addr @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.aw.bits.id <= io.dma_axi.aw.bits.id @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.aw.valid <= io.dma_axi.aw.valid @[quasar.scala 281:27] + io.dma_axi.aw.ready <= dma_ctrl.io.dma_axi.aw.ready @[quasar.scala 281:27] + dbg.io.sb_axi.r.bits.last <= io.sb_axi.r.bits.last @[quasar.scala 282:27] + dbg.io.sb_axi.r.bits.resp <= io.sb_axi.r.bits.resp @[quasar.scala 282:27] + dbg.io.sb_axi.r.bits.data <= io.sb_axi.r.bits.data @[quasar.scala 282:27] + dbg.io.sb_axi.r.bits.id <= io.sb_axi.r.bits.id @[quasar.scala 282:27] + dbg.io.sb_axi.r.valid <= io.sb_axi.r.valid @[quasar.scala 282:27] + io.sb_axi.r.ready <= dbg.io.sb_axi.r.ready @[quasar.scala 282:27] + io.sb_axi.ar.bits.qos <= dbg.io.sb_axi.ar.bits.qos @[quasar.scala 282:27] + io.sb_axi.ar.bits.prot <= dbg.io.sb_axi.ar.bits.prot @[quasar.scala 282:27] + io.sb_axi.ar.bits.cache <= dbg.io.sb_axi.ar.bits.cache @[quasar.scala 282:27] + io.sb_axi.ar.bits.lock <= dbg.io.sb_axi.ar.bits.lock @[quasar.scala 282:27] + io.sb_axi.ar.bits.burst <= dbg.io.sb_axi.ar.bits.burst @[quasar.scala 282:27] + io.sb_axi.ar.bits.size <= dbg.io.sb_axi.ar.bits.size @[quasar.scala 282:27] + io.sb_axi.ar.bits.len <= dbg.io.sb_axi.ar.bits.len @[quasar.scala 282:27] + io.sb_axi.ar.bits.region <= dbg.io.sb_axi.ar.bits.region @[quasar.scala 282:27] + io.sb_axi.ar.bits.addr <= dbg.io.sb_axi.ar.bits.addr @[quasar.scala 282:27] + io.sb_axi.ar.bits.id <= dbg.io.sb_axi.ar.bits.id @[quasar.scala 282:27] + io.sb_axi.ar.valid <= dbg.io.sb_axi.ar.valid @[quasar.scala 282:27] + dbg.io.sb_axi.ar.ready <= io.sb_axi.ar.ready @[quasar.scala 282:27] + dbg.io.sb_axi.b.bits.id <= io.sb_axi.b.bits.id @[quasar.scala 282:27] + dbg.io.sb_axi.b.bits.resp <= io.sb_axi.b.bits.resp @[quasar.scala 282:27] + dbg.io.sb_axi.b.valid <= io.sb_axi.b.valid @[quasar.scala 282:27] + io.sb_axi.b.ready <= dbg.io.sb_axi.b.ready @[quasar.scala 282:27] + io.sb_axi.w.bits.last <= dbg.io.sb_axi.w.bits.last @[quasar.scala 282:27] + io.sb_axi.w.bits.strb <= dbg.io.sb_axi.w.bits.strb @[quasar.scala 282:27] + io.sb_axi.w.bits.data <= dbg.io.sb_axi.w.bits.data @[quasar.scala 282:27] + io.sb_axi.w.valid <= dbg.io.sb_axi.w.valid @[quasar.scala 282:27] + dbg.io.sb_axi.w.ready <= io.sb_axi.w.ready @[quasar.scala 282:27] + io.sb_axi.aw.bits.qos <= dbg.io.sb_axi.aw.bits.qos @[quasar.scala 282:27] + io.sb_axi.aw.bits.prot <= dbg.io.sb_axi.aw.bits.prot @[quasar.scala 282:27] + io.sb_axi.aw.bits.cache <= dbg.io.sb_axi.aw.bits.cache @[quasar.scala 282:27] + io.sb_axi.aw.bits.lock <= dbg.io.sb_axi.aw.bits.lock @[quasar.scala 282:27] + io.sb_axi.aw.bits.burst <= dbg.io.sb_axi.aw.bits.burst @[quasar.scala 282:27] + io.sb_axi.aw.bits.size <= dbg.io.sb_axi.aw.bits.size @[quasar.scala 282:27] + io.sb_axi.aw.bits.len <= dbg.io.sb_axi.aw.bits.len @[quasar.scala 282:27] + io.sb_axi.aw.bits.region <= dbg.io.sb_axi.aw.bits.region @[quasar.scala 282:27] + io.sb_axi.aw.bits.addr <= dbg.io.sb_axi.aw.bits.addr @[quasar.scala 282:27] + io.sb_axi.aw.bits.id <= dbg.io.sb_axi.aw.bits.id @[quasar.scala 282:27] + io.sb_axi.aw.valid <= dbg.io.sb_axi.aw.valid @[quasar.scala 282:27] + dbg.io.sb_axi.aw.ready <= io.sb_axi.aw.ready @[quasar.scala 282:27] + ifu.io.ifu.r.bits.last <= io.ifu_axi.r.bits.last @[quasar.scala 283:27] + ifu.io.ifu.r.bits.resp <= io.ifu_axi.r.bits.resp @[quasar.scala 283:27] + ifu.io.ifu.r.bits.data <= io.ifu_axi.r.bits.data @[quasar.scala 283:27] + ifu.io.ifu.r.bits.id <= io.ifu_axi.r.bits.id @[quasar.scala 283:27] + ifu.io.ifu.r.valid <= io.ifu_axi.r.valid @[quasar.scala 283:27] + io.ifu_axi.r.ready <= ifu.io.ifu.r.ready @[quasar.scala 283:27] + io.ifu_axi.ar.bits.qos <= ifu.io.ifu.ar.bits.qos @[quasar.scala 283:27] + io.ifu_axi.ar.bits.prot <= ifu.io.ifu.ar.bits.prot @[quasar.scala 283:27] + io.ifu_axi.ar.bits.cache <= ifu.io.ifu.ar.bits.cache @[quasar.scala 283:27] + io.ifu_axi.ar.bits.lock <= ifu.io.ifu.ar.bits.lock @[quasar.scala 283:27] + io.ifu_axi.ar.bits.burst <= ifu.io.ifu.ar.bits.burst @[quasar.scala 283:27] + io.ifu_axi.ar.bits.size <= ifu.io.ifu.ar.bits.size @[quasar.scala 283:27] + io.ifu_axi.ar.bits.len <= ifu.io.ifu.ar.bits.len @[quasar.scala 283:27] + io.ifu_axi.ar.bits.region <= ifu.io.ifu.ar.bits.region @[quasar.scala 283:27] + io.ifu_axi.ar.bits.addr <= ifu.io.ifu.ar.bits.addr @[quasar.scala 283:27] + io.ifu_axi.ar.bits.id <= ifu.io.ifu.ar.bits.id @[quasar.scala 283:27] + io.ifu_axi.ar.valid <= ifu.io.ifu.ar.valid @[quasar.scala 283:27] + ifu.io.ifu.ar.ready <= io.ifu_axi.ar.ready @[quasar.scala 283:27] + ifu.io.ifu.b.bits.id <= io.ifu_axi.b.bits.id @[quasar.scala 283:27] + ifu.io.ifu.b.bits.resp <= io.ifu_axi.b.bits.resp @[quasar.scala 283:27] + ifu.io.ifu.b.valid <= io.ifu_axi.b.valid @[quasar.scala 283:27] + io.ifu_axi.b.ready <= ifu.io.ifu.b.ready @[quasar.scala 283:27] + io.ifu_axi.w.bits.last <= ifu.io.ifu.w.bits.last @[quasar.scala 283:27] + io.ifu_axi.w.bits.strb <= ifu.io.ifu.w.bits.strb @[quasar.scala 283:27] + io.ifu_axi.w.bits.data <= ifu.io.ifu.w.bits.data @[quasar.scala 283:27] + io.ifu_axi.w.valid <= ifu.io.ifu.w.valid @[quasar.scala 283:27] + ifu.io.ifu.w.ready <= io.ifu_axi.w.ready @[quasar.scala 283:27] + io.ifu_axi.aw.bits.qos <= ifu.io.ifu.aw.bits.qos @[quasar.scala 283:27] + io.ifu_axi.aw.bits.prot <= ifu.io.ifu.aw.bits.prot @[quasar.scala 283:27] + io.ifu_axi.aw.bits.cache <= ifu.io.ifu.aw.bits.cache @[quasar.scala 283:27] + io.ifu_axi.aw.bits.lock <= ifu.io.ifu.aw.bits.lock @[quasar.scala 283:27] + io.ifu_axi.aw.bits.burst <= ifu.io.ifu.aw.bits.burst @[quasar.scala 283:27] + io.ifu_axi.aw.bits.size <= ifu.io.ifu.aw.bits.size @[quasar.scala 283:27] + io.ifu_axi.aw.bits.len <= ifu.io.ifu.aw.bits.len @[quasar.scala 283:27] + io.ifu_axi.aw.bits.region <= ifu.io.ifu.aw.bits.region @[quasar.scala 283:27] + io.ifu_axi.aw.bits.addr <= ifu.io.ifu.aw.bits.addr @[quasar.scala 283:27] + io.ifu_axi.aw.bits.id <= ifu.io.ifu.aw.bits.id @[quasar.scala 283:27] + io.ifu_axi.aw.valid <= ifu.io.ifu.aw.valid @[quasar.scala 283:27] + ifu.io.ifu.aw.ready <= io.ifu_axi.aw.ready @[quasar.scala 283:27] + lsu.io.axi.r.bits.last <= io.lsu_axi.r.bits.last @[quasar.scala 284:27] + lsu.io.axi.r.bits.resp <= io.lsu_axi.r.bits.resp @[quasar.scala 284:27] + lsu.io.axi.r.bits.data <= io.lsu_axi.r.bits.data @[quasar.scala 284:27] + lsu.io.axi.r.bits.id <= io.lsu_axi.r.bits.id @[quasar.scala 284:27] + lsu.io.axi.r.valid <= io.lsu_axi.r.valid @[quasar.scala 284:27] + io.lsu_axi.r.ready <= lsu.io.axi.r.ready @[quasar.scala 284:27] + io.lsu_axi.ar.bits.qos <= lsu.io.axi.ar.bits.qos @[quasar.scala 284:27] + io.lsu_axi.ar.bits.prot <= lsu.io.axi.ar.bits.prot @[quasar.scala 284:27] + io.lsu_axi.ar.bits.cache <= lsu.io.axi.ar.bits.cache @[quasar.scala 284:27] + io.lsu_axi.ar.bits.lock <= lsu.io.axi.ar.bits.lock @[quasar.scala 284:27] + io.lsu_axi.ar.bits.burst <= lsu.io.axi.ar.bits.burst @[quasar.scala 284:27] + io.lsu_axi.ar.bits.size <= lsu.io.axi.ar.bits.size @[quasar.scala 284:27] + io.lsu_axi.ar.bits.len <= lsu.io.axi.ar.bits.len @[quasar.scala 284:27] + io.lsu_axi.ar.bits.region <= lsu.io.axi.ar.bits.region @[quasar.scala 284:27] + io.lsu_axi.ar.bits.addr <= lsu.io.axi.ar.bits.addr @[quasar.scala 284:27] + io.lsu_axi.ar.bits.id <= lsu.io.axi.ar.bits.id @[quasar.scala 284:27] + io.lsu_axi.ar.valid <= lsu.io.axi.ar.valid @[quasar.scala 284:27] + lsu.io.axi.ar.ready <= io.lsu_axi.ar.ready @[quasar.scala 284:27] + lsu.io.axi.b.bits.id <= io.lsu_axi.b.bits.id @[quasar.scala 284:27] + lsu.io.axi.b.bits.resp <= io.lsu_axi.b.bits.resp @[quasar.scala 284:27] + lsu.io.axi.b.valid <= io.lsu_axi.b.valid @[quasar.scala 284:27] + io.lsu_axi.b.ready <= lsu.io.axi.b.ready @[quasar.scala 284:27] + io.lsu_axi.w.bits.last <= lsu.io.axi.w.bits.last @[quasar.scala 284:27] + io.lsu_axi.w.bits.strb <= lsu.io.axi.w.bits.strb @[quasar.scala 284:27] + io.lsu_axi.w.bits.data <= lsu.io.axi.w.bits.data @[quasar.scala 284:27] + io.lsu_axi.w.valid <= lsu.io.axi.w.valid @[quasar.scala 284:27] + lsu.io.axi.w.ready <= io.lsu_axi.w.ready @[quasar.scala 284:27] + io.lsu_axi.aw.bits.qos <= lsu.io.axi.aw.bits.qos @[quasar.scala 284:27] + io.lsu_axi.aw.bits.prot <= lsu.io.axi.aw.bits.prot @[quasar.scala 284:27] + io.lsu_axi.aw.bits.cache <= lsu.io.axi.aw.bits.cache @[quasar.scala 284:27] + io.lsu_axi.aw.bits.lock <= lsu.io.axi.aw.bits.lock @[quasar.scala 284:27] + io.lsu_axi.aw.bits.burst <= lsu.io.axi.aw.bits.burst @[quasar.scala 284:27] + io.lsu_axi.aw.bits.size <= lsu.io.axi.aw.bits.size @[quasar.scala 284:27] + io.lsu_axi.aw.bits.len <= lsu.io.axi.aw.bits.len @[quasar.scala 284:27] + io.lsu_axi.aw.bits.region <= lsu.io.axi.aw.bits.region @[quasar.scala 284:27] + io.lsu_axi.aw.bits.addr <= lsu.io.axi.aw.bits.addr @[quasar.scala 284:27] + io.lsu_axi.aw.bits.id <= lsu.io.axi.aw.bits.id @[quasar.scala 284:27] + io.lsu_axi.aw.valid <= lsu.io.axi.aw.valid @[quasar.scala 284:27] + lsu.io.axi.aw.ready <= io.lsu_axi.aw.ready @[quasar.scala 284:27] module quasar_wrapper : input clock : Clock input reset : AsyncReset - output io : {flip dbg_rst_l : AsyncReset, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip jtag_id : UInt<31>, lsu_brg : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, ifu_brg : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, sb_brg : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, dma_brg : {flip sig : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, flip hsel : UInt<1>, flip hreadyin : UInt<1>}, flip lsu_bus_clk_en : UInt<1>, flip ifu_bus_clk_en : UInt<1>, flip dbg_bus_clk_en : UInt<1>, flip dma_bus_clk_en : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip extintsrc_req : UInt<31>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, flip jtag_tck : Clock, flip jtag_tms : UInt<1>, flip jtag_tdi : UInt<1>, flip jtag_trst_n : UInt<1>, jtag_tdo : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_halt_status : UInt<1>, o_debug_mode_status : UInt<1>, o_cpu_run_ack : UInt<1>, flip mbist_mode : UInt<1>, rv_trace_pkt : {rv_i_valid_ip : UInt<2>, rv_i_insn_ip : UInt<32>, rv_i_address_ip : UInt<32>, rv_i_exception_ip : UInt<2>, rv_i_ecause_ip : UInt<5>, rv_i_interrupt_ip : UInt<2>, rv_i_tval_ip : UInt<32>}, flip scan_mode : UInt<1>} + output io : {flip dbg_rst_l : AsyncReset, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip jtag_id : UInt<31>, lsu_brg : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ifu_brg : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, sb_brg : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dma_brg : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip lsu_bus_clk_en : UInt<1>, flip ifu_bus_clk_en : UInt<1>, flip dbg_bus_clk_en : UInt<1>, flip dma_bus_clk_en : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip extintsrc_req : UInt<31>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, flip jtag_tck : Clock, flip jtag_tms : UInt<1>, flip jtag_tdi : UInt<1>, flip jtag_trst_n : UInt<1>, jtag_tdo : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_halt_status : UInt<1>, o_debug_mode_status : UInt<1>, o_cpu_run_ack : UInt<1>, flip mbist_mode : UInt<1>, rv_trace_pkt : {rv_i_valid_ip : UInt<2>, rv_i_insn_ip : UInt<32>, rv_i_address_ip : UInt<32>, rv_i_exception_ip : UInt<2>, rv_i_ecause_ip : UInt<5>, rv_i_interrupt_ip : UInt<2>, rv_i_tval_ip : UInt<32>}, flip scan_mode : UInt<1>} inst mem of mem @[quasar_wrapper.scala 63:19] mem.scan_mode is invalid @@ -115011,368 +109905,258 @@ circuit quasar_wrapper : mem.iccm.correction_state <= core.io.iccm.correction_state @[quasar_wrapper.scala 93:16] mem.iccm.buf_correct_ecc <= core.io.iccm.buf_correct_ecc @[quasar_wrapper.scala 93:16] mem.iccm.rw_addr <= core.io.iccm.rw_addr @[quasar_wrapper.scala 93:16] - io.ifu_brg.out.hwdata <= core.io.ifu_ahb.out.hwdata @[quasar_wrapper.scala 108:21] - io.ifu_brg.out.hwrite <= core.io.ifu_ahb.out.hwrite @[quasar_wrapper.scala 108:21] - io.ifu_brg.out.htrans <= core.io.ifu_ahb.out.htrans @[quasar_wrapper.scala 108:21] - io.ifu_brg.out.hsize <= core.io.ifu_ahb.out.hsize @[quasar_wrapper.scala 108:21] - io.ifu_brg.out.hprot <= core.io.ifu_ahb.out.hprot @[quasar_wrapper.scala 108:21] - io.ifu_brg.out.hmastlock <= core.io.ifu_ahb.out.hmastlock @[quasar_wrapper.scala 108:21] - io.ifu_brg.out.hburst <= core.io.ifu_ahb.out.hburst @[quasar_wrapper.scala 108:21] - io.ifu_brg.out.haddr <= core.io.ifu_ahb.out.haddr @[quasar_wrapper.scala 108:21] - core.io.ifu_ahb.in.hresp <= io.ifu_brg.in.hresp @[quasar_wrapper.scala 108:21] - core.io.ifu_ahb.in.hready <= io.ifu_brg.in.hready @[quasar_wrapper.scala 108:21] - core.io.ifu_ahb.in.hrdata <= io.ifu_brg.in.hrdata @[quasar_wrapper.scala 108:21] - io.lsu_brg.out.hwdata <= core.io.lsu_ahb.out.hwdata @[quasar_wrapper.scala 109:21] - io.lsu_brg.out.hwrite <= core.io.lsu_ahb.out.hwrite @[quasar_wrapper.scala 109:21] - io.lsu_brg.out.htrans <= core.io.lsu_ahb.out.htrans @[quasar_wrapper.scala 109:21] - io.lsu_brg.out.hsize <= core.io.lsu_ahb.out.hsize @[quasar_wrapper.scala 109:21] - io.lsu_brg.out.hprot <= core.io.lsu_ahb.out.hprot @[quasar_wrapper.scala 109:21] - io.lsu_brg.out.hmastlock <= core.io.lsu_ahb.out.hmastlock @[quasar_wrapper.scala 109:21] - io.lsu_brg.out.hburst <= core.io.lsu_ahb.out.hburst @[quasar_wrapper.scala 109:21] - io.lsu_brg.out.haddr <= core.io.lsu_ahb.out.haddr @[quasar_wrapper.scala 109:21] - core.io.lsu_ahb.in.hresp <= io.lsu_brg.in.hresp @[quasar_wrapper.scala 109:21] - core.io.lsu_ahb.in.hready <= io.lsu_brg.in.hready @[quasar_wrapper.scala 109:21] - core.io.lsu_ahb.in.hrdata <= io.lsu_brg.in.hrdata @[quasar_wrapper.scala 109:21] - io.sb_brg.out.hwdata <= core.io.sb_ahb.out.hwdata @[quasar_wrapper.scala 110:20] - io.sb_brg.out.hwrite <= core.io.sb_ahb.out.hwrite @[quasar_wrapper.scala 110:20] - io.sb_brg.out.htrans <= core.io.sb_ahb.out.htrans @[quasar_wrapper.scala 110:20] - io.sb_brg.out.hsize <= core.io.sb_ahb.out.hsize @[quasar_wrapper.scala 110:20] - io.sb_brg.out.hprot <= core.io.sb_ahb.out.hprot @[quasar_wrapper.scala 110:20] - io.sb_brg.out.hmastlock <= core.io.sb_ahb.out.hmastlock @[quasar_wrapper.scala 110:20] - io.sb_brg.out.hburst <= core.io.sb_ahb.out.hburst @[quasar_wrapper.scala 110:20] - io.sb_brg.out.haddr <= core.io.sb_ahb.out.haddr @[quasar_wrapper.scala 110:20] - core.io.sb_ahb.in.hresp <= io.sb_brg.in.hresp @[quasar_wrapper.scala 110:20] - core.io.sb_ahb.in.hready <= io.sb_brg.in.hready @[quasar_wrapper.scala 110:20] - core.io.sb_ahb.in.hrdata <= io.sb_brg.in.hrdata @[quasar_wrapper.scala 110:20] - core.io.dma_ahb.hreadyin <= io.dma_brg.hreadyin @[quasar_wrapper.scala 111:21] - core.io.dma_ahb.hsel <= io.dma_brg.hsel @[quasar_wrapper.scala 111:21] - core.io.dma_ahb.sig.out.hwdata <= io.dma_brg.sig.out.hwdata @[quasar_wrapper.scala 111:21] - core.io.dma_ahb.sig.out.hwrite <= io.dma_brg.sig.out.hwrite @[quasar_wrapper.scala 111:21] - core.io.dma_ahb.sig.out.htrans <= io.dma_brg.sig.out.htrans @[quasar_wrapper.scala 111:21] - core.io.dma_ahb.sig.out.hsize <= io.dma_brg.sig.out.hsize @[quasar_wrapper.scala 111:21] - core.io.dma_ahb.sig.out.hprot <= io.dma_brg.sig.out.hprot @[quasar_wrapper.scala 111:21] - core.io.dma_ahb.sig.out.hmastlock <= io.dma_brg.sig.out.hmastlock @[quasar_wrapper.scala 111:21] - core.io.dma_ahb.sig.out.hburst <= io.dma_brg.sig.out.hburst @[quasar_wrapper.scala 111:21] - core.io.dma_ahb.sig.out.haddr <= io.dma_brg.sig.out.haddr @[quasar_wrapper.scala 111:21] - io.dma_brg.sig.in.hresp <= core.io.dma_ahb.sig.in.hresp @[quasar_wrapper.scala 111:21] - io.dma_brg.sig.in.hready <= core.io.dma_ahb.sig.in.hready @[quasar_wrapper.scala 111:21] - io.dma_brg.sig.in.hrdata <= core.io.dma_ahb.sig.in.hrdata @[quasar_wrapper.scala 111:21] - wire _T : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar_wrapper.scala 113:36] - _T.r.bits.last <= UInt<1>("h00") @[quasar_wrapper.scala 113:36] - _T.r.bits.resp <= UInt<2>("h00") @[quasar_wrapper.scala 113:36] - _T.r.bits.data <= UInt<64>("h00") @[quasar_wrapper.scala 113:36] - _T.r.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 113:36] - _T.r.valid <= UInt<1>("h00") @[quasar_wrapper.scala 113:36] - _T.r.ready <= UInt<1>("h00") @[quasar_wrapper.scala 113:36] - _T.ar.bits.qos <= UInt<4>("h00") @[quasar_wrapper.scala 113:36] - _T.ar.bits.prot <= UInt<3>("h00") @[quasar_wrapper.scala 113:36] - _T.ar.bits.cache <= UInt<4>("h00") @[quasar_wrapper.scala 113:36] - _T.ar.bits.lock <= UInt<1>("h00") @[quasar_wrapper.scala 113:36] - _T.ar.bits.burst <= UInt<2>("h00") @[quasar_wrapper.scala 113:36] - _T.ar.bits.size <= UInt<3>("h00") @[quasar_wrapper.scala 113:36] - _T.ar.bits.len <= UInt<8>("h00") @[quasar_wrapper.scala 113:36] - _T.ar.bits.region <= UInt<4>("h00") @[quasar_wrapper.scala 113:36] - _T.ar.bits.addr <= UInt<32>("h00") @[quasar_wrapper.scala 113:36] - _T.ar.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 113:36] - _T.ar.valid <= UInt<1>("h00") @[quasar_wrapper.scala 113:36] - _T.ar.ready <= UInt<1>("h00") @[quasar_wrapper.scala 113:36] - _T.b.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 113:36] - _T.b.bits.resp <= UInt<2>("h00") @[quasar_wrapper.scala 113:36] - _T.b.valid <= UInt<1>("h00") @[quasar_wrapper.scala 113:36] - _T.b.ready <= UInt<1>("h00") @[quasar_wrapper.scala 113:36] - _T.w.bits.last <= UInt<1>("h00") @[quasar_wrapper.scala 113:36] - _T.w.bits.strb <= UInt<8>("h00") @[quasar_wrapper.scala 113:36] - _T.w.bits.data <= UInt<64>("h00") @[quasar_wrapper.scala 113:36] - _T.w.valid <= UInt<1>("h00") @[quasar_wrapper.scala 113:36] - _T.w.ready <= UInt<1>("h00") @[quasar_wrapper.scala 113:36] - _T.aw.bits.qos <= UInt<4>("h00") @[quasar_wrapper.scala 113:36] - _T.aw.bits.prot <= UInt<3>("h00") @[quasar_wrapper.scala 113:36] - _T.aw.bits.cache <= UInt<4>("h00") @[quasar_wrapper.scala 113:36] - _T.aw.bits.lock <= UInt<1>("h00") @[quasar_wrapper.scala 113:36] - _T.aw.bits.burst <= UInt<2>("h00") @[quasar_wrapper.scala 113:36] - _T.aw.bits.size <= UInt<3>("h00") @[quasar_wrapper.scala 113:36] - _T.aw.bits.len <= UInt<8>("h00") @[quasar_wrapper.scala 113:36] - _T.aw.bits.region <= UInt<4>("h00") @[quasar_wrapper.scala 113:36] - _T.aw.bits.addr <= UInt<32>("h00") @[quasar_wrapper.scala 113:36] - _T.aw.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 113:36] - _T.aw.valid <= UInt<1>("h00") @[quasar_wrapper.scala 113:36] - _T.aw.ready <= UInt<1>("h00") @[quasar_wrapper.scala 113:36] - core.io.lsu_axi.r.bits.last <= _T.r.bits.last @[quasar_wrapper.scala 113:21] - core.io.lsu_axi.r.bits.resp <= _T.r.bits.resp @[quasar_wrapper.scala 113:21] - core.io.lsu_axi.r.bits.data <= _T.r.bits.data @[quasar_wrapper.scala 113:21] - core.io.lsu_axi.r.bits.id <= _T.r.bits.id @[quasar_wrapper.scala 113:21] - core.io.lsu_axi.r.valid <= _T.r.valid @[quasar_wrapper.scala 113:21] - _T.r.ready <= core.io.lsu_axi.r.ready @[quasar_wrapper.scala 113:21] - _T.ar.bits.qos <= core.io.lsu_axi.ar.bits.qos @[quasar_wrapper.scala 113:21] - _T.ar.bits.prot <= core.io.lsu_axi.ar.bits.prot @[quasar_wrapper.scala 113:21] - _T.ar.bits.cache <= core.io.lsu_axi.ar.bits.cache @[quasar_wrapper.scala 113:21] - _T.ar.bits.lock <= core.io.lsu_axi.ar.bits.lock @[quasar_wrapper.scala 113:21] - _T.ar.bits.burst <= core.io.lsu_axi.ar.bits.burst @[quasar_wrapper.scala 113:21] - _T.ar.bits.size <= core.io.lsu_axi.ar.bits.size @[quasar_wrapper.scala 113:21] - _T.ar.bits.len <= core.io.lsu_axi.ar.bits.len @[quasar_wrapper.scala 113:21] - _T.ar.bits.region <= core.io.lsu_axi.ar.bits.region @[quasar_wrapper.scala 113:21] - _T.ar.bits.addr <= core.io.lsu_axi.ar.bits.addr @[quasar_wrapper.scala 113:21] - _T.ar.bits.id <= core.io.lsu_axi.ar.bits.id @[quasar_wrapper.scala 113:21] - _T.ar.valid <= core.io.lsu_axi.ar.valid @[quasar_wrapper.scala 113:21] - core.io.lsu_axi.ar.ready <= _T.ar.ready @[quasar_wrapper.scala 113:21] - core.io.lsu_axi.b.bits.id <= _T.b.bits.id @[quasar_wrapper.scala 113:21] - core.io.lsu_axi.b.bits.resp <= _T.b.bits.resp @[quasar_wrapper.scala 113:21] - core.io.lsu_axi.b.valid <= _T.b.valid @[quasar_wrapper.scala 113:21] - _T.b.ready <= core.io.lsu_axi.b.ready @[quasar_wrapper.scala 113:21] - _T.w.bits.last <= core.io.lsu_axi.w.bits.last @[quasar_wrapper.scala 113:21] - _T.w.bits.strb <= core.io.lsu_axi.w.bits.strb @[quasar_wrapper.scala 113:21] - _T.w.bits.data <= core.io.lsu_axi.w.bits.data @[quasar_wrapper.scala 113:21] - _T.w.valid <= core.io.lsu_axi.w.valid @[quasar_wrapper.scala 113:21] - core.io.lsu_axi.w.ready <= _T.w.ready @[quasar_wrapper.scala 113:21] - _T.aw.bits.qos <= core.io.lsu_axi.aw.bits.qos @[quasar_wrapper.scala 113:21] - _T.aw.bits.prot <= core.io.lsu_axi.aw.bits.prot @[quasar_wrapper.scala 113:21] - _T.aw.bits.cache <= core.io.lsu_axi.aw.bits.cache @[quasar_wrapper.scala 113:21] - _T.aw.bits.lock <= core.io.lsu_axi.aw.bits.lock @[quasar_wrapper.scala 113:21] - _T.aw.bits.burst <= core.io.lsu_axi.aw.bits.burst @[quasar_wrapper.scala 113:21] - _T.aw.bits.size <= core.io.lsu_axi.aw.bits.size @[quasar_wrapper.scala 113:21] - _T.aw.bits.len <= core.io.lsu_axi.aw.bits.len @[quasar_wrapper.scala 113:21] - _T.aw.bits.region <= core.io.lsu_axi.aw.bits.region @[quasar_wrapper.scala 113:21] - _T.aw.bits.addr <= core.io.lsu_axi.aw.bits.addr @[quasar_wrapper.scala 113:21] - _T.aw.bits.id <= core.io.lsu_axi.aw.bits.id @[quasar_wrapper.scala 113:21] - _T.aw.valid <= core.io.lsu_axi.aw.valid @[quasar_wrapper.scala 113:21] - core.io.lsu_axi.aw.ready <= _T.aw.ready @[quasar_wrapper.scala 113:21] - wire _T_1 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar_wrapper.scala 114:36] - _T_1.r.bits.last <= UInt<1>("h00") @[quasar_wrapper.scala 114:36] - _T_1.r.bits.resp <= UInt<2>("h00") @[quasar_wrapper.scala 114:36] - _T_1.r.bits.data <= UInt<64>("h00") @[quasar_wrapper.scala 114:36] - _T_1.r.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 114:36] - _T_1.r.valid <= UInt<1>("h00") @[quasar_wrapper.scala 114:36] - _T_1.r.ready <= UInt<1>("h00") @[quasar_wrapper.scala 114:36] - _T_1.ar.bits.qos <= UInt<4>("h00") @[quasar_wrapper.scala 114:36] - _T_1.ar.bits.prot <= UInt<3>("h00") @[quasar_wrapper.scala 114:36] - _T_1.ar.bits.cache <= UInt<4>("h00") @[quasar_wrapper.scala 114:36] - _T_1.ar.bits.lock <= UInt<1>("h00") @[quasar_wrapper.scala 114:36] - _T_1.ar.bits.burst <= UInt<2>("h00") @[quasar_wrapper.scala 114:36] - _T_1.ar.bits.size <= UInt<3>("h00") @[quasar_wrapper.scala 114:36] - _T_1.ar.bits.len <= UInt<8>("h00") @[quasar_wrapper.scala 114:36] - _T_1.ar.bits.region <= UInt<4>("h00") @[quasar_wrapper.scala 114:36] - _T_1.ar.bits.addr <= UInt<32>("h00") @[quasar_wrapper.scala 114:36] - _T_1.ar.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 114:36] - _T_1.ar.valid <= UInt<1>("h00") @[quasar_wrapper.scala 114:36] - _T_1.ar.ready <= UInt<1>("h00") @[quasar_wrapper.scala 114:36] - _T_1.b.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 114:36] - _T_1.b.bits.resp <= UInt<2>("h00") @[quasar_wrapper.scala 114:36] - _T_1.b.valid <= UInt<1>("h00") @[quasar_wrapper.scala 114:36] - _T_1.b.ready <= UInt<1>("h00") @[quasar_wrapper.scala 114:36] - _T_1.w.bits.last <= UInt<1>("h00") @[quasar_wrapper.scala 114:36] - _T_1.w.bits.strb <= UInt<8>("h00") @[quasar_wrapper.scala 114:36] - _T_1.w.bits.data <= UInt<64>("h00") @[quasar_wrapper.scala 114:36] - _T_1.w.valid <= UInt<1>("h00") @[quasar_wrapper.scala 114:36] - _T_1.w.ready <= UInt<1>("h00") @[quasar_wrapper.scala 114:36] - _T_1.aw.bits.qos <= UInt<4>("h00") @[quasar_wrapper.scala 114:36] - _T_1.aw.bits.prot <= UInt<3>("h00") @[quasar_wrapper.scala 114:36] - _T_1.aw.bits.cache <= UInt<4>("h00") @[quasar_wrapper.scala 114:36] - _T_1.aw.bits.lock <= UInt<1>("h00") @[quasar_wrapper.scala 114:36] - _T_1.aw.bits.burst <= UInt<2>("h00") @[quasar_wrapper.scala 114:36] - _T_1.aw.bits.size <= UInt<3>("h00") @[quasar_wrapper.scala 114:36] - _T_1.aw.bits.len <= UInt<8>("h00") @[quasar_wrapper.scala 114:36] - _T_1.aw.bits.region <= UInt<4>("h00") @[quasar_wrapper.scala 114:36] - _T_1.aw.bits.addr <= UInt<32>("h00") @[quasar_wrapper.scala 114:36] - _T_1.aw.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 114:36] - _T_1.aw.valid <= UInt<1>("h00") @[quasar_wrapper.scala 114:36] - _T_1.aw.ready <= UInt<1>("h00") @[quasar_wrapper.scala 114:36] - core.io.ifu_axi.r.bits.last <= _T_1.r.bits.last @[quasar_wrapper.scala 114:21] - core.io.ifu_axi.r.bits.resp <= _T_1.r.bits.resp @[quasar_wrapper.scala 114:21] - core.io.ifu_axi.r.bits.data <= _T_1.r.bits.data @[quasar_wrapper.scala 114:21] - core.io.ifu_axi.r.bits.id <= _T_1.r.bits.id @[quasar_wrapper.scala 114:21] - core.io.ifu_axi.r.valid <= _T_1.r.valid @[quasar_wrapper.scala 114:21] - _T_1.r.ready <= core.io.ifu_axi.r.ready @[quasar_wrapper.scala 114:21] - _T_1.ar.bits.qos <= core.io.ifu_axi.ar.bits.qos @[quasar_wrapper.scala 114:21] - _T_1.ar.bits.prot <= core.io.ifu_axi.ar.bits.prot @[quasar_wrapper.scala 114:21] - _T_1.ar.bits.cache <= core.io.ifu_axi.ar.bits.cache @[quasar_wrapper.scala 114:21] - _T_1.ar.bits.lock <= core.io.ifu_axi.ar.bits.lock @[quasar_wrapper.scala 114:21] - _T_1.ar.bits.burst <= core.io.ifu_axi.ar.bits.burst @[quasar_wrapper.scala 114:21] - _T_1.ar.bits.size <= core.io.ifu_axi.ar.bits.size @[quasar_wrapper.scala 114:21] - _T_1.ar.bits.len <= core.io.ifu_axi.ar.bits.len @[quasar_wrapper.scala 114:21] - _T_1.ar.bits.region <= core.io.ifu_axi.ar.bits.region @[quasar_wrapper.scala 114:21] - _T_1.ar.bits.addr <= core.io.ifu_axi.ar.bits.addr @[quasar_wrapper.scala 114:21] - _T_1.ar.bits.id <= core.io.ifu_axi.ar.bits.id @[quasar_wrapper.scala 114:21] - _T_1.ar.valid <= core.io.ifu_axi.ar.valid @[quasar_wrapper.scala 114:21] - core.io.ifu_axi.ar.ready <= _T_1.ar.ready @[quasar_wrapper.scala 114:21] - core.io.ifu_axi.b.bits.id <= _T_1.b.bits.id @[quasar_wrapper.scala 114:21] - core.io.ifu_axi.b.bits.resp <= _T_1.b.bits.resp @[quasar_wrapper.scala 114:21] - core.io.ifu_axi.b.valid <= _T_1.b.valid @[quasar_wrapper.scala 114:21] - _T_1.b.ready <= core.io.ifu_axi.b.ready @[quasar_wrapper.scala 114:21] - _T_1.w.bits.last <= core.io.ifu_axi.w.bits.last @[quasar_wrapper.scala 114:21] - _T_1.w.bits.strb <= core.io.ifu_axi.w.bits.strb @[quasar_wrapper.scala 114:21] - _T_1.w.bits.data <= core.io.ifu_axi.w.bits.data @[quasar_wrapper.scala 114:21] - _T_1.w.valid <= core.io.ifu_axi.w.valid @[quasar_wrapper.scala 114:21] - core.io.ifu_axi.w.ready <= _T_1.w.ready @[quasar_wrapper.scala 114:21] - _T_1.aw.bits.qos <= core.io.ifu_axi.aw.bits.qos @[quasar_wrapper.scala 114:21] - _T_1.aw.bits.prot <= core.io.ifu_axi.aw.bits.prot @[quasar_wrapper.scala 114:21] - _T_1.aw.bits.cache <= core.io.ifu_axi.aw.bits.cache @[quasar_wrapper.scala 114:21] - _T_1.aw.bits.lock <= core.io.ifu_axi.aw.bits.lock @[quasar_wrapper.scala 114:21] - _T_1.aw.bits.burst <= core.io.ifu_axi.aw.bits.burst @[quasar_wrapper.scala 114:21] - _T_1.aw.bits.size <= core.io.ifu_axi.aw.bits.size @[quasar_wrapper.scala 114:21] - _T_1.aw.bits.len <= core.io.ifu_axi.aw.bits.len @[quasar_wrapper.scala 114:21] - _T_1.aw.bits.region <= core.io.ifu_axi.aw.bits.region @[quasar_wrapper.scala 114:21] - _T_1.aw.bits.addr <= core.io.ifu_axi.aw.bits.addr @[quasar_wrapper.scala 114:21] - _T_1.aw.bits.id <= core.io.ifu_axi.aw.bits.id @[quasar_wrapper.scala 114:21] - _T_1.aw.valid <= core.io.ifu_axi.aw.valid @[quasar_wrapper.scala 114:21] - core.io.ifu_axi.aw.ready <= _T_1.aw.ready @[quasar_wrapper.scala 114:21] - wire _T_2 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar_wrapper.scala 115:36] - _T_2.r.bits.last <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] - _T_2.r.bits.resp <= UInt<2>("h00") @[quasar_wrapper.scala 115:36] - _T_2.r.bits.data <= UInt<64>("h00") @[quasar_wrapper.scala 115:36] - _T_2.r.bits.id <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] - _T_2.r.valid <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] - _T_2.r.ready <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] - _T_2.ar.bits.qos <= UInt<4>("h00") @[quasar_wrapper.scala 115:36] - _T_2.ar.bits.prot <= UInt<3>("h00") @[quasar_wrapper.scala 115:36] - _T_2.ar.bits.cache <= UInt<4>("h00") @[quasar_wrapper.scala 115:36] - _T_2.ar.bits.lock <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] - _T_2.ar.bits.burst <= UInt<2>("h00") @[quasar_wrapper.scala 115:36] - _T_2.ar.bits.size <= UInt<3>("h00") @[quasar_wrapper.scala 115:36] - _T_2.ar.bits.len <= UInt<8>("h00") @[quasar_wrapper.scala 115:36] - _T_2.ar.bits.region <= UInt<4>("h00") @[quasar_wrapper.scala 115:36] - _T_2.ar.bits.addr <= UInt<32>("h00") @[quasar_wrapper.scala 115:36] - _T_2.ar.bits.id <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] - _T_2.ar.valid <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] - _T_2.ar.ready <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] - _T_2.b.bits.id <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] - _T_2.b.bits.resp <= UInt<2>("h00") @[quasar_wrapper.scala 115:36] - _T_2.b.valid <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] - _T_2.b.ready <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] - _T_2.w.bits.last <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] - _T_2.w.bits.strb <= UInt<8>("h00") @[quasar_wrapper.scala 115:36] - _T_2.w.bits.data <= UInt<64>("h00") @[quasar_wrapper.scala 115:36] - _T_2.w.valid <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] - _T_2.w.ready <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] - _T_2.aw.bits.qos <= UInt<4>("h00") @[quasar_wrapper.scala 115:36] - _T_2.aw.bits.prot <= UInt<3>("h00") @[quasar_wrapper.scala 115:36] - _T_2.aw.bits.cache <= UInt<4>("h00") @[quasar_wrapper.scala 115:36] - _T_2.aw.bits.lock <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] - _T_2.aw.bits.burst <= UInt<2>("h00") @[quasar_wrapper.scala 115:36] - _T_2.aw.bits.size <= UInt<3>("h00") @[quasar_wrapper.scala 115:36] - _T_2.aw.bits.len <= UInt<8>("h00") @[quasar_wrapper.scala 115:36] - _T_2.aw.bits.region <= UInt<4>("h00") @[quasar_wrapper.scala 115:36] - _T_2.aw.bits.addr <= UInt<32>("h00") @[quasar_wrapper.scala 115:36] - _T_2.aw.bits.id <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] - _T_2.aw.valid <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] - _T_2.aw.ready <= UInt<1>("h00") @[quasar_wrapper.scala 115:36] - core.io.sb_axi.r.bits.last <= _T_2.r.bits.last @[quasar_wrapper.scala 115:21] - core.io.sb_axi.r.bits.resp <= _T_2.r.bits.resp @[quasar_wrapper.scala 115:21] - core.io.sb_axi.r.bits.data <= _T_2.r.bits.data @[quasar_wrapper.scala 115:21] - core.io.sb_axi.r.bits.id <= _T_2.r.bits.id @[quasar_wrapper.scala 115:21] - core.io.sb_axi.r.valid <= _T_2.r.valid @[quasar_wrapper.scala 115:21] - _T_2.r.ready <= core.io.sb_axi.r.ready @[quasar_wrapper.scala 115:21] - _T_2.ar.bits.qos <= core.io.sb_axi.ar.bits.qos @[quasar_wrapper.scala 115:21] - _T_2.ar.bits.prot <= core.io.sb_axi.ar.bits.prot @[quasar_wrapper.scala 115:21] - _T_2.ar.bits.cache <= core.io.sb_axi.ar.bits.cache @[quasar_wrapper.scala 115:21] - _T_2.ar.bits.lock <= core.io.sb_axi.ar.bits.lock @[quasar_wrapper.scala 115:21] - _T_2.ar.bits.burst <= core.io.sb_axi.ar.bits.burst @[quasar_wrapper.scala 115:21] - _T_2.ar.bits.size <= core.io.sb_axi.ar.bits.size @[quasar_wrapper.scala 115:21] - _T_2.ar.bits.len <= core.io.sb_axi.ar.bits.len @[quasar_wrapper.scala 115:21] - _T_2.ar.bits.region <= core.io.sb_axi.ar.bits.region @[quasar_wrapper.scala 115:21] - _T_2.ar.bits.addr <= core.io.sb_axi.ar.bits.addr @[quasar_wrapper.scala 115:21] - _T_2.ar.bits.id <= core.io.sb_axi.ar.bits.id @[quasar_wrapper.scala 115:21] - _T_2.ar.valid <= core.io.sb_axi.ar.valid @[quasar_wrapper.scala 115:21] - core.io.sb_axi.ar.ready <= _T_2.ar.ready @[quasar_wrapper.scala 115:21] - core.io.sb_axi.b.bits.id <= _T_2.b.bits.id @[quasar_wrapper.scala 115:21] - core.io.sb_axi.b.bits.resp <= _T_2.b.bits.resp @[quasar_wrapper.scala 115:21] - core.io.sb_axi.b.valid <= _T_2.b.valid @[quasar_wrapper.scala 115:21] - _T_2.b.ready <= core.io.sb_axi.b.ready @[quasar_wrapper.scala 115:21] - _T_2.w.bits.last <= core.io.sb_axi.w.bits.last @[quasar_wrapper.scala 115:21] - _T_2.w.bits.strb <= core.io.sb_axi.w.bits.strb @[quasar_wrapper.scala 115:21] - _T_2.w.bits.data <= core.io.sb_axi.w.bits.data @[quasar_wrapper.scala 115:21] - _T_2.w.valid <= core.io.sb_axi.w.valid @[quasar_wrapper.scala 115:21] - core.io.sb_axi.w.ready <= _T_2.w.ready @[quasar_wrapper.scala 115:21] - _T_2.aw.bits.qos <= core.io.sb_axi.aw.bits.qos @[quasar_wrapper.scala 115:21] - _T_2.aw.bits.prot <= core.io.sb_axi.aw.bits.prot @[quasar_wrapper.scala 115:21] - _T_2.aw.bits.cache <= core.io.sb_axi.aw.bits.cache @[quasar_wrapper.scala 115:21] - _T_2.aw.bits.lock <= core.io.sb_axi.aw.bits.lock @[quasar_wrapper.scala 115:21] - _T_2.aw.bits.burst <= core.io.sb_axi.aw.bits.burst @[quasar_wrapper.scala 115:21] - _T_2.aw.bits.size <= core.io.sb_axi.aw.bits.size @[quasar_wrapper.scala 115:21] - _T_2.aw.bits.len <= core.io.sb_axi.aw.bits.len @[quasar_wrapper.scala 115:21] - _T_2.aw.bits.region <= core.io.sb_axi.aw.bits.region @[quasar_wrapper.scala 115:21] - _T_2.aw.bits.addr <= core.io.sb_axi.aw.bits.addr @[quasar_wrapper.scala 115:21] - _T_2.aw.bits.id <= core.io.sb_axi.aw.bits.id @[quasar_wrapper.scala 115:21] - _T_2.aw.valid <= core.io.sb_axi.aw.valid @[quasar_wrapper.scala 115:21] - core.io.sb_axi.aw.ready <= _T_2.aw.ready @[quasar_wrapper.scala 115:21] - wire _T_3 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar_wrapper.scala 116:36] - _T_3.r.bits.last <= UInt<1>("h00") @[quasar_wrapper.scala 116:36] - _T_3.r.bits.resp <= UInt<2>("h00") @[quasar_wrapper.scala 116:36] - _T_3.r.bits.data <= UInt<64>("h00") @[quasar_wrapper.scala 116:36] - _T_3.r.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 116:36] - _T_3.r.valid <= UInt<1>("h00") @[quasar_wrapper.scala 116:36] - _T_3.r.ready <= UInt<1>("h00") @[quasar_wrapper.scala 116:36] - _T_3.ar.bits.qos <= UInt<4>("h00") @[quasar_wrapper.scala 116:36] - _T_3.ar.bits.prot <= UInt<3>("h00") @[quasar_wrapper.scala 116:36] - _T_3.ar.bits.cache <= UInt<4>("h00") @[quasar_wrapper.scala 116:36] - _T_3.ar.bits.lock <= UInt<1>("h00") @[quasar_wrapper.scala 116:36] - _T_3.ar.bits.burst <= UInt<2>("h00") @[quasar_wrapper.scala 116:36] - _T_3.ar.bits.size <= UInt<3>("h00") @[quasar_wrapper.scala 116:36] - _T_3.ar.bits.len <= UInt<8>("h00") @[quasar_wrapper.scala 116:36] - _T_3.ar.bits.region <= UInt<4>("h00") @[quasar_wrapper.scala 116:36] - _T_3.ar.bits.addr <= UInt<32>("h00") @[quasar_wrapper.scala 116:36] - _T_3.ar.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 116:36] - _T_3.ar.valid <= UInt<1>("h00") @[quasar_wrapper.scala 116:36] - _T_3.ar.ready <= UInt<1>("h00") @[quasar_wrapper.scala 116:36] - _T_3.b.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 116:36] - _T_3.b.bits.resp <= UInt<2>("h00") @[quasar_wrapper.scala 116:36] - _T_3.b.valid <= UInt<1>("h00") @[quasar_wrapper.scala 116:36] - _T_3.b.ready <= UInt<1>("h00") @[quasar_wrapper.scala 116:36] - _T_3.w.bits.last <= UInt<1>("h00") @[quasar_wrapper.scala 116:36] - _T_3.w.bits.strb <= UInt<8>("h00") @[quasar_wrapper.scala 116:36] - _T_3.w.bits.data <= UInt<64>("h00") @[quasar_wrapper.scala 116:36] - _T_3.w.valid <= UInt<1>("h00") @[quasar_wrapper.scala 116:36] - _T_3.w.ready <= UInt<1>("h00") @[quasar_wrapper.scala 116:36] - _T_3.aw.bits.qos <= UInt<4>("h00") @[quasar_wrapper.scala 116:36] - _T_3.aw.bits.prot <= UInt<3>("h00") @[quasar_wrapper.scala 116:36] - _T_3.aw.bits.cache <= UInt<4>("h00") @[quasar_wrapper.scala 116:36] - _T_3.aw.bits.lock <= UInt<1>("h00") @[quasar_wrapper.scala 116:36] - _T_3.aw.bits.burst <= UInt<2>("h00") @[quasar_wrapper.scala 116:36] - _T_3.aw.bits.size <= UInt<3>("h00") @[quasar_wrapper.scala 116:36] - _T_3.aw.bits.len <= UInt<8>("h00") @[quasar_wrapper.scala 116:36] - _T_3.aw.bits.region <= UInt<4>("h00") @[quasar_wrapper.scala 116:36] - _T_3.aw.bits.addr <= UInt<32>("h00") @[quasar_wrapper.scala 116:36] - _T_3.aw.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 116:36] - _T_3.aw.valid <= UInt<1>("h00") @[quasar_wrapper.scala 116:36] - _T_3.aw.ready <= UInt<1>("h00") @[quasar_wrapper.scala 116:36] - _T_3.r.bits.last <= core.io.dma_axi.r.bits.last @[quasar_wrapper.scala 116:21] - _T_3.r.bits.resp <= core.io.dma_axi.r.bits.resp @[quasar_wrapper.scala 116:21] - _T_3.r.bits.data <= core.io.dma_axi.r.bits.data @[quasar_wrapper.scala 116:21] - _T_3.r.bits.id <= core.io.dma_axi.r.bits.id @[quasar_wrapper.scala 116:21] - _T_3.r.valid <= core.io.dma_axi.r.valid @[quasar_wrapper.scala 116:21] - core.io.dma_axi.r.ready <= _T_3.r.ready @[quasar_wrapper.scala 116:21] - core.io.dma_axi.ar.bits.qos <= _T_3.ar.bits.qos @[quasar_wrapper.scala 116:21] - core.io.dma_axi.ar.bits.prot <= _T_3.ar.bits.prot @[quasar_wrapper.scala 116:21] - core.io.dma_axi.ar.bits.cache <= _T_3.ar.bits.cache @[quasar_wrapper.scala 116:21] - core.io.dma_axi.ar.bits.lock <= _T_3.ar.bits.lock @[quasar_wrapper.scala 116:21] - core.io.dma_axi.ar.bits.burst <= _T_3.ar.bits.burst @[quasar_wrapper.scala 116:21] - core.io.dma_axi.ar.bits.size <= _T_3.ar.bits.size @[quasar_wrapper.scala 116:21] - core.io.dma_axi.ar.bits.len <= _T_3.ar.bits.len @[quasar_wrapper.scala 116:21] - core.io.dma_axi.ar.bits.region <= _T_3.ar.bits.region @[quasar_wrapper.scala 116:21] - core.io.dma_axi.ar.bits.addr <= _T_3.ar.bits.addr @[quasar_wrapper.scala 116:21] - core.io.dma_axi.ar.bits.id <= _T_3.ar.bits.id @[quasar_wrapper.scala 116:21] - core.io.dma_axi.ar.valid <= _T_3.ar.valid @[quasar_wrapper.scala 116:21] - _T_3.ar.ready <= core.io.dma_axi.ar.ready @[quasar_wrapper.scala 116:21] - _T_3.b.bits.id <= core.io.dma_axi.b.bits.id @[quasar_wrapper.scala 116:21] - _T_3.b.bits.resp <= core.io.dma_axi.b.bits.resp @[quasar_wrapper.scala 116:21] - _T_3.b.valid <= core.io.dma_axi.b.valid @[quasar_wrapper.scala 116:21] - core.io.dma_axi.b.ready <= _T_3.b.ready @[quasar_wrapper.scala 116:21] - core.io.dma_axi.w.bits.last <= _T_3.w.bits.last @[quasar_wrapper.scala 116:21] - core.io.dma_axi.w.bits.strb <= _T_3.w.bits.strb @[quasar_wrapper.scala 116:21] - core.io.dma_axi.w.bits.data <= _T_3.w.bits.data @[quasar_wrapper.scala 116:21] - core.io.dma_axi.w.valid <= _T_3.w.valid @[quasar_wrapper.scala 116:21] - _T_3.w.ready <= core.io.dma_axi.w.ready @[quasar_wrapper.scala 116:21] - core.io.dma_axi.aw.bits.qos <= _T_3.aw.bits.qos @[quasar_wrapper.scala 116:21] - core.io.dma_axi.aw.bits.prot <= _T_3.aw.bits.prot @[quasar_wrapper.scala 116:21] - core.io.dma_axi.aw.bits.cache <= _T_3.aw.bits.cache @[quasar_wrapper.scala 116:21] - core.io.dma_axi.aw.bits.lock <= _T_3.aw.bits.lock @[quasar_wrapper.scala 116:21] - core.io.dma_axi.aw.bits.burst <= _T_3.aw.bits.burst @[quasar_wrapper.scala 116:21] - core.io.dma_axi.aw.bits.size <= _T_3.aw.bits.size @[quasar_wrapper.scala 116:21] - core.io.dma_axi.aw.bits.len <= _T_3.aw.bits.len @[quasar_wrapper.scala 116:21] - core.io.dma_axi.aw.bits.region <= _T_3.aw.bits.region @[quasar_wrapper.scala 116:21] - core.io.dma_axi.aw.bits.addr <= _T_3.aw.bits.addr @[quasar_wrapper.scala 116:21] - core.io.dma_axi.aw.bits.id <= _T_3.aw.bits.id @[quasar_wrapper.scala 116:21] - core.io.dma_axi.aw.valid <= _T_3.aw.valid @[quasar_wrapper.scala 116:21] - _T_3.aw.ready <= core.io.dma_axi.aw.ready @[quasar_wrapper.scala 116:21] + wire _T : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}} @[quasar_wrapper.scala 97:36] + _T.out.hwdata <= UInt<64>("h00") @[quasar_wrapper.scala 97:36] + _T.out.hwrite <= UInt<1>("h00") @[quasar_wrapper.scala 97:36] + _T.out.htrans <= UInt<2>("h00") @[quasar_wrapper.scala 97:36] + _T.out.hsize <= UInt<3>("h00") @[quasar_wrapper.scala 97:36] + _T.out.hprot <= UInt<4>("h00") @[quasar_wrapper.scala 97:36] + _T.out.hmastlock <= UInt<1>("h00") @[quasar_wrapper.scala 97:36] + _T.out.hburst <= UInt<3>("h00") @[quasar_wrapper.scala 97:36] + _T.out.haddr <= UInt<32>("h00") @[quasar_wrapper.scala 97:36] + _T.in.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 97:36] + _T.in.hready <= UInt<1>("h00") @[quasar_wrapper.scala 97:36] + _T.in.hrdata <= UInt<64>("h00") @[quasar_wrapper.scala 97:36] + _T.out.hwdata <= core.io.ifu_ahb.out.hwdata @[quasar_wrapper.scala 97:21] + _T.out.hwrite <= core.io.ifu_ahb.out.hwrite @[quasar_wrapper.scala 97:21] + _T.out.htrans <= core.io.ifu_ahb.out.htrans @[quasar_wrapper.scala 97:21] + _T.out.hsize <= core.io.ifu_ahb.out.hsize @[quasar_wrapper.scala 97:21] + _T.out.hprot <= core.io.ifu_ahb.out.hprot @[quasar_wrapper.scala 97:21] + _T.out.hmastlock <= core.io.ifu_ahb.out.hmastlock @[quasar_wrapper.scala 97:21] + _T.out.hburst <= core.io.ifu_ahb.out.hburst @[quasar_wrapper.scala 97:21] + _T.out.haddr <= core.io.ifu_ahb.out.haddr @[quasar_wrapper.scala 97:21] + core.io.ifu_ahb.in.hresp <= _T.in.hresp @[quasar_wrapper.scala 97:21] + core.io.ifu_ahb.in.hready <= _T.in.hready @[quasar_wrapper.scala 97:21] + core.io.ifu_ahb.in.hrdata <= _T.in.hrdata @[quasar_wrapper.scala 97:21] + wire _T_1 : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}} @[quasar_wrapper.scala 98:36] + _T_1.out.hwdata <= UInt<64>("h00") @[quasar_wrapper.scala 98:36] + _T_1.out.hwrite <= UInt<1>("h00") @[quasar_wrapper.scala 98:36] + _T_1.out.htrans <= UInt<2>("h00") @[quasar_wrapper.scala 98:36] + _T_1.out.hsize <= UInt<3>("h00") @[quasar_wrapper.scala 98:36] + _T_1.out.hprot <= UInt<4>("h00") @[quasar_wrapper.scala 98:36] + _T_1.out.hmastlock <= UInt<1>("h00") @[quasar_wrapper.scala 98:36] + _T_1.out.hburst <= UInt<3>("h00") @[quasar_wrapper.scala 98:36] + _T_1.out.haddr <= UInt<32>("h00") @[quasar_wrapper.scala 98:36] + _T_1.in.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 98:36] + _T_1.in.hready <= UInt<1>("h00") @[quasar_wrapper.scala 98:36] + _T_1.in.hrdata <= UInt<64>("h00") @[quasar_wrapper.scala 98:36] + _T_1.out.hwdata <= core.io.lsu_ahb.out.hwdata @[quasar_wrapper.scala 98:21] + _T_1.out.hwrite <= core.io.lsu_ahb.out.hwrite @[quasar_wrapper.scala 98:21] + _T_1.out.htrans <= core.io.lsu_ahb.out.htrans @[quasar_wrapper.scala 98:21] + _T_1.out.hsize <= core.io.lsu_ahb.out.hsize @[quasar_wrapper.scala 98:21] + _T_1.out.hprot <= core.io.lsu_ahb.out.hprot @[quasar_wrapper.scala 98:21] + _T_1.out.hmastlock <= core.io.lsu_ahb.out.hmastlock @[quasar_wrapper.scala 98:21] + _T_1.out.hburst <= core.io.lsu_ahb.out.hburst @[quasar_wrapper.scala 98:21] + _T_1.out.haddr <= core.io.lsu_ahb.out.haddr @[quasar_wrapper.scala 98:21] + core.io.lsu_ahb.in.hresp <= _T_1.in.hresp @[quasar_wrapper.scala 98:21] + core.io.lsu_ahb.in.hready <= _T_1.in.hready @[quasar_wrapper.scala 98:21] + core.io.lsu_ahb.in.hrdata <= _T_1.in.hrdata @[quasar_wrapper.scala 98:21] + wire _T_2 : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}} @[quasar_wrapper.scala 99:36] + _T_2.out.hwdata <= UInt<64>("h00") @[quasar_wrapper.scala 99:36] + _T_2.out.hwrite <= UInt<1>("h00") @[quasar_wrapper.scala 99:36] + _T_2.out.htrans <= UInt<2>("h00") @[quasar_wrapper.scala 99:36] + _T_2.out.hsize <= UInt<3>("h00") @[quasar_wrapper.scala 99:36] + _T_2.out.hprot <= UInt<4>("h00") @[quasar_wrapper.scala 99:36] + _T_2.out.hmastlock <= UInt<1>("h00") @[quasar_wrapper.scala 99:36] + _T_2.out.hburst <= UInt<3>("h00") @[quasar_wrapper.scala 99:36] + _T_2.out.haddr <= UInt<32>("h00") @[quasar_wrapper.scala 99:36] + _T_2.in.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 99:36] + _T_2.in.hready <= UInt<1>("h00") @[quasar_wrapper.scala 99:36] + _T_2.in.hrdata <= UInt<64>("h00") @[quasar_wrapper.scala 99:36] + _T_2.out.hwdata <= core.io.sb_ahb.out.hwdata @[quasar_wrapper.scala 99:21] + _T_2.out.hwrite <= core.io.sb_ahb.out.hwrite @[quasar_wrapper.scala 99:21] + _T_2.out.htrans <= core.io.sb_ahb.out.htrans @[quasar_wrapper.scala 99:21] + _T_2.out.hsize <= core.io.sb_ahb.out.hsize @[quasar_wrapper.scala 99:21] + _T_2.out.hprot <= core.io.sb_ahb.out.hprot @[quasar_wrapper.scala 99:21] + _T_2.out.hmastlock <= core.io.sb_ahb.out.hmastlock @[quasar_wrapper.scala 99:21] + _T_2.out.hburst <= core.io.sb_ahb.out.hburst @[quasar_wrapper.scala 99:21] + _T_2.out.haddr <= core.io.sb_ahb.out.haddr @[quasar_wrapper.scala 99:21] + core.io.sb_ahb.in.hresp <= _T_2.in.hresp @[quasar_wrapper.scala 99:21] + core.io.sb_ahb.in.hready <= _T_2.in.hready @[quasar_wrapper.scala 99:21] + core.io.sb_ahb.in.hrdata <= _T_2.in.hrdata @[quasar_wrapper.scala 99:21] + wire _T_3 : {flip sig : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, flip hsel : UInt<1>, flip hreadyin : UInt<1>} @[quasar_wrapper.scala 100:36] + _T_3.hreadyin <= UInt<1>("h00") @[quasar_wrapper.scala 100:36] + _T_3.hsel <= UInt<1>("h00") @[quasar_wrapper.scala 100:36] + _T_3.sig.out.hwdata <= UInt<64>("h00") @[quasar_wrapper.scala 100:36] + _T_3.sig.out.hwrite <= UInt<1>("h00") @[quasar_wrapper.scala 100:36] + _T_3.sig.out.htrans <= UInt<2>("h00") @[quasar_wrapper.scala 100:36] + _T_3.sig.out.hsize <= UInt<3>("h00") @[quasar_wrapper.scala 100:36] + _T_3.sig.out.hprot <= UInt<4>("h00") @[quasar_wrapper.scala 100:36] + _T_3.sig.out.hmastlock <= UInt<1>("h00") @[quasar_wrapper.scala 100:36] + _T_3.sig.out.hburst <= UInt<3>("h00") @[quasar_wrapper.scala 100:36] + _T_3.sig.out.haddr <= UInt<32>("h00") @[quasar_wrapper.scala 100:36] + _T_3.sig.in.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 100:36] + _T_3.sig.in.hready <= UInt<1>("h00") @[quasar_wrapper.scala 100:36] + _T_3.sig.in.hrdata <= UInt<64>("h00") @[quasar_wrapper.scala 100:36] + core.io.dma_ahb.hreadyin <= _T_3.hreadyin @[quasar_wrapper.scala 100:21] + core.io.dma_ahb.hsel <= _T_3.hsel @[quasar_wrapper.scala 100:21] + core.io.dma_ahb.sig.out.hwdata <= _T_3.sig.out.hwdata @[quasar_wrapper.scala 100:21] + core.io.dma_ahb.sig.out.hwrite <= _T_3.sig.out.hwrite @[quasar_wrapper.scala 100:21] + core.io.dma_ahb.sig.out.htrans <= _T_3.sig.out.htrans @[quasar_wrapper.scala 100:21] + core.io.dma_ahb.sig.out.hsize <= _T_3.sig.out.hsize @[quasar_wrapper.scala 100:21] + core.io.dma_ahb.sig.out.hprot <= _T_3.sig.out.hprot @[quasar_wrapper.scala 100:21] + core.io.dma_ahb.sig.out.hmastlock <= _T_3.sig.out.hmastlock @[quasar_wrapper.scala 100:21] + core.io.dma_ahb.sig.out.hburst <= _T_3.sig.out.hburst @[quasar_wrapper.scala 100:21] + core.io.dma_ahb.sig.out.haddr <= _T_3.sig.out.haddr @[quasar_wrapper.scala 100:21] + _T_3.sig.in.hresp <= core.io.dma_ahb.sig.in.hresp @[quasar_wrapper.scala 100:21] + _T_3.sig.in.hready <= core.io.dma_ahb.sig.in.hready @[quasar_wrapper.scala 100:21] + _T_3.sig.in.hrdata <= core.io.dma_ahb.sig.in.hrdata @[quasar_wrapper.scala 100:21] + core.io.lsu_axi.r.bits.last <= io.lsu_brg.r.bits.last @[quasar_wrapper.scala 102:21] + core.io.lsu_axi.r.bits.resp <= io.lsu_brg.r.bits.resp @[quasar_wrapper.scala 102:21] + core.io.lsu_axi.r.bits.data <= io.lsu_brg.r.bits.data @[quasar_wrapper.scala 102:21] + core.io.lsu_axi.r.bits.id <= io.lsu_brg.r.bits.id @[quasar_wrapper.scala 102:21] + core.io.lsu_axi.r.valid <= io.lsu_brg.r.valid @[quasar_wrapper.scala 102:21] + io.lsu_brg.r.ready <= core.io.lsu_axi.r.ready @[quasar_wrapper.scala 102:21] + io.lsu_brg.ar.bits.qos <= core.io.lsu_axi.ar.bits.qos @[quasar_wrapper.scala 102:21] + io.lsu_brg.ar.bits.prot <= core.io.lsu_axi.ar.bits.prot @[quasar_wrapper.scala 102:21] + io.lsu_brg.ar.bits.cache <= core.io.lsu_axi.ar.bits.cache @[quasar_wrapper.scala 102:21] + io.lsu_brg.ar.bits.lock <= core.io.lsu_axi.ar.bits.lock @[quasar_wrapper.scala 102:21] + io.lsu_brg.ar.bits.burst <= core.io.lsu_axi.ar.bits.burst @[quasar_wrapper.scala 102:21] + io.lsu_brg.ar.bits.size <= core.io.lsu_axi.ar.bits.size @[quasar_wrapper.scala 102:21] + io.lsu_brg.ar.bits.len <= core.io.lsu_axi.ar.bits.len @[quasar_wrapper.scala 102:21] + io.lsu_brg.ar.bits.region <= core.io.lsu_axi.ar.bits.region @[quasar_wrapper.scala 102:21] + io.lsu_brg.ar.bits.addr <= core.io.lsu_axi.ar.bits.addr @[quasar_wrapper.scala 102:21] + io.lsu_brg.ar.bits.id <= core.io.lsu_axi.ar.bits.id @[quasar_wrapper.scala 102:21] + io.lsu_brg.ar.valid <= core.io.lsu_axi.ar.valid @[quasar_wrapper.scala 102:21] + core.io.lsu_axi.ar.ready <= io.lsu_brg.ar.ready @[quasar_wrapper.scala 102:21] + core.io.lsu_axi.b.bits.id <= io.lsu_brg.b.bits.id @[quasar_wrapper.scala 102:21] + core.io.lsu_axi.b.bits.resp <= io.lsu_brg.b.bits.resp @[quasar_wrapper.scala 102:21] + core.io.lsu_axi.b.valid <= io.lsu_brg.b.valid @[quasar_wrapper.scala 102:21] + io.lsu_brg.b.ready <= core.io.lsu_axi.b.ready @[quasar_wrapper.scala 102:21] + io.lsu_brg.w.bits.last <= core.io.lsu_axi.w.bits.last @[quasar_wrapper.scala 102:21] + io.lsu_brg.w.bits.strb <= core.io.lsu_axi.w.bits.strb @[quasar_wrapper.scala 102:21] + io.lsu_brg.w.bits.data <= core.io.lsu_axi.w.bits.data @[quasar_wrapper.scala 102:21] + io.lsu_brg.w.valid <= core.io.lsu_axi.w.valid @[quasar_wrapper.scala 102:21] + core.io.lsu_axi.w.ready <= io.lsu_brg.w.ready @[quasar_wrapper.scala 102:21] + io.lsu_brg.aw.bits.qos <= core.io.lsu_axi.aw.bits.qos @[quasar_wrapper.scala 102:21] + io.lsu_brg.aw.bits.prot <= core.io.lsu_axi.aw.bits.prot @[quasar_wrapper.scala 102:21] + io.lsu_brg.aw.bits.cache <= core.io.lsu_axi.aw.bits.cache @[quasar_wrapper.scala 102:21] + io.lsu_brg.aw.bits.lock <= core.io.lsu_axi.aw.bits.lock @[quasar_wrapper.scala 102:21] + io.lsu_brg.aw.bits.burst <= core.io.lsu_axi.aw.bits.burst @[quasar_wrapper.scala 102:21] + io.lsu_brg.aw.bits.size <= core.io.lsu_axi.aw.bits.size @[quasar_wrapper.scala 102:21] + io.lsu_brg.aw.bits.len <= core.io.lsu_axi.aw.bits.len @[quasar_wrapper.scala 102:21] + io.lsu_brg.aw.bits.region <= core.io.lsu_axi.aw.bits.region @[quasar_wrapper.scala 102:21] + io.lsu_brg.aw.bits.addr <= core.io.lsu_axi.aw.bits.addr @[quasar_wrapper.scala 102:21] + io.lsu_brg.aw.bits.id <= core.io.lsu_axi.aw.bits.id @[quasar_wrapper.scala 102:21] + io.lsu_brg.aw.valid <= core.io.lsu_axi.aw.valid @[quasar_wrapper.scala 102:21] + core.io.lsu_axi.aw.ready <= io.lsu_brg.aw.ready @[quasar_wrapper.scala 102:21] + core.io.ifu_axi.r.bits.last <= io.ifu_brg.r.bits.last @[quasar_wrapper.scala 103:21] + core.io.ifu_axi.r.bits.resp <= io.ifu_brg.r.bits.resp @[quasar_wrapper.scala 103:21] + core.io.ifu_axi.r.bits.data <= io.ifu_brg.r.bits.data @[quasar_wrapper.scala 103:21] + core.io.ifu_axi.r.bits.id <= io.ifu_brg.r.bits.id @[quasar_wrapper.scala 103:21] + core.io.ifu_axi.r.valid <= io.ifu_brg.r.valid @[quasar_wrapper.scala 103:21] + io.ifu_brg.r.ready <= core.io.ifu_axi.r.ready @[quasar_wrapper.scala 103:21] + io.ifu_brg.ar.bits.qos <= core.io.ifu_axi.ar.bits.qos @[quasar_wrapper.scala 103:21] + io.ifu_brg.ar.bits.prot <= core.io.ifu_axi.ar.bits.prot @[quasar_wrapper.scala 103:21] + io.ifu_brg.ar.bits.cache <= core.io.ifu_axi.ar.bits.cache @[quasar_wrapper.scala 103:21] + io.ifu_brg.ar.bits.lock <= core.io.ifu_axi.ar.bits.lock @[quasar_wrapper.scala 103:21] + io.ifu_brg.ar.bits.burst <= core.io.ifu_axi.ar.bits.burst @[quasar_wrapper.scala 103:21] + io.ifu_brg.ar.bits.size <= core.io.ifu_axi.ar.bits.size @[quasar_wrapper.scala 103:21] + io.ifu_brg.ar.bits.len <= core.io.ifu_axi.ar.bits.len @[quasar_wrapper.scala 103:21] + io.ifu_brg.ar.bits.region <= core.io.ifu_axi.ar.bits.region @[quasar_wrapper.scala 103:21] + io.ifu_brg.ar.bits.addr <= core.io.ifu_axi.ar.bits.addr @[quasar_wrapper.scala 103:21] + io.ifu_brg.ar.bits.id <= core.io.ifu_axi.ar.bits.id @[quasar_wrapper.scala 103:21] + io.ifu_brg.ar.valid <= core.io.ifu_axi.ar.valid @[quasar_wrapper.scala 103:21] + core.io.ifu_axi.ar.ready <= io.ifu_brg.ar.ready @[quasar_wrapper.scala 103:21] + core.io.ifu_axi.b.bits.id <= io.ifu_brg.b.bits.id @[quasar_wrapper.scala 103:21] + core.io.ifu_axi.b.bits.resp <= io.ifu_brg.b.bits.resp @[quasar_wrapper.scala 103:21] + core.io.ifu_axi.b.valid <= io.ifu_brg.b.valid @[quasar_wrapper.scala 103:21] + io.ifu_brg.b.ready <= core.io.ifu_axi.b.ready @[quasar_wrapper.scala 103:21] + io.ifu_brg.w.bits.last <= core.io.ifu_axi.w.bits.last @[quasar_wrapper.scala 103:21] + io.ifu_brg.w.bits.strb <= core.io.ifu_axi.w.bits.strb @[quasar_wrapper.scala 103:21] + io.ifu_brg.w.bits.data <= core.io.ifu_axi.w.bits.data @[quasar_wrapper.scala 103:21] + io.ifu_brg.w.valid <= core.io.ifu_axi.w.valid @[quasar_wrapper.scala 103:21] + core.io.ifu_axi.w.ready <= io.ifu_brg.w.ready @[quasar_wrapper.scala 103:21] + io.ifu_brg.aw.bits.qos <= core.io.ifu_axi.aw.bits.qos @[quasar_wrapper.scala 103:21] + io.ifu_brg.aw.bits.prot <= core.io.ifu_axi.aw.bits.prot @[quasar_wrapper.scala 103:21] + io.ifu_brg.aw.bits.cache <= core.io.ifu_axi.aw.bits.cache @[quasar_wrapper.scala 103:21] + io.ifu_brg.aw.bits.lock <= core.io.ifu_axi.aw.bits.lock @[quasar_wrapper.scala 103:21] + io.ifu_brg.aw.bits.burst <= core.io.ifu_axi.aw.bits.burst @[quasar_wrapper.scala 103:21] + io.ifu_brg.aw.bits.size <= core.io.ifu_axi.aw.bits.size @[quasar_wrapper.scala 103:21] + io.ifu_brg.aw.bits.len <= core.io.ifu_axi.aw.bits.len @[quasar_wrapper.scala 103:21] + io.ifu_brg.aw.bits.region <= core.io.ifu_axi.aw.bits.region @[quasar_wrapper.scala 103:21] + io.ifu_brg.aw.bits.addr <= core.io.ifu_axi.aw.bits.addr @[quasar_wrapper.scala 103:21] + io.ifu_brg.aw.bits.id <= core.io.ifu_axi.aw.bits.id @[quasar_wrapper.scala 103:21] + io.ifu_brg.aw.valid <= core.io.ifu_axi.aw.valid @[quasar_wrapper.scala 103:21] + core.io.ifu_axi.aw.ready <= io.ifu_brg.aw.ready @[quasar_wrapper.scala 103:21] + core.io.sb_axi.r.bits.last <= io.sb_brg.r.bits.last @[quasar_wrapper.scala 104:21] + core.io.sb_axi.r.bits.resp <= io.sb_brg.r.bits.resp @[quasar_wrapper.scala 104:21] + core.io.sb_axi.r.bits.data <= io.sb_brg.r.bits.data @[quasar_wrapper.scala 104:21] + core.io.sb_axi.r.bits.id <= io.sb_brg.r.bits.id @[quasar_wrapper.scala 104:21] + core.io.sb_axi.r.valid <= io.sb_brg.r.valid @[quasar_wrapper.scala 104:21] + io.sb_brg.r.ready <= core.io.sb_axi.r.ready @[quasar_wrapper.scala 104:21] + io.sb_brg.ar.bits.qos <= core.io.sb_axi.ar.bits.qos @[quasar_wrapper.scala 104:21] + io.sb_brg.ar.bits.prot <= core.io.sb_axi.ar.bits.prot @[quasar_wrapper.scala 104:21] + io.sb_brg.ar.bits.cache <= core.io.sb_axi.ar.bits.cache @[quasar_wrapper.scala 104:21] + io.sb_brg.ar.bits.lock <= core.io.sb_axi.ar.bits.lock @[quasar_wrapper.scala 104:21] + io.sb_brg.ar.bits.burst <= core.io.sb_axi.ar.bits.burst @[quasar_wrapper.scala 104:21] + io.sb_brg.ar.bits.size <= core.io.sb_axi.ar.bits.size @[quasar_wrapper.scala 104:21] + io.sb_brg.ar.bits.len <= core.io.sb_axi.ar.bits.len @[quasar_wrapper.scala 104:21] + io.sb_brg.ar.bits.region <= core.io.sb_axi.ar.bits.region @[quasar_wrapper.scala 104:21] + io.sb_brg.ar.bits.addr <= core.io.sb_axi.ar.bits.addr @[quasar_wrapper.scala 104:21] + io.sb_brg.ar.bits.id <= core.io.sb_axi.ar.bits.id @[quasar_wrapper.scala 104:21] + io.sb_brg.ar.valid <= core.io.sb_axi.ar.valid @[quasar_wrapper.scala 104:21] + core.io.sb_axi.ar.ready <= io.sb_brg.ar.ready @[quasar_wrapper.scala 104:21] + core.io.sb_axi.b.bits.id <= io.sb_brg.b.bits.id @[quasar_wrapper.scala 104:21] + core.io.sb_axi.b.bits.resp <= io.sb_brg.b.bits.resp @[quasar_wrapper.scala 104:21] + core.io.sb_axi.b.valid <= io.sb_brg.b.valid @[quasar_wrapper.scala 104:21] + io.sb_brg.b.ready <= core.io.sb_axi.b.ready @[quasar_wrapper.scala 104:21] + io.sb_brg.w.bits.last <= core.io.sb_axi.w.bits.last @[quasar_wrapper.scala 104:21] + io.sb_brg.w.bits.strb <= core.io.sb_axi.w.bits.strb @[quasar_wrapper.scala 104:21] + io.sb_brg.w.bits.data <= core.io.sb_axi.w.bits.data @[quasar_wrapper.scala 104:21] + io.sb_brg.w.valid <= core.io.sb_axi.w.valid @[quasar_wrapper.scala 104:21] + core.io.sb_axi.w.ready <= io.sb_brg.w.ready @[quasar_wrapper.scala 104:21] + io.sb_brg.aw.bits.qos <= core.io.sb_axi.aw.bits.qos @[quasar_wrapper.scala 104:21] + io.sb_brg.aw.bits.prot <= core.io.sb_axi.aw.bits.prot @[quasar_wrapper.scala 104:21] + io.sb_brg.aw.bits.cache <= core.io.sb_axi.aw.bits.cache @[quasar_wrapper.scala 104:21] + io.sb_brg.aw.bits.lock <= core.io.sb_axi.aw.bits.lock @[quasar_wrapper.scala 104:21] + io.sb_brg.aw.bits.burst <= core.io.sb_axi.aw.bits.burst @[quasar_wrapper.scala 104:21] + io.sb_brg.aw.bits.size <= core.io.sb_axi.aw.bits.size @[quasar_wrapper.scala 104:21] + io.sb_brg.aw.bits.len <= core.io.sb_axi.aw.bits.len @[quasar_wrapper.scala 104:21] + io.sb_brg.aw.bits.region <= core.io.sb_axi.aw.bits.region @[quasar_wrapper.scala 104:21] + io.sb_brg.aw.bits.addr <= core.io.sb_axi.aw.bits.addr @[quasar_wrapper.scala 104:21] + io.sb_brg.aw.bits.id <= core.io.sb_axi.aw.bits.id @[quasar_wrapper.scala 104:21] + io.sb_brg.aw.valid <= core.io.sb_axi.aw.valid @[quasar_wrapper.scala 104:21] + core.io.sb_axi.aw.ready <= io.sb_brg.aw.ready @[quasar_wrapper.scala 104:21] + io.dma_brg.r.bits.last <= core.io.dma_axi.r.bits.last @[quasar_wrapper.scala 105:21] + io.dma_brg.r.bits.resp <= core.io.dma_axi.r.bits.resp @[quasar_wrapper.scala 105:21] + io.dma_brg.r.bits.data <= core.io.dma_axi.r.bits.data @[quasar_wrapper.scala 105:21] + io.dma_brg.r.bits.id <= core.io.dma_axi.r.bits.id @[quasar_wrapper.scala 105:21] + io.dma_brg.r.valid <= core.io.dma_axi.r.valid @[quasar_wrapper.scala 105:21] + core.io.dma_axi.r.ready <= io.dma_brg.r.ready @[quasar_wrapper.scala 105:21] + core.io.dma_axi.ar.bits.qos <= io.dma_brg.ar.bits.qos @[quasar_wrapper.scala 105:21] + core.io.dma_axi.ar.bits.prot <= io.dma_brg.ar.bits.prot @[quasar_wrapper.scala 105:21] + core.io.dma_axi.ar.bits.cache <= io.dma_brg.ar.bits.cache @[quasar_wrapper.scala 105:21] + core.io.dma_axi.ar.bits.lock <= io.dma_brg.ar.bits.lock @[quasar_wrapper.scala 105:21] + core.io.dma_axi.ar.bits.burst <= io.dma_brg.ar.bits.burst @[quasar_wrapper.scala 105:21] + core.io.dma_axi.ar.bits.size <= io.dma_brg.ar.bits.size @[quasar_wrapper.scala 105:21] + core.io.dma_axi.ar.bits.len <= io.dma_brg.ar.bits.len @[quasar_wrapper.scala 105:21] + core.io.dma_axi.ar.bits.region <= io.dma_brg.ar.bits.region @[quasar_wrapper.scala 105:21] + core.io.dma_axi.ar.bits.addr <= io.dma_brg.ar.bits.addr @[quasar_wrapper.scala 105:21] + core.io.dma_axi.ar.bits.id <= io.dma_brg.ar.bits.id @[quasar_wrapper.scala 105:21] + core.io.dma_axi.ar.valid <= io.dma_brg.ar.valid @[quasar_wrapper.scala 105:21] + io.dma_brg.ar.ready <= core.io.dma_axi.ar.ready @[quasar_wrapper.scala 105:21] + io.dma_brg.b.bits.id <= core.io.dma_axi.b.bits.id @[quasar_wrapper.scala 105:21] + io.dma_brg.b.bits.resp <= core.io.dma_axi.b.bits.resp @[quasar_wrapper.scala 105:21] + io.dma_brg.b.valid <= core.io.dma_axi.b.valid @[quasar_wrapper.scala 105:21] + core.io.dma_axi.b.ready <= io.dma_brg.b.ready @[quasar_wrapper.scala 105:21] + core.io.dma_axi.w.bits.last <= io.dma_brg.w.bits.last @[quasar_wrapper.scala 105:21] + core.io.dma_axi.w.bits.strb <= io.dma_brg.w.bits.strb @[quasar_wrapper.scala 105:21] + core.io.dma_axi.w.bits.data <= io.dma_brg.w.bits.data @[quasar_wrapper.scala 105:21] + core.io.dma_axi.w.valid <= io.dma_brg.w.valid @[quasar_wrapper.scala 105:21] + io.dma_brg.w.ready <= core.io.dma_axi.w.ready @[quasar_wrapper.scala 105:21] + core.io.dma_axi.aw.bits.qos <= io.dma_brg.aw.bits.qos @[quasar_wrapper.scala 105:21] + core.io.dma_axi.aw.bits.prot <= io.dma_brg.aw.bits.prot @[quasar_wrapper.scala 105:21] + core.io.dma_axi.aw.bits.cache <= io.dma_brg.aw.bits.cache @[quasar_wrapper.scala 105:21] + core.io.dma_axi.aw.bits.lock <= io.dma_brg.aw.bits.lock @[quasar_wrapper.scala 105:21] + core.io.dma_axi.aw.bits.burst <= io.dma_brg.aw.bits.burst @[quasar_wrapper.scala 105:21] + core.io.dma_axi.aw.bits.size <= io.dma_brg.aw.bits.size @[quasar_wrapper.scala 105:21] + core.io.dma_axi.aw.bits.len <= io.dma_brg.aw.bits.len @[quasar_wrapper.scala 105:21] + core.io.dma_axi.aw.bits.region <= io.dma_brg.aw.bits.region @[quasar_wrapper.scala 105:21] + core.io.dma_axi.aw.bits.addr <= io.dma_brg.aw.bits.addr @[quasar_wrapper.scala 105:21] + core.io.dma_axi.aw.bits.id <= io.dma_brg.aw.bits.id @[quasar_wrapper.scala 105:21] + core.io.dma_axi.aw.valid <= io.dma_brg.aw.valid @[quasar_wrapper.scala 105:21] + io.dma_brg.aw.ready <= core.io.dma_axi.aw.ready @[quasar_wrapper.scala 105:21] core.io.dbg_rst_l <= io.dbg_rst_l @[quasar_wrapper.scala 119:21] core.io.rst_vec <= io.rst_vec @[quasar_wrapper.scala 120:19] core.io.nmi_int <= io.nmi_int @[quasar_wrapper.scala 121:19] diff --git a/quasar_wrapper.v b/quasar_wrapper.v index ed76dd8e..a9c1193f 100644 --- a/quasar_wrapper.v +++ b/quasar_wrapper.v @@ -57,6 +57,7 @@ module ifu_mem_ctl( output io_ifu_axi_ar_valid, output [2:0] io_ifu_axi_ar_bits_id, output [31:0] io_ifu_axi_ar_bits_addr, + output [3:0] io_ifu_axi_ar_bits_region, output io_ifu_axi_r_ready, input io_ifu_axi_r_valid, input [2:0] io_ifu_axi_r_bits_id, @@ -1928,6 +1929,7 @@ module ifu_mem_ctl( wire _T_318 = ~stream_miss_f; // @[ifu_mem_ctl.scala 226:106] reg ifc_region_acc_fault_f; // @[ifu_mem_ctl.scala 232:68] reg [2:0] bus_rd_addr_count; // @[ifu_mem_ctl.scala 540:55] + wire [28:0] ifu_ic_req_addr_f = {miss_addr,bus_rd_addr_count}; // @[Cat.scala 29:58] wire _T_325 = _T_239 | _T_2268; // @[ifu_mem_ctl.scala 234:55] wire _T_328 = _T_325 & _T_56; // @[ifu_mem_ctl.scala 234:82] wire _T_2289 = ~ifu_bus_rid_ff[0]; // @[ifu_mem_ctl.scala 378:55] @@ -5660,6 +5662,7 @@ module ifu_mem_ctl( assign io_ifu_axi_ar_valid = ifu_bus_cmd_valid; // @[ifu_mem_ctl.scala 497:23] assign io_ifu_axi_ar_bits_id = bus_rd_addr_count & _T_2608; // @[ifu_mem_ctl.scala 498:25] assign io_ifu_axi_ar_bits_addr = _T_2610 & _T_2612; // @[ifu_mem_ctl.scala 499:27] + assign io_ifu_axi_ar_bits_region = ifu_ic_req_addr_f[28:25]; // @[ifu_mem_ctl.scala 502:29] assign io_ifu_axi_r_ready = 1'h1; // @[ifu_mem_ctl.scala 504:22] assign io_iccm_rw_addr = _T_3110 ? io_dma_mem_ctl_dma_mem_addr[15:1] : _T_3117; // @[ifu_mem_ctl.scala 599:19] assign io_iccm_buf_correct_ecc = iccm_correct_ecc & _T_2497; // @[ifu_mem_ctl.scala 395:27] @@ -44530,6 +44533,7 @@ module ifu( output io_ifu_ar_valid, output [2:0] io_ifu_ar_bits_id, output [31:0] io_ifu_ar_bits_addr, + output [3:0] io_ifu_ar_bits_region, input io_ifu_r_valid, input [2:0] io_ifu_r_bits_id, input [63:0] io_ifu_r_bits_data, @@ -44588,6 +44592,7 @@ module ifu( wire mem_ctl_io_ifu_axi_ar_valid; // @[ifu.scala 34:23] wire [2:0] mem_ctl_io_ifu_axi_ar_bits_id; // @[ifu.scala 34:23] wire [31:0] mem_ctl_io_ifu_axi_ar_bits_addr; // @[ifu.scala 34:23] + wire [3:0] mem_ctl_io_ifu_axi_ar_bits_region; // @[ifu.scala 34:23] wire mem_ctl_io_ifu_axi_r_ready; // @[ifu.scala 34:23] wire mem_ctl_io_ifu_axi_r_valid; // @[ifu.scala 34:23] wire [2:0] mem_ctl_io_ifu_axi_r_bits_id; // @[ifu.scala 34:23] @@ -44803,6 +44808,7 @@ module ifu( .io_ifu_axi_ar_valid(mem_ctl_io_ifu_axi_ar_valid), .io_ifu_axi_ar_bits_id(mem_ctl_io_ifu_axi_ar_bits_id), .io_ifu_axi_ar_bits_addr(mem_ctl_io_ifu_axi_ar_bits_addr), + .io_ifu_axi_ar_bits_region(mem_ctl_io_ifu_axi_ar_bits_region), .io_ifu_axi_r_ready(mem_ctl_io_ifu_axi_r_ready), .io_ifu_axi_r_valid(mem_ctl_io_ifu_axi_r_valid), .io_ifu_axi_r_bits_id(mem_ctl_io_ifu_axi_r_bits_id), @@ -45043,6 +45049,7 @@ module ifu( assign io_ifu_ar_valid = mem_ctl_io_ifu_axi_ar_valid; // @[ifu.scala 103:22] assign io_ifu_ar_bits_id = mem_ctl_io_ifu_axi_ar_bits_id; // @[ifu.scala 103:22] assign io_ifu_ar_bits_addr = mem_ctl_io_ifu_axi_ar_bits_addr; // @[ifu.scala 103:22] + assign io_ifu_ar_bits_region = mem_ctl_io_ifu_axi_ar_bits_region; // @[ifu.scala 103:22] assign io_iccm_dma_ecc_error = mem_ctl_io_iccm_dma_ecc_error; // @[ifu.scala 113:25] assign io_iccm_dma_rvalid = mem_ctl_io_iccm_dma_rvalid; // @[ifu.scala 114:22] assign io_iccm_dma_rdata = mem_ctl_io_iccm_dma_rdata; // @[ifu.scala 115:21] @@ -50517,7 +50524,6 @@ module csr_tlu( output io_dec_tlu_misc_clk_override, output io_dec_tlu_dec_clk_override, output io_dec_tlu_lsu_clk_override, - output io_dec_tlu_bus_clk_override, output io_dec_tlu_pic_clk_override, output io_dec_tlu_dccm_clk_override, output io_dec_tlu_icm_clk_override, @@ -50540,6 +50546,7 @@ module csr_tlu( input io_lsu_imprecise_error_load_any, input io_lsu_imprecise_error_store_any, output [31:0] io_dec_tlu_mrac_ff, + output io_dec_tlu_wb_coalescing_disable, output io_dec_tlu_bpred_disable, output io_dec_tlu_sideeffect_posted_disable, output io_dec_tlu_core_ecc_disable, @@ -50924,13 +50931,13 @@ module csr_tlu( wire _T_2 = ~io_rfpc_i0_r; // @[dec_tlu_ctl.scala 1431:68] wire _T_5 = io_dec_csr_wraddr_r == 12'h300; // @[dec_tlu_ctl.scala 1432:71] wire wr_mstatus_r = io_dec_csr_wen_r_mod & _T_5; // @[dec_tlu_ctl.scala 1432:42] - wire _T_488 = io_dec_csr_wraddr_r == 12'h7c6; // @[dec_tlu_ctl.scala 1818:68] - wire wr_mpmc_r = io_dec_csr_wen_r_mod & _T_488; // @[dec_tlu_ctl.scala 1818:39] - wire _T_500 = ~io_dec_csr_wrdata_r[1]; // @[dec_tlu_ctl.scala 1826:37] + wire _T_498 = io_dec_csr_wraddr_r == 12'h7c6; // @[dec_tlu_ctl.scala 1818:68] + wire wr_mpmc_r = io_dec_csr_wen_r_mod & _T_498; // @[dec_tlu_ctl.scala 1818:39] + wire _T_510 = ~io_dec_csr_wrdata_r[1]; // @[dec_tlu_ctl.scala 1826:37] reg mpmc_b; // @[dec_tlu_ctl.scala 1828:44] wire mpmc = ~mpmc_b; // @[dec_tlu_ctl.scala 1831:10] - wire _T_501 = ~mpmc; // @[dec_tlu_ctl.scala 1826:62] - wire mpmc_b_ns = wr_mpmc_r ? _T_500 : _T_501; // @[dec_tlu_ctl.scala 1826:18] + wire _T_511 = ~mpmc; // @[dec_tlu_ctl.scala 1826:62] + wire mpmc_b_ns = wr_mpmc_r ? _T_510 : _T_511; // @[dec_tlu_ctl.scala 1826:18] wire _T_6 = ~mpmc_b_ns; // @[dec_tlu_ctl.scala 1435:28] wire set_mie_pmu_fw_halt = _T_6 & io_fw_halt_req; // @[dec_tlu_ctl.scala 1435:39] wire _T_7 = ~wr_mstatus_r; // @[dec_tlu_ctl.scala 1438:5] @@ -50965,24 +50972,24 @@ module csr_tlu( wire _T_58 = io_dec_csr_wraddr_r == 12'h305; // @[dec_tlu_ctl.scala 1457:69] reg [30:0] _T_62; // @[lib.scala 374:16] reg [31:0] mdccmect; // @[lib.scala 374:16] - wire [62:0] _T_564 = 63'hffffffff << mdccmect[31:27]; // @[dec_tlu_ctl.scala 1878:41] - wire [31:0] _T_566 = {5'h0,mdccmect[26:0]}; // @[Cat.scala 29:58] - wire [62:0] _GEN_9 = {{31'd0}, _T_566}; // @[dec_tlu_ctl.scala 1878:61] - wire [62:0] _T_567 = _T_564 & _GEN_9; // @[dec_tlu_ctl.scala 1878:61] - wire mdccme_ce_req = |_T_567; // @[dec_tlu_ctl.scala 1878:94] + wire [62:0] _T_574 = 63'hffffffff << mdccmect[31:27]; // @[dec_tlu_ctl.scala 1878:41] + wire [31:0] _T_576 = {5'h0,mdccmect[26:0]}; // @[Cat.scala 29:58] + wire [62:0] _GEN_9 = {{31'd0}, _T_576}; // @[dec_tlu_ctl.scala 1878:61] + wire [62:0] _T_577 = _T_574 & _GEN_9; // @[dec_tlu_ctl.scala 1878:61] + wire mdccme_ce_req = |_T_577; // @[dec_tlu_ctl.scala 1878:94] reg [31:0] miccmect; // @[lib.scala 374:16] - wire [62:0] _T_544 = 63'hffffffff << miccmect[31:27]; // @[dec_tlu_ctl.scala 1863:40] - wire [31:0] _T_546 = {5'h0,miccmect[26:0]}; // @[Cat.scala 29:58] - wire [62:0] _GEN_10 = {{31'd0}, _T_546}; // @[dec_tlu_ctl.scala 1863:60] - wire [62:0] _T_547 = _T_544 & _GEN_10; // @[dec_tlu_ctl.scala 1863:60] - wire miccme_ce_req = |_T_547; // @[dec_tlu_ctl.scala 1863:93] + wire [62:0] _T_554 = 63'hffffffff << miccmect[31:27]; // @[dec_tlu_ctl.scala 1863:40] + wire [31:0] _T_556 = {5'h0,miccmect[26:0]}; // @[Cat.scala 29:58] + wire [62:0] _GEN_10 = {{31'd0}, _T_556}; // @[dec_tlu_ctl.scala 1863:60] + wire [62:0] _T_557 = _T_554 & _GEN_10; // @[dec_tlu_ctl.scala 1863:60] + wire miccme_ce_req = |_T_557; // @[dec_tlu_ctl.scala 1863:93] wire _T_63 = mdccme_ce_req | miccme_ce_req; // @[dec_tlu_ctl.scala 1471:30] reg [31:0] micect; // @[lib.scala 374:16] - wire [62:0] _T_522 = 63'hffffffff << micect[31:27]; // @[dec_tlu_ctl.scala 1848:39] - wire [31:0] _T_524 = {5'h0,micect[26:0]}; // @[Cat.scala 29:58] - wire [62:0] _GEN_11 = {{31'd0}, _T_524}; // @[dec_tlu_ctl.scala 1848:57] - wire [62:0] _T_525 = _T_522 & _GEN_11; // @[dec_tlu_ctl.scala 1848:57] - wire mice_ce_req = |_T_525; // @[dec_tlu_ctl.scala 1848:88] + wire [62:0] _T_532 = 63'hffffffff << micect[31:27]; // @[dec_tlu_ctl.scala 1848:39] + wire [31:0] _T_534 = {5'h0,micect[26:0]}; // @[Cat.scala 29:58] + wire [62:0] _GEN_11 = {{31'd0}, _T_534}; // @[dec_tlu_ctl.scala 1848:57] + wire [62:0] _T_535 = _T_532 & _GEN_11; // @[dec_tlu_ctl.scala 1848:57] + wire mice_ce_req = |_T_535; // @[dec_tlu_ctl.scala 1848:88] wire ce_int = _T_63 | mice_ce_req; // @[dec_tlu_ctl.scala 1471:46] wire [2:0] _T_65 = {io_mexintpend,io_timer_int_sync,io_soft_int_sync}; // @[Cat.scala 29:58] wire [2:0] _T_67 = {ce_int,io_dec_timer_t0_pulse,io_dec_timer_t1_pulse}; // @[Cat.scala 29:58] @@ -51174,430 +51181,424 @@ module csr_tlu( reg [8:0] mcgc; // @[lib.scala 374:16] wire _T_337 = io_dec_csr_wraddr_r == 12'h7f9; // @[dec_tlu_ctl.scala 1724:68] reg [14:0] mfdc_int; // @[lib.scala 374:16] - wire [2:0] _T_341 = ~io_dec_csr_wrdata_r[18:16]; // @[dec_tlu_ctl.scala 1737:19] - wire [2:0] _T_345 = ~mfdc_int[14:12]; // @[dec_tlu_ctl.scala 1738:19] - wire [18:0] mfdc = {_T_345,4'h0,mfdc_int[11:0]}; // @[Cat.scala 29:58] - wire _T_357 = io_dec_csr_wraddr_r == 12'h7c2; // @[dec_tlu_ctl.scala 1757:77] - wire _T_358 = io_dec_csr_wen_r_mod & _T_357; // @[dec_tlu_ctl.scala 1757:48] - wire _T_360 = _T_358 & _T_297; // @[dec_tlu_ctl.scala 1757:87] - wire _T_361 = ~io_take_ext_int_start; // @[dec_tlu_ctl.scala 1757:113] - wire _T_364 = io_dec_csr_wraddr_r == 12'h7c0; // @[dec_tlu_ctl.scala 1764:68] - wire _T_368 = ~io_dec_csr_wrdata_r[31]; // @[dec_tlu_ctl.scala 1767:71] - wire _T_369 = io_dec_csr_wrdata_r[30] & _T_368; // @[dec_tlu_ctl.scala 1767:69] - wire _T_373 = ~io_dec_csr_wrdata_r[29]; // @[dec_tlu_ctl.scala 1768:73] - wire _T_374 = io_dec_csr_wrdata_r[28] & _T_373; // @[dec_tlu_ctl.scala 1768:71] - wire _T_378 = ~io_dec_csr_wrdata_r[27]; // @[dec_tlu_ctl.scala 1769:73] - wire _T_379 = io_dec_csr_wrdata_r[26] & _T_378; // @[dec_tlu_ctl.scala 1769:71] - wire _T_383 = ~io_dec_csr_wrdata_r[25]; // @[dec_tlu_ctl.scala 1770:73] - wire _T_384 = io_dec_csr_wrdata_r[24] & _T_383; // @[dec_tlu_ctl.scala 1770:71] - wire _T_388 = ~io_dec_csr_wrdata_r[23]; // @[dec_tlu_ctl.scala 1771:73] - wire _T_389 = io_dec_csr_wrdata_r[22] & _T_388; // @[dec_tlu_ctl.scala 1771:71] - wire _T_393 = ~io_dec_csr_wrdata_r[21]; // @[dec_tlu_ctl.scala 1772:73] - wire _T_394 = io_dec_csr_wrdata_r[20] & _T_393; // @[dec_tlu_ctl.scala 1772:71] - wire _T_398 = ~io_dec_csr_wrdata_r[19]; // @[dec_tlu_ctl.scala 1773:73] - wire _T_399 = io_dec_csr_wrdata_r[18] & _T_398; // @[dec_tlu_ctl.scala 1773:71] - wire _T_403 = ~io_dec_csr_wrdata_r[17]; // @[dec_tlu_ctl.scala 1774:73] - wire _T_404 = io_dec_csr_wrdata_r[16] & _T_403; // @[dec_tlu_ctl.scala 1774:71] - wire _T_408 = ~io_dec_csr_wrdata_r[15]; // @[dec_tlu_ctl.scala 1775:73] - wire _T_409 = io_dec_csr_wrdata_r[14] & _T_408; // @[dec_tlu_ctl.scala 1775:71] - wire _T_413 = ~io_dec_csr_wrdata_r[13]; // @[dec_tlu_ctl.scala 1776:73] - wire _T_414 = io_dec_csr_wrdata_r[12] & _T_413; // @[dec_tlu_ctl.scala 1776:71] - wire _T_418 = ~io_dec_csr_wrdata_r[11]; // @[dec_tlu_ctl.scala 1777:73] - wire _T_419 = io_dec_csr_wrdata_r[10] & _T_418; // @[dec_tlu_ctl.scala 1777:71] - wire _T_423 = ~io_dec_csr_wrdata_r[9]; // @[dec_tlu_ctl.scala 1778:73] - wire _T_424 = io_dec_csr_wrdata_r[8] & _T_423; // @[dec_tlu_ctl.scala 1778:70] - wire _T_428 = ~io_dec_csr_wrdata_r[7]; // @[dec_tlu_ctl.scala 1779:73] - wire _T_429 = io_dec_csr_wrdata_r[6] & _T_428; // @[dec_tlu_ctl.scala 1779:70] - wire _T_433 = ~io_dec_csr_wrdata_r[5]; // @[dec_tlu_ctl.scala 1780:73] - wire _T_434 = io_dec_csr_wrdata_r[4] & _T_433; // @[dec_tlu_ctl.scala 1780:70] - wire _T_438 = ~io_dec_csr_wrdata_r[3]; // @[dec_tlu_ctl.scala 1781:73] - wire _T_439 = io_dec_csr_wrdata_r[2] & _T_438; // @[dec_tlu_ctl.scala 1781:70] - wire _T_444 = io_dec_csr_wrdata_r[0] & _T_500; // @[dec_tlu_ctl.scala 1782:70] - wire [7:0] _T_451 = {io_dec_csr_wrdata_r[7],_T_429,io_dec_csr_wrdata_r[5],_T_434,io_dec_csr_wrdata_r[3],_T_439,io_dec_csr_wrdata_r[1],_T_444}; // @[Cat.scala 29:58] - wire [15:0] _T_459 = {io_dec_csr_wrdata_r[15],_T_409,io_dec_csr_wrdata_r[13],_T_414,io_dec_csr_wrdata_r[11],_T_419,io_dec_csr_wrdata_r[9],_T_424,_T_451}; // @[Cat.scala 29:58] - wire [7:0] _T_466 = {io_dec_csr_wrdata_r[23],_T_389,io_dec_csr_wrdata_r[21],_T_394,io_dec_csr_wrdata_r[19],_T_399,io_dec_csr_wrdata_r[17],_T_404}; // @[Cat.scala 29:58] - wire [15:0] _T_474 = {io_dec_csr_wrdata_r[31],_T_369,io_dec_csr_wrdata_r[29],_T_374,io_dec_csr_wrdata_r[27],_T_379,io_dec_csr_wrdata_r[25],_T_384,_T_466}; // @[Cat.scala 29:58] + wire [2:0] _T_341 = ~io_dec_csr_wrdata_r[18:16]; // @[dec_tlu_ctl.scala 1733:20] + wire _T_344 = ~io_dec_csr_wrdata_r[6]; // @[dec_tlu_ctl.scala 1733:75] + wire [6:0] _T_346 = {_T_344,io_dec_csr_wrdata_r[5:0]}; // @[Cat.scala 29:58] + wire [7:0] _T_347 = {_T_341,io_dec_csr_wrdata_r[11:7]}; // @[Cat.scala 29:58] + wire [2:0] _T_350 = ~mfdc_int[14:12]; // @[dec_tlu_ctl.scala 1734:20] + wire _T_353 = ~mfdc_int[6]; // @[dec_tlu_ctl.scala 1734:63] + wire [18:0] mfdc = {_T_350,4'h0,mfdc_int[11:7],_T_353,mfdc_int[5:0]}; // @[Cat.scala 29:58] + wire _T_367 = io_dec_csr_wraddr_r == 12'h7c2; // @[dec_tlu_ctl.scala 1757:77] + wire _T_368 = io_dec_csr_wen_r_mod & _T_367; // @[dec_tlu_ctl.scala 1757:48] + wire _T_370 = _T_368 & _T_297; // @[dec_tlu_ctl.scala 1757:87] + wire _T_371 = ~io_take_ext_int_start; // @[dec_tlu_ctl.scala 1757:113] + wire _T_374 = io_dec_csr_wraddr_r == 12'h7c0; // @[dec_tlu_ctl.scala 1764:68] + wire _T_378 = ~io_dec_csr_wrdata_r[31]; // @[dec_tlu_ctl.scala 1767:71] + wire _T_379 = io_dec_csr_wrdata_r[30] & _T_378; // @[dec_tlu_ctl.scala 1767:69] + wire _T_383 = ~io_dec_csr_wrdata_r[29]; // @[dec_tlu_ctl.scala 1768:73] + wire _T_384 = io_dec_csr_wrdata_r[28] & _T_383; // @[dec_tlu_ctl.scala 1768:71] + wire _T_388 = ~io_dec_csr_wrdata_r[27]; // @[dec_tlu_ctl.scala 1769:73] + wire _T_389 = io_dec_csr_wrdata_r[26] & _T_388; // @[dec_tlu_ctl.scala 1769:71] + wire _T_393 = ~io_dec_csr_wrdata_r[25]; // @[dec_tlu_ctl.scala 1770:73] + wire _T_394 = io_dec_csr_wrdata_r[24] & _T_393; // @[dec_tlu_ctl.scala 1770:71] + wire _T_398 = ~io_dec_csr_wrdata_r[23]; // @[dec_tlu_ctl.scala 1771:73] + wire _T_399 = io_dec_csr_wrdata_r[22] & _T_398; // @[dec_tlu_ctl.scala 1771:71] + wire _T_403 = ~io_dec_csr_wrdata_r[21]; // @[dec_tlu_ctl.scala 1772:73] + wire _T_404 = io_dec_csr_wrdata_r[20] & _T_403; // @[dec_tlu_ctl.scala 1772:71] + wire _T_408 = ~io_dec_csr_wrdata_r[19]; // @[dec_tlu_ctl.scala 1773:73] + wire _T_409 = io_dec_csr_wrdata_r[18] & _T_408; // @[dec_tlu_ctl.scala 1773:71] + wire _T_413 = ~io_dec_csr_wrdata_r[17]; // @[dec_tlu_ctl.scala 1774:73] + wire _T_414 = io_dec_csr_wrdata_r[16] & _T_413; // @[dec_tlu_ctl.scala 1774:71] + wire _T_418 = ~io_dec_csr_wrdata_r[15]; // @[dec_tlu_ctl.scala 1775:73] + wire _T_419 = io_dec_csr_wrdata_r[14] & _T_418; // @[dec_tlu_ctl.scala 1775:71] + wire _T_423 = ~io_dec_csr_wrdata_r[13]; // @[dec_tlu_ctl.scala 1776:73] + wire _T_424 = io_dec_csr_wrdata_r[12] & _T_423; // @[dec_tlu_ctl.scala 1776:71] + wire _T_428 = ~io_dec_csr_wrdata_r[11]; // @[dec_tlu_ctl.scala 1777:73] + wire _T_429 = io_dec_csr_wrdata_r[10] & _T_428; // @[dec_tlu_ctl.scala 1777:71] + wire _T_433 = ~io_dec_csr_wrdata_r[9]; // @[dec_tlu_ctl.scala 1778:73] + wire _T_434 = io_dec_csr_wrdata_r[8] & _T_433; // @[dec_tlu_ctl.scala 1778:70] + wire _T_438 = ~io_dec_csr_wrdata_r[7]; // @[dec_tlu_ctl.scala 1779:73] + wire _T_439 = io_dec_csr_wrdata_r[6] & _T_438; // @[dec_tlu_ctl.scala 1779:70] + wire _T_443 = ~io_dec_csr_wrdata_r[5]; // @[dec_tlu_ctl.scala 1780:73] + wire _T_444 = io_dec_csr_wrdata_r[4] & _T_443; // @[dec_tlu_ctl.scala 1780:70] + wire _T_448 = ~io_dec_csr_wrdata_r[3]; // @[dec_tlu_ctl.scala 1781:73] + wire _T_449 = io_dec_csr_wrdata_r[2] & _T_448; // @[dec_tlu_ctl.scala 1781:70] + wire _T_454 = io_dec_csr_wrdata_r[0] & _T_510; // @[dec_tlu_ctl.scala 1782:70] + wire [7:0] _T_461 = {io_dec_csr_wrdata_r[7],_T_439,io_dec_csr_wrdata_r[5],_T_444,io_dec_csr_wrdata_r[3],_T_449,io_dec_csr_wrdata_r[1],_T_454}; // @[Cat.scala 29:58] + wire [15:0] _T_469 = {io_dec_csr_wrdata_r[15],_T_419,io_dec_csr_wrdata_r[13],_T_424,io_dec_csr_wrdata_r[11],_T_429,io_dec_csr_wrdata_r[9],_T_434,_T_461}; // @[Cat.scala 29:58] + wire [7:0] _T_476 = {io_dec_csr_wrdata_r[23],_T_399,io_dec_csr_wrdata_r[21],_T_404,io_dec_csr_wrdata_r[19],_T_409,io_dec_csr_wrdata_r[17],_T_414}; // @[Cat.scala 29:58] + wire [15:0] _T_484 = {io_dec_csr_wrdata_r[31],_T_379,io_dec_csr_wrdata_r[29],_T_384,io_dec_csr_wrdata_r[27],_T_389,io_dec_csr_wrdata_r[25],_T_394,_T_476}; // @[Cat.scala 29:58] reg [31:0] mrac; // @[lib.scala 374:16] - wire _T_477 = io_dec_csr_wraddr_r == 12'hbc0; // @[dec_tlu_ctl.scala 1795:69] - wire wr_mdeau_r = io_dec_csr_wen_r_mod & _T_477; // @[dec_tlu_ctl.scala 1795:40] - wire _T_478 = ~wr_mdeau_r; // @[dec_tlu_ctl.scala 1805:59] - wire _T_479 = io_mdseac_locked_f & _T_478; // @[dec_tlu_ctl.scala 1805:57] - wire _T_481 = io_lsu_imprecise_error_store_any | io_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 1807:49] - wire _T_482 = ~io_nmi_int_detected_f; // @[dec_tlu_ctl.scala 1807:86] - wire _T_483 = _T_481 & _T_482; // @[dec_tlu_ctl.scala 1807:84] - wire _T_484 = ~io_mdseac_locked_f; // @[dec_tlu_ctl.scala 1807:111] - wire mdseac_en = _T_483 & _T_484; // @[dec_tlu_ctl.scala 1807:109] + wire _T_487 = io_dec_csr_wraddr_r == 12'hbc0; // @[dec_tlu_ctl.scala 1795:69] + wire wr_mdeau_r = io_dec_csr_wen_r_mod & _T_487; // @[dec_tlu_ctl.scala 1795:40] + wire _T_488 = ~wr_mdeau_r; // @[dec_tlu_ctl.scala 1805:59] + wire _T_489 = io_mdseac_locked_f & _T_488; // @[dec_tlu_ctl.scala 1805:57] + wire _T_491 = io_lsu_imprecise_error_store_any | io_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 1807:49] + wire _T_492 = ~io_nmi_int_detected_f; // @[dec_tlu_ctl.scala 1807:86] + wire _T_493 = _T_491 & _T_492; // @[dec_tlu_ctl.scala 1807:84] + wire _T_494 = ~io_mdseac_locked_f; // @[dec_tlu_ctl.scala 1807:111] + wire mdseac_en = _T_493 & _T_494; // @[dec_tlu_ctl.scala 1807:109] reg [31:0] mdseac; // @[lib.scala 374:16] - wire _T_490 = wr_mpmc_r & io_dec_csr_wrdata_r[0]; // @[dec_tlu_ctl.scala 1822:30] - wire _T_491 = ~io_internal_dbg_halt_mode_f2; // @[dec_tlu_ctl.scala 1822:57] - wire _T_492 = _T_490 & _T_491; // @[dec_tlu_ctl.scala 1822:55] - wire _T_493 = ~io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 1822:89] - wire _T_506 = io_dec_csr_wrdata_r[31:27] > 5'h1a; // @[dec_tlu_ctl.scala 1840:48] - wire [4:0] csr_sat = _T_506 ? 5'h1a : io_dec_csr_wrdata_r[31:27]; // @[dec_tlu_ctl.scala 1840:19] - wire _T_509 = io_dec_csr_wraddr_r == 12'h7f0; // @[dec_tlu_ctl.scala 1842:70] - wire wr_micect_r = io_dec_csr_wen_r_mod & _T_509; // @[dec_tlu_ctl.scala 1842:41] - wire [26:0] _T_510 = {26'h0,io_ic_perr_r_d1}; // @[Cat.scala 29:58] - wire [31:0] _GEN_14 = {{5'd0}, _T_510}; // @[dec_tlu_ctl.scala 1843:23] - wire [31:0] _T_512 = micect + _GEN_14; // @[dec_tlu_ctl.scala 1843:23] - wire [31:0] _T_515 = {csr_sat,io_dec_csr_wrdata_r[26:0]}; // @[Cat.scala 29:58] - wire [26:0] micect_inc = _T_512[26:0]; // @[dec_tlu_ctl.scala 1843:13] - wire [31:0] _T_517 = {micect[31:27],micect_inc}; // @[Cat.scala 29:58] - wire _T_528 = io_dec_csr_wraddr_r == 12'h7f1; // @[dec_tlu_ctl.scala 1857:76] - wire wr_miccmect_r = io_dec_csr_wen_r_mod & _T_528; // @[dec_tlu_ctl.scala 1857:47] - wire _T_530 = io_iccm_sbecc_r_d1 | io_iccm_dma_sb_error; // @[dec_tlu_ctl.scala 1858:70] - wire [26:0] _T_531 = {26'h0,_T_530}; // @[Cat.scala 29:58] - wire [26:0] miccmect_inc = miccmect[26:0] + _T_531; // @[dec_tlu_ctl.scala 1858:33] - wire [31:0] _T_538 = {miccmect[31:27],miccmect_inc}; // @[Cat.scala 29:58] - wire _T_539 = wr_miccmect_r | io_iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 1861:48] - wire _T_550 = io_dec_csr_wraddr_r == 12'h7f2; // @[dec_tlu_ctl.scala 1872:76] - wire wr_mdccmect_r = io_dec_csr_wen_r_mod & _T_550; // @[dec_tlu_ctl.scala 1872:47] - wire [26:0] _T_552 = {26'h0,io_lsu_single_ecc_error_r_d1}; // @[Cat.scala 29:58] - wire [26:0] mdccmect_inc = mdccmect[26:0] + _T_552; // @[dec_tlu_ctl.scala 1873:33] - wire [31:0] _T_559 = {mdccmect[31:27],mdccmect_inc}; // @[Cat.scala 29:58] - wire _T_570 = io_dec_csr_wraddr_r == 12'h7ce; // @[dec_tlu_ctl.scala 1888:69] - wire wr_mfdht_r = io_dec_csr_wen_r_mod & _T_570; // @[dec_tlu_ctl.scala 1888:40] + wire _T_500 = wr_mpmc_r & io_dec_csr_wrdata_r[0]; // @[dec_tlu_ctl.scala 1822:30] + wire _T_501 = ~io_internal_dbg_halt_mode_f2; // @[dec_tlu_ctl.scala 1822:57] + wire _T_502 = _T_500 & _T_501; // @[dec_tlu_ctl.scala 1822:55] + wire _T_503 = ~io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 1822:89] + wire _T_516 = io_dec_csr_wrdata_r[31:27] > 5'h1a; // @[dec_tlu_ctl.scala 1840:48] + wire [4:0] csr_sat = _T_516 ? 5'h1a : io_dec_csr_wrdata_r[31:27]; // @[dec_tlu_ctl.scala 1840:19] + wire _T_519 = io_dec_csr_wraddr_r == 12'h7f0; // @[dec_tlu_ctl.scala 1842:70] + wire wr_micect_r = io_dec_csr_wen_r_mod & _T_519; // @[dec_tlu_ctl.scala 1842:41] + wire [26:0] _T_520 = {26'h0,io_ic_perr_r_d1}; // @[Cat.scala 29:58] + wire [31:0] _GEN_14 = {{5'd0}, _T_520}; // @[dec_tlu_ctl.scala 1843:23] + wire [31:0] _T_522 = micect + _GEN_14; // @[dec_tlu_ctl.scala 1843:23] + wire [31:0] _T_525 = {csr_sat,io_dec_csr_wrdata_r[26:0]}; // @[Cat.scala 29:58] + wire [26:0] micect_inc = _T_522[26:0]; // @[dec_tlu_ctl.scala 1843:13] + wire [31:0] _T_527 = {micect[31:27],micect_inc}; // @[Cat.scala 29:58] + wire _T_538 = io_dec_csr_wraddr_r == 12'h7f1; // @[dec_tlu_ctl.scala 1857:76] + wire wr_miccmect_r = io_dec_csr_wen_r_mod & _T_538; // @[dec_tlu_ctl.scala 1857:47] + wire _T_540 = io_iccm_sbecc_r_d1 | io_iccm_dma_sb_error; // @[dec_tlu_ctl.scala 1858:70] + wire [26:0] _T_541 = {26'h0,_T_540}; // @[Cat.scala 29:58] + wire [26:0] miccmect_inc = miccmect[26:0] + _T_541; // @[dec_tlu_ctl.scala 1858:33] + wire [31:0] _T_548 = {miccmect[31:27],miccmect_inc}; // @[Cat.scala 29:58] + wire _T_549 = wr_miccmect_r | io_iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 1861:48] + wire _T_560 = io_dec_csr_wraddr_r == 12'h7f2; // @[dec_tlu_ctl.scala 1872:76] + wire wr_mdccmect_r = io_dec_csr_wen_r_mod & _T_560; // @[dec_tlu_ctl.scala 1872:47] + wire [26:0] _T_562 = {26'h0,io_lsu_single_ecc_error_r_d1}; // @[Cat.scala 29:58] + wire [26:0] mdccmect_inc = mdccmect[26:0] + _T_562; // @[dec_tlu_ctl.scala 1873:33] + wire [31:0] _T_569 = {mdccmect[31:27],mdccmect_inc}; // @[Cat.scala 29:58] + wire _T_580 = io_dec_csr_wraddr_r == 12'h7ce; // @[dec_tlu_ctl.scala 1888:69] + wire wr_mfdht_r = io_dec_csr_wen_r_mod & _T_580; // @[dec_tlu_ctl.scala 1888:40] reg [5:0] mfdht; // @[dec_tlu_ctl.scala 1892:43] - wire _T_575 = io_dec_csr_wraddr_r == 12'h7cf; // @[dec_tlu_ctl.scala 1901:69] - wire wr_mfdhs_r = io_dec_csr_wen_r_mod & _T_575; // @[dec_tlu_ctl.scala 1901:40] - wire _T_578 = ~io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 1904:43] - wire _T_579 = io_dbg_tlu_halted & _T_578; // @[dec_tlu_ctl.scala 1904:41] - wire _T_581 = ~io_lsu_idle_any_f; // @[dec_tlu_ctl.scala 1904:78] - wire _T_582 = ~io_ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 1904:98] - wire [1:0] _T_583 = {_T_581,_T_582}; // @[Cat.scala 29:58] + wire _T_585 = io_dec_csr_wraddr_r == 12'h7cf; // @[dec_tlu_ctl.scala 1901:69] + wire wr_mfdhs_r = io_dec_csr_wen_r_mod & _T_585; // @[dec_tlu_ctl.scala 1901:40] + wire _T_588 = ~io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 1904:43] + wire _T_589 = io_dbg_tlu_halted & _T_588; // @[dec_tlu_ctl.scala 1904:41] + wire _T_591 = ~io_lsu_idle_any_f; // @[dec_tlu_ctl.scala 1904:78] + wire _T_592 = ~io_ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 1904:98] + wire [1:0] _T_593 = {_T_591,_T_592}; // @[Cat.scala 29:58] reg [1:0] mfdhs; // @[Reg.scala 27:20] - wire _T_585 = wr_mfdhs_r | io_dbg_tlu_halted; // @[dec_tlu_ctl.scala 1906:71] + wire _T_595 = wr_mfdhs_r | io_dbg_tlu_halted; // @[dec_tlu_ctl.scala 1906:71] reg [31:0] force_halt_ctr_f; // @[Reg.scala 27:20] - wire [31:0] _T_590 = force_halt_ctr_f + 32'h1; // @[dec_tlu_ctl.scala 1908:74] - wire [62:0] _T_597 = 63'hffffffff << mfdht[5:1]; // @[dec_tlu_ctl.scala 1913:71] + wire [31:0] _T_600 = force_halt_ctr_f + 32'h1; // @[dec_tlu_ctl.scala 1908:74] + wire [62:0] _T_607 = 63'hffffffff << mfdht[5:1]; // @[dec_tlu_ctl.scala 1913:71] wire [62:0] _GEN_15 = {{31'd0}, force_halt_ctr_f}; // @[dec_tlu_ctl.scala 1913:48] - wire [62:0] _T_598 = _GEN_15 & _T_597; // @[dec_tlu_ctl.scala 1913:48] - wire _T_599 = |_T_598; // @[dec_tlu_ctl.scala 1913:87] - wire _T_602 = io_dec_csr_wraddr_r == 12'hbc8; // @[dec_tlu_ctl.scala 1921:69] + wire [62:0] _T_608 = _GEN_15 & _T_607; // @[dec_tlu_ctl.scala 1913:48] + wire _T_609 = |_T_608; // @[dec_tlu_ctl.scala 1913:87] + wire _T_612 = io_dec_csr_wraddr_r == 12'hbc8; // @[dec_tlu_ctl.scala 1921:69] reg [21:0] meivt; // @[lib.scala 374:16] - wire _T_621 = io_dec_csr_wraddr_r == 12'hbca; // @[dec_tlu_ctl.scala 1972:69] - wire _T_622 = io_dec_csr_wen_r_mod & _T_621; // @[dec_tlu_ctl.scala 1972:40] - wire wr_meicpct_r = _T_622 | io_take_ext_int_start; // @[dec_tlu_ctl.scala 1972:83] + wire _T_631 = io_dec_csr_wraddr_r == 12'hbca; // @[dec_tlu_ctl.scala 1972:69] + wire _T_632 = io_dec_csr_wen_r_mod & _T_631; // @[dec_tlu_ctl.scala 1972:40] + wire wr_meicpct_r = _T_632 | io_take_ext_int_start; // @[dec_tlu_ctl.scala 1972:83] reg [7:0] meihap; // @[lib.scala 374:16] - wire _T_608 = io_dec_csr_wraddr_r == 12'hbcc; // @[dec_tlu_ctl.scala 1945:72] - wire wr_meicurpl_r = io_dec_csr_wen_r_mod & _T_608; // @[dec_tlu_ctl.scala 1945:43] + wire _T_618 = io_dec_csr_wraddr_r == 12'hbcc; // @[dec_tlu_ctl.scala 1945:72] + wire wr_meicurpl_r = io_dec_csr_wen_r_mod & _T_618; // @[dec_tlu_ctl.scala 1945:43] reg [3:0] meicurpl; // @[dec_tlu_ctl.scala 1948:46] - wire _T_613 = io_dec_csr_wraddr_r == 12'hbcb; // @[dec_tlu_ctl.scala 1960:73] - wire _T_614 = io_dec_csr_wen_r_mod & _T_613; // @[dec_tlu_ctl.scala 1960:44] - wire wr_meicidpl_r = _T_614 | io_take_ext_int_start; // @[dec_tlu_ctl.scala 1960:88] + wire _T_623 = io_dec_csr_wraddr_r == 12'hbcb; // @[dec_tlu_ctl.scala 1960:73] + wire _T_624 = io_dec_csr_wen_r_mod & _T_623; // @[dec_tlu_ctl.scala 1960:44] + wire wr_meicidpl_r = _T_624 | io_take_ext_int_start; // @[dec_tlu_ctl.scala 1960:88] reg [3:0] meicidpl; // @[dec_tlu_ctl.scala 1965:44] - wire _T_625 = io_dec_csr_wraddr_r == 12'hbc9; // @[dec_tlu_ctl.scala 1981:69] - wire wr_meipt_r = io_dec_csr_wen_r_mod & _T_625; // @[dec_tlu_ctl.scala 1981:40] + wire _T_635 = io_dec_csr_wraddr_r == 12'hbc9; // @[dec_tlu_ctl.scala 1981:69] + wire wr_meipt_r = io_dec_csr_wen_r_mod & _T_635; // @[dec_tlu_ctl.scala 1981:40] reg [3:0] meipt; // @[dec_tlu_ctl.scala 1984:43] - wire _T_629 = io_trigger_hit_r_d1 & io_dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 2012:89] - wire trigger_hit_for_dscr_cause_r_d1 = io_trigger_hit_dmode_r_d1 | _T_629; // @[dec_tlu_ctl.scala 2012:66] - wire _T_630 = ~io_ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 2015:31] - wire _T_631 = io_dcsr_single_step_done_f & _T_630; // @[dec_tlu_ctl.scala 2015:29] - wire _T_632 = ~trigger_hit_for_dscr_cause_r_d1; // @[dec_tlu_ctl.scala 2015:63] - wire _T_633 = _T_631 & _T_632; // @[dec_tlu_ctl.scala 2015:61] - wire _T_634 = ~io_debug_halt_req; // @[dec_tlu_ctl.scala 2015:98] - wire _T_635 = _T_633 & _T_634; // @[dec_tlu_ctl.scala 2015:96] - wire _T_638 = io_debug_halt_req & _T_630; // @[dec_tlu_ctl.scala 2016:46] - wire _T_640 = _T_638 & _T_632; // @[dec_tlu_ctl.scala 2016:78] - wire _T_643 = io_ebreak_to_debug_mode_r_d1 & _T_632; // @[dec_tlu_ctl.scala 2017:75] - wire [2:0] _T_646 = _T_635 ? 3'h4 : 3'h0; // @[Mux.scala 27:72] - wire [2:0] _T_647 = _T_640 ? 3'h3 : 3'h0; // @[Mux.scala 27:72] - wire [2:0] _T_648 = _T_643 ? 3'h1 : 3'h0; // @[Mux.scala 27:72] - wire [2:0] _T_649 = trigger_hit_for_dscr_cause_r_d1 ? 3'h2 : 3'h0; // @[Mux.scala 27:72] - wire [2:0] _T_650 = _T_646 | _T_647; // @[Mux.scala 27:72] - wire [2:0] _T_651 = _T_650 | _T_648; // @[Mux.scala 27:72] - wire [2:0] dcsr_cause = _T_651 | _T_649; // @[Mux.scala 27:72] - wire _T_653 = io_allow_dbg_halt_csr_write & io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 2020:46] - wire _T_655 = io_dec_csr_wraddr_r == 12'h7b0; // @[dec_tlu_ctl.scala 2020:98] - wire wr_dcsr_r = _T_653 & _T_655; // @[dec_tlu_ctl.scala 2020:69] - wire _T_657 = io_dcsr[8:6] == 3'h3; // @[dec_tlu_ctl.scala 2026:75] - wire dcsr_cause_upgradeable = io_internal_dbg_halt_mode_f & _T_657; // @[dec_tlu_ctl.scala 2026:59] - wire _T_658 = ~io_dbg_tlu_halted; // @[dec_tlu_ctl.scala 2027:59] - wire _T_659 = _T_658 | dcsr_cause_upgradeable; // @[dec_tlu_ctl.scala 2027:78] - wire enter_debug_halt_req_le = io_enter_debug_halt_req & _T_659; // @[dec_tlu_ctl.scala 2027:56] + wire _T_639 = io_trigger_hit_r_d1 & io_dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 2012:89] + wire trigger_hit_for_dscr_cause_r_d1 = io_trigger_hit_dmode_r_d1 | _T_639; // @[dec_tlu_ctl.scala 2012:66] + wire _T_640 = ~io_ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 2015:31] + wire _T_641 = io_dcsr_single_step_done_f & _T_640; // @[dec_tlu_ctl.scala 2015:29] + wire _T_642 = ~trigger_hit_for_dscr_cause_r_d1; // @[dec_tlu_ctl.scala 2015:63] + wire _T_643 = _T_641 & _T_642; // @[dec_tlu_ctl.scala 2015:61] + wire _T_644 = ~io_debug_halt_req; // @[dec_tlu_ctl.scala 2015:98] + wire _T_645 = _T_643 & _T_644; // @[dec_tlu_ctl.scala 2015:96] + wire _T_648 = io_debug_halt_req & _T_640; // @[dec_tlu_ctl.scala 2016:46] + wire _T_650 = _T_648 & _T_642; // @[dec_tlu_ctl.scala 2016:78] + wire _T_653 = io_ebreak_to_debug_mode_r_d1 & _T_642; // @[dec_tlu_ctl.scala 2017:75] + wire [2:0] _T_656 = _T_645 ? 3'h4 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_657 = _T_650 ? 3'h3 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_658 = _T_653 ? 3'h1 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_659 = trigger_hit_for_dscr_cause_r_d1 ? 3'h2 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_660 = _T_656 | _T_657; // @[Mux.scala 27:72] + wire [2:0] _T_661 = _T_660 | _T_658; // @[Mux.scala 27:72] + wire [2:0] dcsr_cause = _T_661 | _T_659; // @[Mux.scala 27:72] + wire _T_663 = io_allow_dbg_halt_csr_write & io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 2020:46] + wire _T_665 = io_dec_csr_wraddr_r == 12'h7b0; // @[dec_tlu_ctl.scala 2020:98] + wire wr_dcsr_r = _T_663 & _T_665; // @[dec_tlu_ctl.scala 2020:69] + wire _T_667 = io_dcsr[8:6] == 3'h3; // @[dec_tlu_ctl.scala 2026:75] + wire dcsr_cause_upgradeable = io_internal_dbg_halt_mode_f & _T_667; // @[dec_tlu_ctl.scala 2026:59] + wire _T_668 = ~io_dbg_tlu_halted; // @[dec_tlu_ctl.scala 2027:59] + wire _T_669 = _T_668 | dcsr_cause_upgradeable; // @[dec_tlu_ctl.scala 2027:78] + wire enter_debug_halt_req_le = io_enter_debug_halt_req & _T_669; // @[dec_tlu_ctl.scala 2027:56] wire nmi_in_debug_mode = io_nmi_int_detected_f & io_internal_dbg_halt_mode_f; // @[dec_tlu_ctl.scala 2029:48] - wire [15:0] _T_665 = {io_dcsr[15:9],dcsr_cause,io_dcsr[5:2],2'h3}; // @[Cat.scala 29:58] - wire _T_671 = nmi_in_debug_mode | io_dcsr[3]; // @[dec_tlu_ctl.scala 2031:145] - wire [15:0] _T_680 = {io_dec_csr_wrdata_r[15],3'h0,io_dec_csr_wrdata_r[11:10],1'h0,io_dcsr[8:6],2'h0,_T_671,io_dec_csr_wrdata_r[2],2'h3}; // @[Cat.scala 29:58] - wire [15:0] _T_685 = {io_dcsr[15:4],nmi_in_debug_mode,io_dcsr[2],2'h3}; // @[Cat.scala 29:58] - wire _T_687 = enter_debug_halt_req_le | wr_dcsr_r; // @[dec_tlu_ctl.scala 2033:54] - wire _T_688 = _T_687 | io_internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 2033:66] - reg [15:0] _T_691; // @[lib.scala 374:16] - wire _T_694 = io_dec_csr_wraddr_r == 12'h7b1; // @[dec_tlu_ctl.scala 2041:97] - wire wr_dpc_r = _T_653 & _T_694; // @[dec_tlu_ctl.scala 2041:68] - wire _T_697 = ~io_request_debug_mode_done; // @[dec_tlu_ctl.scala 2042:67] - wire dpc_capture_npc = _T_579 & _T_697; // @[dec_tlu_ctl.scala 2042:65] - wire _T_698 = ~io_request_debug_mode_r; // @[dec_tlu_ctl.scala 2046:21] - wire _T_699 = ~dpc_capture_npc; // @[dec_tlu_ctl.scala 2046:39] - wire _T_700 = _T_698 & _T_699; // @[dec_tlu_ctl.scala 2046:37] - wire _T_701 = _T_700 & wr_dpc_r; // @[dec_tlu_ctl.scala 2046:56] - wire _T_706 = _T_698 & dpc_capture_npc; // @[dec_tlu_ctl.scala 2048:49] - wire [30:0] _T_708 = _T_701 ? io_dec_csr_wrdata_r[31:1] : 31'h0; // @[Mux.scala 27:72] - wire [30:0] _T_709 = io_request_debug_mode_r ? pc_r : 31'h0; // @[Mux.scala 27:72] - wire [30:0] _T_710 = _T_706 ? io_npc_r : 31'h0; // @[Mux.scala 27:72] - wire [30:0] _T_711 = _T_708 | _T_709; // @[Mux.scala 27:72] - wire _T_713 = wr_dpc_r | io_request_debug_mode_r; // @[dec_tlu_ctl.scala 2050:36] - reg [30:0] _T_716; // @[lib.scala 374:16] - wire [2:0] _T_720 = {io_dec_csr_wrdata_r[24],io_dec_csr_wrdata_r[21:20]}; // @[Cat.scala 29:58] - wire _T_723 = io_dec_csr_wraddr_r == 12'h7c8; // @[dec_tlu_ctl.scala 2065:102] + wire [15:0] _T_675 = {io_dcsr[15:9],dcsr_cause,io_dcsr[5:2],2'h3}; // @[Cat.scala 29:58] + wire _T_681 = nmi_in_debug_mode | io_dcsr[3]; // @[dec_tlu_ctl.scala 2031:145] + wire [15:0] _T_690 = {io_dec_csr_wrdata_r[15],3'h0,io_dec_csr_wrdata_r[11:10],1'h0,io_dcsr[8:6],2'h0,_T_681,io_dec_csr_wrdata_r[2],2'h3}; // @[Cat.scala 29:58] + wire [15:0] _T_695 = {io_dcsr[15:4],nmi_in_debug_mode,io_dcsr[2],2'h3}; // @[Cat.scala 29:58] + wire _T_697 = enter_debug_halt_req_le | wr_dcsr_r; // @[dec_tlu_ctl.scala 2033:54] + wire _T_698 = _T_697 | io_internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 2033:66] + reg [15:0] _T_701; // @[lib.scala 374:16] + wire _T_704 = io_dec_csr_wraddr_r == 12'h7b1; // @[dec_tlu_ctl.scala 2041:97] + wire wr_dpc_r = _T_663 & _T_704; // @[dec_tlu_ctl.scala 2041:68] + wire _T_707 = ~io_request_debug_mode_done; // @[dec_tlu_ctl.scala 2042:67] + wire dpc_capture_npc = _T_589 & _T_707; // @[dec_tlu_ctl.scala 2042:65] + wire _T_708 = ~io_request_debug_mode_r; // @[dec_tlu_ctl.scala 2046:21] + wire _T_709 = ~dpc_capture_npc; // @[dec_tlu_ctl.scala 2046:39] + wire _T_710 = _T_708 & _T_709; // @[dec_tlu_ctl.scala 2046:37] + wire _T_711 = _T_710 & wr_dpc_r; // @[dec_tlu_ctl.scala 2046:56] + wire _T_716 = _T_708 & dpc_capture_npc; // @[dec_tlu_ctl.scala 2048:49] + wire [30:0] _T_718 = _T_711 ? io_dec_csr_wrdata_r[31:1] : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_719 = io_request_debug_mode_r ? pc_r : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_720 = _T_716 ? io_npc_r : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_721 = _T_718 | _T_719; // @[Mux.scala 27:72] + wire _T_723 = wr_dpc_r | io_request_debug_mode_r; // @[dec_tlu_ctl.scala 2050:36] + reg [30:0] _T_726; // @[lib.scala 374:16] + wire [2:0] _T_730 = {io_dec_csr_wrdata_r[24],io_dec_csr_wrdata_r[21:20]}; // @[Cat.scala 29:58] + wire _T_733 = io_dec_csr_wraddr_r == 12'h7c8; // @[dec_tlu_ctl.scala 2065:102] reg [16:0] dicawics; // @[lib.scala 374:16] - wire _T_727 = io_dec_csr_wraddr_r == 12'h7c9; // @[dec_tlu_ctl.scala 2083:100] - wire wr_dicad0_r = _T_653 & _T_727; // @[dec_tlu_ctl.scala 2083:71] + wire _T_737 = io_dec_csr_wraddr_r == 12'h7c9; // @[dec_tlu_ctl.scala 2083:100] + wire wr_dicad0_r = _T_663 & _T_737; // @[dec_tlu_ctl.scala 2083:71] reg [70:0] dicad0; // @[lib.scala 374:16] - wire _T_733 = io_dec_csr_wraddr_r == 12'h7cc; // @[dec_tlu_ctl.scala 2096:101] - wire wr_dicad0h_r = _T_653 & _T_733; // @[dec_tlu_ctl.scala 2096:72] + wire _T_743 = io_dec_csr_wraddr_r == 12'h7cc; // @[dec_tlu_ctl.scala 2096:101] + wire wr_dicad0h_r = _T_663 & _T_743; // @[dec_tlu_ctl.scala 2096:72] reg [31:0] dicad0h; // @[lib.scala 374:16] - wire _T_741 = io_dec_csr_wraddr_r == 12'h7ca; // @[dec_tlu_ctl.scala 2108:100] - wire _T_742 = _T_653 & _T_741; // @[dec_tlu_ctl.scala 2108:71] - wire [31:0] _T_745 = _T_742 ? io_dec_csr_wrdata_r : {{25'd0}, io_ifu_ic_debug_rd_data[70:64]}; // @[dec_tlu_ctl.scala 2110:21] - wire _T_746 = _T_742 | io_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 2113:78] - reg [31:0] _T_748; // @[Reg.scala 27:20] - wire [31:0] dicad1 = {25'h0,_T_748[6:0]}; // @[Cat.scala 29:58] - wire [38:0] _T_753 = {dicad1[6:0],dicad0h}; // @[Cat.scala 29:58] - wire _T_755 = io_allow_dbg_halt_csr_write & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 2141:52] - wire _T_756 = _T_755 & io_dec_i0_decode_d; // @[dec_tlu_ctl.scala 2141:75] - wire _T_757 = ~io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 2141:98] - wire _T_758 = _T_756 & _T_757; // @[dec_tlu_ctl.scala 2141:96] - wire _T_760 = io_dec_csr_rdaddr_d == 12'h7cb; // @[dec_tlu_ctl.scala 2141:149] - wire _T_763 = io_dec_csr_wraddr_r == 12'h7cb; // @[dec_tlu_ctl.scala 2142:104] + wire _T_751 = io_dec_csr_wraddr_r == 12'h7ca; // @[dec_tlu_ctl.scala 2108:100] + wire _T_752 = _T_663 & _T_751; // @[dec_tlu_ctl.scala 2108:71] + wire [31:0] _T_755 = _T_752 ? io_dec_csr_wrdata_r : {{25'd0}, io_ifu_ic_debug_rd_data[70:64]}; // @[dec_tlu_ctl.scala 2110:21] + wire _T_756 = _T_752 | io_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 2113:78] + reg [31:0] _T_758; // @[Reg.scala 27:20] + wire [31:0] dicad1 = {25'h0,_T_758[6:0]}; // @[Cat.scala 29:58] + wire [38:0] _T_763 = {dicad1[6:0],dicad0h}; // @[Cat.scala 29:58] + wire _T_765 = io_allow_dbg_halt_csr_write & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 2141:52] + wire _T_766 = _T_765 & io_dec_i0_decode_d; // @[dec_tlu_ctl.scala 2141:75] + wire _T_767 = ~io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 2141:98] + wire _T_768 = _T_766 & _T_767; // @[dec_tlu_ctl.scala 2141:96] + wire _T_770 = io_dec_csr_rdaddr_d == 12'h7cb; // @[dec_tlu_ctl.scala 2141:149] + wire _T_773 = io_dec_csr_wraddr_r == 12'h7cb; // @[dec_tlu_ctl.scala 2142:104] reg icache_rd_valid_f; // @[dec_tlu_ctl.scala 2144:58] reg icache_wr_valid_f; // @[dec_tlu_ctl.scala 2145:58] - wire _T_765 = io_dec_csr_wraddr_r == 12'h7a0; // @[dec_tlu_ctl.scala 2156:69] - wire wr_mtsel_r = io_dec_csr_wen_r_mod & _T_765; // @[dec_tlu_ctl.scala 2156:40] + wire _T_775 = io_dec_csr_wraddr_r == 12'h7a0; // @[dec_tlu_ctl.scala 2156:69] + wire wr_mtsel_r = io_dec_csr_wen_r_mod & _T_775; // @[dec_tlu_ctl.scala 2156:40] reg [1:0] mtsel; // @[dec_tlu_ctl.scala 2159:43] - wire tdata_load = io_dec_csr_wrdata_r[0] & _T_398; // @[dec_tlu_ctl.scala 2194:42] - wire tdata_opcode = io_dec_csr_wrdata_r[2] & _T_398; // @[dec_tlu_ctl.scala 2196:44] - wire _T_776 = io_dec_csr_wrdata_r[27] & io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2198:46] - wire tdata_action = _T_776 & io_dec_csr_wrdata_r[12]; // @[dec_tlu_ctl.scala 2198:69] - wire [9:0] tdata_wrdata_r = {_T_776,io_dec_csr_wrdata_r[20:19],tdata_action,io_dec_csr_wrdata_r[11],io_dec_csr_wrdata_r[7:6],tdata_opcode,io_dec_csr_wrdata_r[1],tdata_load}; // @[Cat.scala 29:58] - wire _T_791 = io_dec_csr_wraddr_r == 12'h7a1; // @[dec_tlu_ctl.scala 2204:99] - wire _T_792 = io_dec_csr_wen_r_mod & _T_791; // @[dec_tlu_ctl.scala 2204:70] - wire _T_793 = mtsel == 2'h0; // @[dec_tlu_ctl.scala 2204:121] - wire _T_794 = _T_792 & _T_793; // @[dec_tlu_ctl.scala 2204:112] - wire _T_796 = ~io_mtdata1_t_0[9]; // @[dec_tlu_ctl.scala 2204:138] - wire _T_797 = _T_796 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2204:170] - wire wr_mtdata1_t_r_0 = _T_794 & _T_797; // @[dec_tlu_ctl.scala 2204:135] - wire _T_802 = mtsel == 2'h1; // @[dec_tlu_ctl.scala 2204:121] - wire _T_803 = _T_792 & _T_802; // @[dec_tlu_ctl.scala 2204:112] - wire _T_805 = ~io_mtdata1_t_1[9]; // @[dec_tlu_ctl.scala 2204:138] - wire _T_806 = _T_805 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2204:170] - wire wr_mtdata1_t_r_1 = _T_803 & _T_806; // @[dec_tlu_ctl.scala 2204:135] - wire _T_811 = mtsel == 2'h2; // @[dec_tlu_ctl.scala 2204:121] - wire _T_812 = _T_792 & _T_811; // @[dec_tlu_ctl.scala 2204:112] - wire _T_814 = ~io_mtdata1_t_2[9]; // @[dec_tlu_ctl.scala 2204:138] - wire _T_815 = _T_814 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2204:170] - wire wr_mtdata1_t_r_2 = _T_812 & _T_815; // @[dec_tlu_ctl.scala 2204:135] - wire _T_820 = mtsel == 2'h3; // @[dec_tlu_ctl.scala 2204:121] - wire _T_821 = _T_792 & _T_820; // @[dec_tlu_ctl.scala 2204:112] - wire _T_823 = ~io_mtdata1_t_3[9]; // @[dec_tlu_ctl.scala 2204:138] - wire _T_824 = _T_823 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2204:170] - wire wr_mtdata1_t_r_3 = _T_821 & _T_824; // @[dec_tlu_ctl.scala 2204:135] - wire _T_830 = io_update_hit_bit_r[0] | io_mtdata1_t_0[8]; // @[dec_tlu_ctl.scala 2205:139] - wire [9:0] _T_833 = {io_mtdata1_t_0[9],_T_830,io_mtdata1_t_0[7:0]}; // @[Cat.scala 29:58] - wire _T_839 = io_update_hit_bit_r[1] | io_mtdata1_t_1[8]; // @[dec_tlu_ctl.scala 2205:139] - wire [9:0] _T_842 = {io_mtdata1_t_1[9],_T_839,io_mtdata1_t_1[7:0]}; // @[Cat.scala 29:58] - wire _T_848 = io_update_hit_bit_r[2] | io_mtdata1_t_2[8]; // @[dec_tlu_ctl.scala 2205:139] - wire [9:0] _T_851 = {io_mtdata1_t_2[9],_T_848,io_mtdata1_t_2[7:0]}; // @[Cat.scala 29:58] - wire _T_857 = io_update_hit_bit_r[3] | io_mtdata1_t_3[8]; // @[dec_tlu_ctl.scala 2205:139] - wire [9:0] _T_860 = {io_mtdata1_t_3[9],_T_857,io_mtdata1_t_3[7:0]}; // @[Cat.scala 29:58] - reg [9:0] _T_862; // @[dec_tlu_ctl.scala 2207:74] - reg [9:0] _T_863; // @[dec_tlu_ctl.scala 2207:74] - reg [9:0] _T_864; // @[dec_tlu_ctl.scala 2207:74] - reg [9:0] _T_865; // @[dec_tlu_ctl.scala 2207:74] - wire [31:0] _T_880 = {4'h2,io_mtdata1_t_0[9],6'h1f,io_mtdata1_t_0[8:7],6'h0,io_mtdata1_t_0[6:5],3'h0,io_mtdata1_t_0[4:3],3'h0,io_mtdata1_t_0[2:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_895 = {4'h2,io_mtdata1_t_1[9],6'h1f,io_mtdata1_t_1[8:7],6'h0,io_mtdata1_t_1[6:5],3'h0,io_mtdata1_t_1[4:3],3'h0,io_mtdata1_t_1[2:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_910 = {4'h2,io_mtdata1_t_2[9],6'h1f,io_mtdata1_t_2[8:7],6'h0,io_mtdata1_t_2[6:5],3'h0,io_mtdata1_t_2[4:3],3'h0,io_mtdata1_t_2[2:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_925 = {4'h2,io_mtdata1_t_3[9],6'h1f,io_mtdata1_t_3[8:7],6'h0,io_mtdata1_t_3[6:5],3'h0,io_mtdata1_t_3[4:3],3'h0,io_mtdata1_t_3[2:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_926 = _T_793 ? _T_880 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_927 = _T_802 ? _T_895 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_928 = _T_811 ? _T_910 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_929 = _T_820 ? _T_925 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_930 = _T_926 | _T_927; // @[Mux.scala 27:72] - wire [31:0] _T_931 = _T_930 | _T_928; // @[Mux.scala 27:72] - wire [31:0] mtdata1_tsel_out = _T_931 | _T_929; // @[Mux.scala 27:72] - wire _T_958 = io_dec_csr_wraddr_r == 12'h7a2; // @[dec_tlu_ctl.scala 2224:98] - wire _T_959 = io_dec_csr_wen_r_mod & _T_958; // @[dec_tlu_ctl.scala 2224:69] - wire _T_961 = _T_959 & _T_793; // @[dec_tlu_ctl.scala 2224:111] - wire _T_970 = _T_959 & _T_802; // @[dec_tlu_ctl.scala 2224:111] - wire _T_979 = _T_959 & _T_811; // @[dec_tlu_ctl.scala 2224:111] - wire _T_988 = _T_959 & _T_820; // @[dec_tlu_ctl.scala 2224:111] + wire tdata_load = io_dec_csr_wrdata_r[0] & _T_408; // @[dec_tlu_ctl.scala 2194:42] + wire tdata_opcode = io_dec_csr_wrdata_r[2] & _T_408; // @[dec_tlu_ctl.scala 2196:44] + wire _T_786 = io_dec_csr_wrdata_r[27] & io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2198:46] + wire tdata_action = _T_786 & io_dec_csr_wrdata_r[12]; // @[dec_tlu_ctl.scala 2198:69] + wire [9:0] tdata_wrdata_r = {_T_786,io_dec_csr_wrdata_r[20:19],tdata_action,io_dec_csr_wrdata_r[11],io_dec_csr_wrdata_r[7:6],tdata_opcode,io_dec_csr_wrdata_r[1],tdata_load}; // @[Cat.scala 29:58] + wire _T_801 = io_dec_csr_wraddr_r == 12'h7a1; // @[dec_tlu_ctl.scala 2204:99] + wire _T_802 = io_dec_csr_wen_r_mod & _T_801; // @[dec_tlu_ctl.scala 2204:70] + wire _T_803 = mtsel == 2'h0; // @[dec_tlu_ctl.scala 2204:121] + wire _T_804 = _T_802 & _T_803; // @[dec_tlu_ctl.scala 2204:112] + wire _T_806 = ~io_mtdata1_t_0[9]; // @[dec_tlu_ctl.scala 2204:138] + wire _T_807 = _T_806 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2204:170] + wire wr_mtdata1_t_r_0 = _T_804 & _T_807; // @[dec_tlu_ctl.scala 2204:135] + wire _T_812 = mtsel == 2'h1; // @[dec_tlu_ctl.scala 2204:121] + wire _T_813 = _T_802 & _T_812; // @[dec_tlu_ctl.scala 2204:112] + wire _T_815 = ~io_mtdata1_t_1[9]; // @[dec_tlu_ctl.scala 2204:138] + wire _T_816 = _T_815 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2204:170] + wire wr_mtdata1_t_r_1 = _T_813 & _T_816; // @[dec_tlu_ctl.scala 2204:135] + wire _T_821 = mtsel == 2'h2; // @[dec_tlu_ctl.scala 2204:121] + wire _T_822 = _T_802 & _T_821; // @[dec_tlu_ctl.scala 2204:112] + wire _T_824 = ~io_mtdata1_t_2[9]; // @[dec_tlu_ctl.scala 2204:138] + wire _T_825 = _T_824 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2204:170] + wire wr_mtdata1_t_r_2 = _T_822 & _T_825; // @[dec_tlu_ctl.scala 2204:135] + wire _T_830 = mtsel == 2'h3; // @[dec_tlu_ctl.scala 2204:121] + wire _T_831 = _T_802 & _T_830; // @[dec_tlu_ctl.scala 2204:112] + wire _T_833 = ~io_mtdata1_t_3[9]; // @[dec_tlu_ctl.scala 2204:138] + wire _T_834 = _T_833 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2204:170] + wire wr_mtdata1_t_r_3 = _T_831 & _T_834; // @[dec_tlu_ctl.scala 2204:135] + wire _T_840 = io_update_hit_bit_r[0] | io_mtdata1_t_0[8]; // @[dec_tlu_ctl.scala 2205:139] + wire [9:0] _T_843 = {io_mtdata1_t_0[9],_T_840,io_mtdata1_t_0[7:0]}; // @[Cat.scala 29:58] + wire _T_849 = io_update_hit_bit_r[1] | io_mtdata1_t_1[8]; // @[dec_tlu_ctl.scala 2205:139] + wire [9:0] _T_852 = {io_mtdata1_t_1[9],_T_849,io_mtdata1_t_1[7:0]}; // @[Cat.scala 29:58] + wire _T_858 = io_update_hit_bit_r[2] | io_mtdata1_t_2[8]; // @[dec_tlu_ctl.scala 2205:139] + wire [9:0] _T_861 = {io_mtdata1_t_2[9],_T_858,io_mtdata1_t_2[7:0]}; // @[Cat.scala 29:58] + wire _T_867 = io_update_hit_bit_r[3] | io_mtdata1_t_3[8]; // @[dec_tlu_ctl.scala 2205:139] + wire [9:0] _T_870 = {io_mtdata1_t_3[9],_T_867,io_mtdata1_t_3[7:0]}; // @[Cat.scala 29:58] + reg [9:0] _T_872; // @[dec_tlu_ctl.scala 2207:74] + reg [9:0] _T_873; // @[dec_tlu_ctl.scala 2207:74] + reg [9:0] _T_874; // @[dec_tlu_ctl.scala 2207:74] + reg [9:0] _T_875; // @[dec_tlu_ctl.scala 2207:74] + wire [31:0] _T_890 = {4'h2,io_mtdata1_t_0[9],6'h1f,io_mtdata1_t_0[8:7],6'h0,io_mtdata1_t_0[6:5],3'h0,io_mtdata1_t_0[4:3],3'h0,io_mtdata1_t_0[2:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_905 = {4'h2,io_mtdata1_t_1[9],6'h1f,io_mtdata1_t_1[8:7],6'h0,io_mtdata1_t_1[6:5],3'h0,io_mtdata1_t_1[4:3],3'h0,io_mtdata1_t_1[2:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_920 = {4'h2,io_mtdata1_t_2[9],6'h1f,io_mtdata1_t_2[8:7],6'h0,io_mtdata1_t_2[6:5],3'h0,io_mtdata1_t_2[4:3],3'h0,io_mtdata1_t_2[2:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_935 = {4'h2,io_mtdata1_t_3[9],6'h1f,io_mtdata1_t_3[8:7],6'h0,io_mtdata1_t_3[6:5],3'h0,io_mtdata1_t_3[4:3],3'h0,io_mtdata1_t_3[2:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_936 = _T_803 ? _T_890 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_937 = _T_812 ? _T_905 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_938 = _T_821 ? _T_920 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_939 = _T_830 ? _T_935 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_940 = _T_936 | _T_937; // @[Mux.scala 27:72] + wire [31:0] _T_941 = _T_940 | _T_938; // @[Mux.scala 27:72] + wire [31:0] mtdata1_tsel_out = _T_941 | _T_939; // @[Mux.scala 27:72] + wire _T_968 = io_dec_csr_wraddr_r == 12'h7a2; // @[dec_tlu_ctl.scala 2224:98] + wire _T_969 = io_dec_csr_wen_r_mod & _T_968; // @[dec_tlu_ctl.scala 2224:69] + wire _T_971 = _T_969 & _T_803; // @[dec_tlu_ctl.scala 2224:111] + wire _T_980 = _T_969 & _T_812; // @[dec_tlu_ctl.scala 2224:111] + wire _T_989 = _T_969 & _T_821; // @[dec_tlu_ctl.scala 2224:111] + wire _T_998 = _T_969 & _T_830; // @[dec_tlu_ctl.scala 2224:111] reg [31:0] mtdata2_t_0; // @[lib.scala 374:16] reg [31:0] mtdata2_t_1; // @[lib.scala 374:16] reg [31:0] mtdata2_t_2; // @[lib.scala 374:16] reg [31:0] mtdata2_t_3; // @[lib.scala 374:16] - wire [31:0] _T_1005 = _T_793 ? mtdata2_t_0 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_1006 = _T_802 ? mtdata2_t_1 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_1007 = _T_811 ? mtdata2_t_2 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_1008 = _T_820 ? mtdata2_t_3 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_1009 = _T_1005 | _T_1006; // @[Mux.scala 27:72] - wire [31:0] _T_1010 = _T_1009 | _T_1007; // @[Mux.scala 27:72] - wire [31:0] mtdata2_tsel_out = _T_1010 | _T_1008; // @[Mux.scala 27:72] - wire [3:0] _T_1013 = io_tlu_i0_commit_cmt ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] pmu_i0_itype_qual = io_dec_tlu_packet_r_pmu_i0_itype & _T_1013; // @[dec_tlu_ctl.scala 2249:59] - wire _T_1015 = ~mcountinhibit[3]; // @[dec_tlu_ctl.scala 2255:24] + wire [31:0] _T_1015 = _T_803 ? mtdata2_t_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1016 = _T_812 ? mtdata2_t_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1017 = _T_821 ? mtdata2_t_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1018 = _T_830 ? mtdata2_t_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1019 = _T_1015 | _T_1016; // @[Mux.scala 27:72] + wire [31:0] _T_1020 = _T_1019 | _T_1017; // @[Mux.scala 27:72] + wire [31:0] mtdata2_tsel_out = _T_1020 | _T_1018; // @[Mux.scala 27:72] + wire [3:0] _T_1023 = io_tlu_i0_commit_cmt ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] pmu_i0_itype_qual = io_dec_tlu_packet_r_pmu_i0_itype & _T_1023; // @[dec_tlu_ctl.scala 2249:59] + wire _T_1025 = ~mcountinhibit[3]; // @[dec_tlu_ctl.scala 2255:24] reg [9:0] mhpme3; // @[Reg.scala 27:20] - wire _T_1016 = mhpme3 == 10'h1; // @[dec_tlu_ctl.scala 2256:34] - wire _T_1018 = mhpme3 == 10'h2; // @[dec_tlu_ctl.scala 2257:34] - wire _T_1020 = mhpme3 == 10'h3; // @[dec_tlu_ctl.scala 2258:34] - wire _T_1022 = mhpme3 == 10'h4; // @[dec_tlu_ctl.scala 2259:34] - wire _T_1024 = ~io_illegal_r; // @[dec_tlu_ctl.scala 2259:96] - wire _T_1025 = io_tlu_i0_commit_cmt & _T_1024; // @[dec_tlu_ctl.scala 2259:94] - wire _T_1026 = mhpme3 == 10'h5; // @[dec_tlu_ctl.scala 2260:34] - wire _T_1028 = ~io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2260:96] - wire _T_1029 = io_tlu_i0_commit_cmt & _T_1028; // @[dec_tlu_ctl.scala 2260:94] - wire _T_1031 = _T_1029 & _T_1024; // @[dec_tlu_ctl.scala 2260:115] - wire _T_1032 = mhpme3 == 10'h6; // @[dec_tlu_ctl.scala 2261:34] - wire _T_1034 = io_tlu_i0_commit_cmt & io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2261:94] - wire _T_1036 = _T_1034 & _T_1024; // @[dec_tlu_ctl.scala 2261:115] - wire _T_1037 = mhpme3 == 10'h7; // @[dec_tlu_ctl.scala 2262:34] - wire _T_1039 = mhpme3 == 10'h8; // @[dec_tlu_ctl.scala 2263:34] - wire _T_1041 = mhpme3 == 10'h1e; // @[dec_tlu_ctl.scala 2264:34] - wire _T_1043 = mhpme3 == 10'h9; // @[dec_tlu_ctl.scala 2265:34] - wire _T_1045 = pmu_i0_itype_qual == 4'h1; // @[dec_tlu_ctl.scala 2265:91] - wire _T_1046 = mhpme3 == 10'ha; // @[dec_tlu_ctl.scala 2266:34] - wire _T_1048 = io_dec_tlu_packet_r_pmu_divide & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2266:105] - wire _T_1049 = mhpme3 == 10'hb; // @[dec_tlu_ctl.scala 2267:34] - wire _T_1051 = pmu_i0_itype_qual == 4'h2; // @[dec_tlu_ctl.scala 2267:91] - wire _T_1052 = mhpme3 == 10'hc; // @[dec_tlu_ctl.scala 2268:34] - wire _T_1054 = pmu_i0_itype_qual == 4'h3; // @[dec_tlu_ctl.scala 2268:91] - wire _T_1055 = mhpme3 == 10'hd; // @[dec_tlu_ctl.scala 2269:34] - wire _T_1058 = _T_1051 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2269:100] - wire _T_1059 = mhpme3 == 10'he; // @[dec_tlu_ctl.scala 2270:34] - wire _T_1063 = _T_1054 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2270:101] - wire _T_1064 = mhpme3 == 10'hf; // @[dec_tlu_ctl.scala 2271:34] - wire _T_1066 = pmu_i0_itype_qual == 4'h4; // @[dec_tlu_ctl.scala 2271:89] - wire _T_1067 = mhpme3 == 10'h10; // @[dec_tlu_ctl.scala 2272:34] - wire _T_1069 = pmu_i0_itype_qual == 4'h5; // @[dec_tlu_ctl.scala 2272:89] - wire _T_1070 = mhpme3 == 10'h12; // @[dec_tlu_ctl.scala 2273:34] - wire _T_1072 = pmu_i0_itype_qual == 4'h6; // @[dec_tlu_ctl.scala 2273:89] - wire _T_1073 = mhpme3 == 10'h11; // @[dec_tlu_ctl.scala 2274:34] - wire _T_1075 = pmu_i0_itype_qual == 4'h7; // @[dec_tlu_ctl.scala 2274:89] - wire _T_1076 = mhpme3 == 10'h13; // @[dec_tlu_ctl.scala 2275:34] - wire _T_1078 = pmu_i0_itype_qual == 4'h8; // @[dec_tlu_ctl.scala 2275:89] - wire _T_1079 = mhpme3 == 10'h14; // @[dec_tlu_ctl.scala 2276:34] - wire _T_1081 = pmu_i0_itype_qual == 4'h9; // @[dec_tlu_ctl.scala 2276:89] - wire _T_1082 = mhpme3 == 10'h15; // @[dec_tlu_ctl.scala 2277:34] - wire _T_1084 = pmu_i0_itype_qual == 4'ha; // @[dec_tlu_ctl.scala 2277:89] - wire _T_1085 = mhpme3 == 10'h16; // @[dec_tlu_ctl.scala 2278:34] - wire _T_1087 = pmu_i0_itype_qual == 4'hb; // @[dec_tlu_ctl.scala 2278:89] - wire _T_1088 = mhpme3 == 10'h17; // @[dec_tlu_ctl.scala 2279:34] - wire _T_1090 = pmu_i0_itype_qual == 4'hc; // @[dec_tlu_ctl.scala 2279:89] - wire _T_1091 = mhpme3 == 10'h18; // @[dec_tlu_ctl.scala 2280:34] - wire _T_1093 = pmu_i0_itype_qual == 4'hd; // @[dec_tlu_ctl.scala 2280:89] - wire _T_1094 = pmu_i0_itype_qual == 4'he; // @[dec_tlu_ctl.scala 2280:122] - wire _T_1095 = _T_1093 | _T_1094; // @[dec_tlu_ctl.scala 2280:101] - wire _T_1096 = mhpme3 == 10'h19; // @[dec_tlu_ctl.scala 2281:34] - wire _T_1098 = io_exu_pmu_i0_br_misp & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2281:95] - wire _T_1099 = mhpme3 == 10'h1a; // @[dec_tlu_ctl.scala 2282:34] - wire _T_1101 = io_exu_pmu_i0_br_ataken & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2282:97] - wire _T_1102 = mhpme3 == 10'h1b; // @[dec_tlu_ctl.scala 2283:34] - wire _T_1104 = io_dec_tlu_packet_r_pmu_i0_br_unpred & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2283:110] - wire _T_1105 = mhpme3 == 10'h1c; // @[dec_tlu_ctl.scala 2284:34] - wire _T_1109 = mhpme3 == 10'h1f; // @[dec_tlu_ctl.scala 2286:34] - wire _T_1111 = mhpme3 == 10'h20; // @[dec_tlu_ctl.scala 2287:34] - wire _T_1113 = mhpme3 == 10'h22; // @[dec_tlu_ctl.scala 2288:34] - wire _T_1115 = mhpme3 == 10'h23; // @[dec_tlu_ctl.scala 2289:34] - wire _T_1117 = mhpme3 == 10'h24; // @[dec_tlu_ctl.scala 2290:34] - wire _T_1119 = mhpme3 == 10'h25; // @[dec_tlu_ctl.scala 2291:34] - wire _T_1121 = io_i0_exception_valid_r | io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 2291:98] - wire _T_1122 = _T_1121 | io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 2291:120] - wire _T_1123 = mhpme3 == 10'h26; // @[dec_tlu_ctl.scala 2292:34] - wire _T_1125 = io_take_timer_int | io_take_int_timer0_int; // @[dec_tlu_ctl.scala 2292:92] - wire _T_1126 = _T_1125 | io_take_int_timer1_int; // @[dec_tlu_ctl.scala 2292:117] - wire _T_1127 = mhpme3 == 10'h27; // @[dec_tlu_ctl.scala 2293:34] - wire _T_1129 = mhpme3 == 10'h28; // @[dec_tlu_ctl.scala 2294:34] - wire _T_1131 = mhpme3 == 10'h29; // @[dec_tlu_ctl.scala 2295:34] - wire _T_1133 = io_dec_tlu_br0_error_r | io_dec_tlu_br0_start_error_r; // @[dec_tlu_ctl.scala 2295:97] - wire _T_1134 = _T_1133 & io_rfpc_i0_r; // @[dec_tlu_ctl.scala 2295:129] - wire _T_1135 = mhpme3 == 10'h2a; // @[dec_tlu_ctl.scala 2296:34] - wire _T_1137 = mhpme3 == 10'h2b; // @[dec_tlu_ctl.scala 2297:34] - wire _T_1139 = mhpme3 == 10'h2c; // @[dec_tlu_ctl.scala 2298:34] - wire _T_1141 = mhpme3 == 10'h2d; // @[dec_tlu_ctl.scala 2299:34] - wire _T_1143 = mhpme3 == 10'h2e; // @[dec_tlu_ctl.scala 2300:34] - wire _T_1145 = mhpme3 == 10'h2f; // @[dec_tlu_ctl.scala 2301:34] - wire _T_1147 = mhpme3 == 10'h30; // @[dec_tlu_ctl.scala 2302:34] - wire _T_1149 = mhpme3 == 10'h31; // @[dec_tlu_ctl.scala 2303:34] - wire _T_1153 = ~io_mstatus[0]; // @[dec_tlu_ctl.scala 2303:73] - wire _T_1154 = mhpme3 == 10'h32; // @[dec_tlu_ctl.scala 2304:34] - wire [5:0] _T_1161 = io_mip & mie; // @[dec_tlu_ctl.scala 2304:113] - wire _T_1162 = |_T_1161; // @[dec_tlu_ctl.scala 2304:125] - wire _T_1163 = _T_1153 & _T_1162; // @[dec_tlu_ctl.scala 2304:98] - wire _T_1164 = mhpme3 == 10'h36; // @[dec_tlu_ctl.scala 2305:34] - wire _T_1166 = pmu_i0_itype_qual == 4'hf; // @[dec_tlu_ctl.scala 2305:91] - wire _T_1167 = mhpme3 == 10'h37; // @[dec_tlu_ctl.scala 2306:34] - wire _T_1169 = io_tlu_i0_commit_cmt & io_lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 2306:94] - wire _T_1170 = mhpme3 == 10'h38; // @[dec_tlu_ctl.scala 2307:34] - wire _T_1172 = io_tlu_i0_commit_cmt & io_lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 2307:94] - wire _T_1173 = mhpme3 == 10'h200; // @[dec_tlu_ctl.scala 2309:34] - wire _T_1175 = mhpme3 == 10'h201; // @[dec_tlu_ctl.scala 2310:34] - wire _T_1177 = mhpme3 == 10'h202; // @[dec_tlu_ctl.scala 2311:34] - wire _T_1179 = mhpme3 == 10'h203; // @[dec_tlu_ctl.scala 2312:34] - wire _T_1181 = mhpme3 == 10'h204; // @[dec_tlu_ctl.scala 2313:34] - wire _T_1184 = _T_1018 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] - wire _T_1185 = _T_1020 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] - wire _T_1186 = _T_1022 & _T_1025; // @[Mux.scala 27:72] - wire _T_1187 = _T_1026 & _T_1031; // @[Mux.scala 27:72] - wire _T_1188 = _T_1032 & _T_1036; // @[Mux.scala 27:72] - wire _T_1189 = _T_1037 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] - wire _T_1190 = _T_1039 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] - wire _T_1191 = _T_1041 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] - wire _T_1192 = _T_1043 & _T_1045; // @[Mux.scala 27:72] - wire _T_1193 = _T_1046 & _T_1048; // @[Mux.scala 27:72] - wire _T_1194 = _T_1049 & _T_1051; // @[Mux.scala 27:72] - wire _T_1195 = _T_1052 & _T_1054; // @[Mux.scala 27:72] - wire _T_1196 = _T_1055 & _T_1058; // @[Mux.scala 27:72] - wire _T_1197 = _T_1059 & _T_1063; // @[Mux.scala 27:72] - wire _T_1198 = _T_1064 & _T_1066; // @[Mux.scala 27:72] - wire _T_1199 = _T_1067 & _T_1069; // @[Mux.scala 27:72] - wire _T_1200 = _T_1070 & _T_1072; // @[Mux.scala 27:72] - wire _T_1201 = _T_1073 & _T_1075; // @[Mux.scala 27:72] - wire _T_1202 = _T_1076 & _T_1078; // @[Mux.scala 27:72] - wire _T_1203 = _T_1079 & _T_1081; // @[Mux.scala 27:72] - wire _T_1204 = _T_1082 & _T_1084; // @[Mux.scala 27:72] - wire _T_1205 = _T_1085 & _T_1087; // @[Mux.scala 27:72] - wire _T_1206 = _T_1088 & _T_1090; // @[Mux.scala 27:72] - wire _T_1207 = _T_1091 & _T_1095; // @[Mux.scala 27:72] - wire _T_1208 = _T_1096 & _T_1098; // @[Mux.scala 27:72] - wire _T_1209 = _T_1099 & _T_1101; // @[Mux.scala 27:72] - wire _T_1210 = _T_1102 & _T_1104; // @[Mux.scala 27:72] - wire _T_1211 = _T_1105 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] - wire _T_1213 = _T_1109 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] - wire _T_1214 = _T_1111 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] - wire _T_1215 = _T_1113 & io_lsu_store_stall_any; // @[Mux.scala 27:72] - wire _T_1216 = _T_1115 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] - wire _T_1217 = _T_1117 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] - wire _T_1218 = _T_1119 & _T_1122; // @[Mux.scala 27:72] - wire _T_1219 = _T_1123 & _T_1126; // @[Mux.scala 27:72] - wire _T_1220 = _T_1127 & io_take_ext_int; // @[Mux.scala 27:72] - wire _T_1221 = _T_1129 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] - wire _T_1222 = _T_1131 & _T_1134; // @[Mux.scala 27:72] - wire _T_1223 = _T_1135 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1224 = _T_1137 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1225 = _T_1139 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] - wire _T_1226 = _T_1141 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1227 = _T_1143 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1228 = _T_1145 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1229 = _T_1147 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1230 = _T_1149 & _T_1153; // @[Mux.scala 27:72] - wire _T_1231 = _T_1154 & _T_1163; // @[Mux.scala 27:72] - wire _T_1232 = _T_1164 & _T_1166; // @[Mux.scala 27:72] - wire _T_1233 = _T_1167 & _T_1169; // @[Mux.scala 27:72] - wire _T_1234 = _T_1170 & _T_1172; // @[Mux.scala 27:72] - wire _T_1235 = _T_1173 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] - wire _T_1236 = _T_1175 & io_dma_pmu_any_read; // @[Mux.scala 27:72] - wire _T_1237 = _T_1177 & io_dma_pmu_any_write; // @[Mux.scala 27:72] - wire _T_1238 = _T_1179 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] - wire _T_1239 = _T_1181 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] - wire _T_1240 = _T_1016 | _T_1184; // @[Mux.scala 27:72] - wire _T_1241 = _T_1240 | _T_1185; // @[Mux.scala 27:72] - wire _T_1242 = _T_1241 | _T_1186; // @[Mux.scala 27:72] - wire _T_1243 = _T_1242 | _T_1187; // @[Mux.scala 27:72] - wire _T_1244 = _T_1243 | _T_1188; // @[Mux.scala 27:72] - wire _T_1245 = _T_1244 | _T_1189; // @[Mux.scala 27:72] - wire _T_1246 = _T_1245 | _T_1190; // @[Mux.scala 27:72] - wire _T_1247 = _T_1246 | _T_1191; // @[Mux.scala 27:72] - wire _T_1248 = _T_1247 | _T_1192; // @[Mux.scala 27:72] - wire _T_1249 = _T_1248 | _T_1193; // @[Mux.scala 27:72] - wire _T_1250 = _T_1249 | _T_1194; // @[Mux.scala 27:72] + wire _T_1026 = mhpme3 == 10'h1; // @[dec_tlu_ctl.scala 2256:34] + wire _T_1028 = mhpme3 == 10'h2; // @[dec_tlu_ctl.scala 2257:34] + wire _T_1030 = mhpme3 == 10'h3; // @[dec_tlu_ctl.scala 2258:34] + wire _T_1032 = mhpme3 == 10'h4; // @[dec_tlu_ctl.scala 2259:34] + wire _T_1034 = ~io_illegal_r; // @[dec_tlu_ctl.scala 2259:96] + wire _T_1035 = io_tlu_i0_commit_cmt & _T_1034; // @[dec_tlu_ctl.scala 2259:94] + wire _T_1036 = mhpme3 == 10'h5; // @[dec_tlu_ctl.scala 2260:34] + wire _T_1038 = ~io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2260:96] + wire _T_1039 = io_tlu_i0_commit_cmt & _T_1038; // @[dec_tlu_ctl.scala 2260:94] + wire _T_1041 = _T_1039 & _T_1034; // @[dec_tlu_ctl.scala 2260:115] + wire _T_1042 = mhpme3 == 10'h6; // @[dec_tlu_ctl.scala 2261:34] + wire _T_1044 = io_tlu_i0_commit_cmt & io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2261:94] + wire _T_1046 = _T_1044 & _T_1034; // @[dec_tlu_ctl.scala 2261:115] + wire _T_1047 = mhpme3 == 10'h7; // @[dec_tlu_ctl.scala 2262:34] + wire _T_1049 = mhpme3 == 10'h8; // @[dec_tlu_ctl.scala 2263:34] + wire _T_1051 = mhpme3 == 10'h1e; // @[dec_tlu_ctl.scala 2264:34] + wire _T_1053 = mhpme3 == 10'h9; // @[dec_tlu_ctl.scala 2265:34] + wire _T_1055 = pmu_i0_itype_qual == 4'h1; // @[dec_tlu_ctl.scala 2265:91] + wire _T_1056 = mhpme3 == 10'ha; // @[dec_tlu_ctl.scala 2266:34] + wire _T_1058 = io_dec_tlu_packet_r_pmu_divide & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2266:105] + wire _T_1059 = mhpme3 == 10'hb; // @[dec_tlu_ctl.scala 2267:34] + wire _T_1061 = pmu_i0_itype_qual == 4'h2; // @[dec_tlu_ctl.scala 2267:91] + wire _T_1062 = mhpme3 == 10'hc; // @[dec_tlu_ctl.scala 2268:34] + wire _T_1064 = pmu_i0_itype_qual == 4'h3; // @[dec_tlu_ctl.scala 2268:91] + wire _T_1065 = mhpme3 == 10'hd; // @[dec_tlu_ctl.scala 2269:34] + wire _T_1068 = _T_1061 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2269:100] + wire _T_1069 = mhpme3 == 10'he; // @[dec_tlu_ctl.scala 2270:34] + wire _T_1073 = _T_1064 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2270:101] + wire _T_1074 = mhpme3 == 10'hf; // @[dec_tlu_ctl.scala 2271:34] + wire _T_1076 = pmu_i0_itype_qual == 4'h4; // @[dec_tlu_ctl.scala 2271:89] + wire _T_1077 = mhpme3 == 10'h10; // @[dec_tlu_ctl.scala 2272:34] + wire _T_1079 = pmu_i0_itype_qual == 4'h5; // @[dec_tlu_ctl.scala 2272:89] + wire _T_1080 = mhpme3 == 10'h12; // @[dec_tlu_ctl.scala 2273:34] + wire _T_1082 = pmu_i0_itype_qual == 4'h6; // @[dec_tlu_ctl.scala 2273:89] + wire _T_1083 = mhpme3 == 10'h11; // @[dec_tlu_ctl.scala 2274:34] + wire _T_1085 = pmu_i0_itype_qual == 4'h7; // @[dec_tlu_ctl.scala 2274:89] + wire _T_1086 = mhpme3 == 10'h13; // @[dec_tlu_ctl.scala 2275:34] + wire _T_1088 = pmu_i0_itype_qual == 4'h8; // @[dec_tlu_ctl.scala 2275:89] + wire _T_1089 = mhpme3 == 10'h14; // @[dec_tlu_ctl.scala 2276:34] + wire _T_1091 = pmu_i0_itype_qual == 4'h9; // @[dec_tlu_ctl.scala 2276:89] + wire _T_1092 = mhpme3 == 10'h15; // @[dec_tlu_ctl.scala 2277:34] + wire _T_1094 = pmu_i0_itype_qual == 4'ha; // @[dec_tlu_ctl.scala 2277:89] + wire _T_1095 = mhpme3 == 10'h16; // @[dec_tlu_ctl.scala 2278:34] + wire _T_1097 = pmu_i0_itype_qual == 4'hb; // @[dec_tlu_ctl.scala 2278:89] + wire _T_1098 = mhpme3 == 10'h17; // @[dec_tlu_ctl.scala 2279:34] + wire _T_1100 = pmu_i0_itype_qual == 4'hc; // @[dec_tlu_ctl.scala 2279:89] + wire _T_1101 = mhpme3 == 10'h18; // @[dec_tlu_ctl.scala 2280:34] + wire _T_1103 = pmu_i0_itype_qual == 4'hd; // @[dec_tlu_ctl.scala 2280:89] + wire _T_1104 = pmu_i0_itype_qual == 4'he; // @[dec_tlu_ctl.scala 2280:122] + wire _T_1105 = _T_1103 | _T_1104; // @[dec_tlu_ctl.scala 2280:101] + wire _T_1106 = mhpme3 == 10'h19; // @[dec_tlu_ctl.scala 2281:34] + wire _T_1108 = io_exu_pmu_i0_br_misp & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2281:95] + wire _T_1109 = mhpme3 == 10'h1a; // @[dec_tlu_ctl.scala 2282:34] + wire _T_1111 = io_exu_pmu_i0_br_ataken & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2282:97] + wire _T_1112 = mhpme3 == 10'h1b; // @[dec_tlu_ctl.scala 2283:34] + wire _T_1114 = io_dec_tlu_packet_r_pmu_i0_br_unpred & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2283:110] + wire _T_1115 = mhpme3 == 10'h1c; // @[dec_tlu_ctl.scala 2284:34] + wire _T_1119 = mhpme3 == 10'h1f; // @[dec_tlu_ctl.scala 2286:34] + wire _T_1121 = mhpme3 == 10'h20; // @[dec_tlu_ctl.scala 2287:34] + wire _T_1123 = mhpme3 == 10'h22; // @[dec_tlu_ctl.scala 2288:34] + wire _T_1125 = mhpme3 == 10'h23; // @[dec_tlu_ctl.scala 2289:34] + wire _T_1127 = mhpme3 == 10'h24; // @[dec_tlu_ctl.scala 2290:34] + wire _T_1129 = mhpme3 == 10'h25; // @[dec_tlu_ctl.scala 2291:34] + wire _T_1131 = io_i0_exception_valid_r | io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 2291:98] + wire _T_1132 = _T_1131 | io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 2291:120] + wire _T_1133 = mhpme3 == 10'h26; // @[dec_tlu_ctl.scala 2292:34] + wire _T_1135 = io_take_timer_int | io_take_int_timer0_int; // @[dec_tlu_ctl.scala 2292:92] + wire _T_1136 = _T_1135 | io_take_int_timer1_int; // @[dec_tlu_ctl.scala 2292:117] + wire _T_1137 = mhpme3 == 10'h27; // @[dec_tlu_ctl.scala 2293:34] + wire _T_1139 = mhpme3 == 10'h28; // @[dec_tlu_ctl.scala 2294:34] + wire _T_1141 = mhpme3 == 10'h29; // @[dec_tlu_ctl.scala 2295:34] + wire _T_1143 = io_dec_tlu_br0_error_r | io_dec_tlu_br0_start_error_r; // @[dec_tlu_ctl.scala 2295:97] + wire _T_1144 = _T_1143 & io_rfpc_i0_r; // @[dec_tlu_ctl.scala 2295:129] + wire _T_1145 = mhpme3 == 10'h2a; // @[dec_tlu_ctl.scala 2296:34] + wire _T_1147 = mhpme3 == 10'h2b; // @[dec_tlu_ctl.scala 2297:34] + wire _T_1149 = mhpme3 == 10'h2c; // @[dec_tlu_ctl.scala 2298:34] + wire _T_1151 = mhpme3 == 10'h2d; // @[dec_tlu_ctl.scala 2299:34] + wire _T_1153 = mhpme3 == 10'h2e; // @[dec_tlu_ctl.scala 2300:34] + wire _T_1155 = mhpme3 == 10'h2f; // @[dec_tlu_ctl.scala 2301:34] + wire _T_1157 = mhpme3 == 10'h30; // @[dec_tlu_ctl.scala 2302:34] + wire _T_1159 = mhpme3 == 10'h31; // @[dec_tlu_ctl.scala 2303:34] + wire _T_1163 = ~io_mstatus[0]; // @[dec_tlu_ctl.scala 2303:73] + wire _T_1164 = mhpme3 == 10'h32; // @[dec_tlu_ctl.scala 2304:34] + wire [5:0] _T_1171 = io_mip & mie; // @[dec_tlu_ctl.scala 2304:113] + wire _T_1172 = |_T_1171; // @[dec_tlu_ctl.scala 2304:125] + wire _T_1173 = _T_1163 & _T_1172; // @[dec_tlu_ctl.scala 2304:98] + wire _T_1174 = mhpme3 == 10'h36; // @[dec_tlu_ctl.scala 2305:34] + wire _T_1176 = pmu_i0_itype_qual == 4'hf; // @[dec_tlu_ctl.scala 2305:91] + wire _T_1177 = mhpme3 == 10'h37; // @[dec_tlu_ctl.scala 2306:34] + wire _T_1179 = io_tlu_i0_commit_cmt & io_lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 2306:94] + wire _T_1180 = mhpme3 == 10'h38; // @[dec_tlu_ctl.scala 2307:34] + wire _T_1182 = io_tlu_i0_commit_cmt & io_lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 2307:94] + wire _T_1183 = mhpme3 == 10'h200; // @[dec_tlu_ctl.scala 2309:34] + wire _T_1185 = mhpme3 == 10'h201; // @[dec_tlu_ctl.scala 2310:34] + wire _T_1187 = mhpme3 == 10'h202; // @[dec_tlu_ctl.scala 2311:34] + wire _T_1189 = mhpme3 == 10'h203; // @[dec_tlu_ctl.scala 2312:34] + wire _T_1191 = mhpme3 == 10'h204; // @[dec_tlu_ctl.scala 2313:34] + wire _T_1194 = _T_1028 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_1195 = _T_1030 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_1196 = _T_1032 & _T_1035; // @[Mux.scala 27:72] + wire _T_1197 = _T_1036 & _T_1041; // @[Mux.scala 27:72] + wire _T_1198 = _T_1042 & _T_1046; // @[Mux.scala 27:72] + wire _T_1199 = _T_1047 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_1200 = _T_1049 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_1201 = _T_1051 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_1202 = _T_1053 & _T_1055; // @[Mux.scala 27:72] + wire _T_1203 = _T_1056 & _T_1058; // @[Mux.scala 27:72] + wire _T_1204 = _T_1059 & _T_1061; // @[Mux.scala 27:72] + wire _T_1205 = _T_1062 & _T_1064; // @[Mux.scala 27:72] + wire _T_1206 = _T_1065 & _T_1068; // @[Mux.scala 27:72] + wire _T_1207 = _T_1069 & _T_1073; // @[Mux.scala 27:72] + wire _T_1208 = _T_1074 & _T_1076; // @[Mux.scala 27:72] + wire _T_1209 = _T_1077 & _T_1079; // @[Mux.scala 27:72] + wire _T_1210 = _T_1080 & _T_1082; // @[Mux.scala 27:72] + wire _T_1211 = _T_1083 & _T_1085; // @[Mux.scala 27:72] + wire _T_1212 = _T_1086 & _T_1088; // @[Mux.scala 27:72] + wire _T_1213 = _T_1089 & _T_1091; // @[Mux.scala 27:72] + wire _T_1214 = _T_1092 & _T_1094; // @[Mux.scala 27:72] + wire _T_1215 = _T_1095 & _T_1097; // @[Mux.scala 27:72] + wire _T_1216 = _T_1098 & _T_1100; // @[Mux.scala 27:72] + wire _T_1217 = _T_1101 & _T_1105; // @[Mux.scala 27:72] + wire _T_1218 = _T_1106 & _T_1108; // @[Mux.scala 27:72] + wire _T_1219 = _T_1109 & _T_1111; // @[Mux.scala 27:72] + wire _T_1220 = _T_1112 & _T_1114; // @[Mux.scala 27:72] + wire _T_1221 = _T_1115 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_1223 = _T_1119 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_1224 = _T_1121 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_1225 = _T_1123 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_1226 = _T_1125 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_1227 = _T_1127 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_1228 = _T_1129 & _T_1132; // @[Mux.scala 27:72] + wire _T_1229 = _T_1133 & _T_1136; // @[Mux.scala 27:72] + wire _T_1230 = _T_1137 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_1231 = _T_1139 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_1232 = _T_1141 & _T_1144; // @[Mux.scala 27:72] + wire _T_1233 = _T_1145 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1234 = _T_1147 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1235 = _T_1149 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_1236 = _T_1151 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1237 = _T_1153 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1238 = _T_1155 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1239 = _T_1157 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1240 = _T_1159 & _T_1163; // @[Mux.scala 27:72] + wire _T_1241 = _T_1164 & _T_1173; // @[Mux.scala 27:72] + wire _T_1242 = _T_1174 & _T_1176; // @[Mux.scala 27:72] + wire _T_1243 = _T_1177 & _T_1179; // @[Mux.scala 27:72] + wire _T_1244 = _T_1180 & _T_1182; // @[Mux.scala 27:72] + wire _T_1245 = _T_1183 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_1246 = _T_1185 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_1247 = _T_1187 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_1248 = _T_1189 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_1249 = _T_1191 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_1250 = _T_1026 | _T_1194; // @[Mux.scala 27:72] wire _T_1251 = _T_1250 | _T_1195; // @[Mux.scala 27:72] wire _T_1252 = _T_1251 | _T_1196; // @[Mux.scala 27:72] wire _T_1253 = _T_1252 | _T_1197; // @[Mux.scala 27:72] @@ -51615,7 +51616,7 @@ module csr_tlu( wire _T_1265 = _T_1264 | _T_1209; // @[Mux.scala 27:72] wire _T_1266 = _T_1265 | _T_1210; // @[Mux.scala 27:72] wire _T_1267 = _T_1266 | _T_1211; // @[Mux.scala 27:72] - wire _T_1268 = _T_1267 | _T_1191; // @[Mux.scala 27:72] + wire _T_1268 = _T_1267 | _T_1212; // @[Mux.scala 27:72] wire _T_1269 = _T_1268 | _T_1213; // @[Mux.scala 27:72] wire _T_1270 = _T_1269 | _T_1214; // @[Mux.scala 27:72] wire _T_1271 = _T_1270 | _T_1215; // @[Mux.scala 27:72] @@ -51625,7 +51626,7 @@ module csr_tlu( wire _T_1275 = _T_1274 | _T_1219; // @[Mux.scala 27:72] wire _T_1276 = _T_1275 | _T_1220; // @[Mux.scala 27:72] wire _T_1277 = _T_1276 | _T_1221; // @[Mux.scala 27:72] - wire _T_1278 = _T_1277 | _T_1222; // @[Mux.scala 27:72] + wire _T_1278 = _T_1277 | _T_1201; // @[Mux.scala 27:72] wire _T_1279 = _T_1278 | _T_1223; // @[Mux.scala 27:72] wire _T_1280 = _T_1279 | _T_1224; // @[Mux.scala 27:72] wire _T_1281 = _T_1280 | _T_1225; // @[Mux.scala 27:72] @@ -51643,131 +51644,131 @@ module csr_tlu( wire _T_1293 = _T_1292 | _T_1237; // @[Mux.scala 27:72] wire _T_1294 = _T_1293 | _T_1238; // @[Mux.scala 27:72] wire _T_1295 = _T_1294 | _T_1239; // @[Mux.scala 27:72] - wire mhpmc_inc_r_0 = _T_1015 & _T_1295; // @[dec_tlu_ctl.scala 2255:44] - wire _T_1299 = ~mcountinhibit[4]; // @[dec_tlu_ctl.scala 2255:24] + wire _T_1296 = _T_1295 | _T_1240; // @[Mux.scala 27:72] + wire _T_1297 = _T_1296 | _T_1241; // @[Mux.scala 27:72] + wire _T_1298 = _T_1297 | _T_1242; // @[Mux.scala 27:72] + wire _T_1299 = _T_1298 | _T_1243; // @[Mux.scala 27:72] + wire _T_1300 = _T_1299 | _T_1244; // @[Mux.scala 27:72] + wire _T_1301 = _T_1300 | _T_1245; // @[Mux.scala 27:72] + wire _T_1302 = _T_1301 | _T_1246; // @[Mux.scala 27:72] + wire _T_1303 = _T_1302 | _T_1247; // @[Mux.scala 27:72] + wire _T_1304 = _T_1303 | _T_1248; // @[Mux.scala 27:72] + wire _T_1305 = _T_1304 | _T_1249; // @[Mux.scala 27:72] + wire mhpmc_inc_r_0 = _T_1025 & _T_1305; // @[dec_tlu_ctl.scala 2255:44] + wire _T_1309 = ~mcountinhibit[4]; // @[dec_tlu_ctl.scala 2255:24] reg [9:0] mhpme4; // @[Reg.scala 27:20] - wire _T_1300 = mhpme4 == 10'h1; // @[dec_tlu_ctl.scala 2256:34] - wire _T_1302 = mhpme4 == 10'h2; // @[dec_tlu_ctl.scala 2257:34] - wire _T_1304 = mhpme4 == 10'h3; // @[dec_tlu_ctl.scala 2258:34] - wire _T_1306 = mhpme4 == 10'h4; // @[dec_tlu_ctl.scala 2259:34] - wire _T_1310 = mhpme4 == 10'h5; // @[dec_tlu_ctl.scala 2260:34] - wire _T_1316 = mhpme4 == 10'h6; // @[dec_tlu_ctl.scala 2261:34] - wire _T_1321 = mhpme4 == 10'h7; // @[dec_tlu_ctl.scala 2262:34] - wire _T_1323 = mhpme4 == 10'h8; // @[dec_tlu_ctl.scala 2263:34] - wire _T_1325 = mhpme4 == 10'h1e; // @[dec_tlu_ctl.scala 2264:34] - wire _T_1327 = mhpme4 == 10'h9; // @[dec_tlu_ctl.scala 2265:34] - wire _T_1330 = mhpme4 == 10'ha; // @[dec_tlu_ctl.scala 2266:34] - wire _T_1333 = mhpme4 == 10'hb; // @[dec_tlu_ctl.scala 2267:34] - wire _T_1336 = mhpme4 == 10'hc; // @[dec_tlu_ctl.scala 2268:34] - wire _T_1339 = mhpme4 == 10'hd; // @[dec_tlu_ctl.scala 2269:34] - wire _T_1343 = mhpme4 == 10'he; // @[dec_tlu_ctl.scala 2270:34] - wire _T_1348 = mhpme4 == 10'hf; // @[dec_tlu_ctl.scala 2271:34] - wire _T_1351 = mhpme4 == 10'h10; // @[dec_tlu_ctl.scala 2272:34] - wire _T_1354 = mhpme4 == 10'h12; // @[dec_tlu_ctl.scala 2273:34] - wire _T_1357 = mhpme4 == 10'h11; // @[dec_tlu_ctl.scala 2274:34] - wire _T_1360 = mhpme4 == 10'h13; // @[dec_tlu_ctl.scala 2275:34] - wire _T_1363 = mhpme4 == 10'h14; // @[dec_tlu_ctl.scala 2276:34] - wire _T_1366 = mhpme4 == 10'h15; // @[dec_tlu_ctl.scala 2277:34] - wire _T_1369 = mhpme4 == 10'h16; // @[dec_tlu_ctl.scala 2278:34] - wire _T_1372 = mhpme4 == 10'h17; // @[dec_tlu_ctl.scala 2279:34] - wire _T_1375 = mhpme4 == 10'h18; // @[dec_tlu_ctl.scala 2280:34] - wire _T_1380 = mhpme4 == 10'h19; // @[dec_tlu_ctl.scala 2281:34] - wire _T_1383 = mhpme4 == 10'h1a; // @[dec_tlu_ctl.scala 2282:34] - wire _T_1386 = mhpme4 == 10'h1b; // @[dec_tlu_ctl.scala 2283:34] - wire _T_1389 = mhpme4 == 10'h1c; // @[dec_tlu_ctl.scala 2284:34] - wire _T_1393 = mhpme4 == 10'h1f; // @[dec_tlu_ctl.scala 2286:34] - wire _T_1395 = mhpme4 == 10'h20; // @[dec_tlu_ctl.scala 2287:34] - wire _T_1397 = mhpme4 == 10'h22; // @[dec_tlu_ctl.scala 2288:34] - wire _T_1399 = mhpme4 == 10'h23; // @[dec_tlu_ctl.scala 2289:34] - wire _T_1401 = mhpme4 == 10'h24; // @[dec_tlu_ctl.scala 2290:34] - wire _T_1403 = mhpme4 == 10'h25; // @[dec_tlu_ctl.scala 2291:34] - wire _T_1407 = mhpme4 == 10'h26; // @[dec_tlu_ctl.scala 2292:34] - wire _T_1411 = mhpme4 == 10'h27; // @[dec_tlu_ctl.scala 2293:34] - wire _T_1413 = mhpme4 == 10'h28; // @[dec_tlu_ctl.scala 2294:34] - wire _T_1415 = mhpme4 == 10'h29; // @[dec_tlu_ctl.scala 2295:34] - wire _T_1419 = mhpme4 == 10'h2a; // @[dec_tlu_ctl.scala 2296:34] - wire _T_1421 = mhpme4 == 10'h2b; // @[dec_tlu_ctl.scala 2297:34] - wire _T_1423 = mhpme4 == 10'h2c; // @[dec_tlu_ctl.scala 2298:34] - wire _T_1425 = mhpme4 == 10'h2d; // @[dec_tlu_ctl.scala 2299:34] - wire _T_1427 = mhpme4 == 10'h2e; // @[dec_tlu_ctl.scala 2300:34] - wire _T_1429 = mhpme4 == 10'h2f; // @[dec_tlu_ctl.scala 2301:34] - wire _T_1431 = mhpme4 == 10'h30; // @[dec_tlu_ctl.scala 2302:34] - wire _T_1433 = mhpme4 == 10'h31; // @[dec_tlu_ctl.scala 2303:34] - wire _T_1438 = mhpme4 == 10'h32; // @[dec_tlu_ctl.scala 2304:34] - wire _T_1448 = mhpme4 == 10'h36; // @[dec_tlu_ctl.scala 2305:34] - wire _T_1451 = mhpme4 == 10'h37; // @[dec_tlu_ctl.scala 2306:34] - wire _T_1454 = mhpme4 == 10'h38; // @[dec_tlu_ctl.scala 2307:34] - wire _T_1457 = mhpme4 == 10'h200; // @[dec_tlu_ctl.scala 2309:34] - wire _T_1459 = mhpme4 == 10'h201; // @[dec_tlu_ctl.scala 2310:34] - wire _T_1461 = mhpme4 == 10'h202; // @[dec_tlu_ctl.scala 2311:34] - wire _T_1463 = mhpme4 == 10'h203; // @[dec_tlu_ctl.scala 2312:34] - wire _T_1465 = mhpme4 == 10'h204; // @[dec_tlu_ctl.scala 2313:34] - wire _T_1468 = _T_1302 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] - wire _T_1469 = _T_1304 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] - wire _T_1470 = _T_1306 & _T_1025; // @[Mux.scala 27:72] - wire _T_1471 = _T_1310 & _T_1031; // @[Mux.scala 27:72] - wire _T_1472 = _T_1316 & _T_1036; // @[Mux.scala 27:72] - wire _T_1473 = _T_1321 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] - wire _T_1474 = _T_1323 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] - wire _T_1475 = _T_1325 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] - wire _T_1476 = _T_1327 & _T_1045; // @[Mux.scala 27:72] - wire _T_1477 = _T_1330 & _T_1048; // @[Mux.scala 27:72] - wire _T_1478 = _T_1333 & _T_1051; // @[Mux.scala 27:72] - wire _T_1479 = _T_1336 & _T_1054; // @[Mux.scala 27:72] - wire _T_1480 = _T_1339 & _T_1058; // @[Mux.scala 27:72] - wire _T_1481 = _T_1343 & _T_1063; // @[Mux.scala 27:72] - wire _T_1482 = _T_1348 & _T_1066; // @[Mux.scala 27:72] - wire _T_1483 = _T_1351 & _T_1069; // @[Mux.scala 27:72] - wire _T_1484 = _T_1354 & _T_1072; // @[Mux.scala 27:72] - wire _T_1485 = _T_1357 & _T_1075; // @[Mux.scala 27:72] - wire _T_1486 = _T_1360 & _T_1078; // @[Mux.scala 27:72] - wire _T_1487 = _T_1363 & _T_1081; // @[Mux.scala 27:72] - wire _T_1488 = _T_1366 & _T_1084; // @[Mux.scala 27:72] - wire _T_1489 = _T_1369 & _T_1087; // @[Mux.scala 27:72] - wire _T_1490 = _T_1372 & _T_1090; // @[Mux.scala 27:72] - wire _T_1491 = _T_1375 & _T_1095; // @[Mux.scala 27:72] - wire _T_1492 = _T_1380 & _T_1098; // @[Mux.scala 27:72] - wire _T_1493 = _T_1383 & _T_1101; // @[Mux.scala 27:72] - wire _T_1494 = _T_1386 & _T_1104; // @[Mux.scala 27:72] - wire _T_1495 = _T_1389 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] - wire _T_1497 = _T_1393 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] - wire _T_1498 = _T_1395 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] - wire _T_1499 = _T_1397 & io_lsu_store_stall_any; // @[Mux.scala 27:72] - wire _T_1500 = _T_1399 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] - wire _T_1501 = _T_1401 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] - wire _T_1502 = _T_1403 & _T_1122; // @[Mux.scala 27:72] - wire _T_1503 = _T_1407 & _T_1126; // @[Mux.scala 27:72] - wire _T_1504 = _T_1411 & io_take_ext_int; // @[Mux.scala 27:72] - wire _T_1505 = _T_1413 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] - wire _T_1506 = _T_1415 & _T_1134; // @[Mux.scala 27:72] - wire _T_1507 = _T_1419 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1508 = _T_1421 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1509 = _T_1423 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] - wire _T_1510 = _T_1425 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1511 = _T_1427 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1512 = _T_1429 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1513 = _T_1431 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1514 = _T_1433 & _T_1153; // @[Mux.scala 27:72] - wire _T_1515 = _T_1438 & _T_1163; // @[Mux.scala 27:72] - wire _T_1516 = _T_1448 & _T_1166; // @[Mux.scala 27:72] - wire _T_1517 = _T_1451 & _T_1169; // @[Mux.scala 27:72] - wire _T_1518 = _T_1454 & _T_1172; // @[Mux.scala 27:72] - wire _T_1519 = _T_1457 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] - wire _T_1520 = _T_1459 & io_dma_pmu_any_read; // @[Mux.scala 27:72] - wire _T_1521 = _T_1461 & io_dma_pmu_any_write; // @[Mux.scala 27:72] - wire _T_1522 = _T_1463 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] - wire _T_1523 = _T_1465 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] - wire _T_1524 = _T_1300 | _T_1468; // @[Mux.scala 27:72] - wire _T_1525 = _T_1524 | _T_1469; // @[Mux.scala 27:72] - wire _T_1526 = _T_1525 | _T_1470; // @[Mux.scala 27:72] - wire _T_1527 = _T_1526 | _T_1471; // @[Mux.scala 27:72] - wire _T_1528 = _T_1527 | _T_1472; // @[Mux.scala 27:72] - wire _T_1529 = _T_1528 | _T_1473; // @[Mux.scala 27:72] - wire _T_1530 = _T_1529 | _T_1474; // @[Mux.scala 27:72] - wire _T_1531 = _T_1530 | _T_1475; // @[Mux.scala 27:72] - wire _T_1532 = _T_1531 | _T_1476; // @[Mux.scala 27:72] - wire _T_1533 = _T_1532 | _T_1477; // @[Mux.scala 27:72] - wire _T_1534 = _T_1533 | _T_1478; // @[Mux.scala 27:72] + wire _T_1310 = mhpme4 == 10'h1; // @[dec_tlu_ctl.scala 2256:34] + wire _T_1312 = mhpme4 == 10'h2; // @[dec_tlu_ctl.scala 2257:34] + wire _T_1314 = mhpme4 == 10'h3; // @[dec_tlu_ctl.scala 2258:34] + wire _T_1316 = mhpme4 == 10'h4; // @[dec_tlu_ctl.scala 2259:34] + wire _T_1320 = mhpme4 == 10'h5; // @[dec_tlu_ctl.scala 2260:34] + wire _T_1326 = mhpme4 == 10'h6; // @[dec_tlu_ctl.scala 2261:34] + wire _T_1331 = mhpme4 == 10'h7; // @[dec_tlu_ctl.scala 2262:34] + wire _T_1333 = mhpme4 == 10'h8; // @[dec_tlu_ctl.scala 2263:34] + wire _T_1335 = mhpme4 == 10'h1e; // @[dec_tlu_ctl.scala 2264:34] + wire _T_1337 = mhpme4 == 10'h9; // @[dec_tlu_ctl.scala 2265:34] + wire _T_1340 = mhpme4 == 10'ha; // @[dec_tlu_ctl.scala 2266:34] + wire _T_1343 = mhpme4 == 10'hb; // @[dec_tlu_ctl.scala 2267:34] + wire _T_1346 = mhpme4 == 10'hc; // @[dec_tlu_ctl.scala 2268:34] + wire _T_1349 = mhpme4 == 10'hd; // @[dec_tlu_ctl.scala 2269:34] + wire _T_1353 = mhpme4 == 10'he; // @[dec_tlu_ctl.scala 2270:34] + wire _T_1358 = mhpme4 == 10'hf; // @[dec_tlu_ctl.scala 2271:34] + wire _T_1361 = mhpme4 == 10'h10; // @[dec_tlu_ctl.scala 2272:34] + wire _T_1364 = mhpme4 == 10'h12; // @[dec_tlu_ctl.scala 2273:34] + wire _T_1367 = mhpme4 == 10'h11; // @[dec_tlu_ctl.scala 2274:34] + wire _T_1370 = mhpme4 == 10'h13; // @[dec_tlu_ctl.scala 2275:34] + wire _T_1373 = mhpme4 == 10'h14; // @[dec_tlu_ctl.scala 2276:34] + wire _T_1376 = mhpme4 == 10'h15; // @[dec_tlu_ctl.scala 2277:34] + wire _T_1379 = mhpme4 == 10'h16; // @[dec_tlu_ctl.scala 2278:34] + wire _T_1382 = mhpme4 == 10'h17; // @[dec_tlu_ctl.scala 2279:34] + wire _T_1385 = mhpme4 == 10'h18; // @[dec_tlu_ctl.scala 2280:34] + wire _T_1390 = mhpme4 == 10'h19; // @[dec_tlu_ctl.scala 2281:34] + wire _T_1393 = mhpme4 == 10'h1a; // @[dec_tlu_ctl.scala 2282:34] + wire _T_1396 = mhpme4 == 10'h1b; // @[dec_tlu_ctl.scala 2283:34] + wire _T_1399 = mhpme4 == 10'h1c; // @[dec_tlu_ctl.scala 2284:34] + wire _T_1403 = mhpme4 == 10'h1f; // @[dec_tlu_ctl.scala 2286:34] + wire _T_1405 = mhpme4 == 10'h20; // @[dec_tlu_ctl.scala 2287:34] + wire _T_1407 = mhpme4 == 10'h22; // @[dec_tlu_ctl.scala 2288:34] + wire _T_1409 = mhpme4 == 10'h23; // @[dec_tlu_ctl.scala 2289:34] + wire _T_1411 = mhpme4 == 10'h24; // @[dec_tlu_ctl.scala 2290:34] + wire _T_1413 = mhpme4 == 10'h25; // @[dec_tlu_ctl.scala 2291:34] + wire _T_1417 = mhpme4 == 10'h26; // @[dec_tlu_ctl.scala 2292:34] + wire _T_1421 = mhpme4 == 10'h27; // @[dec_tlu_ctl.scala 2293:34] + wire _T_1423 = mhpme4 == 10'h28; // @[dec_tlu_ctl.scala 2294:34] + wire _T_1425 = mhpme4 == 10'h29; // @[dec_tlu_ctl.scala 2295:34] + wire _T_1429 = mhpme4 == 10'h2a; // @[dec_tlu_ctl.scala 2296:34] + wire _T_1431 = mhpme4 == 10'h2b; // @[dec_tlu_ctl.scala 2297:34] + wire _T_1433 = mhpme4 == 10'h2c; // @[dec_tlu_ctl.scala 2298:34] + wire _T_1435 = mhpme4 == 10'h2d; // @[dec_tlu_ctl.scala 2299:34] + wire _T_1437 = mhpme4 == 10'h2e; // @[dec_tlu_ctl.scala 2300:34] + wire _T_1439 = mhpme4 == 10'h2f; // @[dec_tlu_ctl.scala 2301:34] + wire _T_1441 = mhpme4 == 10'h30; // @[dec_tlu_ctl.scala 2302:34] + wire _T_1443 = mhpme4 == 10'h31; // @[dec_tlu_ctl.scala 2303:34] + wire _T_1448 = mhpme4 == 10'h32; // @[dec_tlu_ctl.scala 2304:34] + wire _T_1458 = mhpme4 == 10'h36; // @[dec_tlu_ctl.scala 2305:34] + wire _T_1461 = mhpme4 == 10'h37; // @[dec_tlu_ctl.scala 2306:34] + wire _T_1464 = mhpme4 == 10'h38; // @[dec_tlu_ctl.scala 2307:34] + wire _T_1467 = mhpme4 == 10'h200; // @[dec_tlu_ctl.scala 2309:34] + wire _T_1469 = mhpme4 == 10'h201; // @[dec_tlu_ctl.scala 2310:34] + wire _T_1471 = mhpme4 == 10'h202; // @[dec_tlu_ctl.scala 2311:34] + wire _T_1473 = mhpme4 == 10'h203; // @[dec_tlu_ctl.scala 2312:34] + wire _T_1475 = mhpme4 == 10'h204; // @[dec_tlu_ctl.scala 2313:34] + wire _T_1478 = _T_1312 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_1479 = _T_1314 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_1480 = _T_1316 & _T_1035; // @[Mux.scala 27:72] + wire _T_1481 = _T_1320 & _T_1041; // @[Mux.scala 27:72] + wire _T_1482 = _T_1326 & _T_1046; // @[Mux.scala 27:72] + wire _T_1483 = _T_1331 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_1484 = _T_1333 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_1485 = _T_1335 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_1486 = _T_1337 & _T_1055; // @[Mux.scala 27:72] + wire _T_1487 = _T_1340 & _T_1058; // @[Mux.scala 27:72] + wire _T_1488 = _T_1343 & _T_1061; // @[Mux.scala 27:72] + wire _T_1489 = _T_1346 & _T_1064; // @[Mux.scala 27:72] + wire _T_1490 = _T_1349 & _T_1068; // @[Mux.scala 27:72] + wire _T_1491 = _T_1353 & _T_1073; // @[Mux.scala 27:72] + wire _T_1492 = _T_1358 & _T_1076; // @[Mux.scala 27:72] + wire _T_1493 = _T_1361 & _T_1079; // @[Mux.scala 27:72] + wire _T_1494 = _T_1364 & _T_1082; // @[Mux.scala 27:72] + wire _T_1495 = _T_1367 & _T_1085; // @[Mux.scala 27:72] + wire _T_1496 = _T_1370 & _T_1088; // @[Mux.scala 27:72] + wire _T_1497 = _T_1373 & _T_1091; // @[Mux.scala 27:72] + wire _T_1498 = _T_1376 & _T_1094; // @[Mux.scala 27:72] + wire _T_1499 = _T_1379 & _T_1097; // @[Mux.scala 27:72] + wire _T_1500 = _T_1382 & _T_1100; // @[Mux.scala 27:72] + wire _T_1501 = _T_1385 & _T_1105; // @[Mux.scala 27:72] + wire _T_1502 = _T_1390 & _T_1108; // @[Mux.scala 27:72] + wire _T_1503 = _T_1393 & _T_1111; // @[Mux.scala 27:72] + wire _T_1504 = _T_1396 & _T_1114; // @[Mux.scala 27:72] + wire _T_1505 = _T_1399 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_1507 = _T_1403 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_1508 = _T_1405 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_1509 = _T_1407 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_1510 = _T_1409 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_1511 = _T_1411 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_1512 = _T_1413 & _T_1132; // @[Mux.scala 27:72] + wire _T_1513 = _T_1417 & _T_1136; // @[Mux.scala 27:72] + wire _T_1514 = _T_1421 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_1515 = _T_1423 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_1516 = _T_1425 & _T_1144; // @[Mux.scala 27:72] + wire _T_1517 = _T_1429 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1518 = _T_1431 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1519 = _T_1433 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_1520 = _T_1435 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1521 = _T_1437 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1522 = _T_1439 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1523 = _T_1441 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1524 = _T_1443 & _T_1163; // @[Mux.scala 27:72] + wire _T_1525 = _T_1448 & _T_1173; // @[Mux.scala 27:72] + wire _T_1526 = _T_1458 & _T_1176; // @[Mux.scala 27:72] + wire _T_1527 = _T_1461 & _T_1179; // @[Mux.scala 27:72] + wire _T_1528 = _T_1464 & _T_1182; // @[Mux.scala 27:72] + wire _T_1529 = _T_1467 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_1530 = _T_1469 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_1531 = _T_1471 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_1532 = _T_1473 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_1533 = _T_1475 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_1534 = _T_1310 | _T_1478; // @[Mux.scala 27:72] wire _T_1535 = _T_1534 | _T_1479; // @[Mux.scala 27:72] wire _T_1536 = _T_1535 | _T_1480; // @[Mux.scala 27:72] wire _T_1537 = _T_1536 | _T_1481; // @[Mux.scala 27:72] @@ -51785,7 +51786,7 @@ module csr_tlu( wire _T_1549 = _T_1548 | _T_1493; // @[Mux.scala 27:72] wire _T_1550 = _T_1549 | _T_1494; // @[Mux.scala 27:72] wire _T_1551 = _T_1550 | _T_1495; // @[Mux.scala 27:72] - wire _T_1552 = _T_1551 | _T_1475; // @[Mux.scala 27:72] + wire _T_1552 = _T_1551 | _T_1496; // @[Mux.scala 27:72] wire _T_1553 = _T_1552 | _T_1497; // @[Mux.scala 27:72] wire _T_1554 = _T_1553 | _T_1498; // @[Mux.scala 27:72] wire _T_1555 = _T_1554 | _T_1499; // @[Mux.scala 27:72] @@ -51795,7 +51796,7 @@ module csr_tlu( wire _T_1559 = _T_1558 | _T_1503; // @[Mux.scala 27:72] wire _T_1560 = _T_1559 | _T_1504; // @[Mux.scala 27:72] wire _T_1561 = _T_1560 | _T_1505; // @[Mux.scala 27:72] - wire _T_1562 = _T_1561 | _T_1506; // @[Mux.scala 27:72] + wire _T_1562 = _T_1561 | _T_1485; // @[Mux.scala 27:72] wire _T_1563 = _T_1562 | _T_1507; // @[Mux.scala 27:72] wire _T_1564 = _T_1563 | _T_1508; // @[Mux.scala 27:72] wire _T_1565 = _T_1564 | _T_1509; // @[Mux.scala 27:72] @@ -51813,131 +51814,131 @@ module csr_tlu( wire _T_1577 = _T_1576 | _T_1521; // @[Mux.scala 27:72] wire _T_1578 = _T_1577 | _T_1522; // @[Mux.scala 27:72] wire _T_1579 = _T_1578 | _T_1523; // @[Mux.scala 27:72] - wire mhpmc_inc_r_1 = _T_1299 & _T_1579; // @[dec_tlu_ctl.scala 2255:44] - wire _T_1583 = ~mcountinhibit[5]; // @[dec_tlu_ctl.scala 2255:24] + wire _T_1580 = _T_1579 | _T_1524; // @[Mux.scala 27:72] + wire _T_1581 = _T_1580 | _T_1525; // @[Mux.scala 27:72] + wire _T_1582 = _T_1581 | _T_1526; // @[Mux.scala 27:72] + wire _T_1583 = _T_1582 | _T_1527; // @[Mux.scala 27:72] + wire _T_1584 = _T_1583 | _T_1528; // @[Mux.scala 27:72] + wire _T_1585 = _T_1584 | _T_1529; // @[Mux.scala 27:72] + wire _T_1586 = _T_1585 | _T_1530; // @[Mux.scala 27:72] + wire _T_1587 = _T_1586 | _T_1531; // @[Mux.scala 27:72] + wire _T_1588 = _T_1587 | _T_1532; // @[Mux.scala 27:72] + wire _T_1589 = _T_1588 | _T_1533; // @[Mux.scala 27:72] + wire mhpmc_inc_r_1 = _T_1309 & _T_1589; // @[dec_tlu_ctl.scala 2255:44] + wire _T_1593 = ~mcountinhibit[5]; // @[dec_tlu_ctl.scala 2255:24] reg [9:0] mhpme5; // @[Reg.scala 27:20] - wire _T_1584 = mhpme5 == 10'h1; // @[dec_tlu_ctl.scala 2256:34] - wire _T_1586 = mhpme5 == 10'h2; // @[dec_tlu_ctl.scala 2257:34] - wire _T_1588 = mhpme5 == 10'h3; // @[dec_tlu_ctl.scala 2258:34] - wire _T_1590 = mhpme5 == 10'h4; // @[dec_tlu_ctl.scala 2259:34] - wire _T_1594 = mhpme5 == 10'h5; // @[dec_tlu_ctl.scala 2260:34] - wire _T_1600 = mhpme5 == 10'h6; // @[dec_tlu_ctl.scala 2261:34] - wire _T_1605 = mhpme5 == 10'h7; // @[dec_tlu_ctl.scala 2262:34] - wire _T_1607 = mhpme5 == 10'h8; // @[dec_tlu_ctl.scala 2263:34] - wire _T_1609 = mhpme5 == 10'h1e; // @[dec_tlu_ctl.scala 2264:34] - wire _T_1611 = mhpme5 == 10'h9; // @[dec_tlu_ctl.scala 2265:34] - wire _T_1614 = mhpme5 == 10'ha; // @[dec_tlu_ctl.scala 2266:34] - wire _T_1617 = mhpme5 == 10'hb; // @[dec_tlu_ctl.scala 2267:34] - wire _T_1620 = mhpme5 == 10'hc; // @[dec_tlu_ctl.scala 2268:34] - wire _T_1623 = mhpme5 == 10'hd; // @[dec_tlu_ctl.scala 2269:34] - wire _T_1627 = mhpme5 == 10'he; // @[dec_tlu_ctl.scala 2270:34] - wire _T_1632 = mhpme5 == 10'hf; // @[dec_tlu_ctl.scala 2271:34] - wire _T_1635 = mhpme5 == 10'h10; // @[dec_tlu_ctl.scala 2272:34] - wire _T_1638 = mhpme5 == 10'h12; // @[dec_tlu_ctl.scala 2273:34] - wire _T_1641 = mhpme5 == 10'h11; // @[dec_tlu_ctl.scala 2274:34] - wire _T_1644 = mhpme5 == 10'h13; // @[dec_tlu_ctl.scala 2275:34] - wire _T_1647 = mhpme5 == 10'h14; // @[dec_tlu_ctl.scala 2276:34] - wire _T_1650 = mhpme5 == 10'h15; // @[dec_tlu_ctl.scala 2277:34] - wire _T_1653 = mhpme5 == 10'h16; // @[dec_tlu_ctl.scala 2278:34] - wire _T_1656 = mhpme5 == 10'h17; // @[dec_tlu_ctl.scala 2279:34] - wire _T_1659 = mhpme5 == 10'h18; // @[dec_tlu_ctl.scala 2280:34] - wire _T_1664 = mhpme5 == 10'h19; // @[dec_tlu_ctl.scala 2281:34] - wire _T_1667 = mhpme5 == 10'h1a; // @[dec_tlu_ctl.scala 2282:34] - wire _T_1670 = mhpme5 == 10'h1b; // @[dec_tlu_ctl.scala 2283:34] - wire _T_1673 = mhpme5 == 10'h1c; // @[dec_tlu_ctl.scala 2284:34] - wire _T_1677 = mhpme5 == 10'h1f; // @[dec_tlu_ctl.scala 2286:34] - wire _T_1679 = mhpme5 == 10'h20; // @[dec_tlu_ctl.scala 2287:34] - wire _T_1681 = mhpme5 == 10'h22; // @[dec_tlu_ctl.scala 2288:34] - wire _T_1683 = mhpme5 == 10'h23; // @[dec_tlu_ctl.scala 2289:34] - wire _T_1685 = mhpme5 == 10'h24; // @[dec_tlu_ctl.scala 2290:34] - wire _T_1687 = mhpme5 == 10'h25; // @[dec_tlu_ctl.scala 2291:34] - wire _T_1691 = mhpme5 == 10'h26; // @[dec_tlu_ctl.scala 2292:34] - wire _T_1695 = mhpme5 == 10'h27; // @[dec_tlu_ctl.scala 2293:34] - wire _T_1697 = mhpme5 == 10'h28; // @[dec_tlu_ctl.scala 2294:34] - wire _T_1699 = mhpme5 == 10'h29; // @[dec_tlu_ctl.scala 2295:34] - wire _T_1703 = mhpme5 == 10'h2a; // @[dec_tlu_ctl.scala 2296:34] - wire _T_1705 = mhpme5 == 10'h2b; // @[dec_tlu_ctl.scala 2297:34] - wire _T_1707 = mhpme5 == 10'h2c; // @[dec_tlu_ctl.scala 2298:34] - wire _T_1709 = mhpme5 == 10'h2d; // @[dec_tlu_ctl.scala 2299:34] - wire _T_1711 = mhpme5 == 10'h2e; // @[dec_tlu_ctl.scala 2300:34] - wire _T_1713 = mhpme5 == 10'h2f; // @[dec_tlu_ctl.scala 2301:34] - wire _T_1715 = mhpme5 == 10'h30; // @[dec_tlu_ctl.scala 2302:34] - wire _T_1717 = mhpme5 == 10'h31; // @[dec_tlu_ctl.scala 2303:34] - wire _T_1722 = mhpme5 == 10'h32; // @[dec_tlu_ctl.scala 2304:34] - wire _T_1732 = mhpme5 == 10'h36; // @[dec_tlu_ctl.scala 2305:34] - wire _T_1735 = mhpme5 == 10'h37; // @[dec_tlu_ctl.scala 2306:34] - wire _T_1738 = mhpme5 == 10'h38; // @[dec_tlu_ctl.scala 2307:34] - wire _T_1741 = mhpme5 == 10'h200; // @[dec_tlu_ctl.scala 2309:34] - wire _T_1743 = mhpme5 == 10'h201; // @[dec_tlu_ctl.scala 2310:34] - wire _T_1745 = mhpme5 == 10'h202; // @[dec_tlu_ctl.scala 2311:34] - wire _T_1747 = mhpme5 == 10'h203; // @[dec_tlu_ctl.scala 2312:34] - wire _T_1749 = mhpme5 == 10'h204; // @[dec_tlu_ctl.scala 2313:34] - wire _T_1752 = _T_1586 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] - wire _T_1753 = _T_1588 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] - wire _T_1754 = _T_1590 & _T_1025; // @[Mux.scala 27:72] - wire _T_1755 = _T_1594 & _T_1031; // @[Mux.scala 27:72] - wire _T_1756 = _T_1600 & _T_1036; // @[Mux.scala 27:72] - wire _T_1757 = _T_1605 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] - wire _T_1758 = _T_1607 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] - wire _T_1759 = _T_1609 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] - wire _T_1760 = _T_1611 & _T_1045; // @[Mux.scala 27:72] - wire _T_1761 = _T_1614 & _T_1048; // @[Mux.scala 27:72] - wire _T_1762 = _T_1617 & _T_1051; // @[Mux.scala 27:72] - wire _T_1763 = _T_1620 & _T_1054; // @[Mux.scala 27:72] - wire _T_1764 = _T_1623 & _T_1058; // @[Mux.scala 27:72] - wire _T_1765 = _T_1627 & _T_1063; // @[Mux.scala 27:72] - wire _T_1766 = _T_1632 & _T_1066; // @[Mux.scala 27:72] - wire _T_1767 = _T_1635 & _T_1069; // @[Mux.scala 27:72] - wire _T_1768 = _T_1638 & _T_1072; // @[Mux.scala 27:72] - wire _T_1769 = _T_1641 & _T_1075; // @[Mux.scala 27:72] - wire _T_1770 = _T_1644 & _T_1078; // @[Mux.scala 27:72] - wire _T_1771 = _T_1647 & _T_1081; // @[Mux.scala 27:72] - wire _T_1772 = _T_1650 & _T_1084; // @[Mux.scala 27:72] - wire _T_1773 = _T_1653 & _T_1087; // @[Mux.scala 27:72] - wire _T_1774 = _T_1656 & _T_1090; // @[Mux.scala 27:72] - wire _T_1775 = _T_1659 & _T_1095; // @[Mux.scala 27:72] - wire _T_1776 = _T_1664 & _T_1098; // @[Mux.scala 27:72] - wire _T_1777 = _T_1667 & _T_1101; // @[Mux.scala 27:72] - wire _T_1778 = _T_1670 & _T_1104; // @[Mux.scala 27:72] - wire _T_1779 = _T_1673 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] - wire _T_1781 = _T_1677 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] - wire _T_1782 = _T_1679 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] - wire _T_1783 = _T_1681 & io_lsu_store_stall_any; // @[Mux.scala 27:72] - wire _T_1784 = _T_1683 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] - wire _T_1785 = _T_1685 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] - wire _T_1786 = _T_1687 & _T_1122; // @[Mux.scala 27:72] - wire _T_1787 = _T_1691 & _T_1126; // @[Mux.scala 27:72] - wire _T_1788 = _T_1695 & io_take_ext_int; // @[Mux.scala 27:72] - wire _T_1789 = _T_1697 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] - wire _T_1790 = _T_1699 & _T_1134; // @[Mux.scala 27:72] - wire _T_1791 = _T_1703 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1792 = _T_1705 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1793 = _T_1707 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] - wire _T_1794 = _T_1709 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1795 = _T_1711 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1796 = _T_1713 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1797 = _T_1715 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1798 = _T_1717 & _T_1153; // @[Mux.scala 27:72] - wire _T_1799 = _T_1722 & _T_1163; // @[Mux.scala 27:72] - wire _T_1800 = _T_1732 & _T_1166; // @[Mux.scala 27:72] - wire _T_1801 = _T_1735 & _T_1169; // @[Mux.scala 27:72] - wire _T_1802 = _T_1738 & _T_1172; // @[Mux.scala 27:72] - wire _T_1803 = _T_1741 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] - wire _T_1804 = _T_1743 & io_dma_pmu_any_read; // @[Mux.scala 27:72] - wire _T_1805 = _T_1745 & io_dma_pmu_any_write; // @[Mux.scala 27:72] - wire _T_1806 = _T_1747 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] - wire _T_1807 = _T_1749 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] - wire _T_1808 = _T_1584 | _T_1752; // @[Mux.scala 27:72] - wire _T_1809 = _T_1808 | _T_1753; // @[Mux.scala 27:72] - wire _T_1810 = _T_1809 | _T_1754; // @[Mux.scala 27:72] - wire _T_1811 = _T_1810 | _T_1755; // @[Mux.scala 27:72] - wire _T_1812 = _T_1811 | _T_1756; // @[Mux.scala 27:72] - wire _T_1813 = _T_1812 | _T_1757; // @[Mux.scala 27:72] - wire _T_1814 = _T_1813 | _T_1758; // @[Mux.scala 27:72] - wire _T_1815 = _T_1814 | _T_1759; // @[Mux.scala 27:72] - wire _T_1816 = _T_1815 | _T_1760; // @[Mux.scala 27:72] - wire _T_1817 = _T_1816 | _T_1761; // @[Mux.scala 27:72] - wire _T_1818 = _T_1817 | _T_1762; // @[Mux.scala 27:72] + wire _T_1594 = mhpme5 == 10'h1; // @[dec_tlu_ctl.scala 2256:34] + wire _T_1596 = mhpme5 == 10'h2; // @[dec_tlu_ctl.scala 2257:34] + wire _T_1598 = mhpme5 == 10'h3; // @[dec_tlu_ctl.scala 2258:34] + wire _T_1600 = mhpme5 == 10'h4; // @[dec_tlu_ctl.scala 2259:34] + wire _T_1604 = mhpme5 == 10'h5; // @[dec_tlu_ctl.scala 2260:34] + wire _T_1610 = mhpme5 == 10'h6; // @[dec_tlu_ctl.scala 2261:34] + wire _T_1615 = mhpme5 == 10'h7; // @[dec_tlu_ctl.scala 2262:34] + wire _T_1617 = mhpme5 == 10'h8; // @[dec_tlu_ctl.scala 2263:34] + wire _T_1619 = mhpme5 == 10'h1e; // @[dec_tlu_ctl.scala 2264:34] + wire _T_1621 = mhpme5 == 10'h9; // @[dec_tlu_ctl.scala 2265:34] + wire _T_1624 = mhpme5 == 10'ha; // @[dec_tlu_ctl.scala 2266:34] + wire _T_1627 = mhpme5 == 10'hb; // @[dec_tlu_ctl.scala 2267:34] + wire _T_1630 = mhpme5 == 10'hc; // @[dec_tlu_ctl.scala 2268:34] + wire _T_1633 = mhpme5 == 10'hd; // @[dec_tlu_ctl.scala 2269:34] + wire _T_1637 = mhpme5 == 10'he; // @[dec_tlu_ctl.scala 2270:34] + wire _T_1642 = mhpme5 == 10'hf; // @[dec_tlu_ctl.scala 2271:34] + wire _T_1645 = mhpme5 == 10'h10; // @[dec_tlu_ctl.scala 2272:34] + wire _T_1648 = mhpme5 == 10'h12; // @[dec_tlu_ctl.scala 2273:34] + wire _T_1651 = mhpme5 == 10'h11; // @[dec_tlu_ctl.scala 2274:34] + wire _T_1654 = mhpme5 == 10'h13; // @[dec_tlu_ctl.scala 2275:34] + wire _T_1657 = mhpme5 == 10'h14; // @[dec_tlu_ctl.scala 2276:34] + wire _T_1660 = mhpme5 == 10'h15; // @[dec_tlu_ctl.scala 2277:34] + wire _T_1663 = mhpme5 == 10'h16; // @[dec_tlu_ctl.scala 2278:34] + wire _T_1666 = mhpme5 == 10'h17; // @[dec_tlu_ctl.scala 2279:34] + wire _T_1669 = mhpme5 == 10'h18; // @[dec_tlu_ctl.scala 2280:34] + wire _T_1674 = mhpme5 == 10'h19; // @[dec_tlu_ctl.scala 2281:34] + wire _T_1677 = mhpme5 == 10'h1a; // @[dec_tlu_ctl.scala 2282:34] + wire _T_1680 = mhpme5 == 10'h1b; // @[dec_tlu_ctl.scala 2283:34] + wire _T_1683 = mhpme5 == 10'h1c; // @[dec_tlu_ctl.scala 2284:34] + wire _T_1687 = mhpme5 == 10'h1f; // @[dec_tlu_ctl.scala 2286:34] + wire _T_1689 = mhpme5 == 10'h20; // @[dec_tlu_ctl.scala 2287:34] + wire _T_1691 = mhpme5 == 10'h22; // @[dec_tlu_ctl.scala 2288:34] + wire _T_1693 = mhpme5 == 10'h23; // @[dec_tlu_ctl.scala 2289:34] + wire _T_1695 = mhpme5 == 10'h24; // @[dec_tlu_ctl.scala 2290:34] + wire _T_1697 = mhpme5 == 10'h25; // @[dec_tlu_ctl.scala 2291:34] + wire _T_1701 = mhpme5 == 10'h26; // @[dec_tlu_ctl.scala 2292:34] + wire _T_1705 = mhpme5 == 10'h27; // @[dec_tlu_ctl.scala 2293:34] + wire _T_1707 = mhpme5 == 10'h28; // @[dec_tlu_ctl.scala 2294:34] + wire _T_1709 = mhpme5 == 10'h29; // @[dec_tlu_ctl.scala 2295:34] + wire _T_1713 = mhpme5 == 10'h2a; // @[dec_tlu_ctl.scala 2296:34] + wire _T_1715 = mhpme5 == 10'h2b; // @[dec_tlu_ctl.scala 2297:34] + wire _T_1717 = mhpme5 == 10'h2c; // @[dec_tlu_ctl.scala 2298:34] + wire _T_1719 = mhpme5 == 10'h2d; // @[dec_tlu_ctl.scala 2299:34] + wire _T_1721 = mhpme5 == 10'h2e; // @[dec_tlu_ctl.scala 2300:34] + wire _T_1723 = mhpme5 == 10'h2f; // @[dec_tlu_ctl.scala 2301:34] + wire _T_1725 = mhpme5 == 10'h30; // @[dec_tlu_ctl.scala 2302:34] + wire _T_1727 = mhpme5 == 10'h31; // @[dec_tlu_ctl.scala 2303:34] + wire _T_1732 = mhpme5 == 10'h32; // @[dec_tlu_ctl.scala 2304:34] + wire _T_1742 = mhpme5 == 10'h36; // @[dec_tlu_ctl.scala 2305:34] + wire _T_1745 = mhpme5 == 10'h37; // @[dec_tlu_ctl.scala 2306:34] + wire _T_1748 = mhpme5 == 10'h38; // @[dec_tlu_ctl.scala 2307:34] + wire _T_1751 = mhpme5 == 10'h200; // @[dec_tlu_ctl.scala 2309:34] + wire _T_1753 = mhpme5 == 10'h201; // @[dec_tlu_ctl.scala 2310:34] + wire _T_1755 = mhpme5 == 10'h202; // @[dec_tlu_ctl.scala 2311:34] + wire _T_1757 = mhpme5 == 10'h203; // @[dec_tlu_ctl.scala 2312:34] + wire _T_1759 = mhpme5 == 10'h204; // @[dec_tlu_ctl.scala 2313:34] + wire _T_1762 = _T_1596 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_1763 = _T_1598 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_1764 = _T_1600 & _T_1035; // @[Mux.scala 27:72] + wire _T_1765 = _T_1604 & _T_1041; // @[Mux.scala 27:72] + wire _T_1766 = _T_1610 & _T_1046; // @[Mux.scala 27:72] + wire _T_1767 = _T_1615 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_1768 = _T_1617 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_1769 = _T_1619 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_1770 = _T_1621 & _T_1055; // @[Mux.scala 27:72] + wire _T_1771 = _T_1624 & _T_1058; // @[Mux.scala 27:72] + wire _T_1772 = _T_1627 & _T_1061; // @[Mux.scala 27:72] + wire _T_1773 = _T_1630 & _T_1064; // @[Mux.scala 27:72] + wire _T_1774 = _T_1633 & _T_1068; // @[Mux.scala 27:72] + wire _T_1775 = _T_1637 & _T_1073; // @[Mux.scala 27:72] + wire _T_1776 = _T_1642 & _T_1076; // @[Mux.scala 27:72] + wire _T_1777 = _T_1645 & _T_1079; // @[Mux.scala 27:72] + wire _T_1778 = _T_1648 & _T_1082; // @[Mux.scala 27:72] + wire _T_1779 = _T_1651 & _T_1085; // @[Mux.scala 27:72] + wire _T_1780 = _T_1654 & _T_1088; // @[Mux.scala 27:72] + wire _T_1781 = _T_1657 & _T_1091; // @[Mux.scala 27:72] + wire _T_1782 = _T_1660 & _T_1094; // @[Mux.scala 27:72] + wire _T_1783 = _T_1663 & _T_1097; // @[Mux.scala 27:72] + wire _T_1784 = _T_1666 & _T_1100; // @[Mux.scala 27:72] + wire _T_1785 = _T_1669 & _T_1105; // @[Mux.scala 27:72] + wire _T_1786 = _T_1674 & _T_1108; // @[Mux.scala 27:72] + wire _T_1787 = _T_1677 & _T_1111; // @[Mux.scala 27:72] + wire _T_1788 = _T_1680 & _T_1114; // @[Mux.scala 27:72] + wire _T_1789 = _T_1683 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_1791 = _T_1687 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_1792 = _T_1689 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_1793 = _T_1691 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_1794 = _T_1693 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_1795 = _T_1695 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_1796 = _T_1697 & _T_1132; // @[Mux.scala 27:72] + wire _T_1797 = _T_1701 & _T_1136; // @[Mux.scala 27:72] + wire _T_1798 = _T_1705 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_1799 = _T_1707 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_1800 = _T_1709 & _T_1144; // @[Mux.scala 27:72] + wire _T_1801 = _T_1713 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1802 = _T_1715 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1803 = _T_1717 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_1804 = _T_1719 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1805 = _T_1721 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1806 = _T_1723 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1807 = _T_1725 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1808 = _T_1727 & _T_1163; // @[Mux.scala 27:72] + wire _T_1809 = _T_1732 & _T_1173; // @[Mux.scala 27:72] + wire _T_1810 = _T_1742 & _T_1176; // @[Mux.scala 27:72] + wire _T_1811 = _T_1745 & _T_1179; // @[Mux.scala 27:72] + wire _T_1812 = _T_1748 & _T_1182; // @[Mux.scala 27:72] + wire _T_1813 = _T_1751 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_1814 = _T_1753 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_1815 = _T_1755 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_1816 = _T_1757 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_1817 = _T_1759 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_1818 = _T_1594 | _T_1762; // @[Mux.scala 27:72] wire _T_1819 = _T_1818 | _T_1763; // @[Mux.scala 27:72] wire _T_1820 = _T_1819 | _T_1764; // @[Mux.scala 27:72] wire _T_1821 = _T_1820 | _T_1765; // @[Mux.scala 27:72] @@ -51955,7 +51956,7 @@ module csr_tlu( wire _T_1833 = _T_1832 | _T_1777; // @[Mux.scala 27:72] wire _T_1834 = _T_1833 | _T_1778; // @[Mux.scala 27:72] wire _T_1835 = _T_1834 | _T_1779; // @[Mux.scala 27:72] - wire _T_1836 = _T_1835 | _T_1759; // @[Mux.scala 27:72] + wire _T_1836 = _T_1835 | _T_1780; // @[Mux.scala 27:72] wire _T_1837 = _T_1836 | _T_1781; // @[Mux.scala 27:72] wire _T_1838 = _T_1837 | _T_1782; // @[Mux.scala 27:72] wire _T_1839 = _T_1838 | _T_1783; // @[Mux.scala 27:72] @@ -51965,7 +51966,7 @@ module csr_tlu( wire _T_1843 = _T_1842 | _T_1787; // @[Mux.scala 27:72] wire _T_1844 = _T_1843 | _T_1788; // @[Mux.scala 27:72] wire _T_1845 = _T_1844 | _T_1789; // @[Mux.scala 27:72] - wire _T_1846 = _T_1845 | _T_1790; // @[Mux.scala 27:72] + wire _T_1846 = _T_1845 | _T_1769; // @[Mux.scala 27:72] wire _T_1847 = _T_1846 | _T_1791; // @[Mux.scala 27:72] wire _T_1848 = _T_1847 | _T_1792; // @[Mux.scala 27:72] wire _T_1849 = _T_1848 | _T_1793; // @[Mux.scala 27:72] @@ -51983,131 +51984,131 @@ module csr_tlu( wire _T_1861 = _T_1860 | _T_1805; // @[Mux.scala 27:72] wire _T_1862 = _T_1861 | _T_1806; // @[Mux.scala 27:72] wire _T_1863 = _T_1862 | _T_1807; // @[Mux.scala 27:72] - wire mhpmc_inc_r_2 = _T_1583 & _T_1863; // @[dec_tlu_ctl.scala 2255:44] - wire _T_1867 = ~mcountinhibit[6]; // @[dec_tlu_ctl.scala 2255:24] + wire _T_1864 = _T_1863 | _T_1808; // @[Mux.scala 27:72] + wire _T_1865 = _T_1864 | _T_1809; // @[Mux.scala 27:72] + wire _T_1866 = _T_1865 | _T_1810; // @[Mux.scala 27:72] + wire _T_1867 = _T_1866 | _T_1811; // @[Mux.scala 27:72] + wire _T_1868 = _T_1867 | _T_1812; // @[Mux.scala 27:72] + wire _T_1869 = _T_1868 | _T_1813; // @[Mux.scala 27:72] + wire _T_1870 = _T_1869 | _T_1814; // @[Mux.scala 27:72] + wire _T_1871 = _T_1870 | _T_1815; // @[Mux.scala 27:72] + wire _T_1872 = _T_1871 | _T_1816; // @[Mux.scala 27:72] + wire _T_1873 = _T_1872 | _T_1817; // @[Mux.scala 27:72] + wire mhpmc_inc_r_2 = _T_1593 & _T_1873; // @[dec_tlu_ctl.scala 2255:44] + wire _T_1877 = ~mcountinhibit[6]; // @[dec_tlu_ctl.scala 2255:24] reg [9:0] mhpme6; // @[Reg.scala 27:20] - wire _T_1868 = mhpme6 == 10'h1; // @[dec_tlu_ctl.scala 2256:34] - wire _T_1870 = mhpme6 == 10'h2; // @[dec_tlu_ctl.scala 2257:34] - wire _T_1872 = mhpme6 == 10'h3; // @[dec_tlu_ctl.scala 2258:34] - wire _T_1874 = mhpme6 == 10'h4; // @[dec_tlu_ctl.scala 2259:34] - wire _T_1878 = mhpme6 == 10'h5; // @[dec_tlu_ctl.scala 2260:34] - wire _T_1884 = mhpme6 == 10'h6; // @[dec_tlu_ctl.scala 2261:34] - wire _T_1889 = mhpme6 == 10'h7; // @[dec_tlu_ctl.scala 2262:34] - wire _T_1891 = mhpme6 == 10'h8; // @[dec_tlu_ctl.scala 2263:34] - wire _T_1893 = mhpme6 == 10'h1e; // @[dec_tlu_ctl.scala 2264:34] - wire _T_1895 = mhpme6 == 10'h9; // @[dec_tlu_ctl.scala 2265:34] - wire _T_1898 = mhpme6 == 10'ha; // @[dec_tlu_ctl.scala 2266:34] - wire _T_1901 = mhpme6 == 10'hb; // @[dec_tlu_ctl.scala 2267:34] - wire _T_1904 = mhpme6 == 10'hc; // @[dec_tlu_ctl.scala 2268:34] - wire _T_1907 = mhpme6 == 10'hd; // @[dec_tlu_ctl.scala 2269:34] - wire _T_1911 = mhpme6 == 10'he; // @[dec_tlu_ctl.scala 2270:34] - wire _T_1916 = mhpme6 == 10'hf; // @[dec_tlu_ctl.scala 2271:34] - wire _T_1919 = mhpme6 == 10'h10; // @[dec_tlu_ctl.scala 2272:34] - wire _T_1922 = mhpme6 == 10'h12; // @[dec_tlu_ctl.scala 2273:34] - wire _T_1925 = mhpme6 == 10'h11; // @[dec_tlu_ctl.scala 2274:34] - wire _T_1928 = mhpme6 == 10'h13; // @[dec_tlu_ctl.scala 2275:34] - wire _T_1931 = mhpme6 == 10'h14; // @[dec_tlu_ctl.scala 2276:34] - wire _T_1934 = mhpme6 == 10'h15; // @[dec_tlu_ctl.scala 2277:34] - wire _T_1937 = mhpme6 == 10'h16; // @[dec_tlu_ctl.scala 2278:34] - wire _T_1940 = mhpme6 == 10'h17; // @[dec_tlu_ctl.scala 2279:34] - wire _T_1943 = mhpme6 == 10'h18; // @[dec_tlu_ctl.scala 2280:34] - wire _T_1948 = mhpme6 == 10'h19; // @[dec_tlu_ctl.scala 2281:34] - wire _T_1951 = mhpme6 == 10'h1a; // @[dec_tlu_ctl.scala 2282:34] - wire _T_1954 = mhpme6 == 10'h1b; // @[dec_tlu_ctl.scala 2283:34] - wire _T_1957 = mhpme6 == 10'h1c; // @[dec_tlu_ctl.scala 2284:34] - wire _T_1961 = mhpme6 == 10'h1f; // @[dec_tlu_ctl.scala 2286:34] - wire _T_1963 = mhpme6 == 10'h20; // @[dec_tlu_ctl.scala 2287:34] - wire _T_1965 = mhpme6 == 10'h22; // @[dec_tlu_ctl.scala 2288:34] - wire _T_1967 = mhpme6 == 10'h23; // @[dec_tlu_ctl.scala 2289:34] - wire _T_1969 = mhpme6 == 10'h24; // @[dec_tlu_ctl.scala 2290:34] - wire _T_1971 = mhpme6 == 10'h25; // @[dec_tlu_ctl.scala 2291:34] - wire _T_1975 = mhpme6 == 10'h26; // @[dec_tlu_ctl.scala 2292:34] - wire _T_1979 = mhpme6 == 10'h27; // @[dec_tlu_ctl.scala 2293:34] - wire _T_1981 = mhpme6 == 10'h28; // @[dec_tlu_ctl.scala 2294:34] - wire _T_1983 = mhpme6 == 10'h29; // @[dec_tlu_ctl.scala 2295:34] - wire _T_1987 = mhpme6 == 10'h2a; // @[dec_tlu_ctl.scala 2296:34] - wire _T_1989 = mhpme6 == 10'h2b; // @[dec_tlu_ctl.scala 2297:34] - wire _T_1991 = mhpme6 == 10'h2c; // @[dec_tlu_ctl.scala 2298:34] - wire _T_1993 = mhpme6 == 10'h2d; // @[dec_tlu_ctl.scala 2299:34] - wire _T_1995 = mhpme6 == 10'h2e; // @[dec_tlu_ctl.scala 2300:34] - wire _T_1997 = mhpme6 == 10'h2f; // @[dec_tlu_ctl.scala 2301:34] - wire _T_1999 = mhpme6 == 10'h30; // @[dec_tlu_ctl.scala 2302:34] - wire _T_2001 = mhpme6 == 10'h31; // @[dec_tlu_ctl.scala 2303:34] - wire _T_2006 = mhpme6 == 10'h32; // @[dec_tlu_ctl.scala 2304:34] - wire _T_2016 = mhpme6 == 10'h36; // @[dec_tlu_ctl.scala 2305:34] - wire _T_2019 = mhpme6 == 10'h37; // @[dec_tlu_ctl.scala 2306:34] - wire _T_2022 = mhpme6 == 10'h38; // @[dec_tlu_ctl.scala 2307:34] - wire _T_2025 = mhpme6 == 10'h200; // @[dec_tlu_ctl.scala 2309:34] - wire _T_2027 = mhpme6 == 10'h201; // @[dec_tlu_ctl.scala 2310:34] - wire _T_2029 = mhpme6 == 10'h202; // @[dec_tlu_ctl.scala 2311:34] - wire _T_2031 = mhpme6 == 10'h203; // @[dec_tlu_ctl.scala 2312:34] - wire _T_2033 = mhpme6 == 10'h204; // @[dec_tlu_ctl.scala 2313:34] - wire _T_2036 = _T_1870 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] - wire _T_2037 = _T_1872 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] - wire _T_2038 = _T_1874 & _T_1025; // @[Mux.scala 27:72] - wire _T_2039 = _T_1878 & _T_1031; // @[Mux.scala 27:72] - wire _T_2040 = _T_1884 & _T_1036; // @[Mux.scala 27:72] - wire _T_2041 = _T_1889 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] - wire _T_2042 = _T_1891 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] - wire _T_2043 = _T_1893 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] - wire _T_2044 = _T_1895 & _T_1045; // @[Mux.scala 27:72] - wire _T_2045 = _T_1898 & _T_1048; // @[Mux.scala 27:72] - wire _T_2046 = _T_1901 & _T_1051; // @[Mux.scala 27:72] - wire _T_2047 = _T_1904 & _T_1054; // @[Mux.scala 27:72] - wire _T_2048 = _T_1907 & _T_1058; // @[Mux.scala 27:72] - wire _T_2049 = _T_1911 & _T_1063; // @[Mux.scala 27:72] - wire _T_2050 = _T_1916 & _T_1066; // @[Mux.scala 27:72] - wire _T_2051 = _T_1919 & _T_1069; // @[Mux.scala 27:72] - wire _T_2052 = _T_1922 & _T_1072; // @[Mux.scala 27:72] - wire _T_2053 = _T_1925 & _T_1075; // @[Mux.scala 27:72] - wire _T_2054 = _T_1928 & _T_1078; // @[Mux.scala 27:72] - wire _T_2055 = _T_1931 & _T_1081; // @[Mux.scala 27:72] - wire _T_2056 = _T_1934 & _T_1084; // @[Mux.scala 27:72] - wire _T_2057 = _T_1937 & _T_1087; // @[Mux.scala 27:72] - wire _T_2058 = _T_1940 & _T_1090; // @[Mux.scala 27:72] - wire _T_2059 = _T_1943 & _T_1095; // @[Mux.scala 27:72] - wire _T_2060 = _T_1948 & _T_1098; // @[Mux.scala 27:72] - wire _T_2061 = _T_1951 & _T_1101; // @[Mux.scala 27:72] - wire _T_2062 = _T_1954 & _T_1104; // @[Mux.scala 27:72] - wire _T_2063 = _T_1957 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] - wire _T_2065 = _T_1961 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] - wire _T_2066 = _T_1963 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] - wire _T_2067 = _T_1965 & io_lsu_store_stall_any; // @[Mux.scala 27:72] - wire _T_2068 = _T_1967 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] - wire _T_2069 = _T_1969 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] - wire _T_2070 = _T_1971 & _T_1122; // @[Mux.scala 27:72] - wire _T_2071 = _T_1975 & _T_1126; // @[Mux.scala 27:72] - wire _T_2072 = _T_1979 & io_take_ext_int; // @[Mux.scala 27:72] - wire _T_2073 = _T_1981 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] - wire _T_2074 = _T_1983 & _T_1134; // @[Mux.scala 27:72] - wire _T_2075 = _T_1987 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_2076 = _T_1989 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_2077 = _T_1991 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] - wire _T_2078 = _T_1993 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_2079 = _T_1995 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_2080 = _T_1997 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_2081 = _T_1999 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_2082 = _T_2001 & _T_1153; // @[Mux.scala 27:72] - wire _T_2083 = _T_2006 & _T_1163; // @[Mux.scala 27:72] - wire _T_2084 = _T_2016 & _T_1166; // @[Mux.scala 27:72] - wire _T_2085 = _T_2019 & _T_1169; // @[Mux.scala 27:72] - wire _T_2086 = _T_2022 & _T_1172; // @[Mux.scala 27:72] - wire _T_2087 = _T_2025 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] - wire _T_2088 = _T_2027 & io_dma_pmu_any_read; // @[Mux.scala 27:72] - wire _T_2089 = _T_2029 & io_dma_pmu_any_write; // @[Mux.scala 27:72] - wire _T_2090 = _T_2031 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] - wire _T_2091 = _T_2033 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] - wire _T_2092 = _T_1868 | _T_2036; // @[Mux.scala 27:72] - wire _T_2093 = _T_2092 | _T_2037; // @[Mux.scala 27:72] - wire _T_2094 = _T_2093 | _T_2038; // @[Mux.scala 27:72] - wire _T_2095 = _T_2094 | _T_2039; // @[Mux.scala 27:72] - wire _T_2096 = _T_2095 | _T_2040; // @[Mux.scala 27:72] - wire _T_2097 = _T_2096 | _T_2041; // @[Mux.scala 27:72] - wire _T_2098 = _T_2097 | _T_2042; // @[Mux.scala 27:72] - wire _T_2099 = _T_2098 | _T_2043; // @[Mux.scala 27:72] - wire _T_2100 = _T_2099 | _T_2044; // @[Mux.scala 27:72] - wire _T_2101 = _T_2100 | _T_2045; // @[Mux.scala 27:72] - wire _T_2102 = _T_2101 | _T_2046; // @[Mux.scala 27:72] + wire _T_1878 = mhpme6 == 10'h1; // @[dec_tlu_ctl.scala 2256:34] + wire _T_1880 = mhpme6 == 10'h2; // @[dec_tlu_ctl.scala 2257:34] + wire _T_1882 = mhpme6 == 10'h3; // @[dec_tlu_ctl.scala 2258:34] + wire _T_1884 = mhpme6 == 10'h4; // @[dec_tlu_ctl.scala 2259:34] + wire _T_1888 = mhpme6 == 10'h5; // @[dec_tlu_ctl.scala 2260:34] + wire _T_1894 = mhpme6 == 10'h6; // @[dec_tlu_ctl.scala 2261:34] + wire _T_1899 = mhpme6 == 10'h7; // @[dec_tlu_ctl.scala 2262:34] + wire _T_1901 = mhpme6 == 10'h8; // @[dec_tlu_ctl.scala 2263:34] + wire _T_1903 = mhpme6 == 10'h1e; // @[dec_tlu_ctl.scala 2264:34] + wire _T_1905 = mhpme6 == 10'h9; // @[dec_tlu_ctl.scala 2265:34] + wire _T_1908 = mhpme6 == 10'ha; // @[dec_tlu_ctl.scala 2266:34] + wire _T_1911 = mhpme6 == 10'hb; // @[dec_tlu_ctl.scala 2267:34] + wire _T_1914 = mhpme6 == 10'hc; // @[dec_tlu_ctl.scala 2268:34] + wire _T_1917 = mhpme6 == 10'hd; // @[dec_tlu_ctl.scala 2269:34] + wire _T_1921 = mhpme6 == 10'he; // @[dec_tlu_ctl.scala 2270:34] + wire _T_1926 = mhpme6 == 10'hf; // @[dec_tlu_ctl.scala 2271:34] + wire _T_1929 = mhpme6 == 10'h10; // @[dec_tlu_ctl.scala 2272:34] + wire _T_1932 = mhpme6 == 10'h12; // @[dec_tlu_ctl.scala 2273:34] + wire _T_1935 = mhpme6 == 10'h11; // @[dec_tlu_ctl.scala 2274:34] + wire _T_1938 = mhpme6 == 10'h13; // @[dec_tlu_ctl.scala 2275:34] + wire _T_1941 = mhpme6 == 10'h14; // @[dec_tlu_ctl.scala 2276:34] + wire _T_1944 = mhpme6 == 10'h15; // @[dec_tlu_ctl.scala 2277:34] + wire _T_1947 = mhpme6 == 10'h16; // @[dec_tlu_ctl.scala 2278:34] + wire _T_1950 = mhpme6 == 10'h17; // @[dec_tlu_ctl.scala 2279:34] + wire _T_1953 = mhpme6 == 10'h18; // @[dec_tlu_ctl.scala 2280:34] + wire _T_1958 = mhpme6 == 10'h19; // @[dec_tlu_ctl.scala 2281:34] + wire _T_1961 = mhpme6 == 10'h1a; // @[dec_tlu_ctl.scala 2282:34] + wire _T_1964 = mhpme6 == 10'h1b; // @[dec_tlu_ctl.scala 2283:34] + wire _T_1967 = mhpme6 == 10'h1c; // @[dec_tlu_ctl.scala 2284:34] + wire _T_1971 = mhpme6 == 10'h1f; // @[dec_tlu_ctl.scala 2286:34] + wire _T_1973 = mhpme6 == 10'h20; // @[dec_tlu_ctl.scala 2287:34] + wire _T_1975 = mhpme6 == 10'h22; // @[dec_tlu_ctl.scala 2288:34] + wire _T_1977 = mhpme6 == 10'h23; // @[dec_tlu_ctl.scala 2289:34] + wire _T_1979 = mhpme6 == 10'h24; // @[dec_tlu_ctl.scala 2290:34] + wire _T_1981 = mhpme6 == 10'h25; // @[dec_tlu_ctl.scala 2291:34] + wire _T_1985 = mhpme6 == 10'h26; // @[dec_tlu_ctl.scala 2292:34] + wire _T_1989 = mhpme6 == 10'h27; // @[dec_tlu_ctl.scala 2293:34] + wire _T_1991 = mhpme6 == 10'h28; // @[dec_tlu_ctl.scala 2294:34] + wire _T_1993 = mhpme6 == 10'h29; // @[dec_tlu_ctl.scala 2295:34] + wire _T_1997 = mhpme6 == 10'h2a; // @[dec_tlu_ctl.scala 2296:34] + wire _T_1999 = mhpme6 == 10'h2b; // @[dec_tlu_ctl.scala 2297:34] + wire _T_2001 = mhpme6 == 10'h2c; // @[dec_tlu_ctl.scala 2298:34] + wire _T_2003 = mhpme6 == 10'h2d; // @[dec_tlu_ctl.scala 2299:34] + wire _T_2005 = mhpme6 == 10'h2e; // @[dec_tlu_ctl.scala 2300:34] + wire _T_2007 = mhpme6 == 10'h2f; // @[dec_tlu_ctl.scala 2301:34] + wire _T_2009 = mhpme6 == 10'h30; // @[dec_tlu_ctl.scala 2302:34] + wire _T_2011 = mhpme6 == 10'h31; // @[dec_tlu_ctl.scala 2303:34] + wire _T_2016 = mhpme6 == 10'h32; // @[dec_tlu_ctl.scala 2304:34] + wire _T_2026 = mhpme6 == 10'h36; // @[dec_tlu_ctl.scala 2305:34] + wire _T_2029 = mhpme6 == 10'h37; // @[dec_tlu_ctl.scala 2306:34] + wire _T_2032 = mhpme6 == 10'h38; // @[dec_tlu_ctl.scala 2307:34] + wire _T_2035 = mhpme6 == 10'h200; // @[dec_tlu_ctl.scala 2309:34] + wire _T_2037 = mhpme6 == 10'h201; // @[dec_tlu_ctl.scala 2310:34] + wire _T_2039 = mhpme6 == 10'h202; // @[dec_tlu_ctl.scala 2311:34] + wire _T_2041 = mhpme6 == 10'h203; // @[dec_tlu_ctl.scala 2312:34] + wire _T_2043 = mhpme6 == 10'h204; // @[dec_tlu_ctl.scala 2313:34] + wire _T_2046 = _T_1880 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_2047 = _T_1882 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_2048 = _T_1884 & _T_1035; // @[Mux.scala 27:72] + wire _T_2049 = _T_1888 & _T_1041; // @[Mux.scala 27:72] + wire _T_2050 = _T_1894 & _T_1046; // @[Mux.scala 27:72] + wire _T_2051 = _T_1899 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_2052 = _T_1901 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_2053 = _T_1903 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_2054 = _T_1905 & _T_1055; // @[Mux.scala 27:72] + wire _T_2055 = _T_1908 & _T_1058; // @[Mux.scala 27:72] + wire _T_2056 = _T_1911 & _T_1061; // @[Mux.scala 27:72] + wire _T_2057 = _T_1914 & _T_1064; // @[Mux.scala 27:72] + wire _T_2058 = _T_1917 & _T_1068; // @[Mux.scala 27:72] + wire _T_2059 = _T_1921 & _T_1073; // @[Mux.scala 27:72] + wire _T_2060 = _T_1926 & _T_1076; // @[Mux.scala 27:72] + wire _T_2061 = _T_1929 & _T_1079; // @[Mux.scala 27:72] + wire _T_2062 = _T_1932 & _T_1082; // @[Mux.scala 27:72] + wire _T_2063 = _T_1935 & _T_1085; // @[Mux.scala 27:72] + wire _T_2064 = _T_1938 & _T_1088; // @[Mux.scala 27:72] + wire _T_2065 = _T_1941 & _T_1091; // @[Mux.scala 27:72] + wire _T_2066 = _T_1944 & _T_1094; // @[Mux.scala 27:72] + wire _T_2067 = _T_1947 & _T_1097; // @[Mux.scala 27:72] + wire _T_2068 = _T_1950 & _T_1100; // @[Mux.scala 27:72] + wire _T_2069 = _T_1953 & _T_1105; // @[Mux.scala 27:72] + wire _T_2070 = _T_1958 & _T_1108; // @[Mux.scala 27:72] + wire _T_2071 = _T_1961 & _T_1111; // @[Mux.scala 27:72] + wire _T_2072 = _T_1964 & _T_1114; // @[Mux.scala 27:72] + wire _T_2073 = _T_1967 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_2075 = _T_1971 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_2076 = _T_1973 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_2077 = _T_1975 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_2078 = _T_1977 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_2079 = _T_1979 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_2080 = _T_1981 & _T_1132; // @[Mux.scala 27:72] + wire _T_2081 = _T_1985 & _T_1136; // @[Mux.scala 27:72] + wire _T_2082 = _T_1989 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_2083 = _T_1991 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_2084 = _T_1993 & _T_1144; // @[Mux.scala 27:72] + wire _T_2085 = _T_1997 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_2086 = _T_1999 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_2087 = _T_2001 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_2088 = _T_2003 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_2089 = _T_2005 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_2090 = _T_2007 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_2091 = _T_2009 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_2092 = _T_2011 & _T_1163; // @[Mux.scala 27:72] + wire _T_2093 = _T_2016 & _T_1173; // @[Mux.scala 27:72] + wire _T_2094 = _T_2026 & _T_1176; // @[Mux.scala 27:72] + wire _T_2095 = _T_2029 & _T_1179; // @[Mux.scala 27:72] + wire _T_2096 = _T_2032 & _T_1182; // @[Mux.scala 27:72] + wire _T_2097 = _T_2035 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_2098 = _T_2037 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_2099 = _T_2039 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_2100 = _T_2041 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_2101 = _T_2043 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_2102 = _T_1878 | _T_2046; // @[Mux.scala 27:72] wire _T_2103 = _T_2102 | _T_2047; // @[Mux.scala 27:72] wire _T_2104 = _T_2103 | _T_2048; // @[Mux.scala 27:72] wire _T_2105 = _T_2104 | _T_2049; // @[Mux.scala 27:72] @@ -52125,7 +52126,7 @@ module csr_tlu( wire _T_2117 = _T_2116 | _T_2061; // @[Mux.scala 27:72] wire _T_2118 = _T_2117 | _T_2062; // @[Mux.scala 27:72] wire _T_2119 = _T_2118 | _T_2063; // @[Mux.scala 27:72] - wire _T_2120 = _T_2119 | _T_2043; // @[Mux.scala 27:72] + wire _T_2120 = _T_2119 | _T_2064; // @[Mux.scala 27:72] wire _T_2121 = _T_2120 | _T_2065; // @[Mux.scala 27:72] wire _T_2122 = _T_2121 | _T_2066; // @[Mux.scala 27:72] wire _T_2123 = _T_2122 | _T_2067; // @[Mux.scala 27:72] @@ -52135,7 +52136,7 @@ module csr_tlu( wire _T_2127 = _T_2126 | _T_2071; // @[Mux.scala 27:72] wire _T_2128 = _T_2127 | _T_2072; // @[Mux.scala 27:72] wire _T_2129 = _T_2128 | _T_2073; // @[Mux.scala 27:72] - wire _T_2130 = _T_2129 | _T_2074; // @[Mux.scala 27:72] + wire _T_2130 = _T_2129 | _T_2053; // @[Mux.scala 27:72] wire _T_2131 = _T_2130 | _T_2075; // @[Mux.scala 27:72] wire _T_2132 = _T_2131 | _T_2076; // @[Mux.scala 27:72] wire _T_2133 = _T_2132 | _T_2077; // @[Mux.scala 27:72] @@ -52153,196 +52154,196 @@ module csr_tlu( wire _T_2145 = _T_2144 | _T_2089; // @[Mux.scala 27:72] wire _T_2146 = _T_2145 | _T_2090; // @[Mux.scala 27:72] wire _T_2147 = _T_2146 | _T_2091; // @[Mux.scala 27:72] - wire mhpmc_inc_r_3 = _T_1867 & _T_2147; // @[dec_tlu_ctl.scala 2255:44] + wire _T_2148 = _T_2147 | _T_2092; // @[Mux.scala 27:72] + wire _T_2149 = _T_2148 | _T_2093; // @[Mux.scala 27:72] + wire _T_2150 = _T_2149 | _T_2094; // @[Mux.scala 27:72] + wire _T_2151 = _T_2150 | _T_2095; // @[Mux.scala 27:72] + wire _T_2152 = _T_2151 | _T_2096; // @[Mux.scala 27:72] + wire _T_2153 = _T_2152 | _T_2097; // @[Mux.scala 27:72] + wire _T_2154 = _T_2153 | _T_2098; // @[Mux.scala 27:72] + wire _T_2155 = _T_2154 | _T_2099; // @[Mux.scala 27:72] + wire _T_2156 = _T_2155 | _T_2100; // @[Mux.scala 27:72] + wire _T_2157 = _T_2156 | _T_2101; // @[Mux.scala 27:72] + wire mhpmc_inc_r_3 = _T_1877 & _T_2157; // @[dec_tlu_ctl.scala 2255:44] reg mhpmc_inc_r_d1_0; // @[dec_tlu_ctl.scala 2316:53] reg mhpmc_inc_r_d1_1; // @[dec_tlu_ctl.scala 2317:53] reg mhpmc_inc_r_d1_2; // @[dec_tlu_ctl.scala 2318:53] reg mhpmc_inc_r_d1_3; // @[dec_tlu_ctl.scala 2319:53] reg perfcnt_halted_d1; // @[dec_tlu_ctl.scala 2320:56] wire perfcnt_halted = _T_85 | io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 2323:67] - wire _T_2159 = ~_T_85; // @[dec_tlu_ctl.scala 2324:37] - wire [3:0] _T_2161 = _T_2159 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] _T_2168 = {mhpme6[9],mhpme5[9],mhpme4[9],mhpme3[9]}; // @[Cat.scala 29:58] - wire [3:0] perfcnt_during_sleep = _T_2161 & _T_2168; // @[dec_tlu_ctl.scala 2324:86] - wire _T_2170 = ~perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2326:67] - wire _T_2171 = perfcnt_halted_d1 & _T_2170; // @[dec_tlu_ctl.scala 2326:65] - wire _T_2172 = ~_T_2171; // @[dec_tlu_ctl.scala 2326:45] - wire _T_2175 = ~perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2327:67] - wire _T_2176 = perfcnt_halted_d1 & _T_2175; // @[dec_tlu_ctl.scala 2327:65] - wire _T_2177 = ~_T_2176; // @[dec_tlu_ctl.scala 2327:45] - wire _T_2180 = ~perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2328:67] - wire _T_2181 = perfcnt_halted_d1 & _T_2180; // @[dec_tlu_ctl.scala 2328:65] - wire _T_2182 = ~_T_2181; // @[dec_tlu_ctl.scala 2328:45] - wire _T_2185 = ~perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2329:67] - wire _T_2186 = perfcnt_halted_d1 & _T_2185; // @[dec_tlu_ctl.scala 2329:65] - wire _T_2187 = ~_T_2186; // @[dec_tlu_ctl.scala 2329:45] - wire _T_2190 = io_dec_csr_wraddr_r == 12'hb03; // @[dec_tlu_ctl.scala 2335:72] - wire mhpmc3_wr_en0 = io_dec_csr_wen_r_mod & _T_2190; // @[dec_tlu_ctl.scala 2335:43] - wire _T_2191 = ~perfcnt_halted; // @[dec_tlu_ctl.scala 2336:23] - wire _T_2193 = _T_2191 | perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2336:39] - wire _T_2194 = |mhpmc_inc_r_0; // @[dec_tlu_ctl.scala 2336:86] - wire mhpmc3_wr_en1 = _T_2193 & _T_2194; // @[dec_tlu_ctl.scala 2336:66] + wire _T_2169 = ~_T_85; // @[dec_tlu_ctl.scala 2324:37] + wire [3:0] _T_2171 = _T_2169 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_2178 = {mhpme6[9],mhpme5[9],mhpme4[9],mhpme3[9]}; // @[Cat.scala 29:58] + wire [3:0] perfcnt_during_sleep = _T_2171 & _T_2178; // @[dec_tlu_ctl.scala 2324:86] + wire _T_2180 = ~perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2326:67] + wire _T_2181 = perfcnt_halted_d1 & _T_2180; // @[dec_tlu_ctl.scala 2326:65] + wire _T_2182 = ~_T_2181; // @[dec_tlu_ctl.scala 2326:45] + wire _T_2185 = ~perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2327:67] + wire _T_2186 = perfcnt_halted_d1 & _T_2185; // @[dec_tlu_ctl.scala 2327:65] + wire _T_2187 = ~_T_2186; // @[dec_tlu_ctl.scala 2327:45] + wire _T_2190 = ~perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2328:67] + wire _T_2191 = perfcnt_halted_d1 & _T_2190; // @[dec_tlu_ctl.scala 2328:65] + wire _T_2192 = ~_T_2191; // @[dec_tlu_ctl.scala 2328:45] + wire _T_2195 = ~perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2329:67] + wire _T_2196 = perfcnt_halted_d1 & _T_2195; // @[dec_tlu_ctl.scala 2329:65] + wire _T_2197 = ~_T_2196; // @[dec_tlu_ctl.scala 2329:45] + wire _T_2200 = io_dec_csr_wraddr_r == 12'hb03; // @[dec_tlu_ctl.scala 2335:72] + wire mhpmc3_wr_en0 = io_dec_csr_wen_r_mod & _T_2200; // @[dec_tlu_ctl.scala 2335:43] + wire _T_2201 = ~perfcnt_halted; // @[dec_tlu_ctl.scala 2336:23] + wire _T_2203 = _T_2201 | perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2336:39] + wire _T_2204 = |mhpmc_inc_r_0; // @[dec_tlu_ctl.scala 2336:86] + wire mhpmc3_wr_en1 = _T_2203 & _T_2204; // @[dec_tlu_ctl.scala 2336:66] reg [31:0] mhpmc3h; // @[lib.scala 374:16] reg [31:0] mhpmc3; // @[lib.scala 374:16] - wire [63:0] _T_2197 = {mhpmc3h,mhpmc3}; // @[Cat.scala 29:58] - wire [63:0] _T_2198 = {63'h0,mhpmc_inc_r_0}; // @[Cat.scala 29:58] - wire [63:0] mhpmc3_incr = _T_2197 + _T_2198; // @[dec_tlu_ctl.scala 2340:49] - wire _T_2206 = io_dec_csr_wraddr_r == 12'hb83; // @[dec_tlu_ctl.scala 2345:73] - wire mhpmc3h_wr_en0 = io_dec_csr_wen_r_mod & _T_2206; // @[dec_tlu_ctl.scala 2345:44] - wire _T_2212 = io_dec_csr_wraddr_r == 12'hb04; // @[dec_tlu_ctl.scala 2354:72] - wire mhpmc4_wr_en0 = io_dec_csr_wen_r_mod & _T_2212; // @[dec_tlu_ctl.scala 2354:43] - wire _T_2215 = _T_2191 | perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2355:39] - wire _T_2216 = |mhpmc_inc_r_1; // @[dec_tlu_ctl.scala 2355:86] - wire mhpmc4_wr_en1 = _T_2215 & _T_2216; // @[dec_tlu_ctl.scala 2355:66] + wire [63:0] _T_2207 = {mhpmc3h,mhpmc3}; // @[Cat.scala 29:58] + wire [63:0] _T_2208 = {63'h0,mhpmc_inc_r_0}; // @[Cat.scala 29:58] + wire [63:0] mhpmc3_incr = _T_2207 + _T_2208; // @[dec_tlu_ctl.scala 2340:49] + wire _T_2216 = io_dec_csr_wraddr_r == 12'hb83; // @[dec_tlu_ctl.scala 2345:73] + wire mhpmc3h_wr_en0 = io_dec_csr_wen_r_mod & _T_2216; // @[dec_tlu_ctl.scala 2345:44] + wire _T_2222 = io_dec_csr_wraddr_r == 12'hb04; // @[dec_tlu_ctl.scala 2354:72] + wire mhpmc4_wr_en0 = io_dec_csr_wen_r_mod & _T_2222; // @[dec_tlu_ctl.scala 2354:43] + wire _T_2225 = _T_2201 | perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2355:39] + wire _T_2226 = |mhpmc_inc_r_1; // @[dec_tlu_ctl.scala 2355:86] + wire mhpmc4_wr_en1 = _T_2225 & _T_2226; // @[dec_tlu_ctl.scala 2355:66] reg [31:0] mhpmc4h; // @[lib.scala 374:16] reg [31:0] mhpmc4; // @[lib.scala 374:16] - wire [63:0] _T_2219 = {mhpmc4h,mhpmc4}; // @[Cat.scala 29:58] - wire [63:0] _T_2220 = {63'h0,mhpmc_inc_r_1}; // @[Cat.scala 29:58] - wire [63:0] mhpmc4_incr = _T_2219 + _T_2220; // @[dec_tlu_ctl.scala 2360:49] - wire _T_2229 = io_dec_csr_wraddr_r == 12'hb84; // @[dec_tlu_ctl.scala 2364:73] - wire mhpmc4h_wr_en0 = io_dec_csr_wen_r_mod & _T_2229; // @[dec_tlu_ctl.scala 2364:44] - wire _T_2235 = io_dec_csr_wraddr_r == 12'hb05; // @[dec_tlu_ctl.scala 2373:72] - wire mhpmc5_wr_en0 = io_dec_csr_wen_r_mod & _T_2235; // @[dec_tlu_ctl.scala 2373:43] - wire _T_2238 = _T_2191 | perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2374:39] - wire _T_2239 = |mhpmc_inc_r_2; // @[dec_tlu_ctl.scala 2374:86] - wire mhpmc5_wr_en1 = _T_2238 & _T_2239; // @[dec_tlu_ctl.scala 2374:66] + wire [63:0] _T_2229 = {mhpmc4h,mhpmc4}; // @[Cat.scala 29:58] + wire [63:0] _T_2230 = {63'h0,mhpmc_inc_r_1}; // @[Cat.scala 29:58] + wire [63:0] mhpmc4_incr = _T_2229 + _T_2230; // @[dec_tlu_ctl.scala 2360:49] + wire _T_2239 = io_dec_csr_wraddr_r == 12'hb84; // @[dec_tlu_ctl.scala 2364:73] + wire mhpmc4h_wr_en0 = io_dec_csr_wen_r_mod & _T_2239; // @[dec_tlu_ctl.scala 2364:44] + wire _T_2245 = io_dec_csr_wraddr_r == 12'hb05; // @[dec_tlu_ctl.scala 2373:72] + wire mhpmc5_wr_en0 = io_dec_csr_wen_r_mod & _T_2245; // @[dec_tlu_ctl.scala 2373:43] + wire _T_2248 = _T_2201 | perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2374:39] + wire _T_2249 = |mhpmc_inc_r_2; // @[dec_tlu_ctl.scala 2374:86] + wire mhpmc5_wr_en1 = _T_2248 & _T_2249; // @[dec_tlu_ctl.scala 2374:66] reg [31:0] mhpmc5h; // @[lib.scala 374:16] reg [31:0] mhpmc5; // @[lib.scala 374:16] - wire [63:0] _T_2242 = {mhpmc5h,mhpmc5}; // @[Cat.scala 29:58] - wire [63:0] _T_2243 = {63'h0,mhpmc_inc_r_2}; // @[Cat.scala 29:58] - wire [63:0] mhpmc5_incr = _T_2242 + _T_2243; // @[dec_tlu_ctl.scala 2377:49] - wire _T_2251 = io_dec_csr_wraddr_r == 12'hb85; // @[dec_tlu_ctl.scala 2382:73] - wire mhpmc5h_wr_en0 = io_dec_csr_wen_r_mod & _T_2251; // @[dec_tlu_ctl.scala 2382:44] - wire _T_2257 = io_dec_csr_wraddr_r == 12'hb06; // @[dec_tlu_ctl.scala 2391:72] - wire mhpmc6_wr_en0 = io_dec_csr_wen_r_mod & _T_2257; // @[dec_tlu_ctl.scala 2391:43] - wire _T_2260 = _T_2191 | perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2392:39] - wire _T_2261 = |mhpmc_inc_r_3; // @[dec_tlu_ctl.scala 2392:86] - wire mhpmc6_wr_en1 = _T_2260 & _T_2261; // @[dec_tlu_ctl.scala 2392:66] + wire [63:0] _T_2252 = {mhpmc5h,mhpmc5}; // @[Cat.scala 29:58] + wire [63:0] _T_2253 = {63'h0,mhpmc_inc_r_2}; // @[Cat.scala 29:58] + wire [63:0] mhpmc5_incr = _T_2252 + _T_2253; // @[dec_tlu_ctl.scala 2377:49] + wire _T_2261 = io_dec_csr_wraddr_r == 12'hb85; // @[dec_tlu_ctl.scala 2382:73] + wire mhpmc5h_wr_en0 = io_dec_csr_wen_r_mod & _T_2261; // @[dec_tlu_ctl.scala 2382:44] + wire _T_2267 = io_dec_csr_wraddr_r == 12'hb06; // @[dec_tlu_ctl.scala 2391:72] + wire mhpmc6_wr_en0 = io_dec_csr_wen_r_mod & _T_2267; // @[dec_tlu_ctl.scala 2391:43] + wire _T_2270 = _T_2201 | perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2392:39] + wire _T_2271 = |mhpmc_inc_r_3; // @[dec_tlu_ctl.scala 2392:86] + wire mhpmc6_wr_en1 = _T_2270 & _T_2271; // @[dec_tlu_ctl.scala 2392:66] reg [31:0] mhpmc6h; // @[lib.scala 374:16] reg [31:0] mhpmc6; // @[lib.scala 374:16] - wire [63:0] _T_2264 = {mhpmc6h,mhpmc6}; // @[Cat.scala 29:58] - wire [63:0] _T_2265 = {63'h0,mhpmc_inc_r_3}; // @[Cat.scala 29:58] - wire [63:0] mhpmc6_incr = _T_2264 + _T_2265; // @[dec_tlu_ctl.scala 2395:49] - wire _T_2273 = io_dec_csr_wraddr_r == 12'hb86; // @[dec_tlu_ctl.scala 2400:73] - wire mhpmc6h_wr_en0 = io_dec_csr_wen_r_mod & _T_2273; // @[dec_tlu_ctl.scala 2400:44] - wire _T_2279 = io_dec_csr_wrdata_r[9:0] > 10'h204; // @[dec_tlu_ctl.scala 2411:56] - wire _T_2281 = |io_dec_csr_wrdata_r[31:10]; // @[dec_tlu_ctl.scala 2411:102] - wire _T_2282 = _T_2279 | _T_2281; // @[dec_tlu_ctl.scala 2411:71] - wire _T_2285 = io_dec_csr_wraddr_r == 12'h323; // @[dec_tlu_ctl.scala 2413:70] - wire wr_mhpme3_r = io_dec_csr_wen_r_mod & _T_2285; // @[dec_tlu_ctl.scala 2413:41] - wire _T_2289 = io_dec_csr_wraddr_r == 12'h324; // @[dec_tlu_ctl.scala 2420:70] - wire wr_mhpme4_r = io_dec_csr_wen_r_mod & _T_2289; // @[dec_tlu_ctl.scala 2420:41] - wire _T_2293 = io_dec_csr_wraddr_r == 12'h325; // @[dec_tlu_ctl.scala 2427:70] - wire wr_mhpme5_r = io_dec_csr_wen_r_mod & _T_2293; // @[dec_tlu_ctl.scala 2427:41] - wire _T_2297 = io_dec_csr_wraddr_r == 12'h326; // @[dec_tlu_ctl.scala 2434:70] - wire wr_mhpme6_r = io_dec_csr_wen_r_mod & _T_2297; // @[dec_tlu_ctl.scala 2434:41] - wire _T_2301 = io_dec_csr_wraddr_r == 12'h320; // @[dec_tlu_ctl.scala 2451:77] - wire wr_mcountinhibit_r = io_dec_csr_wen_r_mod & _T_2301; // @[dec_tlu_ctl.scala 2451:48] - wire _T_2313 = io_i0_valid_wb | io_exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 2466:51] - wire _T_2314 = _T_2313 | io_interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 2466:78] - wire _T_2315 = _T_2314 | io_dec_tlu_i0_valid_wb1; // @[dec_tlu_ctl.scala 2466:104] - wire _T_2316 = _T_2315 | io_dec_tlu_i0_exc_valid_wb1; // @[dec_tlu_ctl.scala 2466:130] - wire _T_2317 = _T_2316 | io_dec_tlu_int_valid_wb1; // @[dec_tlu_ctl.scala 2467:32] - reg _T_2320; // @[dec_tlu_ctl.scala 2469:62] - wire _T_2321 = io_i0_exception_valid_r_d1 | io_lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 2470:91] - wire _T_2322 = ~io_trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 2470:137] - wire _T_2323 = io_trigger_hit_r_d1 & _T_2322; // @[dec_tlu_ctl.scala 2470:135] - reg _T_2325; // @[dec_tlu_ctl.scala 2470:62] - reg [4:0] _T_2326; // @[dec_tlu_ctl.scala 2471:62] - reg _T_2327; // @[dec_tlu_ctl.scala 2472:62] - wire [31:0] _T_2333 = {io_core_id,4'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2342 = {21'h3,3'h0,io_mstatus[1],3'h0,io_mstatus[0],3'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2347 = {io_mtvec[30:1],1'h0,io_mtvec[0]}; // @[Cat.scala 29:58] - wire [31:0] _T_2360 = {1'h0,io_mip[5:3],16'h0,io_mip[2],3'h0,io_mip[1],3'h0,io_mip[0],3'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2373 = {1'h0,mie[5:3],16'h0,mie[2],3'h0,mie[1],3'h0,mie[0],3'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2385 = {io_mepc,1'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2390 = {28'h0,mscause}; // @[Cat.scala 29:58] - wire [31:0] _T_2398 = {meivt,10'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2401 = {meivt,meihap,2'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2404 = {28'h0,meicurpl}; // @[Cat.scala 29:58] - wire [31:0] _T_2407 = {28'h0,meicidpl}; // @[Cat.scala 29:58] - wire [31:0] _T_2410 = {28'h0,meipt}; // @[Cat.scala 29:58] - wire [31:0] _T_2413 = {23'h0,mcgc}; // @[Cat.scala 29:58] - wire [31:0] _T_2416 = {13'h0,_T_345,4'h0,mfdc_int[11:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_2420 = {16'h4000,io_dcsr[15:2],2'h3}; // @[Cat.scala 29:58] - wire [31:0] _T_2422 = {io_dpc,1'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2438 = {7'h0,dicawics[16],2'h0,dicawics[15:14],3'h0,dicawics[13:0],3'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2441 = {30'h0,mtsel}; // @[Cat.scala 29:58] - wire [31:0] _T_2470 = {26'h0,mfdht}; // @[Cat.scala 29:58] - wire [31:0] _T_2473 = {30'h0,mfdhs}; // @[Cat.scala 29:58] - wire [31:0] _T_2476 = {22'h0,mhpme3}; // @[Cat.scala 29:58] - wire [31:0] _T_2479 = {22'h0,mhpme4}; // @[Cat.scala 29:58] - wire [31:0] _T_2482 = {22'h0,mhpme5}; // @[Cat.scala 29:58] - wire [31:0] _T_2485 = {22'h0,mhpme6}; // @[Cat.scala 29:58] - wire [31:0] _T_2488 = {25'h0,temp_ncount6_2,1'h0,temp_ncount0}; // @[Cat.scala 29:58] - wire [31:0] _T_2491 = {30'h0,mpmc,1'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2494 = io_csr_pkt_csr_misa ? 32'h40001104 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2495 = io_csr_pkt_csr_mvendorid ? 32'h45 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2496 = io_csr_pkt_csr_marchid ? 32'h10 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2497 = io_csr_pkt_csr_mimpid ? 32'h2 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2498 = io_csr_pkt_csr_mhartid ? _T_2333 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2499 = io_csr_pkt_csr_mstatus ? _T_2342 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2500 = io_csr_pkt_csr_mtvec ? _T_2347 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2501 = io_csr_pkt_csr_mip ? _T_2360 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2502 = io_csr_pkt_csr_mie ? _T_2373 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2503 = io_csr_pkt_csr_mcyclel ? mcyclel : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2504 = io_csr_pkt_csr_mcycleh ? mcycleh_inc : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2505 = io_csr_pkt_csr_minstretl ? minstretl : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2506 = io_csr_pkt_csr_minstreth ? minstreth_inc : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2507 = io_csr_pkt_csr_mscratch ? mscratch : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2508 = io_csr_pkt_csr_mepc ? _T_2385 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2509 = io_csr_pkt_csr_mcause ? mcause : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2510 = io_csr_pkt_csr_mscause ? _T_2390 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2511 = io_csr_pkt_csr_mtval ? mtval : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2512 = io_csr_pkt_csr_mrac ? mrac : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2513 = io_csr_pkt_csr_mdseac ? mdseac : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2514 = io_csr_pkt_csr_meivt ? _T_2398 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2515 = io_csr_pkt_csr_meihap ? _T_2401 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2516 = io_csr_pkt_csr_meicurpl ? _T_2404 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2517 = io_csr_pkt_csr_meicidpl ? _T_2407 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2518 = io_csr_pkt_csr_meipt ? _T_2410 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2519 = io_csr_pkt_csr_mcgc ? _T_2413 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2520 = io_csr_pkt_csr_mfdc ? _T_2416 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2521 = io_csr_pkt_csr_dcsr ? _T_2420 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2522 = io_csr_pkt_csr_dpc ? _T_2422 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2523 = io_csr_pkt_csr_dicad0 ? dicad0[31:0] : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2524 = io_csr_pkt_csr_dicad0h ? dicad0h : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2525 = io_csr_pkt_csr_dicad1 ? dicad1 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2526 = io_csr_pkt_csr_dicawics ? _T_2438 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2527 = io_csr_pkt_csr_mtsel ? _T_2441 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2528 = io_csr_pkt_csr_mtdata1 ? mtdata1_tsel_out : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2529 = io_csr_pkt_csr_mtdata2 ? mtdata2_tsel_out : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2530 = io_csr_pkt_csr_micect ? micect : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2531 = io_csr_pkt_csr_miccmect ? miccmect : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2532 = io_csr_pkt_csr_mdccmect ? mdccmect : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2533 = io_csr_pkt_csr_mhpmc3 ? mhpmc3 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2534 = io_csr_pkt_csr_mhpmc4 ? mhpmc4 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2535 = io_csr_pkt_csr_mhpmc5 ? mhpmc5 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2536 = io_csr_pkt_csr_mhpmc6 ? mhpmc6 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2537 = io_csr_pkt_csr_mhpmc3h ? mhpmc3h : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2538 = io_csr_pkt_csr_mhpmc4h ? mhpmc4h : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2539 = io_csr_pkt_csr_mhpmc5h ? mhpmc5h : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2540 = io_csr_pkt_csr_mhpmc6h ? mhpmc6h : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2541 = io_csr_pkt_csr_mfdht ? _T_2470 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2542 = io_csr_pkt_csr_mfdhs ? _T_2473 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2543 = io_csr_pkt_csr_mhpme3 ? _T_2476 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2544 = io_csr_pkt_csr_mhpme4 ? _T_2479 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2545 = io_csr_pkt_csr_mhpme5 ? _T_2482 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2546 = io_csr_pkt_csr_mhpme6 ? _T_2485 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2547 = io_csr_pkt_csr_mcountinhibit ? _T_2488 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2548 = io_csr_pkt_csr_mpmc ? _T_2491 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2549 = io_dec_timer_read_d ? io_dec_timer_rddata_d : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2550 = _T_2494 | _T_2495; // @[Mux.scala 27:72] - wire [31:0] _T_2551 = _T_2550 | _T_2496; // @[Mux.scala 27:72] - wire [31:0] _T_2552 = _T_2551 | _T_2497; // @[Mux.scala 27:72] - wire [31:0] _T_2553 = _T_2552 | _T_2498; // @[Mux.scala 27:72] - wire [31:0] _T_2554 = _T_2553 | _T_2499; // @[Mux.scala 27:72] - wire [31:0] _T_2555 = _T_2554 | _T_2500; // @[Mux.scala 27:72] - wire [31:0] _T_2556 = _T_2555 | _T_2501; // @[Mux.scala 27:72] - wire [31:0] _T_2557 = _T_2556 | _T_2502; // @[Mux.scala 27:72] - wire [31:0] _T_2558 = _T_2557 | _T_2503; // @[Mux.scala 27:72] - wire [31:0] _T_2559 = _T_2558 | _T_2504; // @[Mux.scala 27:72] - wire [31:0] _T_2560 = _T_2559 | _T_2505; // @[Mux.scala 27:72] + wire [63:0] _T_2274 = {mhpmc6h,mhpmc6}; // @[Cat.scala 29:58] + wire [63:0] _T_2275 = {63'h0,mhpmc_inc_r_3}; // @[Cat.scala 29:58] + wire [63:0] mhpmc6_incr = _T_2274 + _T_2275; // @[dec_tlu_ctl.scala 2395:49] + wire _T_2283 = io_dec_csr_wraddr_r == 12'hb86; // @[dec_tlu_ctl.scala 2400:73] + wire mhpmc6h_wr_en0 = io_dec_csr_wen_r_mod & _T_2283; // @[dec_tlu_ctl.scala 2400:44] + wire _T_2289 = io_dec_csr_wrdata_r[9:0] > 10'h204; // @[dec_tlu_ctl.scala 2411:56] + wire _T_2291 = |io_dec_csr_wrdata_r[31:10]; // @[dec_tlu_ctl.scala 2411:102] + wire _T_2292 = _T_2289 | _T_2291; // @[dec_tlu_ctl.scala 2411:71] + wire _T_2295 = io_dec_csr_wraddr_r == 12'h323; // @[dec_tlu_ctl.scala 2413:70] + wire wr_mhpme3_r = io_dec_csr_wen_r_mod & _T_2295; // @[dec_tlu_ctl.scala 2413:41] + wire _T_2299 = io_dec_csr_wraddr_r == 12'h324; // @[dec_tlu_ctl.scala 2420:70] + wire wr_mhpme4_r = io_dec_csr_wen_r_mod & _T_2299; // @[dec_tlu_ctl.scala 2420:41] + wire _T_2303 = io_dec_csr_wraddr_r == 12'h325; // @[dec_tlu_ctl.scala 2427:70] + wire wr_mhpme5_r = io_dec_csr_wen_r_mod & _T_2303; // @[dec_tlu_ctl.scala 2427:41] + wire _T_2307 = io_dec_csr_wraddr_r == 12'h326; // @[dec_tlu_ctl.scala 2434:70] + wire wr_mhpme6_r = io_dec_csr_wen_r_mod & _T_2307; // @[dec_tlu_ctl.scala 2434:41] + wire _T_2311 = io_dec_csr_wraddr_r == 12'h320; // @[dec_tlu_ctl.scala 2451:77] + wire wr_mcountinhibit_r = io_dec_csr_wen_r_mod & _T_2311; // @[dec_tlu_ctl.scala 2451:48] + wire _T_2323 = io_i0_valid_wb | io_exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 2466:51] + wire _T_2324 = _T_2323 | io_interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 2466:78] + wire _T_2325 = _T_2324 | io_dec_tlu_i0_valid_wb1; // @[dec_tlu_ctl.scala 2466:104] + wire _T_2326 = _T_2325 | io_dec_tlu_i0_exc_valid_wb1; // @[dec_tlu_ctl.scala 2466:130] + wire _T_2327 = _T_2326 | io_dec_tlu_int_valid_wb1; // @[dec_tlu_ctl.scala 2467:32] + reg _T_2330; // @[dec_tlu_ctl.scala 2469:62] + wire _T_2331 = io_i0_exception_valid_r_d1 | io_lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 2470:91] + wire _T_2332 = ~io_trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 2470:137] + wire _T_2333 = io_trigger_hit_r_d1 & _T_2332; // @[dec_tlu_ctl.scala 2470:135] + reg _T_2335; // @[dec_tlu_ctl.scala 2470:62] + reg [4:0] _T_2336; // @[dec_tlu_ctl.scala 2471:62] + reg _T_2337; // @[dec_tlu_ctl.scala 2472:62] + wire [31:0] _T_2343 = {io_core_id,4'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2352 = {21'h3,3'h0,io_mstatus[1],3'h0,io_mstatus[0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2357 = {io_mtvec[30:1],1'h0,io_mtvec[0]}; // @[Cat.scala 29:58] + wire [31:0] _T_2370 = {1'h0,io_mip[5:3],16'h0,io_mip[2],3'h0,io_mip[1],3'h0,io_mip[0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2383 = {1'h0,mie[5:3],16'h0,mie[2],3'h0,mie[1],3'h0,mie[0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2395 = {io_mepc,1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2400 = {28'h0,mscause}; // @[Cat.scala 29:58] + wire [31:0] _T_2408 = {meivt,10'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2411 = {meivt,meihap,2'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2414 = {28'h0,meicurpl}; // @[Cat.scala 29:58] + wire [31:0] _T_2417 = {28'h0,meicidpl}; // @[Cat.scala 29:58] + wire [31:0] _T_2420 = {28'h0,meipt}; // @[Cat.scala 29:58] + wire [31:0] _T_2423 = {23'h0,mcgc}; // @[Cat.scala 29:58] + wire [31:0] _T_2426 = {13'h0,_T_350,4'h0,mfdc_int[11:7],_T_353,mfdc_int[5:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_2430 = {16'h4000,io_dcsr[15:2],2'h3}; // @[Cat.scala 29:58] + wire [31:0] _T_2432 = {io_dpc,1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2448 = {7'h0,dicawics[16],2'h0,dicawics[15:14],3'h0,dicawics[13:0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2451 = {30'h0,mtsel}; // @[Cat.scala 29:58] + wire [31:0] _T_2480 = {26'h0,mfdht}; // @[Cat.scala 29:58] + wire [31:0] _T_2483 = {30'h0,mfdhs}; // @[Cat.scala 29:58] + wire [31:0] _T_2486 = {22'h0,mhpme3}; // @[Cat.scala 29:58] + wire [31:0] _T_2489 = {22'h0,mhpme4}; // @[Cat.scala 29:58] + wire [31:0] _T_2492 = {22'h0,mhpme5}; // @[Cat.scala 29:58] + wire [31:0] _T_2495 = {22'h0,mhpme6}; // @[Cat.scala 29:58] + wire [31:0] _T_2498 = {25'h0,temp_ncount6_2,1'h0,temp_ncount0}; // @[Cat.scala 29:58] + wire [31:0] _T_2501 = {30'h0,mpmc,1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2504 = io_csr_pkt_csr_misa ? 32'h40001104 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2505 = io_csr_pkt_csr_mvendorid ? 32'h45 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2506 = io_csr_pkt_csr_marchid ? 32'h10 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2507 = io_csr_pkt_csr_mimpid ? 32'h2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2508 = io_csr_pkt_csr_mhartid ? _T_2343 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2509 = io_csr_pkt_csr_mstatus ? _T_2352 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2510 = io_csr_pkt_csr_mtvec ? _T_2357 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2511 = io_csr_pkt_csr_mip ? _T_2370 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2512 = io_csr_pkt_csr_mie ? _T_2383 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2513 = io_csr_pkt_csr_mcyclel ? mcyclel : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2514 = io_csr_pkt_csr_mcycleh ? mcycleh_inc : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2515 = io_csr_pkt_csr_minstretl ? minstretl : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2516 = io_csr_pkt_csr_minstreth ? minstreth_inc : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2517 = io_csr_pkt_csr_mscratch ? mscratch : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2518 = io_csr_pkt_csr_mepc ? _T_2395 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2519 = io_csr_pkt_csr_mcause ? mcause : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2520 = io_csr_pkt_csr_mscause ? _T_2400 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2521 = io_csr_pkt_csr_mtval ? mtval : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2522 = io_csr_pkt_csr_mrac ? mrac : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2523 = io_csr_pkt_csr_mdseac ? mdseac : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2524 = io_csr_pkt_csr_meivt ? _T_2408 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2525 = io_csr_pkt_csr_meihap ? _T_2411 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2526 = io_csr_pkt_csr_meicurpl ? _T_2414 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2527 = io_csr_pkt_csr_meicidpl ? _T_2417 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2528 = io_csr_pkt_csr_meipt ? _T_2420 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2529 = io_csr_pkt_csr_mcgc ? _T_2423 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2530 = io_csr_pkt_csr_mfdc ? _T_2426 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2531 = io_csr_pkt_csr_dcsr ? _T_2430 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2532 = io_csr_pkt_csr_dpc ? _T_2432 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2533 = io_csr_pkt_csr_dicad0 ? dicad0[31:0] : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2534 = io_csr_pkt_csr_dicad0h ? dicad0h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2535 = io_csr_pkt_csr_dicad1 ? dicad1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2536 = io_csr_pkt_csr_dicawics ? _T_2448 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2537 = io_csr_pkt_csr_mtsel ? _T_2451 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2538 = io_csr_pkt_csr_mtdata1 ? mtdata1_tsel_out : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2539 = io_csr_pkt_csr_mtdata2 ? mtdata2_tsel_out : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2540 = io_csr_pkt_csr_micect ? micect : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2541 = io_csr_pkt_csr_miccmect ? miccmect : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2542 = io_csr_pkt_csr_mdccmect ? mdccmect : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2543 = io_csr_pkt_csr_mhpmc3 ? mhpmc3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2544 = io_csr_pkt_csr_mhpmc4 ? mhpmc4 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2545 = io_csr_pkt_csr_mhpmc5 ? mhpmc5 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2546 = io_csr_pkt_csr_mhpmc6 ? mhpmc6 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2547 = io_csr_pkt_csr_mhpmc3h ? mhpmc3h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2548 = io_csr_pkt_csr_mhpmc4h ? mhpmc4h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2549 = io_csr_pkt_csr_mhpmc5h ? mhpmc5h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2550 = io_csr_pkt_csr_mhpmc6h ? mhpmc6h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2551 = io_csr_pkt_csr_mfdht ? _T_2480 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2552 = io_csr_pkt_csr_mfdhs ? _T_2483 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2553 = io_csr_pkt_csr_mhpme3 ? _T_2486 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2554 = io_csr_pkt_csr_mhpme4 ? _T_2489 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2555 = io_csr_pkt_csr_mhpme5 ? _T_2492 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2556 = io_csr_pkt_csr_mhpme6 ? _T_2495 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2557 = io_csr_pkt_csr_mcountinhibit ? _T_2498 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2558 = io_csr_pkt_csr_mpmc ? _T_2501 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2559 = io_dec_timer_read_d ? io_dec_timer_rddata_d : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2560 = _T_2504 | _T_2505; // @[Mux.scala 27:72] wire [31:0] _T_2561 = _T_2560 | _T_2506; // @[Mux.scala 27:72] wire [31:0] _T_2562 = _T_2561 | _T_2507; // @[Mux.scala 27:72] wire [31:0] _T_2563 = _T_2562 | _T_2508; // @[Mux.scala 27:72] @@ -52386,6 +52387,16 @@ module csr_tlu( wire [31:0] _T_2601 = _T_2600 | _T_2546; // @[Mux.scala 27:72] wire [31:0] _T_2602 = _T_2601 | _T_2547; // @[Mux.scala 27:72] wire [31:0] _T_2603 = _T_2602 | _T_2548; // @[Mux.scala 27:72] + wire [31:0] _T_2604 = _T_2603 | _T_2549; // @[Mux.scala 27:72] + wire [31:0] _T_2605 = _T_2604 | _T_2550; // @[Mux.scala 27:72] + wire [31:0] _T_2606 = _T_2605 | _T_2551; // @[Mux.scala 27:72] + wire [31:0] _T_2607 = _T_2606 | _T_2552; // @[Mux.scala 27:72] + wire [31:0] _T_2608 = _T_2607 | _T_2553; // @[Mux.scala 27:72] + wire [31:0] _T_2609 = _T_2608 | _T_2554; // @[Mux.scala 27:72] + wire [31:0] _T_2610 = _T_2609 | _T_2555; // @[Mux.scala 27:72] + wire [31:0] _T_2611 = _T_2610 | _T_2556; // @[Mux.scala 27:72] + wire [31:0] _T_2612 = _T_2611 | _T_2557; // @[Mux.scala 27:72] + wire [31:0] _T_2613 = _T_2612 | _T_2558; // @[Mux.scala 27:72] rvclkhdr rvclkhdr ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), @@ -52596,7 +52607,7 @@ module csr_tlu( .io_en(rvclkhdr_34_io_en), .io_scan_mode(rvclkhdr_34_io_scan_mode) ); - assign io_dec_tlu_ic_diag_pkt_icache_wrdata = {_T_753,dicad0[31:0]}; // @[dec_tlu_ctl.scala 2136:56] + assign io_dec_tlu_ic_diag_pkt_icache_wrdata = {_T_763,dicad0[31:0]}; // @[dec_tlu_ctl.scala 2136:56] assign io_dec_tlu_ic_diag_pkt_icache_dicawics = dicawics; // @[dec_tlu_ctl.scala 2139:41] assign io_dec_tlu_ic_diag_pkt_icache_rd_valid = icache_rd_valid_f; // @[dec_tlu_ctl.scala 2147:41] assign io_dec_tlu_ic_diag_pkt_icache_wr_valid = icache_wr_valid_f; // @[dec_tlu_ctl.scala 2148:41] @@ -52628,52 +52639,52 @@ module csr_tlu( assign io_trigger_pkt_any_3_execute = io_mtdata1_t_3[2]; // @[dec_tlu_ctl.scala 2216:40] assign io_trigger_pkt_any_3_m = io_mtdata1_t_3[3]; // @[dec_tlu_ctl.scala 2217:40] assign io_trigger_pkt_any_3_tdata2 = mtdata2_t_3; // @[dec_tlu_ctl.scala 2230:51] - assign io_dec_tlu_int_valid_wb1 = _T_2327; // @[dec_tlu_ctl.scala 2472:30] - assign io_dec_tlu_i0_exc_valid_wb1 = _T_2325; // @[dec_tlu_ctl.scala 2470:30] - assign io_dec_tlu_i0_valid_wb1 = _T_2320; // @[dec_tlu_ctl.scala 2469:30] + assign io_dec_tlu_int_valid_wb1 = _T_2337; // @[dec_tlu_ctl.scala 2472:30] + assign io_dec_tlu_i0_exc_valid_wb1 = _T_2335; // @[dec_tlu_ctl.scala 2470:30] + assign io_dec_tlu_i0_valid_wb1 = _T_2330; // @[dec_tlu_ctl.scala 2469:30] assign io_dec_tlu_mtval_wb1 = mtval; // @[dec_tlu_ctl.scala 2474:24] - assign io_dec_tlu_exc_cause_wb1 = _T_2326; // @[dec_tlu_ctl.scala 2471:30] - assign io_dec_tlu_perfcnt0 = mhpmc_inc_r_d1_0 & _T_2172; // @[dec_tlu_ctl.scala 2326:22] - assign io_dec_tlu_perfcnt1 = mhpmc_inc_r_d1_1 & _T_2177; // @[dec_tlu_ctl.scala 2327:22] - assign io_dec_tlu_perfcnt2 = mhpmc_inc_r_d1_2 & _T_2182; // @[dec_tlu_ctl.scala 2328:22] - assign io_dec_tlu_perfcnt3 = mhpmc_inc_r_d1_3 & _T_2187; // @[dec_tlu_ctl.scala 2329:22] + assign io_dec_tlu_exc_cause_wb1 = _T_2336; // @[dec_tlu_ctl.scala 2471:30] + assign io_dec_tlu_perfcnt0 = mhpmc_inc_r_d1_0 & _T_2182; // @[dec_tlu_ctl.scala 2326:22] + assign io_dec_tlu_perfcnt1 = mhpmc_inc_r_d1_1 & _T_2187; // @[dec_tlu_ctl.scala 2327:22] + assign io_dec_tlu_perfcnt2 = mhpmc_inc_r_d1_2 & _T_2192; // @[dec_tlu_ctl.scala 2328:22] + assign io_dec_tlu_perfcnt3 = mhpmc_inc_r_d1_3 & _T_2197; // @[dec_tlu_ctl.scala 2329:22] assign io_dec_tlu_misc_clk_override = mcgc[8]; // @[dec_tlu_ctl.scala 1698:31] assign io_dec_tlu_dec_clk_override = mcgc[7]; // @[dec_tlu_ctl.scala 1699:31] assign io_dec_tlu_lsu_clk_override = mcgc[4]; // @[dec_tlu_ctl.scala 1701:31] - assign io_dec_tlu_bus_clk_override = mcgc[3]; // @[dec_tlu_ctl.scala 1702:31] assign io_dec_tlu_pic_clk_override = mcgc[2]; // @[dec_tlu_ctl.scala 1703:31] assign io_dec_tlu_dccm_clk_override = mcgc[1]; // @[dec_tlu_ctl.scala 1704:31] assign io_dec_tlu_icm_clk_override = mcgc[0]; // @[dec_tlu_ctl.scala 1705:31] - assign io_dec_csr_rddata_d = _T_2603 | _T_2549; // @[dec_tlu_ctl.scala 2479:21] + assign io_dec_csr_rddata_d = _T_2613 | _T_2559; // @[dec_tlu_ctl.scala 2479:21] assign io_dec_tlu_pipelining_disable = mfdc[0]; // @[dec_tlu_ctl.scala 1748:39] - assign io_dec_tlu_wr_pause_r = _T_360 & _T_361; // @[dec_tlu_ctl.scala 1757:24] + assign io_dec_tlu_wr_pause_r = _T_370 & _T_371; // @[dec_tlu_ctl.scala 1757:24] assign io_dec_tlu_meipt = meipt; // @[dec_tlu_ctl.scala 1986:19] assign io_dec_tlu_meicurpl = meicurpl; // @[dec_tlu_ctl.scala 1950:22] assign io_dec_tlu_meihap = {meivt,meihap}; // @[dec_tlu_ctl.scala 1936:20] assign io_dec_tlu_mrac_ff = mrac; // @[dec_tlu_ctl.scala 1787:21] + assign io_dec_tlu_wb_coalescing_disable = mfdc[2]; // @[dec_tlu_ctl.scala 1747:39] assign io_dec_tlu_bpred_disable = mfdc[3]; // @[dec_tlu_ctl.scala 1746:39] assign io_dec_tlu_sideeffect_posted_disable = mfdc[6]; // @[dec_tlu_ctl.scala 1745:39] assign io_dec_tlu_core_ecc_disable = mfdc[8]; // @[dec_tlu_ctl.scala 1744:39] assign io_dec_tlu_external_ldfwd_disable = mfdc[11]; // @[dec_tlu_ctl.scala 1743:39] assign io_dec_tlu_dma_qos_prty = mfdc[18:16]; // @[dec_tlu_ctl.scala 1742:39] assign io_dec_csr_wen_r_mod = _T_1 & _T_2; // @[dec_tlu_ctl.scala 1431:23] - assign io_fw_halt_req = _T_492 & _T_493; // @[dec_tlu_ctl.scala 1822:17] + assign io_fw_halt_req = _T_502 & _T_503; // @[dec_tlu_ctl.scala 1822:17] assign io_mstatus = _T_56; // @[dec_tlu_ctl.scala 1447:13] assign io_mstatus_mie_ns = io_mstatus[0] & _T_54; // @[dec_tlu_ctl.scala 1446:20] - assign io_dcsr = _T_691; // @[dec_tlu_ctl.scala 2033:10] + assign io_dcsr = _T_701; // @[dec_tlu_ctl.scala 2033:10] assign io_mtvec = _T_62; // @[dec_tlu_ctl.scala 1459:11] assign io_mip = _T_68; // @[dec_tlu_ctl.scala 1474:9] assign io_mie_ns = wr_mie_r ? _T_78 : mie; // @[dec_tlu_ctl.scala 1488:12] assign io_npc_r = _T_161 | _T_159; // @[dec_tlu_ctl.scala 1582:11] assign io_npc_r_d1 = _T_167; // @[dec_tlu_ctl.scala 1588:14] assign io_mepc = _T_196; // @[dec_tlu_ctl.scala 1607:10] - assign io_mdseac_locked_ns = mdseac_en | _T_479; // @[dec_tlu_ctl.scala 1805:22] - assign io_force_halt = mfdht[0] & _T_599; // @[dec_tlu_ctl.scala 1913:16] - assign io_dpc = _T_716; // @[dec_tlu_ctl.scala 2050:9] - assign io_mtdata1_t_0 = _T_862; // @[dec_tlu_ctl.scala 2207:39] - assign io_mtdata1_t_1 = _T_863; // @[dec_tlu_ctl.scala 2207:39] - assign io_mtdata1_t_2 = _T_864; // @[dec_tlu_ctl.scala 2207:39] - assign io_mtdata1_t_3 = _T_865; // @[dec_tlu_ctl.scala 2207:39] + assign io_mdseac_locked_ns = mdseac_en | _T_489; // @[dec_tlu_ctl.scala 1805:22] + assign io_force_halt = mfdht[0] & _T_609; // @[dec_tlu_ctl.scala 1913:16] + assign io_dpc = _T_726; // @[dec_tlu_ctl.scala 2050:9] + assign io_mtdata1_t_0 = _T_872; // @[dec_tlu_ctl.scala 2207:39] + assign io_mtdata1_t_1 = _T_873; // @[dec_tlu_ctl.scala 2207:39] + assign io_mtdata1_t_2 = _T_874; // @[dec_tlu_ctl.scala 2207:39] + assign io_mtdata1_t_3 = _T_875; // @[dec_tlu_ctl.scala 2207:39] assign rvclkhdr_io_clk = clock; // @[lib.scala 370:18] assign rvclkhdr_io_en = io_dec_csr_wen_r_mod & _T_58; // @[lib.scala 371:17] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] @@ -52705,34 +52716,34 @@ module csr_tlu( assign rvclkhdr_9_io_en = io_dec_csr_wen_r_mod & _T_337; // @[lib.scala 371:17] assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_10_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_10_io_en = io_dec_csr_wen_r_mod & _T_364; // @[lib.scala 371:17] + assign rvclkhdr_10_io_en = io_dec_csr_wen_r_mod & _T_374; // @[lib.scala 371:17] assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_11_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_11_io_en = _T_483 & _T_484; // @[lib.scala 371:17] + assign rvclkhdr_11_io_en = _T_493 & _T_494; // @[lib.scala 371:17] assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_12_io_clk = clock; // @[lib.scala 370:18] assign rvclkhdr_12_io_en = wr_micect_r | io_ic_perr_r_d1; // @[lib.scala 371:17] assign rvclkhdr_12_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_13_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_13_io_en = _T_539 | io_iccm_dma_sb_error; // @[lib.scala 371:17] + assign rvclkhdr_13_io_en = _T_549 | io_iccm_dma_sb_error; // @[lib.scala 371:17] assign rvclkhdr_13_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_14_io_clk = clock; // @[lib.scala 370:18] assign rvclkhdr_14_io_en = wr_mdccmect_r | io_lsu_single_ecc_error_r_d1; // @[lib.scala 371:17] assign rvclkhdr_14_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_15_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_15_io_en = io_dec_csr_wen_r_mod & _T_602; // @[lib.scala 371:17] + assign rvclkhdr_15_io_en = io_dec_csr_wen_r_mod & _T_612; // @[lib.scala 371:17] assign rvclkhdr_15_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_16_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_16_io_en = _T_622 | io_take_ext_int_start; // @[lib.scala 371:17] + assign rvclkhdr_16_io_en = _T_632 | io_take_ext_int_start; // @[lib.scala 371:17] assign rvclkhdr_16_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_17_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_17_io_en = _T_688 | io_take_nmi; // @[lib.scala 371:17] + assign rvclkhdr_17_io_en = _T_698 | io_take_nmi; // @[lib.scala 371:17] assign rvclkhdr_17_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_18_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_18_io_en = _T_713 | dpc_capture_npc; // @[lib.scala 371:17] + assign rvclkhdr_18_io_en = _T_723 | dpc_capture_npc; // @[lib.scala 371:17] assign rvclkhdr_18_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_19_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_19_io_en = _T_653 & _T_723; // @[lib.scala 371:17] + assign rvclkhdr_19_io_en = _T_663 & _T_733; // @[lib.scala 371:17] assign rvclkhdr_19_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_20_io_clk = clock; // @[lib.scala 370:18] assign rvclkhdr_20_io_en = wr_dicad0_r | io_ifu_ic_debug_rd_data_valid; // @[lib.scala 371:17] @@ -52741,16 +52752,16 @@ module csr_tlu( assign rvclkhdr_21_io_en = wr_dicad0h_r | io_ifu_ic_debug_rd_data_valid; // @[lib.scala 371:17] assign rvclkhdr_21_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_22_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_22_io_en = _T_961 & _T_797; // @[lib.scala 371:17] + assign rvclkhdr_22_io_en = _T_971 & _T_807; // @[lib.scala 371:17] assign rvclkhdr_22_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_23_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_23_io_en = _T_970 & _T_806; // @[lib.scala 371:17] + assign rvclkhdr_23_io_en = _T_980 & _T_816; // @[lib.scala 371:17] assign rvclkhdr_23_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_24_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_24_io_en = _T_979 & _T_815; // @[lib.scala 371:17] + assign rvclkhdr_24_io_en = _T_989 & _T_825; // @[lib.scala 371:17] assign rvclkhdr_24_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_25_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_25_io_en = _T_988 & _T_824; // @[lib.scala 371:17] + assign rvclkhdr_25_io_en = _T_998 & _T_834; // @[lib.scala 371:17] assign rvclkhdr_25_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_26_io_clk = clock; // @[lib.scala 370:18] assign rvclkhdr_26_io_en = mhpmc3_wr_en0 | mhpmc3_wr_en1; // @[lib.scala 371:17] @@ -52777,7 +52788,7 @@ module csr_tlu( assign rvclkhdr_33_io_en = mhpmc6h_wr_en0 | mhpmc6_wr_en1; // @[lib.scala 371:17] assign rvclkhdr_33_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_34_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_34_io_en = _T_2317 | io_clk_override; // @[lib.scala 345:16] + assign rvclkhdr_34_io_en = _T_2327 | io_clk_override; // @[lib.scala 345:16] assign rvclkhdr_34_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE @@ -52887,9 +52898,9 @@ initial begin _RAND_35 = {1{`RANDOM}}; meipt = _RAND_35[3:0]; _RAND_36 = {1{`RANDOM}}; - _T_691 = _RAND_36[15:0]; + _T_701 = _RAND_36[15:0]; _RAND_37 = {1{`RANDOM}}; - _T_716 = _RAND_37[30:0]; + _T_726 = _RAND_37[30:0]; _RAND_38 = {1{`RANDOM}}; dicawics = _RAND_38[16:0]; _RAND_39 = {3{`RANDOM}}; @@ -52897,7 +52908,7 @@ initial begin _RAND_40 = {1{`RANDOM}}; dicad0h = _RAND_40[31:0]; _RAND_41 = {1{`RANDOM}}; - _T_748 = _RAND_41[31:0]; + _T_758 = _RAND_41[31:0]; _RAND_42 = {1{`RANDOM}}; icache_rd_valid_f = _RAND_42[0:0]; _RAND_43 = {1{`RANDOM}}; @@ -52905,13 +52916,13 @@ initial begin _RAND_44 = {1{`RANDOM}}; mtsel = _RAND_44[1:0]; _RAND_45 = {1{`RANDOM}}; - _T_862 = _RAND_45[9:0]; + _T_872 = _RAND_45[9:0]; _RAND_46 = {1{`RANDOM}}; - _T_863 = _RAND_46[9:0]; + _T_873 = _RAND_46[9:0]; _RAND_47 = {1{`RANDOM}}; - _T_864 = _RAND_47[9:0]; + _T_874 = _RAND_47[9:0]; _RAND_48 = {1{`RANDOM}}; - _T_865 = _RAND_48[9:0]; + _T_875 = _RAND_48[9:0]; _RAND_49 = {1{`RANDOM}}; mtdata2_t_0 = _RAND_49[31:0]; _RAND_50 = {1{`RANDOM}}; @@ -52955,13 +52966,13 @@ initial begin _RAND_69 = {1{`RANDOM}}; mhpmc6 = _RAND_69[31:0]; _RAND_70 = {1{`RANDOM}}; - _T_2320 = _RAND_70[0:0]; + _T_2330 = _RAND_70[0:0]; _RAND_71 = {1{`RANDOM}}; - _T_2325 = _RAND_71[0:0]; + _T_2335 = _RAND_71[0:0]; _RAND_72 = {1{`RANDOM}}; - _T_2326 = _RAND_72[4:0]; + _T_2336 = _RAND_72[4:0]; _RAND_73 = {1{`RANDOM}}; - _T_2327 = _RAND_73[0:0]; + _T_2337 = _RAND_73[0:0]; `endif // RANDOMIZE_REG_INIT if (reset) begin mpmc_b = 1'h0; @@ -53072,10 +53083,10 @@ initial begin meipt = 4'h0; end if (reset) begin - _T_691 = 16'h0; + _T_701 = 16'h0; end if (reset) begin - _T_716 = 31'h0; + _T_726 = 31'h0; end if (reset) begin dicawics = 17'h0; @@ -53087,7 +53098,7 @@ initial begin dicad0h = 32'h0; end if (reset) begin - _T_748 = 32'h0; + _T_758 = 32'h0; end if (reset) begin icache_rd_valid_f = 1'h0; @@ -53099,16 +53110,16 @@ initial begin mtsel = 2'h0; end if (reset) begin - _T_862 = 10'h0; + _T_872 = 10'h0; end if (reset) begin - _T_863 = 10'h0; + _T_873 = 10'h0; end if (reset) begin - _T_864 = 10'h0; + _T_874 = 10'h0; end if (reset) begin - _T_865 = 10'h0; + _T_875 = 10'h0; end if (reset) begin mtdata2_t_0 = 32'h0; @@ -53174,16 +53185,16 @@ initial begin mhpmc6 = 32'h0; end if (reset) begin - _T_2320 = 1'h0; + _T_2330 = 1'h0; end if (reset) begin - _T_2325 = 1'h0; + _T_2335 = 1'h0; end if (reset) begin - _T_2326 = 5'h0; + _T_2336 = 5'h0; end if (reset) begin - _T_2327 = 1'h0; + _T_2337 = 1'h0; end `endif // RANDOMIZE end // initial @@ -53195,9 +53206,9 @@ end // initial if (reset) begin mpmc_b <= 1'h0; end else if (wr_mpmc_r) begin - mpmc_b <= _T_500; + mpmc_b <= _T_510; end else begin - mpmc_b <= _T_501; + mpmc_b <= _T_511; end end always @(posedge io_free_clk or posedge reset) begin @@ -53218,27 +53229,27 @@ end // initial if (reset) begin mdccmect <= 32'h0; end else if (wr_mdccmect_r) begin - mdccmect <= _T_515; + mdccmect <= _T_525; end else begin - mdccmect <= _T_559; + mdccmect <= _T_569; end end always @(posedge rvclkhdr_13_io_l1clk or posedge reset) begin if (reset) begin miccmect <= 32'h0; end else if (wr_miccmect_r) begin - miccmect <= _T_515; + miccmect <= _T_525; end else begin - miccmect <= _T_538; + miccmect <= _T_548; end end always @(posedge rvclkhdr_12_io_l1clk or posedge reset) begin if (reset) begin micect <= 32'h0; end else if (wr_micect_r) begin - micect <= _T_515; + micect <= _T_525; end else begin - micect <= _T_517; + micect <= _T_527; end end always @(posedge io_free_clk or posedge reset) begin @@ -53386,14 +53397,14 @@ end // initial if (reset) begin mfdc_int <= 15'h0; end else begin - mfdc_int <= {_T_341,io_dec_csr_wrdata_r[11:0]}; + mfdc_int <= {_T_347,_T_346}; end end always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin if (reset) begin mrac <= 32'h0; end else begin - mrac <= {_T_474,_T_459}; + mrac <= {_T_484,_T_469}; end end always @(posedge rvclkhdr_11_io_l1clk or posedge reset) begin @@ -53413,11 +53424,11 @@ end // initial always @(posedge io_active_clk or posedge reset) begin if (reset) begin mfdhs <= 2'h0; - end else if (_T_585) begin + end else if (_T_595) begin if (wr_mfdhs_r) begin mfdhs <= io_dec_csr_wrdata_r[1:0]; - end else if (_T_579) begin - mfdhs <= _T_583; + end else if (_T_589) begin + mfdhs <= _T_593; end end end @@ -53426,7 +53437,7 @@ end // initial force_halt_ctr_f <= 32'h0; end else if (mfdht[0]) begin if (io_debug_halt_req_f) begin - force_halt_ctr_f <= _T_590; + force_halt_ctr_f <= _T_600; end else if (io_dbg_tlu_halted_f) begin force_halt_ctr_f <= 32'h0; end @@ -53471,27 +53482,27 @@ end // initial end always @(posedge rvclkhdr_17_io_l1clk or posedge reset) begin if (reset) begin - _T_691 <= 16'h0; + _T_701 <= 16'h0; end else if (enter_debug_halt_req_le) begin - _T_691 <= _T_665; + _T_701 <= _T_675; end else if (wr_dcsr_r) begin - _T_691 <= _T_680; + _T_701 <= _T_690; end else begin - _T_691 <= _T_685; + _T_701 <= _T_695; end end always @(posedge rvclkhdr_18_io_l1clk or posedge reset) begin if (reset) begin - _T_716 <= 31'h0; + _T_726 <= 31'h0; end else begin - _T_716 <= _T_711 | _T_710; + _T_726 <= _T_721 | _T_720; end end always @(posedge rvclkhdr_19_io_l1clk or posedge reset) begin if (reset) begin dicawics <= 17'h0; end else begin - dicawics <= {_T_720,io_dec_csr_wrdata_r[16:3]}; + dicawics <= {_T_730,io_dec_csr_wrdata_r[16:3]}; end end always @(posedge rvclkhdr_20_io_l1clk or posedge reset) begin @@ -53514,12 +53525,12 @@ end // initial end always @(posedge io_active_clk or posedge reset) begin if (reset) begin - _T_748 <= 32'h0; - end else if (_T_746) begin - if (_T_742) begin - _T_748 <= io_dec_csr_wrdata_r; + _T_758 <= 32'h0; + end else if (_T_756) begin + if (_T_752) begin + _T_758 <= io_dec_csr_wrdata_r; end else begin - _T_748 <= {{25'd0}, io_ifu_ic_debug_rd_data[70:64]}; + _T_758 <= {{25'd0}, io_ifu_ic_debug_rd_data[70:64]}; end end end @@ -53527,14 +53538,14 @@ end // initial if (reset) begin icache_rd_valid_f <= 1'h0; end else begin - icache_rd_valid_f <= _T_758 & _T_760; + icache_rd_valid_f <= _T_768 & _T_770; end end always @(posedge io_active_clk or posedge reset) begin if (reset) begin icache_wr_valid_f <= 1'h0; end else begin - icache_wr_valid_f <= _T_653 & _T_763; + icache_wr_valid_f <= _T_663 & _T_773; end end always @(posedge io_csr_wr_clk or posedge reset) begin @@ -53546,38 +53557,38 @@ end // initial end always @(posedge io_active_clk or posedge reset) begin if (reset) begin - _T_862 <= 10'h0; + _T_872 <= 10'h0; end else if (wr_mtdata1_t_r_0) begin - _T_862 <= tdata_wrdata_r; + _T_872 <= tdata_wrdata_r; end else begin - _T_862 <= _T_833; + _T_872 <= _T_843; end end always @(posedge io_active_clk or posedge reset) begin if (reset) begin - _T_863 <= 10'h0; + _T_873 <= 10'h0; end else if (wr_mtdata1_t_r_1) begin - _T_863 <= tdata_wrdata_r; + _T_873 <= tdata_wrdata_r; end else begin - _T_863 <= _T_842; + _T_873 <= _T_852; end end always @(posedge io_active_clk or posedge reset) begin if (reset) begin - _T_864 <= 10'h0; + _T_874 <= 10'h0; end else if (wr_mtdata1_t_r_2) begin - _T_864 <= tdata_wrdata_r; + _T_874 <= tdata_wrdata_r; end else begin - _T_864 <= _T_851; + _T_874 <= _T_861; end end always @(posedge io_active_clk or posedge reset) begin if (reset) begin - _T_865 <= 10'h0; + _T_875 <= 10'h0; end else if (wr_mtdata1_t_r_3) begin - _T_865 <= tdata_wrdata_r; + _T_875 <= tdata_wrdata_r; end else begin - _T_865 <= _T_860; + _T_875 <= _T_870; end end always @(posedge rvclkhdr_22_io_l1clk or posedge reset) begin @@ -53612,7 +53623,7 @@ end // initial if (reset) begin mhpme3 <= 10'h0; end else if (wr_mhpme3_r) begin - if (_T_2282) begin + if (_T_2292) begin mhpme3 <= 10'h204; end else begin mhpme3 <= io_dec_csr_wrdata_r[9:0]; @@ -53623,7 +53634,7 @@ end // initial if (reset) begin mhpme4 <= 10'h0; end else if (wr_mhpme4_r) begin - if (_T_2282) begin + if (_T_2292) begin mhpme4 <= 10'h204; end else begin mhpme4 <= io_dec_csr_wrdata_r[9:0]; @@ -53634,7 +53645,7 @@ end // initial if (reset) begin mhpme5 <= 10'h0; end else if (wr_mhpme5_r) begin - if (_T_2282) begin + if (_T_2292) begin mhpme5 <= 10'h204; end else begin mhpme5 <= io_dec_csr_wrdata_r[9:0]; @@ -53645,7 +53656,7 @@ end // initial if (reset) begin mhpme6 <= 10'h0; end else if (wr_mhpme6_r) begin - if (_T_2282) begin + if (_T_2292) begin mhpme6 <= 10'h204; end else begin mhpme6 <= io_dec_csr_wrdata_r[9:0]; @@ -53656,28 +53667,28 @@ end // initial if (reset) begin mhpmc_inc_r_d1_0 <= 1'h0; end else begin - mhpmc_inc_r_d1_0 <= _T_1015 & _T_1295; + mhpmc_inc_r_d1_0 <= _T_1025 & _T_1305; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin mhpmc_inc_r_d1_1 <= 1'h0; end else begin - mhpmc_inc_r_d1_1 <= _T_1299 & _T_1579; + mhpmc_inc_r_d1_1 <= _T_1309 & _T_1589; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin mhpmc_inc_r_d1_2 <= 1'h0; end else begin - mhpmc_inc_r_d1_2 <= _T_1583 & _T_1863; + mhpmc_inc_r_d1_2 <= _T_1593 & _T_1873; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin mhpmc_inc_r_d1_3 <= 1'h0; end else begin - mhpmc_inc_r_d1_3 <= _T_1867 & _T_2147; + mhpmc_inc_r_d1_3 <= _T_1877 & _T_2157; end end always @(posedge io_free_clk or posedge reset) begin @@ -53761,30 +53772,30 @@ end // initial end always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin if (reset) begin - _T_2320 <= 1'h0; + _T_2330 <= 1'h0; end else begin - _T_2320 <= io_i0_valid_wb; + _T_2330 <= io_i0_valid_wb; end end always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin if (reset) begin - _T_2325 <= 1'h0; + _T_2335 <= 1'h0; end else begin - _T_2325 <= _T_2321 | _T_2323; + _T_2335 <= _T_2331 | _T_2333; end end always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin if (reset) begin - _T_2326 <= 5'h0; + _T_2336 <= 5'h0; end else begin - _T_2326 <= io_exc_cause_wb; + _T_2336 <= io_exc_cause_wb; end end always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin if (reset) begin - _T_2327 <= 1'h0; + _T_2337 <= 1'h0; end else begin - _T_2327 <= io_interrupt_valid_r_d1; + _T_2337 <= io_interrupt_valid_r_d1; end end endmodule @@ -54368,7 +54379,6 @@ module dec_tlu_ctl( output io_dec_tlu_misc_clk_override, output io_dec_tlu_dec_clk_override, output io_dec_tlu_lsu_clk_override, - output io_dec_tlu_bus_clk_override, output io_dec_tlu_pic_clk_override, output io_dec_tlu_dccm_clk_override, output io_dec_tlu_icm_clk_override, @@ -54409,6 +54419,7 @@ module dec_tlu_ctl( input io_tlu_busbuff_lsu_pmu_bus_error, input io_tlu_busbuff_lsu_pmu_bus_busy, output io_tlu_busbuff_dec_tlu_external_ldfwd_disable, + output io_tlu_busbuff_dec_tlu_wb_coalescing_disable, output io_tlu_busbuff_dec_tlu_sideeffect_posted_disable, input io_tlu_busbuff_lsu_imprecise_error_load_any, input io_tlu_busbuff_lsu_imprecise_error_store_any, @@ -54620,7 +54631,6 @@ module dec_tlu_ctl( wire csr_io_dec_tlu_misc_clk_override; // @[dec_tlu_ctl.scala 813:15] wire csr_io_dec_tlu_dec_clk_override; // @[dec_tlu_ctl.scala 813:15] wire csr_io_dec_tlu_lsu_clk_override; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_dec_tlu_bus_clk_override; // @[dec_tlu_ctl.scala 813:15] wire csr_io_dec_tlu_pic_clk_override; // @[dec_tlu_ctl.scala 813:15] wire csr_io_dec_tlu_dccm_clk_override; // @[dec_tlu_ctl.scala 813:15] wire csr_io_dec_tlu_icm_clk_override; // @[dec_tlu_ctl.scala 813:15] @@ -54643,6 +54653,7 @@ module dec_tlu_ctl( wire csr_io_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 813:15] wire csr_io_lsu_imprecise_error_store_any; // @[dec_tlu_ctl.scala 813:15] wire [31:0] csr_io_dec_tlu_mrac_ff; // @[dec_tlu_ctl.scala 813:15] + wire csr_io_dec_tlu_wb_coalescing_disable; // @[dec_tlu_ctl.scala 813:15] wire csr_io_dec_tlu_bpred_disable; // @[dec_tlu_ctl.scala 813:15] wire csr_io_dec_tlu_sideeffect_posted_disable; // @[dec_tlu_ctl.scala 813:15] wire csr_io_dec_tlu_core_ecc_disable; // @[dec_tlu_ctl.scala 813:15] @@ -55708,7 +55719,6 @@ module dec_tlu_ctl( .io_dec_tlu_misc_clk_override(csr_io_dec_tlu_misc_clk_override), .io_dec_tlu_dec_clk_override(csr_io_dec_tlu_dec_clk_override), .io_dec_tlu_lsu_clk_override(csr_io_dec_tlu_lsu_clk_override), - .io_dec_tlu_bus_clk_override(csr_io_dec_tlu_bus_clk_override), .io_dec_tlu_pic_clk_override(csr_io_dec_tlu_pic_clk_override), .io_dec_tlu_dccm_clk_override(csr_io_dec_tlu_dccm_clk_override), .io_dec_tlu_icm_clk_override(csr_io_dec_tlu_icm_clk_override), @@ -55731,6 +55741,7 @@ module dec_tlu_ctl( .io_lsu_imprecise_error_load_any(csr_io_lsu_imprecise_error_load_any), .io_lsu_imprecise_error_store_any(csr_io_lsu_imprecise_error_store_any), .io_dec_tlu_mrac_ff(csr_io_dec_tlu_mrac_ff), + .io_dec_tlu_wb_coalescing_disable(csr_io_dec_tlu_wb_coalescing_disable), .io_dec_tlu_bpred_disable(csr_io_dec_tlu_bpred_disable), .io_dec_tlu_sideeffect_posted_disable(csr_io_dec_tlu_sideeffect_posted_disable), .io_dec_tlu_core_ecc_disable(csr_io_dec_tlu_core_ecc_disable), @@ -56032,7 +56043,6 @@ module dec_tlu_ctl( assign io_dec_tlu_misc_clk_override = csr_io_dec_tlu_misc_clk_override; // @[dec_tlu_ctl.scala 885:40] assign io_dec_tlu_dec_clk_override = csr_io_dec_tlu_dec_clk_override; // @[dec_tlu_ctl.scala 886:40] assign io_dec_tlu_lsu_clk_override = csr_io_dec_tlu_lsu_clk_override; // @[dec_tlu_ctl.scala 888:40] - assign io_dec_tlu_bus_clk_override = csr_io_dec_tlu_bus_clk_override; // @[dec_tlu_ctl.scala 889:40] assign io_dec_tlu_pic_clk_override = csr_io_dec_tlu_pic_clk_override; // @[dec_tlu_ctl.scala 890:40] assign io_dec_tlu_dccm_clk_override = csr_io_dec_tlu_dccm_clk_override; // @[dec_tlu_ctl.scala 891:40] assign io_dec_tlu_icm_clk_override = csr_io_dec_tlu_icm_clk_override; // @[dec_tlu_ctl.scala 892:40] @@ -56057,6 +56067,7 @@ module dec_tlu_ctl( assign io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wr_valid = csr_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[dec_tlu_ctl.scala 877:44] assign io_tlu_mem_dec_tlu_core_ecc_disable = csr_io_dec_tlu_core_ecc_disable; // @[dec_tlu_ctl.scala 900:48] assign io_tlu_busbuff_dec_tlu_external_ldfwd_disable = csr_io_dec_tlu_external_ldfwd_disable; // @[dec_tlu_ctl.scala 901:52] + assign io_tlu_busbuff_dec_tlu_wb_coalescing_disable = csr_io_dec_tlu_wb_coalescing_disable; // @[dec_tlu_ctl.scala 897:52] assign io_tlu_busbuff_dec_tlu_sideeffect_posted_disable = csr_io_dec_tlu_sideeffect_posted_disable; // @[dec_tlu_ctl.scala 899:52] assign io_dec_pic_dec_tlu_meicurpl = csr_io_dec_tlu_meicurpl; // @[dec_tlu_ctl.scala 871:44] assign io_dec_pic_dec_tlu_meipt = csr_io_dec_tlu_meipt; // @[dec_tlu_ctl.scala 873:44] @@ -57930,7 +57941,6 @@ module dec( output [31:0] io_rv_trace_pkt_rv_i_tval_ip, output io_dec_tlu_misc_clk_override, output io_dec_tlu_lsu_clk_override, - output io_dec_tlu_bus_clk_override, output io_dec_tlu_pic_clk_override, output io_dec_tlu_dccm_clk_override, output io_dec_tlu_icm_clk_override, @@ -58068,6 +58078,7 @@ module dec( input io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error, input io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy, output io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable, + output io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable, output io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable, input io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any, input io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any, @@ -58475,7 +58486,6 @@ module dec( wire tlu_io_dec_tlu_misc_clk_override; // @[dec.scala 120:19] wire tlu_io_dec_tlu_dec_clk_override; // @[dec.scala 120:19] wire tlu_io_dec_tlu_lsu_clk_override; // @[dec.scala 120:19] - wire tlu_io_dec_tlu_bus_clk_override; // @[dec.scala 120:19] wire tlu_io_dec_tlu_pic_clk_override; // @[dec.scala 120:19] wire tlu_io_dec_tlu_dccm_clk_override; // @[dec.scala 120:19] wire tlu_io_dec_tlu_icm_clk_override; // @[dec.scala 120:19] @@ -58516,6 +58526,7 @@ module dec( wire tlu_io_tlu_busbuff_lsu_pmu_bus_error; // @[dec.scala 120:19] wire tlu_io_tlu_busbuff_lsu_pmu_bus_busy; // @[dec.scala 120:19] wire tlu_io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[dec.scala 120:19] + wire tlu_io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[dec.scala 120:19] wire tlu_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[dec.scala 120:19] wire tlu_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[dec.scala 120:19] wire tlu_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[dec.scala 120:19] @@ -58931,7 +58942,6 @@ module dec( .io_dec_tlu_misc_clk_override(tlu_io_dec_tlu_misc_clk_override), .io_dec_tlu_dec_clk_override(tlu_io_dec_tlu_dec_clk_override), .io_dec_tlu_lsu_clk_override(tlu_io_dec_tlu_lsu_clk_override), - .io_dec_tlu_bus_clk_override(tlu_io_dec_tlu_bus_clk_override), .io_dec_tlu_pic_clk_override(tlu_io_dec_tlu_pic_clk_override), .io_dec_tlu_dccm_clk_override(tlu_io_dec_tlu_dccm_clk_override), .io_dec_tlu_icm_clk_override(tlu_io_dec_tlu_icm_clk_override), @@ -58972,6 +58982,7 @@ module dec( .io_tlu_busbuff_lsu_pmu_bus_error(tlu_io_tlu_busbuff_lsu_pmu_bus_error), .io_tlu_busbuff_lsu_pmu_bus_busy(tlu_io_tlu_busbuff_lsu_pmu_bus_busy), .io_tlu_busbuff_dec_tlu_external_ldfwd_disable(tlu_io_tlu_busbuff_dec_tlu_external_ldfwd_disable), + .io_tlu_busbuff_dec_tlu_wb_coalescing_disable(tlu_io_tlu_busbuff_dec_tlu_wb_coalescing_disable), .io_tlu_busbuff_dec_tlu_sideeffect_posted_disable(tlu_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable), .io_tlu_busbuff_lsu_imprecise_error_load_any(tlu_io_tlu_busbuff_lsu_imprecise_error_load_any), .io_tlu_busbuff_lsu_imprecise_error_store_any(tlu_io_tlu_busbuff_lsu_imprecise_error_store_any), @@ -59070,7 +59081,6 @@ module dec( assign io_rv_trace_pkt_rv_i_tval_ip = tlu_io_dec_tlu_mtval_wb1; // @[dec.scala 294:32] assign io_dec_tlu_misc_clk_override = tlu_io_dec_tlu_misc_clk_override; // @[dec.scala 278:35] assign io_dec_tlu_lsu_clk_override = tlu_io_dec_tlu_lsu_clk_override; // @[dec.scala 280:36] - assign io_dec_tlu_bus_clk_override = tlu_io_dec_tlu_bus_clk_override; // @[dec.scala 281:36] assign io_dec_tlu_pic_clk_override = tlu_io_dec_tlu_pic_clk_override; // @[dec.scala 282:36] assign io_dec_tlu_dccm_clk_override = tlu_io_dec_tlu_dccm_clk_override; // @[dec.scala 283:36] assign io_dec_tlu_icm_clk_override = tlu_io_dec_tlu_icm_clk_override; // @[dec.scala 284:36] @@ -59158,6 +59168,7 @@ module dec( assign io_dec_exu_gpr_exu_gpr_i0_rs1_d = gpr_io_gpr_exu_gpr_i0_rs1_d; // @[dec.scala 201:22] assign io_dec_exu_gpr_exu_gpr_i0_rs2_d = gpr_io_gpr_exu_gpr_i0_rs2_d; // @[dec.scala 201:22] assign io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable = tlu_io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[dec.scala 222:26] + assign io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable = tlu_io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[dec.scala 222:26] assign io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable = tlu_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[dec.scala 222:26] assign io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty = tlu_io_tlu_dma_dec_tlu_dma_qos_prty; // @[dec.scala 206:18] assign io_dec_pic_dec_tlu_meicurpl = tlu_io_dec_pic_dec_tlu_meicurpl; // @[dec.scala 224:14] @@ -59407,6 +59418,7 @@ module dbg( input io_sb_axi_aw_ready, output io_sb_axi_aw_valid, output [31:0] io_sb_axi_aw_bits_addr, + output [3:0] io_sb_axi_aw_bits_region, output [2:0] io_sb_axi_aw_bits_size, input io_sb_axi_w_ready, output io_sb_axi_w_valid, @@ -59418,6 +59430,7 @@ module dbg( input io_sb_axi_ar_ready, output io_sb_axi_ar_valid, output [31:0] io_sb_axi_ar_bits_addr, + output [3:0] io_sb_axi_ar_bits_region, output [2:0] io_sb_axi_ar_bits_size, output io_sb_axi_r_ready, input io_sb_axi_r_valid, @@ -60010,6 +60023,7 @@ module dbg( assign io_dmi_reg_rdata = _T_467; // @[dbg.scala 325:20] assign io_sb_axi_aw_valid = _T_558 | _T_559; // @[dbg.scala 412:22] assign io_sb_axi_aw_bits_addr = sbaddress0_reg; // @[dbg.scala 413:26] + assign io_sb_axi_aw_bits_region = sbaddress0_reg[31:28]; // @[dbg.scala 418:28] assign io_sb_axi_aw_bits_size = sbcs_reg[19:17]; // @[dbg.scala 415:26] assign io_sb_axi_w_valid = _T_558 | _T_565; // @[dbg.scala 423:21] assign io_sb_axi_w_bits_data = _T_593 | _T_601; // @[dbg.scala 424:25] @@ -60017,6 +60031,7 @@ module dbg( assign io_sb_axi_b_ready = 1'h1; // @[dbg.scala 444:21] assign io_sb_axi_ar_valid = sb_state == 4'h3; // @[dbg.scala 433:22] assign io_sb_axi_ar_bits_addr = sbaddress0_reg; // @[dbg.scala 434:26] + assign io_sb_axi_ar_bits_region = sbaddress0_reg[31:28]; // @[dbg.scala 439:28] assign io_sb_axi_ar_bits_size = sbcs_reg[19:17]; // @[dbg.scala 436:26] assign io_sb_axi_r_ready = 1'h1; // @[dbg.scala 445:21] assign io_dbg_dec_dbg_ib_dbg_cmd_valid = _T_480 & io_dbg_dma_io_dma_dbg_ready; // @[dbg.scala 331:35] @@ -68176,6 +68191,7 @@ module lsu_bus_buffer( output io_tlu_busbuff_lsu_pmu_bus_error, output io_tlu_busbuff_lsu_pmu_bus_busy, input io_tlu_busbuff_dec_tlu_external_ldfwd_disable, + input io_tlu_busbuff_dec_tlu_wb_coalescing_disable, input io_tlu_busbuff_dec_tlu_sideeffect_posted_disable, output io_tlu_busbuff_lsu_imprecise_error_load_any, output io_tlu_busbuff_lsu_imprecise_error_store_any, @@ -68225,7 +68241,9 @@ module lsu_bus_buffer( output io_lsu_axi_aw_valid, output [2:0] io_lsu_axi_aw_bits_id, output [31:0] io_lsu_axi_aw_bits_addr, + output [3:0] io_lsu_axi_aw_bits_region, output [2:0] io_lsu_axi_aw_bits_size, + output [3:0] io_lsu_axi_aw_bits_cache, input io_lsu_axi_w_ready, output io_lsu_axi_w_valid, output [63:0] io_lsu_axi_w_bits_data, @@ -68238,7 +68256,9 @@ module lsu_bus_buffer( output io_lsu_axi_ar_valid, output [2:0] io_lsu_axi_ar_bits_id, output [31:0] io_lsu_axi_ar_bits_addr, + output [3:0] io_lsu_axi_ar_bits_region, output [2:0] io_lsu_axi_ar_bits_size, + output [3:0] io_lsu_axi_ar_bits_cache, output io_lsu_axi_r_ready, input io_lsu_axi_r_valid, input [2:0] io_lsu_axi_r_bits_id, @@ -68334,9 +68354,9 @@ module lsu_bus_buffer( reg [31:0] _RAND_75; reg [31:0] _RAND_76; reg [31:0] _RAND_77; - reg [63:0] _RAND_78; + reg [31:0] _RAND_78; reg [31:0] _RAND_79; - reg [31:0] _RAND_80; + reg [63:0] _RAND_80; reg [31:0] _RAND_81; reg [31:0] _RAND_82; reg [31:0] _RAND_83; @@ -68361,6 +68381,8 @@ module lsu_bus_buffer( reg [31:0] _RAND_102; reg [31:0] _RAND_103; reg [31:0] _RAND_104; + reg [31:0] _RAND_105; + reg [31:0] _RAND_106; `endif // RANDOMIZE_REG_INIT wire rvclkhdr_io_l1clk; // @[lib.scala 368:23] wire rvclkhdr_io_clk; // @[lib.scala 368:23] @@ -69034,26 +69056,74 @@ module lsu_bus_buffer( wire _T_854 = ~ibuf_byp; // @[lsu_bus_buffer.scala 208:56] wire ibuf_wr_en = _T_853 & _T_854; // @[lsu_bus_buffer.scala 208:54] wire _T_855 = ~ibuf_wr_en; // @[lsu_bus_buffer.scala 210:36] + reg [2:0] ibuf_timer; // @[lsu_bus_buffer.scala 253:55] + wire _T_864 = ibuf_timer == 3'h7; // @[lsu_bus_buffer.scala 216:62] + wire _T_865 = ibuf_wr_en | _T_864; // @[lsu_bus_buffer.scala 216:48] + wire _T_929 = _T_853 & io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 235:54] + wire _T_930 = _T_929 & ibuf_valid; // @[lsu_bus_buffer.scala 235:80] + wire _T_931 = _T_930 & ibuf_write; // @[lsu_bus_buffer.scala 235:93] + wire _T_934 = io_lsu_addr_r[31:2] == ibuf_addr[31:2]; // @[lsu_bus_buffer.scala 235:129] + wire _T_935 = _T_931 & _T_934; // @[lsu_bus_buffer.scala 235:106] + wire _T_936 = ~io_is_sideeffects_r; // @[lsu_bus_buffer.scala 235:152] + wire _T_937 = _T_935 & _T_936; // @[lsu_bus_buffer.scala 235:150] + wire _T_938 = ~io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_buffer.scala 235:175] + wire ibuf_merge_en = _T_937 & _T_938; // @[lsu_bus_buffer.scala 235:173] + wire ibuf_merge_in = ~io_ldst_dual_r; // @[lsu_bus_buffer.scala 236:20] + wire _T_866 = ibuf_merge_en & ibuf_merge_in; // @[lsu_bus_buffer.scala 216:98] + wire _T_867 = ~_T_866; // @[lsu_bus_buffer.scala 216:82] + wire _T_868 = _T_865 & _T_867; // @[lsu_bus_buffer.scala 216:80] + wire _T_869 = _T_868 | ibuf_byp; // @[lsu_bus_buffer.scala 217:5] wire _T_857 = ~io_lsu_busreq_r; // @[lsu_bus_buffer.scala 211:44] wire _T_858 = io_lsu_busreq_m & _T_857; // @[lsu_bus_buffer.scala 211:42] wire _T_859 = _T_858 & ibuf_valid; // @[lsu_bus_buffer.scala 211:61] wire _T_862 = ibuf_addr[31:2] != io_lsu_addr_m[31:2]; // @[lsu_bus_buffer.scala 211:120] wire _T_863 = io_lsu_pkt_m_bits_load | _T_862; // @[lsu_bus_buffer.scala 211:100] wire ibuf_force_drain = _T_859 & _T_863; // @[lsu_bus_buffer.scala 211:74] + wire _T_870 = _T_869 | ibuf_force_drain; // @[lsu_bus_buffer.scala 217:16] reg ibuf_sideeffect; // @[Reg.scala 27:20] - wire _T_856 = ibuf_valid & _T_855; // @[lsu_bus_buffer.scala 210:34] + wire _T_871 = _T_870 | ibuf_sideeffect; // @[lsu_bus_buffer.scala 217:35] + wire _T_872 = ~ibuf_write; // @[lsu_bus_buffer.scala 217:55] + wire _T_873 = _T_871 | _T_872; // @[lsu_bus_buffer.scala 217:53] + wire _T_874 = _T_873 | io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_buffer.scala 217:67] + wire ibuf_drain_vld = ibuf_valid & _T_874; // @[lsu_bus_buffer.scala 216:32] + wire _T_856 = ibuf_drain_vld & _T_855; // @[lsu_bus_buffer.scala 210:34] wire ibuf_rst = _T_856 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 210:49] reg [1:0] WrPtr1_r; // @[lsu_bus_buffer.scala 616:49] reg [1:0] WrPtr0_r; // @[lsu_bus_buffer.scala 615:49] reg [1:0] ibuf_tag; // @[Reg.scala 27:20] wire [1:0] ibuf_sz_in = {io_lsu_pkt_r_bits_word,io_lsu_pkt_r_bits_half}; // @[Cat.scala 29:58] + wire [3:0] _T_881 = ibuf_byteen | ldst_byteen_lo_r; // @[lsu_bus_buffer.scala 226:77] + wire [7:0] _T_889 = ldst_byteen_lo_r[0] ? store_data_lo_r[7:0] : ibuf_data[7:0]; // @[lsu_bus_buffer.scala 231:8] wire [7:0] _T_892 = io_ldst_dual_r ? store_data_hi_r[7:0] : store_data_lo_r[7:0]; // @[lsu_bus_buffer.scala 232:8] + wire [7:0] _T_893 = _T_866 ? _T_889 : _T_892; // @[lsu_bus_buffer.scala 230:46] + wire [7:0] _T_898 = ldst_byteen_lo_r[1] ? store_data_lo_r[15:8] : ibuf_data[15:8]; // @[lsu_bus_buffer.scala 231:8] wire [7:0] _T_901 = io_ldst_dual_r ? store_data_hi_r[15:8] : store_data_lo_r[15:8]; // @[lsu_bus_buffer.scala 232:8] + wire [7:0] _T_902 = _T_866 ? _T_898 : _T_901; // @[lsu_bus_buffer.scala 230:46] + wire [7:0] _T_907 = ldst_byteen_lo_r[2] ? store_data_lo_r[23:16] : ibuf_data[23:16]; // @[lsu_bus_buffer.scala 231:8] wire [7:0] _T_910 = io_ldst_dual_r ? store_data_hi_r[23:16] : store_data_lo_r[23:16]; // @[lsu_bus_buffer.scala 232:8] + wire [7:0] _T_911 = _T_866 ? _T_907 : _T_910; // @[lsu_bus_buffer.scala 230:46] + wire [7:0] _T_916 = ldst_byteen_lo_r[3] ? store_data_lo_r[31:24] : ibuf_data[31:24]; // @[lsu_bus_buffer.scala 231:8] wire [7:0] _T_919 = io_ldst_dual_r ? store_data_hi_r[31:24] : store_data_lo_r[31:24]; // @[lsu_bus_buffer.scala 232:8] - wire [23:0] _T_922 = {_T_919,_T_910,_T_901}; // @[Cat.scala 29:58] - wire [3:0] ibuf_byteen_out = {ibuf_byteen[3],ibuf_byteen[2],ibuf_byteen[1],ibuf_byteen[0]}; // @[Cat.scala 29:58] - wire [31:0] ibuf_data_out = {ibuf_data[31:24],ibuf_data[23:16],ibuf_data[15:8],ibuf_data[7:0]}; // @[Cat.scala 29:58] + wire [7:0] _T_920 = _T_866 ? _T_916 : _T_919; // @[lsu_bus_buffer.scala 230:46] + wire [23:0] _T_922 = {_T_920,_T_911,_T_902}; // @[Cat.scala 29:58] + wire _T_923 = ibuf_timer < 3'h7; // @[lsu_bus_buffer.scala 233:59] + wire [2:0] _T_926 = ibuf_timer + 3'h1; // @[lsu_bus_buffer.scala 233:93] + wire _T_941 = ~ibuf_merge_in; // @[lsu_bus_buffer.scala 237:65] + wire _T_942 = ibuf_merge_en & _T_941; // @[lsu_bus_buffer.scala 237:63] + wire _T_945 = ibuf_byteen[0] | ldst_byteen_lo_r[0]; // @[lsu_bus_buffer.scala 237:96] + wire _T_947 = _T_942 ? _T_945 : ibuf_byteen[0]; // @[lsu_bus_buffer.scala 237:48] + wire _T_952 = ibuf_byteen[1] | ldst_byteen_lo_r[1]; // @[lsu_bus_buffer.scala 237:96] + wire _T_954 = _T_942 ? _T_952 : ibuf_byteen[1]; // @[lsu_bus_buffer.scala 237:48] + wire _T_959 = ibuf_byteen[2] | ldst_byteen_lo_r[2]; // @[lsu_bus_buffer.scala 237:96] + wire _T_961 = _T_942 ? _T_959 : ibuf_byteen[2]; // @[lsu_bus_buffer.scala 237:48] + wire _T_966 = ibuf_byteen[3] | ldst_byteen_lo_r[3]; // @[lsu_bus_buffer.scala 237:96] + wire _T_968 = _T_942 ? _T_966 : ibuf_byteen[3]; // @[lsu_bus_buffer.scala 237:48] + wire [3:0] ibuf_byteen_out = {_T_968,_T_961,_T_954,_T_947}; // @[Cat.scala 29:58] + wire [7:0] _T_978 = _T_942 ? _T_889 : ibuf_data[7:0]; // @[lsu_bus_buffer.scala 238:45] + wire [7:0] _T_986 = _T_942 ? _T_898 : ibuf_data[15:8]; // @[lsu_bus_buffer.scala 238:45] + wire [7:0] _T_994 = _T_942 ? _T_907 : ibuf_data[23:16]; // @[lsu_bus_buffer.scala 238:45] + wire [7:0] _T_1002 = _T_942 ? _T_916 : ibuf_data[31:24]; // @[lsu_bus_buffer.scala 238:45] + wire [31:0] ibuf_data_out = {_T_1002,_T_994,_T_986,_T_978}; // @[Cat.scala 29:58] wire _T_1005 = ibuf_wr_en | ibuf_valid; // @[lsu_bus_buffer.scala 240:58] wire _T_1006 = ~ibuf_rst; // @[lsu_bus_buffer.scala 240:93] reg [1:0] ibuf_dualtag; // @[Reg.scala 27:20] @@ -69062,10 +69132,24 @@ module lsu_bus_buffer( reg ibuf_nomerge; // @[Reg.scala 27:20] reg ibuf_unsign; // @[Reg.scala 27:20] reg [1:0] ibuf_sz; // @[Reg.scala 27:20] + wire _T_4446 = buf_write[3] & _T_2621; // @[lsu_bus_buffer.scala 522:64] wire _T_4447 = ~buf_cmd_state_bus_en_3; // @[lsu_bus_buffer.scala 522:91] + wire _T_4448 = _T_4446 & _T_4447; // @[lsu_bus_buffer.scala 522:89] + wire _T_4441 = buf_write[2] & _T_2616; // @[lsu_bus_buffer.scala 522:64] wire _T_4442 = ~buf_cmd_state_bus_en_2; // @[lsu_bus_buffer.scala 522:91] + wire _T_4443 = _T_4441 & _T_4442; // @[lsu_bus_buffer.scala 522:89] + wire [1:0] _T_4449 = _T_4448 + _T_4443; // @[lsu_bus_buffer.scala 522:142] + wire _T_4436 = buf_write[1] & _T_2611; // @[lsu_bus_buffer.scala 522:64] wire _T_4437 = ~buf_cmd_state_bus_en_1; // @[lsu_bus_buffer.scala 522:91] + wire _T_4438 = _T_4436 & _T_4437; // @[lsu_bus_buffer.scala 522:89] + wire [1:0] _GEN_362 = {{1'd0}, _T_4438}; // @[lsu_bus_buffer.scala 522:142] + wire [2:0] _T_4450 = _T_4449 + _GEN_362; // @[lsu_bus_buffer.scala 522:142] + wire _T_4431 = buf_write[0] & _T_2606; // @[lsu_bus_buffer.scala 522:64] wire _T_4432 = ~buf_cmd_state_bus_en_0; // @[lsu_bus_buffer.scala 522:91] + wire _T_4433 = _T_4431 & _T_4432; // @[lsu_bus_buffer.scala 522:89] + wire [2:0] _GEN_363 = {{2'd0}, _T_4433}; // @[lsu_bus_buffer.scala 522:142] + wire [3:0] buf_numvld_wrcmd_any = _T_4450 + _GEN_363; // @[lsu_bus_buffer.scala 522:142] + wire _T_1016 = buf_numvld_wrcmd_any == 4'h1; // @[lsu_bus_buffer.scala 263:43] wire _T_4463 = _T_2621 & _T_4447; // @[lsu_bus_buffer.scala 523:73] wire _T_4460 = _T_2616 & _T_4442; // @[lsu_bus_buffer.scala 523:73] wire [1:0] _T_4464 = _T_4463 + _T_4460; // @[lsu_bus_buffer.scala 523:126] @@ -69076,6 +69160,11 @@ module lsu_bus_buffer( wire [2:0] _GEN_365 = {{2'd0}, _T_4454}; // @[lsu_bus_buffer.scala 523:126] wire [3:0] buf_numvld_cmd_any = _T_4465 + _GEN_365; // @[lsu_bus_buffer.scala 523:126] wire _T_1017 = buf_numvld_cmd_any == 4'h1; // @[lsu_bus_buffer.scala 263:72] + wire _T_1018 = _T_1016 & _T_1017; // @[lsu_bus_buffer.scala 263:51] + reg [2:0] obuf_wr_timer; // @[lsu_bus_buffer.scala 361:54] + wire _T_1019 = obuf_wr_timer != 3'h7; // @[lsu_bus_buffer.scala 263:97] + wire _T_1020 = _T_1018 & _T_1019; // @[lsu_bus_buffer.scala 263:80] + wire _T_1022 = _T_1020 & _T_938; // @[lsu_bus_buffer.scala 263:114] wire _T_1979 = |buf_age_3; // @[lsu_bus_buffer.scala 378:58] wire _T_1980 = ~_T_1979; // @[lsu_bus_buffer.scala 378:45] wire _T_1982 = _T_1980 & _T_2621; // @[lsu_bus_buffer.scala 378:63] @@ -69110,9 +69199,18 @@ module lsu_bus_buffer( wire _T_1025 = CmdPtr0 == 2'h2; // @[lsu_bus_buffer.scala 264:114] wire _T_1026 = CmdPtr0 == 2'h3; // @[lsu_bus_buffer.scala 264:114] reg buf_nomerge_0; // @[Reg.scala 27:20] + wire _T_1027 = _T_1023 & buf_nomerge_0; // @[Mux.scala 27:72] reg buf_nomerge_1; // @[Reg.scala 27:20] + wire _T_1028 = _T_1024 & buf_nomerge_1; // @[Mux.scala 27:72] reg buf_nomerge_2; // @[Reg.scala 27:20] + wire _T_1029 = _T_1025 & buf_nomerge_2; // @[Mux.scala 27:72] reg buf_nomerge_3; // @[Reg.scala 27:20] + wire _T_1030 = _T_1026 & buf_nomerge_3; // @[Mux.scala 27:72] + wire _T_1031 = _T_1027 | _T_1028; // @[Mux.scala 27:72] + wire _T_1032 = _T_1031 | _T_1029; // @[Mux.scala 27:72] + wire _T_1033 = _T_1032 | _T_1030; // @[Mux.scala 27:72] + wire _T_1035 = ~_T_1033; // @[lsu_bus_buffer.scala 264:31] + wire _T_1036 = _T_1022 & _T_1035; // @[lsu_bus_buffer.scala 264:29] reg _T_4330; // @[Reg.scala 27:20] reg _T_4327; // @[Reg.scala 27:20] reg _T_4324; // @[Reg.scala 27:20] @@ -69126,6 +69224,7 @@ module lsu_bus_buffer( wire _T_1050 = _T_1049 | _T_1047; // @[Mux.scala 27:72] wire _T_1051 = _T_1050 | _T_1048; // @[Mux.scala 27:72] wire _T_1053 = ~_T_1051; // @[lsu_bus_buffer.scala 265:5] + wire _T_1054 = _T_1036 & _T_1053; // @[lsu_bus_buffer.scala 264:140] wire _T_1065 = _T_858 & _T_852; // @[lsu_bus_buffer.scala 267:58] wire _T_1067 = _T_1065 & _T_1017; // @[lsu_bus_buffer.scala 267:72] wire [29:0] _T_1077 = _T_1023 ? buf_addr_0[31:2] : 30'h0; // @[Mux.scala 27:72] @@ -69137,6 +69236,12 @@ module lsu_bus_buffer( wire [29:0] _T_1083 = _T_1082 | _T_1080; // @[Mux.scala 27:72] wire _T_1085 = io_lsu_addr_m[31:2] != _T_1083; // @[lsu_bus_buffer.scala 267:123] wire obuf_force_wr_en = _T_1067 & _T_1085; // @[lsu_bus_buffer.scala 267:101] + wire _T_1055 = ~obuf_force_wr_en; // @[lsu_bus_buffer.scala 265:119] + wire obuf_wr_wait = _T_1054 & _T_1055; // @[lsu_bus_buffer.scala 265:117] + wire _T_1056 = |buf_numvld_cmd_any; // @[lsu_bus_buffer.scala 266:75] + wire _T_1057 = obuf_wr_timer < 3'h7; // @[lsu_bus_buffer.scala 266:95] + wire _T_1058 = _T_1056 & _T_1057; // @[lsu_bus_buffer.scala 266:79] + wire [2:0] _T_1060 = obuf_wr_timer + 3'h1; // @[lsu_bus_buffer.scala 266:123] wire _T_4482 = buf_state_3 == 3'h1; // @[lsu_bus_buffer.scala 524:63] wire _T_4486 = _T_4482 | _T_4463; // @[lsu_bus_buffer.scala 524:74] wire _T_4477 = buf_state_2 == 3'h1; // @[lsu_bus_buffer.scala 524:63] @@ -69293,6 +69398,8 @@ module lsu_bus_buffer( reg obuf_nosend; // @[Reg.scala 27:20] wire _T_1233 = _T_1232 | obuf_nosend; // @[lsu_bus_buffer.scala 288:60] wire _T_1234 = _T_1230 & _T_1233; // @[lsu_bus_buffer.scala 288:29] + wire _T_1235 = ~obuf_wr_wait; // @[lsu_bus_buffer.scala 288:77] + wire _T_1236 = _T_1234 & _T_1235; // @[lsu_bus_buffer.scala 288:75] reg [31:0] obuf_addr; // @[lib.scala 374:16] wire _T_4804 = obuf_addr[31:3] == buf_addr_0[31:3]; // @[lsu_bus_buffer.scala 554:56] wire _T_4805 = obuf_valid & _T_4804; // @[lsu_bus_buffer.scala 554:38] @@ -69330,7 +69437,7 @@ module lsu_bus_buffer( wire _T_4851 = _T_4790 & _T_4847; // @[Mux.scala 27:72] wire bus_addr_match_pending = _T_4853 | _T_4851; // @[Mux.scala 27:72] wire _T_1239 = ~bus_addr_match_pending; // @[lsu_bus_buffer.scala 288:118] - wire _T_1240 = _T_1234 & _T_1239; // @[lsu_bus_buffer.scala 288:116] + wire _T_1240 = _T_1236 & _T_1239; // @[lsu_bus_buffer.scala 288:116] wire obuf_wr_en = _T_1240 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 288:142] wire _T_1242 = obuf_valid & obuf_nosend; // @[lsu_bus_buffer.scala 290:47] wire bus_wcmd_sent = io_lsu_axi_aw_valid & io_lsu_axi_aw_ready; // @[lsu_bus_buffer.scala 557:40] @@ -69586,7 +69693,6 @@ module lsu_bus_buffer( wire _T_1885 = _T_1875 & _T_1884; // @[lsu_bus_buffer.scala 364:76] wire _T_1886 = buf_state_3 == 3'h0; // @[lsu_bus_buffer.scala 364:65] wire _T_1887 = ibuf_tag == 2'h3; // @[lsu_bus_buffer.scala 365:30] - wire _T_1888 = ibuf_valid & _T_1887; // @[lsu_bus_buffer.scala 365:19] wire _T_1889 = WrPtr0_r == 2'h3; // @[lsu_bus_buffer.scala 366:18] wire _T_1890 = WrPtr1_r == 2'h3; // @[lsu_bus_buffer.scala 366:57] wire [1:0] _T_1898 = _T_1885 ? 2'h2 : 2'h3; // @[Mux.scala 98:16] @@ -69662,15 +69768,17 @@ module lsu_bus_buffer( wire _T_2125 = _T_2123 | _T_2104[7]; // @[lsu_bus_buffer.scala 386:104] wire [2:0] _T_2127 = {_T_2111,_T_2118,_T_2125}; // @[Cat.scala 29:58] wire _T_3532 = ibuf_byp | io_ldst_dual_r; // @[lsu_bus_buffer.scala 444:77] + wire _T_3533 = ~ibuf_merge_en; // @[lsu_bus_buffer.scala 444:97] + wire _T_3534 = _T_3532 & _T_3533; // @[lsu_bus_buffer.scala 444:95] wire _T_3535 = 2'h0 == WrPtr0_r; // @[lsu_bus_buffer.scala 444:117] - wire _T_3536 = _T_3532 & _T_3535; // @[lsu_bus_buffer.scala 444:112] + wire _T_3536 = _T_3534 & _T_3535; // @[lsu_bus_buffer.scala 444:112] wire _T_3537 = ibuf_byp & io_ldst_dual_r; // @[lsu_bus_buffer.scala 444:144] wire _T_3538 = 2'h0 == WrPtr1_r; // @[lsu_bus_buffer.scala 444:166] wire _T_3539 = _T_3537 & _T_3538; // @[lsu_bus_buffer.scala 444:161] wire _T_3540 = _T_3536 | _T_3539; // @[lsu_bus_buffer.scala 444:132] wire _T_3541 = _T_853 & _T_3540; // @[lsu_bus_buffer.scala 444:63] wire _T_3542 = 2'h0 == ibuf_tag; // @[lsu_bus_buffer.scala 444:206] - wire _T_3543 = ibuf_valid & _T_3542; // @[lsu_bus_buffer.scala 444:201] + wire _T_3543 = ibuf_drain_vld & _T_3542; // @[lsu_bus_buffer.scala 444:201] wire _T_3544 = _T_3541 | _T_3543; // @[lsu_bus_buffer.scala 444:183] wire _T_3554 = io_lsu_bus_clk_en | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 451:46] wire _T_3589 = 3'h3 == buf_state_0; // @[Conditional.scala 37:30] @@ -69738,7 +69846,7 @@ module lsu_bus_buffer( wire _GEN_64 = _T_3551 ? _T_3554 : _GEN_54; // @[Conditional.scala 39:67] wire buf_state_en_0 = _T_3528 ? _T_3544 : _GEN_64; // @[Conditional.scala 40:58] wire _T_2129 = _T_1853 & buf_state_en_0; // @[lsu_bus_buffer.scala 406:94] - wire _T_2135 = ibuf_valid & io_lsu_busreq_r; // @[lsu_bus_buffer.scala 408:23] + wire _T_2135 = ibuf_drain_vld & io_lsu_busreq_r; // @[lsu_bus_buffer.scala 408:23] wire _T_2137 = _T_2135 & _T_3532; // @[lsu_bus_buffer.scala 408:41] wire _T_2139 = _T_2137 & _T_1856; // @[lsu_bus_buffer.scala 408:71] wire _T_2141 = _T_2139 & _T_1854; // @[lsu_bus_buffer.scala 408:92] @@ -69770,13 +69878,13 @@ module lsu_bus_buffer( wire _T_2227 = _T_2225 | buf_age_0[3]; // @[lsu_bus_buffer.scala 409:97] wire [2:0] _T_2229 = {_T_2227,_T_2202,_T_2177}; // @[Cat.scala 29:58] wire _T_3728 = 2'h1 == WrPtr0_r; // @[lsu_bus_buffer.scala 444:117] - wire _T_3729 = _T_3532 & _T_3728; // @[lsu_bus_buffer.scala 444:112] + wire _T_3729 = _T_3534 & _T_3728; // @[lsu_bus_buffer.scala 444:112] wire _T_3731 = 2'h1 == WrPtr1_r; // @[lsu_bus_buffer.scala 444:166] wire _T_3732 = _T_3537 & _T_3731; // @[lsu_bus_buffer.scala 444:161] wire _T_3733 = _T_3729 | _T_3732; // @[lsu_bus_buffer.scala 444:132] wire _T_3734 = _T_853 & _T_3733; // @[lsu_bus_buffer.scala 444:63] wire _T_3735 = 2'h1 == ibuf_tag; // @[lsu_bus_buffer.scala 444:206] - wire _T_3736 = ibuf_valid & _T_3735; // @[lsu_bus_buffer.scala 444:201] + wire _T_3736 = ibuf_drain_vld & _T_3735; // @[lsu_bus_buffer.scala 444:201] wire _T_3737 = _T_3734 | _T_3736; // @[lsu_bus_buffer.scala 444:183] wire _T_3782 = 3'h3 == buf_state_1; // @[Conditional.scala 37:30] wire _T_3827 = io_lsu_axi_b_bits_id == 3'h1; // @[lsu_bus_buffer.scala 469:73] @@ -69860,13 +69968,13 @@ module lsu_bus_buffer( wire _T_2329 = _T_2327 | buf_age_1[3]; // @[lsu_bus_buffer.scala 409:97] wire [2:0] _T_2331 = {_T_2329,_T_2304,_T_2279}; // @[Cat.scala 29:58] wire _T_3921 = 2'h2 == WrPtr0_r; // @[lsu_bus_buffer.scala 444:117] - wire _T_3922 = _T_3532 & _T_3921; // @[lsu_bus_buffer.scala 444:112] + wire _T_3922 = _T_3534 & _T_3921; // @[lsu_bus_buffer.scala 444:112] wire _T_3924 = 2'h2 == WrPtr1_r; // @[lsu_bus_buffer.scala 444:166] wire _T_3925 = _T_3537 & _T_3924; // @[lsu_bus_buffer.scala 444:161] wire _T_3926 = _T_3922 | _T_3925; // @[lsu_bus_buffer.scala 444:132] wire _T_3927 = _T_853 & _T_3926; // @[lsu_bus_buffer.scala 444:63] wire _T_3928 = 2'h2 == ibuf_tag; // @[lsu_bus_buffer.scala 444:206] - wire _T_3929 = ibuf_valid & _T_3928; // @[lsu_bus_buffer.scala 444:201] + wire _T_3929 = ibuf_drain_vld & _T_3928; // @[lsu_bus_buffer.scala 444:201] wire _T_3930 = _T_3927 | _T_3929; // @[lsu_bus_buffer.scala 444:183] wire _T_3975 = 3'h3 == buf_state_2; // @[Conditional.scala 37:30] wire _T_4020 = io_lsu_axi_b_bits_id == 3'h2; // @[lsu_bus_buffer.scala 469:73] @@ -69950,13 +70058,13 @@ module lsu_bus_buffer( wire _T_2431 = _T_2429 | buf_age_2[3]; // @[lsu_bus_buffer.scala 409:97] wire [2:0] _T_2433 = {_T_2431,_T_2406,_T_2381}; // @[Cat.scala 29:58] wire _T_4114 = 2'h3 == WrPtr0_r; // @[lsu_bus_buffer.scala 444:117] - wire _T_4115 = _T_3532 & _T_4114; // @[lsu_bus_buffer.scala 444:112] + wire _T_4115 = _T_3534 & _T_4114; // @[lsu_bus_buffer.scala 444:112] wire _T_4117 = 2'h3 == WrPtr1_r; // @[lsu_bus_buffer.scala 444:166] wire _T_4118 = _T_3537 & _T_4117; // @[lsu_bus_buffer.scala 444:161] wire _T_4119 = _T_4115 | _T_4118; // @[lsu_bus_buffer.scala 444:132] wire _T_4120 = _T_853 & _T_4119; // @[lsu_bus_buffer.scala 444:63] wire _T_4121 = 2'h3 == ibuf_tag; // @[lsu_bus_buffer.scala 444:206] - wire _T_4122 = ibuf_valid & _T_4121; // @[lsu_bus_buffer.scala 444:201] + wire _T_4122 = ibuf_drain_vld & _T_4121; // @[lsu_bus_buffer.scala 444:201] wire _T_4123 = _T_4120 | _T_4122; // @[lsu_bus_buffer.scala 444:183] wire _T_4168 = 3'h3 == buf_state_3; // @[Conditional.scala 37:30] wire _T_4213 = io_lsu_axi_b_bits_id == 3'h3; // @[lsu_bus_buffer.scala 469:73] @@ -70151,7 +70259,11 @@ module lsu_bus_buffer( wire _T_3213 = buf_rspage_set_3[2] | buf_rspage_3[2]; // @[lsu_bus_buffer.scala 420:88] wire _T_3216 = buf_rspage_set_3[3] | buf_rspage_3[3]; // @[lsu_bus_buffer.scala 420:88] wire [2:0] _T_3218 = {_T_3216,_T_3213,_T_3210}; // @[Cat.scala 29:58] - wire [3:0] ibuf_drainvec_vld = {_T_1888,_T_1877,_T_1866,_T_1855}; // @[Cat.scala 29:58] + wire _T_3329 = ibuf_drain_vld & _T_1854; // @[lsu_bus_buffer.scala 426:63] + wire _T_3331 = ibuf_drain_vld & _T_1865; // @[lsu_bus_buffer.scala 426:63] + wire _T_3333 = ibuf_drain_vld & _T_1876; // @[lsu_bus_buffer.scala 426:63] + wire _T_3335 = ibuf_drain_vld & _T_1887; // @[lsu_bus_buffer.scala 426:63] + wire [3:0] ibuf_drainvec_vld = {_T_3335,_T_3333,_T_3331,_T_3329}; // @[Cat.scala 29:58] wire _T_3343 = _T_3537 & _T_1857; // @[lsu_bus_buffer.scala 428:35] wire _T_3352 = _T_3537 & _T_1868; // @[lsu_bus_buffer.scala 428:35] wire _T_3361 = _T_3537 & _T_1879; // @[lsu_bus_buffer.scala 428:35] @@ -70774,7 +70886,9 @@ module lsu_bus_buffer( assign io_lsu_axi_aw_valid = _T_4876 & _T_1239; // @[lsu_bus_buffer.scala 569:23] assign io_lsu_axi_aw_bits_id = {{1'd0}, _T_1848}; // @[lsu_bus_buffer.scala 570:25] assign io_lsu_axi_aw_bits_addr = obuf_sideeffect ? obuf_addr : _T_4880; // @[lsu_bus_buffer.scala 571:27] + assign io_lsu_axi_aw_bits_region = obuf_addr[31:28]; // @[lsu_bus_buffer.scala 575:29] assign io_lsu_axi_aw_bits_size = obuf_sideeffect ? _T_4882 : 3'h3; // @[lsu_bus_buffer.scala 572:27] + assign io_lsu_axi_aw_bits_cache = obuf_sideeffect ? 4'h0 : 4'hf; // @[lsu_bus_buffer.scala 574:28] assign io_lsu_axi_w_valid = _T_4888 & _T_1239; // @[lsu_bus_buffer.scala 581:22] assign io_lsu_axi_w_bits_data = obuf_data; // @[lsu_bus_buffer.scala 583:26] assign io_lsu_axi_w_bits_strb = obuf_byteen & _T_4892; // @[lsu_bus_buffer.scala 582:26] @@ -70782,7 +70896,9 @@ module lsu_bus_buffer( assign io_lsu_axi_ar_valid = _T_4897 & _T_1239; // @[lsu_bus_buffer.scala 586:23] assign io_lsu_axi_ar_bits_id = {{1'd0}, _T_1848}; // @[lsu_bus_buffer.scala 587:25] assign io_lsu_axi_ar_bits_addr = obuf_sideeffect ? obuf_addr : _T_4880; // @[lsu_bus_buffer.scala 588:27] + assign io_lsu_axi_ar_bits_region = obuf_addr[31:28]; // @[lsu_bus_buffer.scala 592:29] assign io_lsu_axi_ar_bits_size = obuf_sideeffect ? _T_4882 : 3'h3; // @[lsu_bus_buffer.scala 589:27] + assign io_lsu_axi_ar_bits_cache = obuf_sideeffect ? 4'h0 : 4'hf; // @[lsu_bus_buffer.scala 591:28] assign io_lsu_axi_r_ready = 1'h1; // @[lsu_bus_buffer.scala 598:22] assign io_lsu_busreq_r = _T_4987; // @[lsu_bus_buffer.scala 617:19] assign io_lsu_bus_buffer_pend_any = |buf_numvld_pend_any; // @[lsu_bus_buffer.scala 526:30] @@ -70932,147 +71048,151 @@ initial begin _RAND_33 = {1{`RANDOM}}; ibuf_data = _RAND_33[31:0]; _RAND_34 = {1{`RANDOM}}; - ibuf_sideeffect = _RAND_34[0:0]; + ibuf_timer = _RAND_34[2:0]; _RAND_35 = {1{`RANDOM}}; - WrPtr1_r = _RAND_35[1:0]; + ibuf_sideeffect = _RAND_35[0:0]; _RAND_36 = {1{`RANDOM}}; - WrPtr0_r = _RAND_36[1:0]; + WrPtr1_r = _RAND_36[1:0]; _RAND_37 = {1{`RANDOM}}; - ibuf_tag = _RAND_37[1:0]; + WrPtr0_r = _RAND_37[1:0]; _RAND_38 = {1{`RANDOM}}; - ibuf_dualtag = _RAND_38[1:0]; + ibuf_tag = _RAND_38[1:0]; _RAND_39 = {1{`RANDOM}}; - ibuf_dual = _RAND_39[0:0]; + ibuf_dualtag = _RAND_39[1:0]; _RAND_40 = {1{`RANDOM}}; - ibuf_samedw = _RAND_40[0:0]; + ibuf_dual = _RAND_40[0:0]; _RAND_41 = {1{`RANDOM}}; - ibuf_nomerge = _RAND_41[0:0]; + ibuf_samedw = _RAND_41[0:0]; _RAND_42 = {1{`RANDOM}}; - ibuf_unsign = _RAND_42[0:0]; + ibuf_nomerge = _RAND_42[0:0]; _RAND_43 = {1{`RANDOM}}; - ibuf_sz = _RAND_43[1:0]; + ibuf_unsign = _RAND_43[0:0]; _RAND_44 = {1{`RANDOM}}; - buf_nomerge_0 = _RAND_44[0:0]; + ibuf_sz = _RAND_44[1:0]; _RAND_45 = {1{`RANDOM}}; - buf_nomerge_1 = _RAND_45[0:0]; + obuf_wr_timer = _RAND_45[2:0]; _RAND_46 = {1{`RANDOM}}; - buf_nomerge_2 = _RAND_46[0:0]; + buf_nomerge_0 = _RAND_46[0:0]; _RAND_47 = {1{`RANDOM}}; - buf_nomerge_3 = _RAND_47[0:0]; + buf_nomerge_1 = _RAND_47[0:0]; _RAND_48 = {1{`RANDOM}}; - _T_4330 = _RAND_48[0:0]; + buf_nomerge_2 = _RAND_48[0:0]; _RAND_49 = {1{`RANDOM}}; - _T_4327 = _RAND_49[0:0]; + buf_nomerge_3 = _RAND_49[0:0]; _RAND_50 = {1{`RANDOM}}; - _T_4324 = _RAND_50[0:0]; + _T_4330 = _RAND_50[0:0]; _RAND_51 = {1{`RANDOM}}; - _T_4321 = _RAND_51[0:0]; + _T_4327 = _RAND_51[0:0]; _RAND_52 = {1{`RANDOM}}; - obuf_sideeffect = _RAND_52[0:0]; + _T_4324 = _RAND_52[0:0]; _RAND_53 = {1{`RANDOM}}; - buf_dual_3 = _RAND_53[0:0]; + _T_4321 = _RAND_53[0:0]; _RAND_54 = {1{`RANDOM}}; - buf_dual_2 = _RAND_54[0:0]; + obuf_sideeffect = _RAND_54[0:0]; _RAND_55 = {1{`RANDOM}}; - buf_dual_1 = _RAND_55[0:0]; + buf_dual_3 = _RAND_55[0:0]; _RAND_56 = {1{`RANDOM}}; - buf_dual_0 = _RAND_56[0:0]; + buf_dual_2 = _RAND_56[0:0]; _RAND_57 = {1{`RANDOM}}; - buf_samedw_3 = _RAND_57[0:0]; + buf_dual_1 = _RAND_57[0:0]; _RAND_58 = {1{`RANDOM}}; - buf_samedw_2 = _RAND_58[0:0]; + buf_dual_0 = _RAND_58[0:0]; _RAND_59 = {1{`RANDOM}}; - buf_samedw_1 = _RAND_59[0:0]; + buf_samedw_3 = _RAND_59[0:0]; _RAND_60 = {1{`RANDOM}}; - buf_samedw_0 = _RAND_60[0:0]; + buf_samedw_2 = _RAND_60[0:0]; _RAND_61 = {1{`RANDOM}}; - obuf_write = _RAND_61[0:0]; + buf_samedw_1 = _RAND_61[0:0]; _RAND_62 = {1{`RANDOM}}; - obuf_cmd_done = _RAND_62[0:0]; + buf_samedw_0 = _RAND_62[0:0]; _RAND_63 = {1{`RANDOM}}; - obuf_data_done = _RAND_63[0:0]; + obuf_write = _RAND_63[0:0]; _RAND_64 = {1{`RANDOM}}; - obuf_nosend = _RAND_64[0:0]; + obuf_cmd_done = _RAND_64[0:0]; _RAND_65 = {1{`RANDOM}}; - obuf_addr = _RAND_65[31:0]; + obuf_data_done = _RAND_65[0:0]; _RAND_66 = {1{`RANDOM}}; - buf_sz_0 = _RAND_66[1:0]; + obuf_nosend = _RAND_66[0:0]; _RAND_67 = {1{`RANDOM}}; - buf_sz_1 = _RAND_67[1:0]; + obuf_addr = _RAND_67[31:0]; _RAND_68 = {1{`RANDOM}}; - buf_sz_2 = _RAND_68[1:0]; + buf_sz_0 = _RAND_68[1:0]; _RAND_69 = {1{`RANDOM}}; - buf_sz_3 = _RAND_69[1:0]; + buf_sz_1 = _RAND_69[1:0]; _RAND_70 = {1{`RANDOM}}; - obuf_rdrsp_pend = _RAND_70[0:0]; + buf_sz_2 = _RAND_70[1:0]; _RAND_71 = {1{`RANDOM}}; - obuf_rdrsp_tag = _RAND_71[2:0]; + buf_sz_3 = _RAND_71[1:0]; _RAND_72 = {1{`RANDOM}}; - buf_dualhi_3 = _RAND_72[0:0]; + obuf_rdrsp_pend = _RAND_72[0:0]; _RAND_73 = {1{`RANDOM}}; - buf_dualhi_2 = _RAND_73[0:0]; + obuf_rdrsp_tag = _RAND_73[2:0]; _RAND_74 = {1{`RANDOM}}; - buf_dualhi_1 = _RAND_74[0:0]; + buf_dualhi_3 = _RAND_74[0:0]; _RAND_75 = {1{`RANDOM}}; - buf_dualhi_0 = _RAND_75[0:0]; + buf_dualhi_2 = _RAND_75[0:0]; _RAND_76 = {1{`RANDOM}}; - obuf_sz = _RAND_76[1:0]; + buf_dualhi_1 = _RAND_76[0:0]; _RAND_77 = {1{`RANDOM}}; - obuf_byteen = _RAND_77[7:0]; - _RAND_78 = {2{`RANDOM}}; - obuf_data = _RAND_78[63:0]; + buf_dualhi_0 = _RAND_77[0:0]; + _RAND_78 = {1{`RANDOM}}; + obuf_sz = _RAND_78[1:0]; _RAND_79 = {1{`RANDOM}}; - buf_rspageQ_0 = _RAND_79[3:0]; - _RAND_80 = {1{`RANDOM}}; - buf_rspageQ_1 = _RAND_80[3:0]; + obuf_byteen = _RAND_79[7:0]; + _RAND_80 = {2{`RANDOM}}; + obuf_data = _RAND_80[63:0]; _RAND_81 = {1{`RANDOM}}; - buf_rspageQ_2 = _RAND_81[3:0]; + buf_rspageQ_0 = _RAND_81[3:0]; _RAND_82 = {1{`RANDOM}}; - buf_rspageQ_3 = _RAND_82[3:0]; + buf_rspageQ_1 = _RAND_82[3:0]; _RAND_83 = {1{`RANDOM}}; - _T_4307 = _RAND_83[0:0]; + buf_rspageQ_2 = _RAND_83[3:0]; _RAND_84 = {1{`RANDOM}}; - _T_4305 = _RAND_84[0:0]; + buf_rspageQ_3 = _RAND_84[3:0]; _RAND_85 = {1{`RANDOM}}; - _T_4303 = _RAND_85[0:0]; + _T_4307 = _RAND_85[0:0]; _RAND_86 = {1{`RANDOM}}; - _T_4301 = _RAND_86[0:0]; + _T_4305 = _RAND_86[0:0]; _RAND_87 = {1{`RANDOM}}; - buf_ldfwdtag_0 = _RAND_87[1:0]; + _T_4303 = _RAND_87[0:0]; _RAND_88 = {1{`RANDOM}}; - buf_dualtag_0 = _RAND_88[1:0]; + _T_4301 = _RAND_88[0:0]; _RAND_89 = {1{`RANDOM}}; - buf_ldfwdtag_3 = _RAND_89[1:0]; + buf_ldfwdtag_0 = _RAND_89[1:0]; _RAND_90 = {1{`RANDOM}}; - buf_ldfwdtag_2 = _RAND_90[1:0]; + buf_dualtag_0 = _RAND_90[1:0]; _RAND_91 = {1{`RANDOM}}; - buf_ldfwdtag_1 = _RAND_91[1:0]; + buf_ldfwdtag_3 = _RAND_91[1:0]; _RAND_92 = {1{`RANDOM}}; - buf_dualtag_1 = _RAND_92[1:0]; + buf_ldfwdtag_2 = _RAND_92[1:0]; _RAND_93 = {1{`RANDOM}}; - buf_dualtag_2 = _RAND_93[1:0]; + buf_ldfwdtag_1 = _RAND_93[1:0]; _RAND_94 = {1{`RANDOM}}; - buf_dualtag_3 = _RAND_94[1:0]; + buf_dualtag_1 = _RAND_94[1:0]; _RAND_95 = {1{`RANDOM}}; - _T_4336 = _RAND_95[0:0]; + buf_dualtag_2 = _RAND_95[1:0]; _RAND_96 = {1{`RANDOM}}; - _T_4339 = _RAND_96[0:0]; + buf_dualtag_3 = _RAND_96[1:0]; _RAND_97 = {1{`RANDOM}}; - _T_4342 = _RAND_97[0:0]; + _T_4336 = _RAND_97[0:0]; _RAND_98 = {1{`RANDOM}}; - _T_4345 = _RAND_98[0:0]; + _T_4339 = _RAND_98[0:0]; _RAND_99 = {1{`RANDOM}}; - _T_4411 = _RAND_99[0:0]; + _T_4342 = _RAND_99[0:0]; _RAND_100 = {1{`RANDOM}}; - _T_4406 = _RAND_100[0:0]; + _T_4345 = _RAND_100[0:0]; _RAND_101 = {1{`RANDOM}}; - _T_4401 = _RAND_101[0:0]; + _T_4411 = _RAND_101[0:0]; _RAND_102 = {1{`RANDOM}}; - _T_4396 = _RAND_102[0:0]; + _T_4406 = _RAND_102[0:0]; _RAND_103 = {1{`RANDOM}}; - lsu_nonblock_load_valid_r = _RAND_103[0:0]; + _T_4401 = _RAND_103[0:0]; _RAND_104 = {1{`RANDOM}}; - _T_4987 = _RAND_104[0:0]; + _T_4396 = _RAND_104[0:0]; + _RAND_105 = {1{`RANDOM}}; + lsu_nonblock_load_valid_r = _RAND_105[0:0]; + _RAND_106 = {1{`RANDOM}}; + _T_4987 = _RAND_106[0:0]; `endif // RANDOMIZE_REG_INIT if (reset) begin buf_addr_0 = 32'h0; @@ -71176,6 +71296,9 @@ initial begin if (reset) begin ibuf_data = 32'h0; end + if (reset) begin + ibuf_timer = 3'h0; + end if (reset) begin ibuf_sideeffect = 1'h0; end @@ -71206,6 +71329,9 @@ initial begin if (reset) begin ibuf_sz = 2'h0; end + if (reset) begin + obuf_wr_timer = 3'h0; + end if (reset) begin buf_nomerge_0 = 1'h0; end @@ -71808,7 +71934,9 @@ end // initial if (reset) begin ibuf_byteen <= 4'h0; end else if (ibuf_wr_en) begin - if (io_ldst_dual_r) begin + if (_T_866) begin + ibuf_byteen <= _T_881; + end else if (io_ldst_dual_r) begin ibuf_byteen <= ldst_byteen_hi_r; end else begin ibuf_byteen <= ldst_byteen_lo_r; @@ -71972,7 +72100,16 @@ end // initial if (reset) begin ibuf_data <= 32'h0; end else begin - ibuf_data <= {_T_922,_T_892}; + ibuf_data <= {_T_922,_T_893}; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + ibuf_timer <= 3'h0; + end else if (ibuf_wr_en) begin + ibuf_timer <= 3'h0; + end else if (_T_923) begin + ibuf_timer <= _T_926; end end always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin @@ -72012,10 +72149,12 @@ end // initial if (reset) begin ibuf_tag <= 2'h0; end else if (ibuf_wr_en) begin - if (io_ldst_dual_r) begin - ibuf_tag <= WrPtr1_r; - end else begin - ibuf_tag <= WrPtr0_r; + if (!(_T_866)) begin + if (io_ldst_dual_r) begin + ibuf_tag <= WrPtr1_r; + end else begin + ibuf_tag <= WrPtr0_r; + end end end end @@ -72061,6 +72200,15 @@ end // initial ibuf_sz <= ibuf_sz_in; end end + always @(posedge io_lsu_busm_clk or posedge reset) begin + if (reset) begin + obuf_wr_timer <= 3'h0; + end else if (obuf_wr_en) begin + obuf_wr_timer <= 3'h0; + end else if (_T_1058) begin + obuf_wr_timer <= _T_1060; + end + end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin buf_nomerge_0 <= 1'h0; @@ -72608,6 +72756,7 @@ module lsu_bus_intf( output io_tlu_busbuff_lsu_pmu_bus_error, output io_tlu_busbuff_lsu_pmu_bus_busy, input io_tlu_busbuff_dec_tlu_external_ldfwd_disable, + input io_tlu_busbuff_dec_tlu_wb_coalescing_disable, input io_tlu_busbuff_dec_tlu_sideeffect_posted_disable, output io_tlu_busbuff_lsu_imprecise_error_load_any, output io_tlu_busbuff_lsu_imprecise_error_store_any, @@ -72625,7 +72774,9 @@ module lsu_bus_intf( output io_axi_aw_valid, output [2:0] io_axi_aw_bits_id, output [31:0] io_axi_aw_bits_addr, + output [3:0] io_axi_aw_bits_region, output [2:0] io_axi_aw_bits_size, + output [3:0] io_axi_aw_bits_cache, input io_axi_w_ready, output io_axi_w_valid, output [63:0] io_axi_w_bits_data, @@ -72637,7 +72788,9 @@ module lsu_bus_intf( output io_axi_ar_valid, output [2:0] io_axi_ar_bits_id, output [31:0] io_axi_ar_bits_addr, + output [3:0] io_axi_ar_bits_region, output [2:0] io_axi_ar_bits_size, + output [3:0] io_axi_ar_bits_cache, input io_axi_r_valid, input [2:0] io_axi_r_bits_id, input [63:0] io_axi_r_bits_data, @@ -72698,6 +72851,7 @@ module lsu_bus_intf( wire bus_buffer_io_tlu_busbuff_lsu_pmu_bus_error; // @[lsu_bus_intf.scala 100:39] wire bus_buffer_io_tlu_busbuff_lsu_pmu_bus_busy; // @[lsu_bus_intf.scala 100:39] wire bus_buffer_io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu_bus_intf.scala 100:39] + wire bus_buffer_io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_intf.scala 100:39] wire bus_buffer_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_intf.scala 100:39] wire bus_buffer_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[lsu_bus_intf.scala 100:39] wire bus_buffer_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu_bus_intf.scala 100:39] @@ -72747,7 +72901,9 @@ module lsu_bus_intf( wire bus_buffer_io_lsu_axi_aw_valid; // @[lsu_bus_intf.scala 100:39] wire [2:0] bus_buffer_io_lsu_axi_aw_bits_id; // @[lsu_bus_intf.scala 100:39] wire [31:0] bus_buffer_io_lsu_axi_aw_bits_addr; // @[lsu_bus_intf.scala 100:39] + wire [3:0] bus_buffer_io_lsu_axi_aw_bits_region; // @[lsu_bus_intf.scala 100:39] wire [2:0] bus_buffer_io_lsu_axi_aw_bits_size; // @[lsu_bus_intf.scala 100:39] + wire [3:0] bus_buffer_io_lsu_axi_aw_bits_cache; // @[lsu_bus_intf.scala 100:39] wire bus_buffer_io_lsu_axi_w_ready; // @[lsu_bus_intf.scala 100:39] wire bus_buffer_io_lsu_axi_w_valid; // @[lsu_bus_intf.scala 100:39] wire [63:0] bus_buffer_io_lsu_axi_w_bits_data; // @[lsu_bus_intf.scala 100:39] @@ -72760,7 +72916,9 @@ module lsu_bus_intf( wire bus_buffer_io_lsu_axi_ar_valid; // @[lsu_bus_intf.scala 100:39] wire [2:0] bus_buffer_io_lsu_axi_ar_bits_id; // @[lsu_bus_intf.scala 100:39] wire [31:0] bus_buffer_io_lsu_axi_ar_bits_addr; // @[lsu_bus_intf.scala 100:39] + wire [3:0] bus_buffer_io_lsu_axi_ar_bits_region; // @[lsu_bus_intf.scala 100:39] wire [2:0] bus_buffer_io_lsu_axi_ar_bits_size; // @[lsu_bus_intf.scala 100:39] + wire [3:0] bus_buffer_io_lsu_axi_ar_bits_cache; // @[lsu_bus_intf.scala 100:39] wire bus_buffer_io_lsu_axi_r_ready; // @[lsu_bus_intf.scala 100:39] wire bus_buffer_io_lsu_axi_r_valid; // @[lsu_bus_intf.scala 100:39] wire [2:0] bus_buffer_io_lsu_axi_r_bits_id; // @[lsu_bus_intf.scala 100:39] @@ -72966,6 +73124,7 @@ module lsu_bus_intf( .io_tlu_busbuff_lsu_pmu_bus_error(bus_buffer_io_tlu_busbuff_lsu_pmu_bus_error), .io_tlu_busbuff_lsu_pmu_bus_busy(bus_buffer_io_tlu_busbuff_lsu_pmu_bus_busy), .io_tlu_busbuff_dec_tlu_external_ldfwd_disable(bus_buffer_io_tlu_busbuff_dec_tlu_external_ldfwd_disable), + .io_tlu_busbuff_dec_tlu_wb_coalescing_disable(bus_buffer_io_tlu_busbuff_dec_tlu_wb_coalescing_disable), .io_tlu_busbuff_dec_tlu_sideeffect_posted_disable(bus_buffer_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable), .io_tlu_busbuff_lsu_imprecise_error_load_any(bus_buffer_io_tlu_busbuff_lsu_imprecise_error_load_any), .io_tlu_busbuff_lsu_imprecise_error_store_any(bus_buffer_io_tlu_busbuff_lsu_imprecise_error_store_any), @@ -73015,7 +73174,9 @@ module lsu_bus_intf( .io_lsu_axi_aw_valid(bus_buffer_io_lsu_axi_aw_valid), .io_lsu_axi_aw_bits_id(bus_buffer_io_lsu_axi_aw_bits_id), .io_lsu_axi_aw_bits_addr(bus_buffer_io_lsu_axi_aw_bits_addr), + .io_lsu_axi_aw_bits_region(bus_buffer_io_lsu_axi_aw_bits_region), .io_lsu_axi_aw_bits_size(bus_buffer_io_lsu_axi_aw_bits_size), + .io_lsu_axi_aw_bits_cache(bus_buffer_io_lsu_axi_aw_bits_cache), .io_lsu_axi_w_ready(bus_buffer_io_lsu_axi_w_ready), .io_lsu_axi_w_valid(bus_buffer_io_lsu_axi_w_valid), .io_lsu_axi_w_bits_data(bus_buffer_io_lsu_axi_w_bits_data), @@ -73028,7 +73189,9 @@ module lsu_bus_intf( .io_lsu_axi_ar_valid(bus_buffer_io_lsu_axi_ar_valid), .io_lsu_axi_ar_bits_id(bus_buffer_io_lsu_axi_ar_bits_id), .io_lsu_axi_ar_bits_addr(bus_buffer_io_lsu_axi_ar_bits_addr), + .io_lsu_axi_ar_bits_region(bus_buffer_io_lsu_axi_ar_bits_region), .io_lsu_axi_ar_bits_size(bus_buffer_io_lsu_axi_ar_bits_size), + .io_lsu_axi_ar_bits_cache(bus_buffer_io_lsu_axi_ar_bits_cache), .io_lsu_axi_r_ready(bus_buffer_io_lsu_axi_r_ready), .io_lsu_axi_r_valid(bus_buffer_io_lsu_axi_r_valid), .io_lsu_axi_r_bits_id(bus_buffer_io_lsu_axi_r_bits_id), @@ -73055,14 +73218,18 @@ module lsu_bus_intf( assign io_axi_aw_valid = bus_buffer_io_lsu_axi_aw_valid; // @[lsu_bus_intf.scala 129:43] assign io_axi_aw_bits_id = bus_buffer_io_lsu_axi_aw_bits_id; // @[lsu_bus_intf.scala 129:43] assign io_axi_aw_bits_addr = bus_buffer_io_lsu_axi_aw_bits_addr; // @[lsu_bus_intf.scala 129:43] + assign io_axi_aw_bits_region = bus_buffer_io_lsu_axi_aw_bits_region; // @[lsu_bus_intf.scala 129:43] assign io_axi_aw_bits_size = bus_buffer_io_lsu_axi_aw_bits_size; // @[lsu_bus_intf.scala 129:43] + assign io_axi_aw_bits_cache = bus_buffer_io_lsu_axi_aw_bits_cache; // @[lsu_bus_intf.scala 129:43] assign io_axi_w_valid = bus_buffer_io_lsu_axi_w_valid; // @[lsu_bus_intf.scala 129:43] assign io_axi_w_bits_data = bus_buffer_io_lsu_axi_w_bits_data; // @[lsu_bus_intf.scala 129:43] assign io_axi_w_bits_strb = bus_buffer_io_lsu_axi_w_bits_strb; // @[lsu_bus_intf.scala 129:43] assign io_axi_ar_valid = bus_buffer_io_lsu_axi_ar_valid; // @[lsu_bus_intf.scala 129:43] assign io_axi_ar_bits_id = bus_buffer_io_lsu_axi_ar_bits_id; // @[lsu_bus_intf.scala 129:43] assign io_axi_ar_bits_addr = bus_buffer_io_lsu_axi_ar_bits_addr; // @[lsu_bus_intf.scala 129:43] + assign io_axi_ar_bits_region = bus_buffer_io_lsu_axi_ar_bits_region; // @[lsu_bus_intf.scala 129:43] assign io_axi_ar_bits_size = bus_buffer_io_lsu_axi_ar_bits_size; // @[lsu_bus_intf.scala 129:43] + assign io_axi_ar_bits_cache = bus_buffer_io_lsu_axi_ar_bits_cache; // @[lsu_bus_intf.scala 129:43] assign io_lsu_busreq_r = bus_buffer_io_lsu_busreq_r; // @[lsu_bus_intf.scala 132:38] assign io_lsu_bus_buffer_pend_any = bus_buffer_io_lsu_bus_buffer_pend_any; // @[lsu_bus_intf.scala 133:38] assign io_lsu_bus_buffer_full_any = bus_buffer_io_lsu_bus_buffer_full_any; // @[lsu_bus_intf.scala 134:38] @@ -73080,6 +73247,7 @@ module lsu_bus_intf( assign bus_buffer_reset = reset; assign bus_buffer_io_scan_mode = io_scan_mode; // @[lsu_bus_intf.scala 102:29] assign bus_buffer_io_tlu_busbuff_dec_tlu_external_ldfwd_disable = io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu_bus_intf.scala 103:18] + assign bus_buffer_io_tlu_busbuff_dec_tlu_wb_coalescing_disable = io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_intf.scala 103:18] assign bus_buffer_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable = io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_intf.scala 103:18] assign bus_buffer_io_dec_tlu_force_halt = io_dec_tlu_force_halt; // @[lsu_bus_intf.scala 105:51] assign bus_buffer_io_lsu_c2_r_clk = io_lsu_c2_r_clk; // @[lsu_bus_intf.scala 106:51] @@ -73260,6 +73428,7 @@ module lsu( output io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error, output io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy, input io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable, + input io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable, input io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable, output io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any, output io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any, @@ -73288,7 +73457,9 @@ module lsu( output io_axi_aw_valid, output [2:0] io_axi_aw_bits_id, output [31:0] io_axi_aw_bits_addr, + output [3:0] io_axi_aw_bits_region, output [2:0] io_axi_aw_bits_size, + output [3:0] io_axi_aw_bits_cache, input io_axi_w_ready, output io_axi_w_valid, output [63:0] io_axi_w_bits_data, @@ -73300,7 +73471,9 @@ module lsu( output io_axi_ar_valid, output [2:0] io_axi_ar_bits_id, output [31:0] io_axi_ar_bits_addr, + output [3:0] io_axi_ar_bits_region, output [2:0] io_axi_ar_bits_size, + output [3:0] io_axi_ar_bits_cache, input io_axi_r_valid, input [2:0] io_axi_r_bits_id, input [63:0] io_axi_r_bits_data, @@ -73725,6 +73898,7 @@ module lsu( wire bus_intf_io_tlu_busbuff_lsu_pmu_bus_error; // @[lsu.scala 68:30] wire bus_intf_io_tlu_busbuff_lsu_pmu_bus_busy; // @[lsu.scala 68:30] wire bus_intf_io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu.scala 68:30] + wire bus_intf_io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu.scala 68:30] wire bus_intf_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu.scala 68:30] wire bus_intf_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[lsu.scala 68:30] wire bus_intf_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu.scala 68:30] @@ -73742,7 +73916,9 @@ module lsu( wire bus_intf_io_axi_aw_valid; // @[lsu.scala 68:30] wire [2:0] bus_intf_io_axi_aw_bits_id; // @[lsu.scala 68:30] wire [31:0] bus_intf_io_axi_aw_bits_addr; // @[lsu.scala 68:30] + wire [3:0] bus_intf_io_axi_aw_bits_region; // @[lsu.scala 68:30] wire [2:0] bus_intf_io_axi_aw_bits_size; // @[lsu.scala 68:30] + wire [3:0] bus_intf_io_axi_aw_bits_cache; // @[lsu.scala 68:30] wire bus_intf_io_axi_w_ready; // @[lsu.scala 68:30] wire bus_intf_io_axi_w_valid; // @[lsu.scala 68:30] wire [63:0] bus_intf_io_axi_w_bits_data; // @[lsu.scala 68:30] @@ -73754,7 +73930,9 @@ module lsu( wire bus_intf_io_axi_ar_valid; // @[lsu.scala 68:30] wire [2:0] bus_intf_io_axi_ar_bits_id; // @[lsu.scala 68:30] wire [31:0] bus_intf_io_axi_ar_bits_addr; // @[lsu.scala 68:30] + wire [3:0] bus_intf_io_axi_ar_bits_region; // @[lsu.scala 68:30] wire [2:0] bus_intf_io_axi_ar_bits_size; // @[lsu.scala 68:30] + wire [3:0] bus_intf_io_axi_ar_bits_cache; // @[lsu.scala 68:30] wire bus_intf_io_axi_r_valid; // @[lsu.scala 68:30] wire [2:0] bus_intf_io_axi_r_bits_id; // @[lsu.scala 68:30] wire [63:0] bus_intf_io_axi_r_bits_data; // @[lsu.scala 68:30] @@ -74205,6 +74383,7 @@ module lsu( .io_tlu_busbuff_lsu_pmu_bus_error(bus_intf_io_tlu_busbuff_lsu_pmu_bus_error), .io_tlu_busbuff_lsu_pmu_bus_busy(bus_intf_io_tlu_busbuff_lsu_pmu_bus_busy), .io_tlu_busbuff_dec_tlu_external_ldfwd_disable(bus_intf_io_tlu_busbuff_dec_tlu_external_ldfwd_disable), + .io_tlu_busbuff_dec_tlu_wb_coalescing_disable(bus_intf_io_tlu_busbuff_dec_tlu_wb_coalescing_disable), .io_tlu_busbuff_dec_tlu_sideeffect_posted_disable(bus_intf_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable), .io_tlu_busbuff_lsu_imprecise_error_load_any(bus_intf_io_tlu_busbuff_lsu_imprecise_error_load_any), .io_tlu_busbuff_lsu_imprecise_error_store_any(bus_intf_io_tlu_busbuff_lsu_imprecise_error_store_any), @@ -74222,7 +74401,9 @@ module lsu( .io_axi_aw_valid(bus_intf_io_axi_aw_valid), .io_axi_aw_bits_id(bus_intf_io_axi_aw_bits_id), .io_axi_aw_bits_addr(bus_intf_io_axi_aw_bits_addr), + .io_axi_aw_bits_region(bus_intf_io_axi_aw_bits_region), .io_axi_aw_bits_size(bus_intf_io_axi_aw_bits_size), + .io_axi_aw_bits_cache(bus_intf_io_axi_aw_bits_cache), .io_axi_w_ready(bus_intf_io_axi_w_ready), .io_axi_w_valid(bus_intf_io_axi_w_valid), .io_axi_w_bits_data(bus_intf_io_axi_w_bits_data), @@ -74234,7 +74415,9 @@ module lsu( .io_axi_ar_valid(bus_intf_io_axi_ar_valid), .io_axi_ar_bits_id(bus_intf_io_axi_ar_bits_id), .io_axi_ar_bits_addr(bus_intf_io_axi_ar_bits_addr), + .io_axi_ar_bits_region(bus_intf_io_axi_ar_bits_region), .io_axi_ar_bits_size(bus_intf_io_axi_ar_bits_size), + .io_axi_ar_bits_cache(bus_intf_io_axi_ar_bits_cache), .io_axi_r_valid(bus_intf_io_axi_r_valid), .io_axi_r_bits_id(bus_intf_io_axi_r_bits_id), .io_axi_r_bits_data(bus_intf_io_axi_r_bits_data), @@ -74319,14 +74502,18 @@ module lsu( assign io_axi_aw_valid = bus_intf_io_axi_aw_valid; // @[lsu.scala 314:49] assign io_axi_aw_bits_id = bus_intf_io_axi_aw_bits_id; // @[lsu.scala 314:49] assign io_axi_aw_bits_addr = bus_intf_io_axi_aw_bits_addr; // @[lsu.scala 314:49] + assign io_axi_aw_bits_region = bus_intf_io_axi_aw_bits_region; // @[lsu.scala 314:49] assign io_axi_aw_bits_size = bus_intf_io_axi_aw_bits_size; // @[lsu.scala 314:49] + assign io_axi_aw_bits_cache = bus_intf_io_axi_aw_bits_cache; // @[lsu.scala 314:49] assign io_axi_w_valid = bus_intf_io_axi_w_valid; // @[lsu.scala 314:49] assign io_axi_w_bits_data = bus_intf_io_axi_w_bits_data; // @[lsu.scala 314:49] assign io_axi_w_bits_strb = bus_intf_io_axi_w_bits_strb; // @[lsu.scala 314:49] assign io_axi_ar_valid = bus_intf_io_axi_ar_valid; // @[lsu.scala 314:49] assign io_axi_ar_bits_id = bus_intf_io_axi_ar_bits_id; // @[lsu.scala 314:49] assign io_axi_ar_bits_addr = bus_intf_io_axi_ar_bits_addr; // @[lsu.scala 314:49] + assign io_axi_ar_bits_region = bus_intf_io_axi_ar_bits_region; // @[lsu.scala 314:49] assign io_axi_ar_bits_size = bus_intf_io_axi_ar_bits_size; // @[lsu.scala 314:49] + assign io_axi_ar_bits_cache = bus_intf_io_axi_ar_bits_cache; // @[lsu.scala 314:49] assign io_lsu_result_m = lsu_lsc_ctl_io_lsu_result_m; // @[lsu.scala 61:19] assign io_lsu_result_corr_r = lsu_lsc_ctl_io_lsu_result_corr_r; // @[lsu.scala 62:24] assign io_lsu_load_stall_any = bus_intf_io_lsu_bus_buffer_full_any | dccm_ctl_io_ld_single_ecc_error_r_ff; // @[lsu.scala 75:25] @@ -74561,6 +74748,7 @@ module lsu( assign bus_intf_reset = reset; assign bus_intf_io_scan_mode = io_scan_mode; // @[lsu.scala 285:49] assign bus_intf_io_tlu_busbuff_dec_tlu_external_ldfwd_disable = io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu.scala 286:26] + assign bus_intf_io_tlu_busbuff_dec_tlu_wb_coalescing_disable = io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu.scala 286:26] assign bus_intf_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable = io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu.scala 286:26] assign bus_intf_io_lsu_c1_m_clk = clkdomain_io_lsu_c1_m_clk; // @[lsu.scala 287:49] assign bus_intf_io_lsu_c1_r_clk = clkdomain_io_lsu_c1_r_clk; // @[lsu.scala 288:49] @@ -78346,18 +78534,25 @@ module dma_ctrl( input io_iccm_ready, output io_dma_axi_aw_ready, input io_dma_axi_aw_valid, + input io_dma_axi_aw_bits_id, input [31:0] io_dma_axi_aw_bits_addr, input [2:0] io_dma_axi_aw_bits_size, output io_dma_axi_w_ready, input io_dma_axi_w_valid, input [63:0] io_dma_axi_w_bits_data, input [7:0] io_dma_axi_w_bits_strb, + input io_dma_axi_b_ready, output io_dma_axi_b_valid, + output [1:0] io_dma_axi_b_bits_resp, + output io_dma_axi_b_bits_id, output io_dma_axi_ar_ready, input io_dma_axi_ar_valid, + input io_dma_axi_ar_bits_id, input [31:0] io_dma_axi_ar_bits_addr, input [2:0] io_dma_axi_ar_bits_size, + input io_dma_axi_r_ready, output io_dma_axi_r_valid, + output io_dma_axi_r_bits_id, output [63:0] io_dma_axi_r_bits_data, output [1:0] io_dma_axi_r_bits_resp, output io_lsu_dma_dma_lsc_ctl_dma_dccm_req, @@ -78454,6 +78649,13 @@ module dma_ctrl( reg [63:0] _RAND_69; reg [31:0] _RAND_70; reg [31:0] _RAND_71; + reg [31:0] _RAND_72; + reg [31:0] _RAND_73; + reg [31:0] _RAND_74; + reg [31:0] _RAND_75; + reg [31:0] _RAND_76; + reg [31:0] _RAND_77; + reg [31:0] _RAND_78; `endif // RANDOMIZE_REG_INIT wire rvclkhdr_io_l1clk; // @[lib.scala 368:23] wire rvclkhdr_io_clk; // @[lib.scala 368:23] @@ -78850,7 +79052,9 @@ module dma_ctrl( wire _T_399 = fifo_done_en[4] | fifo_done[4]; // @[dma_ctrl.scala 218:75] wire _T_400 = _T_399 & io_dma_bus_clk_en; // @[dma_ctrl.scala 218:91] wire [4:0] fifo_done_bus_en = {_T_400,_T_396,_T_392,_T_388,_T_384}; // @[Cat.scala 29:58] - wire bus_rsp_sent = io_dma_axi_b_valid | io_dma_axi_r_valid; // @[dma_ctrl.scala 489:83] + wire _T_1287 = io_dma_axi_b_valid & io_dma_axi_b_ready; // @[dma_ctrl.scala 489:61] + wire _T_1288 = io_dma_axi_r_valid & io_dma_axi_r_ready; // @[dma_ctrl.scala 489:105] + wire bus_rsp_sent = _T_1287 | _T_1288; // @[dma_ctrl.scala 489:83] wire _T_406 = bus_rsp_sent & io_dma_bus_clk_en; // @[dma_ctrl.scala 220:99] wire _T_407 = _T_406 | io_dma_dbg_cmd_done; // @[dma_ctrl.scala 220:120] reg [2:0] RspPtr; // @[Reg.scala 27:20] @@ -78932,6 +79136,14 @@ module dma_ctrl( reg [63:0] fifo_data_2; // @[lib.scala 374:16] reg [63:0] fifo_data_3; // @[lib.scala 374:16] reg [63:0] fifo_data_4; // @[lib.scala 374:16] + reg fifo_tag_0; // @[Reg.scala 27:20] + reg wrbuf_tag; // @[Reg.scala 27:20] + reg rdbuf_tag; // @[Reg.scala 27:20] + wire bus_cmd_tag = axi_mstr_sel ? wrbuf_tag : rdbuf_tag; // @[dma_ctrl.scala 454:43] + reg fifo_tag_1; // @[Reg.scala 27:20] + reg fifo_tag_2; // @[Reg.scala 27:20] + reg fifo_tag_3; // @[Reg.scala 27:20] + reg fifo_tag_4; // @[Reg.scala 27:20] wire _T_931 = WrPtr == 3'h4; // @[dma_ctrl.scala 260:30] wire [2:0] _T_934 = WrPtr + 3'h1; // @[dma_ctrl.scala 260:76] wire _T_936 = RdPtr == 3'h4; // @[dma_ctrl.scala 262:30] @@ -78998,7 +79210,8 @@ module dma_ctrl( reg dma_dbg_cmd_done_q; // @[dma_ctrl.scala 381:12] wire _T_1212 = bus_cmd_valid & io_dma_bus_clk_en; // @[dma_ctrl.scala 386:44] wire _T_1213 = _T_1212 | io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[dma_ctrl.scala 386:65] - wire _T_1214 = bus_cmd_valid | bus_rsp_sent; // @[dma_ctrl.scala 387:44] + wire bus_rsp_valid = io_dma_axi_b_valid | io_dma_axi_r_valid; // @[dma_ctrl.scala 488:60] + wire _T_1214 = bus_cmd_valid | bus_rsp_valid; // @[dma_ctrl.scala 387:44] wire _T_1215 = _T_1214 | io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[dma_ctrl.scala 387:60] wire _T_1216 = _T_1215 | io_dma_dbg_cmd_done; // @[dma_ctrl.scala 387:94] wire _T_1217 = _T_1216 | dma_dbg_cmd_done_q; // @[dma_ctrl.scala 387:116] @@ -79034,6 +79247,9 @@ module dma_ctrl( wire [4:0] _T_1277 = fifo_write >> RspPtr; // @[dma_ctrl.scala 470:39] wire axi_rsp_write = _T_1277[0]; // @[dma_ctrl.scala 470:39] wire [1:0] _T_1280 = _GEN_57[1] ? 2'h3 : 2'h0; // @[dma_ctrl.scala 471:64] + wire _GEN_86 = 3'h1 == RspPtr ? fifo_tag_1 : fifo_tag_0; // @[dma_ctrl.scala 479:33] + wire _GEN_87 = 3'h2 == RspPtr ? fifo_tag_2 : _GEN_86; // @[dma_ctrl.scala 479:33] + wire _GEN_88 = 3'h3 == RspPtr ? fifo_tag_3 : _GEN_87; // @[dma_ctrl.scala 479:33] wire _T_1283 = ~axi_rsp_write; // @[dma_ctrl.scala 481:46] rvclkhdr rvclkhdr ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_io_l1clk), @@ -79145,8 +79361,11 @@ module dma_ctrl( assign io_dma_axi_aw_ready = ~_T_1245; // @[dma_ctrl.scala 440:27] assign io_dma_axi_w_ready = ~_T_1248; // @[dma_ctrl.scala 441:27] assign io_dma_axi_b_valid = axi_rsp_valid & axi_rsp_write; // @[dma_ctrl.scala 477:27] + assign io_dma_axi_b_bits_resp = _GEN_57[0] ? 2'h2 : _T_1280; // @[dma_ctrl.scala 478:41] + assign io_dma_axi_b_bits_id = 3'h4 == RspPtr ? fifo_tag_4 : _GEN_88; // @[dma_ctrl.scala 479:33] assign io_dma_axi_ar_ready = ~_T_1251; // @[dma_ctrl.scala 442:27] assign io_dma_axi_r_valid = axi_rsp_valid & _T_1283; // @[dma_ctrl.scala 481:27] + assign io_dma_axi_r_bits_id = 3'h4 == RspPtr ? fifo_tag_4 : _GEN_88; // @[dma_ctrl.scala 485:37] assign io_dma_axi_r_bits_data = 3'h4 == RspPtr ? fifo_data_4 : _GEN_51; // @[dma_ctrl.scala 483:43] assign io_dma_axi_r_bits_resp = _GEN_57[0] ? 2'h2 : _T_1280; // @[dma_ctrl.scala 482:41] assign io_lsu_dma_dma_lsc_ctl_dma_dccm_req = _T_1137 & io_lsu_dma_dccm_ready; // @[dma_ctrl.scala 352:40] @@ -79388,9 +79607,23 @@ initial begin _RAND_69 = {2{`RANDOM}}; fifo_data_4 = _RAND_69[63:0]; _RAND_70 = {1{`RANDOM}}; - dma_nack_count = _RAND_70[2:0]; + fifo_tag_0 = _RAND_70[0:0]; _RAND_71 = {1{`RANDOM}}; - dma_dbg_cmd_done_q = _RAND_71[0:0]; + wrbuf_tag = _RAND_71[0:0]; + _RAND_72 = {1{`RANDOM}}; + rdbuf_tag = _RAND_72[0:0]; + _RAND_73 = {1{`RANDOM}}; + fifo_tag_1 = _RAND_73[0:0]; + _RAND_74 = {1{`RANDOM}}; + fifo_tag_2 = _RAND_74[0:0]; + _RAND_75 = {1{`RANDOM}}; + fifo_tag_3 = _RAND_75[0:0]; + _RAND_76 = {1{`RANDOM}}; + fifo_tag_4 = _RAND_76[0:0]; + _RAND_77 = {1{`RANDOM}}; + dma_nack_count = _RAND_77[2:0]; + _RAND_78 = {1{`RANDOM}}; + dma_dbg_cmd_done_q = _RAND_78[0:0]; `endif // RANDOMIZE_REG_INIT if (reset) begin RdPtr = 3'h0; @@ -79602,6 +79835,27 @@ initial begin if (reset) begin fifo_data_4 = 64'h0; end + if (reset) begin + fifo_tag_0 = 1'h0; + end + if (reset) begin + wrbuf_tag = 1'h0; + end + if (reset) begin + rdbuf_tag = 1'h0; + end + if (reset) begin + fifo_tag_1 = 1'h0; + end + if (reset) begin + fifo_tag_2 = 1'h0; + end + if (reset) begin + fifo_tag_3 = 1'h0; + end + if (reset) begin + fifo_tag_4 = 1'h0; + end if (reset) begin dma_nack_count = 3'h0; end @@ -80220,6 +80474,71 @@ end // initial fifo_data_4 <= _T_500; end end + always @(posedge dma_buffer_c1_clk or posedge reset) begin + if (reset) begin + fifo_tag_0 <= 1'h0; + end else if (fifo_cmd_en[0]) begin + if (axi_mstr_sel) begin + fifo_tag_0 <= wrbuf_tag; + end else begin + fifo_tag_0 <= rdbuf_tag; + end + end + end + always @(posedge dma_bus_clk or posedge reset) begin + if (reset) begin + wrbuf_tag <= 1'h0; + end else if (wrbuf_en) begin + wrbuf_tag <= io_dma_axi_aw_bits_id; + end + end + always @(posedge dma_bus_clk or posedge reset) begin + if (reset) begin + rdbuf_tag <= 1'h0; + end else if (rdbuf_en) begin + rdbuf_tag <= io_dma_axi_ar_bits_id; + end + end + always @(posedge dma_buffer_c1_clk or posedge reset) begin + if (reset) begin + fifo_tag_1 <= 1'h0; + end else if (fifo_cmd_en[1]) begin + if (axi_mstr_sel) begin + fifo_tag_1 <= wrbuf_tag; + end else begin + fifo_tag_1 <= rdbuf_tag; + end + end + end + always @(posedge dma_buffer_c1_clk or posedge reset) begin + if (reset) begin + fifo_tag_2 <= 1'h0; + end else if (fifo_cmd_en[2]) begin + if (axi_mstr_sel) begin + fifo_tag_2 <= wrbuf_tag; + end else begin + fifo_tag_2 <= rdbuf_tag; + end + end + end + always @(posedge dma_buffer_c1_clk or posedge reset) begin + if (reset) begin + fifo_tag_3 <= 1'h0; + end else if (fifo_cmd_en[3]) begin + if (axi_mstr_sel) begin + fifo_tag_3 <= wrbuf_tag; + end else begin + fifo_tag_3 <= rdbuf_tag; + end + end + end + always @(posedge dma_buffer_c1_clk or posedge reset) begin + if (reset) begin + fifo_tag_4 <= 1'h0; + end else if (fifo_cmd_en[4]) begin + fifo_tag_4 <= bus_cmd_tag; + end + end always @(posedge dma_free_clk or posedge reset) begin if (reset) begin dma_nack_count <= 3'h0; @@ -80241,2676 +80560,85 @@ end // initial end end endmodule -module axi4_to_ahb( - input clock, - input reset, - input io_scan_mode, - input io_bus_clk_en, - input io_clk_override, - output io_axi_aw_ready, - input io_axi_aw_valid, - input [31:0] io_axi_aw_bits_addr, - input [2:0] io_axi_aw_bits_size, - output io_axi_w_ready, - input io_axi_w_valid, - input [63:0] io_axi_w_bits_data, - input [7:0] io_axi_w_bits_strb, - output io_axi_b_valid, - output [1:0] io_axi_b_bits_resp, - output io_axi_ar_ready, - input io_axi_ar_valid, - input [31:0] io_axi_ar_bits_addr, - input [2:0] io_axi_ar_bits_size, - output io_axi_r_valid, - output [63:0] io_axi_r_bits_data, - output [1:0] io_axi_r_bits_resp, - input [63:0] io_ahb_in_hrdata, - input io_ahb_in_hready, - input io_ahb_in_hresp, - output [31:0] io_ahb_out_haddr, - output [2:0] io_ahb_out_hsize, - output [1:0] io_ahb_out_htrans, - output io_ahb_out_hwrite, - output [63:0] io_ahb_out_hwdata -); -`ifdef RANDOMIZE_REG_INIT - reg [31:0] _RAND_0; - reg [31:0] _RAND_1; - reg [31:0] _RAND_2; - reg [31:0] _RAND_3; - reg [31:0] _RAND_4; - reg [31:0] _RAND_5; - reg [31:0] _RAND_6; - reg [31:0] _RAND_7; - reg [31:0] _RAND_8; - reg [31:0] _RAND_9; - reg [31:0] _RAND_10; - reg [63:0] _RAND_11; - reg [31:0] _RAND_12; - reg [31:0] _RAND_13; - reg [31:0] _RAND_14; - reg [63:0] _RAND_15; - reg [63:0] _RAND_16; - reg [31:0] _RAND_17; - reg [31:0] _RAND_18; - reg [31:0] _RAND_19; - reg [31:0] _RAND_20; - reg [31:0] _RAND_21; - reg [31:0] _RAND_22; -`endif // RANDOMIZE_REG_INIT - wire rvclkhdr_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_io_en; // @[lib.scala 343:22] - wire rvclkhdr_io_scan_mode; // @[lib.scala 343:22] - wire rvclkhdr_1_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_1_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_1_io_en; // @[lib.scala 343:22] - wire rvclkhdr_1_io_scan_mode; // @[lib.scala 343:22] - wire rvclkhdr_2_io_l1clk; // @[lib.scala 368:23] - wire rvclkhdr_2_io_clk; // @[lib.scala 368:23] - wire rvclkhdr_2_io_en; // @[lib.scala 368:23] - wire rvclkhdr_2_io_scan_mode; // @[lib.scala 368:23] - wire rvclkhdr_3_io_l1clk; // @[lib.scala 368:23] - wire rvclkhdr_3_io_clk; // @[lib.scala 368:23] - wire rvclkhdr_3_io_en; // @[lib.scala 368:23] - wire rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23] - wire rvclkhdr_4_io_l1clk; // @[lib.scala 368:23] - wire rvclkhdr_4_io_clk; // @[lib.scala 368:23] - wire rvclkhdr_4_io_en; // @[lib.scala 368:23] - wire rvclkhdr_4_io_scan_mode; // @[lib.scala 368:23] - wire rvclkhdr_5_io_l1clk; // @[lib.scala 368:23] - wire rvclkhdr_5_io_clk; // @[lib.scala 368:23] - wire rvclkhdr_5_io_en; // @[lib.scala 368:23] - wire rvclkhdr_5_io_scan_mode; // @[lib.scala 368:23] - wire rvclkhdr_6_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_6_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_6_io_en; // @[lib.scala 343:22] - wire rvclkhdr_6_io_scan_mode; // @[lib.scala 343:22] - wire rvclkhdr_7_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_7_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_7_io_en; // @[lib.scala 343:22] - wire rvclkhdr_7_io_scan_mode; // @[lib.scala 343:22] - wire rvclkhdr_8_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_8_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_8_io_en; // @[lib.scala 343:22] - wire rvclkhdr_8_io_scan_mode; // @[lib.scala 343:22] - wire rvclkhdr_9_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_9_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_9_io_en; // @[lib.scala 343:22] - wire rvclkhdr_9_io_scan_mode; // @[lib.scala 343:22] - wire ahbm_clk = rvclkhdr_7_io_l1clk; // @[axi4_to_ahb.scala 24:22 axi4_to_ahb.scala 333:12] - reg [2:0] buf_state; // @[axi4_to_ahb.scala 30:45] - wire _T_49 = 3'h0 == buf_state; // @[Conditional.scala 37:30] - wire bus_clk = rvclkhdr_io_l1clk; // @[axi4_to_ahb.scala 50:21 axi4_to_ahb.scala 162:11] - reg wrbuf_vld; // @[axi4_to_ahb.scala 301:51] - reg wrbuf_data_vld; // @[axi4_to_ahb.scala 302:51] - wire wr_cmd_vld = wrbuf_vld & wrbuf_data_vld; // @[axi4_to_ahb.scala 139:27] - wire master_valid = wr_cmd_vld | io_axi_ar_valid; // @[axi4_to_ahb.scala 140:30] - wire _T_101 = 3'h1 == buf_state; // @[Conditional.scala 37:30] - reg ahb_hready_q; // @[axi4_to_ahb.scala 321:52] - reg [1:0] ahb_htrans_q; // @[axi4_to_ahb.scala 322:52] - wire _T_108 = ahb_htrans_q != 2'h0; // @[axi4_to_ahb.scala 183:58] - wire _T_109 = ahb_hready_q & _T_108; // @[axi4_to_ahb.scala 183:36] - wire ahbm_addr_clk = rvclkhdr_8_io_l1clk; // @[axi4_to_ahb.scala 25:27 axi4_to_ahb.scala 334:17] - reg ahb_hwrite_q; // @[axi4_to_ahb.scala 323:57] - wire _T_110 = ~ahb_hwrite_q; // @[axi4_to_ahb.scala 183:72] - wire _T_111 = _T_109 & _T_110; // @[axi4_to_ahb.scala 183:70] - wire _T_136 = 3'h6 == buf_state; // @[Conditional.scala 37:30] - reg ahb_hresp_q; // @[axi4_to_ahb.scala 324:52] - wire _T_156 = ahb_hready_q | ahb_hresp_q; // @[axi4_to_ahb.scala 197:37] - wire _T_175 = 3'h7 == buf_state; // @[Conditional.scala 37:30] - wire _T_186 = 3'h3 == buf_state; // @[Conditional.scala 37:30] - wire _T_188 = 3'h2 == buf_state; // @[Conditional.scala 37:30] - wire _T_189 = ahb_hready_q & ahb_hwrite_q; // @[axi4_to_ahb.scala 229:33] - wire _T_192 = _T_189 & _T_108; // @[axi4_to_ahb.scala 229:48] - wire _T_281 = 3'h4 == buf_state; // @[Conditional.scala 37:30] - wire _GEN_15 = _T_281 & _T_192; // @[Conditional.scala 39:67] - wire _GEN_19 = _T_188 ? _T_192 : _GEN_15; // @[Conditional.scala 39:67] - wire _GEN_40 = _T_186 ? 1'h0 : _GEN_19; // @[Conditional.scala 39:67] - wire _GEN_59 = _T_175 ? 1'h0 : _GEN_40; // @[Conditional.scala 39:67] - wire _GEN_79 = _T_136 ? 1'h0 : _GEN_59; // @[Conditional.scala 39:67] - wire _GEN_95 = _T_101 ? 1'h0 : _GEN_79; // @[Conditional.scala 39:67] - wire trxn_done = _T_49 ? 1'h0 : _GEN_95; // @[Conditional.scala 40:58] - reg cmd_doneQ; // @[axi4_to_ahb.scala 319:52] - wire _T_282 = cmd_doneQ & ahb_hready_q; // @[axi4_to_ahb.scala 239:34] - wire _T_283 = _T_282 | ahb_hresp_q; // @[axi4_to_ahb.scala 239:50] - wire _T_440 = 3'h5 == buf_state; // @[Conditional.scala 37:30] - wire _GEN_3 = _T_281 ? _T_283 : _T_440; // @[Conditional.scala 39:67] - wire _GEN_20 = _T_188 ? trxn_done : _GEN_3; // @[Conditional.scala 39:67] - wire _GEN_35 = _T_186 ? _T_156 : _GEN_20; // @[Conditional.scala 39:67] - wire _GEN_51 = _T_175 ? _T_111 : _GEN_35; // @[Conditional.scala 39:67] - wire _GEN_69 = _T_136 ? _T_156 : _GEN_51; // @[Conditional.scala 39:67] - wire _GEN_83 = _T_101 ? _T_111 : _GEN_69; // @[Conditional.scala 39:67] - wire buf_state_en = _T_49 ? master_valid : _GEN_83; // @[Conditional.scala 40:58] - wire [1:0] _T_14 = wr_cmd_vld ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 142:20] - wire [2:0] master_opc = {{1'd0}, _T_14}; // @[axi4_to_ahb.scala 142:14] - wire _T_51 = master_opc[2:1] == 2'h1; // @[axi4_to_ahb.scala 168:41] - wire _GEN_8 = _T_281 & _T_51; // @[Conditional.scala 39:67] - wire _GEN_29 = _T_188 ? 1'h0 : _GEN_8; // @[Conditional.scala 39:67] - wire _GEN_46 = _T_186 ? 1'h0 : _GEN_29; // @[Conditional.scala 39:67] - wire _GEN_63 = _T_175 ? 1'h0 : _GEN_46; // @[Conditional.scala 39:67] - wire _GEN_81 = _T_136 ? 1'h0 : _GEN_63; // @[Conditional.scala 39:67] - wire _GEN_97 = _T_101 ? 1'h0 : _GEN_81; // @[Conditional.scala 39:67] - wire buf_write_in = _T_49 ? _T_51 : _GEN_97; // @[Conditional.scala 40:58] - wire [2:0] _T_53 = buf_write_in ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 169:26] - wire _T_103 = master_opc == 3'h0; // @[axi4_to_ahb.scala 182:61] - wire _T_104 = master_valid & _T_103; // @[axi4_to_ahb.scala 182:41] - wire [2:0] _T_106 = _T_104 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 182:26] - wire _T_124 = _T_106 == 3'h6; // @[axi4_to_ahb.scala 186:174] - wire _T_125 = _T_111 & _T_124; // @[axi4_to_ahb.scala 186:88] - wire _T_137 = ~ahb_hresp_q; // @[axi4_to_ahb.scala 194:39] - wire _T_138 = ahb_hready_q & _T_137; // @[axi4_to_ahb.scala 194:37] - wire _T_141 = master_valid & _T_51; // @[axi4_to_ahb.scala 194:70] - wire _T_142 = ~_T_141; // @[axi4_to_ahb.scala 194:55] - wire _T_143 = _T_138 & _T_142; // @[axi4_to_ahb.scala 194:53] - wire _T_285 = buf_state_en & _T_137; // @[axi4_to_ahb.scala 240:36] - wire _GEN_4 = _T_281 & _T_285; // @[Conditional.scala 39:67] - wire _GEN_26 = _T_188 ? 1'h0 : _GEN_4; // @[Conditional.scala 39:67] - wire _GEN_45 = _T_186 ? 1'h0 : _GEN_26; // @[Conditional.scala 39:67] - wire _GEN_62 = _T_175 ? 1'h0 : _GEN_45; // @[Conditional.scala 39:67] - wire _GEN_66 = _T_136 ? _T_143 : _GEN_62; // @[Conditional.scala 39:67] - wire _GEN_86 = _T_101 ? _T_125 : _GEN_66; // @[Conditional.scala 39:67] - wire master_ready = _T_49 | _GEN_86; // @[Conditional.scala 40:58] - wire _T_149 = master_valid & master_ready; // @[axi4_to_ahb.scala 196:82] - wire _T_152 = _T_149 & _T_103; // @[axi4_to_ahb.scala 196:97] - wire [2:0] _T_154 = _T_152 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 196:67] - wire [2:0] _T_155 = ahb_hresp_q ? 3'h7 : _T_154; // @[axi4_to_ahb.scala 196:26] - wire [2:0] _T_293 = _T_51 ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 241:99] - wire [2:0] _T_294 = master_valid ? _T_293 : 3'h0; // @[axi4_to_ahb.scala 241:65] - wire [2:0] _T_295 = ahb_hresp_q ? 3'h5 : _T_294; // @[axi4_to_ahb.scala 241:26] - wire [2:0] _GEN_5 = _T_281 ? _T_295 : 3'h0; // @[Conditional.scala 39:67] - wire [2:0] _GEN_18 = _T_188 ? 3'h4 : _GEN_5; // @[Conditional.scala 39:67] - wire [2:0] _GEN_34 = _T_186 ? 3'h5 : _GEN_18; // @[Conditional.scala 39:67] - wire [2:0] _GEN_50 = _T_175 ? 3'h3 : _GEN_34; // @[Conditional.scala 39:67] - wire [2:0] _GEN_68 = _T_136 ? _T_155 : _GEN_50; // @[Conditional.scala 39:67] - wire [2:0] _GEN_82 = _T_101 ? _T_106 : _GEN_68; // @[Conditional.scala 39:67] - wire [2:0] buf_nxtstate = _T_49 ? _T_53 : _GEN_82; // @[Conditional.scala 40:58] - reg [31:0] wrbuf_addr; // @[lib.scala 374:16] - wire [31:0] master_addr = wr_cmd_vld ? wrbuf_addr : io_axi_ar_bits_addr; // @[axi4_to_ahb.scala 143:21] - reg [2:0] wrbuf_size; // @[Reg.scala 27:20] - wire [2:0] master_size = wr_cmd_vld ? wrbuf_size : io_axi_ar_bits_size; // @[axi4_to_ahb.scala 144:21] - reg [7:0] wrbuf_byteen; // @[Reg.scala 27:20] - reg [63:0] wrbuf_data; // @[lib.scala 374:16] - wire _T_358 = buf_nxtstate != 3'h5; // @[axi4_to_ahb.scala 251:55] - wire _T_359 = buf_state_en & _T_358; // @[axi4_to_ahb.scala 251:39] - wire _GEN_14 = _T_281 ? _T_359 : _T_440; // @[Conditional.scala 39:67] - wire _GEN_33 = _T_188 ? 1'h0 : _GEN_14; // @[Conditional.scala 39:67] - wire _GEN_49 = _T_186 ? 1'h0 : _GEN_33; // @[Conditional.scala 39:67] - wire _GEN_52 = _T_175 ? buf_state_en : _GEN_49; // @[Conditional.scala 39:67] - wire _GEN_73 = _T_136 ? _T_285 : _GEN_52; // @[Conditional.scala 39:67] - wire _GEN_94 = _T_101 ? 1'h0 : _GEN_73; // @[Conditional.scala 39:67] - wire slave_valid_pre = _T_49 ? 1'h0 : _GEN_94; // @[Conditional.scala 40:58] - wire buf_clk = rvclkhdr_6_io_l1clk; // @[axi4_to_ahb.scala 118:21 axi4_to_ahb.scala 332:12] - reg slvbuf_write; // @[Reg.scala 27:20] - wire [1:0] _T_596 = slvbuf_write ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 285:23] - reg slvbuf_error; // @[Reg.scala 27:20] - wire [1:0] _T_598 = slvbuf_error ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_599 = _T_598 & 2'h2; // @[axi4_to_ahb.scala 285:88] - wire [3:0] slave_opc = {_T_596,_T_599}; // @[Cat.scala 29:58] - wire [1:0] _T_30 = slave_opc[1] ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 150:55] - wire _T_35 = slave_opc[3:2] == 2'h0; // @[axi4_to_ahb.scala 153:66] - reg [31:0] last_bus_addr; // @[Reg.scala 27:20] - wire [63:0] _T_603 = {last_bus_addr,last_bus_addr}; // @[Cat.scala 29:58] - wire _T_604 = buf_state == 3'h5; // @[axi4_to_ahb.scala 286:91] - reg [63:0] buf_data; // @[lib.scala 374:16] - wire ahbm_data_clk = rvclkhdr_9_io_l1clk; // @[axi4_to_ahb.scala 26:27 axi4_to_ahb.scala 335:17] - reg [63:0] ahb_hrdata_q; // @[axi4_to_ahb.scala 325:57] - wire [63:0] _T_607 = _T_604 ? buf_data : ahb_hrdata_q; // @[axi4_to_ahb.scala 286:79] - wire _T_44 = io_axi_aw_valid & io_axi_aw_ready; // @[axi4_to_ahb.scala 160:57] - wire _T_45 = io_axi_w_valid & io_axi_w_ready; // @[axi4_to_ahb.scala 160:94] - wire _T_46 = _T_44 | _T_45; // @[axi4_to_ahb.scala 160:76] - wire _T_55 = buf_nxtstate == 3'h2; // @[axi4_to_ahb.scala 172:54] - wire _T_56 = buf_state_en & _T_55; // @[axi4_to_ahb.scala 172:38] - wire [2:0] _T_87 = wrbuf_byteen[6] ? 3'h6 : 3'h7; // @[Mux.scala 98:16] - wire [2:0] _T_88 = wrbuf_byteen[5] ? 3'h5 : _T_87; // @[Mux.scala 98:16] - wire [2:0] _T_89 = wrbuf_byteen[4] ? 3'h4 : _T_88; // @[Mux.scala 98:16] - wire [2:0] _T_90 = wrbuf_byteen[3] ? 3'h3 : _T_89; // @[Mux.scala 98:16] - wire [2:0] _T_91 = wrbuf_byteen[2] ? 3'h2 : _T_90; // @[Mux.scala 98:16] - wire [2:0] _T_92 = wrbuf_byteen[1] ? 3'h1 : _T_91; // @[Mux.scala 98:16] - wire [2:0] _T_93 = wrbuf_byteen[0] ? 3'h0 : _T_92; // @[Mux.scala 98:16] - wire [2:0] _T_95 = buf_write_in ? _T_93 : master_addr[2:0]; // @[axi4_to_ahb.scala 175:30] - wire _T_96 = buf_nxtstate == 3'h1; // @[axi4_to_ahb.scala 177:51] - wire _T_126 = master_ready & master_valid; // @[axi4_to_ahb.scala 188:33] - wire _T_162 = buf_nxtstate == 3'h6; // @[axi4_to_ahb.scala 203:64] - wire _T_163 = _T_126 & _T_162; // @[axi4_to_ahb.scala 203:48] - wire _T_164 = _T_163 & buf_state_en; // @[axi4_to_ahb.scala 203:79] - wire _T_349 = buf_state_en & buf_write_in; // @[axi4_to_ahb.scala 249:33] - wire _T_351 = _T_349 & _T_55; // @[axi4_to_ahb.scala 249:48] - wire _GEN_12 = _T_281 & _T_351; // @[Conditional.scala 39:67] - wire _GEN_32 = _T_188 ? 1'h0 : _GEN_12; // @[Conditional.scala 39:67] - wire _GEN_48 = _T_186 ? 1'h0 : _GEN_32; // @[Conditional.scala 39:67] - wire _GEN_65 = _T_175 ? 1'h0 : _GEN_48; // @[Conditional.scala 39:67] - wire _GEN_75 = _T_136 ? _T_164 : _GEN_65; // @[Conditional.scala 39:67] - wire _GEN_88 = _T_101 ? _T_126 : _GEN_75; // @[Conditional.scala 39:67] - wire bypass_en = _T_49 ? buf_state_en : _GEN_88; // @[Conditional.scala 40:58] - wire [1:0] _T_99 = bypass_en ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_100 = _T_99 & 2'h2; // @[axi4_to_ahb.scala 178:49] - wire _T_112 = ~master_valid; // @[axi4_to_ahb.scala 184:34] - wire _T_113 = buf_state_en & _T_112; // @[axi4_to_ahb.scala 184:32] - reg [31:0] buf_addr; // @[lib.scala 374:16] - wire [2:0] _T_130 = bypass_en ? master_addr[2:0] : buf_addr[2:0]; // @[axi4_to_ahb.scala 189:30] - wire _T_131 = ~buf_state_en; // @[axi4_to_ahb.scala 190:48] - wire _T_132 = _T_131 | bypass_en; // @[axi4_to_ahb.scala 190:62] - wire [1:0] _T_134 = _T_132 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_135 = 2'h2 & _T_134; // @[axi4_to_ahb.scala 190:36] - wire _T_169 = buf_nxtstate != 3'h6; // @[axi4_to_ahb.scala 205:63] - wire _T_170 = _T_169 & buf_state_en; // @[axi4_to_ahb.scala 205:78] - wire _T_171 = ~_T_170; // @[axi4_to_ahb.scala 205:47] - wire [1:0] _T_173 = _T_171 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_174 = 2'h2 & _T_173; // @[axi4_to_ahb.scala 205:36] - wire [1:0] _T_184 = _T_131 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_185 = 2'h2 & _T_184; // @[axi4_to_ahb.scala 215:41] - reg [2:0] buf_cmd_byte_ptrQ; // @[Reg.scala 27:20] - reg [7:0] buf_byteen; // @[Reg.scala 27:20] - wire [2:0] _T_197 = buf_cmd_byte_ptrQ + 3'h1; // @[axi4_to_ahb.scala 135:52] - wire _T_200 = 3'h0 >= _T_197; // @[axi4_to_ahb.scala 136:62] - wire _T_201 = buf_byteen[0] & _T_200; // @[axi4_to_ahb.scala 136:48] - wire _T_203 = 3'h1 >= _T_197; // @[axi4_to_ahb.scala 136:62] - wire _T_204 = buf_byteen[1] & _T_203; // @[axi4_to_ahb.scala 136:48] - wire _T_206 = 3'h2 >= _T_197; // @[axi4_to_ahb.scala 136:62] - wire _T_207 = buf_byteen[2] & _T_206; // @[axi4_to_ahb.scala 136:48] - wire _T_209 = 3'h3 >= _T_197; // @[axi4_to_ahb.scala 136:62] - wire _T_210 = buf_byteen[3] & _T_209; // @[axi4_to_ahb.scala 136:48] - wire _T_212 = 3'h4 >= _T_197; // @[axi4_to_ahb.scala 136:62] - wire _T_213 = buf_byteen[4] & _T_212; // @[axi4_to_ahb.scala 136:48] - wire _T_215 = 3'h5 >= _T_197; // @[axi4_to_ahb.scala 136:62] - wire _T_216 = buf_byteen[5] & _T_215; // @[axi4_to_ahb.scala 136:48] - wire _T_218 = 3'h6 >= _T_197; // @[axi4_to_ahb.scala 136:62] - wire _T_219 = buf_byteen[6] & _T_218; // @[axi4_to_ahb.scala 136:48] - wire [2:0] _T_224 = _T_219 ? 3'h6 : 3'h7; // @[Mux.scala 98:16] - wire [2:0] _T_225 = _T_216 ? 3'h5 : _T_224; // @[Mux.scala 98:16] - wire [2:0] _T_226 = _T_213 ? 3'h4 : _T_225; // @[Mux.scala 98:16] - wire [2:0] _T_227 = _T_210 ? 3'h3 : _T_226; // @[Mux.scala 98:16] - wire [2:0] _T_228 = _T_207 ? 3'h2 : _T_227; // @[Mux.scala 98:16] - wire [2:0] _T_229 = _T_204 ? 3'h1 : _T_228; // @[Mux.scala 98:16] - wire [2:0] _T_230 = _T_201 ? 3'h0 : _T_229; // @[Mux.scala 98:16] - wire [2:0] _T_231 = trxn_done ? _T_230 : buf_cmd_byte_ptrQ; // @[axi4_to_ahb.scala 233:30] - wire _T_232 = buf_cmd_byte_ptrQ == 3'h7; // @[axi4_to_ahb.scala 234:65] - reg buf_aligned; // @[Reg.scala 27:20] - wire _T_233 = buf_aligned | _T_232; // @[axi4_to_ahb.scala 234:44] - wire [7:0] _T_271 = buf_byteen >> _T_230; // @[axi4_to_ahb.scala 234:92] - wire _T_273 = ~_T_271[0]; // @[axi4_to_ahb.scala 234:163] - wire _T_274 = _T_233 | _T_273; // @[axi4_to_ahb.scala 234:79] - wire _T_275 = trxn_done & _T_274; // @[axi4_to_ahb.scala 234:29] - wire _T_346 = _T_232 | _T_273; // @[axi4_to_ahb.scala 248:38] - wire _T_347 = _T_109 & _T_346; // @[axi4_to_ahb.scala 247:80] - wire _T_348 = ahb_hresp_q | _T_347; // @[axi4_to_ahb.scala 247:34] - wire _GEN_11 = _T_281 & _T_348; // @[Conditional.scala 39:67] - wire _GEN_24 = _T_188 ? _T_275 : _GEN_11; // @[Conditional.scala 39:67] - wire _GEN_43 = _T_186 ? 1'h0 : _GEN_24; // @[Conditional.scala 39:67] - wire _GEN_61 = _T_175 ? 1'h0 : _GEN_43; // @[Conditional.scala 39:67] - wire _GEN_74 = _T_136 ? _T_113 : _GEN_61; // @[Conditional.scala 39:67] - wire _GEN_84 = _T_101 ? _T_113 : _GEN_74; // @[Conditional.scala 39:67] - wire cmd_done = _T_49 ? 1'h0 : _GEN_84; // @[Conditional.scala 40:58] - wire _T_276 = cmd_done | cmd_doneQ; // @[axi4_to_ahb.scala 235:47] - wire _T_277 = ~_T_276; // @[axi4_to_ahb.scala 235:36] - wire [1:0] _T_279 = _T_277 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_280 = _T_279 & 2'h2; // @[axi4_to_ahb.scala 235:61] - wire _T_300 = _T_55 | _T_96; // @[axi4_to_ahb.scala 245:62] - wire _T_301 = buf_state_en & _T_300; // @[axi4_to_ahb.scala 245:33] - wire _T_354 = _T_277 | bypass_en; // @[axi4_to_ahb.scala 250:61] - wire [1:0] _T_356 = _T_354 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_357 = _T_356 & 2'h2; // @[axi4_to_ahb.scala 250:75] - wire _T_364 = trxn_done | bypass_en; // @[axi4_to_ahb.scala 253:40] - wire [2:0] _T_439 = bypass_en ? _T_93 : _T_231; // @[axi4_to_ahb.scala 254:30] - wire _GEN_6 = _T_281 & ahb_hresp_q; // @[Conditional.scala 39:67] - wire _GEN_7 = _T_281 ? buf_state_en : _T_440; // @[Conditional.scala 39:67] - wire _GEN_9 = _T_281 & _T_301; // @[Conditional.scala 39:67] - wire _GEN_30 = _T_188 ? 1'h0 : _GEN_9; // @[Conditional.scala 39:67] - wire _GEN_47 = _T_186 ? 1'h0 : _GEN_30; // @[Conditional.scala 39:67] - wire _GEN_64 = _T_175 ? 1'h0 : _GEN_47; // @[Conditional.scala 39:67] - wire _GEN_67 = _T_136 ? _T_152 : _GEN_64; // @[Conditional.scala 39:67] - wire _GEN_87 = _T_101 ? master_ready : _GEN_67; // @[Conditional.scala 39:67] - wire buf_wr_en = _T_49 ? buf_state_en : _GEN_87; // @[Conditional.scala 40:58] - wire _GEN_10 = _T_281 & buf_wr_en; // @[Conditional.scala 39:67] - wire [1:0] _GEN_13 = _T_281 ? _T_357 : 2'h0; // @[Conditional.scala 39:67] - wire _GEN_16 = _T_281 & _T_364; // @[Conditional.scala 39:67] - wire [2:0] _GEN_17 = _T_281 ? _T_439 : 3'h0; // @[Conditional.scala 39:67] - wire _GEN_21 = _T_188 ? buf_state_en : _GEN_16; // @[Conditional.scala 39:67] - wire _GEN_22 = _T_188 & buf_state_en; // @[Conditional.scala 39:67] - wire [2:0] _GEN_23 = _T_188 ? _T_231 : _GEN_17; // @[Conditional.scala 39:67] - wire [1:0] _GEN_25 = _T_188 ? _T_280 : _GEN_13; // @[Conditional.scala 39:67] - wire _GEN_28 = _T_188 ? 1'h0 : _GEN_7; // @[Conditional.scala 39:67] - wire _GEN_31 = _T_188 ? 1'h0 : _GEN_10; // @[Conditional.scala 39:67] - wire _GEN_36 = _T_186 ? buf_state_en : _GEN_31; // @[Conditional.scala 39:67] - wire _GEN_38 = _T_186 ? buf_state_en : _GEN_28; // @[Conditional.scala 39:67] - wire _GEN_39 = _T_186 ? buf_state_en : _GEN_22; // @[Conditional.scala 39:67] - wire _GEN_41 = _T_186 ? 1'h0 : _GEN_21; // @[Conditional.scala 39:67] - wire [2:0] _GEN_42 = _T_186 ? 3'h0 : _GEN_23; // @[Conditional.scala 39:67] - wire [1:0] _GEN_44 = _T_186 ? 2'h0 : _GEN_25; // @[Conditional.scala 39:67] - wire _GEN_53 = _T_175 ? buf_state_en : _GEN_39; // @[Conditional.scala 39:67] - wire [2:0] _GEN_54 = _T_175 ? buf_addr[2:0] : _GEN_42; // @[Conditional.scala 39:67] - wire [1:0] _GEN_55 = _T_175 ? _T_185 : _GEN_44; // @[Conditional.scala 39:67] - wire _GEN_56 = _T_175 ? 1'h0 : _GEN_36; // @[Conditional.scala 39:67] - wire _GEN_58 = _T_175 ? 1'h0 : _GEN_38; // @[Conditional.scala 39:67] - wire _GEN_60 = _T_175 ? 1'h0 : _GEN_41; // @[Conditional.scala 39:67] - wire _GEN_70 = _T_136 ? buf_state_en : _GEN_56; // @[Conditional.scala 39:67] - wire _GEN_72 = _T_136 ? buf_state_en : _GEN_58; // @[Conditional.scala 39:67] - wire [2:0] _GEN_76 = _T_136 ? _T_130 : _GEN_54; // @[Conditional.scala 39:67] - wire [1:0] _GEN_77 = _T_136 ? _T_174 : _GEN_55; // @[Conditional.scala 39:67] - wire _GEN_78 = _T_136 ? buf_wr_en : _GEN_53; // @[Conditional.scala 39:67] - wire _GEN_80 = _T_136 ? 1'h0 : _GEN_60; // @[Conditional.scala 39:67] - wire _GEN_85 = _T_101 ? buf_state_en : _GEN_78; // @[Conditional.scala 39:67] - wire [2:0] _GEN_89 = _T_101 ? _T_130 : _GEN_76; // @[Conditional.scala 39:67] - wire [1:0] _GEN_90 = _T_101 ? _T_135 : _GEN_77; // @[Conditional.scala 39:67] - wire _GEN_91 = _T_101 ? 1'h0 : _GEN_70; // @[Conditional.scala 39:67] - wire _GEN_93 = _T_101 ? 1'h0 : _GEN_72; // @[Conditional.scala 39:67] - wire _GEN_96 = _T_101 ? 1'h0 : _GEN_80; // @[Conditional.scala 39:67] - wire buf_data_wr_en = _T_49 ? _T_56 : _GEN_91; // @[Conditional.scala 40:58] - wire buf_cmd_byte_ptr_en = _T_49 ? buf_state_en : _GEN_96; // @[Conditional.scala 40:58] - wire [2:0] buf_cmd_byte_ptr = _T_49 ? _T_95 : _GEN_89; // @[Conditional.scala 40:58] - wire slvbuf_wr_en = _T_49 ? 1'h0 : _GEN_85; // @[Conditional.scala 40:58] - wire slvbuf_error_en = _T_49 ? 1'h0 : _GEN_93; // @[Conditional.scala 40:58] - wire _T_535 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 271:24] - wire _T_536 = _T_103 | _T_535; // @[axi4_to_ahb.scala 270:48] - wire _T_538 = master_size[1:0] == 2'h1; // @[axi4_to_ahb.scala 271:54] - wire _T_539 = _T_536 | _T_538; // @[axi4_to_ahb.scala 271:33] - wire _T_541 = master_size[1:0] == 2'h2; // @[axi4_to_ahb.scala 271:93] - wire _T_542 = _T_539 | _T_541; // @[axi4_to_ahb.scala 271:72] - wire _T_544 = master_size[1:0] == 2'h3; // @[axi4_to_ahb.scala 272:25] - wire _T_546 = wrbuf_byteen == 8'h3; // @[axi4_to_ahb.scala 272:62] - wire _T_548 = wrbuf_byteen == 8'hc; // @[axi4_to_ahb.scala 272:97] - wire _T_549 = _T_546 | _T_548; // @[axi4_to_ahb.scala 272:74] - wire _T_551 = wrbuf_byteen == 8'h30; // @[axi4_to_ahb.scala 272:132] - wire _T_552 = _T_549 | _T_551; // @[axi4_to_ahb.scala 272:109] - wire _T_554 = wrbuf_byteen == 8'hc0; // @[axi4_to_ahb.scala 272:168] - wire _T_555 = _T_552 | _T_554; // @[axi4_to_ahb.scala 272:145] - wire _T_557 = wrbuf_byteen == 8'hf; // @[axi4_to_ahb.scala 273:28] - wire _T_558 = _T_555 | _T_557; // @[axi4_to_ahb.scala 272:181] - wire _T_560 = wrbuf_byteen == 8'hf0; // @[axi4_to_ahb.scala 273:63] - wire _T_561 = _T_558 | _T_560; // @[axi4_to_ahb.scala 273:40] - wire _T_563 = wrbuf_byteen == 8'hff; // @[axi4_to_ahb.scala 273:99] - wire _T_564 = _T_561 | _T_563; // @[axi4_to_ahb.scala 273:76] - wire _T_565 = _T_544 & _T_564; // @[axi4_to_ahb.scala 272:38] - wire buf_aligned_in = _T_542 | _T_565; // @[axi4_to_ahb.scala 271:106] - wire _T_444 = buf_aligned_in & _T_51; // @[axi4_to_ahb.scala 265:60] - wire [2:0] _T_461 = _T_548 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_462 = 3'h2 & _T_461; // @[axi4_to_ahb.scala 128:15] - wire _T_468 = _T_560 | _T_546; // @[axi4_to_ahb.scala 129:56] - wire [2:0] _T_470 = _T_468 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_471 = 3'h4 & _T_470; // @[axi4_to_ahb.scala 129:15] - wire [2:0] _T_472 = _T_462 | _T_471; // @[axi4_to_ahb.scala 128:63] - wire [2:0] _T_476 = _T_554 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_477 = 3'h6 & _T_476; // @[axi4_to_ahb.scala 130:15] - wire [2:0] _T_478 = _T_472 | _T_477; // @[axi4_to_ahb.scala 129:96] - wire [2:0] _T_485 = _T_444 ? _T_478 : master_addr[2:0]; // @[axi4_to_ahb.scala 265:43] - wire _T_489 = buf_state == 3'h3; // @[axi4_to_ahb.scala 268:33] - wire _T_495 = buf_aligned_in & _T_544; // @[axi4_to_ahb.scala 269:38] - wire _T_498 = _T_495 & _T_51; // @[axi4_to_ahb.scala 269:71] - wire [1:0] _T_504 = _T_563 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire _T_510 = _T_560 | _T_557; // @[axi4_to_ahb.scala 122:55] - wire [1:0] _T_512 = _T_510 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_513 = 2'h2 & _T_512; // @[axi4_to_ahb.scala 122:16] - wire [1:0] _T_514 = _T_504 | _T_513; // @[axi4_to_ahb.scala 121:64] - wire _T_519 = _T_554 | _T_551; // @[axi4_to_ahb.scala 123:60] - wire _T_522 = _T_519 | _T_548; // @[axi4_to_ahb.scala 123:89] - wire _T_525 = _T_522 | _T_546; // @[axi4_to_ahb.scala 123:123] - wire [1:0] _T_527 = _T_525 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_528 = 2'h1 & _T_527; // @[axi4_to_ahb.scala 123:21] - wire [1:0] _T_529 = _T_514 | _T_528; // @[axi4_to_ahb.scala 122:93] - wire [1:0] _T_531 = _T_498 ? _T_529 : master_size[1:0]; // @[axi4_to_ahb.scala 269:21] - wire [31:0] _T_570 = {master_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] - wire [31:0] _T_573 = {buf_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] - wire [1:0] _T_577 = buf_aligned_in ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [2:0] buf_size_in = {{1'd0}, _T_531}; // @[axi4_to_ahb.scala 269:15] - wire [1:0] _T_579 = _T_577 & buf_size_in[1:0]; // @[axi4_to_ahb.scala 276:81] - wire [2:0] _T_580 = {1'h0,_T_579}; // @[Cat.scala 29:58] - wire [1:0] _T_582 = buf_aligned ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - reg [1:0] buf_size; // @[Reg.scala 27:20] - wire [1:0] _T_584 = _T_582 & buf_size; // @[axi4_to_ahb.scala 276:138] - wire [2:0] _T_585 = {1'h0,_T_584}; // @[Cat.scala 29:58] - reg buf_write; // @[Reg.scala 27:20] - wire _T_611 = io_ahb_out_htrans != 2'h0; // @[axi4_to_ahb.scala 289:44] - wire _T_612 = _T_611 & io_ahb_in_hready; // @[axi4_to_ahb.scala 289:56] - wire last_addr_en = _T_612 & io_ahb_out_hwrite; // @[axi4_to_ahb.scala 289:75] - wire wrbuf_en = _T_44 & master_ready; // @[axi4_to_ahb.scala 291:49] - wire wrbuf_data_en = _T_45 & master_ready; // @[axi4_to_ahb.scala 292:52] - wire wrbuf_cmd_sent = _T_149 & _T_51; // @[axi4_to_ahb.scala 293:49] - wire _T_622 = ~wrbuf_en; // @[axi4_to_ahb.scala 294:33] - wire wrbuf_rst = wrbuf_cmd_sent & _T_622; // @[axi4_to_ahb.scala 294:31] - wire _T_624 = ~wrbuf_cmd_sent; // @[axi4_to_ahb.scala 296:36] - wire _T_625 = wrbuf_vld & _T_624; // @[axi4_to_ahb.scala 296:34] - wire _T_626 = ~_T_625; // @[axi4_to_ahb.scala 296:22] - wire _T_629 = wrbuf_data_vld & _T_624; // @[axi4_to_ahb.scala 297:38] - wire _T_630 = ~_T_629; // @[axi4_to_ahb.scala 297:21] - wire _T_633 = ~wr_cmd_vld; // @[axi4_to_ahb.scala 298:22] - wire _T_636 = wrbuf_en | wrbuf_vld; // @[axi4_to_ahb.scala 301:55] - wire _T_637 = ~wrbuf_rst; // @[axi4_to_ahb.scala 301:91] - wire _T_641 = wrbuf_data_en | wrbuf_data_vld; // @[axi4_to_ahb.scala 302:55] - wire _T_691 = ~slave_valid_pre; // @[axi4_to_ahb.scala 319:92] - wire _T_704 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 327:43] - wire _T_705 = _T_704 | io_clk_override; // @[axi4_to_ahb.scala 327:58] - wire _T_708 = io_ahb_in_hready & io_ahb_out_htrans[1]; // @[axi4_to_ahb.scala 328:57] - wire _T_709 = _T_708 | io_clk_override; // @[axi4_to_ahb.scala 328:81] - wire _T_711 = buf_state != 3'h0; // @[axi4_to_ahb.scala 329:50] - wire _T_712 = _T_711 | io_clk_override; // @[axi4_to_ahb.scala 329:60] - rvclkhdr rvclkhdr ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_io_l1clk), - .io_clk(rvclkhdr_io_clk), - .io_en(rvclkhdr_io_en), - .io_scan_mode(rvclkhdr_io_scan_mode) - ); - rvclkhdr rvclkhdr_1 ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_1_io_l1clk), - .io_clk(rvclkhdr_1_io_clk), - .io_en(rvclkhdr_1_io_en), - .io_scan_mode(rvclkhdr_1_io_scan_mode) - ); - rvclkhdr rvclkhdr_2 ( // @[lib.scala 368:23] - .io_l1clk(rvclkhdr_2_io_l1clk), - .io_clk(rvclkhdr_2_io_clk), - .io_en(rvclkhdr_2_io_en), - .io_scan_mode(rvclkhdr_2_io_scan_mode) - ); - rvclkhdr rvclkhdr_3 ( // @[lib.scala 368:23] - .io_l1clk(rvclkhdr_3_io_l1clk), - .io_clk(rvclkhdr_3_io_clk), - .io_en(rvclkhdr_3_io_en), - .io_scan_mode(rvclkhdr_3_io_scan_mode) - ); - rvclkhdr rvclkhdr_4 ( // @[lib.scala 368:23] - .io_l1clk(rvclkhdr_4_io_l1clk), - .io_clk(rvclkhdr_4_io_clk), - .io_en(rvclkhdr_4_io_en), - .io_scan_mode(rvclkhdr_4_io_scan_mode) - ); - rvclkhdr rvclkhdr_5 ( // @[lib.scala 368:23] - .io_l1clk(rvclkhdr_5_io_l1clk), - .io_clk(rvclkhdr_5_io_clk), - .io_en(rvclkhdr_5_io_en), - .io_scan_mode(rvclkhdr_5_io_scan_mode) - ); - rvclkhdr rvclkhdr_6 ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_6_io_l1clk), - .io_clk(rvclkhdr_6_io_clk), - .io_en(rvclkhdr_6_io_en), - .io_scan_mode(rvclkhdr_6_io_scan_mode) - ); - rvclkhdr rvclkhdr_7 ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_7_io_l1clk), - .io_clk(rvclkhdr_7_io_clk), - .io_en(rvclkhdr_7_io_en), - .io_scan_mode(rvclkhdr_7_io_scan_mode) - ); - rvclkhdr rvclkhdr_8 ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_8_io_l1clk), - .io_clk(rvclkhdr_8_io_clk), - .io_en(rvclkhdr_8_io_en), - .io_scan_mode(rvclkhdr_8_io_scan_mode) - ); - rvclkhdr rvclkhdr_9 ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_9_io_l1clk), - .io_clk(rvclkhdr_9_io_clk), - .io_en(rvclkhdr_9_io_en), - .io_scan_mode(rvclkhdr_9_io_scan_mode) - ); - assign io_axi_aw_ready = _T_626 & master_ready; // @[axi4_to_ahb.scala 296:19] - assign io_axi_w_ready = _T_630 & master_ready; // @[axi4_to_ahb.scala 297:18] - assign io_axi_b_valid = slave_valid_pre & slave_opc[3]; // @[axi4_to_ahb.scala 149:18] - assign io_axi_b_bits_resp = slave_opc[0] ? 2'h2 : _T_30; // @[axi4_to_ahb.scala 150:22] - assign io_axi_ar_ready = _T_633 & master_ready; // @[axi4_to_ahb.scala 298:19] - assign io_axi_r_valid = slave_valid_pre & _T_35; // @[axi4_to_ahb.scala 153:18] - assign io_axi_r_bits_data = slvbuf_error ? _T_603 : _T_607; // @[axi4_to_ahb.scala 156:22] - assign io_axi_r_bits_resp = slave_opc[0] ? 2'h2 : _T_30; // @[axi4_to_ahb.scala 154:22] - assign io_ahb_out_haddr = bypass_en ? _T_570 : _T_573; // @[axi4_to_ahb.scala 275:20] - assign io_ahb_out_hsize = bypass_en ? _T_580 : _T_585; // @[axi4_to_ahb.scala 276:20] - assign io_ahb_out_htrans = _T_49 ? _T_100 : _GEN_90; // @[axi4_to_ahb.scala 22:21 axi4_to_ahb.scala 178:25 axi4_to_ahb.scala 190:25 axi4_to_ahb.scala 205:25 axi4_to_ahb.scala 215:25 axi4_to_ahb.scala 235:25 axi4_to_ahb.scala 250:25] - assign io_ahb_out_hwrite = bypass_en ? _T_51 : buf_write; // @[axi4_to_ahb.scala 281:21] - assign io_ahb_out_hwdata = buf_data; // @[axi4_to_ahb.scala 282:21] - assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_io_en = io_bus_clk_en; // @[lib.scala 345:16] - assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign rvclkhdr_1_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_1_io_en = io_bus_clk_en & _T_46; // @[lib.scala 345:16] - assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign rvclkhdr_2_io_clk = rvclkhdr_io_l1clk; // @[lib.scala 370:18] - assign rvclkhdr_2_io_en = _T_44 & master_ready; // @[lib.scala 371:17] - assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] - assign rvclkhdr_3_io_clk = rvclkhdr_io_l1clk; // @[lib.scala 370:18] - assign rvclkhdr_3_io_en = _T_45 & master_ready; // @[lib.scala 371:17] - assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] - assign rvclkhdr_4_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_4_io_en = buf_wr_en & io_bus_clk_en; // @[lib.scala 371:17] - assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] - assign rvclkhdr_5_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_5_io_en = buf_data_wr_en & io_bus_clk_en; // @[lib.scala 371:17] - assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] - assign rvclkhdr_6_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_6_io_en = io_bus_clk_en & _T_705; // @[lib.scala 345:16] - assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign rvclkhdr_7_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_7_io_en = io_bus_clk_en; // @[lib.scala 345:16] - assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign rvclkhdr_8_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_8_io_en = io_bus_clk_en & _T_709; // @[lib.scala 345:16] - assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign rvclkhdr_9_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_9_io_en = io_bus_clk_en & _T_712; // @[lib.scala 345:16] - assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] -`ifdef RANDOMIZE_GARBAGE_ASSIGN -`define RANDOMIZE -`endif -`ifdef RANDOMIZE_INVALID_ASSIGN -`define RANDOMIZE -`endif -`ifdef RANDOMIZE_REG_INIT -`define RANDOMIZE -`endif -`ifdef RANDOMIZE_MEM_INIT -`define RANDOMIZE -`endif -`ifndef RANDOM -`define RANDOM $random -`endif -`ifdef RANDOMIZE_MEM_INIT - integer initvar; -`endif -`ifndef SYNTHESIS -`ifdef FIRRTL_BEFORE_INITIAL -`FIRRTL_BEFORE_INITIAL -`endif -initial begin - `ifdef RANDOMIZE - `ifdef INIT_RANDOM - `INIT_RANDOM - `endif - `ifndef VERILATOR - `ifdef RANDOMIZE_DELAY - #`RANDOMIZE_DELAY begin end - `else - #0.002 begin end - `endif - `endif -`ifdef RANDOMIZE_REG_INIT - _RAND_0 = {1{`RANDOM}}; - buf_state = _RAND_0[2:0]; - _RAND_1 = {1{`RANDOM}}; - wrbuf_vld = _RAND_1[0:0]; - _RAND_2 = {1{`RANDOM}}; - wrbuf_data_vld = _RAND_2[0:0]; - _RAND_3 = {1{`RANDOM}}; - ahb_hready_q = _RAND_3[0:0]; - _RAND_4 = {1{`RANDOM}}; - ahb_htrans_q = _RAND_4[1:0]; - _RAND_5 = {1{`RANDOM}}; - ahb_hwrite_q = _RAND_5[0:0]; - _RAND_6 = {1{`RANDOM}}; - ahb_hresp_q = _RAND_6[0:0]; - _RAND_7 = {1{`RANDOM}}; - cmd_doneQ = _RAND_7[0:0]; - _RAND_8 = {1{`RANDOM}}; - wrbuf_addr = _RAND_8[31:0]; - _RAND_9 = {1{`RANDOM}}; - wrbuf_size = _RAND_9[2:0]; - _RAND_10 = {1{`RANDOM}}; - wrbuf_byteen = _RAND_10[7:0]; - _RAND_11 = {2{`RANDOM}}; - wrbuf_data = _RAND_11[63:0]; - _RAND_12 = {1{`RANDOM}}; - slvbuf_write = _RAND_12[0:0]; - _RAND_13 = {1{`RANDOM}}; - slvbuf_error = _RAND_13[0:0]; - _RAND_14 = {1{`RANDOM}}; - last_bus_addr = _RAND_14[31:0]; - _RAND_15 = {2{`RANDOM}}; - buf_data = _RAND_15[63:0]; - _RAND_16 = {2{`RANDOM}}; - ahb_hrdata_q = _RAND_16[63:0]; - _RAND_17 = {1{`RANDOM}}; - buf_addr = _RAND_17[31:0]; - _RAND_18 = {1{`RANDOM}}; - buf_cmd_byte_ptrQ = _RAND_18[2:0]; - _RAND_19 = {1{`RANDOM}}; - buf_byteen = _RAND_19[7:0]; - _RAND_20 = {1{`RANDOM}}; - buf_aligned = _RAND_20[0:0]; - _RAND_21 = {1{`RANDOM}}; - buf_size = _RAND_21[1:0]; - _RAND_22 = {1{`RANDOM}}; - buf_write = _RAND_22[0:0]; -`endif // RANDOMIZE_REG_INIT - if (reset) begin - buf_state = 3'h0; - end - if (reset) begin - wrbuf_vld = 1'h0; - end - if (reset) begin - wrbuf_data_vld = 1'h0; - end - if (reset) begin - ahb_hready_q = 1'h0; - end - if (reset) begin - ahb_htrans_q = 2'h0; - end - if (reset) begin - ahb_hwrite_q = 1'h0; - end - if (reset) begin - ahb_hresp_q = 1'h0; - end - if (reset) begin - cmd_doneQ = 1'h0; - end - if (reset) begin - wrbuf_addr = 32'h0; - end - if (reset) begin - wrbuf_size = 3'h0; - end - if (reset) begin - wrbuf_byteen = 8'h0; - end - if (reset) begin - wrbuf_data = 64'h0; - end - if (reset) begin - slvbuf_write = 1'h0; - end - if (reset) begin - slvbuf_error = 1'h0; - end - if (reset) begin - last_bus_addr = 32'h0; - end - if (reset) begin - buf_data = 64'h0; - end - if (reset) begin - ahb_hrdata_q = 64'h0; - end - if (reset) begin - buf_addr = 32'h0; - end - if (reset) begin - buf_cmd_byte_ptrQ = 3'h0; - end - if (reset) begin - buf_byteen = 8'h0; - end - if (reset) begin - buf_aligned = 1'h0; - end - if (reset) begin - buf_size = 2'h0; - end - if (reset) begin - buf_write = 1'h0; - end - `endif // RANDOMIZE -end // initial -`ifdef FIRRTL_AFTER_INITIAL -`FIRRTL_AFTER_INITIAL -`endif -`endif // SYNTHESIS - always @(posedge ahbm_clk or posedge reset) begin - if (reset) begin - buf_state <= 3'h0; - end else if (buf_state_en) begin - if (_T_49) begin - if (buf_write_in) begin - buf_state <= 3'h2; - end else begin - buf_state <= 3'h1; - end - end else if (_T_101) begin - if (_T_104) begin - buf_state <= 3'h6; - end else begin - buf_state <= 3'h3; - end - end else if (_T_136) begin - if (ahb_hresp_q) begin - buf_state <= 3'h7; - end else if (_T_152) begin - buf_state <= 3'h6; - end else begin - buf_state <= 3'h3; - end - end else if (_T_175) begin - buf_state <= 3'h3; - end else if (_T_186) begin - buf_state <= 3'h5; - end else if (_T_188) begin - buf_state <= 3'h4; - end else if (_T_281) begin - if (ahb_hresp_q) begin - buf_state <= 3'h5; - end else if (master_valid) begin - if (_T_51) begin - buf_state <= 3'h2; - end else begin - buf_state <= 3'h1; - end - end else begin - buf_state <= 3'h0; - end - end else begin - buf_state <= 3'h0; - end - end - end - always @(posedge bus_clk or posedge reset) begin - if (reset) begin - wrbuf_vld <= 1'h0; - end else begin - wrbuf_vld <= _T_636 & _T_637; - end - end - always @(posedge bus_clk or posedge reset) begin - if (reset) begin - wrbuf_data_vld <= 1'h0; - end else begin - wrbuf_data_vld <= _T_641 & _T_637; - end - end - always @(posedge ahbm_clk or posedge reset) begin - if (reset) begin - ahb_hready_q <= 1'h0; - end else begin - ahb_hready_q <= io_ahb_in_hready; - end - end - always @(posedge ahbm_clk or posedge reset) begin - if (reset) begin - ahb_htrans_q <= 2'h0; - end else begin - ahb_htrans_q <= io_ahb_out_htrans; - end - end - always @(posedge ahbm_addr_clk or posedge reset) begin - if (reset) begin - ahb_hwrite_q <= 1'h0; - end else begin - ahb_hwrite_q <= io_ahb_out_hwrite; - end - end - always @(posedge ahbm_clk or posedge reset) begin - if (reset) begin - ahb_hresp_q <= 1'h0; - end else begin - ahb_hresp_q <= io_ahb_in_hresp; - end - end - always @(posedge ahbm_clk or posedge reset) begin - if (reset) begin - cmd_doneQ <= 1'h0; - end else begin - cmd_doneQ <= _T_276 & _T_691; - end - end - always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin - if (reset) begin - wrbuf_addr <= 32'h0; - end else begin - wrbuf_addr <= io_axi_aw_bits_addr; - end - end - always @(posedge bus_clk or posedge reset) begin - if (reset) begin - wrbuf_size <= 3'h0; - end else if (wrbuf_en) begin - wrbuf_size <= io_axi_aw_bits_size; - end - end - always @(posedge bus_clk or posedge reset) begin - if (reset) begin - wrbuf_byteen <= 8'h0; - end else if (wrbuf_data_en) begin - wrbuf_byteen <= io_axi_w_bits_strb; - end - end - always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin - if (reset) begin - wrbuf_data <= 64'h0; - end else begin - wrbuf_data <= io_axi_w_bits_data; - end - end - always @(posedge buf_clk or posedge reset) begin - if (reset) begin - slvbuf_write <= 1'h0; - end else if (slvbuf_wr_en) begin - slvbuf_write <= buf_write; - end - end - always @(posedge ahbm_clk or posedge reset) begin - if (reset) begin - slvbuf_error <= 1'h0; - end else if (slvbuf_error_en) begin - if (_T_49) begin - slvbuf_error <= 1'h0; - end else if (_T_101) begin - slvbuf_error <= 1'h0; - end else if (_T_136) begin - slvbuf_error <= ahb_hresp_q; - end else if (_T_175) begin - slvbuf_error <= 1'h0; - end else if (_T_186) begin - slvbuf_error <= ahb_hresp_q; - end else if (_T_188) begin - slvbuf_error <= 1'h0; - end else begin - slvbuf_error <= _GEN_6; - end - end - end - always @(posedge ahbm_clk or posedge reset) begin - if (reset) begin - last_bus_addr <= 32'h0; - end else if (last_addr_en) begin - last_bus_addr <= io_ahb_out_haddr; - end - end - always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin - if (reset) begin - buf_data <= 64'h0; - end else if (_T_489) begin - buf_data <= ahb_hrdata_q; - end else begin - buf_data <= wrbuf_data; - end - end - always @(posedge ahbm_data_clk or posedge reset) begin - if (reset) begin - ahb_hrdata_q <= 64'h0; - end else begin - ahb_hrdata_q <= io_ahb_in_hrdata; - end - end - always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin - if (reset) begin - buf_addr <= 32'h0; - end else begin - buf_addr <= {master_addr[31:3],_T_485}; - end - end - always @(posedge ahbm_clk or posedge reset) begin - if (reset) begin - buf_cmd_byte_ptrQ <= 3'h0; - end else if (buf_cmd_byte_ptr_en) begin - if (_T_49) begin - if (buf_write_in) begin - if (wrbuf_byteen[0]) begin - buf_cmd_byte_ptrQ <= 3'h0; - end else if (wrbuf_byteen[1]) begin - buf_cmd_byte_ptrQ <= 3'h1; - end else if (wrbuf_byteen[2]) begin - buf_cmd_byte_ptrQ <= 3'h2; - end else if (wrbuf_byteen[3]) begin - buf_cmd_byte_ptrQ <= 3'h3; - end else if (wrbuf_byteen[4]) begin - buf_cmd_byte_ptrQ <= 3'h4; - end else if (wrbuf_byteen[5]) begin - buf_cmd_byte_ptrQ <= 3'h5; - end else if (wrbuf_byteen[6]) begin - buf_cmd_byte_ptrQ <= 3'h6; - end else begin - buf_cmd_byte_ptrQ <= 3'h7; - end - end else begin - buf_cmd_byte_ptrQ <= master_addr[2:0]; - end - end else if (_T_101) begin - if (bypass_en) begin - buf_cmd_byte_ptrQ <= master_addr[2:0]; - end else begin - buf_cmd_byte_ptrQ <= buf_addr[2:0]; - end - end else if (_T_136) begin - if (bypass_en) begin - buf_cmd_byte_ptrQ <= master_addr[2:0]; - end else begin - buf_cmd_byte_ptrQ <= buf_addr[2:0]; - end - end else if (_T_175) begin - buf_cmd_byte_ptrQ <= buf_addr[2:0]; - end else if (_T_186) begin - buf_cmd_byte_ptrQ <= 3'h0; - end else if (_T_188) begin - if (trxn_done) begin - if (_T_201) begin - buf_cmd_byte_ptrQ <= 3'h0; - end else if (_T_204) begin - buf_cmd_byte_ptrQ <= 3'h1; - end else if (_T_207) begin - buf_cmd_byte_ptrQ <= 3'h2; - end else if (_T_210) begin - buf_cmd_byte_ptrQ <= 3'h3; - end else if (_T_213) begin - buf_cmd_byte_ptrQ <= 3'h4; - end else if (_T_216) begin - buf_cmd_byte_ptrQ <= 3'h5; - end else if (_T_219) begin - buf_cmd_byte_ptrQ <= 3'h6; - end else begin - buf_cmd_byte_ptrQ <= 3'h7; - end - end - end else if (_T_281) begin - if (bypass_en) begin - if (wrbuf_byteen[0]) begin - buf_cmd_byte_ptrQ <= 3'h0; - end else if (wrbuf_byteen[1]) begin - buf_cmd_byte_ptrQ <= 3'h1; - end else if (wrbuf_byteen[2]) begin - buf_cmd_byte_ptrQ <= 3'h2; - end else if (wrbuf_byteen[3]) begin - buf_cmd_byte_ptrQ <= 3'h3; - end else if (wrbuf_byteen[4]) begin - buf_cmd_byte_ptrQ <= 3'h4; - end else if (wrbuf_byteen[5]) begin - buf_cmd_byte_ptrQ <= 3'h5; - end else if (wrbuf_byteen[6]) begin - buf_cmd_byte_ptrQ <= 3'h6; - end else begin - buf_cmd_byte_ptrQ <= 3'h7; - end - end else if (trxn_done) begin - if (_T_201) begin - buf_cmd_byte_ptrQ <= 3'h0; - end else if (_T_204) begin - buf_cmd_byte_ptrQ <= 3'h1; - end else if (_T_207) begin - buf_cmd_byte_ptrQ <= 3'h2; - end else if (_T_210) begin - buf_cmd_byte_ptrQ <= 3'h3; - end else if (_T_213) begin - buf_cmd_byte_ptrQ <= 3'h4; - end else if (_T_216) begin - buf_cmd_byte_ptrQ <= 3'h5; - end else if (_T_219) begin - buf_cmd_byte_ptrQ <= 3'h6; - end else begin - buf_cmd_byte_ptrQ <= 3'h7; - end - end - end else begin - buf_cmd_byte_ptrQ <= 3'h0; - end - end - end - always @(posedge buf_clk or posedge reset) begin - if (reset) begin - buf_byteen <= 8'h0; - end else if (buf_wr_en) begin - buf_byteen <= wrbuf_byteen; - end - end - always @(posedge buf_clk or posedge reset) begin - if (reset) begin - buf_aligned <= 1'h0; - end else if (buf_wr_en) begin - buf_aligned <= buf_aligned_in; - end - end - always @(posedge buf_clk or posedge reset) begin - if (reset) begin - buf_size <= 2'h0; - end else if (buf_wr_en) begin - buf_size <= buf_size_in[1:0]; - end - end - always @(posedge buf_clk or posedge reset) begin - if (reset) begin - buf_write <= 1'h0; - end else if (buf_wr_en) begin - if (_T_49) begin - buf_write <= _T_51; - end else if (_T_101) begin - buf_write <= 1'h0; - end else if (_T_136) begin - buf_write <= 1'h0; - end else if (_T_175) begin - buf_write <= 1'h0; - end else if (_T_186) begin - buf_write <= 1'h0; - end else if (_T_188) begin - buf_write <= 1'h0; - end else begin - buf_write <= _GEN_8; - end - end - end -endmodule -module axi4_to_ahb_1( - input clock, - input reset, - input io_scan_mode, - input io_bus_clk_en, - input io_clk_override, - output io_axi_aw_ready, - input io_axi_aw_valid, - input [2:0] io_axi_aw_bits_id, - input [31:0] io_axi_aw_bits_addr, - input [2:0] io_axi_aw_bits_size, - output io_axi_w_ready, - input io_axi_w_valid, - input [63:0] io_axi_w_bits_data, - input [7:0] io_axi_w_bits_strb, - output io_axi_b_valid, - output [1:0] io_axi_b_bits_resp, - output [2:0] io_axi_b_bits_id, - output io_axi_ar_ready, - input io_axi_ar_valid, - input [2:0] io_axi_ar_bits_id, - input [31:0] io_axi_ar_bits_addr, - input [2:0] io_axi_ar_bits_size, - output io_axi_r_valid, - output [2:0] io_axi_r_bits_id, - output [63:0] io_axi_r_bits_data, - output [1:0] io_axi_r_bits_resp, - input [63:0] io_ahb_in_hrdata, - input io_ahb_in_hready, - input io_ahb_in_hresp, - output [31:0] io_ahb_out_haddr, - output [2:0] io_ahb_out_hsize, - output [1:0] io_ahb_out_htrans, - output io_ahb_out_hwrite, - output [63:0] io_ahb_out_hwdata -); -`ifdef RANDOMIZE_REG_INIT - reg [31:0] _RAND_0; - reg [31:0] _RAND_1; - reg [31:0] _RAND_2; - reg [31:0] _RAND_3; - reg [31:0] _RAND_4; - reg [31:0] _RAND_5; - reg [31:0] _RAND_6; - reg [31:0] _RAND_7; - reg [31:0] _RAND_8; - reg [31:0] _RAND_9; - reg [31:0] _RAND_10; - reg [31:0] _RAND_11; - reg [63:0] _RAND_12; - reg [31:0] _RAND_13; - reg [31:0] _RAND_14; - reg [31:0] _RAND_15; - reg [31:0] _RAND_16; - reg [63:0] _RAND_17; - reg [63:0] _RAND_18; - reg [31:0] _RAND_19; - reg [31:0] _RAND_20; - reg [31:0] _RAND_21; - reg [31:0] _RAND_22; - reg [31:0] _RAND_23; - reg [31:0] _RAND_24; - reg [31:0] _RAND_25; -`endif // RANDOMIZE_REG_INIT - wire rvclkhdr_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_io_en; // @[lib.scala 343:22] - wire rvclkhdr_io_scan_mode; // @[lib.scala 343:22] - wire rvclkhdr_1_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_1_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_1_io_en; // @[lib.scala 343:22] - wire rvclkhdr_1_io_scan_mode; // @[lib.scala 343:22] - wire rvclkhdr_2_io_l1clk; // @[lib.scala 368:23] - wire rvclkhdr_2_io_clk; // @[lib.scala 368:23] - wire rvclkhdr_2_io_en; // @[lib.scala 368:23] - wire rvclkhdr_2_io_scan_mode; // @[lib.scala 368:23] - wire rvclkhdr_3_io_l1clk; // @[lib.scala 368:23] - wire rvclkhdr_3_io_clk; // @[lib.scala 368:23] - wire rvclkhdr_3_io_en; // @[lib.scala 368:23] - wire rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23] - wire rvclkhdr_4_io_l1clk; // @[lib.scala 368:23] - wire rvclkhdr_4_io_clk; // @[lib.scala 368:23] - wire rvclkhdr_4_io_en; // @[lib.scala 368:23] - wire rvclkhdr_4_io_scan_mode; // @[lib.scala 368:23] - wire rvclkhdr_5_io_l1clk; // @[lib.scala 368:23] - wire rvclkhdr_5_io_clk; // @[lib.scala 368:23] - wire rvclkhdr_5_io_en; // @[lib.scala 368:23] - wire rvclkhdr_5_io_scan_mode; // @[lib.scala 368:23] - wire rvclkhdr_6_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_6_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_6_io_en; // @[lib.scala 343:22] - wire rvclkhdr_6_io_scan_mode; // @[lib.scala 343:22] - wire rvclkhdr_7_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_7_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_7_io_en; // @[lib.scala 343:22] - wire rvclkhdr_7_io_scan_mode; // @[lib.scala 343:22] - wire rvclkhdr_8_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_8_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_8_io_en; // @[lib.scala 343:22] - wire rvclkhdr_8_io_scan_mode; // @[lib.scala 343:22] - wire rvclkhdr_9_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_9_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_9_io_en; // @[lib.scala 343:22] - wire rvclkhdr_9_io_scan_mode; // @[lib.scala 343:22] - wire ahbm_clk = rvclkhdr_7_io_l1clk; // @[axi4_to_ahb.scala 24:22 axi4_to_ahb.scala 333:12] - reg [2:0] buf_state; // @[axi4_to_ahb.scala 30:45] - wire _T_49 = 3'h0 == buf_state; // @[Conditional.scala 37:30] - wire bus_clk = rvclkhdr_io_l1clk; // @[axi4_to_ahb.scala 50:21 axi4_to_ahb.scala 162:11] - reg wrbuf_vld; // @[axi4_to_ahb.scala 301:51] - reg wrbuf_data_vld; // @[axi4_to_ahb.scala 302:51] - wire wr_cmd_vld = wrbuf_vld & wrbuf_data_vld; // @[axi4_to_ahb.scala 139:27] - wire master_valid = wr_cmd_vld | io_axi_ar_valid; // @[axi4_to_ahb.scala 140:30] - wire _T_101 = 3'h1 == buf_state; // @[Conditional.scala 37:30] - reg ahb_hready_q; // @[axi4_to_ahb.scala 321:52] - reg [1:0] ahb_htrans_q; // @[axi4_to_ahb.scala 322:52] - wire _T_108 = ahb_htrans_q != 2'h0; // @[axi4_to_ahb.scala 183:58] - wire _T_109 = ahb_hready_q & _T_108; // @[axi4_to_ahb.scala 183:36] - wire ahbm_addr_clk = rvclkhdr_8_io_l1clk; // @[axi4_to_ahb.scala 25:27 axi4_to_ahb.scala 334:17] - reg ahb_hwrite_q; // @[axi4_to_ahb.scala 323:57] - wire _T_110 = ~ahb_hwrite_q; // @[axi4_to_ahb.scala 183:72] - wire _T_111 = _T_109 & _T_110; // @[axi4_to_ahb.scala 183:70] - wire _T_136 = 3'h6 == buf_state; // @[Conditional.scala 37:30] - reg ahb_hresp_q; // @[axi4_to_ahb.scala 324:52] - wire _T_156 = ahb_hready_q | ahb_hresp_q; // @[axi4_to_ahb.scala 197:37] - wire _T_175 = 3'h7 == buf_state; // @[Conditional.scala 37:30] - wire _T_186 = 3'h3 == buf_state; // @[Conditional.scala 37:30] - wire _T_188 = 3'h2 == buf_state; // @[Conditional.scala 37:30] - wire _T_189 = ahb_hready_q & ahb_hwrite_q; // @[axi4_to_ahb.scala 229:33] - wire _T_192 = _T_189 & _T_108; // @[axi4_to_ahb.scala 229:48] - wire _T_281 = 3'h4 == buf_state; // @[Conditional.scala 37:30] - wire _GEN_15 = _T_281 & _T_192; // @[Conditional.scala 39:67] - wire _GEN_19 = _T_188 ? _T_192 : _GEN_15; // @[Conditional.scala 39:67] - wire _GEN_40 = _T_186 ? 1'h0 : _GEN_19; // @[Conditional.scala 39:67] - wire _GEN_59 = _T_175 ? 1'h0 : _GEN_40; // @[Conditional.scala 39:67] - wire _GEN_79 = _T_136 ? 1'h0 : _GEN_59; // @[Conditional.scala 39:67] - wire _GEN_95 = _T_101 ? 1'h0 : _GEN_79; // @[Conditional.scala 39:67] - wire trxn_done = _T_49 ? 1'h0 : _GEN_95; // @[Conditional.scala 40:58] - reg cmd_doneQ; // @[axi4_to_ahb.scala 319:52] - wire _T_282 = cmd_doneQ & ahb_hready_q; // @[axi4_to_ahb.scala 239:34] - wire _T_283 = _T_282 | ahb_hresp_q; // @[axi4_to_ahb.scala 239:50] - wire _T_440 = 3'h5 == buf_state; // @[Conditional.scala 37:30] - wire _GEN_3 = _T_281 ? _T_283 : _T_440; // @[Conditional.scala 39:67] - wire _GEN_20 = _T_188 ? trxn_done : _GEN_3; // @[Conditional.scala 39:67] - wire _GEN_35 = _T_186 ? _T_156 : _GEN_20; // @[Conditional.scala 39:67] - wire _GEN_51 = _T_175 ? _T_111 : _GEN_35; // @[Conditional.scala 39:67] - wire _GEN_69 = _T_136 ? _T_156 : _GEN_51; // @[Conditional.scala 39:67] - wire _GEN_83 = _T_101 ? _T_111 : _GEN_69; // @[Conditional.scala 39:67] - wire buf_state_en = _T_49 ? master_valid : _GEN_83; // @[Conditional.scala 40:58] - wire [1:0] _T_14 = wr_cmd_vld ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 142:20] - wire [2:0] master_opc = {{1'd0}, _T_14}; // @[axi4_to_ahb.scala 142:14] - wire _T_51 = master_opc[2:1] == 2'h1; // @[axi4_to_ahb.scala 168:41] - wire _GEN_8 = _T_281 & _T_51; // @[Conditional.scala 39:67] - wire _GEN_29 = _T_188 ? 1'h0 : _GEN_8; // @[Conditional.scala 39:67] - wire _GEN_46 = _T_186 ? 1'h0 : _GEN_29; // @[Conditional.scala 39:67] - wire _GEN_63 = _T_175 ? 1'h0 : _GEN_46; // @[Conditional.scala 39:67] - wire _GEN_81 = _T_136 ? 1'h0 : _GEN_63; // @[Conditional.scala 39:67] - wire _GEN_97 = _T_101 ? 1'h0 : _GEN_81; // @[Conditional.scala 39:67] - wire buf_write_in = _T_49 ? _T_51 : _GEN_97; // @[Conditional.scala 40:58] - wire [2:0] _T_53 = buf_write_in ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 169:26] - wire _T_103 = master_opc == 3'h0; // @[axi4_to_ahb.scala 182:61] - wire _T_104 = master_valid & _T_103; // @[axi4_to_ahb.scala 182:41] - wire [2:0] _T_106 = _T_104 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 182:26] - wire _T_124 = _T_106 == 3'h6; // @[axi4_to_ahb.scala 186:174] - wire _T_125 = _T_111 & _T_124; // @[axi4_to_ahb.scala 186:88] - wire _T_137 = ~ahb_hresp_q; // @[axi4_to_ahb.scala 194:39] - wire _T_138 = ahb_hready_q & _T_137; // @[axi4_to_ahb.scala 194:37] - wire _T_141 = master_valid & _T_51; // @[axi4_to_ahb.scala 194:70] - wire _T_142 = ~_T_141; // @[axi4_to_ahb.scala 194:55] - wire _T_143 = _T_138 & _T_142; // @[axi4_to_ahb.scala 194:53] - wire _T_285 = buf_state_en & _T_137; // @[axi4_to_ahb.scala 240:36] - wire _GEN_4 = _T_281 & _T_285; // @[Conditional.scala 39:67] - wire _GEN_26 = _T_188 ? 1'h0 : _GEN_4; // @[Conditional.scala 39:67] - wire _GEN_45 = _T_186 ? 1'h0 : _GEN_26; // @[Conditional.scala 39:67] - wire _GEN_62 = _T_175 ? 1'h0 : _GEN_45; // @[Conditional.scala 39:67] - wire _GEN_66 = _T_136 ? _T_143 : _GEN_62; // @[Conditional.scala 39:67] - wire _GEN_86 = _T_101 ? _T_125 : _GEN_66; // @[Conditional.scala 39:67] - wire master_ready = _T_49 | _GEN_86; // @[Conditional.scala 40:58] - wire _T_149 = master_valid & master_ready; // @[axi4_to_ahb.scala 196:82] - wire _T_152 = _T_149 & _T_103; // @[axi4_to_ahb.scala 196:97] - wire [2:0] _T_154 = _T_152 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 196:67] - wire [2:0] _T_155 = ahb_hresp_q ? 3'h7 : _T_154; // @[axi4_to_ahb.scala 196:26] - wire [2:0] _T_293 = _T_51 ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 241:99] - wire [2:0] _T_294 = master_valid ? _T_293 : 3'h0; // @[axi4_to_ahb.scala 241:65] - wire [2:0] _T_295 = ahb_hresp_q ? 3'h5 : _T_294; // @[axi4_to_ahb.scala 241:26] - wire [2:0] _GEN_5 = _T_281 ? _T_295 : 3'h0; // @[Conditional.scala 39:67] - wire [2:0] _GEN_18 = _T_188 ? 3'h4 : _GEN_5; // @[Conditional.scala 39:67] - wire [2:0] _GEN_34 = _T_186 ? 3'h5 : _GEN_18; // @[Conditional.scala 39:67] - wire [2:0] _GEN_50 = _T_175 ? 3'h3 : _GEN_34; // @[Conditional.scala 39:67] - wire [2:0] _GEN_68 = _T_136 ? _T_155 : _GEN_50; // @[Conditional.scala 39:67] - wire [2:0] _GEN_82 = _T_101 ? _T_106 : _GEN_68; // @[Conditional.scala 39:67] - wire [2:0] buf_nxtstate = _T_49 ? _T_53 : _GEN_82; // @[Conditional.scala 40:58] - reg [2:0] wrbuf_tag; // @[Reg.scala 27:20] - reg [31:0] wrbuf_addr; // @[lib.scala 374:16] - wire [31:0] master_addr = wr_cmd_vld ? wrbuf_addr : io_axi_ar_bits_addr; // @[axi4_to_ahb.scala 143:21] - reg [2:0] wrbuf_size; // @[Reg.scala 27:20] - wire [2:0] master_size = wr_cmd_vld ? wrbuf_size : io_axi_ar_bits_size; // @[axi4_to_ahb.scala 144:21] - reg [7:0] wrbuf_byteen; // @[Reg.scala 27:20] - reg [63:0] wrbuf_data; // @[lib.scala 374:16] - wire _T_358 = buf_nxtstate != 3'h5; // @[axi4_to_ahb.scala 251:55] - wire _T_359 = buf_state_en & _T_358; // @[axi4_to_ahb.scala 251:39] - wire _GEN_14 = _T_281 ? _T_359 : _T_440; // @[Conditional.scala 39:67] - wire _GEN_33 = _T_188 ? 1'h0 : _GEN_14; // @[Conditional.scala 39:67] - wire _GEN_49 = _T_186 ? 1'h0 : _GEN_33; // @[Conditional.scala 39:67] - wire _GEN_52 = _T_175 ? buf_state_en : _GEN_49; // @[Conditional.scala 39:67] - wire _GEN_73 = _T_136 ? _T_285 : _GEN_52; // @[Conditional.scala 39:67] - wire _GEN_94 = _T_101 ? 1'h0 : _GEN_73; // @[Conditional.scala 39:67] - wire slave_valid_pre = _T_49 ? 1'h0 : _GEN_94; // @[Conditional.scala 40:58] - wire buf_clk = rvclkhdr_6_io_l1clk; // @[axi4_to_ahb.scala 118:21 axi4_to_ahb.scala 332:12] - reg slvbuf_write; // @[Reg.scala 27:20] - wire [1:0] _T_596 = slvbuf_write ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 285:23] - reg slvbuf_error; // @[Reg.scala 27:20] - wire [1:0] _T_598 = slvbuf_error ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_599 = _T_598 & 2'h2; // @[axi4_to_ahb.scala 285:88] - wire [3:0] slave_opc = {_T_596,_T_599}; // @[Cat.scala 29:58] - wire [1:0] _T_30 = slave_opc[1] ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 150:55] - reg [2:0] slvbuf_tag; // @[Reg.scala 27:20] - wire _T_35 = slave_opc[3:2] == 2'h0; // @[axi4_to_ahb.scala 153:66] - reg [31:0] last_bus_addr; // @[Reg.scala 27:20] - wire [63:0] _T_603 = {last_bus_addr,last_bus_addr}; // @[Cat.scala 29:58] - wire _T_604 = buf_state == 3'h5; // @[axi4_to_ahb.scala 286:91] - reg [63:0] buf_data; // @[lib.scala 374:16] - wire ahbm_data_clk = rvclkhdr_9_io_l1clk; // @[axi4_to_ahb.scala 26:27 axi4_to_ahb.scala 335:17] - reg [63:0] ahb_hrdata_q; // @[axi4_to_ahb.scala 325:57] - wire [63:0] _T_607 = _T_604 ? buf_data : ahb_hrdata_q; // @[axi4_to_ahb.scala 286:79] - wire _T_44 = io_axi_aw_valid & io_axi_aw_ready; // @[axi4_to_ahb.scala 160:57] - wire _T_45 = io_axi_w_valid & io_axi_w_ready; // @[axi4_to_ahb.scala 160:94] - wire _T_46 = _T_44 | _T_45; // @[axi4_to_ahb.scala 160:76] - wire _T_55 = buf_nxtstate == 3'h2; // @[axi4_to_ahb.scala 172:54] - wire _T_56 = buf_state_en & _T_55; // @[axi4_to_ahb.scala 172:38] - wire [2:0] _T_87 = wrbuf_byteen[6] ? 3'h6 : 3'h7; // @[Mux.scala 98:16] - wire [2:0] _T_88 = wrbuf_byteen[5] ? 3'h5 : _T_87; // @[Mux.scala 98:16] - wire [2:0] _T_89 = wrbuf_byteen[4] ? 3'h4 : _T_88; // @[Mux.scala 98:16] - wire [2:0] _T_90 = wrbuf_byteen[3] ? 3'h3 : _T_89; // @[Mux.scala 98:16] - wire [2:0] _T_91 = wrbuf_byteen[2] ? 3'h2 : _T_90; // @[Mux.scala 98:16] - wire [2:0] _T_92 = wrbuf_byteen[1] ? 3'h1 : _T_91; // @[Mux.scala 98:16] - wire [2:0] _T_93 = wrbuf_byteen[0] ? 3'h0 : _T_92; // @[Mux.scala 98:16] - wire [2:0] _T_95 = buf_write_in ? _T_93 : master_addr[2:0]; // @[axi4_to_ahb.scala 175:30] - wire _T_96 = buf_nxtstate == 3'h1; // @[axi4_to_ahb.scala 177:51] - wire _T_126 = master_ready & master_valid; // @[axi4_to_ahb.scala 188:33] - wire _T_162 = buf_nxtstate == 3'h6; // @[axi4_to_ahb.scala 203:64] - wire _T_163 = _T_126 & _T_162; // @[axi4_to_ahb.scala 203:48] - wire _T_164 = _T_163 & buf_state_en; // @[axi4_to_ahb.scala 203:79] - wire _T_349 = buf_state_en & buf_write_in; // @[axi4_to_ahb.scala 249:33] - wire _T_351 = _T_349 & _T_55; // @[axi4_to_ahb.scala 249:48] - wire _GEN_12 = _T_281 & _T_351; // @[Conditional.scala 39:67] - wire _GEN_32 = _T_188 ? 1'h0 : _GEN_12; // @[Conditional.scala 39:67] - wire _GEN_48 = _T_186 ? 1'h0 : _GEN_32; // @[Conditional.scala 39:67] - wire _GEN_65 = _T_175 ? 1'h0 : _GEN_48; // @[Conditional.scala 39:67] - wire _GEN_75 = _T_136 ? _T_164 : _GEN_65; // @[Conditional.scala 39:67] - wire _GEN_88 = _T_101 ? _T_126 : _GEN_75; // @[Conditional.scala 39:67] - wire bypass_en = _T_49 ? buf_state_en : _GEN_88; // @[Conditional.scala 40:58] - wire [1:0] _T_99 = bypass_en ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_100 = _T_99 & 2'h2; // @[axi4_to_ahb.scala 178:49] - wire _T_112 = ~master_valid; // @[axi4_to_ahb.scala 184:34] - wire _T_113 = buf_state_en & _T_112; // @[axi4_to_ahb.scala 184:32] - reg [31:0] buf_addr; // @[lib.scala 374:16] - wire [2:0] _T_130 = bypass_en ? master_addr[2:0] : buf_addr[2:0]; // @[axi4_to_ahb.scala 189:30] - wire _T_131 = ~buf_state_en; // @[axi4_to_ahb.scala 190:48] - wire _T_132 = _T_131 | bypass_en; // @[axi4_to_ahb.scala 190:62] - wire [1:0] _T_134 = _T_132 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_135 = 2'h2 & _T_134; // @[axi4_to_ahb.scala 190:36] - wire _T_169 = buf_nxtstate != 3'h6; // @[axi4_to_ahb.scala 205:63] - wire _T_170 = _T_169 & buf_state_en; // @[axi4_to_ahb.scala 205:78] - wire _T_171 = ~_T_170; // @[axi4_to_ahb.scala 205:47] - wire [1:0] _T_173 = _T_171 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_174 = 2'h2 & _T_173; // @[axi4_to_ahb.scala 205:36] - wire [1:0] _T_184 = _T_131 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_185 = 2'h2 & _T_184; // @[axi4_to_ahb.scala 215:41] - reg [2:0] buf_cmd_byte_ptrQ; // @[Reg.scala 27:20] - reg [7:0] buf_byteen; // @[Reg.scala 27:20] - wire [2:0] _T_197 = buf_cmd_byte_ptrQ + 3'h1; // @[axi4_to_ahb.scala 135:52] - wire _T_200 = 3'h0 >= _T_197; // @[axi4_to_ahb.scala 136:62] - wire _T_201 = buf_byteen[0] & _T_200; // @[axi4_to_ahb.scala 136:48] - wire _T_203 = 3'h1 >= _T_197; // @[axi4_to_ahb.scala 136:62] - wire _T_204 = buf_byteen[1] & _T_203; // @[axi4_to_ahb.scala 136:48] - wire _T_206 = 3'h2 >= _T_197; // @[axi4_to_ahb.scala 136:62] - wire _T_207 = buf_byteen[2] & _T_206; // @[axi4_to_ahb.scala 136:48] - wire _T_209 = 3'h3 >= _T_197; // @[axi4_to_ahb.scala 136:62] - wire _T_210 = buf_byteen[3] & _T_209; // @[axi4_to_ahb.scala 136:48] - wire _T_212 = 3'h4 >= _T_197; // @[axi4_to_ahb.scala 136:62] - wire _T_213 = buf_byteen[4] & _T_212; // @[axi4_to_ahb.scala 136:48] - wire _T_215 = 3'h5 >= _T_197; // @[axi4_to_ahb.scala 136:62] - wire _T_216 = buf_byteen[5] & _T_215; // @[axi4_to_ahb.scala 136:48] - wire _T_218 = 3'h6 >= _T_197; // @[axi4_to_ahb.scala 136:62] - wire _T_219 = buf_byteen[6] & _T_218; // @[axi4_to_ahb.scala 136:48] - wire [2:0] _T_224 = _T_219 ? 3'h6 : 3'h7; // @[Mux.scala 98:16] - wire [2:0] _T_225 = _T_216 ? 3'h5 : _T_224; // @[Mux.scala 98:16] - wire [2:0] _T_226 = _T_213 ? 3'h4 : _T_225; // @[Mux.scala 98:16] - wire [2:0] _T_227 = _T_210 ? 3'h3 : _T_226; // @[Mux.scala 98:16] - wire [2:0] _T_228 = _T_207 ? 3'h2 : _T_227; // @[Mux.scala 98:16] - wire [2:0] _T_229 = _T_204 ? 3'h1 : _T_228; // @[Mux.scala 98:16] - wire [2:0] _T_230 = _T_201 ? 3'h0 : _T_229; // @[Mux.scala 98:16] - wire [2:0] _T_231 = trxn_done ? _T_230 : buf_cmd_byte_ptrQ; // @[axi4_to_ahb.scala 233:30] - wire _T_232 = buf_cmd_byte_ptrQ == 3'h7; // @[axi4_to_ahb.scala 234:65] - reg buf_aligned; // @[Reg.scala 27:20] - wire _T_233 = buf_aligned | _T_232; // @[axi4_to_ahb.scala 234:44] - wire [7:0] _T_271 = buf_byteen >> _T_230; // @[axi4_to_ahb.scala 234:92] - wire _T_273 = ~_T_271[0]; // @[axi4_to_ahb.scala 234:163] - wire _T_274 = _T_233 | _T_273; // @[axi4_to_ahb.scala 234:79] - wire _T_275 = trxn_done & _T_274; // @[axi4_to_ahb.scala 234:29] - wire _T_346 = _T_232 | _T_273; // @[axi4_to_ahb.scala 248:38] - wire _T_347 = _T_109 & _T_346; // @[axi4_to_ahb.scala 247:80] - wire _T_348 = ahb_hresp_q | _T_347; // @[axi4_to_ahb.scala 247:34] - wire _GEN_11 = _T_281 & _T_348; // @[Conditional.scala 39:67] - wire _GEN_24 = _T_188 ? _T_275 : _GEN_11; // @[Conditional.scala 39:67] - wire _GEN_43 = _T_186 ? 1'h0 : _GEN_24; // @[Conditional.scala 39:67] - wire _GEN_61 = _T_175 ? 1'h0 : _GEN_43; // @[Conditional.scala 39:67] - wire _GEN_74 = _T_136 ? _T_113 : _GEN_61; // @[Conditional.scala 39:67] - wire _GEN_84 = _T_101 ? _T_113 : _GEN_74; // @[Conditional.scala 39:67] - wire cmd_done = _T_49 ? 1'h0 : _GEN_84; // @[Conditional.scala 40:58] - wire _T_276 = cmd_done | cmd_doneQ; // @[axi4_to_ahb.scala 235:47] - wire _T_277 = ~_T_276; // @[axi4_to_ahb.scala 235:36] - wire [1:0] _T_279 = _T_277 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_280 = _T_279 & 2'h2; // @[axi4_to_ahb.scala 235:61] - wire _T_300 = _T_55 | _T_96; // @[axi4_to_ahb.scala 245:62] - wire _T_301 = buf_state_en & _T_300; // @[axi4_to_ahb.scala 245:33] - wire _T_354 = _T_277 | bypass_en; // @[axi4_to_ahb.scala 250:61] - wire [1:0] _T_356 = _T_354 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_357 = _T_356 & 2'h2; // @[axi4_to_ahb.scala 250:75] - wire _T_364 = trxn_done | bypass_en; // @[axi4_to_ahb.scala 253:40] - wire [2:0] _T_439 = bypass_en ? _T_93 : _T_231; // @[axi4_to_ahb.scala 254:30] - wire _GEN_6 = _T_281 & ahb_hresp_q; // @[Conditional.scala 39:67] - wire _GEN_7 = _T_281 ? buf_state_en : _T_440; // @[Conditional.scala 39:67] - wire _GEN_9 = _T_281 & _T_301; // @[Conditional.scala 39:67] - wire _GEN_30 = _T_188 ? 1'h0 : _GEN_9; // @[Conditional.scala 39:67] - wire _GEN_47 = _T_186 ? 1'h0 : _GEN_30; // @[Conditional.scala 39:67] - wire _GEN_64 = _T_175 ? 1'h0 : _GEN_47; // @[Conditional.scala 39:67] - wire _GEN_67 = _T_136 ? _T_152 : _GEN_64; // @[Conditional.scala 39:67] - wire _GEN_87 = _T_101 ? master_ready : _GEN_67; // @[Conditional.scala 39:67] - wire buf_wr_en = _T_49 ? buf_state_en : _GEN_87; // @[Conditional.scala 40:58] - wire _GEN_10 = _T_281 & buf_wr_en; // @[Conditional.scala 39:67] - wire [1:0] _GEN_13 = _T_281 ? _T_357 : 2'h0; // @[Conditional.scala 39:67] - wire _GEN_16 = _T_281 & _T_364; // @[Conditional.scala 39:67] - wire [2:0] _GEN_17 = _T_281 ? _T_439 : 3'h0; // @[Conditional.scala 39:67] - wire _GEN_21 = _T_188 ? buf_state_en : _GEN_16; // @[Conditional.scala 39:67] - wire _GEN_22 = _T_188 & buf_state_en; // @[Conditional.scala 39:67] - wire [2:0] _GEN_23 = _T_188 ? _T_231 : _GEN_17; // @[Conditional.scala 39:67] - wire [1:0] _GEN_25 = _T_188 ? _T_280 : _GEN_13; // @[Conditional.scala 39:67] - wire _GEN_28 = _T_188 ? 1'h0 : _GEN_7; // @[Conditional.scala 39:67] - wire _GEN_31 = _T_188 ? 1'h0 : _GEN_10; // @[Conditional.scala 39:67] - wire _GEN_36 = _T_186 ? buf_state_en : _GEN_31; // @[Conditional.scala 39:67] - wire _GEN_38 = _T_186 ? buf_state_en : _GEN_28; // @[Conditional.scala 39:67] - wire _GEN_39 = _T_186 ? buf_state_en : _GEN_22; // @[Conditional.scala 39:67] - wire _GEN_41 = _T_186 ? 1'h0 : _GEN_21; // @[Conditional.scala 39:67] - wire [2:0] _GEN_42 = _T_186 ? 3'h0 : _GEN_23; // @[Conditional.scala 39:67] - wire [1:0] _GEN_44 = _T_186 ? 2'h0 : _GEN_25; // @[Conditional.scala 39:67] - wire _GEN_53 = _T_175 ? buf_state_en : _GEN_39; // @[Conditional.scala 39:67] - wire [2:0] _GEN_54 = _T_175 ? buf_addr[2:0] : _GEN_42; // @[Conditional.scala 39:67] - wire [1:0] _GEN_55 = _T_175 ? _T_185 : _GEN_44; // @[Conditional.scala 39:67] - wire _GEN_56 = _T_175 ? 1'h0 : _GEN_36; // @[Conditional.scala 39:67] - wire _GEN_58 = _T_175 ? 1'h0 : _GEN_38; // @[Conditional.scala 39:67] - wire _GEN_60 = _T_175 ? 1'h0 : _GEN_41; // @[Conditional.scala 39:67] - wire _GEN_70 = _T_136 ? buf_state_en : _GEN_56; // @[Conditional.scala 39:67] - wire _GEN_72 = _T_136 ? buf_state_en : _GEN_58; // @[Conditional.scala 39:67] - wire [2:0] _GEN_76 = _T_136 ? _T_130 : _GEN_54; // @[Conditional.scala 39:67] - wire [1:0] _GEN_77 = _T_136 ? _T_174 : _GEN_55; // @[Conditional.scala 39:67] - wire _GEN_78 = _T_136 ? buf_wr_en : _GEN_53; // @[Conditional.scala 39:67] - wire _GEN_80 = _T_136 ? 1'h0 : _GEN_60; // @[Conditional.scala 39:67] - wire _GEN_85 = _T_101 ? buf_state_en : _GEN_78; // @[Conditional.scala 39:67] - wire [2:0] _GEN_89 = _T_101 ? _T_130 : _GEN_76; // @[Conditional.scala 39:67] - wire [1:0] _GEN_90 = _T_101 ? _T_135 : _GEN_77; // @[Conditional.scala 39:67] - wire _GEN_91 = _T_101 ? 1'h0 : _GEN_70; // @[Conditional.scala 39:67] - wire _GEN_93 = _T_101 ? 1'h0 : _GEN_72; // @[Conditional.scala 39:67] - wire _GEN_96 = _T_101 ? 1'h0 : _GEN_80; // @[Conditional.scala 39:67] - wire buf_data_wr_en = _T_49 ? _T_56 : _GEN_91; // @[Conditional.scala 40:58] - wire buf_cmd_byte_ptr_en = _T_49 ? buf_state_en : _GEN_96; // @[Conditional.scala 40:58] - wire [2:0] buf_cmd_byte_ptr = _T_49 ? _T_95 : _GEN_89; // @[Conditional.scala 40:58] - wire slvbuf_wr_en = _T_49 ? 1'h0 : _GEN_85; // @[Conditional.scala 40:58] - wire slvbuf_error_en = _T_49 ? 1'h0 : _GEN_93; // @[Conditional.scala 40:58] - wire _T_535 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 271:24] - wire _T_536 = _T_103 | _T_535; // @[axi4_to_ahb.scala 270:48] - wire _T_538 = master_size[1:0] == 2'h1; // @[axi4_to_ahb.scala 271:54] - wire _T_539 = _T_536 | _T_538; // @[axi4_to_ahb.scala 271:33] - wire _T_541 = master_size[1:0] == 2'h2; // @[axi4_to_ahb.scala 271:93] - wire _T_542 = _T_539 | _T_541; // @[axi4_to_ahb.scala 271:72] - wire _T_544 = master_size[1:0] == 2'h3; // @[axi4_to_ahb.scala 272:25] - wire _T_546 = wrbuf_byteen == 8'h3; // @[axi4_to_ahb.scala 272:62] - wire _T_548 = wrbuf_byteen == 8'hc; // @[axi4_to_ahb.scala 272:97] - wire _T_549 = _T_546 | _T_548; // @[axi4_to_ahb.scala 272:74] - wire _T_551 = wrbuf_byteen == 8'h30; // @[axi4_to_ahb.scala 272:132] - wire _T_552 = _T_549 | _T_551; // @[axi4_to_ahb.scala 272:109] - wire _T_554 = wrbuf_byteen == 8'hc0; // @[axi4_to_ahb.scala 272:168] - wire _T_555 = _T_552 | _T_554; // @[axi4_to_ahb.scala 272:145] - wire _T_557 = wrbuf_byteen == 8'hf; // @[axi4_to_ahb.scala 273:28] - wire _T_558 = _T_555 | _T_557; // @[axi4_to_ahb.scala 272:181] - wire _T_560 = wrbuf_byteen == 8'hf0; // @[axi4_to_ahb.scala 273:63] - wire _T_561 = _T_558 | _T_560; // @[axi4_to_ahb.scala 273:40] - wire _T_563 = wrbuf_byteen == 8'hff; // @[axi4_to_ahb.scala 273:99] - wire _T_564 = _T_561 | _T_563; // @[axi4_to_ahb.scala 273:76] - wire _T_565 = _T_544 & _T_564; // @[axi4_to_ahb.scala 272:38] - wire buf_aligned_in = _T_542 | _T_565; // @[axi4_to_ahb.scala 271:106] - wire _T_444 = buf_aligned_in & _T_51; // @[axi4_to_ahb.scala 265:60] - wire [2:0] _T_461 = _T_548 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_462 = 3'h2 & _T_461; // @[axi4_to_ahb.scala 128:15] - wire _T_468 = _T_560 | _T_546; // @[axi4_to_ahb.scala 129:56] - wire [2:0] _T_470 = _T_468 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_471 = 3'h4 & _T_470; // @[axi4_to_ahb.scala 129:15] - wire [2:0] _T_472 = _T_462 | _T_471; // @[axi4_to_ahb.scala 128:63] - wire [2:0] _T_476 = _T_554 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_477 = 3'h6 & _T_476; // @[axi4_to_ahb.scala 130:15] - wire [2:0] _T_478 = _T_472 | _T_477; // @[axi4_to_ahb.scala 129:96] - wire [2:0] _T_485 = _T_444 ? _T_478 : master_addr[2:0]; // @[axi4_to_ahb.scala 265:43] - wire _T_489 = buf_state == 3'h3; // @[axi4_to_ahb.scala 268:33] - wire _T_495 = buf_aligned_in & _T_544; // @[axi4_to_ahb.scala 269:38] - wire _T_498 = _T_495 & _T_51; // @[axi4_to_ahb.scala 269:71] - wire [1:0] _T_504 = _T_563 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire _T_510 = _T_560 | _T_557; // @[axi4_to_ahb.scala 122:55] - wire [1:0] _T_512 = _T_510 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_513 = 2'h2 & _T_512; // @[axi4_to_ahb.scala 122:16] - wire [1:0] _T_514 = _T_504 | _T_513; // @[axi4_to_ahb.scala 121:64] - wire _T_519 = _T_554 | _T_551; // @[axi4_to_ahb.scala 123:60] - wire _T_522 = _T_519 | _T_548; // @[axi4_to_ahb.scala 123:89] - wire _T_525 = _T_522 | _T_546; // @[axi4_to_ahb.scala 123:123] - wire [1:0] _T_527 = _T_525 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_528 = 2'h1 & _T_527; // @[axi4_to_ahb.scala 123:21] - wire [1:0] _T_529 = _T_514 | _T_528; // @[axi4_to_ahb.scala 122:93] - wire [1:0] _T_531 = _T_498 ? _T_529 : master_size[1:0]; // @[axi4_to_ahb.scala 269:21] - wire [31:0] _T_570 = {master_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] - wire [31:0] _T_573 = {buf_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] - wire [1:0] _T_577 = buf_aligned_in ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [2:0] buf_size_in = {{1'd0}, _T_531}; // @[axi4_to_ahb.scala 269:15] - wire [1:0] _T_579 = _T_577 & buf_size_in[1:0]; // @[axi4_to_ahb.scala 276:81] - wire [2:0] _T_580 = {1'h0,_T_579}; // @[Cat.scala 29:58] - wire [1:0] _T_582 = buf_aligned ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - reg [1:0] buf_size; // @[Reg.scala 27:20] - wire [1:0] _T_584 = _T_582 & buf_size; // @[axi4_to_ahb.scala 276:138] - wire [2:0] _T_585 = {1'h0,_T_584}; // @[Cat.scala 29:58] - reg buf_write; // @[Reg.scala 27:20] - wire _T_611 = io_ahb_out_htrans != 2'h0; // @[axi4_to_ahb.scala 289:44] - wire _T_612 = _T_611 & io_ahb_in_hready; // @[axi4_to_ahb.scala 289:56] - wire last_addr_en = _T_612 & io_ahb_out_hwrite; // @[axi4_to_ahb.scala 289:75] - wire wrbuf_en = _T_44 & master_ready; // @[axi4_to_ahb.scala 291:49] - wire wrbuf_data_en = _T_45 & master_ready; // @[axi4_to_ahb.scala 292:52] - wire wrbuf_cmd_sent = _T_149 & _T_51; // @[axi4_to_ahb.scala 293:49] - wire _T_622 = ~wrbuf_en; // @[axi4_to_ahb.scala 294:33] - wire wrbuf_rst = wrbuf_cmd_sent & _T_622; // @[axi4_to_ahb.scala 294:31] - wire _T_624 = ~wrbuf_cmd_sent; // @[axi4_to_ahb.scala 296:36] - wire _T_625 = wrbuf_vld & _T_624; // @[axi4_to_ahb.scala 296:34] - wire _T_626 = ~_T_625; // @[axi4_to_ahb.scala 296:22] - wire _T_629 = wrbuf_data_vld & _T_624; // @[axi4_to_ahb.scala 297:38] - wire _T_630 = ~_T_629; // @[axi4_to_ahb.scala 297:21] - wire _T_633 = ~wr_cmd_vld; // @[axi4_to_ahb.scala 298:22] - wire _T_636 = wrbuf_en | wrbuf_vld; // @[axi4_to_ahb.scala 301:55] - wire _T_637 = ~wrbuf_rst; // @[axi4_to_ahb.scala 301:91] - wire _T_641 = wrbuf_data_en | wrbuf_data_vld; // @[axi4_to_ahb.scala 302:55] - reg [2:0] buf_tag; // @[Reg.scala 27:20] - wire _T_691 = ~slave_valid_pre; // @[axi4_to_ahb.scala 319:92] - wire _T_704 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 327:43] - wire _T_705 = _T_704 | io_clk_override; // @[axi4_to_ahb.scala 327:58] - wire _T_708 = io_ahb_in_hready & io_ahb_out_htrans[1]; // @[axi4_to_ahb.scala 328:57] - wire _T_709 = _T_708 | io_clk_override; // @[axi4_to_ahb.scala 328:81] - wire _T_711 = buf_state != 3'h0; // @[axi4_to_ahb.scala 329:50] - wire _T_712 = _T_711 | io_clk_override; // @[axi4_to_ahb.scala 329:60] - rvclkhdr rvclkhdr ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_io_l1clk), - .io_clk(rvclkhdr_io_clk), - .io_en(rvclkhdr_io_en), - .io_scan_mode(rvclkhdr_io_scan_mode) - ); - rvclkhdr rvclkhdr_1 ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_1_io_l1clk), - .io_clk(rvclkhdr_1_io_clk), - .io_en(rvclkhdr_1_io_en), - .io_scan_mode(rvclkhdr_1_io_scan_mode) - ); - rvclkhdr rvclkhdr_2 ( // @[lib.scala 368:23] - .io_l1clk(rvclkhdr_2_io_l1clk), - .io_clk(rvclkhdr_2_io_clk), - .io_en(rvclkhdr_2_io_en), - .io_scan_mode(rvclkhdr_2_io_scan_mode) - ); - rvclkhdr rvclkhdr_3 ( // @[lib.scala 368:23] - .io_l1clk(rvclkhdr_3_io_l1clk), - .io_clk(rvclkhdr_3_io_clk), - .io_en(rvclkhdr_3_io_en), - .io_scan_mode(rvclkhdr_3_io_scan_mode) - ); - rvclkhdr rvclkhdr_4 ( // @[lib.scala 368:23] - .io_l1clk(rvclkhdr_4_io_l1clk), - .io_clk(rvclkhdr_4_io_clk), - .io_en(rvclkhdr_4_io_en), - .io_scan_mode(rvclkhdr_4_io_scan_mode) - ); - rvclkhdr rvclkhdr_5 ( // @[lib.scala 368:23] - .io_l1clk(rvclkhdr_5_io_l1clk), - .io_clk(rvclkhdr_5_io_clk), - .io_en(rvclkhdr_5_io_en), - .io_scan_mode(rvclkhdr_5_io_scan_mode) - ); - rvclkhdr rvclkhdr_6 ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_6_io_l1clk), - .io_clk(rvclkhdr_6_io_clk), - .io_en(rvclkhdr_6_io_en), - .io_scan_mode(rvclkhdr_6_io_scan_mode) - ); - rvclkhdr rvclkhdr_7 ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_7_io_l1clk), - .io_clk(rvclkhdr_7_io_clk), - .io_en(rvclkhdr_7_io_en), - .io_scan_mode(rvclkhdr_7_io_scan_mode) - ); - rvclkhdr rvclkhdr_8 ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_8_io_l1clk), - .io_clk(rvclkhdr_8_io_clk), - .io_en(rvclkhdr_8_io_en), - .io_scan_mode(rvclkhdr_8_io_scan_mode) - ); - rvclkhdr rvclkhdr_9 ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_9_io_l1clk), - .io_clk(rvclkhdr_9_io_clk), - .io_en(rvclkhdr_9_io_en), - .io_scan_mode(rvclkhdr_9_io_scan_mode) - ); - assign io_axi_aw_ready = _T_626 & master_ready; // @[axi4_to_ahb.scala 296:19] - assign io_axi_w_ready = _T_630 & master_ready; // @[axi4_to_ahb.scala 297:18] - assign io_axi_b_valid = slave_valid_pre & slave_opc[3]; // @[axi4_to_ahb.scala 149:18] - assign io_axi_b_bits_resp = slave_opc[0] ? 2'h2 : _T_30; // @[axi4_to_ahb.scala 150:22] - assign io_axi_b_bits_id = slvbuf_tag; // @[axi4_to_ahb.scala 151:20] - assign io_axi_ar_ready = _T_633 & master_ready; // @[axi4_to_ahb.scala 298:19] - assign io_axi_r_valid = slave_valid_pre & _T_35; // @[axi4_to_ahb.scala 153:18] - assign io_axi_r_bits_id = slvbuf_tag; // @[axi4_to_ahb.scala 155:20] - assign io_axi_r_bits_data = slvbuf_error ? _T_603 : _T_607; // @[axi4_to_ahb.scala 156:22] - assign io_axi_r_bits_resp = slave_opc[0] ? 2'h2 : _T_30; // @[axi4_to_ahb.scala 154:22] - assign io_ahb_out_haddr = bypass_en ? _T_570 : _T_573; // @[axi4_to_ahb.scala 275:20] - assign io_ahb_out_hsize = bypass_en ? _T_580 : _T_585; // @[axi4_to_ahb.scala 276:20] - assign io_ahb_out_htrans = _T_49 ? _T_100 : _GEN_90; // @[axi4_to_ahb.scala 22:21 axi4_to_ahb.scala 178:25 axi4_to_ahb.scala 190:25 axi4_to_ahb.scala 205:25 axi4_to_ahb.scala 215:25 axi4_to_ahb.scala 235:25 axi4_to_ahb.scala 250:25] - assign io_ahb_out_hwrite = bypass_en ? _T_51 : buf_write; // @[axi4_to_ahb.scala 281:21] - assign io_ahb_out_hwdata = buf_data; // @[axi4_to_ahb.scala 282:21] - assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_io_en = io_bus_clk_en; // @[lib.scala 345:16] - assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign rvclkhdr_1_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_1_io_en = io_bus_clk_en & _T_46; // @[lib.scala 345:16] - assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign rvclkhdr_2_io_clk = rvclkhdr_io_l1clk; // @[lib.scala 370:18] - assign rvclkhdr_2_io_en = _T_44 & master_ready; // @[lib.scala 371:17] - assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] - assign rvclkhdr_3_io_clk = rvclkhdr_io_l1clk; // @[lib.scala 370:18] - assign rvclkhdr_3_io_en = _T_45 & master_ready; // @[lib.scala 371:17] - assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] - assign rvclkhdr_4_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_4_io_en = buf_wr_en & io_bus_clk_en; // @[lib.scala 371:17] - assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] - assign rvclkhdr_5_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_5_io_en = buf_data_wr_en & io_bus_clk_en; // @[lib.scala 371:17] - assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] - assign rvclkhdr_6_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_6_io_en = io_bus_clk_en & _T_705; // @[lib.scala 345:16] - assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign rvclkhdr_7_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_7_io_en = io_bus_clk_en; // @[lib.scala 345:16] - assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign rvclkhdr_8_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_8_io_en = io_bus_clk_en & _T_709; // @[lib.scala 345:16] - assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign rvclkhdr_9_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_9_io_en = io_bus_clk_en & _T_712; // @[lib.scala 345:16] - assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] -`ifdef RANDOMIZE_GARBAGE_ASSIGN -`define RANDOMIZE -`endif -`ifdef RANDOMIZE_INVALID_ASSIGN -`define RANDOMIZE -`endif -`ifdef RANDOMIZE_REG_INIT -`define RANDOMIZE -`endif -`ifdef RANDOMIZE_MEM_INIT -`define RANDOMIZE -`endif -`ifndef RANDOM -`define RANDOM $random -`endif -`ifdef RANDOMIZE_MEM_INIT - integer initvar; -`endif -`ifndef SYNTHESIS -`ifdef FIRRTL_BEFORE_INITIAL -`FIRRTL_BEFORE_INITIAL -`endif -initial begin - `ifdef RANDOMIZE - `ifdef INIT_RANDOM - `INIT_RANDOM - `endif - `ifndef VERILATOR - `ifdef RANDOMIZE_DELAY - #`RANDOMIZE_DELAY begin end - `else - #0.002 begin end - `endif - `endif -`ifdef RANDOMIZE_REG_INIT - _RAND_0 = {1{`RANDOM}}; - buf_state = _RAND_0[2:0]; - _RAND_1 = {1{`RANDOM}}; - wrbuf_vld = _RAND_1[0:0]; - _RAND_2 = {1{`RANDOM}}; - wrbuf_data_vld = _RAND_2[0:0]; - _RAND_3 = {1{`RANDOM}}; - ahb_hready_q = _RAND_3[0:0]; - _RAND_4 = {1{`RANDOM}}; - ahb_htrans_q = _RAND_4[1:0]; - _RAND_5 = {1{`RANDOM}}; - ahb_hwrite_q = _RAND_5[0:0]; - _RAND_6 = {1{`RANDOM}}; - ahb_hresp_q = _RAND_6[0:0]; - _RAND_7 = {1{`RANDOM}}; - cmd_doneQ = _RAND_7[0:0]; - _RAND_8 = {1{`RANDOM}}; - wrbuf_tag = _RAND_8[2:0]; - _RAND_9 = {1{`RANDOM}}; - wrbuf_addr = _RAND_9[31:0]; - _RAND_10 = {1{`RANDOM}}; - wrbuf_size = _RAND_10[2:0]; - _RAND_11 = {1{`RANDOM}}; - wrbuf_byteen = _RAND_11[7:0]; - _RAND_12 = {2{`RANDOM}}; - wrbuf_data = _RAND_12[63:0]; - _RAND_13 = {1{`RANDOM}}; - slvbuf_write = _RAND_13[0:0]; - _RAND_14 = {1{`RANDOM}}; - slvbuf_error = _RAND_14[0:0]; - _RAND_15 = {1{`RANDOM}}; - slvbuf_tag = _RAND_15[2:0]; - _RAND_16 = {1{`RANDOM}}; - last_bus_addr = _RAND_16[31:0]; - _RAND_17 = {2{`RANDOM}}; - buf_data = _RAND_17[63:0]; - _RAND_18 = {2{`RANDOM}}; - ahb_hrdata_q = _RAND_18[63:0]; - _RAND_19 = {1{`RANDOM}}; - buf_addr = _RAND_19[31:0]; - _RAND_20 = {1{`RANDOM}}; - buf_cmd_byte_ptrQ = _RAND_20[2:0]; - _RAND_21 = {1{`RANDOM}}; - buf_byteen = _RAND_21[7:0]; - _RAND_22 = {1{`RANDOM}}; - buf_aligned = _RAND_22[0:0]; - _RAND_23 = {1{`RANDOM}}; - buf_size = _RAND_23[1:0]; - _RAND_24 = {1{`RANDOM}}; - buf_write = _RAND_24[0:0]; - _RAND_25 = {1{`RANDOM}}; - buf_tag = _RAND_25[2:0]; -`endif // RANDOMIZE_REG_INIT - if (reset) begin - buf_state = 3'h0; - end - if (reset) begin - wrbuf_vld = 1'h0; - end - if (reset) begin - wrbuf_data_vld = 1'h0; - end - if (reset) begin - ahb_hready_q = 1'h0; - end - if (reset) begin - ahb_htrans_q = 2'h0; - end - if (reset) begin - ahb_hwrite_q = 1'h0; - end - if (reset) begin - ahb_hresp_q = 1'h0; - end - if (reset) begin - cmd_doneQ = 1'h0; - end - if (reset) begin - wrbuf_tag = 3'h0; - end - if (reset) begin - wrbuf_addr = 32'h0; - end - if (reset) begin - wrbuf_size = 3'h0; - end - if (reset) begin - wrbuf_byteen = 8'h0; - end - if (reset) begin - wrbuf_data = 64'h0; - end - if (reset) begin - slvbuf_write = 1'h0; - end - if (reset) begin - slvbuf_error = 1'h0; - end - if (reset) begin - slvbuf_tag = 3'h0; - end - if (reset) begin - last_bus_addr = 32'h0; - end - if (reset) begin - buf_data = 64'h0; - end - if (reset) begin - ahb_hrdata_q = 64'h0; - end - if (reset) begin - buf_addr = 32'h0; - end - if (reset) begin - buf_cmd_byte_ptrQ = 3'h0; - end - if (reset) begin - buf_byteen = 8'h0; - end - if (reset) begin - buf_aligned = 1'h0; - end - if (reset) begin - buf_size = 2'h0; - end - if (reset) begin - buf_write = 1'h0; - end - if (reset) begin - buf_tag = 3'h0; - end - `endif // RANDOMIZE -end // initial -`ifdef FIRRTL_AFTER_INITIAL -`FIRRTL_AFTER_INITIAL -`endif -`endif // SYNTHESIS - always @(posedge ahbm_clk or posedge reset) begin - if (reset) begin - buf_state <= 3'h0; - end else if (buf_state_en) begin - if (_T_49) begin - if (buf_write_in) begin - buf_state <= 3'h2; - end else begin - buf_state <= 3'h1; - end - end else if (_T_101) begin - if (_T_104) begin - buf_state <= 3'h6; - end else begin - buf_state <= 3'h3; - end - end else if (_T_136) begin - if (ahb_hresp_q) begin - buf_state <= 3'h7; - end else if (_T_152) begin - buf_state <= 3'h6; - end else begin - buf_state <= 3'h3; - end - end else if (_T_175) begin - buf_state <= 3'h3; - end else if (_T_186) begin - buf_state <= 3'h5; - end else if (_T_188) begin - buf_state <= 3'h4; - end else if (_T_281) begin - if (ahb_hresp_q) begin - buf_state <= 3'h5; - end else if (master_valid) begin - if (_T_51) begin - buf_state <= 3'h2; - end else begin - buf_state <= 3'h1; - end - end else begin - buf_state <= 3'h0; - end - end else begin - buf_state <= 3'h0; - end - end - end - always @(posedge bus_clk or posedge reset) begin - if (reset) begin - wrbuf_vld <= 1'h0; - end else begin - wrbuf_vld <= _T_636 & _T_637; - end - end - always @(posedge bus_clk or posedge reset) begin - if (reset) begin - wrbuf_data_vld <= 1'h0; - end else begin - wrbuf_data_vld <= _T_641 & _T_637; - end - end - always @(posedge ahbm_clk or posedge reset) begin - if (reset) begin - ahb_hready_q <= 1'h0; - end else begin - ahb_hready_q <= io_ahb_in_hready; - end - end - always @(posedge ahbm_clk or posedge reset) begin - if (reset) begin - ahb_htrans_q <= 2'h0; - end else begin - ahb_htrans_q <= io_ahb_out_htrans; - end - end - always @(posedge ahbm_addr_clk or posedge reset) begin - if (reset) begin - ahb_hwrite_q <= 1'h0; - end else begin - ahb_hwrite_q <= io_ahb_out_hwrite; - end - end - always @(posedge ahbm_clk or posedge reset) begin - if (reset) begin - ahb_hresp_q <= 1'h0; - end else begin - ahb_hresp_q <= io_ahb_in_hresp; - end - end - always @(posedge ahbm_clk or posedge reset) begin - if (reset) begin - cmd_doneQ <= 1'h0; - end else begin - cmd_doneQ <= _T_276 & _T_691; - end - end - always @(posedge bus_clk or posedge reset) begin - if (reset) begin - wrbuf_tag <= 3'h0; - end else if (wrbuf_en) begin - wrbuf_tag <= io_axi_aw_bits_id; - end - end - always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin - if (reset) begin - wrbuf_addr <= 32'h0; - end else begin - wrbuf_addr <= io_axi_aw_bits_addr; - end - end - always @(posedge bus_clk or posedge reset) begin - if (reset) begin - wrbuf_size <= 3'h0; - end else if (wrbuf_en) begin - wrbuf_size <= io_axi_aw_bits_size; - end - end - always @(posedge bus_clk or posedge reset) begin - if (reset) begin - wrbuf_byteen <= 8'h0; - end else if (wrbuf_data_en) begin - wrbuf_byteen <= io_axi_w_bits_strb; - end - end - always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin - if (reset) begin - wrbuf_data <= 64'h0; - end else begin - wrbuf_data <= io_axi_w_bits_data; - end - end - always @(posedge buf_clk or posedge reset) begin - if (reset) begin - slvbuf_write <= 1'h0; - end else if (slvbuf_wr_en) begin - slvbuf_write <= buf_write; - end - end - always @(posedge ahbm_clk or posedge reset) begin - if (reset) begin - slvbuf_error <= 1'h0; - end else if (slvbuf_error_en) begin - if (_T_49) begin - slvbuf_error <= 1'h0; - end else if (_T_101) begin - slvbuf_error <= 1'h0; - end else if (_T_136) begin - slvbuf_error <= ahb_hresp_q; - end else if (_T_175) begin - slvbuf_error <= 1'h0; - end else if (_T_186) begin - slvbuf_error <= ahb_hresp_q; - end else if (_T_188) begin - slvbuf_error <= 1'h0; - end else begin - slvbuf_error <= _GEN_6; - end - end - end - always @(posedge buf_clk or posedge reset) begin - if (reset) begin - slvbuf_tag <= 3'h0; - end else if (slvbuf_wr_en) begin - slvbuf_tag <= buf_tag; - end - end - always @(posedge ahbm_clk or posedge reset) begin - if (reset) begin - last_bus_addr <= 32'h0; - end else if (last_addr_en) begin - last_bus_addr <= io_ahb_out_haddr; - end - end - always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin - if (reset) begin - buf_data <= 64'h0; - end else if (_T_489) begin - buf_data <= ahb_hrdata_q; - end else begin - buf_data <= wrbuf_data; - end - end - always @(posedge ahbm_data_clk or posedge reset) begin - if (reset) begin - ahb_hrdata_q <= 64'h0; - end else begin - ahb_hrdata_q <= io_ahb_in_hrdata; - end - end - always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin - if (reset) begin - buf_addr <= 32'h0; - end else begin - buf_addr <= {master_addr[31:3],_T_485}; - end - end - always @(posedge ahbm_clk or posedge reset) begin - if (reset) begin - buf_cmd_byte_ptrQ <= 3'h0; - end else if (buf_cmd_byte_ptr_en) begin - if (_T_49) begin - if (buf_write_in) begin - if (wrbuf_byteen[0]) begin - buf_cmd_byte_ptrQ <= 3'h0; - end else if (wrbuf_byteen[1]) begin - buf_cmd_byte_ptrQ <= 3'h1; - end else if (wrbuf_byteen[2]) begin - buf_cmd_byte_ptrQ <= 3'h2; - end else if (wrbuf_byteen[3]) begin - buf_cmd_byte_ptrQ <= 3'h3; - end else if (wrbuf_byteen[4]) begin - buf_cmd_byte_ptrQ <= 3'h4; - end else if (wrbuf_byteen[5]) begin - buf_cmd_byte_ptrQ <= 3'h5; - end else if (wrbuf_byteen[6]) begin - buf_cmd_byte_ptrQ <= 3'h6; - end else begin - buf_cmd_byte_ptrQ <= 3'h7; - end - end else begin - buf_cmd_byte_ptrQ <= master_addr[2:0]; - end - end else if (_T_101) begin - if (bypass_en) begin - buf_cmd_byte_ptrQ <= master_addr[2:0]; - end else begin - buf_cmd_byte_ptrQ <= buf_addr[2:0]; - end - end else if (_T_136) begin - if (bypass_en) begin - buf_cmd_byte_ptrQ <= master_addr[2:0]; - end else begin - buf_cmd_byte_ptrQ <= buf_addr[2:0]; - end - end else if (_T_175) begin - buf_cmd_byte_ptrQ <= buf_addr[2:0]; - end else if (_T_186) begin - buf_cmd_byte_ptrQ <= 3'h0; - end else if (_T_188) begin - if (trxn_done) begin - if (_T_201) begin - buf_cmd_byte_ptrQ <= 3'h0; - end else if (_T_204) begin - buf_cmd_byte_ptrQ <= 3'h1; - end else if (_T_207) begin - buf_cmd_byte_ptrQ <= 3'h2; - end else if (_T_210) begin - buf_cmd_byte_ptrQ <= 3'h3; - end else if (_T_213) begin - buf_cmd_byte_ptrQ <= 3'h4; - end else if (_T_216) begin - buf_cmd_byte_ptrQ <= 3'h5; - end else if (_T_219) begin - buf_cmd_byte_ptrQ <= 3'h6; - end else begin - buf_cmd_byte_ptrQ <= 3'h7; - end - end - end else if (_T_281) begin - if (bypass_en) begin - if (wrbuf_byteen[0]) begin - buf_cmd_byte_ptrQ <= 3'h0; - end else if (wrbuf_byteen[1]) begin - buf_cmd_byte_ptrQ <= 3'h1; - end else if (wrbuf_byteen[2]) begin - buf_cmd_byte_ptrQ <= 3'h2; - end else if (wrbuf_byteen[3]) begin - buf_cmd_byte_ptrQ <= 3'h3; - end else if (wrbuf_byteen[4]) begin - buf_cmd_byte_ptrQ <= 3'h4; - end else if (wrbuf_byteen[5]) begin - buf_cmd_byte_ptrQ <= 3'h5; - end else if (wrbuf_byteen[6]) begin - buf_cmd_byte_ptrQ <= 3'h6; - end else begin - buf_cmd_byte_ptrQ <= 3'h7; - end - end else if (trxn_done) begin - if (_T_201) begin - buf_cmd_byte_ptrQ <= 3'h0; - end else if (_T_204) begin - buf_cmd_byte_ptrQ <= 3'h1; - end else if (_T_207) begin - buf_cmd_byte_ptrQ <= 3'h2; - end else if (_T_210) begin - buf_cmd_byte_ptrQ <= 3'h3; - end else if (_T_213) begin - buf_cmd_byte_ptrQ <= 3'h4; - end else if (_T_216) begin - buf_cmd_byte_ptrQ <= 3'h5; - end else if (_T_219) begin - buf_cmd_byte_ptrQ <= 3'h6; - end else begin - buf_cmd_byte_ptrQ <= 3'h7; - end - end - end else begin - buf_cmd_byte_ptrQ <= 3'h0; - end - end - end - always @(posedge buf_clk or posedge reset) begin - if (reset) begin - buf_byteen <= 8'h0; - end else if (buf_wr_en) begin - buf_byteen <= wrbuf_byteen; - end - end - always @(posedge buf_clk or posedge reset) begin - if (reset) begin - buf_aligned <= 1'h0; - end else if (buf_wr_en) begin - buf_aligned <= buf_aligned_in; - end - end - always @(posedge buf_clk or posedge reset) begin - if (reset) begin - buf_size <= 2'h0; - end else if (buf_wr_en) begin - buf_size <= buf_size_in[1:0]; - end - end - always @(posedge buf_clk or posedge reset) begin - if (reset) begin - buf_write <= 1'h0; - end else if (buf_wr_en) begin - if (_T_49) begin - buf_write <= _T_51; - end else if (_T_101) begin - buf_write <= 1'h0; - end else if (_T_136) begin - buf_write <= 1'h0; - end else if (_T_175) begin - buf_write <= 1'h0; - end else if (_T_186) begin - buf_write <= 1'h0; - end else if (_T_188) begin - buf_write <= 1'h0; - end else begin - buf_write <= _GEN_8; - end - end - end - always @(posedge buf_clk or posedge reset) begin - if (reset) begin - buf_tag <= 3'h0; - end else if (buf_wr_en) begin - if (wr_cmd_vld) begin - buf_tag <= wrbuf_tag; - end else begin - buf_tag <= io_axi_ar_bits_id; - end - end - end -endmodule -module ahb_to_axi4( - input clock, - input reset, - input io_scan_mode, - input io_bus_clk_en, - input io_axi_aw_ready, - output io_axi_aw_valid, - output [31:0] io_axi_aw_bits_addr, - output [2:0] io_axi_aw_bits_size, - output io_axi_w_valid, - output [63:0] io_axi_w_bits_data, - output [7:0] io_axi_w_bits_strb, - input io_axi_ar_ready, - output io_axi_ar_valid, - output [31:0] io_axi_ar_bits_addr, - output [2:0] io_axi_ar_bits_size, - input io_axi_r_valid, - input [63:0] io_axi_r_bits_data, - input [1:0] io_axi_r_bits_resp, - output [63:0] io_ahb_sig_in_hrdata, - output io_ahb_sig_in_hready, - output io_ahb_sig_in_hresp, - input [31:0] io_ahb_sig_out_haddr, - input [2:0] io_ahb_sig_out_hsize, - input [1:0] io_ahb_sig_out_htrans, - input io_ahb_sig_out_hwrite, - input [63:0] io_ahb_sig_out_hwdata, - input io_ahb_hsel, - input io_ahb_hreadyin -); -`ifdef RANDOMIZE_REG_INIT - reg [31:0] _RAND_0; - reg [31:0] _RAND_1; - reg [31:0] _RAND_2; - reg [31:0] _RAND_3; - reg [31:0] _RAND_4; - reg [31:0] _RAND_5; - reg [31:0] _RAND_6; - reg [31:0] _RAND_7; - reg [63:0] _RAND_8; - reg [31:0] _RAND_9; - reg [31:0] _RAND_10; - reg [31:0] _RAND_11; - reg [31:0] _RAND_12; - reg [31:0] _RAND_13; - reg [63:0] _RAND_14; -`endif // RANDOMIZE_REG_INIT - wire rvclkhdr_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_io_en; // @[lib.scala 343:22] - wire rvclkhdr_io_scan_mode; // @[lib.scala 343:22] - wire rvclkhdr_1_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_1_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_1_io_en; // @[lib.scala 343:22] - wire rvclkhdr_1_io_scan_mode; // @[lib.scala 343:22] - wire rvclkhdr_2_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_2_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_2_io_en; // @[lib.scala 343:22] - wire rvclkhdr_2_io_scan_mode; // @[lib.scala 343:22] - wire rvclkhdr_3_io_l1clk; // @[lib.scala 368:23] - wire rvclkhdr_3_io_clk; // @[lib.scala 368:23] - wire rvclkhdr_3_io_en; // @[lib.scala 368:23] - wire rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23] - wire rvclkhdr_4_io_l1clk; // @[lib.scala 368:23] - wire rvclkhdr_4_io_clk; // @[lib.scala 368:23] - wire rvclkhdr_4_io_en; // @[lib.scala 368:23] - wire rvclkhdr_4_io_scan_mode; // @[lib.scala 368:23] - wire rvclkhdr_5_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_5_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_5_io_en; // @[lib.scala 343:22] - wire rvclkhdr_5_io_scan_mode; // @[lib.scala 343:22] - wire ahb_addr_clk = rvclkhdr_1_io_l1clk; // @[ahb_to_axi4.scala 44:33 ahb_to_axi4.scala 133:31] - reg [31:0] ahb_haddr_q; // @[ahb_to_axi4.scala 126:65] - wire ahb_addr_in_dccm = ahb_haddr_q[31:16] == 16'hf004; // @[lib.scala 87:29] - wire ahb_addr_in_iccm = ahb_haddr_q[31:16] == 16'hee00; // @[lib.scala 87:29] - wire ahb_clk = rvclkhdr_io_l1clk; // @[ahb_to_axi4.scala 43:33 ahb_to_axi4.scala 132:31] - reg [1:0] buf_state; // @[Reg.scala 27:20] - wire _T_7 = 2'h0 == buf_state; // @[Conditional.scala 37:30] - wire ahb_hready = io_ahb_sig_in_hready & io_ahb_hreadyin; // @[ahb_to_axi4.scala 104:55] - wire _T_10 = ahb_hready & io_ahb_sig_out_htrans[1]; // @[ahb_to_axi4.scala 76:34] - wire _T_11 = _T_10 & io_ahb_hsel; // @[ahb_to_axi4.scala 76:61] - wire _T_12 = 2'h1 == buf_state; // @[Conditional.scala 37:30] - wire _T_14 = io_ahb_sig_out_htrans == 2'h0; // @[ahb_to_axi4.scala 79:79] - wire _T_15 = io_ahb_sig_in_hresp | _T_14; // @[ahb_to_axi4.scala 79:48] - wire _T_16 = ~io_ahb_hsel; // @[ahb_to_axi4.scala 79:93] - wire _T_17 = _T_15 | _T_16; // @[ahb_to_axi4.scala 79:91] - wire bus_clk = rvclkhdr_5_io_l1clk; // @[ahb_to_axi4.scala 57:33 ahb_to_axi4.scala 180:27] - reg cmdbuf_vld; // @[ahb_to_axi4.scala 139:61] - wire _T_151 = io_axi_aw_valid & io_axi_aw_ready; // @[ahb_to_axi4.scala 137:67] - wire _T_152 = io_axi_ar_valid & io_axi_ar_ready; // @[ahb_to_axi4.scala 137:105] - wire _T_153 = _T_151 | _T_152; // @[ahb_to_axi4.scala 137:86] - wire _T_154 = ~_T_153; // @[ahb_to_axi4.scala 137:48] - wire cmdbuf_full = cmdbuf_vld & _T_154; // @[ahb_to_axi4.scala 137:46] - wire _T_21 = ~cmdbuf_full; // @[ahb_to_axi4.scala 80:24] - wire _T_22 = _T_21 | io_ahb_sig_in_hresp; // @[ahb_to_axi4.scala 80:37] - wire _T_25 = io_ahb_sig_out_htrans == 2'h1; // @[ahb_to_axi4.scala 81:92] - wire _T_26 = _T_25 & io_ahb_hsel; // @[ahb_to_axi4.scala 81:110] - wire _T_27 = io_ahb_sig_in_hresp | _T_26; // @[ahb_to_axi4.scala 81:60] - wire _T_28 = ~_T_27; // @[ahb_to_axi4.scala 81:38] - wire _T_29 = _T_21 & _T_28; // @[ahb_to_axi4.scala 81:36] - wire _T_30 = 2'h2 == buf_state; // @[Conditional.scala 37:30] - wire _T_34 = ~io_ahb_sig_in_hresp; // @[ahb_to_axi4.scala 86:23] - wire _T_36 = _T_34 & _T_21; // @[ahb_to_axi4.scala 86:44] - wire _T_37 = 2'h3 == buf_state; // @[Conditional.scala 37:30] - reg cmdbuf_write; // @[Reg.scala 27:20] - wire _T_38 = ~cmdbuf_write; // @[ahb_to_axi4.scala 90:40] - wire _T_39 = io_axi_r_valid & _T_38; // @[ahb_to_axi4.scala 90:38] - wire _T_41 = |io_axi_r_bits_resp; // @[ahb_to_axi4.scala 92:68] - wire _GEN_1 = _T_37 & _T_39; // @[Conditional.scala 39:67] - wire _GEN_5 = _T_30 ? _T_22 : _GEN_1; // @[Conditional.scala 39:67] - wire _GEN_10 = _T_12 ? _T_22 : _GEN_5; // @[Conditional.scala 39:67] - wire buf_state_en = _T_7 ? _T_11 : _GEN_10; // @[Conditional.scala 40:58] - wire _T_42 = buf_state_en & _T_41; // @[ahb_to_axi4.scala 92:41] - wire _GEN_2 = _T_37 & buf_state_en; // @[Conditional.scala 39:67] - wire _GEN_3 = _T_37 & _T_42; // @[Conditional.scala 39:67] - wire _GEN_6 = _T_30 & _T_36; // @[Conditional.scala 39:67] - wire _GEN_7 = _T_30 ? 1'h0 : _GEN_2; // @[Conditional.scala 39:67] - wire _GEN_11 = _T_12 ? _T_29 : _GEN_6; // @[Conditional.scala 39:67] - wire _GEN_12 = _T_12 ? 1'h0 : _GEN_7; // @[Conditional.scala 39:67] - wire cmdbuf_wr_en = _T_7 ? 1'h0 : _GEN_11; // @[Conditional.scala 40:58] - wire buf_rdata_en = _T_7 ? 1'h0 : _GEN_12; // @[Conditional.scala 40:58] - reg [2:0] ahb_hsize_q; // @[ahb_to_axi4.scala 124:65] - wire _T_46 = ahb_hsize_q == 3'h0; // @[ahb_to_axi4.scala 97:60] - wire [7:0] _T_48 = _T_46 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_50 = 8'h1 << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 97:78] - wire [7:0] _T_51 = _T_48 & _T_50; // @[ahb_to_axi4.scala 97:70] - wire _T_53 = ahb_hsize_q == 3'h1; // @[ahb_to_axi4.scala 98:30] - wire [7:0] _T_55 = _T_53 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [8:0] _T_57 = 9'h3 << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 98:48] - wire [8:0] _GEN_23 = {{1'd0}, _T_55}; // @[ahb_to_axi4.scala 98:40] - wire [8:0] _T_58 = _GEN_23 & _T_57; // @[ahb_to_axi4.scala 98:40] - wire [8:0] _GEN_24 = {{1'd0}, _T_51}; // @[ahb_to_axi4.scala 97:109] - wire [8:0] _T_59 = _GEN_24 | _T_58; // @[ahb_to_axi4.scala 97:109] - wire _T_61 = ahb_hsize_q == 3'h2; // @[ahb_to_axi4.scala 99:30] - wire [7:0] _T_63 = _T_61 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [10:0] _T_65 = 11'hf << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 99:48] - wire [10:0] _GEN_25 = {{3'd0}, _T_63}; // @[ahb_to_axi4.scala 99:40] - wire [10:0] _T_66 = _GEN_25 & _T_65; // @[ahb_to_axi4.scala 99:40] - wire [10:0] _GEN_26 = {{2'd0}, _T_59}; // @[ahb_to_axi4.scala 98:79] - wire [10:0] _T_67 = _GEN_26 | _T_66; // @[ahb_to_axi4.scala 98:79] - wire _T_69 = ahb_hsize_q == 3'h3; // @[ahb_to_axi4.scala 100:30] - wire [7:0] _T_71 = _T_69 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [10:0] _GEN_27 = {{3'd0}, _T_71}; // @[ahb_to_axi4.scala 99:79] - wire [10:0] _T_73 = _T_67 | _GEN_27; // @[ahb_to_axi4.scala 99:79] - reg ahb_hready_q; // @[ahb_to_axi4.scala 122:60] - wire _T_74 = ~ahb_hready_q; // @[ahb_to_axi4.scala 103:80] - reg ahb_hresp_q; // @[ahb_to_axi4.scala 121:60] - wire _T_75 = ahb_hresp_q & _T_74; // @[ahb_to_axi4.scala 103:78] - wire _T_77 = buf_state == 2'h0; // @[ahb_to_axi4.scala 103:124] - wire _T_78 = _T_21 | _T_77; // @[ahb_to_axi4.scala 103:111] - wire _T_79 = buf_state == 2'h2; // @[ahb_to_axi4.scala 103:149] - wire _T_80 = buf_state == 2'h3; // @[ahb_to_axi4.scala 103:168] - wire _T_81 = _T_79 | _T_80; // @[ahb_to_axi4.scala 103:156] - wire _T_82 = ~_T_81; // @[ahb_to_axi4.scala 103:137] - wire _T_83 = _T_78 & _T_82; // @[ahb_to_axi4.scala 103:135] - reg buf_read_error; // @[ahb_to_axi4.scala 118:60] - wire _T_84 = ~buf_read_error; // @[ahb_to_axi4.scala 103:181] - wire _T_85 = _T_83 & _T_84; // @[ahb_to_axi4.scala 103:179] - wire [1:0] _T_89 = io_ahb_hsel ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire buf_rdata_clk = rvclkhdr_2_io_l1clk; // @[ahb_to_axi4.scala 45:33 ahb_to_axi4.scala 134:31] - reg [63:0] buf_rdata; // @[ahb_to_axi4.scala 117:66] - reg [1:0] ahb_htrans_q; // @[ahb_to_axi4.scala 123:60] - wire _T_94 = ahb_htrans_q != 2'h0; // @[ahb_to_axi4.scala 107:61] - wire _T_95 = buf_state != 2'h0; // @[ahb_to_axi4.scala 107:83] - wire _T_96 = _T_94 & _T_95; // @[ahb_to_axi4.scala 107:70] - wire _T_97 = ahb_addr_in_dccm | ahb_addr_in_iccm; // @[ahb_to_axi4.scala 108:26] - wire _T_98 = ~_T_97; // @[ahb_to_axi4.scala 108:7] - reg ahb_hwrite_q; // @[ahb_to_axi4.scala 125:65] - wire _T_99 = ahb_addr_in_dccm & ahb_hwrite_q; // @[ahb_to_axi4.scala 109:46] - wire _T_100 = ahb_addr_in_iccm | _T_99; // @[ahb_to_axi4.scala 109:26] - wire _T_102 = ahb_hsize_q[1:0] == 2'h2; // @[ahb_to_axi4.scala 109:86] - wire _T_104 = ahb_hsize_q[1:0] == 2'h3; // @[ahb_to_axi4.scala 109:115] - wire _T_105 = _T_102 | _T_104; // @[ahb_to_axi4.scala 109:95] - wire _T_106 = ~_T_105; // @[ahb_to_axi4.scala 109:66] - wire _T_107 = _T_100 & _T_106; // @[ahb_to_axi4.scala 109:64] - wire _T_108 = _T_98 | _T_107; // @[ahb_to_axi4.scala 108:47] - wire _T_112 = _T_53 & ahb_haddr_q[0]; // @[ahb_to_axi4.scala 110:35] - wire _T_113 = _T_108 | _T_112; // @[ahb_to_axi4.scala 109:126] - wire _T_117 = |ahb_haddr_q[1:0]; // @[ahb_to_axi4.scala 111:56] - wire _T_118 = _T_61 & _T_117; // @[ahb_to_axi4.scala 111:35] - wire _T_119 = _T_113 | _T_118; // @[ahb_to_axi4.scala 110:55] - wire _T_123 = |ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 112:56] - wire _T_124 = _T_69 & _T_123; // @[ahb_to_axi4.scala 112:35] - wire _T_125 = _T_119 | _T_124; // @[ahb_to_axi4.scala 111:61] - wire _T_126 = _T_96 & _T_125; // @[ahb_to_axi4.scala 107:94] - wire _T_127 = _T_126 | buf_read_error; // @[ahb_to_axi4.scala 112:63] - wire _T_146 = ~cmdbuf_wr_en; // @[ahb_to_axi4.scala 136:113] - wire _T_147 = _T_153 & _T_146; // @[ahb_to_axi4.scala 136:111] - wire _T_149 = io_ahb_sig_in_hresp & _T_38; // @[ahb_to_axi4.scala 136:151] - wire cmdbuf_rst = _T_147 | _T_149; // @[ahb_to_axi4.scala 136:128] - wire _T_157 = cmdbuf_wr_en | cmdbuf_vld; // @[ahb_to_axi4.scala 139:66] - wire _T_158 = ~cmdbuf_rst; // @[ahb_to_axi4.scala 139:110] - reg [2:0] _T_164; // @[Reg.scala 27:20] - reg [7:0] cmdbuf_wstrb; // @[Reg.scala 27:20] - wire [7:0] master_wstrb = _T_73[7:0]; // @[ahb_to_axi4.scala 97:31] - reg [31:0] cmdbuf_addr; // @[lib.scala 374:16] - reg [63:0] cmdbuf_wdata; // @[lib.scala 374:16] - wire [1:0] cmdbuf_size = _T_164[1:0]; // @[ahb_to_axi4.scala 145:31] - rvclkhdr rvclkhdr ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_io_l1clk), - .io_clk(rvclkhdr_io_clk), - .io_en(rvclkhdr_io_en), - .io_scan_mode(rvclkhdr_io_scan_mode) - ); - rvclkhdr rvclkhdr_1 ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_1_io_l1clk), - .io_clk(rvclkhdr_1_io_clk), - .io_en(rvclkhdr_1_io_en), - .io_scan_mode(rvclkhdr_1_io_scan_mode) - ); - rvclkhdr rvclkhdr_2 ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_2_io_l1clk), - .io_clk(rvclkhdr_2_io_clk), - .io_en(rvclkhdr_2_io_en), - .io_scan_mode(rvclkhdr_2_io_scan_mode) - ); - rvclkhdr rvclkhdr_3 ( // @[lib.scala 368:23] - .io_l1clk(rvclkhdr_3_io_l1clk), - .io_clk(rvclkhdr_3_io_clk), - .io_en(rvclkhdr_3_io_en), - .io_scan_mode(rvclkhdr_3_io_scan_mode) - ); - rvclkhdr rvclkhdr_4 ( // @[lib.scala 368:23] - .io_l1clk(rvclkhdr_4_io_l1clk), - .io_clk(rvclkhdr_4_io_clk), - .io_en(rvclkhdr_4_io_en), - .io_scan_mode(rvclkhdr_4_io_scan_mode) - ); - rvclkhdr rvclkhdr_5 ( // @[lib.scala 343:22] - .io_l1clk(rvclkhdr_5_io_l1clk), - .io_clk(rvclkhdr_5_io_clk), - .io_en(rvclkhdr_5_io_en), - .io_scan_mode(rvclkhdr_5_io_scan_mode) - ); - assign io_axi_aw_valid = cmdbuf_vld & cmdbuf_write; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 156:28] - assign io_axi_aw_bits_addr = cmdbuf_addr; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 158:33] - assign io_axi_aw_bits_size = {1'h0,cmdbuf_size}; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 159:33] - assign io_axi_w_valid = cmdbuf_vld & cmdbuf_write; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 164:28] - assign io_axi_w_bits_data = cmdbuf_wdata; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 165:33] - assign io_axi_w_bits_strb = cmdbuf_wstrb; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 166:33] - assign io_axi_ar_valid = cmdbuf_vld & _T_38; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 171:28] - assign io_axi_ar_bits_addr = cmdbuf_addr; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 173:33] - assign io_axi_ar_bits_size = {1'h0,cmdbuf_size}; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 174:33] - assign io_ahb_sig_in_hrdata = buf_rdata; // @[ahb_to_axi4.scala 106:38] - assign io_ahb_sig_in_hready = io_ahb_sig_in_hresp ? _T_75 : _T_85; // @[ahb_to_axi4.scala 103:38] - assign io_ahb_sig_in_hresp = _T_127 | _T_75; // @[ahb_to_axi4.scala 107:38] - assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_io_en = io_bus_clk_en; // @[lib.scala 345:16] - assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign rvclkhdr_1_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_1_io_en = io_bus_clk_en & _T_10; // @[lib.scala 345:16] - assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign rvclkhdr_2_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_2_io_en = io_bus_clk_en & buf_rdata_en; // @[lib.scala 345:16] - assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign rvclkhdr_3_io_clk = rvclkhdr_5_io_l1clk; // @[lib.scala 370:18] - assign rvclkhdr_3_io_en = _T_7 ? 1'h0 : _GEN_11; // @[lib.scala 371:17] - assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] - assign rvclkhdr_4_io_clk = rvclkhdr_5_io_l1clk; // @[lib.scala 370:18] - assign rvclkhdr_4_io_en = _T_7 ? 1'h0 : _GEN_11; // @[lib.scala 371:17] - assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] - assign rvclkhdr_5_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_5_io_en = io_bus_clk_en; // @[lib.scala 345:16] - assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] -`ifdef RANDOMIZE_GARBAGE_ASSIGN -`define RANDOMIZE -`endif -`ifdef RANDOMIZE_INVALID_ASSIGN -`define RANDOMIZE -`endif -`ifdef RANDOMIZE_REG_INIT -`define RANDOMIZE -`endif -`ifdef RANDOMIZE_MEM_INIT -`define RANDOMIZE -`endif -`ifndef RANDOM -`define RANDOM $random -`endif -`ifdef RANDOMIZE_MEM_INIT - integer initvar; -`endif -`ifndef SYNTHESIS -`ifdef FIRRTL_BEFORE_INITIAL -`FIRRTL_BEFORE_INITIAL -`endif -initial begin - `ifdef RANDOMIZE - `ifdef INIT_RANDOM - `INIT_RANDOM - `endif - `ifndef VERILATOR - `ifdef RANDOMIZE_DELAY - #`RANDOMIZE_DELAY begin end - `else - #0.002 begin end - `endif - `endif -`ifdef RANDOMIZE_REG_INIT - _RAND_0 = {1{`RANDOM}}; - ahb_haddr_q = _RAND_0[31:0]; - _RAND_1 = {1{`RANDOM}}; - buf_state = _RAND_1[1:0]; - _RAND_2 = {1{`RANDOM}}; - cmdbuf_vld = _RAND_2[0:0]; - _RAND_3 = {1{`RANDOM}}; - cmdbuf_write = _RAND_3[0:0]; - _RAND_4 = {1{`RANDOM}}; - ahb_hsize_q = _RAND_4[2:0]; - _RAND_5 = {1{`RANDOM}}; - ahb_hready_q = _RAND_5[0:0]; - _RAND_6 = {1{`RANDOM}}; - ahb_hresp_q = _RAND_6[0:0]; - _RAND_7 = {1{`RANDOM}}; - buf_read_error = _RAND_7[0:0]; - _RAND_8 = {2{`RANDOM}}; - buf_rdata = _RAND_8[63:0]; - _RAND_9 = {1{`RANDOM}}; - ahb_htrans_q = _RAND_9[1:0]; - _RAND_10 = {1{`RANDOM}}; - ahb_hwrite_q = _RAND_10[0:0]; - _RAND_11 = {1{`RANDOM}}; - _T_164 = _RAND_11[2:0]; - _RAND_12 = {1{`RANDOM}}; - cmdbuf_wstrb = _RAND_12[7:0]; - _RAND_13 = {1{`RANDOM}}; - cmdbuf_addr = _RAND_13[31:0]; - _RAND_14 = {2{`RANDOM}}; - cmdbuf_wdata = _RAND_14[63:0]; -`endif // RANDOMIZE_REG_INIT - if (reset) begin - ahb_haddr_q = 32'h0; - end - if (reset) begin - buf_state = 2'h0; - end - if (reset) begin - cmdbuf_vld = 1'h0; - end - if (reset) begin - cmdbuf_write = 1'h0; - end - if (reset) begin - ahb_hsize_q = 3'h0; - end - if (reset) begin - ahb_hready_q = 1'h0; - end - if (reset) begin - ahb_hresp_q = 1'h0; - end - if (reset) begin - buf_read_error = 1'h0; - end - if (reset) begin - buf_rdata = 64'h0; - end - if (reset) begin - ahb_htrans_q = 2'h0; - end - if (reset) begin - ahb_hwrite_q = 1'h0; - end - if (reset) begin - _T_164 = 3'h0; - end - if (reset) begin - cmdbuf_wstrb = 8'h0; - end - if (reset) begin - cmdbuf_addr = 32'h0; - end - if (reset) begin - cmdbuf_wdata = 64'h0; - end - `endif // RANDOMIZE -end // initial -`ifdef FIRRTL_AFTER_INITIAL -`FIRRTL_AFTER_INITIAL -`endif -`endif // SYNTHESIS - always @(posedge ahb_addr_clk or posedge reset) begin - if (reset) begin - ahb_haddr_q <= 32'h0; - end else begin - ahb_haddr_q <= io_ahb_sig_out_haddr; - end - end - always @(posedge ahb_clk or posedge reset) begin - if (reset) begin - buf_state <= 2'h0; - end else if (buf_state_en) begin - if (_T_7) begin - if (io_ahb_sig_out_hwrite) begin - buf_state <= 2'h1; - end else begin - buf_state <= 2'h2; - end - end else if (_T_12) begin - if (_T_17) begin - buf_state <= 2'h0; - end else if (io_ahb_sig_out_hwrite) begin - buf_state <= 2'h1; - end else begin - buf_state <= 2'h2; - end - end else if (_T_30) begin - if (io_ahb_sig_in_hresp) begin - buf_state <= 2'h0; - end else begin - buf_state <= 2'h3; - end - end else begin - buf_state <= 2'h0; - end - end - end - always @(posedge bus_clk or posedge reset) begin - if (reset) begin - cmdbuf_vld <= 1'h0; - end else begin - cmdbuf_vld <= _T_157 & _T_158; - end - end - always @(posedge bus_clk or posedge reset) begin - if (reset) begin - cmdbuf_write <= 1'h0; - end else if (cmdbuf_wr_en) begin - cmdbuf_write <= ahb_hwrite_q; - end - end - always @(posedge ahb_addr_clk or posedge reset) begin - if (reset) begin - ahb_hsize_q <= 3'h0; - end else begin - ahb_hsize_q <= io_ahb_sig_out_hsize; - end - end - always @(posedge ahb_clk or posedge reset) begin - if (reset) begin - ahb_hready_q <= 1'h0; - end else begin - ahb_hready_q <= io_ahb_sig_in_hready & io_ahb_hreadyin; - end - end - always @(posedge ahb_clk or posedge reset) begin - if (reset) begin - ahb_hresp_q <= 1'h0; - end else begin - ahb_hresp_q <= io_ahb_sig_in_hresp; - end - end - always @(posedge ahb_clk or posedge reset) begin - if (reset) begin - buf_read_error <= 1'h0; - end else if (_T_7) begin - buf_read_error <= 1'h0; - end else if (_T_12) begin - buf_read_error <= 1'h0; - end else if (_T_30) begin - buf_read_error <= 1'h0; - end else begin - buf_read_error <= _GEN_3; - end - end - always @(posedge buf_rdata_clk or posedge reset) begin - if (reset) begin - buf_rdata <= 64'h0; - end else begin - buf_rdata <= io_axi_r_bits_data; - end - end - always @(posedge ahb_clk or posedge reset) begin - if (reset) begin - ahb_htrans_q <= 2'h0; - end else begin - ahb_htrans_q <= _T_89 & io_ahb_sig_out_htrans; - end - end - always @(posedge ahb_addr_clk or posedge reset) begin - if (reset) begin - ahb_hwrite_q <= 1'h0; - end else begin - ahb_hwrite_q <= io_ahb_sig_out_hwrite; - end - end - always @(posedge bus_clk or posedge reset) begin - if (reset) begin - _T_164 <= 3'h0; - end else if (cmdbuf_wr_en) begin - _T_164 <= ahb_hsize_q; - end - end - always @(posedge bus_clk or posedge reset) begin - if (reset) begin - cmdbuf_wstrb <= 8'h0; - end else if (cmdbuf_wr_en) begin - cmdbuf_wstrb <= master_wstrb; - end - end - always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin - if (reset) begin - cmdbuf_addr <= 32'h0; - end else begin - cmdbuf_addr <= ahb_haddr_q; - end - end - always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin - if (reset) begin - cmdbuf_wdata <= 64'h0; - end else begin - cmdbuf_wdata <= io_ahb_sig_out_hwdata; - end - end -endmodule module quasar( input clock, input reset, - input [63:0] io_lsu_ahb_in_hrdata, - input io_lsu_ahb_in_hready, - input io_lsu_ahb_in_hresp, - output [31:0] io_lsu_ahb_out_haddr, - output [2:0] io_lsu_ahb_out_hsize, - output [1:0] io_lsu_ahb_out_htrans, - output io_lsu_ahb_out_hwrite, - output [63:0] io_lsu_ahb_out_hwdata, - input [63:0] io_ifu_ahb_in_hrdata, - input io_ifu_ahb_in_hready, - input io_ifu_ahb_in_hresp, - output [31:0] io_ifu_ahb_out_haddr, - output [2:0] io_ifu_ahb_out_hsize, - output [1:0] io_ifu_ahb_out_htrans, - output io_ifu_ahb_out_hwrite, - output [63:0] io_ifu_ahb_out_hwdata, - input [63:0] io_sb_ahb_in_hrdata, - input io_sb_ahb_in_hready, - input io_sb_ahb_in_hresp, - output [31:0] io_sb_ahb_out_haddr, - output [2:0] io_sb_ahb_out_hsize, - output [1:0] io_sb_ahb_out_htrans, - output io_sb_ahb_out_hwrite, - output [63:0] io_sb_ahb_out_hwdata, - output [63:0] io_dma_ahb_sig_in_hrdata, - output io_dma_ahb_sig_in_hready, - output io_dma_ahb_sig_in_hresp, - input [31:0] io_dma_ahb_sig_out_haddr, - input [2:0] io_dma_ahb_sig_out_hsize, - input [1:0] io_dma_ahb_sig_out_htrans, - input io_dma_ahb_sig_out_hwrite, - input [63:0] io_dma_ahb_sig_out_hwdata, - input io_dma_ahb_hsel, - input io_dma_ahb_hreadyin, + input io_lsu_axi_aw_ready, + output io_lsu_axi_aw_valid, + output [2:0] io_lsu_axi_aw_bits_id, + output [31:0] io_lsu_axi_aw_bits_addr, + output [3:0] io_lsu_axi_aw_bits_region, + output [2:0] io_lsu_axi_aw_bits_size, + output [3:0] io_lsu_axi_aw_bits_cache, + input io_lsu_axi_w_ready, + output io_lsu_axi_w_valid, + output [63:0] io_lsu_axi_w_bits_data, + output [7:0] io_lsu_axi_w_bits_strb, + input io_lsu_axi_b_valid, + input [1:0] io_lsu_axi_b_bits_resp, + input [2:0] io_lsu_axi_b_bits_id, + input io_lsu_axi_ar_ready, + output io_lsu_axi_ar_valid, + output [2:0] io_lsu_axi_ar_bits_id, + output [31:0] io_lsu_axi_ar_bits_addr, + output [3:0] io_lsu_axi_ar_bits_region, + output [2:0] io_lsu_axi_ar_bits_size, + output [3:0] io_lsu_axi_ar_bits_cache, + input io_lsu_axi_r_valid, + input [2:0] io_lsu_axi_r_bits_id, + input [63:0] io_lsu_axi_r_bits_data, + input [1:0] io_lsu_axi_r_bits_resp, + input io_ifu_axi_ar_ready, + output io_ifu_axi_ar_valid, + output [2:0] io_ifu_axi_ar_bits_id, + output [31:0] io_ifu_axi_ar_bits_addr, + output [3:0] io_ifu_axi_ar_bits_region, + input io_ifu_axi_r_valid, + input [2:0] io_ifu_axi_r_bits_id, + input [63:0] io_ifu_axi_r_bits_data, + input [1:0] io_ifu_axi_r_bits_resp, + input io_sb_axi_aw_ready, + output io_sb_axi_aw_valid, + output [31:0] io_sb_axi_aw_bits_addr, + output [3:0] io_sb_axi_aw_bits_region, + output [2:0] io_sb_axi_aw_bits_size, + input io_sb_axi_w_ready, + output io_sb_axi_w_valid, + output [63:0] io_sb_axi_w_bits_data, + output [7:0] io_sb_axi_w_bits_strb, + input io_sb_axi_b_valid, + input [1:0] io_sb_axi_b_bits_resp, + input io_sb_axi_ar_ready, + output io_sb_axi_ar_valid, + output [31:0] io_sb_axi_ar_bits_addr, + output [3:0] io_sb_axi_ar_bits_region, + output [2:0] io_sb_axi_ar_bits_size, + input io_sb_axi_r_valid, + input [63:0] io_sb_axi_r_bits_data, + input [1:0] io_sb_axi_r_bits_resp, + output io_dma_axi_aw_ready, + input io_dma_axi_aw_valid, + input io_dma_axi_aw_bits_id, + input [31:0] io_dma_axi_aw_bits_addr, + input [2:0] io_dma_axi_aw_bits_size, + output io_dma_axi_w_ready, + input io_dma_axi_w_valid, + input [63:0] io_dma_axi_w_bits_data, + input [7:0] io_dma_axi_w_bits_strb, + input io_dma_axi_b_ready, + output io_dma_axi_b_valid, + output [1:0] io_dma_axi_b_bits_resp, + output io_dma_axi_b_bits_id, + output io_dma_axi_ar_ready, + input io_dma_axi_ar_valid, + input io_dma_axi_ar_bits_id, + input [31:0] io_dma_axi_ar_bits_addr, + input [2:0] io_dma_axi_ar_bits_size, + input io_dma_axi_r_ready, + output io_dma_axi_r_valid, + output io_dma_axi_r_bits_id, + output [63:0] io_dma_axi_r_bits_data, + output [1:0] io_dma_axi_r_bits_resp, input io_dbg_rst_l, input [30:0] io_rst_vec, input io_nmi_int, @@ -83103,6 +80831,7 @@ module quasar( wire ifu_io_ifu_ar_valid; // @[quasar.scala 74:19] wire [2:0] ifu_io_ifu_ar_bits_id; // @[quasar.scala 74:19] wire [31:0] ifu_io_ifu_ar_bits_addr; // @[quasar.scala 74:19] + wire [3:0] ifu_io_ifu_ar_bits_region; // @[quasar.scala 74:19] wire ifu_io_ifu_r_valid; // @[quasar.scala 74:19] wire [2:0] ifu_io_ifu_r_bits_id; // @[quasar.scala 74:19] wire [63:0] ifu_io_ifu_r_bits_data; // @[quasar.scala 74:19] @@ -83223,7 +80952,6 @@ module quasar( wire [31:0] dec_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar.scala 75:19] wire dec_io_dec_tlu_misc_clk_override; // @[quasar.scala 75:19] wire dec_io_dec_tlu_lsu_clk_override; // @[quasar.scala 75:19] - wire dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 75:19] wire dec_io_dec_tlu_pic_clk_override; // @[quasar.scala 75:19] wire dec_io_dec_tlu_dccm_clk_override; // @[quasar.scala 75:19] wire dec_io_dec_tlu_icm_clk_override; // @[quasar.scala 75:19] @@ -83361,6 +81089,7 @@ module quasar( wire dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[quasar.scala 75:19] wire dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[quasar.scala 75:19] wire dec_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 75:19] + wire dec_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[quasar.scala 75:19] wire dec_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 75:19] wire dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[quasar.scala 75:19] wire dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[quasar.scala 75:19] @@ -83415,6 +81144,7 @@ module quasar( wire dbg_io_sb_axi_aw_ready; // @[quasar.scala 76:19] wire dbg_io_sb_axi_aw_valid; // @[quasar.scala 76:19] wire [31:0] dbg_io_sb_axi_aw_bits_addr; // @[quasar.scala 76:19] + wire [3:0] dbg_io_sb_axi_aw_bits_region; // @[quasar.scala 76:19] wire [2:0] dbg_io_sb_axi_aw_bits_size; // @[quasar.scala 76:19] wire dbg_io_sb_axi_w_ready; // @[quasar.scala 76:19] wire dbg_io_sb_axi_w_valid; // @[quasar.scala 76:19] @@ -83426,6 +81156,7 @@ module quasar( wire dbg_io_sb_axi_ar_ready; // @[quasar.scala 76:19] wire dbg_io_sb_axi_ar_valid; // @[quasar.scala 76:19] wire [31:0] dbg_io_sb_axi_ar_bits_addr; // @[quasar.scala 76:19] + wire [3:0] dbg_io_sb_axi_ar_bits_region; // @[quasar.scala 76:19] wire [2:0] dbg_io_sb_axi_ar_bits_size; // @[quasar.scala 76:19] wire dbg_io_sb_axi_r_ready; // @[quasar.scala 76:19] wire dbg_io_sb_axi_r_valid; // @[quasar.scala 76:19] @@ -83580,6 +81311,7 @@ module quasar( wire lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[quasar.scala 78:19] wire lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[quasar.scala 78:19] wire lsu_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 78:19] + wire lsu_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[quasar.scala 78:19] wire lsu_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 78:19] wire lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[quasar.scala 78:19] wire lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[quasar.scala 78:19] @@ -83608,7 +81340,9 @@ module quasar( wire lsu_io_axi_aw_valid; // @[quasar.scala 78:19] wire [2:0] lsu_io_axi_aw_bits_id; // @[quasar.scala 78:19] wire [31:0] lsu_io_axi_aw_bits_addr; // @[quasar.scala 78:19] + wire [3:0] lsu_io_axi_aw_bits_region; // @[quasar.scala 78:19] wire [2:0] lsu_io_axi_aw_bits_size; // @[quasar.scala 78:19] + wire [3:0] lsu_io_axi_aw_bits_cache; // @[quasar.scala 78:19] wire lsu_io_axi_w_ready; // @[quasar.scala 78:19] wire lsu_io_axi_w_valid; // @[quasar.scala 78:19] wire [63:0] lsu_io_axi_w_bits_data; // @[quasar.scala 78:19] @@ -83620,7 +81354,9 @@ module quasar( wire lsu_io_axi_ar_valid; // @[quasar.scala 78:19] wire [2:0] lsu_io_axi_ar_bits_id; // @[quasar.scala 78:19] wire [31:0] lsu_io_axi_ar_bits_addr; // @[quasar.scala 78:19] + wire [3:0] lsu_io_axi_ar_bits_region; // @[quasar.scala 78:19] wire [2:0] lsu_io_axi_ar_bits_size; // @[quasar.scala 78:19] + wire [3:0] lsu_io_axi_ar_bits_cache; // @[quasar.scala 78:19] wire lsu_io_axi_r_valid; // @[quasar.scala 78:19] wire [2:0] lsu_io_axi_r_bits_id; // @[quasar.scala 78:19] wire [63:0] lsu_io_axi_r_bits_data; // @[quasar.scala 78:19] @@ -83734,18 +81470,25 @@ module quasar( wire dma_ctrl_io_iccm_ready; // @[quasar.scala 80:24] wire dma_ctrl_io_dma_axi_aw_ready; // @[quasar.scala 80:24] wire dma_ctrl_io_dma_axi_aw_valid; // @[quasar.scala 80:24] + wire dma_ctrl_io_dma_axi_aw_bits_id; // @[quasar.scala 80:24] wire [31:0] dma_ctrl_io_dma_axi_aw_bits_addr; // @[quasar.scala 80:24] wire [2:0] dma_ctrl_io_dma_axi_aw_bits_size; // @[quasar.scala 80:24] wire dma_ctrl_io_dma_axi_w_ready; // @[quasar.scala 80:24] wire dma_ctrl_io_dma_axi_w_valid; // @[quasar.scala 80:24] wire [63:0] dma_ctrl_io_dma_axi_w_bits_data; // @[quasar.scala 80:24] wire [7:0] dma_ctrl_io_dma_axi_w_bits_strb; // @[quasar.scala 80:24] + wire dma_ctrl_io_dma_axi_b_ready; // @[quasar.scala 80:24] wire dma_ctrl_io_dma_axi_b_valid; // @[quasar.scala 80:24] + wire [1:0] dma_ctrl_io_dma_axi_b_bits_resp; // @[quasar.scala 80:24] + wire dma_ctrl_io_dma_axi_b_bits_id; // @[quasar.scala 80:24] wire dma_ctrl_io_dma_axi_ar_ready; // @[quasar.scala 80:24] wire dma_ctrl_io_dma_axi_ar_valid; // @[quasar.scala 80:24] + wire dma_ctrl_io_dma_axi_ar_bits_id; // @[quasar.scala 80:24] wire [31:0] dma_ctrl_io_dma_axi_ar_bits_addr; // @[quasar.scala 80:24] wire [2:0] dma_ctrl_io_dma_axi_ar_bits_size; // @[quasar.scala 80:24] + wire dma_ctrl_io_dma_axi_r_ready; // @[quasar.scala 80:24] wire dma_ctrl_io_dma_axi_r_valid; // @[quasar.scala 80:24] + wire dma_ctrl_io_dma_axi_r_bits_id; // @[quasar.scala 80:24] wire [63:0] dma_ctrl_io_dma_axi_r_bits_data; // @[quasar.scala 80:24] wire [1:0] dma_ctrl_io_dma_axi_r_bits_resp; // @[quasar.scala 80:24] wire dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_dccm_req; // @[quasar.scala 80:24] @@ -83776,132 +81519,6 @@ module quasar( wire rvclkhdr_1_io_clk; // @[lib.scala 343:22] wire rvclkhdr_1_io_en; // @[lib.scala 343:22] wire rvclkhdr_1_io_scan_mode; // @[lib.scala 343:22] - wire axi4_to_ahb_clock; // @[quasar.scala 241:32] - wire axi4_to_ahb_reset; // @[quasar.scala 241:32] - wire axi4_to_ahb_io_scan_mode; // @[quasar.scala 241:32] - wire axi4_to_ahb_io_bus_clk_en; // @[quasar.scala 241:32] - wire axi4_to_ahb_io_clk_override; // @[quasar.scala 241:32] - wire axi4_to_ahb_io_axi_aw_ready; // @[quasar.scala 241:32] - wire axi4_to_ahb_io_axi_aw_valid; // @[quasar.scala 241:32] - wire [31:0] axi4_to_ahb_io_axi_aw_bits_addr; // @[quasar.scala 241:32] - wire [2:0] axi4_to_ahb_io_axi_aw_bits_size; // @[quasar.scala 241:32] - wire axi4_to_ahb_io_axi_w_ready; // @[quasar.scala 241:32] - wire axi4_to_ahb_io_axi_w_valid; // @[quasar.scala 241:32] - wire [63:0] axi4_to_ahb_io_axi_w_bits_data; // @[quasar.scala 241:32] - wire [7:0] axi4_to_ahb_io_axi_w_bits_strb; // @[quasar.scala 241:32] - wire axi4_to_ahb_io_axi_b_valid; // @[quasar.scala 241:32] - wire [1:0] axi4_to_ahb_io_axi_b_bits_resp; // @[quasar.scala 241:32] - wire axi4_to_ahb_io_axi_ar_ready; // @[quasar.scala 241:32] - wire axi4_to_ahb_io_axi_ar_valid; // @[quasar.scala 241:32] - wire [31:0] axi4_to_ahb_io_axi_ar_bits_addr; // @[quasar.scala 241:32] - wire [2:0] axi4_to_ahb_io_axi_ar_bits_size; // @[quasar.scala 241:32] - wire axi4_to_ahb_io_axi_r_valid; // @[quasar.scala 241:32] - wire [63:0] axi4_to_ahb_io_axi_r_bits_data; // @[quasar.scala 241:32] - wire [1:0] axi4_to_ahb_io_axi_r_bits_resp; // @[quasar.scala 241:32] - wire [63:0] axi4_to_ahb_io_ahb_in_hrdata; // @[quasar.scala 241:32] - wire axi4_to_ahb_io_ahb_in_hready; // @[quasar.scala 241:32] - wire axi4_to_ahb_io_ahb_in_hresp; // @[quasar.scala 241:32] - wire [31:0] axi4_to_ahb_io_ahb_out_haddr; // @[quasar.scala 241:32] - wire [2:0] axi4_to_ahb_io_ahb_out_hsize; // @[quasar.scala 241:32] - wire [1:0] axi4_to_ahb_io_ahb_out_htrans; // @[quasar.scala 241:32] - wire axi4_to_ahb_io_ahb_out_hwrite; // @[quasar.scala 241:32] - wire [63:0] axi4_to_ahb_io_ahb_out_hwdata; // @[quasar.scala 241:32] - wire axi4_to_ahb_1_clock; // @[quasar.scala 242:33] - wire axi4_to_ahb_1_reset; // @[quasar.scala 242:33] - wire axi4_to_ahb_1_io_scan_mode; // @[quasar.scala 242:33] - wire axi4_to_ahb_1_io_bus_clk_en; // @[quasar.scala 242:33] - wire axi4_to_ahb_1_io_clk_override; // @[quasar.scala 242:33] - wire axi4_to_ahb_1_io_axi_aw_ready; // @[quasar.scala 242:33] - wire axi4_to_ahb_1_io_axi_aw_valid; // @[quasar.scala 242:33] - wire [2:0] axi4_to_ahb_1_io_axi_aw_bits_id; // @[quasar.scala 242:33] - wire [31:0] axi4_to_ahb_1_io_axi_aw_bits_addr; // @[quasar.scala 242:33] - wire [2:0] axi4_to_ahb_1_io_axi_aw_bits_size; // @[quasar.scala 242:33] - wire axi4_to_ahb_1_io_axi_w_ready; // @[quasar.scala 242:33] - wire axi4_to_ahb_1_io_axi_w_valid; // @[quasar.scala 242:33] - wire [63:0] axi4_to_ahb_1_io_axi_w_bits_data; // @[quasar.scala 242:33] - wire [7:0] axi4_to_ahb_1_io_axi_w_bits_strb; // @[quasar.scala 242:33] - wire axi4_to_ahb_1_io_axi_b_valid; // @[quasar.scala 242:33] - wire [1:0] axi4_to_ahb_1_io_axi_b_bits_resp; // @[quasar.scala 242:33] - wire [2:0] axi4_to_ahb_1_io_axi_b_bits_id; // @[quasar.scala 242:33] - wire axi4_to_ahb_1_io_axi_ar_ready; // @[quasar.scala 242:33] - wire axi4_to_ahb_1_io_axi_ar_valid; // @[quasar.scala 242:33] - wire [2:0] axi4_to_ahb_1_io_axi_ar_bits_id; // @[quasar.scala 242:33] - wire [31:0] axi4_to_ahb_1_io_axi_ar_bits_addr; // @[quasar.scala 242:33] - wire [2:0] axi4_to_ahb_1_io_axi_ar_bits_size; // @[quasar.scala 242:33] - wire axi4_to_ahb_1_io_axi_r_valid; // @[quasar.scala 242:33] - wire [2:0] axi4_to_ahb_1_io_axi_r_bits_id; // @[quasar.scala 242:33] - wire [63:0] axi4_to_ahb_1_io_axi_r_bits_data; // @[quasar.scala 242:33] - wire [1:0] axi4_to_ahb_1_io_axi_r_bits_resp; // @[quasar.scala 242:33] - wire [63:0] axi4_to_ahb_1_io_ahb_in_hrdata; // @[quasar.scala 242:33] - wire axi4_to_ahb_1_io_ahb_in_hready; // @[quasar.scala 242:33] - wire axi4_to_ahb_1_io_ahb_in_hresp; // @[quasar.scala 242:33] - wire [31:0] axi4_to_ahb_1_io_ahb_out_haddr; // @[quasar.scala 242:33] - wire [2:0] axi4_to_ahb_1_io_ahb_out_hsize; // @[quasar.scala 242:33] - wire [1:0] axi4_to_ahb_1_io_ahb_out_htrans; // @[quasar.scala 242:33] - wire axi4_to_ahb_1_io_ahb_out_hwrite; // @[quasar.scala 242:33] - wire [63:0] axi4_to_ahb_1_io_ahb_out_hwdata; // @[quasar.scala 242:33] - wire axi4_to_ahb_2_clock; // @[quasar.scala 243:33] - wire axi4_to_ahb_2_reset; // @[quasar.scala 243:33] - wire axi4_to_ahb_2_io_scan_mode; // @[quasar.scala 243:33] - wire axi4_to_ahb_2_io_bus_clk_en; // @[quasar.scala 243:33] - wire axi4_to_ahb_2_io_clk_override; // @[quasar.scala 243:33] - wire axi4_to_ahb_2_io_axi_aw_ready; // @[quasar.scala 243:33] - wire axi4_to_ahb_2_io_axi_aw_valid; // @[quasar.scala 243:33] - wire [2:0] axi4_to_ahb_2_io_axi_aw_bits_id; // @[quasar.scala 243:33] - wire [31:0] axi4_to_ahb_2_io_axi_aw_bits_addr; // @[quasar.scala 243:33] - wire [2:0] axi4_to_ahb_2_io_axi_aw_bits_size; // @[quasar.scala 243:33] - wire axi4_to_ahb_2_io_axi_w_ready; // @[quasar.scala 243:33] - wire axi4_to_ahb_2_io_axi_w_valid; // @[quasar.scala 243:33] - wire [63:0] axi4_to_ahb_2_io_axi_w_bits_data; // @[quasar.scala 243:33] - wire [7:0] axi4_to_ahb_2_io_axi_w_bits_strb; // @[quasar.scala 243:33] - wire axi4_to_ahb_2_io_axi_b_valid; // @[quasar.scala 243:33] - wire [1:0] axi4_to_ahb_2_io_axi_b_bits_resp; // @[quasar.scala 243:33] - wire [2:0] axi4_to_ahb_2_io_axi_b_bits_id; // @[quasar.scala 243:33] - wire axi4_to_ahb_2_io_axi_ar_ready; // @[quasar.scala 243:33] - wire axi4_to_ahb_2_io_axi_ar_valid; // @[quasar.scala 243:33] - wire [2:0] axi4_to_ahb_2_io_axi_ar_bits_id; // @[quasar.scala 243:33] - wire [31:0] axi4_to_ahb_2_io_axi_ar_bits_addr; // @[quasar.scala 243:33] - wire [2:0] axi4_to_ahb_2_io_axi_ar_bits_size; // @[quasar.scala 243:33] - wire axi4_to_ahb_2_io_axi_r_valid; // @[quasar.scala 243:33] - wire [2:0] axi4_to_ahb_2_io_axi_r_bits_id; // @[quasar.scala 243:33] - wire [63:0] axi4_to_ahb_2_io_axi_r_bits_data; // @[quasar.scala 243:33] - wire [1:0] axi4_to_ahb_2_io_axi_r_bits_resp; // @[quasar.scala 243:33] - wire [63:0] axi4_to_ahb_2_io_ahb_in_hrdata; // @[quasar.scala 243:33] - wire axi4_to_ahb_2_io_ahb_in_hready; // @[quasar.scala 243:33] - wire axi4_to_ahb_2_io_ahb_in_hresp; // @[quasar.scala 243:33] - wire [31:0] axi4_to_ahb_2_io_ahb_out_haddr; // @[quasar.scala 243:33] - wire [2:0] axi4_to_ahb_2_io_ahb_out_hsize; // @[quasar.scala 243:33] - wire [1:0] axi4_to_ahb_2_io_ahb_out_htrans; // @[quasar.scala 243:33] - wire axi4_to_ahb_2_io_ahb_out_hwrite; // @[quasar.scala 243:33] - wire [63:0] axi4_to_ahb_2_io_ahb_out_hwdata; // @[quasar.scala 243:33] - wire ahb_to_axi4_clock; // @[quasar.scala 244:33] - wire ahb_to_axi4_reset; // @[quasar.scala 244:33] - wire ahb_to_axi4_io_scan_mode; // @[quasar.scala 244:33] - wire ahb_to_axi4_io_bus_clk_en; // @[quasar.scala 244:33] - wire ahb_to_axi4_io_axi_aw_ready; // @[quasar.scala 244:33] - wire ahb_to_axi4_io_axi_aw_valid; // @[quasar.scala 244:33] - wire [31:0] ahb_to_axi4_io_axi_aw_bits_addr; // @[quasar.scala 244:33] - wire [2:0] ahb_to_axi4_io_axi_aw_bits_size; // @[quasar.scala 244:33] - wire ahb_to_axi4_io_axi_w_valid; // @[quasar.scala 244:33] - wire [63:0] ahb_to_axi4_io_axi_w_bits_data; // @[quasar.scala 244:33] - wire [7:0] ahb_to_axi4_io_axi_w_bits_strb; // @[quasar.scala 244:33] - wire ahb_to_axi4_io_axi_ar_ready; // @[quasar.scala 244:33] - wire ahb_to_axi4_io_axi_ar_valid; // @[quasar.scala 244:33] - wire [31:0] ahb_to_axi4_io_axi_ar_bits_addr; // @[quasar.scala 244:33] - wire [2:0] ahb_to_axi4_io_axi_ar_bits_size; // @[quasar.scala 244:33] - wire ahb_to_axi4_io_axi_r_valid; // @[quasar.scala 244:33] - wire [63:0] ahb_to_axi4_io_axi_r_bits_data; // @[quasar.scala 244:33] - wire [1:0] ahb_to_axi4_io_axi_r_bits_resp; // @[quasar.scala 244:33] - wire [63:0] ahb_to_axi4_io_ahb_sig_in_hrdata; // @[quasar.scala 244:33] - wire ahb_to_axi4_io_ahb_sig_in_hready; // @[quasar.scala 244:33] - wire ahb_to_axi4_io_ahb_sig_in_hresp; // @[quasar.scala 244:33] - wire [31:0] ahb_to_axi4_io_ahb_sig_out_haddr; // @[quasar.scala 244:33] - wire [2:0] ahb_to_axi4_io_ahb_sig_out_hsize; // @[quasar.scala 244:33] - wire [1:0] ahb_to_axi4_io_ahb_sig_out_htrans; // @[quasar.scala 244:33] - wire ahb_to_axi4_io_ahb_sig_out_hwrite; // @[quasar.scala 244:33] - wire [63:0] ahb_to_axi4_io_ahb_sig_out_hwdata; // @[quasar.scala 244:33] - wire ahb_to_axi4_io_ahb_hsel; // @[quasar.scala 244:33] - wire ahb_to_axi4_io_ahb_hreadyin; // @[quasar.scala 244:33] wire _T_1 = dbg_io_dbg_core_rst_l; // @[quasar.scala 82:67] wire _T_2 = _T_1 | io_scan_mode; // @[quasar.scala 82:70] wire _T_5 = ~dec_io_dec_pause_state_cg; // @[quasar.scala 83:23] @@ -84014,6 +81631,7 @@ module quasar( .io_ifu_ar_valid(ifu_io_ifu_ar_valid), .io_ifu_ar_bits_id(ifu_io_ifu_ar_bits_id), .io_ifu_ar_bits_addr(ifu_io_ifu_ar_bits_addr), + .io_ifu_ar_bits_region(ifu_io_ifu_ar_bits_region), .io_ifu_r_valid(ifu_io_ifu_r_valid), .io_ifu_r_bits_id(ifu_io_ifu_r_bits_id), .io_ifu_r_bits_data(ifu_io_ifu_r_bits_data), @@ -84136,7 +81754,6 @@ module quasar( .io_rv_trace_pkt_rv_i_tval_ip(dec_io_rv_trace_pkt_rv_i_tval_ip), .io_dec_tlu_misc_clk_override(dec_io_dec_tlu_misc_clk_override), .io_dec_tlu_lsu_clk_override(dec_io_dec_tlu_lsu_clk_override), - .io_dec_tlu_bus_clk_override(dec_io_dec_tlu_bus_clk_override), .io_dec_tlu_pic_clk_override(dec_io_dec_tlu_pic_clk_override), .io_dec_tlu_dccm_clk_override(dec_io_dec_tlu_dccm_clk_override), .io_dec_tlu_icm_clk_override(dec_io_dec_tlu_icm_clk_override), @@ -84274,6 +81891,7 @@ module quasar( .io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error(dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error), .io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy(dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy), .io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable(dec_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable), + .io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable(dec_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable), .io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable(dec_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable), .io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any(dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any), .io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any(dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any), @@ -84330,6 +81948,7 @@ module quasar( .io_sb_axi_aw_ready(dbg_io_sb_axi_aw_ready), .io_sb_axi_aw_valid(dbg_io_sb_axi_aw_valid), .io_sb_axi_aw_bits_addr(dbg_io_sb_axi_aw_bits_addr), + .io_sb_axi_aw_bits_region(dbg_io_sb_axi_aw_bits_region), .io_sb_axi_aw_bits_size(dbg_io_sb_axi_aw_bits_size), .io_sb_axi_w_ready(dbg_io_sb_axi_w_ready), .io_sb_axi_w_valid(dbg_io_sb_axi_w_valid), @@ -84341,6 +81960,7 @@ module quasar( .io_sb_axi_ar_ready(dbg_io_sb_axi_ar_ready), .io_sb_axi_ar_valid(dbg_io_sb_axi_ar_valid), .io_sb_axi_ar_bits_addr(dbg_io_sb_axi_ar_bits_addr), + .io_sb_axi_ar_bits_region(dbg_io_sb_axi_ar_bits_region), .io_sb_axi_ar_bits_size(dbg_io_sb_axi_ar_bits_size), .io_sb_axi_r_ready(dbg_io_sb_axi_r_ready), .io_sb_axi_r_valid(dbg_io_sb_axi_r_valid), @@ -84499,6 +82119,7 @@ module quasar( .io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error(lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error), .io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy(lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy), .io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable(lsu_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable), + .io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable(lsu_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable), .io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable(lsu_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable), .io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any(lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any), .io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any(lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any), @@ -84527,7 +82148,9 @@ module quasar( .io_axi_aw_valid(lsu_io_axi_aw_valid), .io_axi_aw_bits_id(lsu_io_axi_aw_bits_id), .io_axi_aw_bits_addr(lsu_io_axi_aw_bits_addr), + .io_axi_aw_bits_region(lsu_io_axi_aw_bits_region), .io_axi_aw_bits_size(lsu_io_axi_aw_bits_size), + .io_axi_aw_bits_cache(lsu_io_axi_aw_bits_cache), .io_axi_w_ready(lsu_io_axi_w_ready), .io_axi_w_valid(lsu_io_axi_w_valid), .io_axi_w_bits_data(lsu_io_axi_w_bits_data), @@ -84539,7 +82162,9 @@ module quasar( .io_axi_ar_valid(lsu_io_axi_ar_valid), .io_axi_ar_bits_id(lsu_io_axi_ar_bits_id), .io_axi_ar_bits_addr(lsu_io_axi_ar_bits_addr), + .io_axi_ar_bits_region(lsu_io_axi_ar_bits_region), .io_axi_ar_bits_size(lsu_io_axi_ar_bits_size), + .io_axi_ar_bits_cache(lsu_io_axi_ar_bits_cache), .io_axi_r_valid(lsu_io_axi_r_valid), .io_axi_r_bits_id(lsu_io_axi_r_bits_id), .io_axi_r_bits_data(lsu_io_axi_r_bits_data), @@ -84657,18 +82282,25 @@ module quasar( .io_iccm_ready(dma_ctrl_io_iccm_ready), .io_dma_axi_aw_ready(dma_ctrl_io_dma_axi_aw_ready), .io_dma_axi_aw_valid(dma_ctrl_io_dma_axi_aw_valid), + .io_dma_axi_aw_bits_id(dma_ctrl_io_dma_axi_aw_bits_id), .io_dma_axi_aw_bits_addr(dma_ctrl_io_dma_axi_aw_bits_addr), .io_dma_axi_aw_bits_size(dma_ctrl_io_dma_axi_aw_bits_size), .io_dma_axi_w_ready(dma_ctrl_io_dma_axi_w_ready), .io_dma_axi_w_valid(dma_ctrl_io_dma_axi_w_valid), .io_dma_axi_w_bits_data(dma_ctrl_io_dma_axi_w_bits_data), .io_dma_axi_w_bits_strb(dma_ctrl_io_dma_axi_w_bits_strb), + .io_dma_axi_b_ready(dma_ctrl_io_dma_axi_b_ready), .io_dma_axi_b_valid(dma_ctrl_io_dma_axi_b_valid), + .io_dma_axi_b_bits_resp(dma_ctrl_io_dma_axi_b_bits_resp), + .io_dma_axi_b_bits_id(dma_ctrl_io_dma_axi_b_bits_id), .io_dma_axi_ar_ready(dma_ctrl_io_dma_axi_ar_ready), .io_dma_axi_ar_valid(dma_ctrl_io_dma_axi_ar_valid), + .io_dma_axi_ar_bits_id(dma_ctrl_io_dma_axi_ar_bits_id), .io_dma_axi_ar_bits_addr(dma_ctrl_io_dma_axi_ar_bits_addr), .io_dma_axi_ar_bits_size(dma_ctrl_io_dma_axi_ar_bits_size), + .io_dma_axi_r_ready(dma_ctrl_io_dma_axi_r_ready), .io_dma_axi_r_valid(dma_ctrl_io_dma_axi_r_valid), + .io_dma_axi_r_bits_id(dma_ctrl_io_dma_axi_r_bits_id), .io_dma_axi_r_bits_data(dma_ctrl_io_dma_axi_r_bits_data), .io_dma_axi_r_bits_resp(dma_ctrl_io_dma_axi_r_bits_resp), .io_lsu_dma_dma_lsc_ctl_dma_dccm_req(dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_dccm_req), @@ -84704,158 +82336,46 @@ module quasar( .io_en(rvclkhdr_1_io_en), .io_scan_mode(rvclkhdr_1_io_scan_mode) ); - axi4_to_ahb axi4_to_ahb ( // @[quasar.scala 241:32] - .clock(axi4_to_ahb_clock), - .reset(axi4_to_ahb_reset), - .io_scan_mode(axi4_to_ahb_io_scan_mode), - .io_bus_clk_en(axi4_to_ahb_io_bus_clk_en), - .io_clk_override(axi4_to_ahb_io_clk_override), - .io_axi_aw_ready(axi4_to_ahb_io_axi_aw_ready), - .io_axi_aw_valid(axi4_to_ahb_io_axi_aw_valid), - .io_axi_aw_bits_addr(axi4_to_ahb_io_axi_aw_bits_addr), - .io_axi_aw_bits_size(axi4_to_ahb_io_axi_aw_bits_size), - .io_axi_w_ready(axi4_to_ahb_io_axi_w_ready), - .io_axi_w_valid(axi4_to_ahb_io_axi_w_valid), - .io_axi_w_bits_data(axi4_to_ahb_io_axi_w_bits_data), - .io_axi_w_bits_strb(axi4_to_ahb_io_axi_w_bits_strb), - .io_axi_b_valid(axi4_to_ahb_io_axi_b_valid), - .io_axi_b_bits_resp(axi4_to_ahb_io_axi_b_bits_resp), - .io_axi_ar_ready(axi4_to_ahb_io_axi_ar_ready), - .io_axi_ar_valid(axi4_to_ahb_io_axi_ar_valid), - .io_axi_ar_bits_addr(axi4_to_ahb_io_axi_ar_bits_addr), - .io_axi_ar_bits_size(axi4_to_ahb_io_axi_ar_bits_size), - .io_axi_r_valid(axi4_to_ahb_io_axi_r_valid), - .io_axi_r_bits_data(axi4_to_ahb_io_axi_r_bits_data), - .io_axi_r_bits_resp(axi4_to_ahb_io_axi_r_bits_resp), - .io_ahb_in_hrdata(axi4_to_ahb_io_ahb_in_hrdata), - .io_ahb_in_hready(axi4_to_ahb_io_ahb_in_hready), - .io_ahb_in_hresp(axi4_to_ahb_io_ahb_in_hresp), - .io_ahb_out_haddr(axi4_to_ahb_io_ahb_out_haddr), - .io_ahb_out_hsize(axi4_to_ahb_io_ahb_out_hsize), - .io_ahb_out_htrans(axi4_to_ahb_io_ahb_out_htrans), - .io_ahb_out_hwrite(axi4_to_ahb_io_ahb_out_hwrite), - .io_ahb_out_hwdata(axi4_to_ahb_io_ahb_out_hwdata) - ); - axi4_to_ahb_1 axi4_to_ahb_1 ( // @[quasar.scala 242:33] - .clock(axi4_to_ahb_1_clock), - .reset(axi4_to_ahb_1_reset), - .io_scan_mode(axi4_to_ahb_1_io_scan_mode), - .io_bus_clk_en(axi4_to_ahb_1_io_bus_clk_en), - .io_clk_override(axi4_to_ahb_1_io_clk_override), - .io_axi_aw_ready(axi4_to_ahb_1_io_axi_aw_ready), - .io_axi_aw_valid(axi4_to_ahb_1_io_axi_aw_valid), - .io_axi_aw_bits_id(axi4_to_ahb_1_io_axi_aw_bits_id), - .io_axi_aw_bits_addr(axi4_to_ahb_1_io_axi_aw_bits_addr), - .io_axi_aw_bits_size(axi4_to_ahb_1_io_axi_aw_bits_size), - .io_axi_w_ready(axi4_to_ahb_1_io_axi_w_ready), - .io_axi_w_valid(axi4_to_ahb_1_io_axi_w_valid), - .io_axi_w_bits_data(axi4_to_ahb_1_io_axi_w_bits_data), - .io_axi_w_bits_strb(axi4_to_ahb_1_io_axi_w_bits_strb), - .io_axi_b_valid(axi4_to_ahb_1_io_axi_b_valid), - .io_axi_b_bits_resp(axi4_to_ahb_1_io_axi_b_bits_resp), - .io_axi_b_bits_id(axi4_to_ahb_1_io_axi_b_bits_id), - .io_axi_ar_ready(axi4_to_ahb_1_io_axi_ar_ready), - .io_axi_ar_valid(axi4_to_ahb_1_io_axi_ar_valid), - .io_axi_ar_bits_id(axi4_to_ahb_1_io_axi_ar_bits_id), - .io_axi_ar_bits_addr(axi4_to_ahb_1_io_axi_ar_bits_addr), - .io_axi_ar_bits_size(axi4_to_ahb_1_io_axi_ar_bits_size), - .io_axi_r_valid(axi4_to_ahb_1_io_axi_r_valid), - .io_axi_r_bits_id(axi4_to_ahb_1_io_axi_r_bits_id), - .io_axi_r_bits_data(axi4_to_ahb_1_io_axi_r_bits_data), - .io_axi_r_bits_resp(axi4_to_ahb_1_io_axi_r_bits_resp), - .io_ahb_in_hrdata(axi4_to_ahb_1_io_ahb_in_hrdata), - .io_ahb_in_hready(axi4_to_ahb_1_io_ahb_in_hready), - .io_ahb_in_hresp(axi4_to_ahb_1_io_ahb_in_hresp), - .io_ahb_out_haddr(axi4_to_ahb_1_io_ahb_out_haddr), - .io_ahb_out_hsize(axi4_to_ahb_1_io_ahb_out_hsize), - .io_ahb_out_htrans(axi4_to_ahb_1_io_ahb_out_htrans), - .io_ahb_out_hwrite(axi4_to_ahb_1_io_ahb_out_hwrite), - .io_ahb_out_hwdata(axi4_to_ahb_1_io_ahb_out_hwdata) - ); - axi4_to_ahb_1 axi4_to_ahb_2 ( // @[quasar.scala 243:33] - .clock(axi4_to_ahb_2_clock), - .reset(axi4_to_ahb_2_reset), - .io_scan_mode(axi4_to_ahb_2_io_scan_mode), - .io_bus_clk_en(axi4_to_ahb_2_io_bus_clk_en), - .io_clk_override(axi4_to_ahb_2_io_clk_override), - .io_axi_aw_ready(axi4_to_ahb_2_io_axi_aw_ready), - .io_axi_aw_valid(axi4_to_ahb_2_io_axi_aw_valid), - .io_axi_aw_bits_id(axi4_to_ahb_2_io_axi_aw_bits_id), - .io_axi_aw_bits_addr(axi4_to_ahb_2_io_axi_aw_bits_addr), - .io_axi_aw_bits_size(axi4_to_ahb_2_io_axi_aw_bits_size), - .io_axi_w_ready(axi4_to_ahb_2_io_axi_w_ready), - .io_axi_w_valid(axi4_to_ahb_2_io_axi_w_valid), - .io_axi_w_bits_data(axi4_to_ahb_2_io_axi_w_bits_data), - .io_axi_w_bits_strb(axi4_to_ahb_2_io_axi_w_bits_strb), - .io_axi_b_valid(axi4_to_ahb_2_io_axi_b_valid), - .io_axi_b_bits_resp(axi4_to_ahb_2_io_axi_b_bits_resp), - .io_axi_b_bits_id(axi4_to_ahb_2_io_axi_b_bits_id), - .io_axi_ar_ready(axi4_to_ahb_2_io_axi_ar_ready), - .io_axi_ar_valid(axi4_to_ahb_2_io_axi_ar_valid), - .io_axi_ar_bits_id(axi4_to_ahb_2_io_axi_ar_bits_id), - .io_axi_ar_bits_addr(axi4_to_ahb_2_io_axi_ar_bits_addr), - .io_axi_ar_bits_size(axi4_to_ahb_2_io_axi_ar_bits_size), - .io_axi_r_valid(axi4_to_ahb_2_io_axi_r_valid), - .io_axi_r_bits_id(axi4_to_ahb_2_io_axi_r_bits_id), - .io_axi_r_bits_data(axi4_to_ahb_2_io_axi_r_bits_data), - .io_axi_r_bits_resp(axi4_to_ahb_2_io_axi_r_bits_resp), - .io_ahb_in_hrdata(axi4_to_ahb_2_io_ahb_in_hrdata), - .io_ahb_in_hready(axi4_to_ahb_2_io_ahb_in_hready), - .io_ahb_in_hresp(axi4_to_ahb_2_io_ahb_in_hresp), - .io_ahb_out_haddr(axi4_to_ahb_2_io_ahb_out_haddr), - .io_ahb_out_hsize(axi4_to_ahb_2_io_ahb_out_hsize), - .io_ahb_out_htrans(axi4_to_ahb_2_io_ahb_out_htrans), - .io_ahb_out_hwrite(axi4_to_ahb_2_io_ahb_out_hwrite), - .io_ahb_out_hwdata(axi4_to_ahb_2_io_ahb_out_hwdata) - ); - ahb_to_axi4 ahb_to_axi4 ( // @[quasar.scala 244:33] - .clock(ahb_to_axi4_clock), - .reset(ahb_to_axi4_reset), - .io_scan_mode(ahb_to_axi4_io_scan_mode), - .io_bus_clk_en(ahb_to_axi4_io_bus_clk_en), - .io_axi_aw_ready(ahb_to_axi4_io_axi_aw_ready), - .io_axi_aw_valid(ahb_to_axi4_io_axi_aw_valid), - .io_axi_aw_bits_addr(ahb_to_axi4_io_axi_aw_bits_addr), - .io_axi_aw_bits_size(ahb_to_axi4_io_axi_aw_bits_size), - .io_axi_w_valid(ahb_to_axi4_io_axi_w_valid), - .io_axi_w_bits_data(ahb_to_axi4_io_axi_w_bits_data), - .io_axi_w_bits_strb(ahb_to_axi4_io_axi_w_bits_strb), - .io_axi_ar_ready(ahb_to_axi4_io_axi_ar_ready), - .io_axi_ar_valid(ahb_to_axi4_io_axi_ar_valid), - .io_axi_ar_bits_addr(ahb_to_axi4_io_axi_ar_bits_addr), - .io_axi_ar_bits_size(ahb_to_axi4_io_axi_ar_bits_size), - .io_axi_r_valid(ahb_to_axi4_io_axi_r_valid), - .io_axi_r_bits_data(ahb_to_axi4_io_axi_r_bits_data), - .io_axi_r_bits_resp(ahb_to_axi4_io_axi_r_bits_resp), - .io_ahb_sig_in_hrdata(ahb_to_axi4_io_ahb_sig_in_hrdata), - .io_ahb_sig_in_hready(ahb_to_axi4_io_ahb_sig_in_hready), - .io_ahb_sig_in_hresp(ahb_to_axi4_io_ahb_sig_in_hresp), - .io_ahb_sig_out_haddr(ahb_to_axi4_io_ahb_sig_out_haddr), - .io_ahb_sig_out_hsize(ahb_to_axi4_io_ahb_sig_out_hsize), - .io_ahb_sig_out_htrans(ahb_to_axi4_io_ahb_sig_out_htrans), - .io_ahb_sig_out_hwrite(ahb_to_axi4_io_ahb_sig_out_hwrite), - .io_ahb_sig_out_hwdata(ahb_to_axi4_io_ahb_sig_out_hwdata), - .io_ahb_hsel(ahb_to_axi4_io_ahb_hsel), - .io_ahb_hreadyin(ahb_to_axi4_io_ahb_hreadyin) - ); - assign io_lsu_ahb_out_haddr = axi4_to_ahb_2_io_ahb_out_haddr; // @[quasar.scala 250:28] - assign io_lsu_ahb_out_hsize = axi4_to_ahb_2_io_ahb_out_hsize; // @[quasar.scala 250:28] - assign io_lsu_ahb_out_htrans = axi4_to_ahb_2_io_ahb_out_htrans; // @[quasar.scala 250:28] - assign io_lsu_ahb_out_hwrite = axi4_to_ahb_2_io_ahb_out_hwrite; // @[quasar.scala 250:28] - assign io_lsu_ahb_out_hwdata = axi4_to_ahb_2_io_ahb_out_hwdata; // @[quasar.scala 250:28] - assign io_ifu_ahb_out_haddr = axi4_to_ahb_1_io_ahb_out_haddr; // @[quasar.scala 256:28] - assign io_ifu_ahb_out_hsize = axi4_to_ahb_1_io_ahb_out_hsize; // @[quasar.scala 256:28] - assign io_ifu_ahb_out_htrans = axi4_to_ahb_1_io_ahb_out_htrans; // @[quasar.scala 256:28] - assign io_ifu_ahb_out_hwrite = axi4_to_ahb_1_io_ahb_out_hwrite; // @[quasar.scala 256:28] - assign io_ifu_ahb_out_hwdata = axi4_to_ahb_1_io_ahb_out_hwdata; // @[quasar.scala 256:28] - assign io_sb_ahb_out_haddr = axi4_to_ahb_io_ahb_out_haddr; // @[quasar.scala 263:27] - assign io_sb_ahb_out_hsize = axi4_to_ahb_io_ahb_out_hsize; // @[quasar.scala 263:27] - assign io_sb_ahb_out_htrans = axi4_to_ahb_io_ahb_out_htrans; // @[quasar.scala 263:27] - assign io_sb_ahb_out_hwrite = axi4_to_ahb_io_ahb_out_hwrite; // @[quasar.scala 263:27] - assign io_sb_ahb_out_hwdata = axi4_to_ahb_io_ahb_out_hwdata; // @[quasar.scala 263:27] - assign io_dma_ahb_sig_in_hrdata = ahb_to_axi4_io_ahb_sig_in_hrdata; // @[quasar.scala 269:28] - assign io_dma_ahb_sig_in_hready = ahb_to_axi4_io_ahb_sig_in_hready; // @[quasar.scala 269:28] - assign io_dma_ahb_sig_in_hresp = ahb_to_axi4_io_ahb_sig_in_hresp; // @[quasar.scala 269:28] + assign io_lsu_axi_aw_valid = lsu_io_axi_aw_valid; // @[quasar.scala 284:27] + assign io_lsu_axi_aw_bits_id = lsu_io_axi_aw_bits_id; // @[quasar.scala 284:27] + assign io_lsu_axi_aw_bits_addr = lsu_io_axi_aw_bits_addr; // @[quasar.scala 284:27] + assign io_lsu_axi_aw_bits_region = lsu_io_axi_aw_bits_region; // @[quasar.scala 284:27] + assign io_lsu_axi_aw_bits_size = lsu_io_axi_aw_bits_size; // @[quasar.scala 284:27] + assign io_lsu_axi_aw_bits_cache = lsu_io_axi_aw_bits_cache; // @[quasar.scala 284:27] + assign io_lsu_axi_w_valid = lsu_io_axi_w_valid; // @[quasar.scala 284:27] + assign io_lsu_axi_w_bits_data = lsu_io_axi_w_bits_data; // @[quasar.scala 284:27] + assign io_lsu_axi_w_bits_strb = lsu_io_axi_w_bits_strb; // @[quasar.scala 284:27] + assign io_lsu_axi_ar_valid = lsu_io_axi_ar_valid; // @[quasar.scala 284:27] + assign io_lsu_axi_ar_bits_id = lsu_io_axi_ar_bits_id; // @[quasar.scala 284:27] + assign io_lsu_axi_ar_bits_addr = lsu_io_axi_ar_bits_addr; // @[quasar.scala 284:27] + assign io_lsu_axi_ar_bits_region = lsu_io_axi_ar_bits_region; // @[quasar.scala 284:27] + assign io_lsu_axi_ar_bits_size = lsu_io_axi_ar_bits_size; // @[quasar.scala 284:27] + assign io_lsu_axi_ar_bits_cache = lsu_io_axi_ar_bits_cache; // @[quasar.scala 284:27] + assign io_ifu_axi_ar_valid = ifu_io_ifu_ar_valid; // @[quasar.scala 283:27] + assign io_ifu_axi_ar_bits_id = ifu_io_ifu_ar_bits_id; // @[quasar.scala 283:27] + assign io_ifu_axi_ar_bits_addr = ifu_io_ifu_ar_bits_addr; // @[quasar.scala 283:27] + assign io_ifu_axi_ar_bits_region = ifu_io_ifu_ar_bits_region; // @[quasar.scala 283:27] + assign io_sb_axi_aw_valid = dbg_io_sb_axi_aw_valid; // @[quasar.scala 282:27] + assign io_sb_axi_aw_bits_addr = dbg_io_sb_axi_aw_bits_addr; // @[quasar.scala 282:27] + assign io_sb_axi_aw_bits_region = dbg_io_sb_axi_aw_bits_region; // @[quasar.scala 282:27] + assign io_sb_axi_aw_bits_size = dbg_io_sb_axi_aw_bits_size; // @[quasar.scala 282:27] + assign io_sb_axi_w_valid = dbg_io_sb_axi_w_valid; // @[quasar.scala 282:27] + assign io_sb_axi_w_bits_data = dbg_io_sb_axi_w_bits_data; // @[quasar.scala 282:27] + assign io_sb_axi_w_bits_strb = dbg_io_sb_axi_w_bits_strb; // @[quasar.scala 282:27] + assign io_sb_axi_ar_valid = dbg_io_sb_axi_ar_valid; // @[quasar.scala 282:27] + assign io_sb_axi_ar_bits_addr = dbg_io_sb_axi_ar_bits_addr; // @[quasar.scala 282:27] + assign io_sb_axi_ar_bits_region = dbg_io_sb_axi_ar_bits_region; // @[quasar.scala 282:27] + assign io_sb_axi_ar_bits_size = dbg_io_sb_axi_ar_bits_size; // @[quasar.scala 282:27] + assign io_dma_axi_aw_ready = dma_ctrl_io_dma_axi_aw_ready; // @[quasar.scala 281:27] + assign io_dma_axi_w_ready = dma_ctrl_io_dma_axi_w_ready; // @[quasar.scala 281:27] + assign io_dma_axi_b_valid = dma_ctrl_io_dma_axi_b_valid; // @[quasar.scala 281:27] + assign io_dma_axi_b_bits_resp = dma_ctrl_io_dma_axi_b_bits_resp; // @[quasar.scala 281:27] + assign io_dma_axi_b_bits_id = dma_ctrl_io_dma_axi_b_bits_id; // @[quasar.scala 281:27] + assign io_dma_axi_ar_ready = dma_ctrl_io_dma_axi_ar_ready; // @[quasar.scala 281:27] + assign io_dma_axi_r_valid = dma_ctrl_io_dma_axi_r_valid; // @[quasar.scala 281:27] + assign io_dma_axi_r_bits_id = dma_ctrl_io_dma_axi_r_bits_id; // @[quasar.scala 281:27] + assign io_dma_axi_r_bits_data = dma_ctrl_io_dma_axi_r_bits_data; // @[quasar.scala 281:27] + assign io_dma_axi_r_bits_resp = dma_ctrl_io_dma_axi_r_bits_resp; // @[quasar.scala 281:27] assign io_core_rst_l = reset & _T_2; // @[quasar.scala 82:17] assign io_rv_trace_pkt_rv_i_valid_ip = dec_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar.scala 218:19] assign io_rv_trace_pkt_rv_i_insn_ip = dec_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar.scala 218:19] @@ -84958,11 +82478,11 @@ module quasar( assign ifu_io_ic_eccerr = io_ic_eccerr; // @[quasar.scala 100:13] assign ifu_io_ic_rd_hit = io_ic_rd_hit; // @[quasar.scala 100:13] assign ifu_io_ic_tag_perr = io_ic_tag_perr; // @[quasar.scala 100:13] - assign ifu_io_ifu_ar_ready = axi4_to_ahb_1_io_axi_ar_ready; // @[quasar.scala 255:28] - assign ifu_io_ifu_r_valid = axi4_to_ahb_1_io_axi_r_valid; // @[quasar.scala 255:28] - assign ifu_io_ifu_r_bits_id = axi4_to_ahb_1_io_axi_r_bits_id; // @[quasar.scala 255:28] - assign ifu_io_ifu_r_bits_data = axi4_to_ahb_1_io_axi_r_bits_data; // @[quasar.scala 255:28] - assign ifu_io_ifu_r_bits_resp = axi4_to_ahb_1_io_axi_r_bits_resp; // @[quasar.scala 255:28] + assign ifu_io_ifu_ar_ready = io_ifu_axi_ar_ready; // @[quasar.scala 283:27] + assign ifu_io_ifu_r_valid = io_ifu_axi_r_valid; // @[quasar.scala 283:27] + assign ifu_io_ifu_r_bits_id = io_ifu_axi_r_bits_id; // @[quasar.scala 283:27] + assign ifu_io_ifu_r_bits_data = io_ifu_axi_r_bits_data; // @[quasar.scala 283:27] + assign ifu_io_ifu_r_bits_resp = io_ifu_axi_r_bits_resp; // @[quasar.scala 283:27] assign ifu_io_ifu_bus_clk_en = io_ifu_bus_clk_en; // @[quasar.scala 98:25] assign ifu_io_ifu_dma_dma_ifc_dma_iccm_stall_any = dma_ctrl_io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[quasar.scala 99:18] assign ifu_io_ifu_dma_dma_mem_ctl_dma_iccm_req = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[quasar.scala 99:18] @@ -85104,14 +82624,14 @@ module quasar( assign dbg_io_dmi_reg_addr = io_dmi_reg_addr; // @[quasar.scala 184:23] assign dbg_io_dmi_reg_wr_en = io_dmi_reg_wr_en; // @[quasar.scala 185:24] assign dbg_io_dmi_reg_wdata = io_dmi_reg_wdata; // @[quasar.scala 186:24] - assign dbg_io_sb_axi_aw_ready = axi4_to_ahb_io_axi_aw_ready; // @[quasar.scala 262:27] - assign dbg_io_sb_axi_w_ready = axi4_to_ahb_io_axi_w_ready; // @[quasar.scala 262:27] - assign dbg_io_sb_axi_b_valid = axi4_to_ahb_io_axi_b_valid; // @[quasar.scala 262:27] - assign dbg_io_sb_axi_b_bits_resp = axi4_to_ahb_io_axi_b_bits_resp; // @[quasar.scala 262:27] - assign dbg_io_sb_axi_ar_ready = axi4_to_ahb_io_axi_ar_ready; // @[quasar.scala 262:27] - assign dbg_io_sb_axi_r_valid = axi4_to_ahb_io_axi_r_valid; // @[quasar.scala 262:27] - assign dbg_io_sb_axi_r_bits_data = axi4_to_ahb_io_axi_r_bits_data; // @[quasar.scala 262:27] - assign dbg_io_sb_axi_r_bits_resp = axi4_to_ahb_io_axi_r_bits_resp; // @[quasar.scala 262:27] + assign dbg_io_sb_axi_aw_ready = io_sb_axi_aw_ready; // @[quasar.scala 282:27] + assign dbg_io_sb_axi_w_ready = io_sb_axi_w_ready; // @[quasar.scala 282:27] + assign dbg_io_sb_axi_b_valid = io_sb_axi_b_valid; // @[quasar.scala 282:27] + assign dbg_io_sb_axi_b_bits_resp = io_sb_axi_b_bits_resp; // @[quasar.scala 282:27] + assign dbg_io_sb_axi_ar_ready = io_sb_axi_ar_ready; // @[quasar.scala 282:27] + assign dbg_io_sb_axi_r_valid = io_sb_axi_r_valid; // @[quasar.scala 282:27] + assign dbg_io_sb_axi_r_bits_data = io_sb_axi_r_bits_data; // @[quasar.scala 282:27] + assign dbg_io_sb_axi_r_bits_resp = io_sb_axi_r_bits_resp; // @[quasar.scala 282:27] assign dbg_io_dbg_dma_io_dma_dbg_ready = dma_ctrl_io_dbg_dma_io_dma_dbg_ready; // @[quasar.scala 200:26] assign dbg_io_dbg_bus_clk_en = io_dbg_bus_clk_en; // @[quasar.scala 187:25] assign dbg_io_dbg_rst_l = io_dbg_rst_l; // @[quasar.scala 188:20] @@ -85199,19 +82719,20 @@ module quasar( assign lsu_io_lsu_exu_exu_lsu_rs1_d = exu_io_lsu_exu_exu_lsu_rs1_d; // @[quasar.scala 163:18] assign lsu_io_lsu_exu_exu_lsu_rs2_d = exu_io_lsu_exu_exu_lsu_rs2_d; // @[quasar.scala 163:18] assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 122:18] + assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[quasar.scala 122:18] assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 122:18] assign lsu_io_dccm_rd_data_lo = io_dccm_rd_data_lo; // @[quasar.scala 238:11] assign lsu_io_dccm_rd_data_hi = io_dccm_rd_data_hi; // @[quasar.scala 238:11] - assign lsu_io_axi_aw_ready = axi4_to_ahb_2_io_axi_aw_ready; // @[quasar.scala 249:28] - assign lsu_io_axi_w_ready = axi4_to_ahb_2_io_axi_w_ready; // @[quasar.scala 249:28] - assign lsu_io_axi_b_valid = axi4_to_ahb_2_io_axi_b_valid; // @[quasar.scala 249:28] - assign lsu_io_axi_b_bits_resp = axi4_to_ahb_2_io_axi_b_bits_resp; // @[quasar.scala 249:28] - assign lsu_io_axi_b_bits_id = axi4_to_ahb_2_io_axi_b_bits_id; // @[quasar.scala 249:28] - assign lsu_io_axi_ar_ready = axi4_to_ahb_2_io_axi_ar_ready; // @[quasar.scala 249:28] - assign lsu_io_axi_r_valid = axi4_to_ahb_2_io_axi_r_valid; // @[quasar.scala 249:28] - assign lsu_io_axi_r_bits_id = axi4_to_ahb_2_io_axi_r_bits_id; // @[quasar.scala 249:28] - assign lsu_io_axi_r_bits_data = axi4_to_ahb_2_io_axi_r_bits_data; // @[quasar.scala 249:28] - assign lsu_io_axi_r_bits_resp = axi4_to_ahb_2_io_axi_r_bits_resp; // @[quasar.scala 249:28] + assign lsu_io_axi_aw_ready = io_lsu_axi_aw_ready; // @[quasar.scala 284:27] + assign lsu_io_axi_w_ready = io_lsu_axi_w_ready; // @[quasar.scala 284:27] + assign lsu_io_axi_b_valid = io_lsu_axi_b_valid; // @[quasar.scala 284:27] + assign lsu_io_axi_b_bits_resp = io_lsu_axi_b_bits_resp; // @[quasar.scala 284:27] + assign lsu_io_axi_b_bits_id = io_lsu_axi_b_bits_id; // @[quasar.scala 284:27] + assign lsu_io_axi_ar_ready = io_lsu_axi_ar_ready; // @[quasar.scala 284:27] + assign lsu_io_axi_r_valid = io_lsu_axi_r_valid; // @[quasar.scala 284:27] + assign lsu_io_axi_r_bits_id = io_lsu_axi_r_bits_id; // @[quasar.scala 284:27] + assign lsu_io_axi_r_bits_data = io_lsu_axi_r_bits_data; // @[quasar.scala 284:27] + assign lsu_io_axi_r_bits_resp = io_lsu_axi_r_bits_resp; // @[quasar.scala 284:27] assign lsu_io_dec_tlu_flush_lower_r = dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 159:32] assign lsu_io_dec_tlu_i0_kill_writeb_r = dec_io_dec_tlu_i0_kill_writeb_r; // @[quasar.scala 160:35] assign lsu_io_dec_tlu_force_halt = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 161:29] @@ -85286,15 +82807,19 @@ module quasar( assign dma_ctrl_io_iccm_dma_rtag = ifu_io_iccm_dma_rtag; // @[quasar.scala 203:29] assign dma_ctrl_io_iccm_dma_rdata = ifu_io_iccm_dma_rdata; // @[quasar.scala 204:30] assign dma_ctrl_io_iccm_ready = ifu_io_iccm_ready; // @[quasar.scala 205:26] - assign dma_ctrl_io_dma_axi_aw_valid = ahb_to_axi4_io_axi_aw_valid; // @[quasar.scala 268:28] - assign dma_ctrl_io_dma_axi_aw_bits_addr = ahb_to_axi4_io_axi_aw_bits_addr; // @[quasar.scala 268:28] - assign dma_ctrl_io_dma_axi_aw_bits_size = ahb_to_axi4_io_axi_aw_bits_size; // @[quasar.scala 268:28] - assign dma_ctrl_io_dma_axi_w_valid = ahb_to_axi4_io_axi_w_valid; // @[quasar.scala 268:28] - assign dma_ctrl_io_dma_axi_w_bits_data = ahb_to_axi4_io_axi_w_bits_data; // @[quasar.scala 268:28] - assign dma_ctrl_io_dma_axi_w_bits_strb = ahb_to_axi4_io_axi_w_bits_strb; // @[quasar.scala 268:28] - assign dma_ctrl_io_dma_axi_ar_valid = ahb_to_axi4_io_axi_ar_valid; // @[quasar.scala 268:28] - assign dma_ctrl_io_dma_axi_ar_bits_addr = ahb_to_axi4_io_axi_ar_bits_addr; // @[quasar.scala 268:28] - assign dma_ctrl_io_dma_axi_ar_bits_size = ahb_to_axi4_io_axi_ar_bits_size; // @[quasar.scala 268:28] + assign dma_ctrl_io_dma_axi_aw_valid = io_dma_axi_aw_valid; // @[quasar.scala 281:27] + assign dma_ctrl_io_dma_axi_aw_bits_id = io_dma_axi_aw_bits_id; // @[quasar.scala 281:27] + assign dma_ctrl_io_dma_axi_aw_bits_addr = io_dma_axi_aw_bits_addr; // @[quasar.scala 281:27] + assign dma_ctrl_io_dma_axi_aw_bits_size = io_dma_axi_aw_bits_size; // @[quasar.scala 281:27] + assign dma_ctrl_io_dma_axi_w_valid = io_dma_axi_w_valid; // @[quasar.scala 281:27] + assign dma_ctrl_io_dma_axi_w_bits_data = io_dma_axi_w_bits_data; // @[quasar.scala 281:27] + assign dma_ctrl_io_dma_axi_w_bits_strb = io_dma_axi_w_bits_strb; // @[quasar.scala 281:27] + assign dma_ctrl_io_dma_axi_b_ready = io_dma_axi_b_ready; // @[quasar.scala 281:27] + assign dma_ctrl_io_dma_axi_ar_valid = io_dma_axi_ar_valid; // @[quasar.scala 281:27] + assign dma_ctrl_io_dma_axi_ar_bits_id = io_dma_axi_ar_bits_id; // @[quasar.scala 281:27] + assign dma_ctrl_io_dma_axi_ar_bits_addr = io_dma_axi_ar_bits_addr; // @[quasar.scala 281:27] + assign dma_ctrl_io_dma_axi_ar_bits_size = io_dma_axi_ar_bits_size; // @[quasar.scala 281:27] + assign dma_ctrl_io_dma_axi_r_ready = io_dma_axi_r_ready; // @[quasar.scala 281:27] assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid; // @[quasar.scala 171:18] assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error; // @[quasar.scala 171:18] assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[quasar.scala 171:18] @@ -85306,77 +82831,6 @@ module quasar( assign rvclkhdr_1_io_clk = clock; // @[lib.scala 344:17] assign rvclkhdr_1_io_en = _T_6 | dec_io_dec_tlu_misc_clk_override; // @[lib.scala 345:16] assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign axi4_to_ahb_clock = clock; - assign axi4_to_ahb_reset = reset; - assign axi4_to_ahb_io_scan_mode = io_scan_mode; // @[quasar.scala 259:33] - assign axi4_to_ahb_io_bus_clk_en = io_dbg_bus_clk_en; // @[quasar.scala 260:34] - assign axi4_to_ahb_io_clk_override = dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 261:36] - assign axi4_to_ahb_io_axi_aw_valid = dbg_io_sb_axi_aw_valid; // @[quasar.scala 262:27] - assign axi4_to_ahb_io_axi_aw_bits_addr = dbg_io_sb_axi_aw_bits_addr; // @[quasar.scala 262:27] - assign axi4_to_ahb_io_axi_aw_bits_size = dbg_io_sb_axi_aw_bits_size; // @[quasar.scala 262:27] - assign axi4_to_ahb_io_axi_w_valid = dbg_io_sb_axi_w_valid; // @[quasar.scala 262:27] - assign axi4_to_ahb_io_axi_w_bits_data = dbg_io_sb_axi_w_bits_data; // @[quasar.scala 262:27] - assign axi4_to_ahb_io_axi_w_bits_strb = dbg_io_sb_axi_w_bits_strb; // @[quasar.scala 262:27] - assign axi4_to_ahb_io_axi_ar_valid = dbg_io_sb_axi_ar_valid; // @[quasar.scala 262:27] - assign axi4_to_ahb_io_axi_ar_bits_addr = dbg_io_sb_axi_ar_bits_addr; // @[quasar.scala 262:27] - assign axi4_to_ahb_io_axi_ar_bits_size = dbg_io_sb_axi_ar_bits_size; // @[quasar.scala 262:27] - assign axi4_to_ahb_io_ahb_in_hrdata = io_sb_ahb_in_hrdata; // @[quasar.scala 263:27] - assign axi4_to_ahb_io_ahb_in_hready = io_sb_ahb_in_hready; // @[quasar.scala 263:27] - assign axi4_to_ahb_io_ahb_in_hresp = io_sb_ahb_in_hresp; // @[quasar.scala 263:27] - assign axi4_to_ahb_1_clock = clock; - assign axi4_to_ahb_1_reset = reset; - assign axi4_to_ahb_1_io_scan_mode = io_scan_mode; // @[quasar.scala 252:34] - assign axi4_to_ahb_1_io_bus_clk_en = io_ifu_bus_clk_en; // @[quasar.scala 253:35] - assign axi4_to_ahb_1_io_clk_override = dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 254:37] - assign axi4_to_ahb_1_io_axi_aw_valid = 1'h0; // @[quasar.scala 255:28] - assign axi4_to_ahb_1_io_axi_aw_bits_id = 3'h0; // @[quasar.scala 255:28] - assign axi4_to_ahb_1_io_axi_aw_bits_addr = 32'h0; // @[quasar.scala 255:28] - assign axi4_to_ahb_1_io_axi_aw_bits_size = 3'h0; // @[quasar.scala 255:28] - assign axi4_to_ahb_1_io_axi_w_valid = 1'h0; // @[quasar.scala 255:28] - assign axi4_to_ahb_1_io_axi_w_bits_data = 64'h0; // @[quasar.scala 255:28] - assign axi4_to_ahb_1_io_axi_w_bits_strb = 8'h0; // @[quasar.scala 255:28] - assign axi4_to_ahb_1_io_axi_ar_valid = ifu_io_ifu_ar_valid; // @[quasar.scala 255:28] - assign axi4_to_ahb_1_io_axi_ar_bits_id = ifu_io_ifu_ar_bits_id; // @[quasar.scala 255:28] - assign axi4_to_ahb_1_io_axi_ar_bits_addr = ifu_io_ifu_ar_bits_addr; // @[quasar.scala 255:28] - assign axi4_to_ahb_1_io_axi_ar_bits_size = 3'h3; // @[quasar.scala 255:28] - assign axi4_to_ahb_1_io_ahb_in_hrdata = io_ifu_ahb_in_hrdata; // @[quasar.scala 256:28] - assign axi4_to_ahb_1_io_ahb_in_hready = io_ifu_ahb_in_hready; // @[quasar.scala 256:28] - assign axi4_to_ahb_1_io_ahb_in_hresp = io_ifu_ahb_in_hresp; // @[quasar.scala 256:28] - assign axi4_to_ahb_2_clock = clock; - assign axi4_to_ahb_2_reset = reset; - assign axi4_to_ahb_2_io_scan_mode = io_scan_mode; // @[quasar.scala 246:34] - assign axi4_to_ahb_2_io_bus_clk_en = io_lsu_bus_clk_en; // @[quasar.scala 247:35] - assign axi4_to_ahb_2_io_clk_override = dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 248:37] - assign axi4_to_ahb_2_io_axi_aw_valid = lsu_io_axi_aw_valid; // @[quasar.scala 249:28] - assign axi4_to_ahb_2_io_axi_aw_bits_id = lsu_io_axi_aw_bits_id; // @[quasar.scala 249:28] - assign axi4_to_ahb_2_io_axi_aw_bits_addr = lsu_io_axi_aw_bits_addr; // @[quasar.scala 249:28] - assign axi4_to_ahb_2_io_axi_aw_bits_size = lsu_io_axi_aw_bits_size; // @[quasar.scala 249:28] - assign axi4_to_ahb_2_io_axi_w_valid = lsu_io_axi_w_valid; // @[quasar.scala 249:28] - assign axi4_to_ahb_2_io_axi_w_bits_data = lsu_io_axi_w_bits_data; // @[quasar.scala 249:28] - assign axi4_to_ahb_2_io_axi_w_bits_strb = lsu_io_axi_w_bits_strb; // @[quasar.scala 249:28] - assign axi4_to_ahb_2_io_axi_ar_valid = lsu_io_axi_ar_valid; // @[quasar.scala 249:28] - assign axi4_to_ahb_2_io_axi_ar_bits_id = lsu_io_axi_ar_bits_id; // @[quasar.scala 249:28] - assign axi4_to_ahb_2_io_axi_ar_bits_addr = lsu_io_axi_ar_bits_addr; // @[quasar.scala 249:28] - assign axi4_to_ahb_2_io_axi_ar_bits_size = lsu_io_axi_ar_bits_size; // @[quasar.scala 249:28] - assign axi4_to_ahb_2_io_ahb_in_hrdata = io_lsu_ahb_in_hrdata; // @[quasar.scala 250:28] - assign axi4_to_ahb_2_io_ahb_in_hready = io_lsu_ahb_in_hready; // @[quasar.scala 250:28] - assign axi4_to_ahb_2_io_ahb_in_hresp = io_lsu_ahb_in_hresp; // @[quasar.scala 250:28] - assign ahb_to_axi4_clock = clock; - assign ahb_to_axi4_reset = reset; - assign ahb_to_axi4_io_scan_mode = io_scan_mode; // @[quasar.scala 265:34] - assign ahb_to_axi4_io_bus_clk_en = io_dma_bus_clk_en; // @[quasar.scala 266:35] - assign ahb_to_axi4_io_axi_aw_ready = dma_ctrl_io_dma_axi_aw_ready; // @[quasar.scala 268:28] - assign ahb_to_axi4_io_axi_ar_ready = dma_ctrl_io_dma_axi_ar_ready; // @[quasar.scala 268:28] - assign ahb_to_axi4_io_axi_r_valid = dma_ctrl_io_dma_axi_r_valid; // @[quasar.scala 268:28] - assign ahb_to_axi4_io_axi_r_bits_data = dma_ctrl_io_dma_axi_r_bits_data; // @[quasar.scala 268:28] - assign ahb_to_axi4_io_axi_r_bits_resp = dma_ctrl_io_dma_axi_r_bits_resp; // @[quasar.scala 268:28] - assign ahb_to_axi4_io_ahb_sig_out_haddr = io_dma_ahb_sig_out_haddr; // @[quasar.scala 269:28] - assign ahb_to_axi4_io_ahb_sig_out_hsize = io_dma_ahb_sig_out_hsize; // @[quasar.scala 269:28] - assign ahb_to_axi4_io_ahb_sig_out_htrans = io_dma_ahb_sig_out_htrans; // @[quasar.scala 269:28] - assign ahb_to_axi4_io_ahb_sig_out_hwrite = io_dma_ahb_sig_out_hwrite; // @[quasar.scala 269:28] - assign ahb_to_axi4_io_ahb_sig_out_hwdata = io_dma_ahb_sig_out_hwdata; // @[quasar.scala 269:28] - assign ahb_to_axi4_io_ahb_hsel = io_dma_ahb_hsel; // @[quasar.scala 269:28] - assign ahb_to_axi4_io_ahb_hreadyin = io_dma_ahb_hreadyin; // @[quasar.scala 269:28] endmodule module quasar_wrapper( input clock, @@ -85386,52 +82840,162 @@ module quasar_wrapper( input io_nmi_int, input [30:0] io_nmi_vec, input [30:0] io_jtag_id, - input [63:0] io_lsu_brg_in_hrdata, - input io_lsu_brg_in_hready, - input io_lsu_brg_in_hresp, - output [31:0] io_lsu_brg_out_haddr, - output [2:0] io_lsu_brg_out_hburst, - output io_lsu_brg_out_hmastlock, - output [3:0] io_lsu_brg_out_hprot, - output [2:0] io_lsu_brg_out_hsize, - output [1:0] io_lsu_brg_out_htrans, - output io_lsu_brg_out_hwrite, - output [63:0] io_lsu_brg_out_hwdata, - input [63:0] io_ifu_brg_in_hrdata, - input io_ifu_brg_in_hready, - input io_ifu_brg_in_hresp, - output [31:0] io_ifu_brg_out_haddr, - output [2:0] io_ifu_brg_out_hburst, - output io_ifu_brg_out_hmastlock, - output [3:0] io_ifu_brg_out_hprot, - output [2:0] io_ifu_brg_out_hsize, - output [1:0] io_ifu_brg_out_htrans, - output io_ifu_brg_out_hwrite, - output [63:0] io_ifu_brg_out_hwdata, - input [63:0] io_sb_brg_in_hrdata, - input io_sb_brg_in_hready, - input io_sb_brg_in_hresp, - output [31:0] io_sb_brg_out_haddr, - output [2:0] io_sb_brg_out_hburst, - output io_sb_brg_out_hmastlock, - output [3:0] io_sb_brg_out_hprot, - output [2:0] io_sb_brg_out_hsize, - output [1:0] io_sb_brg_out_htrans, - output io_sb_brg_out_hwrite, - output [63:0] io_sb_brg_out_hwdata, - output [63:0] io_dma_brg_sig_in_hrdata, - output io_dma_brg_sig_in_hready, - output io_dma_brg_sig_in_hresp, - input [31:0] io_dma_brg_sig_out_haddr, - input [2:0] io_dma_brg_sig_out_hburst, - input io_dma_brg_sig_out_hmastlock, - input [3:0] io_dma_brg_sig_out_hprot, - input [2:0] io_dma_brg_sig_out_hsize, - input [1:0] io_dma_brg_sig_out_htrans, - input io_dma_brg_sig_out_hwrite, - input [63:0] io_dma_brg_sig_out_hwdata, - input io_dma_brg_hsel, - input io_dma_brg_hreadyin, + input io_lsu_brg_aw_ready, + output io_lsu_brg_aw_valid, + output [2:0] io_lsu_brg_aw_bits_id, + output [31:0] io_lsu_brg_aw_bits_addr, + output [3:0] io_lsu_brg_aw_bits_region, + output [7:0] io_lsu_brg_aw_bits_len, + output [2:0] io_lsu_brg_aw_bits_size, + output [1:0] io_lsu_brg_aw_bits_burst, + output io_lsu_brg_aw_bits_lock, + output [3:0] io_lsu_brg_aw_bits_cache, + output [2:0] io_lsu_brg_aw_bits_prot, + output [3:0] io_lsu_brg_aw_bits_qos, + input io_lsu_brg_w_ready, + output io_lsu_brg_w_valid, + output [63:0] io_lsu_brg_w_bits_data, + output [7:0] io_lsu_brg_w_bits_strb, + output io_lsu_brg_w_bits_last, + output io_lsu_brg_b_ready, + input io_lsu_brg_b_valid, + input [1:0] io_lsu_brg_b_bits_resp, + input [2:0] io_lsu_brg_b_bits_id, + input io_lsu_brg_ar_ready, + output io_lsu_brg_ar_valid, + output [2:0] io_lsu_brg_ar_bits_id, + output [31:0] io_lsu_brg_ar_bits_addr, + output [3:0] io_lsu_brg_ar_bits_region, + output [7:0] io_lsu_brg_ar_bits_len, + output [2:0] io_lsu_brg_ar_bits_size, + output [1:0] io_lsu_brg_ar_bits_burst, + output io_lsu_brg_ar_bits_lock, + output [3:0] io_lsu_brg_ar_bits_cache, + output [2:0] io_lsu_brg_ar_bits_prot, + output [3:0] io_lsu_brg_ar_bits_qos, + output io_lsu_brg_r_ready, + input io_lsu_brg_r_valid, + input [2:0] io_lsu_brg_r_bits_id, + input [63:0] io_lsu_brg_r_bits_data, + input [1:0] io_lsu_brg_r_bits_resp, + input io_lsu_brg_r_bits_last, + input io_ifu_brg_aw_ready, + output io_ifu_brg_aw_valid, + output [2:0] io_ifu_brg_aw_bits_id, + output [31:0] io_ifu_brg_aw_bits_addr, + output [3:0] io_ifu_brg_aw_bits_region, + output [7:0] io_ifu_brg_aw_bits_len, + output [2:0] io_ifu_brg_aw_bits_size, + output [1:0] io_ifu_brg_aw_bits_burst, + output io_ifu_brg_aw_bits_lock, + output [3:0] io_ifu_brg_aw_bits_cache, + output [2:0] io_ifu_brg_aw_bits_prot, + output [3:0] io_ifu_brg_aw_bits_qos, + input io_ifu_brg_w_ready, + output io_ifu_brg_w_valid, + output [63:0] io_ifu_brg_w_bits_data, + output [7:0] io_ifu_brg_w_bits_strb, + output io_ifu_brg_w_bits_last, + output io_ifu_brg_b_ready, + input io_ifu_brg_b_valid, + input [1:0] io_ifu_brg_b_bits_resp, + input [2:0] io_ifu_brg_b_bits_id, + input io_ifu_brg_ar_ready, + output io_ifu_brg_ar_valid, + output [2:0] io_ifu_brg_ar_bits_id, + output [31:0] io_ifu_brg_ar_bits_addr, + output [3:0] io_ifu_brg_ar_bits_region, + output [7:0] io_ifu_brg_ar_bits_len, + output [2:0] io_ifu_brg_ar_bits_size, + output [1:0] io_ifu_brg_ar_bits_burst, + output io_ifu_brg_ar_bits_lock, + output [3:0] io_ifu_brg_ar_bits_cache, + output [2:0] io_ifu_brg_ar_bits_prot, + output [3:0] io_ifu_brg_ar_bits_qos, + output io_ifu_brg_r_ready, + input io_ifu_brg_r_valid, + input [2:0] io_ifu_brg_r_bits_id, + input [63:0] io_ifu_brg_r_bits_data, + input [1:0] io_ifu_brg_r_bits_resp, + input io_ifu_brg_r_bits_last, + input io_sb_brg_aw_ready, + output io_sb_brg_aw_valid, + output io_sb_brg_aw_bits_id, + output [31:0] io_sb_brg_aw_bits_addr, + output [3:0] io_sb_brg_aw_bits_region, + output [7:0] io_sb_brg_aw_bits_len, + output [2:0] io_sb_brg_aw_bits_size, + output [1:0] io_sb_brg_aw_bits_burst, + output io_sb_brg_aw_bits_lock, + output [3:0] io_sb_brg_aw_bits_cache, + output [2:0] io_sb_brg_aw_bits_prot, + output [3:0] io_sb_brg_aw_bits_qos, + input io_sb_brg_w_ready, + output io_sb_brg_w_valid, + output [63:0] io_sb_brg_w_bits_data, + output [7:0] io_sb_brg_w_bits_strb, + output io_sb_brg_w_bits_last, + output io_sb_brg_b_ready, + input io_sb_brg_b_valid, + input [1:0] io_sb_brg_b_bits_resp, + input io_sb_brg_b_bits_id, + input io_sb_brg_ar_ready, + output io_sb_brg_ar_valid, + output io_sb_brg_ar_bits_id, + output [31:0] io_sb_brg_ar_bits_addr, + output [3:0] io_sb_brg_ar_bits_region, + output [7:0] io_sb_brg_ar_bits_len, + output [2:0] io_sb_brg_ar_bits_size, + output [1:0] io_sb_brg_ar_bits_burst, + output io_sb_brg_ar_bits_lock, + output [3:0] io_sb_brg_ar_bits_cache, + output [2:0] io_sb_brg_ar_bits_prot, + output [3:0] io_sb_brg_ar_bits_qos, + output io_sb_brg_r_ready, + input io_sb_brg_r_valid, + input io_sb_brg_r_bits_id, + input [63:0] io_sb_brg_r_bits_data, + input [1:0] io_sb_brg_r_bits_resp, + input io_sb_brg_r_bits_last, + output io_dma_brg_aw_ready, + input io_dma_brg_aw_valid, + input io_dma_brg_aw_bits_id, + input [31:0] io_dma_brg_aw_bits_addr, + input [3:0] io_dma_brg_aw_bits_region, + input [7:0] io_dma_brg_aw_bits_len, + input [2:0] io_dma_brg_aw_bits_size, + input [1:0] io_dma_brg_aw_bits_burst, + input io_dma_brg_aw_bits_lock, + input [3:0] io_dma_brg_aw_bits_cache, + input [2:0] io_dma_brg_aw_bits_prot, + input [3:0] io_dma_brg_aw_bits_qos, + output io_dma_brg_w_ready, + input io_dma_brg_w_valid, + input [63:0] io_dma_brg_w_bits_data, + input [7:0] io_dma_brg_w_bits_strb, + input io_dma_brg_w_bits_last, + input io_dma_brg_b_ready, + output io_dma_brg_b_valid, + output [1:0] io_dma_brg_b_bits_resp, + output io_dma_brg_b_bits_id, + output io_dma_brg_ar_ready, + input io_dma_brg_ar_valid, + input io_dma_brg_ar_bits_id, + input [31:0] io_dma_brg_ar_bits_addr, + input [3:0] io_dma_brg_ar_bits_region, + input [7:0] io_dma_brg_ar_bits_len, + input [2:0] io_dma_brg_ar_bits_size, + input [1:0] io_dma_brg_ar_bits_burst, + input io_dma_brg_ar_bits_lock, + input [3:0] io_dma_brg_ar_bits_cache, + input [2:0] io_dma_brg_ar_bits_prot, + input [3:0] io_dma_brg_ar_bits_qos, + input io_dma_brg_r_ready, + output io_dma_brg_r_valid, + output io_dma_brg_r_bits_id, + output [63:0] io_dma_brg_r_bits_data, + output [1:0] io_dma_brg_r_bits_resp, + output io_dma_brg_r_bits_last, input io_lsu_bus_clk_en, input io_ifu_bus_clk_en, input io_dbg_bus_clk_en, @@ -85534,40 +83098,82 @@ module quasar_wrapper( wire dmi_wrapper_dmi_hard_reset; // @[quasar_wrapper.scala 64:27] wire core_clock; // @[quasar_wrapper.scala 65:20] wire core_reset; // @[quasar_wrapper.scala 65:20] - wire [63:0] core_io_lsu_ahb_in_hrdata; // @[quasar_wrapper.scala 65:20] - wire core_io_lsu_ahb_in_hready; // @[quasar_wrapper.scala 65:20] - wire core_io_lsu_ahb_in_hresp; // @[quasar_wrapper.scala 65:20] - wire [31:0] core_io_lsu_ahb_out_haddr; // @[quasar_wrapper.scala 65:20] - wire [2:0] core_io_lsu_ahb_out_hsize; // @[quasar_wrapper.scala 65:20] - wire [1:0] core_io_lsu_ahb_out_htrans; // @[quasar_wrapper.scala 65:20] - wire core_io_lsu_ahb_out_hwrite; // @[quasar_wrapper.scala 65:20] - wire [63:0] core_io_lsu_ahb_out_hwdata; // @[quasar_wrapper.scala 65:20] - wire [63:0] core_io_ifu_ahb_in_hrdata; // @[quasar_wrapper.scala 65:20] - wire core_io_ifu_ahb_in_hready; // @[quasar_wrapper.scala 65:20] - wire core_io_ifu_ahb_in_hresp; // @[quasar_wrapper.scala 65:20] - wire [31:0] core_io_ifu_ahb_out_haddr; // @[quasar_wrapper.scala 65:20] - wire [2:0] core_io_ifu_ahb_out_hsize; // @[quasar_wrapper.scala 65:20] - wire [1:0] core_io_ifu_ahb_out_htrans; // @[quasar_wrapper.scala 65:20] - wire core_io_ifu_ahb_out_hwrite; // @[quasar_wrapper.scala 65:20] - wire [63:0] core_io_ifu_ahb_out_hwdata; // @[quasar_wrapper.scala 65:20] - wire [63:0] core_io_sb_ahb_in_hrdata; // @[quasar_wrapper.scala 65:20] - wire core_io_sb_ahb_in_hready; // @[quasar_wrapper.scala 65:20] - wire core_io_sb_ahb_in_hresp; // @[quasar_wrapper.scala 65:20] - wire [31:0] core_io_sb_ahb_out_haddr; // @[quasar_wrapper.scala 65:20] - wire [2:0] core_io_sb_ahb_out_hsize; // @[quasar_wrapper.scala 65:20] - wire [1:0] core_io_sb_ahb_out_htrans; // @[quasar_wrapper.scala 65:20] - wire core_io_sb_ahb_out_hwrite; // @[quasar_wrapper.scala 65:20] - wire [63:0] core_io_sb_ahb_out_hwdata; // @[quasar_wrapper.scala 65:20] - wire [63:0] core_io_dma_ahb_sig_in_hrdata; // @[quasar_wrapper.scala 65:20] - wire core_io_dma_ahb_sig_in_hready; // @[quasar_wrapper.scala 65:20] - wire core_io_dma_ahb_sig_in_hresp; // @[quasar_wrapper.scala 65:20] - wire [31:0] core_io_dma_ahb_sig_out_haddr; // @[quasar_wrapper.scala 65:20] - wire [2:0] core_io_dma_ahb_sig_out_hsize; // @[quasar_wrapper.scala 65:20] - wire [1:0] core_io_dma_ahb_sig_out_htrans; // @[quasar_wrapper.scala 65:20] - wire core_io_dma_ahb_sig_out_hwrite; // @[quasar_wrapper.scala 65:20] - wire [63:0] core_io_dma_ahb_sig_out_hwdata; // @[quasar_wrapper.scala 65:20] - wire core_io_dma_ahb_hsel; // @[quasar_wrapper.scala 65:20] - wire core_io_dma_ahb_hreadyin; // @[quasar_wrapper.scala 65:20] + wire core_io_lsu_axi_aw_ready; // @[quasar_wrapper.scala 65:20] + wire core_io_lsu_axi_aw_valid; // @[quasar_wrapper.scala 65:20] + wire [2:0] core_io_lsu_axi_aw_bits_id; // @[quasar_wrapper.scala 65:20] + wire [31:0] core_io_lsu_axi_aw_bits_addr; // @[quasar_wrapper.scala 65:20] + wire [3:0] core_io_lsu_axi_aw_bits_region; // @[quasar_wrapper.scala 65:20] + wire [2:0] core_io_lsu_axi_aw_bits_size; // @[quasar_wrapper.scala 65:20] + wire [3:0] core_io_lsu_axi_aw_bits_cache; // @[quasar_wrapper.scala 65:20] + wire core_io_lsu_axi_w_ready; // @[quasar_wrapper.scala 65:20] + wire core_io_lsu_axi_w_valid; // @[quasar_wrapper.scala 65:20] + wire [63:0] core_io_lsu_axi_w_bits_data; // @[quasar_wrapper.scala 65:20] + wire [7:0] core_io_lsu_axi_w_bits_strb; // @[quasar_wrapper.scala 65:20] + wire core_io_lsu_axi_b_valid; // @[quasar_wrapper.scala 65:20] + wire [1:0] core_io_lsu_axi_b_bits_resp; // @[quasar_wrapper.scala 65:20] + wire [2:0] core_io_lsu_axi_b_bits_id; // @[quasar_wrapper.scala 65:20] + wire core_io_lsu_axi_ar_ready; // @[quasar_wrapper.scala 65:20] + wire core_io_lsu_axi_ar_valid; // @[quasar_wrapper.scala 65:20] + wire [2:0] core_io_lsu_axi_ar_bits_id; // @[quasar_wrapper.scala 65:20] + wire [31:0] core_io_lsu_axi_ar_bits_addr; // @[quasar_wrapper.scala 65:20] + wire [3:0] core_io_lsu_axi_ar_bits_region; // @[quasar_wrapper.scala 65:20] + wire [2:0] core_io_lsu_axi_ar_bits_size; // @[quasar_wrapper.scala 65:20] + wire [3:0] core_io_lsu_axi_ar_bits_cache; // @[quasar_wrapper.scala 65:20] + wire core_io_lsu_axi_r_valid; // @[quasar_wrapper.scala 65:20] + wire [2:0] core_io_lsu_axi_r_bits_id; // @[quasar_wrapper.scala 65:20] + wire [63:0] core_io_lsu_axi_r_bits_data; // @[quasar_wrapper.scala 65:20] + wire [1:0] core_io_lsu_axi_r_bits_resp; // @[quasar_wrapper.scala 65:20] + wire core_io_ifu_axi_ar_ready; // @[quasar_wrapper.scala 65:20] + wire core_io_ifu_axi_ar_valid; // @[quasar_wrapper.scala 65:20] + wire [2:0] core_io_ifu_axi_ar_bits_id; // @[quasar_wrapper.scala 65:20] + wire [31:0] core_io_ifu_axi_ar_bits_addr; // @[quasar_wrapper.scala 65:20] + wire [3:0] core_io_ifu_axi_ar_bits_region; // @[quasar_wrapper.scala 65:20] + wire core_io_ifu_axi_r_valid; // @[quasar_wrapper.scala 65:20] + wire [2:0] core_io_ifu_axi_r_bits_id; // @[quasar_wrapper.scala 65:20] + wire [63:0] core_io_ifu_axi_r_bits_data; // @[quasar_wrapper.scala 65:20] + wire [1:0] core_io_ifu_axi_r_bits_resp; // @[quasar_wrapper.scala 65:20] + wire core_io_sb_axi_aw_ready; // @[quasar_wrapper.scala 65:20] + wire core_io_sb_axi_aw_valid; // @[quasar_wrapper.scala 65:20] + wire [31:0] core_io_sb_axi_aw_bits_addr; // @[quasar_wrapper.scala 65:20] + wire [3:0] core_io_sb_axi_aw_bits_region; // @[quasar_wrapper.scala 65:20] + wire [2:0] core_io_sb_axi_aw_bits_size; // @[quasar_wrapper.scala 65:20] + wire core_io_sb_axi_w_ready; // @[quasar_wrapper.scala 65:20] + wire core_io_sb_axi_w_valid; // @[quasar_wrapper.scala 65:20] + wire [63:0] core_io_sb_axi_w_bits_data; // @[quasar_wrapper.scala 65:20] + wire [7:0] core_io_sb_axi_w_bits_strb; // @[quasar_wrapper.scala 65:20] + wire core_io_sb_axi_b_valid; // @[quasar_wrapper.scala 65:20] + wire [1:0] core_io_sb_axi_b_bits_resp; // @[quasar_wrapper.scala 65:20] + wire core_io_sb_axi_ar_ready; // @[quasar_wrapper.scala 65:20] + wire core_io_sb_axi_ar_valid; // @[quasar_wrapper.scala 65:20] + wire [31:0] core_io_sb_axi_ar_bits_addr; // @[quasar_wrapper.scala 65:20] + wire [3:0] core_io_sb_axi_ar_bits_region; // @[quasar_wrapper.scala 65:20] + wire [2:0] core_io_sb_axi_ar_bits_size; // @[quasar_wrapper.scala 65:20] + wire core_io_sb_axi_r_valid; // @[quasar_wrapper.scala 65:20] + wire [63:0] core_io_sb_axi_r_bits_data; // @[quasar_wrapper.scala 65:20] + wire [1:0] core_io_sb_axi_r_bits_resp; // @[quasar_wrapper.scala 65:20] + wire core_io_dma_axi_aw_ready; // @[quasar_wrapper.scala 65:20] + wire core_io_dma_axi_aw_valid; // @[quasar_wrapper.scala 65:20] + wire core_io_dma_axi_aw_bits_id; // @[quasar_wrapper.scala 65:20] + wire [31:0] core_io_dma_axi_aw_bits_addr; // @[quasar_wrapper.scala 65:20] + wire [2:0] core_io_dma_axi_aw_bits_size; // @[quasar_wrapper.scala 65:20] + wire core_io_dma_axi_w_ready; // @[quasar_wrapper.scala 65:20] + wire core_io_dma_axi_w_valid; // @[quasar_wrapper.scala 65:20] + wire [63:0] core_io_dma_axi_w_bits_data; // @[quasar_wrapper.scala 65:20] + wire [7:0] core_io_dma_axi_w_bits_strb; // @[quasar_wrapper.scala 65:20] + wire core_io_dma_axi_b_ready; // @[quasar_wrapper.scala 65:20] + wire core_io_dma_axi_b_valid; // @[quasar_wrapper.scala 65:20] + wire [1:0] core_io_dma_axi_b_bits_resp; // @[quasar_wrapper.scala 65:20] + wire core_io_dma_axi_b_bits_id; // @[quasar_wrapper.scala 65:20] + wire core_io_dma_axi_ar_ready; // @[quasar_wrapper.scala 65:20] + wire core_io_dma_axi_ar_valid; // @[quasar_wrapper.scala 65:20] + wire core_io_dma_axi_ar_bits_id; // @[quasar_wrapper.scala 65:20] + wire [31:0] core_io_dma_axi_ar_bits_addr; // @[quasar_wrapper.scala 65:20] + wire [2:0] core_io_dma_axi_ar_bits_size; // @[quasar_wrapper.scala 65:20] + wire core_io_dma_axi_r_ready; // @[quasar_wrapper.scala 65:20] + wire core_io_dma_axi_r_valid; // @[quasar_wrapper.scala 65:20] + wire core_io_dma_axi_r_bits_id; // @[quasar_wrapper.scala 65:20] + wire [63:0] core_io_dma_axi_r_bits_data; // @[quasar_wrapper.scala 65:20] + wire [1:0] core_io_dma_axi_r_bits_resp; // @[quasar_wrapper.scala 65:20] wire core_io_dbg_rst_l; // @[quasar_wrapper.scala 65:20] wire [30:0] core_io_rst_vec; // @[quasar_wrapper.scala 65:20] wire core_io_nmi_int; // @[quasar_wrapper.scala 65:20] @@ -85720,40 +83326,82 @@ module quasar_wrapper( quasar core ( // @[quasar_wrapper.scala 65:20] .clock(core_clock), .reset(core_reset), - .io_lsu_ahb_in_hrdata(core_io_lsu_ahb_in_hrdata), - .io_lsu_ahb_in_hready(core_io_lsu_ahb_in_hready), - .io_lsu_ahb_in_hresp(core_io_lsu_ahb_in_hresp), - .io_lsu_ahb_out_haddr(core_io_lsu_ahb_out_haddr), - .io_lsu_ahb_out_hsize(core_io_lsu_ahb_out_hsize), - .io_lsu_ahb_out_htrans(core_io_lsu_ahb_out_htrans), - .io_lsu_ahb_out_hwrite(core_io_lsu_ahb_out_hwrite), - .io_lsu_ahb_out_hwdata(core_io_lsu_ahb_out_hwdata), - .io_ifu_ahb_in_hrdata(core_io_ifu_ahb_in_hrdata), - .io_ifu_ahb_in_hready(core_io_ifu_ahb_in_hready), - .io_ifu_ahb_in_hresp(core_io_ifu_ahb_in_hresp), - .io_ifu_ahb_out_haddr(core_io_ifu_ahb_out_haddr), - .io_ifu_ahb_out_hsize(core_io_ifu_ahb_out_hsize), - .io_ifu_ahb_out_htrans(core_io_ifu_ahb_out_htrans), - .io_ifu_ahb_out_hwrite(core_io_ifu_ahb_out_hwrite), - .io_ifu_ahb_out_hwdata(core_io_ifu_ahb_out_hwdata), - .io_sb_ahb_in_hrdata(core_io_sb_ahb_in_hrdata), - .io_sb_ahb_in_hready(core_io_sb_ahb_in_hready), - .io_sb_ahb_in_hresp(core_io_sb_ahb_in_hresp), - .io_sb_ahb_out_haddr(core_io_sb_ahb_out_haddr), - .io_sb_ahb_out_hsize(core_io_sb_ahb_out_hsize), - .io_sb_ahb_out_htrans(core_io_sb_ahb_out_htrans), - .io_sb_ahb_out_hwrite(core_io_sb_ahb_out_hwrite), - .io_sb_ahb_out_hwdata(core_io_sb_ahb_out_hwdata), - .io_dma_ahb_sig_in_hrdata(core_io_dma_ahb_sig_in_hrdata), - .io_dma_ahb_sig_in_hready(core_io_dma_ahb_sig_in_hready), - .io_dma_ahb_sig_in_hresp(core_io_dma_ahb_sig_in_hresp), - .io_dma_ahb_sig_out_haddr(core_io_dma_ahb_sig_out_haddr), - .io_dma_ahb_sig_out_hsize(core_io_dma_ahb_sig_out_hsize), - .io_dma_ahb_sig_out_htrans(core_io_dma_ahb_sig_out_htrans), - .io_dma_ahb_sig_out_hwrite(core_io_dma_ahb_sig_out_hwrite), - .io_dma_ahb_sig_out_hwdata(core_io_dma_ahb_sig_out_hwdata), - .io_dma_ahb_hsel(core_io_dma_ahb_hsel), - .io_dma_ahb_hreadyin(core_io_dma_ahb_hreadyin), + .io_lsu_axi_aw_ready(core_io_lsu_axi_aw_ready), + .io_lsu_axi_aw_valid(core_io_lsu_axi_aw_valid), + .io_lsu_axi_aw_bits_id(core_io_lsu_axi_aw_bits_id), + .io_lsu_axi_aw_bits_addr(core_io_lsu_axi_aw_bits_addr), + .io_lsu_axi_aw_bits_region(core_io_lsu_axi_aw_bits_region), + .io_lsu_axi_aw_bits_size(core_io_lsu_axi_aw_bits_size), + .io_lsu_axi_aw_bits_cache(core_io_lsu_axi_aw_bits_cache), + .io_lsu_axi_w_ready(core_io_lsu_axi_w_ready), + .io_lsu_axi_w_valid(core_io_lsu_axi_w_valid), + .io_lsu_axi_w_bits_data(core_io_lsu_axi_w_bits_data), + .io_lsu_axi_w_bits_strb(core_io_lsu_axi_w_bits_strb), + .io_lsu_axi_b_valid(core_io_lsu_axi_b_valid), + .io_lsu_axi_b_bits_resp(core_io_lsu_axi_b_bits_resp), + .io_lsu_axi_b_bits_id(core_io_lsu_axi_b_bits_id), + .io_lsu_axi_ar_ready(core_io_lsu_axi_ar_ready), + .io_lsu_axi_ar_valid(core_io_lsu_axi_ar_valid), + .io_lsu_axi_ar_bits_id(core_io_lsu_axi_ar_bits_id), + .io_lsu_axi_ar_bits_addr(core_io_lsu_axi_ar_bits_addr), + .io_lsu_axi_ar_bits_region(core_io_lsu_axi_ar_bits_region), + .io_lsu_axi_ar_bits_size(core_io_lsu_axi_ar_bits_size), + .io_lsu_axi_ar_bits_cache(core_io_lsu_axi_ar_bits_cache), + .io_lsu_axi_r_valid(core_io_lsu_axi_r_valid), + .io_lsu_axi_r_bits_id(core_io_lsu_axi_r_bits_id), + .io_lsu_axi_r_bits_data(core_io_lsu_axi_r_bits_data), + .io_lsu_axi_r_bits_resp(core_io_lsu_axi_r_bits_resp), + .io_ifu_axi_ar_ready(core_io_ifu_axi_ar_ready), + .io_ifu_axi_ar_valid(core_io_ifu_axi_ar_valid), + .io_ifu_axi_ar_bits_id(core_io_ifu_axi_ar_bits_id), + .io_ifu_axi_ar_bits_addr(core_io_ifu_axi_ar_bits_addr), + .io_ifu_axi_ar_bits_region(core_io_ifu_axi_ar_bits_region), + .io_ifu_axi_r_valid(core_io_ifu_axi_r_valid), + .io_ifu_axi_r_bits_id(core_io_ifu_axi_r_bits_id), + .io_ifu_axi_r_bits_data(core_io_ifu_axi_r_bits_data), + .io_ifu_axi_r_bits_resp(core_io_ifu_axi_r_bits_resp), + .io_sb_axi_aw_ready(core_io_sb_axi_aw_ready), + .io_sb_axi_aw_valid(core_io_sb_axi_aw_valid), + .io_sb_axi_aw_bits_addr(core_io_sb_axi_aw_bits_addr), + .io_sb_axi_aw_bits_region(core_io_sb_axi_aw_bits_region), + .io_sb_axi_aw_bits_size(core_io_sb_axi_aw_bits_size), + .io_sb_axi_w_ready(core_io_sb_axi_w_ready), + .io_sb_axi_w_valid(core_io_sb_axi_w_valid), + .io_sb_axi_w_bits_data(core_io_sb_axi_w_bits_data), + .io_sb_axi_w_bits_strb(core_io_sb_axi_w_bits_strb), + .io_sb_axi_b_valid(core_io_sb_axi_b_valid), + .io_sb_axi_b_bits_resp(core_io_sb_axi_b_bits_resp), + .io_sb_axi_ar_ready(core_io_sb_axi_ar_ready), + .io_sb_axi_ar_valid(core_io_sb_axi_ar_valid), + .io_sb_axi_ar_bits_addr(core_io_sb_axi_ar_bits_addr), + .io_sb_axi_ar_bits_region(core_io_sb_axi_ar_bits_region), + .io_sb_axi_ar_bits_size(core_io_sb_axi_ar_bits_size), + .io_sb_axi_r_valid(core_io_sb_axi_r_valid), + .io_sb_axi_r_bits_data(core_io_sb_axi_r_bits_data), + .io_sb_axi_r_bits_resp(core_io_sb_axi_r_bits_resp), + .io_dma_axi_aw_ready(core_io_dma_axi_aw_ready), + .io_dma_axi_aw_valid(core_io_dma_axi_aw_valid), + .io_dma_axi_aw_bits_id(core_io_dma_axi_aw_bits_id), + .io_dma_axi_aw_bits_addr(core_io_dma_axi_aw_bits_addr), + .io_dma_axi_aw_bits_size(core_io_dma_axi_aw_bits_size), + .io_dma_axi_w_ready(core_io_dma_axi_w_ready), + .io_dma_axi_w_valid(core_io_dma_axi_w_valid), + .io_dma_axi_w_bits_data(core_io_dma_axi_w_bits_data), + .io_dma_axi_w_bits_strb(core_io_dma_axi_w_bits_strb), + .io_dma_axi_b_ready(core_io_dma_axi_b_ready), + .io_dma_axi_b_valid(core_io_dma_axi_b_valid), + .io_dma_axi_b_bits_resp(core_io_dma_axi_b_bits_resp), + .io_dma_axi_b_bits_id(core_io_dma_axi_b_bits_id), + .io_dma_axi_ar_ready(core_io_dma_axi_ar_ready), + .io_dma_axi_ar_valid(core_io_dma_axi_ar_valid), + .io_dma_axi_ar_bits_id(core_io_dma_axi_ar_bits_id), + .io_dma_axi_ar_bits_addr(core_io_dma_axi_ar_bits_addr), + .io_dma_axi_ar_bits_size(core_io_dma_axi_ar_bits_size), + .io_dma_axi_r_ready(core_io_dma_axi_r_ready), + .io_dma_axi_r_valid(core_io_dma_axi_r_valid), + .io_dma_axi_r_bits_id(core_io_dma_axi_r_bits_id), + .io_dma_axi_r_bits_data(core_io_dma_axi_r_bits_data), + .io_dma_axi_r_bits_resp(core_io_dma_axi_r_bits_resp), .io_dbg_rst_l(core_io_dbg_rst_l), .io_rst_vec(core_io_rst_vec), .io_nmi_int(core_io_nmi_int), @@ -85839,33 +83487,101 @@ module quasar_wrapper( .io_soft_int(core_io_soft_int), .io_scan_mode(core_io_scan_mode) ); - assign io_lsu_brg_out_haddr = core_io_lsu_ahb_out_haddr; // @[quasar_wrapper.scala 109:21] - assign io_lsu_brg_out_hburst = 3'h0; // @[quasar_wrapper.scala 109:21] - assign io_lsu_brg_out_hmastlock = 1'h0; // @[quasar_wrapper.scala 109:21] - assign io_lsu_brg_out_hprot = 4'h3; // @[quasar_wrapper.scala 109:21] - assign io_lsu_brg_out_hsize = core_io_lsu_ahb_out_hsize; // @[quasar_wrapper.scala 109:21] - assign io_lsu_brg_out_htrans = core_io_lsu_ahb_out_htrans; // @[quasar_wrapper.scala 109:21] - assign io_lsu_brg_out_hwrite = core_io_lsu_ahb_out_hwrite; // @[quasar_wrapper.scala 109:21] - assign io_lsu_brg_out_hwdata = core_io_lsu_ahb_out_hwdata; // @[quasar_wrapper.scala 109:21] - assign io_ifu_brg_out_haddr = core_io_ifu_ahb_out_haddr; // @[quasar_wrapper.scala 108:21] - assign io_ifu_brg_out_hburst = 3'h0; // @[quasar_wrapper.scala 108:21] - assign io_ifu_brg_out_hmastlock = 1'h0; // @[quasar_wrapper.scala 108:21] - assign io_ifu_brg_out_hprot = 4'h3; // @[quasar_wrapper.scala 108:21] - assign io_ifu_brg_out_hsize = core_io_ifu_ahb_out_hsize; // @[quasar_wrapper.scala 108:21] - assign io_ifu_brg_out_htrans = core_io_ifu_ahb_out_htrans; // @[quasar_wrapper.scala 108:21] - assign io_ifu_brg_out_hwrite = core_io_ifu_ahb_out_hwrite; // @[quasar_wrapper.scala 108:21] - assign io_ifu_brg_out_hwdata = core_io_ifu_ahb_out_hwdata; // @[quasar_wrapper.scala 108:21] - assign io_sb_brg_out_haddr = core_io_sb_ahb_out_haddr; // @[quasar_wrapper.scala 110:20] - assign io_sb_brg_out_hburst = 3'h0; // @[quasar_wrapper.scala 110:20] - assign io_sb_brg_out_hmastlock = 1'h0; // @[quasar_wrapper.scala 110:20] - assign io_sb_brg_out_hprot = 4'h3; // @[quasar_wrapper.scala 110:20] - assign io_sb_brg_out_hsize = core_io_sb_ahb_out_hsize; // @[quasar_wrapper.scala 110:20] - assign io_sb_brg_out_htrans = core_io_sb_ahb_out_htrans; // @[quasar_wrapper.scala 110:20] - assign io_sb_brg_out_hwrite = core_io_sb_ahb_out_hwrite; // @[quasar_wrapper.scala 110:20] - assign io_sb_brg_out_hwdata = core_io_sb_ahb_out_hwdata; // @[quasar_wrapper.scala 110:20] - assign io_dma_brg_sig_in_hrdata = core_io_dma_ahb_sig_in_hrdata; // @[quasar_wrapper.scala 111:21] - assign io_dma_brg_sig_in_hready = core_io_dma_ahb_sig_in_hready; // @[quasar_wrapper.scala 111:21] - assign io_dma_brg_sig_in_hresp = core_io_dma_ahb_sig_in_hresp; // @[quasar_wrapper.scala 111:21] + assign io_lsu_brg_aw_valid = core_io_lsu_axi_aw_valid; // @[quasar_wrapper.scala 102:21] + assign io_lsu_brg_aw_bits_id = core_io_lsu_axi_aw_bits_id; // @[quasar_wrapper.scala 102:21] + assign io_lsu_brg_aw_bits_addr = core_io_lsu_axi_aw_bits_addr; // @[quasar_wrapper.scala 102:21] + assign io_lsu_brg_aw_bits_region = core_io_lsu_axi_aw_bits_region; // @[quasar_wrapper.scala 102:21] + assign io_lsu_brg_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 102:21] + assign io_lsu_brg_aw_bits_size = core_io_lsu_axi_aw_bits_size; // @[quasar_wrapper.scala 102:21] + assign io_lsu_brg_aw_bits_burst = 2'h1; // @[quasar_wrapper.scala 102:21] + assign io_lsu_brg_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 102:21] + assign io_lsu_brg_aw_bits_cache = core_io_lsu_axi_aw_bits_cache; // @[quasar_wrapper.scala 102:21] + assign io_lsu_brg_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 102:21] + assign io_lsu_brg_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 102:21] + assign io_lsu_brg_w_valid = core_io_lsu_axi_w_valid; // @[quasar_wrapper.scala 102:21] + assign io_lsu_brg_w_bits_data = core_io_lsu_axi_w_bits_data; // @[quasar_wrapper.scala 102:21] + assign io_lsu_brg_w_bits_strb = core_io_lsu_axi_w_bits_strb; // @[quasar_wrapper.scala 102:21] + assign io_lsu_brg_w_bits_last = 1'h1; // @[quasar_wrapper.scala 102:21] + assign io_lsu_brg_b_ready = 1'h1; // @[quasar_wrapper.scala 102:21] + assign io_lsu_brg_ar_valid = core_io_lsu_axi_ar_valid; // @[quasar_wrapper.scala 102:21] + assign io_lsu_brg_ar_bits_id = core_io_lsu_axi_ar_bits_id; // @[quasar_wrapper.scala 102:21] + assign io_lsu_brg_ar_bits_addr = core_io_lsu_axi_ar_bits_addr; // @[quasar_wrapper.scala 102:21] + assign io_lsu_brg_ar_bits_region = core_io_lsu_axi_ar_bits_region; // @[quasar_wrapper.scala 102:21] + assign io_lsu_brg_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 102:21] + assign io_lsu_brg_ar_bits_size = core_io_lsu_axi_ar_bits_size; // @[quasar_wrapper.scala 102:21] + assign io_lsu_brg_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 102:21] + assign io_lsu_brg_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 102:21] + assign io_lsu_brg_ar_bits_cache = core_io_lsu_axi_ar_bits_cache; // @[quasar_wrapper.scala 102:21] + assign io_lsu_brg_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 102:21] + assign io_lsu_brg_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 102:21] + assign io_lsu_brg_r_ready = 1'h1; // @[quasar_wrapper.scala 102:21] + assign io_ifu_brg_aw_valid = 1'h0; // @[quasar_wrapper.scala 103:21] + assign io_ifu_brg_aw_bits_id = 3'h0; // @[quasar_wrapper.scala 103:21] + assign io_ifu_brg_aw_bits_addr = 32'h0; // @[quasar_wrapper.scala 103:21] + assign io_ifu_brg_aw_bits_region = 4'h0; // @[quasar_wrapper.scala 103:21] + assign io_ifu_brg_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 103:21] + assign io_ifu_brg_aw_bits_size = 3'h0; // @[quasar_wrapper.scala 103:21] + assign io_ifu_brg_aw_bits_burst = 2'h0; // @[quasar_wrapper.scala 103:21] + assign io_ifu_brg_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 103:21] + assign io_ifu_brg_aw_bits_cache = 4'h0; // @[quasar_wrapper.scala 103:21] + assign io_ifu_brg_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 103:21] + assign io_ifu_brg_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 103:21] + assign io_ifu_brg_w_valid = 1'h0; // @[quasar_wrapper.scala 103:21] + assign io_ifu_brg_w_bits_data = 64'h0; // @[quasar_wrapper.scala 103:21] + assign io_ifu_brg_w_bits_strb = 8'h0; // @[quasar_wrapper.scala 103:21] + assign io_ifu_brg_w_bits_last = 1'h0; // @[quasar_wrapper.scala 103:21] + assign io_ifu_brg_b_ready = 1'h0; // @[quasar_wrapper.scala 103:21] + assign io_ifu_brg_ar_valid = core_io_ifu_axi_ar_valid; // @[quasar_wrapper.scala 103:21] + assign io_ifu_brg_ar_bits_id = core_io_ifu_axi_ar_bits_id; // @[quasar_wrapper.scala 103:21] + assign io_ifu_brg_ar_bits_addr = core_io_ifu_axi_ar_bits_addr; // @[quasar_wrapper.scala 103:21] + assign io_ifu_brg_ar_bits_region = core_io_ifu_axi_ar_bits_region; // @[quasar_wrapper.scala 103:21] + assign io_ifu_brg_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 103:21] + assign io_ifu_brg_ar_bits_size = 3'h3; // @[quasar_wrapper.scala 103:21] + assign io_ifu_brg_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 103:21] + assign io_ifu_brg_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 103:21] + assign io_ifu_brg_ar_bits_cache = 4'hf; // @[quasar_wrapper.scala 103:21] + assign io_ifu_brg_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 103:21] + assign io_ifu_brg_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 103:21] + assign io_ifu_brg_r_ready = 1'h1; // @[quasar_wrapper.scala 103:21] + assign io_sb_brg_aw_valid = core_io_sb_axi_aw_valid; // @[quasar_wrapper.scala 104:21] + assign io_sb_brg_aw_bits_id = 1'h0; // @[quasar_wrapper.scala 104:21] + assign io_sb_brg_aw_bits_addr = core_io_sb_axi_aw_bits_addr; // @[quasar_wrapper.scala 104:21] + assign io_sb_brg_aw_bits_region = core_io_sb_axi_aw_bits_region; // @[quasar_wrapper.scala 104:21] + assign io_sb_brg_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 104:21] + assign io_sb_brg_aw_bits_size = core_io_sb_axi_aw_bits_size; // @[quasar_wrapper.scala 104:21] + assign io_sb_brg_aw_bits_burst = 2'h1; // @[quasar_wrapper.scala 104:21] + assign io_sb_brg_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 104:21] + assign io_sb_brg_aw_bits_cache = 4'hf; // @[quasar_wrapper.scala 104:21] + assign io_sb_brg_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 104:21] + assign io_sb_brg_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 104:21] + assign io_sb_brg_w_valid = core_io_sb_axi_w_valid; // @[quasar_wrapper.scala 104:21] + assign io_sb_brg_w_bits_data = core_io_sb_axi_w_bits_data; // @[quasar_wrapper.scala 104:21] + assign io_sb_brg_w_bits_strb = core_io_sb_axi_w_bits_strb; // @[quasar_wrapper.scala 104:21] + assign io_sb_brg_w_bits_last = 1'h1; // @[quasar_wrapper.scala 104:21] + assign io_sb_brg_b_ready = 1'h1; // @[quasar_wrapper.scala 104:21] + assign io_sb_brg_ar_valid = core_io_sb_axi_ar_valid; // @[quasar_wrapper.scala 104:21] + assign io_sb_brg_ar_bits_id = 1'h0; // @[quasar_wrapper.scala 104:21] + assign io_sb_brg_ar_bits_addr = core_io_sb_axi_ar_bits_addr; // @[quasar_wrapper.scala 104:21] + assign io_sb_brg_ar_bits_region = core_io_sb_axi_ar_bits_region; // @[quasar_wrapper.scala 104:21] + assign io_sb_brg_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 104:21] + assign io_sb_brg_ar_bits_size = core_io_sb_axi_ar_bits_size; // @[quasar_wrapper.scala 104:21] + assign io_sb_brg_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 104:21] + assign io_sb_brg_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 104:21] + assign io_sb_brg_ar_bits_cache = 4'h0; // @[quasar_wrapper.scala 104:21] + assign io_sb_brg_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 104:21] + assign io_sb_brg_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 104:21] + assign io_sb_brg_r_ready = 1'h1; // @[quasar_wrapper.scala 104:21] + assign io_dma_brg_aw_ready = core_io_dma_axi_aw_ready; // @[quasar_wrapper.scala 105:21] + assign io_dma_brg_w_ready = core_io_dma_axi_w_ready; // @[quasar_wrapper.scala 105:21] + assign io_dma_brg_b_valid = core_io_dma_axi_b_valid; // @[quasar_wrapper.scala 105:21] + assign io_dma_brg_b_bits_resp = core_io_dma_axi_b_bits_resp; // @[quasar_wrapper.scala 105:21] + assign io_dma_brg_b_bits_id = core_io_dma_axi_b_bits_id; // @[quasar_wrapper.scala 105:21] + assign io_dma_brg_ar_ready = core_io_dma_axi_ar_ready; // @[quasar_wrapper.scala 105:21] + assign io_dma_brg_r_valid = core_io_dma_axi_r_valid; // @[quasar_wrapper.scala 105:21] + assign io_dma_brg_r_bits_id = core_io_dma_axi_r_bits_id; // @[quasar_wrapper.scala 105:21] + assign io_dma_brg_r_bits_data = core_io_dma_axi_r_bits_data; // @[quasar_wrapper.scala 105:21] + assign io_dma_brg_r_bits_resp = core_io_dma_axi_r_bits_resp; // @[quasar_wrapper.scala 105:21] + assign io_dma_brg_r_bits_last = 1'h1; // @[quasar_wrapper.scala 105:21] assign io_dec_tlu_perfcnt0 = core_io_dec_tlu_perfcnt0; // @[quasar_wrapper.scala 157:23] assign io_dec_tlu_perfcnt1 = core_io_dec_tlu_perfcnt1; // @[quasar_wrapper.scala 158:23] assign io_dec_tlu_perfcnt2 = core_io_dec_tlu_perfcnt2; // @[quasar_wrapper.scala 159:23] @@ -85930,22 +83646,42 @@ module quasar_wrapper( assign dmi_wrapper_rd_data = core_io_dmi_reg_rdata; // @[quasar_wrapper.scala 73:26] assign core_clock = clock; assign core_reset = reset; - assign core_io_lsu_ahb_in_hrdata = io_lsu_brg_in_hrdata; // @[quasar_wrapper.scala 109:21] - assign core_io_lsu_ahb_in_hready = io_lsu_brg_in_hready; // @[quasar_wrapper.scala 109:21] - assign core_io_lsu_ahb_in_hresp = io_lsu_brg_in_hresp; // @[quasar_wrapper.scala 109:21] - assign core_io_ifu_ahb_in_hrdata = io_ifu_brg_in_hrdata; // @[quasar_wrapper.scala 108:21] - assign core_io_ifu_ahb_in_hready = io_ifu_brg_in_hready; // @[quasar_wrapper.scala 108:21] - assign core_io_ifu_ahb_in_hresp = io_ifu_brg_in_hresp; // @[quasar_wrapper.scala 108:21] - assign core_io_sb_ahb_in_hrdata = io_sb_brg_in_hrdata; // @[quasar_wrapper.scala 110:20] - assign core_io_sb_ahb_in_hready = io_sb_brg_in_hready; // @[quasar_wrapper.scala 110:20] - assign core_io_sb_ahb_in_hresp = io_sb_brg_in_hresp; // @[quasar_wrapper.scala 110:20] - assign core_io_dma_ahb_sig_out_haddr = io_dma_brg_sig_out_haddr; // @[quasar_wrapper.scala 111:21] - assign core_io_dma_ahb_sig_out_hsize = io_dma_brg_sig_out_hsize; // @[quasar_wrapper.scala 111:21] - assign core_io_dma_ahb_sig_out_htrans = io_dma_brg_sig_out_htrans; // @[quasar_wrapper.scala 111:21] - assign core_io_dma_ahb_sig_out_hwrite = io_dma_brg_sig_out_hwrite; // @[quasar_wrapper.scala 111:21] - assign core_io_dma_ahb_sig_out_hwdata = io_dma_brg_sig_out_hwdata; // @[quasar_wrapper.scala 111:21] - assign core_io_dma_ahb_hsel = io_dma_brg_hsel; // @[quasar_wrapper.scala 111:21] - assign core_io_dma_ahb_hreadyin = io_dma_brg_hreadyin; // @[quasar_wrapper.scala 111:21] + assign core_io_lsu_axi_aw_ready = io_lsu_brg_aw_ready; // @[quasar_wrapper.scala 102:21] + assign core_io_lsu_axi_w_ready = io_lsu_brg_w_ready; // @[quasar_wrapper.scala 102:21] + assign core_io_lsu_axi_b_valid = io_lsu_brg_b_valid; // @[quasar_wrapper.scala 102:21] + assign core_io_lsu_axi_b_bits_resp = io_lsu_brg_b_bits_resp; // @[quasar_wrapper.scala 102:21] + assign core_io_lsu_axi_b_bits_id = io_lsu_brg_b_bits_id; // @[quasar_wrapper.scala 102:21] + assign core_io_lsu_axi_ar_ready = io_lsu_brg_ar_ready; // @[quasar_wrapper.scala 102:21] + assign core_io_lsu_axi_r_valid = io_lsu_brg_r_valid; // @[quasar_wrapper.scala 102:21] + assign core_io_lsu_axi_r_bits_id = io_lsu_brg_r_bits_id; // @[quasar_wrapper.scala 102:21] + assign core_io_lsu_axi_r_bits_data = io_lsu_brg_r_bits_data; // @[quasar_wrapper.scala 102:21] + assign core_io_lsu_axi_r_bits_resp = io_lsu_brg_r_bits_resp; // @[quasar_wrapper.scala 102:21] + assign core_io_ifu_axi_ar_ready = io_ifu_brg_ar_ready; // @[quasar_wrapper.scala 103:21] + assign core_io_ifu_axi_r_valid = io_ifu_brg_r_valid; // @[quasar_wrapper.scala 103:21] + assign core_io_ifu_axi_r_bits_id = io_ifu_brg_r_bits_id; // @[quasar_wrapper.scala 103:21] + assign core_io_ifu_axi_r_bits_data = io_ifu_brg_r_bits_data; // @[quasar_wrapper.scala 103:21] + assign core_io_ifu_axi_r_bits_resp = io_ifu_brg_r_bits_resp; // @[quasar_wrapper.scala 103:21] + assign core_io_sb_axi_aw_ready = io_sb_brg_aw_ready; // @[quasar_wrapper.scala 104:21] + assign core_io_sb_axi_w_ready = io_sb_brg_w_ready; // @[quasar_wrapper.scala 104:21] + assign core_io_sb_axi_b_valid = io_sb_brg_b_valid; // @[quasar_wrapper.scala 104:21] + assign core_io_sb_axi_b_bits_resp = io_sb_brg_b_bits_resp; // @[quasar_wrapper.scala 104:21] + assign core_io_sb_axi_ar_ready = io_sb_brg_ar_ready; // @[quasar_wrapper.scala 104:21] + assign core_io_sb_axi_r_valid = io_sb_brg_r_valid; // @[quasar_wrapper.scala 104:21] + assign core_io_sb_axi_r_bits_data = io_sb_brg_r_bits_data; // @[quasar_wrapper.scala 104:21] + assign core_io_sb_axi_r_bits_resp = io_sb_brg_r_bits_resp; // @[quasar_wrapper.scala 104:21] + assign core_io_dma_axi_aw_valid = io_dma_brg_aw_valid; // @[quasar_wrapper.scala 105:21] + assign core_io_dma_axi_aw_bits_id = io_dma_brg_aw_bits_id; // @[quasar_wrapper.scala 105:21] + assign core_io_dma_axi_aw_bits_addr = io_dma_brg_aw_bits_addr; // @[quasar_wrapper.scala 105:21] + assign core_io_dma_axi_aw_bits_size = io_dma_brg_aw_bits_size; // @[quasar_wrapper.scala 105:21] + assign core_io_dma_axi_w_valid = io_dma_brg_w_valid; // @[quasar_wrapper.scala 105:21] + assign core_io_dma_axi_w_bits_data = io_dma_brg_w_bits_data; // @[quasar_wrapper.scala 105:21] + assign core_io_dma_axi_w_bits_strb = io_dma_brg_w_bits_strb; // @[quasar_wrapper.scala 105:21] + assign core_io_dma_axi_b_ready = io_dma_brg_b_ready; // @[quasar_wrapper.scala 105:21] + assign core_io_dma_axi_ar_valid = io_dma_brg_ar_valid; // @[quasar_wrapper.scala 105:21] + assign core_io_dma_axi_ar_bits_id = io_dma_brg_ar_bits_id; // @[quasar_wrapper.scala 105:21] + assign core_io_dma_axi_ar_bits_addr = io_dma_brg_ar_bits_addr; // @[quasar_wrapper.scala 105:21] + assign core_io_dma_axi_ar_bits_size = io_dma_brg_ar_bits_size; // @[quasar_wrapper.scala 105:21] + assign core_io_dma_axi_r_ready = io_dma_brg_r_ready; // @[quasar_wrapper.scala 105:21] assign core_io_dbg_rst_l = io_dbg_rst_l; // @[quasar_wrapper.scala 91:21 quasar_wrapper.scala 119:21] assign core_io_rst_vec = io_rst_vec; // @[quasar_wrapper.scala 120:19] assign core_io_nmi_int = io_nmi_int; // @[quasar_wrapper.scala 121:19] diff --git a/src/main/scala/lib/param.scala b/src/main/scala/lib/param.scala index e9af12d3..0917162d 100644 --- a/src/main/scala/lib/param.scala +++ b/src/main/scala/lib/param.scala @@ -21,8 +21,8 @@ trait param { val BTB_INDEX3_HI = 0x19 val BTB_INDEX3_LO = 0x12 val BTB_SIZE = 0x200 - val BUILD_AHB_LITE = 0x1 - val BUILD_AXI4 = 0x0 + val BUILD_AHB_LITE = 0x0 + val BUILD_AXI4 = 0x1 val BUILD_AXI_NATIVE = 0x1 val BUS_PRTY_DEFAULT = 0x3 val DATA_ACCESS_ADDR0 = 0x00000000 diff --git a/target/scala-2.12/classes/QUASAR$.class b/target/scala-2.12/classes/QUASAR$.class new file mode 100644 index 0000000000000000000000000000000000000000..02057f0a141c74cfaa9f0c8adbc23d7c5fb236e2 GIT binary patch literal 3815 zcmbtX33n4!7`?AcLPMaXr9h!dfgm9)0SXpLMY@0#Q?}45qT*}vS_Y;wVKRXh6>$Ui z4fo|Ic#aF(fph!;{wR<4%}kmpjhJ(6PiJ}at@nN3{a*k2`~IH*cH?J(=!vm`+`!31 z6hffwyu2jSrnIKg$0p9Jyc#+dgS^8p+jZMGqt0#;FK-bm{#dQdqx$;=sdHZzXFT;^QMkv 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