diff --git a/axi4_to_ahb.anno.json b/axi4_to_ahb.anno.json new file mode 100644 index 00000000..0e21bc50 --- /dev/null +++ b/axi4_to_ahb.anno.json @@ -0,0 +1,113 @@ +[ + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_bvalid", + "sources":[ + "~axi4_to_ahb|axi4_to_ahb>io_axi_bready", + "~axi4_to_ahb|axi4_to_ahb>io_axi_rready", + "~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_htrans", + "sources":[ + "~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid", + "~axi4_to_ahb|axi4_to_ahb>io_axi_bready", + "~axi4_to_ahb|axi4_to_ahb>io_axi_rready" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_wready", + "sources":[ + "~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid", + "~axi4_to_ahb|axi4_to_ahb>io_axi_bready", + "~axi4_to_ahb|axi4_to_ahb>io_axi_rready" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_hwrite", + "sources":[ + "~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid", + "~axi4_to_ahb|axi4_to_ahb>io_axi_bready", + "~axi4_to_ahb|axi4_to_ahb>io_axi_rready" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_haddr", + "sources":[ + "~axi4_to_ahb|axi4_to_ahb>io_axi_araddr", + "~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid", + "~axi4_to_ahb|axi4_to_ahb>io_axi_bready", + "~axi4_to_ahb|axi4_to_ahb>io_axi_rready" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_hsize", + "sources":[ + "~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid", + "~axi4_to_ahb|axi4_to_ahb>io_axi_arsize", + "~axi4_to_ahb|axi4_to_ahb>io_axi_bready", + "~axi4_to_ahb|axi4_to_ahb>io_axi_rready" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_awready", + "sources":[ + "~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid", + "~axi4_to_ahb|axi4_to_ahb>io_axi_bready", + "~axi4_to_ahb|axi4_to_ahb>io_axi_rready" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_arready", + "sources":[ + "~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid", + "~axi4_to_ahb|axi4_to_ahb>io_axi_bready", + "~axi4_to_ahb|axi4_to_ahb>io_axi_rready" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_rvalid", + "sources":[ + "~axi4_to_ahb|axi4_to_ahb>io_axi_bready", + "~axi4_to_ahb|axi4_to_ahb>io_axi_rready", + "~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_hprot", + "sources":[ + "~axi4_to_ahb|axi4_to_ahb>io_axi_arprot" + ] + }, + { + "class":"firrtl.EmitCircuitAnnotation", + "emitter":"firrtl.VerilogEmitter" + }, + { + "class":"firrtl.transforms.BlackBoxResourceAnno", + "target":"axi4_to_ahb.gated_latch", + "resourceId":"/vsrc/gated_latch.v" + }, + { + "class":"firrtl.options.TargetDirAnnotation", + "directory":"." + }, + { + "class":"firrtl.options.OutputAnnotationFileAnnotation", + "file":"axi4_to_ahb" + }, + { + "class":"firrtl.transforms.BlackBoxTargetDirAnno", + "targetDir":"." + } +] \ No newline at end of file diff --git a/axi4_to_ahb.fir b/axi4_to_ahb.fir new file mode 100644 index 00000000..d895ef59 --- /dev/null +++ b/axi4_to_ahb.fir @@ -0,0 +1,1288 @@ +;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 +circuit axi4_to_ahb : + extmodule gated_latch : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_1 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_1 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_1 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_2 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_2 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_2 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_3 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_3 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_3 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_4 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_4 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_4 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_5 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_5 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_5 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + module axi4_to_ahb : + input clock : Clock + input reset : AsyncReset + output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi_awvalid : UInt<1>, flip axi_awid : UInt<1>, flip axi_awaddr : UInt<32>, flip axi_awsize : UInt<3>, flip axi_awprot : UInt<3>, flip axi_wvalid : UInt<1>, flip axi_wdata : UInt<64>, flip axi_wstrb : UInt<8>, flip axi_wlast : UInt<1>, flip axi_bready : UInt<1>, flip axi_arvalid : UInt<1>, flip axi_arid : UInt<1>, flip axi_araddr : UInt<32>, flip axi_arsize : UInt<3>, flip axi_arprot : UInt<3>, flip axi_rready : UInt<1>, flip ahb_hrdata : UInt<64>, flip ahb_hready : UInt<1>, flip ahb_hresp : UInt<1>, axi_awready : UInt<1>, axi_wready : UInt<1>, axi_bvalid : UInt<1>, axi_bresp : UInt<2>, axi_bid : UInt<1>, axi_arready : UInt<1>, axi_rvalid : UInt<1>, axi_rid : UInt<1>, axi_rdata : UInt<32>, axi_rresp : UInt<2>, axi_rlast : UInt<1>, ahb_haddr : UInt<32>, ahb_hburst : UInt<3>, ahb_hmastlock : UInt<1>, ahb_hprot : UInt<4>, ahb_hsize : UInt<3>, ahb_htrans : UInt<2>, ahb_hwrite : UInt<1>, ahb_hwdata : UInt<64>} + + reg state : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[axi4_to_ahb.scala 61:22] + reg buf_state : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[axi4_to_ahb.scala 62:26] + reg buf_nxtstate : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[axi4_to_ahb.scala 63:29] + wire slave_valid : UInt<1> + slave_valid <= UInt<1>("h00") + wire slave_ready : UInt<1> + slave_ready <= UInt<1>("h00") + wire slave_tag : UInt<1> + slave_tag <= UInt<1>("h00") + wire slave_rdata : UInt<64> + slave_rdata <= UInt<64>("h00") + wire slave_opc : UInt<4> + slave_opc <= UInt<4>("h00") + wire wrbuf_en : UInt<1> + wrbuf_en <= UInt<1>("h00") + wire wrbuf_data_en : UInt<1> + wrbuf_data_en <= UInt<1>("h00") + wire wrbuf_cmd_sent : UInt<1> + wrbuf_cmd_sent <= UInt<1>("h00") + wire wrbuf_rst : UInt<1> + wrbuf_rst <= UInt<1>("h00") + wire wrbuf_vld : UInt<1> + wrbuf_vld <= UInt<1>("h00") + wire wrbuf_data_vld : UInt<1> + wrbuf_data_vld <= UInt<1>("h00") + wire wrbuf_tag : UInt<1> + wrbuf_tag <= UInt<1>("h00") + wire wrbuf_size : UInt<3> + wrbuf_size <= UInt<3>("h00") + wire wrbuf_addr : UInt<32> + wrbuf_addr <= UInt<32>("h00") + wire wrbuf_data : UInt<64> + wrbuf_data <= UInt<64>("h00") + wire wrbuf_byteen : UInt<8> + wrbuf_byteen <= UInt<8>("h00") + wire bus_write_clk_en : UInt<1> + bus_write_clk_en <= UInt<1>("h00") + wire bus_clk : Clock @[axi4_to_ahb.scala 83:21] + wire bus_write_clk : Clock @[axi4_to_ahb.scala 84:27] + wire master_valid : UInt<1> + master_valid <= UInt<1>("h00") + wire master_ready : UInt<1> + master_ready <= UInt<1>("h00") + wire master_tag : UInt<1> + master_tag <= UInt<1>("h00") + wire master_addr : UInt<32> + master_addr <= UInt<32>("h00") + wire master_wdata : UInt<64> + master_wdata <= UInt<64>("h00") + wire master_size : UInt<3> + master_size <= UInt<3>("h00") + wire master_opc : UInt<3> + master_opc <= UInt<3>("h00") + wire master_byteen : UInt<8> + master_byteen <= UInt<8>("h00") + wire buf_addr : UInt<32> + buf_addr <= UInt<32>("h00") + wire buf_size : UInt<2> + buf_size <= UInt<2>("h00") + wire buf_write : UInt<1> + buf_write <= UInt<1>("h00") + wire buf_byteen : UInt<8> + buf_byteen <= UInt<8>("h00") + wire buf_aligned : UInt<1> + buf_aligned <= UInt<1>("h00") + wire buf_data : UInt<64> + buf_data <= UInt<64>("h00") + wire buf_tag : UInt<1> + buf_tag <= UInt<1>("h00") + wire buf_rst : UInt<1> + buf_rst <= UInt<1>("h00") + wire buf_tag_in : UInt<1> + buf_tag_in <= UInt<1>("h00") + wire buf_addr_in : UInt<32> + buf_addr_in <= UInt<32>("h00") + wire buf_byteen_in : UInt<8> + buf_byteen_in <= UInt<8>("h00") + wire buf_data_in : UInt<64> + buf_data_in <= UInt<64>("h00") + wire buf_write_in : UInt<1> + buf_write_in <= UInt<1>("h00") + wire buf_aligned_in : UInt<1> + buf_aligned_in <= UInt<1>("h00") + wire buf_size_in : UInt<3> + buf_size_in <= UInt<3>("h00") + wire buf_state_en : UInt<1> + buf_state_en <= UInt<1>("h00") + wire buf_wr_en : UInt<1> + buf_wr_en <= UInt<1>("h00") + wire buf_data_wr_en : UInt<1> + buf_data_wr_en <= UInt<1>("h00") + wire slvbuf_error_en : UInt<1> + slvbuf_error_en <= UInt<1>("h00") + wire wr_cmd_vld : UInt<1> + wr_cmd_vld <= UInt<1>("h00") + wire cmd_done_rst : UInt<1> + cmd_done_rst <= UInt<1>("h00") + wire cmd_done : UInt<1> + cmd_done <= UInt<1>("h00") + wire cmd_doneQ : UInt<1> + cmd_doneQ <= UInt<1>("h00") + wire trxn_done : UInt<1> + trxn_done <= UInt<1>("h00") + wire buf_cmd_byte_ptr : UInt<3> + buf_cmd_byte_ptr <= UInt<3>("h00") + wire buf_cmd_byte_ptrQ : UInt<3> + buf_cmd_byte_ptrQ <= UInt<3>("h00") + wire buf_cmd_nxtbyte_ptr : UInt<3> + buf_cmd_nxtbyte_ptr <= UInt<3>("h00") + wire buf_cmd_byte_ptr_en : UInt<1> + buf_cmd_byte_ptr_en <= UInt<1>("h00") + wire found : UInt<1> + found <= UInt<1>("h00") + wire slave_valid_pre : UInt<1> + slave_valid_pre <= UInt<1>("h00") + wire ahb_hready_q : UInt<1> + ahb_hready_q <= UInt<1>("h00") + wire ahb_hresp_q : UInt<1> + ahb_hresp_q <= UInt<1>("h00") + wire ahb_htrans_q : UInt<2> + ahb_htrans_q <= UInt<2>("h00") + wire ahb_hwrite_q : UInt<1> + ahb_hwrite_q <= UInt<1>("h00") + wire ahb_hrdata_q : UInt<64> + ahb_hrdata_q <= UInt<64>("h00") + wire slvbuf_write : UInt<1> + slvbuf_write <= UInt<1>("h00") + wire slvbuf_error : UInt<1> + slvbuf_error <= UInt<1>("h00") + wire slvbuf_tag : UInt<1> + slvbuf_tag <= UInt<1>("h00") + wire slvbuf_error_in : UInt<1> + slvbuf_error_in <= UInt<1>("h00") + wire slvbuf_wr_en : UInt<1> + slvbuf_wr_en <= UInt<1>("h00") + wire bypass_en : UInt<1> + bypass_en <= UInt<1>("h00") + wire rd_bypass_idle : UInt<1> + rd_bypass_idle <= UInt<1>("h00") + wire last_addr_en : UInt<1> + last_addr_en <= UInt<1>("h00") + wire last_bus_addr : UInt<32> + last_bus_addr <= UInt<32>("h00") + wire buf_clken : UInt<1> + buf_clken <= UInt<1>("h00") + wire slvbuf_clken : UInt<1> + slvbuf_clken <= UInt<1>("h00") + wire ahbm_addr_clken : UInt<1> + ahbm_addr_clken <= UInt<1>("h00") + wire ahbm_data_clken : UInt<1> + ahbm_data_clken <= UInt<1>("h00") + wire buf_clk : Clock @[axi4_to_ahb.scala 151:21] + wire ahbm_clk : Clock @[axi4_to_ahb.scala 153:22] + wire ahbm_addr_clk : Clock @[axi4_to_ahb.scala 154:27] + wire ahbm_data_clk : Clock @[axi4_to_ahb.scala 155:27] + node _T = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 183:30] + node _T_1 = and(_T, master_ready) @[axi4_to_ahb.scala 183:47] + wrbuf_en <= _T_1 @[axi4_to_ahb.scala 183:12] + node _T_2 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 184:34] + node _T_3 = and(_T_2, master_ready) @[axi4_to_ahb.scala 184:50] + wrbuf_data_en <= _T_3 @[axi4_to_ahb.scala 184:17] + node _T_4 = and(master_valid, master_ready) @[axi4_to_ahb.scala 185:34] + node _T_5 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 185:62] + node _T_6 = eq(_T_5, UInt<1>("h01")) @[axi4_to_ahb.scala 185:69] + node _T_7 = and(_T_4, _T_6) @[axi4_to_ahb.scala 185:49] + wrbuf_cmd_sent <= _T_7 @[axi4_to_ahb.scala 185:18] + node _T_8 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 186:33] + node _T_9 = and(wrbuf_cmd_sent, _T_8) @[axi4_to_ahb.scala 186:31] + wrbuf_rst <= _T_9 @[axi4_to_ahb.scala 186:13] + node _T_10 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 188:35] + node _T_11 = and(wrbuf_vld, _T_10) @[axi4_to_ahb.scala 188:33] + node _T_12 = eq(_T_11, UInt<1>("h00")) @[axi4_to_ahb.scala 188:21] + node _T_13 = and(_T_12, master_ready) @[axi4_to_ahb.scala 188:52] + io.axi_awready <= _T_13 @[axi4_to_ahb.scala 188:18] + node _T_14 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 189:39] + node _T_15 = and(wrbuf_data_vld, _T_14) @[axi4_to_ahb.scala 189:37] + node _T_16 = eq(_T_15, UInt<1>("h00")) @[axi4_to_ahb.scala 189:20] + node _T_17 = and(_T_16, master_ready) @[axi4_to_ahb.scala 189:56] + io.axi_wready <= _T_17 @[axi4_to_ahb.scala 189:17] + node _T_18 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 190:33] + node _T_19 = eq(_T_18, UInt<1>("h00")) @[axi4_to_ahb.scala 190:21] + node _T_20 = and(_T_19, master_ready) @[axi4_to_ahb.scala 190:51] + io.axi_arready <= _T_20 @[axi4_to_ahb.scala 190:18] + io.axi_rlast <= UInt<1>("h01") @[axi4_to_ahb.scala 191:16] + node _T_21 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 193:27] + wr_cmd_vld <= _T_21 @[axi4_to_ahb.scala 193:14] + node _T_22 = or(wr_cmd_vld, io.axi_arvalid) @[axi4_to_ahb.scala 194:30] + master_valid <= _T_22 @[axi4_to_ahb.scala 194:16] + node _T_23 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 195:38] + node _T_24 = bits(wrbuf_tag, 0, 0) @[axi4_to_ahb.scala 195:51] + node _T_25 = bits(io.axi_arid, 0, 0) @[axi4_to_ahb.scala 195:76] + node _T_26 = mux(_T_23, _T_24, _T_25) @[axi4_to_ahb.scala 195:20] + master_tag <= _T_26 @[axi4_to_ahb.scala 195:14] + node _T_27 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 196:38] + node _T_28 = mux(_T_27, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 196:20] + master_opc <= _T_28 @[axi4_to_ahb.scala 196:14] + node _T_29 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 197:39] + node _T_30 = bits(wrbuf_addr, 31, 0) @[axi4_to_ahb.scala 197:53] + node _T_31 = bits(io.axi_araddr, 31, 0) @[axi4_to_ahb.scala 197:75] + node _T_32 = mux(_T_29, _T_30, _T_31) @[axi4_to_ahb.scala 197:21] + master_addr <= _T_32 @[axi4_to_ahb.scala 197:15] + node _T_33 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 198:39] + node _T_34 = bits(wrbuf_size, 2, 0) @[axi4_to_ahb.scala 198:53] + node _T_35 = bits(io.axi_arsize, 2, 0) @[axi4_to_ahb.scala 198:74] + node _T_36 = mux(_T_33, _T_34, _T_35) @[axi4_to_ahb.scala 198:21] + master_size <= _T_36 @[axi4_to_ahb.scala 198:15] + node _T_37 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 199:32] + master_byteen <= _T_37 @[axi4_to_ahb.scala 199:17] + node _T_38 = bits(wrbuf_data, 63, 0) @[axi4_to_ahb.scala 200:29] + master_wdata <= _T_38 @[axi4_to_ahb.scala 200:16] + node _T_39 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 203:32] + node _T_40 = bits(slave_opc, 3, 3) @[axi4_to_ahb.scala 203:57] + node _T_41 = and(_T_39, _T_40) @[axi4_to_ahb.scala 203:46] + io.axi_bvalid <= _T_41 @[axi4_to_ahb.scala 203:17] + node _T_42 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 204:32] + node _T_43 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 204:59] + node _T_44 = mux(_T_43, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 204:49] + node _T_45 = mux(_T_42, UInt<2>("h02"), _T_44) @[axi4_to_ahb.scala 204:22] + io.axi_bresp <= _T_45 @[axi4_to_ahb.scala 204:16] + node _T_46 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 205:26] + io.axi_bid <= _T_46 @[axi4_to_ahb.scala 205:14] + node _T_47 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 207:32] + node _T_48 = bits(slave_opc, 3, 2) @[axi4_to_ahb.scala 207:58] + node _T_49 = eq(_T_48, UInt<1>("h00")) @[axi4_to_ahb.scala 207:65] + node _T_50 = and(_T_47, _T_49) @[axi4_to_ahb.scala 207:46] + io.axi_rvalid <= _T_50 @[axi4_to_ahb.scala 207:17] + node _T_51 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 208:32] + node _T_52 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 208:59] + node _T_53 = mux(_T_52, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 208:49] + node _T_54 = mux(_T_51, UInt<2>("h02"), _T_53) @[axi4_to_ahb.scala 208:22] + io.axi_rresp <= _T_54 @[axi4_to_ahb.scala 208:16] + node _T_55 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 209:26] + io.axi_rid <= _T_55 @[axi4_to_ahb.scala 209:14] + node _T_56 = bits(slave_rdata, 63, 0) @[axi4_to_ahb.scala 210:30] + io.axi_rdata <= _T_56 @[axi4_to_ahb.scala 210:16] + node _T_57 = and(io.axi_bready, io.axi_rready) @[axi4_to_ahb.scala 211:32] + slave_ready <= _T_57 @[axi4_to_ahb.scala 211:15] + node _T_58 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 214:56] + node _T_59 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 214:91] + node _T_60 = or(_T_58, _T_59) @[axi4_to_ahb.scala 214:74] + node _T_61 = and(io.bus_clk_en, _T_60) @[axi4_to_ahb.scala 214:37] + bus_write_clk_en <= _T_61 @[axi4_to_ahb.scala 214:20] + inst rvclkhdr of rvclkhdr @[el2_lib.scala 483:22] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr.io.en <= io.bus_clk_en @[el2_lib.scala 485:16] + rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + bus_clk <= rvclkhdr.io.l1clk @[axi4_to_ahb.scala 216:11] + node _T_62 = bits(bus_write_clk_en, 0, 0) @[axi4_to_ahb.scala 217:59] + inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 483:22] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_1.io.en <= _T_62 @[el2_lib.scala 485:16] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + bus_write_clk <= rvclkhdr_1.io.l1clk @[axi4_to_ahb.scala 217:17] + io.ahb_htrans <= UInt<1>("h00") @[axi4_to_ahb.scala 220:17] + master_ready <= UInt<1>("h00") @[axi4_to_ahb.scala 221:16] + buf_state_en <= UInt<1>("h00") @[axi4_to_ahb.scala 222:16] + node _T_63 = eq(UInt<3>("h00"), buf_state) @[Conditional.scala 37:30] + when _T_63 : @[Conditional.scala 40:58] + master_ready <= UInt<1>("h01") @[axi4_to_ahb.scala 225:20] + node _T_64 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 226:34] + node _T_65 = eq(_T_64, UInt<1>("h01")) @[axi4_to_ahb.scala 226:41] + buf_write_in <= _T_65 @[axi4_to_ahb.scala 226:20] + node _T_66 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 227:46] + node _T_67 = mux(_T_66, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 227:26] + buf_nxtstate <= _T_67 @[axi4_to_ahb.scala 227:20] + node _T_68 = and(master_valid, master_ready) @[axi4_to_ahb.scala 228:36] + buf_state_en <= _T_68 @[axi4_to_ahb.scala 228:20] + buf_wr_en <= buf_state_en @[axi4_to_ahb.scala 229:17] + node _T_69 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 230:54] + node _T_70 = and(buf_state_en, _T_69) @[axi4_to_ahb.scala 230:38] + buf_data_wr_en <= _T_70 @[axi4_to_ahb.scala 230:22] + buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 231:27] + node _T_71 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 233:50] + node _T_72 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 233:92] + node _T_73 = add(UInt<1>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 177:52] + node _T_74 = tail(_T_73, 1) @[axi4_to_ahb.scala 177:52] + node _T_75 = mux(UInt<1>("h00"), _T_74, UInt<1>("h00")) @[axi4_to_ahb.scala 177:24] + node _T_76 = bits(_T_72, 0, 0) @[axi4_to_ahb.scala 178:44] + node _T_77 = geq(UInt<1>("h00"), _T_75) @[axi4_to_ahb.scala 178:62] + node _T_78 = and(_T_76, _T_77) @[axi4_to_ahb.scala 178:48] + node _T_79 = bits(_T_72, 1, 1) @[axi4_to_ahb.scala 178:44] + node _T_80 = geq(UInt<1>("h01"), _T_75) @[axi4_to_ahb.scala 178:62] + node _T_81 = and(_T_79, _T_80) @[axi4_to_ahb.scala 178:48] + node _T_82 = bits(_T_72, 2, 2) @[axi4_to_ahb.scala 178:44] + node _T_83 = geq(UInt<2>("h02"), _T_75) @[axi4_to_ahb.scala 178:62] + node _T_84 = and(_T_82, _T_83) @[axi4_to_ahb.scala 178:48] + node _T_85 = bits(_T_72, 3, 3) @[axi4_to_ahb.scala 178:44] + node _T_86 = geq(UInt<2>("h03"), _T_75) @[axi4_to_ahb.scala 178:62] + node _T_87 = and(_T_85, _T_86) @[axi4_to_ahb.scala 178:48] + node _T_88 = bits(_T_72, 4, 4) @[axi4_to_ahb.scala 178:44] + node _T_89 = geq(UInt<3>("h04"), _T_75) @[axi4_to_ahb.scala 178:62] + node _T_90 = and(_T_88, _T_89) @[axi4_to_ahb.scala 178:48] + node _T_91 = bits(_T_72, 5, 5) @[axi4_to_ahb.scala 178:44] + node _T_92 = geq(UInt<3>("h05"), _T_75) @[axi4_to_ahb.scala 178:62] + node _T_93 = and(_T_91, _T_92) @[axi4_to_ahb.scala 178:48] + node _T_94 = bits(_T_72, 6, 6) @[axi4_to_ahb.scala 178:44] + node _T_95 = geq(UInt<3>("h06"), _T_75) @[axi4_to_ahb.scala 178:62] + node _T_96 = and(_T_94, _T_95) @[axi4_to_ahb.scala 178:48] + node _T_97 = bits(_T_72, 7, 7) @[axi4_to_ahb.scala 178:44] + node _T_98 = geq(UInt<3>("h07"), _T_75) @[axi4_to_ahb.scala 178:62] + node _T_99 = and(_T_97, _T_98) @[axi4_to_ahb.scala 178:48] + node _T_100 = mux(_T_99, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16] + node _T_101 = mux(_T_96, UInt<3>("h06"), _T_100) @[Mux.scala 98:16] + node _T_102 = mux(_T_93, UInt<3>("h05"), _T_101) @[Mux.scala 98:16] + node _T_103 = mux(_T_90, UInt<3>("h04"), _T_102) @[Mux.scala 98:16] + node _T_104 = mux(_T_87, UInt<2>("h03"), _T_103) @[Mux.scala 98:16] + node _T_105 = mux(_T_84, UInt<2>("h02"), _T_104) @[Mux.scala 98:16] + node _T_106 = mux(_T_81, UInt<1>("h01"), _T_105) @[Mux.scala 98:16] + node _T_107 = mux(_T_78, UInt<1>("h00"), _T_106) @[Mux.scala 98:16] + node _T_108 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 233:141] + node _T_109 = mux(_T_71, _T_107, _T_108) @[axi4_to_ahb.scala 233:30] + buf_cmd_byte_ptr <= _T_109 @[axi4_to_ahb.scala 233:24] + bypass_en <= buf_state_en @[axi4_to_ahb.scala 234:17] + node _T_110 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 235:51] + node _T_111 = and(bypass_en, _T_110) @[axi4_to_ahb.scala 235:35] + rd_bypass_idle <= _T_111 @[axi4_to_ahb.scala 235:22] + node _T_112 = bits(bypass_en, 0, 0) @[Bitwise.scala 72:15] + node _T_113 = mux(_T_112, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_114 = and(_T_113, UInt<2>("h02")) @[axi4_to_ahb.scala 236:45] + io.ahb_htrans <= _T_114 @[axi4_to_ahb.scala 236:21] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_115 = eq(UInt<3>("h01"), buf_state) @[Conditional.scala 37:30] + when _T_115 : @[Conditional.scala 39:67] + node _T_116 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 240:54] + node _T_117 = eq(_T_116, UInt<1>("h00")) @[axi4_to_ahb.scala 240:61] + node _T_118 = and(master_valid, _T_117) @[axi4_to_ahb.scala 240:41] + node _T_119 = bits(_T_118, 0, 0) @[axi4_to_ahb.scala 240:82] + node _T_120 = mux(_T_119, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 240:26] + buf_nxtstate <= _T_120 @[axi4_to_ahb.scala 240:20] + node _T_121 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 241:51] + node _T_122 = neq(_T_121, UInt<1>("h00")) @[axi4_to_ahb.scala 241:58] + node _T_123 = and(ahb_hready_q, _T_122) @[axi4_to_ahb.scala 241:36] + node _T_124 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 241:72] + node _T_125 = and(_T_123, _T_124) @[axi4_to_ahb.scala 241:70] + buf_state_en <= _T_125 @[axi4_to_ahb.scala 241:20] + node _T_126 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 242:34] + node _T_127 = and(buf_state_en, _T_126) @[axi4_to_ahb.scala 242:32] + cmd_done <= _T_127 @[axi4_to_ahb.scala 242:16] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 243:20] + node _T_128 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 244:52] + node _T_129 = neq(_T_128, UInt<1>("h00")) @[axi4_to_ahb.scala 244:59] + node _T_130 = and(ahb_hready_q, _T_129) @[axi4_to_ahb.scala 244:37] + node _T_131 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 244:73] + node _T_132 = and(_T_130, _T_131) @[axi4_to_ahb.scala 244:71] + node _T_133 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 244:104] + node _T_134 = and(_T_132, _T_133) @[axi4_to_ahb.scala 244:88] + master_ready <= _T_134 @[axi4_to_ahb.scala 244:20] + buf_wr_en <= master_ready @[axi4_to_ahb.scala 245:17] + node _T_135 = and(master_ready, master_valid) @[axi4_to_ahb.scala 246:33] + bypass_en <= _T_135 @[axi4_to_ahb.scala 246:17] + node _T_136 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 247:47] + node _T_137 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 247:62] + node _T_138 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 247:78] + node _T_139 = mux(_T_136, _T_137, _T_138) @[axi4_to_ahb.scala 247:30] + buf_cmd_byte_ptr <= _T_139 @[axi4_to_ahb.scala 247:24] + node _T_140 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 248:44] + node _T_141 = or(_T_140, bypass_en) @[axi4_to_ahb.scala 248:58] + node _T_142 = bits(_T_141, 0, 0) @[Bitwise.scala 72:15] + node _T_143 = mux(_T_142, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_144 = and(UInt<2>("h02"), _T_143) @[axi4_to_ahb.scala 248:32] + io.ahb_htrans <= _T_144 @[axi4_to_ahb.scala 248:21] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_145 = eq(UInt<3>("h06"), buf_state) @[Conditional.scala 37:30] + when _T_145 : @[Conditional.scala 39:67] + node _T_146 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 252:39] + node _T_147 = and(ahb_hready_q, _T_146) @[axi4_to_ahb.scala 252:37] + node _T_148 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 252:82] + node _T_149 = eq(_T_148, UInt<1>("h01")) @[axi4_to_ahb.scala 252:89] + node _T_150 = and(master_valid, _T_149) @[axi4_to_ahb.scala 252:70] + node _T_151 = eq(_T_150, UInt<1>("h00")) @[axi4_to_ahb.scala 252:55] + node _T_152 = and(_T_147, _T_151) @[axi4_to_ahb.scala 252:53] + master_ready <= _T_152 @[axi4_to_ahb.scala 252:20] + node _T_153 = and(master_valid, master_ready) @[axi4_to_ahb.scala 253:34] + node _T_154 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 253:62] + node _T_155 = eq(_T_154, UInt<1>("h00")) @[axi4_to_ahb.scala 253:69] + node _T_156 = and(_T_153, _T_155) @[axi4_to_ahb.scala 253:49] + buf_wr_en <= _T_156 @[axi4_to_ahb.scala 253:17] + node _T_157 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 254:45] + node _T_158 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 254:84] + node _T_159 = mux(_T_158, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 254:67] + node _T_160 = mux(_T_157, UInt<3>("h07"), _T_159) @[axi4_to_ahb.scala 254:26] + buf_nxtstate <= _T_160 @[axi4_to_ahb.scala 254:20] + node _T_161 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 255:37] + buf_state_en <= _T_161 @[axi4_to_ahb.scala 255:20] + buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 256:22] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 257:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 258:23] + node _T_162 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 259:41] + node _T_163 = and(buf_state_en, _T_162) @[axi4_to_ahb.scala 259:39] + slave_valid_pre <= _T_163 @[axi4_to_ahb.scala 259:23] + node _T_164 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 260:34] + node _T_165 = and(buf_state_en, _T_164) @[axi4_to_ahb.scala 260:32] + cmd_done <= _T_165 @[axi4_to_ahb.scala 260:16] + node _T_166 = and(master_ready, master_valid) @[axi4_to_ahb.scala 261:33] + node _T_167 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 261:64] + node _T_168 = and(_T_166, _T_167) @[axi4_to_ahb.scala 261:48] + node _T_169 = and(_T_168, buf_state_en) @[axi4_to_ahb.scala 261:79] + bypass_en <= _T_169 @[axi4_to_ahb.scala 261:17] + node _T_170 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 262:47] + node _T_171 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 262:62] + node _T_172 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 262:78] + node _T_173 = mux(_T_170, _T_171, _T_172) @[axi4_to_ahb.scala 262:30] + buf_cmd_byte_ptr <= _T_173 @[axi4_to_ahb.scala 262:24] + node _T_174 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 263:59] + node _T_175 = and(_T_174, buf_state_en) @[axi4_to_ahb.scala 263:74] + node _T_176 = eq(_T_175, UInt<1>("h00")) @[axi4_to_ahb.scala 263:43] + node _T_177 = bits(_T_176, 0, 0) @[Bitwise.scala 72:15] + node _T_178 = mux(_T_177, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_179 = and(UInt<2>("h02"), _T_178) @[axi4_to_ahb.scala 263:32] + io.ahb_htrans <= _T_179 @[axi4_to_ahb.scala 263:21] + slvbuf_wr_en <= buf_wr_en @[axi4_to_ahb.scala 264:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_180 = eq(UInt<3>("h07"), buf_state) @[Conditional.scala 37:30] + when _T_180 : @[Conditional.scala 39:67] + buf_nxtstate <= UInt<3>("h03") @[axi4_to_ahb.scala 268:20] + node _T_181 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 269:51] + node _T_182 = neq(_T_181, UInt<1>("h00")) @[axi4_to_ahb.scala 269:58] + node _T_183 = and(ahb_hready_q, _T_182) @[axi4_to_ahb.scala 269:36] + node _T_184 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 269:72] + node _T_185 = and(_T_183, _T_184) @[axi4_to_ahb.scala 269:70] + buf_state_en <= _T_185 @[axi4_to_ahb.scala 269:20] + slave_valid_pre <= buf_state_en @[axi4_to_ahb.scala 270:23] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 271:20] + node _T_186 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 272:35] + buf_cmd_byte_ptr <= _T_186 @[axi4_to_ahb.scala 272:24] + node _T_187 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 273:47] + node _T_188 = bits(_T_187, 0, 0) @[Bitwise.scala 72:15] + node _T_189 = mux(_T_188, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_190 = and(UInt<2>("h02"), _T_189) @[axi4_to_ahb.scala 273:37] + io.ahb_htrans <= _T_190 @[axi4_to_ahb.scala 273:21] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_191 = eq(UInt<3>("h03"), buf_state) @[Conditional.scala 37:30] + when _T_191 : @[Conditional.scala 39:67] + buf_nxtstate <= UInt<3>("h05") @[axi4_to_ahb.scala 277:20] + node _T_192 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 278:37] + buf_state_en <= _T_192 @[axi4_to_ahb.scala 278:20] + buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 279:22] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 280:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 281:23] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 282:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_193 = eq(UInt<3>("h02"), buf_state) @[Conditional.scala 37:30] + when _T_193 : @[Conditional.scala 39:67] + buf_nxtstate <= UInt<3>("h04") @[axi4_to_ahb.scala 286:20] + node _T_194 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 287:33] + node _T_195 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 287:63] + node _T_196 = neq(_T_195, UInt<1>("h00")) @[axi4_to_ahb.scala 287:70] + node _T_197 = and(_T_194, _T_196) @[axi4_to_ahb.scala 287:48] + trxn_done <= _T_197 @[axi4_to_ahb.scala 287:17] + buf_state_en <= trxn_done @[axi4_to_ahb.scala 288:20] + buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 289:27] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 290:20] + node _T_198 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 291:47] + node _T_199 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 291:85] + node _T_200 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 291:103] + node _T_201 = add(_T_199, UInt<1>("h01")) @[axi4_to_ahb.scala 177:52] + node _T_202 = tail(_T_201, 1) @[axi4_to_ahb.scala 177:52] + node _T_203 = mux(UInt<1>("h01"), _T_202, _T_199) @[axi4_to_ahb.scala 177:24] + node _T_204 = bits(_T_200, 0, 0) @[axi4_to_ahb.scala 178:44] + node _T_205 = geq(UInt<1>("h00"), _T_203) @[axi4_to_ahb.scala 178:62] + node _T_206 = and(_T_204, _T_205) @[axi4_to_ahb.scala 178:48] + node _T_207 = bits(_T_200, 1, 1) @[axi4_to_ahb.scala 178:44] + node _T_208 = geq(UInt<1>("h01"), _T_203) @[axi4_to_ahb.scala 178:62] + node _T_209 = and(_T_207, _T_208) @[axi4_to_ahb.scala 178:48] + node _T_210 = bits(_T_200, 2, 2) @[axi4_to_ahb.scala 178:44] + node _T_211 = geq(UInt<2>("h02"), _T_203) @[axi4_to_ahb.scala 178:62] + node _T_212 = and(_T_210, _T_211) @[axi4_to_ahb.scala 178:48] + node _T_213 = bits(_T_200, 3, 3) @[axi4_to_ahb.scala 178:44] + node _T_214 = geq(UInt<2>("h03"), _T_203) @[axi4_to_ahb.scala 178:62] + node _T_215 = and(_T_213, _T_214) @[axi4_to_ahb.scala 178:48] + node _T_216 = bits(_T_200, 4, 4) @[axi4_to_ahb.scala 178:44] + node _T_217 = geq(UInt<3>("h04"), _T_203) @[axi4_to_ahb.scala 178:62] + node _T_218 = and(_T_216, _T_217) @[axi4_to_ahb.scala 178:48] + node _T_219 = bits(_T_200, 5, 5) @[axi4_to_ahb.scala 178:44] + node _T_220 = geq(UInt<3>("h05"), _T_203) @[axi4_to_ahb.scala 178:62] + node _T_221 = and(_T_219, _T_220) @[axi4_to_ahb.scala 178:48] + node _T_222 = bits(_T_200, 6, 6) @[axi4_to_ahb.scala 178:44] + node _T_223 = geq(UInt<3>("h06"), _T_203) @[axi4_to_ahb.scala 178:62] + node _T_224 = and(_T_222, _T_223) @[axi4_to_ahb.scala 178:48] + node _T_225 = bits(_T_200, 7, 7) @[axi4_to_ahb.scala 178:44] + node _T_226 = geq(UInt<3>("h07"), _T_203) @[axi4_to_ahb.scala 178:62] + node _T_227 = and(_T_225, _T_226) @[axi4_to_ahb.scala 178:48] + node _T_228 = mux(_T_227, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16] + node _T_229 = mux(_T_224, UInt<3>("h06"), _T_228) @[Mux.scala 98:16] + node _T_230 = mux(_T_221, UInt<3>("h05"), _T_229) @[Mux.scala 98:16] + node _T_231 = mux(_T_218, UInt<3>("h04"), _T_230) @[Mux.scala 98:16] + node _T_232 = mux(_T_215, UInt<2>("h03"), _T_231) @[Mux.scala 98:16] + node _T_233 = mux(_T_212, UInt<2>("h02"), _T_232) @[Mux.scala 98:16] + node _T_234 = mux(_T_209, UInt<1>("h01"), _T_233) @[Mux.scala 98:16] + node _T_235 = mux(_T_206, UInt<1>("h00"), _T_234) @[Mux.scala 98:16] + node _T_236 = mux(_T_198, _T_235, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 291:30] + buf_cmd_byte_ptr <= _T_236 @[axi4_to_ahb.scala 291:24] + node _T_237 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 292:65] + node _T_238 = or(buf_aligned, _T_237) @[axi4_to_ahb.scala 292:44] + node _T_239 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 292:127] + node _T_240 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 292:145] + node _T_241 = add(_T_239, UInt<1>("h01")) @[axi4_to_ahb.scala 177:52] + node _T_242 = tail(_T_241, 1) @[axi4_to_ahb.scala 177:52] + node _T_243 = mux(UInt<1>("h01"), _T_242, _T_239) @[axi4_to_ahb.scala 177:24] + node _T_244 = bits(_T_240, 0, 0) @[axi4_to_ahb.scala 178:44] + node _T_245 = geq(UInt<1>("h00"), _T_243) @[axi4_to_ahb.scala 178:62] + node _T_246 = and(_T_244, _T_245) @[axi4_to_ahb.scala 178:48] + node _T_247 = bits(_T_240, 1, 1) @[axi4_to_ahb.scala 178:44] + node _T_248 = geq(UInt<1>("h01"), _T_243) @[axi4_to_ahb.scala 178:62] + node _T_249 = and(_T_247, _T_248) @[axi4_to_ahb.scala 178:48] + node _T_250 = bits(_T_240, 2, 2) @[axi4_to_ahb.scala 178:44] + node _T_251 = geq(UInt<2>("h02"), _T_243) @[axi4_to_ahb.scala 178:62] + node _T_252 = and(_T_250, _T_251) @[axi4_to_ahb.scala 178:48] + node _T_253 = bits(_T_240, 3, 3) @[axi4_to_ahb.scala 178:44] + node _T_254 = geq(UInt<2>("h03"), _T_243) @[axi4_to_ahb.scala 178:62] + node _T_255 = and(_T_253, _T_254) @[axi4_to_ahb.scala 178:48] + node _T_256 = bits(_T_240, 4, 4) @[axi4_to_ahb.scala 178:44] + node _T_257 = geq(UInt<3>("h04"), _T_243) @[axi4_to_ahb.scala 178:62] + node _T_258 = and(_T_256, _T_257) @[axi4_to_ahb.scala 178:48] + node _T_259 = bits(_T_240, 5, 5) @[axi4_to_ahb.scala 178:44] + node _T_260 = geq(UInt<3>("h05"), _T_243) @[axi4_to_ahb.scala 178:62] + node _T_261 = and(_T_259, _T_260) @[axi4_to_ahb.scala 178:48] + node _T_262 = bits(_T_240, 6, 6) @[axi4_to_ahb.scala 178:44] + node _T_263 = geq(UInt<3>("h06"), _T_243) @[axi4_to_ahb.scala 178:62] + node _T_264 = and(_T_262, _T_263) @[axi4_to_ahb.scala 178:48] + node _T_265 = bits(_T_240, 7, 7) @[axi4_to_ahb.scala 178:44] + node _T_266 = geq(UInt<3>("h07"), _T_243) @[axi4_to_ahb.scala 178:62] + node _T_267 = and(_T_265, _T_266) @[axi4_to_ahb.scala 178:48] + node _T_268 = mux(_T_267, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16] + node _T_269 = mux(_T_264, UInt<3>("h06"), _T_268) @[Mux.scala 98:16] + node _T_270 = mux(_T_261, UInt<3>("h05"), _T_269) @[Mux.scala 98:16] + node _T_271 = mux(_T_258, UInt<3>("h04"), _T_270) @[Mux.scala 98:16] + node _T_272 = mux(_T_255, UInt<2>("h03"), _T_271) @[Mux.scala 98:16] + node _T_273 = mux(_T_252, UInt<2>("h02"), _T_272) @[Mux.scala 98:16] + node _T_274 = mux(_T_249, UInt<1>("h01"), _T_273) @[Mux.scala 98:16] + node _T_275 = mux(_T_246, UInt<1>("h00"), _T_274) @[Mux.scala 98:16] + node _T_276 = dshr(buf_byteen, _T_275) @[axi4_to_ahb.scala 292:92] + node _T_277 = bits(_T_276, 0, 0) @[axi4_to_ahb.scala 292:92] + node _T_278 = eq(_T_277, UInt<1>("h00")) @[axi4_to_ahb.scala 292:163] + node _T_279 = or(_T_238, _T_278) @[axi4_to_ahb.scala 292:79] + node _T_280 = and(trxn_done, _T_279) @[axi4_to_ahb.scala 292:29] + cmd_done <= _T_280 @[axi4_to_ahb.scala 292:16] + node _T_281 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 293:43] + node _T_282 = eq(_T_281, UInt<1>("h00")) @[axi4_to_ahb.scala 293:32] + node _T_283 = bits(_T_282, 0, 0) @[Bitwise.scala 72:15] + node _T_284 = mux(_T_283, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_285 = and(_T_284, UInt<2>("h02")) @[axi4_to_ahb.scala 293:57] + io.ahb_htrans <= _T_285 @[axi4_to_ahb.scala 293:21] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_286 = eq(UInt<3>("h04"), buf_state) @[Conditional.scala 37:30] + when _T_286 : @[Conditional.scala 39:67] + node _T_287 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 297:34] + node _T_288 = or(_T_287, ahb_hresp_q) @[axi4_to_ahb.scala 297:50] + buf_state_en <= _T_288 @[axi4_to_ahb.scala 297:20] + node _T_289 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 298:35] + node _T_290 = or(_T_289, ahb_hresp_q) @[axi4_to_ahb.scala 298:51] + node _T_291 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 298:68] + node _T_292 = and(_T_290, _T_291) @[axi4_to_ahb.scala 298:66] + node _T_293 = and(_T_292, slave_ready) @[axi4_to_ahb.scala 298:81] + master_ready <= _T_293 @[axi4_to_ahb.scala 298:20] + node _T_294 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 299:42] + node _T_295 = or(ahb_hresp_q, _T_294) @[axi4_to_ahb.scala 299:40] + node _T_296 = bits(_T_295, 0, 0) @[axi4_to_ahb.scala 299:62] + node _T_297 = and(master_valid, master_ready) @[axi4_to_ahb.scala 299:90] + node _T_298 = bits(_T_297, 0, 0) @[axi4_to_ahb.scala 299:112] + node _T_299 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 299:131] + node _T_300 = eq(_T_299, UInt<1>("h01")) @[axi4_to_ahb.scala 299:138] + node _T_301 = mux(_T_300, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 299:119] + node _T_302 = mux(_T_298, _T_301, UInt<3>("h00")) @[axi4_to_ahb.scala 299:75] + node _T_303 = mux(_T_296, UInt<3>("h05"), _T_302) @[axi4_to_ahb.scala 299:26] + buf_nxtstate <= _T_303 @[axi4_to_ahb.scala 299:20] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 300:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 301:23] + node _T_304 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 302:34] + node _T_305 = eq(_T_304, UInt<1>("h01")) @[axi4_to_ahb.scala 302:41] + buf_write_in <= _T_305 @[axi4_to_ahb.scala 302:20] + node _T_306 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 303:50] + node _T_307 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 303:78] + node _T_308 = or(_T_306, _T_307) @[axi4_to_ahb.scala 303:62] + node _T_309 = and(buf_state_en, _T_308) @[axi4_to_ahb.scala 303:33] + buf_wr_en <= _T_309 @[axi4_to_ahb.scala 303:17] + buf_data_wr_en <= buf_wr_en @[axi4_to_ahb.scala 304:22] + node _T_310 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 305:63] + node _T_311 = neq(_T_310, UInt<1>("h00")) @[axi4_to_ahb.scala 305:70] + node _T_312 = and(ahb_hready_q, _T_311) @[axi4_to_ahb.scala 305:48] + node _T_313 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 305:104] + node _T_314 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 305:166] + node _T_315 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 305:184] + node _T_316 = add(_T_314, UInt<1>("h01")) @[axi4_to_ahb.scala 177:52] + node _T_317 = tail(_T_316, 1) @[axi4_to_ahb.scala 177:52] + node _T_318 = mux(UInt<1>("h01"), _T_317, _T_314) @[axi4_to_ahb.scala 177:24] + node _T_319 = bits(_T_315, 0, 0) @[axi4_to_ahb.scala 178:44] + node _T_320 = geq(UInt<1>("h00"), _T_318) @[axi4_to_ahb.scala 178:62] + node _T_321 = and(_T_319, _T_320) @[axi4_to_ahb.scala 178:48] + node _T_322 = bits(_T_315, 1, 1) @[axi4_to_ahb.scala 178:44] + node _T_323 = geq(UInt<1>("h01"), _T_318) @[axi4_to_ahb.scala 178:62] + node _T_324 = and(_T_322, _T_323) @[axi4_to_ahb.scala 178:48] + node _T_325 = bits(_T_315, 2, 2) @[axi4_to_ahb.scala 178:44] + node _T_326 = geq(UInt<2>("h02"), _T_318) @[axi4_to_ahb.scala 178:62] + node _T_327 = and(_T_325, _T_326) @[axi4_to_ahb.scala 178:48] + node _T_328 = bits(_T_315, 3, 3) @[axi4_to_ahb.scala 178:44] + node _T_329 = geq(UInt<2>("h03"), _T_318) @[axi4_to_ahb.scala 178:62] + node _T_330 = and(_T_328, _T_329) @[axi4_to_ahb.scala 178:48] + node _T_331 = bits(_T_315, 4, 4) @[axi4_to_ahb.scala 178:44] + node _T_332 = geq(UInt<3>("h04"), _T_318) @[axi4_to_ahb.scala 178:62] + node _T_333 = and(_T_331, _T_332) @[axi4_to_ahb.scala 178:48] + node _T_334 = bits(_T_315, 5, 5) @[axi4_to_ahb.scala 178:44] + node _T_335 = geq(UInt<3>("h05"), _T_318) @[axi4_to_ahb.scala 178:62] + node _T_336 = and(_T_334, _T_335) @[axi4_to_ahb.scala 178:48] + node _T_337 = bits(_T_315, 6, 6) @[axi4_to_ahb.scala 178:44] + node _T_338 = geq(UInt<3>("h06"), _T_318) @[axi4_to_ahb.scala 178:62] + node _T_339 = and(_T_337, _T_338) @[axi4_to_ahb.scala 178:48] + node _T_340 = bits(_T_315, 7, 7) @[axi4_to_ahb.scala 178:44] + node _T_341 = geq(UInt<3>("h07"), _T_318) @[axi4_to_ahb.scala 178:62] + node _T_342 = and(_T_340, _T_341) @[axi4_to_ahb.scala 178:48] + node _T_343 = mux(_T_342, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16] + node _T_344 = mux(_T_339, UInt<3>("h06"), _T_343) @[Mux.scala 98:16] + node _T_345 = mux(_T_336, UInt<3>("h05"), _T_344) @[Mux.scala 98:16] + node _T_346 = mux(_T_333, UInt<3>("h04"), _T_345) @[Mux.scala 98:16] + node _T_347 = mux(_T_330, UInt<2>("h03"), _T_346) @[Mux.scala 98:16] + node _T_348 = mux(_T_327, UInt<2>("h02"), _T_347) @[Mux.scala 98:16] + node _T_349 = mux(_T_324, UInt<1>("h01"), _T_348) @[Mux.scala 98:16] + node _T_350 = mux(_T_321, UInt<1>("h00"), _T_349) @[Mux.scala 98:16] + node _T_351 = dshr(buf_byteen, _T_350) @[axi4_to_ahb.scala 305:131] + node _T_352 = bits(_T_351, 0, 0) @[axi4_to_ahb.scala 305:131] + node _T_353 = eq(_T_352, UInt<1>("h00")) @[axi4_to_ahb.scala 305:202] + node _T_354 = or(_T_313, _T_353) @[axi4_to_ahb.scala 305:118] + node _T_355 = and(_T_312, _T_354) @[axi4_to_ahb.scala 305:82] + node _T_356 = or(ahb_hresp_q, _T_355) @[axi4_to_ahb.scala 305:32] + cmd_done <= _T_356 @[axi4_to_ahb.scala 305:16] + node _T_357 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 306:33] + node _T_358 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 306:64] + node _T_359 = and(_T_357, _T_358) @[axi4_to_ahb.scala 306:48] + bypass_en <= _T_359 @[axi4_to_ahb.scala 306:17] + node _T_360 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 307:44] + node _T_361 = eq(_T_360, UInt<1>("h00")) @[axi4_to_ahb.scala 307:33] + node _T_362 = or(_T_361, bypass_en) @[axi4_to_ahb.scala 307:57] + node _T_363 = bits(_T_362, 0, 0) @[Bitwise.scala 72:15] + node _T_364 = mux(_T_363, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_365 = and(_T_364, UInt<2>("h02")) @[axi4_to_ahb.scala 307:71] + io.ahb_htrans <= _T_365 @[axi4_to_ahb.scala 307:21] + node _T_366 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 308:55] + node _T_367 = and(buf_state_en, _T_366) @[axi4_to_ahb.scala 308:39] + slave_valid_pre <= _T_367 @[axi4_to_ahb.scala 308:23] + node _T_368 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 309:33] + node _T_369 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 309:63] + node _T_370 = neq(_T_369, UInt<1>("h00")) @[axi4_to_ahb.scala 309:70] + node _T_371 = and(_T_368, _T_370) @[axi4_to_ahb.scala 309:48] + trxn_done <= _T_371 @[axi4_to_ahb.scala 309:17] + node _T_372 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 310:40] + buf_cmd_byte_ptr_en <= _T_372 @[axi4_to_ahb.scala 310:27] + node _T_373 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_374 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 313:85] + node _T_375 = add(_T_373, UInt<1>("h01")) @[axi4_to_ahb.scala 177:52] + node _T_376 = tail(_T_375, 1) @[axi4_to_ahb.scala 177:52] + node _T_377 = mux(UInt<1>("h00"), _T_376, _T_373) @[axi4_to_ahb.scala 177:24] + node _T_378 = bits(_T_374, 0, 0) @[axi4_to_ahb.scala 178:44] + node _T_379 = geq(UInt<1>("h00"), _T_377) @[axi4_to_ahb.scala 178:62] + node _T_380 = and(_T_378, _T_379) @[axi4_to_ahb.scala 178:48] + node _T_381 = bits(_T_374, 1, 1) @[axi4_to_ahb.scala 178:44] + node _T_382 = geq(UInt<1>("h01"), _T_377) @[axi4_to_ahb.scala 178:62] + node _T_383 = and(_T_381, _T_382) @[axi4_to_ahb.scala 178:48] + node _T_384 = bits(_T_374, 2, 2) @[axi4_to_ahb.scala 178:44] + node _T_385 = geq(UInt<2>("h02"), _T_377) @[axi4_to_ahb.scala 178:62] + node _T_386 = and(_T_384, _T_385) @[axi4_to_ahb.scala 178:48] + node _T_387 = bits(_T_374, 3, 3) @[axi4_to_ahb.scala 178:44] + node _T_388 = geq(UInt<2>("h03"), _T_377) @[axi4_to_ahb.scala 178:62] + node _T_389 = and(_T_387, _T_388) @[axi4_to_ahb.scala 178:48] + node _T_390 = bits(_T_374, 4, 4) @[axi4_to_ahb.scala 178:44] + node _T_391 = geq(UInt<3>("h04"), _T_377) @[axi4_to_ahb.scala 178:62] + node _T_392 = and(_T_390, _T_391) @[axi4_to_ahb.scala 178:48] + node _T_393 = bits(_T_374, 5, 5) @[axi4_to_ahb.scala 178:44] + node _T_394 = geq(UInt<3>("h05"), _T_377) @[axi4_to_ahb.scala 178:62] + node _T_395 = and(_T_393, _T_394) @[axi4_to_ahb.scala 178:48] + node _T_396 = bits(_T_374, 6, 6) @[axi4_to_ahb.scala 178:44] + node _T_397 = geq(UInt<3>("h06"), _T_377) @[axi4_to_ahb.scala 178:62] + node _T_398 = and(_T_396, _T_397) @[axi4_to_ahb.scala 178:48] + node _T_399 = bits(_T_374, 7, 7) @[axi4_to_ahb.scala 178:44] + node _T_400 = geq(UInt<3>("h07"), _T_377) @[axi4_to_ahb.scala 178:62] + node _T_401 = and(_T_399, _T_400) @[axi4_to_ahb.scala 178:48] + node _T_402 = mux(_T_401, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16] + node _T_403 = mux(_T_398, UInt<3>("h06"), _T_402) @[Mux.scala 98:16] + node _T_404 = mux(_T_395, UInt<3>("h05"), _T_403) @[Mux.scala 98:16] + node _T_405 = mux(_T_392, UInt<3>("h04"), _T_404) @[Mux.scala 98:16] + node _T_406 = mux(_T_389, UInt<2>("h03"), _T_405) @[Mux.scala 98:16] + node _T_407 = mux(_T_386, UInt<2>("h02"), _T_406) @[Mux.scala 98:16] + node _T_408 = mux(_T_383, UInt<1>("h01"), _T_407) @[Mux.scala 98:16] + node _T_409 = mux(_T_380, UInt<1>("h00"), _T_408) @[Mux.scala 98:16] + node _T_410 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 313:151] + node _T_411 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 313:169] + node _T_412 = add(_T_410, UInt<1>("h01")) @[axi4_to_ahb.scala 177:52] + node _T_413 = tail(_T_412, 1) @[axi4_to_ahb.scala 177:52] + node _T_414 = mux(UInt<1>("h01"), _T_413, _T_410) @[axi4_to_ahb.scala 177:24] + node _T_415 = bits(_T_411, 0, 0) @[axi4_to_ahb.scala 178:44] + node _T_416 = geq(UInt<1>("h00"), _T_414) @[axi4_to_ahb.scala 178:62] + node _T_417 = and(_T_415, _T_416) @[axi4_to_ahb.scala 178:48] + node _T_418 = bits(_T_411, 1, 1) @[axi4_to_ahb.scala 178:44] + node _T_419 = geq(UInt<1>("h01"), _T_414) @[axi4_to_ahb.scala 178:62] + node _T_420 = and(_T_418, _T_419) @[axi4_to_ahb.scala 178:48] + node _T_421 = bits(_T_411, 2, 2) @[axi4_to_ahb.scala 178:44] + node _T_422 = geq(UInt<2>("h02"), _T_414) @[axi4_to_ahb.scala 178:62] + node _T_423 = and(_T_421, _T_422) @[axi4_to_ahb.scala 178:48] + node _T_424 = bits(_T_411, 3, 3) @[axi4_to_ahb.scala 178:44] + node _T_425 = geq(UInt<2>("h03"), _T_414) @[axi4_to_ahb.scala 178:62] + node _T_426 = and(_T_424, _T_425) @[axi4_to_ahb.scala 178:48] + node _T_427 = bits(_T_411, 4, 4) @[axi4_to_ahb.scala 178:44] + node _T_428 = geq(UInt<3>("h04"), _T_414) @[axi4_to_ahb.scala 178:62] + node _T_429 = and(_T_427, _T_428) @[axi4_to_ahb.scala 178:48] + node _T_430 = bits(_T_411, 5, 5) @[axi4_to_ahb.scala 178:44] + node _T_431 = geq(UInt<3>("h05"), _T_414) @[axi4_to_ahb.scala 178:62] + node _T_432 = and(_T_430, _T_431) @[axi4_to_ahb.scala 178:48] + node _T_433 = bits(_T_411, 6, 6) @[axi4_to_ahb.scala 178:44] + node _T_434 = geq(UInt<3>("h06"), _T_414) @[axi4_to_ahb.scala 178:62] + node _T_435 = and(_T_433, _T_434) @[axi4_to_ahb.scala 178:48] + node _T_436 = bits(_T_411, 7, 7) @[axi4_to_ahb.scala 178:44] + node _T_437 = geq(UInt<3>("h07"), _T_414) @[axi4_to_ahb.scala 178:62] + node _T_438 = and(_T_436, _T_437) @[axi4_to_ahb.scala 178:48] + node _T_439 = mux(_T_438, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16] + node _T_440 = mux(_T_435, UInt<3>("h06"), _T_439) @[Mux.scala 98:16] + node _T_441 = mux(_T_432, UInt<3>("h05"), _T_440) @[Mux.scala 98:16] + node _T_442 = mux(_T_429, UInt<3>("h04"), _T_441) @[Mux.scala 98:16] + node _T_443 = mux(_T_426, UInt<2>("h03"), _T_442) @[Mux.scala 98:16] + node _T_444 = mux(_T_423, UInt<2>("h02"), _T_443) @[Mux.scala 98:16] + node _T_445 = mux(_T_420, UInt<1>("h01"), _T_444) @[Mux.scala 98:16] + node _T_446 = mux(_T_417, UInt<1>("h00"), _T_445) @[Mux.scala 98:16] + node _T_447 = mux(trxn_done, _T_446, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 313:106] + node _T_448 = mux(bypass_en, _T_409, _T_447) @[axi4_to_ahb.scala 313:30] + buf_cmd_byte_ptr <= _T_448 @[axi4_to_ahb.scala 313:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_449 = eq(UInt<3>("h05"), buf_state) @[Conditional.scala 37:30] + when _T_449 : @[Conditional.scala 39:67] + buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 316:20] + buf_state_en <= slave_ready @[axi4_to_ahb.scala 317:20] + slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 318:23] + slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 319:23] + skip @[Conditional.scala 39:67] + buf_rst <= UInt<1>("h00") @[axi4_to_ahb.scala 323:11] + cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 324:16] + node _T_450 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 325:68] + node _T_451 = eq(_T_450, UInt<1>("h01")) @[axi4_to_ahb.scala 325:75] + node _T_452 = and(buf_aligned_in, _T_451) @[axi4_to_ahb.scala 325:55] + node _T_453 = bits(_T_452, 0, 0) @[axi4_to_ahb.scala 325:95] + node _T_454 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 325:127] + wire _T_455 : UInt<8> + _T_455 <= UInt<8>("h00") + node _T_456 = bits(_T_455, 7, 0) @[axi4_to_ahb.scala 169:44] + node _T_457 = eq(_T_456, UInt<8>("h0ff")) @[axi4_to_ahb.scala 169:51] + node _T_458 = bits(_T_455, 7, 0) @[axi4_to_ahb.scala 169:75] + node _T_459 = eq(_T_458, UInt<4>("h0f")) @[axi4_to_ahb.scala 169:82] + node _T_460 = or(_T_457, _T_459) @[axi4_to_ahb.scala 169:64] + node _T_461 = bits(_T_455, 7, 0) @[axi4_to_ahb.scala 169:106] + node _T_462 = eq(_T_461, UInt<2>("h03")) @[axi4_to_ahb.scala 169:113] + node _T_463 = or(_T_460, _T_462) @[axi4_to_ahb.scala 169:95] + node _T_464 = bits(_T_463, 0, 0) @[Bitwise.scala 72:15] + node _T_465 = mux(_T_464, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_466 = and(UInt<1>("h00"), _T_465) @[axi4_to_ahb.scala 169:24] + node _T_467 = bits(_T_455, 7, 0) @[axi4_to_ahb.scala 170:35] + node _T_468 = eq(_T_467, UInt<4>("h0c")) @[axi4_to_ahb.scala 170:42] + node _T_469 = bits(_T_468, 0, 0) @[Bitwise.scala 72:15] + node _T_470 = mux(_T_469, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_471 = and(UInt<2>("h02"), _T_470) @[axi4_to_ahb.scala 170:15] + node _T_472 = or(_T_466, _T_471) @[axi4_to_ahb.scala 169:128] + node _T_473 = bits(_T_455, 7, 0) @[axi4_to_ahb.scala 171:36] + node _T_474 = eq(_T_473, UInt<8>("h0f0")) @[axi4_to_ahb.scala 171:43] + node _T_475 = bits(_T_455, 7, 0) @[axi4_to_ahb.scala 171:67] + node _T_476 = eq(_T_475, UInt<2>("h03")) @[axi4_to_ahb.scala 171:74] + node _T_477 = or(_T_474, _T_476) @[axi4_to_ahb.scala 171:56] + node _T_478 = bits(_T_477, 0, 0) @[Bitwise.scala 72:15] + node _T_479 = mux(_T_478, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_480 = and(UInt<3>("h04"), _T_479) @[axi4_to_ahb.scala 171:15] + node _T_481 = bits(_T_455, 7, 0) @[axi4_to_ahb.scala 172:37] + node _T_482 = eq(_T_481, UInt<8>("h0c0")) @[axi4_to_ahb.scala 172:44] + node _T_483 = bits(_T_482, 0, 0) @[Bitwise.scala 72:15] + node _T_484 = mux(_T_483, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_485 = and(UInt<3>("h06"), _T_484) @[axi4_to_ahb.scala 172:17] + node _T_486 = or(_T_480, _T_485) @[axi4_to_ahb.scala 171:90] + node _T_487 = or(_T_472, _T_486) @[axi4_to_ahb.scala 170:58] + node _T_488 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 325:147] + node _T_489 = mux(_T_453, _T_487, _T_488) @[axi4_to_ahb.scala 325:38] + node _T_490 = cat(master_addr, _T_489) @[Cat.scala 29:58] + buf_addr_in <= _T_490 @[axi4_to_ahb.scala 325:15] + node _T_491 = bits(master_tag, 0, 0) @[axi4_to_ahb.scala 326:27] + buf_tag_in <= _T_491 @[axi4_to_ahb.scala 326:14] + node _T_492 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 327:32] + buf_byteen_in <= _T_492 @[axi4_to_ahb.scala 327:17] + node _T_493 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 328:33] + node _T_494 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 328:59] + node _T_495 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 328:80] + node _T_496 = mux(_T_493, _T_494, _T_495) @[axi4_to_ahb.scala 328:21] + buf_data_in <= _T_496 @[axi4_to_ahb.scala 328:15] + node _T_497 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 329:52] + node _T_498 = eq(_T_497, UInt<2>("h03")) @[axi4_to_ahb.scala 329:59] + node _T_499 = and(buf_aligned_in, _T_498) @[axi4_to_ahb.scala 329:38] + node _T_500 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 329:85] + node _T_501 = eq(_T_500, UInt<1>("h01")) @[axi4_to_ahb.scala 329:92] + node _T_502 = and(_T_499, _T_501) @[axi4_to_ahb.scala 329:72] + node _T_503 = bits(_T_502, 0, 0) @[axi4_to_ahb.scala 329:112] + node _T_504 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 329:144] + wire _T_505 : UInt<8> + _T_505 <= UInt<8>("h00") + node _T_506 = bits(_T_505, 7, 0) @[axi4_to_ahb.scala 161:43] + node _T_507 = eq(_T_506, UInt<8>("h0ff")) @[axi4_to_ahb.scala 161:50] + node _T_508 = bits(_T_507, 0, 0) @[Bitwise.scala 72:15] + node _T_509 = mux(_T_508, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_510 = and(UInt<2>("h03"), _T_509) @[axi4_to_ahb.scala 161:25] + node _T_511 = bits(_T_505, 7, 0) @[axi4_to_ahb.scala 162:34] + node _T_512 = eq(_T_511, UInt<8>("h0f0")) @[axi4_to_ahb.scala 162:41] + node _T_513 = bits(_T_505, 7, 0) @[axi4_to_ahb.scala 162:63] + node _T_514 = eq(_T_513, UInt<4>("h0f")) @[axi4_to_ahb.scala 162:70] + node _T_515 = or(_T_512, _T_514) @[axi4_to_ahb.scala 162:54] + node _T_516 = bits(_T_515, 0, 0) @[Bitwise.scala 72:15] + node _T_517 = mux(_T_516, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_518 = and(UInt<2>("h02"), _T_517) @[axi4_to_ahb.scala 162:16] + node _T_519 = or(_T_510, _T_518) @[axi4_to_ahb.scala 161:65] + node _T_520 = bits(_T_505, 7, 0) @[axi4_to_ahb.scala 163:34] + node _T_521 = eq(_T_520, UInt<8>("h0c0")) @[axi4_to_ahb.scala 163:41] + node _T_522 = bits(_T_505, 7, 0) @[axi4_to_ahb.scala 163:63] + node _T_523 = eq(_T_522, UInt<6>("h030")) @[axi4_to_ahb.scala 163:70] + node _T_524 = or(_T_521, _T_523) @[axi4_to_ahb.scala 163:54] + node _T_525 = bits(_T_505, 7, 0) @[axi4_to_ahb.scala 163:92] + node _T_526 = eq(_T_525, UInt<4>("h0c")) @[axi4_to_ahb.scala 163:99] + node _T_527 = or(_T_524, _T_526) @[axi4_to_ahb.scala 163:83] + node _T_528 = bits(_T_505, 7, 0) @[axi4_to_ahb.scala 163:121] + node _T_529 = eq(_T_528, UInt<2>("h03")) @[axi4_to_ahb.scala 163:128] + node _T_530 = or(_T_527, _T_529) @[axi4_to_ahb.scala 163:112] + node _T_531 = bits(_T_530, 0, 0) @[Bitwise.scala 72:15] + node _T_532 = mux(_T_531, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_533 = and(UInt<1>("h01"), _T_532) @[axi4_to_ahb.scala 163:16] + node _T_534 = or(_T_519, _T_533) @[axi4_to_ahb.scala 162:86] + node _T_535 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 329:164] + node _T_536 = mux(_T_503, _T_534, _T_535) @[axi4_to_ahb.scala 329:21] + buf_size_in <= _T_536 @[axi4_to_ahb.scala 329:15] + node _T_537 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 330:32] + node _T_538 = eq(_T_537, UInt<1>("h00")) @[axi4_to_ahb.scala 330:39] + node _T_539 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 331:17] + node _T_540 = eq(_T_539, UInt<1>("h00")) @[axi4_to_ahb.scala 331:24] + node _T_541 = or(_T_538, _T_540) @[axi4_to_ahb.scala 330:51] + node _T_542 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 331:50] + node _T_543 = eq(_T_542, UInt<1>("h01")) @[axi4_to_ahb.scala 331:57] + node _T_544 = or(_T_541, _T_543) @[axi4_to_ahb.scala 331:36] + node _T_545 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 331:84] + node _T_546 = eq(_T_545, UInt<2>("h02")) @[axi4_to_ahb.scala 331:91] + node _T_547 = or(_T_544, _T_546) @[axi4_to_ahb.scala 331:70] + node _T_548 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 332:18] + node _T_549 = eq(_T_548, UInt<2>("h03")) @[axi4_to_ahb.scala 332:25] + node _T_550 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 332:55] + node _T_551 = eq(_T_550, UInt<2>("h03")) @[axi4_to_ahb.scala 332:62] + node _T_552 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 332:90] + node _T_553 = eq(_T_552, UInt<4>("h0c")) @[axi4_to_ahb.scala 332:97] + node _T_554 = or(_T_551, _T_553) @[axi4_to_ahb.scala 332:74] + node _T_555 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 332:125] + node _T_556 = eq(_T_555, UInt<6>("h030")) @[axi4_to_ahb.scala 332:132] + node _T_557 = or(_T_554, _T_556) @[axi4_to_ahb.scala 332:109] + node _T_558 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 332:161] + node _T_559 = eq(_T_558, UInt<8>("h0c0")) @[axi4_to_ahb.scala 332:168] + node _T_560 = or(_T_557, _T_559) @[axi4_to_ahb.scala 332:145] + node _T_561 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 333:21] + node _T_562 = eq(_T_561, UInt<4>("h0f")) @[axi4_to_ahb.scala 333:28] + node _T_563 = or(_T_560, _T_562) @[axi4_to_ahb.scala 332:181] + node _T_564 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 333:56] + node _T_565 = eq(_T_564, UInt<8>("h0f0")) @[axi4_to_ahb.scala 333:63] + node _T_566 = or(_T_563, _T_565) @[axi4_to_ahb.scala 333:40] + node _T_567 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 333:92] + node _T_568 = eq(_T_567, UInt<8>("h0ff")) @[axi4_to_ahb.scala 333:99] + node _T_569 = or(_T_566, _T_568) @[axi4_to_ahb.scala 333:76] + node _T_570 = and(_T_549, _T_569) @[axi4_to_ahb.scala 332:38] + node _T_571 = or(_T_547, _T_570) @[axi4_to_ahb.scala 331:104] + buf_aligned_in <= _T_571 @[axi4_to_ahb.scala 330:18] + node _T_572 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 335:39] + node _T_573 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 335:58] + node _T_574 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 335:83] + node _T_575 = cat(_T_573, _T_574) @[Cat.scala 29:58] + node _T_576 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 335:104] + node _T_577 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 335:129] + node _T_578 = cat(_T_576, _T_577) @[Cat.scala 29:58] + node _T_579 = mux(_T_572, _T_575, _T_578) @[axi4_to_ahb.scala 335:22] + io.ahb_haddr <= _T_579 @[axi4_to_ahb.scala 335:16] + node _T_580 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 336:39] + node _T_581 = bits(buf_aligned_in, 0, 0) @[Bitwise.scala 72:15] + node _T_582 = mux(_T_581, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_583 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 336:93] + node _T_584 = and(_T_582, _T_583) @[axi4_to_ahb.scala 336:80] + node _T_585 = cat(UInt<1>("h00"), _T_584) @[Cat.scala 29:58] + node _T_586 = bits(buf_aligned, 0, 0) @[Bitwise.scala 72:15] + node _T_587 = mux(_T_586, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_588 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 336:148] + node _T_589 = and(_T_587, _T_588) @[axi4_to_ahb.scala 336:138] + node _T_590 = cat(UInt<1>("h00"), _T_589) @[Cat.scala 29:58] + node _T_591 = mux(_T_580, _T_585, _T_590) @[axi4_to_ahb.scala 336:22] + io.ahb_hsize <= _T_591 @[axi4_to_ahb.scala 336:16] + io.ahb_hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 338:17] + io.ahb_hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 339:20] + node _T_592 = bits(io.axi_arprot, 2, 2) @[axi4_to_ahb.scala 340:47] + node _T_593 = not(_T_592) @[axi4_to_ahb.scala 340:33] + node _T_594 = cat(UInt<1>("h01"), _T_593) @[Cat.scala 29:58] + io.ahb_hprot <= _T_594 @[axi4_to_ahb.scala 340:16] + node _T_595 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 341:40] + node _T_596 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 341:55] + node _T_597 = eq(_T_596, UInt<1>("h01")) @[axi4_to_ahb.scala 341:62] + node _T_598 = mux(_T_595, _T_597, buf_write) @[axi4_to_ahb.scala 341:23] + io.ahb_hwrite <= _T_598 @[axi4_to_ahb.scala 341:17] + node _T_599 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 342:28] + io.ahb_hwdata <= _T_599 @[axi4_to_ahb.scala 342:17] + slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 344:15] + node _T_600 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 345:43] + node _T_601 = mux(_T_600, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 345:23] + node _T_602 = bits(slvbuf_error, 0, 0) @[Bitwise.scala 72:15] + node _T_603 = mux(_T_602, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_604 = and(_T_603, UInt<2>("h02")) @[axi4_to_ahb.scala 345:88] + node _T_605 = cat(_T_601, _T_604) @[Cat.scala 29:58] + slave_opc <= _T_605 @[axi4_to_ahb.scala 345:13] + node _T_606 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 346:41] + node _T_607 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 346:66] + node _T_608 = cat(_T_607, _T_607) @[Cat.scala 29:58] + node _T_609 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 346:91] + node _T_610 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 346:110] + node _T_611 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 346:131] + node _T_612 = mux(_T_609, _T_610, _T_611) @[axi4_to_ahb.scala 346:79] + node _T_613 = mux(_T_606, _T_608, _T_612) @[axi4_to_ahb.scala 346:21] + slave_rdata <= _T_613 @[axi4_to_ahb.scala 346:15] + node _T_614 = bits(slvbuf_tag, 0, 0) @[axi4_to_ahb.scala 347:26] + slave_tag <= _T_614 @[axi4_to_ahb.scala 347:13] + node _T_615 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 349:33] + node _T_616 = neq(_T_615, UInt<1>("h00")) @[axi4_to_ahb.scala 349:40] + node _T_617 = and(_T_616, io.ahb_hready) @[axi4_to_ahb.scala 349:52] + node _T_618 = and(_T_617, io.ahb_hwrite) @[axi4_to_ahb.scala 349:68] + last_addr_en <= _T_618 @[axi4_to_ahb.scala 349:16] + node _T_619 = and(UInt<1>("h01"), wrbuf_rst) @[axi4_to_ahb.scala 352:58] + node _T_620 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 352:114] + reg _T_621 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_620 : @[Reg.scala 28:19] + _T_621 <= _T_619 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + wrbuf_vld <= _T_621 @[axi4_to_ahb.scala 352:18] + node _T_622 = and(UInt<1>("h01"), wrbuf_rst) @[axi4_to_ahb.scala 353:58] + node _T_623 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 353:119] + reg _T_624 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_623 : @[Reg.scala 28:19] + _T_624 <= _T_622 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + wrbuf_data_vld <= _T_624 @[axi4_to_ahb.scala 353:18] + node _T_625 = bits(io.axi_awid, 0, 0) @[axi4_to_ahb.scala 355:57] + node _T_626 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 355:91] + reg _T_627 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_626 : @[Reg.scala 28:19] + _T_627 <= _T_625 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + wrbuf_tag <= _T_627 @[axi4_to_ahb.scala 355:13] + node _T_628 = bits(io.axi_awsize, 2, 0) @[axi4_to_ahb.scala 356:60] + node _T_629 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 356:88] + reg _T_630 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_629 : @[Reg.scala 28:19] + _T_630 <= _T_628 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + wrbuf_size <= _T_630 @[axi4_to_ahb.scala 356:14] + node _T_631 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 358:62] + reg _T_632 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_631 : @[Reg.scala 28:19] + _T_632 <= io.axi_awaddr @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + wrbuf_addr <= _T_632 @[axi4_to_ahb.scala 358:14] + node _T_633 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 359:66] + reg _T_634 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_633 : @[Reg.scala 28:19] + _T_634 <= io.axi_wdata @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + wrbuf_data <= _T_634 @[axi4_to_ahb.scala 359:14] + node _T_635 = bits(io.axi_wstrb, 7, 0) @[axi4_to_ahb.scala 362:27] + node _T_636 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 362:60] + reg _T_637 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_636 : @[Reg.scala 28:19] + _T_637 <= _T_635 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + wrbuf_byteen <= _T_637 @[axi4_to_ahb.scala 361:16] + node _T_638 = bits(io.ahb_haddr, 31, 0) @[axi4_to_ahb.scala 365:27] + node _T_639 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 365:60] + reg _T_640 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_639 : @[Reg.scala 28:19] + _T_640 <= _T_638 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + last_bus_addr <= _T_640 @[axi4_to_ahb.scala 364:17] + node _T_641 = bits(buf_rst, 0, 0) @[Bitwise.scala 72:15] + node _T_642 = mux(_T_641, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_643 = and(buf_nxtstate, _T_642) @[axi4_to_ahb.scala 369:28] + node _T_644 = bits(buf_state_en, 0, 0) @[axi4_to_ahb.scala 369:92] + reg _T_645 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_644 : @[Reg.scala 28:19] + _T_645 <= _T_643 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_state <= _T_645 @[axi4_to_ahb.scala 368:13] + node _T_646 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 373:50] + reg _T_647 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_646 : @[Reg.scala 28:19] + _T_647 <= buf_write_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_write <= _T_647 @[axi4_to_ahb.scala 372:13] + node _T_648 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 376:25] + node _T_649 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 376:60] + reg _T_650 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_649 : @[Reg.scala 28:19] + _T_650 <= _T_648 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_tag <= _T_650 @[axi4_to_ahb.scala 375:11] + node _T_651 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 379:36] + node _T_652 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 379:61] + node _T_653 = bits(_T_652, 0, 0) @[axi4_to_ahb.scala 379:78] + reg _T_654 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_653 : @[Reg.scala 28:19] + _T_654 <= _T_651 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_addr <= _T_654 @[axi4_to_ahb.scala 379:12] + node _T_655 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 382:23] + node _T_656 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 382:52] + reg _T_657 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_656 : @[Reg.scala 28:19] + _T_657 <= _T_655 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_size <= _T_657 @[axi4_to_ahb.scala 381:12] + node _T_658 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 385:52] + reg _T_659 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_658 : @[Reg.scala 28:19] + _T_659 <= buf_aligned_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_aligned <= _T_659 @[axi4_to_ahb.scala 384:15] + node _T_660 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 388:25] + node _T_661 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 388:54] + reg _T_662 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_661 : @[Reg.scala 28:19] + _T_662 <= _T_660 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_byteen <= _T_662 @[axi4_to_ahb.scala 387:14] + node _T_663 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 391:36] + node _T_664 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 391:66] + node _T_665 = bits(_T_664, 0, 0) @[axi4_to_ahb.scala 391:89] + reg _T_666 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_665 : @[Reg.scala 28:19] + _T_666 <= _T_663 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_data <= _T_666 @[axi4_to_ahb.scala 391:12] + node _T_667 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 394:50] + reg _T_668 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_667 : @[Reg.scala 28:19] + _T_668 <= buf_write @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + slvbuf_write <= _T_668 @[axi4_to_ahb.scala 393:16] + node _T_669 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 397:22] + node _T_670 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 397:60] + reg _T_671 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_670 : @[Reg.scala 28:19] + _T_671 <= _T_669 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + slvbuf_tag <= _T_671 @[axi4_to_ahb.scala 396:14] + node _T_672 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 400:59] + reg _T_673 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_672 : @[Reg.scala 28:19] + _T_673 <= slvbuf_error_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + slvbuf_error <= _T_673 @[axi4_to_ahb.scala 399:16] + node _T_674 = and(UInt<1>("h01"), cmd_done_rst) @[axi4_to_ahb.scala 404:22] + node _T_675 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 404:81] + reg _T_676 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_675 : @[Reg.scala 28:19] + _T_676 <= _T_674 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + cmd_doneQ <= _T_676 @[axi4_to_ahb.scala 403:13] + node _T_677 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 408:31] + node _T_678 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 408:70] + reg _T_679 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_678 : @[Reg.scala 28:19] + _T_679 <= _T_677 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_cmd_byte_ptrQ <= _T_679 @[axi4_to_ahb.scala 407:21] + reg _T_680 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 413:12] + _T_680 <= io.ahb_hready @[axi4_to_ahb.scala 413:12] + ahb_hready_q <= _T_680 @[axi4_to_ahb.scala 412:16] + node _T_681 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 416:26] + reg _T_682 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 416:12] + _T_682 <= _T_681 @[axi4_to_ahb.scala 416:12] + ahb_htrans_q <= _T_682 @[axi4_to_ahb.scala 415:16] + reg _T_683 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 419:12] + _T_683 <= io.ahb_hwrite @[axi4_to_ahb.scala 419:12] + ahb_hwrite_q <= _T_683 @[axi4_to_ahb.scala 418:16] + reg _T_684 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 422:12] + _T_684 <= io.ahb_hresp @[axi4_to_ahb.scala 422:12] + ahb_hresp_q <= _T_684 @[axi4_to_ahb.scala 421:15] + node _T_685 = bits(io.ahb_hrdata, 63, 0) @[axi4_to_ahb.scala 425:26] + reg _T_686 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 425:12] + _T_686 <= _T_685 @[axi4_to_ahb.scala 425:12] + ahb_hrdata_q <= _T_686 @[axi4_to_ahb.scala 424:16] + node _T_687 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 428:43] + node _T_688 = or(_T_687, io.clk_override) @[axi4_to_ahb.scala 428:58] + node _T_689 = and(io.bus_clk_en, _T_688) @[axi4_to_ahb.scala 428:30] + buf_clken <= _T_689 @[axi4_to_ahb.scala 428:13] + node _T_690 = bits(io.ahb_htrans, 1, 1) @[axi4_to_ahb.scala 429:69] + node _T_691 = and(io.ahb_hready, _T_690) @[axi4_to_ahb.scala 429:54] + node _T_692 = or(_T_691, io.clk_override) @[axi4_to_ahb.scala 429:74] + node _T_693 = and(io.bus_clk_en, _T_692) @[axi4_to_ahb.scala 429:36] + ahbm_addr_clken <= _T_693 @[axi4_to_ahb.scala 429:19] + node _T_694 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 430:50] + node _T_695 = or(_T_694, io.clk_override) @[axi4_to_ahb.scala 430:60] + node _T_696 = and(io.bus_clk_en, _T_695) @[axi4_to_ahb.scala 430:36] + ahbm_data_clken <= _T_696 @[axi4_to_ahb.scala 430:19] + inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 483:22] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_2.io.en <= buf_clken @[el2_lib.scala 485:16] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + buf_clk <= rvclkhdr_2.io.l1clk @[axi4_to_ahb.scala 433:11] + inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 483:22] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_3.io.en <= io.bus_clk_en @[el2_lib.scala 485:16] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + ahbm_clk <= rvclkhdr_3.io.l1clk @[axi4_to_ahb.scala 434:12] + inst rvclkhdr_4 of rvclkhdr_4 @[el2_lib.scala 483:22] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= reset + rvclkhdr_4.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_4.io.en <= ahbm_addr_clken @[el2_lib.scala 485:16] + rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + ahbm_addr_clk <= rvclkhdr_4.io.l1clk @[axi4_to_ahb.scala 435:17] + inst rvclkhdr_5 of rvclkhdr_5 @[el2_lib.scala 483:22] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= reset + rvclkhdr_5.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_5.io.en <= ahbm_data_clken @[el2_lib.scala 485:16] + rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + ahbm_data_clk <= rvclkhdr_5.io.l1clk @[axi4_to_ahb.scala 436:17] + diff --git a/axi4_to_ahb.v b/axi4_to_ahb.v new file mode 100644 index 00000000..0588d437 --- /dev/null +++ b/axi4_to_ahb.v @@ -0,0 +1,438 @@ +module rvclkhdr( + output io_l1clk, + input io_clk, + input io_en, + input io_scan_mode +); + wire clkhdr_Q; // @[el2_lib.scala 474:26] + wire clkhdr_CK; // @[el2_lib.scala 474:26] + wire clkhdr_EN; // @[el2_lib.scala 474:26] + wire clkhdr_SE; // @[el2_lib.scala 474:26] + gated_latch clkhdr ( // @[el2_lib.scala 474:26] + .Q(clkhdr_Q), + .CK(clkhdr_CK), + .EN(clkhdr_EN), + .SE(clkhdr_SE) + ); + assign io_l1clk = clkhdr_Q; // @[el2_lib.scala 475:14] + assign clkhdr_CK = io_clk; // @[el2_lib.scala 476:18] + assign clkhdr_EN = io_en; // @[el2_lib.scala 477:18] + assign clkhdr_SE = io_scan_mode; // @[el2_lib.scala 478:18] +endmodule +module axi4_to_ahb( + input clock, + input reset, + input io_scan_mode, + input io_bus_clk_en, + input io_clk_override, + input io_axi_awvalid, + input io_axi_awid, + input [31:0] io_axi_awaddr, + input [2:0] io_axi_awsize, + input [2:0] io_axi_awprot, + input io_axi_wvalid, + input [63:0] io_axi_wdata, + input [7:0] io_axi_wstrb, + input io_axi_wlast, + input io_axi_bready, + input io_axi_arvalid, + input io_axi_arid, + input [31:0] io_axi_araddr, + input [2:0] io_axi_arsize, + input [2:0] io_axi_arprot, + input io_axi_rready, + input [63:0] io_ahb_hrdata, + input io_ahb_hready, + input io_ahb_hresp, + output io_axi_awready, + output io_axi_wready, + output io_axi_bvalid, + output [1:0] io_axi_bresp, + output io_axi_bid, + output io_axi_arready, + output io_axi_rvalid, + output io_axi_rid, + output [31:0] io_axi_rdata, + output [1:0] io_axi_rresp, + output io_axi_rlast, + output [31:0] io_ahb_haddr, + output [2:0] io_ahb_hburst, + output io_ahb_hmastlock, + output [3:0] io_ahb_hprot, + output [2:0] io_ahb_hsize, + output [1:0] io_ahb_htrans, + output io_ahb_hwrite, + output [63:0] io_ahb_hwdata +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [63:0] _RAND_6; + reg [63:0] _RAND_7; + reg [63:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; +`endif // RANDOMIZE_REG_INIT + wire rvclkhdr_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_1_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_1_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_2_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_2_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_3_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_3_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_4_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_4_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_5_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_5_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 483:22] + reg [2:0] buf_nxtstate; // @[axi4_to_ahb.scala 63:29] + wire wrbuf_en = io_axi_awvalid & io_axi_awready; // @[axi4_to_ahb.scala 183:30] + wire bus_clk = rvclkhdr_io_l1clk; // @[axi4_to_ahb.scala 83:21 axi4_to_ahb.scala 216:11] + reg wrbuf_vld; // @[Reg.scala 27:20] + reg wrbuf_data_vld; // @[Reg.scala 27:20] + wire wr_cmd_vld = wrbuf_vld & wrbuf_data_vld; // @[axi4_to_ahb.scala 193:27] + wire master_valid = wr_cmd_vld | io_axi_arvalid; // @[axi4_to_ahb.scala 194:30] + wire [1:0] _T_28 = wr_cmd_vld ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 196:20] + wire [2:0] master_opc = {{1'd0}, _T_28}; // @[axi4_to_ahb.scala 196:14] + wire _T_149 = master_opc[2:1] == 2'h1; // @[axi4_to_ahb.scala 252:89] + wire _T_150 = master_valid & _T_149; // @[axi4_to_ahb.scala 252:70] + wire _T_151 = ~_T_150; // @[axi4_to_ahb.scala 252:55] + wire wrbuf_data_en = io_axi_wvalid & io_axi_wready; // @[axi4_to_ahb.scala 184:34] + wire _T_8 = ~wrbuf_en; // @[axi4_to_ahb.scala 186:33] + wire wrbuf_rst = _T_150 & _T_8; // @[axi4_to_ahb.scala 186:31] + wire _T_11 = wrbuf_vld & _T_151; // @[axi4_to_ahb.scala 188:33] + wire _T_15 = wrbuf_data_vld & _T_151; // @[axi4_to_ahb.scala 189:37] + reg [31:0] wrbuf_addr; // @[Reg.scala 27:20] + wire [31:0] master_addr = wr_cmd_vld ? wrbuf_addr : io_axi_araddr; // @[axi4_to_ahb.scala 197:21] + reg [2:0] wrbuf_size; // @[Reg.scala 27:20] + wire [2:0] master_size = wr_cmd_vld ? wrbuf_size : io_axi_arsize; // @[axi4_to_ahb.scala 198:21] + reg [7:0] wrbuf_byteen; // @[Reg.scala 27:20] + reg [63:0] wrbuf_data; // @[Reg.scala 27:20] + wire buf_clk = rvclkhdr_2_io_l1clk; // @[axi4_to_ahb.scala 151:21 axi4_to_ahb.scala 433:11] + reg [63:0] buf_data; // @[Reg.scala 27:20] + wire ahbm_data_clk = rvclkhdr_5_io_l1clk; // @[axi4_to_ahb.scala 155:27 axi4_to_ahb.scala 436:17] + reg [63:0] ahb_hrdata_q; // @[axi4_to_ahb.scala 425:12] + wire _T_60 = wrbuf_en | wrbuf_data_en; // @[axi4_to_ahb.scala 214:74] + wire _T_69 = buf_nxtstate == 3'h2; // @[axi4_to_ahb.scala 230:54] + wire buf_data_wr_en = master_valid & _T_69; // @[axi4_to_ahb.scala 230:38] + wire [2:0] _T_100 = wrbuf_byteen[7] ? 3'h7 : 3'h0; // @[Mux.scala 98:16] + wire [2:0] _T_101 = wrbuf_byteen[6] ? 3'h6 : _T_100; // @[Mux.scala 98:16] + wire [2:0] _T_102 = wrbuf_byteen[5] ? 3'h5 : _T_101; // @[Mux.scala 98:16] + wire [2:0] _T_103 = wrbuf_byteen[4] ? 3'h4 : _T_102; // @[Mux.scala 98:16] + wire [2:0] _T_104 = wrbuf_byteen[3] ? 3'h3 : _T_103; // @[Mux.scala 98:16] + wire [2:0] _T_105 = wrbuf_byteen[2] ? 3'h2 : _T_104; // @[Mux.scala 98:16] + wire [2:0] _T_106 = wrbuf_byteen[1] ? 3'h1 : _T_105; // @[Mux.scala 98:16] + wire [2:0] _T_107 = wrbuf_byteen[0] ? 3'h0 : _T_106; // @[Mux.scala 98:16] + wire [2:0] buf_cmd_byte_ptr = _T_149 ? _T_107 : master_addr[2:0]; // @[axi4_to_ahb.scala 233:30] + wire [1:0] _T_113 = master_valid ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire _T_117 = master_opc == 3'h0; // @[axi4_to_ahb.scala 240:61] + reg [31:0] buf_addr; // @[Reg.scala 27:20] + wire _T_540 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 331:24] + wire _T_541 = _T_117 | _T_540; // @[axi4_to_ahb.scala 330:51] + wire _T_543 = master_size[1:0] == 2'h1; // @[axi4_to_ahb.scala 331:57] + wire _T_544 = _T_541 | _T_543; // @[axi4_to_ahb.scala 331:36] + wire _T_546 = master_size[1:0] == 2'h2; // @[axi4_to_ahb.scala 331:91] + wire _T_547 = _T_544 | _T_546; // @[axi4_to_ahb.scala 331:70] + wire _T_549 = master_size[1:0] == 2'h3; // @[axi4_to_ahb.scala 332:25] + wire _T_551 = wrbuf_byteen == 8'h3; // @[axi4_to_ahb.scala 332:62] + wire _T_553 = wrbuf_byteen == 8'hc; // @[axi4_to_ahb.scala 332:97] + wire _T_554 = _T_551 | _T_553; // @[axi4_to_ahb.scala 332:74] + wire _T_556 = wrbuf_byteen == 8'h30; // @[axi4_to_ahb.scala 332:132] + wire _T_557 = _T_554 | _T_556; // @[axi4_to_ahb.scala 332:109] + wire _T_559 = wrbuf_byteen == 8'hc0; // @[axi4_to_ahb.scala 332:168] + wire _T_560 = _T_557 | _T_559; // @[axi4_to_ahb.scala 332:145] + wire _T_562 = wrbuf_byteen == 8'hf; // @[axi4_to_ahb.scala 333:28] + wire _T_563 = _T_560 | _T_562; // @[axi4_to_ahb.scala 332:181] + wire _T_565 = wrbuf_byteen == 8'hf0; // @[axi4_to_ahb.scala 333:63] + wire _T_566 = _T_563 | _T_565; // @[axi4_to_ahb.scala 333:40] + wire _T_568 = wrbuf_byteen == 8'hff; // @[axi4_to_ahb.scala 333:99] + wire _T_569 = _T_566 | _T_568; // @[axi4_to_ahb.scala 333:76] + wire _T_570 = _T_549 & _T_569; // @[axi4_to_ahb.scala 332:38] + wire buf_aligned_in = _T_547 | _T_570; // @[axi4_to_ahb.scala 331:104] + wire _T_452 = buf_aligned_in & _T_149; // @[axi4_to_ahb.scala 325:55] + wire [2:0] _T_489 = _T_452 ? 3'h0 : master_addr[2:0]; // @[axi4_to_ahb.scala 325:38] + wire [34:0] _T_490 = {master_addr,_T_489}; // @[Cat.scala 29:58] + wire _T_499 = buf_aligned_in & _T_549; // @[axi4_to_ahb.scala 329:38] + wire _T_502 = _T_499 & _T_149; // @[axi4_to_ahb.scala 329:72] + wire [1:0] _T_536 = _T_502 ? 2'h0 : master_size[1:0]; // @[axi4_to_ahb.scala 329:21] + wire [31:0] _T_575 = {master_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] + wire [31:0] _T_578 = {buf_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] + wire [1:0] _T_582 = buf_aligned_in ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [2:0] buf_size_in = {{1'd0}, _T_536}; // @[axi4_to_ahb.scala 329:15] + wire [1:0] _T_584 = _T_582 & buf_size_in[1:0]; // @[axi4_to_ahb.scala 336:80] + wire [2:0] _T_585 = {1'h0,_T_584}; // @[Cat.scala 29:58] + wire _T_593 = ~io_axi_arprot[2]; // @[axi4_to_ahb.scala 340:33] + wire [1:0] _T_594 = {1'h1,_T_593}; // @[Cat.scala 29:58] + reg buf_write; // @[Reg.scala 27:20] + wire [31:0] buf_addr_in = _T_490[31:0]; // @[axi4_to_ahb.scala 325:15] + wire _T_652 = master_valid & io_bus_clk_en; // @[axi4_to_ahb.scala 379:61] + wire _T_664 = buf_data_wr_en & io_bus_clk_en; // @[axi4_to_ahb.scala 391:66] + wire _T_688 = master_valid | io_clk_override; // @[axi4_to_ahb.scala 428:58] + wire _T_691 = io_ahb_hready & io_ahb_htrans[1]; // @[axi4_to_ahb.scala 429:54] + wire _T_692 = _T_691 | io_clk_override; // @[axi4_to_ahb.scala 429:74] + rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_io_l1clk), + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en), + .io_scan_mode(rvclkhdr_io_scan_mode) + ); + rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_1_io_l1clk), + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en), + .io_scan_mode(rvclkhdr_1_io_scan_mode) + ); + rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_2_io_l1clk), + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en), + .io_scan_mode(rvclkhdr_2_io_scan_mode) + ); + rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_3_io_l1clk), + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en), + .io_scan_mode(rvclkhdr_3_io_scan_mode) + ); + rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_4_io_l1clk), + .io_clk(rvclkhdr_4_io_clk), + .io_en(rvclkhdr_4_io_en), + .io_scan_mode(rvclkhdr_4_io_scan_mode) + ); + rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_5_io_l1clk), + .io_clk(rvclkhdr_5_io_clk), + .io_en(rvclkhdr_5_io_en), + .io_scan_mode(rvclkhdr_5_io_scan_mode) + ); + assign io_axi_awready = ~_T_11; // @[axi4_to_ahb.scala 188:18] + assign io_axi_wready = ~_T_15; // @[axi4_to_ahb.scala 189:17] + assign io_axi_bvalid = 1'h0; // @[axi4_to_ahb.scala 203:17] + assign io_axi_bresp = 2'h0; // @[axi4_to_ahb.scala 204:16] + assign io_axi_bid = 1'h0; // @[axi4_to_ahb.scala 205:14] + assign io_axi_arready = ~wr_cmd_vld; // @[axi4_to_ahb.scala 190:18] + assign io_axi_rvalid = 1'h0; // @[axi4_to_ahb.scala 207:17] + assign io_axi_rid = 1'h0; // @[axi4_to_ahb.scala 209:14] + assign io_axi_rdata = ahb_hrdata_q[31:0]; // @[axi4_to_ahb.scala 210:16] + assign io_axi_rresp = 2'h0; // @[axi4_to_ahb.scala 208:16] + assign io_axi_rlast = 1'h1; // @[axi4_to_ahb.scala 191:16] + assign io_ahb_haddr = master_valid ? _T_575 : _T_578; // @[axi4_to_ahb.scala 335:16] + assign io_ahb_hburst = 3'h0; // @[axi4_to_ahb.scala 338:17] + assign io_ahb_hmastlock = 1'h0; // @[axi4_to_ahb.scala 339:20] + assign io_ahb_hprot = {{2'd0}, _T_594}; // @[axi4_to_ahb.scala 340:16] + assign io_ahb_hsize = master_valid ? _T_585 : 3'h0; // @[axi4_to_ahb.scala 336:16] + assign io_ahb_htrans = _T_113 & 2'h2; // @[axi4_to_ahb.scala 220:17 axi4_to_ahb.scala 236:21 axi4_to_ahb.scala 248:21 axi4_to_ahb.scala 263:21 axi4_to_ahb.scala 273:21 axi4_to_ahb.scala 293:21 axi4_to_ahb.scala 307:21] + assign io_ahb_hwrite = master_valid ? _T_149 : buf_write; // @[axi4_to_ahb.scala 341:17] + assign io_ahb_hwdata = buf_data; // @[axi4_to_ahb.scala 342:17] + assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_io_en = io_bus_clk_en; // @[el2_lib.scala 485:16] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_1_io_en = io_bus_clk_en & _T_60; // @[el2_lib.scala 485:16] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_2_io_en = io_bus_clk_en & _T_688; // @[el2_lib.scala 485:16] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_3_io_en = io_bus_clk_en; // @[el2_lib.scala 485:16] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_4_io_en = io_bus_clk_en & _T_692; // @[el2_lib.scala 485:16] + assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_5_io_en = io_bus_clk_en & io_clk_override; // @[el2_lib.scala 485:16] + assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + buf_nxtstate = _RAND_0[2:0]; + _RAND_1 = {1{`RANDOM}}; + wrbuf_vld = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + wrbuf_data_vld = _RAND_2[0:0]; + _RAND_3 = {1{`RANDOM}}; + wrbuf_addr = _RAND_3[31:0]; + _RAND_4 = {1{`RANDOM}}; + wrbuf_size = _RAND_4[2:0]; + _RAND_5 = {1{`RANDOM}}; + wrbuf_byteen = _RAND_5[7:0]; + _RAND_6 = {2{`RANDOM}}; + wrbuf_data = _RAND_6[63:0]; + _RAND_7 = {2{`RANDOM}}; + buf_data = _RAND_7[63:0]; + _RAND_8 = {2{`RANDOM}}; + ahb_hrdata_q = _RAND_8[63:0]; + _RAND_9 = {1{`RANDOM}}; + buf_addr = _RAND_9[31:0]; + _RAND_10 = {1{`RANDOM}}; + buf_write = _RAND_10[0:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + buf_nxtstate = 3'h0; + end + if (reset) begin + wrbuf_vld = 1'h0; + end + if (reset) begin + wrbuf_data_vld = 1'h0; + end + if (reset) begin + wrbuf_addr = 32'h0; + end + if (reset) begin + wrbuf_size = 3'h0; + end + if (reset) begin + wrbuf_byteen = 8'h0; + end + if (reset) begin + wrbuf_data = 64'h0; + end + if (reset) begin + buf_data = 64'h0; + end + if (reset) begin + ahb_hrdata_q = 64'h0; + end + if (reset) begin + buf_addr = 32'h0; + end + if (reset) begin + buf_write = 1'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge clock or posedge reset) begin + if (reset) begin + buf_nxtstate <= 3'h0; + end else if (_T_149) begin + buf_nxtstate <= 3'h2; + end else begin + buf_nxtstate <= 3'h1; + end + end + always @(posedge bus_clk or posedge reset) begin + if (reset) begin + wrbuf_vld <= 1'h0; + end else if (wrbuf_en) begin + wrbuf_vld <= wrbuf_rst; + end + end + always @(posedge bus_clk or posedge reset) begin + if (reset) begin + wrbuf_data_vld <= 1'h0; + end else if (wrbuf_data_en) begin + wrbuf_data_vld <= wrbuf_rst; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + wrbuf_addr <= 32'h0; + end else if (wrbuf_en) begin + wrbuf_addr <= io_axi_awaddr; + end + end + always @(posedge bus_clk or posedge reset) begin + if (reset) begin + wrbuf_size <= 3'h0; + end else if (wrbuf_en) begin + wrbuf_size <= io_axi_awsize; + end + end + always @(posedge bus_clk or posedge reset) begin + if (reset) begin + wrbuf_byteen <= 8'h0; + end else if (wrbuf_data_en) begin + wrbuf_byteen <= io_axi_wstrb; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + wrbuf_data <= 64'h0; + end else if (wrbuf_data_en) begin + wrbuf_data <= io_axi_wdata; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + buf_data <= 64'h0; + end else if (_T_664) begin + buf_data <= wrbuf_data; + end + end + always @(posedge ahbm_data_clk or posedge reset) begin + if (reset) begin + ahb_hrdata_q <= 64'h0; + end else begin + ahb_hrdata_q <= io_ahb_hrdata; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + buf_addr <= 32'h0; + end else if (_T_652) begin + buf_addr <= buf_addr_in; + end + end + always @(posedge buf_clk or posedge reset) begin + if (reset) begin + buf_write <= 1'h0; + end else if (master_valid) begin + buf_write <= _T_149; + end + end +endmodule diff --git a/el2_dbg.anno.json b/el2_dbg.anno.json new file mode 100644 index 00000000..ea547771 --- /dev/null +++ b/el2_dbg.anno.json @@ -0,0 +1,51 @@ +[ + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dbg|el2_dbg>io_dbg_cmd_valid", + "sources":[ + "~el2_dbg|el2_dbg>io_dma_dbg_ready" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dbg|el2_dbg>io_dbg_resume_req", + "sources":[ + "~el2_dbg|el2_dbg>io_dec_tlu_mpc_halted_only", + "~el2_dbg|el2_dbg>io_dec_tlu_debug_mode", + "~el2_dbg|el2_dbg>io_dbg_cmd_valid", + "~el2_dbg|el2_dbg>io_core_dbg_cmd_done", + "~el2_dbg|el2_dbg>io_dmi_reg_wr_en", + "~el2_dbg|el2_dbg>io_dmi_reg_en", + "~el2_dbg|el2_dbg>io_dma_dbg_ready", + "~el2_dbg|el2_dbg>io_dmi_reg_addr", + "~el2_dbg|el2_dbg>reset" + ] + }, + { + "class":"logger.LogLevelAnnotation", + "globalLogLevel":{ + + } + }, + { + "class":"firrtl.EmitCircuitAnnotation", + "emitter":"firrtl.VerilogEmitter" + }, + { + "class":"firrtl.transforms.BlackBoxResourceAnno", + "target":"el2_dbg.gated_latch", + "resourceId":"/vsrc/gated_latch.v" + }, + { + "class":"firrtl.options.TargetDirAnnotation", + "directory":"." + }, + { + "class":"firrtl.options.OutputAnnotationFileAnnotation", + "file":"el2_dbg" + }, + { + "class":"firrtl.transforms.BlackBoxTargetDirAnno", + "targetDir":"." + } +] \ No newline at end of file diff --git a/el2_dbg.fir b/el2_dbg.fir new file mode 100644 index 00000000..0996fc93 --- /dev/null +++ b/el2_dbg.fir @@ -0,0 +1,1334 @@ +;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 +circuit el2_dbg : + extmodule gated_latch : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_1 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_1 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_1 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_2 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_2 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_2 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_3 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_3 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_3 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_4 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_4 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_4 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_5 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_5 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_5 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_6 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_6 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_6 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_7 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_7 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_7 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + module el2_dbg : + input clock : Clock + input reset : AsyncReset + output io : {dbg_cmd_addr : UInt<32>, dbg_cmd_wrdata : UInt<32>, dbg_cmd_valid : UInt<1>, dbg_cmd_write : UInt<1>, dbg_cmd_type : UInt<2>, dbg_cmd_size : UInt<2>, dbg_core_rst_l : UInt<1>, flip core_dbg_rddata : UInt<32>, flip core_dbg_cmd_done : UInt<1>, flip core_dbg_cmd_fail : UInt<1>, dbg_dma_bubble : UInt<1>, flip dma_dbg_ready : UInt<1>, dbg_halt_req : UInt<1>, dbg_resume_req : UInt<1>, flip dec_tlu_debug_mode : UInt<1>, flip dec_tlu_dbg_halted : UInt<1>, flip dec_tlu_mpc_halted_only : UInt<1>, flip dec_tlu_resume_ack : UInt<1>, flip dmi_reg_en : UInt<1>, flip dmi_reg_addr : UInt<7>, flip dmi_reg_wr_en : UInt<1>, flip dmi_reg_wdata : UInt<32>, dmi_reg_rdata : UInt<32>, sb_axi_awvalid : UInt<1>, flip sb_axi_awready : UInt<1>, sb_axi_awid : UInt<1>, sb_axi_awaddr : UInt<32>, sb_axi_awregion : UInt<4>, sb_axi_awlen : UInt<8>, sb_axi_awsize : UInt<3>, sb_axi_awburst : UInt<2>, sb_axi_awlock : UInt<1>, sb_axi_awcache : UInt<4>, sb_axi_awprot : UInt<3>, sb_axi_awqos : UInt<4>, sb_axi_wvalid : UInt<1>, flip sb_axi_wready : UInt<1>, sb_axi_wdata : UInt<64>, sb_axi_wstrb : UInt<8>, sb_axi_wlast : UInt<1>, flip sb_axi_bvalid : UInt<1>, sb_axi_bready : UInt<1>, flip sb_axi_bresp : UInt<2>, sb_axi_arvalid : UInt<1>, flip sb_axi_arready : UInt<1>, sb_axi_arid : UInt<1>, sb_axi_araddr : UInt<32>, sb_axi_arregion : UInt<4>, sb_axi_arlen : UInt<8>, sb_axi_arsize : UInt<3>, sb_axi_arburst : UInt<2>, sb_axi_arlock : UInt<1>, sb_axi_arcache : UInt<4>, sb_axi_arprot : UInt<3>, sb_axi_arqos : UInt<4>, flip sb_axi_rvalid : UInt<1>, sb_axi_rready : UInt<1>, flip sb_axi_rdata : UInt<64>, flip sb_axi_rresp : UInt<2>, flip dbg_bus_clk_en : UInt<1>, flip dbg_rst_l : AsyncReset, flip clk_override : UInt<1>, flip scan_mode : UInt<1>} + + wire dbg_state : UInt<3> + dbg_state <= UInt<3>("h00") + wire dbg_state_en : UInt<1> + dbg_state_en <= UInt<1>("h00") + wire sb_state : UInt<4> + sb_state <= UInt<4>("h00") + wire sb_state_en : UInt<1> + sb_state_en <= UInt<1>("h00") + wire dmcontrol_reg : UInt<32> + dmcontrol_reg <= UInt<32>("h00") + wire sbaddress0_reg : UInt<32> + sbaddress0_reg <= UInt<32>("h00") + wire sbcs_sbbusy_wren : UInt<1> + sbcs_sbbusy_wren <= UInt<1>("h00") + wire sbcs_sberror_wren : UInt<1> + sbcs_sberror_wren <= UInt<1>("h00") + wire sb_bus_rdata : UInt<64> + sb_bus_rdata <= UInt<64>("h00") + wire sbaddress0_reg_wren1 : UInt<1> + sbaddress0_reg_wren1 <= UInt<1>("h00") + wire dmstatus_reg : UInt<32> + dmstatus_reg <= UInt<32>("h00") + wire dmstatus_havereset : UInt<1> + dmstatus_havereset <= UInt<1>("h00") + wire dmstatus_resumeack : UInt<1> + dmstatus_resumeack <= UInt<1>("h00") + wire dmstatus_unavail : UInt<1> + dmstatus_unavail <= UInt<1>("h00") + wire dmstatus_running : UInt<1> + dmstatus_running <= UInt<1>("h00") + wire dmstatus_halted : UInt<1> + dmstatus_halted <= UInt<1>("h00") + wire abstractcs_busy_wren : UInt<1> + abstractcs_busy_wren <= UInt<1>("h00") + wire abstractcs_busy_din : UInt<1> + abstractcs_busy_din <= UInt<1>("h00") + wire sb_bus_cmd_read : UInt<1> + sb_bus_cmd_read <= UInt<1>("h00") + wire sb_bus_cmd_write_addr : UInt<1> + sb_bus_cmd_write_addr <= UInt<1>("h00") + wire sb_bus_cmd_write_data : UInt<1> + sb_bus_cmd_write_data <= UInt<1>("h00") + wire sb_bus_rsp_read : UInt<1> + sb_bus_rsp_read <= UInt<1>("h00") + wire sb_bus_rsp_error : UInt<1> + sb_bus_rsp_error <= UInt<1>("h00") + wire sb_bus_rsp_write : UInt<1> + sb_bus_rsp_write <= UInt<1>("h00") + wire sbcs_sbbusy_din : UInt<1> + sbcs_sbbusy_din <= UInt<1>("h00") + wire sbcs_sberror_din : UInt<3> + sbcs_sberror_din <= UInt<3>("h00") + wire data1_reg : UInt<32> + data1_reg <= UInt<32>("h00") + wire sbcs_reg : UInt<32> + sbcs_reg <= UInt<32>("h00") + node _T = neq(dbg_state, UInt<3>("h00")) @[el2_dbg.scala 126:51] + node _T_1 = or(io.dmi_reg_en, _T) @[el2_dbg.scala 126:38] + node _T_2 = or(_T_1, dbg_state_en) @[el2_dbg.scala 126:69] + node _T_3 = or(_T_2, io.dec_tlu_dbg_halted) @[el2_dbg.scala 126:84] + node dbg_free_clken = or(_T_3, io.clk_override) @[el2_dbg.scala 126:108] + node _T_4 = or(io.dmi_reg_en, sb_state_en) @[el2_dbg.scala 127:37] + node _T_5 = neq(sb_state, UInt<4>("h00")) @[el2_dbg.scala 127:63] + node _T_6 = or(_T_4, _T_5) @[el2_dbg.scala 127:51] + node sb_free_clken = or(_T_6, io.clk_override) @[el2_dbg.scala 127:86] + inst rvclkhdr of rvclkhdr @[el2_lib.scala 483:22] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr.io.en <= dbg_free_clken @[el2_lib.scala 485:16] + rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 483:22] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_1.io.en <= sb_free_clken @[el2_lib.scala 485:16] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + node _T_7 = asUInt(io.dbg_rst_l) @[el2_dbg.scala 130:42] + node _T_8 = bits(dmcontrol_reg, 0, 0) @[el2_dbg.scala 130:61] + node _T_9 = or(_T_8, io.scan_mode) @[el2_dbg.scala 130:65] + node _T_10 = and(_T_7, _T_9) @[el2_dbg.scala 130:45] + node dbg_dm_rst_l = asAsyncReset(_T_10) @[el2_dbg.scala 130:94] + node _T_11 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 131:39] + node _T_12 = eq(_T_11, UInt<1>("h00")) @[el2_dbg.scala 131:25] + node _T_13 = bits(_T_12, 0, 0) @[el2_dbg.scala 131:50] + io.dbg_core_rst_l <= _T_13 @[el2_dbg.scala 131:21] + node _T_14 = eq(io.dmi_reg_addr, UInt<6>("h038")) @[el2_dbg.scala 132:36] + node _T_15 = and(_T_14, io.dmi_reg_en) @[el2_dbg.scala 132:49] + node _T_16 = and(_T_15, io.dmi_reg_wr_en) @[el2_dbg.scala 132:65] + node _T_17 = eq(sb_state, UInt<4>("h00")) @[el2_dbg.scala 132:96] + node sbcs_wren = and(_T_16, _T_17) @[el2_dbg.scala 132:84] + node _T_18 = bits(io.dmi_reg_wdata, 22, 22) @[el2_dbg.scala 133:60] + node _T_19 = and(sbcs_wren, _T_18) @[el2_dbg.scala 133:42] + node _T_20 = neq(sb_state, UInt<4>("h00")) @[el2_dbg.scala 133:79] + node _T_21 = and(_T_20, io.dmi_reg_en) @[el2_dbg.scala 133:102] + node _T_22 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[el2_dbg.scala 134:23] + node _T_23 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[el2_dbg.scala 134:55] + node _T_24 = or(_T_22, _T_23) @[el2_dbg.scala 134:36] + node _T_25 = eq(io.dmi_reg_addr, UInt<6>("h03d")) @[el2_dbg.scala 134:87] + node _T_26 = or(_T_24, _T_25) @[el2_dbg.scala 134:68] + node _T_27 = and(_T_21, _T_26) @[el2_dbg.scala 133:118] + node sbcs_sbbusyerror_wren = or(_T_19, _T_27) @[el2_dbg.scala 133:66] + node _T_28 = bits(io.dmi_reg_wdata, 22, 22) @[el2_dbg.scala 136:61] + node _T_29 = and(sbcs_wren, _T_28) @[el2_dbg.scala 136:43] + node sbcs_sbbusyerror_din = not(_T_29) @[el2_dbg.scala 136:31] + node _T_30 = asUInt(dbg_dm_rst_l) @[el2_dbg.scala 137:74] + node _T_31 = eq(_T_30, UInt<1>("h00")) @[el2_dbg.scala 137:54] + node _T_32 = asAsyncReset(_T_31) @[el2_dbg.scala 137:90] + reg temp_sbcs_22 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_32, UInt<1>("h00"))) @[Reg.scala 27:20] + when sbcs_sbbusyerror_wren : @[Reg.scala 28:19] + temp_sbcs_22 <= sbcs_sbbusyerror_din @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_33 = asUInt(dbg_dm_rst_l) @[el2_dbg.scala 141:74] + node _T_34 = eq(_T_33, UInt<1>("h00")) @[el2_dbg.scala 141:54] + node _T_35 = asAsyncReset(_T_34) @[el2_dbg.scala 141:90] + reg temp_sbcs_21 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_35, UInt<1>("h00"))) @[Reg.scala 27:20] + when sbcs_sbbusy_wren : @[Reg.scala 28:19] + temp_sbcs_21 <= sbcs_sbbusy_din @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_36 = asUInt(dbg_dm_rst_l) @[el2_dbg.scala 145:74] + node _T_37 = eq(_T_36, UInt<1>("h00")) @[el2_dbg.scala 145:54] + node _T_38 = asAsyncReset(_T_37) @[el2_dbg.scala 145:90] + node _T_39 = bits(io.dmi_reg_wdata, 20, 20) @[el2_dbg.scala 146:31] + reg temp_sbcs_20 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_38, UInt<1>("h00"))) @[Reg.scala 27:20] + when sbcs_wren : @[Reg.scala 28:19] + temp_sbcs_20 <= _T_39 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_40 = asUInt(dbg_dm_rst_l) @[el2_dbg.scala 149:77] + node _T_41 = eq(_T_40, UInt<1>("h00")) @[el2_dbg.scala 149:57] + node _T_42 = asAsyncReset(_T_41) @[el2_dbg.scala 149:93] + node _T_43 = bits(io.dmi_reg_wdata, 19, 15) @[el2_dbg.scala 150:31] + reg temp_sbcs_19_15 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_42, UInt<1>("h00"))) @[Reg.scala 27:20] + when sbcs_wren : @[Reg.scala 28:19] + temp_sbcs_19_15 <= _T_43 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_44 = asUInt(dbg_dm_rst_l) @[el2_dbg.scala 153:77] + node _T_45 = eq(_T_44, UInt<1>("h00")) @[el2_dbg.scala 153:57] + node _T_46 = asAsyncReset(_T_45) @[el2_dbg.scala 153:93] + node _T_47 = bits(sbcs_sberror_din, 2, 0) @[el2_dbg.scala 154:31] + reg temp_sbcs_14_12 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_46, UInt<1>("h00"))) @[Reg.scala 27:20] + when sbcs_sberror_wren : @[Reg.scala 28:19] + temp_sbcs_14_12 <= _T_47 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_48 = cat(UInt<7>("h020"), UInt<5>("h0f")) @[Cat.scala 29:58] + node _T_49 = cat(temp_sbcs_19_15, temp_sbcs_14_12) @[Cat.scala 29:58] + node _T_50 = cat(_T_49, _T_48) @[Cat.scala 29:58] + node _T_51 = cat(temp_sbcs_21, temp_sbcs_20) @[Cat.scala 29:58] + node _T_52 = cat(UInt<3>("h01"), UInt<6>("h00")) @[Cat.scala 29:58] + node _T_53 = cat(_T_52, temp_sbcs_22) @[Cat.scala 29:58] + node _T_54 = cat(_T_53, _T_51) @[Cat.scala 29:58] + node _T_55 = cat(_T_54, _T_50) @[Cat.scala 29:58] + sbcs_reg <= _T_55 @[el2_dbg.scala 156:12] + node _T_56 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 158:33] + node _T_57 = eq(_T_56, UInt<1>("h01")) @[el2_dbg.scala 158:42] + node _T_58 = bits(sbaddress0_reg, 0, 0) @[el2_dbg.scala 158:72] + node _T_59 = and(_T_57, _T_58) @[el2_dbg.scala 158:56] + node _T_60 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 159:14] + node _T_61 = eq(_T_60, UInt<2>("h02")) @[el2_dbg.scala 159:23] + node _T_62 = bits(sbaddress0_reg, 1, 0) @[el2_dbg.scala 159:53] + node _T_63 = orr(_T_62) @[el2_dbg.scala 159:60] + node _T_64 = and(_T_61, _T_63) @[el2_dbg.scala 159:37] + node _T_65 = or(_T_59, _T_64) @[el2_dbg.scala 158:76] + node _T_66 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 160:14] + node _T_67 = eq(_T_66, UInt<2>("h03")) @[el2_dbg.scala 160:23] + node _T_68 = bits(sbaddress0_reg, 2, 0) @[el2_dbg.scala 160:53] + node _T_69 = orr(_T_68) @[el2_dbg.scala 160:60] + node _T_70 = and(_T_67, _T_69) @[el2_dbg.scala 160:37] + node sbcs_unaligned = or(_T_65, _T_70) @[el2_dbg.scala 159:64] + node sbcs_illegal_size = bits(sbcs_reg, 19, 19) @[el2_dbg.scala 162:35] + node _T_71 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 163:42] + node _T_72 = eq(_T_71, UInt<1>("h00")) @[el2_dbg.scala 163:51] + node _T_73 = bits(_T_72, 0, 0) @[Bitwise.scala 72:15] + node _T_74 = mux(_T_73, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_75 = and(_T_74, UInt<1>("h01")) @[el2_dbg.scala 163:64] + node _T_76 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 163:95] + node _T_77 = eq(_T_76, UInt<1>("h01")) @[el2_dbg.scala 163:104] + node _T_78 = bits(_T_77, 0, 0) @[Bitwise.scala 72:15] + node _T_79 = mux(_T_78, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_80 = and(_T_79, UInt<2>("h02")) @[el2_dbg.scala 163:117] + node _T_81 = or(_T_75, _T_80) @[el2_dbg.scala 163:76] + node _T_82 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 164:22] + node _T_83 = eq(_T_82, UInt<2>("h02")) @[el2_dbg.scala 164:31] + node _T_84 = bits(_T_83, 0, 0) @[Bitwise.scala 72:15] + node _T_85 = mux(_T_84, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_86 = and(_T_85, UInt<3>("h04")) @[el2_dbg.scala 164:44] + node _T_87 = or(_T_81, _T_86) @[el2_dbg.scala 163:129] + node _T_88 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 164:75] + node _T_89 = eq(_T_88, UInt<2>("h03")) @[el2_dbg.scala 164:84] + node _T_90 = bits(_T_89, 0, 0) @[Bitwise.scala 72:15] + node _T_91 = mux(_T_90, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_92 = and(_T_91, UInt<4>("h08")) @[el2_dbg.scala 164:97] + node sbaddress0_incr = or(_T_87, _T_92) @[el2_dbg.scala 164:56] + node _T_93 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[el2_dbg.scala 166:41] + node _T_94 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[el2_dbg.scala 166:79] + node sbdata0_reg_wren0 = and(_T_93, _T_94) @[el2_dbg.scala 166:60] + node _T_95 = eq(sb_state, UInt<4>("h07")) @[el2_dbg.scala 167:37] + node _T_96 = and(_T_95, sb_state_en) @[el2_dbg.scala 167:60] + node _T_97 = eq(sbcs_sberror_wren, UInt<1>("h00")) @[el2_dbg.scala 167:76] + node sbdata0_reg_wren1 = and(_T_96, _T_97) @[el2_dbg.scala 167:74] + node sbdata0_reg_wren = or(sbdata0_reg_wren0, sbdata0_reg_wren1) @[el2_dbg.scala 168:44] + node _T_98 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[el2_dbg.scala 169:41] + node _T_99 = eq(io.dmi_reg_addr, UInt<6>("h03d")) @[el2_dbg.scala 169:79] + node sbdata1_reg_wren0 = and(_T_98, _T_99) @[el2_dbg.scala 169:60] + node _T_100 = eq(sb_state, UInt<4>("h07")) @[el2_dbg.scala 170:37] + node _T_101 = and(_T_100, sb_state_en) @[el2_dbg.scala 170:60] + node _T_102 = eq(sbcs_sberror_wren, UInt<1>("h00")) @[el2_dbg.scala 170:76] + node sbdata1_reg_wren1 = and(_T_101, _T_102) @[el2_dbg.scala 170:74] + node sbdata1_reg_wren = or(sbdata1_reg_wren0, sbdata1_reg_wren1) @[el2_dbg.scala 171:44] + node _T_103 = bits(sbdata0_reg_wren0, 0, 0) @[Bitwise.scala 72:15] + node _T_104 = mux(_T_103, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_105 = and(_T_104, io.dmi_reg_wdata) @[el2_dbg.scala 172:49] + node _T_106 = bits(sbdata0_reg_wren1, 0, 0) @[Bitwise.scala 72:15] + node _T_107 = mux(_T_106, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_108 = bits(sb_bus_rdata, 31, 0) @[el2_dbg.scala 173:47] + node _T_109 = and(_T_107, _T_108) @[el2_dbg.scala 173:33] + node sbdata0_din = or(_T_105, _T_109) @[el2_dbg.scala 172:68] + node _T_110 = bits(sbdata1_reg_wren0, 0, 0) @[Bitwise.scala 72:15] + node _T_111 = mux(_T_110, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_112 = and(_T_111, io.dmi_reg_wdata) @[el2_dbg.scala 175:49] + node _T_113 = bits(sbdata1_reg_wren1, 0, 0) @[Bitwise.scala 72:15] + node _T_114 = mux(_T_113, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_115 = bits(sb_bus_rdata, 63, 32) @[el2_dbg.scala 176:47] + node _T_116 = and(_T_114, _T_115) @[el2_dbg.scala 176:33] + node sbdata1_din = or(_T_112, _T_116) @[el2_dbg.scala 175:68] + node _T_117 = asUInt(dbg_dm_rst_l) @[el2_dbg.scala 178:52] + node _T_118 = eq(_T_117, UInt<1>("h00")) @[el2_dbg.scala 178:32] + node _T_119 = asAsyncReset(_T_118) @[el2_dbg.scala 178:68] + inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 508:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= _T_119 + rvclkhdr_2.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_2.io.en <= sbdata0_reg_wren @[el2_lib.scala 511:17] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg sbdata0_reg : UInt, rvclkhdr_2.io.l1clk with : (reset => (_T_119, UInt<1>("h00"))) @[el2_lib.scala 514:16] + sbdata0_reg <= sbdata0_din @[el2_lib.scala 514:16] + node _T_120 = asUInt(dbg_dm_rst_l) @[el2_dbg.scala 182:52] + node _T_121 = eq(_T_120, UInt<1>("h00")) @[el2_dbg.scala 182:32] + node _T_122 = asAsyncReset(_T_121) @[el2_dbg.scala 182:68] + inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 508:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= _T_122 + rvclkhdr_3.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_3.io.en <= sbdata1_reg_wren @[el2_lib.scala 511:17] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg sbdata1_reg : UInt, rvclkhdr_3.io.l1clk with : (reset => (_T_122, UInt<1>("h00"))) @[el2_lib.scala 514:16] + sbdata1_reg <= sbdata1_din @[el2_lib.scala 514:16] + node _T_123 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[el2_dbg.scala 186:44] + node _T_124 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[el2_dbg.scala 186:82] + node sbaddress0_reg_wren0 = and(_T_123, _T_124) @[el2_dbg.scala 186:63] + node sbaddress0_reg_wren = or(sbaddress0_reg_wren0, sbaddress0_reg_wren1) @[el2_dbg.scala 187:50] + node _T_125 = bits(sbaddress0_reg_wren0, 0, 0) @[Bitwise.scala 72:15] + node _T_126 = mux(_T_125, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_127 = and(_T_126, io.dmi_reg_wdata) @[el2_dbg.scala 188:59] + node _T_128 = bits(sbaddress0_reg_wren1, 0, 0) @[Bitwise.scala 72:15] + node _T_129 = mux(_T_128, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_130 = cat(UInt<28>("h00"), sbaddress0_incr) @[Cat.scala 29:58] + node _T_131 = add(sbaddress0_reg, _T_130) @[el2_dbg.scala 189:54] + node _T_132 = tail(_T_131, 1) @[el2_dbg.scala 189:54] + node _T_133 = and(_T_129, _T_132) @[el2_dbg.scala 189:36] + node sbaddress0_reg_din = or(_T_127, _T_133) @[el2_dbg.scala 188:78] + node _T_134 = asUInt(dbg_dm_rst_l) @[el2_dbg.scala 190:52] + node _T_135 = eq(_T_134, UInt<1>("h00")) @[el2_dbg.scala 190:32] + node _T_136 = asAsyncReset(_T_135) @[el2_dbg.scala 190:68] + inst rvclkhdr_4 of rvclkhdr_4 @[el2_lib.scala 508:23] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= _T_136 + rvclkhdr_4.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_4.io.en <= sbaddress0_reg_wren @[el2_lib.scala 511:17] + rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_137 : UInt, rvclkhdr_4.io.l1clk with : (reset => (_T_136, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_137 <= sbaddress0_reg_din @[el2_lib.scala 514:16] + sbaddress0_reg <= _T_137 @[el2_dbg.scala 190:18] + node _T_138 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[el2_dbg.scala 194:43] + node _T_139 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[el2_dbg.scala 194:81] + node _T_140 = and(_T_138, _T_139) @[el2_dbg.scala 194:62] + node _T_141 = bits(sbcs_reg, 20, 20) @[el2_dbg.scala 194:104] + node sbreadonaddr_access = and(_T_140, _T_141) @[el2_dbg.scala 194:94] + node _T_142 = eq(io.dmi_reg_wr_en, UInt<1>("h00")) @[el2_dbg.scala 195:45] + node _T_143 = and(io.dmi_reg_en, _T_142) @[el2_dbg.scala 195:43] + node _T_144 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[el2_dbg.scala 195:82] + node _T_145 = and(_T_143, _T_144) @[el2_dbg.scala 195:63] + node _T_146 = bits(sbcs_reg, 15, 15) @[el2_dbg.scala 195:105] + node sbreadondata_access = and(_T_145, _T_146) @[el2_dbg.scala 195:95] + node _T_147 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[el2_dbg.scala 196:40] + node _T_148 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[el2_dbg.scala 196:78] + node sbdata0wr_access = and(_T_147, _T_148) @[el2_dbg.scala 196:59] + node _T_149 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[el2_dbg.scala 197:41] + node _T_150 = and(_T_149, io.dmi_reg_en) @[el2_dbg.scala 197:54] + node dmcontrol_wren = and(_T_150, io.dmi_reg_wr_en) @[el2_dbg.scala 197:70] + node _T_151 = asUInt(dbg_dm_rst_l) @[el2_dbg.scala 198:70] + node _T_152 = eq(_T_151, UInt<1>("h00")) @[el2_dbg.scala 198:50] + node _T_153 = asAsyncReset(_T_152) @[el2_dbg.scala 198:86] + node _T_154 = bits(io.dmi_reg_wdata, 31, 30) @[el2_dbg.scala 200:27] + node _T_155 = bits(io.dmi_reg_wdata, 28, 28) @[el2_dbg.scala 200:53] + node _T_156 = bits(io.dmi_reg_wdata, 1, 1) @[el2_dbg.scala 200:75] + node _T_157 = cat(_T_154, _T_155) @[Cat.scala 29:58] + node _T_158 = cat(_T_157, _T_156) @[Cat.scala 29:58] + reg dm_temp : UInt, rvclkhdr.io.l1clk with : (reset => (_T_153, UInt<1>("h00"))) @[Reg.scala 27:20] + when dmcontrol_wren : @[Reg.scala 28:19] + dm_temp <= _T_158 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_159 = bits(io.dmi_reg_wdata, 0, 0) @[el2_dbg.scala 205:31] + reg dm_temp_0 : UInt, rvclkhdr.io.l1clk with : (reset => (io.dbg_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] + when dmcontrol_wren : @[Reg.scala 28:19] + dm_temp_0 <= _T_159 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_160 = bits(dm_temp, 3, 2) @[el2_dbg.scala 208:25] + node _T_161 = bits(dm_temp, 1, 1) @[el2_dbg.scala 208:45] + node _T_162 = bits(dm_temp, 0, 0) @[el2_dbg.scala 208:68] + node _T_163 = cat(UInt<26>("h00"), _T_162) @[Cat.scala 29:58] + node _T_164 = cat(_T_163, dm_temp_0) @[Cat.scala 29:58] + node _T_165 = cat(_T_160, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_166 = cat(_T_165, _T_161) @[Cat.scala 29:58] + node temp = cat(_T_166, _T_164) @[Cat.scala 29:58] + dmcontrol_reg <= temp @[el2_dbg.scala 209:17] + node _T_167 = asUInt(dbg_dm_rst_l) @[el2_dbg.scala 211:79] + node _T_168 = eq(_T_167, UInt<1>("h00")) @[el2_dbg.scala 211:59] + node _T_169 = asAsyncReset(_T_168) @[el2_dbg.scala 211:95] + reg dmcontrol_wren_Q : UInt<1>, rvclkhdr.io.l1clk with : (reset => (_T_169, UInt<1>("h00"))) @[el2_dbg.scala 212:12] + dmcontrol_wren_Q <= dmcontrol_wren @[el2_dbg.scala 212:12] + node _T_170 = bits(dmstatus_havereset, 0, 0) @[Bitwise.scala 72:15] + node _T_171 = mux(_T_170, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_172 = bits(dmstatus_resumeack, 0, 0) @[Bitwise.scala 72:15] + node _T_173 = mux(_T_172, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_174 = bits(dmstatus_unavail, 0, 0) @[Bitwise.scala 72:15] + node _T_175 = mux(_T_174, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_176 = bits(dmstatus_running, 0, 0) @[Bitwise.scala 72:15] + node _T_177 = mux(_T_176, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_178 = bits(dmstatus_halted, 0, 0) @[Bitwise.scala 72:15] + node _T_179 = mux(_T_178, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_180 = cat(UInt<3>("h00"), UInt<4>("h02")) @[Cat.scala 29:58] + node _T_181 = cat(_T_177, _T_179) @[Cat.scala 29:58] + node _T_182 = cat(_T_181, UInt<1>("h01")) @[Cat.scala 29:58] + node _T_183 = cat(_T_182, _T_180) @[Cat.scala 29:58] + node _T_184 = cat(UInt<2>("h00"), _T_175) @[Cat.scala 29:58] + node _T_185 = cat(UInt<12>("h00"), _T_171) @[Cat.scala 29:58] + node _T_186 = cat(_T_185, _T_173) @[Cat.scala 29:58] + node _T_187 = cat(_T_186, _T_184) @[Cat.scala 29:58] + node _T_188 = cat(_T_187, _T_183) @[Cat.scala 29:58] + dmstatus_reg <= _T_188 @[el2_dbg.scala 215:16] + node _T_189 = eq(dbg_state, UInt<3>("h06")) @[el2_dbg.scala 217:44] + node _T_190 = and(_T_189, io.dec_tlu_resume_ack) @[el2_dbg.scala 217:66] + node _T_191 = bits(dmcontrol_reg, 30, 30) @[el2_dbg.scala 217:127] + node _T_192 = eq(_T_191, UInt<1>("h00")) @[el2_dbg.scala 217:113] + node _T_193 = and(dmstatus_resumeack, _T_192) @[el2_dbg.scala 217:111] + node dmstatus_resumeack_wren = or(_T_190, _T_193) @[el2_dbg.scala 217:90] + node _T_194 = eq(dbg_state, UInt<3>("h06")) @[el2_dbg.scala 218:43] + node dmstatus_resumeack_din = and(_T_194, io.dec_tlu_resume_ack) @[el2_dbg.scala 218:65] + node _T_195 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[el2_dbg.scala 219:50] + node _T_196 = bits(io.dmi_reg_wdata, 1, 1) @[el2_dbg.scala 219:81] + node _T_197 = and(_T_195, _T_196) @[el2_dbg.scala 219:63] + node _T_198 = and(_T_197, io.dmi_reg_en) @[el2_dbg.scala 219:85] + node dmstatus_havereset_wren = and(_T_198, io.dmi_reg_wr_en) @[el2_dbg.scala 219:101] + node _T_199 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[el2_dbg.scala 220:49] + node _T_200 = bits(io.dmi_reg_wdata, 28, 28) @[el2_dbg.scala 220:80] + node _T_201 = and(_T_199, _T_200) @[el2_dbg.scala 220:62] + node _T_202 = and(_T_201, io.dmi_reg_en) @[el2_dbg.scala 220:85] + node dmstatus_havereset_rst = and(_T_202, io.dmi_reg_wr_en) @[el2_dbg.scala 220:101] + node temp_rst = asUInt(reset) @[el2_dbg.scala 221:30] + node _T_203 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 222:37] + node _T_204 = eq(temp_rst, UInt<1>("h00")) @[el2_dbg.scala 222:43] + node _T_205 = or(_T_203, _T_204) @[el2_dbg.scala 222:41] + node _T_206 = bits(_T_205, 0, 0) @[el2_dbg.scala 222:62] + dmstatus_unavail <= _T_206 @[el2_dbg.scala 222:20] + node _T_207 = or(dmstatus_unavail, dmstatus_halted) @[el2_dbg.scala 223:42] + node _T_208 = not(_T_207) @[el2_dbg.scala 223:23] + dmstatus_running <= _T_208 @[el2_dbg.scala 223:20] + node _T_209 = asUInt(dbg_dm_rst_l) @[el2_dbg.scala 224:78] + node _T_210 = eq(_T_209, UInt<1>("h00")) @[el2_dbg.scala 224:58] + node _T_211 = asAsyncReset(_T_210) @[el2_dbg.scala 224:94] + reg _T_212 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_211, UInt<1>("h00"))) @[Reg.scala 27:20] + when dmstatus_resumeack_wren : @[Reg.scala 28:19] + _T_212 <= dmstatus_resumeack_din @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + dmstatus_resumeack <= _T_212 @[el2_dbg.scala 224:22] + node _T_213 = asUInt(dbg_dm_rst_l) @[el2_dbg.scala 228:75] + node _T_214 = eq(_T_213, UInt<1>("h00")) @[el2_dbg.scala 228:55] + node _T_215 = asAsyncReset(_T_214) @[el2_dbg.scala 228:91] + node _T_216 = eq(io.dec_tlu_mpc_halted_only, UInt<1>("h00")) @[el2_dbg.scala 229:37] + node _T_217 = and(io.dec_tlu_dbg_halted, _T_216) @[el2_dbg.scala 229:35] + reg _T_218 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (_T_215, UInt<1>("h00"))) @[el2_dbg.scala 229:12] + _T_218 <= _T_217 @[el2_dbg.scala 229:12] + dmstatus_halted <= _T_218 @[el2_dbg.scala 228:19] + node _T_219 = asUInt(dbg_dm_rst_l) @[el2_dbg.scala 232:78] + node _T_220 = eq(_T_219, UInt<1>("h00")) @[el2_dbg.scala 232:58] + node _T_221 = asAsyncReset(_T_220) @[el2_dbg.scala 232:94] + node _T_222 = not(dmstatus_havereset_rst) @[el2_dbg.scala 233:15] + reg _T_223 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_221, UInt<1>("h00"))) @[Reg.scala 27:20] + when dmstatus_havereset_wren : @[Reg.scala 28:19] + _T_223 <= _T_222 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + dmstatus_havereset <= _T_223 @[el2_dbg.scala 232:22] + node haltsum0_reg = cat(UInt<31>("h00"), dmstatus_halted) @[Cat.scala 29:58] + wire abstractcs_reg : UInt<32> + abstractcs_reg <= UInt<32>("h02") + node _T_224 = bits(abstractcs_reg, 12, 12) @[el2_dbg.scala 239:45] + node _T_225 = and(_T_224, io.dmi_reg_en) @[el2_dbg.scala 239:50] + node _T_226 = eq(io.dmi_reg_addr, UInt<5>("h016")) @[el2_dbg.scala 239:106] + node _T_227 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[el2_dbg.scala 239:138] + node _T_228 = or(_T_226, _T_227) @[el2_dbg.scala 239:119] + node _T_229 = and(io.dmi_reg_wr_en, _T_228) @[el2_dbg.scala 239:86] + node _T_230 = eq(io.dmi_reg_addr, UInt<3>("h04")) @[el2_dbg.scala 239:171] + node _T_231 = or(_T_229, _T_230) @[el2_dbg.scala 239:152] + node abstractcs_error_sel0 = and(_T_225, _T_231) @[el2_dbg.scala 239:66] + node _T_232 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[el2_dbg.scala 240:45] + node _T_233 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[el2_dbg.scala 240:83] + node _T_234 = and(_T_232, _T_233) @[el2_dbg.scala 240:64] + node _T_235 = bits(io.dmi_reg_wdata, 31, 24) @[el2_dbg.scala 240:117] + node _T_236 = eq(_T_235, UInt<1>("h00")) @[el2_dbg.scala 240:126] + node _T_237 = bits(io.dmi_reg_wdata, 31, 24) @[el2_dbg.scala 240:154] + node _T_238 = eq(_T_237, UInt<2>("h02")) @[el2_dbg.scala 240:163] + node _T_239 = or(_T_236, _T_238) @[el2_dbg.scala 240:135] + node _T_240 = eq(_T_239, UInt<1>("h00")) @[el2_dbg.scala 240:98] + node abstractcs_error_sel1 = and(_T_234, _T_240) @[el2_dbg.scala 240:96] + node abstractcs_error_sel2 = and(io.core_dbg_cmd_done, io.core_dbg_cmd_fail) @[el2_dbg.scala 241:52] + node _T_241 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[el2_dbg.scala 242:45] + node _T_242 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[el2_dbg.scala 242:83] + node _T_243 = and(_T_241, _T_242) @[el2_dbg.scala 242:64] + node _T_244 = bits(dmstatus_reg, 9, 9) @[el2_dbg.scala 242:111] + node _T_245 = eq(_T_244, UInt<1>("h00")) @[el2_dbg.scala 242:98] + node abstractcs_error_sel3 = and(_T_243, _T_245) @[el2_dbg.scala 242:96] + node _T_246 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[el2_dbg.scala 243:48] + node _T_247 = and(_T_246, io.dmi_reg_en) @[el2_dbg.scala 243:61] + node _T_248 = and(_T_247, io.dmi_reg_wr_en) @[el2_dbg.scala 243:77] + node _T_249 = bits(io.dmi_reg_wdata, 22, 20) @[el2_dbg.scala 244:23] + node _T_250 = neq(_T_249, UInt<2>("h02")) @[el2_dbg.scala 244:32] + node _T_251 = bits(io.dmi_reg_wdata, 31, 24) @[el2_dbg.scala 244:66] + node _T_252 = eq(_T_251, UInt<2>("h02")) @[el2_dbg.scala 244:75] + node _T_253 = bits(data1_reg, 1, 0) @[el2_dbg.scala 244:99] + node _T_254 = orr(_T_253) @[el2_dbg.scala 244:106] + node _T_255 = and(_T_252, _T_254) @[el2_dbg.scala 244:87] + node _T_256 = or(_T_250, _T_255) @[el2_dbg.scala 244:46] + node abstractcs_error_sel4 = and(_T_248, _T_256) @[el2_dbg.scala 243:96] + node _T_257 = eq(io.dmi_reg_addr, UInt<5>("h016")) @[el2_dbg.scala 246:48] + node _T_258 = and(_T_257, io.dmi_reg_en) @[el2_dbg.scala 246:61] + node abstractcs_error_sel5 = and(_T_258, io.dmi_reg_wr_en) @[el2_dbg.scala 246:77] + node _T_259 = or(abstractcs_error_sel0, abstractcs_error_sel1) @[el2_dbg.scala 247:54] + node _T_260 = or(_T_259, abstractcs_error_sel2) @[el2_dbg.scala 247:78] + node _T_261 = or(_T_260, abstractcs_error_sel3) @[el2_dbg.scala 247:102] + node _T_262 = or(_T_261, abstractcs_error_sel4) @[el2_dbg.scala 247:126] + node abstractcs_error_selor = or(_T_262, abstractcs_error_sel5) @[el2_dbg.scala 247:150] + node _T_263 = bits(abstractcs_error_sel0, 0, 0) @[Bitwise.scala 72:15] + node _T_264 = mux(_T_263, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_265 = and(_T_264, UInt<1>("h01")) @[el2_dbg.scala 248:62] + node _T_266 = bits(abstractcs_error_sel1, 0, 0) @[Bitwise.scala 72:15] + node _T_267 = mux(_T_266, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_268 = and(_T_267, UInt<2>("h02")) @[el2_dbg.scala 249:37] + node _T_269 = or(_T_265, _T_268) @[el2_dbg.scala 248:74] + node _T_270 = bits(abstractcs_error_sel2, 0, 0) @[Bitwise.scala 72:15] + node _T_271 = mux(_T_270, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_272 = and(_T_271, UInt<2>("h03")) @[el2_dbg.scala 250:37] + node _T_273 = or(_T_269, _T_272) @[el2_dbg.scala 249:49] + node _T_274 = bits(abstractcs_error_sel3, 0, 0) @[Bitwise.scala 72:15] + node _T_275 = mux(_T_274, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_276 = and(_T_275, UInt<3>("h04")) @[el2_dbg.scala 251:37] + node _T_277 = or(_T_273, _T_276) @[el2_dbg.scala 250:49] + node _T_278 = bits(abstractcs_error_sel4, 0, 0) @[Bitwise.scala 72:15] + node _T_279 = mux(_T_278, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_280 = and(_T_279, UInt<3>("h07")) @[el2_dbg.scala 252:37] + node _T_281 = or(_T_277, _T_280) @[el2_dbg.scala 251:49] + node _T_282 = bits(abstractcs_error_sel5, 0, 0) @[Bitwise.scala 72:15] + node _T_283 = mux(_T_282, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_284 = bits(io.dmi_reg_wdata, 10, 8) @[el2_dbg.scala 253:57] + node _T_285 = not(_T_284) @[el2_dbg.scala 253:40] + node _T_286 = and(_T_283, _T_285) @[el2_dbg.scala 253:37] + node _T_287 = bits(abstractcs_reg, 10, 8) @[el2_dbg.scala 253:91] + node _T_288 = and(_T_286, _T_287) @[el2_dbg.scala 253:75] + node _T_289 = or(_T_281, _T_288) @[el2_dbg.scala 252:49] + node _T_290 = not(abstractcs_error_selor) @[el2_dbg.scala 254:15] + node _T_291 = bits(_T_290, 0, 0) @[Bitwise.scala 72:15] + node _T_292 = mux(_T_291, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_293 = bits(abstractcs_reg, 10, 8) @[el2_dbg.scala 254:66] + node _T_294 = and(_T_292, _T_293) @[el2_dbg.scala 254:50] + node abstractcs_error_din = or(_T_289, _T_294) @[el2_dbg.scala 253:100] + node _T_295 = asUInt(dbg_dm_rst_l) @[el2_dbg.scala 256:74] + node _T_296 = eq(_T_295, UInt<1>("h00")) @[el2_dbg.scala 256:54] + node _T_297 = asAsyncReset(_T_296) @[el2_dbg.scala 256:90] + reg abs_temp_12 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_297, UInt<1>("h00"))) @[Reg.scala 27:20] + when abstractcs_busy_wren : @[Reg.scala 28:19] + abs_temp_12 <= abstractcs_busy_din @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_298 = asUInt(dbg_dm_rst_l) @[el2_dbg.scala 260:76] + node _T_299 = eq(_T_298, UInt<1>("h00")) @[el2_dbg.scala 260:56] + node _T_300 = asAsyncReset(_T_299) @[el2_dbg.scala 260:92] + node _T_301 = bits(abstractcs_error_din, 2, 0) @[el2_dbg.scala 261:33] + reg abs_temp_10_8 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_300, UInt<1>("h00"))) @[el2_dbg.scala 261:12] + abs_temp_10_8 <= _T_301 @[el2_dbg.scala 261:12] + node _T_302 = cat(abs_temp_10_8, UInt<8>("h02")) @[Cat.scala 29:58] + node _T_303 = cat(UInt<19>("h00"), abs_temp_12) @[Cat.scala 29:58] + node _T_304 = cat(_T_303, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_305 = cat(_T_304, _T_302) @[Cat.scala 29:58] + abstractcs_reg <= _T_305 @[el2_dbg.scala 264:18] + node _T_306 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[el2_dbg.scala 266:39] + node _T_307 = and(_T_306, io.dmi_reg_en) @[el2_dbg.scala 266:52] + node _T_308 = and(_T_307, io.dmi_reg_wr_en) @[el2_dbg.scala 266:68] + node _T_309 = eq(dbg_state, UInt<3>("h02")) @[el2_dbg.scala 266:100] + node command_wren = and(_T_308, _T_309) @[el2_dbg.scala 266:87] + node _T_310 = bits(io.dmi_reg_wdata, 31, 24) @[el2_dbg.scala 267:41] + node _T_311 = bits(io.dmi_reg_wdata, 22, 20) @[el2_dbg.scala 267:77] + node _T_312 = bits(io.dmi_reg_wdata, 16, 0) @[el2_dbg.scala 267:113] + node _T_313 = cat(UInt<3>("h00"), _T_312) @[Cat.scala 29:58] + node _T_314 = cat(_T_310, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_315 = cat(_T_314, _T_311) @[Cat.scala 29:58] + node command_din = cat(_T_315, _T_313) @[Cat.scala 29:58] + node _T_316 = asUInt(dbg_dm_rst_l) @[el2_dbg.scala 268:52] + node _T_317 = eq(_T_316, UInt<1>("h00")) @[el2_dbg.scala 268:32] + node _T_318 = asAsyncReset(_T_317) @[el2_dbg.scala 268:68] + inst rvclkhdr_5 of rvclkhdr_5 @[el2_lib.scala 508:23] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= _T_318 + rvclkhdr_5.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_5.io.en <= command_wren @[el2_lib.scala 511:17] + rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg command_reg : UInt, rvclkhdr_5.io.l1clk with : (reset => (_T_318, UInt<1>("h00"))) @[el2_lib.scala 514:16] + command_reg <= command_din @[el2_lib.scala 514:16] + node _T_319 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[el2_dbg.scala 272:39] + node _T_320 = eq(io.dmi_reg_addr, UInt<3>("h04")) @[el2_dbg.scala 272:77] + node _T_321 = and(_T_319, _T_320) @[el2_dbg.scala 272:58] + node _T_322 = eq(dbg_state, UInt<3>("h02")) @[el2_dbg.scala 272:102] + node data0_reg_wren0 = and(_T_321, _T_322) @[el2_dbg.scala 272:89] + node _T_323 = eq(dbg_state, UInt<3>("h04")) @[el2_dbg.scala 273:59] + node _T_324 = and(io.core_dbg_cmd_done, _T_323) @[el2_dbg.scala 273:46] + node _T_325 = bits(command_reg, 16, 16) @[el2_dbg.scala 273:95] + node _T_326 = eq(_T_325, UInt<1>("h00")) @[el2_dbg.scala 273:83] + node data0_reg_wren1 = and(_T_324, _T_326) @[el2_dbg.scala 273:81] + node data0_reg_wren = or(data0_reg_wren0, data0_reg_wren1) @[el2_dbg.scala 275:40] + node _T_327 = bits(data0_reg_wren0, 0, 0) @[Bitwise.scala 72:15] + node _T_328 = mux(_T_327, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_329 = and(_T_328, io.dmi_reg_wdata) @[el2_dbg.scala 276:45] + node _T_330 = bits(data0_reg_wren1, 0, 0) @[Bitwise.scala 72:15] + node _T_331 = mux(_T_330, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_332 = and(_T_331, io.core_dbg_rddata) @[el2_dbg.scala 276:92] + node data0_din = or(_T_329, _T_332) @[el2_dbg.scala 276:64] + node _T_333 = asUInt(dbg_dm_rst_l) @[el2_dbg.scala 277:50] + node _T_334 = eq(_T_333, UInt<1>("h00")) @[el2_dbg.scala 277:30] + node _T_335 = asAsyncReset(_T_334) @[el2_dbg.scala 277:66] + inst rvclkhdr_6 of rvclkhdr_6 @[el2_lib.scala 508:23] + rvclkhdr_6.clock <= clock + rvclkhdr_6.reset <= _T_335 + rvclkhdr_6.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_6.io.en <= data0_reg_wren @[el2_lib.scala 511:17] + rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg data0_reg : UInt, rvclkhdr_6.io.l1clk with : (reset => (_T_335, UInt<1>("h00"))) @[el2_lib.scala 514:16] + data0_reg <= data0_din @[el2_lib.scala 514:16] + node _T_336 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[el2_dbg.scala 281:39] + node _T_337 = eq(io.dmi_reg_addr, UInt<3>("h05")) @[el2_dbg.scala 281:77] + node _T_338 = and(_T_336, _T_337) @[el2_dbg.scala 281:58] + node _T_339 = eq(dbg_state, UInt<3>("h02")) @[el2_dbg.scala 281:102] + node data1_reg_wren = and(_T_338, _T_339) @[el2_dbg.scala 281:89] + node _T_340 = bits(data1_reg_wren, 0, 0) @[Bitwise.scala 72:15] + node _T_341 = mux(_T_340, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node data1_din = and(_T_341, io.dmi_reg_wdata) @[el2_dbg.scala 282:44] + node _T_342 = asUInt(dbg_dm_rst_l) @[el2_dbg.scala 283:47] + node _T_343 = eq(_T_342, UInt<1>("h00")) @[el2_dbg.scala 283:27] + node _T_344 = asAsyncReset(_T_343) @[el2_dbg.scala 283:63] + inst rvclkhdr_7 of rvclkhdr_7 @[el2_lib.scala 508:23] + rvclkhdr_7.clock <= clock + rvclkhdr_7.reset <= _T_344 + rvclkhdr_7.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_7.io.en <= data1_reg_wren @[el2_lib.scala 511:17] + rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_345 : UInt, rvclkhdr_7.io.l1clk with : (reset => (_T_344, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_345 <= data1_din @[el2_lib.scala 514:16] + data1_reg <= _T_345 @[el2_dbg.scala 283:13] + wire dbg_nxtstate : UInt<3> + dbg_nxtstate <= UInt<3>("h00") + dbg_nxtstate <= UInt<3>("h00") @[el2_dbg.scala 288:16] + dbg_state_en <= UInt<1>("h00") @[el2_dbg.scala 289:16] + abstractcs_busy_wren <= UInt<1>("h00") @[el2_dbg.scala 290:24] + abstractcs_busy_din <= UInt<1>("h00") @[el2_dbg.scala 291:23] + io.dbg_halt_req <= UInt<1>("h00") @[el2_dbg.scala 292:19] + io.dbg_resume_req <= UInt<1>("h00") @[el2_dbg.scala 293:21] + node _T_346 = eq(UInt<3>("h00"), dbg_state) @[Conditional.scala 37:30] + when _T_346 : @[Conditional.scala 40:58] + node _T_347 = bits(dmstatus_reg, 9, 9) @[el2_dbg.scala 296:39] + node _T_348 = or(_T_347, io.dec_tlu_mpc_halted_only) @[el2_dbg.scala 296:43] + node _T_349 = mux(_T_348, UInt<3>("h02"), UInt<3>("h01")) @[el2_dbg.scala 296:26] + dbg_nxtstate <= _T_349 @[el2_dbg.scala 296:20] + node _T_350 = bits(dmcontrol_reg, 31, 31) @[el2_dbg.scala 297:38] + node _T_351 = eq(io.dec_tlu_debug_mode, UInt<1>("h00")) @[el2_dbg.scala 297:45] + node _T_352 = and(_T_350, _T_351) @[el2_dbg.scala 297:43] + node _T_353 = bits(dmstatus_reg, 9, 9) @[el2_dbg.scala 297:83] + node _T_354 = or(_T_352, _T_353) @[el2_dbg.scala 297:69] + node _T_355 = or(_T_354, io.dec_tlu_mpc_halted_only) @[el2_dbg.scala 297:87] + node _T_356 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 297:133] + node _T_357 = eq(_T_356, UInt<1>("h00")) @[el2_dbg.scala 297:119] + node _T_358 = and(_T_355, _T_357) @[el2_dbg.scala 297:117] + dbg_state_en <= _T_358 @[el2_dbg.scala 297:20] + node _T_359 = bits(dmcontrol_reg, 31, 31) @[el2_dbg.scala 298:40] + node _T_360 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 298:61] + node _T_361 = eq(_T_360, UInt<1>("h00")) @[el2_dbg.scala 298:47] + node _T_362 = and(_T_359, _T_361) @[el2_dbg.scala 298:45] + node _T_363 = bits(_T_362, 0, 0) @[el2_dbg.scala 298:72] + io.dbg_halt_req <= _T_363 @[el2_dbg.scala 298:23] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_364 = eq(UInt<3>("h01"), dbg_state) @[Conditional.scala 37:30] + when _T_364 : @[Conditional.scala 39:67] + node _T_365 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 301:40] + node _T_366 = mux(_T_365, UInt<3>("h00"), UInt<3>("h02")) @[el2_dbg.scala 301:26] + dbg_nxtstate <= _T_366 @[el2_dbg.scala 301:20] + node _T_367 = bits(dmstatus_reg, 9, 9) @[el2_dbg.scala 302:35] + node _T_368 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 302:54] + node _T_369 = or(_T_367, _T_368) @[el2_dbg.scala 302:39] + dbg_state_en <= _T_369 @[el2_dbg.scala 302:20] + node _T_370 = bits(dmcontrol_reg, 31, 31) @[el2_dbg.scala 303:59] + node _T_371 = and(dmcontrol_wren_Q, _T_370) @[el2_dbg.scala 303:44] + node _T_372 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 303:81] + node _T_373 = not(_T_372) @[el2_dbg.scala 303:67] + node _T_374 = and(_T_371, _T_373) @[el2_dbg.scala 303:64] + node _T_375 = bits(_T_374, 0, 0) @[el2_dbg.scala 303:102] + io.dbg_halt_req <= _T_375 @[el2_dbg.scala 303:23] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_376 = eq(UInt<3>("h02"), dbg_state) @[Conditional.scala 37:30] + when _T_376 : @[Conditional.scala 39:67] + node _T_377 = bits(dmstatus_reg, 9, 9) @[el2_dbg.scala 306:39] + node _T_378 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 306:59] + node _T_379 = eq(_T_378, UInt<1>("h00")) @[el2_dbg.scala 306:45] + node _T_380 = and(_T_377, _T_379) @[el2_dbg.scala 306:43] + node _T_381 = bits(dmcontrol_reg, 30, 30) @[el2_dbg.scala 307:26] + node _T_382 = bits(dmcontrol_reg, 3, 3) @[el2_dbg.scala 307:47] + node _T_383 = eq(_T_382, UInt<1>("h00")) @[el2_dbg.scala 307:33] + node _T_384 = and(_T_381, _T_383) @[el2_dbg.scala 307:31] + node _T_385 = mux(_T_384, UInt<3>("h06"), UInt<3>("h03")) @[el2_dbg.scala 307:12] + node _T_386 = bits(dmcontrol_reg, 31, 31) @[el2_dbg.scala 308:26] + node _T_387 = mux(_T_386, UInt<3>("h01"), UInt<3>("h00")) @[el2_dbg.scala 308:12] + node _T_388 = mux(_T_380, _T_385, _T_387) @[el2_dbg.scala 306:26] + dbg_nxtstate <= _T_388 @[el2_dbg.scala 306:20] + node _T_389 = bits(dmstatus_reg, 9, 9) @[el2_dbg.scala 309:35] + node _T_390 = bits(dmcontrol_reg, 30, 30) @[el2_dbg.scala 309:54] + node _T_391 = and(_T_389, _T_390) @[el2_dbg.scala 309:39] + node _T_392 = bits(dmcontrol_reg, 31, 31) @[el2_dbg.scala 309:75] + node _T_393 = eq(_T_392, UInt<1>("h00")) @[el2_dbg.scala 309:61] + node _T_394 = and(_T_391, _T_393) @[el2_dbg.scala 309:59] + node _T_395 = and(_T_394, dmcontrol_wren_Q) @[el2_dbg.scala 309:80] + node _T_396 = or(_T_395, command_wren) @[el2_dbg.scala 309:99] + node _T_397 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 310:22] + node _T_398 = or(_T_396, _T_397) @[el2_dbg.scala 309:114] + node _T_399 = bits(dmstatus_reg, 9, 9) @[el2_dbg.scala 310:42] + node _T_400 = or(_T_399, io.dec_tlu_mpc_halted_only) @[el2_dbg.scala 310:46] + node _T_401 = eq(_T_400, UInt<1>("h00")) @[el2_dbg.scala 310:28] + node _T_402 = or(_T_398, _T_401) @[el2_dbg.scala 310:26] + dbg_state_en <= _T_402 @[el2_dbg.scala 309:20] + node _T_403 = eq(dbg_nxtstate, UInt<3>("h03")) @[el2_dbg.scala 311:60] + node _T_404 = and(dbg_state_en, _T_403) @[el2_dbg.scala 311:44] + abstractcs_busy_wren <= _T_404 @[el2_dbg.scala 311:28] + abstractcs_busy_din <= UInt<1>("h01") @[el2_dbg.scala 312:27] + node _T_405 = eq(dbg_nxtstate, UInt<3>("h06")) @[el2_dbg.scala 313:58] + node _T_406 = and(dbg_state_en, _T_405) @[el2_dbg.scala 313:42] + node _T_407 = bits(_T_406, 0, 0) @[el2_dbg.scala 313:87] + io.dbg_resume_req <= _T_407 @[el2_dbg.scala 313:25] + node _T_408 = bits(dmcontrol_reg, 31, 31) @[el2_dbg.scala 314:59] + node _T_409 = and(dmcontrol_wren_Q, _T_408) @[el2_dbg.scala 314:44] + node _T_410 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 314:81] + node _T_411 = not(_T_410) @[el2_dbg.scala 314:67] + node _T_412 = and(_T_409, _T_411) @[el2_dbg.scala 314:64] + node _T_413 = bits(_T_412, 0, 0) @[el2_dbg.scala 314:102] + io.dbg_halt_req <= _T_413 @[el2_dbg.scala 314:23] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_414 = eq(UInt<3>("h03"), dbg_state) @[Conditional.scala 37:30] + when _T_414 : @[Conditional.scala 39:67] + node _T_415 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 317:40] + node _T_416 = bits(abstractcs_reg, 10, 8) @[el2_dbg.scala 317:77] + node _T_417 = orr(_T_416) @[el2_dbg.scala 317:85] + node _T_418 = mux(_T_417, UInt<3>("h05"), UInt<3>("h04")) @[el2_dbg.scala 317:62] + node _T_419 = mux(_T_415, UInt<3>("h00"), _T_418) @[el2_dbg.scala 317:26] + dbg_nxtstate <= _T_419 @[el2_dbg.scala 317:20] + node _T_420 = bits(abstractcs_reg, 10, 8) @[el2_dbg.scala 318:56] + node _T_421 = orr(_T_420) @[el2_dbg.scala 318:64] + node _T_422 = or(io.dbg_cmd_valid, _T_421) @[el2_dbg.scala 318:40] + node _T_423 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 318:83] + node _T_424 = or(_T_422, _T_423) @[el2_dbg.scala 318:68] + dbg_state_en <= _T_424 @[el2_dbg.scala 318:20] + node _T_425 = bits(dmcontrol_reg, 31, 31) @[el2_dbg.scala 319:59] + node _T_426 = and(dmcontrol_wren_Q, _T_425) @[el2_dbg.scala 319:44] + node _T_427 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 319:81] + node _T_428 = not(_T_427) @[el2_dbg.scala 319:67] + node _T_429 = and(_T_426, _T_428) @[el2_dbg.scala 319:64] + node _T_430 = bits(_T_429, 0, 0) @[el2_dbg.scala 319:102] + io.dbg_halt_req <= _T_430 @[el2_dbg.scala 319:23] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_431 = eq(UInt<3>("h04"), dbg_state) @[Conditional.scala 37:30] + when _T_431 : @[Conditional.scala 39:67] + node _T_432 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 322:40] + node _T_433 = mux(_T_432, UInt<3>("h00"), UInt<3>("h05")) @[el2_dbg.scala 322:26] + dbg_nxtstate <= _T_433 @[el2_dbg.scala 322:20] + node _T_434 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 323:59] + node _T_435 = or(io.core_dbg_cmd_done, _T_434) @[el2_dbg.scala 323:44] + dbg_state_en <= _T_435 @[el2_dbg.scala 323:20] + node _T_436 = bits(dmcontrol_reg, 31, 31) @[el2_dbg.scala 324:59] + node _T_437 = and(dmcontrol_wren_Q, _T_436) @[el2_dbg.scala 324:44] + node _T_438 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 324:81] + node _T_439 = not(_T_438) @[el2_dbg.scala 324:67] + node _T_440 = and(_T_437, _T_439) @[el2_dbg.scala 324:64] + node _T_441 = bits(_T_440, 0, 0) @[el2_dbg.scala 324:102] + io.dbg_halt_req <= _T_441 @[el2_dbg.scala 324:23] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_442 = eq(UInt<3>("h05"), dbg_state) @[Conditional.scala 37:30] + when _T_442 : @[Conditional.scala 39:67] + node _T_443 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 327:40] + node _T_444 = mux(_T_443, UInt<3>("h00"), UInt<3>("h02")) @[el2_dbg.scala 327:26] + dbg_nxtstate <= _T_444 @[el2_dbg.scala 327:20] + dbg_state_en <= UInt<1>("h01") @[el2_dbg.scala 328:20] + abstractcs_busy_wren <= dbg_state_en @[el2_dbg.scala 329:28] + abstractcs_busy_din <= UInt<1>("h00") @[el2_dbg.scala 330:27] + node _T_445 = bits(dmcontrol_reg, 31, 31) @[el2_dbg.scala 331:59] + node _T_446 = and(dmcontrol_wren_Q, _T_445) @[el2_dbg.scala 331:44] + node _T_447 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 331:81] + node _T_448 = not(_T_447) @[el2_dbg.scala 331:67] + node _T_449 = and(_T_446, _T_448) @[el2_dbg.scala 331:64] + node _T_450 = bits(_T_449, 0, 0) @[el2_dbg.scala 331:102] + io.dbg_halt_req <= _T_450 @[el2_dbg.scala 331:23] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_451 = eq(UInt<3>("h06"), dbg_state) @[Conditional.scala 37:30] + when _T_451 : @[Conditional.scala 39:67] + dbg_nxtstate <= UInt<3>("h00") @[el2_dbg.scala 334:20] + node _T_452 = bits(dmstatus_reg, 17, 17) @[el2_dbg.scala 335:35] + node _T_453 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 335:55] + node _T_454 = or(_T_452, _T_453) @[el2_dbg.scala 335:40] + dbg_state_en <= _T_454 @[el2_dbg.scala 335:20] + node _T_455 = bits(dmcontrol_reg, 31, 31) @[el2_dbg.scala 336:59] + node _T_456 = and(dmcontrol_wren_Q, _T_455) @[el2_dbg.scala 336:44] + node _T_457 = bits(dmcontrol_reg, 1, 1) @[el2_dbg.scala 336:81] + node _T_458 = not(_T_457) @[el2_dbg.scala 336:67] + node _T_459 = and(_T_456, _T_458) @[el2_dbg.scala 336:64] + node _T_460 = bits(_T_459, 0, 0) @[el2_dbg.scala 336:102] + io.dbg_halt_req <= _T_460 @[el2_dbg.scala 336:23] + skip @[Conditional.scala 39:67] + node _T_461 = eq(io.dmi_reg_addr, UInt<3>("h04")) @[el2_dbg.scala 339:52] + node _T_462 = bits(_T_461, 0, 0) @[Bitwise.scala 72:15] + node _T_463 = mux(_T_462, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_464 = and(_T_463, data0_reg) @[el2_dbg.scala 339:71] + node _T_465 = eq(io.dmi_reg_addr, UInt<3>("h05")) @[el2_dbg.scala 339:110] + node _T_466 = bits(_T_465, 0, 0) @[Bitwise.scala 72:15] + node _T_467 = mux(_T_466, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_468 = and(_T_467, data1_reg) @[el2_dbg.scala 339:122] + node _T_469 = or(_T_464, _T_468) @[el2_dbg.scala 339:83] + node _T_470 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[el2_dbg.scala 340:30] + node _T_471 = bits(_T_470, 0, 0) @[Bitwise.scala 72:15] + node _T_472 = mux(_T_471, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_473 = and(_T_472, dmcontrol_reg) @[el2_dbg.scala 340:43] + node _T_474 = or(_T_469, _T_473) @[el2_dbg.scala 339:134] + node _T_475 = eq(io.dmi_reg_addr, UInt<5>("h011")) @[el2_dbg.scala 340:86] + node _T_476 = bits(_T_475, 0, 0) @[Bitwise.scala 72:15] + node _T_477 = mux(_T_476, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_478 = and(_T_477, dmstatus_reg) @[el2_dbg.scala 340:99] + node _T_479 = or(_T_474, _T_478) @[el2_dbg.scala 340:59] + node _T_480 = eq(io.dmi_reg_addr, UInt<5>("h016")) @[el2_dbg.scala 341:30] + node _T_481 = bits(_T_480, 0, 0) @[Bitwise.scala 72:15] + node _T_482 = mux(_T_481, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_483 = and(_T_482, abstractcs_reg) @[el2_dbg.scala 341:43] + node _T_484 = or(_T_479, _T_483) @[el2_dbg.scala 340:114] + node _T_485 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[el2_dbg.scala 341:87] + node _T_486 = bits(_T_485, 0, 0) @[Bitwise.scala 72:15] + node _T_487 = mux(_T_486, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_488 = and(_T_487, command_reg) @[el2_dbg.scala 341:100] + node _T_489 = or(_T_484, _T_488) @[el2_dbg.scala 341:60] + node _T_490 = eq(io.dmi_reg_addr, UInt<7>("h040")) @[el2_dbg.scala 342:30] + node _T_491 = bits(_T_490, 0, 0) @[Bitwise.scala 72:15] + node _T_492 = mux(_T_491, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_493 = and(_T_492, haltsum0_reg) @[el2_dbg.scala 342:43] + node _T_494 = or(_T_489, _T_493) @[el2_dbg.scala 341:114] + node _T_495 = eq(io.dmi_reg_addr, UInt<6>("h038")) @[el2_dbg.scala 342:85] + node _T_496 = bits(_T_495, 0, 0) @[Bitwise.scala 72:15] + node _T_497 = mux(_T_496, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_498 = and(_T_497, sbcs_reg) @[el2_dbg.scala 342:98] + node _T_499 = or(_T_494, _T_498) @[el2_dbg.scala 342:58] + node _T_500 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[el2_dbg.scala 343:30] + node _T_501 = bits(_T_500, 0, 0) @[Bitwise.scala 72:15] + node _T_502 = mux(_T_501, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_503 = and(_T_502, sbaddress0_reg) @[el2_dbg.scala 343:43] + node _T_504 = or(_T_499, _T_503) @[el2_dbg.scala 342:109] + node _T_505 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[el2_dbg.scala 343:87] + node _T_506 = bits(_T_505, 0, 0) @[Bitwise.scala 72:15] + node _T_507 = mux(_T_506, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_508 = and(_T_507, sbdata0_reg) @[el2_dbg.scala 343:100] + node _T_509 = or(_T_504, _T_508) @[el2_dbg.scala 343:60] + node _T_510 = eq(io.dmi_reg_addr, UInt<6>("h03d")) @[el2_dbg.scala 344:30] + node _T_511 = bits(_T_510, 0, 0) @[Bitwise.scala 72:15] + node _T_512 = mux(_T_511, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_513 = and(_T_512, sbdata1_reg) @[el2_dbg.scala 344:43] + node dmi_reg_rdata_din = or(_T_509, _T_513) @[el2_dbg.scala 343:114] + node _T_514 = asUInt(dbg_dm_rst_l) @[el2_dbg.scala 346:69] + node _T_515 = eq(_T_514, UInt<1>("h00")) @[el2_dbg.scala 346:49] + node _T_516 = and(_T_515, temp_rst) @[el2_dbg.scala 346:72] + node _T_517 = asAsyncReset(_T_516) @[el2_dbg.scala 346:96] + reg _T_518 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_517, UInt<1>("h00"))) @[Reg.scala 27:20] + when dbg_state_en : @[Reg.scala 28:19] + _T_518 <= dbg_nxtstate @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + dbg_state <= _T_518 @[el2_dbg.scala 346:13] + node _T_519 = asUInt(dbg_dm_rst_l) @[el2_dbg.scala 351:76] + node _T_520 = eq(_T_519, UInt<1>("h00")) @[el2_dbg.scala 351:56] + node _T_521 = asAsyncReset(_T_520) @[el2_dbg.scala 351:92] + reg _T_522 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_521, UInt<1>("h00"))) @[Reg.scala 27:20] + when io.dmi_reg_en : @[Reg.scala 28:19] + _T_522 <= dmi_reg_rdata_din @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.dmi_reg_rdata <= _T_522 @[el2_dbg.scala 351:20] + node _T_523 = bits(command_reg, 31, 24) @[el2_dbg.scala 355:38] + node _T_524 = eq(_T_523, UInt<2>("h02")) @[el2_dbg.scala 355:47] + node _T_525 = bits(data1_reg, 31, 2) @[el2_dbg.scala 355:73] + node _T_526 = cat(_T_525, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_527 = bits(command_reg, 11, 0) @[el2_dbg.scala 355:118] + node _T_528 = cat(UInt<20>("h00"), _T_527) @[Cat.scala 29:58] + node _T_529 = mux(_T_524, _T_526, _T_528) @[el2_dbg.scala 355:25] + io.dbg_cmd_addr <= _T_529 @[el2_dbg.scala 355:19] + node _T_530 = bits(data0_reg, 31, 0) @[el2_dbg.scala 356:33] + io.dbg_cmd_wrdata <= _T_530 @[el2_dbg.scala 356:21] + node _T_531 = eq(dbg_state, UInt<3>("h03")) @[el2_dbg.scala 357:35] + node _T_532 = bits(abstractcs_reg, 10, 8) @[el2_dbg.scala 357:76] + node _T_533 = orr(_T_532) @[el2_dbg.scala 357:84] + node _T_534 = eq(_T_533, UInt<1>("h00")) @[el2_dbg.scala 357:60] + node _T_535 = and(_T_531, _T_534) @[el2_dbg.scala 357:58] + node _T_536 = and(_T_535, io.dma_dbg_ready) @[el2_dbg.scala 357:89] + node _T_537 = bits(_T_536, 0, 0) @[el2_dbg.scala 357:115] + io.dbg_cmd_valid <= _T_537 @[el2_dbg.scala 357:20] + node _T_538 = bits(command_reg, 16, 16) @[el2_dbg.scala 358:34] + node _T_539 = bits(_T_538, 0, 0) @[el2_dbg.scala 358:45] + io.dbg_cmd_write <= _T_539 @[el2_dbg.scala 358:20] + node _T_540 = bits(command_reg, 31, 24) @[el2_dbg.scala 359:38] + node _T_541 = eq(_T_540, UInt<2>("h02")) @[el2_dbg.scala 359:47] + node _T_542 = bits(command_reg, 15, 12) @[el2_dbg.scala 359:93] + node _T_543 = eq(_T_542, UInt<1>("h00")) @[el2_dbg.scala 359:102] + node _T_544 = cat(UInt<1>("h00"), _T_543) @[Cat.scala 29:58] + node _T_545 = mux(_T_541, UInt<2>("h02"), _T_544) @[el2_dbg.scala 359:25] + io.dbg_cmd_type <= _T_545 @[el2_dbg.scala 359:19] + node _T_546 = bits(command_reg, 21, 20) @[el2_dbg.scala 360:33] + io.dbg_cmd_size <= _T_546 @[el2_dbg.scala 360:19] + node _T_547 = eq(dbg_state, UInt<3>("h03")) @[el2_dbg.scala 361:36] + node _T_548 = bits(abstractcs_reg, 10, 8) @[el2_dbg.scala 361:77] + node _T_549 = orr(_T_548) @[el2_dbg.scala 361:85] + node _T_550 = eq(_T_549, UInt<1>("h00")) @[el2_dbg.scala 361:61] + node _T_551 = and(_T_547, _T_550) @[el2_dbg.scala 361:59] + node _T_552 = eq(dbg_state, UInt<3>("h04")) @[el2_dbg.scala 361:103] + node _T_553 = or(_T_551, _T_552) @[el2_dbg.scala 361:90] + node _T_554 = bits(_T_553, 0, 0) @[el2_dbg.scala 361:132] + io.dbg_dma_bubble <= _T_554 @[el2_dbg.scala 361:21] + wire sb_nxtstate : UInt<4> + sb_nxtstate <= UInt<4>("h00") + sb_nxtstate <= UInt<4>("h00") @[el2_dbg.scala 364:15] + sbcs_sbbusy_wren <= UInt<1>("h00") @[el2_dbg.scala 366:20] + sbcs_sbbusy_din <= UInt<1>("h00") @[el2_dbg.scala 367:19] + sbcs_sberror_wren <= UInt<1>("h00") @[el2_dbg.scala 368:21] + sbcs_sberror_din <= UInt<3>("h00") @[el2_dbg.scala 369:20] + sbaddress0_reg_wren1 <= UInt<1>("h00") @[el2_dbg.scala 370:24] + node _T_555 = eq(UInt<4>("h00"), sb_state) @[Conditional.scala 37:30] + when _T_555 : @[Conditional.scala 40:58] + node _T_556 = mux(sbdata0wr_access, UInt<4>("h02"), UInt<4>("h01")) @[el2_dbg.scala 373:25] + sb_nxtstate <= _T_556 @[el2_dbg.scala 373:19] + node _T_557 = or(sbdata0wr_access, sbreadondata_access) @[el2_dbg.scala 374:39] + node _T_558 = or(_T_557, sbreadonaddr_access) @[el2_dbg.scala 374:61] + sb_state_en <= _T_558 @[el2_dbg.scala 374:19] + sbcs_sbbusy_wren <= sb_state_en @[el2_dbg.scala 375:24] + sbcs_sbbusy_din <= UInt<1>("h01") @[el2_dbg.scala 376:23] + node _T_559 = bits(io.dmi_reg_wdata, 14, 12) @[el2_dbg.scala 377:56] + node _T_560 = orr(_T_559) @[el2_dbg.scala 377:65] + node _T_561 = and(sbcs_wren, _T_560) @[el2_dbg.scala 377:38] + sbcs_sberror_wren <= _T_561 @[el2_dbg.scala 377:25] + node _T_562 = bits(io.dmi_reg_wdata, 14, 12) @[el2_dbg.scala 378:44] + node _T_563 = eq(_T_562, UInt<1>("h00")) @[el2_dbg.scala 378:27] + node _T_564 = bits(sbcs_reg, 14, 12) @[el2_dbg.scala 378:63] + node _T_565 = and(_T_563, _T_564) @[el2_dbg.scala 378:53] + sbcs_sberror_din <= _T_565 @[el2_dbg.scala 378:24] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_566 = eq(UInt<4>("h01"), sb_state) @[Conditional.scala 37:30] + when _T_566 : @[Conditional.scala 39:67] + node _T_567 = or(sbcs_unaligned, sbcs_illegal_size) @[el2_dbg.scala 381:41] + node _T_568 = mux(_T_567, UInt<4>("h09"), UInt<4>("h03")) @[el2_dbg.scala 381:25] + sb_nxtstate <= _T_568 @[el2_dbg.scala 381:19] + node _T_569 = or(io.dbg_bus_clk_en, sbcs_unaligned) @[el2_dbg.scala 382:40] + node _T_570 = or(_T_569, sbcs_illegal_size) @[el2_dbg.scala 382:57] + sb_state_en <= _T_570 @[el2_dbg.scala 382:19] + node _T_571 = or(sbcs_unaligned, sbcs_illegal_size) @[el2_dbg.scala 383:43] + sbcs_sberror_wren <= _T_571 @[el2_dbg.scala 383:25] + node _T_572 = mux(sbcs_unaligned, UInt<2>("h03"), UInt<3>("h04")) @[el2_dbg.scala 384:30] + sbcs_sberror_din <= _T_572 @[el2_dbg.scala 384:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_573 = eq(UInt<4>("h02"), sb_state) @[Conditional.scala 37:30] + when _T_573 : @[Conditional.scala 39:67] + node _T_574 = or(sbcs_unaligned, sbcs_illegal_size) @[el2_dbg.scala 387:41] + node _T_575 = mux(_T_574, UInt<4>("h09"), UInt<4>("h04")) @[el2_dbg.scala 387:25] + sb_nxtstate <= _T_575 @[el2_dbg.scala 387:19] + node _T_576 = or(io.dbg_bus_clk_en, sbcs_unaligned) @[el2_dbg.scala 388:40] + node _T_577 = or(_T_576, sbcs_illegal_size) @[el2_dbg.scala 388:57] + sb_state_en <= _T_577 @[el2_dbg.scala 388:19] + node _T_578 = or(sbcs_unaligned, sbcs_illegal_size) @[el2_dbg.scala 389:43] + sbcs_sberror_wren <= _T_578 @[el2_dbg.scala 389:25] + node _T_579 = mux(sbcs_unaligned, UInt<2>("h03"), UInt<3>("h04")) @[el2_dbg.scala 390:30] + sbcs_sberror_din <= _T_579 @[el2_dbg.scala 390:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_580 = eq(UInt<4>("h03"), sb_state) @[Conditional.scala 37:30] + when _T_580 : @[Conditional.scala 39:67] + sb_nxtstate <= UInt<4>("h07") @[el2_dbg.scala 393:19] + node _T_581 = and(sb_bus_cmd_read, io.dbg_bus_clk_en) @[el2_dbg.scala 394:38] + sb_state_en <= _T_581 @[el2_dbg.scala 394:19] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_582 = eq(UInt<4>("h04"), sb_state) @[Conditional.scala 37:30] + when _T_582 : @[Conditional.scala 39:67] + node _T_583 = and(sb_bus_cmd_write_addr, sb_bus_cmd_write_data) @[el2_dbg.scala 397:48] + node _T_584 = mux(sb_bus_cmd_write_data, UInt<4>("h05"), UInt<4>("h06")) @[el2_dbg.scala 397:95] + node _T_585 = mux(_T_583, UInt<4>("h08"), _T_584) @[el2_dbg.scala 397:25] + sb_nxtstate <= _T_585 @[el2_dbg.scala 397:19] + node _T_586 = or(sb_bus_cmd_write_addr, sb_bus_cmd_write_data) @[el2_dbg.scala 398:45] + node _T_587 = and(_T_586, io.dbg_bus_clk_en) @[el2_dbg.scala 398:70] + sb_state_en <= _T_587 @[el2_dbg.scala 398:19] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_588 = eq(UInt<4>("h05"), sb_state) @[Conditional.scala 37:30] + when _T_588 : @[Conditional.scala 39:67] + sb_nxtstate <= UInt<4>("h08") @[el2_dbg.scala 401:19] + node _T_589 = and(sb_bus_cmd_write_addr, io.dbg_bus_clk_en) @[el2_dbg.scala 402:44] + sb_state_en <= _T_589 @[el2_dbg.scala 402:19] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_590 = eq(UInt<4>("h06"), sb_state) @[Conditional.scala 37:30] + when _T_590 : @[Conditional.scala 39:67] + sb_nxtstate <= UInt<4>("h08") @[el2_dbg.scala 405:19] + node _T_591 = and(sb_bus_cmd_write_data, io.dbg_bus_clk_en) @[el2_dbg.scala 406:44] + sb_state_en <= _T_591 @[el2_dbg.scala 406:19] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_592 = eq(UInt<4>("h07"), sb_state) @[Conditional.scala 37:30] + when _T_592 : @[Conditional.scala 39:67] + sb_nxtstate <= UInt<4>("h09") @[el2_dbg.scala 409:19] + node _T_593 = and(sb_bus_rsp_read, io.dbg_bus_clk_en) @[el2_dbg.scala 410:38] + sb_state_en <= _T_593 @[el2_dbg.scala 410:19] + node _T_594 = and(sb_state_en, sb_bus_rsp_error) @[el2_dbg.scala 411:40] + sbcs_sberror_wren <= _T_594 @[el2_dbg.scala 411:25] + sbcs_sberror_din <= UInt<2>("h02") @[el2_dbg.scala 412:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_595 = eq(UInt<4>("h08"), sb_state) @[Conditional.scala 37:30] + when _T_595 : @[Conditional.scala 39:67] + sb_nxtstate <= UInt<4>("h09") @[el2_dbg.scala 415:19] + node _T_596 = and(sb_bus_rsp_write, io.dbg_bus_clk_en) @[el2_dbg.scala 416:39] + sb_state_en <= _T_596 @[el2_dbg.scala 416:19] + node _T_597 = and(sb_state_en, sb_bus_rsp_error) @[el2_dbg.scala 417:40] + sbcs_sberror_wren <= _T_597 @[el2_dbg.scala 417:25] + sbcs_sberror_din <= UInt<2>("h02") @[el2_dbg.scala 418:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_598 = eq(UInt<4>("h09"), sb_state) @[Conditional.scala 37:30] + when _T_598 : @[Conditional.scala 39:67] + sb_nxtstate <= UInt<4>("h00") @[el2_dbg.scala 421:19] + sb_state_en <= UInt<1>("h01") @[el2_dbg.scala 422:19] + sbcs_sbbusy_wren <= UInt<1>("h01") @[el2_dbg.scala 423:24] + sbcs_sbbusy_din <= UInt<1>("h00") @[el2_dbg.scala 424:23] + node _T_599 = bits(sbcs_reg, 16, 16) @[el2_dbg.scala 425:39] + sbaddress0_reg_wren1 <= _T_599 @[el2_dbg.scala 425:28] + skip @[Conditional.scala 39:67] + node _T_600 = asUInt(dbg_dm_rst_l) @[el2_dbg.scala 428:67] + node _T_601 = eq(_T_600, UInt<1>("h00")) @[el2_dbg.scala 428:47] + node _T_602 = asAsyncReset(_T_601) @[el2_dbg.scala 428:83] + reg _T_603 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_602, UInt<1>("h00"))) @[Reg.scala 27:20] + when sb_state_en : @[Reg.scala 28:19] + _T_603 <= sb_nxtstate @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + sb_state <= _T_603 @[el2_dbg.scala 428:12] + node _T_604 = and(io.sb_axi_arvalid, io.sb_axi_arready) @[el2_dbg.scala 432:40] + sb_bus_cmd_read <= _T_604 @[el2_dbg.scala 432:19] + node _T_605 = and(io.sb_axi_awvalid, io.sb_axi_awready) @[el2_dbg.scala 433:46] + sb_bus_cmd_write_addr <= _T_605 @[el2_dbg.scala 433:25] + node _T_606 = and(io.sb_axi_wvalid, io.sb_axi_wready) @[el2_dbg.scala 434:45] + sb_bus_cmd_write_data <= _T_606 @[el2_dbg.scala 434:25] + node _T_607 = and(io.sb_axi_rvalid, io.sb_axi_rready) @[el2_dbg.scala 435:39] + sb_bus_rsp_read <= _T_607 @[el2_dbg.scala 435:19] + node _T_608 = and(io.sb_axi_bvalid, io.sb_axi_bready) @[el2_dbg.scala 436:40] + sb_bus_rsp_write <= _T_608 @[el2_dbg.scala 436:20] + node _T_609 = bits(io.sb_axi_rresp, 1, 0) @[el2_dbg.scala 437:56] + node _T_610 = orr(_T_609) @[el2_dbg.scala 437:63] + node _T_611 = and(sb_bus_rsp_read, _T_610) @[el2_dbg.scala 437:39] + node _T_612 = bits(io.sb_axi_bresp, 1, 0) @[el2_dbg.scala 437:103] + node _T_613 = orr(_T_612) @[el2_dbg.scala 437:110] + node _T_614 = and(sb_bus_rsp_write, _T_613) @[el2_dbg.scala 437:86] + node _T_615 = or(_T_611, _T_614) @[el2_dbg.scala 437:67] + sb_bus_rsp_error <= _T_615 @[el2_dbg.scala 437:20] + node _T_616 = eq(sb_state, UInt<4>("h04")) @[el2_dbg.scala 438:35] + node _T_617 = eq(sb_state, UInt<4>("h05")) @[el2_dbg.scala 438:70] + node _T_618 = or(_T_616, _T_617) @[el2_dbg.scala 438:58] + node _T_619 = bits(_T_618, 0, 0) @[el2_dbg.scala 438:105] + io.sb_axi_awvalid <= _T_619 @[el2_dbg.scala 438:21] + io.sb_axi_awaddr <= sbaddress0_reg @[el2_dbg.scala 439:20] + io.sb_axi_awid <= UInt<1>("h00") @[el2_dbg.scala 440:18] + node _T_620 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 441:31] + io.sb_axi_awsize <= _T_620 @[el2_dbg.scala 441:20] + io.sb_axi_awprot <= UInt<1>("h00") @[el2_dbg.scala 442:20] + io.sb_axi_awcache <= UInt<4>("h0f") @[el2_dbg.scala 443:21] + node _T_621 = bits(sbaddress0_reg, 31, 28) @[el2_dbg.scala 444:39] + io.sb_axi_awregion <= _T_621 @[el2_dbg.scala 444:22] + io.sb_axi_awlen <= UInt<1>("h00") @[el2_dbg.scala 445:19] + io.sb_axi_awburst <= UInt<1>("h01") @[el2_dbg.scala 446:21] + io.sb_axi_awqos <= UInt<1>("h00") @[el2_dbg.scala 447:19] + io.sb_axi_awlock <= UInt<1>("h00") @[el2_dbg.scala 448:20] + node _T_622 = eq(sb_state, UInt<4>("h04")) @[el2_dbg.scala 449:34] + node _T_623 = eq(sb_state, UInt<4>("h06")) @[el2_dbg.scala 449:69] + node _T_624 = or(_T_622, _T_623) @[el2_dbg.scala 449:57] + node _T_625 = bits(_T_624, 0, 0) @[el2_dbg.scala 449:104] + io.sb_axi_wvalid <= _T_625 @[el2_dbg.scala 449:20] + node _T_626 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 450:40] + node _T_627 = eq(_T_626, UInt<1>("h00")) @[el2_dbg.scala 450:49] + node _T_628 = bits(_T_627, 0, 0) @[Bitwise.scala 72:15] + node _T_629 = mux(_T_628, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] + node _T_630 = bits(sbdata0_reg, 7, 0) @[el2_dbg.scala 450:81] + node _T_631 = cat(_T_630, _T_630) @[Cat.scala 29:58] + node _T_632 = cat(_T_631, _T_631) @[Cat.scala 29:58] + node _T_633 = cat(_T_632, _T_632) @[Cat.scala 29:58] + node _T_634 = and(_T_629, _T_633) @[el2_dbg.scala 450:59] + node _T_635 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 450:110] + node _T_636 = eq(_T_635, UInt<1>("h01")) @[el2_dbg.scala 450:119] + node _T_637 = bits(_T_636, 0, 0) @[Bitwise.scala 72:15] + node _T_638 = mux(_T_637, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] + node _T_639 = bits(sbdata0_reg, 15, 0) @[el2_dbg.scala 450:153] + node _T_640 = cat(_T_639, _T_639) @[Cat.scala 29:58] + node _T_641 = cat(_T_640, _T_640) @[Cat.scala 29:58] + node _T_642 = and(_T_638, _T_641) @[el2_dbg.scala 450:132] + node _T_643 = or(_T_634, _T_642) @[el2_dbg.scala 450:90] + node _T_644 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 451:23] + node _T_645 = eq(_T_644, UInt<2>("h02")) @[el2_dbg.scala 451:32] + node _T_646 = bits(_T_645, 0, 0) @[Bitwise.scala 72:15] + node _T_647 = mux(_T_646, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] + node _T_648 = bits(sbdata0_reg, 31, 0) @[el2_dbg.scala 451:67] + node _T_649 = cat(_T_648, _T_648) @[Cat.scala 29:58] + node _T_650 = and(_T_647, _T_649) @[el2_dbg.scala 451:45] + node _T_651 = or(_T_643, _T_650) @[el2_dbg.scala 450:162] + node _T_652 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 451:97] + node _T_653 = eq(_T_652, UInt<2>("h03")) @[el2_dbg.scala 451:106] + node _T_654 = bits(_T_653, 0, 0) @[Bitwise.scala 72:15] + node _T_655 = mux(_T_654, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] + node _T_656 = bits(sbdata1_reg, 31, 0) @[el2_dbg.scala 451:136] + node _T_657 = bits(sbdata0_reg, 31, 0) @[el2_dbg.scala 451:156] + node _T_658 = cat(_T_656, _T_657) @[Cat.scala 29:58] + node _T_659 = and(_T_655, _T_658) @[el2_dbg.scala 451:119] + node _T_660 = or(_T_651, _T_659) @[el2_dbg.scala 451:77] + io.sb_axi_wdata <= _T_660 @[el2_dbg.scala 450:19] + node _T_661 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 453:39] + node _T_662 = eq(_T_661, UInt<1>("h00")) @[el2_dbg.scala 453:48] + node _T_663 = bits(_T_662, 0, 0) @[Bitwise.scala 72:15] + node _T_664 = mux(_T_663, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_665 = bits(sbaddress0_reg, 2, 0) @[el2_dbg.scala 453:93] + node _T_666 = dshl(UInt<8>("h01"), _T_665) @[el2_dbg.scala 453:76] + node _T_667 = and(_T_664, _T_666) @[el2_dbg.scala 453:61] + node _T_668 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 454:22] + node _T_669 = eq(_T_668, UInt<1>("h01")) @[el2_dbg.scala 454:31] + node _T_670 = bits(_T_669, 0, 0) @[Bitwise.scala 72:15] + node _T_671 = mux(_T_670, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_672 = bits(sbaddress0_reg, 2, 1) @[el2_dbg.scala 454:80] + node _T_673 = cat(_T_672, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_674 = dshl(UInt<8>("h03"), _T_673) @[el2_dbg.scala 454:59] + node _T_675 = and(_T_671, _T_674) @[el2_dbg.scala 454:44] + node _T_676 = or(_T_667, _T_675) @[el2_dbg.scala 453:101] + node _T_677 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 455:22] + node _T_678 = eq(_T_677, UInt<2>("h02")) @[el2_dbg.scala 455:31] + node _T_679 = bits(_T_678, 0, 0) @[Bitwise.scala 72:15] + node _T_680 = mux(_T_679, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_681 = bits(sbaddress0_reg, 2, 2) @[el2_dbg.scala 455:80] + node _T_682 = cat(_T_681, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_683 = dshl(UInt<8>("h0f"), _T_682) @[el2_dbg.scala 455:59] + node _T_684 = and(_T_680, _T_683) @[el2_dbg.scala 455:44] + node _T_685 = or(_T_676, _T_684) @[el2_dbg.scala 454:97] + node _T_686 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 456:22] + node _T_687 = eq(_T_686, UInt<2>("h03")) @[el2_dbg.scala 456:31] + node _T_688 = bits(_T_687, 0, 0) @[Bitwise.scala 72:15] + node _T_689 = mux(_T_688, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_690 = and(_T_689, UInt<8>("h0ff")) @[el2_dbg.scala 456:44] + node _T_691 = or(_T_685, _T_690) @[el2_dbg.scala 455:95] + io.sb_axi_wstrb <= _T_691 @[el2_dbg.scala 453:19] + io.sb_axi_wlast <= UInt<1>("h01") @[el2_dbg.scala 458:19] + node _T_692 = eq(sb_state, UInt<4>("h03")) @[el2_dbg.scala 459:34] + node _T_693 = bits(_T_692, 0, 0) @[el2_dbg.scala 459:63] + io.sb_axi_arvalid <= _T_693 @[el2_dbg.scala 459:21] + io.sb_axi_araddr <= sbaddress0_reg @[el2_dbg.scala 460:20] + io.sb_axi_arid <= UInt<1>("h00") @[el2_dbg.scala 461:18] + node _T_694 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 462:31] + io.sb_axi_arsize <= _T_694 @[el2_dbg.scala 462:20] + io.sb_axi_arprot <= UInt<1>("h00") @[el2_dbg.scala 463:20] + io.sb_axi_arcache <= UInt<1>("h00") @[el2_dbg.scala 464:21] + node _T_695 = bits(sbaddress0_reg, 31, 28) @[el2_dbg.scala 465:39] + io.sb_axi_arregion <= _T_695 @[el2_dbg.scala 465:22] + io.sb_axi_arlen <= UInt<1>("h00") @[el2_dbg.scala 466:19] + io.sb_axi_arburst <= UInt<1>("h01") @[el2_dbg.scala 467:21] + io.sb_axi_arqos <= UInt<1>("h00") @[el2_dbg.scala 468:19] + io.sb_axi_arlock <= UInt<1>("h00") @[el2_dbg.scala 469:20] + io.sb_axi_bready <= UInt<1>("h01") @[el2_dbg.scala 470:20] + io.sb_axi_rready <= UInt<1>("h01") @[el2_dbg.scala 471:20] + node _T_696 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 472:37] + node _T_697 = eq(_T_696, UInt<1>("h00")) @[el2_dbg.scala 472:46] + node _T_698 = bits(_T_697, 0, 0) @[Bitwise.scala 72:15] + node _T_699 = mux(_T_698, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] + node _T_700 = bits(io.sb_axi_rdata, 63, 0) @[el2_dbg.scala 472:78] + node _T_701 = bits(sbaddress0_reg, 2, 0) @[el2_dbg.scala 472:109] + node _T_702 = mul(UInt<4>("h08"), _T_701) @[el2_dbg.scala 472:93] + node _T_703 = dshr(_T_700, _T_702) @[el2_dbg.scala 472:86] + node _T_704 = and(_T_703, UInt<64>("h0ff")) @[el2_dbg.scala 472:117] + node _T_705 = and(_T_699, _T_704) @[el2_dbg.scala 472:59] + node _T_706 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 473:23] + node _T_707 = eq(_T_706, UInt<1>("h01")) @[el2_dbg.scala 473:32] + node _T_708 = bits(_T_707, 0, 0) @[Bitwise.scala 72:15] + node _T_709 = mux(_T_708, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] + node _T_710 = bits(io.sb_axi_rdata, 63, 0) @[el2_dbg.scala 473:64] + node _T_711 = bits(sbaddress0_reg, 2, 1) @[el2_dbg.scala 473:96] + node _T_712 = mul(UInt<5>("h010"), _T_711) @[el2_dbg.scala 473:80] + node _T_713 = dshr(_T_710, _T_712) @[el2_dbg.scala 473:72] + node _T_714 = and(_T_713, UInt<64>("h0ffff")) @[el2_dbg.scala 473:104] + node _T_715 = and(_T_709, _T_714) @[el2_dbg.scala 473:45] + node _T_716 = or(_T_705, _T_715) @[el2_dbg.scala 472:134] + node _T_717 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 474:23] + node _T_718 = eq(_T_717, UInt<2>("h02")) @[el2_dbg.scala 474:32] + node _T_719 = bits(_T_718, 0, 0) @[Bitwise.scala 72:15] + node _T_720 = mux(_T_719, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] + node _T_721 = bits(io.sb_axi_rdata, 63, 0) @[el2_dbg.scala 474:64] + node _T_722 = bits(sbaddress0_reg, 2, 2) @[el2_dbg.scala 474:96] + node _T_723 = mul(UInt<6>("h020"), _T_722) @[el2_dbg.scala 474:80] + node _T_724 = dshr(_T_721, _T_723) @[el2_dbg.scala 474:72] + node _T_725 = and(_T_724, UInt<64>("h0ffffffff")) @[el2_dbg.scala 474:101] + node _T_726 = and(_T_720, _T_725) @[el2_dbg.scala 474:45] + node _T_727 = or(_T_716, _T_726) @[el2_dbg.scala 473:123] + node _T_728 = bits(sbcs_reg, 19, 17) @[el2_dbg.scala 475:23] + node _T_729 = eq(_T_728, UInt<2>("h03")) @[el2_dbg.scala 475:32] + node _T_730 = bits(_T_729, 0, 0) @[Bitwise.scala 72:15] + node _T_731 = mux(_T_730, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] + node _T_732 = bits(io.sb_axi_rdata, 63, 0) @[el2_dbg.scala 475:62] + node _T_733 = and(_T_731, _T_732) @[el2_dbg.scala 475:45] + node _T_734 = or(_T_727, _T_733) @[el2_dbg.scala 474:125] + sb_bus_rdata <= _T_734 @[el2_dbg.scala 472:16] + diff --git a/el2_dbg.v b/el2_dbg.v new file mode 100644 index 00000000..186d3ace --- /dev/null +++ b/el2_dbg.v @@ -0,0 +1,1170 @@ +module rvclkhdr( + output io_l1clk, + input io_clk, + input io_en, + input io_scan_mode +); + wire clkhdr_Q; // @[el2_lib.scala 474:26] + wire clkhdr_CK; // @[el2_lib.scala 474:26] + wire clkhdr_EN; // @[el2_lib.scala 474:26] + wire clkhdr_SE; // @[el2_lib.scala 474:26] + gated_latch clkhdr ( // @[el2_lib.scala 474:26] + .Q(clkhdr_Q), + .CK(clkhdr_CK), + .EN(clkhdr_EN), + .SE(clkhdr_SE) + ); + assign io_l1clk = clkhdr_Q; // @[el2_lib.scala 475:14] + assign clkhdr_CK = io_clk; // @[el2_lib.scala 476:18] + assign clkhdr_EN = io_en; // @[el2_lib.scala 477:18] + assign clkhdr_SE = io_scan_mode; // @[el2_lib.scala 478:18] +endmodule +module el2_dbg( + input clock, + input reset, + output [31:0] io_dbg_cmd_addr, + output [31:0] io_dbg_cmd_wrdata, + output io_dbg_cmd_valid, + output io_dbg_cmd_write, + output [1:0] io_dbg_cmd_type, + output [1:0] io_dbg_cmd_size, + output io_dbg_core_rst_l, + input [31:0] io_core_dbg_rddata, + input io_core_dbg_cmd_done, + input io_core_dbg_cmd_fail, + output io_dbg_dma_bubble, + input io_dma_dbg_ready, + output io_dbg_halt_req, + output io_dbg_resume_req, + input io_dec_tlu_debug_mode, + input io_dec_tlu_dbg_halted, + input io_dec_tlu_mpc_halted_only, + input io_dec_tlu_resume_ack, + input io_dmi_reg_en, + input [6:0] io_dmi_reg_addr, + input io_dmi_reg_wr_en, + input [31:0] io_dmi_reg_wdata, + output [31:0] io_dmi_reg_rdata, + output io_sb_axi_awvalid, + input io_sb_axi_awready, + output io_sb_axi_awid, + output [31:0] io_sb_axi_awaddr, + output [3:0] io_sb_axi_awregion, + output [7:0] io_sb_axi_awlen, + output [2:0] io_sb_axi_awsize, + output [1:0] io_sb_axi_awburst, + output io_sb_axi_awlock, + output [3:0] io_sb_axi_awcache, + output [2:0] io_sb_axi_awprot, + output [3:0] io_sb_axi_awqos, + output io_sb_axi_wvalid, + input io_sb_axi_wready, + output [63:0] io_sb_axi_wdata, + output [7:0] io_sb_axi_wstrb, + output io_sb_axi_wlast, + input io_sb_axi_bvalid, + output io_sb_axi_bready, + input [1:0] io_sb_axi_bresp, + output io_sb_axi_arvalid, + input io_sb_axi_arready, + output io_sb_axi_arid, + output [31:0] io_sb_axi_araddr, + output [3:0] io_sb_axi_arregion, + output [7:0] io_sb_axi_arlen, + output [2:0] io_sb_axi_arsize, + output [1:0] io_sb_axi_arburst, + output io_sb_axi_arlock, + output [3:0] io_sb_axi_arcache, + output [2:0] io_sb_axi_arprot, + output [3:0] io_sb_axi_arqos, + input io_sb_axi_rvalid, + output io_sb_axi_rready, + input [63:0] io_sb_axi_rdata, + input [1:0] io_sb_axi_rresp, + input io_dbg_bus_clk_en, + input io_dbg_rst_l, + input io_clk_override, + input io_scan_mode +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; + reg [31:0] _RAND_13; + reg [31:0] _RAND_14; + reg [31:0] _RAND_15; + reg [31:0] _RAND_16; + reg [31:0] _RAND_17; + reg [31:0] _RAND_18; + reg [31:0] _RAND_19; + reg [31:0] _RAND_20; + reg [31:0] _RAND_21; +`endif // RANDOMIZE_REG_INIT + wire [2:0] dbg_state; + wire dbg_state_en; + wire [3:0] sb_state; + wire sb_state_en; + wire [31:0] dmcontrol_reg; + wire [31:0] sbaddress0_reg; + wire sbcs_sbbusy_wren; + wire sbcs_sberror_wren; + wire [63:0] sb_bus_rdata; + wire sbaddress0_reg_wren1; + wire [31:0] dmstatus_reg; + wire dmstatus_havereset; + wire dmstatus_resumeack; + wire dmstatus_unavail; + wire dmstatus_running; + wire dmstatus_halted; + wire abstractcs_busy_wren; + wire sb_bus_cmd_read; + wire sb_bus_cmd_write_addr; + wire sb_bus_cmd_write_data; + wire sb_bus_rsp_read; + wire sb_bus_rsp_error; + wire sb_bus_rsp_write; + wire sbcs_sbbusy_din; + wire [31:0] data1_reg; + wire [31:0] sbcs_reg; + wire _T = dbg_state != 3'h0; // @[el2_dbg.scala 126:51] + wire _T_1 = io_dmi_reg_en | _T; // @[el2_dbg.scala 126:38] + wire _T_2 = _T_1 | dbg_state_en; // @[el2_dbg.scala 126:69] + wire _T_3 = _T_2 | io_dec_tlu_dbg_halted; // @[el2_dbg.scala 126:84] + wire _T_4 = io_dmi_reg_en | sb_state_en; // @[el2_dbg.scala 127:37] + wire _T_5 = sb_state != 4'h0; // @[el2_dbg.scala 127:63] + wire _T_6 = _T_4 | _T_5; // @[el2_dbg.scala 127:51] + wire rvclkhdr_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_1_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_1_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 483:22] + wire _T_9 = dmcontrol_reg[0] | io_scan_mode; // @[el2_dbg.scala 130:65] + wire _T_12 = ~dmcontrol_reg[1]; // @[el2_dbg.scala 131:25] + wire _T_14 = io_dmi_reg_addr == 7'h38; // @[el2_dbg.scala 132:36] + wire _T_15 = _T_14 & io_dmi_reg_en; // @[el2_dbg.scala 132:49] + wire _T_16 = _T_15 & io_dmi_reg_wr_en; // @[el2_dbg.scala 132:65] + wire _T_17 = sb_state == 4'h0; // @[el2_dbg.scala 132:96] + wire sbcs_wren = _T_16 & _T_17; // @[el2_dbg.scala 132:84] + wire _T_19 = sbcs_wren & io_dmi_reg_wdata[22]; // @[el2_dbg.scala 133:42] + wire _T_21 = _T_5 & io_dmi_reg_en; // @[el2_dbg.scala 133:102] + wire _T_22 = io_dmi_reg_addr == 7'h39; // @[el2_dbg.scala 134:23] + wire _T_23 = io_dmi_reg_addr == 7'h3c; // @[el2_dbg.scala 134:55] + wire _T_24 = _T_22 | _T_23; // @[el2_dbg.scala 134:36] + wire _T_25 = io_dmi_reg_addr == 7'h3d; // @[el2_dbg.scala 134:87] + wire _T_26 = _T_24 | _T_25; // @[el2_dbg.scala 134:68] + wire _T_27 = _T_21 & _T_26; // @[el2_dbg.scala 133:118] + wire sbcs_sbbusyerror_wren = _T_19 | _T_27; // @[el2_dbg.scala 133:66] + wire sbcs_sbbusyerror_din = ~_T_19; // @[el2_dbg.scala 136:31] + wire _T_30 = io_dbg_rst_l & _T_9; // @[el2_dbg.scala 137:74] + wire _T_31 = ~_T_30; // @[el2_dbg.scala 137:54] + wire _T_32 = ~_T_30; // @[el2_dbg.scala 137:90] + reg temp_sbcs_22; // @[Reg.scala 27:20] + reg temp_sbcs_21; // @[Reg.scala 27:20] + reg temp_sbcs_20; // @[Reg.scala 27:20] + reg [4:0] temp_sbcs_19_15; // @[Reg.scala 27:20] + reg [2:0] temp_sbcs_14_12; // @[Reg.scala 27:20] + wire [19:0] _T_50 = {temp_sbcs_19_15,temp_sbcs_14_12,12'h40f}; // @[Cat.scala 29:58] + wire [11:0] _T_54 = {9'h40,temp_sbcs_22,temp_sbcs_21,temp_sbcs_20}; // @[Cat.scala 29:58] + wire _T_57 = sbcs_reg[19:17] == 3'h1; // @[el2_dbg.scala 158:42] + wire _T_59 = _T_57 & sbaddress0_reg[0]; // @[el2_dbg.scala 158:56] + wire _T_61 = sbcs_reg[19:17] == 3'h2; // @[el2_dbg.scala 159:23] + wire _T_63 = |sbaddress0_reg[1:0]; // @[el2_dbg.scala 159:60] + wire _T_64 = _T_61 & _T_63; // @[el2_dbg.scala 159:37] + wire _T_65 = _T_59 | _T_64; // @[el2_dbg.scala 158:76] + wire _T_67 = sbcs_reg[19:17] == 3'h3; // @[el2_dbg.scala 160:23] + wire _T_69 = |sbaddress0_reg[2:0]; // @[el2_dbg.scala 160:60] + wire _T_70 = _T_67 & _T_69; // @[el2_dbg.scala 160:37] + wire sbcs_unaligned = _T_65 | _T_70; // @[el2_dbg.scala 159:64] + wire sbcs_illegal_size = sbcs_reg[19]; // @[el2_dbg.scala 162:35] + wire _T_72 = sbcs_reg[19:17] == 3'h0; // @[el2_dbg.scala 163:51] + wire [3:0] _T_74 = _T_72 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_75 = _T_74 & 4'h1; // @[el2_dbg.scala 163:64] + wire [3:0] _T_79 = _T_57 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_80 = _T_79 & 4'h2; // @[el2_dbg.scala 163:117] + wire [3:0] _T_81 = _T_75 | _T_80; // @[el2_dbg.scala 163:76] + wire [3:0] _T_85 = _T_61 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_86 = _T_85 & 4'h4; // @[el2_dbg.scala 164:44] + wire [3:0] _T_87 = _T_81 | _T_86; // @[el2_dbg.scala 163:129] + wire [3:0] _T_91 = _T_67 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_92 = _T_91 & 4'h8; // @[el2_dbg.scala 164:97] + wire [3:0] sbaddress0_incr = _T_87 | _T_92; // @[el2_dbg.scala 164:56] + wire _T_93 = io_dmi_reg_en & io_dmi_reg_wr_en; // @[el2_dbg.scala 166:41] + wire sbdata0_reg_wren0 = _T_93 & _T_23; // @[el2_dbg.scala 166:60] + wire _T_95 = sb_state == 4'h7; // @[el2_dbg.scala 167:37] + wire _T_96 = _T_95 & sb_state_en; // @[el2_dbg.scala 167:60] + wire _T_97 = ~sbcs_sberror_wren; // @[el2_dbg.scala 167:76] + wire sbdata0_reg_wren1 = _T_96 & _T_97; // @[el2_dbg.scala 167:74] + wire sbdata1_reg_wren0 = _T_93 & _T_25; // @[el2_dbg.scala 169:60] + wire [31:0] _T_104 = sbdata0_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_105 = _T_104 & io_dmi_reg_wdata; // @[el2_dbg.scala 172:49] + wire [31:0] _T_107 = sbdata0_reg_wren1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_109 = _T_107 & sb_bus_rdata[31:0]; // @[el2_dbg.scala 173:33] + wire [31:0] _T_111 = sbdata1_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_112 = _T_111 & io_dmi_reg_wdata; // @[el2_dbg.scala 175:49] + wire [31:0] _T_116 = _T_107 & sb_bus_rdata[63:32]; // @[el2_dbg.scala 176:33] + wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_2_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_2_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 508:23] + reg [31:0] sbdata0_reg; // @[el2_lib.scala 514:16] + wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 508:23] + reg [31:0] sbdata1_reg; // @[el2_lib.scala 514:16] + wire sbaddress0_reg_wren0 = _T_93 & _T_22; // @[el2_dbg.scala 186:63] + wire [31:0] _T_126 = sbaddress0_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_127 = _T_126 & io_dmi_reg_wdata; // @[el2_dbg.scala 188:59] + wire [31:0] _T_129 = sbaddress0_reg_wren1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_130 = {28'h0,sbaddress0_incr}; // @[Cat.scala 29:58] + wire [31:0] _T_132 = sbaddress0_reg + _T_130; // @[el2_dbg.scala 189:54] + wire [31:0] _T_133 = _T_129 & _T_132; // @[el2_dbg.scala 189:36] + wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_4_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_4_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 508:23] + reg [31:0] _T_137; // @[el2_lib.scala 514:16] + wire sbreadonaddr_access = sbaddress0_reg_wren0 & sbcs_reg[20]; // @[el2_dbg.scala 194:94] + wire _T_142 = ~io_dmi_reg_wr_en; // @[el2_dbg.scala 195:45] + wire _T_143 = io_dmi_reg_en & _T_142; // @[el2_dbg.scala 195:43] + wire _T_145 = _T_143 & _T_23; // @[el2_dbg.scala 195:63] + wire sbreadondata_access = _T_145 & sbcs_reg[15]; // @[el2_dbg.scala 195:95] + wire _T_149 = io_dmi_reg_addr == 7'h10; // @[el2_dbg.scala 197:41] + wire _T_150 = _T_149 & io_dmi_reg_en; // @[el2_dbg.scala 197:54] + wire dmcontrol_wren = _T_150 & io_dmi_reg_wr_en; // @[el2_dbg.scala 197:70] + wire [3:0] _T_158 = {io_dmi_reg_wdata[31:30],io_dmi_reg_wdata[28],io_dmi_reg_wdata[1]}; // @[Cat.scala 29:58] + reg [3:0] dm_temp; // @[Reg.scala 27:20] + reg dm_temp_0; // @[Reg.scala 27:20] + wire [27:0] _T_164 = {26'h0,dm_temp[0],dm_temp_0}; // @[Cat.scala 29:58] + wire [3:0] _T_166 = {dm_temp[3:2],1'h0,dm_temp[1]}; // @[Cat.scala 29:58] + reg dmcontrol_wren_Q; // @[el2_dbg.scala 212:12] + wire [1:0] _T_171 = dmstatus_havereset ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_173 = dmstatus_resumeack ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_175 = dmstatus_unavail ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_177 = dmstatus_running ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_179 = dmstatus_halted ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [11:0] _T_183 = {_T_177,_T_179,1'h1,7'h2}; // @[Cat.scala 29:58] + wire [19:0] _T_187 = {12'h0,_T_171,_T_173,2'h0,_T_175}; // @[Cat.scala 29:58] + wire _T_189 = dbg_state == 3'h6; // @[el2_dbg.scala 217:44] + wire _T_190 = _T_189 & io_dec_tlu_resume_ack; // @[el2_dbg.scala 217:66] + wire _T_192 = ~dmcontrol_reg[30]; // @[el2_dbg.scala 217:113] + wire _T_193 = dmstatus_resumeack & _T_192; // @[el2_dbg.scala 217:111] + wire dmstatus_resumeack_wren = _T_190 | _T_193; // @[el2_dbg.scala 217:90] + wire _T_197 = _T_149 & io_dmi_reg_wdata[1]; // @[el2_dbg.scala 219:63] + wire _T_198 = _T_197 & io_dmi_reg_en; // @[el2_dbg.scala 219:85] + wire dmstatus_havereset_wren = _T_198 & io_dmi_reg_wr_en; // @[el2_dbg.scala 219:101] + wire _T_201 = _T_149 & io_dmi_reg_wdata[28]; // @[el2_dbg.scala 220:62] + wire _T_202 = _T_201 & io_dmi_reg_en; // @[el2_dbg.scala 220:85] + wire dmstatus_havereset_rst = _T_202 & io_dmi_reg_wr_en; // @[el2_dbg.scala 220:101] + wire _T_204 = ~reset; // @[el2_dbg.scala 222:43] + wire _T_207 = dmstatus_unavail | dmstatus_halted; // @[el2_dbg.scala 223:42] + reg _T_212; // @[Reg.scala 27:20] + wire _T_216 = ~io_dec_tlu_mpc_halted_only; // @[el2_dbg.scala 229:37] + reg _T_218; // @[el2_dbg.scala 229:12] + wire _T_222 = ~dmstatus_havereset_rst; // @[el2_dbg.scala 233:15] + reg _T_223; // @[Reg.scala 27:20] + wire [31:0] haltsum0_reg = {31'h0,dmstatus_halted}; // @[Cat.scala 29:58] + wire [31:0] abstractcs_reg; + wire _T_225 = abstractcs_reg[12] & io_dmi_reg_en; // @[el2_dbg.scala 239:50] + wire _T_226 = io_dmi_reg_addr == 7'h16; // @[el2_dbg.scala 239:106] + wire _T_227 = io_dmi_reg_addr == 7'h17; // @[el2_dbg.scala 239:138] + wire _T_228 = _T_226 | _T_227; // @[el2_dbg.scala 239:119] + wire _T_229 = io_dmi_reg_wr_en & _T_228; // @[el2_dbg.scala 239:86] + wire _T_230 = io_dmi_reg_addr == 7'h4; // @[el2_dbg.scala 239:171] + wire _T_231 = _T_229 | _T_230; // @[el2_dbg.scala 239:152] + wire abstractcs_error_sel0 = _T_225 & _T_231; // @[el2_dbg.scala 239:66] + wire _T_234 = _T_93 & _T_227; // @[el2_dbg.scala 240:64] + wire _T_236 = io_dmi_reg_wdata[31:24] == 8'h0; // @[el2_dbg.scala 240:126] + wire _T_238 = io_dmi_reg_wdata[31:24] == 8'h2; // @[el2_dbg.scala 240:163] + wire _T_239 = _T_236 | _T_238; // @[el2_dbg.scala 240:135] + wire _T_240 = ~_T_239; // @[el2_dbg.scala 240:98] + wire abstractcs_error_sel1 = _T_234 & _T_240; // @[el2_dbg.scala 240:96] + wire abstractcs_error_sel2 = io_core_dbg_cmd_done & io_core_dbg_cmd_fail; // @[el2_dbg.scala 241:52] + wire _T_245 = ~dmstatus_reg[9]; // @[el2_dbg.scala 242:98] + wire abstractcs_error_sel3 = _T_234 & _T_245; // @[el2_dbg.scala 242:96] + wire _T_247 = _T_227 & io_dmi_reg_en; // @[el2_dbg.scala 243:61] + wire _T_248 = _T_247 & io_dmi_reg_wr_en; // @[el2_dbg.scala 243:77] + wire _T_250 = io_dmi_reg_wdata[22:20] != 3'h2; // @[el2_dbg.scala 244:32] + wire _T_254 = |data1_reg[1:0]; // @[el2_dbg.scala 244:106] + wire _T_255 = _T_238 & _T_254; // @[el2_dbg.scala 244:87] + wire _T_256 = _T_250 | _T_255; // @[el2_dbg.scala 244:46] + wire abstractcs_error_sel4 = _T_248 & _T_256; // @[el2_dbg.scala 243:96] + wire _T_258 = _T_226 & io_dmi_reg_en; // @[el2_dbg.scala 246:61] + wire abstractcs_error_sel5 = _T_258 & io_dmi_reg_wr_en; // @[el2_dbg.scala 246:77] + wire _T_259 = abstractcs_error_sel0 | abstractcs_error_sel1; // @[el2_dbg.scala 247:54] + wire _T_260 = _T_259 | abstractcs_error_sel2; // @[el2_dbg.scala 247:78] + wire _T_261 = _T_260 | abstractcs_error_sel3; // @[el2_dbg.scala 247:102] + wire _T_262 = _T_261 | abstractcs_error_sel4; // @[el2_dbg.scala 247:126] + wire abstractcs_error_selor = _T_262 | abstractcs_error_sel5; // @[el2_dbg.scala 247:150] + wire [2:0] _T_264 = abstractcs_error_sel0 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_265 = _T_264 & 3'h1; // @[el2_dbg.scala 248:62] + wire [2:0] _T_267 = abstractcs_error_sel1 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_268 = _T_267 & 3'h2; // @[el2_dbg.scala 249:37] + wire [2:0] _T_269 = _T_265 | _T_268; // @[el2_dbg.scala 248:74] + wire [2:0] _T_271 = abstractcs_error_sel2 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_272 = _T_271 & 3'h3; // @[el2_dbg.scala 250:37] + wire [2:0] _T_273 = _T_269 | _T_272; // @[el2_dbg.scala 249:49] + wire [2:0] _T_275 = abstractcs_error_sel3 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_276 = _T_275 & 3'h4; // @[el2_dbg.scala 251:37] + wire [2:0] _T_277 = _T_273 | _T_276; // @[el2_dbg.scala 250:49] + wire [2:0] _T_279 = abstractcs_error_sel4 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_281 = _T_277 | _T_279; // @[el2_dbg.scala 251:49] + wire [2:0] _T_283 = abstractcs_error_sel5 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_285 = ~io_dmi_reg_wdata[10:8]; // @[el2_dbg.scala 253:40] + wire [2:0] _T_286 = _T_283 & _T_285; // @[el2_dbg.scala 253:37] + wire [2:0] _T_288 = _T_286 & abstractcs_reg[10:8]; // @[el2_dbg.scala 253:75] + wire [2:0] _T_289 = _T_281 | _T_288; // @[el2_dbg.scala 252:49] + wire _T_290 = ~abstractcs_error_selor; // @[el2_dbg.scala 254:15] + wire [2:0] _T_292 = _T_290 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_294 = _T_292 & abstractcs_reg[10:8]; // @[el2_dbg.scala 254:50] + reg abs_temp_12; // @[Reg.scala 27:20] + reg [2:0] abs_temp_10_8; // @[el2_dbg.scala 261:12] + wire [10:0] _T_302 = {abs_temp_10_8,8'h2}; // @[Cat.scala 29:58] + wire [20:0] _T_304 = {19'h0,abs_temp_12,1'h0}; // @[Cat.scala 29:58] + wire _T_309 = dbg_state == 3'h2; // @[el2_dbg.scala 266:100] + wire command_wren = _T_248 & _T_309; // @[el2_dbg.scala 266:87] + wire [19:0] _T_313 = {3'h0,io_dmi_reg_wdata[16:0]}; // @[Cat.scala 29:58] + wire [11:0] _T_315 = {io_dmi_reg_wdata[31:24],1'h0,io_dmi_reg_wdata[22:20]}; // @[Cat.scala 29:58] + wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_5_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_5_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 508:23] + reg [31:0] command_reg; // @[el2_lib.scala 514:16] + wire _T_321 = _T_93 & _T_230; // @[el2_dbg.scala 272:58] + wire data0_reg_wren0 = _T_321 & _T_309; // @[el2_dbg.scala 272:89] + wire _T_323 = dbg_state == 3'h4; // @[el2_dbg.scala 273:59] + wire _T_324 = io_core_dbg_cmd_done & _T_323; // @[el2_dbg.scala 273:46] + wire _T_326 = ~command_reg[16]; // @[el2_dbg.scala 273:83] + wire data0_reg_wren1 = _T_324 & _T_326; // @[el2_dbg.scala 273:81] + wire [31:0] _T_328 = data0_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_329 = _T_328 & io_dmi_reg_wdata; // @[el2_dbg.scala 276:45] + wire [31:0] _T_331 = data0_reg_wren1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_332 = _T_331 & io_core_dbg_rddata; // @[el2_dbg.scala 276:92] + wire rvclkhdr_6_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_6_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_6_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_6_io_scan_mode; // @[el2_lib.scala 508:23] + reg [31:0] data0_reg; // @[el2_lib.scala 514:16] + wire _T_337 = io_dmi_reg_addr == 7'h5; // @[el2_dbg.scala 281:77] + wire _T_338 = _T_93 & _T_337; // @[el2_dbg.scala 281:58] + wire data1_reg_wren = _T_338 & _T_309; // @[el2_dbg.scala 281:89] + wire [31:0] _T_341 = data1_reg_wren ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire rvclkhdr_7_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_7_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_7_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_7_io_scan_mode; // @[el2_lib.scala 508:23] + reg [31:0] _T_345; // @[el2_lib.scala 514:16] + wire [2:0] dbg_nxtstate; + wire _T_346 = 3'h0 == dbg_state; // @[Conditional.scala 37:30] + wire _T_348 = dmstatus_reg[9] | io_dec_tlu_mpc_halted_only; // @[el2_dbg.scala 296:43] + wire [2:0] _T_349 = _T_348 ? 3'h2 : 3'h1; // @[el2_dbg.scala 296:26] + wire _T_351 = ~io_dec_tlu_debug_mode; // @[el2_dbg.scala 297:45] + wire _T_352 = dmcontrol_reg[31] & _T_351; // @[el2_dbg.scala 297:43] + wire _T_354 = _T_352 | dmstatus_reg[9]; // @[el2_dbg.scala 297:69] + wire _T_355 = _T_354 | io_dec_tlu_mpc_halted_only; // @[el2_dbg.scala 297:87] + wire _T_358 = _T_355 & _T_12; // @[el2_dbg.scala 297:117] + wire _T_362 = dmcontrol_reg[31] & _T_12; // @[el2_dbg.scala 298:45] + wire _T_364 = 3'h1 == dbg_state; // @[Conditional.scala 37:30] + wire [2:0] _T_366 = dmcontrol_reg[1] ? 3'h0 : 3'h2; // @[el2_dbg.scala 301:26] + wire _T_369 = dmstatus_reg[9] | dmcontrol_reg[1]; // @[el2_dbg.scala 302:39] + wire _T_371 = dmcontrol_wren_Q & dmcontrol_reg[31]; // @[el2_dbg.scala 303:44] + wire _T_374 = _T_371 & _T_12; // @[el2_dbg.scala 303:64] + wire _T_376 = 3'h2 == dbg_state; // @[Conditional.scala 37:30] + wire _T_380 = dmstatus_reg[9] & _T_12; // @[el2_dbg.scala 306:43] + wire _T_383 = ~dmcontrol_reg[3]; // @[el2_dbg.scala 307:33] + wire _T_384 = dmcontrol_reg[30] & _T_383; // @[el2_dbg.scala 307:31] + wire [2:0] _T_385 = _T_384 ? 3'h6 : 3'h3; // @[el2_dbg.scala 307:12] + wire [2:0] _T_387 = dmcontrol_reg[31] ? 3'h1 : 3'h0; // @[el2_dbg.scala 308:12] + wire [2:0] _T_388 = _T_380 ? _T_385 : _T_387; // @[el2_dbg.scala 306:26] + wire _T_391 = dmstatus_reg[9] & dmcontrol_reg[30]; // @[el2_dbg.scala 309:39] + wire _T_393 = ~dmcontrol_reg[31]; // @[el2_dbg.scala 309:61] + wire _T_394 = _T_391 & _T_393; // @[el2_dbg.scala 309:59] + wire _T_395 = _T_394 & dmcontrol_wren_Q; // @[el2_dbg.scala 309:80] + wire _T_396 = _T_395 | command_wren; // @[el2_dbg.scala 309:99] + wire _T_398 = _T_396 | dmcontrol_reg[1]; // @[el2_dbg.scala 309:114] + wire _T_401 = ~_T_348; // @[el2_dbg.scala 310:28] + wire _T_402 = _T_398 | _T_401; // @[el2_dbg.scala 310:26] + wire _T_403 = dbg_nxtstate == 3'h3; // @[el2_dbg.scala 311:60] + wire _T_404 = dbg_state_en & _T_403; // @[el2_dbg.scala 311:44] + wire _T_405 = dbg_nxtstate == 3'h6; // @[el2_dbg.scala 313:58] + wire _T_406 = dbg_state_en & _T_405; // @[el2_dbg.scala 313:42] + wire _T_414 = 3'h3 == dbg_state; // @[Conditional.scala 37:30] + wire _T_417 = |abstractcs_reg[10:8]; // @[el2_dbg.scala 317:85] + wire [2:0] _T_418 = _T_417 ? 3'h5 : 3'h4; // @[el2_dbg.scala 317:62] + wire [2:0] _T_419 = dmcontrol_reg[1] ? 3'h0 : _T_418; // @[el2_dbg.scala 317:26] + wire _T_422 = io_dbg_cmd_valid | _T_417; // @[el2_dbg.scala 318:40] + wire _T_424 = _T_422 | dmcontrol_reg[1]; // @[el2_dbg.scala 318:68] + wire _T_431 = 3'h4 == dbg_state; // @[Conditional.scala 37:30] + wire [2:0] _T_433 = dmcontrol_reg[1] ? 3'h0 : 3'h5; // @[el2_dbg.scala 322:26] + wire _T_435 = io_core_dbg_cmd_done | dmcontrol_reg[1]; // @[el2_dbg.scala 323:44] + wire _T_442 = 3'h5 == dbg_state; // @[Conditional.scala 37:30] + wire _T_451 = 3'h6 == dbg_state; // @[Conditional.scala 37:30] + wire _T_454 = dmstatus_reg[17] | dmcontrol_reg[1]; // @[el2_dbg.scala 335:40] + wire _GEN_11 = _T_451 & _T_454; // @[Conditional.scala 39:67] + wire _GEN_12 = _T_451 & _T_374; // @[Conditional.scala 39:67] + wire [2:0] _GEN_13 = _T_442 ? _T_366 : 3'h0; // @[Conditional.scala 39:67] + wire _GEN_14 = _T_442 | _GEN_11; // @[Conditional.scala 39:67] + wire _GEN_15 = _T_442 & dbg_state_en; // @[Conditional.scala 39:67] + wire _GEN_17 = _T_442 ? _T_374 : _GEN_12; // @[Conditional.scala 39:67] + wire [2:0] _GEN_18 = _T_431 ? _T_433 : _GEN_13; // @[Conditional.scala 39:67] + wire _GEN_19 = _T_431 ? _T_435 : _GEN_14; // @[Conditional.scala 39:67] + wire _GEN_20 = _T_431 ? _T_374 : _GEN_17; // @[Conditional.scala 39:67] + wire _GEN_21 = _T_431 ? 1'h0 : _GEN_15; // @[Conditional.scala 39:67] + wire [2:0] _GEN_23 = _T_414 ? _T_419 : _GEN_18; // @[Conditional.scala 39:67] + wire _GEN_24 = _T_414 ? _T_424 : _GEN_19; // @[Conditional.scala 39:67] + wire _GEN_25 = _T_414 ? _T_374 : _GEN_20; // @[Conditional.scala 39:67] + wire _GEN_26 = _T_414 ? 1'h0 : _GEN_21; // @[Conditional.scala 39:67] + wire [2:0] _GEN_28 = _T_376 ? _T_388 : _GEN_23; // @[Conditional.scala 39:67] + wire _GEN_29 = _T_376 ? _T_402 : _GEN_24; // @[Conditional.scala 39:67] + wire _GEN_30 = _T_376 ? _T_404 : _GEN_26; // @[Conditional.scala 39:67] + wire _GEN_32 = _T_376 & _T_406; // @[Conditional.scala 39:67] + wire _GEN_33 = _T_376 ? _T_374 : _GEN_25; // @[Conditional.scala 39:67] + wire [2:0] _GEN_34 = _T_364 ? _T_366 : _GEN_28; // @[Conditional.scala 39:67] + wire _GEN_35 = _T_364 ? _T_369 : _GEN_29; // @[Conditional.scala 39:67] + wire _GEN_36 = _T_364 ? _T_374 : _GEN_33; // @[Conditional.scala 39:67] + wire _GEN_37 = _T_364 ? 1'h0 : _GEN_30; // @[Conditional.scala 39:67] + wire _GEN_39 = _T_364 ? 1'h0 : _GEN_32; // @[Conditional.scala 39:67] + wire [31:0] _T_463 = _T_230 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_464 = _T_463 & data0_reg; // @[el2_dbg.scala 339:71] + wire [31:0] _T_467 = _T_337 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_468 = _T_467 & data1_reg; // @[el2_dbg.scala 339:122] + wire [31:0] _T_469 = _T_464 | _T_468; // @[el2_dbg.scala 339:83] + wire [31:0] _T_472 = _T_149 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_473 = _T_472 & dmcontrol_reg; // @[el2_dbg.scala 340:43] + wire [31:0] _T_474 = _T_469 | _T_473; // @[el2_dbg.scala 339:134] + wire _T_475 = io_dmi_reg_addr == 7'h11; // @[el2_dbg.scala 340:86] + wire [31:0] _T_477 = _T_475 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_478 = _T_477 & dmstatus_reg; // @[el2_dbg.scala 340:99] + wire [31:0] _T_479 = _T_474 | _T_478; // @[el2_dbg.scala 340:59] + wire [31:0] _T_482 = _T_226 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_483 = _T_482 & abstractcs_reg; // @[el2_dbg.scala 341:43] + wire [31:0] _T_484 = _T_479 | _T_483; // @[el2_dbg.scala 340:114] + wire [31:0] _T_487 = _T_227 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_488 = _T_487 & command_reg; // @[el2_dbg.scala 341:100] + wire [31:0] _T_489 = _T_484 | _T_488; // @[el2_dbg.scala 341:60] + wire _T_490 = io_dmi_reg_addr == 7'h40; // @[el2_dbg.scala 342:30] + wire [31:0] _T_492 = _T_490 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_493 = _T_492 & haltsum0_reg; // @[el2_dbg.scala 342:43] + wire [31:0] _T_494 = _T_489 | _T_493; // @[el2_dbg.scala 341:114] + wire [31:0] _T_497 = _T_14 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_498 = _T_497 & sbcs_reg; // @[el2_dbg.scala 342:98] + wire [31:0] _T_499 = _T_494 | _T_498; // @[el2_dbg.scala 342:58] + wire [31:0] _T_502 = _T_22 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_503 = _T_502 & sbaddress0_reg; // @[el2_dbg.scala 343:43] + wire [31:0] _T_504 = _T_499 | _T_503; // @[el2_dbg.scala 342:109] + wire [31:0] _T_507 = _T_23 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_508 = _T_507 & sbdata0_reg; // @[el2_dbg.scala 343:100] + wire [31:0] _T_509 = _T_504 | _T_508; // @[el2_dbg.scala 343:60] + wire [31:0] _T_512 = _T_25 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_513 = _T_512 & sbdata1_reg; // @[el2_dbg.scala 344:43] + wire [31:0] dmi_reg_rdata_din = _T_509 | _T_513; // @[el2_dbg.scala 343:114] + wire _T_517 = _T_31 & reset; // @[el2_dbg.scala 346:96] + reg [2:0] _T_518; // @[Reg.scala 27:20] + reg [31:0] _T_522; // @[Reg.scala 27:20] + wire _T_524 = command_reg[31:24] == 8'h2; // @[el2_dbg.scala 355:47] + wire [30:0] _T_526 = {data1_reg[31:2],1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_528 = {20'h0,command_reg[11:0]}; // @[Cat.scala 29:58] + wire _T_531 = dbg_state == 3'h3; // @[el2_dbg.scala 357:35] + wire _T_534 = ~_T_417; // @[el2_dbg.scala 357:60] + wire _T_535 = _T_531 & _T_534; // @[el2_dbg.scala 357:58] + wire _T_543 = command_reg[15:12] == 4'h0; // @[el2_dbg.scala 359:102] + wire [1:0] _T_544 = {1'h0,_T_543}; // @[Cat.scala 29:58] + wire _T_555 = 4'h0 == sb_state; // @[Conditional.scala 37:30] + wire _T_557 = sbdata0_reg_wren0 | sbreadondata_access; // @[el2_dbg.scala 374:39] + wire _T_558 = _T_557 | sbreadonaddr_access; // @[el2_dbg.scala 374:61] + wire _T_560 = |io_dmi_reg_wdata[14:12]; // @[el2_dbg.scala 377:65] + wire _T_561 = sbcs_wren & _T_560; // @[el2_dbg.scala 377:38] + wire _T_563 = io_dmi_reg_wdata[14:12] == 3'h0; // @[el2_dbg.scala 378:27] + wire [2:0] _GEN_116 = {{2'd0}, _T_563}; // @[el2_dbg.scala 378:53] + wire [2:0] _T_565 = _GEN_116 & sbcs_reg[14:12]; // @[el2_dbg.scala 378:53] + wire _T_566 = 4'h1 == sb_state; // @[Conditional.scala 37:30] + wire _T_567 = sbcs_unaligned | sbcs_illegal_size; // @[el2_dbg.scala 381:41] + wire _T_569 = io_dbg_bus_clk_en | sbcs_unaligned; // @[el2_dbg.scala 382:40] + wire _T_570 = _T_569 | sbcs_illegal_size; // @[el2_dbg.scala 382:57] + wire _T_573 = 4'h2 == sb_state; // @[Conditional.scala 37:30] + wire _T_580 = 4'h3 == sb_state; // @[Conditional.scala 37:30] + wire _T_581 = sb_bus_cmd_read & io_dbg_bus_clk_en; // @[el2_dbg.scala 394:38] + wire _T_582 = 4'h4 == sb_state; // @[Conditional.scala 37:30] + wire _T_583 = sb_bus_cmd_write_addr & sb_bus_cmd_write_data; // @[el2_dbg.scala 397:48] + wire _T_586 = sb_bus_cmd_write_addr | sb_bus_cmd_write_data; // @[el2_dbg.scala 398:45] + wire _T_587 = _T_586 & io_dbg_bus_clk_en; // @[el2_dbg.scala 398:70] + wire _T_588 = 4'h5 == sb_state; // @[Conditional.scala 37:30] + wire _T_589 = sb_bus_cmd_write_addr & io_dbg_bus_clk_en; // @[el2_dbg.scala 402:44] + wire _T_590 = 4'h6 == sb_state; // @[Conditional.scala 37:30] + wire _T_591 = sb_bus_cmd_write_data & io_dbg_bus_clk_en; // @[el2_dbg.scala 406:44] + wire _T_592 = 4'h7 == sb_state; // @[Conditional.scala 37:30] + wire _T_593 = sb_bus_rsp_read & io_dbg_bus_clk_en; // @[el2_dbg.scala 410:38] + wire _T_594 = sb_state_en & sb_bus_rsp_error; // @[el2_dbg.scala 411:40] + wire _T_595 = 4'h8 == sb_state; // @[Conditional.scala 37:30] + wire _T_596 = sb_bus_rsp_write & io_dbg_bus_clk_en; // @[el2_dbg.scala 416:39] + wire _T_598 = 4'h9 == sb_state; // @[Conditional.scala 37:30] + wire _GEN_51 = _T_598 & sbcs_reg[16]; // @[Conditional.scala 39:67] + wire _GEN_53 = _T_595 ? _T_596 : _T_598; // @[Conditional.scala 39:67] + wire _GEN_54 = _T_595 & _T_594; // @[Conditional.scala 39:67] + wire _GEN_56 = _T_595 ? 1'h0 : _T_598; // @[Conditional.scala 39:67] + wire _GEN_58 = _T_595 ? 1'h0 : _GEN_51; // @[Conditional.scala 39:67] + wire _GEN_60 = _T_592 ? _T_593 : _GEN_53; // @[Conditional.scala 39:67] + wire _GEN_61 = _T_592 ? _T_594 : _GEN_54; // @[Conditional.scala 39:67] + wire _GEN_63 = _T_592 ? 1'h0 : _GEN_56; // @[Conditional.scala 39:67] + wire _GEN_65 = _T_592 ? 1'h0 : _GEN_58; // @[Conditional.scala 39:67] + wire _GEN_67 = _T_590 ? _T_591 : _GEN_60; // @[Conditional.scala 39:67] + wire _GEN_68 = _T_590 ? 1'h0 : _GEN_61; // @[Conditional.scala 39:67] + wire _GEN_70 = _T_590 ? 1'h0 : _GEN_63; // @[Conditional.scala 39:67] + wire _GEN_72 = _T_590 ? 1'h0 : _GEN_65; // @[Conditional.scala 39:67] + wire _GEN_74 = _T_588 ? _T_589 : _GEN_67; // @[Conditional.scala 39:67] + wire _GEN_75 = _T_588 ? 1'h0 : _GEN_68; // @[Conditional.scala 39:67] + wire _GEN_77 = _T_588 ? 1'h0 : _GEN_70; // @[Conditional.scala 39:67] + wire _GEN_79 = _T_588 ? 1'h0 : _GEN_72; // @[Conditional.scala 39:67] + wire _GEN_81 = _T_582 ? _T_587 : _GEN_74; // @[Conditional.scala 39:67] + wire _GEN_82 = _T_582 ? 1'h0 : _GEN_75; // @[Conditional.scala 39:67] + wire _GEN_84 = _T_582 ? 1'h0 : _GEN_77; // @[Conditional.scala 39:67] + wire _GEN_86 = _T_582 ? 1'h0 : _GEN_79; // @[Conditional.scala 39:67] + wire _GEN_88 = _T_580 ? _T_581 : _GEN_81; // @[Conditional.scala 39:67] + wire _GEN_89 = _T_580 ? 1'h0 : _GEN_82; // @[Conditional.scala 39:67] + wire _GEN_91 = _T_580 ? 1'h0 : _GEN_84; // @[Conditional.scala 39:67] + wire _GEN_93 = _T_580 ? 1'h0 : _GEN_86; // @[Conditional.scala 39:67] + wire _GEN_95 = _T_573 ? _T_570 : _GEN_88; // @[Conditional.scala 39:67] + wire _GEN_96 = _T_573 ? _T_567 : _GEN_89; // @[Conditional.scala 39:67] + wire _GEN_98 = _T_573 ? 1'h0 : _GEN_91; // @[Conditional.scala 39:67] + wire _GEN_100 = _T_573 ? 1'h0 : _GEN_93; // @[Conditional.scala 39:67] + wire _GEN_102 = _T_566 ? _T_570 : _GEN_95; // @[Conditional.scala 39:67] + wire _GEN_103 = _T_566 ? _T_567 : _GEN_96; // @[Conditional.scala 39:67] + wire _GEN_105 = _T_566 ? 1'h0 : _GEN_98; // @[Conditional.scala 39:67] + wire _GEN_107 = _T_566 ? 1'h0 : _GEN_100; // @[Conditional.scala 39:67] + reg [3:0] _T_603; // @[Reg.scala 27:20] + wire _T_610 = |io_sb_axi_rresp; // @[el2_dbg.scala 437:63] + wire _T_611 = sb_bus_rsp_read & _T_610; // @[el2_dbg.scala 437:39] + wire _T_613 = |io_sb_axi_bresp; // @[el2_dbg.scala 437:110] + wire _T_614 = sb_bus_rsp_write & _T_613; // @[el2_dbg.scala 437:86] + wire _T_616 = sb_state == 4'h4; // @[el2_dbg.scala 438:35] + wire _T_617 = sb_state == 4'h5; // @[el2_dbg.scala 438:70] + wire _T_623 = sb_state == 4'h6; // @[el2_dbg.scala 449:69] + wire [63:0] _T_629 = _T_72 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12] + wire [63:0] _T_633 = {sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0]}; // @[Cat.scala 29:58] + wire [63:0] _T_634 = _T_629 & _T_633; // @[el2_dbg.scala 450:59] + wire [63:0] _T_638 = _T_57 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12] + wire [63:0] _T_641 = {sbdata0_reg[15:0],sbdata0_reg[15:0],sbdata0_reg[15:0],sbdata0_reg[15:0]}; // @[Cat.scala 29:58] + wire [63:0] _T_642 = _T_638 & _T_641; // @[el2_dbg.scala 450:132] + wire [63:0] _T_643 = _T_634 | _T_642; // @[el2_dbg.scala 450:90] + wire [63:0] _T_647 = _T_61 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12] + wire [63:0] _T_649 = {sbdata0_reg,sbdata0_reg}; // @[Cat.scala 29:58] + wire [63:0] _T_650 = _T_647 & _T_649; // @[el2_dbg.scala 451:45] + wire [63:0] _T_651 = _T_643 | _T_650; // @[el2_dbg.scala 450:162] + wire [63:0] _T_655 = _T_67 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12] + wire [63:0] _T_658 = {sbdata1_reg,sbdata0_reg}; // @[Cat.scala 29:58] + wire [63:0] _T_659 = _T_655 & _T_658; // @[el2_dbg.scala 451:119] + wire [7:0] _T_664 = _T_72 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [14:0] _T_666 = 15'h1 << sbaddress0_reg[2:0]; // @[el2_dbg.scala 453:76] + wire [14:0] _GEN_117 = {{7'd0}, _T_664}; // @[el2_dbg.scala 453:61] + wire [14:0] _T_667 = _GEN_117 & _T_666; // @[el2_dbg.scala 453:61] + wire [7:0] _T_671 = _T_57 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_673 = {sbaddress0_reg[2:1],1'h0}; // @[Cat.scala 29:58] + wire [14:0] _T_674 = 15'h3 << _T_673; // @[el2_dbg.scala 454:59] + wire [14:0] _GEN_118 = {{7'd0}, _T_671}; // @[el2_dbg.scala 454:44] + wire [14:0] _T_675 = _GEN_118 & _T_674; // @[el2_dbg.scala 454:44] + wire [14:0] _T_676 = _T_667 | _T_675; // @[el2_dbg.scala 453:101] + wire [7:0] _T_680 = _T_61 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_682 = {sbaddress0_reg[2],1'h0}; // @[Cat.scala 29:58] + wire [10:0] _T_683 = 11'hf << _T_682; // @[el2_dbg.scala 455:59] + wire [10:0] _GEN_119 = {{3'd0}, _T_680}; // @[el2_dbg.scala 455:44] + wire [10:0] _T_684 = _GEN_119 & _T_683; // @[el2_dbg.scala 455:44] + wire [14:0] _GEN_120 = {{4'd0}, _T_684}; // @[el2_dbg.scala 454:97] + wire [14:0] _T_685 = _T_676 | _GEN_120; // @[el2_dbg.scala 454:97] + wire [7:0] _T_689 = _T_67 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [14:0] _GEN_121 = {{7'd0}, _T_689}; // @[el2_dbg.scala 455:95] + wire [14:0] _T_691 = _T_685 | _GEN_121; // @[el2_dbg.scala 455:95] + wire [3:0] _GEN_122 = {{1'd0}, sbaddress0_reg[2:0]}; // @[el2_dbg.scala 472:93] + wire [6:0] _T_702 = 4'h8 * _GEN_122; // @[el2_dbg.scala 472:93] + wire [63:0] _T_703 = io_sb_axi_rdata >> _T_702; // @[el2_dbg.scala 472:86] + wire [63:0] _T_704 = _T_703 & 64'hff; // @[el2_dbg.scala 472:117] + wire [63:0] _T_705 = _T_629 & _T_704; // @[el2_dbg.scala 472:59] + wire [4:0] _GEN_123 = {{3'd0}, sbaddress0_reg[2:1]}; // @[el2_dbg.scala 473:80] + wire [6:0] _T_712 = 5'h10 * _GEN_123; // @[el2_dbg.scala 473:80] + wire [63:0] _T_713 = io_sb_axi_rdata >> _T_712; // @[el2_dbg.scala 473:72] + wire [63:0] _T_714 = _T_713 & 64'hffff; // @[el2_dbg.scala 473:104] + wire [63:0] _T_715 = _T_638 & _T_714; // @[el2_dbg.scala 473:45] + wire [63:0] _T_716 = _T_705 | _T_715; // @[el2_dbg.scala 472:134] + wire [5:0] _GEN_124 = {{5'd0}, sbaddress0_reg[2]}; // @[el2_dbg.scala 474:80] + wire [6:0] _T_723 = 6'h20 * _GEN_124; // @[el2_dbg.scala 474:80] + wire [63:0] _T_724 = io_sb_axi_rdata >> _T_723; // @[el2_dbg.scala 474:72] + wire [63:0] _T_725 = _T_724 & 64'hffffffff; // @[el2_dbg.scala 474:101] + wire [63:0] _T_726 = _T_647 & _T_725; // @[el2_dbg.scala 474:45] + wire [63:0] _T_727 = _T_716 | _T_726; // @[el2_dbg.scala 473:123] + wire [63:0] _T_733 = _T_655 & io_sb_axi_rdata; // @[el2_dbg.scala 475:45] + rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_io_l1clk), + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en), + .io_scan_mode(rvclkhdr_io_scan_mode) + ); + rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_1_io_l1clk), + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en), + .io_scan_mode(rvclkhdr_1_io_scan_mode) + ); + rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_2_io_l1clk), + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en), + .io_scan_mode(rvclkhdr_2_io_scan_mode) + ); + rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_3_io_l1clk), + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en), + .io_scan_mode(rvclkhdr_3_io_scan_mode) + ); + rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_4_io_l1clk), + .io_clk(rvclkhdr_4_io_clk), + .io_en(rvclkhdr_4_io_en), + .io_scan_mode(rvclkhdr_4_io_scan_mode) + ); + rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_5_io_l1clk), + .io_clk(rvclkhdr_5_io_clk), + .io_en(rvclkhdr_5_io_en), + .io_scan_mode(rvclkhdr_5_io_scan_mode) + ); + rvclkhdr rvclkhdr_6 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_6_io_l1clk), + .io_clk(rvclkhdr_6_io_clk), + .io_en(rvclkhdr_6_io_en), + .io_scan_mode(rvclkhdr_6_io_scan_mode) + ); + rvclkhdr rvclkhdr_7 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_7_io_l1clk), + .io_clk(rvclkhdr_7_io_clk), + .io_en(rvclkhdr_7_io_en), + .io_scan_mode(rvclkhdr_7_io_scan_mode) + ); + assign io_dbg_cmd_addr = _T_524 ? {{1'd0}, _T_526} : _T_528; // @[el2_dbg.scala 355:19] + assign io_dbg_cmd_wrdata = data0_reg; // @[el2_dbg.scala 356:21] + assign io_dbg_cmd_valid = _T_535 & io_dma_dbg_ready; // @[el2_dbg.scala 357:20] + assign io_dbg_cmd_write = command_reg[16]; // @[el2_dbg.scala 358:20] + assign io_dbg_cmd_type = _T_524 ? 2'h2 : _T_544; // @[el2_dbg.scala 359:19] + assign io_dbg_cmd_size = command_reg[21:20]; // @[el2_dbg.scala 360:19] + assign io_dbg_core_rst_l = ~dmcontrol_reg[1]; // @[el2_dbg.scala 131:21] + assign io_dbg_dma_bubble = _T_535 | _T_323; // @[el2_dbg.scala 361:21] + assign io_dbg_halt_req = _T_346 ? _T_362 : _GEN_36; // @[el2_dbg.scala 292:19 el2_dbg.scala 298:23 el2_dbg.scala 303:23 el2_dbg.scala 314:23 el2_dbg.scala 319:23 el2_dbg.scala 324:23 el2_dbg.scala 331:23 el2_dbg.scala 336:23] + assign io_dbg_resume_req = _T_346 ? 1'h0 : _GEN_39; // @[el2_dbg.scala 293:21 el2_dbg.scala 313:25] + assign io_dmi_reg_rdata = _T_522; // @[el2_dbg.scala 351:20] + assign io_sb_axi_awvalid = _T_616 | _T_617; // @[el2_dbg.scala 438:21] + assign io_sb_axi_awid = 1'h0; // @[el2_dbg.scala 440:18] + assign io_sb_axi_awaddr = sbaddress0_reg; // @[el2_dbg.scala 439:20] + assign io_sb_axi_awregion = sbaddress0_reg[31:28]; // @[el2_dbg.scala 444:22] + assign io_sb_axi_awlen = 8'h0; // @[el2_dbg.scala 445:19] + assign io_sb_axi_awsize = sbcs_reg[19:17]; // @[el2_dbg.scala 441:20] + assign io_sb_axi_awburst = 2'h1; // @[el2_dbg.scala 446:21] + assign io_sb_axi_awlock = 1'h0; // @[el2_dbg.scala 448:20] + assign io_sb_axi_awcache = 4'hf; // @[el2_dbg.scala 443:21] + assign io_sb_axi_awprot = 3'h0; // @[el2_dbg.scala 442:20] + assign io_sb_axi_awqos = 4'h0; // @[el2_dbg.scala 447:19] + assign io_sb_axi_wvalid = _T_616 | _T_623; // @[el2_dbg.scala 449:20] + assign io_sb_axi_wdata = _T_651 | _T_659; // @[el2_dbg.scala 450:19] + assign io_sb_axi_wstrb = _T_691[7:0]; // @[el2_dbg.scala 453:19] + assign io_sb_axi_wlast = 1'h1; // @[el2_dbg.scala 458:19] + assign io_sb_axi_bready = 1'h1; // @[el2_dbg.scala 470:20] + assign io_sb_axi_arvalid = sb_state == 4'h3; // @[el2_dbg.scala 459:21] + assign io_sb_axi_arid = 1'h0; // @[el2_dbg.scala 461:18] + assign io_sb_axi_araddr = sbaddress0_reg; // @[el2_dbg.scala 460:20] + assign io_sb_axi_arregion = sbaddress0_reg[31:28]; // @[el2_dbg.scala 465:22] + assign io_sb_axi_arlen = 8'h0; // @[el2_dbg.scala 466:19] + assign io_sb_axi_arsize = sbcs_reg[19:17]; // @[el2_dbg.scala 462:20] + assign io_sb_axi_arburst = 2'h1; // @[el2_dbg.scala 467:21] + assign io_sb_axi_arlock = 1'h0; // @[el2_dbg.scala 469:20] + assign io_sb_axi_arcache = 4'h0; // @[el2_dbg.scala 464:21] + assign io_sb_axi_arprot = 3'h0; // @[el2_dbg.scala 463:20] + assign io_sb_axi_arqos = 4'h0; // @[el2_dbg.scala 468:19] + assign io_sb_axi_rready = 1'h1; // @[el2_dbg.scala 471:20] + assign dbg_state = _T_518; // @[el2_dbg.scala 346:13] + assign dbg_state_en = _T_346 ? _T_358 : _GEN_35; // @[el2_dbg.scala 289:16 el2_dbg.scala 297:20 el2_dbg.scala 302:20 el2_dbg.scala 309:20 el2_dbg.scala 318:20 el2_dbg.scala 323:20 el2_dbg.scala 328:20 el2_dbg.scala 335:20] + assign sb_state = _T_603; // @[el2_dbg.scala 428:12] + assign sb_state_en = _T_555 ? _T_558 : _GEN_102; // @[el2_dbg.scala 374:19 el2_dbg.scala 382:19 el2_dbg.scala 388:19 el2_dbg.scala 394:19 el2_dbg.scala 398:19 el2_dbg.scala 402:19 el2_dbg.scala 406:19 el2_dbg.scala 410:19 el2_dbg.scala 416:19 el2_dbg.scala 422:19] + assign dmcontrol_reg = {_T_166,_T_164}; // @[el2_dbg.scala 209:17] + assign sbaddress0_reg = _T_137; // @[el2_dbg.scala 190:18] + assign sbcs_sbbusy_wren = _T_555 ? sb_state_en : _GEN_105; // @[el2_dbg.scala 366:20 el2_dbg.scala 375:24 el2_dbg.scala 423:24] + assign sbcs_sberror_wren = _T_555 ? _T_561 : _GEN_103; // @[el2_dbg.scala 368:21 el2_dbg.scala 377:25 el2_dbg.scala 383:25 el2_dbg.scala 389:25 el2_dbg.scala 411:25 el2_dbg.scala 417:25] + assign sb_bus_rdata = _T_727 | _T_733; // @[el2_dbg.scala 472:16] + assign sbaddress0_reg_wren1 = _T_555 ? 1'h0 : _GEN_107; // @[el2_dbg.scala 370:24 el2_dbg.scala 425:28] + assign dmstatus_reg = {_T_187,_T_183}; // @[el2_dbg.scala 215:16] + assign dmstatus_havereset = _T_223; // @[el2_dbg.scala 232:22] + assign dmstatus_resumeack = _T_212; // @[el2_dbg.scala 224:22] + assign dmstatus_unavail = dmcontrol_reg[1] | _T_204; // @[el2_dbg.scala 222:20] + assign dmstatus_running = ~_T_207; // @[el2_dbg.scala 223:20] + assign dmstatus_halted = _T_218; // @[el2_dbg.scala 228:19] + assign abstractcs_busy_wren = _T_346 ? 1'h0 : _GEN_37; // @[el2_dbg.scala 290:24 el2_dbg.scala 311:28 el2_dbg.scala 329:28] + assign sb_bus_cmd_read = io_sb_axi_arvalid & io_sb_axi_arready; // @[el2_dbg.scala 432:19] + assign sb_bus_cmd_write_addr = io_sb_axi_awvalid & io_sb_axi_awready; // @[el2_dbg.scala 433:25] + assign sb_bus_cmd_write_data = io_sb_axi_wvalid & io_sb_axi_wready; // @[el2_dbg.scala 434:25] + assign sb_bus_rsp_read = io_sb_axi_rvalid & io_sb_axi_rready; // @[el2_dbg.scala 435:19] + assign sb_bus_rsp_error = _T_611 | _T_614; // @[el2_dbg.scala 437:20] + assign sb_bus_rsp_write = io_sb_axi_bvalid & io_sb_axi_bready; // @[el2_dbg.scala 436:20] + assign sbcs_sbbusy_din = 4'h0 == sb_state; // @[el2_dbg.scala 367:19 el2_dbg.scala 376:23 el2_dbg.scala 424:23] + assign data1_reg = _T_345; // @[el2_dbg.scala 283:13] + assign sbcs_reg = {_T_54,_T_50}; // @[el2_dbg.scala 156:12] + assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_io_en = _T_3 | io_clk_override; // @[el2_lib.scala 485:16] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_1_io_en = _T_6 | io_clk_override; // @[el2_lib.scala 485:16] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_2_io_en = sbdata0_reg_wren0 | sbdata0_reg_wren1; // @[el2_lib.scala 511:17] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_3_io_en = sbdata1_reg_wren0 | sbdata0_reg_wren1; // @[el2_lib.scala 511:17] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_4_io_en = sbaddress0_reg_wren0 | sbaddress0_reg_wren1; // @[el2_lib.scala 511:17] + assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign abstractcs_reg = {_T_304,_T_302}; // @[el2_dbg.scala 264:18] + assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_5_io_en = _T_248 & _T_309; // @[el2_lib.scala 511:17] + assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_6_io_en = data0_reg_wren0 | data0_reg_wren1; // @[el2_lib.scala 511:17] + assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_7_io_en = _T_338 & _T_309; // @[el2_lib.scala 511:17] + assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign dbg_nxtstate = _T_346 ? _T_349 : _GEN_34; // @[el2_dbg.scala 288:16 el2_dbg.scala 296:20 el2_dbg.scala 301:20 el2_dbg.scala 306:20 el2_dbg.scala 317:20 el2_dbg.scala 322:20 el2_dbg.scala 327:20 el2_dbg.scala 334:20] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + temp_sbcs_22 = _RAND_0[0:0]; + _RAND_1 = {1{`RANDOM}}; + temp_sbcs_21 = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + temp_sbcs_20 = _RAND_2[0:0]; + _RAND_3 = {1{`RANDOM}}; + temp_sbcs_19_15 = _RAND_3[4:0]; + _RAND_4 = {1{`RANDOM}}; + temp_sbcs_14_12 = _RAND_4[2:0]; + _RAND_5 = {1{`RANDOM}}; + sbdata0_reg = _RAND_5[31:0]; + _RAND_6 = {1{`RANDOM}}; + sbdata1_reg = _RAND_6[31:0]; + _RAND_7 = {1{`RANDOM}}; + _T_137 = _RAND_7[31:0]; + _RAND_8 = {1{`RANDOM}}; + dm_temp = _RAND_8[3:0]; + _RAND_9 = {1{`RANDOM}}; + dm_temp_0 = _RAND_9[0:0]; + _RAND_10 = {1{`RANDOM}}; + dmcontrol_wren_Q = _RAND_10[0:0]; + _RAND_11 = {1{`RANDOM}}; + _T_212 = _RAND_11[0:0]; + _RAND_12 = {1{`RANDOM}}; + _T_218 = _RAND_12[0:0]; + _RAND_13 = {1{`RANDOM}}; + _T_223 = _RAND_13[0:0]; + _RAND_14 = {1{`RANDOM}}; + abs_temp_12 = _RAND_14[0:0]; + _RAND_15 = {1{`RANDOM}}; + abs_temp_10_8 = _RAND_15[2:0]; + _RAND_16 = {1{`RANDOM}}; + command_reg = _RAND_16[31:0]; + _RAND_17 = {1{`RANDOM}}; + data0_reg = _RAND_17[31:0]; + _RAND_18 = {1{`RANDOM}}; + _T_345 = _RAND_18[31:0]; + _RAND_19 = {1{`RANDOM}}; + _T_518 = _RAND_19[2:0]; + _RAND_20 = {1{`RANDOM}}; + _T_522 = _RAND_20[31:0]; + _RAND_21 = {1{`RANDOM}}; + _T_603 = _RAND_21[3:0]; +`endif // RANDOMIZE_REG_INIT + if (_T_32) begin + temp_sbcs_22 = 1'h0; + end + if (_T_32) begin + temp_sbcs_21 = 1'h0; + end + if (_T_32) begin + temp_sbcs_20 = 1'h0; + end + if (_T_32) begin + temp_sbcs_19_15 = 5'h0; + end + if (_T_32) begin + temp_sbcs_14_12 = 3'h0; + end + if (_T_32) begin + sbdata0_reg = 32'h0; + end + if (_T_32) begin + sbdata1_reg = 32'h0; + end + if (_T_32) begin + _T_137 = 32'h0; + end + if (_T_32) begin + dm_temp = 4'h0; + end + if (io_dbg_rst_l) begin + dm_temp_0 = 1'h0; + end + if (_T_32) begin + dmcontrol_wren_Q = 1'h0; + end + if (_T_32) begin + _T_212 = 1'h0; + end + if (_T_32) begin + _T_218 = 1'h0; + end + if (_T_32) begin + _T_223 = 1'h0; + end + if (_T_32) begin + abs_temp_12 = 1'h0; + end + if (_T_32) begin + abs_temp_10_8 = 3'h0; + end + if (_T_32) begin + command_reg = 32'h0; + end + if (_T_32) begin + data0_reg = 32'h0; + end + if (_T_32) begin + _T_345 = 32'h0; + end + if (_T_517) begin + _T_518 = 3'h0; + end + if (_T_32) begin + _T_522 = 32'h0; + end + if (_T_32) begin + _T_603 = 4'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge rvclkhdr_1_io_l1clk or posedge _T_32) begin + if (_T_32) begin + temp_sbcs_22 <= 1'h0; + end else if (sbcs_sbbusyerror_wren) begin + temp_sbcs_22 <= sbcs_sbbusyerror_din; + end + end + always @(posedge rvclkhdr_1_io_l1clk or posedge _T_32) begin + if (_T_32) begin + temp_sbcs_21 <= 1'h0; + end else if (sbcs_sbbusy_wren) begin + temp_sbcs_21 <= sbcs_sbbusy_din; + end + end + always @(posedge rvclkhdr_1_io_l1clk or posedge _T_32) begin + if (_T_32) begin + temp_sbcs_20 <= 1'h0; + end else if (sbcs_wren) begin + temp_sbcs_20 <= io_dmi_reg_wdata[20]; + end + end + always @(posedge rvclkhdr_1_io_l1clk or posedge _T_32) begin + if (_T_32) begin + temp_sbcs_19_15 <= 5'h0; + end else if (sbcs_wren) begin + temp_sbcs_19_15 <= io_dmi_reg_wdata[19:15]; + end + end + always @(posedge rvclkhdr_1_io_l1clk or posedge _T_32) begin + if (_T_32) begin + temp_sbcs_14_12 <= 3'h0; + end else if (sbcs_sberror_wren) begin + if (_T_555) begin + temp_sbcs_14_12 <= _T_565; + end else if (_T_566) begin + if (sbcs_unaligned) begin + temp_sbcs_14_12 <= 3'h3; + end else begin + temp_sbcs_14_12 <= 3'h4; + end + end else if (_T_573) begin + if (sbcs_unaligned) begin + temp_sbcs_14_12 <= 3'h3; + end else begin + temp_sbcs_14_12 <= 3'h4; + end + end else if (_T_580) begin + temp_sbcs_14_12 <= 3'h0; + end else if (_T_582) begin + temp_sbcs_14_12 <= 3'h0; + end else if (_T_588) begin + temp_sbcs_14_12 <= 3'h0; + end else if (_T_590) begin + temp_sbcs_14_12 <= 3'h0; + end else if (_T_592) begin + temp_sbcs_14_12 <= 3'h2; + end else if (_T_595) begin + temp_sbcs_14_12 <= 3'h2; + end else begin + temp_sbcs_14_12 <= 3'h0; + end + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge _T_32) begin + if (_T_32) begin + sbdata0_reg <= 32'h0; + end else begin + sbdata0_reg <= _T_105 | _T_109; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge _T_32) begin + if (_T_32) begin + sbdata1_reg <= 32'h0; + end else begin + sbdata1_reg <= _T_112 | _T_116; + end + end + always @(posedge rvclkhdr_4_io_l1clk or posedge _T_32) begin + if (_T_32) begin + _T_137 <= 32'h0; + end else begin + _T_137 <= _T_127 | _T_133; + end + end + always @(posedge rvclkhdr_io_l1clk or posedge _T_32) begin + if (_T_32) begin + dm_temp <= 4'h0; + end else if (dmcontrol_wren) begin + dm_temp <= _T_158; + end + end + always @(posedge rvclkhdr_io_l1clk or posedge io_dbg_rst_l) begin + if (io_dbg_rst_l) begin + dm_temp_0 <= 1'h0; + end else if (dmcontrol_wren) begin + dm_temp_0 <= io_dmi_reg_wdata[0]; + end + end + always @(posedge rvclkhdr_io_l1clk or posedge _T_32) begin + if (_T_32) begin + dmcontrol_wren_Q <= 1'h0; + end else begin + dmcontrol_wren_Q <= _T_150 & io_dmi_reg_wr_en; + end + end + always @(posedge rvclkhdr_io_l1clk or posedge _T_32) begin + if (_T_32) begin + _T_212 <= 1'h0; + end else if (dmstatus_resumeack_wren) begin + _T_212 <= _T_190; + end + end + always @(posedge rvclkhdr_io_l1clk or posedge _T_32) begin + if (_T_32) begin + _T_218 <= 1'h0; + end else begin + _T_218 <= io_dec_tlu_dbg_halted & _T_216; + end + end + always @(posedge rvclkhdr_io_l1clk or posedge _T_32) begin + if (_T_32) begin + _T_223 <= 1'h0; + end else if (dmstatus_havereset_wren) begin + _T_223 <= _T_222; + end + end + always @(posedge rvclkhdr_io_l1clk or posedge _T_32) begin + if (_T_32) begin + abs_temp_12 <= 1'h0; + end else if (abstractcs_busy_wren) begin + if (_T_346) begin + abs_temp_12 <= 1'h0; + end else if (_T_364) begin + abs_temp_12 <= 1'h0; + end else begin + abs_temp_12 <= _T_376; + end + end + end + always @(posedge rvclkhdr_io_l1clk or posedge _T_32) begin + if (_T_32) begin + abs_temp_10_8 <= 3'h0; + end else begin + abs_temp_10_8 <= _T_289 | _T_294; + end + end + always @(posedge rvclkhdr_5_io_l1clk or posedge _T_32) begin + if (_T_32) begin + command_reg <= 32'h0; + end else begin + command_reg <= {_T_315,_T_313}; + end + end + always @(posedge rvclkhdr_6_io_l1clk or posedge _T_32) begin + if (_T_32) begin + data0_reg <= 32'h0; + end else begin + data0_reg <= _T_329 | _T_332; + end + end + always @(posedge rvclkhdr_7_io_l1clk or posedge _T_32) begin + if (_T_32) begin + _T_345 <= 32'h0; + end else begin + _T_345 <= _T_341 & io_dmi_reg_wdata; + end + end + always @(posedge rvclkhdr_io_l1clk or posedge _T_517) begin + if (_T_517) begin + _T_518 <= 3'h0; + end else if (dbg_state_en) begin + if (_T_346) begin + if (_T_348) begin + _T_518 <= 3'h2; + end else begin + _T_518 <= 3'h1; + end + end else if (_T_364) begin + if (dmcontrol_reg[1]) begin + _T_518 <= 3'h0; + end else begin + _T_518 <= 3'h2; + end + end else if (_T_376) begin + if (_T_380) begin + if (_T_384) begin + _T_518 <= 3'h6; + end else begin + _T_518 <= 3'h3; + end + end else if (dmcontrol_reg[31]) begin + _T_518 <= 3'h1; + end else begin + _T_518 <= 3'h0; + end + end else if (_T_414) begin + if (dmcontrol_reg[1]) begin + _T_518 <= 3'h0; + end else if (_T_417) begin + _T_518 <= 3'h5; + end else begin + _T_518 <= 3'h4; + end + end else if (_T_431) begin + if (dmcontrol_reg[1]) begin + _T_518 <= 3'h0; + end else begin + _T_518 <= 3'h5; + end + end else if (_T_442) begin + if (dmcontrol_reg[1]) begin + _T_518 <= 3'h0; + end else begin + _T_518 <= 3'h2; + end + end else begin + _T_518 <= 3'h0; + end + end + end + always @(posedge rvclkhdr_io_l1clk or posedge _T_32) begin + if (_T_32) begin + _T_522 <= 32'h0; + end else if (io_dmi_reg_en) begin + _T_522 <= dmi_reg_rdata_din; + end + end + always @(posedge rvclkhdr_1_io_l1clk or posedge _T_32) begin + if (_T_32) begin + _T_603 <= 4'h0; + end else if (sb_state_en) begin + if (_T_555) begin + if (sbdata0_reg_wren0) begin + _T_603 <= 4'h2; + end else begin + _T_603 <= 4'h1; + end + end else if (_T_566) begin + if (_T_567) begin + _T_603 <= 4'h9; + end else begin + _T_603 <= 4'h3; + end + end else if (_T_573) begin + if (_T_567) begin + _T_603 <= 4'h9; + end else begin + _T_603 <= 4'h4; + end + end else if (_T_580) begin + _T_603 <= 4'h7; + end else if (_T_582) begin + if (_T_583) begin + _T_603 <= 4'h8; + end else if (sb_bus_cmd_write_data) begin + _T_603 <= 4'h5; + end else begin + _T_603 <= 4'h6; + end + end else if (_T_588) begin + _T_603 <= 4'h8; + end else if (_T_590) begin + _T_603 <= 4'h8; + end else if (_T_592) begin + _T_603 <= 4'h9; + end else if (_T_595) begin + _T_603 <= 4'h9; + end else begin + _T_603 <= 4'h0; + end + end + end +endmodule diff --git a/el2_dec.fir b/el2_dec.fir index c713d335..4721a200 100644 --- a/el2_dec.fir +++ b/el2_dec.fir @@ -3,7 +3,7 @@ circuit el2_dec : module el2_dec_ib_ctl : input clock : Clock input reset : Reset - output io : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>, flip i0_brp : {valid : UInt<1>, bits : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, flip ifu_i0_bp_index : UInt<8>, flip ifu_i0_bp_fghr : UInt<8>, flip ifu_i0_bp_btag : UInt<5>, flip ifu_i0_pc4 : UInt<1>, flip ifu_i0_valid : UInt<1>, flip ifu_i0_icaf : UInt<1>, flip ifu_i0_icaf_type : UInt<2>, flip ifu_i0_icaf_f1 : UInt<1>, flip ifu_i0_dbecc : UInt<1>, flip ifu_i0_instr : UInt<32>, flip ifu_i0_pc : UInt<31>, dec_ib0_valid_d : UInt<1>, dec_i0_icaf_type_d : UInt<2>, dec_i0_instr_d : UInt<32>, dec_i0_pc_d : UInt<31>, dec_i0_pc4_d : UInt<1>, dec_i0_brp : {valid : UInt<1>, bits : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, dec_i0_bp_index : UInt<8>, dec_i0_bp_fghr : UInt<8>, dec_i0_bp_btag : UInt<5>, dec_i0_icaf_d : UInt<1>, dec_i0_icaf_f1_d : UInt<1>, dec_i0_dbecc_d : UInt<1>, dec_debug_wdata_rs1_d : UInt<1>, dec_debug_fence_d : UInt<1>} + output io : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>, flip i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, flip ifu_i0_bp_index : UInt<8>, flip ifu_i0_bp_fghr : UInt<8>, flip ifu_i0_bp_btag : UInt<5>, flip ifu_i0_pc4 : UInt<1>, flip ifu_i0_valid : UInt<1>, flip ifu_i0_icaf : UInt<1>, flip ifu_i0_icaf_type : UInt<2>, flip ifu_i0_icaf_f1 : UInt<1>, flip ifu_i0_dbecc : UInt<1>, flip ifu_i0_instr : UInt<32>, flip ifu_i0_pc : UInt<31>, dec_ib0_valid_d : UInt<1>, dec_i0_icaf_type_d : UInt<2>, dec_i0_instr_d : UInt<32>, dec_i0_pc_d : UInt<31>, dec_i0_pc4_d : UInt<1>, dec_i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, dec_i0_bp_index : UInt<8>, dec_i0_bp_fghr : UInt<8>, dec_i0_bp_btag : UInt<5>, dec_i0_icaf_d : UInt<1>, dec_i0_icaf_f1_d : UInt<1>, dec_i0_dbecc_d : UInt<1>, dec_debug_wdata_rs1_d : UInt<1>, dec_debug_fence_d : UInt<1>} io.dec_i0_icaf_f1_d <= io.ifu_i0_icaf_f1 @[el2_dec_ib_ctl.scala 8:31] io.dec_i0_dbecc_d <= io.ifu_i0_dbecc @[el2_dec_ib_ctl.scala 9:31] @@ -19,7 +19,6 @@ circuit el2_dec : io.dec_i0_brp.bits.br_error <= io.i0_brp.bits.br_error @[el2_dec_ib_ctl.scala 14:31] io.dec_i0_brp.bits.hist <= io.i0_brp.bits.hist @[el2_dec_ib_ctl.scala 14:31] io.dec_i0_brp.bits.toffset <= io.i0_brp.bits.toffset @[el2_dec_ib_ctl.scala 14:31] - io.dec_i0_brp.bits.valid <= io.i0_brp.bits.valid @[el2_dec_ib_ctl.scala 14:31] io.dec_i0_brp.valid <= io.i0_brp.valid @[el2_dec_ib_ctl.scala 14:31] io.dec_i0_bp_index <= io.ifu_i0_bp_index @[el2_dec_ib_ctl.scala 15:31] io.dec_i0_bp_fghr <= io.ifu_i0_bp_fghr @[el2_dec_ib_ctl.scala 16:31] @@ -2577,7 +2576,7 @@ circuit el2_dec : module el2_dec_decode_ctl : input clock : Clock input reset : AsyncReset - output io : {flip dec_tlu_flush_extint : UInt<1>, flip dec_tlu_force_halt : UInt<1>, dec_extint_stall : UInt<1>, flip ifu_i0_cinst : UInt<16>, dec_i0_inst_wb1 : UInt<32>, dec_i0_pc_wb1 : UInt<31>, flip lsu_nonblock_load_valid_m : UInt<1>, flip lsu_nonblock_load_tag_m : UInt<2>, flip lsu_nonblock_load_inv_r : UInt<1>, flip lsu_nonblock_load_inv_tag_r : UInt<2>, flip lsu_nonblock_load_data_valid : UInt<1>, flip lsu_nonblock_load_data_error : UInt<1>, flip lsu_nonblock_load_data_tag : UInt<2>, flip lsu_nonblock_load_data : UInt<32>, flip dec_i0_trigger_match_d : UInt<4>, flip dec_tlu_wr_pause_r : UInt<1>, flip dec_tlu_pipelining_disable : UInt<1>, flip lsu_trigger_match_m : UInt<4>, flip lsu_pmu_misaligned_m : UInt<1>, flip dec_tlu_debug_stall : UInt<1>, flip dec_tlu_flush_leak_one_r : UInt<1>, flip dec_debug_fence_d : UInt<1>, flip dbg_cmd_wrdata : UInt<2>, flip dec_i0_icaf_d : UInt<1>, flip dec_i0_icaf_f1_d : UInt<1>, flip dec_i0_icaf_type_d : UInt<2>, flip dec_i0_dbecc_d : UInt<1>, flip dec_i0_brp : {valid : UInt<1>, bits : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, flip dec_i0_bp_index : UInt<8>, flip dec_i0_bp_fghr : UInt<8>, flip dec_i0_bp_btag : UInt<5>, flip dec_i0_pc_d : UInt<31>, flip lsu_idle_any : UInt<1>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip exu_div_wren : UInt<1>, flip dec_tlu_i0_kill_writeb_wb : UInt<1>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_i0_kill_writeb_r : UInt<1>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_pause_r : UInt<1>, flip dec_tlu_presync_d : UInt<1>, flip dec_tlu_postsync_d : UInt<1>, flip dec_i0_pc4_d : UInt<1>, flip dec_csr_rddata_d : UInt<32>, flip dec_csr_legal_d : UInt<1>, flip exu_csr_rs1_x : UInt<32>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip exu_flush_final : UInt<1>, flip exu_i0_pc_x : UInt<31>, flip dec_i0_instr_d : UInt<32>, flip dec_ib0_valid_d : UInt<1>, flip exu_i0_result_x : UInt<32>, flip free_clk : Clock, flip active_clk : Clock, flip clk_override : UInt<1>, dec_i0_rs1_en_d : UInt<1>, dec_i0_rs2_en_d : UInt<1>, dec_i0_rs1_d : UInt<5>, dec_i0_rs2_d : UInt<5>, dec_i0_immed_d : UInt<32>, dec_i0_br_immed_d : UInt<12>, i0_ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, dec_i0_decode_d : UInt<1>, dec_i0_alu_decode_d : UInt<1>, dec_i0_rs1_bypass_data_d : UInt<32>, dec_i0_rs2_bypass_data_d : UInt<32>, dec_i0_waddr_r : UInt<5>, dec_i0_wen_r : UInt<1>, dec_i0_wdata_r : UInt<32>, dec_i0_select_pc_d : UInt<1>, dec_i0_rs1_bypass_en_d : UInt<2>, dec_i0_rs2_bypass_en_d : UInt<2>, lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, div_waddr_wb : UInt<5>, dec_div_cancel : UInt<1>, dec_lsu_valid_raw_d : UInt<1>, dec_lsu_offset_d : UInt<12>, dec_csr_ren_d : UInt<1>, dec_csr_wen_unq_d : UInt<1>, dec_csr_any_unq_d : UInt<1>, dec_csr_rdaddr_d : UInt<12>, dec_csr_wen_r : UInt<1>, dec_csr_wraddr_r : UInt<12>, dec_csr_wrdata_r : UInt<32>, dec_csr_stall_int_ff : UInt<1>, dec_tlu_i0_valid_r : UInt<1>, dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, dec_tlu_i0_pc_r : UInt<31>, dec_illegal_inst : UInt<32>, pred_correct_npc_x : UInt<31>, dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, i0_predict_fghr_d : UInt<8>, i0_predict_index_d : UInt<8>, i0_predict_btag_d : UInt<5>, dec_data_en : UInt<2>, dec_ctl_en : UInt<2>, dec_pmu_instr_decoded : UInt<1>, dec_pmu_decode_stall : UInt<1>, dec_pmu_presync_stall : UInt<1>, dec_pmu_postsync_stall : UInt<1>, dec_nonblock_load_wen : UInt<1>, dec_nonblock_load_waddr : UInt<5>, dec_pause_state : UInt<1>, dec_pause_state_cg : UInt<1>, dec_div_active : UInt<1>, flip scan_mode : UInt<1>} + output io : {flip dec_tlu_flush_extint : UInt<1>, flip dec_tlu_force_halt : UInt<1>, dec_extint_stall : UInt<1>, flip ifu_i0_cinst : UInt<16>, dec_i0_inst_wb1 : UInt<32>, dec_i0_pc_wb1 : UInt<31>, flip lsu_nonblock_load_valid_m : UInt<1>, flip lsu_nonblock_load_tag_m : UInt<2>, flip lsu_nonblock_load_inv_r : UInt<1>, flip lsu_nonblock_load_inv_tag_r : UInt<2>, flip lsu_nonblock_load_data_valid : UInt<1>, flip lsu_nonblock_load_data_error : UInt<1>, flip lsu_nonblock_load_data_tag : UInt<2>, flip lsu_nonblock_load_data : UInt<32>, flip dec_i0_trigger_match_d : UInt<4>, flip dec_tlu_wr_pause_r : UInt<1>, flip dec_tlu_pipelining_disable : UInt<1>, flip lsu_trigger_match_m : UInt<4>, flip lsu_pmu_misaligned_m : UInt<1>, flip dec_tlu_debug_stall : UInt<1>, flip dec_tlu_flush_leak_one_r : UInt<1>, flip dec_debug_fence_d : UInt<1>, flip dbg_cmd_wrdata : UInt<2>, flip dec_i0_icaf_d : UInt<1>, flip dec_i0_icaf_f1_d : UInt<1>, flip dec_i0_icaf_type_d : UInt<2>, flip dec_i0_dbecc_d : UInt<1>, flip dec_i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, flip dec_i0_bp_index : UInt<8>, flip dec_i0_bp_fghr : UInt<8>, flip dec_i0_bp_btag : UInt<5>, flip dec_i0_pc_d : UInt<31>, flip lsu_idle_any : UInt<1>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip exu_div_wren : UInt<1>, flip dec_tlu_i0_kill_writeb_wb : UInt<1>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_i0_kill_writeb_r : UInt<1>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_pause_r : UInt<1>, flip dec_tlu_presync_d : UInt<1>, flip dec_tlu_postsync_d : UInt<1>, flip dec_i0_pc4_d : UInt<1>, flip dec_csr_rddata_d : UInt<32>, flip dec_csr_legal_d : UInt<1>, flip exu_csr_rs1_x : UInt<32>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip exu_flush_final : UInt<1>, flip exu_i0_pc_x : UInt<31>, flip dec_i0_instr_d : UInt<32>, flip dec_ib0_valid_d : UInt<1>, flip exu_i0_result_x : UInt<32>, flip free_clk : Clock, flip active_clk : Clock, flip clk_override : UInt<1>, dec_i0_rs1_en_d : UInt<1>, dec_i0_rs2_en_d : UInt<1>, dec_i0_rs1_d : UInt<5>, dec_i0_rs2_d : UInt<5>, dec_i0_immed_d : UInt<32>, dec_i0_br_immed_d : UInt<12>, i0_ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, dec_i0_decode_d : UInt<1>, dec_i0_alu_decode_d : UInt<1>, dec_i0_rs1_bypass_data_d : UInt<32>, dec_i0_rs2_bypass_data_d : UInt<32>, dec_i0_waddr_r : UInt<5>, dec_i0_wen_r : UInt<1>, dec_i0_wdata_r : UInt<32>, dec_i0_select_pc_d : UInt<1>, dec_i0_rs1_bypass_en_d : UInt<2>, dec_i0_rs2_bypass_en_d : UInt<2>, lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, div_waddr_wb : UInt<5>, dec_div_cancel : UInt<1>, dec_lsu_valid_raw_d : UInt<1>, dec_lsu_offset_d : UInt<12>, dec_csr_ren_d : UInt<1>, dec_csr_wen_unq_d : UInt<1>, dec_csr_any_unq_d : UInt<1>, dec_csr_rdaddr_d : UInt<12>, dec_csr_wen_r : UInt<1>, dec_csr_wraddr_r : UInt<12>, dec_csr_wrdata_r : UInt<32>, dec_csr_stall_int_ff : UInt<1>, dec_tlu_i0_valid_r : UInt<1>, dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, dec_tlu_i0_pc_r : UInt<31>, dec_illegal_inst : UInt<32>, pred_correct_npc_x : UInt<31>, dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, i0_predict_fghr_d : UInt<8>, i0_predict_index_d : UInt<8>, i0_predict_btag_d : UInt<5>, dec_data_en : UInt<2>, dec_ctl_en : UInt<2>, dec_pmu_instr_decoded : UInt<1>, dec_pmu_decode_stall : UInt<1>, dec_pmu_presync_stall : UInt<1>, dec_pmu_postsync_stall : UInt<1>, dec_nonblock_load_wen : UInt<1>, dec_nonblock_load_waddr : UInt<5>, dec_pause_state : UInt<1>, dec_pause_state_cg : UInt<1>, dec_div_active : UInt<1>, flip scan_mode : UInt<1>} wire _T : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}} @[el2_dec_decode_ctl.scala 126:27] _T.bits.bfp <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] @@ -2628,11 +2627,11 @@ circuit el2_dec : wire x_t_in : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 133:20] wire r_t : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 134:17] wire r_t_in : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 135:23] - wire d_d : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 136:17] - wire x_d : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 137:17] - wire r_d : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 138:17] - wire r_d_in : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 139:20] - wire wbd : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 140:17] + wire d_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_dec_decode_ctl.scala 136:17] + wire x_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_dec_decode_ctl.scala 137:17] + wire r_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_dec_decode_ctl.scala 138:17] + wire r_d_in : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_dec_decode_ctl.scala 139:20] + wire wbd : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_dec_decode_ctl.scala 140:17] wire i0_d_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 141:20] wire i0_rs1_class_d : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 142:28] wire i0_rs2_class_d : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 143:28] @@ -2642,14 +2641,14 @@ circuit el2_dec : i0_rs2_depth_d <= UInt<1>("h00") wire cam_wen : UInt<4> cam_wen <= UInt<1>("h00") - wire cam : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}[4] @[el2_dec_decode_ctl.scala 147:17] + wire cam : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}[4] @[el2_dec_decode_ctl.scala 147:17] wire cam_write : UInt<1> cam_write <= UInt<1>("h00") wire cam_inv_reset_val : UInt<1>[4] @[el2_dec_decode_ctl.scala 149:29] wire cam_data_reset_val : UInt<1>[4] @[el2_dec_decode_ctl.scala 150:30] wire nonblock_load_write : UInt<1>[4] @[el2_dec_decode_ctl.scala 151:31] - wire cam_raw : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}[4] @[el2_dec_decode_ctl.scala 152:20] - wire cam_in : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}[4] @[el2_dec_decode_ctl.scala 153:20] + wire cam_raw : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}[4] @[el2_dec_decode_ctl.scala 152:20] + wire cam_in : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}[4] @[el2_dec_decode_ctl.scala 153:20] wire i0_dp : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[el2_dec_decode_ctl.scala 155:18] wire i0_dp_raw : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[el2_dec_decode_ctl.scala 156:22] wire i0_rs1bypass : UInt<3> @@ -3060,34 +3059,34 @@ circuit el2_dec : cam_write <= io.lsu_nonblock_load_valid_m @[el2_dec_decode_ctl.scala 305:25] node cam_write_tag = bits(io.lsu_nonblock_load_tag_m, 1, 0) @[el2_dec_decode_ctl.scala 306:54] node cam_data_reset = or(io.lsu_nonblock_load_data_valid, io.lsu_nonblock_load_data_error) @[el2_dec_decode_ctl.scala 311:63] - node _T_89 = bits(x_d.i0load, 0, 0) @[el2_dec_decode_ctl.scala 314:43] - node nonblock_load_rd = mux(_T_89, x_d.i0rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 314:31] + node _T_89 = bits(x_d.bits.i0load, 0, 0) @[el2_dec_decode_ctl.scala 314:48] + node nonblock_load_rd = mux(_T_89, x_d.bits.i0rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 314:31] node _T_90 = bits(i0_r_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 318:116] reg nonblock_load_valid_m_delay : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_90 : @[Reg.scala 28:19] nonblock_load_valid_m_delay <= io.lsu_nonblock_load_valid_m @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node i0_load_kill_wen_r = and(nonblock_load_valid_m_delay, r_d.i0load) @[el2_dec_decode_ctl.scala 319:56] - node _T_91 = eq(io.lsu_nonblock_load_inv_tag_r, cam[0].tag) @[el2_dec_decode_ctl.scala 321:66] + node i0_load_kill_wen_r = and(nonblock_load_valid_m_delay, r_d.bits.i0load) @[el2_dec_decode_ctl.scala 319:56] + node _T_91 = eq(io.lsu_nonblock_load_inv_tag_r, cam[0].bits.tag) @[el2_dec_decode_ctl.scala 321:66] node _T_92 = and(io.lsu_nonblock_load_inv_r, _T_91) @[el2_dec_decode_ctl.scala 321:45] - node _T_93 = and(_T_92, cam[0].valid) @[el2_dec_decode_ctl.scala 321:82] + node _T_93 = and(_T_92, cam[0].valid) @[el2_dec_decode_ctl.scala 321:87] cam_inv_reset_val[0] <= _T_93 @[el2_dec_decode_ctl.scala 321:26] - node _T_94 = eq(io.lsu_nonblock_load_data_tag, cam[0].tag) @[el2_dec_decode_ctl.scala 322:67] + node _T_94 = eq(io.lsu_nonblock_load_data_tag, cam[0].bits.tag) @[el2_dec_decode_ctl.scala 322:67] node _T_95 = and(cam_data_reset, _T_94) @[el2_dec_decode_ctl.scala 322:45] - node _T_96 = and(_T_95, cam_raw[0].valid) @[el2_dec_decode_ctl.scala 322:83] + node _T_96 = and(_T_95, cam_raw[0].valid) @[el2_dec_decode_ctl.scala 322:88] cam_data_reset_val[0] <= _T_96 @[el2_dec_decode_ctl.scala 322:27] - wire _T_97 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 323:28] - _T_97.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 323:28] - _T_97.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 323:28] - _T_97.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28] + wire _T_97 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 323:28] + _T_97.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 323:28] + _T_97.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 323:28] + _T_97.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28] _T_97.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28] - cam_in[0].rd <= _T_97.rd @[el2_dec_decode_ctl.scala 323:14] - cam_in[0].tag <= _T_97.tag @[el2_dec_decode_ctl.scala 323:14] - cam_in[0].wb <= _T_97.wb @[el2_dec_decode_ctl.scala 323:14] + cam_in[0].bits.rd <= _T_97.bits.rd @[el2_dec_decode_ctl.scala 323:14] + cam_in[0].bits.tag <= _T_97.bits.tag @[el2_dec_decode_ctl.scala 323:14] + cam_in[0].bits.wb <= _T_97.bits.wb @[el2_dec_decode_ctl.scala 323:14] cam_in[0].valid <= _T_97.valid @[el2_dec_decode_ctl.scala 323:14] - cam[0].rd <= cam_raw[0].rd @[el2_dec_decode_ctl.scala 324:11] - cam[0].tag <= cam_raw[0].tag @[el2_dec_decode_ctl.scala 324:11] - cam[0].wb <= cam_raw[0].wb @[el2_dec_decode_ctl.scala 324:11] + cam[0].bits.rd <= cam_raw[0].bits.rd @[el2_dec_decode_ctl.scala 324:11] + cam[0].bits.tag <= cam_raw[0].bits.tag @[el2_dec_decode_ctl.scala 324:11] + cam[0].bits.wb <= cam_raw[0].bits.wb @[el2_dec_decode_ctl.scala 324:11] cam[0].valid <= cam_raw[0].valid @[el2_dec_decode_ctl.scala 324:11] node _T_98 = bits(cam_data_reset_val[0], 0, 0) @[el2_dec_decode_ctl.scala 326:32] when _T_98 : @[el2_dec_decode_ctl.scala 326:39] @@ -3097,75 +3096,75 @@ circuit el2_dec : node _T_100 = bits(_T_99, 0, 0) @[el2_dec_decode_ctl.scala 329:21] when _T_100 : @[el2_dec_decode_ctl.scala 329:28] cam_in[0].valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 330:27] - cam_in[0].wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:27] - cam_in[0].tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:27] - cam_in[0].rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:27] + cam_in[0].bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:32] + cam_in[0].bits.tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:32] + cam_in[0].bits.rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:32] skip @[el2_dec_decode_ctl.scala 329:28] - else : @[el2_dec_decode_ctl.scala 334:116] + else : @[el2_dec_decode_ctl.scala 334:131] node _T_101 = bits(cam_inv_reset_val[0], 0, 0) @[el2_dec_decode_ctl.scala 334:37] node _T_102 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 334:57] - node _T_103 = eq(r_d_in.i0rd, cam[0].rd) @[el2_dec_decode_ctl.scala 334:80] + node _T_103 = eq(r_d_in.bits.i0rd, cam[0].bits.rd) @[el2_dec_decode_ctl.scala 334:85] node _T_104 = and(_T_102, _T_103) @[el2_dec_decode_ctl.scala 334:64] - node _T_105 = bits(cam[0].wb, 0, 0) @[el2_dec_decode_ctl.scala 334:108] - node _T_106 = and(_T_104, _T_105) @[el2_dec_decode_ctl.scala 334:95] + node _T_105 = bits(cam[0].bits.wb, 0, 0) @[el2_dec_decode_ctl.scala 334:123] + node _T_106 = and(_T_104, _T_105) @[el2_dec_decode_ctl.scala 334:105] node _T_107 = or(_T_101, _T_106) @[el2_dec_decode_ctl.scala 334:44] - when _T_107 : @[el2_dec_decode_ctl.scala 334:116] + when _T_107 : @[el2_dec_decode_ctl.scala 334:131] cam_in[0].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:23] - skip @[el2_dec_decode_ctl.scala 334:116] + skip @[el2_dec_decode_ctl.scala 334:131] else : @[el2_dec_decode_ctl.scala 336:16] - cam_in[0].rd <= cam[0].rd @[el2_dec_decode_ctl.scala 337:22] - cam_in[0].tag <= cam[0].tag @[el2_dec_decode_ctl.scala 337:22] - cam_in[0].wb <= cam[0].wb @[el2_dec_decode_ctl.scala 337:22] + cam_in[0].bits.rd <= cam[0].bits.rd @[el2_dec_decode_ctl.scala 337:22] + cam_in[0].bits.tag <= cam[0].bits.tag @[el2_dec_decode_ctl.scala 337:22] + cam_in[0].bits.wb <= cam[0].bits.wb @[el2_dec_decode_ctl.scala 337:22] cam_in[0].valid <= cam[0].valid @[el2_dec_decode_ctl.scala 337:22] skip @[el2_dec_decode_ctl.scala 336:16] node _T_108 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:37] - node _T_109 = eq(io.lsu_nonblock_load_inv_tag_r, cam[0].tag) @[el2_dec_decode_ctl.scala 339:79] + node _T_109 = eq(io.lsu_nonblock_load_inv_tag_r, cam[0].bits.tag) @[el2_dec_decode_ctl.scala 339:79] node _T_110 = and(_T_108, _T_109) @[el2_dec_decode_ctl.scala 339:44] - node _T_111 = eq(cam[0].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:110] - node _T_112 = and(_T_110, _T_111) @[el2_dec_decode_ctl.scala 339:95] - when _T_112 : @[el2_dec_decode_ctl.scala 339:117] - cam_in[0].wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 340:20] - skip @[el2_dec_decode_ctl.scala 339:117] + node _T_111 = eq(cam[0].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:115] + node _T_112 = and(_T_110, _T_111) @[el2_dec_decode_ctl.scala 339:100] + when _T_112 : @[el2_dec_decode_ctl.scala 339:122] + cam_in[0].bits.wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 340:25] + skip @[el2_dec_decode_ctl.scala 339:122] when io.dec_tlu_force_halt : @[el2_dec_decode_ctl.scala 343:32] cam_in[0].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 344:23] skip @[el2_dec_decode_ctl.scala 343:32] - wire _T_113 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 347:70] - _T_113.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 347:70] - _T_113.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 347:70] - _T_113.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70] + wire _T_113 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 347:70] + _T_113.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 347:70] + _T_113.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 347:70] + _T_113.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70] _T_113.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70] - reg _T_114 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}, io.free_clk with : (reset => (reset, _T_113)) @[el2_dec_decode_ctl.scala 347:47] - _T_114.rd <= cam_in[0].rd @[el2_dec_decode_ctl.scala 347:47] - _T_114.tag <= cam_in[0].tag @[el2_dec_decode_ctl.scala 347:47] - _T_114.wb <= cam_in[0].wb @[el2_dec_decode_ctl.scala 347:47] + reg _T_114 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_113)) @[el2_dec_decode_ctl.scala 347:47] + _T_114.bits.rd <= cam_in[0].bits.rd @[el2_dec_decode_ctl.scala 347:47] + _T_114.bits.tag <= cam_in[0].bits.tag @[el2_dec_decode_ctl.scala 347:47] + _T_114.bits.wb <= cam_in[0].bits.wb @[el2_dec_decode_ctl.scala 347:47] _T_114.valid <= cam_in[0].valid @[el2_dec_decode_ctl.scala 347:47] - cam_raw[0].rd <= _T_114.rd @[el2_dec_decode_ctl.scala 347:15] - cam_raw[0].tag <= _T_114.tag @[el2_dec_decode_ctl.scala 347:15] - cam_raw[0].wb <= _T_114.wb @[el2_dec_decode_ctl.scala 347:15] + cam_raw[0].bits.rd <= _T_114.bits.rd @[el2_dec_decode_ctl.scala 347:15] + cam_raw[0].bits.tag <= _T_114.bits.tag @[el2_dec_decode_ctl.scala 347:15] + cam_raw[0].bits.wb <= _T_114.bits.wb @[el2_dec_decode_ctl.scala 347:15] cam_raw[0].valid <= _T_114.valid @[el2_dec_decode_ctl.scala 347:15] - node _T_115 = eq(io.lsu_nonblock_load_data_tag, cam_raw[0].tag) @[el2_dec_decode_ctl.scala 348:46] - node _T_116 = and(_T_115, cam_raw[0].valid) @[el2_dec_decode_ctl.scala 348:66] + node _T_115 = eq(io.lsu_nonblock_load_data_tag, cam_raw[0].bits.tag) @[el2_dec_decode_ctl.scala 348:46] + node _T_116 = and(_T_115, cam_raw[0].valid) @[el2_dec_decode_ctl.scala 348:71] nonblock_load_write[0] <= _T_116 @[el2_dec_decode_ctl.scala 348:28] - node _T_117 = eq(io.lsu_nonblock_load_inv_tag_r, cam[1].tag) @[el2_dec_decode_ctl.scala 321:66] + node _T_117 = eq(io.lsu_nonblock_load_inv_tag_r, cam[1].bits.tag) @[el2_dec_decode_ctl.scala 321:66] node _T_118 = and(io.lsu_nonblock_load_inv_r, _T_117) @[el2_dec_decode_ctl.scala 321:45] - node _T_119 = and(_T_118, cam[1].valid) @[el2_dec_decode_ctl.scala 321:82] + node _T_119 = and(_T_118, cam[1].valid) @[el2_dec_decode_ctl.scala 321:87] cam_inv_reset_val[1] <= _T_119 @[el2_dec_decode_ctl.scala 321:26] - node _T_120 = eq(io.lsu_nonblock_load_data_tag, cam[1].tag) @[el2_dec_decode_ctl.scala 322:67] + node _T_120 = eq(io.lsu_nonblock_load_data_tag, cam[1].bits.tag) @[el2_dec_decode_ctl.scala 322:67] node _T_121 = and(cam_data_reset, _T_120) @[el2_dec_decode_ctl.scala 322:45] - node _T_122 = and(_T_121, cam_raw[1].valid) @[el2_dec_decode_ctl.scala 322:83] + node _T_122 = and(_T_121, cam_raw[1].valid) @[el2_dec_decode_ctl.scala 322:88] cam_data_reset_val[1] <= _T_122 @[el2_dec_decode_ctl.scala 322:27] - wire _T_123 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 323:28] - _T_123.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 323:28] - _T_123.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 323:28] - _T_123.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28] + wire _T_123 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 323:28] + _T_123.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 323:28] + _T_123.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 323:28] + _T_123.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28] _T_123.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28] - cam_in[1].rd <= _T_123.rd @[el2_dec_decode_ctl.scala 323:14] - cam_in[1].tag <= _T_123.tag @[el2_dec_decode_ctl.scala 323:14] - cam_in[1].wb <= _T_123.wb @[el2_dec_decode_ctl.scala 323:14] + cam_in[1].bits.rd <= _T_123.bits.rd @[el2_dec_decode_ctl.scala 323:14] + cam_in[1].bits.tag <= _T_123.bits.tag @[el2_dec_decode_ctl.scala 323:14] + cam_in[1].bits.wb <= _T_123.bits.wb @[el2_dec_decode_ctl.scala 323:14] cam_in[1].valid <= _T_123.valid @[el2_dec_decode_ctl.scala 323:14] - cam[1].rd <= cam_raw[1].rd @[el2_dec_decode_ctl.scala 324:11] - cam[1].tag <= cam_raw[1].tag @[el2_dec_decode_ctl.scala 324:11] - cam[1].wb <= cam_raw[1].wb @[el2_dec_decode_ctl.scala 324:11] + cam[1].bits.rd <= cam_raw[1].bits.rd @[el2_dec_decode_ctl.scala 324:11] + cam[1].bits.tag <= cam_raw[1].bits.tag @[el2_dec_decode_ctl.scala 324:11] + cam[1].bits.wb <= cam_raw[1].bits.wb @[el2_dec_decode_ctl.scala 324:11] cam[1].valid <= cam_raw[1].valid @[el2_dec_decode_ctl.scala 324:11] node _T_124 = bits(cam_data_reset_val[1], 0, 0) @[el2_dec_decode_ctl.scala 326:32] when _T_124 : @[el2_dec_decode_ctl.scala 326:39] @@ -3175,75 +3174,75 @@ circuit el2_dec : node _T_126 = bits(_T_125, 0, 0) @[el2_dec_decode_ctl.scala 329:21] when _T_126 : @[el2_dec_decode_ctl.scala 329:28] cam_in[1].valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 330:27] - cam_in[1].wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:27] - cam_in[1].tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:27] - cam_in[1].rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:27] + cam_in[1].bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:32] + cam_in[1].bits.tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:32] + cam_in[1].bits.rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:32] skip @[el2_dec_decode_ctl.scala 329:28] - else : @[el2_dec_decode_ctl.scala 334:116] + else : @[el2_dec_decode_ctl.scala 334:131] node _T_127 = bits(cam_inv_reset_val[1], 0, 0) @[el2_dec_decode_ctl.scala 334:37] node _T_128 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 334:57] - node _T_129 = eq(r_d_in.i0rd, cam[1].rd) @[el2_dec_decode_ctl.scala 334:80] + node _T_129 = eq(r_d_in.bits.i0rd, cam[1].bits.rd) @[el2_dec_decode_ctl.scala 334:85] node _T_130 = and(_T_128, _T_129) @[el2_dec_decode_ctl.scala 334:64] - node _T_131 = bits(cam[1].wb, 0, 0) @[el2_dec_decode_ctl.scala 334:108] - node _T_132 = and(_T_130, _T_131) @[el2_dec_decode_ctl.scala 334:95] + node _T_131 = bits(cam[1].bits.wb, 0, 0) @[el2_dec_decode_ctl.scala 334:123] + node _T_132 = and(_T_130, _T_131) @[el2_dec_decode_ctl.scala 334:105] node _T_133 = or(_T_127, _T_132) @[el2_dec_decode_ctl.scala 334:44] - when _T_133 : @[el2_dec_decode_ctl.scala 334:116] + when _T_133 : @[el2_dec_decode_ctl.scala 334:131] cam_in[1].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:23] - skip @[el2_dec_decode_ctl.scala 334:116] + skip @[el2_dec_decode_ctl.scala 334:131] else : @[el2_dec_decode_ctl.scala 336:16] - cam_in[1].rd <= cam[1].rd @[el2_dec_decode_ctl.scala 337:22] - cam_in[1].tag <= cam[1].tag @[el2_dec_decode_ctl.scala 337:22] - cam_in[1].wb <= cam[1].wb @[el2_dec_decode_ctl.scala 337:22] + cam_in[1].bits.rd <= cam[1].bits.rd @[el2_dec_decode_ctl.scala 337:22] + cam_in[1].bits.tag <= cam[1].bits.tag @[el2_dec_decode_ctl.scala 337:22] + cam_in[1].bits.wb <= cam[1].bits.wb @[el2_dec_decode_ctl.scala 337:22] cam_in[1].valid <= cam[1].valid @[el2_dec_decode_ctl.scala 337:22] skip @[el2_dec_decode_ctl.scala 336:16] node _T_134 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:37] - node _T_135 = eq(io.lsu_nonblock_load_inv_tag_r, cam[1].tag) @[el2_dec_decode_ctl.scala 339:79] + node _T_135 = eq(io.lsu_nonblock_load_inv_tag_r, cam[1].bits.tag) @[el2_dec_decode_ctl.scala 339:79] node _T_136 = and(_T_134, _T_135) @[el2_dec_decode_ctl.scala 339:44] - node _T_137 = eq(cam[1].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:110] - node _T_138 = and(_T_136, _T_137) @[el2_dec_decode_ctl.scala 339:95] - when _T_138 : @[el2_dec_decode_ctl.scala 339:117] - cam_in[1].wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 340:20] - skip @[el2_dec_decode_ctl.scala 339:117] + node _T_137 = eq(cam[1].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:115] + node _T_138 = and(_T_136, _T_137) @[el2_dec_decode_ctl.scala 339:100] + when _T_138 : @[el2_dec_decode_ctl.scala 339:122] + cam_in[1].bits.wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 340:25] + skip @[el2_dec_decode_ctl.scala 339:122] when io.dec_tlu_force_halt : @[el2_dec_decode_ctl.scala 343:32] cam_in[1].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 344:23] skip @[el2_dec_decode_ctl.scala 343:32] - wire _T_139 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 347:70] - _T_139.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 347:70] - _T_139.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 347:70] - _T_139.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70] + wire _T_139 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 347:70] + _T_139.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 347:70] + _T_139.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 347:70] + _T_139.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70] _T_139.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70] - reg _T_140 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}, io.free_clk with : (reset => (reset, _T_139)) @[el2_dec_decode_ctl.scala 347:47] - _T_140.rd <= cam_in[1].rd @[el2_dec_decode_ctl.scala 347:47] - _T_140.tag <= cam_in[1].tag @[el2_dec_decode_ctl.scala 347:47] - _T_140.wb <= cam_in[1].wb @[el2_dec_decode_ctl.scala 347:47] + reg _T_140 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_139)) @[el2_dec_decode_ctl.scala 347:47] + _T_140.bits.rd <= cam_in[1].bits.rd @[el2_dec_decode_ctl.scala 347:47] + _T_140.bits.tag <= cam_in[1].bits.tag @[el2_dec_decode_ctl.scala 347:47] + _T_140.bits.wb <= cam_in[1].bits.wb @[el2_dec_decode_ctl.scala 347:47] _T_140.valid <= cam_in[1].valid @[el2_dec_decode_ctl.scala 347:47] - cam_raw[1].rd <= _T_140.rd @[el2_dec_decode_ctl.scala 347:15] - cam_raw[1].tag <= _T_140.tag @[el2_dec_decode_ctl.scala 347:15] - cam_raw[1].wb <= _T_140.wb @[el2_dec_decode_ctl.scala 347:15] + cam_raw[1].bits.rd <= _T_140.bits.rd @[el2_dec_decode_ctl.scala 347:15] + cam_raw[1].bits.tag <= _T_140.bits.tag @[el2_dec_decode_ctl.scala 347:15] + cam_raw[1].bits.wb <= _T_140.bits.wb @[el2_dec_decode_ctl.scala 347:15] cam_raw[1].valid <= _T_140.valid @[el2_dec_decode_ctl.scala 347:15] - node _T_141 = eq(io.lsu_nonblock_load_data_tag, cam_raw[1].tag) @[el2_dec_decode_ctl.scala 348:46] - node _T_142 = and(_T_141, cam_raw[1].valid) @[el2_dec_decode_ctl.scala 348:66] + node _T_141 = eq(io.lsu_nonblock_load_data_tag, cam_raw[1].bits.tag) @[el2_dec_decode_ctl.scala 348:46] + node _T_142 = and(_T_141, cam_raw[1].valid) @[el2_dec_decode_ctl.scala 348:71] nonblock_load_write[1] <= _T_142 @[el2_dec_decode_ctl.scala 348:28] - node _T_143 = eq(io.lsu_nonblock_load_inv_tag_r, cam[2].tag) @[el2_dec_decode_ctl.scala 321:66] + node _T_143 = eq(io.lsu_nonblock_load_inv_tag_r, cam[2].bits.tag) @[el2_dec_decode_ctl.scala 321:66] node _T_144 = and(io.lsu_nonblock_load_inv_r, _T_143) @[el2_dec_decode_ctl.scala 321:45] - node _T_145 = and(_T_144, cam[2].valid) @[el2_dec_decode_ctl.scala 321:82] + node _T_145 = and(_T_144, cam[2].valid) @[el2_dec_decode_ctl.scala 321:87] cam_inv_reset_val[2] <= _T_145 @[el2_dec_decode_ctl.scala 321:26] - node _T_146 = eq(io.lsu_nonblock_load_data_tag, cam[2].tag) @[el2_dec_decode_ctl.scala 322:67] + node _T_146 = eq(io.lsu_nonblock_load_data_tag, cam[2].bits.tag) @[el2_dec_decode_ctl.scala 322:67] node _T_147 = and(cam_data_reset, _T_146) @[el2_dec_decode_ctl.scala 322:45] - node _T_148 = and(_T_147, cam_raw[2].valid) @[el2_dec_decode_ctl.scala 322:83] + node _T_148 = and(_T_147, cam_raw[2].valid) @[el2_dec_decode_ctl.scala 322:88] cam_data_reset_val[2] <= _T_148 @[el2_dec_decode_ctl.scala 322:27] - wire _T_149 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 323:28] - _T_149.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 323:28] - _T_149.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 323:28] - _T_149.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28] + wire _T_149 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 323:28] + _T_149.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 323:28] + _T_149.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 323:28] + _T_149.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28] _T_149.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28] - cam_in[2].rd <= _T_149.rd @[el2_dec_decode_ctl.scala 323:14] - cam_in[2].tag <= _T_149.tag @[el2_dec_decode_ctl.scala 323:14] - cam_in[2].wb <= _T_149.wb @[el2_dec_decode_ctl.scala 323:14] + cam_in[2].bits.rd <= _T_149.bits.rd @[el2_dec_decode_ctl.scala 323:14] + cam_in[2].bits.tag <= _T_149.bits.tag @[el2_dec_decode_ctl.scala 323:14] + cam_in[2].bits.wb <= _T_149.bits.wb @[el2_dec_decode_ctl.scala 323:14] cam_in[2].valid <= _T_149.valid @[el2_dec_decode_ctl.scala 323:14] - cam[2].rd <= cam_raw[2].rd @[el2_dec_decode_ctl.scala 324:11] - cam[2].tag <= cam_raw[2].tag @[el2_dec_decode_ctl.scala 324:11] - cam[2].wb <= cam_raw[2].wb @[el2_dec_decode_ctl.scala 324:11] + cam[2].bits.rd <= cam_raw[2].bits.rd @[el2_dec_decode_ctl.scala 324:11] + cam[2].bits.tag <= cam_raw[2].bits.tag @[el2_dec_decode_ctl.scala 324:11] + cam[2].bits.wb <= cam_raw[2].bits.wb @[el2_dec_decode_ctl.scala 324:11] cam[2].valid <= cam_raw[2].valid @[el2_dec_decode_ctl.scala 324:11] node _T_150 = bits(cam_data_reset_val[2], 0, 0) @[el2_dec_decode_ctl.scala 326:32] when _T_150 : @[el2_dec_decode_ctl.scala 326:39] @@ -3253,75 +3252,75 @@ circuit el2_dec : node _T_152 = bits(_T_151, 0, 0) @[el2_dec_decode_ctl.scala 329:21] when _T_152 : @[el2_dec_decode_ctl.scala 329:28] cam_in[2].valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 330:27] - cam_in[2].wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:27] - cam_in[2].tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:27] - cam_in[2].rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:27] + cam_in[2].bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:32] + cam_in[2].bits.tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:32] + cam_in[2].bits.rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:32] skip @[el2_dec_decode_ctl.scala 329:28] - else : @[el2_dec_decode_ctl.scala 334:116] + else : @[el2_dec_decode_ctl.scala 334:131] node _T_153 = bits(cam_inv_reset_val[2], 0, 0) @[el2_dec_decode_ctl.scala 334:37] node _T_154 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 334:57] - node _T_155 = eq(r_d_in.i0rd, cam[2].rd) @[el2_dec_decode_ctl.scala 334:80] + node _T_155 = eq(r_d_in.bits.i0rd, cam[2].bits.rd) @[el2_dec_decode_ctl.scala 334:85] node _T_156 = and(_T_154, _T_155) @[el2_dec_decode_ctl.scala 334:64] - node _T_157 = bits(cam[2].wb, 0, 0) @[el2_dec_decode_ctl.scala 334:108] - node _T_158 = and(_T_156, _T_157) @[el2_dec_decode_ctl.scala 334:95] + node _T_157 = bits(cam[2].bits.wb, 0, 0) @[el2_dec_decode_ctl.scala 334:123] + node _T_158 = and(_T_156, _T_157) @[el2_dec_decode_ctl.scala 334:105] node _T_159 = or(_T_153, _T_158) @[el2_dec_decode_ctl.scala 334:44] - when _T_159 : @[el2_dec_decode_ctl.scala 334:116] + when _T_159 : @[el2_dec_decode_ctl.scala 334:131] cam_in[2].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:23] - skip @[el2_dec_decode_ctl.scala 334:116] + skip @[el2_dec_decode_ctl.scala 334:131] else : @[el2_dec_decode_ctl.scala 336:16] - cam_in[2].rd <= cam[2].rd @[el2_dec_decode_ctl.scala 337:22] - cam_in[2].tag <= cam[2].tag @[el2_dec_decode_ctl.scala 337:22] - cam_in[2].wb <= cam[2].wb @[el2_dec_decode_ctl.scala 337:22] + cam_in[2].bits.rd <= cam[2].bits.rd @[el2_dec_decode_ctl.scala 337:22] + cam_in[2].bits.tag <= cam[2].bits.tag @[el2_dec_decode_ctl.scala 337:22] + cam_in[2].bits.wb <= cam[2].bits.wb @[el2_dec_decode_ctl.scala 337:22] cam_in[2].valid <= cam[2].valid @[el2_dec_decode_ctl.scala 337:22] skip @[el2_dec_decode_ctl.scala 336:16] node _T_160 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:37] - node _T_161 = eq(io.lsu_nonblock_load_inv_tag_r, cam[2].tag) @[el2_dec_decode_ctl.scala 339:79] + node _T_161 = eq(io.lsu_nonblock_load_inv_tag_r, cam[2].bits.tag) @[el2_dec_decode_ctl.scala 339:79] node _T_162 = and(_T_160, _T_161) @[el2_dec_decode_ctl.scala 339:44] - node _T_163 = eq(cam[2].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:110] - node _T_164 = and(_T_162, _T_163) @[el2_dec_decode_ctl.scala 339:95] - when _T_164 : @[el2_dec_decode_ctl.scala 339:117] - cam_in[2].wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 340:20] - skip @[el2_dec_decode_ctl.scala 339:117] + node _T_163 = eq(cam[2].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:115] + node _T_164 = and(_T_162, _T_163) @[el2_dec_decode_ctl.scala 339:100] + when _T_164 : @[el2_dec_decode_ctl.scala 339:122] + cam_in[2].bits.wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 340:25] + skip @[el2_dec_decode_ctl.scala 339:122] when io.dec_tlu_force_halt : @[el2_dec_decode_ctl.scala 343:32] cam_in[2].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 344:23] skip @[el2_dec_decode_ctl.scala 343:32] - wire _T_165 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 347:70] - _T_165.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 347:70] - _T_165.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 347:70] - _T_165.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70] + wire _T_165 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 347:70] + _T_165.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 347:70] + _T_165.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 347:70] + _T_165.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70] _T_165.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70] - reg _T_166 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}, io.free_clk with : (reset => (reset, _T_165)) @[el2_dec_decode_ctl.scala 347:47] - _T_166.rd <= cam_in[2].rd @[el2_dec_decode_ctl.scala 347:47] - _T_166.tag <= cam_in[2].tag @[el2_dec_decode_ctl.scala 347:47] - _T_166.wb <= cam_in[2].wb @[el2_dec_decode_ctl.scala 347:47] + reg _T_166 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_165)) @[el2_dec_decode_ctl.scala 347:47] + _T_166.bits.rd <= cam_in[2].bits.rd @[el2_dec_decode_ctl.scala 347:47] + _T_166.bits.tag <= cam_in[2].bits.tag @[el2_dec_decode_ctl.scala 347:47] + _T_166.bits.wb <= cam_in[2].bits.wb @[el2_dec_decode_ctl.scala 347:47] _T_166.valid <= cam_in[2].valid @[el2_dec_decode_ctl.scala 347:47] - cam_raw[2].rd <= _T_166.rd @[el2_dec_decode_ctl.scala 347:15] - cam_raw[2].tag <= _T_166.tag @[el2_dec_decode_ctl.scala 347:15] - cam_raw[2].wb <= _T_166.wb @[el2_dec_decode_ctl.scala 347:15] + cam_raw[2].bits.rd <= _T_166.bits.rd @[el2_dec_decode_ctl.scala 347:15] + cam_raw[2].bits.tag <= _T_166.bits.tag @[el2_dec_decode_ctl.scala 347:15] + cam_raw[2].bits.wb <= _T_166.bits.wb @[el2_dec_decode_ctl.scala 347:15] cam_raw[2].valid <= _T_166.valid @[el2_dec_decode_ctl.scala 347:15] - node _T_167 = eq(io.lsu_nonblock_load_data_tag, cam_raw[2].tag) @[el2_dec_decode_ctl.scala 348:46] - node _T_168 = and(_T_167, cam_raw[2].valid) @[el2_dec_decode_ctl.scala 348:66] + node _T_167 = eq(io.lsu_nonblock_load_data_tag, cam_raw[2].bits.tag) @[el2_dec_decode_ctl.scala 348:46] + node _T_168 = and(_T_167, cam_raw[2].valid) @[el2_dec_decode_ctl.scala 348:71] nonblock_load_write[2] <= _T_168 @[el2_dec_decode_ctl.scala 348:28] - node _T_169 = eq(io.lsu_nonblock_load_inv_tag_r, cam[3].tag) @[el2_dec_decode_ctl.scala 321:66] + node _T_169 = eq(io.lsu_nonblock_load_inv_tag_r, cam[3].bits.tag) @[el2_dec_decode_ctl.scala 321:66] node _T_170 = and(io.lsu_nonblock_load_inv_r, _T_169) @[el2_dec_decode_ctl.scala 321:45] - node _T_171 = and(_T_170, cam[3].valid) @[el2_dec_decode_ctl.scala 321:82] + node _T_171 = and(_T_170, cam[3].valid) @[el2_dec_decode_ctl.scala 321:87] cam_inv_reset_val[3] <= _T_171 @[el2_dec_decode_ctl.scala 321:26] - node _T_172 = eq(io.lsu_nonblock_load_data_tag, cam[3].tag) @[el2_dec_decode_ctl.scala 322:67] + node _T_172 = eq(io.lsu_nonblock_load_data_tag, cam[3].bits.tag) @[el2_dec_decode_ctl.scala 322:67] node _T_173 = and(cam_data_reset, _T_172) @[el2_dec_decode_ctl.scala 322:45] - node _T_174 = and(_T_173, cam_raw[3].valid) @[el2_dec_decode_ctl.scala 322:83] + node _T_174 = and(_T_173, cam_raw[3].valid) @[el2_dec_decode_ctl.scala 322:88] cam_data_reset_val[3] <= _T_174 @[el2_dec_decode_ctl.scala 322:27] - wire _T_175 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 323:28] - _T_175.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 323:28] - _T_175.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 323:28] - _T_175.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28] + wire _T_175 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 323:28] + _T_175.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 323:28] + _T_175.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 323:28] + _T_175.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28] _T_175.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28] - cam_in[3].rd <= _T_175.rd @[el2_dec_decode_ctl.scala 323:14] - cam_in[3].tag <= _T_175.tag @[el2_dec_decode_ctl.scala 323:14] - cam_in[3].wb <= _T_175.wb @[el2_dec_decode_ctl.scala 323:14] + cam_in[3].bits.rd <= _T_175.bits.rd @[el2_dec_decode_ctl.scala 323:14] + cam_in[3].bits.tag <= _T_175.bits.tag @[el2_dec_decode_ctl.scala 323:14] + cam_in[3].bits.wb <= _T_175.bits.wb @[el2_dec_decode_ctl.scala 323:14] cam_in[3].valid <= _T_175.valid @[el2_dec_decode_ctl.scala 323:14] - cam[3].rd <= cam_raw[3].rd @[el2_dec_decode_ctl.scala 324:11] - cam[3].tag <= cam_raw[3].tag @[el2_dec_decode_ctl.scala 324:11] - cam[3].wb <= cam_raw[3].wb @[el2_dec_decode_ctl.scala 324:11] + cam[3].bits.rd <= cam_raw[3].bits.rd @[el2_dec_decode_ctl.scala 324:11] + cam[3].bits.tag <= cam_raw[3].bits.tag @[el2_dec_decode_ctl.scala 324:11] + cam[3].bits.wb <= cam_raw[3].bits.wb @[el2_dec_decode_ctl.scala 324:11] cam[3].valid <= cam_raw[3].valid @[el2_dec_decode_ctl.scala 324:11] node _T_176 = bits(cam_data_reset_val[3], 0, 0) @[el2_dec_decode_ctl.scala 326:32] when _T_176 : @[el2_dec_decode_ctl.scala 326:39] @@ -3331,58 +3330,58 @@ circuit el2_dec : node _T_178 = bits(_T_177, 0, 0) @[el2_dec_decode_ctl.scala 329:21] when _T_178 : @[el2_dec_decode_ctl.scala 329:28] cam_in[3].valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 330:27] - cam_in[3].wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:27] - cam_in[3].tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:27] - cam_in[3].rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:27] + cam_in[3].bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:32] + cam_in[3].bits.tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:32] + cam_in[3].bits.rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:32] skip @[el2_dec_decode_ctl.scala 329:28] - else : @[el2_dec_decode_ctl.scala 334:116] + else : @[el2_dec_decode_ctl.scala 334:131] node _T_179 = bits(cam_inv_reset_val[3], 0, 0) @[el2_dec_decode_ctl.scala 334:37] node _T_180 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 334:57] - node _T_181 = eq(r_d_in.i0rd, cam[3].rd) @[el2_dec_decode_ctl.scala 334:80] + node _T_181 = eq(r_d_in.bits.i0rd, cam[3].bits.rd) @[el2_dec_decode_ctl.scala 334:85] node _T_182 = and(_T_180, _T_181) @[el2_dec_decode_ctl.scala 334:64] - node _T_183 = bits(cam[3].wb, 0, 0) @[el2_dec_decode_ctl.scala 334:108] - node _T_184 = and(_T_182, _T_183) @[el2_dec_decode_ctl.scala 334:95] + node _T_183 = bits(cam[3].bits.wb, 0, 0) @[el2_dec_decode_ctl.scala 334:123] + node _T_184 = and(_T_182, _T_183) @[el2_dec_decode_ctl.scala 334:105] node _T_185 = or(_T_179, _T_184) @[el2_dec_decode_ctl.scala 334:44] - when _T_185 : @[el2_dec_decode_ctl.scala 334:116] + when _T_185 : @[el2_dec_decode_ctl.scala 334:131] cam_in[3].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:23] - skip @[el2_dec_decode_ctl.scala 334:116] + skip @[el2_dec_decode_ctl.scala 334:131] else : @[el2_dec_decode_ctl.scala 336:16] - cam_in[3].rd <= cam[3].rd @[el2_dec_decode_ctl.scala 337:22] - cam_in[3].tag <= cam[3].tag @[el2_dec_decode_ctl.scala 337:22] - cam_in[3].wb <= cam[3].wb @[el2_dec_decode_ctl.scala 337:22] + cam_in[3].bits.rd <= cam[3].bits.rd @[el2_dec_decode_ctl.scala 337:22] + cam_in[3].bits.tag <= cam[3].bits.tag @[el2_dec_decode_ctl.scala 337:22] + cam_in[3].bits.wb <= cam[3].bits.wb @[el2_dec_decode_ctl.scala 337:22] cam_in[3].valid <= cam[3].valid @[el2_dec_decode_ctl.scala 337:22] skip @[el2_dec_decode_ctl.scala 336:16] node _T_186 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:37] - node _T_187 = eq(io.lsu_nonblock_load_inv_tag_r, cam[3].tag) @[el2_dec_decode_ctl.scala 339:79] + node _T_187 = eq(io.lsu_nonblock_load_inv_tag_r, cam[3].bits.tag) @[el2_dec_decode_ctl.scala 339:79] node _T_188 = and(_T_186, _T_187) @[el2_dec_decode_ctl.scala 339:44] - node _T_189 = eq(cam[3].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:110] - node _T_190 = and(_T_188, _T_189) @[el2_dec_decode_ctl.scala 339:95] - when _T_190 : @[el2_dec_decode_ctl.scala 339:117] - cam_in[3].wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 340:20] - skip @[el2_dec_decode_ctl.scala 339:117] + node _T_189 = eq(cam[3].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:115] + node _T_190 = and(_T_188, _T_189) @[el2_dec_decode_ctl.scala 339:100] + when _T_190 : @[el2_dec_decode_ctl.scala 339:122] + cam_in[3].bits.wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 340:25] + skip @[el2_dec_decode_ctl.scala 339:122] when io.dec_tlu_force_halt : @[el2_dec_decode_ctl.scala 343:32] cam_in[3].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 344:23] skip @[el2_dec_decode_ctl.scala 343:32] - wire _T_191 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 347:70] - _T_191.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 347:70] - _T_191.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 347:70] - _T_191.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70] + wire _T_191 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 347:70] + _T_191.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 347:70] + _T_191.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 347:70] + _T_191.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70] _T_191.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70] - reg _T_192 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}, io.free_clk with : (reset => (reset, _T_191)) @[el2_dec_decode_ctl.scala 347:47] - _T_192.rd <= cam_in[3].rd @[el2_dec_decode_ctl.scala 347:47] - _T_192.tag <= cam_in[3].tag @[el2_dec_decode_ctl.scala 347:47] - _T_192.wb <= cam_in[3].wb @[el2_dec_decode_ctl.scala 347:47] + reg _T_192 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_191)) @[el2_dec_decode_ctl.scala 347:47] + _T_192.bits.rd <= cam_in[3].bits.rd @[el2_dec_decode_ctl.scala 347:47] + _T_192.bits.tag <= cam_in[3].bits.tag @[el2_dec_decode_ctl.scala 347:47] + _T_192.bits.wb <= cam_in[3].bits.wb @[el2_dec_decode_ctl.scala 347:47] _T_192.valid <= cam_in[3].valid @[el2_dec_decode_ctl.scala 347:47] - cam_raw[3].rd <= _T_192.rd @[el2_dec_decode_ctl.scala 347:15] - cam_raw[3].tag <= _T_192.tag @[el2_dec_decode_ctl.scala 347:15] - cam_raw[3].wb <= _T_192.wb @[el2_dec_decode_ctl.scala 347:15] + cam_raw[3].bits.rd <= _T_192.bits.rd @[el2_dec_decode_ctl.scala 347:15] + cam_raw[3].bits.tag <= _T_192.bits.tag @[el2_dec_decode_ctl.scala 347:15] + cam_raw[3].bits.wb <= _T_192.bits.wb @[el2_dec_decode_ctl.scala 347:15] cam_raw[3].valid <= _T_192.valid @[el2_dec_decode_ctl.scala 347:15] - node _T_193 = eq(io.lsu_nonblock_load_data_tag, cam_raw[3].tag) @[el2_dec_decode_ctl.scala 348:46] - node _T_194 = and(_T_193, cam_raw[3].valid) @[el2_dec_decode_ctl.scala 348:66] + node _T_193 = eq(io.lsu_nonblock_load_data_tag, cam_raw[3].bits.tag) @[el2_dec_decode_ctl.scala 348:46] + node _T_194 = and(_T_193, cam_raw[3].valid) @[el2_dec_decode_ctl.scala 348:71] nonblock_load_write[3] <= _T_194 @[el2_dec_decode_ctl.scala 348:28] io.dec_nonblock_load_waddr <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 351:29] - node _T_195 = eq(r_d_in.i0rd, io.dec_nonblock_load_waddr) @[el2_dec_decode_ctl.scala 353:44] - node nonblock_load_cancel = and(_T_195, i0_wen_r) @[el2_dec_decode_ctl.scala 353:76] + node _T_195 = eq(r_d_in.bits.i0rd, io.dec_nonblock_load_waddr) @[el2_dec_decode_ctl.scala 353:49] + node nonblock_load_cancel = and(_T_195, i0_wen_r) @[el2_dec_decode_ctl.scala 353:81] node _T_196 = or(nonblock_load_write[0], nonblock_load_write[1]) @[el2_dec_decode_ctl.scala 354:95] node _T_197 = or(_T_196, nonblock_load_write[2]) @[el2_dec_decode_ctl.scala 354:95] node _T_198 = or(_T_197, nonblock_load_write[3]) @[el2_dec_decode_ctl.scala 354:95] @@ -3401,40 +3400,40 @@ circuit el2_dec : i0_nonblock_load_stall <= i0_nonblock_boundary_stall @[el2_dec_decode_ctl.scala 357:26] node _T_209 = bits(nonblock_load_write[0], 0, 0) @[Bitwise.scala 72:15] node _T_210 = mux(_T_209, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] - node _T_211 = and(_T_210, cam[0].rd) @[el2_dec_decode_ctl.scala 359:88] - node _T_212 = and(io.dec_i0_rs1_en_d, cam[0].valid) @[el2_dec_decode_ctl.scala 359:121] - node _T_213 = eq(cam[0].rd, i0r.rs1) @[el2_dec_decode_ctl.scala 359:149] - node _T_214 = and(_T_212, _T_213) @[el2_dec_decode_ctl.scala 359:136] - node _T_215 = and(io.dec_i0_rs2_en_d, cam[0].valid) @[el2_dec_decode_ctl.scala 359:182] - node _T_216 = eq(cam[0].rd, i0r.rs2) @[el2_dec_decode_ctl.scala 359:210] - node _T_217 = and(_T_215, _T_216) @[el2_dec_decode_ctl.scala 359:197] + node _T_211 = and(_T_210, cam[0].bits.rd) @[el2_dec_decode_ctl.scala 359:88] + node _T_212 = and(io.dec_i0_rs1_en_d, cam[0].valid) @[el2_dec_decode_ctl.scala 359:126] + node _T_213 = eq(cam[0].bits.rd, i0r.rs1) @[el2_dec_decode_ctl.scala 359:159] + node _T_214 = and(_T_212, _T_213) @[el2_dec_decode_ctl.scala 359:141] + node _T_215 = and(io.dec_i0_rs2_en_d, cam[0].valid) @[el2_dec_decode_ctl.scala 359:192] + node _T_216 = eq(cam[0].bits.rd, i0r.rs2) @[el2_dec_decode_ctl.scala 359:225] + node _T_217 = and(_T_215, _T_216) @[el2_dec_decode_ctl.scala 359:207] node _T_218 = bits(nonblock_load_write[1], 0, 0) @[Bitwise.scala 72:15] node _T_219 = mux(_T_218, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] - node _T_220 = and(_T_219, cam[1].rd) @[el2_dec_decode_ctl.scala 359:88] - node _T_221 = and(io.dec_i0_rs1_en_d, cam[1].valid) @[el2_dec_decode_ctl.scala 359:121] - node _T_222 = eq(cam[1].rd, i0r.rs1) @[el2_dec_decode_ctl.scala 359:149] - node _T_223 = and(_T_221, _T_222) @[el2_dec_decode_ctl.scala 359:136] - node _T_224 = and(io.dec_i0_rs2_en_d, cam[1].valid) @[el2_dec_decode_ctl.scala 359:182] - node _T_225 = eq(cam[1].rd, i0r.rs2) @[el2_dec_decode_ctl.scala 359:210] - node _T_226 = and(_T_224, _T_225) @[el2_dec_decode_ctl.scala 359:197] + node _T_220 = and(_T_219, cam[1].bits.rd) @[el2_dec_decode_ctl.scala 359:88] + node _T_221 = and(io.dec_i0_rs1_en_d, cam[1].valid) @[el2_dec_decode_ctl.scala 359:126] + node _T_222 = eq(cam[1].bits.rd, i0r.rs1) @[el2_dec_decode_ctl.scala 359:159] + node _T_223 = and(_T_221, _T_222) @[el2_dec_decode_ctl.scala 359:141] + node _T_224 = and(io.dec_i0_rs2_en_d, cam[1].valid) @[el2_dec_decode_ctl.scala 359:192] + node _T_225 = eq(cam[1].bits.rd, i0r.rs2) @[el2_dec_decode_ctl.scala 359:225] + node _T_226 = and(_T_224, _T_225) @[el2_dec_decode_ctl.scala 359:207] node _T_227 = bits(nonblock_load_write[2], 0, 0) @[Bitwise.scala 72:15] node _T_228 = mux(_T_227, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] - node _T_229 = and(_T_228, cam[2].rd) @[el2_dec_decode_ctl.scala 359:88] - node _T_230 = and(io.dec_i0_rs1_en_d, cam[2].valid) @[el2_dec_decode_ctl.scala 359:121] - node _T_231 = eq(cam[2].rd, i0r.rs1) @[el2_dec_decode_ctl.scala 359:149] - node _T_232 = and(_T_230, _T_231) @[el2_dec_decode_ctl.scala 359:136] - node _T_233 = and(io.dec_i0_rs2_en_d, cam[2].valid) @[el2_dec_decode_ctl.scala 359:182] - node _T_234 = eq(cam[2].rd, i0r.rs2) @[el2_dec_decode_ctl.scala 359:210] - node _T_235 = and(_T_233, _T_234) @[el2_dec_decode_ctl.scala 359:197] + node _T_229 = and(_T_228, cam[2].bits.rd) @[el2_dec_decode_ctl.scala 359:88] + node _T_230 = and(io.dec_i0_rs1_en_d, cam[2].valid) @[el2_dec_decode_ctl.scala 359:126] + node _T_231 = eq(cam[2].bits.rd, i0r.rs1) @[el2_dec_decode_ctl.scala 359:159] + node _T_232 = and(_T_230, _T_231) @[el2_dec_decode_ctl.scala 359:141] + node _T_233 = and(io.dec_i0_rs2_en_d, cam[2].valid) @[el2_dec_decode_ctl.scala 359:192] + node _T_234 = eq(cam[2].bits.rd, i0r.rs2) @[el2_dec_decode_ctl.scala 359:225] + node _T_235 = and(_T_233, _T_234) @[el2_dec_decode_ctl.scala 359:207] node _T_236 = bits(nonblock_load_write[3], 0, 0) @[Bitwise.scala 72:15] node _T_237 = mux(_T_236, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] - node _T_238 = and(_T_237, cam[3].rd) @[el2_dec_decode_ctl.scala 359:88] - node _T_239 = and(io.dec_i0_rs1_en_d, cam[3].valid) @[el2_dec_decode_ctl.scala 359:121] - node _T_240 = eq(cam[3].rd, i0r.rs1) @[el2_dec_decode_ctl.scala 359:149] - node _T_241 = and(_T_239, _T_240) @[el2_dec_decode_ctl.scala 359:136] - node _T_242 = and(io.dec_i0_rs2_en_d, cam[3].valid) @[el2_dec_decode_ctl.scala 359:182] - node _T_243 = eq(cam[3].rd, i0r.rs2) @[el2_dec_decode_ctl.scala 359:210] - node _T_244 = and(_T_242, _T_243) @[el2_dec_decode_ctl.scala 359:197] + node _T_238 = and(_T_237, cam[3].bits.rd) @[el2_dec_decode_ctl.scala 359:88] + node _T_239 = and(io.dec_i0_rs1_en_d, cam[3].valid) @[el2_dec_decode_ctl.scala 359:126] + node _T_240 = eq(cam[3].bits.rd, i0r.rs1) @[el2_dec_decode_ctl.scala 359:159] + node _T_241 = and(_T_239, _T_240) @[el2_dec_decode_ctl.scala 359:141] + node _T_242 = and(io.dec_i0_rs2_en_d, cam[3].valid) @[el2_dec_decode_ctl.scala 359:192] + node _T_243 = eq(cam[3].bits.rd, i0r.rs2) @[el2_dec_decode_ctl.scala 359:225] + node _T_244 = and(_T_242, _T_243) @[el2_dec_decode_ctl.scala 359:207] node _T_245 = or(_T_211, _T_220) @[el2_dec_decode_ctl.scala 360:69] node _T_246 = or(_T_245, _T_229) @[el2_dec_decode_ctl.scala 360:69] node waddr = or(_T_246, _T_238) @[el2_dec_decode_ctl.scala 360:69] @@ -3687,18 +3686,18 @@ circuit el2_dec : io.dec_csr_wen_unq_d <= _T_350 @[el2_dec_decode_ctl.scala 463:24] node _T_351 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 466:30] io.dec_csr_rdaddr_d <= _T_351 @[el2_dec_decode_ctl.scala 466:24] - io.dec_csr_wraddr_r <= r_d.csrwaddr @[el2_dec_decode_ctl.scala 467:23] - node _T_352 = and(r_d.csrwen, r_d.i0valid) @[el2_dec_decode_ctl.scala 471:34] - node _T_353 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 471:50] - node _T_354 = and(_T_352, _T_353) @[el2_dec_decode_ctl.scala 471:48] + io.dec_csr_wraddr_r <= r_d.bits.csrwaddr @[el2_dec_decode_ctl.scala 467:23] + node _T_352 = and(r_d.bits.csrwen, r_d.valid) @[el2_dec_decode_ctl.scala 471:39] + node _T_353 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 471:53] + node _T_354 = and(_T_352, _T_353) @[el2_dec_decode_ctl.scala 471:51] io.dec_csr_wen_r <= _T_354 @[el2_dec_decode_ctl.scala 471:20] - node _T_355 = eq(r_d.csrwaddr, UInt<10>("h0300")) @[el2_dec_decode_ctl.scala 474:45] - node _T_356 = eq(r_d.csrwaddr, UInt<10>("h0304")) @[el2_dec_decode_ctl.scala 474:75] - node _T_357 = or(_T_355, _T_356) @[el2_dec_decode_ctl.scala 474:59] - node _T_358 = and(_T_357, r_d.csrwen) @[el2_dec_decode_ctl.scala 474:90] - node _T_359 = and(_T_358, r_d.i0valid) @[el2_dec_decode_ctl.scala 474:103] - node _T_360 = eq(io.dec_tlu_i0_kill_writeb_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 474:119] - node _T_361 = and(_T_359, _T_360) @[el2_dec_decode_ctl.scala 474:117] + node _T_355 = eq(r_d.bits.csrwaddr, UInt<10>("h0300")) @[el2_dec_decode_ctl.scala 474:50] + node _T_356 = eq(r_d.bits.csrwaddr, UInt<10>("h0304")) @[el2_dec_decode_ctl.scala 474:85] + node _T_357 = or(_T_355, _T_356) @[el2_dec_decode_ctl.scala 474:64] + node _T_358 = and(_T_357, r_d.bits.csrwen) @[el2_dec_decode_ctl.scala 474:100] + node _T_359 = and(_T_358, r_d.valid) @[el2_dec_decode_ctl.scala 474:118] + node _T_360 = eq(io.dec_tlu_i0_kill_writeb_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 474:132] + node _T_361 = and(_T_359, _T_360) @[el2_dec_decode_ctl.scala 474:130] io.dec_csr_stall_int_ff <= _T_361 @[el2_dec_decode_ctl.scala 474:27] reg csr_read_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 476:52] csr_read_x <= csr_read @[el2_dec_decode_ctl.scala 476:52] @@ -3845,11 +3844,11 @@ circuit el2_dec : reg _T_429 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_429 <= write_csr_data_in @[el2_lib.scala 514:16] write_csr_data <= _T_429 @[el2_dec_decode_ctl.scala 508:18] - node _T_430 = bits(r_d.csrwonly, 0, 0) @[el2_dec_decode_ctl.scala 514:44] + node _T_430 = bits(r_d.bits.csrwonly, 0, 0) @[el2_dec_decode_ctl.scala 514:49] node _T_431 = mux(_T_430, i0_result_corr_r, write_csr_data) @[el2_dec_decode_ctl.scala 514:30] io.dec_csr_wrdata_r <= _T_431 @[el2_dec_decode_ctl.scala 514:24] - node _T_432 = or(x_d.csrwonly, r_d.csrwonly) @[el2_dec_decode_ctl.scala 516:38] - node prior_csr_write = or(_T_432, wbd.csrwonly) @[el2_dec_decode_ctl.scala 516:53] + node _T_432 = or(x_d.bits.csrwonly, r_d.bits.csrwonly) @[el2_dec_decode_ctl.scala 516:43] + node prior_csr_write = or(_T_432, wbd.bits.csrwonly) @[el2_dec_decode_ctl.scala 516:63] node _T_433 = bits(io.dbg_cmd_wrdata, 0, 0) @[el2_dec_decode_ctl.scala 518:67] node debug_fence_i = and(io.dec_debug_fence_d, _T_433) @[el2_dec_decode_ctl.scala 518:48] node _T_434 = bits(io.dbg_cmd_wrdata, 1, 1) @[el2_dec_decode_ctl.scala 519:67] @@ -3969,8 +3968,8 @@ circuit el2_dec : io.dec_pmu_postsync_stall <= _T_500 @[el2_dec_decode_ctl.scala 559:29] node _T_501 = bits(presync_stall, 0, 0) @[el2_dec_decode_ctl.scala 560:46] io.dec_pmu_presync_stall <= _T_501 @[el2_dec_decode_ctl.scala 560:29] - node prior_inflight = or(x_d.i0valid, r_d.i0valid) @[el2_dec_decode_ctl.scala 564:41] - node prior_inflight_eff = mux(i0_dp.div, x_d.i0valid, prior_inflight) @[el2_dec_decode_ctl.scala 565:31] + node prior_inflight = or(x_d.valid, r_d.valid) @[el2_dec_decode_ctl.scala 564:41] + node prior_inflight_eff = mux(i0_dp.div, x_d.valid, prior_inflight) @[el2_dec_decode_ctl.scala 565:31] node _T_502 = and(i0_presync, prior_inflight_eff) @[el2_dec_decode_ctl.scala 567:37] presync_stall <= _T_502 @[el2_dec_decode_ctl.scala 567:22] reg _T_503 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 568:53] @@ -3979,7 +3978,7 @@ circuit el2_dec : node _T_504 = eq(i0_legal, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 570:56] node _T_505 = or(i0_postsync, _T_504) @[el2_dec_decode_ctl.scala 570:54] node _T_506 = and(io.dec_i0_decode_d, _T_505) @[el2_dec_decode_ctl.scala 570:39] - node _T_507 = and(postsync_stall, x_d.i0valid) @[el2_dec_decode_ctl.scala 570:88] + node _T_507 = and(postsync_stall, x_d.valid) @[el2_dec_decode_ctl.scala 570:88] node _T_508 = or(_T_506, _T_507) @[el2_dec_decode_ctl.scala 570:69] ps_stall_in <= _T_508 @[el2_dec_decode_ctl.scala 570:15] node _T_509 = and(i0_exulegal_decode_d, i0_dp.alu) @[el2_dec_decode_ctl.scala 572:50] @@ -3990,8 +3989,8 @@ circuit el2_dec : mul_decode_d <= _T_511 @[el2_dec_decode_ctl.scala 575:16] node _T_512 = and(i0_exulegal_decode_d, i0_dp.div) @[el2_dec_decode_ctl.scala 576:40] div_decode_d <= _T_512 @[el2_dec_decode_ctl.scala 576:16] - node _T_513 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 578:47] - node _T_514 = and(r_d.i0valid, _T_513) @[el2_dec_decode_ctl.scala 578:45] + node _T_513 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 578:45] + node _T_514 = and(r_d.valid, _T_513) @[el2_dec_decode_ctl.scala 578:43] io.dec_tlu_i0_valid_r <= _T_514 @[el2_dec_decode_ctl.scala 578:29] d_t.legal <= i0_legal_decode_d @[el2_dec_decode_ctl.scala 581:26] node _T_515 = and(i0_icaf_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 582:40] @@ -4128,7 +4127,7 @@ circuit el2_dec : r_t_in.icaf_f1 <= r_t.icaf_f1 @[el2_dec_decode_ctl.scala 605:10] r_t_in.icaf <= r_t.icaf @[el2_dec_decode_ctl.scala 605:10] r_t_in.legal <= r_t.legal @[el2_dec_decode_ctl.scala 605:10] - node _T_536 = or(r_d.i0load, r_d.i0store) @[el2_dec_decode_ctl.scala 607:56] + node _T_536 = or(r_d.bits.i0load, r_d.bits.i0store) @[el2_dec_decode_ctl.scala 607:61] wire _T_537 : UInt<1>[4] @[el2_lib.scala 162:48] _T_537[0] <= _T_536 @[el2_lib.scala 162:48] _T_537[1] <= _T_536 @[el2_lib.scala 162:48] @@ -4137,8 +4136,8 @@ circuit el2_dec : node _T_538 = cat(_T_537[0], _T_537[1]) @[Cat.scala 29:58] node _T_539 = cat(_T_538, _T_537[2]) @[Cat.scala 29:58] node _T_540 = cat(_T_539, _T_537[3]) @[Cat.scala 29:58] - node _T_541 = and(_T_540, lsu_trigger_match_r) @[el2_dec_decode_ctl.scala 607:72] - node _T_542 = or(_T_541, r_t.i0trigger) @[el2_dec_decode_ctl.scala 607:95] + node _T_541 = and(_T_540, lsu_trigger_match_r) @[el2_dec_decode_ctl.scala 607:82] + node _T_542 = or(_T_541, r_t.i0trigger) @[el2_dec_decode_ctl.scala 607:105] r_t_in.i0trigger <= _T_542 @[el2_dec_decode_ctl.scala 607:33] r_t_in.pmu_lsu_misaligned <= lsu_pmu_misaligned_r @[el2_dec_decode_ctl.scala 608:33] node _T_543 = bits(io.dec_tlu_flush_lower_wb, 0, 0) @[el2_dec_decode_ctl.scala 610:35] @@ -4175,7 +4174,7 @@ circuit el2_dec : io.dec_tlu_packet_r.icaf_f1 <= r_t_in.icaf_f1 @[el2_dec_decode_ctl.scala 612:39] io.dec_tlu_packet_r.icaf <= r_t_in.icaf @[el2_dec_decode_ctl.scala 612:39] io.dec_tlu_packet_r.legal <= r_t_in.legal @[el2_dec_decode_ctl.scala 612:39] - node _T_545 = and(r_d.i0div, r_d.i0valid) @[el2_dec_decode_ctl.scala 613:53] + node _T_545 = and(r_d.bits.i0div, r_d.valid) @[el2_dec_decode_ctl.scala 613:58] io.dec_tlu_packet_r.pmu_divide <= _T_545 @[el2_dec_decode_ctl.scala 613:39] reg _T_546 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 616:52] _T_546 <= io.exu_flush_final @[el2_dec_decode_ctl.scala 616:52] @@ -4495,22 +4494,22 @@ circuit el2_dec : io.dec_data_en <= _T_720 @[el2_dec_decode_ctl.scala 662:27] node _T_721 = cat(i0_x_ctl_en, i0_r_ctl_en) @[Cat.scala 29:58] io.dec_ctl_en <= _T_721 @[el2_dec_decode_ctl.scala 663:27] - d_d.i0rd <= i0r.rd @[el2_dec_decode_ctl.scala 665:29] - node _T_722 = and(i0_rd_en_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 666:45] - d_d.i0v <= _T_722 @[el2_dec_decode_ctl.scala 666:29] - d_d.i0valid <= io.dec_i0_decode_d @[el2_dec_decode_ctl.scala 667:29] - node _T_723 = and(i0_dp.load, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 669:45] - d_d.i0load <= _T_723 @[el2_dec_decode_ctl.scala 669:29] - node _T_724 = and(i0_dp.store, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 670:45] - d_d.i0store <= _T_724 @[el2_dec_decode_ctl.scala 670:29] - node _T_725 = and(i0_dp.div, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 671:45] - d_d.i0div <= _T_725 @[el2_dec_decode_ctl.scala 671:29] - node _T_726 = and(io.dec_csr_wen_unq_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 673:56] - d_d.csrwen <= _T_726 @[el2_dec_decode_ctl.scala 673:29] - node _T_727 = and(i0_csr_write_only_d, io.dec_i0_decode_d) @[el2_dec_decode_ctl.scala 674:53] - d_d.csrwonly <= _T_727 @[el2_dec_decode_ctl.scala 674:29] - node _T_728 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 675:35] - d_d.csrwaddr <= _T_728 @[el2_dec_decode_ctl.scala 675:29] + d_d.bits.i0rd <= i0r.rd @[el2_dec_decode_ctl.scala 665:34] + node _T_722 = and(i0_rd_en_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 666:50] + d_d.bits.i0v <= _T_722 @[el2_dec_decode_ctl.scala 666:34] + d_d.valid <= io.dec_i0_decode_d @[el2_dec_decode_ctl.scala 667:27] + node _T_723 = and(i0_dp.load, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 669:50] + d_d.bits.i0load <= _T_723 @[el2_dec_decode_ctl.scala 669:34] + node _T_724 = and(i0_dp.store, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 670:50] + d_d.bits.i0store <= _T_724 @[el2_dec_decode_ctl.scala 670:34] + node _T_725 = and(i0_dp.div, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 671:50] + d_d.bits.i0div <= _T_725 @[el2_dec_decode_ctl.scala 671:34] + node _T_726 = and(io.dec_csr_wen_unq_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 673:61] + d_d.bits.csrwen <= _T_726 @[el2_dec_decode_ctl.scala 673:34] + node _T_727 = and(i0_csr_write_only_d, io.dec_i0_decode_d) @[el2_dec_decode_ctl.scala 674:58] + d_d.bits.csrwonly <= _T_727 @[el2_dec_decode_ctl.scala 674:34] + node _T_728 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 675:40] + d_d.bits.csrwaddr <= _T_728 @[el2_dec_decode_ctl.scala 675:34] node _T_729 = bits(i0_x_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 677:34] inst rvclkhdr_7 of rvclkhdr_7 @[el2_lib.scala 518:23] rvclkhdr_7.clock <= clock @@ -4518,55 +4517,55 @@ circuit el2_dec : rvclkhdr_7.io.clk <= clock @[el2_lib.scala 520:18] rvclkhdr_7.io.en <= _T_729 @[el2_lib.scala 521:17] rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24] - wire _T_730 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_lib.scala 524:33] - _T_730.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 524:33] - _T_730.csrwonly <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_730.csrwen <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_730.i0valid <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_730.i0v <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_730.i0div <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_730.i0store <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_730.i0load <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_730.i0rd <= UInt<5>("h00") @[el2_lib.scala 524:33] - reg _T_731 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}, rvclkhdr_7.io.l1clk with : (reset => (reset, _T_730)) @[el2_lib.scala 524:16] - _T_731.csrwaddr <= d_d.csrwaddr @[el2_lib.scala 524:16] - _T_731.csrwonly <= d_d.csrwonly @[el2_lib.scala 524:16] - _T_731.csrwen <= d_d.csrwen @[el2_lib.scala 524:16] - _T_731.i0valid <= d_d.i0valid @[el2_lib.scala 524:16] - _T_731.i0v <= d_d.i0v @[el2_lib.scala 524:16] - _T_731.i0div <= d_d.i0div @[el2_lib.scala 524:16] - _T_731.i0store <= d_d.i0store @[el2_lib.scala 524:16] - _T_731.i0load <= d_d.i0load @[el2_lib.scala 524:16] - _T_731.i0rd <= d_d.i0rd @[el2_lib.scala 524:16] - x_d.csrwaddr <= _T_731.csrwaddr @[el2_dec_decode_ctl.scala 677:7] - x_d.csrwonly <= _T_731.csrwonly @[el2_dec_decode_ctl.scala 677:7] - x_d.csrwen <= _T_731.csrwen @[el2_dec_decode_ctl.scala 677:7] - x_d.i0valid <= _T_731.i0valid @[el2_dec_decode_ctl.scala 677:7] - x_d.i0v <= _T_731.i0v @[el2_dec_decode_ctl.scala 677:7] - x_d.i0div <= _T_731.i0div @[el2_dec_decode_ctl.scala 677:7] - x_d.i0store <= _T_731.i0store @[el2_dec_decode_ctl.scala 677:7] - x_d.i0load <= _T_731.i0load @[el2_dec_decode_ctl.scala 677:7] - x_d.i0rd <= _T_731.i0rd @[el2_dec_decode_ctl.scala 677:7] - wire x_d_in : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 678:20] - x_d_in.csrwaddr <= x_d.csrwaddr @[el2_dec_decode_ctl.scala 679:10] - x_d_in.csrwonly <= x_d.csrwonly @[el2_dec_decode_ctl.scala 679:10] - x_d_in.csrwen <= x_d.csrwen @[el2_dec_decode_ctl.scala 679:10] - x_d_in.i0valid <= x_d.i0valid @[el2_dec_decode_ctl.scala 679:10] - x_d_in.i0v <= x_d.i0v @[el2_dec_decode_ctl.scala 679:10] - x_d_in.i0div <= x_d.i0div @[el2_dec_decode_ctl.scala 679:10] - x_d_in.i0store <= x_d.i0store @[el2_dec_decode_ctl.scala 679:10] - x_d_in.i0load <= x_d.i0load @[el2_dec_decode_ctl.scala 679:10] - x_d_in.i0rd <= x_d.i0rd @[el2_dec_decode_ctl.scala 679:10] - node _T_732 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 680:39] - node _T_733 = and(x_d.i0v, _T_732) @[el2_dec_decode_ctl.scala 680:37] - node _T_734 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 680:68] - node _T_735 = and(_T_733, _T_734) @[el2_dec_decode_ctl.scala 680:66] - x_d_in.i0v <= _T_735 @[el2_dec_decode_ctl.scala 680:22] - node _T_736 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 681:39] - node _T_737 = and(x_d.i0valid, _T_736) @[el2_dec_decode_ctl.scala 681:37] - node _T_738 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 681:68] - node _T_739 = and(_T_737, _T_738) @[el2_dec_decode_ctl.scala 681:66] - x_d_in.i0valid <= _T_739 @[el2_dec_decode_ctl.scala 681:22] + wire _T_730 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_lib.scala 524:33] + _T_730.bits.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 524:33] + _T_730.bits.csrwonly <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_730.bits.csrwen <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_730.bits.i0v <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_730.bits.i0div <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_730.bits.i0store <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_730.bits.i0load <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_730.bits.i0rd <= UInt<5>("h00") @[el2_lib.scala 524:33] + _T_730.valid <= UInt<1>("h00") @[el2_lib.scala 524:33] + reg _T_731 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, rvclkhdr_7.io.l1clk with : (reset => (reset, _T_730)) @[el2_lib.scala 524:16] + _T_731.bits.csrwaddr <= d_d.bits.csrwaddr @[el2_lib.scala 524:16] + _T_731.bits.csrwonly <= d_d.bits.csrwonly @[el2_lib.scala 524:16] + _T_731.bits.csrwen <= d_d.bits.csrwen @[el2_lib.scala 524:16] + _T_731.bits.i0v <= d_d.bits.i0v @[el2_lib.scala 524:16] + _T_731.bits.i0div <= d_d.bits.i0div @[el2_lib.scala 524:16] + _T_731.bits.i0store <= d_d.bits.i0store @[el2_lib.scala 524:16] + _T_731.bits.i0load <= d_d.bits.i0load @[el2_lib.scala 524:16] + _T_731.bits.i0rd <= d_d.bits.i0rd @[el2_lib.scala 524:16] + _T_731.valid <= d_d.valid @[el2_lib.scala 524:16] + x_d.bits.csrwaddr <= _T_731.bits.csrwaddr @[el2_dec_decode_ctl.scala 677:7] + x_d.bits.csrwonly <= _T_731.bits.csrwonly @[el2_dec_decode_ctl.scala 677:7] + x_d.bits.csrwen <= _T_731.bits.csrwen @[el2_dec_decode_ctl.scala 677:7] + x_d.bits.i0v <= _T_731.bits.i0v @[el2_dec_decode_ctl.scala 677:7] + x_d.bits.i0div <= _T_731.bits.i0div @[el2_dec_decode_ctl.scala 677:7] + x_d.bits.i0store <= _T_731.bits.i0store @[el2_dec_decode_ctl.scala 677:7] + x_d.bits.i0load <= _T_731.bits.i0load @[el2_dec_decode_ctl.scala 677:7] + x_d.bits.i0rd <= _T_731.bits.i0rd @[el2_dec_decode_ctl.scala 677:7] + x_d.valid <= _T_731.valid @[el2_dec_decode_ctl.scala 677:7] + wire x_d_in : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_dec_decode_ctl.scala 678:20] + x_d_in.bits.csrwaddr <= x_d.bits.csrwaddr @[el2_dec_decode_ctl.scala 679:10] + x_d_in.bits.csrwonly <= x_d.bits.csrwonly @[el2_dec_decode_ctl.scala 679:10] + x_d_in.bits.csrwen <= x_d.bits.csrwen @[el2_dec_decode_ctl.scala 679:10] + x_d_in.bits.i0v <= x_d.bits.i0v @[el2_dec_decode_ctl.scala 679:10] + x_d_in.bits.i0div <= x_d.bits.i0div @[el2_dec_decode_ctl.scala 679:10] + x_d_in.bits.i0store <= x_d.bits.i0store @[el2_dec_decode_ctl.scala 679:10] + x_d_in.bits.i0load <= x_d.bits.i0load @[el2_dec_decode_ctl.scala 679:10] + x_d_in.bits.i0rd <= x_d.bits.i0rd @[el2_dec_decode_ctl.scala 679:10] + x_d_in.valid <= x_d.valid @[el2_dec_decode_ctl.scala 679:10] + node _T_732 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 680:49] + node _T_733 = and(x_d.bits.i0v, _T_732) @[el2_dec_decode_ctl.scala 680:47] + node _T_734 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 680:78] + node _T_735 = and(_T_733, _T_734) @[el2_dec_decode_ctl.scala 680:76] + x_d_in.bits.i0v <= _T_735 @[el2_dec_decode_ctl.scala 680:27] + node _T_736 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 681:35] + node _T_737 = and(x_d.valid, _T_736) @[el2_dec_decode_ctl.scala 681:33] + node _T_738 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 681:64] + node _T_739 = and(_T_737, _T_738) @[el2_dec_decode_ctl.scala 681:62] + x_d_in.valid <= _T_739 @[el2_dec_decode_ctl.scala 681:20] node _T_740 = bits(i0_r_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 683:36] inst rvclkhdr_8 of rvclkhdr_8 @[el2_lib.scala 518:23] rvclkhdr_8.clock <= clock @@ -4574,57 +4573,57 @@ circuit el2_dec : rvclkhdr_8.io.clk <= clock @[el2_lib.scala 520:18] rvclkhdr_8.io.en <= _T_740 @[el2_lib.scala 521:17] rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24] - wire _T_741 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_lib.scala 524:33] - _T_741.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 524:33] - _T_741.csrwonly <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_741.csrwen <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_741.i0valid <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_741.i0v <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_741.i0div <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_741.i0store <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_741.i0load <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_741.i0rd <= UInt<5>("h00") @[el2_lib.scala 524:33] - reg _T_742 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}, rvclkhdr_8.io.l1clk with : (reset => (reset, _T_741)) @[el2_lib.scala 524:16] - _T_742.csrwaddr <= x_d_in.csrwaddr @[el2_lib.scala 524:16] - _T_742.csrwonly <= x_d_in.csrwonly @[el2_lib.scala 524:16] - _T_742.csrwen <= x_d_in.csrwen @[el2_lib.scala 524:16] - _T_742.i0valid <= x_d_in.i0valid @[el2_lib.scala 524:16] - _T_742.i0v <= x_d_in.i0v @[el2_lib.scala 524:16] - _T_742.i0div <= x_d_in.i0div @[el2_lib.scala 524:16] - _T_742.i0store <= x_d_in.i0store @[el2_lib.scala 524:16] - _T_742.i0load <= x_d_in.i0load @[el2_lib.scala 524:16] - _T_742.i0rd <= x_d_in.i0rd @[el2_lib.scala 524:16] - r_d.csrwaddr <= _T_742.csrwaddr @[el2_dec_decode_ctl.scala 683:7] - r_d.csrwonly <= _T_742.csrwonly @[el2_dec_decode_ctl.scala 683:7] - r_d.csrwen <= _T_742.csrwen @[el2_dec_decode_ctl.scala 683:7] - r_d.i0valid <= _T_742.i0valid @[el2_dec_decode_ctl.scala 683:7] - r_d.i0v <= _T_742.i0v @[el2_dec_decode_ctl.scala 683:7] - r_d.i0div <= _T_742.i0div @[el2_dec_decode_ctl.scala 683:7] - r_d.i0store <= _T_742.i0store @[el2_dec_decode_ctl.scala 683:7] - r_d.i0load <= _T_742.i0load @[el2_dec_decode_ctl.scala 683:7] - r_d.i0rd <= _T_742.i0rd @[el2_dec_decode_ctl.scala 683:7] - r_d_in.csrwaddr <= r_d.csrwaddr @[el2_dec_decode_ctl.scala 684:10] - r_d_in.csrwonly <= r_d.csrwonly @[el2_dec_decode_ctl.scala 684:10] - r_d_in.csrwen <= r_d.csrwen @[el2_dec_decode_ctl.scala 684:10] - r_d_in.i0valid <= r_d.i0valid @[el2_dec_decode_ctl.scala 684:10] - r_d_in.i0v <= r_d.i0v @[el2_dec_decode_ctl.scala 684:10] - r_d_in.i0div <= r_d.i0div @[el2_dec_decode_ctl.scala 684:10] - r_d_in.i0store <= r_d.i0store @[el2_dec_decode_ctl.scala 684:10] - r_d_in.i0load <= r_d.i0load @[el2_dec_decode_ctl.scala 684:10] - r_d_in.i0rd <= r_d.i0rd @[el2_dec_decode_ctl.scala 684:10] - r_d_in.i0rd <= r_d.i0rd @[el2_dec_decode_ctl.scala 685:17] - node _T_743 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 687:41] - node _T_744 = and(r_d.i0v, _T_743) @[el2_dec_decode_ctl.scala 687:39] - r_d_in.i0v <= _T_744 @[el2_dec_decode_ctl.scala 687:22] - node _T_745 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 688:41] - node _T_746 = and(r_d.i0valid, _T_745) @[el2_dec_decode_ctl.scala 688:39] - r_d_in.i0valid <= _T_746 @[el2_dec_decode_ctl.scala 688:22] - node _T_747 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 689:41] - node _T_748 = and(r_d.i0load, _T_747) @[el2_dec_decode_ctl.scala 689:39] - r_d_in.i0load <= _T_748 @[el2_dec_decode_ctl.scala 689:22] - node _T_749 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 690:41] - node _T_750 = and(r_d.i0store, _T_749) @[el2_dec_decode_ctl.scala 690:39] - r_d_in.i0store <= _T_750 @[el2_dec_decode_ctl.scala 690:22] + wire _T_741 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_lib.scala 524:33] + _T_741.bits.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 524:33] + _T_741.bits.csrwonly <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_741.bits.csrwen <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_741.bits.i0v <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_741.bits.i0div <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_741.bits.i0store <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_741.bits.i0load <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_741.bits.i0rd <= UInt<5>("h00") @[el2_lib.scala 524:33] + _T_741.valid <= UInt<1>("h00") @[el2_lib.scala 524:33] + reg _T_742 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, rvclkhdr_8.io.l1clk with : (reset => (reset, _T_741)) @[el2_lib.scala 524:16] + _T_742.bits.csrwaddr <= x_d_in.bits.csrwaddr @[el2_lib.scala 524:16] + _T_742.bits.csrwonly <= x_d_in.bits.csrwonly @[el2_lib.scala 524:16] + _T_742.bits.csrwen <= x_d_in.bits.csrwen @[el2_lib.scala 524:16] + _T_742.bits.i0v <= x_d_in.bits.i0v @[el2_lib.scala 524:16] + _T_742.bits.i0div <= x_d_in.bits.i0div @[el2_lib.scala 524:16] + _T_742.bits.i0store <= x_d_in.bits.i0store @[el2_lib.scala 524:16] + _T_742.bits.i0load <= x_d_in.bits.i0load @[el2_lib.scala 524:16] + _T_742.bits.i0rd <= x_d_in.bits.i0rd @[el2_lib.scala 524:16] + _T_742.valid <= x_d_in.valid @[el2_lib.scala 524:16] + r_d.bits.csrwaddr <= _T_742.bits.csrwaddr @[el2_dec_decode_ctl.scala 683:7] + r_d.bits.csrwonly <= _T_742.bits.csrwonly @[el2_dec_decode_ctl.scala 683:7] + r_d.bits.csrwen <= _T_742.bits.csrwen @[el2_dec_decode_ctl.scala 683:7] + r_d.bits.i0v <= _T_742.bits.i0v @[el2_dec_decode_ctl.scala 683:7] + r_d.bits.i0div <= _T_742.bits.i0div @[el2_dec_decode_ctl.scala 683:7] + r_d.bits.i0store <= _T_742.bits.i0store @[el2_dec_decode_ctl.scala 683:7] + r_d.bits.i0load <= _T_742.bits.i0load @[el2_dec_decode_ctl.scala 683:7] + r_d.bits.i0rd <= _T_742.bits.i0rd @[el2_dec_decode_ctl.scala 683:7] + r_d.valid <= _T_742.valid @[el2_dec_decode_ctl.scala 683:7] + r_d_in.bits.csrwaddr <= r_d.bits.csrwaddr @[el2_dec_decode_ctl.scala 684:10] + r_d_in.bits.csrwonly <= r_d.bits.csrwonly @[el2_dec_decode_ctl.scala 684:10] + r_d_in.bits.csrwen <= r_d.bits.csrwen @[el2_dec_decode_ctl.scala 684:10] + r_d_in.bits.i0v <= r_d.bits.i0v @[el2_dec_decode_ctl.scala 684:10] + r_d_in.bits.i0div <= r_d.bits.i0div @[el2_dec_decode_ctl.scala 684:10] + r_d_in.bits.i0store <= r_d.bits.i0store @[el2_dec_decode_ctl.scala 684:10] + r_d_in.bits.i0load <= r_d.bits.i0load @[el2_dec_decode_ctl.scala 684:10] + r_d_in.bits.i0rd <= r_d.bits.i0rd @[el2_dec_decode_ctl.scala 684:10] + r_d_in.valid <= r_d.valid @[el2_dec_decode_ctl.scala 684:10] + r_d_in.bits.i0rd <= r_d.bits.i0rd @[el2_dec_decode_ctl.scala 685:22] + node _T_743 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 687:51] + node _T_744 = and(r_d.bits.i0v, _T_743) @[el2_dec_decode_ctl.scala 687:49] + r_d_in.bits.i0v <= _T_744 @[el2_dec_decode_ctl.scala 687:27] + node _T_745 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 688:37] + node _T_746 = and(r_d.valid, _T_745) @[el2_dec_decode_ctl.scala 688:35] + r_d_in.valid <= _T_746 @[el2_dec_decode_ctl.scala 688:20] + node _T_747 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 689:51] + node _T_748 = and(r_d.bits.i0load, _T_747) @[el2_dec_decode_ctl.scala 689:49] + r_d_in.bits.i0load <= _T_748 @[el2_dec_decode_ctl.scala 689:27] + node _T_749 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 690:51] + node _T_750 = and(r_d.bits.i0store, _T_749) @[el2_dec_decode_ctl.scala 690:49] + r_d_in.bits.i0store <= _T_750 @[el2_dec_decode_ctl.scala 690:27] node _T_751 = bits(i0_wb_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 692:37] inst rvclkhdr_9 of rvclkhdr_9 @[el2_lib.scala 518:23] rvclkhdr_9.clock <= clock @@ -4632,43 +4631,43 @@ circuit el2_dec : rvclkhdr_9.io.clk <= clock @[el2_lib.scala 520:18] rvclkhdr_9.io.en <= _T_751 @[el2_lib.scala 521:17] rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24] - wire _T_752 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_lib.scala 524:33] - _T_752.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 524:33] - _T_752.csrwonly <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_752.csrwen <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_752.i0valid <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_752.i0v <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_752.i0div <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_752.i0store <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_752.i0load <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_752.i0rd <= UInt<5>("h00") @[el2_lib.scala 524:33] - reg _T_753 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}, rvclkhdr_9.io.l1clk with : (reset => (reset, _T_752)) @[el2_lib.scala 524:16] - _T_753.csrwaddr <= r_d_in.csrwaddr @[el2_lib.scala 524:16] - _T_753.csrwonly <= r_d_in.csrwonly @[el2_lib.scala 524:16] - _T_753.csrwen <= r_d_in.csrwen @[el2_lib.scala 524:16] - _T_753.i0valid <= r_d_in.i0valid @[el2_lib.scala 524:16] - _T_753.i0v <= r_d_in.i0v @[el2_lib.scala 524:16] - _T_753.i0div <= r_d_in.i0div @[el2_lib.scala 524:16] - _T_753.i0store <= r_d_in.i0store @[el2_lib.scala 524:16] - _T_753.i0load <= r_d_in.i0load @[el2_lib.scala 524:16] - _T_753.i0rd <= r_d_in.i0rd @[el2_lib.scala 524:16] - wbd.csrwaddr <= _T_753.csrwaddr @[el2_dec_decode_ctl.scala 692:7] - wbd.csrwonly <= _T_753.csrwonly @[el2_dec_decode_ctl.scala 692:7] - wbd.csrwen <= _T_753.csrwen @[el2_dec_decode_ctl.scala 692:7] - wbd.i0valid <= _T_753.i0valid @[el2_dec_decode_ctl.scala 692:7] - wbd.i0v <= _T_753.i0v @[el2_dec_decode_ctl.scala 692:7] - wbd.i0div <= _T_753.i0div @[el2_dec_decode_ctl.scala 692:7] - wbd.i0store <= _T_753.i0store @[el2_dec_decode_ctl.scala 692:7] - wbd.i0load <= _T_753.i0load @[el2_dec_decode_ctl.scala 692:7] - wbd.i0rd <= _T_753.i0rd @[el2_dec_decode_ctl.scala 692:7] - io.dec_i0_waddr_r <= r_d_in.i0rd @[el2_dec_decode_ctl.scala 694:27] - node _T_754 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 695:42] - node _T_755 = and(r_d_in.i0v, _T_754) @[el2_dec_decode_ctl.scala 695:40] + wire _T_752 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_lib.scala 524:33] + _T_752.bits.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 524:33] + _T_752.bits.csrwonly <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_752.bits.csrwen <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_752.bits.i0v <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_752.bits.i0div <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_752.bits.i0store <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_752.bits.i0load <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_752.bits.i0rd <= UInt<5>("h00") @[el2_lib.scala 524:33] + _T_752.valid <= UInt<1>("h00") @[el2_lib.scala 524:33] + reg _T_753 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, rvclkhdr_9.io.l1clk with : (reset => (reset, _T_752)) @[el2_lib.scala 524:16] + _T_753.bits.csrwaddr <= r_d_in.bits.csrwaddr @[el2_lib.scala 524:16] + _T_753.bits.csrwonly <= r_d_in.bits.csrwonly @[el2_lib.scala 524:16] + _T_753.bits.csrwen <= r_d_in.bits.csrwen @[el2_lib.scala 524:16] + _T_753.bits.i0v <= r_d_in.bits.i0v @[el2_lib.scala 524:16] + _T_753.bits.i0div <= r_d_in.bits.i0div @[el2_lib.scala 524:16] + _T_753.bits.i0store <= r_d_in.bits.i0store @[el2_lib.scala 524:16] + _T_753.bits.i0load <= r_d_in.bits.i0load @[el2_lib.scala 524:16] + _T_753.bits.i0rd <= r_d_in.bits.i0rd @[el2_lib.scala 524:16] + _T_753.valid <= r_d_in.valid @[el2_lib.scala 524:16] + wbd.bits.csrwaddr <= _T_753.bits.csrwaddr @[el2_dec_decode_ctl.scala 692:7] + wbd.bits.csrwonly <= _T_753.bits.csrwonly @[el2_dec_decode_ctl.scala 692:7] + wbd.bits.csrwen <= _T_753.bits.csrwen @[el2_dec_decode_ctl.scala 692:7] + wbd.bits.i0v <= _T_753.bits.i0v @[el2_dec_decode_ctl.scala 692:7] + wbd.bits.i0div <= _T_753.bits.i0div @[el2_dec_decode_ctl.scala 692:7] + wbd.bits.i0store <= _T_753.bits.i0store @[el2_dec_decode_ctl.scala 692:7] + wbd.bits.i0load <= _T_753.bits.i0load @[el2_dec_decode_ctl.scala 692:7] + wbd.bits.i0rd <= _T_753.bits.i0rd @[el2_dec_decode_ctl.scala 692:7] + wbd.valid <= _T_753.valid @[el2_dec_decode_ctl.scala 692:7] + io.dec_i0_waddr_r <= r_d_in.bits.i0rd @[el2_dec_decode_ctl.scala 694:27] + node _T_754 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 695:47] + node _T_755 = and(r_d_in.bits.i0v, _T_754) @[el2_dec_decode_ctl.scala 695:45] i0_wen_r <= _T_755 @[el2_dec_decode_ctl.scala 695:25] - node _T_756 = eq(r_d_in.i0div, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 696:49] + node _T_756 = eq(r_d_in.bits.i0div, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 696:49] node _T_757 = and(i0_wen_r, _T_756) @[el2_dec_decode_ctl.scala 696:47] - node _T_758 = eq(i0_load_kill_wen_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 696:65] - node _T_759 = and(_T_757, _T_758) @[el2_dec_decode_ctl.scala 696:63] + node _T_758 = eq(i0_load_kill_wen_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 696:70] + node _T_759 = and(_T_757, _T_758) @[el2_dec_decode_ctl.scala 696:68] io.dec_i0_wen_r <= _T_759 @[el2_dec_decode_ctl.scala 696:32] io.dec_i0_wdata_r <= i0_result_corr_r @[el2_dec_decode_ctl.scala 697:26] node _T_760 = bits(i0_r_data_en, 0, 0) @[el2_dec_decode_ctl.scala 699:57] @@ -4680,13 +4679,13 @@ circuit el2_dec : rvclkhdr_10.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg i0_result_r_raw : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] i0_result_r_raw <= i0_result_x @[el2_lib.scala 514:16] - node _T_761 = and(x_d.i0v, x_d.i0load) @[el2_dec_decode_ctl.scala 705:42] - node _T_762 = bits(_T_761, 0, 0) @[el2_dec_decode_ctl.scala 705:56] + node _T_761 = and(x_d.bits.i0v, x_d.bits.i0load) @[el2_dec_decode_ctl.scala 705:47] + node _T_762 = bits(_T_761, 0, 0) @[el2_dec_decode_ctl.scala 705:66] node _T_763 = mux(_T_762, io.lsu_result_m, io.exu_i0_result_x) @[el2_dec_decode_ctl.scala 705:32] i0_result_x <= _T_763 @[el2_dec_decode_ctl.scala 705:26] i0_result_r <= i0_result_r_raw @[el2_dec_decode_ctl.scala 706:26] - node _T_764 = and(r_d.i0v, r_d.i0load) @[el2_dec_decode_ctl.scala 710:37] - node _T_765 = bits(_T_764, 0, 0) @[el2_dec_decode_ctl.scala 710:51] + node _T_764 = and(r_d.bits.i0v, r_d.bits.i0load) @[el2_dec_decode_ctl.scala 710:42] + node _T_765 = bits(_T_764, 0, 0) @[el2_dec_decode_ctl.scala 710:61] node _T_766 = mux(_T_765, io.lsu_result_corr_r, i0_result_r_raw) @[el2_dec_decode_ctl.scala 710:27] i0_result_corr_r <= _T_766 @[el2_dec_decode_ctl.scala 710:21] node _T_767 = eq(i0_dp.jal, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 711:54] @@ -4755,25 +4754,25 @@ circuit el2_dec : reg _T_798 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_798 <= last_br_immed_d @[el2_lib.scala 514:16] last_br_immed_x <= _T_798 @[el2_dec_decode_ctl.scala 715:19] - node _T_799 = and(x_d.i0div, x_d.i0valid) @[el2_dec_decode_ctl.scala 719:40] - node _T_800 = and(r_d.i0div, r_d.i0valid) @[el2_dec_decode_ctl.scala 719:68] - node div_e1_to_r = or(_T_799, _T_800) @[el2_dec_decode_ctl.scala 719:55] - node _T_801 = and(x_d.i0div, x_d.i0valid) @[el2_dec_decode_ctl.scala 721:43] - node _T_802 = eq(x_d.i0rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 721:69] - node _T_803 = and(_T_801, _T_802) @[el2_dec_decode_ctl.scala 721:57] - node _T_804 = and(x_d.i0div, x_d.i0valid) @[el2_dec_decode_ctl.scala 722:16] - node _T_805 = and(_T_804, io.dec_tlu_flush_lower_r) @[el2_dec_decode_ctl.scala 722:30] - node _T_806 = or(_T_803, _T_805) @[el2_dec_decode_ctl.scala 721:86] - node _T_807 = and(r_d.i0div, r_d.i0valid) @[el2_dec_decode_ctl.scala 723:16] - node _T_808 = and(_T_807, io.dec_tlu_flush_lower_r) @[el2_dec_decode_ctl.scala 723:30] - node _T_809 = and(_T_808, io.dec_tlu_i0_kill_writeb_r) @[el2_dec_decode_ctl.scala 723:57] - node div_flush = or(_T_806, _T_809) @[el2_dec_decode_ctl.scala 722:59] + node _T_799 = and(x_d.bits.i0div, x_d.valid) @[el2_dec_decode_ctl.scala 719:45] + node _T_800 = and(r_d.bits.i0div, r_d.valid) @[el2_dec_decode_ctl.scala 719:76] + node div_e1_to_r = or(_T_799, _T_800) @[el2_dec_decode_ctl.scala 719:58] + node _T_801 = and(x_d.bits.i0div, x_d.valid) @[el2_dec_decode_ctl.scala 721:48] + node _T_802 = eq(x_d.bits.i0rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 721:77] + node _T_803 = and(_T_801, _T_802) @[el2_dec_decode_ctl.scala 721:60] + node _T_804 = and(x_d.bits.i0div, x_d.valid) @[el2_dec_decode_ctl.scala 722:21] + node _T_805 = and(_T_804, io.dec_tlu_flush_lower_r) @[el2_dec_decode_ctl.scala 722:33] + node _T_806 = or(_T_803, _T_805) @[el2_dec_decode_ctl.scala 721:94] + node _T_807 = and(r_d.bits.i0div, r_d.valid) @[el2_dec_decode_ctl.scala 723:21] + node _T_808 = and(_T_807, io.dec_tlu_flush_lower_r) @[el2_dec_decode_ctl.scala 723:33] + node _T_809 = and(_T_808, io.dec_tlu_i0_kill_writeb_r) @[el2_dec_decode_ctl.scala 723:60] + node div_flush = or(_T_806, _T_809) @[el2_dec_decode_ctl.scala 722:62] node _T_810 = and(io.dec_div_active, div_flush) @[el2_dec_decode_ctl.scala 727:51] node _T_811 = eq(div_e1_to_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 728:26] node _T_812 = and(io.dec_div_active, _T_811) @[el2_dec_decode_ctl.scala 728:24] - node _T_813 = eq(r_d.i0rd, io.div_waddr_wb) @[el2_dec_decode_ctl.scala 728:51] + node _T_813 = eq(r_d.bits.i0rd, io.div_waddr_wb) @[el2_dec_decode_ctl.scala 728:56] node _T_814 = and(_T_812, _T_813) @[el2_dec_decode_ctl.scala 728:39] - node _T_815 = and(_T_814, i0_wen_r) @[el2_dec_decode_ctl.scala 728:72] + node _T_815 = and(_T_814, i0_wen_r) @[el2_dec_decode_ctl.scala 728:77] node nonblock_div_cancel = or(_T_810, _T_815) @[el2_dec_decode_ctl.scala 727:65] node _T_816 = bits(nonblock_div_cancel, 0, 0) @[el2_dec_decode_ctl.scala 730:53] io.dec_div_cancel <= _T_816 @[el2_dec_decode_ctl.scala 730:29] @@ -4913,18 +4912,18 @@ circuit el2_dec : node temp_pred_correct_npc_x = cat(_T_874, UInt<1>("h00")) @[Cat.scala 29:58] node _T_875 = bits(temp_pred_correct_npc_x, 31, 1) @[el2_dec_decode_ctl.scala 764:51] io.pred_correct_npc_x <= _T_875 @[el2_dec_decode_ctl.scala 764:25] - node _T_876 = and(io.dec_i0_rs1_en_d, x_d.i0v) @[el2_dec_decode_ctl.scala 768:48] - node _T_877 = eq(x_d.i0rd, i0r.rs1) @[el2_dec_decode_ctl.scala 768:70] - node i0_rs1_depend_i0_x = and(_T_876, _T_877) @[el2_dec_decode_ctl.scala 768:58] - node _T_878 = and(io.dec_i0_rs1_en_d, r_d.i0v) @[el2_dec_decode_ctl.scala 769:48] - node _T_879 = eq(r_d.i0rd, i0r.rs1) @[el2_dec_decode_ctl.scala 769:70] - node i0_rs1_depend_i0_r = and(_T_878, _T_879) @[el2_dec_decode_ctl.scala 769:58] - node _T_880 = and(io.dec_i0_rs2_en_d, x_d.i0v) @[el2_dec_decode_ctl.scala 771:48] - node _T_881 = eq(x_d.i0rd, i0r.rs2) @[el2_dec_decode_ctl.scala 771:70] - node i0_rs2_depend_i0_x = and(_T_880, _T_881) @[el2_dec_decode_ctl.scala 771:58] - node _T_882 = and(io.dec_i0_rs2_en_d, r_d.i0v) @[el2_dec_decode_ctl.scala 772:48] - node _T_883 = eq(r_d.i0rd, i0r.rs2) @[el2_dec_decode_ctl.scala 772:70] - node i0_rs2_depend_i0_r = and(_T_882, _T_883) @[el2_dec_decode_ctl.scala 772:58] + node _T_876 = and(io.dec_i0_rs1_en_d, x_d.bits.i0v) @[el2_dec_decode_ctl.scala 768:48] + node _T_877 = eq(x_d.bits.i0rd, i0r.rs1) @[el2_dec_decode_ctl.scala 768:80] + node i0_rs1_depend_i0_x = and(_T_876, _T_877) @[el2_dec_decode_ctl.scala 768:63] + node _T_878 = and(io.dec_i0_rs1_en_d, r_d.bits.i0v) @[el2_dec_decode_ctl.scala 769:48] + node _T_879 = eq(r_d.bits.i0rd, i0r.rs1) @[el2_dec_decode_ctl.scala 769:80] + node i0_rs1_depend_i0_r = and(_T_878, _T_879) @[el2_dec_decode_ctl.scala 769:63] + node _T_880 = and(io.dec_i0_rs2_en_d, x_d.bits.i0v) @[el2_dec_decode_ctl.scala 771:48] + node _T_881 = eq(x_d.bits.i0rd, i0r.rs2) @[el2_dec_decode_ctl.scala 771:80] + node i0_rs2_depend_i0_x = and(_T_880, _T_881) @[el2_dec_decode_ctl.scala 771:63] + node _T_882 = and(io.dec_i0_rs2_en_d, r_d.bits.i0v) @[el2_dec_decode_ctl.scala 772:48] + node _T_883 = eq(r_d.bits.i0rd, i0r.rs2) @[el2_dec_decode_ctl.scala 772:80] + node i0_rs2_depend_i0_r = and(_T_882, _T_883) @[el2_dec_decode_ctl.scala 772:63] node _T_884 = bits(i0_rs1_depend_i0_x, 0, 0) @[el2_dec_decode_ctl.scala 774:44] node _T_885 = bits(i0_rs1_depend_i0_r, 0, 0) @[el2_dec_decode_ctl.scala 774:81] wire _T_886 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 774:109] @@ -16932,7 +16931,7 @@ circuit el2_dec : module el2_dec : input clock : Clock input reset : AsyncReset - output io : {flip free_clk : Clock, flip active_clk : Clock, flip lsu_fastint_stall_any : UInt<1>, dec_extint_stall : UInt<1>, dec_i0_decode_d : UInt<1>, dec_pause_state_cg : UInt<1>, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, flip exu_pmu_i0_br_misp : UInt<1>, flip exu_pmu_i0_br_ataken : UInt<1>, flip exu_pmu_i0_pc4 : UInt<1>, flip lsu_nonblock_load_valid_m : UInt<1>, flip lsu_nonblock_load_tag_m : UInt<2>, flip lsu_nonblock_load_inv_r : UInt<1>, flip lsu_nonblock_load_inv_tag_r : UInt<2>, flip lsu_nonblock_load_data_valid : UInt<1>, flip lsu_nonblock_load_data_error : UInt<1>, flip lsu_nonblock_load_data_tag : UInt<2>, flip lsu_nonblock_load_data : UInt<32>, flip lsu_pmu_bus_trxn : UInt<1>, flip lsu_pmu_bus_misaligned : UInt<1>, flip lsu_pmu_bus_error : UInt<1>, flip lsu_pmu_bus_busy : UInt<1>, flip lsu_pmu_misaligned_m : UInt<1>, flip lsu_pmu_load_external_m : UInt<1>, flip lsu_pmu_store_external_m : UInt<1>, flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, flip lsu_fir_addr : UInt<31>, flip lsu_fir_error : UInt<2>, flip ifu_pmu_instr_aligned : UInt<1>, flip ifu_pmu_fetch_stall : UInt<1>, flip ifu_pmu_ic_miss : UInt<1>, flip ifu_pmu_ic_hit : UInt<1>, flip ifu_pmu_bus_error : UInt<1>, flip ifu_pmu_bus_busy : UInt<1>, flip ifu_pmu_bus_trxn : UInt<1>, flip ifu_ic_error_start : UInt<1>, flip ifu_iccm_rd_ecc_single_err : UInt<1>, flip lsu_trigger_match_m : UInt<4>, flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>, flip dbg_cmd_wrdata : UInt<2>, flip ifu_i0_icaf : UInt<1>, flip ifu_i0_icaf_type : UInt<2>, flip ifu_i0_icaf_f1 : UInt<1>, flip ifu_i0_dbecc : UInt<1>, flip lsu_idle_any : UInt<1>, flip i0_brp : {valid : UInt<1>, bits : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, flip ifu_i0_bp_index : UInt<8>, flip ifu_i0_bp_fghr : UInt<8>, flip ifu_i0_bp_btag : UInt<5>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, flip lsu_single_ecc_error_incr : UInt<1>, flip lsu_imprecise_error_load_any : UInt<1>, flip lsu_imprecise_error_store_any : UInt<1>, flip lsu_imprecise_error_addr_any : UInt<32>, flip exu_div_result : UInt<32>, flip exu_div_wren : UInt<1>, flip exu_csr_rs1_x : UInt<32>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip iccm_dma_sb_error : UInt<1>, flip exu_flush_final : UInt<1>, flip exu_npc_r : UInt<31>, flip exu_i0_result_x : UInt<32>, flip ifu_i0_valid : UInt<1>, flip ifu_i0_instr : UInt<32>, flip ifu_i0_pc : UInt<31>, flip ifu_i0_pc4 : UInt<1>, flip exu_i0_pc_x : UInt<31>, flip mexintpend : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip pic_claimid : UInt<8>, flip pic_pl : UInt<4>, flip mhwakeup : UInt<1>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meipt : UInt<4>, flip ifu_ic_debug_rd_data : UInt<71>, flip ifu_ic_debug_rd_data_valid : UInt<1>, dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip dbg_halt_req : UInt<1>, flip dbg_resume_req : UInt<1>, flip ifu_miss_state_idle : UInt<1>, dec_tlu_dbg_halted : UInt<1>, dec_tlu_debug_mode : UInt<1>, dec_tlu_resume_ack : UInt<1>, dec_tlu_flush_noredir_r : UInt<1>, dec_tlu_mpc_halted_only : UInt<1>, dec_tlu_flush_leak_one_r : UInt<1>, dec_tlu_flush_err_r : UInt<1>, dec_tlu_meihap : UInt<30>, dec_debug_wdata_rs1_d : UInt<1>, dec_dbg_rddata : UInt<32>, dec_dbg_cmd_done : UInt<1>, dec_dbg_cmd_fail : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], dec_tlu_force_halt : UInt<1>, flip exu_i0_br_hist_r : UInt<2>, flip exu_i0_br_error_r : UInt<1>, flip exu_i0_br_start_error_r : UInt<1>, flip exu_i0_br_valid_r : UInt<1>, flip exu_i0_br_mp_r : UInt<1>, flip exu_i0_br_middle_r : UInt<1>, flip exu_i0_br_way_r : UInt<1>, dec_i0_rs1_en_d : UInt<1>, dec_i0_rs2_en_d : UInt<1>, gpr_i0_rs1_d : UInt<32>, gpr_i0_rs2_d : UInt<32>, dec_i0_immed_d : UInt<32>, dec_i0_br_immed_d : UInt<12>, i0_ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, dec_i0_alu_decode_d : UInt<1>, dec_i0_select_pc_d : UInt<1>, dec_i0_pc_d : UInt<31>, dec_i0_rs1_bypass_en_d : UInt<2>, dec_i0_rs2_bypass_en_d : UInt<2>, dec_i0_rs1_bypass_data_d : UInt<32>, dec_i0_rs2_bypass_data_d : UInt<32>, lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, dec_div_cancel : UInt<1>, dec_lsu_offset_d : UInt<12>, dec_csr_ren_d : UInt<1>, dec_tlu_flush_lower_r : UInt<1>, dec_tlu_flush_path_r : UInt<31>, dec_tlu_i0_kill_writeb_r : UInt<1>, dec_tlu_fence_i_r : UInt<1>, pred_correct_npc_x : UInt<31>, dec_tlu_br0_r_pkt : {valid : UInt<1>, bits : {hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}}, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, i0_predict_fghr_d : UInt<8>, i0_predict_index_d : UInt<8>, i0_predict_btag_d : UInt<5>, dec_lsu_valid_raw_d : UInt<1>, dec_tlu_mrac_ff : UInt<32>, dec_data_en : UInt<2>, dec_ctl_en : UInt<2>, flip ifu_i0_cinst : UInt<16>, rv_trace_pkt : {rv_i_valid_ip : UInt<2>, rv_i_insn_ip : UInt<32>, rv_i_address_ip : UInt<32>, rv_i_exception_ip : UInt<2>, rv_i_ecause_ip : UInt<5>, rv_i_interrupt_ip : UInt<2>, rv_i_tval_ip : UInt<32>}, dec_tlu_external_ldfwd_disable : UInt<1>, dec_tlu_sideeffect_posted_disable : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, dec_tlu_bpred_disable : UInt<1>, dec_tlu_wb_coalescing_disable : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>, dec_tlu_i0_commit_cmt : UInt<1>, flip scan_mode : UInt<1>} + output io : {flip free_clk : Clock, flip active_clk : Clock, flip lsu_fastint_stall_any : UInt<1>, dec_extint_stall : UInt<1>, dec_i0_decode_d : UInt<1>, dec_pause_state_cg : UInt<1>, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, flip exu_pmu_i0_br_misp : UInt<1>, flip exu_pmu_i0_br_ataken : UInt<1>, flip exu_pmu_i0_pc4 : UInt<1>, flip lsu_nonblock_load_valid_m : UInt<1>, flip lsu_nonblock_load_tag_m : UInt<2>, flip lsu_nonblock_load_inv_r : UInt<1>, flip lsu_nonblock_load_inv_tag_r : UInt<2>, flip lsu_nonblock_load_data_valid : UInt<1>, flip lsu_nonblock_load_data_error : UInt<1>, flip lsu_nonblock_load_data_tag : UInt<2>, flip lsu_nonblock_load_data : UInt<32>, flip lsu_pmu_bus_trxn : UInt<1>, flip lsu_pmu_bus_misaligned : UInt<1>, flip lsu_pmu_bus_error : UInt<1>, flip lsu_pmu_bus_busy : UInt<1>, flip lsu_pmu_misaligned_m : UInt<1>, flip lsu_pmu_load_external_m : UInt<1>, flip lsu_pmu_store_external_m : UInt<1>, flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, flip lsu_fir_addr : UInt<31>, flip lsu_fir_error : UInt<2>, flip ifu_pmu_instr_aligned : UInt<1>, flip ifu_pmu_fetch_stall : UInt<1>, flip ifu_pmu_ic_miss : UInt<1>, flip ifu_pmu_ic_hit : UInt<1>, flip ifu_pmu_bus_error : UInt<1>, flip ifu_pmu_bus_busy : UInt<1>, flip ifu_pmu_bus_trxn : UInt<1>, flip ifu_ic_error_start : UInt<1>, flip ifu_iccm_rd_ecc_single_err : UInt<1>, flip lsu_trigger_match_m : UInt<4>, flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>, flip dbg_cmd_wrdata : UInt<2>, flip ifu_i0_icaf : UInt<1>, flip ifu_i0_icaf_type : UInt<2>, flip ifu_i0_icaf_f1 : UInt<1>, flip ifu_i0_dbecc : UInt<1>, flip lsu_idle_any : UInt<1>, flip i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, flip ifu_i0_bp_index : UInt<8>, flip ifu_i0_bp_fghr : UInt<8>, flip ifu_i0_bp_btag : UInt<5>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, flip lsu_single_ecc_error_incr : UInt<1>, flip lsu_imprecise_error_load_any : UInt<1>, flip lsu_imprecise_error_store_any : UInt<1>, flip lsu_imprecise_error_addr_any : UInt<32>, flip exu_div_result : UInt<32>, flip exu_div_wren : UInt<1>, flip exu_csr_rs1_x : UInt<32>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip iccm_dma_sb_error : UInt<1>, flip exu_flush_final : UInt<1>, flip exu_npc_r : UInt<31>, flip exu_i0_result_x : UInt<32>, flip ifu_i0_valid : UInt<1>, flip ifu_i0_instr : UInt<32>, flip ifu_i0_pc : UInt<31>, flip ifu_i0_pc4 : UInt<1>, flip exu_i0_pc_x : UInt<31>, flip mexintpend : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip pic_claimid : UInt<8>, flip pic_pl : UInt<4>, flip mhwakeup : UInt<1>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meipt : UInt<4>, flip ifu_ic_debug_rd_data : UInt<71>, flip ifu_ic_debug_rd_data_valid : UInt<1>, dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip dbg_halt_req : UInt<1>, flip dbg_resume_req : UInt<1>, flip ifu_miss_state_idle : UInt<1>, dec_tlu_dbg_halted : UInt<1>, dec_tlu_debug_mode : UInt<1>, dec_tlu_resume_ack : UInt<1>, dec_tlu_flush_noredir_r : UInt<1>, dec_tlu_mpc_halted_only : UInt<1>, dec_tlu_flush_leak_one_r : UInt<1>, dec_tlu_flush_err_r : UInt<1>, dec_tlu_meihap : UInt<30>, dec_debug_wdata_rs1_d : UInt<1>, dec_dbg_rddata : UInt<32>, dec_dbg_cmd_done : UInt<1>, dec_dbg_cmd_fail : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], dec_tlu_force_halt : UInt<1>, flip exu_i0_br_hist_r : UInt<2>, flip exu_i0_br_error_r : UInt<1>, flip exu_i0_br_start_error_r : UInt<1>, flip exu_i0_br_valid_r : UInt<1>, flip exu_i0_br_mp_r : UInt<1>, flip exu_i0_br_middle_r : UInt<1>, flip exu_i0_br_way_r : UInt<1>, dec_i0_rs1_en_d : UInt<1>, dec_i0_rs2_en_d : UInt<1>, gpr_i0_rs1_d : UInt<32>, gpr_i0_rs2_d : UInt<32>, dec_i0_immed_d : UInt<32>, dec_i0_br_immed_d : UInt<12>, i0_ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, dec_i0_alu_decode_d : UInt<1>, dec_i0_select_pc_d : UInt<1>, dec_i0_pc_d : UInt<31>, dec_i0_rs1_bypass_en_d : UInt<2>, dec_i0_rs2_bypass_en_d : UInt<2>, dec_i0_rs1_bypass_data_d : UInt<32>, dec_i0_rs2_bypass_data_d : UInt<32>, lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, dec_div_cancel : UInt<1>, dec_lsu_offset_d : UInt<12>, dec_csr_ren_d : UInt<1>, dec_tlu_flush_lower_r : UInt<1>, dec_tlu_flush_path_r : UInt<31>, dec_tlu_i0_kill_writeb_r : UInt<1>, dec_tlu_fence_i_r : UInt<1>, pred_correct_npc_x : UInt<31>, dec_tlu_br0_r_pkt : {valid : UInt<1>, bits : {hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}}, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, i0_predict_fghr_d : UInt<8>, i0_predict_index_d : UInt<8>, i0_predict_btag_d : UInt<5>, dec_lsu_valid_raw_d : UInt<1>, dec_tlu_mrac_ff : UInt<32>, dec_data_en : UInt<2>, dec_ctl_en : UInt<2>, flip ifu_i0_cinst : UInt<16>, rv_trace_pkt : {rv_i_valid_ip : UInt<2>, rv_i_insn_ip : UInt<32>, rv_i_address_ip : UInt<32>, rv_i_exception_ip : UInt<2>, rv_i_ecause_ip : UInt<5>, rv_i_interrupt_ip : UInt<2>, rv_i_tval_ip : UInt<32>}, dec_tlu_external_ldfwd_disable : UInt<1>, dec_tlu_sideeffect_posted_disable : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, dec_tlu_bpred_disable : UInt<1>, dec_tlu_wb_coalescing_disable : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>, dec_tlu_i0_commit_cmt : UInt<1>, flip scan_mode : UInt<1>} wire dec_i0_inst_wb1 : UInt<32> dec_i0_inst_wb1 <= UInt<1>("h00") @@ -16976,7 +16975,6 @@ circuit el2_dec : instbuff.io.i0_brp.bits.br_error <= io.i0_brp.bits.br_error @[el2_dec.scala 301:55] instbuff.io.i0_brp.bits.hist <= io.i0_brp.bits.hist @[el2_dec.scala 301:55] instbuff.io.i0_brp.bits.toffset <= io.i0_brp.bits.toffset @[el2_dec.scala 301:55] - instbuff.io.i0_brp.bits.valid <= io.i0_brp.bits.valid @[el2_dec.scala 301:55] instbuff.io.i0_brp.valid <= io.i0_brp.valid @[el2_dec.scala 301:55] instbuff.io.ifu_i0_bp_index <= io.ifu_i0_bp_index @[el2_dec.scala 302:35] instbuff.io.ifu_i0_bp_fghr <= io.ifu_i0_bp_fghr @[el2_dec.scala 303:35] @@ -17051,7 +17049,6 @@ circuit el2_dec : decode.io.dec_i0_brp.bits.br_error <= instbuff.io.dec_i0_brp.bits.br_error @[el2_dec.scala 354:48] decode.io.dec_i0_brp.bits.hist <= instbuff.io.dec_i0_brp.bits.hist @[el2_dec.scala 354:48] decode.io.dec_i0_brp.bits.toffset <= instbuff.io.dec_i0_brp.bits.toffset @[el2_dec.scala 354:48] - decode.io.dec_i0_brp.bits.valid <= instbuff.io.dec_i0_brp.bits.valid @[el2_dec.scala 354:48] decode.io.dec_i0_brp.valid <= instbuff.io.dec_i0_brp.valid @[el2_dec.scala 354:48] decode.io.dec_i0_bp_index <= instbuff.io.dec_i0_bp_index @[el2_dec.scala 355:48] decode.io.dec_i0_bp_fghr <= instbuff.io.dec_i0_bp_fghr @[el2_dec.scala 356:48] diff --git a/el2_dec.v b/el2_dec.v index f93b195c..a20a2246 100644 --- a/el2_dec.v +++ b/el2_dec.v @@ -1328,8 +1328,8 @@ module el2_dec_decode_ctl( wire _T_505 = i0_postsync | _T_504; // @[el2_dec_decode_ctl.scala 570:54] wire _T_506 = io_dec_i0_decode_d & _T_505; // @[el2_dec_decode_ctl.scala 570:39] reg postsync_stall; // @[el2_dec_decode_ctl.scala 568:53] - reg x_d_i0valid; // @[el2_lib.scala 524:16] - wire _T_507 = postsync_stall & x_d_i0valid; // @[el2_dec_decode_ctl.scala 570:88] + reg x_d_valid; // @[el2_lib.scala 524:16] + wire _T_507 = postsync_stall & x_d_valid; // @[el2_dec_decode_ctl.scala 570:88] wire ps_stall_in = _T_506 | _T_507; // @[el2_dec_decode_ctl.scala 570:69] wire _T_12 = ps_stall_in ^ postsync_stall; // @[el2_dec_decode_ctl.scala 217:32] wire _T_13 = _T_11 | _T_12; // @[el2_dec_decode_ctl.scala 216:56] @@ -1425,38 +1425,38 @@ module el2_dec_decode_ctl( wire _T_48 = ~_T_47; // @[el2_dec_decode_ctl.scala 276:26] wire i0_ap_pc2 = ~io_dec_i0_pc4_d; // @[el2_dec_decode_ctl.scala 278:20] wire cam_data_reset = io_lsu_nonblock_load_data_valid | io_lsu_nonblock_load_data_error; // @[el2_dec_decode_ctl.scala 311:63] - reg [2:0] cam_raw_0_tag; // @[el2_dec_decode_ctl.scala 347:47] + reg [2:0] cam_raw_0_bits_tag; // @[el2_dec_decode_ctl.scala 347:47] wire [2:0] _GEN_123 = {{1'd0}, io_lsu_nonblock_load_data_tag}; // @[el2_dec_decode_ctl.scala 322:67] - wire _T_94 = _GEN_123 == cam_raw_0_tag; // @[el2_dec_decode_ctl.scala 322:67] + wire _T_94 = _GEN_123 == cam_raw_0_bits_tag; // @[el2_dec_decode_ctl.scala 322:67] wire _T_95 = cam_data_reset & _T_94; // @[el2_dec_decode_ctl.scala 322:45] reg cam_raw_0_valid; // @[el2_dec_decode_ctl.scala 347:47] - wire cam_data_reset_val_0 = _T_95 & cam_raw_0_valid; // @[el2_dec_decode_ctl.scala 322:83] + wire cam_data_reset_val_0 = _T_95 & cam_raw_0_valid; // @[el2_dec_decode_ctl.scala 322:88] wire cam_0_valid = cam_data_reset_val_0 ? 1'h0 : cam_raw_0_valid; // @[el2_dec_decode_ctl.scala 326:39] wire _T_51 = ~cam_0_valid; // @[el2_dec_decode_ctl.scala 303:78] - reg [2:0] cam_raw_1_tag; // @[el2_dec_decode_ctl.scala 347:47] - wire _T_120 = _GEN_123 == cam_raw_1_tag; // @[el2_dec_decode_ctl.scala 322:67] + reg [2:0] cam_raw_1_bits_tag; // @[el2_dec_decode_ctl.scala 347:47] + wire _T_120 = _GEN_123 == cam_raw_1_bits_tag; // @[el2_dec_decode_ctl.scala 322:67] wire _T_121 = cam_data_reset & _T_120; // @[el2_dec_decode_ctl.scala 322:45] reg cam_raw_1_valid; // @[el2_dec_decode_ctl.scala 347:47] - wire cam_data_reset_val_1 = _T_121 & cam_raw_1_valid; // @[el2_dec_decode_ctl.scala 322:83] + wire cam_data_reset_val_1 = _T_121 & cam_raw_1_valid; // @[el2_dec_decode_ctl.scala 322:88] wire cam_1_valid = cam_data_reset_val_1 ? 1'h0 : cam_raw_1_valid; // @[el2_dec_decode_ctl.scala 326:39] wire _T_54 = ~cam_1_valid; // @[el2_dec_decode_ctl.scala 303:78] wire _T_57 = cam_0_valid & _T_54; // @[el2_dec_decode_ctl.scala 303:126] wire [1:0] _T_59 = {io_lsu_nonblock_load_valid_m, 1'h0}; // @[el2_dec_decode_ctl.scala 303:158] - reg [2:0] cam_raw_2_tag; // @[el2_dec_decode_ctl.scala 347:47] - wire _T_146 = _GEN_123 == cam_raw_2_tag; // @[el2_dec_decode_ctl.scala 322:67] + reg [2:0] cam_raw_2_bits_tag; // @[el2_dec_decode_ctl.scala 347:47] + wire _T_146 = _GEN_123 == cam_raw_2_bits_tag; // @[el2_dec_decode_ctl.scala 322:67] wire _T_147 = cam_data_reset & _T_146; // @[el2_dec_decode_ctl.scala 322:45] reg cam_raw_2_valid; // @[el2_dec_decode_ctl.scala 347:47] - wire cam_data_reset_val_2 = _T_147 & cam_raw_2_valid; // @[el2_dec_decode_ctl.scala 322:83] + wire cam_data_reset_val_2 = _T_147 & cam_raw_2_valid; // @[el2_dec_decode_ctl.scala 322:88] wire cam_2_valid = cam_data_reset_val_2 ? 1'h0 : cam_raw_2_valid; // @[el2_dec_decode_ctl.scala 326:39] wire _T_60 = ~cam_2_valid; // @[el2_dec_decode_ctl.scala 303:78] wire _T_63 = cam_0_valid & cam_1_valid; // @[el2_dec_decode_ctl.scala 303:126] wire _T_66 = _T_63 & _T_60; // @[el2_dec_decode_ctl.scala 303:126] wire [2:0] _T_68 = {io_lsu_nonblock_load_valid_m, 2'h0}; // @[el2_dec_decode_ctl.scala 303:158] - reg [2:0] cam_raw_3_tag; // @[el2_dec_decode_ctl.scala 347:47] - wire _T_172 = _GEN_123 == cam_raw_3_tag; // @[el2_dec_decode_ctl.scala 322:67] + reg [2:0] cam_raw_3_bits_tag; // @[el2_dec_decode_ctl.scala 347:47] + wire _T_172 = _GEN_123 == cam_raw_3_bits_tag; // @[el2_dec_decode_ctl.scala 322:67] wire _T_173 = cam_data_reset & _T_172; // @[el2_dec_decode_ctl.scala 322:45] reg cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 347:47] - wire cam_data_reset_val_3 = _T_173 & cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 322:83] + wire cam_data_reset_val_3 = _T_173 & cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 322:88] wire cam_3_valid = cam_data_reset_val_3 ? 1'h0 : cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 326:39] wire _T_69 = ~cam_3_valid; // @[el2_dec_decode_ctl.scala 303:78] wire _T_75 = _T_63 & cam_2_valid; // @[el2_dec_decode_ctl.scala 303:126] @@ -1472,89 +1472,89 @@ module el2_dec_decode_ctl( wire [2:0] _T_86 = _GEN_128 | _T_83; // @[Mux.scala 27:72] wire [3:0] _GEN_129 = {{1'd0}, _T_86}; // @[Mux.scala 27:72] wire [3:0] cam_wen = _GEN_129 | _T_84; // @[Mux.scala 27:72] - reg x_d_i0load; // @[el2_lib.scala 524:16] - reg [4:0] x_d_i0rd; // @[el2_lib.scala 524:16] - wire [4:0] nonblock_load_rd = x_d_i0load ? x_d_i0rd : 5'h0; // @[el2_dec_decode_ctl.scala 314:31] + reg x_d_bits_i0load; // @[el2_lib.scala 524:16] + reg [4:0] x_d_bits_i0rd; // @[el2_lib.scala 524:16] + wire [4:0] nonblock_load_rd = x_d_bits_i0load ? x_d_bits_i0rd : 5'h0; // @[el2_dec_decode_ctl.scala 314:31] reg [2:0] _T_701; // @[el2_dec_decode_ctl.scala 652:72] wire [3:0] i0_pipe_en = {io_dec_i0_decode_d,_T_701}; // @[Cat.scala 29:58] wire _T_707 = |i0_pipe_en[2:1]; // @[el2_dec_decode_ctl.scala 655:49] wire i0_r_ctl_en = _T_707 | io_clk_override; // @[el2_dec_decode_ctl.scala 655:53] reg nonblock_load_valid_m_delay; // @[Reg.scala 27:20] - reg r_d_i0load; // @[el2_lib.scala 524:16] - wire i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d_i0load; // @[el2_dec_decode_ctl.scala 319:56] + reg r_d_bits_i0load; // @[el2_lib.scala 524:16] + wire i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d_bits_i0load; // @[el2_dec_decode_ctl.scala 319:56] wire [2:0] _GEN_130 = {{1'd0}, io_lsu_nonblock_load_inv_tag_r}; // @[el2_dec_decode_ctl.scala 321:66] - wire _T_91 = _GEN_130 == cam_raw_0_tag; // @[el2_dec_decode_ctl.scala 321:66] + wire _T_91 = _GEN_130 == cam_raw_0_bits_tag; // @[el2_dec_decode_ctl.scala 321:66] wire _T_92 = io_lsu_nonblock_load_inv_r & _T_91; // @[el2_dec_decode_ctl.scala 321:45] - wire cam_inv_reset_val_0 = _T_92 & cam_0_valid; // @[el2_dec_decode_ctl.scala 321:82] - reg r_d_i0v; // @[el2_lib.scala 524:16] - wire _T_743 = ~io_dec_tlu_flush_lower_wb; // @[el2_dec_decode_ctl.scala 687:41] - wire r_d_in_i0v = r_d_i0v & _T_743; // @[el2_dec_decode_ctl.scala 687:39] - wire _T_754 = ~io_dec_tlu_i0_kill_writeb_r; // @[el2_dec_decode_ctl.scala 695:42] - wire i0_wen_r = r_d_in_i0v & _T_754; // @[el2_dec_decode_ctl.scala 695:40] - reg [4:0] r_d_i0rd; // @[el2_lib.scala 524:16] - reg [4:0] cam_raw_0_rd; // @[el2_dec_decode_ctl.scala 347:47] - wire _T_103 = r_d_i0rd == cam_raw_0_rd; // @[el2_dec_decode_ctl.scala 334:80] + wire cam_inv_reset_val_0 = _T_92 & cam_0_valid; // @[el2_dec_decode_ctl.scala 321:87] + reg r_d_bits_i0v; // @[el2_lib.scala 524:16] + wire _T_743 = ~io_dec_tlu_flush_lower_wb; // @[el2_dec_decode_ctl.scala 687:51] + wire r_d_in_bits_i0v = r_d_bits_i0v & _T_743; // @[el2_dec_decode_ctl.scala 687:49] + wire _T_754 = ~io_dec_tlu_i0_kill_writeb_r; // @[el2_dec_decode_ctl.scala 695:47] + wire i0_wen_r = r_d_in_bits_i0v & _T_754; // @[el2_dec_decode_ctl.scala 695:45] + reg [4:0] r_d_bits_i0rd; // @[el2_lib.scala 524:16] + reg [4:0] cam_raw_0_bits_rd; // @[el2_dec_decode_ctl.scala 347:47] + wire _T_103 = r_d_bits_i0rd == cam_raw_0_bits_rd; // @[el2_dec_decode_ctl.scala 334:85] wire _T_104 = i0_wen_r & _T_103; // @[el2_dec_decode_ctl.scala 334:64] - reg cam_raw_0_wb; // @[el2_dec_decode_ctl.scala 347:47] - wire _T_106 = _T_104 & cam_raw_0_wb; // @[el2_dec_decode_ctl.scala 334:95] + reg cam_raw_0_bits_wb; // @[el2_dec_decode_ctl.scala 347:47] + wire _T_106 = _T_104 & cam_raw_0_bits_wb; // @[el2_dec_decode_ctl.scala 334:105] wire _T_107 = cam_inv_reset_val_0 | _T_106; // @[el2_dec_decode_ctl.scala 334:44] - wire _GEN_52 = _T_107 ? 1'h0 : cam_0_valid; // @[el2_dec_decode_ctl.scala 334:116] - wire _GEN_55 = _T_107 ? 1'h0 : cam_raw_0_wb; // @[el2_dec_decode_ctl.scala 334:116] + wire _GEN_52 = _T_107 ? 1'h0 : cam_0_valid; // @[el2_dec_decode_ctl.scala 334:131] + wire _GEN_55 = _T_107 ? 1'h0 : cam_raw_0_bits_wb; // @[el2_dec_decode_ctl.scala 334:131] wire _GEN_56 = cam_wen[0] | _GEN_52; // @[el2_dec_decode_ctl.scala 329:28] wire _GEN_57 = cam_wen[0] ? 1'h0 : _GEN_55; // @[el2_dec_decode_ctl.scala 329:28] wire _T_110 = nonblock_load_valid_m_delay & _T_91; // @[el2_dec_decode_ctl.scala 339:44] - wire _T_112 = _T_110 & cam_0_valid; // @[el2_dec_decode_ctl.scala 339:95] - wire nonblock_load_write_0 = _T_94 & cam_raw_0_valid; // @[el2_dec_decode_ctl.scala 348:66] - wire _T_117 = _GEN_130 == cam_raw_1_tag; // @[el2_dec_decode_ctl.scala 321:66] + wire _T_112 = _T_110 & cam_0_valid; // @[el2_dec_decode_ctl.scala 339:100] + wire nonblock_load_write_0 = _T_94 & cam_raw_0_valid; // @[el2_dec_decode_ctl.scala 348:71] + wire _T_117 = _GEN_130 == cam_raw_1_bits_tag; // @[el2_dec_decode_ctl.scala 321:66] wire _T_118 = io_lsu_nonblock_load_inv_r & _T_117; // @[el2_dec_decode_ctl.scala 321:45] - wire cam_inv_reset_val_1 = _T_118 & cam_1_valid; // @[el2_dec_decode_ctl.scala 321:82] - reg [4:0] cam_raw_1_rd; // @[el2_dec_decode_ctl.scala 347:47] - wire _T_129 = r_d_i0rd == cam_raw_1_rd; // @[el2_dec_decode_ctl.scala 334:80] + wire cam_inv_reset_val_1 = _T_118 & cam_1_valid; // @[el2_dec_decode_ctl.scala 321:87] + reg [4:0] cam_raw_1_bits_rd; // @[el2_dec_decode_ctl.scala 347:47] + wire _T_129 = r_d_bits_i0rd == cam_raw_1_bits_rd; // @[el2_dec_decode_ctl.scala 334:85] wire _T_130 = i0_wen_r & _T_129; // @[el2_dec_decode_ctl.scala 334:64] - reg cam_raw_1_wb; // @[el2_dec_decode_ctl.scala 347:47] - wire _T_132 = _T_130 & cam_raw_1_wb; // @[el2_dec_decode_ctl.scala 334:95] + reg cam_raw_1_bits_wb; // @[el2_dec_decode_ctl.scala 347:47] + wire _T_132 = _T_130 & cam_raw_1_bits_wb; // @[el2_dec_decode_ctl.scala 334:105] wire _T_133 = cam_inv_reset_val_1 | _T_132; // @[el2_dec_decode_ctl.scala 334:44] - wire _GEN_63 = _T_133 ? 1'h0 : cam_1_valid; // @[el2_dec_decode_ctl.scala 334:116] - wire _GEN_66 = _T_133 ? 1'h0 : cam_raw_1_wb; // @[el2_dec_decode_ctl.scala 334:116] + wire _GEN_63 = _T_133 ? 1'h0 : cam_1_valid; // @[el2_dec_decode_ctl.scala 334:131] + wire _GEN_66 = _T_133 ? 1'h0 : cam_raw_1_bits_wb; // @[el2_dec_decode_ctl.scala 334:131] wire _GEN_67 = cam_wen[1] | _GEN_63; // @[el2_dec_decode_ctl.scala 329:28] wire _GEN_68 = cam_wen[1] ? 1'h0 : _GEN_66; // @[el2_dec_decode_ctl.scala 329:28] wire _T_136 = nonblock_load_valid_m_delay & _T_117; // @[el2_dec_decode_ctl.scala 339:44] - wire _T_138 = _T_136 & cam_1_valid; // @[el2_dec_decode_ctl.scala 339:95] - wire nonblock_load_write_1 = _T_120 & cam_raw_1_valid; // @[el2_dec_decode_ctl.scala 348:66] - wire _T_143 = _GEN_130 == cam_raw_2_tag; // @[el2_dec_decode_ctl.scala 321:66] + wire _T_138 = _T_136 & cam_1_valid; // @[el2_dec_decode_ctl.scala 339:100] + wire nonblock_load_write_1 = _T_120 & cam_raw_1_valid; // @[el2_dec_decode_ctl.scala 348:71] + wire _T_143 = _GEN_130 == cam_raw_2_bits_tag; // @[el2_dec_decode_ctl.scala 321:66] wire _T_144 = io_lsu_nonblock_load_inv_r & _T_143; // @[el2_dec_decode_ctl.scala 321:45] - wire cam_inv_reset_val_2 = _T_144 & cam_2_valid; // @[el2_dec_decode_ctl.scala 321:82] - reg [4:0] cam_raw_2_rd; // @[el2_dec_decode_ctl.scala 347:47] - wire _T_155 = r_d_i0rd == cam_raw_2_rd; // @[el2_dec_decode_ctl.scala 334:80] + wire cam_inv_reset_val_2 = _T_144 & cam_2_valid; // @[el2_dec_decode_ctl.scala 321:87] + reg [4:0] cam_raw_2_bits_rd; // @[el2_dec_decode_ctl.scala 347:47] + wire _T_155 = r_d_bits_i0rd == cam_raw_2_bits_rd; // @[el2_dec_decode_ctl.scala 334:85] wire _T_156 = i0_wen_r & _T_155; // @[el2_dec_decode_ctl.scala 334:64] - reg cam_raw_2_wb; // @[el2_dec_decode_ctl.scala 347:47] - wire _T_158 = _T_156 & cam_raw_2_wb; // @[el2_dec_decode_ctl.scala 334:95] + reg cam_raw_2_bits_wb; // @[el2_dec_decode_ctl.scala 347:47] + wire _T_158 = _T_156 & cam_raw_2_bits_wb; // @[el2_dec_decode_ctl.scala 334:105] wire _T_159 = cam_inv_reset_val_2 | _T_158; // @[el2_dec_decode_ctl.scala 334:44] - wire _GEN_74 = _T_159 ? 1'h0 : cam_2_valid; // @[el2_dec_decode_ctl.scala 334:116] - wire _GEN_77 = _T_159 ? 1'h0 : cam_raw_2_wb; // @[el2_dec_decode_ctl.scala 334:116] + wire _GEN_74 = _T_159 ? 1'h0 : cam_2_valid; // @[el2_dec_decode_ctl.scala 334:131] + wire _GEN_77 = _T_159 ? 1'h0 : cam_raw_2_bits_wb; // @[el2_dec_decode_ctl.scala 334:131] wire _GEN_78 = cam_wen[2] | _GEN_74; // @[el2_dec_decode_ctl.scala 329:28] wire _GEN_79 = cam_wen[2] ? 1'h0 : _GEN_77; // @[el2_dec_decode_ctl.scala 329:28] wire _T_162 = nonblock_load_valid_m_delay & _T_143; // @[el2_dec_decode_ctl.scala 339:44] - wire _T_164 = _T_162 & cam_2_valid; // @[el2_dec_decode_ctl.scala 339:95] - wire nonblock_load_write_2 = _T_146 & cam_raw_2_valid; // @[el2_dec_decode_ctl.scala 348:66] - wire _T_169 = _GEN_130 == cam_raw_3_tag; // @[el2_dec_decode_ctl.scala 321:66] + wire _T_164 = _T_162 & cam_2_valid; // @[el2_dec_decode_ctl.scala 339:100] + wire nonblock_load_write_2 = _T_146 & cam_raw_2_valid; // @[el2_dec_decode_ctl.scala 348:71] + wire _T_169 = _GEN_130 == cam_raw_3_bits_tag; // @[el2_dec_decode_ctl.scala 321:66] wire _T_170 = io_lsu_nonblock_load_inv_r & _T_169; // @[el2_dec_decode_ctl.scala 321:45] - wire cam_inv_reset_val_3 = _T_170 & cam_3_valid; // @[el2_dec_decode_ctl.scala 321:82] - reg [4:0] cam_raw_3_rd; // @[el2_dec_decode_ctl.scala 347:47] - wire _T_181 = r_d_i0rd == cam_raw_3_rd; // @[el2_dec_decode_ctl.scala 334:80] + wire cam_inv_reset_val_3 = _T_170 & cam_3_valid; // @[el2_dec_decode_ctl.scala 321:87] + reg [4:0] cam_raw_3_bits_rd; // @[el2_dec_decode_ctl.scala 347:47] + wire _T_181 = r_d_bits_i0rd == cam_raw_3_bits_rd; // @[el2_dec_decode_ctl.scala 334:85] wire _T_182 = i0_wen_r & _T_181; // @[el2_dec_decode_ctl.scala 334:64] - reg cam_raw_3_wb; // @[el2_dec_decode_ctl.scala 347:47] - wire _T_184 = _T_182 & cam_raw_3_wb; // @[el2_dec_decode_ctl.scala 334:95] + reg cam_raw_3_bits_wb; // @[el2_dec_decode_ctl.scala 347:47] + wire _T_184 = _T_182 & cam_raw_3_bits_wb; // @[el2_dec_decode_ctl.scala 334:105] wire _T_185 = cam_inv_reset_val_3 | _T_184; // @[el2_dec_decode_ctl.scala 334:44] - wire _GEN_85 = _T_185 ? 1'h0 : cam_3_valid; // @[el2_dec_decode_ctl.scala 334:116] - wire _GEN_88 = _T_185 ? 1'h0 : cam_raw_3_wb; // @[el2_dec_decode_ctl.scala 334:116] + wire _GEN_85 = _T_185 ? 1'h0 : cam_3_valid; // @[el2_dec_decode_ctl.scala 334:131] + wire _GEN_88 = _T_185 ? 1'h0 : cam_raw_3_bits_wb; // @[el2_dec_decode_ctl.scala 334:131] wire _GEN_89 = cam_wen[3] | _GEN_85; // @[el2_dec_decode_ctl.scala 329:28] wire _GEN_90 = cam_wen[3] ? 1'h0 : _GEN_88; // @[el2_dec_decode_ctl.scala 329:28] wire _T_188 = nonblock_load_valid_m_delay & _T_169; // @[el2_dec_decode_ctl.scala 339:44] - wire _T_190 = _T_188 & cam_3_valid; // @[el2_dec_decode_ctl.scala 339:95] - wire nonblock_load_write_3 = _T_172 & cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 348:66] - wire _T_195 = r_d_i0rd == io_dec_nonblock_load_waddr; // @[el2_dec_decode_ctl.scala 353:44] - wire nonblock_load_cancel = _T_195 & i0_wen_r; // @[el2_dec_decode_ctl.scala 353:76] + wire _T_190 = _T_188 & cam_3_valid; // @[el2_dec_decode_ctl.scala 339:100] + wire nonblock_load_write_3 = _T_172 & cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 348:71] + wire _T_195 = r_d_bits_i0rd == io_dec_nonblock_load_waddr; // @[el2_dec_decode_ctl.scala 353:49] + wire nonblock_load_cancel = _T_195 & i0_wen_r; // @[el2_dec_decode_ctl.scala 353:81] wire _T_196 = nonblock_load_write_0 | nonblock_load_write_1; // @[el2_dec_decode_ctl.scala 354:95] wire _T_197 = _T_196 | nonblock_load_write_2; // @[el2_dec_decode_ctl.scala 354:95] wire _T_198 = _T_197 | nonblock_load_write_3; // @[el2_dec_decode_ctl.scala 354:95] @@ -1569,37 +1569,37 @@ module el2_dec_decode_ctl( wire _T_208 = _T_207 & io_dec_i0_rs2_en_d; // @[el2_dec_decode_ctl.scala 355:180] wire i0_nonblock_boundary_stall = _T_205 | _T_208; // @[el2_dec_decode_ctl.scala 355:118] wire [4:0] _T_210 = nonblock_load_write_0 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] - wire [4:0] _T_211 = _T_210 & cam_raw_0_rd; // @[el2_dec_decode_ctl.scala 359:88] - wire _T_212 = io_dec_i0_rs1_en_d & cam_0_valid; // @[el2_dec_decode_ctl.scala 359:121] - wire _T_213 = cam_raw_0_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 359:149] - wire _T_214 = _T_212 & _T_213; // @[el2_dec_decode_ctl.scala 359:136] - wire _T_215 = io_dec_i0_rs2_en_d & cam_0_valid; // @[el2_dec_decode_ctl.scala 359:182] - wire _T_216 = cam_raw_0_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 359:210] - wire _T_217 = _T_215 & _T_216; // @[el2_dec_decode_ctl.scala 359:197] + wire [4:0] _T_211 = _T_210 & cam_raw_0_bits_rd; // @[el2_dec_decode_ctl.scala 359:88] + wire _T_212 = io_dec_i0_rs1_en_d & cam_0_valid; // @[el2_dec_decode_ctl.scala 359:126] + wire _T_213 = cam_raw_0_bits_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 359:159] + wire _T_214 = _T_212 & _T_213; // @[el2_dec_decode_ctl.scala 359:141] + wire _T_215 = io_dec_i0_rs2_en_d & cam_0_valid; // @[el2_dec_decode_ctl.scala 359:192] + wire _T_216 = cam_raw_0_bits_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 359:225] + wire _T_217 = _T_215 & _T_216; // @[el2_dec_decode_ctl.scala 359:207] wire [4:0] _T_219 = nonblock_load_write_1 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] - wire [4:0] _T_220 = _T_219 & cam_raw_1_rd; // @[el2_dec_decode_ctl.scala 359:88] - wire _T_221 = io_dec_i0_rs1_en_d & cam_1_valid; // @[el2_dec_decode_ctl.scala 359:121] - wire _T_222 = cam_raw_1_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 359:149] - wire _T_223 = _T_221 & _T_222; // @[el2_dec_decode_ctl.scala 359:136] - wire _T_224 = io_dec_i0_rs2_en_d & cam_1_valid; // @[el2_dec_decode_ctl.scala 359:182] - wire _T_225 = cam_raw_1_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 359:210] - wire _T_226 = _T_224 & _T_225; // @[el2_dec_decode_ctl.scala 359:197] + wire [4:0] _T_220 = _T_219 & cam_raw_1_bits_rd; // @[el2_dec_decode_ctl.scala 359:88] + wire _T_221 = io_dec_i0_rs1_en_d & cam_1_valid; // @[el2_dec_decode_ctl.scala 359:126] + wire _T_222 = cam_raw_1_bits_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 359:159] + wire _T_223 = _T_221 & _T_222; // @[el2_dec_decode_ctl.scala 359:141] + wire _T_224 = io_dec_i0_rs2_en_d & cam_1_valid; // @[el2_dec_decode_ctl.scala 359:192] + wire _T_225 = cam_raw_1_bits_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 359:225] + wire _T_226 = _T_224 & _T_225; // @[el2_dec_decode_ctl.scala 359:207] wire [4:0] _T_228 = nonblock_load_write_2 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] - wire [4:0] _T_229 = _T_228 & cam_raw_2_rd; // @[el2_dec_decode_ctl.scala 359:88] - wire _T_230 = io_dec_i0_rs1_en_d & cam_2_valid; // @[el2_dec_decode_ctl.scala 359:121] - wire _T_231 = cam_raw_2_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 359:149] - wire _T_232 = _T_230 & _T_231; // @[el2_dec_decode_ctl.scala 359:136] - wire _T_233 = io_dec_i0_rs2_en_d & cam_2_valid; // @[el2_dec_decode_ctl.scala 359:182] - wire _T_234 = cam_raw_2_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 359:210] - wire _T_235 = _T_233 & _T_234; // @[el2_dec_decode_ctl.scala 359:197] + wire [4:0] _T_229 = _T_228 & cam_raw_2_bits_rd; // @[el2_dec_decode_ctl.scala 359:88] + wire _T_230 = io_dec_i0_rs1_en_d & cam_2_valid; // @[el2_dec_decode_ctl.scala 359:126] + wire _T_231 = cam_raw_2_bits_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 359:159] + wire _T_232 = _T_230 & _T_231; // @[el2_dec_decode_ctl.scala 359:141] + wire _T_233 = io_dec_i0_rs2_en_d & cam_2_valid; // @[el2_dec_decode_ctl.scala 359:192] + wire _T_234 = cam_raw_2_bits_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 359:225] + wire _T_235 = _T_233 & _T_234; // @[el2_dec_decode_ctl.scala 359:207] wire [4:0] _T_237 = nonblock_load_write_3 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] - wire [4:0] _T_238 = _T_237 & cam_raw_3_rd; // @[el2_dec_decode_ctl.scala 359:88] - wire _T_239 = io_dec_i0_rs1_en_d & cam_3_valid; // @[el2_dec_decode_ctl.scala 359:121] - wire _T_240 = cam_raw_3_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 359:149] - wire _T_241 = _T_239 & _T_240; // @[el2_dec_decode_ctl.scala 359:136] - wire _T_242 = io_dec_i0_rs2_en_d & cam_3_valid; // @[el2_dec_decode_ctl.scala 359:182] - wire _T_243 = cam_raw_3_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 359:210] - wire _T_244 = _T_242 & _T_243; // @[el2_dec_decode_ctl.scala 359:197] + wire [4:0] _T_238 = _T_237 & cam_raw_3_bits_rd; // @[el2_dec_decode_ctl.scala 359:88] + wire _T_239 = io_dec_i0_rs1_en_d & cam_3_valid; // @[el2_dec_decode_ctl.scala 359:126] + wire _T_240 = cam_raw_3_bits_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 359:159] + wire _T_241 = _T_239 & _T_240; // @[el2_dec_decode_ctl.scala 359:141] + wire _T_242 = io_dec_i0_rs2_en_d & cam_3_valid; // @[el2_dec_decode_ctl.scala 359:192] + wire _T_243 = cam_raw_3_bits_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 359:225] + wire _T_244 = _T_242 & _T_243; // @[el2_dec_decode_ctl.scala 359:207] wire [4:0] _T_245 = _T_211 | _T_220; // @[el2_dec_decode_ctl.scala 360:69] wire [4:0] _T_246 = _T_245 | _T_229; // @[el2_dec_decode_ctl.scala 360:69] wire _T_247 = _T_214 | _T_223; // @[el2_dec_decode_ctl.scala 360:102] @@ -1641,13 +1641,13 @@ module el2_dec_decode_ctl( reg _T_339; // @[el2_dec_decode_ctl.scala 432:58] wire lsu_decode_d = i0_legal_decode_d & i0_dp_lsu; // @[el2_dec_decode_ctl.scala 574:40] wire _T_902 = i0_dp_load | i0_dp_store; // @[el2_dec_decode_ctl.scala 788:43] - reg x_d_i0v; // @[el2_lib.scala 524:16] - wire _T_876 = io_dec_i0_rs1_en_d & x_d_i0v; // @[el2_dec_decode_ctl.scala 768:48] - wire _T_877 = x_d_i0rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 768:70] - wire i0_rs1_depend_i0_x = _T_876 & _T_877; // @[el2_dec_decode_ctl.scala 768:58] - wire _T_878 = io_dec_i0_rs1_en_d & r_d_i0v; // @[el2_dec_decode_ctl.scala 769:48] - wire _T_879 = r_d_i0rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 769:70] - wire i0_rs1_depend_i0_r = _T_878 & _T_879; // @[el2_dec_decode_ctl.scala 769:58] + reg x_d_bits_i0v; // @[el2_lib.scala 524:16] + wire _T_876 = io_dec_i0_rs1_en_d & x_d_bits_i0v; // @[el2_dec_decode_ctl.scala 768:48] + wire _T_877 = x_d_bits_i0rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 768:80] + wire i0_rs1_depend_i0_x = _T_876 & _T_877; // @[el2_dec_decode_ctl.scala 768:63] + wire _T_878 = io_dec_i0_rs1_en_d & r_d_bits_i0v; // @[el2_dec_decode_ctl.scala 769:48] + wire _T_879 = r_d_bits_i0rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 769:80] + wire i0_rs1_depend_i0_r = _T_878 & _T_879; // @[el2_dec_decode_ctl.scala 769:63] wire [1:0] _T_891 = i0_rs1_depend_i0_r ? 2'h2 : 2'h0; // @[el2_dec_decode_ctl.scala 775:63] wire [1:0] i0_rs1_depth_d = i0_rs1_depend_i0_x ? 2'h1 : _T_891; // @[el2_dec_decode_ctl.scala 775:24] wire _T_904 = _T_902 & i0_rs1_depth_d[0]; // @[el2_dec_decode_ctl.scala 788:58] @@ -1656,12 +1656,12 @@ module el2_dec_decode_ctl( wire _T_887_load = i0_rs1_depend_i0_r & i0_r_c_load; // @[el2_dec_decode_ctl.scala 774:61] wire i0_rs1_class_d_load = i0_rs1_depend_i0_x ? i0_x_c_load : _T_887_load; // @[el2_dec_decode_ctl.scala 774:24] wire load_ldst_bypass_d = _T_904 & i0_rs1_class_d_load; // @[el2_dec_decode_ctl.scala 788:78] - wire _T_880 = io_dec_i0_rs2_en_d & x_d_i0v; // @[el2_dec_decode_ctl.scala 771:48] - wire _T_881 = x_d_i0rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 771:70] - wire i0_rs2_depend_i0_x = _T_880 & _T_881; // @[el2_dec_decode_ctl.scala 771:58] - wire _T_882 = io_dec_i0_rs2_en_d & r_d_i0v; // @[el2_dec_decode_ctl.scala 772:48] - wire _T_883 = r_d_i0rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 772:70] - wire i0_rs2_depend_i0_r = _T_882 & _T_883; // @[el2_dec_decode_ctl.scala 772:58] + wire _T_880 = io_dec_i0_rs2_en_d & x_d_bits_i0v; // @[el2_dec_decode_ctl.scala 771:48] + wire _T_881 = x_d_bits_i0rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 771:80] + wire i0_rs2_depend_i0_x = _T_880 & _T_881; // @[el2_dec_decode_ctl.scala 771:63] + wire _T_882 = io_dec_i0_rs2_en_d & r_d_bits_i0v; // @[el2_dec_decode_ctl.scala 772:48] + wire _T_883 = r_d_bits_i0rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 772:80] + wire i0_rs2_depend_i0_r = _T_882 & _T_883; // @[el2_dec_decode_ctl.scala 772:63] wire [1:0] _T_900 = i0_rs2_depend_i0_r ? 2'h2 : 2'h0; // @[el2_dec_decode_ctl.scala 777:63] wire [1:0] i0_rs2_depth_d = i0_rs2_depend_i0_x ? 2'h1 : _T_900; // @[el2_dec_decode_ctl.scala 777:24] wire _T_907 = i0_dp_store & i0_rs2_depth_d[0]; // @[el2_dec_decode_ctl.scala 789:43] @@ -1669,16 +1669,16 @@ module el2_dec_decode_ctl( wire i0_rs2_class_d_load = i0_rs2_depend_i0_x ? i0_x_c_load : _T_896_load; // @[el2_dec_decode_ctl.scala 776:24] wire store_data_bypass_d = _T_907 & i0_rs2_class_d_load; // @[el2_dec_decode_ctl.scala 789:63] wire _T_349 = i0_dp_csr_clr | i0_dp_csr_set; // @[el2_dec_decode_ctl.scala 463:42] - reg r_d_csrwen; // @[el2_lib.scala 524:16] - reg r_d_i0valid; // @[el2_lib.scala 524:16] - wire _T_352 = r_d_csrwen & r_d_i0valid; // @[el2_dec_decode_ctl.scala 471:34] - reg [11:0] r_d_csrwaddr; // @[el2_lib.scala 524:16] - wire _T_355 = r_d_csrwaddr == 12'h300; // @[el2_dec_decode_ctl.scala 474:45] - wire _T_356 = r_d_csrwaddr == 12'h304; // @[el2_dec_decode_ctl.scala 474:75] - wire _T_357 = _T_355 | _T_356; // @[el2_dec_decode_ctl.scala 474:59] - wire _T_358 = _T_357 & r_d_csrwen; // @[el2_dec_decode_ctl.scala 474:90] - wire _T_359 = _T_358 & r_d_i0valid; // @[el2_dec_decode_ctl.scala 474:103] - wire _T_360 = ~io_dec_tlu_i0_kill_writeb_wb; // @[el2_dec_decode_ctl.scala 474:119] + reg r_d_bits_csrwen; // @[el2_lib.scala 524:16] + reg r_d_valid; // @[el2_lib.scala 524:16] + wire _T_352 = r_d_bits_csrwen & r_d_valid; // @[el2_dec_decode_ctl.scala 471:39] + reg [11:0] r_d_bits_csrwaddr; // @[el2_lib.scala 524:16] + wire _T_355 = r_d_bits_csrwaddr == 12'h300; // @[el2_dec_decode_ctl.scala 474:50] + wire _T_356 = r_d_bits_csrwaddr == 12'h304; // @[el2_dec_decode_ctl.scala 474:85] + wire _T_357 = _T_355 | _T_356; // @[el2_dec_decode_ctl.scala 474:64] + wire _T_358 = _T_357 & r_d_bits_csrwen; // @[el2_dec_decode_ctl.scala 474:100] + wire _T_359 = _T_358 & r_d_valid; // @[el2_dec_decode_ctl.scala 474:118] + wire _T_360 = ~io_dec_tlu_i0_kill_writeb_wb; // @[el2_dec_decode_ctl.scala 474:132] reg csr_read_x; // @[el2_dec_decode_ctl.scala 476:52] reg csr_clr_x; // @[el2_dec_decode_ctl.scala 477:51] reg csr_set_x; // @[el2_dec_decode_ctl.scala 478:51] @@ -1708,14 +1708,14 @@ module el2_dec_decode_ctl( wire _T_426 = _T_425 | csr_write_x; // @[el2_dec_decode_ctl.scala 507:46] wire _T_427 = _T_426 & csr_read_x; // @[el2_dec_decode_ctl.scala 507:61] wire _T_428 = _T_427 | io_dec_tlu_wr_pause_r; // @[el2_dec_decode_ctl.scala 507:75] - reg r_d_csrwonly; // @[el2_lib.scala 524:16] - wire _T_764 = r_d_i0v & r_d_i0load; // @[el2_dec_decode_ctl.scala 710:37] + reg r_d_bits_csrwonly; // @[el2_lib.scala 524:16] + wire _T_764 = r_d_bits_i0v & r_d_bits_i0load; // @[el2_dec_decode_ctl.scala 710:42] reg [31:0] i0_result_r_raw; // @[el2_lib.scala 514:16] wire [31:0] i0_result_corr_r = _T_764 ? io_lsu_result_corr_r : i0_result_r_raw; // @[el2_dec_decode_ctl.scala 710:27] - reg x_d_csrwonly; // @[el2_lib.scala 524:16] - wire _T_432 = x_d_csrwonly | r_d_csrwonly; // @[el2_dec_decode_ctl.scala 516:38] - reg wbd_csrwonly; // @[el2_lib.scala 524:16] - wire prior_csr_write = _T_432 | wbd_csrwonly; // @[el2_dec_decode_ctl.scala 516:53] + reg x_d_bits_csrwonly; // @[el2_lib.scala 524:16] + wire _T_432 = x_d_bits_csrwonly | r_d_bits_csrwonly; // @[el2_dec_decode_ctl.scala 516:43] + reg wbd_bits_csrwonly; // @[el2_lib.scala 524:16] + wire prior_csr_write = _T_432 | wbd_bits_csrwonly; // @[el2_dec_decode_ctl.scala 516:63] wire debug_fence_raw = io_dec_debug_fence_d & io_dbg_cmd_wrdata[1]; // @[el2_dec_decode_ctl.scala 519:48] wire debug_fence = debug_fence_raw | debug_fence_i; // @[el2_dec_decode_ctl.scala 520:40] wire _T_436 = i0_dp_presync | io_dec_tlu_presync_d; // @[el2_dec_decode_ctl.scala 523:34] @@ -1732,8 +1732,8 @@ module el2_dec_decode_ctl( wire _T_473 = _T_472 | leak1_i0_stall; // @[el2_dec_decode_ctl.scala 541:95] wire _T_474 = _T_473 | io_dec_tlu_debug_stall; // @[el2_dec_decode_ctl.scala 542:20] wire _T_475 = _T_474 | postsync_stall; // @[el2_dec_decode_ctl.scala 542:45] - wire prior_inflight = x_d_i0valid | r_d_i0valid; // @[el2_dec_decode_ctl.scala 564:41] - wire prior_inflight_eff = i0_dp_div ? x_d_i0valid : prior_inflight; // @[el2_dec_decode_ctl.scala 565:31] + wire prior_inflight = x_d_valid | r_d_valid; // @[el2_dec_decode_ctl.scala 564:41] + wire prior_inflight_eff = i0_dp_div ? x_d_valid : prior_inflight; // @[el2_dec_decode_ctl.scala 565:31] wire presync_stall = i0_presync & prior_inflight_eff; // @[el2_dec_decode_ctl.scala 567:37] wire _T_476 = _T_475 | presync_stall; // @[el2_dec_decode_ctl.scala 542:62] wire _T_477 = i0_dp_fence | debug_fence; // @[el2_dec_decode_ctl.scala 543:19] @@ -1789,13 +1789,13 @@ module el2_dec_decode_ctl( reg r_t_pmu_i0_br_unpred; // @[el2_lib.scala 524:16] reg [3:0] lsu_trigger_match_r; // @[el2_dec_decode_ctl.scala 602:36] reg lsu_pmu_misaligned_r; // @[el2_dec_decode_ctl.scala 603:37] - reg r_d_i0store; // @[el2_lib.scala 524:16] - wire _T_536 = r_d_i0load | r_d_i0store; // @[el2_dec_decode_ctl.scala 607:56] + reg r_d_bits_i0store; // @[el2_lib.scala 524:16] + wire _T_536 = r_d_bits_i0load | r_d_bits_i0store; // @[el2_dec_decode_ctl.scala 607:61] wire [3:0] _T_540 = {_T_536,_T_536,_T_536,_T_536}; // @[Cat.scala 29:58] - wire [3:0] _T_541 = _T_540 & lsu_trigger_match_r; // @[el2_dec_decode_ctl.scala 607:72] - wire [3:0] _T_542 = _T_541 | r_t_i0trigger; // @[el2_dec_decode_ctl.scala 607:95] - reg r_d_i0div; // @[el2_lib.scala 524:16] - wire _T_545 = r_d_i0div & r_d_i0valid; // @[el2_dec_decode_ctl.scala 613:53] + wire [3:0] _T_541 = _T_540 & lsu_trigger_match_r; // @[el2_dec_decode_ctl.scala 607:82] + wire [3:0] _T_542 = _T_541 | r_t_i0trigger; // @[el2_dec_decode_ctl.scala 607:105] + reg r_d_bits_i0div; // @[el2_lib.scala 524:16] + wire _T_545 = r_d_bits_i0div & r_d_valid; // @[el2_dec_decode_ctl.scala 613:58] wire _T_556 = i0r_rs1 != 5'h0; // @[el2_dec_decode_ctl.scala 624:49] wire _T_558 = i0r_rs2 != 5'h0; // @[el2_dec_decode_ctl.scala 625:49] wire _T_560 = i0r_rd != 5'h0; // @[el2_dec_decode_ctl.scala 626:48] @@ -1831,34 +1831,34 @@ module el2_dec_decode_ctl( reg i0_r_c_alu; // @[Reg.scala 15:16] wire _T_710 = |i0_pipe_en[1:0]; // @[el2_dec_decode_ctl.scala 656:49] wire i0_r_data_en = i0_pipe_en[2] | io_clk_override; // @[el2_dec_decode_ctl.scala 658:50] - reg x_d_i0store; // @[el2_lib.scala 524:16] - reg x_d_i0div; // @[el2_lib.scala 524:16] - reg x_d_csrwen; // @[el2_lib.scala 524:16] - reg [11:0] x_d_csrwaddr; // @[el2_lib.scala 524:16] - wire _T_733 = x_d_i0v & _T_743; // @[el2_dec_decode_ctl.scala 680:37] - wire _T_737 = x_d_i0valid & _T_743; // @[el2_dec_decode_ctl.scala 681:37] - wire _T_756 = ~r_d_i0div; // @[el2_dec_decode_ctl.scala 696:49] + reg x_d_bits_i0store; // @[el2_lib.scala 524:16] + reg x_d_bits_i0div; // @[el2_lib.scala 524:16] + reg x_d_bits_csrwen; // @[el2_lib.scala 524:16] + reg [11:0] x_d_bits_csrwaddr; // @[el2_lib.scala 524:16] + wire _T_733 = x_d_bits_i0v & _T_743; // @[el2_dec_decode_ctl.scala 680:47] + wire _T_737 = x_d_valid & _T_743; // @[el2_dec_decode_ctl.scala 681:33] + wire _T_756 = ~r_d_bits_i0div; // @[el2_dec_decode_ctl.scala 696:49] wire _T_757 = i0_wen_r & _T_756; // @[el2_dec_decode_ctl.scala 696:47] - wire _T_758 = ~i0_load_kill_wen_r; // @[el2_dec_decode_ctl.scala 696:65] - wire _T_761 = x_d_i0v & x_d_i0load; // @[el2_dec_decode_ctl.scala 705:42] + wire _T_758 = ~i0_load_kill_wen_r; // @[el2_dec_decode_ctl.scala 696:70] + wire _T_761 = x_d_bits_i0v & x_d_bits_i0load; // @[el2_dec_decode_ctl.scala 705:47] wire _T_768 = io_i0_ap_predict_nt & _T_561; // @[el2_dec_decode_ctl.scala 711:52] wire [11:0] _T_781 = {10'h0,io_dec_i0_pc4_d,i0_ap_pc2}; // @[Cat.scala 29:58] reg [11:0] last_br_immed_x; // @[el2_lib.scala 514:16] - wire _T_799 = x_d_i0div & x_d_i0valid; // @[el2_dec_decode_ctl.scala 719:40] - wire div_e1_to_r = _T_799 | _T_545; // @[el2_dec_decode_ctl.scala 719:55] - wire _T_802 = x_d_i0rd == 5'h0; // @[el2_dec_decode_ctl.scala 721:69] - wire _T_803 = _T_799 & _T_802; // @[el2_dec_decode_ctl.scala 721:57] - wire _T_805 = _T_799 & io_dec_tlu_flush_lower_r; // @[el2_dec_decode_ctl.scala 722:30] - wire _T_806 = _T_803 | _T_805; // @[el2_dec_decode_ctl.scala 721:86] - wire _T_808 = _T_545 & io_dec_tlu_flush_lower_r; // @[el2_dec_decode_ctl.scala 723:30] - wire _T_809 = _T_808 & io_dec_tlu_i0_kill_writeb_r; // @[el2_dec_decode_ctl.scala 723:57] - wire div_flush = _T_806 | _T_809; // @[el2_dec_decode_ctl.scala 722:59] + wire _T_799 = x_d_bits_i0div & x_d_valid; // @[el2_dec_decode_ctl.scala 719:45] + wire div_e1_to_r = _T_799 | _T_545; // @[el2_dec_decode_ctl.scala 719:58] + wire _T_802 = x_d_bits_i0rd == 5'h0; // @[el2_dec_decode_ctl.scala 721:77] + wire _T_803 = _T_799 & _T_802; // @[el2_dec_decode_ctl.scala 721:60] + wire _T_805 = _T_799 & io_dec_tlu_flush_lower_r; // @[el2_dec_decode_ctl.scala 722:33] + wire _T_806 = _T_803 | _T_805; // @[el2_dec_decode_ctl.scala 721:94] + wire _T_808 = _T_545 & io_dec_tlu_flush_lower_r; // @[el2_dec_decode_ctl.scala 723:33] + wire _T_809 = _T_808 & io_dec_tlu_i0_kill_writeb_r; // @[el2_dec_decode_ctl.scala 723:60] + wire div_flush = _T_806 | _T_809; // @[el2_dec_decode_ctl.scala 722:62] wire _T_810 = io_dec_div_active & div_flush; // @[el2_dec_decode_ctl.scala 727:51] wire _T_811 = ~div_e1_to_r; // @[el2_dec_decode_ctl.scala 728:26] wire _T_812 = io_dec_div_active & _T_811; // @[el2_dec_decode_ctl.scala 728:24] - wire _T_813 = r_d_i0rd == io_div_waddr_wb; // @[el2_dec_decode_ctl.scala 728:51] + wire _T_813 = r_d_bits_i0rd == io_div_waddr_wb; // @[el2_dec_decode_ctl.scala 728:56] wire _T_814 = _T_812 & _T_813; // @[el2_dec_decode_ctl.scala 728:39] - wire _T_815 = _T_814 & i0_wen_r; // @[el2_dec_decode_ctl.scala 728:72] + wire _T_815 = _T_814 & i0_wen_r; // @[el2_dec_decode_ctl.scala 728:77] wire nonblock_div_cancel = _T_810 | _T_815; // @[el2_dec_decode_ctl.scala 727:65] wire i0_div_decode_d = i0_legal_decode_d & i0_dp_div; // @[el2_dec_decode_ctl.scala 731:55] wire _T_817 = ~io_exu_div_wren; // @[el2_dec_decode_ctl.scala 733:62] @@ -2157,7 +2157,7 @@ module el2_dec_decode_ctl( assign io_dec_i0_alu_decode_d = i0_exulegal_decode_d & i0_dp_alu; // @[el2_dec_decode_ctl.scala 572:26] assign io_dec_i0_rs1_bypass_data_d = _T_967 | _T_966; // @[el2_dec_decode_ctl.scala 807:31] assign io_dec_i0_rs2_bypass_data_d = _T_984 | _T_983; // @[el2_dec_decode_ctl.scala 812:31] - assign io_dec_i0_waddr_r = r_d_i0rd; // @[el2_dec_decode_ctl.scala 694:27] + assign io_dec_i0_waddr_r = r_d_bits_i0rd; // @[el2_dec_decode_ctl.scala 694:27] assign io_dec_i0_wen_r = _T_757 & _T_758; // @[el2_dec_decode_ctl.scala 696:32] assign io_dec_i0_wdata_r = _T_764 ? io_lsu_result_corr_r : i0_result_r_raw; // @[el2_dec_decode_ctl.scala 697:26] assign io_dec_i0_select_pc_d = _T_41 ? 1'h0 : i0_dp_raw_pc; // @[el2_dec_decode_ctl.scala 271:25] @@ -2189,10 +2189,10 @@ module el2_dec_decode_ctl( assign io_dec_csr_any_unq_d = i0_dp_csr_read | i0_csr_write; // @[el2_dec_decode_ctl.scala 529:24] assign io_dec_csr_rdaddr_d = io_dec_i0_instr_d[31:20]; // @[el2_dec_decode_ctl.scala 466:24] assign io_dec_csr_wen_r = _T_352 & _T_754; // @[el2_dec_decode_ctl.scala 471:20] - assign io_dec_csr_wraddr_r = r_d_csrwaddr; // @[el2_dec_decode_ctl.scala 467:23] - assign io_dec_csr_wrdata_r = r_d_csrwonly ? i0_result_corr_r : write_csr_data; // @[el2_dec_decode_ctl.scala 514:24] + assign io_dec_csr_wraddr_r = r_d_bits_csrwaddr; // @[el2_dec_decode_ctl.scala 467:23] + assign io_dec_csr_wrdata_r = r_d_bits_csrwonly ? i0_result_corr_r : write_csr_data; // @[el2_dec_decode_ctl.scala 514:24] assign io_dec_csr_stall_int_ff = _T_359 & _T_360; // @[el2_dec_decode_ctl.scala 474:27] - assign io_dec_tlu_i0_valid_r = r_d_i0valid & _T_743; // @[el2_dec_decode_ctl.scala 578:29] + assign io_dec_tlu_i0_valid_r = r_d_valid & _T_743; // @[el2_dec_decode_ctl.scala 578:29] assign io_dec_tlu_packet_r_legal = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_legal; // @[el2_dec_decode_ctl.scala 612:39] assign io_dec_tlu_packet_r_icaf = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf; // @[el2_dec_decode_ctl.scala 612:39] assign io_dec_tlu_packet_r_icaf_f1 = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf_f1; // @[el2_dec_decode_ctl.scala 612:39] @@ -2201,7 +2201,7 @@ module el2_dec_decode_ctl( assign io_dec_tlu_packet_r_i0trigger = io_dec_tlu_flush_lower_wb ? 4'h0 : _T_542; // @[el2_dec_decode_ctl.scala 612:39] assign io_dec_tlu_packet_r_pmu_i0_itype = io_dec_tlu_flush_lower_wb ? 4'h0 : r_t_pmu_i0_itype; // @[el2_dec_decode_ctl.scala 612:39] assign io_dec_tlu_packet_r_pmu_i0_br_unpred = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_pmu_i0_br_unpred; // @[el2_dec_decode_ctl.scala 612:39] - assign io_dec_tlu_packet_r_pmu_divide = r_d_i0div & r_d_i0valid; // @[el2_dec_decode_ctl.scala 612:39 el2_dec_decode_ctl.scala 613:39] + assign io_dec_tlu_packet_r_pmu_divide = r_d_bits_i0div & r_d_valid; // @[el2_dec_decode_ctl.scala 612:39 el2_dec_decode_ctl.scala 613:39] assign io_dec_tlu_packet_r_pmu_lsu_misaligned = io_dec_tlu_flush_lower_wb ? 1'h0 : lsu_pmu_misaligned_r; // @[el2_dec_decode_ctl.scala 612:39] assign io_dec_tlu_i0_pc_r = dec_i0_pc_r; // @[el2_dec_decode_ctl.scala 759:27] assign io_dec_illegal_inst = _T_465; // @[el2_dec_decode_ctl.scala 536:23] @@ -2342,73 +2342,73 @@ initial begin _RAND_6 = {1{`RANDOM}}; postsync_stall = _RAND_6[0:0]; _RAND_7 = {1{`RANDOM}}; - x_d_i0valid = _RAND_7[0:0]; + x_d_valid = _RAND_7[0:0]; _RAND_8 = {1{`RANDOM}}; flush_final_r = _RAND_8[0:0]; _RAND_9 = {1{`RANDOM}}; illegal_lockout = _RAND_9[0:0]; _RAND_10 = {1{`RANDOM}}; - cam_raw_0_tag = _RAND_10[2:0]; + cam_raw_0_bits_tag = _RAND_10[2:0]; _RAND_11 = {1{`RANDOM}}; cam_raw_0_valid = _RAND_11[0:0]; _RAND_12 = {1{`RANDOM}}; - cam_raw_1_tag = _RAND_12[2:0]; + cam_raw_1_bits_tag = _RAND_12[2:0]; _RAND_13 = {1{`RANDOM}}; cam_raw_1_valid = _RAND_13[0:0]; _RAND_14 = {1{`RANDOM}}; - cam_raw_2_tag = _RAND_14[2:0]; + cam_raw_2_bits_tag = _RAND_14[2:0]; _RAND_15 = {1{`RANDOM}}; cam_raw_2_valid = _RAND_15[0:0]; _RAND_16 = {1{`RANDOM}}; - cam_raw_3_tag = _RAND_16[2:0]; + cam_raw_3_bits_tag = _RAND_16[2:0]; _RAND_17 = {1{`RANDOM}}; cam_raw_3_valid = _RAND_17[0:0]; _RAND_18 = {1{`RANDOM}}; - x_d_i0load = _RAND_18[0:0]; + x_d_bits_i0load = _RAND_18[0:0]; _RAND_19 = {1{`RANDOM}}; - x_d_i0rd = _RAND_19[4:0]; + x_d_bits_i0rd = _RAND_19[4:0]; _RAND_20 = {1{`RANDOM}}; _T_701 = _RAND_20[2:0]; _RAND_21 = {1{`RANDOM}}; nonblock_load_valid_m_delay = _RAND_21[0:0]; _RAND_22 = {1{`RANDOM}}; - r_d_i0load = _RAND_22[0:0]; + r_d_bits_i0load = _RAND_22[0:0]; _RAND_23 = {1{`RANDOM}}; - r_d_i0v = _RAND_23[0:0]; + r_d_bits_i0v = _RAND_23[0:0]; _RAND_24 = {1{`RANDOM}}; - r_d_i0rd = _RAND_24[4:0]; + r_d_bits_i0rd = _RAND_24[4:0]; _RAND_25 = {1{`RANDOM}}; - cam_raw_0_rd = _RAND_25[4:0]; + cam_raw_0_bits_rd = _RAND_25[4:0]; _RAND_26 = {1{`RANDOM}}; - cam_raw_0_wb = _RAND_26[0:0]; + cam_raw_0_bits_wb = _RAND_26[0:0]; _RAND_27 = {1{`RANDOM}}; - cam_raw_1_rd = _RAND_27[4:0]; + cam_raw_1_bits_rd = _RAND_27[4:0]; _RAND_28 = {1{`RANDOM}}; - cam_raw_1_wb = _RAND_28[0:0]; + cam_raw_1_bits_wb = _RAND_28[0:0]; _RAND_29 = {1{`RANDOM}}; - cam_raw_2_rd = _RAND_29[4:0]; + cam_raw_2_bits_rd = _RAND_29[4:0]; _RAND_30 = {1{`RANDOM}}; - cam_raw_2_wb = _RAND_30[0:0]; + cam_raw_2_bits_wb = _RAND_30[0:0]; _RAND_31 = {1{`RANDOM}}; - cam_raw_3_rd = _RAND_31[4:0]; + cam_raw_3_bits_rd = _RAND_31[4:0]; _RAND_32 = {1{`RANDOM}}; - cam_raw_3_wb = _RAND_32[0:0]; + cam_raw_3_bits_wb = _RAND_32[0:0]; _RAND_33 = {1{`RANDOM}}; lsu_idle = _RAND_33[0:0]; _RAND_34 = {1{`RANDOM}}; _T_339 = _RAND_34[0:0]; _RAND_35 = {1{`RANDOM}}; - x_d_i0v = _RAND_35[0:0]; + x_d_bits_i0v = _RAND_35[0:0]; _RAND_36 = {1{`RANDOM}}; i0_x_c_load = _RAND_36[0:0]; _RAND_37 = {1{`RANDOM}}; i0_r_c_load = _RAND_37[0:0]; _RAND_38 = {1{`RANDOM}}; - r_d_csrwen = _RAND_38[0:0]; + r_d_bits_csrwen = _RAND_38[0:0]; _RAND_39 = {1{`RANDOM}}; - r_d_i0valid = _RAND_39[0:0]; + r_d_valid = _RAND_39[0:0]; _RAND_40 = {1{`RANDOM}}; - r_d_csrwaddr = _RAND_40[11:0]; + r_d_bits_csrwaddr = _RAND_40[11:0]; _RAND_41 = {1{`RANDOM}}; csr_read_x = _RAND_41[0:0]; _RAND_42 = {1{`RANDOM}}; @@ -2424,13 +2424,13 @@ initial begin _RAND_47 = {1{`RANDOM}}; csr_rddata_x = _RAND_47[31:0]; _RAND_48 = {1{`RANDOM}}; - r_d_csrwonly = _RAND_48[0:0]; + r_d_bits_csrwonly = _RAND_48[0:0]; _RAND_49 = {1{`RANDOM}}; i0_result_r_raw = _RAND_49[31:0]; _RAND_50 = {1{`RANDOM}}; - x_d_csrwonly = _RAND_50[0:0]; + x_d_bits_csrwonly = _RAND_50[0:0]; _RAND_51 = {1{`RANDOM}}; - wbd_csrwonly = _RAND_51[0:0]; + wbd_bits_csrwonly = _RAND_51[0:0]; _RAND_52 = {1{`RANDOM}}; _T_465 = _RAND_52[31:0]; _RAND_53 = {1{`RANDOM}}; @@ -2470,9 +2470,9 @@ initial begin _RAND_70 = {1{`RANDOM}}; lsu_pmu_misaligned_r = _RAND_70[0:0]; _RAND_71 = {1{`RANDOM}}; - r_d_i0store = _RAND_71[0:0]; + r_d_bits_i0store = _RAND_71[0:0]; _RAND_72 = {1{`RANDOM}}; - r_d_i0div = _RAND_72[0:0]; + r_d_bits_i0div = _RAND_72[0:0]; _RAND_73 = {1{`RANDOM}}; i0_x_c_mul = _RAND_73[0:0]; _RAND_74 = {1{`RANDOM}}; @@ -2482,13 +2482,13 @@ initial begin _RAND_76 = {1{`RANDOM}}; i0_r_c_alu = _RAND_76[0:0]; _RAND_77 = {1{`RANDOM}}; - x_d_i0store = _RAND_77[0:0]; + x_d_bits_i0store = _RAND_77[0:0]; _RAND_78 = {1{`RANDOM}}; - x_d_i0div = _RAND_78[0:0]; + x_d_bits_i0div = _RAND_78[0:0]; _RAND_79 = {1{`RANDOM}}; - x_d_csrwen = _RAND_79[0:0]; + x_d_bits_csrwen = _RAND_79[0:0]; _RAND_80 = {1{`RANDOM}}; - x_d_csrwaddr = _RAND_80[11:0]; + x_d_bits_csrwaddr = _RAND_80[11:0]; _RAND_81 = {1{`RANDOM}}; last_br_immed_x = _RAND_81[11:0]; _RAND_82 = {1{`RANDOM}}; @@ -2532,7 +2532,7 @@ initial begin postsync_stall = 1'h0; end if (reset) begin - x_d_i0valid = 1'h0; + x_d_valid = 1'h0; end if (reset) begin flush_final_r = 1'h0; @@ -2541,34 +2541,34 @@ initial begin illegal_lockout = 1'h0; end if (reset) begin - cam_raw_0_tag = 3'h0; + cam_raw_0_bits_tag = 3'h0; end if (reset) begin cam_raw_0_valid = 1'h0; end if (reset) begin - cam_raw_1_tag = 3'h0; + cam_raw_1_bits_tag = 3'h0; end if (reset) begin cam_raw_1_valid = 1'h0; end if (reset) begin - cam_raw_2_tag = 3'h0; + cam_raw_2_bits_tag = 3'h0; end if (reset) begin cam_raw_2_valid = 1'h0; end if (reset) begin - cam_raw_3_tag = 3'h0; + cam_raw_3_bits_tag = 3'h0; end if (reset) begin cam_raw_3_valid = 1'h0; end if (reset) begin - x_d_i0load = 1'h0; + x_d_bits_i0load = 1'h0; end if (reset) begin - x_d_i0rd = 5'h0; + x_d_bits_i0rd = 5'h0; end if (reset) begin _T_701 = 3'h0; @@ -2577,37 +2577,37 @@ initial begin nonblock_load_valid_m_delay = 1'h0; end if (reset) begin - r_d_i0load = 1'h0; + r_d_bits_i0load = 1'h0; end if (reset) begin - r_d_i0v = 1'h0; + r_d_bits_i0v = 1'h0; end if (reset) begin - r_d_i0rd = 5'h0; + r_d_bits_i0rd = 5'h0; end if (reset) begin - cam_raw_0_rd = 5'h0; + cam_raw_0_bits_rd = 5'h0; end if (reset) begin - cam_raw_0_wb = 1'h0; + cam_raw_0_bits_wb = 1'h0; end if (reset) begin - cam_raw_1_rd = 5'h0; + cam_raw_1_bits_rd = 5'h0; end if (reset) begin - cam_raw_1_wb = 1'h0; + cam_raw_1_bits_wb = 1'h0; end if (reset) begin - cam_raw_2_rd = 5'h0; + cam_raw_2_bits_rd = 5'h0; end if (reset) begin - cam_raw_2_wb = 1'h0; + cam_raw_2_bits_wb = 1'h0; end if (reset) begin - cam_raw_3_rd = 5'h0; + cam_raw_3_bits_rd = 5'h0; end if (reset) begin - cam_raw_3_wb = 1'h0; + cam_raw_3_bits_wb = 1'h0; end if (reset) begin lsu_idle = 1'h0; @@ -2616,16 +2616,16 @@ initial begin _T_339 = 1'h0; end if (reset) begin - x_d_i0v = 1'h0; + x_d_bits_i0v = 1'h0; end if (reset) begin - r_d_csrwen = 1'h0; + r_d_bits_csrwen = 1'h0; end if (reset) begin - r_d_i0valid = 1'h0; + r_d_valid = 1'h0; end if (reset) begin - r_d_csrwaddr = 12'h0; + r_d_bits_csrwaddr = 12'h0; end if (reset) begin csr_read_x = 1'h0; @@ -2649,16 +2649,16 @@ initial begin csr_rddata_x = 32'h0; end if (reset) begin - r_d_csrwonly = 1'h0; + r_d_bits_csrwonly = 1'h0; end if (reset) begin i0_result_r_raw = 32'h0; end if (reset) begin - x_d_csrwonly = 1'h0; + x_d_bits_csrwonly = 1'h0; end if (reset) begin - wbd_csrwonly = 1'h0; + wbd_bits_csrwonly = 1'h0; end if (reset) begin _T_465 = 32'h0; @@ -2718,22 +2718,22 @@ initial begin lsu_pmu_misaligned_r = 1'h0; end if (reset) begin - r_d_i0store = 1'h0; + r_d_bits_i0store = 1'h0; end if (reset) begin - r_d_i0div = 1'h0; + r_d_bits_i0div = 1'h0; end if (reset) begin - x_d_i0store = 1'h0; + x_d_bits_i0store = 1'h0; end if (reset) begin - x_d_i0div = 1'h0; + x_d_bits_i0div = 1'h0; end if (reset) begin - x_d_csrwen = 1'h0; + x_d_bits_csrwen = 1'h0; end if (reset) begin - x_d_csrwaddr = 12'h0; + x_d_bits_csrwaddr = 12'h0; end if (reset) begin last_br_immed_x = 12'h0; @@ -2846,9 +2846,9 @@ end // initial end always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin - x_d_i0valid <= 1'h0; + x_d_valid <= 1'h0; end else begin - x_d_i0valid <= io_dec_i0_decode_d; + x_d_valid <= io_dec_i0_decode_d; end end always @(posedge rvclkhdr_io_l1clk or posedge reset) begin @@ -2867,11 +2867,11 @@ end // initial end always @(posedge io_free_clk or posedge reset) begin if (reset) begin - cam_raw_0_tag <= 3'h0; + cam_raw_0_bits_tag <= 3'h0; end else if (cam_wen[0]) begin - cam_raw_0_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m}; + cam_raw_0_bits_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m}; end else if (_T_107) begin - cam_raw_0_tag <= 3'h0; + cam_raw_0_bits_tag <= 3'h0; end end always @(posedge io_free_clk or posedge reset) begin @@ -2885,11 +2885,11 @@ end // initial end always @(posedge io_free_clk or posedge reset) begin if (reset) begin - cam_raw_1_tag <= 3'h0; + cam_raw_1_bits_tag <= 3'h0; end else if (cam_wen[1]) begin - cam_raw_1_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m}; + cam_raw_1_bits_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m}; end else if (_T_133) begin - cam_raw_1_tag <= 3'h0; + cam_raw_1_bits_tag <= 3'h0; end end always @(posedge io_free_clk or posedge reset) begin @@ -2903,11 +2903,11 @@ end // initial end always @(posedge io_free_clk or posedge reset) begin if (reset) begin - cam_raw_2_tag <= 3'h0; + cam_raw_2_bits_tag <= 3'h0; end else if (cam_wen[2]) begin - cam_raw_2_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m}; + cam_raw_2_bits_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m}; end else if (_T_159) begin - cam_raw_2_tag <= 3'h0; + cam_raw_2_bits_tag <= 3'h0; end end always @(posedge io_free_clk or posedge reset) begin @@ -2921,11 +2921,11 @@ end // initial end always @(posedge io_free_clk or posedge reset) begin if (reset) begin - cam_raw_3_tag <= 3'h0; + cam_raw_3_bits_tag <= 3'h0; end else if (cam_wen[3]) begin - cam_raw_3_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m}; + cam_raw_3_bits_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m}; end else if (_T_185) begin - cam_raw_3_tag <= 3'h0; + cam_raw_3_bits_tag <= 3'h0; end end always @(posedge io_free_clk or posedge reset) begin @@ -2939,16 +2939,16 @@ end // initial end always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin - x_d_i0load <= 1'h0; + x_d_bits_i0load <= 1'h0; end else begin - x_d_i0load <= i0_dp_load & i0_legal_decode_d; + x_d_bits_i0load <= i0_dp_load & i0_legal_decode_d; end end always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin - x_d_i0rd <= 5'h0; + x_d_bits_i0rd <= 5'h0; end else begin - x_d_i0rd <= io_dec_i0_instr_d[11:7]; + x_d_bits_i0rd <= io_dec_i0_instr_d[11:7]; end end always @(posedge io_active_clk or posedge reset) begin @@ -2967,103 +2967,103 @@ end // initial end always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin - r_d_i0load <= 1'h0; + r_d_bits_i0load <= 1'h0; end else begin - r_d_i0load <= x_d_i0load; + r_d_bits_i0load <= x_d_bits_i0load; end end always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin - r_d_i0v <= 1'h0; + r_d_bits_i0v <= 1'h0; end else begin - r_d_i0v <= _T_733 & _T_280; + r_d_bits_i0v <= _T_733 & _T_280; end end always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin - r_d_i0rd <= 5'h0; + r_d_bits_i0rd <= 5'h0; end else begin - r_d_i0rd <= x_d_i0rd; + r_d_bits_i0rd <= x_d_bits_i0rd; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin - cam_raw_0_rd <= 5'h0; + cam_raw_0_bits_rd <= 5'h0; end else if (cam_wen[0]) begin - if (x_d_i0load) begin - cam_raw_0_rd <= x_d_i0rd; + if (x_d_bits_i0load) begin + cam_raw_0_bits_rd <= x_d_bits_i0rd; end else begin - cam_raw_0_rd <= 5'h0; + cam_raw_0_bits_rd <= 5'h0; end end else if (_T_107) begin - cam_raw_0_rd <= 5'h0; + cam_raw_0_bits_rd <= 5'h0; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin - cam_raw_0_wb <= 1'h0; + cam_raw_0_bits_wb <= 1'h0; end else begin - cam_raw_0_wb <= _T_112 | _GEN_57; + cam_raw_0_bits_wb <= _T_112 | _GEN_57; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin - cam_raw_1_rd <= 5'h0; + cam_raw_1_bits_rd <= 5'h0; end else if (cam_wen[1]) begin - if (x_d_i0load) begin - cam_raw_1_rd <= x_d_i0rd; + if (x_d_bits_i0load) begin + cam_raw_1_bits_rd <= x_d_bits_i0rd; end else begin - cam_raw_1_rd <= 5'h0; + cam_raw_1_bits_rd <= 5'h0; end end else if (_T_133) begin - cam_raw_1_rd <= 5'h0; + cam_raw_1_bits_rd <= 5'h0; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin - cam_raw_1_wb <= 1'h0; + cam_raw_1_bits_wb <= 1'h0; end else begin - cam_raw_1_wb <= _T_138 | _GEN_68; + cam_raw_1_bits_wb <= _T_138 | _GEN_68; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin - cam_raw_2_rd <= 5'h0; + cam_raw_2_bits_rd <= 5'h0; end else if (cam_wen[2]) begin - if (x_d_i0load) begin - cam_raw_2_rd <= x_d_i0rd; + if (x_d_bits_i0load) begin + cam_raw_2_bits_rd <= x_d_bits_i0rd; end else begin - cam_raw_2_rd <= 5'h0; + cam_raw_2_bits_rd <= 5'h0; end end else if (_T_159) begin - cam_raw_2_rd <= 5'h0; + cam_raw_2_bits_rd <= 5'h0; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin - cam_raw_2_wb <= 1'h0; + cam_raw_2_bits_wb <= 1'h0; end else begin - cam_raw_2_wb <= _T_164 | _GEN_79; + cam_raw_2_bits_wb <= _T_164 | _GEN_79; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin - cam_raw_3_rd <= 5'h0; + cam_raw_3_bits_rd <= 5'h0; end else if (cam_wen[3]) begin - if (x_d_i0load) begin - cam_raw_3_rd <= x_d_i0rd; + if (x_d_bits_i0load) begin + cam_raw_3_bits_rd <= x_d_bits_i0rd; end else begin - cam_raw_3_rd <= 5'h0; + cam_raw_3_bits_rd <= 5'h0; end end else if (_T_185) begin - cam_raw_3_rd <= 5'h0; + cam_raw_3_bits_rd <= 5'h0; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin - cam_raw_3_wb <= 1'h0; + cam_raw_3_bits_wb <= 1'h0; end else begin - cam_raw_3_wb <= _T_190 | _GEN_90; + cam_raw_3_bits_wb <= _T_190 | _GEN_90; end end always @(posedge io_active_clk or posedge reset) begin @@ -3082,30 +3082,30 @@ end // initial end always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin - x_d_i0v <= 1'h0; + x_d_bits_i0v <= 1'h0; end else begin - x_d_i0v <= i0_rd_en_d & i0_legal_decode_d; + x_d_bits_i0v <= i0_rd_en_d & i0_legal_decode_d; end end always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin - r_d_csrwen <= 1'h0; + r_d_bits_csrwen <= 1'h0; end else begin - r_d_csrwen <= x_d_csrwen; + r_d_bits_csrwen <= x_d_bits_csrwen; end end always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin - r_d_i0valid <= 1'h0; + r_d_valid <= 1'h0; end else begin - r_d_i0valid <= _T_737 & _T_280; + r_d_valid <= _T_737 & _T_280; end end always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin - r_d_csrwaddr <= 12'h0; + r_d_bits_csrwaddr <= 12'h0; end else begin - r_d_csrwaddr <= x_d_csrwaddr; + r_d_bits_csrwaddr <= x_d_bits_csrwaddr; end end always @(posedge io_active_clk or posedge reset) begin @@ -3161,9 +3161,9 @@ end // initial end always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin - r_d_csrwonly <= 1'h0; + r_d_bits_csrwonly <= 1'h0; end else begin - r_d_csrwonly <= x_d_csrwonly; + r_d_bits_csrwonly <= x_d_bits_csrwonly; end end always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin @@ -3177,16 +3177,16 @@ end // initial end always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin - x_d_csrwonly <= 1'h0; + x_d_bits_csrwonly <= 1'h0; end else begin - x_d_csrwonly <= i0_csr_write_only_d & io_dec_i0_decode_d; + x_d_bits_csrwonly <= i0_csr_write_only_d & io_dec_i0_decode_d; end end always @(posedge rvclkhdr_9_io_l1clk or posedge reset) begin if (reset) begin - wbd_csrwonly <= 1'h0; + wbd_bits_csrwonly <= 1'h0; end else begin - wbd_csrwonly <= r_d_csrwonly; + wbd_bits_csrwonly <= r_d_bits_csrwonly; end end always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin @@ -3326,44 +3326,44 @@ end // initial end always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin - r_d_i0store <= 1'h0; + r_d_bits_i0store <= 1'h0; end else begin - r_d_i0store <= x_d_i0store; + r_d_bits_i0store <= x_d_bits_i0store; end end always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin - r_d_i0div <= 1'h0; + r_d_bits_i0div <= 1'h0; end else begin - r_d_i0div <= x_d_i0div; + r_d_bits_i0div <= x_d_bits_i0div; end end always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin - x_d_i0store <= 1'h0; + x_d_bits_i0store <= 1'h0; end else begin - x_d_i0store <= i0_dp_store & i0_legal_decode_d; + x_d_bits_i0store <= i0_dp_store & i0_legal_decode_d; end end always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin - x_d_i0div <= 1'h0; + x_d_bits_i0div <= 1'h0; end else begin - x_d_i0div <= i0_dp_div & i0_legal_decode_d; + x_d_bits_i0div <= i0_dp_div & i0_legal_decode_d; end end always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin - x_d_csrwen <= 1'h0; + x_d_bits_csrwen <= 1'h0; end else begin - x_d_csrwen <= io_dec_csr_wen_unq_d & i0_legal_decode_d; + x_d_bits_csrwen <= io_dec_csr_wen_unq_d & i0_legal_decode_d; end end always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin - x_d_csrwaddr <= 12'h0; + x_d_bits_csrwaddr <= 12'h0; end else begin - x_d_csrwaddr <= io_dec_i0_instr_d[31:20]; + x_d_bits_csrwaddr <= io_dec_i0_instr_d[31:20]; end end always @(posedge rvclkhdr_11_io_l1clk or posedge reset) begin @@ -12777,7 +12777,6 @@ module el2_dec( input io_ifu_i0_dbecc, input io_lsu_idle_any, input io_i0_brp_valid, - input io_i0_brp_bits_valid, input [11:0] io_i0_brp_bits_toffset, input [1:0] io_i0_brp_bits_hist, input io_i0_brp_bits_br_error, diff --git a/el2_dec_gpr_ctl.anno.json b/el2_dec_gpr_ctl.anno.json new file mode 100644 index 00000000..3a51c0de --- /dev/null +++ b/el2_dec_gpr_ctl.anno.json @@ -0,0 +1,43 @@ +[ + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_gpr_ctl|el2_dec_gpr_ctl>io_rd1", + "sources":[ + "~el2_dec_gpr_ctl|el2_dec_gpr_ctl>io_raddr1" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_gpr_ctl|el2_dec_gpr_ctl>io_rd0", + "sources":[ + "~el2_dec_gpr_ctl|el2_dec_gpr_ctl>io_raddr0" + ] + }, + { + "class":"logger.LogLevelAnnotation", + "globalLogLevel":{ + + } + }, + { + "class":"firrtl.EmitCircuitAnnotation", + "emitter":"firrtl.VerilogEmitter" + }, + { + "class":"firrtl.transforms.BlackBoxResourceAnno", + "target":"el2_dec_gpr_ctl.gated_latch", + "resourceId":"/vsrc/gated_latch.v" + }, + { + "class":"firrtl.options.TargetDirAnnotation", + "directory":"." + }, + { + "class":"firrtl.options.OutputAnnotationFileAnnotation", + "file":"el2_dec_gpr_ctl" + }, + { + "class":"firrtl.transforms.BlackBoxTargetDirAnno", + "targetDir":"." + } +] \ No newline at end of file diff --git a/el2_dec_gpr_ctl.fir b/el2_dec_gpr_ctl.fir new file mode 100644 index 00000000..a56c3608 --- /dev/null +++ b/el2_dec_gpr_ctl.fir @@ -0,0 +1,2235 @@ +;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 +circuit el2_dec_gpr_ctl : + extmodule gated_latch : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_1 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_1 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_1 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_2 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_2 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_2 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_3 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_3 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_3 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_4 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_4 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_4 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_5 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_5 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_5 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_6 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_6 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_6 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_7 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_7 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_7 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_8 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_8 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_8 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_9 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_9 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_9 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_10 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_10 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_10 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_11 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_11 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_11 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_12 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_12 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_12 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_13 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_13 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_13 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_14 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_14 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_14 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_15 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_15 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_15 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_16 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_16 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_16 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_17 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_17 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_17 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_18 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_18 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_18 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_19 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_19 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_19 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_20 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_20 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_20 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_21 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_21 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_21 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_22 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_22 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_22 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_23 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_23 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_23 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_24 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_24 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_24 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_25 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_25 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_25 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_26 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_26 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_26 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_27 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_27 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_27 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_28 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_28 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_28 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_29 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_29 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_29 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_30 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_30 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_30 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + module el2_dec_gpr_ctl : + input clock : Clock + input reset : AsyncReset + output io : {flip raddr0 : UInt<5>, flip raddr1 : UInt<5>, flip wen0 : UInt<1>, flip waddr0 : UInt<5>, flip wd0 : UInt<32>, flip wen1 : UInt<1>, flip waddr1 : UInt<5>, flip wd1 : UInt<32>, flip wen2 : UInt<1>, flip waddr2 : UInt<5>, flip wd2 : UInt<32>, rd0 : UInt<32>, rd1 : UInt<32>, flip scan_mode : UInt<1>} + + wire w0v : UInt<1>[32] @[el2_dec_gpr_ctl.scala 10:30] + w0v[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[1] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[2] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[3] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[4] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[5] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[6] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[7] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[8] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[9] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[10] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[11] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[12] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[13] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[14] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[15] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[16] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[17] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[18] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[19] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[20] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[21] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[22] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[23] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[24] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[25] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[26] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[27] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[28] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[29] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[30] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[31] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + wire w1v : UInt<1>[32] @[el2_dec_gpr_ctl.scala 13:30] + w1v[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[1] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[2] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[3] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[4] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[5] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[6] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[7] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[8] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[9] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[10] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[11] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[12] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[13] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[14] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[15] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[16] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[17] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[18] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[19] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[20] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[21] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[22] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[23] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[24] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[25] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[26] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[27] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[28] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[29] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[30] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[31] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + wire w2v : UInt<1>[32] @[el2_dec_gpr_ctl.scala 16:30] + w2v[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[1] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[2] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[3] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[4] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[5] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[6] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[7] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[8] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[9] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[10] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[11] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[12] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[13] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[14] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[15] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[16] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[17] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[18] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[19] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[20] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[21] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[22] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[23] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[24] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[25] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[26] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[27] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[28] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[29] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[30] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[31] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + wire gpr_in : UInt<32>[32] @[el2_dec_gpr_ctl.scala 19:22] + gpr_in[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[1] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[2] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[3] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[4] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[5] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[6] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[7] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[8] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[9] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[10] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[11] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[12] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[13] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[14] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[15] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[16] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[17] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[18] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[19] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[20] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[21] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[22] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[23] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[24] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[25] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[26] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[27] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[28] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[29] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[30] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[31] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + wire gpr_out : UInt<32>[32] @[el2_dec_gpr_ctl.scala 22:22] + gpr_out[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[1] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[2] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[3] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[4] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[5] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[6] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[7] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[8] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[9] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[10] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[11] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[12] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[13] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[14] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[15] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[16] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[17] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[18] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[19] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[20] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[21] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[22] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[23] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[24] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[25] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[26] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[27] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[28] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[29] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[30] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[31] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + wire gpr_wr_en : UInt<32> + gpr_wr_en <= UInt<1>("h00") + w0v[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 26:9] + w1v[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 27:9] + w2v[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 28:9] + gpr_out[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 29:13] + gpr_in[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 30:12] + io.rd0 <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 31:9] + io.rd1 <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 32:9] + node _T = eq(io.waddr0, UInt<1>("h01")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_1 = and(io.wen0, _T) @[el2_dec_gpr_ctl.scala 35:28] + w0v[1] <= _T_1 @[el2_dec_gpr_ctl.scala 35:16] + node _T_2 = eq(io.waddr1, UInt<1>("h01")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_3 = and(io.wen1, _T_2) @[el2_dec_gpr_ctl.scala 36:28] + w1v[1] <= _T_3 @[el2_dec_gpr_ctl.scala 36:16] + node _T_4 = eq(io.waddr2, UInt<1>("h01")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_5 = and(io.wen2, _T_4) @[el2_dec_gpr_ctl.scala 37:28] + w2v[1] <= _T_5 @[el2_dec_gpr_ctl.scala 37:16] + node _T_6 = bits(w0v[1], 0, 0) @[Bitwise.scala 72:15] + node _T_7 = mux(_T_6, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_8 = and(_T_7, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_9 = bits(w1v[1], 0, 0) @[Bitwise.scala 72:15] + node _T_10 = mux(_T_9, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_11 = and(_T_10, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_12 = or(_T_8, _T_11) @[el2_dec_gpr_ctl.scala 38:47] + node _T_13 = bits(w2v[1], 0, 0) @[Bitwise.scala 72:15] + node _T_14 = mux(_T_13, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_15 = and(_T_14, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_16 = or(_T_12, _T_15) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[1] <= _T_16 @[el2_dec_gpr_ctl.scala 38:16] + node _T_17 = eq(io.waddr0, UInt<2>("h02")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_18 = and(io.wen0, _T_17) @[el2_dec_gpr_ctl.scala 35:28] + w0v[2] <= _T_18 @[el2_dec_gpr_ctl.scala 35:16] + node _T_19 = eq(io.waddr1, UInt<2>("h02")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_20 = and(io.wen1, _T_19) @[el2_dec_gpr_ctl.scala 36:28] + w1v[2] <= _T_20 @[el2_dec_gpr_ctl.scala 36:16] + node _T_21 = eq(io.waddr2, UInt<2>("h02")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_22 = and(io.wen2, _T_21) @[el2_dec_gpr_ctl.scala 37:28] + w2v[2] <= _T_22 @[el2_dec_gpr_ctl.scala 37:16] + node _T_23 = bits(w0v[2], 0, 0) @[Bitwise.scala 72:15] + node _T_24 = mux(_T_23, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_25 = and(_T_24, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_26 = bits(w1v[2], 0, 0) @[Bitwise.scala 72:15] + node _T_27 = mux(_T_26, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_28 = and(_T_27, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_29 = or(_T_25, _T_28) @[el2_dec_gpr_ctl.scala 38:47] + node _T_30 = bits(w2v[2], 0, 0) @[Bitwise.scala 72:15] + node _T_31 = mux(_T_30, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_32 = and(_T_31, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_33 = or(_T_29, _T_32) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[2] <= _T_33 @[el2_dec_gpr_ctl.scala 38:16] + node _T_34 = eq(io.waddr0, UInt<2>("h03")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_35 = and(io.wen0, _T_34) @[el2_dec_gpr_ctl.scala 35:28] + w0v[3] <= _T_35 @[el2_dec_gpr_ctl.scala 35:16] + node _T_36 = eq(io.waddr1, UInt<2>("h03")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_37 = and(io.wen1, _T_36) @[el2_dec_gpr_ctl.scala 36:28] + w1v[3] <= _T_37 @[el2_dec_gpr_ctl.scala 36:16] + node _T_38 = eq(io.waddr2, UInt<2>("h03")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_39 = and(io.wen2, _T_38) @[el2_dec_gpr_ctl.scala 37:28] + w2v[3] <= _T_39 @[el2_dec_gpr_ctl.scala 37:16] + node _T_40 = bits(w0v[3], 0, 0) @[Bitwise.scala 72:15] + node _T_41 = mux(_T_40, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_42 = and(_T_41, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_43 = bits(w1v[3], 0, 0) @[Bitwise.scala 72:15] + node _T_44 = mux(_T_43, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_45 = and(_T_44, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_46 = or(_T_42, _T_45) @[el2_dec_gpr_ctl.scala 38:47] + node _T_47 = bits(w2v[3], 0, 0) @[Bitwise.scala 72:15] + node _T_48 = mux(_T_47, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_49 = and(_T_48, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_50 = or(_T_46, _T_49) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[3] <= _T_50 @[el2_dec_gpr_ctl.scala 38:16] + node _T_51 = eq(io.waddr0, UInt<3>("h04")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_52 = and(io.wen0, _T_51) @[el2_dec_gpr_ctl.scala 35:28] + w0v[4] <= _T_52 @[el2_dec_gpr_ctl.scala 35:16] + node _T_53 = eq(io.waddr1, UInt<3>("h04")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_54 = and(io.wen1, _T_53) @[el2_dec_gpr_ctl.scala 36:28] + w1v[4] <= _T_54 @[el2_dec_gpr_ctl.scala 36:16] + node _T_55 = eq(io.waddr2, UInt<3>("h04")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_56 = and(io.wen2, _T_55) @[el2_dec_gpr_ctl.scala 37:28] + w2v[4] <= _T_56 @[el2_dec_gpr_ctl.scala 37:16] + node _T_57 = bits(w0v[4], 0, 0) @[Bitwise.scala 72:15] + node _T_58 = mux(_T_57, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_59 = and(_T_58, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_60 = bits(w1v[4], 0, 0) @[Bitwise.scala 72:15] + node _T_61 = mux(_T_60, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_62 = and(_T_61, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_63 = or(_T_59, _T_62) @[el2_dec_gpr_ctl.scala 38:47] + node _T_64 = bits(w2v[4], 0, 0) @[Bitwise.scala 72:15] + node _T_65 = mux(_T_64, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_66 = and(_T_65, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_67 = or(_T_63, _T_66) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[4] <= _T_67 @[el2_dec_gpr_ctl.scala 38:16] + node _T_68 = eq(io.waddr0, UInt<3>("h05")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_69 = and(io.wen0, _T_68) @[el2_dec_gpr_ctl.scala 35:28] + w0v[5] <= _T_69 @[el2_dec_gpr_ctl.scala 35:16] + node _T_70 = eq(io.waddr1, UInt<3>("h05")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_71 = and(io.wen1, _T_70) @[el2_dec_gpr_ctl.scala 36:28] + w1v[5] <= _T_71 @[el2_dec_gpr_ctl.scala 36:16] + node _T_72 = eq(io.waddr2, UInt<3>("h05")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_73 = and(io.wen2, _T_72) @[el2_dec_gpr_ctl.scala 37:28] + w2v[5] <= _T_73 @[el2_dec_gpr_ctl.scala 37:16] + node _T_74 = bits(w0v[5], 0, 0) @[Bitwise.scala 72:15] + node _T_75 = mux(_T_74, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_76 = and(_T_75, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_77 = bits(w1v[5], 0, 0) @[Bitwise.scala 72:15] + node _T_78 = mux(_T_77, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_79 = and(_T_78, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_80 = or(_T_76, _T_79) @[el2_dec_gpr_ctl.scala 38:47] + node _T_81 = bits(w2v[5], 0, 0) @[Bitwise.scala 72:15] + node _T_82 = mux(_T_81, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_83 = and(_T_82, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_84 = or(_T_80, _T_83) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[5] <= _T_84 @[el2_dec_gpr_ctl.scala 38:16] + node _T_85 = eq(io.waddr0, UInt<3>("h06")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_86 = and(io.wen0, _T_85) @[el2_dec_gpr_ctl.scala 35:28] + w0v[6] <= _T_86 @[el2_dec_gpr_ctl.scala 35:16] + node _T_87 = eq(io.waddr1, UInt<3>("h06")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_88 = and(io.wen1, _T_87) @[el2_dec_gpr_ctl.scala 36:28] + w1v[6] <= _T_88 @[el2_dec_gpr_ctl.scala 36:16] + node _T_89 = eq(io.waddr2, UInt<3>("h06")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_90 = and(io.wen2, _T_89) @[el2_dec_gpr_ctl.scala 37:28] + w2v[6] <= _T_90 @[el2_dec_gpr_ctl.scala 37:16] + node _T_91 = bits(w0v[6], 0, 0) @[Bitwise.scala 72:15] + node _T_92 = mux(_T_91, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_93 = and(_T_92, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_94 = bits(w1v[6], 0, 0) @[Bitwise.scala 72:15] + node _T_95 = mux(_T_94, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_96 = and(_T_95, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_97 = or(_T_93, _T_96) @[el2_dec_gpr_ctl.scala 38:47] + node _T_98 = bits(w2v[6], 0, 0) @[Bitwise.scala 72:15] + node _T_99 = mux(_T_98, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_100 = and(_T_99, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_101 = or(_T_97, _T_100) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[6] <= _T_101 @[el2_dec_gpr_ctl.scala 38:16] + node _T_102 = eq(io.waddr0, UInt<3>("h07")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_103 = and(io.wen0, _T_102) @[el2_dec_gpr_ctl.scala 35:28] + w0v[7] <= _T_103 @[el2_dec_gpr_ctl.scala 35:16] + node _T_104 = eq(io.waddr1, UInt<3>("h07")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_105 = and(io.wen1, _T_104) @[el2_dec_gpr_ctl.scala 36:28] + w1v[7] <= _T_105 @[el2_dec_gpr_ctl.scala 36:16] + node _T_106 = eq(io.waddr2, UInt<3>("h07")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_107 = and(io.wen2, _T_106) @[el2_dec_gpr_ctl.scala 37:28] + w2v[7] <= _T_107 @[el2_dec_gpr_ctl.scala 37:16] + node _T_108 = bits(w0v[7], 0, 0) @[Bitwise.scala 72:15] + node _T_109 = mux(_T_108, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_110 = and(_T_109, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_111 = bits(w1v[7], 0, 0) @[Bitwise.scala 72:15] + node _T_112 = mux(_T_111, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_113 = and(_T_112, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_114 = or(_T_110, _T_113) @[el2_dec_gpr_ctl.scala 38:47] + node _T_115 = bits(w2v[7], 0, 0) @[Bitwise.scala 72:15] + node _T_116 = mux(_T_115, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_117 = and(_T_116, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_118 = or(_T_114, _T_117) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[7] <= _T_118 @[el2_dec_gpr_ctl.scala 38:16] + node _T_119 = eq(io.waddr0, UInt<4>("h08")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_120 = and(io.wen0, _T_119) @[el2_dec_gpr_ctl.scala 35:28] + w0v[8] <= _T_120 @[el2_dec_gpr_ctl.scala 35:16] + node _T_121 = eq(io.waddr1, UInt<4>("h08")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_122 = and(io.wen1, _T_121) @[el2_dec_gpr_ctl.scala 36:28] + w1v[8] <= _T_122 @[el2_dec_gpr_ctl.scala 36:16] + node _T_123 = eq(io.waddr2, UInt<4>("h08")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_124 = and(io.wen2, _T_123) @[el2_dec_gpr_ctl.scala 37:28] + w2v[8] <= _T_124 @[el2_dec_gpr_ctl.scala 37:16] + node _T_125 = bits(w0v[8], 0, 0) @[Bitwise.scala 72:15] + node _T_126 = mux(_T_125, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_127 = and(_T_126, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_128 = bits(w1v[8], 0, 0) @[Bitwise.scala 72:15] + node _T_129 = mux(_T_128, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_130 = and(_T_129, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_131 = or(_T_127, _T_130) @[el2_dec_gpr_ctl.scala 38:47] + node _T_132 = bits(w2v[8], 0, 0) @[Bitwise.scala 72:15] + node _T_133 = mux(_T_132, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_134 = and(_T_133, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_135 = or(_T_131, _T_134) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[8] <= _T_135 @[el2_dec_gpr_ctl.scala 38:16] + node _T_136 = eq(io.waddr0, UInt<4>("h09")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_137 = and(io.wen0, _T_136) @[el2_dec_gpr_ctl.scala 35:28] + w0v[9] <= _T_137 @[el2_dec_gpr_ctl.scala 35:16] + node _T_138 = eq(io.waddr1, UInt<4>("h09")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_139 = and(io.wen1, _T_138) @[el2_dec_gpr_ctl.scala 36:28] + w1v[9] <= _T_139 @[el2_dec_gpr_ctl.scala 36:16] + node _T_140 = eq(io.waddr2, UInt<4>("h09")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_141 = and(io.wen2, _T_140) @[el2_dec_gpr_ctl.scala 37:28] + w2v[9] <= _T_141 @[el2_dec_gpr_ctl.scala 37:16] + node _T_142 = bits(w0v[9], 0, 0) @[Bitwise.scala 72:15] + node _T_143 = mux(_T_142, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_144 = and(_T_143, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_145 = bits(w1v[9], 0, 0) @[Bitwise.scala 72:15] + node _T_146 = mux(_T_145, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_147 = and(_T_146, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_148 = or(_T_144, _T_147) @[el2_dec_gpr_ctl.scala 38:47] + node _T_149 = bits(w2v[9], 0, 0) @[Bitwise.scala 72:15] + node _T_150 = mux(_T_149, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_151 = and(_T_150, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_152 = or(_T_148, _T_151) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[9] <= _T_152 @[el2_dec_gpr_ctl.scala 38:16] + node _T_153 = eq(io.waddr0, UInt<4>("h0a")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_154 = and(io.wen0, _T_153) @[el2_dec_gpr_ctl.scala 35:28] + w0v[10] <= _T_154 @[el2_dec_gpr_ctl.scala 35:16] + node _T_155 = eq(io.waddr1, UInt<4>("h0a")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_156 = and(io.wen1, _T_155) @[el2_dec_gpr_ctl.scala 36:28] + w1v[10] <= _T_156 @[el2_dec_gpr_ctl.scala 36:16] + node _T_157 = eq(io.waddr2, UInt<4>("h0a")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_158 = and(io.wen2, _T_157) @[el2_dec_gpr_ctl.scala 37:28] + w2v[10] <= _T_158 @[el2_dec_gpr_ctl.scala 37:16] + node _T_159 = bits(w0v[10], 0, 0) @[Bitwise.scala 72:15] + node _T_160 = mux(_T_159, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_161 = and(_T_160, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_162 = bits(w1v[10], 0, 0) @[Bitwise.scala 72:15] + node _T_163 = mux(_T_162, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_164 = and(_T_163, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_165 = or(_T_161, _T_164) @[el2_dec_gpr_ctl.scala 38:47] + node _T_166 = bits(w2v[10], 0, 0) @[Bitwise.scala 72:15] + node _T_167 = mux(_T_166, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_168 = and(_T_167, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_169 = or(_T_165, _T_168) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[10] <= _T_169 @[el2_dec_gpr_ctl.scala 38:16] + node _T_170 = eq(io.waddr0, UInt<4>("h0b")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_171 = and(io.wen0, _T_170) @[el2_dec_gpr_ctl.scala 35:28] + w0v[11] <= _T_171 @[el2_dec_gpr_ctl.scala 35:16] + node _T_172 = eq(io.waddr1, UInt<4>("h0b")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_173 = and(io.wen1, _T_172) @[el2_dec_gpr_ctl.scala 36:28] + w1v[11] <= _T_173 @[el2_dec_gpr_ctl.scala 36:16] + node _T_174 = eq(io.waddr2, UInt<4>("h0b")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_175 = and(io.wen2, _T_174) @[el2_dec_gpr_ctl.scala 37:28] + w2v[11] <= _T_175 @[el2_dec_gpr_ctl.scala 37:16] + node _T_176 = bits(w0v[11], 0, 0) @[Bitwise.scala 72:15] + node _T_177 = mux(_T_176, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_178 = and(_T_177, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_179 = bits(w1v[11], 0, 0) @[Bitwise.scala 72:15] + node _T_180 = mux(_T_179, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_181 = and(_T_180, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_182 = or(_T_178, _T_181) @[el2_dec_gpr_ctl.scala 38:47] + node _T_183 = bits(w2v[11], 0, 0) @[Bitwise.scala 72:15] + node _T_184 = mux(_T_183, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_185 = and(_T_184, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_186 = or(_T_182, _T_185) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[11] <= _T_186 @[el2_dec_gpr_ctl.scala 38:16] + node _T_187 = eq(io.waddr0, UInt<4>("h0c")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_188 = and(io.wen0, _T_187) @[el2_dec_gpr_ctl.scala 35:28] + w0v[12] <= _T_188 @[el2_dec_gpr_ctl.scala 35:16] + node _T_189 = eq(io.waddr1, UInt<4>("h0c")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_190 = and(io.wen1, _T_189) @[el2_dec_gpr_ctl.scala 36:28] + w1v[12] <= _T_190 @[el2_dec_gpr_ctl.scala 36:16] + node _T_191 = eq(io.waddr2, UInt<4>("h0c")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_192 = and(io.wen2, _T_191) @[el2_dec_gpr_ctl.scala 37:28] + w2v[12] <= _T_192 @[el2_dec_gpr_ctl.scala 37:16] + node _T_193 = bits(w0v[12], 0, 0) @[Bitwise.scala 72:15] + node _T_194 = mux(_T_193, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_195 = and(_T_194, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_196 = bits(w1v[12], 0, 0) @[Bitwise.scala 72:15] + node _T_197 = mux(_T_196, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_198 = and(_T_197, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_199 = or(_T_195, _T_198) @[el2_dec_gpr_ctl.scala 38:47] + node _T_200 = bits(w2v[12], 0, 0) @[Bitwise.scala 72:15] + node _T_201 = mux(_T_200, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_202 = and(_T_201, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_203 = or(_T_199, _T_202) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[12] <= _T_203 @[el2_dec_gpr_ctl.scala 38:16] + node _T_204 = eq(io.waddr0, UInt<4>("h0d")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_205 = and(io.wen0, _T_204) @[el2_dec_gpr_ctl.scala 35:28] + w0v[13] <= _T_205 @[el2_dec_gpr_ctl.scala 35:16] + node _T_206 = eq(io.waddr1, UInt<4>("h0d")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_207 = and(io.wen1, _T_206) @[el2_dec_gpr_ctl.scala 36:28] + w1v[13] <= _T_207 @[el2_dec_gpr_ctl.scala 36:16] + node _T_208 = eq(io.waddr2, UInt<4>("h0d")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_209 = and(io.wen2, _T_208) @[el2_dec_gpr_ctl.scala 37:28] + w2v[13] <= _T_209 @[el2_dec_gpr_ctl.scala 37:16] + node _T_210 = bits(w0v[13], 0, 0) @[Bitwise.scala 72:15] + node _T_211 = mux(_T_210, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_212 = and(_T_211, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_213 = bits(w1v[13], 0, 0) @[Bitwise.scala 72:15] + node _T_214 = mux(_T_213, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_215 = and(_T_214, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_216 = or(_T_212, _T_215) @[el2_dec_gpr_ctl.scala 38:47] + node _T_217 = bits(w2v[13], 0, 0) @[Bitwise.scala 72:15] + node _T_218 = mux(_T_217, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_219 = and(_T_218, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_220 = or(_T_216, _T_219) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[13] <= _T_220 @[el2_dec_gpr_ctl.scala 38:16] + node _T_221 = eq(io.waddr0, UInt<4>("h0e")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_222 = and(io.wen0, _T_221) @[el2_dec_gpr_ctl.scala 35:28] + w0v[14] <= _T_222 @[el2_dec_gpr_ctl.scala 35:16] + node _T_223 = eq(io.waddr1, UInt<4>("h0e")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_224 = and(io.wen1, _T_223) @[el2_dec_gpr_ctl.scala 36:28] + w1v[14] <= _T_224 @[el2_dec_gpr_ctl.scala 36:16] + node _T_225 = eq(io.waddr2, UInt<4>("h0e")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_226 = and(io.wen2, _T_225) @[el2_dec_gpr_ctl.scala 37:28] + w2v[14] <= _T_226 @[el2_dec_gpr_ctl.scala 37:16] + node _T_227 = bits(w0v[14], 0, 0) @[Bitwise.scala 72:15] + node _T_228 = mux(_T_227, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_229 = and(_T_228, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_230 = bits(w1v[14], 0, 0) @[Bitwise.scala 72:15] + node _T_231 = mux(_T_230, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_232 = and(_T_231, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_233 = or(_T_229, _T_232) @[el2_dec_gpr_ctl.scala 38:47] + node _T_234 = bits(w2v[14], 0, 0) @[Bitwise.scala 72:15] + node _T_235 = mux(_T_234, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_236 = and(_T_235, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_237 = or(_T_233, _T_236) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[14] <= _T_237 @[el2_dec_gpr_ctl.scala 38:16] + node _T_238 = eq(io.waddr0, UInt<4>("h0f")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_239 = and(io.wen0, _T_238) @[el2_dec_gpr_ctl.scala 35:28] + w0v[15] <= _T_239 @[el2_dec_gpr_ctl.scala 35:16] + node _T_240 = eq(io.waddr1, UInt<4>("h0f")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_241 = and(io.wen1, _T_240) @[el2_dec_gpr_ctl.scala 36:28] + w1v[15] <= _T_241 @[el2_dec_gpr_ctl.scala 36:16] + node _T_242 = eq(io.waddr2, UInt<4>("h0f")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_243 = and(io.wen2, _T_242) @[el2_dec_gpr_ctl.scala 37:28] + w2v[15] <= _T_243 @[el2_dec_gpr_ctl.scala 37:16] + node _T_244 = bits(w0v[15], 0, 0) @[Bitwise.scala 72:15] + node _T_245 = mux(_T_244, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_246 = and(_T_245, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_247 = bits(w1v[15], 0, 0) @[Bitwise.scala 72:15] + node _T_248 = mux(_T_247, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_249 = and(_T_248, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_250 = or(_T_246, _T_249) @[el2_dec_gpr_ctl.scala 38:47] + node _T_251 = bits(w2v[15], 0, 0) @[Bitwise.scala 72:15] + node _T_252 = mux(_T_251, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_253 = and(_T_252, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_254 = or(_T_250, _T_253) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[15] <= _T_254 @[el2_dec_gpr_ctl.scala 38:16] + node _T_255 = eq(io.waddr0, UInt<5>("h010")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_256 = and(io.wen0, _T_255) @[el2_dec_gpr_ctl.scala 35:28] + w0v[16] <= _T_256 @[el2_dec_gpr_ctl.scala 35:16] + node _T_257 = eq(io.waddr1, UInt<5>("h010")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_258 = and(io.wen1, _T_257) @[el2_dec_gpr_ctl.scala 36:28] + w1v[16] <= _T_258 @[el2_dec_gpr_ctl.scala 36:16] + node _T_259 = eq(io.waddr2, UInt<5>("h010")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_260 = and(io.wen2, _T_259) @[el2_dec_gpr_ctl.scala 37:28] + w2v[16] <= _T_260 @[el2_dec_gpr_ctl.scala 37:16] + node _T_261 = bits(w0v[16], 0, 0) @[Bitwise.scala 72:15] + node _T_262 = mux(_T_261, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_263 = and(_T_262, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_264 = bits(w1v[16], 0, 0) @[Bitwise.scala 72:15] + node _T_265 = mux(_T_264, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_266 = and(_T_265, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_267 = or(_T_263, _T_266) @[el2_dec_gpr_ctl.scala 38:47] + node _T_268 = bits(w2v[16], 0, 0) @[Bitwise.scala 72:15] + node _T_269 = mux(_T_268, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_270 = and(_T_269, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_271 = or(_T_267, _T_270) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[16] <= _T_271 @[el2_dec_gpr_ctl.scala 38:16] + node _T_272 = eq(io.waddr0, UInt<5>("h011")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_273 = and(io.wen0, _T_272) @[el2_dec_gpr_ctl.scala 35:28] + w0v[17] <= _T_273 @[el2_dec_gpr_ctl.scala 35:16] + node _T_274 = eq(io.waddr1, UInt<5>("h011")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_275 = and(io.wen1, _T_274) @[el2_dec_gpr_ctl.scala 36:28] + w1v[17] <= _T_275 @[el2_dec_gpr_ctl.scala 36:16] + node _T_276 = eq(io.waddr2, UInt<5>("h011")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_277 = and(io.wen2, _T_276) @[el2_dec_gpr_ctl.scala 37:28] + w2v[17] <= _T_277 @[el2_dec_gpr_ctl.scala 37:16] + node _T_278 = bits(w0v[17], 0, 0) @[Bitwise.scala 72:15] + node _T_279 = mux(_T_278, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_280 = and(_T_279, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_281 = bits(w1v[17], 0, 0) @[Bitwise.scala 72:15] + node _T_282 = mux(_T_281, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_283 = and(_T_282, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_284 = or(_T_280, _T_283) @[el2_dec_gpr_ctl.scala 38:47] + node _T_285 = bits(w2v[17], 0, 0) @[Bitwise.scala 72:15] + node _T_286 = mux(_T_285, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_287 = and(_T_286, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_288 = or(_T_284, _T_287) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[17] <= _T_288 @[el2_dec_gpr_ctl.scala 38:16] + node _T_289 = eq(io.waddr0, UInt<5>("h012")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_290 = and(io.wen0, _T_289) @[el2_dec_gpr_ctl.scala 35:28] + w0v[18] <= _T_290 @[el2_dec_gpr_ctl.scala 35:16] + node _T_291 = eq(io.waddr1, UInt<5>("h012")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_292 = and(io.wen1, _T_291) @[el2_dec_gpr_ctl.scala 36:28] + w1v[18] <= _T_292 @[el2_dec_gpr_ctl.scala 36:16] + node _T_293 = eq(io.waddr2, UInt<5>("h012")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_294 = and(io.wen2, _T_293) @[el2_dec_gpr_ctl.scala 37:28] + w2v[18] <= _T_294 @[el2_dec_gpr_ctl.scala 37:16] + node _T_295 = bits(w0v[18], 0, 0) @[Bitwise.scala 72:15] + node _T_296 = mux(_T_295, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_297 = and(_T_296, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_298 = bits(w1v[18], 0, 0) @[Bitwise.scala 72:15] + node _T_299 = mux(_T_298, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_300 = and(_T_299, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_301 = or(_T_297, _T_300) @[el2_dec_gpr_ctl.scala 38:47] + node _T_302 = bits(w2v[18], 0, 0) @[Bitwise.scala 72:15] + node _T_303 = mux(_T_302, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_304 = and(_T_303, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_305 = or(_T_301, _T_304) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[18] <= _T_305 @[el2_dec_gpr_ctl.scala 38:16] + node _T_306 = eq(io.waddr0, UInt<5>("h013")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_307 = and(io.wen0, _T_306) @[el2_dec_gpr_ctl.scala 35:28] + w0v[19] <= _T_307 @[el2_dec_gpr_ctl.scala 35:16] + node _T_308 = eq(io.waddr1, UInt<5>("h013")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_309 = and(io.wen1, _T_308) @[el2_dec_gpr_ctl.scala 36:28] + w1v[19] <= _T_309 @[el2_dec_gpr_ctl.scala 36:16] + node _T_310 = eq(io.waddr2, UInt<5>("h013")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_311 = and(io.wen2, _T_310) @[el2_dec_gpr_ctl.scala 37:28] + w2v[19] <= _T_311 @[el2_dec_gpr_ctl.scala 37:16] + node _T_312 = bits(w0v[19], 0, 0) @[Bitwise.scala 72:15] + node _T_313 = mux(_T_312, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_314 = and(_T_313, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_315 = bits(w1v[19], 0, 0) @[Bitwise.scala 72:15] + node _T_316 = mux(_T_315, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_317 = and(_T_316, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_318 = or(_T_314, _T_317) @[el2_dec_gpr_ctl.scala 38:47] + node _T_319 = bits(w2v[19], 0, 0) @[Bitwise.scala 72:15] + node _T_320 = mux(_T_319, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_321 = and(_T_320, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_322 = or(_T_318, _T_321) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[19] <= _T_322 @[el2_dec_gpr_ctl.scala 38:16] + node _T_323 = eq(io.waddr0, UInt<5>("h014")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_324 = and(io.wen0, _T_323) @[el2_dec_gpr_ctl.scala 35:28] + w0v[20] <= _T_324 @[el2_dec_gpr_ctl.scala 35:16] + node _T_325 = eq(io.waddr1, UInt<5>("h014")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_326 = and(io.wen1, _T_325) @[el2_dec_gpr_ctl.scala 36:28] + w1v[20] <= _T_326 @[el2_dec_gpr_ctl.scala 36:16] + node _T_327 = eq(io.waddr2, UInt<5>("h014")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_328 = and(io.wen2, _T_327) @[el2_dec_gpr_ctl.scala 37:28] + w2v[20] <= _T_328 @[el2_dec_gpr_ctl.scala 37:16] + node _T_329 = bits(w0v[20], 0, 0) @[Bitwise.scala 72:15] + node _T_330 = mux(_T_329, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_331 = and(_T_330, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_332 = bits(w1v[20], 0, 0) @[Bitwise.scala 72:15] + node _T_333 = mux(_T_332, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_334 = and(_T_333, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_335 = or(_T_331, _T_334) @[el2_dec_gpr_ctl.scala 38:47] + node _T_336 = bits(w2v[20], 0, 0) @[Bitwise.scala 72:15] + node _T_337 = mux(_T_336, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_338 = and(_T_337, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_339 = or(_T_335, _T_338) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[20] <= _T_339 @[el2_dec_gpr_ctl.scala 38:16] + node _T_340 = eq(io.waddr0, UInt<5>("h015")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_341 = and(io.wen0, _T_340) @[el2_dec_gpr_ctl.scala 35:28] + w0v[21] <= _T_341 @[el2_dec_gpr_ctl.scala 35:16] + node _T_342 = eq(io.waddr1, UInt<5>("h015")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_343 = and(io.wen1, _T_342) @[el2_dec_gpr_ctl.scala 36:28] + w1v[21] <= _T_343 @[el2_dec_gpr_ctl.scala 36:16] + node _T_344 = eq(io.waddr2, UInt<5>("h015")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_345 = and(io.wen2, _T_344) @[el2_dec_gpr_ctl.scala 37:28] + w2v[21] <= _T_345 @[el2_dec_gpr_ctl.scala 37:16] + node _T_346 = bits(w0v[21], 0, 0) @[Bitwise.scala 72:15] + node _T_347 = mux(_T_346, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_348 = and(_T_347, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_349 = bits(w1v[21], 0, 0) @[Bitwise.scala 72:15] + node _T_350 = mux(_T_349, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_351 = and(_T_350, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_352 = or(_T_348, _T_351) @[el2_dec_gpr_ctl.scala 38:47] + node _T_353 = bits(w2v[21], 0, 0) @[Bitwise.scala 72:15] + node _T_354 = mux(_T_353, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_355 = and(_T_354, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_356 = or(_T_352, _T_355) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[21] <= _T_356 @[el2_dec_gpr_ctl.scala 38:16] + node _T_357 = eq(io.waddr0, UInt<5>("h016")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_358 = and(io.wen0, _T_357) @[el2_dec_gpr_ctl.scala 35:28] + w0v[22] <= _T_358 @[el2_dec_gpr_ctl.scala 35:16] + node _T_359 = eq(io.waddr1, UInt<5>("h016")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_360 = and(io.wen1, _T_359) @[el2_dec_gpr_ctl.scala 36:28] + w1v[22] <= _T_360 @[el2_dec_gpr_ctl.scala 36:16] + node _T_361 = eq(io.waddr2, UInt<5>("h016")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_362 = and(io.wen2, _T_361) @[el2_dec_gpr_ctl.scala 37:28] + w2v[22] <= _T_362 @[el2_dec_gpr_ctl.scala 37:16] + node _T_363 = bits(w0v[22], 0, 0) @[Bitwise.scala 72:15] + node _T_364 = mux(_T_363, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_365 = and(_T_364, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_366 = bits(w1v[22], 0, 0) @[Bitwise.scala 72:15] + node _T_367 = mux(_T_366, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_368 = and(_T_367, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_369 = or(_T_365, _T_368) @[el2_dec_gpr_ctl.scala 38:47] + node _T_370 = bits(w2v[22], 0, 0) @[Bitwise.scala 72:15] + node _T_371 = mux(_T_370, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_372 = and(_T_371, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_373 = or(_T_369, _T_372) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[22] <= _T_373 @[el2_dec_gpr_ctl.scala 38:16] + node _T_374 = eq(io.waddr0, UInt<5>("h017")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_375 = and(io.wen0, _T_374) @[el2_dec_gpr_ctl.scala 35:28] + w0v[23] <= _T_375 @[el2_dec_gpr_ctl.scala 35:16] + node _T_376 = eq(io.waddr1, UInt<5>("h017")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_377 = and(io.wen1, _T_376) @[el2_dec_gpr_ctl.scala 36:28] + w1v[23] <= _T_377 @[el2_dec_gpr_ctl.scala 36:16] + node _T_378 = eq(io.waddr2, UInt<5>("h017")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_379 = and(io.wen2, _T_378) @[el2_dec_gpr_ctl.scala 37:28] + w2v[23] <= _T_379 @[el2_dec_gpr_ctl.scala 37:16] + node _T_380 = bits(w0v[23], 0, 0) @[Bitwise.scala 72:15] + node _T_381 = mux(_T_380, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_382 = and(_T_381, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_383 = bits(w1v[23], 0, 0) @[Bitwise.scala 72:15] + node _T_384 = mux(_T_383, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_385 = and(_T_384, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_386 = or(_T_382, _T_385) @[el2_dec_gpr_ctl.scala 38:47] + node _T_387 = bits(w2v[23], 0, 0) @[Bitwise.scala 72:15] + node _T_388 = mux(_T_387, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_389 = and(_T_388, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_390 = or(_T_386, _T_389) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[23] <= _T_390 @[el2_dec_gpr_ctl.scala 38:16] + node _T_391 = eq(io.waddr0, UInt<5>("h018")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_392 = and(io.wen0, _T_391) @[el2_dec_gpr_ctl.scala 35:28] + w0v[24] <= _T_392 @[el2_dec_gpr_ctl.scala 35:16] + node _T_393 = eq(io.waddr1, UInt<5>("h018")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_394 = and(io.wen1, _T_393) @[el2_dec_gpr_ctl.scala 36:28] + w1v[24] <= _T_394 @[el2_dec_gpr_ctl.scala 36:16] + node _T_395 = eq(io.waddr2, UInt<5>("h018")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_396 = and(io.wen2, _T_395) @[el2_dec_gpr_ctl.scala 37:28] + w2v[24] <= _T_396 @[el2_dec_gpr_ctl.scala 37:16] + node _T_397 = bits(w0v[24], 0, 0) @[Bitwise.scala 72:15] + node _T_398 = mux(_T_397, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_399 = and(_T_398, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_400 = bits(w1v[24], 0, 0) @[Bitwise.scala 72:15] + node _T_401 = mux(_T_400, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_402 = and(_T_401, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_403 = or(_T_399, _T_402) @[el2_dec_gpr_ctl.scala 38:47] + node _T_404 = bits(w2v[24], 0, 0) @[Bitwise.scala 72:15] + node _T_405 = mux(_T_404, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_406 = and(_T_405, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_407 = or(_T_403, _T_406) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[24] <= _T_407 @[el2_dec_gpr_ctl.scala 38:16] + node _T_408 = eq(io.waddr0, UInt<5>("h019")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_409 = and(io.wen0, _T_408) @[el2_dec_gpr_ctl.scala 35:28] + w0v[25] <= _T_409 @[el2_dec_gpr_ctl.scala 35:16] + node _T_410 = eq(io.waddr1, UInt<5>("h019")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_411 = and(io.wen1, _T_410) @[el2_dec_gpr_ctl.scala 36:28] + w1v[25] <= _T_411 @[el2_dec_gpr_ctl.scala 36:16] + node _T_412 = eq(io.waddr2, UInt<5>("h019")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_413 = and(io.wen2, _T_412) @[el2_dec_gpr_ctl.scala 37:28] + w2v[25] <= _T_413 @[el2_dec_gpr_ctl.scala 37:16] + node _T_414 = bits(w0v[25], 0, 0) @[Bitwise.scala 72:15] + node _T_415 = mux(_T_414, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_416 = and(_T_415, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_417 = bits(w1v[25], 0, 0) @[Bitwise.scala 72:15] + node _T_418 = mux(_T_417, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_419 = and(_T_418, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_420 = or(_T_416, _T_419) @[el2_dec_gpr_ctl.scala 38:47] + node _T_421 = bits(w2v[25], 0, 0) @[Bitwise.scala 72:15] + node _T_422 = mux(_T_421, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_423 = and(_T_422, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_424 = or(_T_420, _T_423) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[25] <= _T_424 @[el2_dec_gpr_ctl.scala 38:16] + node _T_425 = eq(io.waddr0, UInt<5>("h01a")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_426 = and(io.wen0, _T_425) @[el2_dec_gpr_ctl.scala 35:28] + w0v[26] <= _T_426 @[el2_dec_gpr_ctl.scala 35:16] + node _T_427 = eq(io.waddr1, UInt<5>("h01a")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_428 = and(io.wen1, _T_427) @[el2_dec_gpr_ctl.scala 36:28] + w1v[26] <= _T_428 @[el2_dec_gpr_ctl.scala 36:16] + node _T_429 = eq(io.waddr2, UInt<5>("h01a")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_430 = and(io.wen2, _T_429) @[el2_dec_gpr_ctl.scala 37:28] + w2v[26] <= _T_430 @[el2_dec_gpr_ctl.scala 37:16] + node _T_431 = bits(w0v[26], 0, 0) @[Bitwise.scala 72:15] + node _T_432 = mux(_T_431, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_433 = and(_T_432, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_434 = bits(w1v[26], 0, 0) @[Bitwise.scala 72:15] + node _T_435 = mux(_T_434, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_436 = and(_T_435, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_437 = or(_T_433, _T_436) @[el2_dec_gpr_ctl.scala 38:47] + node _T_438 = bits(w2v[26], 0, 0) @[Bitwise.scala 72:15] + node _T_439 = mux(_T_438, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_440 = and(_T_439, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_441 = or(_T_437, _T_440) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[26] <= _T_441 @[el2_dec_gpr_ctl.scala 38:16] + node _T_442 = eq(io.waddr0, UInt<5>("h01b")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_443 = and(io.wen0, _T_442) @[el2_dec_gpr_ctl.scala 35:28] + w0v[27] <= _T_443 @[el2_dec_gpr_ctl.scala 35:16] + node _T_444 = eq(io.waddr1, UInt<5>("h01b")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_445 = and(io.wen1, _T_444) @[el2_dec_gpr_ctl.scala 36:28] + w1v[27] <= _T_445 @[el2_dec_gpr_ctl.scala 36:16] + node _T_446 = eq(io.waddr2, UInt<5>("h01b")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_447 = and(io.wen2, _T_446) @[el2_dec_gpr_ctl.scala 37:28] + w2v[27] <= _T_447 @[el2_dec_gpr_ctl.scala 37:16] + node _T_448 = bits(w0v[27], 0, 0) @[Bitwise.scala 72:15] + node _T_449 = mux(_T_448, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_450 = and(_T_449, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_451 = bits(w1v[27], 0, 0) @[Bitwise.scala 72:15] + node _T_452 = mux(_T_451, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_453 = and(_T_452, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_454 = or(_T_450, _T_453) @[el2_dec_gpr_ctl.scala 38:47] + node _T_455 = bits(w2v[27], 0, 0) @[Bitwise.scala 72:15] + node _T_456 = mux(_T_455, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_457 = and(_T_456, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_458 = or(_T_454, _T_457) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[27] <= _T_458 @[el2_dec_gpr_ctl.scala 38:16] + node _T_459 = eq(io.waddr0, UInt<5>("h01c")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_460 = and(io.wen0, _T_459) @[el2_dec_gpr_ctl.scala 35:28] + w0v[28] <= _T_460 @[el2_dec_gpr_ctl.scala 35:16] + node _T_461 = eq(io.waddr1, UInt<5>("h01c")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_462 = and(io.wen1, _T_461) @[el2_dec_gpr_ctl.scala 36:28] + w1v[28] <= _T_462 @[el2_dec_gpr_ctl.scala 36:16] + node _T_463 = eq(io.waddr2, UInt<5>("h01c")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_464 = and(io.wen2, _T_463) @[el2_dec_gpr_ctl.scala 37:28] + w2v[28] <= _T_464 @[el2_dec_gpr_ctl.scala 37:16] + node _T_465 = bits(w0v[28], 0, 0) @[Bitwise.scala 72:15] + node _T_466 = mux(_T_465, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_467 = and(_T_466, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_468 = bits(w1v[28], 0, 0) @[Bitwise.scala 72:15] + node _T_469 = mux(_T_468, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_470 = and(_T_469, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_471 = or(_T_467, _T_470) @[el2_dec_gpr_ctl.scala 38:47] + node _T_472 = bits(w2v[28], 0, 0) @[Bitwise.scala 72:15] + node _T_473 = mux(_T_472, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_474 = and(_T_473, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_475 = or(_T_471, _T_474) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[28] <= _T_475 @[el2_dec_gpr_ctl.scala 38:16] + node _T_476 = eq(io.waddr0, UInt<5>("h01d")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_477 = and(io.wen0, _T_476) @[el2_dec_gpr_ctl.scala 35:28] + w0v[29] <= _T_477 @[el2_dec_gpr_ctl.scala 35:16] + node _T_478 = eq(io.waddr1, UInt<5>("h01d")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_479 = and(io.wen1, _T_478) @[el2_dec_gpr_ctl.scala 36:28] + w1v[29] <= _T_479 @[el2_dec_gpr_ctl.scala 36:16] + node _T_480 = eq(io.waddr2, UInt<5>("h01d")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_481 = and(io.wen2, _T_480) @[el2_dec_gpr_ctl.scala 37:28] + w2v[29] <= _T_481 @[el2_dec_gpr_ctl.scala 37:16] + node _T_482 = bits(w0v[29], 0, 0) @[Bitwise.scala 72:15] + node _T_483 = mux(_T_482, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_484 = and(_T_483, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_485 = bits(w1v[29], 0, 0) @[Bitwise.scala 72:15] + node _T_486 = mux(_T_485, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_487 = and(_T_486, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_488 = or(_T_484, _T_487) @[el2_dec_gpr_ctl.scala 38:47] + node _T_489 = bits(w2v[29], 0, 0) @[Bitwise.scala 72:15] + node _T_490 = mux(_T_489, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_491 = and(_T_490, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_492 = or(_T_488, _T_491) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[29] <= _T_492 @[el2_dec_gpr_ctl.scala 38:16] + node _T_493 = eq(io.waddr0, UInt<5>("h01e")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_494 = and(io.wen0, _T_493) @[el2_dec_gpr_ctl.scala 35:28] + w0v[30] <= _T_494 @[el2_dec_gpr_ctl.scala 35:16] + node _T_495 = eq(io.waddr1, UInt<5>("h01e")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_496 = and(io.wen1, _T_495) @[el2_dec_gpr_ctl.scala 36:28] + w1v[30] <= _T_496 @[el2_dec_gpr_ctl.scala 36:16] + node _T_497 = eq(io.waddr2, UInt<5>("h01e")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_498 = and(io.wen2, _T_497) @[el2_dec_gpr_ctl.scala 37:28] + w2v[30] <= _T_498 @[el2_dec_gpr_ctl.scala 37:16] + node _T_499 = bits(w0v[30], 0, 0) @[Bitwise.scala 72:15] + node _T_500 = mux(_T_499, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_501 = and(_T_500, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_502 = bits(w1v[30], 0, 0) @[Bitwise.scala 72:15] + node _T_503 = mux(_T_502, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_504 = and(_T_503, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_505 = or(_T_501, _T_504) @[el2_dec_gpr_ctl.scala 38:47] + node _T_506 = bits(w2v[30], 0, 0) @[Bitwise.scala 72:15] + node _T_507 = mux(_T_506, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_508 = and(_T_507, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_509 = or(_T_505, _T_508) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[30] <= _T_509 @[el2_dec_gpr_ctl.scala 38:16] + node _T_510 = eq(io.waddr0, UInt<5>("h01f")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_511 = and(io.wen0, _T_510) @[el2_dec_gpr_ctl.scala 35:28] + w0v[31] <= _T_511 @[el2_dec_gpr_ctl.scala 35:16] + node _T_512 = eq(io.waddr1, UInt<5>("h01f")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_513 = and(io.wen1, _T_512) @[el2_dec_gpr_ctl.scala 36:28] + w1v[31] <= _T_513 @[el2_dec_gpr_ctl.scala 36:16] + node _T_514 = eq(io.waddr2, UInt<5>("h01f")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_515 = and(io.wen2, _T_514) @[el2_dec_gpr_ctl.scala 37:28] + w2v[31] <= _T_515 @[el2_dec_gpr_ctl.scala 37:16] + node _T_516 = bits(w0v[31], 0, 0) @[Bitwise.scala 72:15] + node _T_517 = mux(_T_516, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_518 = and(_T_517, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_519 = bits(w1v[31], 0, 0) @[Bitwise.scala 72:15] + node _T_520 = mux(_T_519, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_521 = and(_T_520, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_522 = or(_T_518, _T_521) @[el2_dec_gpr_ctl.scala 38:47] + node _T_523 = bits(w2v[31], 0, 0) @[Bitwise.scala 72:15] + node _T_524 = mux(_T_523, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_525 = and(_T_524, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_526 = or(_T_522, _T_525) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[31] <= _T_526 @[el2_dec_gpr_ctl.scala 38:16] + node _T_527 = cat(w0v[1], w0v[0]) @[Cat.scala 29:58] + node _T_528 = cat(w0v[2], _T_527) @[Cat.scala 29:58] + node _T_529 = cat(w0v[3], _T_528) @[Cat.scala 29:58] + node _T_530 = cat(w0v[4], _T_529) @[Cat.scala 29:58] + node _T_531 = cat(w0v[5], _T_530) @[Cat.scala 29:58] + node _T_532 = cat(w0v[6], _T_531) @[Cat.scala 29:58] + node _T_533 = cat(w0v[7], _T_532) @[Cat.scala 29:58] + node _T_534 = cat(w0v[8], _T_533) @[Cat.scala 29:58] + node _T_535 = cat(w0v[9], _T_534) @[Cat.scala 29:58] + node _T_536 = cat(w0v[10], _T_535) @[Cat.scala 29:58] + node _T_537 = cat(w0v[11], _T_536) @[Cat.scala 29:58] + node _T_538 = cat(w0v[12], _T_537) @[Cat.scala 29:58] + node _T_539 = cat(w0v[13], _T_538) @[Cat.scala 29:58] + node _T_540 = cat(w0v[14], _T_539) @[Cat.scala 29:58] + node _T_541 = cat(w0v[15], _T_540) @[Cat.scala 29:58] + node _T_542 = cat(w0v[16], _T_541) @[Cat.scala 29:58] + node _T_543 = cat(w0v[17], _T_542) @[Cat.scala 29:58] + node _T_544 = cat(w0v[18], _T_543) @[Cat.scala 29:58] + node _T_545 = cat(w0v[19], _T_544) @[Cat.scala 29:58] + node _T_546 = cat(w0v[20], _T_545) @[Cat.scala 29:58] + node _T_547 = cat(w0v[21], _T_546) @[Cat.scala 29:58] + node _T_548 = cat(w0v[22], _T_547) @[Cat.scala 29:58] + node _T_549 = cat(w0v[23], _T_548) @[Cat.scala 29:58] + node _T_550 = cat(w0v[24], _T_549) @[Cat.scala 29:58] + node _T_551 = cat(w0v[25], _T_550) @[Cat.scala 29:58] + node _T_552 = cat(w0v[26], _T_551) @[Cat.scala 29:58] + node _T_553 = cat(w0v[27], _T_552) @[Cat.scala 29:58] + node _T_554 = cat(w0v[28], _T_553) @[Cat.scala 29:58] + node _T_555 = cat(w0v[29], _T_554) @[Cat.scala 29:58] + node _T_556 = cat(w0v[30], _T_555) @[Cat.scala 29:58] + node _T_557 = cat(w0v[31], _T_556) @[Cat.scala 29:58] + node _T_558 = cat(w1v[1], w1v[0]) @[Cat.scala 29:58] + node _T_559 = cat(w1v[2], _T_558) @[Cat.scala 29:58] + node _T_560 = cat(w1v[3], _T_559) @[Cat.scala 29:58] + node _T_561 = cat(w1v[4], _T_560) @[Cat.scala 29:58] + node _T_562 = cat(w1v[5], _T_561) @[Cat.scala 29:58] + node _T_563 = cat(w1v[6], _T_562) @[Cat.scala 29:58] + node _T_564 = cat(w1v[7], _T_563) @[Cat.scala 29:58] + node _T_565 = cat(w1v[8], _T_564) @[Cat.scala 29:58] + node _T_566 = cat(w1v[9], _T_565) @[Cat.scala 29:58] + node _T_567 = cat(w1v[10], _T_566) @[Cat.scala 29:58] + node _T_568 = cat(w1v[11], _T_567) @[Cat.scala 29:58] + node _T_569 = cat(w1v[12], _T_568) @[Cat.scala 29:58] + node _T_570 = cat(w1v[13], _T_569) @[Cat.scala 29:58] + node _T_571 = cat(w1v[14], _T_570) @[Cat.scala 29:58] + node _T_572 = cat(w1v[15], _T_571) @[Cat.scala 29:58] + node _T_573 = cat(w1v[16], _T_572) @[Cat.scala 29:58] + node _T_574 = cat(w1v[17], _T_573) @[Cat.scala 29:58] + node _T_575 = cat(w1v[18], _T_574) @[Cat.scala 29:58] + node _T_576 = cat(w1v[19], _T_575) @[Cat.scala 29:58] + node _T_577 = cat(w1v[20], _T_576) @[Cat.scala 29:58] + node _T_578 = cat(w1v[21], _T_577) @[Cat.scala 29:58] + node _T_579 = cat(w1v[22], _T_578) @[Cat.scala 29:58] + node _T_580 = cat(w1v[23], _T_579) @[Cat.scala 29:58] + node _T_581 = cat(w1v[24], _T_580) @[Cat.scala 29:58] + node _T_582 = cat(w1v[25], _T_581) @[Cat.scala 29:58] + node _T_583 = cat(w1v[26], _T_582) @[Cat.scala 29:58] + node _T_584 = cat(w1v[27], _T_583) @[Cat.scala 29:58] + node _T_585 = cat(w1v[28], _T_584) @[Cat.scala 29:58] + node _T_586 = cat(w1v[29], _T_585) @[Cat.scala 29:58] + node _T_587 = cat(w1v[30], _T_586) @[Cat.scala 29:58] + node _T_588 = cat(w1v[31], _T_587) @[Cat.scala 29:58] + node _T_589 = or(_T_557, _T_588) @[el2_dec_gpr_ctl.scala 40:51] + node _T_590 = cat(w2v[1], w2v[0]) @[Cat.scala 29:58] + node _T_591 = cat(w2v[2], _T_590) @[Cat.scala 29:58] + node _T_592 = cat(w2v[3], _T_591) @[Cat.scala 29:58] + node _T_593 = cat(w2v[4], _T_592) @[Cat.scala 29:58] + node _T_594 = cat(w2v[5], _T_593) @[Cat.scala 29:58] + node _T_595 = cat(w2v[6], _T_594) @[Cat.scala 29:58] + node _T_596 = cat(w2v[7], _T_595) @[Cat.scala 29:58] + node _T_597 = cat(w2v[8], _T_596) @[Cat.scala 29:58] + node _T_598 = cat(w2v[9], _T_597) @[Cat.scala 29:58] + node _T_599 = cat(w2v[10], _T_598) @[Cat.scala 29:58] + node _T_600 = cat(w2v[11], _T_599) @[Cat.scala 29:58] + node _T_601 = cat(w2v[12], _T_600) @[Cat.scala 29:58] + node _T_602 = cat(w2v[13], _T_601) @[Cat.scala 29:58] + node _T_603 = cat(w2v[14], _T_602) @[Cat.scala 29:58] + node _T_604 = cat(w2v[15], _T_603) @[Cat.scala 29:58] + node _T_605 = cat(w2v[16], _T_604) @[Cat.scala 29:58] + node _T_606 = cat(w2v[17], _T_605) @[Cat.scala 29:58] + node _T_607 = cat(w2v[18], _T_606) @[Cat.scala 29:58] + node _T_608 = cat(w2v[19], _T_607) @[Cat.scala 29:58] + node _T_609 = cat(w2v[20], _T_608) @[Cat.scala 29:58] + node _T_610 = cat(w2v[21], _T_609) @[Cat.scala 29:58] + node _T_611 = cat(w2v[22], _T_610) @[Cat.scala 29:58] + node _T_612 = cat(w2v[23], _T_611) @[Cat.scala 29:58] + node _T_613 = cat(w2v[24], _T_612) @[Cat.scala 29:58] + node _T_614 = cat(w2v[25], _T_613) @[Cat.scala 29:58] + node _T_615 = cat(w2v[26], _T_614) @[Cat.scala 29:58] + node _T_616 = cat(w2v[27], _T_615) @[Cat.scala 29:58] + node _T_617 = cat(w2v[28], _T_616) @[Cat.scala 29:58] + node _T_618 = cat(w2v[29], _T_617) @[Cat.scala 29:58] + node _T_619 = cat(w2v[30], _T_618) @[Cat.scala 29:58] + node _T_620 = cat(w2v[31], _T_619) @[Cat.scala 29:58] + node _T_621 = or(_T_589, _T_620) @[el2_dec_gpr_ctl.scala 40:89] + gpr_wr_en <= _T_621 @[el2_dec_gpr_ctl.scala 40:12] + node _T_622 = bits(gpr_wr_en, 1, 1) @[el2_dec_gpr_ctl.scala 44:43] + inst rvclkhdr of rvclkhdr @[el2_lib.scala 508:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr.io.en <= _T_622 @[el2_lib.scala 511:17] + rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_623 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_623 <= gpr_in[1] @[el2_lib.scala 514:16] + gpr_out[1] <= _T_623 @[el2_dec_gpr_ctl.scala 44:15] + node _T_624 = bits(gpr_wr_en, 2, 2) @[el2_dec_gpr_ctl.scala 44:43] + inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 508:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_1.io.en <= _T_624 @[el2_lib.scala 511:17] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_625 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_625 <= gpr_in[2] @[el2_lib.scala 514:16] + gpr_out[2] <= _T_625 @[el2_dec_gpr_ctl.scala 44:15] + node _T_626 = bits(gpr_wr_en, 3, 3) @[el2_dec_gpr_ctl.scala 44:43] + inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 508:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_2.io.en <= _T_626 @[el2_lib.scala 511:17] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_627 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_627 <= gpr_in[3] @[el2_lib.scala 514:16] + gpr_out[3] <= _T_627 @[el2_dec_gpr_ctl.scala 44:15] + node _T_628 = bits(gpr_wr_en, 4, 4) @[el2_dec_gpr_ctl.scala 44:43] + inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 508:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_3.io.en <= _T_628 @[el2_lib.scala 511:17] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_629 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_629 <= gpr_in[4] @[el2_lib.scala 514:16] + gpr_out[4] <= _T_629 @[el2_dec_gpr_ctl.scala 44:15] + node _T_630 = bits(gpr_wr_en, 5, 5) @[el2_dec_gpr_ctl.scala 44:43] + inst rvclkhdr_4 of rvclkhdr_4 @[el2_lib.scala 508:23] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= reset + rvclkhdr_4.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_4.io.en <= _T_630 @[el2_lib.scala 511:17] + rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_631 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_631 <= gpr_in[5] @[el2_lib.scala 514:16] + gpr_out[5] <= _T_631 @[el2_dec_gpr_ctl.scala 44:15] + node _T_632 = bits(gpr_wr_en, 6, 6) @[el2_dec_gpr_ctl.scala 44:43] + inst rvclkhdr_5 of rvclkhdr_5 @[el2_lib.scala 508:23] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= reset + rvclkhdr_5.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_5.io.en <= _T_632 @[el2_lib.scala 511:17] + rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_633 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_633 <= gpr_in[6] @[el2_lib.scala 514:16] + gpr_out[6] <= _T_633 @[el2_dec_gpr_ctl.scala 44:15] + node _T_634 = bits(gpr_wr_en, 7, 7) @[el2_dec_gpr_ctl.scala 44:43] + inst rvclkhdr_6 of rvclkhdr_6 @[el2_lib.scala 508:23] + rvclkhdr_6.clock <= clock + rvclkhdr_6.reset <= reset + rvclkhdr_6.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_6.io.en <= _T_634 @[el2_lib.scala 511:17] + rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_635 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_635 <= gpr_in[7] @[el2_lib.scala 514:16] + gpr_out[7] <= _T_635 @[el2_dec_gpr_ctl.scala 44:15] + node _T_636 = bits(gpr_wr_en, 8, 8) @[el2_dec_gpr_ctl.scala 44:43] + inst rvclkhdr_7 of rvclkhdr_7 @[el2_lib.scala 508:23] + rvclkhdr_7.clock <= clock + rvclkhdr_7.reset <= reset + rvclkhdr_7.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_7.io.en <= _T_636 @[el2_lib.scala 511:17] + rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_637 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_637 <= gpr_in[8] @[el2_lib.scala 514:16] + gpr_out[8] <= _T_637 @[el2_dec_gpr_ctl.scala 44:15] + node _T_638 = bits(gpr_wr_en, 9, 9) @[el2_dec_gpr_ctl.scala 44:43] + inst rvclkhdr_8 of rvclkhdr_8 @[el2_lib.scala 508:23] + rvclkhdr_8.clock <= clock + rvclkhdr_8.reset <= reset + rvclkhdr_8.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_8.io.en <= _T_638 @[el2_lib.scala 511:17] + rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_639 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_639 <= gpr_in[9] @[el2_lib.scala 514:16] + gpr_out[9] <= _T_639 @[el2_dec_gpr_ctl.scala 44:15] + node _T_640 = bits(gpr_wr_en, 10, 10) @[el2_dec_gpr_ctl.scala 44:43] + inst rvclkhdr_9 of rvclkhdr_9 @[el2_lib.scala 508:23] + rvclkhdr_9.clock <= clock + rvclkhdr_9.reset <= reset + rvclkhdr_9.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_9.io.en <= _T_640 @[el2_lib.scala 511:17] + rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_641 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_641 <= gpr_in[10] @[el2_lib.scala 514:16] + gpr_out[10] <= _T_641 @[el2_dec_gpr_ctl.scala 44:15] + node _T_642 = bits(gpr_wr_en, 11, 11) @[el2_dec_gpr_ctl.scala 44:43] + inst rvclkhdr_10 of rvclkhdr_10 @[el2_lib.scala 508:23] + rvclkhdr_10.clock <= clock + rvclkhdr_10.reset <= reset + rvclkhdr_10.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_10.io.en <= _T_642 @[el2_lib.scala 511:17] + rvclkhdr_10.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_643 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_643 <= gpr_in[11] @[el2_lib.scala 514:16] + gpr_out[11] <= _T_643 @[el2_dec_gpr_ctl.scala 44:15] + node _T_644 = bits(gpr_wr_en, 12, 12) @[el2_dec_gpr_ctl.scala 44:43] + inst rvclkhdr_11 of rvclkhdr_11 @[el2_lib.scala 508:23] + rvclkhdr_11.clock <= clock + rvclkhdr_11.reset <= reset + rvclkhdr_11.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_11.io.en <= _T_644 @[el2_lib.scala 511:17] + rvclkhdr_11.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_645 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_645 <= gpr_in[12] @[el2_lib.scala 514:16] + gpr_out[12] <= _T_645 @[el2_dec_gpr_ctl.scala 44:15] + node _T_646 = bits(gpr_wr_en, 13, 13) @[el2_dec_gpr_ctl.scala 44:43] + inst rvclkhdr_12 of rvclkhdr_12 @[el2_lib.scala 508:23] + rvclkhdr_12.clock <= clock + rvclkhdr_12.reset <= reset + rvclkhdr_12.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_12.io.en <= _T_646 @[el2_lib.scala 511:17] + rvclkhdr_12.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_647 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_647 <= gpr_in[13] @[el2_lib.scala 514:16] + gpr_out[13] <= _T_647 @[el2_dec_gpr_ctl.scala 44:15] + node _T_648 = bits(gpr_wr_en, 14, 14) @[el2_dec_gpr_ctl.scala 44:43] + inst rvclkhdr_13 of rvclkhdr_13 @[el2_lib.scala 508:23] + rvclkhdr_13.clock <= clock + rvclkhdr_13.reset <= reset + rvclkhdr_13.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_13.io.en <= _T_648 @[el2_lib.scala 511:17] + rvclkhdr_13.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_649 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_649 <= gpr_in[14] @[el2_lib.scala 514:16] + gpr_out[14] <= _T_649 @[el2_dec_gpr_ctl.scala 44:15] + node _T_650 = bits(gpr_wr_en, 15, 15) @[el2_dec_gpr_ctl.scala 44:43] + inst rvclkhdr_14 of rvclkhdr_14 @[el2_lib.scala 508:23] + rvclkhdr_14.clock <= clock + rvclkhdr_14.reset <= reset + rvclkhdr_14.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_14.io.en <= _T_650 @[el2_lib.scala 511:17] + rvclkhdr_14.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_651 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_651 <= gpr_in[15] @[el2_lib.scala 514:16] + gpr_out[15] <= _T_651 @[el2_dec_gpr_ctl.scala 44:15] + node _T_652 = bits(gpr_wr_en, 16, 16) @[el2_dec_gpr_ctl.scala 44:43] + inst rvclkhdr_15 of rvclkhdr_15 @[el2_lib.scala 508:23] + rvclkhdr_15.clock <= clock + rvclkhdr_15.reset <= reset + rvclkhdr_15.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_15.io.en <= _T_652 @[el2_lib.scala 511:17] + rvclkhdr_15.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_653 : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_653 <= gpr_in[16] @[el2_lib.scala 514:16] + gpr_out[16] <= _T_653 @[el2_dec_gpr_ctl.scala 44:15] + node _T_654 = bits(gpr_wr_en, 17, 17) @[el2_dec_gpr_ctl.scala 44:43] + inst rvclkhdr_16 of rvclkhdr_16 @[el2_lib.scala 508:23] + rvclkhdr_16.clock <= clock + rvclkhdr_16.reset <= reset + rvclkhdr_16.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_16.io.en <= _T_654 @[el2_lib.scala 511:17] + rvclkhdr_16.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_655 : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_655 <= gpr_in[17] @[el2_lib.scala 514:16] + gpr_out[17] <= _T_655 @[el2_dec_gpr_ctl.scala 44:15] + node _T_656 = bits(gpr_wr_en, 18, 18) @[el2_dec_gpr_ctl.scala 44:43] + inst rvclkhdr_17 of rvclkhdr_17 @[el2_lib.scala 508:23] + rvclkhdr_17.clock <= clock + rvclkhdr_17.reset <= reset + rvclkhdr_17.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_17.io.en <= _T_656 @[el2_lib.scala 511:17] + rvclkhdr_17.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_657 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_657 <= gpr_in[18] @[el2_lib.scala 514:16] + gpr_out[18] <= _T_657 @[el2_dec_gpr_ctl.scala 44:15] + node _T_658 = bits(gpr_wr_en, 19, 19) @[el2_dec_gpr_ctl.scala 44:43] + inst rvclkhdr_18 of rvclkhdr_18 @[el2_lib.scala 508:23] + rvclkhdr_18.clock <= clock + rvclkhdr_18.reset <= reset + rvclkhdr_18.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_18.io.en <= _T_658 @[el2_lib.scala 511:17] + rvclkhdr_18.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_659 : UInt, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_659 <= gpr_in[19] @[el2_lib.scala 514:16] + gpr_out[19] <= _T_659 @[el2_dec_gpr_ctl.scala 44:15] + node _T_660 = bits(gpr_wr_en, 20, 20) @[el2_dec_gpr_ctl.scala 44:43] + inst rvclkhdr_19 of rvclkhdr_19 @[el2_lib.scala 508:23] + rvclkhdr_19.clock <= clock + rvclkhdr_19.reset <= reset + rvclkhdr_19.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_19.io.en <= _T_660 @[el2_lib.scala 511:17] + rvclkhdr_19.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_661 : UInt, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_661 <= gpr_in[20] @[el2_lib.scala 514:16] + gpr_out[20] <= _T_661 @[el2_dec_gpr_ctl.scala 44:15] + node _T_662 = bits(gpr_wr_en, 21, 21) @[el2_dec_gpr_ctl.scala 44:43] + inst rvclkhdr_20 of rvclkhdr_20 @[el2_lib.scala 508:23] + rvclkhdr_20.clock <= clock + rvclkhdr_20.reset <= reset + rvclkhdr_20.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_20.io.en <= _T_662 @[el2_lib.scala 511:17] + rvclkhdr_20.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_663 : UInt, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_663 <= gpr_in[21] @[el2_lib.scala 514:16] + gpr_out[21] <= _T_663 @[el2_dec_gpr_ctl.scala 44:15] + node _T_664 = bits(gpr_wr_en, 22, 22) @[el2_dec_gpr_ctl.scala 44:43] + inst rvclkhdr_21 of rvclkhdr_21 @[el2_lib.scala 508:23] + rvclkhdr_21.clock <= clock + rvclkhdr_21.reset <= reset + rvclkhdr_21.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_21.io.en <= _T_664 @[el2_lib.scala 511:17] + rvclkhdr_21.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_665 : UInt, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_665 <= gpr_in[22] @[el2_lib.scala 514:16] + gpr_out[22] <= _T_665 @[el2_dec_gpr_ctl.scala 44:15] + node _T_666 = bits(gpr_wr_en, 23, 23) @[el2_dec_gpr_ctl.scala 44:43] + inst rvclkhdr_22 of rvclkhdr_22 @[el2_lib.scala 508:23] + rvclkhdr_22.clock <= clock + rvclkhdr_22.reset <= reset + rvclkhdr_22.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_22.io.en <= _T_666 @[el2_lib.scala 511:17] + rvclkhdr_22.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_667 : UInt, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_667 <= gpr_in[23] @[el2_lib.scala 514:16] + gpr_out[23] <= _T_667 @[el2_dec_gpr_ctl.scala 44:15] + node _T_668 = bits(gpr_wr_en, 24, 24) @[el2_dec_gpr_ctl.scala 44:43] + inst rvclkhdr_23 of rvclkhdr_23 @[el2_lib.scala 508:23] + rvclkhdr_23.clock <= clock + rvclkhdr_23.reset <= reset + rvclkhdr_23.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_23.io.en <= _T_668 @[el2_lib.scala 511:17] + rvclkhdr_23.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_669 : UInt, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_669 <= gpr_in[24] @[el2_lib.scala 514:16] + gpr_out[24] <= _T_669 @[el2_dec_gpr_ctl.scala 44:15] + node _T_670 = bits(gpr_wr_en, 25, 25) @[el2_dec_gpr_ctl.scala 44:43] + inst rvclkhdr_24 of rvclkhdr_24 @[el2_lib.scala 508:23] + rvclkhdr_24.clock <= clock + rvclkhdr_24.reset <= reset + rvclkhdr_24.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_24.io.en <= _T_670 @[el2_lib.scala 511:17] + rvclkhdr_24.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_671 : UInt, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_671 <= gpr_in[25] @[el2_lib.scala 514:16] + gpr_out[25] <= _T_671 @[el2_dec_gpr_ctl.scala 44:15] + node _T_672 = bits(gpr_wr_en, 26, 26) @[el2_dec_gpr_ctl.scala 44:43] + inst rvclkhdr_25 of rvclkhdr_25 @[el2_lib.scala 508:23] + rvclkhdr_25.clock <= clock + rvclkhdr_25.reset <= reset + rvclkhdr_25.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_25.io.en <= _T_672 @[el2_lib.scala 511:17] + rvclkhdr_25.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_673 : UInt, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_673 <= gpr_in[26] @[el2_lib.scala 514:16] + gpr_out[26] <= _T_673 @[el2_dec_gpr_ctl.scala 44:15] + node _T_674 = bits(gpr_wr_en, 27, 27) @[el2_dec_gpr_ctl.scala 44:43] + inst rvclkhdr_26 of rvclkhdr_26 @[el2_lib.scala 508:23] + rvclkhdr_26.clock <= clock + rvclkhdr_26.reset <= reset + rvclkhdr_26.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_26.io.en <= _T_674 @[el2_lib.scala 511:17] + rvclkhdr_26.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_675 : UInt, rvclkhdr_26.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_675 <= gpr_in[27] @[el2_lib.scala 514:16] + gpr_out[27] <= _T_675 @[el2_dec_gpr_ctl.scala 44:15] + node _T_676 = bits(gpr_wr_en, 28, 28) @[el2_dec_gpr_ctl.scala 44:43] + inst rvclkhdr_27 of rvclkhdr_27 @[el2_lib.scala 508:23] + rvclkhdr_27.clock <= clock + rvclkhdr_27.reset <= reset + rvclkhdr_27.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_27.io.en <= _T_676 @[el2_lib.scala 511:17] + rvclkhdr_27.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_677 : UInt, rvclkhdr_27.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_677 <= gpr_in[28] @[el2_lib.scala 514:16] + gpr_out[28] <= _T_677 @[el2_dec_gpr_ctl.scala 44:15] + node _T_678 = bits(gpr_wr_en, 29, 29) @[el2_dec_gpr_ctl.scala 44:43] + inst rvclkhdr_28 of rvclkhdr_28 @[el2_lib.scala 508:23] + rvclkhdr_28.clock <= clock + rvclkhdr_28.reset <= reset + rvclkhdr_28.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_28.io.en <= _T_678 @[el2_lib.scala 511:17] + rvclkhdr_28.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_679 : UInt, rvclkhdr_28.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_679 <= gpr_in[29] @[el2_lib.scala 514:16] + gpr_out[29] <= _T_679 @[el2_dec_gpr_ctl.scala 44:15] + node _T_680 = bits(gpr_wr_en, 30, 30) @[el2_dec_gpr_ctl.scala 44:43] + inst rvclkhdr_29 of rvclkhdr_29 @[el2_lib.scala 508:23] + rvclkhdr_29.clock <= clock + rvclkhdr_29.reset <= reset + rvclkhdr_29.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_29.io.en <= _T_680 @[el2_lib.scala 511:17] + rvclkhdr_29.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_681 : UInt, rvclkhdr_29.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_681 <= gpr_in[30] @[el2_lib.scala 514:16] + gpr_out[30] <= _T_681 @[el2_dec_gpr_ctl.scala 44:15] + node _T_682 = bits(gpr_wr_en, 31, 31) @[el2_dec_gpr_ctl.scala 44:43] + inst rvclkhdr_30 of rvclkhdr_30 @[el2_lib.scala 508:23] + rvclkhdr_30.clock <= clock + rvclkhdr_30.reset <= reset + rvclkhdr_30.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_30.io.en <= _T_682 @[el2_lib.scala 511:17] + rvclkhdr_30.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_683 : UInt, rvclkhdr_30.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_683 <= gpr_in[31] @[el2_lib.scala 514:16] + gpr_out[31] <= _T_683 @[el2_dec_gpr_ctl.scala 44:15] + node _T_684 = eq(io.raddr0, UInt<1>("h01")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_685 = bits(_T_684, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_686 = eq(io.raddr0, UInt<2>("h02")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_687 = bits(_T_686, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_688 = eq(io.raddr0, UInt<2>("h03")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_689 = bits(_T_688, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_690 = eq(io.raddr0, UInt<3>("h04")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_691 = bits(_T_690, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_692 = eq(io.raddr0, UInt<3>("h05")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_693 = bits(_T_692, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_694 = eq(io.raddr0, UInt<3>("h06")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_695 = bits(_T_694, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_696 = eq(io.raddr0, UInt<3>("h07")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_697 = bits(_T_696, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_698 = eq(io.raddr0, UInt<4>("h08")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_699 = bits(_T_698, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_700 = eq(io.raddr0, UInt<4>("h09")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_701 = bits(_T_700, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_702 = eq(io.raddr0, UInt<4>("h0a")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_703 = bits(_T_702, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_704 = eq(io.raddr0, UInt<4>("h0b")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_705 = bits(_T_704, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_706 = eq(io.raddr0, UInt<4>("h0c")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_707 = bits(_T_706, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_708 = eq(io.raddr0, UInt<4>("h0d")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_709 = bits(_T_708, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_710 = eq(io.raddr0, UInt<4>("h0e")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_711 = bits(_T_710, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_712 = eq(io.raddr0, UInt<4>("h0f")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_713 = bits(_T_712, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_714 = eq(io.raddr0, UInt<5>("h010")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_715 = bits(_T_714, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_716 = eq(io.raddr0, UInt<5>("h011")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_717 = bits(_T_716, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_718 = eq(io.raddr0, UInt<5>("h012")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_719 = bits(_T_718, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_720 = eq(io.raddr0, UInt<5>("h013")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_721 = bits(_T_720, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_722 = eq(io.raddr0, UInt<5>("h014")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_723 = bits(_T_722, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_724 = eq(io.raddr0, UInt<5>("h015")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_725 = bits(_T_724, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_726 = eq(io.raddr0, UInt<5>("h016")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_727 = bits(_T_726, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_728 = eq(io.raddr0, UInt<5>("h017")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_729 = bits(_T_728, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_730 = eq(io.raddr0, UInt<5>("h018")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_731 = bits(_T_730, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_732 = eq(io.raddr0, UInt<5>("h019")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_733 = bits(_T_732, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_734 = eq(io.raddr0, UInt<5>("h01a")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_735 = bits(_T_734, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_736 = eq(io.raddr0, UInt<5>("h01b")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_737 = bits(_T_736, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_738 = eq(io.raddr0, UInt<5>("h01c")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_739 = bits(_T_738, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_740 = eq(io.raddr0, UInt<5>("h01d")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_741 = bits(_T_740, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_742 = eq(io.raddr0, UInt<5>("h01e")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_743 = bits(_T_742, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_744 = eq(io.raddr0, UInt<5>("h01f")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_745 = bits(_T_744, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_746 = mux(_T_685, gpr_out[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_747 = mux(_T_687, gpr_out[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_748 = mux(_T_689, gpr_out[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_749 = mux(_T_691, gpr_out[4], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_750 = mux(_T_693, gpr_out[5], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_751 = mux(_T_695, gpr_out[6], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_752 = mux(_T_697, gpr_out[7], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_753 = mux(_T_699, gpr_out[8], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_754 = mux(_T_701, gpr_out[9], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_755 = mux(_T_703, gpr_out[10], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_756 = mux(_T_705, gpr_out[11], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_757 = mux(_T_707, gpr_out[12], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_758 = mux(_T_709, gpr_out[13], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_759 = mux(_T_711, gpr_out[14], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_760 = mux(_T_713, gpr_out[15], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_761 = mux(_T_715, gpr_out[16], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_762 = mux(_T_717, gpr_out[17], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_763 = mux(_T_719, gpr_out[18], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_764 = mux(_T_721, gpr_out[19], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_765 = mux(_T_723, gpr_out[20], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_766 = mux(_T_725, gpr_out[21], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_767 = mux(_T_727, gpr_out[22], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_768 = mux(_T_729, gpr_out[23], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_769 = mux(_T_731, gpr_out[24], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_770 = mux(_T_733, gpr_out[25], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_771 = mux(_T_735, gpr_out[26], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_772 = mux(_T_737, gpr_out[27], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_773 = mux(_T_739, gpr_out[28], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_774 = mux(_T_741, gpr_out[29], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_775 = mux(_T_743, gpr_out[30], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_776 = mux(_T_745, gpr_out[31], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_777 = or(_T_746, _T_747) @[Mux.scala 27:72] + node _T_778 = or(_T_777, _T_748) @[Mux.scala 27:72] + node _T_779 = or(_T_778, _T_749) @[Mux.scala 27:72] + node _T_780 = or(_T_779, _T_750) @[Mux.scala 27:72] + node _T_781 = or(_T_780, _T_751) @[Mux.scala 27:72] + node _T_782 = or(_T_781, _T_752) @[Mux.scala 27:72] + node _T_783 = or(_T_782, _T_753) @[Mux.scala 27:72] + node _T_784 = or(_T_783, _T_754) @[Mux.scala 27:72] + node _T_785 = or(_T_784, _T_755) @[Mux.scala 27:72] + node _T_786 = or(_T_785, _T_756) @[Mux.scala 27:72] + node _T_787 = or(_T_786, _T_757) @[Mux.scala 27:72] + node _T_788 = or(_T_787, _T_758) @[Mux.scala 27:72] + node _T_789 = or(_T_788, _T_759) @[Mux.scala 27:72] + node _T_790 = or(_T_789, _T_760) @[Mux.scala 27:72] + node _T_791 = or(_T_790, _T_761) @[Mux.scala 27:72] + node _T_792 = or(_T_791, _T_762) @[Mux.scala 27:72] + node _T_793 = or(_T_792, _T_763) @[Mux.scala 27:72] + node _T_794 = or(_T_793, _T_764) @[Mux.scala 27:72] + node _T_795 = or(_T_794, _T_765) @[Mux.scala 27:72] + node _T_796 = or(_T_795, _T_766) @[Mux.scala 27:72] + node _T_797 = or(_T_796, _T_767) @[Mux.scala 27:72] + node _T_798 = or(_T_797, _T_768) @[Mux.scala 27:72] + node _T_799 = or(_T_798, _T_769) @[Mux.scala 27:72] + node _T_800 = or(_T_799, _T_770) @[Mux.scala 27:72] + node _T_801 = or(_T_800, _T_771) @[Mux.scala 27:72] + node _T_802 = or(_T_801, _T_772) @[Mux.scala 27:72] + node _T_803 = or(_T_802, _T_773) @[Mux.scala 27:72] + node _T_804 = or(_T_803, _T_774) @[Mux.scala 27:72] + node _T_805 = or(_T_804, _T_775) @[Mux.scala 27:72] + node _T_806 = or(_T_805, _T_776) @[Mux.scala 27:72] + wire _T_807 : UInt<32> @[Mux.scala 27:72] + _T_807 <= _T_806 @[Mux.scala 27:72] + io.rd0 <= _T_807 @[el2_dec_gpr_ctl.scala 47:9] + node _T_808 = eq(io.raddr1, UInt<1>("h01")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_809 = bits(_T_808, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_810 = eq(io.raddr1, UInt<2>("h02")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_811 = bits(_T_810, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_812 = eq(io.raddr1, UInt<2>("h03")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_813 = bits(_T_812, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_814 = eq(io.raddr1, UInt<3>("h04")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_815 = bits(_T_814, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_816 = eq(io.raddr1, UInt<3>("h05")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_817 = bits(_T_816, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_818 = eq(io.raddr1, UInt<3>("h06")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_819 = bits(_T_818, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_820 = eq(io.raddr1, UInt<3>("h07")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_821 = bits(_T_820, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_822 = eq(io.raddr1, UInt<4>("h08")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_823 = bits(_T_822, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_824 = eq(io.raddr1, UInt<4>("h09")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_825 = bits(_T_824, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_826 = eq(io.raddr1, UInt<4>("h0a")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_827 = bits(_T_826, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_828 = eq(io.raddr1, UInt<4>("h0b")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_829 = bits(_T_828, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_830 = eq(io.raddr1, UInt<4>("h0c")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_831 = bits(_T_830, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_832 = eq(io.raddr1, UInt<4>("h0d")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_833 = bits(_T_832, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_834 = eq(io.raddr1, UInt<4>("h0e")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_835 = bits(_T_834, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_836 = eq(io.raddr1, UInt<4>("h0f")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_837 = bits(_T_836, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_838 = eq(io.raddr1, UInt<5>("h010")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_839 = bits(_T_838, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_840 = eq(io.raddr1, UInt<5>("h011")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_841 = bits(_T_840, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_842 = eq(io.raddr1, UInt<5>("h012")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_843 = bits(_T_842, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_844 = eq(io.raddr1, UInt<5>("h013")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_845 = bits(_T_844, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_846 = eq(io.raddr1, UInt<5>("h014")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_847 = bits(_T_846, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_848 = eq(io.raddr1, UInt<5>("h015")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_849 = bits(_T_848, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_850 = eq(io.raddr1, UInt<5>("h016")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_851 = bits(_T_850, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_852 = eq(io.raddr1, UInt<5>("h017")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_853 = bits(_T_852, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_854 = eq(io.raddr1, UInt<5>("h018")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_855 = bits(_T_854, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_856 = eq(io.raddr1, UInt<5>("h019")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_857 = bits(_T_856, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_858 = eq(io.raddr1, UInt<5>("h01a")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_859 = bits(_T_858, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_860 = eq(io.raddr1, UInt<5>("h01b")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_861 = bits(_T_860, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_862 = eq(io.raddr1, UInt<5>("h01c")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_863 = bits(_T_862, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_864 = eq(io.raddr1, UInt<5>("h01d")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_865 = bits(_T_864, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_866 = eq(io.raddr1, UInt<5>("h01e")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_867 = bits(_T_866, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_868 = eq(io.raddr1, UInt<5>("h01f")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_869 = bits(_T_868, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_870 = mux(_T_809, gpr_out[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_871 = mux(_T_811, gpr_out[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_872 = mux(_T_813, gpr_out[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_873 = mux(_T_815, gpr_out[4], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_874 = mux(_T_817, gpr_out[5], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_875 = mux(_T_819, gpr_out[6], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_876 = mux(_T_821, gpr_out[7], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_877 = mux(_T_823, gpr_out[8], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_878 = mux(_T_825, gpr_out[9], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_879 = mux(_T_827, gpr_out[10], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_880 = mux(_T_829, gpr_out[11], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_881 = mux(_T_831, gpr_out[12], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_882 = mux(_T_833, gpr_out[13], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_883 = mux(_T_835, gpr_out[14], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_884 = mux(_T_837, gpr_out[15], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_885 = mux(_T_839, gpr_out[16], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_886 = mux(_T_841, gpr_out[17], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_887 = mux(_T_843, gpr_out[18], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_888 = mux(_T_845, gpr_out[19], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_889 = mux(_T_847, gpr_out[20], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_890 = mux(_T_849, gpr_out[21], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_891 = mux(_T_851, gpr_out[22], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_892 = mux(_T_853, gpr_out[23], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_893 = mux(_T_855, gpr_out[24], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_894 = mux(_T_857, gpr_out[25], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_895 = mux(_T_859, gpr_out[26], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_896 = mux(_T_861, gpr_out[27], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_897 = mux(_T_863, gpr_out[28], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_898 = mux(_T_865, gpr_out[29], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_899 = mux(_T_867, gpr_out[30], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_900 = mux(_T_869, gpr_out[31], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_901 = or(_T_870, _T_871) @[Mux.scala 27:72] + node _T_902 = or(_T_901, _T_872) @[Mux.scala 27:72] + node _T_903 = or(_T_902, _T_873) @[Mux.scala 27:72] + node _T_904 = or(_T_903, _T_874) @[Mux.scala 27:72] + node _T_905 = or(_T_904, _T_875) @[Mux.scala 27:72] + node _T_906 = or(_T_905, _T_876) @[Mux.scala 27:72] + node _T_907 = or(_T_906, _T_877) @[Mux.scala 27:72] + node _T_908 = or(_T_907, _T_878) @[Mux.scala 27:72] + node _T_909 = or(_T_908, _T_879) @[Mux.scala 27:72] + node _T_910 = or(_T_909, _T_880) @[Mux.scala 27:72] + node _T_911 = or(_T_910, _T_881) @[Mux.scala 27:72] + node _T_912 = or(_T_911, _T_882) @[Mux.scala 27:72] + node _T_913 = or(_T_912, _T_883) @[Mux.scala 27:72] + node _T_914 = or(_T_913, _T_884) @[Mux.scala 27:72] + node _T_915 = or(_T_914, _T_885) @[Mux.scala 27:72] + node _T_916 = or(_T_915, _T_886) @[Mux.scala 27:72] + node _T_917 = or(_T_916, _T_887) @[Mux.scala 27:72] + node _T_918 = or(_T_917, _T_888) @[Mux.scala 27:72] + node _T_919 = or(_T_918, _T_889) @[Mux.scala 27:72] + node _T_920 = or(_T_919, _T_890) @[Mux.scala 27:72] + node _T_921 = or(_T_920, _T_891) @[Mux.scala 27:72] + node _T_922 = or(_T_921, _T_892) @[Mux.scala 27:72] + node _T_923 = or(_T_922, _T_893) @[Mux.scala 27:72] + node _T_924 = or(_T_923, _T_894) @[Mux.scala 27:72] + node _T_925 = or(_T_924, _T_895) @[Mux.scala 27:72] + node _T_926 = or(_T_925, _T_896) @[Mux.scala 27:72] + node _T_927 = or(_T_926, _T_897) @[Mux.scala 27:72] + node _T_928 = or(_T_927, _T_898) @[Mux.scala 27:72] + node _T_929 = or(_T_928, _T_899) @[Mux.scala 27:72] + node _T_930 = or(_T_929, _T_900) @[Mux.scala 27:72] + wire _T_931 : UInt<32> @[Mux.scala 27:72] + _T_931 <= _T_930 @[Mux.scala 27:72] + io.rd1 <= _T_931 @[el2_dec_gpr_ctl.scala 48:9] + diff --git a/el2_dec_gpr_ctl.v b/el2_dec_gpr_ctl.v new file mode 100644 index 00000000..31b5d235 --- /dev/null +++ b/el2_dec_gpr_ctl.v @@ -0,0 +1,1522 @@ +module rvclkhdr( + output io_l1clk, + input io_clk, + input io_en, + input io_scan_mode +); + wire clkhdr_Q; // @[el2_lib.scala 474:26] + wire clkhdr_CK; // @[el2_lib.scala 474:26] + wire clkhdr_EN; // @[el2_lib.scala 474:26] + wire clkhdr_SE; // @[el2_lib.scala 474:26] + gated_latch clkhdr ( // @[el2_lib.scala 474:26] + .Q(clkhdr_Q), + .CK(clkhdr_CK), + .EN(clkhdr_EN), + .SE(clkhdr_SE) + ); + assign io_l1clk = clkhdr_Q; // @[el2_lib.scala 475:14] + assign clkhdr_CK = io_clk; // @[el2_lib.scala 476:18] + assign clkhdr_EN = io_en; // @[el2_lib.scala 477:18] + assign clkhdr_SE = io_scan_mode; // @[el2_lib.scala 478:18] +endmodule +module el2_dec_gpr_ctl( + input clock, + input reset, + input [4:0] io_raddr0, + input [4:0] io_raddr1, + input io_wen0, + input [4:0] io_waddr0, + input [31:0] io_wd0, + input io_wen1, + input [4:0] io_waddr1, + input [31:0] io_wd1, + input io_wen2, + input [4:0] io_waddr2, + input [31:0] io_wd2, + output [31:0] io_rd0, + output [31:0] io_rd1, + input io_scan_mode +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; + reg [31:0] _RAND_13; + reg [31:0] _RAND_14; + reg [31:0] _RAND_15; + reg [31:0] _RAND_16; + reg [31:0] _RAND_17; + reg [31:0] _RAND_18; + reg [31:0] _RAND_19; + reg [31:0] _RAND_20; + reg [31:0] _RAND_21; + reg [31:0] _RAND_22; + reg [31:0] _RAND_23; + reg [31:0] _RAND_24; + reg [31:0] _RAND_25; + reg [31:0] _RAND_26; + reg [31:0] _RAND_27; + reg [31:0] _RAND_28; + reg [31:0] _RAND_29; + reg [31:0] _RAND_30; +`endif // RANDOMIZE_REG_INIT + wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_2_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_2_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_4_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_4_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_5_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_5_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_6_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_6_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_6_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_6_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_7_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_7_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_7_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_7_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_8_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_8_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_8_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_8_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_9_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_9_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_9_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_10_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_10_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_10_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_10_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_11_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_11_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_11_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_11_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_12_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_12_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_12_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_12_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_13_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_13_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_13_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_13_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_14_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_14_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_14_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_14_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_15_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_15_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_15_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_15_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_16_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_16_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_16_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_16_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_17_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_17_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_17_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_17_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_18_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_18_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_18_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_18_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_19_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_19_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_19_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_19_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_20_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_20_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_20_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_20_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_21_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_21_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_21_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_21_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_22_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_22_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_22_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_22_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_23_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_23_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_23_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_23_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_24_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_24_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_24_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_24_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_25_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_25_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_25_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_25_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_26_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_26_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_26_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_26_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_27_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_27_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_27_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_27_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_28_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_28_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_28_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_28_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_29_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_29_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_29_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_29_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_30_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_30_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_30_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_30_io_scan_mode; // @[el2_lib.scala 508:23] + wire _T = io_waddr0 == 5'h1; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_1 = io_wen0 & _T; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_2 = io_waddr1 == 5'h1; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_1 = io_wen1 & _T_2; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_4 = io_waddr2 == 5'h1; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_1 = io_wen2 & _T_4; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_7 = w0v_1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_8 = _T_7 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_10 = w1v_1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_11 = _T_10 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_12 = _T_8 | _T_11; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_14 = w2v_1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_15 = _T_14 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_17 = io_waddr0 == 5'h2; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_2 = io_wen0 & _T_17; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_19 = io_waddr1 == 5'h2; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_2 = io_wen1 & _T_19; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_21 = io_waddr2 == 5'h2; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_2 = io_wen2 & _T_21; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_24 = w0v_2 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_25 = _T_24 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_27 = w1v_2 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_28 = _T_27 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_29 = _T_25 | _T_28; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_31 = w2v_2 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_32 = _T_31 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_34 = io_waddr0 == 5'h3; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_3 = io_wen0 & _T_34; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_36 = io_waddr1 == 5'h3; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_3 = io_wen1 & _T_36; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_38 = io_waddr2 == 5'h3; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_3 = io_wen2 & _T_38; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_41 = w0v_3 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_42 = _T_41 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_44 = w1v_3 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_45 = _T_44 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_46 = _T_42 | _T_45; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_48 = w2v_3 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_49 = _T_48 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_51 = io_waddr0 == 5'h4; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_4 = io_wen0 & _T_51; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_53 = io_waddr1 == 5'h4; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_4 = io_wen1 & _T_53; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_55 = io_waddr2 == 5'h4; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_4 = io_wen2 & _T_55; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_58 = w0v_4 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_59 = _T_58 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_61 = w1v_4 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_62 = _T_61 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_63 = _T_59 | _T_62; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_65 = w2v_4 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_66 = _T_65 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_68 = io_waddr0 == 5'h5; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_5 = io_wen0 & _T_68; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_70 = io_waddr1 == 5'h5; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_5 = io_wen1 & _T_70; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_72 = io_waddr2 == 5'h5; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_5 = io_wen2 & _T_72; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_75 = w0v_5 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_76 = _T_75 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_78 = w1v_5 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_79 = _T_78 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_80 = _T_76 | _T_79; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_82 = w2v_5 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_83 = _T_82 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_85 = io_waddr0 == 5'h6; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_6 = io_wen0 & _T_85; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_87 = io_waddr1 == 5'h6; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_6 = io_wen1 & _T_87; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_89 = io_waddr2 == 5'h6; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_6 = io_wen2 & _T_89; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_92 = w0v_6 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_93 = _T_92 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_95 = w1v_6 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_96 = _T_95 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_97 = _T_93 | _T_96; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_99 = w2v_6 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_100 = _T_99 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_102 = io_waddr0 == 5'h7; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_7 = io_wen0 & _T_102; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_104 = io_waddr1 == 5'h7; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_7 = io_wen1 & _T_104; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_106 = io_waddr2 == 5'h7; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_7 = io_wen2 & _T_106; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_109 = w0v_7 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_110 = _T_109 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_112 = w1v_7 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_113 = _T_112 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_114 = _T_110 | _T_113; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_116 = w2v_7 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_117 = _T_116 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_119 = io_waddr0 == 5'h8; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_8 = io_wen0 & _T_119; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_121 = io_waddr1 == 5'h8; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_8 = io_wen1 & _T_121; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_123 = io_waddr2 == 5'h8; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_8 = io_wen2 & _T_123; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_126 = w0v_8 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_127 = _T_126 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_129 = w1v_8 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_130 = _T_129 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_131 = _T_127 | _T_130; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_133 = w2v_8 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_134 = _T_133 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_136 = io_waddr0 == 5'h9; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_9 = io_wen0 & _T_136; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_138 = io_waddr1 == 5'h9; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_9 = io_wen1 & _T_138; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_140 = io_waddr2 == 5'h9; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_9 = io_wen2 & _T_140; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_143 = w0v_9 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_144 = _T_143 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_146 = w1v_9 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_147 = _T_146 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_148 = _T_144 | _T_147; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_150 = w2v_9 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_151 = _T_150 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_153 = io_waddr0 == 5'ha; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_10 = io_wen0 & _T_153; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_155 = io_waddr1 == 5'ha; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_10 = io_wen1 & _T_155; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_157 = io_waddr2 == 5'ha; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_10 = io_wen2 & _T_157; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_160 = w0v_10 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_161 = _T_160 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_163 = w1v_10 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_164 = _T_163 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_165 = _T_161 | _T_164; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_167 = w2v_10 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_168 = _T_167 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_170 = io_waddr0 == 5'hb; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_11 = io_wen0 & _T_170; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_172 = io_waddr1 == 5'hb; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_11 = io_wen1 & _T_172; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_174 = io_waddr2 == 5'hb; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_11 = io_wen2 & _T_174; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_177 = w0v_11 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_178 = _T_177 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_180 = w1v_11 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_181 = _T_180 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_182 = _T_178 | _T_181; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_184 = w2v_11 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_185 = _T_184 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_187 = io_waddr0 == 5'hc; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_12 = io_wen0 & _T_187; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_189 = io_waddr1 == 5'hc; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_12 = io_wen1 & _T_189; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_191 = io_waddr2 == 5'hc; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_12 = io_wen2 & _T_191; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_194 = w0v_12 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_195 = _T_194 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_197 = w1v_12 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_198 = _T_197 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_199 = _T_195 | _T_198; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_201 = w2v_12 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_202 = _T_201 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_204 = io_waddr0 == 5'hd; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_13 = io_wen0 & _T_204; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_206 = io_waddr1 == 5'hd; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_13 = io_wen1 & _T_206; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_208 = io_waddr2 == 5'hd; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_13 = io_wen2 & _T_208; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_211 = w0v_13 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_212 = _T_211 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_214 = w1v_13 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_215 = _T_214 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_216 = _T_212 | _T_215; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_218 = w2v_13 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_219 = _T_218 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_221 = io_waddr0 == 5'he; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_14 = io_wen0 & _T_221; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_223 = io_waddr1 == 5'he; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_14 = io_wen1 & _T_223; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_225 = io_waddr2 == 5'he; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_14 = io_wen2 & _T_225; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_228 = w0v_14 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_229 = _T_228 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_231 = w1v_14 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_232 = _T_231 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_233 = _T_229 | _T_232; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_235 = w2v_14 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_236 = _T_235 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_238 = io_waddr0 == 5'hf; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_15 = io_wen0 & _T_238; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_240 = io_waddr1 == 5'hf; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_15 = io_wen1 & _T_240; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_242 = io_waddr2 == 5'hf; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_15 = io_wen2 & _T_242; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_245 = w0v_15 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_246 = _T_245 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_248 = w1v_15 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_249 = _T_248 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_250 = _T_246 | _T_249; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_252 = w2v_15 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_253 = _T_252 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_255 = io_waddr0 == 5'h10; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_16 = io_wen0 & _T_255; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_257 = io_waddr1 == 5'h10; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_16 = io_wen1 & _T_257; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_259 = io_waddr2 == 5'h10; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_16 = io_wen2 & _T_259; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_262 = w0v_16 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_263 = _T_262 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_265 = w1v_16 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_266 = _T_265 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_267 = _T_263 | _T_266; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_269 = w2v_16 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_270 = _T_269 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_272 = io_waddr0 == 5'h11; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_17 = io_wen0 & _T_272; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_274 = io_waddr1 == 5'h11; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_17 = io_wen1 & _T_274; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_276 = io_waddr2 == 5'h11; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_17 = io_wen2 & _T_276; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_279 = w0v_17 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_280 = _T_279 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_282 = w1v_17 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_283 = _T_282 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_284 = _T_280 | _T_283; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_286 = w2v_17 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_287 = _T_286 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_289 = io_waddr0 == 5'h12; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_18 = io_wen0 & _T_289; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_291 = io_waddr1 == 5'h12; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_18 = io_wen1 & _T_291; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_293 = io_waddr2 == 5'h12; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_18 = io_wen2 & _T_293; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_296 = w0v_18 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_297 = _T_296 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_299 = w1v_18 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_300 = _T_299 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_301 = _T_297 | _T_300; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_303 = w2v_18 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_304 = _T_303 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_306 = io_waddr0 == 5'h13; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_19 = io_wen0 & _T_306; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_308 = io_waddr1 == 5'h13; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_19 = io_wen1 & _T_308; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_310 = io_waddr2 == 5'h13; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_19 = io_wen2 & _T_310; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_313 = w0v_19 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_314 = _T_313 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_316 = w1v_19 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_317 = _T_316 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_318 = _T_314 | _T_317; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_320 = w2v_19 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_321 = _T_320 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_323 = io_waddr0 == 5'h14; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_20 = io_wen0 & _T_323; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_325 = io_waddr1 == 5'h14; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_20 = io_wen1 & _T_325; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_327 = io_waddr2 == 5'h14; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_20 = io_wen2 & _T_327; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_330 = w0v_20 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_331 = _T_330 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_333 = w1v_20 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_334 = _T_333 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_335 = _T_331 | _T_334; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_337 = w2v_20 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_338 = _T_337 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_340 = io_waddr0 == 5'h15; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_21 = io_wen0 & _T_340; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_342 = io_waddr1 == 5'h15; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_21 = io_wen1 & _T_342; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_344 = io_waddr2 == 5'h15; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_21 = io_wen2 & _T_344; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_347 = w0v_21 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_348 = _T_347 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_350 = w1v_21 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_351 = _T_350 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_352 = _T_348 | _T_351; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_354 = w2v_21 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_355 = _T_354 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_357 = io_waddr0 == 5'h16; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_22 = io_wen0 & _T_357; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_359 = io_waddr1 == 5'h16; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_22 = io_wen1 & _T_359; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_361 = io_waddr2 == 5'h16; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_22 = io_wen2 & _T_361; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_364 = w0v_22 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_365 = _T_364 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_367 = w1v_22 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_368 = _T_367 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_369 = _T_365 | _T_368; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_371 = w2v_22 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_372 = _T_371 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_374 = io_waddr0 == 5'h17; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_23 = io_wen0 & _T_374; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_376 = io_waddr1 == 5'h17; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_23 = io_wen1 & _T_376; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_378 = io_waddr2 == 5'h17; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_23 = io_wen2 & _T_378; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_381 = w0v_23 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_382 = _T_381 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_384 = w1v_23 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_385 = _T_384 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_386 = _T_382 | _T_385; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_388 = w2v_23 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_389 = _T_388 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_391 = io_waddr0 == 5'h18; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_24 = io_wen0 & _T_391; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_393 = io_waddr1 == 5'h18; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_24 = io_wen1 & _T_393; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_395 = io_waddr2 == 5'h18; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_24 = io_wen2 & _T_395; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_398 = w0v_24 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_399 = _T_398 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_401 = w1v_24 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_402 = _T_401 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_403 = _T_399 | _T_402; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_405 = w2v_24 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_406 = _T_405 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_408 = io_waddr0 == 5'h19; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_25 = io_wen0 & _T_408; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_410 = io_waddr1 == 5'h19; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_25 = io_wen1 & _T_410; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_412 = io_waddr2 == 5'h19; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_25 = io_wen2 & _T_412; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_415 = w0v_25 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_416 = _T_415 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_418 = w1v_25 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_419 = _T_418 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_420 = _T_416 | _T_419; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_422 = w2v_25 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_423 = _T_422 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_425 = io_waddr0 == 5'h1a; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_26 = io_wen0 & _T_425; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_427 = io_waddr1 == 5'h1a; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_26 = io_wen1 & _T_427; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_429 = io_waddr2 == 5'h1a; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_26 = io_wen2 & _T_429; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_432 = w0v_26 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_433 = _T_432 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_435 = w1v_26 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_436 = _T_435 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_437 = _T_433 | _T_436; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_439 = w2v_26 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_440 = _T_439 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_442 = io_waddr0 == 5'h1b; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_27 = io_wen0 & _T_442; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_444 = io_waddr1 == 5'h1b; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_27 = io_wen1 & _T_444; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_446 = io_waddr2 == 5'h1b; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_27 = io_wen2 & _T_446; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_449 = w0v_27 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_450 = _T_449 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_452 = w1v_27 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_453 = _T_452 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_454 = _T_450 | _T_453; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_456 = w2v_27 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_457 = _T_456 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_459 = io_waddr0 == 5'h1c; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_28 = io_wen0 & _T_459; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_461 = io_waddr1 == 5'h1c; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_28 = io_wen1 & _T_461; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_463 = io_waddr2 == 5'h1c; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_28 = io_wen2 & _T_463; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_466 = w0v_28 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_467 = _T_466 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_469 = w1v_28 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_470 = _T_469 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_471 = _T_467 | _T_470; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_473 = w2v_28 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_474 = _T_473 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_476 = io_waddr0 == 5'h1d; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_29 = io_wen0 & _T_476; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_478 = io_waddr1 == 5'h1d; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_29 = io_wen1 & _T_478; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_480 = io_waddr2 == 5'h1d; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_29 = io_wen2 & _T_480; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_483 = w0v_29 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_484 = _T_483 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_486 = w1v_29 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_487 = _T_486 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_488 = _T_484 | _T_487; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_490 = w2v_29 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_491 = _T_490 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_493 = io_waddr0 == 5'h1e; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_30 = io_wen0 & _T_493; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_495 = io_waddr1 == 5'h1e; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_30 = io_wen1 & _T_495; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_497 = io_waddr2 == 5'h1e; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_30 = io_wen2 & _T_497; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_500 = w0v_30 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_501 = _T_500 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_503 = w1v_30 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_504 = _T_503 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_505 = _T_501 | _T_504; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_507 = w2v_30 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_508 = _T_507 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_510 = io_waddr0 == 5'h1f; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_31 = io_wen0 & _T_510; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_512 = io_waddr1 == 5'h1f; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_31 = io_wen1 & _T_512; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_514 = io_waddr2 == 5'h1f; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_31 = io_wen2 & _T_514; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_517 = w0v_31 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_518 = _T_517 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_520 = w1v_31 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_521 = _T_520 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_522 = _T_518 | _T_521; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_524 = w2v_31 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_525 = _T_524 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire [9:0] _T_535 = {w0v_9,w0v_8,w0v_7,w0v_6,w0v_5,w0v_4,w0v_3,w0v_2,w0v_1,1'h0}; // @[Cat.scala 29:58] + wire [18:0] _T_544 = {w0v_18,w0v_17,w0v_16,w0v_15,w0v_14,w0v_13,w0v_12,w0v_11,w0v_10,_T_535}; // @[Cat.scala 29:58] + wire [27:0] _T_553 = {w0v_27,w0v_26,w0v_25,w0v_24,w0v_23,w0v_22,w0v_21,w0v_20,w0v_19,_T_544}; // @[Cat.scala 29:58] + wire [31:0] _T_557 = {w0v_31,w0v_30,w0v_29,w0v_28,_T_553}; // @[Cat.scala 29:58] + wire [9:0] _T_566 = {w1v_9,w1v_8,w1v_7,w1v_6,w1v_5,w1v_4,w1v_3,w1v_2,w1v_1,1'h0}; // @[Cat.scala 29:58] + wire [18:0] _T_575 = {w1v_18,w1v_17,w1v_16,w1v_15,w1v_14,w1v_13,w1v_12,w1v_11,w1v_10,_T_566}; // @[Cat.scala 29:58] + wire [27:0] _T_584 = {w1v_27,w1v_26,w1v_25,w1v_24,w1v_23,w1v_22,w1v_21,w1v_20,w1v_19,_T_575}; // @[Cat.scala 29:58] + wire [31:0] _T_588 = {w1v_31,w1v_30,w1v_29,w1v_28,_T_584}; // @[Cat.scala 29:58] + wire [31:0] _T_589 = _T_557 | _T_588; // @[el2_dec_gpr_ctl.scala 40:51] + wire [9:0] _T_598 = {w2v_9,w2v_8,w2v_7,w2v_6,w2v_5,w2v_4,w2v_3,w2v_2,w2v_1,1'h0}; // @[Cat.scala 29:58] + wire [18:0] _T_607 = {w2v_18,w2v_17,w2v_16,w2v_15,w2v_14,w2v_13,w2v_12,w2v_11,w2v_10,_T_598}; // @[Cat.scala 29:58] + wire [27:0] _T_616 = {w2v_27,w2v_26,w2v_25,w2v_24,w2v_23,w2v_22,w2v_21,w2v_20,w2v_19,_T_607}; // @[Cat.scala 29:58] + wire [31:0] _T_620 = {w2v_31,w2v_30,w2v_29,w2v_28,_T_616}; // @[Cat.scala 29:58] + wire [31:0] gpr_wr_en = _T_589 | _T_620; // @[el2_dec_gpr_ctl.scala 40:89] + reg [31:0] gpr_out_1; // @[el2_lib.scala 514:16] + reg [31:0] gpr_out_2; // @[el2_lib.scala 514:16] + reg [31:0] gpr_out_3; // @[el2_lib.scala 514:16] + reg [31:0] gpr_out_4; // @[el2_lib.scala 514:16] + reg [31:0] gpr_out_5; // @[el2_lib.scala 514:16] + reg [31:0] gpr_out_6; // @[el2_lib.scala 514:16] + reg [31:0] gpr_out_7; // @[el2_lib.scala 514:16] + reg [31:0] gpr_out_8; // @[el2_lib.scala 514:16] + reg [31:0] gpr_out_9; // @[el2_lib.scala 514:16] + reg [31:0] gpr_out_10; // @[el2_lib.scala 514:16] + reg [31:0] gpr_out_11; // @[el2_lib.scala 514:16] + reg [31:0] gpr_out_12; // @[el2_lib.scala 514:16] + reg [31:0] gpr_out_13; // @[el2_lib.scala 514:16] + reg [31:0] gpr_out_14; // @[el2_lib.scala 514:16] + reg [31:0] gpr_out_15; // @[el2_lib.scala 514:16] + reg [31:0] gpr_out_16; // @[el2_lib.scala 514:16] + reg [31:0] gpr_out_17; // @[el2_lib.scala 514:16] + reg [31:0] gpr_out_18; // @[el2_lib.scala 514:16] + reg [31:0] gpr_out_19; // @[el2_lib.scala 514:16] + reg [31:0] gpr_out_20; // @[el2_lib.scala 514:16] + reg [31:0] gpr_out_21; // @[el2_lib.scala 514:16] + reg [31:0] gpr_out_22; // @[el2_lib.scala 514:16] + reg [31:0] gpr_out_23; // @[el2_lib.scala 514:16] + reg [31:0] gpr_out_24; // @[el2_lib.scala 514:16] + reg [31:0] gpr_out_25; // @[el2_lib.scala 514:16] + reg [31:0] gpr_out_26; // @[el2_lib.scala 514:16] + reg [31:0] gpr_out_27; // @[el2_lib.scala 514:16] + reg [31:0] gpr_out_28; // @[el2_lib.scala 514:16] + reg [31:0] gpr_out_29; // @[el2_lib.scala 514:16] + reg [31:0] gpr_out_30; // @[el2_lib.scala 514:16] + reg [31:0] gpr_out_31; // @[el2_lib.scala 514:16] + wire _T_684 = io_raddr0 == 5'h1; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_686 = io_raddr0 == 5'h2; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_688 = io_raddr0 == 5'h3; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_690 = io_raddr0 == 5'h4; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_692 = io_raddr0 == 5'h5; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_694 = io_raddr0 == 5'h6; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_696 = io_raddr0 == 5'h7; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_698 = io_raddr0 == 5'h8; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_700 = io_raddr0 == 5'h9; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_702 = io_raddr0 == 5'ha; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_704 = io_raddr0 == 5'hb; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_706 = io_raddr0 == 5'hc; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_708 = io_raddr0 == 5'hd; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_710 = io_raddr0 == 5'he; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_712 = io_raddr0 == 5'hf; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_714 = io_raddr0 == 5'h10; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_716 = io_raddr0 == 5'h11; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_718 = io_raddr0 == 5'h12; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_720 = io_raddr0 == 5'h13; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_722 = io_raddr0 == 5'h14; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_724 = io_raddr0 == 5'h15; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_726 = io_raddr0 == 5'h16; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_728 = io_raddr0 == 5'h17; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_730 = io_raddr0 == 5'h18; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_732 = io_raddr0 == 5'h19; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_734 = io_raddr0 == 5'h1a; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_736 = io_raddr0 == 5'h1b; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_738 = io_raddr0 == 5'h1c; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_740 = io_raddr0 == 5'h1d; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_742 = io_raddr0 == 5'h1e; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_744 = io_raddr0 == 5'h1f; // @[el2_dec_gpr_ctl.scala 47:49] + wire [31:0] _T_746 = _T_684 ? gpr_out_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_747 = _T_686 ? gpr_out_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_748 = _T_688 ? gpr_out_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_749 = _T_690 ? gpr_out_4 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_750 = _T_692 ? gpr_out_5 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_751 = _T_694 ? gpr_out_6 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_752 = _T_696 ? gpr_out_7 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_753 = _T_698 ? gpr_out_8 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_754 = _T_700 ? gpr_out_9 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_755 = _T_702 ? gpr_out_10 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_756 = _T_704 ? gpr_out_11 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_757 = _T_706 ? gpr_out_12 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_758 = _T_708 ? gpr_out_13 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_759 = _T_710 ? gpr_out_14 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_760 = _T_712 ? gpr_out_15 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_761 = _T_714 ? gpr_out_16 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_762 = _T_716 ? gpr_out_17 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_763 = _T_718 ? gpr_out_18 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_764 = _T_720 ? gpr_out_19 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_765 = _T_722 ? gpr_out_20 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_766 = _T_724 ? gpr_out_21 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_767 = _T_726 ? gpr_out_22 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_768 = _T_728 ? gpr_out_23 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_769 = _T_730 ? gpr_out_24 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_770 = _T_732 ? gpr_out_25 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_771 = _T_734 ? gpr_out_26 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_772 = _T_736 ? gpr_out_27 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_773 = _T_738 ? gpr_out_28 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_774 = _T_740 ? gpr_out_29 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_775 = _T_742 ? gpr_out_30 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_776 = _T_744 ? gpr_out_31 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_777 = _T_746 | _T_747; // @[Mux.scala 27:72] + wire [31:0] _T_778 = _T_777 | _T_748; // @[Mux.scala 27:72] + wire [31:0] _T_779 = _T_778 | _T_749; // @[Mux.scala 27:72] + wire [31:0] _T_780 = _T_779 | _T_750; // @[Mux.scala 27:72] + wire [31:0] _T_781 = _T_780 | _T_751; // @[Mux.scala 27:72] + wire [31:0] _T_782 = _T_781 | _T_752; // @[Mux.scala 27:72] + wire [31:0] _T_783 = _T_782 | _T_753; // @[Mux.scala 27:72] + wire [31:0] _T_784 = _T_783 | _T_754; // @[Mux.scala 27:72] + wire [31:0] _T_785 = _T_784 | _T_755; // @[Mux.scala 27:72] + wire [31:0] _T_786 = _T_785 | _T_756; // @[Mux.scala 27:72] + wire [31:0] _T_787 = _T_786 | _T_757; // @[Mux.scala 27:72] + wire [31:0] _T_788 = _T_787 | _T_758; // @[Mux.scala 27:72] + wire [31:0] _T_789 = _T_788 | _T_759; // @[Mux.scala 27:72] + wire [31:0] _T_790 = _T_789 | _T_760; // @[Mux.scala 27:72] + wire [31:0] _T_791 = _T_790 | _T_761; // @[Mux.scala 27:72] + wire [31:0] _T_792 = _T_791 | _T_762; // @[Mux.scala 27:72] + wire [31:0] _T_793 = _T_792 | _T_763; // @[Mux.scala 27:72] + wire [31:0] _T_794 = _T_793 | _T_764; // @[Mux.scala 27:72] + wire [31:0] _T_795 = _T_794 | _T_765; // @[Mux.scala 27:72] + wire [31:0] _T_796 = _T_795 | _T_766; // @[Mux.scala 27:72] + wire [31:0] _T_797 = _T_796 | _T_767; // @[Mux.scala 27:72] + wire [31:0] _T_798 = _T_797 | _T_768; // @[Mux.scala 27:72] + wire [31:0] _T_799 = _T_798 | _T_769; // @[Mux.scala 27:72] + wire [31:0] _T_800 = _T_799 | _T_770; // @[Mux.scala 27:72] + wire [31:0] _T_801 = _T_800 | _T_771; // @[Mux.scala 27:72] + wire [31:0] _T_802 = _T_801 | _T_772; // @[Mux.scala 27:72] + wire [31:0] _T_803 = _T_802 | _T_773; // @[Mux.scala 27:72] + wire [31:0] _T_804 = _T_803 | _T_774; // @[Mux.scala 27:72] + wire [31:0] _T_805 = _T_804 | _T_775; // @[Mux.scala 27:72] + wire _T_808 = io_raddr1 == 5'h1; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_810 = io_raddr1 == 5'h2; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_812 = io_raddr1 == 5'h3; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_814 = io_raddr1 == 5'h4; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_816 = io_raddr1 == 5'h5; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_818 = io_raddr1 == 5'h6; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_820 = io_raddr1 == 5'h7; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_822 = io_raddr1 == 5'h8; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_824 = io_raddr1 == 5'h9; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_826 = io_raddr1 == 5'ha; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_828 = io_raddr1 == 5'hb; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_830 = io_raddr1 == 5'hc; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_832 = io_raddr1 == 5'hd; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_834 = io_raddr1 == 5'he; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_836 = io_raddr1 == 5'hf; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_838 = io_raddr1 == 5'h10; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_840 = io_raddr1 == 5'h11; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_842 = io_raddr1 == 5'h12; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_844 = io_raddr1 == 5'h13; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_846 = io_raddr1 == 5'h14; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_848 = io_raddr1 == 5'h15; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_850 = io_raddr1 == 5'h16; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_852 = io_raddr1 == 5'h17; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_854 = io_raddr1 == 5'h18; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_856 = io_raddr1 == 5'h19; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_858 = io_raddr1 == 5'h1a; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_860 = io_raddr1 == 5'h1b; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_862 = io_raddr1 == 5'h1c; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_864 = io_raddr1 == 5'h1d; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_866 = io_raddr1 == 5'h1e; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_868 = io_raddr1 == 5'h1f; // @[el2_dec_gpr_ctl.scala 48:49] + wire [31:0] _T_870 = _T_808 ? gpr_out_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_871 = _T_810 ? gpr_out_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_872 = _T_812 ? gpr_out_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_873 = _T_814 ? gpr_out_4 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_874 = _T_816 ? gpr_out_5 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_875 = _T_818 ? gpr_out_6 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_876 = _T_820 ? gpr_out_7 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_877 = _T_822 ? gpr_out_8 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_878 = _T_824 ? gpr_out_9 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_879 = _T_826 ? gpr_out_10 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_880 = _T_828 ? gpr_out_11 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_881 = _T_830 ? gpr_out_12 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_882 = _T_832 ? gpr_out_13 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_883 = _T_834 ? gpr_out_14 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_884 = _T_836 ? gpr_out_15 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_885 = _T_838 ? gpr_out_16 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_886 = _T_840 ? gpr_out_17 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_887 = _T_842 ? gpr_out_18 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_888 = _T_844 ? gpr_out_19 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_889 = _T_846 ? gpr_out_20 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_890 = _T_848 ? gpr_out_21 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_891 = _T_850 ? gpr_out_22 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_892 = _T_852 ? gpr_out_23 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_893 = _T_854 ? gpr_out_24 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_894 = _T_856 ? gpr_out_25 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_895 = _T_858 ? gpr_out_26 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_896 = _T_860 ? gpr_out_27 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_897 = _T_862 ? gpr_out_28 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_898 = _T_864 ? gpr_out_29 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_899 = _T_866 ? gpr_out_30 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_900 = _T_868 ? gpr_out_31 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_901 = _T_870 | _T_871; // @[Mux.scala 27:72] + wire [31:0] _T_902 = _T_901 | _T_872; // @[Mux.scala 27:72] + wire [31:0] _T_903 = _T_902 | _T_873; // @[Mux.scala 27:72] + wire [31:0] _T_904 = _T_903 | _T_874; // @[Mux.scala 27:72] + wire [31:0] _T_905 = _T_904 | _T_875; // @[Mux.scala 27:72] + wire [31:0] _T_906 = _T_905 | _T_876; // @[Mux.scala 27:72] + wire [31:0] _T_907 = _T_906 | _T_877; // @[Mux.scala 27:72] + wire [31:0] _T_908 = _T_907 | _T_878; // @[Mux.scala 27:72] + wire [31:0] _T_909 = _T_908 | _T_879; // @[Mux.scala 27:72] + wire [31:0] _T_910 = _T_909 | _T_880; // @[Mux.scala 27:72] + wire [31:0] _T_911 = _T_910 | _T_881; // @[Mux.scala 27:72] + wire [31:0] _T_912 = _T_911 | _T_882; // @[Mux.scala 27:72] + wire [31:0] _T_913 = _T_912 | _T_883; // @[Mux.scala 27:72] + wire [31:0] _T_914 = _T_913 | _T_884; // @[Mux.scala 27:72] + wire [31:0] _T_915 = _T_914 | _T_885; // @[Mux.scala 27:72] + wire [31:0] _T_916 = _T_915 | _T_886; // @[Mux.scala 27:72] + wire [31:0] _T_917 = _T_916 | _T_887; // @[Mux.scala 27:72] + wire [31:0] _T_918 = _T_917 | _T_888; // @[Mux.scala 27:72] + wire [31:0] _T_919 = _T_918 | _T_889; // @[Mux.scala 27:72] + wire [31:0] _T_920 = _T_919 | _T_890; // @[Mux.scala 27:72] + wire [31:0] _T_921 = _T_920 | _T_891; // @[Mux.scala 27:72] + wire [31:0] _T_922 = _T_921 | _T_892; // @[Mux.scala 27:72] + wire [31:0] _T_923 = _T_922 | _T_893; // @[Mux.scala 27:72] + wire [31:0] _T_924 = _T_923 | _T_894; // @[Mux.scala 27:72] + wire [31:0] _T_925 = _T_924 | _T_895; // @[Mux.scala 27:72] + wire [31:0] _T_926 = _T_925 | _T_896; // @[Mux.scala 27:72] + wire [31:0] _T_927 = _T_926 | _T_897; // @[Mux.scala 27:72] + wire [31:0] _T_928 = _T_927 | _T_898; // @[Mux.scala 27:72] + wire [31:0] _T_929 = _T_928 | _T_899; // @[Mux.scala 27:72] + rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_io_l1clk), + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en), + .io_scan_mode(rvclkhdr_io_scan_mode) + ); + rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_1_io_l1clk), + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en), + .io_scan_mode(rvclkhdr_1_io_scan_mode) + ); + rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_2_io_l1clk), + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en), + .io_scan_mode(rvclkhdr_2_io_scan_mode) + ); + rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_3_io_l1clk), + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en), + .io_scan_mode(rvclkhdr_3_io_scan_mode) + ); + rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_4_io_l1clk), + .io_clk(rvclkhdr_4_io_clk), + .io_en(rvclkhdr_4_io_en), + .io_scan_mode(rvclkhdr_4_io_scan_mode) + ); + rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_5_io_l1clk), + .io_clk(rvclkhdr_5_io_clk), + .io_en(rvclkhdr_5_io_en), + .io_scan_mode(rvclkhdr_5_io_scan_mode) + ); + rvclkhdr rvclkhdr_6 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_6_io_l1clk), + .io_clk(rvclkhdr_6_io_clk), + .io_en(rvclkhdr_6_io_en), + .io_scan_mode(rvclkhdr_6_io_scan_mode) + ); + rvclkhdr rvclkhdr_7 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_7_io_l1clk), + .io_clk(rvclkhdr_7_io_clk), + .io_en(rvclkhdr_7_io_en), + .io_scan_mode(rvclkhdr_7_io_scan_mode) + ); + rvclkhdr rvclkhdr_8 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_8_io_l1clk), + .io_clk(rvclkhdr_8_io_clk), + .io_en(rvclkhdr_8_io_en), + .io_scan_mode(rvclkhdr_8_io_scan_mode) + ); + rvclkhdr rvclkhdr_9 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_9_io_l1clk), + .io_clk(rvclkhdr_9_io_clk), + .io_en(rvclkhdr_9_io_en), + .io_scan_mode(rvclkhdr_9_io_scan_mode) + ); + rvclkhdr rvclkhdr_10 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_10_io_l1clk), + .io_clk(rvclkhdr_10_io_clk), + .io_en(rvclkhdr_10_io_en), + .io_scan_mode(rvclkhdr_10_io_scan_mode) + ); + rvclkhdr rvclkhdr_11 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_11_io_l1clk), + .io_clk(rvclkhdr_11_io_clk), + .io_en(rvclkhdr_11_io_en), + .io_scan_mode(rvclkhdr_11_io_scan_mode) + ); + rvclkhdr rvclkhdr_12 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_12_io_l1clk), + .io_clk(rvclkhdr_12_io_clk), + .io_en(rvclkhdr_12_io_en), + .io_scan_mode(rvclkhdr_12_io_scan_mode) + ); + rvclkhdr rvclkhdr_13 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_13_io_l1clk), + .io_clk(rvclkhdr_13_io_clk), + .io_en(rvclkhdr_13_io_en), + .io_scan_mode(rvclkhdr_13_io_scan_mode) + ); + rvclkhdr rvclkhdr_14 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_14_io_l1clk), + .io_clk(rvclkhdr_14_io_clk), + .io_en(rvclkhdr_14_io_en), + .io_scan_mode(rvclkhdr_14_io_scan_mode) + ); + rvclkhdr rvclkhdr_15 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_15_io_l1clk), + .io_clk(rvclkhdr_15_io_clk), + .io_en(rvclkhdr_15_io_en), + .io_scan_mode(rvclkhdr_15_io_scan_mode) + ); + rvclkhdr rvclkhdr_16 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_16_io_l1clk), + .io_clk(rvclkhdr_16_io_clk), + .io_en(rvclkhdr_16_io_en), + .io_scan_mode(rvclkhdr_16_io_scan_mode) + ); + rvclkhdr rvclkhdr_17 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_17_io_l1clk), + .io_clk(rvclkhdr_17_io_clk), + .io_en(rvclkhdr_17_io_en), + .io_scan_mode(rvclkhdr_17_io_scan_mode) + ); + rvclkhdr rvclkhdr_18 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_18_io_l1clk), + .io_clk(rvclkhdr_18_io_clk), + .io_en(rvclkhdr_18_io_en), + .io_scan_mode(rvclkhdr_18_io_scan_mode) + ); + rvclkhdr rvclkhdr_19 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_19_io_l1clk), + .io_clk(rvclkhdr_19_io_clk), + .io_en(rvclkhdr_19_io_en), + .io_scan_mode(rvclkhdr_19_io_scan_mode) + ); + rvclkhdr rvclkhdr_20 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_20_io_l1clk), + .io_clk(rvclkhdr_20_io_clk), + .io_en(rvclkhdr_20_io_en), + .io_scan_mode(rvclkhdr_20_io_scan_mode) + ); + rvclkhdr rvclkhdr_21 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_21_io_l1clk), + .io_clk(rvclkhdr_21_io_clk), + .io_en(rvclkhdr_21_io_en), + .io_scan_mode(rvclkhdr_21_io_scan_mode) + ); + rvclkhdr rvclkhdr_22 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_22_io_l1clk), + .io_clk(rvclkhdr_22_io_clk), + .io_en(rvclkhdr_22_io_en), + .io_scan_mode(rvclkhdr_22_io_scan_mode) + ); + rvclkhdr rvclkhdr_23 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_23_io_l1clk), + .io_clk(rvclkhdr_23_io_clk), + .io_en(rvclkhdr_23_io_en), + .io_scan_mode(rvclkhdr_23_io_scan_mode) + ); + rvclkhdr rvclkhdr_24 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_24_io_l1clk), + .io_clk(rvclkhdr_24_io_clk), + .io_en(rvclkhdr_24_io_en), + .io_scan_mode(rvclkhdr_24_io_scan_mode) + ); + rvclkhdr rvclkhdr_25 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_25_io_l1clk), + .io_clk(rvclkhdr_25_io_clk), + .io_en(rvclkhdr_25_io_en), + .io_scan_mode(rvclkhdr_25_io_scan_mode) + ); + rvclkhdr rvclkhdr_26 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_26_io_l1clk), + .io_clk(rvclkhdr_26_io_clk), + .io_en(rvclkhdr_26_io_en), + .io_scan_mode(rvclkhdr_26_io_scan_mode) + ); + rvclkhdr rvclkhdr_27 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_27_io_l1clk), + .io_clk(rvclkhdr_27_io_clk), + .io_en(rvclkhdr_27_io_en), + .io_scan_mode(rvclkhdr_27_io_scan_mode) + ); + rvclkhdr rvclkhdr_28 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_28_io_l1clk), + .io_clk(rvclkhdr_28_io_clk), + .io_en(rvclkhdr_28_io_en), + .io_scan_mode(rvclkhdr_28_io_scan_mode) + ); + rvclkhdr rvclkhdr_29 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_29_io_l1clk), + .io_clk(rvclkhdr_29_io_clk), + .io_en(rvclkhdr_29_io_en), + .io_scan_mode(rvclkhdr_29_io_scan_mode) + ); + rvclkhdr rvclkhdr_30 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_30_io_l1clk), + .io_clk(rvclkhdr_30_io_clk), + .io_en(rvclkhdr_30_io_en), + .io_scan_mode(rvclkhdr_30_io_scan_mode) + ); + assign io_rd0 = _T_805 | _T_776; // @[el2_dec_gpr_ctl.scala 31:9 el2_dec_gpr_ctl.scala 47:9] + assign io_rd1 = _T_929 | _T_900; // @[el2_dec_gpr_ctl.scala 32:9 el2_dec_gpr_ctl.scala 48:9] + assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_io_en = gpr_wr_en[1]; // @[el2_lib.scala 511:17] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_1_io_en = gpr_wr_en[2]; // @[el2_lib.scala 511:17] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_2_io_en = gpr_wr_en[3]; // @[el2_lib.scala 511:17] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_3_io_en = gpr_wr_en[4]; // @[el2_lib.scala 511:17] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_4_io_en = gpr_wr_en[5]; // @[el2_lib.scala 511:17] + assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_5_io_en = gpr_wr_en[6]; // @[el2_lib.scala 511:17] + assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_6_io_en = gpr_wr_en[7]; // @[el2_lib.scala 511:17] + assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_7_io_en = gpr_wr_en[8]; // @[el2_lib.scala 511:17] + assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_8_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_8_io_en = gpr_wr_en[9]; // @[el2_lib.scala 511:17] + assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_9_io_en = gpr_wr_en[10]; // @[el2_lib.scala 511:17] + assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_10_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_10_io_en = gpr_wr_en[11]; // @[el2_lib.scala 511:17] + assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_11_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_11_io_en = gpr_wr_en[12]; // @[el2_lib.scala 511:17] + assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_12_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_12_io_en = gpr_wr_en[13]; // @[el2_lib.scala 511:17] + assign rvclkhdr_12_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_13_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_13_io_en = gpr_wr_en[14]; // @[el2_lib.scala 511:17] + assign rvclkhdr_13_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_14_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_14_io_en = gpr_wr_en[15]; // @[el2_lib.scala 511:17] + assign rvclkhdr_14_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_15_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_15_io_en = gpr_wr_en[16]; // @[el2_lib.scala 511:17] + assign rvclkhdr_15_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_16_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_16_io_en = gpr_wr_en[17]; // @[el2_lib.scala 511:17] + assign rvclkhdr_16_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_17_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_17_io_en = gpr_wr_en[18]; // @[el2_lib.scala 511:17] + assign rvclkhdr_17_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_18_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_18_io_en = gpr_wr_en[19]; // @[el2_lib.scala 511:17] + assign rvclkhdr_18_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_19_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_19_io_en = gpr_wr_en[20]; // @[el2_lib.scala 511:17] + assign rvclkhdr_19_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_20_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_20_io_en = gpr_wr_en[21]; // @[el2_lib.scala 511:17] + assign rvclkhdr_20_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_21_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_21_io_en = gpr_wr_en[22]; // @[el2_lib.scala 511:17] + assign rvclkhdr_21_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_22_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_22_io_en = gpr_wr_en[23]; // @[el2_lib.scala 511:17] + assign rvclkhdr_22_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_23_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_23_io_en = gpr_wr_en[24]; // @[el2_lib.scala 511:17] + assign rvclkhdr_23_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_24_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_24_io_en = gpr_wr_en[25]; // @[el2_lib.scala 511:17] + assign rvclkhdr_24_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_25_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_25_io_en = gpr_wr_en[26]; // @[el2_lib.scala 511:17] + assign rvclkhdr_25_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_26_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_26_io_en = gpr_wr_en[27]; // @[el2_lib.scala 511:17] + assign rvclkhdr_26_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_27_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_27_io_en = gpr_wr_en[28]; // @[el2_lib.scala 511:17] + assign rvclkhdr_27_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_28_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_28_io_en = gpr_wr_en[29]; // @[el2_lib.scala 511:17] + assign rvclkhdr_28_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_29_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_29_io_en = gpr_wr_en[30]; // @[el2_lib.scala 511:17] + assign rvclkhdr_29_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_30_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_30_io_en = gpr_wr_en[31]; // @[el2_lib.scala 511:17] + assign rvclkhdr_30_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + gpr_out_1 = _RAND_0[31:0]; + _RAND_1 = {1{`RANDOM}}; + gpr_out_2 = _RAND_1[31:0]; + _RAND_2 = {1{`RANDOM}}; + gpr_out_3 = _RAND_2[31:0]; + _RAND_3 = {1{`RANDOM}}; + gpr_out_4 = _RAND_3[31:0]; + _RAND_4 = {1{`RANDOM}}; + gpr_out_5 = _RAND_4[31:0]; + _RAND_5 = {1{`RANDOM}}; + gpr_out_6 = _RAND_5[31:0]; + _RAND_6 = {1{`RANDOM}}; + gpr_out_7 = _RAND_6[31:0]; + _RAND_7 = {1{`RANDOM}}; + gpr_out_8 = _RAND_7[31:0]; + _RAND_8 = {1{`RANDOM}}; + gpr_out_9 = _RAND_8[31:0]; + _RAND_9 = {1{`RANDOM}}; + gpr_out_10 = _RAND_9[31:0]; + _RAND_10 = {1{`RANDOM}}; + gpr_out_11 = _RAND_10[31:0]; + _RAND_11 = {1{`RANDOM}}; + gpr_out_12 = _RAND_11[31:0]; + _RAND_12 = {1{`RANDOM}}; + gpr_out_13 = _RAND_12[31:0]; + _RAND_13 = {1{`RANDOM}}; + gpr_out_14 = _RAND_13[31:0]; + _RAND_14 = {1{`RANDOM}}; + gpr_out_15 = _RAND_14[31:0]; + _RAND_15 = {1{`RANDOM}}; + gpr_out_16 = _RAND_15[31:0]; + _RAND_16 = {1{`RANDOM}}; + gpr_out_17 = _RAND_16[31:0]; + _RAND_17 = {1{`RANDOM}}; + gpr_out_18 = _RAND_17[31:0]; + _RAND_18 = {1{`RANDOM}}; + gpr_out_19 = _RAND_18[31:0]; + _RAND_19 = {1{`RANDOM}}; + gpr_out_20 = _RAND_19[31:0]; + _RAND_20 = {1{`RANDOM}}; + gpr_out_21 = _RAND_20[31:0]; + _RAND_21 = {1{`RANDOM}}; + gpr_out_22 = _RAND_21[31:0]; + _RAND_22 = {1{`RANDOM}}; + gpr_out_23 = _RAND_22[31:0]; + _RAND_23 = {1{`RANDOM}}; + gpr_out_24 = _RAND_23[31:0]; + _RAND_24 = {1{`RANDOM}}; + gpr_out_25 = _RAND_24[31:0]; + _RAND_25 = {1{`RANDOM}}; + gpr_out_26 = _RAND_25[31:0]; + _RAND_26 = {1{`RANDOM}}; + gpr_out_27 = _RAND_26[31:0]; + _RAND_27 = {1{`RANDOM}}; + gpr_out_28 = _RAND_27[31:0]; + _RAND_28 = {1{`RANDOM}}; + gpr_out_29 = _RAND_28[31:0]; + _RAND_29 = {1{`RANDOM}}; + gpr_out_30 = _RAND_29[31:0]; + _RAND_30 = {1{`RANDOM}}; + gpr_out_31 = _RAND_30[31:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + gpr_out_1 = 32'h0; + end + if (reset) begin + gpr_out_2 = 32'h0; + end + if (reset) begin + gpr_out_3 = 32'h0; + end + if (reset) begin + gpr_out_4 = 32'h0; + end + if (reset) begin + gpr_out_5 = 32'h0; + end + if (reset) begin + gpr_out_6 = 32'h0; + end + if (reset) begin + gpr_out_7 = 32'h0; + end + if (reset) begin + gpr_out_8 = 32'h0; + end + if (reset) begin + gpr_out_9 = 32'h0; + end + if (reset) begin + gpr_out_10 = 32'h0; + end + if (reset) begin + gpr_out_11 = 32'h0; + end + if (reset) begin + gpr_out_12 = 32'h0; + end + if (reset) begin + gpr_out_13 = 32'h0; + end + if (reset) begin + gpr_out_14 = 32'h0; + end + if (reset) begin + gpr_out_15 = 32'h0; + end + if (reset) begin + gpr_out_16 = 32'h0; + end + if (reset) begin + gpr_out_17 = 32'h0; + end + if (reset) begin + gpr_out_18 = 32'h0; + end + if (reset) begin + gpr_out_19 = 32'h0; + end + if (reset) begin + gpr_out_20 = 32'h0; + end + if (reset) begin + gpr_out_21 = 32'h0; + end + if (reset) begin + gpr_out_22 = 32'h0; + end + if (reset) begin + gpr_out_23 = 32'h0; + end + if (reset) begin + gpr_out_24 = 32'h0; + end + if (reset) begin + gpr_out_25 = 32'h0; + end + if (reset) begin + gpr_out_26 = 32'h0; + end + if (reset) begin + gpr_out_27 = 32'h0; + end + if (reset) begin + gpr_out_28 = 32'h0; + end + if (reset) begin + gpr_out_29 = 32'h0; + end + if (reset) begin + gpr_out_30 = 32'h0; + end + if (reset) begin + gpr_out_31 = 32'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_1 <= 32'h0; + end else begin + gpr_out_1 <= _T_12 | _T_15; + end + end + always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_2 <= 32'h0; + end else begin + gpr_out_2 <= _T_29 | _T_32; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_3 <= 32'h0; + end else begin + gpr_out_3 <= _T_46 | _T_49; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_4 <= 32'h0; + end else begin + gpr_out_4 <= _T_63 | _T_66; + end + end + always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_5 <= 32'h0; + end else begin + gpr_out_5 <= _T_80 | _T_83; + end + end + always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_6 <= 32'h0; + end else begin + gpr_out_6 <= _T_97 | _T_100; + end + end + always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_7 <= 32'h0; + end else begin + gpr_out_7 <= _T_114 | _T_117; + end + end + always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_8 <= 32'h0; + end else begin + gpr_out_8 <= _T_131 | _T_134; + end + end + always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_9 <= 32'h0; + end else begin + gpr_out_9 <= _T_148 | _T_151; + end + end + always @(posedge rvclkhdr_9_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_10 <= 32'h0; + end else begin + gpr_out_10 <= _T_165 | _T_168; + end + end + always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_11 <= 32'h0; + end else begin + gpr_out_11 <= _T_182 | _T_185; + end + end + always @(posedge rvclkhdr_11_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_12 <= 32'h0; + end else begin + gpr_out_12 <= _T_199 | _T_202; + end + end + always @(posedge rvclkhdr_12_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_13 <= 32'h0; + end else begin + gpr_out_13 <= _T_216 | _T_219; + end + end + always @(posedge rvclkhdr_13_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_14 <= 32'h0; + end else begin + gpr_out_14 <= _T_233 | _T_236; + end + end + always @(posedge rvclkhdr_14_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_15 <= 32'h0; + end else begin + gpr_out_15 <= _T_250 | _T_253; + end + end + always @(posedge rvclkhdr_15_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_16 <= 32'h0; + end else begin + gpr_out_16 <= _T_267 | _T_270; + end + end + always @(posedge rvclkhdr_16_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_17 <= 32'h0; + end else begin + gpr_out_17 <= _T_284 | _T_287; + end + end + always @(posedge rvclkhdr_17_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_18 <= 32'h0; + end else begin + gpr_out_18 <= _T_301 | _T_304; + end + end + always @(posedge rvclkhdr_18_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_19 <= 32'h0; + end else begin + gpr_out_19 <= _T_318 | _T_321; + end + end + always @(posedge rvclkhdr_19_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_20 <= 32'h0; + end else begin + gpr_out_20 <= _T_335 | _T_338; + end + end + always @(posedge rvclkhdr_20_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_21 <= 32'h0; + end else begin + gpr_out_21 <= _T_352 | _T_355; + end + end + always @(posedge rvclkhdr_21_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_22 <= 32'h0; + end else begin + gpr_out_22 <= _T_369 | _T_372; + end + end + always @(posedge rvclkhdr_22_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_23 <= 32'h0; + end else begin + gpr_out_23 <= _T_386 | _T_389; + end + end + always @(posedge rvclkhdr_23_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_24 <= 32'h0; + end else begin + gpr_out_24 <= _T_403 | _T_406; + end + end + always @(posedge rvclkhdr_24_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_25 <= 32'h0; + end else begin + gpr_out_25 <= _T_420 | _T_423; + end + end + always @(posedge rvclkhdr_25_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_26 <= 32'h0; + end else begin + gpr_out_26 <= _T_437 | _T_440; + end + end + always @(posedge rvclkhdr_26_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_27 <= 32'h0; + end else begin + gpr_out_27 <= _T_454 | _T_457; + end + end + always @(posedge rvclkhdr_27_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_28 <= 32'h0; + end else begin + gpr_out_28 <= _T_471 | _T_474; + end + end + always @(posedge rvclkhdr_28_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_29 <= 32'h0; + end else begin + gpr_out_29 <= _T_488 | _T_491; + end + end + always @(posedge rvclkhdr_29_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_30 <= 32'h0; + end else begin + gpr_out_30 <= _T_505 | _T_508; + end + end + always @(posedge rvclkhdr_30_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_31 <= 32'h0; + end else begin + gpr_out_31 <= _T_522 | _T_525; + end + end +endmodule diff --git a/el2_dec_ib_ctl.anno.json b/el2_dec_ib_ctl.anno.json new file mode 100644 index 00000000..2f147f79 --- /dev/null +++ b/el2_dec_ib_ctl.anno.json @@ -0,0 +1,189 @@ +[ + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_debug_wdata_rs1_d", + "sources":[ + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_write", + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_type", + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_valid" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_brp_bits_way", + "sources":[ + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_i0_brp_bits_way" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_brp_bits_br_error", + "sources":[ + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_i0_brp_bits_br_error" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_dbecc_d", + "sources":[ + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_ifu_i0_dbecc" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_pc_d", + "sources":[ + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_ifu_i0_pc" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_brp_bits_hist", + "sources":[ + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_brp_bits_toffset", + "sources":[ + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_i0_brp_bits_toffset" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_icaf_f1_d", + "sources":[ + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_ifu_i0_icaf_f1" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_bp_btag", + "sources":[ + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_ifu_i0_bp_btag" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_pc4_d", + "sources":[ + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_ifu_i0_pc4" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_ib0_valid_d", + "sources":[ + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_ifu_i0_valid", + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_valid", + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_type" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_instr_d", + "sources":[ + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_ifu_i0_instr", + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_valid", + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_type", + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_addr", + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_write" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_brp_bits_prett", + "sources":[ + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_i0_brp_bits_prett" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_bp_fghr", + "sources":[ + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_ifu_i0_bp_fghr" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_icaf_d", + "sources":[ + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_ifu_i0_icaf" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_brp_bits_br_start_error", + "sources":[ + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_i0_brp_bits_br_start_error" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_brp_bits_ret", + "sources":[ + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_i0_brp_bits_ret" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_bp_index", + "sources":[ + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_ifu_i0_bp_index" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_icaf_type_d", + "sources":[ + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_ifu_i0_icaf_type" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_brp_valid", + "sources":[ + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_i0_brp_valid" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_brp_bits_bank", + "sources":[ + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_i0_brp_bits_bank" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_debug_fence_d", + "sources":[ + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_write", + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_type", + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_addr", + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_valid" + ] + }, + { + "class":"logger.LogLevelAnnotation", + "globalLogLevel":{ + + } + }, + { + "class":"firrtl.EmitCircuitAnnotation", + "emitter":"firrtl.VerilogEmitter" + }, + { + "class":"firrtl.options.TargetDirAnnotation", + "directory":"." + }, + { + "class":"firrtl.options.OutputAnnotationFileAnnotation", + "file":"el2_dec_ib_ctl" + }, + { + "class":"firrtl.transforms.BlackBoxTargetDirAnno", + "targetDir":"." + } +] \ No newline at end of file diff --git a/el2_dec_ib_ctl.fir b/el2_dec_ib_ctl.fir new file mode 100644 index 00000000..52fed920 --- /dev/null +++ b/el2_dec_ib_ctl.fir @@ -0,0 +1,71 @@ +;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 +circuit el2_dec_ib_ctl : + module el2_dec_ib_ctl : + input clock : Clock + input reset : UInt<1> + output io : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>, flip i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, flip ifu_i0_bp_index : UInt<8>, flip ifu_i0_bp_fghr : UInt<8>, flip ifu_i0_bp_btag : UInt<5>, flip ifu_i0_pc4 : UInt<1>, flip ifu_i0_valid : UInt<1>, flip ifu_i0_icaf : UInt<1>, flip ifu_i0_icaf_type : UInt<2>, flip ifu_i0_icaf_f1 : UInt<1>, flip ifu_i0_dbecc : UInt<1>, flip ifu_i0_instr : UInt<32>, flip ifu_i0_pc : UInt<31>, dec_ib0_valid_d : UInt<1>, dec_i0_icaf_type_d : UInt<2>, dec_i0_instr_d : UInt<32>, dec_i0_pc_d : UInt<31>, dec_i0_pc4_d : UInt<1>, dec_i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, dec_i0_bp_index : UInt<8>, dec_i0_bp_fghr : UInt<8>, dec_i0_bp_btag : UInt<5>, dec_i0_icaf_d : UInt<1>, dec_i0_icaf_f1_d : UInt<1>, dec_i0_dbecc_d : UInt<1>, dec_debug_wdata_rs1_d : UInt<1>, dec_debug_fence_d : UInt<1>} + + io.dec_i0_icaf_f1_d <= io.ifu_i0_icaf_f1 @[el2_dec_ib_ctl.scala 8:31] + io.dec_i0_dbecc_d <= io.ifu_i0_dbecc @[el2_dec_ib_ctl.scala 9:31] + io.dec_i0_icaf_d <= io.ifu_i0_icaf @[el2_dec_ib_ctl.scala 10:31] + io.dec_i0_pc_d <= io.ifu_i0_pc @[el2_dec_ib_ctl.scala 11:31] + io.dec_i0_pc4_d <= io.ifu_i0_pc4 @[el2_dec_ib_ctl.scala 12:31] + io.dec_i0_icaf_type_d <= io.ifu_i0_icaf_type @[el2_dec_ib_ctl.scala 13:31] + io.dec_i0_brp.bits.ret <= io.i0_brp.bits.ret @[el2_dec_ib_ctl.scala 14:31] + io.dec_i0_brp.bits.way <= io.i0_brp.bits.way @[el2_dec_ib_ctl.scala 14:31] + io.dec_i0_brp.bits.prett <= io.i0_brp.bits.prett @[el2_dec_ib_ctl.scala 14:31] + io.dec_i0_brp.bits.bank <= io.i0_brp.bits.bank @[el2_dec_ib_ctl.scala 14:31] + io.dec_i0_brp.bits.br_start_error <= io.i0_brp.bits.br_start_error @[el2_dec_ib_ctl.scala 14:31] + io.dec_i0_brp.bits.br_error <= io.i0_brp.bits.br_error @[el2_dec_ib_ctl.scala 14:31] + io.dec_i0_brp.bits.hist <= io.i0_brp.bits.hist @[el2_dec_ib_ctl.scala 14:31] + io.dec_i0_brp.bits.toffset <= io.i0_brp.bits.toffset @[el2_dec_ib_ctl.scala 14:31] + io.dec_i0_brp.valid <= io.i0_brp.valid @[el2_dec_ib_ctl.scala 14:31] + io.dec_i0_bp_index <= io.ifu_i0_bp_index @[el2_dec_ib_ctl.scala 15:31] + io.dec_i0_bp_fghr <= io.ifu_i0_bp_fghr @[el2_dec_ib_ctl.scala 16:31] + io.dec_i0_bp_btag <= io.ifu_i0_bp_btag @[el2_dec_ib_ctl.scala 17:31] + node _T = neq(io.dbg_cmd_type, UInt<2>("h02")) @[el2_dec_ib_ctl.scala 31:60] + node debug_valid = and(io.dbg_cmd_valid, _T) @[el2_dec_ib_ctl.scala 31:41] + node _T_1 = eq(io.dbg_cmd_write, UInt<1>("h00")) @[el2_dec_ib_ctl.scala 32:38] + node debug_read = and(debug_valid, _T_1) @[el2_dec_ib_ctl.scala 32:36] + node debug_write = and(debug_valid, io.dbg_cmd_write) @[el2_dec_ib_ctl.scala 33:36] + node _T_2 = eq(io.dbg_cmd_type, UInt<1>("h00")) @[el2_dec_ib_ctl.scala 35:55] + node debug_read_gpr = and(debug_read, _T_2) @[el2_dec_ib_ctl.scala 35:37] + node _T_3 = eq(io.dbg_cmd_type, UInt<1>("h00")) @[el2_dec_ib_ctl.scala 36:55] + node debug_write_gpr = and(debug_write, _T_3) @[el2_dec_ib_ctl.scala 36:37] + node _T_4 = eq(io.dbg_cmd_type, UInt<1>("h01")) @[el2_dec_ib_ctl.scala 37:55] + node debug_read_csr = and(debug_read, _T_4) @[el2_dec_ib_ctl.scala 37:37] + node _T_5 = eq(io.dbg_cmd_type, UInt<1>("h01")) @[el2_dec_ib_ctl.scala 38:55] + node debug_write_csr = and(debug_write, _T_5) @[el2_dec_ib_ctl.scala 38:37] + node dreg = bits(io.dbg_cmd_addr, 4, 0) @[el2_dec_ib_ctl.scala 40:40] + node dcsr = bits(io.dbg_cmd_addr, 11, 0) @[el2_dec_ib_ctl.scala 41:40] + node _T_6 = bits(debug_read_gpr, 0, 0) @[el2_dec_ib_ctl.scala 44:20] + node _T_7 = mux(UInt<1>("h00"), UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12] + node _T_8 = cat(_T_7, dreg) @[Cat.scala 29:58] + node _T_9 = cat(_T_8, UInt<15>("h06033")) @[Cat.scala 29:58] + node _T_10 = bits(debug_write_gpr, 0, 0) @[el2_dec_ib_ctl.scala 45:21] + node _T_11 = cat(UInt<3>("h06"), dreg) @[Cat.scala 29:58] + node _T_12 = cat(_T_11, UInt<6>("h033")) @[Cat.scala 29:58] + node _T_13 = bits(debug_read_csr, 0, 0) @[el2_dec_ib_ctl.scala 46:20] + node _T_14 = cat(dcsr, UInt<14>("h02073")) @[Cat.scala 29:58] + node _T_15 = bits(debug_write_csr, 0, 0) @[el2_dec_ib_ctl.scala 47:21] + node _T_16 = cat(dcsr, UInt<13>("h01073")) @[Cat.scala 29:58] + node _T_17 = mux(_T_6, _T_9, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_18 = mux(_T_10, _T_12, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_19 = mux(_T_13, _T_14, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_20 = mux(_T_15, _T_16, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_21 = or(_T_17, _T_18) @[Mux.scala 27:72] + node _T_22 = or(_T_21, _T_19) @[Mux.scala 27:72] + node _T_23 = or(_T_22, _T_20) @[Mux.scala 27:72] + wire ib0_debug_in : UInt<32> @[Mux.scala 27:72] + ib0_debug_in <= _T_23 @[Mux.scala 27:72] + node _T_24 = or(debug_write_gpr, debug_write_csr) @[el2_dec_ib_ctl.scala 51:47] + io.dec_debug_wdata_rs1_d <= _T_24 @[el2_dec_ib_ctl.scala 51:28] + node _T_25 = eq(dcsr, UInt<11>("h07c4")) @[el2_dec_ib_ctl.scala 54:51] + node _T_26 = and(debug_write_csr, _T_25) @[el2_dec_ib_ctl.scala 54:43] + io.dec_debug_fence_d <= _T_26 @[el2_dec_ib_ctl.scala 54:24] + node _T_27 = or(io.ifu_i0_valid, debug_valid) @[el2_dec_ib_ctl.scala 56:41] + io.dec_ib0_valid_d <= _T_27 @[el2_dec_ib_ctl.scala 56:22] + node _T_28 = bits(debug_valid, 0, 0) @[el2_dec_ib_ctl.scala 57:41] + node _T_29 = mux(_T_28, ib0_debug_in, io.ifu_i0_instr) @[el2_dec_ib_ctl.scala 57:28] + io.dec_i0_instr_d <= _T_29 @[el2_dec_ib_ctl.scala 57:22] + diff --git a/el2_dec_ib_ctl.v b/el2_dec_ib_ctl.v new file mode 100644 index 00000000..f37d5012 --- /dev/null +++ b/el2_dec_ib_ctl.v @@ -0,0 +1,101 @@ +module el2_dec_ib_ctl( + input clock, + input reset, + input io_dbg_cmd_valid, + input io_dbg_cmd_write, + input [1:0] io_dbg_cmd_type, + input [31:0] io_dbg_cmd_addr, + input io_i0_brp_valid, + input [11:0] io_i0_brp_bits_toffset, + input [1:0] io_i0_brp_bits_hist, + input io_i0_brp_bits_br_error, + input io_i0_brp_bits_br_start_error, + input io_i0_brp_bits_bank, + input [30:0] io_i0_brp_bits_prett, + input io_i0_brp_bits_way, + input io_i0_brp_bits_ret, + input [7:0] io_ifu_i0_bp_index, + input [7:0] io_ifu_i0_bp_fghr, + input [4:0] io_ifu_i0_bp_btag, + input io_ifu_i0_pc4, + input io_ifu_i0_valid, + input io_ifu_i0_icaf, + input [1:0] io_ifu_i0_icaf_type, + input io_ifu_i0_icaf_f1, + input io_ifu_i0_dbecc, + input [31:0] io_ifu_i0_instr, + input [30:0] io_ifu_i0_pc, + output io_dec_ib0_valid_d, + output [1:0] io_dec_i0_icaf_type_d, + output [31:0] io_dec_i0_instr_d, + output [30:0] io_dec_i0_pc_d, + output io_dec_i0_pc4_d, + output io_dec_i0_brp_valid, + output [11:0] io_dec_i0_brp_bits_toffset, + output [1:0] io_dec_i0_brp_bits_hist, + output io_dec_i0_brp_bits_br_error, + output io_dec_i0_brp_bits_br_start_error, + output io_dec_i0_brp_bits_bank, + output [30:0] io_dec_i0_brp_bits_prett, + output io_dec_i0_brp_bits_way, + output io_dec_i0_brp_bits_ret, + output [7:0] io_dec_i0_bp_index, + output [7:0] io_dec_i0_bp_fghr, + output [4:0] io_dec_i0_bp_btag, + output io_dec_i0_icaf_d, + output io_dec_i0_icaf_f1_d, + output io_dec_i0_dbecc_d, + output io_dec_debug_wdata_rs1_d, + output io_dec_debug_fence_d +); + wire _T = io_dbg_cmd_type != 2'h2; // @[el2_dec_ib_ctl.scala 31:60] + wire debug_valid = io_dbg_cmd_valid & _T; // @[el2_dec_ib_ctl.scala 31:41] + wire _T_1 = ~io_dbg_cmd_write; // @[el2_dec_ib_ctl.scala 32:38] + wire debug_read = debug_valid & _T_1; // @[el2_dec_ib_ctl.scala 32:36] + wire debug_write = debug_valid & io_dbg_cmd_write; // @[el2_dec_ib_ctl.scala 33:36] + wire _T_2 = io_dbg_cmd_type == 2'h0; // @[el2_dec_ib_ctl.scala 35:55] + wire debug_read_gpr = debug_read & _T_2; // @[el2_dec_ib_ctl.scala 35:37] + wire debug_write_gpr = debug_write & _T_2; // @[el2_dec_ib_ctl.scala 36:37] + wire _T_4 = io_dbg_cmd_type == 2'h1; // @[el2_dec_ib_ctl.scala 37:55] + wire debug_read_csr = debug_read & _T_4; // @[el2_dec_ib_ctl.scala 37:37] + wire debug_write_csr = debug_write & _T_4; // @[el2_dec_ib_ctl.scala 38:37] + wire [4:0] dreg = io_dbg_cmd_addr[4:0]; // @[el2_dec_ib_ctl.scala 40:40] + wire [11:0] dcsr = io_dbg_cmd_addr[11:0]; // @[el2_dec_ib_ctl.scala 41:40] + wire [31:0] _T_9 = {12'h0,dreg,15'h6033}; // @[Cat.scala 29:58] + wire [13:0] _T_12 = {3'h6,dreg,6'h33}; // @[Cat.scala 29:58] + wire [25:0] _T_14 = {dcsr,14'h2073}; // @[Cat.scala 29:58] + wire [24:0] _T_16 = {dcsr,13'h1073}; // @[Cat.scala 29:58] + wire [31:0] _T_17 = debug_read_gpr ? _T_9 : 32'h0; // @[Mux.scala 27:72] + wire [13:0] _T_18 = debug_write_gpr ? _T_12 : 14'h0; // @[Mux.scala 27:72] + wire [25:0] _T_19 = debug_read_csr ? _T_14 : 26'h0; // @[Mux.scala 27:72] + wire [24:0] _T_20 = debug_write_csr ? _T_16 : 25'h0; // @[Mux.scala 27:72] + wire [31:0] _GEN_0 = {{18'd0}, _T_18}; // @[Mux.scala 27:72] + wire [31:0] _T_21 = _T_17 | _GEN_0; // @[Mux.scala 27:72] + wire [31:0] _GEN_1 = {{6'd0}, _T_19}; // @[Mux.scala 27:72] + wire [31:0] _T_22 = _T_21 | _GEN_1; // @[Mux.scala 27:72] + wire [31:0] _GEN_2 = {{7'd0}, _T_20}; // @[Mux.scala 27:72] + wire [31:0] ib0_debug_in = _T_22 | _GEN_2; // @[Mux.scala 27:72] + wire _T_25 = dcsr == 12'h7c4; // @[el2_dec_ib_ctl.scala 54:51] + assign io_dec_ib0_valid_d = io_ifu_i0_valid | debug_valid; // @[el2_dec_ib_ctl.scala 56:22] + assign io_dec_i0_icaf_type_d = io_ifu_i0_icaf_type; // @[el2_dec_ib_ctl.scala 13:31] + assign io_dec_i0_instr_d = debug_valid ? ib0_debug_in : io_ifu_i0_instr; // @[el2_dec_ib_ctl.scala 57:22] + assign io_dec_i0_pc_d = io_ifu_i0_pc; // @[el2_dec_ib_ctl.scala 11:31] + assign io_dec_i0_pc4_d = io_ifu_i0_pc4; // @[el2_dec_ib_ctl.scala 12:31] + assign io_dec_i0_brp_valid = io_i0_brp_valid; // @[el2_dec_ib_ctl.scala 14:31] + assign io_dec_i0_brp_bits_toffset = io_i0_brp_bits_toffset; // @[el2_dec_ib_ctl.scala 14:31] + assign io_dec_i0_brp_bits_hist = io_i0_brp_bits_hist; // @[el2_dec_ib_ctl.scala 14:31] + assign io_dec_i0_brp_bits_br_error = io_i0_brp_bits_br_error; // @[el2_dec_ib_ctl.scala 14:31] + assign io_dec_i0_brp_bits_br_start_error = io_i0_brp_bits_br_start_error; // @[el2_dec_ib_ctl.scala 14:31] + assign io_dec_i0_brp_bits_bank = io_i0_brp_bits_bank; // @[el2_dec_ib_ctl.scala 14:31] + assign io_dec_i0_brp_bits_prett = io_i0_brp_bits_prett; // @[el2_dec_ib_ctl.scala 14:31] + assign io_dec_i0_brp_bits_way = io_i0_brp_bits_way; // @[el2_dec_ib_ctl.scala 14:31] + assign io_dec_i0_brp_bits_ret = io_i0_brp_bits_ret; // @[el2_dec_ib_ctl.scala 14:31] + assign io_dec_i0_bp_index = io_ifu_i0_bp_index; // @[el2_dec_ib_ctl.scala 15:31] + assign io_dec_i0_bp_fghr = io_ifu_i0_bp_fghr; // @[el2_dec_ib_ctl.scala 16:31] + assign io_dec_i0_bp_btag = io_ifu_i0_bp_btag; // @[el2_dec_ib_ctl.scala 17:31] + assign io_dec_i0_icaf_d = io_ifu_i0_icaf; // @[el2_dec_ib_ctl.scala 10:31] + assign io_dec_i0_icaf_f1_d = io_ifu_i0_icaf_f1; // @[el2_dec_ib_ctl.scala 8:31] + assign io_dec_i0_dbecc_d = io_ifu_i0_dbecc; // @[el2_dec_ib_ctl.scala 9:31] + assign io_dec_debug_wdata_rs1_d = debug_write_gpr | debug_write_csr; // @[el2_dec_ib_ctl.scala 51:28] + assign io_dec_debug_fence_d = debug_write_csr & _T_25; // @[el2_dec_ib_ctl.scala 54:24] +endmodule diff --git a/el2_dec_tlu_ctl.anno.json b/el2_dec_tlu_ctl.anno.json new file mode 100644 index 00000000..a9e67b94 --- /dev/null +++ b/el2_dec_tlu_ctl.anno.json @@ -0,0 +1,514 @@ +[ + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_br0_r_pkt_bits_br_error", + "sources":[ + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_commit_cmt", + "sources":[ + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_valid", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_br0_r_pkt_bits_way", + "sources":[ + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_way_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_wr_pause_r", + "sources":[ + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fastint_stall_any", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_valid", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_load_any", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_store_any", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dbg_halt_req", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_ifu_miss_state_idle", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_rddata_d", + "sources":[ + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_core_id", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_rdaddr_d" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_dbg_cmd_done", + "sources":[ + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_kill_writeb_r", + "sources":[ + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_valid", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_perfcnt2", + "sources":[ + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_fence_i_r", + "sources":[ + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_valid", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_perfcnt1", + "sources":[ + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_presync_d", + "sources":[ + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_any_unq_d", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_unq_d", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_rdaddr_d" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_br0_r_pkt_bits_br_start_error", + "sources":[ + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_extint", + "sources":[ + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fastint_stall_any", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_valid", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_load_any", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_store_any", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dbg_halt_req", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_ifu_miss_state_idle", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_dbg_cmd_fail", + "sources":[ + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_dbg_cmd_done", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_valid", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_perfcnt0", + "sources":[ + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_leak_one_r", + "sources":[ + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_noredir_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_resume_ack", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_pause_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fastint_stall_any", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_valid", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dbg_halt_req", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_ifu_miss_state_idle", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_load_any", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_store_any" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_postsync_d", + "sources":[ + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_any_unq_d", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_rdaddr_d" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_path_r", + "sources":[ + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_rst_vec", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_pc_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_nmi_vec", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_addr", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_npc_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_valid", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fastint_stall_any", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_exc_type", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_load_any", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_store_any", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dbg_halt_req", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_ifu_miss_state_idle", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_legal_d", + "sources":[ + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_any_unq_d", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_unq_d", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_rdaddr_d" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_noredir_r", + "sources":[ + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_pause_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fastint_stall_any", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_valid", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dbg_halt_req", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_ifu_miss_state_idle", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_load_any", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_store_any" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_br0_r_pkt_bits_hist", + "sources":[ + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_hist_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_err_r", + "sources":[ + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fastint_stall_any", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_valid", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_load_any", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_store_any", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dbg_halt_req", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_ifu_miss_state_idle", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_perfcnt3", + "sources":[ + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_r", + "sources":[ + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fastint_stall_any", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_valid", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_load_any", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_store_any", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dbg_halt_req", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_ifu_miss_state_idle", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_br0_r_pkt_valid", + "sources":[ + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_valid_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_mp_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_pmu_i0_br_ataken" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_br0_r_pkt_bits_middle", + "sources":[ + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_middle_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_pause_r", + "sources":[ + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fastint_stall_any", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_load_any", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_store_any", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_valid", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dbg_halt_req", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_ifu_miss_state_idle", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any" + ] + }, + { + "class":"logger.LogLevelAnnotation", + "globalLogLevel":{ + + } + }, + { + "class":"firrtl.EmitCircuitAnnotation", + "emitter":"firrtl.VerilogEmitter" + }, + { + "class":"firrtl.transforms.BlackBoxResourceAnno", + "target":"el2_dec_tlu_ctl.gated_latch", + "resourceId":"/vsrc/gated_latch.v" + }, + { + "class":"firrtl.options.TargetDirAnnotation", + "directory":"." + }, + { + "class":"firrtl.options.OutputAnnotationFileAnnotation", + "file":"el2_dec_tlu_ctl" + }, + { + "class":"firrtl.transforms.BlackBoxTargetDirAnno", + "targetDir":"." + } +] \ No newline at end of file diff --git a/el2_dec_tlu_ctl.fir b/el2_dec_tlu_ctl.fir new file mode 100644 index 00000000..14c7a591 --- /dev/null +++ b/el2_dec_tlu_ctl.fir @@ -0,0 +1,8160 @@ +;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 +circuit el2_dec_tlu_ctl : + extmodule gated_latch : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_1 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_1 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_1 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_2 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_2 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_2 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_3 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_3 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_3 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + module el2_dec_timer_ctl : + input clock : Clock + input reset : AsyncReset + output io : {flip free_clk : Clock, flip scan_mode : UInt<1>, flip dec_csr_wen_r_mod : UInt<1>, flip dec_csr_rdaddr_d : UInt<12>, flip dec_csr_wraddr_r : UInt<12>, flip dec_csr_wrdata_r : UInt<32>, flip csr_mitctl0 : UInt<1>, flip csr_mitctl1 : UInt<1>, flip csr_mitb0 : UInt<1>, flip csr_mitb1 : UInt<1>, flip csr_mitcnt0 : UInt<1>, flip csr_mitcnt1 : UInt<1>, flip dec_pause_state : UInt<1>, flip dec_tlu_pmu_fw_halted : UInt<1>, flip internal_dbg_halt_timers : UInt<1>, dec_timer_rddata_d : UInt<32>, dec_timer_read_d : UInt<1>, dec_timer_t0_pulse : UInt<1>, dec_timer_t1_pulse : UInt<1>} + + wire mitctl1 : UInt<4> + mitctl1 <= UInt<1>("h00") + wire mitctl0 : UInt<3> + mitctl0 <= UInt<1>("h00") + wire mitb1 : UInt<32> + mitb1 <= UInt<1>("h00") + wire mitb0 : UInt<32> + mitb0 <= UInt<1>("h00") + wire mitcnt1 : UInt<32> + mitcnt1 <= UInt<1>("h00") + wire mitcnt0 : UInt<32> + mitcnt0 <= UInt<1>("h00") + node mit0_match_ns = geq(mitcnt0, mitb0) @[el2_dec_tlu_ctl.scala 2752:30] + node mit1_match_ns = geq(mitcnt1, mitb1) @[el2_dec_tlu_ctl.scala 2753:30] + io.dec_timer_t0_pulse <= mit0_match_ns @[el2_dec_tlu_ctl.scala 2755:25] + io.dec_timer_t1_pulse <= mit1_match_ns @[el2_dec_tlu_ctl.scala 2756:25] + node _T = eq(io.dec_csr_wraddr_r, UInt<12>("h07d2")) @[el2_dec_tlu_ctl.scala 2763:66] + node wr_mitcnt0_r = and(io.dec_csr_wen_r_mod, _T) @[el2_dec_tlu_ctl.scala 2763:43] + node _T_1 = bits(mitctl0, 0, 0) @[el2_dec_tlu_ctl.scala 2765:31] + node _T_2 = not(io.dec_pause_state) @[el2_dec_tlu_ctl.scala 2765:50] + node _T_3 = bits(mitctl0, 2, 2) @[el2_dec_tlu_ctl.scala 2765:79] + node _T_4 = or(_T_2, _T_3) @[el2_dec_tlu_ctl.scala 2765:70] + node _T_5 = and(_T_1, _T_4) @[el2_dec_tlu_ctl.scala 2765:47] + node _T_6 = not(io.dec_tlu_pmu_fw_halted) @[el2_dec_tlu_ctl.scala 2765:106] + node _T_7 = bits(mitctl0, 1, 1) @[el2_dec_tlu_ctl.scala 2765:141] + node _T_8 = or(_T_6, _T_7) @[el2_dec_tlu_ctl.scala 2765:132] + node _T_9 = and(_T_5, _T_8) @[el2_dec_tlu_ctl.scala 2765:103] + node _T_10 = not(io.internal_dbg_halt_timers) @[el2_dec_tlu_ctl.scala 2765:167] + node mitcnt0_inc_ok = and(_T_9, _T_10) @[el2_dec_tlu_ctl.scala 2765:165] + node _T_11 = add(mitcnt0, UInt<32>("h01")) @[el2_dec_tlu_ctl.scala 2766:29] + node mitcnt0_inc = tail(_T_11, 1) @[el2_dec_tlu_ctl.scala 2766:29] + node _T_12 = bits(mit0_match_ns, 0, 0) @[el2_dec_tlu_ctl.scala 2767:38] + node _T_13 = bits(wr_mitcnt0_r, 0, 0) @[el2_dec_tlu_ctl.scala 2767:68] + node _T_14 = mux(_T_13, io.dec_csr_wrdata_r, mitcnt0_inc) @[el2_dec_tlu_ctl.scala 2767:54] + node mitcnt0_ns = mux(_T_12, UInt<1>("h00"), _T_14) @[el2_dec_tlu_ctl.scala 2767:23] + node _T_15 = or(wr_mitcnt0_r, mitcnt0_inc_ok) @[el2_dec_tlu_ctl.scala 2768:59] + node _T_16 = or(_T_15, mit0_match_ns) @[el2_dec_tlu_ctl.scala 2768:76] + node _T_17 = bits(_T_16, 0, 0) @[el2_dec_tlu_ctl.scala 2768:93] + inst rvclkhdr of rvclkhdr @[el2_lib.scala 508:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr.io.en <= _T_17 @[el2_lib.scala 511:17] + rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_18 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_18 <= mitcnt0_ns @[el2_lib.scala 514:16] + mitcnt0 <= _T_18 @[el2_dec_tlu_ctl.scala 2768:25] + node _T_19 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d5")) @[el2_dec_tlu_ctl.scala 2775:66] + node wr_mitcnt1_r = and(io.dec_csr_wen_r_mod, _T_19) @[el2_dec_tlu_ctl.scala 2775:43] + node _T_20 = bits(mitctl1, 0, 0) @[el2_dec_tlu_ctl.scala 2777:31] + node _T_21 = not(io.dec_pause_state) @[el2_dec_tlu_ctl.scala 2777:50] + node _T_22 = bits(mitctl1, 2, 2) @[el2_dec_tlu_ctl.scala 2777:79] + node _T_23 = or(_T_21, _T_22) @[el2_dec_tlu_ctl.scala 2777:70] + node _T_24 = and(_T_20, _T_23) @[el2_dec_tlu_ctl.scala 2777:47] + node _T_25 = not(io.dec_tlu_pmu_fw_halted) @[el2_dec_tlu_ctl.scala 2777:106] + node _T_26 = bits(mitctl1, 1, 1) @[el2_dec_tlu_ctl.scala 2777:141] + node _T_27 = or(_T_25, _T_26) @[el2_dec_tlu_ctl.scala 2777:132] + node _T_28 = and(_T_24, _T_27) @[el2_dec_tlu_ctl.scala 2777:103] + node _T_29 = not(io.internal_dbg_halt_timers) @[el2_dec_tlu_ctl.scala 2777:167] + node mitcnt1_inc_ok = and(_T_28, _T_29) @[el2_dec_tlu_ctl.scala 2777:165] + node _T_30 = mux(UInt<1>("h00"), UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12] + node _T_31 = bits(mitctl1, 3, 3) @[el2_dec_tlu_ctl.scala 2780:62] + node _T_32 = not(_T_31) @[el2_dec_tlu_ctl.scala 2780:54] + node _T_33 = or(_T_32, mit0_match_ns) @[el2_dec_tlu_ctl.scala 2780:66] + node _T_34 = cat(_T_30, _T_33) @[Cat.scala 29:58] + node _T_35 = add(mitcnt1, _T_34) @[el2_dec_tlu_ctl.scala 2780:29] + node mitcnt1_inc = tail(_T_35, 1) @[el2_dec_tlu_ctl.scala 2780:29] + node _T_36 = bits(mit1_match_ns, 0, 0) @[el2_dec_tlu_ctl.scala 2781:39] + node _T_37 = bits(wr_mitcnt1_r, 0, 0) @[el2_dec_tlu_ctl.scala 2781:69] + node _T_38 = mux(_T_37, io.dec_csr_wrdata_r, mitcnt1_inc) @[el2_dec_tlu_ctl.scala 2781:55] + node mitcnt1_ns = mux(_T_36, UInt<1>("h00"), _T_38) @[el2_dec_tlu_ctl.scala 2781:24] + node _T_39 = or(wr_mitcnt1_r, mitcnt1_inc_ok) @[el2_dec_tlu_ctl.scala 2782:52] + node _T_40 = or(_T_39, mit1_match_ns) @[el2_dec_tlu_ctl.scala 2782:69] + node _T_41 = bits(_T_40, 0, 0) @[el2_dec_tlu_ctl.scala 2782:86] + inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 508:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_1.io.en <= _T_41 @[el2_lib.scala 511:17] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_42 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_42 <= mitcnt1_ns @[el2_lib.scala 514:16] + mitcnt1 <= _T_42 @[el2_dec_tlu_ctl.scala 2782:17] + node _T_43 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d3")) @[el2_dec_tlu_ctl.scala 2789:64] + node wr_mitb0_r = and(io.dec_csr_wen_r_mod, _T_43) @[el2_dec_tlu_ctl.scala 2789:41] + node _T_44 = not(io.dec_csr_wrdata_r) @[el2_dec_tlu_ctl.scala 2790:30] + node _T_45 = bits(wr_mitb0_r, 0, 0) @[el2_dec_tlu_ctl.scala 2790:63] + inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 508:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_2.io.en <= _T_45 @[el2_lib.scala 511:17] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg mitb0_b : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + mitb0_b <= _T_44 @[el2_lib.scala 514:16] + node _T_46 = not(mitb0_b) @[el2_dec_tlu_ctl.scala 2791:14] + mitb0 <= _T_46 @[el2_dec_tlu_ctl.scala 2791:11] + node _T_47 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d6")) @[el2_dec_tlu_ctl.scala 2798:63] + node wr_mitb1_r = and(io.dec_csr_wen_r_mod, _T_47) @[el2_dec_tlu_ctl.scala 2798:41] + node _T_48 = not(io.dec_csr_wrdata_r) @[el2_dec_tlu_ctl.scala 2799:23] + node _T_49 = bits(wr_mitb1_r, 0, 0) @[el2_dec_tlu_ctl.scala 2799:56] + inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 508:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_3.io.en <= _T_49 @[el2_lib.scala 511:17] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg mitb1_b : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + mitb1_b <= _T_48 @[el2_lib.scala 514:16] + node _T_50 = not(mitb1_b) @[el2_dec_tlu_ctl.scala 2800:12] + mitb1 <= _T_50 @[el2_dec_tlu_ctl.scala 2800:9] + node _T_51 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d4")) @[el2_dec_tlu_ctl.scala 2811:66] + node wr_mitctl0_r = and(io.dec_csr_wen_r_mod, _T_51) @[el2_dec_tlu_ctl.scala 2811:43] + node _T_52 = bits(wr_mitctl0_r, 0, 0) @[el2_dec_tlu_ctl.scala 2812:45] + node _T_53 = bits(io.dec_csr_wrdata_r, 2, 0) @[el2_dec_tlu_ctl.scala 2812:72] + node _T_54 = bits(mitctl0, 2, 0) @[el2_dec_tlu_ctl.scala 2812:86] + node mitctl0_ns = mux(_T_52, _T_53, _T_54) @[el2_dec_tlu_ctl.scala 2812:31] + node _T_55 = bits(mitctl0_ns, 0, 0) @[el2_dec_tlu_ctl.scala 2814:35] + node mitctl0_0_b_ns = not(_T_55) @[el2_dec_tlu_ctl.scala 2814:24] + reg mitctl0_0_b : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2815:54] + mitctl0_0_b <= mitctl0_0_b_ns @[el2_dec_tlu_ctl.scala 2815:54] + node _T_56 = bits(mitctl0_ns, 2, 1) @[el2_dec_tlu_ctl.scala 2816:78] + reg _T_57 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2816:67] + _T_57 <= _T_56 @[el2_dec_tlu_ctl.scala 2816:67] + node _T_58 = not(mitctl0_0_b) @[el2_dec_tlu_ctl.scala 2816:90] + node _T_59 = cat(_T_57, _T_58) @[Cat.scala 29:58] + mitctl0 <= _T_59 @[el2_dec_tlu_ctl.scala 2816:31] + node _T_60 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d7")) @[el2_dec_tlu_ctl.scala 2826:65] + node wr_mitctl1_r = and(io.dec_csr_wen_r_mod, _T_60) @[el2_dec_tlu_ctl.scala 2826:43] + node _T_61 = bits(wr_mitctl1_r, 0, 0) @[el2_dec_tlu_ctl.scala 2827:45] + node _T_62 = bits(io.dec_csr_wrdata_r, 3, 0) @[el2_dec_tlu_ctl.scala 2827:71] + node _T_63 = bits(mitctl1, 3, 0) @[el2_dec_tlu_ctl.scala 2827:85] + node mitctl1_ns = mux(_T_61, _T_62, _T_63) @[el2_dec_tlu_ctl.scala 2827:31] + node _T_64 = bits(mitctl1_ns, 0, 0) @[el2_dec_tlu_ctl.scala 2828:34] + node mitctl1_0_b_ns = not(_T_64) @[el2_dec_tlu_ctl.scala 2828:23] + reg mitctl1_0_b : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2829:49] + mitctl1_0_b <= mitctl1_0_b_ns @[el2_dec_tlu_ctl.scala 2829:49] + node _T_65 = bits(mitctl1_ns, 3, 1) @[el2_dec_tlu_ctl.scala 2830:57] + reg _T_66 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2830:46] + _T_66 <= _T_65 @[el2_dec_tlu_ctl.scala 2830:46] + node _T_67 = not(mitctl1_0_b) @[el2_dec_tlu_ctl.scala 2830:69] + node _T_68 = cat(_T_66, _T_67) @[Cat.scala 29:58] + mitctl1 <= _T_68 @[el2_dec_tlu_ctl.scala 2830:10] + node _T_69 = or(io.csr_mitcnt1, io.csr_mitcnt0) @[el2_dec_tlu_ctl.scala 2832:43] + node _T_70 = or(_T_69, io.csr_mitb1) @[el2_dec_tlu_ctl.scala 2832:60] + node _T_71 = or(_T_70, io.csr_mitb0) @[el2_dec_tlu_ctl.scala 2832:75] + node _T_72 = or(_T_71, io.csr_mitctl0) @[el2_dec_tlu_ctl.scala 2832:90] + node _T_73 = or(_T_72, io.csr_mitctl1) @[el2_dec_tlu_ctl.scala 2832:107] + io.dec_timer_read_d <= _T_73 @[el2_dec_tlu_ctl.scala 2832:25] + node _T_74 = bits(io.csr_mitcnt0, 0, 0) @[el2_dec_tlu_ctl.scala 2834:20] + node _T_75 = bits(mitcnt0, 31, 0) @[el2_dec_tlu_ctl.scala 2834:39] + node _T_76 = bits(io.csr_mitcnt1, 0, 0) @[el2_dec_tlu_ctl.scala 2835:20] + node _T_77 = bits(io.csr_mitb0, 0, 0) @[el2_dec_tlu_ctl.scala 2836:18] + node _T_78 = bits(io.csr_mitb1, 0, 0) @[el2_dec_tlu_ctl.scala 2837:18] + node _T_79 = bits(io.csr_mitctl0, 0, 0) @[el2_dec_tlu_ctl.scala 2838:20] + node _T_80 = mux(UInt<1>("h00"), UInt<29>("h01fffffff"), UInt<29>("h00")) @[Bitwise.scala 72:12] + node _T_81 = cat(_T_80, mitctl0) @[Cat.scala 29:58] + node _T_82 = bits(io.csr_mitctl1, 0, 0) @[el2_dec_tlu_ctl.scala 2839:20] + node _T_83 = mux(UInt<1>("h00"), UInt<28>("h0fffffff"), UInt<28>("h00")) @[Bitwise.scala 72:12] + node _T_84 = cat(_T_83, mitctl1) @[Cat.scala 29:58] + node _T_85 = mux(_T_74, _T_75, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_86 = mux(_T_76, mitcnt1, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_87 = mux(_T_77, mitb0, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_88 = mux(_T_78, mitb1, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_89 = mux(_T_79, _T_81, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_90 = mux(_T_82, _T_84, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_91 = or(_T_85, _T_86) @[Mux.scala 27:72] + node _T_92 = or(_T_91, _T_87) @[Mux.scala 27:72] + node _T_93 = or(_T_92, _T_88) @[Mux.scala 27:72] + node _T_94 = or(_T_93, _T_89) @[Mux.scala 27:72] + node _T_95 = or(_T_94, _T_90) @[Mux.scala 27:72] + wire _T_96 : UInt<32> @[Mux.scala 27:72] + _T_96 <= _T_95 @[Mux.scala 27:72] + io.dec_timer_rddata_d <= _T_96 @[el2_dec_tlu_ctl.scala 2833:33] + + extmodule gated_latch_4 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_4 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_4 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_5 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_5 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_5 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_6 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_6 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_6 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_7 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_7 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_7 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_8 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_8 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_8 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_9 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_9 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_9 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_10 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_10 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_10 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_11 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_11 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_11 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_12 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_12 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_12 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_13 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_13 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_13 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_14 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_14 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_14 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_15 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_15 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_15 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_16 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_16 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_16 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_17 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_17 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_17 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_18 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_18 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_18 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_19 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_19 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_19 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_20 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_20 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_20 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_21 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_21 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_21 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_22 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_22 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_22 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_23 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_23 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_23 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_24 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_24 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_24 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_25 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_25 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_25 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_26 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_26 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_26 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_27 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_27 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_27 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_28 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_28 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_28 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_29 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_29 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_29 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_30 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_30 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_30 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_31 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_31 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_31 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_32 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_32 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_32 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_33 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_33 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_33 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_34 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_34 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_34 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_35 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_35 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_35 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_36 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_36 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_36 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_37 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_37 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_37 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_38 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_38 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_38 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_39 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_39 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_39 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_40 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_40 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_40 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_41 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_41 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_41 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_42 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_42 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_42 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + module csr_tlu : + input clock : Clock + input reset : AsyncReset + output io : {flip free_clk : Clock, flip active_clk : Clock, flip scan_mode : UInt<1>, flip dec_csr_wrdata_r : UInt<32>, flip dec_csr_wraddr_r : UInt<12>, flip dec_csr_rdaddr_d : UInt<12>, flip dec_csr_wen_unq_d : UInt<1>, flip dec_i0_decode_d : UInt<1>, dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip ifu_ic_debug_rd_data_valid : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip ifu_pmu_bus_trxn : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dec_pmu_presync_stall : UInt<1>, flip dec_pmu_postsync_stall : UInt<1>, flip dec_pmu_decode_stall : UInt<1>, flip ifu_pmu_fetch_stall : UInt<1>, flip dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, flip exu_pmu_i0_br_ataken : UInt<1>, flip exu_pmu_i0_br_misp : UInt<1>, flip dec_pmu_instr_decoded : UInt<1>, flip ifu_pmu_instr_aligned : UInt<1>, flip exu_pmu_i0_pc4 : UInt<1>, flip ifu_pmu_ic_miss : UInt<1>, flip ifu_pmu_ic_hit : UInt<1>, dec_tlu_int_valid_wb1 : UInt<1>, dec_tlu_i0_exc_valid_wb1 : UInt<1>, dec_tlu_i0_valid_wb1 : UInt<1>, flip dec_csr_wen_r : UInt<1>, dec_tlu_mtval_wb1 : UInt<32>, dec_tlu_exc_cause_wb1 : UInt<5>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, flip dec_tlu_dbg_halted : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip lsu_pmu_bus_busy : UInt<1>, flip dec_tlu_i0_pc_r : UInt<31>, flip dec_tlu_i0_valid_r : UInt<1>, flip dec_csr_stall_int_ff : UInt<1>, flip dec_csr_any_unq_d : UInt<1>, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_dec_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>, dec_csr_rddata_d : UInt<32>, dec_tlu_pipelining_disable : UInt<1>, dec_tlu_wr_pause_r : UInt<1>, flip ifu_pmu_bus_busy : UInt<1>, flip lsu_pmu_bus_error : UInt<1>, flip ifu_pmu_bus_error : UInt<1>, flip lsu_pmu_bus_misaligned : UInt<1>, flip lsu_pmu_bus_trxn : UInt<1>, flip ifu_ic_debug_rd_data : UInt<71>, dec_tlu_meipt : UInt<4>, flip pic_pl : UInt<4>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meihap : UInt<30>, flip pic_claimid : UInt<8>, flip iccm_dma_sb_error : UInt<1>, flip lsu_imprecise_error_addr_any : UInt<32>, flip lsu_imprecise_error_load_any : UInt<1>, flip lsu_imprecise_error_store_any : UInt<1>, dec_tlu_mrac_ff : UInt<32>, dec_tlu_wb_coalescing_disable : UInt<1>, dec_tlu_bpred_disable : UInt<1>, dec_tlu_sideeffect_posted_disable : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, dec_tlu_external_ldfwd_disable : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, flip dec_illegal_inst : UInt<32>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, flip mexintpend : UInt<1>, flip exu_npc_r : UInt<31>, flip mpc_reset_run_req : UInt<1>, flip rst_vec : UInt<31>, flip core_id : UInt<28>, flip dec_timer_rddata_d : UInt<32>, flip dec_timer_read_d : UInt<1>, dec_csr_wen_r_mod : UInt<1>, flip rfpc_i0_r : UInt<1>, flip i0_trigger_hit_r : UInt<1>, fw_halt_req : UInt<1>, mstatus : UInt<2>, flip exc_or_int_valid_r : UInt<1>, flip mret_r : UInt<1>, mstatus_mie_ns : UInt<1>, flip dcsr_single_step_running_f : UInt<1>, dcsr : UInt<16>, mtvec : UInt<31>, mip : UInt<6>, flip dec_timer_t0_pulse : UInt<1>, flip dec_timer_t1_pulse : UInt<1>, flip timer_int_sync : UInt<1>, flip soft_int_sync : UInt<1>, mie_ns : UInt<6>, flip csr_wr_clk : Clock, flip ebreak_to_debug_mode_r : UInt<1>, flip dec_tlu_pmu_fw_halted : UInt<1>, flip lsu_fir_error : UInt<2>, npc_r : UInt<31>, flip tlu_flush_lower_r_d1 : UInt<1>, flip dec_tlu_flush_noredir_r_d1 : UInt<1>, flip tlu_flush_path_r_d1 : UInt<31>, npc_r_d1 : UInt<31>, flip reset_delayed : UInt<1>, mepc : UInt<31>, flip interrupt_valid_r : UInt<1>, flip i0_exception_valid_r : UInt<1>, flip lsu_exc_valid_r : UInt<1>, flip mepc_trigger_hit_sel_pc_r : UInt<1>, flip e4e5_int_clk : Clock, flip lsu_i0_exc_r : UInt<1>, flip inst_acc_r : UInt<1>, flip inst_acc_second_r : UInt<1>, flip take_nmi : UInt<1>, flip lsu_error_pkt_addr_r : UInt<32>, flip exc_cause_r : UInt<5>, flip i0_valid_wb : UInt<1>, flip exc_or_int_valid_r_d1 : UInt<1>, flip interrupt_valid_r_d1 : UInt<1>, flip clk_override : UInt<1>, flip i0_exception_valid_r_d1 : UInt<1>, flip lsu_i0_exc_r_d1 : UInt<1>, flip exc_cause_wb : UInt<5>, flip nmi_lsu_store_type : UInt<1>, flip nmi_lsu_load_type : UInt<1>, flip tlu_i0_commit_cmt : UInt<1>, flip ebreak_r : UInt<1>, flip ecall_r : UInt<1>, flip illegal_r : UInt<1>, mdseac_locked_ns : UInt<1>, flip mdseac_locked_f : UInt<1>, flip nmi_int_detected_f : UInt<1>, flip internal_dbg_halt_mode_f2 : UInt<1>, flip ext_int_freeze_d1 : UInt<1>, flip ic_perr_r_d1 : UInt<1>, flip iccm_sbecc_r_d1 : UInt<1>, flip lsu_single_ecc_error_r_d1 : UInt<1>, flip ifu_miss_state_idle_f : UInt<1>, flip lsu_idle_any_f : UInt<1>, flip dbg_tlu_halted_f : UInt<1>, flip dbg_tlu_halted : UInt<1>, flip debug_halt_req_f : UInt<1>, force_halt : UInt<1>, flip take_ext_int_start : UInt<1>, flip trigger_hit_dmode_r_d1 : UInt<1>, flip trigger_hit_r_d1 : UInt<1>, flip dcsr_single_step_done_f : UInt<1>, flip ebreak_to_debug_mode_r_d1 : UInt<1>, flip debug_halt_req : UInt<1>, flip allow_dbg_halt_csr_write : UInt<1>, flip internal_dbg_halt_mode_f : UInt<1>, flip enter_debug_halt_req : UInt<1>, flip internal_dbg_halt_mode : UInt<1>, flip request_debug_mode_done : UInt<1>, flip request_debug_mode_r : UInt<1>, dpc : UInt<31>, flip update_hit_bit_r : UInt<4>, flip take_timer_int : UInt<1>, flip take_int_timer0_int : UInt<1>, flip take_int_timer1_int : UInt<1>, flip take_ext_int : UInt<1>, flip tlu_flush_lower_r : UInt<1>, flip dec_tlu_br0_error_r : UInt<1>, flip dec_tlu_br0_start_error_r : UInt<1>, flip lsu_pmu_load_external_r : UInt<1>, flip lsu_pmu_store_external_r : UInt<1>, flip csr_pkt : {csr_misa : UInt<1>, csr_mvendorid : UInt<1>, csr_marchid : UInt<1>, csr_mimpid : UInt<1>, csr_mhartid : UInt<1>, csr_mstatus : UInt<1>, csr_mtvec : UInt<1>, csr_mip : UInt<1>, csr_mie : UInt<1>, csr_mcyclel : UInt<1>, csr_mcycleh : UInt<1>, csr_minstretl : UInt<1>, csr_minstreth : UInt<1>, csr_mscratch : UInt<1>, csr_mepc : UInt<1>, csr_mcause : UInt<1>, csr_mscause : UInt<1>, csr_mtval : UInt<1>, csr_mrac : UInt<1>, csr_dmst : UInt<1>, csr_mdseac : UInt<1>, csr_meihap : UInt<1>, csr_meivt : UInt<1>, csr_meipt : UInt<1>, csr_meicurpl : UInt<1>, csr_meicidpl : UInt<1>, csr_dcsr : UInt<1>, csr_mcgc : UInt<1>, csr_mfdc : UInt<1>, csr_dpc : UInt<1>, csr_mtsel : UInt<1>, csr_mtdata1 : UInt<1>, csr_mtdata2 : UInt<1>, csr_mhpmc3 : UInt<1>, csr_mhpmc4 : UInt<1>, csr_mhpmc5 : UInt<1>, csr_mhpmc6 : UInt<1>, csr_mhpmc3h : UInt<1>, csr_mhpmc4h : UInt<1>, csr_mhpmc5h : UInt<1>, csr_mhpmc6h : UInt<1>, csr_mhpme3 : UInt<1>, csr_mhpme4 : UInt<1>, csr_mhpme5 : UInt<1>, csr_mhpme6 : UInt<1>, csr_mcountinhibit : UInt<1>, csr_mitctl0 : UInt<1>, csr_mitctl1 : UInt<1>, csr_mitb0 : UInt<1>, csr_mitb1 : UInt<1>, csr_mitcnt0 : UInt<1>, csr_mitcnt1 : UInt<1>, csr_mpmc : UInt<1>, csr_mcpc : UInt<1>, csr_meicpct : UInt<1>, csr_mdeau : UInt<1>, csr_micect : UInt<1>, csr_miccmect : UInt<1>, csr_mdccmect : UInt<1>, csr_mfdht : UInt<1>, csr_mfdhs : UInt<1>, csr_dicawics : UInt<1>, csr_dicad0h : UInt<1>, csr_dicad0 : UInt<1>, csr_dicad1 : UInt<1>, csr_dicago : UInt<1>, presync : UInt<1>, postsync : UInt<1>, legal : UInt<1>}, mtdata1_t : UInt<10>[4]} + + wire miccme_ce_req : UInt<1> + miccme_ce_req <= UInt<1>("h00") + wire mice_ce_req : UInt<1> + mice_ce_req <= UInt<1>("h00") + wire mdccme_ce_req : UInt<1> + mdccme_ce_req <= UInt<1>("h00") + wire pc_r_d1 : UInt<31> + pc_r_d1 <= UInt<1>("h00") + wire mpmc_b_ns : UInt<1> + mpmc_b_ns <= UInt<1>("h00") + wire mpmc_b : UInt<1> + mpmc_b <= UInt<1>("h00") + wire wr_mcycleh_r : UInt<1> + wr_mcycleh_r <= UInt<1>("h00") + wire mcycleh : UInt<32> + mcycleh <= UInt<1>("h00") + wire minstretl_inc : UInt<33> + minstretl_inc <= UInt<1>("h00") + wire wr_minstreth_r : UInt<1> + wr_minstreth_r <= UInt<1>("h00") + wire minstretl : UInt<32> + minstretl <= UInt<1>("h00") + wire minstreth_inc : UInt<32> + minstreth_inc <= UInt<1>("h00") + wire minstreth : UInt<32> + minstreth <= UInt<1>("h00") + wire mfdc_ns : UInt<15> + mfdc_ns <= UInt<1>("h00") + wire mfdc_int : UInt<15> + mfdc_int <= UInt<1>("h00") + wire mhpmc6_incr : UInt<64> + mhpmc6_incr <= UInt<1>("h00") + wire mhpmc5_incr : UInt<64> + mhpmc5_incr <= UInt<1>("h00") + wire mhpmc4_incr : UInt<64> + mhpmc4_incr <= UInt<1>("h00") + wire perfcnt_halted : UInt<1> + perfcnt_halted <= UInt<1>("h00") + wire mhpmc3_incr : UInt<64> + mhpmc3_incr <= UInt<1>("h00") + wire mhpme_vec : UInt<10>[4] @[el2_dec_tlu_ctl.scala 1474:41] + wire mtdata2_t : UInt<32>[4] @[el2_dec_tlu_ctl.scala 1475:65] + wire wr_meicpct_r : UInt<1> + wr_meicpct_r <= UInt<1>("h00") + wire force_halt_ctr_f : UInt<32> + force_halt_ctr_f <= UInt<1>("h00") + wire mdccmect_inc : UInt<27> + mdccmect_inc <= UInt<1>("h00") + wire miccmect_inc : UInt<27> + miccmect_inc <= UInt<1>("h00") + wire fw_halted : UInt<1> + fw_halted <= UInt<1>("h00") + wire micect_inc : UInt<27> + micect_inc <= UInt<1>("h00") + wire mdseac_en : UInt<1> + mdseac_en <= UInt<1>("h00") + wire mie : UInt<6> + mie <= UInt<1>("h00") + wire mcyclel : UInt<32> + mcyclel <= UInt<1>("h00") + wire mscratch : UInt<32> + mscratch <= UInt<1>("h00") + wire mcause : UInt<32> + mcause <= UInt<1>("h00") + wire mscause : UInt<4> + mscause <= UInt<1>("h00") + wire mtval : UInt<32> + mtval <= UInt<1>("h00") + wire meicurpl : UInt<4> + meicurpl <= UInt<1>("h00") + wire meicidpl : UInt<4> + meicidpl <= UInt<1>("h00") + wire meipt : UInt<4> + meipt <= UInt<1>("h00") + wire mfdc : UInt<19> + mfdc <= UInt<1>("h00") + wire mtsel : UInt<2> + mtsel <= UInt<1>("h00") + wire micect : UInt<32> + micect <= UInt<1>("h00") + wire miccmect : UInt<32> + miccmect <= UInt<1>("h00") + wire mdccmect : UInt<32> + mdccmect <= UInt<1>("h00") + wire mhpmc3h : UInt<32> + mhpmc3h <= UInt<1>("h00") + wire mhpmc3 : UInt<32> + mhpmc3 <= UInt<1>("h00") + wire mhpmc4h : UInt<32> + mhpmc4h <= UInt<1>("h00") + wire mhpmc4 : UInt<32> + mhpmc4 <= UInt<1>("h00") + wire mhpmc5h : UInt<32> + mhpmc5h <= UInt<1>("h00") + wire mhpmc5 : UInt<32> + mhpmc5 <= UInt<1>("h00") + wire mhpmc6h : UInt<32> + mhpmc6h <= UInt<1>("h00") + wire mhpmc6 : UInt<32> + mhpmc6 <= UInt<1>("h00") + wire mhpme3 : UInt<10> + mhpme3 <= UInt<1>("h00") + wire mhpme4 : UInt<10> + mhpme4 <= UInt<1>("h00") + wire mhpme5 : UInt<10> + mhpme5 <= UInt<1>("h00") + wire mhpme6 : UInt<10> + mhpme6 <= UInt<1>("h00") + wire mfdht : UInt<6> + mfdht <= UInt<1>("h00") + wire mfdhs : UInt<2> + mfdhs <= UInt<1>("h00") + wire mcountinhibit : UInt<7> + mcountinhibit <= UInt<1>("h00") + wire mpmc : UInt<1> + mpmc <= UInt<1>("h00") + wire dicad1 : UInt<32> + dicad1 <= UInt<1>("h00") + node _T = eq(io.i0_trigger_hit_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1530:46] + node _T_1 = and(io.dec_csr_wen_r, _T) @[el2_dec_tlu_ctl.scala 1530:44] + node _T_2 = eq(io.rfpc_i0_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1530:69] + node _T_3 = and(_T_1, _T_2) @[el2_dec_tlu_ctl.scala 1530:67] + io.dec_csr_wen_r_mod <= _T_3 @[el2_dec_tlu_ctl.scala 1530:24] + node _T_4 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1531:65] + node _T_5 = eq(_T_4, UInt<12>("h0300")) @[el2_dec_tlu_ctl.scala 1531:72] + node wr_mstatus_r = and(io.dec_csr_wen_r_mod, _T_5) @[el2_dec_tlu_ctl.scala 1531:43] + node _T_6 = eq(mpmc_b_ns, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1534:29] + node set_mie_pmu_fw_halt = and(_T_6, io.fw_halt_req) @[el2_dec_tlu_ctl.scala 1534:40] + node _T_7 = eq(wr_mstatus_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1537:6] + node _T_8 = and(_T_7, io.exc_or_int_valid_r) @[el2_dec_tlu_ctl.scala 1537:20] + node _T_9 = bits(_T_8, 0, 0) @[el2_dec_tlu_ctl.scala 1537:45] + node _T_10 = dshr(io.mstatus, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1537:69] + node _T_11 = bits(_T_10, 0, 0) @[el2_dec_tlu_ctl.scala 1537:69] + node _T_12 = and(wr_mstatus_r, io.exc_or_int_valid_r) @[el2_dec_tlu_ctl.scala 1538:19] + node _T_13 = bits(_T_12, 0, 0) @[el2_dec_tlu_ctl.scala 1538:44] + node _T_14 = bits(io.dec_csr_wrdata_r, 3, 3) @[el2_dec_tlu_ctl.scala 1538:77] + node _T_15 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1539:18] + node _T_16 = and(io.mret_r, _T_15) @[el2_dec_tlu_ctl.scala 1539:16] + node _T_17 = bits(_T_16, 0, 0) @[el2_dec_tlu_ctl.scala 1539:42] + node _T_18 = bits(io.mstatus, 1, 1) @[el2_dec_tlu_ctl.scala 1539:71] + node _T_19 = cat(UInt<1>("h01"), _T_18) @[Cat.scala 29:58] + node _T_20 = bits(set_mie_pmu_fw_halt, 0, 0) @[el2_dec_tlu_ctl.scala 1540:27] + node _T_21 = bits(io.mstatus, 1, 1) @[el2_dec_tlu_ctl.scala 1540:51] + node _T_22 = cat(_T_21, UInt<1>("h01")) @[Cat.scala 29:58] + node _T_23 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1541:21] + node _T_24 = and(wr_mstatus_r, _T_23) @[el2_dec_tlu_ctl.scala 1541:19] + node _T_25 = bits(_T_24, 0, 0) @[el2_dec_tlu_ctl.scala 1541:45] + node _T_26 = bits(io.dec_csr_wrdata_r, 7, 7) @[el2_dec_tlu_ctl.scala 1541:78] + node _T_27 = bits(io.dec_csr_wrdata_r, 3, 3) @[el2_dec_tlu_ctl.scala 1541:102] + node _T_28 = cat(_T_26, _T_27) @[Cat.scala 29:58] + node _T_29 = eq(wr_mstatus_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1542:6] + node _T_30 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1542:22] + node _T_31 = and(_T_29, _T_30) @[el2_dec_tlu_ctl.scala 1542:20] + node _T_32 = eq(io.mret_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1542:47] + node _T_33 = and(_T_31, _T_32) @[el2_dec_tlu_ctl.scala 1542:45] + node _T_34 = eq(set_mie_pmu_fw_halt, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1542:60] + node _T_35 = and(_T_33, _T_34) @[el2_dec_tlu_ctl.scala 1542:58] + node _T_36 = bits(_T_35, 0, 0) @[el2_dec_tlu_ctl.scala 1542:82] + node _T_37 = mux(_T_9, _T_11, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_38 = mux(_T_13, _T_14, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_39 = mux(_T_17, _T_19, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_40 = mux(_T_20, _T_22, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_41 = mux(_T_25, _T_28, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_42 = mux(_T_36, io.mstatus, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_43 = or(_T_37, _T_38) @[Mux.scala 27:72] + node _T_44 = or(_T_43, _T_39) @[Mux.scala 27:72] + node _T_45 = or(_T_44, _T_40) @[Mux.scala 27:72] + node _T_46 = or(_T_45, _T_41) @[Mux.scala 27:72] + node _T_47 = or(_T_46, _T_42) @[Mux.scala 27:72] + wire mstatus_ns : UInt<2> @[Mux.scala 27:72] + mstatus_ns <= _T_47 @[Mux.scala 27:72] + node _T_48 = dshr(io.mstatus, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1545:34] + node _T_49 = bits(_T_48, 0, 0) @[el2_dec_tlu_ctl.scala 1545:34] + node _T_50 = not(io.dcsr_single_step_running_f) @[el2_dec_tlu_ctl.scala 1545:51] + node _T_51 = bits(io.dcsr, 11, 11) @[el2_dec_tlu_ctl.scala 1545:91] + node _T_52 = or(_T_50, _T_51) @[el2_dec_tlu_ctl.scala 1545:82] + node _T_53 = and(_T_49, _T_52) @[el2_dec_tlu_ctl.scala 1545:48] + io.mstatus_mie_ns <= _T_53 @[el2_dec_tlu_ctl.scala 1545:21] + reg _T_54 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1547:12] + _T_54 <= mstatus_ns @[el2_dec_tlu_ctl.scala 1547:12] + io.mstatus <= _T_54 @[el2_dec_tlu_ctl.scala 1546:14] + node _T_55 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1556:63] + node _T_56 = eq(_T_55, UInt<12>("h0305")) @[el2_dec_tlu_ctl.scala 1556:70] + node wr_mtvec_r = and(io.dec_csr_wen_r_mod, _T_56) @[el2_dec_tlu_ctl.scala 1556:41] + node _T_57 = bits(io.dec_csr_wrdata_r, 31, 2) @[el2_dec_tlu_ctl.scala 1557:41] + node _T_58 = bits(io.dec_csr_wrdata_r, 0, 0) @[el2_dec_tlu_ctl.scala 1557:69] + node mtvec_ns = cat(_T_57, _T_58) @[Cat.scala 29:58] + node _T_59 = bits(wr_mtvec_r, 0, 0) @[el2_dec_tlu_ctl.scala 1558:43] + inst rvclkhdr of rvclkhdr_8 @[el2_lib.scala 508:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr.io.en <= _T_59 @[el2_lib.scala 511:17] + rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_60 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_60 <= mtvec_ns @[el2_lib.scala 514:16] + io.mtvec <= _T_60 @[el2_dec_tlu_ctl.scala 1558:12] + node _T_61 = or(mdccme_ce_req, miccme_ce_req) @[el2_dec_tlu_ctl.scala 1570:31] + node ce_int = or(_T_61, mice_ce_req) @[el2_dec_tlu_ctl.scala 1570:47] + node _T_62 = cat(io.mexintpend, io.timer_int_sync) @[Cat.scala 29:58] + node _T_63 = cat(_T_62, io.soft_int_sync) @[Cat.scala 29:58] + node _T_64 = cat(ce_int, io.dec_timer_t0_pulse) @[Cat.scala 29:58] + node _T_65 = cat(_T_64, io.dec_timer_t1_pulse) @[Cat.scala 29:58] + node mip_ns = cat(_T_65, _T_63) @[Cat.scala 29:58] + reg _T_66 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1574:12] + _T_66 <= mip_ns @[el2_dec_tlu_ctl.scala 1574:12] + io.mip <= _T_66 @[el2_dec_tlu_ctl.scala 1573:10] + node _T_67 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1586:61] + node _T_68 = eq(_T_67, UInt<12>("h0304")) @[el2_dec_tlu_ctl.scala 1586:68] + node wr_mie_r = and(io.dec_csr_wen_r_mod, _T_68) @[el2_dec_tlu_ctl.scala 1586:39] + node _T_69 = bits(wr_mie_r, 0, 0) @[el2_dec_tlu_ctl.scala 1587:29] + node _T_70 = bits(io.dec_csr_wrdata_r, 30, 28) @[el2_dec_tlu_ctl.scala 1587:60] + node _T_71 = bits(io.dec_csr_wrdata_r, 11, 11) @[el2_dec_tlu_ctl.scala 1587:89] + node _T_72 = bits(io.dec_csr_wrdata_r, 7, 7) @[el2_dec_tlu_ctl.scala 1587:114] + node _T_73 = bits(io.dec_csr_wrdata_r, 3, 3) @[el2_dec_tlu_ctl.scala 1587:138] + node _T_74 = cat(_T_72, _T_73) @[Cat.scala 29:58] + node _T_75 = cat(_T_70, _T_71) @[Cat.scala 29:58] + node _T_76 = cat(_T_75, _T_74) @[Cat.scala 29:58] + node _T_77 = mux(_T_69, _T_76, mie) @[el2_dec_tlu_ctl.scala 1587:19] + io.mie_ns <= _T_77 @[el2_dec_tlu_ctl.scala 1587:13] + reg _T_78 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1589:12] + _T_78 <= io.mie_ns @[el2_dec_tlu_ctl.scala 1589:12] + mie <= _T_78 @[el2_dec_tlu_ctl.scala 1588:7] + node _T_79 = bits(io.dcsr, 10, 10) @[el2_dec_tlu_ctl.scala 1596:64] + node kill_ebreak_count_r = and(io.ebreak_to_debug_mode_r, _T_79) @[el2_dec_tlu_ctl.scala 1596:55] + node _T_80 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1598:65] + node _T_81 = eq(_T_80, UInt<12>("h0b00")) @[el2_dec_tlu_ctl.scala 1598:72] + node wr_mcyclel_r = and(io.dec_csr_wen_r_mod, _T_81) @[el2_dec_tlu_ctl.scala 1598:43] + node _T_82 = bits(io.dcsr, 10, 10) @[el2_dec_tlu_ctl.scala 1600:81] + node _T_83 = and(io.dec_tlu_dbg_halted, _T_82) @[el2_dec_tlu_ctl.scala 1600:72] + node _T_84 = or(kill_ebreak_count_r, _T_83) @[el2_dec_tlu_ctl.scala 1600:47] + node _T_85 = or(_T_84, io.dec_tlu_pmu_fw_halted) @[el2_dec_tlu_ctl.scala 1600:95] + node _T_86 = bits(mcountinhibit, 0, 0) @[el2_dec_tlu_ctl.scala 1600:137] + node _T_87 = or(_T_85, _T_86) @[el2_dec_tlu_ctl.scala 1600:122] + node mcyclel_cout_in = not(_T_87) @[el2_dec_tlu_ctl.scala 1600:25] + wire mcyclel_inc : UInt<33> + mcyclel_inc <= UInt<1>("h00") + node _T_88 = cat(UInt<31>("h00"), mcyclel_cout_in) @[Cat.scala 29:58] + node _T_89 = add(mcyclel, _T_88) @[el2_dec_tlu_ctl.scala 1604:26] + node _T_90 = tail(_T_89, 1) @[el2_dec_tlu_ctl.scala 1604:26] + mcyclel_inc <= _T_90 @[el2_dec_tlu_ctl.scala 1604:15] + node _T_91 = bits(wr_mcyclel_r, 0, 0) @[el2_dec_tlu_ctl.scala 1605:37] + node mcyclel_ns = mux(_T_91, io.dec_csr_wrdata_r, mcyclel_inc) @[el2_dec_tlu_ctl.scala 1605:23] + node _T_92 = bits(mcyclel_inc, 32, 32) @[el2_dec_tlu_ctl.scala 1606:33] + node mcyclel_cout = bits(_T_92, 0, 0) @[el2_dec_tlu_ctl.scala 1606:38] + node _T_93 = or(wr_mcyclel_r, mcyclel_cout_in) @[el2_dec_tlu_ctl.scala 1607:47] + node _T_94 = bits(_T_93, 0, 0) @[el2_dec_tlu_ctl.scala 1607:73] + inst rvclkhdr_1 of rvclkhdr_9 @[el2_lib.scala 508:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_1.io.en <= _T_94 @[el2_lib.scala 511:17] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_95 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_95 <= mcyclel_ns @[el2_lib.scala 514:16] + mcyclel <= _T_95 @[el2_dec_tlu_ctl.scala 1607:11] + node _T_96 = eq(wr_mcycleh_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1608:72] + node _T_97 = and(mcyclel_cout, _T_96) @[el2_dec_tlu_ctl.scala 1608:70] + reg mcyclel_cout_f : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1608:55] + mcyclel_cout_f <= _T_97 @[el2_dec_tlu_ctl.scala 1608:55] + node _T_98 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1614:62] + node _T_99 = eq(_T_98, UInt<12>("h0b80")) @[el2_dec_tlu_ctl.scala 1614:69] + node _T_100 = and(io.dec_csr_wen_r_mod, _T_99) @[el2_dec_tlu_ctl.scala 1614:40] + wr_mcycleh_r <= _T_100 @[el2_dec_tlu_ctl.scala 1614:16] + node _T_101 = cat(UInt<31>("h00"), mcyclel_cout_f) @[Cat.scala 29:58] + node _T_102 = add(mcycleh, _T_101) @[el2_dec_tlu_ctl.scala 1616:29] + node mcycleh_inc = tail(_T_102, 1) @[el2_dec_tlu_ctl.scala 1616:29] + node _T_103 = bits(wr_mcycleh_r, 0, 0) @[el2_dec_tlu_ctl.scala 1617:37] + node mcycleh_ns = mux(_T_103, io.dec_csr_wrdata_r, mcycleh_inc) @[el2_dec_tlu_ctl.scala 1617:23] + node _T_104 = or(wr_mcycleh_r, mcyclel_cout_f) @[el2_dec_tlu_ctl.scala 1619:47] + node _T_105 = bits(_T_104, 0, 0) @[el2_dec_tlu_ctl.scala 1619:65] + inst rvclkhdr_2 of rvclkhdr_10 @[el2_lib.scala 508:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_2.io.en <= _T_105 @[el2_lib.scala 511:17] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_106 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_106 <= mcycleh_ns @[el2_lib.scala 514:16] + mcycleh <= _T_106 @[el2_dec_tlu_ctl.scala 1619:11] + node _T_107 = or(io.ebreak_r, io.ecall_r) @[el2_dec_tlu_ctl.scala 1633:73] + node _T_108 = or(_T_107, io.ebreak_to_debug_mode_r) @[el2_dec_tlu_ctl.scala 1633:86] + node _T_109 = or(_T_108, io.illegal_r) @[el2_dec_tlu_ctl.scala 1633:114] + node _T_110 = bits(mcountinhibit, 2, 2) @[el2_dec_tlu_ctl.scala 1633:144] + node _T_111 = or(_T_109, _T_110) @[el2_dec_tlu_ctl.scala 1633:129] + node _T_112 = bits(_T_111, 0, 0) @[el2_dec_tlu_ctl.scala 1633:149] + node _T_113 = not(_T_112) @[el2_dec_tlu_ctl.scala 1633:59] + node i0_valid_no_ebreak_ecall_r = and(io.tlu_i0_commit_cmt, _T_113) @[el2_dec_tlu_ctl.scala 1633:57] + node _T_114 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1635:67] + node _T_115 = eq(_T_114, UInt<12>("h0b02")) @[el2_dec_tlu_ctl.scala 1635:74] + node wr_minstretl_r = and(io.dec_csr_wen_r_mod, _T_115) @[el2_dec_tlu_ctl.scala 1635:45] + node _T_116 = cat(UInt<31>("h00"), i0_valid_no_ebreak_ecall_r) @[Cat.scala 29:58] + node _T_117 = add(minstretl, _T_116) @[el2_dec_tlu_ctl.scala 1637:30] + node _T_118 = tail(_T_117, 1) @[el2_dec_tlu_ctl.scala 1637:30] + minstretl_inc <= _T_118 @[el2_dec_tlu_ctl.scala 1637:17] + node minstretl_cout = bits(minstretl_inc, 32, 32) @[el2_dec_tlu_ctl.scala 1638:37] + node _T_119 = or(i0_valid_no_ebreak_ecall_r, wr_minstretl_r) @[el2_dec_tlu_ctl.scala 1639:53] + node minstret_enable = bits(_T_119, 0, 0) @[el2_dec_tlu_ctl.scala 1639:71] + node _T_120 = bits(wr_minstretl_r, 0, 0) @[el2_dec_tlu_ctl.scala 1641:41] + node minstretl_ns = mux(_T_120, io.dec_csr_wrdata_r, minstretl_inc) @[el2_dec_tlu_ctl.scala 1641:25] + node _T_121 = bits(minstret_enable, 0, 0) @[el2_dec_tlu_ctl.scala 1642:52] + inst rvclkhdr_3 of rvclkhdr_11 @[el2_lib.scala 508:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_3.io.en <= _T_121 @[el2_lib.scala 511:17] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_122 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_122 <= minstretl_ns @[el2_lib.scala 514:16] + minstretl <= _T_122 @[el2_dec_tlu_ctl.scala 1642:13] + reg minstret_enable_f : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1643:57] + minstret_enable_f <= minstret_enable @[el2_dec_tlu_ctl.scala 1643:57] + node _T_123 = not(wr_minstreth_r) @[el2_dec_tlu_ctl.scala 1644:76] + node _T_124 = and(minstretl_cout, _T_123) @[el2_dec_tlu_ctl.scala 1644:74] + reg minstretl_cout_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1644:57] + minstretl_cout_f <= _T_124 @[el2_dec_tlu_ctl.scala 1644:57] + node _T_125 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1652:65] + node _T_126 = eq(_T_125, UInt<12>("h0b82")) @[el2_dec_tlu_ctl.scala 1652:72] + node _T_127 = and(io.dec_csr_wen_r_mod, _T_126) @[el2_dec_tlu_ctl.scala 1652:43] + node _T_128 = bits(_T_127, 0, 0) @[el2_dec_tlu_ctl.scala 1652:88] + wr_minstreth_r <= _T_128 @[el2_dec_tlu_ctl.scala 1652:18] + node _T_129 = cat(UInt<31>("h00"), minstretl_cout_f) @[Cat.scala 29:58] + node _T_130 = add(minstreth, _T_129) @[el2_dec_tlu_ctl.scala 1655:30] + node _T_131 = tail(_T_130, 1) @[el2_dec_tlu_ctl.scala 1655:30] + minstreth_inc <= _T_131 @[el2_dec_tlu_ctl.scala 1655:17] + node _T_132 = bits(wr_minstreth_r, 0, 0) @[el2_dec_tlu_ctl.scala 1656:42] + node minstreth_ns = mux(_T_132, io.dec_csr_wrdata_r, minstreth_inc) @[el2_dec_tlu_ctl.scala 1656:26] + node _T_133 = or(minstret_enable_f, wr_minstreth_r) @[el2_dec_tlu_ctl.scala 1658:56] + node _T_134 = bits(_T_133, 0, 0) @[el2_dec_tlu_ctl.scala 1658:74] + inst rvclkhdr_4 of rvclkhdr_12 @[el2_lib.scala 508:23] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= reset + rvclkhdr_4.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_4.io.en <= _T_134 @[el2_lib.scala 511:17] + rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_135 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_135 <= minstreth_ns @[el2_lib.scala 514:16] + minstreth <= _T_135 @[el2_dec_tlu_ctl.scala 1658:13] + node _T_136 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1666:66] + node _T_137 = eq(_T_136, UInt<12>("h0340")) @[el2_dec_tlu_ctl.scala 1666:73] + node wr_mscratch_r = and(io.dec_csr_wen_r_mod, _T_137) @[el2_dec_tlu_ctl.scala 1666:44] + node _T_138 = bits(wr_mscratch_r, 0, 0) @[el2_dec_tlu_ctl.scala 1668:56] + inst rvclkhdr_5 of rvclkhdr_13 @[el2_lib.scala 508:23] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= reset + rvclkhdr_5.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_5.io.en <= _T_138 @[el2_lib.scala 511:17] + rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_139 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_139 <= io.dec_csr_wrdata_r @[el2_lib.scala 514:16] + mscratch <= _T_139 @[el2_dec_tlu_ctl.scala 1668:12] + node _T_140 = eq(io.dec_tlu_dbg_halted, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1677:23] + node _T_141 = eq(io.tlu_flush_lower_r_d1, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1677:48] + node _T_142 = and(_T_140, _T_141) @[el2_dec_tlu_ctl.scala 1677:46] + node sel_exu_npc_r = and(_T_142, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 1677:73] + node _T_143 = eq(io.dec_tlu_dbg_halted, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1678:25] + node _T_144 = and(_T_143, io.tlu_flush_lower_r_d1) @[el2_dec_tlu_ctl.scala 1678:48] + node _T_145 = eq(io.dec_tlu_flush_noredir_r_d1, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1678:76] + node sel_flush_npc_r = and(_T_144, _T_145) @[el2_dec_tlu_ctl.scala 1678:74] + node _T_146 = eq(sel_exu_npc_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1679:24] + node _T_147 = eq(sel_flush_npc_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1679:41] + node sel_hold_npc_r = and(_T_146, _T_147) @[el2_dec_tlu_ctl.scala 1679:39] + node _T_148 = bits(sel_exu_npc_r, 0, 0) @[el2_dec_tlu_ctl.scala 1682:19] + node _T_149 = eq(io.mpc_reset_run_req, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1683:6] + node _T_150 = and(_T_149, io.reset_delayed) @[el2_dec_tlu_ctl.scala 1683:28] + node _T_151 = bits(_T_150, 0, 0) @[el2_dec_tlu_ctl.scala 1683:48] + node _T_152 = bits(sel_flush_npc_r, 0, 0) @[el2_dec_tlu_ctl.scala 1684:21] + node _T_153 = bits(sel_hold_npc_r, 0, 0) @[el2_dec_tlu_ctl.scala 1685:20] + node _T_154 = mux(_T_148, io.exu_npc_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_155 = mux(_T_151, io.rst_vec, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_156 = mux(_T_152, io.tlu_flush_path_r_d1, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_157 = mux(_T_153, io.npc_r_d1, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_158 = or(_T_154, _T_155) @[Mux.scala 27:72] + node _T_159 = or(_T_158, _T_156) @[Mux.scala 27:72] + node _T_160 = or(_T_159, _T_157) @[Mux.scala 27:72] + wire _T_161 : UInt<31> @[Mux.scala 27:72] + _T_161 <= _T_160 @[Mux.scala 27:72] + io.npc_r <= _T_161 @[el2_dec_tlu_ctl.scala 1681:12] + node _T_162 = or(sel_exu_npc_r, sel_flush_npc_r) @[el2_dec_tlu_ctl.scala 1687:49] + node _T_163 = or(_T_162, io.reset_delayed) @[el2_dec_tlu_ctl.scala 1687:67] + node _T_164 = bits(_T_163, 0, 0) @[el2_dec_tlu_ctl.scala 1687:87] + inst rvclkhdr_6 of rvclkhdr_14 @[el2_lib.scala 508:23] + rvclkhdr_6.clock <= clock + rvclkhdr_6.reset <= reset + rvclkhdr_6.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_6.io.en <= _T_164 @[el2_lib.scala 511:17] + rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_165 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_165 <= io.npc_r @[el2_lib.scala 514:16] + io.npc_r_d1 <= _T_165 @[el2_dec_tlu_ctl.scala 1687:15] + node _T_166 = eq(io.dec_tlu_dbg_halted, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1690:22] + node _T_167 = and(_T_166, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 1690:45] + node pc0_valid_r = bits(_T_167, 0, 0) @[el2_dec_tlu_ctl.scala 1690:70] + node _T_168 = not(pc0_valid_r) @[el2_dec_tlu_ctl.scala 1694:5] + node _T_169 = mux(pc0_valid_r, io.dec_tlu_i0_pc_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_170 = mux(_T_168, pc_r_d1, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_171 = or(_T_169, _T_170) @[Mux.scala 27:72] + wire pc_r : UInt<31> @[Mux.scala 27:72] + pc_r <= _T_171 @[Mux.scala 27:72] + inst rvclkhdr_7 of rvclkhdr_15 @[el2_lib.scala 508:23] + rvclkhdr_7.clock <= clock + rvclkhdr_7.reset <= reset + rvclkhdr_7.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_7.io.en <= pc0_valid_r @[el2_lib.scala 511:17] + rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_172 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_172 <= pc_r @[el2_lib.scala 514:16] + pc_r_d1 <= _T_172 @[el2_dec_tlu_ctl.scala 1696:11] + node _T_173 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1698:62] + node _T_174 = eq(_T_173, UInt<12>("h0341")) @[el2_dec_tlu_ctl.scala 1698:69] + node wr_mepc_r = and(io.dec_csr_wen_r_mod, _T_174) @[el2_dec_tlu_ctl.scala 1698:40] + node _T_175 = or(io.i0_exception_valid_r, io.lsu_exc_valid_r) @[el2_dec_tlu_ctl.scala 1701:30] + node _T_176 = or(_T_175, io.mepc_trigger_hit_sel_pc_r) @[el2_dec_tlu_ctl.scala 1701:51] + node _T_177 = bits(_T_176, 0, 0) @[el2_dec_tlu_ctl.scala 1701:83] + node _T_178 = bits(io.interrupt_valid_r, 0, 0) @[el2_dec_tlu_ctl.scala 1702:28] + node _T_179 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1703:18] + node _T_180 = and(wr_mepc_r, _T_179) @[el2_dec_tlu_ctl.scala 1703:16] + node _T_181 = bits(_T_180, 0, 0) @[el2_dec_tlu_ctl.scala 1703:42] + node _T_182 = bits(io.dec_csr_wrdata_r, 31, 1) @[el2_dec_tlu_ctl.scala 1703:107] + node _T_183 = eq(wr_mepc_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1704:6] + node _T_184 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1704:19] + node _T_185 = and(_T_183, _T_184) @[el2_dec_tlu_ctl.scala 1704:17] + node _T_186 = bits(_T_185, 0, 0) @[el2_dec_tlu_ctl.scala 1704:43] + node _T_187 = mux(_T_177, pc_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_188 = mux(_T_178, io.npc_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_189 = mux(_T_181, _T_182, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_190 = mux(_T_186, io.mepc, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_191 = or(_T_187, _T_188) @[Mux.scala 27:72] + node _T_192 = or(_T_191, _T_189) @[Mux.scala 27:72] + node _T_193 = or(_T_192, _T_190) @[Mux.scala 27:72] + wire mepc_ns : UInt<31> @[Mux.scala 27:72] + mepc_ns <= _T_193 @[Mux.scala 27:72] + reg _T_194 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1706:48] + _T_194 <= mepc_ns @[el2_dec_tlu_ctl.scala 1706:48] + io.mepc <= _T_194 @[el2_dec_tlu_ctl.scala 1706:11] + node _T_195 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1713:64] + node _T_196 = eq(_T_195, UInt<12>("h0342")) @[el2_dec_tlu_ctl.scala 1713:71] + node wr_mcause_r = and(io.dec_csr_wen_r_mod, _T_196) @[el2_dec_tlu_ctl.scala 1713:42] + node _T_197 = and(io.exc_or_int_valid_r, io.take_nmi) @[el2_dec_tlu_ctl.scala 1714:52] + node mcause_sel_nmi_store = and(_T_197, io.nmi_lsu_store_type) @[el2_dec_tlu_ctl.scala 1714:66] + node _T_198 = and(io.exc_or_int_valid_r, io.take_nmi) @[el2_dec_tlu_ctl.scala 1715:51] + node mcause_sel_nmi_load = and(_T_198, io.nmi_lsu_load_type) @[el2_dec_tlu_ctl.scala 1715:65] + node _T_199 = and(io.exc_or_int_valid_r, io.take_nmi) @[el2_dec_tlu_ctl.scala 1716:50] + node _T_200 = orr(io.lsu_fir_error) @[el2_dec_tlu_ctl.scala 1716:83] + node mcause_sel_nmi_ext = and(_T_199, _T_200) @[el2_dec_tlu_ctl.scala 1716:64] + node _T_201 = andr(io.lsu_fir_error) @[el2_dec_tlu_ctl.scala 1722:52] + node _T_202 = bits(io.lsu_fir_error, 1, 1) @[el2_dec_tlu_ctl.scala 1722:75] + node _T_203 = bits(io.lsu_fir_error, 0, 0) @[el2_dec_tlu_ctl.scala 1722:98] + node _T_204 = not(_T_203) @[el2_dec_tlu_ctl.scala 1722:81] + node _T_205 = and(_T_202, _T_204) @[el2_dec_tlu_ctl.scala 1722:79] + node mcause_fir_error_type = cat(_T_201, _T_205) @[Cat.scala 29:58] + node _T_206 = bits(mcause_sel_nmi_store, 0, 0) @[el2_dec_tlu_ctl.scala 1725:26] + node _T_207 = bits(mcause_sel_nmi_load, 0, 0) @[el2_dec_tlu_ctl.scala 1726:25] + node _T_208 = bits(mcause_sel_nmi_ext, 0, 0) @[el2_dec_tlu_ctl.scala 1727:24] + node _T_209 = cat(UInt<28>("h0f000100"), UInt<2>("h00")) @[Cat.scala 29:58] + node _T_210 = cat(_T_209, mcause_fir_error_type) @[Cat.scala 29:58] + node _T_211 = not(io.take_nmi) @[el2_dec_tlu_ctl.scala 1728:30] + node _T_212 = and(io.exc_or_int_valid_r, _T_211) @[el2_dec_tlu_ctl.scala 1728:28] + node _T_213 = bits(_T_212, 0, 0) @[el2_dec_tlu_ctl.scala 1728:44] + node _T_214 = cat(io.interrupt_valid_r, UInt<26>("h00")) @[Cat.scala 29:58] + node _T_215 = cat(_T_214, io.exc_cause_r) @[Cat.scala 29:58] + node _T_216 = not(io.exc_or_int_valid_r) @[el2_dec_tlu_ctl.scala 1729:20] + node _T_217 = and(wr_mcause_r, _T_216) @[el2_dec_tlu_ctl.scala 1729:18] + node _T_218 = bits(_T_217, 0, 0) @[el2_dec_tlu_ctl.scala 1729:44] + node _T_219 = not(wr_mcause_r) @[el2_dec_tlu_ctl.scala 1730:6] + node _T_220 = not(io.exc_or_int_valid_r) @[el2_dec_tlu_ctl.scala 1730:21] + node _T_221 = and(_T_219, _T_220) @[el2_dec_tlu_ctl.scala 1730:19] + node _T_222 = bits(_T_221, 0, 0) @[el2_dec_tlu_ctl.scala 1730:45] + node _T_223 = mux(_T_206, UInt<32>("h0f0000000"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_224 = mux(_T_207, UInt<32>("h0f0000001"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_225 = mux(_T_208, _T_210, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_226 = mux(_T_213, _T_215, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_227 = mux(_T_218, io.dec_csr_wrdata_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_228 = mux(_T_222, mcause, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_229 = or(_T_223, _T_224) @[Mux.scala 27:72] + node _T_230 = or(_T_229, _T_225) @[Mux.scala 27:72] + node _T_231 = or(_T_230, _T_226) @[Mux.scala 27:72] + node _T_232 = or(_T_231, _T_227) @[Mux.scala 27:72] + node _T_233 = or(_T_232, _T_228) @[Mux.scala 27:72] + wire mcause_ns : UInt<32> @[Mux.scala 27:72] + mcause_ns <= _T_233 @[Mux.scala 27:72] + reg _T_234 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1732:47] + _T_234 <= mcause_ns @[el2_dec_tlu_ctl.scala 1732:47] + mcause <= _T_234 @[el2_dec_tlu_ctl.scala 1732:10] + node _T_235 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1739:65] + node _T_236 = eq(_T_235, UInt<12>("h07ff")) @[el2_dec_tlu_ctl.scala 1739:72] + node wr_mscause_r = and(io.dec_csr_wen_r_mod, _T_236) @[el2_dec_tlu_ctl.scala 1739:43] + node _T_237 = eq(io.dec_tlu_packet_r.icaf_type, UInt<2>("h00")) @[el2_dec_tlu_ctl.scala 1741:57] + node _T_238 = cat(UInt<2>("h00"), io.dec_tlu_packet_r.icaf_type) @[Cat.scala 29:58] + node ifu_mscause = mux(_T_237, UInt<4>("h09"), _T_238) @[el2_dec_tlu_ctl.scala 1741:25] + node _T_239 = bits(io.lsu_i0_exc_r, 0, 0) @[el2_dec_tlu_ctl.scala 1744:21] + node _T_240 = bits(io.i0_trigger_hit_r, 0, 0) @[el2_dec_tlu_ctl.scala 1745:25] + node _T_241 = bits(io.ebreak_r, 0, 0) @[el2_dec_tlu_ctl.scala 1746:17] + node _T_242 = bits(io.inst_acc_r, 0, 0) @[el2_dec_tlu_ctl.scala 1747:19] + node _T_243 = mux(_T_239, io.lsu_error_pkt_r.bits.mscause, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_244 = mux(_T_240, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_245 = mux(_T_241, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_246 = mux(_T_242, ifu_mscause, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_247 = or(_T_243, _T_244) @[Mux.scala 27:72] + node _T_248 = or(_T_247, _T_245) @[Mux.scala 27:72] + node _T_249 = or(_T_248, _T_246) @[Mux.scala 27:72] + wire mscause_type : UInt<4> @[Mux.scala 27:72] + mscause_type <= _T_249 @[Mux.scala 27:72] + node _T_250 = bits(io.exc_or_int_valid_r, 0, 0) @[el2_dec_tlu_ctl.scala 1751:29] + node _T_251 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1752:21] + node _T_252 = and(wr_mscause_r, _T_251) @[el2_dec_tlu_ctl.scala 1752:19] + node _T_253 = bits(_T_252, 0, 0) @[el2_dec_tlu_ctl.scala 1752:45] + node _T_254 = bits(io.dec_csr_wrdata_r, 3, 0) @[el2_dec_tlu_ctl.scala 1752:84] + node _T_255 = eq(wr_mscause_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1753:6] + node _T_256 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1753:22] + node _T_257 = and(_T_255, _T_256) @[el2_dec_tlu_ctl.scala 1753:20] + node _T_258 = bits(_T_257, 0, 0) @[el2_dec_tlu_ctl.scala 1753:46] + node _T_259 = mux(_T_250, mscause_type, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_260 = mux(_T_253, _T_254, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_261 = mux(_T_258, mscause, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_262 = or(_T_259, _T_260) @[Mux.scala 27:72] + node _T_263 = or(_T_262, _T_261) @[Mux.scala 27:72] + wire mscause_ns : UInt<4> @[Mux.scala 27:72] + mscause_ns <= _T_263 @[Mux.scala 27:72] + reg _T_264 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1755:48] + _T_264 <= mscause_ns @[el2_dec_tlu_ctl.scala 1755:48] + mscause <= _T_264 @[el2_dec_tlu_ctl.scala 1755:11] + node _T_265 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1762:63] + node _T_266 = eq(_T_265, UInt<12>("h0343")) @[el2_dec_tlu_ctl.scala 1762:70] + node wr_mtval_r = and(io.dec_csr_wen_r_mod, _T_266) @[el2_dec_tlu_ctl.scala 1762:41] + node _T_267 = not(io.inst_acc_second_r) @[el2_dec_tlu_ctl.scala 1763:84] + node _T_268 = and(io.inst_acc_r, _T_267) @[el2_dec_tlu_ctl.scala 1763:82] + node _T_269 = or(io.ebreak_r, _T_268) @[el2_dec_tlu_ctl.scala 1763:65] + node _T_270 = or(_T_269, io.mepc_trigger_hit_sel_pc_r) @[el2_dec_tlu_ctl.scala 1763:107] + node _T_271 = and(io.exc_or_int_valid_r, _T_270) @[el2_dec_tlu_ctl.scala 1763:50] + node _T_272 = not(io.take_nmi) @[el2_dec_tlu_ctl.scala 1763:141] + node mtval_capture_pc_r = and(_T_271, _T_272) @[el2_dec_tlu_ctl.scala 1763:139] + node _T_273 = and(io.inst_acc_r, io.inst_acc_second_r) @[el2_dec_tlu_ctl.scala 1764:73] + node _T_274 = and(io.exc_or_int_valid_r, _T_273) @[el2_dec_tlu_ctl.scala 1764:56] + node _T_275 = not(io.take_nmi) @[el2_dec_tlu_ctl.scala 1764:99] + node mtval_capture_pc_plus2_r = and(_T_274, _T_275) @[el2_dec_tlu_ctl.scala 1764:97] + node _T_276 = and(io.exc_or_int_valid_r, io.illegal_r) @[el2_dec_tlu_ctl.scala 1765:52] + node _T_277 = not(io.take_nmi) @[el2_dec_tlu_ctl.scala 1765:69] + node mtval_capture_inst_r = and(_T_276, _T_277) @[el2_dec_tlu_ctl.scala 1765:67] + node _T_278 = and(io.exc_or_int_valid_r, io.lsu_exc_valid_r) @[el2_dec_tlu_ctl.scala 1766:51] + node _T_279 = not(io.take_nmi) @[el2_dec_tlu_ctl.scala 1766:74] + node mtval_capture_lsu_r = and(_T_278, _T_279) @[el2_dec_tlu_ctl.scala 1766:72] + node _T_280 = not(mtval_capture_pc_r) @[el2_dec_tlu_ctl.scala 1767:47] + node _T_281 = and(io.exc_or_int_valid_r, _T_280) @[el2_dec_tlu_ctl.scala 1767:45] + node _T_282 = not(mtval_capture_inst_r) @[el2_dec_tlu_ctl.scala 1767:69] + node _T_283 = and(_T_281, _T_282) @[el2_dec_tlu_ctl.scala 1767:67] + node _T_284 = not(mtval_capture_lsu_r) @[el2_dec_tlu_ctl.scala 1767:93] + node _T_285 = and(_T_283, _T_284) @[el2_dec_tlu_ctl.scala 1767:91] + node _T_286 = not(io.mepc_trigger_hit_sel_pc_r) @[el2_dec_tlu_ctl.scala 1767:116] + node mtval_clear_r = and(_T_285, _T_286) @[el2_dec_tlu_ctl.scala 1767:114] + node _T_287 = bits(mtval_capture_pc_r, 0, 0) @[el2_dec_tlu_ctl.scala 1771:26] + node _T_288 = cat(pc_r, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_289 = bits(mtval_capture_pc_plus2_r, 0, 0) @[el2_dec_tlu_ctl.scala 1772:32] + node _T_290 = add(pc_r, UInt<31>("h01")) @[el2_dec_tlu_ctl.scala 1772:84] + node _T_291 = tail(_T_290, 1) @[el2_dec_tlu_ctl.scala 1772:84] + node _T_292 = cat(_T_291, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_293 = bits(mtval_capture_inst_r, 0, 0) @[el2_dec_tlu_ctl.scala 1773:28] + node _T_294 = bits(mtval_capture_lsu_r, 0, 0) @[el2_dec_tlu_ctl.scala 1774:27] + node _T_295 = not(io.interrupt_valid_r) @[el2_dec_tlu_ctl.scala 1775:19] + node _T_296 = and(wr_mtval_r, _T_295) @[el2_dec_tlu_ctl.scala 1775:17] + node _T_297 = bits(_T_296, 0, 0) @[el2_dec_tlu_ctl.scala 1775:49] + node _T_298 = not(io.take_nmi) @[el2_dec_tlu_ctl.scala 1776:6] + node _T_299 = not(wr_mtval_r) @[el2_dec_tlu_ctl.scala 1776:21] + node _T_300 = and(_T_298, _T_299) @[el2_dec_tlu_ctl.scala 1776:19] + node _T_301 = not(mtval_capture_pc_r) @[el2_dec_tlu_ctl.scala 1776:35] + node _T_302 = and(_T_300, _T_301) @[el2_dec_tlu_ctl.scala 1776:33] + node _T_303 = not(mtval_capture_inst_r) @[el2_dec_tlu_ctl.scala 1776:57] + node _T_304 = and(_T_302, _T_303) @[el2_dec_tlu_ctl.scala 1776:55] + node _T_305 = not(mtval_clear_r) @[el2_dec_tlu_ctl.scala 1776:81] + node _T_306 = and(_T_304, _T_305) @[el2_dec_tlu_ctl.scala 1776:79] + node _T_307 = not(mtval_capture_lsu_r) @[el2_dec_tlu_ctl.scala 1776:98] + node _T_308 = and(_T_306, _T_307) @[el2_dec_tlu_ctl.scala 1776:96] + node _T_309 = bits(_T_308, 0, 0) @[el2_dec_tlu_ctl.scala 1776:120] + node _T_310 = mux(_T_287, _T_288, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_311 = mux(_T_289, _T_292, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_312 = mux(_T_293, io.dec_illegal_inst, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_313 = mux(_T_294, io.lsu_error_pkt_addr_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_314 = mux(_T_297, io.dec_csr_wrdata_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_315 = mux(_T_309, mtval, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_316 = or(_T_310, _T_311) @[Mux.scala 27:72] + node _T_317 = or(_T_316, _T_312) @[Mux.scala 27:72] + node _T_318 = or(_T_317, _T_313) @[Mux.scala 27:72] + node _T_319 = or(_T_318, _T_314) @[Mux.scala 27:72] + node _T_320 = or(_T_319, _T_315) @[Mux.scala 27:72] + wire mtval_ns : UInt<32> @[Mux.scala 27:72] + mtval_ns <= _T_320 @[Mux.scala 27:72] + reg _T_321 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1778:47] + _T_321 <= mtval_ns @[el2_dec_tlu_ctl.scala 1778:47] + mtval <= _T_321 @[el2_dec_tlu_ctl.scala 1778:9] + node _T_322 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1793:62] + node _T_323 = eq(_T_322, UInt<12>("h07f8")) @[el2_dec_tlu_ctl.scala 1793:69] + node wr_mcgc_r = and(io.dec_csr_wen_r_mod, _T_323) @[el2_dec_tlu_ctl.scala 1793:40] + node _T_324 = bits(io.dec_csr_wrdata_r, 8, 0) @[el2_dec_tlu_ctl.scala 1795:40] + node _T_325 = bits(wr_mcgc_r, 0, 0) @[el2_dec_tlu_ctl.scala 1795:56] + inst rvclkhdr_8 of rvclkhdr_16 @[el2_lib.scala 508:23] + rvclkhdr_8.clock <= clock + rvclkhdr_8.reset <= reset + rvclkhdr_8.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_8.io.en <= _T_325 @[el2_lib.scala 511:17] + rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg mcgc : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + mcgc <= _T_324 @[el2_lib.scala 514:16] + node _T_326 = bits(mcgc, 8, 8) @[el2_dec_tlu_ctl.scala 1797:39] + io.dec_tlu_misc_clk_override <= _T_326 @[el2_dec_tlu_ctl.scala 1797:32] + node _T_327 = bits(mcgc, 7, 7) @[el2_dec_tlu_ctl.scala 1798:39] + io.dec_tlu_dec_clk_override <= _T_327 @[el2_dec_tlu_ctl.scala 1798:32] + node _T_328 = bits(mcgc, 5, 5) @[el2_dec_tlu_ctl.scala 1799:39] + io.dec_tlu_ifu_clk_override <= _T_328 @[el2_dec_tlu_ctl.scala 1799:32] + node _T_329 = bits(mcgc, 4, 4) @[el2_dec_tlu_ctl.scala 1800:39] + io.dec_tlu_lsu_clk_override <= _T_329 @[el2_dec_tlu_ctl.scala 1800:32] + node _T_330 = bits(mcgc, 3, 3) @[el2_dec_tlu_ctl.scala 1801:39] + io.dec_tlu_bus_clk_override <= _T_330 @[el2_dec_tlu_ctl.scala 1801:32] + node _T_331 = bits(mcgc, 2, 2) @[el2_dec_tlu_ctl.scala 1802:39] + io.dec_tlu_pic_clk_override <= _T_331 @[el2_dec_tlu_ctl.scala 1802:32] + node _T_332 = bits(mcgc, 1, 1) @[el2_dec_tlu_ctl.scala 1803:39] + io.dec_tlu_dccm_clk_override <= _T_332 @[el2_dec_tlu_ctl.scala 1803:32] + node _T_333 = bits(mcgc, 0, 0) @[el2_dec_tlu_ctl.scala 1804:39] + io.dec_tlu_icm_clk_override <= _T_333 @[el2_dec_tlu_ctl.scala 1804:32] + node _T_334 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1823:62] + node _T_335 = eq(_T_334, UInt<12>("h07f9")) @[el2_dec_tlu_ctl.scala 1823:69] + node wr_mfdc_r = and(io.dec_csr_wen_r_mod, _T_335) @[el2_dec_tlu_ctl.scala 1823:40] + node _T_336 = bits(wr_mfdc_r, 0, 0) @[el2_dec_tlu_ctl.scala 1827:40] + inst rvclkhdr_9 of rvclkhdr_17 @[el2_lib.scala 508:23] + rvclkhdr_9.clock <= clock + rvclkhdr_9.reset <= reset + rvclkhdr_9.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_9.io.en <= _T_336 @[el2_lib.scala 511:17] + rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_337 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_337 <= mfdc_ns @[el2_lib.scala 514:16] + mfdc_int <= _T_337 @[el2_dec_tlu_ctl.scala 1827:12] + node _T_338 = bits(io.dec_csr_wrdata_r, 18, 16) @[el2_dec_tlu_ctl.scala 1832:40] + node _T_339 = not(_T_338) @[el2_dec_tlu_ctl.scala 1832:20] + node _T_340 = bits(io.dec_csr_wrdata_r, 11, 7) @[el2_dec_tlu_ctl.scala 1832:67] + node _T_341 = bits(io.dec_csr_wrdata_r, 6, 6) @[el2_dec_tlu_ctl.scala 1832:95] + node _T_342 = not(_T_341) @[el2_dec_tlu_ctl.scala 1832:75] + node _T_343 = bits(io.dec_csr_wrdata_r, 5, 0) @[el2_dec_tlu_ctl.scala 1832:119] + node _T_344 = cat(_T_342, _T_343) @[Cat.scala 29:58] + node _T_345 = cat(_T_339, _T_340) @[Cat.scala 29:58] + node _T_346 = cat(_T_345, _T_344) @[Cat.scala 29:58] + mfdc_ns <= _T_346 @[el2_dec_tlu_ctl.scala 1832:13] + node _T_347 = bits(mfdc_int, 14, 12) @[el2_dec_tlu_ctl.scala 1833:29] + node _T_348 = not(_T_347) @[el2_dec_tlu_ctl.scala 1833:20] + node _T_349 = bits(mfdc_int, 11, 7) @[el2_dec_tlu_ctl.scala 1833:55] + node _T_350 = bits(mfdc_int, 6, 6) @[el2_dec_tlu_ctl.scala 1833:72] + node _T_351 = not(_T_350) @[el2_dec_tlu_ctl.scala 1833:63] + node _T_352 = bits(mfdc_int, 5, 0) @[el2_dec_tlu_ctl.scala 1833:85] + node _T_353 = cat(_T_351, _T_352) @[Cat.scala 29:58] + node _T_354 = cat(_T_348, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_355 = cat(_T_354, _T_349) @[Cat.scala 29:58] + node _T_356 = cat(_T_355, _T_353) @[Cat.scala 29:58] + mfdc <= _T_356 @[el2_dec_tlu_ctl.scala 1833:13] + node _T_357 = bits(mfdc, 18, 16) @[el2_dec_tlu_ctl.scala 1841:47] + io.dec_tlu_dma_qos_prty <= _T_357 @[el2_dec_tlu_ctl.scala 1841:40] + node _T_358 = bits(mfdc, 11, 11) @[el2_dec_tlu_ctl.scala 1842:47] + io.dec_tlu_external_ldfwd_disable <= _T_358 @[el2_dec_tlu_ctl.scala 1842:40] + node _T_359 = bits(mfdc, 8, 8) @[el2_dec_tlu_ctl.scala 1843:47] + io.dec_tlu_core_ecc_disable <= _T_359 @[el2_dec_tlu_ctl.scala 1843:40] + node _T_360 = bits(mfdc, 6, 6) @[el2_dec_tlu_ctl.scala 1844:47] + io.dec_tlu_sideeffect_posted_disable <= _T_360 @[el2_dec_tlu_ctl.scala 1844:40] + node _T_361 = bits(mfdc, 3, 3) @[el2_dec_tlu_ctl.scala 1845:47] + io.dec_tlu_bpred_disable <= _T_361 @[el2_dec_tlu_ctl.scala 1845:40] + node _T_362 = bits(mfdc, 2, 2) @[el2_dec_tlu_ctl.scala 1846:47] + io.dec_tlu_wb_coalescing_disable <= _T_362 @[el2_dec_tlu_ctl.scala 1846:40] + node _T_363 = bits(mfdc, 0, 0) @[el2_dec_tlu_ctl.scala 1847:47] + io.dec_tlu_pipelining_disable <= _T_363 @[el2_dec_tlu_ctl.scala 1847:40] + node _T_364 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1856:71] + node _T_365 = eq(_T_364, UInt<12>("h07c2")) @[el2_dec_tlu_ctl.scala 1856:78] + node _T_366 = and(io.dec_csr_wen_r_mod, _T_365) @[el2_dec_tlu_ctl.scala 1856:49] + node _T_367 = not(io.interrupt_valid_r) @[el2_dec_tlu_ctl.scala 1856:90] + node _T_368 = and(_T_366, _T_367) @[el2_dec_tlu_ctl.scala 1856:88] + node _T_369 = not(io.take_ext_int_start) @[el2_dec_tlu_ctl.scala 1856:114] + node _T_370 = and(_T_368, _T_369) @[el2_dec_tlu_ctl.scala 1856:112] + io.dec_tlu_wr_pause_r <= _T_370 @[el2_dec_tlu_ctl.scala 1856:25] + node _T_371 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1863:62] + node _T_372 = eq(_T_371, UInt<12>("h07c0")) @[el2_dec_tlu_ctl.scala 1863:69] + node wr_mrac_r = and(io.dec_csr_wen_r_mod, _T_372) @[el2_dec_tlu_ctl.scala 1863:40] + node _T_373 = bits(io.dec_csr_wrdata_r, 31, 31) @[el2_dec_tlu_ctl.scala 1866:40] + node _T_374 = bits(io.dec_csr_wrdata_r, 30, 30) @[el2_dec_tlu_ctl.scala 1866:65] + node _T_375 = bits(io.dec_csr_wrdata_r, 31, 31) @[el2_dec_tlu_ctl.scala 1866:92] + node _T_376 = not(_T_375) @[el2_dec_tlu_ctl.scala 1866:72] + node _T_377 = and(_T_374, _T_376) @[el2_dec_tlu_ctl.scala 1866:70] + node _T_378 = bits(io.dec_csr_wrdata_r, 29, 29) @[el2_dec_tlu_ctl.scala 1867:24] + node _T_379 = bits(io.dec_csr_wrdata_r, 28, 28) @[el2_dec_tlu_ctl.scala 1867:49] + node _T_380 = bits(io.dec_csr_wrdata_r, 29, 29) @[el2_dec_tlu_ctl.scala 1867:76] + node _T_381 = not(_T_380) @[el2_dec_tlu_ctl.scala 1867:56] + node _T_382 = and(_T_379, _T_381) @[el2_dec_tlu_ctl.scala 1867:54] + node _T_383 = bits(io.dec_csr_wrdata_r, 27, 27) @[el2_dec_tlu_ctl.scala 1868:24] + node _T_384 = bits(io.dec_csr_wrdata_r, 26, 26) @[el2_dec_tlu_ctl.scala 1868:49] + node _T_385 = bits(io.dec_csr_wrdata_r, 27, 27) @[el2_dec_tlu_ctl.scala 1868:76] + node _T_386 = not(_T_385) @[el2_dec_tlu_ctl.scala 1868:56] + node _T_387 = and(_T_384, _T_386) @[el2_dec_tlu_ctl.scala 1868:54] + node _T_388 = bits(io.dec_csr_wrdata_r, 25, 25) @[el2_dec_tlu_ctl.scala 1869:24] + node _T_389 = bits(io.dec_csr_wrdata_r, 24, 24) @[el2_dec_tlu_ctl.scala 1869:49] + node _T_390 = bits(io.dec_csr_wrdata_r, 25, 25) @[el2_dec_tlu_ctl.scala 1869:76] + node _T_391 = not(_T_390) @[el2_dec_tlu_ctl.scala 1869:56] + node _T_392 = and(_T_389, _T_391) @[el2_dec_tlu_ctl.scala 1869:54] + node _T_393 = bits(io.dec_csr_wrdata_r, 23, 23) @[el2_dec_tlu_ctl.scala 1870:24] + node _T_394 = bits(io.dec_csr_wrdata_r, 22, 22) @[el2_dec_tlu_ctl.scala 1870:49] + node _T_395 = bits(io.dec_csr_wrdata_r, 23, 23) @[el2_dec_tlu_ctl.scala 1870:76] + node _T_396 = not(_T_395) @[el2_dec_tlu_ctl.scala 1870:56] + node _T_397 = and(_T_394, _T_396) @[el2_dec_tlu_ctl.scala 1870:54] + node _T_398 = bits(io.dec_csr_wrdata_r, 21, 21) @[el2_dec_tlu_ctl.scala 1871:24] + node _T_399 = bits(io.dec_csr_wrdata_r, 20, 20) @[el2_dec_tlu_ctl.scala 1871:49] + node _T_400 = bits(io.dec_csr_wrdata_r, 21, 21) @[el2_dec_tlu_ctl.scala 1871:76] + node _T_401 = not(_T_400) @[el2_dec_tlu_ctl.scala 1871:56] + node _T_402 = and(_T_399, _T_401) @[el2_dec_tlu_ctl.scala 1871:54] + node _T_403 = bits(io.dec_csr_wrdata_r, 19, 19) @[el2_dec_tlu_ctl.scala 1872:24] + node _T_404 = bits(io.dec_csr_wrdata_r, 18, 18) @[el2_dec_tlu_ctl.scala 1872:49] + node _T_405 = bits(io.dec_csr_wrdata_r, 19, 19) @[el2_dec_tlu_ctl.scala 1872:76] + node _T_406 = not(_T_405) @[el2_dec_tlu_ctl.scala 1872:56] + node _T_407 = and(_T_404, _T_406) @[el2_dec_tlu_ctl.scala 1872:54] + node _T_408 = bits(io.dec_csr_wrdata_r, 17, 17) @[el2_dec_tlu_ctl.scala 1873:24] + node _T_409 = bits(io.dec_csr_wrdata_r, 16, 16) @[el2_dec_tlu_ctl.scala 1873:49] + node _T_410 = bits(io.dec_csr_wrdata_r, 17, 17) @[el2_dec_tlu_ctl.scala 1873:76] + node _T_411 = not(_T_410) @[el2_dec_tlu_ctl.scala 1873:56] + node _T_412 = and(_T_409, _T_411) @[el2_dec_tlu_ctl.scala 1873:54] + node _T_413 = bits(io.dec_csr_wrdata_r, 15, 15) @[el2_dec_tlu_ctl.scala 1874:24] + node _T_414 = bits(io.dec_csr_wrdata_r, 14, 14) @[el2_dec_tlu_ctl.scala 1874:49] + node _T_415 = bits(io.dec_csr_wrdata_r, 15, 15) @[el2_dec_tlu_ctl.scala 1874:76] + node _T_416 = not(_T_415) @[el2_dec_tlu_ctl.scala 1874:56] + node _T_417 = and(_T_414, _T_416) @[el2_dec_tlu_ctl.scala 1874:54] + node _T_418 = bits(io.dec_csr_wrdata_r, 13, 13) @[el2_dec_tlu_ctl.scala 1875:24] + node _T_419 = bits(io.dec_csr_wrdata_r, 12, 12) @[el2_dec_tlu_ctl.scala 1875:49] + node _T_420 = bits(io.dec_csr_wrdata_r, 13, 13) @[el2_dec_tlu_ctl.scala 1875:76] + node _T_421 = not(_T_420) @[el2_dec_tlu_ctl.scala 1875:56] + node _T_422 = and(_T_419, _T_421) @[el2_dec_tlu_ctl.scala 1875:54] + node _T_423 = bits(io.dec_csr_wrdata_r, 11, 11) @[el2_dec_tlu_ctl.scala 1876:24] + node _T_424 = bits(io.dec_csr_wrdata_r, 10, 10) @[el2_dec_tlu_ctl.scala 1876:49] + node _T_425 = bits(io.dec_csr_wrdata_r, 11, 11) @[el2_dec_tlu_ctl.scala 1876:76] + node _T_426 = not(_T_425) @[el2_dec_tlu_ctl.scala 1876:56] + node _T_427 = and(_T_424, _T_426) @[el2_dec_tlu_ctl.scala 1876:54] + node _T_428 = bits(io.dec_csr_wrdata_r, 9, 9) @[el2_dec_tlu_ctl.scala 1877:24] + node _T_429 = bits(io.dec_csr_wrdata_r, 8, 8) @[el2_dec_tlu_ctl.scala 1877:49] + node _T_430 = bits(io.dec_csr_wrdata_r, 9, 9) @[el2_dec_tlu_ctl.scala 1877:76] + node _T_431 = not(_T_430) @[el2_dec_tlu_ctl.scala 1877:56] + node _T_432 = and(_T_429, _T_431) @[el2_dec_tlu_ctl.scala 1877:53] + node _T_433 = bits(io.dec_csr_wrdata_r, 7, 7) @[el2_dec_tlu_ctl.scala 1878:24] + node _T_434 = bits(io.dec_csr_wrdata_r, 6, 6) @[el2_dec_tlu_ctl.scala 1878:49] + node _T_435 = bits(io.dec_csr_wrdata_r, 7, 7) @[el2_dec_tlu_ctl.scala 1878:76] + node _T_436 = not(_T_435) @[el2_dec_tlu_ctl.scala 1878:56] + node _T_437 = and(_T_434, _T_436) @[el2_dec_tlu_ctl.scala 1878:53] + node _T_438 = bits(io.dec_csr_wrdata_r, 5, 5) @[el2_dec_tlu_ctl.scala 1879:24] + node _T_439 = bits(io.dec_csr_wrdata_r, 4, 4) @[el2_dec_tlu_ctl.scala 1879:49] + node _T_440 = bits(io.dec_csr_wrdata_r, 5, 5) @[el2_dec_tlu_ctl.scala 1879:76] + node _T_441 = not(_T_440) @[el2_dec_tlu_ctl.scala 1879:56] + node _T_442 = and(_T_439, _T_441) @[el2_dec_tlu_ctl.scala 1879:53] + node _T_443 = bits(io.dec_csr_wrdata_r, 3, 3) @[el2_dec_tlu_ctl.scala 1880:24] + node _T_444 = bits(io.dec_csr_wrdata_r, 2, 2) @[el2_dec_tlu_ctl.scala 1880:49] + node _T_445 = bits(io.dec_csr_wrdata_r, 3, 3) @[el2_dec_tlu_ctl.scala 1880:76] + node _T_446 = not(_T_445) @[el2_dec_tlu_ctl.scala 1880:56] + node _T_447 = and(_T_444, _T_446) @[el2_dec_tlu_ctl.scala 1880:53] + node _T_448 = bits(io.dec_csr_wrdata_r, 1, 1) @[el2_dec_tlu_ctl.scala 1881:24] + node _T_449 = bits(io.dec_csr_wrdata_r, 0, 0) @[el2_dec_tlu_ctl.scala 1881:49] + node _T_450 = bits(io.dec_csr_wrdata_r, 1, 1) @[el2_dec_tlu_ctl.scala 1881:76] + node _T_451 = not(_T_450) @[el2_dec_tlu_ctl.scala 1881:56] + node _T_452 = and(_T_449, _T_451) @[el2_dec_tlu_ctl.scala 1881:53] + node _T_453 = cat(_T_448, _T_452) @[Cat.scala 29:58] + node _T_454 = cat(_T_443, _T_447) @[Cat.scala 29:58] + node _T_455 = cat(_T_454, _T_453) @[Cat.scala 29:58] + node _T_456 = cat(_T_438, _T_442) @[Cat.scala 29:58] + node _T_457 = cat(_T_433, _T_437) @[Cat.scala 29:58] + node _T_458 = cat(_T_457, _T_456) @[Cat.scala 29:58] + node _T_459 = cat(_T_458, _T_455) @[Cat.scala 29:58] + node _T_460 = cat(_T_428, _T_432) @[Cat.scala 29:58] + node _T_461 = cat(_T_423, _T_427) @[Cat.scala 29:58] + node _T_462 = cat(_T_461, _T_460) @[Cat.scala 29:58] + node _T_463 = cat(_T_418, _T_422) @[Cat.scala 29:58] + node _T_464 = cat(_T_413, _T_417) @[Cat.scala 29:58] + node _T_465 = cat(_T_464, _T_463) @[Cat.scala 29:58] + node _T_466 = cat(_T_465, _T_462) @[Cat.scala 29:58] + node _T_467 = cat(_T_466, _T_459) @[Cat.scala 29:58] + node _T_468 = cat(_T_408, _T_412) @[Cat.scala 29:58] + node _T_469 = cat(_T_403, _T_407) @[Cat.scala 29:58] + node _T_470 = cat(_T_469, _T_468) @[Cat.scala 29:58] + node _T_471 = cat(_T_398, _T_402) @[Cat.scala 29:58] + node _T_472 = cat(_T_393, _T_397) @[Cat.scala 29:58] + node _T_473 = cat(_T_472, _T_471) @[Cat.scala 29:58] + node _T_474 = cat(_T_473, _T_470) @[Cat.scala 29:58] + node _T_475 = cat(_T_388, _T_392) @[Cat.scala 29:58] + node _T_476 = cat(_T_383, _T_387) @[Cat.scala 29:58] + node _T_477 = cat(_T_476, _T_475) @[Cat.scala 29:58] + node _T_478 = cat(_T_378, _T_382) @[Cat.scala 29:58] + node _T_479 = cat(_T_373, _T_377) @[Cat.scala 29:58] + node _T_480 = cat(_T_479, _T_478) @[Cat.scala 29:58] + node _T_481 = cat(_T_480, _T_477) @[Cat.scala 29:58] + node _T_482 = cat(_T_481, _T_474) @[Cat.scala 29:58] + node mrac_in = cat(_T_482, _T_467) @[Cat.scala 29:58] + node _T_483 = bits(wr_mrac_r, 0, 0) @[el2_dec_tlu_ctl.scala 1884:39] + inst rvclkhdr_10 of rvclkhdr_18 @[el2_lib.scala 508:23] + rvclkhdr_10.clock <= clock + rvclkhdr_10.reset <= reset + rvclkhdr_10.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_10.io.en <= _T_483 @[el2_lib.scala 511:17] + rvclkhdr_10.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg mrac : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + mrac <= mrac_in @[el2_lib.scala 514:16] + io.dec_tlu_mrac_ff <= mrac @[el2_dec_tlu_ctl.scala 1886:22] + node _T_484 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1894:63] + node _T_485 = eq(_T_484, UInt<12>("h0bc0")) @[el2_dec_tlu_ctl.scala 1894:70] + node wr_mdeau_r = and(io.dec_csr_wen_r_mod, _T_485) @[el2_dec_tlu_ctl.scala 1894:41] + node _T_486 = not(wr_mdeau_r) @[el2_dec_tlu_ctl.scala 1904:60] + node _T_487 = and(io.mdseac_locked_f, _T_486) @[el2_dec_tlu_ctl.scala 1904:58] + node _T_488 = or(mdseac_en, _T_487) @[el2_dec_tlu_ctl.scala 1904:36] + io.mdseac_locked_ns <= _T_488 @[el2_dec_tlu_ctl.scala 1904:23] + node _T_489 = or(io.lsu_imprecise_error_store_any, io.lsu_imprecise_error_load_any) @[el2_dec_tlu_ctl.scala 1906:50] + node _T_490 = not(io.nmi_int_detected_f) @[el2_dec_tlu_ctl.scala 1906:87] + node _T_491 = and(_T_489, _T_490) @[el2_dec_tlu_ctl.scala 1906:85] + node _T_492 = not(io.mdseac_locked_f) @[el2_dec_tlu_ctl.scala 1906:112] + node _T_493 = and(_T_491, _T_492) @[el2_dec_tlu_ctl.scala 1906:110] + mdseac_en <= _T_493 @[el2_dec_tlu_ctl.scala 1906:13] + node _T_494 = bits(mdseac_en, 0, 0) @[el2_dec_tlu_ctl.scala 1908:65] + inst rvclkhdr_11 of rvclkhdr_19 @[el2_lib.scala 508:23] + rvclkhdr_11.clock <= clock + rvclkhdr_11.reset <= reset + rvclkhdr_11.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_11.io.en <= _T_494 @[el2_lib.scala 511:17] + rvclkhdr_11.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg mdseac : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + mdseac <= io.lsu_imprecise_error_addr_any @[el2_lib.scala 514:16] + node _T_495 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1917:62] + node _T_496 = eq(_T_495, UInt<12>("h07c6")) @[el2_dec_tlu_ctl.scala 1917:69] + node wr_mpmc_r = and(io.dec_csr_wen_r_mod, _T_496) @[el2_dec_tlu_ctl.scala 1917:40] + node _T_497 = bits(io.dec_csr_wrdata_r, 0, 0) @[el2_dec_tlu_ctl.scala 1921:52] + node _T_498 = and(wr_mpmc_r, _T_497) @[el2_dec_tlu_ctl.scala 1921:31] + node _T_499 = not(io.internal_dbg_halt_mode_f2) @[el2_dec_tlu_ctl.scala 1921:58] + node _T_500 = and(_T_498, _T_499) @[el2_dec_tlu_ctl.scala 1921:56] + node _T_501 = not(io.ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 1921:90] + node _T_502 = and(_T_500, _T_501) @[el2_dec_tlu_ctl.scala 1921:88] + io.fw_halt_req <= _T_502 @[el2_dec_tlu_ctl.scala 1921:18] + node _T_503 = or(io.fw_halt_req, fw_halted) @[el2_dec_tlu_ctl.scala 1923:38] + node _T_504 = not(set_mie_pmu_fw_halt) @[el2_dec_tlu_ctl.scala 1923:53] + node fw_halted_ns = and(_T_503, _T_504) @[el2_dec_tlu_ctl.scala 1923:51] + node _T_505 = bits(wr_mpmc_r, 0, 0) @[el2_dec_tlu_ctl.scala 1924:30] + node _T_506 = bits(io.dec_csr_wrdata_r, 1, 1) @[el2_dec_tlu_ctl.scala 1924:58] + node _T_507 = not(_T_506) @[el2_dec_tlu_ctl.scala 1924:38] + node _T_508 = not(mpmc) @[el2_dec_tlu_ctl.scala 1924:63] + node _T_509 = mux(_T_505, _T_507, _T_508) @[el2_dec_tlu_ctl.scala 1924:19] + mpmc_b_ns <= _T_509 @[el2_dec_tlu_ctl.scala 1924:13] + reg _T_510 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1926:45] + _T_510 <= mpmc_b_ns @[el2_dec_tlu_ctl.scala 1926:45] + mpmc_b <= _T_510 @[el2_dec_tlu_ctl.scala 1926:10] + reg _T_511 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1927:46] + _T_511 <= fw_halted_ns @[el2_dec_tlu_ctl.scala 1927:46] + fw_halted <= _T_511 @[el2_dec_tlu_ctl.scala 1927:13] + node _T_512 = not(mpmc_b) @[el2_dec_tlu_ctl.scala 1929:11] + mpmc <= _T_512 @[el2_dec_tlu_ctl.scala 1929:8] + node _T_513 = bits(io.dec_csr_wrdata_r, 31, 27) @[el2_dec_tlu_ctl.scala 1938:41] + node _T_514 = gt(_T_513, UInt<5>("h01a")) @[el2_dec_tlu_ctl.scala 1938:49] + node _T_515 = bits(io.dec_csr_wrdata_r, 31, 27) @[el2_dec_tlu_ctl.scala 1938:93] + node csr_sat = mux(_T_514, UInt<5>("h01a"), _T_515) @[el2_dec_tlu_ctl.scala 1938:20] + node _T_516 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1940:64] + node _T_517 = eq(_T_516, UInt<12>("h07f0")) @[el2_dec_tlu_ctl.scala 1940:71] + node wr_micect_r = and(io.dec_csr_wen_r_mod, _T_517) @[el2_dec_tlu_ctl.scala 1940:42] + node _T_518 = cat(UInt<26>("h00"), io.ic_perr_r_d1) @[Cat.scala 29:58] + node _T_519 = add(micect, _T_518) @[el2_dec_tlu_ctl.scala 1941:24] + node _T_520 = tail(_T_519, 1) @[el2_dec_tlu_ctl.scala 1941:24] + micect_inc <= _T_520 @[el2_dec_tlu_ctl.scala 1941:14] + node _T_521 = bits(wr_micect_r, 0, 0) @[el2_dec_tlu_ctl.scala 1942:36] + node _T_522 = bits(io.dec_csr_wrdata_r, 26, 0) @[el2_dec_tlu_ctl.scala 1942:76] + node _T_523 = cat(csr_sat, _T_522) @[Cat.scala 29:58] + node _T_524 = bits(micect, 31, 27) @[el2_dec_tlu_ctl.scala 1942:96] + node _T_525 = cat(_T_524, micect_inc) @[Cat.scala 29:58] + node micect_ns = mux(_T_521, _T_523, _T_525) @[el2_dec_tlu_ctl.scala 1942:23] + node _T_526 = or(wr_micect_r, io.ic_perr_r_d1) @[el2_dec_tlu_ctl.scala 1944:43] + node _T_527 = bits(_T_526, 0, 0) @[el2_dec_tlu_ctl.scala 1944:62] + inst rvclkhdr_12 of rvclkhdr_20 @[el2_lib.scala 508:23] + rvclkhdr_12.clock <= clock + rvclkhdr_12.reset <= reset + rvclkhdr_12.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_12.io.en <= _T_527 @[el2_lib.scala 511:17] + rvclkhdr_12.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_528 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_528 <= micect_ns @[el2_lib.scala 514:16] + micect <= _T_528 @[el2_dec_tlu_ctl.scala 1944:10] + node _T_529 = bits(micect, 31, 27) @[el2_dec_tlu_ctl.scala 1946:48] + node _T_530 = dshl(UInt<32>("h0ffffffff"), _T_529) @[el2_dec_tlu_ctl.scala 1946:39] + node _T_531 = orr(_T_530) @[el2_dec_tlu_ctl.scala 1946:57] + node _T_532 = bits(micect, 26, 0) @[el2_dec_tlu_ctl.scala 1946:83] + node _T_533 = cat(UInt<5>("h00"), _T_532) @[Cat.scala 29:58] + node _T_534 = and(_T_531, _T_533) @[el2_dec_tlu_ctl.scala 1946:61] + mice_ce_req <= _T_534 @[el2_dec_tlu_ctl.scala 1946:15] + node _T_535 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1955:70] + node _T_536 = eq(_T_535, UInt<12>("h07f1")) @[el2_dec_tlu_ctl.scala 1955:77] + node wr_miccmect_r = and(io.dec_csr_wen_r_mod, _T_536) @[el2_dec_tlu_ctl.scala 1955:48] + node _T_537 = bits(miccmect, 26, 0) @[el2_dec_tlu_ctl.scala 1956:27] + node _T_538 = or(io.iccm_sbecc_r_d1, io.iccm_dma_sb_error) @[el2_dec_tlu_ctl.scala 1956:71] + node _T_539 = cat(UInt<26>("h00"), _T_538) @[Cat.scala 29:58] + node _T_540 = add(_T_537, _T_539) @[el2_dec_tlu_ctl.scala 1956:34] + node _T_541 = tail(_T_540, 1) @[el2_dec_tlu_ctl.scala 1956:34] + miccmect_inc <= _T_541 @[el2_dec_tlu_ctl.scala 1956:16] + node _T_542 = bits(wr_miccmect_r, 0, 0) @[el2_dec_tlu_ctl.scala 1957:46] + node _T_543 = bits(io.dec_csr_wrdata_r, 26, 0) @[el2_dec_tlu_ctl.scala 1957:86] + node _T_544 = cat(csr_sat, _T_543) @[Cat.scala 29:58] + node _T_545 = bits(miccmect, 31, 27) @[el2_dec_tlu_ctl.scala 1957:108] + node _T_546 = cat(_T_545, miccmect_inc) @[Cat.scala 29:58] + node miccmect_ns = mux(_T_542, _T_544, _T_546) @[el2_dec_tlu_ctl.scala 1957:31] + node _T_547 = or(wr_miccmect_r, io.iccm_sbecc_r_d1) @[el2_dec_tlu_ctl.scala 1959:49] + node _T_548 = or(_T_547, io.iccm_dma_sb_error) @[el2_dec_tlu_ctl.scala 1959:70] + node _T_549 = bits(_T_548, 0, 0) @[el2_dec_tlu_ctl.scala 1959:94] + inst rvclkhdr_13 of rvclkhdr_21 @[el2_lib.scala 508:23] + rvclkhdr_13.clock <= clock + rvclkhdr_13.reset <= reset + rvclkhdr_13.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_13.io.en <= _T_549 @[el2_lib.scala 511:17] + rvclkhdr_13.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_550 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_550 <= miccmect_ns @[el2_lib.scala 514:16] + miccmect <= _T_550 @[el2_dec_tlu_ctl.scala 1959:12] + node _T_551 = bits(miccmect, 31, 27) @[el2_dec_tlu_ctl.scala 1960:53] + node _T_552 = dshl(UInt<32>("h0ffffffff"), _T_551) @[el2_dec_tlu_ctl.scala 1960:42] + node _T_553 = bits(miccmect, 26, 0) @[el2_dec_tlu_ctl.scala 1960:86] + node _T_554 = cat(UInt<5>("h00"), _T_553) @[Cat.scala 29:58] + node _T_555 = and(_T_552, _T_554) @[el2_dec_tlu_ctl.scala 1960:62] + node _T_556 = orr(_T_555) @[el2_dec_tlu_ctl.scala 1960:95] + miccme_ce_req <= _T_556 @[el2_dec_tlu_ctl.scala 1960:17] + node _T_557 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1969:70] + node _T_558 = eq(_T_557, UInt<12>("h07f2")) @[el2_dec_tlu_ctl.scala 1969:77] + node wr_mdccmect_r = and(io.dec_csr_wen_r_mod, _T_558) @[el2_dec_tlu_ctl.scala 1969:48] + node _T_559 = bits(mdccmect, 26, 0) @[el2_dec_tlu_ctl.scala 1970:27] + node _T_560 = cat(UInt<26>("h00"), io.lsu_single_ecc_error_r_d1) @[Cat.scala 29:58] + node _T_561 = add(_T_559, _T_560) @[el2_dec_tlu_ctl.scala 1970:34] + node _T_562 = tail(_T_561, 1) @[el2_dec_tlu_ctl.scala 1970:34] + mdccmect_inc <= _T_562 @[el2_dec_tlu_ctl.scala 1970:16] + node _T_563 = bits(wr_mdccmect_r, 0, 0) @[el2_dec_tlu_ctl.scala 1971:46] + node _T_564 = bits(io.dec_csr_wrdata_r, 26, 0) @[el2_dec_tlu_ctl.scala 1971:86] + node _T_565 = cat(csr_sat, _T_564) @[Cat.scala 29:58] + node _T_566 = bits(mdccmect, 31, 27) @[el2_dec_tlu_ctl.scala 1971:108] + node _T_567 = cat(_T_566, mdccmect_inc) @[Cat.scala 29:58] + node mdccmect_ns = mux(_T_563, _T_565, _T_567) @[el2_dec_tlu_ctl.scala 1971:31] + node _T_568 = or(wr_mdccmect_r, io.lsu_single_ecc_error_r_d1) @[el2_dec_tlu_ctl.scala 1973:50] + node _T_569 = bits(_T_568, 0, 0) @[el2_dec_tlu_ctl.scala 1973:82] + inst rvclkhdr_14 of rvclkhdr_22 @[el2_lib.scala 508:23] + rvclkhdr_14.clock <= clock + rvclkhdr_14.reset <= reset + rvclkhdr_14.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_14.io.en <= _T_569 @[el2_lib.scala 511:17] + rvclkhdr_14.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_570 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_570 <= mdccmect_ns @[el2_lib.scala 514:16] + mdccmect <= _T_570 @[el2_dec_tlu_ctl.scala 1973:12] + node _T_571 = bits(mdccmect, 31, 27) @[el2_dec_tlu_ctl.scala 1975:53] + node _T_572 = dshl(UInt<32>("h0ffffffff"), _T_571) @[el2_dec_tlu_ctl.scala 1975:42] + node _T_573 = bits(mdccmect, 26, 0) @[el2_dec_tlu_ctl.scala 1975:86] + node _T_574 = cat(UInt<5>("h00"), _T_573) @[Cat.scala 29:58] + node _T_575 = and(_T_572, _T_574) @[el2_dec_tlu_ctl.scala 1975:62] + node _T_576 = orr(_T_575) @[el2_dec_tlu_ctl.scala 1975:95] + mdccme_ce_req <= _T_576 @[el2_dec_tlu_ctl.scala 1975:17] + node _T_577 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1985:63] + node _T_578 = eq(_T_577, UInt<12>("h07ce")) @[el2_dec_tlu_ctl.scala 1985:70] + node wr_mfdht_r = and(io.dec_csr_wen_r_mod, _T_578) @[el2_dec_tlu_ctl.scala 1985:41] + node _T_579 = bits(wr_mfdht_r, 0, 0) @[el2_dec_tlu_ctl.scala 1987:33] + node _T_580 = bits(io.dec_csr_wrdata_r, 5, 0) @[el2_dec_tlu_ctl.scala 1987:60] + node mfdht_ns = mux(_T_579, _T_580, mfdht) @[el2_dec_tlu_ctl.scala 1987:21] + reg _T_581 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1989:44] + _T_581 <= mfdht_ns @[el2_dec_tlu_ctl.scala 1989:44] + mfdht <= _T_581 @[el2_dec_tlu_ctl.scala 1989:9] + node _T_582 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1998:63] + node _T_583 = eq(_T_582, UInt<12>("h07cf")) @[el2_dec_tlu_ctl.scala 1998:70] + node wr_mfdhs_r = and(io.dec_csr_wen_r_mod, _T_583) @[el2_dec_tlu_ctl.scala 1998:41] + node _T_584 = bits(wr_mfdhs_r, 0, 0) @[el2_dec_tlu_ctl.scala 2000:33] + node _T_585 = bits(io.dec_csr_wrdata_r, 1, 0) @[el2_dec_tlu_ctl.scala 2000:61] + node _T_586 = not(io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2001:30] + node _T_587 = and(io.dbg_tlu_halted, _T_586) @[el2_dec_tlu_ctl.scala 2001:28] + node _T_588 = bits(_T_587, 0, 0) @[el2_dec_tlu_ctl.scala 2001:52] + node _T_589 = not(io.lsu_idle_any_f) @[el2_dec_tlu_ctl.scala 2001:65] + node _T_590 = not(io.ifu_miss_state_idle_f) @[el2_dec_tlu_ctl.scala 2001:85] + node _T_591 = cat(_T_589, _T_590) @[Cat.scala 29:58] + node _T_592 = mux(_T_588, _T_591, mfdhs) @[el2_dec_tlu_ctl.scala 2001:8] + node mfdhs_ns = mux(_T_584, _T_585, _T_592) @[el2_dec_tlu_ctl.scala 2000:21] + node _T_593 = or(wr_mfdhs_r, io.dbg_tlu_halted) @[el2_dec_tlu_ctl.scala 2003:72] + node _T_594 = bits(_T_593, 0, 0) @[el2_dec_tlu_ctl.scala 2003:93] + reg _T_595 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_594 : @[Reg.scala 28:19] + _T_595 <= mfdhs_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + mfdhs <= _T_595 @[el2_dec_tlu_ctl.scala 2003:9] + node _T_596 = bits(io.debug_halt_req_f, 0, 0) @[el2_dec_tlu_ctl.scala 2005:48] + node _T_597 = add(force_halt_ctr_f, UInt<32>("h01")) @[el2_dec_tlu_ctl.scala 2005:75] + node _T_598 = tail(_T_597, 1) @[el2_dec_tlu_ctl.scala 2005:75] + node _T_599 = bits(io.dbg_tlu_halted_f, 0, 0) @[el2_dec_tlu_ctl.scala 2006:29] + node _T_600 = mux(_T_599, UInt<32>("h00"), force_halt_ctr_f) @[el2_dec_tlu_ctl.scala 2006:8] + node force_halt_ctr = mux(_T_596, _T_598, _T_600) @[el2_dec_tlu_ctl.scala 2005:27] + node _T_601 = bits(mfdht, 0, 0) @[el2_dec_tlu_ctl.scala 2008:82] + reg _T_602 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_601 : @[Reg.scala 28:19] + _T_602 <= force_halt_ctr @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + force_halt_ctr_f <= _T_602 @[el2_dec_tlu_ctl.scala 2008:20] + node _T_603 = bits(mfdht, 0, 0) @[el2_dec_tlu_ctl.scala 2010:25] + node _T_604 = bits(mfdht, 5, 1) @[el2_dec_tlu_ctl.scala 2010:80] + node _T_605 = dshl(UInt<32>("h0ffffffff"), _T_604) @[el2_dec_tlu_ctl.scala 2010:72] + node _T_606 = and(force_halt_ctr_f, _T_605) @[el2_dec_tlu_ctl.scala 2010:49] + node _T_607 = orr(_T_606) @[el2_dec_tlu_ctl.scala 2010:88] + node _T_608 = and(_T_603, _T_607) @[el2_dec_tlu_ctl.scala 2010:29] + io.force_halt <= _T_608 @[el2_dec_tlu_ctl.scala 2010:17] + node _T_609 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2018:63] + node _T_610 = eq(_T_609, UInt<12>("h0bc8")) @[el2_dec_tlu_ctl.scala 2018:70] + node wr_meivt_r = and(io.dec_csr_wen_r_mod, _T_610) @[el2_dec_tlu_ctl.scala 2018:41] + node _T_611 = bits(io.dec_csr_wrdata_r, 31, 10) @[el2_dec_tlu_ctl.scala 2020:41] + node _T_612 = bits(wr_meivt_r, 0, 0) @[el2_dec_tlu_ctl.scala 2020:60] + inst rvclkhdr_15 of rvclkhdr_23 @[el2_lib.scala 508:23] + rvclkhdr_15.clock <= clock + rvclkhdr_15.reset <= reset + rvclkhdr_15.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_15.io.en <= _T_612 @[el2_lib.scala 511:17] + rvclkhdr_15.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg meivt : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + meivt <= _T_611 @[el2_lib.scala 514:16] + node _T_613 = bits(wr_meicpct_r, 0, 0) @[el2_dec_tlu_ctl.scala 2032:50] + inst rvclkhdr_16 of rvclkhdr_24 @[el2_lib.scala 508:23] + rvclkhdr_16.clock <= clock + rvclkhdr_16.reset <= reset + rvclkhdr_16.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_16.io.en <= _T_613 @[el2_lib.scala 511:17] + rvclkhdr_16.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg meihap : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + meihap <= io.pic_claimid @[el2_lib.scala 514:16] + node _T_614 = cat(meivt, meihap) @[Cat.scala 29:58] + node _T_615 = cat(_T_614, UInt<2>("h00")) @[Cat.scala 29:58] + io.dec_tlu_meihap <= _T_615 @[el2_dec_tlu_ctl.scala 2033:21] + node _T_616 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2042:66] + node _T_617 = eq(_T_616, UInt<12>("h0bcc")) @[el2_dec_tlu_ctl.scala 2042:73] + node wr_meicurpl_r = and(io.dec_csr_wen_r_mod, _T_617) @[el2_dec_tlu_ctl.scala 2042:44] + node _T_618 = bits(wr_meicurpl_r, 0, 0) @[el2_dec_tlu_ctl.scala 2043:39] + node _T_619 = bits(io.dec_csr_wrdata_r, 3, 0) @[el2_dec_tlu_ctl.scala 2043:66] + node meicurpl_ns = mux(_T_618, _T_619, meicurpl) @[el2_dec_tlu_ctl.scala 2043:24] + reg _T_620 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2045:47] + _T_620 <= meicurpl_ns @[el2_dec_tlu_ctl.scala 2045:47] + meicurpl <= _T_620 @[el2_dec_tlu_ctl.scala 2045:12] + io.dec_tlu_meicurpl <= meicurpl @[el2_dec_tlu_ctl.scala 2047:23] + node _T_621 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2057:67] + node _T_622 = eq(_T_621, UInt<12>("h0bcb")) @[el2_dec_tlu_ctl.scala 2057:74] + node _T_623 = and(io.dec_csr_wen_r_mod, _T_622) @[el2_dec_tlu_ctl.scala 2057:45] + node wr_meicidpl_r = or(_T_623, io.take_ext_int_start) @[el2_dec_tlu_ctl.scala 2057:89] + node _T_624 = bits(wr_meicpct_r, 0, 0) @[el2_dec_tlu_ctl.scala 2059:38] + node _T_625 = bits(wr_meicidpl_r, 0, 0) @[el2_dec_tlu_ctl.scala 2060:23] + node _T_626 = bits(io.dec_csr_wrdata_r, 3, 0) @[el2_dec_tlu_ctl.scala 2060:50] + node _T_627 = mux(_T_625, _T_626, meicidpl) @[el2_dec_tlu_ctl.scala 2060:8] + node meicidpl_ns = mux(_T_624, io.pic_pl, _T_627) @[el2_dec_tlu_ctl.scala 2059:24] + reg _T_628 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2062:45] + _T_628 <= meicidpl_ns @[el2_dec_tlu_ctl.scala 2062:45] + meicidpl <= _T_628 @[el2_dec_tlu_ctl.scala 2062:12] + node _T_629 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2069:63] + node _T_630 = eq(_T_629, UInt<12>("h0bca")) @[el2_dec_tlu_ctl.scala 2069:70] + node _T_631 = and(io.dec_csr_wen_r_mod, _T_630) @[el2_dec_tlu_ctl.scala 2069:41] + node _T_632 = or(_T_631, io.take_ext_int_start) @[el2_dec_tlu_ctl.scala 2069:84] + wr_meicpct_r <= _T_632 @[el2_dec_tlu_ctl.scala 2069:16] + node _T_633 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2078:63] + node _T_634 = eq(_T_633, UInt<12>("h0bc9")) @[el2_dec_tlu_ctl.scala 2078:70] + node wr_meipt_r = and(io.dec_csr_wen_r_mod, _T_634) @[el2_dec_tlu_ctl.scala 2078:41] + node _T_635 = bits(wr_meipt_r, 0, 0) @[el2_dec_tlu_ctl.scala 2079:33] + node _T_636 = bits(io.dec_csr_wrdata_r, 3, 0) @[el2_dec_tlu_ctl.scala 2079:60] + node meipt_ns = mux(_T_635, _T_636, meipt) @[el2_dec_tlu_ctl.scala 2079:21] + reg _T_637 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2081:44] + _T_637 <= meipt_ns @[el2_dec_tlu_ctl.scala 2081:44] + meipt <= _T_637 @[el2_dec_tlu_ctl.scala 2081:9] + io.dec_tlu_meipt <= meipt @[el2_dec_tlu_ctl.scala 2083:20] + node _T_638 = and(io.trigger_hit_r_d1, io.dcsr_single_step_done_f) @[el2_dec_tlu_ctl.scala 2109:90] + node trigger_hit_for_dscr_cause_r_d1 = or(io.trigger_hit_dmode_r_d1, _T_638) @[el2_dec_tlu_ctl.scala 2109:67] + node _T_639 = not(io.ebreak_to_debug_mode_r_d1) @[el2_dec_tlu_ctl.scala 2112:35] + node _T_640 = and(io.dcsr_single_step_done_f, _T_639) @[el2_dec_tlu_ctl.scala 2112:33] + node _T_641 = not(trigger_hit_for_dscr_cause_r_d1) @[el2_dec_tlu_ctl.scala 2112:67] + node _T_642 = and(_T_640, _T_641) @[el2_dec_tlu_ctl.scala 2112:65] + node _T_643 = not(io.debug_halt_req) @[el2_dec_tlu_ctl.scala 2112:102] + node _T_644 = and(_T_642, _T_643) @[el2_dec_tlu_ctl.scala 2112:100] + node _T_645 = bits(_T_644, 0, 0) @[el2_dec_tlu_ctl.scala 2112:122] + node _T_646 = not(io.ebreak_to_debug_mode_r_d1) @[el2_dec_tlu_ctl.scala 2113:26] + node _T_647 = and(io.debug_halt_req, _T_646) @[el2_dec_tlu_ctl.scala 2113:24] + node _T_648 = not(trigger_hit_for_dscr_cause_r_d1) @[el2_dec_tlu_ctl.scala 2113:58] + node _T_649 = and(_T_647, _T_648) @[el2_dec_tlu_ctl.scala 2113:56] + node _T_650 = bits(_T_649, 0, 0) @[el2_dec_tlu_ctl.scala 2113:92] + node _T_651 = not(trigger_hit_for_dscr_cause_r_d1) @[el2_dec_tlu_ctl.scala 2114:37] + node _T_652 = and(io.ebreak_to_debug_mode_r_d1, _T_651) @[el2_dec_tlu_ctl.scala 2114:35] + node _T_653 = bits(_T_652, 0, 0) @[el2_dec_tlu_ctl.scala 2114:71] + node _T_654 = bits(trigger_hit_for_dscr_cause_r_d1, 0, 0) @[el2_dec_tlu_ctl.scala 2115:39] + node _T_655 = mux(_T_645, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_656 = mux(_T_650, UInt<3>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_657 = mux(_T_653, UInt<3>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_658 = mux(_T_654, UInt<3>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_659 = or(_T_655, _T_656) @[Mux.scala 27:72] + node _T_660 = or(_T_659, _T_657) @[Mux.scala 27:72] + node _T_661 = or(_T_660, _T_658) @[Mux.scala 27:72] + wire dcsr_cause : UInt<3> @[Mux.scala 27:72] + dcsr_cause <= _T_661 @[Mux.scala 27:72] + node _T_662 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[el2_dec_tlu_ctl.scala 2117:47] + node _T_663 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2117:92] + node _T_664 = eq(_T_663, UInt<12>("h07b0")) @[el2_dec_tlu_ctl.scala 2117:99] + node wr_dcsr_r = and(_T_662, _T_664) @[el2_dec_tlu_ctl.scala 2117:70] + node _T_665 = bits(io.dcsr, 8, 6) @[el2_dec_tlu_ctl.scala 2123:70] + node _T_666 = eq(_T_665, UInt<3>("h03")) @[el2_dec_tlu_ctl.scala 2123:76] + node dcsr_cause_upgradeable = and(io.internal_dbg_halt_mode_f, _T_666) @[el2_dec_tlu_ctl.scala 2123:60] + node _T_667 = not(io.dbg_tlu_halted) @[el2_dec_tlu_ctl.scala 2124:60] + node _T_668 = or(_T_667, dcsr_cause_upgradeable) @[el2_dec_tlu_ctl.scala 2124:79] + node enter_debug_halt_req_le = and(io.enter_debug_halt_req, _T_668) @[el2_dec_tlu_ctl.scala 2124:57] + node nmi_in_debug_mode = and(io.nmi_int_detected_f, io.internal_dbg_halt_mode_f) @[el2_dec_tlu_ctl.scala 2126:49] + node _T_669 = bits(enter_debug_halt_req_le, 0, 0) @[el2_dec_tlu_ctl.scala 2127:45] + node _T_670 = bits(io.dcsr, 15, 9) @[el2_dec_tlu_ctl.scala 2127:65] + node _T_671 = bits(io.dcsr, 5, 2) @[el2_dec_tlu_ctl.scala 2127:92] + node _T_672 = cat(_T_671, UInt<2>("h03")) @[Cat.scala 29:58] + node _T_673 = cat(_T_670, dcsr_cause) @[Cat.scala 29:58] + node _T_674 = cat(_T_673, _T_672) @[Cat.scala 29:58] + node _T_675 = bits(wr_dcsr_r, 0, 0) @[el2_dec_tlu_ctl.scala 2128:19] + node _T_676 = bits(io.dec_csr_wrdata_r, 15, 15) @[el2_dec_tlu_ctl.scala 2128:50] + node _T_677 = bits(io.dec_csr_wrdata_r, 11, 10) @[el2_dec_tlu_ctl.scala 2128:85] + node _T_678 = bits(io.dcsr, 8, 6) @[el2_dec_tlu_ctl.scala 2128:111] + node _T_679 = bits(io.dcsr, 3, 3) @[el2_dec_tlu_ctl.scala 2128:155] + node _T_680 = or(nmi_in_debug_mode, _T_679) @[el2_dec_tlu_ctl.scala 2128:146] + node _T_681 = bits(io.dec_csr_wrdata_r, 2, 2) @[el2_dec_tlu_ctl.scala 2128:179] + node _T_682 = cat(_T_681, UInt<2>("h03")) @[Cat.scala 29:58] + node _T_683 = cat(UInt<2>("h00"), _T_680) @[Cat.scala 29:58] + node _T_684 = cat(_T_683, _T_682) @[Cat.scala 29:58] + node _T_685 = cat(UInt<1>("h00"), _T_678) @[Cat.scala 29:58] + node _T_686 = cat(_T_676, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_687 = cat(_T_686, _T_677) @[Cat.scala 29:58] + node _T_688 = cat(_T_687, _T_685) @[Cat.scala 29:58] + node _T_689 = cat(_T_688, _T_684) @[Cat.scala 29:58] + node _T_690 = bits(io.dcsr, 15, 4) @[el2_dec_tlu_ctl.scala 2128:212] + node _T_691 = bits(io.dcsr, 2, 2) @[el2_dec_tlu_ctl.scala 2128:246] + node _T_692 = cat(_T_691, UInt<2>("h03")) @[Cat.scala 29:58] + node _T_693 = cat(_T_690, nmi_in_debug_mode) @[Cat.scala 29:58] + node _T_694 = cat(_T_693, _T_692) @[Cat.scala 29:58] + node _T_695 = mux(_T_675, _T_689, _T_694) @[el2_dec_tlu_ctl.scala 2128:8] + node dcsr_ns = mux(_T_669, _T_674, _T_695) @[el2_dec_tlu_ctl.scala 2127:20] + node _T_696 = or(enter_debug_halt_req_le, wr_dcsr_r) @[el2_dec_tlu_ctl.scala 2130:55] + node _T_697 = or(_T_696, io.internal_dbg_halt_mode) @[el2_dec_tlu_ctl.scala 2130:67] + node _T_698 = or(_T_697, io.take_nmi) @[el2_dec_tlu_ctl.scala 2130:95] + node _T_699 = bits(_T_698, 0, 0) @[el2_dec_tlu_ctl.scala 2130:110] + inst rvclkhdr_17 of rvclkhdr_25 @[el2_lib.scala 508:23] + rvclkhdr_17.clock <= clock + rvclkhdr_17.reset <= reset + rvclkhdr_17.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_17.io.en <= _T_699 @[el2_lib.scala 511:17] + rvclkhdr_17.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_700 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_700 <= dcsr_ns @[el2_lib.scala 514:16] + io.dcsr <= _T_700 @[el2_dec_tlu_ctl.scala 2130:11] + node _T_701 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[el2_dec_tlu_ctl.scala 2138:46] + node _T_702 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2138:91] + node _T_703 = eq(_T_702, UInt<12>("h07b1")) @[el2_dec_tlu_ctl.scala 2138:98] + node wr_dpc_r = and(_T_701, _T_703) @[el2_dec_tlu_ctl.scala 2138:69] + node _T_704 = not(io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2139:45] + node _T_705 = and(io.dbg_tlu_halted, _T_704) @[el2_dec_tlu_ctl.scala 2139:43] + node _T_706 = not(io.request_debug_mode_done) @[el2_dec_tlu_ctl.scala 2139:68] + node dpc_capture_npc = and(_T_705, _T_706) @[el2_dec_tlu_ctl.scala 2139:66] + node _T_707 = not(io.request_debug_mode_r) @[el2_dec_tlu_ctl.scala 2143:6] + node _T_708 = not(dpc_capture_npc) @[el2_dec_tlu_ctl.scala 2143:24] + node _T_709 = and(_T_707, _T_708) @[el2_dec_tlu_ctl.scala 2143:22] + node _T_710 = and(_T_709, wr_dpc_r) @[el2_dec_tlu_ctl.scala 2143:41] + node _T_711 = bits(_T_710, 0, 0) @[el2_dec_tlu_ctl.scala 2143:53] + node _T_712 = bits(io.dec_csr_wrdata_r, 31, 1) @[el2_dec_tlu_ctl.scala 2143:82] + node _T_713 = bits(io.request_debug_mode_r, 0, 0) @[el2_dec_tlu_ctl.scala 2144:22] + node _T_714 = not(io.request_debug_mode_r) @[el2_dec_tlu_ctl.scala 2145:6] + node _T_715 = and(_T_714, dpc_capture_npc) @[el2_dec_tlu_ctl.scala 2145:22] + node _T_716 = bits(_T_715, 0, 0) @[el2_dec_tlu_ctl.scala 2145:41] + node _T_717 = mux(_T_711, _T_712, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_718 = mux(_T_713, pc_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_719 = mux(_T_716, io.npc_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_720 = or(_T_717, _T_718) @[Mux.scala 27:72] + node _T_721 = or(_T_720, _T_719) @[Mux.scala 27:72] + wire dpc_ns : UInt<31> @[Mux.scala 27:72] + dpc_ns <= _T_721 @[Mux.scala 27:72] + node _T_722 = or(wr_dpc_r, io.request_debug_mode_r) @[el2_dec_tlu_ctl.scala 2147:37] + node _T_723 = or(_T_722, dpc_capture_npc) @[el2_dec_tlu_ctl.scala 2147:54] + node _T_724 = bits(_T_723, 0, 0) @[el2_dec_tlu_ctl.scala 2147:73] + inst rvclkhdr_18 of rvclkhdr_26 @[el2_lib.scala 508:23] + rvclkhdr_18.clock <= clock + rvclkhdr_18.reset <= reset + rvclkhdr_18.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_18.io.en <= _T_724 @[el2_lib.scala 511:17] + rvclkhdr_18.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_725 : UInt, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_725 <= dpc_ns @[el2_lib.scala 514:16] + io.dpc <= _T_725 @[el2_dec_tlu_ctl.scala 2147:10] + node _T_726 = bits(io.dec_csr_wrdata_r, 24, 24) @[el2_dec_tlu_ctl.scala 2161:44] + node _T_727 = bits(io.dec_csr_wrdata_r, 21, 20) @[el2_dec_tlu_ctl.scala 2161:69] + node _T_728 = bits(io.dec_csr_wrdata_r, 16, 3) @[el2_dec_tlu_ctl.scala 2161:97] + node _T_729 = cat(_T_726, _T_727) @[Cat.scala 29:58] + node dicawics_ns = cat(_T_729, _T_728) @[Cat.scala 29:58] + node _T_730 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[el2_dec_tlu_ctl.scala 2162:51] + node _T_731 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2162:96] + node _T_732 = eq(_T_731, UInt<12>("h07c8")) @[el2_dec_tlu_ctl.scala 2162:103] + node wr_dicawics_r = and(_T_730, _T_732) @[el2_dec_tlu_ctl.scala 2162:74] + node _T_733 = bits(wr_dicawics_r, 0, 0) @[el2_dec_tlu_ctl.scala 2164:51] + inst rvclkhdr_19 of rvclkhdr_27 @[el2_lib.scala 508:23] + rvclkhdr_19.clock <= clock + rvclkhdr_19.reset <= reset + rvclkhdr_19.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_19.io.en <= _T_733 @[el2_lib.scala 511:17] + rvclkhdr_19.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg dicawics : UInt, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + dicawics <= dicawics_ns @[el2_lib.scala 514:16] + node _T_734 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[el2_dec_tlu_ctl.scala 2180:49] + node _T_735 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2180:94] + node _T_736 = eq(_T_735, UInt<12>("h07c9")) @[el2_dec_tlu_ctl.scala 2180:101] + node wr_dicad0_r = and(_T_734, _T_736) @[el2_dec_tlu_ctl.scala 2180:72] + node _T_737 = bits(wr_dicad0_r, 0, 0) @[el2_dec_tlu_ctl.scala 2181:35] + node dicad0_ns = mux(_T_737, io.dec_csr_wrdata_r, io.ifu_ic_debug_rd_data) @[el2_dec_tlu_ctl.scala 2181:22] + node _T_738 = or(wr_dicad0_r, io.ifu_ic_debug_rd_data_valid) @[el2_dec_tlu_ctl.scala 2183:47] + node _T_739 = bits(_T_738, 0, 0) @[el2_dec_tlu_ctl.scala 2183:80] + inst rvclkhdr_20 of rvclkhdr_28 @[el2_lib.scala 508:23] + rvclkhdr_20.clock <= clock + rvclkhdr_20.reset <= reset + rvclkhdr_20.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_20.io.en <= _T_739 @[el2_lib.scala 511:17] + rvclkhdr_20.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg dicad0 : UInt, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + dicad0 <= dicad0_ns @[el2_lib.scala 514:16] + node _T_740 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[el2_dec_tlu_ctl.scala 2193:50] + node _T_741 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2193:95] + node _T_742 = eq(_T_741, UInt<12>("h07cc")) @[el2_dec_tlu_ctl.scala 2193:102] + node wr_dicad0h_r = and(_T_740, _T_742) @[el2_dec_tlu_ctl.scala 2193:73] + node _T_743 = bits(wr_dicad0h_r, 0, 0) @[el2_dec_tlu_ctl.scala 2195:37] + node _T_744 = bits(io.ifu_ic_debug_rd_data, 63, 32) @[el2_dec_tlu_ctl.scala 2195:89] + node dicad0h_ns = mux(_T_743, io.dec_csr_wrdata_r, _T_744) @[el2_dec_tlu_ctl.scala 2195:23] + node _T_745 = or(wr_dicad0h_r, io.ifu_ic_debug_rd_data_valid) @[el2_dec_tlu_ctl.scala 2197:49] + node _T_746 = bits(_T_745, 0, 0) @[el2_dec_tlu_ctl.scala 2197:82] + inst rvclkhdr_21 of rvclkhdr_29 @[el2_lib.scala 508:23] + rvclkhdr_21.clock <= clock + rvclkhdr_21.reset <= reset + rvclkhdr_21.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_21.io.en <= _T_746 @[el2_lib.scala 511:17] + rvclkhdr_21.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg dicad0h : UInt, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + dicad0h <= dicad0h_ns @[el2_lib.scala 514:16] + wire _T_747 : UInt<7> + _T_747 <= UInt<1>("h00") + node _T_748 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[el2_dec_tlu_ctl.scala 2205:51] + node _T_749 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2205:96] + node _T_750 = eq(_T_749, UInt<12>("h07ca")) @[el2_dec_tlu_ctl.scala 2205:103] + node _T_751 = and(_T_748, _T_750) @[el2_dec_tlu_ctl.scala 2205:74] + node _T_752 = bits(_T_751, 0, 0) @[el2_dec_tlu_ctl.scala 2207:37] + node _T_753 = bits(io.ifu_ic_debug_rd_data, 70, 64) @[el2_dec_tlu_ctl.scala 2207:89] + node _T_754 = mux(_T_752, io.dec_csr_wrdata_r, _T_753) @[el2_dec_tlu_ctl.scala 2207:24] + node _T_755 = or(_T_751, io.ifu_ic_debug_rd_data_valid) @[el2_dec_tlu_ctl.scala 2209:81] + node _T_756 = bits(_T_755, 0, 0) @[el2_dec_tlu_ctl.scala 2209:114] + reg _T_757 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_756 : @[Reg.scala 28:19] + _T_757 <= _T_754 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_747 <= _T_757 @[el2_dec_tlu_ctl.scala 2209:16] + node _T_758 = cat(UInt<25>("h00"), _T_747) @[Cat.scala 29:58] + dicad1 <= _T_758 @[el2_dec_tlu_ctl.scala 2210:12] + node _T_759 = bits(dicad1, 6, 0) @[el2_dec_tlu_ctl.scala 2232:78] + node _T_760 = bits(dicad0h, 31, 0) @[el2_dec_tlu_ctl.scala 2232:92] + node _T_761 = bits(dicad0, 31, 0) @[el2_dec_tlu_ctl.scala 2232:106] + node _T_762 = cat(_T_759, _T_760) @[Cat.scala 29:58] + node _T_763 = cat(_T_762, _T_761) @[Cat.scala 29:58] + io.dec_tlu_ic_diag_pkt.icache_wrdata <= _T_763 @[el2_dec_tlu_ctl.scala 2232:65] + io.dec_tlu_ic_diag_pkt.icache_dicawics <= dicawics @[el2_dec_tlu_ctl.scala 2235:42] + node _T_764 = and(io.allow_dbg_halt_csr_write, io.dec_csr_any_unq_d) @[el2_dec_tlu_ctl.scala 2237:53] + node _T_765 = and(_T_764, io.dec_i0_decode_d) @[el2_dec_tlu_ctl.scala 2237:76] + node _T_766 = not(io.dec_csr_wen_unq_d) @[el2_dec_tlu_ctl.scala 2237:99] + node _T_767 = and(_T_765, _T_766) @[el2_dec_tlu_ctl.scala 2237:97] + node _T_768 = bits(io.dec_csr_rdaddr_d, 11, 0) @[el2_dec_tlu_ctl.scala 2237:143] + node _T_769 = eq(_T_768, UInt<12>("h07cb")) @[el2_dec_tlu_ctl.scala 2237:150] + node icache_rd_valid = and(_T_767, _T_769) @[el2_dec_tlu_ctl.scala 2237:121] + node _T_770 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[el2_dec_tlu_ctl.scala 2238:53] + node _T_771 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2238:98] + node _T_772 = eq(_T_771, UInt<12>("h07cb")) @[el2_dec_tlu_ctl.scala 2238:105] + node icache_wr_valid = and(_T_770, _T_772) @[el2_dec_tlu_ctl.scala 2238:76] + reg icache_rd_valid_f : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2240:59] + icache_rd_valid_f <= icache_rd_valid @[el2_dec_tlu_ctl.scala 2240:59] + reg icache_wr_valid_f : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2241:59] + icache_wr_valid_f <= icache_wr_valid @[el2_dec_tlu_ctl.scala 2241:59] + io.dec_tlu_ic_diag_pkt.icache_rd_valid <= icache_rd_valid_f @[el2_dec_tlu_ctl.scala 2243:42] + io.dec_tlu_ic_diag_pkt.icache_wr_valid <= icache_wr_valid_f @[el2_dec_tlu_ctl.scala 2244:42] + node _T_773 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2252:63] + node _T_774 = eq(_T_773, UInt<12>("h07a0")) @[el2_dec_tlu_ctl.scala 2252:70] + node wr_mtsel_r = and(io.dec_csr_wen_r_mod, _T_774) @[el2_dec_tlu_ctl.scala 2252:41] + node _T_775 = bits(wr_mtsel_r, 0, 0) @[el2_dec_tlu_ctl.scala 2253:33] + node _T_776 = bits(io.dec_csr_wrdata_r, 1, 0) @[el2_dec_tlu_ctl.scala 2253:60] + node mtsel_ns = mux(_T_775, _T_776, mtsel) @[el2_dec_tlu_ctl.scala 2253:21] + reg _T_777 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2255:44] + _T_777 <= mtsel_ns @[el2_dec_tlu_ctl.scala 2255:44] + mtsel <= _T_777 @[el2_dec_tlu_ctl.scala 2255:9] + node _T_778 = bits(io.dec_csr_wrdata_r, 0, 0) @[el2_dec_tlu_ctl.scala 2290:39] + node _T_779 = bits(io.dec_csr_wrdata_r, 19, 19) @[el2_dec_tlu_ctl.scala 2290:65] + node _T_780 = not(_T_779) @[el2_dec_tlu_ctl.scala 2290:45] + node tdata_load = and(_T_778, _T_780) @[el2_dec_tlu_ctl.scala 2290:43] + node _T_781 = bits(io.dec_csr_wrdata_r, 2, 2) @[el2_dec_tlu_ctl.scala 2292:41] + node _T_782 = bits(io.dec_csr_wrdata_r, 19, 19) @[el2_dec_tlu_ctl.scala 2292:67] + node _T_783 = not(_T_782) @[el2_dec_tlu_ctl.scala 2292:47] + node tdata_opcode = and(_T_781, _T_783) @[el2_dec_tlu_ctl.scala 2292:45] + node _T_784 = bits(io.dec_csr_wrdata_r, 27, 27) @[el2_dec_tlu_ctl.scala 2294:42] + node _T_785 = and(_T_784, io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2294:47] + node _T_786 = bits(io.dec_csr_wrdata_r, 12, 12) @[el2_dec_tlu_ctl.scala 2294:91] + node tdata_action = and(_T_785, _T_786) @[el2_dec_tlu_ctl.scala 2294:70] + node _T_787 = bits(io.dec_csr_wrdata_r, 27, 27) @[el2_dec_tlu_ctl.scala 2296:48] + node _T_788 = and(_T_787, io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2296:53] + node _T_789 = bits(io.dec_csr_wrdata_r, 20, 19) @[el2_dec_tlu_ctl.scala 2296:95] + node _T_790 = bits(io.dec_csr_wrdata_r, 11, 11) @[el2_dec_tlu_ctl.scala 2296:137] + node _T_791 = bits(io.dec_csr_wrdata_r, 7, 6) @[el2_dec_tlu_ctl.scala 2297:24] + node _T_792 = bits(io.dec_csr_wrdata_r, 1, 1) @[el2_dec_tlu_ctl.scala 2297:64] + node _T_793 = cat(_T_792, tdata_load) @[Cat.scala 29:58] + node _T_794 = cat(_T_791, tdata_opcode) @[Cat.scala 29:58] + node _T_795 = cat(_T_794, _T_793) @[Cat.scala 29:58] + node _T_796 = cat(tdata_action, _T_790) @[Cat.scala 29:58] + node _T_797 = cat(_T_788, _T_789) @[Cat.scala 29:58] + node _T_798 = cat(_T_797, _T_796) @[Cat.scala 29:58] + node tdata_wrdata_r = cat(_T_798, _T_795) @[Cat.scala 29:58] + node _T_799 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2300:93] + node _T_800 = eq(_T_799, UInt<12>("h07a1")) @[el2_dec_tlu_ctl.scala 2300:100] + node _T_801 = and(io.dec_csr_wen_r_mod, _T_800) @[el2_dec_tlu_ctl.scala 2300:71] + node _T_802 = eq(mtsel, UInt<2>("h00")) @[el2_dec_tlu_ctl.scala 2300:122] + node _T_803 = and(_T_801, _T_802) @[el2_dec_tlu_ctl.scala 2300:113] + node _T_804 = bits(io.mtdata1_t[0], 9, 9) @[el2_dec_tlu_ctl.scala 2300:155] + node _T_805 = not(_T_804) @[el2_dec_tlu_ctl.scala 2300:139] + node _T_806 = or(_T_805, io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2300:171] + node _T_807 = and(_T_803, _T_806) @[el2_dec_tlu_ctl.scala 2300:136] + node _T_808 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2300:93] + node _T_809 = eq(_T_808, UInt<12>("h07a1")) @[el2_dec_tlu_ctl.scala 2300:100] + node _T_810 = and(io.dec_csr_wen_r_mod, _T_809) @[el2_dec_tlu_ctl.scala 2300:71] + node _T_811 = eq(mtsel, UInt<2>("h00")) @[el2_dec_tlu_ctl.scala 2300:122] + node _T_812 = and(_T_810, _T_811) @[el2_dec_tlu_ctl.scala 2300:113] + node _T_813 = bits(io.mtdata1_t[1], 9, 9) @[el2_dec_tlu_ctl.scala 2300:155] + node _T_814 = not(_T_813) @[el2_dec_tlu_ctl.scala 2300:139] + node _T_815 = or(_T_814, io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2300:171] + node _T_816 = and(_T_812, _T_815) @[el2_dec_tlu_ctl.scala 2300:136] + node _T_817 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2300:93] + node _T_818 = eq(_T_817, UInt<12>("h07a1")) @[el2_dec_tlu_ctl.scala 2300:100] + node _T_819 = and(io.dec_csr_wen_r_mod, _T_818) @[el2_dec_tlu_ctl.scala 2300:71] + node _T_820 = eq(mtsel, UInt<2>("h00")) @[el2_dec_tlu_ctl.scala 2300:122] + node _T_821 = and(_T_819, _T_820) @[el2_dec_tlu_ctl.scala 2300:113] + node _T_822 = bits(io.mtdata1_t[2], 9, 9) @[el2_dec_tlu_ctl.scala 2300:155] + node _T_823 = not(_T_822) @[el2_dec_tlu_ctl.scala 2300:139] + node _T_824 = or(_T_823, io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2300:171] + node _T_825 = and(_T_821, _T_824) @[el2_dec_tlu_ctl.scala 2300:136] + node _T_826 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2300:93] + node _T_827 = eq(_T_826, UInt<12>("h07a1")) @[el2_dec_tlu_ctl.scala 2300:100] + node _T_828 = and(io.dec_csr_wen_r_mod, _T_827) @[el2_dec_tlu_ctl.scala 2300:71] + node _T_829 = eq(mtsel, UInt<2>("h00")) @[el2_dec_tlu_ctl.scala 2300:122] + node _T_830 = and(_T_828, _T_829) @[el2_dec_tlu_ctl.scala 2300:113] + node _T_831 = bits(io.mtdata1_t[3], 9, 9) @[el2_dec_tlu_ctl.scala 2300:155] + node _T_832 = not(_T_831) @[el2_dec_tlu_ctl.scala 2300:139] + node _T_833 = or(_T_832, io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2300:171] + node _T_834 = and(_T_830, _T_833) @[el2_dec_tlu_ctl.scala 2300:136] + wire wr_mtdata1_t_r : UInt<1>[4] @[el2_dec_tlu_ctl.scala 2300:43] + wr_mtdata1_t_r[0] <= _T_807 @[el2_dec_tlu_ctl.scala 2300:43] + wr_mtdata1_t_r[1] <= _T_816 @[el2_dec_tlu_ctl.scala 2300:43] + wr_mtdata1_t_r[2] <= _T_825 @[el2_dec_tlu_ctl.scala 2300:43] + wr_mtdata1_t_r[3] <= _T_834 @[el2_dec_tlu_ctl.scala 2300:43] + node _T_835 = bits(wr_mtdata1_t_r[0], 0, 0) @[el2_dec_tlu_ctl.scala 2301:69] + node _T_836 = bits(io.mtdata1_t[0], 9, 9) @[el2_dec_tlu_ctl.scala 2301:112] + node _T_837 = bits(io.update_hit_bit_r, 0, 0) @[el2_dec_tlu_ctl.scala 2301:136] + node _T_838 = bits(io.mtdata1_t[0], 8, 8) @[el2_dec_tlu_ctl.scala 2301:157] + node _T_839 = or(_T_837, _T_838) @[el2_dec_tlu_ctl.scala 2301:140] + node _T_840 = bits(io.mtdata1_t[0], 7, 0) @[el2_dec_tlu_ctl.scala 2301:177] + node _T_841 = cat(_T_836, _T_839) @[Cat.scala 29:58] + node _T_842 = cat(_T_841, _T_840) @[Cat.scala 29:58] + node _T_843 = mux(_T_835, tdata_wrdata_r, _T_842) @[el2_dec_tlu_ctl.scala 2301:50] + node _T_844 = bits(wr_mtdata1_t_r[1], 0, 0) @[el2_dec_tlu_ctl.scala 2301:69] + node _T_845 = bits(io.mtdata1_t[1], 9, 9) @[el2_dec_tlu_ctl.scala 2301:112] + node _T_846 = bits(io.update_hit_bit_r, 1, 1) @[el2_dec_tlu_ctl.scala 2301:136] + node _T_847 = bits(io.mtdata1_t[1], 8, 8) @[el2_dec_tlu_ctl.scala 2301:157] + node _T_848 = or(_T_846, _T_847) @[el2_dec_tlu_ctl.scala 2301:140] + node _T_849 = bits(io.mtdata1_t[1], 7, 0) @[el2_dec_tlu_ctl.scala 2301:177] + node _T_850 = cat(_T_845, _T_848) @[Cat.scala 29:58] + node _T_851 = cat(_T_850, _T_849) @[Cat.scala 29:58] + node _T_852 = mux(_T_844, tdata_wrdata_r, _T_851) @[el2_dec_tlu_ctl.scala 2301:50] + node _T_853 = bits(wr_mtdata1_t_r[2], 0, 0) @[el2_dec_tlu_ctl.scala 2301:69] + node _T_854 = bits(io.mtdata1_t[2], 9, 9) @[el2_dec_tlu_ctl.scala 2301:112] + node _T_855 = bits(io.update_hit_bit_r, 2, 2) @[el2_dec_tlu_ctl.scala 2301:136] + node _T_856 = bits(io.mtdata1_t[2], 8, 8) @[el2_dec_tlu_ctl.scala 2301:157] + node _T_857 = or(_T_855, _T_856) @[el2_dec_tlu_ctl.scala 2301:140] + node _T_858 = bits(io.mtdata1_t[2], 7, 0) @[el2_dec_tlu_ctl.scala 2301:177] + node _T_859 = cat(_T_854, _T_857) @[Cat.scala 29:58] + node _T_860 = cat(_T_859, _T_858) @[Cat.scala 29:58] + node _T_861 = mux(_T_853, tdata_wrdata_r, _T_860) @[el2_dec_tlu_ctl.scala 2301:50] + node _T_862 = bits(wr_mtdata1_t_r[3], 0, 0) @[el2_dec_tlu_ctl.scala 2301:69] + node _T_863 = bits(io.mtdata1_t[3], 9, 9) @[el2_dec_tlu_ctl.scala 2301:112] + node _T_864 = bits(io.update_hit_bit_r, 3, 3) @[el2_dec_tlu_ctl.scala 2301:136] + node _T_865 = bits(io.mtdata1_t[3], 8, 8) @[el2_dec_tlu_ctl.scala 2301:157] + node _T_866 = or(_T_864, _T_865) @[el2_dec_tlu_ctl.scala 2301:140] + node _T_867 = bits(io.mtdata1_t[3], 7, 0) @[el2_dec_tlu_ctl.scala 2301:177] + node _T_868 = cat(_T_863, _T_866) @[Cat.scala 29:58] + node _T_869 = cat(_T_868, _T_867) @[Cat.scala 29:58] + node _T_870 = mux(_T_862, tdata_wrdata_r, _T_869) @[el2_dec_tlu_ctl.scala 2301:50] + wire mtdata1_t_ns : UInt<10>[4] @[el2_dec_tlu_ctl.scala 2301:41] + mtdata1_t_ns[0] <= _T_843 @[el2_dec_tlu_ctl.scala 2301:41] + mtdata1_t_ns[1] <= _T_852 @[el2_dec_tlu_ctl.scala 2301:41] + mtdata1_t_ns[2] <= _T_861 @[el2_dec_tlu_ctl.scala 2301:41] + mtdata1_t_ns[3] <= _T_870 @[el2_dec_tlu_ctl.scala 2301:41] + reg _T_871 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2303:76] + _T_871 <= mtdata1_t_ns[0] @[el2_dec_tlu_ctl.scala 2303:76] + io.mtdata1_t[0] <= _T_871 @[el2_dec_tlu_ctl.scala 2303:41] + reg _T_872 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2303:76] + _T_872 <= mtdata1_t_ns[1] @[el2_dec_tlu_ctl.scala 2303:76] + io.mtdata1_t[1] <= _T_872 @[el2_dec_tlu_ctl.scala 2303:41] + reg _T_873 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2303:76] + _T_873 <= mtdata1_t_ns[2] @[el2_dec_tlu_ctl.scala 2303:76] + io.mtdata1_t[2] <= _T_873 @[el2_dec_tlu_ctl.scala 2303:41] + reg _T_874 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2303:76] + _T_874 <= mtdata1_t_ns[3] @[el2_dec_tlu_ctl.scala 2303:76] + io.mtdata1_t[3] <= _T_874 @[el2_dec_tlu_ctl.scala 2303:41] + node _T_875 = eq(mtsel, UInt<2>("h00")) @[el2_dec_tlu_ctl.scala 2306:60] + node _T_876 = bits(io.mtdata1_t[0], 9, 9) @[el2_dec_tlu_ctl.scala 2306:106] + node _T_877 = bits(io.mtdata1_t[0], 8, 7) @[el2_dec_tlu_ctl.scala 2306:144] + node _T_878 = bits(io.mtdata1_t[0], 6, 5) @[el2_dec_tlu_ctl.scala 2306:176] + node _T_879 = bits(io.mtdata1_t[0], 4, 3) @[el2_dec_tlu_ctl.scala 2306:208] + node _T_880 = bits(io.mtdata1_t[0], 2, 0) @[el2_dec_tlu_ctl.scala 2306:240] + node _T_881 = cat(UInt<3>("h00"), _T_880) @[Cat.scala 29:58] + node _T_882 = cat(_T_878, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_883 = cat(_T_882, _T_879) @[Cat.scala 29:58] + node _T_884 = cat(_T_883, _T_881) @[Cat.scala 29:58] + node _T_885 = cat(_T_877, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_886 = cat(UInt<4>("h02"), _T_876) @[Cat.scala 29:58] + node _T_887 = cat(_T_886, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_888 = cat(_T_887, _T_885) @[Cat.scala 29:58] + node _T_889 = cat(_T_888, _T_884) @[Cat.scala 29:58] + node _T_890 = eq(mtsel, UInt<2>("h01")) @[el2_dec_tlu_ctl.scala 2306:60] + node _T_891 = bits(io.mtdata1_t[1], 9, 9) @[el2_dec_tlu_ctl.scala 2306:106] + node _T_892 = bits(io.mtdata1_t[1], 8, 7) @[el2_dec_tlu_ctl.scala 2306:144] + node _T_893 = bits(io.mtdata1_t[1], 6, 5) @[el2_dec_tlu_ctl.scala 2306:176] + node _T_894 = bits(io.mtdata1_t[1], 4, 3) @[el2_dec_tlu_ctl.scala 2306:208] + node _T_895 = bits(io.mtdata1_t[1], 2, 0) @[el2_dec_tlu_ctl.scala 2306:240] + node _T_896 = cat(UInt<3>("h00"), _T_895) @[Cat.scala 29:58] + node _T_897 = cat(_T_893, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_898 = cat(_T_897, _T_894) @[Cat.scala 29:58] + node _T_899 = cat(_T_898, _T_896) @[Cat.scala 29:58] + node _T_900 = cat(_T_892, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_901 = cat(UInt<4>("h02"), _T_891) @[Cat.scala 29:58] + node _T_902 = cat(_T_901, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_903 = cat(_T_902, _T_900) @[Cat.scala 29:58] + node _T_904 = cat(_T_903, _T_899) @[Cat.scala 29:58] + node _T_905 = eq(mtsel, UInt<2>("h02")) @[el2_dec_tlu_ctl.scala 2306:60] + node _T_906 = bits(io.mtdata1_t[2], 9, 9) @[el2_dec_tlu_ctl.scala 2306:106] + node _T_907 = bits(io.mtdata1_t[2], 8, 7) @[el2_dec_tlu_ctl.scala 2306:144] + node _T_908 = bits(io.mtdata1_t[2], 6, 5) @[el2_dec_tlu_ctl.scala 2306:176] + node _T_909 = bits(io.mtdata1_t[2], 4, 3) @[el2_dec_tlu_ctl.scala 2306:208] + node _T_910 = bits(io.mtdata1_t[2], 2, 0) @[el2_dec_tlu_ctl.scala 2306:240] + node _T_911 = cat(UInt<3>("h00"), _T_910) @[Cat.scala 29:58] + node _T_912 = cat(_T_908, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_913 = cat(_T_912, _T_909) @[Cat.scala 29:58] + node _T_914 = cat(_T_913, _T_911) @[Cat.scala 29:58] + node _T_915 = cat(_T_907, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_916 = cat(UInt<4>("h02"), _T_906) @[Cat.scala 29:58] + node _T_917 = cat(_T_916, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_918 = cat(_T_917, _T_915) @[Cat.scala 29:58] + node _T_919 = cat(_T_918, _T_914) @[Cat.scala 29:58] + node _T_920 = eq(mtsel, UInt<2>("h03")) @[el2_dec_tlu_ctl.scala 2306:60] + node _T_921 = bits(io.mtdata1_t[3], 9, 9) @[el2_dec_tlu_ctl.scala 2306:106] + node _T_922 = bits(io.mtdata1_t[3], 8, 7) @[el2_dec_tlu_ctl.scala 2306:144] + node _T_923 = bits(io.mtdata1_t[3], 6, 5) @[el2_dec_tlu_ctl.scala 2306:176] + node _T_924 = bits(io.mtdata1_t[3], 4, 3) @[el2_dec_tlu_ctl.scala 2306:208] + node _T_925 = bits(io.mtdata1_t[3], 2, 0) @[el2_dec_tlu_ctl.scala 2306:240] + node _T_926 = cat(UInt<3>("h00"), _T_925) @[Cat.scala 29:58] + node _T_927 = cat(_T_923, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_928 = cat(_T_927, _T_924) @[Cat.scala 29:58] + node _T_929 = cat(_T_928, _T_926) @[Cat.scala 29:58] + node _T_930 = cat(_T_922, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_931 = cat(UInt<4>("h02"), _T_921) @[Cat.scala 29:58] + node _T_932 = cat(_T_931, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_933 = cat(_T_932, _T_930) @[Cat.scala 29:58] + node _T_934 = cat(_T_933, _T_929) @[Cat.scala 29:58] + node _T_935 = mux(_T_875, _T_889, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_936 = mux(_T_890, _T_904, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_937 = mux(_T_905, _T_919, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_938 = mux(_T_920, _T_934, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_939 = or(_T_935, _T_936) @[Mux.scala 27:72] + node _T_940 = or(_T_939, _T_937) @[Mux.scala 27:72] + node _T_941 = or(_T_940, _T_938) @[Mux.scala 27:72] + wire mtdata1_tsel_out : UInt<32> @[Mux.scala 27:72] + mtdata1_tsel_out <= _T_941 @[Mux.scala 27:72] + node _T_942 = bits(io.mtdata1_t[0], 7, 7) @[el2_dec_tlu_ctl.scala 2308:54] + io.trigger_pkt_any[0].select <= _T_942 @[el2_dec_tlu_ctl.scala 2308:36] + node _T_943 = bits(io.mtdata1_t[0], 4, 4) @[el2_dec_tlu_ctl.scala 2309:57] + io.trigger_pkt_any[0].match_pkt <= _T_943 @[el2_dec_tlu_ctl.scala 2309:39] + node _T_944 = bits(io.mtdata1_t[0], 1, 1) @[el2_dec_tlu_ctl.scala 2310:54] + io.trigger_pkt_any[0].store <= _T_944 @[el2_dec_tlu_ctl.scala 2310:36] + node _T_945 = bits(io.mtdata1_t[0], 0, 0) @[el2_dec_tlu_ctl.scala 2311:54] + io.trigger_pkt_any[0].load <= _T_945 @[el2_dec_tlu_ctl.scala 2311:36] + node _T_946 = bits(io.mtdata1_t[0], 2, 2) @[el2_dec_tlu_ctl.scala 2312:54] + io.trigger_pkt_any[0].execute <= _T_946 @[el2_dec_tlu_ctl.scala 2312:36] + node _T_947 = bits(io.mtdata1_t[0], 3, 3) @[el2_dec_tlu_ctl.scala 2313:54] + io.trigger_pkt_any[0].m <= _T_947 @[el2_dec_tlu_ctl.scala 2313:36] + node _T_948 = bits(io.mtdata1_t[1], 7, 7) @[el2_dec_tlu_ctl.scala 2308:54] + io.trigger_pkt_any[1].select <= _T_948 @[el2_dec_tlu_ctl.scala 2308:36] + node _T_949 = bits(io.mtdata1_t[1], 4, 4) @[el2_dec_tlu_ctl.scala 2309:57] + io.trigger_pkt_any[1].match_pkt <= _T_949 @[el2_dec_tlu_ctl.scala 2309:39] + node _T_950 = bits(io.mtdata1_t[1], 1, 1) @[el2_dec_tlu_ctl.scala 2310:54] + io.trigger_pkt_any[1].store <= _T_950 @[el2_dec_tlu_ctl.scala 2310:36] + node _T_951 = bits(io.mtdata1_t[1], 0, 0) @[el2_dec_tlu_ctl.scala 2311:54] + io.trigger_pkt_any[1].load <= _T_951 @[el2_dec_tlu_ctl.scala 2311:36] + node _T_952 = bits(io.mtdata1_t[1], 2, 2) @[el2_dec_tlu_ctl.scala 2312:54] + io.trigger_pkt_any[1].execute <= _T_952 @[el2_dec_tlu_ctl.scala 2312:36] + node _T_953 = bits(io.mtdata1_t[1], 3, 3) @[el2_dec_tlu_ctl.scala 2313:54] + io.trigger_pkt_any[1].m <= _T_953 @[el2_dec_tlu_ctl.scala 2313:36] + node _T_954 = bits(io.mtdata1_t[2], 7, 7) @[el2_dec_tlu_ctl.scala 2308:54] + io.trigger_pkt_any[2].select <= _T_954 @[el2_dec_tlu_ctl.scala 2308:36] + node _T_955 = bits(io.mtdata1_t[2], 4, 4) @[el2_dec_tlu_ctl.scala 2309:57] + io.trigger_pkt_any[2].match_pkt <= _T_955 @[el2_dec_tlu_ctl.scala 2309:39] + node _T_956 = bits(io.mtdata1_t[2], 1, 1) @[el2_dec_tlu_ctl.scala 2310:54] + io.trigger_pkt_any[2].store <= _T_956 @[el2_dec_tlu_ctl.scala 2310:36] + node _T_957 = bits(io.mtdata1_t[2], 0, 0) @[el2_dec_tlu_ctl.scala 2311:54] + io.trigger_pkt_any[2].load <= _T_957 @[el2_dec_tlu_ctl.scala 2311:36] + node _T_958 = bits(io.mtdata1_t[2], 2, 2) @[el2_dec_tlu_ctl.scala 2312:54] + io.trigger_pkt_any[2].execute <= _T_958 @[el2_dec_tlu_ctl.scala 2312:36] + node _T_959 = bits(io.mtdata1_t[2], 3, 3) @[el2_dec_tlu_ctl.scala 2313:54] + io.trigger_pkt_any[2].m <= _T_959 @[el2_dec_tlu_ctl.scala 2313:36] + node _T_960 = bits(io.mtdata1_t[3], 7, 7) @[el2_dec_tlu_ctl.scala 2308:54] + io.trigger_pkt_any[3].select <= _T_960 @[el2_dec_tlu_ctl.scala 2308:36] + node _T_961 = bits(io.mtdata1_t[3], 4, 4) @[el2_dec_tlu_ctl.scala 2309:57] + io.trigger_pkt_any[3].match_pkt <= _T_961 @[el2_dec_tlu_ctl.scala 2309:39] + node _T_962 = bits(io.mtdata1_t[3], 1, 1) @[el2_dec_tlu_ctl.scala 2310:54] + io.trigger_pkt_any[3].store <= _T_962 @[el2_dec_tlu_ctl.scala 2310:36] + node _T_963 = bits(io.mtdata1_t[3], 0, 0) @[el2_dec_tlu_ctl.scala 2311:54] + io.trigger_pkt_any[3].load <= _T_963 @[el2_dec_tlu_ctl.scala 2311:36] + node _T_964 = bits(io.mtdata1_t[3], 2, 2) @[el2_dec_tlu_ctl.scala 2312:54] + io.trigger_pkt_any[3].execute <= _T_964 @[el2_dec_tlu_ctl.scala 2312:36] + node _T_965 = bits(io.mtdata1_t[3], 3, 3) @[el2_dec_tlu_ctl.scala 2313:54] + io.trigger_pkt_any[3].m <= _T_965 @[el2_dec_tlu_ctl.scala 2313:36] + node _T_966 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2320:92] + node _T_967 = eq(_T_966, UInt<12>("h07a2")) @[el2_dec_tlu_ctl.scala 2320:99] + node _T_968 = and(io.dec_csr_wen_r_mod, _T_967) @[el2_dec_tlu_ctl.scala 2320:70] + node _T_969 = eq(mtsel, UInt<2>("h00")) @[el2_dec_tlu_ctl.scala 2320:121] + node _T_970 = and(_T_968, _T_969) @[el2_dec_tlu_ctl.scala 2320:112] + node _T_971 = bits(io.mtdata1_t[0], 9, 9) @[el2_dec_tlu_ctl.scala 2320:154] + node _T_972 = not(_T_971) @[el2_dec_tlu_ctl.scala 2320:138] + node _T_973 = or(_T_972, io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2320:170] + node _T_974 = and(_T_970, _T_973) @[el2_dec_tlu_ctl.scala 2320:135] + node _T_975 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2320:92] + node _T_976 = eq(_T_975, UInt<12>("h07a2")) @[el2_dec_tlu_ctl.scala 2320:99] + node _T_977 = and(io.dec_csr_wen_r_mod, _T_976) @[el2_dec_tlu_ctl.scala 2320:70] + node _T_978 = eq(mtsel, UInt<2>("h01")) @[el2_dec_tlu_ctl.scala 2320:121] + node _T_979 = and(_T_977, _T_978) @[el2_dec_tlu_ctl.scala 2320:112] + node _T_980 = bits(io.mtdata1_t[1], 9, 9) @[el2_dec_tlu_ctl.scala 2320:154] + node _T_981 = not(_T_980) @[el2_dec_tlu_ctl.scala 2320:138] + node _T_982 = or(_T_981, io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2320:170] + node _T_983 = and(_T_979, _T_982) @[el2_dec_tlu_ctl.scala 2320:135] + node _T_984 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2320:92] + node _T_985 = eq(_T_984, UInt<12>("h07a2")) @[el2_dec_tlu_ctl.scala 2320:99] + node _T_986 = and(io.dec_csr_wen_r_mod, _T_985) @[el2_dec_tlu_ctl.scala 2320:70] + node _T_987 = eq(mtsel, UInt<2>("h02")) @[el2_dec_tlu_ctl.scala 2320:121] + node _T_988 = and(_T_986, _T_987) @[el2_dec_tlu_ctl.scala 2320:112] + node _T_989 = bits(io.mtdata1_t[2], 9, 9) @[el2_dec_tlu_ctl.scala 2320:154] + node _T_990 = not(_T_989) @[el2_dec_tlu_ctl.scala 2320:138] + node _T_991 = or(_T_990, io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2320:170] + node _T_992 = and(_T_988, _T_991) @[el2_dec_tlu_ctl.scala 2320:135] + node _T_993 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2320:92] + node _T_994 = eq(_T_993, UInt<12>("h07a2")) @[el2_dec_tlu_ctl.scala 2320:99] + node _T_995 = and(io.dec_csr_wen_r_mod, _T_994) @[el2_dec_tlu_ctl.scala 2320:70] + node _T_996 = eq(mtsel, UInt<2>("h03")) @[el2_dec_tlu_ctl.scala 2320:121] + node _T_997 = and(_T_995, _T_996) @[el2_dec_tlu_ctl.scala 2320:112] + node _T_998 = bits(io.mtdata1_t[3], 9, 9) @[el2_dec_tlu_ctl.scala 2320:154] + node _T_999 = not(_T_998) @[el2_dec_tlu_ctl.scala 2320:138] + node _T_1000 = or(_T_999, io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2320:170] + node _T_1001 = and(_T_997, _T_1000) @[el2_dec_tlu_ctl.scala 2320:135] + wire wr_mtdata2_t_r : UInt<1>[4] @[el2_dec_tlu_ctl.scala 2320:43] + wr_mtdata2_t_r[0] <= _T_974 @[el2_dec_tlu_ctl.scala 2320:43] + wr_mtdata2_t_r[1] <= _T_983 @[el2_dec_tlu_ctl.scala 2320:43] + wr_mtdata2_t_r[2] <= _T_992 @[el2_dec_tlu_ctl.scala 2320:43] + wr_mtdata2_t_r[3] <= _T_1001 @[el2_dec_tlu_ctl.scala 2320:43] + node _T_1002 = bits(wr_mtdata2_t_r[0], 0, 0) @[el2_dec_tlu_ctl.scala 2321:86] + inst rvclkhdr_22 of rvclkhdr_30 @[el2_lib.scala 508:23] + rvclkhdr_22.clock <= clock + rvclkhdr_22.reset <= reset + rvclkhdr_22.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_22.io.en <= _T_1002 @[el2_lib.scala 511:17] + rvclkhdr_22.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_1003 : UInt, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_1003 <= io.dec_csr_wrdata_r @[el2_lib.scala 514:16] + mtdata2_t[0] <= _T_1003 @[el2_dec_tlu_ctl.scala 2321:38] + node _T_1004 = bits(wr_mtdata2_t_r[1], 0, 0) @[el2_dec_tlu_ctl.scala 2321:86] + inst rvclkhdr_23 of rvclkhdr_31 @[el2_lib.scala 508:23] + rvclkhdr_23.clock <= clock + rvclkhdr_23.reset <= reset + rvclkhdr_23.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_23.io.en <= _T_1004 @[el2_lib.scala 511:17] + rvclkhdr_23.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_1005 : UInt, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_1005 <= io.dec_csr_wrdata_r @[el2_lib.scala 514:16] + mtdata2_t[1] <= _T_1005 @[el2_dec_tlu_ctl.scala 2321:38] + node _T_1006 = bits(wr_mtdata2_t_r[2], 0, 0) @[el2_dec_tlu_ctl.scala 2321:86] + inst rvclkhdr_24 of rvclkhdr_32 @[el2_lib.scala 508:23] + rvclkhdr_24.clock <= clock + rvclkhdr_24.reset <= reset + rvclkhdr_24.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_24.io.en <= _T_1006 @[el2_lib.scala 511:17] + rvclkhdr_24.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_1007 : UInt, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_1007 <= io.dec_csr_wrdata_r @[el2_lib.scala 514:16] + mtdata2_t[2] <= _T_1007 @[el2_dec_tlu_ctl.scala 2321:38] + node _T_1008 = bits(wr_mtdata2_t_r[3], 0, 0) @[el2_dec_tlu_ctl.scala 2321:86] + inst rvclkhdr_25 of rvclkhdr_33 @[el2_lib.scala 508:23] + rvclkhdr_25.clock <= clock + rvclkhdr_25.reset <= reset + rvclkhdr_25.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_25.io.en <= _T_1008 @[el2_lib.scala 511:17] + rvclkhdr_25.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_1009 : UInt, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_1009 <= io.dec_csr_wrdata_r @[el2_lib.scala 514:16] + mtdata2_t[3] <= _T_1009 @[el2_dec_tlu_ctl.scala 2321:38] + node _T_1010 = eq(mtsel, UInt<2>("h00")) @[el2_dec_tlu_ctl.scala 2325:59] + node _T_1011 = eq(mtsel, UInt<2>("h01")) @[el2_dec_tlu_ctl.scala 2325:59] + node _T_1012 = eq(mtsel, UInt<2>("h02")) @[el2_dec_tlu_ctl.scala 2325:59] + node _T_1013 = eq(mtsel, UInt<2>("h03")) @[el2_dec_tlu_ctl.scala 2325:59] + node _T_1014 = mux(_T_1010, mtdata2_t[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1015 = mux(_T_1011, mtdata2_t[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1016 = mux(_T_1012, mtdata2_t[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1017 = mux(_T_1013, mtdata2_t[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1018 = or(_T_1014, _T_1015) @[Mux.scala 27:72] + node _T_1019 = or(_T_1018, _T_1016) @[Mux.scala 27:72] + node _T_1020 = or(_T_1019, _T_1017) @[Mux.scala 27:72] + wire mtdata2_tsel_out : UInt<32> @[Mux.scala 27:72] + mtdata2_tsel_out <= _T_1020 @[Mux.scala 27:72] + io.trigger_pkt_any[0].tdata2 <= mtdata2_t[0] @[el2_dec_tlu_ctl.scala 2326:53] + io.trigger_pkt_any[1].tdata2 <= mtdata2_t[1] @[el2_dec_tlu_ctl.scala 2326:53] + io.trigger_pkt_any[2].tdata2 <= mtdata2_t[2] @[el2_dec_tlu_ctl.scala 2326:53] + io.trigger_pkt_any[3].tdata2 <= mtdata2_t[3] @[el2_dec_tlu_ctl.scala 2326:53] + mhpme_vec[0] <= mhpme3 @[el2_dec_tlu_ctl.scala 2336:16] + mhpme_vec[1] <= mhpme4 @[el2_dec_tlu_ctl.scala 2337:16] + mhpme_vec[2] <= mhpme5 @[el2_dec_tlu_ctl.scala 2338:16] + mhpme_vec[3] <= mhpme6 @[el2_dec_tlu_ctl.scala 2339:16] + node _T_1021 = bits(io.tlu_i0_commit_cmt, 0, 0) @[Bitwise.scala 72:15] + node _T_1022 = mux(_T_1021, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node pmu_i0_itype_qual = and(io.dec_tlu_packet_r.pmu_i0_itype, _T_1022) @[el2_dec_tlu_ctl.scala 2345:60] + wire mhpmc_inc_r : UInt<1>[4] @[el2_dec_tlu_ctl.scala 2346:25] + wire mhpmc_inc_r_d1 : UInt<1>[4] @[el2_dec_tlu_ctl.scala 2347:28] + node _T_1023 = bits(mcountinhibit, 3, 3) @[el2_dec_tlu_ctl.scala 2351:39] + node _T_1024 = not(_T_1023) @[el2_dec_tlu_ctl.scala 2351:25] + node _T_1025 = eq(mhpme_vec[0], UInt<1>("h01")) @[el2_dec_tlu_ctl.scala 2352:21] + node _T_1026 = bits(_T_1025, 0, 0) @[el2_dec_tlu_ctl.scala 2352:49] + node _T_1027 = eq(mhpme_vec[0], UInt<2>("h02")) @[el2_dec_tlu_ctl.scala 2353:21] + node _T_1028 = bits(_T_1027, 0, 0) @[el2_dec_tlu_ctl.scala 2353:49] + node _T_1029 = eq(mhpme_vec[0], UInt<2>("h03")) @[el2_dec_tlu_ctl.scala 2354:21] + node _T_1030 = bits(_T_1029, 0, 0) @[el2_dec_tlu_ctl.scala 2354:49] + node _T_1031 = eq(mhpme_vec[0], UInt<3>("h04")) @[el2_dec_tlu_ctl.scala 2355:21] + node _T_1032 = bits(_T_1031, 0, 0) @[el2_dec_tlu_ctl.scala 2355:49] + node _T_1033 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2355:83] + node _T_1034 = and(io.tlu_i0_commit_cmt, _T_1033) @[el2_dec_tlu_ctl.scala 2355:81] + node _T_1035 = eq(mhpme_vec[0], UInt<3>("h05")) @[el2_dec_tlu_ctl.scala 2356:21] + node _T_1036 = bits(_T_1035, 0, 0) @[el2_dec_tlu_ctl.scala 2356:49] + node _T_1037 = not(io.exu_pmu_i0_pc4) @[el2_dec_tlu_ctl.scala 2356:83] + node _T_1038 = and(io.tlu_i0_commit_cmt, _T_1037) @[el2_dec_tlu_ctl.scala 2356:81] + node _T_1039 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2356:104] + node _T_1040 = and(_T_1038, _T_1039) @[el2_dec_tlu_ctl.scala 2356:102] + node _T_1041 = eq(mhpme_vec[0], UInt<3>("h06")) @[el2_dec_tlu_ctl.scala 2357:21] + node _T_1042 = bits(_T_1041, 0, 0) @[el2_dec_tlu_ctl.scala 2357:49] + node _T_1043 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[el2_dec_tlu_ctl.scala 2357:81] + node _T_1044 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2357:104] + node _T_1045 = and(_T_1043, _T_1044) @[el2_dec_tlu_ctl.scala 2357:102] + node _T_1046 = eq(mhpme_vec[0], UInt<3>("h07")) @[el2_dec_tlu_ctl.scala 2358:21] + node _T_1047 = bits(_T_1046, 0, 0) @[el2_dec_tlu_ctl.scala 2358:49] + node _T_1048 = eq(mhpme_vec[0], UInt<4>("h08")) @[el2_dec_tlu_ctl.scala 2359:21] + node _T_1049 = bits(_T_1048, 0, 0) @[el2_dec_tlu_ctl.scala 2359:49] + node _T_1050 = eq(mhpme_vec[0], UInt<5>("h01e")) @[el2_dec_tlu_ctl.scala 2360:21] + node _T_1051 = bits(_T_1050, 0, 0) @[el2_dec_tlu_ctl.scala 2360:49] + node _T_1052 = eq(mhpme_vec[0], UInt<4>("h09")) @[el2_dec_tlu_ctl.scala 2361:21] + node _T_1053 = bits(_T_1052, 0, 0) @[el2_dec_tlu_ctl.scala 2361:49] + node _T_1054 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[el2_dec_tlu_ctl.scala 2361:78] + node _T_1055 = eq(mhpme_vec[0], UInt<4>("h0a")) @[el2_dec_tlu_ctl.scala 2362:21] + node _T_1056 = bits(_T_1055, 0, 0) @[el2_dec_tlu_ctl.scala 2362:49] + node _T_1057 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2362:92] + node _T_1058 = eq(mhpme_vec[0], UInt<4>("h0b")) @[el2_dec_tlu_ctl.scala 2363:21] + node _T_1059 = bits(_T_1058, 0, 0) @[el2_dec_tlu_ctl.scala 2363:49] + node _T_1060 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[el2_dec_tlu_ctl.scala 2363:78] + node _T_1061 = eq(mhpme_vec[0], UInt<4>("h0c")) @[el2_dec_tlu_ctl.scala 2364:21] + node _T_1062 = bits(_T_1061, 0, 0) @[el2_dec_tlu_ctl.scala 2364:49] + node _T_1063 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[el2_dec_tlu_ctl.scala 2364:78] + node _T_1064 = eq(mhpme_vec[0], UInt<4>("h0d")) @[el2_dec_tlu_ctl.scala 2365:21] + node _T_1065 = bits(_T_1064, 0, 0) @[el2_dec_tlu_ctl.scala 2365:49] + node _T_1066 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[el2_dec_tlu_ctl.scala 2365:79] + node _T_1067 = eq(mhpme_vec[0], UInt<4>("h0e")) @[el2_dec_tlu_ctl.scala 2366:21] + node _T_1068 = dshr(io.dec_tlu_packet_r.pmu_lsu_misaligned, _T_1067) @[el2_dec_tlu_ctl.scala 2366:7] + node _T_1069 = bits(_T_1068, 0, 0) @[el2_dec_tlu_ctl.scala 2366:7] + node _T_1070 = and(_T_1066, _T_1069) @[el2_dec_tlu_ctl.scala 2365:89] + node _T_1071 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[el2_dec_tlu_ctl.scala 2366:66] + node _T_1072 = and(_T_1070, _T_1071) @[el2_dec_tlu_ctl.scala 2366:45] + node _T_1073 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[el2_dec_tlu_ctl.scala 2367:48] + node _T_1074 = and(_T_1072, _T_1073) @[el2_dec_tlu_ctl.scala 2366:77] + node _T_1075 = eq(mhpme_vec[0], UInt<4>("h0f")) @[el2_dec_tlu_ctl.scala 2368:21] + node _T_1076 = bits(_T_1075, 0, 0) @[el2_dec_tlu_ctl.scala 2368:41] + node _T_1077 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[el2_dec_tlu_ctl.scala 2368:76] + node _T_1078 = eq(mhpme_vec[0], UInt<5>("h010")) @[el2_dec_tlu_ctl.scala 2369:21] + node _T_1079 = bits(_T_1078, 0, 0) @[el2_dec_tlu_ctl.scala 2369:46] + node _T_1080 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[el2_dec_tlu_ctl.scala 2369:76] + node _T_1081 = eq(mhpme_vec[0], UInt<5>("h012")) @[el2_dec_tlu_ctl.scala 2370:21] + node _T_1082 = bits(_T_1081, 0, 0) @[el2_dec_tlu_ctl.scala 2370:46] + node _T_1083 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[el2_dec_tlu_ctl.scala 2370:76] + node _T_1084 = eq(mhpme_vec[0], UInt<5>("h011")) @[el2_dec_tlu_ctl.scala 2371:21] + node _T_1085 = bits(_T_1084, 0, 0) @[el2_dec_tlu_ctl.scala 2371:46] + node _T_1086 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[el2_dec_tlu_ctl.scala 2371:76] + node _T_1087 = eq(mhpme_vec[0], UInt<5>("h013")) @[el2_dec_tlu_ctl.scala 2372:21] + node _T_1088 = bits(_T_1087, 0, 0) @[el2_dec_tlu_ctl.scala 2372:46] + node _T_1089 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[el2_dec_tlu_ctl.scala 2372:76] + node _T_1090 = eq(mhpme_vec[0], UInt<5>("h014")) @[el2_dec_tlu_ctl.scala 2373:21] + node _T_1091 = bits(_T_1090, 0, 0) @[el2_dec_tlu_ctl.scala 2373:46] + node _T_1092 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[el2_dec_tlu_ctl.scala 2373:76] + node _T_1093 = eq(mhpme_vec[0], UInt<5>("h015")) @[el2_dec_tlu_ctl.scala 2374:21] + node _T_1094 = bits(_T_1093, 0, 0) @[el2_dec_tlu_ctl.scala 2374:46] + node _T_1095 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[el2_dec_tlu_ctl.scala 2374:76] + node _T_1096 = eq(mhpme_vec[0], UInt<5>("h016")) @[el2_dec_tlu_ctl.scala 2375:21] + node _T_1097 = bits(_T_1096, 0, 0) @[el2_dec_tlu_ctl.scala 2375:46] + node _T_1098 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[el2_dec_tlu_ctl.scala 2375:76] + node _T_1099 = eq(mhpme_vec[0], UInt<5>("h017")) @[el2_dec_tlu_ctl.scala 2376:21] + node _T_1100 = bits(_T_1099, 0, 0) @[el2_dec_tlu_ctl.scala 2376:46] + node _T_1101 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[el2_dec_tlu_ctl.scala 2376:76] + node _T_1102 = eq(mhpme_vec[0], UInt<5>("h018")) @[el2_dec_tlu_ctl.scala 2377:21] + node _T_1103 = bits(_T_1102, 0, 0) @[el2_dec_tlu_ctl.scala 2377:46] + node _T_1104 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[el2_dec_tlu_ctl.scala 2377:76] + node _T_1105 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[el2_dec_tlu_ctl.scala 2377:109] + node _T_1106 = or(_T_1104, _T_1105) @[el2_dec_tlu_ctl.scala 2377:88] + node _T_1107 = eq(mhpme_vec[0], UInt<5>("h019")) @[el2_dec_tlu_ctl.scala 2378:21] + node _T_1108 = bits(_T_1107, 0, 0) @[el2_dec_tlu_ctl.scala 2378:49] + node _T_1109 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2378:82] + node _T_1110 = eq(mhpme_vec[0], UInt<5>("h01a")) @[el2_dec_tlu_ctl.scala 2379:21] + node _T_1111 = bits(_T_1110, 0, 0) @[el2_dec_tlu_ctl.scala 2379:49] + node _T_1112 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2379:84] + node _T_1113 = eq(mhpme_vec[0], UInt<5>("h01b")) @[el2_dec_tlu_ctl.scala 2380:21] + node _T_1114 = bits(_T_1113, 0, 0) @[el2_dec_tlu_ctl.scala 2380:49] + node _T_1115 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2380:97] + node _T_1116 = eq(mhpme_vec[0], UInt<5>("h01c")) @[el2_dec_tlu_ctl.scala 2381:21] + node _T_1117 = bits(_T_1116, 0, 0) @[el2_dec_tlu_ctl.scala 2381:49] + node _T_1118 = eq(mhpme_vec[0], UInt<5>("h01e")) @[el2_dec_tlu_ctl.scala 2382:21] + node _T_1119 = bits(_T_1118, 0, 0) @[el2_dec_tlu_ctl.scala 2382:49] + node _T_1120 = eq(mhpme_vec[0], UInt<5>("h01f")) @[el2_dec_tlu_ctl.scala 2383:21] + node _T_1121 = bits(_T_1120, 0, 0) @[el2_dec_tlu_ctl.scala 2383:49] + node _T_1122 = eq(mhpme_vec[0], UInt<6>("h020")) @[el2_dec_tlu_ctl.scala 2384:21] + node _T_1123 = bits(_T_1122, 0, 0) @[el2_dec_tlu_ctl.scala 2384:49] + node _T_1124 = eq(mhpme_vec[0], UInt<6>("h022")) @[el2_dec_tlu_ctl.scala 2385:21] + node _T_1125 = bits(_T_1124, 0, 0) @[el2_dec_tlu_ctl.scala 2385:49] + node _T_1126 = eq(mhpme_vec[0], UInt<6>("h023")) @[el2_dec_tlu_ctl.scala 2386:21] + node _T_1127 = bits(_T_1126, 0, 0) @[el2_dec_tlu_ctl.scala 2386:49] + node _T_1128 = eq(mhpme_vec[0], UInt<6>("h024")) @[el2_dec_tlu_ctl.scala 2387:21] + node _T_1129 = bits(_T_1128, 0, 0) @[el2_dec_tlu_ctl.scala 2387:49] + node _T_1130 = eq(mhpme_vec[0], UInt<6>("h025")) @[el2_dec_tlu_ctl.scala 2388:21] + node _T_1131 = bits(_T_1130, 0, 0) @[el2_dec_tlu_ctl.scala 2388:49] + node _T_1132 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 2388:85] + node _T_1133 = or(_T_1132, io.lsu_exc_valid_r) @[el2_dec_tlu_ctl.scala 2388:107] + node _T_1134 = eq(mhpme_vec[0], UInt<6>("h026")) @[el2_dec_tlu_ctl.scala 2389:21] + node _T_1135 = bits(_T_1134, 0, 0) @[el2_dec_tlu_ctl.scala 2389:49] + node _T_1136 = or(io.take_timer_int, io.take_int_timer0_int) @[el2_dec_tlu_ctl.scala 2389:79] + node _T_1137 = or(_T_1136, io.take_int_timer1_int) @[el2_dec_tlu_ctl.scala 2389:104] + node _T_1138 = eq(mhpme_vec[0], UInt<6>("h027")) @[el2_dec_tlu_ctl.scala 2390:21] + node _T_1139 = bits(_T_1138, 0, 0) @[el2_dec_tlu_ctl.scala 2390:49] + node _T_1140 = eq(mhpme_vec[0], UInt<6>("h028")) @[el2_dec_tlu_ctl.scala 2391:21] + node _T_1141 = bits(_T_1140, 0, 0) @[el2_dec_tlu_ctl.scala 2391:49] + node _T_1142 = eq(mhpme_vec[0], UInt<6>("h029")) @[el2_dec_tlu_ctl.scala 2392:21] + node _T_1143 = bits(_T_1142, 0, 0) @[el2_dec_tlu_ctl.scala 2392:49] + node _T_1144 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[el2_dec_tlu_ctl.scala 2392:84] + node _T_1145 = and(_T_1144, io.rfpc_i0_r) @[el2_dec_tlu_ctl.scala 2392:116] + node _T_1146 = eq(mhpme_vec[0], UInt<6>("h02a")) @[el2_dec_tlu_ctl.scala 2393:21] + node _T_1147 = bits(_T_1146, 0, 0) @[el2_dec_tlu_ctl.scala 2393:49] + node _T_1148 = eq(mhpme_vec[0], UInt<6>("h02b")) @[el2_dec_tlu_ctl.scala 2394:21] + node _T_1149 = bits(_T_1148, 0, 0) @[el2_dec_tlu_ctl.scala 2394:49] + node _T_1150 = eq(mhpme_vec[0], UInt<6>("h02c")) @[el2_dec_tlu_ctl.scala 2395:21] + node _T_1151 = bits(_T_1150, 0, 0) @[el2_dec_tlu_ctl.scala 2395:49] + node _T_1152 = eq(mhpme_vec[0], UInt<6>("h02d")) @[el2_dec_tlu_ctl.scala 2396:21] + node _T_1153 = bits(_T_1152, 0, 0) @[el2_dec_tlu_ctl.scala 2396:49] + node _T_1154 = eq(mhpme_vec[0], UInt<6>("h02e")) @[el2_dec_tlu_ctl.scala 2397:21] + node _T_1155 = bits(_T_1154, 0, 0) @[el2_dec_tlu_ctl.scala 2397:49] + node _T_1156 = eq(mhpme_vec[0], UInt<6>("h02f")) @[el2_dec_tlu_ctl.scala 2398:21] + node _T_1157 = bits(_T_1156, 0, 0) @[el2_dec_tlu_ctl.scala 2398:49] + node _T_1158 = eq(mhpme_vec[0], UInt<6>("h030")) @[el2_dec_tlu_ctl.scala 2399:21] + node _T_1159 = bits(_T_1158, 0, 0) @[el2_dec_tlu_ctl.scala 2399:49] + node _T_1160 = eq(mhpme_vec[0], UInt<6>("h031")) @[el2_dec_tlu_ctl.scala 2400:21] + node _T_1161 = bits(_T_1160, 0, 0) @[el2_dec_tlu_ctl.scala 2400:49] + node _T_1162 = dshr(io.mstatus, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2400:71] + node _T_1163 = bits(_T_1162, 0, 0) @[el2_dec_tlu_ctl.scala 2400:71] + node _T_1164 = not(_T_1163) @[el2_dec_tlu_ctl.scala 2400:60] + node _T_1165 = eq(mhpme_vec[0], UInt<6>("h032")) @[el2_dec_tlu_ctl.scala 2401:21] + node _T_1166 = bits(_T_1165, 0, 0) @[el2_dec_tlu_ctl.scala 2401:49] + node _T_1167 = dshr(io.mstatus, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2401:71] + node _T_1168 = bits(_T_1167, 0, 0) @[el2_dec_tlu_ctl.scala 2401:71] + node _T_1169 = not(_T_1168) @[el2_dec_tlu_ctl.scala 2401:60] + node _T_1170 = bits(io.mip, 5, 0) @[el2_dec_tlu_ctl.scala 2401:94] + node _T_1171 = bits(mie, 5, 0) @[el2_dec_tlu_ctl.scala 2401:105] + node _T_1172 = and(_T_1170, _T_1171) @[el2_dec_tlu_ctl.scala 2401:100] + node _T_1173 = and(_T_1169, _T_1172) @[el2_dec_tlu_ctl.scala 2401:85] + node _T_1174 = eq(mhpme_vec[0], UInt<6>("h036")) @[el2_dec_tlu_ctl.scala 2402:21] + node _T_1175 = bits(_T_1174, 0, 0) @[el2_dec_tlu_ctl.scala 2402:49] + node _T_1176 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[el2_dec_tlu_ctl.scala 2402:78] + node _T_1177 = eq(mhpme_vec[0], UInt<6>("h037")) @[el2_dec_tlu_ctl.scala 2403:21] + node _T_1178 = bits(_T_1177, 0, 0) @[el2_dec_tlu_ctl.scala 2403:49] + node _T_1179 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[el2_dec_tlu_ctl.scala 2403:81] + node _T_1180 = eq(mhpme_vec[0], UInt<6>("h038")) @[el2_dec_tlu_ctl.scala 2404:21] + node _T_1181 = bits(_T_1180, 0, 0) @[el2_dec_tlu_ctl.scala 2404:49] + node _T_1182 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[el2_dec_tlu_ctl.scala 2404:81] + node _T_1183 = eq(mhpme_vec[0], UInt<10>("h0200")) @[el2_dec_tlu_ctl.scala 2406:21] + node _T_1184 = bits(_T_1183, 0, 0) @[el2_dec_tlu_ctl.scala 2406:49] + node _T_1185 = eq(mhpme_vec[0], UInt<10>("h0201")) @[el2_dec_tlu_ctl.scala 2407:21] + node _T_1186 = bits(_T_1185, 0, 0) @[el2_dec_tlu_ctl.scala 2407:49] + node _T_1187 = eq(mhpme_vec[0], UInt<10>("h0202")) @[el2_dec_tlu_ctl.scala 2408:21] + node _T_1188 = bits(_T_1187, 0, 0) @[el2_dec_tlu_ctl.scala 2408:49] + node _T_1189 = eq(mhpme_vec[0], UInt<10>("h0203")) @[el2_dec_tlu_ctl.scala 2409:21] + node _T_1190 = bits(_T_1189, 0, 0) @[el2_dec_tlu_ctl.scala 2409:49] + node _T_1191 = eq(mhpme_vec[0], UInt<10>("h0204")) @[el2_dec_tlu_ctl.scala 2410:21] + node _T_1192 = bits(_T_1191, 0, 0) @[el2_dec_tlu_ctl.scala 2410:49] + node _T_1193 = mux(_T_1026, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1194 = mux(_T_1028, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1195 = mux(_T_1030, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1196 = mux(_T_1032, _T_1034, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1197 = mux(_T_1036, _T_1040, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1198 = mux(_T_1042, _T_1045, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1199 = mux(_T_1047, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1200 = mux(_T_1049, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1201 = mux(_T_1051, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1202 = mux(_T_1053, _T_1054, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1203 = mux(_T_1056, _T_1057, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1204 = mux(_T_1059, _T_1060, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1205 = mux(_T_1062, _T_1063, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1206 = mux(_T_1065, _T_1074, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1207 = mux(_T_1076, _T_1077, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1208 = mux(_T_1079, _T_1080, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1209 = mux(_T_1082, _T_1083, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1210 = mux(_T_1085, _T_1086, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1211 = mux(_T_1088, _T_1089, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1212 = mux(_T_1091, _T_1092, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1213 = mux(_T_1094, _T_1095, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1214 = mux(_T_1097, _T_1098, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1215 = mux(_T_1100, _T_1101, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1216 = mux(_T_1103, _T_1106, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1217 = mux(_T_1108, _T_1109, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1218 = mux(_T_1111, _T_1112, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1219 = mux(_T_1114, _T_1115, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1220 = mux(_T_1117, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1221 = mux(_T_1119, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1222 = mux(_T_1121, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1223 = mux(_T_1123, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1224 = mux(_T_1125, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1225 = mux(_T_1127, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1226 = mux(_T_1129, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1227 = mux(_T_1131, _T_1133, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1228 = mux(_T_1135, _T_1137, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1229 = mux(_T_1139, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1230 = mux(_T_1141, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1231 = mux(_T_1143, _T_1145, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1232 = mux(_T_1147, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1233 = mux(_T_1149, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1234 = mux(_T_1151, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1235 = mux(_T_1153, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1236 = mux(_T_1155, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1237 = mux(_T_1157, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1238 = mux(_T_1159, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1239 = mux(_T_1161, _T_1164, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1240 = mux(_T_1166, _T_1173, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1241 = mux(_T_1175, _T_1176, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1242 = mux(_T_1178, _T_1179, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1243 = mux(_T_1181, _T_1182, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1244 = mux(_T_1184, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1245 = mux(_T_1186, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1246 = mux(_T_1188, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1247 = mux(_T_1190, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1248 = mux(_T_1192, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1249 = or(_T_1193, _T_1194) @[Mux.scala 27:72] + node _T_1250 = or(_T_1249, _T_1195) @[Mux.scala 27:72] + node _T_1251 = or(_T_1250, _T_1196) @[Mux.scala 27:72] + node _T_1252 = or(_T_1251, _T_1197) @[Mux.scala 27:72] + node _T_1253 = or(_T_1252, _T_1198) @[Mux.scala 27:72] + node _T_1254 = or(_T_1253, _T_1199) @[Mux.scala 27:72] + node _T_1255 = or(_T_1254, _T_1200) @[Mux.scala 27:72] + node _T_1256 = or(_T_1255, _T_1201) @[Mux.scala 27:72] + node _T_1257 = or(_T_1256, _T_1202) @[Mux.scala 27:72] + node _T_1258 = or(_T_1257, _T_1203) @[Mux.scala 27:72] + node _T_1259 = or(_T_1258, _T_1204) @[Mux.scala 27:72] + node _T_1260 = or(_T_1259, _T_1205) @[Mux.scala 27:72] + node _T_1261 = or(_T_1260, _T_1206) @[Mux.scala 27:72] + node _T_1262 = or(_T_1261, _T_1207) @[Mux.scala 27:72] + node _T_1263 = or(_T_1262, _T_1208) @[Mux.scala 27:72] + node _T_1264 = or(_T_1263, _T_1209) @[Mux.scala 27:72] + node _T_1265 = or(_T_1264, _T_1210) @[Mux.scala 27:72] + node _T_1266 = or(_T_1265, _T_1211) @[Mux.scala 27:72] + node _T_1267 = or(_T_1266, _T_1212) @[Mux.scala 27:72] + node _T_1268 = or(_T_1267, _T_1213) @[Mux.scala 27:72] + node _T_1269 = or(_T_1268, _T_1214) @[Mux.scala 27:72] + node _T_1270 = or(_T_1269, _T_1215) @[Mux.scala 27:72] + node _T_1271 = or(_T_1270, _T_1216) @[Mux.scala 27:72] + node _T_1272 = or(_T_1271, _T_1217) @[Mux.scala 27:72] + node _T_1273 = or(_T_1272, _T_1218) @[Mux.scala 27:72] + node _T_1274 = or(_T_1273, _T_1219) @[Mux.scala 27:72] + node _T_1275 = or(_T_1274, _T_1220) @[Mux.scala 27:72] + node _T_1276 = or(_T_1275, _T_1221) @[Mux.scala 27:72] + node _T_1277 = or(_T_1276, _T_1222) @[Mux.scala 27:72] + node _T_1278 = or(_T_1277, _T_1223) @[Mux.scala 27:72] + node _T_1279 = or(_T_1278, _T_1224) @[Mux.scala 27:72] + node _T_1280 = or(_T_1279, _T_1225) @[Mux.scala 27:72] + node _T_1281 = or(_T_1280, _T_1226) @[Mux.scala 27:72] + node _T_1282 = or(_T_1281, _T_1227) @[Mux.scala 27:72] + node _T_1283 = or(_T_1282, _T_1228) @[Mux.scala 27:72] + node _T_1284 = or(_T_1283, _T_1229) @[Mux.scala 27:72] + node _T_1285 = or(_T_1284, _T_1230) @[Mux.scala 27:72] + node _T_1286 = or(_T_1285, _T_1231) @[Mux.scala 27:72] + node _T_1287 = or(_T_1286, _T_1232) @[Mux.scala 27:72] + node _T_1288 = or(_T_1287, _T_1233) @[Mux.scala 27:72] + node _T_1289 = or(_T_1288, _T_1234) @[Mux.scala 27:72] + node _T_1290 = or(_T_1289, _T_1235) @[Mux.scala 27:72] + node _T_1291 = or(_T_1290, _T_1236) @[Mux.scala 27:72] + node _T_1292 = or(_T_1291, _T_1237) @[Mux.scala 27:72] + node _T_1293 = or(_T_1292, _T_1238) @[Mux.scala 27:72] + node _T_1294 = or(_T_1293, _T_1239) @[Mux.scala 27:72] + node _T_1295 = or(_T_1294, _T_1240) @[Mux.scala 27:72] + node _T_1296 = or(_T_1295, _T_1241) @[Mux.scala 27:72] + node _T_1297 = or(_T_1296, _T_1242) @[Mux.scala 27:72] + node _T_1298 = or(_T_1297, _T_1243) @[Mux.scala 27:72] + node _T_1299 = or(_T_1298, _T_1244) @[Mux.scala 27:72] + node _T_1300 = or(_T_1299, _T_1245) @[Mux.scala 27:72] + node _T_1301 = or(_T_1300, _T_1246) @[Mux.scala 27:72] + node _T_1302 = or(_T_1301, _T_1247) @[Mux.scala 27:72] + node _T_1303 = or(_T_1302, _T_1248) @[Mux.scala 27:72] + wire _T_1304 : UInt<6> @[Mux.scala 27:72] + _T_1304 <= _T_1303 @[Mux.scala 27:72] + node _T_1305 = and(_T_1024, _T_1304) @[el2_dec_tlu_ctl.scala 2351:45] + mhpmc_inc_r[0] <= _T_1305 @[el2_dec_tlu_ctl.scala 2351:20] + node _T_1306 = bits(mcountinhibit, 4, 4) @[el2_dec_tlu_ctl.scala 2351:39] + node _T_1307 = not(_T_1306) @[el2_dec_tlu_ctl.scala 2351:25] + node _T_1308 = eq(mhpme_vec[1], UInt<1>("h01")) @[el2_dec_tlu_ctl.scala 2352:21] + node _T_1309 = bits(_T_1308, 0, 0) @[el2_dec_tlu_ctl.scala 2352:49] + node _T_1310 = eq(mhpme_vec[1], UInt<2>("h02")) @[el2_dec_tlu_ctl.scala 2353:21] + node _T_1311 = bits(_T_1310, 0, 0) @[el2_dec_tlu_ctl.scala 2353:49] + node _T_1312 = eq(mhpme_vec[1], UInt<2>("h03")) @[el2_dec_tlu_ctl.scala 2354:21] + node _T_1313 = bits(_T_1312, 0, 0) @[el2_dec_tlu_ctl.scala 2354:49] + node _T_1314 = eq(mhpme_vec[1], UInt<3>("h04")) @[el2_dec_tlu_ctl.scala 2355:21] + node _T_1315 = bits(_T_1314, 0, 0) @[el2_dec_tlu_ctl.scala 2355:49] + node _T_1316 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2355:83] + node _T_1317 = and(io.tlu_i0_commit_cmt, _T_1316) @[el2_dec_tlu_ctl.scala 2355:81] + node _T_1318 = eq(mhpme_vec[1], UInt<3>("h05")) @[el2_dec_tlu_ctl.scala 2356:21] + node _T_1319 = bits(_T_1318, 0, 0) @[el2_dec_tlu_ctl.scala 2356:49] + node _T_1320 = not(io.exu_pmu_i0_pc4) @[el2_dec_tlu_ctl.scala 2356:83] + node _T_1321 = and(io.tlu_i0_commit_cmt, _T_1320) @[el2_dec_tlu_ctl.scala 2356:81] + node _T_1322 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2356:104] + node _T_1323 = and(_T_1321, _T_1322) @[el2_dec_tlu_ctl.scala 2356:102] + node _T_1324 = eq(mhpme_vec[1], UInt<3>("h06")) @[el2_dec_tlu_ctl.scala 2357:21] + node _T_1325 = bits(_T_1324, 0, 0) @[el2_dec_tlu_ctl.scala 2357:49] + node _T_1326 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[el2_dec_tlu_ctl.scala 2357:81] + node _T_1327 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2357:104] + node _T_1328 = and(_T_1326, _T_1327) @[el2_dec_tlu_ctl.scala 2357:102] + node _T_1329 = eq(mhpme_vec[1], UInt<3>("h07")) @[el2_dec_tlu_ctl.scala 2358:21] + node _T_1330 = bits(_T_1329, 0, 0) @[el2_dec_tlu_ctl.scala 2358:49] + node _T_1331 = eq(mhpme_vec[1], UInt<4>("h08")) @[el2_dec_tlu_ctl.scala 2359:21] + node _T_1332 = bits(_T_1331, 0, 0) @[el2_dec_tlu_ctl.scala 2359:49] + node _T_1333 = eq(mhpme_vec[1], UInt<5>("h01e")) @[el2_dec_tlu_ctl.scala 2360:21] + node _T_1334 = bits(_T_1333, 0, 0) @[el2_dec_tlu_ctl.scala 2360:49] + node _T_1335 = eq(mhpme_vec[1], UInt<4>("h09")) @[el2_dec_tlu_ctl.scala 2361:21] + node _T_1336 = bits(_T_1335, 0, 0) @[el2_dec_tlu_ctl.scala 2361:49] + node _T_1337 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[el2_dec_tlu_ctl.scala 2361:78] + node _T_1338 = eq(mhpme_vec[1], UInt<4>("h0a")) @[el2_dec_tlu_ctl.scala 2362:21] + node _T_1339 = bits(_T_1338, 0, 0) @[el2_dec_tlu_ctl.scala 2362:49] + node _T_1340 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2362:92] + node _T_1341 = eq(mhpme_vec[1], UInt<4>("h0b")) @[el2_dec_tlu_ctl.scala 2363:21] + node _T_1342 = bits(_T_1341, 0, 0) @[el2_dec_tlu_ctl.scala 2363:49] + node _T_1343 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[el2_dec_tlu_ctl.scala 2363:78] + node _T_1344 = eq(mhpme_vec[1], UInt<4>("h0c")) @[el2_dec_tlu_ctl.scala 2364:21] + node _T_1345 = bits(_T_1344, 0, 0) @[el2_dec_tlu_ctl.scala 2364:49] + node _T_1346 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[el2_dec_tlu_ctl.scala 2364:78] + node _T_1347 = eq(mhpme_vec[1], UInt<4>("h0d")) @[el2_dec_tlu_ctl.scala 2365:21] + node _T_1348 = bits(_T_1347, 0, 0) @[el2_dec_tlu_ctl.scala 2365:49] + node _T_1349 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[el2_dec_tlu_ctl.scala 2365:79] + node _T_1350 = eq(mhpme_vec[1], UInt<4>("h0e")) @[el2_dec_tlu_ctl.scala 2366:21] + node _T_1351 = dshr(io.dec_tlu_packet_r.pmu_lsu_misaligned, _T_1350) @[el2_dec_tlu_ctl.scala 2366:7] + node _T_1352 = bits(_T_1351, 0, 0) @[el2_dec_tlu_ctl.scala 2366:7] + node _T_1353 = and(_T_1349, _T_1352) @[el2_dec_tlu_ctl.scala 2365:89] + node _T_1354 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[el2_dec_tlu_ctl.scala 2366:66] + node _T_1355 = and(_T_1353, _T_1354) @[el2_dec_tlu_ctl.scala 2366:45] + node _T_1356 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[el2_dec_tlu_ctl.scala 2367:48] + node _T_1357 = and(_T_1355, _T_1356) @[el2_dec_tlu_ctl.scala 2366:77] + node _T_1358 = eq(mhpme_vec[1], UInt<4>("h0f")) @[el2_dec_tlu_ctl.scala 2368:21] + node _T_1359 = bits(_T_1358, 0, 0) @[el2_dec_tlu_ctl.scala 2368:41] + node _T_1360 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[el2_dec_tlu_ctl.scala 2368:76] + node _T_1361 = eq(mhpme_vec[1], UInt<5>("h010")) @[el2_dec_tlu_ctl.scala 2369:21] + node _T_1362 = bits(_T_1361, 0, 0) @[el2_dec_tlu_ctl.scala 2369:46] + node _T_1363 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[el2_dec_tlu_ctl.scala 2369:76] + node _T_1364 = eq(mhpme_vec[1], UInt<5>("h012")) @[el2_dec_tlu_ctl.scala 2370:21] + node _T_1365 = bits(_T_1364, 0, 0) @[el2_dec_tlu_ctl.scala 2370:46] + node _T_1366 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[el2_dec_tlu_ctl.scala 2370:76] + node _T_1367 = eq(mhpme_vec[1], UInt<5>("h011")) @[el2_dec_tlu_ctl.scala 2371:21] + node _T_1368 = bits(_T_1367, 0, 0) @[el2_dec_tlu_ctl.scala 2371:46] + node _T_1369 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[el2_dec_tlu_ctl.scala 2371:76] + node _T_1370 = eq(mhpme_vec[1], UInt<5>("h013")) @[el2_dec_tlu_ctl.scala 2372:21] + node _T_1371 = bits(_T_1370, 0, 0) @[el2_dec_tlu_ctl.scala 2372:46] + node _T_1372 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[el2_dec_tlu_ctl.scala 2372:76] + node _T_1373 = eq(mhpme_vec[1], UInt<5>("h014")) @[el2_dec_tlu_ctl.scala 2373:21] + node _T_1374 = bits(_T_1373, 0, 0) @[el2_dec_tlu_ctl.scala 2373:46] + node _T_1375 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[el2_dec_tlu_ctl.scala 2373:76] + node _T_1376 = eq(mhpme_vec[1], UInt<5>("h015")) @[el2_dec_tlu_ctl.scala 2374:21] + node _T_1377 = bits(_T_1376, 0, 0) @[el2_dec_tlu_ctl.scala 2374:46] + node _T_1378 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[el2_dec_tlu_ctl.scala 2374:76] + node _T_1379 = eq(mhpme_vec[1], UInt<5>("h016")) @[el2_dec_tlu_ctl.scala 2375:21] + node _T_1380 = bits(_T_1379, 0, 0) @[el2_dec_tlu_ctl.scala 2375:46] + node _T_1381 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[el2_dec_tlu_ctl.scala 2375:76] + node _T_1382 = eq(mhpme_vec[1], UInt<5>("h017")) @[el2_dec_tlu_ctl.scala 2376:21] + node _T_1383 = bits(_T_1382, 0, 0) @[el2_dec_tlu_ctl.scala 2376:46] + node _T_1384 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[el2_dec_tlu_ctl.scala 2376:76] + node _T_1385 = eq(mhpme_vec[1], UInt<5>("h018")) @[el2_dec_tlu_ctl.scala 2377:21] + node _T_1386 = bits(_T_1385, 0, 0) @[el2_dec_tlu_ctl.scala 2377:46] + node _T_1387 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[el2_dec_tlu_ctl.scala 2377:76] + node _T_1388 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[el2_dec_tlu_ctl.scala 2377:109] + node _T_1389 = or(_T_1387, _T_1388) @[el2_dec_tlu_ctl.scala 2377:88] + node _T_1390 = eq(mhpme_vec[1], UInt<5>("h019")) @[el2_dec_tlu_ctl.scala 2378:21] + node _T_1391 = bits(_T_1390, 0, 0) @[el2_dec_tlu_ctl.scala 2378:49] + node _T_1392 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2378:82] + node _T_1393 = eq(mhpme_vec[1], UInt<5>("h01a")) @[el2_dec_tlu_ctl.scala 2379:21] + node _T_1394 = bits(_T_1393, 0, 0) @[el2_dec_tlu_ctl.scala 2379:49] + node _T_1395 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2379:84] + node _T_1396 = eq(mhpme_vec[1], UInt<5>("h01b")) @[el2_dec_tlu_ctl.scala 2380:21] + node _T_1397 = bits(_T_1396, 0, 0) @[el2_dec_tlu_ctl.scala 2380:49] + node _T_1398 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2380:97] + node _T_1399 = eq(mhpme_vec[1], UInt<5>("h01c")) @[el2_dec_tlu_ctl.scala 2381:21] + node _T_1400 = bits(_T_1399, 0, 0) @[el2_dec_tlu_ctl.scala 2381:49] + node _T_1401 = eq(mhpme_vec[1], UInt<5>("h01e")) @[el2_dec_tlu_ctl.scala 2382:21] + node _T_1402 = bits(_T_1401, 0, 0) @[el2_dec_tlu_ctl.scala 2382:49] + node _T_1403 = eq(mhpme_vec[1], UInt<5>("h01f")) @[el2_dec_tlu_ctl.scala 2383:21] + node _T_1404 = bits(_T_1403, 0, 0) @[el2_dec_tlu_ctl.scala 2383:49] + node _T_1405 = eq(mhpme_vec[1], UInt<6>("h020")) @[el2_dec_tlu_ctl.scala 2384:21] + node _T_1406 = bits(_T_1405, 0, 0) @[el2_dec_tlu_ctl.scala 2384:49] + node _T_1407 = eq(mhpme_vec[1], UInt<6>("h022")) @[el2_dec_tlu_ctl.scala 2385:21] + node _T_1408 = bits(_T_1407, 0, 0) @[el2_dec_tlu_ctl.scala 2385:49] + node _T_1409 = eq(mhpme_vec[1], UInt<6>("h023")) @[el2_dec_tlu_ctl.scala 2386:21] + node _T_1410 = bits(_T_1409, 0, 0) @[el2_dec_tlu_ctl.scala 2386:49] + node _T_1411 = eq(mhpme_vec[1], UInt<6>("h024")) @[el2_dec_tlu_ctl.scala 2387:21] + node _T_1412 = bits(_T_1411, 0, 0) @[el2_dec_tlu_ctl.scala 2387:49] + node _T_1413 = eq(mhpme_vec[1], UInt<6>("h025")) @[el2_dec_tlu_ctl.scala 2388:21] + node _T_1414 = bits(_T_1413, 0, 0) @[el2_dec_tlu_ctl.scala 2388:49] + node _T_1415 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 2388:85] + node _T_1416 = or(_T_1415, io.lsu_exc_valid_r) @[el2_dec_tlu_ctl.scala 2388:107] + node _T_1417 = eq(mhpme_vec[1], UInt<6>("h026")) @[el2_dec_tlu_ctl.scala 2389:21] + node _T_1418 = bits(_T_1417, 0, 0) @[el2_dec_tlu_ctl.scala 2389:49] + node _T_1419 = or(io.take_timer_int, io.take_int_timer0_int) @[el2_dec_tlu_ctl.scala 2389:79] + node _T_1420 = or(_T_1419, io.take_int_timer1_int) @[el2_dec_tlu_ctl.scala 2389:104] + node _T_1421 = eq(mhpme_vec[1], UInt<6>("h027")) @[el2_dec_tlu_ctl.scala 2390:21] + node _T_1422 = bits(_T_1421, 0, 0) @[el2_dec_tlu_ctl.scala 2390:49] + node _T_1423 = eq(mhpme_vec[1], UInt<6>("h028")) @[el2_dec_tlu_ctl.scala 2391:21] + node _T_1424 = bits(_T_1423, 0, 0) @[el2_dec_tlu_ctl.scala 2391:49] + node _T_1425 = eq(mhpme_vec[1], UInt<6>("h029")) @[el2_dec_tlu_ctl.scala 2392:21] + node _T_1426 = bits(_T_1425, 0, 0) @[el2_dec_tlu_ctl.scala 2392:49] + node _T_1427 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[el2_dec_tlu_ctl.scala 2392:84] + node _T_1428 = and(_T_1427, io.rfpc_i0_r) @[el2_dec_tlu_ctl.scala 2392:116] + node _T_1429 = eq(mhpme_vec[1], UInt<6>("h02a")) @[el2_dec_tlu_ctl.scala 2393:21] + node _T_1430 = bits(_T_1429, 0, 0) @[el2_dec_tlu_ctl.scala 2393:49] + node _T_1431 = eq(mhpme_vec[1], UInt<6>("h02b")) @[el2_dec_tlu_ctl.scala 2394:21] + node _T_1432 = bits(_T_1431, 0, 0) @[el2_dec_tlu_ctl.scala 2394:49] + node _T_1433 = eq(mhpme_vec[1], UInt<6>("h02c")) @[el2_dec_tlu_ctl.scala 2395:21] + node _T_1434 = bits(_T_1433, 0, 0) @[el2_dec_tlu_ctl.scala 2395:49] + node _T_1435 = eq(mhpme_vec[1], UInt<6>("h02d")) @[el2_dec_tlu_ctl.scala 2396:21] + node _T_1436 = bits(_T_1435, 0, 0) @[el2_dec_tlu_ctl.scala 2396:49] + node _T_1437 = eq(mhpme_vec[1], UInt<6>("h02e")) @[el2_dec_tlu_ctl.scala 2397:21] + node _T_1438 = bits(_T_1437, 0, 0) @[el2_dec_tlu_ctl.scala 2397:49] + node _T_1439 = eq(mhpme_vec[1], UInt<6>("h02f")) @[el2_dec_tlu_ctl.scala 2398:21] + node _T_1440 = bits(_T_1439, 0, 0) @[el2_dec_tlu_ctl.scala 2398:49] + node _T_1441 = eq(mhpme_vec[1], UInt<6>("h030")) @[el2_dec_tlu_ctl.scala 2399:21] + node _T_1442 = bits(_T_1441, 0, 0) @[el2_dec_tlu_ctl.scala 2399:49] + node _T_1443 = eq(mhpme_vec[1], UInt<6>("h031")) @[el2_dec_tlu_ctl.scala 2400:21] + node _T_1444 = bits(_T_1443, 0, 0) @[el2_dec_tlu_ctl.scala 2400:49] + node _T_1445 = dshr(io.mstatus, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2400:71] + node _T_1446 = bits(_T_1445, 0, 0) @[el2_dec_tlu_ctl.scala 2400:71] + node _T_1447 = not(_T_1446) @[el2_dec_tlu_ctl.scala 2400:60] + node _T_1448 = eq(mhpme_vec[1], UInt<6>("h032")) @[el2_dec_tlu_ctl.scala 2401:21] + node _T_1449 = bits(_T_1448, 0, 0) @[el2_dec_tlu_ctl.scala 2401:49] + node _T_1450 = dshr(io.mstatus, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2401:71] + node _T_1451 = bits(_T_1450, 0, 0) @[el2_dec_tlu_ctl.scala 2401:71] + node _T_1452 = not(_T_1451) @[el2_dec_tlu_ctl.scala 2401:60] + node _T_1453 = bits(io.mip, 5, 0) @[el2_dec_tlu_ctl.scala 2401:94] + node _T_1454 = bits(mie, 5, 0) @[el2_dec_tlu_ctl.scala 2401:105] + node _T_1455 = and(_T_1453, _T_1454) @[el2_dec_tlu_ctl.scala 2401:100] + node _T_1456 = and(_T_1452, _T_1455) @[el2_dec_tlu_ctl.scala 2401:85] + node _T_1457 = eq(mhpme_vec[1], UInt<6>("h036")) @[el2_dec_tlu_ctl.scala 2402:21] + node _T_1458 = bits(_T_1457, 0, 0) @[el2_dec_tlu_ctl.scala 2402:49] + node _T_1459 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[el2_dec_tlu_ctl.scala 2402:78] + node _T_1460 = eq(mhpme_vec[1], UInt<6>("h037")) @[el2_dec_tlu_ctl.scala 2403:21] + node _T_1461 = bits(_T_1460, 0, 0) @[el2_dec_tlu_ctl.scala 2403:49] + node _T_1462 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[el2_dec_tlu_ctl.scala 2403:81] + node _T_1463 = eq(mhpme_vec[1], UInt<6>("h038")) @[el2_dec_tlu_ctl.scala 2404:21] + node _T_1464 = bits(_T_1463, 0, 0) @[el2_dec_tlu_ctl.scala 2404:49] + node _T_1465 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[el2_dec_tlu_ctl.scala 2404:81] + node _T_1466 = eq(mhpme_vec[1], UInt<10>("h0200")) @[el2_dec_tlu_ctl.scala 2406:21] + node _T_1467 = bits(_T_1466, 0, 0) @[el2_dec_tlu_ctl.scala 2406:49] + node _T_1468 = eq(mhpme_vec[1], UInt<10>("h0201")) @[el2_dec_tlu_ctl.scala 2407:21] + node _T_1469 = bits(_T_1468, 0, 0) @[el2_dec_tlu_ctl.scala 2407:49] + node _T_1470 = eq(mhpme_vec[1], UInt<10>("h0202")) @[el2_dec_tlu_ctl.scala 2408:21] + node _T_1471 = bits(_T_1470, 0, 0) @[el2_dec_tlu_ctl.scala 2408:49] + node _T_1472 = eq(mhpme_vec[1], UInt<10>("h0203")) @[el2_dec_tlu_ctl.scala 2409:21] + node _T_1473 = bits(_T_1472, 0, 0) @[el2_dec_tlu_ctl.scala 2409:49] + node _T_1474 = eq(mhpme_vec[1], UInt<10>("h0204")) @[el2_dec_tlu_ctl.scala 2410:21] + node _T_1475 = bits(_T_1474, 0, 0) @[el2_dec_tlu_ctl.scala 2410:49] + node _T_1476 = mux(_T_1309, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1477 = mux(_T_1311, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1478 = mux(_T_1313, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1479 = mux(_T_1315, _T_1317, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1480 = mux(_T_1319, _T_1323, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1481 = mux(_T_1325, _T_1328, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1482 = mux(_T_1330, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1483 = mux(_T_1332, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1484 = mux(_T_1334, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1485 = mux(_T_1336, _T_1337, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1486 = mux(_T_1339, _T_1340, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1487 = mux(_T_1342, _T_1343, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1488 = mux(_T_1345, _T_1346, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1489 = mux(_T_1348, _T_1357, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1490 = mux(_T_1359, _T_1360, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1491 = mux(_T_1362, _T_1363, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1492 = mux(_T_1365, _T_1366, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1493 = mux(_T_1368, _T_1369, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1494 = mux(_T_1371, _T_1372, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1495 = mux(_T_1374, _T_1375, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1496 = mux(_T_1377, _T_1378, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1497 = mux(_T_1380, _T_1381, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1498 = mux(_T_1383, _T_1384, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1499 = mux(_T_1386, _T_1389, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1500 = mux(_T_1391, _T_1392, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1501 = mux(_T_1394, _T_1395, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1502 = mux(_T_1397, _T_1398, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1503 = mux(_T_1400, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1504 = mux(_T_1402, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1505 = mux(_T_1404, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1506 = mux(_T_1406, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1507 = mux(_T_1408, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1508 = mux(_T_1410, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1509 = mux(_T_1412, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1510 = mux(_T_1414, _T_1416, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1511 = mux(_T_1418, _T_1420, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1512 = mux(_T_1422, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1513 = mux(_T_1424, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1514 = mux(_T_1426, _T_1428, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1515 = mux(_T_1430, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1516 = mux(_T_1432, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1517 = mux(_T_1434, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1518 = mux(_T_1436, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1519 = mux(_T_1438, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1520 = mux(_T_1440, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1521 = mux(_T_1442, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1522 = mux(_T_1444, _T_1447, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1523 = mux(_T_1449, _T_1456, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1524 = mux(_T_1458, _T_1459, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1525 = mux(_T_1461, _T_1462, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1526 = mux(_T_1464, _T_1465, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1527 = mux(_T_1467, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1528 = mux(_T_1469, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1529 = mux(_T_1471, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1530 = mux(_T_1473, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1531 = mux(_T_1475, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1532 = or(_T_1476, _T_1477) @[Mux.scala 27:72] + node _T_1533 = or(_T_1532, _T_1478) @[Mux.scala 27:72] + node _T_1534 = or(_T_1533, _T_1479) @[Mux.scala 27:72] + node _T_1535 = or(_T_1534, _T_1480) @[Mux.scala 27:72] + node _T_1536 = or(_T_1535, _T_1481) @[Mux.scala 27:72] + node _T_1537 = or(_T_1536, _T_1482) @[Mux.scala 27:72] + node _T_1538 = or(_T_1537, _T_1483) @[Mux.scala 27:72] + node _T_1539 = or(_T_1538, _T_1484) @[Mux.scala 27:72] + node _T_1540 = or(_T_1539, _T_1485) @[Mux.scala 27:72] + node _T_1541 = or(_T_1540, _T_1486) @[Mux.scala 27:72] + node _T_1542 = or(_T_1541, _T_1487) @[Mux.scala 27:72] + node _T_1543 = or(_T_1542, _T_1488) @[Mux.scala 27:72] + node _T_1544 = or(_T_1543, _T_1489) @[Mux.scala 27:72] + node _T_1545 = or(_T_1544, _T_1490) @[Mux.scala 27:72] + node _T_1546 = or(_T_1545, _T_1491) @[Mux.scala 27:72] + node _T_1547 = or(_T_1546, _T_1492) @[Mux.scala 27:72] + node _T_1548 = or(_T_1547, _T_1493) @[Mux.scala 27:72] + node _T_1549 = or(_T_1548, _T_1494) @[Mux.scala 27:72] + node _T_1550 = or(_T_1549, _T_1495) @[Mux.scala 27:72] + node _T_1551 = or(_T_1550, _T_1496) @[Mux.scala 27:72] + node _T_1552 = or(_T_1551, _T_1497) @[Mux.scala 27:72] + node _T_1553 = or(_T_1552, _T_1498) @[Mux.scala 27:72] + node _T_1554 = or(_T_1553, _T_1499) @[Mux.scala 27:72] + node _T_1555 = or(_T_1554, _T_1500) @[Mux.scala 27:72] + node _T_1556 = or(_T_1555, _T_1501) @[Mux.scala 27:72] + node _T_1557 = or(_T_1556, _T_1502) @[Mux.scala 27:72] + node _T_1558 = or(_T_1557, _T_1503) @[Mux.scala 27:72] + node _T_1559 = or(_T_1558, _T_1504) @[Mux.scala 27:72] + node _T_1560 = or(_T_1559, _T_1505) @[Mux.scala 27:72] + node _T_1561 = or(_T_1560, _T_1506) @[Mux.scala 27:72] + node _T_1562 = or(_T_1561, _T_1507) @[Mux.scala 27:72] + node _T_1563 = or(_T_1562, _T_1508) @[Mux.scala 27:72] + node _T_1564 = or(_T_1563, _T_1509) @[Mux.scala 27:72] + node _T_1565 = or(_T_1564, _T_1510) @[Mux.scala 27:72] + node _T_1566 = or(_T_1565, _T_1511) @[Mux.scala 27:72] + node _T_1567 = or(_T_1566, _T_1512) @[Mux.scala 27:72] + node _T_1568 = or(_T_1567, _T_1513) @[Mux.scala 27:72] + node _T_1569 = or(_T_1568, _T_1514) @[Mux.scala 27:72] + node _T_1570 = or(_T_1569, _T_1515) @[Mux.scala 27:72] + node _T_1571 = or(_T_1570, _T_1516) @[Mux.scala 27:72] + node _T_1572 = or(_T_1571, _T_1517) @[Mux.scala 27:72] + node _T_1573 = or(_T_1572, _T_1518) @[Mux.scala 27:72] + node _T_1574 = or(_T_1573, _T_1519) @[Mux.scala 27:72] + node _T_1575 = or(_T_1574, _T_1520) @[Mux.scala 27:72] + node _T_1576 = or(_T_1575, _T_1521) @[Mux.scala 27:72] + node _T_1577 = or(_T_1576, _T_1522) @[Mux.scala 27:72] + node _T_1578 = or(_T_1577, _T_1523) @[Mux.scala 27:72] + node _T_1579 = or(_T_1578, _T_1524) @[Mux.scala 27:72] + node _T_1580 = or(_T_1579, _T_1525) @[Mux.scala 27:72] + node _T_1581 = or(_T_1580, _T_1526) @[Mux.scala 27:72] + node _T_1582 = or(_T_1581, _T_1527) @[Mux.scala 27:72] + node _T_1583 = or(_T_1582, _T_1528) @[Mux.scala 27:72] + node _T_1584 = or(_T_1583, _T_1529) @[Mux.scala 27:72] + node _T_1585 = or(_T_1584, _T_1530) @[Mux.scala 27:72] + node _T_1586 = or(_T_1585, _T_1531) @[Mux.scala 27:72] + wire _T_1587 : UInt<6> @[Mux.scala 27:72] + _T_1587 <= _T_1586 @[Mux.scala 27:72] + node _T_1588 = and(_T_1307, _T_1587) @[el2_dec_tlu_ctl.scala 2351:45] + mhpmc_inc_r[1] <= _T_1588 @[el2_dec_tlu_ctl.scala 2351:20] + node _T_1589 = bits(mcountinhibit, 5, 5) @[el2_dec_tlu_ctl.scala 2351:39] + node _T_1590 = not(_T_1589) @[el2_dec_tlu_ctl.scala 2351:25] + node _T_1591 = eq(mhpme_vec[2], UInt<1>("h01")) @[el2_dec_tlu_ctl.scala 2352:21] + node _T_1592 = bits(_T_1591, 0, 0) @[el2_dec_tlu_ctl.scala 2352:49] + node _T_1593 = eq(mhpme_vec[2], UInt<2>("h02")) @[el2_dec_tlu_ctl.scala 2353:21] + node _T_1594 = bits(_T_1593, 0, 0) @[el2_dec_tlu_ctl.scala 2353:49] + node _T_1595 = eq(mhpme_vec[2], UInt<2>("h03")) @[el2_dec_tlu_ctl.scala 2354:21] + node _T_1596 = bits(_T_1595, 0, 0) @[el2_dec_tlu_ctl.scala 2354:49] + node _T_1597 = eq(mhpme_vec[2], UInt<3>("h04")) @[el2_dec_tlu_ctl.scala 2355:21] + node _T_1598 = bits(_T_1597, 0, 0) @[el2_dec_tlu_ctl.scala 2355:49] + node _T_1599 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2355:83] + node _T_1600 = and(io.tlu_i0_commit_cmt, _T_1599) @[el2_dec_tlu_ctl.scala 2355:81] + node _T_1601 = eq(mhpme_vec[2], UInt<3>("h05")) @[el2_dec_tlu_ctl.scala 2356:21] + node _T_1602 = bits(_T_1601, 0, 0) @[el2_dec_tlu_ctl.scala 2356:49] + node _T_1603 = not(io.exu_pmu_i0_pc4) @[el2_dec_tlu_ctl.scala 2356:83] + node _T_1604 = and(io.tlu_i0_commit_cmt, _T_1603) @[el2_dec_tlu_ctl.scala 2356:81] + node _T_1605 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2356:104] + node _T_1606 = and(_T_1604, _T_1605) @[el2_dec_tlu_ctl.scala 2356:102] + node _T_1607 = eq(mhpme_vec[2], UInt<3>("h06")) @[el2_dec_tlu_ctl.scala 2357:21] + node _T_1608 = bits(_T_1607, 0, 0) @[el2_dec_tlu_ctl.scala 2357:49] + node _T_1609 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[el2_dec_tlu_ctl.scala 2357:81] + node _T_1610 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2357:104] + node _T_1611 = and(_T_1609, _T_1610) @[el2_dec_tlu_ctl.scala 2357:102] + node _T_1612 = eq(mhpme_vec[2], UInt<3>("h07")) @[el2_dec_tlu_ctl.scala 2358:21] + node _T_1613 = bits(_T_1612, 0, 0) @[el2_dec_tlu_ctl.scala 2358:49] + node _T_1614 = eq(mhpme_vec[2], UInt<4>("h08")) @[el2_dec_tlu_ctl.scala 2359:21] + node _T_1615 = bits(_T_1614, 0, 0) @[el2_dec_tlu_ctl.scala 2359:49] + node _T_1616 = eq(mhpme_vec[2], UInt<5>("h01e")) @[el2_dec_tlu_ctl.scala 2360:21] + node _T_1617 = bits(_T_1616, 0, 0) @[el2_dec_tlu_ctl.scala 2360:49] + node _T_1618 = eq(mhpme_vec[2], UInt<4>("h09")) @[el2_dec_tlu_ctl.scala 2361:21] + node _T_1619 = bits(_T_1618, 0, 0) @[el2_dec_tlu_ctl.scala 2361:49] + node _T_1620 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[el2_dec_tlu_ctl.scala 2361:78] + node _T_1621 = eq(mhpme_vec[2], UInt<4>("h0a")) @[el2_dec_tlu_ctl.scala 2362:21] + node _T_1622 = bits(_T_1621, 0, 0) @[el2_dec_tlu_ctl.scala 2362:49] + node _T_1623 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2362:92] + node _T_1624 = eq(mhpme_vec[2], UInt<4>("h0b")) @[el2_dec_tlu_ctl.scala 2363:21] + node _T_1625 = bits(_T_1624, 0, 0) @[el2_dec_tlu_ctl.scala 2363:49] + node _T_1626 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[el2_dec_tlu_ctl.scala 2363:78] + node _T_1627 = eq(mhpme_vec[2], UInt<4>("h0c")) @[el2_dec_tlu_ctl.scala 2364:21] + node _T_1628 = bits(_T_1627, 0, 0) @[el2_dec_tlu_ctl.scala 2364:49] + node _T_1629 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[el2_dec_tlu_ctl.scala 2364:78] + node _T_1630 = eq(mhpme_vec[2], UInt<4>("h0d")) @[el2_dec_tlu_ctl.scala 2365:21] + node _T_1631 = bits(_T_1630, 0, 0) @[el2_dec_tlu_ctl.scala 2365:49] + node _T_1632 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[el2_dec_tlu_ctl.scala 2365:79] + node _T_1633 = eq(mhpme_vec[2], UInt<4>("h0e")) @[el2_dec_tlu_ctl.scala 2366:21] + node _T_1634 = dshr(io.dec_tlu_packet_r.pmu_lsu_misaligned, _T_1633) @[el2_dec_tlu_ctl.scala 2366:7] + node _T_1635 = bits(_T_1634, 0, 0) @[el2_dec_tlu_ctl.scala 2366:7] + node _T_1636 = and(_T_1632, _T_1635) @[el2_dec_tlu_ctl.scala 2365:89] + node _T_1637 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[el2_dec_tlu_ctl.scala 2366:66] + node _T_1638 = and(_T_1636, _T_1637) @[el2_dec_tlu_ctl.scala 2366:45] + node _T_1639 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[el2_dec_tlu_ctl.scala 2367:48] + node _T_1640 = and(_T_1638, _T_1639) @[el2_dec_tlu_ctl.scala 2366:77] + node _T_1641 = eq(mhpme_vec[2], UInt<4>("h0f")) @[el2_dec_tlu_ctl.scala 2368:21] + node _T_1642 = bits(_T_1641, 0, 0) @[el2_dec_tlu_ctl.scala 2368:41] + node _T_1643 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[el2_dec_tlu_ctl.scala 2368:76] + node _T_1644 = eq(mhpme_vec[2], UInt<5>("h010")) @[el2_dec_tlu_ctl.scala 2369:21] + node _T_1645 = bits(_T_1644, 0, 0) @[el2_dec_tlu_ctl.scala 2369:46] + node _T_1646 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[el2_dec_tlu_ctl.scala 2369:76] + node _T_1647 = eq(mhpme_vec[2], UInt<5>("h012")) @[el2_dec_tlu_ctl.scala 2370:21] + node _T_1648 = bits(_T_1647, 0, 0) @[el2_dec_tlu_ctl.scala 2370:46] + node _T_1649 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[el2_dec_tlu_ctl.scala 2370:76] + node _T_1650 = eq(mhpme_vec[2], UInt<5>("h011")) @[el2_dec_tlu_ctl.scala 2371:21] + node _T_1651 = bits(_T_1650, 0, 0) @[el2_dec_tlu_ctl.scala 2371:46] + node _T_1652 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[el2_dec_tlu_ctl.scala 2371:76] + node _T_1653 = eq(mhpme_vec[2], UInt<5>("h013")) @[el2_dec_tlu_ctl.scala 2372:21] + node _T_1654 = bits(_T_1653, 0, 0) @[el2_dec_tlu_ctl.scala 2372:46] + node _T_1655 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[el2_dec_tlu_ctl.scala 2372:76] + node _T_1656 = eq(mhpme_vec[2], UInt<5>("h014")) @[el2_dec_tlu_ctl.scala 2373:21] + node _T_1657 = bits(_T_1656, 0, 0) @[el2_dec_tlu_ctl.scala 2373:46] + node _T_1658 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[el2_dec_tlu_ctl.scala 2373:76] + node _T_1659 = eq(mhpme_vec[2], UInt<5>("h015")) @[el2_dec_tlu_ctl.scala 2374:21] + node _T_1660 = bits(_T_1659, 0, 0) @[el2_dec_tlu_ctl.scala 2374:46] + node _T_1661 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[el2_dec_tlu_ctl.scala 2374:76] + node _T_1662 = eq(mhpme_vec[2], UInt<5>("h016")) @[el2_dec_tlu_ctl.scala 2375:21] + node _T_1663 = bits(_T_1662, 0, 0) @[el2_dec_tlu_ctl.scala 2375:46] + node _T_1664 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[el2_dec_tlu_ctl.scala 2375:76] + node _T_1665 = eq(mhpme_vec[2], UInt<5>("h017")) @[el2_dec_tlu_ctl.scala 2376:21] + node _T_1666 = bits(_T_1665, 0, 0) @[el2_dec_tlu_ctl.scala 2376:46] + node _T_1667 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[el2_dec_tlu_ctl.scala 2376:76] + node _T_1668 = eq(mhpme_vec[2], UInt<5>("h018")) @[el2_dec_tlu_ctl.scala 2377:21] + node _T_1669 = bits(_T_1668, 0, 0) @[el2_dec_tlu_ctl.scala 2377:46] + node _T_1670 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[el2_dec_tlu_ctl.scala 2377:76] + node _T_1671 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[el2_dec_tlu_ctl.scala 2377:109] + node _T_1672 = or(_T_1670, _T_1671) @[el2_dec_tlu_ctl.scala 2377:88] + node _T_1673 = eq(mhpme_vec[2], UInt<5>("h019")) @[el2_dec_tlu_ctl.scala 2378:21] + node _T_1674 = bits(_T_1673, 0, 0) @[el2_dec_tlu_ctl.scala 2378:49] + node _T_1675 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2378:82] + node _T_1676 = eq(mhpme_vec[2], UInt<5>("h01a")) @[el2_dec_tlu_ctl.scala 2379:21] + node _T_1677 = bits(_T_1676, 0, 0) @[el2_dec_tlu_ctl.scala 2379:49] + node _T_1678 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2379:84] + node _T_1679 = eq(mhpme_vec[2], UInt<5>("h01b")) @[el2_dec_tlu_ctl.scala 2380:21] + node _T_1680 = bits(_T_1679, 0, 0) @[el2_dec_tlu_ctl.scala 2380:49] + node _T_1681 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2380:97] + node _T_1682 = eq(mhpme_vec[2], UInt<5>("h01c")) @[el2_dec_tlu_ctl.scala 2381:21] + node _T_1683 = bits(_T_1682, 0, 0) @[el2_dec_tlu_ctl.scala 2381:49] + node _T_1684 = eq(mhpme_vec[2], UInt<5>("h01e")) @[el2_dec_tlu_ctl.scala 2382:21] + node _T_1685 = bits(_T_1684, 0, 0) @[el2_dec_tlu_ctl.scala 2382:49] + node _T_1686 = eq(mhpme_vec[2], UInt<5>("h01f")) @[el2_dec_tlu_ctl.scala 2383:21] + node _T_1687 = bits(_T_1686, 0, 0) @[el2_dec_tlu_ctl.scala 2383:49] + node _T_1688 = eq(mhpme_vec[2], UInt<6>("h020")) @[el2_dec_tlu_ctl.scala 2384:21] + node _T_1689 = bits(_T_1688, 0, 0) @[el2_dec_tlu_ctl.scala 2384:49] + node _T_1690 = eq(mhpme_vec[2], UInt<6>("h022")) @[el2_dec_tlu_ctl.scala 2385:21] + node _T_1691 = bits(_T_1690, 0, 0) @[el2_dec_tlu_ctl.scala 2385:49] + node _T_1692 = eq(mhpme_vec[2], UInt<6>("h023")) @[el2_dec_tlu_ctl.scala 2386:21] + node _T_1693 = bits(_T_1692, 0, 0) @[el2_dec_tlu_ctl.scala 2386:49] + node _T_1694 = eq(mhpme_vec[2], UInt<6>("h024")) @[el2_dec_tlu_ctl.scala 2387:21] + node _T_1695 = bits(_T_1694, 0, 0) @[el2_dec_tlu_ctl.scala 2387:49] + node _T_1696 = eq(mhpme_vec[2], UInt<6>("h025")) @[el2_dec_tlu_ctl.scala 2388:21] + node _T_1697 = bits(_T_1696, 0, 0) @[el2_dec_tlu_ctl.scala 2388:49] + node _T_1698 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 2388:85] + node _T_1699 = or(_T_1698, io.lsu_exc_valid_r) @[el2_dec_tlu_ctl.scala 2388:107] + node _T_1700 = eq(mhpme_vec[2], UInt<6>("h026")) @[el2_dec_tlu_ctl.scala 2389:21] + node _T_1701 = bits(_T_1700, 0, 0) @[el2_dec_tlu_ctl.scala 2389:49] + node _T_1702 = or(io.take_timer_int, io.take_int_timer0_int) @[el2_dec_tlu_ctl.scala 2389:79] + node _T_1703 = or(_T_1702, io.take_int_timer1_int) @[el2_dec_tlu_ctl.scala 2389:104] + node _T_1704 = eq(mhpme_vec[2], UInt<6>("h027")) @[el2_dec_tlu_ctl.scala 2390:21] + node _T_1705 = bits(_T_1704, 0, 0) @[el2_dec_tlu_ctl.scala 2390:49] + node _T_1706 = eq(mhpme_vec[2], UInt<6>("h028")) @[el2_dec_tlu_ctl.scala 2391:21] + node _T_1707 = bits(_T_1706, 0, 0) @[el2_dec_tlu_ctl.scala 2391:49] + node _T_1708 = eq(mhpme_vec[2], UInt<6>("h029")) @[el2_dec_tlu_ctl.scala 2392:21] + node _T_1709 = bits(_T_1708, 0, 0) @[el2_dec_tlu_ctl.scala 2392:49] + node _T_1710 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[el2_dec_tlu_ctl.scala 2392:84] + node _T_1711 = and(_T_1710, io.rfpc_i0_r) @[el2_dec_tlu_ctl.scala 2392:116] + node _T_1712 = eq(mhpme_vec[2], UInt<6>("h02a")) @[el2_dec_tlu_ctl.scala 2393:21] + node _T_1713 = bits(_T_1712, 0, 0) @[el2_dec_tlu_ctl.scala 2393:49] + node _T_1714 = eq(mhpme_vec[2], UInt<6>("h02b")) @[el2_dec_tlu_ctl.scala 2394:21] + node _T_1715 = bits(_T_1714, 0, 0) @[el2_dec_tlu_ctl.scala 2394:49] + node _T_1716 = eq(mhpme_vec[2], UInt<6>("h02c")) @[el2_dec_tlu_ctl.scala 2395:21] + node _T_1717 = bits(_T_1716, 0, 0) @[el2_dec_tlu_ctl.scala 2395:49] + node _T_1718 = eq(mhpme_vec[2], UInt<6>("h02d")) @[el2_dec_tlu_ctl.scala 2396:21] + node _T_1719 = bits(_T_1718, 0, 0) @[el2_dec_tlu_ctl.scala 2396:49] + node _T_1720 = eq(mhpme_vec[2], UInt<6>("h02e")) @[el2_dec_tlu_ctl.scala 2397:21] + node _T_1721 = bits(_T_1720, 0, 0) @[el2_dec_tlu_ctl.scala 2397:49] + node _T_1722 = eq(mhpme_vec[2], UInt<6>("h02f")) @[el2_dec_tlu_ctl.scala 2398:21] + node _T_1723 = bits(_T_1722, 0, 0) @[el2_dec_tlu_ctl.scala 2398:49] + node _T_1724 = eq(mhpme_vec[2], UInt<6>("h030")) @[el2_dec_tlu_ctl.scala 2399:21] + node _T_1725 = bits(_T_1724, 0, 0) @[el2_dec_tlu_ctl.scala 2399:49] + node _T_1726 = eq(mhpme_vec[2], UInt<6>("h031")) @[el2_dec_tlu_ctl.scala 2400:21] + node _T_1727 = bits(_T_1726, 0, 0) @[el2_dec_tlu_ctl.scala 2400:49] + node _T_1728 = dshr(io.mstatus, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2400:71] + node _T_1729 = bits(_T_1728, 0, 0) @[el2_dec_tlu_ctl.scala 2400:71] + node _T_1730 = not(_T_1729) @[el2_dec_tlu_ctl.scala 2400:60] + node _T_1731 = eq(mhpme_vec[2], UInt<6>("h032")) @[el2_dec_tlu_ctl.scala 2401:21] + node _T_1732 = bits(_T_1731, 0, 0) @[el2_dec_tlu_ctl.scala 2401:49] + node _T_1733 = dshr(io.mstatus, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2401:71] + node _T_1734 = bits(_T_1733, 0, 0) @[el2_dec_tlu_ctl.scala 2401:71] + node _T_1735 = not(_T_1734) @[el2_dec_tlu_ctl.scala 2401:60] + node _T_1736 = bits(io.mip, 5, 0) @[el2_dec_tlu_ctl.scala 2401:94] + node _T_1737 = bits(mie, 5, 0) @[el2_dec_tlu_ctl.scala 2401:105] + node _T_1738 = and(_T_1736, _T_1737) @[el2_dec_tlu_ctl.scala 2401:100] + node _T_1739 = and(_T_1735, _T_1738) @[el2_dec_tlu_ctl.scala 2401:85] + node _T_1740 = eq(mhpme_vec[2], UInt<6>("h036")) @[el2_dec_tlu_ctl.scala 2402:21] + node _T_1741 = bits(_T_1740, 0, 0) @[el2_dec_tlu_ctl.scala 2402:49] + node _T_1742 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[el2_dec_tlu_ctl.scala 2402:78] + node _T_1743 = eq(mhpme_vec[2], UInt<6>("h037")) @[el2_dec_tlu_ctl.scala 2403:21] + node _T_1744 = bits(_T_1743, 0, 0) @[el2_dec_tlu_ctl.scala 2403:49] + node _T_1745 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[el2_dec_tlu_ctl.scala 2403:81] + node _T_1746 = eq(mhpme_vec[2], UInt<6>("h038")) @[el2_dec_tlu_ctl.scala 2404:21] + node _T_1747 = bits(_T_1746, 0, 0) @[el2_dec_tlu_ctl.scala 2404:49] + node _T_1748 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[el2_dec_tlu_ctl.scala 2404:81] + node _T_1749 = eq(mhpme_vec[2], UInt<10>("h0200")) @[el2_dec_tlu_ctl.scala 2406:21] + node _T_1750 = bits(_T_1749, 0, 0) @[el2_dec_tlu_ctl.scala 2406:49] + node _T_1751 = eq(mhpme_vec[2], UInt<10>("h0201")) @[el2_dec_tlu_ctl.scala 2407:21] + node _T_1752 = bits(_T_1751, 0, 0) @[el2_dec_tlu_ctl.scala 2407:49] + node _T_1753 = eq(mhpme_vec[2], UInt<10>("h0202")) @[el2_dec_tlu_ctl.scala 2408:21] + node _T_1754 = bits(_T_1753, 0, 0) @[el2_dec_tlu_ctl.scala 2408:49] + node _T_1755 = eq(mhpme_vec[2], UInt<10>("h0203")) @[el2_dec_tlu_ctl.scala 2409:21] + node _T_1756 = bits(_T_1755, 0, 0) @[el2_dec_tlu_ctl.scala 2409:49] + node _T_1757 = eq(mhpme_vec[2], UInt<10>("h0204")) @[el2_dec_tlu_ctl.scala 2410:21] + node _T_1758 = bits(_T_1757, 0, 0) @[el2_dec_tlu_ctl.scala 2410:49] + node _T_1759 = mux(_T_1592, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1760 = mux(_T_1594, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1761 = mux(_T_1596, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1762 = mux(_T_1598, _T_1600, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1763 = mux(_T_1602, _T_1606, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1764 = mux(_T_1608, _T_1611, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1765 = mux(_T_1613, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1766 = mux(_T_1615, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1767 = mux(_T_1617, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1768 = mux(_T_1619, _T_1620, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1769 = mux(_T_1622, _T_1623, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1770 = mux(_T_1625, _T_1626, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1771 = mux(_T_1628, _T_1629, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1772 = mux(_T_1631, _T_1640, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1773 = mux(_T_1642, _T_1643, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1774 = mux(_T_1645, _T_1646, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1775 = mux(_T_1648, _T_1649, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1776 = mux(_T_1651, _T_1652, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1777 = mux(_T_1654, _T_1655, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1778 = mux(_T_1657, _T_1658, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1779 = mux(_T_1660, _T_1661, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1780 = mux(_T_1663, _T_1664, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1781 = mux(_T_1666, _T_1667, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1782 = mux(_T_1669, _T_1672, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1783 = mux(_T_1674, _T_1675, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1784 = mux(_T_1677, _T_1678, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1785 = mux(_T_1680, _T_1681, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1786 = mux(_T_1683, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1787 = mux(_T_1685, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1788 = mux(_T_1687, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1789 = mux(_T_1689, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1790 = mux(_T_1691, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1791 = mux(_T_1693, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1792 = mux(_T_1695, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1793 = mux(_T_1697, _T_1699, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1794 = mux(_T_1701, _T_1703, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1795 = mux(_T_1705, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1796 = mux(_T_1707, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1797 = mux(_T_1709, _T_1711, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1798 = mux(_T_1713, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1799 = mux(_T_1715, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1800 = mux(_T_1717, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1801 = mux(_T_1719, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1802 = mux(_T_1721, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1803 = mux(_T_1723, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1804 = mux(_T_1725, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1805 = mux(_T_1727, _T_1730, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1806 = mux(_T_1732, _T_1739, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1807 = mux(_T_1741, _T_1742, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1808 = mux(_T_1744, _T_1745, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1809 = mux(_T_1747, _T_1748, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1810 = mux(_T_1750, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1811 = mux(_T_1752, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1812 = mux(_T_1754, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1813 = mux(_T_1756, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1814 = mux(_T_1758, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1815 = or(_T_1759, _T_1760) @[Mux.scala 27:72] + node _T_1816 = or(_T_1815, _T_1761) @[Mux.scala 27:72] + node _T_1817 = or(_T_1816, _T_1762) @[Mux.scala 27:72] + node _T_1818 = or(_T_1817, _T_1763) @[Mux.scala 27:72] + node _T_1819 = or(_T_1818, _T_1764) @[Mux.scala 27:72] + node _T_1820 = or(_T_1819, _T_1765) @[Mux.scala 27:72] + node _T_1821 = or(_T_1820, _T_1766) @[Mux.scala 27:72] + node _T_1822 = or(_T_1821, _T_1767) @[Mux.scala 27:72] + node _T_1823 = or(_T_1822, _T_1768) @[Mux.scala 27:72] + node _T_1824 = or(_T_1823, _T_1769) @[Mux.scala 27:72] + node _T_1825 = or(_T_1824, _T_1770) @[Mux.scala 27:72] + node _T_1826 = or(_T_1825, _T_1771) @[Mux.scala 27:72] + node _T_1827 = or(_T_1826, _T_1772) @[Mux.scala 27:72] + node _T_1828 = or(_T_1827, _T_1773) @[Mux.scala 27:72] + node _T_1829 = or(_T_1828, _T_1774) @[Mux.scala 27:72] + node _T_1830 = or(_T_1829, _T_1775) @[Mux.scala 27:72] + node _T_1831 = or(_T_1830, _T_1776) @[Mux.scala 27:72] + node _T_1832 = or(_T_1831, _T_1777) @[Mux.scala 27:72] + node _T_1833 = or(_T_1832, _T_1778) @[Mux.scala 27:72] + node _T_1834 = or(_T_1833, _T_1779) @[Mux.scala 27:72] + node _T_1835 = or(_T_1834, _T_1780) @[Mux.scala 27:72] + node _T_1836 = or(_T_1835, _T_1781) @[Mux.scala 27:72] + node _T_1837 = or(_T_1836, _T_1782) @[Mux.scala 27:72] + node _T_1838 = or(_T_1837, _T_1783) @[Mux.scala 27:72] + node _T_1839 = or(_T_1838, _T_1784) @[Mux.scala 27:72] + node _T_1840 = or(_T_1839, _T_1785) @[Mux.scala 27:72] + node _T_1841 = or(_T_1840, _T_1786) @[Mux.scala 27:72] + node _T_1842 = or(_T_1841, _T_1787) @[Mux.scala 27:72] + node _T_1843 = or(_T_1842, _T_1788) @[Mux.scala 27:72] + node _T_1844 = or(_T_1843, _T_1789) @[Mux.scala 27:72] + node _T_1845 = or(_T_1844, _T_1790) @[Mux.scala 27:72] + node _T_1846 = or(_T_1845, _T_1791) @[Mux.scala 27:72] + node _T_1847 = or(_T_1846, _T_1792) @[Mux.scala 27:72] + node _T_1848 = or(_T_1847, _T_1793) @[Mux.scala 27:72] + node _T_1849 = or(_T_1848, _T_1794) @[Mux.scala 27:72] + node _T_1850 = or(_T_1849, _T_1795) @[Mux.scala 27:72] + node _T_1851 = or(_T_1850, _T_1796) @[Mux.scala 27:72] + node _T_1852 = or(_T_1851, _T_1797) @[Mux.scala 27:72] + node _T_1853 = or(_T_1852, _T_1798) @[Mux.scala 27:72] + node _T_1854 = or(_T_1853, _T_1799) @[Mux.scala 27:72] + node _T_1855 = or(_T_1854, _T_1800) @[Mux.scala 27:72] + node _T_1856 = or(_T_1855, _T_1801) @[Mux.scala 27:72] + node _T_1857 = or(_T_1856, _T_1802) @[Mux.scala 27:72] + node _T_1858 = or(_T_1857, _T_1803) @[Mux.scala 27:72] + node _T_1859 = or(_T_1858, _T_1804) @[Mux.scala 27:72] + node _T_1860 = or(_T_1859, _T_1805) @[Mux.scala 27:72] + node _T_1861 = or(_T_1860, _T_1806) @[Mux.scala 27:72] + node _T_1862 = or(_T_1861, _T_1807) @[Mux.scala 27:72] + node _T_1863 = or(_T_1862, _T_1808) @[Mux.scala 27:72] + node _T_1864 = or(_T_1863, _T_1809) @[Mux.scala 27:72] + node _T_1865 = or(_T_1864, _T_1810) @[Mux.scala 27:72] + node _T_1866 = or(_T_1865, _T_1811) @[Mux.scala 27:72] + node _T_1867 = or(_T_1866, _T_1812) @[Mux.scala 27:72] + node _T_1868 = or(_T_1867, _T_1813) @[Mux.scala 27:72] + node _T_1869 = or(_T_1868, _T_1814) @[Mux.scala 27:72] + wire _T_1870 : UInt<6> @[Mux.scala 27:72] + _T_1870 <= _T_1869 @[Mux.scala 27:72] + node _T_1871 = and(_T_1590, _T_1870) @[el2_dec_tlu_ctl.scala 2351:45] + mhpmc_inc_r[2] <= _T_1871 @[el2_dec_tlu_ctl.scala 2351:20] + node _T_1872 = bits(mcountinhibit, 6, 6) @[el2_dec_tlu_ctl.scala 2351:39] + node _T_1873 = not(_T_1872) @[el2_dec_tlu_ctl.scala 2351:25] + node _T_1874 = eq(mhpme_vec[3], UInt<1>("h01")) @[el2_dec_tlu_ctl.scala 2352:21] + node _T_1875 = bits(_T_1874, 0, 0) @[el2_dec_tlu_ctl.scala 2352:49] + node _T_1876 = eq(mhpme_vec[3], UInt<2>("h02")) @[el2_dec_tlu_ctl.scala 2353:21] + node _T_1877 = bits(_T_1876, 0, 0) @[el2_dec_tlu_ctl.scala 2353:49] + node _T_1878 = eq(mhpme_vec[3], UInt<2>("h03")) @[el2_dec_tlu_ctl.scala 2354:21] + node _T_1879 = bits(_T_1878, 0, 0) @[el2_dec_tlu_ctl.scala 2354:49] + node _T_1880 = eq(mhpme_vec[3], UInt<3>("h04")) @[el2_dec_tlu_ctl.scala 2355:21] + node _T_1881 = bits(_T_1880, 0, 0) @[el2_dec_tlu_ctl.scala 2355:49] + node _T_1882 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2355:83] + node _T_1883 = and(io.tlu_i0_commit_cmt, _T_1882) @[el2_dec_tlu_ctl.scala 2355:81] + node _T_1884 = eq(mhpme_vec[3], UInt<3>("h05")) @[el2_dec_tlu_ctl.scala 2356:21] + node _T_1885 = bits(_T_1884, 0, 0) @[el2_dec_tlu_ctl.scala 2356:49] + node _T_1886 = not(io.exu_pmu_i0_pc4) @[el2_dec_tlu_ctl.scala 2356:83] + node _T_1887 = and(io.tlu_i0_commit_cmt, _T_1886) @[el2_dec_tlu_ctl.scala 2356:81] + node _T_1888 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2356:104] + node _T_1889 = and(_T_1887, _T_1888) @[el2_dec_tlu_ctl.scala 2356:102] + node _T_1890 = eq(mhpme_vec[3], UInt<3>("h06")) @[el2_dec_tlu_ctl.scala 2357:21] + node _T_1891 = bits(_T_1890, 0, 0) @[el2_dec_tlu_ctl.scala 2357:49] + node _T_1892 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[el2_dec_tlu_ctl.scala 2357:81] + node _T_1893 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2357:104] + node _T_1894 = and(_T_1892, _T_1893) @[el2_dec_tlu_ctl.scala 2357:102] + node _T_1895 = eq(mhpme_vec[3], UInt<3>("h07")) @[el2_dec_tlu_ctl.scala 2358:21] + node _T_1896 = bits(_T_1895, 0, 0) @[el2_dec_tlu_ctl.scala 2358:49] + node _T_1897 = eq(mhpme_vec[3], UInt<4>("h08")) @[el2_dec_tlu_ctl.scala 2359:21] + node _T_1898 = bits(_T_1897, 0, 0) @[el2_dec_tlu_ctl.scala 2359:49] + node _T_1899 = eq(mhpme_vec[3], UInt<5>("h01e")) @[el2_dec_tlu_ctl.scala 2360:21] + node _T_1900 = bits(_T_1899, 0, 0) @[el2_dec_tlu_ctl.scala 2360:49] + node _T_1901 = eq(mhpme_vec[3], UInt<4>("h09")) @[el2_dec_tlu_ctl.scala 2361:21] + node _T_1902 = bits(_T_1901, 0, 0) @[el2_dec_tlu_ctl.scala 2361:49] + node _T_1903 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[el2_dec_tlu_ctl.scala 2361:78] + node _T_1904 = eq(mhpme_vec[3], UInt<4>("h0a")) @[el2_dec_tlu_ctl.scala 2362:21] + node _T_1905 = bits(_T_1904, 0, 0) @[el2_dec_tlu_ctl.scala 2362:49] + node _T_1906 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2362:92] + node _T_1907 = eq(mhpme_vec[3], UInt<4>("h0b")) @[el2_dec_tlu_ctl.scala 2363:21] + node _T_1908 = bits(_T_1907, 0, 0) @[el2_dec_tlu_ctl.scala 2363:49] + node _T_1909 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[el2_dec_tlu_ctl.scala 2363:78] + node _T_1910 = eq(mhpme_vec[3], UInt<4>("h0c")) @[el2_dec_tlu_ctl.scala 2364:21] + node _T_1911 = bits(_T_1910, 0, 0) @[el2_dec_tlu_ctl.scala 2364:49] + node _T_1912 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[el2_dec_tlu_ctl.scala 2364:78] + node _T_1913 = eq(mhpme_vec[3], UInt<4>("h0d")) @[el2_dec_tlu_ctl.scala 2365:21] + node _T_1914 = bits(_T_1913, 0, 0) @[el2_dec_tlu_ctl.scala 2365:49] + node _T_1915 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[el2_dec_tlu_ctl.scala 2365:79] + node _T_1916 = eq(mhpme_vec[3], UInt<4>("h0e")) @[el2_dec_tlu_ctl.scala 2366:21] + node _T_1917 = dshr(io.dec_tlu_packet_r.pmu_lsu_misaligned, _T_1916) @[el2_dec_tlu_ctl.scala 2366:7] + node _T_1918 = bits(_T_1917, 0, 0) @[el2_dec_tlu_ctl.scala 2366:7] + node _T_1919 = and(_T_1915, _T_1918) @[el2_dec_tlu_ctl.scala 2365:89] + node _T_1920 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[el2_dec_tlu_ctl.scala 2366:66] + node _T_1921 = and(_T_1919, _T_1920) @[el2_dec_tlu_ctl.scala 2366:45] + node _T_1922 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[el2_dec_tlu_ctl.scala 2367:48] + node _T_1923 = and(_T_1921, _T_1922) @[el2_dec_tlu_ctl.scala 2366:77] + node _T_1924 = eq(mhpme_vec[3], UInt<4>("h0f")) @[el2_dec_tlu_ctl.scala 2368:21] + node _T_1925 = bits(_T_1924, 0, 0) @[el2_dec_tlu_ctl.scala 2368:41] + node _T_1926 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[el2_dec_tlu_ctl.scala 2368:76] + node _T_1927 = eq(mhpme_vec[3], UInt<5>("h010")) @[el2_dec_tlu_ctl.scala 2369:21] + node _T_1928 = bits(_T_1927, 0, 0) @[el2_dec_tlu_ctl.scala 2369:46] + node _T_1929 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[el2_dec_tlu_ctl.scala 2369:76] + node _T_1930 = eq(mhpme_vec[3], UInt<5>("h012")) @[el2_dec_tlu_ctl.scala 2370:21] + node _T_1931 = bits(_T_1930, 0, 0) @[el2_dec_tlu_ctl.scala 2370:46] + node _T_1932 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[el2_dec_tlu_ctl.scala 2370:76] + node _T_1933 = eq(mhpme_vec[3], UInt<5>("h011")) @[el2_dec_tlu_ctl.scala 2371:21] + node _T_1934 = bits(_T_1933, 0, 0) @[el2_dec_tlu_ctl.scala 2371:46] + node _T_1935 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[el2_dec_tlu_ctl.scala 2371:76] + node _T_1936 = eq(mhpme_vec[3], UInt<5>("h013")) @[el2_dec_tlu_ctl.scala 2372:21] + node _T_1937 = bits(_T_1936, 0, 0) @[el2_dec_tlu_ctl.scala 2372:46] + node _T_1938 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[el2_dec_tlu_ctl.scala 2372:76] + node _T_1939 = eq(mhpme_vec[3], UInt<5>("h014")) @[el2_dec_tlu_ctl.scala 2373:21] + node _T_1940 = bits(_T_1939, 0, 0) @[el2_dec_tlu_ctl.scala 2373:46] + node _T_1941 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[el2_dec_tlu_ctl.scala 2373:76] + node _T_1942 = eq(mhpme_vec[3], UInt<5>("h015")) @[el2_dec_tlu_ctl.scala 2374:21] + node _T_1943 = bits(_T_1942, 0, 0) @[el2_dec_tlu_ctl.scala 2374:46] + node _T_1944 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[el2_dec_tlu_ctl.scala 2374:76] + node _T_1945 = eq(mhpme_vec[3], UInt<5>("h016")) @[el2_dec_tlu_ctl.scala 2375:21] + node _T_1946 = bits(_T_1945, 0, 0) @[el2_dec_tlu_ctl.scala 2375:46] + node _T_1947 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[el2_dec_tlu_ctl.scala 2375:76] + node _T_1948 = eq(mhpme_vec[3], UInt<5>("h017")) @[el2_dec_tlu_ctl.scala 2376:21] + node _T_1949 = bits(_T_1948, 0, 0) @[el2_dec_tlu_ctl.scala 2376:46] + node _T_1950 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[el2_dec_tlu_ctl.scala 2376:76] + node _T_1951 = eq(mhpme_vec[3], UInt<5>("h018")) @[el2_dec_tlu_ctl.scala 2377:21] + node _T_1952 = bits(_T_1951, 0, 0) @[el2_dec_tlu_ctl.scala 2377:46] + node _T_1953 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[el2_dec_tlu_ctl.scala 2377:76] + node _T_1954 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[el2_dec_tlu_ctl.scala 2377:109] + node _T_1955 = or(_T_1953, _T_1954) @[el2_dec_tlu_ctl.scala 2377:88] + node _T_1956 = eq(mhpme_vec[3], UInt<5>("h019")) @[el2_dec_tlu_ctl.scala 2378:21] + node _T_1957 = bits(_T_1956, 0, 0) @[el2_dec_tlu_ctl.scala 2378:49] + node _T_1958 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2378:82] + node _T_1959 = eq(mhpme_vec[3], UInt<5>("h01a")) @[el2_dec_tlu_ctl.scala 2379:21] + node _T_1960 = bits(_T_1959, 0, 0) @[el2_dec_tlu_ctl.scala 2379:49] + node _T_1961 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2379:84] + node _T_1962 = eq(mhpme_vec[3], UInt<5>("h01b")) @[el2_dec_tlu_ctl.scala 2380:21] + node _T_1963 = bits(_T_1962, 0, 0) @[el2_dec_tlu_ctl.scala 2380:49] + node _T_1964 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2380:97] + node _T_1965 = eq(mhpme_vec[3], UInt<5>("h01c")) @[el2_dec_tlu_ctl.scala 2381:21] + node _T_1966 = bits(_T_1965, 0, 0) @[el2_dec_tlu_ctl.scala 2381:49] + node _T_1967 = eq(mhpme_vec[3], UInt<5>("h01e")) @[el2_dec_tlu_ctl.scala 2382:21] + node _T_1968 = bits(_T_1967, 0, 0) @[el2_dec_tlu_ctl.scala 2382:49] + node _T_1969 = eq(mhpme_vec[3], UInt<5>("h01f")) @[el2_dec_tlu_ctl.scala 2383:21] + node _T_1970 = bits(_T_1969, 0, 0) @[el2_dec_tlu_ctl.scala 2383:49] + node _T_1971 = eq(mhpme_vec[3], UInt<6>("h020")) @[el2_dec_tlu_ctl.scala 2384:21] + node _T_1972 = bits(_T_1971, 0, 0) @[el2_dec_tlu_ctl.scala 2384:49] + node _T_1973 = eq(mhpme_vec[3], UInt<6>("h022")) @[el2_dec_tlu_ctl.scala 2385:21] + node _T_1974 = bits(_T_1973, 0, 0) @[el2_dec_tlu_ctl.scala 2385:49] + node _T_1975 = eq(mhpme_vec[3], UInt<6>("h023")) @[el2_dec_tlu_ctl.scala 2386:21] + node _T_1976 = bits(_T_1975, 0, 0) @[el2_dec_tlu_ctl.scala 2386:49] + node _T_1977 = eq(mhpme_vec[3], UInt<6>("h024")) @[el2_dec_tlu_ctl.scala 2387:21] + node _T_1978 = bits(_T_1977, 0, 0) @[el2_dec_tlu_ctl.scala 2387:49] + node _T_1979 = eq(mhpme_vec[3], UInt<6>("h025")) @[el2_dec_tlu_ctl.scala 2388:21] + node _T_1980 = bits(_T_1979, 0, 0) @[el2_dec_tlu_ctl.scala 2388:49] + node _T_1981 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 2388:85] + node _T_1982 = or(_T_1981, io.lsu_exc_valid_r) @[el2_dec_tlu_ctl.scala 2388:107] + node _T_1983 = eq(mhpme_vec[3], UInt<6>("h026")) @[el2_dec_tlu_ctl.scala 2389:21] + node _T_1984 = bits(_T_1983, 0, 0) @[el2_dec_tlu_ctl.scala 2389:49] + node _T_1985 = or(io.take_timer_int, io.take_int_timer0_int) @[el2_dec_tlu_ctl.scala 2389:79] + node _T_1986 = or(_T_1985, io.take_int_timer1_int) @[el2_dec_tlu_ctl.scala 2389:104] + node _T_1987 = eq(mhpme_vec[3], UInt<6>("h027")) @[el2_dec_tlu_ctl.scala 2390:21] + node _T_1988 = bits(_T_1987, 0, 0) @[el2_dec_tlu_ctl.scala 2390:49] + node _T_1989 = eq(mhpme_vec[3], UInt<6>("h028")) @[el2_dec_tlu_ctl.scala 2391:21] + node _T_1990 = bits(_T_1989, 0, 0) @[el2_dec_tlu_ctl.scala 2391:49] + node _T_1991 = eq(mhpme_vec[3], UInt<6>("h029")) @[el2_dec_tlu_ctl.scala 2392:21] + node _T_1992 = bits(_T_1991, 0, 0) @[el2_dec_tlu_ctl.scala 2392:49] + node _T_1993 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[el2_dec_tlu_ctl.scala 2392:84] + node _T_1994 = and(_T_1993, io.rfpc_i0_r) @[el2_dec_tlu_ctl.scala 2392:116] + node _T_1995 = eq(mhpme_vec[3], UInt<6>("h02a")) @[el2_dec_tlu_ctl.scala 2393:21] + node _T_1996 = bits(_T_1995, 0, 0) @[el2_dec_tlu_ctl.scala 2393:49] + node _T_1997 = eq(mhpme_vec[3], UInt<6>("h02b")) @[el2_dec_tlu_ctl.scala 2394:21] + node _T_1998 = bits(_T_1997, 0, 0) @[el2_dec_tlu_ctl.scala 2394:49] + node _T_1999 = eq(mhpme_vec[3], UInt<6>("h02c")) @[el2_dec_tlu_ctl.scala 2395:21] + node _T_2000 = bits(_T_1999, 0, 0) @[el2_dec_tlu_ctl.scala 2395:49] + node _T_2001 = eq(mhpme_vec[3], UInt<6>("h02d")) @[el2_dec_tlu_ctl.scala 2396:21] + node _T_2002 = bits(_T_2001, 0, 0) @[el2_dec_tlu_ctl.scala 2396:49] + node _T_2003 = eq(mhpme_vec[3], UInt<6>("h02e")) @[el2_dec_tlu_ctl.scala 2397:21] + node _T_2004 = bits(_T_2003, 0, 0) @[el2_dec_tlu_ctl.scala 2397:49] + node _T_2005 = eq(mhpme_vec[3], UInt<6>("h02f")) @[el2_dec_tlu_ctl.scala 2398:21] + node _T_2006 = bits(_T_2005, 0, 0) @[el2_dec_tlu_ctl.scala 2398:49] + node _T_2007 = eq(mhpme_vec[3], UInt<6>("h030")) @[el2_dec_tlu_ctl.scala 2399:21] + node _T_2008 = bits(_T_2007, 0, 0) @[el2_dec_tlu_ctl.scala 2399:49] + node _T_2009 = eq(mhpme_vec[3], UInt<6>("h031")) @[el2_dec_tlu_ctl.scala 2400:21] + node _T_2010 = bits(_T_2009, 0, 0) @[el2_dec_tlu_ctl.scala 2400:49] + node _T_2011 = dshr(io.mstatus, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2400:71] + node _T_2012 = bits(_T_2011, 0, 0) @[el2_dec_tlu_ctl.scala 2400:71] + node _T_2013 = not(_T_2012) @[el2_dec_tlu_ctl.scala 2400:60] + node _T_2014 = eq(mhpme_vec[3], UInt<6>("h032")) @[el2_dec_tlu_ctl.scala 2401:21] + node _T_2015 = bits(_T_2014, 0, 0) @[el2_dec_tlu_ctl.scala 2401:49] + node _T_2016 = dshr(io.mstatus, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2401:71] + node _T_2017 = bits(_T_2016, 0, 0) @[el2_dec_tlu_ctl.scala 2401:71] + node _T_2018 = not(_T_2017) @[el2_dec_tlu_ctl.scala 2401:60] + node _T_2019 = bits(io.mip, 5, 0) @[el2_dec_tlu_ctl.scala 2401:94] + node _T_2020 = bits(mie, 5, 0) @[el2_dec_tlu_ctl.scala 2401:105] + node _T_2021 = and(_T_2019, _T_2020) @[el2_dec_tlu_ctl.scala 2401:100] + node _T_2022 = and(_T_2018, _T_2021) @[el2_dec_tlu_ctl.scala 2401:85] + node _T_2023 = eq(mhpme_vec[3], UInt<6>("h036")) @[el2_dec_tlu_ctl.scala 2402:21] + node _T_2024 = bits(_T_2023, 0, 0) @[el2_dec_tlu_ctl.scala 2402:49] + node _T_2025 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[el2_dec_tlu_ctl.scala 2402:78] + node _T_2026 = eq(mhpme_vec[3], UInt<6>("h037")) @[el2_dec_tlu_ctl.scala 2403:21] + node _T_2027 = bits(_T_2026, 0, 0) @[el2_dec_tlu_ctl.scala 2403:49] + node _T_2028 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[el2_dec_tlu_ctl.scala 2403:81] + node _T_2029 = eq(mhpme_vec[3], UInt<6>("h038")) @[el2_dec_tlu_ctl.scala 2404:21] + node _T_2030 = bits(_T_2029, 0, 0) @[el2_dec_tlu_ctl.scala 2404:49] + node _T_2031 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[el2_dec_tlu_ctl.scala 2404:81] + node _T_2032 = eq(mhpme_vec[3], UInt<10>("h0200")) @[el2_dec_tlu_ctl.scala 2406:21] + node _T_2033 = bits(_T_2032, 0, 0) @[el2_dec_tlu_ctl.scala 2406:49] + node _T_2034 = eq(mhpme_vec[3], UInt<10>("h0201")) @[el2_dec_tlu_ctl.scala 2407:21] + node _T_2035 = bits(_T_2034, 0, 0) @[el2_dec_tlu_ctl.scala 2407:49] + node _T_2036 = eq(mhpme_vec[3], UInt<10>("h0202")) @[el2_dec_tlu_ctl.scala 2408:21] + node _T_2037 = bits(_T_2036, 0, 0) @[el2_dec_tlu_ctl.scala 2408:49] + node _T_2038 = eq(mhpme_vec[3], UInt<10>("h0203")) @[el2_dec_tlu_ctl.scala 2409:21] + node _T_2039 = bits(_T_2038, 0, 0) @[el2_dec_tlu_ctl.scala 2409:49] + node _T_2040 = eq(mhpme_vec[3], UInt<10>("h0204")) @[el2_dec_tlu_ctl.scala 2410:21] + node _T_2041 = bits(_T_2040, 0, 0) @[el2_dec_tlu_ctl.scala 2410:49] + node _T_2042 = mux(_T_1875, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2043 = mux(_T_1877, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2044 = mux(_T_1879, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2045 = mux(_T_1881, _T_1883, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2046 = mux(_T_1885, _T_1889, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2047 = mux(_T_1891, _T_1894, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2048 = mux(_T_1896, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2049 = mux(_T_1898, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2050 = mux(_T_1900, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2051 = mux(_T_1902, _T_1903, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2052 = mux(_T_1905, _T_1906, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2053 = mux(_T_1908, _T_1909, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2054 = mux(_T_1911, _T_1912, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2055 = mux(_T_1914, _T_1923, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2056 = mux(_T_1925, _T_1926, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2057 = mux(_T_1928, _T_1929, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2058 = mux(_T_1931, _T_1932, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2059 = mux(_T_1934, _T_1935, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2060 = mux(_T_1937, _T_1938, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2061 = mux(_T_1940, _T_1941, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2062 = mux(_T_1943, _T_1944, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2063 = mux(_T_1946, _T_1947, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2064 = mux(_T_1949, _T_1950, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2065 = mux(_T_1952, _T_1955, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2066 = mux(_T_1957, _T_1958, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2067 = mux(_T_1960, _T_1961, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2068 = mux(_T_1963, _T_1964, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2069 = mux(_T_1966, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2070 = mux(_T_1968, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2071 = mux(_T_1970, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2072 = mux(_T_1972, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2073 = mux(_T_1974, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2074 = mux(_T_1976, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2075 = mux(_T_1978, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2076 = mux(_T_1980, _T_1982, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2077 = mux(_T_1984, _T_1986, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2078 = mux(_T_1988, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2079 = mux(_T_1990, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2080 = mux(_T_1992, _T_1994, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2081 = mux(_T_1996, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2082 = mux(_T_1998, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2083 = mux(_T_2000, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2084 = mux(_T_2002, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2085 = mux(_T_2004, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2086 = mux(_T_2006, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2087 = mux(_T_2008, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2088 = mux(_T_2010, _T_2013, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2089 = mux(_T_2015, _T_2022, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2090 = mux(_T_2024, _T_2025, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2091 = mux(_T_2027, _T_2028, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2092 = mux(_T_2030, _T_2031, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2093 = mux(_T_2033, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2094 = mux(_T_2035, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2095 = mux(_T_2037, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2096 = mux(_T_2039, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2097 = mux(_T_2041, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2098 = or(_T_2042, _T_2043) @[Mux.scala 27:72] + node _T_2099 = or(_T_2098, _T_2044) @[Mux.scala 27:72] + node _T_2100 = or(_T_2099, _T_2045) @[Mux.scala 27:72] + node _T_2101 = or(_T_2100, _T_2046) @[Mux.scala 27:72] + node _T_2102 = or(_T_2101, _T_2047) @[Mux.scala 27:72] + node _T_2103 = or(_T_2102, _T_2048) @[Mux.scala 27:72] + node _T_2104 = or(_T_2103, _T_2049) @[Mux.scala 27:72] + node _T_2105 = or(_T_2104, _T_2050) @[Mux.scala 27:72] + node _T_2106 = or(_T_2105, _T_2051) @[Mux.scala 27:72] + node _T_2107 = or(_T_2106, _T_2052) @[Mux.scala 27:72] + node _T_2108 = or(_T_2107, _T_2053) @[Mux.scala 27:72] + node _T_2109 = or(_T_2108, _T_2054) @[Mux.scala 27:72] + node _T_2110 = or(_T_2109, _T_2055) @[Mux.scala 27:72] + node _T_2111 = or(_T_2110, _T_2056) @[Mux.scala 27:72] + node _T_2112 = or(_T_2111, _T_2057) @[Mux.scala 27:72] + node _T_2113 = or(_T_2112, _T_2058) @[Mux.scala 27:72] + node _T_2114 = or(_T_2113, _T_2059) @[Mux.scala 27:72] + node _T_2115 = or(_T_2114, _T_2060) @[Mux.scala 27:72] + node _T_2116 = or(_T_2115, _T_2061) @[Mux.scala 27:72] + node _T_2117 = or(_T_2116, _T_2062) @[Mux.scala 27:72] + node _T_2118 = or(_T_2117, _T_2063) @[Mux.scala 27:72] + node _T_2119 = or(_T_2118, _T_2064) @[Mux.scala 27:72] + node _T_2120 = or(_T_2119, _T_2065) @[Mux.scala 27:72] + node _T_2121 = or(_T_2120, _T_2066) @[Mux.scala 27:72] + node _T_2122 = or(_T_2121, _T_2067) @[Mux.scala 27:72] + node _T_2123 = or(_T_2122, _T_2068) @[Mux.scala 27:72] + node _T_2124 = or(_T_2123, _T_2069) @[Mux.scala 27:72] + node _T_2125 = or(_T_2124, _T_2070) @[Mux.scala 27:72] + node _T_2126 = or(_T_2125, _T_2071) @[Mux.scala 27:72] + node _T_2127 = or(_T_2126, _T_2072) @[Mux.scala 27:72] + node _T_2128 = or(_T_2127, _T_2073) @[Mux.scala 27:72] + node _T_2129 = or(_T_2128, _T_2074) @[Mux.scala 27:72] + node _T_2130 = or(_T_2129, _T_2075) @[Mux.scala 27:72] + node _T_2131 = or(_T_2130, _T_2076) @[Mux.scala 27:72] + node _T_2132 = or(_T_2131, _T_2077) @[Mux.scala 27:72] + node _T_2133 = or(_T_2132, _T_2078) @[Mux.scala 27:72] + node _T_2134 = or(_T_2133, _T_2079) @[Mux.scala 27:72] + node _T_2135 = or(_T_2134, _T_2080) @[Mux.scala 27:72] + node _T_2136 = or(_T_2135, _T_2081) @[Mux.scala 27:72] + node _T_2137 = or(_T_2136, _T_2082) @[Mux.scala 27:72] + node _T_2138 = or(_T_2137, _T_2083) @[Mux.scala 27:72] + node _T_2139 = or(_T_2138, _T_2084) @[Mux.scala 27:72] + node _T_2140 = or(_T_2139, _T_2085) @[Mux.scala 27:72] + node _T_2141 = or(_T_2140, _T_2086) @[Mux.scala 27:72] + node _T_2142 = or(_T_2141, _T_2087) @[Mux.scala 27:72] + node _T_2143 = or(_T_2142, _T_2088) @[Mux.scala 27:72] + node _T_2144 = or(_T_2143, _T_2089) @[Mux.scala 27:72] + node _T_2145 = or(_T_2144, _T_2090) @[Mux.scala 27:72] + node _T_2146 = or(_T_2145, _T_2091) @[Mux.scala 27:72] + node _T_2147 = or(_T_2146, _T_2092) @[Mux.scala 27:72] + node _T_2148 = or(_T_2147, _T_2093) @[Mux.scala 27:72] + node _T_2149 = or(_T_2148, _T_2094) @[Mux.scala 27:72] + node _T_2150 = or(_T_2149, _T_2095) @[Mux.scala 27:72] + node _T_2151 = or(_T_2150, _T_2096) @[Mux.scala 27:72] + node _T_2152 = or(_T_2151, _T_2097) @[Mux.scala 27:72] + wire _T_2153 : UInt<6> @[Mux.scala 27:72] + _T_2153 <= _T_2152 @[Mux.scala 27:72] + node _T_2154 = and(_T_1873, _T_2153) @[el2_dec_tlu_ctl.scala 2351:45] + mhpmc_inc_r[3] <= _T_2154 @[el2_dec_tlu_ctl.scala 2351:20] + reg _T_2155 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2413:54] + _T_2155 <= mhpmc_inc_r[0] @[el2_dec_tlu_ctl.scala 2413:54] + mhpmc_inc_r_d1[0] <= _T_2155 @[el2_dec_tlu_ctl.scala 2413:21] + reg _T_2156 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2414:54] + _T_2156 <= mhpmc_inc_r[1] @[el2_dec_tlu_ctl.scala 2414:54] + mhpmc_inc_r_d1[1] <= _T_2156 @[el2_dec_tlu_ctl.scala 2414:21] + reg _T_2157 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2415:54] + _T_2157 <= mhpmc_inc_r[2] @[el2_dec_tlu_ctl.scala 2415:54] + mhpmc_inc_r_d1[2] <= _T_2157 @[el2_dec_tlu_ctl.scala 2415:21] + reg _T_2158 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2416:54] + _T_2158 <= mhpmc_inc_r[3] @[el2_dec_tlu_ctl.scala 2416:54] + mhpmc_inc_r_d1[3] <= _T_2158 @[el2_dec_tlu_ctl.scala 2416:21] + reg perfcnt_halted_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2417:57] + perfcnt_halted_d1 <= perfcnt_halted @[el2_dec_tlu_ctl.scala 2417:57] + node _T_2159 = bits(io.dcsr, 10, 10) @[el2_dec_tlu_ctl.scala 2420:54] + node _T_2160 = and(io.dec_tlu_dbg_halted, _T_2159) @[el2_dec_tlu_ctl.scala 2420:45] + node _T_2161 = or(_T_2160, io.dec_tlu_pmu_fw_halted) @[el2_dec_tlu_ctl.scala 2420:68] + perfcnt_halted <= _T_2161 @[el2_dec_tlu_ctl.scala 2420:18] + node _T_2162 = bits(io.dcsr, 10, 10) @[el2_dec_tlu_ctl.scala 2421:71] + node _T_2163 = and(io.dec_tlu_dbg_halted, _T_2162) @[el2_dec_tlu_ctl.scala 2421:62] + node _T_2164 = not(_T_2163) @[el2_dec_tlu_ctl.scala 2421:38] + node _T_2165 = bits(_T_2164, 0, 0) @[Bitwise.scala 72:15] + node _T_2166 = mux(_T_2165, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_2167 = bits(mhpme_vec[3], 9, 9) @[el2_dec_tlu_ctl.scala 2421:105] + node _T_2168 = bits(mhpme_vec[2], 9, 9) @[el2_dec_tlu_ctl.scala 2421:121] + node _T_2169 = bits(mhpme_vec[1], 9, 9) @[el2_dec_tlu_ctl.scala 2421:137] + node _T_2170 = bits(mhpme_vec[0], 9, 9) @[el2_dec_tlu_ctl.scala 2421:153] + node _T_2171 = cat(_T_2169, _T_2170) @[Cat.scala 29:58] + node _T_2172 = cat(_T_2167, _T_2168) @[Cat.scala 29:58] + node _T_2173 = cat(_T_2172, _T_2171) @[Cat.scala 29:58] + node perfcnt_during_sleep = and(_T_2166, _T_2173) @[el2_dec_tlu_ctl.scala 2421:87] + node _T_2174 = bits(perfcnt_during_sleep, 0, 0) @[el2_dec_tlu_ctl.scala 2423:89] + node _T_2175 = not(_T_2174) @[el2_dec_tlu_ctl.scala 2423:68] + node _T_2176 = and(perfcnt_halted_d1, _T_2175) @[el2_dec_tlu_ctl.scala 2423:66] + node _T_2177 = not(_T_2176) @[el2_dec_tlu_ctl.scala 2423:46] + node _T_2178 = and(mhpmc_inc_r_d1[0], _T_2177) @[el2_dec_tlu_ctl.scala 2423:44] + io.dec_tlu_perfcnt0 <= _T_2178 @[el2_dec_tlu_ctl.scala 2423:23] + node _T_2179 = bits(perfcnt_during_sleep, 1, 1) @[el2_dec_tlu_ctl.scala 2424:89] + node _T_2180 = not(_T_2179) @[el2_dec_tlu_ctl.scala 2424:68] + node _T_2181 = and(perfcnt_halted_d1, _T_2180) @[el2_dec_tlu_ctl.scala 2424:66] + node _T_2182 = not(_T_2181) @[el2_dec_tlu_ctl.scala 2424:46] + node _T_2183 = and(mhpmc_inc_r_d1[1], _T_2182) @[el2_dec_tlu_ctl.scala 2424:44] + io.dec_tlu_perfcnt1 <= _T_2183 @[el2_dec_tlu_ctl.scala 2424:23] + node _T_2184 = bits(perfcnt_during_sleep, 2, 2) @[el2_dec_tlu_ctl.scala 2425:89] + node _T_2185 = not(_T_2184) @[el2_dec_tlu_ctl.scala 2425:68] + node _T_2186 = and(perfcnt_halted_d1, _T_2185) @[el2_dec_tlu_ctl.scala 2425:66] + node _T_2187 = not(_T_2186) @[el2_dec_tlu_ctl.scala 2425:46] + node _T_2188 = and(mhpmc_inc_r_d1[2], _T_2187) @[el2_dec_tlu_ctl.scala 2425:44] + io.dec_tlu_perfcnt2 <= _T_2188 @[el2_dec_tlu_ctl.scala 2425:23] + node _T_2189 = bits(perfcnt_during_sleep, 3, 3) @[el2_dec_tlu_ctl.scala 2426:89] + node _T_2190 = not(_T_2189) @[el2_dec_tlu_ctl.scala 2426:68] + node _T_2191 = and(perfcnt_halted_d1, _T_2190) @[el2_dec_tlu_ctl.scala 2426:66] + node _T_2192 = not(_T_2191) @[el2_dec_tlu_ctl.scala 2426:46] + node _T_2193 = and(mhpmc_inc_r_d1[3], _T_2192) @[el2_dec_tlu_ctl.scala 2426:44] + io.dec_tlu_perfcnt3 <= _T_2193 @[el2_dec_tlu_ctl.scala 2426:23] + node _T_2194 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2432:66] + node _T_2195 = eq(_T_2194, UInt<12>("h0b03")) @[el2_dec_tlu_ctl.scala 2432:73] + node mhpmc3_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2195) @[el2_dec_tlu_ctl.scala 2432:44] + node _T_2196 = not(perfcnt_halted) @[el2_dec_tlu_ctl.scala 2433:24] + node _T_2197 = bits(perfcnt_during_sleep, 0, 0) @[el2_dec_tlu_ctl.scala 2433:62] + node _T_2198 = or(_T_2196, _T_2197) @[el2_dec_tlu_ctl.scala 2433:40] + node _T_2199 = orr(mhpmc_inc_r[0]) @[el2_dec_tlu_ctl.scala 2433:87] + node mhpmc3_wr_en1 = and(_T_2198, _T_2199) @[el2_dec_tlu_ctl.scala 2433:67] + node mhpmc3_wr_en = or(mhpmc3_wr_en0, mhpmc3_wr_en1) @[el2_dec_tlu_ctl.scala 2434:37] + node _T_2200 = bits(mhpmc3h, 31, 0) @[el2_dec_tlu_ctl.scala 2437:29] + node _T_2201 = bits(mhpmc3, 31, 0) @[el2_dec_tlu_ctl.scala 2437:42] + node _T_2202 = cat(_T_2200, _T_2201) @[Cat.scala 29:58] + node _T_2203 = cat(UInt<63>("h00"), mhpmc_inc_r[0]) @[Cat.scala 29:58] + node _T_2204 = add(_T_2202, _T_2203) @[el2_dec_tlu_ctl.scala 2437:50] + node _T_2205 = tail(_T_2204, 1) @[el2_dec_tlu_ctl.scala 2437:50] + mhpmc3_incr <= _T_2205 @[el2_dec_tlu_ctl.scala 2437:15] + node _T_2206 = bits(mhpmc3_wr_en0, 0, 0) @[el2_dec_tlu_ctl.scala 2438:37] + node _T_2207 = bits(mhpmc3_incr, 31, 0) @[el2_dec_tlu_ctl.scala 2438:77] + node mhpmc3_ns = mux(_T_2206, io.dec_csr_wrdata_r, _T_2207) @[el2_dec_tlu_ctl.scala 2438:22] + node _T_2208 = bits(mhpmc3_wr_en, 0, 0) @[el2_dec_tlu_ctl.scala 2440:43] + inst rvclkhdr_26 of rvclkhdr_34 @[el2_lib.scala 508:23] + rvclkhdr_26.clock <= clock + rvclkhdr_26.reset <= reset + rvclkhdr_26.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_26.io.en <= _T_2208 @[el2_lib.scala 511:17] + rvclkhdr_26.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_2209 : UInt, rvclkhdr_26.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_2209 <= mhpmc3_ns @[el2_lib.scala 514:16] + mhpmc3 <= _T_2209 @[el2_dec_tlu_ctl.scala 2440:10] + node _T_2210 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2442:67] + node _T_2211 = eq(_T_2210, UInt<12>("h0b83")) @[el2_dec_tlu_ctl.scala 2442:74] + node mhpmc3h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2211) @[el2_dec_tlu_ctl.scala 2442:45] + node mhpmc3h_wr_en = or(mhpmc3h_wr_en0, mhpmc3_wr_en1) @[el2_dec_tlu_ctl.scala 2443:39] + node _T_2212 = bits(mhpmc3h_wr_en0, 0, 0) @[el2_dec_tlu_ctl.scala 2444:39] + node _T_2213 = bits(mhpmc3_incr, 63, 32) @[el2_dec_tlu_ctl.scala 2444:79] + node mhpmc3h_ns = mux(_T_2212, io.dec_csr_wrdata_r, _T_2213) @[el2_dec_tlu_ctl.scala 2444:23] + node _T_2214 = bits(mhpmc3h_wr_en, 0, 0) @[el2_dec_tlu_ctl.scala 2446:47] + inst rvclkhdr_27 of rvclkhdr_35 @[el2_lib.scala 508:23] + rvclkhdr_27.clock <= clock + rvclkhdr_27.reset <= reset + rvclkhdr_27.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_27.io.en <= _T_2214 @[el2_lib.scala 511:17] + rvclkhdr_27.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_2215 : UInt, rvclkhdr_27.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_2215 <= mhpmc3h_ns @[el2_lib.scala 514:16] + mhpmc3h <= _T_2215 @[el2_dec_tlu_ctl.scala 2446:11] + node _T_2216 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2451:66] + node _T_2217 = eq(_T_2216, UInt<12>("h0b04")) @[el2_dec_tlu_ctl.scala 2451:73] + node mhpmc4_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2217) @[el2_dec_tlu_ctl.scala 2451:44] + node _T_2218 = not(perfcnt_halted) @[el2_dec_tlu_ctl.scala 2452:24] + node _T_2219 = bits(perfcnt_during_sleep, 1, 1) @[el2_dec_tlu_ctl.scala 2452:62] + node _T_2220 = or(_T_2218, _T_2219) @[el2_dec_tlu_ctl.scala 2452:40] + node _T_2221 = orr(mhpmc_inc_r[1]) @[el2_dec_tlu_ctl.scala 2452:87] + node mhpmc4_wr_en1 = and(_T_2220, _T_2221) @[el2_dec_tlu_ctl.scala 2452:67] + node mhpmc4_wr_en = or(mhpmc4_wr_en0, mhpmc4_wr_en1) @[el2_dec_tlu_ctl.scala 2453:37] + node _T_2222 = bits(mhpmc4h, 31, 0) @[el2_dec_tlu_ctl.scala 2457:29] + node _T_2223 = bits(mhpmc4, 31, 0) @[el2_dec_tlu_ctl.scala 2457:42] + node _T_2224 = cat(_T_2222, _T_2223) @[Cat.scala 29:58] + node _T_2225 = cat(UInt<63>("h00"), mhpmc_inc_r[1]) @[Cat.scala 29:58] + node _T_2226 = add(_T_2224, _T_2225) @[el2_dec_tlu_ctl.scala 2457:50] + node _T_2227 = tail(_T_2226, 1) @[el2_dec_tlu_ctl.scala 2457:50] + mhpmc4_incr <= _T_2227 @[el2_dec_tlu_ctl.scala 2457:15] + node _T_2228 = bits(mhpmc4_wr_en0, 0, 0) @[el2_dec_tlu_ctl.scala 2458:37] + node _T_2229 = bits(io.dec_csr_wrdata_r, 31, 0) @[el2_dec_tlu_ctl.scala 2458:64] + node _T_2230 = bits(mhpmc4_incr, 31, 0) @[el2_dec_tlu_ctl.scala 2458:83] + node mhpmc4_ns = mux(_T_2228, _T_2229, _T_2230) @[el2_dec_tlu_ctl.scala 2458:22] + node _T_2231 = bits(mhpmc4_wr_en, 0, 0) @[el2_dec_tlu_ctl.scala 2459:44] + inst rvclkhdr_28 of rvclkhdr_36 @[el2_lib.scala 508:23] + rvclkhdr_28.clock <= clock + rvclkhdr_28.reset <= reset + rvclkhdr_28.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_28.io.en <= _T_2231 @[el2_lib.scala 511:17] + rvclkhdr_28.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_2232 : UInt, rvclkhdr_28.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_2232 <= mhpmc4_ns @[el2_lib.scala 514:16] + mhpmc4 <= _T_2232 @[el2_dec_tlu_ctl.scala 2459:10] + node _T_2233 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2461:67] + node _T_2234 = eq(_T_2233, UInt<12>("h0b84")) @[el2_dec_tlu_ctl.scala 2461:74] + node mhpmc4h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2234) @[el2_dec_tlu_ctl.scala 2461:45] + node mhpmc4h_wr_en = or(mhpmc4h_wr_en0, mhpmc4_wr_en1) @[el2_dec_tlu_ctl.scala 2462:39] + node _T_2235 = bits(mhpmc4h_wr_en0, 0, 0) @[el2_dec_tlu_ctl.scala 2463:39] + node _T_2236 = bits(mhpmc4_incr, 63, 32) @[el2_dec_tlu_ctl.scala 2463:79] + node mhpmc4h_ns = mux(_T_2235, io.dec_csr_wrdata_r, _T_2236) @[el2_dec_tlu_ctl.scala 2463:23] + node _T_2237 = bits(mhpmc4h_wr_en, 0, 0) @[el2_dec_tlu_ctl.scala 2464:47] + inst rvclkhdr_29 of rvclkhdr_37 @[el2_lib.scala 508:23] + rvclkhdr_29.clock <= clock + rvclkhdr_29.reset <= reset + rvclkhdr_29.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_29.io.en <= _T_2237 @[el2_lib.scala 511:17] + rvclkhdr_29.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_2238 : UInt, rvclkhdr_29.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_2238 <= mhpmc4h_ns @[el2_lib.scala 514:16] + mhpmc4h <= _T_2238 @[el2_dec_tlu_ctl.scala 2464:11] + node _T_2239 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2470:66] + node _T_2240 = eq(_T_2239, UInt<12>("h0b05")) @[el2_dec_tlu_ctl.scala 2470:73] + node mhpmc5_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2240) @[el2_dec_tlu_ctl.scala 2470:44] + node _T_2241 = not(perfcnt_halted) @[el2_dec_tlu_ctl.scala 2471:24] + node _T_2242 = bits(perfcnt_during_sleep, 2, 2) @[el2_dec_tlu_ctl.scala 2471:62] + node _T_2243 = or(_T_2241, _T_2242) @[el2_dec_tlu_ctl.scala 2471:40] + node _T_2244 = orr(mhpmc_inc_r[2]) @[el2_dec_tlu_ctl.scala 2471:87] + node mhpmc5_wr_en1 = and(_T_2243, _T_2244) @[el2_dec_tlu_ctl.scala 2471:67] + node mhpmc5_wr_en = or(mhpmc5_wr_en0, mhpmc5_wr_en1) @[el2_dec_tlu_ctl.scala 2472:37] + node _T_2245 = bits(mhpmc5h, 31, 0) @[el2_dec_tlu_ctl.scala 2474:29] + node _T_2246 = bits(mhpmc5, 31, 0) @[el2_dec_tlu_ctl.scala 2474:42] + node _T_2247 = cat(_T_2245, _T_2246) @[Cat.scala 29:58] + node _T_2248 = cat(UInt<63>("h00"), mhpmc_inc_r[2]) @[Cat.scala 29:58] + node _T_2249 = add(_T_2247, _T_2248) @[el2_dec_tlu_ctl.scala 2474:50] + node _T_2250 = tail(_T_2249, 1) @[el2_dec_tlu_ctl.scala 2474:50] + mhpmc5_incr <= _T_2250 @[el2_dec_tlu_ctl.scala 2474:15] + node _T_2251 = bits(mhpmc5_wr_en0, 0, 0) @[el2_dec_tlu_ctl.scala 2475:37] + node _T_2252 = bits(mhpmc5_incr, 31, 0) @[el2_dec_tlu_ctl.scala 2475:77] + node mhpmc5_ns = mux(_T_2251, io.dec_csr_wrdata_r, _T_2252) @[el2_dec_tlu_ctl.scala 2475:22] + node _T_2253 = bits(mhpmc5_wr_en, 0, 0) @[el2_dec_tlu_ctl.scala 2477:44] + inst rvclkhdr_30 of rvclkhdr_38 @[el2_lib.scala 508:23] + rvclkhdr_30.clock <= clock + rvclkhdr_30.reset <= reset + rvclkhdr_30.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_30.io.en <= _T_2253 @[el2_lib.scala 511:17] + rvclkhdr_30.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_2254 : UInt, rvclkhdr_30.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_2254 <= mhpmc5_ns @[el2_lib.scala 514:16] + mhpmc5 <= _T_2254 @[el2_dec_tlu_ctl.scala 2477:10] + node _T_2255 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2479:67] + node _T_2256 = eq(_T_2255, UInt<12>("h0b85")) @[el2_dec_tlu_ctl.scala 2479:74] + node mhpmc5h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2256) @[el2_dec_tlu_ctl.scala 2479:45] + node mhpmc5h_wr_en = or(mhpmc5h_wr_en0, mhpmc5_wr_en1) @[el2_dec_tlu_ctl.scala 2480:39] + node _T_2257 = bits(mhpmc5h_wr_en0, 0, 0) @[el2_dec_tlu_ctl.scala 2481:39] + node _T_2258 = bits(mhpmc5_incr, 63, 32) @[el2_dec_tlu_ctl.scala 2481:79] + node mhpmc5h_ns = mux(_T_2257, io.dec_csr_wrdata_r, _T_2258) @[el2_dec_tlu_ctl.scala 2481:23] + node _T_2259 = bits(mhpmc5h_wr_en, 0, 0) @[el2_dec_tlu_ctl.scala 2483:47] + inst rvclkhdr_31 of rvclkhdr_39 @[el2_lib.scala 508:23] + rvclkhdr_31.clock <= clock + rvclkhdr_31.reset <= reset + rvclkhdr_31.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_31.io.en <= _T_2259 @[el2_lib.scala 511:17] + rvclkhdr_31.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_2260 : UInt, rvclkhdr_31.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_2260 <= mhpmc5h_ns @[el2_lib.scala 514:16] + mhpmc5h <= _T_2260 @[el2_dec_tlu_ctl.scala 2483:11] + node _T_2261 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2488:66] + node _T_2262 = eq(_T_2261, UInt<12>("h0b06")) @[el2_dec_tlu_ctl.scala 2488:73] + node mhpmc6_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2262) @[el2_dec_tlu_ctl.scala 2488:44] + node _T_2263 = not(perfcnt_halted) @[el2_dec_tlu_ctl.scala 2489:24] + node _T_2264 = bits(perfcnt_during_sleep, 3, 3) @[el2_dec_tlu_ctl.scala 2489:62] + node _T_2265 = or(_T_2263, _T_2264) @[el2_dec_tlu_ctl.scala 2489:40] + node _T_2266 = orr(mhpmc_inc_r[3]) @[el2_dec_tlu_ctl.scala 2489:87] + node mhpmc6_wr_en1 = and(_T_2265, _T_2266) @[el2_dec_tlu_ctl.scala 2489:67] + node mhpmc6_wr_en = or(mhpmc6_wr_en0, mhpmc6_wr_en1) @[el2_dec_tlu_ctl.scala 2490:37] + node _T_2267 = bits(mhpmc6h, 31, 0) @[el2_dec_tlu_ctl.scala 2492:29] + node _T_2268 = bits(mhpmc6, 31, 0) @[el2_dec_tlu_ctl.scala 2492:42] + node _T_2269 = cat(_T_2267, _T_2268) @[Cat.scala 29:58] + node _T_2270 = cat(UInt<63>("h00"), mhpmc_inc_r[3]) @[Cat.scala 29:58] + node _T_2271 = add(_T_2269, _T_2270) @[el2_dec_tlu_ctl.scala 2492:50] + node _T_2272 = tail(_T_2271, 1) @[el2_dec_tlu_ctl.scala 2492:50] + mhpmc6_incr <= _T_2272 @[el2_dec_tlu_ctl.scala 2492:15] + node _T_2273 = bits(mhpmc6_wr_en0, 0, 0) @[el2_dec_tlu_ctl.scala 2493:37] + node _T_2274 = bits(mhpmc6_incr, 31, 0) @[el2_dec_tlu_ctl.scala 2493:77] + node mhpmc6_ns = mux(_T_2273, io.dec_csr_wrdata_r, _T_2274) @[el2_dec_tlu_ctl.scala 2493:22] + node _T_2275 = bits(mhpmc6_wr_en, 0, 0) @[el2_dec_tlu_ctl.scala 2495:44] + inst rvclkhdr_32 of rvclkhdr_40 @[el2_lib.scala 508:23] + rvclkhdr_32.clock <= clock + rvclkhdr_32.reset <= reset + rvclkhdr_32.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_32.io.en <= _T_2275 @[el2_lib.scala 511:17] + rvclkhdr_32.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_2276 : UInt, rvclkhdr_32.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_2276 <= mhpmc6_ns @[el2_lib.scala 514:16] + mhpmc6 <= _T_2276 @[el2_dec_tlu_ctl.scala 2495:10] + node _T_2277 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2497:67] + node _T_2278 = eq(_T_2277, UInt<12>("h0b86")) @[el2_dec_tlu_ctl.scala 2497:74] + node mhpmc6h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2278) @[el2_dec_tlu_ctl.scala 2497:45] + node mhpmc6h_wr_en = or(mhpmc6h_wr_en0, mhpmc6_wr_en1) @[el2_dec_tlu_ctl.scala 2498:39] + node _T_2279 = bits(mhpmc6h_wr_en0, 0, 0) @[el2_dec_tlu_ctl.scala 2499:39] + node _T_2280 = bits(mhpmc6_incr, 63, 32) @[el2_dec_tlu_ctl.scala 2499:79] + node mhpmc6h_ns = mux(_T_2279, io.dec_csr_wrdata_r, _T_2280) @[el2_dec_tlu_ctl.scala 2499:23] + node _T_2281 = bits(mhpmc6h_wr_en, 0, 0) @[el2_dec_tlu_ctl.scala 2501:47] + inst rvclkhdr_33 of rvclkhdr_41 @[el2_lib.scala 508:23] + rvclkhdr_33.clock <= clock + rvclkhdr_33.reset <= reset + rvclkhdr_33.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_33.io.en <= _T_2281 @[el2_lib.scala 511:17] + rvclkhdr_33.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_2282 : UInt, rvclkhdr_33.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_2282 <= mhpmc6h_ns @[el2_lib.scala 514:16] + mhpmc6h <= _T_2282 @[el2_dec_tlu_ctl.scala 2501:11] + node _T_2283 = bits(io.dec_csr_wrdata_r, 9, 0) @[el2_dec_tlu_ctl.scala 2508:51] + node _T_2284 = gt(_T_2283, UInt<10>("h0204")) @[el2_dec_tlu_ctl.scala 2508:57] + node _T_2285 = bits(io.dec_csr_wrdata_r, 31, 10) @[el2_dec_tlu_ctl.scala 2508:94] + node _T_2286 = orr(_T_2285) @[el2_dec_tlu_ctl.scala 2508:103] + node _T_2287 = or(_T_2284, _T_2286) @[el2_dec_tlu_ctl.scala 2508:72] + node _T_2288 = bits(io.dec_csr_wrdata_r, 9, 0) @[el2_dec_tlu_ctl.scala 2508:142] + node event_saturate_r = mux(_T_2287, UInt<10>("h0204"), _T_2288) @[el2_dec_tlu_ctl.scala 2508:29] + node _T_2289 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2510:64] + node _T_2290 = eq(_T_2289, UInt<12>("h0323")) @[el2_dec_tlu_ctl.scala 2510:71] + node wr_mhpme3_r = and(io.dec_csr_wen_r_mod, _T_2290) @[el2_dec_tlu_ctl.scala 2510:42] + node _T_2291 = bits(wr_mhpme3_r, 0, 0) @[el2_dec_tlu_ctl.scala 2512:81] + reg _T_2292 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2291 : @[Reg.scala 28:19] + _T_2292 <= event_saturate_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + mhpme3 <= _T_2292 @[el2_dec_tlu_ctl.scala 2512:10] + node _T_2293 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2517:64] + node _T_2294 = eq(_T_2293, UInt<12>("h0324")) @[el2_dec_tlu_ctl.scala 2517:71] + node wr_mhpme4_r = and(io.dec_csr_wen_r_mod, _T_2294) @[el2_dec_tlu_ctl.scala 2517:42] + node _T_2295 = bits(wr_mhpme4_r, 0, 0) @[el2_dec_tlu_ctl.scala 2518:81] + reg _T_2296 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2295 : @[Reg.scala 28:19] + _T_2296 <= event_saturate_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + mhpme4 <= _T_2296 @[el2_dec_tlu_ctl.scala 2518:10] + node _T_2297 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2524:64] + node _T_2298 = eq(_T_2297, UInt<12>("h0325")) @[el2_dec_tlu_ctl.scala 2524:71] + node wr_mhpme5_r = and(io.dec_csr_wen_r_mod, _T_2298) @[el2_dec_tlu_ctl.scala 2524:42] + node _T_2299 = bits(wr_mhpme5_r, 0, 0) @[el2_dec_tlu_ctl.scala 2525:81] + reg _T_2300 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2299 : @[Reg.scala 28:19] + _T_2300 <= event_saturate_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + mhpme5 <= _T_2300 @[el2_dec_tlu_ctl.scala 2525:10] + node _T_2301 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2531:64] + node _T_2302 = eq(_T_2301, UInt<12>("h0326")) @[el2_dec_tlu_ctl.scala 2531:71] + node wr_mhpme6_r = and(io.dec_csr_wen_r_mod, _T_2302) @[el2_dec_tlu_ctl.scala 2531:42] + node _T_2303 = bits(wr_mhpme6_r, 0, 0) @[el2_dec_tlu_ctl.scala 2532:81] + reg _T_2304 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2303 : @[Reg.scala 28:19] + _T_2304 <= event_saturate_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + mhpme6 <= _T_2304 @[el2_dec_tlu_ctl.scala 2532:10] + node _T_2305 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2548:71] + node _T_2306 = eq(_T_2305, UInt<12>("h0320")) @[el2_dec_tlu_ctl.scala 2548:78] + node wr_mcountinhibit_r = and(io.dec_csr_wen_r_mod, _T_2306) @[el2_dec_tlu_ctl.scala 2548:49] + node _T_2307 = bits(mcountinhibit, 0, 0) @[el2_dec_tlu_ctl.scala 2550:55] + wire temp_ncount0 : UInt<1> + temp_ncount0 <= _T_2307 + node _T_2308 = bits(mcountinhibit, 1, 1) @[el2_dec_tlu_ctl.scala 2551:55] + wire temp_ncount1 : UInt<1> + temp_ncount1 <= _T_2308 + node _T_2309 = bits(mcountinhibit, 6, 2) @[el2_dec_tlu_ctl.scala 2552:56] + wire temp_ncount6_2 : UInt<5> + temp_ncount6_2 <= _T_2309 + node _T_2310 = bits(io.dec_csr_wrdata_r, 6, 2) @[el2_dec_tlu_ctl.scala 2553:75] + node _T_2311 = bits(wr_mcountinhibit_r, 0, 0) @[el2_dec_tlu_ctl.scala 2553:104] + reg _T_2312 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2311 : @[Reg.scala 28:19] + _T_2312 <= _T_2310 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + temp_ncount6_2 <= _T_2312 @[el2_dec_tlu_ctl.scala 2553:18] + node _T_2313 = bits(io.dec_csr_wrdata_r, 0, 0) @[el2_dec_tlu_ctl.scala 2555:73] + node _T_2314 = bits(wr_mcountinhibit_r, 0, 0) @[el2_dec_tlu_ctl.scala 2555:100] + reg _T_2315 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2314 : @[Reg.scala 28:19] + _T_2315 <= _T_2313 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + temp_ncount0 <= _T_2315 @[el2_dec_tlu_ctl.scala 2555:16] + node _T_2316 = cat(temp_ncount6_2, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2317 = cat(_T_2316, temp_ncount0) @[Cat.scala 29:58] + mcountinhibit <= _T_2317 @[el2_dec_tlu_ctl.scala 2556:17] + node _T_2318 = or(io.i0_valid_wb, io.exc_or_int_valid_r_d1) @[el2_dec_tlu_ctl.scala 2563:52] + node _T_2319 = or(_T_2318, io.interrupt_valid_r_d1) @[el2_dec_tlu_ctl.scala 2563:79] + node _T_2320 = or(_T_2319, io.dec_tlu_i0_valid_wb1) @[el2_dec_tlu_ctl.scala 2563:105] + node _T_2321 = or(_T_2320, io.dec_tlu_i0_exc_valid_wb1) @[el2_dec_tlu_ctl.scala 2563:131] + node _T_2322 = or(_T_2321, io.dec_tlu_int_valid_wb1) @[el2_dec_tlu_ctl.scala 2564:33] + node _T_2323 = or(_T_2322, io.clk_override) @[el2_dec_tlu_ctl.scala 2564:60] + node _T_2324 = bits(_T_2323, 0, 0) @[el2_dec_tlu_ctl.scala 2564:79] + inst rvclkhdr_34 of rvclkhdr_42 @[el2_lib.scala 483:22] + rvclkhdr_34.clock <= clock + rvclkhdr_34.reset <= reset + rvclkhdr_34.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_34.io.en <= _T_2324 @[el2_lib.scala 485:16] + rvclkhdr_34.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + reg _T_2325 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2566:63] + _T_2325 <= io.i0_valid_wb @[el2_dec_tlu_ctl.scala 2566:63] + io.dec_tlu_i0_valid_wb1 <= _T_2325 @[el2_dec_tlu_ctl.scala 2566:31] + node _T_2326 = or(io.i0_exception_valid_r_d1, io.lsu_i0_exc_r_d1) @[el2_dec_tlu_ctl.scala 2567:92] + node _T_2327 = not(io.trigger_hit_dmode_r_d1) @[el2_dec_tlu_ctl.scala 2567:138] + node _T_2328 = and(io.trigger_hit_r_d1, _T_2327) @[el2_dec_tlu_ctl.scala 2567:136] + node _T_2329 = or(_T_2326, _T_2328) @[el2_dec_tlu_ctl.scala 2567:113] + reg _T_2330 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2567:63] + _T_2330 <= _T_2329 @[el2_dec_tlu_ctl.scala 2567:63] + io.dec_tlu_i0_exc_valid_wb1 <= _T_2330 @[el2_dec_tlu_ctl.scala 2567:31] + reg _T_2331 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2568:63] + _T_2331 <= io.exc_cause_wb @[el2_dec_tlu_ctl.scala 2568:63] + io.dec_tlu_exc_cause_wb1 <= _T_2331 @[el2_dec_tlu_ctl.scala 2568:31] + reg _T_2332 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2569:63] + _T_2332 <= io.interrupt_valid_r_d1 @[el2_dec_tlu_ctl.scala 2569:63] + io.dec_tlu_int_valid_wb1 <= _T_2332 @[el2_dec_tlu_ctl.scala 2569:31] + io.dec_tlu_mtval_wb1 <= mtval @[el2_dec_tlu_ctl.scala 2571:25] + node _T_2333 = bits(io.csr_pkt.csr_misa, 0, 0) @[el2_dec_tlu_ctl.scala 2577:25] + node _T_2334 = bits(io.csr_pkt.csr_mvendorid, 0, 0) @[el2_dec_tlu_ctl.scala 2578:30] + node _T_2335 = bits(io.csr_pkt.csr_marchid, 0, 0) @[el2_dec_tlu_ctl.scala 2579:28] + node _T_2336 = bits(io.csr_pkt.csr_mimpid, 0, 0) @[el2_dec_tlu_ctl.scala 2580:27] + node _T_2337 = bits(io.csr_pkt.csr_mhartid, 0, 0) @[el2_dec_tlu_ctl.scala 2581:28] + node _T_2338 = cat(io.core_id, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_2339 = bits(io.csr_pkt.csr_mstatus, 0, 0) @[el2_dec_tlu_ctl.scala 2582:28] + node _T_2340 = bits(io.mstatus, 1, 1) @[el2_dec_tlu_ctl.scala 2582:91] + node _T_2341 = bits(io.mstatus, 0, 0) @[el2_dec_tlu_ctl.scala 2582:116] + node _T_2342 = cat(UInt<3>("h00"), _T_2341) @[Cat.scala 29:58] + node _T_2343 = cat(_T_2342, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2344 = cat(UInt<3>("h00"), _T_2340) @[Cat.scala 29:58] + node _T_2345 = cat(UInt<19>("h00"), UInt<2>("h03")) @[Cat.scala 29:58] + node _T_2346 = cat(_T_2345, _T_2344) @[Cat.scala 29:58] + node _T_2347 = cat(_T_2346, _T_2343) @[Cat.scala 29:58] + node _T_2348 = bits(io.csr_pkt.csr_mtvec, 0, 0) @[el2_dec_tlu_ctl.scala 2583:26] + node _T_2349 = bits(io.mtvec, 30, 1) @[el2_dec_tlu_ctl.scala 2583:58] + node _T_2350 = bits(io.mtvec, 0, 0) @[el2_dec_tlu_ctl.scala 2583:84] + node _T_2351 = cat(_T_2349, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2352 = cat(_T_2351, _T_2350) @[Cat.scala 29:58] + node _T_2353 = bits(io.csr_pkt.csr_mip, 0, 0) @[el2_dec_tlu_ctl.scala 2584:24] + node _T_2354 = bits(io.mip, 5, 3) @[el2_dec_tlu_ctl.scala 2584:66] + node _T_2355 = bits(io.mip, 2, 2) @[el2_dec_tlu_ctl.scala 2584:90] + node _T_2356 = bits(io.mip, 1, 1) @[el2_dec_tlu_ctl.scala 2584:111] + node _T_2357 = bits(io.mip, 0, 0) @[el2_dec_tlu_ctl.scala 2584:132] + node _T_2358 = cat(_T_2357, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2359 = cat(_T_2356, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2360 = cat(_T_2359, _T_2358) @[Cat.scala 29:58] + node _T_2361 = cat(_T_2355, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2362 = cat(UInt<1>("h00"), _T_2354) @[Cat.scala 29:58] + node _T_2363 = cat(_T_2362, UInt<16>("h00")) @[Cat.scala 29:58] + node _T_2364 = cat(_T_2363, _T_2361) @[Cat.scala 29:58] + node _T_2365 = cat(_T_2364, _T_2360) @[Cat.scala 29:58] + node _T_2366 = bits(io.csr_pkt.csr_mie, 0, 0) @[el2_dec_tlu_ctl.scala 2585:24] + node _T_2367 = bits(mie, 5, 3) @[el2_dec_tlu_ctl.scala 2585:63] + node _T_2368 = bits(mie, 2, 2) @[el2_dec_tlu_ctl.scala 2585:84] + node _T_2369 = bits(mie, 1, 1) @[el2_dec_tlu_ctl.scala 2585:102] + node _T_2370 = bits(mie, 0, 0) @[el2_dec_tlu_ctl.scala 2585:120] + node _T_2371 = cat(_T_2370, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2372 = cat(_T_2369, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2373 = cat(_T_2372, _T_2371) @[Cat.scala 29:58] + node _T_2374 = cat(_T_2368, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2375 = cat(UInt<1>("h00"), _T_2367) @[Cat.scala 29:58] + node _T_2376 = cat(_T_2375, UInt<16>("h00")) @[Cat.scala 29:58] + node _T_2377 = cat(_T_2376, _T_2374) @[Cat.scala 29:58] + node _T_2378 = cat(_T_2377, _T_2373) @[Cat.scala 29:58] + node _T_2379 = bits(io.csr_pkt.csr_mcyclel, 0, 0) @[el2_dec_tlu_ctl.scala 2586:28] + node _T_2380 = bits(mcyclel, 31, 0) @[el2_dec_tlu_ctl.scala 2586:53] + node _T_2381 = bits(io.csr_pkt.csr_mcycleh, 0, 0) @[el2_dec_tlu_ctl.scala 2587:28] + node _T_2382 = bits(mcycleh_inc, 31, 0) @[el2_dec_tlu_ctl.scala 2587:57] + node _T_2383 = bits(io.csr_pkt.csr_minstretl, 0, 0) @[el2_dec_tlu_ctl.scala 2588:30] + node _T_2384 = bits(minstretl, 31, 0) @[el2_dec_tlu_ctl.scala 2588:60] + node _T_2385 = bits(io.csr_pkt.csr_minstreth, 0, 0) @[el2_dec_tlu_ctl.scala 2589:30] + node _T_2386 = bits(minstreth_inc, 31, 0) @[el2_dec_tlu_ctl.scala 2589:60] + node _T_2387 = bits(io.csr_pkt.csr_mscratch, 0, 0) @[el2_dec_tlu_ctl.scala 2590:29] + node _T_2388 = bits(mscratch, 31, 0) @[el2_dec_tlu_ctl.scala 2590:54] + node _T_2389 = bits(io.csr_pkt.csr_mepc, 0, 0) @[el2_dec_tlu_ctl.scala 2591:25] + node _T_2390 = cat(io.mepc, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2391 = bits(io.csr_pkt.csr_mcause, 0, 0) @[el2_dec_tlu_ctl.scala 2592:27] + node _T_2392 = bits(mcause, 31, 0) @[el2_dec_tlu_ctl.scala 2592:52] + node _T_2393 = bits(io.csr_pkt.csr_mscause, 0, 0) @[el2_dec_tlu_ctl.scala 2593:28] + node _T_2394 = bits(mscause, 3, 0) @[el2_dec_tlu_ctl.scala 2593:68] + node _T_2395 = cat(UInt<28>("h00"), _T_2394) @[Cat.scala 29:58] + node _T_2396 = bits(io.csr_pkt.csr_mtval, 0, 0) @[el2_dec_tlu_ctl.scala 2594:26] + node _T_2397 = bits(mtval, 31, 0) @[el2_dec_tlu_ctl.scala 2594:51] + node _T_2398 = bits(io.csr_pkt.csr_mrac, 0, 0) @[el2_dec_tlu_ctl.scala 2595:25] + node _T_2399 = bits(mrac, 31, 0) @[el2_dec_tlu_ctl.scala 2595:50] + node _T_2400 = bits(io.csr_pkt.csr_mdseac, 0, 0) @[el2_dec_tlu_ctl.scala 2596:27] + node _T_2401 = bits(mdseac, 31, 0) @[el2_dec_tlu_ctl.scala 2596:52] + node _T_2402 = bits(io.csr_pkt.csr_meivt, 0, 0) @[el2_dec_tlu_ctl.scala 2597:26] + node _T_2403 = cat(meivt, UInt<10>("h00")) @[Cat.scala 29:58] + node _T_2404 = bits(io.csr_pkt.csr_meihap, 0, 0) @[el2_dec_tlu_ctl.scala 2598:27] + node _T_2405 = cat(meivt, meihap) @[Cat.scala 29:58] + node _T_2406 = cat(_T_2405, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_2407 = bits(io.csr_pkt.csr_meicurpl, 0, 0) @[el2_dec_tlu_ctl.scala 2599:29] + node _T_2408 = bits(meicurpl, 3, 0) @[el2_dec_tlu_ctl.scala 2599:69] + node _T_2409 = cat(UInt<28>("h00"), _T_2408) @[Cat.scala 29:58] + node _T_2410 = bits(io.csr_pkt.csr_meicidpl, 0, 0) @[el2_dec_tlu_ctl.scala 2600:29] + node _T_2411 = bits(meicidpl, 3, 0) @[el2_dec_tlu_ctl.scala 2600:69] + node _T_2412 = cat(UInt<28>("h00"), _T_2411) @[Cat.scala 29:58] + node _T_2413 = bits(io.csr_pkt.csr_meipt, 0, 0) @[el2_dec_tlu_ctl.scala 2601:26] + node _T_2414 = bits(meipt, 3, 0) @[el2_dec_tlu_ctl.scala 2601:66] + node _T_2415 = cat(UInt<28>("h00"), _T_2414) @[Cat.scala 29:58] + node _T_2416 = bits(io.csr_pkt.csr_mcgc, 0, 0) @[el2_dec_tlu_ctl.scala 2602:25] + node _T_2417 = bits(mcgc, 8, 0) @[el2_dec_tlu_ctl.scala 2602:65] + node _T_2418 = cat(UInt<23>("h00"), _T_2417) @[Cat.scala 29:58] + node _T_2419 = bits(io.csr_pkt.csr_mfdc, 0, 0) @[el2_dec_tlu_ctl.scala 2603:25] + node _T_2420 = bits(mfdc, 18, 0) @[el2_dec_tlu_ctl.scala 2603:65] + node _T_2421 = cat(UInt<13>("h00"), _T_2420) @[Cat.scala 29:58] + node _T_2422 = bits(io.csr_pkt.csr_dcsr, 0, 0) @[el2_dec_tlu_ctl.scala 2604:25] + node _T_2423 = bits(io.dcsr, 15, 2) @[el2_dec_tlu_ctl.scala 2604:73] + node _T_2424 = cat(UInt<16>("h04000"), _T_2423) @[Cat.scala 29:58] + node _T_2425 = cat(_T_2424, UInt<2>("h03")) @[Cat.scala 29:58] + node _T_2426 = bits(io.csr_pkt.csr_dpc, 0, 0) @[el2_dec_tlu_ctl.scala 2605:24] + node _T_2427 = cat(io.dpc, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2428 = bits(io.csr_pkt.csr_dicad0, 0, 0) @[el2_dec_tlu_ctl.scala 2606:27] + node _T_2429 = bits(dicad0, 31, 0) @[el2_dec_tlu_ctl.scala 2606:52] + node _T_2430 = bits(io.csr_pkt.csr_dicad0h, 0, 0) @[el2_dec_tlu_ctl.scala 2607:28] + node _T_2431 = bits(dicad0h, 31, 0) @[el2_dec_tlu_ctl.scala 2607:53] + node _T_2432 = bits(io.csr_pkt.csr_dicad1, 0, 0) @[el2_dec_tlu_ctl.scala 2608:27] + node _T_2433 = bits(dicad1, 31, 0) @[el2_dec_tlu_ctl.scala 2608:52] + node _T_2434 = bits(io.csr_pkt.csr_dicawics, 0, 0) @[el2_dec_tlu_ctl.scala 2609:29] + node _T_2435 = bits(dicawics, 16, 16) @[el2_dec_tlu_ctl.scala 2609:68] + node _T_2436 = bits(dicawics, 15, 14) @[el2_dec_tlu_ctl.scala 2609:92] + node _T_2437 = bits(dicawics, 13, 0) @[el2_dec_tlu_ctl.scala 2609:119] + node _T_2438 = cat(UInt<3>("h00"), _T_2437) @[Cat.scala 29:58] + node _T_2439 = cat(_T_2438, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2440 = cat(UInt<2>("h00"), _T_2436) @[Cat.scala 29:58] + node _T_2441 = cat(UInt<7>("h00"), _T_2435) @[Cat.scala 29:58] + node _T_2442 = cat(_T_2441, _T_2440) @[Cat.scala 29:58] + node _T_2443 = cat(_T_2442, _T_2439) @[Cat.scala 29:58] + node _T_2444 = bits(io.csr_pkt.csr_mtsel, 0, 0) @[el2_dec_tlu_ctl.scala 2610:26] + node _T_2445 = bits(mtsel, 1, 0) @[el2_dec_tlu_ctl.scala 2610:66] + node _T_2446 = cat(UInt<30>("h00"), _T_2445) @[Cat.scala 29:58] + node _T_2447 = bits(io.csr_pkt.csr_mtdata1, 0, 0) @[el2_dec_tlu_ctl.scala 2611:28] + node _T_2448 = bits(mtdata1_tsel_out, 31, 0) @[el2_dec_tlu_ctl.scala 2611:62] + node _T_2449 = bits(io.csr_pkt.csr_mtdata2, 0, 0) @[el2_dec_tlu_ctl.scala 2612:28] + node _T_2450 = bits(mtdata2_tsel_out, 31, 0) @[el2_dec_tlu_ctl.scala 2612:62] + node _T_2451 = bits(io.csr_pkt.csr_micect, 0, 0) @[el2_dec_tlu_ctl.scala 2613:27] + node _T_2452 = bits(micect, 31, 0) @[el2_dec_tlu_ctl.scala 2613:52] + node _T_2453 = bits(io.csr_pkt.csr_miccmect, 0, 0) @[el2_dec_tlu_ctl.scala 2614:29] + node _T_2454 = bits(miccmect, 31, 0) @[el2_dec_tlu_ctl.scala 2614:54] + node _T_2455 = bits(io.csr_pkt.csr_mdccmect, 0, 0) @[el2_dec_tlu_ctl.scala 2615:29] + node _T_2456 = bits(mdccmect, 31, 0) @[el2_dec_tlu_ctl.scala 2615:54] + node _T_2457 = bits(io.csr_pkt.csr_mhpmc3, 0, 0) @[el2_dec_tlu_ctl.scala 2616:27] + node _T_2458 = bits(mhpmc3, 31, 0) @[el2_dec_tlu_ctl.scala 2616:52] + node _T_2459 = bits(io.csr_pkt.csr_mhpmc4, 0, 0) @[el2_dec_tlu_ctl.scala 2617:27] + node _T_2460 = bits(mhpmc4, 31, 0) @[el2_dec_tlu_ctl.scala 2617:52] + node _T_2461 = bits(io.csr_pkt.csr_mhpmc5, 0, 0) @[el2_dec_tlu_ctl.scala 2618:27] + node _T_2462 = bits(mhpmc5, 31, 0) @[el2_dec_tlu_ctl.scala 2618:52] + node _T_2463 = bits(io.csr_pkt.csr_mhpmc6, 0, 0) @[el2_dec_tlu_ctl.scala 2619:27] + node _T_2464 = bits(mhpmc6, 31, 0) @[el2_dec_tlu_ctl.scala 2619:52] + node _T_2465 = bits(io.csr_pkt.csr_mhpmc3h, 0, 0) @[el2_dec_tlu_ctl.scala 2620:28] + node _T_2466 = bits(mhpmc3h, 31, 0) @[el2_dec_tlu_ctl.scala 2620:53] + node _T_2467 = bits(io.csr_pkt.csr_mhpmc4h, 0, 0) @[el2_dec_tlu_ctl.scala 2621:28] + node _T_2468 = bits(mhpmc4h, 31, 0) @[el2_dec_tlu_ctl.scala 2621:53] + node _T_2469 = bits(io.csr_pkt.csr_mhpmc5h, 0, 0) @[el2_dec_tlu_ctl.scala 2622:28] + node _T_2470 = bits(mhpmc5h, 31, 0) @[el2_dec_tlu_ctl.scala 2622:53] + node _T_2471 = bits(io.csr_pkt.csr_mhpmc6h, 0, 0) @[el2_dec_tlu_ctl.scala 2623:28] + node _T_2472 = bits(mhpmc6h, 31, 0) @[el2_dec_tlu_ctl.scala 2623:53] + node _T_2473 = bits(io.csr_pkt.csr_mfdht, 0, 0) @[el2_dec_tlu_ctl.scala 2624:26] + node _T_2474 = bits(mfdht, 5, 0) @[el2_dec_tlu_ctl.scala 2624:66] + node _T_2475 = cat(UInt<26>("h00"), _T_2474) @[Cat.scala 29:58] + node _T_2476 = bits(io.csr_pkt.csr_mfdhs, 0, 0) @[el2_dec_tlu_ctl.scala 2625:26] + node _T_2477 = bits(mfdhs, 1, 0) @[el2_dec_tlu_ctl.scala 2625:66] + node _T_2478 = cat(UInt<30>("h00"), _T_2477) @[Cat.scala 29:58] + node _T_2479 = bits(io.csr_pkt.csr_mhpme3, 0, 0) @[el2_dec_tlu_ctl.scala 2626:27] + node _T_2480 = bits(mhpme3, 9, 0) @[el2_dec_tlu_ctl.scala 2626:67] + node _T_2481 = cat(UInt<22>("h00"), _T_2480) @[Cat.scala 29:58] + node _T_2482 = bits(io.csr_pkt.csr_mhpme4, 0, 0) @[el2_dec_tlu_ctl.scala 2627:27] + node _T_2483 = bits(mhpme4, 9, 0) @[el2_dec_tlu_ctl.scala 2627:67] + node _T_2484 = cat(UInt<22>("h00"), _T_2483) @[Cat.scala 29:58] + node _T_2485 = bits(io.csr_pkt.csr_mhpme5, 0, 0) @[el2_dec_tlu_ctl.scala 2628:27] + node _T_2486 = bits(mhpme5, 9, 0) @[el2_dec_tlu_ctl.scala 2628:66] + node _T_2487 = cat(UInt<22>("h00"), _T_2486) @[Cat.scala 29:58] + node _T_2488 = bits(io.csr_pkt.csr_mhpme6, 0, 0) @[el2_dec_tlu_ctl.scala 2629:27] + node _T_2489 = bits(mhpme6, 9, 0) @[el2_dec_tlu_ctl.scala 2629:66] + node _T_2490 = cat(UInt<22>("h00"), _T_2489) @[Cat.scala 29:58] + node _T_2491 = bits(io.csr_pkt.csr_mcountinhibit, 0, 0) @[el2_dec_tlu_ctl.scala 2630:34] + node _T_2492 = bits(mcountinhibit, 6, 0) @[el2_dec_tlu_ctl.scala 2630:74] + node _T_2493 = cat(UInt<25>("h00"), _T_2492) @[Cat.scala 29:58] + node _T_2494 = bits(io.csr_pkt.csr_mpmc, 0, 0) @[el2_dec_tlu_ctl.scala 2631:25] + node _T_2495 = cat(UInt<30>("h00"), mpmc) @[Cat.scala 29:58] + node _T_2496 = cat(_T_2495, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2497 = bits(io.dec_timer_read_d, 0, 0) @[el2_dec_tlu_ctl.scala 2632:25] + node _T_2498 = bits(io.dec_timer_rddata_d, 31, 0) @[el2_dec_tlu_ctl.scala 2632:64] + node _T_2499 = mux(_T_2333, UInt<32>("h040001104"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2500 = mux(_T_2334, UInt<32>("h045"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2501 = mux(_T_2335, UInt<32>("h010"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2502 = mux(_T_2336, UInt<32>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2503 = mux(_T_2337, _T_2338, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2504 = mux(_T_2339, _T_2347, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2505 = mux(_T_2348, _T_2352, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2506 = mux(_T_2353, _T_2365, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2507 = mux(_T_2366, _T_2378, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2508 = mux(_T_2379, _T_2380, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2509 = mux(_T_2381, _T_2382, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2510 = mux(_T_2383, _T_2384, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2511 = mux(_T_2385, _T_2386, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2512 = mux(_T_2387, _T_2388, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2513 = mux(_T_2389, _T_2390, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2514 = mux(_T_2391, _T_2392, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2515 = mux(_T_2393, _T_2395, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2516 = mux(_T_2396, _T_2397, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2517 = mux(_T_2398, _T_2399, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2518 = mux(_T_2400, _T_2401, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2519 = mux(_T_2402, _T_2403, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2520 = mux(_T_2404, _T_2406, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2521 = mux(_T_2407, _T_2409, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2522 = mux(_T_2410, _T_2412, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2523 = mux(_T_2413, _T_2415, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2524 = mux(_T_2416, _T_2418, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2525 = mux(_T_2419, _T_2421, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2526 = mux(_T_2422, _T_2425, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2527 = mux(_T_2426, _T_2427, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2528 = mux(_T_2428, _T_2429, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2529 = mux(_T_2430, _T_2431, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2530 = mux(_T_2432, _T_2433, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2531 = mux(_T_2434, _T_2443, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2532 = mux(_T_2444, _T_2446, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2533 = mux(_T_2447, _T_2448, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2534 = mux(_T_2449, _T_2450, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2535 = mux(_T_2451, _T_2452, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2536 = mux(_T_2453, _T_2454, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2537 = mux(_T_2455, _T_2456, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2538 = mux(_T_2457, _T_2458, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2539 = mux(_T_2459, _T_2460, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2540 = mux(_T_2461, _T_2462, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2541 = mux(_T_2463, _T_2464, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2542 = mux(_T_2465, _T_2466, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2543 = mux(_T_2467, _T_2468, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2544 = mux(_T_2469, _T_2470, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2545 = mux(_T_2471, _T_2472, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2546 = mux(_T_2473, _T_2475, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2547 = mux(_T_2476, _T_2478, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2548 = mux(_T_2479, _T_2481, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2549 = mux(_T_2482, _T_2484, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2550 = mux(_T_2485, _T_2487, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2551 = mux(_T_2488, _T_2490, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2552 = mux(_T_2491, _T_2493, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2553 = mux(_T_2494, _T_2496, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2554 = mux(_T_2497, _T_2498, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2555 = or(_T_2499, _T_2500) @[Mux.scala 27:72] + node _T_2556 = or(_T_2555, _T_2501) @[Mux.scala 27:72] + node _T_2557 = or(_T_2556, _T_2502) @[Mux.scala 27:72] + node _T_2558 = or(_T_2557, _T_2503) @[Mux.scala 27:72] + node _T_2559 = or(_T_2558, _T_2504) @[Mux.scala 27:72] + node _T_2560 = or(_T_2559, _T_2505) @[Mux.scala 27:72] + node _T_2561 = or(_T_2560, _T_2506) @[Mux.scala 27:72] + node _T_2562 = or(_T_2561, _T_2507) @[Mux.scala 27:72] + node _T_2563 = or(_T_2562, _T_2508) @[Mux.scala 27:72] + node _T_2564 = or(_T_2563, _T_2509) @[Mux.scala 27:72] + node _T_2565 = or(_T_2564, _T_2510) @[Mux.scala 27:72] + node _T_2566 = or(_T_2565, _T_2511) @[Mux.scala 27:72] + node _T_2567 = or(_T_2566, _T_2512) @[Mux.scala 27:72] + node _T_2568 = or(_T_2567, _T_2513) @[Mux.scala 27:72] + node _T_2569 = or(_T_2568, _T_2514) @[Mux.scala 27:72] + node _T_2570 = or(_T_2569, _T_2515) @[Mux.scala 27:72] + node _T_2571 = or(_T_2570, _T_2516) @[Mux.scala 27:72] + node _T_2572 = or(_T_2571, _T_2517) @[Mux.scala 27:72] + node _T_2573 = or(_T_2572, _T_2518) @[Mux.scala 27:72] + node _T_2574 = or(_T_2573, _T_2519) @[Mux.scala 27:72] + node _T_2575 = or(_T_2574, _T_2520) @[Mux.scala 27:72] + node _T_2576 = or(_T_2575, _T_2521) @[Mux.scala 27:72] + node _T_2577 = or(_T_2576, _T_2522) @[Mux.scala 27:72] + node _T_2578 = or(_T_2577, _T_2523) @[Mux.scala 27:72] + node _T_2579 = or(_T_2578, _T_2524) @[Mux.scala 27:72] + node _T_2580 = or(_T_2579, _T_2525) @[Mux.scala 27:72] + node _T_2581 = or(_T_2580, _T_2526) @[Mux.scala 27:72] + node _T_2582 = or(_T_2581, _T_2527) @[Mux.scala 27:72] + node _T_2583 = or(_T_2582, _T_2528) @[Mux.scala 27:72] + node _T_2584 = or(_T_2583, _T_2529) @[Mux.scala 27:72] + node _T_2585 = or(_T_2584, _T_2530) @[Mux.scala 27:72] + node _T_2586 = or(_T_2585, _T_2531) @[Mux.scala 27:72] + node _T_2587 = or(_T_2586, _T_2532) @[Mux.scala 27:72] + node _T_2588 = or(_T_2587, _T_2533) @[Mux.scala 27:72] + node _T_2589 = or(_T_2588, _T_2534) @[Mux.scala 27:72] + node _T_2590 = or(_T_2589, _T_2535) @[Mux.scala 27:72] + node _T_2591 = or(_T_2590, _T_2536) @[Mux.scala 27:72] + node _T_2592 = or(_T_2591, _T_2537) @[Mux.scala 27:72] + node _T_2593 = or(_T_2592, _T_2538) @[Mux.scala 27:72] + node _T_2594 = or(_T_2593, _T_2539) @[Mux.scala 27:72] + node _T_2595 = or(_T_2594, _T_2540) @[Mux.scala 27:72] + node _T_2596 = or(_T_2595, _T_2541) @[Mux.scala 27:72] + node _T_2597 = or(_T_2596, _T_2542) @[Mux.scala 27:72] + node _T_2598 = or(_T_2597, _T_2543) @[Mux.scala 27:72] + node _T_2599 = or(_T_2598, _T_2544) @[Mux.scala 27:72] + node _T_2600 = or(_T_2599, _T_2545) @[Mux.scala 27:72] + node _T_2601 = or(_T_2600, _T_2546) @[Mux.scala 27:72] + node _T_2602 = or(_T_2601, _T_2547) @[Mux.scala 27:72] + node _T_2603 = or(_T_2602, _T_2548) @[Mux.scala 27:72] + node _T_2604 = or(_T_2603, _T_2549) @[Mux.scala 27:72] + node _T_2605 = or(_T_2604, _T_2550) @[Mux.scala 27:72] + node _T_2606 = or(_T_2605, _T_2551) @[Mux.scala 27:72] + node _T_2607 = or(_T_2606, _T_2552) @[Mux.scala 27:72] + node _T_2608 = or(_T_2607, _T_2553) @[Mux.scala 27:72] + node _T_2609 = or(_T_2608, _T_2554) @[Mux.scala 27:72] + wire _T_2610 : UInt @[Mux.scala 27:72] + _T_2610 <= _T_2609 @[Mux.scala 27:72] + io.dec_csr_rddata_d <= _T_2610 @[el2_dec_tlu_ctl.scala 2576:22] + + module el2_dec_decode_csr_read : + input clock : Clock + input reset : AsyncReset + output io : {flip dec_csr_rdaddr_d : UInt<12>, csr_pkt : {csr_misa : UInt<1>, csr_mvendorid : UInt<1>, csr_marchid : UInt<1>, csr_mimpid : UInt<1>, csr_mhartid : UInt<1>, csr_mstatus : UInt<1>, csr_mtvec : UInt<1>, csr_mip : UInt<1>, csr_mie : UInt<1>, csr_mcyclel : UInt<1>, csr_mcycleh : UInt<1>, csr_minstretl : UInt<1>, csr_minstreth : UInt<1>, csr_mscratch : UInt<1>, csr_mepc : UInt<1>, csr_mcause : UInt<1>, csr_mscause : UInt<1>, csr_mtval : UInt<1>, csr_mrac : UInt<1>, csr_dmst : UInt<1>, csr_mdseac : UInt<1>, csr_meihap : UInt<1>, csr_meivt : UInt<1>, csr_meipt : UInt<1>, csr_meicurpl : UInt<1>, csr_meicidpl : UInt<1>, csr_dcsr : UInt<1>, csr_mcgc : UInt<1>, csr_mfdc : UInt<1>, csr_dpc : UInt<1>, csr_mtsel : UInt<1>, csr_mtdata1 : UInt<1>, csr_mtdata2 : UInt<1>, csr_mhpmc3 : UInt<1>, csr_mhpmc4 : UInt<1>, csr_mhpmc5 : UInt<1>, csr_mhpmc6 : UInt<1>, csr_mhpmc3h : UInt<1>, csr_mhpmc4h : UInt<1>, csr_mhpmc5h : UInt<1>, csr_mhpmc6h : UInt<1>, csr_mhpme3 : UInt<1>, csr_mhpme4 : UInt<1>, csr_mhpme5 : UInt<1>, csr_mhpme6 : UInt<1>, csr_mcountinhibit : UInt<1>, csr_mitctl0 : UInt<1>, csr_mitctl1 : UInt<1>, csr_mitb0 : UInt<1>, csr_mitb1 : UInt<1>, csr_mitcnt0 : UInt<1>, csr_mitcnt1 : UInt<1>, csr_mpmc : UInt<1>, csr_mcpc : UInt<1>, csr_meicpct : UInt<1>, csr_mdeau : UInt<1>, csr_micect : UInt<1>, csr_miccmect : UInt<1>, csr_mdccmect : UInt<1>, csr_mfdht : UInt<1>, csr_mfdhs : UInt<1>, csr_dicawics : UInt<1>, csr_dicad0h : UInt<1>, csr_dicad0 : UInt<1>, csr_dicad1 : UInt<1>, csr_dicago : UInt<1>, presync : UInt<1>, postsync : UInt<1>, legal : UInt<1>}} + + node _T = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1 = eq(_T, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_2 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_3 = eq(_T_2, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_4 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_5 = eq(_T_4, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_6 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_7 = eq(_T_6, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_8 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_9 = and(_T_1, _T_3) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_10 = and(_T_9, _T_5) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_11 = and(_T_10, _T_7) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_12 = and(_T_11, _T_8) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_misa <= _T_12 @[el2_dec_tlu_ctl.scala 2650:49] + node _T_13 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_14 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_15 = eq(_T_14, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_16 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_17 = eq(_T_16, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_18 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_19 = and(_T_13, _T_15) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_20 = and(_T_19, _T_17) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_21 = and(_T_20, _T_18) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mvendorid <= _T_21 @[el2_dec_tlu_ctl.scala 2651:49] + node _T_22 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_23 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_24 = eq(_T_23, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_25 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_26 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_27 = eq(_T_26, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_28 = and(_T_22, _T_24) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_29 = and(_T_28, _T_25) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_30 = and(_T_29, _T_27) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_marchid <= _T_30 @[el2_dec_tlu_ctl.scala 2652:57] + node _T_31 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_32 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_33 = eq(_T_32, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_34 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_35 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_36 = and(_T_31, _T_33) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_37 = and(_T_36, _T_34) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_38 = and(_T_37, _T_35) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mimpid <= _T_38 @[el2_dec_tlu_ctl.scala 2653:57] + node _T_39 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_40 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_41 = eq(_T_40, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_42 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_43 = and(_T_39, _T_41) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_44 = and(_T_43, _T_42) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mhartid <= _T_44 @[el2_dec_tlu_ctl.scala 2654:57] + node _T_45 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_46 = eq(_T_45, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_47 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_48 = eq(_T_47, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_49 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_50 = eq(_T_49, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_51 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_52 = eq(_T_51, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_53 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_54 = eq(_T_53, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_55 = and(_T_46, _T_48) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_56 = and(_T_55, _T_50) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_57 = and(_T_56, _T_52) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_58 = and(_T_57, _T_54) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mstatus <= _T_58 @[el2_dec_tlu_ctl.scala 2655:57] + node _T_59 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_60 = eq(_T_59, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_61 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_62 = eq(_T_61, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_63 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_64 = eq(_T_63, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_65 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_66 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_67 = and(_T_60, _T_62) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_68 = and(_T_67, _T_64) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_69 = and(_T_68, _T_65) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_70 = and(_T_69, _T_66) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mtvec <= _T_70 @[el2_dec_tlu_ctl.scala 2656:49] + node _T_71 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_72 = eq(_T_71, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_73 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_74 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_75 = and(_T_72, _T_73) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_76 = and(_T_75, _T_74) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mip <= _T_76 @[el2_dec_tlu_ctl.scala 2657:57] + node _T_77 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_78 = eq(_T_77, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_79 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_80 = eq(_T_79, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_81 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_82 = eq(_T_81, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_83 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_84 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_85 = eq(_T_84, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_86 = and(_T_78, _T_80) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_87 = and(_T_86, _T_82) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_88 = and(_T_87, _T_83) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_89 = and(_T_88, _T_85) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mie <= _T_89 @[el2_dec_tlu_ctl.scala 2658:57] + node _T_90 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_91 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_92 = eq(_T_91, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_93 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_94 = eq(_T_93, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_95 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_96 = eq(_T_95, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_97 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_98 = eq(_T_97, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_99 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_100 = eq(_T_99, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_101 = and(_T_90, _T_92) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_102 = and(_T_101, _T_94) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_103 = and(_T_102, _T_96) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_104 = and(_T_103, _T_98) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_105 = and(_T_104, _T_100) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mcyclel <= _T_105 @[el2_dec_tlu_ctl.scala 2659:57] + node _T_106 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_107 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_108 = eq(_T_107, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_109 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_110 = eq(_T_109, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_111 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_112 = eq(_T_111, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_113 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_114 = eq(_T_113, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_115 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_116 = eq(_T_115, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_117 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_118 = eq(_T_117, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_119 = and(_T_106, _T_108) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_120 = and(_T_119, _T_110) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_121 = and(_T_120, _T_112) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_122 = and(_T_121, _T_114) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_123 = and(_T_122, _T_116) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_124 = and(_T_123, _T_118) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mcycleh <= _T_124 @[el2_dec_tlu_ctl.scala 2660:57] + node _T_125 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_126 = eq(_T_125, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_127 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_128 = eq(_T_127, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_129 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_130 = eq(_T_129, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_131 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_132 = eq(_T_131, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_133 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_134 = eq(_T_133, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_135 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_136 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_137 = eq(_T_136, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_138 = and(_T_126, _T_128) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_139 = and(_T_138, _T_130) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_140 = and(_T_139, _T_132) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_141 = and(_T_140, _T_134) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_142 = and(_T_141, _T_135) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_143 = and(_T_142, _T_137) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_minstretl <= _T_143 @[el2_dec_tlu_ctl.scala 2661:49] + node _T_144 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_145 = eq(_T_144, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_146 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_147 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_148 = eq(_T_147, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_149 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_150 = eq(_T_149, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_151 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_152 = eq(_T_151, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_153 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_154 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_155 = eq(_T_154, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_156 = and(_T_145, _T_146) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_157 = and(_T_156, _T_148) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_158 = and(_T_157, _T_150) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_159 = and(_T_158, _T_152) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_160 = and(_T_159, _T_153) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_161 = and(_T_160, _T_155) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_minstreth <= _T_161 @[el2_dec_tlu_ctl.scala 2662:49] + node _T_162 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_163 = eq(_T_162, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_164 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_165 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_166 = eq(_T_165, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_167 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_168 = eq(_T_167, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_169 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_170 = eq(_T_169, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_171 = and(_T_163, _T_164) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_172 = and(_T_171, _T_166) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_173 = and(_T_172, _T_168) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_174 = and(_T_173, _T_170) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mscratch <= _T_174 @[el2_dec_tlu_ctl.scala 2663:49] + node _T_175 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_176 = eq(_T_175, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_177 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_178 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_179 = eq(_T_178, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_180 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_181 = and(_T_176, _T_177) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_182 = and(_T_181, _T_179) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_183 = and(_T_182, _T_180) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mepc <= _T_183 @[el2_dec_tlu_ctl.scala 2664:49] + node _T_184 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_185 = eq(_T_184, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_186 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_187 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_188 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_189 = eq(_T_188, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_190 = and(_T_185, _T_186) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_191 = and(_T_190, _T_187) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_192 = and(_T_191, _T_189) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mcause <= _T_192 @[el2_dec_tlu_ctl.scala 2665:57] + node _T_193 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_194 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_195 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_196 = and(_T_193, _T_194) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_197 = and(_T_196, _T_195) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mscause <= _T_197 @[el2_dec_tlu_ctl.scala 2666:57] + node _T_198 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_199 = eq(_T_198, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_200 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_201 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_202 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_203 = and(_T_199, _T_200) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_204 = and(_T_203, _T_201) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_205 = and(_T_204, _T_202) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mtval <= _T_205 @[el2_dec_tlu_ctl.scala 2667:49] + node _T_206 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_207 = eq(_T_206, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_208 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_209 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_210 = eq(_T_209, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_211 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_212 = eq(_T_211, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_213 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_214 = eq(_T_213, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_215 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_216 = eq(_T_215, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_217 = and(_T_207, _T_208) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_218 = and(_T_217, _T_210) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_219 = and(_T_218, _T_212) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_220 = and(_T_219, _T_214) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_221 = and(_T_220, _T_216) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mrac <= _T_221 @[el2_dec_tlu_ctl.scala 2668:49] + node _T_222 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_223 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_224 = eq(_T_223, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_225 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_226 = eq(_T_225, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_227 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_228 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_229 = eq(_T_228, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_230 = and(_T_222, _T_224) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_231 = and(_T_230, _T_226) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_232 = and(_T_231, _T_227) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_233 = and(_T_232, _T_229) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_dmst <= _T_233 @[el2_dec_tlu_ctl.scala 2669:49] + node _T_234 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_235 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_236 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_237 = eq(_T_236, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_238 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_239 = eq(_T_238, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_240 = and(_T_234, _T_235) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_241 = and(_T_240, _T_237) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_242 = and(_T_241, _T_239) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mdseac <= _T_242 @[el2_dec_tlu_ctl.scala 2670:57] + node _T_243 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_244 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_245 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_246 = and(_T_243, _T_244) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_247 = and(_T_246, _T_245) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_meihap <= _T_247 @[el2_dec_tlu_ctl.scala 2671:57] + node _T_248 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_249 = eq(_T_248, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_250 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_251 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_252 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_253 = eq(_T_252, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_254 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_255 = eq(_T_254, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_256 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_257 = eq(_T_256, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_258 = and(_T_249, _T_250) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_259 = and(_T_258, _T_251) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_260 = and(_T_259, _T_253) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_261 = and(_T_260, _T_255) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_262 = and(_T_261, _T_257) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_meivt <= _T_262 @[el2_dec_tlu_ctl.scala 2672:49] + node _T_263 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_264 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_265 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_266 = eq(_T_265, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_267 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_268 = and(_T_263, _T_264) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_269 = and(_T_268, _T_266) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_270 = and(_T_269, _T_267) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_meipt <= _T_270 @[el2_dec_tlu_ctl.scala 2673:49] + node _T_271 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_272 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_273 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_274 = and(_T_271, _T_272) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_275 = and(_T_274, _T_273) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_meicurpl <= _T_275 @[el2_dec_tlu_ctl.scala 2674:49] + node _T_276 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_277 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_278 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_279 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_280 = and(_T_276, _T_277) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_281 = and(_T_280, _T_278) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_282 = and(_T_281, _T_279) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_meicidpl <= _T_282 @[el2_dec_tlu_ctl.scala 2675:49] + node _T_283 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_284 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_285 = eq(_T_284, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_286 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_287 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_288 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_289 = eq(_T_288, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_290 = and(_T_283, _T_285) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_291 = and(_T_290, _T_286) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_292 = and(_T_291, _T_287) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_293 = and(_T_292, _T_289) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_dcsr <= _T_293 @[el2_dec_tlu_ctl.scala 2676:49] + node _T_294 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_295 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_296 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_297 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_298 = eq(_T_297, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_299 = and(_T_294, _T_295) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_300 = and(_T_299, _T_296) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_301 = and(_T_300, _T_298) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mcgc <= _T_301 @[el2_dec_tlu_ctl.scala 2677:49] + node _T_302 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_303 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_304 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_305 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_306 = eq(_T_305, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_307 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_308 = and(_T_302, _T_303) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_309 = and(_T_308, _T_304) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_310 = and(_T_309, _T_306) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_311 = and(_T_310, _T_307) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mfdc <= _T_311 @[el2_dec_tlu_ctl.scala 2678:49] + node _T_312 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_313 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_314 = eq(_T_313, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_315 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_316 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_317 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_318 = and(_T_312, _T_314) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_319 = and(_T_318, _T_315) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_320 = and(_T_319, _T_316) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_321 = and(_T_320, _T_317) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_dpc <= _T_321 @[el2_dec_tlu_ctl.scala 2679:57] + node _T_322 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_323 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_324 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_325 = eq(_T_324, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_326 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_327 = eq(_T_326, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_328 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_329 = eq(_T_328, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_330 = and(_T_322, _T_323) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_331 = and(_T_330, _T_325) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_332 = and(_T_331, _T_327) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_333 = and(_T_332, _T_329) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mtsel <= _T_333 @[el2_dec_tlu_ctl.scala 2680:49] + node _T_334 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_335 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_336 = eq(_T_335, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_337 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_338 = eq(_T_337, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_339 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_340 = and(_T_334, _T_336) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_341 = and(_T_340, _T_338) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_342 = and(_T_341, _T_339) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mtdata1 <= _T_342 @[el2_dec_tlu_ctl.scala 2681:57] + node _T_343 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_344 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_345 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_346 = eq(_T_345, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_347 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_348 = and(_T_343, _T_344) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_349 = and(_T_348, _T_346) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_350 = and(_T_349, _T_347) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mtdata2 <= _T_350 @[el2_dec_tlu_ctl.scala 2682:57] + node _T_351 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_352 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_353 = eq(_T_352, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_354 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_355 = eq(_T_354, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_356 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_357 = eq(_T_356, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_358 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_359 = eq(_T_358, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_360 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_361 = and(_T_351, _T_353) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_362 = and(_T_361, _T_355) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_363 = and(_T_362, _T_357) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_364 = and(_T_363, _T_359) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_365 = and(_T_364, _T_360) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mhpmc3 <= _T_365 @[el2_dec_tlu_ctl.scala 2683:57] + node _T_366 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_367 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_368 = eq(_T_367, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_369 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_370 = eq(_T_369, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_371 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_372 = eq(_T_371, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_373 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_374 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_375 = eq(_T_374, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_376 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_377 = eq(_T_376, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_378 = and(_T_366, _T_368) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_379 = and(_T_378, _T_370) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_380 = and(_T_379, _T_372) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_381 = and(_T_380, _T_373) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_382 = and(_T_381, _T_375) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_383 = and(_T_382, _T_377) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mhpmc4 <= _T_383 @[el2_dec_tlu_ctl.scala 2684:57] + node _T_384 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_385 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_386 = eq(_T_385, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_387 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_388 = eq(_T_387, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_389 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_390 = eq(_T_389, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_391 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_392 = eq(_T_391, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_393 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_394 = and(_T_384, _T_386) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_395 = and(_T_394, _T_388) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_396 = and(_T_395, _T_390) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_397 = and(_T_396, _T_392) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_398 = and(_T_397, _T_393) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mhpmc5 <= _T_398 @[el2_dec_tlu_ctl.scala 2685:57] + node _T_399 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_400 = eq(_T_399, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_401 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_402 = eq(_T_401, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_403 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_404 = eq(_T_403, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_405 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_406 = eq(_T_405, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_407 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_408 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_409 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_410 = eq(_T_409, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_411 = and(_T_400, _T_402) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_412 = and(_T_411, _T_404) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_413 = and(_T_412, _T_406) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_414 = and(_T_413, _T_407) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_415 = and(_T_414, _T_408) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_416 = and(_T_415, _T_410) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mhpmc6 <= _T_416 @[el2_dec_tlu_ctl.scala 2686:57] + node _T_417 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_418 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_419 = eq(_T_418, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_420 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_421 = eq(_T_420, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_422 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_423 = eq(_T_422, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_424 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_425 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_426 = and(_T_417, _T_419) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_427 = and(_T_426, _T_421) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_428 = and(_T_427, _T_423) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_429 = and(_T_428, _T_424) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_430 = and(_T_429, _T_425) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mhpmc3h <= _T_430 @[el2_dec_tlu_ctl.scala 2687:57] + node _T_431 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_432 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_433 = eq(_T_432, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_434 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_435 = eq(_T_434, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_436 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_437 = eq(_T_436, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_438 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_439 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_440 = eq(_T_439, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_441 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_442 = eq(_T_441, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_443 = and(_T_431, _T_433) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_444 = and(_T_443, _T_435) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_445 = and(_T_444, _T_437) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_446 = and(_T_445, _T_438) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_447 = and(_T_446, _T_440) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_448 = and(_T_447, _T_442) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mhpmc4h <= _T_448 @[el2_dec_tlu_ctl.scala 2688:57] + node _T_449 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_450 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_451 = eq(_T_450, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_452 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_453 = eq(_T_452, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_454 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_455 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_456 = eq(_T_455, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_457 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_458 = and(_T_449, _T_451) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_459 = and(_T_458, _T_453) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_460 = and(_T_459, _T_454) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_461 = and(_T_460, _T_456) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_462 = and(_T_461, _T_457) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mhpmc5h <= _T_462 @[el2_dec_tlu_ctl.scala 2689:57] + node _T_463 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_464 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_465 = eq(_T_464, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_466 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_467 = eq(_T_466, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_468 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_469 = eq(_T_468, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_470 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_471 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_472 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_473 = eq(_T_472, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_474 = and(_T_463, _T_465) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_475 = and(_T_474, _T_467) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_476 = and(_T_475, _T_469) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_477 = and(_T_476, _T_470) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_478 = and(_T_477, _T_471) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_479 = and(_T_478, _T_473) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mhpmc6h <= _T_479 @[el2_dec_tlu_ctl.scala 2690:57] + node _T_480 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_481 = eq(_T_480, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_482 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_483 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_484 = eq(_T_483, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_485 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_486 = eq(_T_485, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_487 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_488 = eq(_T_487, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_489 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_490 = and(_T_481, _T_482) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_491 = and(_T_490, _T_484) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_492 = and(_T_491, _T_486) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_493 = and(_T_492, _T_488) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_494 = and(_T_493, _T_489) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mhpme3 <= _T_494 @[el2_dec_tlu_ctl.scala 2691:57] + node _T_495 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_496 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_497 = eq(_T_496, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_498 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_499 = eq(_T_498, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_500 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_501 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_502 = eq(_T_501, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_503 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_504 = eq(_T_503, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_505 = and(_T_495, _T_497) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_506 = and(_T_505, _T_499) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_507 = and(_T_506, _T_500) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_508 = and(_T_507, _T_502) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_509 = and(_T_508, _T_504) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mhpme4 <= _T_509 @[el2_dec_tlu_ctl.scala 2692:57] + node _T_510 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_511 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_512 = eq(_T_511, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_513 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_514 = eq(_T_513, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_515 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_516 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_517 = eq(_T_516, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_518 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_519 = and(_T_510, _T_512) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_520 = and(_T_519, _T_514) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_521 = and(_T_520, _T_515) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_522 = and(_T_521, _T_517) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_523 = and(_T_522, _T_518) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mhpme5 <= _T_523 @[el2_dec_tlu_ctl.scala 2693:57] + node _T_524 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_525 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_526 = eq(_T_525, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_527 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_528 = eq(_T_527, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_529 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_530 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_531 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_532 = eq(_T_531, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_533 = and(_T_524, _T_526) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_534 = and(_T_533, _T_528) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_535 = and(_T_534, _T_529) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_536 = and(_T_535, _T_530) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_537 = and(_T_536, _T_532) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mhpme6 <= _T_537 @[el2_dec_tlu_ctl.scala 2694:57] + node _T_538 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_539 = eq(_T_538, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_540 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_541 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_542 = eq(_T_541, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_543 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_544 = eq(_T_543, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_545 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_546 = eq(_T_545, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_547 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_548 = eq(_T_547, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_549 = and(_T_539, _T_540) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_550 = and(_T_549, _T_542) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_551 = and(_T_550, _T_544) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_552 = and(_T_551, _T_546) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_553 = and(_T_552, _T_548) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mcountinhibit <= _T_553 @[el2_dec_tlu_ctl.scala 2695:41] + node _T_554 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_555 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_556 = eq(_T_555, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_557 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_558 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_559 = eq(_T_558, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_560 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_561 = eq(_T_560, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_562 = and(_T_554, _T_556) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_563 = and(_T_562, _T_557) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_564 = and(_T_563, _T_559) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_565 = and(_T_564, _T_561) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mitctl0 <= _T_565 @[el2_dec_tlu_ctl.scala 2696:57] + node _T_566 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_567 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_568 = eq(_T_567, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_569 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_570 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_571 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_572 = and(_T_566, _T_568) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_573 = and(_T_572, _T_569) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_574 = and(_T_573, _T_570) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_575 = and(_T_574, _T_571) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mitctl1 <= _T_575 @[el2_dec_tlu_ctl.scala 2697:57] + node _T_576 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_577 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_578 = eq(_T_577, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_579 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_580 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_581 = eq(_T_580, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_582 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_583 = and(_T_576, _T_578) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_584 = and(_T_583, _T_579) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_585 = and(_T_584, _T_581) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_586 = and(_T_585, _T_582) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mitb0 <= _T_586 @[el2_dec_tlu_ctl.scala 2698:49] + node _T_587 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_588 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_589 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_590 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_591 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_592 = eq(_T_591, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_593 = and(_T_587, _T_588) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_594 = and(_T_593, _T_589) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_595 = and(_T_594, _T_590) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_596 = and(_T_595, _T_592) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mitb1 <= _T_596 @[el2_dec_tlu_ctl.scala 2699:49] + node _T_597 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_598 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_599 = eq(_T_598, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_600 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_601 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_602 = eq(_T_601, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_603 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_604 = eq(_T_603, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_605 = and(_T_597, _T_599) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_606 = and(_T_605, _T_600) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_607 = and(_T_606, _T_602) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_608 = and(_T_607, _T_604) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mitcnt0 <= _T_608 @[el2_dec_tlu_ctl.scala 2700:57] + node _T_609 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_610 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_611 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_612 = eq(_T_611, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_613 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_614 = and(_T_609, _T_610) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_615 = and(_T_614, _T_612) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_616 = and(_T_615, _T_613) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mitcnt1 <= _T_616 @[el2_dec_tlu_ctl.scala 2701:57] + node _T_617 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_618 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_619 = eq(_T_618, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_620 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_621 = eq(_T_620, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_622 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_623 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_624 = and(_T_617, _T_619) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_625 = and(_T_624, _T_621) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_626 = and(_T_625, _T_622) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_627 = and(_T_626, _T_623) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mpmc <= _T_627 @[el2_dec_tlu_ctl.scala 2702:49] + node _T_628 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_629 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_630 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_631 = eq(_T_630, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_632 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_633 = eq(_T_632, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_634 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_635 = eq(_T_634, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_636 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_637 = and(_T_628, _T_629) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_638 = and(_T_637, _T_631) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_639 = and(_T_638, _T_633) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_640 = and(_T_639, _T_635) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_641 = and(_T_640, _T_636) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mcpc <= _T_641 @[el2_dec_tlu_ctl.scala 2703:49] + node _T_642 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_643 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_644 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_645 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_646 = eq(_T_645, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_647 = and(_T_642, _T_643) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_648 = and(_T_647, _T_644) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_649 = and(_T_648, _T_646) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_meicpct <= _T_649 @[el2_dec_tlu_ctl.scala 2704:57] + node _T_650 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_651 = eq(_T_650, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_652 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_653 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_654 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_655 = eq(_T_654, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_656 = and(_T_651, _T_652) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_657 = and(_T_656, _T_653) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_658 = and(_T_657, _T_655) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mdeau <= _T_658 @[el2_dec_tlu_ctl.scala 2705:49] + node _T_659 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_660 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_661 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_662 = eq(_T_661, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_663 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_664 = eq(_T_663, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_665 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_666 = eq(_T_665, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_667 = and(_T_659, _T_660) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_668 = and(_T_667, _T_662) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_669 = and(_T_668, _T_664) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_670 = and(_T_669, _T_666) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_micect <= _T_670 @[el2_dec_tlu_ctl.scala 2706:57] + node _T_671 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_672 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_673 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_674 = eq(_T_673, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_675 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_676 = and(_T_671, _T_672) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_677 = and(_T_676, _T_674) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_678 = and(_T_677, _T_675) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_miccmect <= _T_678 @[el2_dec_tlu_ctl.scala 2707:49] + node _T_679 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_680 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_681 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_682 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_683 = eq(_T_682, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_684 = and(_T_679, _T_680) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_685 = and(_T_684, _T_681) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_686 = and(_T_685, _T_683) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mdccmect <= _T_686 @[el2_dec_tlu_ctl.scala 2708:49] + node _T_687 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_688 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_689 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_690 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_691 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_692 = eq(_T_691, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_693 = and(_T_687, _T_688) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_694 = and(_T_693, _T_689) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_695 = and(_T_694, _T_690) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_696 = and(_T_695, _T_692) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mfdht <= _T_696 @[el2_dec_tlu_ctl.scala 2709:49] + node _T_697 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_698 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_699 = eq(_T_698, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_700 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_701 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_702 = and(_T_697, _T_699) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_703 = and(_T_702, _T_700) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_704 = and(_T_703, _T_701) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mfdhs <= _T_704 @[el2_dec_tlu_ctl.scala 2710:49] + node _T_705 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_706 = eq(_T_705, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_707 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_708 = eq(_T_707, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_709 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_710 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_711 = eq(_T_710, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_712 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_713 = eq(_T_712, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_714 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_715 = eq(_T_714, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_716 = and(_T_706, _T_708) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_717 = and(_T_716, _T_709) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_718 = and(_T_717, _T_711) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_719 = and(_T_718, _T_713) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_720 = and(_T_719, _T_715) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_dicawics <= _T_720 @[el2_dec_tlu_ctl.scala 2711:49] + node _T_721 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_722 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_723 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_724 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_725 = eq(_T_724, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_726 = and(_T_721, _T_722) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_727 = and(_T_726, _T_723) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_728 = and(_T_727, _T_725) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_dicad0h <= _T_728 @[el2_dec_tlu_ctl.scala 2712:57] + node _T_729 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_730 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_731 = eq(_T_730, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_732 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_733 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_734 = eq(_T_733, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_735 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_736 = and(_T_729, _T_731) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_737 = and(_T_736, _T_732) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_738 = and(_T_737, _T_734) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_739 = and(_T_738, _T_735) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_dicad0 <= _T_739 @[el2_dec_tlu_ctl.scala 2713:57] + node _T_740 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_741 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_742 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_743 = eq(_T_742, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_744 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_745 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_746 = eq(_T_745, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_747 = and(_T_740, _T_741) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_748 = and(_T_747, _T_743) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_749 = and(_T_748, _T_744) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_750 = and(_T_749, _T_746) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_dicad1 <= _T_750 @[el2_dec_tlu_ctl.scala 2714:57] + node _T_751 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_752 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_753 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_754 = eq(_T_753, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_755 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_756 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_757 = and(_T_751, _T_752) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_758 = and(_T_757, _T_754) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_759 = and(_T_758, _T_755) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_760 = and(_T_759, _T_756) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_dicago <= _T_760 @[el2_dec_tlu_ctl.scala 2715:57] + node _T_761 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_762 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_763 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_764 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_765 = eq(_T_764, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_766 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_767 = and(_T_761, _T_762) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_768 = and(_T_767, _T_763) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_769 = and(_T_768, _T_765) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_770 = and(_T_769, _T_766) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_771 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_772 = eq(_T_771, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_773 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_774 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_775 = eq(_T_774, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_776 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_777 = eq(_T_776, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_778 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_779 = eq(_T_778, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_780 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_781 = eq(_T_780, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_782 = and(_T_772, _T_773) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_783 = and(_T_782, _T_775) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_784 = and(_T_783, _T_777) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_785 = and(_T_784, _T_779) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_786 = and(_T_785, _T_781) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_787 = or(_T_770, _T_786) @[el2_dec_tlu_ctl.scala 2716:73] + node _T_788 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_789 = eq(_T_788, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_790 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_791 = eq(_T_790, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_792 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_793 = eq(_T_792, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_794 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_795 = eq(_T_794, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_796 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_797 = eq(_T_796, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_798 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_799 = and(_T_789, _T_791) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_800 = and(_T_799, _T_793) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_801 = and(_T_800, _T_795) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_802 = and(_T_801, _T_797) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_803 = and(_T_802, _T_798) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_804 = or(_T_787, _T_803) @[el2_dec_tlu_ctl.scala 2716:113] + node _T_805 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_806 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_807 = eq(_T_806, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_808 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_809 = eq(_T_808, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_810 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_811 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_812 = eq(_T_811, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_813 = and(_T_805, _T_807) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_814 = and(_T_813, _T_809) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_815 = and(_T_814, _T_810) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_816 = and(_T_815, _T_812) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_817 = or(_T_804, _T_816) @[el2_dec_tlu_ctl.scala 2716:147] + node _T_818 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_819 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_820 = eq(_T_819, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_821 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_822 = eq(_T_821, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_823 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_824 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_825 = eq(_T_824, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_826 = and(_T_818, _T_820) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_827 = and(_T_826, _T_822) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_828 = and(_T_827, _T_823) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_829 = and(_T_828, _T_825) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_830 = or(_T_817, _T_829) @[el2_dec_tlu_ctl.scala 2717:41] + node _T_831 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_832 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_833 = eq(_T_832, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_834 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_835 = eq(_T_834, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_836 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_837 = eq(_T_836, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_838 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_839 = eq(_T_838, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_840 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_841 = and(_T_831, _T_833) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_842 = and(_T_841, _T_835) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_843 = and(_T_842, _T_837) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_844 = and(_T_843, _T_839) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_845 = and(_T_844, _T_840) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_846 = or(_T_830, _T_845) @[el2_dec_tlu_ctl.scala 2717:81] + io.csr_pkt.presync <= _T_846 @[el2_dec_tlu_ctl.scala 2716:26] + node _T_847 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_848 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_849 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_850 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_851 = eq(_T_850, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_852 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_853 = and(_T_847, _T_848) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_854 = and(_T_853, _T_849) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_855 = and(_T_854, _T_851) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_856 = and(_T_855, _T_852) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_857 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_858 = eq(_T_857, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_859 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_860 = eq(_T_859, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_861 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_862 = eq(_T_861, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_863 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_864 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_865 = and(_T_858, _T_860) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_866 = and(_T_865, _T_862) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_867 = and(_T_866, _T_863) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_868 = and(_T_867, _T_864) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_869 = or(_T_856, _T_868) @[el2_dec_tlu_ctl.scala 2718:73] + node _T_870 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_871 = eq(_T_870, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_872 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_873 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_874 = eq(_T_873, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_875 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_876 = and(_T_871, _T_872) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_877 = and(_T_876, _T_874) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_878 = and(_T_877, _T_875) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_879 = or(_T_869, _T_878) @[el2_dec_tlu_ctl.scala 2718:113] + node _T_880 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_881 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_882 = eq(_T_881, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_883 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_884 = eq(_T_883, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_885 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_886 = and(_T_880, _T_882) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_887 = and(_T_886, _T_884) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_888 = and(_T_887, _T_885) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_889 = or(_T_879, _T_888) @[el2_dec_tlu_ctl.scala 2718:154] + node _T_890 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_891 = eq(_T_890, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_892 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_893 = eq(_T_892, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_894 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_895 = eq(_T_894, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_896 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_897 = eq(_T_896, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_898 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_899 = eq(_T_898, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_900 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_901 = eq(_T_900, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_902 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_903 = eq(_T_902, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_904 = and(_T_891, _T_893) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_905 = and(_T_904, _T_895) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_906 = and(_T_905, _T_897) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_907 = and(_T_906, _T_899) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_908 = and(_T_907, _T_901) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_909 = and(_T_908, _T_903) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_910 = or(_T_889, _T_909) @[el2_dec_tlu_ctl.scala 2719:41] + node _T_911 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_912 = eq(_T_911, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_913 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_914 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_915 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_916 = eq(_T_915, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_917 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_918 = eq(_T_917, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_919 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_920 = eq(_T_919, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_921 = and(_T_912, _T_913) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_922 = and(_T_921, _T_914) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_923 = and(_T_922, _T_916) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_924 = and(_T_923, _T_918) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_925 = and(_T_924, _T_920) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_926 = or(_T_910, _T_925) @[el2_dec_tlu_ctl.scala 2719:81] + node _T_927 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_928 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_929 = eq(_T_928, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_930 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_931 = eq(_T_930, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_932 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_933 = eq(_T_932, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_934 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_935 = and(_T_927, _T_929) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_936 = and(_T_935, _T_931) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_937 = and(_T_936, _T_933) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_938 = and(_T_937, _T_934) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_939 = or(_T_926, _T_938) @[el2_dec_tlu_ctl.scala 2719:114] + io.csr_pkt.postsync <= _T_939 @[el2_dec_tlu_ctl.scala 2718:24] + node _T_940 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_941 = eq(_T_940, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_942 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_943 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_944 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_945 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_946 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_947 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_948 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_949 = eq(_T_948, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_950 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_951 = eq(_T_950, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_952 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_953 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_954 = eq(_T_953, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_955 = and(_T_941, _T_942) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_956 = and(_T_955, _T_943) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_957 = and(_T_956, _T_944) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_958 = and(_T_957, _T_945) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_959 = and(_T_958, _T_946) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_960 = and(_T_959, _T_947) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_961 = and(_T_960, _T_949) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_962 = and(_T_961, _T_951) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_963 = and(_T_962, _T_952) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_964 = and(_T_963, _T_954) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_965 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_966 = eq(_T_965, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_967 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_968 = eq(_T_967, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_969 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_970 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_971 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_972 = eq(_T_971, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_973 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_974 = eq(_T_973, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_975 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_976 = eq(_T_975, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_977 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_978 = eq(_T_977, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_979 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_980 = eq(_T_979, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_981 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_982 = eq(_T_981, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_983 = and(_T_966, _T_968) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_984 = and(_T_983, _T_969) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_985 = and(_T_984, _T_970) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_986 = and(_T_985, _T_972) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_987 = and(_T_986, _T_974) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_988 = and(_T_987, _T_976) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_989 = and(_T_988, _T_978) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_990 = and(_T_989, _T_980) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_991 = and(_T_990, _T_982) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_992 = or(_T_964, _T_991) @[el2_dec_tlu_ctl.scala 2721:73] + node _T_993 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_994 = eq(_T_993, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_995 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_996 = eq(_T_995, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_997 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_998 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_999 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1000 = eq(_T_999, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1001 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1002 = eq(_T_1001, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1003 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1004 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1005 = eq(_T_1004, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1006 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_1007 = eq(_T_1006, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_1008 = and(_T_994, _T_996) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1009 = and(_T_1008, _T_997) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1010 = and(_T_1009, _T_998) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1011 = and(_T_1010, _T_1000) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1012 = and(_T_1011, _T_1002) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1013 = and(_T_1012, _T_1003) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1014 = and(_T_1013, _T_1005) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1015 = and(_T_1014, _T_1007) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1016 = or(_T_992, _T_1015) @[el2_dec_tlu_ctl.scala 2721:121] + node _T_1017 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1018 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1019 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1020 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1021 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1022 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1023 = eq(_T_1022, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1024 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1025 = eq(_T_1024, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1026 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1027 = eq(_T_1026, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1028 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1029 = eq(_T_1028, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1030 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_1031 = eq(_T_1030, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_1032 = and(_T_1017, _T_1018) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1033 = and(_T_1032, _T_1019) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1034 = and(_T_1033, _T_1020) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1035 = and(_T_1034, _T_1021) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1036 = and(_T_1035, _T_1023) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1037 = and(_T_1036, _T_1025) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1038 = and(_T_1037, _T_1027) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1039 = and(_T_1038, _T_1029) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1040 = and(_T_1039, _T_1031) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1041 = or(_T_1016, _T_1040) @[el2_dec_tlu_ctl.scala 2722:57] + node _T_1042 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1043 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1044 = eq(_T_1043, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1045 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1046 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1047 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1048 = eq(_T_1047, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1049 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1050 = eq(_T_1049, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1051 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_1052 = eq(_T_1051, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_1053 = and(_T_1042, _T_1044) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1054 = and(_T_1053, _T_1045) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1055 = and(_T_1054, _T_1046) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1056 = and(_T_1055, _T_1048) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1057 = and(_T_1056, _T_1050) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1058 = and(_T_1057, _T_1052) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1059 = or(_T_1041, _T_1058) @[el2_dec_tlu_ctl.scala 2722:105] + node _T_1060 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1061 = eq(_T_1060, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1062 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1063 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1064 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1065 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1066 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1067 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1068 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1069 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1070 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1071 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1072 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1073 = and(_T_1061, _T_1062) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1074 = and(_T_1073, _T_1063) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1075 = and(_T_1074, _T_1064) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1076 = and(_T_1075, _T_1065) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1077 = and(_T_1076, _T_1066) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1078 = and(_T_1077, _T_1067) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1079 = and(_T_1078, _T_1068) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1080 = and(_T_1079, _T_1069) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1081 = and(_T_1080, _T_1070) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1082 = and(_T_1081, _T_1071) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1083 = and(_T_1082, _T_1072) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1084 = or(_T_1059, _T_1083) @[el2_dec_tlu_ctl.scala 2723:65] + node _T_1085 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1086 = eq(_T_1085, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1087 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1088 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1089 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1090 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1091 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1092 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1093 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1094 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1095 = eq(_T_1094, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1096 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1097 = eq(_T_1096, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1098 = and(_T_1086, _T_1087) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1099 = and(_T_1098, _T_1088) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1100 = and(_T_1099, _T_1089) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1101 = and(_T_1100, _T_1090) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1102 = and(_T_1101, _T_1091) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1103 = and(_T_1102, _T_1092) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1104 = and(_T_1103, _T_1093) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1105 = and(_T_1104, _T_1095) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1106 = and(_T_1105, _T_1097) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1107 = or(_T_1084, _T_1106) @[el2_dec_tlu_ctl.scala 2723:113] + node _T_1108 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1109 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1110 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1111 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1112 = eq(_T_1111, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1113 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1114 = eq(_T_1113, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1115 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1116 = eq(_T_1115, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1117 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1118 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1119 = eq(_T_1118, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1120 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1121 = eq(_T_1120, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1122 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1123 = and(_T_1108, _T_1109) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1124 = and(_T_1123, _T_1110) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1125 = and(_T_1124, _T_1112) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1126 = and(_T_1125, _T_1114) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1127 = and(_T_1126, _T_1116) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1128 = and(_T_1127, _T_1117) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1129 = and(_T_1128, _T_1119) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1130 = and(_T_1129, _T_1121) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1131 = and(_T_1130, _T_1122) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1132 = or(_T_1107, _T_1131) @[el2_dec_tlu_ctl.scala 2724:57] + node _T_1133 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1134 = eq(_T_1133, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1135 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1136 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1137 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1138 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1139 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1140 = eq(_T_1139, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1141 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1142 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1143 = eq(_T_1142, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1144 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1145 = eq(_T_1144, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1146 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1147 = eq(_T_1146, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1148 = and(_T_1134, _T_1135) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1149 = and(_T_1148, _T_1136) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1150 = and(_T_1149, _T_1137) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1151 = and(_T_1150, _T_1138) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1152 = and(_T_1151, _T_1140) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1153 = and(_T_1152, _T_1141) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1154 = and(_T_1153, _T_1143) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1155 = and(_T_1154, _T_1145) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1156 = and(_T_1155, _T_1147) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1157 = or(_T_1132, _T_1156) @[el2_dec_tlu_ctl.scala 2724:113] + node _T_1158 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1159 = eq(_T_1158, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1160 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1161 = eq(_T_1160, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1162 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1163 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1164 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1165 = eq(_T_1164, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1166 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1167 = eq(_T_1166, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1168 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1169 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1170 = and(_T_1159, _T_1161) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1171 = and(_T_1170, _T_1162) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1172 = and(_T_1171, _T_1163) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1173 = and(_T_1172, _T_1165) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1174 = and(_T_1173, _T_1167) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1175 = and(_T_1174, _T_1168) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1176 = and(_T_1175, _T_1169) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1177 = or(_T_1157, _T_1176) @[el2_dec_tlu_ctl.scala 2725:57] + node _T_1178 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1179 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1180 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1181 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1182 = eq(_T_1181, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1183 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1184 = eq(_T_1183, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1185 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1186 = eq(_T_1185, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1187 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1188 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1189 = eq(_T_1188, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1190 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1191 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1192 = eq(_T_1191, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1193 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_1194 = eq(_T_1193, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_1195 = and(_T_1178, _T_1179) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1196 = and(_T_1195, _T_1180) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1197 = and(_T_1196, _T_1182) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1198 = and(_T_1197, _T_1184) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1199 = and(_T_1198, _T_1186) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1200 = and(_T_1199, _T_1187) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1201 = and(_T_1200, _T_1189) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1202 = and(_T_1201, _T_1190) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1203 = and(_T_1202, _T_1192) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1204 = and(_T_1203, _T_1194) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1205 = or(_T_1177, _T_1204) @[el2_dec_tlu_ctl.scala 2725:113] + node _T_1206 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1207 = eq(_T_1206, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1208 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1209 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1210 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1211 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1212 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1213 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1214 = eq(_T_1213, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1215 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1216 = eq(_T_1215, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1217 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1218 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1219 = and(_T_1207, _T_1208) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1220 = and(_T_1219, _T_1209) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1221 = and(_T_1220, _T_1210) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1222 = and(_T_1221, _T_1211) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1223 = and(_T_1222, _T_1212) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1224 = and(_T_1223, _T_1214) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1225 = and(_T_1224, _T_1216) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1226 = and(_T_1225, _T_1217) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1227 = and(_T_1226, _T_1218) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1228 = or(_T_1205, _T_1227) @[el2_dec_tlu_ctl.scala 2726:57] + node _T_1229 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1230 = eq(_T_1229, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1231 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1232 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1233 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1234 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1235 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1236 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1237 = eq(_T_1236, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1238 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1239 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1240 = eq(_T_1239, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1241 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1242 = and(_T_1230, _T_1231) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1243 = and(_T_1242, _T_1232) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1244 = and(_T_1243, _T_1233) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1245 = and(_T_1244, _T_1234) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1246 = and(_T_1245, _T_1235) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1247 = and(_T_1246, _T_1237) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1248 = and(_T_1247, _T_1238) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1249 = and(_T_1248, _T_1240) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1250 = and(_T_1249, _T_1241) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1251 = or(_T_1228, _T_1250) @[el2_dec_tlu_ctl.scala 2726:113] + node _T_1252 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1253 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1254 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1255 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1256 = eq(_T_1255, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1257 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1258 = eq(_T_1257, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1259 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1260 = eq(_T_1259, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1261 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1262 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1263 = eq(_T_1262, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1264 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1265 = eq(_T_1264, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1266 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1267 = and(_T_1252, _T_1253) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1268 = and(_T_1267, _T_1254) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1269 = and(_T_1268, _T_1256) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1270 = and(_T_1269, _T_1258) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1271 = and(_T_1270, _T_1260) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1272 = and(_T_1271, _T_1261) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1273 = and(_T_1272, _T_1263) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1274 = and(_T_1273, _T_1265) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1275 = and(_T_1274, _T_1266) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1276 = or(_T_1251, _T_1275) @[el2_dec_tlu_ctl.scala 2727:57] + node _T_1277 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1278 = eq(_T_1277, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1279 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1280 = eq(_T_1279, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1281 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1282 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1283 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1284 = eq(_T_1283, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1285 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1286 = eq(_T_1285, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1287 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1288 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1289 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1290 = and(_T_1278, _T_1280) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1291 = and(_T_1290, _T_1281) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1292 = and(_T_1291, _T_1282) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1293 = and(_T_1292, _T_1284) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1294 = and(_T_1293, _T_1286) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1295 = and(_T_1294, _T_1287) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1296 = and(_T_1295, _T_1288) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1297 = and(_T_1296, _T_1289) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1298 = or(_T_1276, _T_1297) @[el2_dec_tlu_ctl.scala 2727:113] + node _T_1299 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1300 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1301 = eq(_T_1300, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1302 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1303 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1304 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1305 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1306 = eq(_T_1305, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1307 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1308 = eq(_T_1307, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1309 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1310 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1311 = eq(_T_1310, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1312 = and(_T_1299, _T_1301) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1313 = and(_T_1312, _T_1302) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1314 = and(_T_1313, _T_1303) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1315 = and(_T_1314, _T_1304) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1316 = and(_T_1315, _T_1306) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1317 = and(_T_1316, _T_1308) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1318 = and(_T_1317, _T_1309) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1319 = and(_T_1318, _T_1311) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1320 = or(_T_1298, _T_1319) @[el2_dec_tlu_ctl.scala 2728:65] + node _T_1321 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1322 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1323 = eq(_T_1322, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1324 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1325 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1326 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1327 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1328 = eq(_T_1327, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1329 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1330 = eq(_T_1329, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1331 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1332 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1333 = eq(_T_1332, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1334 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_1335 = eq(_T_1334, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_1336 = and(_T_1321, _T_1323) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1337 = and(_T_1336, _T_1324) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1338 = and(_T_1337, _T_1325) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1339 = and(_T_1338, _T_1326) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1340 = and(_T_1339, _T_1328) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1341 = and(_T_1340, _T_1330) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1342 = and(_T_1341, _T_1331) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1343 = and(_T_1342, _T_1333) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1344 = and(_T_1343, _T_1335) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1345 = or(_T_1320, _T_1344) @[el2_dec_tlu_ctl.scala 2728:121] + node _T_1346 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1347 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1348 = eq(_T_1347, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1349 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1350 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1351 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1352 = eq(_T_1351, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1353 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1354 = eq(_T_1353, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1355 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1356 = and(_T_1346, _T_1348) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1357 = and(_T_1356, _T_1349) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1358 = and(_T_1357, _T_1350) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1359 = and(_T_1358, _T_1352) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1360 = and(_T_1359, _T_1354) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1361 = and(_T_1360, _T_1355) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1362 = or(_T_1345, _T_1361) @[el2_dec_tlu_ctl.scala 2729:57] + node _T_1363 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1364 = eq(_T_1363, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1365 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1366 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1367 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1368 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1369 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1370 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1371 = eq(_T_1370, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1372 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1373 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1374 = eq(_T_1373, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1375 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1376 = and(_T_1364, _T_1365) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1377 = and(_T_1376, _T_1366) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1378 = and(_T_1377, _T_1367) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1379 = and(_T_1378, _T_1368) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1380 = and(_T_1379, _T_1369) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1381 = and(_T_1380, _T_1371) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1382 = and(_T_1381, _T_1372) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1383 = and(_T_1382, _T_1374) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1384 = and(_T_1383, _T_1375) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1385 = or(_T_1362, _T_1384) @[el2_dec_tlu_ctl.scala 2729:113] + node _T_1386 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1387 = eq(_T_1386, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1388 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1389 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1390 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1391 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1392 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1393 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1394 = eq(_T_1393, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1395 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1396 = eq(_T_1395, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1397 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_1398 = eq(_T_1397, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_1399 = and(_T_1387, _T_1388) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1400 = and(_T_1399, _T_1389) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1401 = and(_T_1400, _T_1390) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1402 = and(_T_1401, _T_1391) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1403 = and(_T_1402, _T_1392) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1404 = and(_T_1403, _T_1394) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1405 = and(_T_1404, _T_1396) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1406 = and(_T_1405, _T_1398) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1407 = or(_T_1385, _T_1406) @[el2_dec_tlu_ctl.scala 2730:57] + node _T_1408 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1409 = eq(_T_1408, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1410 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1411 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1412 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1413 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1414 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1415 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1416 = eq(_T_1415, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1417 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1418 = eq(_T_1417, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1419 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1420 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1421 = eq(_T_1420, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1422 = and(_T_1409, _T_1410) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1423 = and(_T_1422, _T_1411) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1424 = and(_T_1423, _T_1412) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1425 = and(_T_1424, _T_1413) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1426 = and(_T_1425, _T_1414) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1427 = and(_T_1426, _T_1416) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1428 = and(_T_1427, _T_1418) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1429 = and(_T_1428, _T_1419) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1430 = and(_T_1429, _T_1421) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1431 = or(_T_1407, _T_1430) @[el2_dec_tlu_ctl.scala 2730:113] + node _T_1432 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1433 = eq(_T_1432, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1434 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1435 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1436 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1437 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1438 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1439 = eq(_T_1438, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1440 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1441 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1442 = eq(_T_1441, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1443 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1444 = eq(_T_1443, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1445 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1446 = eq(_T_1445, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1447 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_1448 = eq(_T_1447, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_1449 = and(_T_1433, _T_1434) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1450 = and(_T_1449, _T_1435) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1451 = and(_T_1450, _T_1436) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1452 = and(_T_1451, _T_1437) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1453 = and(_T_1452, _T_1439) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1454 = and(_T_1453, _T_1440) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1455 = and(_T_1454, _T_1442) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1456 = and(_T_1455, _T_1444) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1457 = and(_T_1456, _T_1446) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1458 = and(_T_1457, _T_1448) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1459 = or(_T_1431, _T_1458) @[el2_dec_tlu_ctl.scala 2731:57] + node _T_1460 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1461 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1462 = eq(_T_1461, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1463 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1464 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1465 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1466 = eq(_T_1465, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1467 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1468 = eq(_T_1467, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1469 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1470 = and(_T_1460, _T_1462) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1471 = and(_T_1470, _T_1463) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1472 = and(_T_1471, _T_1464) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1473 = and(_T_1472, _T_1466) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1474 = and(_T_1473, _T_1468) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1475 = and(_T_1474, _T_1469) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1476 = or(_T_1459, _T_1475) @[el2_dec_tlu_ctl.scala 2731:105] + node _T_1477 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1478 = eq(_T_1477, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1479 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1480 = eq(_T_1479, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1481 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1482 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1483 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1484 = eq(_T_1483, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1485 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1486 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1487 = eq(_T_1486, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1488 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1489 = eq(_T_1488, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1490 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1491 = eq(_T_1490, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1492 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1493 = eq(_T_1492, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1494 = and(_T_1478, _T_1480) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1495 = and(_T_1494, _T_1481) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1496 = and(_T_1495, _T_1482) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1497 = and(_T_1496, _T_1484) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1498 = and(_T_1497, _T_1485) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1499 = and(_T_1498, _T_1487) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1500 = and(_T_1499, _T_1489) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1501 = and(_T_1500, _T_1491) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1502 = and(_T_1501, _T_1493) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1503 = or(_T_1476, _T_1502) @[el2_dec_tlu_ctl.scala 2732:65] + node _T_1504 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1505 = eq(_T_1504, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1506 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1507 = eq(_T_1506, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1508 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1509 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1510 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1511 = eq(_T_1510, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1512 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1513 = eq(_T_1512, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1514 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1515 = eq(_T_1514, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1516 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1517 = eq(_T_1516, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1518 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1519 = eq(_T_1518, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1520 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_1521 = eq(_T_1520, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_1522 = and(_T_1505, _T_1507) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1523 = and(_T_1522, _T_1508) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1524 = and(_T_1523, _T_1509) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1525 = and(_T_1524, _T_1511) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1526 = and(_T_1525, _T_1513) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1527 = and(_T_1526, _T_1515) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1528 = and(_T_1527, _T_1517) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1529 = and(_T_1528, _T_1519) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1530 = and(_T_1529, _T_1521) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1531 = or(_T_1503, _T_1530) @[el2_dec_tlu_ctl.scala 2732:113] + node _T_1532 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1533 = eq(_T_1532, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1534 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1535 = eq(_T_1534, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1536 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1537 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1538 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1539 = eq(_T_1538, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1540 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1541 = eq(_T_1540, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1542 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1543 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1544 = and(_T_1533, _T_1535) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1545 = and(_T_1544, _T_1536) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1546 = and(_T_1545, _T_1537) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1547 = and(_T_1546, _T_1539) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1548 = and(_T_1547, _T_1541) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1549 = and(_T_1548, _T_1542) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1550 = and(_T_1549, _T_1543) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1551 = or(_T_1531, _T_1550) @[el2_dec_tlu_ctl.scala 2733:57] + node _T_1552 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1553 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1554 = eq(_T_1553, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1555 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1556 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1557 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1558 = eq(_T_1557, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1559 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1560 = eq(_T_1559, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1561 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1562 = and(_T_1552, _T_1554) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1563 = and(_T_1562, _T_1555) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1564 = and(_T_1563, _T_1556) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1565 = and(_T_1564, _T_1558) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1566 = and(_T_1565, _T_1560) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1567 = and(_T_1566, _T_1561) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1568 = or(_T_1551, _T_1567) @[el2_dec_tlu_ctl.scala 2733:113] + node _T_1569 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1570 = eq(_T_1569, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1571 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1572 = eq(_T_1571, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1573 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1574 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1575 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1576 = eq(_T_1575, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1577 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1578 = eq(_T_1577, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1579 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1580 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1581 = and(_T_1570, _T_1572) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1582 = and(_T_1581, _T_1573) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1583 = and(_T_1582, _T_1574) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1584 = and(_T_1583, _T_1576) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1585 = and(_T_1584, _T_1578) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1586 = and(_T_1585, _T_1579) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1587 = and(_T_1586, _T_1580) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1588 = or(_T_1568, _T_1587) @[el2_dec_tlu_ctl.scala 2734:65] + node _T_1589 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1590 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1591 = eq(_T_1590, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1592 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1593 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1594 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1595 = eq(_T_1594, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1596 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1597 = eq(_T_1596, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1598 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1599 = and(_T_1589, _T_1591) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1600 = and(_T_1599, _T_1592) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1601 = and(_T_1600, _T_1593) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1602 = and(_T_1601, _T_1595) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1603 = and(_T_1602, _T_1597) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1604 = and(_T_1603, _T_1598) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1605 = or(_T_1588, _T_1604) @[el2_dec_tlu_ctl.scala 2734:121] + io.csr_pkt.legal <= _T_1605 @[el2_dec_tlu_ctl.scala 2721:20] + + module el2_dec_tlu_ctl : + input clock : Clock + input reset : AsyncReset + output io : {flip active_clk : Clock, flip free_clk : Clock, flip scan_mode : UInt<1>, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, flip lsu_fastint_stall_any : UInt<1>, flip ifu_pmu_instr_aligned : UInt<1>, flip ifu_pmu_fetch_stall : UInt<1>, flip ifu_pmu_ic_miss : UInt<1>, flip ifu_pmu_ic_hit : UInt<1>, flip ifu_pmu_bus_error : UInt<1>, flip ifu_pmu_bus_busy : UInt<1>, flip ifu_pmu_bus_trxn : UInt<1>, flip dec_pmu_instr_decoded : UInt<1>, flip dec_pmu_decode_stall : UInt<1>, flip dec_pmu_presync_stall : UInt<1>, flip dec_pmu_postsync_stall : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip exu_pmu_i0_br_misp : UInt<1>, flip exu_pmu_i0_br_ataken : UInt<1>, flip exu_pmu_i0_pc4 : UInt<1>, flip lsu_pmu_bus_trxn : UInt<1>, flip lsu_pmu_bus_misaligned : UInt<1>, flip lsu_pmu_bus_error : UInt<1>, flip lsu_pmu_bus_busy : UInt<1>, flip lsu_pmu_load_external_m : UInt<1>, flip lsu_pmu_store_external_m : UInt<1>, flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, flip lsu_fir_addr : UInt<31>, flip lsu_fir_error : UInt<2>, flip iccm_dma_sb_error : UInt<1>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, flip lsu_single_ecc_error_incr : UInt<1>, flip dec_pause_state : UInt<1>, flip lsu_imprecise_error_store_any : UInt<1>, flip lsu_imprecise_error_load_any : UInt<1>, flip lsu_imprecise_error_addr_any : UInt<32>, flip dec_csr_wen_unq_d : UInt<1>, flip dec_csr_any_unq_d : UInt<1>, flip dec_csr_rdaddr_d : UInt<12>, flip dec_csr_wen_r : UInt<1>, flip dec_csr_wraddr_r : UInt<12>, flip dec_csr_wrdata_r : UInt<32>, flip dec_csr_stall_int_ff : UInt<1>, flip dec_tlu_i0_valid_r : UInt<1>, flip exu_npc_r : UInt<31>, flip dec_tlu_i0_pc_r : UInt<31>, flip dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, flip dec_illegal_inst : UInt<32>, flip dec_i0_decode_d : UInt<1>, flip exu_i0_br_hist_r : UInt<2>, flip exu_i0_br_error_r : UInt<1>, flip exu_i0_br_start_error_r : UInt<1>, flip exu_i0_br_valid_r : UInt<1>, flip exu_i0_br_mp_r : UInt<1>, flip exu_i0_br_middle_r : UInt<1>, flip exu_i0_br_way_r : UInt<1>, dec_dbg_cmd_done : UInt<1>, dec_dbg_cmd_fail : UInt<1>, dec_tlu_dbg_halted : UInt<1>, dec_tlu_debug_mode : UInt<1>, dec_tlu_resume_ack : UInt<1>, dec_tlu_debug_stall : UInt<1>, dec_tlu_flush_noredir_r : UInt<1>, dec_tlu_mpc_halted_only : UInt<1>, dec_tlu_flush_leak_one_r : UInt<1>, dec_tlu_flush_err_r : UInt<1>, dec_tlu_flush_extint : UInt<1>, dec_tlu_meihap : UInt<30>, flip dbg_halt_req : UInt<1>, flip dbg_resume_req : UInt<1>, flip ifu_miss_state_idle : UInt<1>, flip lsu_idle_any : UInt<1>, flip dec_div_active : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip ifu_ic_error_start : UInt<1>, flip ifu_iccm_rd_ecc_single_err : UInt<1>, flip ifu_ic_debug_rd_data : UInt<71>, flip ifu_ic_debug_rd_data_valid : UInt<1>, dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip pic_claimid : UInt<8>, flip pic_pl : UInt<4>, flip mhwakeup : UInt<1>, flip mexintpend : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meipt : UInt<4>, dec_csr_rddata_d : UInt<32>, dec_csr_legal_d : UInt<1>, dec_tlu_br0_r_pkt : {valid : UInt<1>, bits : {hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}}, dec_tlu_i0_kill_writeb_wb : UInt<1>, dec_tlu_flush_lower_wb : UInt<1>, dec_tlu_i0_commit_cmt : UInt<1>, dec_tlu_i0_kill_writeb_r : UInt<1>, dec_tlu_flush_lower_r : UInt<1>, dec_tlu_flush_path_r : UInt<31>, dec_tlu_fence_i_r : UInt<1>, dec_tlu_wr_pause_r : UInt<1>, dec_tlu_flush_pause_r : UInt<1>, dec_tlu_presync_d : UInt<1>, dec_tlu_postsync_d : UInt<1>, dec_tlu_mrac_ff : UInt<32>, dec_tlu_force_halt : UInt<1>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, dec_tlu_i0_exc_valid_wb1 : UInt<1>, dec_tlu_i0_valid_wb1 : UInt<1>, dec_tlu_int_valid_wb1 : UInt<1>, dec_tlu_exc_cause_wb1 : UInt<5>, dec_tlu_mtval_wb1 : UInt<32>, dec_tlu_external_ldfwd_disable : UInt<1>, dec_tlu_sideeffect_posted_disable : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, dec_tlu_bpred_disable : UInt<1>, dec_tlu_wb_coalescing_disable : UInt<1>, dec_tlu_pipelining_disable : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_dec_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>} + + wire mtdata1_t : UInt<10>[4] @[el2_dec_tlu_ctl.scala 236:59] + wire pause_expired_wb : UInt<1> + pause_expired_wb <= UInt<1>("h00") + wire take_nmi_r_d1 : UInt<1> + take_nmi_r_d1 <= UInt<1>("h00") + wire exc_or_int_valid_r_d1 : UInt<1> + exc_or_int_valid_r_d1 <= UInt<1>("h00") + wire interrupt_valid_r_d1 : UInt<1> + interrupt_valid_r_d1 <= UInt<1>("h00") + wire tlu_flush_lower_r : UInt<1> + tlu_flush_lower_r <= UInt<1>("h00") + wire synchronous_flush_r : UInt<1> + synchronous_flush_r <= UInt<1>("h00") + wire interrupt_valid_r : UInt<1> + interrupt_valid_r <= UInt<1>("h00") + wire take_nmi : UInt<1> + take_nmi <= UInt<1>("h00") + wire take_reset : UInt<1> + take_reset <= UInt<1>("h00") + wire take_int_timer1_int : UInt<1> + take_int_timer1_int <= UInt<1>("h00") + wire take_int_timer0_int : UInt<1> + take_int_timer0_int <= UInt<1>("h00") + wire take_timer_int : UInt<1> + take_timer_int <= UInt<1>("h00") + wire take_soft_int : UInt<1> + take_soft_int <= UInt<1>("h00") + wire take_ce_int : UInt<1> + take_ce_int <= UInt<1>("h00") + wire take_ext_int_start : UInt<1> + take_ext_int_start <= UInt<1>("h00") + wire ext_int_freeze : UInt<1> + ext_int_freeze <= UInt<1>("h00") + wire ext_int_freeze_d1 : UInt<1> + ext_int_freeze_d1 <= UInt<1>("h00") + wire take_ext_int_start_d1 : UInt<1> + take_ext_int_start_d1 <= UInt<1>("h00") + wire take_ext_int_start_d2 : UInt<1> + take_ext_int_start_d2 <= UInt<1>("h00") + wire take_ext_int_start_d3 : UInt<1> + take_ext_int_start_d3 <= UInt<1>("h00") + wire fast_int_meicpct : UInt<1> + fast_int_meicpct <= UInt<1>("h00") + wire ignore_ext_int_due_to_lsu_stall : UInt<1> + ignore_ext_int_due_to_lsu_stall <= UInt<1>("h00") + wire take_ext_int : UInt<1> + take_ext_int <= UInt<1>("h00") + wire internal_dbg_halt_timers : UInt<1> + internal_dbg_halt_timers <= UInt<1>("h00") + wire int_timer1_int_hold : UInt<1> + int_timer1_int_hold <= UInt<1>("h00") + wire int_timer0_int_hold : UInt<1> + int_timer0_int_hold <= UInt<1>("h00") + wire mhwakeup_ready : UInt<1> + mhwakeup_ready <= UInt<1>("h00") + wire ext_int_ready : UInt<1> + ext_int_ready <= UInt<1>("h00") + wire ce_int_ready : UInt<1> + ce_int_ready <= UInt<1>("h00") + wire soft_int_ready : UInt<1> + soft_int_ready <= UInt<1>("h00") + wire timer_int_ready : UInt<1> + timer_int_ready <= UInt<1>("h00") + wire ebreak_to_debug_mode_r_d1 : UInt<1> + ebreak_to_debug_mode_r_d1 <= UInt<1>("h00") + wire ebreak_to_debug_mode_r : UInt<1> + ebreak_to_debug_mode_r <= UInt<1>("h00") + wire inst_acc_r : UInt<1> + inst_acc_r <= UInt<1>("h00") + wire inst_acc_r_raw : UInt<1> + inst_acc_r_raw <= UInt<1>("h00") + wire iccm_sbecc_r : UInt<1> + iccm_sbecc_r <= UInt<1>("h00") + wire ic_perr_r : UInt<1> + ic_perr_r <= UInt<1>("h00") + wire fence_i_r : UInt<1> + fence_i_r <= UInt<1>("h00") + wire ebreak_r : UInt<1> + ebreak_r <= UInt<1>("h00") + wire ecall_r : UInt<1> + ecall_r <= UInt<1>("h00") + wire illegal_r : UInt<1> + illegal_r <= UInt<1>("h00") + wire mret_r : UInt<1> + mret_r <= UInt<1>("h00") + wire iccm_repair_state_ns : UInt<1> + iccm_repair_state_ns <= UInt<1>("h00") + wire rfpc_i0_r : UInt<1> + rfpc_i0_r <= UInt<1>("h00") + wire tlu_i0_kill_writeb_r : UInt<1> + tlu_i0_kill_writeb_r <= UInt<1>("h00") + wire lsu_exc_valid_r_d1 : UInt<1> + lsu_exc_valid_r_d1 <= UInt<1>("h00") + wire lsu_i0_exc_r_raw : UInt<1> + lsu_i0_exc_r_raw <= UInt<1>("h00") + wire mdseac_locked_f : UInt<1> + mdseac_locked_f <= UInt<1>("h00") + wire i_cpu_run_req_d1 : UInt<1> + i_cpu_run_req_d1 <= UInt<1>("h00") + wire cpu_run_ack : UInt<1> + cpu_run_ack <= UInt<1>("h00") + wire cpu_halt_status : UInt<1> + cpu_halt_status <= UInt<1>("h00") + wire cpu_halt_ack : UInt<1> + cpu_halt_ack <= UInt<1>("h00") + wire pmu_fw_tlu_halted : UInt<1> + pmu_fw_tlu_halted <= UInt<1>("h00") + wire internal_pmu_fw_halt_mode : UInt<1> + internal_pmu_fw_halt_mode <= UInt<1>("h00") + wire pmu_fw_halt_req_ns : UInt<1> + pmu_fw_halt_req_ns <= UInt<1>("h00") + wire pmu_fw_halt_req_f : UInt<1> + pmu_fw_halt_req_f <= UInt<1>("h00") + wire pmu_fw_tlu_halted_f : UInt<1> + pmu_fw_tlu_halted_f <= UInt<1>("h00") + wire int_timer0_int_hold_f : UInt<1> + int_timer0_int_hold_f <= UInt<1>("h00") + wire int_timer1_int_hold_f : UInt<1> + int_timer1_int_hold_f <= UInt<1>("h00") + wire trigger_hit_dmode_r : UInt<1> + trigger_hit_dmode_r <= UInt<1>("h00") + wire i0_trigger_hit_r : UInt<1> + i0_trigger_hit_r <= UInt<1>("h00") + wire pause_expired_r : UInt<1> + pause_expired_r <= UInt<1>("h00") + wire dec_tlu_pmu_fw_halted : UInt<1> + dec_tlu_pmu_fw_halted <= UInt<1>("h00") + wire dec_tlu_flush_noredir_r_d1 : UInt<1> + dec_tlu_flush_noredir_r_d1 <= UInt<1>("h00") + wire halt_taken_f : UInt<1> + halt_taken_f <= UInt<1>("h00") + wire lsu_idle_any_f : UInt<1> + lsu_idle_any_f <= UInt<1>("h00") + wire ifu_miss_state_idle_f : UInt<1> + ifu_miss_state_idle_f <= UInt<1>("h00") + wire dbg_tlu_halted_f : UInt<1> + dbg_tlu_halted_f <= UInt<1>("h00") + wire debug_halt_req_f : UInt<1> + debug_halt_req_f <= UInt<1>("h00") + wire debug_resume_req_f : UInt<1> + debug_resume_req_f <= UInt<1>("h00") + wire trigger_hit_dmode_r_d1 : UInt<1> + trigger_hit_dmode_r_d1 <= UInt<1>("h00") + wire dcsr_single_step_done_f : UInt<1> + dcsr_single_step_done_f <= UInt<1>("h00") + wire debug_halt_req_d1 : UInt<1> + debug_halt_req_d1 <= UInt<1>("h00") + wire request_debug_mode_r_d1 : UInt<1> + request_debug_mode_r_d1 <= UInt<1>("h00") + wire request_debug_mode_done_f : UInt<1> + request_debug_mode_done_f <= UInt<1>("h00") + wire dcsr_single_step_running_f : UInt<1> + dcsr_single_step_running_f <= UInt<1>("h00") + wire dec_tlu_flush_pause_r_d1 : UInt<1> + dec_tlu_flush_pause_r_d1 <= UInt<1>("h00") + wire dbg_halt_req_held : UInt<1> + dbg_halt_req_held <= UInt<1>("h00") + wire debug_halt_req_ns : UInt<1> + debug_halt_req_ns <= UInt<1>("h00") + wire internal_dbg_halt_mode : UInt<1> + internal_dbg_halt_mode <= UInt<1>("h00") + wire core_empty : UInt<1> + core_empty <= UInt<1>("h00") + wire dbg_halt_req_final : UInt<1> + dbg_halt_req_final <= UInt<1>("h00") + wire debug_brkpt_status_ns : UInt<1> + debug_brkpt_status_ns <= UInt<1>("h00") + wire mpc_debug_halt_ack_ns : UInt<1> + mpc_debug_halt_ack_ns <= UInt<1>("h00") + wire mpc_debug_run_ack_ns : UInt<1> + mpc_debug_run_ack_ns <= UInt<1>("h00") + wire mpc_halt_state_ns : UInt<1> + mpc_halt_state_ns <= UInt<1>("h00") + wire mpc_run_state_ns : UInt<1> + mpc_run_state_ns <= UInt<1>("h00") + wire dbg_halt_state_ns : UInt<1> + dbg_halt_state_ns <= UInt<1>("h00") + wire dbg_run_state_ns : UInt<1> + dbg_run_state_ns <= UInt<1>("h00") + wire dbg_halt_state_f : UInt<1> + dbg_halt_state_f <= UInt<1>("h00") + wire mpc_halt_state_f : UInt<1> + mpc_halt_state_f <= UInt<1>("h00") + wire nmi_int_detected : UInt<1> + nmi_int_detected <= UInt<1>("h00") + wire nmi_lsu_load_type : UInt<1> + nmi_lsu_load_type <= UInt<1>("h00") + wire nmi_lsu_store_type : UInt<1> + nmi_lsu_store_type <= UInt<1>("h00") + wire reset_delayed : UInt<1> + reset_delayed <= UInt<1>("h00") + wire debug_mode_status : UInt<1> + debug_mode_status <= UInt<1>("h00") + wire e5_valid : UInt<1> + e5_valid <= UInt<1>("h00") + wire ic_perr_r_d1 : UInt<1> + ic_perr_r_d1 <= UInt<1>("h00") + wire iccm_sbecc_r_d1 : UInt<1> + iccm_sbecc_r_d1 <= UInt<1>("h00") + wire npc_r : UInt<31> + npc_r <= UInt<1>("h00") + wire npc_r_d1 : UInt<31> + npc_r_d1 <= UInt<1>("h00") + wire mie_ns : UInt<6> + mie_ns <= UInt<1>("h00") + wire mepc : UInt<31> + mepc <= UInt<1>("h00") + wire mdseac_locked_ns : UInt<1> + mdseac_locked_ns <= UInt<1>("h00") + wire force_halt : UInt<1> + force_halt <= UInt<1>("h00") + wire dpc : UInt<31> + dpc <= UInt<1>("h00") + wire mstatus_mie_ns : UInt<1> + mstatus_mie_ns <= UInt<1>("h00") + wire dec_csr_wen_r_mod : UInt<1> + dec_csr_wen_r_mod <= UInt<1>("h00") + wire fw_halt_req : UInt<1> + fw_halt_req <= UInt<1>("h00") + wire mstatus : UInt<2> + mstatus <= UInt<1>("h00") + wire dcsr : UInt<16> + dcsr <= UInt<1>("h00") + wire mtvec : UInt<31> + mtvec <= UInt<1>("h00") + wire mip : UInt<6> + mip <= UInt<1>("h00") + wire csr_pkt : {csr_misa : UInt<1>, csr_mvendorid : UInt<1>, csr_marchid : UInt<1>, csr_mimpid : UInt<1>, csr_mhartid : UInt<1>, csr_mstatus : UInt<1>, csr_mtvec : UInt<1>, csr_mip : UInt<1>, csr_mie : UInt<1>, csr_mcyclel : UInt<1>, csr_mcycleh : UInt<1>, csr_minstretl : UInt<1>, csr_minstreth : UInt<1>, csr_mscratch : UInt<1>, csr_mepc : UInt<1>, csr_mcause : UInt<1>, csr_mscause : UInt<1>, csr_mtval : UInt<1>, csr_mrac : UInt<1>, csr_dmst : UInt<1>, csr_mdseac : UInt<1>, csr_meihap : UInt<1>, csr_meivt : UInt<1>, csr_meipt : UInt<1>, csr_meicurpl : UInt<1>, csr_meicidpl : UInt<1>, csr_dcsr : UInt<1>, csr_mcgc : UInt<1>, csr_mfdc : UInt<1>, csr_dpc : UInt<1>, csr_mtsel : UInt<1>, csr_mtdata1 : UInt<1>, csr_mtdata2 : UInt<1>, csr_mhpmc3 : UInt<1>, csr_mhpmc4 : UInt<1>, csr_mhpmc5 : UInt<1>, csr_mhpmc6 : UInt<1>, csr_mhpmc3h : UInt<1>, csr_mhpmc4h : UInt<1>, csr_mhpmc5h : UInt<1>, csr_mhpmc6h : UInt<1>, csr_mhpme3 : UInt<1>, csr_mhpme4 : UInt<1>, csr_mhpme5 : UInt<1>, csr_mhpme6 : UInt<1>, csr_mcountinhibit : UInt<1>, csr_mitctl0 : UInt<1>, csr_mitctl1 : UInt<1>, csr_mitb0 : UInt<1>, csr_mitb1 : UInt<1>, csr_mitcnt0 : UInt<1>, csr_mitcnt1 : UInt<1>, csr_mpmc : UInt<1>, csr_mcpc : UInt<1>, csr_meicpct : UInt<1>, csr_mdeau : UInt<1>, csr_micect : UInt<1>, csr_miccmect : UInt<1>, csr_mdccmect : UInt<1>, csr_mfdht : UInt<1>, csr_mfdhs : UInt<1>, csr_dicawics : UInt<1>, csr_dicad0h : UInt<1>, csr_dicad0 : UInt<1>, csr_dicad1 : UInt<1>, csr_dicago : UInt<1>, presync : UInt<1>, postsync : UInt<1>, legal : UInt<1>} @[el2_dec_tlu_ctl.scala 351:41] + wire dec_tlu_mpc_halted_only_ns : UInt<1> + dec_tlu_mpc_halted_only_ns <= UInt<1>("h00") + node _T = not(dbg_halt_state_f) @[el2_dec_tlu_ctl.scala 354:33] + node _T_1 = and(_T, mpc_halt_state_f) @[el2_dec_tlu_ctl.scala 354:51] + dec_tlu_mpc_halted_only_ns <= _T_1 @[el2_dec_tlu_ctl.scala 354:30] + inst int_timers of el2_dec_timer_ctl @[el2_dec_tlu_ctl.scala 355:24] + int_timers.clock <= clock + int_timers.reset <= reset + int_timers.io.free_clk <= io.free_clk @[el2_dec_tlu_ctl.scala 356:57] + int_timers.io.scan_mode <= io.scan_mode @[el2_dec_tlu_ctl.scala 357:57] + int_timers.io.dec_csr_wen_r_mod <= dec_csr_wen_r_mod @[el2_dec_tlu_ctl.scala 358:49] + int_timers.io.dec_csr_rdaddr_d <= io.dec_csr_rdaddr_d @[el2_dec_tlu_ctl.scala 359:49] + int_timers.io.dec_csr_wraddr_r <= io.dec_csr_wraddr_r @[el2_dec_tlu_ctl.scala 360:49] + int_timers.io.dec_csr_wrdata_r <= io.dec_csr_wrdata_r @[el2_dec_tlu_ctl.scala 361:49] + int_timers.io.csr_mitctl0 <= csr_pkt.csr_mitctl0 @[el2_dec_tlu_ctl.scala 362:49] + int_timers.io.csr_mitctl1 <= csr_pkt.csr_mitctl1 @[el2_dec_tlu_ctl.scala 363:49] + int_timers.io.csr_mitb0 <= csr_pkt.csr_mitb0 @[el2_dec_tlu_ctl.scala 364:57] + int_timers.io.csr_mitb1 <= csr_pkt.csr_mitb1 @[el2_dec_tlu_ctl.scala 365:57] + int_timers.io.csr_mitcnt0 <= csr_pkt.csr_mitcnt0 @[el2_dec_tlu_ctl.scala 366:49] + int_timers.io.csr_mitcnt1 <= csr_pkt.csr_mitcnt1 @[el2_dec_tlu_ctl.scala 367:49] + int_timers.io.dec_pause_state <= io.dec_pause_state @[el2_dec_tlu_ctl.scala 368:41] + int_timers.io.dec_tlu_pmu_fw_halted <= dec_tlu_pmu_fw_halted @[el2_dec_tlu_ctl.scala 369:41] + int_timers.io.internal_dbg_halt_timers <= internal_dbg_halt_timers @[el2_dec_tlu_ctl.scala 370:41] + node _T_2 = cat(io.i_cpu_run_req, io.mpc_debug_halt_req) @[Cat.scala 29:58] + node _T_3 = cat(_T_2, io.mpc_debug_run_req) @[Cat.scala 29:58] + node _T_4 = cat(io.soft_int, io.i_cpu_halt_req) @[Cat.scala 29:58] + node _T_5 = cat(io.nmi_int, io.timer_int) @[Cat.scala 29:58] + node _T_6 = cat(_T_5, _T_4) @[Cat.scala 29:58] + node _T_7 = cat(_T_6, _T_3) @[Cat.scala 29:58] + reg _T_8 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 177:81] + _T_8 <= _T_7 @[el2_lib.scala 177:81] + reg syncro_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 177:58] + syncro_ff <= _T_8 @[el2_lib.scala 177:58] + node nmi_int_sync = bits(syncro_ff, 6, 6) @[el2_dec_tlu_ctl.scala 382:67] + node timer_int_sync = bits(syncro_ff, 5, 5) @[el2_dec_tlu_ctl.scala 383:59] + node soft_int_sync = bits(syncro_ff, 4, 4) @[el2_dec_tlu_ctl.scala 384:59] + node i_cpu_halt_req_sync = bits(syncro_ff, 3, 3) @[el2_dec_tlu_ctl.scala 385:59] + node i_cpu_run_req_sync = bits(syncro_ff, 2, 2) @[el2_dec_tlu_ctl.scala 386:59] + node mpc_debug_halt_req_sync_raw = bits(syncro_ff, 1, 1) @[el2_dec_tlu_ctl.scala 387:51] + node mpc_debug_run_req_sync = bits(syncro_ff, 0, 0) @[el2_dec_tlu_ctl.scala 388:51] + node _T_9 = or(dec_csr_wen_r_mod, io.dec_tlu_dec_clk_override) @[el2_dec_tlu_ctl.scala 391:52] + node _T_10 = bits(_T_9, 0, 0) @[el2_dec_tlu_ctl.scala 391:68] + inst rvclkhdr of rvclkhdr_4 @[el2_lib.scala 483:22] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr.io.en <= _T_10 @[el2_lib.scala 485:16] + rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + node _T_11 = or(io.lsu_error_pkt_r.valid, lsu_exc_valid_r_d1) @[el2_dec_tlu_ctl.scala 392:61] + node _T_12 = or(_T_11, io.dec_tlu_dec_clk_override) @[el2_dec_tlu_ctl.scala 392:82] + node _T_13 = bits(_T_12, 0, 0) @[el2_dec_tlu_ctl.scala 392:98] + inst rvclkhdr_1 of rvclkhdr_5 @[el2_lib.scala 483:22] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_1.io.en <= _T_13 @[el2_lib.scala 485:16] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + node e4e5_valid = or(io.dec_tlu_i0_valid_r, e5_valid) @[el2_dec_tlu_ctl.scala 395:29] + node _T_14 = or(debug_mode_status, i_cpu_run_req_d1) @[el2_dec_tlu_ctl.scala 396:49] + node _T_15 = or(_T_14, interrupt_valid_r) @[el2_dec_tlu_ctl.scala 396:68] + node _T_16 = or(_T_15, interrupt_valid_r_d1) @[el2_dec_tlu_ctl.scala 396:88] + node _T_17 = or(_T_16, reset_delayed) @[el2_dec_tlu_ctl.scala 396:111] + node _T_18 = or(_T_17, pause_expired_r) @[el2_dec_tlu_ctl.scala 396:127] + node _T_19 = or(_T_18, pause_expired_wb) @[el2_dec_tlu_ctl.scala 396:145] + node _T_20 = or(_T_19, ic_perr_r) @[el2_dec_tlu_ctl.scala 396:164] + node _T_21 = or(_T_20, ic_perr_r_d1) @[el2_dec_tlu_ctl.scala 396:176] + node _T_22 = or(_T_21, iccm_sbecc_r) @[el2_dec_tlu_ctl.scala 396:191] + node _T_23 = or(_T_22, iccm_sbecc_r_d1) @[el2_dec_tlu_ctl.scala 396:206] + node flush_clkvalid = or(_T_23, io.dec_tlu_dec_clk_override) @[el2_dec_tlu_ctl.scala 396:224] + node _T_24 = or(e4e5_valid, io.dec_tlu_dec_clk_override) @[el2_dec_tlu_ctl.scala 398:43] + node _T_25 = bits(_T_24, 0, 0) @[el2_dec_tlu_ctl.scala 398:59] + inst rvclkhdr_2 of rvclkhdr_6 @[el2_lib.scala 483:22] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_2.io.en <= _T_25 @[el2_lib.scala 485:16] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + node _T_26 = or(e4e5_valid, flush_clkvalid) @[el2_dec_tlu_ctl.scala 399:47] + node _T_27 = bits(_T_26, 0, 0) @[el2_dec_tlu_ctl.scala 399:65] + inst rvclkhdr_3 of rvclkhdr_7 @[el2_lib.scala 483:22] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_3.io.en <= _T_27 @[el2_lib.scala 485:16] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + reg iccm_repair_state_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 401:72] + iccm_repair_state_d1 <= iccm_repair_state_ns @[el2_dec_tlu_ctl.scala 401:72] + reg _T_28 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 402:81] + _T_28 <= ic_perr_r @[el2_dec_tlu_ctl.scala 402:81] + ic_perr_r_d1 <= _T_28 @[el2_dec_tlu_ctl.scala 402:49] + reg _T_29 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 403:89] + _T_29 <= iccm_sbecc_r @[el2_dec_tlu_ctl.scala 403:89] + iccm_sbecc_r_d1 <= _T_29 @[el2_dec_tlu_ctl.scala 403:57] + reg _T_30 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 404:89] + _T_30 <= io.dec_tlu_i0_valid_r @[el2_dec_tlu_ctl.scala 404:89] + e5_valid <= _T_30 @[el2_dec_tlu_ctl.scala 404:57] + reg _T_31 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 405:73] + _T_31 <= internal_dbg_halt_mode @[el2_dec_tlu_ctl.scala 405:73] + debug_mode_status <= _T_31 @[el2_dec_tlu_ctl.scala 405:41] + reg lsu_pmu_load_external_r : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 406:72] + lsu_pmu_load_external_r <= io.lsu_pmu_load_external_m @[el2_dec_tlu_ctl.scala 406:72] + reg lsu_pmu_store_external_r : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 407:64] + lsu_pmu_store_external_r <= io.lsu_pmu_store_external_m @[el2_dec_tlu_ctl.scala 407:64] + reg tlu_flush_lower_r_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 408:72] + tlu_flush_lower_r_d1 <= tlu_flush_lower_r @[el2_dec_tlu_ctl.scala 408:72] + reg _T_32 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 409:65] + _T_32 <= tlu_i0_kill_writeb_r @[el2_dec_tlu_ctl.scala 409:65] + io.dec_tlu_i0_kill_writeb_wb <= _T_32 @[el2_dec_tlu_ctl.scala 409:33] + reg internal_dbg_halt_mode_f2 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 410:64] + internal_dbg_halt_mode_f2 <= debug_mode_status @[el2_dec_tlu_ctl.scala 410:64] + reg _T_33 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 411:73] + _T_33 <= force_halt @[el2_dec_tlu_ctl.scala 411:73] + io.dec_tlu_force_halt <= _T_33 @[el2_dec_tlu_ctl.scala 411:41] + io.dec_tlu_i0_kill_writeb_r <= tlu_i0_kill_writeb_r @[el2_dec_tlu_ctl.scala 415:33] + reg reset_detect : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 416:80] + reset_detect <= UInt<1>("h01") @[el2_dec_tlu_ctl.scala 416:80] + reg reset_detected : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 417:80] + reset_detected <= reset_detect @[el2_dec_tlu_ctl.scala 417:80] + node _T_34 = xor(reset_detect, reset_detected) @[el2_dec_tlu_ctl.scala 418:64] + reset_delayed <= _T_34 @[el2_dec_tlu_ctl.scala 418:49] + reg nmi_int_delayed : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 420:64] + nmi_int_delayed <= nmi_int_sync @[el2_dec_tlu_ctl.scala 420:64] + reg nmi_int_detected_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 421:72] + nmi_int_detected_f <= nmi_int_detected @[el2_dec_tlu_ctl.scala 421:72] + reg nmi_lsu_load_type_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 422:72] + nmi_lsu_load_type_f <= nmi_lsu_load_type @[el2_dec_tlu_ctl.scala 422:72] + reg nmi_lsu_store_type_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 423:64] + nmi_lsu_store_type_f <= nmi_lsu_store_type @[el2_dec_tlu_ctl.scala 423:64] + node _T_35 = not(mdseac_locked_f) @[el2_dec_tlu_ctl.scala 427:26] + node _T_36 = or(io.lsu_imprecise_error_load_any, io.lsu_imprecise_error_store_any) @[el2_dec_tlu_ctl.scala 427:78] + node nmi_lsu_detected = and(_T_35, _T_36) @[el2_dec_tlu_ctl.scala 427:43] + node _T_37 = not(nmi_int_delayed) @[el2_dec_tlu_ctl.scala 429:39] + node _T_38 = and(nmi_int_sync, _T_37) @[el2_dec_tlu_ctl.scala 429:37] + node _T_39 = or(_T_38, nmi_lsu_detected) @[el2_dec_tlu_ctl.scala 429:57] + node _T_40 = not(take_nmi_r_d1) @[el2_dec_tlu_ctl.scala 429:100] + node _T_41 = and(nmi_int_detected_f, _T_40) @[el2_dec_tlu_ctl.scala 429:98] + node _T_42 = or(_T_39, _T_41) @[el2_dec_tlu_ctl.scala 429:76] + node _T_43 = orr(io.lsu_fir_error) @[el2_dec_tlu_ctl.scala 429:159] + node _T_44 = and(take_ext_int_start_d3, _T_43) @[el2_dec_tlu_ctl.scala 429:140] + node _T_45 = or(_T_42, _T_44) @[el2_dec_tlu_ctl.scala 429:116] + nmi_int_detected <= _T_45 @[el2_dec_tlu_ctl.scala 429:20] + node _T_46 = and(nmi_lsu_detected, io.lsu_imprecise_error_load_any) @[el2_dec_tlu_ctl.scala 431:42] + node _T_47 = not(take_nmi_r_d1) @[el2_dec_tlu_ctl.scala 431:101] + node _T_48 = and(nmi_int_detected_f, _T_47) @[el2_dec_tlu_ctl.scala 431:99] + node _T_49 = not(_T_48) @[el2_dec_tlu_ctl.scala 431:78] + node _T_50 = and(_T_46, _T_49) @[el2_dec_tlu_ctl.scala 431:76] + node _T_51 = not(take_nmi_r_d1) @[el2_dec_tlu_ctl.scala 431:143] + node _T_52 = and(nmi_lsu_load_type_f, _T_51) @[el2_dec_tlu_ctl.scala 431:141] + node _T_53 = or(_T_50, _T_52) @[el2_dec_tlu_ctl.scala 431:118] + nmi_lsu_load_type <= _T_53 @[el2_dec_tlu_ctl.scala 431:21] + node _T_54 = and(nmi_lsu_detected, io.lsu_imprecise_error_store_any) @[el2_dec_tlu_ctl.scala 432:43] + node _T_55 = not(take_nmi_r_d1) @[el2_dec_tlu_ctl.scala 432:103] + node _T_56 = and(nmi_int_detected_f, _T_55) @[el2_dec_tlu_ctl.scala 432:101] + node _T_57 = not(_T_56) @[el2_dec_tlu_ctl.scala 432:80] + node _T_58 = and(_T_54, _T_57) @[el2_dec_tlu_ctl.scala 432:78] + node _T_59 = not(take_nmi_r_d1) @[el2_dec_tlu_ctl.scala 432:146] + node _T_60 = and(nmi_lsu_store_type_f, _T_59) @[el2_dec_tlu_ctl.scala 432:144] + node _T_61 = or(_T_58, _T_60) @[el2_dec_tlu_ctl.scala 432:120] + nmi_lsu_store_type <= _T_61 @[el2_dec_tlu_ctl.scala 432:22] + node _T_62 = not(ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 439:63] + node mpc_debug_halt_req_sync = and(mpc_debug_halt_req_sync_raw, _T_62) @[el2_dec_tlu_ctl.scala 439:61] + reg mpc_debug_halt_req_sync_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 440:64] + mpc_debug_halt_req_sync_f <= mpc_debug_halt_req_sync @[el2_dec_tlu_ctl.scala 440:64] + reg mpc_debug_run_req_sync_f : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 441:64] + mpc_debug_run_req_sync_f <= mpc_debug_run_req_sync @[el2_dec_tlu_ctl.scala 441:64] + reg _T_63 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 442:81] + _T_63 <= mpc_halt_state_ns @[el2_dec_tlu_ctl.scala 442:81] + mpc_halt_state_f <= _T_63 @[el2_dec_tlu_ctl.scala 442:49] + reg mpc_run_state_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 443:80] + mpc_run_state_f <= mpc_run_state_ns @[el2_dec_tlu_ctl.scala 443:80] + reg debug_brkpt_status_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 444:72] + debug_brkpt_status_f <= debug_brkpt_status_ns @[el2_dec_tlu_ctl.scala 444:72] + reg mpc_debug_halt_ack_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 445:72] + mpc_debug_halt_ack_f <= mpc_debug_halt_ack_ns @[el2_dec_tlu_ctl.scala 445:72] + reg mpc_debug_run_ack_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 446:80] + mpc_debug_run_ack_f <= mpc_debug_run_ack_ns @[el2_dec_tlu_ctl.scala 446:80] + reg _T_64 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 447:81] + _T_64 <= dbg_halt_state_ns @[el2_dec_tlu_ctl.scala 447:81] + dbg_halt_state_f <= _T_64 @[el2_dec_tlu_ctl.scala 447:49] + reg dbg_run_state_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 448:80] + dbg_run_state_f <= dbg_run_state_ns @[el2_dec_tlu_ctl.scala 448:80] + reg _T_65 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 449:73] + _T_65 <= dec_tlu_mpc_halted_only_ns @[el2_dec_tlu_ctl.scala 449:73] + io.dec_tlu_mpc_halted_only <= _T_65 @[el2_dec_tlu_ctl.scala 449:41] + node _T_66 = not(mpc_debug_halt_req_sync_f) @[el2_dec_tlu_ctl.scala 453:65] + node mpc_debug_halt_req_sync_pulse = and(mpc_debug_halt_req_sync, _T_66) @[el2_dec_tlu_ctl.scala 453:63] + node _T_67 = not(mpc_debug_run_req_sync_f) @[el2_dec_tlu_ctl.scala 454:64] + node mpc_debug_run_req_sync_pulse = and(mpc_debug_run_req_sync, _T_67) @[el2_dec_tlu_ctl.scala 454:62] + node _T_68 = or(mpc_halt_state_f, mpc_debug_halt_req_sync_pulse) @[el2_dec_tlu_ctl.scala 456:42] + node _T_69 = not(io.mpc_reset_run_req) @[el2_dec_tlu_ctl.scala 456:93] + node _T_70 = and(reset_delayed, _T_69) @[el2_dec_tlu_ctl.scala 456:91] + node _T_71 = or(_T_68, _T_70) @[el2_dec_tlu_ctl.scala 456:74] + node _T_72 = not(mpc_debug_run_req_sync) @[el2_dec_tlu_ctl.scala 456:119] + node _T_73 = and(_T_71, _T_72) @[el2_dec_tlu_ctl.scala 456:117] + mpc_halt_state_ns <= _T_73 @[el2_dec_tlu_ctl.scala 456:21] + node _T_74 = not(mpc_debug_run_ack_f) @[el2_dec_tlu_ctl.scala 457:74] + node _T_75 = and(mpc_debug_run_req_sync_pulse, _T_74) @[el2_dec_tlu_ctl.scala 457:72] + node _T_76 = or(mpc_run_state_f, _T_75) @[el2_dec_tlu_ctl.scala 457:40] + node _T_77 = not(dcsr_single_step_running_f) @[el2_dec_tlu_ctl.scala 457:127] + node _T_78 = and(debug_mode_status, _T_77) @[el2_dec_tlu_ctl.scala 457:125] + node _T_79 = and(_T_76, _T_78) @[el2_dec_tlu_ctl.scala 457:97] + mpc_run_state_ns <= _T_79 @[el2_dec_tlu_ctl.scala 457:20] + node _T_80 = or(dbg_halt_req_final, dcsr_single_step_done_f) @[el2_dec_tlu_ctl.scala 459:64] + node _T_81 = or(_T_80, trigger_hit_dmode_r_d1) @[el2_dec_tlu_ctl.scala 459:90] + node _T_82 = or(_T_81, ebreak_to_debug_mode_r_d1) @[el2_dec_tlu_ctl.scala 459:115] + node _T_83 = or(dbg_halt_state_f, _T_82) @[el2_dec_tlu_ctl.scala 459:42] + node _T_84 = not(io.dbg_resume_req) @[el2_dec_tlu_ctl.scala 459:147] + node _T_85 = and(_T_83, _T_84) @[el2_dec_tlu_ctl.scala 459:145] + dbg_halt_state_ns <= _T_85 @[el2_dec_tlu_ctl.scala 459:21] + node _T_86 = or(dbg_run_state_f, io.dbg_resume_req) @[el2_dec_tlu_ctl.scala 460:40] + node _T_87 = not(dcsr_single_step_running_f) @[el2_dec_tlu_ctl.scala 460:91] + node _T_88 = and(debug_mode_status, _T_87) @[el2_dec_tlu_ctl.scala 460:89] + node _T_89 = and(_T_86, _T_88) @[el2_dec_tlu_ctl.scala 460:61] + dbg_run_state_ns <= _T_89 @[el2_dec_tlu_ctl.scala 460:20] + node _T_90 = not(dbg_halt_state_f) @[el2_dec_tlu_ctl.scala 463:33] + node _T_91 = and(_T_90, mpc_halt_state_f) @[el2_dec_tlu_ctl.scala 463:51] + dec_tlu_mpc_halted_only_ns <= _T_91 @[el2_dec_tlu_ctl.scala 463:30] + node debug_brkpt_valid = or(ebreak_to_debug_mode_r_d1, trigger_hit_dmode_r_d1) @[el2_dec_tlu_ctl.scala 466:53] + node _T_92 = or(debug_brkpt_valid, debug_brkpt_status_f) @[el2_dec_tlu_ctl.scala 467:47] + node _T_93 = not(dcsr_single_step_running_f) @[el2_dec_tlu_ctl.scala 467:99] + node _T_94 = and(internal_dbg_halt_mode, _T_93) @[el2_dec_tlu_ctl.scala 467:97] + node _T_95 = and(_T_92, _T_94) @[el2_dec_tlu_ctl.scala 467:71] + debug_brkpt_status_ns <= _T_95 @[el2_dec_tlu_ctl.scala 467:25] + node _T_96 = and(mpc_halt_state_f, debug_mode_status) @[el2_dec_tlu_ctl.scala 470:45] + node _T_97 = and(_T_96, mpc_debug_halt_req_sync) @[el2_dec_tlu_ctl.scala 470:72] + node _T_98 = and(_T_97, core_empty) @[el2_dec_tlu_ctl.scala 470:98] + mpc_debug_halt_ack_ns <= _T_98 @[el2_dec_tlu_ctl.scala 470:25] + node _T_99 = not(dbg_halt_state_ns) @[el2_dec_tlu_ctl.scala 471:53] + node _T_100 = and(mpc_debug_run_req_sync, _T_99) @[el2_dec_tlu_ctl.scala 471:51] + node _T_101 = not(mpc_debug_halt_req_sync) @[el2_dec_tlu_ctl.scala 471:74] + node _T_102 = and(_T_100, _T_101) @[el2_dec_tlu_ctl.scala 471:72] + node _T_103 = and(mpc_debug_run_ack_f, mpc_debug_run_req_sync) @[el2_dec_tlu_ctl.scala 471:123] + node _T_104 = or(_T_102, _T_103) @[el2_dec_tlu_ctl.scala 471:100] + mpc_debug_run_ack_ns <= _T_104 @[el2_dec_tlu_ctl.scala 471:24] + io.mpc_debug_halt_ack <= mpc_debug_halt_ack_f @[el2_dec_tlu_ctl.scala 474:25] + io.mpc_debug_run_ack <= mpc_debug_run_ack_f @[el2_dec_tlu_ctl.scala 475:25] + io.debug_brkpt_status <= debug_brkpt_status_f @[el2_dec_tlu_ctl.scala 476:25] + node _T_105 = or(io.dbg_halt_req, dbg_halt_req_held) @[el2_dec_tlu_ctl.scala 479:47] + node dbg_halt_req_held_ns = and(_T_105, ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 479:68] + node _T_106 = or(io.dbg_halt_req, dbg_halt_req_held) @[el2_dec_tlu_ctl.scala 480:42] + node _T_107 = not(ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 480:65] + node _T_108 = and(_T_106, _T_107) @[el2_dec_tlu_ctl.scala 480:63] + dbg_halt_req_final <= _T_108 @[el2_dec_tlu_ctl.scala 480:22] + node _T_109 = or(dbg_halt_req_final, mpc_debug_halt_req_sync) @[el2_dec_tlu_ctl.scala 483:44] + node _T_110 = not(io.mpc_reset_run_req) @[el2_dec_tlu_ctl.scala 483:89] + node _T_111 = and(reset_delayed, _T_110) @[el2_dec_tlu_ctl.scala 483:87] + node _T_112 = or(_T_109, _T_111) @[el2_dec_tlu_ctl.scala 483:70] + node _T_113 = not(debug_mode_status) @[el2_dec_tlu_ctl.scala 483:115] + node _T_114 = and(_T_112, _T_113) @[el2_dec_tlu_ctl.scala 483:113] + node _T_115 = not(ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 483:143] + node debug_halt_req = and(_T_114, _T_115) @[el2_dec_tlu_ctl.scala 483:141] + node _T_116 = not(debug_resume_req_f) @[el2_dec_tlu_ctl.scala 485:26] + node _T_117 = not(dbg_halt_state_ns) @[el2_dec_tlu_ctl.scala 485:69] + node _T_118 = and(mpc_run_state_ns, _T_117) @[el2_dec_tlu_ctl.scala 485:67] + node _T_119 = not(mpc_halt_state_ns) @[el2_dec_tlu_ctl.scala 485:111] + node _T_120 = and(dbg_run_state_ns, _T_119) @[el2_dec_tlu_ctl.scala 485:109] + node _T_121 = or(_T_118, _T_120) @[el2_dec_tlu_ctl.scala 485:89] + node debug_resume_req = and(_T_116, _T_121) @[el2_dec_tlu_ctl.scala 485:46] + node _T_122 = or(debug_halt_req_f, pmu_fw_halt_req_f) @[el2_dec_tlu_ctl.scala 490:37] + node _T_123 = not(synchronous_flush_r) @[el2_dec_tlu_ctl.scala 490:60] + node _T_124 = and(_T_122, _T_123) @[el2_dec_tlu_ctl.scala 490:58] + node _T_125 = not(mret_r) @[el2_dec_tlu_ctl.scala 490:83] + node _T_126 = and(_T_124, _T_125) @[el2_dec_tlu_ctl.scala 490:81] + node _T_127 = not(halt_taken_f) @[el2_dec_tlu_ctl.scala 490:93] + node _T_128 = and(_T_126, _T_127) @[el2_dec_tlu_ctl.scala 490:91] + node _T_129 = not(dec_tlu_flush_noredir_r_d1) @[el2_dec_tlu_ctl.scala 490:109] + node _T_130 = and(_T_128, _T_129) @[el2_dec_tlu_ctl.scala 490:107] + node _T_131 = not(take_reset) @[el2_dec_tlu_ctl.scala 490:139] + node take_halt = and(_T_130, _T_131) @[el2_dec_tlu_ctl.scala 490:137] + node _T_132 = not(dec_tlu_flush_pause_r_d1) @[el2_dec_tlu_ctl.scala 493:50] + node _T_133 = and(dec_tlu_flush_noredir_r_d1, _T_132) @[el2_dec_tlu_ctl.scala 493:48] + node _T_134 = not(take_ext_int_start_d1) @[el2_dec_tlu_ctl.scala 493:78] + node _T_135 = and(_T_133, _T_134) @[el2_dec_tlu_ctl.scala 493:76] + node _T_136 = not(dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 493:120] + node _T_137 = and(halt_taken_f, _T_136) @[el2_dec_tlu_ctl.scala 493:118] + node _T_138 = not(pmu_fw_tlu_halted_f) @[el2_dec_tlu_ctl.scala 493:140] + node _T_139 = and(_T_137, _T_138) @[el2_dec_tlu_ctl.scala 493:138] + node _T_140 = not(interrupt_valid_r_d1) @[el2_dec_tlu_ctl.scala 493:163] + node _T_141 = and(_T_139, _T_140) @[el2_dec_tlu_ctl.scala 493:161] + node halt_taken = or(_T_135, _T_141) @[el2_dec_tlu_ctl.scala 493:102] + node _T_142 = and(io.lsu_idle_any, lsu_idle_any_f) @[el2_dec_tlu_ctl.scala 497:47] + node _T_143 = and(_T_142, io.ifu_miss_state_idle) @[el2_dec_tlu_ctl.scala 497:64] + node _T_144 = and(_T_143, ifu_miss_state_idle_f) @[el2_dec_tlu_ctl.scala 497:89] + node _T_145 = not(debug_halt_req) @[el2_dec_tlu_ctl.scala 497:115] + node _T_146 = and(_T_144, _T_145) @[el2_dec_tlu_ctl.scala 497:113] + node _T_147 = not(debug_halt_req_d1) @[el2_dec_tlu_ctl.scala 497:133] + node _T_148 = and(_T_146, _T_147) @[el2_dec_tlu_ctl.scala 497:131] + node _T_149 = not(io.dec_div_active) @[el2_dec_tlu_ctl.scala 497:154] + node _T_150 = and(_T_148, _T_149) @[el2_dec_tlu_ctl.scala 497:152] + node _T_151 = or(force_halt, _T_150) @[el2_dec_tlu_ctl.scala 497:28] + core_empty <= _T_151 @[el2_dec_tlu_ctl.scala 497:14] + node _T_152 = not(debug_mode_status) @[el2_dec_tlu_ctl.scala 503:31] + node _T_153 = and(_T_152, debug_halt_req) @[el2_dec_tlu_ctl.scala 503:57] + node _T_154 = or(_T_153, dcsr_single_step_done_f) @[el2_dec_tlu_ctl.scala 503:75] + node _T_155 = or(_T_154, trigger_hit_dmode_r_d1) @[el2_dec_tlu_ctl.scala 503:101] + node enter_debug_halt_req = or(_T_155, ebreak_to_debug_mode_r_d1) @[el2_dec_tlu_ctl.scala 503:126] + node _T_156 = bits(dcsr, 2, 2) @[el2_dec_tlu_ctl.scala 506:105] + node _T_157 = not(_T_156) @[el2_dec_tlu_ctl.scala 506:100] + node _T_158 = and(debug_resume_req_f, _T_157) @[el2_dec_tlu_ctl.scala 506:98] + node _T_159 = not(_T_158) @[el2_dec_tlu_ctl.scala 506:77] + node _T_160 = and(debug_mode_status, _T_159) @[el2_dec_tlu_ctl.scala 506:75] + node _T_161 = or(debug_halt_req_ns, _T_160) @[el2_dec_tlu_ctl.scala 506:47] + internal_dbg_halt_mode <= _T_161 @[el2_dec_tlu_ctl.scala 506:26] + node _T_162 = not(dcsr_single_step_running_f) @[el2_dec_tlu_ctl.scala 508:61] + node allow_dbg_halt_csr_write = and(debug_mode_status, _T_162) @[el2_dec_tlu_ctl.scala 508:59] + node _T_163 = and(debug_halt_req_f, core_empty) @[el2_dec_tlu_ctl.scala 513:42] + node _T_164 = and(_T_163, halt_taken) @[el2_dec_tlu_ctl.scala 513:55] + node _T_165 = not(debug_resume_req_f) @[el2_dec_tlu_ctl.scala 513:91] + node _T_166 = and(dbg_tlu_halted_f, _T_165) @[el2_dec_tlu_ctl.scala 513:89] + node dbg_tlu_halted = or(_T_164, _T_166) @[el2_dec_tlu_ctl.scala 513:69] + node _T_167 = not(dbg_tlu_halted) @[el2_dec_tlu_ctl.scala 514:67] + node _T_168 = and(debug_halt_req_f, _T_167) @[el2_dec_tlu_ctl.scala 514:65] + node _T_169 = or(enter_debug_halt_req, _T_168) @[el2_dec_tlu_ctl.scala 514:45] + debug_halt_req_ns <= _T_169 @[el2_dec_tlu_ctl.scala 514:21] + node _T_170 = and(debug_resume_req_f, dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 515:43] + node resume_ack_ns = and(_T_170, dbg_run_state_ns) @[el2_dec_tlu_ctl.scala 515:62] + node _T_171 = not(io.dec_tlu_dbg_halted) @[el2_dec_tlu_ctl.scala 517:55] + node _T_172 = and(io.dec_tlu_i0_valid_r, _T_171) @[el2_dec_tlu_ctl.scala 517:53] + node _T_173 = bits(dcsr, 2, 2) @[el2_dec_tlu_ctl.scala 517:84] + node _T_174 = and(_T_172, _T_173) @[el2_dec_tlu_ctl.scala 517:78] + node _T_175 = not(rfpc_i0_r) @[el2_dec_tlu_ctl.scala 517:98] + node dcsr_single_step_done = and(_T_174, _T_175) @[el2_dec_tlu_ctl.scala 517:96] + node _T_176 = bits(dcsr, 2, 2) @[el2_dec_tlu_ctl.scala 519:60] + node _T_177 = and(debug_resume_req_f, _T_176) @[el2_dec_tlu_ctl.scala 519:54] + node _T_178 = not(dcsr_single_step_done_f) @[el2_dec_tlu_ctl.scala 519:105] + node _T_179 = and(dcsr_single_step_running_f, _T_178) @[el2_dec_tlu_ctl.scala 519:103] + node dcsr_single_step_running = or(_T_177, _T_179) @[el2_dec_tlu_ctl.scala 519:73] + node dbg_cmd_done_ns = and(io.dec_tlu_i0_valid_r, io.dec_tlu_dbg_halted) @[el2_dec_tlu_ctl.scala 521:47] + node _T_180 = or(trigger_hit_dmode_r, ebreak_to_debug_mode_r) @[el2_dec_tlu_ctl.scala 524:51] + node _T_181 = not(io.dec_tlu_flush_lower_wb) @[el2_dec_tlu_ctl.scala 524:106] + node _T_182 = and(request_debug_mode_r_d1, _T_181) @[el2_dec_tlu_ctl.scala 524:104] + node request_debug_mode_r = or(_T_180, _T_182) @[el2_dec_tlu_ctl.scala 524:77] + node _T_183 = or(request_debug_mode_r_d1, request_debug_mode_done_f) @[el2_dec_tlu_ctl.scala 526:58] + node _T_184 = not(dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 526:89] + node request_debug_mode_done = and(_T_183, _T_184) @[el2_dec_tlu_ctl.scala 526:87] + reg _T_185 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 529:73] + _T_185 <= io.dec_tlu_flush_noredir_r @[el2_dec_tlu_ctl.scala 529:73] + dec_tlu_flush_noredir_r_d1 <= _T_185 @[el2_dec_tlu_ctl.scala 529:41] + reg _T_186 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 530:81] + _T_186 <= halt_taken @[el2_dec_tlu_ctl.scala 530:81] + halt_taken_f <= _T_186 @[el2_dec_tlu_ctl.scala 530:49] + reg _T_187 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 531:89] + _T_187 <= io.lsu_idle_any @[el2_dec_tlu_ctl.scala 531:89] + lsu_idle_any_f <= _T_187 @[el2_dec_tlu_ctl.scala 531:57] + reg _T_188 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 532:73] + _T_188 <= io.ifu_miss_state_idle @[el2_dec_tlu_ctl.scala 532:73] + ifu_miss_state_idle_f <= _T_188 @[el2_dec_tlu_ctl.scala 532:41] + reg _T_189 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 533:81] + _T_189 <= dbg_tlu_halted @[el2_dec_tlu_ctl.scala 533:81] + dbg_tlu_halted_f <= _T_189 @[el2_dec_tlu_ctl.scala 533:49] + reg _T_190 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 534:73] + _T_190 <= resume_ack_ns @[el2_dec_tlu_ctl.scala 534:73] + io.dec_tlu_resume_ack <= _T_190 @[el2_dec_tlu_ctl.scala 534:41] + reg _T_191 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 535:81] + _T_191 <= debug_halt_req_ns @[el2_dec_tlu_ctl.scala 535:81] + debug_halt_req_f <= _T_191 @[el2_dec_tlu_ctl.scala 535:49] + reg _T_192 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 536:81] + _T_192 <= debug_resume_req @[el2_dec_tlu_ctl.scala 536:81] + debug_resume_req_f <= _T_192 @[el2_dec_tlu_ctl.scala 536:49] + reg _T_193 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 537:81] + _T_193 <= trigger_hit_dmode_r @[el2_dec_tlu_ctl.scala 537:81] + trigger_hit_dmode_r_d1 <= _T_193 @[el2_dec_tlu_ctl.scala 537:49] + reg _T_194 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 538:81] + _T_194 <= dcsr_single_step_done @[el2_dec_tlu_ctl.scala 538:81] + dcsr_single_step_done_f <= _T_194 @[el2_dec_tlu_ctl.scala 538:49] + reg _T_195 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 539:81] + _T_195 <= debug_halt_req @[el2_dec_tlu_ctl.scala 539:81] + debug_halt_req_d1 <= _T_195 @[el2_dec_tlu_ctl.scala 539:49] + reg dec_tlu_wr_pause_r_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 540:73] + dec_tlu_wr_pause_r_d1 <= io.dec_tlu_wr_pause_r @[el2_dec_tlu_ctl.scala 540:73] + reg dec_pause_state_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 541:73] + dec_pause_state_f <= io.dec_pause_state @[el2_dec_tlu_ctl.scala 541:73] + reg _T_196 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 542:81] + _T_196 <= request_debug_mode_r @[el2_dec_tlu_ctl.scala 542:81] + request_debug_mode_r_d1 <= _T_196 @[el2_dec_tlu_ctl.scala 542:49] + reg _T_197 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 543:73] + _T_197 <= request_debug_mode_done @[el2_dec_tlu_ctl.scala 543:73] + request_debug_mode_done_f <= _T_197 @[el2_dec_tlu_ctl.scala 543:41] + reg _T_198 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 544:73] + _T_198 <= dcsr_single_step_running @[el2_dec_tlu_ctl.scala 544:73] + dcsr_single_step_running_f <= _T_198 @[el2_dec_tlu_ctl.scala 544:41] + reg _T_199 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 545:73] + _T_199 <= io.dec_tlu_flush_pause_r @[el2_dec_tlu_ctl.scala 545:73] + dec_tlu_flush_pause_r_d1 <= _T_199 @[el2_dec_tlu_ctl.scala 545:41] + reg _T_200 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 546:81] + _T_200 <= dbg_halt_req_held_ns @[el2_dec_tlu_ctl.scala 546:81] + dbg_halt_req_held <= _T_200 @[el2_dec_tlu_ctl.scala 546:49] + io.dec_tlu_debug_stall <= debug_halt_req_f @[el2_dec_tlu_ctl.scala 549:41] + io.dec_tlu_dbg_halted <= dbg_tlu_halted_f @[el2_dec_tlu_ctl.scala 550:41] + io.dec_tlu_debug_mode <= debug_mode_status @[el2_dec_tlu_ctl.scala 551:41] + dec_tlu_pmu_fw_halted <= pmu_fw_tlu_halted_f @[el2_dec_tlu_ctl.scala 552:41] + node _T_201 = and(fence_i_r, internal_dbg_halt_mode) @[el2_dec_tlu_ctl.scala 555:56] + node _T_202 = or(take_halt, _T_201) @[el2_dec_tlu_ctl.scala 555:43] + node _T_203 = or(_T_202, io.dec_tlu_flush_pause_r) @[el2_dec_tlu_ctl.scala 555:82] + node _T_204 = and(i0_trigger_hit_r, trigger_hit_dmode_r) @[el2_dec_tlu_ctl.scala 555:129] + node _T_205 = or(_T_203, _T_204) @[el2_dec_tlu_ctl.scala 555:109] + node _T_206 = or(_T_205, take_ext_int_start) @[el2_dec_tlu_ctl.scala 555:152] + io.dec_tlu_flush_noredir_r <= _T_206 @[el2_dec_tlu_ctl.scala 555:30] + io.dec_tlu_flush_extint <= take_ext_int_start @[el2_dec_tlu_ctl.scala 557:27] + node _T_207 = not(interrupt_valid_r) @[el2_dec_tlu_ctl.scala 560:55] + node _T_208 = and(dec_tlu_wr_pause_r_d1, _T_207) @[el2_dec_tlu_ctl.scala 560:53] + node _T_209 = not(take_ext_int_start) @[el2_dec_tlu_ctl.scala 560:76] + node _T_210 = and(_T_208, _T_209) @[el2_dec_tlu_ctl.scala 560:74] + io.dec_tlu_flush_pause_r <= _T_210 @[el2_dec_tlu_ctl.scala 560:28] + node _T_211 = not(io.dec_pause_state) @[el2_dec_tlu_ctl.scala 562:22] + node _T_212 = and(_T_211, dec_pause_state_f) @[el2_dec_tlu_ctl.scala 562:42] + node _T_213 = or(ext_int_ready, ce_int_ready) @[el2_dec_tlu_ctl.scala 562:80] + node _T_214 = or(_T_213, timer_int_ready) @[el2_dec_tlu_ctl.scala 562:95] + node _T_215 = or(_T_214, soft_int_ready) @[el2_dec_tlu_ctl.scala 562:113] + node _T_216 = or(_T_215, int_timer0_int_hold_f) @[el2_dec_tlu_ctl.scala 562:130] + node _T_217 = or(_T_216, int_timer1_int_hold_f) @[el2_dec_tlu_ctl.scala 562:154] + node _T_218 = or(_T_217, nmi_int_detected) @[el2_dec_tlu_ctl.scala 562:178] + node _T_219 = or(_T_218, ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 562:197] + node _T_220 = not(_T_219) @[el2_dec_tlu_ctl.scala 562:64] + node _T_221 = and(_T_212, _T_220) @[el2_dec_tlu_ctl.scala 562:62] + node _T_222 = not(interrupt_valid_r_d1) @[el2_dec_tlu_ctl.scala 562:220] + node _T_223 = and(_T_221, _T_222) @[el2_dec_tlu_ctl.scala 562:218] + node _T_224 = not(debug_halt_req_f) @[el2_dec_tlu_ctl.scala 562:244] + node _T_225 = and(_T_223, _T_224) @[el2_dec_tlu_ctl.scala 562:242] + node _T_226 = not(pmu_fw_halt_req_f) @[el2_dec_tlu_ctl.scala 562:264] + node _T_227 = and(_T_225, _T_226) @[el2_dec_tlu_ctl.scala 562:262] + node _T_228 = not(halt_taken_f) @[el2_dec_tlu_ctl.scala 562:285] + node _T_229 = and(_T_227, _T_228) @[el2_dec_tlu_ctl.scala 562:283] + pause_expired_r <= _T_229 @[el2_dec_tlu_ctl.scala 562:19] + node _T_230 = bits(dcsr, 2, 2) @[el2_dec_tlu_ctl.scala 564:66] + node _T_231 = and(io.dec_tlu_flush_lower_r, _T_230) @[el2_dec_tlu_ctl.scala 564:60] + node _T_232 = or(io.dec_tlu_resume_ack, dcsr_single_step_running) @[el2_dec_tlu_ctl.scala 564:103] + node _T_233 = and(_T_231, _T_232) @[el2_dec_tlu_ctl.scala 564:78] + node _T_234 = not(io.dec_tlu_flush_noredir_r) @[el2_dec_tlu_ctl.scala 564:133] + node _T_235 = and(_T_233, _T_234) @[el2_dec_tlu_ctl.scala 564:131] + io.dec_tlu_flush_leak_one_r <= _T_235 @[el2_dec_tlu_ctl.scala 564:31] + node _T_236 = or(ic_perr_r_d1, iccm_sbecc_r_d1) @[el2_dec_tlu_ctl.scala 565:70] + node _T_237 = and(io.dec_tlu_flush_lower_r, _T_236) @[el2_dec_tlu_ctl.scala 565:54] + io.dec_tlu_flush_err_r <= _T_237 @[el2_dec_tlu_ctl.scala 565:26] + io.dec_dbg_cmd_done <= dbg_cmd_done_ns @[el2_dec_tlu_ctl.scala 568:23] + node _T_238 = and(illegal_r, io.dec_dbg_cmd_done) @[el2_dec_tlu_ctl.scala 569:36] + io.dec_dbg_cmd_fail <= _T_238 @[el2_dec_tlu_ctl.scala 569:23] + node _T_239 = bits(mtdata1_t[3], 2, 2) @[el2_dec_tlu_ctl.scala 582:42] + node _T_240 = bits(mtdata1_t[2], 2, 2) @[el2_dec_tlu_ctl.scala 582:69] + node _T_241 = bits(mtdata1_t[1], 2, 2) @[el2_dec_tlu_ctl.scala 582:96] + node _T_242 = bits(mtdata1_t[0], 2, 2) @[el2_dec_tlu_ctl.scala 582:123] + node _T_243 = cat(_T_241, _T_242) @[Cat.scala 29:58] + node _T_244 = cat(_T_239, _T_240) @[Cat.scala 29:58] + node trigger_execute = cat(_T_244, _T_243) @[Cat.scala 29:58] + node _T_245 = bits(mtdata1_t[3], 7, 7) @[el2_dec_tlu_ctl.scala 583:44] + node _T_246 = bits(mtdata1_t[2], 7, 7) @[el2_dec_tlu_ctl.scala 583:71] + node _T_247 = bits(mtdata1_t[1], 7, 7) @[el2_dec_tlu_ctl.scala 583:98] + node _T_248 = bits(mtdata1_t[0], 7, 7) @[el2_dec_tlu_ctl.scala 583:125] + node _T_249 = cat(_T_247, _T_248) @[Cat.scala 29:58] + node _T_250 = cat(_T_245, _T_246) @[Cat.scala 29:58] + node trigger_data = cat(_T_250, _T_249) @[Cat.scala 29:58] + node _T_251 = bits(mtdata1_t[3], 1, 1) @[el2_dec_tlu_ctl.scala 584:44] + node _T_252 = bits(mtdata1_t[2], 1, 1) @[el2_dec_tlu_ctl.scala 584:71] + node _T_253 = bits(mtdata1_t[1], 1, 1) @[el2_dec_tlu_ctl.scala 584:98] + node _T_254 = bits(mtdata1_t[0], 1, 1) @[el2_dec_tlu_ctl.scala 584:125] + node _T_255 = cat(_T_253, _T_254) @[Cat.scala 29:58] + node _T_256 = cat(_T_251, _T_252) @[Cat.scala 29:58] + node trigger_store = cat(_T_256, _T_255) @[Cat.scala 29:58] + node _T_257 = bits(mtdata1_t[3], 6, 6) @[el2_dec_tlu_ctl.scala 587:45] + node _T_258 = bits(mstatus, 0, 0) @[el2_dec_tlu_ctl.scala 587:71] + node _T_259 = or(_T_257, _T_258) @[el2_dec_tlu_ctl.scala 587:62] + node _T_260 = bits(mtdata1_t[3], 3, 3) @[el2_dec_tlu_ctl.scala 587:100] + node _T_261 = and(_T_259, _T_260) @[el2_dec_tlu_ctl.scala 587:86] + node _T_262 = bits(mtdata1_t[2], 6, 6) @[el2_dec_tlu_ctl.scala 587:133] + node _T_263 = bits(mstatus, 0, 0) @[el2_dec_tlu_ctl.scala 587:159] + node _T_264 = or(_T_262, _T_263) @[el2_dec_tlu_ctl.scala 587:150] + node _T_265 = bits(mtdata1_t[2], 3, 3) @[el2_dec_tlu_ctl.scala 587:188] + node _T_266 = and(_T_264, _T_265) @[el2_dec_tlu_ctl.scala 587:174] + node _T_267 = bits(mtdata1_t[1], 6, 6) @[el2_dec_tlu_ctl.scala 587:222] + node _T_268 = bits(mstatus, 0, 0) @[el2_dec_tlu_ctl.scala 587:248] + node _T_269 = or(_T_267, _T_268) @[el2_dec_tlu_ctl.scala 587:239] + node _T_270 = bits(mtdata1_t[1], 3, 3) @[el2_dec_tlu_ctl.scala 587:277] + node _T_271 = and(_T_269, _T_270) @[el2_dec_tlu_ctl.scala 587:263] + node _T_272 = bits(mtdata1_t[0], 6, 6) @[el2_dec_tlu_ctl.scala 587:311] + node _T_273 = bits(mstatus, 0, 0) @[el2_dec_tlu_ctl.scala 587:337] + node _T_274 = or(_T_272, _T_273) @[el2_dec_tlu_ctl.scala 587:328] + node _T_275 = bits(mtdata1_t[0], 3, 3) @[el2_dec_tlu_ctl.scala 587:366] + node _T_276 = and(_T_274, _T_275) @[el2_dec_tlu_ctl.scala 587:352] + node _T_277 = cat(_T_271, _T_276) @[Cat.scala 29:58] + node _T_278 = cat(_T_261, _T_266) @[Cat.scala 29:58] + node trigger_enabled = cat(_T_278, _T_277) @[Cat.scala 29:58] + node _T_279 = and(trigger_execute, trigger_data) @[el2_dec_tlu_ctl.scala 590:56] + node _T_280 = bits(inst_acc_r_raw, 0, 0) @[Bitwise.scala 72:15] + node _T_281 = mux(_T_280, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_282 = and(_T_279, _T_281) @[el2_dec_tlu_ctl.scala 590:71] + node _T_283 = or(io.exu_i0_br_error_r, io.exu_i0_br_start_error_r) @[el2_dec_tlu_ctl.scala 590:128] + node _T_284 = bits(_T_283, 0, 0) @[Bitwise.scala 72:15] + node _T_285 = mux(_T_284, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_286 = or(_T_282, _T_285) @[el2_dec_tlu_ctl.scala 590:97] + node i0_iside_trigger_has_pri_r = not(_T_286) @[el2_dec_tlu_ctl.scala 590:37] + node _T_287 = and(trigger_store, trigger_data) @[el2_dec_tlu_ctl.scala 593:50] + node _T_288 = bits(lsu_i0_exc_r_raw, 0, 0) @[Bitwise.scala 72:15] + node _T_289 = mux(_T_288, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_290 = and(_T_287, _T_289) @[el2_dec_tlu_ctl.scala 593:65] + node i0_lsu_trigger_has_pri_r = not(_T_290) @[el2_dec_tlu_ctl.scala 593:34] + node _T_291 = bits(io.dec_tlu_i0_valid_r, 0, 0) @[Bitwise.scala 72:15] + node _T_292 = mux(_T_291, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_293 = bits(io.dec_tlu_packet_r.i0trigger, 3, 0) @[el2_dec_tlu_ctl.scala 598:83] + node _T_294 = and(_T_292, _T_293) @[el2_dec_tlu_ctl.scala 598:52] + node _T_295 = and(_T_294, i0_iside_trigger_has_pri_r) @[el2_dec_tlu_ctl.scala 598:89] + node _T_296 = and(_T_295, i0_lsu_trigger_has_pri_r) @[el2_dec_tlu_ctl.scala 598:118] + node i0trigger_qual_r = and(_T_296, trigger_enabled) @[el2_dec_tlu_ctl.scala 598:145] + node _T_297 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_dbg_halted) @[el2_dec_tlu_ctl.scala 600:57] + node _T_298 = bits(_T_297, 0, 0) @[Bitwise.scala 72:15] + node _T_299 = mux(_T_298, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_300 = not(_T_299) @[el2_dec_tlu_ctl.scala 600:22] + node i0_trigger_r = and(_T_300, i0trigger_qual_r) @[el2_dec_tlu_ctl.scala 600:83] + node _T_301 = bits(i0_trigger_r, 3, 3) @[el2_dec_tlu_ctl.scala 603:52] + node _T_302 = bits(mtdata1_t[2], 5, 5) @[el2_dec_tlu_ctl.scala 603:72] + node _T_303 = not(_T_302) @[el2_dec_tlu_ctl.scala 603:59] + node _T_304 = bits(i0_trigger_r, 2, 2) @[el2_dec_tlu_ctl.scala 603:102] + node _T_305 = or(_T_303, _T_304) @[el2_dec_tlu_ctl.scala 603:88] + node _T_306 = and(_T_301, _T_305) @[el2_dec_tlu_ctl.scala 603:56] + node _T_307 = bits(i0_trigger_r, 2, 2) @[el2_dec_tlu_ctl.scala 603:120] + node _T_308 = bits(mtdata1_t[2], 5, 5) @[el2_dec_tlu_ctl.scala 603:140] + node _T_309 = not(_T_308) @[el2_dec_tlu_ctl.scala 603:127] + node _T_310 = bits(i0_trigger_r, 3, 3) @[el2_dec_tlu_ctl.scala 603:170] + node _T_311 = or(_T_309, _T_310) @[el2_dec_tlu_ctl.scala 603:156] + node _T_312 = and(_T_307, _T_311) @[el2_dec_tlu_ctl.scala 603:124] + node _T_313 = bits(i0_trigger_r, 1, 1) @[el2_dec_tlu_ctl.scala 603:188] + node _T_314 = bits(mtdata1_t[0], 5, 5) @[el2_dec_tlu_ctl.scala 603:208] + node _T_315 = not(_T_314) @[el2_dec_tlu_ctl.scala 603:195] + node _T_316 = bits(i0_trigger_r, 0, 0) @[el2_dec_tlu_ctl.scala 603:238] + node _T_317 = or(_T_315, _T_316) @[el2_dec_tlu_ctl.scala 603:224] + node _T_318 = and(_T_313, _T_317) @[el2_dec_tlu_ctl.scala 603:192] + node _T_319 = bits(i0_trigger_r, 0, 0) @[el2_dec_tlu_ctl.scala 603:256] + node _T_320 = bits(mtdata1_t[0], 5, 5) @[el2_dec_tlu_ctl.scala 603:276] + node _T_321 = not(_T_320) @[el2_dec_tlu_ctl.scala 603:263] + node _T_322 = bits(i0_trigger_r, 1, 1) @[el2_dec_tlu_ctl.scala 603:306] + node _T_323 = or(_T_321, _T_322) @[el2_dec_tlu_ctl.scala 603:292] + node _T_324 = and(_T_319, _T_323) @[el2_dec_tlu_ctl.scala 603:260] + node _T_325 = cat(_T_318, _T_324) @[Cat.scala 29:58] + node _T_326 = cat(_T_306, _T_312) @[Cat.scala 29:58] + node i0_trigger_chain_masked_r = cat(_T_326, _T_325) @[Cat.scala 29:58] + node i0_trigger_hit_raw_r = orr(i0_trigger_chain_masked_r) @[el2_dec_tlu_ctl.scala 606:56] + i0_trigger_hit_r <= i0_trigger_hit_raw_r @[el2_dec_tlu_ctl.scala 608:25] + node _T_327 = bits(mtdata1_t[3], 6, 6) @[el2_dec_tlu_ctl.scala 612:44] + node _T_328 = bits(mtdata1_t[3], 9, 9) @[el2_dec_tlu_ctl.scala 612:75] + node _T_329 = and(_T_327, _T_328) @[el2_dec_tlu_ctl.scala 612:61] + node _T_330 = bits(mtdata1_t[2], 6, 6) @[el2_dec_tlu_ctl.scala 612:104] + node _T_331 = bits(mtdata1_t[2], 9, 9) @[el2_dec_tlu_ctl.scala 612:135] + node _T_332 = and(_T_330, _T_331) @[el2_dec_tlu_ctl.scala 612:121] + node _T_333 = bits(mtdata1_t[1], 6, 6) @[el2_dec_tlu_ctl.scala 612:164] + node _T_334 = bits(mtdata1_t[1], 9, 9) @[el2_dec_tlu_ctl.scala 612:195] + node _T_335 = and(_T_333, _T_334) @[el2_dec_tlu_ctl.scala 612:181] + node _T_336 = bits(mtdata1_t[0], 6, 6) @[el2_dec_tlu_ctl.scala 612:224] + node _T_337 = bits(mtdata1_t[0], 9, 9) @[el2_dec_tlu_ctl.scala 612:255] + node _T_338 = and(_T_336, _T_337) @[el2_dec_tlu_ctl.scala 612:241] + node _T_339 = cat(_T_335, _T_338) @[Cat.scala 29:58] + node _T_340 = cat(_T_329, _T_332) @[Cat.scala 29:58] + node trigger_action = cat(_T_340, _T_339) @[Cat.scala 29:58] + node _T_341 = bits(i0_trigger_hit_r, 0, 0) @[Bitwise.scala 72:15] + node _T_342 = mux(_T_341, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node update_hit_bit_r = and(_T_342, i0_trigger_chain_masked_r) @[el2_dec_tlu_ctl.scala 615:56] + node _T_343 = and(i0_trigger_chain_masked_r, trigger_action) @[el2_dec_tlu_ctl.scala 618:56] + node i0_trigger_action_r = orr(_T_343) @[el2_dec_tlu_ctl.scala 618:74] + node _T_344 = and(i0_trigger_hit_r, i0_trigger_action_r) @[el2_dec_tlu_ctl.scala 620:44] + trigger_hit_dmode_r <= _T_344 @[el2_dec_tlu_ctl.scala 620:23] + node _T_345 = not(trigger_hit_dmode_r) @[el2_dec_tlu_ctl.scala 622:54] + node mepc_trigger_hit_sel_pc_r = and(i0_trigger_hit_r, _T_345) @[el2_dec_tlu_ctl.scala 622:52] + node _T_346 = not(io.dec_tlu_debug_mode) @[el2_dec_tlu_ctl.scala 649:56] + node _T_347 = and(i_cpu_halt_req_sync, _T_346) @[el2_dec_tlu_ctl.scala 649:54] + node _T_348 = not(ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 649:81] + node i_cpu_halt_req_sync_qual = and(_T_347, _T_348) @[el2_dec_tlu_ctl.scala 649:79] + node _T_349 = not(io.dec_tlu_debug_mode) @[el2_dec_tlu_ctl.scala 650:54] + node _T_350 = and(i_cpu_run_req_sync, _T_349) @[el2_dec_tlu_ctl.scala 650:52] + node _T_351 = and(_T_350, pmu_fw_tlu_halted_f) @[el2_dec_tlu_ctl.scala 650:77] + node _T_352 = not(ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 650:101] + node i_cpu_run_req_sync_qual = and(_T_351, _T_352) @[el2_dec_tlu_ctl.scala 650:99] + reg i_cpu_halt_req_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 652:80] + i_cpu_halt_req_d1 <= i_cpu_halt_req_sync_qual @[el2_dec_tlu_ctl.scala 652:80] + reg i_cpu_run_req_d1_raw : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 653:72] + i_cpu_run_req_d1_raw <= i_cpu_run_req_sync_qual @[el2_dec_tlu_ctl.scala 653:72] + reg _T_353 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 654:73] + _T_353 <= cpu_halt_status @[el2_dec_tlu_ctl.scala 654:73] + io.o_cpu_halt_status <= _T_353 @[el2_dec_tlu_ctl.scala 654:41] + reg _T_354 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 655:81] + _T_354 <= cpu_halt_ack @[el2_dec_tlu_ctl.scala 655:81] + io.o_cpu_halt_ack <= _T_354 @[el2_dec_tlu_ctl.scala 655:49] + reg _T_355 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 656:81] + _T_355 <= cpu_run_ack @[el2_dec_tlu_ctl.scala 656:81] + io.o_cpu_run_ack <= _T_355 @[el2_dec_tlu_ctl.scala 656:49] + reg internal_pmu_fw_halt_mode_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 657:66] + internal_pmu_fw_halt_mode_f <= internal_pmu_fw_halt_mode @[el2_dec_tlu_ctl.scala 657:66] + reg _T_356 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 658:73] + _T_356 <= pmu_fw_halt_req_ns @[el2_dec_tlu_ctl.scala 658:73] + pmu_fw_halt_req_f <= _T_356 @[el2_dec_tlu_ctl.scala 658:41] + reg _T_357 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 659:73] + _T_357 <= pmu_fw_tlu_halted @[el2_dec_tlu_ctl.scala 659:73] + pmu_fw_tlu_halted_f <= _T_357 @[el2_dec_tlu_ctl.scala 659:41] + reg _T_358 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 660:65] + _T_358 <= int_timer0_int_hold @[el2_dec_tlu_ctl.scala 660:65] + int_timer0_int_hold_f <= _T_358 @[el2_dec_tlu_ctl.scala 660:33] + reg _T_359 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 661:65] + _T_359 <= int_timer1_int_hold @[el2_dec_tlu_ctl.scala 661:65] + int_timer1_int_hold_f <= _T_359 @[el2_dec_tlu_ctl.scala 661:33] + node _T_360 = not(i_cpu_halt_req_d1) @[el2_dec_tlu_ctl.scala 665:51] + node ext_halt_pulse = and(i_cpu_halt_req_sync_qual, _T_360) @[el2_dec_tlu_ctl.scala 665:49] + node enter_pmu_fw_halt_req = or(ext_halt_pulse, fw_halt_req) @[el2_dec_tlu_ctl.scala 666:47] + node _T_361 = not(pmu_fw_tlu_halted) @[el2_dec_tlu_ctl.scala 667:71] + node _T_362 = and(pmu_fw_halt_req_f, _T_361) @[el2_dec_tlu_ctl.scala 667:69] + node _T_363 = or(enter_pmu_fw_halt_req, _T_362) @[el2_dec_tlu_ctl.scala 667:48] + node _T_364 = not(debug_halt_req_f) @[el2_dec_tlu_ctl.scala 667:94] + node _T_365 = and(_T_363, _T_364) @[el2_dec_tlu_ctl.scala 667:92] + pmu_fw_halt_req_ns <= _T_365 @[el2_dec_tlu_ctl.scala 667:22] + node _T_366 = not(i_cpu_run_req_d1) @[el2_dec_tlu_ctl.scala 668:84] + node _T_367 = and(internal_pmu_fw_halt_mode_f, _T_366) @[el2_dec_tlu_ctl.scala 668:82] + node _T_368 = not(debug_halt_req_f) @[el2_dec_tlu_ctl.scala 668:104] + node _T_369 = and(_T_367, _T_368) @[el2_dec_tlu_ctl.scala 668:102] + node _T_370 = or(pmu_fw_halt_req_ns, _T_369) @[el2_dec_tlu_ctl.scala 668:51] + internal_pmu_fw_halt_mode <= _T_370 @[el2_dec_tlu_ctl.scala 668:29] + node _T_371 = and(pmu_fw_halt_req_f, core_empty) @[el2_dec_tlu_ctl.scala 671:44] + node _T_372 = and(_T_371, halt_taken) @[el2_dec_tlu_ctl.scala 671:57] + node _T_373 = not(enter_debug_halt_req) @[el2_dec_tlu_ctl.scala 671:72] + node _T_374 = and(_T_372, _T_373) @[el2_dec_tlu_ctl.scala 671:70] + node _T_375 = not(i_cpu_run_req_d1) @[el2_dec_tlu_ctl.scala 671:120] + node _T_376 = and(pmu_fw_tlu_halted_f, _T_375) @[el2_dec_tlu_ctl.scala 671:118] + node _T_377 = or(_T_374, _T_376) @[el2_dec_tlu_ctl.scala 671:95] + node _T_378 = not(debug_halt_req_f) @[el2_dec_tlu_ctl.scala 671:142] + node _T_379 = and(_T_377, _T_378) @[el2_dec_tlu_ctl.scala 671:140] + pmu_fw_tlu_halted <= _T_379 @[el2_dec_tlu_ctl.scala 671:21] + node _T_380 = and(i_cpu_halt_req_d1, pmu_fw_tlu_halted_f) @[el2_dec_tlu_ctl.scala 673:37] + cpu_halt_ack <= _T_380 @[el2_dec_tlu_ctl.scala 673:16] + node _T_381 = not(i_cpu_run_req_d1) @[el2_dec_tlu_ctl.scala 674:45] + node _T_382 = and(pmu_fw_tlu_halted_f, _T_381) @[el2_dec_tlu_ctl.scala 674:43] + node _T_383 = not(i_cpu_run_req_d1) @[el2_dec_tlu_ctl.scala 674:90] + node _T_384 = and(io.o_cpu_halt_status, _T_383) @[el2_dec_tlu_ctl.scala 674:88] + node _T_385 = not(debug_mode_status) @[el2_dec_tlu_ctl.scala 674:110] + node _T_386 = and(_T_384, _T_385) @[el2_dec_tlu_ctl.scala 674:108] + node _T_387 = or(_T_382, _T_386) @[el2_dec_tlu_ctl.scala 674:64] + cpu_halt_status <= _T_387 @[el2_dec_tlu_ctl.scala 674:19] + node _T_388 = and(io.o_cpu_halt_status, i_cpu_run_req_sync_qual) @[el2_dec_tlu_ctl.scala 675:40] + node _T_389 = and(io.o_cpu_run_ack, i_cpu_run_req_sync_qual) @[el2_dec_tlu_ctl.scala 675:87] + node _T_390 = or(_T_388, _T_389) @[el2_dec_tlu_ctl.scala 675:67] + cpu_run_ack <= _T_390 @[el2_dec_tlu_ctl.scala 675:15] + io.o_debug_mode_status <= debug_mode_status @[el2_dec_tlu_ctl.scala 677:26] + node _T_391 = or(nmi_int_detected, timer_int_ready) @[el2_dec_tlu_ctl.scala 680:65] + node _T_392 = or(_T_391, soft_int_ready) @[el2_dec_tlu_ctl.scala 680:83] + node _T_393 = or(_T_392, int_timer0_int_hold_f) @[el2_dec_tlu_ctl.scala 680:100] + node _T_394 = or(_T_393, int_timer1_int_hold_f) @[el2_dec_tlu_ctl.scala 680:124] + node _T_395 = and(io.mhwakeup, mhwakeup_ready) @[el2_dec_tlu_ctl.scala 680:163] + node _T_396 = or(_T_394, _T_395) @[el2_dec_tlu_ctl.scala 680:148] + node _T_397 = and(_T_396, io.o_cpu_halt_status) @[el2_dec_tlu_ctl.scala 680:182] + node _T_398 = not(i_cpu_halt_req_d1) @[el2_dec_tlu_ctl.scala 680:207] + node _T_399 = and(_T_397, _T_398) @[el2_dec_tlu_ctl.scala 680:205] + node _T_400 = or(i_cpu_run_req_d1_raw, _T_399) @[el2_dec_tlu_ctl.scala 680:44] + i_cpu_run_req_d1 <= _T_400 @[el2_dec_tlu_ctl.scala 680:20] + reg _T_401 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 686:89] + _T_401 <= mdseac_locked_ns @[el2_dec_tlu_ctl.scala 686:89] + mdseac_locked_f <= _T_401 @[el2_dec_tlu_ctl.scala 686:57] + reg lsu_single_ecc_error_r_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 687:64] + lsu_single_ecc_error_r_d1 <= io.lsu_single_ecc_error_incr @[el2_dec_tlu_ctl.scala 687:64] + node _T_402 = not(io.dec_tlu_flush_lower_wb) @[el2_dec_tlu_ctl.scala 689:56] + node lsu_exc_valid_r_raw = and(io.lsu_error_pkt_r.valid, _T_402) @[el2_dec_tlu_ctl.scala 689:54] + lsu_i0_exc_r_raw <= io.lsu_error_pkt_r.valid @[el2_dec_tlu_ctl.scala 690:20] + node _T_403 = and(lsu_i0_exc_r_raw, lsu_exc_valid_r_raw) @[el2_dec_tlu_ctl.scala 691:39] + node _T_404 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 691:63] + node _T_405 = and(_T_403, _T_404) @[el2_dec_tlu_ctl.scala 691:61] + node _T_406 = not(rfpc_i0_r) @[el2_dec_tlu_ctl.scala 691:83] + node lsu_exc_valid_r = and(_T_405, _T_406) @[el2_dec_tlu_ctl.scala 691:81] + reg _T_407 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 693:74] + _T_407 <= lsu_exc_valid_r @[el2_dec_tlu_ctl.scala 693:74] + lsu_exc_valid_r_d1 <= _T_407 @[el2_dec_tlu_ctl.scala 693:41] + reg lsu_i0_exc_r_d1 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 694:73] + lsu_i0_exc_r_d1 <= lsu_exc_valid_r @[el2_dec_tlu_ctl.scala 694:73] + node _T_408 = not(io.lsu_error_pkt_r.bits.exc_type) @[el2_dec_tlu_ctl.scala 695:39] + node lsu_exc_ma_r = and(lsu_exc_valid_r, _T_408) @[el2_dec_tlu_ctl.scala 695:37] + node lsu_exc_acc_r = and(lsu_exc_valid_r, io.lsu_error_pkt_r.bits.exc_type) @[el2_dec_tlu_ctl.scala 696:37] + node lsu_exc_st_r = and(lsu_exc_valid_r, io.lsu_error_pkt_r.bits.inst_type) @[el2_dec_tlu_ctl.scala 697:37] + node _T_409 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 701:48] + node _T_410 = and(io.dec_tlu_i0_valid_r, _T_409) @[el2_dec_tlu_ctl.scala 701:46] + node _T_411 = not(io.lsu_error_pkt_r.bits.inst_type) @[el2_dec_tlu_ctl.scala 701:69] + node _T_412 = and(_T_411, io.lsu_error_pkt_r.bits.single_ecc_error) @[el2_dec_tlu_ctl.scala 701:104] + node lsu_i0_rfnpc_r = and(_T_410, _T_412) @[el2_dec_tlu_ctl.scala 701:66] + node _T_413 = not(rfpc_i0_r) @[el2_dec_tlu_ctl.scala 704:51] + node _T_414 = and(io.dec_tlu_i0_valid_r, _T_413) @[el2_dec_tlu_ctl.scala 704:49] + node _T_415 = not(lsu_exc_valid_r) @[el2_dec_tlu_ctl.scala 704:64] + node _T_416 = and(_T_414, _T_415) @[el2_dec_tlu_ctl.scala 704:62] + node _T_417 = not(inst_acc_r) @[el2_dec_tlu_ctl.scala 704:81] + node _T_418 = and(_T_416, _T_417) @[el2_dec_tlu_ctl.scala 704:78] + node _T_419 = not(io.dec_tlu_dbg_halted) @[el2_dec_tlu_ctl.scala 704:95] + node _T_420 = and(_T_418, _T_419) @[el2_dec_tlu_ctl.scala 704:93] + node _T_421 = not(request_debug_mode_r_d1) @[el2_dec_tlu_ctl.scala 704:120] + node _T_422 = and(_T_420, _T_421) @[el2_dec_tlu_ctl.scala 704:118] + node _T_423 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 704:147] + node tlu_i0_commit_cmt = and(_T_422, _T_423) @[el2_dec_tlu_ctl.scala 704:145] + node _T_424 = or(rfpc_i0_r, lsu_exc_valid_r) @[el2_dec_tlu_ctl.scala 707:37] + node _T_425 = or(_T_424, inst_acc_r) @[el2_dec_tlu_ctl.scala 707:52] + node _T_426 = and(illegal_r, io.dec_tlu_dbg_halted) @[el2_dec_tlu_ctl.scala 707:78] + node _T_427 = or(_T_425, _T_426) @[el2_dec_tlu_ctl.scala 707:65] + node _T_428 = or(_T_427, i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 707:103] + tlu_i0_kill_writeb_r <= _T_428 @[el2_dec_tlu_ctl.scala 707:24] + io.dec_tlu_i0_commit_cmt <= tlu_i0_commit_cmt @[el2_dec_tlu_ctl.scala 708:28] + node _T_429 = not(tlu_flush_lower_r_d1) @[el2_dec_tlu_ctl.scala 713:43] + node _T_430 = and(io.dec_tlu_i0_valid_r, _T_429) @[el2_dec_tlu_ctl.scala 713:41] + node _T_431 = or(io.exu_i0_br_error_r, io.exu_i0_br_start_error_r) @[el2_dec_tlu_ctl.scala 713:89] + node _T_432 = and(_T_430, _T_431) @[el2_dec_tlu_ctl.scala 713:65] + node _T_433 = or(ic_perr_r_d1, iccm_sbecc_r_d1) @[el2_dec_tlu_ctl.scala 713:137] + node _T_434 = not(ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 713:158] + node _T_435 = and(_T_433, _T_434) @[el2_dec_tlu_ctl.scala 713:156] + node _T_436 = or(_T_432, _T_435) @[el2_dec_tlu_ctl.scala 713:120] + node _T_437 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 713:182] + node _T_438 = and(_T_436, _T_437) @[el2_dec_tlu_ctl.scala 713:179] + node _T_439 = not(lsu_i0_rfnpc_r) @[el2_dec_tlu_ctl.scala 713:203] + node _T_440 = and(_T_438, _T_439) @[el2_dec_tlu_ctl.scala 713:200] + rfpc_i0_r <= _T_440 @[el2_dec_tlu_ctl.scala 713:13] + node _T_441 = not(io.dec_tlu_flush_lower_r) @[el2_dec_tlu_ctl.scala 716:69] + node _T_442 = and(iccm_repair_state_d1, _T_441) @[el2_dec_tlu_ctl.scala 716:67] + node _T_443 = or(iccm_sbecc_r_d1, _T_442) @[el2_dec_tlu_ctl.scala 716:43] + iccm_repair_state_ns <= _T_443 @[el2_dec_tlu_ctl.scala 716:24] + node _T_444 = and(tlu_i0_commit_cmt, iccm_repair_state_d1) @[el2_dec_tlu_ctl.scala 722:51] + node _T_445 = or(ebreak_r, ecall_r) @[el2_dec_tlu_ctl.scala 722:87] + node _T_446 = or(_T_445, mret_r) @[el2_dec_tlu_ctl.scala 722:97] + node _T_447 = or(_T_446, take_reset) @[el2_dec_tlu_ctl.scala 722:106] + node _T_448 = or(_T_447, illegal_r) @[el2_dec_tlu_ctl.scala 722:119] + node _T_449 = eq(io.dec_csr_wraddr_r, UInt<12>("h07c2")) @[el2_dec_tlu_ctl.scala 722:175] + node _T_450 = and(dec_csr_wen_r_mod, _T_449) @[el2_dec_tlu_ctl.scala 722:152] + node _T_451 = or(_T_448, _T_450) @[el2_dec_tlu_ctl.scala 722:131] + node _T_452 = not(_T_451) @[el2_dec_tlu_ctl.scala 722:76] + node iccm_repair_state_rfnpc = and(_T_444, _T_452) @[el2_dec_tlu_ctl.scala 722:74] + node _T_453 = and(io.exu_i0_br_error_r, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 725:50] + node _T_454 = not(tlu_flush_lower_r_d1) @[el2_dec_tlu_ctl.scala 725:76] + node dec_tlu_br0_error_r = and(_T_453, _T_454) @[el2_dec_tlu_ctl.scala 725:74] + node _T_455 = and(io.exu_i0_br_start_error_r, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 726:62] + node _T_456 = not(tlu_flush_lower_r_d1) @[el2_dec_tlu_ctl.scala 726:88] + node dec_tlu_br0_start_error_r = and(_T_455, _T_456) @[el2_dec_tlu_ctl.scala 726:86] + node _T_457 = and(io.exu_i0_br_valid_r, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 727:46] + node _T_458 = not(tlu_flush_lower_r_d1) @[el2_dec_tlu_ctl.scala 727:72] + node _T_459 = and(_T_457, _T_458) @[el2_dec_tlu_ctl.scala 727:70] + node _T_460 = not(io.exu_i0_br_mp_r) @[el2_dec_tlu_ctl.scala 727:97] + node _T_461 = not(io.exu_pmu_i0_br_ataken) @[el2_dec_tlu_ctl.scala 727:118] + node _T_462 = or(_T_460, _T_461) @[el2_dec_tlu_ctl.scala 727:116] + node dec_tlu_br0_v_r = and(_T_459, _T_462) @[el2_dec_tlu_ctl.scala 727:94] + io.dec_tlu_br0_r_pkt.bits.hist <= io.exu_i0_br_hist_r @[el2_dec_tlu_ctl.scala 730:57] + io.dec_tlu_br0_r_pkt.bits.br_error <= dec_tlu_br0_error_r @[el2_dec_tlu_ctl.scala 731:49] + io.dec_tlu_br0_r_pkt.bits.br_start_error <= dec_tlu_br0_start_error_r @[el2_dec_tlu_ctl.scala 732:49] + io.dec_tlu_br0_r_pkt.valid <= dec_tlu_br0_v_r @[el2_dec_tlu_ctl.scala 733:49] + io.dec_tlu_br0_r_pkt.bits.way <= io.exu_i0_br_way_r @[el2_dec_tlu_ctl.scala 734:57] + io.dec_tlu_br0_r_pkt.bits.middle <= io.exu_i0_br_middle_r @[el2_dec_tlu_ctl.scala 735:57] + node _T_463 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h08")) @[el2_dec_tlu_ctl.scala 738:51] + node _T_464 = and(_T_463, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 738:64] + node _T_465 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 738:90] + node _T_466 = and(_T_464, _T_465) @[el2_dec_tlu_ctl.scala 738:88] + node _T_467 = bits(dcsr, 15, 15) @[el2_dec_tlu_ctl.scala 738:115] + node _T_468 = not(_T_467) @[el2_dec_tlu_ctl.scala 738:110] + node _T_469 = and(_T_466, _T_468) @[el2_dec_tlu_ctl.scala 738:108] + node _T_470 = not(rfpc_i0_r) @[el2_dec_tlu_ctl.scala 738:132] + node _T_471 = and(_T_469, _T_470) @[el2_dec_tlu_ctl.scala 738:130] + ebreak_r <= _T_471 @[el2_dec_tlu_ctl.scala 738:13] + node _T_472 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h09")) @[el2_dec_tlu_ctl.scala 739:51] + node _T_473 = and(_T_472, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 739:64] + node _T_474 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 739:90] + node _T_475 = and(_T_473, _T_474) @[el2_dec_tlu_ctl.scala 739:88] + node _T_476 = not(rfpc_i0_r) @[el2_dec_tlu_ctl.scala 739:110] + node _T_477 = and(_T_475, _T_476) @[el2_dec_tlu_ctl.scala 739:108] + ecall_r <= _T_477 @[el2_dec_tlu_ctl.scala 739:13] + node _T_478 = not(io.dec_tlu_packet_r.legal) @[el2_dec_tlu_ctl.scala 740:17] + node _T_479 = and(_T_478, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 740:46] + node _T_480 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 740:72] + node _T_481 = and(_T_479, _T_480) @[el2_dec_tlu_ctl.scala 740:70] + node _T_482 = not(rfpc_i0_r) @[el2_dec_tlu_ctl.scala 740:92] + node _T_483 = and(_T_481, _T_482) @[el2_dec_tlu_ctl.scala 740:90] + illegal_r <= _T_483 @[el2_dec_tlu_ctl.scala 740:13] + node _T_484 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h0c")) @[el2_dec_tlu_ctl.scala 741:51] + node _T_485 = and(_T_484, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 741:64] + node _T_486 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 741:90] + node _T_487 = and(_T_485, _T_486) @[el2_dec_tlu_ctl.scala 741:88] + node _T_488 = not(rfpc_i0_r) @[el2_dec_tlu_ctl.scala 741:110] + node _T_489 = and(_T_487, _T_488) @[el2_dec_tlu_ctl.scala 741:108] + mret_r <= _T_489 @[el2_dec_tlu_ctl.scala 741:13] + node _T_490 = and(io.dec_tlu_packet_r.fence_i, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 743:49] + node _T_491 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 743:75] + node _T_492 = and(_T_490, _T_491) @[el2_dec_tlu_ctl.scala 743:73] + node _T_493 = not(rfpc_i0_r) @[el2_dec_tlu_ctl.scala 743:96] + node _T_494 = and(_T_492, _T_493) @[el2_dec_tlu_ctl.scala 743:94] + fence_i_r <= _T_494 @[el2_dec_tlu_ctl.scala 743:16] + node _T_495 = not(ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 744:44] + node _T_496 = and(io.ifu_ic_error_start, _T_495) @[el2_dec_tlu_ctl.scala 744:42] + node _T_497 = not(debug_mode_status) @[el2_dec_tlu_ctl.scala 744:66] + node _T_498 = or(_T_497, dcsr_single_step_running) @[el2_dec_tlu_ctl.scala 744:92] + node _T_499 = and(_T_496, _T_498) @[el2_dec_tlu_ctl.scala 744:63] + node _T_500 = not(internal_pmu_fw_halt_mode_f) @[el2_dec_tlu_ctl.scala 744:122] + node _T_501 = and(_T_499, _T_500) @[el2_dec_tlu_ctl.scala 744:120] + ic_perr_r <= _T_501 @[el2_dec_tlu_ctl.scala 744:16] + node _T_502 = not(ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 745:52] + node _T_503 = and(io.ifu_iccm_rd_ecc_single_err, _T_502) @[el2_dec_tlu_ctl.scala 745:50] + node _T_504 = not(debug_mode_status) @[el2_dec_tlu_ctl.scala 745:74] + node _T_505 = or(_T_504, dcsr_single_step_running) @[el2_dec_tlu_ctl.scala 745:100] + node _T_506 = and(_T_503, _T_505) @[el2_dec_tlu_ctl.scala 745:71] + node _T_507 = not(internal_pmu_fw_halt_mode_f) @[el2_dec_tlu_ctl.scala 745:130] + node _T_508 = and(_T_506, _T_507) @[el2_dec_tlu_ctl.scala 745:128] + iccm_sbecc_r <= _T_508 @[el2_dec_tlu_ctl.scala 745:16] + node _T_509 = and(io.dec_tlu_packet_r.icaf, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 746:48] + inst_acc_r_raw <= _T_509 @[el2_dec_tlu_ctl.scala 746:19] + node _T_510 = not(rfpc_i0_r) @[el2_dec_tlu_ctl.scala 747:34] + node _T_511 = and(inst_acc_r_raw, _T_510) @[el2_dec_tlu_ctl.scala 747:32] + node _T_512 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 747:47] + node _T_513 = and(_T_511, _T_512) @[el2_dec_tlu_ctl.scala 747:45] + inst_acc_r <= _T_513 @[el2_dec_tlu_ctl.scala 747:14] + node _T_514 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h08")) @[el2_dec_tlu_ctl.scala 750:63] + node _T_515 = and(_T_514, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 750:76] + node _T_516 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 750:102] + node _T_517 = and(_T_515, _T_516) @[el2_dec_tlu_ctl.scala 750:100] + node _T_518 = bits(dcsr, 15, 15) @[el2_dec_tlu_ctl.scala 750:126] + node _T_519 = and(_T_517, _T_518) @[el2_dec_tlu_ctl.scala 750:120] + node _T_520 = not(rfpc_i0_r) @[el2_dec_tlu_ctl.scala 750:143] + node _T_521 = and(_T_519, _T_520) @[el2_dec_tlu_ctl.scala 750:141] + ebreak_to_debug_mode_r <= _T_521 @[el2_dec_tlu_ctl.scala 750:26] + reg _T_522 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 752:58] + _T_522 <= ebreak_to_debug_mode_r @[el2_dec_tlu_ctl.scala 752:58] + ebreak_to_debug_mode_r_d1 <= _T_522 @[el2_dec_tlu_ctl.scala 752:28] + io.dec_tlu_fence_i_r <= fence_i_r @[el2_dec_tlu_ctl.scala 753:24] + node _T_523 = or(ebreak_r, ecall_r) @[el2_dec_tlu_ctl.scala 766:40] + node _T_524 = or(_T_523, illegal_r) @[el2_dec_tlu_ctl.scala 766:50] + node _T_525 = or(_T_524, inst_acc_r) @[el2_dec_tlu_ctl.scala 766:62] + node _T_526 = not(rfpc_i0_r) @[el2_dec_tlu_ctl.scala 766:78] + node _T_527 = and(_T_525, _T_526) @[el2_dec_tlu_ctl.scala 766:76] + node _T_528 = not(io.dec_tlu_dbg_halted) @[el2_dec_tlu_ctl.scala 766:91] + node i0_exception_valid_r = and(_T_527, _T_528) @[el2_dec_tlu_ctl.scala 766:89] + node _T_529 = not(take_nmi) @[el2_dec_tlu_ctl.scala 775:21] + node _T_530 = and(take_ext_int, _T_529) @[el2_dec_tlu_ctl.scala 775:19] + node _T_531 = bits(_T_530, 0, 0) @[el2_dec_tlu_ctl.scala 775:32] + node _T_532 = not(take_nmi) @[el2_dec_tlu_ctl.scala 776:23] + node _T_533 = and(take_timer_int, _T_532) @[el2_dec_tlu_ctl.scala 776:21] + node _T_534 = bits(_T_533, 0, 0) @[el2_dec_tlu_ctl.scala 776:34] + node _T_535 = not(take_nmi) @[el2_dec_tlu_ctl.scala 777:22] + node _T_536 = and(take_soft_int, _T_535) @[el2_dec_tlu_ctl.scala 777:20] + node _T_537 = bits(_T_536, 0, 0) @[el2_dec_tlu_ctl.scala 777:33] + node _T_538 = not(take_nmi) @[el2_dec_tlu_ctl.scala 778:28] + node _T_539 = and(take_int_timer0_int, _T_538) @[el2_dec_tlu_ctl.scala 778:26] + node _T_540 = bits(_T_539, 0, 0) @[el2_dec_tlu_ctl.scala 778:39] + node _T_541 = not(take_nmi) @[el2_dec_tlu_ctl.scala 779:28] + node _T_542 = and(take_int_timer1_int, _T_541) @[el2_dec_tlu_ctl.scala 779:26] + node _T_543 = bits(_T_542, 0, 0) @[el2_dec_tlu_ctl.scala 779:39] + node _T_544 = not(take_nmi) @[el2_dec_tlu_ctl.scala 780:20] + node _T_545 = and(take_ce_int, _T_544) @[el2_dec_tlu_ctl.scala 780:18] + node _T_546 = bits(_T_545, 0, 0) @[el2_dec_tlu_ctl.scala 780:31] + node _T_547 = not(take_nmi) @[el2_dec_tlu_ctl.scala 781:18] + node _T_548 = and(illegal_r, _T_547) @[el2_dec_tlu_ctl.scala 781:16] + node _T_549 = bits(_T_548, 0, 0) @[el2_dec_tlu_ctl.scala 781:29] + node _T_550 = not(take_nmi) @[el2_dec_tlu_ctl.scala 782:17] + node _T_551 = and(ecall_r, _T_550) @[el2_dec_tlu_ctl.scala 782:15] + node _T_552 = bits(_T_551, 0, 0) @[el2_dec_tlu_ctl.scala 782:28] + node _T_553 = not(take_nmi) @[el2_dec_tlu_ctl.scala 783:20] + node _T_554 = and(inst_acc_r, _T_553) @[el2_dec_tlu_ctl.scala 783:18] + node _T_555 = bits(_T_554, 0, 0) @[el2_dec_tlu_ctl.scala 783:31] + node _T_556 = or(ebreak_r, i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 784:16] + node _T_557 = not(take_nmi) @[el2_dec_tlu_ctl.scala 784:38] + node _T_558 = and(_T_556, _T_557) @[el2_dec_tlu_ctl.scala 784:36] + node _T_559 = bits(_T_558, 0, 0) @[el2_dec_tlu_ctl.scala 784:49] + node _T_560 = not(lsu_exc_st_r) @[el2_dec_tlu_ctl.scala 785:21] + node _T_561 = and(lsu_exc_ma_r, _T_560) @[el2_dec_tlu_ctl.scala 785:19] + node _T_562 = not(take_nmi) @[el2_dec_tlu_ctl.scala 785:37] + node _T_563 = and(_T_561, _T_562) @[el2_dec_tlu_ctl.scala 785:35] + node _T_564 = bits(_T_563, 0, 0) @[el2_dec_tlu_ctl.scala 785:48] + node _T_565 = not(lsu_exc_st_r) @[el2_dec_tlu_ctl.scala 786:22] + node _T_566 = and(lsu_exc_acc_r, _T_565) @[el2_dec_tlu_ctl.scala 786:20] + node _T_567 = not(take_nmi) @[el2_dec_tlu_ctl.scala 786:38] + node _T_568 = and(_T_566, _T_567) @[el2_dec_tlu_ctl.scala 786:36] + node _T_569 = bits(_T_568, 0, 0) @[el2_dec_tlu_ctl.scala 786:49] + node _T_570 = and(lsu_exc_ma_r, lsu_exc_st_r) @[el2_dec_tlu_ctl.scala 787:19] + node _T_571 = not(take_nmi) @[el2_dec_tlu_ctl.scala 787:36] + node _T_572 = and(_T_570, _T_571) @[el2_dec_tlu_ctl.scala 787:34] + node _T_573 = bits(_T_572, 0, 0) @[el2_dec_tlu_ctl.scala 787:47] + node _T_574 = and(lsu_exc_acc_r, lsu_exc_st_r) @[el2_dec_tlu_ctl.scala 788:20] + node _T_575 = not(take_nmi) @[el2_dec_tlu_ctl.scala 788:37] + node _T_576 = and(_T_574, _T_575) @[el2_dec_tlu_ctl.scala 788:35] + node _T_577 = bits(_T_576, 0, 0) @[el2_dec_tlu_ctl.scala 788:48] + node _T_578 = mux(_T_531, UInt<5>("h0b"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_579 = mux(_T_534, UInt<5>("h07"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_580 = mux(_T_537, UInt<5>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_581 = mux(_T_540, UInt<5>("h01d"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_582 = mux(_T_543, UInt<5>("h01c"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_583 = mux(_T_546, UInt<5>("h01e"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_584 = mux(_T_549, UInt<5>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_585 = mux(_T_552, UInt<5>("h0b"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_586 = mux(_T_555, UInt<5>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_587 = mux(_T_559, UInt<5>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_588 = mux(_T_564, UInt<5>("h04"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_589 = mux(_T_569, UInt<5>("h05"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_590 = mux(_T_573, UInt<5>("h06"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_591 = mux(_T_577, UInt<5>("h07"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_592 = or(_T_578, _T_579) @[Mux.scala 27:72] + node _T_593 = or(_T_592, _T_580) @[Mux.scala 27:72] + node _T_594 = or(_T_593, _T_581) @[Mux.scala 27:72] + node _T_595 = or(_T_594, _T_582) @[Mux.scala 27:72] + node _T_596 = or(_T_595, _T_583) @[Mux.scala 27:72] + node _T_597 = or(_T_596, _T_584) @[Mux.scala 27:72] + node _T_598 = or(_T_597, _T_585) @[Mux.scala 27:72] + node _T_599 = or(_T_598, _T_586) @[Mux.scala 27:72] + node _T_600 = or(_T_599, _T_587) @[Mux.scala 27:72] + node _T_601 = or(_T_600, _T_588) @[Mux.scala 27:72] + node _T_602 = or(_T_601, _T_589) @[Mux.scala 27:72] + node _T_603 = or(_T_602, _T_590) @[Mux.scala 27:72] + node _T_604 = or(_T_603, _T_591) @[Mux.scala 27:72] + wire exc_cause_r : UInt<5> @[Mux.scala 27:72] + exc_cause_r <= _T_604 @[Mux.scala 27:72] + node _T_605 = not(io.dec_csr_stall_int_ff) @[el2_dec_tlu_ctl.scala 799:23] + node _T_606 = and(_T_605, mstatus_mie_ns) @[el2_dec_tlu_ctl.scala 799:48] + node _T_607 = bits(mip, 2, 2) @[el2_dec_tlu_ctl.scala 799:70] + node _T_608 = and(_T_606, _T_607) @[el2_dec_tlu_ctl.scala 799:65] + node _T_609 = bits(mie_ns, 2, 2) @[el2_dec_tlu_ctl.scala 799:91] + node _T_610 = and(_T_608, _T_609) @[el2_dec_tlu_ctl.scala 799:83] + mhwakeup_ready <= _T_610 @[el2_dec_tlu_ctl.scala 799:19] + node _T_611 = not(io.dec_csr_stall_int_ff) @[el2_dec_tlu_ctl.scala 800:22] + node _T_612 = and(_T_611, mstatus_mie_ns) @[el2_dec_tlu_ctl.scala 800:47] + node _T_613 = bits(mip, 2, 2) @[el2_dec_tlu_ctl.scala 800:69] + node _T_614 = and(_T_612, _T_613) @[el2_dec_tlu_ctl.scala 800:64] + node _T_615 = bits(mie_ns, 2, 2) @[el2_dec_tlu_ctl.scala 800:90] + node _T_616 = and(_T_614, _T_615) @[el2_dec_tlu_ctl.scala 800:82] + node _T_617 = not(ignore_ext_int_due_to_lsu_stall) @[el2_dec_tlu_ctl.scala 800:103] + node _T_618 = and(_T_616, _T_617) @[el2_dec_tlu_ctl.scala 800:101] + ext_int_ready <= _T_618 @[el2_dec_tlu_ctl.scala 800:19] + node _T_619 = not(io.dec_csr_stall_int_ff) @[el2_dec_tlu_ctl.scala 801:22] + node _T_620 = and(_T_619, mstatus_mie_ns) @[el2_dec_tlu_ctl.scala 801:47] + node _T_621 = bits(mip, 5, 5) @[el2_dec_tlu_ctl.scala 801:69] + node _T_622 = and(_T_620, _T_621) @[el2_dec_tlu_ctl.scala 801:64] + node _T_623 = bits(mie_ns, 5, 5) @[el2_dec_tlu_ctl.scala 801:90] + node _T_624 = and(_T_622, _T_623) @[el2_dec_tlu_ctl.scala 801:82] + ce_int_ready <= _T_624 @[el2_dec_tlu_ctl.scala 801:19] + node _T_625 = not(io.dec_csr_stall_int_ff) @[el2_dec_tlu_ctl.scala 802:22] + node _T_626 = and(_T_625, mstatus_mie_ns) @[el2_dec_tlu_ctl.scala 802:47] + node _T_627 = bits(mip, 0, 0) @[el2_dec_tlu_ctl.scala 802:69] + node _T_628 = and(_T_626, _T_627) @[el2_dec_tlu_ctl.scala 802:64] + node _T_629 = bits(mie_ns, 0, 0) @[el2_dec_tlu_ctl.scala 802:90] + node _T_630 = and(_T_628, _T_629) @[el2_dec_tlu_ctl.scala 802:82] + soft_int_ready <= _T_630 @[el2_dec_tlu_ctl.scala 802:19] + node _T_631 = not(io.dec_csr_stall_int_ff) @[el2_dec_tlu_ctl.scala 803:22] + node _T_632 = and(_T_631, mstatus_mie_ns) @[el2_dec_tlu_ctl.scala 803:47] + node _T_633 = bits(mip, 1, 1) @[el2_dec_tlu_ctl.scala 803:69] + node _T_634 = and(_T_632, _T_633) @[el2_dec_tlu_ctl.scala 803:64] + node _T_635 = bits(mie_ns, 1, 1) @[el2_dec_tlu_ctl.scala 803:90] + node _T_636 = and(_T_634, _T_635) @[el2_dec_tlu_ctl.scala 803:82] + timer_int_ready <= _T_636 @[el2_dec_tlu_ctl.scala 803:19] + node _T_637 = bits(mie_ns, 4, 4) @[el2_dec_tlu_ctl.scala 806:56] + node int_timer0_int_possible = and(mstatus_mie_ns, _T_637) @[el2_dec_tlu_ctl.scala 806:48] + node _T_638 = bits(mip, 4, 4) @[el2_dec_tlu_ctl.scala 807:33] + node int_timer0_int_ready = and(_T_638, int_timer0_int_possible) @[el2_dec_tlu_ctl.scala 807:46] + node _T_639 = bits(mie_ns, 3, 3) @[el2_dec_tlu_ctl.scala 808:56] + node int_timer1_int_possible = and(mstatus_mie_ns, _T_639) @[el2_dec_tlu_ctl.scala 808:48] + node _T_640 = bits(mip, 3, 3) @[el2_dec_tlu_ctl.scala 809:33] + node int_timer1_int_ready = and(_T_640, int_timer1_int_possible) @[el2_dec_tlu_ctl.scala 809:46] + node _T_641 = or(io.dec_csr_stall_int_ff, synchronous_flush_r) @[el2_dec_tlu_ctl.scala 813:51] + node _T_642 = or(_T_641, exc_or_int_valid_r_d1) @[el2_dec_tlu_ctl.scala 813:73] + node int_timer_stalled = or(_T_642, mret_r) @[el2_dec_tlu_ctl.scala 813:97] + node _T_643 = or(pmu_fw_tlu_halted_f, int_timer_stalled) @[el2_dec_tlu_ctl.scala 815:71] + node _T_644 = and(int_timer0_int_ready, _T_643) @[el2_dec_tlu_ctl.scala 815:48] + node _T_645 = and(int_timer0_int_possible, int_timer0_int_hold_f) @[el2_dec_tlu_ctl.scala 815:120] + node _T_646 = not(interrupt_valid_r) @[el2_dec_tlu_ctl.scala 815:146] + node _T_647 = and(_T_645, _T_646) @[el2_dec_tlu_ctl.scala 815:144] + node _T_648 = not(take_ext_int_start) @[el2_dec_tlu_ctl.scala 815:167] + node _T_649 = and(_T_647, _T_648) @[el2_dec_tlu_ctl.scala 815:165] + node _T_650 = not(debug_mode_status) @[el2_dec_tlu_ctl.scala 815:189] + node _T_651 = and(_T_649, _T_650) @[el2_dec_tlu_ctl.scala 815:187] + node _T_652 = or(_T_644, _T_651) @[el2_dec_tlu_ctl.scala 815:93] + int_timer0_int_hold <= _T_652 @[el2_dec_tlu_ctl.scala 815:23] + node _T_653 = or(pmu_fw_tlu_halted_f, int_timer_stalled) @[el2_dec_tlu_ctl.scala 816:71] + node _T_654 = and(int_timer1_int_ready, _T_653) @[el2_dec_tlu_ctl.scala 816:48] + node _T_655 = and(int_timer1_int_possible, int_timer1_int_hold_f) @[el2_dec_tlu_ctl.scala 816:120] + node _T_656 = not(interrupt_valid_r) @[el2_dec_tlu_ctl.scala 816:146] + node _T_657 = and(_T_655, _T_656) @[el2_dec_tlu_ctl.scala 816:144] + node _T_658 = not(take_ext_int_start) @[el2_dec_tlu_ctl.scala 816:167] + node _T_659 = and(_T_657, _T_658) @[el2_dec_tlu_ctl.scala 816:165] + node _T_660 = not(debug_mode_status) @[el2_dec_tlu_ctl.scala 816:189] + node _T_661 = and(_T_659, _T_660) @[el2_dec_tlu_ctl.scala 816:187] + node _T_662 = or(_T_654, _T_661) @[el2_dec_tlu_ctl.scala 816:93] + int_timer1_int_hold <= _T_662 @[el2_dec_tlu_ctl.scala 816:23] + node _T_663 = not(dcsr_single_step_running) @[el2_dec_tlu_ctl.scala 818:58] + node _T_664 = and(debug_mode_status, _T_663) @[el2_dec_tlu_ctl.scala 818:56] + internal_dbg_halt_timers <= _T_664 @[el2_dec_tlu_ctl.scala 818:28] + node _T_665 = not(dcsr_single_step_running) @[el2_dec_tlu_ctl.scala 820:54] + node _T_666 = or(_T_665, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 820:80] + node _T_667 = and(internal_dbg_halt_mode, _T_666) @[el2_dec_tlu_ctl.scala 820:51] + node _T_668 = or(_T_667, internal_pmu_fw_halt_mode) @[el2_dec_tlu_ctl.scala 820:106] + node _T_669 = or(_T_668, i_cpu_halt_req_d1) @[el2_dec_tlu_ctl.scala 820:134] + node _T_670 = or(_T_669, take_nmi) @[el2_dec_tlu_ctl.scala 820:154] + node _T_671 = or(_T_670, ebreak_to_debug_mode_r) @[el2_dec_tlu_ctl.scala 820:165] + node _T_672 = or(_T_671, synchronous_flush_r) @[el2_dec_tlu_ctl.scala 820:190] + node _T_673 = or(_T_672, exc_or_int_valid_r_d1) @[el2_dec_tlu_ctl.scala 820:213] + node _T_674 = or(_T_673, mret_r) @[el2_dec_tlu_ctl.scala 820:237] + node block_interrupts = or(_T_674, ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 820:246] + reg _T_675 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 824:58] + _T_675 <= take_ext_int_start @[el2_dec_tlu_ctl.scala 824:58] + take_ext_int_start_d1 <= _T_675 @[el2_dec_tlu_ctl.scala 824:26] + reg _T_676 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 825:58] + _T_676 <= take_ext_int_start_d1 @[el2_dec_tlu_ctl.scala 825:58] + take_ext_int_start_d2 <= _T_676 @[el2_dec_tlu_ctl.scala 825:26] + reg _T_677 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 826:58] + _T_677 <= take_ext_int_start_d2 @[el2_dec_tlu_ctl.scala 826:58] + take_ext_int_start_d3 <= _T_677 @[el2_dec_tlu_ctl.scala 826:26] + reg _T_678 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 827:58] + _T_678 <= ext_int_freeze @[el2_dec_tlu_ctl.scala 827:58] + ext_int_freeze_d1 <= _T_678 @[el2_dec_tlu_ctl.scala 827:26] + node _T_679 = not(block_interrupts) @[el2_dec_tlu_ctl.scala 828:43] + node _T_680 = and(ext_int_ready, _T_679) @[el2_dec_tlu_ctl.scala 828:41] + take_ext_int_start <= _T_680 @[el2_dec_tlu_ctl.scala 828:24] + node _T_681 = or(take_ext_int_start, take_ext_int_start_d1) @[el2_dec_tlu_ctl.scala 830:42] + node _T_682 = or(_T_681, take_ext_int_start_d2) @[el2_dec_tlu_ctl.scala 830:66] + node _T_683 = or(_T_682, take_ext_int_start_d3) @[el2_dec_tlu_ctl.scala 830:90] + ext_int_freeze <= _T_683 @[el2_dec_tlu_ctl.scala 830:20] + node _T_684 = orr(io.lsu_fir_error) @[el2_dec_tlu_ctl.scala 831:63] + node _T_685 = not(_T_684) @[el2_dec_tlu_ctl.scala 831:45] + node _T_686 = and(take_ext_int_start_d3, _T_685) @[el2_dec_tlu_ctl.scala 831:43] + take_ext_int <= _T_686 @[el2_dec_tlu_ctl.scala 831:18] + node _T_687 = and(csr_pkt.csr_meicpct, io.dec_csr_any_unq_d) @[el2_dec_tlu_ctl.scala 832:45] + fast_int_meicpct <= _T_687 @[el2_dec_tlu_ctl.scala 832:22] + ignore_ext_int_due_to_lsu_stall <= io.lsu_fastint_stall_any @[el2_dec_tlu_ctl.scala 833:37] + node _T_688 = not(ext_int_ready) @[el2_dec_tlu_ctl.scala 846:34] + node _T_689 = and(ce_int_ready, _T_688) @[el2_dec_tlu_ctl.scala 846:32] + node _T_690 = not(block_interrupts) @[el2_dec_tlu_ctl.scala 846:51] + node _T_691 = and(_T_689, _T_690) @[el2_dec_tlu_ctl.scala 846:49] + take_ce_int <= _T_691 @[el2_dec_tlu_ctl.scala 846:16] + node _T_692 = not(ext_int_ready) @[el2_dec_tlu_ctl.scala 847:37] + node _T_693 = and(soft_int_ready, _T_692) @[el2_dec_tlu_ctl.scala 847:35] + node _T_694 = not(ce_int_ready) @[el2_dec_tlu_ctl.scala 847:54] + node _T_695 = and(_T_693, _T_694) @[el2_dec_tlu_ctl.scala 847:52] + node _T_696 = not(block_interrupts) @[el2_dec_tlu_ctl.scala 847:70] + node _T_697 = and(_T_695, _T_696) @[el2_dec_tlu_ctl.scala 847:68] + take_soft_int <= _T_697 @[el2_dec_tlu_ctl.scala 847:17] + node _T_698 = not(soft_int_ready) @[el2_dec_tlu_ctl.scala 848:39] + node _T_699 = and(timer_int_ready, _T_698) @[el2_dec_tlu_ctl.scala 848:37] + node _T_700 = not(ext_int_ready) @[el2_dec_tlu_ctl.scala 848:57] + node _T_701 = and(_T_699, _T_700) @[el2_dec_tlu_ctl.scala 848:55] + node _T_702 = not(ce_int_ready) @[el2_dec_tlu_ctl.scala 848:74] + node _T_703 = and(_T_701, _T_702) @[el2_dec_tlu_ctl.scala 848:72] + node _T_704 = not(block_interrupts) @[el2_dec_tlu_ctl.scala 848:90] + node _T_705 = and(_T_703, _T_704) @[el2_dec_tlu_ctl.scala 848:88] + take_timer_int <= _T_705 @[el2_dec_tlu_ctl.scala 848:18] + node _T_706 = or(int_timer0_int_ready, int_timer0_int_hold_f) @[el2_dec_tlu_ctl.scala 849:48] + node _T_707 = and(_T_706, int_timer0_int_possible) @[el2_dec_tlu_ctl.scala 849:73] + node _T_708 = not(io.dec_csr_stall_int_ff) @[el2_dec_tlu_ctl.scala 849:101] + node _T_709 = and(_T_707, _T_708) @[el2_dec_tlu_ctl.scala 849:99] + node _T_710 = not(timer_int_ready) @[el2_dec_tlu_ctl.scala 849:128] + node _T_711 = and(_T_709, _T_710) @[el2_dec_tlu_ctl.scala 849:126] + node _T_712 = not(soft_int_ready) @[el2_dec_tlu_ctl.scala 849:147] + node _T_713 = and(_T_711, _T_712) @[el2_dec_tlu_ctl.scala 849:145] + node _T_714 = not(ext_int_ready) @[el2_dec_tlu_ctl.scala 849:165] + node _T_715 = and(_T_713, _T_714) @[el2_dec_tlu_ctl.scala 849:163] + node _T_716 = not(ce_int_ready) @[el2_dec_tlu_ctl.scala 849:182] + node _T_717 = and(_T_715, _T_716) @[el2_dec_tlu_ctl.scala 849:180] + node _T_718 = not(block_interrupts) @[el2_dec_tlu_ctl.scala 849:198] + node _T_719 = and(_T_717, _T_718) @[el2_dec_tlu_ctl.scala 849:196] + take_int_timer0_int <= _T_719 @[el2_dec_tlu_ctl.scala 849:23] + node _T_720 = or(int_timer1_int_ready, int_timer1_int_hold_f) @[el2_dec_tlu_ctl.scala 850:48] + node _T_721 = and(_T_720, int_timer1_int_possible) @[el2_dec_tlu_ctl.scala 850:73] + node _T_722 = not(io.dec_csr_stall_int_ff) @[el2_dec_tlu_ctl.scala 850:101] + node _T_723 = and(_T_721, _T_722) @[el2_dec_tlu_ctl.scala 850:99] + node _T_724 = or(int_timer0_int_ready, int_timer0_int_hold_f) @[el2_dec_tlu_ctl.scala 850:151] + node _T_725 = not(_T_724) @[el2_dec_tlu_ctl.scala 850:128] + node _T_726 = and(_T_723, _T_725) @[el2_dec_tlu_ctl.scala 850:126] + node _T_727 = not(timer_int_ready) @[el2_dec_tlu_ctl.scala 850:178] + node _T_728 = and(_T_726, _T_727) @[el2_dec_tlu_ctl.scala 850:176] + node _T_729 = not(soft_int_ready) @[el2_dec_tlu_ctl.scala 850:197] + node _T_730 = and(_T_728, _T_729) @[el2_dec_tlu_ctl.scala 850:195] + node _T_731 = not(ext_int_ready) @[el2_dec_tlu_ctl.scala 850:215] + node _T_732 = and(_T_730, _T_731) @[el2_dec_tlu_ctl.scala 850:213] + node _T_733 = not(ce_int_ready) @[el2_dec_tlu_ctl.scala 850:232] + node _T_734 = and(_T_732, _T_733) @[el2_dec_tlu_ctl.scala 850:230] + node _T_735 = not(block_interrupts) @[el2_dec_tlu_ctl.scala 850:248] + node _T_736 = and(_T_734, _T_735) @[el2_dec_tlu_ctl.scala 850:246] + take_int_timer1_int <= _T_736 @[el2_dec_tlu_ctl.scala 850:23] + node _T_737 = and(reset_delayed, io.mpc_reset_run_req) @[el2_dec_tlu_ctl.scala 851:31] + take_reset <= _T_737 @[el2_dec_tlu_ctl.scala 851:14] + node _T_738 = not(internal_pmu_fw_halt_mode) @[el2_dec_tlu_ctl.scala 852:34] + node _T_739 = and(nmi_int_detected, _T_738) @[el2_dec_tlu_ctl.scala 852:32] + node _T_740 = not(internal_dbg_halt_mode) @[el2_dec_tlu_ctl.scala 852:64] + node _T_741 = bits(dcsr, 11, 11) @[el2_dec_tlu_ctl.scala 852:124] + node _T_742 = and(dcsr_single_step_running_f, _T_741) @[el2_dec_tlu_ctl.scala 852:118] + node _T_743 = not(io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 852:140] + node _T_744 = and(_T_742, _T_743) @[el2_dec_tlu_ctl.scala 852:138] + node _T_745 = not(dcsr_single_step_done_f) @[el2_dec_tlu_ctl.scala 852:165] + node _T_746 = and(_T_744, _T_745) @[el2_dec_tlu_ctl.scala 852:163] + node _T_747 = or(_T_740, _T_746) @[el2_dec_tlu_ctl.scala 852:88] + node _T_748 = and(_T_739, _T_747) @[el2_dec_tlu_ctl.scala 852:61] + node _T_749 = not(synchronous_flush_r) @[el2_dec_tlu_ctl.scala 852:194] + node _T_750 = and(_T_748, _T_749) @[el2_dec_tlu_ctl.scala 852:192] + node _T_751 = not(mret_r) @[el2_dec_tlu_ctl.scala 852:217] + node _T_752 = and(_T_750, _T_751) @[el2_dec_tlu_ctl.scala 852:215] + node _T_753 = not(take_reset) @[el2_dec_tlu_ctl.scala 852:227] + node _T_754 = and(_T_752, _T_753) @[el2_dec_tlu_ctl.scala 852:225] + node _T_755 = not(ebreak_to_debug_mode_r) @[el2_dec_tlu_ctl.scala 852:241] + node _T_756 = and(_T_754, _T_755) @[el2_dec_tlu_ctl.scala 852:239] + node _T_757 = not(ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 852:268] + node _T_758 = orr(io.lsu_fir_error) @[el2_dec_tlu_ctl.scala 852:331] + node _T_759 = and(take_ext_int_start_d3, _T_758) @[el2_dec_tlu_ctl.scala 852:312] + node _T_760 = or(_T_757, _T_759) @[el2_dec_tlu_ctl.scala 852:287] + node _T_761 = and(_T_756, _T_760) @[el2_dec_tlu_ctl.scala 852:265] + take_nmi <= _T_761 @[el2_dec_tlu_ctl.scala 852:12] + node _T_762 = or(take_ext_int, take_timer_int) @[el2_dec_tlu_ctl.scala 855:37] + node _T_763 = or(_T_762, take_soft_int) @[el2_dec_tlu_ctl.scala 855:54] + node _T_764 = or(_T_763, take_nmi) @[el2_dec_tlu_ctl.scala 855:70] + node _T_765 = or(_T_764, take_ce_int) @[el2_dec_tlu_ctl.scala 855:81] + node _T_766 = or(_T_765, take_int_timer0_int) @[el2_dec_tlu_ctl.scala 855:95] + node _T_767 = or(_T_766, take_int_timer1_int) @[el2_dec_tlu_ctl.scala 855:117] + interrupt_valid_r <= _T_767 @[el2_dec_tlu_ctl.scala 855:21] + node _T_768 = bits(mtvec, 30, 1) @[el2_dec_tlu_ctl.scala 860:33] + node _T_769 = cat(_T_768, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_770 = cat(UInt<25>("h00"), exc_cause_r) @[Cat.scala 29:58] + node _T_771 = cat(_T_770, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_772 = add(_T_769, _T_771) @[el2_dec_tlu_ctl.scala 860:50] + node vectored_path = tail(_T_772, 1) @[el2_dec_tlu_ctl.scala 860:50] + node _T_773 = bits(take_nmi, 0, 0) @[el2_dec_tlu_ctl.scala 861:37] + node _T_774 = bits(mtvec, 0, 0) @[el2_dec_tlu_ctl.scala 861:66] + node _T_775 = eq(_T_774, UInt<1>("h01")) @[el2_dec_tlu_ctl.scala 861:70] + node _T_776 = bits(mtvec, 30, 1) @[el2_dec_tlu_ctl.scala 861:103] + node _T_777 = cat(_T_776, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_778 = mux(_T_775, vectored_path, _T_777) @[el2_dec_tlu_ctl.scala 861:60] + node interrupt_path = mux(_T_773, io.nmi_vec, _T_778) @[el2_dec_tlu_ctl.scala 861:27] + node _T_779 = or(lsu_i0_rfnpc_r, fence_i_r) @[el2_dec_tlu_ctl.scala 862:35] + node _T_780 = or(_T_779, iccm_repair_state_rfnpc) @[el2_dec_tlu_ctl.scala 862:47] + node _T_781 = not(interrupt_valid_r) @[el2_dec_tlu_ctl.scala 862:95] + node _T_782 = and(i_cpu_run_req_d1, _T_781) @[el2_dec_tlu_ctl.scala 862:93] + node _T_783 = or(_T_780, _T_782) @[el2_dec_tlu_ctl.scala 862:73] + node _T_784 = not(io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 862:130] + node _T_785 = and(rfpc_i0_r, _T_784) @[el2_dec_tlu_ctl.scala 862:128] + node sel_npc_r = or(_T_783, _T_785) @[el2_dec_tlu_ctl.scala 862:115] + node _T_786 = and(i_cpu_run_req_d1, pmu_fw_tlu_halted_f) @[el2_dec_tlu_ctl.scala 863:42] + node sel_npc_resume = or(_T_786, pause_expired_r) @[el2_dec_tlu_ctl.scala 863:65] + node _T_787 = orr(io.lsu_fir_error) @[el2_dec_tlu_ctl.scala 864:64] + node _T_788 = not(_T_787) @[el2_dec_tlu_ctl.scala 864:46] + node sel_fir_addr = and(take_ext_int_start_d3, _T_788) @[el2_dec_tlu_ctl.scala 864:44] + node _T_789 = or(i0_exception_valid_r, rfpc_i0_r) @[el2_dec_tlu_ctl.scala 865:48] + node _T_790 = or(_T_789, lsu_exc_valid_r) @[el2_dec_tlu_ctl.scala 865:60] + node _T_791 = or(_T_790, fence_i_r) @[el2_dec_tlu_ctl.scala 865:78] + node _T_792 = or(_T_791, lsu_i0_rfnpc_r) @[el2_dec_tlu_ctl.scala 865:90] + node _T_793 = or(_T_792, iccm_repair_state_rfnpc) @[el2_dec_tlu_ctl.scala 865:107] + node _T_794 = or(_T_793, debug_resume_req_f) @[el2_dec_tlu_ctl.scala 865:134] + node _T_795 = or(_T_794, sel_npc_resume) @[el2_dec_tlu_ctl.scala 865:156] + node _T_796 = or(_T_795, dec_tlu_wr_pause_r_d1) @[el2_dec_tlu_ctl.scala 865:174] + node _T_797 = or(_T_796, i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 865:200] + synchronous_flush_r <= _T_797 @[el2_dec_tlu_ctl.scala 865:24] + node _T_798 = or(interrupt_valid_r, mret_r) @[el2_dec_tlu_ctl.scala 866:42] + node _T_799 = or(_T_798, synchronous_flush_r) @[el2_dec_tlu_ctl.scala 866:51] + node _T_800 = or(_T_799, take_halt) @[el2_dec_tlu_ctl.scala 866:73] + node _T_801 = or(_T_800, take_reset) @[el2_dec_tlu_ctl.scala 866:85] + node _T_802 = or(_T_801, take_ext_int_start) @[el2_dec_tlu_ctl.scala 866:98] + tlu_flush_lower_r <= _T_802 @[el2_dec_tlu_ctl.scala 866:21] + node _T_803 = bits(take_reset, 0, 0) @[el2_dec_tlu_ctl.scala 868:41] + node _T_804 = bits(sel_fir_addr, 0, 0) @[el2_dec_tlu_ctl.scala 869:20] + node _T_805 = eq(take_nmi, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 870:14] + node _T_806 = eq(sel_npc_r, UInt<1>("h01")) @[el2_dec_tlu_ctl.scala 870:32] + node _T_807 = and(_T_805, _T_806) @[el2_dec_tlu_ctl.scala 870:21] + node _T_808 = eq(take_nmi, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 871:14] + node _T_809 = eq(rfpc_i0_r, UInt<1>("h01")) @[el2_dec_tlu_ctl.scala 871:32] + node _T_810 = and(_T_808, _T_809) @[el2_dec_tlu_ctl.scala 871:21] + node _T_811 = eq(io.dec_tlu_i0_valid_r, UInt<1>("h01")) @[el2_dec_tlu_ctl.scala 871:62] + node _T_812 = and(_T_810, _T_811) @[el2_dec_tlu_ctl.scala 871:39] + node _T_813 = eq(sel_npc_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 871:80] + node _T_814 = and(_T_812, _T_813) @[el2_dec_tlu_ctl.scala 871:69] + node _T_815 = eq(interrupt_valid_r, UInt<1>("h01")) @[el2_dec_tlu_ctl.scala 872:23] + node _T_816 = eq(sel_fir_addr, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 872:44] + node _T_817 = and(_T_815, _T_816) @[el2_dec_tlu_ctl.scala 872:30] + node _T_818 = or(i0_exception_valid_r, lsu_exc_valid_r) @[el2_dec_tlu_ctl.scala 873:28] + node _T_819 = not(trigger_hit_dmode_r) @[el2_dec_tlu_ctl.scala 873:68] + node _T_820 = and(i0_trigger_hit_r, _T_819) @[el2_dec_tlu_ctl.scala 873:66] + node _T_821 = or(_T_818, _T_820) @[el2_dec_tlu_ctl.scala 873:46] + node _T_822 = not(interrupt_valid_r) @[el2_dec_tlu_ctl.scala 873:93] + node _T_823 = and(_T_821, _T_822) @[el2_dec_tlu_ctl.scala 873:91] + node _T_824 = not(sel_fir_addr) @[el2_dec_tlu_ctl.scala 873:114] + node _T_825 = and(_T_823, _T_824) @[el2_dec_tlu_ctl.scala 873:112] + node _T_826 = bits(_T_825, 0, 0) @[el2_dec_tlu_ctl.scala 873:129] + node _T_827 = bits(mtvec, 30, 1) @[el2_dec_tlu_ctl.scala 873:149] + node _T_828 = cat(_T_827, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_829 = not(take_nmi) @[el2_dec_tlu_ctl.scala 874:6] + node _T_830 = and(_T_829, mret_r) @[el2_dec_tlu_ctl.scala 874:16] + node _T_831 = bits(_T_830, 0, 0) @[el2_dec_tlu_ctl.scala 874:26] + node _T_832 = not(take_nmi) @[el2_dec_tlu_ctl.scala 875:6] + node _T_833 = and(_T_832, debug_resume_req_f) @[el2_dec_tlu_ctl.scala 875:16] + node _T_834 = bits(_T_833, 0, 0) @[el2_dec_tlu_ctl.scala 875:38] + node _T_835 = not(take_nmi) @[el2_dec_tlu_ctl.scala 876:6] + node _T_836 = and(_T_835, sel_npc_resume) @[el2_dec_tlu_ctl.scala 876:16] + node _T_837 = bits(_T_836, 0, 0) @[el2_dec_tlu_ctl.scala 876:34] + node _T_838 = mux(_T_804, io.lsu_fir_addr, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_839 = mux(_T_807, npc_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_840 = mux(_T_814, io.dec_tlu_i0_pc_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_841 = mux(_T_817, interrupt_path, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_842 = mux(_T_826, _T_828, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_843 = mux(_T_831, mepc, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_844 = mux(_T_834, dpc, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_845 = mux(_T_837, npc_r_d1, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_846 = or(_T_838, _T_839) @[Mux.scala 27:72] + node _T_847 = or(_T_846, _T_840) @[Mux.scala 27:72] + node _T_848 = or(_T_847, _T_841) @[Mux.scala 27:72] + node _T_849 = or(_T_848, _T_842) @[Mux.scala 27:72] + node _T_850 = or(_T_849, _T_843) @[Mux.scala 27:72] + node _T_851 = or(_T_850, _T_844) @[Mux.scala 27:72] + node _T_852 = or(_T_851, _T_845) @[Mux.scala 27:72] + wire _T_853 : UInt<31> @[Mux.scala 27:72] + _T_853 <= _T_852 @[Mux.scala 27:72] + node tlu_flush_path_r = mux(_T_803, io.rst_vec, _T_853) @[el2_dec_tlu_ctl.scala 868:29] + reg tlu_flush_path_r_d1 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 879:58] + tlu_flush_path_r_d1 <= tlu_flush_path_r @[el2_dec_tlu_ctl.scala 879:58] + io.dec_tlu_flush_lower_wb <= tlu_flush_lower_r_d1 @[el2_dec_tlu_ctl.scala 881:33] + io.dec_tlu_flush_lower_r <= tlu_flush_lower_r @[el2_dec_tlu_ctl.scala 882:33] + io.dec_tlu_flush_path_r <= tlu_flush_path_r @[el2_dec_tlu_ctl.scala 883:33] + node _T_854 = or(lsu_exc_valid_r, i0_exception_valid_r) @[el2_dec_tlu_ctl.scala 886:44] + node _T_855 = or(_T_854, interrupt_valid_r) @[el2_dec_tlu_ctl.scala 886:67] + node _T_856 = not(trigger_hit_dmode_r) @[el2_dec_tlu_ctl.scala 886:109] + node _T_857 = and(i0_trigger_hit_r, _T_856) @[el2_dec_tlu_ctl.scala 886:107] + node exc_or_int_valid_r = or(_T_855, _T_857) @[el2_dec_tlu_ctl.scala 886:87] + reg _T_858 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 888:82] + _T_858 <= interrupt_valid_r @[el2_dec_tlu_ctl.scala 888:82] + interrupt_valid_r_d1 <= _T_858 @[el2_dec_tlu_ctl.scala 888:49] + reg i0_exception_valid_r_d1 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 889:81] + i0_exception_valid_r_d1 <= i0_exception_valid_r @[el2_dec_tlu_ctl.scala 889:81] + reg _T_859 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 890:82] + _T_859 <= exc_or_int_valid_r @[el2_dec_tlu_ctl.scala 890:82] + exc_or_int_valid_r_d1 <= _T_859 @[el2_dec_tlu_ctl.scala 890:49] + reg exc_cause_wb : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 891:89] + exc_cause_wb <= exc_cause_r @[el2_dec_tlu_ctl.scala 891:89] + node _T_860 = not(illegal_r) @[el2_dec_tlu_ctl.scala 892:119] + node _T_861 = and(tlu_i0_commit_cmt, _T_860) @[el2_dec_tlu_ctl.scala 892:117] + reg i0_valid_wb : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 892:97] + i0_valid_wb <= _T_861 @[el2_dec_tlu_ctl.scala 892:97] + reg trigger_hit_r_d1 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 893:81] + trigger_hit_r_d1 <= i0_trigger_hit_r @[el2_dec_tlu_ctl.scala 893:81] + reg _T_862 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 894:90] + _T_862 <= take_nmi @[el2_dec_tlu_ctl.scala 894:90] + take_nmi_r_d1 <= _T_862 @[el2_dec_tlu_ctl.scala 894:57] + reg _T_863 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 895:90] + _T_863 <= pause_expired_r @[el2_dec_tlu_ctl.scala 895:90] + pause_expired_wb <= _T_863 @[el2_dec_tlu_ctl.scala 895:57] + inst csr of csr_tlu @[el2_dec_tlu_ctl.scala 897:17] + csr.clock <= clock + csr.reset <= reset + csr.io.free_clk <= io.free_clk @[el2_dec_tlu_ctl.scala 898:44] + csr.io.active_clk <= io.active_clk @[el2_dec_tlu_ctl.scala 899:44] + csr.io.scan_mode <= io.scan_mode @[el2_dec_tlu_ctl.scala 900:44] + csr.io.dec_csr_wrdata_r <= io.dec_csr_wrdata_r @[el2_dec_tlu_ctl.scala 901:44] + csr.io.dec_csr_wraddr_r <= io.dec_csr_wraddr_r @[el2_dec_tlu_ctl.scala 902:44] + csr.io.dec_csr_rdaddr_d <= io.dec_csr_rdaddr_d @[el2_dec_tlu_ctl.scala 903:44] + csr.io.dec_csr_wen_unq_d <= io.dec_csr_wen_unq_d @[el2_dec_tlu_ctl.scala 904:44] + csr.io.dec_i0_decode_d <= io.dec_i0_decode_d @[el2_dec_tlu_ctl.scala 905:44] + csr.io.ifu_ic_debug_rd_data_valid <= io.ifu_ic_debug_rd_data_valid @[el2_dec_tlu_ctl.scala 906:44] + csr.io.ifu_pmu_bus_trxn <= io.ifu_pmu_bus_trxn @[el2_dec_tlu_ctl.scala 907:44] + csr.io.dma_iccm_stall_any <= io.dma_iccm_stall_any @[el2_dec_tlu_ctl.scala 908:44] + csr.io.dma_dccm_stall_any <= io.dma_dccm_stall_any @[el2_dec_tlu_ctl.scala 909:44] + csr.io.lsu_store_stall_any <= io.lsu_store_stall_any @[el2_dec_tlu_ctl.scala 910:44] + csr.io.dec_pmu_presync_stall <= io.dec_pmu_presync_stall @[el2_dec_tlu_ctl.scala 911:44] + csr.io.dec_pmu_postsync_stall <= io.dec_pmu_postsync_stall @[el2_dec_tlu_ctl.scala 912:44] + csr.io.dec_pmu_decode_stall <= io.dec_pmu_decode_stall @[el2_dec_tlu_ctl.scala 913:44] + csr.io.ifu_pmu_fetch_stall <= io.ifu_pmu_fetch_stall @[el2_dec_tlu_ctl.scala 914:44] + csr.io.dec_tlu_packet_r.pmu_lsu_misaligned <= io.dec_tlu_packet_r.pmu_lsu_misaligned @[el2_dec_tlu_ctl.scala 915:44] + csr.io.dec_tlu_packet_r.pmu_divide <= io.dec_tlu_packet_r.pmu_divide @[el2_dec_tlu_ctl.scala 915:44] + csr.io.dec_tlu_packet_r.pmu_i0_br_unpred <= io.dec_tlu_packet_r.pmu_i0_br_unpred @[el2_dec_tlu_ctl.scala 915:44] + csr.io.dec_tlu_packet_r.pmu_i0_itype <= io.dec_tlu_packet_r.pmu_i0_itype @[el2_dec_tlu_ctl.scala 915:44] + csr.io.dec_tlu_packet_r.i0trigger <= io.dec_tlu_packet_r.i0trigger @[el2_dec_tlu_ctl.scala 915:44] + csr.io.dec_tlu_packet_r.fence_i <= io.dec_tlu_packet_r.fence_i @[el2_dec_tlu_ctl.scala 915:44] + csr.io.dec_tlu_packet_r.icaf_type <= io.dec_tlu_packet_r.icaf_type @[el2_dec_tlu_ctl.scala 915:44] + csr.io.dec_tlu_packet_r.icaf_f1 <= io.dec_tlu_packet_r.icaf_f1 @[el2_dec_tlu_ctl.scala 915:44] + csr.io.dec_tlu_packet_r.icaf <= io.dec_tlu_packet_r.icaf @[el2_dec_tlu_ctl.scala 915:44] + csr.io.dec_tlu_packet_r.legal <= io.dec_tlu_packet_r.legal @[el2_dec_tlu_ctl.scala 915:44] + csr.io.exu_pmu_i0_br_ataken <= io.exu_pmu_i0_br_ataken @[el2_dec_tlu_ctl.scala 916:44] + csr.io.exu_pmu_i0_br_misp <= io.exu_pmu_i0_br_misp @[el2_dec_tlu_ctl.scala 917:44] + csr.io.dec_pmu_instr_decoded <= io.dec_pmu_instr_decoded @[el2_dec_tlu_ctl.scala 918:44] + csr.io.ifu_pmu_instr_aligned <= io.ifu_pmu_instr_aligned @[el2_dec_tlu_ctl.scala 919:44] + csr.io.exu_pmu_i0_pc4 <= io.exu_pmu_i0_pc4 @[el2_dec_tlu_ctl.scala 920:44] + csr.io.ifu_pmu_ic_miss <= io.ifu_pmu_ic_miss @[el2_dec_tlu_ctl.scala 921:44] + csr.io.ifu_pmu_ic_hit <= io.ifu_pmu_ic_hit @[el2_dec_tlu_ctl.scala 922:44] + csr.io.dec_csr_wen_r <= io.dec_csr_wen_r @[el2_dec_tlu_ctl.scala 923:44] + csr.io.dec_tlu_dbg_halted <= io.dec_tlu_dbg_halted @[el2_dec_tlu_ctl.scala 924:44] + csr.io.dma_pmu_dccm_write <= io.dma_pmu_dccm_write @[el2_dec_tlu_ctl.scala 925:44] + csr.io.dma_pmu_dccm_read <= io.dma_pmu_dccm_read @[el2_dec_tlu_ctl.scala 926:44] + csr.io.dma_pmu_any_write <= io.dma_pmu_any_write @[el2_dec_tlu_ctl.scala 927:44] + csr.io.dma_pmu_any_read <= io.dma_pmu_any_read @[el2_dec_tlu_ctl.scala 928:44] + csr.io.lsu_pmu_bus_busy <= io.lsu_pmu_bus_busy @[el2_dec_tlu_ctl.scala 929:44] + csr.io.dec_tlu_i0_pc_r <= io.dec_tlu_i0_pc_r @[el2_dec_tlu_ctl.scala 930:44] + csr.io.dec_tlu_i0_valid_r <= io.dec_tlu_i0_valid_r @[el2_dec_tlu_ctl.scala 931:44] + csr.io.dec_csr_stall_int_ff <= io.dec_csr_stall_int_ff @[el2_dec_tlu_ctl.scala 932:44] + csr.io.dec_csr_any_unq_d <= io.dec_csr_any_unq_d @[el2_dec_tlu_ctl.scala 933:44] + csr.io.ifu_pmu_bus_busy <= io.ifu_pmu_bus_busy @[el2_dec_tlu_ctl.scala 934:44] + csr.io.lsu_pmu_bus_error <= io.lsu_pmu_bus_error @[el2_dec_tlu_ctl.scala 935:44] + csr.io.ifu_pmu_bus_error <= io.ifu_pmu_bus_error @[el2_dec_tlu_ctl.scala 936:44] + csr.io.lsu_pmu_bus_misaligned <= io.lsu_pmu_bus_misaligned @[el2_dec_tlu_ctl.scala 937:44] + csr.io.lsu_pmu_bus_trxn <= io.lsu_pmu_bus_trxn @[el2_dec_tlu_ctl.scala 938:44] + csr.io.ifu_ic_debug_rd_data <= io.ifu_ic_debug_rd_data @[el2_dec_tlu_ctl.scala 939:44] + csr.io.pic_pl <= io.pic_pl @[el2_dec_tlu_ctl.scala 940:44] + csr.io.pic_claimid <= io.pic_claimid @[el2_dec_tlu_ctl.scala 941:44] + csr.io.iccm_dma_sb_error <= io.iccm_dma_sb_error @[el2_dec_tlu_ctl.scala 942:44] + csr.io.lsu_imprecise_error_addr_any <= io.lsu_imprecise_error_addr_any @[el2_dec_tlu_ctl.scala 943:44] + csr.io.lsu_imprecise_error_load_any <= io.lsu_imprecise_error_load_any @[el2_dec_tlu_ctl.scala 944:44] + csr.io.lsu_imprecise_error_store_any <= io.lsu_imprecise_error_store_any @[el2_dec_tlu_ctl.scala 945:44] + csr.io.dec_illegal_inst <= io.dec_illegal_inst @[el2_dec_tlu_ctl.scala 946:44] + csr.io.lsu_error_pkt_r.bits.addr <= io.lsu_error_pkt_r.bits.addr @[el2_dec_tlu_ctl.scala 947:44] + csr.io.lsu_error_pkt_r.bits.mscause <= io.lsu_error_pkt_r.bits.mscause @[el2_dec_tlu_ctl.scala 947:44] + csr.io.lsu_error_pkt_r.bits.exc_type <= io.lsu_error_pkt_r.bits.exc_type @[el2_dec_tlu_ctl.scala 947:44] + csr.io.lsu_error_pkt_r.bits.inst_type <= io.lsu_error_pkt_r.bits.inst_type @[el2_dec_tlu_ctl.scala 947:44] + csr.io.lsu_error_pkt_r.bits.single_ecc_error <= io.lsu_error_pkt_r.bits.single_ecc_error @[el2_dec_tlu_ctl.scala 947:44] + csr.io.lsu_error_pkt_r.valid <= io.lsu_error_pkt_r.valid @[el2_dec_tlu_ctl.scala 947:44] + csr.io.mexintpend <= io.mexintpend @[el2_dec_tlu_ctl.scala 948:44] + csr.io.exu_npc_r <= io.exu_npc_r @[el2_dec_tlu_ctl.scala 949:44] + csr.io.mpc_reset_run_req <= io.mpc_reset_run_req @[el2_dec_tlu_ctl.scala 950:44] + csr.io.rst_vec <= io.rst_vec @[el2_dec_tlu_ctl.scala 951:44] + csr.io.core_id <= io.core_id @[el2_dec_tlu_ctl.scala 952:44] + csr.io.dec_timer_rddata_d <= int_timers.io.dec_timer_rddata_d @[el2_dec_tlu_ctl.scala 953:44] + csr.io.dec_timer_read_d <= int_timers.io.dec_timer_read_d @[el2_dec_tlu_ctl.scala 954:44] + io.dec_tlu_meicurpl <= csr.io.dec_tlu_meicurpl @[el2_dec_tlu_ctl.scala 955:44] + io.dec_tlu_meihap <= csr.io.dec_tlu_meihap @[el2_dec_tlu_ctl.scala 956:44] + io.dec_tlu_meipt <= csr.io.dec_tlu_meipt @[el2_dec_tlu_ctl.scala 957:44] + io.dec_tlu_int_valid_wb1 <= csr.io.dec_tlu_int_valid_wb1 @[el2_dec_tlu_ctl.scala 958:44] + io.dec_tlu_i0_exc_valid_wb1 <= csr.io.dec_tlu_i0_exc_valid_wb1 @[el2_dec_tlu_ctl.scala 959:44] + io.dec_tlu_i0_valid_wb1 <= csr.io.dec_tlu_i0_valid_wb1 @[el2_dec_tlu_ctl.scala 960:44] + io.dec_tlu_ic_diag_pkt.icache_wr_valid <= csr.io.dec_tlu_ic_diag_pkt.icache_wr_valid @[el2_dec_tlu_ctl.scala 961:44] + io.dec_tlu_ic_diag_pkt.icache_rd_valid <= csr.io.dec_tlu_ic_diag_pkt.icache_rd_valid @[el2_dec_tlu_ctl.scala 961:44] + io.dec_tlu_ic_diag_pkt.icache_dicawics <= csr.io.dec_tlu_ic_diag_pkt.icache_dicawics @[el2_dec_tlu_ctl.scala 961:44] + io.dec_tlu_ic_diag_pkt.icache_wrdata <= csr.io.dec_tlu_ic_diag_pkt.icache_wrdata @[el2_dec_tlu_ctl.scala 961:44] + io.trigger_pkt_any[0].tdata2 <= csr.io.trigger_pkt_any[0].tdata2 @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[0].m <= csr.io.trigger_pkt_any[0].m @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[0].execute <= csr.io.trigger_pkt_any[0].execute @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[0].load <= csr.io.trigger_pkt_any[0].load @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[0].store <= csr.io.trigger_pkt_any[0].store @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[0].match_pkt <= csr.io.trigger_pkt_any[0].match_pkt @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[0].select <= csr.io.trigger_pkt_any[0].select @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[1].tdata2 <= csr.io.trigger_pkt_any[1].tdata2 @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[1].m <= csr.io.trigger_pkt_any[1].m @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[1].execute <= csr.io.trigger_pkt_any[1].execute @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[1].load <= csr.io.trigger_pkt_any[1].load @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[1].store <= csr.io.trigger_pkt_any[1].store @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[1].match_pkt <= csr.io.trigger_pkt_any[1].match_pkt @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[1].select <= csr.io.trigger_pkt_any[1].select @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[2].tdata2 <= csr.io.trigger_pkt_any[2].tdata2 @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[2].m <= csr.io.trigger_pkt_any[2].m @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[2].execute <= csr.io.trigger_pkt_any[2].execute @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[2].load <= csr.io.trigger_pkt_any[2].load @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[2].store <= csr.io.trigger_pkt_any[2].store @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[2].match_pkt <= csr.io.trigger_pkt_any[2].match_pkt @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[2].select <= csr.io.trigger_pkt_any[2].select @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[3].tdata2 <= csr.io.trigger_pkt_any[3].tdata2 @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[3].m <= csr.io.trigger_pkt_any[3].m @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[3].execute <= csr.io.trigger_pkt_any[3].execute @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[3].load <= csr.io.trigger_pkt_any[3].load @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[3].store <= csr.io.trigger_pkt_any[3].store @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[3].match_pkt <= csr.io.trigger_pkt_any[3].match_pkt @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[3].select <= csr.io.trigger_pkt_any[3].select @[el2_dec_tlu_ctl.scala 962:40] + io.dec_tlu_mtval_wb1 <= csr.io.dec_tlu_mtval_wb1 @[el2_dec_tlu_ctl.scala 963:40] + io.dec_tlu_exc_cause_wb1 <= csr.io.dec_tlu_exc_cause_wb1 @[el2_dec_tlu_ctl.scala 964:40] + io.dec_tlu_perfcnt0 <= csr.io.dec_tlu_perfcnt0 @[el2_dec_tlu_ctl.scala 965:40] + io.dec_tlu_perfcnt1 <= csr.io.dec_tlu_perfcnt1 @[el2_dec_tlu_ctl.scala 966:40] + io.dec_tlu_perfcnt2 <= csr.io.dec_tlu_perfcnt2 @[el2_dec_tlu_ctl.scala 967:40] + io.dec_tlu_perfcnt3 <= csr.io.dec_tlu_perfcnt3 @[el2_dec_tlu_ctl.scala 968:40] + io.dec_tlu_misc_clk_override <= csr.io.dec_tlu_misc_clk_override @[el2_dec_tlu_ctl.scala 969:40] + io.dec_tlu_dec_clk_override <= csr.io.dec_tlu_dec_clk_override @[el2_dec_tlu_ctl.scala 970:40] + io.dec_tlu_ifu_clk_override <= csr.io.dec_tlu_ifu_clk_override @[el2_dec_tlu_ctl.scala 971:40] + io.dec_tlu_lsu_clk_override <= csr.io.dec_tlu_lsu_clk_override @[el2_dec_tlu_ctl.scala 972:40] + io.dec_tlu_bus_clk_override <= csr.io.dec_tlu_bus_clk_override @[el2_dec_tlu_ctl.scala 973:40] + io.dec_tlu_pic_clk_override <= csr.io.dec_tlu_pic_clk_override @[el2_dec_tlu_ctl.scala 974:40] + io.dec_tlu_dccm_clk_override <= csr.io.dec_tlu_dccm_clk_override @[el2_dec_tlu_ctl.scala 975:40] + io.dec_tlu_icm_clk_override <= csr.io.dec_tlu_icm_clk_override @[el2_dec_tlu_ctl.scala 976:40] + io.dec_csr_rddata_d <= csr.io.dec_csr_rddata_d @[el2_dec_tlu_ctl.scala 977:40] + io.dec_tlu_pipelining_disable <= csr.io.dec_tlu_pipelining_disable @[el2_dec_tlu_ctl.scala 978:40] + io.dec_tlu_wr_pause_r <= csr.io.dec_tlu_wr_pause_r @[el2_dec_tlu_ctl.scala 979:40] + io.dec_tlu_mrac_ff <= csr.io.dec_tlu_mrac_ff @[el2_dec_tlu_ctl.scala 980:40] + io.dec_tlu_wb_coalescing_disable <= csr.io.dec_tlu_wb_coalescing_disable @[el2_dec_tlu_ctl.scala 981:40] + io.dec_tlu_bpred_disable <= csr.io.dec_tlu_bpred_disable @[el2_dec_tlu_ctl.scala 982:40] + io.dec_tlu_sideeffect_posted_disable <= csr.io.dec_tlu_sideeffect_posted_disable @[el2_dec_tlu_ctl.scala 983:40] + io.dec_tlu_core_ecc_disable <= csr.io.dec_tlu_core_ecc_disable @[el2_dec_tlu_ctl.scala 984:40] + io.dec_tlu_external_ldfwd_disable <= csr.io.dec_tlu_external_ldfwd_disable @[el2_dec_tlu_ctl.scala 985:40] + io.dec_tlu_dma_qos_prty <= csr.io.dec_tlu_dma_qos_prty @[el2_dec_tlu_ctl.scala 986:40] + csr.io.dec_illegal_inst <= io.dec_illegal_inst @[el2_dec_tlu_ctl.scala 987:44] + csr.io.lsu_error_pkt_r.bits.addr <= io.lsu_error_pkt_r.bits.addr @[el2_dec_tlu_ctl.scala 988:44] + csr.io.lsu_error_pkt_r.bits.mscause <= io.lsu_error_pkt_r.bits.mscause @[el2_dec_tlu_ctl.scala 988:44] + csr.io.lsu_error_pkt_r.bits.exc_type <= io.lsu_error_pkt_r.bits.exc_type @[el2_dec_tlu_ctl.scala 988:44] + csr.io.lsu_error_pkt_r.bits.inst_type <= io.lsu_error_pkt_r.bits.inst_type @[el2_dec_tlu_ctl.scala 988:44] + csr.io.lsu_error_pkt_r.bits.single_ecc_error <= io.lsu_error_pkt_r.bits.single_ecc_error @[el2_dec_tlu_ctl.scala 988:44] + csr.io.lsu_error_pkt_r.valid <= io.lsu_error_pkt_r.valid @[el2_dec_tlu_ctl.scala 988:44] + csr.io.mexintpend <= io.mexintpend @[el2_dec_tlu_ctl.scala 989:44] + csr.io.exu_npc_r <= io.exu_npc_r @[el2_dec_tlu_ctl.scala 990:44] + csr.io.mpc_reset_run_req <= io.mpc_reset_run_req @[el2_dec_tlu_ctl.scala 991:44] + csr.io.rst_vec <= io.rst_vec @[el2_dec_tlu_ctl.scala 992:44] + csr.io.core_id <= io.core_id @[el2_dec_tlu_ctl.scala 993:44] + csr.io.dec_timer_rddata_d <= int_timers.io.dec_timer_rddata_d @[el2_dec_tlu_ctl.scala 994:44] + csr.io.dec_timer_read_d <= int_timers.io.dec_timer_read_d @[el2_dec_tlu_ctl.scala 995:44] + csr.io.rfpc_i0_r <= rfpc_i0_r @[el2_dec_tlu_ctl.scala 998:39] + csr.io.i0_trigger_hit_r <= i0_trigger_hit_r @[el2_dec_tlu_ctl.scala 999:39] + csr.io.exc_or_int_valid_r <= exc_or_int_valid_r @[el2_dec_tlu_ctl.scala 1000:39] + csr.io.mret_r <= mret_r @[el2_dec_tlu_ctl.scala 1001:39] + csr.io.dcsr_single_step_running_f <= dcsr_single_step_running_f @[el2_dec_tlu_ctl.scala 1002:39] + csr.io.dec_timer_t0_pulse <= int_timers.io.dec_timer_t0_pulse @[el2_dec_tlu_ctl.scala 1003:39] + csr.io.dec_timer_t1_pulse <= int_timers.io.dec_timer_t1_pulse @[el2_dec_tlu_ctl.scala 1004:39] + csr.io.timer_int_sync <= timer_int_sync @[el2_dec_tlu_ctl.scala 1005:39] + csr.io.soft_int_sync <= soft_int_sync @[el2_dec_tlu_ctl.scala 1006:39] + csr.io.csr_wr_clk <= rvclkhdr.io.l1clk @[el2_dec_tlu_ctl.scala 1007:39] + csr.io.ebreak_to_debug_mode_r <= ebreak_to_debug_mode_r @[el2_dec_tlu_ctl.scala 1008:39] + csr.io.dec_tlu_pmu_fw_halted <= dec_tlu_pmu_fw_halted @[el2_dec_tlu_ctl.scala 1009:39] + csr.io.lsu_fir_error <= io.lsu_fir_error @[el2_dec_tlu_ctl.scala 1010:39] + csr.io.tlu_flush_lower_r_d1 <= tlu_flush_lower_r_d1 @[el2_dec_tlu_ctl.scala 1011:39] + csr.io.dec_tlu_flush_noredir_r_d1 <= dec_tlu_flush_noredir_r_d1 @[el2_dec_tlu_ctl.scala 1012:39] + csr.io.tlu_flush_path_r_d1 <= tlu_flush_path_r_d1 @[el2_dec_tlu_ctl.scala 1013:39] + csr.io.reset_delayed <= reset_delayed @[el2_dec_tlu_ctl.scala 1014:39] + csr.io.interrupt_valid_r <= interrupt_valid_r @[el2_dec_tlu_ctl.scala 1015:39] + csr.io.i0_exception_valid_r <= i0_exception_valid_r @[el2_dec_tlu_ctl.scala 1016:39] + csr.io.lsu_exc_valid_r <= lsu_exc_valid_r @[el2_dec_tlu_ctl.scala 1017:39] + csr.io.mepc_trigger_hit_sel_pc_r <= mepc_trigger_hit_sel_pc_r @[el2_dec_tlu_ctl.scala 1018:39] + csr.io.e4e5_int_clk <= rvclkhdr_3.io.l1clk @[el2_dec_tlu_ctl.scala 1019:39] + csr.io.lsu_i0_exc_r <= lsu_exc_valid_r @[el2_dec_tlu_ctl.scala 1020:39] + csr.io.inst_acc_r <= inst_acc_r @[el2_dec_tlu_ctl.scala 1021:39] + csr.io.inst_acc_second_r <= io.dec_tlu_packet_r.icaf_f1 @[el2_dec_tlu_ctl.scala 1022:39] + csr.io.take_nmi <= take_nmi @[el2_dec_tlu_ctl.scala 1023:39] + csr.io.lsu_error_pkt_addr_r <= io.lsu_error_pkt_r.bits.addr @[el2_dec_tlu_ctl.scala 1024:39] + csr.io.exc_cause_r <= exc_cause_r @[el2_dec_tlu_ctl.scala 1025:39] + csr.io.i0_valid_wb <= i0_valid_wb @[el2_dec_tlu_ctl.scala 1026:39] + csr.io.exc_or_int_valid_r_d1 <= exc_or_int_valid_r_d1 @[el2_dec_tlu_ctl.scala 1027:39] + csr.io.interrupt_valid_r_d1 <= interrupt_valid_r_d1 @[el2_dec_tlu_ctl.scala 1028:39] + csr.io.clk_override <= io.dec_tlu_dec_clk_override @[el2_dec_tlu_ctl.scala 1029:39] + csr.io.i0_exception_valid_r_d1 <= i0_exception_valid_r_d1 @[el2_dec_tlu_ctl.scala 1030:39] + csr.io.lsu_i0_exc_r_d1 <= lsu_i0_exc_r_d1 @[el2_dec_tlu_ctl.scala 1031:39] + csr.io.exc_cause_wb <= exc_cause_wb @[el2_dec_tlu_ctl.scala 1032:39] + csr.io.nmi_lsu_store_type <= nmi_lsu_store_type @[el2_dec_tlu_ctl.scala 1033:39] + csr.io.nmi_lsu_load_type <= nmi_lsu_load_type @[el2_dec_tlu_ctl.scala 1034:39] + csr.io.tlu_i0_commit_cmt <= tlu_i0_commit_cmt @[el2_dec_tlu_ctl.scala 1035:39] + csr.io.ebreak_r <= ebreak_r @[el2_dec_tlu_ctl.scala 1036:39] + csr.io.ecall_r <= ecall_r @[el2_dec_tlu_ctl.scala 1037:39] + csr.io.illegal_r <= illegal_r @[el2_dec_tlu_ctl.scala 1038:39] + csr.io.mdseac_locked_f <= mdseac_locked_f @[el2_dec_tlu_ctl.scala 1039:39] + csr.io.nmi_int_detected_f <= nmi_int_detected_f @[el2_dec_tlu_ctl.scala 1040:39] + csr.io.internal_dbg_halt_mode_f2 <= internal_dbg_halt_mode_f2 @[el2_dec_tlu_ctl.scala 1041:39] + csr.io.ext_int_freeze_d1 <= ext_int_freeze_d1 @[el2_dec_tlu_ctl.scala 1042:39] + csr.io.ic_perr_r_d1 <= ic_perr_r_d1 @[el2_dec_tlu_ctl.scala 1043:39] + csr.io.iccm_sbecc_r_d1 <= iccm_sbecc_r_d1 @[el2_dec_tlu_ctl.scala 1044:39] + csr.io.lsu_single_ecc_error_r_d1 <= lsu_single_ecc_error_r_d1 @[el2_dec_tlu_ctl.scala 1045:39] + csr.io.ifu_miss_state_idle_f <= ifu_miss_state_idle_f @[el2_dec_tlu_ctl.scala 1046:39] + csr.io.lsu_idle_any_f <= lsu_idle_any_f @[el2_dec_tlu_ctl.scala 1047:39] + csr.io.dbg_tlu_halted_f <= dbg_tlu_halted_f @[el2_dec_tlu_ctl.scala 1048:39] + csr.io.dbg_tlu_halted <= dbg_tlu_halted @[el2_dec_tlu_ctl.scala 1049:39] + csr.io.debug_halt_req_f <= debug_halt_req_f @[el2_dec_tlu_ctl.scala 1050:51] + csr.io.take_ext_int_start <= take_ext_int_start @[el2_dec_tlu_ctl.scala 1051:47] + csr.io.trigger_hit_dmode_r_d1 <= trigger_hit_dmode_r_d1 @[el2_dec_tlu_ctl.scala 1052:43] + csr.io.trigger_hit_r_d1 <= trigger_hit_r_d1 @[el2_dec_tlu_ctl.scala 1053:43] + csr.io.dcsr_single_step_done_f <= dcsr_single_step_done_f @[el2_dec_tlu_ctl.scala 1054:43] + csr.io.ebreak_to_debug_mode_r_d1 <= ebreak_to_debug_mode_r_d1 @[el2_dec_tlu_ctl.scala 1055:39] + csr.io.debug_halt_req <= debug_halt_req @[el2_dec_tlu_ctl.scala 1056:51] + csr.io.allow_dbg_halt_csr_write <= allow_dbg_halt_csr_write @[el2_dec_tlu_ctl.scala 1057:39] + csr.io.internal_dbg_halt_mode_f <= debug_mode_status @[el2_dec_tlu_ctl.scala 1058:39] + csr.io.enter_debug_halt_req <= enter_debug_halt_req @[el2_dec_tlu_ctl.scala 1059:39] + csr.io.internal_dbg_halt_mode <= internal_dbg_halt_mode @[el2_dec_tlu_ctl.scala 1060:39] + csr.io.request_debug_mode_done <= request_debug_mode_done @[el2_dec_tlu_ctl.scala 1061:39] + csr.io.request_debug_mode_r <= request_debug_mode_r @[el2_dec_tlu_ctl.scala 1062:39] + csr.io.update_hit_bit_r <= update_hit_bit_r @[el2_dec_tlu_ctl.scala 1063:39] + csr.io.take_timer_int <= take_timer_int @[el2_dec_tlu_ctl.scala 1064:39] + csr.io.take_int_timer0_int <= take_int_timer0_int @[el2_dec_tlu_ctl.scala 1065:39] + csr.io.take_int_timer1_int <= take_int_timer1_int @[el2_dec_tlu_ctl.scala 1066:39] + csr.io.take_ext_int <= take_ext_int @[el2_dec_tlu_ctl.scala 1067:39] + csr.io.tlu_flush_lower_r <= tlu_flush_lower_r @[el2_dec_tlu_ctl.scala 1068:39] + csr.io.dec_tlu_br0_error_r <= dec_tlu_br0_error_r @[el2_dec_tlu_ctl.scala 1069:39] + csr.io.dec_tlu_br0_start_error_r <= dec_tlu_br0_start_error_r @[el2_dec_tlu_ctl.scala 1070:39] + csr.io.lsu_pmu_load_external_r <= lsu_pmu_load_external_r @[el2_dec_tlu_ctl.scala 1071:39] + csr.io.lsu_pmu_store_external_r <= lsu_pmu_store_external_r @[el2_dec_tlu_ctl.scala 1072:39] + csr.io.csr_pkt.legal <= csr_pkt.legal @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.postsync <= csr_pkt.postsync @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.presync <= csr_pkt.presync @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_dicago <= csr_pkt.csr_dicago @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_dicad1 <= csr_pkt.csr_dicad1 @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_dicad0 <= csr_pkt.csr_dicad0 @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_dicad0h <= csr_pkt.csr_dicad0h @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_dicawics <= csr_pkt.csr_dicawics @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mfdhs <= csr_pkt.csr_mfdhs @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mfdht <= csr_pkt.csr_mfdht @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mdccmect <= csr_pkt.csr_mdccmect @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_miccmect <= csr_pkt.csr_miccmect @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_micect <= csr_pkt.csr_micect @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mdeau <= csr_pkt.csr_mdeau @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_meicpct <= csr_pkt.csr_meicpct @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mcpc <= csr_pkt.csr_mcpc @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mpmc <= csr_pkt.csr_mpmc @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mitcnt1 <= csr_pkt.csr_mitcnt1 @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mitcnt0 <= csr_pkt.csr_mitcnt0 @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mitb1 <= csr_pkt.csr_mitb1 @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mitb0 <= csr_pkt.csr_mitb0 @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mitctl1 <= csr_pkt.csr_mitctl1 @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mitctl0 <= csr_pkt.csr_mitctl0 @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mcountinhibit <= csr_pkt.csr_mcountinhibit @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mhpme6 <= csr_pkt.csr_mhpme6 @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mhpme5 <= csr_pkt.csr_mhpme5 @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mhpme4 <= csr_pkt.csr_mhpme4 @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mhpme3 <= csr_pkt.csr_mhpme3 @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mhpmc6h <= csr_pkt.csr_mhpmc6h @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mhpmc5h <= csr_pkt.csr_mhpmc5h @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mhpmc4h <= csr_pkt.csr_mhpmc4h @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mhpmc3h <= csr_pkt.csr_mhpmc3h @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mhpmc6 <= csr_pkt.csr_mhpmc6 @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mhpmc5 <= csr_pkt.csr_mhpmc5 @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mhpmc4 <= csr_pkt.csr_mhpmc4 @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mhpmc3 <= csr_pkt.csr_mhpmc3 @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mtdata2 <= csr_pkt.csr_mtdata2 @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mtdata1 <= csr_pkt.csr_mtdata1 @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mtsel <= csr_pkt.csr_mtsel @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_dpc <= csr_pkt.csr_dpc @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mfdc <= csr_pkt.csr_mfdc @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mcgc <= csr_pkt.csr_mcgc @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_dcsr <= csr_pkt.csr_dcsr @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_meicidpl <= csr_pkt.csr_meicidpl @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_meicurpl <= csr_pkt.csr_meicurpl @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_meipt <= csr_pkt.csr_meipt @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_meivt <= csr_pkt.csr_meivt @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_meihap <= csr_pkt.csr_meihap @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mdseac <= csr_pkt.csr_mdseac @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_dmst <= csr_pkt.csr_dmst @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mrac <= csr_pkt.csr_mrac @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mtval <= csr_pkt.csr_mtval @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mscause <= csr_pkt.csr_mscause @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mcause <= csr_pkt.csr_mcause @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mepc <= csr_pkt.csr_mepc @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mscratch <= csr_pkt.csr_mscratch @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_minstreth <= csr_pkt.csr_minstreth @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_minstretl <= csr_pkt.csr_minstretl @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mcycleh <= csr_pkt.csr_mcycleh @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mcyclel <= csr_pkt.csr_mcyclel @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mie <= csr_pkt.csr_mie @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mip <= csr_pkt.csr_mip @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mtvec <= csr_pkt.csr_mtvec @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mstatus <= csr_pkt.csr_mstatus @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mhartid <= csr_pkt.csr_mhartid @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mimpid <= csr_pkt.csr_mimpid @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_marchid <= csr_pkt.csr_marchid @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mvendorid <= csr_pkt.csr_mvendorid @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_misa <= csr_pkt.csr_misa @[el2_dec_tlu_ctl.scala 1073:39] + npc_r <= csr.io.npc_r @[el2_dec_tlu_ctl.scala 1075:31] + npc_r_d1 <= csr.io.npc_r_d1 @[el2_dec_tlu_ctl.scala 1076:31] + mie_ns <= csr.io.mie_ns @[el2_dec_tlu_ctl.scala 1077:31] + mepc <= csr.io.mepc @[el2_dec_tlu_ctl.scala 1078:31] + mdseac_locked_ns <= csr.io.mdseac_locked_ns @[el2_dec_tlu_ctl.scala 1079:31] + force_halt <= csr.io.force_halt @[el2_dec_tlu_ctl.scala 1080:31] + dpc <= csr.io.dpc @[el2_dec_tlu_ctl.scala 1081:31] + mstatus_mie_ns <= csr.io.mstatus_mie_ns @[el2_dec_tlu_ctl.scala 1082:31] + dec_csr_wen_r_mod <= csr.io.dec_csr_wen_r_mod @[el2_dec_tlu_ctl.scala 1083:31] + fw_halt_req <= csr.io.fw_halt_req @[el2_dec_tlu_ctl.scala 1084:31] + mstatus <= csr.io.mstatus @[el2_dec_tlu_ctl.scala 1085:31] + dcsr <= csr.io.dcsr @[el2_dec_tlu_ctl.scala 1086:31] + mtvec <= csr.io.mtvec @[el2_dec_tlu_ctl.scala 1087:31] + mip <= csr.io.mip @[el2_dec_tlu_ctl.scala 1088:31] + mtdata1_t[0] <= csr.io.mtdata1_t[0] @[el2_dec_tlu_ctl.scala 1089:33] + mtdata1_t[1] <= csr.io.mtdata1_t[1] @[el2_dec_tlu_ctl.scala 1089:33] + mtdata1_t[2] <= csr.io.mtdata1_t[2] @[el2_dec_tlu_ctl.scala 1089:33] + mtdata1_t[3] <= csr.io.mtdata1_t[3] @[el2_dec_tlu_ctl.scala 1089:33] + inst csr_read of el2_dec_decode_csr_read @[el2_dec_tlu_ctl.scala 1090:22] + csr_read.clock <= clock + csr_read.reset <= reset + csr_read.io.dec_csr_rdaddr_d <= io.dec_csr_rdaddr_d @[el2_dec_tlu_ctl.scala 1091:31] + csr_pkt.legal <= csr_read.io.csr_pkt.legal @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.postsync <= csr_read.io.csr_pkt.postsync @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.presync <= csr_read.io.csr_pkt.presync @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_dicago <= csr_read.io.csr_pkt.csr_dicago @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_dicad1 <= csr_read.io.csr_pkt.csr_dicad1 @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_dicad0 <= csr_read.io.csr_pkt.csr_dicad0 @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_dicad0h <= csr_read.io.csr_pkt.csr_dicad0h @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_dicawics <= csr_read.io.csr_pkt.csr_dicawics @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mfdhs <= csr_read.io.csr_pkt.csr_mfdhs @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mfdht <= csr_read.io.csr_pkt.csr_mfdht @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mdccmect <= csr_read.io.csr_pkt.csr_mdccmect @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_miccmect <= csr_read.io.csr_pkt.csr_miccmect @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_micect <= csr_read.io.csr_pkt.csr_micect @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mdeau <= csr_read.io.csr_pkt.csr_mdeau @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_meicpct <= csr_read.io.csr_pkt.csr_meicpct @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mcpc <= csr_read.io.csr_pkt.csr_mcpc @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mpmc <= csr_read.io.csr_pkt.csr_mpmc @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mitcnt1 <= csr_read.io.csr_pkt.csr_mitcnt1 @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mitcnt0 <= csr_read.io.csr_pkt.csr_mitcnt0 @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mitb1 <= csr_read.io.csr_pkt.csr_mitb1 @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mitb0 <= csr_read.io.csr_pkt.csr_mitb0 @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mitctl1 <= csr_read.io.csr_pkt.csr_mitctl1 @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mitctl0 <= csr_read.io.csr_pkt.csr_mitctl0 @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mcountinhibit <= csr_read.io.csr_pkt.csr_mcountinhibit @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mhpme6 <= csr_read.io.csr_pkt.csr_mhpme6 @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mhpme5 <= csr_read.io.csr_pkt.csr_mhpme5 @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mhpme4 <= csr_read.io.csr_pkt.csr_mhpme4 @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mhpme3 <= csr_read.io.csr_pkt.csr_mhpme3 @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mhpmc6h <= csr_read.io.csr_pkt.csr_mhpmc6h @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mhpmc5h <= csr_read.io.csr_pkt.csr_mhpmc5h @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mhpmc4h <= csr_read.io.csr_pkt.csr_mhpmc4h @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mhpmc3h <= csr_read.io.csr_pkt.csr_mhpmc3h @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mhpmc6 <= csr_read.io.csr_pkt.csr_mhpmc6 @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mhpmc5 <= csr_read.io.csr_pkt.csr_mhpmc5 @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mhpmc4 <= csr_read.io.csr_pkt.csr_mhpmc4 @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mhpmc3 <= csr_read.io.csr_pkt.csr_mhpmc3 @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mtdata2 <= csr_read.io.csr_pkt.csr_mtdata2 @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mtdata1 <= csr_read.io.csr_pkt.csr_mtdata1 @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mtsel <= csr_read.io.csr_pkt.csr_mtsel @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_dpc <= csr_read.io.csr_pkt.csr_dpc @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mfdc <= csr_read.io.csr_pkt.csr_mfdc @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mcgc <= csr_read.io.csr_pkt.csr_mcgc @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_dcsr <= csr_read.io.csr_pkt.csr_dcsr @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_meicidpl <= csr_read.io.csr_pkt.csr_meicidpl @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_meicurpl <= csr_read.io.csr_pkt.csr_meicurpl @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_meipt <= csr_read.io.csr_pkt.csr_meipt @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_meivt <= csr_read.io.csr_pkt.csr_meivt @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_meihap <= csr_read.io.csr_pkt.csr_meihap @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mdseac <= csr_read.io.csr_pkt.csr_mdseac @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_dmst <= csr_read.io.csr_pkt.csr_dmst @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mrac <= csr_read.io.csr_pkt.csr_mrac @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mtval <= csr_read.io.csr_pkt.csr_mtval @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mscause <= csr_read.io.csr_pkt.csr_mscause @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mcause <= csr_read.io.csr_pkt.csr_mcause @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mepc <= csr_read.io.csr_pkt.csr_mepc @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mscratch <= csr_read.io.csr_pkt.csr_mscratch @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_minstreth <= csr_read.io.csr_pkt.csr_minstreth @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_minstretl <= csr_read.io.csr_pkt.csr_minstretl @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mcycleh <= csr_read.io.csr_pkt.csr_mcycleh @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mcyclel <= csr_read.io.csr_pkt.csr_mcyclel @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mie <= csr_read.io.csr_pkt.csr_mie @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mip <= csr_read.io.csr_pkt.csr_mip @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mtvec <= csr_read.io.csr_pkt.csr_mtvec @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mstatus <= csr_read.io.csr_pkt.csr_mstatus @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mhartid <= csr_read.io.csr_pkt.csr_mhartid @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mimpid <= csr_read.io.csr_pkt.csr_mimpid @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_marchid <= csr_read.io.csr_pkt.csr_marchid @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mvendorid <= csr_read.io.csr_pkt.csr_mvendorid @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_misa <= csr_read.io.csr_pkt.csr_misa @[el2_dec_tlu_ctl.scala 1092:10] + node _T_864 = and(csr_pkt.presync, io.dec_csr_any_unq_d) @[el2_dec_tlu_ctl.scala 1094:44] + node _T_865 = not(io.dec_csr_wen_unq_d) @[el2_dec_tlu_ctl.scala 1094:69] + node _T_866 = and(_T_864, _T_865) @[el2_dec_tlu_ctl.scala 1094:67] + io.dec_tlu_presync_d <= _T_866 @[el2_dec_tlu_ctl.scala 1094:25] + node _T_867 = and(csr_pkt.postsync, io.dec_csr_any_unq_d) @[el2_dec_tlu_ctl.scala 1095:45] + io.dec_tlu_postsync_d <= _T_867 @[el2_dec_tlu_ctl.scala 1095:25] + node _T_868 = or(csr_pkt.csr_mitcnt0, csr_pkt.csr_mitcnt1) @[el2_dec_tlu_ctl.scala 1098:52] + node _T_869 = or(_T_868, csr_pkt.csr_mitb0) @[el2_dec_tlu_ctl.scala 1098:74] + node _T_870 = or(_T_869, csr_pkt.csr_mitb1) @[el2_dec_tlu_ctl.scala 1098:94] + node _T_871 = or(_T_870, csr_pkt.csr_mitctl0) @[el2_dec_tlu_ctl.scala 1098:114] + node _T_872 = or(_T_871, csr_pkt.csr_mitctl1) @[el2_dec_tlu_ctl.scala 1098:136] + node _T_873 = not(UInt<1>("h01")) @[el2_dec_tlu_ctl.scala 1098:161] + node conditionally_illegal = and(_T_872, _T_873) @[el2_dec_tlu_ctl.scala 1098:159] + node _T_874 = or(csr_pkt.csr_dcsr, csr_pkt.csr_dpc) @[el2_dec_tlu_ctl.scala 1099:57] + node _T_875 = or(_T_874, csr_pkt.csr_dmst) @[el2_dec_tlu_ctl.scala 1099:75] + node _T_876 = or(_T_875, csr_pkt.csr_dicawics) @[el2_dec_tlu_ctl.scala 1099:94] + node _T_877 = or(_T_876, csr_pkt.csr_dicad0) @[el2_dec_tlu_ctl.scala 1099:117] + node _T_878 = or(_T_877, csr_pkt.csr_dicad0h) @[el2_dec_tlu_ctl.scala 1099:138] + node _T_879 = or(_T_878, csr_pkt.csr_dicad1) @[el2_dec_tlu_ctl.scala 1099:160] + node _T_880 = or(_T_879, csr_pkt.csr_dicago) @[el2_dec_tlu_ctl.scala 1099:181] + node _T_881 = not(_T_880) @[el2_dec_tlu_ctl.scala 1099:38] + node _T_882 = or(_T_881, dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 1099:203] + node _T_883 = and(csr_pkt.legal, _T_882) @[el2_dec_tlu_ctl.scala 1099:35] + node _T_884 = not(fast_int_meicpct) @[el2_dec_tlu_ctl.scala 1099:225] + node _T_885 = and(_T_883, _T_884) @[el2_dec_tlu_ctl.scala 1099:223] + node _T_886 = not(conditionally_illegal) @[el2_dec_tlu_ctl.scala 1099:245] + node valid_csr = and(_T_885, _T_886) @[el2_dec_tlu_ctl.scala 1099:243] + node _T_887 = and(io.dec_csr_any_unq_d, valid_csr) @[el2_dec_tlu_ctl.scala 1101:48] + node _T_888 = or(csr_pkt.csr_mvendorid, csr_pkt.csr_marchid) @[el2_dec_tlu_ctl.scala 1101:109] + node _T_889 = or(_T_888, csr_pkt.csr_mimpid) @[el2_dec_tlu_ctl.scala 1101:131] + node _T_890 = or(_T_889, csr_pkt.csr_mhartid) @[el2_dec_tlu_ctl.scala 1101:152] + node _T_891 = or(_T_890, csr_pkt.csr_mdseac) @[el2_dec_tlu_ctl.scala 1101:174] + node _T_892 = or(_T_891, csr_pkt.csr_meihap) @[el2_dec_tlu_ctl.scala 1101:195] + node _T_893 = and(io.dec_csr_wen_unq_d, _T_892) @[el2_dec_tlu_ctl.scala 1101:84] + node _T_894 = not(_T_893) @[el2_dec_tlu_ctl.scala 1101:61] + node _T_895 = and(_T_887, _T_894) @[el2_dec_tlu_ctl.scala 1101:59] + io.dec_csr_legal_d <= _T_895 @[el2_dec_tlu_ctl.scala 1101:22] + diff --git a/el2_dec_tlu_ctl.v b/el2_dec_tlu_ctl.v new file mode 100644 index 00000000..da918364 --- /dev/null +++ b/el2_dec_tlu_ctl.v @@ -0,0 +1,7181 @@ +module rvclkhdr( + output io_l1clk, + input io_clk, + input io_en, + input io_scan_mode +); + wire clkhdr_Q; // @[el2_lib.scala 474:26] + wire clkhdr_CK; // @[el2_lib.scala 474:26] + wire clkhdr_EN; // @[el2_lib.scala 474:26] + wire clkhdr_SE; // @[el2_lib.scala 474:26] + gated_latch clkhdr ( // @[el2_lib.scala 474:26] + .Q(clkhdr_Q), + .CK(clkhdr_CK), + .EN(clkhdr_EN), + .SE(clkhdr_SE) + ); + assign io_l1clk = clkhdr_Q; // @[el2_lib.scala 475:14] + assign clkhdr_CK = io_clk; // @[el2_lib.scala 476:18] + assign clkhdr_EN = io_en; // @[el2_lib.scala 477:18] + assign clkhdr_SE = io_scan_mode; // @[el2_lib.scala 478:18] +endmodule +module el2_dec_timer_ctl( + input clock, + input reset, + input io_free_clk, + input io_scan_mode, + input io_dec_csr_wen_r_mod, + input [11:0] io_dec_csr_wraddr_r, + input [31:0] io_dec_csr_wrdata_r, + input io_csr_mitctl0, + input io_csr_mitctl1, + input io_csr_mitb0, + input io_csr_mitb1, + input io_csr_mitcnt0, + input io_csr_mitcnt1, + input io_dec_pause_state, + input io_dec_tlu_pmu_fw_halted, + input io_internal_dbg_halt_timers, + output [31:0] io_dec_timer_rddata_d, + output io_dec_timer_read_d, + output io_dec_timer_t0_pulse, + output io_dec_timer_t1_pulse +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; +`endif // RANDOMIZE_REG_INIT + wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_2_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_2_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 508:23] + reg [31:0] mitcnt0; // @[el2_lib.scala 514:16] + reg [31:0] mitb0_b; // @[el2_lib.scala 514:16] + wire [31:0] mitb0 = ~mitb0_b; // @[el2_dec_tlu_ctl.scala 2791:14] + wire mit0_match_ns = mitcnt0 >= mitb0; // @[el2_dec_tlu_ctl.scala 2752:30] + reg [31:0] mitcnt1; // @[el2_lib.scala 514:16] + reg [31:0] mitb1_b; // @[el2_lib.scala 514:16] + wire [31:0] mitb1 = ~mitb1_b; // @[el2_dec_tlu_ctl.scala 2800:12] + wire mit1_match_ns = mitcnt1 >= mitb1; // @[el2_dec_tlu_ctl.scala 2753:30] + wire _T = io_dec_csr_wraddr_r == 12'h7d2; // @[el2_dec_tlu_ctl.scala 2763:66] + wire wr_mitcnt0_r = io_dec_csr_wen_r_mod & _T; // @[el2_dec_tlu_ctl.scala 2763:43] + reg [1:0] _T_57; // @[el2_dec_tlu_ctl.scala 2816:67] + reg mitctl0_0_b; // @[el2_dec_tlu_ctl.scala 2815:54] + wire _T_58 = ~mitctl0_0_b; // @[el2_dec_tlu_ctl.scala 2816:90] + wire [2:0] mitctl0 = {_T_57,_T_58}; // @[Cat.scala 29:58] + wire _T_2 = ~io_dec_pause_state; // @[el2_dec_tlu_ctl.scala 2765:50] + wire _T_4 = _T_2 | mitctl0[2]; // @[el2_dec_tlu_ctl.scala 2765:70] + wire _T_5 = mitctl0[0] & _T_4; // @[el2_dec_tlu_ctl.scala 2765:47] + wire _T_6 = ~io_dec_tlu_pmu_fw_halted; // @[el2_dec_tlu_ctl.scala 2765:106] + wire _T_8 = _T_6 | mitctl0[1]; // @[el2_dec_tlu_ctl.scala 2765:132] + wire _T_9 = _T_5 & _T_8; // @[el2_dec_tlu_ctl.scala 2765:103] + wire _T_10 = ~io_internal_dbg_halt_timers; // @[el2_dec_tlu_ctl.scala 2765:167] + wire mitcnt0_inc_ok = _T_9 & _T_10; // @[el2_dec_tlu_ctl.scala 2765:165] + wire [31:0] mitcnt0_inc = mitcnt0 + 32'h1; // @[el2_dec_tlu_ctl.scala 2766:29] + wire _T_15 = wr_mitcnt0_r | mitcnt0_inc_ok; // @[el2_dec_tlu_ctl.scala 2768:59] + wire _T_19 = io_dec_csr_wraddr_r == 12'h7d5; // @[el2_dec_tlu_ctl.scala 2775:66] + wire wr_mitcnt1_r = io_dec_csr_wen_r_mod & _T_19; // @[el2_dec_tlu_ctl.scala 2775:43] + reg [2:0] _T_66; // @[el2_dec_tlu_ctl.scala 2830:46] + reg mitctl1_0_b; // @[el2_dec_tlu_ctl.scala 2829:49] + wire _T_67 = ~mitctl1_0_b; // @[el2_dec_tlu_ctl.scala 2830:69] + wire [3:0] mitctl1 = {_T_66,_T_67}; // @[Cat.scala 29:58] + wire _T_23 = _T_2 | mitctl1[2]; // @[el2_dec_tlu_ctl.scala 2777:70] + wire _T_24 = mitctl1[0] & _T_23; // @[el2_dec_tlu_ctl.scala 2777:47] + wire _T_27 = _T_6 | mitctl1[1]; // @[el2_dec_tlu_ctl.scala 2777:132] + wire _T_28 = _T_24 & _T_27; // @[el2_dec_tlu_ctl.scala 2777:103] + wire mitcnt1_inc_ok = _T_28 & _T_10; // @[el2_dec_tlu_ctl.scala 2777:165] + wire _T_32 = ~mitctl1[3]; // @[el2_dec_tlu_ctl.scala 2780:54] + wire _T_33 = _T_32 | mit0_match_ns; // @[el2_dec_tlu_ctl.scala 2780:66] + wire [31:0] _T_34 = {31'h0,_T_33}; // @[Cat.scala 29:58] + wire [31:0] mitcnt1_inc = mitcnt1 + _T_34; // @[el2_dec_tlu_ctl.scala 2780:29] + wire _T_39 = wr_mitcnt1_r | mitcnt1_inc_ok; // @[el2_dec_tlu_ctl.scala 2782:52] + wire _T_43 = io_dec_csr_wraddr_r == 12'h7d3; // @[el2_dec_tlu_ctl.scala 2789:64] + wire _T_47 = io_dec_csr_wraddr_r == 12'h7d6; // @[el2_dec_tlu_ctl.scala 2798:63] + wire _T_51 = io_dec_csr_wraddr_r == 12'h7d4; // @[el2_dec_tlu_ctl.scala 2811:66] + wire wr_mitctl0_r = io_dec_csr_wen_r_mod & _T_51; // @[el2_dec_tlu_ctl.scala 2811:43] + wire [2:0] mitctl0_ns = wr_mitctl0_r ? io_dec_csr_wrdata_r[2:0] : mitctl0; // @[el2_dec_tlu_ctl.scala 2812:31] + wire _T_60 = io_dec_csr_wraddr_r == 12'h7d7; // @[el2_dec_tlu_ctl.scala 2826:65] + wire wr_mitctl1_r = io_dec_csr_wen_r_mod & _T_60; // @[el2_dec_tlu_ctl.scala 2826:43] + wire [3:0] mitctl1_ns = wr_mitctl1_r ? io_dec_csr_wrdata_r[3:0] : mitctl1; // @[el2_dec_tlu_ctl.scala 2827:31] + wire _T_69 = io_csr_mitcnt1 | io_csr_mitcnt0; // @[el2_dec_tlu_ctl.scala 2832:43] + wire _T_70 = _T_69 | io_csr_mitb1; // @[el2_dec_tlu_ctl.scala 2832:60] + wire _T_71 = _T_70 | io_csr_mitb0; // @[el2_dec_tlu_ctl.scala 2832:75] + wire _T_72 = _T_71 | io_csr_mitctl0; // @[el2_dec_tlu_ctl.scala 2832:90] + wire [31:0] _T_81 = {29'h0,_T_57,_T_58}; // @[Cat.scala 29:58] + wire [31:0] _T_84 = {28'h0,_T_66,_T_67}; // @[Cat.scala 29:58] + wire [31:0] _T_85 = io_csr_mitcnt0 ? mitcnt0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_86 = io_csr_mitcnt1 ? mitcnt1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_87 = io_csr_mitb0 ? mitb0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_88 = io_csr_mitb1 ? mitb1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_89 = io_csr_mitctl0 ? _T_81 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_90 = io_csr_mitctl1 ? _T_84 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_91 = _T_85 | _T_86; // @[Mux.scala 27:72] + wire [31:0] _T_92 = _T_91 | _T_87; // @[Mux.scala 27:72] + wire [31:0] _T_93 = _T_92 | _T_88; // @[Mux.scala 27:72] + wire [31:0] _T_94 = _T_93 | _T_89; // @[Mux.scala 27:72] + rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_io_l1clk), + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en), + .io_scan_mode(rvclkhdr_io_scan_mode) + ); + rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_1_io_l1clk), + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en), + .io_scan_mode(rvclkhdr_1_io_scan_mode) + ); + rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_2_io_l1clk), + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en), + .io_scan_mode(rvclkhdr_2_io_scan_mode) + ); + rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_3_io_l1clk), + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en), + .io_scan_mode(rvclkhdr_3_io_scan_mode) + ); + assign io_dec_timer_rddata_d = _T_94 | _T_90; // @[el2_dec_tlu_ctl.scala 2833:33] + assign io_dec_timer_read_d = _T_72 | io_csr_mitctl1; // @[el2_dec_tlu_ctl.scala 2832:25] + assign io_dec_timer_t0_pulse = mitcnt0 >= mitb0; // @[el2_dec_tlu_ctl.scala 2755:25] + assign io_dec_timer_t1_pulse = mitcnt1 >= mitb1; // @[el2_dec_tlu_ctl.scala 2756:25] + assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_io_en = _T_15 | mit0_match_ns; // @[el2_lib.scala 511:17] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_1_io_en = _T_39 | mit1_match_ns; // @[el2_lib.scala 511:17] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_2_io_en = io_dec_csr_wen_r_mod & _T_43; // @[el2_lib.scala 511:17] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_3_io_en = io_dec_csr_wen_r_mod & _T_47; // @[el2_lib.scala 511:17] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + mitcnt0 = _RAND_0[31:0]; + _RAND_1 = {1{`RANDOM}}; + mitb0_b = _RAND_1[31:0]; + _RAND_2 = {1{`RANDOM}}; + mitcnt1 = _RAND_2[31:0]; + _RAND_3 = {1{`RANDOM}}; + mitb1_b = _RAND_3[31:0]; + _RAND_4 = {1{`RANDOM}}; + _T_57 = _RAND_4[1:0]; + _RAND_5 = {1{`RANDOM}}; + mitctl0_0_b = _RAND_5[0:0]; + _RAND_6 = {1{`RANDOM}}; + _T_66 = _RAND_6[2:0]; + _RAND_7 = {1{`RANDOM}}; + mitctl1_0_b = _RAND_7[0:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + mitcnt0 = 32'h0; + end + if (reset) begin + mitb0_b = 32'h0; + end + if (reset) begin + mitcnt1 = 32'h0; + end + if (reset) begin + mitb1_b = 32'h0; + end + if (reset) begin + _T_57 = 2'h0; + end + if (reset) begin + mitctl0_0_b = 1'h0; + end + if (reset) begin + _T_66 = 3'h0; + end + if (reset) begin + mitctl1_0_b = 1'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin + if (reset) begin + mitcnt0 <= 32'h0; + end else if (mit0_match_ns) begin + mitcnt0 <= 32'h0; + end else if (wr_mitcnt0_r) begin + mitcnt0 <= io_dec_csr_wrdata_r; + end else begin + mitcnt0 <= mitcnt0_inc; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + mitb0_b <= 32'h0; + end else begin + mitb0_b <= ~io_dec_csr_wrdata_r; + end + end + always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin + if (reset) begin + mitcnt1 <= 32'h0; + end else if (mit1_match_ns) begin + mitcnt1 <= 32'h0; + end else if (wr_mitcnt1_r) begin + mitcnt1 <= io_dec_csr_wrdata_r; + end else begin + mitcnt1 <= mitcnt1_inc; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + mitb1_b <= 32'h0; + end else begin + mitb1_b <= ~io_dec_csr_wrdata_r; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + _T_57 <= 2'h0; + end else begin + _T_57 <= mitctl0_ns[2:1]; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + mitctl0_0_b <= 1'h0; + end else begin + mitctl0_0_b <= ~mitctl0_ns[0]; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + _T_66 <= 3'h0; + end else begin + _T_66 <= mitctl1_ns[3:1]; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + mitctl1_0_b <= 1'h0; + end else begin + mitctl1_0_b <= ~mitctl1_ns[0]; + end + end +endmodule +module csr_tlu( + input clock, + input reset, + input io_free_clk, + input io_active_clk, + input io_scan_mode, + input [31:0] io_dec_csr_wrdata_r, + input [11:0] io_dec_csr_wraddr_r, + input [11:0] io_dec_csr_rdaddr_d, + input io_dec_csr_wen_unq_d, + input io_dec_i0_decode_d, + output [70:0] io_dec_tlu_ic_diag_pkt_icache_wrdata, + output [16:0] io_dec_tlu_ic_diag_pkt_icache_dicawics, + output io_dec_tlu_ic_diag_pkt_icache_rd_valid, + output io_dec_tlu_ic_diag_pkt_icache_wr_valid, + input io_ifu_ic_debug_rd_data_valid, + output io_trigger_pkt_any_0_select, + output io_trigger_pkt_any_0_match_pkt, + output io_trigger_pkt_any_0_store, + output io_trigger_pkt_any_0_load, + output io_trigger_pkt_any_0_execute, + output io_trigger_pkt_any_0_m, + output [31:0] io_trigger_pkt_any_0_tdata2, + output io_trigger_pkt_any_1_select, + output io_trigger_pkt_any_1_match_pkt, + output io_trigger_pkt_any_1_store, + output io_trigger_pkt_any_1_load, + output io_trigger_pkt_any_1_execute, + output io_trigger_pkt_any_1_m, + output [31:0] io_trigger_pkt_any_1_tdata2, + output io_trigger_pkt_any_2_select, + output io_trigger_pkt_any_2_match_pkt, + output io_trigger_pkt_any_2_store, + output io_trigger_pkt_any_2_load, + output io_trigger_pkt_any_2_execute, + output io_trigger_pkt_any_2_m, + output [31:0] io_trigger_pkt_any_2_tdata2, + output io_trigger_pkt_any_3_select, + output io_trigger_pkt_any_3_match_pkt, + output io_trigger_pkt_any_3_store, + output io_trigger_pkt_any_3_load, + output io_trigger_pkt_any_3_execute, + output io_trigger_pkt_any_3_m, + output [31:0] io_trigger_pkt_any_3_tdata2, + input io_ifu_pmu_bus_trxn, + input io_dma_iccm_stall_any, + input io_dma_dccm_stall_any, + input io_lsu_store_stall_any, + input io_dec_pmu_presync_stall, + input io_dec_pmu_postsync_stall, + input io_dec_pmu_decode_stall, + input io_ifu_pmu_fetch_stall, + input [1:0] io_dec_tlu_packet_r_icaf_type, + input [3:0] io_dec_tlu_packet_r_pmu_i0_itype, + input io_dec_tlu_packet_r_pmu_i0_br_unpred, + input io_dec_tlu_packet_r_pmu_divide, + input io_dec_tlu_packet_r_pmu_lsu_misaligned, + input io_exu_pmu_i0_br_ataken, + input io_exu_pmu_i0_br_misp, + input io_dec_pmu_instr_decoded, + input io_ifu_pmu_instr_aligned, + input io_exu_pmu_i0_pc4, + input io_ifu_pmu_ic_miss, + input io_ifu_pmu_ic_hit, + output io_dec_tlu_int_valid_wb1, + output io_dec_tlu_i0_exc_valid_wb1, + output io_dec_tlu_i0_valid_wb1, + input io_dec_csr_wen_r, + output [31:0] io_dec_tlu_mtval_wb1, + output [4:0] io_dec_tlu_exc_cause_wb1, + output io_dec_tlu_perfcnt0, + output io_dec_tlu_perfcnt1, + output io_dec_tlu_perfcnt2, + output io_dec_tlu_perfcnt3, + input io_dec_tlu_dbg_halted, + input io_dma_pmu_dccm_write, + input io_dma_pmu_dccm_read, + input io_dma_pmu_any_write, + input io_dma_pmu_any_read, + input io_lsu_pmu_bus_busy, + input [30:0] io_dec_tlu_i0_pc_r, + input io_dec_tlu_i0_valid_r, + input io_dec_csr_any_unq_d, + output io_dec_tlu_misc_clk_override, + output io_dec_tlu_dec_clk_override, + output io_dec_tlu_ifu_clk_override, + output io_dec_tlu_lsu_clk_override, + output io_dec_tlu_bus_clk_override, + output io_dec_tlu_pic_clk_override, + output io_dec_tlu_dccm_clk_override, + output io_dec_tlu_icm_clk_override, + output [31:0] io_dec_csr_rddata_d, + output io_dec_tlu_pipelining_disable, + output io_dec_tlu_wr_pause_r, + input io_ifu_pmu_bus_busy, + input io_lsu_pmu_bus_error, + input io_ifu_pmu_bus_error, + input io_lsu_pmu_bus_misaligned, + input io_lsu_pmu_bus_trxn, + input [70:0] io_ifu_ic_debug_rd_data, + output [3:0] io_dec_tlu_meipt, + input [3:0] io_pic_pl, + output [3:0] io_dec_tlu_meicurpl, + output [29:0] io_dec_tlu_meihap, + input [7:0] io_pic_claimid, + input io_iccm_dma_sb_error, + input [31:0] io_lsu_imprecise_error_addr_any, + input io_lsu_imprecise_error_load_any, + input io_lsu_imprecise_error_store_any, + output [31:0] io_dec_tlu_mrac_ff, + output io_dec_tlu_wb_coalescing_disable, + output io_dec_tlu_bpred_disable, + output io_dec_tlu_sideeffect_posted_disable, + output io_dec_tlu_core_ecc_disable, + output io_dec_tlu_external_ldfwd_disable, + output [2:0] io_dec_tlu_dma_qos_prty, + input [31:0] io_dec_illegal_inst, + input [3:0] io_lsu_error_pkt_r_bits_mscause, + input io_mexintpend, + input [30:0] io_exu_npc_r, + input io_mpc_reset_run_req, + input [30:0] io_rst_vec, + input [27:0] io_core_id, + input [31:0] io_dec_timer_rddata_d, + input io_dec_timer_read_d, + output io_dec_csr_wen_r_mod, + input io_rfpc_i0_r, + input io_i0_trigger_hit_r, + output io_fw_halt_req, + output [1:0] io_mstatus, + input io_exc_or_int_valid_r, + input io_mret_r, + output io_mstatus_mie_ns, + input io_dcsr_single_step_running_f, + output [15:0] io_dcsr, + output [30:0] io_mtvec, + output [5:0] io_mip, + input io_dec_timer_t0_pulse, + input io_dec_timer_t1_pulse, + input io_timer_int_sync, + input io_soft_int_sync, + output [5:0] io_mie_ns, + input io_csr_wr_clk, + input io_ebreak_to_debug_mode_r, + input io_dec_tlu_pmu_fw_halted, + input [1:0] io_lsu_fir_error, + output [30:0] io_npc_r, + input io_tlu_flush_lower_r_d1, + input io_dec_tlu_flush_noredir_r_d1, + input [30:0] io_tlu_flush_path_r_d1, + output [30:0] io_npc_r_d1, + input io_reset_delayed, + output [30:0] io_mepc, + input io_interrupt_valid_r, + input io_i0_exception_valid_r, + input io_lsu_exc_valid_r, + input io_mepc_trigger_hit_sel_pc_r, + input io_e4e5_int_clk, + input io_lsu_i0_exc_r, + input io_inst_acc_r, + input io_inst_acc_second_r, + input io_take_nmi, + input [31:0] io_lsu_error_pkt_addr_r, + input [4:0] io_exc_cause_r, + input io_i0_valid_wb, + input io_exc_or_int_valid_r_d1, + input io_interrupt_valid_r_d1, + input io_clk_override, + input io_i0_exception_valid_r_d1, + input io_lsu_i0_exc_r_d1, + input [4:0] io_exc_cause_wb, + input io_nmi_lsu_store_type, + input io_nmi_lsu_load_type, + input io_tlu_i0_commit_cmt, + input io_ebreak_r, + input io_ecall_r, + input io_illegal_r, + output io_mdseac_locked_ns, + input io_mdseac_locked_f, + input io_nmi_int_detected_f, + input io_internal_dbg_halt_mode_f2, + input io_ext_int_freeze_d1, + input io_ic_perr_r_d1, + input io_iccm_sbecc_r_d1, + input io_lsu_single_ecc_error_r_d1, + input io_ifu_miss_state_idle_f, + input io_lsu_idle_any_f, + input io_dbg_tlu_halted_f, + input io_dbg_tlu_halted, + input io_debug_halt_req_f, + output io_force_halt, + input io_take_ext_int_start, + input io_trigger_hit_dmode_r_d1, + input io_trigger_hit_r_d1, + input io_dcsr_single_step_done_f, + input io_ebreak_to_debug_mode_r_d1, + input io_debug_halt_req, + input io_allow_dbg_halt_csr_write, + input io_internal_dbg_halt_mode_f, + input io_enter_debug_halt_req, + input io_internal_dbg_halt_mode, + input io_request_debug_mode_done, + input io_request_debug_mode_r, + output [30:0] io_dpc, + input [3:0] io_update_hit_bit_r, + input io_take_timer_int, + input io_take_int_timer0_int, + input io_take_int_timer1_int, + input io_take_ext_int, + input io_tlu_flush_lower_r, + input io_dec_tlu_br0_error_r, + input io_dec_tlu_br0_start_error_r, + input io_lsu_pmu_load_external_r, + input io_lsu_pmu_store_external_r, + input io_csr_pkt_csr_misa, + input io_csr_pkt_csr_mvendorid, + input io_csr_pkt_csr_marchid, + input io_csr_pkt_csr_mimpid, + input io_csr_pkt_csr_mhartid, + input io_csr_pkt_csr_mstatus, + input io_csr_pkt_csr_mtvec, + input io_csr_pkt_csr_mip, + input io_csr_pkt_csr_mie, + input io_csr_pkt_csr_mcyclel, + input io_csr_pkt_csr_mcycleh, + input io_csr_pkt_csr_minstretl, + input io_csr_pkt_csr_minstreth, + input io_csr_pkt_csr_mscratch, + input io_csr_pkt_csr_mepc, + input io_csr_pkt_csr_mcause, + input io_csr_pkt_csr_mscause, + input io_csr_pkt_csr_mtval, + input io_csr_pkt_csr_mrac, + input io_csr_pkt_csr_mdseac, + input io_csr_pkt_csr_meihap, + input io_csr_pkt_csr_meivt, + input io_csr_pkt_csr_meipt, + input io_csr_pkt_csr_meicurpl, + input io_csr_pkt_csr_meicidpl, + input io_csr_pkt_csr_dcsr, + input io_csr_pkt_csr_mcgc, + input io_csr_pkt_csr_mfdc, + input io_csr_pkt_csr_dpc, + input io_csr_pkt_csr_mtsel, + input io_csr_pkt_csr_mtdata1, + input io_csr_pkt_csr_mtdata2, + input io_csr_pkt_csr_mhpmc3, + input io_csr_pkt_csr_mhpmc4, + input io_csr_pkt_csr_mhpmc5, + input io_csr_pkt_csr_mhpmc6, + input io_csr_pkt_csr_mhpmc3h, + input io_csr_pkt_csr_mhpmc4h, + input io_csr_pkt_csr_mhpmc5h, + input io_csr_pkt_csr_mhpmc6h, + input io_csr_pkt_csr_mhpme3, + input io_csr_pkt_csr_mhpme4, + input io_csr_pkt_csr_mhpme5, + input io_csr_pkt_csr_mhpme6, + input io_csr_pkt_csr_mcountinhibit, + input io_csr_pkt_csr_mpmc, + input io_csr_pkt_csr_micect, + input io_csr_pkt_csr_miccmect, + input io_csr_pkt_csr_mdccmect, + input io_csr_pkt_csr_mfdht, + input io_csr_pkt_csr_mfdhs, + input io_csr_pkt_csr_dicawics, + input io_csr_pkt_csr_dicad0h, + input io_csr_pkt_csr_dicad0, + input io_csr_pkt_csr_dicad1, + output [9:0] io_mtdata1_t_0, + output [9:0] io_mtdata1_t_1, + output [9:0] io_mtdata1_t_2, + output [9:0] io_mtdata1_t_3 +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [63:0] _RAND_10; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; + reg [63:0] _RAND_13; + reg [31:0] _RAND_14; + reg [31:0] _RAND_15; + reg [31:0] _RAND_16; + reg [31:0] _RAND_17; + reg [31:0] _RAND_18; + reg [31:0] _RAND_19; + reg [31:0] _RAND_20; + reg [31:0] _RAND_21; + reg [31:0] _RAND_22; + reg [31:0] _RAND_23; + reg [31:0] _RAND_24; + reg [31:0] _RAND_25; + reg [31:0] _RAND_26; + reg [31:0] _RAND_27; + reg [31:0] _RAND_28; + reg [31:0] _RAND_29; + reg [31:0] _RAND_30; + reg [31:0] _RAND_31; + reg [31:0] _RAND_32; + reg [31:0] _RAND_33; + reg [31:0] _RAND_34; + reg [31:0] _RAND_35; + reg [31:0] _RAND_36; + reg [31:0] _RAND_37; + reg [31:0] _RAND_38; + reg [95:0] _RAND_39; + reg [31:0] _RAND_40; + reg [31:0] _RAND_41; + reg [31:0] _RAND_42; + reg [31:0] _RAND_43; + reg [31:0] _RAND_44; + reg [31:0] _RAND_45; + reg [31:0] _RAND_46; + reg [31:0] _RAND_47; + reg [31:0] _RAND_48; + reg [31:0] _RAND_49; + reg [31:0] _RAND_50; + reg [31:0] _RAND_51; + reg [31:0] _RAND_52; + reg [31:0] _RAND_53; + reg [31:0] _RAND_54; + reg [31:0] _RAND_55; + reg [31:0] _RAND_56; + reg [31:0] _RAND_57; + reg [31:0] _RAND_58; + reg [31:0] _RAND_59; + reg [31:0] _RAND_60; + reg [31:0] _RAND_61; + reg [31:0] _RAND_62; + reg [31:0] _RAND_63; + reg [31:0] _RAND_64; + reg [31:0] _RAND_65; + reg [31:0] _RAND_66; + reg [31:0] _RAND_67; + reg [31:0] _RAND_68; + reg [31:0] _RAND_69; + reg [31:0] _RAND_70; + reg [31:0] _RAND_71; + reg [31:0] _RAND_72; + reg [31:0] _RAND_73; +`endif // RANDOMIZE_REG_INIT + wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_2_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_2_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_4_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_4_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_5_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_5_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_6_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_6_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_6_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_6_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_7_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_7_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_7_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_7_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_8_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_8_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_8_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_8_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_9_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_9_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_9_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_10_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_10_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_10_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_10_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_11_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_11_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_11_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_11_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_12_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_12_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_12_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_12_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_13_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_13_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_13_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_13_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_14_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_14_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_14_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_14_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_15_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_15_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_15_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_15_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_16_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_16_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_16_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_16_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_17_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_17_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_17_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_17_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_18_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_18_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_18_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_18_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_19_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_19_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_19_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_19_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_20_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_20_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_20_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_20_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_21_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_21_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_21_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_21_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_22_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_22_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_22_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_22_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_23_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_23_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_23_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_23_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_24_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_24_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_24_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_24_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_25_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_25_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_25_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_25_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_26_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_26_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_26_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_26_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_27_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_27_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_27_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_27_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_28_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_28_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_28_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_28_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_29_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_29_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_29_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_29_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_30_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_30_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_30_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_30_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_31_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_31_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_31_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_31_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_32_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_32_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_32_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_32_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_33_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_33_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_33_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_33_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_34_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_34_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_34_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_34_io_scan_mode; // @[el2_lib.scala 483:22] + wire _T = ~io_i0_trigger_hit_r; // @[el2_dec_tlu_ctl.scala 1530:46] + wire _T_1 = io_dec_csr_wen_r & _T; // @[el2_dec_tlu_ctl.scala 1530:44] + wire _T_2 = ~io_rfpc_i0_r; // @[el2_dec_tlu_ctl.scala 1530:69] + wire _T_5 = io_dec_csr_wraddr_r == 12'h300; // @[el2_dec_tlu_ctl.scala 1531:72] + wire wr_mstatus_r = io_dec_csr_wen_r_mod & _T_5; // @[el2_dec_tlu_ctl.scala 1531:43] + wire _T_496 = io_dec_csr_wraddr_r == 12'h7c6; // @[el2_dec_tlu_ctl.scala 1917:69] + wire wr_mpmc_r = io_dec_csr_wen_r_mod & _T_496; // @[el2_dec_tlu_ctl.scala 1917:40] + wire _T_507 = ~io_dec_csr_wrdata_r[1]; // @[el2_dec_tlu_ctl.scala 1924:38] + reg mpmc_b; // @[el2_dec_tlu_ctl.scala 1926:45] + wire mpmc = ~mpmc_b; // @[el2_dec_tlu_ctl.scala 1929:11] + wire _T_508 = ~mpmc; // @[el2_dec_tlu_ctl.scala 1924:63] + wire mpmc_b_ns = wr_mpmc_r ? _T_507 : _T_508; // @[el2_dec_tlu_ctl.scala 1924:19] + wire _T_6 = ~mpmc_b_ns; // @[el2_dec_tlu_ctl.scala 1534:29] + wire set_mie_pmu_fw_halt = _T_6 & io_fw_halt_req; // @[el2_dec_tlu_ctl.scala 1534:40] + wire _T_7 = ~wr_mstatus_r; // @[el2_dec_tlu_ctl.scala 1537:6] + wire _T_8 = _T_7 & io_exc_or_int_valid_r; // @[el2_dec_tlu_ctl.scala 1537:20] + wire _T_12 = wr_mstatus_r & io_exc_or_int_valid_r; // @[el2_dec_tlu_ctl.scala 1538:19] + wire _T_15 = ~io_exc_or_int_valid_r; // @[el2_dec_tlu_ctl.scala 1539:18] + wire _T_16 = io_mret_r & _T_15; // @[el2_dec_tlu_ctl.scala 1539:16] + wire [1:0] _T_19 = {1'h1,io_mstatus[1]}; // @[Cat.scala 29:58] + wire [1:0] _T_22 = {io_mstatus[1],1'h1}; // @[Cat.scala 29:58] + wire _T_24 = wr_mstatus_r & _T_15; // @[el2_dec_tlu_ctl.scala 1541:19] + wire [1:0] _T_28 = {io_dec_csr_wrdata_r[7],io_dec_csr_wrdata_r[3]}; // @[Cat.scala 29:58] + wire _T_31 = _T_7 & _T_15; // @[el2_dec_tlu_ctl.scala 1542:20] + wire _T_32 = ~io_mret_r; // @[el2_dec_tlu_ctl.scala 1542:47] + wire _T_33 = _T_31 & _T_32; // @[el2_dec_tlu_ctl.scala 1542:45] + wire _T_34 = ~set_mie_pmu_fw_halt; // @[el2_dec_tlu_ctl.scala 1542:60] + wire _T_35 = _T_33 & _T_34; // @[el2_dec_tlu_ctl.scala 1542:58] + wire _T_37 = _T_8 & io_mstatus[0]; // @[Mux.scala 27:72] + wire _T_38 = _T_12 & io_dec_csr_wrdata_r[3]; // @[Mux.scala 27:72] + wire [1:0] _T_39 = _T_16 ? _T_19 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_40 = set_mie_pmu_fw_halt ? _T_22 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_41 = _T_24 ? _T_28 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_42 = _T_35 ? io_mstatus : 2'h0; // @[Mux.scala 27:72] + wire _T_43 = _T_37 | _T_38; // @[Mux.scala 27:72] + wire [1:0] _GEN_9 = {{1'd0}, _T_43}; // @[Mux.scala 27:72] + wire [1:0] _T_44 = _GEN_9 | _T_39; // @[Mux.scala 27:72] + wire [1:0] _T_45 = _T_44 | _T_40; // @[Mux.scala 27:72] + wire [1:0] _T_46 = _T_45 | _T_41; // @[Mux.scala 27:72] + wire _T_50 = ~io_dcsr_single_step_running_f; // @[el2_dec_tlu_ctl.scala 1545:51] + wire _T_52 = _T_50 | io_dcsr[11]; // @[el2_dec_tlu_ctl.scala 1545:82] + reg [1:0] _T_54; // @[el2_dec_tlu_ctl.scala 1547:12] + wire _T_56 = io_dec_csr_wraddr_r == 12'h305; // @[el2_dec_tlu_ctl.scala 1556:70] + reg [30:0] _T_60; // @[el2_lib.scala 514:16] + reg [31:0] mdccmect; // @[el2_lib.scala 514:16] + wire [62:0] _T_572 = 63'hffffffff << mdccmect[31:27]; // @[el2_dec_tlu_ctl.scala 1975:42] + wire [31:0] _T_574 = {5'h0,mdccmect[26:0]}; // @[Cat.scala 29:58] + wire [62:0] _GEN_10 = {{31'd0}, _T_574}; // @[el2_dec_tlu_ctl.scala 1975:62] + wire [62:0] _T_575 = _T_572 & _GEN_10; // @[el2_dec_tlu_ctl.scala 1975:62] + wire mdccme_ce_req = |_T_575; // @[el2_dec_tlu_ctl.scala 1975:95] + reg [31:0] miccmect; // @[el2_lib.scala 514:16] + wire [62:0] _T_552 = 63'hffffffff << miccmect[31:27]; // @[el2_dec_tlu_ctl.scala 1960:42] + wire [31:0] _T_554 = {5'h0,miccmect[26:0]}; // @[Cat.scala 29:58] + wire [62:0] _GEN_11 = {{31'd0}, _T_554}; // @[el2_dec_tlu_ctl.scala 1960:62] + wire [62:0] _T_555 = _T_552 & _GEN_11; // @[el2_dec_tlu_ctl.scala 1960:62] + wire miccme_ce_req = |_T_555; // @[el2_dec_tlu_ctl.scala 1960:95] + wire _T_61 = mdccme_ce_req | miccme_ce_req; // @[el2_dec_tlu_ctl.scala 1570:31] + reg [31:0] micect; // @[el2_lib.scala 514:16] + wire [62:0] _T_530 = 63'hffffffff << micect[31:27]; // @[el2_dec_tlu_ctl.scala 1946:39] + wire _T_531 = |_T_530; // @[el2_dec_tlu_ctl.scala 1946:57] + wire [31:0] _T_533 = {5'h0,micect[26:0]}; // @[Cat.scala 29:58] + wire [31:0] _GEN_12 = {{31'd0}, _T_531}; // @[el2_dec_tlu_ctl.scala 1946:61] + wire [31:0] _T_534 = _GEN_12 & _T_533; // @[el2_dec_tlu_ctl.scala 1946:61] + wire mice_ce_req = _T_534[0]; // @[el2_dec_tlu_ctl.scala 1946:15] + wire ce_int = _T_61 | mice_ce_req; // @[el2_dec_tlu_ctl.scala 1570:47] + wire [2:0] _T_63 = {io_mexintpend,io_timer_int_sync,io_soft_int_sync}; // @[Cat.scala 29:58] + wire [2:0] _T_65 = {ce_int,io_dec_timer_t0_pulse,io_dec_timer_t1_pulse}; // @[Cat.scala 29:58] + reg [5:0] _T_66; // @[el2_dec_tlu_ctl.scala 1574:12] + wire _T_68 = io_dec_csr_wraddr_r == 12'h304; // @[el2_dec_tlu_ctl.scala 1586:68] + wire wr_mie_r = io_dec_csr_wen_r_mod & _T_68; // @[el2_dec_tlu_ctl.scala 1586:39] + wire [5:0] _T_76 = {io_dec_csr_wrdata_r[30:28],io_dec_csr_wrdata_r[11],io_dec_csr_wrdata_r[7],io_dec_csr_wrdata_r[3]}; // @[Cat.scala 29:58] + reg [5:0] mie; // @[el2_dec_tlu_ctl.scala 1589:12] + wire kill_ebreak_count_r = io_ebreak_to_debug_mode_r & io_dcsr[10]; // @[el2_dec_tlu_ctl.scala 1596:55] + wire _T_81 = io_dec_csr_wraddr_r == 12'hb00; // @[el2_dec_tlu_ctl.scala 1598:72] + wire wr_mcyclel_r = io_dec_csr_wen_r_mod & _T_81; // @[el2_dec_tlu_ctl.scala 1598:43] + wire _T_83 = io_dec_tlu_dbg_halted & io_dcsr[10]; // @[el2_dec_tlu_ctl.scala 1600:72] + wire _T_84 = kill_ebreak_count_r | _T_83; // @[el2_dec_tlu_ctl.scala 1600:47] + wire _T_85 = _T_84 | io_dec_tlu_pmu_fw_halted; // @[el2_dec_tlu_ctl.scala 1600:95] + reg [4:0] temp_ncount6_2; // @[Reg.scala 27:20] + reg temp_ncount0; // @[Reg.scala 27:20] + wire [6:0] mcountinhibit = {temp_ncount6_2,1'h0,temp_ncount0}; // @[Cat.scala 29:58] + wire _T_87 = _T_85 | mcountinhibit[0]; // @[el2_dec_tlu_ctl.scala 1600:122] + wire mcyclel_cout_in = ~_T_87; // @[el2_dec_tlu_ctl.scala 1600:25] + wire [31:0] _T_88 = {31'h0,mcyclel_cout_in}; // @[Cat.scala 29:58] + reg [32:0] _T_95; // @[el2_lib.scala 514:16] + wire [31:0] mcyclel = _T_95[31:0]; // @[el2_dec_tlu_ctl.scala 1607:11] + wire [31:0] _T_90 = mcyclel + _T_88; // @[el2_dec_tlu_ctl.scala 1604:26] + wire [32:0] mcyclel_inc = {{1'd0}, _T_90}; // @[el2_dec_tlu_ctl.scala 1604:15] + wire mcyclel_cout = mcyclel_inc[32]; // @[el2_dec_tlu_ctl.scala 1606:33] + wire _T_99 = io_dec_csr_wraddr_r == 12'hb80; // @[el2_dec_tlu_ctl.scala 1614:69] + wire wr_mcycleh_r = io_dec_csr_wen_r_mod & _T_99; // @[el2_dec_tlu_ctl.scala 1614:40] + wire _T_96 = ~wr_mcycleh_r; // @[el2_dec_tlu_ctl.scala 1608:72] + reg mcyclel_cout_f; // @[el2_dec_tlu_ctl.scala 1608:55] + wire [31:0] _T_101 = {31'h0,mcyclel_cout_f}; // @[Cat.scala 29:58] + reg [31:0] mcycleh; // @[el2_lib.scala 514:16] + wire [31:0] mcycleh_inc = mcycleh + _T_101; // @[el2_dec_tlu_ctl.scala 1616:29] + wire _T_107 = io_ebreak_r | io_ecall_r; // @[el2_dec_tlu_ctl.scala 1633:73] + wire _T_108 = _T_107 | io_ebreak_to_debug_mode_r; // @[el2_dec_tlu_ctl.scala 1633:86] + wire _T_109 = _T_108 | io_illegal_r; // @[el2_dec_tlu_ctl.scala 1633:114] + wire _T_111 = _T_109 | mcountinhibit[2]; // @[el2_dec_tlu_ctl.scala 1633:129] + wire _T_113 = ~_T_111; // @[el2_dec_tlu_ctl.scala 1633:59] + wire i0_valid_no_ebreak_ecall_r = io_tlu_i0_commit_cmt & _T_113; // @[el2_dec_tlu_ctl.scala 1633:57] + wire _T_115 = io_dec_csr_wraddr_r == 12'hb02; // @[el2_dec_tlu_ctl.scala 1635:74] + wire wr_minstretl_r = io_dec_csr_wen_r_mod & _T_115; // @[el2_dec_tlu_ctl.scala 1635:45] + wire [31:0] _T_116 = {31'h0,i0_valid_no_ebreak_ecall_r}; // @[Cat.scala 29:58] + reg [32:0] _T_122; // @[el2_lib.scala 514:16] + wire [31:0] minstretl = _T_122[31:0]; // @[el2_dec_tlu_ctl.scala 1642:13] + wire [31:0] _T_118 = minstretl + _T_116; // @[el2_dec_tlu_ctl.scala 1637:30] + wire [32:0] minstretl_inc = {{1'd0}, _T_118}; // @[el2_dec_tlu_ctl.scala 1637:17] + wire minstretl_cout = minstretl_inc[32]; // @[el2_dec_tlu_ctl.scala 1638:37] + reg minstret_enable_f; // @[el2_dec_tlu_ctl.scala 1643:57] + wire _T_126 = io_dec_csr_wraddr_r == 12'hb82; // @[el2_dec_tlu_ctl.scala 1652:72] + wire wr_minstreth_r = io_dec_csr_wen_r_mod & _T_126; // @[el2_dec_tlu_ctl.scala 1652:43] + wire _T_123 = ~wr_minstreth_r; // @[el2_dec_tlu_ctl.scala 1644:76] + reg minstretl_cout_f; // @[el2_dec_tlu_ctl.scala 1644:57] + wire [31:0] _T_129 = {31'h0,minstretl_cout_f}; // @[Cat.scala 29:58] + reg [31:0] minstreth; // @[el2_lib.scala 514:16] + wire [31:0] minstreth_inc = minstreth + _T_129; // @[el2_dec_tlu_ctl.scala 1655:30] + wire _T_137 = io_dec_csr_wraddr_r == 12'h340; // @[el2_dec_tlu_ctl.scala 1666:73] + reg [31:0] mscratch; // @[el2_lib.scala 514:16] + wire _T_140 = ~io_dec_tlu_dbg_halted; // @[el2_dec_tlu_ctl.scala 1677:23] + wire _T_141 = ~io_tlu_flush_lower_r_d1; // @[el2_dec_tlu_ctl.scala 1677:48] + wire _T_142 = _T_140 & _T_141; // @[el2_dec_tlu_ctl.scala 1677:46] + wire sel_exu_npc_r = _T_142 & io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 1677:73] + wire _T_144 = _T_140 & io_tlu_flush_lower_r_d1; // @[el2_dec_tlu_ctl.scala 1678:48] + wire _T_145 = ~io_dec_tlu_flush_noredir_r_d1; // @[el2_dec_tlu_ctl.scala 1678:76] + wire sel_flush_npc_r = _T_144 & _T_145; // @[el2_dec_tlu_ctl.scala 1678:74] + wire _T_146 = ~sel_exu_npc_r; // @[el2_dec_tlu_ctl.scala 1679:24] + wire _T_147 = ~sel_flush_npc_r; // @[el2_dec_tlu_ctl.scala 1679:41] + wire sel_hold_npc_r = _T_146 & _T_147; // @[el2_dec_tlu_ctl.scala 1679:39] + wire _T_149 = ~io_mpc_reset_run_req; // @[el2_dec_tlu_ctl.scala 1683:6] + wire _T_150 = _T_149 & io_reset_delayed; // @[el2_dec_tlu_ctl.scala 1683:28] + wire [30:0] _T_154 = sel_exu_npc_r ? io_exu_npc_r : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_155 = _T_150 ? io_rst_vec : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_156 = sel_flush_npc_r ? io_tlu_flush_path_r_d1 : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_157 = sel_hold_npc_r ? io_npc_r_d1 : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_158 = _T_154 | _T_155; // @[Mux.scala 27:72] + wire [30:0] _T_159 = _T_158 | _T_156; // @[Mux.scala 27:72] + wire _T_162 = sel_exu_npc_r | sel_flush_npc_r; // @[el2_dec_tlu_ctl.scala 1687:49] + reg [30:0] _T_165; // @[el2_lib.scala 514:16] + wire pc0_valid_r = _T_140 & io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 1690:45] + wire _T_168 = ~pc0_valid_r; // @[el2_dec_tlu_ctl.scala 1694:5] + wire [30:0] _T_169 = pc0_valid_r ? io_dec_tlu_i0_pc_r : 31'h0; // @[Mux.scala 27:72] + reg [30:0] pc_r_d1; // @[el2_lib.scala 514:16] + wire [30:0] _T_170 = _T_168 ? pc_r_d1 : 31'h0; // @[Mux.scala 27:72] + wire [30:0] pc_r = _T_169 | _T_170; // @[Mux.scala 27:72] + wire _T_174 = io_dec_csr_wraddr_r == 12'h341; // @[el2_dec_tlu_ctl.scala 1698:69] + wire wr_mepc_r = io_dec_csr_wen_r_mod & _T_174; // @[el2_dec_tlu_ctl.scala 1698:40] + wire _T_175 = io_i0_exception_valid_r | io_lsu_exc_valid_r; // @[el2_dec_tlu_ctl.scala 1701:30] + wire _T_176 = _T_175 | io_mepc_trigger_hit_sel_pc_r; // @[el2_dec_tlu_ctl.scala 1701:51] + wire _T_180 = wr_mepc_r & _T_15; // @[el2_dec_tlu_ctl.scala 1703:16] + wire _T_183 = ~wr_mepc_r; // @[el2_dec_tlu_ctl.scala 1704:6] + wire _T_185 = _T_183 & _T_15; // @[el2_dec_tlu_ctl.scala 1704:17] + wire [30:0] _T_187 = _T_176 ? pc_r : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_188 = io_interrupt_valid_r ? io_npc_r : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_189 = _T_180 ? io_dec_csr_wrdata_r[31:1] : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_190 = _T_185 ? io_mepc : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_191 = _T_187 | _T_188; // @[Mux.scala 27:72] + wire [30:0] _T_192 = _T_191 | _T_189; // @[Mux.scala 27:72] + reg [30:0] _T_194; // @[el2_dec_tlu_ctl.scala 1706:48] + wire _T_196 = io_dec_csr_wraddr_r == 12'h342; // @[el2_dec_tlu_ctl.scala 1713:71] + wire wr_mcause_r = io_dec_csr_wen_r_mod & _T_196; // @[el2_dec_tlu_ctl.scala 1713:42] + wire _T_197 = io_exc_or_int_valid_r & io_take_nmi; // @[el2_dec_tlu_ctl.scala 1714:52] + wire mcause_sel_nmi_store = _T_197 & io_nmi_lsu_store_type; // @[el2_dec_tlu_ctl.scala 1714:66] + wire mcause_sel_nmi_load = _T_197 & io_nmi_lsu_load_type; // @[el2_dec_tlu_ctl.scala 1715:65] + wire _T_200 = |io_lsu_fir_error; // @[el2_dec_tlu_ctl.scala 1716:83] + wire mcause_sel_nmi_ext = _T_197 & _T_200; // @[el2_dec_tlu_ctl.scala 1716:64] + wire _T_201 = &io_lsu_fir_error; // @[el2_dec_tlu_ctl.scala 1722:52] + wire _T_204 = ~io_lsu_fir_error[0]; // @[el2_dec_tlu_ctl.scala 1722:81] + wire _T_205 = io_lsu_fir_error[1] & _T_204; // @[el2_dec_tlu_ctl.scala 1722:79] + wire [31:0] _T_210 = {30'h3c000400,_T_201,_T_205}; // @[Cat.scala 29:58] + wire _T_211 = ~io_take_nmi; // @[el2_dec_tlu_ctl.scala 1728:30] + wire _T_212 = io_exc_or_int_valid_r & _T_211; // @[el2_dec_tlu_ctl.scala 1728:28] + wire [31:0] _T_215 = {io_interrupt_valid_r,26'h0,io_exc_cause_r}; // @[Cat.scala 29:58] + wire _T_217 = wr_mcause_r & _T_15; // @[el2_dec_tlu_ctl.scala 1729:18] + wire _T_219 = ~wr_mcause_r; // @[el2_dec_tlu_ctl.scala 1730:6] + wire _T_221 = _T_219 & _T_15; // @[el2_dec_tlu_ctl.scala 1730:19] + wire [31:0] _T_223 = mcause_sel_nmi_store ? 32'hf0000000 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_224 = mcause_sel_nmi_load ? 32'hf0000001 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_225 = mcause_sel_nmi_ext ? _T_210 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_226 = _T_212 ? _T_215 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_227 = _T_217 ? io_dec_csr_wrdata_r : 32'h0; // @[Mux.scala 27:72] + reg [31:0] mcause; // @[el2_dec_tlu_ctl.scala 1732:47] + wire [31:0] _T_228 = _T_221 ? mcause : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_229 = _T_223 | _T_224; // @[Mux.scala 27:72] + wire [31:0] _T_230 = _T_229 | _T_225; // @[Mux.scala 27:72] + wire [31:0] _T_231 = _T_230 | _T_226; // @[Mux.scala 27:72] + wire [31:0] _T_232 = _T_231 | _T_227; // @[Mux.scala 27:72] + wire _T_236 = io_dec_csr_wraddr_r == 12'h7ff; // @[el2_dec_tlu_ctl.scala 1739:72] + wire wr_mscause_r = io_dec_csr_wen_r_mod & _T_236; // @[el2_dec_tlu_ctl.scala 1739:43] + wire _T_237 = io_dec_tlu_packet_r_icaf_type == 2'h0; // @[el2_dec_tlu_ctl.scala 1741:57] + wire [3:0] _T_238 = {2'h0,io_dec_tlu_packet_r_icaf_type}; // @[Cat.scala 29:58] + wire [3:0] ifu_mscause = _T_237 ? 4'h9 : _T_238; // @[el2_dec_tlu_ctl.scala 1741:25] + wire [3:0] _T_243 = io_lsu_i0_exc_r ? io_lsu_error_pkt_r_bits_mscause : 4'h0; // @[Mux.scala 27:72] + wire [1:0] _T_245 = io_ebreak_r ? 2'h2 : 2'h0; // @[Mux.scala 27:72] + wire [3:0] _T_246 = io_inst_acc_r ? ifu_mscause : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _GEN_13 = {{3'd0}, io_i0_trigger_hit_r}; // @[Mux.scala 27:72] + wire [3:0] _T_247 = _T_243 | _GEN_13; // @[Mux.scala 27:72] + wire [3:0] _GEN_14 = {{2'd0}, _T_245}; // @[Mux.scala 27:72] + wire [3:0] _T_248 = _T_247 | _GEN_14; // @[Mux.scala 27:72] + wire [3:0] mscause_type = _T_248 | _T_246; // @[Mux.scala 27:72] + wire _T_252 = wr_mscause_r & _T_15; // @[el2_dec_tlu_ctl.scala 1752:19] + wire _T_255 = ~wr_mscause_r; // @[el2_dec_tlu_ctl.scala 1753:6] + wire _T_257 = _T_255 & _T_15; // @[el2_dec_tlu_ctl.scala 1753:20] + wire [3:0] _T_259 = io_exc_or_int_valid_r ? mscause_type : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_260 = _T_252 ? io_dec_csr_wrdata_r[3:0] : 4'h0; // @[Mux.scala 27:72] + reg [3:0] mscause; // @[el2_dec_tlu_ctl.scala 1755:48] + wire [3:0] _T_261 = _T_257 ? mscause : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_262 = _T_259 | _T_260; // @[Mux.scala 27:72] + wire _T_266 = io_dec_csr_wraddr_r == 12'h343; // @[el2_dec_tlu_ctl.scala 1762:70] + wire wr_mtval_r = io_dec_csr_wen_r_mod & _T_266; // @[el2_dec_tlu_ctl.scala 1762:41] + wire _T_267 = ~io_inst_acc_second_r; // @[el2_dec_tlu_ctl.scala 1763:84] + wire _T_268 = io_inst_acc_r & _T_267; // @[el2_dec_tlu_ctl.scala 1763:82] + wire _T_269 = io_ebreak_r | _T_268; // @[el2_dec_tlu_ctl.scala 1763:65] + wire _T_270 = _T_269 | io_mepc_trigger_hit_sel_pc_r; // @[el2_dec_tlu_ctl.scala 1763:107] + wire _T_271 = io_exc_or_int_valid_r & _T_270; // @[el2_dec_tlu_ctl.scala 1763:50] + wire mtval_capture_pc_r = _T_271 & _T_211; // @[el2_dec_tlu_ctl.scala 1763:139] + wire _T_273 = io_inst_acc_r & io_inst_acc_second_r; // @[el2_dec_tlu_ctl.scala 1764:73] + wire _T_274 = io_exc_or_int_valid_r & _T_273; // @[el2_dec_tlu_ctl.scala 1764:56] + wire mtval_capture_pc_plus2_r = _T_274 & _T_211; // @[el2_dec_tlu_ctl.scala 1764:97] + wire _T_276 = io_exc_or_int_valid_r & io_illegal_r; // @[el2_dec_tlu_ctl.scala 1765:52] + wire mtval_capture_inst_r = _T_276 & _T_211; // @[el2_dec_tlu_ctl.scala 1765:67] + wire _T_278 = io_exc_or_int_valid_r & io_lsu_exc_valid_r; // @[el2_dec_tlu_ctl.scala 1766:51] + wire mtval_capture_lsu_r = _T_278 & _T_211; // @[el2_dec_tlu_ctl.scala 1766:72] + wire _T_280 = ~mtval_capture_pc_r; // @[el2_dec_tlu_ctl.scala 1767:47] + wire _T_281 = io_exc_or_int_valid_r & _T_280; // @[el2_dec_tlu_ctl.scala 1767:45] + wire _T_282 = ~mtval_capture_inst_r; // @[el2_dec_tlu_ctl.scala 1767:69] + wire _T_283 = _T_281 & _T_282; // @[el2_dec_tlu_ctl.scala 1767:67] + wire _T_284 = ~mtval_capture_lsu_r; // @[el2_dec_tlu_ctl.scala 1767:93] + wire _T_285 = _T_283 & _T_284; // @[el2_dec_tlu_ctl.scala 1767:91] + wire _T_286 = ~io_mepc_trigger_hit_sel_pc_r; // @[el2_dec_tlu_ctl.scala 1767:116] + wire mtval_clear_r = _T_285 & _T_286; // @[el2_dec_tlu_ctl.scala 1767:114] + wire [31:0] _T_288 = {pc_r,1'h0}; // @[Cat.scala 29:58] + wire [30:0] _T_291 = pc_r + 31'h1; // @[el2_dec_tlu_ctl.scala 1772:84] + wire [31:0] _T_292 = {_T_291,1'h0}; // @[Cat.scala 29:58] + wire _T_295 = ~io_interrupt_valid_r; // @[el2_dec_tlu_ctl.scala 1775:19] + wire _T_296 = wr_mtval_r & _T_295; // @[el2_dec_tlu_ctl.scala 1775:17] + wire _T_299 = ~wr_mtval_r; // @[el2_dec_tlu_ctl.scala 1776:21] + wire _T_300 = _T_211 & _T_299; // @[el2_dec_tlu_ctl.scala 1776:19] + wire _T_302 = _T_300 & _T_280; // @[el2_dec_tlu_ctl.scala 1776:33] + wire _T_304 = _T_302 & _T_282; // @[el2_dec_tlu_ctl.scala 1776:55] + wire _T_305 = ~mtval_clear_r; // @[el2_dec_tlu_ctl.scala 1776:81] + wire _T_306 = _T_304 & _T_305; // @[el2_dec_tlu_ctl.scala 1776:79] + wire _T_308 = _T_306 & _T_284; // @[el2_dec_tlu_ctl.scala 1776:96] + wire [31:0] _T_310 = mtval_capture_pc_r ? _T_288 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_311 = mtval_capture_pc_plus2_r ? _T_292 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_312 = mtval_capture_inst_r ? io_dec_illegal_inst : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_313 = mtval_capture_lsu_r ? io_lsu_error_pkt_addr_r : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_314 = _T_296 ? io_dec_csr_wrdata_r : 32'h0; // @[Mux.scala 27:72] + reg [31:0] mtval; // @[el2_dec_tlu_ctl.scala 1778:47] + wire [31:0] _T_315 = _T_308 ? mtval : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_316 = _T_310 | _T_311; // @[Mux.scala 27:72] + wire [31:0] _T_317 = _T_316 | _T_312; // @[Mux.scala 27:72] + wire [31:0] _T_318 = _T_317 | _T_313; // @[Mux.scala 27:72] + wire [31:0] _T_319 = _T_318 | _T_314; // @[Mux.scala 27:72] + wire _T_323 = io_dec_csr_wraddr_r == 12'h7f8; // @[el2_dec_tlu_ctl.scala 1793:69] + reg [8:0] mcgc; // @[el2_lib.scala 514:16] + wire _T_335 = io_dec_csr_wraddr_r == 12'h7f9; // @[el2_dec_tlu_ctl.scala 1823:69] + reg [14:0] mfdc_int; // @[el2_lib.scala 514:16] + wire [2:0] _T_339 = ~io_dec_csr_wrdata_r[18:16]; // @[el2_dec_tlu_ctl.scala 1832:20] + wire _T_342 = ~io_dec_csr_wrdata_r[6]; // @[el2_dec_tlu_ctl.scala 1832:75] + wire [6:0] _T_344 = {_T_342,io_dec_csr_wrdata_r[5:0]}; // @[Cat.scala 29:58] + wire [7:0] _T_345 = {_T_339,io_dec_csr_wrdata_r[11:7]}; // @[Cat.scala 29:58] + wire [2:0] _T_348 = ~mfdc_int[14:12]; // @[el2_dec_tlu_ctl.scala 1833:20] + wire _T_351 = ~mfdc_int[6]; // @[el2_dec_tlu_ctl.scala 1833:63] + wire [18:0] mfdc = {_T_348,4'h0,mfdc_int[11:7],_T_351,mfdc_int[5:0]}; // @[Cat.scala 29:58] + wire _T_365 = io_dec_csr_wraddr_r == 12'h7c2; // @[el2_dec_tlu_ctl.scala 1856:78] + wire _T_366 = io_dec_csr_wen_r_mod & _T_365; // @[el2_dec_tlu_ctl.scala 1856:49] + wire _T_368 = _T_366 & _T_295; // @[el2_dec_tlu_ctl.scala 1856:88] + wire _T_369 = ~io_take_ext_int_start; // @[el2_dec_tlu_ctl.scala 1856:114] + wire _T_372 = io_dec_csr_wraddr_r == 12'h7c0; // @[el2_dec_tlu_ctl.scala 1863:69] + wire _T_376 = ~io_dec_csr_wrdata_r[31]; // @[el2_dec_tlu_ctl.scala 1866:72] + wire _T_377 = io_dec_csr_wrdata_r[30] & _T_376; // @[el2_dec_tlu_ctl.scala 1866:70] + wire _T_381 = ~io_dec_csr_wrdata_r[29]; // @[el2_dec_tlu_ctl.scala 1867:56] + wire _T_382 = io_dec_csr_wrdata_r[28] & _T_381; // @[el2_dec_tlu_ctl.scala 1867:54] + wire _T_386 = ~io_dec_csr_wrdata_r[27]; // @[el2_dec_tlu_ctl.scala 1868:56] + wire _T_387 = io_dec_csr_wrdata_r[26] & _T_386; // @[el2_dec_tlu_ctl.scala 1868:54] + wire _T_391 = ~io_dec_csr_wrdata_r[25]; // @[el2_dec_tlu_ctl.scala 1869:56] + wire _T_392 = io_dec_csr_wrdata_r[24] & _T_391; // @[el2_dec_tlu_ctl.scala 1869:54] + wire _T_396 = ~io_dec_csr_wrdata_r[23]; // @[el2_dec_tlu_ctl.scala 1870:56] + wire _T_397 = io_dec_csr_wrdata_r[22] & _T_396; // @[el2_dec_tlu_ctl.scala 1870:54] + wire _T_401 = ~io_dec_csr_wrdata_r[21]; // @[el2_dec_tlu_ctl.scala 1871:56] + wire _T_402 = io_dec_csr_wrdata_r[20] & _T_401; // @[el2_dec_tlu_ctl.scala 1871:54] + wire _T_406 = ~io_dec_csr_wrdata_r[19]; // @[el2_dec_tlu_ctl.scala 1872:56] + wire _T_407 = io_dec_csr_wrdata_r[18] & _T_406; // @[el2_dec_tlu_ctl.scala 1872:54] + wire _T_411 = ~io_dec_csr_wrdata_r[17]; // @[el2_dec_tlu_ctl.scala 1873:56] + wire _T_412 = io_dec_csr_wrdata_r[16] & _T_411; // @[el2_dec_tlu_ctl.scala 1873:54] + wire _T_416 = ~io_dec_csr_wrdata_r[15]; // @[el2_dec_tlu_ctl.scala 1874:56] + wire _T_417 = io_dec_csr_wrdata_r[14] & _T_416; // @[el2_dec_tlu_ctl.scala 1874:54] + wire _T_421 = ~io_dec_csr_wrdata_r[13]; // @[el2_dec_tlu_ctl.scala 1875:56] + wire _T_422 = io_dec_csr_wrdata_r[12] & _T_421; // @[el2_dec_tlu_ctl.scala 1875:54] + wire _T_426 = ~io_dec_csr_wrdata_r[11]; // @[el2_dec_tlu_ctl.scala 1876:56] + wire _T_427 = io_dec_csr_wrdata_r[10] & _T_426; // @[el2_dec_tlu_ctl.scala 1876:54] + wire _T_431 = ~io_dec_csr_wrdata_r[9]; // @[el2_dec_tlu_ctl.scala 1877:56] + wire _T_432 = io_dec_csr_wrdata_r[8] & _T_431; // @[el2_dec_tlu_ctl.scala 1877:53] + wire _T_436 = ~io_dec_csr_wrdata_r[7]; // @[el2_dec_tlu_ctl.scala 1878:56] + wire _T_437 = io_dec_csr_wrdata_r[6] & _T_436; // @[el2_dec_tlu_ctl.scala 1878:53] + wire _T_441 = ~io_dec_csr_wrdata_r[5]; // @[el2_dec_tlu_ctl.scala 1879:56] + wire _T_442 = io_dec_csr_wrdata_r[4] & _T_441; // @[el2_dec_tlu_ctl.scala 1879:53] + wire _T_446 = ~io_dec_csr_wrdata_r[3]; // @[el2_dec_tlu_ctl.scala 1880:56] + wire _T_447 = io_dec_csr_wrdata_r[2] & _T_446; // @[el2_dec_tlu_ctl.scala 1880:53] + wire _T_452 = io_dec_csr_wrdata_r[0] & _T_507; // @[el2_dec_tlu_ctl.scala 1881:53] + wire [7:0] _T_459 = {io_dec_csr_wrdata_r[7],_T_437,io_dec_csr_wrdata_r[5],_T_442,io_dec_csr_wrdata_r[3],_T_447,io_dec_csr_wrdata_r[1],_T_452}; // @[Cat.scala 29:58] + wire [15:0] _T_467 = {io_dec_csr_wrdata_r[15],_T_417,io_dec_csr_wrdata_r[13],_T_422,io_dec_csr_wrdata_r[11],_T_427,io_dec_csr_wrdata_r[9],_T_432,_T_459}; // @[Cat.scala 29:58] + wire [7:0] _T_474 = {io_dec_csr_wrdata_r[23],_T_397,io_dec_csr_wrdata_r[21],_T_402,io_dec_csr_wrdata_r[19],_T_407,io_dec_csr_wrdata_r[17],_T_412}; // @[Cat.scala 29:58] + wire [15:0] _T_482 = {io_dec_csr_wrdata_r[31],_T_377,io_dec_csr_wrdata_r[29],_T_382,io_dec_csr_wrdata_r[27],_T_387,io_dec_csr_wrdata_r[25],_T_392,_T_474}; // @[Cat.scala 29:58] + reg [31:0] mrac; // @[el2_lib.scala 514:16] + wire _T_485 = io_dec_csr_wraddr_r == 12'hbc0; // @[el2_dec_tlu_ctl.scala 1894:70] + wire wr_mdeau_r = io_dec_csr_wen_r_mod & _T_485; // @[el2_dec_tlu_ctl.scala 1894:41] + wire _T_486 = ~wr_mdeau_r; // @[el2_dec_tlu_ctl.scala 1904:60] + wire _T_487 = io_mdseac_locked_f & _T_486; // @[el2_dec_tlu_ctl.scala 1904:58] + wire _T_489 = io_lsu_imprecise_error_store_any | io_lsu_imprecise_error_load_any; // @[el2_dec_tlu_ctl.scala 1906:50] + wire _T_490 = ~io_nmi_int_detected_f; // @[el2_dec_tlu_ctl.scala 1906:87] + wire _T_491 = _T_489 & _T_490; // @[el2_dec_tlu_ctl.scala 1906:85] + wire _T_492 = ~io_mdseac_locked_f; // @[el2_dec_tlu_ctl.scala 1906:112] + wire mdseac_en = _T_491 & _T_492; // @[el2_dec_tlu_ctl.scala 1906:110] + reg [31:0] mdseac; // @[el2_lib.scala 514:16] + wire _T_498 = wr_mpmc_r & io_dec_csr_wrdata_r[0]; // @[el2_dec_tlu_ctl.scala 1921:31] + wire _T_499 = ~io_internal_dbg_halt_mode_f2; // @[el2_dec_tlu_ctl.scala 1921:58] + wire _T_500 = _T_498 & _T_499; // @[el2_dec_tlu_ctl.scala 1921:56] + wire _T_501 = ~io_ext_int_freeze_d1; // @[el2_dec_tlu_ctl.scala 1921:90] + wire _T_514 = io_dec_csr_wrdata_r[31:27] > 5'h1a; // @[el2_dec_tlu_ctl.scala 1938:49] + wire [4:0] csr_sat = _T_514 ? 5'h1a : io_dec_csr_wrdata_r[31:27]; // @[el2_dec_tlu_ctl.scala 1938:20] + wire _T_517 = io_dec_csr_wraddr_r == 12'h7f0; // @[el2_dec_tlu_ctl.scala 1940:71] + wire wr_micect_r = io_dec_csr_wen_r_mod & _T_517; // @[el2_dec_tlu_ctl.scala 1940:42] + wire [26:0] _T_518 = {26'h0,io_ic_perr_r_d1}; // @[Cat.scala 29:58] + wire [31:0] _GEN_15 = {{5'd0}, _T_518}; // @[el2_dec_tlu_ctl.scala 1941:24] + wire [31:0] _T_520 = micect + _GEN_15; // @[el2_dec_tlu_ctl.scala 1941:24] + wire [31:0] _T_523 = {csr_sat,io_dec_csr_wrdata_r[26:0]}; // @[Cat.scala 29:58] + wire [26:0] micect_inc = _T_520[26:0]; // @[el2_dec_tlu_ctl.scala 1941:14] + wire [31:0] _T_525 = {micect[31:27],micect_inc}; // @[Cat.scala 29:58] + wire _T_536 = io_dec_csr_wraddr_r == 12'h7f1; // @[el2_dec_tlu_ctl.scala 1955:77] + wire wr_miccmect_r = io_dec_csr_wen_r_mod & _T_536; // @[el2_dec_tlu_ctl.scala 1955:48] + wire _T_538 = io_iccm_sbecc_r_d1 | io_iccm_dma_sb_error; // @[el2_dec_tlu_ctl.scala 1956:71] + wire [26:0] _T_539 = {26'h0,_T_538}; // @[Cat.scala 29:58] + wire [26:0] miccmect_inc = miccmect[26:0] + _T_539; // @[el2_dec_tlu_ctl.scala 1956:34] + wire [31:0] _T_546 = {miccmect[31:27],miccmect_inc}; // @[Cat.scala 29:58] + wire _T_547 = wr_miccmect_r | io_iccm_sbecc_r_d1; // @[el2_dec_tlu_ctl.scala 1959:49] + wire _T_558 = io_dec_csr_wraddr_r == 12'h7f2; // @[el2_dec_tlu_ctl.scala 1969:77] + wire wr_mdccmect_r = io_dec_csr_wen_r_mod & _T_558; // @[el2_dec_tlu_ctl.scala 1969:48] + wire [26:0] _T_560 = {26'h0,io_lsu_single_ecc_error_r_d1}; // @[Cat.scala 29:58] + wire [26:0] mdccmect_inc = mdccmect[26:0] + _T_560; // @[el2_dec_tlu_ctl.scala 1970:34] + wire [31:0] _T_567 = {mdccmect[31:27],mdccmect_inc}; // @[Cat.scala 29:58] + wire _T_578 = io_dec_csr_wraddr_r == 12'h7ce; // @[el2_dec_tlu_ctl.scala 1985:70] + wire wr_mfdht_r = io_dec_csr_wen_r_mod & _T_578; // @[el2_dec_tlu_ctl.scala 1985:41] + reg [5:0] mfdht; // @[el2_dec_tlu_ctl.scala 1989:44] + wire _T_583 = io_dec_csr_wraddr_r == 12'h7cf; // @[el2_dec_tlu_ctl.scala 1998:70] + wire wr_mfdhs_r = io_dec_csr_wen_r_mod & _T_583; // @[el2_dec_tlu_ctl.scala 1998:41] + wire _T_586 = ~io_dbg_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 2001:30] + wire _T_587 = io_dbg_tlu_halted & _T_586; // @[el2_dec_tlu_ctl.scala 2001:28] + wire _T_589 = ~io_lsu_idle_any_f; // @[el2_dec_tlu_ctl.scala 2001:65] + wire _T_590 = ~io_ifu_miss_state_idle_f; // @[el2_dec_tlu_ctl.scala 2001:85] + wire [1:0] _T_591 = {_T_589,_T_590}; // @[Cat.scala 29:58] + reg [1:0] mfdhs; // @[Reg.scala 27:20] + wire _T_593 = wr_mfdhs_r | io_dbg_tlu_halted; // @[el2_dec_tlu_ctl.scala 2003:72] + reg [31:0] force_halt_ctr_f; // @[Reg.scala 27:20] + wire [31:0] _T_598 = force_halt_ctr_f + 32'h1; // @[el2_dec_tlu_ctl.scala 2005:75] + wire [62:0] _T_605 = 63'hffffffff << mfdht[5:1]; // @[el2_dec_tlu_ctl.scala 2010:72] + wire [62:0] _GEN_16 = {{31'd0}, force_halt_ctr_f}; // @[el2_dec_tlu_ctl.scala 2010:49] + wire [62:0] _T_606 = _GEN_16 & _T_605; // @[el2_dec_tlu_ctl.scala 2010:49] + wire _T_607 = |_T_606; // @[el2_dec_tlu_ctl.scala 2010:88] + wire _T_610 = io_dec_csr_wraddr_r == 12'hbc8; // @[el2_dec_tlu_ctl.scala 2018:70] + reg [21:0] meivt; // @[el2_lib.scala 514:16] + wire _T_630 = io_dec_csr_wraddr_r == 12'hbca; // @[el2_dec_tlu_ctl.scala 2069:70] + wire _T_631 = io_dec_csr_wen_r_mod & _T_630; // @[el2_dec_tlu_ctl.scala 2069:41] + wire wr_meicpct_r = _T_631 | io_take_ext_int_start; // @[el2_dec_tlu_ctl.scala 2069:84] + reg [7:0] meihap; // @[el2_lib.scala 514:16] + wire [31:0] _T_615 = {meivt,meihap,2'h0}; // @[Cat.scala 29:58] + wire _T_617 = io_dec_csr_wraddr_r == 12'hbcc; // @[el2_dec_tlu_ctl.scala 2042:73] + wire wr_meicurpl_r = io_dec_csr_wen_r_mod & _T_617; // @[el2_dec_tlu_ctl.scala 2042:44] + reg [3:0] meicurpl; // @[el2_dec_tlu_ctl.scala 2045:47] + wire _T_622 = io_dec_csr_wraddr_r == 12'hbcb; // @[el2_dec_tlu_ctl.scala 2057:74] + wire _T_623 = io_dec_csr_wen_r_mod & _T_622; // @[el2_dec_tlu_ctl.scala 2057:45] + wire wr_meicidpl_r = _T_623 | io_take_ext_int_start; // @[el2_dec_tlu_ctl.scala 2057:89] + reg [3:0] meicidpl; // @[el2_dec_tlu_ctl.scala 2062:45] + wire _T_634 = io_dec_csr_wraddr_r == 12'hbc9; // @[el2_dec_tlu_ctl.scala 2078:70] + wire wr_meipt_r = io_dec_csr_wen_r_mod & _T_634; // @[el2_dec_tlu_ctl.scala 2078:41] + reg [3:0] meipt; // @[el2_dec_tlu_ctl.scala 2081:44] + wire _T_638 = io_trigger_hit_r_d1 & io_dcsr_single_step_done_f; // @[el2_dec_tlu_ctl.scala 2109:90] + wire trigger_hit_for_dscr_cause_r_d1 = io_trigger_hit_dmode_r_d1 | _T_638; // @[el2_dec_tlu_ctl.scala 2109:67] + wire _T_639 = ~io_ebreak_to_debug_mode_r_d1; // @[el2_dec_tlu_ctl.scala 2112:35] + wire _T_640 = io_dcsr_single_step_done_f & _T_639; // @[el2_dec_tlu_ctl.scala 2112:33] + wire _T_641 = ~trigger_hit_for_dscr_cause_r_d1; // @[el2_dec_tlu_ctl.scala 2112:67] + wire _T_642 = _T_640 & _T_641; // @[el2_dec_tlu_ctl.scala 2112:65] + wire _T_643 = ~io_debug_halt_req; // @[el2_dec_tlu_ctl.scala 2112:102] + wire _T_644 = _T_642 & _T_643; // @[el2_dec_tlu_ctl.scala 2112:100] + wire _T_647 = io_debug_halt_req & _T_639; // @[el2_dec_tlu_ctl.scala 2113:24] + wire _T_649 = _T_647 & _T_641; // @[el2_dec_tlu_ctl.scala 2113:56] + wire _T_652 = io_ebreak_to_debug_mode_r_d1 & _T_641; // @[el2_dec_tlu_ctl.scala 2114:35] + wire [2:0] _T_655 = _T_644 ? 3'h4 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_656 = _T_649 ? 3'h3 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_657 = _T_652 ? 3'h1 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_658 = trigger_hit_for_dscr_cause_r_d1 ? 3'h2 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_659 = _T_655 | _T_656; // @[Mux.scala 27:72] + wire [2:0] _T_660 = _T_659 | _T_657; // @[Mux.scala 27:72] + wire [2:0] dcsr_cause = _T_660 | _T_658; // @[Mux.scala 27:72] + wire _T_662 = io_allow_dbg_halt_csr_write & io_dec_csr_wen_r_mod; // @[el2_dec_tlu_ctl.scala 2117:47] + wire _T_664 = io_dec_csr_wraddr_r == 12'h7b0; // @[el2_dec_tlu_ctl.scala 2117:99] + wire wr_dcsr_r = _T_662 & _T_664; // @[el2_dec_tlu_ctl.scala 2117:70] + wire _T_666 = io_dcsr[8:6] == 3'h3; // @[el2_dec_tlu_ctl.scala 2123:76] + wire dcsr_cause_upgradeable = io_internal_dbg_halt_mode_f & _T_666; // @[el2_dec_tlu_ctl.scala 2123:60] + wire _T_667 = ~io_dbg_tlu_halted; // @[el2_dec_tlu_ctl.scala 2124:60] + wire _T_668 = _T_667 | dcsr_cause_upgradeable; // @[el2_dec_tlu_ctl.scala 2124:79] + wire enter_debug_halt_req_le = io_enter_debug_halt_req & _T_668; // @[el2_dec_tlu_ctl.scala 2124:57] + wire nmi_in_debug_mode = io_nmi_int_detected_f & io_internal_dbg_halt_mode_f; // @[el2_dec_tlu_ctl.scala 2126:49] + wire [15:0] _T_674 = {io_dcsr[15:9],dcsr_cause,io_dcsr[5:2],2'h3}; // @[Cat.scala 29:58] + wire _T_680 = nmi_in_debug_mode | io_dcsr[3]; // @[el2_dec_tlu_ctl.scala 2128:146] + wire [15:0] _T_689 = {io_dec_csr_wrdata_r[15],3'h0,io_dec_csr_wrdata_r[11:10],1'h0,io_dcsr[8:6],2'h0,_T_680,io_dec_csr_wrdata_r[2],2'h3}; // @[Cat.scala 29:58] + wire [15:0] _T_694 = {io_dcsr[15:4],nmi_in_debug_mode,io_dcsr[2],2'h3}; // @[Cat.scala 29:58] + wire _T_696 = enter_debug_halt_req_le | wr_dcsr_r; // @[el2_dec_tlu_ctl.scala 2130:55] + wire _T_697 = _T_696 | io_internal_dbg_halt_mode; // @[el2_dec_tlu_ctl.scala 2130:67] + reg [15:0] _T_700; // @[el2_lib.scala 514:16] + wire _T_703 = io_dec_csr_wraddr_r == 12'h7b1; // @[el2_dec_tlu_ctl.scala 2138:98] + wire wr_dpc_r = _T_662 & _T_703; // @[el2_dec_tlu_ctl.scala 2138:69] + wire _T_706 = ~io_request_debug_mode_done; // @[el2_dec_tlu_ctl.scala 2139:68] + wire dpc_capture_npc = _T_587 & _T_706; // @[el2_dec_tlu_ctl.scala 2139:66] + wire _T_707 = ~io_request_debug_mode_r; // @[el2_dec_tlu_ctl.scala 2143:6] + wire _T_708 = ~dpc_capture_npc; // @[el2_dec_tlu_ctl.scala 2143:24] + wire _T_709 = _T_707 & _T_708; // @[el2_dec_tlu_ctl.scala 2143:22] + wire _T_710 = _T_709 & wr_dpc_r; // @[el2_dec_tlu_ctl.scala 2143:41] + wire _T_715 = _T_707 & dpc_capture_npc; // @[el2_dec_tlu_ctl.scala 2145:22] + wire [30:0] _T_717 = _T_710 ? io_dec_csr_wrdata_r[31:1] : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_718 = io_request_debug_mode_r ? pc_r : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_719 = _T_715 ? io_npc_r : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_720 = _T_717 | _T_718; // @[Mux.scala 27:72] + wire _T_722 = wr_dpc_r | io_request_debug_mode_r; // @[el2_dec_tlu_ctl.scala 2147:37] + reg [30:0] _T_725; // @[el2_lib.scala 514:16] + wire [2:0] _T_729 = {io_dec_csr_wrdata_r[24],io_dec_csr_wrdata_r[21:20]}; // @[Cat.scala 29:58] + wire _T_732 = io_dec_csr_wraddr_r == 12'h7c8; // @[el2_dec_tlu_ctl.scala 2162:103] + reg [16:0] dicawics; // @[el2_lib.scala 514:16] + wire _T_736 = io_dec_csr_wraddr_r == 12'h7c9; // @[el2_dec_tlu_ctl.scala 2180:101] + wire wr_dicad0_r = _T_662 & _T_736; // @[el2_dec_tlu_ctl.scala 2180:72] + reg [70:0] dicad0; // @[el2_lib.scala 514:16] + wire _T_742 = io_dec_csr_wraddr_r == 12'h7cc; // @[el2_dec_tlu_ctl.scala 2193:102] + wire wr_dicad0h_r = _T_662 & _T_742; // @[el2_dec_tlu_ctl.scala 2193:73] + reg [31:0] dicad0h; // @[el2_lib.scala 514:16] + wire _T_750 = io_dec_csr_wraddr_r == 12'h7ca; // @[el2_dec_tlu_ctl.scala 2205:103] + wire _T_751 = _T_662 & _T_750; // @[el2_dec_tlu_ctl.scala 2205:74] + wire _T_755 = _T_751 | io_ifu_ic_debug_rd_data_valid; // @[el2_dec_tlu_ctl.scala 2209:81] + reg [31:0] _T_757; // @[Reg.scala 27:20] + wire [31:0] dicad1 = {25'h0,_T_757[6:0]}; // @[Cat.scala 29:58] + wire [38:0] _T_762 = {dicad1[6:0],dicad0h}; // @[Cat.scala 29:58] + wire _T_764 = io_allow_dbg_halt_csr_write & io_dec_csr_any_unq_d; // @[el2_dec_tlu_ctl.scala 2237:53] + wire _T_765 = _T_764 & io_dec_i0_decode_d; // @[el2_dec_tlu_ctl.scala 2237:76] + wire _T_766 = ~io_dec_csr_wen_unq_d; // @[el2_dec_tlu_ctl.scala 2237:99] + wire _T_767 = _T_765 & _T_766; // @[el2_dec_tlu_ctl.scala 2237:97] + wire _T_769 = io_dec_csr_rdaddr_d == 12'h7cb; // @[el2_dec_tlu_ctl.scala 2237:150] + wire _T_772 = io_dec_csr_wraddr_r == 12'h7cb; // @[el2_dec_tlu_ctl.scala 2238:105] + reg icache_rd_valid_f; // @[el2_dec_tlu_ctl.scala 2240:59] + reg icache_wr_valid_f; // @[el2_dec_tlu_ctl.scala 2241:59] + wire _T_774 = io_dec_csr_wraddr_r == 12'h7a0; // @[el2_dec_tlu_ctl.scala 2252:70] + wire wr_mtsel_r = io_dec_csr_wen_r_mod & _T_774; // @[el2_dec_tlu_ctl.scala 2252:41] + reg [1:0] mtsel; // @[el2_dec_tlu_ctl.scala 2255:44] + wire tdata_load = io_dec_csr_wrdata_r[0] & _T_406; // @[el2_dec_tlu_ctl.scala 2290:43] + wire tdata_opcode = io_dec_csr_wrdata_r[2] & _T_406; // @[el2_dec_tlu_ctl.scala 2292:45] + wire _T_785 = io_dec_csr_wrdata_r[27] & io_dbg_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 2294:47] + wire tdata_action = _T_785 & io_dec_csr_wrdata_r[12]; // @[el2_dec_tlu_ctl.scala 2294:70] + wire [9:0] tdata_wrdata_r = {_T_785,io_dec_csr_wrdata_r[20:19],tdata_action,io_dec_csr_wrdata_r[11],io_dec_csr_wrdata_r[7:6],tdata_opcode,io_dec_csr_wrdata_r[1],tdata_load}; // @[Cat.scala 29:58] + wire _T_800 = io_dec_csr_wraddr_r == 12'h7a1; // @[el2_dec_tlu_ctl.scala 2300:100] + wire _T_801 = io_dec_csr_wen_r_mod & _T_800; // @[el2_dec_tlu_ctl.scala 2300:71] + wire _T_802 = mtsel == 2'h0; // @[el2_dec_tlu_ctl.scala 2300:122] + wire _T_803 = _T_801 & _T_802; // @[el2_dec_tlu_ctl.scala 2300:113] + wire _T_805 = ~io_mtdata1_t_0[9]; // @[el2_dec_tlu_ctl.scala 2300:139] + wire _T_806 = _T_805 | io_dbg_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 2300:171] + wire wr_mtdata1_t_r_0 = _T_803 & _T_806; // @[el2_dec_tlu_ctl.scala 2300:136] + wire _T_814 = ~io_mtdata1_t_1[9]; // @[el2_dec_tlu_ctl.scala 2300:139] + wire _T_815 = _T_814 | io_dbg_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 2300:171] + wire wr_mtdata1_t_r_1 = _T_803 & _T_815; // @[el2_dec_tlu_ctl.scala 2300:136] + wire _T_823 = ~io_mtdata1_t_2[9]; // @[el2_dec_tlu_ctl.scala 2300:139] + wire _T_824 = _T_823 | io_dbg_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 2300:171] + wire wr_mtdata1_t_r_2 = _T_803 & _T_824; // @[el2_dec_tlu_ctl.scala 2300:136] + wire _T_832 = ~io_mtdata1_t_3[9]; // @[el2_dec_tlu_ctl.scala 2300:139] + wire _T_833 = _T_832 | io_dbg_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 2300:171] + wire wr_mtdata1_t_r_3 = _T_803 & _T_833; // @[el2_dec_tlu_ctl.scala 2300:136] + wire _T_839 = io_update_hit_bit_r[0] | io_mtdata1_t_0[8]; // @[el2_dec_tlu_ctl.scala 2301:140] + wire [9:0] _T_842 = {io_mtdata1_t_0[9],_T_839,io_mtdata1_t_0[7:0]}; // @[Cat.scala 29:58] + wire _T_848 = io_update_hit_bit_r[1] | io_mtdata1_t_1[8]; // @[el2_dec_tlu_ctl.scala 2301:140] + wire [9:0] _T_851 = {io_mtdata1_t_1[9],_T_848,io_mtdata1_t_1[7:0]}; // @[Cat.scala 29:58] + wire _T_857 = io_update_hit_bit_r[2] | io_mtdata1_t_2[8]; // @[el2_dec_tlu_ctl.scala 2301:140] + wire [9:0] _T_860 = {io_mtdata1_t_2[9],_T_857,io_mtdata1_t_2[7:0]}; // @[Cat.scala 29:58] + wire _T_866 = io_update_hit_bit_r[3] | io_mtdata1_t_3[8]; // @[el2_dec_tlu_ctl.scala 2301:140] + wire [9:0] _T_869 = {io_mtdata1_t_3[9],_T_866,io_mtdata1_t_3[7:0]}; // @[Cat.scala 29:58] + reg [9:0] _T_871; // @[el2_dec_tlu_ctl.scala 2303:76] + reg [9:0] _T_872; // @[el2_dec_tlu_ctl.scala 2303:76] + reg [9:0] _T_873; // @[el2_dec_tlu_ctl.scala 2303:76] + reg [9:0] _T_874; // @[el2_dec_tlu_ctl.scala 2303:76] + wire [31:0] _T_889 = {4'h2,io_mtdata1_t_0[9],6'h1f,io_mtdata1_t_0[8:7],6'h0,io_mtdata1_t_0[6:5],3'h0,io_mtdata1_t_0[4:3],3'h0,io_mtdata1_t_0[2:0]}; // @[Cat.scala 29:58] + wire _T_890 = mtsel == 2'h1; // @[el2_dec_tlu_ctl.scala 2306:60] + wire [31:0] _T_904 = {4'h2,io_mtdata1_t_1[9],6'h1f,io_mtdata1_t_1[8:7],6'h0,io_mtdata1_t_1[6:5],3'h0,io_mtdata1_t_1[4:3],3'h0,io_mtdata1_t_1[2:0]}; // @[Cat.scala 29:58] + wire _T_905 = mtsel == 2'h2; // @[el2_dec_tlu_ctl.scala 2306:60] + wire [31:0] _T_919 = {4'h2,io_mtdata1_t_2[9],6'h1f,io_mtdata1_t_2[8:7],6'h0,io_mtdata1_t_2[6:5],3'h0,io_mtdata1_t_2[4:3],3'h0,io_mtdata1_t_2[2:0]}; // @[Cat.scala 29:58] + wire _T_920 = mtsel == 2'h3; // @[el2_dec_tlu_ctl.scala 2306:60] + wire [31:0] _T_934 = {4'h2,io_mtdata1_t_3[9],6'h1f,io_mtdata1_t_3[8:7],6'h0,io_mtdata1_t_3[6:5],3'h0,io_mtdata1_t_3[4:3],3'h0,io_mtdata1_t_3[2:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_935 = _T_802 ? _T_889 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_936 = _T_890 ? _T_904 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_937 = _T_905 ? _T_919 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_938 = _T_920 ? _T_934 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_939 = _T_935 | _T_936; // @[Mux.scala 27:72] + wire [31:0] _T_940 = _T_939 | _T_937; // @[Mux.scala 27:72] + wire [31:0] mtdata1_tsel_out = _T_940 | _T_938; // @[Mux.scala 27:72] + wire _T_967 = io_dec_csr_wraddr_r == 12'h7a2; // @[el2_dec_tlu_ctl.scala 2320:99] + wire _T_968 = io_dec_csr_wen_r_mod & _T_967; // @[el2_dec_tlu_ctl.scala 2320:70] + wire _T_970 = _T_968 & _T_802; // @[el2_dec_tlu_ctl.scala 2320:112] + wire _T_979 = _T_968 & _T_890; // @[el2_dec_tlu_ctl.scala 2320:112] + wire _T_988 = _T_968 & _T_905; // @[el2_dec_tlu_ctl.scala 2320:112] + wire _T_997 = _T_968 & _T_920; // @[el2_dec_tlu_ctl.scala 2320:112] + reg [31:0] mtdata2_t_0; // @[el2_lib.scala 514:16] + reg [31:0] mtdata2_t_1; // @[el2_lib.scala 514:16] + reg [31:0] mtdata2_t_2; // @[el2_lib.scala 514:16] + reg [31:0] mtdata2_t_3; // @[el2_lib.scala 514:16] + wire [31:0] _T_1014 = _T_802 ? mtdata2_t_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1015 = _T_890 ? mtdata2_t_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1016 = _T_905 ? mtdata2_t_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1017 = _T_920 ? mtdata2_t_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1018 = _T_1014 | _T_1015; // @[Mux.scala 27:72] + wire [31:0] _T_1019 = _T_1018 | _T_1016; // @[Mux.scala 27:72] + wire [31:0] mtdata2_tsel_out = _T_1019 | _T_1017; // @[Mux.scala 27:72] + wire [3:0] _T_1022 = io_tlu_i0_commit_cmt ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] pmu_i0_itype_qual = io_dec_tlu_packet_r_pmu_i0_itype & _T_1022; // @[el2_dec_tlu_ctl.scala 2345:60] + wire _T_1024 = ~mcountinhibit[3]; // @[el2_dec_tlu_ctl.scala 2351:25] + reg [9:0] mhpme3; // @[Reg.scala 27:20] + wire _T_1025 = mhpme3 == 10'h1; // @[el2_dec_tlu_ctl.scala 2352:21] + wire _T_1027 = mhpme3 == 10'h2; // @[el2_dec_tlu_ctl.scala 2353:21] + wire _T_1029 = mhpme3 == 10'h3; // @[el2_dec_tlu_ctl.scala 2354:21] + wire _T_1031 = mhpme3 == 10'h4; // @[el2_dec_tlu_ctl.scala 2355:21] + wire _T_1033 = ~io_illegal_r; // @[el2_dec_tlu_ctl.scala 2355:83] + wire _T_1034 = io_tlu_i0_commit_cmt & _T_1033; // @[el2_dec_tlu_ctl.scala 2355:81] + wire _T_1035 = mhpme3 == 10'h5; // @[el2_dec_tlu_ctl.scala 2356:21] + wire _T_1037 = ~io_exu_pmu_i0_pc4; // @[el2_dec_tlu_ctl.scala 2356:83] + wire _T_1038 = io_tlu_i0_commit_cmt & _T_1037; // @[el2_dec_tlu_ctl.scala 2356:81] + wire _T_1040 = _T_1038 & _T_1033; // @[el2_dec_tlu_ctl.scala 2356:102] + wire _T_1041 = mhpme3 == 10'h6; // @[el2_dec_tlu_ctl.scala 2357:21] + wire _T_1043 = io_tlu_i0_commit_cmt & io_exu_pmu_i0_pc4; // @[el2_dec_tlu_ctl.scala 2357:81] + wire _T_1045 = _T_1043 & _T_1033; // @[el2_dec_tlu_ctl.scala 2357:102] + wire _T_1046 = mhpme3 == 10'h7; // @[el2_dec_tlu_ctl.scala 2358:21] + wire _T_1048 = mhpme3 == 10'h8; // @[el2_dec_tlu_ctl.scala 2359:21] + wire _T_1050 = mhpme3 == 10'h1e; // @[el2_dec_tlu_ctl.scala 2360:21] + wire _T_1052 = mhpme3 == 10'h9; // @[el2_dec_tlu_ctl.scala 2361:21] + wire _T_1054 = pmu_i0_itype_qual == 4'h1; // @[el2_dec_tlu_ctl.scala 2361:78] + wire _T_1055 = mhpme3 == 10'ha; // @[el2_dec_tlu_ctl.scala 2362:21] + wire _T_1057 = io_dec_tlu_packet_r_pmu_divide & io_tlu_i0_commit_cmt; // @[el2_dec_tlu_ctl.scala 2362:92] + wire _T_1058 = mhpme3 == 10'hb; // @[el2_dec_tlu_ctl.scala 2363:21] + wire _T_1060 = pmu_i0_itype_qual == 4'h2; // @[el2_dec_tlu_ctl.scala 2363:78] + wire _T_1061 = mhpme3 == 10'hc; // @[el2_dec_tlu_ctl.scala 2364:21] + wire _T_1063 = pmu_i0_itype_qual == 4'h3; // @[el2_dec_tlu_ctl.scala 2364:78] + wire _T_1064 = mhpme3 == 10'hd; // @[el2_dec_tlu_ctl.scala 2365:21] + wire _T_1067 = mhpme3 == 10'he; // @[el2_dec_tlu_ctl.scala 2366:21] + wire _T_1068 = io_dec_tlu_packet_r_pmu_lsu_misaligned >> _T_1067; // @[el2_dec_tlu_ctl.scala 2366:7] + wire _T_1070 = _T_1060 & _T_1068; // @[el2_dec_tlu_ctl.scala 2365:89] + wire _T_1072 = _T_1070 & _T_1063; // @[el2_dec_tlu_ctl.scala 2366:45] + wire _T_1074 = _T_1072 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[el2_dec_tlu_ctl.scala 2366:77] + wire _T_1075 = mhpme3 == 10'hf; // @[el2_dec_tlu_ctl.scala 2368:21] + wire _T_1077 = pmu_i0_itype_qual == 4'h4; // @[el2_dec_tlu_ctl.scala 2368:76] + wire _T_1078 = mhpme3 == 10'h10; // @[el2_dec_tlu_ctl.scala 2369:21] + wire _T_1080 = pmu_i0_itype_qual == 4'h5; // @[el2_dec_tlu_ctl.scala 2369:76] + wire _T_1081 = mhpme3 == 10'h12; // @[el2_dec_tlu_ctl.scala 2370:21] + wire _T_1083 = pmu_i0_itype_qual == 4'h6; // @[el2_dec_tlu_ctl.scala 2370:76] + wire _T_1084 = mhpme3 == 10'h11; // @[el2_dec_tlu_ctl.scala 2371:21] + wire _T_1086 = pmu_i0_itype_qual == 4'h7; // @[el2_dec_tlu_ctl.scala 2371:76] + wire _T_1087 = mhpme3 == 10'h13; // @[el2_dec_tlu_ctl.scala 2372:21] + wire _T_1089 = pmu_i0_itype_qual == 4'h8; // @[el2_dec_tlu_ctl.scala 2372:76] + wire _T_1090 = mhpme3 == 10'h14; // @[el2_dec_tlu_ctl.scala 2373:21] + wire _T_1092 = pmu_i0_itype_qual == 4'h9; // @[el2_dec_tlu_ctl.scala 2373:76] + wire _T_1093 = mhpme3 == 10'h15; // @[el2_dec_tlu_ctl.scala 2374:21] + wire _T_1095 = pmu_i0_itype_qual == 4'ha; // @[el2_dec_tlu_ctl.scala 2374:76] + wire _T_1096 = mhpme3 == 10'h16; // @[el2_dec_tlu_ctl.scala 2375:21] + wire _T_1098 = pmu_i0_itype_qual == 4'hb; // @[el2_dec_tlu_ctl.scala 2375:76] + wire _T_1099 = mhpme3 == 10'h17; // @[el2_dec_tlu_ctl.scala 2376:21] + wire _T_1101 = pmu_i0_itype_qual == 4'hc; // @[el2_dec_tlu_ctl.scala 2376:76] + wire _T_1102 = mhpme3 == 10'h18; // @[el2_dec_tlu_ctl.scala 2377:21] + wire _T_1104 = pmu_i0_itype_qual == 4'hd; // @[el2_dec_tlu_ctl.scala 2377:76] + wire _T_1105 = pmu_i0_itype_qual == 4'he; // @[el2_dec_tlu_ctl.scala 2377:109] + wire _T_1106 = _T_1104 | _T_1105; // @[el2_dec_tlu_ctl.scala 2377:88] + wire _T_1107 = mhpme3 == 10'h19; // @[el2_dec_tlu_ctl.scala 2378:21] + wire _T_1109 = io_exu_pmu_i0_br_misp & io_tlu_i0_commit_cmt; // @[el2_dec_tlu_ctl.scala 2378:82] + wire _T_1110 = mhpme3 == 10'h1a; // @[el2_dec_tlu_ctl.scala 2379:21] + wire _T_1112 = io_exu_pmu_i0_br_ataken & io_tlu_i0_commit_cmt; // @[el2_dec_tlu_ctl.scala 2379:84] + wire _T_1113 = mhpme3 == 10'h1b; // @[el2_dec_tlu_ctl.scala 2380:21] + wire _T_1115 = io_dec_tlu_packet_r_pmu_i0_br_unpred & io_tlu_i0_commit_cmt; // @[el2_dec_tlu_ctl.scala 2380:97] + wire _T_1116 = mhpme3 == 10'h1c; // @[el2_dec_tlu_ctl.scala 2381:21] + wire _T_1120 = mhpme3 == 10'h1f; // @[el2_dec_tlu_ctl.scala 2383:21] + wire _T_1122 = mhpme3 == 10'h20; // @[el2_dec_tlu_ctl.scala 2384:21] + wire _T_1124 = mhpme3 == 10'h22; // @[el2_dec_tlu_ctl.scala 2385:21] + wire _T_1126 = mhpme3 == 10'h23; // @[el2_dec_tlu_ctl.scala 2386:21] + wire _T_1128 = mhpme3 == 10'h24; // @[el2_dec_tlu_ctl.scala 2387:21] + wire _T_1130 = mhpme3 == 10'h25; // @[el2_dec_tlu_ctl.scala 2388:21] + wire _T_1132 = io_i0_exception_valid_r | io_i0_trigger_hit_r; // @[el2_dec_tlu_ctl.scala 2388:85] + wire _T_1133 = _T_1132 | io_lsu_exc_valid_r; // @[el2_dec_tlu_ctl.scala 2388:107] + wire _T_1134 = mhpme3 == 10'h26; // @[el2_dec_tlu_ctl.scala 2389:21] + wire _T_1136 = io_take_timer_int | io_take_int_timer0_int; // @[el2_dec_tlu_ctl.scala 2389:79] + wire _T_1137 = _T_1136 | io_take_int_timer1_int; // @[el2_dec_tlu_ctl.scala 2389:104] + wire _T_1138 = mhpme3 == 10'h27; // @[el2_dec_tlu_ctl.scala 2390:21] + wire _T_1140 = mhpme3 == 10'h28; // @[el2_dec_tlu_ctl.scala 2391:21] + wire _T_1142 = mhpme3 == 10'h29; // @[el2_dec_tlu_ctl.scala 2392:21] + wire _T_1144 = io_dec_tlu_br0_error_r | io_dec_tlu_br0_start_error_r; // @[el2_dec_tlu_ctl.scala 2392:84] + wire _T_1145 = _T_1144 & io_rfpc_i0_r; // @[el2_dec_tlu_ctl.scala 2392:116] + wire _T_1146 = mhpme3 == 10'h2a; // @[el2_dec_tlu_ctl.scala 2393:21] + wire _T_1148 = mhpme3 == 10'h2b; // @[el2_dec_tlu_ctl.scala 2394:21] + wire _T_1150 = mhpme3 == 10'h2c; // @[el2_dec_tlu_ctl.scala 2395:21] + wire _T_1152 = mhpme3 == 10'h2d; // @[el2_dec_tlu_ctl.scala 2396:21] + wire _T_1154 = mhpme3 == 10'h2e; // @[el2_dec_tlu_ctl.scala 2397:21] + wire _T_1156 = mhpme3 == 10'h2f; // @[el2_dec_tlu_ctl.scala 2398:21] + wire _T_1158 = mhpme3 == 10'h30; // @[el2_dec_tlu_ctl.scala 2399:21] + wire _T_1160 = mhpme3 == 10'h31; // @[el2_dec_tlu_ctl.scala 2400:21] + wire _T_1164 = ~io_mstatus[0]; // @[el2_dec_tlu_ctl.scala 2400:60] + wire _T_1165 = mhpme3 == 10'h32; // @[el2_dec_tlu_ctl.scala 2401:21] + wire [5:0] _T_1172 = io_mip & mie; // @[el2_dec_tlu_ctl.scala 2401:100] + wire [5:0] _GEN_17 = {{5'd0}, _T_1164}; // @[el2_dec_tlu_ctl.scala 2401:85] + wire [5:0] _T_1173 = _GEN_17 & _T_1172; // @[el2_dec_tlu_ctl.scala 2401:85] + wire _T_1174 = mhpme3 == 10'h36; // @[el2_dec_tlu_ctl.scala 2402:21] + wire _T_1176 = pmu_i0_itype_qual == 4'hf; // @[el2_dec_tlu_ctl.scala 2402:78] + wire _T_1177 = mhpme3 == 10'h37; // @[el2_dec_tlu_ctl.scala 2403:21] + wire _T_1179 = io_tlu_i0_commit_cmt & io_lsu_pmu_load_external_r; // @[el2_dec_tlu_ctl.scala 2403:81] + wire _T_1180 = mhpme3 == 10'h38; // @[el2_dec_tlu_ctl.scala 2404:21] + wire _T_1182 = io_tlu_i0_commit_cmt & io_lsu_pmu_store_external_r; // @[el2_dec_tlu_ctl.scala 2404:81] + wire _T_1183 = mhpme3 == 10'h200; // @[el2_dec_tlu_ctl.scala 2406:21] + wire _T_1185 = mhpme3 == 10'h201; // @[el2_dec_tlu_ctl.scala 2407:21] + wire _T_1187 = mhpme3 == 10'h202; // @[el2_dec_tlu_ctl.scala 2408:21] + wire _T_1189 = mhpme3 == 10'h203; // @[el2_dec_tlu_ctl.scala 2409:21] + wire _T_1191 = mhpme3 == 10'h204; // @[el2_dec_tlu_ctl.scala 2410:21] + wire _T_1194 = _T_1027 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_1195 = _T_1029 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_1196 = _T_1031 & _T_1034; // @[Mux.scala 27:72] + wire _T_1197 = _T_1035 & _T_1040; // @[Mux.scala 27:72] + wire _T_1198 = _T_1041 & _T_1045; // @[Mux.scala 27:72] + wire _T_1199 = _T_1046 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_1200 = _T_1048 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_1201 = _T_1050 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_1202 = _T_1052 & _T_1054; // @[Mux.scala 27:72] + wire _T_1203 = _T_1055 & _T_1057; // @[Mux.scala 27:72] + wire _T_1204 = _T_1058 & _T_1060; // @[Mux.scala 27:72] + wire _T_1205 = _T_1061 & _T_1063; // @[Mux.scala 27:72] + wire _T_1206 = _T_1064 & _T_1074; // @[Mux.scala 27:72] + wire _T_1207 = _T_1075 & _T_1077; // @[Mux.scala 27:72] + wire _T_1208 = _T_1078 & _T_1080; // @[Mux.scala 27:72] + wire _T_1209 = _T_1081 & _T_1083; // @[Mux.scala 27:72] + wire _T_1210 = _T_1084 & _T_1086; // @[Mux.scala 27:72] + wire _T_1211 = _T_1087 & _T_1089; // @[Mux.scala 27:72] + wire _T_1212 = _T_1090 & _T_1092; // @[Mux.scala 27:72] + wire _T_1213 = _T_1093 & _T_1095; // @[Mux.scala 27:72] + wire _T_1214 = _T_1096 & _T_1098; // @[Mux.scala 27:72] + wire _T_1215 = _T_1099 & _T_1101; // @[Mux.scala 27:72] + wire _T_1216 = _T_1102 & _T_1106; // @[Mux.scala 27:72] + wire _T_1217 = _T_1107 & _T_1109; // @[Mux.scala 27:72] + wire _T_1218 = _T_1110 & _T_1112; // @[Mux.scala 27:72] + wire _T_1219 = _T_1113 & _T_1115; // @[Mux.scala 27:72] + wire _T_1220 = _T_1116 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_1222 = _T_1120 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_1223 = _T_1122 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_1224 = _T_1124 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_1225 = _T_1126 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_1226 = _T_1128 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_1227 = _T_1130 & _T_1133; // @[Mux.scala 27:72] + wire _T_1228 = _T_1134 & _T_1137; // @[Mux.scala 27:72] + wire _T_1229 = _T_1138 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_1230 = _T_1140 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_1231 = _T_1142 & _T_1145; // @[Mux.scala 27:72] + wire _T_1232 = _T_1146 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1233 = _T_1148 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1234 = _T_1150 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_1235 = _T_1152 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1236 = _T_1154 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1237 = _T_1156 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1238 = _T_1158 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1239 = _T_1160 & _T_1164; // @[Mux.scala 27:72] + wire [5:0] _T_1240 = _T_1165 ? _T_1173 : 6'h0; // @[Mux.scala 27:72] + wire _T_1241 = _T_1174 & _T_1176; // @[Mux.scala 27:72] + wire _T_1242 = _T_1177 & _T_1179; // @[Mux.scala 27:72] + wire _T_1243 = _T_1180 & _T_1182; // @[Mux.scala 27:72] + wire _T_1244 = _T_1183 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_1245 = _T_1185 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_1246 = _T_1187 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_1247 = _T_1189 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_1248 = _T_1191 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_1249 = _T_1025 | _T_1194; // @[Mux.scala 27:72] + wire _T_1250 = _T_1249 | _T_1195; // @[Mux.scala 27:72] + wire _T_1251 = _T_1250 | _T_1196; // @[Mux.scala 27:72] + wire _T_1252 = _T_1251 | _T_1197; // @[Mux.scala 27:72] + wire _T_1253 = _T_1252 | _T_1198; // @[Mux.scala 27:72] + wire _T_1254 = _T_1253 | _T_1199; // @[Mux.scala 27:72] + wire _T_1255 = _T_1254 | _T_1200; // @[Mux.scala 27:72] + wire _T_1256 = _T_1255 | _T_1201; // @[Mux.scala 27:72] + wire _T_1257 = _T_1256 | _T_1202; // @[Mux.scala 27:72] + wire _T_1258 = _T_1257 | _T_1203; // @[Mux.scala 27:72] + wire _T_1259 = _T_1258 | _T_1204; // @[Mux.scala 27:72] + wire _T_1260 = _T_1259 | _T_1205; // @[Mux.scala 27:72] + wire _T_1261 = _T_1260 | _T_1206; // @[Mux.scala 27:72] + wire _T_1262 = _T_1261 | _T_1207; // @[Mux.scala 27:72] + wire _T_1263 = _T_1262 | _T_1208; // @[Mux.scala 27:72] + wire _T_1264 = _T_1263 | _T_1209; // @[Mux.scala 27:72] + wire _T_1265 = _T_1264 | _T_1210; // @[Mux.scala 27:72] + wire _T_1266 = _T_1265 | _T_1211; // @[Mux.scala 27:72] + wire _T_1267 = _T_1266 | _T_1212; // @[Mux.scala 27:72] + wire _T_1268 = _T_1267 | _T_1213; // @[Mux.scala 27:72] + wire _T_1269 = _T_1268 | _T_1214; // @[Mux.scala 27:72] + wire _T_1270 = _T_1269 | _T_1215; // @[Mux.scala 27:72] + wire _T_1271 = _T_1270 | _T_1216; // @[Mux.scala 27:72] + wire _T_1272 = _T_1271 | _T_1217; // @[Mux.scala 27:72] + wire _T_1273 = _T_1272 | _T_1218; // @[Mux.scala 27:72] + wire _T_1274 = _T_1273 | _T_1219; // @[Mux.scala 27:72] + wire _T_1275 = _T_1274 | _T_1220; // @[Mux.scala 27:72] + wire _T_1276 = _T_1275 | _T_1201; // @[Mux.scala 27:72] + wire _T_1277 = _T_1276 | _T_1222; // @[Mux.scala 27:72] + wire _T_1278 = _T_1277 | _T_1223; // @[Mux.scala 27:72] + wire _T_1279 = _T_1278 | _T_1224; // @[Mux.scala 27:72] + wire _T_1280 = _T_1279 | _T_1225; // @[Mux.scala 27:72] + wire _T_1281 = _T_1280 | _T_1226; // @[Mux.scala 27:72] + wire _T_1282 = _T_1281 | _T_1227; // @[Mux.scala 27:72] + wire _T_1283 = _T_1282 | _T_1228; // @[Mux.scala 27:72] + wire _T_1284 = _T_1283 | _T_1229; // @[Mux.scala 27:72] + wire _T_1285 = _T_1284 | _T_1230; // @[Mux.scala 27:72] + wire _T_1286 = _T_1285 | _T_1231; // @[Mux.scala 27:72] + wire _T_1287 = _T_1286 | _T_1232; // @[Mux.scala 27:72] + wire _T_1288 = _T_1287 | _T_1233; // @[Mux.scala 27:72] + wire _T_1289 = _T_1288 | _T_1234; // @[Mux.scala 27:72] + wire _T_1290 = _T_1289 | _T_1235; // @[Mux.scala 27:72] + wire _T_1291 = _T_1290 | _T_1236; // @[Mux.scala 27:72] + wire _T_1292 = _T_1291 | _T_1237; // @[Mux.scala 27:72] + wire _T_1293 = _T_1292 | _T_1238; // @[Mux.scala 27:72] + wire _T_1294 = _T_1293 | _T_1239; // @[Mux.scala 27:72] + wire [5:0] _GEN_18 = {{5'd0}, _T_1294}; // @[Mux.scala 27:72] + wire [5:0] _T_1295 = _GEN_18 | _T_1240; // @[Mux.scala 27:72] + wire [5:0] _GEN_19 = {{5'd0}, _T_1241}; // @[Mux.scala 27:72] + wire [5:0] _T_1296 = _T_1295 | _GEN_19; // @[Mux.scala 27:72] + wire [5:0] _GEN_20 = {{5'd0}, _T_1242}; // @[Mux.scala 27:72] + wire [5:0] _T_1297 = _T_1296 | _GEN_20; // @[Mux.scala 27:72] + wire [5:0] _GEN_21 = {{5'd0}, _T_1243}; // @[Mux.scala 27:72] + wire [5:0] _T_1298 = _T_1297 | _GEN_21; // @[Mux.scala 27:72] + wire [5:0] _GEN_22 = {{5'd0}, _T_1244}; // @[Mux.scala 27:72] + wire [5:0] _T_1299 = _T_1298 | _GEN_22; // @[Mux.scala 27:72] + wire [5:0] _GEN_23 = {{5'd0}, _T_1245}; // @[Mux.scala 27:72] + wire [5:0] _T_1300 = _T_1299 | _GEN_23; // @[Mux.scala 27:72] + wire [5:0] _GEN_24 = {{5'd0}, _T_1246}; // @[Mux.scala 27:72] + wire [5:0] _T_1301 = _T_1300 | _GEN_24; // @[Mux.scala 27:72] + wire [5:0] _GEN_25 = {{5'd0}, _T_1247}; // @[Mux.scala 27:72] + wire [5:0] _T_1302 = _T_1301 | _GEN_25; // @[Mux.scala 27:72] + wire [5:0] _GEN_26 = {{5'd0}, _T_1248}; // @[Mux.scala 27:72] + wire [5:0] _T_1303 = _T_1302 | _GEN_26; // @[Mux.scala 27:72] + wire [5:0] _GEN_27 = {{5'd0}, _T_1024}; // @[el2_dec_tlu_ctl.scala 2351:45] + wire [5:0] _T_1305 = _GEN_27 & _T_1303; // @[el2_dec_tlu_ctl.scala 2351:45] + wire _T_1307 = ~mcountinhibit[4]; // @[el2_dec_tlu_ctl.scala 2351:25] + reg [9:0] mhpme4; // @[Reg.scala 27:20] + wire _T_1308 = mhpme4 == 10'h1; // @[el2_dec_tlu_ctl.scala 2352:21] + wire _T_1310 = mhpme4 == 10'h2; // @[el2_dec_tlu_ctl.scala 2353:21] + wire _T_1312 = mhpme4 == 10'h3; // @[el2_dec_tlu_ctl.scala 2354:21] + wire _T_1314 = mhpme4 == 10'h4; // @[el2_dec_tlu_ctl.scala 2355:21] + wire _T_1318 = mhpme4 == 10'h5; // @[el2_dec_tlu_ctl.scala 2356:21] + wire _T_1324 = mhpme4 == 10'h6; // @[el2_dec_tlu_ctl.scala 2357:21] + wire _T_1329 = mhpme4 == 10'h7; // @[el2_dec_tlu_ctl.scala 2358:21] + wire _T_1331 = mhpme4 == 10'h8; // @[el2_dec_tlu_ctl.scala 2359:21] + wire _T_1333 = mhpme4 == 10'h1e; // @[el2_dec_tlu_ctl.scala 2360:21] + wire _T_1335 = mhpme4 == 10'h9; // @[el2_dec_tlu_ctl.scala 2361:21] + wire _T_1338 = mhpme4 == 10'ha; // @[el2_dec_tlu_ctl.scala 2362:21] + wire _T_1341 = mhpme4 == 10'hb; // @[el2_dec_tlu_ctl.scala 2363:21] + wire _T_1344 = mhpme4 == 10'hc; // @[el2_dec_tlu_ctl.scala 2364:21] + wire _T_1347 = mhpme4 == 10'hd; // @[el2_dec_tlu_ctl.scala 2365:21] + wire _T_1350 = mhpme4 == 10'he; // @[el2_dec_tlu_ctl.scala 2366:21] + wire _T_1351 = io_dec_tlu_packet_r_pmu_lsu_misaligned >> _T_1350; // @[el2_dec_tlu_ctl.scala 2366:7] + wire _T_1353 = _T_1060 & _T_1351; // @[el2_dec_tlu_ctl.scala 2365:89] + wire _T_1355 = _T_1353 & _T_1063; // @[el2_dec_tlu_ctl.scala 2366:45] + wire _T_1357 = _T_1355 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[el2_dec_tlu_ctl.scala 2366:77] + wire _T_1358 = mhpme4 == 10'hf; // @[el2_dec_tlu_ctl.scala 2368:21] + wire _T_1361 = mhpme4 == 10'h10; // @[el2_dec_tlu_ctl.scala 2369:21] + wire _T_1364 = mhpme4 == 10'h12; // @[el2_dec_tlu_ctl.scala 2370:21] + wire _T_1367 = mhpme4 == 10'h11; // @[el2_dec_tlu_ctl.scala 2371:21] + wire _T_1370 = mhpme4 == 10'h13; // @[el2_dec_tlu_ctl.scala 2372:21] + wire _T_1373 = mhpme4 == 10'h14; // @[el2_dec_tlu_ctl.scala 2373:21] + wire _T_1376 = mhpme4 == 10'h15; // @[el2_dec_tlu_ctl.scala 2374:21] + wire _T_1379 = mhpme4 == 10'h16; // @[el2_dec_tlu_ctl.scala 2375:21] + wire _T_1382 = mhpme4 == 10'h17; // @[el2_dec_tlu_ctl.scala 2376:21] + wire _T_1385 = mhpme4 == 10'h18; // @[el2_dec_tlu_ctl.scala 2377:21] + wire _T_1390 = mhpme4 == 10'h19; // @[el2_dec_tlu_ctl.scala 2378:21] + wire _T_1393 = mhpme4 == 10'h1a; // @[el2_dec_tlu_ctl.scala 2379:21] + wire _T_1396 = mhpme4 == 10'h1b; // @[el2_dec_tlu_ctl.scala 2380:21] + wire _T_1399 = mhpme4 == 10'h1c; // @[el2_dec_tlu_ctl.scala 2381:21] + wire _T_1403 = mhpme4 == 10'h1f; // @[el2_dec_tlu_ctl.scala 2383:21] + wire _T_1405 = mhpme4 == 10'h20; // @[el2_dec_tlu_ctl.scala 2384:21] + wire _T_1407 = mhpme4 == 10'h22; // @[el2_dec_tlu_ctl.scala 2385:21] + wire _T_1409 = mhpme4 == 10'h23; // @[el2_dec_tlu_ctl.scala 2386:21] + wire _T_1411 = mhpme4 == 10'h24; // @[el2_dec_tlu_ctl.scala 2387:21] + wire _T_1413 = mhpme4 == 10'h25; // @[el2_dec_tlu_ctl.scala 2388:21] + wire _T_1417 = mhpme4 == 10'h26; // @[el2_dec_tlu_ctl.scala 2389:21] + wire _T_1421 = mhpme4 == 10'h27; // @[el2_dec_tlu_ctl.scala 2390:21] + wire _T_1423 = mhpme4 == 10'h28; // @[el2_dec_tlu_ctl.scala 2391:21] + wire _T_1425 = mhpme4 == 10'h29; // @[el2_dec_tlu_ctl.scala 2392:21] + wire _T_1429 = mhpme4 == 10'h2a; // @[el2_dec_tlu_ctl.scala 2393:21] + wire _T_1431 = mhpme4 == 10'h2b; // @[el2_dec_tlu_ctl.scala 2394:21] + wire _T_1433 = mhpme4 == 10'h2c; // @[el2_dec_tlu_ctl.scala 2395:21] + wire _T_1435 = mhpme4 == 10'h2d; // @[el2_dec_tlu_ctl.scala 2396:21] + wire _T_1437 = mhpme4 == 10'h2e; // @[el2_dec_tlu_ctl.scala 2397:21] + wire _T_1439 = mhpme4 == 10'h2f; // @[el2_dec_tlu_ctl.scala 2398:21] + wire _T_1441 = mhpme4 == 10'h30; // @[el2_dec_tlu_ctl.scala 2399:21] + wire _T_1443 = mhpme4 == 10'h31; // @[el2_dec_tlu_ctl.scala 2400:21] + wire _T_1448 = mhpme4 == 10'h32; // @[el2_dec_tlu_ctl.scala 2401:21] + wire _T_1457 = mhpme4 == 10'h36; // @[el2_dec_tlu_ctl.scala 2402:21] + wire _T_1460 = mhpme4 == 10'h37; // @[el2_dec_tlu_ctl.scala 2403:21] + wire _T_1463 = mhpme4 == 10'h38; // @[el2_dec_tlu_ctl.scala 2404:21] + wire _T_1466 = mhpme4 == 10'h200; // @[el2_dec_tlu_ctl.scala 2406:21] + wire _T_1468 = mhpme4 == 10'h201; // @[el2_dec_tlu_ctl.scala 2407:21] + wire _T_1470 = mhpme4 == 10'h202; // @[el2_dec_tlu_ctl.scala 2408:21] + wire _T_1472 = mhpme4 == 10'h203; // @[el2_dec_tlu_ctl.scala 2409:21] + wire _T_1474 = mhpme4 == 10'h204; // @[el2_dec_tlu_ctl.scala 2410:21] + wire _T_1477 = _T_1310 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_1478 = _T_1312 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_1479 = _T_1314 & _T_1034; // @[Mux.scala 27:72] + wire _T_1480 = _T_1318 & _T_1040; // @[Mux.scala 27:72] + wire _T_1481 = _T_1324 & _T_1045; // @[Mux.scala 27:72] + wire _T_1482 = _T_1329 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_1483 = _T_1331 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_1484 = _T_1333 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_1485 = _T_1335 & _T_1054; // @[Mux.scala 27:72] + wire _T_1486 = _T_1338 & _T_1057; // @[Mux.scala 27:72] + wire _T_1487 = _T_1341 & _T_1060; // @[Mux.scala 27:72] + wire _T_1488 = _T_1344 & _T_1063; // @[Mux.scala 27:72] + wire _T_1489 = _T_1347 & _T_1357; // @[Mux.scala 27:72] + wire _T_1490 = _T_1358 & _T_1077; // @[Mux.scala 27:72] + wire _T_1491 = _T_1361 & _T_1080; // @[Mux.scala 27:72] + wire _T_1492 = _T_1364 & _T_1083; // @[Mux.scala 27:72] + wire _T_1493 = _T_1367 & _T_1086; // @[Mux.scala 27:72] + wire _T_1494 = _T_1370 & _T_1089; // @[Mux.scala 27:72] + wire _T_1495 = _T_1373 & _T_1092; // @[Mux.scala 27:72] + wire _T_1496 = _T_1376 & _T_1095; // @[Mux.scala 27:72] + wire _T_1497 = _T_1379 & _T_1098; // @[Mux.scala 27:72] + wire _T_1498 = _T_1382 & _T_1101; // @[Mux.scala 27:72] + wire _T_1499 = _T_1385 & _T_1106; // @[Mux.scala 27:72] + wire _T_1500 = _T_1390 & _T_1109; // @[Mux.scala 27:72] + wire _T_1501 = _T_1393 & _T_1112; // @[Mux.scala 27:72] + wire _T_1502 = _T_1396 & _T_1115; // @[Mux.scala 27:72] + wire _T_1503 = _T_1399 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_1505 = _T_1403 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_1506 = _T_1405 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_1507 = _T_1407 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_1508 = _T_1409 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_1509 = _T_1411 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_1510 = _T_1413 & _T_1133; // @[Mux.scala 27:72] + wire _T_1511 = _T_1417 & _T_1137; // @[Mux.scala 27:72] + wire _T_1512 = _T_1421 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_1513 = _T_1423 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_1514 = _T_1425 & _T_1145; // @[Mux.scala 27:72] + wire _T_1515 = _T_1429 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1516 = _T_1431 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1517 = _T_1433 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_1518 = _T_1435 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1519 = _T_1437 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1520 = _T_1439 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1521 = _T_1441 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1522 = _T_1443 & _T_1164; // @[Mux.scala 27:72] + wire [5:0] _T_1523 = _T_1448 ? _T_1173 : 6'h0; // @[Mux.scala 27:72] + wire _T_1524 = _T_1457 & _T_1176; // @[Mux.scala 27:72] + wire _T_1525 = _T_1460 & _T_1179; // @[Mux.scala 27:72] + wire _T_1526 = _T_1463 & _T_1182; // @[Mux.scala 27:72] + wire _T_1527 = _T_1466 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_1528 = _T_1468 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_1529 = _T_1470 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_1530 = _T_1472 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_1531 = _T_1474 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_1532 = _T_1308 | _T_1477; // @[Mux.scala 27:72] + wire _T_1533 = _T_1532 | _T_1478; // @[Mux.scala 27:72] + wire _T_1534 = _T_1533 | _T_1479; // @[Mux.scala 27:72] + wire _T_1535 = _T_1534 | _T_1480; // @[Mux.scala 27:72] + wire _T_1536 = _T_1535 | _T_1481; // @[Mux.scala 27:72] + wire _T_1537 = _T_1536 | _T_1482; // @[Mux.scala 27:72] + wire _T_1538 = _T_1537 | _T_1483; // @[Mux.scala 27:72] + wire _T_1539 = _T_1538 | _T_1484; // @[Mux.scala 27:72] + wire _T_1540 = _T_1539 | _T_1485; // @[Mux.scala 27:72] + wire _T_1541 = _T_1540 | _T_1486; // @[Mux.scala 27:72] + wire _T_1542 = _T_1541 | _T_1487; // @[Mux.scala 27:72] + wire _T_1543 = _T_1542 | _T_1488; // @[Mux.scala 27:72] + wire _T_1544 = _T_1543 | _T_1489; // @[Mux.scala 27:72] + wire _T_1545 = _T_1544 | _T_1490; // @[Mux.scala 27:72] + wire _T_1546 = _T_1545 | _T_1491; // @[Mux.scala 27:72] + wire _T_1547 = _T_1546 | _T_1492; // @[Mux.scala 27:72] + wire _T_1548 = _T_1547 | _T_1493; // @[Mux.scala 27:72] + wire _T_1549 = _T_1548 | _T_1494; // @[Mux.scala 27:72] + wire _T_1550 = _T_1549 | _T_1495; // @[Mux.scala 27:72] + wire _T_1551 = _T_1550 | _T_1496; // @[Mux.scala 27:72] + wire _T_1552 = _T_1551 | _T_1497; // @[Mux.scala 27:72] + wire _T_1553 = _T_1552 | _T_1498; // @[Mux.scala 27:72] + wire _T_1554 = _T_1553 | _T_1499; // @[Mux.scala 27:72] + wire _T_1555 = _T_1554 | _T_1500; // @[Mux.scala 27:72] + wire _T_1556 = _T_1555 | _T_1501; // @[Mux.scala 27:72] + wire _T_1557 = _T_1556 | _T_1502; // @[Mux.scala 27:72] + wire _T_1558 = _T_1557 | _T_1503; // @[Mux.scala 27:72] + wire _T_1559 = _T_1558 | _T_1484; // @[Mux.scala 27:72] + wire _T_1560 = _T_1559 | _T_1505; // @[Mux.scala 27:72] + wire _T_1561 = _T_1560 | _T_1506; // @[Mux.scala 27:72] + wire _T_1562 = _T_1561 | _T_1507; // @[Mux.scala 27:72] + wire _T_1563 = _T_1562 | _T_1508; // @[Mux.scala 27:72] + wire _T_1564 = _T_1563 | _T_1509; // @[Mux.scala 27:72] + wire _T_1565 = _T_1564 | _T_1510; // @[Mux.scala 27:72] + wire _T_1566 = _T_1565 | _T_1511; // @[Mux.scala 27:72] + wire _T_1567 = _T_1566 | _T_1512; // @[Mux.scala 27:72] + wire _T_1568 = _T_1567 | _T_1513; // @[Mux.scala 27:72] + wire _T_1569 = _T_1568 | _T_1514; // @[Mux.scala 27:72] + wire _T_1570 = _T_1569 | _T_1515; // @[Mux.scala 27:72] + wire _T_1571 = _T_1570 | _T_1516; // @[Mux.scala 27:72] + wire _T_1572 = _T_1571 | _T_1517; // @[Mux.scala 27:72] + wire _T_1573 = _T_1572 | _T_1518; // @[Mux.scala 27:72] + wire _T_1574 = _T_1573 | _T_1519; // @[Mux.scala 27:72] + wire _T_1575 = _T_1574 | _T_1520; // @[Mux.scala 27:72] + wire _T_1576 = _T_1575 | _T_1521; // @[Mux.scala 27:72] + wire _T_1577 = _T_1576 | _T_1522; // @[Mux.scala 27:72] + wire [5:0] _GEN_29 = {{5'd0}, _T_1577}; // @[Mux.scala 27:72] + wire [5:0] _T_1578 = _GEN_29 | _T_1523; // @[Mux.scala 27:72] + wire [5:0] _GEN_30 = {{5'd0}, _T_1524}; // @[Mux.scala 27:72] + wire [5:0] _T_1579 = _T_1578 | _GEN_30; // @[Mux.scala 27:72] + wire [5:0] _GEN_31 = {{5'd0}, _T_1525}; // @[Mux.scala 27:72] + wire [5:0] _T_1580 = _T_1579 | _GEN_31; // @[Mux.scala 27:72] + wire [5:0] _GEN_32 = {{5'd0}, _T_1526}; // @[Mux.scala 27:72] + wire [5:0] _T_1581 = _T_1580 | _GEN_32; // @[Mux.scala 27:72] + wire [5:0] _GEN_33 = {{5'd0}, _T_1527}; // @[Mux.scala 27:72] + wire [5:0] _T_1582 = _T_1581 | _GEN_33; // @[Mux.scala 27:72] + wire [5:0] _GEN_34 = {{5'd0}, _T_1528}; // @[Mux.scala 27:72] + wire [5:0] _T_1583 = _T_1582 | _GEN_34; // @[Mux.scala 27:72] + wire [5:0] _GEN_35 = {{5'd0}, _T_1529}; // @[Mux.scala 27:72] + wire [5:0] _T_1584 = _T_1583 | _GEN_35; // @[Mux.scala 27:72] + wire [5:0] _GEN_36 = {{5'd0}, _T_1530}; // @[Mux.scala 27:72] + wire [5:0] _T_1585 = _T_1584 | _GEN_36; // @[Mux.scala 27:72] + wire [5:0] _GEN_37 = {{5'd0}, _T_1531}; // @[Mux.scala 27:72] + wire [5:0] _T_1586 = _T_1585 | _GEN_37; // @[Mux.scala 27:72] + wire [5:0] _GEN_38 = {{5'd0}, _T_1307}; // @[el2_dec_tlu_ctl.scala 2351:45] + wire [5:0] _T_1588 = _GEN_38 & _T_1586; // @[el2_dec_tlu_ctl.scala 2351:45] + wire _T_1590 = ~mcountinhibit[5]; // @[el2_dec_tlu_ctl.scala 2351:25] + reg [9:0] mhpme5; // @[Reg.scala 27:20] + wire _T_1591 = mhpme5 == 10'h1; // @[el2_dec_tlu_ctl.scala 2352:21] + wire _T_1593 = mhpme5 == 10'h2; // @[el2_dec_tlu_ctl.scala 2353:21] + wire _T_1595 = mhpme5 == 10'h3; // @[el2_dec_tlu_ctl.scala 2354:21] + wire _T_1597 = mhpme5 == 10'h4; // @[el2_dec_tlu_ctl.scala 2355:21] + wire _T_1601 = mhpme5 == 10'h5; // @[el2_dec_tlu_ctl.scala 2356:21] + wire _T_1607 = mhpme5 == 10'h6; // @[el2_dec_tlu_ctl.scala 2357:21] + wire _T_1612 = mhpme5 == 10'h7; // @[el2_dec_tlu_ctl.scala 2358:21] + wire _T_1614 = mhpme5 == 10'h8; // @[el2_dec_tlu_ctl.scala 2359:21] + wire _T_1616 = mhpme5 == 10'h1e; // @[el2_dec_tlu_ctl.scala 2360:21] + wire _T_1618 = mhpme5 == 10'h9; // @[el2_dec_tlu_ctl.scala 2361:21] + wire _T_1621 = mhpme5 == 10'ha; // @[el2_dec_tlu_ctl.scala 2362:21] + wire _T_1624 = mhpme5 == 10'hb; // @[el2_dec_tlu_ctl.scala 2363:21] + wire _T_1627 = mhpme5 == 10'hc; // @[el2_dec_tlu_ctl.scala 2364:21] + wire _T_1630 = mhpme5 == 10'hd; // @[el2_dec_tlu_ctl.scala 2365:21] + wire _T_1633 = mhpme5 == 10'he; // @[el2_dec_tlu_ctl.scala 2366:21] + wire _T_1634 = io_dec_tlu_packet_r_pmu_lsu_misaligned >> _T_1633; // @[el2_dec_tlu_ctl.scala 2366:7] + wire _T_1636 = _T_1060 & _T_1634; // @[el2_dec_tlu_ctl.scala 2365:89] + wire _T_1638 = _T_1636 & _T_1063; // @[el2_dec_tlu_ctl.scala 2366:45] + wire _T_1640 = _T_1638 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[el2_dec_tlu_ctl.scala 2366:77] + wire _T_1641 = mhpme5 == 10'hf; // @[el2_dec_tlu_ctl.scala 2368:21] + wire _T_1644 = mhpme5 == 10'h10; // @[el2_dec_tlu_ctl.scala 2369:21] + wire _T_1647 = mhpme5 == 10'h12; // @[el2_dec_tlu_ctl.scala 2370:21] + wire _T_1650 = mhpme5 == 10'h11; // @[el2_dec_tlu_ctl.scala 2371:21] + wire _T_1653 = mhpme5 == 10'h13; // @[el2_dec_tlu_ctl.scala 2372:21] + wire _T_1656 = mhpme5 == 10'h14; // @[el2_dec_tlu_ctl.scala 2373:21] + wire _T_1659 = mhpme5 == 10'h15; // @[el2_dec_tlu_ctl.scala 2374:21] + wire _T_1662 = mhpme5 == 10'h16; // @[el2_dec_tlu_ctl.scala 2375:21] + wire _T_1665 = mhpme5 == 10'h17; // @[el2_dec_tlu_ctl.scala 2376:21] + wire _T_1668 = mhpme5 == 10'h18; // @[el2_dec_tlu_ctl.scala 2377:21] + wire _T_1673 = mhpme5 == 10'h19; // @[el2_dec_tlu_ctl.scala 2378:21] + wire _T_1676 = mhpme5 == 10'h1a; // @[el2_dec_tlu_ctl.scala 2379:21] + wire _T_1679 = mhpme5 == 10'h1b; // @[el2_dec_tlu_ctl.scala 2380:21] + wire _T_1682 = mhpme5 == 10'h1c; // @[el2_dec_tlu_ctl.scala 2381:21] + wire _T_1686 = mhpme5 == 10'h1f; // @[el2_dec_tlu_ctl.scala 2383:21] + wire _T_1688 = mhpme5 == 10'h20; // @[el2_dec_tlu_ctl.scala 2384:21] + wire _T_1690 = mhpme5 == 10'h22; // @[el2_dec_tlu_ctl.scala 2385:21] + wire _T_1692 = mhpme5 == 10'h23; // @[el2_dec_tlu_ctl.scala 2386:21] + wire _T_1694 = mhpme5 == 10'h24; // @[el2_dec_tlu_ctl.scala 2387:21] + wire _T_1696 = mhpme5 == 10'h25; // @[el2_dec_tlu_ctl.scala 2388:21] + wire _T_1700 = mhpme5 == 10'h26; // @[el2_dec_tlu_ctl.scala 2389:21] + wire _T_1704 = mhpme5 == 10'h27; // @[el2_dec_tlu_ctl.scala 2390:21] + wire _T_1706 = mhpme5 == 10'h28; // @[el2_dec_tlu_ctl.scala 2391:21] + wire _T_1708 = mhpme5 == 10'h29; // @[el2_dec_tlu_ctl.scala 2392:21] + wire _T_1712 = mhpme5 == 10'h2a; // @[el2_dec_tlu_ctl.scala 2393:21] + wire _T_1714 = mhpme5 == 10'h2b; // @[el2_dec_tlu_ctl.scala 2394:21] + wire _T_1716 = mhpme5 == 10'h2c; // @[el2_dec_tlu_ctl.scala 2395:21] + wire _T_1718 = mhpme5 == 10'h2d; // @[el2_dec_tlu_ctl.scala 2396:21] + wire _T_1720 = mhpme5 == 10'h2e; // @[el2_dec_tlu_ctl.scala 2397:21] + wire _T_1722 = mhpme5 == 10'h2f; // @[el2_dec_tlu_ctl.scala 2398:21] + wire _T_1724 = mhpme5 == 10'h30; // @[el2_dec_tlu_ctl.scala 2399:21] + wire _T_1726 = mhpme5 == 10'h31; // @[el2_dec_tlu_ctl.scala 2400:21] + wire _T_1731 = mhpme5 == 10'h32; // @[el2_dec_tlu_ctl.scala 2401:21] + wire _T_1740 = mhpme5 == 10'h36; // @[el2_dec_tlu_ctl.scala 2402:21] + wire _T_1743 = mhpme5 == 10'h37; // @[el2_dec_tlu_ctl.scala 2403:21] + wire _T_1746 = mhpme5 == 10'h38; // @[el2_dec_tlu_ctl.scala 2404:21] + wire _T_1749 = mhpme5 == 10'h200; // @[el2_dec_tlu_ctl.scala 2406:21] + wire _T_1751 = mhpme5 == 10'h201; // @[el2_dec_tlu_ctl.scala 2407:21] + wire _T_1753 = mhpme5 == 10'h202; // @[el2_dec_tlu_ctl.scala 2408:21] + wire _T_1755 = mhpme5 == 10'h203; // @[el2_dec_tlu_ctl.scala 2409:21] + wire _T_1757 = mhpme5 == 10'h204; // @[el2_dec_tlu_ctl.scala 2410:21] + wire _T_1760 = _T_1593 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_1761 = _T_1595 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_1762 = _T_1597 & _T_1034; // @[Mux.scala 27:72] + wire _T_1763 = _T_1601 & _T_1040; // @[Mux.scala 27:72] + wire _T_1764 = _T_1607 & _T_1045; // @[Mux.scala 27:72] + wire _T_1765 = _T_1612 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_1766 = _T_1614 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_1767 = _T_1616 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_1768 = _T_1618 & _T_1054; // @[Mux.scala 27:72] + wire _T_1769 = _T_1621 & _T_1057; // @[Mux.scala 27:72] + wire _T_1770 = _T_1624 & _T_1060; // @[Mux.scala 27:72] + wire _T_1771 = _T_1627 & _T_1063; // @[Mux.scala 27:72] + wire _T_1772 = _T_1630 & _T_1640; // @[Mux.scala 27:72] + wire _T_1773 = _T_1641 & _T_1077; // @[Mux.scala 27:72] + wire _T_1774 = _T_1644 & _T_1080; // @[Mux.scala 27:72] + wire _T_1775 = _T_1647 & _T_1083; // @[Mux.scala 27:72] + wire _T_1776 = _T_1650 & _T_1086; // @[Mux.scala 27:72] + wire _T_1777 = _T_1653 & _T_1089; // @[Mux.scala 27:72] + wire _T_1778 = _T_1656 & _T_1092; // @[Mux.scala 27:72] + wire _T_1779 = _T_1659 & _T_1095; // @[Mux.scala 27:72] + wire _T_1780 = _T_1662 & _T_1098; // @[Mux.scala 27:72] + wire _T_1781 = _T_1665 & _T_1101; // @[Mux.scala 27:72] + wire _T_1782 = _T_1668 & _T_1106; // @[Mux.scala 27:72] + wire _T_1783 = _T_1673 & _T_1109; // @[Mux.scala 27:72] + wire _T_1784 = _T_1676 & _T_1112; // @[Mux.scala 27:72] + wire _T_1785 = _T_1679 & _T_1115; // @[Mux.scala 27:72] + wire _T_1786 = _T_1682 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_1788 = _T_1686 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_1789 = _T_1688 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_1790 = _T_1690 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_1791 = _T_1692 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_1792 = _T_1694 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_1793 = _T_1696 & _T_1133; // @[Mux.scala 27:72] + wire _T_1794 = _T_1700 & _T_1137; // @[Mux.scala 27:72] + wire _T_1795 = _T_1704 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_1796 = _T_1706 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_1797 = _T_1708 & _T_1145; // @[Mux.scala 27:72] + wire _T_1798 = _T_1712 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1799 = _T_1714 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1800 = _T_1716 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_1801 = _T_1718 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1802 = _T_1720 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1803 = _T_1722 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1804 = _T_1724 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1805 = _T_1726 & _T_1164; // @[Mux.scala 27:72] + wire [5:0] _T_1806 = _T_1731 ? _T_1173 : 6'h0; // @[Mux.scala 27:72] + wire _T_1807 = _T_1740 & _T_1176; // @[Mux.scala 27:72] + wire _T_1808 = _T_1743 & _T_1179; // @[Mux.scala 27:72] + wire _T_1809 = _T_1746 & _T_1182; // @[Mux.scala 27:72] + wire _T_1810 = _T_1749 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_1811 = _T_1751 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_1812 = _T_1753 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_1813 = _T_1755 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_1814 = _T_1757 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_1815 = _T_1591 | _T_1760; // @[Mux.scala 27:72] + wire _T_1816 = _T_1815 | _T_1761; // @[Mux.scala 27:72] + wire _T_1817 = _T_1816 | _T_1762; // @[Mux.scala 27:72] + wire _T_1818 = _T_1817 | _T_1763; // @[Mux.scala 27:72] + wire _T_1819 = _T_1818 | _T_1764; // @[Mux.scala 27:72] + wire _T_1820 = _T_1819 | _T_1765; // @[Mux.scala 27:72] + wire _T_1821 = _T_1820 | _T_1766; // @[Mux.scala 27:72] + wire _T_1822 = _T_1821 | _T_1767; // @[Mux.scala 27:72] + wire _T_1823 = _T_1822 | _T_1768; // @[Mux.scala 27:72] + wire _T_1824 = _T_1823 | _T_1769; // @[Mux.scala 27:72] + wire _T_1825 = _T_1824 | _T_1770; // @[Mux.scala 27:72] + wire _T_1826 = _T_1825 | _T_1771; // @[Mux.scala 27:72] + wire _T_1827 = _T_1826 | _T_1772; // @[Mux.scala 27:72] + wire _T_1828 = _T_1827 | _T_1773; // @[Mux.scala 27:72] + wire _T_1829 = _T_1828 | _T_1774; // @[Mux.scala 27:72] + wire _T_1830 = _T_1829 | _T_1775; // @[Mux.scala 27:72] + wire _T_1831 = _T_1830 | _T_1776; // @[Mux.scala 27:72] + wire _T_1832 = _T_1831 | _T_1777; // @[Mux.scala 27:72] + wire _T_1833 = _T_1832 | _T_1778; // @[Mux.scala 27:72] + wire _T_1834 = _T_1833 | _T_1779; // @[Mux.scala 27:72] + wire _T_1835 = _T_1834 | _T_1780; // @[Mux.scala 27:72] + wire _T_1836 = _T_1835 | _T_1781; // @[Mux.scala 27:72] + wire _T_1837 = _T_1836 | _T_1782; // @[Mux.scala 27:72] + wire _T_1838 = _T_1837 | _T_1783; // @[Mux.scala 27:72] + wire _T_1839 = _T_1838 | _T_1784; // @[Mux.scala 27:72] + wire _T_1840 = _T_1839 | _T_1785; // @[Mux.scala 27:72] + wire _T_1841 = _T_1840 | _T_1786; // @[Mux.scala 27:72] + wire _T_1842 = _T_1841 | _T_1767; // @[Mux.scala 27:72] + wire _T_1843 = _T_1842 | _T_1788; // @[Mux.scala 27:72] + wire _T_1844 = _T_1843 | _T_1789; // @[Mux.scala 27:72] + wire _T_1845 = _T_1844 | _T_1790; // @[Mux.scala 27:72] + wire _T_1846 = _T_1845 | _T_1791; // @[Mux.scala 27:72] + wire _T_1847 = _T_1846 | _T_1792; // @[Mux.scala 27:72] + wire _T_1848 = _T_1847 | _T_1793; // @[Mux.scala 27:72] + wire _T_1849 = _T_1848 | _T_1794; // @[Mux.scala 27:72] + wire _T_1850 = _T_1849 | _T_1795; // @[Mux.scala 27:72] + wire _T_1851 = _T_1850 | _T_1796; // @[Mux.scala 27:72] + wire _T_1852 = _T_1851 | _T_1797; // @[Mux.scala 27:72] + wire _T_1853 = _T_1852 | _T_1798; // @[Mux.scala 27:72] + wire _T_1854 = _T_1853 | _T_1799; // @[Mux.scala 27:72] + wire _T_1855 = _T_1854 | _T_1800; // @[Mux.scala 27:72] + wire _T_1856 = _T_1855 | _T_1801; // @[Mux.scala 27:72] + wire _T_1857 = _T_1856 | _T_1802; // @[Mux.scala 27:72] + wire _T_1858 = _T_1857 | _T_1803; // @[Mux.scala 27:72] + wire _T_1859 = _T_1858 | _T_1804; // @[Mux.scala 27:72] + wire _T_1860 = _T_1859 | _T_1805; // @[Mux.scala 27:72] + wire [5:0] _GEN_40 = {{5'd0}, _T_1860}; // @[Mux.scala 27:72] + wire [5:0] _T_1861 = _GEN_40 | _T_1806; // @[Mux.scala 27:72] + wire [5:0] _GEN_41 = {{5'd0}, _T_1807}; // @[Mux.scala 27:72] + wire [5:0] _T_1862 = _T_1861 | _GEN_41; // @[Mux.scala 27:72] + wire [5:0] _GEN_42 = {{5'd0}, _T_1808}; // @[Mux.scala 27:72] + wire [5:0] _T_1863 = _T_1862 | _GEN_42; // @[Mux.scala 27:72] + wire [5:0] _GEN_43 = {{5'd0}, _T_1809}; // @[Mux.scala 27:72] + wire [5:0] _T_1864 = _T_1863 | _GEN_43; // @[Mux.scala 27:72] + wire [5:0] _GEN_44 = {{5'd0}, _T_1810}; // @[Mux.scala 27:72] + wire [5:0] _T_1865 = _T_1864 | _GEN_44; // @[Mux.scala 27:72] + wire [5:0] _GEN_45 = {{5'd0}, _T_1811}; // @[Mux.scala 27:72] + wire [5:0] _T_1866 = _T_1865 | _GEN_45; // @[Mux.scala 27:72] + wire [5:0] _GEN_46 = {{5'd0}, _T_1812}; // @[Mux.scala 27:72] + wire [5:0] _T_1867 = _T_1866 | _GEN_46; // @[Mux.scala 27:72] + wire [5:0] _GEN_47 = {{5'd0}, _T_1813}; // @[Mux.scala 27:72] + wire [5:0] _T_1868 = _T_1867 | _GEN_47; // @[Mux.scala 27:72] + wire [5:0] _GEN_48 = {{5'd0}, _T_1814}; // @[Mux.scala 27:72] + wire [5:0] _T_1869 = _T_1868 | _GEN_48; // @[Mux.scala 27:72] + wire [5:0] _GEN_49 = {{5'd0}, _T_1590}; // @[el2_dec_tlu_ctl.scala 2351:45] + wire [5:0] _T_1871 = _GEN_49 & _T_1869; // @[el2_dec_tlu_ctl.scala 2351:45] + wire _T_1873 = ~mcountinhibit[6]; // @[el2_dec_tlu_ctl.scala 2351:25] + reg [9:0] mhpme6; // @[Reg.scala 27:20] + wire _T_1874 = mhpme6 == 10'h1; // @[el2_dec_tlu_ctl.scala 2352:21] + wire _T_1876 = mhpme6 == 10'h2; // @[el2_dec_tlu_ctl.scala 2353:21] + wire _T_1878 = mhpme6 == 10'h3; // @[el2_dec_tlu_ctl.scala 2354:21] + wire _T_1880 = mhpme6 == 10'h4; // @[el2_dec_tlu_ctl.scala 2355:21] + wire _T_1884 = mhpme6 == 10'h5; // @[el2_dec_tlu_ctl.scala 2356:21] + wire _T_1890 = mhpme6 == 10'h6; // @[el2_dec_tlu_ctl.scala 2357:21] + wire _T_1895 = mhpme6 == 10'h7; // @[el2_dec_tlu_ctl.scala 2358:21] + wire _T_1897 = mhpme6 == 10'h8; // @[el2_dec_tlu_ctl.scala 2359:21] + wire _T_1899 = mhpme6 == 10'h1e; // @[el2_dec_tlu_ctl.scala 2360:21] + wire _T_1901 = mhpme6 == 10'h9; // @[el2_dec_tlu_ctl.scala 2361:21] + wire _T_1904 = mhpme6 == 10'ha; // @[el2_dec_tlu_ctl.scala 2362:21] + wire _T_1907 = mhpme6 == 10'hb; // @[el2_dec_tlu_ctl.scala 2363:21] + wire _T_1910 = mhpme6 == 10'hc; // @[el2_dec_tlu_ctl.scala 2364:21] + wire _T_1913 = mhpme6 == 10'hd; // @[el2_dec_tlu_ctl.scala 2365:21] + wire _T_1916 = mhpme6 == 10'he; // @[el2_dec_tlu_ctl.scala 2366:21] + wire _T_1917 = io_dec_tlu_packet_r_pmu_lsu_misaligned >> _T_1916; // @[el2_dec_tlu_ctl.scala 2366:7] + wire _T_1919 = _T_1060 & _T_1917; // @[el2_dec_tlu_ctl.scala 2365:89] + wire _T_1921 = _T_1919 & _T_1063; // @[el2_dec_tlu_ctl.scala 2366:45] + wire _T_1923 = _T_1921 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[el2_dec_tlu_ctl.scala 2366:77] + wire _T_1924 = mhpme6 == 10'hf; // @[el2_dec_tlu_ctl.scala 2368:21] + wire _T_1927 = mhpme6 == 10'h10; // @[el2_dec_tlu_ctl.scala 2369:21] + wire _T_1930 = mhpme6 == 10'h12; // @[el2_dec_tlu_ctl.scala 2370:21] + wire _T_1933 = mhpme6 == 10'h11; // @[el2_dec_tlu_ctl.scala 2371:21] + wire _T_1936 = mhpme6 == 10'h13; // @[el2_dec_tlu_ctl.scala 2372:21] + wire _T_1939 = mhpme6 == 10'h14; // @[el2_dec_tlu_ctl.scala 2373:21] + wire _T_1942 = mhpme6 == 10'h15; // @[el2_dec_tlu_ctl.scala 2374:21] + wire _T_1945 = mhpme6 == 10'h16; // @[el2_dec_tlu_ctl.scala 2375:21] + wire _T_1948 = mhpme6 == 10'h17; // @[el2_dec_tlu_ctl.scala 2376:21] + wire _T_1951 = mhpme6 == 10'h18; // @[el2_dec_tlu_ctl.scala 2377:21] + wire _T_1956 = mhpme6 == 10'h19; // @[el2_dec_tlu_ctl.scala 2378:21] + wire _T_1959 = mhpme6 == 10'h1a; // @[el2_dec_tlu_ctl.scala 2379:21] + wire _T_1962 = mhpme6 == 10'h1b; // @[el2_dec_tlu_ctl.scala 2380:21] + wire _T_1965 = mhpme6 == 10'h1c; // @[el2_dec_tlu_ctl.scala 2381:21] + wire _T_1969 = mhpme6 == 10'h1f; // @[el2_dec_tlu_ctl.scala 2383:21] + wire _T_1971 = mhpme6 == 10'h20; // @[el2_dec_tlu_ctl.scala 2384:21] + wire _T_1973 = mhpme6 == 10'h22; // @[el2_dec_tlu_ctl.scala 2385:21] + wire _T_1975 = mhpme6 == 10'h23; // @[el2_dec_tlu_ctl.scala 2386:21] + wire _T_1977 = mhpme6 == 10'h24; // @[el2_dec_tlu_ctl.scala 2387:21] + wire _T_1979 = mhpme6 == 10'h25; // @[el2_dec_tlu_ctl.scala 2388:21] + wire _T_1983 = mhpme6 == 10'h26; // @[el2_dec_tlu_ctl.scala 2389:21] + wire _T_1987 = mhpme6 == 10'h27; // @[el2_dec_tlu_ctl.scala 2390:21] + wire _T_1989 = mhpme6 == 10'h28; // @[el2_dec_tlu_ctl.scala 2391:21] + wire _T_1991 = mhpme6 == 10'h29; // @[el2_dec_tlu_ctl.scala 2392:21] + wire _T_1995 = mhpme6 == 10'h2a; // @[el2_dec_tlu_ctl.scala 2393:21] + wire _T_1997 = mhpme6 == 10'h2b; // @[el2_dec_tlu_ctl.scala 2394:21] + wire _T_1999 = mhpme6 == 10'h2c; // @[el2_dec_tlu_ctl.scala 2395:21] + wire _T_2001 = mhpme6 == 10'h2d; // @[el2_dec_tlu_ctl.scala 2396:21] + wire _T_2003 = mhpme6 == 10'h2e; // @[el2_dec_tlu_ctl.scala 2397:21] + wire _T_2005 = mhpme6 == 10'h2f; // @[el2_dec_tlu_ctl.scala 2398:21] + wire _T_2007 = mhpme6 == 10'h30; // @[el2_dec_tlu_ctl.scala 2399:21] + wire _T_2009 = mhpme6 == 10'h31; // @[el2_dec_tlu_ctl.scala 2400:21] + wire _T_2014 = mhpme6 == 10'h32; // @[el2_dec_tlu_ctl.scala 2401:21] + wire _T_2023 = mhpme6 == 10'h36; // @[el2_dec_tlu_ctl.scala 2402:21] + wire _T_2026 = mhpme6 == 10'h37; // @[el2_dec_tlu_ctl.scala 2403:21] + wire _T_2029 = mhpme6 == 10'h38; // @[el2_dec_tlu_ctl.scala 2404:21] + wire _T_2032 = mhpme6 == 10'h200; // @[el2_dec_tlu_ctl.scala 2406:21] + wire _T_2034 = mhpme6 == 10'h201; // @[el2_dec_tlu_ctl.scala 2407:21] + wire _T_2036 = mhpme6 == 10'h202; // @[el2_dec_tlu_ctl.scala 2408:21] + wire _T_2038 = mhpme6 == 10'h203; // @[el2_dec_tlu_ctl.scala 2409:21] + wire _T_2040 = mhpme6 == 10'h204; // @[el2_dec_tlu_ctl.scala 2410:21] + wire _T_2043 = _T_1876 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_2044 = _T_1878 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_2045 = _T_1880 & _T_1034; // @[Mux.scala 27:72] + wire _T_2046 = _T_1884 & _T_1040; // @[Mux.scala 27:72] + wire _T_2047 = _T_1890 & _T_1045; // @[Mux.scala 27:72] + wire _T_2048 = _T_1895 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_2049 = _T_1897 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_2050 = _T_1899 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_2051 = _T_1901 & _T_1054; // @[Mux.scala 27:72] + wire _T_2052 = _T_1904 & _T_1057; // @[Mux.scala 27:72] + wire _T_2053 = _T_1907 & _T_1060; // @[Mux.scala 27:72] + wire _T_2054 = _T_1910 & _T_1063; // @[Mux.scala 27:72] + wire _T_2055 = _T_1913 & _T_1923; // @[Mux.scala 27:72] + wire _T_2056 = _T_1924 & _T_1077; // @[Mux.scala 27:72] + wire _T_2057 = _T_1927 & _T_1080; // @[Mux.scala 27:72] + wire _T_2058 = _T_1930 & _T_1083; // @[Mux.scala 27:72] + wire _T_2059 = _T_1933 & _T_1086; // @[Mux.scala 27:72] + wire _T_2060 = _T_1936 & _T_1089; // @[Mux.scala 27:72] + wire _T_2061 = _T_1939 & _T_1092; // @[Mux.scala 27:72] + wire _T_2062 = _T_1942 & _T_1095; // @[Mux.scala 27:72] + wire _T_2063 = _T_1945 & _T_1098; // @[Mux.scala 27:72] + wire _T_2064 = _T_1948 & _T_1101; // @[Mux.scala 27:72] + wire _T_2065 = _T_1951 & _T_1106; // @[Mux.scala 27:72] + wire _T_2066 = _T_1956 & _T_1109; // @[Mux.scala 27:72] + wire _T_2067 = _T_1959 & _T_1112; // @[Mux.scala 27:72] + wire _T_2068 = _T_1962 & _T_1115; // @[Mux.scala 27:72] + wire _T_2069 = _T_1965 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_2071 = _T_1969 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_2072 = _T_1971 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_2073 = _T_1973 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_2074 = _T_1975 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_2075 = _T_1977 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_2076 = _T_1979 & _T_1133; // @[Mux.scala 27:72] + wire _T_2077 = _T_1983 & _T_1137; // @[Mux.scala 27:72] + wire _T_2078 = _T_1987 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_2079 = _T_1989 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_2080 = _T_1991 & _T_1145; // @[Mux.scala 27:72] + wire _T_2081 = _T_1995 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_2082 = _T_1997 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_2083 = _T_1999 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_2084 = _T_2001 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_2085 = _T_2003 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_2086 = _T_2005 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_2087 = _T_2007 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_2088 = _T_2009 & _T_1164; // @[Mux.scala 27:72] + wire [5:0] _T_2089 = _T_2014 ? _T_1173 : 6'h0; // @[Mux.scala 27:72] + wire _T_2090 = _T_2023 & _T_1176; // @[Mux.scala 27:72] + wire _T_2091 = _T_2026 & _T_1179; // @[Mux.scala 27:72] + wire _T_2092 = _T_2029 & _T_1182; // @[Mux.scala 27:72] + wire _T_2093 = _T_2032 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_2094 = _T_2034 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_2095 = _T_2036 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_2096 = _T_2038 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_2097 = _T_2040 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_2098 = _T_1874 | _T_2043; // @[Mux.scala 27:72] + wire _T_2099 = _T_2098 | _T_2044; // @[Mux.scala 27:72] + wire _T_2100 = _T_2099 | _T_2045; // @[Mux.scala 27:72] + wire _T_2101 = _T_2100 | _T_2046; // @[Mux.scala 27:72] + wire _T_2102 = _T_2101 | _T_2047; // @[Mux.scala 27:72] + wire _T_2103 = _T_2102 | _T_2048; // @[Mux.scala 27:72] + wire _T_2104 = _T_2103 | _T_2049; // @[Mux.scala 27:72] + wire _T_2105 = _T_2104 | _T_2050; // @[Mux.scala 27:72] + wire _T_2106 = _T_2105 | _T_2051; // @[Mux.scala 27:72] + wire _T_2107 = _T_2106 | _T_2052; // @[Mux.scala 27:72] + wire _T_2108 = _T_2107 | _T_2053; // @[Mux.scala 27:72] + wire _T_2109 = _T_2108 | _T_2054; // @[Mux.scala 27:72] + wire _T_2110 = _T_2109 | _T_2055; // @[Mux.scala 27:72] + wire _T_2111 = _T_2110 | _T_2056; // @[Mux.scala 27:72] + wire _T_2112 = _T_2111 | _T_2057; // @[Mux.scala 27:72] + wire _T_2113 = _T_2112 | _T_2058; // @[Mux.scala 27:72] + wire _T_2114 = _T_2113 | _T_2059; // @[Mux.scala 27:72] + wire _T_2115 = _T_2114 | _T_2060; // @[Mux.scala 27:72] + wire _T_2116 = _T_2115 | _T_2061; // @[Mux.scala 27:72] + wire _T_2117 = _T_2116 | _T_2062; // @[Mux.scala 27:72] + wire _T_2118 = _T_2117 | _T_2063; // @[Mux.scala 27:72] + wire _T_2119 = _T_2118 | _T_2064; // @[Mux.scala 27:72] + wire _T_2120 = _T_2119 | _T_2065; // @[Mux.scala 27:72] + wire _T_2121 = _T_2120 | _T_2066; // @[Mux.scala 27:72] + wire _T_2122 = _T_2121 | _T_2067; // @[Mux.scala 27:72] + wire _T_2123 = _T_2122 | _T_2068; // @[Mux.scala 27:72] + wire _T_2124 = _T_2123 | _T_2069; // @[Mux.scala 27:72] + wire _T_2125 = _T_2124 | _T_2050; // @[Mux.scala 27:72] + wire _T_2126 = _T_2125 | _T_2071; // @[Mux.scala 27:72] + wire _T_2127 = _T_2126 | _T_2072; // @[Mux.scala 27:72] + wire _T_2128 = _T_2127 | _T_2073; // @[Mux.scala 27:72] + wire _T_2129 = _T_2128 | _T_2074; // @[Mux.scala 27:72] + wire _T_2130 = _T_2129 | _T_2075; // @[Mux.scala 27:72] + wire _T_2131 = _T_2130 | _T_2076; // @[Mux.scala 27:72] + wire _T_2132 = _T_2131 | _T_2077; // @[Mux.scala 27:72] + wire _T_2133 = _T_2132 | _T_2078; // @[Mux.scala 27:72] + wire _T_2134 = _T_2133 | _T_2079; // @[Mux.scala 27:72] + wire _T_2135 = _T_2134 | _T_2080; // @[Mux.scala 27:72] + wire _T_2136 = _T_2135 | _T_2081; // @[Mux.scala 27:72] + wire _T_2137 = _T_2136 | _T_2082; // @[Mux.scala 27:72] + wire _T_2138 = _T_2137 | _T_2083; // @[Mux.scala 27:72] + wire _T_2139 = _T_2138 | _T_2084; // @[Mux.scala 27:72] + wire _T_2140 = _T_2139 | _T_2085; // @[Mux.scala 27:72] + wire _T_2141 = _T_2140 | _T_2086; // @[Mux.scala 27:72] + wire _T_2142 = _T_2141 | _T_2087; // @[Mux.scala 27:72] + wire _T_2143 = _T_2142 | _T_2088; // @[Mux.scala 27:72] + wire [5:0] _GEN_51 = {{5'd0}, _T_2143}; // @[Mux.scala 27:72] + wire [5:0] _T_2144 = _GEN_51 | _T_2089; // @[Mux.scala 27:72] + wire [5:0] _GEN_52 = {{5'd0}, _T_2090}; // @[Mux.scala 27:72] + wire [5:0] _T_2145 = _T_2144 | _GEN_52; // @[Mux.scala 27:72] + wire [5:0] _GEN_53 = {{5'd0}, _T_2091}; // @[Mux.scala 27:72] + wire [5:0] _T_2146 = _T_2145 | _GEN_53; // @[Mux.scala 27:72] + wire [5:0] _GEN_54 = {{5'd0}, _T_2092}; // @[Mux.scala 27:72] + wire [5:0] _T_2147 = _T_2146 | _GEN_54; // @[Mux.scala 27:72] + wire [5:0] _GEN_55 = {{5'd0}, _T_2093}; // @[Mux.scala 27:72] + wire [5:0] _T_2148 = _T_2147 | _GEN_55; // @[Mux.scala 27:72] + wire [5:0] _GEN_56 = {{5'd0}, _T_2094}; // @[Mux.scala 27:72] + wire [5:0] _T_2149 = _T_2148 | _GEN_56; // @[Mux.scala 27:72] + wire [5:0] _GEN_57 = {{5'd0}, _T_2095}; // @[Mux.scala 27:72] + wire [5:0] _T_2150 = _T_2149 | _GEN_57; // @[Mux.scala 27:72] + wire [5:0] _GEN_58 = {{5'd0}, _T_2096}; // @[Mux.scala 27:72] + wire [5:0] _T_2151 = _T_2150 | _GEN_58; // @[Mux.scala 27:72] + wire [5:0] _GEN_59 = {{5'd0}, _T_2097}; // @[Mux.scala 27:72] + wire [5:0] _T_2152 = _T_2151 | _GEN_59; // @[Mux.scala 27:72] + wire [5:0] _GEN_60 = {{5'd0}, _T_1873}; // @[el2_dec_tlu_ctl.scala 2351:45] + wire [5:0] _T_2154 = _GEN_60 & _T_2152; // @[el2_dec_tlu_ctl.scala 2351:45] + reg mhpmc_inc_r_d1_0; // @[el2_dec_tlu_ctl.scala 2413:54] + reg mhpmc_inc_r_d1_1; // @[el2_dec_tlu_ctl.scala 2414:54] + reg mhpmc_inc_r_d1_2; // @[el2_dec_tlu_ctl.scala 2415:54] + reg mhpmc_inc_r_d1_3; // @[el2_dec_tlu_ctl.scala 2416:54] + reg perfcnt_halted_d1; // @[el2_dec_tlu_ctl.scala 2417:57] + wire perfcnt_halted = _T_83 | io_dec_tlu_pmu_fw_halted; // @[el2_dec_tlu_ctl.scala 2420:68] + wire _T_2164 = ~_T_83; // @[el2_dec_tlu_ctl.scala 2421:38] + wire [3:0] _T_2166 = _T_2164 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_2173 = {mhpme6[9],mhpme5[9],mhpme4[9],mhpme3[9]}; // @[Cat.scala 29:58] + wire [3:0] perfcnt_during_sleep = _T_2166 & _T_2173; // @[el2_dec_tlu_ctl.scala 2421:87] + wire _T_2175 = ~perfcnt_during_sleep[0]; // @[el2_dec_tlu_ctl.scala 2423:68] + wire _T_2176 = perfcnt_halted_d1 & _T_2175; // @[el2_dec_tlu_ctl.scala 2423:66] + wire _T_2177 = ~_T_2176; // @[el2_dec_tlu_ctl.scala 2423:46] + wire _T_2180 = ~perfcnt_during_sleep[1]; // @[el2_dec_tlu_ctl.scala 2424:68] + wire _T_2181 = perfcnt_halted_d1 & _T_2180; // @[el2_dec_tlu_ctl.scala 2424:66] + wire _T_2182 = ~_T_2181; // @[el2_dec_tlu_ctl.scala 2424:46] + wire _T_2185 = ~perfcnt_during_sleep[2]; // @[el2_dec_tlu_ctl.scala 2425:68] + wire _T_2186 = perfcnt_halted_d1 & _T_2185; // @[el2_dec_tlu_ctl.scala 2425:66] + wire _T_2187 = ~_T_2186; // @[el2_dec_tlu_ctl.scala 2425:46] + wire _T_2190 = ~perfcnt_during_sleep[3]; // @[el2_dec_tlu_ctl.scala 2426:68] + wire _T_2191 = perfcnt_halted_d1 & _T_2190; // @[el2_dec_tlu_ctl.scala 2426:66] + wire _T_2192 = ~_T_2191; // @[el2_dec_tlu_ctl.scala 2426:46] + wire _T_2195 = io_dec_csr_wraddr_r == 12'hb03; // @[el2_dec_tlu_ctl.scala 2432:73] + wire mhpmc3_wr_en0 = io_dec_csr_wen_r_mod & _T_2195; // @[el2_dec_tlu_ctl.scala 2432:44] + wire _T_2196 = ~perfcnt_halted; // @[el2_dec_tlu_ctl.scala 2433:24] + wire _T_2198 = _T_2196 | perfcnt_during_sleep[0]; // @[el2_dec_tlu_ctl.scala 2433:40] + wire mhpmc_inc_r_0 = _T_1305[0]; // @[el2_dec_tlu_ctl.scala 2346:25 el2_dec_tlu_ctl.scala 2351:20] + wire _T_2199 = |mhpmc_inc_r_0; // @[el2_dec_tlu_ctl.scala 2433:87] + wire mhpmc3_wr_en1 = _T_2198 & _T_2199; // @[el2_dec_tlu_ctl.scala 2433:67] + reg [31:0] mhpmc3h; // @[el2_lib.scala 514:16] + reg [31:0] mhpmc3; // @[el2_lib.scala 514:16] + wire [63:0] _T_2202 = {mhpmc3h,mhpmc3}; // @[Cat.scala 29:58] + wire [63:0] _T_2203 = {63'h0,mhpmc_inc_r_0}; // @[Cat.scala 29:58] + wire [63:0] mhpmc3_incr = _T_2202 + _T_2203; // @[el2_dec_tlu_ctl.scala 2437:50] + wire _T_2211 = io_dec_csr_wraddr_r == 12'hb83; // @[el2_dec_tlu_ctl.scala 2442:74] + wire mhpmc3h_wr_en0 = io_dec_csr_wen_r_mod & _T_2211; // @[el2_dec_tlu_ctl.scala 2442:45] + wire _T_2217 = io_dec_csr_wraddr_r == 12'hb04; // @[el2_dec_tlu_ctl.scala 2451:73] + wire mhpmc4_wr_en0 = io_dec_csr_wen_r_mod & _T_2217; // @[el2_dec_tlu_ctl.scala 2451:44] + wire _T_2220 = _T_2196 | perfcnt_during_sleep[1]; // @[el2_dec_tlu_ctl.scala 2452:40] + wire mhpmc_inc_r_1 = _T_1588[0]; // @[el2_dec_tlu_ctl.scala 2346:25 el2_dec_tlu_ctl.scala 2351:20] + wire _T_2221 = |mhpmc_inc_r_1; // @[el2_dec_tlu_ctl.scala 2452:87] + wire mhpmc4_wr_en1 = _T_2220 & _T_2221; // @[el2_dec_tlu_ctl.scala 2452:67] + reg [31:0] mhpmc4h; // @[el2_lib.scala 514:16] + reg [31:0] mhpmc4; // @[el2_lib.scala 514:16] + wire [63:0] _T_2224 = {mhpmc4h,mhpmc4}; // @[Cat.scala 29:58] + wire [63:0] _T_2225 = {63'h0,mhpmc_inc_r_1}; // @[Cat.scala 29:58] + wire [63:0] mhpmc4_incr = _T_2224 + _T_2225; // @[el2_dec_tlu_ctl.scala 2457:50] + wire _T_2234 = io_dec_csr_wraddr_r == 12'hb84; // @[el2_dec_tlu_ctl.scala 2461:74] + wire mhpmc4h_wr_en0 = io_dec_csr_wen_r_mod & _T_2234; // @[el2_dec_tlu_ctl.scala 2461:45] + wire _T_2240 = io_dec_csr_wraddr_r == 12'hb05; // @[el2_dec_tlu_ctl.scala 2470:73] + wire mhpmc5_wr_en0 = io_dec_csr_wen_r_mod & _T_2240; // @[el2_dec_tlu_ctl.scala 2470:44] + wire _T_2243 = _T_2196 | perfcnt_during_sleep[2]; // @[el2_dec_tlu_ctl.scala 2471:40] + wire mhpmc_inc_r_2 = _T_1871[0]; // @[el2_dec_tlu_ctl.scala 2346:25 el2_dec_tlu_ctl.scala 2351:20] + wire _T_2244 = |mhpmc_inc_r_2; // @[el2_dec_tlu_ctl.scala 2471:87] + wire mhpmc5_wr_en1 = _T_2243 & _T_2244; // @[el2_dec_tlu_ctl.scala 2471:67] + reg [31:0] mhpmc5h; // @[el2_lib.scala 514:16] + reg [31:0] mhpmc5; // @[el2_lib.scala 514:16] + wire [63:0] _T_2247 = {mhpmc5h,mhpmc5}; // @[Cat.scala 29:58] + wire [63:0] _T_2248 = {63'h0,mhpmc_inc_r_2}; // @[Cat.scala 29:58] + wire [63:0] mhpmc5_incr = _T_2247 + _T_2248; // @[el2_dec_tlu_ctl.scala 2474:50] + wire _T_2256 = io_dec_csr_wraddr_r == 12'hb85; // @[el2_dec_tlu_ctl.scala 2479:74] + wire mhpmc5h_wr_en0 = io_dec_csr_wen_r_mod & _T_2256; // @[el2_dec_tlu_ctl.scala 2479:45] + wire _T_2262 = io_dec_csr_wraddr_r == 12'hb06; // @[el2_dec_tlu_ctl.scala 2488:73] + wire mhpmc6_wr_en0 = io_dec_csr_wen_r_mod & _T_2262; // @[el2_dec_tlu_ctl.scala 2488:44] + wire _T_2265 = _T_2196 | perfcnt_during_sleep[3]; // @[el2_dec_tlu_ctl.scala 2489:40] + wire mhpmc_inc_r_3 = _T_2154[0]; // @[el2_dec_tlu_ctl.scala 2346:25 el2_dec_tlu_ctl.scala 2351:20] + wire _T_2266 = |mhpmc_inc_r_3; // @[el2_dec_tlu_ctl.scala 2489:87] + wire mhpmc6_wr_en1 = _T_2265 & _T_2266; // @[el2_dec_tlu_ctl.scala 2489:67] + reg [31:0] mhpmc6h; // @[el2_lib.scala 514:16] + reg [31:0] mhpmc6; // @[el2_lib.scala 514:16] + wire [63:0] _T_2269 = {mhpmc6h,mhpmc6}; // @[Cat.scala 29:58] + wire [63:0] _T_2270 = {63'h0,mhpmc_inc_r_3}; // @[Cat.scala 29:58] + wire [63:0] mhpmc6_incr = _T_2269 + _T_2270; // @[el2_dec_tlu_ctl.scala 2492:50] + wire _T_2278 = io_dec_csr_wraddr_r == 12'hb86; // @[el2_dec_tlu_ctl.scala 2497:74] + wire mhpmc6h_wr_en0 = io_dec_csr_wen_r_mod & _T_2278; // @[el2_dec_tlu_ctl.scala 2497:45] + wire _T_2284 = io_dec_csr_wrdata_r[9:0] > 10'h204; // @[el2_dec_tlu_ctl.scala 2508:57] + wire _T_2286 = |io_dec_csr_wrdata_r[31:10]; // @[el2_dec_tlu_ctl.scala 2508:103] + wire _T_2287 = _T_2284 | _T_2286; // @[el2_dec_tlu_ctl.scala 2508:72] + wire _T_2290 = io_dec_csr_wraddr_r == 12'h323; // @[el2_dec_tlu_ctl.scala 2510:71] + wire wr_mhpme3_r = io_dec_csr_wen_r_mod & _T_2290; // @[el2_dec_tlu_ctl.scala 2510:42] + wire _T_2294 = io_dec_csr_wraddr_r == 12'h324; // @[el2_dec_tlu_ctl.scala 2517:71] + wire wr_mhpme4_r = io_dec_csr_wen_r_mod & _T_2294; // @[el2_dec_tlu_ctl.scala 2517:42] + wire _T_2298 = io_dec_csr_wraddr_r == 12'h325; // @[el2_dec_tlu_ctl.scala 2524:71] + wire wr_mhpme5_r = io_dec_csr_wen_r_mod & _T_2298; // @[el2_dec_tlu_ctl.scala 2524:42] + wire _T_2302 = io_dec_csr_wraddr_r == 12'h326; // @[el2_dec_tlu_ctl.scala 2531:71] + wire wr_mhpme6_r = io_dec_csr_wen_r_mod & _T_2302; // @[el2_dec_tlu_ctl.scala 2531:42] + wire _T_2306 = io_dec_csr_wraddr_r == 12'h320; // @[el2_dec_tlu_ctl.scala 2548:78] + wire wr_mcountinhibit_r = io_dec_csr_wen_r_mod & _T_2306; // @[el2_dec_tlu_ctl.scala 2548:49] + wire _T_2318 = io_i0_valid_wb | io_exc_or_int_valid_r_d1; // @[el2_dec_tlu_ctl.scala 2563:52] + wire _T_2319 = _T_2318 | io_interrupt_valid_r_d1; // @[el2_dec_tlu_ctl.scala 2563:79] + wire _T_2320 = _T_2319 | io_dec_tlu_i0_valid_wb1; // @[el2_dec_tlu_ctl.scala 2563:105] + wire _T_2321 = _T_2320 | io_dec_tlu_i0_exc_valid_wb1; // @[el2_dec_tlu_ctl.scala 2563:131] + wire _T_2322 = _T_2321 | io_dec_tlu_int_valid_wb1; // @[el2_dec_tlu_ctl.scala 2564:33] + reg _T_2325; // @[el2_dec_tlu_ctl.scala 2566:63] + wire _T_2326 = io_i0_exception_valid_r_d1 | io_lsu_i0_exc_r_d1; // @[el2_dec_tlu_ctl.scala 2567:92] + wire _T_2327 = ~io_trigger_hit_dmode_r_d1; // @[el2_dec_tlu_ctl.scala 2567:138] + wire _T_2328 = io_trigger_hit_r_d1 & _T_2327; // @[el2_dec_tlu_ctl.scala 2567:136] + reg _T_2330; // @[el2_dec_tlu_ctl.scala 2567:63] + reg [4:0] _T_2331; // @[el2_dec_tlu_ctl.scala 2568:63] + reg _T_2332; // @[el2_dec_tlu_ctl.scala 2569:63] + wire [31:0] _T_2338 = {io_core_id,4'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2347 = {21'h3,3'h0,io_mstatus[1],3'h0,io_mstatus[0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2352 = {io_mtvec[30:1],1'h0,io_mtvec[0]}; // @[Cat.scala 29:58] + wire [31:0] _T_2365 = {1'h0,io_mip[5:3],16'h0,io_mip[2],3'h0,io_mip[1],3'h0,io_mip[0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2378 = {1'h0,mie[5:3],16'h0,mie[2],3'h0,mie[1],3'h0,mie[0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2390 = {io_mepc,1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2395 = {28'h0,mscause}; // @[Cat.scala 29:58] + wire [31:0] _T_2403 = {meivt,10'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2409 = {28'h0,meicurpl}; // @[Cat.scala 29:58] + wire [31:0] _T_2412 = {28'h0,meicidpl}; // @[Cat.scala 29:58] + wire [31:0] _T_2415 = {28'h0,meipt}; // @[Cat.scala 29:58] + wire [31:0] _T_2418 = {23'h0,mcgc}; // @[Cat.scala 29:58] + wire [31:0] _T_2421 = {13'h0,_T_348,4'h0,mfdc_int[11:7],_T_351,mfdc_int[5:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_2425 = {16'h4000,io_dcsr[15:2],2'h3}; // @[Cat.scala 29:58] + wire [31:0] _T_2427 = {io_dpc,1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2443 = {7'h0,dicawics[16],2'h0,dicawics[15:14],3'h0,dicawics[13:0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2446 = {30'h0,mtsel}; // @[Cat.scala 29:58] + wire [31:0] _T_2475 = {26'h0,mfdht}; // @[Cat.scala 29:58] + wire [31:0] _T_2478 = {30'h0,mfdhs}; // @[Cat.scala 29:58] + wire [31:0] _T_2481 = {22'h0,mhpme3}; // @[Cat.scala 29:58] + wire [31:0] _T_2484 = {22'h0,mhpme4}; // @[Cat.scala 29:58] + wire [31:0] _T_2487 = {22'h0,mhpme5}; // @[Cat.scala 29:58] + wire [31:0] _T_2490 = {22'h0,mhpme6}; // @[Cat.scala 29:58] + wire [31:0] _T_2493 = {25'h0,temp_ncount6_2,1'h0,temp_ncount0}; // @[Cat.scala 29:58] + wire [31:0] _T_2496 = {30'h0,mpmc,1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2499 = io_csr_pkt_csr_misa ? 32'h40001104 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2500 = io_csr_pkt_csr_mvendorid ? 32'h45 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2501 = io_csr_pkt_csr_marchid ? 32'h10 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2502 = io_csr_pkt_csr_mimpid ? 32'h2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2503 = io_csr_pkt_csr_mhartid ? _T_2338 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2504 = io_csr_pkt_csr_mstatus ? _T_2347 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2505 = io_csr_pkt_csr_mtvec ? _T_2352 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2506 = io_csr_pkt_csr_mip ? _T_2365 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2507 = io_csr_pkt_csr_mie ? _T_2378 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2508 = io_csr_pkt_csr_mcyclel ? mcyclel : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2509 = io_csr_pkt_csr_mcycleh ? mcycleh_inc : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2510 = io_csr_pkt_csr_minstretl ? minstretl : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2511 = io_csr_pkt_csr_minstreth ? minstreth_inc : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2512 = io_csr_pkt_csr_mscratch ? mscratch : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2513 = io_csr_pkt_csr_mepc ? _T_2390 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2514 = io_csr_pkt_csr_mcause ? mcause : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2515 = io_csr_pkt_csr_mscause ? _T_2395 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2516 = io_csr_pkt_csr_mtval ? mtval : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2517 = io_csr_pkt_csr_mrac ? mrac : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2518 = io_csr_pkt_csr_mdseac ? mdseac : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2519 = io_csr_pkt_csr_meivt ? _T_2403 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2520 = io_csr_pkt_csr_meihap ? _T_615 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2521 = io_csr_pkt_csr_meicurpl ? _T_2409 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2522 = io_csr_pkt_csr_meicidpl ? _T_2412 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2523 = io_csr_pkt_csr_meipt ? _T_2415 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2524 = io_csr_pkt_csr_mcgc ? _T_2418 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2525 = io_csr_pkt_csr_mfdc ? _T_2421 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2526 = io_csr_pkt_csr_dcsr ? _T_2425 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2527 = io_csr_pkt_csr_dpc ? _T_2427 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2528 = io_csr_pkt_csr_dicad0 ? dicad0[31:0] : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2529 = io_csr_pkt_csr_dicad0h ? dicad0h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2530 = io_csr_pkt_csr_dicad1 ? dicad1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2531 = io_csr_pkt_csr_dicawics ? _T_2443 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2532 = io_csr_pkt_csr_mtsel ? _T_2446 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2533 = io_csr_pkt_csr_mtdata1 ? mtdata1_tsel_out : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2534 = io_csr_pkt_csr_mtdata2 ? mtdata2_tsel_out : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2535 = io_csr_pkt_csr_micect ? micect : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2536 = io_csr_pkt_csr_miccmect ? miccmect : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2537 = io_csr_pkt_csr_mdccmect ? mdccmect : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2538 = io_csr_pkt_csr_mhpmc3 ? mhpmc3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2539 = io_csr_pkt_csr_mhpmc4 ? mhpmc4 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2540 = io_csr_pkt_csr_mhpmc5 ? mhpmc5 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2541 = io_csr_pkt_csr_mhpmc6 ? mhpmc6 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2542 = io_csr_pkt_csr_mhpmc3h ? mhpmc3h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2543 = io_csr_pkt_csr_mhpmc4h ? mhpmc4h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2544 = io_csr_pkt_csr_mhpmc5h ? mhpmc5h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2545 = io_csr_pkt_csr_mhpmc6h ? mhpmc6h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2546 = io_csr_pkt_csr_mfdht ? _T_2475 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2547 = io_csr_pkt_csr_mfdhs ? _T_2478 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2548 = io_csr_pkt_csr_mhpme3 ? _T_2481 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2549 = io_csr_pkt_csr_mhpme4 ? _T_2484 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2550 = io_csr_pkt_csr_mhpme5 ? _T_2487 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2551 = io_csr_pkt_csr_mhpme6 ? _T_2490 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2552 = io_csr_pkt_csr_mcountinhibit ? _T_2493 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2553 = io_csr_pkt_csr_mpmc ? _T_2496 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2554 = io_dec_timer_read_d ? io_dec_timer_rddata_d : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2555 = _T_2499 | _T_2500; // @[Mux.scala 27:72] + wire [31:0] _T_2556 = _T_2555 | _T_2501; // @[Mux.scala 27:72] + wire [31:0] _T_2557 = _T_2556 | _T_2502; // @[Mux.scala 27:72] + wire [31:0] _T_2558 = _T_2557 | _T_2503; // @[Mux.scala 27:72] + wire [31:0] _T_2559 = _T_2558 | _T_2504; // @[Mux.scala 27:72] + wire [31:0] _T_2560 = _T_2559 | _T_2505; // @[Mux.scala 27:72] + wire [31:0] _T_2561 = _T_2560 | _T_2506; // @[Mux.scala 27:72] + wire [31:0] _T_2562 = _T_2561 | _T_2507; // @[Mux.scala 27:72] + wire [31:0] _T_2563 = _T_2562 | _T_2508; // @[Mux.scala 27:72] + wire [31:0] _T_2564 = _T_2563 | _T_2509; // @[Mux.scala 27:72] + wire [31:0] _T_2565 = _T_2564 | _T_2510; // @[Mux.scala 27:72] + wire [31:0] _T_2566 = _T_2565 | _T_2511; // @[Mux.scala 27:72] + wire [31:0] _T_2567 = _T_2566 | _T_2512; // @[Mux.scala 27:72] + wire [31:0] _T_2568 = _T_2567 | _T_2513; // @[Mux.scala 27:72] + wire [31:0] _T_2569 = _T_2568 | _T_2514; // @[Mux.scala 27:72] + wire [31:0] _T_2570 = _T_2569 | _T_2515; // @[Mux.scala 27:72] + wire [31:0] _T_2571 = _T_2570 | _T_2516; // @[Mux.scala 27:72] + wire [31:0] _T_2572 = _T_2571 | _T_2517; // @[Mux.scala 27:72] + wire [31:0] _T_2573 = _T_2572 | _T_2518; // @[Mux.scala 27:72] + wire [31:0] _T_2574 = _T_2573 | _T_2519; // @[Mux.scala 27:72] + wire [31:0] _T_2575 = _T_2574 | _T_2520; // @[Mux.scala 27:72] + wire [31:0] _T_2576 = _T_2575 | _T_2521; // @[Mux.scala 27:72] + wire [31:0] _T_2577 = _T_2576 | _T_2522; // @[Mux.scala 27:72] + wire [31:0] _T_2578 = _T_2577 | _T_2523; // @[Mux.scala 27:72] + wire [31:0] _T_2579 = _T_2578 | _T_2524; // @[Mux.scala 27:72] + wire [31:0] _T_2580 = _T_2579 | _T_2525; // @[Mux.scala 27:72] + wire [31:0] _T_2581 = _T_2580 | _T_2526; // @[Mux.scala 27:72] + wire [31:0] _T_2582 = _T_2581 | _T_2527; // @[Mux.scala 27:72] + wire [31:0] _T_2583 = _T_2582 | _T_2528; // @[Mux.scala 27:72] + wire [31:0] _T_2584 = _T_2583 | _T_2529; // @[Mux.scala 27:72] + wire [31:0] _T_2585 = _T_2584 | _T_2530; // @[Mux.scala 27:72] + wire [31:0] _T_2586 = _T_2585 | _T_2531; // @[Mux.scala 27:72] + wire [31:0] _T_2587 = _T_2586 | _T_2532; // @[Mux.scala 27:72] + wire [31:0] _T_2588 = _T_2587 | _T_2533; // @[Mux.scala 27:72] + wire [31:0] _T_2589 = _T_2588 | _T_2534; // @[Mux.scala 27:72] + wire [31:0] _T_2590 = _T_2589 | _T_2535; // @[Mux.scala 27:72] + wire [31:0] _T_2591 = _T_2590 | _T_2536; // @[Mux.scala 27:72] + wire [31:0] _T_2592 = _T_2591 | _T_2537; // @[Mux.scala 27:72] + wire [31:0] _T_2593 = _T_2592 | _T_2538; // @[Mux.scala 27:72] + wire [31:0] _T_2594 = _T_2593 | _T_2539; // @[Mux.scala 27:72] + wire [31:0] _T_2595 = _T_2594 | _T_2540; // @[Mux.scala 27:72] + wire [31:0] _T_2596 = _T_2595 | _T_2541; // @[Mux.scala 27:72] + wire [31:0] _T_2597 = _T_2596 | _T_2542; // @[Mux.scala 27:72] + wire [31:0] _T_2598 = _T_2597 | _T_2543; // @[Mux.scala 27:72] + wire [31:0] _T_2599 = _T_2598 | _T_2544; // @[Mux.scala 27:72] + wire [31:0] _T_2600 = _T_2599 | _T_2545; // @[Mux.scala 27:72] + wire [31:0] _T_2601 = _T_2600 | _T_2546; // @[Mux.scala 27:72] + wire [31:0] _T_2602 = _T_2601 | _T_2547; // @[Mux.scala 27:72] + wire [31:0] _T_2603 = _T_2602 | _T_2548; // @[Mux.scala 27:72] + wire [31:0] _T_2604 = _T_2603 | _T_2549; // @[Mux.scala 27:72] + wire [31:0] _T_2605 = _T_2604 | _T_2550; // @[Mux.scala 27:72] + wire [31:0] _T_2606 = _T_2605 | _T_2551; // @[Mux.scala 27:72] + wire [31:0] _T_2607 = _T_2606 | _T_2552; // @[Mux.scala 27:72] + wire [31:0] _T_2608 = _T_2607 | _T_2553; // @[Mux.scala 27:72] + rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_io_l1clk), + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en), + .io_scan_mode(rvclkhdr_io_scan_mode) + ); + rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_1_io_l1clk), + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en), + .io_scan_mode(rvclkhdr_1_io_scan_mode) + ); + rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_2_io_l1clk), + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en), + .io_scan_mode(rvclkhdr_2_io_scan_mode) + ); + rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_3_io_l1clk), + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en), + .io_scan_mode(rvclkhdr_3_io_scan_mode) + ); + rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_4_io_l1clk), + .io_clk(rvclkhdr_4_io_clk), + .io_en(rvclkhdr_4_io_en), + .io_scan_mode(rvclkhdr_4_io_scan_mode) + ); + rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_5_io_l1clk), + .io_clk(rvclkhdr_5_io_clk), + .io_en(rvclkhdr_5_io_en), + .io_scan_mode(rvclkhdr_5_io_scan_mode) + ); + rvclkhdr rvclkhdr_6 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_6_io_l1clk), + .io_clk(rvclkhdr_6_io_clk), + .io_en(rvclkhdr_6_io_en), + .io_scan_mode(rvclkhdr_6_io_scan_mode) + ); + rvclkhdr rvclkhdr_7 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_7_io_l1clk), + .io_clk(rvclkhdr_7_io_clk), + .io_en(rvclkhdr_7_io_en), + .io_scan_mode(rvclkhdr_7_io_scan_mode) + ); + rvclkhdr rvclkhdr_8 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_8_io_l1clk), + .io_clk(rvclkhdr_8_io_clk), + .io_en(rvclkhdr_8_io_en), + .io_scan_mode(rvclkhdr_8_io_scan_mode) + ); + rvclkhdr rvclkhdr_9 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_9_io_l1clk), + .io_clk(rvclkhdr_9_io_clk), + .io_en(rvclkhdr_9_io_en), + .io_scan_mode(rvclkhdr_9_io_scan_mode) + ); + rvclkhdr rvclkhdr_10 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_10_io_l1clk), + .io_clk(rvclkhdr_10_io_clk), + .io_en(rvclkhdr_10_io_en), + .io_scan_mode(rvclkhdr_10_io_scan_mode) + ); + rvclkhdr rvclkhdr_11 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_11_io_l1clk), + .io_clk(rvclkhdr_11_io_clk), + .io_en(rvclkhdr_11_io_en), + .io_scan_mode(rvclkhdr_11_io_scan_mode) + ); + rvclkhdr rvclkhdr_12 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_12_io_l1clk), + .io_clk(rvclkhdr_12_io_clk), + .io_en(rvclkhdr_12_io_en), + .io_scan_mode(rvclkhdr_12_io_scan_mode) + ); + rvclkhdr rvclkhdr_13 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_13_io_l1clk), + .io_clk(rvclkhdr_13_io_clk), + .io_en(rvclkhdr_13_io_en), + .io_scan_mode(rvclkhdr_13_io_scan_mode) + ); + rvclkhdr rvclkhdr_14 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_14_io_l1clk), + .io_clk(rvclkhdr_14_io_clk), + .io_en(rvclkhdr_14_io_en), + .io_scan_mode(rvclkhdr_14_io_scan_mode) + ); + rvclkhdr rvclkhdr_15 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_15_io_l1clk), + .io_clk(rvclkhdr_15_io_clk), + .io_en(rvclkhdr_15_io_en), + .io_scan_mode(rvclkhdr_15_io_scan_mode) + ); + rvclkhdr rvclkhdr_16 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_16_io_l1clk), + .io_clk(rvclkhdr_16_io_clk), + .io_en(rvclkhdr_16_io_en), + .io_scan_mode(rvclkhdr_16_io_scan_mode) + ); + rvclkhdr rvclkhdr_17 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_17_io_l1clk), + .io_clk(rvclkhdr_17_io_clk), + .io_en(rvclkhdr_17_io_en), + .io_scan_mode(rvclkhdr_17_io_scan_mode) + ); + rvclkhdr rvclkhdr_18 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_18_io_l1clk), + .io_clk(rvclkhdr_18_io_clk), + .io_en(rvclkhdr_18_io_en), + .io_scan_mode(rvclkhdr_18_io_scan_mode) + ); + rvclkhdr rvclkhdr_19 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_19_io_l1clk), + .io_clk(rvclkhdr_19_io_clk), + .io_en(rvclkhdr_19_io_en), + .io_scan_mode(rvclkhdr_19_io_scan_mode) + ); + rvclkhdr rvclkhdr_20 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_20_io_l1clk), + .io_clk(rvclkhdr_20_io_clk), + .io_en(rvclkhdr_20_io_en), + .io_scan_mode(rvclkhdr_20_io_scan_mode) + ); + rvclkhdr rvclkhdr_21 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_21_io_l1clk), + .io_clk(rvclkhdr_21_io_clk), + .io_en(rvclkhdr_21_io_en), + .io_scan_mode(rvclkhdr_21_io_scan_mode) + ); + rvclkhdr rvclkhdr_22 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_22_io_l1clk), + .io_clk(rvclkhdr_22_io_clk), + .io_en(rvclkhdr_22_io_en), + .io_scan_mode(rvclkhdr_22_io_scan_mode) + ); + rvclkhdr rvclkhdr_23 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_23_io_l1clk), + .io_clk(rvclkhdr_23_io_clk), + .io_en(rvclkhdr_23_io_en), + .io_scan_mode(rvclkhdr_23_io_scan_mode) + ); + rvclkhdr rvclkhdr_24 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_24_io_l1clk), + .io_clk(rvclkhdr_24_io_clk), + .io_en(rvclkhdr_24_io_en), + .io_scan_mode(rvclkhdr_24_io_scan_mode) + ); + rvclkhdr rvclkhdr_25 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_25_io_l1clk), + .io_clk(rvclkhdr_25_io_clk), + .io_en(rvclkhdr_25_io_en), + .io_scan_mode(rvclkhdr_25_io_scan_mode) + ); + rvclkhdr rvclkhdr_26 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_26_io_l1clk), + .io_clk(rvclkhdr_26_io_clk), + .io_en(rvclkhdr_26_io_en), + .io_scan_mode(rvclkhdr_26_io_scan_mode) + ); + rvclkhdr rvclkhdr_27 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_27_io_l1clk), + .io_clk(rvclkhdr_27_io_clk), + .io_en(rvclkhdr_27_io_en), + .io_scan_mode(rvclkhdr_27_io_scan_mode) + ); + rvclkhdr rvclkhdr_28 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_28_io_l1clk), + .io_clk(rvclkhdr_28_io_clk), + .io_en(rvclkhdr_28_io_en), + .io_scan_mode(rvclkhdr_28_io_scan_mode) + ); + rvclkhdr rvclkhdr_29 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_29_io_l1clk), + .io_clk(rvclkhdr_29_io_clk), + .io_en(rvclkhdr_29_io_en), + .io_scan_mode(rvclkhdr_29_io_scan_mode) + ); + rvclkhdr rvclkhdr_30 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_30_io_l1clk), + .io_clk(rvclkhdr_30_io_clk), + .io_en(rvclkhdr_30_io_en), + .io_scan_mode(rvclkhdr_30_io_scan_mode) + ); + rvclkhdr rvclkhdr_31 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_31_io_l1clk), + .io_clk(rvclkhdr_31_io_clk), + .io_en(rvclkhdr_31_io_en), + .io_scan_mode(rvclkhdr_31_io_scan_mode) + ); + rvclkhdr rvclkhdr_32 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_32_io_l1clk), + .io_clk(rvclkhdr_32_io_clk), + .io_en(rvclkhdr_32_io_en), + .io_scan_mode(rvclkhdr_32_io_scan_mode) + ); + rvclkhdr rvclkhdr_33 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_33_io_l1clk), + .io_clk(rvclkhdr_33_io_clk), + .io_en(rvclkhdr_33_io_en), + .io_scan_mode(rvclkhdr_33_io_scan_mode) + ); + rvclkhdr rvclkhdr_34 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_34_io_l1clk), + .io_clk(rvclkhdr_34_io_clk), + .io_en(rvclkhdr_34_io_en), + .io_scan_mode(rvclkhdr_34_io_scan_mode) + ); + assign io_dec_tlu_ic_diag_pkt_icache_wrdata = {_T_762,dicad0[31:0]}; // @[el2_dec_tlu_ctl.scala 2232:65] + assign io_dec_tlu_ic_diag_pkt_icache_dicawics = dicawics; // @[el2_dec_tlu_ctl.scala 2235:42] + assign io_dec_tlu_ic_diag_pkt_icache_rd_valid = icache_rd_valid_f; // @[el2_dec_tlu_ctl.scala 2243:42] + assign io_dec_tlu_ic_diag_pkt_icache_wr_valid = icache_wr_valid_f; // @[el2_dec_tlu_ctl.scala 2244:42] + assign io_trigger_pkt_any_0_select = io_mtdata1_t_0[7]; // @[el2_dec_tlu_ctl.scala 2308:36] + assign io_trigger_pkt_any_0_match_pkt = io_mtdata1_t_0[4]; // @[el2_dec_tlu_ctl.scala 2309:39] + assign io_trigger_pkt_any_0_store = io_mtdata1_t_0[1]; // @[el2_dec_tlu_ctl.scala 2310:36] + assign io_trigger_pkt_any_0_load = io_mtdata1_t_0[0]; // @[el2_dec_tlu_ctl.scala 2311:36] + assign io_trigger_pkt_any_0_execute = io_mtdata1_t_0[2]; // @[el2_dec_tlu_ctl.scala 2312:36] + assign io_trigger_pkt_any_0_m = io_mtdata1_t_0[3]; // @[el2_dec_tlu_ctl.scala 2313:36] + assign io_trigger_pkt_any_0_tdata2 = mtdata2_t_0; // @[el2_dec_tlu_ctl.scala 2326:53] + assign io_trigger_pkt_any_1_select = io_mtdata1_t_1[7]; // @[el2_dec_tlu_ctl.scala 2308:36] + assign io_trigger_pkt_any_1_match_pkt = io_mtdata1_t_1[4]; // @[el2_dec_tlu_ctl.scala 2309:39] + assign io_trigger_pkt_any_1_store = io_mtdata1_t_1[1]; // @[el2_dec_tlu_ctl.scala 2310:36] + assign io_trigger_pkt_any_1_load = io_mtdata1_t_1[0]; // @[el2_dec_tlu_ctl.scala 2311:36] + assign io_trigger_pkt_any_1_execute = io_mtdata1_t_1[2]; // @[el2_dec_tlu_ctl.scala 2312:36] + assign io_trigger_pkt_any_1_m = io_mtdata1_t_1[3]; // @[el2_dec_tlu_ctl.scala 2313:36] + assign io_trigger_pkt_any_1_tdata2 = mtdata2_t_1; // @[el2_dec_tlu_ctl.scala 2326:53] + assign io_trigger_pkt_any_2_select = io_mtdata1_t_2[7]; // @[el2_dec_tlu_ctl.scala 2308:36] + assign io_trigger_pkt_any_2_match_pkt = io_mtdata1_t_2[4]; // @[el2_dec_tlu_ctl.scala 2309:39] + assign io_trigger_pkt_any_2_store = io_mtdata1_t_2[1]; // @[el2_dec_tlu_ctl.scala 2310:36] + assign io_trigger_pkt_any_2_load = io_mtdata1_t_2[0]; // @[el2_dec_tlu_ctl.scala 2311:36] + assign io_trigger_pkt_any_2_execute = io_mtdata1_t_2[2]; // @[el2_dec_tlu_ctl.scala 2312:36] + assign io_trigger_pkt_any_2_m = io_mtdata1_t_2[3]; // @[el2_dec_tlu_ctl.scala 2313:36] + assign io_trigger_pkt_any_2_tdata2 = mtdata2_t_2; // @[el2_dec_tlu_ctl.scala 2326:53] + assign io_trigger_pkt_any_3_select = io_mtdata1_t_3[7]; // @[el2_dec_tlu_ctl.scala 2308:36] + assign io_trigger_pkt_any_3_match_pkt = io_mtdata1_t_3[4]; // @[el2_dec_tlu_ctl.scala 2309:39] + assign io_trigger_pkt_any_3_store = io_mtdata1_t_3[1]; // @[el2_dec_tlu_ctl.scala 2310:36] + assign io_trigger_pkt_any_3_load = io_mtdata1_t_3[0]; // @[el2_dec_tlu_ctl.scala 2311:36] + assign io_trigger_pkt_any_3_execute = io_mtdata1_t_3[2]; // @[el2_dec_tlu_ctl.scala 2312:36] + assign io_trigger_pkt_any_3_m = io_mtdata1_t_3[3]; // @[el2_dec_tlu_ctl.scala 2313:36] + assign io_trigger_pkt_any_3_tdata2 = mtdata2_t_3; // @[el2_dec_tlu_ctl.scala 2326:53] + assign io_dec_tlu_int_valid_wb1 = _T_2332; // @[el2_dec_tlu_ctl.scala 2569:31] + assign io_dec_tlu_i0_exc_valid_wb1 = _T_2330; // @[el2_dec_tlu_ctl.scala 2567:31] + assign io_dec_tlu_i0_valid_wb1 = _T_2325; // @[el2_dec_tlu_ctl.scala 2566:31] + assign io_dec_tlu_mtval_wb1 = mtval; // @[el2_dec_tlu_ctl.scala 2571:25] + assign io_dec_tlu_exc_cause_wb1 = _T_2331; // @[el2_dec_tlu_ctl.scala 2568:31] + assign io_dec_tlu_perfcnt0 = mhpmc_inc_r_d1_0 & _T_2177; // @[el2_dec_tlu_ctl.scala 2423:23] + assign io_dec_tlu_perfcnt1 = mhpmc_inc_r_d1_1 & _T_2182; // @[el2_dec_tlu_ctl.scala 2424:23] + assign io_dec_tlu_perfcnt2 = mhpmc_inc_r_d1_2 & _T_2187; // @[el2_dec_tlu_ctl.scala 2425:23] + assign io_dec_tlu_perfcnt3 = mhpmc_inc_r_d1_3 & _T_2192; // @[el2_dec_tlu_ctl.scala 2426:23] + assign io_dec_tlu_misc_clk_override = mcgc[8]; // @[el2_dec_tlu_ctl.scala 1797:32] + assign io_dec_tlu_dec_clk_override = mcgc[7]; // @[el2_dec_tlu_ctl.scala 1798:32] + assign io_dec_tlu_ifu_clk_override = mcgc[5]; // @[el2_dec_tlu_ctl.scala 1799:32] + assign io_dec_tlu_lsu_clk_override = mcgc[4]; // @[el2_dec_tlu_ctl.scala 1800:32] + assign io_dec_tlu_bus_clk_override = mcgc[3]; // @[el2_dec_tlu_ctl.scala 1801:32] + assign io_dec_tlu_pic_clk_override = mcgc[2]; // @[el2_dec_tlu_ctl.scala 1802:32] + assign io_dec_tlu_dccm_clk_override = mcgc[1]; // @[el2_dec_tlu_ctl.scala 1803:32] + assign io_dec_tlu_icm_clk_override = mcgc[0]; // @[el2_dec_tlu_ctl.scala 1804:32] + assign io_dec_csr_rddata_d = _T_2608 | _T_2554; // @[el2_dec_tlu_ctl.scala 2576:22] + assign io_dec_tlu_pipelining_disable = mfdc[0]; // @[el2_dec_tlu_ctl.scala 1847:40] + assign io_dec_tlu_wr_pause_r = _T_368 & _T_369; // @[el2_dec_tlu_ctl.scala 1856:25] + assign io_dec_tlu_meipt = meipt; // @[el2_dec_tlu_ctl.scala 2083:20] + assign io_dec_tlu_meicurpl = meicurpl; // @[el2_dec_tlu_ctl.scala 2047:23] + assign io_dec_tlu_meihap = _T_615[29:0]; // @[el2_dec_tlu_ctl.scala 2033:21] + assign io_dec_tlu_mrac_ff = mrac; // @[el2_dec_tlu_ctl.scala 1886:22] + assign io_dec_tlu_wb_coalescing_disable = mfdc[2]; // @[el2_dec_tlu_ctl.scala 1846:40] + assign io_dec_tlu_bpred_disable = mfdc[3]; // @[el2_dec_tlu_ctl.scala 1845:40] + assign io_dec_tlu_sideeffect_posted_disable = mfdc[6]; // @[el2_dec_tlu_ctl.scala 1844:40] + assign io_dec_tlu_core_ecc_disable = mfdc[8]; // @[el2_dec_tlu_ctl.scala 1843:40] + assign io_dec_tlu_external_ldfwd_disable = mfdc[11]; // @[el2_dec_tlu_ctl.scala 1842:40] + assign io_dec_tlu_dma_qos_prty = mfdc[18:16]; // @[el2_dec_tlu_ctl.scala 1841:40] + assign io_dec_csr_wen_r_mod = _T_1 & _T_2; // @[el2_dec_tlu_ctl.scala 1530:24] + assign io_fw_halt_req = _T_500 & _T_501; // @[el2_dec_tlu_ctl.scala 1921:18] + assign io_mstatus = _T_54; // @[el2_dec_tlu_ctl.scala 1546:14] + assign io_mstatus_mie_ns = io_mstatus[0] & _T_52; // @[el2_dec_tlu_ctl.scala 1545:21] + assign io_dcsr = _T_700; // @[el2_dec_tlu_ctl.scala 2130:11] + assign io_mtvec = _T_60; // @[el2_dec_tlu_ctl.scala 1558:12] + assign io_mip = _T_66; // @[el2_dec_tlu_ctl.scala 1573:10] + assign io_mie_ns = wr_mie_r ? _T_76 : mie; // @[el2_dec_tlu_ctl.scala 1587:13] + assign io_npc_r = _T_159 | _T_157; // @[el2_dec_tlu_ctl.scala 1681:12] + assign io_npc_r_d1 = _T_165; // @[el2_dec_tlu_ctl.scala 1687:15] + assign io_mepc = _T_194; // @[el2_dec_tlu_ctl.scala 1706:11] + assign io_mdseac_locked_ns = mdseac_en | _T_487; // @[el2_dec_tlu_ctl.scala 1904:23] + assign io_force_halt = mfdht[0] & _T_607; // @[el2_dec_tlu_ctl.scala 2010:17] + assign io_dpc = _T_725; // @[el2_dec_tlu_ctl.scala 2147:10] + assign io_mtdata1_t_0 = _T_871; // @[el2_dec_tlu_ctl.scala 2303:41] + assign io_mtdata1_t_1 = _T_872; // @[el2_dec_tlu_ctl.scala 2303:41] + assign io_mtdata1_t_2 = _T_873; // @[el2_dec_tlu_ctl.scala 2303:41] + assign io_mtdata1_t_3 = _T_874; // @[el2_dec_tlu_ctl.scala 2303:41] + assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_io_en = io_dec_csr_wen_r_mod & _T_56; // @[el2_lib.scala 511:17] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_1_io_en = wr_mcyclel_r | mcyclel_cout_in; // @[el2_lib.scala 511:17] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_2_io_en = wr_mcycleh_r | mcyclel_cout_f; // @[el2_lib.scala 511:17] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_3_io_en = i0_valid_no_ebreak_ecall_r | wr_minstretl_r; // @[el2_lib.scala 511:17] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_4_io_en = minstret_enable_f | wr_minstreth_r; // @[el2_lib.scala 511:17] + assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_5_io_en = io_dec_csr_wen_r_mod & _T_137; // @[el2_lib.scala 511:17] + assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_6_io_en = _T_162 | io_reset_delayed; // @[el2_lib.scala 511:17] + assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_7_io_en = _T_140 & io_dec_tlu_i0_valid_r; // @[el2_lib.scala 511:17] + assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_8_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_8_io_en = io_dec_csr_wen_r_mod & _T_323; // @[el2_lib.scala 511:17] + assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_9_io_en = io_dec_csr_wen_r_mod & _T_335; // @[el2_lib.scala 511:17] + assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_10_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_10_io_en = io_dec_csr_wen_r_mod & _T_372; // @[el2_lib.scala 511:17] + assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_11_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_11_io_en = _T_491 & _T_492; // @[el2_lib.scala 511:17] + assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_12_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_12_io_en = wr_micect_r | io_ic_perr_r_d1; // @[el2_lib.scala 511:17] + assign rvclkhdr_12_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_13_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_13_io_en = _T_547 | io_iccm_dma_sb_error; // @[el2_lib.scala 511:17] + assign rvclkhdr_13_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_14_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_14_io_en = wr_mdccmect_r | io_lsu_single_ecc_error_r_d1; // @[el2_lib.scala 511:17] + assign rvclkhdr_14_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_15_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_15_io_en = io_dec_csr_wen_r_mod & _T_610; // @[el2_lib.scala 511:17] + assign rvclkhdr_15_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_16_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_16_io_en = _T_631 | io_take_ext_int_start; // @[el2_lib.scala 511:17] + assign rvclkhdr_16_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_17_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_17_io_en = _T_697 | io_take_nmi; // @[el2_lib.scala 511:17] + assign rvclkhdr_17_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_18_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_18_io_en = _T_722 | dpc_capture_npc; // @[el2_lib.scala 511:17] + assign rvclkhdr_18_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_19_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_19_io_en = _T_662 & _T_732; // @[el2_lib.scala 511:17] + assign rvclkhdr_19_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_20_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_20_io_en = wr_dicad0_r | io_ifu_ic_debug_rd_data_valid; // @[el2_lib.scala 511:17] + assign rvclkhdr_20_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_21_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_21_io_en = wr_dicad0h_r | io_ifu_ic_debug_rd_data_valid; // @[el2_lib.scala 511:17] + assign rvclkhdr_21_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_22_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_22_io_en = _T_970 & _T_806; // @[el2_lib.scala 511:17] + assign rvclkhdr_22_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_23_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_23_io_en = _T_979 & _T_815; // @[el2_lib.scala 511:17] + assign rvclkhdr_23_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_24_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_24_io_en = _T_988 & _T_824; // @[el2_lib.scala 511:17] + assign rvclkhdr_24_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_25_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_25_io_en = _T_997 & _T_833; // @[el2_lib.scala 511:17] + assign rvclkhdr_25_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_26_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_26_io_en = mhpmc3_wr_en0 | mhpmc3_wr_en1; // @[el2_lib.scala 511:17] + assign rvclkhdr_26_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_27_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_27_io_en = mhpmc3h_wr_en0 | mhpmc3_wr_en1; // @[el2_lib.scala 511:17] + assign rvclkhdr_27_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_28_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_28_io_en = mhpmc4_wr_en0 | mhpmc4_wr_en1; // @[el2_lib.scala 511:17] + assign rvclkhdr_28_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_29_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_29_io_en = mhpmc4h_wr_en0 | mhpmc4_wr_en1; // @[el2_lib.scala 511:17] + assign rvclkhdr_29_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_30_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_30_io_en = mhpmc5_wr_en0 | mhpmc5_wr_en1; // @[el2_lib.scala 511:17] + assign rvclkhdr_30_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_31_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_31_io_en = mhpmc5h_wr_en0 | mhpmc5_wr_en1; // @[el2_lib.scala 511:17] + assign rvclkhdr_31_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_32_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_32_io_en = mhpmc6_wr_en0 | mhpmc6_wr_en1; // @[el2_lib.scala 511:17] + assign rvclkhdr_32_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_33_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_33_io_en = mhpmc6h_wr_en0 | mhpmc6_wr_en1; // @[el2_lib.scala 511:17] + assign rvclkhdr_33_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_34_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_34_io_en = _T_2322 | io_clk_override; // @[el2_lib.scala 485:16] + assign rvclkhdr_34_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + mpmc_b = _RAND_0[0:0]; + _RAND_1 = {1{`RANDOM}}; + _T_54 = _RAND_1[1:0]; + _RAND_2 = {1{`RANDOM}}; + _T_60 = _RAND_2[30:0]; + _RAND_3 = {1{`RANDOM}}; + mdccmect = _RAND_3[31:0]; + _RAND_4 = {1{`RANDOM}}; + miccmect = _RAND_4[31:0]; + _RAND_5 = {1{`RANDOM}}; + micect = _RAND_5[31:0]; + _RAND_6 = {1{`RANDOM}}; + _T_66 = _RAND_6[5:0]; + _RAND_7 = {1{`RANDOM}}; + mie = _RAND_7[5:0]; + _RAND_8 = {1{`RANDOM}}; + temp_ncount6_2 = _RAND_8[4:0]; + _RAND_9 = {1{`RANDOM}}; + temp_ncount0 = _RAND_9[0:0]; + _RAND_10 = {2{`RANDOM}}; + _T_95 = _RAND_10[32:0]; + _RAND_11 = {1{`RANDOM}}; + mcyclel_cout_f = _RAND_11[0:0]; + _RAND_12 = {1{`RANDOM}}; + mcycleh = _RAND_12[31:0]; + _RAND_13 = {2{`RANDOM}}; + _T_122 = _RAND_13[32:0]; + _RAND_14 = {1{`RANDOM}}; + minstret_enable_f = _RAND_14[0:0]; + _RAND_15 = {1{`RANDOM}}; + minstretl_cout_f = _RAND_15[0:0]; + _RAND_16 = {1{`RANDOM}}; + minstreth = _RAND_16[31:0]; + _RAND_17 = {1{`RANDOM}}; + mscratch = _RAND_17[31:0]; + _RAND_18 = {1{`RANDOM}}; + _T_165 = _RAND_18[30:0]; + _RAND_19 = {1{`RANDOM}}; + pc_r_d1 = _RAND_19[30:0]; + _RAND_20 = {1{`RANDOM}}; + _T_194 = _RAND_20[30:0]; + _RAND_21 = {1{`RANDOM}}; + mcause = _RAND_21[31:0]; + _RAND_22 = {1{`RANDOM}}; + mscause = _RAND_22[3:0]; + _RAND_23 = {1{`RANDOM}}; + mtval = _RAND_23[31:0]; + _RAND_24 = {1{`RANDOM}}; + mcgc = _RAND_24[8:0]; + _RAND_25 = {1{`RANDOM}}; + mfdc_int = _RAND_25[14:0]; + _RAND_26 = {1{`RANDOM}}; + mrac = _RAND_26[31:0]; + _RAND_27 = {1{`RANDOM}}; + mdseac = _RAND_27[31:0]; + _RAND_28 = {1{`RANDOM}}; + mfdht = _RAND_28[5:0]; + _RAND_29 = {1{`RANDOM}}; + mfdhs = _RAND_29[1:0]; + _RAND_30 = {1{`RANDOM}}; + force_halt_ctr_f = _RAND_30[31:0]; + _RAND_31 = {1{`RANDOM}}; + meivt = _RAND_31[21:0]; + _RAND_32 = {1{`RANDOM}}; + meihap = _RAND_32[7:0]; + _RAND_33 = {1{`RANDOM}}; + meicurpl = _RAND_33[3:0]; + _RAND_34 = {1{`RANDOM}}; + meicidpl = _RAND_34[3:0]; + _RAND_35 = {1{`RANDOM}}; + meipt = _RAND_35[3:0]; + _RAND_36 = {1{`RANDOM}}; + _T_700 = _RAND_36[15:0]; + _RAND_37 = {1{`RANDOM}}; + _T_725 = _RAND_37[30:0]; + _RAND_38 = {1{`RANDOM}}; + dicawics = _RAND_38[16:0]; + _RAND_39 = {3{`RANDOM}}; + dicad0 = _RAND_39[70:0]; + _RAND_40 = {1{`RANDOM}}; + dicad0h = _RAND_40[31:0]; + _RAND_41 = {1{`RANDOM}}; + _T_757 = _RAND_41[31:0]; + _RAND_42 = {1{`RANDOM}}; + icache_rd_valid_f = _RAND_42[0:0]; + _RAND_43 = {1{`RANDOM}}; + icache_wr_valid_f = _RAND_43[0:0]; + _RAND_44 = {1{`RANDOM}}; + mtsel = _RAND_44[1:0]; + _RAND_45 = {1{`RANDOM}}; + _T_871 = _RAND_45[9:0]; + _RAND_46 = {1{`RANDOM}}; + _T_872 = _RAND_46[9:0]; + _RAND_47 = {1{`RANDOM}}; + _T_873 = _RAND_47[9:0]; + _RAND_48 = {1{`RANDOM}}; + _T_874 = _RAND_48[9:0]; + _RAND_49 = {1{`RANDOM}}; + mtdata2_t_0 = _RAND_49[31:0]; + _RAND_50 = {1{`RANDOM}}; + mtdata2_t_1 = _RAND_50[31:0]; + _RAND_51 = {1{`RANDOM}}; + mtdata2_t_2 = _RAND_51[31:0]; + _RAND_52 = {1{`RANDOM}}; + mtdata2_t_3 = _RAND_52[31:0]; + _RAND_53 = {1{`RANDOM}}; + mhpme3 = _RAND_53[9:0]; + _RAND_54 = {1{`RANDOM}}; + mhpme4 = _RAND_54[9:0]; + _RAND_55 = {1{`RANDOM}}; + mhpme5 = _RAND_55[9:0]; + _RAND_56 = {1{`RANDOM}}; + mhpme6 = _RAND_56[9:0]; + _RAND_57 = {1{`RANDOM}}; + mhpmc_inc_r_d1_0 = _RAND_57[0:0]; + _RAND_58 = {1{`RANDOM}}; + mhpmc_inc_r_d1_1 = _RAND_58[0:0]; + _RAND_59 = {1{`RANDOM}}; + mhpmc_inc_r_d1_2 = _RAND_59[0:0]; + _RAND_60 = {1{`RANDOM}}; + mhpmc_inc_r_d1_3 = _RAND_60[0:0]; + _RAND_61 = {1{`RANDOM}}; + perfcnt_halted_d1 = _RAND_61[0:0]; + _RAND_62 = {1{`RANDOM}}; + mhpmc3h = _RAND_62[31:0]; + _RAND_63 = {1{`RANDOM}}; + mhpmc3 = _RAND_63[31:0]; + _RAND_64 = {1{`RANDOM}}; + mhpmc4h = _RAND_64[31:0]; + _RAND_65 = {1{`RANDOM}}; + mhpmc4 = _RAND_65[31:0]; + _RAND_66 = {1{`RANDOM}}; + mhpmc5h = _RAND_66[31:0]; + _RAND_67 = {1{`RANDOM}}; + mhpmc5 = _RAND_67[31:0]; + _RAND_68 = {1{`RANDOM}}; + mhpmc6h = _RAND_68[31:0]; + _RAND_69 = {1{`RANDOM}}; + mhpmc6 = _RAND_69[31:0]; + _RAND_70 = {1{`RANDOM}}; + _T_2325 = _RAND_70[0:0]; + _RAND_71 = {1{`RANDOM}}; + _T_2330 = _RAND_71[0:0]; + _RAND_72 = {1{`RANDOM}}; + _T_2331 = _RAND_72[4:0]; + _RAND_73 = {1{`RANDOM}}; + _T_2332 = _RAND_73[0:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + mpmc_b = 1'h0; + end + if (reset) begin + _T_54 = 2'h0; + end + if (reset) begin + _T_60 = 31'h0; + end + if (reset) begin + mdccmect = 32'h0; + end + if (reset) begin + miccmect = 32'h0; + end + if (reset) begin + micect = 32'h0; + end + if (reset) begin + _T_66 = 6'h0; + end + if (reset) begin + mie = 6'h0; + end + if (reset) begin + temp_ncount6_2 = 5'h0; + end + if (reset) begin + temp_ncount0 = 1'h0; + end + if (reset) begin + _T_95 = 33'h0; + end + if (reset) begin + mcyclel_cout_f = 1'h0; + end + if (reset) begin + mcycleh = 32'h0; + end + if (reset) begin + _T_122 = 33'h0; + end + if (reset) begin + minstret_enable_f = 1'h0; + end + if (reset) begin + minstretl_cout_f = 1'h0; + end + if (reset) begin + minstreth = 32'h0; + end + if (reset) begin + mscratch = 32'h0; + end + if (reset) begin + _T_165 = 31'h0; + end + if (reset) begin + pc_r_d1 = 31'h0; + end + if (reset) begin + _T_194 = 31'h0; + end + if (reset) begin + mcause = 32'h0; + end + if (reset) begin + mscause = 4'h0; + end + if (reset) begin + mtval = 32'h0; + end + if (reset) begin + mcgc = 9'h0; + end + if (reset) begin + mfdc_int = 15'h0; + end + if (reset) begin + mrac = 32'h0; + end + if (reset) begin + mdseac = 32'h0; + end + if (reset) begin + mfdht = 6'h0; + end + if (reset) begin + mfdhs = 2'h0; + end + if (reset) begin + force_halt_ctr_f = 32'h0; + end + if (reset) begin + meivt = 22'h0; + end + if (reset) begin + meihap = 8'h0; + end + if (reset) begin + meicurpl = 4'h0; + end + if (reset) begin + meicidpl = 4'h0; + end + if (reset) begin + meipt = 4'h0; + end + if (reset) begin + _T_700 = 16'h0; + end + if (reset) begin + _T_725 = 31'h0; + end + if (reset) begin + dicawics = 17'h0; + end + if (reset) begin + dicad0 = 71'h0; + end + if (reset) begin + dicad0h = 32'h0; + end + if (reset) begin + _T_757 = 32'h0; + end + if (reset) begin + icache_rd_valid_f = 1'h0; + end + if (reset) begin + icache_wr_valid_f = 1'h0; + end + if (reset) begin + mtsel = 2'h0; + end + if (reset) begin + _T_871 = 10'h0; + end + if (reset) begin + _T_872 = 10'h0; + end + if (reset) begin + _T_873 = 10'h0; + end + if (reset) begin + _T_874 = 10'h0; + end + if (reset) begin + mtdata2_t_0 = 32'h0; + end + if (reset) begin + mtdata2_t_1 = 32'h0; + end + if (reset) begin + mtdata2_t_2 = 32'h0; + end + if (reset) begin + mtdata2_t_3 = 32'h0; + end + if (reset) begin + mhpme3 = 10'h0; + end + if (reset) begin + mhpme4 = 10'h0; + end + if (reset) begin + mhpme5 = 10'h0; + end + if (reset) begin + mhpme6 = 10'h0; + end + if (reset) begin + mhpmc_inc_r_d1_0 = 1'h0; + end + if (reset) begin + mhpmc_inc_r_d1_1 = 1'h0; + end + if (reset) begin + mhpmc_inc_r_d1_2 = 1'h0; + end + if (reset) begin + mhpmc_inc_r_d1_3 = 1'h0; + end + if (reset) begin + perfcnt_halted_d1 = 1'h0; + end + if (reset) begin + mhpmc3h = 32'h0; + end + if (reset) begin + mhpmc3 = 32'h0; + end + if (reset) begin + mhpmc4h = 32'h0; + end + if (reset) begin + mhpmc4 = 32'h0; + end + if (reset) begin + mhpmc5h = 32'h0; + end + if (reset) begin + mhpmc5 = 32'h0; + end + if (reset) begin + mhpmc6h = 32'h0; + end + if (reset) begin + mhpmc6 = 32'h0; + end + if (reset) begin + _T_2325 = 1'h0; + end + if (reset) begin + _T_2330 = 1'h0; + end + if (reset) begin + _T_2331 = 5'h0; + end + if (reset) begin + _T_2332 = 1'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge io_csr_wr_clk or posedge reset) begin + if (reset) begin + mpmc_b <= 1'h0; + end else if (wr_mpmc_r) begin + mpmc_b <= _T_507; + end else begin + mpmc_b <= _T_508; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + _T_54 <= 2'h0; + end else begin + _T_54 <= _T_46 | _T_42; + end + end + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin + if (reset) begin + _T_60 <= 31'h0; + end else begin + _T_60 <= {io_dec_csr_wrdata_r[31:2],io_dec_csr_wrdata_r[0]}; + end + end + always @(posedge rvclkhdr_14_io_l1clk or posedge reset) begin + if (reset) begin + mdccmect <= 32'h0; + end else if (wr_mdccmect_r) begin + mdccmect <= _T_523; + end else begin + mdccmect <= _T_567; + end + end + always @(posedge rvclkhdr_13_io_l1clk or posedge reset) begin + if (reset) begin + miccmect <= 32'h0; + end else if (wr_miccmect_r) begin + miccmect <= _T_523; + end else begin + miccmect <= _T_546; + end + end + always @(posedge rvclkhdr_12_io_l1clk or posedge reset) begin + if (reset) begin + micect <= 32'h0; + end else if (wr_micect_r) begin + micect <= _T_523; + end else begin + micect <= _T_525; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + _T_66 <= 6'h0; + end else begin + _T_66 <= {_T_65,_T_63}; + end + end + always @(posedge io_csr_wr_clk or posedge reset) begin + if (reset) begin + mie <= 6'h0; + end else begin + mie <= io_mie_ns; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + temp_ncount6_2 <= 5'h0; + end else if (wr_mcountinhibit_r) begin + temp_ncount6_2 <= io_dec_csr_wrdata_r[6:2]; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + temp_ncount0 <= 1'h0; + end else if (wr_mcountinhibit_r) begin + temp_ncount0 <= io_dec_csr_wrdata_r[0]; + end + end + always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin + if (reset) begin + _T_95 <= 33'h0; + end else if (wr_mcyclel_r) begin + _T_95 <= {{1'd0}, io_dec_csr_wrdata_r}; + end else begin + _T_95 <= mcyclel_inc; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + mcyclel_cout_f <= 1'h0; + end else begin + mcyclel_cout_f <= mcyclel_cout & _T_96; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + mcycleh <= 32'h0; + end else if (wr_mcycleh_r) begin + mcycleh <= io_dec_csr_wrdata_r; + end else begin + mcycleh <= mcycleh_inc; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + _T_122 <= 33'h0; + end else if (wr_minstretl_r) begin + _T_122 <= {{1'd0}, io_dec_csr_wrdata_r}; + end else begin + _T_122 <= minstretl_inc; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + minstret_enable_f <= 1'h0; + end else begin + minstret_enable_f <= i0_valid_no_ebreak_ecall_r | wr_minstretl_r; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + minstretl_cout_f <= 1'h0; + end else begin + minstretl_cout_f <= minstretl_cout & _T_123; + end + end + always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + if (reset) begin + minstreth <= 32'h0; + end else if (wr_minstreth_r) begin + minstreth <= io_dec_csr_wrdata_r; + end else begin + minstreth <= minstreth_inc; + end + end + always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin + if (reset) begin + mscratch <= 32'h0; + end else begin + mscratch <= io_dec_csr_wrdata_r; + end + end + always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin + if (reset) begin + _T_165 <= 31'h0; + end else begin + _T_165 <= io_npc_r; + end + end + always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin + if (reset) begin + pc_r_d1 <= 31'h0; + end else begin + pc_r_d1 <= _T_169 | _T_170; + end + end + always @(posedge io_e4e5_int_clk or posedge reset) begin + if (reset) begin + _T_194 <= 31'h0; + end else begin + _T_194 <= _T_192 | _T_190; + end + end + always @(posedge io_e4e5_int_clk or posedge reset) begin + if (reset) begin + mcause <= 32'h0; + end else begin + mcause <= _T_232 | _T_228; + end + end + always @(posedge io_e4e5_int_clk or posedge reset) begin + if (reset) begin + mscause <= 4'h0; + end else begin + mscause <= _T_262 | _T_261; + end + end + always @(posedge io_e4e5_int_clk or posedge reset) begin + if (reset) begin + mtval <= 32'h0; + end else begin + mtval <= _T_319 | _T_315; + end + end + always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin + if (reset) begin + mcgc <= 9'h0; + end else begin + mcgc <= io_dec_csr_wrdata_r[8:0]; + end + end + always @(posedge rvclkhdr_9_io_l1clk or posedge reset) begin + if (reset) begin + mfdc_int <= 15'h0; + end else begin + mfdc_int <= {_T_345,_T_344}; + end + end + always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin + if (reset) begin + mrac <= 32'h0; + end else begin + mrac <= {_T_482,_T_467}; + end + end + always @(posedge rvclkhdr_11_io_l1clk or posedge reset) begin + if (reset) begin + mdseac <= 32'h0; + end else begin + mdseac <= io_lsu_imprecise_error_addr_any; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + mfdht <= 6'h0; + end else if (wr_mfdht_r) begin + mfdht <= io_dec_csr_wrdata_r[5:0]; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + mfdhs <= 2'h0; + end else if (_T_593) begin + if (wr_mfdhs_r) begin + mfdhs <= io_dec_csr_wrdata_r[1:0]; + end else if (_T_587) begin + mfdhs <= _T_591; + end + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + force_halt_ctr_f <= 32'h0; + end else if (mfdht[0]) begin + if (io_debug_halt_req_f) begin + force_halt_ctr_f <= _T_598; + end else if (io_dbg_tlu_halted_f) begin + force_halt_ctr_f <= 32'h0; + end + end + end + always @(posedge rvclkhdr_15_io_l1clk or posedge reset) begin + if (reset) begin + meivt <= 22'h0; + end else begin + meivt <= io_dec_csr_wrdata_r[31:10]; + end + end + always @(posedge rvclkhdr_16_io_l1clk or posedge reset) begin + if (reset) begin + meihap <= 8'h0; + end else begin + meihap <= io_pic_claimid; + end + end + always @(posedge io_csr_wr_clk or posedge reset) begin + if (reset) begin + meicurpl <= 4'h0; + end else if (wr_meicurpl_r) begin + meicurpl <= io_dec_csr_wrdata_r[3:0]; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + meicidpl <= 4'h0; + end else if (wr_meicpct_r) begin + meicidpl <= io_pic_pl; + end else if (wr_meicidpl_r) begin + meicidpl <= io_dec_csr_wrdata_r[3:0]; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + meipt <= 4'h0; + end else if (wr_meipt_r) begin + meipt <= io_dec_csr_wrdata_r[3:0]; + end + end + always @(posedge rvclkhdr_17_io_l1clk or posedge reset) begin + if (reset) begin + _T_700 <= 16'h0; + end else if (enter_debug_halt_req_le) begin + _T_700 <= _T_674; + end else if (wr_dcsr_r) begin + _T_700 <= _T_689; + end else begin + _T_700 <= _T_694; + end + end + always @(posedge rvclkhdr_18_io_l1clk or posedge reset) begin + if (reset) begin + _T_725 <= 31'h0; + end else begin + _T_725 <= _T_720 | _T_719; + end + end + always @(posedge rvclkhdr_19_io_l1clk or posedge reset) begin + if (reset) begin + dicawics <= 17'h0; + end else begin + dicawics <= {_T_729,io_dec_csr_wrdata_r[16:3]}; + end + end + always @(posedge rvclkhdr_20_io_l1clk or posedge reset) begin + if (reset) begin + dicad0 <= 71'h0; + end else if (wr_dicad0_r) begin + dicad0 <= {{39'd0}, io_dec_csr_wrdata_r}; + end else begin + dicad0 <= io_ifu_ic_debug_rd_data; + end + end + always @(posedge rvclkhdr_21_io_l1clk or posedge reset) begin + if (reset) begin + dicad0h <= 32'h0; + end else if (wr_dicad0h_r) begin + dicad0h <= io_dec_csr_wrdata_r; + end else begin + dicad0h <= io_ifu_ic_debug_rd_data[63:32]; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + _T_757 <= 32'h0; + end else if (_T_755) begin + if (_T_751) begin + _T_757 <= io_dec_csr_wrdata_r; + end else begin + _T_757 <= {{25'd0}, io_ifu_ic_debug_rd_data[70:64]}; + end + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + icache_rd_valid_f <= 1'h0; + end else begin + icache_rd_valid_f <= _T_767 & _T_769; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + icache_wr_valid_f <= 1'h0; + end else begin + icache_wr_valid_f <= _T_662 & _T_772; + end + end + always @(posedge io_csr_wr_clk or posedge reset) begin + if (reset) begin + mtsel <= 2'h0; + end else if (wr_mtsel_r) begin + mtsel <= io_dec_csr_wrdata_r[1:0]; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + _T_871 <= 10'h0; + end else if (wr_mtdata1_t_r_0) begin + _T_871 <= tdata_wrdata_r; + end else begin + _T_871 <= _T_842; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + _T_872 <= 10'h0; + end else if (wr_mtdata1_t_r_1) begin + _T_872 <= tdata_wrdata_r; + end else begin + _T_872 <= _T_851; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + _T_873 <= 10'h0; + end else if (wr_mtdata1_t_r_2) begin + _T_873 <= tdata_wrdata_r; + end else begin + _T_873 <= _T_860; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + _T_874 <= 10'h0; + end else if (wr_mtdata1_t_r_3) begin + _T_874 <= tdata_wrdata_r; + end else begin + _T_874 <= _T_869; + end + end + always @(posedge rvclkhdr_22_io_l1clk or posedge reset) begin + if (reset) begin + mtdata2_t_0 <= 32'h0; + end else begin + mtdata2_t_0 <= io_dec_csr_wrdata_r; + end + end + always @(posedge rvclkhdr_23_io_l1clk or posedge reset) begin + if (reset) begin + mtdata2_t_1 <= 32'h0; + end else begin + mtdata2_t_1 <= io_dec_csr_wrdata_r; + end + end + always @(posedge rvclkhdr_24_io_l1clk or posedge reset) begin + if (reset) begin + mtdata2_t_2 <= 32'h0; + end else begin + mtdata2_t_2 <= io_dec_csr_wrdata_r; + end + end + always @(posedge rvclkhdr_25_io_l1clk or posedge reset) begin + if (reset) begin + mtdata2_t_3 <= 32'h0; + end else begin + mtdata2_t_3 <= io_dec_csr_wrdata_r; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + mhpme3 <= 10'h0; + end else if (wr_mhpme3_r) begin + if (_T_2287) begin + mhpme3 <= 10'h204; + end else begin + mhpme3 <= io_dec_csr_wrdata_r[9:0]; + end + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + mhpme4 <= 10'h0; + end else if (wr_mhpme4_r) begin + if (_T_2287) begin + mhpme4 <= 10'h204; + end else begin + mhpme4 <= io_dec_csr_wrdata_r[9:0]; + end + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + mhpme5 <= 10'h0; + end else if (wr_mhpme5_r) begin + if (_T_2287) begin + mhpme5 <= 10'h204; + end else begin + mhpme5 <= io_dec_csr_wrdata_r[9:0]; + end + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + mhpme6 <= 10'h0; + end else if (wr_mhpme6_r) begin + if (_T_2287) begin + mhpme6 <= 10'h204; + end else begin + mhpme6 <= io_dec_csr_wrdata_r[9:0]; + end + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + mhpmc_inc_r_d1_0 <= 1'h0; + end else begin + mhpmc_inc_r_d1_0 <= _T_1305[0]; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + mhpmc_inc_r_d1_1 <= 1'h0; + end else begin + mhpmc_inc_r_d1_1 <= _T_1588[0]; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + mhpmc_inc_r_d1_2 <= 1'h0; + end else begin + mhpmc_inc_r_d1_2 <= _T_1871[0]; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + mhpmc_inc_r_d1_3 <= 1'h0; + end else begin + mhpmc_inc_r_d1_3 <= _T_2154[0]; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + perfcnt_halted_d1 <= 1'h0; + end else begin + perfcnt_halted_d1 <= _T_83 | io_dec_tlu_pmu_fw_halted; + end + end + always @(posedge rvclkhdr_27_io_l1clk or posedge reset) begin + if (reset) begin + mhpmc3h <= 32'h0; + end else if (mhpmc3h_wr_en0) begin + mhpmc3h <= io_dec_csr_wrdata_r; + end else begin + mhpmc3h <= mhpmc3_incr[63:32]; + end + end + always @(posedge rvclkhdr_26_io_l1clk or posedge reset) begin + if (reset) begin + mhpmc3 <= 32'h0; + end else if (mhpmc3_wr_en0) begin + mhpmc3 <= io_dec_csr_wrdata_r; + end else begin + mhpmc3 <= mhpmc3_incr[31:0]; + end + end + always @(posedge rvclkhdr_29_io_l1clk or posedge reset) begin + if (reset) begin + mhpmc4h <= 32'h0; + end else if (mhpmc4h_wr_en0) begin + mhpmc4h <= io_dec_csr_wrdata_r; + end else begin + mhpmc4h <= mhpmc4_incr[63:32]; + end + end + always @(posedge rvclkhdr_28_io_l1clk or posedge reset) begin + if (reset) begin + mhpmc4 <= 32'h0; + end else if (mhpmc4_wr_en0) begin + mhpmc4 <= io_dec_csr_wrdata_r; + end else begin + mhpmc4 <= mhpmc4_incr[31:0]; + end + end + always @(posedge rvclkhdr_31_io_l1clk or posedge reset) begin + if (reset) begin + mhpmc5h <= 32'h0; + end else if (mhpmc5h_wr_en0) begin + mhpmc5h <= io_dec_csr_wrdata_r; + end else begin + mhpmc5h <= mhpmc5_incr[63:32]; + end + end + always @(posedge rvclkhdr_30_io_l1clk or posedge reset) begin + if (reset) begin + mhpmc5 <= 32'h0; + end else if (mhpmc5_wr_en0) begin + mhpmc5 <= io_dec_csr_wrdata_r; + end else begin + mhpmc5 <= mhpmc5_incr[31:0]; + end + end + always @(posedge rvclkhdr_33_io_l1clk or posedge reset) begin + if (reset) begin + mhpmc6h <= 32'h0; + end else if (mhpmc6h_wr_en0) begin + mhpmc6h <= io_dec_csr_wrdata_r; + end else begin + mhpmc6h <= mhpmc6_incr[63:32]; + end + end + always @(posedge rvclkhdr_32_io_l1clk or posedge reset) begin + if (reset) begin + mhpmc6 <= 32'h0; + end else if (mhpmc6_wr_en0) begin + mhpmc6 <= io_dec_csr_wrdata_r; + end else begin + mhpmc6 <= mhpmc6_incr[31:0]; + end + end + always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin + if (reset) begin + _T_2325 <= 1'h0; + end else begin + _T_2325 <= io_i0_valid_wb; + end + end + always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin + if (reset) begin + _T_2330 <= 1'h0; + end else begin + _T_2330 <= _T_2326 | _T_2328; + end + end + always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin + if (reset) begin + _T_2331 <= 5'h0; + end else begin + _T_2331 <= io_exc_cause_wb; + end + end + always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin + if (reset) begin + _T_2332 <= 1'h0; + end else begin + _T_2332 <= io_interrupt_valid_r_d1; + end + end +endmodule +module el2_dec_decode_csr_read( + input [11:0] io_dec_csr_rdaddr_d, + output io_csr_pkt_csr_misa, + output io_csr_pkt_csr_mvendorid, + output io_csr_pkt_csr_marchid, + output io_csr_pkt_csr_mimpid, + output io_csr_pkt_csr_mhartid, + output io_csr_pkt_csr_mstatus, + output io_csr_pkt_csr_mtvec, + output io_csr_pkt_csr_mip, + output io_csr_pkt_csr_mie, + output io_csr_pkt_csr_mcyclel, + output io_csr_pkt_csr_mcycleh, + output io_csr_pkt_csr_minstretl, + output io_csr_pkt_csr_minstreth, + output io_csr_pkt_csr_mscratch, + output io_csr_pkt_csr_mepc, + output io_csr_pkt_csr_mcause, + output io_csr_pkt_csr_mscause, + output io_csr_pkt_csr_mtval, + output io_csr_pkt_csr_mrac, + output io_csr_pkt_csr_dmst, + output io_csr_pkt_csr_mdseac, + output io_csr_pkt_csr_meihap, + output io_csr_pkt_csr_meivt, + output io_csr_pkt_csr_meipt, + output io_csr_pkt_csr_meicurpl, + output io_csr_pkt_csr_meicidpl, + output io_csr_pkt_csr_dcsr, + output io_csr_pkt_csr_mcgc, + output io_csr_pkt_csr_mfdc, + output io_csr_pkt_csr_dpc, + output io_csr_pkt_csr_mtsel, + output io_csr_pkt_csr_mtdata1, + output io_csr_pkt_csr_mtdata2, + output io_csr_pkt_csr_mhpmc3, + output io_csr_pkt_csr_mhpmc4, + output io_csr_pkt_csr_mhpmc5, + output io_csr_pkt_csr_mhpmc6, + output io_csr_pkt_csr_mhpmc3h, + output io_csr_pkt_csr_mhpmc4h, + output io_csr_pkt_csr_mhpmc5h, + output io_csr_pkt_csr_mhpmc6h, + output io_csr_pkt_csr_mhpme3, + output io_csr_pkt_csr_mhpme4, + output io_csr_pkt_csr_mhpme5, + output io_csr_pkt_csr_mhpme6, + output io_csr_pkt_csr_mcountinhibit, + output io_csr_pkt_csr_mitctl0, + output io_csr_pkt_csr_mitctl1, + output io_csr_pkt_csr_mitb0, + output io_csr_pkt_csr_mitb1, + output io_csr_pkt_csr_mitcnt0, + output io_csr_pkt_csr_mitcnt1, + output io_csr_pkt_csr_mpmc, + output io_csr_pkt_csr_meicpct, + output io_csr_pkt_csr_micect, + output io_csr_pkt_csr_miccmect, + output io_csr_pkt_csr_mdccmect, + output io_csr_pkt_csr_mfdht, + output io_csr_pkt_csr_mfdhs, + output io_csr_pkt_csr_dicawics, + output io_csr_pkt_csr_dicad0h, + output io_csr_pkt_csr_dicad0, + output io_csr_pkt_csr_dicad1, + output io_csr_pkt_csr_dicago, + output io_csr_pkt_presync, + output io_csr_pkt_postsync, + output io_csr_pkt_legal +); + wire _T_1 = ~io_dec_csr_rdaddr_d[11]; // @[el2_dec_tlu_ctl.scala 2648:123] + wire _T_3 = ~io_dec_csr_rdaddr_d[6]; // @[el2_dec_tlu_ctl.scala 2648:123] + wire _T_5 = ~io_dec_csr_rdaddr_d[5]; // @[el2_dec_tlu_ctl.scala 2648:123] + wire _T_7 = ~io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:123] + wire _T_9 = _T_1 & _T_3; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_10 = _T_9 & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_11 = _T_10 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_15 = ~io_dec_csr_rdaddr_d[7]; // @[el2_dec_tlu_ctl.scala 2648:123] + wire _T_17 = ~io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:123] + wire _T_19 = io_dec_csr_rdaddr_d[10] & _T_15; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_20 = _T_19 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_27 = ~io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2648:159] + wire _T_29 = _T_19 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_36 = io_dec_csr_rdaddr_d[10] & _T_3; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_37 = _T_36 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_69 = _T_10 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_70 = _T_69 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_75 = _T_15 & io_dec_csr_rdaddr_d[6]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_94 = ~io_dec_csr_rdaddr_d[4]; // @[el2_dec_tlu_ctl.scala 2648:123] + wire _T_96 = ~io_dec_csr_rdaddr_d[3]; // @[el2_dec_tlu_ctl.scala 2648:123] + wire _T_101 = io_dec_csr_rdaddr_d[11] & _T_15; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_102 = _T_101 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_103 = _T_102 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_104 = _T_103 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_119 = io_dec_csr_rdaddr_d[7] & _T_3; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_120 = _T_119 & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_121 = _T_120 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_122 = _T_121 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_123 = _T_122 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_138 = _T_15 & _T_3; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_139 = _T_138 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_140 = _T_139 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_141 = _T_140 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_142 = _T_141 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_145 = ~io_dec_csr_rdaddr_d[10]; // @[el2_dec_tlu_ctl.scala 2648:123] + wire _T_156 = _T_145 & io_dec_csr_rdaddr_d[7]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_157 = _T_156 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_158 = _T_157 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_159 = _T_158 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_160 = _T_159 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_172 = _T_75 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_173 = _T_172 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_182 = _T_75 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_183 = _T_182 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_191 = _T_75 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_196 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[5]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_217 = _T_1 & io_dec_csr_rdaddr_d[7]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_218 = _T_217 & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_219 = _T_218 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_220 = _T_219 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_230 = io_dec_csr_rdaddr_d[10] & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_231 = _T_230 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_232 = _T_231 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_240 = io_dec_csr_rdaddr_d[11] & io_dec_csr_rdaddr_d[10]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_241 = _T_240 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_258 = _T_145 & io_dec_csr_rdaddr_d[6]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_259 = _T_258 & io_dec_csr_rdaddr_d[3]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_260 = _T_259 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_261 = _T_260 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_268 = io_dec_csr_rdaddr_d[11] & io_dec_csr_rdaddr_d[6]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_269 = _T_268 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_281 = _T_268 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_291 = _T_36 & io_dec_csr_rdaddr_d[5]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_292 = _T_291 & io_dec_csr_rdaddr_d[4]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_299 = io_dec_csr_rdaddr_d[10] & io_dec_csr_rdaddr_d[4]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_300 = _T_299 & io_dec_csr_rdaddr_d[3]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_310 = _T_300 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_311 = _T_310 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_330 = io_dec_csr_rdaddr_d[10] & io_dec_csr_rdaddr_d[5]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_331 = _T_330 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_332 = _T_331 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_342 = _T_231 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_381 = _T_103 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_382 = _T_381 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_397 = _T_103 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_411 = _T_15 & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_412 = _T_411 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_413 = _T_412 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_414 = _T_413 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_415 = _T_414 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_426 = io_dec_csr_rdaddr_d[7] & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_427 = _T_426 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_428 = _T_427 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_429 = _T_428 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_444 = _T_119 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_445 = _T_444 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_446 = _T_445 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_447 = _T_446 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_460 = _T_427 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_461 = _T_460 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_478 = _T_446 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_490 = _T_15 & io_dec_csr_rdaddr_d[5]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_491 = _T_490 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_492 = _T_491 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_493 = _T_492 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_505 = io_dec_csr_rdaddr_d[5] & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_506 = _T_505 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_507 = _T_506 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_508 = _T_507 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_536 = _T_507 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_553 = _T_493 & _T_27; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_562 = io_dec_csr_rdaddr_d[6] & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_563 = _T_562 & io_dec_csr_rdaddr_d[4]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_564 = _T_563 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_572 = io_dec_csr_rdaddr_d[6] & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_573 = _T_572 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_574 = _T_573 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_585 = _T_563 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_593 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[4]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_594 = _T_593 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_595 = _T_594 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_614 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_615 = _T_614 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_624 = io_dec_csr_rdaddr_d[6] & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_625 = _T_624 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_626 = _T_625 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_668 = _T_196 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_669 = _T_668 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_685 = _T_196 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_693 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[3]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_694 = _T_693 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_695 = _T_694 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_703 = _T_624 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_716 = _T_1 & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_717 = _T_716 & io_dec_csr_rdaddr_d[3]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_718 = _T_717 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_719 = _T_718 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_726 = io_dec_csr_rdaddr_d[10] & io_dec_csr_rdaddr_d[3]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_727 = _T_726 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_737 = _T_230 & io_dec_csr_rdaddr_d[3]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_738 = _T_737 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_748 = _T_726 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_749 = _T_748 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_787 = _T_311 | _T_553; // @[el2_dec_tlu_ctl.scala 2716:73] + wire _T_799 = _T_3 & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_800 = _T_799 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_801 = _T_800 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_802 = _T_801 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_803 = _T_802 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_804 = _T_787 | _T_803; // @[el2_dec_tlu_ctl.scala 2716:113] + wire _T_813 = io_dec_csr_rdaddr_d[11] & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_814 = _T_813 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_815 = _T_814 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_816 = _T_815 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_817 = _T_804 | _T_816; // @[el2_dec_tlu_ctl.scala 2716:147] + wire _T_828 = _T_814 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_829 = _T_828 & _T_27; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_830 = _T_817 | _T_829; // @[el2_dec_tlu_ctl.scala 2717:41] + wire _T_841 = io_dec_csr_rdaddr_d[7] & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_842 = _T_841 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_843 = _T_842 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_844 = _T_843 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_845 = _T_844 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_869 = _T_311 | _T_70; // @[el2_dec_tlu_ctl.scala 2718:73] + wire _T_879 = _T_869 | _T_183; // @[el2_dec_tlu_ctl.scala 2718:113] + wire _T_889 = _T_879 | _T_342; // @[el2_dec_tlu_ctl.scala 2718:154] + wire _T_904 = _T_1 & _T_15; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_905 = _T_904 & _T_3; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_906 = _T_905 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_907 = _T_906 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_908 = _T_907 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_909 = _T_908 & _T_27; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_910 = _T_889 | _T_909; // @[el2_dec_tlu_ctl.scala 2719:41] + wire _T_922 = _T_217 & io_dec_csr_rdaddr_d[6]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_923 = _T_922 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_924 = _T_923 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_925 = _T_924 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_926 = _T_910 | _T_925; // @[el2_dec_tlu_ctl.scala 2719:81] + wire _T_937 = _T_231 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_938 = _T_937 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_955 = _T_1 & io_dec_csr_rdaddr_d[10]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_956 = _T_955 & io_dec_csr_rdaddr_d[9]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_957 = _T_956 & io_dec_csr_rdaddr_d[8]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_958 = _T_957 & io_dec_csr_rdaddr_d[7]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_959 = _T_958 & io_dec_csr_rdaddr_d[6]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_960 = _T_959 & io_dec_csr_rdaddr_d[4]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_961 = _T_960 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_962 = _T_961 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_963 = _T_962 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_964 = _T_963 & _T_27; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_983 = _T_1 & _T_145; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_984 = _T_983 & io_dec_csr_rdaddr_d[9]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_985 = _T_984 & io_dec_csr_rdaddr_d[8]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_986 = _T_985 & _T_15; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_987 = _T_986 & _T_3; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_988 = _T_987 & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_989 = _T_988 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_990 = _T_989 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_991 = _T_990 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_992 = _T_964 | _T_991; // @[el2_dec_tlu_ctl.scala 2721:73] + wire _T_1013 = _T_987 & io_dec_csr_rdaddr_d[5]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1014 = _T_1013 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1015 = _T_1014 & _T_27; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1016 = _T_992 | _T_1015; // @[el2_dec_tlu_ctl.scala 2721:121] + wire _T_1032 = io_dec_csr_rdaddr_d[11] & io_dec_csr_rdaddr_d[9]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1033 = _T_1032 & io_dec_csr_rdaddr_d[8]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1034 = _T_1033 & io_dec_csr_rdaddr_d[7]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1035 = _T_1034 & io_dec_csr_rdaddr_d[6]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1036 = _T_1035 & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1037 = _T_1036 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1038 = _T_1037 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1039 = _T_1038 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1040 = _T_1039 & _T_27; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1041 = _T_1016 | _T_1040; // @[el2_dec_tlu_ctl.scala 2722:57] + wire _T_1053 = io_dec_csr_rdaddr_d[11] & _T_145; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1054 = _T_1053 & io_dec_csr_rdaddr_d[9]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1055 = _T_1054 & io_dec_csr_rdaddr_d[8]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1056 = _T_1055 & _T_3; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1057 = _T_1056 & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1058 = _T_1057 & _T_27; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1059 = _T_1041 | _T_1058; // @[el2_dec_tlu_ctl.scala 2722:105] + wire _T_1078 = _T_959 & io_dec_csr_rdaddr_d[5]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1079 = _T_1078 & io_dec_csr_rdaddr_d[4]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1080 = _T_1079 & io_dec_csr_rdaddr_d[3]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1081 = _T_1080 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1082 = _T_1081 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1083 = _T_1082 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1084 = _T_1059 | _T_1083; // @[el2_dec_tlu_ctl.scala 2723:65] + wire _T_1105 = _T_1079 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1106 = _T_1105 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1107 = _T_1084 | _T_1106; // @[el2_dec_tlu_ctl.scala 2723:113] + wire _T_1125 = _T_1033 & _T_15; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1126 = _T_1125 & _T_3; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1127 = _T_1126 & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1128 = _T_1127 & io_dec_csr_rdaddr_d[4]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1129 = _T_1128 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1130 = _T_1129 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1131 = _T_1130 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1132 = _T_1107 | _T_1131; // @[el2_dec_tlu_ctl.scala 2724:57] + wire _T_1152 = _T_958 & _T_3; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1153 = _T_1152 & io_dec_csr_rdaddr_d[5]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1154 = _T_1153 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1155 = _T_1154 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1156 = _T_1155 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1157 = _T_1132 | _T_1156; // @[el2_dec_tlu_ctl.scala 2724:113] + wire _T_1176 = _T_1013 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1177 = _T_1157 | _T_1176; // @[el2_dec_tlu_ctl.scala 2725:57] + wire _T_1202 = _T_1129 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1203 = _T_1202 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1204 = _T_1203 & _T_27; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1205 = _T_1177 | _T_1204; // @[el2_dec_tlu_ctl.scala 2725:113] + wire _T_1224 = _T_959 & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1225 = _T_1224 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1226 = _T_1225 & io_dec_csr_rdaddr_d[3]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1227 = _T_1226 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1228 = _T_1205 | _T_1227; // @[el2_dec_tlu_ctl.scala 2726:57] + wire _T_1248 = _T_1224 & io_dec_csr_rdaddr_d[4]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1249 = _T_1248 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1250 = _T_1249 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1251 = _T_1228 | _T_1250; // @[el2_dec_tlu_ctl.scala 2726:113] + wire _T_1275 = _T_1130 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1276 = _T_1251 | _T_1275; // @[el2_dec_tlu_ctl.scala 2727:57] + wire _T_1296 = _T_1013 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1297 = _T_1296 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1298 = _T_1276 | _T_1297; // @[el2_dec_tlu_ctl.scala 2727:113] + wire _T_1315 = _T_1055 & io_dec_csr_rdaddr_d[7]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1316 = _T_1315 & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1317 = _T_1316 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1318 = _T_1317 & io_dec_csr_rdaddr_d[3]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1319 = _T_1318 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1320 = _T_1298 | _T_1319; // @[el2_dec_tlu_ctl.scala 2728:65] + wire _T_1343 = _T_1318 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1344 = _T_1343 & _T_27; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1345 = _T_1320 | _T_1344; // @[el2_dec_tlu_ctl.scala 2728:121] + wire _T_1361 = _T_1057 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1362 = _T_1345 | _T_1361; // @[el2_dec_tlu_ctl.scala 2729:57] + wire _T_1384 = _T_1249 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1385 = _T_1362 | _T_1384; // @[el2_dec_tlu_ctl.scala 2729:113] + wire _T_1406 = _T_1225 & _T_27; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1407 = _T_1385 | _T_1406; // @[el2_dec_tlu_ctl.scala 2730:57] + wire _T_1430 = _T_1226 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1431 = _T_1407 | _T_1430; // @[el2_dec_tlu_ctl.scala 2730:113] + wire _T_1455 = _T_1153 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1456 = _T_1455 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1457 = _T_1456 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1458 = _T_1457 & _T_27; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1459 = _T_1431 | _T_1458; // @[el2_dec_tlu_ctl.scala 2731:57] + wire _T_1475 = _T_1057 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1476 = _T_1459 | _T_1475; // @[el2_dec_tlu_ctl.scala 2731:105] + wire _T_1498 = _T_986 & io_dec_csr_rdaddr_d[6]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1499 = _T_1498 & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1500 = _T_1499 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1501 = _T_1500 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1502 = _T_1501 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1503 = _T_1476 | _T_1502; // @[el2_dec_tlu_ctl.scala 2732:65] + wire _T_1526 = _T_986 & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1527 = _T_1526 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1528 = _T_1527 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1529 = _T_1528 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1530 = _T_1529 & _T_27; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1531 = _T_1503 | _T_1530; // @[el2_dec_tlu_ctl.scala 2732:113] + wire _T_1550 = _T_1013 & io_dec_csr_rdaddr_d[3]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1551 = _T_1531 | _T_1550; // @[el2_dec_tlu_ctl.scala 2733:57] + wire _T_1567 = _T_1057 & io_dec_csr_rdaddr_d[3]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1568 = _T_1551 | _T_1567; // @[el2_dec_tlu_ctl.scala 2733:113] + wire _T_1587 = _T_1013 & io_dec_csr_rdaddr_d[4]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1588 = _T_1568 | _T_1587; // @[el2_dec_tlu_ctl.scala 2734:65] + wire _T_1604 = _T_1057 & io_dec_csr_rdaddr_d[4]; // @[el2_dec_tlu_ctl.scala 2648:192] + assign io_csr_pkt_csr_misa = _T_11 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2650:49] + assign io_csr_pkt_csr_mvendorid = _T_20 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2651:49] + assign io_csr_pkt_csr_marchid = _T_29 & _T_27; // @[el2_dec_tlu_ctl.scala 2652:57] + assign io_csr_pkt_csr_mimpid = _T_37 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2653:57] + assign io_csr_pkt_csr_mhartid = _T_19 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2654:57] + assign io_csr_pkt_csr_mstatus = _T_11 & _T_27; // @[el2_dec_tlu_ctl.scala 2655:57] + assign io_csr_pkt_csr_mtvec = _T_69 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2656:49] + assign io_csr_pkt_csr_mip = _T_75 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2657:57] + assign io_csr_pkt_csr_mie = _T_69 & _T_27; // @[el2_dec_tlu_ctl.scala 2658:57] + assign io_csr_pkt_csr_mcyclel = _T_104 & _T_17; // @[el2_dec_tlu_ctl.scala 2659:57] + assign io_csr_pkt_csr_mcycleh = _T_123 & _T_17; // @[el2_dec_tlu_ctl.scala 2660:57] + assign io_csr_pkt_csr_minstretl = _T_142 & _T_27; // @[el2_dec_tlu_ctl.scala 2661:49] + assign io_csr_pkt_csr_minstreth = _T_160 & _T_27; // @[el2_dec_tlu_ctl.scala 2662:49] + assign io_csr_pkt_csr_mscratch = _T_173 & _T_27; // @[el2_dec_tlu_ctl.scala 2663:49] + assign io_csr_pkt_csr_mepc = _T_182 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2664:49] + assign io_csr_pkt_csr_mcause = _T_191 & _T_27; // @[el2_dec_tlu_ctl.scala 2665:57] + assign io_csr_pkt_csr_mscause = _T_196 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2666:57] + assign io_csr_pkt_csr_mtval = _T_191 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2667:49] + assign io_csr_pkt_csr_mrac = _T_220 & _T_17; // @[el2_dec_tlu_ctl.scala 2668:49] + assign io_csr_pkt_csr_dmst = _T_232 & _T_17; // @[el2_dec_tlu_ctl.scala 2669:49] + assign io_csr_pkt_csr_mdseac = _T_241 & _T_96; // @[el2_dec_tlu_ctl.scala 2670:57] + assign io_csr_pkt_csr_meihap = _T_240 & io_dec_csr_rdaddr_d[3]; // @[el2_dec_tlu_ctl.scala 2671:57] + assign io_csr_pkt_csr_meivt = _T_261 & _T_27; // @[el2_dec_tlu_ctl.scala 2672:49] + assign io_csr_pkt_csr_meipt = _T_269 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2673:49] + assign io_csr_pkt_csr_meicurpl = _T_268 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2674:49] + assign io_csr_pkt_csr_meicidpl = _T_281 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2675:49] + assign io_csr_pkt_csr_dcsr = _T_292 & _T_27; // @[el2_dec_tlu_ctl.scala 2676:49] + assign io_csr_pkt_csr_mcgc = _T_300 & _T_27; // @[el2_dec_tlu_ctl.scala 2677:49] + assign io_csr_pkt_csr_mfdc = _T_310 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2678:49] + assign io_csr_pkt_csr_dpc = _T_292 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2679:57] + assign io_csr_pkt_csr_mtsel = _T_332 & _T_27; // @[el2_dec_tlu_ctl.scala 2680:49] + assign io_csr_pkt_csr_mtdata1 = _T_231 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2681:57] + assign io_csr_pkt_csr_mtdata2 = _T_331 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2682:57] + assign io_csr_pkt_csr_mhpmc3 = _T_104 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2683:57] + assign io_csr_pkt_csr_mhpmc4 = _T_382 & _T_27; // @[el2_dec_tlu_ctl.scala 2684:57] + assign io_csr_pkt_csr_mhpmc5 = _T_397 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2685:57] + assign io_csr_pkt_csr_mhpmc6 = _T_415 & _T_27; // @[el2_dec_tlu_ctl.scala 2686:57] + assign io_csr_pkt_csr_mhpmc3h = _T_429 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2687:57] + assign io_csr_pkt_csr_mhpmc4h = _T_447 & _T_27; // @[el2_dec_tlu_ctl.scala 2688:57] + assign io_csr_pkt_csr_mhpmc5h = _T_461 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2689:57] + assign io_csr_pkt_csr_mhpmc6h = _T_478 & _T_27; // @[el2_dec_tlu_ctl.scala 2690:57] + assign io_csr_pkt_csr_mhpme3 = _T_493 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2691:57] + assign io_csr_pkt_csr_mhpme4 = _T_508 & _T_27; // @[el2_dec_tlu_ctl.scala 2692:57] + assign io_csr_pkt_csr_mhpme5 = _T_508 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2693:57] + assign io_csr_pkt_csr_mhpme6 = _T_536 & _T_27; // @[el2_dec_tlu_ctl.scala 2694:57] + assign io_csr_pkt_csr_mcountinhibit = _T_493 & _T_27; // @[el2_dec_tlu_ctl.scala 2695:41] + assign io_csr_pkt_csr_mitctl0 = _T_564 & _T_27; // @[el2_dec_tlu_ctl.scala 2696:57] + assign io_csr_pkt_csr_mitctl1 = _T_574 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2697:57] + assign io_csr_pkt_csr_mitb0 = _T_585 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2698:49] + assign io_csr_pkt_csr_mitb1 = _T_595 & _T_27; // @[el2_dec_tlu_ctl.scala 2699:49] + assign io_csr_pkt_csr_mitcnt0 = _T_585 & _T_27; // @[el2_dec_tlu_ctl.scala 2700:57] + assign io_csr_pkt_csr_mitcnt1 = _T_615 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2701:57] + assign io_csr_pkt_csr_mpmc = _T_626 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2702:49] + assign io_csr_pkt_csr_meicpct = _T_281 & _T_27; // @[el2_dec_tlu_ctl.scala 2704:57] + assign io_csr_pkt_csr_micect = _T_669 & _T_27; // @[el2_dec_tlu_ctl.scala 2706:57] + assign io_csr_pkt_csr_miccmect = _T_668 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2707:49] + assign io_csr_pkt_csr_mdccmect = _T_685 & _T_27; // @[el2_dec_tlu_ctl.scala 2708:49] + assign io_csr_pkt_csr_mfdht = _T_695 & _T_27; // @[el2_dec_tlu_ctl.scala 2709:49] + assign io_csr_pkt_csr_mfdhs = _T_703 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2710:49] + assign io_csr_pkt_csr_dicawics = _T_719 & _T_27; // @[el2_dec_tlu_ctl.scala 2711:49] + assign io_csr_pkt_csr_dicad0h = _T_727 & _T_17; // @[el2_dec_tlu_ctl.scala 2712:57] + assign io_csr_pkt_csr_dicad0 = _T_738 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2713:57] + assign io_csr_pkt_csr_dicad1 = _T_749 & _T_27; // @[el2_dec_tlu_ctl.scala 2714:57] + assign io_csr_pkt_csr_dicago = _T_749 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2715:57] + assign io_csr_pkt_presync = _T_830 | _T_845; // @[el2_dec_tlu_ctl.scala 2716:26] + assign io_csr_pkt_postsync = _T_926 | _T_938; // @[el2_dec_tlu_ctl.scala 2718:24] + assign io_csr_pkt_legal = _T_1588 | _T_1604; // @[el2_dec_tlu_ctl.scala 2721:20] +endmodule +module el2_dec_tlu_ctl( + input clock, + input reset, + input io_active_clk, + input io_free_clk, + input io_scan_mode, + input [30:0] io_rst_vec, + input io_nmi_int, + input [30:0] io_nmi_vec, + input io_i_cpu_halt_req, + input io_i_cpu_run_req, + input io_lsu_fastint_stall_any, + input io_ifu_pmu_instr_aligned, + input io_ifu_pmu_fetch_stall, + input io_ifu_pmu_ic_miss, + input io_ifu_pmu_ic_hit, + input io_ifu_pmu_bus_error, + input io_ifu_pmu_bus_busy, + input io_ifu_pmu_bus_trxn, + input io_dec_pmu_instr_decoded, + input io_dec_pmu_decode_stall, + input io_dec_pmu_presync_stall, + input io_dec_pmu_postsync_stall, + input io_lsu_store_stall_any, + input io_dma_dccm_stall_any, + input io_dma_iccm_stall_any, + input io_exu_pmu_i0_br_misp, + input io_exu_pmu_i0_br_ataken, + input io_exu_pmu_i0_pc4, + input io_lsu_pmu_bus_trxn, + input io_lsu_pmu_bus_misaligned, + input io_lsu_pmu_bus_error, + input io_lsu_pmu_bus_busy, + input io_lsu_pmu_load_external_m, + input io_lsu_pmu_store_external_m, + input io_dma_pmu_dccm_read, + input io_dma_pmu_dccm_write, + input io_dma_pmu_any_read, + input io_dma_pmu_any_write, + input [30:0] io_lsu_fir_addr, + input [1:0] io_lsu_fir_error, + input io_iccm_dma_sb_error, + input io_lsu_error_pkt_r_valid, + input io_lsu_error_pkt_r_bits_single_ecc_error, + input io_lsu_error_pkt_r_bits_inst_type, + input io_lsu_error_pkt_r_bits_exc_type, + input [3:0] io_lsu_error_pkt_r_bits_mscause, + input [31:0] io_lsu_error_pkt_r_bits_addr, + input io_lsu_single_ecc_error_incr, + input io_dec_pause_state, + input io_lsu_imprecise_error_store_any, + input io_lsu_imprecise_error_load_any, + input [31:0] io_lsu_imprecise_error_addr_any, + input io_dec_csr_wen_unq_d, + input io_dec_csr_any_unq_d, + input [11:0] io_dec_csr_rdaddr_d, + input io_dec_csr_wen_r, + input [11:0] io_dec_csr_wraddr_r, + input [31:0] io_dec_csr_wrdata_r, + input io_dec_csr_stall_int_ff, + input io_dec_tlu_i0_valid_r, + input [30:0] io_exu_npc_r, + input [30:0] io_dec_tlu_i0_pc_r, + input io_dec_tlu_packet_r_legal, + input io_dec_tlu_packet_r_icaf, + input io_dec_tlu_packet_r_icaf_f1, + input [1:0] io_dec_tlu_packet_r_icaf_type, + input io_dec_tlu_packet_r_fence_i, + input [3:0] io_dec_tlu_packet_r_i0trigger, + input [3:0] io_dec_tlu_packet_r_pmu_i0_itype, + input io_dec_tlu_packet_r_pmu_i0_br_unpred, + input io_dec_tlu_packet_r_pmu_divide, + input io_dec_tlu_packet_r_pmu_lsu_misaligned, + input [31:0] io_dec_illegal_inst, + input io_dec_i0_decode_d, + input [1:0] io_exu_i0_br_hist_r, + input io_exu_i0_br_error_r, + input io_exu_i0_br_start_error_r, + input io_exu_i0_br_valid_r, + input io_exu_i0_br_mp_r, + input io_exu_i0_br_middle_r, + input io_exu_i0_br_way_r, + output io_dec_dbg_cmd_done, + output io_dec_dbg_cmd_fail, + output io_dec_tlu_dbg_halted, + output io_dec_tlu_debug_mode, + output io_dec_tlu_resume_ack, + output io_dec_tlu_debug_stall, + output io_dec_tlu_flush_noredir_r, + output io_dec_tlu_mpc_halted_only, + output io_dec_tlu_flush_leak_one_r, + output io_dec_tlu_flush_err_r, + output io_dec_tlu_flush_extint, + output [29:0] io_dec_tlu_meihap, + input io_dbg_halt_req, + input io_dbg_resume_req, + input io_ifu_miss_state_idle, + input io_lsu_idle_any, + input io_dec_div_active, + output io_trigger_pkt_any_0_select, + output io_trigger_pkt_any_0_match_pkt, + output io_trigger_pkt_any_0_store, + output io_trigger_pkt_any_0_load, + output io_trigger_pkt_any_0_execute, + output io_trigger_pkt_any_0_m, + output [31:0] io_trigger_pkt_any_0_tdata2, + output io_trigger_pkt_any_1_select, + output io_trigger_pkt_any_1_match_pkt, + output io_trigger_pkt_any_1_store, + output io_trigger_pkt_any_1_load, + output io_trigger_pkt_any_1_execute, + output io_trigger_pkt_any_1_m, + output [31:0] io_trigger_pkt_any_1_tdata2, + output io_trigger_pkt_any_2_select, + output io_trigger_pkt_any_2_match_pkt, + output io_trigger_pkt_any_2_store, + output io_trigger_pkt_any_2_load, + output io_trigger_pkt_any_2_execute, + output io_trigger_pkt_any_2_m, + output [31:0] io_trigger_pkt_any_2_tdata2, + output io_trigger_pkt_any_3_select, + output io_trigger_pkt_any_3_match_pkt, + output io_trigger_pkt_any_3_store, + output io_trigger_pkt_any_3_load, + output io_trigger_pkt_any_3_execute, + output io_trigger_pkt_any_3_m, + output [31:0] io_trigger_pkt_any_3_tdata2, + input io_ifu_ic_error_start, + input io_ifu_iccm_rd_ecc_single_err, + input [70:0] io_ifu_ic_debug_rd_data, + input io_ifu_ic_debug_rd_data_valid, + output [70:0] io_dec_tlu_ic_diag_pkt_icache_wrdata, + output [16:0] io_dec_tlu_ic_diag_pkt_icache_dicawics, + output io_dec_tlu_ic_diag_pkt_icache_rd_valid, + output io_dec_tlu_ic_diag_pkt_icache_wr_valid, + input [7:0] io_pic_claimid, + input [3:0] io_pic_pl, + input io_mhwakeup, + input io_mexintpend, + input io_timer_int, + input io_soft_int, + output io_o_cpu_halt_status, + output io_o_cpu_halt_ack, + output io_o_cpu_run_ack, + output io_o_debug_mode_status, + input [27:0] io_core_id, + input io_mpc_debug_halt_req, + input io_mpc_debug_run_req, + input io_mpc_reset_run_req, + output io_mpc_debug_halt_ack, + output io_mpc_debug_run_ack, + output io_debug_brkpt_status, + output [3:0] io_dec_tlu_meicurpl, + output [3:0] io_dec_tlu_meipt, + output [31:0] io_dec_csr_rddata_d, + output io_dec_csr_legal_d, + output io_dec_tlu_br0_r_pkt_valid, + output [1:0] io_dec_tlu_br0_r_pkt_bits_hist, + output io_dec_tlu_br0_r_pkt_bits_br_error, + output io_dec_tlu_br0_r_pkt_bits_br_start_error, + output io_dec_tlu_br0_r_pkt_bits_way, + output io_dec_tlu_br0_r_pkt_bits_middle, + output io_dec_tlu_i0_kill_writeb_wb, + output io_dec_tlu_flush_lower_wb, + output io_dec_tlu_i0_commit_cmt, + output io_dec_tlu_i0_kill_writeb_r, + output io_dec_tlu_flush_lower_r, + output [30:0] io_dec_tlu_flush_path_r, + output io_dec_tlu_fence_i_r, + output io_dec_tlu_wr_pause_r, + output io_dec_tlu_flush_pause_r, + output io_dec_tlu_presync_d, + output io_dec_tlu_postsync_d, + output [31:0] io_dec_tlu_mrac_ff, + output io_dec_tlu_force_halt, + output io_dec_tlu_perfcnt0, + output io_dec_tlu_perfcnt1, + output io_dec_tlu_perfcnt2, + output io_dec_tlu_perfcnt3, + output io_dec_tlu_i0_exc_valid_wb1, + output io_dec_tlu_i0_valid_wb1, + output io_dec_tlu_int_valid_wb1, + output [4:0] io_dec_tlu_exc_cause_wb1, + output [31:0] io_dec_tlu_mtval_wb1, + output io_dec_tlu_external_ldfwd_disable, + output io_dec_tlu_sideeffect_posted_disable, + output io_dec_tlu_core_ecc_disable, + output io_dec_tlu_bpred_disable, + output io_dec_tlu_wb_coalescing_disable, + output io_dec_tlu_pipelining_disable, + output [2:0] io_dec_tlu_dma_qos_prty, + output io_dec_tlu_misc_clk_override, + output io_dec_tlu_dec_clk_override, + output io_dec_tlu_ifu_clk_override, + output io_dec_tlu_lsu_clk_override, + output io_dec_tlu_bus_clk_override, + output io_dec_tlu_pic_clk_override, + output io_dec_tlu_dccm_clk_override, + output io_dec_tlu_icm_clk_override +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; + reg [31:0] _RAND_13; + reg [31:0] _RAND_14; + reg [31:0] _RAND_15; + reg [31:0] _RAND_16; + reg [31:0] _RAND_17; + reg [31:0] _RAND_18; + reg [31:0] _RAND_19; + reg [31:0] _RAND_20; + reg [31:0] _RAND_21; + reg [31:0] _RAND_22; + reg [31:0] _RAND_23; + reg [31:0] _RAND_24; + reg [31:0] _RAND_25; + reg [31:0] _RAND_26; + reg [31:0] _RAND_27; + reg [31:0] _RAND_28; + reg [31:0] _RAND_29; + reg [31:0] _RAND_30; + reg [31:0] _RAND_31; + reg [31:0] _RAND_32; + reg [31:0] _RAND_33; + reg [31:0] _RAND_34; + reg [31:0] _RAND_35; + reg [31:0] _RAND_36; + reg [31:0] _RAND_37; + reg [31:0] _RAND_38; + reg [31:0] _RAND_39; + reg [31:0] _RAND_40; + reg [31:0] _RAND_41; + reg [31:0] _RAND_42; + reg [31:0] _RAND_43; + reg [31:0] _RAND_44; + reg [31:0] _RAND_45; + reg [31:0] _RAND_46; + reg [31:0] _RAND_47; + reg [31:0] _RAND_48; + reg [31:0] _RAND_49; + reg [31:0] _RAND_50; + reg [31:0] _RAND_51; + reg [31:0] _RAND_52; + reg [31:0] _RAND_53; + reg [31:0] _RAND_54; + reg [31:0] _RAND_55; + reg [31:0] _RAND_56; + reg [31:0] _RAND_57; + reg [31:0] _RAND_58; + reg [31:0] _RAND_59; + reg [31:0] _RAND_60; + reg [31:0] _RAND_61; + reg [31:0] _RAND_62; + reg [31:0] _RAND_63; + reg [31:0] _RAND_64; + reg [31:0] _RAND_65; + reg [31:0] _RAND_66; + reg [31:0] _RAND_67; + reg [31:0] _RAND_68; + reg [31:0] _RAND_69; + reg [31:0] _RAND_70; + reg [31:0] _RAND_71; + reg [31:0] _RAND_72; + reg [31:0] _RAND_73; + reg [31:0] _RAND_74; +`endif // RANDOMIZE_REG_INIT + wire int_timers_clock; // @[el2_dec_tlu_ctl.scala 355:24] + wire int_timers_reset; // @[el2_dec_tlu_ctl.scala 355:24] + wire int_timers_io_free_clk; // @[el2_dec_tlu_ctl.scala 355:24] + wire int_timers_io_scan_mode; // @[el2_dec_tlu_ctl.scala 355:24] + wire int_timers_io_dec_csr_wen_r_mod; // @[el2_dec_tlu_ctl.scala 355:24] + wire [11:0] int_timers_io_dec_csr_wraddr_r; // @[el2_dec_tlu_ctl.scala 355:24] + wire [31:0] int_timers_io_dec_csr_wrdata_r; // @[el2_dec_tlu_ctl.scala 355:24] + wire int_timers_io_csr_mitctl0; // @[el2_dec_tlu_ctl.scala 355:24] + wire int_timers_io_csr_mitctl1; // @[el2_dec_tlu_ctl.scala 355:24] + wire int_timers_io_csr_mitb0; // @[el2_dec_tlu_ctl.scala 355:24] + wire int_timers_io_csr_mitb1; // @[el2_dec_tlu_ctl.scala 355:24] + wire int_timers_io_csr_mitcnt0; // @[el2_dec_tlu_ctl.scala 355:24] + wire int_timers_io_csr_mitcnt1; // @[el2_dec_tlu_ctl.scala 355:24] + wire int_timers_io_dec_pause_state; // @[el2_dec_tlu_ctl.scala 355:24] + wire int_timers_io_dec_tlu_pmu_fw_halted; // @[el2_dec_tlu_ctl.scala 355:24] + wire int_timers_io_internal_dbg_halt_timers; // @[el2_dec_tlu_ctl.scala 355:24] + wire [31:0] int_timers_io_dec_timer_rddata_d; // @[el2_dec_tlu_ctl.scala 355:24] + wire int_timers_io_dec_timer_read_d; // @[el2_dec_tlu_ctl.scala 355:24] + wire int_timers_io_dec_timer_t0_pulse; // @[el2_dec_tlu_ctl.scala 355:24] + wire int_timers_io_dec_timer_t1_pulse; // @[el2_dec_tlu_ctl.scala 355:24] + wire rvclkhdr_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_1_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_1_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_2_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_2_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_3_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_3_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 483:22] + wire csr_clock; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_reset; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_free_clk; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_active_clk; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_scan_mode; // @[el2_dec_tlu_ctl.scala 897:17] + wire [31:0] csr_io_dec_csr_wrdata_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire [11:0] csr_io_dec_csr_wraddr_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire [11:0] csr_io_dec_csr_rdaddr_d; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_csr_wen_unq_d; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_i0_decode_d; // @[el2_dec_tlu_ctl.scala 897:17] + wire [70:0] csr_io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[el2_dec_tlu_ctl.scala 897:17] + wire [16:0] csr_io_dec_tlu_ic_diag_pkt_icache_dicawics; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_ifu_ic_debug_rd_data_valid; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_0_select; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_0_match_pkt; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_0_store; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_0_load; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_0_execute; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_0_m; // @[el2_dec_tlu_ctl.scala 897:17] + wire [31:0] csr_io_trigger_pkt_any_0_tdata2; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_1_select; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_1_match_pkt; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_1_store; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_1_load; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_1_execute; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_1_m; // @[el2_dec_tlu_ctl.scala 897:17] + wire [31:0] csr_io_trigger_pkt_any_1_tdata2; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_2_select; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_2_match_pkt; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_2_store; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_2_load; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_2_execute; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_2_m; // @[el2_dec_tlu_ctl.scala 897:17] + wire [31:0] csr_io_trigger_pkt_any_2_tdata2; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_3_select; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_3_match_pkt; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_3_store; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_3_load; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_3_execute; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_3_m; // @[el2_dec_tlu_ctl.scala 897:17] + wire [31:0] csr_io_trigger_pkt_any_3_tdata2; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_ifu_pmu_bus_trxn; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dma_iccm_stall_any; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dma_dccm_stall_any; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_lsu_store_stall_any; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_pmu_presync_stall; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_pmu_postsync_stall; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_pmu_decode_stall; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_ifu_pmu_fetch_stall; // @[el2_dec_tlu_ctl.scala 897:17] + wire [1:0] csr_io_dec_tlu_packet_r_icaf_type; // @[el2_dec_tlu_ctl.scala 897:17] + wire [3:0] csr_io_dec_tlu_packet_r_pmu_i0_itype; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_packet_r_pmu_divide; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_exu_pmu_i0_br_ataken; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_exu_pmu_i0_br_misp; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_pmu_instr_decoded; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_ifu_pmu_instr_aligned; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_exu_pmu_i0_pc4; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_ifu_pmu_ic_miss; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_ifu_pmu_ic_hit; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_int_valid_wb1; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_i0_exc_valid_wb1; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_i0_valid_wb1; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_csr_wen_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire [31:0] csr_io_dec_tlu_mtval_wb1; // @[el2_dec_tlu_ctl.scala 897:17] + wire [4:0] csr_io_dec_tlu_exc_cause_wb1; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_perfcnt0; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_perfcnt1; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_perfcnt2; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_perfcnt3; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_dbg_halted; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dma_pmu_dccm_write; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dma_pmu_dccm_read; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dma_pmu_any_write; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dma_pmu_any_read; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_lsu_pmu_bus_busy; // @[el2_dec_tlu_ctl.scala 897:17] + wire [30:0] csr_io_dec_tlu_i0_pc_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_csr_any_unq_d; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_misc_clk_override; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_dec_clk_override; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_ifu_clk_override; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_lsu_clk_override; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_bus_clk_override; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_pic_clk_override; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_dccm_clk_override; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_icm_clk_override; // @[el2_dec_tlu_ctl.scala 897:17] + wire [31:0] csr_io_dec_csr_rddata_d; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_pipelining_disable; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_wr_pause_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_ifu_pmu_bus_busy; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_lsu_pmu_bus_error; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_ifu_pmu_bus_error; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_lsu_pmu_bus_misaligned; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_lsu_pmu_bus_trxn; // @[el2_dec_tlu_ctl.scala 897:17] + wire [70:0] csr_io_ifu_ic_debug_rd_data; // @[el2_dec_tlu_ctl.scala 897:17] + wire [3:0] csr_io_dec_tlu_meipt; // @[el2_dec_tlu_ctl.scala 897:17] + wire [3:0] csr_io_pic_pl; // @[el2_dec_tlu_ctl.scala 897:17] + wire [3:0] csr_io_dec_tlu_meicurpl; // @[el2_dec_tlu_ctl.scala 897:17] + wire [29:0] csr_io_dec_tlu_meihap; // @[el2_dec_tlu_ctl.scala 897:17] + wire [7:0] csr_io_pic_claimid; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_iccm_dma_sb_error; // @[el2_dec_tlu_ctl.scala 897:17] + wire [31:0] csr_io_lsu_imprecise_error_addr_any; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_lsu_imprecise_error_load_any; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_lsu_imprecise_error_store_any; // @[el2_dec_tlu_ctl.scala 897:17] + wire [31:0] csr_io_dec_tlu_mrac_ff; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_wb_coalescing_disable; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_bpred_disable; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_sideeffect_posted_disable; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_core_ecc_disable; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_external_ldfwd_disable; // @[el2_dec_tlu_ctl.scala 897:17] + wire [2:0] csr_io_dec_tlu_dma_qos_prty; // @[el2_dec_tlu_ctl.scala 897:17] + wire [31:0] csr_io_dec_illegal_inst; // @[el2_dec_tlu_ctl.scala 897:17] + wire [3:0] csr_io_lsu_error_pkt_r_bits_mscause; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_mexintpend; // @[el2_dec_tlu_ctl.scala 897:17] + wire [30:0] csr_io_exu_npc_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_mpc_reset_run_req; // @[el2_dec_tlu_ctl.scala 897:17] + wire [30:0] csr_io_rst_vec; // @[el2_dec_tlu_ctl.scala 897:17] + wire [27:0] csr_io_core_id; // @[el2_dec_tlu_ctl.scala 897:17] + wire [31:0] csr_io_dec_timer_rddata_d; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_timer_read_d; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_csr_wen_r_mod; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_rfpc_i0_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_i0_trigger_hit_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_fw_halt_req; // @[el2_dec_tlu_ctl.scala 897:17] + wire [1:0] csr_io_mstatus; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_exc_or_int_valid_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_mret_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_mstatus_mie_ns; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dcsr_single_step_running_f; // @[el2_dec_tlu_ctl.scala 897:17] + wire [15:0] csr_io_dcsr; // @[el2_dec_tlu_ctl.scala 897:17] + wire [30:0] csr_io_mtvec; // @[el2_dec_tlu_ctl.scala 897:17] + wire [5:0] csr_io_mip; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_timer_t0_pulse; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_timer_t1_pulse; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_timer_int_sync; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_soft_int_sync; // @[el2_dec_tlu_ctl.scala 897:17] + wire [5:0] csr_io_mie_ns; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_wr_clk; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_ebreak_to_debug_mode_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_pmu_fw_halted; // @[el2_dec_tlu_ctl.scala 897:17] + wire [1:0] csr_io_lsu_fir_error; // @[el2_dec_tlu_ctl.scala 897:17] + wire [30:0] csr_io_npc_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_tlu_flush_lower_r_d1; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_flush_noredir_r_d1; // @[el2_dec_tlu_ctl.scala 897:17] + wire [30:0] csr_io_tlu_flush_path_r_d1; // @[el2_dec_tlu_ctl.scala 897:17] + wire [30:0] csr_io_npc_r_d1; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_reset_delayed; // @[el2_dec_tlu_ctl.scala 897:17] + wire [30:0] csr_io_mepc; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_interrupt_valid_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_i0_exception_valid_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_lsu_exc_valid_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_mepc_trigger_hit_sel_pc_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_e4e5_int_clk; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_lsu_i0_exc_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_inst_acc_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_inst_acc_second_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_take_nmi; // @[el2_dec_tlu_ctl.scala 897:17] + wire [31:0] csr_io_lsu_error_pkt_addr_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire [4:0] csr_io_exc_cause_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_i0_valid_wb; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_exc_or_int_valid_r_d1; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_interrupt_valid_r_d1; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_clk_override; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_i0_exception_valid_r_d1; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_lsu_i0_exc_r_d1; // @[el2_dec_tlu_ctl.scala 897:17] + wire [4:0] csr_io_exc_cause_wb; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_nmi_lsu_store_type; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_nmi_lsu_load_type; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_tlu_i0_commit_cmt; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_ebreak_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_ecall_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_illegal_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_mdseac_locked_ns; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_mdseac_locked_f; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_nmi_int_detected_f; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_internal_dbg_halt_mode_f2; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_ext_int_freeze_d1; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_ic_perr_r_d1; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_iccm_sbecc_r_d1; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_lsu_single_ecc_error_r_d1; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_ifu_miss_state_idle_f; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_lsu_idle_any_f; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dbg_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dbg_tlu_halted; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_debug_halt_req_f; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_force_halt; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_take_ext_int_start; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_hit_dmode_r_d1; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_hit_r_d1; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dcsr_single_step_done_f; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_ebreak_to_debug_mode_r_d1; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_debug_halt_req; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_allow_dbg_halt_csr_write; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_internal_dbg_halt_mode_f; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_enter_debug_halt_req; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_internal_dbg_halt_mode; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_request_debug_mode_done; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_request_debug_mode_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire [30:0] csr_io_dpc; // @[el2_dec_tlu_ctl.scala 897:17] + wire [3:0] csr_io_update_hit_bit_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_take_timer_int; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_take_int_timer0_int; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_take_int_timer1_int; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_take_ext_int; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_tlu_flush_lower_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_br0_error_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_br0_start_error_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_lsu_pmu_load_external_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_lsu_pmu_store_external_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_misa; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mvendorid; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_marchid; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mimpid; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mhartid; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mstatus; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mtvec; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mip; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mie; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mcyclel; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mcycleh; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_minstretl; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_minstreth; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mscratch; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mepc; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mcause; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mscause; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mtval; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mrac; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mdseac; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_meihap; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_meivt; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_meipt; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_meicurpl; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_meicidpl; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_dcsr; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mcgc; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mfdc; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_dpc; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mtsel; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mtdata1; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mtdata2; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mhpmc3; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mhpmc4; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mhpmc5; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mhpmc6; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mhpmc3h; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mhpmc4h; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mhpmc5h; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mhpmc6h; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mhpme3; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mhpme4; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mhpme5; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mhpme6; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mcountinhibit; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mpmc; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_micect; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_miccmect; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mdccmect; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mfdht; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mfdhs; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_dicawics; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_dicad0h; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_dicad0; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_dicad1; // @[el2_dec_tlu_ctl.scala 897:17] + wire [9:0] csr_io_mtdata1_t_0; // @[el2_dec_tlu_ctl.scala 897:17] + wire [9:0] csr_io_mtdata1_t_1; // @[el2_dec_tlu_ctl.scala 897:17] + wire [9:0] csr_io_mtdata1_t_2; // @[el2_dec_tlu_ctl.scala 897:17] + wire [9:0] csr_io_mtdata1_t_3; // @[el2_dec_tlu_ctl.scala 897:17] + wire [11:0] csr_read_io_dec_csr_rdaddr_d; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_misa; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mvendorid; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_marchid; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mimpid; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mhartid; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mstatus; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mtvec; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mip; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mie; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mcyclel; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mcycleh; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_minstretl; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_minstreth; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mscratch; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mepc; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mcause; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mscause; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mtval; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mrac; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_dmst; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mdseac; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_meihap; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_meivt; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_meipt; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_meicurpl; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_meicidpl; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_dcsr; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mcgc; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mfdc; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_dpc; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mtsel; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mtdata1; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mtdata2; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mhpmc3; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mhpmc4; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mhpmc5; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mhpmc6; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mhpmc3h; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mhpmc4h; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mhpmc5h; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mhpmc6h; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mhpme3; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mhpme4; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mhpme5; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mhpme6; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mcountinhibit; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mitctl0; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mitctl1; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mitb0; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mitb1; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mitcnt0; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mitcnt1; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mpmc; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_meicpct; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_micect; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_miccmect; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mdccmect; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mfdht; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mfdhs; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_dicawics; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_dicad0h; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_dicad0; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_dicad1; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_dicago; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_presync; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_postsync; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_legal; // @[el2_dec_tlu_ctl.scala 1090:22] + reg dbg_halt_state_f; // @[el2_dec_tlu_ctl.scala 447:81] + wire _T = ~dbg_halt_state_f; // @[el2_dec_tlu_ctl.scala 354:33] + reg mpc_halt_state_f; // @[el2_dec_tlu_ctl.scala 442:81] + wire [2:0] _T_3 = {io_i_cpu_run_req,io_mpc_debug_halt_req,io_mpc_debug_run_req}; // @[Cat.scala 29:58] + wire [3:0] _T_6 = {io_nmi_int,io_timer_int,io_soft_int,io_i_cpu_halt_req}; // @[Cat.scala 29:58] + reg [6:0] _T_8; // @[el2_lib.scala 177:81] + reg [6:0] syncro_ff; // @[el2_lib.scala 177:58] + wire nmi_int_sync = syncro_ff[6]; // @[el2_dec_tlu_ctl.scala 382:67] + wire i_cpu_halt_req_sync = syncro_ff[3]; // @[el2_dec_tlu_ctl.scala 385:59] + wire i_cpu_run_req_sync = syncro_ff[2]; // @[el2_dec_tlu_ctl.scala 386:59] + wire mpc_debug_halt_req_sync_raw = syncro_ff[1]; // @[el2_dec_tlu_ctl.scala 387:51] + wire mpc_debug_run_req_sync = syncro_ff[0]; // @[el2_dec_tlu_ctl.scala 388:51] + wire dec_csr_wen_r_mod = csr_io_dec_csr_wen_r_mod; // @[el2_dec_tlu_ctl.scala 1083:31] + reg lsu_exc_valid_r_d1; // @[el2_dec_tlu_ctl.scala 693:74] + wire _T_11 = io_lsu_error_pkt_r_valid | lsu_exc_valid_r_d1; // @[el2_dec_tlu_ctl.scala 392:61] + reg e5_valid; // @[el2_dec_tlu_ctl.scala 404:89] + wire e4e5_valid = io_dec_tlu_i0_valid_r | e5_valid; // @[el2_dec_tlu_ctl.scala 395:29] + reg debug_mode_status; // @[el2_dec_tlu_ctl.scala 405:73] + reg i_cpu_run_req_d1_raw; // @[el2_dec_tlu_ctl.scala 653:72] + reg nmi_int_delayed; // @[el2_dec_tlu_ctl.scala 420:64] + wire _T_37 = ~nmi_int_delayed; // @[el2_dec_tlu_ctl.scala 429:39] + wire _T_38 = nmi_int_sync & _T_37; // @[el2_dec_tlu_ctl.scala 429:37] + reg mdseac_locked_f; // @[el2_dec_tlu_ctl.scala 686:89] + wire _T_35 = ~mdseac_locked_f; // @[el2_dec_tlu_ctl.scala 427:26] + wire _T_36 = io_lsu_imprecise_error_load_any | io_lsu_imprecise_error_store_any; // @[el2_dec_tlu_ctl.scala 427:78] + wire nmi_lsu_detected = _T_35 & _T_36; // @[el2_dec_tlu_ctl.scala 427:43] + wire _T_39 = _T_38 | nmi_lsu_detected; // @[el2_dec_tlu_ctl.scala 429:57] + reg nmi_int_detected_f; // @[el2_dec_tlu_ctl.scala 421:72] + reg take_nmi_r_d1; // @[el2_dec_tlu_ctl.scala 894:90] + wire _T_40 = ~take_nmi_r_d1; // @[el2_dec_tlu_ctl.scala 429:100] + wire _T_41 = nmi_int_detected_f & _T_40; // @[el2_dec_tlu_ctl.scala 429:98] + wire _T_42 = _T_39 | _T_41; // @[el2_dec_tlu_ctl.scala 429:76] + reg take_ext_int_start_d3; // @[el2_dec_tlu_ctl.scala 826:58] + wire _T_43 = |io_lsu_fir_error; // @[el2_dec_tlu_ctl.scala 429:159] + wire _T_44 = take_ext_int_start_d3 & _T_43; // @[el2_dec_tlu_ctl.scala 429:140] + wire nmi_int_detected = _T_42 | _T_44; // @[el2_dec_tlu_ctl.scala 429:116] + wire _T_631 = ~io_dec_csr_stall_int_ff; // @[el2_dec_tlu_ctl.scala 803:22] + wire mstatus_mie_ns = csr_io_mstatus_mie_ns; // @[el2_dec_tlu_ctl.scala 1082:31] + wire _T_632 = _T_631 & mstatus_mie_ns; // @[el2_dec_tlu_ctl.scala 803:47] + wire [5:0] mip = csr_io_mip; // @[el2_dec_tlu_ctl.scala 1088:31] + wire _T_634 = _T_632 & mip[1]; // @[el2_dec_tlu_ctl.scala 803:64] + wire [5:0] mie_ns = csr_io_mie_ns; // @[el2_dec_tlu_ctl.scala 1077:31] + wire timer_int_ready = _T_634 & mie_ns[1]; // @[el2_dec_tlu_ctl.scala 803:82] + wire _T_391 = nmi_int_detected | timer_int_ready; // @[el2_dec_tlu_ctl.scala 680:65] + wire _T_628 = _T_632 & mip[0]; // @[el2_dec_tlu_ctl.scala 802:64] + wire soft_int_ready = _T_628 & mie_ns[0]; // @[el2_dec_tlu_ctl.scala 802:82] + wire _T_392 = _T_391 | soft_int_ready; // @[el2_dec_tlu_ctl.scala 680:83] + reg int_timer0_int_hold_f; // @[el2_dec_tlu_ctl.scala 660:65] + wire _T_393 = _T_392 | int_timer0_int_hold_f; // @[el2_dec_tlu_ctl.scala 680:100] + reg int_timer1_int_hold_f; // @[el2_dec_tlu_ctl.scala 661:65] + wire _T_394 = _T_393 | int_timer1_int_hold_f; // @[el2_dec_tlu_ctl.scala 680:124] + wire _T_608 = _T_632 & mip[2]; // @[el2_dec_tlu_ctl.scala 799:65] + wire mhwakeup_ready = _T_608 & mie_ns[2]; // @[el2_dec_tlu_ctl.scala 799:83] + wire _T_395 = io_mhwakeup & mhwakeup_ready; // @[el2_dec_tlu_ctl.scala 680:163] + wire _T_396 = _T_394 | _T_395; // @[el2_dec_tlu_ctl.scala 680:148] + wire _T_397 = _T_396 & io_o_cpu_halt_status; // @[el2_dec_tlu_ctl.scala 680:182] + reg i_cpu_halt_req_d1; // @[el2_dec_tlu_ctl.scala 652:80] + wire _T_398 = ~i_cpu_halt_req_d1; // @[el2_dec_tlu_ctl.scala 680:207] + wire _T_399 = _T_397 & _T_398; // @[el2_dec_tlu_ctl.scala 680:205] + wire i_cpu_run_req_d1 = i_cpu_run_req_d1_raw | _T_399; // @[el2_dec_tlu_ctl.scala 680:44] + wire _T_14 = debug_mode_status | i_cpu_run_req_d1; // @[el2_dec_tlu_ctl.scala 396:49] + wire _T_685 = ~_T_43; // @[el2_dec_tlu_ctl.scala 831:45] + wire take_ext_int = take_ext_int_start_d3 & _T_685; // @[el2_dec_tlu_ctl.scala 831:43] + wire _T_698 = ~soft_int_ready; // @[el2_dec_tlu_ctl.scala 848:39] + wire _T_699 = timer_int_ready & _T_698; // @[el2_dec_tlu_ctl.scala 848:37] + wire _T_617 = ~io_lsu_fastint_stall_any; // @[el2_dec_tlu_ctl.scala 800:103] + wire ext_int_ready = mhwakeup_ready & _T_617; // @[el2_dec_tlu_ctl.scala 800:101] + wire _T_700 = ~ext_int_ready; // @[el2_dec_tlu_ctl.scala 848:57] + wire _T_701 = _T_699 & _T_700; // @[el2_dec_tlu_ctl.scala 848:55] + wire _T_622 = _T_632 & mip[5]; // @[el2_dec_tlu_ctl.scala 801:64] + wire ce_int_ready = _T_622 & mie_ns[5]; // @[el2_dec_tlu_ctl.scala 801:82] + wire _T_702 = ~ce_int_ready; // @[el2_dec_tlu_ctl.scala 848:74] + wire _T_703 = _T_701 & _T_702; // @[el2_dec_tlu_ctl.scala 848:72] + wire _T_152 = ~debug_mode_status; // @[el2_dec_tlu_ctl.scala 503:31] + reg dbg_halt_req_held; // @[el2_dec_tlu_ctl.scala 546:81] + wire _T_106 = io_dbg_halt_req | dbg_halt_req_held; // @[el2_dec_tlu_ctl.scala 480:42] + reg ext_int_freeze_d1; // @[el2_dec_tlu_ctl.scala 827:58] + wire _T_107 = ~ext_int_freeze_d1; // @[el2_dec_tlu_ctl.scala 480:65] + wire dbg_halt_req_final = _T_106 & _T_107; // @[el2_dec_tlu_ctl.scala 480:63] + wire mpc_debug_halt_req_sync = mpc_debug_halt_req_sync_raw & _T_107; // @[el2_dec_tlu_ctl.scala 439:61] + wire _T_109 = dbg_halt_req_final | mpc_debug_halt_req_sync; // @[el2_dec_tlu_ctl.scala 483:44] + reg reset_detect; // @[el2_dec_tlu_ctl.scala 416:80] + reg reset_detected; // @[el2_dec_tlu_ctl.scala 417:80] + wire reset_delayed = reset_detect ^ reset_detected; // @[el2_dec_tlu_ctl.scala 418:64] + wire _T_110 = ~io_mpc_reset_run_req; // @[el2_dec_tlu_ctl.scala 483:89] + wire _T_111 = reset_delayed & _T_110; // @[el2_dec_tlu_ctl.scala 483:87] + wire _T_112 = _T_109 | _T_111; // @[el2_dec_tlu_ctl.scala 483:70] + wire _T_114 = _T_112 & _T_152; // @[el2_dec_tlu_ctl.scala 483:113] + wire debug_halt_req = _T_114 & _T_107; // @[el2_dec_tlu_ctl.scala 483:141] + wire _T_153 = _T_152 & debug_halt_req; // @[el2_dec_tlu_ctl.scala 503:57] + reg dcsr_single_step_done_f; // @[el2_dec_tlu_ctl.scala 538:81] + wire _T_154 = _T_153 | dcsr_single_step_done_f; // @[el2_dec_tlu_ctl.scala 503:75] + reg trigger_hit_dmode_r_d1; // @[el2_dec_tlu_ctl.scala 537:81] + wire _T_155 = _T_154 | trigger_hit_dmode_r_d1; // @[el2_dec_tlu_ctl.scala 503:101] + reg ebreak_to_debug_mode_r_d1; // @[el2_dec_tlu_ctl.scala 752:58] + wire enter_debug_halt_req = _T_155 | ebreak_to_debug_mode_r_d1; // @[el2_dec_tlu_ctl.scala 503:126] + reg debug_halt_req_f; // @[el2_dec_tlu_ctl.scala 535:81] + wire force_halt = csr_io_force_halt; // @[el2_dec_tlu_ctl.scala 1080:31] + reg lsu_idle_any_f; // @[el2_dec_tlu_ctl.scala 531:89] + wire _T_142 = io_lsu_idle_any & lsu_idle_any_f; // @[el2_dec_tlu_ctl.scala 497:47] + wire _T_143 = _T_142 & io_ifu_miss_state_idle; // @[el2_dec_tlu_ctl.scala 497:64] + reg ifu_miss_state_idle_f; // @[el2_dec_tlu_ctl.scala 532:73] + wire _T_144 = _T_143 & ifu_miss_state_idle_f; // @[el2_dec_tlu_ctl.scala 497:89] + wire _T_145 = ~debug_halt_req; // @[el2_dec_tlu_ctl.scala 497:115] + wire _T_146 = _T_144 & _T_145; // @[el2_dec_tlu_ctl.scala 497:113] + reg debug_halt_req_d1; // @[el2_dec_tlu_ctl.scala 539:81] + wire _T_147 = ~debug_halt_req_d1; // @[el2_dec_tlu_ctl.scala 497:133] + wire _T_148 = _T_146 & _T_147; // @[el2_dec_tlu_ctl.scala 497:131] + wire _T_149 = ~io_dec_div_active; // @[el2_dec_tlu_ctl.scala 497:154] + wire _T_150 = _T_148 & _T_149; // @[el2_dec_tlu_ctl.scala 497:152] + wire core_empty = force_halt | _T_150; // @[el2_dec_tlu_ctl.scala 497:28] + wire _T_163 = debug_halt_req_f & core_empty; // @[el2_dec_tlu_ctl.scala 513:42] + reg dec_tlu_flush_noredir_r_d1; // @[el2_dec_tlu_ctl.scala 529:73] + reg dec_tlu_flush_pause_r_d1; // @[el2_dec_tlu_ctl.scala 545:73] + wire _T_132 = ~dec_tlu_flush_pause_r_d1; // @[el2_dec_tlu_ctl.scala 493:50] + wire _T_133 = dec_tlu_flush_noredir_r_d1 & _T_132; // @[el2_dec_tlu_ctl.scala 493:48] + reg take_ext_int_start_d1; // @[el2_dec_tlu_ctl.scala 824:58] + wire _T_134 = ~take_ext_int_start_d1; // @[el2_dec_tlu_ctl.scala 493:78] + wire _T_135 = _T_133 & _T_134; // @[el2_dec_tlu_ctl.scala 493:76] + reg halt_taken_f; // @[el2_dec_tlu_ctl.scala 530:81] + reg dbg_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 533:81] + wire _T_136 = ~dbg_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 493:120] + wire _T_137 = halt_taken_f & _T_136; // @[el2_dec_tlu_ctl.scala 493:118] + reg pmu_fw_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 659:73] + wire _T_138 = ~pmu_fw_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 493:140] + wire _T_139 = _T_137 & _T_138; // @[el2_dec_tlu_ctl.scala 493:138] + reg interrupt_valid_r_d1; // @[el2_dec_tlu_ctl.scala 888:82] + wire _T_140 = ~interrupt_valid_r_d1; // @[el2_dec_tlu_ctl.scala 493:163] + wire _T_141 = _T_139 & _T_140; // @[el2_dec_tlu_ctl.scala 493:161] + wire halt_taken = _T_135 | _T_141; // @[el2_dec_tlu_ctl.scala 493:102] + wire _T_164 = _T_163 & halt_taken; // @[el2_dec_tlu_ctl.scala 513:55] + reg debug_resume_req_f; // @[el2_dec_tlu_ctl.scala 536:81] + wire _T_165 = ~debug_resume_req_f; // @[el2_dec_tlu_ctl.scala 513:91] + wire _T_166 = dbg_tlu_halted_f & _T_165; // @[el2_dec_tlu_ctl.scala 513:89] + wire dbg_tlu_halted = _T_164 | _T_166; // @[el2_dec_tlu_ctl.scala 513:69] + wire _T_167 = ~dbg_tlu_halted; // @[el2_dec_tlu_ctl.scala 514:67] + wire _T_168 = debug_halt_req_f & _T_167; // @[el2_dec_tlu_ctl.scala 514:65] + wire debug_halt_req_ns = enter_debug_halt_req | _T_168; // @[el2_dec_tlu_ctl.scala 514:45] + wire [15:0] dcsr = csr_io_dcsr; // @[el2_dec_tlu_ctl.scala 1086:31] + wire _T_157 = ~dcsr[2]; // @[el2_dec_tlu_ctl.scala 506:100] + wire _T_158 = debug_resume_req_f & _T_157; // @[el2_dec_tlu_ctl.scala 506:98] + wire _T_159 = ~_T_158; // @[el2_dec_tlu_ctl.scala 506:77] + wire _T_160 = debug_mode_status & _T_159; // @[el2_dec_tlu_ctl.scala 506:75] + wire internal_dbg_halt_mode = debug_halt_req_ns | _T_160; // @[el2_dec_tlu_ctl.scala 506:47] + wire _T_177 = debug_resume_req_f & dcsr[2]; // @[el2_dec_tlu_ctl.scala 519:54] + reg dcsr_single_step_running_f; // @[el2_dec_tlu_ctl.scala 544:73] + wire _T_178 = ~dcsr_single_step_done_f; // @[el2_dec_tlu_ctl.scala 519:105] + wire _T_179 = dcsr_single_step_running_f & _T_178; // @[el2_dec_tlu_ctl.scala 519:103] + wire dcsr_single_step_running = _T_177 | _T_179; // @[el2_dec_tlu_ctl.scala 519:73] + wire _T_665 = ~dcsr_single_step_running; // @[el2_dec_tlu_ctl.scala 820:54] + wire _T_666 = _T_665 | io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 820:80] + wire _T_667 = internal_dbg_halt_mode & _T_666; // @[el2_dec_tlu_ctl.scala 820:51] + wire _T_346 = ~io_dec_tlu_debug_mode; // @[el2_dec_tlu_ctl.scala 649:56] + wire _T_347 = i_cpu_halt_req_sync & _T_346; // @[el2_dec_tlu_ctl.scala 649:54] + wire i_cpu_halt_req_sync_qual = _T_347 & _T_107; // @[el2_dec_tlu_ctl.scala 649:79] + wire ext_halt_pulse = i_cpu_halt_req_sync_qual & _T_398; // @[el2_dec_tlu_ctl.scala 665:49] + wire fw_halt_req = csr_io_fw_halt_req; // @[el2_dec_tlu_ctl.scala 1084:31] + wire enter_pmu_fw_halt_req = ext_halt_pulse | fw_halt_req; // @[el2_dec_tlu_ctl.scala 666:47] + reg pmu_fw_halt_req_f; // @[el2_dec_tlu_ctl.scala 658:73] + wire _T_371 = pmu_fw_halt_req_f & core_empty; // @[el2_dec_tlu_ctl.scala 671:44] + wire _T_372 = _T_371 & halt_taken; // @[el2_dec_tlu_ctl.scala 671:57] + wire _T_373 = ~enter_debug_halt_req; // @[el2_dec_tlu_ctl.scala 671:72] + wire _T_374 = _T_372 & _T_373; // @[el2_dec_tlu_ctl.scala 671:70] + wire _T_375 = ~i_cpu_run_req_d1; // @[el2_dec_tlu_ctl.scala 671:120] + wire _T_376 = pmu_fw_tlu_halted_f & _T_375; // @[el2_dec_tlu_ctl.scala 671:118] + wire _T_377 = _T_374 | _T_376; // @[el2_dec_tlu_ctl.scala 671:95] + wire _T_378 = ~debug_halt_req_f; // @[el2_dec_tlu_ctl.scala 671:142] + wire pmu_fw_tlu_halted = _T_377 & _T_378; // @[el2_dec_tlu_ctl.scala 671:140] + wire _T_361 = ~pmu_fw_tlu_halted; // @[el2_dec_tlu_ctl.scala 667:71] + wire _T_362 = pmu_fw_halt_req_f & _T_361; // @[el2_dec_tlu_ctl.scala 667:69] + wire _T_363 = enter_pmu_fw_halt_req | _T_362; // @[el2_dec_tlu_ctl.scala 667:48] + wire pmu_fw_halt_req_ns = _T_363 & _T_378; // @[el2_dec_tlu_ctl.scala 667:92] + reg internal_pmu_fw_halt_mode_f; // @[el2_dec_tlu_ctl.scala 657:66] + wire _T_367 = internal_pmu_fw_halt_mode_f & _T_375; // @[el2_dec_tlu_ctl.scala 668:82] + wire _T_369 = _T_367 & _T_378; // @[el2_dec_tlu_ctl.scala 668:102] + wire internal_pmu_fw_halt_mode = pmu_fw_halt_req_ns | _T_369; // @[el2_dec_tlu_ctl.scala 668:51] + wire _T_668 = _T_667 | internal_pmu_fw_halt_mode; // @[el2_dec_tlu_ctl.scala 820:106] + wire _T_669 = _T_668 | i_cpu_halt_req_d1; // @[el2_dec_tlu_ctl.scala 820:134] + wire _T_738 = ~internal_pmu_fw_halt_mode; // @[el2_dec_tlu_ctl.scala 852:34] + wire _T_739 = nmi_int_detected & _T_738; // @[el2_dec_tlu_ctl.scala 852:32] + wire _T_740 = ~internal_dbg_halt_mode; // @[el2_dec_tlu_ctl.scala 852:64] + wire _T_742 = dcsr_single_step_running_f & dcsr[11]; // @[el2_dec_tlu_ctl.scala 852:118] + wire _T_743 = ~io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 852:140] + wire _T_744 = _T_742 & _T_743; // @[el2_dec_tlu_ctl.scala 852:138] + wire _T_746 = _T_744 & _T_178; // @[el2_dec_tlu_ctl.scala 852:163] + wire _T_747 = _T_740 | _T_746; // @[el2_dec_tlu_ctl.scala 852:88] + wire _T_748 = _T_739 & _T_747; // @[el2_dec_tlu_ctl.scala 852:61] + wire _T_463 = io_dec_tlu_packet_r_pmu_i0_itype == 4'h8; // @[el2_dec_tlu_ctl.scala 738:51] + wire _T_464 = _T_463 & io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 738:64] + wire _T_297 = io_dec_tlu_flush_lower_wb | io_dec_tlu_dbg_halted; // @[el2_dec_tlu_ctl.scala 600:57] + wire [3:0] _T_299 = _T_297 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_300 = ~_T_299; // @[el2_dec_tlu_ctl.scala 600:22] + wire [3:0] _T_292 = io_dec_tlu_i0_valid_r ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_294 = _T_292 & io_dec_tlu_packet_r_i0trigger; // @[el2_dec_tlu_ctl.scala 598:52] + wire [9:0] mtdata1_t_3 = csr_io_mtdata1_t_3; // @[el2_dec_tlu_ctl.scala 236:59 el2_dec_tlu_ctl.scala 1089:33] + wire [9:0] mtdata1_t_2 = csr_io_mtdata1_t_2; // @[el2_dec_tlu_ctl.scala 236:59 el2_dec_tlu_ctl.scala 1089:33] + wire [9:0] mtdata1_t_1 = csr_io_mtdata1_t_1; // @[el2_dec_tlu_ctl.scala 236:59 el2_dec_tlu_ctl.scala 1089:33] + wire [9:0] mtdata1_t_0 = csr_io_mtdata1_t_0; // @[el2_dec_tlu_ctl.scala 236:59 el2_dec_tlu_ctl.scala 1089:33] + wire [3:0] trigger_execute = {mtdata1_t_3[2],mtdata1_t_2[2],mtdata1_t_1[2],mtdata1_t_0[2]}; // @[Cat.scala 29:58] + wire [3:0] trigger_data = {mtdata1_t_3[7],mtdata1_t_2[7],mtdata1_t_1[7],mtdata1_t_0[7]}; // @[Cat.scala 29:58] + wire [3:0] _T_279 = trigger_execute & trigger_data; // @[el2_dec_tlu_ctl.scala 590:56] + wire inst_acc_r_raw = io_dec_tlu_packet_r_icaf & io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 746:48] + wire [3:0] _T_281 = inst_acc_r_raw ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_282 = _T_279 & _T_281; // @[el2_dec_tlu_ctl.scala 590:71] + wire _T_283 = io_exu_i0_br_error_r | io_exu_i0_br_start_error_r; // @[el2_dec_tlu_ctl.scala 590:128] + wire [3:0] _T_285 = _T_283 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_286 = _T_282 | _T_285; // @[el2_dec_tlu_ctl.scala 590:97] + wire [3:0] i0_iside_trigger_has_pri_r = ~_T_286; // @[el2_dec_tlu_ctl.scala 590:37] + wire [3:0] _T_295 = _T_294 & i0_iside_trigger_has_pri_r; // @[el2_dec_tlu_ctl.scala 598:89] + wire [3:0] trigger_store = {mtdata1_t_3[1],mtdata1_t_2[1],mtdata1_t_1[1],mtdata1_t_0[1]}; // @[Cat.scala 29:58] + wire [3:0] _T_287 = trigger_store & trigger_data; // @[el2_dec_tlu_ctl.scala 593:50] + wire [3:0] _T_289 = io_lsu_error_pkt_r_valid ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_290 = _T_287 & _T_289; // @[el2_dec_tlu_ctl.scala 593:65] + wire [3:0] i0_lsu_trigger_has_pri_r = ~_T_290; // @[el2_dec_tlu_ctl.scala 593:34] + wire [3:0] _T_296 = _T_295 & i0_lsu_trigger_has_pri_r; // @[el2_dec_tlu_ctl.scala 598:118] + wire [1:0] mstatus = csr_io_mstatus; // @[el2_dec_tlu_ctl.scala 1085:31] + wire _T_259 = mtdata1_t_3[6] | mstatus[0]; // @[el2_dec_tlu_ctl.scala 587:62] + wire _T_261 = _T_259 & mtdata1_t_3[3]; // @[el2_dec_tlu_ctl.scala 587:86] + wire _T_264 = mtdata1_t_2[6] | mstatus[0]; // @[el2_dec_tlu_ctl.scala 587:150] + wire _T_266 = _T_264 & mtdata1_t_2[3]; // @[el2_dec_tlu_ctl.scala 587:174] + wire _T_269 = mtdata1_t_1[6] | mstatus[0]; // @[el2_dec_tlu_ctl.scala 587:239] + wire _T_271 = _T_269 & mtdata1_t_1[3]; // @[el2_dec_tlu_ctl.scala 587:263] + wire _T_274 = mtdata1_t_0[6] | mstatus[0]; // @[el2_dec_tlu_ctl.scala 587:328] + wire _T_276 = _T_274 & mtdata1_t_0[3]; // @[el2_dec_tlu_ctl.scala 587:352] + wire [3:0] trigger_enabled = {_T_261,_T_266,_T_271,_T_276}; // @[Cat.scala 29:58] + wire [3:0] i0trigger_qual_r = _T_296 & trigger_enabled; // @[el2_dec_tlu_ctl.scala 598:145] + wire [3:0] i0_trigger_r = _T_300 & i0trigger_qual_r; // @[el2_dec_tlu_ctl.scala 600:83] + wire _T_303 = ~mtdata1_t_2[5]; // @[el2_dec_tlu_ctl.scala 603:59] + wire _T_305 = _T_303 | i0_trigger_r[2]; // @[el2_dec_tlu_ctl.scala 603:88] + wire _T_306 = i0_trigger_r[3] & _T_305; // @[el2_dec_tlu_ctl.scala 603:56] + wire _T_311 = _T_303 | i0_trigger_r[3]; // @[el2_dec_tlu_ctl.scala 603:156] + wire _T_312 = i0_trigger_r[2] & _T_311; // @[el2_dec_tlu_ctl.scala 603:124] + wire _T_315 = ~mtdata1_t_0[5]; // @[el2_dec_tlu_ctl.scala 603:195] + wire _T_317 = _T_315 | i0_trigger_r[0]; // @[el2_dec_tlu_ctl.scala 603:224] + wire _T_318 = i0_trigger_r[1] & _T_317; // @[el2_dec_tlu_ctl.scala 603:192] + wire _T_323 = _T_315 | i0_trigger_r[1]; // @[el2_dec_tlu_ctl.scala 603:292] + wire _T_324 = i0_trigger_r[0] & _T_323; // @[el2_dec_tlu_ctl.scala 603:260] + wire [3:0] i0_trigger_chain_masked_r = {_T_306,_T_312,_T_318,_T_324}; // @[Cat.scala 29:58] + wire i0_trigger_hit_raw_r = |i0_trigger_chain_masked_r; // @[el2_dec_tlu_ctl.scala 606:56] + wire _T_465 = ~i0_trigger_hit_raw_r; // @[el2_dec_tlu_ctl.scala 738:90] + wire _T_466 = _T_464 & _T_465; // @[el2_dec_tlu_ctl.scala 738:88] + wire _T_468 = ~dcsr[15]; // @[el2_dec_tlu_ctl.scala 738:110] + wire _T_469 = _T_466 & _T_468; // @[el2_dec_tlu_ctl.scala 738:108] + reg tlu_flush_lower_r_d1; // @[el2_dec_tlu_ctl.scala 408:72] + wire _T_429 = ~tlu_flush_lower_r_d1; // @[el2_dec_tlu_ctl.scala 713:43] + wire _T_430 = io_dec_tlu_i0_valid_r & _T_429; // @[el2_dec_tlu_ctl.scala 713:41] + wire _T_432 = _T_430 & _T_283; // @[el2_dec_tlu_ctl.scala 713:65] + reg ic_perr_r_d1; // @[el2_dec_tlu_ctl.scala 402:81] + reg iccm_sbecc_r_d1; // @[el2_dec_tlu_ctl.scala 403:89] + wire _T_433 = ic_perr_r_d1 | iccm_sbecc_r_d1; // @[el2_dec_tlu_ctl.scala 713:137] + wire _T_435 = _T_433 & _T_107; // @[el2_dec_tlu_ctl.scala 713:156] + wire _T_436 = _T_432 | _T_435; // @[el2_dec_tlu_ctl.scala 713:120] + wire _T_438 = _T_436 & _T_465; // @[el2_dec_tlu_ctl.scala 713:179] + wire _T_410 = io_dec_tlu_i0_valid_r & _T_465; // @[el2_dec_tlu_ctl.scala 701:46] + wire _T_411 = ~io_lsu_error_pkt_r_bits_inst_type; // @[el2_dec_tlu_ctl.scala 701:69] + wire _T_412 = _T_411 & io_lsu_error_pkt_r_bits_single_ecc_error; // @[el2_dec_tlu_ctl.scala 701:104] + wire lsu_i0_rfnpc_r = _T_410 & _T_412; // @[el2_dec_tlu_ctl.scala 701:66] + wire _T_439 = ~lsu_i0_rfnpc_r; // @[el2_dec_tlu_ctl.scala 713:203] + wire rfpc_i0_r = _T_438 & _T_439; // @[el2_dec_tlu_ctl.scala 713:200] + wire _T_470 = ~rfpc_i0_r; // @[el2_dec_tlu_ctl.scala 738:132] + wire ebreak_r = _T_469 & _T_470; // @[el2_dec_tlu_ctl.scala 738:130] + wire _T_472 = io_dec_tlu_packet_r_pmu_i0_itype == 4'h9; // @[el2_dec_tlu_ctl.scala 739:51] + wire _T_473 = _T_472 & io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 739:64] + wire _T_475 = _T_473 & _T_465; // @[el2_dec_tlu_ctl.scala 739:88] + wire ecall_r = _T_475 & _T_470; // @[el2_dec_tlu_ctl.scala 739:108] + wire _T_523 = ebreak_r | ecall_r; // @[el2_dec_tlu_ctl.scala 766:40] + wire _T_478 = ~io_dec_tlu_packet_r_legal; // @[el2_dec_tlu_ctl.scala 740:17] + wire _T_479 = _T_478 & io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 740:46] + wire _T_481 = _T_479 & _T_465; // @[el2_dec_tlu_ctl.scala 740:70] + wire illegal_r = _T_481 & _T_470; // @[el2_dec_tlu_ctl.scala 740:90] + wire _T_524 = _T_523 | illegal_r; // @[el2_dec_tlu_ctl.scala 766:50] + wire _T_511 = inst_acc_r_raw & _T_470; // @[el2_dec_tlu_ctl.scala 747:32] + wire inst_acc_r = _T_511 & _T_465; // @[el2_dec_tlu_ctl.scala 747:45] + wire _T_525 = _T_524 | inst_acc_r; // @[el2_dec_tlu_ctl.scala 766:62] + wire _T_527 = _T_525 & _T_470; // @[el2_dec_tlu_ctl.scala 766:76] + wire _T_528 = ~io_dec_tlu_dbg_halted; // @[el2_dec_tlu_ctl.scala 766:91] + wire i0_exception_valid_r = _T_527 & _T_528; // @[el2_dec_tlu_ctl.scala 766:89] + wire _T_789 = i0_exception_valid_r | rfpc_i0_r; // @[el2_dec_tlu_ctl.scala 865:48] + wire _T_402 = ~io_dec_tlu_flush_lower_wb; // @[el2_dec_tlu_ctl.scala 689:56] + wire lsu_exc_valid_r_raw = io_lsu_error_pkt_r_valid & _T_402; // @[el2_dec_tlu_ctl.scala 689:54] + wire _T_403 = io_lsu_error_pkt_r_valid & lsu_exc_valid_r_raw; // @[el2_dec_tlu_ctl.scala 691:39] + wire _T_405 = _T_403 & _T_465; // @[el2_dec_tlu_ctl.scala 691:61] + wire lsu_exc_valid_r = _T_405 & _T_470; // @[el2_dec_tlu_ctl.scala 691:81] + wire _T_790 = _T_789 | lsu_exc_valid_r; // @[el2_dec_tlu_ctl.scala 865:60] + wire _T_490 = io_dec_tlu_packet_r_fence_i & io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 743:49] + wire _T_492 = _T_490 & _T_465; // @[el2_dec_tlu_ctl.scala 743:73] + wire fence_i_r = _T_492 & _T_470; // @[el2_dec_tlu_ctl.scala 743:94] + wire _T_791 = _T_790 | fence_i_r; // @[el2_dec_tlu_ctl.scala 865:78] + wire _T_792 = _T_791 | lsu_i0_rfnpc_r; // @[el2_dec_tlu_ctl.scala 865:90] + wire _T_414 = io_dec_tlu_i0_valid_r & _T_470; // @[el2_dec_tlu_ctl.scala 704:49] + wire _T_415 = ~lsu_exc_valid_r; // @[el2_dec_tlu_ctl.scala 704:64] + wire _T_416 = _T_414 & _T_415; // @[el2_dec_tlu_ctl.scala 704:62] + wire _T_417 = ~inst_acc_r; // @[el2_dec_tlu_ctl.scala 704:81] + wire _T_418 = _T_416 & _T_417; // @[el2_dec_tlu_ctl.scala 704:78] + wire _T_420 = _T_418 & _T_528; // @[el2_dec_tlu_ctl.scala 704:93] + reg request_debug_mode_r_d1; // @[el2_dec_tlu_ctl.scala 542:81] + wire _T_421 = ~request_debug_mode_r_d1; // @[el2_dec_tlu_ctl.scala 704:120] + wire _T_422 = _T_420 & _T_421; // @[el2_dec_tlu_ctl.scala 704:118] + wire tlu_i0_commit_cmt = _T_422 & _T_465; // @[el2_dec_tlu_ctl.scala 704:145] + reg iccm_repair_state_d1; // @[el2_dec_tlu_ctl.scala 401:72] + wire _T_444 = tlu_i0_commit_cmt & iccm_repair_state_d1; // @[el2_dec_tlu_ctl.scala 722:51] + wire _T_484 = io_dec_tlu_packet_r_pmu_i0_itype == 4'hc; // @[el2_dec_tlu_ctl.scala 741:51] + wire _T_485 = _T_484 & io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 741:64] + wire _T_487 = _T_485 & _T_465; // @[el2_dec_tlu_ctl.scala 741:88] + wire mret_r = _T_487 & _T_470; // @[el2_dec_tlu_ctl.scala 741:108] + wire _T_446 = _T_523 | mret_r; // @[el2_dec_tlu_ctl.scala 722:97] + wire take_reset = reset_delayed & io_mpc_reset_run_req; // @[el2_dec_tlu_ctl.scala 851:31] + wire _T_447 = _T_446 | take_reset; // @[el2_dec_tlu_ctl.scala 722:106] + wire _T_448 = _T_447 | illegal_r; // @[el2_dec_tlu_ctl.scala 722:119] + wire _T_449 = io_dec_csr_wraddr_r == 12'h7c2; // @[el2_dec_tlu_ctl.scala 722:175] + wire _T_450 = dec_csr_wen_r_mod & _T_449; // @[el2_dec_tlu_ctl.scala 722:152] + wire _T_451 = _T_448 | _T_450; // @[el2_dec_tlu_ctl.scala 722:131] + wire _T_452 = ~_T_451; // @[el2_dec_tlu_ctl.scala 722:76] + wire iccm_repair_state_rfnpc = _T_444 & _T_452; // @[el2_dec_tlu_ctl.scala 722:74] + wire _T_793 = _T_792 | iccm_repair_state_rfnpc; // @[el2_dec_tlu_ctl.scala 865:107] + wire _T_794 = _T_793 | debug_resume_req_f; // @[el2_dec_tlu_ctl.scala 865:134] + wire _T_786 = i_cpu_run_req_d1 & pmu_fw_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 863:42] + wire _T_211 = ~io_dec_pause_state; // @[el2_dec_tlu_ctl.scala 562:22] + reg dec_pause_state_f; // @[el2_dec_tlu_ctl.scala 541:73] + wire _T_212 = _T_211 & dec_pause_state_f; // @[el2_dec_tlu_ctl.scala 562:42] + wire _T_213 = ext_int_ready | ce_int_ready; // @[el2_dec_tlu_ctl.scala 562:80] + wire _T_214 = _T_213 | timer_int_ready; // @[el2_dec_tlu_ctl.scala 562:95] + wire _T_215 = _T_214 | soft_int_ready; // @[el2_dec_tlu_ctl.scala 562:113] + wire _T_216 = _T_215 | int_timer0_int_hold_f; // @[el2_dec_tlu_ctl.scala 562:130] + wire _T_217 = _T_216 | int_timer1_int_hold_f; // @[el2_dec_tlu_ctl.scala 562:154] + wire _T_218 = _T_217 | nmi_int_detected; // @[el2_dec_tlu_ctl.scala 562:178] + wire _T_219 = _T_218 | ext_int_freeze_d1; // @[el2_dec_tlu_ctl.scala 562:197] + wire _T_220 = ~_T_219; // @[el2_dec_tlu_ctl.scala 562:64] + wire _T_221 = _T_212 & _T_220; // @[el2_dec_tlu_ctl.scala 562:62] + wire _T_223 = _T_221 & _T_140; // @[el2_dec_tlu_ctl.scala 562:218] + wire _T_225 = _T_223 & _T_378; // @[el2_dec_tlu_ctl.scala 562:242] + wire _T_226 = ~pmu_fw_halt_req_f; // @[el2_dec_tlu_ctl.scala 562:264] + wire _T_227 = _T_225 & _T_226; // @[el2_dec_tlu_ctl.scala 562:262] + wire _T_228 = ~halt_taken_f; // @[el2_dec_tlu_ctl.scala 562:285] + wire pause_expired_r = _T_227 & _T_228; // @[el2_dec_tlu_ctl.scala 562:283] + wire sel_npc_resume = _T_786 | pause_expired_r; // @[el2_dec_tlu_ctl.scala 863:65] + wire _T_795 = _T_794 | sel_npc_resume; // @[el2_dec_tlu_ctl.scala 865:156] + reg dec_tlu_wr_pause_r_d1; // @[el2_dec_tlu_ctl.scala 540:73] + wire _T_796 = _T_795 | dec_tlu_wr_pause_r_d1; // @[el2_dec_tlu_ctl.scala 865:174] + wire synchronous_flush_r = _T_796 | i0_trigger_hit_raw_r; // @[el2_dec_tlu_ctl.scala 865:200] + wire _T_749 = ~synchronous_flush_r; // @[el2_dec_tlu_ctl.scala 852:194] + wire _T_750 = _T_748 & _T_749; // @[el2_dec_tlu_ctl.scala 852:192] + wire _T_751 = ~mret_r; // @[el2_dec_tlu_ctl.scala 852:217] + wire _T_752 = _T_750 & _T_751; // @[el2_dec_tlu_ctl.scala 852:215] + wire _T_753 = ~take_reset; // @[el2_dec_tlu_ctl.scala 852:227] + wire _T_754 = _T_752 & _T_753; // @[el2_dec_tlu_ctl.scala 852:225] + wire _T_519 = _T_466 & dcsr[15]; // @[el2_dec_tlu_ctl.scala 750:120] + wire ebreak_to_debug_mode_r = _T_519 & _T_470; // @[el2_dec_tlu_ctl.scala 750:141] + wire _T_755 = ~ebreak_to_debug_mode_r; // @[el2_dec_tlu_ctl.scala 852:241] + wire _T_756 = _T_754 & _T_755; // @[el2_dec_tlu_ctl.scala 852:239] + wire _T_760 = _T_107 | _T_44; // @[el2_dec_tlu_ctl.scala 852:287] + wire take_nmi = _T_756 & _T_760; // @[el2_dec_tlu_ctl.scala 852:265] + wire _T_670 = _T_669 | take_nmi; // @[el2_dec_tlu_ctl.scala 820:154] + wire _T_671 = _T_670 | ebreak_to_debug_mode_r; // @[el2_dec_tlu_ctl.scala 820:165] + wire _T_672 = _T_671 | synchronous_flush_r; // @[el2_dec_tlu_ctl.scala 820:190] + reg exc_or_int_valid_r_d1; // @[el2_dec_tlu_ctl.scala 890:82] + wire _T_673 = _T_672 | exc_or_int_valid_r_d1; // @[el2_dec_tlu_ctl.scala 820:213] + wire _T_674 = _T_673 | mret_r; // @[el2_dec_tlu_ctl.scala 820:237] + wire block_interrupts = _T_674 | ext_int_freeze_d1; // @[el2_dec_tlu_ctl.scala 820:246] + wire _T_704 = ~block_interrupts; // @[el2_dec_tlu_ctl.scala 848:90] + wire take_timer_int = _T_703 & _T_704; // @[el2_dec_tlu_ctl.scala 848:88] + wire _T_762 = take_ext_int | take_timer_int; // @[el2_dec_tlu_ctl.scala 855:37] + wire _T_693 = soft_int_ready & _T_700; // @[el2_dec_tlu_ctl.scala 847:35] + wire _T_695 = _T_693 & _T_702; // @[el2_dec_tlu_ctl.scala 847:52] + wire take_soft_int = _T_695 & _T_704; // @[el2_dec_tlu_ctl.scala 847:68] + wire _T_763 = _T_762 | take_soft_int; // @[el2_dec_tlu_ctl.scala 855:54] + wire _T_764 = _T_763 | take_nmi; // @[el2_dec_tlu_ctl.scala 855:70] + wire _T_689 = ce_int_ready & _T_700; // @[el2_dec_tlu_ctl.scala 846:32] + wire take_ce_int = _T_689 & _T_704; // @[el2_dec_tlu_ctl.scala 846:49] + wire _T_765 = _T_764 | take_ce_int; // @[el2_dec_tlu_ctl.scala 855:81] + wire int_timer0_int_possible = mstatus_mie_ns & mie_ns[4]; // @[el2_dec_tlu_ctl.scala 806:48] + wire int_timer0_int_ready = mip[4] & int_timer0_int_possible; // @[el2_dec_tlu_ctl.scala 807:46] + wire _T_706 = int_timer0_int_ready | int_timer0_int_hold_f; // @[el2_dec_tlu_ctl.scala 849:48] + wire _T_707 = _T_706 & int_timer0_int_possible; // @[el2_dec_tlu_ctl.scala 849:73] + wire _T_709 = _T_707 & _T_631; // @[el2_dec_tlu_ctl.scala 849:99] + wire _T_710 = ~timer_int_ready; // @[el2_dec_tlu_ctl.scala 849:128] + wire _T_711 = _T_709 & _T_710; // @[el2_dec_tlu_ctl.scala 849:126] + wire _T_713 = _T_711 & _T_698; // @[el2_dec_tlu_ctl.scala 849:145] + wire _T_715 = _T_713 & _T_700; // @[el2_dec_tlu_ctl.scala 849:163] + wire _T_717 = _T_715 & _T_702; // @[el2_dec_tlu_ctl.scala 849:180] + wire take_int_timer0_int = _T_717 & _T_704; // @[el2_dec_tlu_ctl.scala 849:196] + wire _T_766 = _T_765 | take_int_timer0_int; // @[el2_dec_tlu_ctl.scala 855:95] + wire int_timer1_int_possible = mstatus_mie_ns & mie_ns[3]; // @[el2_dec_tlu_ctl.scala 808:48] + wire int_timer1_int_ready = mip[3] & int_timer1_int_possible; // @[el2_dec_tlu_ctl.scala 809:46] + wire _T_720 = int_timer1_int_ready | int_timer1_int_hold_f; // @[el2_dec_tlu_ctl.scala 850:48] + wire _T_721 = _T_720 & int_timer1_int_possible; // @[el2_dec_tlu_ctl.scala 850:73] + wire _T_723 = _T_721 & _T_631; // @[el2_dec_tlu_ctl.scala 850:99] + wire _T_725 = ~_T_706; // @[el2_dec_tlu_ctl.scala 850:128] + wire _T_726 = _T_723 & _T_725; // @[el2_dec_tlu_ctl.scala 850:126] + wire _T_728 = _T_726 & _T_710; // @[el2_dec_tlu_ctl.scala 850:176] + wire _T_730 = _T_728 & _T_698; // @[el2_dec_tlu_ctl.scala 850:195] + wire _T_732 = _T_730 & _T_700; // @[el2_dec_tlu_ctl.scala 850:213] + wire _T_734 = _T_732 & _T_702; // @[el2_dec_tlu_ctl.scala 850:230] + wire take_int_timer1_int = _T_734 & _T_704; // @[el2_dec_tlu_ctl.scala 850:246] + wire interrupt_valid_r = _T_766 | take_int_timer1_int; // @[el2_dec_tlu_ctl.scala 855:117] + wire _T_15 = _T_14 | interrupt_valid_r; // @[el2_dec_tlu_ctl.scala 396:68] + wire _T_16 = _T_15 | interrupt_valid_r_d1; // @[el2_dec_tlu_ctl.scala 396:88] + wire _T_17 = _T_16 | reset_delayed; // @[el2_dec_tlu_ctl.scala 396:111] + wire _T_18 = _T_17 | pause_expired_r; // @[el2_dec_tlu_ctl.scala 396:127] + reg pause_expired_wb; // @[el2_dec_tlu_ctl.scala 895:90] + wire _T_19 = _T_18 | pause_expired_wb; // @[el2_dec_tlu_ctl.scala 396:145] + wire _T_496 = io_ifu_ic_error_start & _T_107; // @[el2_dec_tlu_ctl.scala 744:42] + wire _T_498 = _T_152 | dcsr_single_step_running; // @[el2_dec_tlu_ctl.scala 744:92] + wire _T_499 = _T_496 & _T_498; // @[el2_dec_tlu_ctl.scala 744:63] + wire _T_500 = ~internal_pmu_fw_halt_mode_f; // @[el2_dec_tlu_ctl.scala 744:122] + wire ic_perr_r = _T_499 & _T_500; // @[el2_dec_tlu_ctl.scala 744:120] + wire _T_20 = _T_19 | ic_perr_r; // @[el2_dec_tlu_ctl.scala 396:164] + wire _T_21 = _T_20 | ic_perr_r_d1; // @[el2_dec_tlu_ctl.scala 396:176] + wire _T_503 = io_ifu_iccm_rd_ecc_single_err & _T_107; // @[el2_dec_tlu_ctl.scala 745:50] + wire _T_506 = _T_503 & _T_498; // @[el2_dec_tlu_ctl.scala 745:71] + wire iccm_sbecc_r = _T_506 & _T_500; // @[el2_dec_tlu_ctl.scala 745:128] + wire _T_22 = _T_21 | iccm_sbecc_r; // @[el2_dec_tlu_ctl.scala 396:191] + wire _T_23 = _T_22 | iccm_sbecc_r_d1; // @[el2_dec_tlu_ctl.scala 396:206] + wire flush_clkvalid = _T_23 | io_dec_tlu_dec_clk_override; // @[el2_dec_tlu_ctl.scala 396:224] + reg lsu_pmu_load_external_r; // @[el2_dec_tlu_ctl.scala 406:72] + reg lsu_pmu_store_external_r; // @[el2_dec_tlu_ctl.scala 407:64] + reg _T_32; // @[el2_dec_tlu_ctl.scala 409:65] + reg internal_dbg_halt_mode_f2; // @[el2_dec_tlu_ctl.scala 410:64] + reg _T_33; // @[el2_dec_tlu_ctl.scala 411:73] + reg nmi_lsu_load_type_f; // @[el2_dec_tlu_ctl.scala 422:72] + reg nmi_lsu_store_type_f; // @[el2_dec_tlu_ctl.scala 423:64] + wire _T_46 = nmi_lsu_detected & io_lsu_imprecise_error_load_any; // @[el2_dec_tlu_ctl.scala 431:42] + wire _T_49 = ~_T_41; // @[el2_dec_tlu_ctl.scala 431:78] + wire _T_50 = _T_46 & _T_49; // @[el2_dec_tlu_ctl.scala 431:76] + wire _T_52 = nmi_lsu_load_type_f & _T_40; // @[el2_dec_tlu_ctl.scala 431:141] + wire _T_54 = nmi_lsu_detected & io_lsu_imprecise_error_store_any; // @[el2_dec_tlu_ctl.scala 432:43] + wire _T_58 = _T_54 & _T_49; // @[el2_dec_tlu_ctl.scala 432:78] + wire _T_60 = nmi_lsu_store_type_f & _T_40; // @[el2_dec_tlu_ctl.scala 432:144] + reg mpc_debug_halt_req_sync_f; // @[el2_dec_tlu_ctl.scala 440:64] + reg mpc_debug_run_req_sync_f; // @[el2_dec_tlu_ctl.scala 441:64] + reg mpc_run_state_f; // @[el2_dec_tlu_ctl.scala 443:80] + reg debug_brkpt_status_f; // @[el2_dec_tlu_ctl.scala 444:72] + reg mpc_debug_halt_ack_f; // @[el2_dec_tlu_ctl.scala 445:72] + reg mpc_debug_run_ack_f; // @[el2_dec_tlu_ctl.scala 446:80] + reg dbg_run_state_f; // @[el2_dec_tlu_ctl.scala 448:80] + reg _T_65; // @[el2_dec_tlu_ctl.scala 449:73] + wire _T_66 = ~mpc_debug_halt_req_sync_f; // @[el2_dec_tlu_ctl.scala 453:65] + wire mpc_debug_halt_req_sync_pulse = mpc_debug_halt_req_sync & _T_66; // @[el2_dec_tlu_ctl.scala 453:63] + wire _T_67 = ~mpc_debug_run_req_sync_f; // @[el2_dec_tlu_ctl.scala 454:64] + wire mpc_debug_run_req_sync_pulse = mpc_debug_run_req_sync & _T_67; // @[el2_dec_tlu_ctl.scala 454:62] + wire _T_68 = mpc_halt_state_f | mpc_debug_halt_req_sync_pulse; // @[el2_dec_tlu_ctl.scala 456:42] + wire _T_71 = _T_68 | _T_111; // @[el2_dec_tlu_ctl.scala 456:74] + wire _T_72 = ~mpc_debug_run_req_sync; // @[el2_dec_tlu_ctl.scala 456:119] + wire mpc_halt_state_ns = _T_71 & _T_72; // @[el2_dec_tlu_ctl.scala 456:117] + wire _T_74 = ~mpc_debug_run_ack_f; // @[el2_dec_tlu_ctl.scala 457:74] + wire _T_75 = mpc_debug_run_req_sync_pulse & _T_74; // @[el2_dec_tlu_ctl.scala 457:72] + wire _T_76 = mpc_run_state_f | _T_75; // @[el2_dec_tlu_ctl.scala 457:40] + wire _T_77 = ~dcsr_single_step_running_f; // @[el2_dec_tlu_ctl.scala 457:127] + wire _T_78 = debug_mode_status & _T_77; // @[el2_dec_tlu_ctl.scala 457:125] + wire mpc_run_state_ns = _T_76 & _T_78; // @[el2_dec_tlu_ctl.scala 457:97] + wire _T_80 = dbg_halt_req_final | dcsr_single_step_done_f; // @[el2_dec_tlu_ctl.scala 459:64] + wire _T_81 = _T_80 | trigger_hit_dmode_r_d1; // @[el2_dec_tlu_ctl.scala 459:90] + wire _T_82 = _T_81 | ebreak_to_debug_mode_r_d1; // @[el2_dec_tlu_ctl.scala 459:115] + wire _T_83 = dbg_halt_state_f | _T_82; // @[el2_dec_tlu_ctl.scala 459:42] + wire _T_84 = ~io_dbg_resume_req; // @[el2_dec_tlu_ctl.scala 459:147] + wire dbg_halt_state_ns = _T_83 & _T_84; // @[el2_dec_tlu_ctl.scala 459:145] + wire _T_86 = dbg_run_state_f | io_dbg_resume_req; // @[el2_dec_tlu_ctl.scala 460:40] + wire dbg_run_state_ns = _T_86 & _T_78; // @[el2_dec_tlu_ctl.scala 460:61] + wire debug_brkpt_valid = ebreak_to_debug_mode_r_d1 | trigger_hit_dmode_r_d1; // @[el2_dec_tlu_ctl.scala 466:53] + wire _T_92 = debug_brkpt_valid | debug_brkpt_status_f; // @[el2_dec_tlu_ctl.scala 467:47] + wire _T_94 = internal_dbg_halt_mode & _T_77; // @[el2_dec_tlu_ctl.scala 467:97] + wire _T_96 = mpc_halt_state_f & debug_mode_status; // @[el2_dec_tlu_ctl.scala 470:45] + wire _T_97 = _T_96 & mpc_debug_halt_req_sync; // @[el2_dec_tlu_ctl.scala 470:72] + wire _T_99 = ~dbg_halt_state_ns; // @[el2_dec_tlu_ctl.scala 471:53] + wire _T_100 = mpc_debug_run_req_sync & _T_99; // @[el2_dec_tlu_ctl.scala 471:51] + wire _T_101 = ~mpc_debug_halt_req_sync; // @[el2_dec_tlu_ctl.scala 471:74] + wire _T_102 = _T_100 & _T_101; // @[el2_dec_tlu_ctl.scala 471:72] + wire _T_103 = mpc_debug_run_ack_f & mpc_debug_run_req_sync; // @[el2_dec_tlu_ctl.scala 471:123] + wire _T_118 = mpc_run_state_ns & _T_99; // @[el2_dec_tlu_ctl.scala 485:67] + wire _T_119 = ~mpc_halt_state_ns; // @[el2_dec_tlu_ctl.scala 485:111] + wire _T_120 = dbg_run_state_ns & _T_119; // @[el2_dec_tlu_ctl.scala 485:109] + wire _T_121 = _T_118 | _T_120; // @[el2_dec_tlu_ctl.scala 485:89] + wire _T_122 = debug_halt_req_f | pmu_fw_halt_req_f; // @[el2_dec_tlu_ctl.scala 490:37] + wire _T_124 = _T_122 & _T_749; // @[el2_dec_tlu_ctl.scala 490:58] + wire _T_126 = _T_124 & _T_751; // @[el2_dec_tlu_ctl.scala 490:81] + wire _T_128 = _T_126 & _T_228; // @[el2_dec_tlu_ctl.scala 490:91] + wire _T_129 = ~dec_tlu_flush_noredir_r_d1; // @[el2_dec_tlu_ctl.scala 490:109] + wire _T_130 = _T_128 & _T_129; // @[el2_dec_tlu_ctl.scala 490:107] + wire take_halt = _T_130 & _T_753; // @[el2_dec_tlu_ctl.scala 490:137] + wire _T_170 = debug_resume_req_f & dbg_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 515:43] + wire _T_172 = io_dec_tlu_i0_valid_r & _T_528; // @[el2_dec_tlu_ctl.scala 517:53] + wire _T_174 = _T_172 & dcsr[2]; // @[el2_dec_tlu_ctl.scala 517:78] + wire _T_329 = mtdata1_t_3[6] & mtdata1_t_3[9]; // @[el2_dec_tlu_ctl.scala 612:61] + wire _T_332 = mtdata1_t_2[6] & mtdata1_t_2[9]; // @[el2_dec_tlu_ctl.scala 612:121] + wire _T_335 = mtdata1_t_1[6] & mtdata1_t_1[9]; // @[el2_dec_tlu_ctl.scala 612:181] + wire _T_338 = mtdata1_t_0[6] & mtdata1_t_0[9]; // @[el2_dec_tlu_ctl.scala 612:241] + wire [3:0] trigger_action = {_T_329,_T_332,_T_335,_T_338}; // @[Cat.scala 29:58] + wire [3:0] _T_343 = i0_trigger_chain_masked_r & trigger_action; // @[el2_dec_tlu_ctl.scala 618:56] + wire i0_trigger_action_r = |_T_343; // @[el2_dec_tlu_ctl.scala 618:74] + wire trigger_hit_dmode_r = i0_trigger_hit_raw_r & i0_trigger_action_r; // @[el2_dec_tlu_ctl.scala 620:44] + wire _T_180 = trigger_hit_dmode_r | ebreak_to_debug_mode_r; // @[el2_dec_tlu_ctl.scala 524:51] + wire _T_182 = request_debug_mode_r_d1 & _T_402; // @[el2_dec_tlu_ctl.scala 524:104] + reg request_debug_mode_done_f; // @[el2_dec_tlu_ctl.scala 543:73] + wire _T_183 = request_debug_mode_r_d1 | request_debug_mode_done_f; // @[el2_dec_tlu_ctl.scala 526:58] + reg _T_190; // @[el2_dec_tlu_ctl.scala 534:73] + wire _T_201 = fence_i_r & internal_dbg_halt_mode; // @[el2_dec_tlu_ctl.scala 555:56] + wire _T_202 = take_halt | _T_201; // @[el2_dec_tlu_ctl.scala 555:43] + wire _T_203 = _T_202 | io_dec_tlu_flush_pause_r; // @[el2_dec_tlu_ctl.scala 555:82] + wire _T_204 = i0_trigger_hit_raw_r & trigger_hit_dmode_r; // @[el2_dec_tlu_ctl.scala 555:129] + wire _T_205 = _T_203 | _T_204; // @[el2_dec_tlu_ctl.scala 555:109] + wire take_ext_int_start = ext_int_ready & _T_704; // @[el2_dec_tlu_ctl.scala 828:41] + wire _T_207 = ~interrupt_valid_r; // @[el2_dec_tlu_ctl.scala 560:55] + wire _T_208 = dec_tlu_wr_pause_r_d1 & _T_207; // @[el2_dec_tlu_ctl.scala 560:53] + wire _T_209 = ~take_ext_int_start; // @[el2_dec_tlu_ctl.scala 560:76] + wire _T_231 = io_dec_tlu_flush_lower_r & dcsr[2]; // @[el2_dec_tlu_ctl.scala 564:60] + wire _T_232 = io_dec_tlu_resume_ack | dcsr_single_step_running; // @[el2_dec_tlu_ctl.scala 564:103] + wire _T_233 = _T_231 & _T_232; // @[el2_dec_tlu_ctl.scala 564:78] + wire _T_234 = ~io_dec_tlu_flush_noredir_r; // @[el2_dec_tlu_ctl.scala 564:133] + wire [3:0] _T_342 = i0_trigger_hit_raw_r ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire _T_345 = ~trigger_hit_dmode_r; // @[el2_dec_tlu_ctl.scala 622:54] + wire mepc_trigger_hit_sel_pc_r = i0_trigger_hit_raw_r & _T_345; // @[el2_dec_tlu_ctl.scala 622:52] + wire _T_350 = i_cpu_run_req_sync & _T_346; // @[el2_dec_tlu_ctl.scala 650:52] + wire _T_351 = _T_350 & pmu_fw_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 650:77] + wire i_cpu_run_req_sync_qual = _T_351 & _T_107; // @[el2_dec_tlu_ctl.scala 650:99] + reg _T_353; // @[el2_dec_tlu_ctl.scala 654:73] + reg _T_354; // @[el2_dec_tlu_ctl.scala 655:81] + reg _T_355; // @[el2_dec_tlu_ctl.scala 656:81] + wire _T_384 = io_o_cpu_halt_status & _T_375; // @[el2_dec_tlu_ctl.scala 674:88] + wire _T_386 = _T_384 & _T_152; // @[el2_dec_tlu_ctl.scala 674:108] + wire _T_388 = io_o_cpu_halt_status & i_cpu_run_req_sync_qual; // @[el2_dec_tlu_ctl.scala 675:40] + wire _T_389 = io_o_cpu_run_ack & i_cpu_run_req_sync_qual; // @[el2_dec_tlu_ctl.scala 675:87] + reg lsu_single_ecc_error_r_d1; // @[el2_dec_tlu_ctl.scala 687:64] + reg lsu_i0_exc_r_d1; // @[el2_dec_tlu_ctl.scala 694:73] + wire _T_408 = ~io_lsu_error_pkt_r_bits_exc_type; // @[el2_dec_tlu_ctl.scala 695:39] + wire lsu_exc_ma_r = lsu_exc_valid_r & _T_408; // @[el2_dec_tlu_ctl.scala 695:37] + wire lsu_exc_acc_r = lsu_exc_valid_r & io_lsu_error_pkt_r_bits_exc_type; // @[el2_dec_tlu_ctl.scala 696:37] + wire lsu_exc_st_r = lsu_exc_valid_r & io_lsu_error_pkt_r_bits_inst_type; // @[el2_dec_tlu_ctl.scala 697:37] + wire _T_424 = rfpc_i0_r | lsu_exc_valid_r; // @[el2_dec_tlu_ctl.scala 707:37] + wire _T_425 = _T_424 | inst_acc_r; // @[el2_dec_tlu_ctl.scala 707:52] + wire _T_426 = illegal_r & io_dec_tlu_dbg_halted; // @[el2_dec_tlu_ctl.scala 707:78] + wire _T_427 = _T_425 | _T_426; // @[el2_dec_tlu_ctl.scala 707:65] + wire _T_441 = ~io_dec_tlu_flush_lower_r; // @[el2_dec_tlu_ctl.scala 716:69] + wire _T_442 = iccm_repair_state_d1 & _T_441; // @[el2_dec_tlu_ctl.scala 716:67] + wire _T_453 = io_exu_i0_br_error_r & io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 725:50] + wire _T_455 = io_exu_i0_br_start_error_r & io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 726:62] + wire _T_457 = io_exu_i0_br_valid_r & io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 727:46] + wire _T_459 = _T_457 & _T_429; // @[el2_dec_tlu_ctl.scala 727:70] + wire _T_460 = ~io_exu_i0_br_mp_r; // @[el2_dec_tlu_ctl.scala 727:97] + wire _T_461 = ~io_exu_pmu_i0_br_ataken; // @[el2_dec_tlu_ctl.scala 727:118] + wire _T_462 = _T_460 | _T_461; // @[el2_dec_tlu_ctl.scala 727:116] + wire _T_529 = ~take_nmi; // @[el2_dec_tlu_ctl.scala 775:21] + wire _T_530 = take_ext_int & _T_529; // @[el2_dec_tlu_ctl.scala 775:19] + wire _T_533 = take_timer_int & _T_529; // @[el2_dec_tlu_ctl.scala 776:21] + wire _T_536 = take_soft_int & _T_529; // @[el2_dec_tlu_ctl.scala 777:20] + wire _T_539 = take_int_timer0_int & _T_529; // @[el2_dec_tlu_ctl.scala 778:26] + wire _T_542 = take_int_timer1_int & _T_529; // @[el2_dec_tlu_ctl.scala 779:26] + wire _T_545 = take_ce_int & _T_529; // @[el2_dec_tlu_ctl.scala 780:18] + wire _T_548 = illegal_r & _T_529; // @[el2_dec_tlu_ctl.scala 781:16] + wire _T_551 = ecall_r & _T_529; // @[el2_dec_tlu_ctl.scala 782:15] + wire _T_554 = inst_acc_r & _T_529; // @[el2_dec_tlu_ctl.scala 783:18] + wire _T_556 = ebreak_r | i0_trigger_hit_raw_r; // @[el2_dec_tlu_ctl.scala 784:16] + wire _T_558 = _T_556 & _T_529; // @[el2_dec_tlu_ctl.scala 784:36] + wire _T_560 = ~lsu_exc_st_r; // @[el2_dec_tlu_ctl.scala 785:21] + wire _T_561 = lsu_exc_ma_r & _T_560; // @[el2_dec_tlu_ctl.scala 785:19] + wire _T_563 = _T_561 & _T_529; // @[el2_dec_tlu_ctl.scala 785:35] + wire _T_566 = lsu_exc_acc_r & _T_560; // @[el2_dec_tlu_ctl.scala 786:20] + wire _T_568 = _T_566 & _T_529; // @[el2_dec_tlu_ctl.scala 786:36] + wire _T_570 = lsu_exc_ma_r & lsu_exc_st_r; // @[el2_dec_tlu_ctl.scala 787:19] + wire _T_572 = _T_570 & _T_529; // @[el2_dec_tlu_ctl.scala 787:34] + wire _T_574 = lsu_exc_acc_r & lsu_exc_st_r; // @[el2_dec_tlu_ctl.scala 788:20] + wire _T_576 = _T_574 & _T_529; // @[el2_dec_tlu_ctl.scala 788:35] + wire [4:0] _T_578 = _T_530 ? 5'hb : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_579 = _T_533 ? 5'h7 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_580 = _T_536 ? 5'h3 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_581 = _T_539 ? 5'h1d : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_582 = _T_542 ? 5'h1c : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_583 = _T_545 ? 5'h1e : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_584 = _T_548 ? 5'h2 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_585 = _T_551 ? 5'hb : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_586 = _T_554 ? 5'h1 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_587 = _T_558 ? 5'h3 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_588 = _T_563 ? 5'h4 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_589 = _T_568 ? 5'h5 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_590 = _T_572 ? 5'h6 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_591 = _T_576 ? 5'h7 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_592 = _T_578 | _T_579; // @[Mux.scala 27:72] + wire [4:0] _T_593 = _T_592 | _T_580; // @[Mux.scala 27:72] + wire [4:0] _T_594 = _T_593 | _T_581; // @[Mux.scala 27:72] + wire [4:0] _T_595 = _T_594 | _T_582; // @[Mux.scala 27:72] + wire [4:0] _T_596 = _T_595 | _T_583; // @[Mux.scala 27:72] + wire [4:0] _T_597 = _T_596 | _T_584; // @[Mux.scala 27:72] + wire [4:0] _T_598 = _T_597 | _T_585; // @[Mux.scala 27:72] + wire [4:0] _T_599 = _T_598 | _T_586; // @[Mux.scala 27:72] + wire [4:0] _T_600 = _T_599 | _T_587; // @[Mux.scala 27:72] + wire [4:0] _T_601 = _T_600 | _T_588; // @[Mux.scala 27:72] + wire [4:0] _T_602 = _T_601 | _T_589; // @[Mux.scala 27:72] + wire [4:0] _T_603 = _T_602 | _T_590; // @[Mux.scala 27:72] + wire [4:0] exc_cause_r = _T_603 | _T_591; // @[Mux.scala 27:72] + wire _T_641 = io_dec_csr_stall_int_ff | synchronous_flush_r; // @[el2_dec_tlu_ctl.scala 813:51] + wire _T_642 = _T_641 | exc_or_int_valid_r_d1; // @[el2_dec_tlu_ctl.scala 813:73] + wire int_timer_stalled = _T_642 | mret_r; // @[el2_dec_tlu_ctl.scala 813:97] + wire _T_643 = pmu_fw_tlu_halted_f | int_timer_stalled; // @[el2_dec_tlu_ctl.scala 815:71] + wire _T_644 = int_timer0_int_ready & _T_643; // @[el2_dec_tlu_ctl.scala 815:48] + wire _T_645 = int_timer0_int_possible & int_timer0_int_hold_f; // @[el2_dec_tlu_ctl.scala 815:120] + wire _T_647 = _T_645 & _T_207; // @[el2_dec_tlu_ctl.scala 815:144] + wire _T_649 = _T_647 & _T_209; // @[el2_dec_tlu_ctl.scala 815:165] + wire _T_651 = _T_649 & _T_152; // @[el2_dec_tlu_ctl.scala 815:187] + wire _T_654 = int_timer1_int_ready & _T_643; // @[el2_dec_tlu_ctl.scala 816:48] + wire _T_655 = int_timer1_int_possible & int_timer1_int_hold_f; // @[el2_dec_tlu_ctl.scala 816:120] + wire _T_657 = _T_655 & _T_207; // @[el2_dec_tlu_ctl.scala 816:144] + wire _T_659 = _T_657 & _T_209; // @[el2_dec_tlu_ctl.scala 816:165] + wire _T_661 = _T_659 & _T_152; // @[el2_dec_tlu_ctl.scala 816:187] + reg take_ext_int_start_d2; // @[el2_dec_tlu_ctl.scala 825:58] + wire _T_681 = take_ext_int_start | take_ext_int_start_d1; // @[el2_dec_tlu_ctl.scala 830:42] + wire _T_682 = _T_681 | take_ext_int_start_d2; // @[el2_dec_tlu_ctl.scala 830:66] + wire csr_pkt_csr_meicpct = csr_read_io_csr_pkt_csr_meicpct; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10] + wire fast_int_meicpct = csr_pkt_csr_meicpct & io_dec_csr_any_unq_d; // @[el2_dec_tlu_ctl.scala 832:45] + wire [30:0] mtvec = csr_io_mtvec; // @[el2_dec_tlu_ctl.scala 1087:31] + wire [30:0] _T_769 = {mtvec[30:1],1'h0}; // @[Cat.scala 29:58] + wire [30:0] _T_771 = {25'h0,exc_cause_r,1'h0}; // @[Cat.scala 29:58] + wire [30:0] vectored_path = _T_769 + _T_771; // @[el2_dec_tlu_ctl.scala 860:50] + wire [30:0] _T_778 = mtvec[0] ? vectored_path : _T_769; // @[el2_dec_tlu_ctl.scala 861:60] + wire [30:0] interrupt_path = take_nmi ? io_nmi_vec : _T_778; // @[el2_dec_tlu_ctl.scala 861:27] + wire _T_779 = lsu_i0_rfnpc_r | fence_i_r; // @[el2_dec_tlu_ctl.scala 862:35] + wire _T_780 = _T_779 | iccm_repair_state_rfnpc; // @[el2_dec_tlu_ctl.scala 862:47] + wire _T_782 = i_cpu_run_req_d1 & _T_207; // @[el2_dec_tlu_ctl.scala 862:93] + wire _T_783 = _T_780 | _T_782; // @[el2_dec_tlu_ctl.scala 862:73] + wire _T_785 = rfpc_i0_r & _T_743; // @[el2_dec_tlu_ctl.scala 862:128] + wire sel_npc_r = _T_783 | _T_785; // @[el2_dec_tlu_ctl.scala 862:115] + wire _T_798 = interrupt_valid_r | mret_r; // @[el2_dec_tlu_ctl.scala 866:42] + wire _T_799 = _T_798 | synchronous_flush_r; // @[el2_dec_tlu_ctl.scala 866:51] + wire _T_800 = _T_799 | take_halt; // @[el2_dec_tlu_ctl.scala 866:73] + wire _T_801 = _T_800 | take_reset; // @[el2_dec_tlu_ctl.scala 866:85] + wire _T_807 = _T_529 & sel_npc_r; // @[el2_dec_tlu_ctl.scala 870:21] + wire _T_810 = _T_529 & rfpc_i0_r; // @[el2_dec_tlu_ctl.scala 871:21] + wire _T_812 = _T_810 & io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 871:39] + wire _T_813 = ~sel_npc_r; // @[el2_dec_tlu_ctl.scala 871:80] + wire _T_814 = _T_812 & _T_813; // @[el2_dec_tlu_ctl.scala 871:69] + wire _T_816 = ~take_ext_int; // @[el2_dec_tlu_ctl.scala 872:44] + wire _T_817 = interrupt_valid_r & _T_816; // @[el2_dec_tlu_ctl.scala 872:30] + wire _T_818 = i0_exception_valid_r | lsu_exc_valid_r; // @[el2_dec_tlu_ctl.scala 873:28] + wire _T_821 = _T_818 | mepc_trigger_hit_sel_pc_r; // @[el2_dec_tlu_ctl.scala 873:46] + wire _T_823 = _T_821 & _T_207; // @[el2_dec_tlu_ctl.scala 873:91] + wire _T_825 = _T_823 & _T_816; // @[el2_dec_tlu_ctl.scala 873:112] + wire _T_830 = _T_529 & mret_r; // @[el2_dec_tlu_ctl.scala 874:16] + wire _T_833 = _T_529 & debug_resume_req_f; // @[el2_dec_tlu_ctl.scala 875:16] + wire _T_836 = _T_529 & sel_npc_resume; // @[el2_dec_tlu_ctl.scala 876:16] + wire [30:0] _T_838 = take_ext_int ? io_lsu_fir_addr : 31'h0; // @[Mux.scala 27:72] + wire [30:0] npc_r = csr_io_npc_r; // @[el2_dec_tlu_ctl.scala 1075:31] + wire [30:0] _T_839 = _T_807 ? npc_r : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_840 = _T_814 ? io_dec_tlu_i0_pc_r : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_841 = _T_817 ? interrupt_path : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_842 = _T_825 ? _T_769 : 31'h0; // @[Mux.scala 27:72] + wire [30:0] mepc = csr_io_mepc; // @[el2_dec_tlu_ctl.scala 1078:31] + wire [30:0] _T_843 = _T_830 ? mepc : 31'h0; // @[Mux.scala 27:72] + wire [30:0] dpc = csr_io_dpc; // @[el2_dec_tlu_ctl.scala 1081:31] + wire [30:0] _T_844 = _T_833 ? dpc : 31'h0; // @[Mux.scala 27:72] + wire [30:0] npc_r_d1 = csr_io_npc_r_d1; // @[el2_dec_tlu_ctl.scala 1076:31] + wire [30:0] _T_845 = _T_836 ? npc_r_d1 : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_846 = _T_838 | _T_839; // @[Mux.scala 27:72] + wire [30:0] _T_847 = _T_846 | _T_840; // @[Mux.scala 27:72] + wire [30:0] _T_848 = _T_847 | _T_841; // @[Mux.scala 27:72] + wire [30:0] _T_849 = _T_848 | _T_842; // @[Mux.scala 27:72] + wire [30:0] _T_850 = _T_849 | _T_843; // @[Mux.scala 27:72] + wire [30:0] _T_851 = _T_850 | _T_844; // @[Mux.scala 27:72] + wire [30:0] _T_852 = _T_851 | _T_845; // @[Mux.scala 27:72] + reg [30:0] tlu_flush_path_r_d1; // @[el2_dec_tlu_ctl.scala 879:58] + wire _T_854 = lsu_exc_valid_r | i0_exception_valid_r; // @[el2_dec_tlu_ctl.scala 886:44] + wire _T_855 = _T_854 | interrupt_valid_r; // @[el2_dec_tlu_ctl.scala 886:67] + reg i0_exception_valid_r_d1; // @[el2_dec_tlu_ctl.scala 889:81] + reg [4:0] exc_cause_wb; // @[el2_dec_tlu_ctl.scala 891:89] + wire _T_860 = ~illegal_r; // @[el2_dec_tlu_ctl.scala 892:119] + reg i0_valid_wb; // @[el2_dec_tlu_ctl.scala 892:97] + reg trigger_hit_r_d1; // @[el2_dec_tlu_ctl.scala 893:81] + wire csr_pkt_presync = csr_read_io_csr_pkt_presync; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10] + wire _T_864 = csr_pkt_presync & io_dec_csr_any_unq_d; // @[el2_dec_tlu_ctl.scala 1094:44] + wire _T_865 = ~io_dec_csr_wen_unq_d; // @[el2_dec_tlu_ctl.scala 1094:69] + wire csr_pkt_postsync = csr_read_io_csr_pkt_postsync; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10] + wire csr_pkt_csr_dcsr = csr_read_io_csr_pkt_csr_dcsr; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10] + wire csr_pkt_csr_dpc = csr_read_io_csr_pkt_csr_dpc; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10] + wire _T_874 = csr_pkt_csr_dcsr | csr_pkt_csr_dpc; // @[el2_dec_tlu_ctl.scala 1099:57] + wire csr_pkt_csr_dmst = csr_read_io_csr_pkt_csr_dmst; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10] + wire _T_875 = _T_874 | csr_pkt_csr_dmst; // @[el2_dec_tlu_ctl.scala 1099:75] + wire csr_pkt_csr_dicawics = csr_read_io_csr_pkt_csr_dicawics; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10] + wire _T_876 = _T_875 | csr_pkt_csr_dicawics; // @[el2_dec_tlu_ctl.scala 1099:94] + wire csr_pkt_csr_dicad0 = csr_read_io_csr_pkt_csr_dicad0; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10] + wire _T_877 = _T_876 | csr_pkt_csr_dicad0; // @[el2_dec_tlu_ctl.scala 1099:117] + wire csr_pkt_csr_dicad0h = csr_read_io_csr_pkt_csr_dicad0h; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10] + wire _T_878 = _T_877 | csr_pkt_csr_dicad0h; // @[el2_dec_tlu_ctl.scala 1099:138] + wire csr_pkt_csr_dicad1 = csr_read_io_csr_pkt_csr_dicad1; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10] + wire _T_879 = _T_878 | csr_pkt_csr_dicad1; // @[el2_dec_tlu_ctl.scala 1099:160] + wire csr_pkt_csr_dicago = csr_read_io_csr_pkt_csr_dicago; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10] + wire _T_880 = _T_879 | csr_pkt_csr_dicago; // @[el2_dec_tlu_ctl.scala 1099:181] + wire _T_881 = ~_T_880; // @[el2_dec_tlu_ctl.scala 1099:38] + wire _T_882 = _T_881 | dbg_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 1099:203] + wire csr_pkt_legal = csr_read_io_csr_pkt_legal; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10] + wire _T_883 = csr_pkt_legal & _T_882; // @[el2_dec_tlu_ctl.scala 1099:35] + wire _T_884 = ~fast_int_meicpct; // @[el2_dec_tlu_ctl.scala 1099:225] + wire valid_csr = _T_883 & _T_884; // @[el2_dec_tlu_ctl.scala 1099:223] + wire _T_887 = io_dec_csr_any_unq_d & valid_csr; // @[el2_dec_tlu_ctl.scala 1101:48] + wire csr_pkt_csr_mvendorid = csr_read_io_csr_pkt_csr_mvendorid; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10] + wire csr_pkt_csr_marchid = csr_read_io_csr_pkt_csr_marchid; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10] + wire _T_888 = csr_pkt_csr_mvendorid | csr_pkt_csr_marchid; // @[el2_dec_tlu_ctl.scala 1101:109] + wire csr_pkt_csr_mimpid = csr_read_io_csr_pkt_csr_mimpid; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10] + wire _T_889 = _T_888 | csr_pkt_csr_mimpid; // @[el2_dec_tlu_ctl.scala 1101:131] + wire csr_pkt_csr_mhartid = csr_read_io_csr_pkt_csr_mhartid; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10] + wire _T_890 = _T_889 | csr_pkt_csr_mhartid; // @[el2_dec_tlu_ctl.scala 1101:152] + wire csr_pkt_csr_mdseac = csr_read_io_csr_pkt_csr_mdseac; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10] + wire _T_891 = _T_890 | csr_pkt_csr_mdseac; // @[el2_dec_tlu_ctl.scala 1101:174] + wire csr_pkt_csr_meihap = csr_read_io_csr_pkt_csr_meihap; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10] + wire _T_892 = _T_891 | csr_pkt_csr_meihap; // @[el2_dec_tlu_ctl.scala 1101:195] + wire _T_893 = io_dec_csr_wen_unq_d & _T_892; // @[el2_dec_tlu_ctl.scala 1101:84] + wire _T_894 = ~_T_893; // @[el2_dec_tlu_ctl.scala 1101:61] + el2_dec_timer_ctl int_timers ( // @[el2_dec_tlu_ctl.scala 355:24] + .clock(int_timers_clock), + .reset(int_timers_reset), + .io_free_clk(int_timers_io_free_clk), + .io_scan_mode(int_timers_io_scan_mode), + .io_dec_csr_wen_r_mod(int_timers_io_dec_csr_wen_r_mod), + .io_dec_csr_wraddr_r(int_timers_io_dec_csr_wraddr_r), + .io_dec_csr_wrdata_r(int_timers_io_dec_csr_wrdata_r), + .io_csr_mitctl0(int_timers_io_csr_mitctl0), + .io_csr_mitctl1(int_timers_io_csr_mitctl1), + .io_csr_mitb0(int_timers_io_csr_mitb0), + .io_csr_mitb1(int_timers_io_csr_mitb1), + .io_csr_mitcnt0(int_timers_io_csr_mitcnt0), + .io_csr_mitcnt1(int_timers_io_csr_mitcnt1), + .io_dec_pause_state(int_timers_io_dec_pause_state), + .io_dec_tlu_pmu_fw_halted(int_timers_io_dec_tlu_pmu_fw_halted), + .io_internal_dbg_halt_timers(int_timers_io_internal_dbg_halt_timers), + .io_dec_timer_rddata_d(int_timers_io_dec_timer_rddata_d), + .io_dec_timer_read_d(int_timers_io_dec_timer_read_d), + .io_dec_timer_t0_pulse(int_timers_io_dec_timer_t0_pulse), + .io_dec_timer_t1_pulse(int_timers_io_dec_timer_t1_pulse) + ); + rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_io_l1clk), + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en), + .io_scan_mode(rvclkhdr_io_scan_mode) + ); + rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_1_io_l1clk), + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en), + .io_scan_mode(rvclkhdr_1_io_scan_mode) + ); + rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_2_io_l1clk), + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en), + .io_scan_mode(rvclkhdr_2_io_scan_mode) + ); + rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_3_io_l1clk), + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en), + .io_scan_mode(rvclkhdr_3_io_scan_mode) + ); + csr_tlu csr ( // @[el2_dec_tlu_ctl.scala 897:17] + .clock(csr_clock), + .reset(csr_reset), + .io_free_clk(csr_io_free_clk), + .io_active_clk(csr_io_active_clk), + .io_scan_mode(csr_io_scan_mode), + .io_dec_csr_wrdata_r(csr_io_dec_csr_wrdata_r), + .io_dec_csr_wraddr_r(csr_io_dec_csr_wraddr_r), + .io_dec_csr_rdaddr_d(csr_io_dec_csr_rdaddr_d), + .io_dec_csr_wen_unq_d(csr_io_dec_csr_wen_unq_d), + .io_dec_i0_decode_d(csr_io_dec_i0_decode_d), + .io_dec_tlu_ic_diag_pkt_icache_wrdata(csr_io_dec_tlu_ic_diag_pkt_icache_wrdata), + .io_dec_tlu_ic_diag_pkt_icache_dicawics(csr_io_dec_tlu_ic_diag_pkt_icache_dicawics), + .io_dec_tlu_ic_diag_pkt_icache_rd_valid(csr_io_dec_tlu_ic_diag_pkt_icache_rd_valid), + .io_dec_tlu_ic_diag_pkt_icache_wr_valid(csr_io_dec_tlu_ic_diag_pkt_icache_wr_valid), + .io_ifu_ic_debug_rd_data_valid(csr_io_ifu_ic_debug_rd_data_valid), + .io_trigger_pkt_any_0_select(csr_io_trigger_pkt_any_0_select), + .io_trigger_pkt_any_0_match_pkt(csr_io_trigger_pkt_any_0_match_pkt), + .io_trigger_pkt_any_0_store(csr_io_trigger_pkt_any_0_store), + .io_trigger_pkt_any_0_load(csr_io_trigger_pkt_any_0_load), + .io_trigger_pkt_any_0_execute(csr_io_trigger_pkt_any_0_execute), + .io_trigger_pkt_any_0_m(csr_io_trigger_pkt_any_0_m), + .io_trigger_pkt_any_0_tdata2(csr_io_trigger_pkt_any_0_tdata2), + .io_trigger_pkt_any_1_select(csr_io_trigger_pkt_any_1_select), + .io_trigger_pkt_any_1_match_pkt(csr_io_trigger_pkt_any_1_match_pkt), + .io_trigger_pkt_any_1_store(csr_io_trigger_pkt_any_1_store), + .io_trigger_pkt_any_1_load(csr_io_trigger_pkt_any_1_load), + .io_trigger_pkt_any_1_execute(csr_io_trigger_pkt_any_1_execute), + .io_trigger_pkt_any_1_m(csr_io_trigger_pkt_any_1_m), + .io_trigger_pkt_any_1_tdata2(csr_io_trigger_pkt_any_1_tdata2), + .io_trigger_pkt_any_2_select(csr_io_trigger_pkt_any_2_select), + .io_trigger_pkt_any_2_match_pkt(csr_io_trigger_pkt_any_2_match_pkt), + .io_trigger_pkt_any_2_store(csr_io_trigger_pkt_any_2_store), + .io_trigger_pkt_any_2_load(csr_io_trigger_pkt_any_2_load), + .io_trigger_pkt_any_2_execute(csr_io_trigger_pkt_any_2_execute), + .io_trigger_pkt_any_2_m(csr_io_trigger_pkt_any_2_m), + .io_trigger_pkt_any_2_tdata2(csr_io_trigger_pkt_any_2_tdata2), + .io_trigger_pkt_any_3_select(csr_io_trigger_pkt_any_3_select), + .io_trigger_pkt_any_3_match_pkt(csr_io_trigger_pkt_any_3_match_pkt), + .io_trigger_pkt_any_3_store(csr_io_trigger_pkt_any_3_store), + .io_trigger_pkt_any_3_load(csr_io_trigger_pkt_any_3_load), + .io_trigger_pkt_any_3_execute(csr_io_trigger_pkt_any_3_execute), + .io_trigger_pkt_any_3_m(csr_io_trigger_pkt_any_3_m), + .io_trigger_pkt_any_3_tdata2(csr_io_trigger_pkt_any_3_tdata2), + .io_ifu_pmu_bus_trxn(csr_io_ifu_pmu_bus_trxn), + .io_dma_iccm_stall_any(csr_io_dma_iccm_stall_any), + .io_dma_dccm_stall_any(csr_io_dma_dccm_stall_any), + .io_lsu_store_stall_any(csr_io_lsu_store_stall_any), + .io_dec_pmu_presync_stall(csr_io_dec_pmu_presync_stall), + .io_dec_pmu_postsync_stall(csr_io_dec_pmu_postsync_stall), + .io_dec_pmu_decode_stall(csr_io_dec_pmu_decode_stall), + .io_ifu_pmu_fetch_stall(csr_io_ifu_pmu_fetch_stall), + .io_dec_tlu_packet_r_icaf_type(csr_io_dec_tlu_packet_r_icaf_type), + .io_dec_tlu_packet_r_pmu_i0_itype(csr_io_dec_tlu_packet_r_pmu_i0_itype), + .io_dec_tlu_packet_r_pmu_i0_br_unpred(csr_io_dec_tlu_packet_r_pmu_i0_br_unpred), + .io_dec_tlu_packet_r_pmu_divide(csr_io_dec_tlu_packet_r_pmu_divide), + .io_dec_tlu_packet_r_pmu_lsu_misaligned(csr_io_dec_tlu_packet_r_pmu_lsu_misaligned), + .io_exu_pmu_i0_br_ataken(csr_io_exu_pmu_i0_br_ataken), + .io_exu_pmu_i0_br_misp(csr_io_exu_pmu_i0_br_misp), + .io_dec_pmu_instr_decoded(csr_io_dec_pmu_instr_decoded), + .io_ifu_pmu_instr_aligned(csr_io_ifu_pmu_instr_aligned), + .io_exu_pmu_i0_pc4(csr_io_exu_pmu_i0_pc4), + .io_ifu_pmu_ic_miss(csr_io_ifu_pmu_ic_miss), + .io_ifu_pmu_ic_hit(csr_io_ifu_pmu_ic_hit), + .io_dec_tlu_int_valid_wb1(csr_io_dec_tlu_int_valid_wb1), + .io_dec_tlu_i0_exc_valid_wb1(csr_io_dec_tlu_i0_exc_valid_wb1), + .io_dec_tlu_i0_valid_wb1(csr_io_dec_tlu_i0_valid_wb1), + .io_dec_csr_wen_r(csr_io_dec_csr_wen_r), + .io_dec_tlu_mtval_wb1(csr_io_dec_tlu_mtval_wb1), + .io_dec_tlu_exc_cause_wb1(csr_io_dec_tlu_exc_cause_wb1), + .io_dec_tlu_perfcnt0(csr_io_dec_tlu_perfcnt0), + .io_dec_tlu_perfcnt1(csr_io_dec_tlu_perfcnt1), + .io_dec_tlu_perfcnt2(csr_io_dec_tlu_perfcnt2), + .io_dec_tlu_perfcnt3(csr_io_dec_tlu_perfcnt3), + .io_dec_tlu_dbg_halted(csr_io_dec_tlu_dbg_halted), + .io_dma_pmu_dccm_write(csr_io_dma_pmu_dccm_write), + .io_dma_pmu_dccm_read(csr_io_dma_pmu_dccm_read), + .io_dma_pmu_any_write(csr_io_dma_pmu_any_write), + .io_dma_pmu_any_read(csr_io_dma_pmu_any_read), + .io_lsu_pmu_bus_busy(csr_io_lsu_pmu_bus_busy), + .io_dec_tlu_i0_pc_r(csr_io_dec_tlu_i0_pc_r), + .io_dec_tlu_i0_valid_r(csr_io_dec_tlu_i0_valid_r), + .io_dec_csr_any_unq_d(csr_io_dec_csr_any_unq_d), + .io_dec_tlu_misc_clk_override(csr_io_dec_tlu_misc_clk_override), + .io_dec_tlu_dec_clk_override(csr_io_dec_tlu_dec_clk_override), + .io_dec_tlu_ifu_clk_override(csr_io_dec_tlu_ifu_clk_override), + .io_dec_tlu_lsu_clk_override(csr_io_dec_tlu_lsu_clk_override), + .io_dec_tlu_bus_clk_override(csr_io_dec_tlu_bus_clk_override), + .io_dec_tlu_pic_clk_override(csr_io_dec_tlu_pic_clk_override), + .io_dec_tlu_dccm_clk_override(csr_io_dec_tlu_dccm_clk_override), + .io_dec_tlu_icm_clk_override(csr_io_dec_tlu_icm_clk_override), + .io_dec_csr_rddata_d(csr_io_dec_csr_rddata_d), + .io_dec_tlu_pipelining_disable(csr_io_dec_tlu_pipelining_disable), + .io_dec_tlu_wr_pause_r(csr_io_dec_tlu_wr_pause_r), + .io_ifu_pmu_bus_busy(csr_io_ifu_pmu_bus_busy), + .io_lsu_pmu_bus_error(csr_io_lsu_pmu_bus_error), + .io_ifu_pmu_bus_error(csr_io_ifu_pmu_bus_error), + .io_lsu_pmu_bus_misaligned(csr_io_lsu_pmu_bus_misaligned), + .io_lsu_pmu_bus_trxn(csr_io_lsu_pmu_bus_trxn), + .io_ifu_ic_debug_rd_data(csr_io_ifu_ic_debug_rd_data), + .io_dec_tlu_meipt(csr_io_dec_tlu_meipt), + .io_pic_pl(csr_io_pic_pl), + .io_dec_tlu_meicurpl(csr_io_dec_tlu_meicurpl), + .io_dec_tlu_meihap(csr_io_dec_tlu_meihap), + .io_pic_claimid(csr_io_pic_claimid), + .io_iccm_dma_sb_error(csr_io_iccm_dma_sb_error), + .io_lsu_imprecise_error_addr_any(csr_io_lsu_imprecise_error_addr_any), + .io_lsu_imprecise_error_load_any(csr_io_lsu_imprecise_error_load_any), + .io_lsu_imprecise_error_store_any(csr_io_lsu_imprecise_error_store_any), + .io_dec_tlu_mrac_ff(csr_io_dec_tlu_mrac_ff), + .io_dec_tlu_wb_coalescing_disable(csr_io_dec_tlu_wb_coalescing_disable), + .io_dec_tlu_bpred_disable(csr_io_dec_tlu_bpred_disable), + .io_dec_tlu_sideeffect_posted_disable(csr_io_dec_tlu_sideeffect_posted_disable), + .io_dec_tlu_core_ecc_disable(csr_io_dec_tlu_core_ecc_disable), + .io_dec_tlu_external_ldfwd_disable(csr_io_dec_tlu_external_ldfwd_disable), + .io_dec_tlu_dma_qos_prty(csr_io_dec_tlu_dma_qos_prty), + .io_dec_illegal_inst(csr_io_dec_illegal_inst), + .io_lsu_error_pkt_r_bits_mscause(csr_io_lsu_error_pkt_r_bits_mscause), + .io_mexintpend(csr_io_mexintpend), + .io_exu_npc_r(csr_io_exu_npc_r), + .io_mpc_reset_run_req(csr_io_mpc_reset_run_req), + .io_rst_vec(csr_io_rst_vec), + .io_core_id(csr_io_core_id), + .io_dec_timer_rddata_d(csr_io_dec_timer_rddata_d), + .io_dec_timer_read_d(csr_io_dec_timer_read_d), + .io_dec_csr_wen_r_mod(csr_io_dec_csr_wen_r_mod), + .io_rfpc_i0_r(csr_io_rfpc_i0_r), + .io_i0_trigger_hit_r(csr_io_i0_trigger_hit_r), + .io_fw_halt_req(csr_io_fw_halt_req), + .io_mstatus(csr_io_mstatus), + .io_exc_or_int_valid_r(csr_io_exc_or_int_valid_r), + .io_mret_r(csr_io_mret_r), + .io_mstatus_mie_ns(csr_io_mstatus_mie_ns), + .io_dcsr_single_step_running_f(csr_io_dcsr_single_step_running_f), + .io_dcsr(csr_io_dcsr), + .io_mtvec(csr_io_mtvec), + .io_mip(csr_io_mip), + .io_dec_timer_t0_pulse(csr_io_dec_timer_t0_pulse), + .io_dec_timer_t1_pulse(csr_io_dec_timer_t1_pulse), + .io_timer_int_sync(csr_io_timer_int_sync), + .io_soft_int_sync(csr_io_soft_int_sync), + .io_mie_ns(csr_io_mie_ns), + .io_csr_wr_clk(csr_io_csr_wr_clk), + .io_ebreak_to_debug_mode_r(csr_io_ebreak_to_debug_mode_r), + .io_dec_tlu_pmu_fw_halted(csr_io_dec_tlu_pmu_fw_halted), + .io_lsu_fir_error(csr_io_lsu_fir_error), + .io_npc_r(csr_io_npc_r), + .io_tlu_flush_lower_r_d1(csr_io_tlu_flush_lower_r_d1), + .io_dec_tlu_flush_noredir_r_d1(csr_io_dec_tlu_flush_noredir_r_d1), + .io_tlu_flush_path_r_d1(csr_io_tlu_flush_path_r_d1), + .io_npc_r_d1(csr_io_npc_r_d1), + .io_reset_delayed(csr_io_reset_delayed), + .io_mepc(csr_io_mepc), + .io_interrupt_valid_r(csr_io_interrupt_valid_r), + .io_i0_exception_valid_r(csr_io_i0_exception_valid_r), + .io_lsu_exc_valid_r(csr_io_lsu_exc_valid_r), + .io_mepc_trigger_hit_sel_pc_r(csr_io_mepc_trigger_hit_sel_pc_r), + .io_e4e5_int_clk(csr_io_e4e5_int_clk), + .io_lsu_i0_exc_r(csr_io_lsu_i0_exc_r), + .io_inst_acc_r(csr_io_inst_acc_r), + .io_inst_acc_second_r(csr_io_inst_acc_second_r), + .io_take_nmi(csr_io_take_nmi), + .io_lsu_error_pkt_addr_r(csr_io_lsu_error_pkt_addr_r), + .io_exc_cause_r(csr_io_exc_cause_r), + .io_i0_valid_wb(csr_io_i0_valid_wb), + .io_exc_or_int_valid_r_d1(csr_io_exc_or_int_valid_r_d1), + .io_interrupt_valid_r_d1(csr_io_interrupt_valid_r_d1), + .io_clk_override(csr_io_clk_override), + .io_i0_exception_valid_r_d1(csr_io_i0_exception_valid_r_d1), + .io_lsu_i0_exc_r_d1(csr_io_lsu_i0_exc_r_d1), + .io_exc_cause_wb(csr_io_exc_cause_wb), + .io_nmi_lsu_store_type(csr_io_nmi_lsu_store_type), + .io_nmi_lsu_load_type(csr_io_nmi_lsu_load_type), + .io_tlu_i0_commit_cmt(csr_io_tlu_i0_commit_cmt), + .io_ebreak_r(csr_io_ebreak_r), + .io_ecall_r(csr_io_ecall_r), + .io_illegal_r(csr_io_illegal_r), + .io_mdseac_locked_ns(csr_io_mdseac_locked_ns), + .io_mdseac_locked_f(csr_io_mdseac_locked_f), + .io_nmi_int_detected_f(csr_io_nmi_int_detected_f), + .io_internal_dbg_halt_mode_f2(csr_io_internal_dbg_halt_mode_f2), + .io_ext_int_freeze_d1(csr_io_ext_int_freeze_d1), + .io_ic_perr_r_d1(csr_io_ic_perr_r_d1), + .io_iccm_sbecc_r_d1(csr_io_iccm_sbecc_r_d1), + .io_lsu_single_ecc_error_r_d1(csr_io_lsu_single_ecc_error_r_d1), + .io_ifu_miss_state_idle_f(csr_io_ifu_miss_state_idle_f), + .io_lsu_idle_any_f(csr_io_lsu_idle_any_f), + .io_dbg_tlu_halted_f(csr_io_dbg_tlu_halted_f), + .io_dbg_tlu_halted(csr_io_dbg_tlu_halted), + .io_debug_halt_req_f(csr_io_debug_halt_req_f), + .io_force_halt(csr_io_force_halt), + .io_take_ext_int_start(csr_io_take_ext_int_start), + .io_trigger_hit_dmode_r_d1(csr_io_trigger_hit_dmode_r_d1), + .io_trigger_hit_r_d1(csr_io_trigger_hit_r_d1), + .io_dcsr_single_step_done_f(csr_io_dcsr_single_step_done_f), + .io_ebreak_to_debug_mode_r_d1(csr_io_ebreak_to_debug_mode_r_d1), + .io_debug_halt_req(csr_io_debug_halt_req), + .io_allow_dbg_halt_csr_write(csr_io_allow_dbg_halt_csr_write), + .io_internal_dbg_halt_mode_f(csr_io_internal_dbg_halt_mode_f), + .io_enter_debug_halt_req(csr_io_enter_debug_halt_req), + .io_internal_dbg_halt_mode(csr_io_internal_dbg_halt_mode), + .io_request_debug_mode_done(csr_io_request_debug_mode_done), + .io_request_debug_mode_r(csr_io_request_debug_mode_r), + .io_dpc(csr_io_dpc), + .io_update_hit_bit_r(csr_io_update_hit_bit_r), + .io_take_timer_int(csr_io_take_timer_int), + .io_take_int_timer0_int(csr_io_take_int_timer0_int), + .io_take_int_timer1_int(csr_io_take_int_timer1_int), + .io_take_ext_int(csr_io_take_ext_int), + .io_tlu_flush_lower_r(csr_io_tlu_flush_lower_r), + .io_dec_tlu_br0_error_r(csr_io_dec_tlu_br0_error_r), + .io_dec_tlu_br0_start_error_r(csr_io_dec_tlu_br0_start_error_r), + .io_lsu_pmu_load_external_r(csr_io_lsu_pmu_load_external_r), + .io_lsu_pmu_store_external_r(csr_io_lsu_pmu_store_external_r), + .io_csr_pkt_csr_misa(csr_io_csr_pkt_csr_misa), + .io_csr_pkt_csr_mvendorid(csr_io_csr_pkt_csr_mvendorid), + .io_csr_pkt_csr_marchid(csr_io_csr_pkt_csr_marchid), + .io_csr_pkt_csr_mimpid(csr_io_csr_pkt_csr_mimpid), + .io_csr_pkt_csr_mhartid(csr_io_csr_pkt_csr_mhartid), + .io_csr_pkt_csr_mstatus(csr_io_csr_pkt_csr_mstatus), + .io_csr_pkt_csr_mtvec(csr_io_csr_pkt_csr_mtvec), + .io_csr_pkt_csr_mip(csr_io_csr_pkt_csr_mip), + .io_csr_pkt_csr_mie(csr_io_csr_pkt_csr_mie), + .io_csr_pkt_csr_mcyclel(csr_io_csr_pkt_csr_mcyclel), + .io_csr_pkt_csr_mcycleh(csr_io_csr_pkt_csr_mcycleh), + .io_csr_pkt_csr_minstretl(csr_io_csr_pkt_csr_minstretl), + .io_csr_pkt_csr_minstreth(csr_io_csr_pkt_csr_minstreth), + .io_csr_pkt_csr_mscratch(csr_io_csr_pkt_csr_mscratch), + .io_csr_pkt_csr_mepc(csr_io_csr_pkt_csr_mepc), + .io_csr_pkt_csr_mcause(csr_io_csr_pkt_csr_mcause), + .io_csr_pkt_csr_mscause(csr_io_csr_pkt_csr_mscause), + .io_csr_pkt_csr_mtval(csr_io_csr_pkt_csr_mtval), + .io_csr_pkt_csr_mrac(csr_io_csr_pkt_csr_mrac), + .io_csr_pkt_csr_mdseac(csr_io_csr_pkt_csr_mdseac), + .io_csr_pkt_csr_meihap(csr_io_csr_pkt_csr_meihap), + .io_csr_pkt_csr_meivt(csr_io_csr_pkt_csr_meivt), + .io_csr_pkt_csr_meipt(csr_io_csr_pkt_csr_meipt), + .io_csr_pkt_csr_meicurpl(csr_io_csr_pkt_csr_meicurpl), + .io_csr_pkt_csr_meicidpl(csr_io_csr_pkt_csr_meicidpl), + .io_csr_pkt_csr_dcsr(csr_io_csr_pkt_csr_dcsr), + .io_csr_pkt_csr_mcgc(csr_io_csr_pkt_csr_mcgc), + .io_csr_pkt_csr_mfdc(csr_io_csr_pkt_csr_mfdc), + .io_csr_pkt_csr_dpc(csr_io_csr_pkt_csr_dpc), + .io_csr_pkt_csr_mtsel(csr_io_csr_pkt_csr_mtsel), + .io_csr_pkt_csr_mtdata1(csr_io_csr_pkt_csr_mtdata1), + .io_csr_pkt_csr_mtdata2(csr_io_csr_pkt_csr_mtdata2), + .io_csr_pkt_csr_mhpmc3(csr_io_csr_pkt_csr_mhpmc3), + .io_csr_pkt_csr_mhpmc4(csr_io_csr_pkt_csr_mhpmc4), + .io_csr_pkt_csr_mhpmc5(csr_io_csr_pkt_csr_mhpmc5), + .io_csr_pkt_csr_mhpmc6(csr_io_csr_pkt_csr_mhpmc6), + .io_csr_pkt_csr_mhpmc3h(csr_io_csr_pkt_csr_mhpmc3h), + .io_csr_pkt_csr_mhpmc4h(csr_io_csr_pkt_csr_mhpmc4h), + .io_csr_pkt_csr_mhpmc5h(csr_io_csr_pkt_csr_mhpmc5h), + .io_csr_pkt_csr_mhpmc6h(csr_io_csr_pkt_csr_mhpmc6h), + .io_csr_pkt_csr_mhpme3(csr_io_csr_pkt_csr_mhpme3), + .io_csr_pkt_csr_mhpme4(csr_io_csr_pkt_csr_mhpme4), + .io_csr_pkt_csr_mhpme5(csr_io_csr_pkt_csr_mhpme5), + .io_csr_pkt_csr_mhpme6(csr_io_csr_pkt_csr_mhpme6), + .io_csr_pkt_csr_mcountinhibit(csr_io_csr_pkt_csr_mcountinhibit), + .io_csr_pkt_csr_mpmc(csr_io_csr_pkt_csr_mpmc), + .io_csr_pkt_csr_micect(csr_io_csr_pkt_csr_micect), + .io_csr_pkt_csr_miccmect(csr_io_csr_pkt_csr_miccmect), + .io_csr_pkt_csr_mdccmect(csr_io_csr_pkt_csr_mdccmect), + .io_csr_pkt_csr_mfdht(csr_io_csr_pkt_csr_mfdht), + .io_csr_pkt_csr_mfdhs(csr_io_csr_pkt_csr_mfdhs), + .io_csr_pkt_csr_dicawics(csr_io_csr_pkt_csr_dicawics), + .io_csr_pkt_csr_dicad0h(csr_io_csr_pkt_csr_dicad0h), + .io_csr_pkt_csr_dicad0(csr_io_csr_pkt_csr_dicad0), + .io_csr_pkt_csr_dicad1(csr_io_csr_pkt_csr_dicad1), + .io_mtdata1_t_0(csr_io_mtdata1_t_0), + .io_mtdata1_t_1(csr_io_mtdata1_t_1), + .io_mtdata1_t_2(csr_io_mtdata1_t_2), + .io_mtdata1_t_3(csr_io_mtdata1_t_3) + ); + el2_dec_decode_csr_read csr_read ( // @[el2_dec_tlu_ctl.scala 1090:22] + .io_dec_csr_rdaddr_d(csr_read_io_dec_csr_rdaddr_d), + .io_csr_pkt_csr_misa(csr_read_io_csr_pkt_csr_misa), + .io_csr_pkt_csr_mvendorid(csr_read_io_csr_pkt_csr_mvendorid), + .io_csr_pkt_csr_marchid(csr_read_io_csr_pkt_csr_marchid), + .io_csr_pkt_csr_mimpid(csr_read_io_csr_pkt_csr_mimpid), + .io_csr_pkt_csr_mhartid(csr_read_io_csr_pkt_csr_mhartid), + .io_csr_pkt_csr_mstatus(csr_read_io_csr_pkt_csr_mstatus), + .io_csr_pkt_csr_mtvec(csr_read_io_csr_pkt_csr_mtvec), + .io_csr_pkt_csr_mip(csr_read_io_csr_pkt_csr_mip), + .io_csr_pkt_csr_mie(csr_read_io_csr_pkt_csr_mie), + .io_csr_pkt_csr_mcyclel(csr_read_io_csr_pkt_csr_mcyclel), + .io_csr_pkt_csr_mcycleh(csr_read_io_csr_pkt_csr_mcycleh), + .io_csr_pkt_csr_minstretl(csr_read_io_csr_pkt_csr_minstretl), + .io_csr_pkt_csr_minstreth(csr_read_io_csr_pkt_csr_minstreth), + .io_csr_pkt_csr_mscratch(csr_read_io_csr_pkt_csr_mscratch), + .io_csr_pkt_csr_mepc(csr_read_io_csr_pkt_csr_mepc), + .io_csr_pkt_csr_mcause(csr_read_io_csr_pkt_csr_mcause), + .io_csr_pkt_csr_mscause(csr_read_io_csr_pkt_csr_mscause), + .io_csr_pkt_csr_mtval(csr_read_io_csr_pkt_csr_mtval), + .io_csr_pkt_csr_mrac(csr_read_io_csr_pkt_csr_mrac), + .io_csr_pkt_csr_dmst(csr_read_io_csr_pkt_csr_dmst), + .io_csr_pkt_csr_mdseac(csr_read_io_csr_pkt_csr_mdseac), + .io_csr_pkt_csr_meihap(csr_read_io_csr_pkt_csr_meihap), + .io_csr_pkt_csr_meivt(csr_read_io_csr_pkt_csr_meivt), + .io_csr_pkt_csr_meipt(csr_read_io_csr_pkt_csr_meipt), + .io_csr_pkt_csr_meicurpl(csr_read_io_csr_pkt_csr_meicurpl), + .io_csr_pkt_csr_meicidpl(csr_read_io_csr_pkt_csr_meicidpl), + .io_csr_pkt_csr_dcsr(csr_read_io_csr_pkt_csr_dcsr), + .io_csr_pkt_csr_mcgc(csr_read_io_csr_pkt_csr_mcgc), + .io_csr_pkt_csr_mfdc(csr_read_io_csr_pkt_csr_mfdc), + .io_csr_pkt_csr_dpc(csr_read_io_csr_pkt_csr_dpc), + .io_csr_pkt_csr_mtsel(csr_read_io_csr_pkt_csr_mtsel), + .io_csr_pkt_csr_mtdata1(csr_read_io_csr_pkt_csr_mtdata1), + .io_csr_pkt_csr_mtdata2(csr_read_io_csr_pkt_csr_mtdata2), + .io_csr_pkt_csr_mhpmc3(csr_read_io_csr_pkt_csr_mhpmc3), + .io_csr_pkt_csr_mhpmc4(csr_read_io_csr_pkt_csr_mhpmc4), + .io_csr_pkt_csr_mhpmc5(csr_read_io_csr_pkt_csr_mhpmc5), + .io_csr_pkt_csr_mhpmc6(csr_read_io_csr_pkt_csr_mhpmc6), + .io_csr_pkt_csr_mhpmc3h(csr_read_io_csr_pkt_csr_mhpmc3h), + .io_csr_pkt_csr_mhpmc4h(csr_read_io_csr_pkt_csr_mhpmc4h), + .io_csr_pkt_csr_mhpmc5h(csr_read_io_csr_pkt_csr_mhpmc5h), + .io_csr_pkt_csr_mhpmc6h(csr_read_io_csr_pkt_csr_mhpmc6h), + .io_csr_pkt_csr_mhpme3(csr_read_io_csr_pkt_csr_mhpme3), + .io_csr_pkt_csr_mhpme4(csr_read_io_csr_pkt_csr_mhpme4), + .io_csr_pkt_csr_mhpme5(csr_read_io_csr_pkt_csr_mhpme5), + .io_csr_pkt_csr_mhpme6(csr_read_io_csr_pkt_csr_mhpme6), + .io_csr_pkt_csr_mcountinhibit(csr_read_io_csr_pkt_csr_mcountinhibit), + .io_csr_pkt_csr_mitctl0(csr_read_io_csr_pkt_csr_mitctl0), + .io_csr_pkt_csr_mitctl1(csr_read_io_csr_pkt_csr_mitctl1), + .io_csr_pkt_csr_mitb0(csr_read_io_csr_pkt_csr_mitb0), + .io_csr_pkt_csr_mitb1(csr_read_io_csr_pkt_csr_mitb1), + .io_csr_pkt_csr_mitcnt0(csr_read_io_csr_pkt_csr_mitcnt0), + .io_csr_pkt_csr_mitcnt1(csr_read_io_csr_pkt_csr_mitcnt1), + .io_csr_pkt_csr_mpmc(csr_read_io_csr_pkt_csr_mpmc), + .io_csr_pkt_csr_meicpct(csr_read_io_csr_pkt_csr_meicpct), + .io_csr_pkt_csr_micect(csr_read_io_csr_pkt_csr_micect), + .io_csr_pkt_csr_miccmect(csr_read_io_csr_pkt_csr_miccmect), + .io_csr_pkt_csr_mdccmect(csr_read_io_csr_pkt_csr_mdccmect), + .io_csr_pkt_csr_mfdht(csr_read_io_csr_pkt_csr_mfdht), + .io_csr_pkt_csr_mfdhs(csr_read_io_csr_pkt_csr_mfdhs), + .io_csr_pkt_csr_dicawics(csr_read_io_csr_pkt_csr_dicawics), + .io_csr_pkt_csr_dicad0h(csr_read_io_csr_pkt_csr_dicad0h), + .io_csr_pkt_csr_dicad0(csr_read_io_csr_pkt_csr_dicad0), + .io_csr_pkt_csr_dicad1(csr_read_io_csr_pkt_csr_dicad1), + .io_csr_pkt_csr_dicago(csr_read_io_csr_pkt_csr_dicago), + .io_csr_pkt_presync(csr_read_io_csr_pkt_presync), + .io_csr_pkt_postsync(csr_read_io_csr_pkt_postsync), + .io_csr_pkt_legal(csr_read_io_csr_pkt_legal) + ); + assign io_dec_dbg_cmd_done = io_dec_tlu_i0_valid_r & io_dec_tlu_dbg_halted; // @[el2_dec_tlu_ctl.scala 568:23] + assign io_dec_dbg_cmd_fail = illegal_r & io_dec_dbg_cmd_done; // @[el2_dec_tlu_ctl.scala 569:23] + assign io_dec_tlu_dbg_halted = dbg_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 550:41] + assign io_dec_tlu_debug_mode = debug_mode_status; // @[el2_dec_tlu_ctl.scala 551:41] + assign io_dec_tlu_resume_ack = _T_190; // @[el2_dec_tlu_ctl.scala 534:41] + assign io_dec_tlu_debug_stall = debug_halt_req_f; // @[el2_dec_tlu_ctl.scala 549:41] + assign io_dec_tlu_flush_noredir_r = _T_205 | take_ext_int_start; // @[el2_dec_tlu_ctl.scala 555:30] + assign io_dec_tlu_mpc_halted_only = _T_65; // @[el2_dec_tlu_ctl.scala 449:41] + assign io_dec_tlu_flush_leak_one_r = _T_233 & _T_234; // @[el2_dec_tlu_ctl.scala 564:31] + assign io_dec_tlu_flush_err_r = io_dec_tlu_flush_lower_r & _T_433; // @[el2_dec_tlu_ctl.scala 565:26] + assign io_dec_tlu_flush_extint = ext_int_ready & _T_704; // @[el2_dec_tlu_ctl.scala 557:27] + assign io_dec_tlu_meihap = csr_io_dec_tlu_meihap; // @[el2_dec_tlu_ctl.scala 956:44] + assign io_trigger_pkt_any_0_select = csr_io_trigger_pkt_any_0_select; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_0_match_pkt = csr_io_trigger_pkt_any_0_match_pkt; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_0_store = csr_io_trigger_pkt_any_0_store; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_0_load = csr_io_trigger_pkt_any_0_load; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_0_execute = csr_io_trigger_pkt_any_0_execute; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_0_m = csr_io_trigger_pkt_any_0_m; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_0_tdata2 = csr_io_trigger_pkt_any_0_tdata2; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_1_select = csr_io_trigger_pkt_any_1_select; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_1_match_pkt = csr_io_trigger_pkt_any_1_match_pkt; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_1_store = csr_io_trigger_pkt_any_1_store; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_1_load = csr_io_trigger_pkt_any_1_load; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_1_execute = csr_io_trigger_pkt_any_1_execute; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_1_m = csr_io_trigger_pkt_any_1_m; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_1_tdata2 = csr_io_trigger_pkt_any_1_tdata2; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_2_select = csr_io_trigger_pkt_any_2_select; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_2_match_pkt = csr_io_trigger_pkt_any_2_match_pkt; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_2_store = csr_io_trigger_pkt_any_2_store; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_2_load = csr_io_trigger_pkt_any_2_load; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_2_execute = csr_io_trigger_pkt_any_2_execute; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_2_m = csr_io_trigger_pkt_any_2_m; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_2_tdata2 = csr_io_trigger_pkt_any_2_tdata2; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_3_select = csr_io_trigger_pkt_any_3_select; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_3_match_pkt = csr_io_trigger_pkt_any_3_match_pkt; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_3_store = csr_io_trigger_pkt_any_3_store; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_3_load = csr_io_trigger_pkt_any_3_load; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_3_execute = csr_io_trigger_pkt_any_3_execute; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_3_m = csr_io_trigger_pkt_any_3_m; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_3_tdata2 = csr_io_trigger_pkt_any_3_tdata2; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_dec_tlu_ic_diag_pkt_icache_wrdata = csr_io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[el2_dec_tlu_ctl.scala 961:44] + assign io_dec_tlu_ic_diag_pkt_icache_dicawics = csr_io_dec_tlu_ic_diag_pkt_icache_dicawics; // @[el2_dec_tlu_ctl.scala 961:44] + assign io_dec_tlu_ic_diag_pkt_icache_rd_valid = csr_io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[el2_dec_tlu_ctl.scala 961:44] + assign io_dec_tlu_ic_diag_pkt_icache_wr_valid = csr_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[el2_dec_tlu_ctl.scala 961:44] + assign io_o_cpu_halt_status = _T_353; // @[el2_dec_tlu_ctl.scala 654:41] + assign io_o_cpu_halt_ack = _T_354; // @[el2_dec_tlu_ctl.scala 655:49] + assign io_o_cpu_run_ack = _T_355; // @[el2_dec_tlu_ctl.scala 656:49] + assign io_o_debug_mode_status = debug_mode_status; // @[el2_dec_tlu_ctl.scala 677:26] + assign io_mpc_debug_halt_ack = mpc_debug_halt_ack_f; // @[el2_dec_tlu_ctl.scala 474:25] + assign io_mpc_debug_run_ack = mpc_debug_run_ack_f; // @[el2_dec_tlu_ctl.scala 475:25] + assign io_debug_brkpt_status = debug_brkpt_status_f; // @[el2_dec_tlu_ctl.scala 476:25] + assign io_dec_tlu_meicurpl = csr_io_dec_tlu_meicurpl; // @[el2_dec_tlu_ctl.scala 955:44] + assign io_dec_tlu_meipt = csr_io_dec_tlu_meipt; // @[el2_dec_tlu_ctl.scala 957:44] + assign io_dec_csr_rddata_d = csr_io_dec_csr_rddata_d; // @[el2_dec_tlu_ctl.scala 977:40] + assign io_dec_csr_legal_d = _T_887 & _T_894; // @[el2_dec_tlu_ctl.scala 1101:22] + assign io_dec_tlu_br0_r_pkt_valid = _T_459 & _T_462; // @[el2_dec_tlu_ctl.scala 733:49] + assign io_dec_tlu_br0_r_pkt_bits_hist = io_exu_i0_br_hist_r; // @[el2_dec_tlu_ctl.scala 730:57] + assign io_dec_tlu_br0_r_pkt_bits_br_error = _T_453 & _T_429; // @[el2_dec_tlu_ctl.scala 731:49] + assign io_dec_tlu_br0_r_pkt_bits_br_start_error = _T_455 & _T_429; // @[el2_dec_tlu_ctl.scala 732:49] + assign io_dec_tlu_br0_r_pkt_bits_way = io_exu_i0_br_way_r; // @[el2_dec_tlu_ctl.scala 734:57] + assign io_dec_tlu_br0_r_pkt_bits_middle = io_exu_i0_br_middle_r; // @[el2_dec_tlu_ctl.scala 735:57] + assign io_dec_tlu_i0_kill_writeb_wb = _T_32; // @[el2_dec_tlu_ctl.scala 409:33] + assign io_dec_tlu_flush_lower_wb = tlu_flush_lower_r_d1; // @[el2_dec_tlu_ctl.scala 881:33] + assign io_dec_tlu_i0_commit_cmt = _T_422 & _T_465; // @[el2_dec_tlu_ctl.scala 708:28] + assign io_dec_tlu_i0_kill_writeb_r = _T_427 | i0_trigger_hit_raw_r; // @[el2_dec_tlu_ctl.scala 415:33] + assign io_dec_tlu_flush_lower_r = _T_801 | take_ext_int_start; // @[el2_dec_tlu_ctl.scala 882:33] + assign io_dec_tlu_flush_path_r = take_reset ? io_rst_vec : _T_852; // @[el2_dec_tlu_ctl.scala 883:33] + assign io_dec_tlu_fence_i_r = _T_492 & _T_470; // @[el2_dec_tlu_ctl.scala 753:24] + assign io_dec_tlu_wr_pause_r = csr_io_dec_tlu_wr_pause_r; // @[el2_dec_tlu_ctl.scala 979:40] + assign io_dec_tlu_flush_pause_r = _T_208 & _T_209; // @[el2_dec_tlu_ctl.scala 560:28] + assign io_dec_tlu_presync_d = _T_864 & _T_865; // @[el2_dec_tlu_ctl.scala 1094:25] + assign io_dec_tlu_postsync_d = csr_pkt_postsync & io_dec_csr_any_unq_d; // @[el2_dec_tlu_ctl.scala 1095:25] + assign io_dec_tlu_mrac_ff = csr_io_dec_tlu_mrac_ff; // @[el2_dec_tlu_ctl.scala 980:40] + assign io_dec_tlu_force_halt = _T_33; // @[el2_dec_tlu_ctl.scala 411:41] + assign io_dec_tlu_perfcnt0 = csr_io_dec_tlu_perfcnt0; // @[el2_dec_tlu_ctl.scala 965:40] + assign io_dec_tlu_perfcnt1 = csr_io_dec_tlu_perfcnt1; // @[el2_dec_tlu_ctl.scala 966:40] + assign io_dec_tlu_perfcnt2 = csr_io_dec_tlu_perfcnt2; // @[el2_dec_tlu_ctl.scala 967:40] + assign io_dec_tlu_perfcnt3 = csr_io_dec_tlu_perfcnt3; // @[el2_dec_tlu_ctl.scala 968:40] + assign io_dec_tlu_i0_exc_valid_wb1 = csr_io_dec_tlu_i0_exc_valid_wb1; // @[el2_dec_tlu_ctl.scala 959:44] + assign io_dec_tlu_i0_valid_wb1 = csr_io_dec_tlu_i0_valid_wb1; // @[el2_dec_tlu_ctl.scala 960:44] + assign io_dec_tlu_int_valid_wb1 = csr_io_dec_tlu_int_valid_wb1; // @[el2_dec_tlu_ctl.scala 958:44] + assign io_dec_tlu_exc_cause_wb1 = csr_io_dec_tlu_exc_cause_wb1; // @[el2_dec_tlu_ctl.scala 964:40] + assign io_dec_tlu_mtval_wb1 = csr_io_dec_tlu_mtval_wb1; // @[el2_dec_tlu_ctl.scala 963:40] + assign io_dec_tlu_external_ldfwd_disable = csr_io_dec_tlu_external_ldfwd_disable; // @[el2_dec_tlu_ctl.scala 985:40] + assign io_dec_tlu_sideeffect_posted_disable = csr_io_dec_tlu_sideeffect_posted_disable; // @[el2_dec_tlu_ctl.scala 983:40] + assign io_dec_tlu_core_ecc_disable = csr_io_dec_tlu_core_ecc_disable; // @[el2_dec_tlu_ctl.scala 984:40] + assign io_dec_tlu_bpred_disable = csr_io_dec_tlu_bpred_disable; // @[el2_dec_tlu_ctl.scala 982:40] + assign io_dec_tlu_wb_coalescing_disable = csr_io_dec_tlu_wb_coalescing_disable; // @[el2_dec_tlu_ctl.scala 981:40] + assign io_dec_tlu_pipelining_disable = csr_io_dec_tlu_pipelining_disable; // @[el2_dec_tlu_ctl.scala 978:40] + assign io_dec_tlu_dma_qos_prty = csr_io_dec_tlu_dma_qos_prty; // @[el2_dec_tlu_ctl.scala 986:40] + assign io_dec_tlu_misc_clk_override = csr_io_dec_tlu_misc_clk_override; // @[el2_dec_tlu_ctl.scala 969:40] + assign io_dec_tlu_dec_clk_override = csr_io_dec_tlu_dec_clk_override; // @[el2_dec_tlu_ctl.scala 970:40] + assign io_dec_tlu_ifu_clk_override = csr_io_dec_tlu_ifu_clk_override; // @[el2_dec_tlu_ctl.scala 971:40] + assign io_dec_tlu_lsu_clk_override = csr_io_dec_tlu_lsu_clk_override; // @[el2_dec_tlu_ctl.scala 972:40] + assign io_dec_tlu_bus_clk_override = csr_io_dec_tlu_bus_clk_override; // @[el2_dec_tlu_ctl.scala 973:40] + assign io_dec_tlu_pic_clk_override = csr_io_dec_tlu_pic_clk_override; // @[el2_dec_tlu_ctl.scala 974:40] + assign io_dec_tlu_dccm_clk_override = csr_io_dec_tlu_dccm_clk_override; // @[el2_dec_tlu_ctl.scala 975:40] + assign io_dec_tlu_icm_clk_override = csr_io_dec_tlu_icm_clk_override; // @[el2_dec_tlu_ctl.scala 976:40] + assign int_timers_clock = clock; + assign int_timers_reset = reset; + assign int_timers_io_free_clk = io_free_clk; // @[el2_dec_tlu_ctl.scala 356:57] + assign int_timers_io_scan_mode = io_scan_mode; // @[el2_dec_tlu_ctl.scala 357:57] + assign int_timers_io_dec_csr_wen_r_mod = csr_io_dec_csr_wen_r_mod; // @[el2_dec_tlu_ctl.scala 358:49] + assign int_timers_io_dec_csr_wraddr_r = io_dec_csr_wraddr_r; // @[el2_dec_tlu_ctl.scala 360:49] + assign int_timers_io_dec_csr_wrdata_r = io_dec_csr_wrdata_r; // @[el2_dec_tlu_ctl.scala 361:49] + assign int_timers_io_csr_mitctl0 = csr_read_io_csr_pkt_csr_mitctl0; // @[el2_dec_tlu_ctl.scala 362:49] + assign int_timers_io_csr_mitctl1 = csr_read_io_csr_pkt_csr_mitctl1; // @[el2_dec_tlu_ctl.scala 363:49] + assign int_timers_io_csr_mitb0 = csr_read_io_csr_pkt_csr_mitb0; // @[el2_dec_tlu_ctl.scala 364:57] + assign int_timers_io_csr_mitb1 = csr_read_io_csr_pkt_csr_mitb1; // @[el2_dec_tlu_ctl.scala 365:57] + assign int_timers_io_csr_mitcnt0 = csr_read_io_csr_pkt_csr_mitcnt0; // @[el2_dec_tlu_ctl.scala 366:49] + assign int_timers_io_csr_mitcnt1 = csr_read_io_csr_pkt_csr_mitcnt1; // @[el2_dec_tlu_ctl.scala 367:49] + assign int_timers_io_dec_pause_state = io_dec_pause_state; // @[el2_dec_tlu_ctl.scala 368:41] + assign int_timers_io_dec_tlu_pmu_fw_halted = pmu_fw_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 369:41] + assign int_timers_io_internal_dbg_halt_timers = debug_mode_status & _T_665; // @[el2_dec_tlu_ctl.scala 370:41] + assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_io_en = dec_csr_wen_r_mod | io_dec_tlu_dec_clk_override; // @[el2_lib.scala 485:16] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_1_io_en = _T_11 | io_dec_tlu_dec_clk_override; // @[el2_lib.scala 485:16] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_2_io_en = e4e5_valid | io_dec_tlu_dec_clk_override; // @[el2_lib.scala 485:16] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_3_io_en = e4e5_valid | flush_clkvalid; // @[el2_lib.scala 485:16] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign csr_clock = clock; + assign csr_reset = reset; + assign csr_io_free_clk = io_free_clk; // @[el2_dec_tlu_ctl.scala 898:44] + assign csr_io_active_clk = io_active_clk; // @[el2_dec_tlu_ctl.scala 899:44] + assign csr_io_scan_mode = io_scan_mode; // @[el2_dec_tlu_ctl.scala 900:44] + assign csr_io_dec_csr_wrdata_r = io_dec_csr_wrdata_r; // @[el2_dec_tlu_ctl.scala 901:44] + assign csr_io_dec_csr_wraddr_r = io_dec_csr_wraddr_r; // @[el2_dec_tlu_ctl.scala 902:44] + assign csr_io_dec_csr_rdaddr_d = io_dec_csr_rdaddr_d; // @[el2_dec_tlu_ctl.scala 903:44] + assign csr_io_dec_csr_wen_unq_d = io_dec_csr_wen_unq_d; // @[el2_dec_tlu_ctl.scala 904:44] + assign csr_io_dec_i0_decode_d = io_dec_i0_decode_d; // @[el2_dec_tlu_ctl.scala 905:44] + assign csr_io_ifu_ic_debug_rd_data_valid = io_ifu_ic_debug_rd_data_valid; // @[el2_dec_tlu_ctl.scala 906:44] + assign csr_io_ifu_pmu_bus_trxn = io_ifu_pmu_bus_trxn; // @[el2_dec_tlu_ctl.scala 907:44] + assign csr_io_dma_iccm_stall_any = io_dma_iccm_stall_any; // @[el2_dec_tlu_ctl.scala 908:44] + assign csr_io_dma_dccm_stall_any = io_dma_dccm_stall_any; // @[el2_dec_tlu_ctl.scala 909:44] + assign csr_io_lsu_store_stall_any = io_lsu_store_stall_any; // @[el2_dec_tlu_ctl.scala 910:44] + assign csr_io_dec_pmu_presync_stall = io_dec_pmu_presync_stall; // @[el2_dec_tlu_ctl.scala 911:44] + assign csr_io_dec_pmu_postsync_stall = io_dec_pmu_postsync_stall; // @[el2_dec_tlu_ctl.scala 912:44] + assign csr_io_dec_pmu_decode_stall = io_dec_pmu_decode_stall; // @[el2_dec_tlu_ctl.scala 913:44] + assign csr_io_ifu_pmu_fetch_stall = io_ifu_pmu_fetch_stall; // @[el2_dec_tlu_ctl.scala 914:44] + assign csr_io_dec_tlu_packet_r_icaf_type = io_dec_tlu_packet_r_icaf_type; // @[el2_dec_tlu_ctl.scala 915:44] + assign csr_io_dec_tlu_packet_r_pmu_i0_itype = io_dec_tlu_packet_r_pmu_i0_itype; // @[el2_dec_tlu_ctl.scala 915:44] + assign csr_io_dec_tlu_packet_r_pmu_i0_br_unpred = io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[el2_dec_tlu_ctl.scala 915:44] + assign csr_io_dec_tlu_packet_r_pmu_divide = io_dec_tlu_packet_r_pmu_divide; // @[el2_dec_tlu_ctl.scala 915:44] + assign csr_io_dec_tlu_packet_r_pmu_lsu_misaligned = io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[el2_dec_tlu_ctl.scala 915:44] + assign csr_io_exu_pmu_i0_br_ataken = io_exu_pmu_i0_br_ataken; // @[el2_dec_tlu_ctl.scala 916:44] + assign csr_io_exu_pmu_i0_br_misp = io_exu_pmu_i0_br_misp; // @[el2_dec_tlu_ctl.scala 917:44] + assign csr_io_dec_pmu_instr_decoded = io_dec_pmu_instr_decoded; // @[el2_dec_tlu_ctl.scala 918:44] + assign csr_io_ifu_pmu_instr_aligned = io_ifu_pmu_instr_aligned; // @[el2_dec_tlu_ctl.scala 919:44] + assign csr_io_exu_pmu_i0_pc4 = io_exu_pmu_i0_pc4; // @[el2_dec_tlu_ctl.scala 920:44] + assign csr_io_ifu_pmu_ic_miss = io_ifu_pmu_ic_miss; // @[el2_dec_tlu_ctl.scala 921:44] + assign csr_io_ifu_pmu_ic_hit = io_ifu_pmu_ic_hit; // @[el2_dec_tlu_ctl.scala 922:44] + assign csr_io_dec_csr_wen_r = io_dec_csr_wen_r; // @[el2_dec_tlu_ctl.scala 923:44] + assign csr_io_dec_tlu_dbg_halted = io_dec_tlu_dbg_halted; // @[el2_dec_tlu_ctl.scala 924:44] + assign csr_io_dma_pmu_dccm_write = io_dma_pmu_dccm_write; // @[el2_dec_tlu_ctl.scala 925:44] + assign csr_io_dma_pmu_dccm_read = io_dma_pmu_dccm_read; // @[el2_dec_tlu_ctl.scala 926:44] + assign csr_io_dma_pmu_any_write = io_dma_pmu_any_write; // @[el2_dec_tlu_ctl.scala 927:44] + assign csr_io_dma_pmu_any_read = io_dma_pmu_any_read; // @[el2_dec_tlu_ctl.scala 928:44] + assign csr_io_lsu_pmu_bus_busy = io_lsu_pmu_bus_busy; // @[el2_dec_tlu_ctl.scala 929:44] + assign csr_io_dec_tlu_i0_pc_r = io_dec_tlu_i0_pc_r; // @[el2_dec_tlu_ctl.scala 930:44] + assign csr_io_dec_tlu_i0_valid_r = io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 931:44] + assign csr_io_dec_csr_any_unq_d = io_dec_csr_any_unq_d; // @[el2_dec_tlu_ctl.scala 933:44] + assign csr_io_ifu_pmu_bus_busy = io_ifu_pmu_bus_busy; // @[el2_dec_tlu_ctl.scala 934:44] + assign csr_io_lsu_pmu_bus_error = io_lsu_pmu_bus_error; // @[el2_dec_tlu_ctl.scala 935:44] + assign csr_io_ifu_pmu_bus_error = io_ifu_pmu_bus_error; // @[el2_dec_tlu_ctl.scala 936:44] + assign csr_io_lsu_pmu_bus_misaligned = io_lsu_pmu_bus_misaligned; // @[el2_dec_tlu_ctl.scala 937:44] + assign csr_io_lsu_pmu_bus_trxn = io_lsu_pmu_bus_trxn; // @[el2_dec_tlu_ctl.scala 938:44] + assign csr_io_ifu_ic_debug_rd_data = io_ifu_ic_debug_rd_data; // @[el2_dec_tlu_ctl.scala 939:44] + assign csr_io_pic_pl = io_pic_pl; // @[el2_dec_tlu_ctl.scala 940:44] + assign csr_io_pic_claimid = io_pic_claimid; // @[el2_dec_tlu_ctl.scala 941:44] + assign csr_io_iccm_dma_sb_error = io_iccm_dma_sb_error; // @[el2_dec_tlu_ctl.scala 942:44] + assign csr_io_lsu_imprecise_error_addr_any = io_lsu_imprecise_error_addr_any; // @[el2_dec_tlu_ctl.scala 943:44] + assign csr_io_lsu_imprecise_error_load_any = io_lsu_imprecise_error_load_any; // @[el2_dec_tlu_ctl.scala 944:44] + assign csr_io_lsu_imprecise_error_store_any = io_lsu_imprecise_error_store_any; // @[el2_dec_tlu_ctl.scala 945:44] + assign csr_io_dec_illegal_inst = io_dec_illegal_inst; // @[el2_dec_tlu_ctl.scala 946:44 el2_dec_tlu_ctl.scala 987:44] + assign csr_io_lsu_error_pkt_r_bits_mscause = io_lsu_error_pkt_r_bits_mscause; // @[el2_dec_tlu_ctl.scala 947:44 el2_dec_tlu_ctl.scala 988:44] + assign csr_io_mexintpend = io_mexintpend; // @[el2_dec_tlu_ctl.scala 948:44 el2_dec_tlu_ctl.scala 989:44] + assign csr_io_exu_npc_r = io_exu_npc_r; // @[el2_dec_tlu_ctl.scala 949:44 el2_dec_tlu_ctl.scala 990:44] + assign csr_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[el2_dec_tlu_ctl.scala 950:44 el2_dec_tlu_ctl.scala 991:44] + assign csr_io_rst_vec = io_rst_vec; // @[el2_dec_tlu_ctl.scala 951:44 el2_dec_tlu_ctl.scala 992:44] + assign csr_io_core_id = io_core_id; // @[el2_dec_tlu_ctl.scala 952:44 el2_dec_tlu_ctl.scala 993:44] + assign csr_io_dec_timer_rddata_d = int_timers_io_dec_timer_rddata_d; // @[el2_dec_tlu_ctl.scala 953:44 el2_dec_tlu_ctl.scala 994:44] + assign csr_io_dec_timer_read_d = int_timers_io_dec_timer_read_d; // @[el2_dec_tlu_ctl.scala 954:44 el2_dec_tlu_ctl.scala 995:44] + assign csr_io_rfpc_i0_r = _T_438 & _T_439; // @[el2_dec_tlu_ctl.scala 998:39] + assign csr_io_i0_trigger_hit_r = |i0_trigger_chain_masked_r; // @[el2_dec_tlu_ctl.scala 999:39] + assign csr_io_exc_or_int_valid_r = _T_855 | mepc_trigger_hit_sel_pc_r; // @[el2_dec_tlu_ctl.scala 1000:39] + assign csr_io_mret_r = _T_487 & _T_470; // @[el2_dec_tlu_ctl.scala 1001:39] + assign csr_io_dcsr_single_step_running_f = dcsr_single_step_running_f; // @[el2_dec_tlu_ctl.scala 1002:39] + assign csr_io_dec_timer_t0_pulse = int_timers_io_dec_timer_t0_pulse; // @[el2_dec_tlu_ctl.scala 1003:39] + assign csr_io_dec_timer_t1_pulse = int_timers_io_dec_timer_t1_pulse; // @[el2_dec_tlu_ctl.scala 1004:39] + assign csr_io_timer_int_sync = syncro_ff[5]; // @[el2_dec_tlu_ctl.scala 1005:39] + assign csr_io_soft_int_sync = syncro_ff[4]; // @[el2_dec_tlu_ctl.scala 1006:39] + assign csr_io_csr_wr_clk = rvclkhdr_io_l1clk; // @[el2_dec_tlu_ctl.scala 1007:39] + assign csr_io_ebreak_to_debug_mode_r = _T_519 & _T_470; // @[el2_dec_tlu_ctl.scala 1008:39] + assign csr_io_dec_tlu_pmu_fw_halted = pmu_fw_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 1009:39] + assign csr_io_lsu_fir_error = io_lsu_fir_error; // @[el2_dec_tlu_ctl.scala 1010:39] + assign csr_io_tlu_flush_lower_r_d1 = tlu_flush_lower_r_d1; // @[el2_dec_tlu_ctl.scala 1011:39] + assign csr_io_dec_tlu_flush_noredir_r_d1 = dec_tlu_flush_noredir_r_d1; // @[el2_dec_tlu_ctl.scala 1012:39] + assign csr_io_tlu_flush_path_r_d1 = tlu_flush_path_r_d1; // @[el2_dec_tlu_ctl.scala 1013:39] + assign csr_io_reset_delayed = reset_detect ^ reset_detected; // @[el2_dec_tlu_ctl.scala 1014:39] + assign csr_io_interrupt_valid_r = _T_766 | take_int_timer1_int; // @[el2_dec_tlu_ctl.scala 1015:39] + assign csr_io_i0_exception_valid_r = _T_527 & _T_528; // @[el2_dec_tlu_ctl.scala 1016:39] + assign csr_io_lsu_exc_valid_r = _T_405 & _T_470; // @[el2_dec_tlu_ctl.scala 1017:39] + assign csr_io_mepc_trigger_hit_sel_pc_r = i0_trigger_hit_raw_r & _T_345; // @[el2_dec_tlu_ctl.scala 1018:39] + assign csr_io_e4e5_int_clk = rvclkhdr_3_io_l1clk; // @[el2_dec_tlu_ctl.scala 1019:39] + assign csr_io_lsu_i0_exc_r = _T_405 & _T_470; // @[el2_dec_tlu_ctl.scala 1020:39] + assign csr_io_inst_acc_r = _T_511 & _T_465; // @[el2_dec_tlu_ctl.scala 1021:39] + assign csr_io_inst_acc_second_r = io_dec_tlu_packet_r_icaf_f1; // @[el2_dec_tlu_ctl.scala 1022:39] + assign csr_io_take_nmi = _T_756 & _T_760; // @[el2_dec_tlu_ctl.scala 1023:39] + assign csr_io_lsu_error_pkt_addr_r = io_lsu_error_pkt_r_bits_addr; // @[el2_dec_tlu_ctl.scala 1024:39] + assign csr_io_exc_cause_r = _T_603 | _T_591; // @[el2_dec_tlu_ctl.scala 1025:39] + assign csr_io_i0_valid_wb = i0_valid_wb; // @[el2_dec_tlu_ctl.scala 1026:39] + assign csr_io_exc_or_int_valid_r_d1 = exc_or_int_valid_r_d1; // @[el2_dec_tlu_ctl.scala 1027:39] + assign csr_io_interrupt_valid_r_d1 = interrupt_valid_r_d1; // @[el2_dec_tlu_ctl.scala 1028:39] + assign csr_io_clk_override = io_dec_tlu_dec_clk_override; // @[el2_dec_tlu_ctl.scala 1029:39] + assign csr_io_i0_exception_valid_r_d1 = i0_exception_valid_r_d1; // @[el2_dec_tlu_ctl.scala 1030:39] + assign csr_io_lsu_i0_exc_r_d1 = lsu_i0_exc_r_d1; // @[el2_dec_tlu_ctl.scala 1031:39] + assign csr_io_exc_cause_wb = exc_cause_wb; // @[el2_dec_tlu_ctl.scala 1032:39] + assign csr_io_nmi_lsu_store_type = _T_58 | _T_60; // @[el2_dec_tlu_ctl.scala 1033:39] + assign csr_io_nmi_lsu_load_type = _T_50 | _T_52; // @[el2_dec_tlu_ctl.scala 1034:39] + assign csr_io_tlu_i0_commit_cmt = _T_422 & _T_465; // @[el2_dec_tlu_ctl.scala 1035:39] + assign csr_io_ebreak_r = _T_469 & _T_470; // @[el2_dec_tlu_ctl.scala 1036:39] + assign csr_io_ecall_r = _T_475 & _T_470; // @[el2_dec_tlu_ctl.scala 1037:39] + assign csr_io_illegal_r = _T_481 & _T_470; // @[el2_dec_tlu_ctl.scala 1038:39] + assign csr_io_mdseac_locked_f = mdseac_locked_f; // @[el2_dec_tlu_ctl.scala 1039:39] + assign csr_io_nmi_int_detected_f = nmi_int_detected_f; // @[el2_dec_tlu_ctl.scala 1040:39] + assign csr_io_internal_dbg_halt_mode_f2 = internal_dbg_halt_mode_f2; // @[el2_dec_tlu_ctl.scala 1041:39] + assign csr_io_ext_int_freeze_d1 = ext_int_freeze_d1; // @[el2_dec_tlu_ctl.scala 1042:39] + assign csr_io_ic_perr_r_d1 = ic_perr_r_d1; // @[el2_dec_tlu_ctl.scala 1043:39] + assign csr_io_iccm_sbecc_r_d1 = iccm_sbecc_r_d1; // @[el2_dec_tlu_ctl.scala 1044:39] + assign csr_io_lsu_single_ecc_error_r_d1 = lsu_single_ecc_error_r_d1; // @[el2_dec_tlu_ctl.scala 1045:39] + assign csr_io_ifu_miss_state_idle_f = ifu_miss_state_idle_f; // @[el2_dec_tlu_ctl.scala 1046:39] + assign csr_io_lsu_idle_any_f = lsu_idle_any_f; // @[el2_dec_tlu_ctl.scala 1047:39] + assign csr_io_dbg_tlu_halted_f = dbg_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 1048:39] + assign csr_io_dbg_tlu_halted = _T_164 | _T_166; // @[el2_dec_tlu_ctl.scala 1049:39] + assign csr_io_debug_halt_req_f = debug_halt_req_f; // @[el2_dec_tlu_ctl.scala 1050:51] + assign csr_io_take_ext_int_start = ext_int_ready & _T_704; // @[el2_dec_tlu_ctl.scala 1051:47] + assign csr_io_trigger_hit_dmode_r_d1 = trigger_hit_dmode_r_d1; // @[el2_dec_tlu_ctl.scala 1052:43] + assign csr_io_trigger_hit_r_d1 = trigger_hit_r_d1; // @[el2_dec_tlu_ctl.scala 1053:43] + assign csr_io_dcsr_single_step_done_f = dcsr_single_step_done_f; // @[el2_dec_tlu_ctl.scala 1054:43] + assign csr_io_ebreak_to_debug_mode_r_d1 = ebreak_to_debug_mode_r_d1; // @[el2_dec_tlu_ctl.scala 1055:39] + assign csr_io_debug_halt_req = _T_114 & _T_107; // @[el2_dec_tlu_ctl.scala 1056:51] + assign csr_io_allow_dbg_halt_csr_write = debug_mode_status & _T_77; // @[el2_dec_tlu_ctl.scala 1057:39] + assign csr_io_internal_dbg_halt_mode_f = debug_mode_status; // @[el2_dec_tlu_ctl.scala 1058:39] + assign csr_io_enter_debug_halt_req = _T_155 | ebreak_to_debug_mode_r_d1; // @[el2_dec_tlu_ctl.scala 1059:39] + assign csr_io_internal_dbg_halt_mode = debug_halt_req_ns | _T_160; // @[el2_dec_tlu_ctl.scala 1060:39] + assign csr_io_request_debug_mode_done = _T_183 & _T_136; // @[el2_dec_tlu_ctl.scala 1061:39] + assign csr_io_request_debug_mode_r = _T_180 | _T_182; // @[el2_dec_tlu_ctl.scala 1062:39] + assign csr_io_update_hit_bit_r = _T_342 & i0_trigger_chain_masked_r; // @[el2_dec_tlu_ctl.scala 1063:39] + assign csr_io_take_timer_int = _T_703 & _T_704; // @[el2_dec_tlu_ctl.scala 1064:39] + assign csr_io_take_int_timer0_int = _T_717 & _T_704; // @[el2_dec_tlu_ctl.scala 1065:39] + assign csr_io_take_int_timer1_int = _T_734 & _T_704; // @[el2_dec_tlu_ctl.scala 1066:39] + assign csr_io_take_ext_int = take_ext_int_start_d3 & _T_685; // @[el2_dec_tlu_ctl.scala 1067:39] + assign csr_io_tlu_flush_lower_r = _T_801 | take_ext_int_start; // @[el2_dec_tlu_ctl.scala 1068:39] + assign csr_io_dec_tlu_br0_error_r = _T_453 & _T_429; // @[el2_dec_tlu_ctl.scala 1069:39] + assign csr_io_dec_tlu_br0_start_error_r = _T_455 & _T_429; // @[el2_dec_tlu_ctl.scala 1070:39] + assign csr_io_lsu_pmu_load_external_r = lsu_pmu_load_external_r; // @[el2_dec_tlu_ctl.scala 1071:39] + assign csr_io_lsu_pmu_store_external_r = lsu_pmu_store_external_r; // @[el2_dec_tlu_ctl.scala 1072:39] + assign csr_io_csr_pkt_csr_misa = csr_read_io_csr_pkt_csr_misa; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mvendorid = csr_read_io_csr_pkt_csr_mvendorid; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_marchid = csr_read_io_csr_pkt_csr_marchid; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mimpid = csr_read_io_csr_pkt_csr_mimpid; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mhartid = csr_read_io_csr_pkt_csr_mhartid; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mstatus = csr_read_io_csr_pkt_csr_mstatus; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mtvec = csr_read_io_csr_pkt_csr_mtvec; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mip = csr_read_io_csr_pkt_csr_mip; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mie = csr_read_io_csr_pkt_csr_mie; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mcyclel = csr_read_io_csr_pkt_csr_mcyclel; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mcycleh = csr_read_io_csr_pkt_csr_mcycleh; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_minstretl = csr_read_io_csr_pkt_csr_minstretl; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_minstreth = csr_read_io_csr_pkt_csr_minstreth; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mscratch = csr_read_io_csr_pkt_csr_mscratch; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mepc = csr_read_io_csr_pkt_csr_mepc; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mcause = csr_read_io_csr_pkt_csr_mcause; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mscause = csr_read_io_csr_pkt_csr_mscause; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mtval = csr_read_io_csr_pkt_csr_mtval; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mrac = csr_read_io_csr_pkt_csr_mrac; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mdseac = csr_read_io_csr_pkt_csr_mdseac; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_meihap = csr_read_io_csr_pkt_csr_meihap; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_meivt = csr_read_io_csr_pkt_csr_meivt; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_meipt = csr_read_io_csr_pkt_csr_meipt; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_meicurpl = csr_read_io_csr_pkt_csr_meicurpl; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_meicidpl = csr_read_io_csr_pkt_csr_meicidpl; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_dcsr = csr_read_io_csr_pkt_csr_dcsr; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mcgc = csr_read_io_csr_pkt_csr_mcgc; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mfdc = csr_read_io_csr_pkt_csr_mfdc; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_dpc = csr_read_io_csr_pkt_csr_dpc; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mtsel = csr_read_io_csr_pkt_csr_mtsel; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mtdata1 = csr_read_io_csr_pkt_csr_mtdata1; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mtdata2 = csr_read_io_csr_pkt_csr_mtdata2; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mhpmc3 = csr_read_io_csr_pkt_csr_mhpmc3; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mhpmc4 = csr_read_io_csr_pkt_csr_mhpmc4; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mhpmc5 = csr_read_io_csr_pkt_csr_mhpmc5; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mhpmc6 = csr_read_io_csr_pkt_csr_mhpmc6; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mhpmc3h = csr_read_io_csr_pkt_csr_mhpmc3h; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mhpmc4h = csr_read_io_csr_pkt_csr_mhpmc4h; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mhpmc5h = csr_read_io_csr_pkt_csr_mhpmc5h; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mhpmc6h = csr_read_io_csr_pkt_csr_mhpmc6h; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mhpme3 = csr_read_io_csr_pkt_csr_mhpme3; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mhpme4 = csr_read_io_csr_pkt_csr_mhpme4; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mhpme5 = csr_read_io_csr_pkt_csr_mhpme5; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mhpme6 = csr_read_io_csr_pkt_csr_mhpme6; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mcountinhibit = csr_read_io_csr_pkt_csr_mcountinhibit; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mpmc = csr_read_io_csr_pkt_csr_mpmc; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_micect = csr_read_io_csr_pkt_csr_micect; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_miccmect = csr_read_io_csr_pkt_csr_miccmect; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mdccmect = csr_read_io_csr_pkt_csr_mdccmect; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mfdht = csr_read_io_csr_pkt_csr_mfdht; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mfdhs = csr_read_io_csr_pkt_csr_mfdhs; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_dicawics = csr_read_io_csr_pkt_csr_dicawics; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_dicad0h = csr_read_io_csr_pkt_csr_dicad0h; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_dicad0 = csr_read_io_csr_pkt_csr_dicad0; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_dicad1 = csr_read_io_csr_pkt_csr_dicad1; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_read_io_dec_csr_rdaddr_d = io_dec_csr_rdaddr_d; // @[el2_dec_tlu_ctl.scala 1091:31] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + dbg_halt_state_f = _RAND_0[0:0]; + _RAND_1 = {1{`RANDOM}}; + mpc_halt_state_f = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + _T_8 = _RAND_2[6:0]; + _RAND_3 = {1{`RANDOM}}; + syncro_ff = _RAND_3[6:0]; + _RAND_4 = {1{`RANDOM}}; + lsu_exc_valid_r_d1 = _RAND_4[0:0]; + _RAND_5 = {1{`RANDOM}}; + e5_valid = _RAND_5[0:0]; + _RAND_6 = {1{`RANDOM}}; + debug_mode_status = _RAND_6[0:0]; + _RAND_7 = {1{`RANDOM}}; + i_cpu_run_req_d1_raw = _RAND_7[0:0]; + _RAND_8 = {1{`RANDOM}}; + nmi_int_delayed = _RAND_8[0:0]; + _RAND_9 = {1{`RANDOM}}; + mdseac_locked_f = _RAND_9[0:0]; + _RAND_10 = {1{`RANDOM}}; + nmi_int_detected_f = _RAND_10[0:0]; + _RAND_11 = {1{`RANDOM}}; + take_nmi_r_d1 = _RAND_11[0:0]; + _RAND_12 = {1{`RANDOM}}; + take_ext_int_start_d3 = _RAND_12[0:0]; + _RAND_13 = {1{`RANDOM}}; + int_timer0_int_hold_f = _RAND_13[0:0]; + _RAND_14 = {1{`RANDOM}}; + int_timer1_int_hold_f = _RAND_14[0:0]; + _RAND_15 = {1{`RANDOM}}; + i_cpu_halt_req_d1 = _RAND_15[0:0]; + _RAND_16 = {1{`RANDOM}}; + dbg_halt_req_held = _RAND_16[0:0]; + _RAND_17 = {1{`RANDOM}}; + ext_int_freeze_d1 = _RAND_17[0:0]; + _RAND_18 = {1{`RANDOM}}; + reset_detect = _RAND_18[0:0]; + _RAND_19 = {1{`RANDOM}}; + reset_detected = _RAND_19[0:0]; + _RAND_20 = {1{`RANDOM}}; + dcsr_single_step_done_f = _RAND_20[0:0]; + _RAND_21 = {1{`RANDOM}}; + trigger_hit_dmode_r_d1 = _RAND_21[0:0]; + _RAND_22 = {1{`RANDOM}}; + ebreak_to_debug_mode_r_d1 = _RAND_22[0:0]; + _RAND_23 = {1{`RANDOM}}; + debug_halt_req_f = _RAND_23[0:0]; + _RAND_24 = {1{`RANDOM}}; + lsu_idle_any_f = _RAND_24[0:0]; + _RAND_25 = {1{`RANDOM}}; + ifu_miss_state_idle_f = _RAND_25[0:0]; + _RAND_26 = {1{`RANDOM}}; + debug_halt_req_d1 = _RAND_26[0:0]; + _RAND_27 = {1{`RANDOM}}; + dec_tlu_flush_noredir_r_d1 = _RAND_27[0:0]; + _RAND_28 = {1{`RANDOM}}; + dec_tlu_flush_pause_r_d1 = _RAND_28[0:0]; + _RAND_29 = {1{`RANDOM}}; + take_ext_int_start_d1 = _RAND_29[0:0]; + _RAND_30 = {1{`RANDOM}}; + halt_taken_f = _RAND_30[0:0]; + _RAND_31 = {1{`RANDOM}}; + dbg_tlu_halted_f = _RAND_31[0:0]; + _RAND_32 = {1{`RANDOM}}; + pmu_fw_tlu_halted_f = _RAND_32[0:0]; + _RAND_33 = {1{`RANDOM}}; + interrupt_valid_r_d1 = _RAND_33[0:0]; + _RAND_34 = {1{`RANDOM}}; + debug_resume_req_f = _RAND_34[0:0]; + _RAND_35 = {1{`RANDOM}}; + dcsr_single_step_running_f = _RAND_35[0:0]; + _RAND_36 = {1{`RANDOM}}; + pmu_fw_halt_req_f = _RAND_36[0:0]; + _RAND_37 = {1{`RANDOM}}; + internal_pmu_fw_halt_mode_f = _RAND_37[0:0]; + _RAND_38 = {1{`RANDOM}}; + tlu_flush_lower_r_d1 = _RAND_38[0:0]; + _RAND_39 = {1{`RANDOM}}; + ic_perr_r_d1 = _RAND_39[0:0]; + _RAND_40 = {1{`RANDOM}}; + iccm_sbecc_r_d1 = _RAND_40[0:0]; + _RAND_41 = {1{`RANDOM}}; + request_debug_mode_r_d1 = _RAND_41[0:0]; + _RAND_42 = {1{`RANDOM}}; + iccm_repair_state_d1 = _RAND_42[0:0]; + _RAND_43 = {1{`RANDOM}}; + dec_pause_state_f = _RAND_43[0:0]; + _RAND_44 = {1{`RANDOM}}; + dec_tlu_wr_pause_r_d1 = _RAND_44[0:0]; + _RAND_45 = {1{`RANDOM}}; + exc_or_int_valid_r_d1 = _RAND_45[0:0]; + _RAND_46 = {1{`RANDOM}}; + pause_expired_wb = _RAND_46[0:0]; + _RAND_47 = {1{`RANDOM}}; + lsu_pmu_load_external_r = _RAND_47[0:0]; + _RAND_48 = {1{`RANDOM}}; + lsu_pmu_store_external_r = _RAND_48[0:0]; + _RAND_49 = {1{`RANDOM}}; + _T_32 = _RAND_49[0:0]; + _RAND_50 = {1{`RANDOM}}; + internal_dbg_halt_mode_f2 = _RAND_50[0:0]; + _RAND_51 = {1{`RANDOM}}; + _T_33 = _RAND_51[0:0]; + _RAND_52 = {1{`RANDOM}}; + nmi_lsu_load_type_f = _RAND_52[0:0]; + _RAND_53 = {1{`RANDOM}}; + nmi_lsu_store_type_f = _RAND_53[0:0]; + _RAND_54 = {1{`RANDOM}}; + mpc_debug_halt_req_sync_f = _RAND_54[0:0]; + _RAND_55 = {1{`RANDOM}}; + mpc_debug_run_req_sync_f = _RAND_55[0:0]; + _RAND_56 = {1{`RANDOM}}; + mpc_run_state_f = _RAND_56[0:0]; + _RAND_57 = {1{`RANDOM}}; + debug_brkpt_status_f = _RAND_57[0:0]; + _RAND_58 = {1{`RANDOM}}; + mpc_debug_halt_ack_f = _RAND_58[0:0]; + _RAND_59 = {1{`RANDOM}}; + mpc_debug_run_ack_f = _RAND_59[0:0]; + _RAND_60 = {1{`RANDOM}}; + dbg_run_state_f = _RAND_60[0:0]; + _RAND_61 = {1{`RANDOM}}; + _T_65 = _RAND_61[0:0]; + _RAND_62 = {1{`RANDOM}}; + request_debug_mode_done_f = _RAND_62[0:0]; + _RAND_63 = {1{`RANDOM}}; + _T_190 = _RAND_63[0:0]; + _RAND_64 = {1{`RANDOM}}; + _T_353 = _RAND_64[0:0]; + _RAND_65 = {1{`RANDOM}}; + _T_354 = _RAND_65[0:0]; + _RAND_66 = {1{`RANDOM}}; + _T_355 = _RAND_66[0:0]; + _RAND_67 = {1{`RANDOM}}; + lsu_single_ecc_error_r_d1 = _RAND_67[0:0]; + _RAND_68 = {1{`RANDOM}}; + lsu_i0_exc_r_d1 = _RAND_68[0:0]; + _RAND_69 = {1{`RANDOM}}; + take_ext_int_start_d2 = _RAND_69[0:0]; + _RAND_70 = {1{`RANDOM}}; + tlu_flush_path_r_d1 = _RAND_70[30:0]; + _RAND_71 = {1{`RANDOM}}; + i0_exception_valid_r_d1 = _RAND_71[0:0]; + _RAND_72 = {1{`RANDOM}}; + exc_cause_wb = _RAND_72[4:0]; + _RAND_73 = {1{`RANDOM}}; + i0_valid_wb = _RAND_73[0:0]; + _RAND_74 = {1{`RANDOM}}; + trigger_hit_r_d1 = _RAND_74[0:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + dbg_halt_state_f = 1'h0; + end + if (reset) begin + mpc_halt_state_f = 1'h0; + end + if (reset) begin + _T_8 = 7'h0; + end + if (reset) begin + syncro_ff = 7'h0; + end + if (reset) begin + lsu_exc_valid_r_d1 = 1'h0; + end + if (reset) begin + e5_valid = 1'h0; + end + if (reset) begin + debug_mode_status = 1'h0; + end + if (reset) begin + i_cpu_run_req_d1_raw = 1'h0; + end + if (reset) begin + nmi_int_delayed = 1'h0; + end + if (reset) begin + mdseac_locked_f = 1'h0; + end + if (reset) begin + nmi_int_detected_f = 1'h0; + end + if (reset) begin + take_nmi_r_d1 = 1'h0; + end + if (reset) begin + take_ext_int_start_d3 = 1'h0; + end + if (reset) begin + int_timer0_int_hold_f = 1'h0; + end + if (reset) begin + int_timer1_int_hold_f = 1'h0; + end + if (reset) begin + i_cpu_halt_req_d1 = 1'h0; + end + if (reset) begin + dbg_halt_req_held = 1'h0; + end + if (reset) begin + ext_int_freeze_d1 = 1'h0; + end + if (reset) begin + reset_detect = 1'h0; + end + if (reset) begin + reset_detected = 1'h0; + end + if (reset) begin + dcsr_single_step_done_f = 1'h0; + end + if (reset) begin + trigger_hit_dmode_r_d1 = 1'h0; + end + if (reset) begin + ebreak_to_debug_mode_r_d1 = 1'h0; + end + if (reset) begin + debug_halt_req_f = 1'h0; + end + if (reset) begin + lsu_idle_any_f = 1'h0; + end + if (reset) begin + ifu_miss_state_idle_f = 1'h0; + end + if (reset) begin + debug_halt_req_d1 = 1'h0; + end + if (reset) begin + dec_tlu_flush_noredir_r_d1 = 1'h0; + end + if (reset) begin + dec_tlu_flush_pause_r_d1 = 1'h0; + end + if (reset) begin + take_ext_int_start_d1 = 1'h0; + end + if (reset) begin + halt_taken_f = 1'h0; + end + if (reset) begin + dbg_tlu_halted_f = 1'h0; + end + if (reset) begin + pmu_fw_tlu_halted_f = 1'h0; + end + if (reset) begin + interrupt_valid_r_d1 = 1'h0; + end + if (reset) begin + debug_resume_req_f = 1'h0; + end + if (reset) begin + dcsr_single_step_running_f = 1'h0; + end + if (reset) begin + pmu_fw_halt_req_f = 1'h0; + end + if (reset) begin + internal_pmu_fw_halt_mode_f = 1'h0; + end + if (reset) begin + tlu_flush_lower_r_d1 = 1'h0; + end + if (reset) begin + ic_perr_r_d1 = 1'h0; + end + if (reset) begin + iccm_sbecc_r_d1 = 1'h0; + end + if (reset) begin + request_debug_mode_r_d1 = 1'h0; + end + if (reset) begin + iccm_repair_state_d1 = 1'h0; + end + if (reset) begin + dec_pause_state_f = 1'h0; + end + if (reset) begin + dec_tlu_wr_pause_r_d1 = 1'h0; + end + if (reset) begin + exc_or_int_valid_r_d1 = 1'h0; + end + if (reset) begin + pause_expired_wb = 1'h0; + end + if (reset) begin + lsu_pmu_load_external_r = 1'h0; + end + if (reset) begin + lsu_pmu_store_external_r = 1'h0; + end + if (reset) begin + _T_32 = 1'h0; + end + if (reset) begin + internal_dbg_halt_mode_f2 = 1'h0; + end + if (reset) begin + _T_33 = 1'h0; + end + if (reset) begin + nmi_lsu_load_type_f = 1'h0; + end + if (reset) begin + nmi_lsu_store_type_f = 1'h0; + end + if (reset) begin + mpc_debug_halt_req_sync_f = 1'h0; + end + if (reset) begin + mpc_debug_run_req_sync_f = 1'h0; + end + if (reset) begin + mpc_run_state_f = 1'h0; + end + if (reset) begin + debug_brkpt_status_f = 1'h0; + end + if (reset) begin + mpc_debug_halt_ack_f = 1'h0; + end + if (reset) begin + mpc_debug_run_ack_f = 1'h0; + end + if (reset) begin + dbg_run_state_f = 1'h0; + end + if (reset) begin + _T_65 = 1'h0; + end + if (reset) begin + request_debug_mode_done_f = 1'h0; + end + if (reset) begin + _T_190 = 1'h0; + end + if (reset) begin + _T_353 = 1'h0; + end + if (reset) begin + _T_354 = 1'h0; + end + if (reset) begin + _T_355 = 1'h0; + end + if (reset) begin + lsu_single_ecc_error_r_d1 = 1'h0; + end + if (reset) begin + lsu_i0_exc_r_d1 = 1'h0; + end + if (reset) begin + take_ext_int_start_d2 = 1'h0; + end + if (reset) begin + tlu_flush_path_r_d1 = 31'h0; + end + if (reset) begin + i0_exception_valid_r_d1 = 1'h0; + end + if (reset) begin + exc_cause_wb = 5'h0; + end + if (reset) begin + i0_valid_wb = 1'h0; + end + if (reset) begin + trigger_hit_r_d1 = 1'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + dbg_halt_state_f <= 1'h0; + end else begin + dbg_halt_state_f <= _T_83 & _T_84; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + mpc_halt_state_f <= 1'h0; + end else begin + mpc_halt_state_f <= _T_71 & _T_72; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + _T_8 <= 7'h0; + end else begin + _T_8 <= {_T_6,_T_3}; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + syncro_ff <= 7'h0; + end else begin + syncro_ff <= _T_8; + end + end + always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin + if (reset) begin + lsu_exc_valid_r_d1 <= 1'h0; + end else begin + lsu_exc_valid_r_d1 <= _T_405 & _T_470; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + e5_valid <= 1'h0; + end else begin + e5_valid <= io_dec_tlu_i0_valid_r; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + debug_mode_status <= 1'h0; + end else begin + debug_mode_status <= debug_halt_req_ns | _T_160; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + i_cpu_run_req_d1_raw <= 1'h0; + end else begin + i_cpu_run_req_d1_raw <= _T_351 & _T_107; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + nmi_int_delayed <= 1'h0; + end else begin + nmi_int_delayed <= syncro_ff[6]; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + mdseac_locked_f <= 1'h0; + end else begin + mdseac_locked_f <= csr_io_mdseac_locked_ns; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + nmi_int_detected_f <= 1'h0; + end else begin + nmi_int_detected_f <= _T_42 | _T_44; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + take_nmi_r_d1 <= 1'h0; + end else begin + take_nmi_r_d1 <= _T_756 & _T_760; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + take_ext_int_start_d3 <= 1'h0; + end else begin + take_ext_int_start_d3 <= take_ext_int_start_d2; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + int_timer0_int_hold_f <= 1'h0; + end else begin + int_timer0_int_hold_f <= _T_644 | _T_651; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + int_timer1_int_hold_f <= 1'h0; + end else begin + int_timer1_int_hold_f <= _T_654 | _T_661; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + i_cpu_halt_req_d1 <= 1'h0; + end else begin + i_cpu_halt_req_d1 <= _T_347 & _T_107; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + dbg_halt_req_held <= 1'h0; + end else begin + dbg_halt_req_held <= _T_106 & ext_int_freeze_d1; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + ext_int_freeze_d1 <= 1'h0; + end else begin + ext_int_freeze_d1 <= _T_682 | take_ext_int_start_d3; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + reset_detect <= 1'h0; + end else begin + reset_detect <= 1'h1; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + reset_detected <= 1'h0; + end else begin + reset_detected <= reset_detect; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + dcsr_single_step_done_f <= 1'h0; + end else begin + dcsr_single_step_done_f <= _T_174 & _T_470; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + trigger_hit_dmode_r_d1 <= 1'h0; + end else begin + trigger_hit_dmode_r_d1 <= i0_trigger_hit_raw_r & i0_trigger_action_r; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + ebreak_to_debug_mode_r_d1 <= 1'h0; + end else begin + ebreak_to_debug_mode_r_d1 <= _T_519 & _T_470; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + debug_halt_req_f <= 1'h0; + end else begin + debug_halt_req_f <= enter_debug_halt_req | _T_168; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + lsu_idle_any_f <= 1'h0; + end else begin + lsu_idle_any_f <= io_lsu_idle_any; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + ifu_miss_state_idle_f <= 1'h0; + end else begin + ifu_miss_state_idle_f <= io_ifu_miss_state_idle; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + debug_halt_req_d1 <= 1'h0; + end else begin + debug_halt_req_d1 <= _T_114 & _T_107; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + dec_tlu_flush_noredir_r_d1 <= 1'h0; + end else begin + dec_tlu_flush_noredir_r_d1 <= io_dec_tlu_flush_noredir_r; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + dec_tlu_flush_pause_r_d1 <= 1'h0; + end else begin + dec_tlu_flush_pause_r_d1 <= io_dec_tlu_flush_pause_r; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + take_ext_int_start_d1 <= 1'h0; + end else begin + take_ext_int_start_d1 <= ext_int_ready & _T_704; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + halt_taken_f <= 1'h0; + end else begin + halt_taken_f <= _T_135 | _T_141; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + dbg_tlu_halted_f <= 1'h0; + end else begin + dbg_tlu_halted_f <= _T_164 | _T_166; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + pmu_fw_tlu_halted_f <= 1'h0; + end else begin + pmu_fw_tlu_halted_f <= _T_377 & _T_378; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + interrupt_valid_r_d1 <= 1'h0; + end else begin + interrupt_valid_r_d1 <= _T_766 | take_int_timer1_int; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + debug_resume_req_f <= 1'h0; + end else begin + debug_resume_req_f <= _T_165 & _T_121; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + dcsr_single_step_running_f <= 1'h0; + end else begin + dcsr_single_step_running_f <= _T_177 | _T_179; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + pmu_fw_halt_req_f <= 1'h0; + end else begin + pmu_fw_halt_req_f <= _T_363 & _T_378; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + internal_pmu_fw_halt_mode_f <= 1'h0; + end else begin + internal_pmu_fw_halt_mode_f <= pmu_fw_halt_req_ns | _T_369; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + tlu_flush_lower_r_d1 <= 1'h0; + end else begin + tlu_flush_lower_r_d1 <= _T_801 | take_ext_int_start; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + ic_perr_r_d1 <= 1'h0; + end else begin + ic_perr_r_d1 <= _T_499 & _T_500; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + iccm_sbecc_r_d1 <= 1'h0; + end else begin + iccm_sbecc_r_d1 <= _T_506 & _T_500; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + request_debug_mode_r_d1 <= 1'h0; + end else begin + request_debug_mode_r_d1 <= _T_180 | _T_182; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + iccm_repair_state_d1 <= 1'h0; + end else begin + iccm_repair_state_d1 <= iccm_sbecc_r_d1 | _T_442; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + dec_pause_state_f <= 1'h0; + end else begin + dec_pause_state_f <= io_dec_pause_state; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + dec_tlu_wr_pause_r_d1 <= 1'h0; + end else begin + dec_tlu_wr_pause_r_d1 <= io_dec_tlu_wr_pause_r; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + exc_or_int_valid_r_d1 <= 1'h0; + end else begin + exc_or_int_valid_r_d1 <= _T_855 | mepc_trigger_hit_sel_pc_r; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + pause_expired_wb <= 1'h0; + end else begin + pause_expired_wb <= _T_227 & _T_228; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + lsu_pmu_load_external_r <= 1'h0; + end else begin + lsu_pmu_load_external_r <= io_lsu_pmu_load_external_m; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + lsu_pmu_store_external_r <= 1'h0; + end else begin + lsu_pmu_store_external_r <= io_lsu_pmu_store_external_m; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + _T_32 <= 1'h0; + end else begin + _T_32 <= _T_427 | i0_trigger_hit_raw_r; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + internal_dbg_halt_mode_f2 <= 1'h0; + end else begin + internal_dbg_halt_mode_f2 <= debug_mode_status; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + _T_33 <= 1'h0; + end else begin + _T_33 <= csr_io_force_halt; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + nmi_lsu_load_type_f <= 1'h0; + end else begin + nmi_lsu_load_type_f <= _T_50 | _T_52; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + nmi_lsu_store_type_f <= 1'h0; + end else begin + nmi_lsu_store_type_f <= _T_58 | _T_60; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + mpc_debug_halt_req_sync_f <= 1'h0; + end else begin + mpc_debug_halt_req_sync_f <= mpc_debug_halt_req_sync_raw & _T_107; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + mpc_debug_run_req_sync_f <= 1'h0; + end else begin + mpc_debug_run_req_sync_f <= syncro_ff[0]; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + mpc_run_state_f <= 1'h0; + end else begin + mpc_run_state_f <= _T_76 & _T_78; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + debug_brkpt_status_f <= 1'h0; + end else begin + debug_brkpt_status_f <= _T_92 & _T_94; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + mpc_debug_halt_ack_f <= 1'h0; + end else begin + mpc_debug_halt_ack_f <= _T_97 & core_empty; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + mpc_debug_run_ack_f <= 1'h0; + end else begin + mpc_debug_run_ack_f <= _T_102 | _T_103; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + dbg_run_state_f <= 1'h0; + end else begin + dbg_run_state_f <= _T_86 & _T_78; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + _T_65 <= 1'h0; + end else begin + _T_65 <= _T & mpc_halt_state_f; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + request_debug_mode_done_f <= 1'h0; + end else begin + request_debug_mode_done_f <= _T_183 & _T_136; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + _T_190 <= 1'h0; + end else begin + _T_190 <= _T_170 & dbg_run_state_ns; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + _T_353 <= 1'h0; + end else begin + _T_353 <= _T_376 | _T_386; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + _T_354 <= 1'h0; + end else begin + _T_354 <= i_cpu_halt_req_d1 & pmu_fw_tlu_halted_f; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + _T_355 <= 1'h0; + end else begin + _T_355 <= _T_388 | _T_389; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + lsu_single_ecc_error_r_d1 <= 1'h0; + end else begin + lsu_single_ecc_error_r_d1 <= io_lsu_single_ecc_error_incr; + end + end + always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin + if (reset) begin + lsu_i0_exc_r_d1 <= 1'h0; + end else begin + lsu_i0_exc_r_d1 <= _T_405 & _T_470; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + take_ext_int_start_d2 <= 1'h0; + end else begin + take_ext_int_start_d2 <= take_ext_int_start_d1; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + tlu_flush_path_r_d1 <= 31'h0; + end else if (take_reset) begin + tlu_flush_path_r_d1 <= io_rst_vec; + end else begin + tlu_flush_path_r_d1 <= _T_852; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + i0_exception_valid_r_d1 <= 1'h0; + end else begin + i0_exception_valid_r_d1 <= _T_527 & _T_528; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + exc_cause_wb <= 5'h0; + end else begin + exc_cause_wb <= _T_603 | _T_591; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + i0_valid_wb <= 1'h0; + end else begin + i0_valid_wb <= tlu_i0_commit_cmt & _T_860; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + trigger_hit_r_d1 <= 1'h0; + end else begin + trigger_hit_r_d1 <= |i0_trigger_chain_masked_r; + end + end +endmodule diff --git a/el2_dec_trigger.anno.json b/el2_dec_trigger.anno.json index b46322b8..cc27db89 100644 --- a/el2_dec_trigger.anno.json +++ b/el2_dec_trigger.anno.json @@ -12,13 +12,13 @@ "~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_2_execute", "~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_2_m", "~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_0_tdata2", + "~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_0_match_pkt", "~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_1_tdata2", - "~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_0_match_", + "~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_1_match_pkt", "~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_3_tdata2", + "~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_3_match_pkt", "~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_2_tdata2", - "~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_1_match_", - "~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_3_match_", - "~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_2_match_", + "~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_2_match_pkt", "~el2_dec_trigger|el2_dec_trigger>io_dec_i0_pc_d", "~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_0_select", "~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_1_select", @@ -26,6 +26,12 @@ "~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_2_select" ] }, + { + "class":"logger.LogLevelAnnotation", + "globalLogLevel":{ + + } + }, { "class":"firrtl.EmitCircuitAnnotation", "emitter":"firrtl.VerilogEmitter" diff --git a/el2_dec_trigger.fir b/el2_dec_trigger.fir index 26647ae8..7cf06567 100644 --- a/el2_dec_trigger.fir +++ b/el2_dec_trigger.fir @@ -3,43 +3,43 @@ circuit el2_dec_trigger : module el2_dec_trigger : input clock : Clock input reset : UInt<1> - output io : {flip trigger_pkt_any : {select : UInt<1>, match_ : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip dec_i0_pc_d : UInt<31>, dec_i0_trigger_match_d : UInt<4>} + output io : {flip trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip dec_i0_pc_d : UInt<31>, dec_i0_trigger_match_d : UInt<4>} - node _T = eq(io.trigger_pkt_any[0].select, UInt<1>("h00")) @[el2_lsu_trigger.scala 15:63] - node _T_1 = and(_T, io.trigger_pkt_any[0].execute) @[el2_lsu_trigger.scala 15:93] - wire _T_2 : UInt<1>[32] @[el2_lib.scala 177:24] - _T_2[0] <= _T_1 @[el2_lib.scala 177:24] - _T_2[1] <= _T_1 @[el2_lib.scala 177:24] - _T_2[2] <= _T_1 @[el2_lib.scala 177:24] - _T_2[3] <= _T_1 @[el2_lib.scala 177:24] - _T_2[4] <= _T_1 @[el2_lib.scala 177:24] - _T_2[5] <= _T_1 @[el2_lib.scala 177:24] - _T_2[6] <= _T_1 @[el2_lib.scala 177:24] - _T_2[7] <= _T_1 @[el2_lib.scala 177:24] - _T_2[8] <= _T_1 @[el2_lib.scala 177:24] - _T_2[9] <= _T_1 @[el2_lib.scala 177:24] - _T_2[10] <= _T_1 @[el2_lib.scala 177:24] - _T_2[11] <= _T_1 @[el2_lib.scala 177:24] - _T_2[12] <= _T_1 @[el2_lib.scala 177:24] - _T_2[13] <= _T_1 @[el2_lib.scala 177:24] - _T_2[14] <= _T_1 @[el2_lib.scala 177:24] - _T_2[15] <= _T_1 @[el2_lib.scala 177:24] - _T_2[16] <= _T_1 @[el2_lib.scala 177:24] - _T_2[17] <= _T_1 @[el2_lib.scala 177:24] - _T_2[18] <= _T_1 @[el2_lib.scala 177:24] - _T_2[19] <= _T_1 @[el2_lib.scala 177:24] - _T_2[20] <= _T_1 @[el2_lib.scala 177:24] - _T_2[21] <= _T_1 @[el2_lib.scala 177:24] - _T_2[22] <= _T_1 @[el2_lib.scala 177:24] - _T_2[23] <= _T_1 @[el2_lib.scala 177:24] - _T_2[24] <= _T_1 @[el2_lib.scala 177:24] - _T_2[25] <= _T_1 @[el2_lib.scala 177:24] - _T_2[26] <= _T_1 @[el2_lib.scala 177:24] - _T_2[27] <= _T_1 @[el2_lib.scala 177:24] - _T_2[28] <= _T_1 @[el2_lib.scala 177:24] - _T_2[29] <= _T_1 @[el2_lib.scala 177:24] - _T_2[30] <= _T_1 @[el2_lib.scala 177:24] - _T_2[31] <= _T_1 @[el2_lib.scala 177:24] + node _T = eq(io.trigger_pkt_any[0].select, UInt<1>("h00")) @[el2_dec_trigger.scala 14:63] + node _T_1 = and(_T, io.trigger_pkt_any[0].execute) @[el2_dec_trigger.scala 14:93] + wire _T_2 : UInt<1>[32] @[el2_lib.scala 162:48] + _T_2[0] <= _T_1 @[el2_lib.scala 162:48] + _T_2[1] <= _T_1 @[el2_lib.scala 162:48] + _T_2[2] <= _T_1 @[el2_lib.scala 162:48] + _T_2[3] <= _T_1 @[el2_lib.scala 162:48] + _T_2[4] <= _T_1 @[el2_lib.scala 162:48] + _T_2[5] <= _T_1 @[el2_lib.scala 162:48] + _T_2[6] <= _T_1 @[el2_lib.scala 162:48] + _T_2[7] <= _T_1 @[el2_lib.scala 162:48] + _T_2[8] <= _T_1 @[el2_lib.scala 162:48] + _T_2[9] <= _T_1 @[el2_lib.scala 162:48] + _T_2[10] <= _T_1 @[el2_lib.scala 162:48] + _T_2[11] <= _T_1 @[el2_lib.scala 162:48] + _T_2[12] <= _T_1 @[el2_lib.scala 162:48] + _T_2[13] <= _T_1 @[el2_lib.scala 162:48] + _T_2[14] <= _T_1 @[el2_lib.scala 162:48] + _T_2[15] <= _T_1 @[el2_lib.scala 162:48] + _T_2[16] <= _T_1 @[el2_lib.scala 162:48] + _T_2[17] <= _T_1 @[el2_lib.scala 162:48] + _T_2[18] <= _T_1 @[el2_lib.scala 162:48] + _T_2[19] <= _T_1 @[el2_lib.scala 162:48] + _T_2[20] <= _T_1 @[el2_lib.scala 162:48] + _T_2[21] <= _T_1 @[el2_lib.scala 162:48] + _T_2[22] <= _T_1 @[el2_lib.scala 162:48] + _T_2[23] <= _T_1 @[el2_lib.scala 162:48] + _T_2[24] <= _T_1 @[el2_lib.scala 162:48] + _T_2[25] <= _T_1 @[el2_lib.scala 162:48] + _T_2[26] <= _T_1 @[el2_lib.scala 162:48] + _T_2[27] <= _T_1 @[el2_lib.scala 162:48] + _T_2[28] <= _T_1 @[el2_lib.scala 162:48] + _T_2[29] <= _T_1 @[el2_lib.scala 162:48] + _T_2[30] <= _T_1 @[el2_lib.scala 162:48] + _T_2[31] <= _T_1 @[el2_lib.scala 162:48] node _T_3 = cat(_T_2[0], _T_2[1]) @[Cat.scala 29:58] node _T_4 = cat(_T_3, _T_2[2]) @[Cat.scala 29:58] node _T_5 = cat(_T_4, _T_2[3]) @[Cat.scala 29:58] @@ -71,44 +71,44 @@ circuit el2_dec_trigger : node _T_31 = cat(_T_30, _T_2[29]) @[Cat.scala 29:58] node _T_32 = cat(_T_31, _T_2[30]) @[Cat.scala 29:58] node _T_33 = cat(_T_32, _T_2[31]) @[Cat.scala 29:58] - node _T_34 = bits(io.trigger_pkt_any[0].tdata2, 0, 0) @[el2_lsu_trigger.scala 15:177] + node _T_34 = bits(io.trigger_pkt_any[0].tdata2, 0, 0) @[el2_dec_trigger.scala 14:177] node _T_35 = cat(io.dec_i0_pc_d, _T_34) @[Cat.scala 29:58] - node _T_36 = and(_T_33, _T_35) @[el2_lsu_trigger.scala 15:127] - node _T_37 = eq(io.trigger_pkt_any[1].select, UInt<1>("h00")) @[el2_lsu_trigger.scala 15:63] - node _T_38 = and(_T_37, io.trigger_pkt_any[1].execute) @[el2_lsu_trigger.scala 15:93] - wire _T_39 : UInt<1>[32] @[el2_lib.scala 177:24] - _T_39[0] <= _T_38 @[el2_lib.scala 177:24] - _T_39[1] <= _T_38 @[el2_lib.scala 177:24] - _T_39[2] <= _T_38 @[el2_lib.scala 177:24] - _T_39[3] <= _T_38 @[el2_lib.scala 177:24] - _T_39[4] <= _T_38 @[el2_lib.scala 177:24] - _T_39[5] <= _T_38 @[el2_lib.scala 177:24] - _T_39[6] <= _T_38 @[el2_lib.scala 177:24] - _T_39[7] <= _T_38 @[el2_lib.scala 177:24] - _T_39[8] <= _T_38 @[el2_lib.scala 177:24] - _T_39[9] <= _T_38 @[el2_lib.scala 177:24] - _T_39[10] <= _T_38 @[el2_lib.scala 177:24] - _T_39[11] <= _T_38 @[el2_lib.scala 177:24] - _T_39[12] <= _T_38 @[el2_lib.scala 177:24] - _T_39[13] <= _T_38 @[el2_lib.scala 177:24] - _T_39[14] <= _T_38 @[el2_lib.scala 177:24] - _T_39[15] <= _T_38 @[el2_lib.scala 177:24] - _T_39[16] <= _T_38 @[el2_lib.scala 177:24] - _T_39[17] <= _T_38 @[el2_lib.scala 177:24] - _T_39[18] <= _T_38 @[el2_lib.scala 177:24] - _T_39[19] <= _T_38 @[el2_lib.scala 177:24] - _T_39[20] <= _T_38 @[el2_lib.scala 177:24] - _T_39[21] <= _T_38 @[el2_lib.scala 177:24] - _T_39[22] <= _T_38 @[el2_lib.scala 177:24] - _T_39[23] <= _T_38 @[el2_lib.scala 177:24] - _T_39[24] <= _T_38 @[el2_lib.scala 177:24] - _T_39[25] <= _T_38 @[el2_lib.scala 177:24] - _T_39[26] <= _T_38 @[el2_lib.scala 177:24] - _T_39[27] <= _T_38 @[el2_lib.scala 177:24] - _T_39[28] <= _T_38 @[el2_lib.scala 177:24] - _T_39[29] <= _T_38 @[el2_lib.scala 177:24] - _T_39[30] <= _T_38 @[el2_lib.scala 177:24] - _T_39[31] <= _T_38 @[el2_lib.scala 177:24] + node _T_36 = and(_T_33, _T_35) @[el2_dec_trigger.scala 14:127] + node _T_37 = eq(io.trigger_pkt_any[1].select, UInt<1>("h00")) @[el2_dec_trigger.scala 14:63] + node _T_38 = and(_T_37, io.trigger_pkt_any[1].execute) @[el2_dec_trigger.scala 14:93] + wire _T_39 : UInt<1>[32] @[el2_lib.scala 162:48] + _T_39[0] <= _T_38 @[el2_lib.scala 162:48] + _T_39[1] <= _T_38 @[el2_lib.scala 162:48] + _T_39[2] <= _T_38 @[el2_lib.scala 162:48] + _T_39[3] <= _T_38 @[el2_lib.scala 162:48] + _T_39[4] <= _T_38 @[el2_lib.scala 162:48] + _T_39[5] <= _T_38 @[el2_lib.scala 162:48] + _T_39[6] <= _T_38 @[el2_lib.scala 162:48] + _T_39[7] <= _T_38 @[el2_lib.scala 162:48] + _T_39[8] <= _T_38 @[el2_lib.scala 162:48] + _T_39[9] <= _T_38 @[el2_lib.scala 162:48] + _T_39[10] <= _T_38 @[el2_lib.scala 162:48] + _T_39[11] <= _T_38 @[el2_lib.scala 162:48] + _T_39[12] <= _T_38 @[el2_lib.scala 162:48] + _T_39[13] <= _T_38 @[el2_lib.scala 162:48] + _T_39[14] <= _T_38 @[el2_lib.scala 162:48] + _T_39[15] <= _T_38 @[el2_lib.scala 162:48] + _T_39[16] <= _T_38 @[el2_lib.scala 162:48] + _T_39[17] <= _T_38 @[el2_lib.scala 162:48] + _T_39[18] <= _T_38 @[el2_lib.scala 162:48] + _T_39[19] <= _T_38 @[el2_lib.scala 162:48] + _T_39[20] <= _T_38 @[el2_lib.scala 162:48] + _T_39[21] <= _T_38 @[el2_lib.scala 162:48] + _T_39[22] <= _T_38 @[el2_lib.scala 162:48] + _T_39[23] <= _T_38 @[el2_lib.scala 162:48] + _T_39[24] <= _T_38 @[el2_lib.scala 162:48] + _T_39[25] <= _T_38 @[el2_lib.scala 162:48] + _T_39[26] <= _T_38 @[el2_lib.scala 162:48] + _T_39[27] <= _T_38 @[el2_lib.scala 162:48] + _T_39[28] <= _T_38 @[el2_lib.scala 162:48] + _T_39[29] <= _T_38 @[el2_lib.scala 162:48] + _T_39[30] <= _T_38 @[el2_lib.scala 162:48] + _T_39[31] <= _T_38 @[el2_lib.scala 162:48] node _T_40 = cat(_T_39[0], _T_39[1]) @[Cat.scala 29:58] node _T_41 = cat(_T_40, _T_39[2]) @[Cat.scala 29:58] node _T_42 = cat(_T_41, _T_39[3]) @[Cat.scala 29:58] @@ -140,44 +140,44 @@ circuit el2_dec_trigger : node _T_68 = cat(_T_67, _T_39[29]) @[Cat.scala 29:58] node _T_69 = cat(_T_68, _T_39[30]) @[Cat.scala 29:58] node _T_70 = cat(_T_69, _T_39[31]) @[Cat.scala 29:58] - node _T_71 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[el2_lsu_trigger.scala 15:177] + node _T_71 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[el2_dec_trigger.scala 14:177] node _T_72 = cat(io.dec_i0_pc_d, _T_71) @[Cat.scala 29:58] - node _T_73 = and(_T_70, _T_72) @[el2_lsu_trigger.scala 15:127] - node _T_74 = eq(io.trigger_pkt_any[2].select, UInt<1>("h00")) @[el2_lsu_trigger.scala 15:63] - node _T_75 = and(_T_74, io.trigger_pkt_any[2].execute) @[el2_lsu_trigger.scala 15:93] - wire _T_76 : UInt<1>[32] @[el2_lib.scala 177:24] - _T_76[0] <= _T_75 @[el2_lib.scala 177:24] - _T_76[1] <= _T_75 @[el2_lib.scala 177:24] - _T_76[2] <= _T_75 @[el2_lib.scala 177:24] - _T_76[3] <= _T_75 @[el2_lib.scala 177:24] - _T_76[4] <= _T_75 @[el2_lib.scala 177:24] - _T_76[5] <= _T_75 @[el2_lib.scala 177:24] - _T_76[6] <= _T_75 @[el2_lib.scala 177:24] - _T_76[7] <= _T_75 @[el2_lib.scala 177:24] - _T_76[8] <= _T_75 @[el2_lib.scala 177:24] - _T_76[9] <= _T_75 @[el2_lib.scala 177:24] - _T_76[10] <= _T_75 @[el2_lib.scala 177:24] - _T_76[11] <= _T_75 @[el2_lib.scala 177:24] - _T_76[12] <= _T_75 @[el2_lib.scala 177:24] - _T_76[13] <= _T_75 @[el2_lib.scala 177:24] - _T_76[14] <= _T_75 @[el2_lib.scala 177:24] - _T_76[15] <= _T_75 @[el2_lib.scala 177:24] - _T_76[16] <= _T_75 @[el2_lib.scala 177:24] - _T_76[17] <= _T_75 @[el2_lib.scala 177:24] - _T_76[18] <= _T_75 @[el2_lib.scala 177:24] - _T_76[19] <= _T_75 @[el2_lib.scala 177:24] - _T_76[20] <= _T_75 @[el2_lib.scala 177:24] - _T_76[21] <= _T_75 @[el2_lib.scala 177:24] - _T_76[22] <= _T_75 @[el2_lib.scala 177:24] - _T_76[23] <= _T_75 @[el2_lib.scala 177:24] - _T_76[24] <= _T_75 @[el2_lib.scala 177:24] - _T_76[25] <= _T_75 @[el2_lib.scala 177:24] - _T_76[26] <= _T_75 @[el2_lib.scala 177:24] - _T_76[27] <= _T_75 @[el2_lib.scala 177:24] - _T_76[28] <= _T_75 @[el2_lib.scala 177:24] - _T_76[29] <= _T_75 @[el2_lib.scala 177:24] - _T_76[30] <= _T_75 @[el2_lib.scala 177:24] - _T_76[31] <= _T_75 @[el2_lib.scala 177:24] + node _T_73 = and(_T_70, _T_72) @[el2_dec_trigger.scala 14:127] + node _T_74 = eq(io.trigger_pkt_any[2].select, UInt<1>("h00")) @[el2_dec_trigger.scala 14:63] + node _T_75 = and(_T_74, io.trigger_pkt_any[2].execute) @[el2_dec_trigger.scala 14:93] + wire _T_76 : UInt<1>[32] @[el2_lib.scala 162:48] + _T_76[0] <= _T_75 @[el2_lib.scala 162:48] + _T_76[1] <= _T_75 @[el2_lib.scala 162:48] + _T_76[2] <= _T_75 @[el2_lib.scala 162:48] + _T_76[3] <= _T_75 @[el2_lib.scala 162:48] + _T_76[4] <= _T_75 @[el2_lib.scala 162:48] + _T_76[5] <= _T_75 @[el2_lib.scala 162:48] + _T_76[6] <= _T_75 @[el2_lib.scala 162:48] + _T_76[7] <= _T_75 @[el2_lib.scala 162:48] + _T_76[8] <= _T_75 @[el2_lib.scala 162:48] + _T_76[9] <= _T_75 @[el2_lib.scala 162:48] + _T_76[10] <= _T_75 @[el2_lib.scala 162:48] + _T_76[11] <= _T_75 @[el2_lib.scala 162:48] + _T_76[12] <= _T_75 @[el2_lib.scala 162:48] + _T_76[13] <= _T_75 @[el2_lib.scala 162:48] + _T_76[14] <= _T_75 @[el2_lib.scala 162:48] + _T_76[15] <= _T_75 @[el2_lib.scala 162:48] + _T_76[16] <= _T_75 @[el2_lib.scala 162:48] + _T_76[17] <= _T_75 @[el2_lib.scala 162:48] + _T_76[18] <= _T_75 @[el2_lib.scala 162:48] + _T_76[19] <= _T_75 @[el2_lib.scala 162:48] + _T_76[20] <= _T_75 @[el2_lib.scala 162:48] + _T_76[21] <= _T_75 @[el2_lib.scala 162:48] + _T_76[22] <= _T_75 @[el2_lib.scala 162:48] + _T_76[23] <= _T_75 @[el2_lib.scala 162:48] + _T_76[24] <= _T_75 @[el2_lib.scala 162:48] + _T_76[25] <= _T_75 @[el2_lib.scala 162:48] + _T_76[26] <= _T_75 @[el2_lib.scala 162:48] + _T_76[27] <= _T_75 @[el2_lib.scala 162:48] + _T_76[28] <= _T_75 @[el2_lib.scala 162:48] + _T_76[29] <= _T_75 @[el2_lib.scala 162:48] + _T_76[30] <= _T_75 @[el2_lib.scala 162:48] + _T_76[31] <= _T_75 @[el2_lib.scala 162:48] node _T_77 = cat(_T_76[0], _T_76[1]) @[Cat.scala 29:58] node _T_78 = cat(_T_77, _T_76[2]) @[Cat.scala 29:58] node _T_79 = cat(_T_78, _T_76[3]) @[Cat.scala 29:58] @@ -209,44 +209,44 @@ circuit el2_dec_trigger : node _T_105 = cat(_T_104, _T_76[29]) @[Cat.scala 29:58] node _T_106 = cat(_T_105, _T_76[30]) @[Cat.scala 29:58] node _T_107 = cat(_T_106, _T_76[31]) @[Cat.scala 29:58] - node _T_108 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[el2_lsu_trigger.scala 15:177] + node _T_108 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[el2_dec_trigger.scala 14:177] node _T_109 = cat(io.dec_i0_pc_d, _T_108) @[Cat.scala 29:58] - node _T_110 = and(_T_107, _T_109) @[el2_lsu_trigger.scala 15:127] - node _T_111 = eq(io.trigger_pkt_any[3].select, UInt<1>("h00")) @[el2_lsu_trigger.scala 15:63] - node _T_112 = and(_T_111, io.trigger_pkt_any[3].execute) @[el2_lsu_trigger.scala 15:93] - wire _T_113 : UInt<1>[32] @[el2_lib.scala 177:24] - _T_113[0] <= _T_112 @[el2_lib.scala 177:24] - _T_113[1] <= _T_112 @[el2_lib.scala 177:24] - _T_113[2] <= _T_112 @[el2_lib.scala 177:24] - _T_113[3] <= _T_112 @[el2_lib.scala 177:24] - _T_113[4] <= _T_112 @[el2_lib.scala 177:24] - _T_113[5] <= _T_112 @[el2_lib.scala 177:24] - _T_113[6] <= _T_112 @[el2_lib.scala 177:24] - _T_113[7] <= _T_112 @[el2_lib.scala 177:24] - _T_113[8] <= _T_112 @[el2_lib.scala 177:24] - _T_113[9] <= _T_112 @[el2_lib.scala 177:24] - _T_113[10] <= _T_112 @[el2_lib.scala 177:24] - _T_113[11] <= _T_112 @[el2_lib.scala 177:24] - _T_113[12] <= _T_112 @[el2_lib.scala 177:24] - _T_113[13] <= _T_112 @[el2_lib.scala 177:24] - _T_113[14] <= _T_112 @[el2_lib.scala 177:24] - _T_113[15] <= _T_112 @[el2_lib.scala 177:24] - _T_113[16] <= _T_112 @[el2_lib.scala 177:24] - _T_113[17] <= _T_112 @[el2_lib.scala 177:24] - _T_113[18] <= _T_112 @[el2_lib.scala 177:24] - _T_113[19] <= _T_112 @[el2_lib.scala 177:24] - _T_113[20] <= _T_112 @[el2_lib.scala 177:24] - _T_113[21] <= _T_112 @[el2_lib.scala 177:24] - _T_113[22] <= _T_112 @[el2_lib.scala 177:24] - _T_113[23] <= _T_112 @[el2_lib.scala 177:24] - _T_113[24] <= _T_112 @[el2_lib.scala 177:24] - _T_113[25] <= _T_112 @[el2_lib.scala 177:24] - _T_113[26] <= _T_112 @[el2_lib.scala 177:24] - _T_113[27] <= _T_112 @[el2_lib.scala 177:24] - _T_113[28] <= _T_112 @[el2_lib.scala 177:24] - _T_113[29] <= _T_112 @[el2_lib.scala 177:24] - _T_113[30] <= _T_112 @[el2_lib.scala 177:24] - _T_113[31] <= _T_112 @[el2_lib.scala 177:24] + node _T_110 = and(_T_107, _T_109) @[el2_dec_trigger.scala 14:127] + node _T_111 = eq(io.trigger_pkt_any[3].select, UInt<1>("h00")) @[el2_dec_trigger.scala 14:63] + node _T_112 = and(_T_111, io.trigger_pkt_any[3].execute) @[el2_dec_trigger.scala 14:93] + wire _T_113 : UInt<1>[32] @[el2_lib.scala 162:48] + _T_113[0] <= _T_112 @[el2_lib.scala 162:48] + _T_113[1] <= _T_112 @[el2_lib.scala 162:48] + _T_113[2] <= _T_112 @[el2_lib.scala 162:48] + _T_113[3] <= _T_112 @[el2_lib.scala 162:48] + _T_113[4] <= _T_112 @[el2_lib.scala 162:48] + _T_113[5] <= _T_112 @[el2_lib.scala 162:48] + _T_113[6] <= _T_112 @[el2_lib.scala 162:48] + _T_113[7] <= _T_112 @[el2_lib.scala 162:48] + _T_113[8] <= _T_112 @[el2_lib.scala 162:48] + _T_113[9] <= _T_112 @[el2_lib.scala 162:48] + _T_113[10] <= _T_112 @[el2_lib.scala 162:48] + _T_113[11] <= _T_112 @[el2_lib.scala 162:48] + _T_113[12] <= _T_112 @[el2_lib.scala 162:48] + _T_113[13] <= _T_112 @[el2_lib.scala 162:48] + _T_113[14] <= _T_112 @[el2_lib.scala 162:48] + _T_113[15] <= _T_112 @[el2_lib.scala 162:48] + _T_113[16] <= _T_112 @[el2_lib.scala 162:48] + _T_113[17] <= _T_112 @[el2_lib.scala 162:48] + _T_113[18] <= _T_112 @[el2_lib.scala 162:48] + _T_113[19] <= _T_112 @[el2_lib.scala 162:48] + _T_113[20] <= _T_112 @[el2_lib.scala 162:48] + _T_113[21] <= _T_112 @[el2_lib.scala 162:48] + _T_113[22] <= _T_112 @[el2_lib.scala 162:48] + _T_113[23] <= _T_112 @[el2_lib.scala 162:48] + _T_113[24] <= _T_112 @[el2_lib.scala 162:48] + _T_113[25] <= _T_112 @[el2_lib.scala 162:48] + _T_113[26] <= _T_112 @[el2_lib.scala 162:48] + _T_113[27] <= _T_112 @[el2_lib.scala 162:48] + _T_113[28] <= _T_112 @[el2_lib.scala 162:48] + _T_113[29] <= _T_112 @[el2_lib.scala 162:48] + _T_113[30] <= _T_112 @[el2_lib.scala 162:48] + _T_113[31] <= _T_112 @[el2_lib.scala 162:48] node _T_114 = cat(_T_113[0], _T_113[1]) @[Cat.scala 29:58] node _T_115 = cat(_T_114, _T_113[2]) @[Cat.scala 29:58] node _T_116 = cat(_T_115, _T_113[3]) @[Cat.scala 29:58] @@ -278,1180 +278,1180 @@ circuit el2_dec_trigger : node _T_142 = cat(_T_141, _T_113[29]) @[Cat.scala 29:58] node _T_143 = cat(_T_142, _T_113[30]) @[Cat.scala 29:58] node _T_144 = cat(_T_143, _T_113[31]) @[Cat.scala 29:58] - node _T_145 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[el2_lsu_trigger.scala 15:177] + node _T_145 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[el2_dec_trigger.scala 14:177] node _T_146 = cat(io.dec_i0_pc_d, _T_145) @[Cat.scala 29:58] - node _T_147 = and(_T_144, _T_146) @[el2_lsu_trigger.scala 15:127] - wire dec_i0_match_data : UInt<32>[4] @[el2_lsu_trigger.scala 15:46] - dec_i0_match_data[0] <= _T_36 @[el2_lsu_trigger.scala 15:46] - dec_i0_match_data[1] <= _T_73 @[el2_lsu_trigger.scala 15:46] - dec_i0_match_data[2] <= _T_110 @[el2_lsu_trigger.scala 15:46] - dec_i0_match_data[3] <= _T_147 @[el2_lsu_trigger.scala 15:46] - node _T_148 = and(io.trigger_pkt_any[0].execute, io.trigger_pkt_any[0].m) @[el2_lsu_trigger.scala 16:83] - node _T_149 = bits(io.trigger_pkt_any[0].match_, 0, 0) @[el2_lsu_trigger.scala 16:213] - wire _T_150 : UInt<1>[32] @[el2_lib.scala 193:24] - node _T_151 = andr(io.trigger_pkt_any[0].tdata2) @[el2_lib.scala 194:45] - node _T_152 = not(_T_151) @[el2_lib.scala 194:39] - node _T_153 = and(_T_149, _T_152) @[el2_lib.scala 194:37] - node _T_154 = bits(io.trigger_pkt_any[0].tdata2, 0, 0) @[el2_lib.scala 195:48] - node _T_155 = bits(dec_i0_match_data[0], 0, 0) @[el2_lib.scala 195:60] - node _T_156 = eq(_T_154, _T_155) @[el2_lib.scala 195:52] - node _T_157 = or(_T_153, _T_156) @[el2_lib.scala 195:41] - _T_150[0] <= _T_157 @[el2_lib.scala 195:18] - node _T_158 = bits(io.trigger_pkt_any[0].tdata2, 0, 0) @[el2_lib.scala 197:30] - node _T_159 = andr(_T_158) @[el2_lib.scala 197:38] - node _T_160 = and(_T_159, _T_153) @[el2_lib.scala 197:43] - node _T_161 = bits(io.trigger_pkt_any[0].tdata2, 1, 1) @[el2_lib.scala 197:76] - node _T_162 = bits(dec_i0_match_data[0], 1, 1) @[el2_lib.scala 197:88] - node _T_163 = eq(_T_161, _T_162) @[el2_lib.scala 197:80] - node _T_164 = mux(_T_160, UInt<1>("h01"), _T_163) @[el2_lib.scala 197:25] - _T_150[1] <= _T_164 @[el2_lib.scala 197:19] - node _T_165 = bits(io.trigger_pkt_any[0].tdata2, 1, 0) @[el2_lib.scala 197:30] - node _T_166 = andr(_T_165) @[el2_lib.scala 197:38] - node _T_167 = and(_T_166, _T_153) @[el2_lib.scala 197:43] - node _T_168 = bits(io.trigger_pkt_any[0].tdata2, 2, 2) @[el2_lib.scala 197:76] - node _T_169 = bits(dec_i0_match_data[0], 2, 2) @[el2_lib.scala 197:88] - node _T_170 = eq(_T_168, _T_169) @[el2_lib.scala 197:80] - node _T_171 = mux(_T_167, UInt<1>("h01"), _T_170) @[el2_lib.scala 197:25] - _T_150[2] <= _T_171 @[el2_lib.scala 197:19] - node _T_172 = bits(io.trigger_pkt_any[0].tdata2, 2, 0) @[el2_lib.scala 197:30] - node _T_173 = andr(_T_172) @[el2_lib.scala 197:38] - node _T_174 = and(_T_173, _T_153) @[el2_lib.scala 197:43] - node _T_175 = bits(io.trigger_pkt_any[0].tdata2, 3, 3) @[el2_lib.scala 197:76] - node _T_176 = bits(dec_i0_match_data[0], 3, 3) @[el2_lib.scala 197:88] - node _T_177 = eq(_T_175, _T_176) @[el2_lib.scala 197:80] - node _T_178 = mux(_T_174, UInt<1>("h01"), _T_177) @[el2_lib.scala 197:25] - _T_150[3] <= _T_178 @[el2_lib.scala 197:19] - node _T_179 = bits(io.trigger_pkt_any[0].tdata2, 3, 0) @[el2_lib.scala 197:30] - node _T_180 = andr(_T_179) @[el2_lib.scala 197:38] - node _T_181 = and(_T_180, _T_153) @[el2_lib.scala 197:43] - node _T_182 = bits(io.trigger_pkt_any[0].tdata2, 4, 4) @[el2_lib.scala 197:76] - node _T_183 = bits(dec_i0_match_data[0], 4, 4) @[el2_lib.scala 197:88] - node _T_184 = eq(_T_182, _T_183) @[el2_lib.scala 197:80] - node _T_185 = mux(_T_181, UInt<1>("h01"), _T_184) @[el2_lib.scala 197:25] - _T_150[4] <= _T_185 @[el2_lib.scala 197:19] - node _T_186 = bits(io.trigger_pkt_any[0].tdata2, 4, 0) @[el2_lib.scala 197:30] - node _T_187 = andr(_T_186) @[el2_lib.scala 197:38] - node _T_188 = and(_T_187, _T_153) @[el2_lib.scala 197:43] - node _T_189 = bits(io.trigger_pkt_any[0].tdata2, 5, 5) @[el2_lib.scala 197:76] - node _T_190 = bits(dec_i0_match_data[0], 5, 5) @[el2_lib.scala 197:88] - node _T_191 = eq(_T_189, _T_190) @[el2_lib.scala 197:80] - node _T_192 = mux(_T_188, UInt<1>("h01"), _T_191) @[el2_lib.scala 197:25] - _T_150[5] <= _T_192 @[el2_lib.scala 197:19] - node _T_193 = bits(io.trigger_pkt_any[0].tdata2, 5, 0) @[el2_lib.scala 197:30] - node _T_194 = andr(_T_193) @[el2_lib.scala 197:38] - node _T_195 = and(_T_194, _T_153) @[el2_lib.scala 197:43] - node _T_196 = bits(io.trigger_pkt_any[0].tdata2, 6, 6) @[el2_lib.scala 197:76] - node _T_197 = bits(dec_i0_match_data[0], 6, 6) @[el2_lib.scala 197:88] - node _T_198 = eq(_T_196, _T_197) @[el2_lib.scala 197:80] - node _T_199 = mux(_T_195, UInt<1>("h01"), _T_198) @[el2_lib.scala 197:25] - _T_150[6] <= _T_199 @[el2_lib.scala 197:19] - node _T_200 = bits(io.trigger_pkt_any[0].tdata2, 6, 0) @[el2_lib.scala 197:30] - node _T_201 = andr(_T_200) @[el2_lib.scala 197:38] - node _T_202 = and(_T_201, _T_153) @[el2_lib.scala 197:43] - node _T_203 = bits(io.trigger_pkt_any[0].tdata2, 7, 7) @[el2_lib.scala 197:76] - node _T_204 = bits(dec_i0_match_data[0], 7, 7) @[el2_lib.scala 197:88] - node _T_205 = eq(_T_203, _T_204) @[el2_lib.scala 197:80] - node _T_206 = mux(_T_202, UInt<1>("h01"), _T_205) @[el2_lib.scala 197:25] - _T_150[7] <= _T_206 @[el2_lib.scala 197:19] - node _T_207 = bits(io.trigger_pkt_any[0].tdata2, 7, 0) @[el2_lib.scala 197:30] - node _T_208 = andr(_T_207) @[el2_lib.scala 197:38] - node _T_209 = and(_T_208, _T_153) @[el2_lib.scala 197:43] - node _T_210 = bits(io.trigger_pkt_any[0].tdata2, 8, 8) @[el2_lib.scala 197:76] - node _T_211 = bits(dec_i0_match_data[0], 8, 8) @[el2_lib.scala 197:88] - node _T_212 = eq(_T_210, _T_211) @[el2_lib.scala 197:80] - node _T_213 = mux(_T_209, UInt<1>("h01"), _T_212) @[el2_lib.scala 197:25] - _T_150[8] <= _T_213 @[el2_lib.scala 197:19] - node _T_214 = bits(io.trigger_pkt_any[0].tdata2, 8, 0) @[el2_lib.scala 197:30] - node _T_215 = andr(_T_214) @[el2_lib.scala 197:38] - node _T_216 = and(_T_215, _T_153) @[el2_lib.scala 197:43] - node _T_217 = bits(io.trigger_pkt_any[0].tdata2, 9, 9) @[el2_lib.scala 197:76] - node _T_218 = bits(dec_i0_match_data[0], 9, 9) @[el2_lib.scala 197:88] - node _T_219 = eq(_T_217, _T_218) @[el2_lib.scala 197:80] - node _T_220 = mux(_T_216, UInt<1>("h01"), _T_219) @[el2_lib.scala 197:25] - _T_150[9] <= _T_220 @[el2_lib.scala 197:19] - node _T_221 = bits(io.trigger_pkt_any[0].tdata2, 9, 0) @[el2_lib.scala 197:30] - node _T_222 = andr(_T_221) @[el2_lib.scala 197:38] - node _T_223 = and(_T_222, _T_153) @[el2_lib.scala 197:43] - node _T_224 = bits(io.trigger_pkt_any[0].tdata2, 10, 10) @[el2_lib.scala 197:76] - node _T_225 = bits(dec_i0_match_data[0], 10, 10) @[el2_lib.scala 197:88] - node _T_226 = eq(_T_224, _T_225) @[el2_lib.scala 197:80] - node _T_227 = mux(_T_223, UInt<1>("h01"), _T_226) @[el2_lib.scala 197:25] - _T_150[10] <= _T_227 @[el2_lib.scala 197:19] - node _T_228 = bits(io.trigger_pkt_any[0].tdata2, 10, 0) @[el2_lib.scala 197:30] - node _T_229 = andr(_T_228) @[el2_lib.scala 197:38] - node _T_230 = and(_T_229, _T_153) @[el2_lib.scala 197:43] - node _T_231 = bits(io.trigger_pkt_any[0].tdata2, 11, 11) @[el2_lib.scala 197:76] - node _T_232 = bits(dec_i0_match_data[0], 11, 11) @[el2_lib.scala 197:88] - node _T_233 = eq(_T_231, _T_232) @[el2_lib.scala 197:80] - node _T_234 = mux(_T_230, UInt<1>("h01"), _T_233) @[el2_lib.scala 197:25] - _T_150[11] <= _T_234 @[el2_lib.scala 197:19] - node _T_235 = bits(io.trigger_pkt_any[0].tdata2, 11, 0) @[el2_lib.scala 197:30] - node _T_236 = andr(_T_235) @[el2_lib.scala 197:38] - node _T_237 = and(_T_236, _T_153) @[el2_lib.scala 197:43] - node _T_238 = bits(io.trigger_pkt_any[0].tdata2, 12, 12) @[el2_lib.scala 197:76] - node _T_239 = bits(dec_i0_match_data[0], 12, 12) @[el2_lib.scala 197:88] - node _T_240 = eq(_T_238, _T_239) @[el2_lib.scala 197:80] - node _T_241 = mux(_T_237, UInt<1>("h01"), _T_240) @[el2_lib.scala 197:25] - _T_150[12] <= _T_241 @[el2_lib.scala 197:19] - node _T_242 = bits(io.trigger_pkt_any[0].tdata2, 12, 0) @[el2_lib.scala 197:30] - node _T_243 = andr(_T_242) @[el2_lib.scala 197:38] - node _T_244 = and(_T_243, _T_153) @[el2_lib.scala 197:43] - node _T_245 = bits(io.trigger_pkt_any[0].tdata2, 13, 13) @[el2_lib.scala 197:76] - node _T_246 = bits(dec_i0_match_data[0], 13, 13) @[el2_lib.scala 197:88] - node _T_247 = eq(_T_245, _T_246) @[el2_lib.scala 197:80] - node _T_248 = mux(_T_244, UInt<1>("h01"), _T_247) @[el2_lib.scala 197:25] - _T_150[13] <= _T_248 @[el2_lib.scala 197:19] - node _T_249 = bits(io.trigger_pkt_any[0].tdata2, 13, 0) @[el2_lib.scala 197:30] - node _T_250 = andr(_T_249) @[el2_lib.scala 197:38] - node _T_251 = and(_T_250, _T_153) @[el2_lib.scala 197:43] - node _T_252 = bits(io.trigger_pkt_any[0].tdata2, 14, 14) @[el2_lib.scala 197:76] - node _T_253 = bits(dec_i0_match_data[0], 14, 14) @[el2_lib.scala 197:88] - node _T_254 = eq(_T_252, _T_253) @[el2_lib.scala 197:80] - node _T_255 = mux(_T_251, UInt<1>("h01"), _T_254) @[el2_lib.scala 197:25] - _T_150[14] <= _T_255 @[el2_lib.scala 197:19] - node _T_256 = bits(io.trigger_pkt_any[0].tdata2, 14, 0) @[el2_lib.scala 197:30] - node _T_257 = andr(_T_256) @[el2_lib.scala 197:38] - node _T_258 = and(_T_257, _T_153) @[el2_lib.scala 197:43] - node _T_259 = bits(io.trigger_pkt_any[0].tdata2, 15, 15) @[el2_lib.scala 197:76] - node _T_260 = bits(dec_i0_match_data[0], 15, 15) @[el2_lib.scala 197:88] - node _T_261 = eq(_T_259, _T_260) @[el2_lib.scala 197:80] - node _T_262 = mux(_T_258, UInt<1>("h01"), _T_261) @[el2_lib.scala 197:25] - _T_150[15] <= _T_262 @[el2_lib.scala 197:19] - node _T_263 = bits(io.trigger_pkt_any[0].tdata2, 15, 0) @[el2_lib.scala 197:30] - node _T_264 = andr(_T_263) @[el2_lib.scala 197:38] - node _T_265 = and(_T_264, _T_153) @[el2_lib.scala 197:43] - node _T_266 = bits(io.trigger_pkt_any[0].tdata2, 16, 16) @[el2_lib.scala 197:76] - node _T_267 = bits(dec_i0_match_data[0], 16, 16) @[el2_lib.scala 197:88] - node _T_268 = eq(_T_266, _T_267) @[el2_lib.scala 197:80] - node _T_269 = mux(_T_265, UInt<1>("h01"), _T_268) @[el2_lib.scala 197:25] - _T_150[16] <= _T_269 @[el2_lib.scala 197:19] - node _T_270 = bits(io.trigger_pkt_any[0].tdata2, 16, 0) @[el2_lib.scala 197:30] - node _T_271 = andr(_T_270) @[el2_lib.scala 197:38] - node _T_272 = and(_T_271, _T_153) @[el2_lib.scala 197:43] - node _T_273 = bits(io.trigger_pkt_any[0].tdata2, 17, 17) @[el2_lib.scala 197:76] - node _T_274 = bits(dec_i0_match_data[0], 17, 17) @[el2_lib.scala 197:88] - node _T_275 = eq(_T_273, _T_274) @[el2_lib.scala 197:80] - node _T_276 = mux(_T_272, UInt<1>("h01"), _T_275) @[el2_lib.scala 197:25] - _T_150[17] <= _T_276 @[el2_lib.scala 197:19] - node _T_277 = bits(io.trigger_pkt_any[0].tdata2, 17, 0) @[el2_lib.scala 197:30] - node _T_278 = andr(_T_277) @[el2_lib.scala 197:38] - node _T_279 = and(_T_278, _T_153) @[el2_lib.scala 197:43] - node _T_280 = bits(io.trigger_pkt_any[0].tdata2, 18, 18) @[el2_lib.scala 197:76] - node _T_281 = bits(dec_i0_match_data[0], 18, 18) @[el2_lib.scala 197:88] - node _T_282 = eq(_T_280, _T_281) @[el2_lib.scala 197:80] - node _T_283 = mux(_T_279, UInt<1>("h01"), _T_282) @[el2_lib.scala 197:25] - _T_150[18] <= _T_283 @[el2_lib.scala 197:19] - node _T_284 = bits(io.trigger_pkt_any[0].tdata2, 18, 0) @[el2_lib.scala 197:30] - node _T_285 = andr(_T_284) @[el2_lib.scala 197:38] - node _T_286 = and(_T_285, _T_153) @[el2_lib.scala 197:43] - node _T_287 = bits(io.trigger_pkt_any[0].tdata2, 19, 19) @[el2_lib.scala 197:76] - node _T_288 = bits(dec_i0_match_data[0], 19, 19) @[el2_lib.scala 197:88] - node _T_289 = eq(_T_287, _T_288) @[el2_lib.scala 197:80] - node _T_290 = mux(_T_286, UInt<1>("h01"), _T_289) @[el2_lib.scala 197:25] - _T_150[19] <= _T_290 @[el2_lib.scala 197:19] - node _T_291 = bits(io.trigger_pkt_any[0].tdata2, 19, 0) @[el2_lib.scala 197:30] - node _T_292 = andr(_T_291) @[el2_lib.scala 197:38] - node _T_293 = and(_T_292, _T_153) @[el2_lib.scala 197:43] - node _T_294 = bits(io.trigger_pkt_any[0].tdata2, 20, 20) @[el2_lib.scala 197:76] - node _T_295 = bits(dec_i0_match_data[0], 20, 20) @[el2_lib.scala 197:88] - node _T_296 = eq(_T_294, _T_295) @[el2_lib.scala 197:80] - node _T_297 = mux(_T_293, UInt<1>("h01"), _T_296) @[el2_lib.scala 197:25] - _T_150[20] <= _T_297 @[el2_lib.scala 197:19] - node _T_298 = bits(io.trigger_pkt_any[0].tdata2, 20, 0) @[el2_lib.scala 197:30] - node _T_299 = andr(_T_298) @[el2_lib.scala 197:38] - node _T_300 = and(_T_299, _T_153) @[el2_lib.scala 197:43] - node _T_301 = bits(io.trigger_pkt_any[0].tdata2, 21, 21) @[el2_lib.scala 197:76] - node _T_302 = bits(dec_i0_match_data[0], 21, 21) @[el2_lib.scala 197:88] - node _T_303 = eq(_T_301, _T_302) @[el2_lib.scala 197:80] - node _T_304 = mux(_T_300, UInt<1>("h01"), _T_303) @[el2_lib.scala 197:25] - _T_150[21] <= _T_304 @[el2_lib.scala 197:19] - node _T_305 = bits(io.trigger_pkt_any[0].tdata2, 21, 0) @[el2_lib.scala 197:30] - node _T_306 = andr(_T_305) @[el2_lib.scala 197:38] - node _T_307 = and(_T_306, _T_153) @[el2_lib.scala 197:43] - node _T_308 = bits(io.trigger_pkt_any[0].tdata2, 22, 22) @[el2_lib.scala 197:76] - node _T_309 = bits(dec_i0_match_data[0], 22, 22) @[el2_lib.scala 197:88] - node _T_310 = eq(_T_308, _T_309) @[el2_lib.scala 197:80] - node _T_311 = mux(_T_307, UInt<1>("h01"), _T_310) @[el2_lib.scala 197:25] - _T_150[22] <= _T_311 @[el2_lib.scala 197:19] - node _T_312 = bits(io.trigger_pkt_any[0].tdata2, 22, 0) @[el2_lib.scala 197:30] - node _T_313 = andr(_T_312) @[el2_lib.scala 197:38] - node _T_314 = and(_T_313, _T_153) @[el2_lib.scala 197:43] - node _T_315 = bits(io.trigger_pkt_any[0].tdata2, 23, 23) @[el2_lib.scala 197:76] - node _T_316 = bits(dec_i0_match_data[0], 23, 23) @[el2_lib.scala 197:88] - node _T_317 = eq(_T_315, _T_316) @[el2_lib.scala 197:80] - node _T_318 = mux(_T_314, UInt<1>("h01"), _T_317) @[el2_lib.scala 197:25] - _T_150[23] <= _T_318 @[el2_lib.scala 197:19] - node _T_319 = bits(io.trigger_pkt_any[0].tdata2, 23, 0) @[el2_lib.scala 197:30] - node _T_320 = andr(_T_319) @[el2_lib.scala 197:38] - node _T_321 = and(_T_320, _T_153) @[el2_lib.scala 197:43] - node _T_322 = bits(io.trigger_pkt_any[0].tdata2, 24, 24) @[el2_lib.scala 197:76] - node _T_323 = bits(dec_i0_match_data[0], 24, 24) @[el2_lib.scala 197:88] - node _T_324 = eq(_T_322, _T_323) @[el2_lib.scala 197:80] - node _T_325 = mux(_T_321, UInt<1>("h01"), _T_324) @[el2_lib.scala 197:25] - _T_150[24] <= _T_325 @[el2_lib.scala 197:19] - node _T_326 = bits(io.trigger_pkt_any[0].tdata2, 24, 0) @[el2_lib.scala 197:30] - node _T_327 = andr(_T_326) @[el2_lib.scala 197:38] - node _T_328 = and(_T_327, _T_153) @[el2_lib.scala 197:43] - node _T_329 = bits(io.trigger_pkt_any[0].tdata2, 25, 25) @[el2_lib.scala 197:76] - node _T_330 = bits(dec_i0_match_data[0], 25, 25) @[el2_lib.scala 197:88] - node _T_331 = eq(_T_329, _T_330) @[el2_lib.scala 197:80] - node _T_332 = mux(_T_328, UInt<1>("h01"), _T_331) @[el2_lib.scala 197:25] - _T_150[25] <= _T_332 @[el2_lib.scala 197:19] - node _T_333 = bits(io.trigger_pkt_any[0].tdata2, 25, 0) @[el2_lib.scala 197:30] - node _T_334 = andr(_T_333) @[el2_lib.scala 197:38] - node _T_335 = and(_T_334, _T_153) @[el2_lib.scala 197:43] - node _T_336 = bits(io.trigger_pkt_any[0].tdata2, 26, 26) @[el2_lib.scala 197:76] - node _T_337 = bits(dec_i0_match_data[0], 26, 26) @[el2_lib.scala 197:88] - node _T_338 = eq(_T_336, _T_337) @[el2_lib.scala 197:80] - node _T_339 = mux(_T_335, UInt<1>("h01"), _T_338) @[el2_lib.scala 197:25] - _T_150[26] <= _T_339 @[el2_lib.scala 197:19] - node _T_340 = bits(io.trigger_pkt_any[0].tdata2, 26, 0) @[el2_lib.scala 197:30] - node _T_341 = andr(_T_340) @[el2_lib.scala 197:38] - node _T_342 = and(_T_341, _T_153) @[el2_lib.scala 197:43] - node _T_343 = bits(io.trigger_pkt_any[0].tdata2, 27, 27) @[el2_lib.scala 197:76] - node _T_344 = bits(dec_i0_match_data[0], 27, 27) @[el2_lib.scala 197:88] - node _T_345 = eq(_T_343, _T_344) @[el2_lib.scala 197:80] - node _T_346 = mux(_T_342, UInt<1>("h01"), _T_345) @[el2_lib.scala 197:25] - _T_150[27] <= _T_346 @[el2_lib.scala 197:19] - node _T_347 = bits(io.trigger_pkt_any[0].tdata2, 27, 0) @[el2_lib.scala 197:30] - node _T_348 = andr(_T_347) @[el2_lib.scala 197:38] - node _T_349 = and(_T_348, _T_153) @[el2_lib.scala 197:43] - node _T_350 = bits(io.trigger_pkt_any[0].tdata2, 28, 28) @[el2_lib.scala 197:76] - node _T_351 = bits(dec_i0_match_data[0], 28, 28) @[el2_lib.scala 197:88] - node _T_352 = eq(_T_350, _T_351) @[el2_lib.scala 197:80] - node _T_353 = mux(_T_349, UInt<1>("h01"), _T_352) @[el2_lib.scala 197:25] - _T_150[28] <= _T_353 @[el2_lib.scala 197:19] - node _T_354 = bits(io.trigger_pkt_any[0].tdata2, 28, 0) @[el2_lib.scala 197:30] - node _T_355 = andr(_T_354) @[el2_lib.scala 197:38] - node _T_356 = and(_T_355, _T_153) @[el2_lib.scala 197:43] - node _T_357 = bits(io.trigger_pkt_any[0].tdata2, 29, 29) @[el2_lib.scala 197:76] - node _T_358 = bits(dec_i0_match_data[0], 29, 29) @[el2_lib.scala 197:88] - node _T_359 = eq(_T_357, _T_358) @[el2_lib.scala 197:80] - node _T_360 = mux(_T_356, UInt<1>("h01"), _T_359) @[el2_lib.scala 197:25] - _T_150[29] <= _T_360 @[el2_lib.scala 197:19] - node _T_361 = bits(io.trigger_pkt_any[0].tdata2, 29, 0) @[el2_lib.scala 197:30] - node _T_362 = andr(_T_361) @[el2_lib.scala 197:38] - node _T_363 = and(_T_362, _T_153) @[el2_lib.scala 197:43] - node _T_364 = bits(io.trigger_pkt_any[0].tdata2, 30, 30) @[el2_lib.scala 197:76] - node _T_365 = bits(dec_i0_match_data[0], 30, 30) @[el2_lib.scala 197:88] - node _T_366 = eq(_T_364, _T_365) @[el2_lib.scala 197:80] - node _T_367 = mux(_T_363, UInt<1>("h01"), _T_366) @[el2_lib.scala 197:25] - _T_150[30] <= _T_367 @[el2_lib.scala 197:19] - node _T_368 = bits(io.trigger_pkt_any[0].tdata2, 30, 0) @[el2_lib.scala 197:30] - node _T_369 = andr(_T_368) @[el2_lib.scala 197:38] - node _T_370 = and(_T_369, _T_153) @[el2_lib.scala 197:43] - node _T_371 = bits(io.trigger_pkt_any[0].tdata2, 31, 31) @[el2_lib.scala 197:76] - node _T_372 = bits(dec_i0_match_data[0], 31, 31) @[el2_lib.scala 197:88] - node _T_373 = eq(_T_371, _T_372) @[el2_lib.scala 197:80] - node _T_374 = mux(_T_370, UInt<1>("h01"), _T_373) @[el2_lib.scala 197:25] - _T_150[31] <= _T_374 @[el2_lib.scala 197:19] - node _T_375 = and(_T_150[0], _T_150[1]) @[el2_lib.scala 198:22] - node _T_376 = and(_T_375, _T_150[2]) @[el2_lib.scala 198:22] - node _T_377 = and(_T_376, _T_150[3]) @[el2_lib.scala 198:22] - node _T_378 = and(_T_377, _T_150[4]) @[el2_lib.scala 198:22] - node _T_379 = and(_T_378, _T_150[5]) @[el2_lib.scala 198:22] - node _T_380 = and(_T_379, _T_150[6]) @[el2_lib.scala 198:22] - node _T_381 = and(_T_380, _T_150[7]) @[el2_lib.scala 198:22] - node _T_382 = and(_T_381, _T_150[8]) @[el2_lib.scala 198:22] - node _T_383 = and(_T_382, _T_150[9]) @[el2_lib.scala 198:22] - node _T_384 = and(_T_383, _T_150[10]) @[el2_lib.scala 198:22] - node _T_385 = and(_T_384, _T_150[11]) @[el2_lib.scala 198:22] - node _T_386 = and(_T_385, _T_150[12]) @[el2_lib.scala 198:22] - node _T_387 = and(_T_386, _T_150[13]) @[el2_lib.scala 198:22] - node _T_388 = and(_T_387, _T_150[14]) @[el2_lib.scala 198:22] - node _T_389 = and(_T_388, _T_150[15]) @[el2_lib.scala 198:22] - node _T_390 = and(_T_389, _T_150[16]) @[el2_lib.scala 198:22] - node _T_391 = and(_T_390, _T_150[17]) @[el2_lib.scala 198:22] - node _T_392 = and(_T_391, _T_150[18]) @[el2_lib.scala 198:22] - node _T_393 = and(_T_392, _T_150[19]) @[el2_lib.scala 198:22] - node _T_394 = and(_T_393, _T_150[20]) @[el2_lib.scala 198:22] - node _T_395 = and(_T_394, _T_150[21]) @[el2_lib.scala 198:22] - node _T_396 = and(_T_395, _T_150[22]) @[el2_lib.scala 198:22] - node _T_397 = and(_T_396, _T_150[23]) @[el2_lib.scala 198:22] - node _T_398 = and(_T_397, _T_150[24]) @[el2_lib.scala 198:22] - node _T_399 = and(_T_398, _T_150[25]) @[el2_lib.scala 198:22] - node _T_400 = and(_T_399, _T_150[26]) @[el2_lib.scala 198:22] - node _T_401 = and(_T_400, _T_150[27]) @[el2_lib.scala 198:22] - node _T_402 = and(_T_401, _T_150[28]) @[el2_lib.scala 198:22] - node _T_403 = and(_T_402, _T_150[29]) @[el2_lib.scala 198:22] - node _T_404 = and(_T_403, _T_150[30]) @[el2_lib.scala 198:22] - node _T_405 = and(_T_404, _T_150[31]) @[el2_lib.scala 198:22] - node _T_406 = and(_T_148, _T_405) @[el2_lsu_trigger.scala 16:109] - node _T_407 = and(io.trigger_pkt_any[1].execute, io.trigger_pkt_any[1].m) @[el2_lsu_trigger.scala 16:83] - node _T_408 = bits(io.trigger_pkt_any[1].match_, 0, 0) @[el2_lsu_trigger.scala 16:213] - wire _T_409 : UInt<1>[32] @[el2_lib.scala 193:24] - node _T_410 = andr(io.trigger_pkt_any[1].tdata2) @[el2_lib.scala 194:45] - node _T_411 = not(_T_410) @[el2_lib.scala 194:39] - node _T_412 = and(_T_408, _T_411) @[el2_lib.scala 194:37] - node _T_413 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[el2_lib.scala 195:48] - node _T_414 = bits(dec_i0_match_data[1], 0, 0) @[el2_lib.scala 195:60] - node _T_415 = eq(_T_413, _T_414) @[el2_lib.scala 195:52] - node _T_416 = or(_T_412, _T_415) @[el2_lib.scala 195:41] - _T_409[0] <= _T_416 @[el2_lib.scala 195:18] - node _T_417 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[el2_lib.scala 197:30] - node _T_418 = andr(_T_417) @[el2_lib.scala 197:38] - node _T_419 = and(_T_418, _T_412) @[el2_lib.scala 197:43] - node _T_420 = bits(io.trigger_pkt_any[1].tdata2, 1, 1) @[el2_lib.scala 197:76] - node _T_421 = bits(dec_i0_match_data[1], 1, 1) @[el2_lib.scala 197:88] - node _T_422 = eq(_T_420, _T_421) @[el2_lib.scala 197:80] - node _T_423 = mux(_T_419, UInt<1>("h01"), _T_422) @[el2_lib.scala 197:25] - _T_409[1] <= _T_423 @[el2_lib.scala 197:19] - node _T_424 = bits(io.trigger_pkt_any[1].tdata2, 1, 0) @[el2_lib.scala 197:30] - node _T_425 = andr(_T_424) @[el2_lib.scala 197:38] - node _T_426 = and(_T_425, _T_412) @[el2_lib.scala 197:43] - node _T_427 = bits(io.trigger_pkt_any[1].tdata2, 2, 2) @[el2_lib.scala 197:76] - node _T_428 = bits(dec_i0_match_data[1], 2, 2) @[el2_lib.scala 197:88] - node _T_429 = eq(_T_427, _T_428) @[el2_lib.scala 197:80] - node _T_430 = mux(_T_426, UInt<1>("h01"), _T_429) @[el2_lib.scala 197:25] - _T_409[2] <= _T_430 @[el2_lib.scala 197:19] - node _T_431 = bits(io.trigger_pkt_any[1].tdata2, 2, 0) @[el2_lib.scala 197:30] - node _T_432 = andr(_T_431) @[el2_lib.scala 197:38] - node _T_433 = and(_T_432, _T_412) @[el2_lib.scala 197:43] - node _T_434 = bits(io.trigger_pkt_any[1].tdata2, 3, 3) @[el2_lib.scala 197:76] - node _T_435 = bits(dec_i0_match_data[1], 3, 3) @[el2_lib.scala 197:88] - node _T_436 = eq(_T_434, _T_435) @[el2_lib.scala 197:80] - node _T_437 = mux(_T_433, UInt<1>("h01"), _T_436) @[el2_lib.scala 197:25] - _T_409[3] <= _T_437 @[el2_lib.scala 197:19] - node _T_438 = bits(io.trigger_pkt_any[1].tdata2, 3, 0) @[el2_lib.scala 197:30] - node _T_439 = andr(_T_438) @[el2_lib.scala 197:38] - node _T_440 = and(_T_439, _T_412) @[el2_lib.scala 197:43] - node _T_441 = bits(io.trigger_pkt_any[1].tdata2, 4, 4) @[el2_lib.scala 197:76] - node _T_442 = bits(dec_i0_match_data[1], 4, 4) @[el2_lib.scala 197:88] - node _T_443 = eq(_T_441, _T_442) @[el2_lib.scala 197:80] - node _T_444 = mux(_T_440, UInt<1>("h01"), _T_443) @[el2_lib.scala 197:25] - _T_409[4] <= _T_444 @[el2_lib.scala 197:19] - node _T_445 = bits(io.trigger_pkt_any[1].tdata2, 4, 0) @[el2_lib.scala 197:30] - node _T_446 = andr(_T_445) @[el2_lib.scala 197:38] - node _T_447 = and(_T_446, _T_412) @[el2_lib.scala 197:43] - node _T_448 = bits(io.trigger_pkt_any[1].tdata2, 5, 5) @[el2_lib.scala 197:76] - node _T_449 = bits(dec_i0_match_data[1], 5, 5) @[el2_lib.scala 197:88] - node _T_450 = eq(_T_448, _T_449) @[el2_lib.scala 197:80] - node _T_451 = mux(_T_447, UInt<1>("h01"), _T_450) @[el2_lib.scala 197:25] - _T_409[5] <= _T_451 @[el2_lib.scala 197:19] - node _T_452 = bits(io.trigger_pkt_any[1].tdata2, 5, 0) @[el2_lib.scala 197:30] - node _T_453 = andr(_T_452) @[el2_lib.scala 197:38] - node _T_454 = and(_T_453, _T_412) @[el2_lib.scala 197:43] - node _T_455 = bits(io.trigger_pkt_any[1].tdata2, 6, 6) @[el2_lib.scala 197:76] - node _T_456 = bits(dec_i0_match_data[1], 6, 6) @[el2_lib.scala 197:88] - node _T_457 = eq(_T_455, _T_456) @[el2_lib.scala 197:80] - node _T_458 = mux(_T_454, UInt<1>("h01"), _T_457) @[el2_lib.scala 197:25] - _T_409[6] <= _T_458 @[el2_lib.scala 197:19] - node _T_459 = bits(io.trigger_pkt_any[1].tdata2, 6, 0) @[el2_lib.scala 197:30] - node _T_460 = andr(_T_459) @[el2_lib.scala 197:38] - node _T_461 = and(_T_460, _T_412) @[el2_lib.scala 197:43] - node _T_462 = bits(io.trigger_pkt_any[1].tdata2, 7, 7) @[el2_lib.scala 197:76] - node _T_463 = bits(dec_i0_match_data[1], 7, 7) @[el2_lib.scala 197:88] - node _T_464 = eq(_T_462, _T_463) @[el2_lib.scala 197:80] - node _T_465 = mux(_T_461, UInt<1>("h01"), _T_464) @[el2_lib.scala 197:25] - _T_409[7] <= _T_465 @[el2_lib.scala 197:19] - node _T_466 = bits(io.trigger_pkt_any[1].tdata2, 7, 0) @[el2_lib.scala 197:30] - node _T_467 = andr(_T_466) @[el2_lib.scala 197:38] - node _T_468 = and(_T_467, _T_412) @[el2_lib.scala 197:43] - node _T_469 = bits(io.trigger_pkt_any[1].tdata2, 8, 8) @[el2_lib.scala 197:76] - node _T_470 = bits(dec_i0_match_data[1], 8, 8) @[el2_lib.scala 197:88] - node _T_471 = eq(_T_469, _T_470) @[el2_lib.scala 197:80] - node _T_472 = mux(_T_468, UInt<1>("h01"), _T_471) @[el2_lib.scala 197:25] - _T_409[8] <= _T_472 @[el2_lib.scala 197:19] - node _T_473 = bits(io.trigger_pkt_any[1].tdata2, 8, 0) @[el2_lib.scala 197:30] - node _T_474 = andr(_T_473) @[el2_lib.scala 197:38] - node _T_475 = and(_T_474, _T_412) @[el2_lib.scala 197:43] - node _T_476 = bits(io.trigger_pkt_any[1].tdata2, 9, 9) @[el2_lib.scala 197:76] - node _T_477 = bits(dec_i0_match_data[1], 9, 9) @[el2_lib.scala 197:88] - node _T_478 = eq(_T_476, _T_477) @[el2_lib.scala 197:80] - node _T_479 = mux(_T_475, UInt<1>("h01"), _T_478) @[el2_lib.scala 197:25] - _T_409[9] <= _T_479 @[el2_lib.scala 197:19] - node _T_480 = bits(io.trigger_pkt_any[1].tdata2, 9, 0) @[el2_lib.scala 197:30] - node _T_481 = andr(_T_480) @[el2_lib.scala 197:38] - node _T_482 = and(_T_481, _T_412) @[el2_lib.scala 197:43] - node _T_483 = bits(io.trigger_pkt_any[1].tdata2, 10, 10) @[el2_lib.scala 197:76] - node _T_484 = bits(dec_i0_match_data[1], 10, 10) @[el2_lib.scala 197:88] - node _T_485 = eq(_T_483, _T_484) @[el2_lib.scala 197:80] - node _T_486 = mux(_T_482, UInt<1>("h01"), _T_485) @[el2_lib.scala 197:25] - _T_409[10] <= _T_486 @[el2_lib.scala 197:19] - node _T_487 = bits(io.trigger_pkt_any[1].tdata2, 10, 0) @[el2_lib.scala 197:30] - node _T_488 = andr(_T_487) @[el2_lib.scala 197:38] - node _T_489 = and(_T_488, _T_412) @[el2_lib.scala 197:43] - node _T_490 = bits(io.trigger_pkt_any[1].tdata2, 11, 11) @[el2_lib.scala 197:76] - node _T_491 = bits(dec_i0_match_data[1], 11, 11) @[el2_lib.scala 197:88] - node _T_492 = eq(_T_490, _T_491) @[el2_lib.scala 197:80] - node _T_493 = mux(_T_489, UInt<1>("h01"), _T_492) @[el2_lib.scala 197:25] - _T_409[11] <= _T_493 @[el2_lib.scala 197:19] - node _T_494 = bits(io.trigger_pkt_any[1].tdata2, 11, 0) @[el2_lib.scala 197:30] - node _T_495 = andr(_T_494) @[el2_lib.scala 197:38] - node _T_496 = and(_T_495, _T_412) @[el2_lib.scala 197:43] - node _T_497 = bits(io.trigger_pkt_any[1].tdata2, 12, 12) @[el2_lib.scala 197:76] - node _T_498 = bits(dec_i0_match_data[1], 12, 12) @[el2_lib.scala 197:88] - node _T_499 = eq(_T_497, _T_498) @[el2_lib.scala 197:80] - node _T_500 = mux(_T_496, UInt<1>("h01"), _T_499) @[el2_lib.scala 197:25] - _T_409[12] <= _T_500 @[el2_lib.scala 197:19] - node _T_501 = bits(io.trigger_pkt_any[1].tdata2, 12, 0) @[el2_lib.scala 197:30] - node _T_502 = andr(_T_501) @[el2_lib.scala 197:38] - node _T_503 = and(_T_502, _T_412) @[el2_lib.scala 197:43] - node _T_504 = bits(io.trigger_pkt_any[1].tdata2, 13, 13) @[el2_lib.scala 197:76] - node _T_505 = bits(dec_i0_match_data[1], 13, 13) @[el2_lib.scala 197:88] - node _T_506 = eq(_T_504, _T_505) @[el2_lib.scala 197:80] - node _T_507 = mux(_T_503, UInt<1>("h01"), _T_506) @[el2_lib.scala 197:25] - _T_409[13] <= _T_507 @[el2_lib.scala 197:19] - node _T_508 = bits(io.trigger_pkt_any[1].tdata2, 13, 0) @[el2_lib.scala 197:30] - node _T_509 = andr(_T_508) @[el2_lib.scala 197:38] - node _T_510 = and(_T_509, _T_412) @[el2_lib.scala 197:43] - node _T_511 = bits(io.trigger_pkt_any[1].tdata2, 14, 14) @[el2_lib.scala 197:76] - node _T_512 = bits(dec_i0_match_data[1], 14, 14) @[el2_lib.scala 197:88] - node _T_513 = eq(_T_511, _T_512) @[el2_lib.scala 197:80] - node _T_514 = mux(_T_510, UInt<1>("h01"), _T_513) @[el2_lib.scala 197:25] - _T_409[14] <= _T_514 @[el2_lib.scala 197:19] - node _T_515 = bits(io.trigger_pkt_any[1].tdata2, 14, 0) @[el2_lib.scala 197:30] - node _T_516 = andr(_T_515) @[el2_lib.scala 197:38] - node _T_517 = and(_T_516, _T_412) @[el2_lib.scala 197:43] - node _T_518 = bits(io.trigger_pkt_any[1].tdata2, 15, 15) @[el2_lib.scala 197:76] - node _T_519 = bits(dec_i0_match_data[1], 15, 15) @[el2_lib.scala 197:88] - node _T_520 = eq(_T_518, _T_519) @[el2_lib.scala 197:80] - node _T_521 = mux(_T_517, UInt<1>("h01"), _T_520) @[el2_lib.scala 197:25] - _T_409[15] <= _T_521 @[el2_lib.scala 197:19] - node _T_522 = bits(io.trigger_pkt_any[1].tdata2, 15, 0) @[el2_lib.scala 197:30] - node _T_523 = andr(_T_522) @[el2_lib.scala 197:38] - node _T_524 = and(_T_523, _T_412) @[el2_lib.scala 197:43] - node _T_525 = bits(io.trigger_pkt_any[1].tdata2, 16, 16) @[el2_lib.scala 197:76] - node _T_526 = bits(dec_i0_match_data[1], 16, 16) @[el2_lib.scala 197:88] - node _T_527 = eq(_T_525, _T_526) @[el2_lib.scala 197:80] - node _T_528 = mux(_T_524, UInt<1>("h01"), _T_527) @[el2_lib.scala 197:25] - _T_409[16] <= _T_528 @[el2_lib.scala 197:19] - node _T_529 = bits(io.trigger_pkt_any[1].tdata2, 16, 0) @[el2_lib.scala 197:30] - node _T_530 = andr(_T_529) @[el2_lib.scala 197:38] - node _T_531 = and(_T_530, _T_412) @[el2_lib.scala 197:43] - node _T_532 = bits(io.trigger_pkt_any[1].tdata2, 17, 17) @[el2_lib.scala 197:76] - node _T_533 = bits(dec_i0_match_data[1], 17, 17) @[el2_lib.scala 197:88] - node _T_534 = eq(_T_532, _T_533) @[el2_lib.scala 197:80] - node _T_535 = mux(_T_531, UInt<1>("h01"), _T_534) @[el2_lib.scala 197:25] - _T_409[17] <= _T_535 @[el2_lib.scala 197:19] - node _T_536 = bits(io.trigger_pkt_any[1].tdata2, 17, 0) @[el2_lib.scala 197:30] - node _T_537 = andr(_T_536) @[el2_lib.scala 197:38] - node _T_538 = and(_T_537, _T_412) @[el2_lib.scala 197:43] - node _T_539 = bits(io.trigger_pkt_any[1].tdata2, 18, 18) @[el2_lib.scala 197:76] - node _T_540 = bits(dec_i0_match_data[1], 18, 18) @[el2_lib.scala 197:88] - node _T_541 = eq(_T_539, _T_540) @[el2_lib.scala 197:80] - node _T_542 = mux(_T_538, UInt<1>("h01"), _T_541) @[el2_lib.scala 197:25] - _T_409[18] <= _T_542 @[el2_lib.scala 197:19] - node _T_543 = bits(io.trigger_pkt_any[1].tdata2, 18, 0) @[el2_lib.scala 197:30] - node _T_544 = andr(_T_543) @[el2_lib.scala 197:38] - node _T_545 = and(_T_544, _T_412) @[el2_lib.scala 197:43] - node _T_546 = bits(io.trigger_pkt_any[1].tdata2, 19, 19) @[el2_lib.scala 197:76] - node _T_547 = bits(dec_i0_match_data[1], 19, 19) @[el2_lib.scala 197:88] - node _T_548 = eq(_T_546, _T_547) @[el2_lib.scala 197:80] - node _T_549 = mux(_T_545, UInt<1>("h01"), _T_548) @[el2_lib.scala 197:25] - _T_409[19] <= _T_549 @[el2_lib.scala 197:19] - node _T_550 = bits(io.trigger_pkt_any[1].tdata2, 19, 0) @[el2_lib.scala 197:30] - node _T_551 = andr(_T_550) @[el2_lib.scala 197:38] - node _T_552 = and(_T_551, _T_412) @[el2_lib.scala 197:43] - node _T_553 = bits(io.trigger_pkt_any[1].tdata2, 20, 20) @[el2_lib.scala 197:76] - node _T_554 = bits(dec_i0_match_data[1], 20, 20) @[el2_lib.scala 197:88] - node _T_555 = eq(_T_553, _T_554) @[el2_lib.scala 197:80] - node _T_556 = mux(_T_552, UInt<1>("h01"), _T_555) @[el2_lib.scala 197:25] - _T_409[20] <= _T_556 @[el2_lib.scala 197:19] - node _T_557 = bits(io.trigger_pkt_any[1].tdata2, 20, 0) @[el2_lib.scala 197:30] - node _T_558 = andr(_T_557) @[el2_lib.scala 197:38] - node _T_559 = and(_T_558, _T_412) @[el2_lib.scala 197:43] - node _T_560 = bits(io.trigger_pkt_any[1].tdata2, 21, 21) @[el2_lib.scala 197:76] - node _T_561 = bits(dec_i0_match_data[1], 21, 21) @[el2_lib.scala 197:88] - node _T_562 = eq(_T_560, _T_561) @[el2_lib.scala 197:80] - node _T_563 = mux(_T_559, UInt<1>("h01"), _T_562) @[el2_lib.scala 197:25] - _T_409[21] <= _T_563 @[el2_lib.scala 197:19] - node _T_564 = bits(io.trigger_pkt_any[1].tdata2, 21, 0) @[el2_lib.scala 197:30] - node _T_565 = andr(_T_564) @[el2_lib.scala 197:38] - node _T_566 = and(_T_565, _T_412) @[el2_lib.scala 197:43] - node _T_567 = bits(io.trigger_pkt_any[1].tdata2, 22, 22) @[el2_lib.scala 197:76] - node _T_568 = bits(dec_i0_match_data[1], 22, 22) @[el2_lib.scala 197:88] - node _T_569 = eq(_T_567, _T_568) @[el2_lib.scala 197:80] - node _T_570 = mux(_T_566, UInt<1>("h01"), _T_569) @[el2_lib.scala 197:25] - _T_409[22] <= _T_570 @[el2_lib.scala 197:19] - node _T_571 = bits(io.trigger_pkt_any[1].tdata2, 22, 0) @[el2_lib.scala 197:30] - node _T_572 = andr(_T_571) @[el2_lib.scala 197:38] - node _T_573 = and(_T_572, _T_412) @[el2_lib.scala 197:43] - node _T_574 = bits(io.trigger_pkt_any[1].tdata2, 23, 23) @[el2_lib.scala 197:76] - node _T_575 = bits(dec_i0_match_data[1], 23, 23) @[el2_lib.scala 197:88] - node _T_576 = eq(_T_574, _T_575) @[el2_lib.scala 197:80] - node _T_577 = mux(_T_573, UInt<1>("h01"), _T_576) @[el2_lib.scala 197:25] - _T_409[23] <= _T_577 @[el2_lib.scala 197:19] - node _T_578 = bits(io.trigger_pkt_any[1].tdata2, 23, 0) @[el2_lib.scala 197:30] - node _T_579 = andr(_T_578) @[el2_lib.scala 197:38] - node _T_580 = and(_T_579, _T_412) @[el2_lib.scala 197:43] - node _T_581 = bits(io.trigger_pkt_any[1].tdata2, 24, 24) @[el2_lib.scala 197:76] - node _T_582 = bits(dec_i0_match_data[1], 24, 24) @[el2_lib.scala 197:88] - node _T_583 = eq(_T_581, _T_582) @[el2_lib.scala 197:80] - node _T_584 = mux(_T_580, UInt<1>("h01"), _T_583) @[el2_lib.scala 197:25] - _T_409[24] <= _T_584 @[el2_lib.scala 197:19] - node _T_585 = bits(io.trigger_pkt_any[1].tdata2, 24, 0) @[el2_lib.scala 197:30] - node _T_586 = andr(_T_585) @[el2_lib.scala 197:38] - node _T_587 = and(_T_586, _T_412) @[el2_lib.scala 197:43] - node _T_588 = bits(io.trigger_pkt_any[1].tdata2, 25, 25) @[el2_lib.scala 197:76] - node _T_589 = bits(dec_i0_match_data[1], 25, 25) @[el2_lib.scala 197:88] - node _T_590 = eq(_T_588, _T_589) @[el2_lib.scala 197:80] - node _T_591 = mux(_T_587, UInt<1>("h01"), _T_590) @[el2_lib.scala 197:25] - _T_409[25] <= _T_591 @[el2_lib.scala 197:19] - node _T_592 = bits(io.trigger_pkt_any[1].tdata2, 25, 0) @[el2_lib.scala 197:30] - node _T_593 = andr(_T_592) @[el2_lib.scala 197:38] - node _T_594 = and(_T_593, _T_412) @[el2_lib.scala 197:43] - node _T_595 = bits(io.trigger_pkt_any[1].tdata2, 26, 26) @[el2_lib.scala 197:76] - node _T_596 = bits(dec_i0_match_data[1], 26, 26) @[el2_lib.scala 197:88] - node _T_597 = eq(_T_595, _T_596) @[el2_lib.scala 197:80] - node _T_598 = mux(_T_594, UInt<1>("h01"), _T_597) @[el2_lib.scala 197:25] - _T_409[26] <= _T_598 @[el2_lib.scala 197:19] - node _T_599 = bits(io.trigger_pkt_any[1].tdata2, 26, 0) @[el2_lib.scala 197:30] - node _T_600 = andr(_T_599) @[el2_lib.scala 197:38] - node _T_601 = and(_T_600, _T_412) @[el2_lib.scala 197:43] - node _T_602 = bits(io.trigger_pkt_any[1].tdata2, 27, 27) @[el2_lib.scala 197:76] - node _T_603 = bits(dec_i0_match_data[1], 27, 27) @[el2_lib.scala 197:88] - node _T_604 = eq(_T_602, _T_603) @[el2_lib.scala 197:80] - node _T_605 = mux(_T_601, UInt<1>("h01"), _T_604) @[el2_lib.scala 197:25] - _T_409[27] <= _T_605 @[el2_lib.scala 197:19] - node _T_606 = bits(io.trigger_pkt_any[1].tdata2, 27, 0) @[el2_lib.scala 197:30] - node _T_607 = andr(_T_606) @[el2_lib.scala 197:38] - node _T_608 = and(_T_607, _T_412) @[el2_lib.scala 197:43] - node _T_609 = bits(io.trigger_pkt_any[1].tdata2, 28, 28) @[el2_lib.scala 197:76] - node _T_610 = bits(dec_i0_match_data[1], 28, 28) @[el2_lib.scala 197:88] - node _T_611 = eq(_T_609, _T_610) @[el2_lib.scala 197:80] - node _T_612 = mux(_T_608, UInt<1>("h01"), _T_611) @[el2_lib.scala 197:25] - _T_409[28] <= _T_612 @[el2_lib.scala 197:19] - node _T_613 = bits(io.trigger_pkt_any[1].tdata2, 28, 0) @[el2_lib.scala 197:30] - node _T_614 = andr(_T_613) @[el2_lib.scala 197:38] - node _T_615 = and(_T_614, _T_412) @[el2_lib.scala 197:43] - node _T_616 = bits(io.trigger_pkt_any[1].tdata2, 29, 29) @[el2_lib.scala 197:76] - node _T_617 = bits(dec_i0_match_data[1], 29, 29) @[el2_lib.scala 197:88] - node _T_618 = eq(_T_616, _T_617) @[el2_lib.scala 197:80] - node _T_619 = mux(_T_615, UInt<1>("h01"), _T_618) @[el2_lib.scala 197:25] - _T_409[29] <= _T_619 @[el2_lib.scala 197:19] - node _T_620 = bits(io.trigger_pkt_any[1].tdata2, 29, 0) @[el2_lib.scala 197:30] - node _T_621 = andr(_T_620) @[el2_lib.scala 197:38] - node _T_622 = and(_T_621, _T_412) @[el2_lib.scala 197:43] - node _T_623 = bits(io.trigger_pkt_any[1].tdata2, 30, 30) @[el2_lib.scala 197:76] - node _T_624 = bits(dec_i0_match_data[1], 30, 30) @[el2_lib.scala 197:88] - node _T_625 = eq(_T_623, _T_624) @[el2_lib.scala 197:80] - node _T_626 = mux(_T_622, UInt<1>("h01"), _T_625) @[el2_lib.scala 197:25] - _T_409[30] <= _T_626 @[el2_lib.scala 197:19] - node _T_627 = bits(io.trigger_pkt_any[1].tdata2, 30, 0) @[el2_lib.scala 197:30] - node _T_628 = andr(_T_627) @[el2_lib.scala 197:38] - node _T_629 = and(_T_628, _T_412) @[el2_lib.scala 197:43] - node _T_630 = bits(io.trigger_pkt_any[1].tdata2, 31, 31) @[el2_lib.scala 197:76] - node _T_631 = bits(dec_i0_match_data[1], 31, 31) @[el2_lib.scala 197:88] - node _T_632 = eq(_T_630, _T_631) @[el2_lib.scala 197:80] - node _T_633 = mux(_T_629, UInt<1>("h01"), _T_632) @[el2_lib.scala 197:25] - _T_409[31] <= _T_633 @[el2_lib.scala 197:19] - node _T_634 = and(_T_409[0], _T_409[1]) @[el2_lib.scala 198:22] - node _T_635 = and(_T_634, _T_409[2]) @[el2_lib.scala 198:22] - node _T_636 = and(_T_635, _T_409[3]) @[el2_lib.scala 198:22] - node _T_637 = and(_T_636, _T_409[4]) @[el2_lib.scala 198:22] - node _T_638 = and(_T_637, _T_409[5]) @[el2_lib.scala 198:22] - node _T_639 = and(_T_638, _T_409[6]) @[el2_lib.scala 198:22] - node _T_640 = and(_T_639, _T_409[7]) @[el2_lib.scala 198:22] - node _T_641 = and(_T_640, _T_409[8]) @[el2_lib.scala 198:22] - node _T_642 = and(_T_641, _T_409[9]) @[el2_lib.scala 198:22] - node _T_643 = and(_T_642, _T_409[10]) @[el2_lib.scala 198:22] - node _T_644 = and(_T_643, _T_409[11]) @[el2_lib.scala 198:22] - node _T_645 = and(_T_644, _T_409[12]) @[el2_lib.scala 198:22] - node _T_646 = and(_T_645, _T_409[13]) @[el2_lib.scala 198:22] - node _T_647 = and(_T_646, _T_409[14]) @[el2_lib.scala 198:22] - node _T_648 = and(_T_647, _T_409[15]) @[el2_lib.scala 198:22] - node _T_649 = and(_T_648, _T_409[16]) @[el2_lib.scala 198:22] - node _T_650 = and(_T_649, _T_409[17]) @[el2_lib.scala 198:22] - node _T_651 = and(_T_650, _T_409[18]) @[el2_lib.scala 198:22] - node _T_652 = and(_T_651, _T_409[19]) @[el2_lib.scala 198:22] - node _T_653 = and(_T_652, _T_409[20]) @[el2_lib.scala 198:22] - node _T_654 = and(_T_653, _T_409[21]) @[el2_lib.scala 198:22] - node _T_655 = and(_T_654, _T_409[22]) @[el2_lib.scala 198:22] - node _T_656 = and(_T_655, _T_409[23]) @[el2_lib.scala 198:22] - node _T_657 = and(_T_656, _T_409[24]) @[el2_lib.scala 198:22] - node _T_658 = and(_T_657, _T_409[25]) @[el2_lib.scala 198:22] - node _T_659 = and(_T_658, _T_409[26]) @[el2_lib.scala 198:22] - node _T_660 = and(_T_659, _T_409[27]) @[el2_lib.scala 198:22] - node _T_661 = and(_T_660, _T_409[28]) @[el2_lib.scala 198:22] - node _T_662 = and(_T_661, _T_409[29]) @[el2_lib.scala 198:22] - node _T_663 = and(_T_662, _T_409[30]) @[el2_lib.scala 198:22] - node _T_664 = and(_T_663, _T_409[31]) @[el2_lib.scala 198:22] - node _T_665 = and(_T_407, _T_664) @[el2_lsu_trigger.scala 16:109] - node _T_666 = and(io.trigger_pkt_any[2].execute, io.trigger_pkt_any[2].m) @[el2_lsu_trigger.scala 16:83] - node _T_667 = bits(io.trigger_pkt_any[2].match_, 0, 0) @[el2_lsu_trigger.scala 16:213] - wire _T_668 : UInt<1>[32] @[el2_lib.scala 193:24] - node _T_669 = andr(io.trigger_pkt_any[2].tdata2) @[el2_lib.scala 194:45] - node _T_670 = not(_T_669) @[el2_lib.scala 194:39] - node _T_671 = and(_T_667, _T_670) @[el2_lib.scala 194:37] - node _T_672 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[el2_lib.scala 195:48] - node _T_673 = bits(dec_i0_match_data[2], 0, 0) @[el2_lib.scala 195:60] - node _T_674 = eq(_T_672, _T_673) @[el2_lib.scala 195:52] - node _T_675 = or(_T_671, _T_674) @[el2_lib.scala 195:41] - _T_668[0] <= _T_675 @[el2_lib.scala 195:18] - node _T_676 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[el2_lib.scala 197:30] - node _T_677 = andr(_T_676) @[el2_lib.scala 197:38] - node _T_678 = and(_T_677, _T_671) @[el2_lib.scala 197:43] - node _T_679 = bits(io.trigger_pkt_any[2].tdata2, 1, 1) @[el2_lib.scala 197:76] - node _T_680 = bits(dec_i0_match_data[2], 1, 1) @[el2_lib.scala 197:88] - node _T_681 = eq(_T_679, _T_680) @[el2_lib.scala 197:80] - node _T_682 = mux(_T_678, UInt<1>("h01"), _T_681) @[el2_lib.scala 197:25] - _T_668[1] <= _T_682 @[el2_lib.scala 197:19] - node _T_683 = bits(io.trigger_pkt_any[2].tdata2, 1, 0) @[el2_lib.scala 197:30] - node _T_684 = andr(_T_683) @[el2_lib.scala 197:38] - node _T_685 = and(_T_684, _T_671) @[el2_lib.scala 197:43] - node _T_686 = bits(io.trigger_pkt_any[2].tdata2, 2, 2) @[el2_lib.scala 197:76] - node _T_687 = bits(dec_i0_match_data[2], 2, 2) @[el2_lib.scala 197:88] - node _T_688 = eq(_T_686, _T_687) @[el2_lib.scala 197:80] - node _T_689 = mux(_T_685, UInt<1>("h01"), _T_688) @[el2_lib.scala 197:25] - _T_668[2] <= _T_689 @[el2_lib.scala 197:19] - node _T_690 = bits(io.trigger_pkt_any[2].tdata2, 2, 0) @[el2_lib.scala 197:30] - node _T_691 = andr(_T_690) @[el2_lib.scala 197:38] - node _T_692 = and(_T_691, _T_671) @[el2_lib.scala 197:43] - node _T_693 = bits(io.trigger_pkt_any[2].tdata2, 3, 3) @[el2_lib.scala 197:76] - node _T_694 = bits(dec_i0_match_data[2], 3, 3) @[el2_lib.scala 197:88] - node _T_695 = eq(_T_693, _T_694) @[el2_lib.scala 197:80] - node _T_696 = mux(_T_692, UInt<1>("h01"), _T_695) @[el2_lib.scala 197:25] - _T_668[3] <= _T_696 @[el2_lib.scala 197:19] - node _T_697 = bits(io.trigger_pkt_any[2].tdata2, 3, 0) @[el2_lib.scala 197:30] - node _T_698 = andr(_T_697) @[el2_lib.scala 197:38] - node _T_699 = and(_T_698, _T_671) @[el2_lib.scala 197:43] - node _T_700 = bits(io.trigger_pkt_any[2].tdata2, 4, 4) @[el2_lib.scala 197:76] - node _T_701 = bits(dec_i0_match_data[2], 4, 4) @[el2_lib.scala 197:88] - node _T_702 = eq(_T_700, _T_701) @[el2_lib.scala 197:80] - node _T_703 = mux(_T_699, UInt<1>("h01"), _T_702) @[el2_lib.scala 197:25] - _T_668[4] <= _T_703 @[el2_lib.scala 197:19] - node _T_704 = bits(io.trigger_pkt_any[2].tdata2, 4, 0) @[el2_lib.scala 197:30] - node _T_705 = andr(_T_704) @[el2_lib.scala 197:38] - node _T_706 = and(_T_705, _T_671) @[el2_lib.scala 197:43] - node _T_707 = bits(io.trigger_pkt_any[2].tdata2, 5, 5) @[el2_lib.scala 197:76] - node _T_708 = bits(dec_i0_match_data[2], 5, 5) @[el2_lib.scala 197:88] - node _T_709 = eq(_T_707, _T_708) @[el2_lib.scala 197:80] - node _T_710 = mux(_T_706, UInt<1>("h01"), _T_709) @[el2_lib.scala 197:25] - _T_668[5] <= _T_710 @[el2_lib.scala 197:19] - node _T_711 = bits(io.trigger_pkt_any[2].tdata2, 5, 0) @[el2_lib.scala 197:30] - node _T_712 = andr(_T_711) @[el2_lib.scala 197:38] - node _T_713 = and(_T_712, _T_671) @[el2_lib.scala 197:43] - node _T_714 = bits(io.trigger_pkt_any[2].tdata2, 6, 6) @[el2_lib.scala 197:76] - node _T_715 = bits(dec_i0_match_data[2], 6, 6) @[el2_lib.scala 197:88] - node _T_716 = eq(_T_714, _T_715) @[el2_lib.scala 197:80] - node _T_717 = mux(_T_713, UInt<1>("h01"), _T_716) @[el2_lib.scala 197:25] - _T_668[6] <= _T_717 @[el2_lib.scala 197:19] - node _T_718 = bits(io.trigger_pkt_any[2].tdata2, 6, 0) @[el2_lib.scala 197:30] - node _T_719 = andr(_T_718) @[el2_lib.scala 197:38] - node _T_720 = and(_T_719, _T_671) @[el2_lib.scala 197:43] - node _T_721 = bits(io.trigger_pkt_any[2].tdata2, 7, 7) @[el2_lib.scala 197:76] - node _T_722 = bits(dec_i0_match_data[2], 7, 7) @[el2_lib.scala 197:88] - node _T_723 = eq(_T_721, _T_722) @[el2_lib.scala 197:80] - node _T_724 = mux(_T_720, UInt<1>("h01"), _T_723) @[el2_lib.scala 197:25] - _T_668[7] <= _T_724 @[el2_lib.scala 197:19] - node _T_725 = bits(io.trigger_pkt_any[2].tdata2, 7, 0) @[el2_lib.scala 197:30] - node _T_726 = andr(_T_725) @[el2_lib.scala 197:38] - node _T_727 = and(_T_726, _T_671) @[el2_lib.scala 197:43] - node _T_728 = bits(io.trigger_pkt_any[2].tdata2, 8, 8) @[el2_lib.scala 197:76] - node _T_729 = bits(dec_i0_match_data[2], 8, 8) @[el2_lib.scala 197:88] - node _T_730 = eq(_T_728, _T_729) @[el2_lib.scala 197:80] - node _T_731 = mux(_T_727, UInt<1>("h01"), _T_730) @[el2_lib.scala 197:25] - _T_668[8] <= _T_731 @[el2_lib.scala 197:19] - node _T_732 = bits(io.trigger_pkt_any[2].tdata2, 8, 0) @[el2_lib.scala 197:30] - node _T_733 = andr(_T_732) @[el2_lib.scala 197:38] - node _T_734 = and(_T_733, _T_671) @[el2_lib.scala 197:43] - node _T_735 = bits(io.trigger_pkt_any[2].tdata2, 9, 9) @[el2_lib.scala 197:76] - node _T_736 = bits(dec_i0_match_data[2], 9, 9) @[el2_lib.scala 197:88] - node _T_737 = eq(_T_735, _T_736) @[el2_lib.scala 197:80] - node _T_738 = mux(_T_734, UInt<1>("h01"), _T_737) @[el2_lib.scala 197:25] - _T_668[9] <= _T_738 @[el2_lib.scala 197:19] - node _T_739 = bits(io.trigger_pkt_any[2].tdata2, 9, 0) @[el2_lib.scala 197:30] - node _T_740 = andr(_T_739) @[el2_lib.scala 197:38] - node _T_741 = and(_T_740, _T_671) @[el2_lib.scala 197:43] - node _T_742 = bits(io.trigger_pkt_any[2].tdata2, 10, 10) @[el2_lib.scala 197:76] - node _T_743 = bits(dec_i0_match_data[2], 10, 10) @[el2_lib.scala 197:88] - node _T_744 = eq(_T_742, _T_743) @[el2_lib.scala 197:80] - node _T_745 = mux(_T_741, UInt<1>("h01"), _T_744) @[el2_lib.scala 197:25] - _T_668[10] <= _T_745 @[el2_lib.scala 197:19] - node _T_746 = bits(io.trigger_pkt_any[2].tdata2, 10, 0) @[el2_lib.scala 197:30] - node _T_747 = andr(_T_746) @[el2_lib.scala 197:38] - node _T_748 = and(_T_747, _T_671) @[el2_lib.scala 197:43] - node _T_749 = bits(io.trigger_pkt_any[2].tdata2, 11, 11) @[el2_lib.scala 197:76] - node _T_750 = bits(dec_i0_match_data[2], 11, 11) @[el2_lib.scala 197:88] - node _T_751 = eq(_T_749, _T_750) @[el2_lib.scala 197:80] - node _T_752 = mux(_T_748, UInt<1>("h01"), _T_751) @[el2_lib.scala 197:25] - _T_668[11] <= _T_752 @[el2_lib.scala 197:19] - node _T_753 = bits(io.trigger_pkt_any[2].tdata2, 11, 0) @[el2_lib.scala 197:30] - node _T_754 = andr(_T_753) @[el2_lib.scala 197:38] - node _T_755 = and(_T_754, _T_671) @[el2_lib.scala 197:43] - node _T_756 = bits(io.trigger_pkt_any[2].tdata2, 12, 12) @[el2_lib.scala 197:76] - node _T_757 = bits(dec_i0_match_data[2], 12, 12) @[el2_lib.scala 197:88] - node _T_758 = eq(_T_756, _T_757) @[el2_lib.scala 197:80] - node _T_759 = mux(_T_755, UInt<1>("h01"), _T_758) @[el2_lib.scala 197:25] - _T_668[12] <= _T_759 @[el2_lib.scala 197:19] - node _T_760 = bits(io.trigger_pkt_any[2].tdata2, 12, 0) @[el2_lib.scala 197:30] - node _T_761 = andr(_T_760) @[el2_lib.scala 197:38] - node _T_762 = and(_T_761, _T_671) @[el2_lib.scala 197:43] - node _T_763 = bits(io.trigger_pkt_any[2].tdata2, 13, 13) @[el2_lib.scala 197:76] - node _T_764 = bits(dec_i0_match_data[2], 13, 13) @[el2_lib.scala 197:88] - node _T_765 = eq(_T_763, _T_764) @[el2_lib.scala 197:80] - node _T_766 = mux(_T_762, UInt<1>("h01"), _T_765) @[el2_lib.scala 197:25] - _T_668[13] <= _T_766 @[el2_lib.scala 197:19] - node _T_767 = bits(io.trigger_pkt_any[2].tdata2, 13, 0) @[el2_lib.scala 197:30] - node _T_768 = andr(_T_767) @[el2_lib.scala 197:38] - node _T_769 = and(_T_768, _T_671) @[el2_lib.scala 197:43] - node _T_770 = bits(io.trigger_pkt_any[2].tdata2, 14, 14) @[el2_lib.scala 197:76] - node _T_771 = bits(dec_i0_match_data[2], 14, 14) @[el2_lib.scala 197:88] - node _T_772 = eq(_T_770, _T_771) @[el2_lib.scala 197:80] - node _T_773 = mux(_T_769, UInt<1>("h01"), _T_772) @[el2_lib.scala 197:25] - _T_668[14] <= _T_773 @[el2_lib.scala 197:19] - node _T_774 = bits(io.trigger_pkt_any[2].tdata2, 14, 0) @[el2_lib.scala 197:30] - node _T_775 = andr(_T_774) @[el2_lib.scala 197:38] - node _T_776 = and(_T_775, _T_671) @[el2_lib.scala 197:43] - node _T_777 = bits(io.trigger_pkt_any[2].tdata2, 15, 15) @[el2_lib.scala 197:76] - node _T_778 = bits(dec_i0_match_data[2], 15, 15) @[el2_lib.scala 197:88] - node _T_779 = eq(_T_777, _T_778) @[el2_lib.scala 197:80] - node _T_780 = mux(_T_776, UInt<1>("h01"), _T_779) @[el2_lib.scala 197:25] - _T_668[15] <= _T_780 @[el2_lib.scala 197:19] - node _T_781 = bits(io.trigger_pkt_any[2].tdata2, 15, 0) @[el2_lib.scala 197:30] - node _T_782 = andr(_T_781) @[el2_lib.scala 197:38] - node _T_783 = and(_T_782, _T_671) @[el2_lib.scala 197:43] - node _T_784 = bits(io.trigger_pkt_any[2].tdata2, 16, 16) @[el2_lib.scala 197:76] - node _T_785 = bits(dec_i0_match_data[2], 16, 16) @[el2_lib.scala 197:88] - node _T_786 = eq(_T_784, _T_785) @[el2_lib.scala 197:80] - node _T_787 = mux(_T_783, UInt<1>("h01"), _T_786) @[el2_lib.scala 197:25] - _T_668[16] <= _T_787 @[el2_lib.scala 197:19] - node _T_788 = bits(io.trigger_pkt_any[2].tdata2, 16, 0) @[el2_lib.scala 197:30] - node _T_789 = andr(_T_788) @[el2_lib.scala 197:38] - node _T_790 = and(_T_789, _T_671) @[el2_lib.scala 197:43] - node _T_791 = bits(io.trigger_pkt_any[2].tdata2, 17, 17) @[el2_lib.scala 197:76] - node _T_792 = bits(dec_i0_match_data[2], 17, 17) @[el2_lib.scala 197:88] - node _T_793 = eq(_T_791, _T_792) @[el2_lib.scala 197:80] - node _T_794 = mux(_T_790, UInt<1>("h01"), _T_793) @[el2_lib.scala 197:25] - _T_668[17] <= _T_794 @[el2_lib.scala 197:19] - node _T_795 = bits(io.trigger_pkt_any[2].tdata2, 17, 0) @[el2_lib.scala 197:30] - node _T_796 = andr(_T_795) @[el2_lib.scala 197:38] - node _T_797 = and(_T_796, _T_671) @[el2_lib.scala 197:43] - node _T_798 = bits(io.trigger_pkt_any[2].tdata2, 18, 18) @[el2_lib.scala 197:76] - node _T_799 = bits(dec_i0_match_data[2], 18, 18) @[el2_lib.scala 197:88] - node _T_800 = eq(_T_798, _T_799) @[el2_lib.scala 197:80] - node _T_801 = mux(_T_797, UInt<1>("h01"), _T_800) @[el2_lib.scala 197:25] - _T_668[18] <= _T_801 @[el2_lib.scala 197:19] - node _T_802 = bits(io.trigger_pkt_any[2].tdata2, 18, 0) @[el2_lib.scala 197:30] - node _T_803 = andr(_T_802) @[el2_lib.scala 197:38] - node _T_804 = and(_T_803, _T_671) @[el2_lib.scala 197:43] - node _T_805 = bits(io.trigger_pkt_any[2].tdata2, 19, 19) @[el2_lib.scala 197:76] - node _T_806 = bits(dec_i0_match_data[2], 19, 19) @[el2_lib.scala 197:88] - node _T_807 = eq(_T_805, _T_806) @[el2_lib.scala 197:80] - node _T_808 = mux(_T_804, UInt<1>("h01"), _T_807) @[el2_lib.scala 197:25] - _T_668[19] <= _T_808 @[el2_lib.scala 197:19] - node _T_809 = bits(io.trigger_pkt_any[2].tdata2, 19, 0) @[el2_lib.scala 197:30] - node _T_810 = andr(_T_809) @[el2_lib.scala 197:38] - node _T_811 = and(_T_810, _T_671) @[el2_lib.scala 197:43] - node _T_812 = bits(io.trigger_pkt_any[2].tdata2, 20, 20) @[el2_lib.scala 197:76] - node _T_813 = bits(dec_i0_match_data[2], 20, 20) @[el2_lib.scala 197:88] - node _T_814 = eq(_T_812, _T_813) @[el2_lib.scala 197:80] - node _T_815 = mux(_T_811, UInt<1>("h01"), _T_814) @[el2_lib.scala 197:25] - _T_668[20] <= _T_815 @[el2_lib.scala 197:19] - node _T_816 = bits(io.trigger_pkt_any[2].tdata2, 20, 0) @[el2_lib.scala 197:30] - node _T_817 = andr(_T_816) @[el2_lib.scala 197:38] - node _T_818 = and(_T_817, _T_671) @[el2_lib.scala 197:43] - node _T_819 = bits(io.trigger_pkt_any[2].tdata2, 21, 21) @[el2_lib.scala 197:76] - node _T_820 = bits(dec_i0_match_data[2], 21, 21) @[el2_lib.scala 197:88] - node _T_821 = eq(_T_819, _T_820) @[el2_lib.scala 197:80] - node _T_822 = mux(_T_818, UInt<1>("h01"), _T_821) @[el2_lib.scala 197:25] - _T_668[21] <= _T_822 @[el2_lib.scala 197:19] - node _T_823 = bits(io.trigger_pkt_any[2].tdata2, 21, 0) @[el2_lib.scala 197:30] - node _T_824 = andr(_T_823) @[el2_lib.scala 197:38] - node _T_825 = and(_T_824, _T_671) @[el2_lib.scala 197:43] - node _T_826 = bits(io.trigger_pkt_any[2].tdata2, 22, 22) @[el2_lib.scala 197:76] - node _T_827 = bits(dec_i0_match_data[2], 22, 22) @[el2_lib.scala 197:88] - node _T_828 = eq(_T_826, _T_827) @[el2_lib.scala 197:80] - node _T_829 = mux(_T_825, UInt<1>("h01"), _T_828) @[el2_lib.scala 197:25] - _T_668[22] <= _T_829 @[el2_lib.scala 197:19] - node _T_830 = bits(io.trigger_pkt_any[2].tdata2, 22, 0) @[el2_lib.scala 197:30] - node _T_831 = andr(_T_830) @[el2_lib.scala 197:38] - node _T_832 = and(_T_831, _T_671) @[el2_lib.scala 197:43] - node _T_833 = bits(io.trigger_pkt_any[2].tdata2, 23, 23) @[el2_lib.scala 197:76] - node _T_834 = bits(dec_i0_match_data[2], 23, 23) @[el2_lib.scala 197:88] - node _T_835 = eq(_T_833, _T_834) @[el2_lib.scala 197:80] - node _T_836 = mux(_T_832, UInt<1>("h01"), _T_835) @[el2_lib.scala 197:25] - _T_668[23] <= _T_836 @[el2_lib.scala 197:19] - node _T_837 = bits(io.trigger_pkt_any[2].tdata2, 23, 0) @[el2_lib.scala 197:30] - node _T_838 = andr(_T_837) @[el2_lib.scala 197:38] - node _T_839 = and(_T_838, _T_671) @[el2_lib.scala 197:43] - node _T_840 = bits(io.trigger_pkt_any[2].tdata2, 24, 24) @[el2_lib.scala 197:76] - node _T_841 = bits(dec_i0_match_data[2], 24, 24) @[el2_lib.scala 197:88] - node _T_842 = eq(_T_840, _T_841) @[el2_lib.scala 197:80] - node _T_843 = mux(_T_839, UInt<1>("h01"), _T_842) @[el2_lib.scala 197:25] - _T_668[24] <= _T_843 @[el2_lib.scala 197:19] - node _T_844 = bits(io.trigger_pkt_any[2].tdata2, 24, 0) @[el2_lib.scala 197:30] - node _T_845 = andr(_T_844) @[el2_lib.scala 197:38] - node _T_846 = and(_T_845, _T_671) @[el2_lib.scala 197:43] - node _T_847 = bits(io.trigger_pkt_any[2].tdata2, 25, 25) @[el2_lib.scala 197:76] - node _T_848 = bits(dec_i0_match_data[2], 25, 25) @[el2_lib.scala 197:88] - node _T_849 = eq(_T_847, _T_848) @[el2_lib.scala 197:80] - node _T_850 = mux(_T_846, UInt<1>("h01"), _T_849) @[el2_lib.scala 197:25] - _T_668[25] <= _T_850 @[el2_lib.scala 197:19] - node _T_851 = bits(io.trigger_pkt_any[2].tdata2, 25, 0) @[el2_lib.scala 197:30] - node _T_852 = andr(_T_851) @[el2_lib.scala 197:38] - node _T_853 = and(_T_852, _T_671) @[el2_lib.scala 197:43] - node _T_854 = bits(io.trigger_pkt_any[2].tdata2, 26, 26) @[el2_lib.scala 197:76] - node _T_855 = bits(dec_i0_match_data[2], 26, 26) @[el2_lib.scala 197:88] - node _T_856 = eq(_T_854, _T_855) @[el2_lib.scala 197:80] - node _T_857 = mux(_T_853, UInt<1>("h01"), _T_856) @[el2_lib.scala 197:25] - _T_668[26] <= _T_857 @[el2_lib.scala 197:19] - node _T_858 = bits(io.trigger_pkt_any[2].tdata2, 26, 0) @[el2_lib.scala 197:30] - node _T_859 = andr(_T_858) @[el2_lib.scala 197:38] - node _T_860 = and(_T_859, _T_671) @[el2_lib.scala 197:43] - node _T_861 = bits(io.trigger_pkt_any[2].tdata2, 27, 27) @[el2_lib.scala 197:76] - node _T_862 = bits(dec_i0_match_data[2], 27, 27) @[el2_lib.scala 197:88] - node _T_863 = eq(_T_861, _T_862) @[el2_lib.scala 197:80] - node _T_864 = mux(_T_860, UInt<1>("h01"), _T_863) @[el2_lib.scala 197:25] - _T_668[27] <= _T_864 @[el2_lib.scala 197:19] - node _T_865 = bits(io.trigger_pkt_any[2].tdata2, 27, 0) @[el2_lib.scala 197:30] - node _T_866 = andr(_T_865) @[el2_lib.scala 197:38] - node _T_867 = and(_T_866, _T_671) @[el2_lib.scala 197:43] - node _T_868 = bits(io.trigger_pkt_any[2].tdata2, 28, 28) @[el2_lib.scala 197:76] - node _T_869 = bits(dec_i0_match_data[2], 28, 28) @[el2_lib.scala 197:88] - node _T_870 = eq(_T_868, _T_869) @[el2_lib.scala 197:80] - node _T_871 = mux(_T_867, UInt<1>("h01"), _T_870) @[el2_lib.scala 197:25] - _T_668[28] <= _T_871 @[el2_lib.scala 197:19] - node _T_872 = bits(io.trigger_pkt_any[2].tdata2, 28, 0) @[el2_lib.scala 197:30] - node _T_873 = andr(_T_872) @[el2_lib.scala 197:38] - node _T_874 = and(_T_873, _T_671) @[el2_lib.scala 197:43] - node _T_875 = bits(io.trigger_pkt_any[2].tdata2, 29, 29) @[el2_lib.scala 197:76] - node _T_876 = bits(dec_i0_match_data[2], 29, 29) @[el2_lib.scala 197:88] - node _T_877 = eq(_T_875, _T_876) @[el2_lib.scala 197:80] - node _T_878 = mux(_T_874, UInt<1>("h01"), _T_877) @[el2_lib.scala 197:25] - _T_668[29] <= _T_878 @[el2_lib.scala 197:19] - node _T_879 = bits(io.trigger_pkt_any[2].tdata2, 29, 0) @[el2_lib.scala 197:30] - node _T_880 = andr(_T_879) @[el2_lib.scala 197:38] - node _T_881 = and(_T_880, _T_671) @[el2_lib.scala 197:43] - node _T_882 = bits(io.trigger_pkt_any[2].tdata2, 30, 30) @[el2_lib.scala 197:76] - node _T_883 = bits(dec_i0_match_data[2], 30, 30) @[el2_lib.scala 197:88] - node _T_884 = eq(_T_882, _T_883) @[el2_lib.scala 197:80] - node _T_885 = mux(_T_881, UInt<1>("h01"), _T_884) @[el2_lib.scala 197:25] - _T_668[30] <= _T_885 @[el2_lib.scala 197:19] - node _T_886 = bits(io.trigger_pkt_any[2].tdata2, 30, 0) @[el2_lib.scala 197:30] - node _T_887 = andr(_T_886) @[el2_lib.scala 197:38] - node _T_888 = and(_T_887, _T_671) @[el2_lib.scala 197:43] - node _T_889 = bits(io.trigger_pkt_any[2].tdata2, 31, 31) @[el2_lib.scala 197:76] - node _T_890 = bits(dec_i0_match_data[2], 31, 31) @[el2_lib.scala 197:88] - node _T_891 = eq(_T_889, _T_890) @[el2_lib.scala 197:80] - node _T_892 = mux(_T_888, UInt<1>("h01"), _T_891) @[el2_lib.scala 197:25] - _T_668[31] <= _T_892 @[el2_lib.scala 197:19] - node _T_893 = and(_T_668[0], _T_668[1]) @[el2_lib.scala 198:22] - node _T_894 = and(_T_893, _T_668[2]) @[el2_lib.scala 198:22] - node _T_895 = and(_T_894, _T_668[3]) @[el2_lib.scala 198:22] - node _T_896 = and(_T_895, _T_668[4]) @[el2_lib.scala 198:22] - node _T_897 = and(_T_896, _T_668[5]) @[el2_lib.scala 198:22] - node _T_898 = and(_T_897, _T_668[6]) @[el2_lib.scala 198:22] - node _T_899 = and(_T_898, _T_668[7]) @[el2_lib.scala 198:22] - node _T_900 = and(_T_899, _T_668[8]) @[el2_lib.scala 198:22] - node _T_901 = and(_T_900, _T_668[9]) @[el2_lib.scala 198:22] - node _T_902 = and(_T_901, _T_668[10]) @[el2_lib.scala 198:22] - node _T_903 = and(_T_902, _T_668[11]) @[el2_lib.scala 198:22] - node _T_904 = and(_T_903, _T_668[12]) @[el2_lib.scala 198:22] - node _T_905 = and(_T_904, _T_668[13]) @[el2_lib.scala 198:22] - node _T_906 = and(_T_905, _T_668[14]) @[el2_lib.scala 198:22] - node _T_907 = and(_T_906, _T_668[15]) @[el2_lib.scala 198:22] - node _T_908 = and(_T_907, _T_668[16]) @[el2_lib.scala 198:22] - node _T_909 = and(_T_908, _T_668[17]) @[el2_lib.scala 198:22] - node _T_910 = and(_T_909, _T_668[18]) @[el2_lib.scala 198:22] - node _T_911 = and(_T_910, _T_668[19]) @[el2_lib.scala 198:22] - node _T_912 = and(_T_911, _T_668[20]) @[el2_lib.scala 198:22] - node _T_913 = and(_T_912, _T_668[21]) @[el2_lib.scala 198:22] - node _T_914 = and(_T_913, _T_668[22]) @[el2_lib.scala 198:22] - node _T_915 = and(_T_914, _T_668[23]) @[el2_lib.scala 198:22] - node _T_916 = and(_T_915, _T_668[24]) @[el2_lib.scala 198:22] - node _T_917 = and(_T_916, _T_668[25]) @[el2_lib.scala 198:22] - node _T_918 = and(_T_917, _T_668[26]) @[el2_lib.scala 198:22] - node _T_919 = and(_T_918, _T_668[27]) @[el2_lib.scala 198:22] - node _T_920 = and(_T_919, _T_668[28]) @[el2_lib.scala 198:22] - node _T_921 = and(_T_920, _T_668[29]) @[el2_lib.scala 198:22] - node _T_922 = and(_T_921, _T_668[30]) @[el2_lib.scala 198:22] - node _T_923 = and(_T_922, _T_668[31]) @[el2_lib.scala 198:22] - node _T_924 = and(_T_666, _T_923) @[el2_lsu_trigger.scala 16:109] - node _T_925 = and(io.trigger_pkt_any[3].execute, io.trigger_pkt_any[3].m) @[el2_lsu_trigger.scala 16:83] - node _T_926 = bits(io.trigger_pkt_any[3].match_, 0, 0) @[el2_lsu_trigger.scala 16:213] - wire _T_927 : UInt<1>[32] @[el2_lib.scala 193:24] - node _T_928 = andr(io.trigger_pkt_any[3].tdata2) @[el2_lib.scala 194:45] - node _T_929 = not(_T_928) @[el2_lib.scala 194:39] - node _T_930 = and(_T_926, _T_929) @[el2_lib.scala 194:37] - node _T_931 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[el2_lib.scala 195:48] - node _T_932 = bits(dec_i0_match_data[3], 0, 0) @[el2_lib.scala 195:60] - node _T_933 = eq(_T_931, _T_932) @[el2_lib.scala 195:52] - node _T_934 = or(_T_930, _T_933) @[el2_lib.scala 195:41] - _T_927[0] <= _T_934 @[el2_lib.scala 195:18] - node _T_935 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[el2_lib.scala 197:30] - node _T_936 = andr(_T_935) @[el2_lib.scala 197:38] - node _T_937 = and(_T_936, _T_930) @[el2_lib.scala 197:43] - node _T_938 = bits(io.trigger_pkt_any[3].tdata2, 1, 1) @[el2_lib.scala 197:76] - node _T_939 = bits(dec_i0_match_data[3], 1, 1) @[el2_lib.scala 197:88] - node _T_940 = eq(_T_938, _T_939) @[el2_lib.scala 197:80] - node _T_941 = mux(_T_937, UInt<1>("h01"), _T_940) @[el2_lib.scala 197:25] - _T_927[1] <= _T_941 @[el2_lib.scala 197:19] - node _T_942 = bits(io.trigger_pkt_any[3].tdata2, 1, 0) @[el2_lib.scala 197:30] - node _T_943 = andr(_T_942) @[el2_lib.scala 197:38] - node _T_944 = and(_T_943, _T_930) @[el2_lib.scala 197:43] - node _T_945 = bits(io.trigger_pkt_any[3].tdata2, 2, 2) @[el2_lib.scala 197:76] - node _T_946 = bits(dec_i0_match_data[3], 2, 2) @[el2_lib.scala 197:88] - node _T_947 = eq(_T_945, _T_946) @[el2_lib.scala 197:80] - node _T_948 = mux(_T_944, UInt<1>("h01"), _T_947) @[el2_lib.scala 197:25] - _T_927[2] <= _T_948 @[el2_lib.scala 197:19] - node _T_949 = bits(io.trigger_pkt_any[3].tdata2, 2, 0) @[el2_lib.scala 197:30] - node _T_950 = andr(_T_949) @[el2_lib.scala 197:38] - node _T_951 = and(_T_950, _T_930) @[el2_lib.scala 197:43] - node _T_952 = bits(io.trigger_pkt_any[3].tdata2, 3, 3) @[el2_lib.scala 197:76] - node _T_953 = bits(dec_i0_match_data[3], 3, 3) @[el2_lib.scala 197:88] - node _T_954 = eq(_T_952, _T_953) @[el2_lib.scala 197:80] - node _T_955 = mux(_T_951, UInt<1>("h01"), _T_954) @[el2_lib.scala 197:25] - _T_927[3] <= _T_955 @[el2_lib.scala 197:19] - node _T_956 = bits(io.trigger_pkt_any[3].tdata2, 3, 0) @[el2_lib.scala 197:30] - node _T_957 = andr(_T_956) @[el2_lib.scala 197:38] - node _T_958 = and(_T_957, _T_930) @[el2_lib.scala 197:43] - node _T_959 = bits(io.trigger_pkt_any[3].tdata2, 4, 4) @[el2_lib.scala 197:76] - node _T_960 = bits(dec_i0_match_data[3], 4, 4) @[el2_lib.scala 197:88] - node _T_961 = eq(_T_959, _T_960) @[el2_lib.scala 197:80] - node _T_962 = mux(_T_958, UInt<1>("h01"), _T_961) @[el2_lib.scala 197:25] - _T_927[4] <= _T_962 @[el2_lib.scala 197:19] - node _T_963 = bits(io.trigger_pkt_any[3].tdata2, 4, 0) @[el2_lib.scala 197:30] - node _T_964 = andr(_T_963) @[el2_lib.scala 197:38] - node _T_965 = and(_T_964, _T_930) @[el2_lib.scala 197:43] - node _T_966 = bits(io.trigger_pkt_any[3].tdata2, 5, 5) @[el2_lib.scala 197:76] - node _T_967 = bits(dec_i0_match_data[3], 5, 5) @[el2_lib.scala 197:88] - node _T_968 = eq(_T_966, _T_967) @[el2_lib.scala 197:80] - node _T_969 = mux(_T_965, UInt<1>("h01"), _T_968) @[el2_lib.scala 197:25] - _T_927[5] <= _T_969 @[el2_lib.scala 197:19] - node _T_970 = bits(io.trigger_pkt_any[3].tdata2, 5, 0) @[el2_lib.scala 197:30] - node _T_971 = andr(_T_970) @[el2_lib.scala 197:38] - node _T_972 = and(_T_971, _T_930) @[el2_lib.scala 197:43] - node _T_973 = bits(io.trigger_pkt_any[3].tdata2, 6, 6) @[el2_lib.scala 197:76] - node _T_974 = bits(dec_i0_match_data[3], 6, 6) @[el2_lib.scala 197:88] - node _T_975 = eq(_T_973, _T_974) @[el2_lib.scala 197:80] - node _T_976 = mux(_T_972, UInt<1>("h01"), _T_975) @[el2_lib.scala 197:25] - _T_927[6] <= _T_976 @[el2_lib.scala 197:19] - node _T_977 = bits(io.trigger_pkt_any[3].tdata2, 6, 0) @[el2_lib.scala 197:30] - node _T_978 = andr(_T_977) @[el2_lib.scala 197:38] - node _T_979 = and(_T_978, _T_930) @[el2_lib.scala 197:43] - node _T_980 = bits(io.trigger_pkt_any[3].tdata2, 7, 7) @[el2_lib.scala 197:76] - node _T_981 = bits(dec_i0_match_data[3], 7, 7) @[el2_lib.scala 197:88] - node _T_982 = eq(_T_980, _T_981) @[el2_lib.scala 197:80] - node _T_983 = mux(_T_979, UInt<1>("h01"), _T_982) @[el2_lib.scala 197:25] - _T_927[7] <= _T_983 @[el2_lib.scala 197:19] - node _T_984 = bits(io.trigger_pkt_any[3].tdata2, 7, 0) @[el2_lib.scala 197:30] - node _T_985 = andr(_T_984) @[el2_lib.scala 197:38] - node _T_986 = and(_T_985, _T_930) @[el2_lib.scala 197:43] - node _T_987 = bits(io.trigger_pkt_any[3].tdata2, 8, 8) @[el2_lib.scala 197:76] - node _T_988 = bits(dec_i0_match_data[3], 8, 8) @[el2_lib.scala 197:88] - node _T_989 = eq(_T_987, _T_988) @[el2_lib.scala 197:80] - node _T_990 = mux(_T_986, UInt<1>("h01"), _T_989) @[el2_lib.scala 197:25] - _T_927[8] <= _T_990 @[el2_lib.scala 197:19] - node _T_991 = bits(io.trigger_pkt_any[3].tdata2, 8, 0) @[el2_lib.scala 197:30] - node _T_992 = andr(_T_991) @[el2_lib.scala 197:38] - node _T_993 = and(_T_992, _T_930) @[el2_lib.scala 197:43] - node _T_994 = bits(io.trigger_pkt_any[3].tdata2, 9, 9) @[el2_lib.scala 197:76] - node _T_995 = bits(dec_i0_match_data[3], 9, 9) @[el2_lib.scala 197:88] - node _T_996 = eq(_T_994, _T_995) @[el2_lib.scala 197:80] - node _T_997 = mux(_T_993, UInt<1>("h01"), _T_996) @[el2_lib.scala 197:25] - _T_927[9] <= _T_997 @[el2_lib.scala 197:19] - node _T_998 = bits(io.trigger_pkt_any[3].tdata2, 9, 0) @[el2_lib.scala 197:30] - node _T_999 = andr(_T_998) @[el2_lib.scala 197:38] - node _T_1000 = and(_T_999, _T_930) @[el2_lib.scala 197:43] - node _T_1001 = bits(io.trigger_pkt_any[3].tdata2, 10, 10) @[el2_lib.scala 197:76] - node _T_1002 = bits(dec_i0_match_data[3], 10, 10) @[el2_lib.scala 197:88] - node _T_1003 = eq(_T_1001, _T_1002) @[el2_lib.scala 197:80] - node _T_1004 = mux(_T_1000, UInt<1>("h01"), _T_1003) @[el2_lib.scala 197:25] - _T_927[10] <= _T_1004 @[el2_lib.scala 197:19] - node _T_1005 = bits(io.trigger_pkt_any[3].tdata2, 10, 0) @[el2_lib.scala 197:30] - node _T_1006 = andr(_T_1005) @[el2_lib.scala 197:38] - node _T_1007 = and(_T_1006, _T_930) @[el2_lib.scala 197:43] - node _T_1008 = bits(io.trigger_pkt_any[3].tdata2, 11, 11) @[el2_lib.scala 197:76] - node _T_1009 = bits(dec_i0_match_data[3], 11, 11) @[el2_lib.scala 197:88] - node _T_1010 = eq(_T_1008, _T_1009) @[el2_lib.scala 197:80] - node _T_1011 = mux(_T_1007, UInt<1>("h01"), _T_1010) @[el2_lib.scala 197:25] - _T_927[11] <= _T_1011 @[el2_lib.scala 197:19] - node _T_1012 = bits(io.trigger_pkt_any[3].tdata2, 11, 0) @[el2_lib.scala 197:30] - node _T_1013 = andr(_T_1012) @[el2_lib.scala 197:38] - node _T_1014 = and(_T_1013, _T_930) @[el2_lib.scala 197:43] - node _T_1015 = bits(io.trigger_pkt_any[3].tdata2, 12, 12) @[el2_lib.scala 197:76] - node _T_1016 = bits(dec_i0_match_data[3], 12, 12) @[el2_lib.scala 197:88] - node _T_1017 = eq(_T_1015, _T_1016) @[el2_lib.scala 197:80] - node _T_1018 = mux(_T_1014, UInt<1>("h01"), _T_1017) @[el2_lib.scala 197:25] - _T_927[12] <= _T_1018 @[el2_lib.scala 197:19] - node _T_1019 = bits(io.trigger_pkt_any[3].tdata2, 12, 0) @[el2_lib.scala 197:30] - node _T_1020 = andr(_T_1019) @[el2_lib.scala 197:38] - node _T_1021 = and(_T_1020, _T_930) @[el2_lib.scala 197:43] - node _T_1022 = bits(io.trigger_pkt_any[3].tdata2, 13, 13) @[el2_lib.scala 197:76] - node _T_1023 = bits(dec_i0_match_data[3], 13, 13) @[el2_lib.scala 197:88] - node _T_1024 = eq(_T_1022, _T_1023) @[el2_lib.scala 197:80] - node _T_1025 = mux(_T_1021, UInt<1>("h01"), _T_1024) @[el2_lib.scala 197:25] - _T_927[13] <= _T_1025 @[el2_lib.scala 197:19] - node _T_1026 = bits(io.trigger_pkt_any[3].tdata2, 13, 0) @[el2_lib.scala 197:30] - node _T_1027 = andr(_T_1026) @[el2_lib.scala 197:38] - node _T_1028 = and(_T_1027, _T_930) @[el2_lib.scala 197:43] - node _T_1029 = bits(io.trigger_pkt_any[3].tdata2, 14, 14) @[el2_lib.scala 197:76] - node _T_1030 = bits(dec_i0_match_data[3], 14, 14) @[el2_lib.scala 197:88] - node _T_1031 = eq(_T_1029, _T_1030) @[el2_lib.scala 197:80] - node _T_1032 = mux(_T_1028, UInt<1>("h01"), _T_1031) @[el2_lib.scala 197:25] - _T_927[14] <= _T_1032 @[el2_lib.scala 197:19] - node _T_1033 = bits(io.trigger_pkt_any[3].tdata2, 14, 0) @[el2_lib.scala 197:30] - node _T_1034 = andr(_T_1033) @[el2_lib.scala 197:38] - node _T_1035 = and(_T_1034, _T_930) @[el2_lib.scala 197:43] - node _T_1036 = bits(io.trigger_pkt_any[3].tdata2, 15, 15) @[el2_lib.scala 197:76] - node _T_1037 = bits(dec_i0_match_data[3], 15, 15) @[el2_lib.scala 197:88] - node _T_1038 = eq(_T_1036, _T_1037) @[el2_lib.scala 197:80] - node _T_1039 = mux(_T_1035, UInt<1>("h01"), _T_1038) @[el2_lib.scala 197:25] - _T_927[15] <= _T_1039 @[el2_lib.scala 197:19] - node _T_1040 = bits(io.trigger_pkt_any[3].tdata2, 15, 0) @[el2_lib.scala 197:30] - node _T_1041 = andr(_T_1040) @[el2_lib.scala 197:38] - node _T_1042 = and(_T_1041, _T_930) @[el2_lib.scala 197:43] - node _T_1043 = bits(io.trigger_pkt_any[3].tdata2, 16, 16) @[el2_lib.scala 197:76] - node _T_1044 = bits(dec_i0_match_data[3], 16, 16) @[el2_lib.scala 197:88] - node _T_1045 = eq(_T_1043, _T_1044) @[el2_lib.scala 197:80] - node _T_1046 = mux(_T_1042, UInt<1>("h01"), _T_1045) @[el2_lib.scala 197:25] - _T_927[16] <= _T_1046 @[el2_lib.scala 197:19] - node _T_1047 = bits(io.trigger_pkt_any[3].tdata2, 16, 0) @[el2_lib.scala 197:30] - node _T_1048 = andr(_T_1047) @[el2_lib.scala 197:38] - node _T_1049 = and(_T_1048, _T_930) @[el2_lib.scala 197:43] - node _T_1050 = bits(io.trigger_pkt_any[3].tdata2, 17, 17) @[el2_lib.scala 197:76] - node _T_1051 = bits(dec_i0_match_data[3], 17, 17) @[el2_lib.scala 197:88] - node _T_1052 = eq(_T_1050, _T_1051) @[el2_lib.scala 197:80] - node _T_1053 = mux(_T_1049, UInt<1>("h01"), _T_1052) @[el2_lib.scala 197:25] - _T_927[17] <= _T_1053 @[el2_lib.scala 197:19] - node _T_1054 = bits(io.trigger_pkt_any[3].tdata2, 17, 0) @[el2_lib.scala 197:30] - node _T_1055 = andr(_T_1054) @[el2_lib.scala 197:38] - node _T_1056 = and(_T_1055, _T_930) @[el2_lib.scala 197:43] - node _T_1057 = bits(io.trigger_pkt_any[3].tdata2, 18, 18) @[el2_lib.scala 197:76] - node _T_1058 = bits(dec_i0_match_data[3], 18, 18) @[el2_lib.scala 197:88] - node _T_1059 = eq(_T_1057, _T_1058) @[el2_lib.scala 197:80] - node _T_1060 = mux(_T_1056, UInt<1>("h01"), _T_1059) @[el2_lib.scala 197:25] - _T_927[18] <= _T_1060 @[el2_lib.scala 197:19] - node _T_1061 = bits(io.trigger_pkt_any[3].tdata2, 18, 0) @[el2_lib.scala 197:30] - node _T_1062 = andr(_T_1061) @[el2_lib.scala 197:38] - node _T_1063 = and(_T_1062, _T_930) @[el2_lib.scala 197:43] - node _T_1064 = bits(io.trigger_pkt_any[3].tdata2, 19, 19) @[el2_lib.scala 197:76] - node _T_1065 = bits(dec_i0_match_data[3], 19, 19) @[el2_lib.scala 197:88] - node _T_1066 = eq(_T_1064, _T_1065) @[el2_lib.scala 197:80] - node _T_1067 = mux(_T_1063, UInt<1>("h01"), _T_1066) @[el2_lib.scala 197:25] - _T_927[19] <= _T_1067 @[el2_lib.scala 197:19] - node _T_1068 = bits(io.trigger_pkt_any[3].tdata2, 19, 0) @[el2_lib.scala 197:30] - node _T_1069 = andr(_T_1068) @[el2_lib.scala 197:38] - node _T_1070 = and(_T_1069, _T_930) @[el2_lib.scala 197:43] - node _T_1071 = bits(io.trigger_pkt_any[3].tdata2, 20, 20) @[el2_lib.scala 197:76] - node _T_1072 = bits(dec_i0_match_data[3], 20, 20) @[el2_lib.scala 197:88] - node _T_1073 = eq(_T_1071, _T_1072) @[el2_lib.scala 197:80] - node _T_1074 = mux(_T_1070, UInt<1>("h01"), _T_1073) @[el2_lib.scala 197:25] - _T_927[20] <= _T_1074 @[el2_lib.scala 197:19] - node _T_1075 = bits(io.trigger_pkt_any[3].tdata2, 20, 0) @[el2_lib.scala 197:30] - node _T_1076 = andr(_T_1075) @[el2_lib.scala 197:38] - node _T_1077 = and(_T_1076, _T_930) @[el2_lib.scala 197:43] - node _T_1078 = bits(io.trigger_pkt_any[3].tdata2, 21, 21) @[el2_lib.scala 197:76] - node _T_1079 = bits(dec_i0_match_data[3], 21, 21) @[el2_lib.scala 197:88] - node _T_1080 = eq(_T_1078, _T_1079) @[el2_lib.scala 197:80] - node _T_1081 = mux(_T_1077, UInt<1>("h01"), _T_1080) @[el2_lib.scala 197:25] - _T_927[21] <= _T_1081 @[el2_lib.scala 197:19] - node _T_1082 = bits(io.trigger_pkt_any[3].tdata2, 21, 0) @[el2_lib.scala 197:30] - node _T_1083 = andr(_T_1082) @[el2_lib.scala 197:38] - node _T_1084 = and(_T_1083, _T_930) @[el2_lib.scala 197:43] - node _T_1085 = bits(io.trigger_pkt_any[3].tdata2, 22, 22) @[el2_lib.scala 197:76] - node _T_1086 = bits(dec_i0_match_data[3], 22, 22) @[el2_lib.scala 197:88] - node _T_1087 = eq(_T_1085, _T_1086) @[el2_lib.scala 197:80] - node _T_1088 = mux(_T_1084, UInt<1>("h01"), _T_1087) @[el2_lib.scala 197:25] - _T_927[22] <= _T_1088 @[el2_lib.scala 197:19] - node _T_1089 = bits(io.trigger_pkt_any[3].tdata2, 22, 0) @[el2_lib.scala 197:30] - node _T_1090 = andr(_T_1089) @[el2_lib.scala 197:38] - node _T_1091 = and(_T_1090, _T_930) @[el2_lib.scala 197:43] - node _T_1092 = bits(io.trigger_pkt_any[3].tdata2, 23, 23) @[el2_lib.scala 197:76] - node _T_1093 = bits(dec_i0_match_data[3], 23, 23) @[el2_lib.scala 197:88] - node _T_1094 = eq(_T_1092, _T_1093) @[el2_lib.scala 197:80] - node _T_1095 = mux(_T_1091, UInt<1>("h01"), _T_1094) @[el2_lib.scala 197:25] - _T_927[23] <= _T_1095 @[el2_lib.scala 197:19] - node _T_1096 = bits(io.trigger_pkt_any[3].tdata2, 23, 0) @[el2_lib.scala 197:30] - node _T_1097 = andr(_T_1096) @[el2_lib.scala 197:38] - node _T_1098 = and(_T_1097, _T_930) @[el2_lib.scala 197:43] - node _T_1099 = bits(io.trigger_pkt_any[3].tdata2, 24, 24) @[el2_lib.scala 197:76] - node _T_1100 = bits(dec_i0_match_data[3], 24, 24) @[el2_lib.scala 197:88] - node _T_1101 = eq(_T_1099, _T_1100) @[el2_lib.scala 197:80] - node _T_1102 = mux(_T_1098, UInt<1>("h01"), _T_1101) @[el2_lib.scala 197:25] - _T_927[24] <= _T_1102 @[el2_lib.scala 197:19] - node _T_1103 = bits(io.trigger_pkt_any[3].tdata2, 24, 0) @[el2_lib.scala 197:30] - node _T_1104 = andr(_T_1103) @[el2_lib.scala 197:38] - node _T_1105 = and(_T_1104, _T_930) @[el2_lib.scala 197:43] - node _T_1106 = bits(io.trigger_pkt_any[3].tdata2, 25, 25) @[el2_lib.scala 197:76] - node _T_1107 = bits(dec_i0_match_data[3], 25, 25) @[el2_lib.scala 197:88] - node _T_1108 = eq(_T_1106, _T_1107) @[el2_lib.scala 197:80] - node _T_1109 = mux(_T_1105, UInt<1>("h01"), _T_1108) @[el2_lib.scala 197:25] - _T_927[25] <= _T_1109 @[el2_lib.scala 197:19] - node _T_1110 = bits(io.trigger_pkt_any[3].tdata2, 25, 0) @[el2_lib.scala 197:30] - node _T_1111 = andr(_T_1110) @[el2_lib.scala 197:38] - node _T_1112 = and(_T_1111, _T_930) @[el2_lib.scala 197:43] - node _T_1113 = bits(io.trigger_pkt_any[3].tdata2, 26, 26) @[el2_lib.scala 197:76] - node _T_1114 = bits(dec_i0_match_data[3], 26, 26) @[el2_lib.scala 197:88] - node _T_1115 = eq(_T_1113, _T_1114) @[el2_lib.scala 197:80] - node _T_1116 = mux(_T_1112, UInt<1>("h01"), _T_1115) @[el2_lib.scala 197:25] - _T_927[26] <= _T_1116 @[el2_lib.scala 197:19] - node _T_1117 = bits(io.trigger_pkt_any[3].tdata2, 26, 0) @[el2_lib.scala 197:30] - node _T_1118 = andr(_T_1117) @[el2_lib.scala 197:38] - node _T_1119 = and(_T_1118, _T_930) @[el2_lib.scala 197:43] - node _T_1120 = bits(io.trigger_pkt_any[3].tdata2, 27, 27) @[el2_lib.scala 197:76] - node _T_1121 = bits(dec_i0_match_data[3], 27, 27) @[el2_lib.scala 197:88] - node _T_1122 = eq(_T_1120, _T_1121) @[el2_lib.scala 197:80] - node _T_1123 = mux(_T_1119, UInt<1>("h01"), _T_1122) @[el2_lib.scala 197:25] - _T_927[27] <= _T_1123 @[el2_lib.scala 197:19] - node _T_1124 = bits(io.trigger_pkt_any[3].tdata2, 27, 0) @[el2_lib.scala 197:30] - node _T_1125 = andr(_T_1124) @[el2_lib.scala 197:38] - node _T_1126 = and(_T_1125, _T_930) @[el2_lib.scala 197:43] - node _T_1127 = bits(io.trigger_pkt_any[3].tdata2, 28, 28) @[el2_lib.scala 197:76] - node _T_1128 = bits(dec_i0_match_data[3], 28, 28) @[el2_lib.scala 197:88] - node _T_1129 = eq(_T_1127, _T_1128) @[el2_lib.scala 197:80] - node _T_1130 = mux(_T_1126, UInt<1>("h01"), _T_1129) @[el2_lib.scala 197:25] - _T_927[28] <= _T_1130 @[el2_lib.scala 197:19] - node _T_1131 = bits(io.trigger_pkt_any[3].tdata2, 28, 0) @[el2_lib.scala 197:30] - node _T_1132 = andr(_T_1131) @[el2_lib.scala 197:38] - node _T_1133 = and(_T_1132, _T_930) @[el2_lib.scala 197:43] - node _T_1134 = bits(io.trigger_pkt_any[3].tdata2, 29, 29) @[el2_lib.scala 197:76] - node _T_1135 = bits(dec_i0_match_data[3], 29, 29) @[el2_lib.scala 197:88] - node _T_1136 = eq(_T_1134, _T_1135) @[el2_lib.scala 197:80] - node _T_1137 = mux(_T_1133, UInt<1>("h01"), _T_1136) @[el2_lib.scala 197:25] - _T_927[29] <= _T_1137 @[el2_lib.scala 197:19] - node _T_1138 = bits(io.trigger_pkt_any[3].tdata2, 29, 0) @[el2_lib.scala 197:30] - node _T_1139 = andr(_T_1138) @[el2_lib.scala 197:38] - node _T_1140 = and(_T_1139, _T_930) @[el2_lib.scala 197:43] - node _T_1141 = bits(io.trigger_pkt_any[3].tdata2, 30, 30) @[el2_lib.scala 197:76] - node _T_1142 = bits(dec_i0_match_data[3], 30, 30) @[el2_lib.scala 197:88] - node _T_1143 = eq(_T_1141, _T_1142) @[el2_lib.scala 197:80] - node _T_1144 = mux(_T_1140, UInt<1>("h01"), _T_1143) @[el2_lib.scala 197:25] - _T_927[30] <= _T_1144 @[el2_lib.scala 197:19] - node _T_1145 = bits(io.trigger_pkt_any[3].tdata2, 30, 0) @[el2_lib.scala 197:30] - node _T_1146 = andr(_T_1145) @[el2_lib.scala 197:38] - node _T_1147 = and(_T_1146, _T_930) @[el2_lib.scala 197:43] - node _T_1148 = bits(io.trigger_pkt_any[3].tdata2, 31, 31) @[el2_lib.scala 197:76] - node _T_1149 = bits(dec_i0_match_data[3], 31, 31) @[el2_lib.scala 197:88] - node _T_1150 = eq(_T_1148, _T_1149) @[el2_lib.scala 197:80] - node _T_1151 = mux(_T_1147, UInt<1>("h01"), _T_1150) @[el2_lib.scala 197:25] - _T_927[31] <= _T_1151 @[el2_lib.scala 197:19] - node _T_1152 = and(_T_927[0], _T_927[1]) @[el2_lib.scala 198:22] - node _T_1153 = and(_T_1152, _T_927[2]) @[el2_lib.scala 198:22] - node _T_1154 = and(_T_1153, _T_927[3]) @[el2_lib.scala 198:22] - node _T_1155 = and(_T_1154, _T_927[4]) @[el2_lib.scala 198:22] - node _T_1156 = and(_T_1155, _T_927[5]) @[el2_lib.scala 198:22] - node _T_1157 = and(_T_1156, _T_927[6]) @[el2_lib.scala 198:22] - node _T_1158 = and(_T_1157, _T_927[7]) @[el2_lib.scala 198:22] - node _T_1159 = and(_T_1158, _T_927[8]) @[el2_lib.scala 198:22] - node _T_1160 = and(_T_1159, _T_927[9]) @[el2_lib.scala 198:22] - node _T_1161 = and(_T_1160, _T_927[10]) @[el2_lib.scala 198:22] - node _T_1162 = and(_T_1161, _T_927[11]) @[el2_lib.scala 198:22] - node _T_1163 = and(_T_1162, _T_927[12]) @[el2_lib.scala 198:22] - node _T_1164 = and(_T_1163, _T_927[13]) @[el2_lib.scala 198:22] - node _T_1165 = and(_T_1164, _T_927[14]) @[el2_lib.scala 198:22] - node _T_1166 = and(_T_1165, _T_927[15]) @[el2_lib.scala 198:22] - node _T_1167 = and(_T_1166, _T_927[16]) @[el2_lib.scala 198:22] - node _T_1168 = and(_T_1167, _T_927[17]) @[el2_lib.scala 198:22] - node _T_1169 = and(_T_1168, _T_927[18]) @[el2_lib.scala 198:22] - node _T_1170 = and(_T_1169, _T_927[19]) @[el2_lib.scala 198:22] - node _T_1171 = and(_T_1170, _T_927[20]) @[el2_lib.scala 198:22] - node _T_1172 = and(_T_1171, _T_927[21]) @[el2_lib.scala 198:22] - node _T_1173 = and(_T_1172, _T_927[22]) @[el2_lib.scala 198:22] - node _T_1174 = and(_T_1173, _T_927[23]) @[el2_lib.scala 198:22] - node _T_1175 = and(_T_1174, _T_927[24]) @[el2_lib.scala 198:22] - node _T_1176 = and(_T_1175, _T_927[25]) @[el2_lib.scala 198:22] - node _T_1177 = and(_T_1176, _T_927[26]) @[el2_lib.scala 198:22] - node _T_1178 = and(_T_1177, _T_927[27]) @[el2_lib.scala 198:22] - node _T_1179 = and(_T_1178, _T_927[28]) @[el2_lib.scala 198:22] - node _T_1180 = and(_T_1179, _T_927[29]) @[el2_lib.scala 198:22] - node _T_1181 = and(_T_1180, _T_927[30]) @[el2_lib.scala 198:22] - node _T_1182 = and(_T_1181, _T_927[31]) @[el2_lib.scala 198:22] - node _T_1183 = and(_T_925, _T_1182) @[el2_lsu_trigger.scala 16:109] + node _T_147 = and(_T_144, _T_146) @[el2_dec_trigger.scala 14:127] + wire dec_i0_match_data : UInt<32>[4] @[el2_dec_trigger.scala 14:46] + dec_i0_match_data[0] <= _T_36 @[el2_dec_trigger.scala 14:46] + dec_i0_match_data[1] <= _T_73 @[el2_dec_trigger.scala 14:46] + dec_i0_match_data[2] <= _T_110 @[el2_dec_trigger.scala 14:46] + dec_i0_match_data[3] <= _T_147 @[el2_dec_trigger.scala 14:46] + node _T_148 = and(io.trigger_pkt_any[0].execute, io.trigger_pkt_any[0].m) @[el2_dec_trigger.scala 15:83] + node _T_149 = bits(io.trigger_pkt_any[0].match_pkt, 0, 0) @[el2_dec_trigger.scala 15:216] + wire _T_150 : UInt<1>[32] @[el2_lib.scala 240:24] + node _T_151 = andr(io.trigger_pkt_any[0].tdata2) @[el2_lib.scala 241:45] + node _T_152 = not(_T_151) @[el2_lib.scala 241:39] + node _T_153 = and(_T_149, _T_152) @[el2_lib.scala 241:37] + node _T_154 = bits(io.trigger_pkt_any[0].tdata2, 0, 0) @[el2_lib.scala 242:48] + node _T_155 = bits(dec_i0_match_data[0], 0, 0) @[el2_lib.scala 242:60] + node _T_156 = eq(_T_154, _T_155) @[el2_lib.scala 242:52] + node _T_157 = or(_T_153, _T_156) @[el2_lib.scala 242:41] + _T_150[0] <= _T_157 @[el2_lib.scala 242:18] + node _T_158 = bits(io.trigger_pkt_any[0].tdata2, 0, 0) @[el2_lib.scala 244:28] + node _T_159 = andr(_T_158) @[el2_lib.scala 244:36] + node _T_160 = and(_T_159, _T_153) @[el2_lib.scala 244:41] + node _T_161 = bits(io.trigger_pkt_any[0].tdata2, 1, 1) @[el2_lib.scala 244:74] + node _T_162 = bits(dec_i0_match_data[0], 1, 1) @[el2_lib.scala 244:86] + node _T_163 = eq(_T_161, _T_162) @[el2_lib.scala 244:78] + node _T_164 = mux(_T_160, UInt<1>("h01"), _T_163) @[el2_lib.scala 244:23] + _T_150[1] <= _T_164 @[el2_lib.scala 244:17] + node _T_165 = bits(io.trigger_pkt_any[0].tdata2, 1, 0) @[el2_lib.scala 244:28] + node _T_166 = andr(_T_165) @[el2_lib.scala 244:36] + node _T_167 = and(_T_166, _T_153) @[el2_lib.scala 244:41] + node _T_168 = bits(io.trigger_pkt_any[0].tdata2, 2, 2) @[el2_lib.scala 244:74] + node _T_169 = bits(dec_i0_match_data[0], 2, 2) @[el2_lib.scala 244:86] + node _T_170 = eq(_T_168, _T_169) @[el2_lib.scala 244:78] + node _T_171 = mux(_T_167, UInt<1>("h01"), _T_170) @[el2_lib.scala 244:23] + _T_150[2] <= _T_171 @[el2_lib.scala 244:17] + node _T_172 = bits(io.trigger_pkt_any[0].tdata2, 2, 0) @[el2_lib.scala 244:28] + node _T_173 = andr(_T_172) @[el2_lib.scala 244:36] + node _T_174 = and(_T_173, _T_153) @[el2_lib.scala 244:41] + node _T_175 = bits(io.trigger_pkt_any[0].tdata2, 3, 3) @[el2_lib.scala 244:74] + node _T_176 = bits(dec_i0_match_data[0], 3, 3) @[el2_lib.scala 244:86] + node _T_177 = eq(_T_175, _T_176) @[el2_lib.scala 244:78] + node _T_178 = mux(_T_174, UInt<1>("h01"), _T_177) @[el2_lib.scala 244:23] + _T_150[3] <= _T_178 @[el2_lib.scala 244:17] + node _T_179 = bits(io.trigger_pkt_any[0].tdata2, 3, 0) @[el2_lib.scala 244:28] + node _T_180 = andr(_T_179) @[el2_lib.scala 244:36] + node _T_181 = and(_T_180, _T_153) @[el2_lib.scala 244:41] + node _T_182 = bits(io.trigger_pkt_any[0].tdata2, 4, 4) @[el2_lib.scala 244:74] + node _T_183 = bits(dec_i0_match_data[0], 4, 4) @[el2_lib.scala 244:86] + node _T_184 = eq(_T_182, _T_183) @[el2_lib.scala 244:78] + node _T_185 = mux(_T_181, UInt<1>("h01"), _T_184) @[el2_lib.scala 244:23] + _T_150[4] <= _T_185 @[el2_lib.scala 244:17] + node _T_186 = bits(io.trigger_pkt_any[0].tdata2, 4, 0) @[el2_lib.scala 244:28] + node _T_187 = andr(_T_186) @[el2_lib.scala 244:36] + node _T_188 = and(_T_187, _T_153) @[el2_lib.scala 244:41] + node _T_189 = bits(io.trigger_pkt_any[0].tdata2, 5, 5) @[el2_lib.scala 244:74] + node _T_190 = bits(dec_i0_match_data[0], 5, 5) @[el2_lib.scala 244:86] + node _T_191 = eq(_T_189, _T_190) @[el2_lib.scala 244:78] + node _T_192 = mux(_T_188, UInt<1>("h01"), _T_191) @[el2_lib.scala 244:23] + _T_150[5] <= _T_192 @[el2_lib.scala 244:17] + node _T_193 = bits(io.trigger_pkt_any[0].tdata2, 5, 0) @[el2_lib.scala 244:28] + node _T_194 = andr(_T_193) @[el2_lib.scala 244:36] + node _T_195 = and(_T_194, _T_153) @[el2_lib.scala 244:41] + node _T_196 = bits(io.trigger_pkt_any[0].tdata2, 6, 6) @[el2_lib.scala 244:74] + node _T_197 = bits(dec_i0_match_data[0], 6, 6) @[el2_lib.scala 244:86] + node _T_198 = eq(_T_196, _T_197) @[el2_lib.scala 244:78] + node _T_199 = mux(_T_195, UInt<1>("h01"), _T_198) @[el2_lib.scala 244:23] + _T_150[6] <= _T_199 @[el2_lib.scala 244:17] + node _T_200 = bits(io.trigger_pkt_any[0].tdata2, 6, 0) @[el2_lib.scala 244:28] + node _T_201 = andr(_T_200) @[el2_lib.scala 244:36] + node _T_202 = and(_T_201, _T_153) @[el2_lib.scala 244:41] + node _T_203 = bits(io.trigger_pkt_any[0].tdata2, 7, 7) @[el2_lib.scala 244:74] + node _T_204 = bits(dec_i0_match_data[0], 7, 7) @[el2_lib.scala 244:86] + node _T_205 = eq(_T_203, _T_204) @[el2_lib.scala 244:78] + node _T_206 = mux(_T_202, UInt<1>("h01"), _T_205) @[el2_lib.scala 244:23] + _T_150[7] <= _T_206 @[el2_lib.scala 244:17] + node _T_207 = bits(io.trigger_pkt_any[0].tdata2, 7, 0) @[el2_lib.scala 244:28] + node _T_208 = andr(_T_207) @[el2_lib.scala 244:36] + node _T_209 = and(_T_208, _T_153) @[el2_lib.scala 244:41] + node _T_210 = bits(io.trigger_pkt_any[0].tdata2, 8, 8) @[el2_lib.scala 244:74] + node _T_211 = bits(dec_i0_match_data[0], 8, 8) @[el2_lib.scala 244:86] + node _T_212 = eq(_T_210, _T_211) @[el2_lib.scala 244:78] + node _T_213 = mux(_T_209, UInt<1>("h01"), _T_212) @[el2_lib.scala 244:23] + _T_150[8] <= _T_213 @[el2_lib.scala 244:17] + node _T_214 = bits(io.trigger_pkt_any[0].tdata2, 8, 0) @[el2_lib.scala 244:28] + node _T_215 = andr(_T_214) @[el2_lib.scala 244:36] + node _T_216 = and(_T_215, _T_153) @[el2_lib.scala 244:41] + node _T_217 = bits(io.trigger_pkt_any[0].tdata2, 9, 9) @[el2_lib.scala 244:74] + node _T_218 = bits(dec_i0_match_data[0], 9, 9) @[el2_lib.scala 244:86] + node _T_219 = eq(_T_217, _T_218) @[el2_lib.scala 244:78] + node _T_220 = mux(_T_216, UInt<1>("h01"), _T_219) @[el2_lib.scala 244:23] + _T_150[9] <= _T_220 @[el2_lib.scala 244:17] + node _T_221 = bits(io.trigger_pkt_any[0].tdata2, 9, 0) @[el2_lib.scala 244:28] + node _T_222 = andr(_T_221) @[el2_lib.scala 244:36] + node _T_223 = and(_T_222, _T_153) @[el2_lib.scala 244:41] + node _T_224 = bits(io.trigger_pkt_any[0].tdata2, 10, 10) @[el2_lib.scala 244:74] + node _T_225 = bits(dec_i0_match_data[0], 10, 10) @[el2_lib.scala 244:86] + node _T_226 = eq(_T_224, _T_225) @[el2_lib.scala 244:78] + node _T_227 = mux(_T_223, UInt<1>("h01"), _T_226) @[el2_lib.scala 244:23] + _T_150[10] <= _T_227 @[el2_lib.scala 244:17] + node _T_228 = bits(io.trigger_pkt_any[0].tdata2, 10, 0) @[el2_lib.scala 244:28] + node _T_229 = andr(_T_228) @[el2_lib.scala 244:36] + node _T_230 = and(_T_229, _T_153) @[el2_lib.scala 244:41] + node _T_231 = bits(io.trigger_pkt_any[0].tdata2, 11, 11) @[el2_lib.scala 244:74] + node _T_232 = bits(dec_i0_match_data[0], 11, 11) @[el2_lib.scala 244:86] + node _T_233 = eq(_T_231, _T_232) @[el2_lib.scala 244:78] + node _T_234 = mux(_T_230, UInt<1>("h01"), _T_233) @[el2_lib.scala 244:23] + _T_150[11] <= _T_234 @[el2_lib.scala 244:17] + node _T_235 = bits(io.trigger_pkt_any[0].tdata2, 11, 0) @[el2_lib.scala 244:28] + node _T_236 = andr(_T_235) @[el2_lib.scala 244:36] + node _T_237 = and(_T_236, _T_153) @[el2_lib.scala 244:41] + node _T_238 = bits(io.trigger_pkt_any[0].tdata2, 12, 12) @[el2_lib.scala 244:74] + node _T_239 = bits(dec_i0_match_data[0], 12, 12) @[el2_lib.scala 244:86] + node _T_240 = eq(_T_238, _T_239) @[el2_lib.scala 244:78] + node _T_241 = mux(_T_237, UInt<1>("h01"), _T_240) @[el2_lib.scala 244:23] + _T_150[12] <= _T_241 @[el2_lib.scala 244:17] + node _T_242 = bits(io.trigger_pkt_any[0].tdata2, 12, 0) @[el2_lib.scala 244:28] + node _T_243 = andr(_T_242) @[el2_lib.scala 244:36] + node _T_244 = and(_T_243, _T_153) @[el2_lib.scala 244:41] + node _T_245 = bits(io.trigger_pkt_any[0].tdata2, 13, 13) @[el2_lib.scala 244:74] + node _T_246 = bits(dec_i0_match_data[0], 13, 13) @[el2_lib.scala 244:86] + node _T_247 = eq(_T_245, _T_246) @[el2_lib.scala 244:78] + node _T_248 = mux(_T_244, UInt<1>("h01"), _T_247) @[el2_lib.scala 244:23] + _T_150[13] <= _T_248 @[el2_lib.scala 244:17] + node _T_249 = bits(io.trigger_pkt_any[0].tdata2, 13, 0) @[el2_lib.scala 244:28] + node _T_250 = andr(_T_249) @[el2_lib.scala 244:36] + node _T_251 = and(_T_250, _T_153) @[el2_lib.scala 244:41] + node _T_252 = bits(io.trigger_pkt_any[0].tdata2, 14, 14) @[el2_lib.scala 244:74] + node _T_253 = bits(dec_i0_match_data[0], 14, 14) @[el2_lib.scala 244:86] + node _T_254 = eq(_T_252, _T_253) @[el2_lib.scala 244:78] + node _T_255 = mux(_T_251, UInt<1>("h01"), _T_254) @[el2_lib.scala 244:23] + _T_150[14] <= _T_255 @[el2_lib.scala 244:17] + node _T_256 = bits(io.trigger_pkt_any[0].tdata2, 14, 0) @[el2_lib.scala 244:28] + node _T_257 = andr(_T_256) @[el2_lib.scala 244:36] + node _T_258 = and(_T_257, _T_153) @[el2_lib.scala 244:41] + node _T_259 = bits(io.trigger_pkt_any[0].tdata2, 15, 15) @[el2_lib.scala 244:74] + node _T_260 = bits(dec_i0_match_data[0], 15, 15) @[el2_lib.scala 244:86] + node _T_261 = eq(_T_259, _T_260) @[el2_lib.scala 244:78] + node _T_262 = mux(_T_258, UInt<1>("h01"), _T_261) @[el2_lib.scala 244:23] + _T_150[15] <= _T_262 @[el2_lib.scala 244:17] + node _T_263 = bits(io.trigger_pkt_any[0].tdata2, 15, 0) @[el2_lib.scala 244:28] + node _T_264 = andr(_T_263) @[el2_lib.scala 244:36] + node _T_265 = and(_T_264, _T_153) @[el2_lib.scala 244:41] + node _T_266 = bits(io.trigger_pkt_any[0].tdata2, 16, 16) @[el2_lib.scala 244:74] + node _T_267 = bits(dec_i0_match_data[0], 16, 16) @[el2_lib.scala 244:86] + node _T_268 = eq(_T_266, _T_267) @[el2_lib.scala 244:78] + node _T_269 = mux(_T_265, UInt<1>("h01"), _T_268) @[el2_lib.scala 244:23] + _T_150[16] <= _T_269 @[el2_lib.scala 244:17] + node _T_270 = bits(io.trigger_pkt_any[0].tdata2, 16, 0) @[el2_lib.scala 244:28] + node _T_271 = andr(_T_270) @[el2_lib.scala 244:36] + node _T_272 = and(_T_271, _T_153) @[el2_lib.scala 244:41] + node _T_273 = bits(io.trigger_pkt_any[0].tdata2, 17, 17) @[el2_lib.scala 244:74] + node _T_274 = bits(dec_i0_match_data[0], 17, 17) @[el2_lib.scala 244:86] + node _T_275 = eq(_T_273, _T_274) @[el2_lib.scala 244:78] + node _T_276 = mux(_T_272, UInt<1>("h01"), _T_275) @[el2_lib.scala 244:23] + _T_150[17] <= _T_276 @[el2_lib.scala 244:17] + node _T_277 = bits(io.trigger_pkt_any[0].tdata2, 17, 0) @[el2_lib.scala 244:28] + node _T_278 = andr(_T_277) @[el2_lib.scala 244:36] + node _T_279 = and(_T_278, _T_153) @[el2_lib.scala 244:41] + node _T_280 = bits(io.trigger_pkt_any[0].tdata2, 18, 18) @[el2_lib.scala 244:74] + node _T_281 = bits(dec_i0_match_data[0], 18, 18) @[el2_lib.scala 244:86] + node _T_282 = eq(_T_280, _T_281) @[el2_lib.scala 244:78] + node _T_283 = mux(_T_279, UInt<1>("h01"), _T_282) @[el2_lib.scala 244:23] + _T_150[18] <= _T_283 @[el2_lib.scala 244:17] + node _T_284 = bits(io.trigger_pkt_any[0].tdata2, 18, 0) @[el2_lib.scala 244:28] + node _T_285 = andr(_T_284) @[el2_lib.scala 244:36] + node _T_286 = and(_T_285, _T_153) @[el2_lib.scala 244:41] + node _T_287 = bits(io.trigger_pkt_any[0].tdata2, 19, 19) @[el2_lib.scala 244:74] + node _T_288 = bits(dec_i0_match_data[0], 19, 19) @[el2_lib.scala 244:86] + node _T_289 = eq(_T_287, _T_288) @[el2_lib.scala 244:78] + node _T_290 = mux(_T_286, UInt<1>("h01"), _T_289) @[el2_lib.scala 244:23] + _T_150[19] <= _T_290 @[el2_lib.scala 244:17] + node _T_291 = bits(io.trigger_pkt_any[0].tdata2, 19, 0) @[el2_lib.scala 244:28] + node _T_292 = andr(_T_291) @[el2_lib.scala 244:36] + node _T_293 = and(_T_292, _T_153) @[el2_lib.scala 244:41] + node _T_294 = bits(io.trigger_pkt_any[0].tdata2, 20, 20) @[el2_lib.scala 244:74] + node _T_295 = bits(dec_i0_match_data[0], 20, 20) @[el2_lib.scala 244:86] + node _T_296 = eq(_T_294, _T_295) @[el2_lib.scala 244:78] + node _T_297 = mux(_T_293, UInt<1>("h01"), _T_296) @[el2_lib.scala 244:23] + _T_150[20] <= _T_297 @[el2_lib.scala 244:17] + node _T_298 = bits(io.trigger_pkt_any[0].tdata2, 20, 0) @[el2_lib.scala 244:28] + node _T_299 = andr(_T_298) @[el2_lib.scala 244:36] + node _T_300 = and(_T_299, _T_153) @[el2_lib.scala 244:41] + node _T_301 = bits(io.trigger_pkt_any[0].tdata2, 21, 21) @[el2_lib.scala 244:74] + node _T_302 = bits(dec_i0_match_data[0], 21, 21) @[el2_lib.scala 244:86] + node _T_303 = eq(_T_301, _T_302) @[el2_lib.scala 244:78] + node _T_304 = mux(_T_300, UInt<1>("h01"), _T_303) @[el2_lib.scala 244:23] + _T_150[21] <= _T_304 @[el2_lib.scala 244:17] + node _T_305 = bits(io.trigger_pkt_any[0].tdata2, 21, 0) @[el2_lib.scala 244:28] + node _T_306 = andr(_T_305) @[el2_lib.scala 244:36] + node _T_307 = and(_T_306, _T_153) @[el2_lib.scala 244:41] + node _T_308 = bits(io.trigger_pkt_any[0].tdata2, 22, 22) @[el2_lib.scala 244:74] + node _T_309 = bits(dec_i0_match_data[0], 22, 22) @[el2_lib.scala 244:86] + node _T_310 = eq(_T_308, _T_309) @[el2_lib.scala 244:78] + node _T_311 = mux(_T_307, UInt<1>("h01"), _T_310) @[el2_lib.scala 244:23] + _T_150[22] <= _T_311 @[el2_lib.scala 244:17] + node _T_312 = bits(io.trigger_pkt_any[0].tdata2, 22, 0) @[el2_lib.scala 244:28] + node _T_313 = andr(_T_312) @[el2_lib.scala 244:36] + node _T_314 = and(_T_313, _T_153) @[el2_lib.scala 244:41] + node _T_315 = bits(io.trigger_pkt_any[0].tdata2, 23, 23) @[el2_lib.scala 244:74] + node _T_316 = bits(dec_i0_match_data[0], 23, 23) @[el2_lib.scala 244:86] + node _T_317 = eq(_T_315, _T_316) @[el2_lib.scala 244:78] + node _T_318 = mux(_T_314, UInt<1>("h01"), _T_317) @[el2_lib.scala 244:23] + _T_150[23] <= _T_318 @[el2_lib.scala 244:17] + node _T_319 = bits(io.trigger_pkt_any[0].tdata2, 23, 0) @[el2_lib.scala 244:28] + node _T_320 = andr(_T_319) @[el2_lib.scala 244:36] + node _T_321 = and(_T_320, _T_153) @[el2_lib.scala 244:41] + node _T_322 = bits(io.trigger_pkt_any[0].tdata2, 24, 24) @[el2_lib.scala 244:74] + node _T_323 = bits(dec_i0_match_data[0], 24, 24) @[el2_lib.scala 244:86] + node _T_324 = eq(_T_322, _T_323) @[el2_lib.scala 244:78] + node _T_325 = mux(_T_321, UInt<1>("h01"), _T_324) @[el2_lib.scala 244:23] + _T_150[24] <= _T_325 @[el2_lib.scala 244:17] + node _T_326 = bits(io.trigger_pkt_any[0].tdata2, 24, 0) @[el2_lib.scala 244:28] + node _T_327 = andr(_T_326) @[el2_lib.scala 244:36] + node _T_328 = and(_T_327, _T_153) @[el2_lib.scala 244:41] + node _T_329 = bits(io.trigger_pkt_any[0].tdata2, 25, 25) @[el2_lib.scala 244:74] + node _T_330 = bits(dec_i0_match_data[0], 25, 25) @[el2_lib.scala 244:86] + node _T_331 = eq(_T_329, _T_330) @[el2_lib.scala 244:78] + node _T_332 = mux(_T_328, UInt<1>("h01"), _T_331) @[el2_lib.scala 244:23] + _T_150[25] <= _T_332 @[el2_lib.scala 244:17] + node _T_333 = bits(io.trigger_pkt_any[0].tdata2, 25, 0) @[el2_lib.scala 244:28] + node _T_334 = andr(_T_333) @[el2_lib.scala 244:36] + node _T_335 = and(_T_334, _T_153) @[el2_lib.scala 244:41] + node _T_336 = bits(io.trigger_pkt_any[0].tdata2, 26, 26) @[el2_lib.scala 244:74] + node _T_337 = bits(dec_i0_match_data[0], 26, 26) @[el2_lib.scala 244:86] + node _T_338 = eq(_T_336, _T_337) @[el2_lib.scala 244:78] + node _T_339 = mux(_T_335, UInt<1>("h01"), _T_338) @[el2_lib.scala 244:23] + _T_150[26] <= _T_339 @[el2_lib.scala 244:17] + node _T_340 = bits(io.trigger_pkt_any[0].tdata2, 26, 0) @[el2_lib.scala 244:28] + node _T_341 = andr(_T_340) @[el2_lib.scala 244:36] + node _T_342 = and(_T_341, _T_153) @[el2_lib.scala 244:41] + node _T_343 = bits(io.trigger_pkt_any[0].tdata2, 27, 27) @[el2_lib.scala 244:74] + node _T_344 = bits(dec_i0_match_data[0], 27, 27) @[el2_lib.scala 244:86] + node _T_345 = eq(_T_343, _T_344) @[el2_lib.scala 244:78] + node _T_346 = mux(_T_342, UInt<1>("h01"), _T_345) @[el2_lib.scala 244:23] + _T_150[27] <= _T_346 @[el2_lib.scala 244:17] + node _T_347 = bits(io.trigger_pkt_any[0].tdata2, 27, 0) @[el2_lib.scala 244:28] + node _T_348 = andr(_T_347) @[el2_lib.scala 244:36] + node _T_349 = and(_T_348, _T_153) @[el2_lib.scala 244:41] + node _T_350 = bits(io.trigger_pkt_any[0].tdata2, 28, 28) @[el2_lib.scala 244:74] + node _T_351 = bits(dec_i0_match_data[0], 28, 28) @[el2_lib.scala 244:86] + node _T_352 = eq(_T_350, _T_351) @[el2_lib.scala 244:78] + node _T_353 = mux(_T_349, UInt<1>("h01"), _T_352) @[el2_lib.scala 244:23] + _T_150[28] <= _T_353 @[el2_lib.scala 244:17] + node _T_354 = bits(io.trigger_pkt_any[0].tdata2, 28, 0) @[el2_lib.scala 244:28] + node _T_355 = andr(_T_354) @[el2_lib.scala 244:36] + node _T_356 = and(_T_355, _T_153) @[el2_lib.scala 244:41] + node _T_357 = bits(io.trigger_pkt_any[0].tdata2, 29, 29) @[el2_lib.scala 244:74] + node _T_358 = bits(dec_i0_match_data[0], 29, 29) @[el2_lib.scala 244:86] + node _T_359 = eq(_T_357, _T_358) @[el2_lib.scala 244:78] + node _T_360 = mux(_T_356, UInt<1>("h01"), _T_359) @[el2_lib.scala 244:23] + _T_150[29] <= _T_360 @[el2_lib.scala 244:17] + node _T_361 = bits(io.trigger_pkt_any[0].tdata2, 29, 0) @[el2_lib.scala 244:28] + node _T_362 = andr(_T_361) @[el2_lib.scala 244:36] + node _T_363 = and(_T_362, _T_153) @[el2_lib.scala 244:41] + node _T_364 = bits(io.trigger_pkt_any[0].tdata2, 30, 30) @[el2_lib.scala 244:74] + node _T_365 = bits(dec_i0_match_data[0], 30, 30) @[el2_lib.scala 244:86] + node _T_366 = eq(_T_364, _T_365) @[el2_lib.scala 244:78] + node _T_367 = mux(_T_363, UInt<1>("h01"), _T_366) @[el2_lib.scala 244:23] + _T_150[30] <= _T_367 @[el2_lib.scala 244:17] + node _T_368 = bits(io.trigger_pkt_any[0].tdata2, 30, 0) @[el2_lib.scala 244:28] + node _T_369 = andr(_T_368) @[el2_lib.scala 244:36] + node _T_370 = and(_T_369, _T_153) @[el2_lib.scala 244:41] + node _T_371 = bits(io.trigger_pkt_any[0].tdata2, 31, 31) @[el2_lib.scala 244:74] + node _T_372 = bits(dec_i0_match_data[0], 31, 31) @[el2_lib.scala 244:86] + node _T_373 = eq(_T_371, _T_372) @[el2_lib.scala 244:78] + node _T_374 = mux(_T_370, UInt<1>("h01"), _T_373) @[el2_lib.scala 244:23] + _T_150[31] <= _T_374 @[el2_lib.scala 244:17] + node _T_375 = cat(_T_150[1], _T_150[0]) @[el2_lib.scala 245:14] + node _T_376 = cat(_T_150[3], _T_150[2]) @[el2_lib.scala 245:14] + node _T_377 = cat(_T_376, _T_375) @[el2_lib.scala 245:14] + node _T_378 = cat(_T_150[5], _T_150[4]) @[el2_lib.scala 245:14] + node _T_379 = cat(_T_150[7], _T_150[6]) @[el2_lib.scala 245:14] + node _T_380 = cat(_T_379, _T_378) @[el2_lib.scala 245:14] + node _T_381 = cat(_T_380, _T_377) @[el2_lib.scala 245:14] + node _T_382 = cat(_T_150[9], _T_150[8]) @[el2_lib.scala 245:14] + node _T_383 = cat(_T_150[11], _T_150[10]) @[el2_lib.scala 245:14] + node _T_384 = cat(_T_383, _T_382) @[el2_lib.scala 245:14] + node _T_385 = cat(_T_150[13], _T_150[12]) @[el2_lib.scala 245:14] + node _T_386 = cat(_T_150[15], _T_150[14]) @[el2_lib.scala 245:14] + node _T_387 = cat(_T_386, _T_385) @[el2_lib.scala 245:14] + node _T_388 = cat(_T_387, _T_384) @[el2_lib.scala 245:14] + node _T_389 = cat(_T_388, _T_381) @[el2_lib.scala 245:14] + node _T_390 = cat(_T_150[17], _T_150[16]) @[el2_lib.scala 245:14] + node _T_391 = cat(_T_150[19], _T_150[18]) @[el2_lib.scala 245:14] + node _T_392 = cat(_T_391, _T_390) @[el2_lib.scala 245:14] + node _T_393 = cat(_T_150[21], _T_150[20]) @[el2_lib.scala 245:14] + node _T_394 = cat(_T_150[23], _T_150[22]) @[el2_lib.scala 245:14] + node _T_395 = cat(_T_394, _T_393) @[el2_lib.scala 245:14] + node _T_396 = cat(_T_395, _T_392) @[el2_lib.scala 245:14] + node _T_397 = cat(_T_150[25], _T_150[24]) @[el2_lib.scala 245:14] + node _T_398 = cat(_T_150[27], _T_150[26]) @[el2_lib.scala 245:14] + node _T_399 = cat(_T_398, _T_397) @[el2_lib.scala 245:14] + node _T_400 = cat(_T_150[29], _T_150[28]) @[el2_lib.scala 245:14] + node _T_401 = cat(_T_150[31], _T_150[30]) @[el2_lib.scala 245:14] + node _T_402 = cat(_T_401, _T_400) @[el2_lib.scala 245:14] + node _T_403 = cat(_T_402, _T_399) @[el2_lib.scala 245:14] + node _T_404 = cat(_T_403, _T_396) @[el2_lib.scala 245:14] + node _T_405 = cat(_T_404, _T_389) @[el2_lib.scala 245:14] + node _T_406 = and(_T_148, _T_405) @[el2_dec_trigger.scala 15:109] + node _T_407 = and(io.trigger_pkt_any[1].execute, io.trigger_pkt_any[1].m) @[el2_dec_trigger.scala 15:83] + node _T_408 = bits(io.trigger_pkt_any[1].match_pkt, 0, 0) @[el2_dec_trigger.scala 15:216] + wire _T_409 : UInt<1>[32] @[el2_lib.scala 240:24] + node _T_410 = andr(io.trigger_pkt_any[1].tdata2) @[el2_lib.scala 241:45] + node _T_411 = not(_T_410) @[el2_lib.scala 241:39] + node _T_412 = and(_T_408, _T_411) @[el2_lib.scala 241:37] + node _T_413 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[el2_lib.scala 242:48] + node _T_414 = bits(dec_i0_match_data[1], 0, 0) @[el2_lib.scala 242:60] + node _T_415 = eq(_T_413, _T_414) @[el2_lib.scala 242:52] + node _T_416 = or(_T_412, _T_415) @[el2_lib.scala 242:41] + _T_409[0] <= _T_416 @[el2_lib.scala 242:18] + node _T_417 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[el2_lib.scala 244:28] + node _T_418 = andr(_T_417) @[el2_lib.scala 244:36] + node _T_419 = and(_T_418, _T_412) @[el2_lib.scala 244:41] + node _T_420 = bits(io.trigger_pkt_any[1].tdata2, 1, 1) @[el2_lib.scala 244:74] + node _T_421 = bits(dec_i0_match_data[1], 1, 1) @[el2_lib.scala 244:86] + node _T_422 = eq(_T_420, _T_421) @[el2_lib.scala 244:78] + node _T_423 = mux(_T_419, UInt<1>("h01"), _T_422) @[el2_lib.scala 244:23] + _T_409[1] <= _T_423 @[el2_lib.scala 244:17] + node _T_424 = bits(io.trigger_pkt_any[1].tdata2, 1, 0) @[el2_lib.scala 244:28] + node _T_425 = andr(_T_424) @[el2_lib.scala 244:36] + node _T_426 = and(_T_425, _T_412) @[el2_lib.scala 244:41] + node _T_427 = bits(io.trigger_pkt_any[1].tdata2, 2, 2) @[el2_lib.scala 244:74] + node _T_428 = bits(dec_i0_match_data[1], 2, 2) @[el2_lib.scala 244:86] + node _T_429 = eq(_T_427, _T_428) @[el2_lib.scala 244:78] + node _T_430 = mux(_T_426, UInt<1>("h01"), _T_429) @[el2_lib.scala 244:23] + _T_409[2] <= _T_430 @[el2_lib.scala 244:17] + node _T_431 = bits(io.trigger_pkt_any[1].tdata2, 2, 0) @[el2_lib.scala 244:28] + node _T_432 = andr(_T_431) @[el2_lib.scala 244:36] + node _T_433 = and(_T_432, _T_412) @[el2_lib.scala 244:41] + node _T_434 = bits(io.trigger_pkt_any[1].tdata2, 3, 3) @[el2_lib.scala 244:74] + node _T_435 = bits(dec_i0_match_data[1], 3, 3) @[el2_lib.scala 244:86] + node _T_436 = eq(_T_434, _T_435) @[el2_lib.scala 244:78] + node _T_437 = mux(_T_433, UInt<1>("h01"), _T_436) @[el2_lib.scala 244:23] + _T_409[3] <= _T_437 @[el2_lib.scala 244:17] + node _T_438 = bits(io.trigger_pkt_any[1].tdata2, 3, 0) @[el2_lib.scala 244:28] + node _T_439 = andr(_T_438) @[el2_lib.scala 244:36] + node _T_440 = and(_T_439, _T_412) @[el2_lib.scala 244:41] + node _T_441 = bits(io.trigger_pkt_any[1].tdata2, 4, 4) @[el2_lib.scala 244:74] + node _T_442 = bits(dec_i0_match_data[1], 4, 4) @[el2_lib.scala 244:86] + node _T_443 = eq(_T_441, _T_442) @[el2_lib.scala 244:78] + node _T_444 = mux(_T_440, UInt<1>("h01"), _T_443) @[el2_lib.scala 244:23] + _T_409[4] <= _T_444 @[el2_lib.scala 244:17] + node _T_445 = bits(io.trigger_pkt_any[1].tdata2, 4, 0) @[el2_lib.scala 244:28] + node _T_446 = andr(_T_445) @[el2_lib.scala 244:36] + node _T_447 = and(_T_446, _T_412) @[el2_lib.scala 244:41] + node _T_448 = bits(io.trigger_pkt_any[1].tdata2, 5, 5) @[el2_lib.scala 244:74] + node _T_449 = bits(dec_i0_match_data[1], 5, 5) @[el2_lib.scala 244:86] + node _T_450 = eq(_T_448, _T_449) @[el2_lib.scala 244:78] + node _T_451 = mux(_T_447, UInt<1>("h01"), _T_450) @[el2_lib.scala 244:23] + _T_409[5] <= _T_451 @[el2_lib.scala 244:17] + node _T_452 = bits(io.trigger_pkt_any[1].tdata2, 5, 0) @[el2_lib.scala 244:28] + node _T_453 = andr(_T_452) @[el2_lib.scala 244:36] + node _T_454 = and(_T_453, _T_412) @[el2_lib.scala 244:41] + node _T_455 = bits(io.trigger_pkt_any[1].tdata2, 6, 6) @[el2_lib.scala 244:74] + node _T_456 = bits(dec_i0_match_data[1], 6, 6) @[el2_lib.scala 244:86] + node _T_457 = eq(_T_455, _T_456) @[el2_lib.scala 244:78] + node _T_458 = mux(_T_454, UInt<1>("h01"), _T_457) @[el2_lib.scala 244:23] + _T_409[6] <= _T_458 @[el2_lib.scala 244:17] + node _T_459 = bits(io.trigger_pkt_any[1].tdata2, 6, 0) @[el2_lib.scala 244:28] + node _T_460 = andr(_T_459) @[el2_lib.scala 244:36] + node _T_461 = and(_T_460, _T_412) @[el2_lib.scala 244:41] + node _T_462 = bits(io.trigger_pkt_any[1].tdata2, 7, 7) @[el2_lib.scala 244:74] + node _T_463 = bits(dec_i0_match_data[1], 7, 7) @[el2_lib.scala 244:86] + node _T_464 = eq(_T_462, _T_463) @[el2_lib.scala 244:78] + node _T_465 = mux(_T_461, UInt<1>("h01"), _T_464) @[el2_lib.scala 244:23] + _T_409[7] <= _T_465 @[el2_lib.scala 244:17] + node _T_466 = bits(io.trigger_pkt_any[1].tdata2, 7, 0) @[el2_lib.scala 244:28] + node _T_467 = andr(_T_466) @[el2_lib.scala 244:36] + node _T_468 = and(_T_467, _T_412) @[el2_lib.scala 244:41] + node _T_469 = bits(io.trigger_pkt_any[1].tdata2, 8, 8) @[el2_lib.scala 244:74] + node _T_470 = bits(dec_i0_match_data[1], 8, 8) @[el2_lib.scala 244:86] + node _T_471 = eq(_T_469, _T_470) @[el2_lib.scala 244:78] + node _T_472 = mux(_T_468, UInt<1>("h01"), _T_471) @[el2_lib.scala 244:23] + _T_409[8] <= _T_472 @[el2_lib.scala 244:17] + node _T_473 = bits(io.trigger_pkt_any[1].tdata2, 8, 0) @[el2_lib.scala 244:28] + node _T_474 = andr(_T_473) @[el2_lib.scala 244:36] + node _T_475 = and(_T_474, _T_412) @[el2_lib.scala 244:41] + node _T_476 = bits(io.trigger_pkt_any[1].tdata2, 9, 9) @[el2_lib.scala 244:74] + node _T_477 = bits(dec_i0_match_data[1], 9, 9) @[el2_lib.scala 244:86] + node _T_478 = eq(_T_476, _T_477) @[el2_lib.scala 244:78] + node _T_479 = mux(_T_475, UInt<1>("h01"), _T_478) @[el2_lib.scala 244:23] + _T_409[9] <= _T_479 @[el2_lib.scala 244:17] + node _T_480 = bits(io.trigger_pkt_any[1].tdata2, 9, 0) @[el2_lib.scala 244:28] + node _T_481 = andr(_T_480) @[el2_lib.scala 244:36] + node _T_482 = and(_T_481, _T_412) @[el2_lib.scala 244:41] + node _T_483 = bits(io.trigger_pkt_any[1].tdata2, 10, 10) @[el2_lib.scala 244:74] + node _T_484 = bits(dec_i0_match_data[1], 10, 10) @[el2_lib.scala 244:86] + node _T_485 = eq(_T_483, _T_484) @[el2_lib.scala 244:78] + node _T_486 = mux(_T_482, UInt<1>("h01"), _T_485) @[el2_lib.scala 244:23] + _T_409[10] <= _T_486 @[el2_lib.scala 244:17] + node _T_487 = bits(io.trigger_pkt_any[1].tdata2, 10, 0) @[el2_lib.scala 244:28] + node _T_488 = andr(_T_487) @[el2_lib.scala 244:36] + node _T_489 = and(_T_488, _T_412) @[el2_lib.scala 244:41] + node _T_490 = bits(io.trigger_pkt_any[1].tdata2, 11, 11) @[el2_lib.scala 244:74] + node _T_491 = bits(dec_i0_match_data[1], 11, 11) @[el2_lib.scala 244:86] + node _T_492 = eq(_T_490, _T_491) @[el2_lib.scala 244:78] + node _T_493 = mux(_T_489, UInt<1>("h01"), _T_492) @[el2_lib.scala 244:23] + _T_409[11] <= _T_493 @[el2_lib.scala 244:17] + node _T_494 = bits(io.trigger_pkt_any[1].tdata2, 11, 0) @[el2_lib.scala 244:28] + node _T_495 = andr(_T_494) @[el2_lib.scala 244:36] + node _T_496 = and(_T_495, _T_412) @[el2_lib.scala 244:41] + node _T_497 = bits(io.trigger_pkt_any[1].tdata2, 12, 12) @[el2_lib.scala 244:74] + node _T_498 = bits(dec_i0_match_data[1], 12, 12) @[el2_lib.scala 244:86] + node _T_499 = eq(_T_497, _T_498) @[el2_lib.scala 244:78] + node _T_500 = mux(_T_496, UInt<1>("h01"), _T_499) @[el2_lib.scala 244:23] + _T_409[12] <= _T_500 @[el2_lib.scala 244:17] + node _T_501 = bits(io.trigger_pkt_any[1].tdata2, 12, 0) @[el2_lib.scala 244:28] + node _T_502 = andr(_T_501) @[el2_lib.scala 244:36] + node _T_503 = and(_T_502, _T_412) @[el2_lib.scala 244:41] + node _T_504 = bits(io.trigger_pkt_any[1].tdata2, 13, 13) @[el2_lib.scala 244:74] + node _T_505 = bits(dec_i0_match_data[1], 13, 13) @[el2_lib.scala 244:86] + node _T_506 = eq(_T_504, _T_505) @[el2_lib.scala 244:78] + node _T_507 = mux(_T_503, UInt<1>("h01"), _T_506) @[el2_lib.scala 244:23] + _T_409[13] <= _T_507 @[el2_lib.scala 244:17] + node _T_508 = bits(io.trigger_pkt_any[1].tdata2, 13, 0) @[el2_lib.scala 244:28] + node _T_509 = andr(_T_508) @[el2_lib.scala 244:36] + node _T_510 = and(_T_509, _T_412) @[el2_lib.scala 244:41] + node _T_511 = bits(io.trigger_pkt_any[1].tdata2, 14, 14) @[el2_lib.scala 244:74] + node _T_512 = bits(dec_i0_match_data[1], 14, 14) @[el2_lib.scala 244:86] + node _T_513 = eq(_T_511, _T_512) @[el2_lib.scala 244:78] + node _T_514 = mux(_T_510, UInt<1>("h01"), _T_513) @[el2_lib.scala 244:23] + _T_409[14] <= _T_514 @[el2_lib.scala 244:17] + node _T_515 = bits(io.trigger_pkt_any[1].tdata2, 14, 0) @[el2_lib.scala 244:28] + node _T_516 = andr(_T_515) @[el2_lib.scala 244:36] + node _T_517 = and(_T_516, _T_412) @[el2_lib.scala 244:41] + node _T_518 = bits(io.trigger_pkt_any[1].tdata2, 15, 15) @[el2_lib.scala 244:74] + node _T_519 = bits(dec_i0_match_data[1], 15, 15) @[el2_lib.scala 244:86] + node _T_520 = eq(_T_518, _T_519) @[el2_lib.scala 244:78] + node _T_521 = mux(_T_517, UInt<1>("h01"), _T_520) @[el2_lib.scala 244:23] + _T_409[15] <= _T_521 @[el2_lib.scala 244:17] + node _T_522 = bits(io.trigger_pkt_any[1].tdata2, 15, 0) @[el2_lib.scala 244:28] + node _T_523 = andr(_T_522) @[el2_lib.scala 244:36] + node _T_524 = and(_T_523, _T_412) @[el2_lib.scala 244:41] + node _T_525 = bits(io.trigger_pkt_any[1].tdata2, 16, 16) @[el2_lib.scala 244:74] + node _T_526 = bits(dec_i0_match_data[1], 16, 16) @[el2_lib.scala 244:86] + node _T_527 = eq(_T_525, _T_526) @[el2_lib.scala 244:78] + node _T_528 = mux(_T_524, UInt<1>("h01"), _T_527) @[el2_lib.scala 244:23] + _T_409[16] <= _T_528 @[el2_lib.scala 244:17] + node _T_529 = bits(io.trigger_pkt_any[1].tdata2, 16, 0) @[el2_lib.scala 244:28] + node _T_530 = andr(_T_529) @[el2_lib.scala 244:36] + node _T_531 = and(_T_530, _T_412) @[el2_lib.scala 244:41] + node _T_532 = bits(io.trigger_pkt_any[1].tdata2, 17, 17) @[el2_lib.scala 244:74] + node _T_533 = bits(dec_i0_match_data[1], 17, 17) @[el2_lib.scala 244:86] + node _T_534 = eq(_T_532, _T_533) @[el2_lib.scala 244:78] + node _T_535 = mux(_T_531, UInt<1>("h01"), _T_534) @[el2_lib.scala 244:23] + _T_409[17] <= _T_535 @[el2_lib.scala 244:17] + node _T_536 = bits(io.trigger_pkt_any[1].tdata2, 17, 0) @[el2_lib.scala 244:28] + node _T_537 = andr(_T_536) @[el2_lib.scala 244:36] + node _T_538 = and(_T_537, _T_412) @[el2_lib.scala 244:41] + node _T_539 = bits(io.trigger_pkt_any[1].tdata2, 18, 18) @[el2_lib.scala 244:74] + node _T_540 = bits(dec_i0_match_data[1], 18, 18) @[el2_lib.scala 244:86] + node _T_541 = eq(_T_539, _T_540) @[el2_lib.scala 244:78] + node _T_542 = mux(_T_538, UInt<1>("h01"), _T_541) @[el2_lib.scala 244:23] + _T_409[18] <= _T_542 @[el2_lib.scala 244:17] + node _T_543 = bits(io.trigger_pkt_any[1].tdata2, 18, 0) @[el2_lib.scala 244:28] + node _T_544 = andr(_T_543) @[el2_lib.scala 244:36] + node _T_545 = and(_T_544, _T_412) @[el2_lib.scala 244:41] + node _T_546 = bits(io.trigger_pkt_any[1].tdata2, 19, 19) @[el2_lib.scala 244:74] + node _T_547 = bits(dec_i0_match_data[1], 19, 19) @[el2_lib.scala 244:86] + node _T_548 = eq(_T_546, _T_547) @[el2_lib.scala 244:78] + node _T_549 = mux(_T_545, UInt<1>("h01"), _T_548) @[el2_lib.scala 244:23] + _T_409[19] <= _T_549 @[el2_lib.scala 244:17] + node _T_550 = bits(io.trigger_pkt_any[1].tdata2, 19, 0) @[el2_lib.scala 244:28] + node _T_551 = andr(_T_550) @[el2_lib.scala 244:36] + node _T_552 = and(_T_551, _T_412) @[el2_lib.scala 244:41] + node _T_553 = bits(io.trigger_pkt_any[1].tdata2, 20, 20) @[el2_lib.scala 244:74] + node _T_554 = bits(dec_i0_match_data[1], 20, 20) @[el2_lib.scala 244:86] + node _T_555 = eq(_T_553, _T_554) @[el2_lib.scala 244:78] + node _T_556 = mux(_T_552, UInt<1>("h01"), _T_555) @[el2_lib.scala 244:23] + _T_409[20] <= _T_556 @[el2_lib.scala 244:17] + node _T_557 = bits(io.trigger_pkt_any[1].tdata2, 20, 0) @[el2_lib.scala 244:28] + node _T_558 = andr(_T_557) @[el2_lib.scala 244:36] + node _T_559 = and(_T_558, _T_412) @[el2_lib.scala 244:41] + node _T_560 = bits(io.trigger_pkt_any[1].tdata2, 21, 21) @[el2_lib.scala 244:74] + node _T_561 = bits(dec_i0_match_data[1], 21, 21) @[el2_lib.scala 244:86] + node _T_562 = eq(_T_560, _T_561) @[el2_lib.scala 244:78] + node _T_563 = mux(_T_559, UInt<1>("h01"), _T_562) @[el2_lib.scala 244:23] + _T_409[21] <= _T_563 @[el2_lib.scala 244:17] + node _T_564 = bits(io.trigger_pkt_any[1].tdata2, 21, 0) @[el2_lib.scala 244:28] + node _T_565 = andr(_T_564) @[el2_lib.scala 244:36] + node _T_566 = and(_T_565, _T_412) @[el2_lib.scala 244:41] + node _T_567 = bits(io.trigger_pkt_any[1].tdata2, 22, 22) @[el2_lib.scala 244:74] + node _T_568 = bits(dec_i0_match_data[1], 22, 22) @[el2_lib.scala 244:86] + node _T_569 = eq(_T_567, _T_568) @[el2_lib.scala 244:78] + node _T_570 = mux(_T_566, UInt<1>("h01"), _T_569) @[el2_lib.scala 244:23] + _T_409[22] <= _T_570 @[el2_lib.scala 244:17] + node _T_571 = bits(io.trigger_pkt_any[1].tdata2, 22, 0) @[el2_lib.scala 244:28] + node _T_572 = andr(_T_571) @[el2_lib.scala 244:36] + node _T_573 = and(_T_572, _T_412) @[el2_lib.scala 244:41] + node _T_574 = bits(io.trigger_pkt_any[1].tdata2, 23, 23) @[el2_lib.scala 244:74] + node _T_575 = bits(dec_i0_match_data[1], 23, 23) @[el2_lib.scala 244:86] + node _T_576 = eq(_T_574, _T_575) @[el2_lib.scala 244:78] + node _T_577 = mux(_T_573, UInt<1>("h01"), _T_576) @[el2_lib.scala 244:23] + _T_409[23] <= _T_577 @[el2_lib.scala 244:17] + node _T_578 = bits(io.trigger_pkt_any[1].tdata2, 23, 0) @[el2_lib.scala 244:28] + node _T_579 = andr(_T_578) @[el2_lib.scala 244:36] + node _T_580 = and(_T_579, _T_412) @[el2_lib.scala 244:41] + node _T_581 = bits(io.trigger_pkt_any[1].tdata2, 24, 24) @[el2_lib.scala 244:74] + node _T_582 = bits(dec_i0_match_data[1], 24, 24) @[el2_lib.scala 244:86] + node _T_583 = eq(_T_581, _T_582) @[el2_lib.scala 244:78] + node _T_584 = mux(_T_580, UInt<1>("h01"), _T_583) @[el2_lib.scala 244:23] + _T_409[24] <= _T_584 @[el2_lib.scala 244:17] + node _T_585 = bits(io.trigger_pkt_any[1].tdata2, 24, 0) @[el2_lib.scala 244:28] + node _T_586 = andr(_T_585) @[el2_lib.scala 244:36] + node _T_587 = and(_T_586, _T_412) @[el2_lib.scala 244:41] + node _T_588 = bits(io.trigger_pkt_any[1].tdata2, 25, 25) @[el2_lib.scala 244:74] + node _T_589 = bits(dec_i0_match_data[1], 25, 25) @[el2_lib.scala 244:86] + node _T_590 = eq(_T_588, _T_589) @[el2_lib.scala 244:78] + node _T_591 = mux(_T_587, UInt<1>("h01"), _T_590) @[el2_lib.scala 244:23] + _T_409[25] <= _T_591 @[el2_lib.scala 244:17] + node _T_592 = bits(io.trigger_pkt_any[1].tdata2, 25, 0) @[el2_lib.scala 244:28] + node _T_593 = andr(_T_592) @[el2_lib.scala 244:36] + node _T_594 = and(_T_593, _T_412) @[el2_lib.scala 244:41] + node _T_595 = bits(io.trigger_pkt_any[1].tdata2, 26, 26) @[el2_lib.scala 244:74] + node _T_596 = bits(dec_i0_match_data[1], 26, 26) @[el2_lib.scala 244:86] + node _T_597 = eq(_T_595, _T_596) @[el2_lib.scala 244:78] + node _T_598 = mux(_T_594, UInt<1>("h01"), _T_597) @[el2_lib.scala 244:23] + _T_409[26] <= _T_598 @[el2_lib.scala 244:17] + node _T_599 = bits(io.trigger_pkt_any[1].tdata2, 26, 0) @[el2_lib.scala 244:28] + node _T_600 = andr(_T_599) @[el2_lib.scala 244:36] + node _T_601 = and(_T_600, _T_412) @[el2_lib.scala 244:41] + node _T_602 = bits(io.trigger_pkt_any[1].tdata2, 27, 27) @[el2_lib.scala 244:74] + node _T_603 = bits(dec_i0_match_data[1], 27, 27) @[el2_lib.scala 244:86] + node _T_604 = eq(_T_602, _T_603) @[el2_lib.scala 244:78] + node _T_605 = mux(_T_601, UInt<1>("h01"), _T_604) @[el2_lib.scala 244:23] + _T_409[27] <= _T_605 @[el2_lib.scala 244:17] + node _T_606 = bits(io.trigger_pkt_any[1].tdata2, 27, 0) @[el2_lib.scala 244:28] + node _T_607 = andr(_T_606) @[el2_lib.scala 244:36] + node _T_608 = and(_T_607, _T_412) @[el2_lib.scala 244:41] + node _T_609 = bits(io.trigger_pkt_any[1].tdata2, 28, 28) @[el2_lib.scala 244:74] + node _T_610 = bits(dec_i0_match_data[1], 28, 28) @[el2_lib.scala 244:86] + node _T_611 = eq(_T_609, _T_610) @[el2_lib.scala 244:78] + node _T_612 = mux(_T_608, UInt<1>("h01"), _T_611) @[el2_lib.scala 244:23] + _T_409[28] <= _T_612 @[el2_lib.scala 244:17] + node _T_613 = bits(io.trigger_pkt_any[1].tdata2, 28, 0) @[el2_lib.scala 244:28] + node _T_614 = andr(_T_613) @[el2_lib.scala 244:36] + node _T_615 = and(_T_614, _T_412) @[el2_lib.scala 244:41] + node _T_616 = bits(io.trigger_pkt_any[1].tdata2, 29, 29) @[el2_lib.scala 244:74] + node _T_617 = bits(dec_i0_match_data[1], 29, 29) @[el2_lib.scala 244:86] + node _T_618 = eq(_T_616, _T_617) @[el2_lib.scala 244:78] + node _T_619 = mux(_T_615, UInt<1>("h01"), _T_618) @[el2_lib.scala 244:23] + _T_409[29] <= _T_619 @[el2_lib.scala 244:17] + node _T_620 = bits(io.trigger_pkt_any[1].tdata2, 29, 0) @[el2_lib.scala 244:28] + node _T_621 = andr(_T_620) @[el2_lib.scala 244:36] + node _T_622 = and(_T_621, _T_412) @[el2_lib.scala 244:41] + node _T_623 = bits(io.trigger_pkt_any[1].tdata2, 30, 30) @[el2_lib.scala 244:74] + node _T_624 = bits(dec_i0_match_data[1], 30, 30) @[el2_lib.scala 244:86] + node _T_625 = eq(_T_623, _T_624) @[el2_lib.scala 244:78] + node _T_626 = mux(_T_622, UInt<1>("h01"), _T_625) @[el2_lib.scala 244:23] + _T_409[30] <= _T_626 @[el2_lib.scala 244:17] + node _T_627 = bits(io.trigger_pkt_any[1].tdata2, 30, 0) @[el2_lib.scala 244:28] + node _T_628 = andr(_T_627) @[el2_lib.scala 244:36] + node _T_629 = and(_T_628, _T_412) @[el2_lib.scala 244:41] + node _T_630 = bits(io.trigger_pkt_any[1].tdata2, 31, 31) @[el2_lib.scala 244:74] + node _T_631 = bits(dec_i0_match_data[1], 31, 31) @[el2_lib.scala 244:86] + node _T_632 = eq(_T_630, _T_631) @[el2_lib.scala 244:78] + node _T_633 = mux(_T_629, UInt<1>("h01"), _T_632) @[el2_lib.scala 244:23] + _T_409[31] <= _T_633 @[el2_lib.scala 244:17] + node _T_634 = cat(_T_409[1], _T_409[0]) @[el2_lib.scala 245:14] + node _T_635 = cat(_T_409[3], _T_409[2]) @[el2_lib.scala 245:14] + node _T_636 = cat(_T_635, _T_634) @[el2_lib.scala 245:14] + node _T_637 = cat(_T_409[5], _T_409[4]) @[el2_lib.scala 245:14] + node _T_638 = cat(_T_409[7], _T_409[6]) @[el2_lib.scala 245:14] + node _T_639 = cat(_T_638, _T_637) @[el2_lib.scala 245:14] + node _T_640 = cat(_T_639, _T_636) @[el2_lib.scala 245:14] + node _T_641 = cat(_T_409[9], _T_409[8]) @[el2_lib.scala 245:14] + node _T_642 = cat(_T_409[11], _T_409[10]) @[el2_lib.scala 245:14] + node _T_643 = cat(_T_642, _T_641) @[el2_lib.scala 245:14] + node _T_644 = cat(_T_409[13], _T_409[12]) @[el2_lib.scala 245:14] + node _T_645 = cat(_T_409[15], _T_409[14]) @[el2_lib.scala 245:14] + node _T_646 = cat(_T_645, _T_644) @[el2_lib.scala 245:14] + node _T_647 = cat(_T_646, _T_643) @[el2_lib.scala 245:14] + node _T_648 = cat(_T_647, _T_640) @[el2_lib.scala 245:14] + node _T_649 = cat(_T_409[17], _T_409[16]) @[el2_lib.scala 245:14] + node _T_650 = cat(_T_409[19], _T_409[18]) @[el2_lib.scala 245:14] + node _T_651 = cat(_T_650, _T_649) @[el2_lib.scala 245:14] + node _T_652 = cat(_T_409[21], _T_409[20]) @[el2_lib.scala 245:14] + node _T_653 = cat(_T_409[23], _T_409[22]) @[el2_lib.scala 245:14] + node _T_654 = cat(_T_653, _T_652) @[el2_lib.scala 245:14] + node _T_655 = cat(_T_654, _T_651) @[el2_lib.scala 245:14] + node _T_656 = cat(_T_409[25], _T_409[24]) @[el2_lib.scala 245:14] + node _T_657 = cat(_T_409[27], _T_409[26]) @[el2_lib.scala 245:14] + node _T_658 = cat(_T_657, _T_656) @[el2_lib.scala 245:14] + node _T_659 = cat(_T_409[29], _T_409[28]) @[el2_lib.scala 245:14] + node _T_660 = cat(_T_409[31], _T_409[30]) @[el2_lib.scala 245:14] + node _T_661 = cat(_T_660, _T_659) @[el2_lib.scala 245:14] + node _T_662 = cat(_T_661, _T_658) @[el2_lib.scala 245:14] + node _T_663 = cat(_T_662, _T_655) @[el2_lib.scala 245:14] + node _T_664 = cat(_T_663, _T_648) @[el2_lib.scala 245:14] + node _T_665 = and(_T_407, _T_664) @[el2_dec_trigger.scala 15:109] + node _T_666 = and(io.trigger_pkt_any[2].execute, io.trigger_pkt_any[2].m) @[el2_dec_trigger.scala 15:83] + node _T_667 = bits(io.trigger_pkt_any[2].match_pkt, 0, 0) @[el2_dec_trigger.scala 15:216] + wire _T_668 : UInt<1>[32] @[el2_lib.scala 240:24] + node _T_669 = andr(io.trigger_pkt_any[2].tdata2) @[el2_lib.scala 241:45] + node _T_670 = not(_T_669) @[el2_lib.scala 241:39] + node _T_671 = and(_T_667, _T_670) @[el2_lib.scala 241:37] + node _T_672 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[el2_lib.scala 242:48] + node _T_673 = bits(dec_i0_match_data[2], 0, 0) @[el2_lib.scala 242:60] + node _T_674 = eq(_T_672, _T_673) @[el2_lib.scala 242:52] + node _T_675 = or(_T_671, _T_674) @[el2_lib.scala 242:41] + _T_668[0] <= _T_675 @[el2_lib.scala 242:18] + node _T_676 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[el2_lib.scala 244:28] + node _T_677 = andr(_T_676) @[el2_lib.scala 244:36] + node _T_678 = and(_T_677, _T_671) @[el2_lib.scala 244:41] + node _T_679 = bits(io.trigger_pkt_any[2].tdata2, 1, 1) @[el2_lib.scala 244:74] + node _T_680 = bits(dec_i0_match_data[2], 1, 1) @[el2_lib.scala 244:86] + node _T_681 = eq(_T_679, _T_680) @[el2_lib.scala 244:78] + node _T_682 = mux(_T_678, UInt<1>("h01"), _T_681) @[el2_lib.scala 244:23] + _T_668[1] <= _T_682 @[el2_lib.scala 244:17] + node _T_683 = bits(io.trigger_pkt_any[2].tdata2, 1, 0) @[el2_lib.scala 244:28] + node _T_684 = andr(_T_683) @[el2_lib.scala 244:36] + node _T_685 = and(_T_684, _T_671) @[el2_lib.scala 244:41] + node _T_686 = bits(io.trigger_pkt_any[2].tdata2, 2, 2) @[el2_lib.scala 244:74] + node _T_687 = bits(dec_i0_match_data[2], 2, 2) @[el2_lib.scala 244:86] + node _T_688 = eq(_T_686, _T_687) @[el2_lib.scala 244:78] + node _T_689 = mux(_T_685, UInt<1>("h01"), _T_688) @[el2_lib.scala 244:23] + _T_668[2] <= _T_689 @[el2_lib.scala 244:17] + node _T_690 = bits(io.trigger_pkt_any[2].tdata2, 2, 0) @[el2_lib.scala 244:28] + node _T_691 = andr(_T_690) @[el2_lib.scala 244:36] + node _T_692 = and(_T_691, _T_671) @[el2_lib.scala 244:41] + node _T_693 = bits(io.trigger_pkt_any[2].tdata2, 3, 3) @[el2_lib.scala 244:74] + node _T_694 = bits(dec_i0_match_data[2], 3, 3) @[el2_lib.scala 244:86] + node _T_695 = eq(_T_693, _T_694) @[el2_lib.scala 244:78] + node _T_696 = mux(_T_692, UInt<1>("h01"), _T_695) @[el2_lib.scala 244:23] + _T_668[3] <= _T_696 @[el2_lib.scala 244:17] + node _T_697 = bits(io.trigger_pkt_any[2].tdata2, 3, 0) @[el2_lib.scala 244:28] + node _T_698 = andr(_T_697) @[el2_lib.scala 244:36] + node _T_699 = and(_T_698, _T_671) @[el2_lib.scala 244:41] + node _T_700 = bits(io.trigger_pkt_any[2].tdata2, 4, 4) @[el2_lib.scala 244:74] + node _T_701 = bits(dec_i0_match_data[2], 4, 4) @[el2_lib.scala 244:86] + node _T_702 = eq(_T_700, _T_701) @[el2_lib.scala 244:78] + node _T_703 = mux(_T_699, UInt<1>("h01"), _T_702) @[el2_lib.scala 244:23] + _T_668[4] <= _T_703 @[el2_lib.scala 244:17] + node _T_704 = bits(io.trigger_pkt_any[2].tdata2, 4, 0) @[el2_lib.scala 244:28] + node _T_705 = andr(_T_704) @[el2_lib.scala 244:36] + node _T_706 = and(_T_705, _T_671) @[el2_lib.scala 244:41] + node _T_707 = bits(io.trigger_pkt_any[2].tdata2, 5, 5) @[el2_lib.scala 244:74] + node _T_708 = bits(dec_i0_match_data[2], 5, 5) @[el2_lib.scala 244:86] + node _T_709 = eq(_T_707, _T_708) @[el2_lib.scala 244:78] + node _T_710 = mux(_T_706, UInt<1>("h01"), _T_709) @[el2_lib.scala 244:23] + _T_668[5] <= _T_710 @[el2_lib.scala 244:17] + node _T_711 = bits(io.trigger_pkt_any[2].tdata2, 5, 0) @[el2_lib.scala 244:28] + node _T_712 = andr(_T_711) @[el2_lib.scala 244:36] + node _T_713 = and(_T_712, _T_671) @[el2_lib.scala 244:41] + node _T_714 = bits(io.trigger_pkt_any[2].tdata2, 6, 6) @[el2_lib.scala 244:74] + node _T_715 = bits(dec_i0_match_data[2], 6, 6) @[el2_lib.scala 244:86] + node _T_716 = eq(_T_714, _T_715) @[el2_lib.scala 244:78] + node _T_717 = mux(_T_713, UInt<1>("h01"), _T_716) @[el2_lib.scala 244:23] + _T_668[6] <= _T_717 @[el2_lib.scala 244:17] + node _T_718 = bits(io.trigger_pkt_any[2].tdata2, 6, 0) @[el2_lib.scala 244:28] + node _T_719 = andr(_T_718) @[el2_lib.scala 244:36] + node _T_720 = and(_T_719, _T_671) @[el2_lib.scala 244:41] + node _T_721 = bits(io.trigger_pkt_any[2].tdata2, 7, 7) @[el2_lib.scala 244:74] + node _T_722 = bits(dec_i0_match_data[2], 7, 7) @[el2_lib.scala 244:86] + node _T_723 = eq(_T_721, _T_722) @[el2_lib.scala 244:78] + node _T_724 = mux(_T_720, UInt<1>("h01"), _T_723) @[el2_lib.scala 244:23] + _T_668[7] <= _T_724 @[el2_lib.scala 244:17] + node _T_725 = bits(io.trigger_pkt_any[2].tdata2, 7, 0) @[el2_lib.scala 244:28] + node _T_726 = andr(_T_725) @[el2_lib.scala 244:36] + node _T_727 = and(_T_726, _T_671) @[el2_lib.scala 244:41] + node _T_728 = bits(io.trigger_pkt_any[2].tdata2, 8, 8) @[el2_lib.scala 244:74] + node _T_729 = bits(dec_i0_match_data[2], 8, 8) @[el2_lib.scala 244:86] + node _T_730 = eq(_T_728, _T_729) @[el2_lib.scala 244:78] + node _T_731 = mux(_T_727, UInt<1>("h01"), _T_730) @[el2_lib.scala 244:23] + _T_668[8] <= _T_731 @[el2_lib.scala 244:17] + node _T_732 = bits(io.trigger_pkt_any[2].tdata2, 8, 0) @[el2_lib.scala 244:28] + node _T_733 = andr(_T_732) @[el2_lib.scala 244:36] + node _T_734 = and(_T_733, _T_671) @[el2_lib.scala 244:41] + node _T_735 = bits(io.trigger_pkt_any[2].tdata2, 9, 9) @[el2_lib.scala 244:74] + node _T_736 = bits(dec_i0_match_data[2], 9, 9) @[el2_lib.scala 244:86] + node _T_737 = eq(_T_735, _T_736) @[el2_lib.scala 244:78] + node _T_738 = mux(_T_734, UInt<1>("h01"), _T_737) @[el2_lib.scala 244:23] + _T_668[9] <= _T_738 @[el2_lib.scala 244:17] + node _T_739 = bits(io.trigger_pkt_any[2].tdata2, 9, 0) @[el2_lib.scala 244:28] + node _T_740 = andr(_T_739) @[el2_lib.scala 244:36] + node _T_741 = and(_T_740, _T_671) @[el2_lib.scala 244:41] + node _T_742 = bits(io.trigger_pkt_any[2].tdata2, 10, 10) @[el2_lib.scala 244:74] + node _T_743 = bits(dec_i0_match_data[2], 10, 10) @[el2_lib.scala 244:86] + node _T_744 = eq(_T_742, _T_743) @[el2_lib.scala 244:78] + node _T_745 = mux(_T_741, UInt<1>("h01"), _T_744) @[el2_lib.scala 244:23] + _T_668[10] <= _T_745 @[el2_lib.scala 244:17] + node _T_746 = bits(io.trigger_pkt_any[2].tdata2, 10, 0) @[el2_lib.scala 244:28] + node _T_747 = andr(_T_746) @[el2_lib.scala 244:36] + node _T_748 = and(_T_747, _T_671) @[el2_lib.scala 244:41] + node _T_749 = bits(io.trigger_pkt_any[2].tdata2, 11, 11) @[el2_lib.scala 244:74] + node _T_750 = bits(dec_i0_match_data[2], 11, 11) @[el2_lib.scala 244:86] + node _T_751 = eq(_T_749, _T_750) @[el2_lib.scala 244:78] + node _T_752 = mux(_T_748, UInt<1>("h01"), _T_751) @[el2_lib.scala 244:23] + _T_668[11] <= _T_752 @[el2_lib.scala 244:17] + node _T_753 = bits(io.trigger_pkt_any[2].tdata2, 11, 0) @[el2_lib.scala 244:28] + node _T_754 = andr(_T_753) @[el2_lib.scala 244:36] + node _T_755 = and(_T_754, _T_671) @[el2_lib.scala 244:41] + node _T_756 = bits(io.trigger_pkt_any[2].tdata2, 12, 12) @[el2_lib.scala 244:74] + node _T_757 = bits(dec_i0_match_data[2], 12, 12) @[el2_lib.scala 244:86] + node _T_758 = eq(_T_756, _T_757) @[el2_lib.scala 244:78] + node _T_759 = mux(_T_755, UInt<1>("h01"), _T_758) @[el2_lib.scala 244:23] + _T_668[12] <= _T_759 @[el2_lib.scala 244:17] + node _T_760 = bits(io.trigger_pkt_any[2].tdata2, 12, 0) @[el2_lib.scala 244:28] + node _T_761 = andr(_T_760) @[el2_lib.scala 244:36] + node _T_762 = and(_T_761, _T_671) @[el2_lib.scala 244:41] + node _T_763 = bits(io.trigger_pkt_any[2].tdata2, 13, 13) @[el2_lib.scala 244:74] + node _T_764 = bits(dec_i0_match_data[2], 13, 13) @[el2_lib.scala 244:86] + node _T_765 = eq(_T_763, _T_764) @[el2_lib.scala 244:78] + node _T_766 = mux(_T_762, UInt<1>("h01"), _T_765) @[el2_lib.scala 244:23] + _T_668[13] <= _T_766 @[el2_lib.scala 244:17] + node _T_767 = bits(io.trigger_pkt_any[2].tdata2, 13, 0) @[el2_lib.scala 244:28] + node _T_768 = andr(_T_767) @[el2_lib.scala 244:36] + node _T_769 = and(_T_768, _T_671) @[el2_lib.scala 244:41] + node _T_770 = bits(io.trigger_pkt_any[2].tdata2, 14, 14) @[el2_lib.scala 244:74] + node _T_771 = bits(dec_i0_match_data[2], 14, 14) @[el2_lib.scala 244:86] + node _T_772 = eq(_T_770, _T_771) @[el2_lib.scala 244:78] + node _T_773 = mux(_T_769, UInt<1>("h01"), _T_772) @[el2_lib.scala 244:23] + _T_668[14] <= _T_773 @[el2_lib.scala 244:17] + node _T_774 = bits(io.trigger_pkt_any[2].tdata2, 14, 0) @[el2_lib.scala 244:28] + node _T_775 = andr(_T_774) @[el2_lib.scala 244:36] + node _T_776 = and(_T_775, _T_671) @[el2_lib.scala 244:41] + node _T_777 = bits(io.trigger_pkt_any[2].tdata2, 15, 15) @[el2_lib.scala 244:74] + node _T_778 = bits(dec_i0_match_data[2], 15, 15) @[el2_lib.scala 244:86] + node _T_779 = eq(_T_777, _T_778) @[el2_lib.scala 244:78] + node _T_780 = mux(_T_776, UInt<1>("h01"), _T_779) @[el2_lib.scala 244:23] + _T_668[15] <= _T_780 @[el2_lib.scala 244:17] + node _T_781 = bits(io.trigger_pkt_any[2].tdata2, 15, 0) @[el2_lib.scala 244:28] + node _T_782 = andr(_T_781) @[el2_lib.scala 244:36] + node _T_783 = and(_T_782, _T_671) @[el2_lib.scala 244:41] + node _T_784 = bits(io.trigger_pkt_any[2].tdata2, 16, 16) @[el2_lib.scala 244:74] + node _T_785 = bits(dec_i0_match_data[2], 16, 16) @[el2_lib.scala 244:86] + node _T_786 = eq(_T_784, _T_785) @[el2_lib.scala 244:78] + node _T_787 = mux(_T_783, UInt<1>("h01"), _T_786) @[el2_lib.scala 244:23] + _T_668[16] <= _T_787 @[el2_lib.scala 244:17] + node _T_788 = bits(io.trigger_pkt_any[2].tdata2, 16, 0) @[el2_lib.scala 244:28] + node _T_789 = andr(_T_788) @[el2_lib.scala 244:36] + node _T_790 = and(_T_789, _T_671) @[el2_lib.scala 244:41] + node _T_791 = bits(io.trigger_pkt_any[2].tdata2, 17, 17) @[el2_lib.scala 244:74] + node _T_792 = bits(dec_i0_match_data[2], 17, 17) @[el2_lib.scala 244:86] + node _T_793 = eq(_T_791, _T_792) @[el2_lib.scala 244:78] + node _T_794 = mux(_T_790, UInt<1>("h01"), _T_793) @[el2_lib.scala 244:23] + _T_668[17] <= _T_794 @[el2_lib.scala 244:17] + node _T_795 = bits(io.trigger_pkt_any[2].tdata2, 17, 0) @[el2_lib.scala 244:28] + node _T_796 = andr(_T_795) @[el2_lib.scala 244:36] + node _T_797 = and(_T_796, _T_671) @[el2_lib.scala 244:41] + node _T_798 = bits(io.trigger_pkt_any[2].tdata2, 18, 18) @[el2_lib.scala 244:74] + node _T_799 = bits(dec_i0_match_data[2], 18, 18) @[el2_lib.scala 244:86] + node _T_800 = eq(_T_798, _T_799) @[el2_lib.scala 244:78] + node _T_801 = mux(_T_797, UInt<1>("h01"), _T_800) @[el2_lib.scala 244:23] + _T_668[18] <= _T_801 @[el2_lib.scala 244:17] + node _T_802 = bits(io.trigger_pkt_any[2].tdata2, 18, 0) @[el2_lib.scala 244:28] + node _T_803 = andr(_T_802) @[el2_lib.scala 244:36] + node _T_804 = and(_T_803, _T_671) @[el2_lib.scala 244:41] + node _T_805 = bits(io.trigger_pkt_any[2].tdata2, 19, 19) @[el2_lib.scala 244:74] + node _T_806 = bits(dec_i0_match_data[2], 19, 19) @[el2_lib.scala 244:86] + node _T_807 = eq(_T_805, _T_806) @[el2_lib.scala 244:78] + node _T_808 = mux(_T_804, UInt<1>("h01"), _T_807) @[el2_lib.scala 244:23] + _T_668[19] <= _T_808 @[el2_lib.scala 244:17] + node _T_809 = bits(io.trigger_pkt_any[2].tdata2, 19, 0) @[el2_lib.scala 244:28] + node _T_810 = andr(_T_809) @[el2_lib.scala 244:36] + node _T_811 = and(_T_810, _T_671) @[el2_lib.scala 244:41] + node _T_812 = bits(io.trigger_pkt_any[2].tdata2, 20, 20) @[el2_lib.scala 244:74] + node _T_813 = bits(dec_i0_match_data[2], 20, 20) @[el2_lib.scala 244:86] + node _T_814 = eq(_T_812, _T_813) @[el2_lib.scala 244:78] + node _T_815 = mux(_T_811, UInt<1>("h01"), _T_814) @[el2_lib.scala 244:23] + _T_668[20] <= _T_815 @[el2_lib.scala 244:17] + node _T_816 = bits(io.trigger_pkt_any[2].tdata2, 20, 0) @[el2_lib.scala 244:28] + node _T_817 = andr(_T_816) @[el2_lib.scala 244:36] + node _T_818 = and(_T_817, _T_671) @[el2_lib.scala 244:41] + node _T_819 = bits(io.trigger_pkt_any[2].tdata2, 21, 21) @[el2_lib.scala 244:74] + node _T_820 = bits(dec_i0_match_data[2], 21, 21) @[el2_lib.scala 244:86] + node _T_821 = eq(_T_819, _T_820) @[el2_lib.scala 244:78] + node _T_822 = mux(_T_818, UInt<1>("h01"), _T_821) @[el2_lib.scala 244:23] + _T_668[21] <= _T_822 @[el2_lib.scala 244:17] + node _T_823 = bits(io.trigger_pkt_any[2].tdata2, 21, 0) @[el2_lib.scala 244:28] + node _T_824 = andr(_T_823) @[el2_lib.scala 244:36] + node _T_825 = and(_T_824, _T_671) @[el2_lib.scala 244:41] + node _T_826 = bits(io.trigger_pkt_any[2].tdata2, 22, 22) @[el2_lib.scala 244:74] + node _T_827 = bits(dec_i0_match_data[2], 22, 22) @[el2_lib.scala 244:86] + node _T_828 = eq(_T_826, _T_827) @[el2_lib.scala 244:78] + node _T_829 = mux(_T_825, UInt<1>("h01"), _T_828) @[el2_lib.scala 244:23] + _T_668[22] <= _T_829 @[el2_lib.scala 244:17] + node _T_830 = bits(io.trigger_pkt_any[2].tdata2, 22, 0) @[el2_lib.scala 244:28] + node _T_831 = andr(_T_830) @[el2_lib.scala 244:36] + node _T_832 = and(_T_831, _T_671) @[el2_lib.scala 244:41] + node _T_833 = bits(io.trigger_pkt_any[2].tdata2, 23, 23) @[el2_lib.scala 244:74] + node _T_834 = bits(dec_i0_match_data[2], 23, 23) @[el2_lib.scala 244:86] + node _T_835 = eq(_T_833, _T_834) @[el2_lib.scala 244:78] + node _T_836 = mux(_T_832, UInt<1>("h01"), _T_835) @[el2_lib.scala 244:23] + _T_668[23] <= _T_836 @[el2_lib.scala 244:17] + node _T_837 = bits(io.trigger_pkt_any[2].tdata2, 23, 0) @[el2_lib.scala 244:28] + node _T_838 = andr(_T_837) @[el2_lib.scala 244:36] + node _T_839 = and(_T_838, _T_671) @[el2_lib.scala 244:41] + node _T_840 = bits(io.trigger_pkt_any[2].tdata2, 24, 24) @[el2_lib.scala 244:74] + node _T_841 = bits(dec_i0_match_data[2], 24, 24) @[el2_lib.scala 244:86] + node _T_842 = eq(_T_840, _T_841) @[el2_lib.scala 244:78] + node _T_843 = mux(_T_839, UInt<1>("h01"), _T_842) @[el2_lib.scala 244:23] + _T_668[24] <= _T_843 @[el2_lib.scala 244:17] + node _T_844 = bits(io.trigger_pkt_any[2].tdata2, 24, 0) @[el2_lib.scala 244:28] + node _T_845 = andr(_T_844) @[el2_lib.scala 244:36] + node _T_846 = and(_T_845, _T_671) @[el2_lib.scala 244:41] + node _T_847 = bits(io.trigger_pkt_any[2].tdata2, 25, 25) @[el2_lib.scala 244:74] + node _T_848 = bits(dec_i0_match_data[2], 25, 25) @[el2_lib.scala 244:86] + node _T_849 = eq(_T_847, _T_848) @[el2_lib.scala 244:78] + node _T_850 = mux(_T_846, UInt<1>("h01"), _T_849) @[el2_lib.scala 244:23] + _T_668[25] <= _T_850 @[el2_lib.scala 244:17] + node _T_851 = bits(io.trigger_pkt_any[2].tdata2, 25, 0) @[el2_lib.scala 244:28] + node _T_852 = andr(_T_851) @[el2_lib.scala 244:36] + node _T_853 = and(_T_852, _T_671) @[el2_lib.scala 244:41] + node _T_854 = bits(io.trigger_pkt_any[2].tdata2, 26, 26) @[el2_lib.scala 244:74] + node _T_855 = bits(dec_i0_match_data[2], 26, 26) @[el2_lib.scala 244:86] + node _T_856 = eq(_T_854, _T_855) @[el2_lib.scala 244:78] + node _T_857 = mux(_T_853, UInt<1>("h01"), _T_856) @[el2_lib.scala 244:23] + _T_668[26] <= _T_857 @[el2_lib.scala 244:17] + node _T_858 = bits(io.trigger_pkt_any[2].tdata2, 26, 0) @[el2_lib.scala 244:28] + node _T_859 = andr(_T_858) @[el2_lib.scala 244:36] + node _T_860 = and(_T_859, _T_671) @[el2_lib.scala 244:41] + node _T_861 = bits(io.trigger_pkt_any[2].tdata2, 27, 27) @[el2_lib.scala 244:74] + node _T_862 = bits(dec_i0_match_data[2], 27, 27) @[el2_lib.scala 244:86] + node _T_863 = eq(_T_861, _T_862) @[el2_lib.scala 244:78] + node _T_864 = mux(_T_860, UInt<1>("h01"), _T_863) @[el2_lib.scala 244:23] + _T_668[27] <= _T_864 @[el2_lib.scala 244:17] + node _T_865 = bits(io.trigger_pkt_any[2].tdata2, 27, 0) @[el2_lib.scala 244:28] + node _T_866 = andr(_T_865) @[el2_lib.scala 244:36] + node _T_867 = and(_T_866, _T_671) @[el2_lib.scala 244:41] + node _T_868 = bits(io.trigger_pkt_any[2].tdata2, 28, 28) @[el2_lib.scala 244:74] + node _T_869 = bits(dec_i0_match_data[2], 28, 28) @[el2_lib.scala 244:86] + node _T_870 = eq(_T_868, _T_869) @[el2_lib.scala 244:78] + node _T_871 = mux(_T_867, UInt<1>("h01"), _T_870) @[el2_lib.scala 244:23] + _T_668[28] <= _T_871 @[el2_lib.scala 244:17] + node _T_872 = bits(io.trigger_pkt_any[2].tdata2, 28, 0) @[el2_lib.scala 244:28] + node _T_873 = andr(_T_872) @[el2_lib.scala 244:36] + node _T_874 = and(_T_873, _T_671) @[el2_lib.scala 244:41] + node _T_875 = bits(io.trigger_pkt_any[2].tdata2, 29, 29) @[el2_lib.scala 244:74] + node _T_876 = bits(dec_i0_match_data[2], 29, 29) @[el2_lib.scala 244:86] + node _T_877 = eq(_T_875, _T_876) @[el2_lib.scala 244:78] + node _T_878 = mux(_T_874, UInt<1>("h01"), _T_877) @[el2_lib.scala 244:23] + _T_668[29] <= _T_878 @[el2_lib.scala 244:17] + node _T_879 = bits(io.trigger_pkt_any[2].tdata2, 29, 0) @[el2_lib.scala 244:28] + node _T_880 = andr(_T_879) @[el2_lib.scala 244:36] + node _T_881 = and(_T_880, _T_671) @[el2_lib.scala 244:41] + node _T_882 = bits(io.trigger_pkt_any[2].tdata2, 30, 30) @[el2_lib.scala 244:74] + node _T_883 = bits(dec_i0_match_data[2], 30, 30) @[el2_lib.scala 244:86] + node _T_884 = eq(_T_882, _T_883) @[el2_lib.scala 244:78] + node _T_885 = mux(_T_881, UInt<1>("h01"), _T_884) @[el2_lib.scala 244:23] + _T_668[30] <= _T_885 @[el2_lib.scala 244:17] + node _T_886 = bits(io.trigger_pkt_any[2].tdata2, 30, 0) @[el2_lib.scala 244:28] + node _T_887 = andr(_T_886) @[el2_lib.scala 244:36] + node _T_888 = and(_T_887, _T_671) @[el2_lib.scala 244:41] + node _T_889 = bits(io.trigger_pkt_any[2].tdata2, 31, 31) @[el2_lib.scala 244:74] + node _T_890 = bits(dec_i0_match_data[2], 31, 31) @[el2_lib.scala 244:86] + node _T_891 = eq(_T_889, _T_890) @[el2_lib.scala 244:78] + node _T_892 = mux(_T_888, UInt<1>("h01"), _T_891) @[el2_lib.scala 244:23] + _T_668[31] <= _T_892 @[el2_lib.scala 244:17] + node _T_893 = cat(_T_668[1], _T_668[0]) @[el2_lib.scala 245:14] + node _T_894 = cat(_T_668[3], _T_668[2]) @[el2_lib.scala 245:14] + node _T_895 = cat(_T_894, _T_893) @[el2_lib.scala 245:14] + node _T_896 = cat(_T_668[5], _T_668[4]) @[el2_lib.scala 245:14] + node _T_897 = cat(_T_668[7], _T_668[6]) @[el2_lib.scala 245:14] + node _T_898 = cat(_T_897, _T_896) @[el2_lib.scala 245:14] + node _T_899 = cat(_T_898, _T_895) @[el2_lib.scala 245:14] + node _T_900 = cat(_T_668[9], _T_668[8]) @[el2_lib.scala 245:14] + node _T_901 = cat(_T_668[11], _T_668[10]) @[el2_lib.scala 245:14] + node _T_902 = cat(_T_901, _T_900) @[el2_lib.scala 245:14] + node _T_903 = cat(_T_668[13], _T_668[12]) @[el2_lib.scala 245:14] + node _T_904 = cat(_T_668[15], _T_668[14]) @[el2_lib.scala 245:14] + node _T_905 = cat(_T_904, _T_903) @[el2_lib.scala 245:14] + node _T_906 = cat(_T_905, _T_902) @[el2_lib.scala 245:14] + node _T_907 = cat(_T_906, _T_899) @[el2_lib.scala 245:14] + node _T_908 = cat(_T_668[17], _T_668[16]) @[el2_lib.scala 245:14] + node _T_909 = cat(_T_668[19], _T_668[18]) @[el2_lib.scala 245:14] + node _T_910 = cat(_T_909, _T_908) @[el2_lib.scala 245:14] + node _T_911 = cat(_T_668[21], _T_668[20]) @[el2_lib.scala 245:14] + node _T_912 = cat(_T_668[23], _T_668[22]) @[el2_lib.scala 245:14] + node _T_913 = cat(_T_912, _T_911) @[el2_lib.scala 245:14] + node _T_914 = cat(_T_913, _T_910) @[el2_lib.scala 245:14] + node _T_915 = cat(_T_668[25], _T_668[24]) @[el2_lib.scala 245:14] + node _T_916 = cat(_T_668[27], _T_668[26]) @[el2_lib.scala 245:14] + node _T_917 = cat(_T_916, _T_915) @[el2_lib.scala 245:14] + node _T_918 = cat(_T_668[29], _T_668[28]) @[el2_lib.scala 245:14] + node _T_919 = cat(_T_668[31], _T_668[30]) @[el2_lib.scala 245:14] + node _T_920 = cat(_T_919, _T_918) @[el2_lib.scala 245:14] + node _T_921 = cat(_T_920, _T_917) @[el2_lib.scala 245:14] + node _T_922 = cat(_T_921, _T_914) @[el2_lib.scala 245:14] + node _T_923 = cat(_T_922, _T_907) @[el2_lib.scala 245:14] + node _T_924 = and(_T_666, _T_923) @[el2_dec_trigger.scala 15:109] + node _T_925 = and(io.trigger_pkt_any[3].execute, io.trigger_pkt_any[3].m) @[el2_dec_trigger.scala 15:83] + node _T_926 = bits(io.trigger_pkt_any[3].match_pkt, 0, 0) @[el2_dec_trigger.scala 15:216] + wire _T_927 : UInt<1>[32] @[el2_lib.scala 240:24] + node _T_928 = andr(io.trigger_pkt_any[3].tdata2) @[el2_lib.scala 241:45] + node _T_929 = not(_T_928) @[el2_lib.scala 241:39] + node _T_930 = and(_T_926, _T_929) @[el2_lib.scala 241:37] + node _T_931 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[el2_lib.scala 242:48] + node _T_932 = bits(dec_i0_match_data[3], 0, 0) @[el2_lib.scala 242:60] + node _T_933 = eq(_T_931, _T_932) @[el2_lib.scala 242:52] + node _T_934 = or(_T_930, _T_933) @[el2_lib.scala 242:41] + _T_927[0] <= _T_934 @[el2_lib.scala 242:18] + node _T_935 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[el2_lib.scala 244:28] + node _T_936 = andr(_T_935) @[el2_lib.scala 244:36] + node _T_937 = and(_T_936, _T_930) @[el2_lib.scala 244:41] + node _T_938 = bits(io.trigger_pkt_any[3].tdata2, 1, 1) @[el2_lib.scala 244:74] + node _T_939 = bits(dec_i0_match_data[3], 1, 1) @[el2_lib.scala 244:86] + node _T_940 = eq(_T_938, _T_939) @[el2_lib.scala 244:78] + node _T_941 = mux(_T_937, UInt<1>("h01"), _T_940) @[el2_lib.scala 244:23] + _T_927[1] <= _T_941 @[el2_lib.scala 244:17] + node _T_942 = bits(io.trigger_pkt_any[3].tdata2, 1, 0) @[el2_lib.scala 244:28] + node _T_943 = andr(_T_942) @[el2_lib.scala 244:36] + node _T_944 = and(_T_943, _T_930) @[el2_lib.scala 244:41] + node _T_945 = bits(io.trigger_pkt_any[3].tdata2, 2, 2) @[el2_lib.scala 244:74] + node _T_946 = bits(dec_i0_match_data[3], 2, 2) @[el2_lib.scala 244:86] + node _T_947 = eq(_T_945, _T_946) @[el2_lib.scala 244:78] + node _T_948 = mux(_T_944, UInt<1>("h01"), _T_947) @[el2_lib.scala 244:23] + _T_927[2] <= _T_948 @[el2_lib.scala 244:17] + node _T_949 = bits(io.trigger_pkt_any[3].tdata2, 2, 0) @[el2_lib.scala 244:28] + node _T_950 = andr(_T_949) @[el2_lib.scala 244:36] + node _T_951 = and(_T_950, _T_930) @[el2_lib.scala 244:41] + node _T_952 = bits(io.trigger_pkt_any[3].tdata2, 3, 3) @[el2_lib.scala 244:74] + node _T_953 = bits(dec_i0_match_data[3], 3, 3) @[el2_lib.scala 244:86] + node _T_954 = eq(_T_952, _T_953) @[el2_lib.scala 244:78] + node _T_955 = mux(_T_951, UInt<1>("h01"), _T_954) @[el2_lib.scala 244:23] + _T_927[3] <= _T_955 @[el2_lib.scala 244:17] + node _T_956 = bits(io.trigger_pkt_any[3].tdata2, 3, 0) @[el2_lib.scala 244:28] + node _T_957 = andr(_T_956) @[el2_lib.scala 244:36] + node _T_958 = and(_T_957, _T_930) @[el2_lib.scala 244:41] + node _T_959 = bits(io.trigger_pkt_any[3].tdata2, 4, 4) @[el2_lib.scala 244:74] + node _T_960 = bits(dec_i0_match_data[3], 4, 4) @[el2_lib.scala 244:86] + node _T_961 = eq(_T_959, _T_960) @[el2_lib.scala 244:78] + node _T_962 = mux(_T_958, UInt<1>("h01"), _T_961) @[el2_lib.scala 244:23] + _T_927[4] <= _T_962 @[el2_lib.scala 244:17] + node _T_963 = bits(io.trigger_pkt_any[3].tdata2, 4, 0) @[el2_lib.scala 244:28] + node _T_964 = andr(_T_963) @[el2_lib.scala 244:36] + node _T_965 = and(_T_964, _T_930) @[el2_lib.scala 244:41] + node _T_966 = bits(io.trigger_pkt_any[3].tdata2, 5, 5) @[el2_lib.scala 244:74] + node _T_967 = bits(dec_i0_match_data[3], 5, 5) @[el2_lib.scala 244:86] + node _T_968 = eq(_T_966, _T_967) @[el2_lib.scala 244:78] + node _T_969 = mux(_T_965, UInt<1>("h01"), _T_968) @[el2_lib.scala 244:23] + _T_927[5] <= _T_969 @[el2_lib.scala 244:17] + node _T_970 = bits(io.trigger_pkt_any[3].tdata2, 5, 0) @[el2_lib.scala 244:28] + node _T_971 = andr(_T_970) @[el2_lib.scala 244:36] + node _T_972 = and(_T_971, _T_930) @[el2_lib.scala 244:41] + node _T_973 = bits(io.trigger_pkt_any[3].tdata2, 6, 6) @[el2_lib.scala 244:74] + node _T_974 = bits(dec_i0_match_data[3], 6, 6) @[el2_lib.scala 244:86] + node _T_975 = eq(_T_973, _T_974) @[el2_lib.scala 244:78] + node _T_976 = mux(_T_972, UInt<1>("h01"), _T_975) @[el2_lib.scala 244:23] + _T_927[6] <= _T_976 @[el2_lib.scala 244:17] + node _T_977 = bits(io.trigger_pkt_any[3].tdata2, 6, 0) @[el2_lib.scala 244:28] + node _T_978 = andr(_T_977) @[el2_lib.scala 244:36] + node _T_979 = and(_T_978, _T_930) @[el2_lib.scala 244:41] + node _T_980 = bits(io.trigger_pkt_any[3].tdata2, 7, 7) @[el2_lib.scala 244:74] + node _T_981 = bits(dec_i0_match_data[3], 7, 7) @[el2_lib.scala 244:86] + node _T_982 = eq(_T_980, _T_981) @[el2_lib.scala 244:78] + node _T_983 = mux(_T_979, UInt<1>("h01"), _T_982) @[el2_lib.scala 244:23] + _T_927[7] <= _T_983 @[el2_lib.scala 244:17] + node _T_984 = bits(io.trigger_pkt_any[3].tdata2, 7, 0) @[el2_lib.scala 244:28] + node _T_985 = andr(_T_984) @[el2_lib.scala 244:36] + node _T_986 = and(_T_985, _T_930) @[el2_lib.scala 244:41] + node _T_987 = bits(io.trigger_pkt_any[3].tdata2, 8, 8) @[el2_lib.scala 244:74] + node _T_988 = bits(dec_i0_match_data[3], 8, 8) @[el2_lib.scala 244:86] + node _T_989 = eq(_T_987, _T_988) @[el2_lib.scala 244:78] + node _T_990 = mux(_T_986, UInt<1>("h01"), _T_989) @[el2_lib.scala 244:23] + _T_927[8] <= _T_990 @[el2_lib.scala 244:17] + node _T_991 = bits(io.trigger_pkt_any[3].tdata2, 8, 0) @[el2_lib.scala 244:28] + node _T_992 = andr(_T_991) @[el2_lib.scala 244:36] + node _T_993 = and(_T_992, _T_930) @[el2_lib.scala 244:41] + node _T_994 = bits(io.trigger_pkt_any[3].tdata2, 9, 9) @[el2_lib.scala 244:74] + node _T_995 = bits(dec_i0_match_data[3], 9, 9) @[el2_lib.scala 244:86] + node _T_996 = eq(_T_994, _T_995) @[el2_lib.scala 244:78] + node _T_997 = mux(_T_993, UInt<1>("h01"), _T_996) @[el2_lib.scala 244:23] + _T_927[9] <= _T_997 @[el2_lib.scala 244:17] + node _T_998 = bits(io.trigger_pkt_any[3].tdata2, 9, 0) @[el2_lib.scala 244:28] + node _T_999 = andr(_T_998) @[el2_lib.scala 244:36] + node _T_1000 = and(_T_999, _T_930) @[el2_lib.scala 244:41] + node _T_1001 = bits(io.trigger_pkt_any[3].tdata2, 10, 10) @[el2_lib.scala 244:74] + node _T_1002 = bits(dec_i0_match_data[3], 10, 10) @[el2_lib.scala 244:86] + node _T_1003 = eq(_T_1001, _T_1002) @[el2_lib.scala 244:78] + node _T_1004 = mux(_T_1000, UInt<1>("h01"), _T_1003) @[el2_lib.scala 244:23] + _T_927[10] <= _T_1004 @[el2_lib.scala 244:17] + node _T_1005 = bits(io.trigger_pkt_any[3].tdata2, 10, 0) @[el2_lib.scala 244:28] + node _T_1006 = andr(_T_1005) @[el2_lib.scala 244:36] + node _T_1007 = and(_T_1006, _T_930) @[el2_lib.scala 244:41] + node _T_1008 = bits(io.trigger_pkt_any[3].tdata2, 11, 11) @[el2_lib.scala 244:74] + node _T_1009 = bits(dec_i0_match_data[3], 11, 11) @[el2_lib.scala 244:86] + node _T_1010 = eq(_T_1008, _T_1009) @[el2_lib.scala 244:78] + node _T_1011 = mux(_T_1007, UInt<1>("h01"), _T_1010) @[el2_lib.scala 244:23] + _T_927[11] <= _T_1011 @[el2_lib.scala 244:17] + node _T_1012 = bits(io.trigger_pkt_any[3].tdata2, 11, 0) @[el2_lib.scala 244:28] + node _T_1013 = andr(_T_1012) @[el2_lib.scala 244:36] + node _T_1014 = and(_T_1013, _T_930) @[el2_lib.scala 244:41] + node _T_1015 = bits(io.trigger_pkt_any[3].tdata2, 12, 12) @[el2_lib.scala 244:74] + node _T_1016 = bits(dec_i0_match_data[3], 12, 12) @[el2_lib.scala 244:86] + node _T_1017 = eq(_T_1015, _T_1016) @[el2_lib.scala 244:78] + node _T_1018 = mux(_T_1014, UInt<1>("h01"), _T_1017) @[el2_lib.scala 244:23] + _T_927[12] <= _T_1018 @[el2_lib.scala 244:17] + node _T_1019 = bits(io.trigger_pkt_any[3].tdata2, 12, 0) @[el2_lib.scala 244:28] + node _T_1020 = andr(_T_1019) @[el2_lib.scala 244:36] + node _T_1021 = and(_T_1020, _T_930) @[el2_lib.scala 244:41] + node _T_1022 = bits(io.trigger_pkt_any[3].tdata2, 13, 13) @[el2_lib.scala 244:74] + node _T_1023 = bits(dec_i0_match_data[3], 13, 13) @[el2_lib.scala 244:86] + node _T_1024 = eq(_T_1022, _T_1023) @[el2_lib.scala 244:78] + node _T_1025 = mux(_T_1021, UInt<1>("h01"), _T_1024) @[el2_lib.scala 244:23] + _T_927[13] <= _T_1025 @[el2_lib.scala 244:17] + node _T_1026 = bits(io.trigger_pkt_any[3].tdata2, 13, 0) @[el2_lib.scala 244:28] + node _T_1027 = andr(_T_1026) @[el2_lib.scala 244:36] + node _T_1028 = and(_T_1027, _T_930) @[el2_lib.scala 244:41] + node _T_1029 = bits(io.trigger_pkt_any[3].tdata2, 14, 14) @[el2_lib.scala 244:74] + node _T_1030 = bits(dec_i0_match_data[3], 14, 14) @[el2_lib.scala 244:86] + node _T_1031 = eq(_T_1029, _T_1030) @[el2_lib.scala 244:78] + node _T_1032 = mux(_T_1028, UInt<1>("h01"), _T_1031) @[el2_lib.scala 244:23] + _T_927[14] <= _T_1032 @[el2_lib.scala 244:17] + node _T_1033 = bits(io.trigger_pkt_any[3].tdata2, 14, 0) @[el2_lib.scala 244:28] + node _T_1034 = andr(_T_1033) @[el2_lib.scala 244:36] + node _T_1035 = and(_T_1034, _T_930) @[el2_lib.scala 244:41] + node _T_1036 = bits(io.trigger_pkt_any[3].tdata2, 15, 15) @[el2_lib.scala 244:74] + node _T_1037 = bits(dec_i0_match_data[3], 15, 15) @[el2_lib.scala 244:86] + node _T_1038 = eq(_T_1036, _T_1037) @[el2_lib.scala 244:78] + node _T_1039 = mux(_T_1035, UInt<1>("h01"), _T_1038) @[el2_lib.scala 244:23] + _T_927[15] <= _T_1039 @[el2_lib.scala 244:17] + node _T_1040 = bits(io.trigger_pkt_any[3].tdata2, 15, 0) @[el2_lib.scala 244:28] + node _T_1041 = andr(_T_1040) @[el2_lib.scala 244:36] + node _T_1042 = and(_T_1041, _T_930) @[el2_lib.scala 244:41] + node _T_1043 = bits(io.trigger_pkt_any[3].tdata2, 16, 16) @[el2_lib.scala 244:74] + node _T_1044 = bits(dec_i0_match_data[3], 16, 16) @[el2_lib.scala 244:86] + node _T_1045 = eq(_T_1043, _T_1044) @[el2_lib.scala 244:78] + node _T_1046 = mux(_T_1042, UInt<1>("h01"), _T_1045) @[el2_lib.scala 244:23] + _T_927[16] <= _T_1046 @[el2_lib.scala 244:17] + node _T_1047 = bits(io.trigger_pkt_any[3].tdata2, 16, 0) @[el2_lib.scala 244:28] + node _T_1048 = andr(_T_1047) @[el2_lib.scala 244:36] + node _T_1049 = and(_T_1048, _T_930) @[el2_lib.scala 244:41] + node _T_1050 = bits(io.trigger_pkt_any[3].tdata2, 17, 17) @[el2_lib.scala 244:74] + node _T_1051 = bits(dec_i0_match_data[3], 17, 17) @[el2_lib.scala 244:86] + node _T_1052 = eq(_T_1050, _T_1051) @[el2_lib.scala 244:78] + node _T_1053 = mux(_T_1049, UInt<1>("h01"), _T_1052) @[el2_lib.scala 244:23] + _T_927[17] <= _T_1053 @[el2_lib.scala 244:17] + node _T_1054 = bits(io.trigger_pkt_any[3].tdata2, 17, 0) @[el2_lib.scala 244:28] + node _T_1055 = andr(_T_1054) @[el2_lib.scala 244:36] + node _T_1056 = and(_T_1055, _T_930) @[el2_lib.scala 244:41] + node _T_1057 = bits(io.trigger_pkt_any[3].tdata2, 18, 18) @[el2_lib.scala 244:74] + node _T_1058 = bits(dec_i0_match_data[3], 18, 18) @[el2_lib.scala 244:86] + node _T_1059 = eq(_T_1057, _T_1058) @[el2_lib.scala 244:78] + node _T_1060 = mux(_T_1056, UInt<1>("h01"), _T_1059) @[el2_lib.scala 244:23] + _T_927[18] <= _T_1060 @[el2_lib.scala 244:17] + node _T_1061 = bits(io.trigger_pkt_any[3].tdata2, 18, 0) @[el2_lib.scala 244:28] + node _T_1062 = andr(_T_1061) @[el2_lib.scala 244:36] + node _T_1063 = and(_T_1062, _T_930) @[el2_lib.scala 244:41] + node _T_1064 = bits(io.trigger_pkt_any[3].tdata2, 19, 19) @[el2_lib.scala 244:74] + node _T_1065 = bits(dec_i0_match_data[3], 19, 19) @[el2_lib.scala 244:86] + node _T_1066 = eq(_T_1064, _T_1065) @[el2_lib.scala 244:78] + node _T_1067 = mux(_T_1063, UInt<1>("h01"), _T_1066) @[el2_lib.scala 244:23] + _T_927[19] <= _T_1067 @[el2_lib.scala 244:17] + node _T_1068 = bits(io.trigger_pkt_any[3].tdata2, 19, 0) @[el2_lib.scala 244:28] + node _T_1069 = andr(_T_1068) @[el2_lib.scala 244:36] + node _T_1070 = and(_T_1069, _T_930) @[el2_lib.scala 244:41] + node _T_1071 = bits(io.trigger_pkt_any[3].tdata2, 20, 20) @[el2_lib.scala 244:74] + node _T_1072 = bits(dec_i0_match_data[3], 20, 20) @[el2_lib.scala 244:86] + node _T_1073 = eq(_T_1071, _T_1072) @[el2_lib.scala 244:78] + node _T_1074 = mux(_T_1070, UInt<1>("h01"), _T_1073) @[el2_lib.scala 244:23] + _T_927[20] <= _T_1074 @[el2_lib.scala 244:17] + node _T_1075 = bits(io.trigger_pkt_any[3].tdata2, 20, 0) @[el2_lib.scala 244:28] + node _T_1076 = andr(_T_1075) @[el2_lib.scala 244:36] + node _T_1077 = and(_T_1076, _T_930) @[el2_lib.scala 244:41] + node _T_1078 = bits(io.trigger_pkt_any[3].tdata2, 21, 21) @[el2_lib.scala 244:74] + node _T_1079 = bits(dec_i0_match_data[3], 21, 21) @[el2_lib.scala 244:86] + node _T_1080 = eq(_T_1078, _T_1079) @[el2_lib.scala 244:78] + node _T_1081 = mux(_T_1077, UInt<1>("h01"), _T_1080) @[el2_lib.scala 244:23] + _T_927[21] <= _T_1081 @[el2_lib.scala 244:17] + node _T_1082 = bits(io.trigger_pkt_any[3].tdata2, 21, 0) @[el2_lib.scala 244:28] + node _T_1083 = andr(_T_1082) @[el2_lib.scala 244:36] + node _T_1084 = and(_T_1083, _T_930) @[el2_lib.scala 244:41] + node _T_1085 = bits(io.trigger_pkt_any[3].tdata2, 22, 22) @[el2_lib.scala 244:74] + node _T_1086 = bits(dec_i0_match_data[3], 22, 22) @[el2_lib.scala 244:86] + node _T_1087 = eq(_T_1085, _T_1086) @[el2_lib.scala 244:78] + node _T_1088 = mux(_T_1084, UInt<1>("h01"), _T_1087) @[el2_lib.scala 244:23] + _T_927[22] <= _T_1088 @[el2_lib.scala 244:17] + node _T_1089 = bits(io.trigger_pkt_any[3].tdata2, 22, 0) @[el2_lib.scala 244:28] + node _T_1090 = andr(_T_1089) @[el2_lib.scala 244:36] + node _T_1091 = and(_T_1090, _T_930) @[el2_lib.scala 244:41] + node _T_1092 = bits(io.trigger_pkt_any[3].tdata2, 23, 23) @[el2_lib.scala 244:74] + node _T_1093 = bits(dec_i0_match_data[3], 23, 23) @[el2_lib.scala 244:86] + node _T_1094 = eq(_T_1092, _T_1093) @[el2_lib.scala 244:78] + node _T_1095 = mux(_T_1091, UInt<1>("h01"), _T_1094) @[el2_lib.scala 244:23] + _T_927[23] <= _T_1095 @[el2_lib.scala 244:17] + node _T_1096 = bits(io.trigger_pkt_any[3].tdata2, 23, 0) @[el2_lib.scala 244:28] + node _T_1097 = andr(_T_1096) @[el2_lib.scala 244:36] + node _T_1098 = and(_T_1097, _T_930) @[el2_lib.scala 244:41] + node _T_1099 = bits(io.trigger_pkt_any[3].tdata2, 24, 24) @[el2_lib.scala 244:74] + node _T_1100 = bits(dec_i0_match_data[3], 24, 24) @[el2_lib.scala 244:86] + node _T_1101 = eq(_T_1099, _T_1100) @[el2_lib.scala 244:78] + node _T_1102 = mux(_T_1098, UInt<1>("h01"), _T_1101) @[el2_lib.scala 244:23] + _T_927[24] <= _T_1102 @[el2_lib.scala 244:17] + node _T_1103 = bits(io.trigger_pkt_any[3].tdata2, 24, 0) @[el2_lib.scala 244:28] + node _T_1104 = andr(_T_1103) @[el2_lib.scala 244:36] + node _T_1105 = and(_T_1104, _T_930) @[el2_lib.scala 244:41] + node _T_1106 = bits(io.trigger_pkt_any[3].tdata2, 25, 25) @[el2_lib.scala 244:74] + node _T_1107 = bits(dec_i0_match_data[3], 25, 25) @[el2_lib.scala 244:86] + node _T_1108 = eq(_T_1106, _T_1107) @[el2_lib.scala 244:78] + node _T_1109 = mux(_T_1105, UInt<1>("h01"), _T_1108) @[el2_lib.scala 244:23] + _T_927[25] <= _T_1109 @[el2_lib.scala 244:17] + node _T_1110 = bits(io.trigger_pkt_any[3].tdata2, 25, 0) @[el2_lib.scala 244:28] + node _T_1111 = andr(_T_1110) @[el2_lib.scala 244:36] + node _T_1112 = and(_T_1111, _T_930) @[el2_lib.scala 244:41] + node _T_1113 = bits(io.trigger_pkt_any[3].tdata2, 26, 26) @[el2_lib.scala 244:74] + node _T_1114 = bits(dec_i0_match_data[3], 26, 26) @[el2_lib.scala 244:86] + node _T_1115 = eq(_T_1113, _T_1114) @[el2_lib.scala 244:78] + node _T_1116 = mux(_T_1112, UInt<1>("h01"), _T_1115) @[el2_lib.scala 244:23] + _T_927[26] <= _T_1116 @[el2_lib.scala 244:17] + node _T_1117 = bits(io.trigger_pkt_any[3].tdata2, 26, 0) @[el2_lib.scala 244:28] + node _T_1118 = andr(_T_1117) @[el2_lib.scala 244:36] + node _T_1119 = and(_T_1118, _T_930) @[el2_lib.scala 244:41] + node _T_1120 = bits(io.trigger_pkt_any[3].tdata2, 27, 27) @[el2_lib.scala 244:74] + node _T_1121 = bits(dec_i0_match_data[3], 27, 27) @[el2_lib.scala 244:86] + node _T_1122 = eq(_T_1120, _T_1121) @[el2_lib.scala 244:78] + node _T_1123 = mux(_T_1119, UInt<1>("h01"), _T_1122) @[el2_lib.scala 244:23] + _T_927[27] <= _T_1123 @[el2_lib.scala 244:17] + node _T_1124 = bits(io.trigger_pkt_any[3].tdata2, 27, 0) @[el2_lib.scala 244:28] + node _T_1125 = andr(_T_1124) @[el2_lib.scala 244:36] + node _T_1126 = and(_T_1125, _T_930) @[el2_lib.scala 244:41] + node _T_1127 = bits(io.trigger_pkt_any[3].tdata2, 28, 28) @[el2_lib.scala 244:74] + node _T_1128 = bits(dec_i0_match_data[3], 28, 28) @[el2_lib.scala 244:86] + node _T_1129 = eq(_T_1127, _T_1128) @[el2_lib.scala 244:78] + node _T_1130 = mux(_T_1126, UInt<1>("h01"), _T_1129) @[el2_lib.scala 244:23] + _T_927[28] <= _T_1130 @[el2_lib.scala 244:17] + node _T_1131 = bits(io.trigger_pkt_any[3].tdata2, 28, 0) @[el2_lib.scala 244:28] + node _T_1132 = andr(_T_1131) @[el2_lib.scala 244:36] + node _T_1133 = and(_T_1132, _T_930) @[el2_lib.scala 244:41] + node _T_1134 = bits(io.trigger_pkt_any[3].tdata2, 29, 29) @[el2_lib.scala 244:74] + node _T_1135 = bits(dec_i0_match_data[3], 29, 29) @[el2_lib.scala 244:86] + node _T_1136 = eq(_T_1134, _T_1135) @[el2_lib.scala 244:78] + node _T_1137 = mux(_T_1133, UInt<1>("h01"), _T_1136) @[el2_lib.scala 244:23] + _T_927[29] <= _T_1137 @[el2_lib.scala 244:17] + node _T_1138 = bits(io.trigger_pkt_any[3].tdata2, 29, 0) @[el2_lib.scala 244:28] + node _T_1139 = andr(_T_1138) @[el2_lib.scala 244:36] + node _T_1140 = and(_T_1139, _T_930) @[el2_lib.scala 244:41] + node _T_1141 = bits(io.trigger_pkt_any[3].tdata2, 30, 30) @[el2_lib.scala 244:74] + node _T_1142 = bits(dec_i0_match_data[3], 30, 30) @[el2_lib.scala 244:86] + node _T_1143 = eq(_T_1141, _T_1142) @[el2_lib.scala 244:78] + node _T_1144 = mux(_T_1140, UInt<1>("h01"), _T_1143) @[el2_lib.scala 244:23] + _T_927[30] <= _T_1144 @[el2_lib.scala 244:17] + node _T_1145 = bits(io.trigger_pkt_any[3].tdata2, 30, 0) @[el2_lib.scala 244:28] + node _T_1146 = andr(_T_1145) @[el2_lib.scala 244:36] + node _T_1147 = and(_T_1146, _T_930) @[el2_lib.scala 244:41] + node _T_1148 = bits(io.trigger_pkt_any[3].tdata2, 31, 31) @[el2_lib.scala 244:74] + node _T_1149 = bits(dec_i0_match_data[3], 31, 31) @[el2_lib.scala 244:86] + node _T_1150 = eq(_T_1148, _T_1149) @[el2_lib.scala 244:78] + node _T_1151 = mux(_T_1147, UInt<1>("h01"), _T_1150) @[el2_lib.scala 244:23] + _T_927[31] <= _T_1151 @[el2_lib.scala 244:17] + node _T_1152 = cat(_T_927[1], _T_927[0]) @[el2_lib.scala 245:14] + node _T_1153 = cat(_T_927[3], _T_927[2]) @[el2_lib.scala 245:14] + node _T_1154 = cat(_T_1153, _T_1152) @[el2_lib.scala 245:14] + node _T_1155 = cat(_T_927[5], _T_927[4]) @[el2_lib.scala 245:14] + node _T_1156 = cat(_T_927[7], _T_927[6]) @[el2_lib.scala 245:14] + node _T_1157 = cat(_T_1156, _T_1155) @[el2_lib.scala 245:14] + node _T_1158 = cat(_T_1157, _T_1154) @[el2_lib.scala 245:14] + node _T_1159 = cat(_T_927[9], _T_927[8]) @[el2_lib.scala 245:14] + node _T_1160 = cat(_T_927[11], _T_927[10]) @[el2_lib.scala 245:14] + node _T_1161 = cat(_T_1160, _T_1159) @[el2_lib.scala 245:14] + node _T_1162 = cat(_T_927[13], _T_927[12]) @[el2_lib.scala 245:14] + node _T_1163 = cat(_T_927[15], _T_927[14]) @[el2_lib.scala 245:14] + node _T_1164 = cat(_T_1163, _T_1162) @[el2_lib.scala 245:14] + node _T_1165 = cat(_T_1164, _T_1161) @[el2_lib.scala 245:14] + node _T_1166 = cat(_T_1165, _T_1158) @[el2_lib.scala 245:14] + node _T_1167 = cat(_T_927[17], _T_927[16]) @[el2_lib.scala 245:14] + node _T_1168 = cat(_T_927[19], _T_927[18]) @[el2_lib.scala 245:14] + node _T_1169 = cat(_T_1168, _T_1167) @[el2_lib.scala 245:14] + node _T_1170 = cat(_T_927[21], _T_927[20]) @[el2_lib.scala 245:14] + node _T_1171 = cat(_T_927[23], _T_927[22]) @[el2_lib.scala 245:14] + node _T_1172 = cat(_T_1171, _T_1170) @[el2_lib.scala 245:14] + node _T_1173 = cat(_T_1172, _T_1169) @[el2_lib.scala 245:14] + node _T_1174 = cat(_T_927[25], _T_927[24]) @[el2_lib.scala 245:14] + node _T_1175 = cat(_T_927[27], _T_927[26]) @[el2_lib.scala 245:14] + node _T_1176 = cat(_T_1175, _T_1174) @[el2_lib.scala 245:14] + node _T_1177 = cat(_T_927[29], _T_927[28]) @[el2_lib.scala 245:14] + node _T_1178 = cat(_T_927[31], _T_927[30]) @[el2_lib.scala 245:14] + node _T_1179 = cat(_T_1178, _T_1177) @[el2_lib.scala 245:14] + node _T_1180 = cat(_T_1179, _T_1176) @[el2_lib.scala 245:14] + node _T_1181 = cat(_T_1180, _T_1173) @[el2_lib.scala 245:14] + node _T_1182 = cat(_T_1181, _T_1166) @[el2_lib.scala 245:14] + node _T_1183 = and(_T_925, _T_1182) @[el2_dec_trigger.scala 15:109] node _T_1184 = cat(_T_1183, _T_924) @[Cat.scala 29:58] node _T_1185 = cat(_T_1184, _T_665) @[Cat.scala 29:58] node _T_1186 = cat(_T_1185, _T_406) @[Cat.scala 29:58] - io.dec_i0_trigger_match_d <= _T_1186 @[el2_lsu_trigger.scala 16:29] + io.dec_i0_trigger_match_d <= _T_1186 @[el2_dec_trigger.scala 15:29] diff --git a/el2_dec_trigger.v b/el2_dec_trigger.v index b97ba28e..6735dc32 100644 --- a/el2_dec_trigger.v +++ b/el2_dec_trigger.v @@ -2,28 +2,28 @@ module el2_dec_trigger( input clock, input reset, input io_trigger_pkt_any_0_select, - input io_trigger_pkt_any_0_match_, + input io_trigger_pkt_any_0_match_pkt, input io_trigger_pkt_any_0_store, input io_trigger_pkt_any_0_load, input io_trigger_pkt_any_0_execute, input io_trigger_pkt_any_0_m, input [31:0] io_trigger_pkt_any_0_tdata2, input io_trigger_pkt_any_1_select, - input io_trigger_pkt_any_1_match_, + input io_trigger_pkt_any_1_match_pkt, input io_trigger_pkt_any_1_store, input io_trigger_pkt_any_1_load, input io_trigger_pkt_any_1_execute, input io_trigger_pkt_any_1_m, input [31:0] io_trigger_pkt_any_1_tdata2, input io_trigger_pkt_any_2_select, - input io_trigger_pkt_any_2_match_, + input io_trigger_pkt_any_2_match_pkt, input io_trigger_pkt_any_2_store, input io_trigger_pkt_any_2_load, input io_trigger_pkt_any_2_execute, input io_trigger_pkt_any_2_m, input [31:0] io_trigger_pkt_any_2_tdata2, input io_trigger_pkt_any_3_select, - input io_trigger_pkt_any_3_match_, + input io_trigger_pkt_any_3_match_pkt, input io_trigger_pkt_any_3_store, input io_trigger_pkt_any_3_load, input io_trigger_pkt_any_3_execute, @@ -32,686 +32,582 @@ module el2_dec_trigger( input [30:0] io_dec_i0_pc_d, output [3:0] io_dec_i0_trigger_match_d ); - wire _T = ~io_trigger_pkt_any_0_select; // @[el2_lsu_trigger.scala 15:63] - wire _T_1 = _T & io_trigger_pkt_any_0_execute; // @[el2_lsu_trigger.scala 15:93] + wire _T = ~io_trigger_pkt_any_0_select; // @[el2_dec_trigger.scala 14:63] + wire _T_1 = _T & io_trigger_pkt_any_0_execute; // @[el2_dec_trigger.scala 14:93] wire [9:0] _T_11 = {_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1}; // @[Cat.scala 29:58] wire [18:0] _T_20 = {_T_11,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1}; // @[Cat.scala 29:58] wire [27:0] _T_29 = {_T_20,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1}; // @[Cat.scala 29:58] wire [31:0] _T_33 = {_T_29,_T_1,_T_1,_T_1,_T_1}; // @[Cat.scala 29:58] wire [31:0] _T_35 = {io_dec_i0_pc_d,io_trigger_pkt_any_0_tdata2[0]}; // @[Cat.scala 29:58] - wire [31:0] dec_i0_match_data_0 = _T_33 & _T_35; // @[el2_lsu_trigger.scala 15:127] - wire _T_37 = ~io_trigger_pkt_any_1_select; // @[el2_lsu_trigger.scala 15:63] - wire _T_38 = _T_37 & io_trigger_pkt_any_1_execute; // @[el2_lsu_trigger.scala 15:93] + wire [31:0] dec_i0_match_data_0 = _T_33 & _T_35; // @[el2_dec_trigger.scala 14:127] + wire _T_37 = ~io_trigger_pkt_any_1_select; // @[el2_dec_trigger.scala 14:63] + wire _T_38 = _T_37 & io_trigger_pkt_any_1_execute; // @[el2_dec_trigger.scala 14:93] wire [9:0] _T_48 = {_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38}; // @[Cat.scala 29:58] wire [18:0] _T_57 = {_T_48,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38}; // @[Cat.scala 29:58] wire [27:0] _T_66 = {_T_57,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38}; // @[Cat.scala 29:58] wire [31:0] _T_70 = {_T_66,_T_38,_T_38,_T_38,_T_38}; // @[Cat.scala 29:58] wire [31:0] _T_72 = {io_dec_i0_pc_d,io_trigger_pkt_any_1_tdata2[0]}; // @[Cat.scala 29:58] - wire [31:0] dec_i0_match_data_1 = _T_70 & _T_72; // @[el2_lsu_trigger.scala 15:127] - wire _T_74 = ~io_trigger_pkt_any_2_select; // @[el2_lsu_trigger.scala 15:63] - wire _T_75 = _T_74 & io_trigger_pkt_any_2_execute; // @[el2_lsu_trigger.scala 15:93] + wire [31:0] dec_i0_match_data_1 = _T_70 & _T_72; // @[el2_dec_trigger.scala 14:127] + wire _T_74 = ~io_trigger_pkt_any_2_select; // @[el2_dec_trigger.scala 14:63] + wire _T_75 = _T_74 & io_trigger_pkt_any_2_execute; // @[el2_dec_trigger.scala 14:93] wire [9:0] _T_85 = {_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75}; // @[Cat.scala 29:58] wire [18:0] _T_94 = {_T_85,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75}; // @[Cat.scala 29:58] wire [27:0] _T_103 = {_T_94,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75}; // @[Cat.scala 29:58] wire [31:0] _T_107 = {_T_103,_T_75,_T_75,_T_75,_T_75}; // @[Cat.scala 29:58] wire [31:0] _T_109 = {io_dec_i0_pc_d,io_trigger_pkt_any_2_tdata2[0]}; // @[Cat.scala 29:58] - wire [31:0] dec_i0_match_data_2 = _T_107 & _T_109; // @[el2_lsu_trigger.scala 15:127] - wire _T_111 = ~io_trigger_pkt_any_3_select; // @[el2_lsu_trigger.scala 15:63] - wire _T_112 = _T_111 & io_trigger_pkt_any_3_execute; // @[el2_lsu_trigger.scala 15:93] + wire [31:0] dec_i0_match_data_2 = _T_107 & _T_109; // @[el2_dec_trigger.scala 14:127] + wire _T_111 = ~io_trigger_pkt_any_3_select; // @[el2_dec_trigger.scala 14:63] + wire _T_112 = _T_111 & io_trigger_pkt_any_3_execute; // @[el2_dec_trigger.scala 14:93] wire [9:0] _T_122 = {_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112}; // @[Cat.scala 29:58] wire [18:0] _T_131 = {_T_122,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112}; // @[Cat.scala 29:58] wire [27:0] _T_140 = {_T_131,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112}; // @[Cat.scala 29:58] wire [31:0] _T_144 = {_T_140,_T_112,_T_112,_T_112,_T_112}; // @[Cat.scala 29:58] wire [31:0] _T_146 = {io_dec_i0_pc_d,io_trigger_pkt_any_3_tdata2[0]}; // @[Cat.scala 29:58] - wire [31:0] dec_i0_match_data_3 = _T_144 & _T_146; // @[el2_lsu_trigger.scala 15:127] - wire _T_148 = io_trigger_pkt_any_0_execute & io_trigger_pkt_any_0_m; // @[el2_lsu_trigger.scala 16:83] - wire _T_151 = &io_trigger_pkt_any_0_tdata2; // @[el2_lib.scala 194:45] - wire _T_152 = ~_T_151; // @[el2_lib.scala 194:39] - wire _T_153 = io_trigger_pkt_any_0_match_ & _T_152; // @[el2_lib.scala 194:37] - wire _T_156 = io_trigger_pkt_any_0_tdata2[0] == dec_i0_match_data_0[0]; // @[el2_lib.scala 195:52] - wire _T_157 = _T_153 | _T_156; // @[el2_lib.scala 195:41] - wire _T_159 = &io_trigger_pkt_any_0_tdata2[0]; // @[el2_lib.scala 197:38] - wire _T_160 = _T_159 & _T_153; // @[el2_lib.scala 197:43] - wire _T_163 = io_trigger_pkt_any_0_tdata2[1] == dec_i0_match_data_0[1]; // @[el2_lib.scala 197:80] - wire _T_164 = _T_160 | _T_163; // @[el2_lib.scala 197:25] - wire _T_166 = &io_trigger_pkt_any_0_tdata2[1:0]; // @[el2_lib.scala 197:38] - wire _T_167 = _T_166 & _T_153; // @[el2_lib.scala 197:43] - wire _T_170 = io_trigger_pkt_any_0_tdata2[2] == dec_i0_match_data_0[2]; // @[el2_lib.scala 197:80] - wire _T_171 = _T_167 | _T_170; // @[el2_lib.scala 197:25] - wire _T_173 = &io_trigger_pkt_any_0_tdata2[2:0]; // @[el2_lib.scala 197:38] - wire _T_174 = _T_173 & _T_153; // @[el2_lib.scala 197:43] - wire _T_177 = io_trigger_pkt_any_0_tdata2[3] == dec_i0_match_data_0[3]; // @[el2_lib.scala 197:80] - wire _T_178 = _T_174 | _T_177; // @[el2_lib.scala 197:25] - wire _T_180 = &io_trigger_pkt_any_0_tdata2[3:0]; // @[el2_lib.scala 197:38] - wire _T_181 = _T_180 & _T_153; // @[el2_lib.scala 197:43] - wire _T_184 = io_trigger_pkt_any_0_tdata2[4] == dec_i0_match_data_0[4]; // @[el2_lib.scala 197:80] - wire _T_185 = _T_181 | _T_184; // @[el2_lib.scala 197:25] - wire _T_187 = &io_trigger_pkt_any_0_tdata2[4:0]; // @[el2_lib.scala 197:38] - wire _T_188 = _T_187 & _T_153; // @[el2_lib.scala 197:43] - wire _T_191 = io_trigger_pkt_any_0_tdata2[5] == dec_i0_match_data_0[5]; // @[el2_lib.scala 197:80] - wire _T_192 = _T_188 | _T_191; // @[el2_lib.scala 197:25] - wire _T_194 = &io_trigger_pkt_any_0_tdata2[5:0]; // @[el2_lib.scala 197:38] - wire _T_195 = _T_194 & _T_153; // @[el2_lib.scala 197:43] - wire _T_198 = io_trigger_pkt_any_0_tdata2[6] == dec_i0_match_data_0[6]; // @[el2_lib.scala 197:80] - wire _T_199 = _T_195 | _T_198; // @[el2_lib.scala 197:25] - wire _T_201 = &io_trigger_pkt_any_0_tdata2[6:0]; // @[el2_lib.scala 197:38] - wire _T_202 = _T_201 & _T_153; // @[el2_lib.scala 197:43] - wire _T_205 = io_trigger_pkt_any_0_tdata2[7] == dec_i0_match_data_0[7]; // @[el2_lib.scala 197:80] - wire _T_206 = _T_202 | _T_205; // @[el2_lib.scala 197:25] - wire _T_208 = &io_trigger_pkt_any_0_tdata2[7:0]; // @[el2_lib.scala 197:38] - wire _T_209 = _T_208 & _T_153; // @[el2_lib.scala 197:43] - wire _T_212 = io_trigger_pkt_any_0_tdata2[8] == dec_i0_match_data_0[8]; // @[el2_lib.scala 197:80] - wire _T_213 = _T_209 | _T_212; // @[el2_lib.scala 197:25] - wire _T_215 = &io_trigger_pkt_any_0_tdata2[8:0]; // @[el2_lib.scala 197:38] - wire _T_216 = _T_215 & _T_153; // @[el2_lib.scala 197:43] - wire _T_219 = io_trigger_pkt_any_0_tdata2[9] == dec_i0_match_data_0[9]; // @[el2_lib.scala 197:80] - wire _T_220 = _T_216 | _T_219; // @[el2_lib.scala 197:25] - wire _T_222 = &io_trigger_pkt_any_0_tdata2[9:0]; // @[el2_lib.scala 197:38] - wire _T_223 = _T_222 & _T_153; // @[el2_lib.scala 197:43] - wire _T_226 = io_trigger_pkt_any_0_tdata2[10] == dec_i0_match_data_0[10]; // @[el2_lib.scala 197:80] - wire _T_227 = _T_223 | _T_226; // @[el2_lib.scala 197:25] - wire _T_229 = &io_trigger_pkt_any_0_tdata2[10:0]; // @[el2_lib.scala 197:38] - wire _T_230 = _T_229 & _T_153; // @[el2_lib.scala 197:43] - wire _T_233 = io_trigger_pkt_any_0_tdata2[11] == dec_i0_match_data_0[11]; // @[el2_lib.scala 197:80] - wire _T_234 = _T_230 | _T_233; // @[el2_lib.scala 197:25] - wire _T_236 = &io_trigger_pkt_any_0_tdata2[11:0]; // @[el2_lib.scala 197:38] - wire _T_237 = _T_236 & _T_153; // @[el2_lib.scala 197:43] - wire _T_240 = io_trigger_pkt_any_0_tdata2[12] == dec_i0_match_data_0[12]; // @[el2_lib.scala 197:80] - wire _T_241 = _T_237 | _T_240; // @[el2_lib.scala 197:25] - wire _T_243 = &io_trigger_pkt_any_0_tdata2[12:0]; // @[el2_lib.scala 197:38] - wire _T_244 = _T_243 & _T_153; // @[el2_lib.scala 197:43] - wire _T_247 = io_trigger_pkt_any_0_tdata2[13] == dec_i0_match_data_0[13]; // @[el2_lib.scala 197:80] - wire _T_248 = _T_244 | _T_247; // @[el2_lib.scala 197:25] - wire _T_250 = &io_trigger_pkt_any_0_tdata2[13:0]; // @[el2_lib.scala 197:38] - wire _T_251 = _T_250 & _T_153; // @[el2_lib.scala 197:43] - wire _T_254 = io_trigger_pkt_any_0_tdata2[14] == dec_i0_match_data_0[14]; // @[el2_lib.scala 197:80] - wire _T_255 = _T_251 | _T_254; // @[el2_lib.scala 197:25] - wire _T_257 = &io_trigger_pkt_any_0_tdata2[14:0]; // @[el2_lib.scala 197:38] - wire _T_258 = _T_257 & _T_153; // @[el2_lib.scala 197:43] - wire _T_261 = io_trigger_pkt_any_0_tdata2[15] == dec_i0_match_data_0[15]; // @[el2_lib.scala 197:80] - wire _T_262 = _T_258 | _T_261; // @[el2_lib.scala 197:25] - wire _T_264 = &io_trigger_pkt_any_0_tdata2[15:0]; // @[el2_lib.scala 197:38] - wire _T_265 = _T_264 & _T_153; // @[el2_lib.scala 197:43] - wire _T_268 = io_trigger_pkt_any_0_tdata2[16] == dec_i0_match_data_0[16]; // @[el2_lib.scala 197:80] - wire _T_269 = _T_265 | _T_268; // @[el2_lib.scala 197:25] - wire _T_271 = &io_trigger_pkt_any_0_tdata2[16:0]; // @[el2_lib.scala 197:38] - wire _T_272 = _T_271 & _T_153; // @[el2_lib.scala 197:43] - wire _T_275 = io_trigger_pkt_any_0_tdata2[17] == dec_i0_match_data_0[17]; // @[el2_lib.scala 197:80] - wire _T_276 = _T_272 | _T_275; // @[el2_lib.scala 197:25] - wire _T_278 = &io_trigger_pkt_any_0_tdata2[17:0]; // @[el2_lib.scala 197:38] - wire _T_279 = _T_278 & _T_153; // @[el2_lib.scala 197:43] - wire _T_282 = io_trigger_pkt_any_0_tdata2[18] == dec_i0_match_data_0[18]; // @[el2_lib.scala 197:80] - wire _T_283 = _T_279 | _T_282; // @[el2_lib.scala 197:25] - wire _T_285 = &io_trigger_pkt_any_0_tdata2[18:0]; // @[el2_lib.scala 197:38] - wire _T_286 = _T_285 & _T_153; // @[el2_lib.scala 197:43] - wire _T_289 = io_trigger_pkt_any_0_tdata2[19] == dec_i0_match_data_0[19]; // @[el2_lib.scala 197:80] - wire _T_290 = _T_286 | _T_289; // @[el2_lib.scala 197:25] - wire _T_292 = &io_trigger_pkt_any_0_tdata2[19:0]; // @[el2_lib.scala 197:38] - wire _T_293 = _T_292 & _T_153; // @[el2_lib.scala 197:43] - wire _T_296 = io_trigger_pkt_any_0_tdata2[20] == dec_i0_match_data_0[20]; // @[el2_lib.scala 197:80] - wire _T_297 = _T_293 | _T_296; // @[el2_lib.scala 197:25] - wire _T_299 = &io_trigger_pkt_any_0_tdata2[20:0]; // @[el2_lib.scala 197:38] - wire _T_300 = _T_299 & _T_153; // @[el2_lib.scala 197:43] - wire _T_303 = io_trigger_pkt_any_0_tdata2[21] == dec_i0_match_data_0[21]; // @[el2_lib.scala 197:80] - wire _T_304 = _T_300 | _T_303; // @[el2_lib.scala 197:25] - wire _T_306 = &io_trigger_pkt_any_0_tdata2[21:0]; // @[el2_lib.scala 197:38] - wire _T_307 = _T_306 & _T_153; // @[el2_lib.scala 197:43] - wire _T_310 = io_trigger_pkt_any_0_tdata2[22] == dec_i0_match_data_0[22]; // @[el2_lib.scala 197:80] - wire _T_311 = _T_307 | _T_310; // @[el2_lib.scala 197:25] - wire _T_313 = &io_trigger_pkt_any_0_tdata2[22:0]; // @[el2_lib.scala 197:38] - wire _T_314 = _T_313 & _T_153; // @[el2_lib.scala 197:43] - wire _T_317 = io_trigger_pkt_any_0_tdata2[23] == dec_i0_match_data_0[23]; // @[el2_lib.scala 197:80] - wire _T_318 = _T_314 | _T_317; // @[el2_lib.scala 197:25] - wire _T_320 = &io_trigger_pkt_any_0_tdata2[23:0]; // @[el2_lib.scala 197:38] - wire _T_321 = _T_320 & _T_153; // @[el2_lib.scala 197:43] - wire _T_324 = io_trigger_pkt_any_0_tdata2[24] == dec_i0_match_data_0[24]; // @[el2_lib.scala 197:80] - wire _T_325 = _T_321 | _T_324; // @[el2_lib.scala 197:25] - wire _T_327 = &io_trigger_pkt_any_0_tdata2[24:0]; // @[el2_lib.scala 197:38] - wire _T_328 = _T_327 & _T_153; // @[el2_lib.scala 197:43] - wire _T_331 = io_trigger_pkt_any_0_tdata2[25] == dec_i0_match_data_0[25]; // @[el2_lib.scala 197:80] - wire _T_332 = _T_328 | _T_331; // @[el2_lib.scala 197:25] - wire _T_334 = &io_trigger_pkt_any_0_tdata2[25:0]; // @[el2_lib.scala 197:38] - wire _T_335 = _T_334 & _T_153; // @[el2_lib.scala 197:43] - wire _T_338 = io_trigger_pkt_any_0_tdata2[26] == dec_i0_match_data_0[26]; // @[el2_lib.scala 197:80] - wire _T_339 = _T_335 | _T_338; // @[el2_lib.scala 197:25] - wire _T_341 = &io_trigger_pkt_any_0_tdata2[26:0]; // @[el2_lib.scala 197:38] - wire _T_342 = _T_341 & _T_153; // @[el2_lib.scala 197:43] - wire _T_345 = io_trigger_pkt_any_0_tdata2[27] == dec_i0_match_data_0[27]; // @[el2_lib.scala 197:80] - wire _T_346 = _T_342 | _T_345; // @[el2_lib.scala 197:25] - wire _T_348 = &io_trigger_pkt_any_0_tdata2[27:0]; // @[el2_lib.scala 197:38] - wire _T_349 = _T_348 & _T_153; // @[el2_lib.scala 197:43] - wire _T_352 = io_trigger_pkt_any_0_tdata2[28] == dec_i0_match_data_0[28]; // @[el2_lib.scala 197:80] - wire _T_353 = _T_349 | _T_352; // @[el2_lib.scala 197:25] - wire _T_355 = &io_trigger_pkt_any_0_tdata2[28:0]; // @[el2_lib.scala 197:38] - wire _T_356 = _T_355 & _T_153; // @[el2_lib.scala 197:43] - wire _T_359 = io_trigger_pkt_any_0_tdata2[29] == dec_i0_match_data_0[29]; // @[el2_lib.scala 197:80] - wire _T_360 = _T_356 | _T_359; // @[el2_lib.scala 197:25] - wire _T_362 = &io_trigger_pkt_any_0_tdata2[29:0]; // @[el2_lib.scala 197:38] - wire _T_363 = _T_362 & _T_153; // @[el2_lib.scala 197:43] - wire _T_366 = io_trigger_pkt_any_0_tdata2[30] == dec_i0_match_data_0[30]; // @[el2_lib.scala 197:80] - wire _T_367 = _T_363 | _T_366; // @[el2_lib.scala 197:25] - wire _T_369 = &io_trigger_pkt_any_0_tdata2[30:0]; // @[el2_lib.scala 197:38] - wire _T_370 = _T_369 & _T_153; // @[el2_lib.scala 197:43] - wire _T_373 = io_trigger_pkt_any_0_tdata2[31] == dec_i0_match_data_0[31]; // @[el2_lib.scala 197:80] - wire _T_374 = _T_370 | _T_373; // @[el2_lib.scala 197:25] - wire _T_375 = _T_157 & _T_164; // @[el2_lib.scala 198:22] - wire _T_376 = _T_375 & _T_171; // @[el2_lib.scala 198:22] - wire _T_377 = _T_376 & _T_178; // @[el2_lib.scala 198:22] - wire _T_378 = _T_377 & _T_185; // @[el2_lib.scala 198:22] - wire _T_379 = _T_378 & _T_192; // @[el2_lib.scala 198:22] - wire _T_380 = _T_379 & _T_199; // @[el2_lib.scala 198:22] - wire _T_381 = _T_380 & _T_206; // @[el2_lib.scala 198:22] - wire _T_382 = _T_381 & _T_213; // @[el2_lib.scala 198:22] - wire _T_383 = _T_382 & _T_220; // @[el2_lib.scala 198:22] - wire _T_384 = _T_383 & _T_227; // @[el2_lib.scala 198:22] - wire _T_385 = _T_384 & _T_234; // @[el2_lib.scala 198:22] - wire _T_386 = _T_385 & _T_241; // @[el2_lib.scala 198:22] - wire _T_387 = _T_386 & _T_248; // @[el2_lib.scala 198:22] - wire _T_388 = _T_387 & _T_255; // @[el2_lib.scala 198:22] - wire _T_389 = _T_388 & _T_262; // @[el2_lib.scala 198:22] - wire _T_390 = _T_389 & _T_269; // @[el2_lib.scala 198:22] - wire _T_391 = _T_390 & _T_276; // @[el2_lib.scala 198:22] - wire _T_392 = _T_391 & _T_283; // @[el2_lib.scala 198:22] - wire _T_393 = _T_392 & _T_290; // @[el2_lib.scala 198:22] - wire _T_394 = _T_393 & _T_297; // @[el2_lib.scala 198:22] - wire _T_395 = _T_394 & _T_304; // @[el2_lib.scala 198:22] - wire _T_396 = _T_395 & _T_311; // @[el2_lib.scala 198:22] - wire _T_397 = _T_396 & _T_318; // @[el2_lib.scala 198:22] - wire _T_398 = _T_397 & _T_325; // @[el2_lib.scala 198:22] - wire _T_399 = _T_398 & _T_332; // @[el2_lib.scala 198:22] - wire _T_400 = _T_399 & _T_339; // @[el2_lib.scala 198:22] - wire _T_401 = _T_400 & _T_346; // @[el2_lib.scala 198:22] - wire _T_402 = _T_401 & _T_353; // @[el2_lib.scala 198:22] - wire _T_403 = _T_402 & _T_360; // @[el2_lib.scala 198:22] - wire _T_404 = _T_403 & _T_367; // @[el2_lib.scala 198:22] - wire _T_405 = _T_404 & _T_374; // @[el2_lib.scala 198:22] - wire _T_406 = _T_148 & _T_405; // @[el2_lsu_trigger.scala 16:109] - wire _T_407 = io_trigger_pkt_any_1_execute & io_trigger_pkt_any_1_m; // @[el2_lsu_trigger.scala 16:83] - wire _T_410 = &io_trigger_pkt_any_1_tdata2; // @[el2_lib.scala 194:45] - wire _T_411 = ~_T_410; // @[el2_lib.scala 194:39] - wire _T_412 = io_trigger_pkt_any_1_match_ & _T_411; // @[el2_lib.scala 194:37] - wire _T_415 = io_trigger_pkt_any_1_tdata2[0] == dec_i0_match_data_1[0]; // @[el2_lib.scala 195:52] - wire _T_416 = _T_412 | _T_415; // @[el2_lib.scala 195:41] - wire _T_418 = &io_trigger_pkt_any_1_tdata2[0]; // @[el2_lib.scala 197:38] - wire _T_419 = _T_418 & _T_412; // @[el2_lib.scala 197:43] - wire _T_422 = io_trigger_pkt_any_1_tdata2[1] == dec_i0_match_data_1[1]; // @[el2_lib.scala 197:80] - wire _T_423 = _T_419 | _T_422; // @[el2_lib.scala 197:25] - wire _T_425 = &io_trigger_pkt_any_1_tdata2[1:0]; // @[el2_lib.scala 197:38] - wire _T_426 = _T_425 & _T_412; // @[el2_lib.scala 197:43] - wire _T_429 = io_trigger_pkt_any_1_tdata2[2] == dec_i0_match_data_1[2]; // @[el2_lib.scala 197:80] - wire _T_430 = _T_426 | _T_429; // @[el2_lib.scala 197:25] - wire _T_432 = &io_trigger_pkt_any_1_tdata2[2:0]; // @[el2_lib.scala 197:38] - wire _T_433 = _T_432 & _T_412; // @[el2_lib.scala 197:43] - wire _T_436 = io_trigger_pkt_any_1_tdata2[3] == dec_i0_match_data_1[3]; // @[el2_lib.scala 197:80] - wire _T_437 = _T_433 | _T_436; // @[el2_lib.scala 197:25] - wire _T_439 = &io_trigger_pkt_any_1_tdata2[3:0]; // @[el2_lib.scala 197:38] - wire _T_440 = _T_439 & _T_412; // @[el2_lib.scala 197:43] - wire _T_443 = io_trigger_pkt_any_1_tdata2[4] == dec_i0_match_data_1[4]; // @[el2_lib.scala 197:80] - wire _T_444 = _T_440 | _T_443; // @[el2_lib.scala 197:25] - wire _T_446 = &io_trigger_pkt_any_1_tdata2[4:0]; // @[el2_lib.scala 197:38] - wire _T_447 = _T_446 & _T_412; // @[el2_lib.scala 197:43] - wire _T_450 = io_trigger_pkt_any_1_tdata2[5] == dec_i0_match_data_1[5]; // @[el2_lib.scala 197:80] - wire _T_451 = _T_447 | _T_450; // @[el2_lib.scala 197:25] - wire _T_453 = &io_trigger_pkt_any_1_tdata2[5:0]; // @[el2_lib.scala 197:38] - wire _T_454 = _T_453 & _T_412; // @[el2_lib.scala 197:43] - wire _T_457 = io_trigger_pkt_any_1_tdata2[6] == dec_i0_match_data_1[6]; // @[el2_lib.scala 197:80] - wire _T_458 = _T_454 | _T_457; // @[el2_lib.scala 197:25] - wire _T_460 = &io_trigger_pkt_any_1_tdata2[6:0]; // @[el2_lib.scala 197:38] - wire _T_461 = _T_460 & _T_412; // @[el2_lib.scala 197:43] - wire _T_464 = io_trigger_pkt_any_1_tdata2[7] == dec_i0_match_data_1[7]; // @[el2_lib.scala 197:80] - wire _T_465 = _T_461 | _T_464; // @[el2_lib.scala 197:25] - wire _T_467 = &io_trigger_pkt_any_1_tdata2[7:0]; // @[el2_lib.scala 197:38] - wire _T_468 = _T_467 & _T_412; // @[el2_lib.scala 197:43] - wire _T_471 = io_trigger_pkt_any_1_tdata2[8] == dec_i0_match_data_1[8]; // @[el2_lib.scala 197:80] - wire _T_472 = _T_468 | _T_471; // @[el2_lib.scala 197:25] - wire _T_474 = &io_trigger_pkt_any_1_tdata2[8:0]; // @[el2_lib.scala 197:38] - wire _T_475 = _T_474 & _T_412; // @[el2_lib.scala 197:43] - wire _T_478 = io_trigger_pkt_any_1_tdata2[9] == dec_i0_match_data_1[9]; // @[el2_lib.scala 197:80] - wire _T_479 = _T_475 | _T_478; // @[el2_lib.scala 197:25] - wire _T_481 = &io_trigger_pkt_any_1_tdata2[9:0]; // @[el2_lib.scala 197:38] - wire _T_482 = _T_481 & _T_412; // @[el2_lib.scala 197:43] - wire _T_485 = io_trigger_pkt_any_1_tdata2[10] == dec_i0_match_data_1[10]; // @[el2_lib.scala 197:80] - wire _T_486 = _T_482 | _T_485; // @[el2_lib.scala 197:25] - wire _T_488 = &io_trigger_pkt_any_1_tdata2[10:0]; // @[el2_lib.scala 197:38] - wire _T_489 = _T_488 & _T_412; // @[el2_lib.scala 197:43] - wire _T_492 = io_trigger_pkt_any_1_tdata2[11] == dec_i0_match_data_1[11]; // @[el2_lib.scala 197:80] - wire _T_493 = _T_489 | _T_492; // @[el2_lib.scala 197:25] - wire _T_495 = &io_trigger_pkt_any_1_tdata2[11:0]; // @[el2_lib.scala 197:38] - wire _T_496 = _T_495 & _T_412; // @[el2_lib.scala 197:43] - wire _T_499 = io_trigger_pkt_any_1_tdata2[12] == dec_i0_match_data_1[12]; // @[el2_lib.scala 197:80] - wire _T_500 = _T_496 | _T_499; // @[el2_lib.scala 197:25] - wire _T_502 = &io_trigger_pkt_any_1_tdata2[12:0]; // @[el2_lib.scala 197:38] - wire _T_503 = _T_502 & _T_412; // @[el2_lib.scala 197:43] - wire _T_506 = io_trigger_pkt_any_1_tdata2[13] == dec_i0_match_data_1[13]; // @[el2_lib.scala 197:80] - wire _T_507 = _T_503 | _T_506; // @[el2_lib.scala 197:25] - wire _T_509 = &io_trigger_pkt_any_1_tdata2[13:0]; // @[el2_lib.scala 197:38] - wire _T_510 = _T_509 & _T_412; // @[el2_lib.scala 197:43] - wire _T_513 = io_trigger_pkt_any_1_tdata2[14] == dec_i0_match_data_1[14]; // @[el2_lib.scala 197:80] - wire _T_514 = _T_510 | _T_513; // @[el2_lib.scala 197:25] - wire _T_516 = &io_trigger_pkt_any_1_tdata2[14:0]; // @[el2_lib.scala 197:38] - wire _T_517 = _T_516 & _T_412; // @[el2_lib.scala 197:43] - wire _T_520 = io_trigger_pkt_any_1_tdata2[15] == dec_i0_match_data_1[15]; // @[el2_lib.scala 197:80] - wire _T_521 = _T_517 | _T_520; // @[el2_lib.scala 197:25] - wire _T_523 = &io_trigger_pkt_any_1_tdata2[15:0]; // @[el2_lib.scala 197:38] - wire _T_524 = _T_523 & _T_412; // @[el2_lib.scala 197:43] - wire _T_527 = io_trigger_pkt_any_1_tdata2[16] == dec_i0_match_data_1[16]; // @[el2_lib.scala 197:80] - wire _T_528 = _T_524 | _T_527; // @[el2_lib.scala 197:25] - wire _T_530 = &io_trigger_pkt_any_1_tdata2[16:0]; // @[el2_lib.scala 197:38] - wire _T_531 = _T_530 & _T_412; // @[el2_lib.scala 197:43] - wire _T_534 = io_trigger_pkt_any_1_tdata2[17] == dec_i0_match_data_1[17]; // @[el2_lib.scala 197:80] - wire _T_535 = _T_531 | _T_534; // @[el2_lib.scala 197:25] - wire _T_537 = &io_trigger_pkt_any_1_tdata2[17:0]; // @[el2_lib.scala 197:38] - wire _T_538 = _T_537 & _T_412; // @[el2_lib.scala 197:43] - wire _T_541 = io_trigger_pkt_any_1_tdata2[18] == dec_i0_match_data_1[18]; // @[el2_lib.scala 197:80] - wire _T_542 = _T_538 | _T_541; // @[el2_lib.scala 197:25] - wire _T_544 = &io_trigger_pkt_any_1_tdata2[18:0]; // @[el2_lib.scala 197:38] - wire _T_545 = _T_544 & _T_412; // @[el2_lib.scala 197:43] - wire _T_548 = io_trigger_pkt_any_1_tdata2[19] == dec_i0_match_data_1[19]; // @[el2_lib.scala 197:80] - wire _T_549 = _T_545 | _T_548; // @[el2_lib.scala 197:25] - wire _T_551 = &io_trigger_pkt_any_1_tdata2[19:0]; // @[el2_lib.scala 197:38] - wire _T_552 = _T_551 & _T_412; // @[el2_lib.scala 197:43] - wire _T_555 = io_trigger_pkt_any_1_tdata2[20] == dec_i0_match_data_1[20]; // @[el2_lib.scala 197:80] - wire _T_556 = _T_552 | _T_555; // @[el2_lib.scala 197:25] - wire _T_558 = &io_trigger_pkt_any_1_tdata2[20:0]; // @[el2_lib.scala 197:38] - wire _T_559 = _T_558 & _T_412; // @[el2_lib.scala 197:43] - wire _T_562 = io_trigger_pkt_any_1_tdata2[21] == dec_i0_match_data_1[21]; // @[el2_lib.scala 197:80] - wire _T_563 = _T_559 | _T_562; // @[el2_lib.scala 197:25] - wire _T_565 = &io_trigger_pkt_any_1_tdata2[21:0]; // @[el2_lib.scala 197:38] - wire _T_566 = _T_565 & _T_412; // @[el2_lib.scala 197:43] - wire _T_569 = io_trigger_pkt_any_1_tdata2[22] == dec_i0_match_data_1[22]; // @[el2_lib.scala 197:80] - wire _T_570 = _T_566 | _T_569; // @[el2_lib.scala 197:25] - wire _T_572 = &io_trigger_pkt_any_1_tdata2[22:0]; // @[el2_lib.scala 197:38] - wire _T_573 = _T_572 & _T_412; // @[el2_lib.scala 197:43] - wire _T_576 = io_trigger_pkt_any_1_tdata2[23] == dec_i0_match_data_1[23]; // @[el2_lib.scala 197:80] - wire _T_577 = _T_573 | _T_576; // @[el2_lib.scala 197:25] - wire _T_579 = &io_trigger_pkt_any_1_tdata2[23:0]; // @[el2_lib.scala 197:38] - wire _T_580 = _T_579 & _T_412; // @[el2_lib.scala 197:43] - wire _T_583 = io_trigger_pkt_any_1_tdata2[24] == dec_i0_match_data_1[24]; // @[el2_lib.scala 197:80] - wire _T_584 = _T_580 | _T_583; // @[el2_lib.scala 197:25] - wire _T_586 = &io_trigger_pkt_any_1_tdata2[24:0]; // @[el2_lib.scala 197:38] - wire _T_587 = _T_586 & _T_412; // @[el2_lib.scala 197:43] - wire _T_590 = io_trigger_pkt_any_1_tdata2[25] == dec_i0_match_data_1[25]; // @[el2_lib.scala 197:80] - wire _T_591 = _T_587 | _T_590; // @[el2_lib.scala 197:25] - wire _T_593 = &io_trigger_pkt_any_1_tdata2[25:0]; // @[el2_lib.scala 197:38] - wire _T_594 = _T_593 & _T_412; // @[el2_lib.scala 197:43] - wire _T_597 = io_trigger_pkt_any_1_tdata2[26] == dec_i0_match_data_1[26]; // @[el2_lib.scala 197:80] - wire _T_598 = _T_594 | _T_597; // @[el2_lib.scala 197:25] - wire _T_600 = &io_trigger_pkt_any_1_tdata2[26:0]; // @[el2_lib.scala 197:38] - wire _T_601 = _T_600 & _T_412; // @[el2_lib.scala 197:43] - wire _T_604 = io_trigger_pkt_any_1_tdata2[27] == dec_i0_match_data_1[27]; // @[el2_lib.scala 197:80] - wire _T_605 = _T_601 | _T_604; // @[el2_lib.scala 197:25] - wire _T_607 = &io_trigger_pkt_any_1_tdata2[27:0]; // @[el2_lib.scala 197:38] - wire _T_608 = _T_607 & _T_412; // @[el2_lib.scala 197:43] - wire _T_611 = io_trigger_pkt_any_1_tdata2[28] == dec_i0_match_data_1[28]; // @[el2_lib.scala 197:80] - wire _T_612 = _T_608 | _T_611; // @[el2_lib.scala 197:25] - wire _T_614 = &io_trigger_pkt_any_1_tdata2[28:0]; // @[el2_lib.scala 197:38] - wire _T_615 = _T_614 & _T_412; // @[el2_lib.scala 197:43] - wire _T_618 = io_trigger_pkt_any_1_tdata2[29] == dec_i0_match_data_1[29]; // @[el2_lib.scala 197:80] - wire _T_619 = _T_615 | _T_618; // @[el2_lib.scala 197:25] - wire _T_621 = &io_trigger_pkt_any_1_tdata2[29:0]; // @[el2_lib.scala 197:38] - wire _T_622 = _T_621 & _T_412; // @[el2_lib.scala 197:43] - wire _T_625 = io_trigger_pkt_any_1_tdata2[30] == dec_i0_match_data_1[30]; // @[el2_lib.scala 197:80] - wire _T_626 = _T_622 | _T_625; // @[el2_lib.scala 197:25] - wire _T_628 = &io_trigger_pkt_any_1_tdata2[30:0]; // @[el2_lib.scala 197:38] - wire _T_629 = _T_628 & _T_412; // @[el2_lib.scala 197:43] - wire _T_632 = io_trigger_pkt_any_1_tdata2[31] == dec_i0_match_data_1[31]; // @[el2_lib.scala 197:80] - wire _T_633 = _T_629 | _T_632; // @[el2_lib.scala 197:25] - wire _T_634 = _T_416 & _T_423; // @[el2_lib.scala 198:22] - wire _T_635 = _T_634 & _T_430; // @[el2_lib.scala 198:22] - wire _T_636 = _T_635 & _T_437; // @[el2_lib.scala 198:22] - wire _T_637 = _T_636 & _T_444; // @[el2_lib.scala 198:22] - wire _T_638 = _T_637 & _T_451; // @[el2_lib.scala 198:22] - wire _T_639 = _T_638 & _T_458; // @[el2_lib.scala 198:22] - wire _T_640 = _T_639 & _T_465; // @[el2_lib.scala 198:22] - wire _T_641 = _T_640 & _T_472; // @[el2_lib.scala 198:22] - wire _T_642 = _T_641 & _T_479; // @[el2_lib.scala 198:22] - wire _T_643 = _T_642 & _T_486; // @[el2_lib.scala 198:22] - wire _T_644 = _T_643 & _T_493; // @[el2_lib.scala 198:22] - wire _T_645 = _T_644 & _T_500; // @[el2_lib.scala 198:22] - wire _T_646 = _T_645 & _T_507; // @[el2_lib.scala 198:22] - wire _T_647 = _T_646 & _T_514; // @[el2_lib.scala 198:22] - wire _T_648 = _T_647 & _T_521; // @[el2_lib.scala 198:22] - wire _T_649 = _T_648 & _T_528; // @[el2_lib.scala 198:22] - wire _T_650 = _T_649 & _T_535; // @[el2_lib.scala 198:22] - wire _T_651 = _T_650 & _T_542; // @[el2_lib.scala 198:22] - wire _T_652 = _T_651 & _T_549; // @[el2_lib.scala 198:22] - wire _T_653 = _T_652 & _T_556; // @[el2_lib.scala 198:22] - wire _T_654 = _T_653 & _T_563; // @[el2_lib.scala 198:22] - wire _T_655 = _T_654 & _T_570; // @[el2_lib.scala 198:22] - wire _T_656 = _T_655 & _T_577; // @[el2_lib.scala 198:22] - wire _T_657 = _T_656 & _T_584; // @[el2_lib.scala 198:22] - wire _T_658 = _T_657 & _T_591; // @[el2_lib.scala 198:22] - wire _T_659 = _T_658 & _T_598; // @[el2_lib.scala 198:22] - wire _T_660 = _T_659 & _T_605; // @[el2_lib.scala 198:22] - wire _T_661 = _T_660 & _T_612; // @[el2_lib.scala 198:22] - wire _T_662 = _T_661 & _T_619; // @[el2_lib.scala 198:22] - wire _T_663 = _T_662 & _T_626; // @[el2_lib.scala 198:22] - wire _T_664 = _T_663 & _T_633; // @[el2_lib.scala 198:22] - wire _T_665 = _T_407 & _T_664; // @[el2_lsu_trigger.scala 16:109] - wire _T_666 = io_trigger_pkt_any_2_execute & io_trigger_pkt_any_2_m; // @[el2_lsu_trigger.scala 16:83] - wire _T_669 = &io_trigger_pkt_any_2_tdata2; // @[el2_lib.scala 194:45] - wire _T_670 = ~_T_669; // @[el2_lib.scala 194:39] - wire _T_671 = io_trigger_pkt_any_2_match_ & _T_670; // @[el2_lib.scala 194:37] - wire _T_674 = io_trigger_pkt_any_2_tdata2[0] == dec_i0_match_data_2[0]; // @[el2_lib.scala 195:52] - wire _T_675 = _T_671 | _T_674; // @[el2_lib.scala 195:41] - wire _T_677 = &io_trigger_pkt_any_2_tdata2[0]; // @[el2_lib.scala 197:38] - wire _T_678 = _T_677 & _T_671; // @[el2_lib.scala 197:43] - wire _T_681 = io_trigger_pkt_any_2_tdata2[1] == dec_i0_match_data_2[1]; // @[el2_lib.scala 197:80] - wire _T_682 = _T_678 | _T_681; // @[el2_lib.scala 197:25] - wire _T_684 = &io_trigger_pkt_any_2_tdata2[1:0]; // @[el2_lib.scala 197:38] - wire _T_685 = _T_684 & _T_671; // @[el2_lib.scala 197:43] - wire _T_688 = io_trigger_pkt_any_2_tdata2[2] == dec_i0_match_data_2[2]; // @[el2_lib.scala 197:80] - wire _T_689 = _T_685 | _T_688; // @[el2_lib.scala 197:25] - wire _T_691 = &io_trigger_pkt_any_2_tdata2[2:0]; // @[el2_lib.scala 197:38] - wire _T_692 = _T_691 & _T_671; // @[el2_lib.scala 197:43] - wire _T_695 = io_trigger_pkt_any_2_tdata2[3] == dec_i0_match_data_2[3]; // @[el2_lib.scala 197:80] - wire _T_696 = _T_692 | _T_695; // @[el2_lib.scala 197:25] - wire _T_698 = &io_trigger_pkt_any_2_tdata2[3:0]; // @[el2_lib.scala 197:38] - wire _T_699 = _T_698 & _T_671; // @[el2_lib.scala 197:43] - wire _T_702 = io_trigger_pkt_any_2_tdata2[4] == dec_i0_match_data_2[4]; // @[el2_lib.scala 197:80] - wire _T_703 = _T_699 | _T_702; // @[el2_lib.scala 197:25] - wire _T_705 = &io_trigger_pkt_any_2_tdata2[4:0]; // @[el2_lib.scala 197:38] - wire _T_706 = _T_705 & _T_671; // @[el2_lib.scala 197:43] - wire _T_709 = io_trigger_pkt_any_2_tdata2[5] == dec_i0_match_data_2[5]; // @[el2_lib.scala 197:80] - wire _T_710 = _T_706 | _T_709; // @[el2_lib.scala 197:25] - wire _T_712 = &io_trigger_pkt_any_2_tdata2[5:0]; // @[el2_lib.scala 197:38] - wire _T_713 = _T_712 & _T_671; // @[el2_lib.scala 197:43] - wire _T_716 = io_trigger_pkt_any_2_tdata2[6] == dec_i0_match_data_2[6]; // @[el2_lib.scala 197:80] - wire _T_717 = _T_713 | _T_716; // @[el2_lib.scala 197:25] - wire _T_719 = &io_trigger_pkt_any_2_tdata2[6:0]; // @[el2_lib.scala 197:38] - wire _T_720 = _T_719 & _T_671; // @[el2_lib.scala 197:43] - wire _T_723 = io_trigger_pkt_any_2_tdata2[7] == dec_i0_match_data_2[7]; // @[el2_lib.scala 197:80] - wire _T_724 = _T_720 | _T_723; // @[el2_lib.scala 197:25] - wire _T_726 = &io_trigger_pkt_any_2_tdata2[7:0]; // @[el2_lib.scala 197:38] - wire _T_727 = _T_726 & _T_671; // @[el2_lib.scala 197:43] - wire _T_730 = io_trigger_pkt_any_2_tdata2[8] == dec_i0_match_data_2[8]; // @[el2_lib.scala 197:80] - wire _T_731 = _T_727 | _T_730; // @[el2_lib.scala 197:25] - wire _T_733 = &io_trigger_pkt_any_2_tdata2[8:0]; // @[el2_lib.scala 197:38] - wire _T_734 = _T_733 & _T_671; // @[el2_lib.scala 197:43] - wire _T_737 = io_trigger_pkt_any_2_tdata2[9] == dec_i0_match_data_2[9]; // @[el2_lib.scala 197:80] - wire _T_738 = _T_734 | _T_737; // @[el2_lib.scala 197:25] - wire _T_740 = &io_trigger_pkt_any_2_tdata2[9:0]; // @[el2_lib.scala 197:38] - wire _T_741 = _T_740 & _T_671; // @[el2_lib.scala 197:43] - wire _T_744 = io_trigger_pkt_any_2_tdata2[10] == dec_i0_match_data_2[10]; // @[el2_lib.scala 197:80] - wire _T_745 = _T_741 | _T_744; // @[el2_lib.scala 197:25] - wire _T_747 = &io_trigger_pkt_any_2_tdata2[10:0]; // @[el2_lib.scala 197:38] - wire _T_748 = _T_747 & _T_671; // @[el2_lib.scala 197:43] - wire _T_751 = io_trigger_pkt_any_2_tdata2[11] == dec_i0_match_data_2[11]; // @[el2_lib.scala 197:80] - wire _T_752 = _T_748 | _T_751; // @[el2_lib.scala 197:25] - wire _T_754 = &io_trigger_pkt_any_2_tdata2[11:0]; // @[el2_lib.scala 197:38] - wire _T_755 = _T_754 & _T_671; // @[el2_lib.scala 197:43] - wire _T_758 = io_trigger_pkt_any_2_tdata2[12] == dec_i0_match_data_2[12]; // @[el2_lib.scala 197:80] - wire _T_759 = _T_755 | _T_758; // @[el2_lib.scala 197:25] - wire _T_761 = &io_trigger_pkt_any_2_tdata2[12:0]; // @[el2_lib.scala 197:38] - wire _T_762 = _T_761 & _T_671; // @[el2_lib.scala 197:43] - wire _T_765 = io_trigger_pkt_any_2_tdata2[13] == dec_i0_match_data_2[13]; // @[el2_lib.scala 197:80] - wire _T_766 = _T_762 | _T_765; // @[el2_lib.scala 197:25] - wire _T_768 = &io_trigger_pkt_any_2_tdata2[13:0]; // @[el2_lib.scala 197:38] - wire _T_769 = _T_768 & _T_671; // @[el2_lib.scala 197:43] - wire _T_772 = io_trigger_pkt_any_2_tdata2[14] == dec_i0_match_data_2[14]; // @[el2_lib.scala 197:80] - wire _T_773 = _T_769 | _T_772; // @[el2_lib.scala 197:25] - wire _T_775 = &io_trigger_pkt_any_2_tdata2[14:0]; // @[el2_lib.scala 197:38] - wire _T_776 = _T_775 & _T_671; // @[el2_lib.scala 197:43] - wire _T_779 = io_trigger_pkt_any_2_tdata2[15] == dec_i0_match_data_2[15]; // @[el2_lib.scala 197:80] - wire _T_780 = _T_776 | _T_779; // @[el2_lib.scala 197:25] - wire _T_782 = &io_trigger_pkt_any_2_tdata2[15:0]; // @[el2_lib.scala 197:38] - wire _T_783 = _T_782 & _T_671; // @[el2_lib.scala 197:43] - wire _T_786 = io_trigger_pkt_any_2_tdata2[16] == dec_i0_match_data_2[16]; // @[el2_lib.scala 197:80] - wire _T_787 = _T_783 | _T_786; // @[el2_lib.scala 197:25] - wire _T_789 = &io_trigger_pkt_any_2_tdata2[16:0]; // @[el2_lib.scala 197:38] - wire _T_790 = _T_789 & _T_671; // @[el2_lib.scala 197:43] - wire _T_793 = io_trigger_pkt_any_2_tdata2[17] == dec_i0_match_data_2[17]; // @[el2_lib.scala 197:80] - wire _T_794 = _T_790 | _T_793; // @[el2_lib.scala 197:25] - wire _T_796 = &io_trigger_pkt_any_2_tdata2[17:0]; // @[el2_lib.scala 197:38] - wire _T_797 = _T_796 & _T_671; // @[el2_lib.scala 197:43] - wire _T_800 = io_trigger_pkt_any_2_tdata2[18] == dec_i0_match_data_2[18]; // @[el2_lib.scala 197:80] - wire _T_801 = _T_797 | _T_800; // @[el2_lib.scala 197:25] - wire _T_803 = &io_trigger_pkt_any_2_tdata2[18:0]; // @[el2_lib.scala 197:38] - wire _T_804 = _T_803 & _T_671; // @[el2_lib.scala 197:43] - wire _T_807 = io_trigger_pkt_any_2_tdata2[19] == dec_i0_match_data_2[19]; // @[el2_lib.scala 197:80] - wire _T_808 = _T_804 | _T_807; // @[el2_lib.scala 197:25] - wire _T_810 = &io_trigger_pkt_any_2_tdata2[19:0]; // @[el2_lib.scala 197:38] - wire _T_811 = _T_810 & _T_671; // @[el2_lib.scala 197:43] - wire _T_814 = io_trigger_pkt_any_2_tdata2[20] == dec_i0_match_data_2[20]; // @[el2_lib.scala 197:80] - wire _T_815 = _T_811 | _T_814; // @[el2_lib.scala 197:25] - wire _T_817 = &io_trigger_pkt_any_2_tdata2[20:0]; // @[el2_lib.scala 197:38] - wire _T_818 = _T_817 & _T_671; // @[el2_lib.scala 197:43] - wire _T_821 = io_trigger_pkt_any_2_tdata2[21] == dec_i0_match_data_2[21]; // @[el2_lib.scala 197:80] - wire _T_822 = _T_818 | _T_821; // @[el2_lib.scala 197:25] - wire _T_824 = &io_trigger_pkt_any_2_tdata2[21:0]; // @[el2_lib.scala 197:38] - wire _T_825 = _T_824 & _T_671; // @[el2_lib.scala 197:43] - wire _T_828 = io_trigger_pkt_any_2_tdata2[22] == dec_i0_match_data_2[22]; // @[el2_lib.scala 197:80] - wire _T_829 = _T_825 | _T_828; // @[el2_lib.scala 197:25] - wire _T_831 = &io_trigger_pkt_any_2_tdata2[22:0]; // @[el2_lib.scala 197:38] - wire _T_832 = _T_831 & _T_671; // @[el2_lib.scala 197:43] - wire _T_835 = io_trigger_pkt_any_2_tdata2[23] == dec_i0_match_data_2[23]; // @[el2_lib.scala 197:80] - wire _T_836 = _T_832 | _T_835; // @[el2_lib.scala 197:25] - wire _T_838 = &io_trigger_pkt_any_2_tdata2[23:0]; // @[el2_lib.scala 197:38] - wire _T_839 = _T_838 & _T_671; // @[el2_lib.scala 197:43] - wire _T_842 = io_trigger_pkt_any_2_tdata2[24] == dec_i0_match_data_2[24]; // @[el2_lib.scala 197:80] - wire _T_843 = _T_839 | _T_842; // @[el2_lib.scala 197:25] - wire _T_845 = &io_trigger_pkt_any_2_tdata2[24:0]; // @[el2_lib.scala 197:38] - wire _T_846 = _T_845 & _T_671; // @[el2_lib.scala 197:43] - wire _T_849 = io_trigger_pkt_any_2_tdata2[25] == dec_i0_match_data_2[25]; // @[el2_lib.scala 197:80] - wire _T_850 = _T_846 | _T_849; // @[el2_lib.scala 197:25] - wire _T_852 = &io_trigger_pkt_any_2_tdata2[25:0]; // @[el2_lib.scala 197:38] - wire _T_853 = _T_852 & _T_671; // @[el2_lib.scala 197:43] - wire _T_856 = io_trigger_pkt_any_2_tdata2[26] == dec_i0_match_data_2[26]; // @[el2_lib.scala 197:80] - wire _T_857 = _T_853 | _T_856; // @[el2_lib.scala 197:25] - wire _T_859 = &io_trigger_pkt_any_2_tdata2[26:0]; // @[el2_lib.scala 197:38] - wire _T_860 = _T_859 & _T_671; // @[el2_lib.scala 197:43] - wire _T_863 = io_trigger_pkt_any_2_tdata2[27] == dec_i0_match_data_2[27]; // @[el2_lib.scala 197:80] - wire _T_864 = _T_860 | _T_863; // @[el2_lib.scala 197:25] - wire _T_866 = &io_trigger_pkt_any_2_tdata2[27:0]; // @[el2_lib.scala 197:38] - wire _T_867 = _T_866 & _T_671; // @[el2_lib.scala 197:43] - wire _T_870 = io_trigger_pkt_any_2_tdata2[28] == dec_i0_match_data_2[28]; // @[el2_lib.scala 197:80] - wire _T_871 = _T_867 | _T_870; // @[el2_lib.scala 197:25] - wire _T_873 = &io_trigger_pkt_any_2_tdata2[28:0]; // @[el2_lib.scala 197:38] - wire _T_874 = _T_873 & _T_671; // @[el2_lib.scala 197:43] - wire _T_877 = io_trigger_pkt_any_2_tdata2[29] == dec_i0_match_data_2[29]; // @[el2_lib.scala 197:80] - wire _T_878 = _T_874 | _T_877; // @[el2_lib.scala 197:25] - wire _T_880 = &io_trigger_pkt_any_2_tdata2[29:0]; // @[el2_lib.scala 197:38] - wire _T_881 = _T_880 & _T_671; // @[el2_lib.scala 197:43] - wire _T_884 = io_trigger_pkt_any_2_tdata2[30] == dec_i0_match_data_2[30]; // @[el2_lib.scala 197:80] - wire _T_885 = _T_881 | _T_884; // @[el2_lib.scala 197:25] - wire _T_887 = &io_trigger_pkt_any_2_tdata2[30:0]; // @[el2_lib.scala 197:38] - wire _T_888 = _T_887 & _T_671; // @[el2_lib.scala 197:43] - wire _T_891 = io_trigger_pkt_any_2_tdata2[31] == dec_i0_match_data_2[31]; // @[el2_lib.scala 197:80] - wire _T_892 = _T_888 | _T_891; // @[el2_lib.scala 197:25] - wire _T_893 = _T_675 & _T_682; // @[el2_lib.scala 198:22] - wire _T_894 = _T_893 & _T_689; // @[el2_lib.scala 198:22] - wire _T_895 = _T_894 & _T_696; // @[el2_lib.scala 198:22] - wire _T_896 = _T_895 & _T_703; // @[el2_lib.scala 198:22] - wire _T_897 = _T_896 & _T_710; // @[el2_lib.scala 198:22] - wire _T_898 = _T_897 & _T_717; // @[el2_lib.scala 198:22] - wire _T_899 = _T_898 & _T_724; // @[el2_lib.scala 198:22] - wire _T_900 = _T_899 & _T_731; // @[el2_lib.scala 198:22] - wire _T_901 = _T_900 & _T_738; // @[el2_lib.scala 198:22] - wire _T_902 = _T_901 & _T_745; // @[el2_lib.scala 198:22] - wire _T_903 = _T_902 & _T_752; // @[el2_lib.scala 198:22] - wire _T_904 = _T_903 & _T_759; // @[el2_lib.scala 198:22] - wire _T_905 = _T_904 & _T_766; // @[el2_lib.scala 198:22] - wire _T_906 = _T_905 & _T_773; // @[el2_lib.scala 198:22] - wire _T_907 = _T_906 & _T_780; // @[el2_lib.scala 198:22] - wire _T_908 = _T_907 & _T_787; // @[el2_lib.scala 198:22] - wire _T_909 = _T_908 & _T_794; // @[el2_lib.scala 198:22] - wire _T_910 = _T_909 & _T_801; // @[el2_lib.scala 198:22] - wire _T_911 = _T_910 & _T_808; // @[el2_lib.scala 198:22] - wire _T_912 = _T_911 & _T_815; // @[el2_lib.scala 198:22] - wire _T_913 = _T_912 & _T_822; // @[el2_lib.scala 198:22] - wire _T_914 = _T_913 & _T_829; // @[el2_lib.scala 198:22] - wire _T_915 = _T_914 & _T_836; // @[el2_lib.scala 198:22] - wire _T_916 = _T_915 & _T_843; // @[el2_lib.scala 198:22] - wire _T_917 = _T_916 & _T_850; // @[el2_lib.scala 198:22] - wire _T_918 = _T_917 & _T_857; // @[el2_lib.scala 198:22] - wire _T_919 = _T_918 & _T_864; // @[el2_lib.scala 198:22] - wire _T_920 = _T_919 & _T_871; // @[el2_lib.scala 198:22] - wire _T_921 = _T_920 & _T_878; // @[el2_lib.scala 198:22] - wire _T_922 = _T_921 & _T_885; // @[el2_lib.scala 198:22] - wire _T_923 = _T_922 & _T_892; // @[el2_lib.scala 198:22] - wire _T_924 = _T_666 & _T_923; // @[el2_lsu_trigger.scala 16:109] - wire _T_925 = io_trigger_pkt_any_3_execute & io_trigger_pkt_any_3_m; // @[el2_lsu_trigger.scala 16:83] - wire _T_928 = &io_trigger_pkt_any_3_tdata2; // @[el2_lib.scala 194:45] - wire _T_929 = ~_T_928; // @[el2_lib.scala 194:39] - wire _T_930 = io_trigger_pkt_any_3_match_ & _T_929; // @[el2_lib.scala 194:37] - wire _T_933 = io_trigger_pkt_any_3_tdata2[0] == dec_i0_match_data_3[0]; // @[el2_lib.scala 195:52] - wire _T_934 = _T_930 | _T_933; // @[el2_lib.scala 195:41] - wire _T_936 = &io_trigger_pkt_any_3_tdata2[0]; // @[el2_lib.scala 197:38] - wire _T_937 = _T_936 & _T_930; // @[el2_lib.scala 197:43] - wire _T_940 = io_trigger_pkt_any_3_tdata2[1] == dec_i0_match_data_3[1]; // @[el2_lib.scala 197:80] - wire _T_941 = _T_937 | _T_940; // @[el2_lib.scala 197:25] - wire _T_943 = &io_trigger_pkt_any_3_tdata2[1:0]; // @[el2_lib.scala 197:38] - wire _T_944 = _T_943 & _T_930; // @[el2_lib.scala 197:43] - wire _T_947 = io_trigger_pkt_any_3_tdata2[2] == dec_i0_match_data_3[2]; // @[el2_lib.scala 197:80] - wire _T_948 = _T_944 | _T_947; // @[el2_lib.scala 197:25] - wire _T_950 = &io_trigger_pkt_any_3_tdata2[2:0]; // @[el2_lib.scala 197:38] - wire _T_951 = _T_950 & _T_930; // @[el2_lib.scala 197:43] - wire _T_954 = io_trigger_pkt_any_3_tdata2[3] == dec_i0_match_data_3[3]; // @[el2_lib.scala 197:80] - wire _T_955 = _T_951 | _T_954; // @[el2_lib.scala 197:25] - wire _T_957 = &io_trigger_pkt_any_3_tdata2[3:0]; // @[el2_lib.scala 197:38] - wire _T_958 = _T_957 & _T_930; // @[el2_lib.scala 197:43] - wire _T_961 = io_trigger_pkt_any_3_tdata2[4] == dec_i0_match_data_3[4]; // @[el2_lib.scala 197:80] - wire _T_962 = _T_958 | _T_961; // @[el2_lib.scala 197:25] - wire _T_964 = &io_trigger_pkt_any_3_tdata2[4:0]; // @[el2_lib.scala 197:38] - wire _T_965 = _T_964 & _T_930; // @[el2_lib.scala 197:43] - wire _T_968 = io_trigger_pkt_any_3_tdata2[5] == dec_i0_match_data_3[5]; // @[el2_lib.scala 197:80] - wire _T_969 = _T_965 | _T_968; // @[el2_lib.scala 197:25] - wire _T_971 = &io_trigger_pkt_any_3_tdata2[5:0]; // @[el2_lib.scala 197:38] - wire _T_972 = _T_971 & _T_930; // @[el2_lib.scala 197:43] - wire _T_975 = io_trigger_pkt_any_3_tdata2[6] == dec_i0_match_data_3[6]; // @[el2_lib.scala 197:80] - wire _T_976 = _T_972 | _T_975; // @[el2_lib.scala 197:25] - wire _T_978 = &io_trigger_pkt_any_3_tdata2[6:0]; // @[el2_lib.scala 197:38] - wire _T_979 = _T_978 & _T_930; // @[el2_lib.scala 197:43] - wire _T_982 = io_trigger_pkt_any_3_tdata2[7] == dec_i0_match_data_3[7]; // @[el2_lib.scala 197:80] - wire _T_983 = _T_979 | _T_982; // @[el2_lib.scala 197:25] - wire _T_985 = &io_trigger_pkt_any_3_tdata2[7:0]; // @[el2_lib.scala 197:38] - wire _T_986 = _T_985 & _T_930; // @[el2_lib.scala 197:43] - wire _T_989 = io_trigger_pkt_any_3_tdata2[8] == dec_i0_match_data_3[8]; // @[el2_lib.scala 197:80] - wire _T_990 = _T_986 | _T_989; // @[el2_lib.scala 197:25] - wire _T_992 = &io_trigger_pkt_any_3_tdata2[8:0]; // @[el2_lib.scala 197:38] - wire _T_993 = _T_992 & _T_930; // @[el2_lib.scala 197:43] - wire _T_996 = io_trigger_pkt_any_3_tdata2[9] == dec_i0_match_data_3[9]; // @[el2_lib.scala 197:80] - wire _T_997 = _T_993 | _T_996; // @[el2_lib.scala 197:25] - wire _T_999 = &io_trigger_pkt_any_3_tdata2[9:0]; // @[el2_lib.scala 197:38] - wire _T_1000 = _T_999 & _T_930; // @[el2_lib.scala 197:43] - wire _T_1003 = io_trigger_pkt_any_3_tdata2[10] == dec_i0_match_data_3[10]; // @[el2_lib.scala 197:80] - wire _T_1004 = _T_1000 | _T_1003; // @[el2_lib.scala 197:25] - wire _T_1006 = &io_trigger_pkt_any_3_tdata2[10:0]; // @[el2_lib.scala 197:38] - wire _T_1007 = _T_1006 & _T_930; // @[el2_lib.scala 197:43] - wire _T_1010 = io_trigger_pkt_any_3_tdata2[11] == dec_i0_match_data_3[11]; // @[el2_lib.scala 197:80] - wire _T_1011 = _T_1007 | _T_1010; // @[el2_lib.scala 197:25] - wire _T_1013 = &io_trigger_pkt_any_3_tdata2[11:0]; // @[el2_lib.scala 197:38] - wire _T_1014 = _T_1013 & _T_930; // @[el2_lib.scala 197:43] - wire _T_1017 = io_trigger_pkt_any_3_tdata2[12] == dec_i0_match_data_3[12]; // @[el2_lib.scala 197:80] - wire _T_1018 = _T_1014 | _T_1017; // @[el2_lib.scala 197:25] - wire _T_1020 = &io_trigger_pkt_any_3_tdata2[12:0]; // @[el2_lib.scala 197:38] - wire _T_1021 = _T_1020 & _T_930; // @[el2_lib.scala 197:43] - wire _T_1024 = io_trigger_pkt_any_3_tdata2[13] == dec_i0_match_data_3[13]; // @[el2_lib.scala 197:80] - wire _T_1025 = _T_1021 | _T_1024; // @[el2_lib.scala 197:25] - wire _T_1027 = &io_trigger_pkt_any_3_tdata2[13:0]; // @[el2_lib.scala 197:38] - wire _T_1028 = _T_1027 & _T_930; // @[el2_lib.scala 197:43] - wire _T_1031 = io_trigger_pkt_any_3_tdata2[14] == dec_i0_match_data_3[14]; // @[el2_lib.scala 197:80] - wire _T_1032 = _T_1028 | _T_1031; // @[el2_lib.scala 197:25] - wire _T_1034 = &io_trigger_pkt_any_3_tdata2[14:0]; // @[el2_lib.scala 197:38] - wire _T_1035 = _T_1034 & _T_930; // @[el2_lib.scala 197:43] - wire _T_1038 = io_trigger_pkt_any_3_tdata2[15] == dec_i0_match_data_3[15]; // @[el2_lib.scala 197:80] - wire _T_1039 = _T_1035 | _T_1038; // @[el2_lib.scala 197:25] - wire _T_1041 = &io_trigger_pkt_any_3_tdata2[15:0]; // @[el2_lib.scala 197:38] - wire _T_1042 = _T_1041 & _T_930; // @[el2_lib.scala 197:43] - wire _T_1045 = io_trigger_pkt_any_3_tdata2[16] == dec_i0_match_data_3[16]; // @[el2_lib.scala 197:80] - wire _T_1046 = _T_1042 | _T_1045; // @[el2_lib.scala 197:25] - wire _T_1048 = &io_trigger_pkt_any_3_tdata2[16:0]; // @[el2_lib.scala 197:38] - wire _T_1049 = _T_1048 & _T_930; // @[el2_lib.scala 197:43] - wire _T_1052 = io_trigger_pkt_any_3_tdata2[17] == dec_i0_match_data_3[17]; // @[el2_lib.scala 197:80] - wire _T_1053 = _T_1049 | _T_1052; // @[el2_lib.scala 197:25] - wire _T_1055 = &io_trigger_pkt_any_3_tdata2[17:0]; // @[el2_lib.scala 197:38] - wire _T_1056 = _T_1055 & _T_930; // @[el2_lib.scala 197:43] - wire _T_1059 = io_trigger_pkt_any_3_tdata2[18] == dec_i0_match_data_3[18]; // @[el2_lib.scala 197:80] - wire _T_1060 = _T_1056 | _T_1059; // @[el2_lib.scala 197:25] - wire _T_1062 = &io_trigger_pkt_any_3_tdata2[18:0]; // @[el2_lib.scala 197:38] - wire _T_1063 = _T_1062 & _T_930; // @[el2_lib.scala 197:43] - wire _T_1066 = io_trigger_pkt_any_3_tdata2[19] == dec_i0_match_data_3[19]; // @[el2_lib.scala 197:80] - wire _T_1067 = _T_1063 | _T_1066; // @[el2_lib.scala 197:25] - wire _T_1069 = &io_trigger_pkt_any_3_tdata2[19:0]; // @[el2_lib.scala 197:38] - wire _T_1070 = _T_1069 & _T_930; // @[el2_lib.scala 197:43] - wire _T_1073 = io_trigger_pkt_any_3_tdata2[20] == dec_i0_match_data_3[20]; // @[el2_lib.scala 197:80] - wire _T_1074 = _T_1070 | _T_1073; // @[el2_lib.scala 197:25] - wire _T_1076 = &io_trigger_pkt_any_3_tdata2[20:0]; // @[el2_lib.scala 197:38] - wire _T_1077 = _T_1076 & _T_930; // @[el2_lib.scala 197:43] - wire _T_1080 = io_trigger_pkt_any_3_tdata2[21] == dec_i0_match_data_3[21]; // @[el2_lib.scala 197:80] - wire _T_1081 = _T_1077 | _T_1080; // @[el2_lib.scala 197:25] - wire _T_1083 = &io_trigger_pkt_any_3_tdata2[21:0]; // @[el2_lib.scala 197:38] - wire _T_1084 = _T_1083 & _T_930; // @[el2_lib.scala 197:43] - wire _T_1087 = io_trigger_pkt_any_3_tdata2[22] == dec_i0_match_data_3[22]; // @[el2_lib.scala 197:80] - wire _T_1088 = _T_1084 | _T_1087; // @[el2_lib.scala 197:25] - wire _T_1090 = &io_trigger_pkt_any_3_tdata2[22:0]; // @[el2_lib.scala 197:38] - wire _T_1091 = _T_1090 & _T_930; // @[el2_lib.scala 197:43] - wire _T_1094 = io_trigger_pkt_any_3_tdata2[23] == dec_i0_match_data_3[23]; // @[el2_lib.scala 197:80] - wire _T_1095 = _T_1091 | _T_1094; // @[el2_lib.scala 197:25] - wire _T_1097 = &io_trigger_pkt_any_3_tdata2[23:0]; // @[el2_lib.scala 197:38] - wire _T_1098 = _T_1097 & _T_930; // @[el2_lib.scala 197:43] - wire _T_1101 = io_trigger_pkt_any_3_tdata2[24] == dec_i0_match_data_3[24]; // @[el2_lib.scala 197:80] - wire _T_1102 = _T_1098 | _T_1101; // @[el2_lib.scala 197:25] - wire _T_1104 = &io_trigger_pkt_any_3_tdata2[24:0]; // @[el2_lib.scala 197:38] - wire _T_1105 = _T_1104 & _T_930; // @[el2_lib.scala 197:43] - wire _T_1108 = io_trigger_pkt_any_3_tdata2[25] == dec_i0_match_data_3[25]; // @[el2_lib.scala 197:80] - wire _T_1109 = _T_1105 | _T_1108; // @[el2_lib.scala 197:25] - wire _T_1111 = &io_trigger_pkt_any_3_tdata2[25:0]; // @[el2_lib.scala 197:38] - wire _T_1112 = _T_1111 & _T_930; // @[el2_lib.scala 197:43] - wire _T_1115 = io_trigger_pkt_any_3_tdata2[26] == dec_i0_match_data_3[26]; // @[el2_lib.scala 197:80] - wire _T_1116 = _T_1112 | _T_1115; // @[el2_lib.scala 197:25] - wire _T_1118 = &io_trigger_pkt_any_3_tdata2[26:0]; // @[el2_lib.scala 197:38] - wire _T_1119 = _T_1118 & _T_930; // @[el2_lib.scala 197:43] - wire _T_1122 = io_trigger_pkt_any_3_tdata2[27] == dec_i0_match_data_3[27]; // @[el2_lib.scala 197:80] - wire _T_1123 = _T_1119 | _T_1122; // @[el2_lib.scala 197:25] - wire _T_1125 = &io_trigger_pkt_any_3_tdata2[27:0]; // @[el2_lib.scala 197:38] - wire _T_1126 = _T_1125 & _T_930; // @[el2_lib.scala 197:43] - wire _T_1129 = io_trigger_pkt_any_3_tdata2[28] == dec_i0_match_data_3[28]; // @[el2_lib.scala 197:80] - wire _T_1130 = _T_1126 | _T_1129; // @[el2_lib.scala 197:25] - wire _T_1132 = &io_trigger_pkt_any_3_tdata2[28:0]; // @[el2_lib.scala 197:38] - wire _T_1133 = _T_1132 & _T_930; // @[el2_lib.scala 197:43] - wire _T_1136 = io_trigger_pkt_any_3_tdata2[29] == dec_i0_match_data_3[29]; // @[el2_lib.scala 197:80] - wire _T_1137 = _T_1133 | _T_1136; // @[el2_lib.scala 197:25] - wire _T_1139 = &io_trigger_pkt_any_3_tdata2[29:0]; // @[el2_lib.scala 197:38] - wire _T_1140 = _T_1139 & _T_930; // @[el2_lib.scala 197:43] - wire _T_1143 = io_trigger_pkt_any_3_tdata2[30] == dec_i0_match_data_3[30]; // @[el2_lib.scala 197:80] - wire _T_1144 = _T_1140 | _T_1143; // @[el2_lib.scala 197:25] - wire _T_1146 = &io_trigger_pkt_any_3_tdata2[30:0]; // @[el2_lib.scala 197:38] - wire _T_1147 = _T_1146 & _T_930; // @[el2_lib.scala 197:43] - wire _T_1150 = io_trigger_pkt_any_3_tdata2[31] == dec_i0_match_data_3[31]; // @[el2_lib.scala 197:80] - wire _T_1151 = _T_1147 | _T_1150; // @[el2_lib.scala 197:25] - wire _T_1152 = _T_934 & _T_941; // @[el2_lib.scala 198:22] - wire _T_1153 = _T_1152 & _T_948; // @[el2_lib.scala 198:22] - wire _T_1154 = _T_1153 & _T_955; // @[el2_lib.scala 198:22] - wire _T_1155 = _T_1154 & _T_962; // @[el2_lib.scala 198:22] - wire _T_1156 = _T_1155 & _T_969; // @[el2_lib.scala 198:22] - wire _T_1157 = _T_1156 & _T_976; // @[el2_lib.scala 198:22] - wire _T_1158 = _T_1157 & _T_983; // @[el2_lib.scala 198:22] - wire _T_1159 = _T_1158 & _T_990; // @[el2_lib.scala 198:22] - wire _T_1160 = _T_1159 & _T_997; // @[el2_lib.scala 198:22] - wire _T_1161 = _T_1160 & _T_1004; // @[el2_lib.scala 198:22] - wire _T_1162 = _T_1161 & _T_1011; // @[el2_lib.scala 198:22] - wire _T_1163 = _T_1162 & _T_1018; // @[el2_lib.scala 198:22] - wire _T_1164 = _T_1163 & _T_1025; // @[el2_lib.scala 198:22] - wire _T_1165 = _T_1164 & _T_1032; // @[el2_lib.scala 198:22] - wire _T_1166 = _T_1165 & _T_1039; // @[el2_lib.scala 198:22] - wire _T_1167 = _T_1166 & _T_1046; // @[el2_lib.scala 198:22] - wire _T_1168 = _T_1167 & _T_1053; // @[el2_lib.scala 198:22] - wire _T_1169 = _T_1168 & _T_1060; // @[el2_lib.scala 198:22] - wire _T_1170 = _T_1169 & _T_1067; // @[el2_lib.scala 198:22] - wire _T_1171 = _T_1170 & _T_1074; // @[el2_lib.scala 198:22] - wire _T_1172 = _T_1171 & _T_1081; // @[el2_lib.scala 198:22] - wire _T_1173 = _T_1172 & _T_1088; // @[el2_lib.scala 198:22] - wire _T_1174 = _T_1173 & _T_1095; // @[el2_lib.scala 198:22] - wire _T_1175 = _T_1174 & _T_1102; // @[el2_lib.scala 198:22] - wire _T_1176 = _T_1175 & _T_1109; // @[el2_lib.scala 198:22] - wire _T_1177 = _T_1176 & _T_1116; // @[el2_lib.scala 198:22] - wire _T_1178 = _T_1177 & _T_1123; // @[el2_lib.scala 198:22] - wire _T_1179 = _T_1178 & _T_1130; // @[el2_lib.scala 198:22] - wire _T_1180 = _T_1179 & _T_1137; // @[el2_lib.scala 198:22] - wire _T_1181 = _T_1180 & _T_1144; // @[el2_lib.scala 198:22] - wire _T_1182 = _T_1181 & _T_1151; // @[el2_lib.scala 198:22] - wire _T_1183 = _T_925 & _T_1182; // @[el2_lsu_trigger.scala 16:109] - wire [2:0] _T_1185 = {_T_1183,_T_924,_T_665}; // @[Cat.scala 29:58] - assign io_dec_i0_trigger_match_d = {_T_1185,_T_406}; // @[el2_lsu_trigger.scala 16:29] + wire [31:0] dec_i0_match_data_3 = _T_144 & _T_146; // @[el2_dec_trigger.scala 14:127] + wire _T_148 = io_trigger_pkt_any_0_execute & io_trigger_pkt_any_0_m; // @[el2_dec_trigger.scala 15:83] + wire _T_151 = &io_trigger_pkt_any_0_tdata2; // @[el2_lib.scala 241:45] + wire _T_152 = ~_T_151; // @[el2_lib.scala 241:39] + wire _T_153 = io_trigger_pkt_any_0_match_pkt & _T_152; // @[el2_lib.scala 241:37] + wire _T_156 = io_trigger_pkt_any_0_tdata2[0] == dec_i0_match_data_0[0]; // @[el2_lib.scala 242:52] + wire _T_157 = _T_153 | _T_156; // @[el2_lib.scala 242:41] + wire _T_159 = &io_trigger_pkt_any_0_tdata2[0]; // @[el2_lib.scala 244:36] + wire _T_160 = _T_159 & _T_153; // @[el2_lib.scala 244:41] + wire _T_163 = io_trigger_pkt_any_0_tdata2[1] == dec_i0_match_data_0[1]; // @[el2_lib.scala 244:78] + wire _T_164 = _T_160 | _T_163; // @[el2_lib.scala 244:23] + wire _T_166 = &io_trigger_pkt_any_0_tdata2[1:0]; // @[el2_lib.scala 244:36] + wire _T_167 = _T_166 & _T_153; // @[el2_lib.scala 244:41] + wire _T_170 = io_trigger_pkt_any_0_tdata2[2] == dec_i0_match_data_0[2]; // @[el2_lib.scala 244:78] + wire _T_171 = _T_167 | _T_170; // @[el2_lib.scala 244:23] + wire _T_173 = &io_trigger_pkt_any_0_tdata2[2:0]; // @[el2_lib.scala 244:36] + wire _T_174 = _T_173 & _T_153; // @[el2_lib.scala 244:41] + wire _T_177 = io_trigger_pkt_any_0_tdata2[3] == dec_i0_match_data_0[3]; // @[el2_lib.scala 244:78] + wire _T_178 = _T_174 | _T_177; // @[el2_lib.scala 244:23] + wire _T_180 = &io_trigger_pkt_any_0_tdata2[3:0]; // @[el2_lib.scala 244:36] + wire _T_181 = _T_180 & _T_153; // @[el2_lib.scala 244:41] + wire _T_184 = io_trigger_pkt_any_0_tdata2[4] == dec_i0_match_data_0[4]; // @[el2_lib.scala 244:78] + wire _T_185 = _T_181 | _T_184; // @[el2_lib.scala 244:23] + wire _T_187 = &io_trigger_pkt_any_0_tdata2[4:0]; // @[el2_lib.scala 244:36] + wire _T_188 = _T_187 & _T_153; // @[el2_lib.scala 244:41] + wire _T_191 = io_trigger_pkt_any_0_tdata2[5] == dec_i0_match_data_0[5]; // @[el2_lib.scala 244:78] + wire _T_192 = _T_188 | _T_191; // @[el2_lib.scala 244:23] + wire _T_194 = &io_trigger_pkt_any_0_tdata2[5:0]; // @[el2_lib.scala 244:36] + wire _T_195 = _T_194 & _T_153; // @[el2_lib.scala 244:41] + wire _T_198 = io_trigger_pkt_any_0_tdata2[6] == dec_i0_match_data_0[6]; // @[el2_lib.scala 244:78] + wire _T_199 = _T_195 | _T_198; // @[el2_lib.scala 244:23] + wire _T_201 = &io_trigger_pkt_any_0_tdata2[6:0]; // @[el2_lib.scala 244:36] + wire _T_202 = _T_201 & _T_153; // @[el2_lib.scala 244:41] + wire _T_205 = io_trigger_pkt_any_0_tdata2[7] == dec_i0_match_data_0[7]; // @[el2_lib.scala 244:78] + wire _T_206 = _T_202 | _T_205; // @[el2_lib.scala 244:23] + wire _T_208 = &io_trigger_pkt_any_0_tdata2[7:0]; // @[el2_lib.scala 244:36] + wire _T_209 = _T_208 & _T_153; // @[el2_lib.scala 244:41] + wire _T_212 = io_trigger_pkt_any_0_tdata2[8] == dec_i0_match_data_0[8]; // @[el2_lib.scala 244:78] + wire _T_213 = _T_209 | _T_212; // @[el2_lib.scala 244:23] + wire _T_215 = &io_trigger_pkt_any_0_tdata2[8:0]; // @[el2_lib.scala 244:36] + wire _T_216 = _T_215 & _T_153; // @[el2_lib.scala 244:41] + wire _T_219 = io_trigger_pkt_any_0_tdata2[9] == dec_i0_match_data_0[9]; // @[el2_lib.scala 244:78] + wire _T_220 = _T_216 | _T_219; // @[el2_lib.scala 244:23] + wire _T_222 = &io_trigger_pkt_any_0_tdata2[9:0]; // @[el2_lib.scala 244:36] + wire _T_223 = _T_222 & _T_153; // @[el2_lib.scala 244:41] + wire _T_226 = io_trigger_pkt_any_0_tdata2[10] == dec_i0_match_data_0[10]; // @[el2_lib.scala 244:78] + wire _T_227 = _T_223 | _T_226; // @[el2_lib.scala 244:23] + wire _T_229 = &io_trigger_pkt_any_0_tdata2[10:0]; // @[el2_lib.scala 244:36] + wire _T_230 = _T_229 & _T_153; // @[el2_lib.scala 244:41] + wire _T_233 = io_trigger_pkt_any_0_tdata2[11] == dec_i0_match_data_0[11]; // @[el2_lib.scala 244:78] + wire _T_234 = _T_230 | _T_233; // @[el2_lib.scala 244:23] + wire _T_236 = &io_trigger_pkt_any_0_tdata2[11:0]; // @[el2_lib.scala 244:36] + wire _T_237 = _T_236 & _T_153; // @[el2_lib.scala 244:41] + wire _T_240 = io_trigger_pkt_any_0_tdata2[12] == dec_i0_match_data_0[12]; // @[el2_lib.scala 244:78] + wire _T_241 = _T_237 | _T_240; // @[el2_lib.scala 244:23] + wire _T_243 = &io_trigger_pkt_any_0_tdata2[12:0]; // @[el2_lib.scala 244:36] + wire _T_244 = _T_243 & _T_153; // @[el2_lib.scala 244:41] + wire _T_247 = io_trigger_pkt_any_0_tdata2[13] == dec_i0_match_data_0[13]; // @[el2_lib.scala 244:78] + wire _T_248 = _T_244 | _T_247; // @[el2_lib.scala 244:23] + wire _T_250 = &io_trigger_pkt_any_0_tdata2[13:0]; // @[el2_lib.scala 244:36] + wire _T_251 = _T_250 & _T_153; // @[el2_lib.scala 244:41] + wire _T_254 = io_trigger_pkt_any_0_tdata2[14] == dec_i0_match_data_0[14]; // @[el2_lib.scala 244:78] + wire _T_255 = _T_251 | _T_254; // @[el2_lib.scala 244:23] + wire _T_257 = &io_trigger_pkt_any_0_tdata2[14:0]; // @[el2_lib.scala 244:36] + wire _T_258 = _T_257 & _T_153; // @[el2_lib.scala 244:41] + wire _T_261 = io_trigger_pkt_any_0_tdata2[15] == dec_i0_match_data_0[15]; // @[el2_lib.scala 244:78] + wire _T_262 = _T_258 | _T_261; // @[el2_lib.scala 244:23] + wire _T_264 = &io_trigger_pkt_any_0_tdata2[15:0]; // @[el2_lib.scala 244:36] + wire _T_265 = _T_264 & _T_153; // @[el2_lib.scala 244:41] + wire _T_268 = io_trigger_pkt_any_0_tdata2[16] == dec_i0_match_data_0[16]; // @[el2_lib.scala 244:78] + wire _T_269 = _T_265 | _T_268; // @[el2_lib.scala 244:23] + wire _T_271 = &io_trigger_pkt_any_0_tdata2[16:0]; // @[el2_lib.scala 244:36] + wire _T_272 = _T_271 & _T_153; // @[el2_lib.scala 244:41] + wire _T_275 = io_trigger_pkt_any_0_tdata2[17] == dec_i0_match_data_0[17]; // @[el2_lib.scala 244:78] + wire _T_276 = _T_272 | _T_275; // @[el2_lib.scala 244:23] + wire _T_278 = &io_trigger_pkt_any_0_tdata2[17:0]; // @[el2_lib.scala 244:36] + wire _T_279 = _T_278 & _T_153; // @[el2_lib.scala 244:41] + wire _T_282 = io_trigger_pkt_any_0_tdata2[18] == dec_i0_match_data_0[18]; // @[el2_lib.scala 244:78] + wire _T_283 = _T_279 | _T_282; // @[el2_lib.scala 244:23] + wire _T_285 = &io_trigger_pkt_any_0_tdata2[18:0]; // @[el2_lib.scala 244:36] + wire _T_286 = _T_285 & _T_153; // @[el2_lib.scala 244:41] + wire _T_289 = io_trigger_pkt_any_0_tdata2[19] == dec_i0_match_data_0[19]; // @[el2_lib.scala 244:78] + wire _T_290 = _T_286 | _T_289; // @[el2_lib.scala 244:23] + wire _T_292 = &io_trigger_pkt_any_0_tdata2[19:0]; // @[el2_lib.scala 244:36] + wire _T_293 = _T_292 & _T_153; // @[el2_lib.scala 244:41] + wire _T_296 = io_trigger_pkt_any_0_tdata2[20] == dec_i0_match_data_0[20]; // @[el2_lib.scala 244:78] + wire _T_297 = _T_293 | _T_296; // @[el2_lib.scala 244:23] + wire _T_299 = &io_trigger_pkt_any_0_tdata2[20:0]; // @[el2_lib.scala 244:36] + wire _T_300 = _T_299 & _T_153; // @[el2_lib.scala 244:41] + wire _T_303 = io_trigger_pkt_any_0_tdata2[21] == dec_i0_match_data_0[21]; // @[el2_lib.scala 244:78] + wire _T_304 = _T_300 | _T_303; // @[el2_lib.scala 244:23] + wire _T_306 = &io_trigger_pkt_any_0_tdata2[21:0]; // @[el2_lib.scala 244:36] + wire _T_307 = _T_306 & _T_153; // @[el2_lib.scala 244:41] + wire _T_310 = io_trigger_pkt_any_0_tdata2[22] == dec_i0_match_data_0[22]; // @[el2_lib.scala 244:78] + wire _T_311 = _T_307 | _T_310; // @[el2_lib.scala 244:23] + wire _T_313 = &io_trigger_pkt_any_0_tdata2[22:0]; // @[el2_lib.scala 244:36] + wire _T_314 = _T_313 & _T_153; // @[el2_lib.scala 244:41] + wire _T_317 = io_trigger_pkt_any_0_tdata2[23] == dec_i0_match_data_0[23]; // @[el2_lib.scala 244:78] + wire _T_318 = _T_314 | _T_317; // @[el2_lib.scala 244:23] + wire _T_320 = &io_trigger_pkt_any_0_tdata2[23:0]; // @[el2_lib.scala 244:36] + wire _T_321 = _T_320 & _T_153; // @[el2_lib.scala 244:41] + wire _T_324 = io_trigger_pkt_any_0_tdata2[24] == dec_i0_match_data_0[24]; // @[el2_lib.scala 244:78] + wire _T_325 = _T_321 | _T_324; // @[el2_lib.scala 244:23] + wire _T_327 = &io_trigger_pkt_any_0_tdata2[24:0]; // @[el2_lib.scala 244:36] + wire _T_328 = _T_327 & _T_153; // @[el2_lib.scala 244:41] + wire _T_331 = io_trigger_pkt_any_0_tdata2[25] == dec_i0_match_data_0[25]; // @[el2_lib.scala 244:78] + wire _T_332 = _T_328 | _T_331; // @[el2_lib.scala 244:23] + wire _T_334 = &io_trigger_pkt_any_0_tdata2[25:0]; // @[el2_lib.scala 244:36] + wire _T_335 = _T_334 & _T_153; // @[el2_lib.scala 244:41] + wire _T_338 = io_trigger_pkt_any_0_tdata2[26] == dec_i0_match_data_0[26]; // @[el2_lib.scala 244:78] + wire _T_339 = _T_335 | _T_338; // @[el2_lib.scala 244:23] + wire _T_341 = &io_trigger_pkt_any_0_tdata2[26:0]; // @[el2_lib.scala 244:36] + wire _T_342 = _T_341 & _T_153; // @[el2_lib.scala 244:41] + wire _T_345 = io_trigger_pkt_any_0_tdata2[27] == dec_i0_match_data_0[27]; // @[el2_lib.scala 244:78] + wire _T_346 = _T_342 | _T_345; // @[el2_lib.scala 244:23] + wire _T_348 = &io_trigger_pkt_any_0_tdata2[27:0]; // @[el2_lib.scala 244:36] + wire _T_349 = _T_348 & _T_153; // @[el2_lib.scala 244:41] + wire _T_352 = io_trigger_pkt_any_0_tdata2[28] == dec_i0_match_data_0[28]; // @[el2_lib.scala 244:78] + wire _T_353 = _T_349 | _T_352; // @[el2_lib.scala 244:23] + wire _T_355 = &io_trigger_pkt_any_0_tdata2[28:0]; // @[el2_lib.scala 244:36] + wire _T_356 = _T_355 & _T_153; // @[el2_lib.scala 244:41] + wire _T_359 = io_trigger_pkt_any_0_tdata2[29] == dec_i0_match_data_0[29]; // @[el2_lib.scala 244:78] + wire _T_360 = _T_356 | _T_359; // @[el2_lib.scala 244:23] + wire _T_362 = &io_trigger_pkt_any_0_tdata2[29:0]; // @[el2_lib.scala 244:36] + wire _T_363 = _T_362 & _T_153; // @[el2_lib.scala 244:41] + wire _T_366 = io_trigger_pkt_any_0_tdata2[30] == dec_i0_match_data_0[30]; // @[el2_lib.scala 244:78] + wire _T_367 = _T_363 | _T_366; // @[el2_lib.scala 244:23] + wire _T_369 = &io_trigger_pkt_any_0_tdata2[30:0]; // @[el2_lib.scala 244:36] + wire _T_370 = _T_369 & _T_153; // @[el2_lib.scala 244:41] + wire _T_373 = io_trigger_pkt_any_0_tdata2[31] == dec_i0_match_data_0[31]; // @[el2_lib.scala 244:78] + wire _T_374 = _T_370 | _T_373; // @[el2_lib.scala 244:23] + wire [7:0] _T_381 = {_T_206,_T_199,_T_192,_T_185,_T_178,_T_171,_T_164,_T_157}; // @[el2_lib.scala 245:14] + wire [15:0] _T_389 = {_T_262,_T_255,_T_248,_T_241,_T_234,_T_227,_T_220,_T_213,_T_381}; // @[el2_lib.scala 245:14] + wire [7:0] _T_396 = {_T_318,_T_311,_T_304,_T_297,_T_290,_T_283,_T_276,_T_269}; // @[el2_lib.scala 245:14] + wire [31:0] _T_405 = {_T_374,_T_367,_T_360,_T_353,_T_346,_T_339,_T_332,_T_325,_T_396,_T_389}; // @[el2_lib.scala 245:14] + wire [31:0] _GEN_0 = {{31'd0}, _T_148}; // @[el2_dec_trigger.scala 15:109] + wire [31:0] _T_406 = _GEN_0 & _T_405; // @[el2_dec_trigger.scala 15:109] + wire _T_407 = io_trigger_pkt_any_1_execute & io_trigger_pkt_any_1_m; // @[el2_dec_trigger.scala 15:83] + wire _T_410 = &io_trigger_pkt_any_1_tdata2; // @[el2_lib.scala 241:45] + wire _T_411 = ~_T_410; // @[el2_lib.scala 241:39] + wire _T_412 = io_trigger_pkt_any_1_match_pkt & _T_411; // @[el2_lib.scala 241:37] + wire _T_415 = io_trigger_pkt_any_1_tdata2[0] == dec_i0_match_data_1[0]; // @[el2_lib.scala 242:52] + wire _T_416 = _T_412 | _T_415; // @[el2_lib.scala 242:41] + wire _T_418 = &io_trigger_pkt_any_1_tdata2[0]; // @[el2_lib.scala 244:36] + wire _T_419 = _T_418 & _T_412; // @[el2_lib.scala 244:41] + wire _T_422 = io_trigger_pkt_any_1_tdata2[1] == dec_i0_match_data_1[1]; // @[el2_lib.scala 244:78] + wire _T_423 = _T_419 | _T_422; // @[el2_lib.scala 244:23] + wire _T_425 = &io_trigger_pkt_any_1_tdata2[1:0]; // @[el2_lib.scala 244:36] + wire _T_426 = _T_425 & _T_412; // @[el2_lib.scala 244:41] + wire _T_429 = io_trigger_pkt_any_1_tdata2[2] == dec_i0_match_data_1[2]; // @[el2_lib.scala 244:78] + wire _T_430 = _T_426 | _T_429; // @[el2_lib.scala 244:23] + wire _T_432 = &io_trigger_pkt_any_1_tdata2[2:0]; // @[el2_lib.scala 244:36] + wire _T_433 = _T_432 & _T_412; // @[el2_lib.scala 244:41] + wire _T_436 = io_trigger_pkt_any_1_tdata2[3] == dec_i0_match_data_1[3]; // @[el2_lib.scala 244:78] + wire _T_437 = _T_433 | _T_436; // @[el2_lib.scala 244:23] + wire _T_439 = &io_trigger_pkt_any_1_tdata2[3:0]; // @[el2_lib.scala 244:36] + wire _T_440 = _T_439 & _T_412; // @[el2_lib.scala 244:41] + wire _T_443 = io_trigger_pkt_any_1_tdata2[4] == dec_i0_match_data_1[4]; // @[el2_lib.scala 244:78] + wire _T_444 = _T_440 | _T_443; // @[el2_lib.scala 244:23] + wire _T_446 = &io_trigger_pkt_any_1_tdata2[4:0]; // @[el2_lib.scala 244:36] + wire _T_447 = _T_446 & _T_412; // @[el2_lib.scala 244:41] + wire _T_450 = io_trigger_pkt_any_1_tdata2[5] == dec_i0_match_data_1[5]; // @[el2_lib.scala 244:78] + wire _T_451 = _T_447 | _T_450; // @[el2_lib.scala 244:23] + wire _T_453 = &io_trigger_pkt_any_1_tdata2[5:0]; // @[el2_lib.scala 244:36] + wire _T_454 = _T_453 & _T_412; // @[el2_lib.scala 244:41] + wire _T_457 = io_trigger_pkt_any_1_tdata2[6] == dec_i0_match_data_1[6]; // @[el2_lib.scala 244:78] + wire _T_458 = _T_454 | _T_457; // @[el2_lib.scala 244:23] + wire _T_460 = &io_trigger_pkt_any_1_tdata2[6:0]; // @[el2_lib.scala 244:36] + wire _T_461 = _T_460 & _T_412; // @[el2_lib.scala 244:41] + wire _T_464 = io_trigger_pkt_any_1_tdata2[7] == dec_i0_match_data_1[7]; // @[el2_lib.scala 244:78] + wire _T_465 = _T_461 | _T_464; // @[el2_lib.scala 244:23] + wire _T_467 = &io_trigger_pkt_any_1_tdata2[7:0]; // @[el2_lib.scala 244:36] + wire _T_468 = _T_467 & _T_412; // @[el2_lib.scala 244:41] + wire _T_471 = io_trigger_pkt_any_1_tdata2[8] == dec_i0_match_data_1[8]; // @[el2_lib.scala 244:78] + wire _T_472 = _T_468 | _T_471; // @[el2_lib.scala 244:23] + wire _T_474 = &io_trigger_pkt_any_1_tdata2[8:0]; // @[el2_lib.scala 244:36] + wire _T_475 = _T_474 & _T_412; // @[el2_lib.scala 244:41] + wire _T_478 = io_trigger_pkt_any_1_tdata2[9] == dec_i0_match_data_1[9]; // @[el2_lib.scala 244:78] + wire _T_479 = _T_475 | _T_478; // @[el2_lib.scala 244:23] + wire _T_481 = &io_trigger_pkt_any_1_tdata2[9:0]; // @[el2_lib.scala 244:36] + wire _T_482 = _T_481 & _T_412; // @[el2_lib.scala 244:41] + wire _T_485 = io_trigger_pkt_any_1_tdata2[10] == dec_i0_match_data_1[10]; // @[el2_lib.scala 244:78] + wire _T_486 = _T_482 | _T_485; // @[el2_lib.scala 244:23] + wire _T_488 = &io_trigger_pkt_any_1_tdata2[10:0]; // @[el2_lib.scala 244:36] + wire _T_489 = _T_488 & _T_412; // @[el2_lib.scala 244:41] + wire _T_492 = io_trigger_pkt_any_1_tdata2[11] == dec_i0_match_data_1[11]; // @[el2_lib.scala 244:78] + wire _T_493 = _T_489 | _T_492; // @[el2_lib.scala 244:23] + wire _T_495 = &io_trigger_pkt_any_1_tdata2[11:0]; // @[el2_lib.scala 244:36] + wire _T_496 = _T_495 & _T_412; // @[el2_lib.scala 244:41] + wire _T_499 = io_trigger_pkt_any_1_tdata2[12] == dec_i0_match_data_1[12]; // @[el2_lib.scala 244:78] + wire _T_500 = _T_496 | _T_499; // @[el2_lib.scala 244:23] + wire _T_502 = &io_trigger_pkt_any_1_tdata2[12:0]; // @[el2_lib.scala 244:36] + wire _T_503 = _T_502 & _T_412; // @[el2_lib.scala 244:41] + wire _T_506 = io_trigger_pkt_any_1_tdata2[13] == dec_i0_match_data_1[13]; // @[el2_lib.scala 244:78] + wire _T_507 = _T_503 | _T_506; // @[el2_lib.scala 244:23] + wire _T_509 = &io_trigger_pkt_any_1_tdata2[13:0]; // @[el2_lib.scala 244:36] + wire _T_510 = _T_509 & _T_412; // @[el2_lib.scala 244:41] + wire _T_513 = io_trigger_pkt_any_1_tdata2[14] == dec_i0_match_data_1[14]; // @[el2_lib.scala 244:78] + wire _T_514 = _T_510 | _T_513; // @[el2_lib.scala 244:23] + wire _T_516 = &io_trigger_pkt_any_1_tdata2[14:0]; // @[el2_lib.scala 244:36] + wire _T_517 = _T_516 & _T_412; // @[el2_lib.scala 244:41] + wire _T_520 = io_trigger_pkt_any_1_tdata2[15] == dec_i0_match_data_1[15]; // @[el2_lib.scala 244:78] + wire _T_521 = _T_517 | _T_520; // @[el2_lib.scala 244:23] + wire _T_523 = &io_trigger_pkt_any_1_tdata2[15:0]; // @[el2_lib.scala 244:36] + wire _T_524 = _T_523 & _T_412; // @[el2_lib.scala 244:41] + wire _T_527 = io_trigger_pkt_any_1_tdata2[16] == dec_i0_match_data_1[16]; // @[el2_lib.scala 244:78] + wire _T_528 = _T_524 | _T_527; // @[el2_lib.scala 244:23] + wire _T_530 = &io_trigger_pkt_any_1_tdata2[16:0]; // @[el2_lib.scala 244:36] + wire _T_531 = _T_530 & _T_412; // @[el2_lib.scala 244:41] + wire _T_534 = io_trigger_pkt_any_1_tdata2[17] == dec_i0_match_data_1[17]; // @[el2_lib.scala 244:78] + wire _T_535 = _T_531 | _T_534; // @[el2_lib.scala 244:23] + wire _T_537 = &io_trigger_pkt_any_1_tdata2[17:0]; // @[el2_lib.scala 244:36] + wire _T_538 = _T_537 & _T_412; // @[el2_lib.scala 244:41] + wire _T_541 = io_trigger_pkt_any_1_tdata2[18] == dec_i0_match_data_1[18]; // @[el2_lib.scala 244:78] + wire _T_542 = _T_538 | _T_541; // @[el2_lib.scala 244:23] + wire _T_544 = &io_trigger_pkt_any_1_tdata2[18:0]; // @[el2_lib.scala 244:36] + wire _T_545 = _T_544 & _T_412; // @[el2_lib.scala 244:41] + wire _T_548 = io_trigger_pkt_any_1_tdata2[19] == dec_i0_match_data_1[19]; // @[el2_lib.scala 244:78] + wire _T_549 = _T_545 | _T_548; // @[el2_lib.scala 244:23] + wire _T_551 = &io_trigger_pkt_any_1_tdata2[19:0]; // @[el2_lib.scala 244:36] + wire _T_552 = _T_551 & _T_412; // @[el2_lib.scala 244:41] + wire _T_555 = io_trigger_pkt_any_1_tdata2[20] == dec_i0_match_data_1[20]; // @[el2_lib.scala 244:78] + wire _T_556 = _T_552 | _T_555; // @[el2_lib.scala 244:23] + wire _T_558 = &io_trigger_pkt_any_1_tdata2[20:0]; // @[el2_lib.scala 244:36] + wire _T_559 = _T_558 & _T_412; // @[el2_lib.scala 244:41] + wire _T_562 = io_trigger_pkt_any_1_tdata2[21] == dec_i0_match_data_1[21]; // @[el2_lib.scala 244:78] + wire _T_563 = _T_559 | _T_562; // @[el2_lib.scala 244:23] + wire _T_565 = &io_trigger_pkt_any_1_tdata2[21:0]; // @[el2_lib.scala 244:36] + wire _T_566 = _T_565 & _T_412; // @[el2_lib.scala 244:41] + wire _T_569 = io_trigger_pkt_any_1_tdata2[22] == dec_i0_match_data_1[22]; // @[el2_lib.scala 244:78] + wire _T_570 = _T_566 | _T_569; // @[el2_lib.scala 244:23] + wire _T_572 = &io_trigger_pkt_any_1_tdata2[22:0]; // @[el2_lib.scala 244:36] + wire _T_573 = _T_572 & _T_412; // @[el2_lib.scala 244:41] + wire _T_576 = io_trigger_pkt_any_1_tdata2[23] == dec_i0_match_data_1[23]; // @[el2_lib.scala 244:78] + wire _T_577 = _T_573 | _T_576; // @[el2_lib.scala 244:23] + wire _T_579 = &io_trigger_pkt_any_1_tdata2[23:0]; // @[el2_lib.scala 244:36] + wire _T_580 = _T_579 & _T_412; // @[el2_lib.scala 244:41] + wire _T_583 = io_trigger_pkt_any_1_tdata2[24] == dec_i0_match_data_1[24]; // @[el2_lib.scala 244:78] + wire _T_584 = _T_580 | _T_583; // @[el2_lib.scala 244:23] + wire _T_586 = &io_trigger_pkt_any_1_tdata2[24:0]; // @[el2_lib.scala 244:36] + wire _T_587 = _T_586 & _T_412; // @[el2_lib.scala 244:41] + wire _T_590 = io_trigger_pkt_any_1_tdata2[25] == dec_i0_match_data_1[25]; // @[el2_lib.scala 244:78] + wire _T_591 = _T_587 | _T_590; // @[el2_lib.scala 244:23] + wire _T_593 = &io_trigger_pkt_any_1_tdata2[25:0]; // @[el2_lib.scala 244:36] + wire _T_594 = _T_593 & _T_412; // @[el2_lib.scala 244:41] + wire _T_597 = io_trigger_pkt_any_1_tdata2[26] == dec_i0_match_data_1[26]; // @[el2_lib.scala 244:78] + wire _T_598 = _T_594 | _T_597; // @[el2_lib.scala 244:23] + wire _T_600 = &io_trigger_pkt_any_1_tdata2[26:0]; // @[el2_lib.scala 244:36] + wire _T_601 = _T_600 & _T_412; // @[el2_lib.scala 244:41] + wire _T_604 = io_trigger_pkt_any_1_tdata2[27] == dec_i0_match_data_1[27]; // @[el2_lib.scala 244:78] + wire _T_605 = _T_601 | _T_604; // @[el2_lib.scala 244:23] + wire _T_607 = &io_trigger_pkt_any_1_tdata2[27:0]; // @[el2_lib.scala 244:36] + wire _T_608 = _T_607 & _T_412; // @[el2_lib.scala 244:41] + wire _T_611 = io_trigger_pkt_any_1_tdata2[28] == dec_i0_match_data_1[28]; // @[el2_lib.scala 244:78] + wire _T_612 = _T_608 | _T_611; // @[el2_lib.scala 244:23] + wire _T_614 = &io_trigger_pkt_any_1_tdata2[28:0]; // @[el2_lib.scala 244:36] + wire _T_615 = _T_614 & _T_412; // @[el2_lib.scala 244:41] + wire _T_618 = io_trigger_pkt_any_1_tdata2[29] == dec_i0_match_data_1[29]; // @[el2_lib.scala 244:78] + wire _T_619 = _T_615 | _T_618; // @[el2_lib.scala 244:23] + wire _T_621 = &io_trigger_pkt_any_1_tdata2[29:0]; // @[el2_lib.scala 244:36] + wire _T_622 = _T_621 & _T_412; // @[el2_lib.scala 244:41] + wire _T_625 = io_trigger_pkt_any_1_tdata2[30] == dec_i0_match_data_1[30]; // @[el2_lib.scala 244:78] + wire _T_626 = _T_622 | _T_625; // @[el2_lib.scala 244:23] + wire _T_628 = &io_trigger_pkt_any_1_tdata2[30:0]; // @[el2_lib.scala 244:36] + wire _T_629 = _T_628 & _T_412; // @[el2_lib.scala 244:41] + wire _T_632 = io_trigger_pkt_any_1_tdata2[31] == dec_i0_match_data_1[31]; // @[el2_lib.scala 244:78] + wire _T_633 = _T_629 | _T_632; // @[el2_lib.scala 244:23] + wire [7:0] _T_640 = {_T_465,_T_458,_T_451,_T_444,_T_437,_T_430,_T_423,_T_416}; // @[el2_lib.scala 245:14] + wire [15:0] _T_648 = {_T_521,_T_514,_T_507,_T_500,_T_493,_T_486,_T_479,_T_472,_T_640}; // @[el2_lib.scala 245:14] + wire [7:0] _T_655 = {_T_577,_T_570,_T_563,_T_556,_T_549,_T_542,_T_535,_T_528}; // @[el2_lib.scala 245:14] + wire [31:0] _T_664 = {_T_633,_T_626,_T_619,_T_612,_T_605,_T_598,_T_591,_T_584,_T_655,_T_648}; // @[el2_lib.scala 245:14] + wire [31:0] _GEN_1 = {{31'd0}, _T_407}; // @[el2_dec_trigger.scala 15:109] + wire [31:0] _T_665 = _GEN_1 & _T_664; // @[el2_dec_trigger.scala 15:109] + wire _T_666 = io_trigger_pkt_any_2_execute & io_trigger_pkt_any_2_m; // @[el2_dec_trigger.scala 15:83] + wire _T_669 = &io_trigger_pkt_any_2_tdata2; // @[el2_lib.scala 241:45] + wire _T_670 = ~_T_669; // @[el2_lib.scala 241:39] + wire _T_671 = io_trigger_pkt_any_2_match_pkt & _T_670; // @[el2_lib.scala 241:37] + wire _T_674 = io_trigger_pkt_any_2_tdata2[0] == dec_i0_match_data_2[0]; // @[el2_lib.scala 242:52] + wire _T_675 = _T_671 | _T_674; // @[el2_lib.scala 242:41] + wire _T_677 = &io_trigger_pkt_any_2_tdata2[0]; // @[el2_lib.scala 244:36] + wire _T_678 = _T_677 & _T_671; // @[el2_lib.scala 244:41] + wire _T_681 = io_trigger_pkt_any_2_tdata2[1] == dec_i0_match_data_2[1]; // @[el2_lib.scala 244:78] + wire _T_682 = _T_678 | _T_681; // @[el2_lib.scala 244:23] + wire _T_684 = &io_trigger_pkt_any_2_tdata2[1:0]; // @[el2_lib.scala 244:36] + wire _T_685 = _T_684 & _T_671; // @[el2_lib.scala 244:41] + wire _T_688 = io_trigger_pkt_any_2_tdata2[2] == dec_i0_match_data_2[2]; // @[el2_lib.scala 244:78] + wire _T_689 = _T_685 | _T_688; // @[el2_lib.scala 244:23] + wire _T_691 = &io_trigger_pkt_any_2_tdata2[2:0]; // @[el2_lib.scala 244:36] + wire _T_692 = _T_691 & _T_671; // @[el2_lib.scala 244:41] + wire _T_695 = io_trigger_pkt_any_2_tdata2[3] == dec_i0_match_data_2[3]; // @[el2_lib.scala 244:78] + wire _T_696 = _T_692 | _T_695; // @[el2_lib.scala 244:23] + wire _T_698 = &io_trigger_pkt_any_2_tdata2[3:0]; // @[el2_lib.scala 244:36] + wire _T_699 = _T_698 & _T_671; // @[el2_lib.scala 244:41] + wire _T_702 = io_trigger_pkt_any_2_tdata2[4] == dec_i0_match_data_2[4]; // @[el2_lib.scala 244:78] + wire _T_703 = _T_699 | _T_702; // @[el2_lib.scala 244:23] + wire _T_705 = &io_trigger_pkt_any_2_tdata2[4:0]; // @[el2_lib.scala 244:36] + wire _T_706 = _T_705 & _T_671; // @[el2_lib.scala 244:41] + wire _T_709 = io_trigger_pkt_any_2_tdata2[5] == dec_i0_match_data_2[5]; // @[el2_lib.scala 244:78] + wire _T_710 = _T_706 | _T_709; // @[el2_lib.scala 244:23] + wire _T_712 = &io_trigger_pkt_any_2_tdata2[5:0]; // @[el2_lib.scala 244:36] + wire _T_713 = _T_712 & _T_671; // @[el2_lib.scala 244:41] + wire _T_716 = io_trigger_pkt_any_2_tdata2[6] == dec_i0_match_data_2[6]; // @[el2_lib.scala 244:78] + wire _T_717 = _T_713 | _T_716; // @[el2_lib.scala 244:23] + wire _T_719 = &io_trigger_pkt_any_2_tdata2[6:0]; // @[el2_lib.scala 244:36] + wire _T_720 = _T_719 & _T_671; // @[el2_lib.scala 244:41] + wire _T_723 = io_trigger_pkt_any_2_tdata2[7] == dec_i0_match_data_2[7]; // @[el2_lib.scala 244:78] + wire _T_724 = _T_720 | _T_723; // @[el2_lib.scala 244:23] + wire _T_726 = &io_trigger_pkt_any_2_tdata2[7:0]; // @[el2_lib.scala 244:36] + wire _T_727 = _T_726 & _T_671; // @[el2_lib.scala 244:41] + wire _T_730 = io_trigger_pkt_any_2_tdata2[8] == dec_i0_match_data_2[8]; // @[el2_lib.scala 244:78] + wire _T_731 = _T_727 | _T_730; // @[el2_lib.scala 244:23] + wire _T_733 = &io_trigger_pkt_any_2_tdata2[8:0]; // @[el2_lib.scala 244:36] + wire _T_734 = _T_733 & _T_671; // @[el2_lib.scala 244:41] + wire _T_737 = io_trigger_pkt_any_2_tdata2[9] == dec_i0_match_data_2[9]; // @[el2_lib.scala 244:78] + wire _T_738 = _T_734 | _T_737; // @[el2_lib.scala 244:23] + wire _T_740 = &io_trigger_pkt_any_2_tdata2[9:0]; // @[el2_lib.scala 244:36] + wire _T_741 = _T_740 & _T_671; // @[el2_lib.scala 244:41] + wire _T_744 = io_trigger_pkt_any_2_tdata2[10] == dec_i0_match_data_2[10]; // @[el2_lib.scala 244:78] + wire _T_745 = _T_741 | _T_744; // @[el2_lib.scala 244:23] + wire _T_747 = &io_trigger_pkt_any_2_tdata2[10:0]; // @[el2_lib.scala 244:36] + wire _T_748 = _T_747 & _T_671; // @[el2_lib.scala 244:41] + wire _T_751 = io_trigger_pkt_any_2_tdata2[11] == dec_i0_match_data_2[11]; // @[el2_lib.scala 244:78] + wire _T_752 = _T_748 | _T_751; // @[el2_lib.scala 244:23] + wire _T_754 = &io_trigger_pkt_any_2_tdata2[11:0]; // @[el2_lib.scala 244:36] + wire _T_755 = _T_754 & _T_671; // @[el2_lib.scala 244:41] + wire _T_758 = io_trigger_pkt_any_2_tdata2[12] == dec_i0_match_data_2[12]; // @[el2_lib.scala 244:78] + wire _T_759 = _T_755 | _T_758; // @[el2_lib.scala 244:23] + wire _T_761 = &io_trigger_pkt_any_2_tdata2[12:0]; // @[el2_lib.scala 244:36] + wire _T_762 = _T_761 & _T_671; // @[el2_lib.scala 244:41] + wire _T_765 = io_trigger_pkt_any_2_tdata2[13] == dec_i0_match_data_2[13]; // @[el2_lib.scala 244:78] + wire _T_766 = _T_762 | _T_765; // @[el2_lib.scala 244:23] + wire _T_768 = &io_trigger_pkt_any_2_tdata2[13:0]; // @[el2_lib.scala 244:36] + wire _T_769 = _T_768 & _T_671; // @[el2_lib.scala 244:41] + wire _T_772 = io_trigger_pkt_any_2_tdata2[14] == dec_i0_match_data_2[14]; // @[el2_lib.scala 244:78] + wire _T_773 = _T_769 | _T_772; // @[el2_lib.scala 244:23] + wire _T_775 = &io_trigger_pkt_any_2_tdata2[14:0]; // @[el2_lib.scala 244:36] + wire _T_776 = _T_775 & _T_671; // @[el2_lib.scala 244:41] + wire _T_779 = io_trigger_pkt_any_2_tdata2[15] == dec_i0_match_data_2[15]; // @[el2_lib.scala 244:78] + wire _T_780 = _T_776 | _T_779; // @[el2_lib.scala 244:23] + wire _T_782 = &io_trigger_pkt_any_2_tdata2[15:0]; // @[el2_lib.scala 244:36] + wire _T_783 = _T_782 & _T_671; // @[el2_lib.scala 244:41] + wire _T_786 = io_trigger_pkt_any_2_tdata2[16] == dec_i0_match_data_2[16]; // @[el2_lib.scala 244:78] + wire _T_787 = _T_783 | _T_786; // @[el2_lib.scala 244:23] + wire _T_789 = &io_trigger_pkt_any_2_tdata2[16:0]; // @[el2_lib.scala 244:36] + wire _T_790 = _T_789 & _T_671; // @[el2_lib.scala 244:41] + wire _T_793 = io_trigger_pkt_any_2_tdata2[17] == dec_i0_match_data_2[17]; // @[el2_lib.scala 244:78] + wire _T_794 = _T_790 | _T_793; // @[el2_lib.scala 244:23] + wire _T_796 = &io_trigger_pkt_any_2_tdata2[17:0]; // @[el2_lib.scala 244:36] + wire _T_797 = _T_796 & _T_671; // @[el2_lib.scala 244:41] + wire _T_800 = io_trigger_pkt_any_2_tdata2[18] == dec_i0_match_data_2[18]; // @[el2_lib.scala 244:78] + wire _T_801 = _T_797 | _T_800; // @[el2_lib.scala 244:23] + wire _T_803 = &io_trigger_pkt_any_2_tdata2[18:0]; // @[el2_lib.scala 244:36] + wire _T_804 = _T_803 & _T_671; // @[el2_lib.scala 244:41] + wire _T_807 = io_trigger_pkt_any_2_tdata2[19] == dec_i0_match_data_2[19]; // @[el2_lib.scala 244:78] + wire _T_808 = _T_804 | _T_807; // @[el2_lib.scala 244:23] + wire _T_810 = &io_trigger_pkt_any_2_tdata2[19:0]; // @[el2_lib.scala 244:36] + wire _T_811 = _T_810 & _T_671; // @[el2_lib.scala 244:41] + wire _T_814 = io_trigger_pkt_any_2_tdata2[20] == dec_i0_match_data_2[20]; // @[el2_lib.scala 244:78] + wire _T_815 = _T_811 | _T_814; // @[el2_lib.scala 244:23] + wire _T_817 = &io_trigger_pkt_any_2_tdata2[20:0]; // @[el2_lib.scala 244:36] + wire _T_818 = _T_817 & _T_671; // @[el2_lib.scala 244:41] + wire _T_821 = io_trigger_pkt_any_2_tdata2[21] == dec_i0_match_data_2[21]; // @[el2_lib.scala 244:78] + wire _T_822 = _T_818 | _T_821; // @[el2_lib.scala 244:23] + wire _T_824 = &io_trigger_pkt_any_2_tdata2[21:0]; // @[el2_lib.scala 244:36] + wire _T_825 = _T_824 & _T_671; // @[el2_lib.scala 244:41] + wire _T_828 = io_trigger_pkt_any_2_tdata2[22] == dec_i0_match_data_2[22]; // @[el2_lib.scala 244:78] + wire _T_829 = _T_825 | _T_828; // @[el2_lib.scala 244:23] + wire _T_831 = &io_trigger_pkt_any_2_tdata2[22:0]; // @[el2_lib.scala 244:36] + wire _T_832 = _T_831 & _T_671; // @[el2_lib.scala 244:41] + wire _T_835 = io_trigger_pkt_any_2_tdata2[23] == dec_i0_match_data_2[23]; // @[el2_lib.scala 244:78] + wire _T_836 = _T_832 | _T_835; // @[el2_lib.scala 244:23] + wire _T_838 = &io_trigger_pkt_any_2_tdata2[23:0]; // @[el2_lib.scala 244:36] + wire _T_839 = _T_838 & _T_671; // @[el2_lib.scala 244:41] + wire _T_842 = io_trigger_pkt_any_2_tdata2[24] == dec_i0_match_data_2[24]; // @[el2_lib.scala 244:78] + wire _T_843 = _T_839 | _T_842; // @[el2_lib.scala 244:23] + wire _T_845 = &io_trigger_pkt_any_2_tdata2[24:0]; // @[el2_lib.scala 244:36] + wire _T_846 = _T_845 & _T_671; // @[el2_lib.scala 244:41] + wire _T_849 = io_trigger_pkt_any_2_tdata2[25] == dec_i0_match_data_2[25]; // @[el2_lib.scala 244:78] + wire _T_850 = _T_846 | _T_849; // @[el2_lib.scala 244:23] + wire _T_852 = &io_trigger_pkt_any_2_tdata2[25:0]; // @[el2_lib.scala 244:36] + wire _T_853 = _T_852 & _T_671; // @[el2_lib.scala 244:41] + wire _T_856 = io_trigger_pkt_any_2_tdata2[26] == dec_i0_match_data_2[26]; // @[el2_lib.scala 244:78] + wire _T_857 = _T_853 | _T_856; // @[el2_lib.scala 244:23] + wire _T_859 = &io_trigger_pkt_any_2_tdata2[26:0]; // @[el2_lib.scala 244:36] + wire _T_860 = _T_859 & _T_671; // @[el2_lib.scala 244:41] + wire _T_863 = io_trigger_pkt_any_2_tdata2[27] == dec_i0_match_data_2[27]; // @[el2_lib.scala 244:78] + wire _T_864 = _T_860 | _T_863; // @[el2_lib.scala 244:23] + wire _T_866 = &io_trigger_pkt_any_2_tdata2[27:0]; // @[el2_lib.scala 244:36] + wire _T_867 = _T_866 & _T_671; // @[el2_lib.scala 244:41] + wire _T_870 = io_trigger_pkt_any_2_tdata2[28] == dec_i0_match_data_2[28]; // @[el2_lib.scala 244:78] + wire _T_871 = _T_867 | _T_870; // @[el2_lib.scala 244:23] + wire _T_873 = &io_trigger_pkt_any_2_tdata2[28:0]; // @[el2_lib.scala 244:36] + wire _T_874 = _T_873 & _T_671; // @[el2_lib.scala 244:41] + wire _T_877 = io_trigger_pkt_any_2_tdata2[29] == dec_i0_match_data_2[29]; // @[el2_lib.scala 244:78] + wire _T_878 = _T_874 | _T_877; // @[el2_lib.scala 244:23] + wire _T_880 = &io_trigger_pkt_any_2_tdata2[29:0]; // @[el2_lib.scala 244:36] + wire _T_881 = _T_880 & _T_671; // @[el2_lib.scala 244:41] + wire _T_884 = io_trigger_pkt_any_2_tdata2[30] == dec_i0_match_data_2[30]; // @[el2_lib.scala 244:78] + wire _T_885 = _T_881 | _T_884; // @[el2_lib.scala 244:23] + wire _T_887 = &io_trigger_pkt_any_2_tdata2[30:0]; // @[el2_lib.scala 244:36] + wire _T_888 = _T_887 & _T_671; // @[el2_lib.scala 244:41] + wire _T_891 = io_trigger_pkt_any_2_tdata2[31] == dec_i0_match_data_2[31]; // @[el2_lib.scala 244:78] + wire _T_892 = _T_888 | _T_891; // @[el2_lib.scala 244:23] + wire [7:0] _T_899 = {_T_724,_T_717,_T_710,_T_703,_T_696,_T_689,_T_682,_T_675}; // @[el2_lib.scala 245:14] + wire [15:0] _T_907 = {_T_780,_T_773,_T_766,_T_759,_T_752,_T_745,_T_738,_T_731,_T_899}; // @[el2_lib.scala 245:14] + wire [7:0] _T_914 = {_T_836,_T_829,_T_822,_T_815,_T_808,_T_801,_T_794,_T_787}; // @[el2_lib.scala 245:14] + wire [31:0] _T_923 = {_T_892,_T_885,_T_878,_T_871,_T_864,_T_857,_T_850,_T_843,_T_914,_T_907}; // @[el2_lib.scala 245:14] + wire [31:0] _GEN_2 = {{31'd0}, _T_666}; // @[el2_dec_trigger.scala 15:109] + wire [31:0] _T_924 = _GEN_2 & _T_923; // @[el2_dec_trigger.scala 15:109] + wire _T_925 = io_trigger_pkt_any_3_execute & io_trigger_pkt_any_3_m; // @[el2_dec_trigger.scala 15:83] + wire _T_928 = &io_trigger_pkt_any_3_tdata2; // @[el2_lib.scala 241:45] + wire _T_929 = ~_T_928; // @[el2_lib.scala 241:39] + wire _T_930 = io_trigger_pkt_any_3_match_pkt & _T_929; // @[el2_lib.scala 241:37] + wire _T_933 = io_trigger_pkt_any_3_tdata2[0] == dec_i0_match_data_3[0]; // @[el2_lib.scala 242:52] + wire _T_934 = _T_930 | _T_933; // @[el2_lib.scala 242:41] + wire _T_936 = &io_trigger_pkt_any_3_tdata2[0]; // @[el2_lib.scala 244:36] + wire _T_937 = _T_936 & _T_930; // @[el2_lib.scala 244:41] + wire _T_940 = io_trigger_pkt_any_3_tdata2[1] == dec_i0_match_data_3[1]; // @[el2_lib.scala 244:78] + wire _T_941 = _T_937 | _T_940; // @[el2_lib.scala 244:23] + wire _T_943 = &io_trigger_pkt_any_3_tdata2[1:0]; // @[el2_lib.scala 244:36] + wire _T_944 = _T_943 & _T_930; // @[el2_lib.scala 244:41] + wire _T_947 = io_trigger_pkt_any_3_tdata2[2] == dec_i0_match_data_3[2]; // @[el2_lib.scala 244:78] + wire _T_948 = _T_944 | _T_947; // @[el2_lib.scala 244:23] + wire _T_950 = &io_trigger_pkt_any_3_tdata2[2:0]; // @[el2_lib.scala 244:36] + wire _T_951 = _T_950 & _T_930; // @[el2_lib.scala 244:41] + wire _T_954 = io_trigger_pkt_any_3_tdata2[3] == dec_i0_match_data_3[3]; // @[el2_lib.scala 244:78] + wire _T_955 = _T_951 | _T_954; // @[el2_lib.scala 244:23] + wire _T_957 = &io_trigger_pkt_any_3_tdata2[3:0]; // @[el2_lib.scala 244:36] + wire _T_958 = _T_957 & _T_930; // @[el2_lib.scala 244:41] + wire _T_961 = io_trigger_pkt_any_3_tdata2[4] == dec_i0_match_data_3[4]; // @[el2_lib.scala 244:78] + wire _T_962 = _T_958 | _T_961; // @[el2_lib.scala 244:23] + wire _T_964 = &io_trigger_pkt_any_3_tdata2[4:0]; // @[el2_lib.scala 244:36] + wire _T_965 = _T_964 & _T_930; // @[el2_lib.scala 244:41] + wire _T_968 = io_trigger_pkt_any_3_tdata2[5] == dec_i0_match_data_3[5]; // @[el2_lib.scala 244:78] + wire _T_969 = _T_965 | _T_968; // @[el2_lib.scala 244:23] + wire _T_971 = &io_trigger_pkt_any_3_tdata2[5:0]; // @[el2_lib.scala 244:36] + wire _T_972 = _T_971 & _T_930; // @[el2_lib.scala 244:41] + wire _T_975 = io_trigger_pkt_any_3_tdata2[6] == dec_i0_match_data_3[6]; // @[el2_lib.scala 244:78] + wire _T_976 = _T_972 | _T_975; // @[el2_lib.scala 244:23] + wire _T_978 = &io_trigger_pkt_any_3_tdata2[6:0]; // @[el2_lib.scala 244:36] + wire _T_979 = _T_978 & _T_930; // @[el2_lib.scala 244:41] + wire _T_982 = io_trigger_pkt_any_3_tdata2[7] == dec_i0_match_data_3[7]; // @[el2_lib.scala 244:78] + wire _T_983 = _T_979 | _T_982; // @[el2_lib.scala 244:23] + wire _T_985 = &io_trigger_pkt_any_3_tdata2[7:0]; // @[el2_lib.scala 244:36] + wire _T_986 = _T_985 & _T_930; // @[el2_lib.scala 244:41] + wire _T_989 = io_trigger_pkt_any_3_tdata2[8] == dec_i0_match_data_3[8]; // @[el2_lib.scala 244:78] + wire _T_990 = _T_986 | _T_989; // @[el2_lib.scala 244:23] + wire _T_992 = &io_trigger_pkt_any_3_tdata2[8:0]; // @[el2_lib.scala 244:36] + wire _T_993 = _T_992 & _T_930; // @[el2_lib.scala 244:41] + wire _T_996 = io_trigger_pkt_any_3_tdata2[9] == dec_i0_match_data_3[9]; // @[el2_lib.scala 244:78] + wire _T_997 = _T_993 | _T_996; // @[el2_lib.scala 244:23] + wire _T_999 = &io_trigger_pkt_any_3_tdata2[9:0]; // @[el2_lib.scala 244:36] + wire _T_1000 = _T_999 & _T_930; // @[el2_lib.scala 244:41] + wire _T_1003 = io_trigger_pkt_any_3_tdata2[10] == dec_i0_match_data_3[10]; // @[el2_lib.scala 244:78] + wire _T_1004 = _T_1000 | _T_1003; // @[el2_lib.scala 244:23] + wire _T_1006 = &io_trigger_pkt_any_3_tdata2[10:0]; // @[el2_lib.scala 244:36] + wire _T_1007 = _T_1006 & _T_930; // @[el2_lib.scala 244:41] + wire _T_1010 = io_trigger_pkt_any_3_tdata2[11] == dec_i0_match_data_3[11]; // @[el2_lib.scala 244:78] + wire _T_1011 = _T_1007 | _T_1010; // @[el2_lib.scala 244:23] + wire _T_1013 = &io_trigger_pkt_any_3_tdata2[11:0]; // @[el2_lib.scala 244:36] + wire _T_1014 = _T_1013 & _T_930; // @[el2_lib.scala 244:41] + wire _T_1017 = io_trigger_pkt_any_3_tdata2[12] == dec_i0_match_data_3[12]; // @[el2_lib.scala 244:78] + wire _T_1018 = _T_1014 | _T_1017; // @[el2_lib.scala 244:23] + wire _T_1020 = &io_trigger_pkt_any_3_tdata2[12:0]; // @[el2_lib.scala 244:36] + wire _T_1021 = _T_1020 & _T_930; // @[el2_lib.scala 244:41] + wire _T_1024 = io_trigger_pkt_any_3_tdata2[13] == dec_i0_match_data_3[13]; // @[el2_lib.scala 244:78] + wire _T_1025 = _T_1021 | _T_1024; // @[el2_lib.scala 244:23] + wire _T_1027 = &io_trigger_pkt_any_3_tdata2[13:0]; // @[el2_lib.scala 244:36] + wire _T_1028 = _T_1027 & _T_930; // @[el2_lib.scala 244:41] + wire _T_1031 = io_trigger_pkt_any_3_tdata2[14] == dec_i0_match_data_3[14]; // @[el2_lib.scala 244:78] + wire _T_1032 = _T_1028 | _T_1031; // @[el2_lib.scala 244:23] + wire _T_1034 = &io_trigger_pkt_any_3_tdata2[14:0]; // @[el2_lib.scala 244:36] + wire _T_1035 = _T_1034 & _T_930; // @[el2_lib.scala 244:41] + wire _T_1038 = io_trigger_pkt_any_3_tdata2[15] == dec_i0_match_data_3[15]; // @[el2_lib.scala 244:78] + wire _T_1039 = _T_1035 | _T_1038; // @[el2_lib.scala 244:23] + wire _T_1041 = &io_trigger_pkt_any_3_tdata2[15:0]; // @[el2_lib.scala 244:36] + wire _T_1042 = _T_1041 & _T_930; // @[el2_lib.scala 244:41] + wire _T_1045 = io_trigger_pkt_any_3_tdata2[16] == dec_i0_match_data_3[16]; // @[el2_lib.scala 244:78] + wire _T_1046 = _T_1042 | _T_1045; // @[el2_lib.scala 244:23] + wire _T_1048 = &io_trigger_pkt_any_3_tdata2[16:0]; // @[el2_lib.scala 244:36] + wire _T_1049 = _T_1048 & _T_930; // @[el2_lib.scala 244:41] + wire _T_1052 = io_trigger_pkt_any_3_tdata2[17] == dec_i0_match_data_3[17]; // @[el2_lib.scala 244:78] + wire _T_1053 = _T_1049 | _T_1052; // @[el2_lib.scala 244:23] + wire _T_1055 = &io_trigger_pkt_any_3_tdata2[17:0]; // @[el2_lib.scala 244:36] + wire _T_1056 = _T_1055 & _T_930; // @[el2_lib.scala 244:41] + wire _T_1059 = io_trigger_pkt_any_3_tdata2[18] == dec_i0_match_data_3[18]; // @[el2_lib.scala 244:78] + wire _T_1060 = _T_1056 | _T_1059; // @[el2_lib.scala 244:23] + wire _T_1062 = &io_trigger_pkt_any_3_tdata2[18:0]; // @[el2_lib.scala 244:36] + wire _T_1063 = _T_1062 & _T_930; // @[el2_lib.scala 244:41] + wire _T_1066 = io_trigger_pkt_any_3_tdata2[19] == dec_i0_match_data_3[19]; // @[el2_lib.scala 244:78] + wire _T_1067 = _T_1063 | _T_1066; // @[el2_lib.scala 244:23] + wire _T_1069 = &io_trigger_pkt_any_3_tdata2[19:0]; // @[el2_lib.scala 244:36] + wire _T_1070 = _T_1069 & _T_930; // @[el2_lib.scala 244:41] + wire _T_1073 = io_trigger_pkt_any_3_tdata2[20] == dec_i0_match_data_3[20]; // @[el2_lib.scala 244:78] + wire _T_1074 = _T_1070 | _T_1073; // @[el2_lib.scala 244:23] + wire _T_1076 = &io_trigger_pkt_any_3_tdata2[20:0]; // @[el2_lib.scala 244:36] + wire _T_1077 = _T_1076 & _T_930; // @[el2_lib.scala 244:41] + wire _T_1080 = io_trigger_pkt_any_3_tdata2[21] == dec_i0_match_data_3[21]; // @[el2_lib.scala 244:78] + wire _T_1081 = _T_1077 | _T_1080; // @[el2_lib.scala 244:23] + wire _T_1083 = &io_trigger_pkt_any_3_tdata2[21:0]; // @[el2_lib.scala 244:36] + wire _T_1084 = _T_1083 & _T_930; // @[el2_lib.scala 244:41] + wire _T_1087 = io_trigger_pkt_any_3_tdata2[22] == dec_i0_match_data_3[22]; // @[el2_lib.scala 244:78] + wire _T_1088 = _T_1084 | _T_1087; // @[el2_lib.scala 244:23] + wire _T_1090 = &io_trigger_pkt_any_3_tdata2[22:0]; // @[el2_lib.scala 244:36] + wire _T_1091 = _T_1090 & _T_930; // @[el2_lib.scala 244:41] + wire _T_1094 = io_trigger_pkt_any_3_tdata2[23] == dec_i0_match_data_3[23]; // @[el2_lib.scala 244:78] + wire _T_1095 = _T_1091 | _T_1094; // @[el2_lib.scala 244:23] + wire _T_1097 = &io_trigger_pkt_any_3_tdata2[23:0]; // @[el2_lib.scala 244:36] + wire _T_1098 = _T_1097 & _T_930; // @[el2_lib.scala 244:41] + wire _T_1101 = io_trigger_pkt_any_3_tdata2[24] == dec_i0_match_data_3[24]; // @[el2_lib.scala 244:78] + wire _T_1102 = _T_1098 | _T_1101; // @[el2_lib.scala 244:23] + wire _T_1104 = &io_trigger_pkt_any_3_tdata2[24:0]; // @[el2_lib.scala 244:36] + wire _T_1105 = _T_1104 & _T_930; // @[el2_lib.scala 244:41] + wire _T_1108 = io_trigger_pkt_any_3_tdata2[25] == dec_i0_match_data_3[25]; // @[el2_lib.scala 244:78] + wire _T_1109 = _T_1105 | _T_1108; // @[el2_lib.scala 244:23] + wire _T_1111 = &io_trigger_pkt_any_3_tdata2[25:0]; // @[el2_lib.scala 244:36] + wire _T_1112 = _T_1111 & _T_930; // @[el2_lib.scala 244:41] + wire _T_1115 = io_trigger_pkt_any_3_tdata2[26] == dec_i0_match_data_3[26]; // @[el2_lib.scala 244:78] + wire _T_1116 = _T_1112 | _T_1115; // @[el2_lib.scala 244:23] + wire _T_1118 = &io_trigger_pkt_any_3_tdata2[26:0]; // @[el2_lib.scala 244:36] + wire _T_1119 = _T_1118 & _T_930; // @[el2_lib.scala 244:41] + wire _T_1122 = io_trigger_pkt_any_3_tdata2[27] == dec_i0_match_data_3[27]; // @[el2_lib.scala 244:78] + wire _T_1123 = _T_1119 | _T_1122; // @[el2_lib.scala 244:23] + wire _T_1125 = &io_trigger_pkt_any_3_tdata2[27:0]; // @[el2_lib.scala 244:36] + wire _T_1126 = _T_1125 & _T_930; // @[el2_lib.scala 244:41] + wire _T_1129 = io_trigger_pkt_any_3_tdata2[28] == dec_i0_match_data_3[28]; // @[el2_lib.scala 244:78] + wire _T_1130 = _T_1126 | _T_1129; // @[el2_lib.scala 244:23] + wire _T_1132 = &io_trigger_pkt_any_3_tdata2[28:0]; // @[el2_lib.scala 244:36] + wire _T_1133 = _T_1132 & _T_930; // @[el2_lib.scala 244:41] + wire _T_1136 = io_trigger_pkt_any_3_tdata2[29] == dec_i0_match_data_3[29]; // @[el2_lib.scala 244:78] + wire _T_1137 = _T_1133 | _T_1136; // @[el2_lib.scala 244:23] + wire _T_1139 = &io_trigger_pkt_any_3_tdata2[29:0]; // @[el2_lib.scala 244:36] + wire _T_1140 = _T_1139 & _T_930; // @[el2_lib.scala 244:41] + wire _T_1143 = io_trigger_pkt_any_3_tdata2[30] == dec_i0_match_data_3[30]; // @[el2_lib.scala 244:78] + wire _T_1144 = _T_1140 | _T_1143; // @[el2_lib.scala 244:23] + wire _T_1146 = &io_trigger_pkt_any_3_tdata2[30:0]; // @[el2_lib.scala 244:36] + wire _T_1147 = _T_1146 & _T_930; // @[el2_lib.scala 244:41] + wire _T_1150 = io_trigger_pkt_any_3_tdata2[31] == dec_i0_match_data_3[31]; // @[el2_lib.scala 244:78] + wire _T_1151 = _T_1147 | _T_1150; // @[el2_lib.scala 244:23] + wire [7:0] _T_1158 = {_T_983,_T_976,_T_969,_T_962,_T_955,_T_948,_T_941,_T_934}; // @[el2_lib.scala 245:14] + wire [15:0] _T_1166 = {_T_1039,_T_1032,_T_1025,_T_1018,_T_1011,_T_1004,_T_997,_T_990,_T_1158}; // @[el2_lib.scala 245:14] + wire [7:0] _T_1173 = {_T_1095,_T_1088,_T_1081,_T_1074,_T_1067,_T_1060,_T_1053,_T_1046}; // @[el2_lib.scala 245:14] + wire [31:0] _T_1182 = {_T_1151,_T_1144,_T_1137,_T_1130,_T_1123,_T_1116,_T_1109,_T_1102,_T_1173,_T_1166}; // @[el2_lib.scala 245:14] + wire [31:0] _GEN_3 = {{31'd0}, _T_925}; // @[el2_dec_trigger.scala 15:109] + wire [31:0] _T_1183 = _GEN_3 & _T_1182; // @[el2_dec_trigger.scala 15:109] + wire [127:0] _T_1186 = {_T_1183,_T_924,_T_665,_T_406}; // @[Cat.scala 29:58] + assign io_dec_i0_trigger_match_d = _T_1186[3:0]; // @[el2_dec_trigger.scala 15:29] endmodule diff --git a/el2_dma_ctrl.anno.json b/el2_dma_ctrl.anno.json new file mode 100644 index 00000000..1f336a93 --- /dev/null +++ b/el2_dma_ctrl.anno.json @@ -0,0 +1,115 @@ +[ + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_dccm_stall_any", + "sources":[ + "~el2_dma_ctrl|el2_dma_ctrl>io_dec_tlu_dma_qos_prty", + "~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_pmu_any_write", + "sources":[ + "~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write", + "~el2_dma_ctrl|el2_dma_ctrl>io_dma_dccm_req", + "~el2_dma_ctrl|el2_dma_ctrl>io_dma_iccm_req", + "~el2_dma_ctrl|el2_dma_ctrl>io_dccm_ready", + "~el2_dma_ctrl|el2_dma_ctrl>io_iccm_ready" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_pmu_dccm_write", + "sources":[ + "~el2_dma_ctrl|el2_dma_ctrl>io_dma_dccm_req", + "~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write", + "~el2_dma_ctrl|el2_dma_ctrl>io_dccm_ready" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_iccm_stall_any", + "sources":[ + "~el2_dma_ctrl|el2_dma_ctrl>io_dec_tlu_dma_qos_prty", + "~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_dccm_req", + "sources":[ + "~el2_dma_ctrl|el2_dma_ctrl>io_dccm_ready", + "~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_addr", + "sources":[ + "~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_pmu_any_read", + "sources":[ + "~el2_dma_ctrl|el2_dma_ctrl>io_dma_dccm_req", + "~el2_dma_ctrl|el2_dma_ctrl>io_dma_iccm_req", + "~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write", + "~el2_dma_ctrl|el2_dma_ctrl>io_dccm_ready", + "~el2_dma_ctrl|el2_dma_ctrl>io_iccm_ready" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_pmu_dccm_read", + "sources":[ + "~el2_dma_ctrl|el2_dma_ctrl>io_dma_dccm_req", + "~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write", + "~el2_dma_ctrl|el2_dma_ctrl>io_dccm_ready" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_sz", + "sources":[ + "~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_iccm_req", + "sources":[ + "~el2_dma_ctrl|el2_dma_ctrl>io_iccm_ready", + "~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write" + ] + }, + { + "class":"logger.LogLevelAnnotation", + "globalLogLevel":{ + + } + }, + { + "class":"firrtl.EmitCircuitAnnotation", + "emitter":"firrtl.VerilogEmitter" + }, + { + "class":"firrtl.transforms.BlackBoxResourceAnno", + "target":"el2_dma_ctrl.gated_latch", + "resourceId":"/vsrc/gated_latch.v" + }, + { + "class":"firrtl.options.TargetDirAnnotation", + "directory":"." + }, + { + "class":"firrtl.options.OutputAnnotationFileAnnotation", + "file":"el2_dma_ctrl" + }, + { + "class":"firrtl.transforms.BlackBoxTargetDirAnno", + "targetDir":"." + } +] \ No newline at end of file diff --git a/el2_dma_ctrl.fir b/el2_dma_ctrl.fir new file mode 100644 index 00000000..66bcd7d2 --- /dev/null +++ b/el2_dma_ctrl.fir @@ -0,0 +1,2267 @@ +;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 +circuit el2_dma_ctrl : + extmodule gated_latch : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_1 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_1 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_1 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_2 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_2 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_2 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_3 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_3 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_3 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_4 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_4 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_4 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_5 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_5 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_5 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_6 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_6 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_6 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_7 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_7 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_7 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_8 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_8 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_8 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_9 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_9 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_9 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_10 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_10 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_10 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_11 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_11 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_11 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_12 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_12 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_12 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_13 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_13 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_13 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_14 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_14 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_14 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_15 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_15 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_15 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + module el2_dma_ctrl : + input clock : Clock + input reset : AsyncReset + output io : {flip free_clk : Clock, flip dma_bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip scan_mode : UInt<1>, flip dbg_cmd_addr : UInt<32>, flip dbg_cmd_wrdata : UInt<32>, flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_size : UInt<2>, flip dbg_dma_bubble : UInt<1>, dma_dbg_ready : UInt<1>, dma_dbg_cmd_done : UInt<1>, dma_dbg_cmd_fail : UInt<1>, dma_dbg_rddata : UInt<32>, dma_dccm_req : UInt<1>, dma_iccm_req : UInt<1>, dma_mem_tag : UInt<3>, dma_mem_addr : UInt<32>, dma_mem_sz : UInt<3>, dma_mem_write : UInt<1>, dma_mem_wdata : UInt<64>, flip dccm_dma_rvalid : UInt<1>, flip dccm_dma_ecc_error : UInt<1>, flip dccm_dma_rtag : UInt<3>, flip dccm_dma_rdata : UInt<64>, flip iccm_dma_rvalid : UInt<1>, flip iccm_dma_ecc_error : UInt<1>, flip iccm_dma_rtag : UInt<3>, flip iccm_dma_rdata : UInt<64>, dma_dccm_stall_any : UInt<1>, dma_iccm_stall_any : UInt<1>, flip dccm_ready : UInt<1>, flip iccm_ready : UInt<1>, flip dec_tlu_dma_qos_prty : UInt<3>, dma_pmu_dccm_read : UInt<1>, dma_pmu_dccm_write : UInt<1>, dma_pmu_any_read : UInt<1>, dma_pmu_any_write : UInt<1>, flip dma_axi_awvalid : UInt<1>, dma_axi_awready : UInt<1>, flip dma_axi_awid : UInt<1>, flip dma_axi_awaddr : UInt<32>, flip dma_axi_awsize : UInt<3>, flip dma_axi_wvalid : UInt<1>, dma_axi_wready : UInt<1>, flip dma_axi_wdata : UInt<64>, flip dma_axi_wstrb : UInt<8>, dma_axi_bvalid : UInt<1>, flip dma_axi_bready : UInt<1>, dma_axi_bresp : UInt<2>, dma_axi_bid : UInt<1>, flip dma_axi_arvalid : UInt<1>, dma_axi_arready : UInt<1>, flip dma_axi_arid : UInt<1>, flip dma_axi_araddr : UInt<32>, flip dma_axi_arsize : UInt<3>, dma_axi_rvalid : UInt<1>, flip dma_axi_rready : UInt<1>, dma_axi_rid : UInt<1>, dma_axi_rdata : UInt<64>, dma_axi_rresp : UInt<2>, dma_axi_rlast : UInt<1>} + + wire fifo_error : UInt<2>[5] @[el2_dma_ctrl.scala 92:24] + wire fifo_error_bus : UInt<5> + fifo_error_bus <= UInt<1>("h00") + wire fifo_done : UInt<5> + fifo_done <= UInt<1>("h00") + wire fifo_addr : UInt<32>[5] @[el2_dma_ctrl.scala 98:23] + wire fifo_sz : UInt<3>[5] @[el2_dma_ctrl.scala 100:21] + wire fifo_byteen : UInt<8>[5] @[el2_dma_ctrl.scala 102:25] + wire fifo_data : UInt<64>[5] @[el2_dma_ctrl.scala 104:23] + wire fifo_tag : UInt<1>[5] @[el2_dma_ctrl.scala 106:22] + wire fifo_mid : UInt<1>[5] @[el2_dma_ctrl.scala 108:22] + wire fifo_prty : UInt<2>[5] @[el2_dma_ctrl.scala 110:23] + wire fifo_error_en : UInt<5> + fifo_error_en <= UInt<1>("h00") + wire fifo_error_in : UInt<2>[5] @[el2_dma_ctrl.scala 114:27] + wire fifo_data_in : UInt<64>[5] @[el2_dma_ctrl.scala 116:26] + wire RspPtr : UInt<3> + RspPtr <= UInt<1>("h00") + wire WrPtr : UInt<3> + WrPtr <= UInt<1>("h00") + wire RdPtr : UInt<3> + RdPtr <= UInt<1>("h00") + wire NxtRspPtr : UInt<3> + NxtRspPtr <= UInt<1>("h00") + wire NxtWrPtr : UInt<3> + NxtWrPtr <= UInt<1>("h00") + wire NxtRdPtr : UInt<3> + NxtRdPtr <= UInt<1>("h00") + wire dma_dbg_cmd_error : UInt<1> + dma_dbg_cmd_error <= UInt<1>("h00") + wire dma_dbg_cmd_done_q : UInt<1> + dma_dbg_cmd_done_q <= UInt<1>("h00") + wire fifo_empty : UInt<1> + fifo_empty <= UInt<1>("h00") + wire dma_address_error : UInt<1> + dma_address_error <= UInt<1>("h00") + wire dma_alignment_error : UInt<1> + dma_alignment_error <= UInt<1>("h00") + wire num_fifo_vld : UInt<4> + num_fifo_vld <= UInt<1>("h00") + wire dma_mem_req : UInt<1> + dma_mem_req <= UInt<1>("h00") + wire dma_mem_addr_int : UInt<32> + dma_mem_addr_int <= UInt<1>("h00") + wire dma_mem_sz_int : UInt<3> + dma_mem_sz_int <= UInt<1>("h00") + wire dma_mem_byteen : UInt<8> + dma_mem_byteen <= UInt<1>("h00") + wire dma_nack_count : UInt<3> + dma_nack_count <= UInt<1>("h00") + wire dma_nack_count_csr : UInt<3> + dma_nack_count_csr <= UInt<1>("h00") + wire bus_rsp_valid : UInt<1> + bus_rsp_valid <= UInt<1>("h00") + wire bus_rsp_sent : UInt<1> + bus_rsp_sent <= UInt<1>("h00") + wire bus_cmd_valid : UInt<1> + bus_cmd_valid <= UInt<1>("h00") + wire axi_mstr_prty_en : UInt<1> + axi_mstr_prty_en <= UInt<1>("h00") + wire bus_cmd_write : UInt<1> + bus_cmd_write <= UInt<1>("h00") + wire bus_cmd_posted_write : UInt<1> + bus_cmd_posted_write <= UInt<1>("h00") + wire bus_cmd_byteen : UInt<8> + bus_cmd_byteen <= UInt<1>("h00") + wire bus_cmd_sz : UInt<3> + bus_cmd_sz <= UInt<1>("h00") + wire bus_cmd_addr : UInt<32> + bus_cmd_addr <= UInt<1>("h00") + wire bus_cmd_wdata : UInt<64> + bus_cmd_wdata <= UInt<1>("h00") + wire bus_cmd_tag : UInt<1> + bus_cmd_tag <= UInt<1>("h00") + wire bus_cmd_mid : UInt<1> + bus_cmd_mid <= UInt<1>("h00") + wire bus_cmd_prty : UInt<2> + bus_cmd_prty <= UInt<1>("h00") + wire bus_posted_write_done : UInt<1> + bus_posted_write_done <= UInt<1>("h00") + wire fifo_full : UInt<1> + fifo_full <= UInt<1>("h00") + wire dbg_dma_bubble_bus : UInt<1> + dbg_dma_bubble_bus <= UInt<1>("h00") + wire axi_mstr_priority : UInt<1> + axi_mstr_priority <= UInt<1>("h00") + wire axi_mstr_sel : UInt<1> + axi_mstr_sel <= UInt<1>("h00") + wire axi_rsp_sent : UInt<1> + axi_rsp_sent <= UInt<1>("h00") + wire fifo_cmd_en : UInt<5> + fifo_cmd_en <= UInt<1>("h00") + wire fifo_data_en : UInt<5> + fifo_data_en <= UInt<1>("h00") + wire fifo_pend_en : UInt<5> + fifo_pend_en <= UInt<1>("h00") + wire fifo_error_bus_en : UInt<5> + fifo_error_bus_en <= UInt<1>("h00") + wire fifo_done_en : UInt<5> + fifo_done_en <= UInt<1>("h00") + wire fifo_done_bus_en : UInt<5> + fifo_done_bus_en <= UInt<1>("h00") + wire fifo_reset : UInt<5> + fifo_reset <= UInt<1>("h00") + wire fifo_valid : UInt<5> + fifo_valid <= UInt<1>("h00") + wire fifo_rpend : UInt<5> + fifo_rpend <= UInt<1>("h00") + wire fifo_done_bus : UInt<5> + fifo_done_bus <= UInt<1>("h00") + wire fifo_write : UInt<5> + fifo_write <= UInt<1>("h00") + wire fifo_posted_write : UInt<5> + fifo_posted_write <= UInt<1>("h00") + wire fifo_dbg : UInt<5> + fifo_dbg <= UInt<1>("h00") + wire wrbuf_vld : UInt<1> + wrbuf_vld <= UInt<1>("h00") + wire wrbuf_data_vld : UInt<1> + wrbuf_data_vld <= UInt<1>("h00") + wire rdbuf_vld : UInt<1> + rdbuf_vld <= UInt<1>("h00") + wire dma_free_clk : Clock @[el2_dma_ctrl.scala 224:26] + wire dma_bus_clk : Clock @[el2_dma_ctrl.scala 226:25] + wire dma_buffer_c1_clk : Clock @[el2_dma_ctrl.scala 228:31] + wire fifo_byteen_in : UInt<8> + fifo_byteen_in <= UInt<1>("h00") + node _T = bits(dma_mem_addr_int, 31, 0) @[el2_dma_ctrl.scala 237:95] + node _T_1 = bits(_T, 31, 28) @[el2_lib.scala 496:27] + node dma_mem_addr_in_dccm_region_nc = eq(_T_1, UInt<4>("h0f")) @[el2_lib.scala 496:49] + wire dma_mem_addr_in_dccm : UInt<1> @[el2_lib.scala 497:26] + node _T_2 = bits(_T, 31, 16) @[el2_lib.scala 501:24] + node _T_3 = eq(_T_2, UInt<16>("h0f004")) @[el2_lib.scala 501:39] + dma_mem_addr_in_dccm <= _T_3 @[el2_lib.scala 501:16] + node _T_4 = bits(dma_mem_addr_int, 31, 0) @[el2_dma_ctrl.scala 241:93] + node _T_5 = bits(_T_4, 31, 28) @[el2_lib.scala 496:27] + node dma_mem_addr_in_pic_region_nc = eq(_T_5, UInt<4>("h0f")) @[el2_lib.scala 496:49] + wire dma_mem_addr_in_pic : UInt<1> @[el2_lib.scala 497:26] + node _T_6 = bits(_T_4, 31, 15) @[el2_lib.scala 501:24] + node _T_7 = eq(_T_6, UInt<17>("h01e018")) @[el2_lib.scala 501:39] + dma_mem_addr_in_pic <= _T_7 @[el2_lib.scala 501:16] + node _T_8 = bits(dma_mem_addr_int, 31, 0) @[el2_dma_ctrl.scala 245:111] + node _T_9 = bits(_T_8, 31, 28) @[el2_lib.scala 496:27] + node dma_mem_addr_in_iccm_region_nc = eq(_T_9, UInt<4>("h0e")) @[el2_lib.scala 496:49] + wire dma_mem_addr_in_iccm : UInt<1> @[el2_lib.scala 497:26] + node _T_10 = bits(_T_8, 31, 16) @[el2_lib.scala 501:24] + node _T_11 = eq(_T_10, UInt<16>("h0ee00")) @[el2_lib.scala 501:39] + dma_mem_addr_in_iccm <= _T_11 @[el2_lib.scala 501:16] + node _T_12 = bits(io.dbg_cmd_valid, 0, 0) @[el2_dma_ctrl.scala 249:51] + node _T_13 = bits(io.dbg_cmd_addr, 31, 0) @[el2_dma_ctrl.scala 249:74] + node _T_14 = bits(bus_cmd_addr, 31, 0) @[el2_dma_ctrl.scala 249:94] + node fifo_addr_in = mux(_T_12, _T_13, _T_14) @[el2_dma_ctrl.scala 249:33] + node _T_15 = bits(io.dbg_cmd_valid, 0, 0) @[el2_dma_ctrl.scala 251:52] + node _T_16 = bits(io.dbg_cmd_addr, 2, 2) @[el2_dma_ctrl.scala 251:93] + node _T_17 = mul(UInt<3>("h04"), _T_16) @[el2_dma_ctrl.scala 251:76] + node _T_18 = dshl(UInt<4>("h0f"), _T_17) @[el2_dma_ctrl.scala 251:68] + node _T_19 = bits(bus_cmd_byteen, 7, 0) @[el2_dma_ctrl.scala 251:113] + node _T_20 = mux(_T_15, _T_18, _T_19) @[el2_dma_ctrl.scala 251:34] + fifo_byteen_in <= _T_20 @[el2_dma_ctrl.scala 251:28] + node _T_21 = bits(io.dbg_cmd_valid, 0, 0) @[el2_dma_ctrl.scala 253:51] + node _T_22 = bits(io.dbg_cmd_size, 1, 0) @[el2_dma_ctrl.scala 253:83] + node _T_23 = cat(UInt<1>("h00"), _T_22) @[Cat.scala 29:58] + node _T_24 = bits(bus_cmd_sz, 2, 0) @[el2_dma_ctrl.scala 253:101] + node fifo_sz_in = mux(_T_21, _T_23, _T_24) @[el2_dma_ctrl.scala 253:33] + node _T_25 = bits(io.dbg_cmd_valid, 0, 0) @[el2_dma_ctrl.scala 255:51] + node fifo_write_in = mux(_T_25, io.dbg_cmd_write, bus_cmd_write) @[el2_dma_ctrl.scala 255:33] + node _T_26 = eq(io.dbg_cmd_valid, UInt<1>("h00")) @[el2_dma_ctrl.scala 257:30] + node fifo_posted_write_in = and(_T_26, bus_cmd_posted_write) @[el2_dma_ctrl.scala 257:48] + node _T_27 = bits(axi_mstr_prty_en, 0, 0) @[el2_dma_ctrl.scala 262:73] + node _T_28 = and(_T_27, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 262:80] + node _T_29 = bits(io.dbg_cmd_type, 1, 1) @[el2_dma_ctrl.scala 262:138] + node _T_30 = bits(_T_29, 0, 0) @[el2_dma_ctrl.scala 262:142] + node _T_31 = and(io.dbg_cmd_valid, _T_30) @[el2_dma_ctrl.scala 262:121] + node _T_32 = or(_T_28, _T_31) @[el2_dma_ctrl.scala 262:101] + node _T_33 = eq(UInt<1>("h00"), WrPtr) @[el2_dma_ctrl.scala 262:158] + node _T_34 = and(_T_32, _T_33) @[el2_dma_ctrl.scala 262:151] + node _T_35 = bits(axi_mstr_prty_en, 0, 0) @[el2_dma_ctrl.scala 262:73] + node _T_36 = and(_T_35, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 262:80] + node _T_37 = bits(io.dbg_cmd_type, 1, 1) @[el2_dma_ctrl.scala 262:138] + node _T_38 = bits(_T_37, 0, 0) @[el2_dma_ctrl.scala 262:142] + node _T_39 = and(io.dbg_cmd_valid, _T_38) @[el2_dma_ctrl.scala 262:121] + node _T_40 = or(_T_36, _T_39) @[el2_dma_ctrl.scala 262:101] + node _T_41 = eq(UInt<1>("h01"), WrPtr) @[el2_dma_ctrl.scala 262:158] + node _T_42 = and(_T_40, _T_41) @[el2_dma_ctrl.scala 262:151] + node _T_43 = bits(axi_mstr_prty_en, 0, 0) @[el2_dma_ctrl.scala 262:73] + node _T_44 = and(_T_43, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 262:80] + node _T_45 = bits(io.dbg_cmd_type, 1, 1) @[el2_dma_ctrl.scala 262:138] + node _T_46 = bits(_T_45, 0, 0) @[el2_dma_ctrl.scala 262:142] + node _T_47 = and(io.dbg_cmd_valid, _T_46) @[el2_dma_ctrl.scala 262:121] + node _T_48 = or(_T_44, _T_47) @[el2_dma_ctrl.scala 262:101] + node _T_49 = eq(UInt<2>("h02"), WrPtr) @[el2_dma_ctrl.scala 262:158] + node _T_50 = and(_T_48, _T_49) @[el2_dma_ctrl.scala 262:151] + node _T_51 = bits(axi_mstr_prty_en, 0, 0) @[el2_dma_ctrl.scala 262:73] + node _T_52 = and(_T_51, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 262:80] + node _T_53 = bits(io.dbg_cmd_type, 1, 1) @[el2_dma_ctrl.scala 262:138] + node _T_54 = bits(_T_53, 0, 0) @[el2_dma_ctrl.scala 262:142] + node _T_55 = and(io.dbg_cmd_valid, _T_54) @[el2_dma_ctrl.scala 262:121] + node _T_56 = or(_T_52, _T_55) @[el2_dma_ctrl.scala 262:101] + node _T_57 = eq(UInt<2>("h03"), WrPtr) @[el2_dma_ctrl.scala 262:158] + node _T_58 = and(_T_56, _T_57) @[el2_dma_ctrl.scala 262:151] + node _T_59 = bits(axi_mstr_prty_en, 0, 0) @[el2_dma_ctrl.scala 262:73] + node _T_60 = and(_T_59, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 262:80] + node _T_61 = bits(io.dbg_cmd_type, 1, 1) @[el2_dma_ctrl.scala 262:138] + node _T_62 = bits(_T_61, 0, 0) @[el2_dma_ctrl.scala 262:142] + node _T_63 = and(io.dbg_cmd_valid, _T_62) @[el2_dma_ctrl.scala 262:121] + node _T_64 = or(_T_60, _T_63) @[el2_dma_ctrl.scala 262:101] + node _T_65 = eq(UInt<3>("h04"), WrPtr) @[el2_dma_ctrl.scala 262:158] + node _T_66 = and(_T_64, _T_65) @[el2_dma_ctrl.scala 262:151] + node _T_67 = cat(_T_66, _T_58) @[Cat.scala 29:58] + node _T_68 = cat(_T_67, _T_50) @[Cat.scala 29:58] + node _T_69 = cat(_T_68, _T_42) @[Cat.scala 29:58] + node _T_70 = cat(_T_69, _T_34) @[Cat.scala 29:58] + fifo_cmd_en <= _T_70 @[el2_dma_ctrl.scala 262:21] + node _T_71 = and(axi_mstr_prty_en, fifo_write_in) @[el2_dma_ctrl.scala 264:73] + node _T_72 = and(_T_71, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 264:89] + node _T_73 = bits(io.dbg_cmd_type, 1, 1) @[el2_dma_ctrl.scala 264:147] + node _T_74 = and(io.dbg_cmd_valid, _T_73) @[el2_dma_ctrl.scala 264:130] + node _T_75 = and(_T_74, io.dbg_cmd_write) @[el2_dma_ctrl.scala 264:151] + node _T_76 = or(_T_72, _T_75) @[el2_dma_ctrl.scala 264:110] + node _T_77 = eq(UInt<1>("h00"), WrPtr) @[el2_dma_ctrl.scala 264:179] + node _T_78 = and(_T_76, _T_77) @[el2_dma_ctrl.scala 264:172] + node _T_79 = or(dma_address_error, dma_alignment_error) @[el2_dma_ctrl.scala 264:213] + node _T_80 = eq(UInt<1>("h00"), RdPtr) @[el2_dma_ctrl.scala 264:243] + node _T_81 = and(_T_79, _T_80) @[el2_dma_ctrl.scala 264:236] + node _T_82 = or(_T_78, _T_81) @[el2_dma_ctrl.scala 264:191] + node _T_83 = eq(UInt<1>("h00"), io.dccm_dma_rtag) @[el2_dma_ctrl.scala 264:284] + node _T_84 = and(io.dccm_dma_rvalid, _T_83) @[el2_dma_ctrl.scala 264:277] + node _T_85 = or(_T_82, _T_84) @[el2_dma_ctrl.scala 264:255] + node _T_86 = eq(UInt<1>("h00"), io.iccm_dma_rtag) @[el2_dma_ctrl.scala 264:336] + node _T_87 = and(io.iccm_dma_rvalid, _T_86) @[el2_dma_ctrl.scala 264:329] + node _T_88 = or(_T_85, _T_87) @[el2_dma_ctrl.scala 264:307] + node _T_89 = and(axi_mstr_prty_en, fifo_write_in) @[el2_dma_ctrl.scala 264:73] + node _T_90 = and(_T_89, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 264:89] + node _T_91 = bits(io.dbg_cmd_type, 1, 1) @[el2_dma_ctrl.scala 264:147] + node _T_92 = and(io.dbg_cmd_valid, _T_91) @[el2_dma_ctrl.scala 264:130] + node _T_93 = and(_T_92, io.dbg_cmd_write) @[el2_dma_ctrl.scala 264:151] + node _T_94 = or(_T_90, _T_93) @[el2_dma_ctrl.scala 264:110] + node _T_95 = eq(UInt<1>("h01"), WrPtr) @[el2_dma_ctrl.scala 264:179] + node _T_96 = and(_T_94, _T_95) @[el2_dma_ctrl.scala 264:172] + node _T_97 = or(dma_address_error, dma_alignment_error) @[el2_dma_ctrl.scala 264:213] + node _T_98 = eq(UInt<1>("h01"), RdPtr) @[el2_dma_ctrl.scala 264:243] + node _T_99 = and(_T_97, _T_98) @[el2_dma_ctrl.scala 264:236] + node _T_100 = or(_T_96, _T_99) @[el2_dma_ctrl.scala 264:191] + node _T_101 = eq(UInt<1>("h01"), io.dccm_dma_rtag) @[el2_dma_ctrl.scala 264:284] + node _T_102 = and(io.dccm_dma_rvalid, _T_101) @[el2_dma_ctrl.scala 264:277] + node _T_103 = or(_T_100, _T_102) @[el2_dma_ctrl.scala 264:255] + node _T_104 = eq(UInt<1>("h01"), io.iccm_dma_rtag) @[el2_dma_ctrl.scala 264:336] + node _T_105 = and(io.iccm_dma_rvalid, _T_104) @[el2_dma_ctrl.scala 264:329] + node _T_106 = or(_T_103, _T_105) @[el2_dma_ctrl.scala 264:307] + node _T_107 = and(axi_mstr_prty_en, fifo_write_in) @[el2_dma_ctrl.scala 264:73] + node _T_108 = and(_T_107, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 264:89] + node _T_109 = bits(io.dbg_cmd_type, 1, 1) @[el2_dma_ctrl.scala 264:147] + node _T_110 = and(io.dbg_cmd_valid, _T_109) @[el2_dma_ctrl.scala 264:130] + node _T_111 = and(_T_110, io.dbg_cmd_write) @[el2_dma_ctrl.scala 264:151] + node _T_112 = or(_T_108, _T_111) @[el2_dma_ctrl.scala 264:110] + node _T_113 = eq(UInt<2>("h02"), WrPtr) @[el2_dma_ctrl.scala 264:179] + node _T_114 = and(_T_112, _T_113) @[el2_dma_ctrl.scala 264:172] + node _T_115 = or(dma_address_error, dma_alignment_error) @[el2_dma_ctrl.scala 264:213] + node _T_116 = eq(UInt<2>("h02"), RdPtr) @[el2_dma_ctrl.scala 264:243] + node _T_117 = and(_T_115, _T_116) @[el2_dma_ctrl.scala 264:236] + node _T_118 = or(_T_114, _T_117) @[el2_dma_ctrl.scala 264:191] + node _T_119 = eq(UInt<2>("h02"), io.dccm_dma_rtag) @[el2_dma_ctrl.scala 264:284] + node _T_120 = and(io.dccm_dma_rvalid, _T_119) @[el2_dma_ctrl.scala 264:277] + node _T_121 = or(_T_118, _T_120) @[el2_dma_ctrl.scala 264:255] + node _T_122 = eq(UInt<2>("h02"), io.iccm_dma_rtag) @[el2_dma_ctrl.scala 264:336] + node _T_123 = and(io.iccm_dma_rvalid, _T_122) @[el2_dma_ctrl.scala 264:329] + node _T_124 = or(_T_121, _T_123) @[el2_dma_ctrl.scala 264:307] + node _T_125 = and(axi_mstr_prty_en, fifo_write_in) @[el2_dma_ctrl.scala 264:73] + node _T_126 = and(_T_125, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 264:89] + node _T_127 = bits(io.dbg_cmd_type, 1, 1) @[el2_dma_ctrl.scala 264:147] + node _T_128 = and(io.dbg_cmd_valid, _T_127) @[el2_dma_ctrl.scala 264:130] + node _T_129 = and(_T_128, io.dbg_cmd_write) @[el2_dma_ctrl.scala 264:151] + node _T_130 = or(_T_126, _T_129) @[el2_dma_ctrl.scala 264:110] + node _T_131 = eq(UInt<2>("h03"), WrPtr) @[el2_dma_ctrl.scala 264:179] + node _T_132 = and(_T_130, _T_131) @[el2_dma_ctrl.scala 264:172] + node _T_133 = or(dma_address_error, dma_alignment_error) @[el2_dma_ctrl.scala 264:213] + node _T_134 = eq(UInt<2>("h03"), RdPtr) @[el2_dma_ctrl.scala 264:243] + node _T_135 = and(_T_133, _T_134) @[el2_dma_ctrl.scala 264:236] + node _T_136 = or(_T_132, _T_135) @[el2_dma_ctrl.scala 264:191] + node _T_137 = eq(UInt<2>("h03"), io.dccm_dma_rtag) @[el2_dma_ctrl.scala 264:284] + node _T_138 = and(io.dccm_dma_rvalid, _T_137) @[el2_dma_ctrl.scala 264:277] + node _T_139 = or(_T_136, _T_138) @[el2_dma_ctrl.scala 264:255] + node _T_140 = eq(UInt<2>("h03"), io.iccm_dma_rtag) @[el2_dma_ctrl.scala 264:336] + node _T_141 = and(io.iccm_dma_rvalid, _T_140) @[el2_dma_ctrl.scala 264:329] + node _T_142 = or(_T_139, _T_141) @[el2_dma_ctrl.scala 264:307] + node _T_143 = and(axi_mstr_prty_en, fifo_write_in) @[el2_dma_ctrl.scala 264:73] + node _T_144 = and(_T_143, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 264:89] + node _T_145 = bits(io.dbg_cmd_type, 1, 1) @[el2_dma_ctrl.scala 264:147] + node _T_146 = and(io.dbg_cmd_valid, _T_145) @[el2_dma_ctrl.scala 264:130] + node _T_147 = and(_T_146, io.dbg_cmd_write) @[el2_dma_ctrl.scala 264:151] + node _T_148 = or(_T_144, _T_147) @[el2_dma_ctrl.scala 264:110] + node _T_149 = eq(UInt<3>("h04"), WrPtr) @[el2_dma_ctrl.scala 264:179] + node _T_150 = and(_T_148, _T_149) @[el2_dma_ctrl.scala 264:172] + node _T_151 = or(dma_address_error, dma_alignment_error) @[el2_dma_ctrl.scala 264:213] + node _T_152 = eq(UInt<3>("h04"), RdPtr) @[el2_dma_ctrl.scala 264:243] + node _T_153 = and(_T_151, _T_152) @[el2_dma_ctrl.scala 264:236] + node _T_154 = or(_T_150, _T_153) @[el2_dma_ctrl.scala 264:191] + node _T_155 = eq(UInt<3>("h04"), io.dccm_dma_rtag) @[el2_dma_ctrl.scala 264:284] + node _T_156 = and(io.dccm_dma_rvalid, _T_155) @[el2_dma_ctrl.scala 264:277] + node _T_157 = or(_T_154, _T_156) @[el2_dma_ctrl.scala 264:255] + node _T_158 = eq(UInt<3>("h04"), io.iccm_dma_rtag) @[el2_dma_ctrl.scala 264:336] + node _T_159 = and(io.iccm_dma_rvalid, _T_158) @[el2_dma_ctrl.scala 264:329] + node _T_160 = or(_T_157, _T_159) @[el2_dma_ctrl.scala 264:307] + node _T_161 = cat(_T_160, _T_142) @[Cat.scala 29:58] + node _T_162 = cat(_T_161, _T_124) @[Cat.scala 29:58] + node _T_163 = cat(_T_162, _T_106) @[Cat.scala 29:58] + node _T_164 = cat(_T_163, _T_88) @[Cat.scala 29:58] + fifo_data_en <= _T_164 @[el2_dma_ctrl.scala 264:21] + node _T_165 = or(io.dma_dccm_req, io.dma_iccm_req) @[el2_dma_ctrl.scala 266:75] + node _T_166 = eq(io.dma_mem_write, UInt<1>("h00")) @[el2_dma_ctrl.scala 266:96] + node _T_167 = and(_T_165, _T_166) @[el2_dma_ctrl.scala 266:94] + node _T_168 = eq(UInt<1>("h00"), RdPtr) @[el2_dma_ctrl.scala 266:121] + node _T_169 = and(_T_167, _T_168) @[el2_dma_ctrl.scala 266:114] + node _T_170 = or(io.dma_dccm_req, io.dma_iccm_req) @[el2_dma_ctrl.scala 266:75] + node _T_171 = eq(io.dma_mem_write, UInt<1>("h00")) @[el2_dma_ctrl.scala 266:96] + node _T_172 = and(_T_170, _T_171) @[el2_dma_ctrl.scala 266:94] + node _T_173 = eq(UInt<1>("h01"), RdPtr) @[el2_dma_ctrl.scala 266:121] + node _T_174 = and(_T_172, _T_173) @[el2_dma_ctrl.scala 266:114] + node _T_175 = or(io.dma_dccm_req, io.dma_iccm_req) @[el2_dma_ctrl.scala 266:75] + node _T_176 = eq(io.dma_mem_write, UInt<1>("h00")) @[el2_dma_ctrl.scala 266:96] + node _T_177 = and(_T_175, _T_176) @[el2_dma_ctrl.scala 266:94] + node _T_178 = eq(UInt<2>("h02"), RdPtr) @[el2_dma_ctrl.scala 266:121] + node _T_179 = and(_T_177, _T_178) @[el2_dma_ctrl.scala 266:114] + node _T_180 = or(io.dma_dccm_req, io.dma_iccm_req) @[el2_dma_ctrl.scala 266:75] + node _T_181 = eq(io.dma_mem_write, UInt<1>("h00")) @[el2_dma_ctrl.scala 266:96] + node _T_182 = and(_T_180, _T_181) @[el2_dma_ctrl.scala 266:94] + node _T_183 = eq(UInt<2>("h03"), RdPtr) @[el2_dma_ctrl.scala 266:121] + node _T_184 = and(_T_182, _T_183) @[el2_dma_ctrl.scala 266:114] + node _T_185 = or(io.dma_dccm_req, io.dma_iccm_req) @[el2_dma_ctrl.scala 266:75] + node _T_186 = eq(io.dma_mem_write, UInt<1>("h00")) @[el2_dma_ctrl.scala 266:96] + node _T_187 = and(_T_185, _T_186) @[el2_dma_ctrl.scala 266:94] + node _T_188 = eq(UInt<3>("h04"), RdPtr) @[el2_dma_ctrl.scala 266:121] + node _T_189 = and(_T_187, _T_188) @[el2_dma_ctrl.scala 266:114] + node _T_190 = cat(_T_189, _T_184) @[Cat.scala 29:58] + node _T_191 = cat(_T_190, _T_179) @[Cat.scala 29:58] + node _T_192 = cat(_T_191, _T_174) @[Cat.scala 29:58] + node _T_193 = cat(_T_192, _T_169) @[Cat.scala 29:58] + fifo_pend_en <= _T_193 @[el2_dma_ctrl.scala 266:21] + node _T_194 = bits(dma_address_error, 0, 0) @[el2_dma_ctrl.scala 268:78] + node _T_195 = bits(dma_alignment_error, 0, 0) @[el2_dma_ctrl.scala 268:107] + node _T_196 = or(_T_194, _T_195) @[el2_dma_ctrl.scala 268:85] + node _T_197 = or(_T_196, dma_dbg_cmd_error) @[el2_dma_ctrl.scala 268:114] + node _T_198 = eq(UInt<1>("h00"), RdPtr) @[el2_dma_ctrl.scala 268:142] + node _T_199 = and(_T_197, _T_198) @[el2_dma_ctrl.scala 268:135] + node _T_200 = and(io.dccm_dma_rvalid, io.dccm_dma_ecc_error) @[el2_dma_ctrl.scala 268:177] + node _T_201 = eq(UInt<1>("h00"), io.dccm_dma_rtag) @[el2_dma_ctrl.scala 268:209] + node _T_202 = and(_T_200, _T_201) @[el2_dma_ctrl.scala 268:202] + node _T_203 = or(_T_199, _T_202) @[el2_dma_ctrl.scala 268:154] + node _T_204 = and(io.iccm_dma_rvalid, io.iccm_dma_ecc_error) @[el2_dma_ctrl.scala 268:255] + node _T_205 = eq(UInt<1>("h00"), io.iccm_dma_rtag) @[el2_dma_ctrl.scala 268:287] + node _T_206 = and(_T_204, _T_205) @[el2_dma_ctrl.scala 268:280] + node _T_207 = or(_T_203, _T_206) @[el2_dma_ctrl.scala 268:232] + node _T_208 = bits(dma_address_error, 0, 0) @[el2_dma_ctrl.scala 268:78] + node _T_209 = bits(dma_alignment_error, 0, 0) @[el2_dma_ctrl.scala 268:107] + node _T_210 = or(_T_208, _T_209) @[el2_dma_ctrl.scala 268:85] + node _T_211 = or(_T_210, dma_dbg_cmd_error) @[el2_dma_ctrl.scala 268:114] + node _T_212 = eq(UInt<1>("h01"), RdPtr) @[el2_dma_ctrl.scala 268:142] + node _T_213 = and(_T_211, _T_212) @[el2_dma_ctrl.scala 268:135] + node _T_214 = and(io.dccm_dma_rvalid, io.dccm_dma_ecc_error) @[el2_dma_ctrl.scala 268:177] + node _T_215 = eq(UInt<1>("h01"), io.dccm_dma_rtag) @[el2_dma_ctrl.scala 268:209] + node _T_216 = and(_T_214, _T_215) @[el2_dma_ctrl.scala 268:202] + node _T_217 = or(_T_213, _T_216) @[el2_dma_ctrl.scala 268:154] + node _T_218 = and(io.iccm_dma_rvalid, io.iccm_dma_ecc_error) @[el2_dma_ctrl.scala 268:255] + node _T_219 = eq(UInt<1>("h01"), io.iccm_dma_rtag) @[el2_dma_ctrl.scala 268:287] + node _T_220 = and(_T_218, _T_219) @[el2_dma_ctrl.scala 268:280] + node _T_221 = or(_T_217, _T_220) @[el2_dma_ctrl.scala 268:232] + node _T_222 = bits(dma_address_error, 0, 0) @[el2_dma_ctrl.scala 268:78] + node _T_223 = bits(dma_alignment_error, 0, 0) @[el2_dma_ctrl.scala 268:107] + node _T_224 = or(_T_222, _T_223) @[el2_dma_ctrl.scala 268:85] + node _T_225 = or(_T_224, dma_dbg_cmd_error) @[el2_dma_ctrl.scala 268:114] + node _T_226 = eq(UInt<2>("h02"), RdPtr) @[el2_dma_ctrl.scala 268:142] + node _T_227 = and(_T_225, _T_226) @[el2_dma_ctrl.scala 268:135] + node _T_228 = and(io.dccm_dma_rvalid, io.dccm_dma_ecc_error) @[el2_dma_ctrl.scala 268:177] + node _T_229 = eq(UInt<2>("h02"), io.dccm_dma_rtag) @[el2_dma_ctrl.scala 268:209] + node _T_230 = and(_T_228, _T_229) @[el2_dma_ctrl.scala 268:202] + node _T_231 = or(_T_227, _T_230) @[el2_dma_ctrl.scala 268:154] + node _T_232 = and(io.iccm_dma_rvalid, io.iccm_dma_ecc_error) @[el2_dma_ctrl.scala 268:255] + node _T_233 = eq(UInt<2>("h02"), io.iccm_dma_rtag) @[el2_dma_ctrl.scala 268:287] + node _T_234 = and(_T_232, _T_233) @[el2_dma_ctrl.scala 268:280] + node _T_235 = or(_T_231, _T_234) @[el2_dma_ctrl.scala 268:232] + node _T_236 = bits(dma_address_error, 0, 0) @[el2_dma_ctrl.scala 268:78] + node _T_237 = bits(dma_alignment_error, 0, 0) @[el2_dma_ctrl.scala 268:107] + node _T_238 = or(_T_236, _T_237) @[el2_dma_ctrl.scala 268:85] + node _T_239 = or(_T_238, dma_dbg_cmd_error) @[el2_dma_ctrl.scala 268:114] + node _T_240 = eq(UInt<2>("h03"), RdPtr) @[el2_dma_ctrl.scala 268:142] + node _T_241 = and(_T_239, _T_240) @[el2_dma_ctrl.scala 268:135] + node _T_242 = and(io.dccm_dma_rvalid, io.dccm_dma_ecc_error) @[el2_dma_ctrl.scala 268:177] + node _T_243 = eq(UInt<2>("h03"), io.dccm_dma_rtag) @[el2_dma_ctrl.scala 268:209] + node _T_244 = and(_T_242, _T_243) @[el2_dma_ctrl.scala 268:202] + node _T_245 = or(_T_241, _T_244) @[el2_dma_ctrl.scala 268:154] + node _T_246 = and(io.iccm_dma_rvalid, io.iccm_dma_ecc_error) @[el2_dma_ctrl.scala 268:255] + node _T_247 = eq(UInt<2>("h03"), io.iccm_dma_rtag) @[el2_dma_ctrl.scala 268:287] + node _T_248 = and(_T_246, _T_247) @[el2_dma_ctrl.scala 268:280] + node _T_249 = or(_T_245, _T_248) @[el2_dma_ctrl.scala 268:232] + node _T_250 = bits(dma_address_error, 0, 0) @[el2_dma_ctrl.scala 268:78] + node _T_251 = bits(dma_alignment_error, 0, 0) @[el2_dma_ctrl.scala 268:107] + node _T_252 = or(_T_250, _T_251) @[el2_dma_ctrl.scala 268:85] + node _T_253 = or(_T_252, dma_dbg_cmd_error) @[el2_dma_ctrl.scala 268:114] + node _T_254 = eq(UInt<3>("h04"), RdPtr) @[el2_dma_ctrl.scala 268:142] + node _T_255 = and(_T_253, _T_254) @[el2_dma_ctrl.scala 268:135] + node _T_256 = and(io.dccm_dma_rvalid, io.dccm_dma_ecc_error) @[el2_dma_ctrl.scala 268:177] + node _T_257 = eq(UInt<3>("h04"), io.dccm_dma_rtag) @[el2_dma_ctrl.scala 268:209] + node _T_258 = and(_T_256, _T_257) @[el2_dma_ctrl.scala 268:202] + node _T_259 = or(_T_255, _T_258) @[el2_dma_ctrl.scala 268:154] + node _T_260 = and(io.iccm_dma_rvalid, io.iccm_dma_ecc_error) @[el2_dma_ctrl.scala 268:255] + node _T_261 = eq(UInt<3>("h04"), io.iccm_dma_rtag) @[el2_dma_ctrl.scala 268:287] + node _T_262 = and(_T_260, _T_261) @[el2_dma_ctrl.scala 268:280] + node _T_263 = or(_T_259, _T_262) @[el2_dma_ctrl.scala 268:232] + node _T_264 = cat(_T_263, _T_249) @[Cat.scala 29:58] + node _T_265 = cat(_T_264, _T_235) @[Cat.scala 29:58] + node _T_266 = cat(_T_265, _T_221) @[Cat.scala 29:58] + node _T_267 = cat(_T_266, _T_207) @[Cat.scala 29:58] + fifo_error_en <= _T_267 @[el2_dma_ctrl.scala 268:21] + node _T_268 = bits(fifo_error_in[0], 1, 0) @[el2_dma_ctrl.scala 270:77] + node _T_269 = orr(_T_268) @[el2_dma_ctrl.scala 270:83] + node _T_270 = bits(fifo_error_en, 0, 0) @[el2_dma_ctrl.scala 270:103] + node _T_271 = and(_T_269, _T_270) @[el2_dma_ctrl.scala 270:88] + node _T_272 = orr(fifo_error[0]) @[el2_dma_ctrl.scala 270:125] + node _T_273 = or(_T_271, _T_272) @[el2_dma_ctrl.scala 270:108] + node _T_274 = and(_T_273, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 270:131] + node _T_275 = bits(fifo_error_in[1], 1, 0) @[el2_dma_ctrl.scala 270:77] + node _T_276 = orr(_T_275) @[el2_dma_ctrl.scala 270:83] + node _T_277 = bits(fifo_error_en, 1, 1) @[el2_dma_ctrl.scala 270:103] + node _T_278 = and(_T_276, _T_277) @[el2_dma_ctrl.scala 270:88] + node _T_279 = orr(fifo_error[1]) @[el2_dma_ctrl.scala 270:125] + node _T_280 = or(_T_278, _T_279) @[el2_dma_ctrl.scala 270:108] + node _T_281 = and(_T_280, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 270:131] + node _T_282 = bits(fifo_error_in[2], 1, 0) @[el2_dma_ctrl.scala 270:77] + node _T_283 = orr(_T_282) @[el2_dma_ctrl.scala 270:83] + node _T_284 = bits(fifo_error_en, 2, 2) @[el2_dma_ctrl.scala 270:103] + node _T_285 = and(_T_283, _T_284) @[el2_dma_ctrl.scala 270:88] + node _T_286 = orr(fifo_error[2]) @[el2_dma_ctrl.scala 270:125] + node _T_287 = or(_T_285, _T_286) @[el2_dma_ctrl.scala 270:108] + node _T_288 = and(_T_287, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 270:131] + node _T_289 = bits(fifo_error_in[3], 1, 0) @[el2_dma_ctrl.scala 270:77] + node _T_290 = orr(_T_289) @[el2_dma_ctrl.scala 270:83] + node _T_291 = bits(fifo_error_en, 3, 3) @[el2_dma_ctrl.scala 270:103] + node _T_292 = and(_T_290, _T_291) @[el2_dma_ctrl.scala 270:88] + node _T_293 = orr(fifo_error[3]) @[el2_dma_ctrl.scala 270:125] + node _T_294 = or(_T_292, _T_293) @[el2_dma_ctrl.scala 270:108] + node _T_295 = and(_T_294, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 270:131] + node _T_296 = bits(fifo_error_in[4], 1, 0) @[el2_dma_ctrl.scala 270:77] + node _T_297 = orr(_T_296) @[el2_dma_ctrl.scala 270:83] + node _T_298 = bits(fifo_error_en, 4, 4) @[el2_dma_ctrl.scala 270:103] + node _T_299 = and(_T_297, _T_298) @[el2_dma_ctrl.scala 270:88] + node _T_300 = orr(fifo_error[4]) @[el2_dma_ctrl.scala 270:125] + node _T_301 = or(_T_299, _T_300) @[el2_dma_ctrl.scala 270:108] + node _T_302 = and(_T_301, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 270:131] + node _T_303 = cat(_T_302, _T_295) @[Cat.scala 29:58] + node _T_304 = cat(_T_303, _T_288) @[Cat.scala 29:58] + node _T_305 = cat(_T_304, _T_281) @[Cat.scala 29:58] + node _T_306 = cat(_T_305, _T_274) @[Cat.scala 29:58] + fifo_error_bus_en <= _T_306 @[el2_dma_ctrl.scala 270:21] + node _T_307 = orr(fifo_error[0]) @[el2_dma_ctrl.scala 272:74] + node _T_308 = bits(fifo_error_en, 0, 0) @[el2_dma_ctrl.scala 272:93] + node _T_309 = or(_T_307, _T_308) @[el2_dma_ctrl.scala 272:78] + node _T_310 = or(io.dma_dccm_req, io.dma_iccm_req) @[el2_dma_ctrl.scala 272:117] + node _T_311 = and(_T_310, io.dma_mem_write) @[el2_dma_ctrl.scala 272:136] + node _T_312 = or(_T_309, _T_311) @[el2_dma_ctrl.scala 272:97] + node _T_313 = eq(UInt<1>("h00"), RdPtr) @[el2_dma_ctrl.scala 272:164] + node _T_314 = and(_T_312, _T_313) @[el2_dma_ctrl.scala 272:157] + node _T_315 = eq(UInt<1>("h00"), io.dccm_dma_rtag) @[el2_dma_ctrl.scala 272:205] + node _T_316 = and(io.dccm_dma_rvalid, _T_315) @[el2_dma_ctrl.scala 272:198] + node _T_317 = or(_T_314, _T_316) @[el2_dma_ctrl.scala 272:176] + node _T_318 = eq(UInt<1>("h00"), io.iccm_dma_rtag) @[el2_dma_ctrl.scala 272:257] + node _T_319 = and(io.iccm_dma_rvalid, _T_318) @[el2_dma_ctrl.scala 272:250] + node _T_320 = or(_T_317, _T_319) @[el2_dma_ctrl.scala 272:228] + node _T_321 = orr(fifo_error[1]) @[el2_dma_ctrl.scala 272:74] + node _T_322 = bits(fifo_error_en, 1, 1) @[el2_dma_ctrl.scala 272:93] + node _T_323 = or(_T_321, _T_322) @[el2_dma_ctrl.scala 272:78] + node _T_324 = or(io.dma_dccm_req, io.dma_iccm_req) @[el2_dma_ctrl.scala 272:117] + node _T_325 = and(_T_324, io.dma_mem_write) @[el2_dma_ctrl.scala 272:136] + node _T_326 = or(_T_323, _T_325) @[el2_dma_ctrl.scala 272:97] + node _T_327 = eq(UInt<1>("h01"), RdPtr) @[el2_dma_ctrl.scala 272:164] + node _T_328 = and(_T_326, _T_327) @[el2_dma_ctrl.scala 272:157] + node _T_329 = eq(UInt<1>("h01"), io.dccm_dma_rtag) @[el2_dma_ctrl.scala 272:205] + node _T_330 = and(io.dccm_dma_rvalid, _T_329) @[el2_dma_ctrl.scala 272:198] + node _T_331 = or(_T_328, _T_330) @[el2_dma_ctrl.scala 272:176] + node _T_332 = eq(UInt<1>("h01"), io.iccm_dma_rtag) @[el2_dma_ctrl.scala 272:257] + node _T_333 = and(io.iccm_dma_rvalid, _T_332) @[el2_dma_ctrl.scala 272:250] + node _T_334 = or(_T_331, _T_333) @[el2_dma_ctrl.scala 272:228] + node _T_335 = orr(fifo_error[2]) @[el2_dma_ctrl.scala 272:74] + node _T_336 = bits(fifo_error_en, 2, 2) @[el2_dma_ctrl.scala 272:93] + node _T_337 = or(_T_335, _T_336) @[el2_dma_ctrl.scala 272:78] + node _T_338 = or(io.dma_dccm_req, io.dma_iccm_req) @[el2_dma_ctrl.scala 272:117] + node _T_339 = and(_T_338, io.dma_mem_write) @[el2_dma_ctrl.scala 272:136] + node _T_340 = or(_T_337, _T_339) @[el2_dma_ctrl.scala 272:97] + node _T_341 = eq(UInt<2>("h02"), RdPtr) @[el2_dma_ctrl.scala 272:164] + node _T_342 = and(_T_340, _T_341) @[el2_dma_ctrl.scala 272:157] + node _T_343 = eq(UInt<2>("h02"), io.dccm_dma_rtag) @[el2_dma_ctrl.scala 272:205] + node _T_344 = and(io.dccm_dma_rvalid, _T_343) @[el2_dma_ctrl.scala 272:198] + node _T_345 = or(_T_342, _T_344) @[el2_dma_ctrl.scala 272:176] + node _T_346 = eq(UInt<2>("h02"), io.iccm_dma_rtag) @[el2_dma_ctrl.scala 272:257] + node _T_347 = and(io.iccm_dma_rvalid, _T_346) @[el2_dma_ctrl.scala 272:250] + node _T_348 = or(_T_345, _T_347) @[el2_dma_ctrl.scala 272:228] + node _T_349 = orr(fifo_error[3]) @[el2_dma_ctrl.scala 272:74] + node _T_350 = bits(fifo_error_en, 3, 3) @[el2_dma_ctrl.scala 272:93] + node _T_351 = or(_T_349, _T_350) @[el2_dma_ctrl.scala 272:78] + node _T_352 = or(io.dma_dccm_req, io.dma_iccm_req) @[el2_dma_ctrl.scala 272:117] + node _T_353 = and(_T_352, io.dma_mem_write) @[el2_dma_ctrl.scala 272:136] + node _T_354 = or(_T_351, _T_353) @[el2_dma_ctrl.scala 272:97] + node _T_355 = eq(UInt<2>("h03"), RdPtr) @[el2_dma_ctrl.scala 272:164] + node _T_356 = and(_T_354, _T_355) @[el2_dma_ctrl.scala 272:157] + node _T_357 = eq(UInt<2>("h03"), io.dccm_dma_rtag) @[el2_dma_ctrl.scala 272:205] + node _T_358 = and(io.dccm_dma_rvalid, _T_357) @[el2_dma_ctrl.scala 272:198] + node _T_359 = or(_T_356, _T_358) @[el2_dma_ctrl.scala 272:176] + node _T_360 = eq(UInt<2>("h03"), io.iccm_dma_rtag) @[el2_dma_ctrl.scala 272:257] + node _T_361 = and(io.iccm_dma_rvalid, _T_360) @[el2_dma_ctrl.scala 272:250] + node _T_362 = or(_T_359, _T_361) @[el2_dma_ctrl.scala 272:228] + node _T_363 = orr(fifo_error[4]) @[el2_dma_ctrl.scala 272:74] + node _T_364 = bits(fifo_error_en, 4, 4) @[el2_dma_ctrl.scala 272:93] + node _T_365 = or(_T_363, _T_364) @[el2_dma_ctrl.scala 272:78] + node _T_366 = or(io.dma_dccm_req, io.dma_iccm_req) @[el2_dma_ctrl.scala 272:117] + node _T_367 = and(_T_366, io.dma_mem_write) @[el2_dma_ctrl.scala 272:136] + node _T_368 = or(_T_365, _T_367) @[el2_dma_ctrl.scala 272:97] + node _T_369 = eq(UInt<3>("h04"), RdPtr) @[el2_dma_ctrl.scala 272:164] + node _T_370 = and(_T_368, _T_369) @[el2_dma_ctrl.scala 272:157] + node _T_371 = eq(UInt<3>("h04"), io.dccm_dma_rtag) @[el2_dma_ctrl.scala 272:205] + node _T_372 = and(io.dccm_dma_rvalid, _T_371) @[el2_dma_ctrl.scala 272:198] + node _T_373 = or(_T_370, _T_372) @[el2_dma_ctrl.scala 272:176] + node _T_374 = eq(UInt<3>("h04"), io.iccm_dma_rtag) @[el2_dma_ctrl.scala 272:257] + node _T_375 = and(io.iccm_dma_rvalid, _T_374) @[el2_dma_ctrl.scala 272:250] + node _T_376 = or(_T_373, _T_375) @[el2_dma_ctrl.scala 272:228] + node _T_377 = cat(_T_376, _T_362) @[Cat.scala 29:58] + node _T_378 = cat(_T_377, _T_348) @[Cat.scala 29:58] + node _T_379 = cat(_T_378, _T_334) @[Cat.scala 29:58] + node _T_380 = cat(_T_379, _T_320) @[Cat.scala 29:58] + fifo_done_en <= _T_380 @[el2_dma_ctrl.scala 272:21] + node _T_381 = bits(fifo_done_en, 0, 0) @[el2_dma_ctrl.scala 274:71] + node _T_382 = bits(fifo_done, 0, 0) @[el2_dma_ctrl.scala 274:86] + node _T_383 = or(_T_381, _T_382) @[el2_dma_ctrl.scala 274:75] + node _T_384 = and(_T_383, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 274:91] + node _T_385 = bits(fifo_done_en, 1, 1) @[el2_dma_ctrl.scala 274:71] + node _T_386 = bits(fifo_done, 1, 1) @[el2_dma_ctrl.scala 274:86] + node _T_387 = or(_T_385, _T_386) @[el2_dma_ctrl.scala 274:75] + node _T_388 = and(_T_387, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 274:91] + node _T_389 = bits(fifo_done_en, 2, 2) @[el2_dma_ctrl.scala 274:71] + node _T_390 = bits(fifo_done, 2, 2) @[el2_dma_ctrl.scala 274:86] + node _T_391 = or(_T_389, _T_390) @[el2_dma_ctrl.scala 274:75] + node _T_392 = and(_T_391, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 274:91] + node _T_393 = bits(fifo_done_en, 3, 3) @[el2_dma_ctrl.scala 274:71] + node _T_394 = bits(fifo_done, 3, 3) @[el2_dma_ctrl.scala 274:86] + node _T_395 = or(_T_393, _T_394) @[el2_dma_ctrl.scala 274:75] + node _T_396 = and(_T_395, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 274:91] + node _T_397 = bits(fifo_done_en, 4, 4) @[el2_dma_ctrl.scala 274:71] + node _T_398 = bits(fifo_done, 4, 4) @[el2_dma_ctrl.scala 274:86] + node _T_399 = or(_T_397, _T_398) @[el2_dma_ctrl.scala 274:75] + node _T_400 = and(_T_399, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 274:91] + node _T_401 = cat(_T_400, _T_396) @[Cat.scala 29:58] + node _T_402 = cat(_T_401, _T_392) @[Cat.scala 29:58] + node _T_403 = cat(_T_402, _T_388) @[Cat.scala 29:58] + node _T_404 = cat(_T_403, _T_384) @[Cat.scala 29:58] + fifo_done_bus_en <= _T_404 @[el2_dma_ctrl.scala 274:21] + node _T_405 = or(bus_rsp_sent, bus_posted_write_done) @[el2_dma_ctrl.scala 276:74] + node _T_406 = and(_T_405, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 276:99] + node _T_407 = or(_T_406, io.dma_dbg_cmd_done) @[el2_dma_ctrl.scala 276:120] + node _T_408 = eq(UInt<1>("h00"), RspPtr) @[el2_dma_ctrl.scala 276:150] + node _T_409 = and(_T_407, _T_408) @[el2_dma_ctrl.scala 276:143] + node _T_410 = or(bus_rsp_sent, bus_posted_write_done) @[el2_dma_ctrl.scala 276:74] + node _T_411 = and(_T_410, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 276:99] + node _T_412 = or(_T_411, io.dma_dbg_cmd_done) @[el2_dma_ctrl.scala 276:120] + node _T_413 = eq(UInt<1>("h01"), RspPtr) @[el2_dma_ctrl.scala 276:150] + node _T_414 = and(_T_412, _T_413) @[el2_dma_ctrl.scala 276:143] + node _T_415 = or(bus_rsp_sent, bus_posted_write_done) @[el2_dma_ctrl.scala 276:74] + node _T_416 = and(_T_415, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 276:99] + node _T_417 = or(_T_416, io.dma_dbg_cmd_done) @[el2_dma_ctrl.scala 276:120] + node _T_418 = eq(UInt<2>("h02"), RspPtr) @[el2_dma_ctrl.scala 276:150] + node _T_419 = and(_T_417, _T_418) @[el2_dma_ctrl.scala 276:143] + node _T_420 = or(bus_rsp_sent, bus_posted_write_done) @[el2_dma_ctrl.scala 276:74] + node _T_421 = and(_T_420, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 276:99] + node _T_422 = or(_T_421, io.dma_dbg_cmd_done) @[el2_dma_ctrl.scala 276:120] + node _T_423 = eq(UInt<2>("h03"), RspPtr) @[el2_dma_ctrl.scala 276:150] + node _T_424 = and(_T_422, _T_423) @[el2_dma_ctrl.scala 276:143] + node _T_425 = or(bus_rsp_sent, bus_posted_write_done) @[el2_dma_ctrl.scala 276:74] + node _T_426 = and(_T_425, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 276:99] + node _T_427 = or(_T_426, io.dma_dbg_cmd_done) @[el2_dma_ctrl.scala 276:120] + node _T_428 = eq(UInt<3>("h04"), RspPtr) @[el2_dma_ctrl.scala 276:150] + node _T_429 = and(_T_427, _T_428) @[el2_dma_ctrl.scala 276:143] + node _T_430 = cat(_T_429, _T_424) @[Cat.scala 29:58] + node _T_431 = cat(_T_430, _T_419) @[Cat.scala 29:58] + node _T_432 = cat(_T_431, _T_414) @[Cat.scala 29:58] + node _T_433 = cat(_T_432, _T_409) @[Cat.scala 29:58] + fifo_reset <= _T_433 @[el2_dma_ctrl.scala 276:21] + node _T_434 = eq(UInt<1>("h00"), io.dccm_dma_rtag) @[el2_dma_ctrl.scala 278:87] + node _T_435 = and(io.dccm_dma_rvalid, _T_434) @[el2_dma_ctrl.scala 278:80] + node _T_436 = cat(UInt<1>("h00"), io.dccm_dma_ecc_error) @[Cat.scala 29:58] + node _T_437 = eq(UInt<1>("h00"), io.iccm_dma_rtag) @[el2_dma_ctrl.scala 278:173] + node _T_438 = and(io.iccm_dma_rvalid, _T_437) @[el2_dma_ctrl.scala 278:166] + node _T_439 = cat(UInt<1>("h00"), io.iccm_dma_ecc_error) @[Cat.scala 29:58] + node _T_440 = or(dma_address_error, dma_alignment_error) @[el2_dma_ctrl.scala 278:255] + node _T_441 = or(_T_440, dma_dbg_cmd_error) @[el2_dma_ctrl.scala 278:277] + node _T_442 = cat(_T_441, dma_alignment_error) @[Cat.scala 29:58] + node _T_443 = mux(_T_438, _T_439, _T_442) @[el2_dma_ctrl.scala 278:146] + node _T_444 = mux(_T_435, _T_436, _T_443) @[el2_dma_ctrl.scala 278:60] + fifo_error_in[0] <= _T_444 @[el2_dma_ctrl.scala 278:53] + node _T_445 = eq(UInt<1>("h01"), io.dccm_dma_rtag) @[el2_dma_ctrl.scala 278:87] + node _T_446 = and(io.dccm_dma_rvalid, _T_445) @[el2_dma_ctrl.scala 278:80] + node _T_447 = cat(UInt<1>("h00"), io.dccm_dma_ecc_error) @[Cat.scala 29:58] + node _T_448 = eq(UInt<1>("h01"), io.iccm_dma_rtag) @[el2_dma_ctrl.scala 278:173] + node _T_449 = and(io.iccm_dma_rvalid, _T_448) @[el2_dma_ctrl.scala 278:166] + node _T_450 = cat(UInt<1>("h00"), io.iccm_dma_ecc_error) @[Cat.scala 29:58] + node _T_451 = or(dma_address_error, dma_alignment_error) @[el2_dma_ctrl.scala 278:255] + node _T_452 = or(_T_451, dma_dbg_cmd_error) @[el2_dma_ctrl.scala 278:277] + node _T_453 = cat(_T_452, dma_alignment_error) @[Cat.scala 29:58] + node _T_454 = mux(_T_449, _T_450, _T_453) @[el2_dma_ctrl.scala 278:146] + node _T_455 = mux(_T_446, _T_447, _T_454) @[el2_dma_ctrl.scala 278:60] + fifo_error_in[1] <= _T_455 @[el2_dma_ctrl.scala 278:53] + node _T_456 = eq(UInt<2>("h02"), io.dccm_dma_rtag) @[el2_dma_ctrl.scala 278:87] + node _T_457 = and(io.dccm_dma_rvalid, _T_456) @[el2_dma_ctrl.scala 278:80] + node _T_458 = cat(UInt<1>("h00"), io.dccm_dma_ecc_error) @[Cat.scala 29:58] + node _T_459 = eq(UInt<2>("h02"), io.iccm_dma_rtag) @[el2_dma_ctrl.scala 278:173] + node _T_460 = and(io.iccm_dma_rvalid, _T_459) @[el2_dma_ctrl.scala 278:166] + node _T_461 = cat(UInt<1>("h00"), io.iccm_dma_ecc_error) @[Cat.scala 29:58] + node _T_462 = or(dma_address_error, dma_alignment_error) @[el2_dma_ctrl.scala 278:255] + node _T_463 = or(_T_462, dma_dbg_cmd_error) @[el2_dma_ctrl.scala 278:277] + node _T_464 = cat(_T_463, dma_alignment_error) @[Cat.scala 29:58] + node _T_465 = mux(_T_460, _T_461, _T_464) @[el2_dma_ctrl.scala 278:146] + node _T_466 = mux(_T_457, _T_458, _T_465) @[el2_dma_ctrl.scala 278:60] + fifo_error_in[2] <= _T_466 @[el2_dma_ctrl.scala 278:53] + node _T_467 = eq(UInt<2>("h03"), io.dccm_dma_rtag) @[el2_dma_ctrl.scala 278:87] + node _T_468 = and(io.dccm_dma_rvalid, _T_467) @[el2_dma_ctrl.scala 278:80] + node _T_469 = cat(UInt<1>("h00"), io.dccm_dma_ecc_error) @[Cat.scala 29:58] + node _T_470 = eq(UInt<2>("h03"), io.iccm_dma_rtag) @[el2_dma_ctrl.scala 278:173] + node _T_471 = and(io.iccm_dma_rvalid, _T_470) @[el2_dma_ctrl.scala 278:166] + node _T_472 = cat(UInt<1>("h00"), io.iccm_dma_ecc_error) @[Cat.scala 29:58] + node _T_473 = or(dma_address_error, dma_alignment_error) @[el2_dma_ctrl.scala 278:255] + node _T_474 = or(_T_473, dma_dbg_cmd_error) @[el2_dma_ctrl.scala 278:277] + node _T_475 = cat(_T_474, dma_alignment_error) @[Cat.scala 29:58] + node _T_476 = mux(_T_471, _T_472, _T_475) @[el2_dma_ctrl.scala 278:146] + node _T_477 = mux(_T_468, _T_469, _T_476) @[el2_dma_ctrl.scala 278:60] + fifo_error_in[3] <= _T_477 @[el2_dma_ctrl.scala 278:53] + node _T_478 = eq(UInt<3>("h04"), io.dccm_dma_rtag) @[el2_dma_ctrl.scala 278:87] + node _T_479 = and(io.dccm_dma_rvalid, _T_478) @[el2_dma_ctrl.scala 278:80] + node _T_480 = cat(UInt<1>("h00"), io.dccm_dma_ecc_error) @[Cat.scala 29:58] + node _T_481 = eq(UInt<3>("h04"), io.iccm_dma_rtag) @[el2_dma_ctrl.scala 278:173] + node _T_482 = and(io.iccm_dma_rvalid, _T_481) @[el2_dma_ctrl.scala 278:166] + node _T_483 = cat(UInt<1>("h00"), io.iccm_dma_ecc_error) @[Cat.scala 29:58] + node _T_484 = or(dma_address_error, dma_alignment_error) @[el2_dma_ctrl.scala 278:255] + node _T_485 = or(_T_484, dma_dbg_cmd_error) @[el2_dma_ctrl.scala 278:277] + node _T_486 = cat(_T_485, dma_alignment_error) @[Cat.scala 29:58] + node _T_487 = mux(_T_482, _T_483, _T_486) @[el2_dma_ctrl.scala 278:146] + node _T_488 = mux(_T_479, _T_480, _T_487) @[el2_dma_ctrl.scala 278:60] + fifo_error_in[4] <= _T_488 @[el2_dma_ctrl.scala 278:53] + node _T_489 = bits(fifo_error_en, 0, 0) @[el2_dma_ctrl.scala 280:73] + node _T_490 = orr(fifo_error_in[0]) @[el2_dma_ctrl.scala 280:97] + node _T_491 = and(_T_489, _T_490) @[el2_dma_ctrl.scala 280:77] + node _T_492 = mux(UInt<1>("h00"), UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_493 = cat(_T_492, fifo_addr[0]) @[Cat.scala 29:58] + node _T_494 = eq(UInt<1>("h00"), io.dccm_dma_rtag) @[el2_dma_ctrl.scala 280:167] + node _T_495 = and(io.dccm_dma_rvalid, _T_494) @[el2_dma_ctrl.scala 280:160] + node _T_496 = eq(UInt<1>("h00"), io.iccm_dma_rtag) @[el2_dma_ctrl.scala 280:239] + node _T_497 = and(io.iccm_dma_rvalid, _T_496) @[el2_dma_ctrl.scala 280:232] + node _T_498 = cat(io.dbg_cmd_wrdata, io.dbg_cmd_wrdata) @[Cat.scala 29:58] + node _T_499 = bits(bus_cmd_wdata, 63, 0) @[el2_dma_ctrl.scala 280:344] + node _T_500 = mux(io.dbg_cmd_valid, _T_498, _T_499) @[el2_dma_ctrl.scala 280:284] + node _T_501 = mux(_T_497, io.iccm_dma_rdata, _T_500) @[el2_dma_ctrl.scala 280:212] + node _T_502 = mux(_T_495, io.dccm_dma_rdata, _T_501) @[el2_dma_ctrl.scala 280:140] + node _T_503 = mux(_T_491, _T_493, _T_502) @[el2_dma_ctrl.scala 280:59] + fifo_data_in[0] <= _T_503 @[el2_dma_ctrl.scala 280:52] + node _T_504 = bits(fifo_error_en, 1, 1) @[el2_dma_ctrl.scala 280:73] + node _T_505 = orr(fifo_error_in[1]) @[el2_dma_ctrl.scala 280:97] + node _T_506 = and(_T_504, _T_505) @[el2_dma_ctrl.scala 280:77] + node _T_507 = mux(UInt<1>("h00"), UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_508 = cat(_T_507, fifo_addr[1]) @[Cat.scala 29:58] + node _T_509 = eq(UInt<1>("h01"), io.dccm_dma_rtag) @[el2_dma_ctrl.scala 280:167] + node _T_510 = and(io.dccm_dma_rvalid, _T_509) @[el2_dma_ctrl.scala 280:160] + node _T_511 = eq(UInt<1>("h01"), io.iccm_dma_rtag) @[el2_dma_ctrl.scala 280:239] + node _T_512 = and(io.iccm_dma_rvalid, _T_511) @[el2_dma_ctrl.scala 280:232] + node _T_513 = cat(io.dbg_cmd_wrdata, io.dbg_cmd_wrdata) @[Cat.scala 29:58] + node _T_514 = bits(bus_cmd_wdata, 63, 0) @[el2_dma_ctrl.scala 280:344] + node _T_515 = mux(io.dbg_cmd_valid, _T_513, _T_514) @[el2_dma_ctrl.scala 280:284] + node _T_516 = mux(_T_512, io.iccm_dma_rdata, _T_515) @[el2_dma_ctrl.scala 280:212] + node _T_517 = mux(_T_510, io.dccm_dma_rdata, _T_516) @[el2_dma_ctrl.scala 280:140] + node _T_518 = mux(_T_506, _T_508, _T_517) @[el2_dma_ctrl.scala 280:59] + fifo_data_in[1] <= _T_518 @[el2_dma_ctrl.scala 280:52] + node _T_519 = bits(fifo_error_en, 2, 2) @[el2_dma_ctrl.scala 280:73] + node _T_520 = orr(fifo_error_in[2]) @[el2_dma_ctrl.scala 280:97] + node _T_521 = and(_T_519, _T_520) @[el2_dma_ctrl.scala 280:77] + node _T_522 = mux(UInt<1>("h00"), UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_523 = cat(_T_522, fifo_addr[2]) @[Cat.scala 29:58] + node _T_524 = eq(UInt<2>("h02"), io.dccm_dma_rtag) @[el2_dma_ctrl.scala 280:167] + node _T_525 = and(io.dccm_dma_rvalid, _T_524) @[el2_dma_ctrl.scala 280:160] + node _T_526 = eq(UInt<2>("h02"), io.iccm_dma_rtag) @[el2_dma_ctrl.scala 280:239] + node _T_527 = and(io.iccm_dma_rvalid, _T_526) @[el2_dma_ctrl.scala 280:232] + node _T_528 = cat(io.dbg_cmd_wrdata, io.dbg_cmd_wrdata) @[Cat.scala 29:58] + node _T_529 = bits(bus_cmd_wdata, 63, 0) @[el2_dma_ctrl.scala 280:344] + node _T_530 = mux(io.dbg_cmd_valid, _T_528, _T_529) @[el2_dma_ctrl.scala 280:284] + node _T_531 = mux(_T_527, io.iccm_dma_rdata, _T_530) @[el2_dma_ctrl.scala 280:212] + node _T_532 = mux(_T_525, io.dccm_dma_rdata, _T_531) @[el2_dma_ctrl.scala 280:140] + node _T_533 = mux(_T_521, _T_523, _T_532) @[el2_dma_ctrl.scala 280:59] + fifo_data_in[2] <= _T_533 @[el2_dma_ctrl.scala 280:52] + node _T_534 = bits(fifo_error_en, 3, 3) @[el2_dma_ctrl.scala 280:73] + node _T_535 = orr(fifo_error_in[3]) @[el2_dma_ctrl.scala 280:97] + node _T_536 = and(_T_534, _T_535) @[el2_dma_ctrl.scala 280:77] + node _T_537 = mux(UInt<1>("h00"), UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_538 = cat(_T_537, fifo_addr[3]) @[Cat.scala 29:58] + node _T_539 = eq(UInt<2>("h03"), io.dccm_dma_rtag) @[el2_dma_ctrl.scala 280:167] + node _T_540 = and(io.dccm_dma_rvalid, _T_539) @[el2_dma_ctrl.scala 280:160] + node _T_541 = eq(UInt<2>("h03"), io.iccm_dma_rtag) @[el2_dma_ctrl.scala 280:239] + node _T_542 = and(io.iccm_dma_rvalid, _T_541) @[el2_dma_ctrl.scala 280:232] + node _T_543 = cat(io.dbg_cmd_wrdata, io.dbg_cmd_wrdata) @[Cat.scala 29:58] + node _T_544 = bits(bus_cmd_wdata, 63, 0) @[el2_dma_ctrl.scala 280:344] + node _T_545 = mux(io.dbg_cmd_valid, _T_543, _T_544) @[el2_dma_ctrl.scala 280:284] + node _T_546 = mux(_T_542, io.iccm_dma_rdata, _T_545) @[el2_dma_ctrl.scala 280:212] + node _T_547 = mux(_T_540, io.dccm_dma_rdata, _T_546) @[el2_dma_ctrl.scala 280:140] + node _T_548 = mux(_T_536, _T_538, _T_547) @[el2_dma_ctrl.scala 280:59] + fifo_data_in[3] <= _T_548 @[el2_dma_ctrl.scala 280:52] + node _T_549 = bits(fifo_error_en, 4, 4) @[el2_dma_ctrl.scala 280:73] + node _T_550 = orr(fifo_error_in[4]) @[el2_dma_ctrl.scala 280:97] + node _T_551 = and(_T_549, _T_550) @[el2_dma_ctrl.scala 280:77] + node _T_552 = mux(UInt<1>("h00"), UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_553 = cat(_T_552, fifo_addr[4]) @[Cat.scala 29:58] + node _T_554 = eq(UInt<3>("h04"), io.dccm_dma_rtag) @[el2_dma_ctrl.scala 280:167] + node _T_555 = and(io.dccm_dma_rvalid, _T_554) @[el2_dma_ctrl.scala 280:160] + node _T_556 = eq(UInt<3>("h04"), io.iccm_dma_rtag) @[el2_dma_ctrl.scala 280:239] + node _T_557 = and(io.iccm_dma_rvalid, _T_556) @[el2_dma_ctrl.scala 280:232] + node _T_558 = cat(io.dbg_cmd_wrdata, io.dbg_cmd_wrdata) @[Cat.scala 29:58] + node _T_559 = bits(bus_cmd_wdata, 63, 0) @[el2_dma_ctrl.scala 280:344] + node _T_560 = mux(io.dbg_cmd_valid, _T_558, _T_559) @[el2_dma_ctrl.scala 280:284] + node _T_561 = mux(_T_557, io.iccm_dma_rdata, _T_560) @[el2_dma_ctrl.scala 280:212] + node _T_562 = mux(_T_555, io.dccm_dma_rdata, _T_561) @[el2_dma_ctrl.scala 280:140] + node _T_563 = mux(_T_551, _T_553, _T_562) @[el2_dma_ctrl.scala 280:59] + fifo_data_in[4] <= _T_563 @[el2_dma_ctrl.scala 280:52] + node _T_564 = bits(fifo_cmd_en, 0, 0) @[el2_dma_ctrl.scala 282:98] + node _T_565 = bits(fifo_valid, 0, 0) @[el2_dma_ctrl.scala 282:118] + node _T_566 = mux(_T_564, UInt<1>("h01"), _T_565) @[el2_dma_ctrl.scala 282:86] + node _T_567 = bits(fifo_reset, 0, 0) @[el2_dma_ctrl.scala 282:136] + node _T_568 = eq(_T_567, UInt<1>("h00")) @[el2_dma_ctrl.scala 282:125] + node _T_569 = and(_T_566, _T_568) @[el2_dma_ctrl.scala 282:123] + reg _T_570 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 282:82] + _T_570 <= _T_569 @[el2_dma_ctrl.scala 282:82] + node _T_571 = bits(fifo_cmd_en, 1, 1) @[el2_dma_ctrl.scala 282:98] + node _T_572 = bits(fifo_valid, 1, 1) @[el2_dma_ctrl.scala 282:118] + node _T_573 = mux(_T_571, UInt<1>("h01"), _T_572) @[el2_dma_ctrl.scala 282:86] + node _T_574 = bits(fifo_reset, 1, 1) @[el2_dma_ctrl.scala 282:136] + node _T_575 = eq(_T_574, UInt<1>("h00")) @[el2_dma_ctrl.scala 282:125] + node _T_576 = and(_T_573, _T_575) @[el2_dma_ctrl.scala 282:123] + reg _T_577 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 282:82] + _T_577 <= _T_576 @[el2_dma_ctrl.scala 282:82] + node _T_578 = bits(fifo_cmd_en, 2, 2) @[el2_dma_ctrl.scala 282:98] + node _T_579 = bits(fifo_valid, 2, 2) @[el2_dma_ctrl.scala 282:118] + node _T_580 = mux(_T_578, UInt<1>("h01"), _T_579) @[el2_dma_ctrl.scala 282:86] + node _T_581 = bits(fifo_reset, 2, 2) @[el2_dma_ctrl.scala 282:136] + node _T_582 = eq(_T_581, UInt<1>("h00")) @[el2_dma_ctrl.scala 282:125] + node _T_583 = and(_T_580, _T_582) @[el2_dma_ctrl.scala 282:123] + reg _T_584 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 282:82] + _T_584 <= _T_583 @[el2_dma_ctrl.scala 282:82] + node _T_585 = bits(fifo_cmd_en, 3, 3) @[el2_dma_ctrl.scala 282:98] + node _T_586 = bits(fifo_valid, 3, 3) @[el2_dma_ctrl.scala 282:118] + node _T_587 = mux(_T_585, UInt<1>("h01"), _T_586) @[el2_dma_ctrl.scala 282:86] + node _T_588 = bits(fifo_reset, 3, 3) @[el2_dma_ctrl.scala 282:136] + node _T_589 = eq(_T_588, UInt<1>("h00")) @[el2_dma_ctrl.scala 282:125] + node _T_590 = and(_T_587, _T_589) @[el2_dma_ctrl.scala 282:123] + reg _T_591 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 282:82] + _T_591 <= _T_590 @[el2_dma_ctrl.scala 282:82] + node _T_592 = bits(fifo_cmd_en, 4, 4) @[el2_dma_ctrl.scala 282:98] + node _T_593 = bits(fifo_valid, 4, 4) @[el2_dma_ctrl.scala 282:118] + node _T_594 = mux(_T_592, UInt<1>("h01"), _T_593) @[el2_dma_ctrl.scala 282:86] + node _T_595 = bits(fifo_reset, 4, 4) @[el2_dma_ctrl.scala 282:136] + node _T_596 = eq(_T_595, UInt<1>("h00")) @[el2_dma_ctrl.scala 282:125] + node _T_597 = and(_T_594, _T_596) @[el2_dma_ctrl.scala 282:123] + reg _T_598 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 282:82] + _T_598 <= _T_597 @[el2_dma_ctrl.scala 282:82] + node _T_599 = cat(_T_598, _T_591) @[Cat.scala 29:58] + node _T_600 = cat(_T_599, _T_584) @[Cat.scala 29:58] + node _T_601 = cat(_T_600, _T_577) @[Cat.scala 29:58] + node _T_602 = cat(_T_601, _T_570) @[Cat.scala 29:58] + fifo_valid <= _T_602 @[el2_dma_ctrl.scala 282:14] + node _T_603 = bits(fifo_error_en, 0, 0) @[el2_dma_ctrl.scala 284:103] + node _T_604 = bits(_T_603, 0, 0) @[el2_dma_ctrl.scala 284:113] + node _T_605 = mux(_T_604, fifo_error_in[0], fifo_error[0]) @[el2_dma_ctrl.scala 284:89] + node _T_606 = bits(fifo_reset, 0, 0) @[el2_dma_ctrl.scala 284:196] + node _T_607 = eq(_T_606, UInt<1>("h00")) @[el2_dma_ctrl.scala 284:185] + node _T_608 = bits(_T_607, 0, 0) @[Bitwise.scala 72:15] + node _T_609 = mux(_T_608, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_610 = and(_T_605, _T_609) @[el2_dma_ctrl.scala 284:150] + reg _T_611 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 284:85] + _T_611 <= _T_610 @[el2_dma_ctrl.scala 284:85] + fifo_error[0] <= _T_611 @[el2_dma_ctrl.scala 284:50] + node _T_612 = bits(fifo_error_en, 1, 1) @[el2_dma_ctrl.scala 284:103] + node _T_613 = bits(_T_612, 0, 0) @[el2_dma_ctrl.scala 284:113] + node _T_614 = mux(_T_613, fifo_error_in[1], fifo_error[1]) @[el2_dma_ctrl.scala 284:89] + node _T_615 = bits(fifo_reset, 1, 1) @[el2_dma_ctrl.scala 284:196] + node _T_616 = eq(_T_615, UInt<1>("h00")) @[el2_dma_ctrl.scala 284:185] + node _T_617 = bits(_T_616, 0, 0) @[Bitwise.scala 72:15] + node _T_618 = mux(_T_617, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_619 = and(_T_614, _T_618) @[el2_dma_ctrl.scala 284:150] + reg _T_620 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 284:85] + _T_620 <= _T_619 @[el2_dma_ctrl.scala 284:85] + fifo_error[1] <= _T_620 @[el2_dma_ctrl.scala 284:50] + node _T_621 = bits(fifo_error_en, 2, 2) @[el2_dma_ctrl.scala 284:103] + node _T_622 = bits(_T_621, 0, 0) @[el2_dma_ctrl.scala 284:113] + node _T_623 = mux(_T_622, fifo_error_in[2], fifo_error[2]) @[el2_dma_ctrl.scala 284:89] + node _T_624 = bits(fifo_reset, 2, 2) @[el2_dma_ctrl.scala 284:196] + node _T_625 = eq(_T_624, UInt<1>("h00")) @[el2_dma_ctrl.scala 284:185] + node _T_626 = bits(_T_625, 0, 0) @[Bitwise.scala 72:15] + node _T_627 = mux(_T_626, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_628 = and(_T_623, _T_627) @[el2_dma_ctrl.scala 284:150] + reg _T_629 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 284:85] + _T_629 <= _T_628 @[el2_dma_ctrl.scala 284:85] + fifo_error[2] <= _T_629 @[el2_dma_ctrl.scala 284:50] + node _T_630 = bits(fifo_error_en, 3, 3) @[el2_dma_ctrl.scala 284:103] + node _T_631 = bits(_T_630, 0, 0) @[el2_dma_ctrl.scala 284:113] + node _T_632 = mux(_T_631, fifo_error_in[3], fifo_error[3]) @[el2_dma_ctrl.scala 284:89] + node _T_633 = bits(fifo_reset, 3, 3) @[el2_dma_ctrl.scala 284:196] + node _T_634 = eq(_T_633, UInt<1>("h00")) @[el2_dma_ctrl.scala 284:185] + node _T_635 = bits(_T_634, 0, 0) @[Bitwise.scala 72:15] + node _T_636 = mux(_T_635, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_637 = and(_T_632, _T_636) @[el2_dma_ctrl.scala 284:150] + reg _T_638 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 284:85] + _T_638 <= _T_637 @[el2_dma_ctrl.scala 284:85] + fifo_error[3] <= _T_638 @[el2_dma_ctrl.scala 284:50] + node _T_639 = bits(fifo_error_en, 4, 4) @[el2_dma_ctrl.scala 284:103] + node _T_640 = bits(_T_639, 0, 0) @[el2_dma_ctrl.scala 284:113] + node _T_641 = mux(_T_640, fifo_error_in[4], fifo_error[4]) @[el2_dma_ctrl.scala 284:89] + node _T_642 = bits(fifo_reset, 4, 4) @[el2_dma_ctrl.scala 284:196] + node _T_643 = eq(_T_642, UInt<1>("h00")) @[el2_dma_ctrl.scala 284:185] + node _T_644 = bits(_T_643, 0, 0) @[Bitwise.scala 72:15] + node _T_645 = mux(_T_644, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_646 = and(_T_641, _T_645) @[el2_dma_ctrl.scala 284:150] + reg _T_647 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 284:85] + _T_647 <= _T_646 @[el2_dma_ctrl.scala 284:85] + fifo_error[4] <= _T_647 @[el2_dma_ctrl.scala 284:50] + node _T_648 = bits(fifo_error_bus_en, 0, 0) @[el2_dma_ctrl.scala 286:111] + node _T_649 = bits(fifo_error_bus, 0, 0) @[el2_dma_ctrl.scala 286:135] + node _T_650 = mux(_T_648, UInt<1>("h01"), _T_649) @[el2_dma_ctrl.scala 286:93] + node _T_651 = bits(fifo_reset, 0, 0) @[el2_dma_ctrl.scala 286:153] + node _T_652 = eq(_T_651, UInt<1>("h00")) @[el2_dma_ctrl.scala 286:142] + node _T_653 = and(_T_650, _T_652) @[el2_dma_ctrl.scala 286:140] + reg _T_654 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 286:89] + _T_654 <= _T_653 @[el2_dma_ctrl.scala 286:89] + node _T_655 = bits(fifo_error_bus_en, 1, 1) @[el2_dma_ctrl.scala 286:111] + node _T_656 = bits(fifo_error_bus, 1, 1) @[el2_dma_ctrl.scala 286:135] + node _T_657 = mux(_T_655, UInt<1>("h01"), _T_656) @[el2_dma_ctrl.scala 286:93] + node _T_658 = bits(fifo_reset, 1, 1) @[el2_dma_ctrl.scala 286:153] + node _T_659 = eq(_T_658, UInt<1>("h00")) @[el2_dma_ctrl.scala 286:142] + node _T_660 = and(_T_657, _T_659) @[el2_dma_ctrl.scala 286:140] + reg _T_661 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 286:89] + _T_661 <= _T_660 @[el2_dma_ctrl.scala 286:89] + node _T_662 = bits(fifo_error_bus_en, 2, 2) @[el2_dma_ctrl.scala 286:111] + node _T_663 = bits(fifo_error_bus, 2, 2) @[el2_dma_ctrl.scala 286:135] + node _T_664 = mux(_T_662, UInt<1>("h01"), _T_663) @[el2_dma_ctrl.scala 286:93] + node _T_665 = bits(fifo_reset, 2, 2) @[el2_dma_ctrl.scala 286:153] + node _T_666 = eq(_T_665, UInt<1>("h00")) @[el2_dma_ctrl.scala 286:142] + node _T_667 = and(_T_664, _T_666) @[el2_dma_ctrl.scala 286:140] + reg _T_668 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 286:89] + _T_668 <= _T_667 @[el2_dma_ctrl.scala 286:89] + node _T_669 = bits(fifo_error_bus_en, 3, 3) @[el2_dma_ctrl.scala 286:111] + node _T_670 = bits(fifo_error_bus, 3, 3) @[el2_dma_ctrl.scala 286:135] + node _T_671 = mux(_T_669, UInt<1>("h01"), _T_670) @[el2_dma_ctrl.scala 286:93] + node _T_672 = bits(fifo_reset, 3, 3) @[el2_dma_ctrl.scala 286:153] + node _T_673 = eq(_T_672, UInt<1>("h00")) @[el2_dma_ctrl.scala 286:142] + node _T_674 = and(_T_671, _T_673) @[el2_dma_ctrl.scala 286:140] + reg _T_675 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 286:89] + _T_675 <= _T_674 @[el2_dma_ctrl.scala 286:89] + node _T_676 = bits(fifo_error_bus_en, 4, 4) @[el2_dma_ctrl.scala 286:111] + node _T_677 = bits(fifo_error_bus, 4, 4) @[el2_dma_ctrl.scala 286:135] + node _T_678 = mux(_T_676, UInt<1>("h01"), _T_677) @[el2_dma_ctrl.scala 286:93] + node _T_679 = bits(fifo_reset, 4, 4) @[el2_dma_ctrl.scala 286:153] + node _T_680 = eq(_T_679, UInt<1>("h00")) @[el2_dma_ctrl.scala 286:142] + node _T_681 = and(_T_678, _T_680) @[el2_dma_ctrl.scala 286:140] + reg _T_682 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 286:89] + _T_682 <= _T_681 @[el2_dma_ctrl.scala 286:89] + node _T_683 = cat(_T_682, _T_675) @[Cat.scala 29:58] + node _T_684 = cat(_T_683, _T_668) @[Cat.scala 29:58] + node _T_685 = cat(_T_684, _T_661) @[Cat.scala 29:58] + node _T_686 = cat(_T_685, _T_654) @[Cat.scala 29:58] + fifo_error_bus <= _T_686 @[el2_dma_ctrl.scala 286:21] + node _T_687 = bits(fifo_pend_en, 0, 0) @[el2_dma_ctrl.scala 288:106] + node _T_688 = bits(fifo_rpend, 0, 0) @[el2_dma_ctrl.scala 288:126] + node _T_689 = mux(_T_687, UInt<1>("h01"), _T_688) @[el2_dma_ctrl.scala 288:93] + node _T_690 = bits(fifo_reset, 0, 0) @[el2_dma_ctrl.scala 288:144] + node _T_691 = eq(_T_690, UInt<1>("h00")) @[el2_dma_ctrl.scala 288:133] + node _T_692 = and(_T_689, _T_691) @[el2_dma_ctrl.scala 288:131] + reg _T_693 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 288:89] + _T_693 <= _T_692 @[el2_dma_ctrl.scala 288:89] + node _T_694 = bits(fifo_pend_en, 1, 1) @[el2_dma_ctrl.scala 288:106] + node _T_695 = bits(fifo_rpend, 1, 1) @[el2_dma_ctrl.scala 288:126] + node _T_696 = mux(_T_694, UInt<1>("h01"), _T_695) @[el2_dma_ctrl.scala 288:93] + node _T_697 = bits(fifo_reset, 1, 1) @[el2_dma_ctrl.scala 288:144] + node _T_698 = eq(_T_697, UInt<1>("h00")) @[el2_dma_ctrl.scala 288:133] + node _T_699 = and(_T_696, _T_698) @[el2_dma_ctrl.scala 288:131] + reg _T_700 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 288:89] + _T_700 <= _T_699 @[el2_dma_ctrl.scala 288:89] + node _T_701 = bits(fifo_pend_en, 2, 2) @[el2_dma_ctrl.scala 288:106] + node _T_702 = bits(fifo_rpend, 2, 2) @[el2_dma_ctrl.scala 288:126] + node _T_703 = mux(_T_701, UInt<1>("h01"), _T_702) @[el2_dma_ctrl.scala 288:93] + node _T_704 = bits(fifo_reset, 2, 2) @[el2_dma_ctrl.scala 288:144] + node _T_705 = eq(_T_704, UInt<1>("h00")) @[el2_dma_ctrl.scala 288:133] + node _T_706 = and(_T_703, _T_705) @[el2_dma_ctrl.scala 288:131] + reg _T_707 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 288:89] + _T_707 <= _T_706 @[el2_dma_ctrl.scala 288:89] + node _T_708 = bits(fifo_pend_en, 3, 3) @[el2_dma_ctrl.scala 288:106] + node _T_709 = bits(fifo_rpend, 3, 3) @[el2_dma_ctrl.scala 288:126] + node _T_710 = mux(_T_708, UInt<1>("h01"), _T_709) @[el2_dma_ctrl.scala 288:93] + node _T_711 = bits(fifo_reset, 3, 3) @[el2_dma_ctrl.scala 288:144] + node _T_712 = eq(_T_711, UInt<1>("h00")) @[el2_dma_ctrl.scala 288:133] + node _T_713 = and(_T_710, _T_712) @[el2_dma_ctrl.scala 288:131] + reg _T_714 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 288:89] + _T_714 <= _T_713 @[el2_dma_ctrl.scala 288:89] + node _T_715 = bits(fifo_pend_en, 4, 4) @[el2_dma_ctrl.scala 288:106] + node _T_716 = bits(fifo_rpend, 4, 4) @[el2_dma_ctrl.scala 288:126] + node _T_717 = mux(_T_715, UInt<1>("h01"), _T_716) @[el2_dma_ctrl.scala 288:93] + node _T_718 = bits(fifo_reset, 4, 4) @[el2_dma_ctrl.scala 288:144] + node _T_719 = eq(_T_718, UInt<1>("h00")) @[el2_dma_ctrl.scala 288:133] + node _T_720 = and(_T_717, _T_719) @[el2_dma_ctrl.scala 288:131] + reg _T_721 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 288:89] + _T_721 <= _T_720 @[el2_dma_ctrl.scala 288:89] + node _T_722 = cat(_T_721, _T_714) @[Cat.scala 29:58] + node _T_723 = cat(_T_722, _T_707) @[Cat.scala 29:58] + node _T_724 = cat(_T_723, _T_700) @[Cat.scala 29:58] + node _T_725 = cat(_T_724, _T_693) @[Cat.scala 29:58] + fifo_rpend <= _T_725 @[el2_dma_ctrl.scala 288:21] + node _T_726 = bits(fifo_done_en, 0, 0) @[el2_dma_ctrl.scala 290:106] + node _T_727 = bits(fifo_done, 0, 0) @[el2_dma_ctrl.scala 290:125] + node _T_728 = mux(_T_726, UInt<1>("h01"), _T_727) @[el2_dma_ctrl.scala 290:93] + node _T_729 = bits(fifo_reset, 0, 0) @[el2_dma_ctrl.scala 290:143] + node _T_730 = eq(_T_729, UInt<1>("h00")) @[el2_dma_ctrl.scala 290:132] + node _T_731 = and(_T_728, _T_730) @[el2_dma_ctrl.scala 290:130] + reg _T_732 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 290:89] + _T_732 <= _T_731 @[el2_dma_ctrl.scala 290:89] + node _T_733 = bits(fifo_done_en, 1, 1) @[el2_dma_ctrl.scala 290:106] + node _T_734 = bits(fifo_done, 1, 1) @[el2_dma_ctrl.scala 290:125] + node _T_735 = mux(_T_733, UInt<1>("h01"), _T_734) @[el2_dma_ctrl.scala 290:93] + node _T_736 = bits(fifo_reset, 1, 1) @[el2_dma_ctrl.scala 290:143] + node _T_737 = eq(_T_736, UInt<1>("h00")) @[el2_dma_ctrl.scala 290:132] + node _T_738 = and(_T_735, _T_737) @[el2_dma_ctrl.scala 290:130] + reg _T_739 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 290:89] + _T_739 <= _T_738 @[el2_dma_ctrl.scala 290:89] + node _T_740 = bits(fifo_done_en, 2, 2) @[el2_dma_ctrl.scala 290:106] + node _T_741 = bits(fifo_done, 2, 2) @[el2_dma_ctrl.scala 290:125] + node _T_742 = mux(_T_740, UInt<1>("h01"), _T_741) @[el2_dma_ctrl.scala 290:93] + node _T_743 = bits(fifo_reset, 2, 2) @[el2_dma_ctrl.scala 290:143] + node _T_744 = eq(_T_743, UInt<1>("h00")) @[el2_dma_ctrl.scala 290:132] + node _T_745 = and(_T_742, _T_744) @[el2_dma_ctrl.scala 290:130] + reg _T_746 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 290:89] + _T_746 <= _T_745 @[el2_dma_ctrl.scala 290:89] + node _T_747 = bits(fifo_done_en, 3, 3) @[el2_dma_ctrl.scala 290:106] + node _T_748 = bits(fifo_done, 3, 3) @[el2_dma_ctrl.scala 290:125] + node _T_749 = mux(_T_747, UInt<1>("h01"), _T_748) @[el2_dma_ctrl.scala 290:93] + node _T_750 = bits(fifo_reset, 3, 3) @[el2_dma_ctrl.scala 290:143] + node _T_751 = eq(_T_750, UInt<1>("h00")) @[el2_dma_ctrl.scala 290:132] + node _T_752 = and(_T_749, _T_751) @[el2_dma_ctrl.scala 290:130] + reg _T_753 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 290:89] + _T_753 <= _T_752 @[el2_dma_ctrl.scala 290:89] + node _T_754 = bits(fifo_done_en, 4, 4) @[el2_dma_ctrl.scala 290:106] + node _T_755 = bits(fifo_done, 4, 4) @[el2_dma_ctrl.scala 290:125] + node _T_756 = mux(_T_754, UInt<1>("h01"), _T_755) @[el2_dma_ctrl.scala 290:93] + node _T_757 = bits(fifo_reset, 4, 4) @[el2_dma_ctrl.scala 290:143] + node _T_758 = eq(_T_757, UInt<1>("h00")) @[el2_dma_ctrl.scala 290:132] + node _T_759 = and(_T_756, _T_758) @[el2_dma_ctrl.scala 290:130] + reg _T_760 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 290:89] + _T_760 <= _T_759 @[el2_dma_ctrl.scala 290:89] + node _T_761 = cat(_T_760, _T_753) @[Cat.scala 29:58] + node _T_762 = cat(_T_761, _T_746) @[Cat.scala 29:58] + node _T_763 = cat(_T_762, _T_739) @[Cat.scala 29:58] + node _T_764 = cat(_T_763, _T_732) @[Cat.scala 29:58] + fifo_done <= _T_764 @[el2_dma_ctrl.scala 290:21] + node _T_765 = bits(fifo_done_bus_en, 0, 0) @[el2_dma_ctrl.scala 292:110] + node _T_766 = bits(fifo_done_bus, 0, 0) @[el2_dma_ctrl.scala 292:133] + node _T_767 = mux(_T_765, UInt<1>("h01"), _T_766) @[el2_dma_ctrl.scala 292:93] + node _T_768 = bits(fifo_reset, 0, 0) @[el2_dma_ctrl.scala 292:151] + node _T_769 = eq(_T_768, UInt<1>("h00")) @[el2_dma_ctrl.scala 292:140] + node _T_770 = and(_T_767, _T_769) @[el2_dma_ctrl.scala 292:138] + reg _T_771 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 292:89] + _T_771 <= _T_770 @[el2_dma_ctrl.scala 292:89] + node _T_772 = bits(fifo_done_bus_en, 1, 1) @[el2_dma_ctrl.scala 292:110] + node _T_773 = bits(fifo_done_bus, 1, 1) @[el2_dma_ctrl.scala 292:133] + node _T_774 = mux(_T_772, UInt<1>("h01"), _T_773) @[el2_dma_ctrl.scala 292:93] + node _T_775 = bits(fifo_reset, 1, 1) @[el2_dma_ctrl.scala 292:151] + node _T_776 = eq(_T_775, UInt<1>("h00")) @[el2_dma_ctrl.scala 292:140] + node _T_777 = and(_T_774, _T_776) @[el2_dma_ctrl.scala 292:138] + reg _T_778 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 292:89] + _T_778 <= _T_777 @[el2_dma_ctrl.scala 292:89] + node _T_779 = bits(fifo_done_bus_en, 2, 2) @[el2_dma_ctrl.scala 292:110] + node _T_780 = bits(fifo_done_bus, 2, 2) @[el2_dma_ctrl.scala 292:133] + node _T_781 = mux(_T_779, UInt<1>("h01"), _T_780) @[el2_dma_ctrl.scala 292:93] + node _T_782 = bits(fifo_reset, 2, 2) @[el2_dma_ctrl.scala 292:151] + node _T_783 = eq(_T_782, UInt<1>("h00")) @[el2_dma_ctrl.scala 292:140] + node _T_784 = and(_T_781, _T_783) @[el2_dma_ctrl.scala 292:138] + reg _T_785 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 292:89] + _T_785 <= _T_784 @[el2_dma_ctrl.scala 292:89] + node _T_786 = bits(fifo_done_bus_en, 3, 3) @[el2_dma_ctrl.scala 292:110] + node _T_787 = bits(fifo_done_bus, 3, 3) @[el2_dma_ctrl.scala 292:133] + node _T_788 = mux(_T_786, UInt<1>("h01"), _T_787) @[el2_dma_ctrl.scala 292:93] + node _T_789 = bits(fifo_reset, 3, 3) @[el2_dma_ctrl.scala 292:151] + node _T_790 = eq(_T_789, UInt<1>("h00")) @[el2_dma_ctrl.scala 292:140] + node _T_791 = and(_T_788, _T_790) @[el2_dma_ctrl.scala 292:138] + reg _T_792 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 292:89] + _T_792 <= _T_791 @[el2_dma_ctrl.scala 292:89] + node _T_793 = bits(fifo_done_bus_en, 4, 4) @[el2_dma_ctrl.scala 292:110] + node _T_794 = bits(fifo_done_bus, 4, 4) @[el2_dma_ctrl.scala 292:133] + node _T_795 = mux(_T_793, UInt<1>("h01"), _T_794) @[el2_dma_ctrl.scala 292:93] + node _T_796 = bits(fifo_reset, 4, 4) @[el2_dma_ctrl.scala 292:151] + node _T_797 = eq(_T_796, UInt<1>("h00")) @[el2_dma_ctrl.scala 292:140] + node _T_798 = and(_T_795, _T_797) @[el2_dma_ctrl.scala 292:138] + reg _T_799 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 292:89] + _T_799 <= _T_798 @[el2_dma_ctrl.scala 292:89] + node _T_800 = cat(_T_799, _T_792) @[Cat.scala 29:58] + node _T_801 = cat(_T_800, _T_785) @[Cat.scala 29:58] + node _T_802 = cat(_T_801, _T_778) @[Cat.scala 29:58] + node _T_803 = cat(_T_802, _T_771) @[Cat.scala 29:58] + fifo_done_bus <= _T_803 @[el2_dma_ctrl.scala 292:21] + node _T_804 = bits(fifo_cmd_en, 0, 0) @[el2_dma_ctrl.scala 294:84] + inst rvclkhdr of rvclkhdr @[el2_lib.scala 508:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr.io.en <= _T_804 @[el2_lib.scala 511:17] + rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_805 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_805 <= fifo_addr_in @[el2_lib.scala 514:16] + fifo_addr[0] <= _T_805 @[el2_dma_ctrl.scala 294:49] + node _T_806 = bits(fifo_cmd_en, 1, 1) @[el2_dma_ctrl.scala 294:84] + inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 508:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_1.io.en <= _T_806 @[el2_lib.scala 511:17] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_807 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_807 <= fifo_addr_in @[el2_lib.scala 514:16] + fifo_addr[1] <= _T_807 @[el2_dma_ctrl.scala 294:49] + node _T_808 = bits(fifo_cmd_en, 2, 2) @[el2_dma_ctrl.scala 294:84] + inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 508:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_2.io.en <= _T_808 @[el2_lib.scala 511:17] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_809 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_809 <= fifo_addr_in @[el2_lib.scala 514:16] + fifo_addr[2] <= _T_809 @[el2_dma_ctrl.scala 294:49] + node _T_810 = bits(fifo_cmd_en, 3, 3) @[el2_dma_ctrl.scala 294:84] + inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 508:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_3.io.en <= _T_810 @[el2_lib.scala 511:17] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_811 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_811 <= fifo_addr_in @[el2_lib.scala 514:16] + fifo_addr[3] <= _T_811 @[el2_dma_ctrl.scala 294:49] + node _T_812 = bits(fifo_cmd_en, 4, 4) @[el2_dma_ctrl.scala 294:84] + inst rvclkhdr_4 of rvclkhdr_4 @[el2_lib.scala 508:23] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= reset + rvclkhdr_4.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_4.io.en <= _T_812 @[el2_lib.scala 511:17] + rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_813 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_813 <= fifo_addr_in @[el2_lib.scala 514:16] + fifo_addr[4] <= _T_813 @[el2_dma_ctrl.scala 294:49] + node _T_814 = bits(fifo_sz_in, 2, 0) @[el2_dma_ctrl.scala 296:100] + node _T_815 = bits(fifo_cmd_en, 0, 0) @[el2_dma_ctrl.scala 296:123] + reg _T_816 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_815 : @[Reg.scala 28:19] + _T_816 <= _T_814 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + fifo_sz[0] <= _T_816 @[el2_dma_ctrl.scala 296:47] + node _T_817 = bits(fifo_sz_in, 2, 0) @[el2_dma_ctrl.scala 296:100] + node _T_818 = bits(fifo_cmd_en, 1, 1) @[el2_dma_ctrl.scala 296:123] + reg _T_819 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_818 : @[Reg.scala 28:19] + _T_819 <= _T_817 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + fifo_sz[1] <= _T_819 @[el2_dma_ctrl.scala 296:47] + node _T_820 = bits(fifo_sz_in, 2, 0) @[el2_dma_ctrl.scala 296:100] + node _T_821 = bits(fifo_cmd_en, 2, 2) @[el2_dma_ctrl.scala 296:123] + reg _T_822 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_821 : @[Reg.scala 28:19] + _T_822 <= _T_820 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + fifo_sz[2] <= _T_822 @[el2_dma_ctrl.scala 296:47] + node _T_823 = bits(fifo_sz_in, 2, 0) @[el2_dma_ctrl.scala 296:100] + node _T_824 = bits(fifo_cmd_en, 3, 3) @[el2_dma_ctrl.scala 296:123] + reg _T_825 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_824 : @[Reg.scala 28:19] + _T_825 <= _T_823 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + fifo_sz[3] <= _T_825 @[el2_dma_ctrl.scala 296:47] + node _T_826 = bits(fifo_sz_in, 2, 0) @[el2_dma_ctrl.scala 296:100] + node _T_827 = bits(fifo_cmd_en, 4, 4) @[el2_dma_ctrl.scala 296:123] + reg _T_828 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_827 : @[Reg.scala 28:19] + _T_828 <= _T_826 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + fifo_sz[4] <= _T_828 @[el2_dma_ctrl.scala 296:47] + node _T_829 = bits(fifo_byteen_in, 7, 0) @[el2_dma_ctrl.scala 298:108] + node _T_830 = bits(fifo_cmd_en, 0, 0) @[el2_dma_ctrl.scala 298:131] + node _T_831 = bits(_T_830, 0, 0) @[el2_dma_ctrl.scala 298:141] + reg _T_832 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_831 : @[Reg.scala 28:19] + _T_832 <= _T_829 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + fifo_byteen[0] <= _T_832 @[el2_dma_ctrl.scala 298:51] + node _T_833 = bits(fifo_byteen_in, 7, 0) @[el2_dma_ctrl.scala 298:108] + node _T_834 = bits(fifo_cmd_en, 1, 1) @[el2_dma_ctrl.scala 298:131] + node _T_835 = bits(_T_834, 0, 0) @[el2_dma_ctrl.scala 298:141] + reg _T_836 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_835 : @[Reg.scala 28:19] + _T_836 <= _T_833 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + fifo_byteen[1] <= _T_836 @[el2_dma_ctrl.scala 298:51] + node _T_837 = bits(fifo_byteen_in, 7, 0) @[el2_dma_ctrl.scala 298:108] + node _T_838 = bits(fifo_cmd_en, 2, 2) @[el2_dma_ctrl.scala 298:131] + node _T_839 = bits(_T_838, 0, 0) @[el2_dma_ctrl.scala 298:141] + reg _T_840 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_839 : @[Reg.scala 28:19] + _T_840 <= _T_837 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + fifo_byteen[2] <= _T_840 @[el2_dma_ctrl.scala 298:51] + node _T_841 = bits(fifo_byteen_in, 7, 0) @[el2_dma_ctrl.scala 298:108] + node _T_842 = bits(fifo_cmd_en, 3, 3) @[el2_dma_ctrl.scala 298:131] + node _T_843 = bits(_T_842, 0, 0) @[el2_dma_ctrl.scala 298:141] + reg _T_844 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_843 : @[Reg.scala 28:19] + _T_844 <= _T_841 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + fifo_byteen[3] <= _T_844 @[el2_dma_ctrl.scala 298:51] + node _T_845 = bits(fifo_byteen_in, 7, 0) @[el2_dma_ctrl.scala 298:108] + node _T_846 = bits(fifo_cmd_en, 4, 4) @[el2_dma_ctrl.scala 298:131] + node _T_847 = bits(_T_846, 0, 0) @[el2_dma_ctrl.scala 298:141] + reg _T_848 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_847 : @[Reg.scala 28:19] + _T_848 <= _T_845 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + fifo_byteen[4] <= _T_848 @[el2_dma_ctrl.scala 298:51] + node _T_849 = bits(fifo_cmd_en, 0, 0) @[el2_dma_ctrl.scala 300:129] + reg _T_850 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_849 : @[Reg.scala 28:19] + _T_850 <= fifo_write_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_851 = bits(fifo_cmd_en, 1, 1) @[el2_dma_ctrl.scala 300:129] + reg _T_852 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_851 : @[Reg.scala 28:19] + _T_852 <= fifo_write_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_853 = bits(fifo_cmd_en, 2, 2) @[el2_dma_ctrl.scala 300:129] + reg _T_854 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_853 : @[Reg.scala 28:19] + _T_854 <= fifo_write_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_855 = bits(fifo_cmd_en, 3, 3) @[el2_dma_ctrl.scala 300:129] + reg _T_856 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_855 : @[Reg.scala 28:19] + _T_856 <= fifo_write_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_857 = bits(fifo_cmd_en, 4, 4) @[el2_dma_ctrl.scala 300:129] + reg _T_858 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_857 : @[Reg.scala 28:19] + _T_858 <= fifo_write_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_859 = cat(_T_858, _T_856) @[Cat.scala 29:58] + node _T_860 = cat(_T_859, _T_854) @[Cat.scala 29:58] + node _T_861 = cat(_T_860, _T_852) @[Cat.scala 29:58] + node _T_862 = cat(_T_861, _T_850) @[Cat.scala 29:58] + fifo_write <= _T_862 @[el2_dma_ctrl.scala 300:21] + node _T_863 = bits(fifo_cmd_en, 0, 0) @[el2_dma_ctrl.scala 302:136] + reg _T_864 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_863 : @[Reg.scala 28:19] + _T_864 <= fifo_posted_write_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_865 = bits(fifo_cmd_en, 1, 1) @[el2_dma_ctrl.scala 302:136] + reg _T_866 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_865 : @[Reg.scala 28:19] + _T_866 <= fifo_posted_write_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_867 = bits(fifo_cmd_en, 2, 2) @[el2_dma_ctrl.scala 302:136] + reg _T_868 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_867 : @[Reg.scala 28:19] + _T_868 <= fifo_posted_write_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_869 = bits(fifo_cmd_en, 3, 3) @[el2_dma_ctrl.scala 302:136] + reg _T_870 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_869 : @[Reg.scala 28:19] + _T_870 <= fifo_posted_write_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_871 = bits(fifo_cmd_en, 4, 4) @[el2_dma_ctrl.scala 302:136] + reg _T_872 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_871 : @[Reg.scala 28:19] + _T_872 <= fifo_posted_write_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_873 = cat(_T_872, _T_870) @[Cat.scala 29:58] + node _T_874 = cat(_T_873, _T_868) @[Cat.scala 29:58] + node _T_875 = cat(_T_874, _T_866) @[Cat.scala 29:58] + node _T_876 = cat(_T_875, _T_864) @[Cat.scala 29:58] + fifo_posted_write <= _T_876 @[el2_dma_ctrl.scala 302:21] + node _T_877 = bits(fifo_cmd_en, 0, 0) @[el2_dma_ctrl.scala 304:126] + reg _T_878 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_877 : @[Reg.scala 28:19] + _T_878 <= io.dbg_cmd_valid @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_879 = bits(fifo_cmd_en, 1, 1) @[el2_dma_ctrl.scala 304:126] + reg _T_880 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_879 : @[Reg.scala 28:19] + _T_880 <= io.dbg_cmd_valid @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_881 = bits(fifo_cmd_en, 2, 2) @[el2_dma_ctrl.scala 304:126] + reg _T_882 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_881 : @[Reg.scala 28:19] + _T_882 <= io.dbg_cmd_valid @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_883 = bits(fifo_cmd_en, 3, 3) @[el2_dma_ctrl.scala 304:126] + reg _T_884 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_883 : @[Reg.scala 28:19] + _T_884 <= io.dbg_cmd_valid @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_885 = bits(fifo_cmd_en, 4, 4) @[el2_dma_ctrl.scala 304:126] + reg _T_886 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_885 : @[Reg.scala 28:19] + _T_886 <= io.dbg_cmd_valid @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_887 = cat(_T_886, _T_884) @[Cat.scala 29:58] + node _T_888 = cat(_T_887, _T_882) @[Cat.scala 29:58] + node _T_889 = cat(_T_888, _T_880) @[Cat.scala 29:58] + node _T_890 = cat(_T_889, _T_878) @[Cat.scala 29:58] + fifo_dbg <= _T_890 @[el2_dma_ctrl.scala 304:21] + node _T_891 = bits(fifo_data_en, 0, 0) @[el2_dma_ctrl.scala 306:88] + inst rvclkhdr_5 of rvclkhdr_5 @[el2_lib.scala 508:23] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= reset + rvclkhdr_5.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_5.io.en <= _T_891 @[el2_lib.scala 511:17] + rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_892 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_892 <= fifo_data_in[0] @[el2_lib.scala 514:16] + fifo_data[0] <= _T_892 @[el2_dma_ctrl.scala 306:49] + node _T_893 = bits(fifo_data_en, 1, 1) @[el2_dma_ctrl.scala 306:88] + inst rvclkhdr_6 of rvclkhdr_6 @[el2_lib.scala 508:23] + rvclkhdr_6.clock <= clock + rvclkhdr_6.reset <= reset + rvclkhdr_6.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_6.io.en <= _T_893 @[el2_lib.scala 511:17] + rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_894 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_894 <= fifo_data_in[1] @[el2_lib.scala 514:16] + fifo_data[1] <= _T_894 @[el2_dma_ctrl.scala 306:49] + node _T_895 = bits(fifo_data_en, 2, 2) @[el2_dma_ctrl.scala 306:88] + inst rvclkhdr_7 of rvclkhdr_7 @[el2_lib.scala 508:23] + rvclkhdr_7.clock <= clock + rvclkhdr_7.reset <= reset + rvclkhdr_7.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_7.io.en <= _T_895 @[el2_lib.scala 511:17] + rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_896 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_896 <= fifo_data_in[2] @[el2_lib.scala 514:16] + fifo_data[2] <= _T_896 @[el2_dma_ctrl.scala 306:49] + node _T_897 = bits(fifo_data_en, 3, 3) @[el2_dma_ctrl.scala 306:88] + inst rvclkhdr_8 of rvclkhdr_8 @[el2_lib.scala 508:23] + rvclkhdr_8.clock <= clock + rvclkhdr_8.reset <= reset + rvclkhdr_8.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_8.io.en <= _T_897 @[el2_lib.scala 511:17] + rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_898 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_898 <= fifo_data_in[3] @[el2_lib.scala 514:16] + fifo_data[3] <= _T_898 @[el2_dma_ctrl.scala 306:49] + node _T_899 = bits(fifo_data_en, 4, 4) @[el2_dma_ctrl.scala 306:88] + inst rvclkhdr_9 of rvclkhdr_9 @[el2_lib.scala 508:23] + rvclkhdr_9.clock <= clock + rvclkhdr_9.reset <= reset + rvclkhdr_9.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_9.io.en <= _T_899 @[el2_lib.scala 511:17] + rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_900 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_900 <= fifo_data_in[4] @[el2_lib.scala 514:16] + fifo_data[4] <= _T_900 @[el2_dma_ctrl.scala 306:49] + node _T_901 = bits(fifo_cmd_en, 0, 0) @[el2_dma_ctrl.scala 308:120] + reg _T_902 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_901 : @[Reg.scala 28:19] + _T_902 <= bus_cmd_tag @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + fifo_tag[0] <= _T_902 @[el2_dma_ctrl.scala 308:48] + node _T_903 = bits(fifo_cmd_en, 1, 1) @[el2_dma_ctrl.scala 308:120] + reg _T_904 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_903 : @[Reg.scala 28:19] + _T_904 <= bus_cmd_tag @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + fifo_tag[1] <= _T_904 @[el2_dma_ctrl.scala 308:48] + node _T_905 = bits(fifo_cmd_en, 2, 2) @[el2_dma_ctrl.scala 308:120] + reg _T_906 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_905 : @[Reg.scala 28:19] + _T_906 <= bus_cmd_tag @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + fifo_tag[2] <= _T_906 @[el2_dma_ctrl.scala 308:48] + node _T_907 = bits(fifo_cmd_en, 3, 3) @[el2_dma_ctrl.scala 308:120] + reg _T_908 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_907 : @[Reg.scala 28:19] + _T_908 <= bus_cmd_tag @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + fifo_tag[3] <= _T_908 @[el2_dma_ctrl.scala 308:48] + node _T_909 = bits(fifo_cmd_en, 4, 4) @[el2_dma_ctrl.scala 308:120] + reg _T_910 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_909 : @[Reg.scala 28:19] + _T_910 <= bus_cmd_tag @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + fifo_tag[4] <= _T_910 @[el2_dma_ctrl.scala 308:48] + node _T_911 = bits(fifo_cmd_en, 0, 0) @[el2_dma_ctrl.scala 310:120] + reg _T_912 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_911 : @[Reg.scala 28:19] + _T_912 <= bus_cmd_mid @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + fifo_mid[0] <= _T_912 @[el2_dma_ctrl.scala 310:48] + node _T_913 = bits(fifo_cmd_en, 1, 1) @[el2_dma_ctrl.scala 310:120] + reg _T_914 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_913 : @[Reg.scala 28:19] + _T_914 <= bus_cmd_mid @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + fifo_mid[1] <= _T_914 @[el2_dma_ctrl.scala 310:48] + node _T_915 = bits(fifo_cmd_en, 2, 2) @[el2_dma_ctrl.scala 310:120] + reg _T_916 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_915 : @[Reg.scala 28:19] + _T_916 <= bus_cmd_mid @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + fifo_mid[2] <= _T_916 @[el2_dma_ctrl.scala 310:48] + node _T_917 = bits(fifo_cmd_en, 3, 3) @[el2_dma_ctrl.scala 310:120] + reg _T_918 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_917 : @[Reg.scala 28:19] + _T_918 <= bus_cmd_mid @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + fifo_mid[3] <= _T_918 @[el2_dma_ctrl.scala 310:48] + node _T_919 = bits(fifo_cmd_en, 4, 4) @[el2_dma_ctrl.scala 310:120] + reg _T_920 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_919 : @[Reg.scala 28:19] + _T_920 <= bus_cmd_mid @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + fifo_mid[4] <= _T_920 @[el2_dma_ctrl.scala 310:48] + node _T_921 = bits(fifo_cmd_en, 0, 0) @[el2_dma_ctrl.scala 312:122] + reg _T_922 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_921 : @[Reg.scala 28:19] + _T_922 <= bus_cmd_prty @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + fifo_prty[0] <= _T_922 @[el2_dma_ctrl.scala 312:49] + node _T_923 = bits(fifo_cmd_en, 1, 1) @[el2_dma_ctrl.scala 312:122] + reg _T_924 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_923 : @[Reg.scala 28:19] + _T_924 <= bus_cmd_prty @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + fifo_prty[1] <= _T_924 @[el2_dma_ctrl.scala 312:49] + node _T_925 = bits(fifo_cmd_en, 2, 2) @[el2_dma_ctrl.scala 312:122] + reg _T_926 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_925 : @[Reg.scala 28:19] + _T_926 <= bus_cmd_prty @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + fifo_prty[2] <= _T_926 @[el2_dma_ctrl.scala 312:49] + node _T_927 = bits(fifo_cmd_en, 3, 3) @[el2_dma_ctrl.scala 312:122] + reg _T_928 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_927 : @[Reg.scala 28:19] + _T_928 <= bus_cmd_prty @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + fifo_prty[3] <= _T_928 @[el2_dma_ctrl.scala 312:49] + node _T_929 = bits(fifo_cmd_en, 4, 4) @[el2_dma_ctrl.scala 312:122] + reg _T_930 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_929 : @[Reg.scala 28:19] + _T_930 <= bus_cmd_prty @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + fifo_prty[4] <= _T_930 @[el2_dma_ctrl.scala 312:49] + node _T_931 = eq(WrPtr, UInt<3>("h04")) @[el2_dma_ctrl.scala 316:30] + node _T_932 = bits(_T_931, 0, 0) @[el2_dma_ctrl.scala 316:57] + node _T_933 = add(WrPtr, UInt<1>("h01")) @[el2_dma_ctrl.scala 316:76] + node _T_934 = tail(_T_933, 1) @[el2_dma_ctrl.scala 316:76] + node _T_935 = mux(_T_932, UInt<1>("h00"), _T_934) @[el2_dma_ctrl.scala 316:22] + NxtWrPtr <= _T_935 @[el2_dma_ctrl.scala 316:16] + node _T_936 = eq(RdPtr, UInt<3>("h04")) @[el2_dma_ctrl.scala 318:30] + node _T_937 = bits(_T_936, 0, 0) @[el2_dma_ctrl.scala 318:57] + node _T_938 = add(RdPtr, UInt<1>("h01")) @[el2_dma_ctrl.scala 318:76] + node _T_939 = tail(_T_938, 1) @[el2_dma_ctrl.scala 318:76] + node _T_940 = mux(_T_937, UInt<1>("h00"), _T_939) @[el2_dma_ctrl.scala 318:22] + NxtRdPtr <= _T_940 @[el2_dma_ctrl.scala 318:16] + node _T_941 = eq(RspPtr, UInt<3>("h04")) @[el2_dma_ctrl.scala 320:31] + node _T_942 = bits(_T_941, 0, 0) @[el2_dma_ctrl.scala 320:58] + node _T_943 = add(RspPtr, UInt<1>("h01")) @[el2_dma_ctrl.scala 320:78] + node _T_944 = tail(_T_943, 1) @[el2_dma_ctrl.scala 320:78] + node _T_945 = mux(_T_942, UInt<1>("h00"), _T_944) @[el2_dma_ctrl.scala 320:22] + NxtRspPtr <= _T_945 @[el2_dma_ctrl.scala 320:16] + node WrPtrEn = orr(fifo_cmd_en) @[el2_dma_ctrl.scala 322:30] + node _T_946 = or(io.dma_dccm_req, io.dma_iccm_req) @[el2_dma_ctrl.scala 324:35] + node _T_947 = bits(dma_address_error, 0, 0) @[el2_dma_ctrl.scala 324:74] + node _T_948 = bits(dma_alignment_error, 0, 0) @[el2_dma_ctrl.scala 324:103] + node _T_949 = or(_T_947, _T_948) @[el2_dma_ctrl.scala 324:81] + node _T_950 = or(_T_949, dma_dbg_cmd_error) @[el2_dma_ctrl.scala 324:110] + node RdPtrEn = or(_T_946, _T_950) @[el2_dma_ctrl.scala 324:53] + node _T_951 = or(bus_rsp_sent, bus_posted_write_done) @[el2_dma_ctrl.scala 326:55] + node _T_952 = and(_T_951, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 326:80] + node RspPtrEn = or(io.dma_dbg_cmd_done, _T_952) @[el2_dma_ctrl.scala 326:39] + reg _T_953 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when WrPtrEn : @[Reg.scala 28:19] + _T_953 <= NxtWrPtr @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + WrPtr <= _T_953 @[el2_dma_ctrl.scala 328:16] + node _T_954 = bits(RdPtrEn, 0, 0) @[el2_dma_ctrl.scala 333:38] + reg _T_955 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_954 : @[Reg.scala 28:19] + _T_955 <= NxtRdPtr @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + RdPtr <= _T_955 @[el2_dma_ctrl.scala 332:16] + node _T_956 = bits(RspPtrEn, 0, 0) @[el2_dma_ctrl.scala 337:40] + reg _T_957 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_956 : @[Reg.scala 28:19] + _T_957 <= NxtRspPtr @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + RspPtr <= _T_957 @[el2_dma_ctrl.scala 336:16] + wire num_fifo_vld_tmp : UInt<4> + num_fifo_vld_tmp <= UInt<1>("h00") + wire num_fifo_vld_tmp2 : UInt<4> + num_fifo_vld_tmp2 <= UInt<1>("h00") + node _T_958 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_959 = cat(_T_958, axi_mstr_prty_en) @[Cat.scala 29:58] + node _T_960 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_961 = cat(_T_960, bus_rsp_sent) @[Cat.scala 29:58] + node _T_962 = sub(_T_959, _T_961) @[el2_dma_ctrl.scala 347:62] + node _T_963 = tail(_T_962, 1) @[el2_dma_ctrl.scala 347:62] + num_fifo_vld_tmp <= _T_963 @[el2_dma_ctrl.scala 347:25] + node _T_964 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_965 = bits(fifo_valid, 0, 0) @[el2_dma_ctrl.scala 349:88] + node _T_966 = cat(_T_964, _T_965) @[Cat.scala 29:58] + node _T_967 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_968 = bits(fifo_valid, 1, 1) @[el2_dma_ctrl.scala 349:88] + node _T_969 = cat(_T_967, _T_968) @[Cat.scala 29:58] + node _T_970 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_971 = bits(fifo_valid, 2, 2) @[el2_dma_ctrl.scala 349:88] + node _T_972 = cat(_T_970, _T_971) @[Cat.scala 29:58] + node _T_973 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_974 = bits(fifo_valid, 3, 3) @[el2_dma_ctrl.scala 349:88] + node _T_975 = cat(_T_973, _T_974) @[Cat.scala 29:58] + node _T_976 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_977 = bits(fifo_valid, 4, 4) @[el2_dma_ctrl.scala 349:88] + node _T_978 = cat(_T_976, _T_977) @[Cat.scala 29:58] + node _T_979 = add(_T_966, _T_969) @[el2_dma_ctrl.scala 349:102] + node _T_980 = tail(_T_979, 1) @[el2_dma_ctrl.scala 349:102] + node _T_981 = add(_T_980, _T_972) @[el2_dma_ctrl.scala 349:102] + node _T_982 = tail(_T_981, 1) @[el2_dma_ctrl.scala 349:102] + node _T_983 = add(_T_982, _T_975) @[el2_dma_ctrl.scala 349:102] + node _T_984 = tail(_T_983, 1) @[el2_dma_ctrl.scala 349:102] + node _T_985 = add(_T_984, _T_978) @[el2_dma_ctrl.scala 349:102] + node _T_986 = tail(_T_985, 1) @[el2_dma_ctrl.scala 349:102] + num_fifo_vld_tmp2 <= _T_986 @[el2_dma_ctrl.scala 349:25] + node _T_987 = add(num_fifo_vld_tmp, num_fifo_vld_tmp2) @[el2_dma_ctrl.scala 351:45] + node _T_988 = tail(_T_987, 1) @[el2_dma_ctrl.scala 351:45] + num_fifo_vld <= _T_988 @[el2_dma_ctrl.scala 351:25] + node fifo_full_spec = geq(num_fifo_vld_tmp2, UInt<3>("h05")) @[el2_dma_ctrl.scala 353:46] + node _T_989 = or(fifo_full, dbg_dma_bubble_bus) @[el2_dma_ctrl.scala 355:39] + node dma_fifo_ready = not(_T_989) @[el2_dma_ctrl.scala 355:27] + node _T_990 = dshr(fifo_valid, RdPtr) @[el2_dma_ctrl.scala 359:38] + node _T_991 = bits(_T_990, 0, 0) @[el2_dma_ctrl.scala 359:38] + node _T_992 = dshr(fifo_done, RdPtr) @[el2_dma_ctrl.scala 359:58] + node _T_993 = bits(_T_992, 0, 0) @[el2_dma_ctrl.scala 359:58] + node _T_994 = eq(_T_993, UInt<1>("h00")) @[el2_dma_ctrl.scala 359:48] + node _T_995 = and(_T_991, _T_994) @[el2_dma_ctrl.scala 359:46] + node _T_996 = dshr(fifo_dbg, RdPtr) @[el2_dma_ctrl.scala 359:77] + node _T_997 = bits(_T_996, 0, 0) @[el2_dma_ctrl.scala 359:77] + node _T_998 = eq(_T_997, UInt<1>("h00")) @[el2_dma_ctrl.scala 359:68] + node _T_999 = and(_T_995, _T_998) @[el2_dma_ctrl.scala 359:66] + node _T_1000 = or(dma_mem_addr_in_dccm, dma_mem_addr_in_iccm) @[el2_dma_ctrl.scala 359:111] + node _T_1001 = not(_T_1000) @[el2_dma_ctrl.scala 359:88] + node _T_1002 = and(_T_999, _T_1001) @[el2_dma_ctrl.scala 359:85] + dma_address_error <= _T_1002 @[el2_dma_ctrl.scala 359:25] + node _T_1003 = dshr(fifo_valid, RdPtr) @[el2_dma_ctrl.scala 360:38] + node _T_1004 = bits(_T_1003, 0, 0) @[el2_dma_ctrl.scala 360:38] + node _T_1005 = dshr(fifo_done, RdPtr) @[el2_dma_ctrl.scala 360:58] + node _T_1006 = bits(_T_1005, 0, 0) @[el2_dma_ctrl.scala 360:58] + node _T_1007 = eq(_T_1006, UInt<1>("h00")) @[el2_dma_ctrl.scala 360:48] + node _T_1008 = and(_T_1004, _T_1007) @[el2_dma_ctrl.scala 360:46] + node _T_1009 = eq(dma_address_error, UInt<1>("h00")) @[el2_dma_ctrl.scala 360:68] + node _T_1010 = and(_T_1008, _T_1009) @[el2_dma_ctrl.scala 360:66] + node _T_1011 = bits(dma_mem_sz_int, 2, 0) @[el2_dma_ctrl.scala 361:22] + node _T_1012 = eq(_T_1011, UInt<1>("h01")) @[el2_dma_ctrl.scala 361:28] + node _T_1013 = bits(dma_mem_addr_int, 0, 0) @[el2_dma_ctrl.scala 361:55] + node _T_1014 = and(_T_1012, _T_1013) @[el2_dma_ctrl.scala 361:37] + node _T_1015 = bits(dma_mem_sz_int, 2, 0) @[el2_dma_ctrl.scala 362:23] + node _T_1016 = eq(_T_1015, UInt<2>("h02")) @[el2_dma_ctrl.scala 362:29] + node _T_1017 = bits(dma_mem_addr_int, 1, 0) @[el2_dma_ctrl.scala 362:57] + node _T_1018 = orr(_T_1017) @[el2_dma_ctrl.scala 362:64] + node _T_1019 = and(_T_1016, _T_1018) @[el2_dma_ctrl.scala 362:38] + node _T_1020 = or(_T_1014, _T_1019) @[el2_dma_ctrl.scala 361:60] + node _T_1021 = bits(dma_mem_sz_int, 2, 0) @[el2_dma_ctrl.scala 363:23] + node _T_1022 = eq(_T_1021, UInt<2>("h03")) @[el2_dma_ctrl.scala 363:29] + node _T_1023 = bits(dma_mem_addr_int, 2, 0) @[el2_dma_ctrl.scala 363:57] + node _T_1024 = orr(_T_1023) @[el2_dma_ctrl.scala 363:64] + node _T_1025 = and(_T_1022, _T_1024) @[el2_dma_ctrl.scala 363:38] + node _T_1026 = or(_T_1020, _T_1025) @[el2_dma_ctrl.scala 362:70] + node _T_1027 = bits(dma_mem_sz_int, 1, 0) @[el2_dma_ctrl.scala 364:48] + node _T_1028 = eq(_T_1027, UInt<2>("h02")) @[el2_dma_ctrl.scala 364:55] + node _T_1029 = bits(dma_mem_sz_int, 1, 0) @[el2_dma_ctrl.scala 364:81] + node _T_1030 = eq(_T_1029, UInt<2>("h03")) @[el2_dma_ctrl.scala 364:88] + node _T_1031 = or(_T_1028, _T_1030) @[el2_dma_ctrl.scala 364:64] + node _T_1032 = not(_T_1031) @[el2_dma_ctrl.scala 364:31] + node _T_1033 = and(dma_mem_addr_in_iccm, _T_1032) @[el2_dma_ctrl.scala 364:29] + node _T_1034 = or(_T_1026, _T_1033) @[el2_dma_ctrl.scala 363:70] + node _T_1035 = and(dma_mem_addr_in_dccm, io.dma_mem_write) @[el2_dma_ctrl.scala 365:29] + node _T_1036 = bits(dma_mem_sz_int, 1, 0) @[el2_dma_ctrl.scala 365:67] + node _T_1037 = eq(_T_1036, UInt<2>("h02")) @[el2_dma_ctrl.scala 365:74] + node _T_1038 = bits(dma_mem_sz_int, 1, 0) @[el2_dma_ctrl.scala 365:100] + node _T_1039 = eq(_T_1038, UInt<2>("h03")) @[el2_dma_ctrl.scala 365:107] + node _T_1040 = or(_T_1037, _T_1039) @[el2_dma_ctrl.scala 365:83] + node _T_1041 = not(_T_1040) @[el2_dma_ctrl.scala 365:50] + node _T_1042 = and(_T_1035, _T_1041) @[el2_dma_ctrl.scala 365:48] + node _T_1043 = or(_T_1034, _T_1042) @[el2_dma_ctrl.scala 364:108] + node _T_1044 = bits(dma_mem_sz_int, 2, 0) @[el2_dma_ctrl.scala 366:42] + node _T_1045 = eq(_T_1044, UInt<2>("h02")) @[el2_dma_ctrl.scala 366:49] + node _T_1046 = and(io.dma_mem_write, _T_1045) @[el2_dma_ctrl.scala 366:25] + node _T_1047 = bits(dma_mem_addr_int, 2, 0) @[el2_dma_ctrl.scala 366:88] + node _T_1048 = eq(_T_1047, UInt<1>("h00")) @[el2_dma_ctrl.scala 366:94] + node _T_1049 = bits(dma_mem_byteen, 3, 0) @[el2_dma_ctrl.scala 366:121] + node _T_1050 = bits(dma_mem_addr_int, 2, 0) @[el2_dma_ctrl.scala 367:26] + node _T_1051 = eq(_T_1050, UInt<1>("h01")) @[el2_dma_ctrl.scala 367:32] + node _T_1052 = bits(dma_mem_byteen, 4, 1) @[el2_dma_ctrl.scala 367:59] + node _T_1053 = bits(dma_mem_addr_int, 2, 0) @[el2_dma_ctrl.scala 368:26] + node _T_1054 = eq(_T_1053, UInt<2>("h02")) @[el2_dma_ctrl.scala 368:32] + node _T_1055 = bits(dma_mem_byteen, 5, 2) @[el2_dma_ctrl.scala 368:59] + node _T_1056 = bits(dma_mem_addr_int, 2, 0) @[el2_dma_ctrl.scala 369:26] + node _T_1057 = eq(_T_1056, UInt<2>("h03")) @[el2_dma_ctrl.scala 369:32] + node _T_1058 = bits(dma_mem_byteen, 6, 3) @[el2_dma_ctrl.scala 369:59] + node _T_1059 = mux(_T_1048, _T_1049, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1060 = mux(_T_1051, _T_1052, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1061 = mux(_T_1054, _T_1055, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1062 = mux(_T_1057, _T_1058, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1063 = or(_T_1059, _T_1060) @[Mux.scala 27:72] + node _T_1064 = or(_T_1063, _T_1061) @[Mux.scala 27:72] + node _T_1065 = or(_T_1064, _T_1062) @[Mux.scala 27:72] + wire _T_1066 : UInt<4> @[Mux.scala 27:72] + _T_1066 <= _T_1065 @[Mux.scala 27:72] + node _T_1067 = neq(_T_1066, UInt<4>("h0f")) @[el2_dma_ctrl.scala 369:68] + node _T_1068 = and(_T_1046, _T_1067) @[el2_dma_ctrl.scala 366:58] + node _T_1069 = or(_T_1043, _T_1068) @[el2_dma_ctrl.scala 365:125] + node _T_1070 = bits(dma_mem_sz_int, 2, 0) @[el2_dma_ctrl.scala 370:42] + node _T_1071 = eq(_T_1070, UInt<2>("h03")) @[el2_dma_ctrl.scala 370:49] + node _T_1072 = and(io.dma_mem_write, _T_1071) @[el2_dma_ctrl.scala 370:25] + node _T_1073 = bits(dma_mem_byteen, 7, 0) @[el2_dma_ctrl.scala 370:77] + node _T_1074 = eq(_T_1073, UInt<4>("h0f")) @[el2_dma_ctrl.scala 370:83] + node _T_1075 = bits(dma_mem_byteen, 7, 0) @[el2_dma_ctrl.scala 370:113] + node _T_1076 = eq(_T_1075, UInt<8>("h0f0")) @[el2_dma_ctrl.scala 370:119] + node _T_1077 = or(_T_1074, _T_1076) @[el2_dma_ctrl.scala 370:96] + node _T_1078 = bits(dma_mem_byteen, 7, 0) @[el2_dma_ctrl.scala 370:149] + node _T_1079 = eq(_T_1078, UInt<8>("h0ff")) @[el2_dma_ctrl.scala 370:155] + node _T_1080 = or(_T_1077, _T_1079) @[el2_dma_ctrl.scala 370:132] + node _T_1081 = eq(_T_1080, UInt<1>("h00")) @[el2_dma_ctrl.scala 370:60] + node _T_1082 = and(_T_1072, _T_1081) @[el2_dma_ctrl.scala 370:58] + node _T_1083 = or(_T_1069, _T_1082) @[el2_dma_ctrl.scala 369:79] + node _T_1084 = and(_T_1010, _T_1083) @[el2_dma_ctrl.scala 360:87] + dma_alignment_error <= _T_1084 @[el2_dma_ctrl.scala 360:25] + node _T_1085 = and(fifo_empty, dbg_dma_bubble_bus) @[el2_dma_ctrl.scala 374:39] + io.dma_dbg_ready <= _T_1085 @[el2_dma_ctrl.scala 374:25] + node _T_1086 = dshr(fifo_valid, RspPtr) @[el2_dma_ctrl.scala 375:39] + node _T_1087 = bits(_T_1086, 0, 0) @[el2_dma_ctrl.scala 375:39] + node _T_1088 = dshr(fifo_dbg, RspPtr) @[el2_dma_ctrl.scala 375:58] + node _T_1089 = bits(_T_1088, 0, 0) @[el2_dma_ctrl.scala 375:58] + node _T_1090 = and(_T_1087, _T_1089) @[el2_dma_ctrl.scala 375:48] + node _T_1091 = dshr(fifo_done, RspPtr) @[el2_dma_ctrl.scala 375:78] + node _T_1092 = bits(_T_1091, 0, 0) @[el2_dma_ctrl.scala 375:78] + node _T_1093 = and(_T_1090, _T_1092) @[el2_dma_ctrl.scala 375:67] + io.dma_dbg_cmd_done <= _T_1093 @[el2_dma_ctrl.scala 375:25] + node _T_1094 = bits(fifo_addr[RspPtr], 2, 2) @[el2_dma_ctrl.scala 376:49] + node _T_1095 = bits(fifo_data[RspPtr], 63, 32) @[el2_dma_ctrl.scala 376:71] + node _T_1096 = bits(fifo_data[RspPtr], 31, 0) @[el2_dma_ctrl.scala 376:98] + node _T_1097 = mux(_T_1094, _T_1095, _T_1096) @[el2_dma_ctrl.scala 376:31] + io.dma_dbg_rddata <= _T_1097 @[el2_dma_ctrl.scala 376:25] + node _T_1098 = orr(fifo_error[RspPtr]) @[el2_dma_ctrl.scala 377:47] + io.dma_dbg_cmd_fail <= _T_1098 @[el2_dma_ctrl.scala 377:25] + node _T_1099 = dshr(fifo_valid, RdPtr) @[el2_dma_ctrl.scala 379:38] + node _T_1100 = bits(_T_1099, 0, 0) @[el2_dma_ctrl.scala 379:38] + node _T_1101 = dshr(fifo_done, RdPtr) @[el2_dma_ctrl.scala 379:58] + node _T_1102 = bits(_T_1101, 0, 0) @[el2_dma_ctrl.scala 379:58] + node _T_1103 = eq(_T_1102, UInt<1>("h00")) @[el2_dma_ctrl.scala 379:48] + node _T_1104 = and(_T_1100, _T_1103) @[el2_dma_ctrl.scala 379:46] + node _T_1105 = dshr(fifo_dbg, RdPtr) @[el2_dma_ctrl.scala 379:76] + node _T_1106 = bits(_T_1105, 0, 0) @[el2_dma_ctrl.scala 379:76] + node _T_1107 = and(_T_1104, _T_1106) @[el2_dma_ctrl.scala 379:66] + node _T_1108 = or(dma_mem_addr_in_dccm, dma_mem_addr_in_iccm) @[el2_dma_ctrl.scala 379:111] + node _T_1109 = or(_T_1108, dma_mem_addr_in_pic) @[el2_dma_ctrl.scala 379:134] + node _T_1110 = not(_T_1109) @[el2_dma_ctrl.scala 379:88] + node _T_1111 = bits(_T_1110, 0, 0) @[el2_dma_ctrl.scala 379:164] + node _T_1112 = bits(dma_mem_sz_int, 1, 0) @[el2_dma_ctrl.scala 379:184] + node _T_1113 = neq(_T_1112, UInt<2>("h02")) @[el2_dma_ctrl.scala 379:191] + node _T_1114 = or(_T_1111, _T_1113) @[el2_dma_ctrl.scala 379:167] + node _T_1115 = and(_T_1107, _T_1114) @[el2_dma_ctrl.scala 379:84] + dma_dbg_cmd_error <= _T_1115 @[el2_dma_ctrl.scala 379:25] + node _T_1116 = or(dma_mem_addr_in_dccm, dma_mem_addr_in_pic) @[el2_dma_ctrl.scala 383:64] + node _T_1117 = and(dma_mem_req, _T_1116) @[el2_dma_ctrl.scala 383:40] + node _T_1118 = geq(dma_nack_count, dma_nack_count_csr) @[el2_dma_ctrl.scala 383:105] + node _T_1119 = and(_T_1117, _T_1118) @[el2_dma_ctrl.scala 383:87] + io.dma_dccm_stall_any <= _T_1119 @[el2_dma_ctrl.scala 383:25] + node _T_1120 = and(dma_mem_req, dma_mem_addr_in_iccm) @[el2_dma_ctrl.scala 384:40] + node _T_1121 = geq(dma_nack_count, dma_nack_count_csr) @[el2_dma_ctrl.scala 384:81] + node _T_1122 = and(_T_1120, _T_1121) @[el2_dma_ctrl.scala 384:63] + io.dma_iccm_stall_any <= _T_1122 @[el2_dma_ctrl.scala 384:25] + node _T_1123 = orr(fifo_valid) @[el2_dma_ctrl.scala 388:30] + node _T_1124 = not(_T_1123) @[el2_dma_ctrl.scala 388:17] + fifo_empty <= _T_1124 @[el2_dma_ctrl.scala 388:14] + dma_nack_count_csr <= io.dec_tlu_dma_qos_prty @[el2_dma_ctrl.scala 392:22] + node _T_1125 = geq(dma_nack_count, dma_nack_count_csr) @[el2_dma_ctrl.scala 393:45] + node _T_1126 = or(io.dma_dccm_req, io.dma_iccm_req) @[el2_dma_ctrl.scala 393:95] + node _T_1127 = eq(_T_1126, UInt<1>("h00")) @[el2_dma_ctrl.scala 393:77] + node _T_1128 = bits(_T_1127, 0, 0) @[Bitwise.scala 72:15] + node _T_1129 = mux(_T_1128, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_1130 = bits(dma_nack_count, 2, 0) @[el2_dma_ctrl.scala 393:131] + node _T_1131 = and(_T_1129, _T_1130) @[el2_dma_ctrl.scala 393:115] + node _T_1132 = bits(dma_mem_req, 0, 0) @[el2_dma_ctrl.scala 393:156] + node _T_1133 = or(io.dma_dccm_req, io.dma_iccm_req) @[el2_dma_ctrl.scala 393:183] + node _T_1134 = eq(_T_1133, UInt<1>("h00")) @[el2_dma_ctrl.scala 393:165] + node _T_1135 = and(_T_1132, _T_1134) @[el2_dma_ctrl.scala 393:163] + node _T_1136 = bits(dma_nack_count, 2, 0) @[el2_dma_ctrl.scala 393:218] + node _T_1137 = add(_T_1136, UInt<1>("h01")) @[el2_dma_ctrl.scala 393:224] + node _T_1138 = tail(_T_1137, 1) @[el2_dma_ctrl.scala 393:224] + node _T_1139 = mux(_T_1135, _T_1138, UInt<1>("h00")) @[el2_dma_ctrl.scala 393:142] + node dma_nack_count_d = mux(_T_1125, _T_1131, _T_1139) @[el2_dma_ctrl.scala 393:29] + node _T_1140 = bits(dma_nack_count_d, 2, 0) @[el2_dma_ctrl.scala 396:31] + node _T_1141 = bits(dma_mem_req, 0, 0) @[el2_dma_ctrl.scala 396:55] + reg _T_1142 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1141 : @[Reg.scala 28:19] + _T_1142 <= _T_1140 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + dma_nack_count <= _T_1142 @[el2_dma_ctrl.scala 395:22] + node _T_1143 = dshr(fifo_valid, RdPtr) @[el2_dma_ctrl.scala 401:33] + node _T_1144 = bits(_T_1143, 0, 0) @[el2_dma_ctrl.scala 401:33] + node _T_1145 = dshr(fifo_rpend, RdPtr) @[el2_dma_ctrl.scala 401:54] + node _T_1146 = bits(_T_1145, 0, 0) @[el2_dma_ctrl.scala 401:54] + node _T_1147 = eq(_T_1146, UInt<1>("h00")) @[el2_dma_ctrl.scala 401:43] + node _T_1148 = and(_T_1144, _T_1147) @[el2_dma_ctrl.scala 401:41] + node _T_1149 = dshr(fifo_done, RdPtr) @[el2_dma_ctrl.scala 401:74] + node _T_1150 = bits(_T_1149, 0, 0) @[el2_dma_ctrl.scala 401:74] + node _T_1151 = eq(_T_1150, UInt<1>("h00")) @[el2_dma_ctrl.scala 401:64] + node _T_1152 = and(_T_1148, _T_1151) @[el2_dma_ctrl.scala 401:62] + node _T_1153 = or(dma_address_error, dma_alignment_error) @[el2_dma_ctrl.scala 401:104] + node _T_1154 = or(_T_1153, dma_dbg_cmd_error) @[el2_dma_ctrl.scala 401:126] + node _T_1155 = eq(_T_1154, UInt<1>("h00")) @[el2_dma_ctrl.scala 401:84] + node _T_1156 = and(_T_1152, _T_1155) @[el2_dma_ctrl.scala 401:82] + dma_mem_req <= _T_1156 @[el2_dma_ctrl.scala 401:20] + node _T_1157 = or(dma_mem_addr_in_dccm, dma_mem_addr_in_pic) @[el2_dma_ctrl.scala 402:59] + node _T_1158 = and(dma_mem_req, _T_1157) @[el2_dma_ctrl.scala 402:35] + node _T_1159 = and(_T_1158, io.dccm_ready) @[el2_dma_ctrl.scala 402:82] + io.dma_dccm_req <= _T_1159 @[el2_dma_ctrl.scala 402:20] + node _T_1160 = and(dma_mem_req, dma_mem_addr_in_iccm) @[el2_dma_ctrl.scala 403:35] + node _T_1161 = and(_T_1160, io.iccm_ready) @[el2_dma_ctrl.scala 403:58] + io.dma_iccm_req <= _T_1161 @[el2_dma_ctrl.scala 403:20] + io.dma_mem_tag <= RdPtr @[el2_dma_ctrl.scala 404:20] + dma_mem_addr_int <= fifo_addr[RdPtr] @[el2_dma_ctrl.scala 405:20] + dma_mem_sz_int <= fifo_sz[RdPtr] @[el2_dma_ctrl.scala 406:20] + node _T_1162 = bits(dma_mem_byteen, 7, 0) @[el2_dma_ctrl.scala 407:61] + node _T_1163 = eq(_T_1162, UInt<8>("h0f0")) @[el2_dma_ctrl.scala 407:67] + node _T_1164 = and(io.dma_mem_write, _T_1163) @[el2_dma_ctrl.scala 407:44] + node _T_1165 = bits(dma_mem_addr_int, 31, 3) @[el2_dma_ctrl.scala 407:101] + node _T_1166 = bits(dma_mem_addr_int, 1, 0) @[el2_dma_ctrl.scala 407:131] + node _T_1167 = cat(_T_1165, UInt<1>("h01")) @[Cat.scala 29:58] + node _T_1168 = cat(_T_1167, _T_1166) @[Cat.scala 29:58] + node _T_1169 = bits(dma_mem_addr_int, 31, 0) @[el2_dma_ctrl.scala 407:156] + node _T_1170 = mux(_T_1164, _T_1168, _T_1169) @[el2_dma_ctrl.scala 407:26] + io.dma_mem_addr <= _T_1170 @[el2_dma_ctrl.scala 407:20] + node _T_1171 = bits(dma_mem_byteen, 7, 0) @[el2_dma_ctrl.scala 408:62] + node _T_1172 = eq(_T_1171, UInt<4>("h0f")) @[el2_dma_ctrl.scala 408:68] + node _T_1173 = bits(dma_mem_byteen, 7, 0) @[el2_dma_ctrl.scala 408:98] + node _T_1174 = eq(_T_1173, UInt<8>("h0f0")) @[el2_dma_ctrl.scala 408:104] + node _T_1175 = or(_T_1172, _T_1174) @[el2_dma_ctrl.scala 408:81] + node _T_1176 = and(io.dma_mem_write, _T_1175) @[el2_dma_ctrl.scala 408:44] + node _T_1177 = bits(dma_mem_sz_int, 2, 0) @[el2_dma_ctrl.scala 408:138] + node _T_1178 = mux(_T_1176, UInt<2>("h02"), _T_1177) @[el2_dma_ctrl.scala 408:26] + io.dma_mem_sz <= _T_1178 @[el2_dma_ctrl.scala 408:20] + dma_mem_byteen <= fifo_byteen[RdPtr] @[el2_dma_ctrl.scala 409:20] + node _T_1179 = dshr(fifo_write, RdPtr) @[el2_dma_ctrl.scala 410:33] + node _T_1180 = bits(_T_1179, 0, 0) @[el2_dma_ctrl.scala 410:33] + io.dma_mem_write <= _T_1180 @[el2_dma_ctrl.scala 410:20] + io.dma_mem_wdata <= fifo_data[RdPtr] @[el2_dma_ctrl.scala 411:20] + node _T_1181 = eq(io.dma_mem_write, UInt<1>("h00")) @[el2_dma_ctrl.scala 415:47] + node _T_1182 = and(io.dma_dccm_req, _T_1181) @[el2_dma_ctrl.scala 415:45] + io.dma_pmu_dccm_read <= _T_1182 @[el2_dma_ctrl.scala 415:26] + node _T_1183 = and(io.dma_dccm_req, io.dma_mem_write) @[el2_dma_ctrl.scala 416:45] + io.dma_pmu_dccm_write <= _T_1183 @[el2_dma_ctrl.scala 416:26] + node _T_1184 = or(io.dma_dccm_req, io.dma_iccm_req) @[el2_dma_ctrl.scala 417:46] + node _T_1185 = eq(io.dma_mem_write, UInt<1>("h00")) @[el2_dma_ctrl.scala 417:67] + node _T_1186 = and(_T_1184, _T_1185) @[el2_dma_ctrl.scala 417:65] + io.dma_pmu_any_read <= _T_1186 @[el2_dma_ctrl.scala 417:26] + node _T_1187 = or(io.dma_dccm_req, io.dma_iccm_req) @[el2_dma_ctrl.scala 418:46] + node _T_1188 = and(_T_1187, io.dma_mem_write) @[el2_dma_ctrl.scala 418:65] + io.dma_pmu_any_write <= _T_1188 @[el2_dma_ctrl.scala 418:26] + reg _T_1189 : UInt<1>, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 423:12] + _T_1189 <= fifo_full_spec @[el2_dma_ctrl.scala 423:12] + fifo_full <= _T_1189 @[el2_dma_ctrl.scala 422:22] + reg _T_1190 : UInt<1>, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 427:12] + _T_1190 <= io.dbg_dma_bubble @[el2_dma_ctrl.scala 427:12] + dbg_dma_bubble_bus <= _T_1190 @[el2_dma_ctrl.scala 426:22] + reg _T_1191 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 431:12] + _T_1191 <= io.dma_dbg_cmd_done @[el2_dma_ctrl.scala 431:12] + dma_dbg_cmd_done_q <= _T_1191 @[el2_dma_ctrl.scala 430:22] + node _T_1192 = and(bus_cmd_valid, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 436:44] + node _T_1193 = or(_T_1192, io.dbg_cmd_valid) @[el2_dma_ctrl.scala 436:65] + node dma_buffer_c1_clken = or(_T_1193, io.clk_override) @[el2_dma_ctrl.scala 436:84] + node _T_1194 = or(bus_cmd_valid, bus_rsp_valid) @[el2_dma_ctrl.scala 437:44] + node _T_1195 = or(_T_1194, io.dbg_cmd_valid) @[el2_dma_ctrl.scala 437:60] + node _T_1196 = or(_T_1195, io.dma_dbg_cmd_done) @[el2_dma_ctrl.scala 437:79] + node _T_1197 = or(_T_1196, dma_dbg_cmd_done_q) @[el2_dma_ctrl.scala 437:101] + node _T_1198 = orr(fifo_valid) @[el2_dma_ctrl.scala 437:136] + node _T_1199 = or(_T_1197, _T_1198) @[el2_dma_ctrl.scala 437:122] + node dma_free_clken = or(_T_1199, io.clk_override) @[el2_dma_ctrl.scala 437:141] + inst dma_buffer_c1cgc of rvclkhdr_10 @[el2_dma_ctrl.scala 439:32] + dma_buffer_c1cgc.clock <= clock + dma_buffer_c1cgc.reset <= reset + dma_buffer_c1cgc.io.en <= dma_buffer_c1_clken @[el2_dma_ctrl.scala 440:33] + dma_buffer_c1cgc.io.scan_mode <= io.scan_mode @[el2_dma_ctrl.scala 441:33] + dma_buffer_c1cgc.io.clk <= clock @[el2_dma_ctrl.scala 442:33] + dma_buffer_c1_clk <= dma_buffer_c1cgc.io.l1clk @[el2_dma_ctrl.scala 443:33] + inst dma_free_cgc of rvclkhdr_11 @[el2_dma_ctrl.scala 445:28] + dma_free_cgc.clock <= clock + dma_free_cgc.reset <= reset + dma_free_cgc.io.en <= dma_free_clken @[el2_dma_ctrl.scala 446:29] + dma_free_cgc.io.scan_mode <= io.scan_mode @[el2_dma_ctrl.scala 447:29] + dma_free_cgc.io.clk <= clock @[el2_dma_ctrl.scala 448:29] + dma_free_clk <= dma_free_cgc.io.l1clk @[el2_dma_ctrl.scala 449:29] + inst dma_bus_cgc of rvclkhdr_12 @[el2_dma_ctrl.scala 451:27] + dma_bus_cgc.clock <= clock + dma_bus_cgc.reset <= reset + dma_bus_cgc.io.en <= io.dma_bus_clk_en @[el2_dma_ctrl.scala 452:28] + dma_bus_cgc.io.scan_mode <= io.scan_mode @[el2_dma_ctrl.scala 453:28] + dma_bus_cgc.io.clk <= clock @[el2_dma_ctrl.scala 454:28] + dma_bus_clk <= dma_bus_cgc.io.l1clk @[el2_dma_ctrl.scala 455:28] + node wrbuf_en = and(io.dma_axi_awvalid, io.dma_axi_awready) @[el2_dma_ctrl.scala 459:46] + node wrbuf_data_en = and(io.dma_axi_wvalid, io.dma_axi_wready) @[el2_dma_ctrl.scala 460:45] + node wrbuf_cmd_sent = and(axi_mstr_prty_en, bus_cmd_write) @[el2_dma_ctrl.scala 461:40] + node _T_1200 = bits(wrbuf_cmd_sent, 0, 0) @[el2_dma_ctrl.scala 462:42] + node _T_1201 = eq(wrbuf_en, UInt<1>("h00")) @[el2_dma_ctrl.scala 462:51] + node wrbuf_rst = and(_T_1200, _T_1201) @[el2_dma_ctrl.scala 462:49] + node _T_1202 = bits(wrbuf_cmd_sent, 0, 0) @[el2_dma_ctrl.scala 463:42] + node _T_1203 = eq(wrbuf_data_en, UInt<1>("h00")) @[el2_dma_ctrl.scala 463:51] + node wrbuf_data_rst = and(_T_1202, _T_1203) @[el2_dma_ctrl.scala 463:49] + node _T_1204 = mux(wrbuf_en, UInt<1>("h01"), wrbuf_vld) @[el2_dma_ctrl.scala 465:63] + node _T_1205 = eq(wrbuf_rst, UInt<1>("h00")) @[el2_dma_ctrl.scala 465:92] + node _T_1206 = and(_T_1204, _T_1205) @[el2_dma_ctrl.scala 465:90] + reg _T_1207 : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 465:59] + _T_1207 <= _T_1206 @[el2_dma_ctrl.scala 465:59] + wrbuf_vld <= _T_1207 @[el2_dma_ctrl.scala 465:25] + node _T_1208 = mux(wrbuf_data_en, UInt<1>("h01"), wrbuf_data_vld) @[el2_dma_ctrl.scala 467:63] + node _T_1209 = eq(wrbuf_data_rst, UInt<1>("h00")) @[el2_dma_ctrl.scala 467:102] + node _T_1210 = and(_T_1208, _T_1209) @[el2_dma_ctrl.scala 467:100] + reg _T_1211 : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 467:59] + _T_1211 <= _T_1210 @[el2_dma_ctrl.scala 467:59] + wrbuf_data_vld <= _T_1211 @[el2_dma_ctrl.scala 467:25] + reg wrbuf_tag : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when wrbuf_en : @[Reg.scala 28:19] + wrbuf_tag <= io.dma_axi_awid @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg wrbuf_sz : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when wrbuf_en : @[Reg.scala 28:19] + wrbuf_sz <= io.dma_axi_awsize @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_1212 = and(wrbuf_en, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 477:62] + inst rvclkhdr_10 of rvclkhdr_13 @[el2_lib.scala 508:23] + rvclkhdr_10.clock <= clock + rvclkhdr_10.reset <= reset + rvclkhdr_10.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_10.io.en <= _T_1212 @[el2_lib.scala 511:17] + rvclkhdr_10.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg wrbuf_addr : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + wrbuf_addr <= io.dma_axi_awaddr @[el2_lib.scala 514:16] + node _T_1213 = and(wrbuf_data_en, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 479:66] + inst rvclkhdr_11 of rvclkhdr_14 @[el2_lib.scala 508:23] + rvclkhdr_11.clock <= clock + rvclkhdr_11.reset <= reset + rvclkhdr_11.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_11.io.en <= _T_1213 @[el2_lib.scala 511:17] + rvclkhdr_11.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg wrbuf_data : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + wrbuf_data <= io.dma_axi_wdata @[el2_lib.scala 514:16] + reg wrbuf_byteen : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when wrbuf_data_en : @[Reg.scala 28:19] + wrbuf_byteen <= io.dma_axi_wstrb @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node rdbuf_en = and(io.dma_axi_arvalid, io.dma_axi_arready) @[el2_dma_ctrl.scala 487:58] + node _T_1214 = eq(bus_cmd_write, UInt<1>("h00")) @[el2_dma_ctrl.scala 488:44] + node rdbuf_cmd_sent = and(axi_mstr_prty_en, _T_1214) @[el2_dma_ctrl.scala 488:42] + node _T_1215 = bits(rdbuf_cmd_sent, 0, 0) @[el2_dma_ctrl.scala 489:54] + node _T_1216 = eq(rdbuf_en, UInt<1>("h00")) @[el2_dma_ctrl.scala 489:63] + node rdbuf_rst = and(_T_1215, _T_1216) @[el2_dma_ctrl.scala 489:61] + node _T_1217 = mux(rdbuf_en, UInt<1>("h01"), rdbuf_vld) @[el2_dma_ctrl.scala 491:51] + node _T_1218 = eq(rdbuf_rst, UInt<1>("h00")) @[el2_dma_ctrl.scala 491:80] + node _T_1219 = and(_T_1217, _T_1218) @[el2_dma_ctrl.scala 491:78] + reg _T_1220 : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 491:47] + _T_1220 <= _T_1219 @[el2_dma_ctrl.scala 491:47] + rdbuf_vld <= _T_1220 @[el2_dma_ctrl.scala 491:13] + reg rdbuf_tag : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when rdbuf_en : @[Reg.scala 28:19] + rdbuf_tag <= io.dma_axi_arid @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg rdbuf_sz : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when rdbuf_en : @[Reg.scala 28:19] + rdbuf_sz <= io.dma_axi_arsize @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_1221 = and(rdbuf_en, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 501:55] + inst rvclkhdr_12 of rvclkhdr_15 @[el2_lib.scala 508:23] + rvclkhdr_12.clock <= clock + rvclkhdr_12.reset <= reset + rvclkhdr_12.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_12.io.en <= _T_1221 @[el2_lib.scala 511:17] + rvclkhdr_12.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg rdbuf_addr : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + rdbuf_addr <= io.dma_axi_araddr @[el2_lib.scala 514:16] + node _T_1222 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[el2_dma_ctrl.scala 503:44] + node _T_1223 = and(wrbuf_vld, _T_1222) @[el2_dma_ctrl.scala 503:42] + node _T_1224 = not(_T_1223) @[el2_dma_ctrl.scala 503:30] + io.dma_axi_awready <= _T_1224 @[el2_dma_ctrl.scala 503:27] + node _T_1225 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[el2_dma_ctrl.scala 504:49] + node _T_1226 = and(wrbuf_data_vld, _T_1225) @[el2_dma_ctrl.scala 504:47] + node _T_1227 = not(_T_1226) @[el2_dma_ctrl.scala 504:30] + io.dma_axi_wready <= _T_1227 @[el2_dma_ctrl.scala 504:27] + node _T_1228 = eq(rdbuf_cmd_sent, UInt<1>("h00")) @[el2_dma_ctrl.scala 505:44] + node _T_1229 = and(rdbuf_vld, _T_1228) @[el2_dma_ctrl.scala 505:42] + node _T_1230 = not(_T_1229) @[el2_dma_ctrl.scala 505:30] + io.dma_axi_arready <= _T_1230 @[el2_dma_ctrl.scala 505:27] + node _T_1231 = and(wrbuf_vld, wrbuf_data_vld) @[el2_dma_ctrl.scala 509:51] + node _T_1232 = or(_T_1231, rdbuf_vld) @[el2_dma_ctrl.scala 509:69] + bus_cmd_valid <= _T_1232 @[el2_dma_ctrl.scala 509:37] + node _T_1233 = and(bus_cmd_valid, dma_fifo_ready) @[el2_dma_ctrl.scala 510:54] + axi_mstr_prty_en <= _T_1233 @[el2_dma_ctrl.scala 510:37] + bus_cmd_write <= axi_mstr_sel @[el2_dma_ctrl.scala 511:37] + bus_cmd_posted_write <= UInt<1>("h00") @[el2_dma_ctrl.scala 512:25] + node _T_1234 = bits(axi_mstr_sel, 0, 0) @[el2_dma_ctrl.scala 513:57] + node _T_1235 = mux(_T_1234, wrbuf_addr, rdbuf_addr) @[el2_dma_ctrl.scala 513:43] + bus_cmd_addr <= _T_1235 @[el2_dma_ctrl.scala 513:37] + node _T_1236 = bits(axi_mstr_sel, 0, 0) @[el2_dma_ctrl.scala 514:59] + node _T_1237 = mux(_T_1236, wrbuf_sz, rdbuf_sz) @[el2_dma_ctrl.scala 514:45] + bus_cmd_sz <= _T_1237 @[el2_dma_ctrl.scala 514:39] + bus_cmd_wdata <= wrbuf_data @[el2_dma_ctrl.scala 515:37] + bus_cmd_byteen <= wrbuf_byteen @[el2_dma_ctrl.scala 516:37] + node _T_1238 = bits(axi_mstr_sel, 0, 0) @[el2_dma_ctrl.scala 517:57] + node _T_1239 = mux(_T_1238, wrbuf_tag, rdbuf_tag) @[el2_dma_ctrl.scala 517:43] + bus_cmd_tag <= _T_1239 @[el2_dma_ctrl.scala 517:37] + bus_cmd_mid <= UInt<1>("h00") @[el2_dma_ctrl.scala 518:37] + bus_cmd_prty <= UInt<1>("h00") @[el2_dma_ctrl.scala 519:37] + node _T_1240 = and(wrbuf_vld, wrbuf_data_vld) @[el2_dma_ctrl.scala 523:43] + node _T_1241 = and(_T_1240, rdbuf_vld) @[el2_dma_ctrl.scala 523:60] + node _T_1242 = eq(_T_1241, UInt<1>("h01")) @[el2_dma_ctrl.scala 523:73] + node _T_1243 = and(wrbuf_vld, wrbuf_data_vld) @[el2_dma_ctrl.scala 523:111] + node _T_1244 = mux(_T_1242, axi_mstr_priority, _T_1243) @[el2_dma_ctrl.scala 523:31] + axi_mstr_sel <= _T_1244 @[el2_dma_ctrl.scala 523:25] + node axi_mstr_prty_in = not(axi_mstr_priority) @[el2_dma_ctrl.scala 524:27] + node _T_1245 = bits(axi_mstr_prty_en, 0, 0) @[el2_dma_ctrl.scala 528:55] + reg _T_1246 : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1245 : @[Reg.scala 28:19] + _T_1246 <= axi_mstr_prty_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + axi_mstr_priority <= _T_1246 @[el2_dma_ctrl.scala 527:27] + node _T_1247 = dshr(fifo_valid, RspPtr) @[el2_dma_ctrl.scala 531:39] + node _T_1248 = bits(_T_1247, 0, 0) @[el2_dma_ctrl.scala 531:39] + node _T_1249 = dshr(fifo_dbg, RspPtr) @[el2_dma_ctrl.scala 531:59] + node _T_1250 = bits(_T_1249, 0, 0) @[el2_dma_ctrl.scala 531:59] + node _T_1251 = eq(_T_1250, UInt<1>("h00")) @[el2_dma_ctrl.scala 531:50] + node _T_1252 = and(_T_1248, _T_1251) @[el2_dma_ctrl.scala 531:48] + node _T_1253 = dshr(fifo_done_bus, RspPtr) @[el2_dma_ctrl.scala 531:83] + node _T_1254 = bits(_T_1253, 0, 0) @[el2_dma_ctrl.scala 531:83] + node axi_rsp_valid = and(_T_1252, _T_1254) @[el2_dma_ctrl.scala 531:68] + node _T_1255 = dshr(fifo_write, RspPtr) @[el2_dma_ctrl.scala 533:39] + node axi_rsp_write = bits(_T_1255, 0, 0) @[el2_dma_ctrl.scala 533:39] + node _T_1256 = bits(fifo_error[RspPtr], 0, 0) @[el2_dma_ctrl.scala 534:51] + node _T_1257 = bits(fifo_error[RspPtr], 1, 1) @[el2_dma_ctrl.scala 534:83] + node _T_1258 = mux(_T_1257, UInt<2>("h03"), UInt<1>("h00")) @[el2_dma_ctrl.scala 534:64] + node axi_rsp_error = mux(_T_1256, UInt<2>("h02"), _T_1258) @[el2_dma_ctrl.scala 534:32] + node _T_1259 = and(axi_rsp_valid, axi_rsp_write) @[el2_dma_ctrl.scala 540:44] + io.dma_axi_bvalid <= _T_1259 @[el2_dma_ctrl.scala 540:27] + node _T_1260 = bits(axi_rsp_error, 1, 0) @[el2_dma_ctrl.scala 541:49] + io.dma_axi_bresp <= _T_1260 @[el2_dma_ctrl.scala 541:33] + io.dma_axi_bid <= fifo_tag[RspPtr] @[el2_dma_ctrl.scala 542:33] + node _T_1261 = eq(axi_rsp_write, UInt<1>("h00")) @[el2_dma_ctrl.scala 544:46] + node _T_1262 = and(axi_rsp_valid, _T_1261) @[el2_dma_ctrl.scala 544:44] + io.dma_axi_rvalid <= _T_1262 @[el2_dma_ctrl.scala 544:27] + io.dma_axi_rresp <= axi_rsp_error @[el2_dma_ctrl.scala 545:33] + node _T_1263 = bits(fifo_data[RspPtr], 63, 0) @[el2_dma_ctrl.scala 546:51] + io.dma_axi_rdata <= _T_1263 @[el2_dma_ctrl.scala 546:35] + io.dma_axi_rlast <= UInt<1>("h01") @[el2_dma_ctrl.scala 547:33] + io.dma_axi_rid <= fifo_tag[RspPtr] @[el2_dma_ctrl.scala 548:37] + bus_posted_write_done <= UInt<1>("h00") @[el2_dma_ctrl.scala 550:25] + node _T_1264 = or(io.dma_axi_bvalid, io.dma_axi_rvalid) @[el2_dma_ctrl.scala 551:59] + bus_rsp_valid <= _T_1264 @[el2_dma_ctrl.scala 551:37] + node _T_1265 = and(io.dma_axi_bvalid, io.dma_axi_bready) @[el2_dma_ctrl.scala 552:60] + node _T_1266 = and(io.dma_axi_rvalid, io.dma_axi_rready) @[el2_dma_ctrl.scala 552:102] + node _T_1267 = or(_T_1265, _T_1266) @[el2_dma_ctrl.scala 552:81] + bus_rsp_sent <= _T_1267 @[el2_dma_ctrl.scala 552:37] + diff --git a/el2_dma_ctrl.v b/el2_dma_ctrl.v new file mode 100644 index 00000000..fa7d288a --- /dev/null +++ b/el2_dma_ctrl.v @@ -0,0 +1,2045 @@ +module rvclkhdr( + output io_l1clk, + input io_clk, + input io_en, + input io_scan_mode +); + wire clkhdr_Q; // @[el2_lib.scala 474:26] + wire clkhdr_CK; // @[el2_lib.scala 474:26] + wire clkhdr_EN; // @[el2_lib.scala 474:26] + wire clkhdr_SE; // @[el2_lib.scala 474:26] + gated_latch clkhdr ( // @[el2_lib.scala 474:26] + .Q(clkhdr_Q), + .CK(clkhdr_CK), + .EN(clkhdr_EN), + .SE(clkhdr_SE) + ); + assign io_l1clk = clkhdr_Q; // @[el2_lib.scala 475:14] + assign clkhdr_CK = io_clk; // @[el2_lib.scala 476:18] + assign clkhdr_EN = io_en; // @[el2_lib.scala 477:18] + assign clkhdr_SE = io_scan_mode; // @[el2_lib.scala 478:18] +endmodule +module el2_dma_ctrl( + input clock, + input reset, + input io_free_clk, + input io_dma_bus_clk_en, + input io_clk_override, + input io_scan_mode, + input [31:0] io_dbg_cmd_addr, + input [31:0] io_dbg_cmd_wrdata, + input io_dbg_cmd_valid, + input io_dbg_cmd_write, + input [1:0] io_dbg_cmd_type, + input [1:0] io_dbg_cmd_size, + input io_dbg_dma_bubble, + output io_dma_dbg_ready, + output io_dma_dbg_cmd_done, + output io_dma_dbg_cmd_fail, + output [31:0] io_dma_dbg_rddata, + output io_dma_dccm_req, + output io_dma_iccm_req, + output [2:0] io_dma_mem_tag, + output [31:0] io_dma_mem_addr, + output [2:0] io_dma_mem_sz, + output io_dma_mem_write, + output [63:0] io_dma_mem_wdata, + input io_dccm_dma_rvalid, + input io_dccm_dma_ecc_error, + input [2:0] io_dccm_dma_rtag, + input [63:0] io_dccm_dma_rdata, + input io_iccm_dma_rvalid, + input io_iccm_dma_ecc_error, + input [2:0] io_iccm_dma_rtag, + input [63:0] io_iccm_dma_rdata, + output io_dma_dccm_stall_any, + output io_dma_iccm_stall_any, + input io_dccm_ready, + input io_iccm_ready, + input [2:0] io_dec_tlu_dma_qos_prty, + output io_dma_pmu_dccm_read, + output io_dma_pmu_dccm_write, + output io_dma_pmu_any_read, + output io_dma_pmu_any_write, + input io_dma_axi_awvalid, + output io_dma_axi_awready, + input io_dma_axi_awid, + input [31:0] io_dma_axi_awaddr, + input [2:0] io_dma_axi_awsize, + input io_dma_axi_wvalid, + output io_dma_axi_wready, + input [63:0] io_dma_axi_wdata, + input [7:0] io_dma_axi_wstrb, + output io_dma_axi_bvalid, + input io_dma_axi_bready, + output [1:0] io_dma_axi_bresp, + output io_dma_axi_bid, + input io_dma_axi_arvalid, + output io_dma_axi_arready, + input io_dma_axi_arid, + input [31:0] io_dma_axi_araddr, + input [2:0] io_dma_axi_arsize, + output io_dma_axi_rvalid, + input io_dma_axi_rready, + output io_dma_axi_rid, + output [63:0] io_dma_axi_rdata, + output [1:0] io_dma_axi_rresp, + output io_dma_axi_rlast +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; + reg [31:0] _RAND_13; + reg [31:0] _RAND_14; + reg [31:0] _RAND_15; + reg [31:0] _RAND_16; + reg [31:0] _RAND_17; + reg [31:0] _RAND_18; + reg [31:0] _RAND_19; + reg [31:0] _RAND_20; + reg [31:0] _RAND_21; + reg [31:0] _RAND_22; + reg [31:0] _RAND_23; + reg [31:0] _RAND_24; + reg [31:0] _RAND_25; + reg [31:0] _RAND_26; + reg [31:0] _RAND_27; + reg [31:0] _RAND_28; + reg [31:0] _RAND_29; + reg [31:0] _RAND_30; + reg [31:0] _RAND_31; + reg [31:0] _RAND_32; + reg [31:0] _RAND_33; + reg [31:0] _RAND_34; + reg [31:0] _RAND_35; + reg [31:0] _RAND_36; + reg [31:0] _RAND_37; + reg [31:0] _RAND_38; + reg [31:0] _RAND_39; + reg [31:0] _RAND_40; + reg [31:0] _RAND_41; + reg [31:0] _RAND_42; + reg [31:0] _RAND_43; + reg [31:0] _RAND_44; + reg [31:0] _RAND_45; + reg [31:0] _RAND_46; + reg [31:0] _RAND_47; + reg [31:0] _RAND_48; + reg [63:0] _RAND_49; + reg [31:0] _RAND_50; + reg [31:0] _RAND_51; + reg [31:0] _RAND_52; + reg [31:0] _RAND_53; + reg [31:0] _RAND_54; + reg [31:0] _RAND_55; + reg [31:0] _RAND_56; + reg [31:0] _RAND_57; + reg [31:0] _RAND_58; + reg [31:0] _RAND_59; + reg [31:0] _RAND_60; + reg [31:0] _RAND_61; + reg [31:0] _RAND_62; + reg [31:0] _RAND_63; + reg [31:0] _RAND_64; + reg [63:0] _RAND_65; + reg [63:0] _RAND_66; + reg [63:0] _RAND_67; + reg [63:0] _RAND_68; + reg [63:0] _RAND_69; + reg [31:0] _RAND_70; + reg [31:0] _RAND_71; + reg [31:0] _RAND_72; + reg [31:0] _RAND_73; + reg [31:0] _RAND_74; + reg [31:0] _RAND_75; + reg [31:0] _RAND_76; + reg [31:0] _RAND_77; + reg [31:0] _RAND_78; +`endif // RANDOMIZE_REG_INIT + wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_2_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_2_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_4_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_4_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_5_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_5_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_6_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_6_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_6_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_6_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_7_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_7_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_7_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_7_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_8_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_8_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_8_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_8_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_9_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_9_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_9_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 508:23] + wire dma_buffer_c1cgc_io_l1clk; // @[el2_dma_ctrl.scala 439:32] + wire dma_buffer_c1cgc_io_clk; // @[el2_dma_ctrl.scala 439:32] + wire dma_buffer_c1cgc_io_en; // @[el2_dma_ctrl.scala 439:32] + wire dma_buffer_c1cgc_io_scan_mode; // @[el2_dma_ctrl.scala 439:32] + wire dma_free_cgc_io_l1clk; // @[el2_dma_ctrl.scala 445:28] + wire dma_free_cgc_io_clk; // @[el2_dma_ctrl.scala 445:28] + wire dma_free_cgc_io_en; // @[el2_dma_ctrl.scala 445:28] + wire dma_free_cgc_io_scan_mode; // @[el2_dma_ctrl.scala 445:28] + wire dma_bus_cgc_io_l1clk; // @[el2_dma_ctrl.scala 451:27] + wire dma_bus_cgc_io_clk; // @[el2_dma_ctrl.scala 451:27] + wire dma_bus_cgc_io_en; // @[el2_dma_ctrl.scala 451:27] + wire dma_bus_cgc_io_scan_mode; // @[el2_dma_ctrl.scala 451:27] + wire rvclkhdr_10_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_10_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_10_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_10_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_11_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_11_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_11_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_11_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_12_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_12_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_12_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_12_io_scan_mode; // @[el2_lib.scala 508:23] + wire dma_free_clk = dma_free_cgc_io_l1clk; // @[el2_dma_ctrl.scala 224:26 el2_dma_ctrl.scala 449:29] + reg [2:0] RdPtr; // @[Reg.scala 27:20] + reg [31:0] fifo_addr_4; // @[el2_lib.scala 514:16] + reg [31:0] fifo_addr_3; // @[el2_lib.scala 514:16] + reg [31:0] fifo_addr_2; // @[el2_lib.scala 514:16] + reg [31:0] fifo_addr_1; // @[el2_lib.scala 514:16] + reg [31:0] fifo_addr_0; // @[el2_lib.scala 514:16] + wire [31:0] _GEN_60 = 3'h1 == RdPtr ? fifo_addr_1 : fifo_addr_0; // @[el2_dma_ctrl.scala 405:20] + wire [31:0] _GEN_61 = 3'h2 == RdPtr ? fifo_addr_2 : _GEN_60; // @[el2_dma_ctrl.scala 405:20] + wire [31:0] _GEN_62 = 3'h3 == RdPtr ? fifo_addr_3 : _GEN_61; // @[el2_dma_ctrl.scala 405:20] + wire [31:0] dma_mem_addr_int = 3'h4 == RdPtr ? fifo_addr_4 : _GEN_62; // @[el2_dma_ctrl.scala 405:20] + wire dma_mem_addr_in_dccm = dma_mem_addr_int[31:16] == 16'hf004; // @[el2_lib.scala 501:39] + wire dma_mem_addr_in_pic = dma_mem_addr_int[31:15] == 17'h1e018; // @[el2_lib.scala 501:39] + wire dma_mem_addr_in_iccm = dma_mem_addr_int[31:16] == 16'hee00; // @[el2_lib.scala 501:39] + wire dma_bus_clk = dma_bus_cgc_io_l1clk; // @[el2_dma_ctrl.scala 226:25 el2_dma_ctrl.scala 455:28] + reg wrbuf_vld; // @[el2_dma_ctrl.scala 465:59] + reg wrbuf_data_vld; // @[el2_dma_ctrl.scala 467:59] + wire _T_1240 = wrbuf_vld & wrbuf_data_vld; // @[el2_dma_ctrl.scala 523:43] + reg rdbuf_vld; // @[el2_dma_ctrl.scala 491:47] + wire _T_1241 = _T_1240 & rdbuf_vld; // @[el2_dma_ctrl.scala 523:60] + reg axi_mstr_priority; // @[Reg.scala 27:20] + wire axi_mstr_sel = _T_1241 ? axi_mstr_priority : _T_1240; // @[el2_dma_ctrl.scala 523:31] + reg [31:0] wrbuf_addr; // @[el2_lib.scala 514:16] + reg [31:0] rdbuf_addr; // @[el2_lib.scala 514:16] + wire [31:0] bus_cmd_addr = axi_mstr_sel ? wrbuf_addr : rdbuf_addr; // @[el2_dma_ctrl.scala 513:43] + wire [2:0] _GEN_90 = {{2'd0}, io_dbg_cmd_addr[2]}; // @[el2_dma_ctrl.scala 251:76] + wire [3:0] _T_17 = 3'h4 * _GEN_90; // @[el2_dma_ctrl.scala 251:76] + wire [18:0] _T_18 = 19'hf << _T_17; // @[el2_dma_ctrl.scala 251:68] + reg [7:0] wrbuf_byteen; // @[Reg.scala 27:20] + wire [18:0] _T_20 = io_dbg_cmd_valid ? _T_18 : {{11'd0}, wrbuf_byteen}; // @[el2_dma_ctrl.scala 251:34] + wire [2:0] _T_23 = {1'h0,io_dbg_cmd_size}; // @[Cat.scala 29:58] + reg [2:0] wrbuf_sz; // @[Reg.scala 27:20] + reg [2:0] rdbuf_sz; // @[Reg.scala 27:20] + wire [2:0] bus_cmd_sz = axi_mstr_sel ? wrbuf_sz : rdbuf_sz; // @[el2_dma_ctrl.scala 514:45] + wire [2:0] fifo_sz_in = io_dbg_cmd_valid ? _T_23 : bus_cmd_sz; // @[el2_dma_ctrl.scala 253:33] + wire fifo_write_in = io_dbg_cmd_valid ? io_dbg_cmd_write : axi_mstr_sel; // @[el2_dma_ctrl.scala 255:33] + wire bus_cmd_valid = _T_1240 | rdbuf_vld; // @[el2_dma_ctrl.scala 509:69] + reg fifo_full; // @[el2_dma_ctrl.scala 423:12] + reg dbg_dma_bubble_bus; // @[el2_dma_ctrl.scala 427:12] + wire _T_989 = fifo_full | dbg_dma_bubble_bus; // @[el2_dma_ctrl.scala 355:39] + wire dma_fifo_ready = ~_T_989; // @[el2_dma_ctrl.scala 355:27] + wire axi_mstr_prty_en = bus_cmd_valid & dma_fifo_ready; // @[el2_dma_ctrl.scala 510:54] + wire _T_28 = axi_mstr_prty_en & io_dma_bus_clk_en; // @[el2_dma_ctrl.scala 262:80] + wire _T_31 = io_dbg_cmd_valid & io_dbg_cmd_type[1]; // @[el2_dma_ctrl.scala 262:121] + wire _T_32 = _T_28 | _T_31; // @[el2_dma_ctrl.scala 262:101] + reg [2:0] WrPtr; // @[Reg.scala 27:20] + wire _T_33 = 3'h0 == WrPtr; // @[el2_dma_ctrl.scala 262:158] + wire _T_34 = _T_32 & _T_33; // @[el2_dma_ctrl.scala 262:151] + wire _T_41 = 3'h1 == WrPtr; // @[el2_dma_ctrl.scala 262:158] + wire _T_42 = _T_32 & _T_41; // @[el2_dma_ctrl.scala 262:151] + wire _T_49 = 3'h2 == WrPtr; // @[el2_dma_ctrl.scala 262:158] + wire _T_50 = _T_32 & _T_49; // @[el2_dma_ctrl.scala 262:151] + wire _T_57 = 3'h3 == WrPtr; // @[el2_dma_ctrl.scala 262:158] + wire _T_58 = _T_32 & _T_57; // @[el2_dma_ctrl.scala 262:151] + wire _T_65 = 3'h4 == WrPtr; // @[el2_dma_ctrl.scala 262:158] + wire _T_66 = _T_32 & _T_65; // @[el2_dma_ctrl.scala 262:151] + wire [4:0] fifo_cmd_en = {_T_66,_T_58,_T_50,_T_42,_T_34}; // @[Cat.scala 29:58] + wire _T_71 = axi_mstr_prty_en & fifo_write_in; // @[el2_dma_ctrl.scala 264:73] + wire _T_72 = _T_71 & io_dma_bus_clk_en; // @[el2_dma_ctrl.scala 264:89] + wire _T_75 = _T_31 & io_dbg_cmd_write; // @[el2_dma_ctrl.scala 264:151] + wire _T_76 = _T_72 | _T_75; // @[el2_dma_ctrl.scala 264:110] + wire _T_78 = _T_76 & _T_33; // @[el2_dma_ctrl.scala 264:172] + reg _T_598; // @[el2_dma_ctrl.scala 282:82] + reg _T_591; // @[el2_dma_ctrl.scala 282:82] + reg _T_584; // @[el2_dma_ctrl.scala 282:82] + reg _T_577; // @[el2_dma_ctrl.scala 282:82] + reg _T_570; // @[el2_dma_ctrl.scala 282:82] + wire [4:0] fifo_valid = {_T_598,_T_591,_T_584,_T_577,_T_570}; // @[Cat.scala 29:58] + wire [4:0] _T_990 = fifo_valid >> RdPtr; // @[el2_dma_ctrl.scala 359:38] + reg _T_760; // @[el2_dma_ctrl.scala 290:89] + reg _T_753; // @[el2_dma_ctrl.scala 290:89] + reg _T_746; // @[el2_dma_ctrl.scala 290:89] + reg _T_739; // @[el2_dma_ctrl.scala 290:89] + reg _T_732; // @[el2_dma_ctrl.scala 290:89] + wire [4:0] fifo_done = {_T_760,_T_753,_T_746,_T_739,_T_732}; // @[Cat.scala 29:58] + wire [4:0] _T_992 = fifo_done >> RdPtr; // @[el2_dma_ctrl.scala 359:58] + wire _T_994 = ~_T_992[0]; // @[el2_dma_ctrl.scala 359:48] + wire _T_995 = _T_990[0] & _T_994; // @[el2_dma_ctrl.scala 359:46] + wire dma_buffer_c1_clk = dma_buffer_c1cgc_io_l1clk; // @[el2_dma_ctrl.scala 228:31 el2_dma_ctrl.scala 443:33] + reg _T_886; // @[Reg.scala 27:20] + reg _T_884; // @[Reg.scala 27:20] + reg _T_882; // @[Reg.scala 27:20] + reg _T_880; // @[Reg.scala 27:20] + reg _T_878; // @[Reg.scala 27:20] + wire [4:0] fifo_dbg = {_T_886,_T_884,_T_882,_T_880,_T_878}; // @[Cat.scala 29:58] + wire [4:0] _T_996 = fifo_dbg >> RdPtr; // @[el2_dma_ctrl.scala 359:77] + wire _T_998 = ~_T_996[0]; // @[el2_dma_ctrl.scala 359:68] + wire _T_999 = _T_995 & _T_998; // @[el2_dma_ctrl.scala 359:66] + wire _T_1000 = dma_mem_addr_in_dccm | dma_mem_addr_in_iccm; // @[el2_dma_ctrl.scala 359:111] + wire _T_1001 = ~_T_1000; // @[el2_dma_ctrl.scala 359:88] + wire dma_address_error = _T_999 & _T_1001; // @[el2_dma_ctrl.scala 359:85] + wire _T_1009 = ~dma_address_error; // @[el2_dma_ctrl.scala 360:68] + wire _T_1010 = _T_995 & _T_1009; // @[el2_dma_ctrl.scala 360:66] + reg [2:0] fifo_sz_4; // @[Reg.scala 27:20] + reg [2:0] fifo_sz_3; // @[Reg.scala 27:20] + reg [2:0] fifo_sz_2; // @[Reg.scala 27:20] + reg [2:0] fifo_sz_1; // @[Reg.scala 27:20] + reg [2:0] fifo_sz_0; // @[Reg.scala 27:20] + wire [2:0] _GEN_65 = 3'h1 == RdPtr ? fifo_sz_1 : fifo_sz_0; // @[el2_dma_ctrl.scala 406:20] + wire [2:0] _GEN_66 = 3'h2 == RdPtr ? fifo_sz_2 : _GEN_65; // @[el2_dma_ctrl.scala 406:20] + wire [2:0] _GEN_67 = 3'h3 == RdPtr ? fifo_sz_3 : _GEN_66; // @[el2_dma_ctrl.scala 406:20] + wire [2:0] dma_mem_sz_int = 3'h4 == RdPtr ? fifo_sz_4 : _GEN_67; // @[el2_dma_ctrl.scala 406:20] + wire _T_1012 = dma_mem_sz_int == 3'h1; // @[el2_dma_ctrl.scala 361:28] + wire _T_1014 = _T_1012 & dma_mem_addr_int[0]; // @[el2_dma_ctrl.scala 361:37] + wire _T_1016 = dma_mem_sz_int == 3'h2; // @[el2_dma_ctrl.scala 362:29] + wire _T_1018 = |dma_mem_addr_int[1:0]; // @[el2_dma_ctrl.scala 362:64] + wire _T_1019 = _T_1016 & _T_1018; // @[el2_dma_ctrl.scala 362:38] + wire _T_1020 = _T_1014 | _T_1019; // @[el2_dma_ctrl.scala 361:60] + wire _T_1022 = dma_mem_sz_int == 3'h3; // @[el2_dma_ctrl.scala 363:29] + wire _T_1024 = |dma_mem_addr_int[2:0]; // @[el2_dma_ctrl.scala 363:64] + wire _T_1025 = _T_1022 & _T_1024; // @[el2_dma_ctrl.scala 363:38] + wire _T_1026 = _T_1020 | _T_1025; // @[el2_dma_ctrl.scala 362:70] + wire _T_1028 = dma_mem_sz_int[1:0] == 2'h2; // @[el2_dma_ctrl.scala 364:55] + wire _T_1030 = dma_mem_sz_int[1:0] == 2'h3; // @[el2_dma_ctrl.scala 364:88] + wire _T_1031 = _T_1028 | _T_1030; // @[el2_dma_ctrl.scala 364:64] + wire _T_1032 = ~_T_1031; // @[el2_dma_ctrl.scala 364:31] + wire _T_1033 = dma_mem_addr_in_iccm & _T_1032; // @[el2_dma_ctrl.scala 364:29] + wire _T_1034 = _T_1026 | _T_1033; // @[el2_dma_ctrl.scala 363:70] + wire _T_1035 = dma_mem_addr_in_dccm & io_dma_mem_write; // @[el2_dma_ctrl.scala 365:29] + wire _T_1042 = _T_1035 & _T_1032; // @[el2_dma_ctrl.scala 365:48] + wire _T_1043 = _T_1034 | _T_1042; // @[el2_dma_ctrl.scala 364:108] + wire _T_1046 = io_dma_mem_write & _T_1016; // @[el2_dma_ctrl.scala 366:25] + wire _T_1048 = dma_mem_addr_int[2:0] == 3'h0; // @[el2_dma_ctrl.scala 366:94] + reg [7:0] fifo_byteen_4; // @[Reg.scala 27:20] + reg [7:0] fifo_byteen_3; // @[Reg.scala 27:20] + reg [7:0] fifo_byteen_2; // @[Reg.scala 27:20] + reg [7:0] fifo_byteen_1; // @[Reg.scala 27:20] + reg [7:0] fifo_byteen_0; // @[Reg.scala 27:20] + wire [7:0] _GEN_70 = 3'h1 == RdPtr ? fifo_byteen_1 : fifo_byteen_0; // @[el2_dma_ctrl.scala 409:20] + wire [7:0] _GEN_71 = 3'h2 == RdPtr ? fifo_byteen_2 : _GEN_70; // @[el2_dma_ctrl.scala 409:20] + wire [7:0] _GEN_72 = 3'h3 == RdPtr ? fifo_byteen_3 : _GEN_71; // @[el2_dma_ctrl.scala 409:20] + wire [7:0] dma_mem_byteen = 3'h4 == RdPtr ? fifo_byteen_4 : _GEN_72; // @[el2_dma_ctrl.scala 409:20] + wire [3:0] _T_1059 = _T_1048 ? dma_mem_byteen[3:0] : 4'h0; // @[Mux.scala 27:72] + wire _T_1051 = dma_mem_addr_int[2:0] == 3'h1; // @[el2_dma_ctrl.scala 367:32] + wire [3:0] _T_1060 = _T_1051 ? dma_mem_byteen[4:1] : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1063 = _T_1059 | _T_1060; // @[Mux.scala 27:72] + wire _T_1054 = dma_mem_addr_int[2:0] == 3'h2; // @[el2_dma_ctrl.scala 368:32] + wire [3:0] _T_1061 = _T_1054 ? dma_mem_byteen[5:2] : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1064 = _T_1063 | _T_1061; // @[Mux.scala 27:72] + wire _T_1057 = dma_mem_addr_int[2:0] == 3'h3; // @[el2_dma_ctrl.scala 369:32] + wire [3:0] _T_1062 = _T_1057 ? dma_mem_byteen[6:3] : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1065 = _T_1064 | _T_1062; // @[Mux.scala 27:72] + wire _T_1067 = _T_1065 != 4'hf; // @[el2_dma_ctrl.scala 369:68] + wire _T_1068 = _T_1046 & _T_1067; // @[el2_dma_ctrl.scala 366:58] + wire _T_1069 = _T_1043 | _T_1068; // @[el2_dma_ctrl.scala 365:125] + wire _T_1072 = io_dma_mem_write & _T_1022; // @[el2_dma_ctrl.scala 370:25] + wire _T_1074 = dma_mem_byteen == 8'hf; // @[el2_dma_ctrl.scala 370:83] + wire _T_1076 = dma_mem_byteen == 8'hf0; // @[el2_dma_ctrl.scala 370:119] + wire _T_1077 = _T_1074 | _T_1076; // @[el2_dma_ctrl.scala 370:96] + wire _T_1079 = dma_mem_byteen == 8'hff; // @[el2_dma_ctrl.scala 370:155] + wire _T_1080 = _T_1077 | _T_1079; // @[el2_dma_ctrl.scala 370:132] + wire _T_1081 = ~_T_1080; // @[el2_dma_ctrl.scala 370:60] + wire _T_1082 = _T_1072 & _T_1081; // @[el2_dma_ctrl.scala 370:58] + wire _T_1083 = _T_1069 | _T_1082; // @[el2_dma_ctrl.scala 369:79] + wire dma_alignment_error = _T_1010 & _T_1083; // @[el2_dma_ctrl.scala 360:87] + wire _T_79 = dma_address_error | dma_alignment_error; // @[el2_dma_ctrl.scala 264:213] + wire _T_80 = 3'h0 == RdPtr; // @[el2_dma_ctrl.scala 264:243] + wire _T_81 = _T_79 & _T_80; // @[el2_dma_ctrl.scala 264:236] + wire _T_82 = _T_78 | _T_81; // @[el2_dma_ctrl.scala 264:191] + wire _T_83 = 3'h0 == io_dccm_dma_rtag; // @[el2_dma_ctrl.scala 264:284] + wire _T_84 = io_dccm_dma_rvalid & _T_83; // @[el2_dma_ctrl.scala 264:277] + wire _T_85 = _T_82 | _T_84; // @[el2_dma_ctrl.scala 264:255] + wire _T_86 = 3'h0 == io_iccm_dma_rtag; // @[el2_dma_ctrl.scala 264:336] + wire _T_87 = io_iccm_dma_rvalid & _T_86; // @[el2_dma_ctrl.scala 264:329] + wire _T_88 = _T_85 | _T_87; // @[el2_dma_ctrl.scala 264:307] + wire _T_96 = _T_76 & _T_41; // @[el2_dma_ctrl.scala 264:172] + wire _T_98 = 3'h1 == RdPtr; // @[el2_dma_ctrl.scala 264:243] + wire _T_99 = _T_79 & _T_98; // @[el2_dma_ctrl.scala 264:236] + wire _T_100 = _T_96 | _T_99; // @[el2_dma_ctrl.scala 264:191] + wire _T_101 = 3'h1 == io_dccm_dma_rtag; // @[el2_dma_ctrl.scala 264:284] + wire _T_102 = io_dccm_dma_rvalid & _T_101; // @[el2_dma_ctrl.scala 264:277] + wire _T_103 = _T_100 | _T_102; // @[el2_dma_ctrl.scala 264:255] + wire _T_104 = 3'h1 == io_iccm_dma_rtag; // @[el2_dma_ctrl.scala 264:336] + wire _T_105 = io_iccm_dma_rvalid & _T_104; // @[el2_dma_ctrl.scala 264:329] + wire _T_106 = _T_103 | _T_105; // @[el2_dma_ctrl.scala 264:307] + wire _T_114 = _T_76 & _T_49; // @[el2_dma_ctrl.scala 264:172] + wire _T_116 = 3'h2 == RdPtr; // @[el2_dma_ctrl.scala 264:243] + wire _T_117 = _T_79 & _T_116; // @[el2_dma_ctrl.scala 264:236] + wire _T_118 = _T_114 | _T_117; // @[el2_dma_ctrl.scala 264:191] + wire _T_119 = 3'h2 == io_dccm_dma_rtag; // @[el2_dma_ctrl.scala 264:284] + wire _T_120 = io_dccm_dma_rvalid & _T_119; // @[el2_dma_ctrl.scala 264:277] + wire _T_121 = _T_118 | _T_120; // @[el2_dma_ctrl.scala 264:255] + wire _T_122 = 3'h2 == io_iccm_dma_rtag; // @[el2_dma_ctrl.scala 264:336] + wire _T_123 = io_iccm_dma_rvalid & _T_122; // @[el2_dma_ctrl.scala 264:329] + wire _T_124 = _T_121 | _T_123; // @[el2_dma_ctrl.scala 264:307] + wire _T_132 = _T_76 & _T_57; // @[el2_dma_ctrl.scala 264:172] + wire _T_134 = 3'h3 == RdPtr; // @[el2_dma_ctrl.scala 264:243] + wire _T_135 = _T_79 & _T_134; // @[el2_dma_ctrl.scala 264:236] + wire _T_136 = _T_132 | _T_135; // @[el2_dma_ctrl.scala 264:191] + wire _T_137 = 3'h3 == io_dccm_dma_rtag; // @[el2_dma_ctrl.scala 264:284] + wire _T_138 = io_dccm_dma_rvalid & _T_137; // @[el2_dma_ctrl.scala 264:277] + wire _T_139 = _T_136 | _T_138; // @[el2_dma_ctrl.scala 264:255] + wire _T_140 = 3'h3 == io_iccm_dma_rtag; // @[el2_dma_ctrl.scala 264:336] + wire _T_141 = io_iccm_dma_rvalid & _T_140; // @[el2_dma_ctrl.scala 264:329] + wire _T_142 = _T_139 | _T_141; // @[el2_dma_ctrl.scala 264:307] + wire _T_150 = _T_76 & _T_65; // @[el2_dma_ctrl.scala 264:172] + wire _T_152 = 3'h4 == RdPtr; // @[el2_dma_ctrl.scala 264:243] + wire _T_153 = _T_79 & _T_152; // @[el2_dma_ctrl.scala 264:236] + wire _T_154 = _T_150 | _T_153; // @[el2_dma_ctrl.scala 264:191] + wire _T_155 = 3'h4 == io_dccm_dma_rtag; // @[el2_dma_ctrl.scala 264:284] + wire _T_156 = io_dccm_dma_rvalid & _T_155; // @[el2_dma_ctrl.scala 264:277] + wire _T_157 = _T_154 | _T_156; // @[el2_dma_ctrl.scala 264:255] + wire _T_158 = 3'h4 == io_iccm_dma_rtag; // @[el2_dma_ctrl.scala 264:336] + wire _T_159 = io_iccm_dma_rvalid & _T_158; // @[el2_dma_ctrl.scala 264:329] + wire _T_160 = _T_157 | _T_159; // @[el2_dma_ctrl.scala 264:307] + wire [4:0] fifo_data_en = {_T_160,_T_142,_T_124,_T_106,_T_88}; // @[Cat.scala 29:58] + wire _T_165 = io_dma_dccm_req | io_dma_iccm_req; // @[el2_dma_ctrl.scala 266:75] + wire _T_166 = ~io_dma_mem_write; // @[el2_dma_ctrl.scala 266:96] + wire _T_167 = _T_165 & _T_166; // @[el2_dma_ctrl.scala 266:94] + wire _T_169 = _T_167 & _T_80; // @[el2_dma_ctrl.scala 266:114] + wire _T_174 = _T_167 & _T_98; // @[el2_dma_ctrl.scala 266:114] + wire _T_179 = _T_167 & _T_116; // @[el2_dma_ctrl.scala 266:114] + wire _T_184 = _T_167 & _T_134; // @[el2_dma_ctrl.scala 266:114] + wire _T_189 = _T_167 & _T_152; // @[el2_dma_ctrl.scala 266:114] + wire [4:0] fifo_pend_en = {_T_189,_T_184,_T_179,_T_174,_T_169}; // @[Cat.scala 29:58] + wire _T_1107 = _T_995 & _T_996[0]; // @[el2_dma_ctrl.scala 379:66] + wire _T_1109 = _T_1000 | dma_mem_addr_in_pic; // @[el2_dma_ctrl.scala 379:134] + wire _T_1110 = ~_T_1109; // @[el2_dma_ctrl.scala 379:88] + wire _T_1113 = dma_mem_sz_int[1:0] != 2'h2; // @[el2_dma_ctrl.scala 379:191] + wire _T_1114 = _T_1110 | _T_1113; // @[el2_dma_ctrl.scala 379:167] + wire dma_dbg_cmd_error = _T_1107 & _T_1114; // @[el2_dma_ctrl.scala 379:84] + wire _T_197 = _T_79 | dma_dbg_cmd_error; // @[el2_dma_ctrl.scala 268:114] + wire _T_199 = _T_197 & _T_80; // @[el2_dma_ctrl.scala 268:135] + wire _T_200 = io_dccm_dma_rvalid & io_dccm_dma_ecc_error; // @[el2_dma_ctrl.scala 268:177] + wire _T_202 = _T_200 & _T_83; // @[el2_dma_ctrl.scala 268:202] + wire _T_203 = _T_199 | _T_202; // @[el2_dma_ctrl.scala 268:154] + wire _T_204 = io_iccm_dma_rvalid & io_iccm_dma_ecc_error; // @[el2_dma_ctrl.scala 268:255] + wire _T_206 = _T_204 & _T_86; // @[el2_dma_ctrl.scala 268:280] + wire _T_207 = _T_203 | _T_206; // @[el2_dma_ctrl.scala 268:232] + wire _T_213 = _T_197 & _T_98; // @[el2_dma_ctrl.scala 268:135] + wire _T_216 = _T_200 & _T_101; // @[el2_dma_ctrl.scala 268:202] + wire _T_217 = _T_213 | _T_216; // @[el2_dma_ctrl.scala 268:154] + wire _T_220 = _T_204 & _T_104; // @[el2_dma_ctrl.scala 268:280] + wire _T_221 = _T_217 | _T_220; // @[el2_dma_ctrl.scala 268:232] + wire _T_227 = _T_197 & _T_116; // @[el2_dma_ctrl.scala 268:135] + wire _T_230 = _T_200 & _T_119; // @[el2_dma_ctrl.scala 268:202] + wire _T_231 = _T_227 | _T_230; // @[el2_dma_ctrl.scala 268:154] + wire _T_234 = _T_204 & _T_122; // @[el2_dma_ctrl.scala 268:280] + wire _T_235 = _T_231 | _T_234; // @[el2_dma_ctrl.scala 268:232] + wire _T_241 = _T_197 & _T_134; // @[el2_dma_ctrl.scala 268:135] + wire _T_244 = _T_200 & _T_137; // @[el2_dma_ctrl.scala 268:202] + wire _T_245 = _T_241 | _T_244; // @[el2_dma_ctrl.scala 268:154] + wire _T_248 = _T_204 & _T_140; // @[el2_dma_ctrl.scala 268:280] + wire _T_249 = _T_245 | _T_248; // @[el2_dma_ctrl.scala 268:232] + wire _T_255 = _T_197 & _T_152; // @[el2_dma_ctrl.scala 268:135] + wire _T_258 = _T_200 & _T_155; // @[el2_dma_ctrl.scala 268:202] + wire _T_259 = _T_255 | _T_258; // @[el2_dma_ctrl.scala 268:154] + wire _T_262 = _T_204 & _T_158; // @[el2_dma_ctrl.scala 268:280] + wire _T_263 = _T_259 | _T_262; // @[el2_dma_ctrl.scala 268:232] + wire [4:0] fifo_error_en = {_T_263,_T_249,_T_235,_T_221,_T_207}; // @[Cat.scala 29:58] + wire [1:0] _T_436 = {1'h0,io_dccm_dma_ecc_error}; // @[Cat.scala 29:58] + wire [1:0] _T_439 = {1'h0,io_iccm_dma_ecc_error}; // @[Cat.scala 29:58] + wire [1:0] _T_442 = {_T_197,dma_alignment_error}; // @[Cat.scala 29:58] + wire [1:0] _T_443 = _T_87 ? _T_439 : _T_442; // @[el2_dma_ctrl.scala 278:146] + wire [1:0] fifo_error_in_0 = _T_84 ? _T_436 : _T_443; // @[el2_dma_ctrl.scala 278:60] + wire _T_269 = |fifo_error_in_0; // @[el2_dma_ctrl.scala 270:83] + reg [1:0] fifo_error_0; // @[el2_dma_ctrl.scala 284:85] + wire _T_272 = |fifo_error_0; // @[el2_dma_ctrl.scala 270:125] + wire [1:0] _T_454 = _T_105 ? _T_439 : _T_442; // @[el2_dma_ctrl.scala 278:146] + wire [1:0] fifo_error_in_1 = _T_102 ? _T_436 : _T_454; // @[el2_dma_ctrl.scala 278:60] + wire _T_276 = |fifo_error_in_1; // @[el2_dma_ctrl.scala 270:83] + reg [1:0] fifo_error_1; // @[el2_dma_ctrl.scala 284:85] + wire _T_279 = |fifo_error_1; // @[el2_dma_ctrl.scala 270:125] + wire [1:0] _T_465 = _T_123 ? _T_439 : _T_442; // @[el2_dma_ctrl.scala 278:146] + wire [1:0] fifo_error_in_2 = _T_120 ? _T_436 : _T_465; // @[el2_dma_ctrl.scala 278:60] + wire _T_283 = |fifo_error_in_2; // @[el2_dma_ctrl.scala 270:83] + reg [1:0] fifo_error_2; // @[el2_dma_ctrl.scala 284:85] + wire _T_286 = |fifo_error_2; // @[el2_dma_ctrl.scala 270:125] + wire [1:0] _T_476 = _T_141 ? _T_439 : _T_442; // @[el2_dma_ctrl.scala 278:146] + wire [1:0] fifo_error_in_3 = _T_138 ? _T_436 : _T_476; // @[el2_dma_ctrl.scala 278:60] + wire _T_290 = |fifo_error_in_3; // @[el2_dma_ctrl.scala 270:83] + reg [1:0] fifo_error_3; // @[el2_dma_ctrl.scala 284:85] + wire _T_293 = |fifo_error_3; // @[el2_dma_ctrl.scala 270:125] + wire [1:0] _T_487 = _T_159 ? _T_439 : _T_442; // @[el2_dma_ctrl.scala 278:146] + wire [1:0] fifo_error_in_4 = _T_156 ? _T_436 : _T_487; // @[el2_dma_ctrl.scala 278:60] + wire _T_297 = |fifo_error_in_4; // @[el2_dma_ctrl.scala 270:83] + reg [1:0] fifo_error_4; // @[el2_dma_ctrl.scala 284:85] + wire _T_300 = |fifo_error_4; // @[el2_dma_ctrl.scala 270:125] + wire _T_309 = _T_272 | fifo_error_en[0]; // @[el2_dma_ctrl.scala 272:78] + wire _T_311 = _T_165 & io_dma_mem_write; // @[el2_dma_ctrl.scala 272:136] + wire _T_312 = _T_309 | _T_311; // @[el2_dma_ctrl.scala 272:97] + wire _T_314 = _T_312 & _T_80; // @[el2_dma_ctrl.scala 272:157] + wire _T_317 = _T_314 | _T_84; // @[el2_dma_ctrl.scala 272:176] + wire _T_320 = _T_317 | _T_87; // @[el2_dma_ctrl.scala 272:228] + wire _T_323 = _T_279 | fifo_error_en[1]; // @[el2_dma_ctrl.scala 272:78] + wire _T_326 = _T_323 | _T_311; // @[el2_dma_ctrl.scala 272:97] + wire _T_328 = _T_326 & _T_98; // @[el2_dma_ctrl.scala 272:157] + wire _T_331 = _T_328 | _T_102; // @[el2_dma_ctrl.scala 272:176] + wire _T_334 = _T_331 | _T_105; // @[el2_dma_ctrl.scala 272:228] + wire _T_337 = _T_286 | fifo_error_en[2]; // @[el2_dma_ctrl.scala 272:78] + wire _T_340 = _T_337 | _T_311; // @[el2_dma_ctrl.scala 272:97] + wire _T_342 = _T_340 & _T_116; // @[el2_dma_ctrl.scala 272:157] + wire _T_345 = _T_342 | _T_120; // @[el2_dma_ctrl.scala 272:176] + wire _T_348 = _T_345 | _T_123; // @[el2_dma_ctrl.scala 272:228] + wire _T_351 = _T_293 | fifo_error_en[3]; // @[el2_dma_ctrl.scala 272:78] + wire _T_354 = _T_351 | _T_311; // @[el2_dma_ctrl.scala 272:97] + wire _T_356 = _T_354 & _T_134; // @[el2_dma_ctrl.scala 272:157] + wire _T_359 = _T_356 | _T_138; // @[el2_dma_ctrl.scala 272:176] + wire _T_362 = _T_359 | _T_141; // @[el2_dma_ctrl.scala 272:228] + wire _T_365 = _T_300 | fifo_error_en[4]; // @[el2_dma_ctrl.scala 272:78] + wire _T_368 = _T_365 | _T_311; // @[el2_dma_ctrl.scala 272:97] + wire _T_370 = _T_368 & _T_152; // @[el2_dma_ctrl.scala 272:157] + wire _T_373 = _T_370 | _T_156; // @[el2_dma_ctrl.scala 272:176] + wire _T_376 = _T_373 | _T_159; // @[el2_dma_ctrl.scala 272:228] + wire [4:0] fifo_done_en = {_T_376,_T_362,_T_348,_T_334,_T_320}; // @[Cat.scala 29:58] + wire _T_383 = fifo_done_en[0] | fifo_done[0]; // @[el2_dma_ctrl.scala 274:75] + wire _T_384 = _T_383 & io_dma_bus_clk_en; // @[el2_dma_ctrl.scala 274:91] + wire _T_387 = fifo_done_en[1] | fifo_done[1]; // @[el2_dma_ctrl.scala 274:75] + wire _T_388 = _T_387 & io_dma_bus_clk_en; // @[el2_dma_ctrl.scala 274:91] + wire _T_391 = fifo_done_en[2] | fifo_done[2]; // @[el2_dma_ctrl.scala 274:75] + wire _T_392 = _T_391 & io_dma_bus_clk_en; // @[el2_dma_ctrl.scala 274:91] + wire _T_395 = fifo_done_en[3] | fifo_done[3]; // @[el2_dma_ctrl.scala 274:75] + wire _T_396 = _T_395 & io_dma_bus_clk_en; // @[el2_dma_ctrl.scala 274:91] + wire _T_399 = fifo_done_en[4] | fifo_done[4]; // @[el2_dma_ctrl.scala 274:75] + wire _T_400 = _T_399 & io_dma_bus_clk_en; // @[el2_dma_ctrl.scala 274:91] + wire [4:0] fifo_done_bus_en = {_T_400,_T_396,_T_392,_T_388,_T_384}; // @[Cat.scala 29:58] + wire _T_1265 = io_dma_axi_bvalid & io_dma_axi_bready; // @[el2_dma_ctrl.scala 552:60] + wire _T_1266 = io_dma_axi_rvalid & io_dma_axi_rready; // @[el2_dma_ctrl.scala 552:102] + wire bus_rsp_sent = _T_1265 | _T_1266; // @[el2_dma_ctrl.scala 552:81] + wire _T_406 = bus_rsp_sent & io_dma_bus_clk_en; // @[el2_dma_ctrl.scala 276:99] + wire _T_407 = _T_406 | io_dma_dbg_cmd_done; // @[el2_dma_ctrl.scala 276:120] + reg [2:0] RspPtr; // @[Reg.scala 27:20] + wire _T_408 = 3'h0 == RspPtr; // @[el2_dma_ctrl.scala 276:150] + wire _T_409 = _T_407 & _T_408; // @[el2_dma_ctrl.scala 276:143] + wire _T_413 = 3'h1 == RspPtr; // @[el2_dma_ctrl.scala 276:150] + wire _T_414 = _T_407 & _T_413; // @[el2_dma_ctrl.scala 276:143] + wire _T_418 = 3'h2 == RspPtr; // @[el2_dma_ctrl.scala 276:150] + wire _T_419 = _T_407 & _T_418; // @[el2_dma_ctrl.scala 276:143] + wire _T_423 = 3'h3 == RspPtr; // @[el2_dma_ctrl.scala 276:150] + wire _T_424 = _T_407 & _T_423; // @[el2_dma_ctrl.scala 276:143] + wire _T_428 = 3'h4 == RspPtr; // @[el2_dma_ctrl.scala 276:150] + wire _T_429 = _T_407 & _T_428; // @[el2_dma_ctrl.scala 276:143] + wire [4:0] fifo_reset = {_T_429,_T_424,_T_419,_T_414,_T_409}; // @[Cat.scala 29:58] + wire _T_491 = fifo_error_en[0] & _T_269; // @[el2_dma_ctrl.scala 280:77] + wire [63:0] _T_493 = {32'h0,fifo_addr_0}; // @[Cat.scala 29:58] + wire [63:0] _T_498 = {io_dbg_cmd_wrdata,io_dbg_cmd_wrdata}; // @[Cat.scala 29:58] + reg [63:0] wrbuf_data; // @[el2_lib.scala 514:16] + wire [63:0] _T_500 = io_dbg_cmd_valid ? _T_498 : wrbuf_data; // @[el2_dma_ctrl.scala 280:284] + wire _T_506 = fifo_error_en[1] & _T_276; // @[el2_dma_ctrl.scala 280:77] + wire [63:0] _T_508 = {32'h0,fifo_addr_1}; // @[Cat.scala 29:58] + wire _T_521 = fifo_error_en[2] & _T_283; // @[el2_dma_ctrl.scala 280:77] + wire [63:0] _T_523 = {32'h0,fifo_addr_2}; // @[Cat.scala 29:58] + wire _T_536 = fifo_error_en[3] & _T_290; // @[el2_dma_ctrl.scala 280:77] + wire [63:0] _T_538 = {32'h0,fifo_addr_3}; // @[Cat.scala 29:58] + wire _T_551 = fifo_error_en[4] & _T_297; // @[el2_dma_ctrl.scala 280:77] + wire [63:0] _T_553 = {32'h0,fifo_addr_4}; // @[Cat.scala 29:58] + wire _T_566 = fifo_cmd_en[0] | fifo_valid[0]; // @[el2_dma_ctrl.scala 282:86] + wire _T_568 = ~fifo_reset[0]; // @[el2_dma_ctrl.scala 282:125] + wire _T_573 = fifo_cmd_en[1] | fifo_valid[1]; // @[el2_dma_ctrl.scala 282:86] + wire _T_575 = ~fifo_reset[1]; // @[el2_dma_ctrl.scala 282:125] + wire _T_580 = fifo_cmd_en[2] | fifo_valid[2]; // @[el2_dma_ctrl.scala 282:86] + wire _T_582 = ~fifo_reset[2]; // @[el2_dma_ctrl.scala 282:125] + wire _T_587 = fifo_cmd_en[3] | fifo_valid[3]; // @[el2_dma_ctrl.scala 282:86] + wire _T_589 = ~fifo_reset[3]; // @[el2_dma_ctrl.scala 282:125] + wire _T_594 = fifo_cmd_en[4] | fifo_valid[4]; // @[el2_dma_ctrl.scala 282:86] + wire _T_596 = ~fifo_reset[4]; // @[el2_dma_ctrl.scala 282:125] + wire [1:0] _T_605 = fifo_error_en[0] ? fifo_error_in_0 : fifo_error_0; // @[el2_dma_ctrl.scala 284:89] + wire [1:0] _T_609 = _T_568 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_614 = fifo_error_en[1] ? fifo_error_in_1 : fifo_error_1; // @[el2_dma_ctrl.scala 284:89] + wire [1:0] _T_618 = _T_575 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_623 = fifo_error_en[2] ? fifo_error_in_2 : fifo_error_2; // @[el2_dma_ctrl.scala 284:89] + wire [1:0] _T_627 = _T_582 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_632 = fifo_error_en[3] ? fifo_error_in_3 : fifo_error_3; // @[el2_dma_ctrl.scala 284:89] + wire [1:0] _T_636 = _T_589 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_641 = fifo_error_en[4] ? fifo_error_in_4 : fifo_error_4; // @[el2_dma_ctrl.scala 284:89] + wire [1:0] _T_645 = _T_596 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + reg _T_721; // @[el2_dma_ctrl.scala 288:89] + reg _T_714; // @[el2_dma_ctrl.scala 288:89] + reg _T_707; // @[el2_dma_ctrl.scala 288:89] + reg _T_700; // @[el2_dma_ctrl.scala 288:89] + reg _T_693; // @[el2_dma_ctrl.scala 288:89] + wire [4:0] fifo_rpend = {_T_721,_T_714,_T_707,_T_700,_T_693}; // @[Cat.scala 29:58] + wire _T_689 = fifo_pend_en[0] | fifo_rpend[0]; // @[el2_dma_ctrl.scala 288:93] + wire _T_696 = fifo_pend_en[1] | fifo_rpend[1]; // @[el2_dma_ctrl.scala 288:93] + wire _T_703 = fifo_pend_en[2] | fifo_rpend[2]; // @[el2_dma_ctrl.scala 288:93] + wire _T_710 = fifo_pend_en[3] | fifo_rpend[3]; // @[el2_dma_ctrl.scala 288:93] + wire _T_717 = fifo_pend_en[4] | fifo_rpend[4]; // @[el2_dma_ctrl.scala 288:93] + reg _T_799; // @[el2_dma_ctrl.scala 292:89] + reg _T_792; // @[el2_dma_ctrl.scala 292:89] + reg _T_785; // @[el2_dma_ctrl.scala 292:89] + reg _T_778; // @[el2_dma_ctrl.scala 292:89] + reg _T_771; // @[el2_dma_ctrl.scala 292:89] + wire [4:0] fifo_done_bus = {_T_799,_T_792,_T_785,_T_778,_T_771}; // @[Cat.scala 29:58] + wire _T_767 = fifo_done_bus_en[0] | fifo_done_bus[0]; // @[el2_dma_ctrl.scala 292:93] + wire _T_774 = fifo_done_bus_en[1] | fifo_done_bus[1]; // @[el2_dma_ctrl.scala 292:93] + wire _T_781 = fifo_done_bus_en[2] | fifo_done_bus[2]; // @[el2_dma_ctrl.scala 292:93] + wire _T_788 = fifo_done_bus_en[3] | fifo_done_bus[3]; // @[el2_dma_ctrl.scala 292:93] + wire _T_795 = fifo_done_bus_en[4] | fifo_done_bus[4]; // @[el2_dma_ctrl.scala 292:93] + wire [7:0] fifo_byteen_in = _T_20[7:0]; // @[el2_dma_ctrl.scala 251:28] + reg _T_850; // @[Reg.scala 27:20] + reg _T_852; // @[Reg.scala 27:20] + reg _T_854; // @[Reg.scala 27:20] + reg _T_856; // @[Reg.scala 27:20] + reg _T_858; // @[Reg.scala 27:20] + wire [4:0] fifo_write = {_T_858,_T_856,_T_854,_T_852,_T_850}; // @[Cat.scala 29:58] + reg [63:0] fifo_data_0; // @[el2_lib.scala 514:16] + reg [63:0] fifo_data_1; // @[el2_lib.scala 514:16] + reg [63:0] fifo_data_2; // @[el2_lib.scala 514:16] + reg [63:0] fifo_data_3; // @[el2_lib.scala 514:16] + reg [63:0] fifo_data_4; // @[el2_lib.scala 514:16] + reg fifo_tag_0; // @[Reg.scala 27:20] + reg wrbuf_tag; // @[Reg.scala 27:20] + reg rdbuf_tag; // @[Reg.scala 27:20] + wire bus_cmd_tag = axi_mstr_sel ? wrbuf_tag : rdbuf_tag; // @[el2_dma_ctrl.scala 517:43] + reg fifo_tag_1; // @[Reg.scala 27:20] + reg fifo_tag_2; // @[Reg.scala 27:20] + reg fifo_tag_3; // @[Reg.scala 27:20] + reg fifo_tag_4; // @[Reg.scala 27:20] + wire _T_931 = WrPtr == 3'h4; // @[el2_dma_ctrl.scala 316:30] + wire [2:0] _T_934 = WrPtr + 3'h1; // @[el2_dma_ctrl.scala 316:76] + wire _T_936 = RdPtr == 3'h4; // @[el2_dma_ctrl.scala 318:30] + wire [2:0] _T_939 = RdPtr + 3'h1; // @[el2_dma_ctrl.scala 318:76] + wire _T_941 = RspPtr == 3'h4; // @[el2_dma_ctrl.scala 320:31] + wire [2:0] _T_944 = RspPtr + 3'h1; // @[el2_dma_ctrl.scala 320:78] + wire WrPtrEn = |fifo_cmd_en; // @[el2_dma_ctrl.scala 322:30] + wire RdPtrEn = _T_165 | _T_197; // @[el2_dma_ctrl.scala 324:53] + wire RspPtrEn = io_dma_dbg_cmd_done | _T_406; // @[el2_dma_ctrl.scala 326:39] + wire [3:0] _T_966 = {3'h0,fifo_valid[0]}; // @[Cat.scala 29:58] + wire [3:0] _T_969 = {3'h0,fifo_valid[1]}; // @[Cat.scala 29:58] + wire [3:0] _T_972 = {3'h0,fifo_valid[2]}; // @[Cat.scala 29:58] + wire [3:0] _T_975 = {3'h0,fifo_valid[3]}; // @[Cat.scala 29:58] + wire [3:0] _T_978 = {3'h0,fifo_valid[4]}; // @[Cat.scala 29:58] + wire [3:0] _T_980 = _T_966 + _T_969; // @[el2_dma_ctrl.scala 349:102] + wire [3:0] _T_982 = _T_980 + _T_972; // @[el2_dma_ctrl.scala 349:102] + wire [3:0] _T_984 = _T_982 + _T_975; // @[el2_dma_ctrl.scala 349:102] + wire [3:0] num_fifo_vld_tmp2 = _T_984 + _T_978; // @[el2_dma_ctrl.scala 349:102] + wire _T_1123 = |fifo_valid; // @[el2_dma_ctrl.scala 388:30] + wire fifo_empty = ~_T_1123; // @[el2_dma_ctrl.scala 388:17] + wire [4:0] _T_1086 = fifo_valid >> RspPtr; // @[el2_dma_ctrl.scala 375:39] + wire [4:0] _T_1088 = fifo_dbg >> RspPtr; // @[el2_dma_ctrl.scala 375:58] + wire _T_1090 = _T_1086[0] & _T_1088[0]; // @[el2_dma_ctrl.scala 375:48] + wire [4:0] _T_1091 = fifo_done >> RspPtr; // @[el2_dma_ctrl.scala 375:78] + wire [31:0] _GEN_44 = 3'h1 == RspPtr ? fifo_addr_1 : fifo_addr_0; // @[el2_dma_ctrl.scala 376:49] + wire [31:0] _GEN_45 = 3'h2 == RspPtr ? fifo_addr_2 : _GEN_44; // @[el2_dma_ctrl.scala 376:49] + wire [31:0] _GEN_46 = 3'h3 == RspPtr ? fifo_addr_3 : _GEN_45; // @[el2_dma_ctrl.scala 376:49] + wire [31:0] _GEN_47 = 3'h4 == RspPtr ? fifo_addr_4 : _GEN_46; // @[el2_dma_ctrl.scala 376:49] + wire [63:0] _GEN_49 = 3'h1 == RspPtr ? fifo_data_1 : fifo_data_0; // @[el2_dma_ctrl.scala 376:71] + wire [63:0] _GEN_50 = 3'h2 == RspPtr ? fifo_data_2 : _GEN_49; // @[el2_dma_ctrl.scala 376:71] + wire [63:0] _GEN_51 = 3'h3 == RspPtr ? fifo_data_3 : _GEN_50; // @[el2_dma_ctrl.scala 376:71] + wire [63:0] _GEN_52 = 3'h4 == RspPtr ? fifo_data_4 : _GEN_51; // @[el2_dma_ctrl.scala 376:71] + wire [1:0] _GEN_54 = 3'h1 == RspPtr ? fifo_error_1 : fifo_error_0; // @[el2_dma_ctrl.scala 377:47] + wire [1:0] _GEN_55 = 3'h2 == RspPtr ? fifo_error_2 : _GEN_54; // @[el2_dma_ctrl.scala 377:47] + wire [1:0] _GEN_56 = 3'h3 == RspPtr ? fifo_error_3 : _GEN_55; // @[el2_dma_ctrl.scala 377:47] + wire [1:0] _GEN_57 = 3'h4 == RspPtr ? fifo_error_4 : _GEN_56; // @[el2_dma_ctrl.scala 377:47] + wire _T_1116 = dma_mem_addr_in_dccm | dma_mem_addr_in_pic; // @[el2_dma_ctrl.scala 383:64] + wire [4:0] _T_1145 = fifo_rpend >> RdPtr; // @[el2_dma_ctrl.scala 401:54] + wire _T_1147 = ~_T_1145[0]; // @[el2_dma_ctrl.scala 401:43] + wire _T_1148 = _T_990[0] & _T_1147; // @[el2_dma_ctrl.scala 401:41] + wire _T_1152 = _T_1148 & _T_994; // @[el2_dma_ctrl.scala 401:62] + wire _T_1155 = ~_T_197; // @[el2_dma_ctrl.scala 401:84] + wire dma_mem_req = _T_1152 & _T_1155; // @[el2_dma_ctrl.scala 401:82] + wire _T_1117 = dma_mem_req & _T_1116; // @[el2_dma_ctrl.scala 383:40] + reg [2:0] dma_nack_count; // @[Reg.scala 27:20] + wire _T_1118 = dma_nack_count >= io_dec_tlu_dma_qos_prty; // @[el2_dma_ctrl.scala 383:105] + wire _T_1120 = dma_mem_req & dma_mem_addr_in_iccm; // @[el2_dma_ctrl.scala 384:40] + wire _T_1127 = ~_T_165; // @[el2_dma_ctrl.scala 393:77] + wire [2:0] _T_1129 = _T_1127 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_1131 = _T_1129 & dma_nack_count; // @[el2_dma_ctrl.scala 393:115] + wire _T_1135 = dma_mem_req & _T_1127; // @[el2_dma_ctrl.scala 393:163] + wire [2:0] _T_1138 = dma_nack_count + 3'h1; // @[el2_dma_ctrl.scala 393:224] + wire _T_1164 = io_dma_mem_write & _T_1076; // @[el2_dma_ctrl.scala 407:44] + wire [31:0] _T_1168 = {dma_mem_addr_int[31:3],1'h1,dma_mem_addr_int[1:0]}; // @[Cat.scala 29:58] + wire _T_1176 = io_dma_mem_write & _T_1077; // @[el2_dma_ctrl.scala 408:44] + wire [4:0] _T_1179 = fifo_write >> RdPtr; // @[el2_dma_ctrl.scala 410:33] + wire [63:0] _GEN_75 = 3'h1 == RdPtr ? fifo_data_1 : fifo_data_0; // @[el2_dma_ctrl.scala 411:20] + wire [63:0] _GEN_76 = 3'h2 == RdPtr ? fifo_data_2 : _GEN_75; // @[el2_dma_ctrl.scala 411:20] + wire [63:0] _GEN_77 = 3'h3 == RdPtr ? fifo_data_3 : _GEN_76; // @[el2_dma_ctrl.scala 411:20] + reg dma_dbg_cmd_done_q; // @[el2_dma_ctrl.scala 431:12] + wire _T_1192 = bus_cmd_valid & io_dma_bus_clk_en; // @[el2_dma_ctrl.scala 436:44] + wire _T_1193 = _T_1192 | io_dbg_cmd_valid; // @[el2_dma_ctrl.scala 436:65] + wire bus_rsp_valid = io_dma_axi_bvalid | io_dma_axi_rvalid; // @[el2_dma_ctrl.scala 551:59] + wire _T_1194 = bus_cmd_valid | bus_rsp_valid; // @[el2_dma_ctrl.scala 437:44] + wire _T_1195 = _T_1194 | io_dbg_cmd_valid; // @[el2_dma_ctrl.scala 437:60] + wire _T_1196 = _T_1195 | io_dma_dbg_cmd_done; // @[el2_dma_ctrl.scala 437:79] + wire _T_1197 = _T_1196 | dma_dbg_cmd_done_q; // @[el2_dma_ctrl.scala 437:101] + wire _T_1199 = _T_1197 | _T_1123; // @[el2_dma_ctrl.scala 437:122] + wire wrbuf_en = io_dma_axi_awvalid & io_dma_axi_awready; // @[el2_dma_ctrl.scala 459:46] + wire wrbuf_data_en = io_dma_axi_wvalid & io_dma_axi_wready; // @[el2_dma_ctrl.scala 460:45] + wire wrbuf_cmd_sent = axi_mstr_prty_en & axi_mstr_sel; // @[el2_dma_ctrl.scala 461:40] + wire _T_1201 = ~wrbuf_en; // @[el2_dma_ctrl.scala 462:51] + wire wrbuf_rst = wrbuf_cmd_sent & _T_1201; // @[el2_dma_ctrl.scala 462:49] + wire _T_1203 = ~wrbuf_data_en; // @[el2_dma_ctrl.scala 463:51] + wire wrbuf_data_rst = wrbuf_cmd_sent & _T_1203; // @[el2_dma_ctrl.scala 463:49] + wire _T_1204 = wrbuf_en | wrbuf_vld; // @[el2_dma_ctrl.scala 465:63] + wire _T_1205 = ~wrbuf_rst; // @[el2_dma_ctrl.scala 465:92] + wire _T_1208 = wrbuf_data_en | wrbuf_data_vld; // @[el2_dma_ctrl.scala 467:63] + wire _T_1209 = ~wrbuf_data_rst; // @[el2_dma_ctrl.scala 467:102] + wire rdbuf_en = io_dma_axi_arvalid & io_dma_axi_arready; // @[el2_dma_ctrl.scala 487:58] + wire _T_1214 = ~axi_mstr_sel; // @[el2_dma_ctrl.scala 488:44] + wire rdbuf_cmd_sent = axi_mstr_prty_en & _T_1214; // @[el2_dma_ctrl.scala 488:42] + wire _T_1216 = ~rdbuf_en; // @[el2_dma_ctrl.scala 489:63] + wire rdbuf_rst = rdbuf_cmd_sent & _T_1216; // @[el2_dma_ctrl.scala 489:61] + wire _T_1217 = rdbuf_en | rdbuf_vld; // @[el2_dma_ctrl.scala 491:51] + wire _T_1218 = ~rdbuf_rst; // @[el2_dma_ctrl.scala 491:80] + wire _T_1222 = ~wrbuf_cmd_sent; // @[el2_dma_ctrl.scala 503:44] + wire _T_1223 = wrbuf_vld & _T_1222; // @[el2_dma_ctrl.scala 503:42] + wire _T_1226 = wrbuf_data_vld & _T_1222; // @[el2_dma_ctrl.scala 504:47] + wire _T_1228 = ~rdbuf_cmd_sent; // @[el2_dma_ctrl.scala 505:44] + wire _T_1229 = rdbuf_vld & _T_1228; // @[el2_dma_ctrl.scala 505:42] + wire axi_mstr_prty_in = ~axi_mstr_priority; // @[el2_dma_ctrl.scala 524:27] + wire _T_1251 = ~_T_1088[0]; // @[el2_dma_ctrl.scala 531:50] + wire _T_1252 = _T_1086[0] & _T_1251; // @[el2_dma_ctrl.scala 531:48] + wire [4:0] _T_1253 = fifo_done_bus >> RspPtr; // @[el2_dma_ctrl.scala 531:83] + wire axi_rsp_valid = _T_1252 & _T_1253[0]; // @[el2_dma_ctrl.scala 531:68] + wire [4:0] _T_1255 = fifo_write >> RspPtr; // @[el2_dma_ctrl.scala 533:39] + wire axi_rsp_write = _T_1255[0]; // @[el2_dma_ctrl.scala 533:39] + wire [1:0] _T_1258 = _GEN_57[1] ? 2'h3 : 2'h0; // @[el2_dma_ctrl.scala 534:64] + wire _GEN_86 = 3'h1 == RspPtr ? fifo_tag_1 : fifo_tag_0; // @[el2_dma_ctrl.scala 542:33] + wire _GEN_87 = 3'h2 == RspPtr ? fifo_tag_2 : _GEN_86; // @[el2_dma_ctrl.scala 542:33] + wire _GEN_88 = 3'h3 == RspPtr ? fifo_tag_3 : _GEN_87; // @[el2_dma_ctrl.scala 542:33] + wire _T_1261 = ~axi_rsp_write; // @[el2_dma_ctrl.scala 544:46] + rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_io_l1clk), + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en), + .io_scan_mode(rvclkhdr_io_scan_mode) + ); + rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_1_io_l1clk), + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en), + .io_scan_mode(rvclkhdr_1_io_scan_mode) + ); + rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_2_io_l1clk), + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en), + .io_scan_mode(rvclkhdr_2_io_scan_mode) + ); + rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_3_io_l1clk), + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en), + .io_scan_mode(rvclkhdr_3_io_scan_mode) + ); + rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_4_io_l1clk), + .io_clk(rvclkhdr_4_io_clk), + .io_en(rvclkhdr_4_io_en), + .io_scan_mode(rvclkhdr_4_io_scan_mode) + ); + rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_5_io_l1clk), + .io_clk(rvclkhdr_5_io_clk), + .io_en(rvclkhdr_5_io_en), + .io_scan_mode(rvclkhdr_5_io_scan_mode) + ); + rvclkhdr rvclkhdr_6 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_6_io_l1clk), + .io_clk(rvclkhdr_6_io_clk), + .io_en(rvclkhdr_6_io_en), + .io_scan_mode(rvclkhdr_6_io_scan_mode) + ); + rvclkhdr rvclkhdr_7 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_7_io_l1clk), + .io_clk(rvclkhdr_7_io_clk), + .io_en(rvclkhdr_7_io_en), + .io_scan_mode(rvclkhdr_7_io_scan_mode) + ); + rvclkhdr rvclkhdr_8 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_8_io_l1clk), + .io_clk(rvclkhdr_8_io_clk), + .io_en(rvclkhdr_8_io_en), + .io_scan_mode(rvclkhdr_8_io_scan_mode) + ); + rvclkhdr rvclkhdr_9 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_9_io_l1clk), + .io_clk(rvclkhdr_9_io_clk), + .io_en(rvclkhdr_9_io_en), + .io_scan_mode(rvclkhdr_9_io_scan_mode) + ); + rvclkhdr dma_buffer_c1cgc ( // @[el2_dma_ctrl.scala 439:32] + .io_l1clk(dma_buffer_c1cgc_io_l1clk), + .io_clk(dma_buffer_c1cgc_io_clk), + .io_en(dma_buffer_c1cgc_io_en), + .io_scan_mode(dma_buffer_c1cgc_io_scan_mode) + ); + rvclkhdr dma_free_cgc ( // @[el2_dma_ctrl.scala 445:28] + .io_l1clk(dma_free_cgc_io_l1clk), + .io_clk(dma_free_cgc_io_clk), + .io_en(dma_free_cgc_io_en), + .io_scan_mode(dma_free_cgc_io_scan_mode) + ); + rvclkhdr dma_bus_cgc ( // @[el2_dma_ctrl.scala 451:27] + .io_l1clk(dma_bus_cgc_io_l1clk), + .io_clk(dma_bus_cgc_io_clk), + .io_en(dma_bus_cgc_io_en), + .io_scan_mode(dma_bus_cgc_io_scan_mode) + ); + rvclkhdr rvclkhdr_10 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_10_io_l1clk), + .io_clk(rvclkhdr_10_io_clk), + .io_en(rvclkhdr_10_io_en), + .io_scan_mode(rvclkhdr_10_io_scan_mode) + ); + rvclkhdr rvclkhdr_11 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_11_io_l1clk), + .io_clk(rvclkhdr_11_io_clk), + .io_en(rvclkhdr_11_io_en), + .io_scan_mode(rvclkhdr_11_io_scan_mode) + ); + rvclkhdr rvclkhdr_12 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_12_io_l1clk), + .io_clk(rvclkhdr_12_io_clk), + .io_en(rvclkhdr_12_io_en), + .io_scan_mode(rvclkhdr_12_io_scan_mode) + ); + assign io_dma_dbg_ready = fifo_empty & dbg_dma_bubble_bus; // @[el2_dma_ctrl.scala 374:25] + assign io_dma_dbg_cmd_done = _T_1090 & _T_1091[0]; // @[el2_dma_ctrl.scala 375:25] + assign io_dma_dbg_cmd_fail = |_GEN_57; // @[el2_dma_ctrl.scala 377:25] + assign io_dma_dbg_rddata = _GEN_47[2] ? _GEN_52[63:32] : _GEN_52[31:0]; // @[el2_dma_ctrl.scala 376:25] + assign io_dma_dccm_req = _T_1117 & io_dccm_ready; // @[el2_dma_ctrl.scala 402:20] + assign io_dma_iccm_req = _T_1120 & io_iccm_ready; // @[el2_dma_ctrl.scala 403:20] + assign io_dma_mem_tag = RdPtr; // @[el2_dma_ctrl.scala 404:20] + assign io_dma_mem_addr = _T_1164 ? _T_1168 : dma_mem_addr_int; // @[el2_dma_ctrl.scala 407:20] + assign io_dma_mem_sz = _T_1176 ? 3'h2 : dma_mem_sz_int; // @[el2_dma_ctrl.scala 408:20] + assign io_dma_mem_write = _T_1179[0]; // @[el2_dma_ctrl.scala 410:20] + assign io_dma_mem_wdata = 3'h4 == RdPtr ? fifo_data_4 : _GEN_77; // @[el2_dma_ctrl.scala 411:20] + assign io_dma_dccm_stall_any = _T_1117 & _T_1118; // @[el2_dma_ctrl.scala 383:25] + assign io_dma_iccm_stall_any = _T_1120 & _T_1118; // @[el2_dma_ctrl.scala 384:25] + assign io_dma_pmu_dccm_read = io_dma_dccm_req & _T_166; // @[el2_dma_ctrl.scala 415:26] + assign io_dma_pmu_dccm_write = io_dma_dccm_req & io_dma_mem_write; // @[el2_dma_ctrl.scala 416:26] + assign io_dma_pmu_any_read = _T_165 & _T_166; // @[el2_dma_ctrl.scala 417:26] + assign io_dma_pmu_any_write = _T_165 & io_dma_mem_write; // @[el2_dma_ctrl.scala 418:26] + assign io_dma_axi_awready = ~_T_1223; // @[el2_dma_ctrl.scala 503:27] + assign io_dma_axi_wready = ~_T_1226; // @[el2_dma_ctrl.scala 504:27] + assign io_dma_axi_bvalid = axi_rsp_valid & axi_rsp_write; // @[el2_dma_ctrl.scala 540:27] + assign io_dma_axi_bresp = _GEN_57[0] ? 2'h2 : _T_1258; // @[el2_dma_ctrl.scala 541:33] + assign io_dma_axi_bid = 3'h4 == RspPtr ? fifo_tag_4 : _GEN_88; // @[el2_dma_ctrl.scala 542:33] + assign io_dma_axi_arready = ~_T_1229; // @[el2_dma_ctrl.scala 505:27] + assign io_dma_axi_rvalid = axi_rsp_valid & _T_1261; // @[el2_dma_ctrl.scala 544:27] + assign io_dma_axi_rid = 3'h4 == RspPtr ? fifo_tag_4 : _GEN_88; // @[el2_dma_ctrl.scala 548:37] + assign io_dma_axi_rdata = 3'h4 == RspPtr ? fifo_data_4 : _GEN_51; // @[el2_dma_ctrl.scala 546:35] + assign io_dma_axi_rresp = _GEN_57[0] ? 2'h2 : _T_1258; // @[el2_dma_ctrl.scala 545:33] + assign io_dma_axi_rlast = 1'h1; // @[el2_dma_ctrl.scala 547:33] + assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_io_en = fifo_cmd_en[0]; // @[el2_lib.scala 511:17] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_1_io_en = fifo_cmd_en[1]; // @[el2_lib.scala 511:17] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_2_io_en = fifo_cmd_en[2]; // @[el2_lib.scala 511:17] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_3_io_en = fifo_cmd_en[3]; // @[el2_lib.scala 511:17] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_4_io_en = fifo_cmd_en[4]; // @[el2_lib.scala 511:17] + assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_5_io_en = fifo_data_en[0]; // @[el2_lib.scala 511:17] + assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_6_io_en = fifo_data_en[1]; // @[el2_lib.scala 511:17] + assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_7_io_en = fifo_data_en[2]; // @[el2_lib.scala 511:17] + assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_8_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_8_io_en = fifo_data_en[3]; // @[el2_lib.scala 511:17] + assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_9_io_en = fifo_data_en[4]; // @[el2_lib.scala 511:17] + assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign dma_buffer_c1cgc_io_clk = clock; // @[el2_dma_ctrl.scala 442:33] + assign dma_buffer_c1cgc_io_en = _T_1193 | io_clk_override; // @[el2_dma_ctrl.scala 440:33] + assign dma_buffer_c1cgc_io_scan_mode = io_scan_mode; // @[el2_dma_ctrl.scala 441:33] + assign dma_free_cgc_io_clk = clock; // @[el2_dma_ctrl.scala 448:29] + assign dma_free_cgc_io_en = _T_1199 | io_clk_override; // @[el2_dma_ctrl.scala 446:29] + assign dma_free_cgc_io_scan_mode = io_scan_mode; // @[el2_dma_ctrl.scala 447:29] + assign dma_bus_cgc_io_clk = clock; // @[el2_dma_ctrl.scala 454:28] + assign dma_bus_cgc_io_en = io_dma_bus_clk_en; // @[el2_dma_ctrl.scala 452:28] + assign dma_bus_cgc_io_scan_mode = io_scan_mode; // @[el2_dma_ctrl.scala 453:28] + assign rvclkhdr_10_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_10_io_en = wrbuf_en & io_dma_bus_clk_en; // @[el2_lib.scala 511:17] + assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_11_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_11_io_en = wrbuf_data_en & io_dma_bus_clk_en; // @[el2_lib.scala 511:17] + assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_12_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_12_io_en = rdbuf_en & io_dma_bus_clk_en; // @[el2_lib.scala 511:17] + assign rvclkhdr_12_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + RdPtr = _RAND_0[2:0]; + _RAND_1 = {1{`RANDOM}}; + fifo_addr_4 = _RAND_1[31:0]; + _RAND_2 = {1{`RANDOM}}; + fifo_addr_3 = _RAND_2[31:0]; + _RAND_3 = {1{`RANDOM}}; + fifo_addr_2 = _RAND_3[31:0]; + _RAND_4 = {1{`RANDOM}}; + fifo_addr_1 = _RAND_4[31:0]; + _RAND_5 = {1{`RANDOM}}; + fifo_addr_0 = _RAND_5[31:0]; + _RAND_6 = {1{`RANDOM}}; + wrbuf_vld = _RAND_6[0:0]; + _RAND_7 = {1{`RANDOM}}; + wrbuf_data_vld = _RAND_7[0:0]; + _RAND_8 = {1{`RANDOM}}; + rdbuf_vld = _RAND_8[0:0]; + _RAND_9 = {1{`RANDOM}}; + axi_mstr_priority = _RAND_9[0:0]; + _RAND_10 = {1{`RANDOM}}; + wrbuf_addr = _RAND_10[31:0]; + _RAND_11 = {1{`RANDOM}}; + rdbuf_addr = _RAND_11[31:0]; + _RAND_12 = {1{`RANDOM}}; + wrbuf_byteen = _RAND_12[7:0]; + _RAND_13 = {1{`RANDOM}}; + wrbuf_sz = _RAND_13[2:0]; + _RAND_14 = {1{`RANDOM}}; + rdbuf_sz = _RAND_14[2:0]; + _RAND_15 = {1{`RANDOM}}; + fifo_full = _RAND_15[0:0]; + _RAND_16 = {1{`RANDOM}}; + dbg_dma_bubble_bus = _RAND_16[0:0]; + _RAND_17 = {1{`RANDOM}}; + WrPtr = _RAND_17[2:0]; + _RAND_18 = {1{`RANDOM}}; + _T_598 = _RAND_18[0:0]; + _RAND_19 = {1{`RANDOM}}; + _T_591 = _RAND_19[0:0]; + _RAND_20 = {1{`RANDOM}}; + _T_584 = _RAND_20[0:0]; + _RAND_21 = {1{`RANDOM}}; + _T_577 = _RAND_21[0:0]; + _RAND_22 = {1{`RANDOM}}; + _T_570 = _RAND_22[0:0]; + _RAND_23 = {1{`RANDOM}}; + _T_760 = _RAND_23[0:0]; + _RAND_24 = {1{`RANDOM}}; + _T_753 = _RAND_24[0:0]; + _RAND_25 = {1{`RANDOM}}; + _T_746 = _RAND_25[0:0]; + _RAND_26 = {1{`RANDOM}}; + _T_739 = _RAND_26[0:0]; + _RAND_27 = {1{`RANDOM}}; + _T_732 = _RAND_27[0:0]; + _RAND_28 = {1{`RANDOM}}; + _T_886 = _RAND_28[0:0]; + _RAND_29 = {1{`RANDOM}}; + _T_884 = _RAND_29[0:0]; + _RAND_30 = {1{`RANDOM}}; + _T_882 = _RAND_30[0:0]; + _RAND_31 = {1{`RANDOM}}; + _T_880 = _RAND_31[0:0]; + _RAND_32 = {1{`RANDOM}}; + _T_878 = _RAND_32[0:0]; + _RAND_33 = {1{`RANDOM}}; + fifo_sz_4 = _RAND_33[2:0]; + _RAND_34 = {1{`RANDOM}}; + fifo_sz_3 = _RAND_34[2:0]; + _RAND_35 = {1{`RANDOM}}; + fifo_sz_2 = _RAND_35[2:0]; + _RAND_36 = {1{`RANDOM}}; + fifo_sz_1 = _RAND_36[2:0]; + _RAND_37 = {1{`RANDOM}}; + fifo_sz_0 = _RAND_37[2:0]; + _RAND_38 = {1{`RANDOM}}; + fifo_byteen_4 = _RAND_38[7:0]; + _RAND_39 = {1{`RANDOM}}; + fifo_byteen_3 = _RAND_39[7:0]; + _RAND_40 = {1{`RANDOM}}; + fifo_byteen_2 = _RAND_40[7:0]; + _RAND_41 = {1{`RANDOM}}; + fifo_byteen_1 = _RAND_41[7:0]; + _RAND_42 = {1{`RANDOM}}; + fifo_byteen_0 = _RAND_42[7:0]; + _RAND_43 = {1{`RANDOM}}; + fifo_error_0 = _RAND_43[1:0]; + _RAND_44 = {1{`RANDOM}}; + fifo_error_1 = _RAND_44[1:0]; + _RAND_45 = {1{`RANDOM}}; + fifo_error_2 = _RAND_45[1:0]; + _RAND_46 = {1{`RANDOM}}; + fifo_error_3 = _RAND_46[1:0]; + _RAND_47 = {1{`RANDOM}}; + fifo_error_4 = _RAND_47[1:0]; + _RAND_48 = {1{`RANDOM}}; + RspPtr = _RAND_48[2:0]; + _RAND_49 = {2{`RANDOM}}; + wrbuf_data = _RAND_49[63:0]; + _RAND_50 = {1{`RANDOM}}; + _T_721 = _RAND_50[0:0]; + _RAND_51 = {1{`RANDOM}}; + _T_714 = _RAND_51[0:0]; + _RAND_52 = {1{`RANDOM}}; + _T_707 = _RAND_52[0:0]; + _RAND_53 = {1{`RANDOM}}; + _T_700 = _RAND_53[0:0]; + _RAND_54 = {1{`RANDOM}}; + _T_693 = _RAND_54[0:0]; + _RAND_55 = {1{`RANDOM}}; + _T_799 = _RAND_55[0:0]; + _RAND_56 = {1{`RANDOM}}; + _T_792 = _RAND_56[0:0]; + _RAND_57 = {1{`RANDOM}}; + _T_785 = _RAND_57[0:0]; + _RAND_58 = {1{`RANDOM}}; + _T_778 = _RAND_58[0:0]; + _RAND_59 = {1{`RANDOM}}; + _T_771 = _RAND_59[0:0]; + _RAND_60 = {1{`RANDOM}}; + _T_850 = _RAND_60[0:0]; + _RAND_61 = {1{`RANDOM}}; + _T_852 = _RAND_61[0:0]; + _RAND_62 = {1{`RANDOM}}; + _T_854 = _RAND_62[0:0]; + _RAND_63 = {1{`RANDOM}}; + _T_856 = _RAND_63[0:0]; + _RAND_64 = {1{`RANDOM}}; + _T_858 = _RAND_64[0:0]; + _RAND_65 = {2{`RANDOM}}; + fifo_data_0 = _RAND_65[63:0]; + _RAND_66 = {2{`RANDOM}}; + fifo_data_1 = _RAND_66[63:0]; + _RAND_67 = {2{`RANDOM}}; + fifo_data_2 = _RAND_67[63:0]; + _RAND_68 = {2{`RANDOM}}; + fifo_data_3 = _RAND_68[63:0]; + _RAND_69 = {2{`RANDOM}}; + fifo_data_4 = _RAND_69[63:0]; + _RAND_70 = {1{`RANDOM}}; + fifo_tag_0 = _RAND_70[0:0]; + _RAND_71 = {1{`RANDOM}}; + wrbuf_tag = _RAND_71[0:0]; + _RAND_72 = {1{`RANDOM}}; + rdbuf_tag = _RAND_72[0:0]; + _RAND_73 = {1{`RANDOM}}; + fifo_tag_1 = _RAND_73[0:0]; + _RAND_74 = {1{`RANDOM}}; + fifo_tag_2 = _RAND_74[0:0]; + _RAND_75 = {1{`RANDOM}}; + fifo_tag_3 = _RAND_75[0:0]; + _RAND_76 = {1{`RANDOM}}; + fifo_tag_4 = _RAND_76[0:0]; + _RAND_77 = {1{`RANDOM}}; + dma_nack_count = _RAND_77[2:0]; + _RAND_78 = {1{`RANDOM}}; + dma_dbg_cmd_done_q = _RAND_78[0:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + RdPtr = 3'h0; + end + if (reset) begin + fifo_addr_4 = 32'h0; + end + if (reset) begin + fifo_addr_3 = 32'h0; + end + if (reset) begin + fifo_addr_2 = 32'h0; + end + if (reset) begin + fifo_addr_1 = 32'h0; + end + if (reset) begin + fifo_addr_0 = 32'h0; + end + if (reset) begin + wrbuf_vld = 1'h0; + end + if (reset) begin + wrbuf_data_vld = 1'h0; + end + if (reset) begin + rdbuf_vld = 1'h0; + end + if (reset) begin + axi_mstr_priority = 1'h0; + end + if (reset) begin + wrbuf_addr = 32'h0; + end + if (reset) begin + rdbuf_addr = 32'h0; + end + if (reset) begin + wrbuf_byteen = 8'h0; + end + if (reset) begin + wrbuf_sz = 3'h0; + end + if (reset) begin + rdbuf_sz = 3'h0; + end + if (reset) begin + fifo_full = 1'h0; + end + if (reset) begin + dbg_dma_bubble_bus = 1'h0; + end + if (reset) begin + WrPtr = 3'h0; + end + if (reset) begin + _T_598 = 1'h0; + end + if (reset) begin + _T_591 = 1'h0; + end + if (reset) begin + _T_584 = 1'h0; + end + if (reset) begin + _T_577 = 1'h0; + end + if (reset) begin + _T_570 = 1'h0; + end + if (reset) begin + _T_760 = 1'h0; + end + if (reset) begin + _T_753 = 1'h0; + end + if (reset) begin + _T_746 = 1'h0; + end + if (reset) begin + _T_739 = 1'h0; + end + if (reset) begin + _T_732 = 1'h0; + end + if (reset) begin + _T_886 = 1'h0; + end + if (reset) begin + _T_884 = 1'h0; + end + if (reset) begin + _T_882 = 1'h0; + end + if (reset) begin + _T_880 = 1'h0; + end + if (reset) begin + _T_878 = 1'h0; + end + if (reset) begin + fifo_sz_4 = 3'h0; + end + if (reset) begin + fifo_sz_3 = 3'h0; + end + if (reset) begin + fifo_sz_2 = 3'h0; + end + if (reset) begin + fifo_sz_1 = 3'h0; + end + if (reset) begin + fifo_sz_0 = 3'h0; + end + if (reset) begin + fifo_byteen_4 = 8'h0; + end + if (reset) begin + fifo_byteen_3 = 8'h0; + end + if (reset) begin + fifo_byteen_2 = 8'h0; + end + if (reset) begin + fifo_byteen_1 = 8'h0; + end + if (reset) begin + fifo_byteen_0 = 8'h0; + end + if (reset) begin + fifo_error_0 = 2'h0; + end + if (reset) begin + fifo_error_1 = 2'h0; + end + if (reset) begin + fifo_error_2 = 2'h0; + end + if (reset) begin + fifo_error_3 = 2'h0; + end + if (reset) begin + fifo_error_4 = 2'h0; + end + if (reset) begin + RspPtr = 3'h0; + end + if (reset) begin + wrbuf_data = 64'h0; + end + if (reset) begin + _T_721 = 1'h0; + end + if (reset) begin + _T_714 = 1'h0; + end + if (reset) begin + _T_707 = 1'h0; + end + if (reset) begin + _T_700 = 1'h0; + end + if (reset) begin + _T_693 = 1'h0; + end + if (reset) begin + _T_799 = 1'h0; + end + if (reset) begin + _T_792 = 1'h0; + end + if (reset) begin + _T_785 = 1'h0; + end + if (reset) begin + _T_778 = 1'h0; + end + if (reset) begin + _T_771 = 1'h0; + end + if (reset) begin + _T_850 = 1'h0; + end + if (reset) begin + _T_852 = 1'h0; + end + if (reset) begin + _T_854 = 1'h0; + end + if (reset) begin + _T_856 = 1'h0; + end + if (reset) begin + _T_858 = 1'h0; + end + if (reset) begin + fifo_data_0 = 64'h0; + end + if (reset) begin + fifo_data_1 = 64'h0; + end + if (reset) begin + fifo_data_2 = 64'h0; + end + if (reset) begin + fifo_data_3 = 64'h0; + end + if (reset) begin + fifo_data_4 = 64'h0; + end + if (reset) begin + fifo_tag_0 = 1'h0; + end + if (reset) begin + wrbuf_tag = 1'h0; + end + if (reset) begin + rdbuf_tag = 1'h0; + end + if (reset) begin + fifo_tag_1 = 1'h0; + end + if (reset) begin + fifo_tag_2 = 1'h0; + end + if (reset) begin + fifo_tag_3 = 1'h0; + end + if (reset) begin + fifo_tag_4 = 1'h0; + end + if (reset) begin + dma_nack_count = 3'h0; + end + if (reset) begin + dma_dbg_cmd_done_q = 1'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge dma_free_clk or posedge reset) begin + if (reset) begin + RdPtr <= 3'h0; + end else if (RdPtrEn) begin + if (_T_936) begin + RdPtr <= 3'h0; + end else begin + RdPtr <= _T_939; + end + end + end + always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + if (reset) begin + fifo_addr_4 <= 32'h0; + end else if (io_dbg_cmd_valid) begin + fifo_addr_4 <= io_dbg_cmd_addr; + end else if (axi_mstr_sel) begin + fifo_addr_4 <= wrbuf_addr; + end else begin + fifo_addr_4 <= rdbuf_addr; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + fifo_addr_3 <= 32'h0; + end else if (io_dbg_cmd_valid) begin + fifo_addr_3 <= io_dbg_cmd_addr; + end else if (axi_mstr_sel) begin + fifo_addr_3 <= wrbuf_addr; + end else begin + fifo_addr_3 <= rdbuf_addr; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + fifo_addr_2 <= 32'h0; + end else if (io_dbg_cmd_valid) begin + fifo_addr_2 <= io_dbg_cmd_addr; + end else if (axi_mstr_sel) begin + fifo_addr_2 <= wrbuf_addr; + end else begin + fifo_addr_2 <= rdbuf_addr; + end + end + always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin + if (reset) begin + fifo_addr_1 <= 32'h0; + end else if (io_dbg_cmd_valid) begin + fifo_addr_1 <= io_dbg_cmd_addr; + end else if (axi_mstr_sel) begin + fifo_addr_1 <= wrbuf_addr; + end else begin + fifo_addr_1 <= rdbuf_addr; + end + end + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin + if (reset) begin + fifo_addr_0 <= 32'h0; + end else if (io_dbg_cmd_valid) begin + fifo_addr_0 <= io_dbg_cmd_addr; + end else begin + fifo_addr_0 <= bus_cmd_addr; + end + end + always @(posedge dma_bus_clk or posedge reset) begin + if (reset) begin + wrbuf_vld <= 1'h0; + end else begin + wrbuf_vld <= _T_1204 & _T_1205; + end + end + always @(posedge dma_bus_clk or posedge reset) begin + if (reset) begin + wrbuf_data_vld <= 1'h0; + end else begin + wrbuf_data_vld <= _T_1208 & _T_1209; + end + end + always @(posedge dma_bus_clk or posedge reset) begin + if (reset) begin + rdbuf_vld <= 1'h0; + end else begin + rdbuf_vld <= _T_1217 & _T_1218; + end + end + always @(posedge dma_bus_clk or posedge reset) begin + if (reset) begin + axi_mstr_priority <= 1'h0; + end else if (axi_mstr_prty_en) begin + axi_mstr_priority <= axi_mstr_prty_in; + end + end + always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin + if (reset) begin + wrbuf_addr <= 32'h0; + end else begin + wrbuf_addr <= io_dma_axi_awaddr; + end + end + always @(posedge rvclkhdr_12_io_l1clk or posedge reset) begin + if (reset) begin + rdbuf_addr <= 32'h0; + end else begin + rdbuf_addr <= io_dma_axi_araddr; + end + end + always @(posedge dma_bus_clk or posedge reset) begin + if (reset) begin + wrbuf_byteen <= 8'h0; + end else if (wrbuf_data_en) begin + wrbuf_byteen <= io_dma_axi_wstrb; + end + end + always @(posedge dma_bus_clk or posedge reset) begin + if (reset) begin + wrbuf_sz <= 3'h0; + end else if (wrbuf_en) begin + wrbuf_sz <= io_dma_axi_awsize; + end + end + always @(posedge dma_bus_clk or posedge reset) begin + if (reset) begin + rdbuf_sz <= 3'h0; + end else if (rdbuf_en) begin + rdbuf_sz <= io_dma_axi_arsize; + end + end + always @(posedge dma_bus_clk or posedge reset) begin + if (reset) begin + fifo_full <= 1'h0; + end else begin + fifo_full <= num_fifo_vld_tmp2 >= 4'h5; + end + end + always @(posedge dma_bus_clk or posedge reset) begin + if (reset) begin + dbg_dma_bubble_bus <= 1'h0; + end else begin + dbg_dma_bubble_bus <= io_dbg_dma_bubble; + end + end + always @(posedge dma_free_clk or posedge reset) begin + if (reset) begin + WrPtr <= 3'h0; + end else if (WrPtrEn) begin + if (_T_931) begin + WrPtr <= 3'h0; + end else begin + WrPtr <= _T_934; + end + end + end + always @(posedge dma_free_clk or posedge reset) begin + if (reset) begin + _T_598 <= 1'h0; + end else begin + _T_598 <= _T_594 & _T_596; + end + end + always @(posedge dma_free_clk or posedge reset) begin + if (reset) begin + _T_591 <= 1'h0; + end else begin + _T_591 <= _T_587 & _T_589; + end + end + always @(posedge dma_free_clk or posedge reset) begin + if (reset) begin + _T_584 <= 1'h0; + end else begin + _T_584 <= _T_580 & _T_582; + end + end + always @(posedge dma_free_clk or posedge reset) begin + if (reset) begin + _T_577 <= 1'h0; + end else begin + _T_577 <= _T_573 & _T_575; + end + end + always @(posedge dma_free_clk or posedge reset) begin + if (reset) begin + _T_570 <= 1'h0; + end else begin + _T_570 <= _T_566 & _T_568; + end + end + always @(posedge dma_free_clk or posedge reset) begin + if (reset) begin + _T_760 <= 1'h0; + end else begin + _T_760 <= _T_399 & _T_596; + end + end + always @(posedge dma_free_clk or posedge reset) begin + if (reset) begin + _T_753 <= 1'h0; + end else begin + _T_753 <= _T_395 & _T_589; + end + end + always @(posedge dma_free_clk or posedge reset) begin + if (reset) begin + _T_746 <= 1'h0; + end else begin + _T_746 <= _T_391 & _T_582; + end + end + always @(posedge dma_free_clk or posedge reset) begin + if (reset) begin + _T_739 <= 1'h0; + end else begin + _T_739 <= _T_387 & _T_575; + end + end + always @(posedge dma_free_clk or posedge reset) begin + if (reset) begin + _T_732 <= 1'h0; + end else begin + _T_732 <= _T_383 & _T_568; + end + end + always @(posedge dma_buffer_c1_clk or posedge reset) begin + if (reset) begin + _T_886 <= 1'h0; + end else if (fifo_cmd_en[4]) begin + _T_886 <= io_dbg_cmd_valid; + end + end + always @(posedge dma_buffer_c1_clk or posedge reset) begin + if (reset) begin + _T_884 <= 1'h0; + end else if (fifo_cmd_en[3]) begin + _T_884 <= io_dbg_cmd_valid; + end + end + always @(posedge dma_buffer_c1_clk or posedge reset) begin + if (reset) begin + _T_882 <= 1'h0; + end else if (fifo_cmd_en[2]) begin + _T_882 <= io_dbg_cmd_valid; + end + end + always @(posedge dma_buffer_c1_clk or posedge reset) begin + if (reset) begin + _T_880 <= 1'h0; + end else if (fifo_cmd_en[1]) begin + _T_880 <= io_dbg_cmd_valid; + end + end + always @(posedge dma_buffer_c1_clk or posedge reset) begin + if (reset) begin + _T_878 <= 1'h0; + end else if (fifo_cmd_en[0]) begin + _T_878 <= io_dbg_cmd_valid; + end + end + always @(posedge dma_buffer_c1_clk or posedge reset) begin + if (reset) begin + fifo_sz_4 <= 3'h0; + end else if (fifo_cmd_en[4]) begin + if (io_dbg_cmd_valid) begin + fifo_sz_4 <= _T_23; + end else if (axi_mstr_sel) begin + fifo_sz_4 <= wrbuf_sz; + end else begin + fifo_sz_4 <= rdbuf_sz; + end + end + end + always @(posedge dma_buffer_c1_clk or posedge reset) begin + if (reset) begin + fifo_sz_3 <= 3'h0; + end else if (fifo_cmd_en[3]) begin + if (io_dbg_cmd_valid) begin + fifo_sz_3 <= _T_23; + end else if (axi_mstr_sel) begin + fifo_sz_3 <= wrbuf_sz; + end else begin + fifo_sz_3 <= rdbuf_sz; + end + end + end + always @(posedge dma_buffer_c1_clk or posedge reset) begin + if (reset) begin + fifo_sz_2 <= 3'h0; + end else if (fifo_cmd_en[2]) begin + if (io_dbg_cmd_valid) begin + fifo_sz_2 <= _T_23; + end else if (axi_mstr_sel) begin + fifo_sz_2 <= wrbuf_sz; + end else begin + fifo_sz_2 <= rdbuf_sz; + end + end + end + always @(posedge dma_buffer_c1_clk or posedge reset) begin + if (reset) begin + fifo_sz_1 <= 3'h0; + end else if (fifo_cmd_en[1]) begin + if (io_dbg_cmd_valid) begin + fifo_sz_1 <= _T_23; + end else if (axi_mstr_sel) begin + fifo_sz_1 <= wrbuf_sz; + end else begin + fifo_sz_1 <= rdbuf_sz; + end + end + end + always @(posedge dma_buffer_c1_clk or posedge reset) begin + if (reset) begin + fifo_sz_0 <= 3'h0; + end else if (fifo_cmd_en[0]) begin + fifo_sz_0 <= fifo_sz_in; + end + end + always @(posedge dma_buffer_c1_clk or posedge reset) begin + if (reset) begin + fifo_byteen_4 <= 8'h0; + end else if (fifo_cmd_en[4]) begin + fifo_byteen_4 <= fifo_byteen_in; + end + end + always @(posedge dma_buffer_c1_clk or posedge reset) begin + if (reset) begin + fifo_byteen_3 <= 8'h0; + end else if (fifo_cmd_en[3]) begin + fifo_byteen_3 <= fifo_byteen_in; + end + end + always @(posedge dma_buffer_c1_clk or posedge reset) begin + if (reset) begin + fifo_byteen_2 <= 8'h0; + end else if (fifo_cmd_en[2]) begin + fifo_byteen_2 <= fifo_byteen_in; + end + end + always @(posedge dma_buffer_c1_clk or posedge reset) begin + if (reset) begin + fifo_byteen_1 <= 8'h0; + end else if (fifo_cmd_en[1]) begin + fifo_byteen_1 <= fifo_byteen_in; + end + end + always @(posedge dma_buffer_c1_clk or posedge reset) begin + if (reset) begin + fifo_byteen_0 <= 8'h0; + end else if (fifo_cmd_en[0]) begin + fifo_byteen_0 <= fifo_byteen_in; + end + end + always @(posedge dma_free_clk or posedge reset) begin + if (reset) begin + fifo_error_0 <= 2'h0; + end else begin + fifo_error_0 <= _T_605 & _T_609; + end + end + always @(posedge dma_free_clk or posedge reset) begin + if (reset) begin + fifo_error_1 <= 2'h0; + end else begin + fifo_error_1 <= _T_614 & _T_618; + end + end + always @(posedge dma_free_clk or posedge reset) begin + if (reset) begin + fifo_error_2 <= 2'h0; + end else begin + fifo_error_2 <= _T_623 & _T_627; + end + end + always @(posedge dma_free_clk or posedge reset) begin + if (reset) begin + fifo_error_3 <= 2'h0; + end else begin + fifo_error_3 <= _T_632 & _T_636; + end + end + always @(posedge dma_free_clk or posedge reset) begin + if (reset) begin + fifo_error_4 <= 2'h0; + end else begin + fifo_error_4 <= _T_641 & _T_645; + end + end + always @(posedge dma_free_clk or posedge reset) begin + if (reset) begin + RspPtr <= 3'h0; + end else if (RspPtrEn) begin + if (_T_941) begin + RspPtr <= 3'h0; + end else begin + RspPtr <= _T_944; + end + end + end + always @(posedge rvclkhdr_11_io_l1clk or posedge reset) begin + if (reset) begin + wrbuf_data <= 64'h0; + end else begin + wrbuf_data <= io_dma_axi_wdata; + end + end + always @(posedge dma_free_clk or posedge reset) begin + if (reset) begin + _T_721 <= 1'h0; + end else begin + _T_721 <= _T_717 & _T_596; + end + end + always @(posedge dma_free_clk or posedge reset) begin + if (reset) begin + _T_714 <= 1'h0; + end else begin + _T_714 <= _T_710 & _T_589; + end + end + always @(posedge dma_free_clk or posedge reset) begin + if (reset) begin + _T_707 <= 1'h0; + end else begin + _T_707 <= _T_703 & _T_582; + end + end + always @(posedge dma_free_clk or posedge reset) begin + if (reset) begin + _T_700 <= 1'h0; + end else begin + _T_700 <= _T_696 & _T_575; + end + end + always @(posedge dma_free_clk or posedge reset) begin + if (reset) begin + _T_693 <= 1'h0; + end else begin + _T_693 <= _T_689 & _T_568; + end + end + always @(posedge dma_free_clk or posedge reset) begin + if (reset) begin + _T_799 <= 1'h0; + end else begin + _T_799 <= _T_795 & _T_596; + end + end + always @(posedge dma_free_clk or posedge reset) begin + if (reset) begin + _T_792 <= 1'h0; + end else begin + _T_792 <= _T_788 & _T_589; + end + end + always @(posedge dma_free_clk or posedge reset) begin + if (reset) begin + _T_785 <= 1'h0; + end else begin + _T_785 <= _T_781 & _T_582; + end + end + always @(posedge dma_free_clk or posedge reset) begin + if (reset) begin + _T_778 <= 1'h0; + end else begin + _T_778 <= _T_774 & _T_575; + end + end + always @(posedge dma_free_clk or posedge reset) begin + if (reset) begin + _T_771 <= 1'h0; + end else begin + _T_771 <= _T_767 & _T_568; + end + end + always @(posedge dma_buffer_c1_clk or posedge reset) begin + if (reset) begin + _T_850 <= 1'h0; + end else if (fifo_cmd_en[0]) begin + if (io_dbg_cmd_valid) begin + _T_850 <= io_dbg_cmd_write; + end else if (_T_1241) begin + _T_850 <= axi_mstr_priority; + end else begin + _T_850 <= _T_1240; + end + end + end + always @(posedge dma_buffer_c1_clk or posedge reset) begin + if (reset) begin + _T_852 <= 1'h0; + end else if (fifo_cmd_en[1]) begin + if (io_dbg_cmd_valid) begin + _T_852 <= io_dbg_cmd_write; + end else if (_T_1241) begin + _T_852 <= axi_mstr_priority; + end else begin + _T_852 <= _T_1240; + end + end + end + always @(posedge dma_buffer_c1_clk or posedge reset) begin + if (reset) begin + _T_854 <= 1'h0; + end else if (fifo_cmd_en[2]) begin + if (io_dbg_cmd_valid) begin + _T_854 <= io_dbg_cmd_write; + end else if (_T_1241) begin + _T_854 <= axi_mstr_priority; + end else begin + _T_854 <= _T_1240; + end + end + end + always @(posedge dma_buffer_c1_clk or posedge reset) begin + if (reset) begin + _T_856 <= 1'h0; + end else if (fifo_cmd_en[3]) begin + if (io_dbg_cmd_valid) begin + _T_856 <= io_dbg_cmd_write; + end else if (_T_1241) begin + _T_856 <= axi_mstr_priority; + end else begin + _T_856 <= _T_1240; + end + end + end + always @(posedge dma_buffer_c1_clk or posedge reset) begin + if (reset) begin + _T_858 <= 1'h0; + end else if (fifo_cmd_en[4]) begin + _T_858 <= fifo_write_in; + end + end + always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin + if (reset) begin + fifo_data_0 <= 64'h0; + end else if (_T_491) begin + fifo_data_0 <= _T_493; + end else if (_T_84) begin + fifo_data_0 <= io_dccm_dma_rdata; + end else if (_T_87) begin + fifo_data_0 <= io_iccm_dma_rdata; + end else if (io_dbg_cmd_valid) begin + fifo_data_0 <= _T_498; + end else begin + fifo_data_0 <= wrbuf_data; + end + end + always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin + if (reset) begin + fifo_data_1 <= 64'h0; + end else if (_T_506) begin + fifo_data_1 <= _T_508; + end else if (_T_102) begin + fifo_data_1 <= io_dccm_dma_rdata; + end else if (_T_105) begin + fifo_data_1 <= io_iccm_dma_rdata; + end else if (io_dbg_cmd_valid) begin + fifo_data_1 <= _T_498; + end else begin + fifo_data_1 <= wrbuf_data; + end + end + always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin + if (reset) begin + fifo_data_2 <= 64'h0; + end else if (_T_521) begin + fifo_data_2 <= _T_523; + end else if (_T_120) begin + fifo_data_2 <= io_dccm_dma_rdata; + end else if (_T_123) begin + fifo_data_2 <= io_iccm_dma_rdata; + end else if (io_dbg_cmd_valid) begin + fifo_data_2 <= _T_498; + end else begin + fifo_data_2 <= wrbuf_data; + end + end + always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin + if (reset) begin + fifo_data_3 <= 64'h0; + end else if (_T_536) begin + fifo_data_3 <= _T_538; + end else if (_T_138) begin + fifo_data_3 <= io_dccm_dma_rdata; + end else if (_T_141) begin + fifo_data_3 <= io_iccm_dma_rdata; + end else if (io_dbg_cmd_valid) begin + fifo_data_3 <= _T_498; + end else begin + fifo_data_3 <= wrbuf_data; + end + end + always @(posedge rvclkhdr_9_io_l1clk or posedge reset) begin + if (reset) begin + fifo_data_4 <= 64'h0; + end else if (_T_551) begin + fifo_data_4 <= _T_553; + end else if (_T_156) begin + fifo_data_4 <= io_dccm_dma_rdata; + end else if (_T_159) begin + fifo_data_4 <= io_iccm_dma_rdata; + end else begin + fifo_data_4 <= _T_500; + end + end + always @(posedge dma_buffer_c1_clk or posedge reset) begin + if (reset) begin + fifo_tag_0 <= 1'h0; + end else if (fifo_cmd_en[0]) begin + if (axi_mstr_sel) begin + fifo_tag_0 <= wrbuf_tag; + end else begin + fifo_tag_0 <= rdbuf_tag; + end + end + end + always @(posedge dma_bus_clk or posedge reset) begin + if (reset) begin + wrbuf_tag <= 1'h0; + end else if (wrbuf_en) begin + wrbuf_tag <= io_dma_axi_awid; + end + end + always @(posedge dma_bus_clk or posedge reset) begin + if (reset) begin + rdbuf_tag <= 1'h0; + end else if (rdbuf_en) begin + rdbuf_tag <= io_dma_axi_arid; + end + end + always @(posedge dma_buffer_c1_clk or posedge reset) begin + if (reset) begin + fifo_tag_1 <= 1'h0; + end else if (fifo_cmd_en[1]) begin + if (axi_mstr_sel) begin + fifo_tag_1 <= wrbuf_tag; + end else begin + fifo_tag_1 <= rdbuf_tag; + end + end + end + always @(posedge dma_buffer_c1_clk or posedge reset) begin + if (reset) begin + fifo_tag_2 <= 1'h0; + end else if (fifo_cmd_en[2]) begin + if (axi_mstr_sel) begin + fifo_tag_2 <= wrbuf_tag; + end else begin + fifo_tag_2 <= rdbuf_tag; + end + end + end + always @(posedge dma_buffer_c1_clk or posedge reset) begin + if (reset) begin + fifo_tag_3 <= 1'h0; + end else if (fifo_cmd_en[3]) begin + if (axi_mstr_sel) begin + fifo_tag_3 <= wrbuf_tag; + end else begin + fifo_tag_3 <= rdbuf_tag; + end + end + end + always @(posedge dma_buffer_c1_clk or posedge reset) begin + if (reset) begin + fifo_tag_4 <= 1'h0; + end else if (fifo_cmd_en[4]) begin + fifo_tag_4 <= bus_cmd_tag; + end + end + always @(posedge dma_free_clk or posedge reset) begin + if (reset) begin + dma_nack_count <= 3'h0; + end else if (dma_mem_req) begin + if (_T_1118) begin + dma_nack_count <= _T_1131; + end else if (_T_1135) begin + dma_nack_count <= _T_1138; + end else begin + dma_nack_count <= 3'h0; + end + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + dma_dbg_cmd_done_q <= 1'h0; + end else begin + dma_dbg_cmd_done_q <= io_dma_dbg_cmd_done; + end + end +endmodule diff --git a/el2_ifu.fir b/el2_ifu.fir index 3217e507..664fe950 100644 --- a/el2_ifu.fir +++ b/el2_ifu.fir @@ -6187,9 +6187,9 @@ circuit el2_ifu : node _T_2554 = and(_T_2552, _T_2553) @[el2_ifu_mem_ctl.scala 563:59] node _T_2555 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 563:77] node bus_cmd_req_in = and(_T_2554, _T_2555) @[el2_ifu_mem_ctl.scala 563:75] - reg _T_2556 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 564:49] - _T_2556 <= bus_cmd_req_in @[el2_ifu_mem_ctl.scala 564:49] - bus_cmd_sent <= _T_2556 @[el2_ifu_mem_ctl.scala 564:16] + reg _T_2556 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 564:53] + _T_2556 <= bus_cmd_req_in @[el2_ifu_mem_ctl.scala 564:53] + bus_cmd_req_hold <= _T_2556 @[el2_ifu_mem_ctl.scala 564:20] io.ifu_axi_arvalid <= ifu_bus_cmd_valid @[el2_ifu_mem_ctl.scala 566:22] node _T_2557 = bits(ifu_bus_cmd_valid, 0, 0) @[Bitwise.scala 72:15] node _T_2558 = mux(_T_2557, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] diff --git a/el2_ifu.v b/el2_ifu.v index 21edbc0a..18b7d440 100644 --- a/el2_ifu.v +++ b/el2_ifu.v @@ -570,13 +570,13 @@ module el2_ifu_mem_ctl( reg [31:0] _RAND_447; reg [31:0] _RAND_448; reg [31:0] _RAND_449; - reg [63:0] _RAND_450; - reg [31:0] _RAND_451; + reg [31:0] _RAND_450; + reg [63:0] _RAND_451; reg [31:0] _RAND_452; reg [31:0] _RAND_453; reg [31:0] _RAND_454; - reg [63:0] _RAND_455; - reg [31:0] _RAND_456; + reg [31:0] _RAND_455; + reg [63:0] _RAND_456; reg [31:0] _RAND_457; reg [31:0] _RAND_458; reg [31:0] _RAND_459; @@ -590,6 +590,7 @@ module el2_ifu_mem_ctl( reg [31:0] _RAND_467; reg [31:0] _RAND_468; reg [31:0] _RAND_469; + reg [31:0] _RAND_470; `endif // RANDOMIZE_REG_INIT wire rvclkhdr_io_l1clk; // @[el2_lib.scala 483:22] wire rvclkhdr_io_clk; // @[el2_lib.scala 483:22] @@ -3407,8 +3408,10 @@ module el2_ifu_mem_ctl( wire _GEN_41 = _T_2481 ? _T_2499 : _GEN_37; // @[Conditional.scala 39:67] wire _GEN_43 = _T_2481 | _GEN_39; // @[Conditional.scala 39:67] wire err_stop_state_en = _T_2476 ? _T_2480 : _GEN_41; // @[Conditional.scala 40:58] + reg bus_cmd_req_hold; // @[el2_ifu_mem_ctl.scala 564:53] + wire _T_2541 = ic_act_miss_f | bus_cmd_req_hold; // @[el2_ifu_mem_ctl.scala 560:45] reg ifu_bus_cmd_valid; // @[el2_ifu_mem_ctl.scala 561:55] - wire _T_2542 = ic_act_miss_f | ifu_bus_cmd_valid; // @[el2_ifu_mem_ctl.scala 560:64] + wire _T_2542 = _T_2541 | ifu_bus_cmd_valid; // @[el2_ifu_mem_ctl.scala 560:64] wire _T_2544 = _T_2542 & _T_2573; // @[el2_ifu_mem_ctl.scala 560:85] reg [2:0] bus_cmd_beat_count; // @[Reg.scala 27:20] wire _T_2546 = bus_cmd_beat_count == 3'h7; // @[el2_ifu_mem_ctl.scala 560:133] @@ -3420,6 +3423,8 @@ module el2_ifu_mem_ctl( wire _T_2567 = io_ifu_axi_arvalid & ifu_bus_arready; // @[el2_ifu_mem_ctl.scala 595:35] wire _T_2568 = _T_2567 & miss_pending; // @[el2_ifu_mem_ctl.scala 595:53] wire bus_cmd_sent = _T_2568 & _T_2573; // @[el2_ifu_mem_ctl.scala 595:68] + wire _T_2553 = ~bus_cmd_sent; // @[el2_ifu_mem_ctl.scala 563:61] + wire _T_2554 = _T_2541 & _T_2553; // @[el2_ifu_mem_ctl.scala 563:59] wire [2:0] _T_2558 = ifu_bus_cmd_valid ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] wire [31:0] _T_2560 = {miss_addr,bus_rd_addr_count,3'h0}; // @[Cat.scala 29:58] wire [31:0] _T_2562 = ifu_bus_cmd_valid ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] @@ -6899,55 +6904,57 @@ initial begin _RAND_444 = {1{`RANDOM}}; dma_sb_err_state_ff = _RAND_444[0:0]; _RAND_445 = {1{`RANDOM}}; - ifu_bus_cmd_valid = _RAND_445[0:0]; + bus_cmd_req_hold = _RAND_445[0:0]; _RAND_446 = {1{`RANDOM}}; - bus_cmd_beat_count = _RAND_446[2:0]; + ifu_bus_cmd_valid = _RAND_446[0:0]; _RAND_447 = {1{`RANDOM}}; - ifu_bus_arready_unq_ff = _RAND_447[0:0]; + bus_cmd_beat_count = _RAND_447[2:0]; _RAND_448 = {1{`RANDOM}}; - ifu_bus_arvalid_ff = _RAND_448[0:0]; + ifu_bus_arready_unq_ff = _RAND_448[0:0]; _RAND_449 = {1{`RANDOM}}; - ifc_dma_access_ok_prev = _RAND_449[0:0]; - _RAND_450 = {2{`RANDOM}}; - iccm_ecc_corr_data_ff = _RAND_450[38:0]; - _RAND_451 = {1{`RANDOM}}; - dma_mem_addr_ff = _RAND_451[1:0]; + ifu_bus_arvalid_ff = _RAND_449[0:0]; + _RAND_450 = {1{`RANDOM}}; + ifc_dma_access_ok_prev = _RAND_450[0:0]; + _RAND_451 = {2{`RANDOM}}; + iccm_ecc_corr_data_ff = _RAND_451[38:0]; _RAND_452 = {1{`RANDOM}}; - dma_mem_tag_ff = _RAND_452[2:0]; + dma_mem_addr_ff = _RAND_452[1:0]; _RAND_453 = {1{`RANDOM}}; - iccm_dma_rtag_temp = _RAND_453[2:0]; + dma_mem_tag_ff = _RAND_453[2:0]; _RAND_454 = {1{`RANDOM}}; - iccm_dma_rvalid_temp = _RAND_454[0:0]; - _RAND_455 = {2{`RANDOM}}; - iccm_dma_rdata_temp = _RAND_455[63:0]; - _RAND_456 = {1{`RANDOM}}; - iccm_ecc_corr_index_ff = _RAND_456[13:0]; + iccm_dma_rtag_temp = _RAND_454[2:0]; + _RAND_455 = {1{`RANDOM}}; + iccm_dma_rvalid_temp = _RAND_455[0:0]; + _RAND_456 = {2{`RANDOM}}; + iccm_dma_rdata_temp = _RAND_456[63:0]; _RAND_457 = {1{`RANDOM}}; - iccm_rd_ecc_single_err_ff = _RAND_457[0:0]; + iccm_ecc_corr_index_ff = _RAND_457[13:0]; _RAND_458 = {1{`RANDOM}}; - iccm_rw_addr_f = _RAND_458[13:0]; + iccm_rd_ecc_single_err_ff = _RAND_458[0:0]; _RAND_459 = {1{`RANDOM}}; - ifu_status_wr_addr_ff = _RAND_459[6:0]; + iccm_rw_addr_f = _RAND_459[13:0]; _RAND_460 = {1{`RANDOM}}; - way_status_wr_en_ff = _RAND_460[0:0]; + ifu_status_wr_addr_ff = _RAND_460[6:0]; _RAND_461 = {1{`RANDOM}}; - way_status_new_ff = _RAND_461[0:0]; + way_status_wr_en_ff = _RAND_461[0:0]; _RAND_462 = {1{`RANDOM}}; - ifu_tag_wren_ff = _RAND_462[1:0]; + way_status_new_ff = _RAND_462[0:0]; _RAND_463 = {1{`RANDOM}}; - ic_valid_ff = _RAND_463[0:0]; + ifu_tag_wren_ff = _RAND_463[1:0]; _RAND_464 = {1{`RANDOM}}; - _T_9747 = _RAND_464[0:0]; + ic_valid_ff = _RAND_464[0:0]; _RAND_465 = {1{`RANDOM}}; - _T_9748 = _RAND_465[0:0]; + _T_9747 = _RAND_465[0:0]; _RAND_466 = {1{`RANDOM}}; - _T_9749 = _RAND_466[0:0]; + _T_9748 = _RAND_466[0:0]; _RAND_467 = {1{`RANDOM}}; - _T_9753 = _RAND_467[0:0]; + _T_9749 = _RAND_467[0:0]; _RAND_468 = {1{`RANDOM}}; - _T_9754 = _RAND_468[0:0]; + _T_9753 = _RAND_468[0:0]; _RAND_469 = {1{`RANDOM}}; - _T_9775 = _RAND_469[0:0]; + _T_9754 = _RAND_469[0:0]; + _RAND_470 = {1{`RANDOM}}; + _T_9775 = _RAND_470[0:0]; `endif // RANDOMIZE_REG_INIT if (reset) begin flush_final_f = 1'h0; @@ -8278,6 +8285,9 @@ initial begin if (reset) begin dma_sb_err_state_ff = 1'h0; end + if (reset) begin + bus_cmd_req_hold = 1'h0; + end if (reset) begin ifu_bus_cmd_valid = 1'h0; end @@ -11616,6 +11626,13 @@ end // initial dma_sb_err_state_ff <= perr_state == 3'h4; end end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + bus_cmd_req_hold <= 1'h0; + end else begin + bus_cmd_req_hold <= _T_2554 & _T_2573; + end + end always @(posedge rvclkhdr_69_io_l1clk or posedge reset) begin if (reset) begin ifu_bus_cmd_valid <= 1'h0; diff --git a/el2_ifu_aln_ctl.fir b/el2_ifu_aln_ctl.fir index 04f9b018..cedffb10 100644 --- a/el2_ifu_aln_ctl.fir +++ b/el2_ifu_aln_ctl.fir @@ -2284,7 +2284,7 @@ circuit el2_ifu_aln_ctl : module el2_ifu_aln_ctl : input clock : Clock input reset : AsyncReset - output io : {flip scan_mode : UInt<1>, flip active_clk : Clock, flip ifu_async_error_start : UInt<1>, flip iccm_rd_ecc_double_err : UInt<1>, flip ic_access_fault_f : UInt<1>, flip ic_access_fault_type_f : UInt<2>, flip ifu_bp_fghr_f : UInt<8>, flip ifu_bp_btb_target_f : UInt<31>, flip ifu_bp_poffset_f : UInt<12>, flip ifu_bp_hist0_f : UInt<2>, flip ifu_bp_hist1_f : UInt<2>, flip ifu_bp_pc4_f : UInt<2>, flip ifu_bp_way_f : UInt<2>, flip ifu_bp_valid_f : UInt<2>, flip ifu_bp_ret_f : UInt<2>, flip exu_flush_final : UInt<1>, flip dec_i0_decode_d : UInt<1>, flip ifu_fetch_data_f : UInt<32>, flip ifu_fetch_val : UInt<2>, flip ifu_fetch_pc : UInt<31>, ifu_i0_valid : UInt<1>, ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_icaf_f1 : UInt<1>, ifu_i0_dbecc : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<31>, ifu_i0_pc4 : UInt<1>, ifu_fb_consume1 : UInt<1>, ifu_fb_consume2 : UInt<1>, ifu_i0_bp_index : UInt<8>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, ifu_pmu_instr_aligned : UInt<1>, ifu_i0_cinst : UInt<16>, i0_brp : {valid : UInt<1>, bits : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}} + output io : {flip scan_mode : UInt<1>, flip active_clk : Clock, flip ifu_async_error_start : UInt<1>, flip iccm_rd_ecc_double_err : UInt<1>, flip ic_access_fault_f : UInt<1>, flip ic_access_fault_type_f : UInt<2>, flip ifu_bp_fghr_f : UInt<8>, flip ifu_bp_btb_target_f : UInt<31>, flip ifu_bp_poffset_f : UInt<12>, flip ifu_bp_hist0_f : UInt<2>, flip ifu_bp_hist1_f : UInt<2>, flip ifu_bp_pc4_f : UInt<2>, flip ifu_bp_way_f : UInt<2>, flip ifu_bp_valid_f : UInt<2>, flip ifu_bp_ret_f : UInt<2>, flip exu_flush_final : UInt<1>, flip dec_i0_decode_d : UInt<1>, flip ifu_fetch_data_f : UInt<32>, flip ifu_fetch_val : UInt<2>, flip ifu_fetch_pc : UInt<31>, ifu_i0_valid : UInt<1>, ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_icaf_f1 : UInt<1>, ifu_i0_dbecc : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<31>, ifu_i0_pc4 : UInt<1>, ifu_fb_consume1 : UInt<1>, ifu_fb_consume2 : UInt<1>, ifu_i0_bp_index : UInt<8>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, ifu_pmu_instr_aligned : UInt<1>, ifu_i0_cinst : UInt<16>, i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}} io.ifu_i0_valid <= UInt<1>("h00") @[el2_ifu_aln_ctl.scala 47:19] io.ifu_i0_icaf <= UInt<1>("h00") @[el2_ifu_aln_ctl.scala 48:18] diff --git a/el2_ifu_ifc_ctl.anno.json b/el2_ifu_ifc_ctl.anno.json new file mode 100644 index 00000000..cdd55407 --- /dev/null +++ b/el2_ifu_ifc_ctl.anno.json @@ -0,0 +1,127 @@ +[ + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_dma_access_ok", + "sources":[ + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_final", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_iccm_access_bf", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_req_bf", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_fb_consume2", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_fb_consume1", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_dec_tlu_flush_noredir_wb", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_addr_bf", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ic_write_stall", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_req_bf_raw", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ic_dma_active", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_bp_btb_target_f", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_path_final", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_addr_f", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ic_hit_f", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_bp_hit_taken_f", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_req_f" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_pmu_fetch_stall", + "sources":[ + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_req_bf_raw", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ic_dma_active", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_final", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_fb_consume2", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_fb_consume1" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_addr_bf", + "sources":[ + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_bp_btb_target_f", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_path_final", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_addr_f", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ic_hit_f", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_final", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_bp_hit_taken_f", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_req_f" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_iccm_access_bf", + "sources":[ + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_addr_bf", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_bp_btb_target_f", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_path_final", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_addr_f", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ic_hit_f", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_final", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_bp_hit_taken_f", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_req_f" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_req_bf", + "sources":[ + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_dec_tlu_flush_noredir_wb", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ic_write_stall", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_req_bf_raw", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ic_dma_active", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_fb_consume2", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_fb_consume1", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_final", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_req_f", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ic_hit_f" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_region_acc_fault_bf", + "sources":[ + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_addr_bf", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_bp_btb_target_f", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_path_final", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_addr_f", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ic_hit_f", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_final", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_bp_hit_taken_f", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_req_f" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_uncacheable_bf", + "sources":[ + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_dec_tlu_mrac_ff", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_addr_bf", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_bp_btb_target_f", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_path_final", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_addr_f", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ic_hit_f", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_exu_flush_final", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifu_bp_hit_taken_f", + "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_req_f" + ] + }, + { + "class":"firrtl.EmitCircuitAnnotation", + "emitter":"firrtl.VerilogEmitter" + }, + { + "class":"firrtl.transforms.BlackBoxResourceAnno", + "target":"el2_ifu_ifc_ctl.gated_latch", + "resourceId":"/vsrc/gated_latch.v" + }, + { + "class":"firrtl.options.TargetDirAnnotation", + "directory":"." + }, + { + "class":"firrtl.options.OutputAnnotationFileAnnotation", + "file":"el2_ifu_ifc_ctl" + }, + { + "class":"firrtl.transforms.BlackBoxTargetDirAnno", + "targetDir":"." + } +] \ No newline at end of file diff --git a/el2_ifu_ifc_ctl.fir b/el2_ifu_ifc_ctl.fir new file mode 100644 index 00000000..92c63955 --- /dev/null +++ b/el2_ifu_ifc_ctl.fir @@ -0,0 +1,295 @@ +;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 +circuit el2_ifu_ifc_ctl : + extmodule gated_latch : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + module el2_ifu_ifc_ctl : + input clock : Clock + input reset : AsyncReset + output io : {flip free_clk : Clock, flip active_clk : Clock, flip scan_mode : UInt<1>, flip ic_hit_f : UInt<1>, flip ifu_ic_mb_empty : UInt<1>, flip ifu_fb_consume1 : UInt<1>, flip ifu_fb_consume2 : UInt<1>, flip dec_tlu_flush_noredir_wb : UInt<1>, flip exu_flush_final : UInt<1>, flip exu_flush_path_final : UInt<31>, flip ifu_bp_hit_taken_f : UInt<1>, flip ifu_bp_btb_target_f : UInt<31>, flip ic_dma_active : UInt<1>, flip ic_write_stall : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, ifc_fetch_addr_f : UInt<31>, ifc_fetch_addr_bf : UInt<31>, ifc_fetch_req_f : UInt<1>, ifu_pmu_fetch_stall : UInt<1>, ifc_fetch_uncacheable_bf : UInt<1>, ifc_fetch_req_bf : UInt<1>, ifc_fetch_req_bf_raw : UInt<1>, ifc_iccm_access_bf : UInt<1>, ifc_region_acc_fault_bf : UInt<1>, ifc_dma_access_ok : UInt<1>} + + wire fetch_addr_bf : UInt<31> + fetch_addr_bf <= UInt<1>("h00") + wire fetch_addr_next_0 : UInt<1> + fetch_addr_next_0 <= UInt<1>("h00") + wire fetch_addr_next : UInt<31> + fetch_addr_next <= UInt<1>("h00") + wire fb_write_ns : UInt<4> + fb_write_ns <= UInt<1>("h00") + wire fb_write_f : UInt<4> + fb_write_f <= UInt<1>("h00") + wire fb_full_f_ns : UInt<1> + fb_full_f_ns <= UInt<1>("h00") + wire fb_right : UInt<1> + fb_right <= UInt<1>("h00") + wire fb_right2 : UInt<1> + fb_right2 <= UInt<1>("h00") + wire fb_left : UInt<1> + fb_left <= UInt<1>("h00") + wire wfm : UInt<1> + wfm <= UInt<1>("h00") + wire idle : UInt<1> + idle <= UInt<1>("h00") + wire miss_f : UInt<1> + miss_f <= UInt<1>("h00") + wire miss_a : UInt<1> + miss_a <= UInt<1>("h00") + wire flush_fb : UInt<1> + flush_fb <= UInt<1>("h00") + wire mb_empty_mod : UInt<1> + mb_empty_mod <= UInt<1>("h00") + wire goto_idle : UInt<1> + goto_idle <= UInt<1>("h00") + wire leave_idle : UInt<1> + leave_idle <= UInt<1>("h00") + wire fetch_bf_en : UInt<1> + fetch_bf_en <= UInt<1>("h00") + wire line_wrap : UInt<1> + line_wrap <= UInt<1>("h00") + wire state : UInt<2> + state <= UInt<1>("h00") + wire dma_iccm_stall_any_f : UInt<1> + dma_iccm_stall_any_f <= UInt<1>("h00") + node dma_stall = or(io.ic_dma_active, dma_iccm_stall_any_f) @[el2_ifu_ifc_ctl.scala 62:36] + reg _T : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 63:58] + _T <= io.dma_iccm_stall_any @[el2_ifu_ifc_ctl.scala 63:58] + dma_iccm_stall_any_f <= _T @[el2_ifu_ifc_ctl.scala 63:24] + reg _T_1 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 65:44] + _T_1 <= miss_f @[el2_ifu_ifc_ctl.scala 65:44] + miss_a <= _T_1 @[el2_ifu_ifc_ctl.scala 65:10] + node _T_2 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 67:26] + node _T_3 = eq(io.ifc_fetch_req_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 67:49] + node _T_4 = eq(io.ic_hit_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 67:71] + node _T_5 = or(_T_3, _T_4) @[el2_ifu_ifc_ctl.scala 67:69] + node sel_last_addr_bf = and(_T_2, _T_5) @[el2_ifu_ifc_ctl.scala 67:46] + node _T_6 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 68:26] + node _T_7 = and(_T_6, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 68:46] + node _T_8 = and(_T_7, io.ifu_bp_hit_taken_f) @[el2_ifu_ifc_ctl.scala 68:67] + node sel_btb_addr_bf = and(_T_8, io.ic_hit_f) @[el2_ifu_ifc_ctl.scala 68:92] + node _T_9 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 69:26] + node _T_10 = and(_T_9, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 69:46] + node _T_11 = eq(io.ifu_bp_hit_taken_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 69:69] + node _T_12 = and(_T_10, _T_11) @[el2_ifu_ifc_ctl.scala 69:67] + node sel_next_addr_bf = and(_T_12, io.ic_hit_f) @[el2_ifu_ifc_ctl.scala 69:92] + node _T_13 = bits(io.exu_flush_final, 0, 0) @[el2_ifu_ifc_ctl.scala 72:56] + node _T_14 = bits(sel_last_addr_bf, 0, 0) @[el2_ifu_ifc_ctl.scala 73:22] + node _T_15 = bits(sel_btb_addr_bf, 0, 0) @[el2_ifu_ifc_ctl.scala 74:21] + node _T_16 = bits(sel_next_addr_bf, 0, 0) @[el2_ifu_ifc_ctl.scala 75:22] + node _T_17 = mux(_T_13, io.exu_flush_path_final, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_18 = mux(_T_14, io.ifc_fetch_addr_f, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_19 = mux(_T_15, io.ifu_bp_btb_target_f, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_20 = mux(_T_16, fetch_addr_next, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_21 = or(_T_17, _T_18) @[Mux.scala 27:72] + node _T_22 = or(_T_21, _T_19) @[Mux.scala 27:72] + node _T_23 = or(_T_22, _T_20) @[Mux.scala 27:72] + wire _T_24 : UInt<31> @[Mux.scala 27:72] + _T_24 <= _T_23 @[Mux.scala 27:72] + io.ifc_fetch_addr_bf <= _T_24 @[el2_ifu_ifc_ctl.scala 72:24] + node _T_25 = bits(io.ifc_fetch_addr_f, 30, 1) @[el2_ifu_ifc_ctl.scala 77:42] + node _T_26 = add(_T_25, UInt<1>("h01")) @[el2_ifu_ifc_ctl.scala 77:48] + node address_upper = tail(_T_26, 1) @[el2_ifu_ifc_ctl.scala 77:48] + node _T_27 = bits(address_upper, 4, 4) @[el2_ifu_ifc_ctl.scala 78:39] + node _T_28 = bits(io.ifc_fetch_addr_f, 5, 5) @[el2_ifu_ifc_ctl.scala 78:84] + node _T_29 = xor(_T_27, _T_28) @[el2_ifu_ifc_ctl.scala 78:63] + node _T_30 = eq(_T_29, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 78:24] + node _T_31 = bits(io.ifc_fetch_addr_f, 0, 0) @[el2_ifu_ifc_ctl.scala 78:130] + node _T_32 = and(_T_30, _T_31) @[el2_ifu_ifc_ctl.scala 78:109] + fetch_addr_next_0 <= _T_32 @[el2_ifu_ifc_ctl.scala 78:21] + node _T_33 = cat(address_upper, fetch_addr_next_0) @[Cat.scala 29:58] + fetch_addr_next <= _T_33 @[el2_ifu_ifc_ctl.scala 80:19] + node _T_34 = not(idle) @[el2_ifu_ifc_ctl.scala 82:30] + io.ifc_fetch_req_bf_raw <= _T_34 @[el2_ifu_ifc_ctl.scala 82:27] + node _T_35 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctl.scala 84:91] + node _T_36 = eq(_T_35, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 84:70] + node _T_37 = and(fb_full_f_ns, _T_36) @[el2_ifu_ifc_ctl.scala 84:68] + node _T_38 = eq(_T_37, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 84:53] + node _T_39 = and(io.ifc_fetch_req_bf_raw, _T_38) @[el2_ifu_ifc_ctl.scala 84:51] + node _T_40 = eq(dma_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 85:5] + node _T_41 = and(_T_39, _T_40) @[el2_ifu_ifc_ctl.scala 84:114] + node _T_42 = eq(io.ic_write_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 85:18] + node _T_43 = and(_T_41, _T_42) @[el2_ifu_ifc_ctl.scala 85:16] + node _T_44 = eq(io.dec_tlu_flush_noredir_wb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 85:39] + node _T_45 = and(_T_43, _T_44) @[el2_ifu_ifc_ctl.scala 85:37] + io.ifc_fetch_req_bf <= _T_45 @[el2_ifu_ifc_ctl.scala 84:23] + node _T_46 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 87:37] + fetch_bf_en <= _T_46 @[el2_ifu_ifc_ctl.scala 87:15] + node _T_47 = eq(io.ic_hit_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 89:34] + node _T_48 = and(io.ifc_fetch_req_f, _T_47) @[el2_ifu_ifc_ctl.scala 89:32] + node _T_49 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 89:49] + node _T_50 = and(_T_48, _T_49) @[el2_ifu_ifc_ctl.scala 89:47] + miss_f <= _T_50 @[el2_ifu_ifc_ctl.scala 89:10] + node _T_51 = or(io.ifu_ic_mb_empty, io.exu_flush_final) @[el2_ifu_ifc_ctl.scala 91:39] + node _T_52 = eq(dma_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 91:63] + node _T_53 = and(_T_51, _T_52) @[el2_ifu_ifc_ctl.scala 91:61] + node _T_54 = eq(miss_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 91:76] + node _T_55 = and(_T_53, _T_54) @[el2_ifu_ifc_ctl.scala 91:74] + node _T_56 = eq(miss_a, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 91:86] + node _T_57 = and(_T_55, _T_56) @[el2_ifu_ifc_ctl.scala 91:84] + mb_empty_mod <= _T_57 @[el2_ifu_ifc_ctl.scala 91:16] + node _T_58 = and(io.exu_flush_final, io.dec_tlu_flush_noredir_wb) @[el2_ifu_ifc_ctl.scala 93:35] + goto_idle <= _T_58 @[el2_ifu_ifc_ctl.scala 93:13] + node _T_59 = eq(io.dec_tlu_flush_noredir_wb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 95:38] + node _T_60 = and(io.exu_flush_final, _T_59) @[el2_ifu_ifc_ctl.scala 95:36] + node _T_61 = and(_T_60, idle) @[el2_ifu_ifc_ctl.scala 95:67] + leave_idle <= _T_61 @[el2_ifu_ifc_ctl.scala 95:14] + node _T_62 = bits(state, 1, 1) @[el2_ifu_ifc_ctl.scala 97:29] + node _T_63 = eq(_T_62, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 97:23] + node _T_64 = bits(state, 0, 0) @[el2_ifu_ifc_ctl.scala 97:40] + node _T_65 = and(_T_63, _T_64) @[el2_ifu_ifc_ctl.scala 97:33] + node _T_66 = and(_T_65, miss_f) @[el2_ifu_ifc_ctl.scala 97:44] + node _T_67 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 97:55] + node _T_68 = and(_T_66, _T_67) @[el2_ifu_ifc_ctl.scala 97:53] + node _T_69 = bits(state, 1, 1) @[el2_ifu_ifc_ctl.scala 98:11] + node _T_70 = eq(mb_empty_mod, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 98:17] + node _T_71 = and(_T_69, _T_70) @[el2_ifu_ifc_ctl.scala 98:15] + node _T_72 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 98:33] + node _T_73 = and(_T_71, _T_72) @[el2_ifu_ifc_ctl.scala 98:31] + node next_state_1 = or(_T_68, _T_73) @[el2_ifu_ifc_ctl.scala 97:67] + node _T_74 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 100:23] + node _T_75 = and(_T_74, leave_idle) @[el2_ifu_ifc_ctl.scala 100:34] + node _T_76 = bits(state, 0, 0) @[el2_ifu_ifc_ctl.scala 100:56] + node _T_77 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 100:62] + node _T_78 = and(_T_76, _T_77) @[el2_ifu_ifc_ctl.scala 100:60] + node next_state_0 = or(_T_75, _T_78) @[el2_ifu_ifc_ctl.scala 100:48] + node _T_79 = cat(next_state_1, next_state_0) @[Cat.scala 29:58] + reg _T_80 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 102:45] + _T_80 <= _T_79 @[el2_ifu_ifc_ctl.scala 102:45] + state <= _T_80 @[el2_ifu_ifc_ctl.scala 102:9] + flush_fb <= io.exu_flush_final @[el2_ifu_ifc_ctl.scala 104:12] + node _T_81 = eq(io.ifu_fb_consume2, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 106:38] + node _T_82 = and(io.ifu_fb_consume1, _T_81) @[el2_ifu_ifc_ctl.scala 106:36] + node _T_83 = eq(io.ifc_fetch_req_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 106:61] + node _T_84 = or(_T_83, miss_f) @[el2_ifu_ifc_ctl.scala 106:81] + node _T_85 = and(_T_82, _T_84) @[el2_ifu_ifc_ctl.scala 106:58] + node _T_86 = and(io.ifu_fb_consume2, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 107:25] + node _T_87 = or(_T_85, _T_86) @[el2_ifu_ifc_ctl.scala 106:92] + fb_right <= _T_87 @[el2_ifu_ifc_ctl.scala 106:12] + node _T_88 = not(io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 109:39] + node _T_89 = or(_T_88, miss_f) @[el2_ifu_ifc_ctl.scala 109:59] + node _T_90 = and(io.ifu_fb_consume2, _T_89) @[el2_ifu_ifc_ctl.scala 109:36] + fb_right2 <= _T_90 @[el2_ifu_ifc_ctl.scala 109:13] + node _T_91 = or(io.ifu_fb_consume1, io.ifu_fb_consume2) @[el2_ifu_ifc_ctl.scala 110:56] + node _T_92 = eq(_T_91, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 110:35] + node _T_93 = and(io.ifc_fetch_req_f, _T_92) @[el2_ifu_ifc_ctl.scala 110:33] + node _T_94 = eq(miss_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 110:80] + node _T_95 = and(_T_93, _T_94) @[el2_ifu_ifc_ctl.scala 110:78] + fb_left <= _T_95 @[el2_ifu_ifc_ctl.scala 110:11] + node _T_96 = bits(flush_fb, 0, 0) @[el2_ifu_ifc_ctl.scala 112:37] + node _T_97 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 113:6] + node _T_98 = and(_T_97, fb_right) @[el2_ifu_ifc_ctl.scala 113:16] + node _T_99 = bits(_T_98, 0, 0) @[el2_ifu_ifc_ctl.scala 113:28] + node _T_100 = bits(fb_write_f, 3, 1) @[el2_ifu_ifc_ctl.scala 113:62] + node _T_101 = cat(UInt<1>("h00"), _T_100) @[Cat.scala 29:58] + node _T_102 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 114:6] + node _T_103 = and(_T_102, fb_right2) @[el2_ifu_ifc_ctl.scala 114:16] + node _T_104 = bits(_T_103, 0, 0) @[el2_ifu_ifc_ctl.scala 114:29] + node _T_105 = bits(fb_write_f, 3, 2) @[el2_ifu_ifc_ctl.scala 114:63] + node _T_106 = cat(UInt<2>("h00"), _T_105) @[Cat.scala 29:58] + node _T_107 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 115:6] + node _T_108 = and(_T_107, fb_left) @[el2_ifu_ifc_ctl.scala 115:16] + node _T_109 = bits(_T_108, 0, 0) @[el2_ifu_ifc_ctl.scala 115:27] + node _T_110 = bits(fb_write_f, 2, 0) @[el2_ifu_ifc_ctl.scala 115:51] + node _T_111 = cat(_T_110, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_112 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 116:6] + node _T_113 = eq(fb_right, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 116:18] + node _T_114 = and(_T_112, _T_113) @[el2_ifu_ifc_ctl.scala 116:16] + node _T_115 = eq(fb_right2, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 116:30] + node _T_116 = and(_T_114, _T_115) @[el2_ifu_ifc_ctl.scala 116:28] + node _T_117 = eq(fb_left, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 116:43] + node _T_118 = and(_T_116, _T_117) @[el2_ifu_ifc_ctl.scala 116:41] + node _T_119 = bits(_T_118, 0, 0) @[el2_ifu_ifc_ctl.scala 116:53] + node _T_120 = bits(fb_write_f, 3, 0) @[el2_ifu_ifc_ctl.scala 116:73] + node _T_121 = mux(_T_96, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_122 = mux(_T_99, _T_101, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_123 = mux(_T_104, _T_106, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_124 = mux(_T_109, _T_111, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_125 = mux(_T_119, _T_120, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_126 = or(_T_121, _T_122) @[Mux.scala 27:72] + node _T_127 = or(_T_126, _T_123) @[Mux.scala 27:72] + node _T_128 = or(_T_127, _T_124) @[Mux.scala 27:72] + node _T_129 = or(_T_128, _T_125) @[Mux.scala 27:72] + wire _T_130 : UInt<4> @[Mux.scala 27:72] + _T_130 <= _T_129 @[Mux.scala 27:72] + fb_write_ns <= _T_130 @[el2_ifu_ifc_ctl.scala 112:15] + node _T_131 = eq(state, UInt<2>("h00")) @[el2_ifu_ifc_ctl.scala 119:17] + idle <= _T_131 @[el2_ifu_ifc_ctl.scala 119:8] + node _T_132 = eq(state, UInt<2>("h03")) @[el2_ifu_ifc_ctl.scala 120:16] + wfm <= _T_132 @[el2_ifu_ifc_ctl.scala 120:7] + node _T_133 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctl.scala 122:30] + fb_full_f_ns <= _T_133 @[el2_ifu_ifc_ctl.scala 122:16] + reg fb_full_f : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 123:52] + fb_full_f <= fb_full_f_ns @[el2_ifu_ifc_ctl.scala 123:52] + reg _T_134 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 124:50] + _T_134 <= fb_write_ns @[el2_ifu_ifc_ctl.scala 124:50] + fb_write_f <= _T_134 @[el2_ifu_ifc_ctl.scala 124:14] + node _T_135 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctl.scala 127:40] + node _T_136 = or(_T_135, io.exu_flush_final) @[el2_ifu_ifc_ctl.scala 127:61] + node _T_137 = eq(_T_136, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 127:19] + node _T_138 = and(fb_full_f, _T_137) @[el2_ifu_ifc_ctl.scala 127:17] + node _T_139 = or(_T_138, dma_stall) @[el2_ifu_ifc_ctl.scala 127:84] + node _T_140 = and(io.ifc_fetch_req_bf_raw, _T_139) @[el2_ifu_ifc_ctl.scala 126:60] + node _T_141 = or(wfm, _T_140) @[el2_ifu_ifc_ctl.scala 126:33] + io.ifu_pmu_fetch_stall <= _T_141 @[el2_ifu_ifc_ctl.scala 126:26] + node _T_142 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_143 = bits(_T_142, 31, 28) @[el2_lib.scala 224:25] + node iccm_acc_in_region_bf = eq(_T_143, UInt<4>("h0e")) @[el2_lib.scala 224:47] + node _T_144 = bits(_T_142, 31, 16) @[el2_lib.scala 227:14] + node iccm_acc_in_range_bf = eq(_T_144, UInt<16>("h0ee00")) @[el2_lib.scala 227:29] + io.ifc_iccm_access_bf <= iccm_acc_in_range_bf @[el2_ifu_ifc_ctl.scala 132:25] + node _T_145 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 133:30] + node _T_146 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctl.scala 134:39] + node _T_147 = eq(_T_146, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 134:18] + node _T_148 = and(fb_full_f, _T_147) @[el2_ifu_ifc_ctl.scala 134:16] + node _T_149 = or(_T_145, _T_148) @[el2_ifu_ifc_ctl.scala 133:53] + node _T_150 = eq(io.ifc_fetch_req_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 135:13] + node _T_151 = and(wfm, _T_150) @[el2_ifu_ifc_ctl.scala 135:11] + node _T_152 = or(_T_149, _T_151) @[el2_ifu_ifc_ctl.scala 134:62] + node _T_153 = or(_T_152, idle) @[el2_ifu_ifc_ctl.scala 135:35] + node _T_154 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 135:46] + node _T_155 = and(_T_153, _T_154) @[el2_ifu_ifc_ctl.scala 135:44] + node _T_156 = or(_T_155, dma_iccm_stall_any_f) @[el2_ifu_ifc_ctl.scala 135:67] + io.ifc_dma_access_ok <= _T_156 @[el2_ifu_ifc_ctl.scala 133:24] + node _T_157 = eq(iccm_acc_in_range_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 137:33] + node _T_158 = and(_T_157, iccm_acc_in_region_bf) @[el2_ifu_ifc_ctl.scala 137:55] + io.ifc_region_acc_fault_bf <= _T_158 @[el2_ifu_ifc_ctl.scala 137:30] + node _T_159 = bits(io.ifc_fetch_addr_bf, 30, 27) @[el2_ifu_ifc_ctl.scala 138:78] + node _T_160 = cat(_T_159, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_161 = dshr(io.dec_tlu_mrac_ff, _T_160) @[el2_ifu_ifc_ctl.scala 138:53] + node _T_162 = bits(_T_161, 0, 0) @[el2_ifu_ifc_ctl.scala 138:53] + node _T_163 = not(_T_162) @[el2_ifu_ifc_ctl.scala 138:34] + io.ifc_fetch_uncacheable_bf <= _T_163 @[el2_ifu_ifc_ctl.scala 138:31] + reg _T_164 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 140:57] + _T_164 <= io.ifc_fetch_req_bf @[el2_ifu_ifc_ctl.scala 140:57] + io.ifc_fetch_req_f <= _T_164 @[el2_ifu_ifc_ctl.scala 140:22] + node _T_165 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 142:73] + inst rvclkhdr of rvclkhdr @[el2_lib.scala 508:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr.io.en <= _T_165 @[el2_lib.scala 511:17] + rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_166 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_166 <= io.ifc_fetch_addr_bf @[el2_lib.scala 514:16] + io.ifc_fetch_addr_f <= _T_166 @[el2_ifu_ifc_ctl.scala 142:23] + diff --git a/el2_ifu_ifc_ctl.v b/el2_ifu_ifc_ctl.v new file mode 100644 index 00000000..2b174c5b --- /dev/null +++ b/el2_ifu_ifc_ctl.v @@ -0,0 +1,327 @@ +module rvclkhdr( + output io_l1clk, + input io_clk, + input io_en, + input io_scan_mode +); + wire clkhdr_Q; // @[el2_lib.scala 474:26] + wire clkhdr_CK; // @[el2_lib.scala 474:26] + wire clkhdr_EN; // @[el2_lib.scala 474:26] + wire clkhdr_SE; // @[el2_lib.scala 474:26] + gated_latch clkhdr ( // @[el2_lib.scala 474:26] + .Q(clkhdr_Q), + .CK(clkhdr_CK), + .EN(clkhdr_EN), + .SE(clkhdr_SE) + ); + assign io_l1clk = clkhdr_Q; // @[el2_lib.scala 475:14] + assign clkhdr_CK = io_clk; // @[el2_lib.scala 476:18] + assign clkhdr_EN = io_en; // @[el2_lib.scala 477:18] + assign clkhdr_SE = io_scan_mode; // @[el2_lib.scala 478:18] +endmodule +module el2_ifu_ifc_ctl( + input clock, + input reset, + input io_free_clk, + input io_active_clk, + input io_scan_mode, + input io_ic_hit_f, + input io_ifu_ic_mb_empty, + input io_ifu_fb_consume1, + input io_ifu_fb_consume2, + input io_dec_tlu_flush_noredir_wb, + input io_exu_flush_final, + input [30:0] io_exu_flush_path_final, + input io_ifu_bp_hit_taken_f, + input [30:0] io_ifu_bp_btb_target_f, + input io_ic_dma_active, + input io_ic_write_stall, + input io_dma_iccm_stall_any, + input [31:0] io_dec_tlu_mrac_ff, + output [30:0] io_ifc_fetch_addr_f, + output [30:0] io_ifc_fetch_addr_bf, + output io_ifc_fetch_req_f, + output io_ifu_pmu_fetch_stall, + output io_ifc_fetch_uncacheable_bf, + output io_ifc_fetch_req_bf, + output io_ifc_fetch_req_bf_raw, + output io_ifc_iccm_access_bf, + output io_ifc_region_acc_fault_bf, + output io_ifc_dma_access_ok +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; +`endif // RANDOMIZE_REG_INIT + wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23] + reg dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctl.scala 63:58] + wire dma_stall = io_ic_dma_active | dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctl.scala 62:36] + reg miss_a; // @[el2_ifu_ifc_ctl.scala 65:44] + wire _T_2 = ~io_exu_flush_final; // @[el2_ifu_ifc_ctl.scala 67:26] + wire _T_3 = ~io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctl.scala 67:49] + wire _T_4 = ~io_ic_hit_f; // @[el2_ifu_ifc_ctl.scala 67:71] + wire _T_5 = _T_3 | _T_4; // @[el2_ifu_ifc_ctl.scala 67:69] + wire sel_last_addr_bf = _T_2 & _T_5; // @[el2_ifu_ifc_ctl.scala 67:46] + wire _T_7 = _T_2 & io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctl.scala 68:46] + wire _T_8 = _T_7 & io_ifu_bp_hit_taken_f; // @[el2_ifu_ifc_ctl.scala 68:67] + wire sel_btb_addr_bf = _T_8 & io_ic_hit_f; // @[el2_ifu_ifc_ctl.scala 68:92] + wire _T_11 = ~io_ifu_bp_hit_taken_f; // @[el2_ifu_ifc_ctl.scala 69:69] + wire _T_12 = _T_7 & _T_11; // @[el2_ifu_ifc_ctl.scala 69:67] + wire sel_next_addr_bf = _T_12 & io_ic_hit_f; // @[el2_ifu_ifc_ctl.scala 69:92] + wire [30:0] _T_17 = io_exu_flush_final ? io_exu_flush_path_final : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_18 = sel_last_addr_bf ? io_ifc_fetch_addr_f : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_19 = sel_btb_addr_bf ? io_ifu_bp_btb_target_f : 31'h0; // @[Mux.scala 27:72] + wire [29:0] address_upper = io_ifc_fetch_addr_f[30:1] + 30'h1; // @[el2_ifu_ifc_ctl.scala 77:48] + wire _T_29 = address_upper[4] ^ io_ifc_fetch_addr_f[5]; // @[el2_ifu_ifc_ctl.scala 78:63] + wire _T_30 = ~_T_29; // @[el2_ifu_ifc_ctl.scala 78:24] + wire fetch_addr_next_0 = _T_30 & io_ifc_fetch_addr_f[0]; // @[el2_ifu_ifc_ctl.scala 78:109] + wire [30:0] fetch_addr_next = {address_upper,fetch_addr_next_0}; // @[Cat.scala 29:58] + wire [30:0] _T_20 = sel_next_addr_bf ? fetch_addr_next : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_21 = _T_17 | _T_18; // @[Mux.scala 27:72] + wire [30:0] _T_22 = _T_21 | _T_19; // @[Mux.scala 27:72] + reg [1:0] state; // @[el2_ifu_ifc_ctl.scala 102:45] + wire idle = state == 2'h0; // @[el2_ifu_ifc_ctl.scala 119:17] + wire _T_35 = io_ifu_fb_consume2 | io_ifu_fb_consume1; // @[el2_ifu_ifc_ctl.scala 84:91] + wire _T_36 = ~_T_35; // @[el2_ifu_ifc_ctl.scala 84:70] + wire [3:0] _T_121 = io_exu_flush_final ? 4'h1 : 4'h0; // @[Mux.scala 27:72] + wire _T_81 = ~io_ifu_fb_consume2; // @[el2_ifu_ifc_ctl.scala 106:38] + wire _T_82 = io_ifu_fb_consume1 & _T_81; // @[el2_ifu_ifc_ctl.scala 106:36] + wire _T_48 = io_ifc_fetch_req_f & _T_4; // @[el2_ifu_ifc_ctl.scala 89:32] + wire miss_f = _T_48 & _T_2; // @[el2_ifu_ifc_ctl.scala 89:47] + wire _T_84 = _T_3 | miss_f; // @[el2_ifu_ifc_ctl.scala 106:81] + wire _T_85 = _T_82 & _T_84; // @[el2_ifu_ifc_ctl.scala 106:58] + wire _T_86 = io_ifu_fb_consume2 & io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctl.scala 107:25] + wire fb_right = _T_85 | _T_86; // @[el2_ifu_ifc_ctl.scala 106:92] + wire _T_98 = _T_2 & fb_right; // @[el2_ifu_ifc_ctl.scala 113:16] + reg [3:0] fb_write_f; // @[el2_ifu_ifc_ctl.scala 124:50] + wire [3:0] _T_101 = {1'h0,fb_write_f[3:1]}; // @[Cat.scala 29:58] + wire [3:0] _T_122 = _T_98 ? _T_101 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_126 = _T_121 | _T_122; // @[Mux.scala 27:72] + wire fb_right2 = io_ifu_fb_consume2 & _T_84; // @[el2_ifu_ifc_ctl.scala 109:36] + wire _T_103 = _T_2 & fb_right2; // @[el2_ifu_ifc_ctl.scala 114:16] + wire [3:0] _T_106 = {2'h0,fb_write_f[3:2]}; // @[Cat.scala 29:58] + wire [3:0] _T_123 = _T_103 ? _T_106 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_127 = _T_126 | _T_123; // @[Mux.scala 27:72] + wire _T_91 = io_ifu_fb_consume1 | io_ifu_fb_consume2; // @[el2_ifu_ifc_ctl.scala 110:56] + wire _T_92 = ~_T_91; // @[el2_ifu_ifc_ctl.scala 110:35] + wire _T_93 = io_ifc_fetch_req_f & _T_92; // @[el2_ifu_ifc_ctl.scala 110:33] + wire _T_94 = ~miss_f; // @[el2_ifu_ifc_ctl.scala 110:80] + wire fb_left = _T_93 & _T_94; // @[el2_ifu_ifc_ctl.scala 110:78] + wire _T_108 = _T_2 & fb_left; // @[el2_ifu_ifc_ctl.scala 115:16] + wire [3:0] _T_111 = {fb_write_f[2:0],1'h0}; // @[Cat.scala 29:58] + wire [3:0] _T_124 = _T_108 ? _T_111 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_128 = _T_127 | _T_124; // @[Mux.scala 27:72] + wire _T_113 = ~fb_right; // @[el2_ifu_ifc_ctl.scala 116:18] + wire _T_114 = _T_2 & _T_113; // @[el2_ifu_ifc_ctl.scala 116:16] + wire _T_115 = ~fb_right2; // @[el2_ifu_ifc_ctl.scala 116:30] + wire _T_116 = _T_114 & _T_115; // @[el2_ifu_ifc_ctl.scala 116:28] + wire _T_117 = ~fb_left; // @[el2_ifu_ifc_ctl.scala 116:43] + wire _T_118 = _T_116 & _T_117; // @[el2_ifu_ifc_ctl.scala 116:41] + wire [3:0] _T_125 = _T_118 ? fb_write_f : 4'h0; // @[Mux.scala 27:72] + wire [3:0] fb_write_ns = _T_128 | _T_125; // @[Mux.scala 27:72] + wire fb_full_f_ns = fb_write_ns[3]; // @[el2_ifu_ifc_ctl.scala 122:30] + wire _T_37 = fb_full_f_ns & _T_36; // @[el2_ifu_ifc_ctl.scala 84:68] + wire _T_38 = ~_T_37; // @[el2_ifu_ifc_ctl.scala 84:53] + wire _T_39 = io_ifc_fetch_req_bf_raw & _T_38; // @[el2_ifu_ifc_ctl.scala 84:51] + wire _T_40 = ~dma_stall; // @[el2_ifu_ifc_ctl.scala 85:5] + wire _T_41 = _T_39 & _T_40; // @[el2_ifu_ifc_ctl.scala 84:114] + wire _T_42 = ~io_ic_write_stall; // @[el2_ifu_ifc_ctl.scala 85:18] + wire _T_43 = _T_41 & _T_42; // @[el2_ifu_ifc_ctl.scala 85:16] + wire _T_44 = ~io_dec_tlu_flush_noredir_wb; // @[el2_ifu_ifc_ctl.scala 85:39] + wire _T_51 = io_ifu_ic_mb_empty | io_exu_flush_final; // @[el2_ifu_ifc_ctl.scala 91:39] + wire _T_53 = _T_51 & _T_40; // @[el2_ifu_ifc_ctl.scala 91:61] + wire _T_55 = _T_53 & _T_94; // @[el2_ifu_ifc_ctl.scala 91:74] + wire _T_56 = ~miss_a; // @[el2_ifu_ifc_ctl.scala 91:86] + wire mb_empty_mod = _T_55 & _T_56; // @[el2_ifu_ifc_ctl.scala 91:84] + wire goto_idle = io_exu_flush_final & io_dec_tlu_flush_noredir_wb; // @[el2_ifu_ifc_ctl.scala 93:35] + wire _T_60 = io_exu_flush_final & _T_44; // @[el2_ifu_ifc_ctl.scala 95:36] + wire leave_idle = _T_60 & idle; // @[el2_ifu_ifc_ctl.scala 95:67] + wire _T_63 = ~state[1]; // @[el2_ifu_ifc_ctl.scala 97:23] + wire _T_65 = _T_63 & state[0]; // @[el2_ifu_ifc_ctl.scala 97:33] + wire _T_66 = _T_65 & miss_f; // @[el2_ifu_ifc_ctl.scala 97:44] + wire _T_67 = ~goto_idle; // @[el2_ifu_ifc_ctl.scala 97:55] + wire _T_68 = _T_66 & _T_67; // @[el2_ifu_ifc_ctl.scala 97:53] + wire _T_70 = ~mb_empty_mod; // @[el2_ifu_ifc_ctl.scala 98:17] + wire _T_71 = state[1] & _T_70; // @[el2_ifu_ifc_ctl.scala 98:15] + wire _T_73 = _T_71 & _T_67; // @[el2_ifu_ifc_ctl.scala 98:31] + wire next_state_1 = _T_68 | _T_73; // @[el2_ifu_ifc_ctl.scala 97:67] + wire _T_75 = _T_67 & leave_idle; // @[el2_ifu_ifc_ctl.scala 100:34] + wire _T_78 = state[0] & _T_67; // @[el2_ifu_ifc_ctl.scala 100:60] + wire next_state_0 = _T_75 | _T_78; // @[el2_ifu_ifc_ctl.scala 100:48] + wire wfm = state == 2'h3; // @[el2_ifu_ifc_ctl.scala 120:16] + reg fb_full_f; // @[el2_ifu_ifc_ctl.scala 123:52] + wire _T_136 = _T_35 | io_exu_flush_final; // @[el2_ifu_ifc_ctl.scala 127:61] + wire _T_137 = ~_T_136; // @[el2_ifu_ifc_ctl.scala 127:19] + wire _T_138 = fb_full_f & _T_137; // @[el2_ifu_ifc_ctl.scala 127:17] + wire _T_139 = _T_138 | dma_stall; // @[el2_ifu_ifc_ctl.scala 127:84] + wire _T_140 = io_ifc_fetch_req_bf_raw & _T_139; // @[el2_ifu_ifc_ctl.scala 126:60] + wire [31:0] _T_142 = {io_ifc_fetch_addr_bf,1'h0}; // @[Cat.scala 29:58] + wire iccm_acc_in_region_bf = _T_142[31:28] == 4'he; // @[el2_lib.scala 224:47] + wire iccm_acc_in_range_bf = _T_142[31:16] == 16'hee00; // @[el2_lib.scala 227:29] + wire _T_145 = ~io_ifc_iccm_access_bf; // @[el2_ifu_ifc_ctl.scala 133:30] + wire _T_148 = fb_full_f & _T_36; // @[el2_ifu_ifc_ctl.scala 134:16] + wire _T_149 = _T_145 | _T_148; // @[el2_ifu_ifc_ctl.scala 133:53] + wire _T_150 = ~io_ifc_fetch_req_bf; // @[el2_ifu_ifc_ctl.scala 135:13] + wire _T_151 = wfm & _T_150; // @[el2_ifu_ifc_ctl.scala 135:11] + wire _T_152 = _T_149 | _T_151; // @[el2_ifu_ifc_ctl.scala 134:62] + wire _T_153 = _T_152 | idle; // @[el2_ifu_ifc_ctl.scala 135:35] + wire _T_155 = _T_153 & _T_2; // @[el2_ifu_ifc_ctl.scala 135:44] + wire _T_157 = ~iccm_acc_in_range_bf; // @[el2_ifu_ifc_ctl.scala 137:33] + wire [4:0] _T_160 = {io_ifc_fetch_addr_bf[30:27],1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_161 = io_dec_tlu_mrac_ff >> _T_160; // @[el2_ifu_ifc_ctl.scala 138:53] + reg _T_164; // @[el2_ifu_ifc_ctl.scala 140:57] + reg [30:0] _T_166; // @[el2_lib.scala 514:16] + rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_io_l1clk), + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en), + .io_scan_mode(rvclkhdr_io_scan_mode) + ); + assign io_ifc_fetch_addr_f = _T_166; // @[el2_ifu_ifc_ctl.scala 142:23] + assign io_ifc_fetch_addr_bf = _T_22 | _T_20; // @[el2_ifu_ifc_ctl.scala 72:24] + assign io_ifc_fetch_req_f = _T_164; // @[el2_ifu_ifc_ctl.scala 140:22] + assign io_ifu_pmu_fetch_stall = wfm | _T_140; // @[el2_ifu_ifc_ctl.scala 126:26] + assign io_ifc_fetch_uncacheable_bf = ~_T_161[0]; // @[el2_ifu_ifc_ctl.scala 138:31] + assign io_ifc_fetch_req_bf = _T_43 & _T_44; // @[el2_ifu_ifc_ctl.scala 84:23] + assign io_ifc_fetch_req_bf_raw = ~idle; // @[el2_ifu_ifc_ctl.scala 82:27] + assign io_ifc_iccm_access_bf = _T_142[31:16] == 16'hee00; // @[el2_ifu_ifc_ctl.scala 132:25] + assign io_ifc_region_acc_fault_bf = _T_157 & iccm_acc_in_region_bf; // @[el2_ifu_ifc_ctl.scala 137:30] + assign io_ifc_dma_access_ok = _T_155 | dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctl.scala 133:24] + assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_io_en = io_exu_flush_final | io_ifc_fetch_req_f; // @[el2_lib.scala 511:17] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + dma_iccm_stall_any_f = _RAND_0[0:0]; + _RAND_1 = {1{`RANDOM}}; + miss_a = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + state = _RAND_2[1:0]; + _RAND_3 = {1{`RANDOM}}; + fb_write_f = _RAND_3[3:0]; + _RAND_4 = {1{`RANDOM}}; + fb_full_f = _RAND_4[0:0]; + _RAND_5 = {1{`RANDOM}}; + _T_164 = _RAND_5[0:0]; + _RAND_6 = {1{`RANDOM}}; + _T_166 = _RAND_6[30:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + dma_iccm_stall_any_f = 1'h0; + end + if (reset) begin + miss_a = 1'h0; + end + if (reset) begin + state = 2'h0; + end + if (reset) begin + fb_write_f = 4'h0; + end + if (reset) begin + fb_full_f = 1'h0; + end + if (reset) begin + _T_164 = 1'h0; + end + if (reset) begin + _T_166 = 31'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + dma_iccm_stall_any_f <= 1'h0; + end else begin + dma_iccm_stall_any_f <= io_dma_iccm_stall_any; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + miss_a <= 1'h0; + end else begin + miss_a <= _T_48 & _T_2; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + state <= 2'h0; + end else begin + state <= {next_state_1,next_state_0}; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + fb_write_f <= 4'h0; + end else begin + fb_write_f <= _T_128 | _T_125; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + fb_full_f <= 1'h0; + end else begin + fb_full_f <= fb_write_ns[3]; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + _T_164 <= 1'h0; + end else begin + _T_164 <= io_ifc_fetch_req_bf; + end + end + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin + if (reset) begin + _T_166 <= 31'h0; + end else begin + _T_166 <= io_ifc_fetch_addr_bf; + end + end +endmodule diff --git a/el2_ifu_mem_ctl.anno.json b/el2_ifu_mem_ctl.anno.json new file mode 100644 index 00000000..a9095102 --- /dev/null +++ b/el2_ifu_mem_ctl.anno.json @@ -0,0 +1,357 @@ +[ + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f", + "sources":[ + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_access_fault_type_f", + "sources":[ + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_ecc_double_err", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_core_ecc_disable", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_data_ecc", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_inst_mask_f", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_sel_premux_data", + "sources":[ + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_hit_taken_f", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_axi_rid", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_axi_rvalid", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bus_clk_en" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_write_stall", + "sources":[ + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_hit_taken_f", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rw_addr", + "sources":[ + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dma_mem_addr", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dma_iccm_req", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_fetch_addr_bf", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_dma_sb_error", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_dma_access_ok", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_core_ecc_disable", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_data_ecc", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_inst_mask_f", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_debug_addr", + "sources":[ + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_ic_diag_pkt_icache_dicawics" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_async_error_start", + "sources":[ + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_ecc_single_err", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_error_start", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_eccerr", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_tag_perr", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_core_ecc_disable", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_data_ecc", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_hit_taken_f", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_inst_mask_f", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_axi_rid", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_axi_rvalid", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bus_clk_en" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_debug_way", + "sources":[ + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_ic_diag_pkt_icache_dicawics" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_wren", + "sources":[ + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dma_mem_write", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dma_iccm_req", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_dma_sb_error", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_dma_access_ok", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_core_ecc_disable", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_data_ecc", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_inst_mask_f", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_debug_rd_en", + "sources":[ + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_ic_diag_pkt_icache_rd_valid" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_access_fault_f", + "sources":[ + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rden", + "sources":[ + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_iccm_access_bf", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_fetch_req_bf", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dma_iccm_req", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dma_mem_write", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_dma_sb_error", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_dma_access_ok", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_core_ecc_disable", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_data_ecc", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_inst_mask_f", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_en", + "sources":[ + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_iccm_access_bf", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_fetch_req_bf", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_fetch_uncacheable_bf", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_force_halt", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_hit_taken_f", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_premux_data", + "sources":[ + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_data", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_hit_taken_f", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_axi_rid", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_axi_rvalid", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bus_clk_en" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_wr_size", + "sources":[ + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dma_mem_sz", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dma_iccm_req" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_debug_wr_en", + "sources":[ + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_ic_diag_pkt_icache_wr_valid" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_dma_active", + "sources":[ + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_flush_err_wb", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_i0_commit_cmt", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_fetch_val", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_data_f", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_data" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_ready", + "sources":[ + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_dma_sb_error", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_dma_access_ok", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_core_ecc_disable", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_data_ecc", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_inst_mask_f", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_dma_sb_error", + "sources":[ + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_core_ecc_disable", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_data_ecc", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_inst_mask_f", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_error_start", + "sources":[ + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_eccerr", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_tag_perr", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_hit_taken_f", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_axi_rid", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_axi_rvalid", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bus_clk_en" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f", + "sources":[ + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_inst_mask_f", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_debug_tag_array", + "sources":[ + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_ic_diag_pkt_icache_dicawics" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_wr_data", + "sources":[ + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dma_iccm_req", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dma_mem_wdata", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_dma_sb_error", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_dma_access_ok", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_core_ecc_disable", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_data_ecc", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_inst_mask_f", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_tag_valid", + "sources":[ + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_ecc_single_err", + "sources":[ + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_core_ecc_disable", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_data_ecc", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_inst_mask_f", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_data_f", + "sources":[ + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_data" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rw_addr", + "sources":[ + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_fetch_addr_bf" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_ecc_double_err", + "sources":[ + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_core_ecc_disable", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_data_ecc", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_inst_mask_f", + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_debug_wr_data", + "sources":[ + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_ic_diag_pkt_icache_wrdata" + ] + }, + { + "class":"firrtl.EmitCircuitAnnotation", + "emitter":"firrtl.VerilogEmitter" + }, + { + "class":"firrtl.transforms.BlackBoxResourceAnno", + "target":"el2_ifu_mem_ctl.gated_latch", + "resourceId":"/vsrc/gated_latch.v" + }, + { + "class":"firrtl.options.TargetDirAnnotation", + "directory":"." + }, + { + "class":"firrtl.options.OutputAnnotationFileAnnotation", + "file":"el2_ifu_mem_ctl" + }, + { + "class":"firrtl.transforms.BlackBoxTargetDirAnno", + "targetDir":"." + } +] \ No newline at end of file diff --git a/el2_ifu_mem_ctl.fir b/el2_ifu_mem_ctl.fir new file mode 100644 index 00000000..b25a0606 --- /dev/null +++ b/el2_ifu_mem_ctl.fir @@ -0,0 +1,15682 @@ +;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 +circuit el2_ifu_mem_ctl : + extmodule gated_latch : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_1 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_1 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_1 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_2 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_2 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_2 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_3 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_3 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_3 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_4 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_4 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_4 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_5 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_5 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_5 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_6 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_6 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_6 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_7 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_7 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_7 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_8 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_8 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_8 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_9 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_9 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_9 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_10 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_10 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_10 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_11 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_11 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_11 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_12 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_12 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_12 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_13 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_13 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_13 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_14 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_14 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_14 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_15 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_15 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_15 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_16 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_16 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_16 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_17 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_17 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_17 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_18 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_18 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_18 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_19 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_19 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_19 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_20 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_20 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_20 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_21 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_21 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_21 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_22 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_22 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_22 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_23 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_23 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_23 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_24 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_24 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_24 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_25 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_25 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_25 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_26 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_26 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_26 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_27 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_27 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_27 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_28 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_28 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_28 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_29 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_29 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_29 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_30 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_30 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_30 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_31 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_31 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_31 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_32 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_32 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_32 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_33 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_33 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_33 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_34 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_34 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_34 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_35 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_35 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_35 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_36 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_36 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_36 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_37 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_37 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_37 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_38 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_38 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_38 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_39 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_39 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_39 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_40 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_40 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_40 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_41 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_41 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_41 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_42 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_42 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_42 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_43 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_43 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_43 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_44 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_44 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_44 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_45 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_45 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_45 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_46 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_46 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_46 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_47 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_47 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_47 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_48 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_48 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_48 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_49 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_49 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_49 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_50 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_50 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_50 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_51 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_51 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_51 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_52 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_52 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_52 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_53 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_53 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_53 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_54 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_54 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_54 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_55 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_55 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_55 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_56 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_56 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_56 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_57 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_57 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_57 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_58 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_58 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_58 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_59 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_59 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_59 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_60 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_60 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_60 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_61 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_61 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_61 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_62 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_62 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_62 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_63 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_63 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_63 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_64 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_64 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_64 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_65 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_65 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_65 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_66 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_66 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_66 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_67 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_67 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_67 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_68 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_68 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_68 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_69 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_69 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_69 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_70 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_70 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_70 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_71 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_71 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_71 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_72 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_72 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_72 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_73 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_73 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_73 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_74 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_74 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_74 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_75 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_75 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_75 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_76 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_76 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_76 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_77 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_77 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_77 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_78 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_78 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_78 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_79 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_79 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_79 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_80 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_80 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_80 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_81 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_81 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_81 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_82 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_82 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_82 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_83 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_83 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_83 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_84 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_84 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_84 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_85 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_85 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_85 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_86 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_86 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_86 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_87 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_87 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_87 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_88 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_88 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_88 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_89 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_89 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_89 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_90 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_90 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_90 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_91 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_91 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_91 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_92 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_92 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_92 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_93 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_93 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_93 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + module el2_ifu_mem_ctl : + input clock : Clock + input reset : AsyncReset + output io : {flip free_clk : Clock, flip active_clk : Clock, flip exu_flush_final : UInt<1>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_flush_err_wb : UInt<1>, flip dec_tlu_i0_commit_cmt : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip ifc_fetch_addr_bf : UInt<31>, flip ifc_fetch_uncacheable_bf : UInt<1>, flip ifc_fetch_req_bf : UInt<1>, flip ifc_fetch_req_bf_raw : UInt<1>, flip ifc_iccm_access_bf : UInt<1>, flip ifc_region_acc_fault_bf : UInt<1>, flip ifc_dma_access_ok : UInt<1>, flip dec_tlu_fence_i_wb : UInt<1>, flip ifu_bp_hit_taken_f : UInt<1>, flip ifu_bp_inst_mask_f : UInt<1>, flip ifu_axi_arready : UInt<1>, flip ifu_axi_rvalid : UInt<1>, flip ifu_axi_rid : UInt<3>, flip ifu_axi_rdata : UInt<64>, flip ifu_axi_rresp : UInt<2>, flip ifu_bus_clk_en : UInt<1>, flip dma_iccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>, flip dma_mem_tag : UInt<3>, flip ic_rd_data : UInt<64>, flip ic_debug_rd_data : UInt<71>, flip ictag_debug_rd_data : UInt<26>, flip ic_eccerr : UInt<2>, flip ic_parerr : UInt<2>, flip ic_rd_hit : UInt<2>, flip ic_tag_perr : UInt<1>, flip iccm_rd_data : UInt<64>, flip iccm_rd_data_ecc : UInt<78>, flip ifu_fetch_val : UInt<2>, flip dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, ifu_miss_state_idle : UInt<1>, ifu_ic_mb_empty : UInt<1>, ic_dma_active : UInt<1>, ic_write_stall : UInt<1>, ifu_pmu_ic_miss : UInt<1>, ifu_pmu_ic_hit : UInt<1>, ifu_pmu_bus_error : UInt<1>, ifu_pmu_bus_busy : UInt<1>, ifu_pmu_bus_trxn : UInt<1>, ifu_axi_awvalid : UInt<1>, ifu_axi_awid : UInt<3>, ifu_axi_awaddr : UInt<32>, ifu_axi_awregion : UInt<4>, ifu_axi_awlen : UInt<8>, ifu_axi_awsize : UInt<3>, ifu_axi_awburst : UInt<2>, ifu_axi_awlock : UInt<1>, ifu_axi_awcache : UInt<4>, ifu_axi_awprot : UInt<3>, ifu_axi_awqos : UInt<4>, ifu_axi_wvalid : UInt<1>, ifu_axi_wdata : UInt<64>, ifu_axi_wstrb : UInt<8>, ifu_axi_wlast : UInt<1>, ifu_axi_bready : UInt<1>, ifu_axi_arvalid : UInt<1>, ifu_axi_arid : UInt<3>, ifu_axi_araddr : UInt<32>, ifu_axi_arregion : UInt<4>, ifu_axi_arlen : UInt<8>, ifu_axi_arsize : UInt<3>, ifu_axi_arburst : UInt<2>, ifu_axi_arlock : UInt<1>, ifu_axi_arcache : UInt<4>, ifu_axi_arprot : UInt<3>, ifu_axi_arqos : UInt<4>, ifu_axi_rready : UInt<1>, iccm_dma_ecc_error : UInt<1>, iccm_dma_rvalid : UInt<1>, iccm_dma_rdata : UInt<64>, iccm_dma_rtag : UInt<3>, iccm_ready : UInt<1>, ic_rw_addr : UInt<31>, ic_wr_en : UInt<2>, ic_rd_en : UInt<1>, ic_wr_data : UInt<71>[2], ic_debug_wr_data : UInt<71>, ifu_ic_debug_rd_data : UInt<71>, ic_debug_addr : UInt<10>, ic_debug_rd_en : UInt<1>, ic_debug_wr_en : UInt<1>, ic_debug_tag_array : UInt<1>, ic_debug_way : UInt<2>, ic_tag_valid : UInt<2>, iccm_rw_addr : UInt<15>, iccm_wren : UInt<1>, iccm_rden : UInt<1>, iccm_wr_data : UInt<78>, iccm_wr_size : UInt<3>, ic_hit_f : UInt<1>, ic_access_fault_f : UInt<1>, ic_access_fault_type_f : UInt<2>, iccm_rd_ecc_single_err : UInt<1>, iccm_rd_ecc_double_err : UInt<1>, ic_error_start : UInt<1>, ifu_async_error_start : UInt<1>, iccm_dma_sb_error : UInt<1>, ic_fetch_val_f : UInt<2>, ic_data_f : UInt<32>, ic_premux_data : UInt<64>, ic_sel_premux_data : UInt<1>, flip dec_tlu_core_ecc_disable : UInt<1>, ifu_ic_debug_rd_data_valid : UInt<1>, iccm_buf_correct_ecc : UInt<1>, iccm_correction_state : UInt<1>, flip scan_mode : UInt<1>} + + io.ifu_axi_wvalid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 135:21] + io.ifu_axi_wdata <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 136:20] + io.ifu_axi_awqos <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 137:20] + io.ifu_axi_awaddr <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 138:21] + io.ifu_axi_awprot <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 139:21] + io.ifu_axi_awlen <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 140:20] + io.ifu_axi_arlock <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 141:21] + io.ifu_axi_awregion <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 142:23] + io.ifu_axi_awid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 143:19] + io.ifu_axi_awvalid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 144:22] + io.ifu_axi_wstrb <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 145:20] + io.ifu_axi_awcache <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 146:22] + io.ifu_axi_arqos <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 147:20] + io.ifu_axi_awlock <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 148:21] + io.ifu_axi_bready <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 149:21] + io.ifu_axi_arlen <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 150:20] + io.ifu_axi_awsize <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 151:21] + io.ifu_axi_arprot <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 152:21] + io.ifu_axi_awburst <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 153:22] + io.ifu_axi_wlast <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 154:20] + wire iccm_single_ecc_error : UInt<2> + iccm_single_ecc_error <= UInt<1>("h00") + wire ifc_fetch_req_f : UInt<1> + ifc_fetch_req_f <= UInt<1>("h00") + wire miss_pending : UInt<1> + miss_pending <= UInt<1>("h00") + wire scnd_miss_req : UInt<1> + scnd_miss_req <= UInt<1>("h00") + wire dma_iccm_req_f : UInt<1> + dma_iccm_req_f <= UInt<1>("h00") + wire iccm_correct_ecc : UInt<1> + iccm_correct_ecc <= UInt<1>("h00") + wire perr_state : UInt<3> + perr_state <= UInt<1>("h00") + wire err_stop_state : UInt<2> + err_stop_state <= UInt<1>("h00") + wire err_stop_fetch : UInt<1> + err_stop_fetch <= UInt<1>("h00") + wire miss_state : UInt<3> + miss_state <= UInt<1>("h00") + wire miss_nxtstate : UInt<3> + miss_nxtstate <= UInt<1>("h00") + wire miss_state_en : UInt<1> + miss_state_en <= UInt<1>("h00") + wire ifu_bus_rsp_valid : UInt<1> + ifu_bus_rsp_valid <= UInt<1>("h00") + wire bus_ifu_bus_clk_en : UInt<1> + bus_ifu_bus_clk_en <= UInt<1>("h00") + wire ifu_bus_rsp_ready : UInt<1> + ifu_bus_rsp_ready <= UInt<1>("h00") + wire uncacheable_miss_ff : UInt<1> + uncacheable_miss_ff <= UInt<1>("h00") + wire ic_act_miss_f : UInt<1> + ic_act_miss_f <= UInt<1>("h00") + wire ic_byp_hit_f : UInt<1> + ic_byp_hit_f <= UInt<1>("h00") + wire bus_new_data_beat_count : UInt<3> + bus_new_data_beat_count <= UInt<1>("h00") + wire bus_ifu_wr_en_ff : UInt<1> + bus_ifu_wr_en_ff <= UInt<1>("h00") + wire last_beat : UInt<1> + last_beat <= UInt<1>("h00") + wire last_data_recieved_ff : UInt<1> + last_data_recieved_ff <= UInt<1>("h00") + wire stream_eol_f : UInt<1> + stream_eol_f <= UInt<1>("h00") + wire ic_miss_under_miss_f : UInt<1> + ic_miss_under_miss_f <= UInt<1>("h00") + wire ic_ignore_2nd_miss_f : UInt<1> + ic_ignore_2nd_miss_f <= UInt<1>("h00") + wire ic_debug_rd_en_ff : UInt<1> + ic_debug_rd_en_ff <= UInt<1>("h00") + inst rvclkhdr of rvclkhdr @[el2_lib.scala 483:22] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr.io.en <= ic_debug_rd_en_ff @[el2_lib.scala 485:16] + rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + reg flush_final_f : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 186:53] + flush_final_f <= io.exu_flush_final @[el2_ifu_mem_ctl.scala 186:53] + node _T = or(io.ifc_fetch_req_bf_raw, ifc_fetch_req_f) @[el2_ifu_mem_ctl.scala 187:53] + node _T_1 = or(_T, miss_pending) @[el2_ifu_mem_ctl.scala 187:71] + node _T_2 = or(_T_1, io.exu_flush_final) @[el2_ifu_mem_ctl.scala 187:86] + node fetch_bf_f_c1_clken = or(_T_2, scnd_miss_req) @[el2_ifu_mem_ctl.scala 187:107] + node debug_c1_clken = or(io.ic_debug_rd_en, io.ic_debug_wr_en) @[el2_ifu_mem_ctl.scala 188:42] + inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 483:22] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_1.io.en <= debug_c1_clken @[el2_lib.scala 485:16] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 483:22] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_2.io.en <= fetch_bf_f_c1_clken @[el2_lib.scala 485:16] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + node _T_3 = orr(iccm_single_ecc_error) @[el2_ifu_mem_ctl.scala 191:52] + node _T_4 = bits(dma_iccm_req_f, 0, 0) @[el2_ifu_mem_ctl.scala 191:78] + node _T_5 = and(_T_3, _T_4) @[el2_ifu_mem_ctl.scala 191:55] + io.iccm_dma_sb_error <= _T_5 @[el2_ifu_mem_ctl.scala 191:24] + node _T_6 = or(io.iccm_rd_ecc_single_err, io.ic_error_start) @[el2_ifu_mem_ctl.scala 192:57] + io.ifu_async_error_start <= _T_6 @[el2_ifu_mem_ctl.scala 192:28] + node _T_7 = eq(perr_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 193:54] + node _T_8 = or(iccm_correct_ecc, _T_7) @[el2_ifu_mem_ctl.scala 193:40] + node _T_9 = eq(err_stop_state, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 193:90] + node _T_10 = or(_T_8, _T_9) @[el2_ifu_mem_ctl.scala 193:72] + node _T_11 = or(_T_10, err_stop_fetch) @[el2_ifu_mem_ctl.scala 193:112] + node _T_12 = or(_T_11, io.dec_tlu_flush_err_wb) @[el2_ifu_mem_ctl.scala 193:129] + io.ic_dma_active <= _T_12 @[el2_ifu_mem_ctl.scala 193:20] + node _T_13 = and(ifu_bus_rsp_valid, bus_ifu_bus_clk_en) @[el2_ifu_mem_ctl.scala 195:44] + node _T_14 = and(_T_13, ifu_bus_rsp_ready) @[el2_ifu_mem_ctl.scala 195:65] + node _T_15 = andr(bus_new_data_beat_count) @[el2_ifu_mem_ctl.scala 195:112] + node _T_16 = and(_T_14, _T_15) @[el2_ifu_mem_ctl.scala 195:85] + node _T_17 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 196:5] + node _T_18 = and(_T_16, _T_17) @[el2_ifu_mem_ctl.scala 195:118] + node _T_19 = eq(miss_state, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 196:41] + node _T_20 = eq(miss_nxtstate, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 196:73] + node _T_21 = or(_T_19, _T_20) @[el2_ifu_mem_ctl.scala 196:57] + node _T_22 = and(_T_18, _T_21) @[el2_ifu_mem_ctl.scala 196:26] + node _T_23 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 196:93] + node scnd_miss_req_in = and(_T_22, _T_23) @[el2_ifu_mem_ctl.scala 196:91] + node ifu_bp_hit_taken_q_f = and(io.ifu_bp_hit_taken_f, io.ic_hit_f) @[el2_ifu_mem_ctl.scala 198:52] + node _T_24 = eq(UInt<3>("h00"), miss_state) @[Conditional.scala 37:30] + when _T_24 : @[Conditional.scala 40:58] + node _T_25 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 202:45] + node _T_26 = and(ic_act_miss_f, _T_25) @[el2_ifu_mem_ctl.scala 202:43] + node _T_27 = bits(_T_26, 0, 0) @[el2_ifu_mem_ctl.scala 202:66] + node _T_28 = mux(_T_27, UInt<3>("h01"), UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 202:27] + miss_nxtstate <= _T_28 @[el2_ifu_mem_ctl.scala 202:21] + node _T_29 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 203:40] + node _T_30 = and(ic_act_miss_f, _T_29) @[el2_ifu_mem_ctl.scala 203:38] + miss_state_en <= _T_30 @[el2_ifu_mem_ctl.scala 203:21] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_31 = eq(UInt<3>("h01"), miss_state) @[Conditional.scala 37:30] + when _T_31 : @[Conditional.scala 39:67] + node _T_32 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 206:113] + node _T_33 = or(last_data_recieved_ff, _T_32) @[el2_ifu_mem_ctl.scala 206:93] + node _T_34 = and(ic_byp_hit_f, _T_33) @[el2_ifu_mem_ctl.scala 206:67] + node _T_35 = and(_T_34, uncacheable_miss_ff) @[el2_ifu_mem_ctl.scala 206:127] + node _T_36 = or(io.dec_tlu_force_halt, _T_35) @[el2_ifu_mem_ctl.scala 206:51] + node _T_37 = bits(_T_36, 0, 0) @[el2_ifu_mem_ctl.scala 206:152] + node _T_38 = eq(last_data_recieved_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 207:30] + node _T_39 = and(ic_byp_hit_f, _T_38) @[el2_ifu_mem_ctl.scala 207:27] + node _T_40 = and(_T_39, uncacheable_miss_ff) @[el2_ifu_mem_ctl.scala 207:53] + node _T_41 = bits(_T_40, 0, 0) @[el2_ifu_mem_ctl.scala 207:77] + node _T_42 = eq(ic_byp_hit_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 208:16] + node _T_43 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 208:32] + node _T_44 = and(_T_42, _T_43) @[el2_ifu_mem_ctl.scala 208:30] + node _T_45 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 208:72] + node _T_46 = and(_T_44, _T_45) @[el2_ifu_mem_ctl.scala 208:52] + node _T_47 = and(_T_46, uncacheable_miss_ff) @[el2_ifu_mem_ctl.scala 208:85] + node _T_48 = bits(_T_47, 0, 0) @[el2_ifu_mem_ctl.scala 208:109] + node _T_49 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 209:36] + node _T_50 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 209:51] + node _T_51 = and(_T_49, _T_50) @[el2_ifu_mem_ctl.scala 209:49] + node _T_52 = bits(_T_51, 0, 0) @[el2_ifu_mem_ctl.scala 209:73] + node _T_53 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 210:35] + node _T_54 = and(ic_byp_hit_f, _T_53) @[el2_ifu_mem_ctl.scala 210:33] + node _T_55 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 210:76] + node _T_56 = eq(_T_55, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 210:57] + node _T_57 = and(_T_54, _T_56) @[el2_ifu_mem_ctl.scala 210:55] + node _T_58 = eq(ifu_bp_hit_taken_q_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 210:91] + node _T_59 = and(_T_57, _T_58) @[el2_ifu_mem_ctl.scala 210:89] + node _T_60 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 210:115] + node _T_61 = and(_T_59, _T_60) @[el2_ifu_mem_ctl.scala 210:113] + node _T_62 = bits(_T_61, 0, 0) @[el2_ifu_mem_ctl.scala 210:137] + node _T_63 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 211:41] + node _T_64 = and(bus_ifu_wr_en_ff, _T_63) @[el2_ifu_mem_ctl.scala 211:39] + node _T_65 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 211:82] + node _T_66 = eq(_T_65, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 211:63] + node _T_67 = and(_T_64, _T_66) @[el2_ifu_mem_ctl.scala 211:61] + node _T_68 = eq(ifu_bp_hit_taken_q_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 211:97] + node _T_69 = and(_T_67, _T_68) @[el2_ifu_mem_ctl.scala 211:95] + node _T_70 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 211:121] + node _T_71 = and(_T_69, _T_70) @[el2_ifu_mem_ctl.scala 211:119] + node _T_72 = bits(_T_71, 0, 0) @[el2_ifu_mem_ctl.scala 211:143] + node _T_73 = eq(ic_byp_hit_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 212:24] + node _T_74 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 212:42] + node _T_75 = and(_T_73, _T_74) @[el2_ifu_mem_ctl.scala 212:39] + node _T_76 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 212:83] + node _T_77 = and(_T_75, _T_76) @[el2_ifu_mem_ctl.scala 212:62] + node _T_78 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 212:104] + node _T_79 = and(_T_77, _T_78) @[el2_ifu_mem_ctl.scala 212:102] + node _T_80 = bits(_T_79, 0, 0) @[el2_ifu_mem_ctl.scala 212:126] + node _T_81 = or(io.exu_flush_final, ifu_bp_hit_taken_q_f) @[el2_ifu_mem_ctl.scala 213:46] + node _T_82 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 213:91] + node _T_83 = eq(_T_82, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 213:72] + node _T_84 = and(_T_81, _T_83) @[el2_ifu_mem_ctl.scala 213:70] + node _T_85 = bits(_T_84, 0, 0) @[el2_ifu_mem_ctl.scala 213:105] + node _T_86 = mux(_T_85, UInt<3>("h02"), UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 213:24] + node _T_87 = mux(_T_80, UInt<3>("h00"), _T_86) @[el2_ifu_mem_ctl.scala 212:22] + node _T_88 = mux(_T_72, UInt<3>("h06"), _T_87) @[el2_ifu_mem_ctl.scala 211:20] + node _T_89 = mux(_T_62, UInt<3>("h06"), _T_88) @[el2_ifu_mem_ctl.scala 210:18] + node _T_90 = mux(_T_52, UInt<3>("h00"), _T_89) @[el2_ifu_mem_ctl.scala 209:16] + node _T_91 = mux(_T_48, UInt<3>("h04"), _T_90) @[el2_ifu_mem_ctl.scala 208:14] + node _T_92 = mux(_T_41, UInt<3>("h03"), _T_91) @[el2_ifu_mem_ctl.scala 207:12] + node _T_93 = mux(_T_37, UInt<3>("h00"), _T_92) @[el2_ifu_mem_ctl.scala 206:27] + miss_nxtstate <= _T_93 @[el2_ifu_mem_ctl.scala 206:21] + node _T_94 = or(io.dec_tlu_force_halt, io.exu_flush_final) @[el2_ifu_mem_ctl.scala 214:46] + node _T_95 = or(_T_94, ic_byp_hit_f) @[el2_ifu_mem_ctl.scala 214:67] + node _T_96 = or(_T_95, ifu_bp_hit_taken_q_f) @[el2_ifu_mem_ctl.scala 214:82] + node _T_97 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 214:125] + node _T_98 = or(_T_96, _T_97) @[el2_ifu_mem_ctl.scala 214:105] + node _T_99 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 214:160] + node _T_100 = and(bus_ifu_wr_en_ff, _T_99) @[el2_ifu_mem_ctl.scala 214:158] + node _T_101 = or(_T_98, _T_100) @[el2_ifu_mem_ctl.scala 214:138] + miss_state_en <= _T_101 @[el2_ifu_mem_ctl.scala 214:21] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_102 = eq(UInt<3>("h04"), miss_state) @[Conditional.scala 37:30] + when _T_102 : @[Conditional.scala 39:67] + miss_nxtstate <= UInt<3>("h00") @[el2_ifu_mem_ctl.scala 217:21] + node _T_103 = or(io.exu_flush_final, flush_final_f) @[el2_ifu_mem_ctl.scala 218:43] + node _T_104 = or(_T_103, ic_byp_hit_f) @[el2_ifu_mem_ctl.scala 218:59] + node _T_105 = or(_T_104, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 218:74] + miss_state_en <= _T_105 @[el2_ifu_mem_ctl.scala 218:21] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_106 = eq(UInt<3>("h06"), miss_state) @[Conditional.scala 37:30] + when _T_106 : @[Conditional.scala 39:67] + node _T_107 = or(io.exu_flush_final, ifu_bp_hit_taken_q_f) @[el2_ifu_mem_ctl.scala 221:49] + node _T_108 = or(_T_107, stream_eol_f) @[el2_ifu_mem_ctl.scala 221:72] + node _T_109 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 221:108] + node _T_110 = eq(_T_109, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 221:89] + node _T_111 = and(_T_108, _T_110) @[el2_ifu_mem_ctl.scala 221:87] + node _T_112 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 221:124] + node _T_113 = and(_T_111, _T_112) @[el2_ifu_mem_ctl.scala 221:122] + node _T_114 = bits(_T_113, 0, 0) @[el2_ifu_mem_ctl.scala 221:148] + node _T_115 = mux(_T_114, UInt<3>("h02"), UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 221:27] + miss_nxtstate <= _T_115 @[el2_ifu_mem_ctl.scala 221:21] + node _T_116 = or(io.exu_flush_final, ifu_bp_hit_taken_q_f) @[el2_ifu_mem_ctl.scala 222:43] + node _T_117 = or(_T_116, stream_eol_f) @[el2_ifu_mem_ctl.scala 222:67] + node _T_118 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 222:105] + node _T_119 = or(_T_117, _T_118) @[el2_ifu_mem_ctl.scala 222:84] + node _T_120 = or(_T_119, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 222:118] + miss_state_en <= _T_120 @[el2_ifu_mem_ctl.scala 222:21] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_121 = eq(UInt<3>("h03"), miss_state) @[Conditional.scala 37:30] + when _T_121 : @[Conditional.scala 39:67] + node _T_122 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 225:69] + node _T_123 = eq(_T_122, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 225:50] + node _T_124 = and(io.exu_flush_final, _T_123) @[el2_ifu_mem_ctl.scala 225:48] + node _T_125 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 225:84] + node _T_126 = and(_T_124, _T_125) @[el2_ifu_mem_ctl.scala 225:82] + node _T_127 = bits(_T_126, 0, 0) @[el2_ifu_mem_ctl.scala 225:108] + node _T_128 = mux(_T_127, UInt<3>("h02"), UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 225:27] + miss_nxtstate <= _T_128 @[el2_ifu_mem_ctl.scala 225:21] + node _T_129 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 226:63] + node _T_130 = or(io.exu_flush_final, _T_129) @[el2_ifu_mem_ctl.scala 226:43] + node _T_131 = or(_T_130, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 226:76] + miss_state_en <= _T_131 @[el2_ifu_mem_ctl.scala 226:21] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_132 = eq(UInt<3>("h02"), miss_state) @[Conditional.scala 37:30] + when _T_132 : @[Conditional.scala 39:67] + node _T_133 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 229:71] + node _T_134 = eq(_T_133, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 229:52] + node _T_135 = and(ic_miss_under_miss_f, _T_134) @[el2_ifu_mem_ctl.scala 229:50] + node _T_136 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 229:86] + node _T_137 = and(_T_135, _T_136) @[el2_ifu_mem_ctl.scala 229:84] + node _T_138 = bits(_T_137, 0, 0) @[el2_ifu_mem_ctl.scala 229:110] + node _T_139 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 230:56] + node _T_140 = eq(_T_139, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 230:37] + node _T_141 = and(ic_ignore_2nd_miss_f, _T_140) @[el2_ifu_mem_ctl.scala 230:35] + node _T_142 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 230:71] + node _T_143 = and(_T_141, _T_142) @[el2_ifu_mem_ctl.scala 230:69] + node _T_144 = bits(_T_143, 0, 0) @[el2_ifu_mem_ctl.scala 230:95] + node _T_145 = mux(_T_144, UInt<3>("h07"), UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 230:12] + node _T_146 = mux(_T_138, UInt<3>("h05"), _T_145) @[el2_ifu_mem_ctl.scala 229:27] + miss_nxtstate <= _T_146 @[el2_ifu_mem_ctl.scala 229:21] + node _T_147 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 231:42] + node _T_148 = or(_T_147, ic_miss_under_miss_f) @[el2_ifu_mem_ctl.scala 231:55] + node _T_149 = or(_T_148, ic_ignore_2nd_miss_f) @[el2_ifu_mem_ctl.scala 231:78] + node _T_150 = or(_T_149, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 231:101] + miss_state_en <= _T_150 @[el2_ifu_mem_ctl.scala 231:21] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_151 = eq(UInt<3>("h05"), miss_state) @[Conditional.scala 37:30] + when _T_151 : @[Conditional.scala 39:67] + node _T_152 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 235:31] + node _T_153 = bits(_T_152, 0, 0) @[el2_ifu_mem_ctl.scala 235:44] + node _T_154 = mux(_T_153, UInt<3>("h00"), UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 235:12] + node _T_155 = mux(io.exu_flush_final, _T_154, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 234:62] + node _T_156 = mux(io.dec_tlu_force_halt, UInt<3>("h00"), _T_155) @[el2_ifu_mem_ctl.scala 234:27] + miss_nxtstate <= _T_156 @[el2_ifu_mem_ctl.scala 234:21] + node _T_157 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 236:42] + node _T_158 = or(_T_157, io.exu_flush_final) @[el2_ifu_mem_ctl.scala 236:55] + node _T_159 = or(_T_158, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 236:76] + miss_state_en <= _T_159 @[el2_ifu_mem_ctl.scala 236:21] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_160 = eq(UInt<3>("h07"), miss_state) @[Conditional.scala 37:30] + when _T_160 : @[Conditional.scala 39:67] + node _T_161 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 240:31] + node _T_162 = bits(_T_161, 0, 0) @[el2_ifu_mem_ctl.scala 240:44] + node _T_163 = mux(_T_162, UInt<3>("h00"), UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 240:12] + node _T_164 = mux(io.exu_flush_final, _T_163, UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 239:62] + node _T_165 = mux(io.dec_tlu_force_halt, UInt<3>("h00"), _T_164) @[el2_ifu_mem_ctl.scala 239:27] + miss_nxtstate <= _T_165 @[el2_ifu_mem_ctl.scala 239:21] + node _T_166 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 241:42] + node _T_167 = or(_T_166, io.exu_flush_final) @[el2_ifu_mem_ctl.scala 241:55] + node _T_168 = or(_T_167, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 241:76] + miss_state_en <= _T_168 @[el2_ifu_mem_ctl.scala 241:21] + skip @[Conditional.scala 39:67] + node _T_169 = bits(miss_state_en, 0, 0) @[el2_ifu_mem_ctl.scala 244:84] + reg _T_170 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_169 : @[Reg.scala 28:19] + _T_170 <= miss_nxtstate @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + miss_state <= _T_170 @[el2_ifu_mem_ctl.scala 244:14] + wire crit_byp_hit_f : UInt<1> + crit_byp_hit_f <= UInt<1>("h00") + wire way_status_mb_scnd_ff : UInt<1> + way_status_mb_scnd_ff <= UInt<1>("h00") + wire way_status : UInt<1> + way_status <= UInt<1>("h00") + wire tagv_mb_scnd_ff : UInt<2> + tagv_mb_scnd_ff <= UInt<1>("h00") + wire uncacheable_miss_scnd_ff : UInt<1> + uncacheable_miss_scnd_ff <= UInt<1>("h00") + wire imb_scnd_ff : UInt<31> + imb_scnd_ff <= UInt<1>("h00") + wire reset_all_tags : UInt<1> + reset_all_tags <= UInt<1>("h00") + wire bus_rd_addr_count : UInt<3> + bus_rd_addr_count <= UInt<1>("h00") + wire ifu_bus_rid_ff : UInt<3> + ifu_bus_rid_ff <= UInt<1>("h00") + node _T_171 = neq(miss_state, UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 254:30] + miss_pending <= _T_171 @[el2_ifu_mem_ctl.scala 254:16] + node _T_172 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 255:39] + node _T_173 = eq(miss_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 255:73] + node _T_174 = eq(flush_final_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 255:95] + node _T_175 = and(_T_173, _T_174) @[el2_ifu_mem_ctl.scala 255:93] + node crit_wd_byp_ok_ff = or(_T_172, _T_175) @[el2_ifu_mem_ctl.scala 255:58] + node _T_176 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 256:57] + node _T_177 = eq(_T_176, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 256:38] + node _T_178 = and(miss_pending, _T_177) @[el2_ifu_mem_ctl.scala 256:36] + node _T_179 = eq(miss_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 256:86] + node _T_180 = and(_T_179, io.exu_flush_final) @[el2_ifu_mem_ctl.scala 256:106] + node _T_181 = eq(_T_180, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 256:72] + node _T_182 = and(_T_178, _T_181) @[el2_ifu_mem_ctl.scala 256:70] + node _T_183 = eq(miss_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 257:19] + node _T_184 = and(_T_183, crit_byp_hit_f) @[el2_ifu_mem_ctl.scala 257:39] + node _T_185 = eq(_T_184, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 257:5] + node _T_186 = and(_T_182, _T_185) @[el2_ifu_mem_ctl.scala 256:128] + node _T_187 = or(_T_186, ic_act_miss_f) @[el2_ifu_mem_ctl.scala 257:59] + node _T_188 = eq(miss_nxtstate, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 258:36] + node _T_189 = and(miss_pending, _T_188) @[el2_ifu_mem_ctl.scala 258:19] + node sel_hold_imb = or(_T_187, _T_189) @[el2_ifu_mem_ctl.scala 257:75] + node _T_190 = eq(miss_state, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 260:40] + node _T_191 = or(_T_190, ic_miss_under_miss_f) @[el2_ifu_mem_ctl.scala 260:57] + node _T_192 = eq(flush_final_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 260:83] + node sel_hold_imb_scnd = and(_T_191, _T_192) @[el2_ifu_mem_ctl.scala 260:81] + node _T_193 = eq(miss_state, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 261:46] + node way_status_mb_scnd_in = mux(_T_193, way_status_mb_scnd_ff, way_status) @[el2_ifu_mem_ctl.scala 261:34] + node _T_194 = eq(miss_state, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 263:40] + node _T_195 = eq(reset_all_tags, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 263:96] + node _T_196 = bits(_T_195, 0, 0) @[Bitwise.scala 72:15] + node _T_197 = mux(_T_196, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_198 = and(_T_197, io.ic_tag_valid) @[el2_ifu_mem_ctl.scala 263:113] + node tagv_mb_scnd_in = mux(_T_194, tagv_mb_scnd_ff, _T_198) @[el2_ifu_mem_ctl.scala 263:28] + node _T_199 = bits(sel_hold_imb_scnd, 0, 0) @[el2_ifu_mem_ctl.scala 264:56] + node uncacheable_miss_scnd_in = mux(_T_199, uncacheable_miss_scnd_ff, io.ifc_fetch_uncacheable_bf) @[el2_ifu_mem_ctl.scala 264:37] + reg _T_200 : UInt<1>, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 265:67] + _T_200 <= uncacheable_miss_scnd_in @[el2_ifu_mem_ctl.scala 265:67] + uncacheable_miss_scnd_ff <= _T_200 @[el2_ifu_mem_ctl.scala 265:28] + node _T_201 = bits(sel_hold_imb_scnd, 0, 0) @[el2_ifu_mem_ctl.scala 266:43] + node imb_scnd_in = mux(_T_201, imb_scnd_ff, io.ifc_fetch_addr_bf) @[el2_ifu_mem_ctl.scala 266:24] + reg _T_202 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 267:54] + _T_202 <= imb_scnd_in @[el2_ifu_mem_ctl.scala 267:54] + imb_scnd_ff <= _T_202 @[el2_ifu_mem_ctl.scala 267:15] + reg _T_203 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 268:64] + _T_203 <= way_status_mb_scnd_in @[el2_ifu_mem_ctl.scala 268:64] + way_status_mb_scnd_ff <= _T_203 @[el2_ifu_mem_ctl.scala 268:25] + reg _T_204 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 269:58] + _T_204 <= tagv_mb_scnd_in @[el2_ifu_mem_ctl.scala 269:58] + tagv_mb_scnd_ff <= _T_204 @[el2_ifu_mem_ctl.scala 269:19] + node _T_205 = bits(bus_ifu_wr_en_ff, 0, 0) @[Bitwise.scala 72:15] + node _T_206 = mux(_T_205, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node ic_wr_addr_bits_hi_3 = and(ifu_bus_rid_ff, _T_206) @[el2_ifu_mem_ctl.scala 272:45] + wire ifc_iccm_access_f : UInt<1> + ifc_iccm_access_f <= UInt<1>("h00") + wire ifc_region_acc_fault_final_f : UInt<1> + ifc_region_acc_fault_final_f <= UInt<1>("h00") + node _T_207 = eq(ifc_iccm_access_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 275:48] + node _T_208 = and(ifc_fetch_req_f, _T_207) @[el2_ifu_mem_ctl.scala 275:46] + node _T_209 = eq(ifc_region_acc_fault_final_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 275:69] + node fetch_req_icache_f = and(_T_208, _T_209) @[el2_ifu_mem_ctl.scala 275:67] + node fetch_req_iccm_f = and(ifc_fetch_req_f, ifc_iccm_access_f) @[el2_ifu_mem_ctl.scala 276:46] + node _T_210 = eq(miss_pending, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 277:45] + node _T_211 = eq(miss_state, UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 277:73] + node _T_212 = or(_T_210, _T_211) @[el2_ifu_mem_ctl.scala 277:59] + node _T_213 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 277:105] + node _T_214 = or(_T_212, _T_213) @[el2_ifu_mem_ctl.scala 277:91] + node ic_iccm_hit_f = and(fetch_req_iccm_f, _T_214) @[el2_ifu_mem_ctl.scala 277:41] + wire stream_hit_f : UInt<1> + stream_hit_f <= UInt<1>("h00") + node _T_215 = or(crit_byp_hit_f, stream_hit_f) @[el2_ifu_mem_ctl.scala 279:35] + node _T_216 = and(_T_215, fetch_req_icache_f) @[el2_ifu_mem_ctl.scala 279:52] + node _T_217 = and(_T_216, miss_pending) @[el2_ifu_mem_ctl.scala 279:73] + ic_byp_hit_f <= _T_217 @[el2_ifu_mem_ctl.scala 279:16] + wire sel_mb_addr_ff : UInt<1> + sel_mb_addr_ff <= UInt<1>("h00") + wire imb_ff : UInt<31> + imb_ff <= UInt<1>("h00") + wire ifu_fetch_addr_int_f : UInt<31> + ifu_fetch_addr_int_f <= UInt<1>("h00") + node _T_218 = orr(io.ic_rd_hit) @[el2_ifu_mem_ctl.scala 283:35] + node _T_219 = and(_T_218, fetch_req_icache_f) @[el2_ifu_mem_ctl.scala 283:39] + node _T_220 = eq(reset_all_tags, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 283:62] + node _T_221 = and(_T_219, _T_220) @[el2_ifu_mem_ctl.scala 283:60] + node _T_222 = eq(miss_pending, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 283:81] + node _T_223 = eq(miss_state, UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 283:108] + node _T_224 = or(_T_222, _T_223) @[el2_ifu_mem_ctl.scala 283:95] + node _T_225 = and(_T_221, _T_224) @[el2_ifu_mem_ctl.scala 283:78] + node _T_226 = eq(sel_mb_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 283:128] + node ic_act_hit_f = and(_T_225, _T_226) @[el2_ifu_mem_ctl.scala 283:126] + node _T_227 = orr(io.ic_rd_hit) @[el2_ifu_mem_ctl.scala 284:37] + node _T_228 = eq(_T_227, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 284:23] + node _T_229 = or(_T_228, reset_all_tags) @[el2_ifu_mem_ctl.scala 284:41] + node _T_230 = and(_T_229, fetch_req_icache_f) @[el2_ifu_mem_ctl.scala 284:59] + node _T_231 = eq(miss_pending, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 284:82] + node _T_232 = and(_T_230, _T_231) @[el2_ifu_mem_ctl.scala 284:80] + node _T_233 = or(_T_232, scnd_miss_req) @[el2_ifu_mem_ctl.scala 284:97] + node _T_234 = eq(ifc_region_acc_fault_final_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 284:116] + node _T_235 = and(_T_233, _T_234) @[el2_ifu_mem_ctl.scala 284:114] + ic_act_miss_f <= _T_235 @[el2_ifu_mem_ctl.scala 284:17] + node _T_236 = eq(io.ic_rd_hit, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 285:28] + node _T_237 = or(_T_236, reset_all_tags) @[el2_ifu_mem_ctl.scala 285:42] + node _T_238 = and(_T_237, fetch_req_icache_f) @[el2_ifu_mem_ctl.scala 285:60] + node _T_239 = eq(miss_state, UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 285:94] + node _T_240 = and(_T_238, _T_239) @[el2_ifu_mem_ctl.scala 285:81] + node _T_241 = bits(imb_ff, 30, 5) @[el2_ifu_mem_ctl.scala 286:12] + node _T_242 = bits(ifu_fetch_addr_int_f, 30, 5) @[el2_ifu_mem_ctl.scala 286:63] + node _T_243 = neq(_T_241, _T_242) @[el2_ifu_mem_ctl.scala 286:39] + node _T_244 = and(_T_240, _T_243) @[el2_ifu_mem_ctl.scala 285:111] + node _T_245 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 286:93] + node _T_246 = and(_T_244, _T_245) @[el2_ifu_mem_ctl.scala 286:91] + node _T_247 = eq(sel_mb_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 286:116] + node _T_248 = and(_T_246, _T_247) @[el2_ifu_mem_ctl.scala 286:114] + node _T_249 = eq(ifc_region_acc_fault_final_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 286:134] + node _T_250 = and(_T_248, _T_249) @[el2_ifu_mem_ctl.scala 286:132] + ic_miss_under_miss_f <= _T_250 @[el2_ifu_mem_ctl.scala 285:24] + node _T_251 = orr(io.ic_rd_hit) @[el2_ifu_mem_ctl.scala 287:42] + node _T_252 = eq(_T_251, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 287:28] + node _T_253 = or(_T_252, reset_all_tags) @[el2_ifu_mem_ctl.scala 287:46] + node _T_254 = and(_T_253, fetch_req_icache_f) @[el2_ifu_mem_ctl.scala 287:64] + node _T_255 = eq(miss_state, UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 287:99] + node _T_256 = and(_T_254, _T_255) @[el2_ifu_mem_ctl.scala 287:85] + node _T_257 = bits(imb_ff, 30, 5) @[el2_ifu_mem_ctl.scala 288:13] + node _T_258 = bits(ifu_fetch_addr_int_f, 30, 5) @[el2_ifu_mem_ctl.scala 288:62] + node _T_259 = eq(_T_257, _T_258) @[el2_ifu_mem_ctl.scala 288:39] + node _T_260 = or(_T_259, uncacheable_miss_ff) @[el2_ifu_mem_ctl.scala 288:91] + node _T_261 = and(_T_256, _T_260) @[el2_ifu_mem_ctl.scala 287:117] + ic_ignore_2nd_miss_f <= _T_261 @[el2_ifu_mem_ctl.scala 287:24] + node _T_262 = or(ic_act_hit_f, ic_byp_hit_f) @[el2_ifu_mem_ctl.scala 290:31] + node _T_263 = or(_T_262, ic_iccm_hit_f) @[el2_ifu_mem_ctl.scala 290:46] + node _T_264 = and(ifc_region_acc_fault_final_f, ifc_fetch_req_f) @[el2_ifu_mem_ctl.scala 290:94] + node _T_265 = or(_T_263, _T_264) @[el2_ifu_mem_ctl.scala 290:62] + io.ic_hit_f <= _T_265 @[el2_ifu_mem_ctl.scala 290:15] + node _T_266 = bits(scnd_miss_req, 0, 0) @[el2_ifu_mem_ctl.scala 291:47] + node _T_267 = bits(sel_hold_imb, 0, 0) @[el2_ifu_mem_ctl.scala 291:98] + node _T_268 = mux(_T_267, uncacheable_miss_ff, io.ifc_fetch_uncacheable_bf) @[el2_ifu_mem_ctl.scala 291:84] + node uncacheable_miss_in = mux(_T_266, uncacheable_miss_scnd_ff, _T_268) @[el2_ifu_mem_ctl.scala 291:32] + node _T_269 = bits(scnd_miss_req, 0, 0) @[el2_ifu_mem_ctl.scala 292:34] + node _T_270 = bits(sel_hold_imb, 0, 0) @[el2_ifu_mem_ctl.scala 292:72] + node _T_271 = mux(_T_270, imb_ff, io.ifc_fetch_addr_bf) @[el2_ifu_mem_ctl.scala 292:58] + node imb_in = mux(_T_269, imb_scnd_ff, _T_271) @[el2_ifu_mem_ctl.scala 292:19] + wire ifu_wr_cumulative_err_data : UInt<1> + ifu_wr_cumulative_err_data <= UInt<1>("h00") + node _T_272 = bits(imb_ff, 11, 5) @[el2_ifu_mem_ctl.scala 294:38] + node _T_273 = bits(imb_scnd_ff, 11, 5) @[el2_ifu_mem_ctl.scala 294:93] + node _T_274 = eq(_T_272, _T_273) @[el2_ifu_mem_ctl.scala 294:79] + node _T_275 = and(_T_274, scnd_miss_req) @[el2_ifu_mem_ctl.scala 294:135] + node _T_276 = eq(ifu_wr_cumulative_err_data, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 294:153] + node scnd_miss_index_match = and(_T_275, _T_276) @[el2_ifu_mem_ctl.scala 294:151] + wire way_status_mb_ff : UInt<1> + way_status_mb_ff <= UInt<1>("h00") + wire way_status_rep_new : UInt<1> + way_status_rep_new <= UInt<1>("h00") + node _T_277 = eq(scnd_miss_index_match, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 297:47] + node _T_278 = and(scnd_miss_req, _T_277) @[el2_ifu_mem_ctl.scala 297:45] + node _T_279 = bits(_T_278, 0, 0) @[el2_ifu_mem_ctl.scala 297:71] + node _T_280 = and(scnd_miss_req, scnd_miss_index_match) @[el2_ifu_mem_ctl.scala 298:24] + node _T_281 = bits(_T_280, 0, 0) @[el2_ifu_mem_ctl.scala 298:50] + node _T_282 = bits(miss_pending, 0, 0) @[el2_ifu_mem_ctl.scala 299:24] + node _T_283 = mux(_T_282, way_status_mb_ff, way_status) @[el2_ifu_mem_ctl.scala 299:10] + node _T_284 = mux(_T_281, way_status_rep_new, _T_283) @[el2_ifu_mem_ctl.scala 298:8] + node way_status_mb_in = mux(_T_279, way_status_mb_scnd_ff, _T_284) @[el2_ifu_mem_ctl.scala 297:29] + wire replace_way_mb_any : UInt<1>[2] @[el2_ifu_mem_ctl.scala 300:32] + wire tagv_mb_ff : UInt<2> + tagv_mb_ff <= UInt<1>("h00") + node _T_285 = bits(scnd_miss_req, 0, 0) @[el2_ifu_mem_ctl.scala 302:38] + node _T_286 = bits(scnd_miss_index_match, 0, 0) @[Bitwise.scala 72:15] + node _T_287 = mux(_T_286, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_288 = cat(replace_way_mb_any[1], replace_way_mb_any[0]) @[Cat.scala 29:58] + node _T_289 = and(_T_287, _T_288) @[el2_ifu_mem_ctl.scala 302:110] + node _T_290 = or(tagv_mb_scnd_ff, _T_289) @[el2_ifu_mem_ctl.scala 302:62] + node _T_291 = bits(miss_pending, 0, 0) @[el2_ifu_mem_ctl.scala 303:22] + node _T_292 = eq(reset_all_tags, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 303:82] + node _T_293 = bits(_T_292, 0, 0) @[Bitwise.scala 72:15] + node _T_294 = mux(_T_293, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_295 = and(io.ic_tag_valid, _T_294) @[el2_ifu_mem_ctl.scala 303:58] + node _T_296 = mux(_T_291, tagv_mb_ff, _T_295) @[el2_ifu_mem_ctl.scala 303:8] + node tagv_mb_in = mux(_T_285, _T_290, _T_296) @[el2_ifu_mem_ctl.scala 302:23] + wire scnd_miss_req_q : UInt<1> + scnd_miss_req_q <= UInt<1>("h00") + wire reset_ic_ff : UInt<1> + reset_ic_ff <= UInt<1>("h00") + node _T_297 = eq(scnd_miss_req_q, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 306:36] + node _T_298 = and(miss_pending, _T_297) @[el2_ifu_mem_ctl.scala 306:34] + node _T_299 = or(reset_all_tags, reset_ic_ff) @[el2_ifu_mem_ctl.scala 306:72] + node reset_ic_in = and(_T_298, _T_299) @[el2_ifu_mem_ctl.scala 306:53] + reg _T_300 : UInt, io.free_clk @[el2_ifu_mem_ctl.scala 307:48] + _T_300 <= reset_ic_in @[el2_ifu_mem_ctl.scala 307:48] + reset_ic_ff <= _T_300 @[el2_ifu_mem_ctl.scala 307:15] + reg fetch_uncacheable_ff : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 308:62] + fetch_uncacheable_ff <= io.ifc_fetch_uncacheable_bf @[el2_ifu_mem_ctl.scala 308:62] + reg _T_301 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 309:63] + _T_301 <= io.ifc_fetch_addr_bf @[el2_ifu_mem_ctl.scala 309:63] + ifu_fetch_addr_int_f <= _T_301 @[el2_ifu_mem_ctl.scala 309:24] + node vaddr_f = bits(ifu_fetch_addr_int_f, 4, 0) @[el2_ifu_mem_ctl.scala 310:37] + reg _T_302 : UInt<1>, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 311:62] + _T_302 <= uncacheable_miss_in @[el2_ifu_mem_ctl.scala 311:62] + uncacheable_miss_ff <= _T_302 @[el2_ifu_mem_ctl.scala 311:23] + reg _T_303 : UInt, rvclkhdr_2.io.l1clk @[el2_ifu_mem_ctl.scala 312:49] + _T_303 <= imb_in @[el2_ifu_mem_ctl.scala 312:49] + imb_ff <= _T_303 @[el2_ifu_mem_ctl.scala 312:10] + wire miss_addr : UInt<26> + miss_addr <= UInt<1>("h00") + node _T_304 = eq(miss_pending, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 314:26] + node _T_305 = bits(imb_ff, 30, 5) @[el2_ifu_mem_ctl.scala 314:47] + node _T_306 = bits(scnd_miss_req_q, 0, 0) @[el2_ifu_mem_ctl.scala 315:25] + node _T_307 = bits(imb_scnd_ff, 30, 5) @[el2_ifu_mem_ctl.scala 315:44] + node _T_308 = mux(_T_306, _T_307, miss_addr) @[el2_ifu_mem_ctl.scala 315:8] + node miss_addr_in = mux(_T_304, _T_305, _T_308) @[el2_ifu_mem_ctl.scala 314:25] + node _T_309 = or(bus_ifu_bus_clk_en, ic_act_miss_f) @[el2_ifu_mem_ctl.scala 316:57] + node _T_310 = or(_T_309, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 316:73] + inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 483:22] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_3.io.en <= _T_310 @[el2_lib.scala 485:16] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + reg _T_311 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 317:48] + _T_311 <= miss_addr_in @[el2_ifu_mem_ctl.scala 317:48] + miss_addr <= _T_311 @[el2_ifu_mem_ctl.scala 317:13] + reg _T_312 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 318:59] + _T_312 <= way_status_mb_in @[el2_ifu_mem_ctl.scala 318:59] + way_status_mb_ff <= _T_312 @[el2_ifu_mem_ctl.scala 318:20] + reg _T_313 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 319:53] + _T_313 <= tagv_mb_in @[el2_ifu_mem_ctl.scala 319:53] + tagv_mb_ff <= _T_313 @[el2_ifu_mem_ctl.scala 319:14] + wire stream_miss_f : UInt<1> + stream_miss_f <= UInt<1>("h00") + node _T_314 = eq(miss_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 321:68] + node _T_315 = and(_T_314, flush_final_f) @[el2_ifu_mem_ctl.scala 321:87] + node _T_316 = eq(_T_315, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 321:55] + node _T_317 = and(io.ifc_fetch_req_bf, _T_316) @[el2_ifu_mem_ctl.scala 321:53] + node _T_318 = eq(stream_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 321:106] + node ifc_fetch_req_qual_bf = and(_T_317, _T_318) @[el2_ifu_mem_ctl.scala 321:104] + reg ifc_fetch_req_f_raw : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 322:61] + ifc_fetch_req_f_raw <= ifc_fetch_req_qual_bf @[el2_ifu_mem_ctl.scala 322:61] + node _T_319 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 323:44] + node _T_320 = and(ifc_fetch_req_f_raw, _T_319) @[el2_ifu_mem_ctl.scala 323:42] + ifc_fetch_req_f <= _T_320 @[el2_ifu_mem_ctl.scala 323:19] + reg _T_321 : UInt<1>, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 324:60] + _T_321 <= io.ifc_iccm_access_bf @[el2_ifu_mem_ctl.scala 324:60] + ifc_iccm_access_f <= _T_321 @[el2_ifu_mem_ctl.scala 324:21] + wire ifc_region_acc_fault_final_bf : UInt<1> + ifc_region_acc_fault_final_bf <= UInt<1>("h00") + reg _T_322 : UInt<1>, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 326:71] + _T_322 <= ifc_region_acc_fault_final_bf @[el2_ifu_mem_ctl.scala 326:71] + ifc_region_acc_fault_final_f <= _T_322 @[el2_ifu_mem_ctl.scala 326:32] + reg ifc_region_acc_fault_f : UInt<1>, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 327:68] + ifc_region_acc_fault_f <= io.ifc_region_acc_fault_bf @[el2_ifu_mem_ctl.scala 327:68] + node ifu_ic_req_addr_f = cat(miss_addr, bus_rd_addr_count) @[Cat.scala 29:58] + node _T_323 = eq(miss_state, UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 329:38] + node _T_324 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 329:68] + node _T_325 = or(_T_323, _T_324) @[el2_ifu_mem_ctl.scala 329:55] + node _T_326 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 329:103] + node _T_327 = eq(_T_326, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 329:84] + node _T_328 = and(_T_325, _T_327) @[el2_ifu_mem_ctl.scala 329:82] + node _T_329 = eq(miss_pending, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 329:119] + node _T_330 = or(_T_328, _T_329) @[el2_ifu_mem_ctl.scala 329:117] + io.ifu_ic_mb_empty <= _T_330 @[el2_ifu_mem_ctl.scala 329:22] + node _T_331 = eq(miss_state, UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 330:40] + io.ifu_miss_state_idle <= _T_331 @[el2_ifu_mem_ctl.scala 330:26] + wire write_ic_16_bytes : UInt<1> + write_ic_16_bytes <= UInt<1>("h00") + wire reset_tag_valid_for_miss : UInt<1> + reset_tag_valid_for_miss <= UInt<1>("h00") + node _T_332 = and(miss_pending, write_ic_16_bytes) @[el2_ifu_mem_ctl.scala 333:35] + node _T_333 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 333:57] + node _T_334 = and(_T_332, _T_333) @[el2_ifu_mem_ctl.scala 333:55] + node sel_mb_addr = or(_T_334, reset_tag_valid_for_miss) @[el2_ifu_mem_ctl.scala 333:79] + node _T_335 = bits(imb_ff, 30, 5) @[el2_ifu_mem_ctl.scala 334:63] + node _T_336 = bits(imb_ff, 1, 0) @[el2_ifu_mem_ctl.scala 334:119] + node _T_337 = cat(_T_335, ic_wr_addr_bits_hi_3) @[Cat.scala 29:58] + node _T_338 = cat(_T_337, _T_336) @[Cat.scala 29:58] + node _T_339 = eq(sel_mb_addr, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 335:5] + node _T_340 = mux(sel_mb_addr, _T_338, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_341 = mux(_T_339, io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_342 = or(_T_340, _T_341) @[Mux.scala 27:72] + wire ifu_ic_rw_int_addr : UInt<31> @[Mux.scala 27:72] + ifu_ic_rw_int_addr <= _T_342 @[Mux.scala 27:72] + wire bus_ifu_wr_en_ff_q : UInt<1> + bus_ifu_wr_en_ff_q <= UInt<1>("h00") + node _T_343 = and(miss_pending, write_ic_16_bytes) @[el2_ifu_mem_ctl.scala 337:41] + node _T_344 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 337:63] + node _T_345 = and(_T_343, _T_344) @[el2_ifu_mem_ctl.scala 337:61] + node _T_346 = and(_T_345, last_beat) @[el2_ifu_mem_ctl.scala 337:84] + node sel_mb_status_addr = and(_T_346, bus_ifu_wr_en_ff_q) @[el2_ifu_mem_ctl.scala 337:96] + node _T_347 = bits(imb_ff, 30, 5) @[el2_ifu_mem_ctl.scala 338:62] + node _T_348 = bits(imb_ff, 1, 0) @[el2_ifu_mem_ctl.scala 338:116] + node _T_349 = cat(_T_347, ic_wr_addr_bits_hi_3) @[Cat.scala 29:58] + node _T_350 = cat(_T_349, _T_348) @[Cat.scala 29:58] + node ifu_status_wr_addr = mux(sel_mb_status_addr, _T_350, ifu_fetch_addr_int_f) @[el2_ifu_mem_ctl.scala 338:31] + io.ic_rw_addr <= ifu_ic_rw_int_addr @[el2_ifu_mem_ctl.scala 339:17] + reg _T_351 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 340:51] + _T_351 <= sel_mb_addr @[el2_ifu_mem_ctl.scala 340:51] + sel_mb_addr_ff <= _T_351 @[el2_ifu_mem_ctl.scala 340:18] + wire ifu_bus_rdata_ff : UInt<64> + ifu_bus_rdata_ff <= UInt<1>("h00") + wire ic_miss_buff_half : UInt<64> + ic_miss_buff_half <= UInt<1>("h00") + wire _T_352 : UInt<1>[35] @[el2_lib.scala 395:18] + wire _T_353 : UInt<1>[35] @[el2_lib.scala 396:18] + wire _T_354 : UInt<1>[35] @[el2_lib.scala 397:18] + wire _T_355 : UInt<1>[31] @[el2_lib.scala 398:18] + wire _T_356 : UInt<1>[31] @[el2_lib.scala 399:18] + wire _T_357 : UInt<1>[31] @[el2_lib.scala 400:18] + wire _T_358 : UInt<1>[7] @[el2_lib.scala 401:18] + node _T_359 = bits(ifu_bus_rdata_ff, 0, 0) @[el2_lib.scala 408:36] + _T_352[0] <= _T_359 @[el2_lib.scala 408:30] + node _T_360 = bits(ifu_bus_rdata_ff, 0, 0) @[el2_lib.scala 409:36] + _T_353[0] <= _T_360 @[el2_lib.scala 409:30] + node _T_361 = bits(ifu_bus_rdata_ff, 1, 1) @[el2_lib.scala 408:36] + _T_352[1] <= _T_361 @[el2_lib.scala 408:30] + node _T_362 = bits(ifu_bus_rdata_ff, 1, 1) @[el2_lib.scala 410:36] + _T_354[0] <= _T_362 @[el2_lib.scala 410:30] + node _T_363 = bits(ifu_bus_rdata_ff, 2, 2) @[el2_lib.scala 409:36] + _T_353[1] <= _T_363 @[el2_lib.scala 409:30] + node _T_364 = bits(ifu_bus_rdata_ff, 2, 2) @[el2_lib.scala 410:36] + _T_354[1] <= _T_364 @[el2_lib.scala 410:30] + node _T_365 = bits(ifu_bus_rdata_ff, 3, 3) @[el2_lib.scala 408:36] + _T_352[2] <= _T_365 @[el2_lib.scala 408:30] + node _T_366 = bits(ifu_bus_rdata_ff, 3, 3) @[el2_lib.scala 409:36] + _T_353[2] <= _T_366 @[el2_lib.scala 409:30] + node _T_367 = bits(ifu_bus_rdata_ff, 3, 3) @[el2_lib.scala 410:36] + _T_354[2] <= _T_367 @[el2_lib.scala 410:30] + node _T_368 = bits(ifu_bus_rdata_ff, 4, 4) @[el2_lib.scala 408:36] + _T_352[3] <= _T_368 @[el2_lib.scala 408:30] + node _T_369 = bits(ifu_bus_rdata_ff, 4, 4) @[el2_lib.scala 411:36] + _T_355[0] <= _T_369 @[el2_lib.scala 411:30] + node _T_370 = bits(ifu_bus_rdata_ff, 5, 5) @[el2_lib.scala 409:36] + _T_353[3] <= _T_370 @[el2_lib.scala 409:30] + node _T_371 = bits(ifu_bus_rdata_ff, 5, 5) @[el2_lib.scala 411:36] + _T_355[1] <= _T_371 @[el2_lib.scala 411:30] + node _T_372 = bits(ifu_bus_rdata_ff, 6, 6) @[el2_lib.scala 408:36] + _T_352[4] <= _T_372 @[el2_lib.scala 408:30] + node _T_373 = bits(ifu_bus_rdata_ff, 6, 6) @[el2_lib.scala 409:36] + _T_353[4] <= _T_373 @[el2_lib.scala 409:30] + node _T_374 = bits(ifu_bus_rdata_ff, 6, 6) @[el2_lib.scala 411:36] + _T_355[2] <= _T_374 @[el2_lib.scala 411:30] + node _T_375 = bits(ifu_bus_rdata_ff, 7, 7) @[el2_lib.scala 410:36] + _T_354[3] <= _T_375 @[el2_lib.scala 410:30] + node _T_376 = bits(ifu_bus_rdata_ff, 7, 7) @[el2_lib.scala 411:36] + _T_355[3] <= _T_376 @[el2_lib.scala 411:30] + node _T_377 = bits(ifu_bus_rdata_ff, 8, 8) @[el2_lib.scala 408:36] + _T_352[5] <= _T_377 @[el2_lib.scala 408:30] + node _T_378 = bits(ifu_bus_rdata_ff, 8, 8) @[el2_lib.scala 410:36] + _T_354[4] <= _T_378 @[el2_lib.scala 410:30] + node _T_379 = bits(ifu_bus_rdata_ff, 8, 8) @[el2_lib.scala 411:36] + _T_355[4] <= _T_379 @[el2_lib.scala 411:30] + node _T_380 = bits(ifu_bus_rdata_ff, 9, 9) @[el2_lib.scala 409:36] + _T_353[5] <= _T_380 @[el2_lib.scala 409:30] + node _T_381 = bits(ifu_bus_rdata_ff, 9, 9) @[el2_lib.scala 410:36] + _T_354[5] <= _T_381 @[el2_lib.scala 410:30] + node _T_382 = bits(ifu_bus_rdata_ff, 9, 9) @[el2_lib.scala 411:36] + _T_355[5] <= _T_382 @[el2_lib.scala 411:30] + node _T_383 = bits(ifu_bus_rdata_ff, 10, 10) @[el2_lib.scala 408:36] + _T_352[6] <= _T_383 @[el2_lib.scala 408:30] + node _T_384 = bits(ifu_bus_rdata_ff, 10, 10) @[el2_lib.scala 409:36] + _T_353[6] <= _T_384 @[el2_lib.scala 409:30] + node _T_385 = bits(ifu_bus_rdata_ff, 10, 10) @[el2_lib.scala 410:36] + _T_354[6] <= _T_385 @[el2_lib.scala 410:30] + node _T_386 = bits(ifu_bus_rdata_ff, 10, 10) @[el2_lib.scala 411:36] + _T_355[6] <= _T_386 @[el2_lib.scala 411:30] + node _T_387 = bits(ifu_bus_rdata_ff, 11, 11) @[el2_lib.scala 408:36] + _T_352[7] <= _T_387 @[el2_lib.scala 408:30] + node _T_388 = bits(ifu_bus_rdata_ff, 11, 11) @[el2_lib.scala 412:36] + _T_356[0] <= _T_388 @[el2_lib.scala 412:30] + node _T_389 = bits(ifu_bus_rdata_ff, 12, 12) @[el2_lib.scala 409:36] + _T_353[7] <= _T_389 @[el2_lib.scala 409:30] + node _T_390 = bits(ifu_bus_rdata_ff, 12, 12) @[el2_lib.scala 412:36] + _T_356[1] <= _T_390 @[el2_lib.scala 412:30] + node _T_391 = bits(ifu_bus_rdata_ff, 13, 13) @[el2_lib.scala 408:36] + _T_352[8] <= _T_391 @[el2_lib.scala 408:30] + node _T_392 = bits(ifu_bus_rdata_ff, 13, 13) @[el2_lib.scala 409:36] + _T_353[8] <= _T_392 @[el2_lib.scala 409:30] + node _T_393 = bits(ifu_bus_rdata_ff, 13, 13) @[el2_lib.scala 412:36] + _T_356[2] <= _T_393 @[el2_lib.scala 412:30] + node _T_394 = bits(ifu_bus_rdata_ff, 14, 14) @[el2_lib.scala 410:36] + _T_354[7] <= _T_394 @[el2_lib.scala 410:30] + node _T_395 = bits(ifu_bus_rdata_ff, 14, 14) @[el2_lib.scala 412:36] + _T_356[3] <= _T_395 @[el2_lib.scala 412:30] + node _T_396 = bits(ifu_bus_rdata_ff, 15, 15) @[el2_lib.scala 408:36] + _T_352[9] <= _T_396 @[el2_lib.scala 408:30] + node _T_397 = bits(ifu_bus_rdata_ff, 15, 15) @[el2_lib.scala 410:36] + _T_354[8] <= _T_397 @[el2_lib.scala 410:30] + node _T_398 = bits(ifu_bus_rdata_ff, 15, 15) @[el2_lib.scala 412:36] + _T_356[4] <= _T_398 @[el2_lib.scala 412:30] + node _T_399 = bits(ifu_bus_rdata_ff, 16, 16) @[el2_lib.scala 409:36] + _T_353[9] <= _T_399 @[el2_lib.scala 409:30] + node _T_400 = bits(ifu_bus_rdata_ff, 16, 16) @[el2_lib.scala 410:36] + _T_354[9] <= _T_400 @[el2_lib.scala 410:30] + node _T_401 = bits(ifu_bus_rdata_ff, 16, 16) @[el2_lib.scala 412:36] + _T_356[5] <= _T_401 @[el2_lib.scala 412:30] + node _T_402 = bits(ifu_bus_rdata_ff, 17, 17) @[el2_lib.scala 408:36] + _T_352[10] <= _T_402 @[el2_lib.scala 408:30] + node _T_403 = bits(ifu_bus_rdata_ff, 17, 17) @[el2_lib.scala 409:36] + _T_353[10] <= _T_403 @[el2_lib.scala 409:30] + node _T_404 = bits(ifu_bus_rdata_ff, 17, 17) @[el2_lib.scala 410:36] + _T_354[10] <= _T_404 @[el2_lib.scala 410:30] + node _T_405 = bits(ifu_bus_rdata_ff, 17, 17) @[el2_lib.scala 412:36] + _T_356[6] <= _T_405 @[el2_lib.scala 412:30] + node _T_406 = bits(ifu_bus_rdata_ff, 18, 18) @[el2_lib.scala 411:36] + _T_355[7] <= _T_406 @[el2_lib.scala 411:30] + node _T_407 = bits(ifu_bus_rdata_ff, 18, 18) @[el2_lib.scala 412:36] + _T_356[7] <= _T_407 @[el2_lib.scala 412:30] + node _T_408 = bits(ifu_bus_rdata_ff, 19, 19) @[el2_lib.scala 408:36] + _T_352[11] <= _T_408 @[el2_lib.scala 408:30] + node _T_409 = bits(ifu_bus_rdata_ff, 19, 19) @[el2_lib.scala 411:36] + _T_355[8] <= _T_409 @[el2_lib.scala 411:30] + node _T_410 = bits(ifu_bus_rdata_ff, 19, 19) @[el2_lib.scala 412:36] + _T_356[8] <= _T_410 @[el2_lib.scala 412:30] + node _T_411 = bits(ifu_bus_rdata_ff, 20, 20) @[el2_lib.scala 409:36] + _T_353[11] <= _T_411 @[el2_lib.scala 409:30] + node _T_412 = bits(ifu_bus_rdata_ff, 20, 20) @[el2_lib.scala 411:36] + _T_355[9] <= _T_412 @[el2_lib.scala 411:30] + node _T_413 = bits(ifu_bus_rdata_ff, 20, 20) @[el2_lib.scala 412:36] + _T_356[9] <= _T_413 @[el2_lib.scala 412:30] + node _T_414 = bits(ifu_bus_rdata_ff, 21, 21) @[el2_lib.scala 408:36] + _T_352[12] <= _T_414 @[el2_lib.scala 408:30] + node _T_415 = bits(ifu_bus_rdata_ff, 21, 21) @[el2_lib.scala 409:36] + _T_353[12] <= _T_415 @[el2_lib.scala 409:30] + node _T_416 = bits(ifu_bus_rdata_ff, 21, 21) @[el2_lib.scala 411:36] + _T_355[10] <= _T_416 @[el2_lib.scala 411:30] + node _T_417 = bits(ifu_bus_rdata_ff, 21, 21) @[el2_lib.scala 412:36] + _T_356[10] <= _T_417 @[el2_lib.scala 412:30] + node _T_418 = bits(ifu_bus_rdata_ff, 22, 22) @[el2_lib.scala 410:36] + _T_354[11] <= _T_418 @[el2_lib.scala 410:30] + node _T_419 = bits(ifu_bus_rdata_ff, 22, 22) @[el2_lib.scala 411:36] + _T_355[11] <= _T_419 @[el2_lib.scala 411:30] + node _T_420 = bits(ifu_bus_rdata_ff, 22, 22) @[el2_lib.scala 412:36] + _T_356[11] <= _T_420 @[el2_lib.scala 412:30] + node _T_421 = bits(ifu_bus_rdata_ff, 23, 23) @[el2_lib.scala 408:36] + _T_352[13] <= _T_421 @[el2_lib.scala 408:30] + node _T_422 = bits(ifu_bus_rdata_ff, 23, 23) @[el2_lib.scala 410:36] + _T_354[12] <= _T_422 @[el2_lib.scala 410:30] + node _T_423 = bits(ifu_bus_rdata_ff, 23, 23) @[el2_lib.scala 411:36] + _T_355[12] <= _T_423 @[el2_lib.scala 411:30] + node _T_424 = bits(ifu_bus_rdata_ff, 23, 23) @[el2_lib.scala 412:36] + _T_356[12] <= _T_424 @[el2_lib.scala 412:30] + node _T_425 = bits(ifu_bus_rdata_ff, 24, 24) @[el2_lib.scala 409:36] + _T_353[13] <= _T_425 @[el2_lib.scala 409:30] + node _T_426 = bits(ifu_bus_rdata_ff, 24, 24) @[el2_lib.scala 410:36] + _T_354[13] <= _T_426 @[el2_lib.scala 410:30] + node _T_427 = bits(ifu_bus_rdata_ff, 24, 24) @[el2_lib.scala 411:36] + _T_355[13] <= _T_427 @[el2_lib.scala 411:30] + node _T_428 = bits(ifu_bus_rdata_ff, 24, 24) @[el2_lib.scala 412:36] + _T_356[13] <= _T_428 @[el2_lib.scala 412:30] + node _T_429 = bits(ifu_bus_rdata_ff, 25, 25) @[el2_lib.scala 408:36] + _T_352[14] <= _T_429 @[el2_lib.scala 408:30] + node _T_430 = bits(ifu_bus_rdata_ff, 25, 25) @[el2_lib.scala 409:36] + _T_353[14] <= _T_430 @[el2_lib.scala 409:30] + node _T_431 = bits(ifu_bus_rdata_ff, 25, 25) @[el2_lib.scala 410:36] + _T_354[14] <= _T_431 @[el2_lib.scala 410:30] + node _T_432 = bits(ifu_bus_rdata_ff, 25, 25) @[el2_lib.scala 411:36] + _T_355[14] <= _T_432 @[el2_lib.scala 411:30] + node _T_433 = bits(ifu_bus_rdata_ff, 25, 25) @[el2_lib.scala 412:36] + _T_356[14] <= _T_433 @[el2_lib.scala 412:30] + node _T_434 = bits(ifu_bus_rdata_ff, 26, 26) @[el2_lib.scala 408:36] + _T_352[15] <= _T_434 @[el2_lib.scala 408:30] + node _T_435 = bits(ifu_bus_rdata_ff, 26, 26) @[el2_lib.scala 413:36] + _T_357[0] <= _T_435 @[el2_lib.scala 413:30] + node _T_436 = bits(ifu_bus_rdata_ff, 27, 27) @[el2_lib.scala 409:36] + _T_353[15] <= _T_436 @[el2_lib.scala 409:30] + node _T_437 = bits(ifu_bus_rdata_ff, 27, 27) @[el2_lib.scala 413:36] + _T_357[1] <= _T_437 @[el2_lib.scala 413:30] + node _T_438 = bits(ifu_bus_rdata_ff, 28, 28) @[el2_lib.scala 408:36] + _T_352[16] <= _T_438 @[el2_lib.scala 408:30] + node _T_439 = bits(ifu_bus_rdata_ff, 28, 28) @[el2_lib.scala 409:36] + _T_353[16] <= _T_439 @[el2_lib.scala 409:30] + node _T_440 = bits(ifu_bus_rdata_ff, 28, 28) @[el2_lib.scala 413:36] + _T_357[2] <= _T_440 @[el2_lib.scala 413:30] + node _T_441 = bits(ifu_bus_rdata_ff, 29, 29) @[el2_lib.scala 410:36] + _T_354[15] <= _T_441 @[el2_lib.scala 410:30] + node _T_442 = bits(ifu_bus_rdata_ff, 29, 29) @[el2_lib.scala 413:36] + _T_357[3] <= _T_442 @[el2_lib.scala 413:30] + node _T_443 = bits(ifu_bus_rdata_ff, 30, 30) @[el2_lib.scala 408:36] + _T_352[17] <= _T_443 @[el2_lib.scala 408:30] + node _T_444 = bits(ifu_bus_rdata_ff, 30, 30) @[el2_lib.scala 410:36] + _T_354[16] <= _T_444 @[el2_lib.scala 410:30] + node _T_445 = bits(ifu_bus_rdata_ff, 30, 30) @[el2_lib.scala 413:36] + _T_357[4] <= _T_445 @[el2_lib.scala 413:30] + node _T_446 = bits(ifu_bus_rdata_ff, 31, 31) @[el2_lib.scala 409:36] + _T_353[17] <= _T_446 @[el2_lib.scala 409:30] + node _T_447 = bits(ifu_bus_rdata_ff, 31, 31) @[el2_lib.scala 410:36] + _T_354[17] <= _T_447 @[el2_lib.scala 410:30] + node _T_448 = bits(ifu_bus_rdata_ff, 31, 31) @[el2_lib.scala 413:36] + _T_357[5] <= _T_448 @[el2_lib.scala 413:30] + node _T_449 = bits(ifu_bus_rdata_ff, 32, 32) @[el2_lib.scala 408:36] + _T_352[18] <= _T_449 @[el2_lib.scala 408:30] + node _T_450 = bits(ifu_bus_rdata_ff, 32, 32) @[el2_lib.scala 409:36] + _T_353[18] <= _T_450 @[el2_lib.scala 409:30] + node _T_451 = bits(ifu_bus_rdata_ff, 32, 32) @[el2_lib.scala 410:36] + _T_354[18] <= _T_451 @[el2_lib.scala 410:30] + node _T_452 = bits(ifu_bus_rdata_ff, 32, 32) @[el2_lib.scala 413:36] + _T_357[6] <= _T_452 @[el2_lib.scala 413:30] + node _T_453 = bits(ifu_bus_rdata_ff, 33, 33) @[el2_lib.scala 411:36] + _T_355[15] <= _T_453 @[el2_lib.scala 411:30] + node _T_454 = bits(ifu_bus_rdata_ff, 33, 33) @[el2_lib.scala 413:36] + _T_357[7] <= _T_454 @[el2_lib.scala 413:30] + node _T_455 = bits(ifu_bus_rdata_ff, 34, 34) @[el2_lib.scala 408:36] + _T_352[19] <= _T_455 @[el2_lib.scala 408:30] + node _T_456 = bits(ifu_bus_rdata_ff, 34, 34) @[el2_lib.scala 411:36] + _T_355[16] <= _T_456 @[el2_lib.scala 411:30] + node _T_457 = bits(ifu_bus_rdata_ff, 34, 34) @[el2_lib.scala 413:36] + _T_357[8] <= _T_457 @[el2_lib.scala 413:30] + node _T_458 = bits(ifu_bus_rdata_ff, 35, 35) @[el2_lib.scala 409:36] + _T_353[19] <= _T_458 @[el2_lib.scala 409:30] + node _T_459 = bits(ifu_bus_rdata_ff, 35, 35) @[el2_lib.scala 411:36] + _T_355[17] <= _T_459 @[el2_lib.scala 411:30] + node _T_460 = bits(ifu_bus_rdata_ff, 35, 35) @[el2_lib.scala 413:36] + _T_357[9] <= _T_460 @[el2_lib.scala 413:30] + node _T_461 = bits(ifu_bus_rdata_ff, 36, 36) @[el2_lib.scala 408:36] + _T_352[20] <= _T_461 @[el2_lib.scala 408:30] + node _T_462 = bits(ifu_bus_rdata_ff, 36, 36) @[el2_lib.scala 409:36] + _T_353[20] <= _T_462 @[el2_lib.scala 409:30] + node _T_463 = bits(ifu_bus_rdata_ff, 36, 36) @[el2_lib.scala 411:36] + _T_355[18] <= _T_463 @[el2_lib.scala 411:30] + node _T_464 = bits(ifu_bus_rdata_ff, 36, 36) @[el2_lib.scala 413:36] + _T_357[10] <= _T_464 @[el2_lib.scala 413:30] + node _T_465 = bits(ifu_bus_rdata_ff, 37, 37) @[el2_lib.scala 410:36] + _T_354[19] <= _T_465 @[el2_lib.scala 410:30] + node _T_466 = bits(ifu_bus_rdata_ff, 37, 37) @[el2_lib.scala 411:36] + _T_355[19] <= _T_466 @[el2_lib.scala 411:30] + node _T_467 = bits(ifu_bus_rdata_ff, 37, 37) @[el2_lib.scala 413:36] + _T_357[11] <= _T_467 @[el2_lib.scala 413:30] + node _T_468 = bits(ifu_bus_rdata_ff, 38, 38) @[el2_lib.scala 408:36] + _T_352[21] <= _T_468 @[el2_lib.scala 408:30] + node _T_469 = bits(ifu_bus_rdata_ff, 38, 38) @[el2_lib.scala 410:36] + _T_354[20] <= _T_469 @[el2_lib.scala 410:30] + node _T_470 = bits(ifu_bus_rdata_ff, 38, 38) @[el2_lib.scala 411:36] + _T_355[20] <= _T_470 @[el2_lib.scala 411:30] + node _T_471 = bits(ifu_bus_rdata_ff, 38, 38) @[el2_lib.scala 413:36] + _T_357[12] <= _T_471 @[el2_lib.scala 413:30] + node _T_472 = bits(ifu_bus_rdata_ff, 39, 39) @[el2_lib.scala 409:36] + _T_353[21] <= _T_472 @[el2_lib.scala 409:30] + node _T_473 = bits(ifu_bus_rdata_ff, 39, 39) @[el2_lib.scala 410:36] + _T_354[21] <= _T_473 @[el2_lib.scala 410:30] + node _T_474 = bits(ifu_bus_rdata_ff, 39, 39) @[el2_lib.scala 411:36] + _T_355[21] <= _T_474 @[el2_lib.scala 411:30] + node _T_475 = bits(ifu_bus_rdata_ff, 39, 39) @[el2_lib.scala 413:36] + _T_357[13] <= _T_475 @[el2_lib.scala 413:30] + node _T_476 = bits(ifu_bus_rdata_ff, 40, 40) @[el2_lib.scala 408:36] + _T_352[22] <= _T_476 @[el2_lib.scala 408:30] + node _T_477 = bits(ifu_bus_rdata_ff, 40, 40) @[el2_lib.scala 409:36] + _T_353[22] <= _T_477 @[el2_lib.scala 409:30] + node _T_478 = bits(ifu_bus_rdata_ff, 40, 40) @[el2_lib.scala 410:36] + _T_354[22] <= _T_478 @[el2_lib.scala 410:30] + node _T_479 = bits(ifu_bus_rdata_ff, 40, 40) @[el2_lib.scala 411:36] + _T_355[22] <= _T_479 @[el2_lib.scala 411:30] + node _T_480 = bits(ifu_bus_rdata_ff, 40, 40) @[el2_lib.scala 413:36] + _T_357[14] <= _T_480 @[el2_lib.scala 413:30] + node _T_481 = bits(ifu_bus_rdata_ff, 41, 41) @[el2_lib.scala 412:36] + _T_356[15] <= _T_481 @[el2_lib.scala 412:30] + node _T_482 = bits(ifu_bus_rdata_ff, 41, 41) @[el2_lib.scala 413:36] + _T_357[15] <= _T_482 @[el2_lib.scala 413:30] + node _T_483 = bits(ifu_bus_rdata_ff, 42, 42) @[el2_lib.scala 408:36] + _T_352[23] <= _T_483 @[el2_lib.scala 408:30] + node _T_484 = bits(ifu_bus_rdata_ff, 42, 42) @[el2_lib.scala 412:36] + _T_356[16] <= _T_484 @[el2_lib.scala 412:30] + node _T_485 = bits(ifu_bus_rdata_ff, 42, 42) @[el2_lib.scala 413:36] + _T_357[16] <= _T_485 @[el2_lib.scala 413:30] + node _T_486 = bits(ifu_bus_rdata_ff, 43, 43) @[el2_lib.scala 409:36] + _T_353[23] <= _T_486 @[el2_lib.scala 409:30] + node _T_487 = bits(ifu_bus_rdata_ff, 43, 43) @[el2_lib.scala 412:36] + _T_356[17] <= _T_487 @[el2_lib.scala 412:30] + node _T_488 = bits(ifu_bus_rdata_ff, 43, 43) @[el2_lib.scala 413:36] + _T_357[17] <= _T_488 @[el2_lib.scala 413:30] + node _T_489 = bits(ifu_bus_rdata_ff, 44, 44) @[el2_lib.scala 408:36] + _T_352[24] <= _T_489 @[el2_lib.scala 408:30] + node _T_490 = bits(ifu_bus_rdata_ff, 44, 44) @[el2_lib.scala 409:36] + _T_353[24] <= _T_490 @[el2_lib.scala 409:30] + node _T_491 = bits(ifu_bus_rdata_ff, 44, 44) @[el2_lib.scala 412:36] + _T_356[18] <= _T_491 @[el2_lib.scala 412:30] + node _T_492 = bits(ifu_bus_rdata_ff, 44, 44) @[el2_lib.scala 413:36] + _T_357[18] <= _T_492 @[el2_lib.scala 413:30] + node _T_493 = bits(ifu_bus_rdata_ff, 45, 45) @[el2_lib.scala 410:36] + _T_354[23] <= _T_493 @[el2_lib.scala 410:30] + node _T_494 = bits(ifu_bus_rdata_ff, 45, 45) @[el2_lib.scala 412:36] + _T_356[19] <= _T_494 @[el2_lib.scala 412:30] + node _T_495 = bits(ifu_bus_rdata_ff, 45, 45) @[el2_lib.scala 413:36] + _T_357[19] <= _T_495 @[el2_lib.scala 413:30] + node _T_496 = bits(ifu_bus_rdata_ff, 46, 46) @[el2_lib.scala 408:36] + _T_352[25] <= _T_496 @[el2_lib.scala 408:30] + node _T_497 = bits(ifu_bus_rdata_ff, 46, 46) @[el2_lib.scala 410:36] + _T_354[24] <= _T_497 @[el2_lib.scala 410:30] + node _T_498 = bits(ifu_bus_rdata_ff, 46, 46) @[el2_lib.scala 412:36] + _T_356[20] <= _T_498 @[el2_lib.scala 412:30] + node _T_499 = bits(ifu_bus_rdata_ff, 46, 46) @[el2_lib.scala 413:36] + _T_357[20] <= _T_499 @[el2_lib.scala 413:30] + node _T_500 = bits(ifu_bus_rdata_ff, 47, 47) @[el2_lib.scala 409:36] + _T_353[25] <= _T_500 @[el2_lib.scala 409:30] + node _T_501 = bits(ifu_bus_rdata_ff, 47, 47) @[el2_lib.scala 410:36] + _T_354[25] <= _T_501 @[el2_lib.scala 410:30] + node _T_502 = bits(ifu_bus_rdata_ff, 47, 47) @[el2_lib.scala 412:36] + _T_356[21] <= _T_502 @[el2_lib.scala 412:30] + node _T_503 = bits(ifu_bus_rdata_ff, 47, 47) @[el2_lib.scala 413:36] + _T_357[21] <= _T_503 @[el2_lib.scala 413:30] + node _T_504 = bits(ifu_bus_rdata_ff, 48, 48) @[el2_lib.scala 408:36] + _T_352[26] <= _T_504 @[el2_lib.scala 408:30] + node _T_505 = bits(ifu_bus_rdata_ff, 48, 48) @[el2_lib.scala 409:36] + _T_353[26] <= _T_505 @[el2_lib.scala 409:30] + node _T_506 = bits(ifu_bus_rdata_ff, 48, 48) @[el2_lib.scala 410:36] + _T_354[26] <= _T_506 @[el2_lib.scala 410:30] + node _T_507 = bits(ifu_bus_rdata_ff, 48, 48) @[el2_lib.scala 412:36] + _T_356[22] <= _T_507 @[el2_lib.scala 412:30] + node _T_508 = bits(ifu_bus_rdata_ff, 48, 48) @[el2_lib.scala 413:36] + _T_357[22] <= _T_508 @[el2_lib.scala 413:30] + node _T_509 = bits(ifu_bus_rdata_ff, 49, 49) @[el2_lib.scala 411:36] + _T_355[23] <= _T_509 @[el2_lib.scala 411:30] + node _T_510 = bits(ifu_bus_rdata_ff, 49, 49) @[el2_lib.scala 412:36] + _T_356[23] <= _T_510 @[el2_lib.scala 412:30] + node _T_511 = bits(ifu_bus_rdata_ff, 49, 49) @[el2_lib.scala 413:36] + _T_357[23] <= _T_511 @[el2_lib.scala 413:30] + node _T_512 = bits(ifu_bus_rdata_ff, 50, 50) @[el2_lib.scala 408:36] + _T_352[27] <= _T_512 @[el2_lib.scala 408:30] + node _T_513 = bits(ifu_bus_rdata_ff, 50, 50) @[el2_lib.scala 411:36] + _T_355[24] <= _T_513 @[el2_lib.scala 411:30] + node _T_514 = bits(ifu_bus_rdata_ff, 50, 50) @[el2_lib.scala 412:36] + _T_356[24] <= _T_514 @[el2_lib.scala 412:30] + node _T_515 = bits(ifu_bus_rdata_ff, 50, 50) @[el2_lib.scala 413:36] + _T_357[24] <= _T_515 @[el2_lib.scala 413:30] + node _T_516 = bits(ifu_bus_rdata_ff, 51, 51) @[el2_lib.scala 409:36] + _T_353[27] <= _T_516 @[el2_lib.scala 409:30] + node _T_517 = bits(ifu_bus_rdata_ff, 51, 51) @[el2_lib.scala 411:36] + _T_355[25] <= _T_517 @[el2_lib.scala 411:30] + node _T_518 = bits(ifu_bus_rdata_ff, 51, 51) @[el2_lib.scala 412:36] + _T_356[25] <= _T_518 @[el2_lib.scala 412:30] + node _T_519 = bits(ifu_bus_rdata_ff, 51, 51) @[el2_lib.scala 413:36] + _T_357[25] <= _T_519 @[el2_lib.scala 413:30] + node _T_520 = bits(ifu_bus_rdata_ff, 52, 52) @[el2_lib.scala 408:36] + _T_352[28] <= _T_520 @[el2_lib.scala 408:30] + node _T_521 = bits(ifu_bus_rdata_ff, 52, 52) @[el2_lib.scala 409:36] + _T_353[28] <= _T_521 @[el2_lib.scala 409:30] + node _T_522 = bits(ifu_bus_rdata_ff, 52, 52) @[el2_lib.scala 411:36] + _T_355[26] <= _T_522 @[el2_lib.scala 411:30] + node _T_523 = bits(ifu_bus_rdata_ff, 52, 52) @[el2_lib.scala 412:36] + _T_356[26] <= _T_523 @[el2_lib.scala 412:30] + node _T_524 = bits(ifu_bus_rdata_ff, 52, 52) @[el2_lib.scala 413:36] + _T_357[26] <= _T_524 @[el2_lib.scala 413:30] + node _T_525 = bits(ifu_bus_rdata_ff, 53, 53) @[el2_lib.scala 410:36] + _T_354[27] <= _T_525 @[el2_lib.scala 410:30] + node _T_526 = bits(ifu_bus_rdata_ff, 53, 53) @[el2_lib.scala 411:36] + _T_355[27] <= _T_526 @[el2_lib.scala 411:30] + node _T_527 = bits(ifu_bus_rdata_ff, 53, 53) @[el2_lib.scala 412:36] + _T_356[27] <= _T_527 @[el2_lib.scala 412:30] + node _T_528 = bits(ifu_bus_rdata_ff, 53, 53) @[el2_lib.scala 413:36] + _T_357[27] <= _T_528 @[el2_lib.scala 413:30] + node _T_529 = bits(ifu_bus_rdata_ff, 54, 54) @[el2_lib.scala 408:36] + _T_352[29] <= _T_529 @[el2_lib.scala 408:30] + node _T_530 = bits(ifu_bus_rdata_ff, 54, 54) @[el2_lib.scala 410:36] + _T_354[28] <= _T_530 @[el2_lib.scala 410:30] + node _T_531 = bits(ifu_bus_rdata_ff, 54, 54) @[el2_lib.scala 411:36] + _T_355[28] <= _T_531 @[el2_lib.scala 411:30] + node _T_532 = bits(ifu_bus_rdata_ff, 54, 54) @[el2_lib.scala 412:36] + _T_356[28] <= _T_532 @[el2_lib.scala 412:30] + node _T_533 = bits(ifu_bus_rdata_ff, 54, 54) @[el2_lib.scala 413:36] + _T_357[28] <= _T_533 @[el2_lib.scala 413:30] + node _T_534 = bits(ifu_bus_rdata_ff, 55, 55) @[el2_lib.scala 409:36] + _T_353[29] <= _T_534 @[el2_lib.scala 409:30] + node _T_535 = bits(ifu_bus_rdata_ff, 55, 55) @[el2_lib.scala 410:36] + _T_354[29] <= _T_535 @[el2_lib.scala 410:30] + node _T_536 = bits(ifu_bus_rdata_ff, 55, 55) @[el2_lib.scala 411:36] + _T_355[29] <= _T_536 @[el2_lib.scala 411:30] + node _T_537 = bits(ifu_bus_rdata_ff, 55, 55) @[el2_lib.scala 412:36] + _T_356[29] <= _T_537 @[el2_lib.scala 412:30] + node _T_538 = bits(ifu_bus_rdata_ff, 55, 55) @[el2_lib.scala 413:36] + _T_357[29] <= _T_538 @[el2_lib.scala 413:30] + node _T_539 = bits(ifu_bus_rdata_ff, 56, 56) @[el2_lib.scala 408:36] + _T_352[30] <= _T_539 @[el2_lib.scala 408:30] + node _T_540 = bits(ifu_bus_rdata_ff, 56, 56) @[el2_lib.scala 409:36] + _T_353[30] <= _T_540 @[el2_lib.scala 409:30] + node _T_541 = bits(ifu_bus_rdata_ff, 56, 56) @[el2_lib.scala 410:36] + _T_354[30] <= _T_541 @[el2_lib.scala 410:30] + node _T_542 = bits(ifu_bus_rdata_ff, 56, 56) @[el2_lib.scala 411:36] + _T_355[30] <= _T_542 @[el2_lib.scala 411:30] + node _T_543 = bits(ifu_bus_rdata_ff, 56, 56) @[el2_lib.scala 412:36] + _T_356[30] <= _T_543 @[el2_lib.scala 412:30] + node _T_544 = bits(ifu_bus_rdata_ff, 56, 56) @[el2_lib.scala 413:36] + _T_357[30] <= _T_544 @[el2_lib.scala 413:30] + node _T_545 = bits(ifu_bus_rdata_ff, 57, 57) @[el2_lib.scala 408:36] + _T_352[31] <= _T_545 @[el2_lib.scala 408:30] + node _T_546 = bits(ifu_bus_rdata_ff, 57, 57) @[el2_lib.scala 414:36] + _T_358[0] <= _T_546 @[el2_lib.scala 414:30] + node _T_547 = bits(ifu_bus_rdata_ff, 58, 58) @[el2_lib.scala 409:36] + _T_353[31] <= _T_547 @[el2_lib.scala 409:30] + node _T_548 = bits(ifu_bus_rdata_ff, 58, 58) @[el2_lib.scala 414:36] + _T_358[1] <= _T_548 @[el2_lib.scala 414:30] + node _T_549 = bits(ifu_bus_rdata_ff, 59, 59) @[el2_lib.scala 408:36] + _T_352[32] <= _T_549 @[el2_lib.scala 408:30] + node _T_550 = bits(ifu_bus_rdata_ff, 59, 59) @[el2_lib.scala 409:36] + _T_353[32] <= _T_550 @[el2_lib.scala 409:30] + node _T_551 = bits(ifu_bus_rdata_ff, 59, 59) @[el2_lib.scala 414:36] + _T_358[2] <= _T_551 @[el2_lib.scala 414:30] + node _T_552 = bits(ifu_bus_rdata_ff, 60, 60) @[el2_lib.scala 410:36] + _T_354[31] <= _T_552 @[el2_lib.scala 410:30] + node _T_553 = bits(ifu_bus_rdata_ff, 60, 60) @[el2_lib.scala 414:36] + _T_358[3] <= _T_553 @[el2_lib.scala 414:30] + node _T_554 = bits(ifu_bus_rdata_ff, 61, 61) @[el2_lib.scala 408:36] + _T_352[33] <= _T_554 @[el2_lib.scala 408:30] + node _T_555 = bits(ifu_bus_rdata_ff, 61, 61) @[el2_lib.scala 410:36] + _T_354[32] <= _T_555 @[el2_lib.scala 410:30] + node _T_556 = bits(ifu_bus_rdata_ff, 61, 61) @[el2_lib.scala 414:36] + _T_358[4] <= _T_556 @[el2_lib.scala 414:30] + node _T_557 = bits(ifu_bus_rdata_ff, 62, 62) @[el2_lib.scala 409:36] + _T_353[33] <= _T_557 @[el2_lib.scala 409:30] + node _T_558 = bits(ifu_bus_rdata_ff, 62, 62) @[el2_lib.scala 410:36] + _T_354[33] <= _T_558 @[el2_lib.scala 410:30] + node _T_559 = bits(ifu_bus_rdata_ff, 62, 62) @[el2_lib.scala 414:36] + _T_358[5] <= _T_559 @[el2_lib.scala 414:30] + node _T_560 = bits(ifu_bus_rdata_ff, 63, 63) @[el2_lib.scala 408:36] + _T_352[34] <= _T_560 @[el2_lib.scala 408:30] + node _T_561 = bits(ifu_bus_rdata_ff, 63, 63) @[el2_lib.scala 409:36] + _T_353[34] <= _T_561 @[el2_lib.scala 409:30] + node _T_562 = bits(ifu_bus_rdata_ff, 63, 63) @[el2_lib.scala 410:36] + _T_354[34] <= _T_562 @[el2_lib.scala 410:30] + node _T_563 = bits(ifu_bus_rdata_ff, 63, 63) @[el2_lib.scala 414:36] + _T_358[6] <= _T_563 @[el2_lib.scala 414:30] + node _T_564 = cat(_T_358[2], _T_358[1]) @[el2_lib.scala 416:13] + node _T_565 = cat(_T_564, _T_358[0]) @[el2_lib.scala 416:13] + node _T_566 = cat(_T_358[4], _T_358[3]) @[el2_lib.scala 416:13] + node _T_567 = cat(_T_358[6], _T_358[5]) @[el2_lib.scala 416:13] + node _T_568 = cat(_T_567, _T_566) @[el2_lib.scala 416:13] + node _T_569 = cat(_T_568, _T_565) @[el2_lib.scala 416:13] + node _T_570 = xorr(_T_569) @[el2_lib.scala 416:20] + node _T_571 = cat(_T_357[2], _T_357[1]) @[el2_lib.scala 416:30] + node _T_572 = cat(_T_571, _T_357[0]) @[el2_lib.scala 416:30] + node _T_573 = cat(_T_357[4], _T_357[3]) @[el2_lib.scala 416:30] + node _T_574 = cat(_T_357[6], _T_357[5]) @[el2_lib.scala 416:30] + node _T_575 = cat(_T_574, _T_573) @[el2_lib.scala 416:30] + node _T_576 = cat(_T_575, _T_572) @[el2_lib.scala 416:30] + node _T_577 = cat(_T_357[8], _T_357[7]) @[el2_lib.scala 416:30] + node _T_578 = cat(_T_357[10], _T_357[9]) @[el2_lib.scala 416:30] + node _T_579 = cat(_T_578, _T_577) @[el2_lib.scala 416:30] + node _T_580 = cat(_T_357[12], _T_357[11]) @[el2_lib.scala 416:30] + node _T_581 = cat(_T_357[14], _T_357[13]) @[el2_lib.scala 416:30] + node _T_582 = cat(_T_581, _T_580) @[el2_lib.scala 416:30] + node _T_583 = cat(_T_582, _T_579) @[el2_lib.scala 416:30] + node _T_584 = cat(_T_583, _T_576) @[el2_lib.scala 416:30] + node _T_585 = cat(_T_357[16], _T_357[15]) @[el2_lib.scala 416:30] + node _T_586 = cat(_T_357[18], _T_357[17]) @[el2_lib.scala 416:30] + node _T_587 = cat(_T_586, _T_585) @[el2_lib.scala 416:30] + node _T_588 = cat(_T_357[20], _T_357[19]) @[el2_lib.scala 416:30] + node _T_589 = cat(_T_357[22], _T_357[21]) @[el2_lib.scala 416:30] + node _T_590 = cat(_T_589, _T_588) @[el2_lib.scala 416:30] + node _T_591 = cat(_T_590, _T_587) @[el2_lib.scala 416:30] + node _T_592 = cat(_T_357[24], _T_357[23]) @[el2_lib.scala 416:30] + node _T_593 = cat(_T_357[26], _T_357[25]) @[el2_lib.scala 416:30] + node _T_594 = cat(_T_593, _T_592) @[el2_lib.scala 416:30] + node _T_595 = cat(_T_357[28], _T_357[27]) @[el2_lib.scala 416:30] + node _T_596 = cat(_T_357[30], _T_357[29]) @[el2_lib.scala 416:30] + node _T_597 = cat(_T_596, _T_595) @[el2_lib.scala 416:30] + node _T_598 = cat(_T_597, _T_594) @[el2_lib.scala 416:30] + node _T_599 = cat(_T_598, _T_591) @[el2_lib.scala 416:30] + node _T_600 = cat(_T_599, _T_584) @[el2_lib.scala 416:30] + node _T_601 = xorr(_T_600) @[el2_lib.scala 416:37] + node _T_602 = cat(_T_356[2], _T_356[1]) @[el2_lib.scala 416:47] + node _T_603 = cat(_T_602, _T_356[0]) @[el2_lib.scala 416:47] + node _T_604 = cat(_T_356[4], _T_356[3]) @[el2_lib.scala 416:47] + node _T_605 = cat(_T_356[6], _T_356[5]) @[el2_lib.scala 416:47] + node _T_606 = cat(_T_605, _T_604) @[el2_lib.scala 416:47] + node _T_607 = cat(_T_606, _T_603) @[el2_lib.scala 416:47] + node _T_608 = cat(_T_356[8], _T_356[7]) @[el2_lib.scala 416:47] + node _T_609 = cat(_T_356[10], _T_356[9]) @[el2_lib.scala 416:47] + node _T_610 = cat(_T_609, _T_608) @[el2_lib.scala 416:47] + node _T_611 = cat(_T_356[12], _T_356[11]) @[el2_lib.scala 416:47] + node _T_612 = cat(_T_356[14], _T_356[13]) @[el2_lib.scala 416:47] + node _T_613 = cat(_T_612, _T_611) @[el2_lib.scala 416:47] + node _T_614 = cat(_T_613, _T_610) @[el2_lib.scala 416:47] + node _T_615 = cat(_T_614, _T_607) @[el2_lib.scala 416:47] + node _T_616 = cat(_T_356[16], _T_356[15]) @[el2_lib.scala 416:47] + node _T_617 = cat(_T_356[18], _T_356[17]) @[el2_lib.scala 416:47] + node _T_618 = cat(_T_617, _T_616) @[el2_lib.scala 416:47] + node _T_619 = cat(_T_356[20], _T_356[19]) @[el2_lib.scala 416:47] + node _T_620 = cat(_T_356[22], _T_356[21]) @[el2_lib.scala 416:47] + node _T_621 = cat(_T_620, _T_619) @[el2_lib.scala 416:47] + node _T_622 = cat(_T_621, _T_618) @[el2_lib.scala 416:47] + node _T_623 = cat(_T_356[24], _T_356[23]) @[el2_lib.scala 416:47] + node _T_624 = cat(_T_356[26], _T_356[25]) @[el2_lib.scala 416:47] + node _T_625 = cat(_T_624, _T_623) @[el2_lib.scala 416:47] + node _T_626 = cat(_T_356[28], _T_356[27]) @[el2_lib.scala 416:47] + node _T_627 = cat(_T_356[30], _T_356[29]) @[el2_lib.scala 416:47] + node _T_628 = cat(_T_627, _T_626) @[el2_lib.scala 416:47] + node _T_629 = cat(_T_628, _T_625) @[el2_lib.scala 416:47] + node _T_630 = cat(_T_629, _T_622) @[el2_lib.scala 416:47] + node _T_631 = cat(_T_630, _T_615) @[el2_lib.scala 416:47] + node _T_632 = xorr(_T_631) @[el2_lib.scala 416:54] + node _T_633 = cat(_T_355[2], _T_355[1]) @[el2_lib.scala 416:64] + node _T_634 = cat(_T_633, _T_355[0]) @[el2_lib.scala 416:64] + node _T_635 = cat(_T_355[4], _T_355[3]) @[el2_lib.scala 416:64] + node _T_636 = cat(_T_355[6], _T_355[5]) @[el2_lib.scala 416:64] + node _T_637 = cat(_T_636, _T_635) @[el2_lib.scala 416:64] + node _T_638 = cat(_T_637, _T_634) @[el2_lib.scala 416:64] + node _T_639 = cat(_T_355[8], _T_355[7]) @[el2_lib.scala 416:64] + node _T_640 = cat(_T_355[10], _T_355[9]) @[el2_lib.scala 416:64] + node _T_641 = cat(_T_640, _T_639) @[el2_lib.scala 416:64] + node _T_642 = cat(_T_355[12], _T_355[11]) @[el2_lib.scala 416:64] + node _T_643 = cat(_T_355[14], _T_355[13]) @[el2_lib.scala 416:64] + node _T_644 = cat(_T_643, _T_642) @[el2_lib.scala 416:64] + node _T_645 = cat(_T_644, _T_641) @[el2_lib.scala 416:64] + node _T_646 = cat(_T_645, _T_638) @[el2_lib.scala 416:64] + node _T_647 = cat(_T_355[16], _T_355[15]) @[el2_lib.scala 416:64] + node _T_648 = cat(_T_355[18], _T_355[17]) @[el2_lib.scala 416:64] + node _T_649 = cat(_T_648, _T_647) @[el2_lib.scala 416:64] + node _T_650 = cat(_T_355[20], _T_355[19]) @[el2_lib.scala 416:64] + node _T_651 = cat(_T_355[22], _T_355[21]) @[el2_lib.scala 416:64] + node _T_652 = cat(_T_651, _T_650) @[el2_lib.scala 416:64] + node _T_653 = cat(_T_652, _T_649) @[el2_lib.scala 416:64] + node _T_654 = cat(_T_355[24], _T_355[23]) @[el2_lib.scala 416:64] + node _T_655 = cat(_T_355[26], _T_355[25]) @[el2_lib.scala 416:64] + node _T_656 = cat(_T_655, _T_654) @[el2_lib.scala 416:64] + node _T_657 = cat(_T_355[28], _T_355[27]) @[el2_lib.scala 416:64] + node _T_658 = cat(_T_355[30], _T_355[29]) @[el2_lib.scala 416:64] + node _T_659 = cat(_T_658, _T_657) @[el2_lib.scala 416:64] + node _T_660 = cat(_T_659, _T_656) @[el2_lib.scala 416:64] + node _T_661 = cat(_T_660, _T_653) @[el2_lib.scala 416:64] + node _T_662 = cat(_T_661, _T_646) @[el2_lib.scala 416:64] + node _T_663 = xorr(_T_662) @[el2_lib.scala 416:71] + node _T_664 = cat(_T_354[1], _T_354[0]) @[el2_lib.scala 416:81] + node _T_665 = cat(_T_354[3], _T_354[2]) @[el2_lib.scala 416:81] + node _T_666 = cat(_T_665, _T_664) @[el2_lib.scala 416:81] + node _T_667 = cat(_T_354[5], _T_354[4]) @[el2_lib.scala 416:81] + node _T_668 = cat(_T_354[7], _T_354[6]) @[el2_lib.scala 416:81] + node _T_669 = cat(_T_668, _T_667) @[el2_lib.scala 416:81] + node _T_670 = cat(_T_669, _T_666) @[el2_lib.scala 416:81] + node _T_671 = cat(_T_354[9], _T_354[8]) @[el2_lib.scala 416:81] + node _T_672 = cat(_T_354[11], _T_354[10]) @[el2_lib.scala 416:81] + node _T_673 = cat(_T_672, _T_671) @[el2_lib.scala 416:81] + node _T_674 = cat(_T_354[13], _T_354[12]) @[el2_lib.scala 416:81] + node _T_675 = cat(_T_354[16], _T_354[15]) @[el2_lib.scala 416:81] + node _T_676 = cat(_T_675, _T_354[14]) @[el2_lib.scala 416:81] + node _T_677 = cat(_T_676, _T_674) @[el2_lib.scala 416:81] + node _T_678 = cat(_T_677, _T_673) @[el2_lib.scala 416:81] + node _T_679 = cat(_T_678, _T_670) @[el2_lib.scala 416:81] + node _T_680 = cat(_T_354[18], _T_354[17]) @[el2_lib.scala 416:81] + node _T_681 = cat(_T_354[20], _T_354[19]) @[el2_lib.scala 416:81] + node _T_682 = cat(_T_681, _T_680) @[el2_lib.scala 416:81] + node _T_683 = cat(_T_354[22], _T_354[21]) @[el2_lib.scala 416:81] + node _T_684 = cat(_T_354[25], _T_354[24]) @[el2_lib.scala 416:81] + node _T_685 = cat(_T_684, _T_354[23]) @[el2_lib.scala 416:81] + node _T_686 = cat(_T_685, _T_683) @[el2_lib.scala 416:81] + node _T_687 = cat(_T_686, _T_682) @[el2_lib.scala 416:81] + node _T_688 = cat(_T_354[27], _T_354[26]) @[el2_lib.scala 416:81] + node _T_689 = cat(_T_354[29], _T_354[28]) @[el2_lib.scala 416:81] + node _T_690 = cat(_T_689, _T_688) @[el2_lib.scala 416:81] + node _T_691 = cat(_T_354[31], _T_354[30]) @[el2_lib.scala 416:81] + node _T_692 = cat(_T_354[34], _T_354[33]) @[el2_lib.scala 416:81] + node _T_693 = cat(_T_692, _T_354[32]) @[el2_lib.scala 416:81] + node _T_694 = cat(_T_693, _T_691) @[el2_lib.scala 416:81] + node _T_695 = cat(_T_694, _T_690) @[el2_lib.scala 416:81] + node _T_696 = cat(_T_695, _T_687) @[el2_lib.scala 416:81] + node _T_697 = cat(_T_696, _T_679) @[el2_lib.scala 416:81] + node _T_698 = xorr(_T_697) @[el2_lib.scala 416:88] + node _T_699 = cat(_T_353[1], _T_353[0]) @[el2_lib.scala 416:98] + node _T_700 = cat(_T_353[3], _T_353[2]) @[el2_lib.scala 416:98] + node _T_701 = cat(_T_700, _T_699) @[el2_lib.scala 416:98] + node _T_702 = cat(_T_353[5], _T_353[4]) @[el2_lib.scala 416:98] + node _T_703 = cat(_T_353[7], _T_353[6]) @[el2_lib.scala 416:98] + node _T_704 = cat(_T_703, _T_702) @[el2_lib.scala 416:98] + node _T_705 = cat(_T_704, _T_701) @[el2_lib.scala 416:98] + node _T_706 = cat(_T_353[9], _T_353[8]) @[el2_lib.scala 416:98] + node _T_707 = cat(_T_353[11], _T_353[10]) @[el2_lib.scala 416:98] + node _T_708 = cat(_T_707, _T_706) @[el2_lib.scala 416:98] + node _T_709 = cat(_T_353[13], _T_353[12]) @[el2_lib.scala 416:98] + node _T_710 = cat(_T_353[16], _T_353[15]) @[el2_lib.scala 416:98] + node _T_711 = cat(_T_710, _T_353[14]) @[el2_lib.scala 416:98] + node _T_712 = cat(_T_711, _T_709) @[el2_lib.scala 416:98] + node _T_713 = cat(_T_712, _T_708) @[el2_lib.scala 416:98] + node _T_714 = cat(_T_713, _T_705) @[el2_lib.scala 416:98] + node _T_715 = cat(_T_353[18], _T_353[17]) @[el2_lib.scala 416:98] + node _T_716 = cat(_T_353[20], _T_353[19]) @[el2_lib.scala 416:98] + node _T_717 = cat(_T_716, _T_715) @[el2_lib.scala 416:98] + node _T_718 = cat(_T_353[22], _T_353[21]) @[el2_lib.scala 416:98] + node _T_719 = cat(_T_353[25], _T_353[24]) @[el2_lib.scala 416:98] + node _T_720 = cat(_T_719, _T_353[23]) @[el2_lib.scala 416:98] + node _T_721 = cat(_T_720, _T_718) @[el2_lib.scala 416:98] + node _T_722 = cat(_T_721, _T_717) @[el2_lib.scala 416:98] + node _T_723 = cat(_T_353[27], _T_353[26]) @[el2_lib.scala 416:98] + node _T_724 = cat(_T_353[29], _T_353[28]) @[el2_lib.scala 416:98] + node _T_725 = cat(_T_724, _T_723) @[el2_lib.scala 416:98] + node _T_726 = cat(_T_353[31], _T_353[30]) @[el2_lib.scala 416:98] + node _T_727 = cat(_T_353[34], _T_353[33]) @[el2_lib.scala 416:98] + node _T_728 = cat(_T_727, _T_353[32]) @[el2_lib.scala 416:98] + node _T_729 = cat(_T_728, _T_726) @[el2_lib.scala 416:98] + node _T_730 = cat(_T_729, _T_725) @[el2_lib.scala 416:98] + node _T_731 = cat(_T_730, _T_722) @[el2_lib.scala 416:98] + node _T_732 = cat(_T_731, _T_714) @[el2_lib.scala 416:98] + node _T_733 = xorr(_T_732) @[el2_lib.scala 416:105] + node _T_734 = cat(_T_352[1], _T_352[0]) @[el2_lib.scala 416:115] + node _T_735 = cat(_T_352[3], _T_352[2]) @[el2_lib.scala 416:115] + node _T_736 = cat(_T_735, _T_734) @[el2_lib.scala 416:115] + node _T_737 = cat(_T_352[5], _T_352[4]) @[el2_lib.scala 416:115] + node _T_738 = cat(_T_352[7], _T_352[6]) @[el2_lib.scala 416:115] + node _T_739 = cat(_T_738, _T_737) @[el2_lib.scala 416:115] + node _T_740 = cat(_T_739, _T_736) @[el2_lib.scala 416:115] + node _T_741 = cat(_T_352[9], _T_352[8]) @[el2_lib.scala 416:115] + node _T_742 = cat(_T_352[11], _T_352[10]) @[el2_lib.scala 416:115] + node _T_743 = cat(_T_742, _T_741) @[el2_lib.scala 416:115] + node _T_744 = cat(_T_352[13], _T_352[12]) @[el2_lib.scala 416:115] + node _T_745 = cat(_T_352[16], _T_352[15]) @[el2_lib.scala 416:115] + node _T_746 = cat(_T_745, _T_352[14]) @[el2_lib.scala 416:115] + node _T_747 = cat(_T_746, _T_744) @[el2_lib.scala 416:115] + node _T_748 = cat(_T_747, _T_743) @[el2_lib.scala 416:115] + node _T_749 = cat(_T_748, _T_740) @[el2_lib.scala 416:115] + node _T_750 = cat(_T_352[18], _T_352[17]) @[el2_lib.scala 416:115] + node _T_751 = cat(_T_352[20], _T_352[19]) @[el2_lib.scala 416:115] + node _T_752 = cat(_T_751, _T_750) @[el2_lib.scala 416:115] + node _T_753 = cat(_T_352[22], _T_352[21]) @[el2_lib.scala 416:115] + node _T_754 = cat(_T_352[25], _T_352[24]) @[el2_lib.scala 416:115] + node _T_755 = cat(_T_754, _T_352[23]) @[el2_lib.scala 416:115] + node _T_756 = cat(_T_755, _T_753) @[el2_lib.scala 416:115] + node _T_757 = cat(_T_756, _T_752) @[el2_lib.scala 416:115] + node _T_758 = cat(_T_352[27], _T_352[26]) @[el2_lib.scala 416:115] + node _T_759 = cat(_T_352[29], _T_352[28]) @[el2_lib.scala 416:115] + node _T_760 = cat(_T_759, _T_758) @[el2_lib.scala 416:115] + node _T_761 = cat(_T_352[31], _T_352[30]) @[el2_lib.scala 416:115] + node _T_762 = cat(_T_352[34], _T_352[33]) @[el2_lib.scala 416:115] + node _T_763 = cat(_T_762, _T_352[32]) @[el2_lib.scala 416:115] + node _T_764 = cat(_T_763, _T_761) @[el2_lib.scala 416:115] + node _T_765 = cat(_T_764, _T_760) @[el2_lib.scala 416:115] + node _T_766 = cat(_T_765, _T_757) @[el2_lib.scala 416:115] + node _T_767 = cat(_T_766, _T_749) @[el2_lib.scala 416:115] + node _T_768 = xorr(_T_767) @[el2_lib.scala 416:122] + node _T_769 = cat(_T_698, _T_733) @[Cat.scala 29:58] + node _T_770 = cat(_T_769, _T_768) @[Cat.scala 29:58] + node _T_771 = cat(_T_632, _T_663) @[Cat.scala 29:58] + node _T_772 = cat(_T_570, _T_601) @[Cat.scala 29:58] + node _T_773 = cat(_T_772, _T_771) @[Cat.scala 29:58] + node ic_wr_ecc = cat(_T_773, _T_770) @[Cat.scala 29:58] + wire _T_774 : UInt<1>[35] @[el2_lib.scala 395:18] + wire _T_775 : UInt<1>[35] @[el2_lib.scala 396:18] + wire _T_776 : UInt<1>[35] @[el2_lib.scala 397:18] + wire _T_777 : UInt<1>[31] @[el2_lib.scala 398:18] + wire _T_778 : UInt<1>[31] @[el2_lib.scala 399:18] + wire _T_779 : UInt<1>[31] @[el2_lib.scala 400:18] + wire _T_780 : UInt<1>[7] @[el2_lib.scala 401:18] + node _T_781 = bits(ic_miss_buff_half, 0, 0) @[el2_lib.scala 408:36] + _T_774[0] <= _T_781 @[el2_lib.scala 408:30] + node _T_782 = bits(ic_miss_buff_half, 0, 0) @[el2_lib.scala 409:36] + _T_775[0] <= _T_782 @[el2_lib.scala 409:30] + node _T_783 = bits(ic_miss_buff_half, 1, 1) @[el2_lib.scala 408:36] + _T_774[1] <= _T_783 @[el2_lib.scala 408:30] + node _T_784 = bits(ic_miss_buff_half, 1, 1) @[el2_lib.scala 410:36] + _T_776[0] <= _T_784 @[el2_lib.scala 410:30] + node _T_785 = bits(ic_miss_buff_half, 2, 2) @[el2_lib.scala 409:36] + _T_775[1] <= _T_785 @[el2_lib.scala 409:30] + node _T_786 = bits(ic_miss_buff_half, 2, 2) @[el2_lib.scala 410:36] + _T_776[1] <= _T_786 @[el2_lib.scala 410:30] + node _T_787 = bits(ic_miss_buff_half, 3, 3) @[el2_lib.scala 408:36] + _T_774[2] <= _T_787 @[el2_lib.scala 408:30] + node _T_788 = bits(ic_miss_buff_half, 3, 3) @[el2_lib.scala 409:36] + _T_775[2] <= _T_788 @[el2_lib.scala 409:30] + node _T_789 = bits(ic_miss_buff_half, 3, 3) @[el2_lib.scala 410:36] + _T_776[2] <= _T_789 @[el2_lib.scala 410:30] + node _T_790 = bits(ic_miss_buff_half, 4, 4) @[el2_lib.scala 408:36] + _T_774[3] <= _T_790 @[el2_lib.scala 408:30] + node _T_791 = bits(ic_miss_buff_half, 4, 4) @[el2_lib.scala 411:36] + _T_777[0] <= _T_791 @[el2_lib.scala 411:30] + node _T_792 = bits(ic_miss_buff_half, 5, 5) @[el2_lib.scala 409:36] + _T_775[3] <= _T_792 @[el2_lib.scala 409:30] + node _T_793 = bits(ic_miss_buff_half, 5, 5) @[el2_lib.scala 411:36] + _T_777[1] <= _T_793 @[el2_lib.scala 411:30] + node _T_794 = bits(ic_miss_buff_half, 6, 6) @[el2_lib.scala 408:36] + _T_774[4] <= _T_794 @[el2_lib.scala 408:30] + node _T_795 = bits(ic_miss_buff_half, 6, 6) @[el2_lib.scala 409:36] + _T_775[4] <= _T_795 @[el2_lib.scala 409:30] + node _T_796 = bits(ic_miss_buff_half, 6, 6) @[el2_lib.scala 411:36] + _T_777[2] <= _T_796 @[el2_lib.scala 411:30] + node _T_797 = bits(ic_miss_buff_half, 7, 7) @[el2_lib.scala 410:36] + _T_776[3] <= _T_797 @[el2_lib.scala 410:30] + node _T_798 = bits(ic_miss_buff_half, 7, 7) @[el2_lib.scala 411:36] + _T_777[3] <= _T_798 @[el2_lib.scala 411:30] + node _T_799 = bits(ic_miss_buff_half, 8, 8) @[el2_lib.scala 408:36] + _T_774[5] <= _T_799 @[el2_lib.scala 408:30] + node _T_800 = bits(ic_miss_buff_half, 8, 8) @[el2_lib.scala 410:36] + _T_776[4] <= _T_800 @[el2_lib.scala 410:30] + node _T_801 = bits(ic_miss_buff_half, 8, 8) @[el2_lib.scala 411:36] + _T_777[4] <= _T_801 @[el2_lib.scala 411:30] + node _T_802 = bits(ic_miss_buff_half, 9, 9) @[el2_lib.scala 409:36] + _T_775[5] <= _T_802 @[el2_lib.scala 409:30] + node _T_803 = bits(ic_miss_buff_half, 9, 9) @[el2_lib.scala 410:36] + _T_776[5] <= _T_803 @[el2_lib.scala 410:30] + node _T_804 = bits(ic_miss_buff_half, 9, 9) @[el2_lib.scala 411:36] + _T_777[5] <= _T_804 @[el2_lib.scala 411:30] + node _T_805 = bits(ic_miss_buff_half, 10, 10) @[el2_lib.scala 408:36] + _T_774[6] <= _T_805 @[el2_lib.scala 408:30] + node _T_806 = bits(ic_miss_buff_half, 10, 10) @[el2_lib.scala 409:36] + _T_775[6] <= _T_806 @[el2_lib.scala 409:30] + node _T_807 = bits(ic_miss_buff_half, 10, 10) @[el2_lib.scala 410:36] + _T_776[6] <= _T_807 @[el2_lib.scala 410:30] + node _T_808 = bits(ic_miss_buff_half, 10, 10) @[el2_lib.scala 411:36] + _T_777[6] <= _T_808 @[el2_lib.scala 411:30] + node _T_809 = bits(ic_miss_buff_half, 11, 11) @[el2_lib.scala 408:36] + _T_774[7] <= _T_809 @[el2_lib.scala 408:30] + node _T_810 = bits(ic_miss_buff_half, 11, 11) @[el2_lib.scala 412:36] + _T_778[0] <= _T_810 @[el2_lib.scala 412:30] + node _T_811 = bits(ic_miss_buff_half, 12, 12) @[el2_lib.scala 409:36] + _T_775[7] <= _T_811 @[el2_lib.scala 409:30] + node _T_812 = bits(ic_miss_buff_half, 12, 12) @[el2_lib.scala 412:36] + _T_778[1] <= _T_812 @[el2_lib.scala 412:30] + node _T_813 = bits(ic_miss_buff_half, 13, 13) @[el2_lib.scala 408:36] + _T_774[8] <= _T_813 @[el2_lib.scala 408:30] + node _T_814 = bits(ic_miss_buff_half, 13, 13) @[el2_lib.scala 409:36] + _T_775[8] <= _T_814 @[el2_lib.scala 409:30] + node _T_815 = bits(ic_miss_buff_half, 13, 13) @[el2_lib.scala 412:36] + _T_778[2] <= _T_815 @[el2_lib.scala 412:30] + node _T_816 = bits(ic_miss_buff_half, 14, 14) @[el2_lib.scala 410:36] + _T_776[7] <= _T_816 @[el2_lib.scala 410:30] + node _T_817 = bits(ic_miss_buff_half, 14, 14) @[el2_lib.scala 412:36] + _T_778[3] <= _T_817 @[el2_lib.scala 412:30] + node _T_818 = bits(ic_miss_buff_half, 15, 15) @[el2_lib.scala 408:36] + _T_774[9] <= _T_818 @[el2_lib.scala 408:30] + node _T_819 = bits(ic_miss_buff_half, 15, 15) @[el2_lib.scala 410:36] + _T_776[8] <= _T_819 @[el2_lib.scala 410:30] + node _T_820 = bits(ic_miss_buff_half, 15, 15) @[el2_lib.scala 412:36] + _T_778[4] <= _T_820 @[el2_lib.scala 412:30] + node _T_821 = bits(ic_miss_buff_half, 16, 16) @[el2_lib.scala 409:36] + _T_775[9] <= _T_821 @[el2_lib.scala 409:30] + node _T_822 = bits(ic_miss_buff_half, 16, 16) @[el2_lib.scala 410:36] + _T_776[9] <= _T_822 @[el2_lib.scala 410:30] + node _T_823 = bits(ic_miss_buff_half, 16, 16) @[el2_lib.scala 412:36] + _T_778[5] <= _T_823 @[el2_lib.scala 412:30] + node _T_824 = bits(ic_miss_buff_half, 17, 17) @[el2_lib.scala 408:36] + _T_774[10] <= _T_824 @[el2_lib.scala 408:30] + node _T_825 = bits(ic_miss_buff_half, 17, 17) @[el2_lib.scala 409:36] + _T_775[10] <= _T_825 @[el2_lib.scala 409:30] + node _T_826 = bits(ic_miss_buff_half, 17, 17) @[el2_lib.scala 410:36] + _T_776[10] <= _T_826 @[el2_lib.scala 410:30] + node _T_827 = bits(ic_miss_buff_half, 17, 17) @[el2_lib.scala 412:36] + _T_778[6] <= _T_827 @[el2_lib.scala 412:30] + node _T_828 = bits(ic_miss_buff_half, 18, 18) @[el2_lib.scala 411:36] + _T_777[7] <= _T_828 @[el2_lib.scala 411:30] + node _T_829 = bits(ic_miss_buff_half, 18, 18) @[el2_lib.scala 412:36] + _T_778[7] <= _T_829 @[el2_lib.scala 412:30] + node _T_830 = bits(ic_miss_buff_half, 19, 19) @[el2_lib.scala 408:36] + _T_774[11] <= _T_830 @[el2_lib.scala 408:30] + node _T_831 = bits(ic_miss_buff_half, 19, 19) @[el2_lib.scala 411:36] + _T_777[8] <= _T_831 @[el2_lib.scala 411:30] + node _T_832 = bits(ic_miss_buff_half, 19, 19) @[el2_lib.scala 412:36] + _T_778[8] <= _T_832 @[el2_lib.scala 412:30] + node _T_833 = bits(ic_miss_buff_half, 20, 20) @[el2_lib.scala 409:36] + _T_775[11] <= _T_833 @[el2_lib.scala 409:30] + node _T_834 = bits(ic_miss_buff_half, 20, 20) @[el2_lib.scala 411:36] + _T_777[9] <= _T_834 @[el2_lib.scala 411:30] + node _T_835 = bits(ic_miss_buff_half, 20, 20) @[el2_lib.scala 412:36] + _T_778[9] <= _T_835 @[el2_lib.scala 412:30] + node _T_836 = bits(ic_miss_buff_half, 21, 21) @[el2_lib.scala 408:36] + _T_774[12] <= _T_836 @[el2_lib.scala 408:30] + node _T_837 = bits(ic_miss_buff_half, 21, 21) @[el2_lib.scala 409:36] + _T_775[12] <= _T_837 @[el2_lib.scala 409:30] + node _T_838 = bits(ic_miss_buff_half, 21, 21) @[el2_lib.scala 411:36] + _T_777[10] <= _T_838 @[el2_lib.scala 411:30] + node _T_839 = bits(ic_miss_buff_half, 21, 21) @[el2_lib.scala 412:36] + _T_778[10] <= _T_839 @[el2_lib.scala 412:30] + node _T_840 = bits(ic_miss_buff_half, 22, 22) @[el2_lib.scala 410:36] + _T_776[11] <= _T_840 @[el2_lib.scala 410:30] + node _T_841 = bits(ic_miss_buff_half, 22, 22) @[el2_lib.scala 411:36] + _T_777[11] <= _T_841 @[el2_lib.scala 411:30] + node _T_842 = bits(ic_miss_buff_half, 22, 22) @[el2_lib.scala 412:36] + _T_778[11] <= _T_842 @[el2_lib.scala 412:30] + node _T_843 = bits(ic_miss_buff_half, 23, 23) @[el2_lib.scala 408:36] + _T_774[13] <= _T_843 @[el2_lib.scala 408:30] + node _T_844 = bits(ic_miss_buff_half, 23, 23) @[el2_lib.scala 410:36] + _T_776[12] <= _T_844 @[el2_lib.scala 410:30] + node _T_845 = bits(ic_miss_buff_half, 23, 23) @[el2_lib.scala 411:36] + _T_777[12] <= _T_845 @[el2_lib.scala 411:30] + node _T_846 = bits(ic_miss_buff_half, 23, 23) @[el2_lib.scala 412:36] + _T_778[12] <= _T_846 @[el2_lib.scala 412:30] + node _T_847 = bits(ic_miss_buff_half, 24, 24) @[el2_lib.scala 409:36] + _T_775[13] <= _T_847 @[el2_lib.scala 409:30] + node _T_848 = bits(ic_miss_buff_half, 24, 24) @[el2_lib.scala 410:36] + _T_776[13] <= _T_848 @[el2_lib.scala 410:30] + node _T_849 = bits(ic_miss_buff_half, 24, 24) @[el2_lib.scala 411:36] + _T_777[13] <= _T_849 @[el2_lib.scala 411:30] + node _T_850 = bits(ic_miss_buff_half, 24, 24) @[el2_lib.scala 412:36] + _T_778[13] <= _T_850 @[el2_lib.scala 412:30] + node _T_851 = bits(ic_miss_buff_half, 25, 25) @[el2_lib.scala 408:36] + _T_774[14] <= _T_851 @[el2_lib.scala 408:30] + node _T_852 = bits(ic_miss_buff_half, 25, 25) @[el2_lib.scala 409:36] + _T_775[14] <= _T_852 @[el2_lib.scala 409:30] + node _T_853 = bits(ic_miss_buff_half, 25, 25) @[el2_lib.scala 410:36] + _T_776[14] <= _T_853 @[el2_lib.scala 410:30] + node _T_854 = bits(ic_miss_buff_half, 25, 25) @[el2_lib.scala 411:36] + _T_777[14] <= _T_854 @[el2_lib.scala 411:30] + node _T_855 = bits(ic_miss_buff_half, 25, 25) @[el2_lib.scala 412:36] + _T_778[14] <= _T_855 @[el2_lib.scala 412:30] + node _T_856 = bits(ic_miss_buff_half, 26, 26) @[el2_lib.scala 408:36] + _T_774[15] <= _T_856 @[el2_lib.scala 408:30] + node _T_857 = bits(ic_miss_buff_half, 26, 26) @[el2_lib.scala 413:36] + _T_779[0] <= _T_857 @[el2_lib.scala 413:30] + node _T_858 = bits(ic_miss_buff_half, 27, 27) @[el2_lib.scala 409:36] + _T_775[15] <= _T_858 @[el2_lib.scala 409:30] + node _T_859 = bits(ic_miss_buff_half, 27, 27) @[el2_lib.scala 413:36] + _T_779[1] <= _T_859 @[el2_lib.scala 413:30] + node _T_860 = bits(ic_miss_buff_half, 28, 28) @[el2_lib.scala 408:36] + _T_774[16] <= _T_860 @[el2_lib.scala 408:30] + node _T_861 = bits(ic_miss_buff_half, 28, 28) @[el2_lib.scala 409:36] + _T_775[16] <= _T_861 @[el2_lib.scala 409:30] + node _T_862 = bits(ic_miss_buff_half, 28, 28) @[el2_lib.scala 413:36] + _T_779[2] <= _T_862 @[el2_lib.scala 413:30] + node _T_863 = bits(ic_miss_buff_half, 29, 29) @[el2_lib.scala 410:36] + _T_776[15] <= _T_863 @[el2_lib.scala 410:30] + node _T_864 = bits(ic_miss_buff_half, 29, 29) @[el2_lib.scala 413:36] + _T_779[3] <= _T_864 @[el2_lib.scala 413:30] + node _T_865 = bits(ic_miss_buff_half, 30, 30) @[el2_lib.scala 408:36] + _T_774[17] <= _T_865 @[el2_lib.scala 408:30] + node _T_866 = bits(ic_miss_buff_half, 30, 30) @[el2_lib.scala 410:36] + _T_776[16] <= _T_866 @[el2_lib.scala 410:30] + node _T_867 = bits(ic_miss_buff_half, 30, 30) @[el2_lib.scala 413:36] + _T_779[4] <= _T_867 @[el2_lib.scala 413:30] + node _T_868 = bits(ic_miss_buff_half, 31, 31) @[el2_lib.scala 409:36] + _T_775[17] <= _T_868 @[el2_lib.scala 409:30] + node _T_869 = bits(ic_miss_buff_half, 31, 31) @[el2_lib.scala 410:36] + _T_776[17] <= _T_869 @[el2_lib.scala 410:30] + node _T_870 = bits(ic_miss_buff_half, 31, 31) @[el2_lib.scala 413:36] + _T_779[5] <= _T_870 @[el2_lib.scala 413:30] + node _T_871 = bits(ic_miss_buff_half, 32, 32) @[el2_lib.scala 408:36] + _T_774[18] <= _T_871 @[el2_lib.scala 408:30] + node _T_872 = bits(ic_miss_buff_half, 32, 32) @[el2_lib.scala 409:36] + _T_775[18] <= _T_872 @[el2_lib.scala 409:30] + node _T_873 = bits(ic_miss_buff_half, 32, 32) @[el2_lib.scala 410:36] + _T_776[18] <= _T_873 @[el2_lib.scala 410:30] + node _T_874 = bits(ic_miss_buff_half, 32, 32) @[el2_lib.scala 413:36] + _T_779[6] <= _T_874 @[el2_lib.scala 413:30] + node _T_875 = bits(ic_miss_buff_half, 33, 33) @[el2_lib.scala 411:36] + _T_777[15] <= _T_875 @[el2_lib.scala 411:30] + node _T_876 = bits(ic_miss_buff_half, 33, 33) @[el2_lib.scala 413:36] + _T_779[7] <= _T_876 @[el2_lib.scala 413:30] + node _T_877 = bits(ic_miss_buff_half, 34, 34) @[el2_lib.scala 408:36] + _T_774[19] <= _T_877 @[el2_lib.scala 408:30] + node _T_878 = bits(ic_miss_buff_half, 34, 34) @[el2_lib.scala 411:36] + _T_777[16] <= _T_878 @[el2_lib.scala 411:30] + node _T_879 = bits(ic_miss_buff_half, 34, 34) @[el2_lib.scala 413:36] + _T_779[8] <= _T_879 @[el2_lib.scala 413:30] + node _T_880 = bits(ic_miss_buff_half, 35, 35) @[el2_lib.scala 409:36] + _T_775[19] <= _T_880 @[el2_lib.scala 409:30] + node _T_881 = bits(ic_miss_buff_half, 35, 35) @[el2_lib.scala 411:36] + _T_777[17] <= _T_881 @[el2_lib.scala 411:30] + node _T_882 = bits(ic_miss_buff_half, 35, 35) @[el2_lib.scala 413:36] + _T_779[9] <= _T_882 @[el2_lib.scala 413:30] + node _T_883 = bits(ic_miss_buff_half, 36, 36) @[el2_lib.scala 408:36] + _T_774[20] <= _T_883 @[el2_lib.scala 408:30] + node _T_884 = bits(ic_miss_buff_half, 36, 36) @[el2_lib.scala 409:36] + _T_775[20] <= _T_884 @[el2_lib.scala 409:30] + node _T_885 = bits(ic_miss_buff_half, 36, 36) @[el2_lib.scala 411:36] + _T_777[18] <= _T_885 @[el2_lib.scala 411:30] + node _T_886 = bits(ic_miss_buff_half, 36, 36) @[el2_lib.scala 413:36] + _T_779[10] <= _T_886 @[el2_lib.scala 413:30] + node _T_887 = bits(ic_miss_buff_half, 37, 37) @[el2_lib.scala 410:36] + _T_776[19] <= _T_887 @[el2_lib.scala 410:30] + node _T_888 = bits(ic_miss_buff_half, 37, 37) @[el2_lib.scala 411:36] + _T_777[19] <= _T_888 @[el2_lib.scala 411:30] + node _T_889 = bits(ic_miss_buff_half, 37, 37) @[el2_lib.scala 413:36] + _T_779[11] <= _T_889 @[el2_lib.scala 413:30] + node _T_890 = bits(ic_miss_buff_half, 38, 38) @[el2_lib.scala 408:36] + _T_774[21] <= _T_890 @[el2_lib.scala 408:30] + node _T_891 = bits(ic_miss_buff_half, 38, 38) @[el2_lib.scala 410:36] + _T_776[20] <= _T_891 @[el2_lib.scala 410:30] + node _T_892 = bits(ic_miss_buff_half, 38, 38) @[el2_lib.scala 411:36] + _T_777[20] <= _T_892 @[el2_lib.scala 411:30] + node _T_893 = bits(ic_miss_buff_half, 38, 38) @[el2_lib.scala 413:36] + _T_779[12] <= _T_893 @[el2_lib.scala 413:30] + node _T_894 = bits(ic_miss_buff_half, 39, 39) @[el2_lib.scala 409:36] + _T_775[21] <= _T_894 @[el2_lib.scala 409:30] + node _T_895 = bits(ic_miss_buff_half, 39, 39) @[el2_lib.scala 410:36] + _T_776[21] <= _T_895 @[el2_lib.scala 410:30] + node _T_896 = bits(ic_miss_buff_half, 39, 39) @[el2_lib.scala 411:36] + _T_777[21] <= _T_896 @[el2_lib.scala 411:30] + node _T_897 = bits(ic_miss_buff_half, 39, 39) @[el2_lib.scala 413:36] + _T_779[13] <= _T_897 @[el2_lib.scala 413:30] + node _T_898 = bits(ic_miss_buff_half, 40, 40) @[el2_lib.scala 408:36] + _T_774[22] <= _T_898 @[el2_lib.scala 408:30] + node _T_899 = bits(ic_miss_buff_half, 40, 40) @[el2_lib.scala 409:36] + _T_775[22] <= _T_899 @[el2_lib.scala 409:30] + node _T_900 = bits(ic_miss_buff_half, 40, 40) @[el2_lib.scala 410:36] + _T_776[22] <= _T_900 @[el2_lib.scala 410:30] + node _T_901 = bits(ic_miss_buff_half, 40, 40) @[el2_lib.scala 411:36] + _T_777[22] <= _T_901 @[el2_lib.scala 411:30] + node _T_902 = bits(ic_miss_buff_half, 40, 40) @[el2_lib.scala 413:36] + _T_779[14] <= _T_902 @[el2_lib.scala 413:30] + node _T_903 = bits(ic_miss_buff_half, 41, 41) @[el2_lib.scala 412:36] + _T_778[15] <= _T_903 @[el2_lib.scala 412:30] + node _T_904 = bits(ic_miss_buff_half, 41, 41) @[el2_lib.scala 413:36] + _T_779[15] <= _T_904 @[el2_lib.scala 413:30] + node _T_905 = bits(ic_miss_buff_half, 42, 42) @[el2_lib.scala 408:36] + _T_774[23] <= _T_905 @[el2_lib.scala 408:30] + node _T_906 = bits(ic_miss_buff_half, 42, 42) @[el2_lib.scala 412:36] + _T_778[16] <= _T_906 @[el2_lib.scala 412:30] + node _T_907 = bits(ic_miss_buff_half, 42, 42) @[el2_lib.scala 413:36] + _T_779[16] <= _T_907 @[el2_lib.scala 413:30] + node _T_908 = bits(ic_miss_buff_half, 43, 43) @[el2_lib.scala 409:36] + _T_775[23] <= _T_908 @[el2_lib.scala 409:30] + node _T_909 = bits(ic_miss_buff_half, 43, 43) @[el2_lib.scala 412:36] + _T_778[17] <= _T_909 @[el2_lib.scala 412:30] + node _T_910 = bits(ic_miss_buff_half, 43, 43) @[el2_lib.scala 413:36] + _T_779[17] <= _T_910 @[el2_lib.scala 413:30] + node _T_911 = bits(ic_miss_buff_half, 44, 44) @[el2_lib.scala 408:36] + _T_774[24] <= _T_911 @[el2_lib.scala 408:30] + node _T_912 = bits(ic_miss_buff_half, 44, 44) @[el2_lib.scala 409:36] + _T_775[24] <= _T_912 @[el2_lib.scala 409:30] + node _T_913 = bits(ic_miss_buff_half, 44, 44) @[el2_lib.scala 412:36] + _T_778[18] <= _T_913 @[el2_lib.scala 412:30] + node _T_914 = bits(ic_miss_buff_half, 44, 44) @[el2_lib.scala 413:36] + _T_779[18] <= _T_914 @[el2_lib.scala 413:30] + node _T_915 = bits(ic_miss_buff_half, 45, 45) @[el2_lib.scala 410:36] + _T_776[23] <= _T_915 @[el2_lib.scala 410:30] + node _T_916 = bits(ic_miss_buff_half, 45, 45) @[el2_lib.scala 412:36] + _T_778[19] <= _T_916 @[el2_lib.scala 412:30] + node _T_917 = bits(ic_miss_buff_half, 45, 45) @[el2_lib.scala 413:36] + _T_779[19] <= _T_917 @[el2_lib.scala 413:30] + node _T_918 = bits(ic_miss_buff_half, 46, 46) @[el2_lib.scala 408:36] + _T_774[25] <= _T_918 @[el2_lib.scala 408:30] + node _T_919 = bits(ic_miss_buff_half, 46, 46) @[el2_lib.scala 410:36] + _T_776[24] <= _T_919 @[el2_lib.scala 410:30] + node _T_920 = bits(ic_miss_buff_half, 46, 46) @[el2_lib.scala 412:36] + _T_778[20] <= _T_920 @[el2_lib.scala 412:30] + node _T_921 = bits(ic_miss_buff_half, 46, 46) @[el2_lib.scala 413:36] + _T_779[20] <= _T_921 @[el2_lib.scala 413:30] + node _T_922 = bits(ic_miss_buff_half, 47, 47) @[el2_lib.scala 409:36] + _T_775[25] <= _T_922 @[el2_lib.scala 409:30] + node _T_923 = bits(ic_miss_buff_half, 47, 47) @[el2_lib.scala 410:36] + _T_776[25] <= _T_923 @[el2_lib.scala 410:30] + node _T_924 = bits(ic_miss_buff_half, 47, 47) @[el2_lib.scala 412:36] + _T_778[21] <= _T_924 @[el2_lib.scala 412:30] + node _T_925 = bits(ic_miss_buff_half, 47, 47) @[el2_lib.scala 413:36] + _T_779[21] <= _T_925 @[el2_lib.scala 413:30] + node _T_926 = bits(ic_miss_buff_half, 48, 48) @[el2_lib.scala 408:36] + _T_774[26] <= _T_926 @[el2_lib.scala 408:30] + node _T_927 = bits(ic_miss_buff_half, 48, 48) @[el2_lib.scala 409:36] + _T_775[26] <= _T_927 @[el2_lib.scala 409:30] + node _T_928 = bits(ic_miss_buff_half, 48, 48) @[el2_lib.scala 410:36] + _T_776[26] <= _T_928 @[el2_lib.scala 410:30] + node _T_929 = bits(ic_miss_buff_half, 48, 48) @[el2_lib.scala 412:36] + _T_778[22] <= _T_929 @[el2_lib.scala 412:30] + node _T_930 = bits(ic_miss_buff_half, 48, 48) @[el2_lib.scala 413:36] + _T_779[22] <= _T_930 @[el2_lib.scala 413:30] + node _T_931 = bits(ic_miss_buff_half, 49, 49) @[el2_lib.scala 411:36] + _T_777[23] <= _T_931 @[el2_lib.scala 411:30] + node _T_932 = bits(ic_miss_buff_half, 49, 49) @[el2_lib.scala 412:36] + _T_778[23] <= _T_932 @[el2_lib.scala 412:30] + node _T_933 = bits(ic_miss_buff_half, 49, 49) @[el2_lib.scala 413:36] + _T_779[23] <= _T_933 @[el2_lib.scala 413:30] + node _T_934 = bits(ic_miss_buff_half, 50, 50) @[el2_lib.scala 408:36] + _T_774[27] <= _T_934 @[el2_lib.scala 408:30] + node _T_935 = bits(ic_miss_buff_half, 50, 50) @[el2_lib.scala 411:36] + _T_777[24] <= _T_935 @[el2_lib.scala 411:30] + node _T_936 = bits(ic_miss_buff_half, 50, 50) @[el2_lib.scala 412:36] + _T_778[24] <= _T_936 @[el2_lib.scala 412:30] + node _T_937 = bits(ic_miss_buff_half, 50, 50) @[el2_lib.scala 413:36] + _T_779[24] <= _T_937 @[el2_lib.scala 413:30] + node _T_938 = bits(ic_miss_buff_half, 51, 51) @[el2_lib.scala 409:36] + _T_775[27] <= _T_938 @[el2_lib.scala 409:30] + node _T_939 = bits(ic_miss_buff_half, 51, 51) @[el2_lib.scala 411:36] + _T_777[25] <= _T_939 @[el2_lib.scala 411:30] + node _T_940 = bits(ic_miss_buff_half, 51, 51) @[el2_lib.scala 412:36] + _T_778[25] <= _T_940 @[el2_lib.scala 412:30] + node _T_941 = bits(ic_miss_buff_half, 51, 51) @[el2_lib.scala 413:36] + _T_779[25] <= _T_941 @[el2_lib.scala 413:30] + node _T_942 = bits(ic_miss_buff_half, 52, 52) @[el2_lib.scala 408:36] + _T_774[28] <= _T_942 @[el2_lib.scala 408:30] + node _T_943 = bits(ic_miss_buff_half, 52, 52) @[el2_lib.scala 409:36] + _T_775[28] <= _T_943 @[el2_lib.scala 409:30] + node _T_944 = bits(ic_miss_buff_half, 52, 52) @[el2_lib.scala 411:36] + _T_777[26] <= _T_944 @[el2_lib.scala 411:30] + node _T_945 = bits(ic_miss_buff_half, 52, 52) @[el2_lib.scala 412:36] + _T_778[26] <= _T_945 @[el2_lib.scala 412:30] + node _T_946 = bits(ic_miss_buff_half, 52, 52) @[el2_lib.scala 413:36] + _T_779[26] <= _T_946 @[el2_lib.scala 413:30] + node _T_947 = bits(ic_miss_buff_half, 53, 53) @[el2_lib.scala 410:36] + _T_776[27] <= _T_947 @[el2_lib.scala 410:30] + node _T_948 = bits(ic_miss_buff_half, 53, 53) @[el2_lib.scala 411:36] + _T_777[27] <= _T_948 @[el2_lib.scala 411:30] + node _T_949 = bits(ic_miss_buff_half, 53, 53) @[el2_lib.scala 412:36] + _T_778[27] <= _T_949 @[el2_lib.scala 412:30] + node _T_950 = bits(ic_miss_buff_half, 53, 53) @[el2_lib.scala 413:36] + _T_779[27] <= _T_950 @[el2_lib.scala 413:30] + node _T_951 = bits(ic_miss_buff_half, 54, 54) @[el2_lib.scala 408:36] + _T_774[29] <= _T_951 @[el2_lib.scala 408:30] + node _T_952 = bits(ic_miss_buff_half, 54, 54) @[el2_lib.scala 410:36] + _T_776[28] <= _T_952 @[el2_lib.scala 410:30] + node _T_953 = bits(ic_miss_buff_half, 54, 54) @[el2_lib.scala 411:36] + _T_777[28] <= _T_953 @[el2_lib.scala 411:30] + node _T_954 = bits(ic_miss_buff_half, 54, 54) @[el2_lib.scala 412:36] + _T_778[28] <= _T_954 @[el2_lib.scala 412:30] + node _T_955 = bits(ic_miss_buff_half, 54, 54) @[el2_lib.scala 413:36] + _T_779[28] <= _T_955 @[el2_lib.scala 413:30] + node _T_956 = bits(ic_miss_buff_half, 55, 55) @[el2_lib.scala 409:36] + _T_775[29] <= _T_956 @[el2_lib.scala 409:30] + node _T_957 = bits(ic_miss_buff_half, 55, 55) @[el2_lib.scala 410:36] + _T_776[29] <= _T_957 @[el2_lib.scala 410:30] + node _T_958 = bits(ic_miss_buff_half, 55, 55) @[el2_lib.scala 411:36] + _T_777[29] <= _T_958 @[el2_lib.scala 411:30] + node _T_959 = bits(ic_miss_buff_half, 55, 55) @[el2_lib.scala 412:36] + _T_778[29] <= _T_959 @[el2_lib.scala 412:30] + node _T_960 = bits(ic_miss_buff_half, 55, 55) @[el2_lib.scala 413:36] + _T_779[29] <= _T_960 @[el2_lib.scala 413:30] + node _T_961 = bits(ic_miss_buff_half, 56, 56) @[el2_lib.scala 408:36] + _T_774[30] <= _T_961 @[el2_lib.scala 408:30] + node _T_962 = bits(ic_miss_buff_half, 56, 56) @[el2_lib.scala 409:36] + _T_775[30] <= _T_962 @[el2_lib.scala 409:30] + node _T_963 = bits(ic_miss_buff_half, 56, 56) @[el2_lib.scala 410:36] + _T_776[30] <= _T_963 @[el2_lib.scala 410:30] + node _T_964 = bits(ic_miss_buff_half, 56, 56) @[el2_lib.scala 411:36] + _T_777[30] <= _T_964 @[el2_lib.scala 411:30] + node _T_965 = bits(ic_miss_buff_half, 56, 56) @[el2_lib.scala 412:36] + _T_778[30] <= _T_965 @[el2_lib.scala 412:30] + node _T_966 = bits(ic_miss_buff_half, 56, 56) @[el2_lib.scala 413:36] + _T_779[30] <= _T_966 @[el2_lib.scala 413:30] + node _T_967 = bits(ic_miss_buff_half, 57, 57) @[el2_lib.scala 408:36] + _T_774[31] <= _T_967 @[el2_lib.scala 408:30] + node _T_968 = bits(ic_miss_buff_half, 57, 57) @[el2_lib.scala 414:36] + _T_780[0] <= _T_968 @[el2_lib.scala 414:30] + node _T_969 = bits(ic_miss_buff_half, 58, 58) @[el2_lib.scala 409:36] + _T_775[31] <= _T_969 @[el2_lib.scala 409:30] + node _T_970 = bits(ic_miss_buff_half, 58, 58) @[el2_lib.scala 414:36] + _T_780[1] <= _T_970 @[el2_lib.scala 414:30] + node _T_971 = bits(ic_miss_buff_half, 59, 59) @[el2_lib.scala 408:36] + _T_774[32] <= _T_971 @[el2_lib.scala 408:30] + node _T_972 = bits(ic_miss_buff_half, 59, 59) @[el2_lib.scala 409:36] + _T_775[32] <= _T_972 @[el2_lib.scala 409:30] + node _T_973 = bits(ic_miss_buff_half, 59, 59) @[el2_lib.scala 414:36] + _T_780[2] <= _T_973 @[el2_lib.scala 414:30] + node _T_974 = bits(ic_miss_buff_half, 60, 60) @[el2_lib.scala 410:36] + _T_776[31] <= _T_974 @[el2_lib.scala 410:30] + node _T_975 = bits(ic_miss_buff_half, 60, 60) @[el2_lib.scala 414:36] + _T_780[3] <= _T_975 @[el2_lib.scala 414:30] + node _T_976 = bits(ic_miss_buff_half, 61, 61) @[el2_lib.scala 408:36] + _T_774[33] <= _T_976 @[el2_lib.scala 408:30] + node _T_977 = bits(ic_miss_buff_half, 61, 61) @[el2_lib.scala 410:36] + _T_776[32] <= _T_977 @[el2_lib.scala 410:30] + node _T_978 = bits(ic_miss_buff_half, 61, 61) @[el2_lib.scala 414:36] + _T_780[4] <= _T_978 @[el2_lib.scala 414:30] + node _T_979 = bits(ic_miss_buff_half, 62, 62) @[el2_lib.scala 409:36] + _T_775[33] <= _T_979 @[el2_lib.scala 409:30] + node _T_980 = bits(ic_miss_buff_half, 62, 62) @[el2_lib.scala 410:36] + _T_776[33] <= _T_980 @[el2_lib.scala 410:30] + node _T_981 = bits(ic_miss_buff_half, 62, 62) @[el2_lib.scala 414:36] + _T_780[5] <= _T_981 @[el2_lib.scala 414:30] + node _T_982 = bits(ic_miss_buff_half, 63, 63) @[el2_lib.scala 408:36] + _T_774[34] <= _T_982 @[el2_lib.scala 408:30] + node _T_983 = bits(ic_miss_buff_half, 63, 63) @[el2_lib.scala 409:36] + _T_775[34] <= _T_983 @[el2_lib.scala 409:30] + node _T_984 = bits(ic_miss_buff_half, 63, 63) @[el2_lib.scala 410:36] + _T_776[34] <= _T_984 @[el2_lib.scala 410:30] + node _T_985 = bits(ic_miss_buff_half, 63, 63) @[el2_lib.scala 414:36] + _T_780[6] <= _T_985 @[el2_lib.scala 414:30] + node _T_986 = cat(_T_780[2], _T_780[1]) @[el2_lib.scala 416:13] + node _T_987 = cat(_T_986, _T_780[0]) @[el2_lib.scala 416:13] + node _T_988 = cat(_T_780[4], _T_780[3]) @[el2_lib.scala 416:13] + node _T_989 = cat(_T_780[6], _T_780[5]) @[el2_lib.scala 416:13] + node _T_990 = cat(_T_989, _T_988) @[el2_lib.scala 416:13] + node _T_991 = cat(_T_990, _T_987) @[el2_lib.scala 416:13] + node _T_992 = xorr(_T_991) @[el2_lib.scala 416:20] + node _T_993 = cat(_T_779[2], _T_779[1]) @[el2_lib.scala 416:30] + node _T_994 = cat(_T_993, _T_779[0]) @[el2_lib.scala 416:30] + node _T_995 = cat(_T_779[4], _T_779[3]) @[el2_lib.scala 416:30] + node _T_996 = cat(_T_779[6], _T_779[5]) @[el2_lib.scala 416:30] + node _T_997 = cat(_T_996, _T_995) @[el2_lib.scala 416:30] + node _T_998 = cat(_T_997, _T_994) @[el2_lib.scala 416:30] + node _T_999 = cat(_T_779[8], _T_779[7]) @[el2_lib.scala 416:30] + node _T_1000 = cat(_T_779[10], _T_779[9]) @[el2_lib.scala 416:30] + node _T_1001 = cat(_T_1000, _T_999) @[el2_lib.scala 416:30] + node _T_1002 = cat(_T_779[12], _T_779[11]) @[el2_lib.scala 416:30] + node _T_1003 = cat(_T_779[14], _T_779[13]) @[el2_lib.scala 416:30] + node _T_1004 = cat(_T_1003, _T_1002) @[el2_lib.scala 416:30] + node _T_1005 = cat(_T_1004, _T_1001) @[el2_lib.scala 416:30] + node _T_1006 = cat(_T_1005, _T_998) @[el2_lib.scala 416:30] + node _T_1007 = cat(_T_779[16], _T_779[15]) @[el2_lib.scala 416:30] + node _T_1008 = cat(_T_779[18], _T_779[17]) @[el2_lib.scala 416:30] + node _T_1009 = cat(_T_1008, _T_1007) @[el2_lib.scala 416:30] + node _T_1010 = cat(_T_779[20], _T_779[19]) @[el2_lib.scala 416:30] + node _T_1011 = cat(_T_779[22], _T_779[21]) @[el2_lib.scala 416:30] + node _T_1012 = cat(_T_1011, _T_1010) @[el2_lib.scala 416:30] + node _T_1013 = cat(_T_1012, _T_1009) @[el2_lib.scala 416:30] + node _T_1014 = cat(_T_779[24], _T_779[23]) @[el2_lib.scala 416:30] + node _T_1015 = cat(_T_779[26], _T_779[25]) @[el2_lib.scala 416:30] + node _T_1016 = cat(_T_1015, _T_1014) @[el2_lib.scala 416:30] + node _T_1017 = cat(_T_779[28], _T_779[27]) @[el2_lib.scala 416:30] + node _T_1018 = cat(_T_779[30], _T_779[29]) @[el2_lib.scala 416:30] + node _T_1019 = cat(_T_1018, _T_1017) @[el2_lib.scala 416:30] + node _T_1020 = cat(_T_1019, _T_1016) @[el2_lib.scala 416:30] + node _T_1021 = cat(_T_1020, _T_1013) @[el2_lib.scala 416:30] + node _T_1022 = cat(_T_1021, _T_1006) @[el2_lib.scala 416:30] + node _T_1023 = xorr(_T_1022) @[el2_lib.scala 416:37] + node _T_1024 = cat(_T_778[2], _T_778[1]) @[el2_lib.scala 416:47] + node _T_1025 = cat(_T_1024, _T_778[0]) @[el2_lib.scala 416:47] + node _T_1026 = cat(_T_778[4], _T_778[3]) @[el2_lib.scala 416:47] + node _T_1027 = cat(_T_778[6], _T_778[5]) @[el2_lib.scala 416:47] + node _T_1028 = cat(_T_1027, _T_1026) @[el2_lib.scala 416:47] + node _T_1029 = cat(_T_1028, _T_1025) @[el2_lib.scala 416:47] + node _T_1030 = cat(_T_778[8], _T_778[7]) @[el2_lib.scala 416:47] + node _T_1031 = cat(_T_778[10], _T_778[9]) @[el2_lib.scala 416:47] + node _T_1032 = cat(_T_1031, _T_1030) @[el2_lib.scala 416:47] + node _T_1033 = cat(_T_778[12], _T_778[11]) @[el2_lib.scala 416:47] + node _T_1034 = cat(_T_778[14], _T_778[13]) @[el2_lib.scala 416:47] + node _T_1035 = cat(_T_1034, _T_1033) @[el2_lib.scala 416:47] + node _T_1036 = cat(_T_1035, _T_1032) @[el2_lib.scala 416:47] + node _T_1037 = cat(_T_1036, _T_1029) @[el2_lib.scala 416:47] + node _T_1038 = cat(_T_778[16], _T_778[15]) @[el2_lib.scala 416:47] + node _T_1039 = cat(_T_778[18], _T_778[17]) @[el2_lib.scala 416:47] + node _T_1040 = cat(_T_1039, _T_1038) @[el2_lib.scala 416:47] + node _T_1041 = cat(_T_778[20], _T_778[19]) @[el2_lib.scala 416:47] + node _T_1042 = cat(_T_778[22], _T_778[21]) @[el2_lib.scala 416:47] + node _T_1043 = cat(_T_1042, _T_1041) @[el2_lib.scala 416:47] + node _T_1044 = cat(_T_1043, _T_1040) @[el2_lib.scala 416:47] + node _T_1045 = cat(_T_778[24], _T_778[23]) @[el2_lib.scala 416:47] + node _T_1046 = cat(_T_778[26], _T_778[25]) @[el2_lib.scala 416:47] + node _T_1047 = cat(_T_1046, _T_1045) @[el2_lib.scala 416:47] + node _T_1048 = cat(_T_778[28], _T_778[27]) @[el2_lib.scala 416:47] + node _T_1049 = cat(_T_778[30], _T_778[29]) @[el2_lib.scala 416:47] + node _T_1050 = cat(_T_1049, _T_1048) @[el2_lib.scala 416:47] + node _T_1051 = cat(_T_1050, _T_1047) @[el2_lib.scala 416:47] + node _T_1052 = cat(_T_1051, _T_1044) @[el2_lib.scala 416:47] + node _T_1053 = cat(_T_1052, _T_1037) @[el2_lib.scala 416:47] + node _T_1054 = xorr(_T_1053) @[el2_lib.scala 416:54] + node _T_1055 = cat(_T_777[2], _T_777[1]) @[el2_lib.scala 416:64] + node _T_1056 = cat(_T_1055, _T_777[0]) @[el2_lib.scala 416:64] + node _T_1057 = cat(_T_777[4], _T_777[3]) @[el2_lib.scala 416:64] + node _T_1058 = cat(_T_777[6], _T_777[5]) @[el2_lib.scala 416:64] + node _T_1059 = cat(_T_1058, _T_1057) @[el2_lib.scala 416:64] + node _T_1060 = cat(_T_1059, _T_1056) @[el2_lib.scala 416:64] + node _T_1061 = cat(_T_777[8], _T_777[7]) @[el2_lib.scala 416:64] + node _T_1062 = cat(_T_777[10], _T_777[9]) @[el2_lib.scala 416:64] + node _T_1063 = cat(_T_1062, _T_1061) @[el2_lib.scala 416:64] + node _T_1064 = cat(_T_777[12], _T_777[11]) @[el2_lib.scala 416:64] + node _T_1065 = cat(_T_777[14], _T_777[13]) @[el2_lib.scala 416:64] + node _T_1066 = cat(_T_1065, _T_1064) @[el2_lib.scala 416:64] + node _T_1067 = cat(_T_1066, _T_1063) @[el2_lib.scala 416:64] + node _T_1068 = cat(_T_1067, _T_1060) @[el2_lib.scala 416:64] + node _T_1069 = cat(_T_777[16], _T_777[15]) @[el2_lib.scala 416:64] + node _T_1070 = cat(_T_777[18], _T_777[17]) @[el2_lib.scala 416:64] + node _T_1071 = cat(_T_1070, _T_1069) @[el2_lib.scala 416:64] + node _T_1072 = cat(_T_777[20], _T_777[19]) @[el2_lib.scala 416:64] + node _T_1073 = cat(_T_777[22], _T_777[21]) @[el2_lib.scala 416:64] + node _T_1074 = cat(_T_1073, _T_1072) @[el2_lib.scala 416:64] + node _T_1075 = cat(_T_1074, _T_1071) @[el2_lib.scala 416:64] + node _T_1076 = cat(_T_777[24], _T_777[23]) @[el2_lib.scala 416:64] + node _T_1077 = cat(_T_777[26], _T_777[25]) @[el2_lib.scala 416:64] + node _T_1078 = cat(_T_1077, _T_1076) @[el2_lib.scala 416:64] + node _T_1079 = cat(_T_777[28], _T_777[27]) @[el2_lib.scala 416:64] + node _T_1080 = cat(_T_777[30], _T_777[29]) @[el2_lib.scala 416:64] + node _T_1081 = cat(_T_1080, _T_1079) @[el2_lib.scala 416:64] + node _T_1082 = cat(_T_1081, _T_1078) @[el2_lib.scala 416:64] + node _T_1083 = cat(_T_1082, _T_1075) @[el2_lib.scala 416:64] + node _T_1084 = cat(_T_1083, _T_1068) @[el2_lib.scala 416:64] + node _T_1085 = xorr(_T_1084) @[el2_lib.scala 416:71] + node _T_1086 = cat(_T_776[1], _T_776[0]) @[el2_lib.scala 416:81] + node _T_1087 = cat(_T_776[3], _T_776[2]) @[el2_lib.scala 416:81] + node _T_1088 = cat(_T_1087, _T_1086) @[el2_lib.scala 416:81] + node _T_1089 = cat(_T_776[5], _T_776[4]) @[el2_lib.scala 416:81] + node _T_1090 = cat(_T_776[7], _T_776[6]) @[el2_lib.scala 416:81] + node _T_1091 = cat(_T_1090, _T_1089) @[el2_lib.scala 416:81] + node _T_1092 = cat(_T_1091, _T_1088) @[el2_lib.scala 416:81] + node _T_1093 = cat(_T_776[9], _T_776[8]) @[el2_lib.scala 416:81] + node _T_1094 = cat(_T_776[11], _T_776[10]) @[el2_lib.scala 416:81] + node _T_1095 = cat(_T_1094, _T_1093) @[el2_lib.scala 416:81] + node _T_1096 = cat(_T_776[13], _T_776[12]) @[el2_lib.scala 416:81] + node _T_1097 = cat(_T_776[16], _T_776[15]) @[el2_lib.scala 416:81] + node _T_1098 = cat(_T_1097, _T_776[14]) @[el2_lib.scala 416:81] + node _T_1099 = cat(_T_1098, _T_1096) @[el2_lib.scala 416:81] + node _T_1100 = cat(_T_1099, _T_1095) @[el2_lib.scala 416:81] + node _T_1101 = cat(_T_1100, _T_1092) @[el2_lib.scala 416:81] + node _T_1102 = cat(_T_776[18], _T_776[17]) @[el2_lib.scala 416:81] + node _T_1103 = cat(_T_776[20], _T_776[19]) @[el2_lib.scala 416:81] + node _T_1104 = cat(_T_1103, _T_1102) @[el2_lib.scala 416:81] + node _T_1105 = cat(_T_776[22], _T_776[21]) @[el2_lib.scala 416:81] + node _T_1106 = cat(_T_776[25], _T_776[24]) @[el2_lib.scala 416:81] + node _T_1107 = cat(_T_1106, _T_776[23]) @[el2_lib.scala 416:81] + node _T_1108 = cat(_T_1107, _T_1105) @[el2_lib.scala 416:81] + node _T_1109 = cat(_T_1108, _T_1104) @[el2_lib.scala 416:81] + node _T_1110 = cat(_T_776[27], _T_776[26]) @[el2_lib.scala 416:81] + node _T_1111 = cat(_T_776[29], _T_776[28]) @[el2_lib.scala 416:81] + node _T_1112 = cat(_T_1111, _T_1110) @[el2_lib.scala 416:81] + node _T_1113 = cat(_T_776[31], _T_776[30]) @[el2_lib.scala 416:81] + node _T_1114 = cat(_T_776[34], _T_776[33]) @[el2_lib.scala 416:81] + node _T_1115 = cat(_T_1114, _T_776[32]) @[el2_lib.scala 416:81] + node _T_1116 = cat(_T_1115, _T_1113) @[el2_lib.scala 416:81] + node _T_1117 = cat(_T_1116, _T_1112) @[el2_lib.scala 416:81] + node _T_1118 = cat(_T_1117, _T_1109) @[el2_lib.scala 416:81] + node _T_1119 = cat(_T_1118, _T_1101) @[el2_lib.scala 416:81] + node _T_1120 = xorr(_T_1119) @[el2_lib.scala 416:88] + node _T_1121 = cat(_T_775[1], _T_775[0]) @[el2_lib.scala 416:98] + node _T_1122 = cat(_T_775[3], _T_775[2]) @[el2_lib.scala 416:98] + node _T_1123 = cat(_T_1122, _T_1121) @[el2_lib.scala 416:98] + node _T_1124 = cat(_T_775[5], _T_775[4]) @[el2_lib.scala 416:98] + node _T_1125 = cat(_T_775[7], _T_775[6]) @[el2_lib.scala 416:98] + node _T_1126 = cat(_T_1125, _T_1124) @[el2_lib.scala 416:98] + node _T_1127 = cat(_T_1126, _T_1123) @[el2_lib.scala 416:98] + node _T_1128 = cat(_T_775[9], _T_775[8]) @[el2_lib.scala 416:98] + node _T_1129 = cat(_T_775[11], _T_775[10]) @[el2_lib.scala 416:98] + node _T_1130 = cat(_T_1129, _T_1128) @[el2_lib.scala 416:98] + node _T_1131 = cat(_T_775[13], _T_775[12]) @[el2_lib.scala 416:98] + node _T_1132 = cat(_T_775[16], _T_775[15]) @[el2_lib.scala 416:98] + node _T_1133 = cat(_T_1132, _T_775[14]) @[el2_lib.scala 416:98] + node _T_1134 = cat(_T_1133, _T_1131) @[el2_lib.scala 416:98] + node _T_1135 = cat(_T_1134, _T_1130) @[el2_lib.scala 416:98] + node _T_1136 = cat(_T_1135, _T_1127) @[el2_lib.scala 416:98] + node _T_1137 = cat(_T_775[18], _T_775[17]) @[el2_lib.scala 416:98] + node _T_1138 = cat(_T_775[20], _T_775[19]) @[el2_lib.scala 416:98] + node _T_1139 = cat(_T_1138, _T_1137) @[el2_lib.scala 416:98] + node _T_1140 = cat(_T_775[22], _T_775[21]) @[el2_lib.scala 416:98] + node _T_1141 = cat(_T_775[25], _T_775[24]) @[el2_lib.scala 416:98] + node _T_1142 = cat(_T_1141, _T_775[23]) @[el2_lib.scala 416:98] + node _T_1143 = cat(_T_1142, _T_1140) @[el2_lib.scala 416:98] + node _T_1144 = cat(_T_1143, _T_1139) @[el2_lib.scala 416:98] + node _T_1145 = cat(_T_775[27], _T_775[26]) @[el2_lib.scala 416:98] + node _T_1146 = cat(_T_775[29], _T_775[28]) @[el2_lib.scala 416:98] + node _T_1147 = cat(_T_1146, _T_1145) @[el2_lib.scala 416:98] + node _T_1148 = cat(_T_775[31], _T_775[30]) @[el2_lib.scala 416:98] + node _T_1149 = cat(_T_775[34], _T_775[33]) @[el2_lib.scala 416:98] + node _T_1150 = cat(_T_1149, _T_775[32]) @[el2_lib.scala 416:98] + node _T_1151 = cat(_T_1150, _T_1148) @[el2_lib.scala 416:98] + node _T_1152 = cat(_T_1151, _T_1147) @[el2_lib.scala 416:98] + node _T_1153 = cat(_T_1152, _T_1144) @[el2_lib.scala 416:98] + node _T_1154 = cat(_T_1153, _T_1136) @[el2_lib.scala 416:98] + node _T_1155 = xorr(_T_1154) @[el2_lib.scala 416:105] + node _T_1156 = cat(_T_774[1], _T_774[0]) @[el2_lib.scala 416:115] + node _T_1157 = cat(_T_774[3], _T_774[2]) @[el2_lib.scala 416:115] + node _T_1158 = cat(_T_1157, _T_1156) @[el2_lib.scala 416:115] + node _T_1159 = cat(_T_774[5], _T_774[4]) @[el2_lib.scala 416:115] + node _T_1160 = cat(_T_774[7], _T_774[6]) @[el2_lib.scala 416:115] + node _T_1161 = cat(_T_1160, _T_1159) @[el2_lib.scala 416:115] + node _T_1162 = cat(_T_1161, _T_1158) @[el2_lib.scala 416:115] + node _T_1163 = cat(_T_774[9], _T_774[8]) @[el2_lib.scala 416:115] + node _T_1164 = cat(_T_774[11], _T_774[10]) @[el2_lib.scala 416:115] + node _T_1165 = cat(_T_1164, _T_1163) @[el2_lib.scala 416:115] + node _T_1166 = cat(_T_774[13], _T_774[12]) @[el2_lib.scala 416:115] + node _T_1167 = cat(_T_774[16], _T_774[15]) @[el2_lib.scala 416:115] + node _T_1168 = cat(_T_1167, _T_774[14]) @[el2_lib.scala 416:115] + node _T_1169 = cat(_T_1168, _T_1166) @[el2_lib.scala 416:115] + node _T_1170 = cat(_T_1169, _T_1165) @[el2_lib.scala 416:115] + node _T_1171 = cat(_T_1170, _T_1162) @[el2_lib.scala 416:115] + node _T_1172 = cat(_T_774[18], _T_774[17]) @[el2_lib.scala 416:115] + node _T_1173 = cat(_T_774[20], _T_774[19]) @[el2_lib.scala 416:115] + node _T_1174 = cat(_T_1173, _T_1172) @[el2_lib.scala 416:115] + node _T_1175 = cat(_T_774[22], _T_774[21]) @[el2_lib.scala 416:115] + node _T_1176 = cat(_T_774[25], _T_774[24]) @[el2_lib.scala 416:115] + node _T_1177 = cat(_T_1176, _T_774[23]) @[el2_lib.scala 416:115] + node _T_1178 = cat(_T_1177, _T_1175) @[el2_lib.scala 416:115] + node _T_1179 = cat(_T_1178, _T_1174) @[el2_lib.scala 416:115] + node _T_1180 = cat(_T_774[27], _T_774[26]) @[el2_lib.scala 416:115] + node _T_1181 = cat(_T_774[29], _T_774[28]) @[el2_lib.scala 416:115] + node _T_1182 = cat(_T_1181, _T_1180) @[el2_lib.scala 416:115] + node _T_1183 = cat(_T_774[31], _T_774[30]) @[el2_lib.scala 416:115] + node _T_1184 = cat(_T_774[34], _T_774[33]) @[el2_lib.scala 416:115] + node _T_1185 = cat(_T_1184, _T_774[32]) @[el2_lib.scala 416:115] + node _T_1186 = cat(_T_1185, _T_1183) @[el2_lib.scala 416:115] + node _T_1187 = cat(_T_1186, _T_1182) @[el2_lib.scala 416:115] + node _T_1188 = cat(_T_1187, _T_1179) @[el2_lib.scala 416:115] + node _T_1189 = cat(_T_1188, _T_1171) @[el2_lib.scala 416:115] + node _T_1190 = xorr(_T_1189) @[el2_lib.scala 416:122] + node _T_1191 = cat(_T_1120, _T_1155) @[Cat.scala 29:58] + node _T_1192 = cat(_T_1191, _T_1190) @[Cat.scala 29:58] + node _T_1193 = cat(_T_1054, _T_1085) @[Cat.scala 29:58] + node _T_1194 = cat(_T_992, _T_1023) @[Cat.scala 29:58] + node _T_1195 = cat(_T_1194, _T_1193) @[Cat.scala 29:58] + node ic_miss_buff_ecc = cat(_T_1195, _T_1192) @[Cat.scala 29:58] + wire ic_wr_16bytes_data : UInt<142> + ic_wr_16bytes_data <= UInt<1>("h00") + node _T_1196 = bits(ic_wr_16bytes_data, 70, 0) @[el2_ifu_mem_ctl.scala 346:72] + node _T_1197 = bits(ic_wr_16bytes_data, 141, 71) @[el2_ifu_mem_ctl.scala 346:72] + io.ic_wr_data[0] <= _T_1196 @[el2_ifu_mem_ctl.scala 346:17] + io.ic_wr_data[1] <= _T_1197 @[el2_ifu_mem_ctl.scala 346:17] + io.ic_debug_wr_data <= io.dec_tlu_ic_diag_pkt.icache_wrdata @[el2_ifu_mem_ctl.scala 347:23] + wire ic_rd_parity_final_err : UInt<1> + ic_rd_parity_final_err <= UInt<1>("h00") + node _T_1198 = orr(io.ic_eccerr) @[el2_ifu_mem_ctl.scala 349:56] + node _T_1199 = and(_T_1198, ic_act_hit_f) @[el2_ifu_mem_ctl.scala 349:83] + node _T_1200 = or(_T_1199, ic_rd_parity_final_err) @[el2_ifu_mem_ctl.scala 349:99] + io.ic_error_start <= _T_1200 @[el2_ifu_mem_ctl.scala 349:21] + wire ic_debug_tag_val_rd_out : UInt<1> + ic_debug_tag_val_rd_out <= UInt<1>("h00") + wire ic_debug_ict_array_sel_ff : UInt<1> + ic_debug_ict_array_sel_ff <= UInt<1>("h00") + node _T_1201 = bits(ic_debug_ict_array_sel_ff, 0, 0) @[el2_ifu_mem_ctl.scala 352:63] + node _T_1202 = bits(io.ictag_debug_rd_data, 25, 21) @[el2_ifu_mem_ctl.scala 352:121] + node _T_1203 = bits(io.ictag_debug_rd_data, 20, 0) @[el2_ifu_mem_ctl.scala 352:161] + node _T_1204 = cat(UInt<3>("h00"), ic_debug_tag_val_rd_out) @[Cat.scala 29:58] + node _T_1205 = cat(UInt<6>("h00"), way_status) @[Cat.scala 29:58] + node _T_1206 = cat(_T_1205, _T_1204) @[Cat.scala 29:58] + node _T_1207 = cat(UInt<32>("h00"), _T_1203) @[Cat.scala 29:58] + node _T_1208 = cat(UInt<2>("h00"), _T_1202) @[Cat.scala 29:58] + node _T_1209 = cat(_T_1208, _T_1207) @[Cat.scala 29:58] + node _T_1210 = cat(_T_1209, _T_1206) @[Cat.scala 29:58] + node ifu_ic_debug_rd_data_in = mux(_T_1201, _T_1210, io.ic_debug_rd_data) @[el2_ifu_mem_ctl.scala 352:36] + reg _T_1211 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 355:63] + _T_1211 <= ifu_ic_debug_rd_data_in @[el2_ifu_mem_ctl.scala 355:63] + io.ifu_ic_debug_rd_data <= _T_1211 @[el2_ifu_mem_ctl.scala 355:27] + node _T_1212 = bits(ifu_bus_rdata_ff, 15, 0) @[el2_ifu_mem_ctl.scala 356:74] + node _T_1213 = xorr(_T_1212) @[el2_lib.scala 204:13] + node _T_1214 = bits(ifu_bus_rdata_ff, 31, 16) @[el2_ifu_mem_ctl.scala 356:74] + node _T_1215 = xorr(_T_1214) @[el2_lib.scala 204:13] + node _T_1216 = bits(ifu_bus_rdata_ff, 47, 32) @[el2_ifu_mem_ctl.scala 356:74] + node _T_1217 = xorr(_T_1216) @[el2_lib.scala 204:13] + node _T_1218 = bits(ifu_bus_rdata_ff, 63, 48) @[el2_ifu_mem_ctl.scala 356:74] + node _T_1219 = xorr(_T_1218) @[el2_lib.scala 204:13] + node _T_1220 = cat(_T_1219, _T_1217) @[Cat.scala 29:58] + node _T_1221 = cat(_T_1220, _T_1215) @[Cat.scala 29:58] + node ic_wr_parity = cat(_T_1221, _T_1213) @[Cat.scala 29:58] + node _T_1222 = bits(ic_miss_buff_half, 15, 0) @[el2_ifu_mem_ctl.scala 357:82] + node _T_1223 = xorr(_T_1222) @[el2_lib.scala 204:13] + node _T_1224 = bits(ic_miss_buff_half, 31, 16) @[el2_ifu_mem_ctl.scala 357:82] + node _T_1225 = xorr(_T_1224) @[el2_lib.scala 204:13] + node _T_1226 = bits(ic_miss_buff_half, 47, 32) @[el2_ifu_mem_ctl.scala 357:82] + node _T_1227 = xorr(_T_1226) @[el2_lib.scala 204:13] + node _T_1228 = bits(ic_miss_buff_half, 63, 48) @[el2_ifu_mem_ctl.scala 357:82] + node _T_1229 = xorr(_T_1228) @[el2_lib.scala 204:13] + node _T_1230 = cat(_T_1229, _T_1227) @[Cat.scala 29:58] + node _T_1231 = cat(_T_1230, _T_1225) @[Cat.scala 29:58] + node ic_miss_buff_parity = cat(_T_1231, _T_1223) @[Cat.scala 29:58] + node _T_1232 = bits(ifu_bus_rid_ff, 0, 0) @[el2_ifu_mem_ctl.scala 359:43] + node _T_1233 = bits(_T_1232, 0, 0) @[el2_ifu_mem_ctl.scala 359:47] + node _T_1234 = cat(ic_miss_buff_ecc, ic_miss_buff_half) @[Cat.scala 29:58] + node _T_1235 = cat(ic_wr_ecc, ifu_bus_rdata_ff) @[Cat.scala 29:58] + node _T_1236 = cat(_T_1235, _T_1234) @[Cat.scala 29:58] + node _T_1237 = cat(ic_wr_ecc, ifu_bus_rdata_ff) @[Cat.scala 29:58] + node _T_1238 = cat(ic_miss_buff_ecc, ic_miss_buff_half) @[Cat.scala 29:58] + node _T_1239 = cat(_T_1238, _T_1237) @[Cat.scala 29:58] + node _T_1240 = mux(_T_1233, _T_1236, _T_1239) @[el2_ifu_mem_ctl.scala 359:28] + ic_wr_16bytes_data <= _T_1240 @[el2_ifu_mem_ctl.scala 359:22] + wire bus_ifu_wr_data_error_ff : UInt<1> + bus_ifu_wr_data_error_ff <= UInt<1>("h00") + wire ifu_wr_data_comb_err_ff : UInt<1> + ifu_wr_data_comb_err_ff <= UInt<1>("h00") + wire reset_beat_cnt : UInt<1> + reset_beat_cnt <= UInt<1>("h00") + node _T_1241 = or(bus_ifu_wr_data_error_ff, ifu_wr_data_comb_err_ff) @[el2_ifu_mem_ctl.scala 366:53] + node _T_1242 = eq(reset_beat_cnt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 366:82] + node ifu_wr_cumulative_err = and(_T_1241, _T_1242) @[el2_ifu_mem_ctl.scala 366:80] + node _T_1243 = or(bus_ifu_wr_data_error_ff, ifu_wr_data_comb_err_ff) @[el2_ifu_mem_ctl.scala 367:55] + ifu_wr_cumulative_err_data <= _T_1243 @[el2_ifu_mem_ctl.scala 367:30] + reg _T_1244 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 368:61] + _T_1244 <= ifu_wr_cumulative_err @[el2_ifu_mem_ctl.scala 368:61] + ifu_wr_data_comb_err_ff <= _T_1244 @[el2_ifu_mem_ctl.scala 368:27] + wire ic_crit_wd_rdy : UInt<1> + ic_crit_wd_rdy <= UInt<1>("h00") + wire ifu_byp_data_err_new : UInt<1> + ifu_byp_data_err_new <= UInt<1>("h00") + node _T_1245 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 371:51] + node _T_1246 = or(ic_crit_wd_rdy, _T_1245) @[el2_ifu_mem_ctl.scala 371:38] + node _T_1247 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 371:77] + node _T_1248 = or(_T_1246, _T_1247) @[el2_ifu_mem_ctl.scala 371:64] + node _T_1249 = eq(ifu_byp_data_err_new, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 371:98] + node sel_byp_data = and(_T_1248, _T_1249) @[el2_ifu_mem_ctl.scala 371:96] + node _T_1250 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 372:51] + node _T_1251 = or(ic_crit_wd_rdy, _T_1250) @[el2_ifu_mem_ctl.scala 372:38] + node _T_1252 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 372:77] + node _T_1253 = or(_T_1251, _T_1252) @[el2_ifu_mem_ctl.scala 372:64] + node _T_1254 = eq(_T_1253, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 372:21] + node _T_1255 = eq(fetch_req_iccm_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 372:98] + node sel_ic_data = and(_T_1254, _T_1255) @[el2_ifu_mem_ctl.scala 372:96] + wire ic_byp_data_only_new : UInt<80> + ic_byp_data_only_new <= UInt<1>("h00") + node _T_1256 = or(fetch_req_iccm_f, sel_ic_data) @[el2_ifu_mem_ctl.scala 376:81] + node _T_1257 = or(sel_byp_data, _T_1256) @[el2_ifu_mem_ctl.scala 376:47] + node _T_1258 = bits(_T_1257, 0, 0) @[el2_ifu_mem_ctl.scala 376:140] + node _T_1259 = bits(fetch_req_iccm_f, 0, 0) @[Bitwise.scala 72:15] + node _T_1260 = mux(_T_1259, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] + node _T_1261 = and(_T_1260, io.iccm_rd_data) @[el2_ifu_mem_ctl.scala 378:69] + node _T_1262 = bits(sel_byp_data, 0, 0) @[Bitwise.scala 72:15] + node _T_1263 = mux(_T_1262, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] + node _T_1264 = and(_T_1263, ic_byp_data_only_new) @[el2_ifu_mem_ctl.scala 378:114] + node ic_premux_data_temp = or(_T_1261, _T_1264) @[el2_ifu_mem_ctl.scala 378:88] + node ic_sel_premux_data_temp = or(fetch_req_iccm_f, sel_byp_data) @[el2_ifu_mem_ctl.scala 380:63] + io.ic_premux_data <= ic_premux_data_temp @[el2_ifu_mem_ctl.scala 381:21] + io.ic_sel_premux_data <= ic_sel_premux_data_temp @[el2_ifu_mem_ctl.scala 382:25] + node ifc_bus_acc_fault_f = and(ic_byp_hit_f, ifu_byp_data_err_new) @[el2_ifu_mem_ctl.scala 383:42] + io.ic_data_f <= io.ic_rd_data @[el2_ifu_mem_ctl.scala 384:16] + node _T_1265 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 385:40] + node fetch_req_f_qual = and(io.ic_hit_f, _T_1265) @[el2_ifu_mem_ctl.scala 385:38] + wire ifc_region_acc_fault_memory_f : UInt<1> + ifc_region_acc_fault_memory_f <= UInt<1>("h00") + node _T_1266 = or(ifc_region_acc_fault_final_f, ifc_bus_acc_fault_f) @[el2_ifu_mem_ctl.scala 387:57] + node _T_1267 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 387:82] + node _T_1268 = and(_T_1266, _T_1267) @[el2_ifu_mem_ctl.scala 387:80] + io.ic_access_fault_f <= _T_1268 @[el2_ifu_mem_ctl.scala 387:24] + node _T_1269 = bits(io.iccm_rd_ecc_double_err, 0, 0) @[el2_ifu_mem_ctl.scala 388:62] + node _T_1270 = bits(ifc_region_acc_fault_f, 0, 0) @[el2_ifu_mem_ctl.scala 389:32] + node _T_1271 = bits(ifc_region_acc_fault_memory_f, 0, 0) @[el2_ifu_mem_ctl.scala 390:47] + node _T_1272 = mux(_T_1271, UInt<2>("h03"), UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 390:10] + node _T_1273 = mux(_T_1270, UInt<2>("h02"), _T_1272) @[el2_ifu_mem_ctl.scala 389:8] + node _T_1274 = mux(_T_1269, UInt<1>("h01"), _T_1273) @[el2_ifu_mem_ctl.scala 388:35] + io.ic_access_fault_type_f <= _T_1274 @[el2_ifu_mem_ctl.scala 388:29] + node _T_1275 = and(fetch_req_f_qual, io.ifu_bp_inst_mask_f) @[el2_ifu_mem_ctl.scala 391:45] + node _T_1276 = mux(UInt<1>("h01"), UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] + node _T_1277 = eq(vaddr_f, _T_1276) @[el2_ifu_mem_ctl.scala 391:80] + node _T_1278 = eq(_T_1277, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 391:71] + node _T_1279 = and(_T_1275, _T_1278) @[el2_ifu_mem_ctl.scala 391:69] + node _T_1280 = neq(err_stop_state, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 391:131] + node _T_1281 = and(_T_1279, _T_1280) @[el2_ifu_mem_ctl.scala 391:114] + node _T_1282 = cat(_T_1281, fetch_req_f_qual) @[Cat.scala 29:58] + io.ic_fetch_val_f <= _T_1282 @[el2_ifu_mem_ctl.scala 391:21] + node _T_1283 = bits(io.ic_data_f, 1, 0) @[el2_ifu_mem_ctl.scala 392:36] + node two_byte_instr = neq(_T_1283, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 392:42] + wire ic_miss_buff_data_in : UInt<64> + ic_miss_buff_data_in <= UInt<1>("h00") + wire ifu_bus_rsp_tag : UInt<3> + ifu_bus_rsp_tag <= UInt<1>("h00") + wire bus_ifu_wr_en : UInt<1> + bus_ifu_wr_en <= UInt<1>("h00") + node _T_1284 = eq(ifu_bus_rsp_tag, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 398:91] + node write_fill_data_0 = and(bus_ifu_wr_en, _T_1284) @[el2_ifu_mem_ctl.scala 398:73] + node _T_1285 = eq(ifu_bus_rsp_tag, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 398:91] + node write_fill_data_1 = and(bus_ifu_wr_en, _T_1285) @[el2_ifu_mem_ctl.scala 398:73] + node _T_1286 = eq(ifu_bus_rsp_tag, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 398:91] + node write_fill_data_2 = and(bus_ifu_wr_en, _T_1286) @[el2_ifu_mem_ctl.scala 398:73] + node _T_1287 = eq(ifu_bus_rsp_tag, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 398:91] + node write_fill_data_3 = and(bus_ifu_wr_en, _T_1287) @[el2_ifu_mem_ctl.scala 398:73] + node _T_1288 = eq(ifu_bus_rsp_tag, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 398:91] + node write_fill_data_4 = and(bus_ifu_wr_en, _T_1288) @[el2_ifu_mem_ctl.scala 398:73] + node _T_1289 = eq(ifu_bus_rsp_tag, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 398:91] + node write_fill_data_5 = and(bus_ifu_wr_en, _T_1289) @[el2_ifu_mem_ctl.scala 398:73] + node _T_1290 = eq(ifu_bus_rsp_tag, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 398:91] + node write_fill_data_6 = and(bus_ifu_wr_en, _T_1290) @[el2_ifu_mem_ctl.scala 398:73] + node _T_1291 = eq(ifu_bus_rsp_tag, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 398:91] + node write_fill_data_7 = and(bus_ifu_wr_en, _T_1291) @[el2_ifu_mem_ctl.scala 398:73] + wire ic_miss_buff_data : UInt<32>[16] @[el2_ifu_mem_ctl.scala 399:31] + inst rvclkhdr_4 of rvclkhdr_4 @[el2_lib.scala 483:22] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= reset + rvclkhdr_4.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_4.io.en <= write_fill_data_0 @[el2_lib.scala 485:16] + rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_5 of rvclkhdr_5 @[el2_lib.scala 483:22] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= reset + rvclkhdr_5.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_5.io.en <= write_fill_data_1 @[el2_lib.scala 485:16] + rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_6 of rvclkhdr_6 @[el2_lib.scala 483:22] + rvclkhdr_6.clock <= clock + rvclkhdr_6.reset <= reset + rvclkhdr_6.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_6.io.en <= write_fill_data_2 @[el2_lib.scala 485:16] + rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_7 of rvclkhdr_7 @[el2_lib.scala 483:22] + rvclkhdr_7.clock <= clock + rvclkhdr_7.reset <= reset + rvclkhdr_7.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_7.io.en <= write_fill_data_3 @[el2_lib.scala 485:16] + rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_8 of rvclkhdr_8 @[el2_lib.scala 483:22] + rvclkhdr_8.clock <= clock + rvclkhdr_8.reset <= reset + rvclkhdr_8.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_8.io.en <= write_fill_data_4 @[el2_lib.scala 485:16] + rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_9 of rvclkhdr_9 @[el2_lib.scala 483:22] + rvclkhdr_9.clock <= clock + rvclkhdr_9.reset <= reset + rvclkhdr_9.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_9.io.en <= write_fill_data_5 @[el2_lib.scala 485:16] + rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_10 of rvclkhdr_10 @[el2_lib.scala 483:22] + rvclkhdr_10.clock <= clock + rvclkhdr_10.reset <= reset + rvclkhdr_10.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_10.io.en <= write_fill_data_6 @[el2_lib.scala 485:16] + rvclkhdr_10.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_11 of rvclkhdr_11 @[el2_lib.scala 483:22] + rvclkhdr_11.clock <= clock + rvclkhdr_11.reset <= reset + rvclkhdr_11.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_11.io.en <= write_fill_data_7 @[el2_lib.scala 485:16] + rvclkhdr_11.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + node _T_1292 = bits(ic_miss_buff_data_in, 31, 0) @[el2_ifu_mem_ctl.scala 402:88] + reg _T_1293 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 402:67] + _T_1293 <= _T_1292 @[el2_ifu_mem_ctl.scala 402:67] + ic_miss_buff_data[0] <= _T_1293 @[el2_ifu_mem_ctl.scala 402:28] + node _T_1294 = bits(ic_miss_buff_data_in, 63, 32) @[el2_ifu_mem_ctl.scala 403:90] + reg _T_1295 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 403:69] + _T_1295 <= _T_1294 @[el2_ifu_mem_ctl.scala 403:69] + ic_miss_buff_data[1] <= _T_1295 @[el2_ifu_mem_ctl.scala 403:30] + inst rvclkhdr_12 of rvclkhdr_12 @[el2_lib.scala 483:22] + rvclkhdr_12.clock <= clock + rvclkhdr_12.reset <= reset + rvclkhdr_12.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_12.io.en <= write_fill_data_0 @[el2_lib.scala 485:16] + rvclkhdr_12.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_13 of rvclkhdr_13 @[el2_lib.scala 483:22] + rvclkhdr_13.clock <= clock + rvclkhdr_13.reset <= reset + rvclkhdr_13.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_13.io.en <= write_fill_data_1 @[el2_lib.scala 485:16] + rvclkhdr_13.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_14 of rvclkhdr_14 @[el2_lib.scala 483:22] + rvclkhdr_14.clock <= clock + rvclkhdr_14.reset <= reset + rvclkhdr_14.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_14.io.en <= write_fill_data_2 @[el2_lib.scala 485:16] + rvclkhdr_14.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_15 of rvclkhdr_15 @[el2_lib.scala 483:22] + rvclkhdr_15.clock <= clock + rvclkhdr_15.reset <= reset + rvclkhdr_15.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_15.io.en <= write_fill_data_3 @[el2_lib.scala 485:16] + rvclkhdr_15.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_16 of rvclkhdr_16 @[el2_lib.scala 483:22] + rvclkhdr_16.clock <= clock + rvclkhdr_16.reset <= reset + rvclkhdr_16.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_16.io.en <= write_fill_data_4 @[el2_lib.scala 485:16] + rvclkhdr_16.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_17 of rvclkhdr_17 @[el2_lib.scala 483:22] + rvclkhdr_17.clock <= clock + rvclkhdr_17.reset <= reset + rvclkhdr_17.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_17.io.en <= write_fill_data_5 @[el2_lib.scala 485:16] + rvclkhdr_17.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_18 of rvclkhdr_18 @[el2_lib.scala 483:22] + rvclkhdr_18.clock <= clock + rvclkhdr_18.reset <= reset + rvclkhdr_18.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_18.io.en <= write_fill_data_6 @[el2_lib.scala 485:16] + rvclkhdr_18.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_19 of rvclkhdr_19 @[el2_lib.scala 483:22] + rvclkhdr_19.clock <= clock + rvclkhdr_19.reset <= reset + rvclkhdr_19.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_19.io.en <= write_fill_data_7 @[el2_lib.scala 485:16] + rvclkhdr_19.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + node _T_1296 = bits(ic_miss_buff_data_in, 31, 0) @[el2_ifu_mem_ctl.scala 402:88] + reg _T_1297 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 402:67] + _T_1297 <= _T_1296 @[el2_ifu_mem_ctl.scala 402:67] + ic_miss_buff_data[2] <= _T_1297 @[el2_ifu_mem_ctl.scala 402:28] + node _T_1298 = bits(ic_miss_buff_data_in, 63, 32) @[el2_ifu_mem_ctl.scala 403:90] + reg _T_1299 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 403:69] + _T_1299 <= _T_1298 @[el2_ifu_mem_ctl.scala 403:69] + ic_miss_buff_data[3] <= _T_1299 @[el2_ifu_mem_ctl.scala 403:30] + inst rvclkhdr_20 of rvclkhdr_20 @[el2_lib.scala 483:22] + rvclkhdr_20.clock <= clock + rvclkhdr_20.reset <= reset + rvclkhdr_20.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_20.io.en <= write_fill_data_0 @[el2_lib.scala 485:16] + rvclkhdr_20.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_21 of rvclkhdr_21 @[el2_lib.scala 483:22] + rvclkhdr_21.clock <= clock + rvclkhdr_21.reset <= reset + rvclkhdr_21.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_21.io.en <= write_fill_data_1 @[el2_lib.scala 485:16] + rvclkhdr_21.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_22 of rvclkhdr_22 @[el2_lib.scala 483:22] + rvclkhdr_22.clock <= clock + rvclkhdr_22.reset <= reset + rvclkhdr_22.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_22.io.en <= write_fill_data_2 @[el2_lib.scala 485:16] + rvclkhdr_22.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_23 of rvclkhdr_23 @[el2_lib.scala 483:22] + rvclkhdr_23.clock <= clock + rvclkhdr_23.reset <= reset + rvclkhdr_23.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_23.io.en <= write_fill_data_3 @[el2_lib.scala 485:16] + rvclkhdr_23.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_24 of rvclkhdr_24 @[el2_lib.scala 483:22] + rvclkhdr_24.clock <= clock + rvclkhdr_24.reset <= reset + rvclkhdr_24.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_24.io.en <= write_fill_data_4 @[el2_lib.scala 485:16] + rvclkhdr_24.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_25 of rvclkhdr_25 @[el2_lib.scala 483:22] + rvclkhdr_25.clock <= clock + rvclkhdr_25.reset <= reset + rvclkhdr_25.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_25.io.en <= write_fill_data_5 @[el2_lib.scala 485:16] + rvclkhdr_25.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_26 of rvclkhdr_26 @[el2_lib.scala 483:22] + rvclkhdr_26.clock <= clock + rvclkhdr_26.reset <= reset + rvclkhdr_26.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_26.io.en <= write_fill_data_6 @[el2_lib.scala 485:16] + rvclkhdr_26.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_27 of rvclkhdr_27 @[el2_lib.scala 483:22] + rvclkhdr_27.clock <= clock + rvclkhdr_27.reset <= reset + rvclkhdr_27.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_27.io.en <= write_fill_data_7 @[el2_lib.scala 485:16] + rvclkhdr_27.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + node _T_1300 = bits(ic_miss_buff_data_in, 31, 0) @[el2_ifu_mem_ctl.scala 402:88] + reg _T_1301 : UInt, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 402:67] + _T_1301 <= _T_1300 @[el2_ifu_mem_ctl.scala 402:67] + ic_miss_buff_data[4] <= _T_1301 @[el2_ifu_mem_ctl.scala 402:28] + node _T_1302 = bits(ic_miss_buff_data_in, 63, 32) @[el2_ifu_mem_ctl.scala 403:90] + reg _T_1303 : UInt, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 403:69] + _T_1303 <= _T_1302 @[el2_ifu_mem_ctl.scala 403:69] + ic_miss_buff_data[5] <= _T_1303 @[el2_ifu_mem_ctl.scala 403:30] + inst rvclkhdr_28 of rvclkhdr_28 @[el2_lib.scala 483:22] + rvclkhdr_28.clock <= clock + rvclkhdr_28.reset <= reset + rvclkhdr_28.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_28.io.en <= write_fill_data_0 @[el2_lib.scala 485:16] + rvclkhdr_28.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_29 of rvclkhdr_29 @[el2_lib.scala 483:22] + rvclkhdr_29.clock <= clock + rvclkhdr_29.reset <= reset + rvclkhdr_29.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_29.io.en <= write_fill_data_1 @[el2_lib.scala 485:16] + rvclkhdr_29.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_30 of rvclkhdr_30 @[el2_lib.scala 483:22] + rvclkhdr_30.clock <= clock + rvclkhdr_30.reset <= reset + rvclkhdr_30.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_30.io.en <= write_fill_data_2 @[el2_lib.scala 485:16] + rvclkhdr_30.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_31 of rvclkhdr_31 @[el2_lib.scala 483:22] + rvclkhdr_31.clock <= clock + rvclkhdr_31.reset <= reset + rvclkhdr_31.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_31.io.en <= write_fill_data_3 @[el2_lib.scala 485:16] + rvclkhdr_31.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_32 of rvclkhdr_32 @[el2_lib.scala 483:22] + rvclkhdr_32.clock <= clock + rvclkhdr_32.reset <= reset + rvclkhdr_32.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_32.io.en <= write_fill_data_4 @[el2_lib.scala 485:16] + rvclkhdr_32.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_33 of rvclkhdr_33 @[el2_lib.scala 483:22] + rvclkhdr_33.clock <= clock + rvclkhdr_33.reset <= reset + rvclkhdr_33.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_33.io.en <= write_fill_data_5 @[el2_lib.scala 485:16] + rvclkhdr_33.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_34 of rvclkhdr_34 @[el2_lib.scala 483:22] + rvclkhdr_34.clock <= clock + rvclkhdr_34.reset <= reset + rvclkhdr_34.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_34.io.en <= write_fill_data_6 @[el2_lib.scala 485:16] + rvclkhdr_34.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_35 of rvclkhdr_35 @[el2_lib.scala 483:22] + rvclkhdr_35.clock <= clock + rvclkhdr_35.reset <= reset + rvclkhdr_35.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_35.io.en <= write_fill_data_7 @[el2_lib.scala 485:16] + rvclkhdr_35.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + node _T_1304 = bits(ic_miss_buff_data_in, 31, 0) @[el2_ifu_mem_ctl.scala 402:88] + reg _T_1305 : UInt, rvclkhdr_31.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 402:67] + _T_1305 <= _T_1304 @[el2_ifu_mem_ctl.scala 402:67] + ic_miss_buff_data[6] <= _T_1305 @[el2_ifu_mem_ctl.scala 402:28] + node _T_1306 = bits(ic_miss_buff_data_in, 63, 32) @[el2_ifu_mem_ctl.scala 403:90] + reg _T_1307 : UInt, rvclkhdr_31.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 403:69] + _T_1307 <= _T_1306 @[el2_ifu_mem_ctl.scala 403:69] + ic_miss_buff_data[7] <= _T_1307 @[el2_ifu_mem_ctl.scala 403:30] + inst rvclkhdr_36 of rvclkhdr_36 @[el2_lib.scala 483:22] + rvclkhdr_36.clock <= clock + rvclkhdr_36.reset <= reset + rvclkhdr_36.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_36.io.en <= write_fill_data_0 @[el2_lib.scala 485:16] + rvclkhdr_36.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_37 of rvclkhdr_37 @[el2_lib.scala 483:22] + rvclkhdr_37.clock <= clock + rvclkhdr_37.reset <= reset + rvclkhdr_37.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_37.io.en <= write_fill_data_1 @[el2_lib.scala 485:16] + rvclkhdr_37.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_38 of rvclkhdr_38 @[el2_lib.scala 483:22] + rvclkhdr_38.clock <= clock + rvclkhdr_38.reset <= reset + rvclkhdr_38.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_38.io.en <= write_fill_data_2 @[el2_lib.scala 485:16] + rvclkhdr_38.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_39 of rvclkhdr_39 @[el2_lib.scala 483:22] + rvclkhdr_39.clock <= clock + rvclkhdr_39.reset <= reset + rvclkhdr_39.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_39.io.en <= write_fill_data_3 @[el2_lib.scala 485:16] + rvclkhdr_39.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_40 of rvclkhdr_40 @[el2_lib.scala 483:22] + rvclkhdr_40.clock <= clock + rvclkhdr_40.reset <= reset + rvclkhdr_40.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_40.io.en <= write_fill_data_4 @[el2_lib.scala 485:16] + rvclkhdr_40.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_41 of rvclkhdr_41 @[el2_lib.scala 483:22] + rvclkhdr_41.clock <= clock + rvclkhdr_41.reset <= reset + rvclkhdr_41.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_41.io.en <= write_fill_data_5 @[el2_lib.scala 485:16] + rvclkhdr_41.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_42 of rvclkhdr_42 @[el2_lib.scala 483:22] + rvclkhdr_42.clock <= clock + rvclkhdr_42.reset <= reset + rvclkhdr_42.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_42.io.en <= write_fill_data_6 @[el2_lib.scala 485:16] + rvclkhdr_42.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_43 of rvclkhdr_43 @[el2_lib.scala 483:22] + rvclkhdr_43.clock <= clock + rvclkhdr_43.reset <= reset + rvclkhdr_43.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_43.io.en <= write_fill_data_7 @[el2_lib.scala 485:16] + rvclkhdr_43.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + node _T_1308 = bits(ic_miss_buff_data_in, 31, 0) @[el2_ifu_mem_ctl.scala 402:88] + reg _T_1309 : UInt, rvclkhdr_40.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 402:67] + _T_1309 <= _T_1308 @[el2_ifu_mem_ctl.scala 402:67] + ic_miss_buff_data[8] <= _T_1309 @[el2_ifu_mem_ctl.scala 402:28] + node _T_1310 = bits(ic_miss_buff_data_in, 63, 32) @[el2_ifu_mem_ctl.scala 403:90] + reg _T_1311 : UInt, rvclkhdr_40.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 403:69] + _T_1311 <= _T_1310 @[el2_ifu_mem_ctl.scala 403:69] + ic_miss_buff_data[9] <= _T_1311 @[el2_ifu_mem_ctl.scala 403:30] + inst rvclkhdr_44 of rvclkhdr_44 @[el2_lib.scala 483:22] + rvclkhdr_44.clock <= clock + rvclkhdr_44.reset <= reset + rvclkhdr_44.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_44.io.en <= write_fill_data_0 @[el2_lib.scala 485:16] + rvclkhdr_44.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_45 of rvclkhdr_45 @[el2_lib.scala 483:22] + rvclkhdr_45.clock <= clock + rvclkhdr_45.reset <= reset + rvclkhdr_45.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_45.io.en <= write_fill_data_1 @[el2_lib.scala 485:16] + rvclkhdr_45.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_46 of rvclkhdr_46 @[el2_lib.scala 483:22] + rvclkhdr_46.clock <= clock + rvclkhdr_46.reset <= reset + rvclkhdr_46.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_46.io.en <= write_fill_data_2 @[el2_lib.scala 485:16] + rvclkhdr_46.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_47 of rvclkhdr_47 @[el2_lib.scala 483:22] + rvclkhdr_47.clock <= clock + rvclkhdr_47.reset <= reset + rvclkhdr_47.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_47.io.en <= write_fill_data_3 @[el2_lib.scala 485:16] + rvclkhdr_47.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_48 of rvclkhdr_48 @[el2_lib.scala 483:22] + rvclkhdr_48.clock <= clock + rvclkhdr_48.reset <= reset + rvclkhdr_48.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_48.io.en <= write_fill_data_4 @[el2_lib.scala 485:16] + rvclkhdr_48.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_49 of rvclkhdr_49 @[el2_lib.scala 483:22] + rvclkhdr_49.clock <= clock + rvclkhdr_49.reset <= reset + rvclkhdr_49.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_49.io.en <= write_fill_data_5 @[el2_lib.scala 485:16] + rvclkhdr_49.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_50 of rvclkhdr_50 @[el2_lib.scala 483:22] + rvclkhdr_50.clock <= clock + rvclkhdr_50.reset <= reset + rvclkhdr_50.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_50.io.en <= write_fill_data_6 @[el2_lib.scala 485:16] + rvclkhdr_50.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_51 of rvclkhdr_51 @[el2_lib.scala 483:22] + rvclkhdr_51.clock <= clock + rvclkhdr_51.reset <= reset + rvclkhdr_51.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_51.io.en <= write_fill_data_7 @[el2_lib.scala 485:16] + rvclkhdr_51.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + node _T_1312 = bits(ic_miss_buff_data_in, 31, 0) @[el2_ifu_mem_ctl.scala 402:88] + reg _T_1313 : UInt, rvclkhdr_49.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 402:67] + _T_1313 <= _T_1312 @[el2_ifu_mem_ctl.scala 402:67] + ic_miss_buff_data[10] <= _T_1313 @[el2_ifu_mem_ctl.scala 402:28] + node _T_1314 = bits(ic_miss_buff_data_in, 63, 32) @[el2_ifu_mem_ctl.scala 403:90] + reg _T_1315 : UInt, rvclkhdr_49.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 403:69] + _T_1315 <= _T_1314 @[el2_ifu_mem_ctl.scala 403:69] + ic_miss_buff_data[11] <= _T_1315 @[el2_ifu_mem_ctl.scala 403:30] + inst rvclkhdr_52 of rvclkhdr_52 @[el2_lib.scala 483:22] + rvclkhdr_52.clock <= clock + rvclkhdr_52.reset <= reset + rvclkhdr_52.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_52.io.en <= write_fill_data_0 @[el2_lib.scala 485:16] + rvclkhdr_52.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_53 of rvclkhdr_53 @[el2_lib.scala 483:22] + rvclkhdr_53.clock <= clock + rvclkhdr_53.reset <= reset + rvclkhdr_53.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_53.io.en <= write_fill_data_1 @[el2_lib.scala 485:16] + rvclkhdr_53.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_54 of rvclkhdr_54 @[el2_lib.scala 483:22] + rvclkhdr_54.clock <= clock + rvclkhdr_54.reset <= reset + rvclkhdr_54.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_54.io.en <= write_fill_data_2 @[el2_lib.scala 485:16] + rvclkhdr_54.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_55 of rvclkhdr_55 @[el2_lib.scala 483:22] + rvclkhdr_55.clock <= clock + rvclkhdr_55.reset <= reset + rvclkhdr_55.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_55.io.en <= write_fill_data_3 @[el2_lib.scala 485:16] + rvclkhdr_55.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_56 of rvclkhdr_56 @[el2_lib.scala 483:22] + rvclkhdr_56.clock <= clock + rvclkhdr_56.reset <= reset + rvclkhdr_56.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_56.io.en <= write_fill_data_4 @[el2_lib.scala 485:16] + rvclkhdr_56.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_57 of rvclkhdr_57 @[el2_lib.scala 483:22] + rvclkhdr_57.clock <= clock + rvclkhdr_57.reset <= reset + rvclkhdr_57.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_57.io.en <= write_fill_data_5 @[el2_lib.scala 485:16] + rvclkhdr_57.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_58 of rvclkhdr_58 @[el2_lib.scala 483:22] + rvclkhdr_58.clock <= clock + rvclkhdr_58.reset <= reset + rvclkhdr_58.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_58.io.en <= write_fill_data_6 @[el2_lib.scala 485:16] + rvclkhdr_58.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_59 of rvclkhdr_59 @[el2_lib.scala 483:22] + rvclkhdr_59.clock <= clock + rvclkhdr_59.reset <= reset + rvclkhdr_59.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_59.io.en <= write_fill_data_7 @[el2_lib.scala 485:16] + rvclkhdr_59.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + node _T_1316 = bits(ic_miss_buff_data_in, 31, 0) @[el2_ifu_mem_ctl.scala 402:88] + reg _T_1317 : UInt, rvclkhdr_58.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 402:67] + _T_1317 <= _T_1316 @[el2_ifu_mem_ctl.scala 402:67] + ic_miss_buff_data[12] <= _T_1317 @[el2_ifu_mem_ctl.scala 402:28] + node _T_1318 = bits(ic_miss_buff_data_in, 63, 32) @[el2_ifu_mem_ctl.scala 403:90] + reg _T_1319 : UInt, rvclkhdr_58.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 403:69] + _T_1319 <= _T_1318 @[el2_ifu_mem_ctl.scala 403:69] + ic_miss_buff_data[13] <= _T_1319 @[el2_ifu_mem_ctl.scala 403:30] + inst rvclkhdr_60 of rvclkhdr_60 @[el2_lib.scala 483:22] + rvclkhdr_60.clock <= clock + rvclkhdr_60.reset <= reset + rvclkhdr_60.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_60.io.en <= write_fill_data_0 @[el2_lib.scala 485:16] + rvclkhdr_60.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_61 of rvclkhdr_61 @[el2_lib.scala 483:22] + rvclkhdr_61.clock <= clock + rvclkhdr_61.reset <= reset + rvclkhdr_61.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_61.io.en <= write_fill_data_1 @[el2_lib.scala 485:16] + rvclkhdr_61.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_62 of rvclkhdr_62 @[el2_lib.scala 483:22] + rvclkhdr_62.clock <= clock + rvclkhdr_62.reset <= reset + rvclkhdr_62.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_62.io.en <= write_fill_data_2 @[el2_lib.scala 485:16] + rvclkhdr_62.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_63 of rvclkhdr_63 @[el2_lib.scala 483:22] + rvclkhdr_63.clock <= clock + rvclkhdr_63.reset <= reset + rvclkhdr_63.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_63.io.en <= write_fill_data_3 @[el2_lib.scala 485:16] + rvclkhdr_63.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_64 of rvclkhdr_64 @[el2_lib.scala 483:22] + rvclkhdr_64.clock <= clock + rvclkhdr_64.reset <= reset + rvclkhdr_64.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_64.io.en <= write_fill_data_4 @[el2_lib.scala 485:16] + rvclkhdr_64.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_65 of rvclkhdr_65 @[el2_lib.scala 483:22] + rvclkhdr_65.clock <= clock + rvclkhdr_65.reset <= reset + rvclkhdr_65.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_65.io.en <= write_fill_data_5 @[el2_lib.scala 485:16] + rvclkhdr_65.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_66 of rvclkhdr_66 @[el2_lib.scala 483:22] + rvclkhdr_66.clock <= clock + rvclkhdr_66.reset <= reset + rvclkhdr_66.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_66.io.en <= write_fill_data_6 @[el2_lib.scala 485:16] + rvclkhdr_66.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_67 of rvclkhdr_67 @[el2_lib.scala 483:22] + rvclkhdr_67.clock <= clock + rvclkhdr_67.reset <= reset + rvclkhdr_67.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_67.io.en <= write_fill_data_7 @[el2_lib.scala 485:16] + rvclkhdr_67.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + node _T_1320 = bits(ic_miss_buff_data_in, 31, 0) @[el2_ifu_mem_ctl.scala 402:88] + reg _T_1321 : UInt, rvclkhdr_67.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 402:67] + _T_1321 <= _T_1320 @[el2_ifu_mem_ctl.scala 402:67] + ic_miss_buff_data[14] <= _T_1321 @[el2_ifu_mem_ctl.scala 402:28] + node _T_1322 = bits(ic_miss_buff_data_in, 63, 32) @[el2_ifu_mem_ctl.scala 403:90] + reg _T_1323 : UInt, rvclkhdr_67.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 403:69] + _T_1323 <= _T_1322 @[el2_ifu_mem_ctl.scala 403:69] + ic_miss_buff_data[15] <= _T_1323 @[el2_ifu_mem_ctl.scala 403:30] + wire ic_miss_buff_data_valid : UInt<8> + ic_miss_buff_data_valid <= UInt<1>("h00") + node _T_1324 = bits(ic_miss_buff_data_valid, 0, 0) @[el2_ifu_mem_ctl.scala 405:113] + node _T_1325 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 405:118] + node _T_1326 = and(_T_1324, _T_1325) @[el2_ifu_mem_ctl.scala 405:116] + node ic_miss_buff_data_valid_in_0 = or(write_fill_data_0, _T_1326) @[el2_ifu_mem_ctl.scala 405:88] + node _T_1327 = bits(ic_miss_buff_data_valid, 1, 1) @[el2_ifu_mem_ctl.scala 405:113] + node _T_1328 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 405:118] + node _T_1329 = and(_T_1327, _T_1328) @[el2_ifu_mem_ctl.scala 405:116] + node ic_miss_buff_data_valid_in_1 = or(write_fill_data_1, _T_1329) @[el2_ifu_mem_ctl.scala 405:88] + node _T_1330 = bits(ic_miss_buff_data_valid, 2, 2) @[el2_ifu_mem_ctl.scala 405:113] + node _T_1331 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 405:118] + node _T_1332 = and(_T_1330, _T_1331) @[el2_ifu_mem_ctl.scala 405:116] + node ic_miss_buff_data_valid_in_2 = or(write_fill_data_2, _T_1332) @[el2_ifu_mem_ctl.scala 405:88] + node _T_1333 = bits(ic_miss_buff_data_valid, 3, 3) @[el2_ifu_mem_ctl.scala 405:113] + node _T_1334 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 405:118] + node _T_1335 = and(_T_1333, _T_1334) @[el2_ifu_mem_ctl.scala 405:116] + node ic_miss_buff_data_valid_in_3 = or(write_fill_data_3, _T_1335) @[el2_ifu_mem_ctl.scala 405:88] + node _T_1336 = bits(ic_miss_buff_data_valid, 4, 4) @[el2_ifu_mem_ctl.scala 405:113] + node _T_1337 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 405:118] + node _T_1338 = and(_T_1336, _T_1337) @[el2_ifu_mem_ctl.scala 405:116] + node ic_miss_buff_data_valid_in_4 = or(write_fill_data_4, _T_1338) @[el2_ifu_mem_ctl.scala 405:88] + node _T_1339 = bits(ic_miss_buff_data_valid, 5, 5) @[el2_ifu_mem_ctl.scala 405:113] + node _T_1340 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 405:118] + node _T_1341 = and(_T_1339, _T_1340) @[el2_ifu_mem_ctl.scala 405:116] + node ic_miss_buff_data_valid_in_5 = or(write_fill_data_5, _T_1341) @[el2_ifu_mem_ctl.scala 405:88] + node _T_1342 = bits(ic_miss_buff_data_valid, 6, 6) @[el2_ifu_mem_ctl.scala 405:113] + node _T_1343 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 405:118] + node _T_1344 = and(_T_1342, _T_1343) @[el2_ifu_mem_ctl.scala 405:116] + node ic_miss_buff_data_valid_in_6 = or(write_fill_data_6, _T_1344) @[el2_ifu_mem_ctl.scala 405:88] + node _T_1345 = bits(ic_miss_buff_data_valid, 7, 7) @[el2_ifu_mem_ctl.scala 405:113] + node _T_1346 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 405:118] + node _T_1347 = and(_T_1345, _T_1346) @[el2_ifu_mem_ctl.scala 405:116] + node ic_miss_buff_data_valid_in_7 = or(write_fill_data_7, _T_1347) @[el2_ifu_mem_ctl.scala 405:88] + node _T_1348 = cat(ic_miss_buff_data_valid_in_7, ic_miss_buff_data_valid_in_6) @[Cat.scala 29:58] + node _T_1349 = cat(_T_1348, ic_miss_buff_data_valid_in_5) @[Cat.scala 29:58] + node _T_1350 = cat(_T_1349, ic_miss_buff_data_valid_in_4) @[Cat.scala 29:58] + node _T_1351 = cat(_T_1350, ic_miss_buff_data_valid_in_3) @[Cat.scala 29:58] + node _T_1352 = cat(_T_1351, ic_miss_buff_data_valid_in_2) @[Cat.scala 29:58] + node _T_1353 = cat(_T_1352, ic_miss_buff_data_valid_in_1) @[Cat.scala 29:58] + node _T_1354 = cat(_T_1353, ic_miss_buff_data_valid_in_0) @[Cat.scala 29:58] + reg _T_1355 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 406:60] + _T_1355 <= _T_1354 @[el2_ifu_mem_ctl.scala 406:60] + ic_miss_buff_data_valid <= _T_1355 @[el2_ifu_mem_ctl.scala 406:27] + wire bus_ifu_wr_data_error : UInt<1> + bus_ifu_wr_data_error <= UInt<1>("h00") + wire ic_miss_buff_data_error : UInt<8> + ic_miss_buff_data_error <= UInt<1>("h00") + node _T_1356 = bits(write_fill_data_0, 0, 0) @[el2_ifu_mem_ctl.scala 409:92] + node _T_1357 = bits(ic_miss_buff_data_error, 0, 0) @[el2_ifu_mem_ctl.scala 410:28] + node _T_1358 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 410:34] + node _T_1359 = and(_T_1357, _T_1358) @[el2_ifu_mem_ctl.scala 410:32] + node ic_miss_buff_data_error_in_0 = mux(_T_1356, bus_ifu_wr_data_error, _T_1359) @[el2_ifu_mem_ctl.scala 409:72] + node _T_1360 = bits(write_fill_data_1, 0, 0) @[el2_ifu_mem_ctl.scala 409:92] + node _T_1361 = bits(ic_miss_buff_data_error, 1, 1) @[el2_ifu_mem_ctl.scala 410:28] + node _T_1362 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 410:34] + node _T_1363 = and(_T_1361, _T_1362) @[el2_ifu_mem_ctl.scala 410:32] + node ic_miss_buff_data_error_in_1 = mux(_T_1360, bus_ifu_wr_data_error, _T_1363) @[el2_ifu_mem_ctl.scala 409:72] + node _T_1364 = bits(write_fill_data_2, 0, 0) @[el2_ifu_mem_ctl.scala 409:92] + node _T_1365 = bits(ic_miss_buff_data_error, 2, 2) @[el2_ifu_mem_ctl.scala 410:28] + node _T_1366 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 410:34] + node _T_1367 = and(_T_1365, _T_1366) @[el2_ifu_mem_ctl.scala 410:32] + node ic_miss_buff_data_error_in_2 = mux(_T_1364, bus_ifu_wr_data_error, _T_1367) @[el2_ifu_mem_ctl.scala 409:72] + node _T_1368 = bits(write_fill_data_3, 0, 0) @[el2_ifu_mem_ctl.scala 409:92] + node _T_1369 = bits(ic_miss_buff_data_error, 3, 3) @[el2_ifu_mem_ctl.scala 410:28] + node _T_1370 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 410:34] + node _T_1371 = and(_T_1369, _T_1370) @[el2_ifu_mem_ctl.scala 410:32] + node ic_miss_buff_data_error_in_3 = mux(_T_1368, bus_ifu_wr_data_error, _T_1371) @[el2_ifu_mem_ctl.scala 409:72] + node _T_1372 = bits(write_fill_data_4, 0, 0) @[el2_ifu_mem_ctl.scala 409:92] + node _T_1373 = bits(ic_miss_buff_data_error, 4, 4) @[el2_ifu_mem_ctl.scala 410:28] + node _T_1374 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 410:34] + node _T_1375 = and(_T_1373, _T_1374) @[el2_ifu_mem_ctl.scala 410:32] + node ic_miss_buff_data_error_in_4 = mux(_T_1372, bus_ifu_wr_data_error, _T_1375) @[el2_ifu_mem_ctl.scala 409:72] + node _T_1376 = bits(write_fill_data_5, 0, 0) @[el2_ifu_mem_ctl.scala 409:92] + node _T_1377 = bits(ic_miss_buff_data_error, 5, 5) @[el2_ifu_mem_ctl.scala 410:28] + node _T_1378 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 410:34] + node _T_1379 = and(_T_1377, _T_1378) @[el2_ifu_mem_ctl.scala 410:32] + node ic_miss_buff_data_error_in_5 = mux(_T_1376, bus_ifu_wr_data_error, _T_1379) @[el2_ifu_mem_ctl.scala 409:72] + node _T_1380 = bits(write_fill_data_6, 0, 0) @[el2_ifu_mem_ctl.scala 409:92] + node _T_1381 = bits(ic_miss_buff_data_error, 6, 6) @[el2_ifu_mem_ctl.scala 410:28] + node _T_1382 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 410:34] + node _T_1383 = and(_T_1381, _T_1382) @[el2_ifu_mem_ctl.scala 410:32] + node ic_miss_buff_data_error_in_6 = mux(_T_1380, bus_ifu_wr_data_error, _T_1383) @[el2_ifu_mem_ctl.scala 409:72] + node _T_1384 = bits(write_fill_data_7, 0, 0) @[el2_ifu_mem_ctl.scala 409:92] + node _T_1385 = bits(ic_miss_buff_data_error, 7, 7) @[el2_ifu_mem_ctl.scala 410:28] + node _T_1386 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 410:34] + node _T_1387 = and(_T_1385, _T_1386) @[el2_ifu_mem_ctl.scala 410:32] + node ic_miss_buff_data_error_in_7 = mux(_T_1384, bus_ifu_wr_data_error, _T_1387) @[el2_ifu_mem_ctl.scala 409:72] + node _T_1388 = cat(ic_miss_buff_data_error_in_7, ic_miss_buff_data_error_in_6) @[Cat.scala 29:58] + node _T_1389 = cat(_T_1388, ic_miss_buff_data_error_in_5) @[Cat.scala 29:58] + node _T_1390 = cat(_T_1389, ic_miss_buff_data_error_in_4) @[Cat.scala 29:58] + node _T_1391 = cat(_T_1390, ic_miss_buff_data_error_in_3) @[Cat.scala 29:58] + node _T_1392 = cat(_T_1391, ic_miss_buff_data_error_in_2) @[Cat.scala 29:58] + node _T_1393 = cat(_T_1392, ic_miss_buff_data_error_in_1) @[Cat.scala 29:58] + node _T_1394 = cat(_T_1393, ic_miss_buff_data_error_in_0) @[Cat.scala 29:58] + reg _T_1395 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 411:60] + _T_1395 <= _T_1394 @[el2_ifu_mem_ctl.scala 411:60] + ic_miss_buff_data_error <= _T_1395 @[el2_ifu_mem_ctl.scala 411:27] + node bypass_index = bits(imb_ff, 4, 0) @[el2_ifu_mem_ctl.scala 414:28] + node _T_1396 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 415:42] + node _T_1397 = add(_T_1396, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 415:70] + node bypass_index_5_3_inc = tail(_T_1397, 1) @[el2_ifu_mem_ctl.scala 415:70] + node _T_1398 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 416:87] + node _T_1399 = eq(_T_1398, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 416:114] + node _T_1400 = bits(_T_1399, 0, 0) @[el2_ifu_mem_ctl.scala 416:122] + node _T_1401 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 416:87] + node _T_1402 = eq(_T_1401, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 416:114] + node _T_1403 = bits(_T_1402, 0, 0) @[el2_ifu_mem_ctl.scala 416:122] + node _T_1404 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 416:87] + node _T_1405 = eq(_T_1404, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 416:114] + node _T_1406 = bits(_T_1405, 0, 0) @[el2_ifu_mem_ctl.scala 416:122] + node _T_1407 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 416:87] + node _T_1408 = eq(_T_1407, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 416:114] + node _T_1409 = bits(_T_1408, 0, 0) @[el2_ifu_mem_ctl.scala 416:122] + node _T_1410 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 416:87] + node _T_1411 = eq(_T_1410, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 416:114] + node _T_1412 = bits(_T_1411, 0, 0) @[el2_ifu_mem_ctl.scala 416:122] + node _T_1413 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 416:87] + node _T_1414 = eq(_T_1413, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 416:114] + node _T_1415 = bits(_T_1414, 0, 0) @[el2_ifu_mem_ctl.scala 416:122] + node _T_1416 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 416:87] + node _T_1417 = eq(_T_1416, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 416:114] + node _T_1418 = bits(_T_1417, 0, 0) @[el2_ifu_mem_ctl.scala 416:122] + node _T_1419 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 416:87] + node _T_1420 = eq(_T_1419, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 416:114] + node _T_1421 = bits(_T_1420, 0, 0) @[el2_ifu_mem_ctl.scala 416:122] + node _T_1422 = mux(_T_1400, ic_miss_buff_data_valid_in_0, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1423 = mux(_T_1403, ic_miss_buff_data_valid_in_1, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1424 = mux(_T_1406, ic_miss_buff_data_valid_in_2, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1425 = mux(_T_1409, ic_miss_buff_data_valid_in_3, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1426 = mux(_T_1412, ic_miss_buff_data_valid_in_4, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1427 = mux(_T_1415, ic_miss_buff_data_valid_in_5, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1428 = mux(_T_1418, ic_miss_buff_data_valid_in_6, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1429 = mux(_T_1421, ic_miss_buff_data_valid_in_7, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1430 = or(_T_1422, _T_1423) @[Mux.scala 27:72] + node _T_1431 = or(_T_1430, _T_1424) @[Mux.scala 27:72] + node _T_1432 = or(_T_1431, _T_1425) @[Mux.scala 27:72] + node _T_1433 = or(_T_1432, _T_1426) @[Mux.scala 27:72] + node _T_1434 = or(_T_1433, _T_1427) @[Mux.scala 27:72] + node _T_1435 = or(_T_1434, _T_1428) @[Mux.scala 27:72] + node _T_1436 = or(_T_1435, _T_1429) @[Mux.scala 27:72] + wire bypass_valid_value_check : UInt<1> @[Mux.scala 27:72] + bypass_valid_value_check <= _T_1436 @[Mux.scala 27:72] + node _T_1437 = bits(bypass_index, 1, 1) @[el2_ifu_mem_ctl.scala 417:71] + node _T_1438 = eq(_T_1437, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 417:58] + node _T_1439 = and(bypass_valid_value_check, _T_1438) @[el2_ifu_mem_ctl.scala 417:56] + node _T_1440 = bits(bypass_index, 0, 0) @[el2_ifu_mem_ctl.scala 417:90] + node _T_1441 = eq(_T_1440, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 417:77] + node _T_1442 = and(_T_1439, _T_1441) @[el2_ifu_mem_ctl.scala 417:75] + node _T_1443 = bits(bypass_index, 1, 1) @[el2_ifu_mem_ctl.scala 418:46] + node _T_1444 = eq(_T_1443, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 418:33] + node _T_1445 = and(bypass_valid_value_check, _T_1444) @[el2_ifu_mem_ctl.scala 418:31] + node _T_1446 = bits(bypass_index, 0, 0) @[el2_ifu_mem_ctl.scala 418:64] + node _T_1447 = and(_T_1445, _T_1446) @[el2_ifu_mem_ctl.scala 418:50] + node _T_1448 = or(_T_1442, _T_1447) @[el2_ifu_mem_ctl.scala 417:95] + node _T_1449 = bits(bypass_index, 1, 1) @[el2_ifu_mem_ctl.scala 419:45] + node _T_1450 = and(bypass_valid_value_check, _T_1449) @[el2_ifu_mem_ctl.scala 419:31] + node _T_1451 = bits(bypass_index, 0, 0) @[el2_ifu_mem_ctl.scala 419:64] + node _T_1452 = eq(_T_1451, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 419:51] + node _T_1453 = and(_T_1450, _T_1452) @[el2_ifu_mem_ctl.scala 419:49] + node _T_1454 = or(_T_1448, _T_1453) @[el2_ifu_mem_ctl.scala 418:69] + node _T_1455 = bits(bypass_index, 1, 1) @[el2_ifu_mem_ctl.scala 420:45] + node _T_1456 = and(bypass_valid_value_check, _T_1455) @[el2_ifu_mem_ctl.scala 420:31] + node _T_1457 = bits(bypass_index, 0, 0) @[el2_ifu_mem_ctl.scala 420:63] + node _T_1458 = and(_T_1456, _T_1457) @[el2_ifu_mem_ctl.scala 420:49] + node _T_1459 = eq(bypass_index_5_3_inc, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 420:130] + node _T_1460 = bits(_T_1459, 0, 0) @[el2_ifu_mem_ctl.scala 420:138] + node _T_1461 = eq(bypass_index_5_3_inc, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 420:130] + node _T_1462 = bits(_T_1461, 0, 0) @[el2_ifu_mem_ctl.scala 420:138] + node _T_1463 = eq(bypass_index_5_3_inc, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 420:130] + node _T_1464 = bits(_T_1463, 0, 0) @[el2_ifu_mem_ctl.scala 420:138] + node _T_1465 = eq(bypass_index_5_3_inc, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 420:130] + node _T_1466 = bits(_T_1465, 0, 0) @[el2_ifu_mem_ctl.scala 420:138] + node _T_1467 = eq(bypass_index_5_3_inc, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 420:130] + node _T_1468 = bits(_T_1467, 0, 0) @[el2_ifu_mem_ctl.scala 420:138] + node _T_1469 = eq(bypass_index_5_3_inc, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 420:130] + node _T_1470 = bits(_T_1469, 0, 0) @[el2_ifu_mem_ctl.scala 420:138] + node _T_1471 = eq(bypass_index_5_3_inc, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 420:130] + node _T_1472 = bits(_T_1471, 0, 0) @[el2_ifu_mem_ctl.scala 420:138] + node _T_1473 = eq(bypass_index_5_3_inc, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 420:130] + node _T_1474 = bits(_T_1473, 0, 0) @[el2_ifu_mem_ctl.scala 420:138] + node _T_1475 = mux(_T_1460, ic_miss_buff_data_valid_in_0, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1476 = mux(_T_1462, ic_miss_buff_data_valid_in_1, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1477 = mux(_T_1464, ic_miss_buff_data_valid_in_2, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1478 = mux(_T_1466, ic_miss_buff_data_valid_in_3, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1479 = mux(_T_1468, ic_miss_buff_data_valid_in_4, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1480 = mux(_T_1470, ic_miss_buff_data_valid_in_5, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1481 = mux(_T_1472, ic_miss_buff_data_valid_in_6, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1482 = mux(_T_1474, ic_miss_buff_data_valid_in_7, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1483 = or(_T_1475, _T_1476) @[Mux.scala 27:72] + node _T_1484 = or(_T_1483, _T_1477) @[Mux.scala 27:72] + node _T_1485 = or(_T_1484, _T_1478) @[Mux.scala 27:72] + node _T_1486 = or(_T_1485, _T_1479) @[Mux.scala 27:72] + node _T_1487 = or(_T_1486, _T_1480) @[Mux.scala 27:72] + node _T_1488 = or(_T_1487, _T_1481) @[Mux.scala 27:72] + node _T_1489 = or(_T_1488, _T_1482) @[Mux.scala 27:72] + wire _T_1490 : UInt<1> @[Mux.scala 27:72] + _T_1490 <= _T_1489 @[Mux.scala 27:72] + node _T_1491 = and(_T_1458, _T_1490) @[el2_ifu_mem_ctl.scala 420:67] + node _T_1492 = or(_T_1454, _T_1491) @[el2_ifu_mem_ctl.scala 419:69] + node _T_1493 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 421:45] + node _T_1494 = mux(UInt<1>("h01"), UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] + node _T_1495 = eq(_T_1493, _T_1494) @[el2_ifu_mem_ctl.scala 421:70] + node _T_1496 = and(bypass_valid_value_check, _T_1495) @[el2_ifu_mem_ctl.scala 421:31] + node bypass_data_ready_in = or(_T_1492, _T_1496) @[el2_ifu_mem_ctl.scala 420:179] + wire ic_crit_wd_rdy_new_ff : UInt<1> + ic_crit_wd_rdy_new_ff <= UInt<1>("h00") + node _T_1497 = and(bypass_data_ready_in, crit_wd_byp_ok_ff) @[el2_ifu_mem_ctl.scala 425:53] + node _T_1498 = and(_T_1497, uncacheable_miss_ff) @[el2_ifu_mem_ctl.scala 425:73] + node _T_1499 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 425:98] + node _T_1500 = and(_T_1498, _T_1499) @[el2_ifu_mem_ctl.scala 425:96] + node _T_1501 = eq(ifu_bp_hit_taken_q_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 425:120] + node _T_1502 = and(_T_1500, _T_1501) @[el2_ifu_mem_ctl.scala 425:118] + node _T_1503 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 426:49] + node _T_1504 = and(crit_wd_byp_ok_ff, _T_1503) @[el2_ifu_mem_ctl.scala 426:47] + node _T_1505 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 426:72] + node _T_1506 = and(_T_1504, _T_1505) @[el2_ifu_mem_ctl.scala 426:70] + node _T_1507 = eq(ifu_bp_hit_taken_q_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 426:94] + node _T_1508 = and(_T_1506, _T_1507) @[el2_ifu_mem_ctl.scala 426:92] + node _T_1509 = or(_T_1502, _T_1508) @[el2_ifu_mem_ctl.scala 425:143] + node _T_1510 = and(ic_crit_wd_rdy_new_ff, crit_wd_byp_ok_ff) @[el2_ifu_mem_ctl.scala 427:28] + node _T_1511 = eq(fetch_req_icache_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 427:50] + node _T_1512 = and(_T_1510, _T_1511) @[el2_ifu_mem_ctl.scala 427:48] + node _T_1513 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 427:72] + node _T_1514 = and(_T_1512, _T_1513) @[el2_ifu_mem_ctl.scala 427:70] + node ic_crit_wd_rdy_new_in = or(_T_1509, _T_1514) @[el2_ifu_mem_ctl.scala 426:117] + reg _T_1515 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 428:58] + _T_1515 <= ic_crit_wd_rdy_new_in @[el2_ifu_mem_ctl.scala 428:58] + ic_crit_wd_rdy_new_ff <= _T_1515 @[el2_ifu_mem_ctl.scala 428:25] + node byp_fetch_index = bits(ifu_fetch_addr_int_f, 4, 0) @[el2_ifu_mem_ctl.scala 429:45] + node _T_1516 = bits(ifu_fetch_addr_int_f, 4, 2) @[el2_ifu_mem_ctl.scala 430:51] + node byp_fetch_index_0 = cat(_T_1516, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_1517 = bits(ifu_fetch_addr_int_f, 4, 2) @[el2_ifu_mem_ctl.scala 431:51] + node byp_fetch_index_1 = cat(_T_1517, UInt<1>("h01")) @[Cat.scala 29:58] + node _T_1518 = bits(ifu_fetch_addr_int_f, 4, 2) @[el2_ifu_mem_ctl.scala 432:49] + node _T_1519 = add(_T_1518, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 432:75] + node byp_fetch_index_inc = tail(_T_1519, 1) @[el2_ifu_mem_ctl.scala 432:75] + node byp_fetch_index_inc_0 = cat(byp_fetch_index_inc, UInt<1>("h00")) @[Cat.scala 29:58] + node byp_fetch_index_inc_1 = cat(byp_fetch_index_inc, UInt<1>("h01")) @[Cat.scala 29:58] + node _T_1520 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 435:93] + node _T_1521 = eq(_T_1520, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 435:118] + node _T_1522 = bits(_T_1521, 0, 0) @[el2_ifu_mem_ctl.scala 435:126] + node _T_1523 = bits(ic_miss_buff_data_error, 0, 0) @[el2_ifu_mem_ctl.scala 435:157] + node _T_1524 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 435:93] + node _T_1525 = eq(_T_1524, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 435:118] + node _T_1526 = bits(_T_1525, 0, 0) @[el2_ifu_mem_ctl.scala 435:126] + node _T_1527 = bits(ic_miss_buff_data_error, 1, 1) @[el2_ifu_mem_ctl.scala 435:157] + node _T_1528 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 435:93] + node _T_1529 = eq(_T_1528, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 435:118] + node _T_1530 = bits(_T_1529, 0, 0) @[el2_ifu_mem_ctl.scala 435:126] + node _T_1531 = bits(ic_miss_buff_data_error, 2, 2) @[el2_ifu_mem_ctl.scala 435:157] + node _T_1532 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 435:93] + node _T_1533 = eq(_T_1532, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 435:118] + node _T_1534 = bits(_T_1533, 0, 0) @[el2_ifu_mem_ctl.scala 435:126] + node _T_1535 = bits(ic_miss_buff_data_error, 3, 3) @[el2_ifu_mem_ctl.scala 435:157] + node _T_1536 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 435:93] + node _T_1537 = eq(_T_1536, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 435:118] + node _T_1538 = bits(_T_1537, 0, 0) @[el2_ifu_mem_ctl.scala 435:126] + node _T_1539 = bits(ic_miss_buff_data_error, 4, 4) @[el2_ifu_mem_ctl.scala 435:157] + node _T_1540 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 435:93] + node _T_1541 = eq(_T_1540, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 435:118] + node _T_1542 = bits(_T_1541, 0, 0) @[el2_ifu_mem_ctl.scala 435:126] + node _T_1543 = bits(ic_miss_buff_data_error, 5, 5) @[el2_ifu_mem_ctl.scala 435:157] + node _T_1544 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 435:93] + node _T_1545 = eq(_T_1544, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 435:118] + node _T_1546 = bits(_T_1545, 0, 0) @[el2_ifu_mem_ctl.scala 435:126] + node _T_1547 = bits(ic_miss_buff_data_error, 6, 6) @[el2_ifu_mem_ctl.scala 435:157] + node _T_1548 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 435:93] + node _T_1549 = eq(_T_1548, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 435:118] + node _T_1550 = bits(_T_1549, 0, 0) @[el2_ifu_mem_ctl.scala 435:126] + node _T_1551 = bits(ic_miss_buff_data_error, 7, 7) @[el2_ifu_mem_ctl.scala 435:157] + node _T_1552 = mux(_T_1522, _T_1523, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1553 = mux(_T_1526, _T_1527, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1554 = mux(_T_1530, _T_1531, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1555 = mux(_T_1534, _T_1535, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1556 = mux(_T_1538, _T_1539, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1557 = mux(_T_1542, _T_1543, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1558 = mux(_T_1546, _T_1547, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1559 = mux(_T_1550, _T_1551, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1560 = or(_T_1552, _T_1553) @[Mux.scala 27:72] + node _T_1561 = or(_T_1560, _T_1554) @[Mux.scala 27:72] + node _T_1562 = or(_T_1561, _T_1555) @[Mux.scala 27:72] + node _T_1563 = or(_T_1562, _T_1556) @[Mux.scala 27:72] + node _T_1564 = or(_T_1563, _T_1557) @[Mux.scala 27:72] + node _T_1565 = or(_T_1564, _T_1558) @[Mux.scala 27:72] + node _T_1566 = or(_T_1565, _T_1559) @[Mux.scala 27:72] + wire ic_miss_buff_data_error_bypass : UInt<1> @[Mux.scala 27:72] + ic_miss_buff_data_error_bypass <= _T_1566 @[Mux.scala 27:72] + node _T_1567 = eq(byp_fetch_index_inc, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 436:104] + node _T_1568 = bits(_T_1567, 0, 0) @[el2_ifu_mem_ctl.scala 436:112] + node _T_1569 = bits(ic_miss_buff_data_error, 0, 0) @[el2_ifu_mem_ctl.scala 436:143] + node _T_1570 = eq(byp_fetch_index_inc, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 436:104] + node _T_1571 = bits(_T_1570, 0, 0) @[el2_ifu_mem_ctl.scala 436:112] + node _T_1572 = bits(ic_miss_buff_data_error, 1, 1) @[el2_ifu_mem_ctl.scala 436:143] + node _T_1573 = eq(byp_fetch_index_inc, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 436:104] + node _T_1574 = bits(_T_1573, 0, 0) @[el2_ifu_mem_ctl.scala 436:112] + node _T_1575 = bits(ic_miss_buff_data_error, 2, 2) @[el2_ifu_mem_ctl.scala 436:143] + node _T_1576 = eq(byp_fetch_index_inc, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 436:104] + node _T_1577 = bits(_T_1576, 0, 0) @[el2_ifu_mem_ctl.scala 436:112] + node _T_1578 = bits(ic_miss_buff_data_error, 3, 3) @[el2_ifu_mem_ctl.scala 436:143] + node _T_1579 = eq(byp_fetch_index_inc, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 436:104] + node _T_1580 = bits(_T_1579, 0, 0) @[el2_ifu_mem_ctl.scala 436:112] + node _T_1581 = bits(ic_miss_buff_data_error, 4, 4) @[el2_ifu_mem_ctl.scala 436:143] + node _T_1582 = eq(byp_fetch_index_inc, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 436:104] + node _T_1583 = bits(_T_1582, 0, 0) @[el2_ifu_mem_ctl.scala 436:112] + node _T_1584 = bits(ic_miss_buff_data_error, 5, 5) @[el2_ifu_mem_ctl.scala 436:143] + node _T_1585 = eq(byp_fetch_index_inc, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 436:104] + node _T_1586 = bits(_T_1585, 0, 0) @[el2_ifu_mem_ctl.scala 436:112] + node _T_1587 = bits(ic_miss_buff_data_error, 6, 6) @[el2_ifu_mem_ctl.scala 436:143] + node _T_1588 = eq(byp_fetch_index_inc, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 436:104] + node _T_1589 = bits(_T_1588, 0, 0) @[el2_ifu_mem_ctl.scala 436:112] + node _T_1590 = bits(ic_miss_buff_data_error, 7, 7) @[el2_ifu_mem_ctl.scala 436:143] + node _T_1591 = mux(_T_1568, _T_1569, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1592 = mux(_T_1571, _T_1572, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1593 = mux(_T_1574, _T_1575, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1594 = mux(_T_1577, _T_1578, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1595 = mux(_T_1580, _T_1581, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1596 = mux(_T_1583, _T_1584, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1597 = mux(_T_1586, _T_1587, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1598 = mux(_T_1589, _T_1590, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1599 = or(_T_1591, _T_1592) @[Mux.scala 27:72] + node _T_1600 = or(_T_1599, _T_1593) @[Mux.scala 27:72] + node _T_1601 = or(_T_1600, _T_1594) @[Mux.scala 27:72] + node _T_1602 = or(_T_1601, _T_1595) @[Mux.scala 27:72] + node _T_1603 = or(_T_1602, _T_1596) @[Mux.scala 27:72] + node _T_1604 = or(_T_1603, _T_1597) @[Mux.scala 27:72] + node _T_1605 = or(_T_1604, _T_1598) @[Mux.scala 27:72] + wire ic_miss_buff_data_error_bypass_inc : UInt<1> @[Mux.scala 27:72] + ic_miss_buff_data_error_bypass_inc <= _T_1605 @[Mux.scala 27:72] + node _T_1606 = bits(ifu_fetch_addr_int_f, 1, 1) @[el2_ifu_mem_ctl.scala 439:28] + node _T_1607 = bits(ifu_fetch_addr_int_f, 0, 0) @[el2_ifu_mem_ctl.scala 439:52] + node _T_1608 = and(_T_1606, _T_1607) @[el2_ifu_mem_ctl.scala 439:31] + when _T_1608 : @[el2_ifu_mem_ctl.scala 439:56] + ifu_byp_data_err_new <= ic_miss_buff_data_error_bypass @[el2_ifu_mem_ctl.scala 440:26] + skip @[el2_ifu_mem_ctl.scala 439:56] + else : @[el2_ifu_mem_ctl.scala 441:5] + node _T_1609 = or(ic_miss_buff_data_error_bypass, ic_miss_buff_data_error_bypass_inc) @[el2_ifu_mem_ctl.scala 441:70] + ifu_byp_data_err_new <= _T_1609 @[el2_ifu_mem_ctl.scala 441:36] + skip @[el2_ifu_mem_ctl.scala 441:5] + node _T_1610 = bits(ifu_fetch_addr_int_f, 1, 1) @[el2_ifu_mem_ctl.scala 443:59] + node _T_1611 = bits(_T_1610, 0, 0) @[el2_ifu_mem_ctl.scala 443:63] + node _T_1612 = eq(_T_1611, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 443:38] + node _T_1613 = eq(byp_fetch_index_inc_0, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 444:73] + node _T_1614 = bits(_T_1613, 0, 0) @[el2_ifu_mem_ctl.scala 444:81] + node _T_1615 = bits(ic_miss_buff_data[0], 15, 0) @[el2_ifu_mem_ctl.scala 444:109] + node _T_1616 = eq(byp_fetch_index_inc_0, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 444:73] + node _T_1617 = bits(_T_1616, 0, 0) @[el2_ifu_mem_ctl.scala 444:81] + node _T_1618 = bits(ic_miss_buff_data[1], 15, 0) @[el2_ifu_mem_ctl.scala 444:109] + node _T_1619 = eq(byp_fetch_index_inc_0, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 444:73] + node _T_1620 = bits(_T_1619, 0, 0) @[el2_ifu_mem_ctl.scala 444:81] + node _T_1621 = bits(ic_miss_buff_data[2], 15, 0) @[el2_ifu_mem_ctl.scala 444:109] + node _T_1622 = eq(byp_fetch_index_inc_0, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 444:73] + node _T_1623 = bits(_T_1622, 0, 0) @[el2_ifu_mem_ctl.scala 444:81] + node _T_1624 = bits(ic_miss_buff_data[3], 15, 0) @[el2_ifu_mem_ctl.scala 444:109] + node _T_1625 = eq(byp_fetch_index_inc_0, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 444:73] + node _T_1626 = bits(_T_1625, 0, 0) @[el2_ifu_mem_ctl.scala 444:81] + node _T_1627 = bits(ic_miss_buff_data[4], 15, 0) @[el2_ifu_mem_ctl.scala 444:109] + node _T_1628 = eq(byp_fetch_index_inc_0, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 444:73] + node _T_1629 = bits(_T_1628, 0, 0) @[el2_ifu_mem_ctl.scala 444:81] + node _T_1630 = bits(ic_miss_buff_data[5], 15, 0) @[el2_ifu_mem_ctl.scala 444:109] + node _T_1631 = eq(byp_fetch_index_inc_0, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 444:73] + node _T_1632 = bits(_T_1631, 0, 0) @[el2_ifu_mem_ctl.scala 444:81] + node _T_1633 = bits(ic_miss_buff_data[6], 15, 0) @[el2_ifu_mem_ctl.scala 444:109] + node _T_1634 = eq(byp_fetch_index_inc_0, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 444:73] + node _T_1635 = bits(_T_1634, 0, 0) @[el2_ifu_mem_ctl.scala 444:81] + node _T_1636 = bits(ic_miss_buff_data[7], 15, 0) @[el2_ifu_mem_ctl.scala 444:109] + node _T_1637 = eq(byp_fetch_index_inc_0, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 444:73] + node _T_1638 = bits(_T_1637, 0, 0) @[el2_ifu_mem_ctl.scala 444:81] + node _T_1639 = bits(ic_miss_buff_data[8], 15, 0) @[el2_ifu_mem_ctl.scala 444:109] + node _T_1640 = eq(byp_fetch_index_inc_0, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 444:73] + node _T_1641 = bits(_T_1640, 0, 0) @[el2_ifu_mem_ctl.scala 444:81] + node _T_1642 = bits(ic_miss_buff_data[9], 15, 0) @[el2_ifu_mem_ctl.scala 444:109] + node _T_1643 = eq(byp_fetch_index_inc_0, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 444:73] + node _T_1644 = bits(_T_1643, 0, 0) @[el2_ifu_mem_ctl.scala 444:81] + node _T_1645 = bits(ic_miss_buff_data[10], 15, 0) @[el2_ifu_mem_ctl.scala 444:109] + node _T_1646 = eq(byp_fetch_index_inc_0, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 444:73] + node _T_1647 = bits(_T_1646, 0, 0) @[el2_ifu_mem_ctl.scala 444:81] + node _T_1648 = bits(ic_miss_buff_data[11], 15, 0) @[el2_ifu_mem_ctl.scala 444:109] + node _T_1649 = eq(byp_fetch_index_inc_0, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 444:73] + node _T_1650 = bits(_T_1649, 0, 0) @[el2_ifu_mem_ctl.scala 444:81] + node _T_1651 = bits(ic_miss_buff_data[12], 15, 0) @[el2_ifu_mem_ctl.scala 444:109] + node _T_1652 = eq(byp_fetch_index_inc_0, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 444:73] + node _T_1653 = bits(_T_1652, 0, 0) @[el2_ifu_mem_ctl.scala 444:81] + node _T_1654 = bits(ic_miss_buff_data[13], 15, 0) @[el2_ifu_mem_ctl.scala 444:109] + node _T_1655 = eq(byp_fetch_index_inc_0, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 444:73] + node _T_1656 = bits(_T_1655, 0, 0) @[el2_ifu_mem_ctl.scala 444:81] + node _T_1657 = bits(ic_miss_buff_data[14], 15, 0) @[el2_ifu_mem_ctl.scala 444:109] + node _T_1658 = eq(byp_fetch_index_inc_0, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 444:73] + node _T_1659 = bits(_T_1658, 0, 0) @[el2_ifu_mem_ctl.scala 444:81] + node _T_1660 = bits(ic_miss_buff_data[15], 15, 0) @[el2_ifu_mem_ctl.scala 444:109] + node _T_1661 = mux(_T_1614, _T_1615, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1662 = mux(_T_1617, _T_1618, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1663 = mux(_T_1620, _T_1621, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1664 = mux(_T_1623, _T_1624, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1665 = mux(_T_1626, _T_1627, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1666 = mux(_T_1629, _T_1630, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1667 = mux(_T_1632, _T_1633, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1668 = mux(_T_1635, _T_1636, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1669 = mux(_T_1638, _T_1639, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1670 = mux(_T_1641, _T_1642, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1671 = mux(_T_1644, _T_1645, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1672 = mux(_T_1647, _T_1648, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1673 = mux(_T_1650, _T_1651, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1674 = mux(_T_1653, _T_1654, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1675 = mux(_T_1656, _T_1657, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1676 = mux(_T_1659, _T_1660, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1677 = or(_T_1661, _T_1662) @[Mux.scala 27:72] + node _T_1678 = or(_T_1677, _T_1663) @[Mux.scala 27:72] + node _T_1679 = or(_T_1678, _T_1664) @[Mux.scala 27:72] + node _T_1680 = or(_T_1679, _T_1665) @[Mux.scala 27:72] + node _T_1681 = or(_T_1680, _T_1666) @[Mux.scala 27:72] + node _T_1682 = or(_T_1681, _T_1667) @[Mux.scala 27:72] + node _T_1683 = or(_T_1682, _T_1668) @[Mux.scala 27:72] + node _T_1684 = or(_T_1683, _T_1669) @[Mux.scala 27:72] + node _T_1685 = or(_T_1684, _T_1670) @[Mux.scala 27:72] + node _T_1686 = or(_T_1685, _T_1671) @[Mux.scala 27:72] + node _T_1687 = or(_T_1686, _T_1672) @[Mux.scala 27:72] + node _T_1688 = or(_T_1687, _T_1673) @[Mux.scala 27:72] + node _T_1689 = or(_T_1688, _T_1674) @[Mux.scala 27:72] + node _T_1690 = or(_T_1689, _T_1675) @[Mux.scala 27:72] + node _T_1691 = or(_T_1690, _T_1676) @[Mux.scala 27:72] + wire _T_1692 : UInt<16> @[Mux.scala 27:72] + _T_1692 <= _T_1691 @[Mux.scala 27:72] + node _T_1693 = eq(byp_fetch_index_1, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 444:179] + node _T_1694 = bits(_T_1693, 0, 0) @[el2_ifu_mem_ctl.scala 444:187] + node _T_1695 = bits(ic_miss_buff_data[0], 31, 0) @[el2_ifu_mem_ctl.scala 444:215] + node _T_1696 = eq(byp_fetch_index_1, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 444:179] + node _T_1697 = bits(_T_1696, 0, 0) @[el2_ifu_mem_ctl.scala 444:187] + node _T_1698 = bits(ic_miss_buff_data[1], 31, 0) @[el2_ifu_mem_ctl.scala 444:215] + node _T_1699 = eq(byp_fetch_index_1, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 444:179] + node _T_1700 = bits(_T_1699, 0, 0) @[el2_ifu_mem_ctl.scala 444:187] + node _T_1701 = bits(ic_miss_buff_data[2], 31, 0) @[el2_ifu_mem_ctl.scala 444:215] + node _T_1702 = eq(byp_fetch_index_1, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 444:179] + node _T_1703 = bits(_T_1702, 0, 0) @[el2_ifu_mem_ctl.scala 444:187] + node _T_1704 = bits(ic_miss_buff_data[3], 31, 0) @[el2_ifu_mem_ctl.scala 444:215] + node _T_1705 = eq(byp_fetch_index_1, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 444:179] + node _T_1706 = bits(_T_1705, 0, 0) @[el2_ifu_mem_ctl.scala 444:187] + node _T_1707 = bits(ic_miss_buff_data[4], 31, 0) @[el2_ifu_mem_ctl.scala 444:215] + node _T_1708 = eq(byp_fetch_index_1, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 444:179] + node _T_1709 = bits(_T_1708, 0, 0) @[el2_ifu_mem_ctl.scala 444:187] + node _T_1710 = bits(ic_miss_buff_data[5], 31, 0) @[el2_ifu_mem_ctl.scala 444:215] + node _T_1711 = eq(byp_fetch_index_1, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 444:179] + node _T_1712 = bits(_T_1711, 0, 0) @[el2_ifu_mem_ctl.scala 444:187] + node _T_1713 = bits(ic_miss_buff_data[6], 31, 0) @[el2_ifu_mem_ctl.scala 444:215] + node _T_1714 = eq(byp_fetch_index_1, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 444:179] + node _T_1715 = bits(_T_1714, 0, 0) @[el2_ifu_mem_ctl.scala 444:187] + node _T_1716 = bits(ic_miss_buff_data[7], 31, 0) @[el2_ifu_mem_ctl.scala 444:215] + node _T_1717 = eq(byp_fetch_index_1, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 444:179] + node _T_1718 = bits(_T_1717, 0, 0) @[el2_ifu_mem_ctl.scala 444:187] + node _T_1719 = bits(ic_miss_buff_data[8], 31, 0) @[el2_ifu_mem_ctl.scala 444:215] + node _T_1720 = eq(byp_fetch_index_1, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 444:179] + node _T_1721 = bits(_T_1720, 0, 0) @[el2_ifu_mem_ctl.scala 444:187] + node _T_1722 = bits(ic_miss_buff_data[9], 31, 0) @[el2_ifu_mem_ctl.scala 444:215] + node _T_1723 = eq(byp_fetch_index_1, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 444:179] + node _T_1724 = bits(_T_1723, 0, 0) @[el2_ifu_mem_ctl.scala 444:187] + node _T_1725 = bits(ic_miss_buff_data[10], 31, 0) @[el2_ifu_mem_ctl.scala 444:215] + node _T_1726 = eq(byp_fetch_index_1, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 444:179] + node _T_1727 = bits(_T_1726, 0, 0) @[el2_ifu_mem_ctl.scala 444:187] + node _T_1728 = bits(ic_miss_buff_data[11], 31, 0) @[el2_ifu_mem_ctl.scala 444:215] + node _T_1729 = eq(byp_fetch_index_1, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 444:179] + node _T_1730 = bits(_T_1729, 0, 0) @[el2_ifu_mem_ctl.scala 444:187] + node _T_1731 = bits(ic_miss_buff_data[12], 31, 0) @[el2_ifu_mem_ctl.scala 444:215] + node _T_1732 = eq(byp_fetch_index_1, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 444:179] + node _T_1733 = bits(_T_1732, 0, 0) @[el2_ifu_mem_ctl.scala 444:187] + node _T_1734 = bits(ic_miss_buff_data[13], 31, 0) @[el2_ifu_mem_ctl.scala 444:215] + node _T_1735 = eq(byp_fetch_index_1, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 444:179] + node _T_1736 = bits(_T_1735, 0, 0) @[el2_ifu_mem_ctl.scala 444:187] + node _T_1737 = bits(ic_miss_buff_data[14], 31, 0) @[el2_ifu_mem_ctl.scala 444:215] + node _T_1738 = eq(byp_fetch_index_1, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 444:179] + node _T_1739 = bits(_T_1738, 0, 0) @[el2_ifu_mem_ctl.scala 444:187] + node _T_1740 = bits(ic_miss_buff_data[15], 31, 0) @[el2_ifu_mem_ctl.scala 444:215] + node _T_1741 = mux(_T_1694, _T_1695, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1742 = mux(_T_1697, _T_1698, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1743 = mux(_T_1700, _T_1701, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1744 = mux(_T_1703, _T_1704, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1745 = mux(_T_1706, _T_1707, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1746 = mux(_T_1709, _T_1710, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1747 = mux(_T_1712, _T_1713, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1748 = mux(_T_1715, _T_1716, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1749 = mux(_T_1718, _T_1719, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1750 = mux(_T_1721, _T_1722, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1751 = mux(_T_1724, _T_1725, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1752 = mux(_T_1727, _T_1728, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1753 = mux(_T_1730, _T_1731, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1754 = mux(_T_1733, _T_1734, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1755 = mux(_T_1736, _T_1737, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1756 = mux(_T_1739, _T_1740, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1757 = or(_T_1741, _T_1742) @[Mux.scala 27:72] + node _T_1758 = or(_T_1757, _T_1743) @[Mux.scala 27:72] + node _T_1759 = or(_T_1758, _T_1744) @[Mux.scala 27:72] + node _T_1760 = or(_T_1759, _T_1745) @[Mux.scala 27:72] + node _T_1761 = or(_T_1760, _T_1746) @[Mux.scala 27:72] + node _T_1762 = or(_T_1761, _T_1747) @[Mux.scala 27:72] + node _T_1763 = or(_T_1762, _T_1748) @[Mux.scala 27:72] + node _T_1764 = or(_T_1763, _T_1749) @[Mux.scala 27:72] + node _T_1765 = or(_T_1764, _T_1750) @[Mux.scala 27:72] + node _T_1766 = or(_T_1765, _T_1751) @[Mux.scala 27:72] + node _T_1767 = or(_T_1766, _T_1752) @[Mux.scala 27:72] + node _T_1768 = or(_T_1767, _T_1753) @[Mux.scala 27:72] + node _T_1769 = or(_T_1768, _T_1754) @[Mux.scala 27:72] + node _T_1770 = or(_T_1769, _T_1755) @[Mux.scala 27:72] + node _T_1771 = or(_T_1770, _T_1756) @[Mux.scala 27:72] + wire _T_1772 : UInt<32> @[Mux.scala 27:72] + _T_1772 <= _T_1771 @[Mux.scala 27:72] + node _T_1773 = eq(byp_fetch_index_0, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 444:285] + node _T_1774 = bits(_T_1773, 0, 0) @[el2_ifu_mem_ctl.scala 444:293] + node _T_1775 = bits(ic_miss_buff_data[0], 31, 0) @[el2_ifu_mem_ctl.scala 444:321] + node _T_1776 = eq(byp_fetch_index_0, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 444:285] + node _T_1777 = bits(_T_1776, 0, 0) @[el2_ifu_mem_ctl.scala 444:293] + node _T_1778 = bits(ic_miss_buff_data[1], 31, 0) @[el2_ifu_mem_ctl.scala 444:321] + node _T_1779 = eq(byp_fetch_index_0, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 444:285] + node _T_1780 = bits(_T_1779, 0, 0) @[el2_ifu_mem_ctl.scala 444:293] + node _T_1781 = bits(ic_miss_buff_data[2], 31, 0) @[el2_ifu_mem_ctl.scala 444:321] + node _T_1782 = eq(byp_fetch_index_0, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 444:285] + node _T_1783 = bits(_T_1782, 0, 0) @[el2_ifu_mem_ctl.scala 444:293] + node _T_1784 = bits(ic_miss_buff_data[3], 31, 0) @[el2_ifu_mem_ctl.scala 444:321] + node _T_1785 = eq(byp_fetch_index_0, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 444:285] + node _T_1786 = bits(_T_1785, 0, 0) @[el2_ifu_mem_ctl.scala 444:293] + node _T_1787 = bits(ic_miss_buff_data[4], 31, 0) @[el2_ifu_mem_ctl.scala 444:321] + node _T_1788 = eq(byp_fetch_index_0, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 444:285] + node _T_1789 = bits(_T_1788, 0, 0) @[el2_ifu_mem_ctl.scala 444:293] + node _T_1790 = bits(ic_miss_buff_data[5], 31, 0) @[el2_ifu_mem_ctl.scala 444:321] + node _T_1791 = eq(byp_fetch_index_0, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 444:285] + node _T_1792 = bits(_T_1791, 0, 0) @[el2_ifu_mem_ctl.scala 444:293] + node _T_1793 = bits(ic_miss_buff_data[6], 31, 0) @[el2_ifu_mem_ctl.scala 444:321] + node _T_1794 = eq(byp_fetch_index_0, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 444:285] + node _T_1795 = bits(_T_1794, 0, 0) @[el2_ifu_mem_ctl.scala 444:293] + node _T_1796 = bits(ic_miss_buff_data[7], 31, 0) @[el2_ifu_mem_ctl.scala 444:321] + node _T_1797 = eq(byp_fetch_index_0, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 444:285] + node _T_1798 = bits(_T_1797, 0, 0) @[el2_ifu_mem_ctl.scala 444:293] + node _T_1799 = bits(ic_miss_buff_data[8], 31, 0) @[el2_ifu_mem_ctl.scala 444:321] + node _T_1800 = eq(byp_fetch_index_0, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 444:285] + node _T_1801 = bits(_T_1800, 0, 0) @[el2_ifu_mem_ctl.scala 444:293] + node _T_1802 = bits(ic_miss_buff_data[9], 31, 0) @[el2_ifu_mem_ctl.scala 444:321] + node _T_1803 = eq(byp_fetch_index_0, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 444:285] + node _T_1804 = bits(_T_1803, 0, 0) @[el2_ifu_mem_ctl.scala 444:293] + node _T_1805 = bits(ic_miss_buff_data[10], 31, 0) @[el2_ifu_mem_ctl.scala 444:321] + node _T_1806 = eq(byp_fetch_index_0, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 444:285] + node _T_1807 = bits(_T_1806, 0, 0) @[el2_ifu_mem_ctl.scala 444:293] + node _T_1808 = bits(ic_miss_buff_data[11], 31, 0) @[el2_ifu_mem_ctl.scala 444:321] + node _T_1809 = eq(byp_fetch_index_0, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 444:285] + node _T_1810 = bits(_T_1809, 0, 0) @[el2_ifu_mem_ctl.scala 444:293] + node _T_1811 = bits(ic_miss_buff_data[12], 31, 0) @[el2_ifu_mem_ctl.scala 444:321] + node _T_1812 = eq(byp_fetch_index_0, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 444:285] + node _T_1813 = bits(_T_1812, 0, 0) @[el2_ifu_mem_ctl.scala 444:293] + node _T_1814 = bits(ic_miss_buff_data[13], 31, 0) @[el2_ifu_mem_ctl.scala 444:321] + node _T_1815 = eq(byp_fetch_index_0, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 444:285] + node _T_1816 = bits(_T_1815, 0, 0) @[el2_ifu_mem_ctl.scala 444:293] + node _T_1817 = bits(ic_miss_buff_data[14], 31, 0) @[el2_ifu_mem_ctl.scala 444:321] + node _T_1818 = eq(byp_fetch_index_0, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 444:285] + node _T_1819 = bits(_T_1818, 0, 0) @[el2_ifu_mem_ctl.scala 444:293] + node _T_1820 = bits(ic_miss_buff_data[15], 31, 0) @[el2_ifu_mem_ctl.scala 444:321] + node _T_1821 = mux(_T_1774, _T_1775, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1822 = mux(_T_1777, _T_1778, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1823 = mux(_T_1780, _T_1781, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1824 = mux(_T_1783, _T_1784, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1825 = mux(_T_1786, _T_1787, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1826 = mux(_T_1789, _T_1790, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1827 = mux(_T_1792, _T_1793, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1828 = mux(_T_1795, _T_1796, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1829 = mux(_T_1798, _T_1799, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1830 = mux(_T_1801, _T_1802, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1831 = mux(_T_1804, _T_1805, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1832 = mux(_T_1807, _T_1808, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1833 = mux(_T_1810, _T_1811, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1834 = mux(_T_1813, _T_1814, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1835 = mux(_T_1816, _T_1817, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1836 = mux(_T_1819, _T_1820, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1837 = or(_T_1821, _T_1822) @[Mux.scala 27:72] + node _T_1838 = or(_T_1837, _T_1823) @[Mux.scala 27:72] + node _T_1839 = or(_T_1838, _T_1824) @[Mux.scala 27:72] + node _T_1840 = or(_T_1839, _T_1825) @[Mux.scala 27:72] + node _T_1841 = or(_T_1840, _T_1826) @[Mux.scala 27:72] + node _T_1842 = or(_T_1841, _T_1827) @[Mux.scala 27:72] + node _T_1843 = or(_T_1842, _T_1828) @[Mux.scala 27:72] + node _T_1844 = or(_T_1843, _T_1829) @[Mux.scala 27:72] + node _T_1845 = or(_T_1844, _T_1830) @[Mux.scala 27:72] + node _T_1846 = or(_T_1845, _T_1831) @[Mux.scala 27:72] + node _T_1847 = or(_T_1846, _T_1832) @[Mux.scala 27:72] + node _T_1848 = or(_T_1847, _T_1833) @[Mux.scala 27:72] + node _T_1849 = or(_T_1848, _T_1834) @[Mux.scala 27:72] + node _T_1850 = or(_T_1849, _T_1835) @[Mux.scala 27:72] + node _T_1851 = or(_T_1850, _T_1836) @[Mux.scala 27:72] + wire _T_1852 : UInt<32> @[Mux.scala 27:72] + _T_1852 <= _T_1851 @[Mux.scala 27:72] + node _T_1853 = cat(_T_1692, _T_1772) @[Cat.scala 29:58] + node _T_1854 = cat(_T_1853, _T_1852) @[Cat.scala 29:58] + node _T_1855 = eq(byp_fetch_index_inc_1, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 445:73] + node _T_1856 = bits(_T_1855, 0, 0) @[el2_ifu_mem_ctl.scala 445:81] + node _T_1857 = bits(ic_miss_buff_data[0], 15, 0) @[el2_ifu_mem_ctl.scala 445:109] + node _T_1858 = eq(byp_fetch_index_inc_1, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 445:73] + node _T_1859 = bits(_T_1858, 0, 0) @[el2_ifu_mem_ctl.scala 445:81] + node _T_1860 = bits(ic_miss_buff_data[1], 15, 0) @[el2_ifu_mem_ctl.scala 445:109] + node _T_1861 = eq(byp_fetch_index_inc_1, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 445:73] + node _T_1862 = bits(_T_1861, 0, 0) @[el2_ifu_mem_ctl.scala 445:81] + node _T_1863 = bits(ic_miss_buff_data[2], 15, 0) @[el2_ifu_mem_ctl.scala 445:109] + node _T_1864 = eq(byp_fetch_index_inc_1, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 445:73] + node _T_1865 = bits(_T_1864, 0, 0) @[el2_ifu_mem_ctl.scala 445:81] + node _T_1866 = bits(ic_miss_buff_data[3], 15, 0) @[el2_ifu_mem_ctl.scala 445:109] + node _T_1867 = eq(byp_fetch_index_inc_1, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 445:73] + node _T_1868 = bits(_T_1867, 0, 0) @[el2_ifu_mem_ctl.scala 445:81] + node _T_1869 = bits(ic_miss_buff_data[4], 15, 0) @[el2_ifu_mem_ctl.scala 445:109] + node _T_1870 = eq(byp_fetch_index_inc_1, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 445:73] + node _T_1871 = bits(_T_1870, 0, 0) @[el2_ifu_mem_ctl.scala 445:81] + node _T_1872 = bits(ic_miss_buff_data[5], 15, 0) @[el2_ifu_mem_ctl.scala 445:109] + node _T_1873 = eq(byp_fetch_index_inc_1, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 445:73] + node _T_1874 = bits(_T_1873, 0, 0) @[el2_ifu_mem_ctl.scala 445:81] + node _T_1875 = bits(ic_miss_buff_data[6], 15, 0) @[el2_ifu_mem_ctl.scala 445:109] + node _T_1876 = eq(byp_fetch_index_inc_1, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 445:73] + node _T_1877 = bits(_T_1876, 0, 0) @[el2_ifu_mem_ctl.scala 445:81] + node _T_1878 = bits(ic_miss_buff_data[7], 15, 0) @[el2_ifu_mem_ctl.scala 445:109] + node _T_1879 = eq(byp_fetch_index_inc_1, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 445:73] + node _T_1880 = bits(_T_1879, 0, 0) @[el2_ifu_mem_ctl.scala 445:81] + node _T_1881 = bits(ic_miss_buff_data[8], 15, 0) @[el2_ifu_mem_ctl.scala 445:109] + node _T_1882 = eq(byp_fetch_index_inc_1, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 445:73] + node _T_1883 = bits(_T_1882, 0, 0) @[el2_ifu_mem_ctl.scala 445:81] + node _T_1884 = bits(ic_miss_buff_data[9], 15, 0) @[el2_ifu_mem_ctl.scala 445:109] + node _T_1885 = eq(byp_fetch_index_inc_1, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 445:73] + node _T_1886 = bits(_T_1885, 0, 0) @[el2_ifu_mem_ctl.scala 445:81] + node _T_1887 = bits(ic_miss_buff_data[10], 15, 0) @[el2_ifu_mem_ctl.scala 445:109] + node _T_1888 = eq(byp_fetch_index_inc_1, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 445:73] + node _T_1889 = bits(_T_1888, 0, 0) @[el2_ifu_mem_ctl.scala 445:81] + node _T_1890 = bits(ic_miss_buff_data[11], 15, 0) @[el2_ifu_mem_ctl.scala 445:109] + node _T_1891 = eq(byp_fetch_index_inc_1, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 445:73] + node _T_1892 = bits(_T_1891, 0, 0) @[el2_ifu_mem_ctl.scala 445:81] + node _T_1893 = bits(ic_miss_buff_data[12], 15, 0) @[el2_ifu_mem_ctl.scala 445:109] + node _T_1894 = eq(byp_fetch_index_inc_1, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 445:73] + node _T_1895 = bits(_T_1894, 0, 0) @[el2_ifu_mem_ctl.scala 445:81] + node _T_1896 = bits(ic_miss_buff_data[13], 15, 0) @[el2_ifu_mem_ctl.scala 445:109] + node _T_1897 = eq(byp_fetch_index_inc_1, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 445:73] + node _T_1898 = bits(_T_1897, 0, 0) @[el2_ifu_mem_ctl.scala 445:81] + node _T_1899 = bits(ic_miss_buff_data[14], 15, 0) @[el2_ifu_mem_ctl.scala 445:109] + node _T_1900 = eq(byp_fetch_index_inc_1, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 445:73] + node _T_1901 = bits(_T_1900, 0, 0) @[el2_ifu_mem_ctl.scala 445:81] + node _T_1902 = bits(ic_miss_buff_data[15], 15, 0) @[el2_ifu_mem_ctl.scala 445:109] + node _T_1903 = mux(_T_1856, _T_1857, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1904 = mux(_T_1859, _T_1860, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1905 = mux(_T_1862, _T_1863, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1906 = mux(_T_1865, _T_1866, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1907 = mux(_T_1868, _T_1869, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1908 = mux(_T_1871, _T_1872, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1909 = mux(_T_1874, _T_1875, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1910 = mux(_T_1877, _T_1878, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1911 = mux(_T_1880, _T_1881, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1912 = mux(_T_1883, _T_1884, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1913 = mux(_T_1886, _T_1887, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1914 = mux(_T_1889, _T_1890, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1915 = mux(_T_1892, _T_1893, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1916 = mux(_T_1895, _T_1896, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1917 = mux(_T_1898, _T_1899, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1918 = mux(_T_1901, _T_1902, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1919 = or(_T_1903, _T_1904) @[Mux.scala 27:72] + node _T_1920 = or(_T_1919, _T_1905) @[Mux.scala 27:72] + node _T_1921 = or(_T_1920, _T_1906) @[Mux.scala 27:72] + node _T_1922 = or(_T_1921, _T_1907) @[Mux.scala 27:72] + node _T_1923 = or(_T_1922, _T_1908) @[Mux.scala 27:72] + node _T_1924 = or(_T_1923, _T_1909) @[Mux.scala 27:72] + node _T_1925 = or(_T_1924, _T_1910) @[Mux.scala 27:72] + node _T_1926 = or(_T_1925, _T_1911) @[Mux.scala 27:72] + node _T_1927 = or(_T_1926, _T_1912) @[Mux.scala 27:72] + node _T_1928 = or(_T_1927, _T_1913) @[Mux.scala 27:72] + node _T_1929 = or(_T_1928, _T_1914) @[Mux.scala 27:72] + node _T_1930 = or(_T_1929, _T_1915) @[Mux.scala 27:72] + node _T_1931 = or(_T_1930, _T_1916) @[Mux.scala 27:72] + node _T_1932 = or(_T_1931, _T_1917) @[Mux.scala 27:72] + node _T_1933 = or(_T_1932, _T_1918) @[Mux.scala 27:72] + wire _T_1934 : UInt<16> @[Mux.scala 27:72] + _T_1934 <= _T_1933 @[Mux.scala 27:72] + node _T_1935 = eq(byp_fetch_index_inc_0, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 445:183] + node _T_1936 = bits(_T_1935, 0, 0) @[el2_ifu_mem_ctl.scala 445:191] + node _T_1937 = bits(ic_miss_buff_data[0], 31, 0) @[el2_ifu_mem_ctl.scala 445:219] + node _T_1938 = eq(byp_fetch_index_inc_0, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 445:183] + node _T_1939 = bits(_T_1938, 0, 0) @[el2_ifu_mem_ctl.scala 445:191] + node _T_1940 = bits(ic_miss_buff_data[1], 31, 0) @[el2_ifu_mem_ctl.scala 445:219] + node _T_1941 = eq(byp_fetch_index_inc_0, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 445:183] + node _T_1942 = bits(_T_1941, 0, 0) @[el2_ifu_mem_ctl.scala 445:191] + node _T_1943 = bits(ic_miss_buff_data[2], 31, 0) @[el2_ifu_mem_ctl.scala 445:219] + node _T_1944 = eq(byp_fetch_index_inc_0, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 445:183] + node _T_1945 = bits(_T_1944, 0, 0) @[el2_ifu_mem_ctl.scala 445:191] + node _T_1946 = bits(ic_miss_buff_data[3], 31, 0) @[el2_ifu_mem_ctl.scala 445:219] + node _T_1947 = eq(byp_fetch_index_inc_0, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 445:183] + node _T_1948 = bits(_T_1947, 0, 0) @[el2_ifu_mem_ctl.scala 445:191] + node _T_1949 = bits(ic_miss_buff_data[4], 31, 0) @[el2_ifu_mem_ctl.scala 445:219] + node _T_1950 = eq(byp_fetch_index_inc_0, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 445:183] + node _T_1951 = bits(_T_1950, 0, 0) @[el2_ifu_mem_ctl.scala 445:191] + node _T_1952 = bits(ic_miss_buff_data[5], 31, 0) @[el2_ifu_mem_ctl.scala 445:219] + node _T_1953 = eq(byp_fetch_index_inc_0, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 445:183] + node _T_1954 = bits(_T_1953, 0, 0) @[el2_ifu_mem_ctl.scala 445:191] + node _T_1955 = bits(ic_miss_buff_data[6], 31, 0) @[el2_ifu_mem_ctl.scala 445:219] + node _T_1956 = eq(byp_fetch_index_inc_0, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 445:183] + node _T_1957 = bits(_T_1956, 0, 0) @[el2_ifu_mem_ctl.scala 445:191] + node _T_1958 = bits(ic_miss_buff_data[7], 31, 0) @[el2_ifu_mem_ctl.scala 445:219] + node _T_1959 = eq(byp_fetch_index_inc_0, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 445:183] + node _T_1960 = bits(_T_1959, 0, 0) @[el2_ifu_mem_ctl.scala 445:191] + node _T_1961 = bits(ic_miss_buff_data[8], 31, 0) @[el2_ifu_mem_ctl.scala 445:219] + node _T_1962 = eq(byp_fetch_index_inc_0, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 445:183] + node _T_1963 = bits(_T_1962, 0, 0) @[el2_ifu_mem_ctl.scala 445:191] + node _T_1964 = bits(ic_miss_buff_data[9], 31, 0) @[el2_ifu_mem_ctl.scala 445:219] + node _T_1965 = eq(byp_fetch_index_inc_0, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 445:183] + node _T_1966 = bits(_T_1965, 0, 0) @[el2_ifu_mem_ctl.scala 445:191] + node _T_1967 = bits(ic_miss_buff_data[10], 31, 0) @[el2_ifu_mem_ctl.scala 445:219] + node _T_1968 = eq(byp_fetch_index_inc_0, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 445:183] + node _T_1969 = bits(_T_1968, 0, 0) @[el2_ifu_mem_ctl.scala 445:191] + node _T_1970 = bits(ic_miss_buff_data[11], 31, 0) @[el2_ifu_mem_ctl.scala 445:219] + node _T_1971 = eq(byp_fetch_index_inc_0, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 445:183] + node _T_1972 = bits(_T_1971, 0, 0) @[el2_ifu_mem_ctl.scala 445:191] + node _T_1973 = bits(ic_miss_buff_data[12], 31, 0) @[el2_ifu_mem_ctl.scala 445:219] + node _T_1974 = eq(byp_fetch_index_inc_0, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 445:183] + node _T_1975 = bits(_T_1974, 0, 0) @[el2_ifu_mem_ctl.scala 445:191] + node _T_1976 = bits(ic_miss_buff_data[13], 31, 0) @[el2_ifu_mem_ctl.scala 445:219] + node _T_1977 = eq(byp_fetch_index_inc_0, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 445:183] + node _T_1978 = bits(_T_1977, 0, 0) @[el2_ifu_mem_ctl.scala 445:191] + node _T_1979 = bits(ic_miss_buff_data[14], 31, 0) @[el2_ifu_mem_ctl.scala 445:219] + node _T_1980 = eq(byp_fetch_index_inc_0, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 445:183] + node _T_1981 = bits(_T_1980, 0, 0) @[el2_ifu_mem_ctl.scala 445:191] + node _T_1982 = bits(ic_miss_buff_data[15], 31, 0) @[el2_ifu_mem_ctl.scala 445:219] + node _T_1983 = mux(_T_1936, _T_1937, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1984 = mux(_T_1939, _T_1940, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1985 = mux(_T_1942, _T_1943, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1986 = mux(_T_1945, _T_1946, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1987 = mux(_T_1948, _T_1949, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1988 = mux(_T_1951, _T_1952, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1989 = mux(_T_1954, _T_1955, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1990 = mux(_T_1957, _T_1958, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1991 = mux(_T_1960, _T_1961, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1992 = mux(_T_1963, _T_1964, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1993 = mux(_T_1966, _T_1967, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1994 = mux(_T_1969, _T_1970, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1995 = mux(_T_1972, _T_1973, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1996 = mux(_T_1975, _T_1976, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1997 = mux(_T_1978, _T_1979, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1998 = mux(_T_1981, _T_1982, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1999 = or(_T_1983, _T_1984) @[Mux.scala 27:72] + node _T_2000 = or(_T_1999, _T_1985) @[Mux.scala 27:72] + node _T_2001 = or(_T_2000, _T_1986) @[Mux.scala 27:72] + node _T_2002 = or(_T_2001, _T_1987) @[Mux.scala 27:72] + node _T_2003 = or(_T_2002, _T_1988) @[Mux.scala 27:72] + node _T_2004 = or(_T_2003, _T_1989) @[Mux.scala 27:72] + node _T_2005 = or(_T_2004, _T_1990) @[Mux.scala 27:72] + node _T_2006 = or(_T_2005, _T_1991) @[Mux.scala 27:72] + node _T_2007 = or(_T_2006, _T_1992) @[Mux.scala 27:72] + node _T_2008 = or(_T_2007, _T_1993) @[Mux.scala 27:72] + node _T_2009 = or(_T_2008, _T_1994) @[Mux.scala 27:72] + node _T_2010 = or(_T_2009, _T_1995) @[Mux.scala 27:72] + node _T_2011 = or(_T_2010, _T_1996) @[Mux.scala 27:72] + node _T_2012 = or(_T_2011, _T_1997) @[Mux.scala 27:72] + node _T_2013 = or(_T_2012, _T_1998) @[Mux.scala 27:72] + wire _T_2014 : UInt<32> @[Mux.scala 27:72] + _T_2014 <= _T_2013 @[Mux.scala 27:72] + node _T_2015 = eq(byp_fetch_index_1, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 445:289] + node _T_2016 = bits(_T_2015, 0, 0) @[el2_ifu_mem_ctl.scala 445:297] + node _T_2017 = bits(ic_miss_buff_data[0], 31, 0) @[el2_ifu_mem_ctl.scala 445:325] + node _T_2018 = eq(byp_fetch_index_1, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 445:289] + node _T_2019 = bits(_T_2018, 0, 0) @[el2_ifu_mem_ctl.scala 445:297] + node _T_2020 = bits(ic_miss_buff_data[1], 31, 0) @[el2_ifu_mem_ctl.scala 445:325] + node _T_2021 = eq(byp_fetch_index_1, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 445:289] + node _T_2022 = bits(_T_2021, 0, 0) @[el2_ifu_mem_ctl.scala 445:297] + node _T_2023 = bits(ic_miss_buff_data[2], 31, 0) @[el2_ifu_mem_ctl.scala 445:325] + node _T_2024 = eq(byp_fetch_index_1, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 445:289] + node _T_2025 = bits(_T_2024, 0, 0) @[el2_ifu_mem_ctl.scala 445:297] + node _T_2026 = bits(ic_miss_buff_data[3], 31, 0) @[el2_ifu_mem_ctl.scala 445:325] + node _T_2027 = eq(byp_fetch_index_1, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 445:289] + node _T_2028 = bits(_T_2027, 0, 0) @[el2_ifu_mem_ctl.scala 445:297] + node _T_2029 = bits(ic_miss_buff_data[4], 31, 0) @[el2_ifu_mem_ctl.scala 445:325] + node _T_2030 = eq(byp_fetch_index_1, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 445:289] + node _T_2031 = bits(_T_2030, 0, 0) @[el2_ifu_mem_ctl.scala 445:297] + node _T_2032 = bits(ic_miss_buff_data[5], 31, 0) @[el2_ifu_mem_ctl.scala 445:325] + node _T_2033 = eq(byp_fetch_index_1, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 445:289] + node _T_2034 = bits(_T_2033, 0, 0) @[el2_ifu_mem_ctl.scala 445:297] + node _T_2035 = bits(ic_miss_buff_data[6], 31, 0) @[el2_ifu_mem_ctl.scala 445:325] + node _T_2036 = eq(byp_fetch_index_1, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 445:289] + node _T_2037 = bits(_T_2036, 0, 0) @[el2_ifu_mem_ctl.scala 445:297] + node _T_2038 = bits(ic_miss_buff_data[7], 31, 0) @[el2_ifu_mem_ctl.scala 445:325] + node _T_2039 = eq(byp_fetch_index_1, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 445:289] + node _T_2040 = bits(_T_2039, 0, 0) @[el2_ifu_mem_ctl.scala 445:297] + node _T_2041 = bits(ic_miss_buff_data[8], 31, 0) @[el2_ifu_mem_ctl.scala 445:325] + node _T_2042 = eq(byp_fetch_index_1, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 445:289] + node _T_2043 = bits(_T_2042, 0, 0) @[el2_ifu_mem_ctl.scala 445:297] + node _T_2044 = bits(ic_miss_buff_data[9], 31, 0) @[el2_ifu_mem_ctl.scala 445:325] + node _T_2045 = eq(byp_fetch_index_1, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 445:289] + node _T_2046 = bits(_T_2045, 0, 0) @[el2_ifu_mem_ctl.scala 445:297] + node _T_2047 = bits(ic_miss_buff_data[10], 31, 0) @[el2_ifu_mem_ctl.scala 445:325] + node _T_2048 = eq(byp_fetch_index_1, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 445:289] + node _T_2049 = bits(_T_2048, 0, 0) @[el2_ifu_mem_ctl.scala 445:297] + node _T_2050 = bits(ic_miss_buff_data[11], 31, 0) @[el2_ifu_mem_ctl.scala 445:325] + node _T_2051 = eq(byp_fetch_index_1, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 445:289] + node _T_2052 = bits(_T_2051, 0, 0) @[el2_ifu_mem_ctl.scala 445:297] + node _T_2053 = bits(ic_miss_buff_data[12], 31, 0) @[el2_ifu_mem_ctl.scala 445:325] + node _T_2054 = eq(byp_fetch_index_1, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 445:289] + node _T_2055 = bits(_T_2054, 0, 0) @[el2_ifu_mem_ctl.scala 445:297] + node _T_2056 = bits(ic_miss_buff_data[13], 31, 0) @[el2_ifu_mem_ctl.scala 445:325] + node _T_2057 = eq(byp_fetch_index_1, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 445:289] + node _T_2058 = bits(_T_2057, 0, 0) @[el2_ifu_mem_ctl.scala 445:297] + node _T_2059 = bits(ic_miss_buff_data[14], 31, 0) @[el2_ifu_mem_ctl.scala 445:325] + node _T_2060 = eq(byp_fetch_index_1, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 445:289] + node _T_2061 = bits(_T_2060, 0, 0) @[el2_ifu_mem_ctl.scala 445:297] + node _T_2062 = bits(ic_miss_buff_data[15], 31, 0) @[el2_ifu_mem_ctl.scala 445:325] + node _T_2063 = mux(_T_2016, _T_2017, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2064 = mux(_T_2019, _T_2020, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2065 = mux(_T_2022, _T_2023, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2066 = mux(_T_2025, _T_2026, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2067 = mux(_T_2028, _T_2029, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2068 = mux(_T_2031, _T_2032, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2069 = mux(_T_2034, _T_2035, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2070 = mux(_T_2037, _T_2038, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2071 = mux(_T_2040, _T_2041, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2072 = mux(_T_2043, _T_2044, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2073 = mux(_T_2046, _T_2047, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2074 = mux(_T_2049, _T_2050, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2075 = mux(_T_2052, _T_2053, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2076 = mux(_T_2055, _T_2056, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2077 = mux(_T_2058, _T_2059, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2078 = mux(_T_2061, _T_2062, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2079 = or(_T_2063, _T_2064) @[Mux.scala 27:72] + node _T_2080 = or(_T_2079, _T_2065) @[Mux.scala 27:72] + node _T_2081 = or(_T_2080, _T_2066) @[Mux.scala 27:72] + node _T_2082 = or(_T_2081, _T_2067) @[Mux.scala 27:72] + node _T_2083 = or(_T_2082, _T_2068) @[Mux.scala 27:72] + node _T_2084 = or(_T_2083, _T_2069) @[Mux.scala 27:72] + node _T_2085 = or(_T_2084, _T_2070) @[Mux.scala 27:72] + node _T_2086 = or(_T_2085, _T_2071) @[Mux.scala 27:72] + node _T_2087 = or(_T_2086, _T_2072) @[Mux.scala 27:72] + node _T_2088 = or(_T_2087, _T_2073) @[Mux.scala 27:72] + node _T_2089 = or(_T_2088, _T_2074) @[Mux.scala 27:72] + node _T_2090 = or(_T_2089, _T_2075) @[Mux.scala 27:72] + node _T_2091 = or(_T_2090, _T_2076) @[Mux.scala 27:72] + node _T_2092 = or(_T_2091, _T_2077) @[Mux.scala 27:72] + node _T_2093 = or(_T_2092, _T_2078) @[Mux.scala 27:72] + wire _T_2094 : UInt<32> @[Mux.scala 27:72] + _T_2094 <= _T_2093 @[Mux.scala 27:72] + node _T_2095 = cat(_T_1934, _T_2014) @[Cat.scala 29:58] + node _T_2096 = cat(_T_2095, _T_2094) @[Cat.scala 29:58] + node ic_byp_data_only_pre_new = mux(_T_1612, _T_1854, _T_2096) @[el2_ifu_mem_ctl.scala 443:37] + node _T_2097 = bits(ifu_fetch_addr_int_f, 0, 0) @[el2_ifu_mem_ctl.scala 447:52] + node _T_2098 = bits(_T_2097, 0, 0) @[el2_ifu_mem_ctl.scala 447:62] + node _T_2099 = eq(_T_2098, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 447:31] + node _T_2100 = bits(ic_byp_data_only_pre_new, 79, 16) @[el2_ifu_mem_ctl.scala 447:128] + node _T_2101 = cat(UInt<16>("h00"), _T_2100) @[Cat.scala 29:58] + node _T_2102 = mux(_T_2099, ic_byp_data_only_pre_new, _T_2101) @[el2_ifu_mem_ctl.scala 447:30] + ic_byp_data_only_new <= _T_2102 @[el2_ifu_mem_ctl.scala 447:24] + node _T_2103 = bits(imb_ff, 5, 5) @[el2_ifu_mem_ctl.scala 449:27] + node _T_2104 = bits(ifu_fetch_addr_int_f, 5, 5) @[el2_ifu_mem_ctl.scala 449:75] + node miss_wrap_f = neq(_T_2103, _T_2104) @[el2_ifu_mem_ctl.scala 449:51] + node _T_2105 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 450:102] + node _T_2106 = eq(_T_2105, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 450:127] + node _T_2107 = bits(_T_2106, 0, 0) @[el2_ifu_mem_ctl.scala 450:135] + node _T_2108 = bits(ic_miss_buff_data_valid, 0, 0) @[el2_ifu_mem_ctl.scala 450:166] + node _T_2109 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 450:102] + node _T_2110 = eq(_T_2109, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 450:127] + node _T_2111 = bits(_T_2110, 0, 0) @[el2_ifu_mem_ctl.scala 450:135] + node _T_2112 = bits(ic_miss_buff_data_valid, 1, 1) @[el2_ifu_mem_ctl.scala 450:166] + node _T_2113 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 450:102] + node _T_2114 = eq(_T_2113, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 450:127] + node _T_2115 = bits(_T_2114, 0, 0) @[el2_ifu_mem_ctl.scala 450:135] + node _T_2116 = bits(ic_miss_buff_data_valid, 2, 2) @[el2_ifu_mem_ctl.scala 450:166] + node _T_2117 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 450:102] + node _T_2118 = eq(_T_2117, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 450:127] + node _T_2119 = bits(_T_2118, 0, 0) @[el2_ifu_mem_ctl.scala 450:135] + node _T_2120 = bits(ic_miss_buff_data_valid, 3, 3) @[el2_ifu_mem_ctl.scala 450:166] + node _T_2121 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 450:102] + node _T_2122 = eq(_T_2121, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 450:127] + node _T_2123 = bits(_T_2122, 0, 0) @[el2_ifu_mem_ctl.scala 450:135] + node _T_2124 = bits(ic_miss_buff_data_valid, 4, 4) @[el2_ifu_mem_ctl.scala 450:166] + node _T_2125 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 450:102] + node _T_2126 = eq(_T_2125, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 450:127] + node _T_2127 = bits(_T_2126, 0, 0) @[el2_ifu_mem_ctl.scala 450:135] + node _T_2128 = bits(ic_miss_buff_data_valid, 5, 5) @[el2_ifu_mem_ctl.scala 450:166] + node _T_2129 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 450:102] + node _T_2130 = eq(_T_2129, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 450:127] + node _T_2131 = bits(_T_2130, 0, 0) @[el2_ifu_mem_ctl.scala 450:135] + node _T_2132 = bits(ic_miss_buff_data_valid, 6, 6) @[el2_ifu_mem_ctl.scala 450:166] + node _T_2133 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 450:102] + node _T_2134 = eq(_T_2133, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 450:127] + node _T_2135 = bits(_T_2134, 0, 0) @[el2_ifu_mem_ctl.scala 450:135] + node _T_2136 = bits(ic_miss_buff_data_valid, 7, 7) @[el2_ifu_mem_ctl.scala 450:166] + node _T_2137 = mux(_T_2107, _T_2108, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2138 = mux(_T_2111, _T_2112, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2139 = mux(_T_2115, _T_2116, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2140 = mux(_T_2119, _T_2120, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2141 = mux(_T_2123, _T_2124, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2142 = mux(_T_2127, _T_2128, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2143 = mux(_T_2131, _T_2132, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2144 = mux(_T_2135, _T_2136, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2145 = or(_T_2137, _T_2138) @[Mux.scala 27:72] + node _T_2146 = or(_T_2145, _T_2139) @[Mux.scala 27:72] + node _T_2147 = or(_T_2146, _T_2140) @[Mux.scala 27:72] + node _T_2148 = or(_T_2147, _T_2141) @[Mux.scala 27:72] + node _T_2149 = or(_T_2148, _T_2142) @[Mux.scala 27:72] + node _T_2150 = or(_T_2149, _T_2143) @[Mux.scala 27:72] + node _T_2151 = or(_T_2150, _T_2144) @[Mux.scala 27:72] + wire ic_miss_buff_data_valid_bypass_index : UInt<1> @[Mux.scala 27:72] + ic_miss_buff_data_valid_bypass_index <= _T_2151 @[Mux.scala 27:72] + node _T_2152 = eq(byp_fetch_index_inc, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 451:110] + node _T_2153 = bits(_T_2152, 0, 0) @[el2_ifu_mem_ctl.scala 451:118] + node _T_2154 = bits(ic_miss_buff_data_valid, 0, 0) @[el2_ifu_mem_ctl.scala 451:149] + node _T_2155 = eq(byp_fetch_index_inc, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 451:110] + node _T_2156 = bits(_T_2155, 0, 0) @[el2_ifu_mem_ctl.scala 451:118] + node _T_2157 = bits(ic_miss_buff_data_valid, 1, 1) @[el2_ifu_mem_ctl.scala 451:149] + node _T_2158 = eq(byp_fetch_index_inc, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 451:110] + node _T_2159 = bits(_T_2158, 0, 0) @[el2_ifu_mem_ctl.scala 451:118] + node _T_2160 = bits(ic_miss_buff_data_valid, 2, 2) @[el2_ifu_mem_ctl.scala 451:149] + node _T_2161 = eq(byp_fetch_index_inc, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 451:110] + node _T_2162 = bits(_T_2161, 0, 0) @[el2_ifu_mem_ctl.scala 451:118] + node _T_2163 = bits(ic_miss_buff_data_valid, 3, 3) @[el2_ifu_mem_ctl.scala 451:149] + node _T_2164 = eq(byp_fetch_index_inc, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 451:110] + node _T_2165 = bits(_T_2164, 0, 0) @[el2_ifu_mem_ctl.scala 451:118] + node _T_2166 = bits(ic_miss_buff_data_valid, 4, 4) @[el2_ifu_mem_ctl.scala 451:149] + node _T_2167 = eq(byp_fetch_index_inc, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 451:110] + node _T_2168 = bits(_T_2167, 0, 0) @[el2_ifu_mem_ctl.scala 451:118] + node _T_2169 = bits(ic_miss_buff_data_valid, 5, 5) @[el2_ifu_mem_ctl.scala 451:149] + node _T_2170 = eq(byp_fetch_index_inc, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 451:110] + node _T_2171 = bits(_T_2170, 0, 0) @[el2_ifu_mem_ctl.scala 451:118] + node _T_2172 = bits(ic_miss_buff_data_valid, 6, 6) @[el2_ifu_mem_ctl.scala 451:149] + node _T_2173 = eq(byp_fetch_index_inc, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 451:110] + node _T_2174 = bits(_T_2173, 0, 0) @[el2_ifu_mem_ctl.scala 451:118] + node _T_2175 = bits(ic_miss_buff_data_valid, 7, 7) @[el2_ifu_mem_ctl.scala 451:149] + node _T_2176 = mux(_T_2153, _T_2154, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2177 = mux(_T_2156, _T_2157, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2178 = mux(_T_2159, _T_2160, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2179 = mux(_T_2162, _T_2163, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2180 = mux(_T_2165, _T_2166, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2181 = mux(_T_2168, _T_2169, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2182 = mux(_T_2171, _T_2172, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2183 = mux(_T_2174, _T_2175, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2184 = or(_T_2176, _T_2177) @[Mux.scala 27:72] + node _T_2185 = or(_T_2184, _T_2178) @[Mux.scala 27:72] + node _T_2186 = or(_T_2185, _T_2179) @[Mux.scala 27:72] + node _T_2187 = or(_T_2186, _T_2180) @[Mux.scala 27:72] + node _T_2188 = or(_T_2187, _T_2181) @[Mux.scala 27:72] + node _T_2189 = or(_T_2188, _T_2182) @[Mux.scala 27:72] + node _T_2190 = or(_T_2189, _T_2183) @[Mux.scala 27:72] + wire ic_miss_buff_data_valid_inc_bypass_index : UInt<1> @[Mux.scala 27:72] + ic_miss_buff_data_valid_inc_bypass_index <= _T_2190 @[Mux.scala 27:72] + node _T_2191 = bits(byp_fetch_index, 1, 1) @[el2_ifu_mem_ctl.scala 452:85] + node _T_2192 = eq(_T_2191, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 452:69] + node _T_2193 = and(ic_miss_buff_data_valid_bypass_index, _T_2192) @[el2_ifu_mem_ctl.scala 452:67] + node _T_2194 = bits(byp_fetch_index, 0, 0) @[el2_ifu_mem_ctl.scala 452:107] + node _T_2195 = eq(_T_2194, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 452:91] + node _T_2196 = and(_T_2193, _T_2195) @[el2_ifu_mem_ctl.scala 452:89] + node _T_2197 = bits(byp_fetch_index, 1, 1) @[el2_ifu_mem_ctl.scala 453:61] + node _T_2198 = eq(_T_2197, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 453:45] + node _T_2199 = and(ic_miss_buff_data_valid_bypass_index, _T_2198) @[el2_ifu_mem_ctl.scala 453:43] + node _T_2200 = bits(byp_fetch_index, 0, 0) @[el2_ifu_mem_ctl.scala 453:83] + node _T_2201 = and(_T_2199, _T_2200) @[el2_ifu_mem_ctl.scala 453:65] + node _T_2202 = or(_T_2196, _T_2201) @[el2_ifu_mem_ctl.scala 452:112] + node _T_2203 = bits(byp_fetch_index, 1, 1) @[el2_ifu_mem_ctl.scala 454:61] + node _T_2204 = and(ic_miss_buff_data_valid_bypass_index, _T_2203) @[el2_ifu_mem_ctl.scala 454:43] + node _T_2205 = bits(byp_fetch_index, 0, 0) @[el2_ifu_mem_ctl.scala 454:83] + node _T_2206 = eq(_T_2205, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 454:67] + node _T_2207 = and(_T_2204, _T_2206) @[el2_ifu_mem_ctl.scala 454:65] + node _T_2208 = or(_T_2202, _T_2207) @[el2_ifu_mem_ctl.scala 453:88] + node _T_2209 = bits(byp_fetch_index, 1, 1) @[el2_ifu_mem_ctl.scala 455:61] + node _T_2210 = and(ic_miss_buff_data_valid_bypass_index, _T_2209) @[el2_ifu_mem_ctl.scala 455:43] + node _T_2211 = bits(byp_fetch_index, 0, 0) @[el2_ifu_mem_ctl.scala 455:83] + node _T_2212 = and(_T_2210, _T_2211) @[el2_ifu_mem_ctl.scala 455:65] + node _T_2213 = and(_T_2212, ic_miss_buff_data_valid_inc_bypass_index) @[el2_ifu_mem_ctl.scala 455:87] + node _T_2214 = or(_T_2208, _T_2213) @[el2_ifu_mem_ctl.scala 454:88] + node _T_2215 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 456:61] + node _T_2216 = mux(UInt<1>("h01"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_2217 = eq(_T_2215, _T_2216) @[el2_ifu_mem_ctl.scala 456:87] + node _T_2218 = and(ic_miss_buff_data_valid_bypass_index, _T_2217) @[el2_ifu_mem_ctl.scala 456:43] + node miss_buff_hit_unq_f = or(_T_2214, _T_2218) @[el2_ifu_mem_ctl.scala 455:131] + node _T_2219 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 458:30] + node _T_2220 = eq(miss_wrap_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 458:68] + node _T_2221 = and(miss_buff_hit_unq_f, _T_2220) @[el2_ifu_mem_ctl.scala 458:66] + node _T_2222 = and(_T_2219, _T_2221) @[el2_ifu_mem_ctl.scala 458:43] + stream_hit_f <= _T_2222 @[el2_ifu_mem_ctl.scala 458:16] + node _T_2223 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 459:31] + node _T_2224 = eq(miss_wrap_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 459:70] + node _T_2225 = and(miss_buff_hit_unq_f, _T_2224) @[el2_ifu_mem_ctl.scala 459:68] + node _T_2226 = eq(_T_2225, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 459:46] + node _T_2227 = and(_T_2223, _T_2226) @[el2_ifu_mem_ctl.scala 459:44] + node _T_2228 = and(_T_2227, ifc_fetch_req_f) @[el2_ifu_mem_ctl.scala 459:84] + stream_miss_f <= _T_2228 @[el2_ifu_mem_ctl.scala 459:17] + node _T_2229 = bits(byp_fetch_index, 4, 1) @[el2_ifu_mem_ctl.scala 460:35] + node _T_2230 = mux(UInt<1>("h01"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_2231 = eq(_T_2229, _T_2230) @[el2_ifu_mem_ctl.scala 460:60] + node _T_2232 = and(_T_2231, ifc_fetch_req_f) @[el2_ifu_mem_ctl.scala 460:94] + node _T_2233 = and(_T_2232, stream_hit_f) @[el2_ifu_mem_ctl.scala 460:112] + stream_eol_f <= _T_2233 @[el2_ifu_mem_ctl.scala 460:16] + node _T_2234 = eq(miss_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 461:55] + node _T_2235 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 461:87] + node _T_2236 = or(_T_2234, _T_2235) @[el2_ifu_mem_ctl.scala 461:74] + node _T_2237 = and(miss_buff_hit_unq_f, _T_2236) @[el2_ifu_mem_ctl.scala 461:41] + crit_byp_hit_f <= _T_2237 @[el2_ifu_mem_ctl.scala 461:18] + node _T_2238 = bits(ifu_bus_rid_ff, 2, 1) @[el2_ifu_mem_ctl.scala 464:37] + node _T_2239 = bits(ifu_bus_rid_ff, 0, 0) @[el2_ifu_mem_ctl.scala 464:70] + node _T_2240 = eq(_T_2239, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 464:55] + node other_tag = cat(_T_2238, _T_2240) @[Cat.scala 29:58] + node _T_2241 = eq(other_tag, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 465:81] + node _T_2242 = bits(_T_2241, 0, 0) @[el2_ifu_mem_ctl.scala 465:89] + node _T_2243 = bits(ic_miss_buff_data_valid, 0, 0) @[el2_ifu_mem_ctl.scala 465:120] + node _T_2244 = eq(other_tag, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 465:81] + node _T_2245 = bits(_T_2244, 0, 0) @[el2_ifu_mem_ctl.scala 465:89] + node _T_2246 = bits(ic_miss_buff_data_valid, 1, 1) @[el2_ifu_mem_ctl.scala 465:120] + node _T_2247 = eq(other_tag, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 465:81] + node _T_2248 = bits(_T_2247, 0, 0) @[el2_ifu_mem_ctl.scala 465:89] + node _T_2249 = bits(ic_miss_buff_data_valid, 2, 2) @[el2_ifu_mem_ctl.scala 465:120] + node _T_2250 = eq(other_tag, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 465:81] + node _T_2251 = bits(_T_2250, 0, 0) @[el2_ifu_mem_ctl.scala 465:89] + node _T_2252 = bits(ic_miss_buff_data_valid, 3, 3) @[el2_ifu_mem_ctl.scala 465:120] + node _T_2253 = eq(other_tag, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 465:81] + node _T_2254 = bits(_T_2253, 0, 0) @[el2_ifu_mem_ctl.scala 465:89] + node _T_2255 = bits(ic_miss_buff_data_valid, 4, 4) @[el2_ifu_mem_ctl.scala 465:120] + node _T_2256 = eq(other_tag, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 465:81] + node _T_2257 = bits(_T_2256, 0, 0) @[el2_ifu_mem_ctl.scala 465:89] + node _T_2258 = bits(ic_miss_buff_data_valid, 5, 5) @[el2_ifu_mem_ctl.scala 465:120] + node _T_2259 = eq(other_tag, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 465:81] + node _T_2260 = bits(_T_2259, 0, 0) @[el2_ifu_mem_ctl.scala 465:89] + node _T_2261 = bits(ic_miss_buff_data_valid, 6, 6) @[el2_ifu_mem_ctl.scala 465:120] + node _T_2262 = eq(other_tag, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 465:81] + node _T_2263 = bits(_T_2262, 0, 0) @[el2_ifu_mem_ctl.scala 465:89] + node _T_2264 = bits(ic_miss_buff_data_valid, 7, 7) @[el2_ifu_mem_ctl.scala 465:120] + node _T_2265 = mux(_T_2242, _T_2243, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2266 = mux(_T_2245, _T_2246, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2267 = mux(_T_2248, _T_2249, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2268 = mux(_T_2251, _T_2252, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2269 = mux(_T_2254, _T_2255, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2270 = mux(_T_2257, _T_2258, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2271 = mux(_T_2260, _T_2261, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2272 = mux(_T_2263, _T_2264, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2273 = or(_T_2265, _T_2266) @[Mux.scala 27:72] + node _T_2274 = or(_T_2273, _T_2267) @[Mux.scala 27:72] + node _T_2275 = or(_T_2274, _T_2268) @[Mux.scala 27:72] + node _T_2276 = or(_T_2275, _T_2269) @[Mux.scala 27:72] + node _T_2277 = or(_T_2276, _T_2270) @[Mux.scala 27:72] + node _T_2278 = or(_T_2277, _T_2271) @[Mux.scala 27:72] + node _T_2279 = or(_T_2278, _T_2272) @[Mux.scala 27:72] + wire second_half_available : UInt<1> @[Mux.scala 27:72] + second_half_available <= _T_2279 @[Mux.scala 27:72] + node _T_2280 = and(second_half_available, bus_ifu_wr_en_ff) @[el2_ifu_mem_ctl.scala 466:46] + write_ic_16_bytes <= _T_2280 @[el2_ifu_mem_ctl.scala 466:21] + node _T_2281 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58] + node _T_2282 = eq(_T_2281, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 467:89] + node _T_2283 = bits(_T_2282, 0, 0) @[el2_ifu_mem_ctl.scala 467:97] + node _T_2284 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58] + node _T_2285 = eq(_T_2284, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 467:89] + node _T_2286 = bits(_T_2285, 0, 0) @[el2_ifu_mem_ctl.scala 467:97] + node _T_2287 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58] + node _T_2288 = eq(_T_2287, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 467:89] + node _T_2289 = bits(_T_2288, 0, 0) @[el2_ifu_mem_ctl.scala 467:97] + node _T_2290 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58] + node _T_2291 = eq(_T_2290, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 467:89] + node _T_2292 = bits(_T_2291, 0, 0) @[el2_ifu_mem_ctl.scala 467:97] + node _T_2293 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58] + node _T_2294 = eq(_T_2293, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 467:89] + node _T_2295 = bits(_T_2294, 0, 0) @[el2_ifu_mem_ctl.scala 467:97] + node _T_2296 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58] + node _T_2297 = eq(_T_2296, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 467:89] + node _T_2298 = bits(_T_2297, 0, 0) @[el2_ifu_mem_ctl.scala 467:97] + node _T_2299 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58] + node _T_2300 = eq(_T_2299, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 467:89] + node _T_2301 = bits(_T_2300, 0, 0) @[el2_ifu_mem_ctl.scala 467:97] + node _T_2302 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58] + node _T_2303 = eq(_T_2302, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 467:89] + node _T_2304 = bits(_T_2303, 0, 0) @[el2_ifu_mem_ctl.scala 467:97] + node _T_2305 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58] + node _T_2306 = eq(_T_2305, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 467:89] + node _T_2307 = bits(_T_2306, 0, 0) @[el2_ifu_mem_ctl.scala 467:97] + node _T_2308 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58] + node _T_2309 = eq(_T_2308, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 467:89] + node _T_2310 = bits(_T_2309, 0, 0) @[el2_ifu_mem_ctl.scala 467:97] + node _T_2311 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58] + node _T_2312 = eq(_T_2311, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 467:89] + node _T_2313 = bits(_T_2312, 0, 0) @[el2_ifu_mem_ctl.scala 467:97] + node _T_2314 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58] + node _T_2315 = eq(_T_2314, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 467:89] + node _T_2316 = bits(_T_2315, 0, 0) @[el2_ifu_mem_ctl.scala 467:97] + node _T_2317 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58] + node _T_2318 = eq(_T_2317, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 467:89] + node _T_2319 = bits(_T_2318, 0, 0) @[el2_ifu_mem_ctl.scala 467:97] + node _T_2320 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58] + node _T_2321 = eq(_T_2320, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 467:89] + node _T_2322 = bits(_T_2321, 0, 0) @[el2_ifu_mem_ctl.scala 467:97] + node _T_2323 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58] + node _T_2324 = eq(_T_2323, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 467:89] + node _T_2325 = bits(_T_2324, 0, 0) @[el2_ifu_mem_ctl.scala 467:97] + node _T_2326 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58] + node _T_2327 = eq(_T_2326, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 467:89] + node _T_2328 = bits(_T_2327, 0, 0) @[el2_ifu_mem_ctl.scala 467:97] + node _T_2329 = mux(_T_2283, ic_miss_buff_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2330 = mux(_T_2286, ic_miss_buff_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2331 = mux(_T_2289, ic_miss_buff_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2332 = mux(_T_2292, ic_miss_buff_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2333 = mux(_T_2295, ic_miss_buff_data[4], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2334 = mux(_T_2298, ic_miss_buff_data[5], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2335 = mux(_T_2301, ic_miss_buff_data[6], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2336 = mux(_T_2304, ic_miss_buff_data[7], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2337 = mux(_T_2307, ic_miss_buff_data[8], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2338 = mux(_T_2310, ic_miss_buff_data[9], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2339 = mux(_T_2313, ic_miss_buff_data[10], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2340 = mux(_T_2316, ic_miss_buff_data[11], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2341 = mux(_T_2319, ic_miss_buff_data[12], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2342 = mux(_T_2322, ic_miss_buff_data[13], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2343 = mux(_T_2325, ic_miss_buff_data[14], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2344 = mux(_T_2328, ic_miss_buff_data[15], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2345 = or(_T_2329, _T_2330) @[Mux.scala 27:72] + node _T_2346 = or(_T_2345, _T_2331) @[Mux.scala 27:72] + node _T_2347 = or(_T_2346, _T_2332) @[Mux.scala 27:72] + node _T_2348 = or(_T_2347, _T_2333) @[Mux.scala 27:72] + node _T_2349 = or(_T_2348, _T_2334) @[Mux.scala 27:72] + node _T_2350 = or(_T_2349, _T_2335) @[Mux.scala 27:72] + node _T_2351 = or(_T_2350, _T_2336) @[Mux.scala 27:72] + node _T_2352 = or(_T_2351, _T_2337) @[Mux.scala 27:72] + node _T_2353 = or(_T_2352, _T_2338) @[Mux.scala 27:72] + node _T_2354 = or(_T_2353, _T_2339) @[Mux.scala 27:72] + node _T_2355 = or(_T_2354, _T_2340) @[Mux.scala 27:72] + node _T_2356 = or(_T_2355, _T_2341) @[Mux.scala 27:72] + node _T_2357 = or(_T_2356, _T_2342) @[Mux.scala 27:72] + node _T_2358 = or(_T_2357, _T_2343) @[Mux.scala 27:72] + node _T_2359 = or(_T_2358, _T_2344) @[Mux.scala 27:72] + wire _T_2360 : UInt<32> @[Mux.scala 27:72] + _T_2360 <= _T_2359 @[Mux.scala 27:72] + node _T_2361 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2362 = eq(_T_2361, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 468:66] + node _T_2363 = bits(_T_2362, 0, 0) @[el2_ifu_mem_ctl.scala 468:74] + node _T_2364 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2365 = eq(_T_2364, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 468:66] + node _T_2366 = bits(_T_2365, 0, 0) @[el2_ifu_mem_ctl.scala 468:74] + node _T_2367 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2368 = eq(_T_2367, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 468:66] + node _T_2369 = bits(_T_2368, 0, 0) @[el2_ifu_mem_ctl.scala 468:74] + node _T_2370 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2371 = eq(_T_2370, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 468:66] + node _T_2372 = bits(_T_2371, 0, 0) @[el2_ifu_mem_ctl.scala 468:74] + node _T_2373 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2374 = eq(_T_2373, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 468:66] + node _T_2375 = bits(_T_2374, 0, 0) @[el2_ifu_mem_ctl.scala 468:74] + node _T_2376 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2377 = eq(_T_2376, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 468:66] + node _T_2378 = bits(_T_2377, 0, 0) @[el2_ifu_mem_ctl.scala 468:74] + node _T_2379 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2380 = eq(_T_2379, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 468:66] + node _T_2381 = bits(_T_2380, 0, 0) @[el2_ifu_mem_ctl.scala 468:74] + node _T_2382 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2383 = eq(_T_2382, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 468:66] + node _T_2384 = bits(_T_2383, 0, 0) @[el2_ifu_mem_ctl.scala 468:74] + node _T_2385 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2386 = eq(_T_2385, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 468:66] + node _T_2387 = bits(_T_2386, 0, 0) @[el2_ifu_mem_ctl.scala 468:74] + node _T_2388 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2389 = eq(_T_2388, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 468:66] + node _T_2390 = bits(_T_2389, 0, 0) @[el2_ifu_mem_ctl.scala 468:74] + node _T_2391 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2392 = eq(_T_2391, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 468:66] + node _T_2393 = bits(_T_2392, 0, 0) @[el2_ifu_mem_ctl.scala 468:74] + node _T_2394 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2395 = eq(_T_2394, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 468:66] + node _T_2396 = bits(_T_2395, 0, 0) @[el2_ifu_mem_ctl.scala 468:74] + node _T_2397 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2398 = eq(_T_2397, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 468:66] + node _T_2399 = bits(_T_2398, 0, 0) @[el2_ifu_mem_ctl.scala 468:74] + node _T_2400 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2401 = eq(_T_2400, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 468:66] + node _T_2402 = bits(_T_2401, 0, 0) @[el2_ifu_mem_ctl.scala 468:74] + node _T_2403 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2404 = eq(_T_2403, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 468:66] + node _T_2405 = bits(_T_2404, 0, 0) @[el2_ifu_mem_ctl.scala 468:74] + node _T_2406 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2407 = eq(_T_2406, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 468:66] + node _T_2408 = bits(_T_2407, 0, 0) @[el2_ifu_mem_ctl.scala 468:74] + node _T_2409 = mux(_T_2363, ic_miss_buff_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2410 = mux(_T_2366, ic_miss_buff_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2411 = mux(_T_2369, ic_miss_buff_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2412 = mux(_T_2372, ic_miss_buff_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2413 = mux(_T_2375, ic_miss_buff_data[4], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2414 = mux(_T_2378, ic_miss_buff_data[5], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2415 = mux(_T_2381, ic_miss_buff_data[6], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2416 = mux(_T_2384, ic_miss_buff_data[7], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2417 = mux(_T_2387, ic_miss_buff_data[8], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2418 = mux(_T_2390, ic_miss_buff_data[9], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2419 = mux(_T_2393, ic_miss_buff_data[10], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2420 = mux(_T_2396, ic_miss_buff_data[11], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2421 = mux(_T_2399, ic_miss_buff_data[12], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2422 = mux(_T_2402, ic_miss_buff_data[13], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2423 = mux(_T_2405, ic_miss_buff_data[14], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2424 = mux(_T_2408, ic_miss_buff_data[15], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2425 = or(_T_2409, _T_2410) @[Mux.scala 27:72] + node _T_2426 = or(_T_2425, _T_2411) @[Mux.scala 27:72] + node _T_2427 = or(_T_2426, _T_2412) @[Mux.scala 27:72] + node _T_2428 = or(_T_2427, _T_2413) @[Mux.scala 27:72] + node _T_2429 = or(_T_2428, _T_2414) @[Mux.scala 27:72] + node _T_2430 = or(_T_2429, _T_2415) @[Mux.scala 27:72] + node _T_2431 = or(_T_2430, _T_2416) @[Mux.scala 27:72] + node _T_2432 = or(_T_2431, _T_2417) @[Mux.scala 27:72] + node _T_2433 = or(_T_2432, _T_2418) @[Mux.scala 27:72] + node _T_2434 = or(_T_2433, _T_2419) @[Mux.scala 27:72] + node _T_2435 = or(_T_2434, _T_2420) @[Mux.scala 27:72] + node _T_2436 = or(_T_2435, _T_2421) @[Mux.scala 27:72] + node _T_2437 = or(_T_2436, _T_2422) @[Mux.scala 27:72] + node _T_2438 = or(_T_2437, _T_2423) @[Mux.scala 27:72] + node _T_2439 = or(_T_2438, _T_2424) @[Mux.scala 27:72] + wire _T_2440 : UInt<32> @[Mux.scala 27:72] + _T_2440 <= _T_2439 @[Mux.scala 27:72] + node _T_2441 = cat(_T_2360, _T_2440) @[Cat.scala 29:58] + ic_miss_buff_half <= _T_2441 @[el2_ifu_mem_ctl.scala 467:21] + node _T_2442 = and(io.ic_tag_perr, sel_ic_data) @[el2_ifu_mem_ctl.scala 472:44] + node _T_2443 = or(ifc_region_acc_fault_final_f, ifc_bus_acc_fault_f) @[el2_ifu_mem_ctl.scala 472:91] + node _T_2444 = eq(_T_2443, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 472:60] + node _T_2445 = and(_T_2442, _T_2444) @[el2_ifu_mem_ctl.scala 472:58] + ic_rd_parity_final_err <= _T_2445 @[el2_ifu_mem_ctl.scala 472:26] + wire ifu_ic_rw_int_addr_ff : UInt<7> + ifu_ic_rw_int_addr_ff <= UInt<1>("h00") + wire perr_sb_write_status : UInt<1> + perr_sb_write_status <= UInt<1>("h00") + reg perr_ic_index_ff : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when perr_sb_write_status : @[Reg.scala 28:19] + perr_ic_index_ff <= ifu_ic_rw_int_addr_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + wire perr_sel_invalidate : UInt<1> + perr_sel_invalidate <= UInt<1>("h00") + node _T_2446 = bits(perr_sel_invalidate, 0, 0) @[Bitwise.scala 72:15] + node perr_err_inv_way = mux(_T_2446, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_2447 = eq(perr_state, UInt<3>("h03")) @[el2_ifu_mem_ctl.scala 479:34] + iccm_correct_ecc <= _T_2447 @[el2_ifu_mem_ctl.scala 479:20] + node dma_sb_err_state = eq(perr_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 480:37] + wire dma_sb_err_state_ff : UInt<1> @[el2_ifu_mem_ctl.scala 481:33] + node _T_2448 = eq(dma_sb_err_state_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 482:49] + node _T_2449 = and(iccm_correct_ecc, _T_2448) @[el2_ifu_mem_ctl.scala 482:47] + io.iccm_buf_correct_ecc <= _T_2449 @[el2_ifu_mem_ctl.scala 482:27] + reg _T_2450 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 483:58] + _T_2450 <= dma_sb_err_state @[el2_ifu_mem_ctl.scala 483:58] + dma_sb_err_state_ff <= _T_2450 @[el2_ifu_mem_ctl.scala 483:23] + wire perr_nxtstate : UInt<3> + perr_nxtstate <= UInt<1>("h00") + wire perr_state_en : UInt<1> + perr_state_en <= UInt<1>("h00") + wire iccm_error_start : UInt<1> + iccm_error_start <= UInt<1>("h00") + node _T_2451 = eq(UInt<3>("h00"), perr_state) @[Conditional.scala 37:30] + when _T_2451 : @[Conditional.scala 40:58] + node _T_2452 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 491:89] + node _T_2453 = and(io.ic_error_start, _T_2452) @[el2_ifu_mem_ctl.scala 491:87] + node _T_2454 = bits(_T_2453, 0, 0) @[el2_ifu_mem_ctl.scala 491:110] + node _T_2455 = mux(_T_2454, UInt<3>("h01"), UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 491:67] + node _T_2456 = mux(io.iccm_dma_sb_error, UInt<3>("h04"), _T_2455) @[el2_ifu_mem_ctl.scala 491:27] + perr_nxtstate <= _T_2456 @[el2_ifu_mem_ctl.scala 491:21] + node _T_2457 = or(iccm_error_start, io.ic_error_start) @[el2_ifu_mem_ctl.scala 492:44] + node _T_2458 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 492:67] + node _T_2459 = and(_T_2457, _T_2458) @[el2_ifu_mem_ctl.scala 492:65] + node _T_2460 = or(_T_2459, io.iccm_dma_sb_error) @[el2_ifu_mem_ctl.scala 492:88] + node _T_2461 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 492:114] + node _T_2462 = and(_T_2460, _T_2461) @[el2_ifu_mem_ctl.scala 492:112] + perr_state_en <= _T_2462 @[el2_ifu_mem_ctl.scala 492:21] + perr_sb_write_status <= perr_state_en @[el2_ifu_mem_ctl.scala 493:28] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_2463 = eq(UInt<3>("h01"), perr_state) @[Conditional.scala 37:30] + when _T_2463 : @[Conditional.scala 39:67] + perr_nxtstate <= UInt<3>("h00") @[el2_ifu_mem_ctl.scala 496:21] + node _T_2464 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 497:50] + perr_state_en <= _T_2464 @[el2_ifu_mem_ctl.scala 497:21] + node _T_2465 = and(io.dec_tlu_flush_lower_wb, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 498:56] + perr_sel_invalidate <= _T_2465 @[el2_ifu_mem_ctl.scala 498:27] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2466 = eq(UInt<3>("h02"), perr_state) @[Conditional.scala 37:30] + when _T_2466 : @[Conditional.scala 39:67] + node _T_2467 = eq(io.dec_tlu_flush_err_wb, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 501:30] + node _T_2468 = and(_T_2467, io.dec_tlu_flush_lower_wb) @[el2_ifu_mem_ctl.scala 501:55] + node _T_2469 = or(_T_2468, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 501:85] + node _T_2470 = bits(_T_2469, 0, 0) @[el2_ifu_mem_ctl.scala 501:116] + node _T_2471 = mux(_T_2470, UInt<3>("h00"), UInt<3>("h03")) @[el2_ifu_mem_ctl.scala 501:27] + perr_nxtstate <= _T_2471 @[el2_ifu_mem_ctl.scala 501:21] + node _T_2472 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 502:50] + perr_state_en <= _T_2472 @[el2_ifu_mem_ctl.scala 502:21] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2473 = eq(UInt<3>("h04"), perr_state) @[Conditional.scala 37:30] + when _T_2473 : @[Conditional.scala 39:67] + node _T_2474 = mux(io.dec_tlu_force_halt, UInt<3>("h00"), UInt<3>("h03")) @[el2_ifu_mem_ctl.scala 505:27] + perr_nxtstate <= _T_2474 @[el2_ifu_mem_ctl.scala 505:21] + perr_state_en <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 506:21] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2475 = eq(UInt<3>("h03"), perr_state) @[Conditional.scala 37:30] + when _T_2475 : @[Conditional.scala 39:67] + perr_nxtstate <= UInt<3>("h00") @[el2_ifu_mem_ctl.scala 509:21] + perr_state_en <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 510:21] + skip @[Conditional.scala 39:67] + reg _T_2476 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when perr_state_en : @[Reg.scala 28:19] + _T_2476 <= perr_nxtstate @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + perr_state <= _T_2476 @[el2_ifu_mem_ctl.scala 513:14] + wire err_stop_nxtstate : UInt<2> + err_stop_nxtstate <= UInt<1>("h00") + wire err_stop_state_en : UInt<1> + err_stop_state_en <= UInt<1>("h00") + io.iccm_correction_state <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 517:28] + node _T_2477 = eq(UInt<2>("h00"), err_stop_state) @[Conditional.scala 37:30] + when _T_2477 : @[Conditional.scala 40:58] + err_stop_nxtstate <= UInt<2>("h01") @[el2_ifu_mem_ctl.scala 521:25] + node _T_2478 = eq(perr_state, UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 522:66] + node _T_2479 = and(io.dec_tlu_flush_err_wb, _T_2478) @[el2_ifu_mem_ctl.scala 522:52] + node _T_2480 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 522:83] + node _T_2481 = and(_T_2479, _T_2480) @[el2_ifu_mem_ctl.scala 522:81] + err_stop_state_en <= _T_2481 @[el2_ifu_mem_ctl.scala 522:25] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_2482 = eq(UInt<2>("h01"), err_stop_state) @[Conditional.scala 37:30] + when _T_2482 : @[Conditional.scala 39:67] + node _T_2483 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_i0_commit_cmt) @[el2_ifu_mem_ctl.scala 525:59] + node _T_2484 = or(_T_2483, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 525:86] + node _T_2485 = bits(_T_2484, 0, 0) @[el2_ifu_mem_ctl.scala 525:117] + node _T_2486 = eq(io.ifu_fetch_val, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 526:31] + node _T_2487 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_mem_ctl.scala 526:56] + node _T_2488 = and(_T_2487, two_byte_instr) @[el2_ifu_mem_ctl.scala 526:59] + node _T_2489 = or(_T_2486, _T_2488) @[el2_ifu_mem_ctl.scala 526:38] + node _T_2490 = bits(_T_2489, 0, 0) @[el2_ifu_mem_ctl.scala 526:83] + node _T_2491 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_mem_ctl.scala 527:31] + node _T_2492 = bits(_T_2491, 0, 0) @[el2_ifu_mem_ctl.scala 527:41] + node _T_2493 = mux(_T_2492, UInt<2>("h02"), UInt<2>("h01")) @[el2_ifu_mem_ctl.scala 527:14] + node _T_2494 = mux(_T_2490, UInt<2>("h03"), _T_2493) @[el2_ifu_mem_ctl.scala 526:12] + node _T_2495 = mux(_T_2485, UInt<2>("h00"), _T_2494) @[el2_ifu_mem_ctl.scala 525:31] + err_stop_nxtstate <= _T_2495 @[el2_ifu_mem_ctl.scala 525:25] + node _T_2496 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_i0_commit_cmt) @[el2_ifu_mem_ctl.scala 528:54] + node _T_2497 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_mem_ctl.scala 528:99] + node _T_2498 = or(_T_2496, _T_2497) @[el2_ifu_mem_ctl.scala 528:81] + node _T_2499 = or(_T_2498, ifu_bp_hit_taken_q_f) @[el2_ifu_mem_ctl.scala 528:103] + node _T_2500 = or(_T_2499, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 528:126] + err_stop_state_en <= _T_2500 @[el2_ifu_mem_ctl.scala 528:25] + node _T_2501 = bits(io.ifu_fetch_val, 1, 0) @[el2_ifu_mem_ctl.scala 529:43] + node _T_2502 = eq(_T_2501, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 529:48] + node _T_2503 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_mem_ctl.scala 529:75] + node _T_2504 = and(_T_2503, two_byte_instr) @[el2_ifu_mem_ctl.scala 529:79] + node _T_2505 = or(_T_2502, _T_2504) @[el2_ifu_mem_ctl.scala 529:56] + node _T_2506 = or(io.exu_flush_final, io.dec_tlu_i0_commit_cmt) @[el2_ifu_mem_ctl.scala 529:122] + node _T_2507 = eq(_T_2506, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 529:101] + node _T_2508 = and(_T_2505, _T_2507) @[el2_ifu_mem_ctl.scala 529:99] + err_stop_fetch <= _T_2508 @[el2_ifu_mem_ctl.scala 529:22] + io.iccm_correction_state <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 530:32] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2509 = eq(UInt<2>("h02"), err_stop_state) @[Conditional.scala 37:30] + when _T_2509 : @[Conditional.scala 39:67] + node _T_2510 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_i0_commit_cmt) @[el2_ifu_mem_ctl.scala 533:59] + node _T_2511 = or(_T_2510, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 533:86] + node _T_2512 = bits(_T_2511, 0, 0) @[el2_ifu_mem_ctl.scala 533:111] + node _T_2513 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_mem_ctl.scala 534:46] + node _T_2514 = bits(_T_2513, 0, 0) @[el2_ifu_mem_ctl.scala 534:50] + node _T_2515 = mux(_T_2514, UInt<2>("h03"), UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 534:29] + node _T_2516 = mux(_T_2512, UInt<2>("h00"), _T_2515) @[el2_ifu_mem_ctl.scala 533:31] + err_stop_nxtstate <= _T_2516 @[el2_ifu_mem_ctl.scala 533:25] + node _T_2517 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_i0_commit_cmt) @[el2_ifu_mem_ctl.scala 535:54] + node _T_2518 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_mem_ctl.scala 535:99] + node _T_2519 = or(_T_2517, _T_2518) @[el2_ifu_mem_ctl.scala 535:81] + node _T_2520 = or(_T_2519, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 535:103] + err_stop_state_en <= _T_2520 @[el2_ifu_mem_ctl.scala 535:25] + node _T_2521 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_mem_ctl.scala 536:41] + node _T_2522 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 536:47] + node _T_2523 = and(_T_2521, _T_2522) @[el2_ifu_mem_ctl.scala 536:45] + node _T_2524 = eq(io.dec_tlu_i0_commit_cmt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 536:69] + node _T_2525 = and(_T_2523, _T_2524) @[el2_ifu_mem_ctl.scala 536:67] + err_stop_fetch <= _T_2525 @[el2_ifu_mem_ctl.scala 536:22] + io.iccm_correction_state <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 537:32] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2526 = eq(UInt<2>("h03"), err_stop_state) @[Conditional.scala 37:30] + when _T_2526 : @[Conditional.scala 39:67] + node _T_2527 = eq(io.dec_tlu_flush_err_wb, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 540:62] + node _T_2528 = and(io.dec_tlu_flush_lower_wb, _T_2527) @[el2_ifu_mem_ctl.scala 540:60] + node _T_2529 = or(_T_2528, io.dec_tlu_i0_commit_cmt) @[el2_ifu_mem_ctl.scala 540:88] + node _T_2530 = or(_T_2529, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 540:115] + node _T_2531 = bits(_T_2530, 0, 0) @[el2_ifu_mem_ctl.scala 540:140] + node _T_2532 = bits(io.dec_tlu_flush_err_wb, 0, 0) @[el2_ifu_mem_ctl.scala 541:60] + node _T_2533 = mux(_T_2532, UInt<2>("h01"), UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 541:29] + node _T_2534 = mux(_T_2531, UInt<2>("h00"), _T_2533) @[el2_ifu_mem_ctl.scala 540:31] + err_stop_nxtstate <= _T_2534 @[el2_ifu_mem_ctl.scala 540:25] + node _T_2535 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_i0_commit_cmt) @[el2_ifu_mem_ctl.scala 542:54] + node _T_2536 = or(_T_2535, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 542:81] + err_stop_state_en <= _T_2536 @[el2_ifu_mem_ctl.scala 542:25] + err_stop_fetch <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 543:22] + io.iccm_correction_state <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 544:32] + skip @[Conditional.scala 39:67] + reg _T_2537 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when err_stop_state_en : @[Reg.scala 28:19] + _T_2537 <= err_stop_nxtstate @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + err_stop_state <= _T_2537 @[el2_ifu_mem_ctl.scala 547:18] + bus_ifu_bus_clk_en <= io.ifu_bus_clk_en @[el2_ifu_mem_ctl.scala 548:22] + inst rvclkhdr_68 of rvclkhdr_68 @[el2_lib.scala 483:22] + rvclkhdr_68.clock <= clock + rvclkhdr_68.reset <= reset + rvclkhdr_68.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_68.io.en <= bus_ifu_bus_clk_en @[el2_lib.scala 485:16] + rvclkhdr_68.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + node _T_2538 = or(bus_ifu_bus_clk_en, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 550:57] + inst rvclkhdr_69 of rvclkhdr_69 @[el2_lib.scala 483:22] + rvclkhdr_69.clock <= clock + rvclkhdr_69.reset <= reset + rvclkhdr_69.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_69.io.en <= _T_2538 @[el2_lib.scala 485:16] + rvclkhdr_69.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + reg bus_ifu_bus_clk_en_ff : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 551:61] + bus_ifu_bus_clk_en_ff <= bus_ifu_bus_clk_en @[el2_ifu_mem_ctl.scala 551:61] + reg _T_2539 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 552:52] + _T_2539 <= scnd_miss_req_in @[el2_ifu_mem_ctl.scala 552:52] + scnd_miss_req_q <= _T_2539 @[el2_ifu_mem_ctl.scala 552:19] + reg scnd_miss_req_ff2 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 553:57] + scnd_miss_req_ff2 <= scnd_miss_req @[el2_ifu_mem_ctl.scala 553:57] + node _T_2540 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 554:39] + node _T_2541 = and(scnd_miss_req_q, _T_2540) @[el2_ifu_mem_ctl.scala 554:36] + scnd_miss_req <= _T_2541 @[el2_ifu_mem_ctl.scala 554:17] + wire bus_cmd_req_hold : UInt<1> + bus_cmd_req_hold <= UInt<1>("h00") + wire ifu_bus_cmd_valid : UInt<1> + ifu_bus_cmd_valid <= UInt<1>("h00") + wire bus_cmd_beat_count : UInt<3> + bus_cmd_beat_count <= UInt<1>("h00") + wire ifu_bus_cmd_ready : UInt<1> + ifu_bus_cmd_ready <= UInt<1>("h00") + node _T_2542 = or(ic_act_miss_f, bus_cmd_req_hold) @[el2_ifu_mem_ctl.scala 559:45] + node _T_2543 = or(_T_2542, ifu_bus_cmd_valid) @[el2_ifu_mem_ctl.scala 559:64] + node _T_2544 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 559:87] + node _T_2545 = and(_T_2543, _T_2544) @[el2_ifu_mem_ctl.scala 559:85] + node _T_2546 = mux(UInt<1>("h01"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_2547 = eq(bus_cmd_beat_count, _T_2546) @[el2_ifu_mem_ctl.scala 559:133] + node _T_2548 = and(_T_2547, ifu_bus_cmd_valid) @[el2_ifu_mem_ctl.scala 559:164] + node _T_2549 = and(_T_2548, ifu_bus_cmd_ready) @[el2_ifu_mem_ctl.scala 559:184] + node _T_2550 = and(_T_2549, miss_pending) @[el2_ifu_mem_ctl.scala 559:204] + node _T_2551 = eq(_T_2550, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 559:112] + node ifc_bus_ic_req_ff_in = and(_T_2545, _T_2551) @[el2_ifu_mem_ctl.scala 559:110] + reg _T_2552 : UInt<1>, rvclkhdr_69.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 560:55] + _T_2552 <= ifc_bus_ic_req_ff_in @[el2_ifu_mem_ctl.scala 560:55] + ifu_bus_cmd_valid <= _T_2552 @[el2_ifu_mem_ctl.scala 560:21] + wire bus_cmd_sent : UInt<1> + bus_cmd_sent <= UInt<1>("h00") + node _T_2553 = or(ic_act_miss_f, bus_cmd_req_hold) @[el2_ifu_mem_ctl.scala 562:39] + node _T_2554 = eq(bus_cmd_sent, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 562:61] + node _T_2555 = and(_T_2553, _T_2554) @[el2_ifu_mem_ctl.scala 562:59] + node _T_2556 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 562:77] + node bus_cmd_req_in = and(_T_2555, _T_2556) @[el2_ifu_mem_ctl.scala 562:75] + reg _T_2557 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 563:53] + _T_2557 <= bus_cmd_req_in @[el2_ifu_mem_ctl.scala 563:53] + bus_cmd_req_hold <= _T_2557 @[el2_ifu_mem_ctl.scala 563:20] + io.ifu_axi_arvalid <= ifu_bus_cmd_valid @[el2_ifu_mem_ctl.scala 565:22] + node _T_2558 = bits(ifu_bus_cmd_valid, 0, 0) @[Bitwise.scala 72:15] + node _T_2559 = mux(_T_2558, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_2560 = and(bus_rd_addr_count, _T_2559) @[el2_ifu_mem_ctl.scala 566:40] + io.ifu_axi_arid <= _T_2560 @[el2_ifu_mem_ctl.scala 566:19] + node _T_2561 = cat(ifu_ic_req_addr_f, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2562 = bits(ifu_bus_cmd_valid, 0, 0) @[Bitwise.scala 72:15] + node _T_2563 = mux(_T_2562, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_2564 = and(_T_2561, _T_2563) @[el2_ifu_mem_ctl.scala 567:57] + io.ifu_axi_araddr <= _T_2564 @[el2_ifu_mem_ctl.scala 567:21] + io.ifu_axi_arsize <= UInt<3>("h03") @[el2_ifu_mem_ctl.scala 568:21] + io.ifu_axi_arcache <= UInt<4>("h0f") @[el2_ifu_mem_ctl.scala 569:22] + node _T_2565 = bits(ifu_ic_req_addr_f, 28, 25) @[el2_ifu_mem_ctl.scala 570:43] + io.ifu_axi_arregion <= _T_2565 @[el2_ifu_mem_ctl.scala 570:23] + io.ifu_axi_arburst <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 571:22] + io.ifu_axi_rready <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 572:21] + reg ifu_bus_arready_unq_ff : UInt<1>, rvclkhdr_68.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 578:57] + ifu_bus_arready_unq_ff <= io.ifu_axi_arready @[el2_ifu_mem_ctl.scala 578:57] + reg ifu_bus_rvalid_unq_ff : UInt<1>, rvclkhdr_68.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 579:56] + ifu_bus_rvalid_unq_ff <= io.ifu_axi_rvalid @[el2_ifu_mem_ctl.scala 579:56] + reg ifu_bus_arvalid_ff : UInt<1>, rvclkhdr_68.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 580:53] + ifu_bus_arvalid_ff <= io.ifu_axi_arvalid @[el2_ifu_mem_ctl.scala 580:53] + reg ifu_bus_rresp_ff : UInt, rvclkhdr_68.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 581:51] + ifu_bus_rresp_ff <= io.ifu_axi_rresp @[el2_ifu_mem_ctl.scala 581:51] + reg _T_2566 : UInt, rvclkhdr_68.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 582:48] + _T_2566 <= io.ifu_axi_rdata @[el2_ifu_mem_ctl.scala 582:48] + ifu_bus_rdata_ff <= _T_2566 @[el2_ifu_mem_ctl.scala 582:20] + reg _T_2567 : UInt, rvclkhdr_68.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 583:46] + _T_2567 <= io.ifu_axi_rid @[el2_ifu_mem_ctl.scala 583:46] + ifu_bus_rid_ff <= _T_2567 @[el2_ifu_mem_ctl.scala 583:18] + ifu_bus_cmd_ready <= io.ifu_axi_arready @[el2_ifu_mem_ctl.scala 584:21] + ifu_bus_rsp_valid <= io.ifu_axi_rvalid @[el2_ifu_mem_ctl.scala 585:21] + ifu_bus_rsp_ready <= io.ifu_axi_rready @[el2_ifu_mem_ctl.scala 586:21] + ifu_bus_rsp_tag <= io.ifu_axi_rid @[el2_ifu_mem_ctl.scala 587:19] + ic_miss_buff_data_in <= io.ifu_axi_rdata @[el2_ifu_mem_ctl.scala 588:21] + node ifu_bus_rvalid = and(ifu_bus_rsp_valid, bus_ifu_bus_clk_en) @[el2_ifu_mem_ctl.scala 590:42] + node ifu_bus_arready = and(io.ifu_axi_arready, bus_ifu_bus_clk_en) @[el2_ifu_mem_ctl.scala 591:45] + node ifu_bus_arready_ff = and(ifu_bus_arready_unq_ff, bus_ifu_bus_clk_en_ff) @[el2_ifu_mem_ctl.scala 592:51] + node ifu_bus_rvalid_ff = and(ifu_bus_rvalid_unq_ff, bus_ifu_bus_clk_en_ff) @[el2_ifu_mem_ctl.scala 593:49] + node _T_2568 = and(io.ifu_axi_arvalid, ifu_bus_arready) @[el2_ifu_mem_ctl.scala 594:35] + node _T_2569 = and(_T_2568, miss_pending) @[el2_ifu_mem_ctl.scala 594:53] + node _T_2570 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 594:70] + node _T_2571 = and(_T_2569, _T_2570) @[el2_ifu_mem_ctl.scala 594:68] + bus_cmd_sent <= _T_2571 @[el2_ifu_mem_ctl.scala 594:16] + wire bus_last_data_beat : UInt<1> + bus_last_data_beat <= UInt<1>("h00") + node _T_2572 = eq(bus_last_data_beat, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 596:50] + node _T_2573 = and(bus_ifu_wr_en_ff, _T_2572) @[el2_ifu_mem_ctl.scala 596:48] + node _T_2574 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 596:72] + node bus_inc_data_beat_cnt = and(_T_2573, _T_2574) @[el2_ifu_mem_ctl.scala 596:70] + node _T_2575 = and(bus_ifu_wr_en_ff, bus_last_data_beat) @[el2_ifu_mem_ctl.scala 597:68] + node _T_2576 = or(ic_act_miss_f, _T_2575) @[el2_ifu_mem_ctl.scala 597:48] + node bus_reset_data_beat_cnt = or(_T_2576, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 597:91] + node _T_2577 = eq(bus_inc_data_beat_cnt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 598:32] + node _T_2578 = eq(bus_reset_data_beat_cnt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 598:57] + node bus_hold_data_beat_cnt = and(_T_2577, _T_2578) @[el2_ifu_mem_ctl.scala 598:55] + wire bus_data_beat_count : UInt<3> + bus_data_beat_count <= UInt<1>("h00") + node _T_2579 = add(bus_data_beat_count, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 600:115] + node _T_2580 = tail(_T_2579, 1) @[el2_ifu_mem_ctl.scala 600:115] + node _T_2581 = mux(bus_reset_data_beat_cnt, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2582 = mux(bus_inc_data_beat_cnt, _T_2580, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2583 = mux(bus_hold_data_beat_cnt, bus_data_beat_count, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2584 = or(_T_2581, _T_2582) @[Mux.scala 27:72] + node _T_2585 = or(_T_2584, _T_2583) @[Mux.scala 27:72] + wire _T_2586 : UInt<3> @[Mux.scala 27:72] + _T_2586 <= _T_2585 @[Mux.scala 27:72] + bus_new_data_beat_count <= _T_2586 @[el2_ifu_mem_ctl.scala 600:27] + reg _T_2587 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 601:56] + _T_2587 <= bus_new_data_beat_count @[el2_ifu_mem_ctl.scala 601:56] + bus_data_beat_count <= _T_2587 @[el2_ifu_mem_ctl.scala 601:23] + node _T_2588 = and(bus_ifu_wr_en_ff, bus_last_data_beat) @[el2_ifu_mem_ctl.scala 602:49] + node _T_2589 = eq(scnd_miss_req, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 602:73] + node _T_2590 = and(_T_2588, _T_2589) @[el2_ifu_mem_ctl.scala 602:71] + node _T_2591 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 602:116] + node _T_2592 = and(last_data_recieved_ff, _T_2591) @[el2_ifu_mem_ctl.scala 602:114] + node last_data_recieved_in = or(_T_2590, _T_2592) @[el2_ifu_mem_ctl.scala 602:89] + reg _T_2593 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 603:58] + _T_2593 <= last_data_recieved_in @[el2_ifu_mem_ctl.scala 603:58] + last_data_recieved_ff <= _T_2593 @[el2_ifu_mem_ctl.scala 603:25] + node _T_2594 = eq(miss_pending, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 605:35] + node _T_2595 = bits(imb_ff, 4, 2) @[el2_ifu_mem_ctl.scala 605:56] + node _T_2596 = bits(imb_scnd_ff, 4, 2) @[el2_ifu_mem_ctl.scala 606:37] + node _T_2597 = add(bus_rd_addr_count, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 607:43] + node _T_2598 = tail(_T_2597, 1) @[el2_ifu_mem_ctl.scala 607:43] + node _T_2599 = mux(bus_cmd_sent, _T_2598, bus_rd_addr_count) @[el2_ifu_mem_ctl.scala 607:10] + node _T_2600 = mux(scnd_miss_req_q, _T_2596, _T_2599) @[el2_ifu_mem_ctl.scala 606:8] + node bus_new_rd_addr_count = mux(_T_2594, _T_2595, _T_2600) @[el2_ifu_mem_ctl.scala 605:34] + reg _T_2601 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 608:55] + _T_2601 <= bus_new_rd_addr_count @[el2_ifu_mem_ctl.scala 608:55] + bus_rd_addr_count <= _T_2601 @[el2_ifu_mem_ctl.scala 608:21] + node _T_2602 = and(ifu_bus_cmd_valid, ifu_bus_cmd_ready) @[el2_ifu_mem_ctl.scala 610:48] + node _T_2603 = and(_T_2602, miss_pending) @[el2_ifu_mem_ctl.scala 610:68] + node _T_2604 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 610:85] + node bus_inc_cmd_beat_cnt = and(_T_2603, _T_2604) @[el2_ifu_mem_ctl.scala 610:83] + node _T_2605 = eq(uncacheable_miss_in, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 611:51] + node _T_2606 = and(ic_act_miss_f, _T_2605) @[el2_ifu_mem_ctl.scala 611:49] + node bus_reset_cmd_beat_cnt_0 = or(_T_2606, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 611:73] + node bus_reset_cmd_beat_cnt_secondlast = and(ic_act_miss_f, uncacheable_miss_in) @[el2_ifu_mem_ctl.scala 612:57] + node _T_2607 = eq(bus_inc_cmd_beat_cnt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 613:31] + node _T_2608 = or(ic_act_miss_f, scnd_miss_req) @[el2_ifu_mem_ctl.scala 613:71] + node _T_2609 = or(_T_2608, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 613:87] + node _T_2610 = eq(_T_2609, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 613:55] + node bus_hold_cmd_beat_cnt = and(_T_2607, _T_2610) @[el2_ifu_mem_ctl.scala 613:53] + node _T_2611 = or(bus_inc_cmd_beat_cnt, ic_act_miss_f) @[el2_ifu_mem_ctl.scala 614:46] + node bus_cmd_beat_en = or(_T_2611, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 614:62] + node _T_2612 = bits(bus_reset_cmd_beat_cnt_secondlast, 0, 0) @[el2_ifu_mem_ctl.scala 615:107] + node _T_2613 = add(bus_cmd_beat_count, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 616:46] + node _T_2614 = tail(_T_2613, 1) @[el2_ifu_mem_ctl.scala 616:46] + node _T_2615 = mux(bus_reset_cmd_beat_cnt_0, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2616 = mux(_T_2612, UInt<3>("h06"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2617 = mux(bus_inc_cmd_beat_cnt, _T_2614, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2618 = mux(bus_hold_cmd_beat_cnt, bus_cmd_beat_count, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2619 = or(_T_2615, _T_2616) @[Mux.scala 27:72] + node _T_2620 = or(_T_2619, _T_2617) @[Mux.scala 27:72] + node _T_2621 = or(_T_2620, _T_2618) @[Mux.scala 27:72] + wire bus_new_cmd_beat_count : UInt<3> @[Mux.scala 27:72] + bus_new_cmd_beat_count <= _T_2621 @[Mux.scala 27:72] + reg _T_2622 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when bus_cmd_beat_en : @[Reg.scala 28:19] + _T_2622 <= bus_new_cmd_beat_count @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + bus_cmd_beat_count <= _T_2622 @[el2_ifu_mem_ctl.scala 617:22] + node _T_2623 = eq(bus_data_beat_count, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 618:69] + node _T_2624 = andr(bus_data_beat_count) @[el2_ifu_mem_ctl.scala 618:101] + node _T_2625 = mux(uncacheable_miss_ff, _T_2623, _T_2624) @[el2_ifu_mem_ctl.scala 618:28] + bus_last_data_beat <= _T_2625 @[el2_ifu_mem_ctl.scala 618:22] + node _T_2626 = and(ifu_bus_rvalid, miss_pending) @[el2_ifu_mem_ctl.scala 619:35] + bus_ifu_wr_en <= _T_2626 @[el2_ifu_mem_ctl.scala 619:17] + node _T_2627 = and(ifu_bus_rvalid_ff, miss_pending) @[el2_ifu_mem_ctl.scala 620:41] + bus_ifu_wr_en_ff <= _T_2627 @[el2_ifu_mem_ctl.scala 620:20] + node _T_2628 = and(ifu_bus_rvalid_ff, miss_pending) @[el2_ifu_mem_ctl.scala 621:44] + node _T_2629 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 621:61] + node _T_2630 = and(_T_2628, _T_2629) @[el2_ifu_mem_ctl.scala 621:59] + node _T_2631 = orr(ifu_bus_rresp_ff) @[el2_ifu_mem_ctl.scala 621:103] + node _T_2632 = eq(_T_2631, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 621:84] + node _T_2633 = and(_T_2630, _T_2632) @[el2_ifu_mem_ctl.scala 621:82] + node _T_2634 = and(_T_2633, write_ic_16_bytes) @[el2_ifu_mem_ctl.scala 621:108] + bus_ifu_wr_en_ff_q <= _T_2634 @[el2_ifu_mem_ctl.scala 621:22] + node _T_2635 = and(ifu_bus_rvalid_ff, miss_pending) @[el2_ifu_mem_ctl.scala 622:51] + node _T_2636 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 622:68] + node bus_ifu_wr_en_ff_wo_err = and(_T_2635, _T_2636) @[el2_ifu_mem_ctl.scala 622:66] + reg ic_act_miss_f_delayed : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 623:61] + ic_act_miss_f_delayed <= ic_act_miss_f @[el2_ifu_mem_ctl.scala 623:61] + node _T_2637 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 624:66] + node _T_2638 = and(ic_act_miss_f_delayed, _T_2637) @[el2_ifu_mem_ctl.scala 624:53] + node _T_2639 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 624:86] + node _T_2640 = and(_T_2638, _T_2639) @[el2_ifu_mem_ctl.scala 624:84] + reset_tag_valid_for_miss <= _T_2640 @[el2_ifu_mem_ctl.scala 624:28] + node _T_2641 = orr(io.ifu_axi_rresp) @[el2_ifu_mem_ctl.scala 625:47] + node _T_2642 = and(_T_2641, ifu_bus_rvalid) @[el2_ifu_mem_ctl.scala 625:50] + node _T_2643 = and(_T_2642, miss_pending) @[el2_ifu_mem_ctl.scala 625:68] + bus_ifu_wr_data_error <= _T_2643 @[el2_ifu_mem_ctl.scala 625:25] + node _T_2644 = orr(ifu_bus_rresp_ff) @[el2_ifu_mem_ctl.scala 626:48] + node _T_2645 = and(_T_2644, ifu_bus_rvalid_ff) @[el2_ifu_mem_ctl.scala 626:52] + node _T_2646 = and(_T_2645, miss_pending) @[el2_ifu_mem_ctl.scala 626:73] + bus_ifu_wr_data_error_ff <= _T_2646 @[el2_ifu_mem_ctl.scala 626:28] + wire ifc_dma_access_ok_d : UInt<1> + ifc_dma_access_ok_d <= UInt<1>("h00") + reg ifc_dma_access_ok_prev : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 628:62] + ifc_dma_access_ok_prev <= ifc_dma_access_ok_d @[el2_ifu_mem_ctl.scala 628:62] + node _T_2647 = or(ic_crit_wd_rdy_new_in, ic_crit_wd_rdy_new_ff) @[el2_ifu_mem_ctl.scala 629:43] + ic_crit_wd_rdy <= _T_2647 @[el2_ifu_mem_ctl.scala 629:18] + node _T_2648 = and(bus_last_data_beat, bus_ifu_wr_en_ff) @[el2_ifu_mem_ctl.scala 630:35] + last_beat <= _T_2648 @[el2_ifu_mem_ctl.scala 630:13] + reset_beat_cnt <= bus_reset_data_beat_cnt @[el2_ifu_mem_ctl.scala 631:18] + node _T_2649 = eq(iccm_correct_ecc, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 633:50] + node _T_2650 = and(io.ifc_dma_access_ok, _T_2649) @[el2_ifu_mem_ctl.scala 633:47] + node _T_2651 = eq(io.iccm_dma_sb_error, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 633:70] + node _T_2652 = and(_T_2650, _T_2651) @[el2_ifu_mem_ctl.scala 633:68] + ifc_dma_access_ok_d <= _T_2652 @[el2_ifu_mem_ctl.scala 633:23] + node _T_2653 = eq(iccm_correct_ecc, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 634:54] + node _T_2654 = and(io.ifc_dma_access_ok, _T_2653) @[el2_ifu_mem_ctl.scala 634:51] + node _T_2655 = and(_T_2654, ifc_dma_access_ok_prev) @[el2_ifu_mem_ctl.scala 634:72] + node _T_2656 = eq(perr_state, UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 634:111] + node _T_2657 = and(_T_2655, _T_2656) @[el2_ifu_mem_ctl.scala 634:97] + node _T_2658 = eq(io.iccm_dma_sb_error, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 634:129] + node ifc_dma_access_q_ok = and(_T_2657, _T_2658) @[el2_ifu_mem_ctl.scala 634:127] + io.iccm_ready <= ifc_dma_access_q_ok @[el2_ifu_mem_ctl.scala 635:17] + reg _T_2659 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 636:51] + _T_2659 <= io.dma_iccm_req @[el2_ifu_mem_ctl.scala 636:51] + dma_iccm_req_f <= _T_2659 @[el2_ifu_mem_ctl.scala 636:18] + node _T_2660 = and(ifc_dma_access_q_ok, io.dma_iccm_req) @[el2_ifu_mem_ctl.scala 637:40] + node _T_2661 = and(_T_2660, io.dma_mem_write) @[el2_ifu_mem_ctl.scala 637:58] + node _T_2662 = or(_T_2661, iccm_correct_ecc) @[el2_ifu_mem_ctl.scala 637:79] + io.iccm_wren <= _T_2662 @[el2_ifu_mem_ctl.scala 637:16] + node _T_2663 = and(ifc_dma_access_q_ok, io.dma_iccm_req) @[el2_ifu_mem_ctl.scala 638:40] + node _T_2664 = eq(io.dma_mem_write, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 638:60] + node _T_2665 = and(_T_2663, _T_2664) @[el2_ifu_mem_ctl.scala 638:58] + node _T_2666 = and(io.ifc_iccm_access_bf, io.ifc_fetch_req_bf) @[el2_ifu_mem_ctl.scala 638:104] + node _T_2667 = or(_T_2665, _T_2666) @[el2_ifu_mem_ctl.scala 638:79] + io.iccm_rden <= _T_2667 @[el2_ifu_mem_ctl.scala 638:16] + node _T_2668 = and(ifc_dma_access_q_ok, io.dma_iccm_req) @[el2_ifu_mem_ctl.scala 639:43] + node _T_2669 = eq(io.dma_mem_write, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 639:63] + node iccm_dma_rden = and(_T_2668, _T_2669) @[el2_ifu_mem_ctl.scala 639:61] + node _T_2670 = bits(io.dma_iccm_req, 0, 0) @[Bitwise.scala 72:15] + node _T_2671 = mux(_T_2670, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_2672 = and(_T_2671, io.dma_mem_sz) @[el2_ifu_mem_ctl.scala 640:47] + io.iccm_wr_size <= _T_2672 @[el2_ifu_mem_ctl.scala 640:19] + node _T_2673 = bits(io.dma_mem_wdata, 63, 32) @[el2_ifu_mem_ctl.scala 642:54] + node _T_2674 = bits(_T_2673, 0, 0) @[el2_lib.scala 259:58] + node _T_2675 = bits(_T_2673, 1, 1) @[el2_lib.scala 259:58] + node _T_2676 = bits(_T_2673, 3, 3) @[el2_lib.scala 259:58] + node _T_2677 = bits(_T_2673, 4, 4) @[el2_lib.scala 259:58] + node _T_2678 = bits(_T_2673, 6, 6) @[el2_lib.scala 259:58] + node _T_2679 = bits(_T_2673, 8, 8) @[el2_lib.scala 259:58] + node _T_2680 = bits(_T_2673, 10, 10) @[el2_lib.scala 259:58] + node _T_2681 = bits(_T_2673, 11, 11) @[el2_lib.scala 259:58] + node _T_2682 = bits(_T_2673, 13, 13) @[el2_lib.scala 259:58] + node _T_2683 = bits(_T_2673, 15, 15) @[el2_lib.scala 259:58] + node _T_2684 = bits(_T_2673, 17, 17) @[el2_lib.scala 259:58] + node _T_2685 = bits(_T_2673, 19, 19) @[el2_lib.scala 259:58] + node _T_2686 = bits(_T_2673, 21, 21) @[el2_lib.scala 259:58] + node _T_2687 = bits(_T_2673, 23, 23) @[el2_lib.scala 259:58] + node _T_2688 = bits(_T_2673, 25, 25) @[el2_lib.scala 259:58] + node _T_2689 = bits(_T_2673, 26, 26) @[el2_lib.scala 259:58] + node _T_2690 = bits(_T_2673, 28, 28) @[el2_lib.scala 259:58] + node _T_2691 = bits(_T_2673, 30, 30) @[el2_lib.scala 259:58] + node _T_2692 = xor(_T_2674, _T_2675) @[el2_lib.scala 259:74] + node _T_2693 = xor(_T_2692, _T_2676) @[el2_lib.scala 259:74] + node _T_2694 = xor(_T_2693, _T_2677) @[el2_lib.scala 259:74] + node _T_2695 = xor(_T_2694, _T_2678) @[el2_lib.scala 259:74] + node _T_2696 = xor(_T_2695, _T_2679) @[el2_lib.scala 259:74] + node _T_2697 = xor(_T_2696, _T_2680) @[el2_lib.scala 259:74] + node _T_2698 = xor(_T_2697, _T_2681) @[el2_lib.scala 259:74] + node _T_2699 = xor(_T_2698, _T_2682) @[el2_lib.scala 259:74] + node _T_2700 = xor(_T_2699, _T_2683) @[el2_lib.scala 259:74] + node _T_2701 = xor(_T_2700, _T_2684) @[el2_lib.scala 259:74] + node _T_2702 = xor(_T_2701, _T_2685) @[el2_lib.scala 259:74] + node _T_2703 = xor(_T_2702, _T_2686) @[el2_lib.scala 259:74] + node _T_2704 = xor(_T_2703, _T_2687) @[el2_lib.scala 259:74] + node _T_2705 = xor(_T_2704, _T_2688) @[el2_lib.scala 259:74] + node _T_2706 = xor(_T_2705, _T_2689) @[el2_lib.scala 259:74] + node _T_2707 = xor(_T_2706, _T_2690) @[el2_lib.scala 259:74] + node _T_2708 = xor(_T_2707, _T_2691) @[el2_lib.scala 259:74] + node _T_2709 = bits(_T_2673, 0, 0) @[el2_lib.scala 259:58] + node _T_2710 = bits(_T_2673, 2, 2) @[el2_lib.scala 259:58] + node _T_2711 = bits(_T_2673, 3, 3) @[el2_lib.scala 259:58] + node _T_2712 = bits(_T_2673, 5, 5) @[el2_lib.scala 259:58] + node _T_2713 = bits(_T_2673, 6, 6) @[el2_lib.scala 259:58] + node _T_2714 = bits(_T_2673, 9, 9) @[el2_lib.scala 259:58] + node _T_2715 = bits(_T_2673, 10, 10) @[el2_lib.scala 259:58] + node _T_2716 = bits(_T_2673, 12, 12) @[el2_lib.scala 259:58] + node _T_2717 = bits(_T_2673, 13, 13) @[el2_lib.scala 259:58] + node _T_2718 = bits(_T_2673, 16, 16) @[el2_lib.scala 259:58] + node _T_2719 = bits(_T_2673, 17, 17) @[el2_lib.scala 259:58] + node _T_2720 = bits(_T_2673, 20, 20) @[el2_lib.scala 259:58] + node _T_2721 = bits(_T_2673, 21, 21) @[el2_lib.scala 259:58] + node _T_2722 = bits(_T_2673, 24, 24) @[el2_lib.scala 259:58] + node _T_2723 = bits(_T_2673, 25, 25) @[el2_lib.scala 259:58] + node _T_2724 = bits(_T_2673, 27, 27) @[el2_lib.scala 259:58] + node _T_2725 = bits(_T_2673, 28, 28) @[el2_lib.scala 259:58] + node _T_2726 = bits(_T_2673, 31, 31) @[el2_lib.scala 259:58] + node _T_2727 = xor(_T_2709, _T_2710) @[el2_lib.scala 259:74] + node _T_2728 = xor(_T_2727, _T_2711) @[el2_lib.scala 259:74] + node _T_2729 = xor(_T_2728, _T_2712) @[el2_lib.scala 259:74] + node _T_2730 = xor(_T_2729, _T_2713) @[el2_lib.scala 259:74] + node _T_2731 = xor(_T_2730, _T_2714) @[el2_lib.scala 259:74] + node _T_2732 = xor(_T_2731, _T_2715) @[el2_lib.scala 259:74] + node _T_2733 = xor(_T_2732, _T_2716) @[el2_lib.scala 259:74] + node _T_2734 = xor(_T_2733, _T_2717) @[el2_lib.scala 259:74] + node _T_2735 = xor(_T_2734, _T_2718) @[el2_lib.scala 259:74] + node _T_2736 = xor(_T_2735, _T_2719) @[el2_lib.scala 259:74] + node _T_2737 = xor(_T_2736, _T_2720) @[el2_lib.scala 259:74] + node _T_2738 = xor(_T_2737, _T_2721) @[el2_lib.scala 259:74] + node _T_2739 = xor(_T_2738, _T_2722) @[el2_lib.scala 259:74] + node _T_2740 = xor(_T_2739, _T_2723) @[el2_lib.scala 259:74] + node _T_2741 = xor(_T_2740, _T_2724) @[el2_lib.scala 259:74] + node _T_2742 = xor(_T_2741, _T_2725) @[el2_lib.scala 259:74] + node _T_2743 = xor(_T_2742, _T_2726) @[el2_lib.scala 259:74] + node _T_2744 = bits(_T_2673, 1, 1) @[el2_lib.scala 259:58] + node _T_2745 = bits(_T_2673, 2, 2) @[el2_lib.scala 259:58] + node _T_2746 = bits(_T_2673, 3, 3) @[el2_lib.scala 259:58] + node _T_2747 = bits(_T_2673, 7, 7) @[el2_lib.scala 259:58] + node _T_2748 = bits(_T_2673, 8, 8) @[el2_lib.scala 259:58] + node _T_2749 = bits(_T_2673, 9, 9) @[el2_lib.scala 259:58] + node _T_2750 = bits(_T_2673, 10, 10) @[el2_lib.scala 259:58] + node _T_2751 = bits(_T_2673, 14, 14) @[el2_lib.scala 259:58] + node _T_2752 = bits(_T_2673, 15, 15) @[el2_lib.scala 259:58] + node _T_2753 = bits(_T_2673, 16, 16) @[el2_lib.scala 259:58] + node _T_2754 = bits(_T_2673, 17, 17) @[el2_lib.scala 259:58] + node _T_2755 = bits(_T_2673, 22, 22) @[el2_lib.scala 259:58] + node _T_2756 = bits(_T_2673, 23, 23) @[el2_lib.scala 259:58] + node _T_2757 = bits(_T_2673, 24, 24) @[el2_lib.scala 259:58] + node _T_2758 = bits(_T_2673, 25, 25) @[el2_lib.scala 259:58] + node _T_2759 = bits(_T_2673, 29, 29) @[el2_lib.scala 259:58] + node _T_2760 = bits(_T_2673, 30, 30) @[el2_lib.scala 259:58] + node _T_2761 = bits(_T_2673, 31, 31) @[el2_lib.scala 259:58] + node _T_2762 = xor(_T_2744, _T_2745) @[el2_lib.scala 259:74] + node _T_2763 = xor(_T_2762, _T_2746) @[el2_lib.scala 259:74] + node _T_2764 = xor(_T_2763, _T_2747) @[el2_lib.scala 259:74] + node _T_2765 = xor(_T_2764, _T_2748) @[el2_lib.scala 259:74] + node _T_2766 = xor(_T_2765, _T_2749) @[el2_lib.scala 259:74] + node _T_2767 = xor(_T_2766, _T_2750) @[el2_lib.scala 259:74] + node _T_2768 = xor(_T_2767, _T_2751) @[el2_lib.scala 259:74] + node _T_2769 = xor(_T_2768, _T_2752) @[el2_lib.scala 259:74] + node _T_2770 = xor(_T_2769, _T_2753) @[el2_lib.scala 259:74] + node _T_2771 = xor(_T_2770, _T_2754) @[el2_lib.scala 259:74] + node _T_2772 = xor(_T_2771, _T_2755) @[el2_lib.scala 259:74] + node _T_2773 = xor(_T_2772, _T_2756) @[el2_lib.scala 259:74] + node _T_2774 = xor(_T_2773, _T_2757) @[el2_lib.scala 259:74] + node _T_2775 = xor(_T_2774, _T_2758) @[el2_lib.scala 259:74] + node _T_2776 = xor(_T_2775, _T_2759) @[el2_lib.scala 259:74] + node _T_2777 = xor(_T_2776, _T_2760) @[el2_lib.scala 259:74] + node _T_2778 = xor(_T_2777, _T_2761) @[el2_lib.scala 259:74] + node _T_2779 = bits(_T_2673, 4, 4) @[el2_lib.scala 259:58] + node _T_2780 = bits(_T_2673, 5, 5) @[el2_lib.scala 259:58] + node _T_2781 = bits(_T_2673, 6, 6) @[el2_lib.scala 259:58] + node _T_2782 = bits(_T_2673, 7, 7) @[el2_lib.scala 259:58] + node _T_2783 = bits(_T_2673, 8, 8) @[el2_lib.scala 259:58] + node _T_2784 = bits(_T_2673, 9, 9) @[el2_lib.scala 259:58] + node _T_2785 = bits(_T_2673, 10, 10) @[el2_lib.scala 259:58] + node _T_2786 = bits(_T_2673, 18, 18) @[el2_lib.scala 259:58] + node _T_2787 = bits(_T_2673, 19, 19) @[el2_lib.scala 259:58] + node _T_2788 = bits(_T_2673, 20, 20) @[el2_lib.scala 259:58] + node _T_2789 = bits(_T_2673, 21, 21) @[el2_lib.scala 259:58] + node _T_2790 = bits(_T_2673, 22, 22) @[el2_lib.scala 259:58] + node _T_2791 = bits(_T_2673, 23, 23) @[el2_lib.scala 259:58] + node _T_2792 = bits(_T_2673, 24, 24) @[el2_lib.scala 259:58] + node _T_2793 = bits(_T_2673, 25, 25) @[el2_lib.scala 259:58] + node _T_2794 = xor(_T_2779, _T_2780) @[el2_lib.scala 259:74] + node _T_2795 = xor(_T_2794, _T_2781) @[el2_lib.scala 259:74] + node _T_2796 = xor(_T_2795, _T_2782) @[el2_lib.scala 259:74] + node _T_2797 = xor(_T_2796, _T_2783) @[el2_lib.scala 259:74] + node _T_2798 = xor(_T_2797, _T_2784) @[el2_lib.scala 259:74] + node _T_2799 = xor(_T_2798, _T_2785) @[el2_lib.scala 259:74] + node _T_2800 = xor(_T_2799, _T_2786) @[el2_lib.scala 259:74] + node _T_2801 = xor(_T_2800, _T_2787) @[el2_lib.scala 259:74] + node _T_2802 = xor(_T_2801, _T_2788) @[el2_lib.scala 259:74] + node _T_2803 = xor(_T_2802, _T_2789) @[el2_lib.scala 259:74] + node _T_2804 = xor(_T_2803, _T_2790) @[el2_lib.scala 259:74] + node _T_2805 = xor(_T_2804, _T_2791) @[el2_lib.scala 259:74] + node _T_2806 = xor(_T_2805, _T_2792) @[el2_lib.scala 259:74] + node _T_2807 = xor(_T_2806, _T_2793) @[el2_lib.scala 259:74] + node _T_2808 = bits(_T_2673, 11, 11) @[el2_lib.scala 259:58] + node _T_2809 = bits(_T_2673, 12, 12) @[el2_lib.scala 259:58] + node _T_2810 = bits(_T_2673, 13, 13) @[el2_lib.scala 259:58] + node _T_2811 = bits(_T_2673, 14, 14) @[el2_lib.scala 259:58] + node _T_2812 = bits(_T_2673, 15, 15) @[el2_lib.scala 259:58] + node _T_2813 = bits(_T_2673, 16, 16) @[el2_lib.scala 259:58] + node _T_2814 = bits(_T_2673, 17, 17) @[el2_lib.scala 259:58] + node _T_2815 = bits(_T_2673, 18, 18) @[el2_lib.scala 259:58] + node _T_2816 = bits(_T_2673, 19, 19) @[el2_lib.scala 259:58] + node _T_2817 = bits(_T_2673, 20, 20) @[el2_lib.scala 259:58] + node _T_2818 = bits(_T_2673, 21, 21) @[el2_lib.scala 259:58] + node _T_2819 = bits(_T_2673, 22, 22) @[el2_lib.scala 259:58] + node _T_2820 = bits(_T_2673, 23, 23) @[el2_lib.scala 259:58] + node _T_2821 = bits(_T_2673, 24, 24) @[el2_lib.scala 259:58] + node _T_2822 = bits(_T_2673, 25, 25) @[el2_lib.scala 259:58] + node _T_2823 = xor(_T_2808, _T_2809) @[el2_lib.scala 259:74] + node _T_2824 = xor(_T_2823, _T_2810) @[el2_lib.scala 259:74] + node _T_2825 = xor(_T_2824, _T_2811) @[el2_lib.scala 259:74] + node _T_2826 = xor(_T_2825, _T_2812) @[el2_lib.scala 259:74] + node _T_2827 = xor(_T_2826, _T_2813) @[el2_lib.scala 259:74] + node _T_2828 = xor(_T_2827, _T_2814) @[el2_lib.scala 259:74] + node _T_2829 = xor(_T_2828, _T_2815) @[el2_lib.scala 259:74] + node _T_2830 = xor(_T_2829, _T_2816) @[el2_lib.scala 259:74] + node _T_2831 = xor(_T_2830, _T_2817) @[el2_lib.scala 259:74] + node _T_2832 = xor(_T_2831, _T_2818) @[el2_lib.scala 259:74] + node _T_2833 = xor(_T_2832, _T_2819) @[el2_lib.scala 259:74] + node _T_2834 = xor(_T_2833, _T_2820) @[el2_lib.scala 259:74] + node _T_2835 = xor(_T_2834, _T_2821) @[el2_lib.scala 259:74] + node _T_2836 = xor(_T_2835, _T_2822) @[el2_lib.scala 259:74] + node _T_2837 = bits(_T_2673, 26, 26) @[el2_lib.scala 259:58] + node _T_2838 = bits(_T_2673, 27, 27) @[el2_lib.scala 259:58] + node _T_2839 = bits(_T_2673, 28, 28) @[el2_lib.scala 259:58] + node _T_2840 = bits(_T_2673, 29, 29) @[el2_lib.scala 259:58] + node _T_2841 = bits(_T_2673, 30, 30) @[el2_lib.scala 259:58] + node _T_2842 = bits(_T_2673, 31, 31) @[el2_lib.scala 259:58] + node _T_2843 = xor(_T_2837, _T_2838) @[el2_lib.scala 259:74] + node _T_2844 = xor(_T_2843, _T_2839) @[el2_lib.scala 259:74] + node _T_2845 = xor(_T_2844, _T_2840) @[el2_lib.scala 259:74] + node _T_2846 = xor(_T_2845, _T_2841) @[el2_lib.scala 259:74] + node _T_2847 = xor(_T_2846, _T_2842) @[el2_lib.scala 259:74] + node _T_2848 = cat(_T_2778, _T_2743) @[Cat.scala 29:58] + node _T_2849 = cat(_T_2848, _T_2708) @[Cat.scala 29:58] + node _T_2850 = cat(_T_2847, _T_2836) @[Cat.scala 29:58] + node _T_2851 = cat(_T_2850, _T_2807) @[Cat.scala 29:58] + node _T_2852 = cat(_T_2851, _T_2849) @[Cat.scala 29:58] + node _T_2853 = xorr(_T_2673) @[el2_lib.scala 267:13] + node _T_2854 = xorr(_T_2852) @[el2_lib.scala 267:23] + node _T_2855 = xor(_T_2853, _T_2854) @[el2_lib.scala 267:18] + node _T_2856 = cat(_T_2855, _T_2852) @[Cat.scala 29:58] + node _T_2857 = bits(io.dma_mem_wdata, 31, 0) @[el2_ifu_mem_ctl.scala 642:93] + node _T_2858 = bits(_T_2857, 0, 0) @[el2_lib.scala 259:58] + node _T_2859 = bits(_T_2857, 1, 1) @[el2_lib.scala 259:58] + node _T_2860 = bits(_T_2857, 3, 3) @[el2_lib.scala 259:58] + node _T_2861 = bits(_T_2857, 4, 4) @[el2_lib.scala 259:58] + node _T_2862 = bits(_T_2857, 6, 6) @[el2_lib.scala 259:58] + node _T_2863 = bits(_T_2857, 8, 8) @[el2_lib.scala 259:58] + node _T_2864 = bits(_T_2857, 10, 10) @[el2_lib.scala 259:58] + node _T_2865 = bits(_T_2857, 11, 11) @[el2_lib.scala 259:58] + node _T_2866 = bits(_T_2857, 13, 13) @[el2_lib.scala 259:58] + node _T_2867 = bits(_T_2857, 15, 15) @[el2_lib.scala 259:58] + node _T_2868 = bits(_T_2857, 17, 17) @[el2_lib.scala 259:58] + node _T_2869 = bits(_T_2857, 19, 19) @[el2_lib.scala 259:58] + node _T_2870 = bits(_T_2857, 21, 21) @[el2_lib.scala 259:58] + node _T_2871 = bits(_T_2857, 23, 23) @[el2_lib.scala 259:58] + node _T_2872 = bits(_T_2857, 25, 25) @[el2_lib.scala 259:58] + node _T_2873 = bits(_T_2857, 26, 26) @[el2_lib.scala 259:58] + node _T_2874 = bits(_T_2857, 28, 28) @[el2_lib.scala 259:58] + node _T_2875 = bits(_T_2857, 30, 30) @[el2_lib.scala 259:58] + node _T_2876 = xor(_T_2858, _T_2859) @[el2_lib.scala 259:74] + node _T_2877 = xor(_T_2876, _T_2860) @[el2_lib.scala 259:74] + node _T_2878 = xor(_T_2877, _T_2861) @[el2_lib.scala 259:74] + node _T_2879 = xor(_T_2878, _T_2862) @[el2_lib.scala 259:74] + node _T_2880 = xor(_T_2879, _T_2863) @[el2_lib.scala 259:74] + node _T_2881 = xor(_T_2880, _T_2864) @[el2_lib.scala 259:74] + node _T_2882 = xor(_T_2881, _T_2865) @[el2_lib.scala 259:74] + node _T_2883 = xor(_T_2882, _T_2866) @[el2_lib.scala 259:74] + node _T_2884 = xor(_T_2883, _T_2867) @[el2_lib.scala 259:74] + node _T_2885 = xor(_T_2884, _T_2868) @[el2_lib.scala 259:74] + node _T_2886 = xor(_T_2885, _T_2869) @[el2_lib.scala 259:74] + node _T_2887 = xor(_T_2886, _T_2870) @[el2_lib.scala 259:74] + node _T_2888 = xor(_T_2887, _T_2871) @[el2_lib.scala 259:74] + node _T_2889 = xor(_T_2888, _T_2872) @[el2_lib.scala 259:74] + node _T_2890 = xor(_T_2889, _T_2873) @[el2_lib.scala 259:74] + node _T_2891 = xor(_T_2890, _T_2874) @[el2_lib.scala 259:74] + node _T_2892 = xor(_T_2891, _T_2875) @[el2_lib.scala 259:74] + node _T_2893 = bits(_T_2857, 0, 0) @[el2_lib.scala 259:58] + node _T_2894 = bits(_T_2857, 2, 2) @[el2_lib.scala 259:58] + node _T_2895 = bits(_T_2857, 3, 3) @[el2_lib.scala 259:58] + node _T_2896 = bits(_T_2857, 5, 5) @[el2_lib.scala 259:58] + node _T_2897 = bits(_T_2857, 6, 6) @[el2_lib.scala 259:58] + node _T_2898 = bits(_T_2857, 9, 9) @[el2_lib.scala 259:58] + node _T_2899 = bits(_T_2857, 10, 10) @[el2_lib.scala 259:58] + node _T_2900 = bits(_T_2857, 12, 12) @[el2_lib.scala 259:58] + node _T_2901 = bits(_T_2857, 13, 13) @[el2_lib.scala 259:58] + node _T_2902 = bits(_T_2857, 16, 16) @[el2_lib.scala 259:58] + node _T_2903 = bits(_T_2857, 17, 17) @[el2_lib.scala 259:58] + node _T_2904 = bits(_T_2857, 20, 20) @[el2_lib.scala 259:58] + node _T_2905 = bits(_T_2857, 21, 21) @[el2_lib.scala 259:58] + node _T_2906 = bits(_T_2857, 24, 24) @[el2_lib.scala 259:58] + node _T_2907 = bits(_T_2857, 25, 25) @[el2_lib.scala 259:58] + node _T_2908 = bits(_T_2857, 27, 27) @[el2_lib.scala 259:58] + node _T_2909 = bits(_T_2857, 28, 28) @[el2_lib.scala 259:58] + node _T_2910 = bits(_T_2857, 31, 31) @[el2_lib.scala 259:58] + node _T_2911 = xor(_T_2893, _T_2894) @[el2_lib.scala 259:74] + node _T_2912 = xor(_T_2911, _T_2895) @[el2_lib.scala 259:74] + node _T_2913 = xor(_T_2912, _T_2896) @[el2_lib.scala 259:74] + node _T_2914 = xor(_T_2913, _T_2897) @[el2_lib.scala 259:74] + node _T_2915 = xor(_T_2914, _T_2898) @[el2_lib.scala 259:74] + node _T_2916 = xor(_T_2915, _T_2899) @[el2_lib.scala 259:74] + node _T_2917 = xor(_T_2916, _T_2900) @[el2_lib.scala 259:74] + node _T_2918 = xor(_T_2917, _T_2901) @[el2_lib.scala 259:74] + node _T_2919 = xor(_T_2918, _T_2902) @[el2_lib.scala 259:74] + node _T_2920 = xor(_T_2919, _T_2903) @[el2_lib.scala 259:74] + node _T_2921 = xor(_T_2920, _T_2904) @[el2_lib.scala 259:74] + node _T_2922 = xor(_T_2921, _T_2905) @[el2_lib.scala 259:74] + node _T_2923 = xor(_T_2922, _T_2906) @[el2_lib.scala 259:74] + node _T_2924 = xor(_T_2923, _T_2907) @[el2_lib.scala 259:74] + node _T_2925 = xor(_T_2924, _T_2908) @[el2_lib.scala 259:74] + node _T_2926 = xor(_T_2925, _T_2909) @[el2_lib.scala 259:74] + node _T_2927 = xor(_T_2926, _T_2910) @[el2_lib.scala 259:74] + node _T_2928 = bits(_T_2857, 1, 1) @[el2_lib.scala 259:58] + node _T_2929 = bits(_T_2857, 2, 2) @[el2_lib.scala 259:58] + node _T_2930 = bits(_T_2857, 3, 3) @[el2_lib.scala 259:58] + node _T_2931 = bits(_T_2857, 7, 7) @[el2_lib.scala 259:58] + node _T_2932 = bits(_T_2857, 8, 8) @[el2_lib.scala 259:58] + node _T_2933 = bits(_T_2857, 9, 9) @[el2_lib.scala 259:58] + node _T_2934 = bits(_T_2857, 10, 10) @[el2_lib.scala 259:58] + node _T_2935 = bits(_T_2857, 14, 14) @[el2_lib.scala 259:58] + node _T_2936 = bits(_T_2857, 15, 15) @[el2_lib.scala 259:58] + node _T_2937 = bits(_T_2857, 16, 16) @[el2_lib.scala 259:58] + node _T_2938 = bits(_T_2857, 17, 17) @[el2_lib.scala 259:58] + node _T_2939 = bits(_T_2857, 22, 22) @[el2_lib.scala 259:58] + node _T_2940 = bits(_T_2857, 23, 23) @[el2_lib.scala 259:58] + node _T_2941 = bits(_T_2857, 24, 24) @[el2_lib.scala 259:58] + node _T_2942 = bits(_T_2857, 25, 25) @[el2_lib.scala 259:58] + node _T_2943 = bits(_T_2857, 29, 29) @[el2_lib.scala 259:58] + node _T_2944 = bits(_T_2857, 30, 30) @[el2_lib.scala 259:58] + node _T_2945 = bits(_T_2857, 31, 31) @[el2_lib.scala 259:58] + node _T_2946 = xor(_T_2928, _T_2929) @[el2_lib.scala 259:74] + node _T_2947 = xor(_T_2946, _T_2930) @[el2_lib.scala 259:74] + node _T_2948 = xor(_T_2947, _T_2931) @[el2_lib.scala 259:74] + node _T_2949 = xor(_T_2948, _T_2932) @[el2_lib.scala 259:74] + node _T_2950 = xor(_T_2949, _T_2933) @[el2_lib.scala 259:74] + node _T_2951 = xor(_T_2950, _T_2934) @[el2_lib.scala 259:74] + node _T_2952 = xor(_T_2951, _T_2935) @[el2_lib.scala 259:74] + node _T_2953 = xor(_T_2952, _T_2936) @[el2_lib.scala 259:74] + node _T_2954 = xor(_T_2953, _T_2937) @[el2_lib.scala 259:74] + node _T_2955 = xor(_T_2954, _T_2938) @[el2_lib.scala 259:74] + node _T_2956 = xor(_T_2955, _T_2939) @[el2_lib.scala 259:74] + node _T_2957 = xor(_T_2956, _T_2940) @[el2_lib.scala 259:74] + node _T_2958 = xor(_T_2957, _T_2941) @[el2_lib.scala 259:74] + node _T_2959 = xor(_T_2958, _T_2942) @[el2_lib.scala 259:74] + node _T_2960 = xor(_T_2959, _T_2943) @[el2_lib.scala 259:74] + node _T_2961 = xor(_T_2960, _T_2944) @[el2_lib.scala 259:74] + node _T_2962 = xor(_T_2961, _T_2945) @[el2_lib.scala 259:74] + node _T_2963 = bits(_T_2857, 4, 4) @[el2_lib.scala 259:58] + node _T_2964 = bits(_T_2857, 5, 5) @[el2_lib.scala 259:58] + node _T_2965 = bits(_T_2857, 6, 6) @[el2_lib.scala 259:58] + node _T_2966 = bits(_T_2857, 7, 7) @[el2_lib.scala 259:58] + node _T_2967 = bits(_T_2857, 8, 8) @[el2_lib.scala 259:58] + node _T_2968 = bits(_T_2857, 9, 9) @[el2_lib.scala 259:58] + node _T_2969 = bits(_T_2857, 10, 10) @[el2_lib.scala 259:58] + node _T_2970 = bits(_T_2857, 18, 18) @[el2_lib.scala 259:58] + node _T_2971 = bits(_T_2857, 19, 19) @[el2_lib.scala 259:58] + node _T_2972 = bits(_T_2857, 20, 20) @[el2_lib.scala 259:58] + node _T_2973 = bits(_T_2857, 21, 21) @[el2_lib.scala 259:58] + node _T_2974 = bits(_T_2857, 22, 22) @[el2_lib.scala 259:58] + node _T_2975 = bits(_T_2857, 23, 23) @[el2_lib.scala 259:58] + node _T_2976 = bits(_T_2857, 24, 24) @[el2_lib.scala 259:58] + node _T_2977 = bits(_T_2857, 25, 25) @[el2_lib.scala 259:58] + node _T_2978 = xor(_T_2963, _T_2964) @[el2_lib.scala 259:74] + node _T_2979 = xor(_T_2978, _T_2965) @[el2_lib.scala 259:74] + node _T_2980 = xor(_T_2979, _T_2966) @[el2_lib.scala 259:74] + node _T_2981 = xor(_T_2980, _T_2967) @[el2_lib.scala 259:74] + node _T_2982 = xor(_T_2981, _T_2968) @[el2_lib.scala 259:74] + node _T_2983 = xor(_T_2982, _T_2969) @[el2_lib.scala 259:74] + node _T_2984 = xor(_T_2983, _T_2970) @[el2_lib.scala 259:74] + node _T_2985 = xor(_T_2984, _T_2971) @[el2_lib.scala 259:74] + node _T_2986 = xor(_T_2985, _T_2972) @[el2_lib.scala 259:74] + node _T_2987 = xor(_T_2986, _T_2973) @[el2_lib.scala 259:74] + node _T_2988 = xor(_T_2987, _T_2974) @[el2_lib.scala 259:74] + node _T_2989 = xor(_T_2988, _T_2975) @[el2_lib.scala 259:74] + node _T_2990 = xor(_T_2989, _T_2976) @[el2_lib.scala 259:74] + node _T_2991 = xor(_T_2990, _T_2977) @[el2_lib.scala 259:74] + node _T_2992 = bits(_T_2857, 11, 11) @[el2_lib.scala 259:58] + node _T_2993 = bits(_T_2857, 12, 12) @[el2_lib.scala 259:58] + node _T_2994 = bits(_T_2857, 13, 13) @[el2_lib.scala 259:58] + node _T_2995 = bits(_T_2857, 14, 14) @[el2_lib.scala 259:58] + node _T_2996 = bits(_T_2857, 15, 15) @[el2_lib.scala 259:58] + node _T_2997 = bits(_T_2857, 16, 16) @[el2_lib.scala 259:58] + node _T_2998 = bits(_T_2857, 17, 17) @[el2_lib.scala 259:58] + node _T_2999 = bits(_T_2857, 18, 18) @[el2_lib.scala 259:58] + node _T_3000 = bits(_T_2857, 19, 19) @[el2_lib.scala 259:58] + node _T_3001 = bits(_T_2857, 20, 20) @[el2_lib.scala 259:58] + node _T_3002 = bits(_T_2857, 21, 21) @[el2_lib.scala 259:58] + node _T_3003 = bits(_T_2857, 22, 22) @[el2_lib.scala 259:58] + node _T_3004 = bits(_T_2857, 23, 23) @[el2_lib.scala 259:58] + node _T_3005 = bits(_T_2857, 24, 24) @[el2_lib.scala 259:58] + node _T_3006 = bits(_T_2857, 25, 25) @[el2_lib.scala 259:58] + node _T_3007 = xor(_T_2992, _T_2993) @[el2_lib.scala 259:74] + node _T_3008 = xor(_T_3007, _T_2994) @[el2_lib.scala 259:74] + node _T_3009 = xor(_T_3008, _T_2995) @[el2_lib.scala 259:74] + node _T_3010 = xor(_T_3009, _T_2996) @[el2_lib.scala 259:74] + node _T_3011 = xor(_T_3010, _T_2997) @[el2_lib.scala 259:74] + node _T_3012 = xor(_T_3011, _T_2998) @[el2_lib.scala 259:74] + node _T_3013 = xor(_T_3012, _T_2999) @[el2_lib.scala 259:74] + node _T_3014 = xor(_T_3013, _T_3000) @[el2_lib.scala 259:74] + node _T_3015 = xor(_T_3014, _T_3001) @[el2_lib.scala 259:74] + node _T_3016 = xor(_T_3015, _T_3002) @[el2_lib.scala 259:74] + node _T_3017 = xor(_T_3016, _T_3003) @[el2_lib.scala 259:74] + node _T_3018 = xor(_T_3017, _T_3004) @[el2_lib.scala 259:74] + node _T_3019 = xor(_T_3018, _T_3005) @[el2_lib.scala 259:74] + node _T_3020 = xor(_T_3019, _T_3006) @[el2_lib.scala 259:74] + node _T_3021 = bits(_T_2857, 26, 26) @[el2_lib.scala 259:58] + node _T_3022 = bits(_T_2857, 27, 27) @[el2_lib.scala 259:58] + node _T_3023 = bits(_T_2857, 28, 28) @[el2_lib.scala 259:58] + node _T_3024 = bits(_T_2857, 29, 29) @[el2_lib.scala 259:58] + node _T_3025 = bits(_T_2857, 30, 30) @[el2_lib.scala 259:58] + node _T_3026 = bits(_T_2857, 31, 31) @[el2_lib.scala 259:58] + node _T_3027 = xor(_T_3021, _T_3022) @[el2_lib.scala 259:74] + node _T_3028 = xor(_T_3027, _T_3023) @[el2_lib.scala 259:74] + node _T_3029 = xor(_T_3028, _T_3024) @[el2_lib.scala 259:74] + node _T_3030 = xor(_T_3029, _T_3025) @[el2_lib.scala 259:74] + node _T_3031 = xor(_T_3030, _T_3026) @[el2_lib.scala 259:74] + node _T_3032 = cat(_T_2962, _T_2927) @[Cat.scala 29:58] + node _T_3033 = cat(_T_3032, _T_2892) @[Cat.scala 29:58] + node _T_3034 = cat(_T_3031, _T_3020) @[Cat.scala 29:58] + node _T_3035 = cat(_T_3034, _T_2991) @[Cat.scala 29:58] + node _T_3036 = cat(_T_3035, _T_3033) @[Cat.scala 29:58] + node _T_3037 = xorr(_T_2857) @[el2_lib.scala 267:13] + node _T_3038 = xorr(_T_3036) @[el2_lib.scala 267:23] + node _T_3039 = xor(_T_3037, _T_3038) @[el2_lib.scala 267:18] + node _T_3040 = cat(_T_3039, _T_3036) @[Cat.scala 29:58] + node dma_mem_ecc = cat(_T_2856, _T_3040) @[Cat.scala 29:58] + wire iccm_ecc_corr_data_ff : UInt<39> + iccm_ecc_corr_data_ff <= UInt<1>("h00") + node _T_3041 = and(ifc_dma_access_q_ok, io.dma_iccm_req) @[el2_ifu_mem_ctl.scala 644:67] + node _T_3042 = eq(_T_3041, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 644:45] + node _T_3043 = and(iccm_correct_ecc, _T_3042) @[el2_ifu_mem_ctl.scala 644:43] + node _T_3044 = cat(iccm_ecc_corr_data_ff, iccm_ecc_corr_data_ff) @[Cat.scala 29:58] + node _T_3045 = bits(dma_mem_ecc, 13, 7) @[el2_ifu_mem_ctl.scala 645:20] + node _T_3046 = bits(io.dma_mem_wdata, 63, 32) @[el2_ifu_mem_ctl.scala 645:43] + node _T_3047 = bits(dma_mem_ecc, 6, 0) @[el2_ifu_mem_ctl.scala 645:63] + node _T_3048 = bits(io.dma_mem_wdata, 31, 0) @[el2_ifu_mem_ctl.scala 645:86] + node _T_3049 = cat(_T_3047, _T_3048) @[Cat.scala 29:58] + node _T_3050 = cat(_T_3045, _T_3046) @[Cat.scala 29:58] + node _T_3051 = cat(_T_3050, _T_3049) @[Cat.scala 29:58] + node _T_3052 = mux(_T_3043, _T_3044, _T_3051) @[el2_ifu_mem_ctl.scala 644:25] + io.iccm_wr_data <= _T_3052 @[el2_ifu_mem_ctl.scala 644:19] + wire iccm_corrected_data : UInt<32>[2] @[el2_ifu_mem_ctl.scala 646:33] + iccm_corrected_data[0] <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 647:26] + iccm_corrected_data[1] <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 648:26] + wire dma_mem_addr_ff : UInt<2> + dma_mem_addr_ff <= UInt<1>("h00") + node _T_3053 = bits(dma_mem_addr_ff, 0, 0) @[el2_ifu_mem_ctl.scala 650:51] + node _T_3054 = bits(_T_3053, 0, 0) @[el2_ifu_mem_ctl.scala 650:55] + node iccm_dma_rdata_1_muxed = mux(_T_3054, iccm_corrected_data[0], iccm_corrected_data[1]) @[el2_ifu_mem_ctl.scala 650:35] + wire iccm_double_ecc_error : UInt<2> + iccm_double_ecc_error <= UInt<1>("h00") + node iccm_dma_ecc_error_in = orr(iccm_double_ecc_error) @[el2_ifu_mem_ctl.scala 652:53] + node _T_3055 = cat(io.dma_mem_addr, io.dma_mem_addr) @[Cat.scala 29:58] + node _T_3056 = cat(iccm_dma_rdata_1_muxed, iccm_corrected_data[0]) @[Cat.scala 29:58] + node iccm_dma_rdata_in = mux(iccm_dma_ecc_error_in, _T_3055, _T_3056) @[el2_ifu_mem_ctl.scala 653:30] + reg dma_mem_tag_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 654:54] + dma_mem_tag_ff <= io.dma_mem_tag @[el2_ifu_mem_ctl.scala 654:54] + reg iccm_dma_rtag_temp : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 655:74] + iccm_dma_rtag_temp <= dma_mem_tag_ff @[el2_ifu_mem_ctl.scala 655:74] + io.iccm_dma_rtag <= iccm_dma_rtag_temp @[el2_ifu_mem_ctl.scala 656:20] + node _T_3057 = bits(io.dma_mem_addr, 3, 2) @[el2_ifu_mem_ctl.scala 658:69] + reg _T_3058 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 658:53] + _T_3058 <= _T_3057 @[el2_ifu_mem_ctl.scala 658:53] + dma_mem_addr_ff <= _T_3058 @[el2_ifu_mem_ctl.scala 658:19] + reg iccm_dma_rvalid_in : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 659:59] + iccm_dma_rvalid_in <= iccm_dma_rden @[el2_ifu_mem_ctl.scala 659:59] + reg iccm_dma_rvalid_temp : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 660:76] + iccm_dma_rvalid_temp <= iccm_dma_rvalid_in @[el2_ifu_mem_ctl.scala 660:76] + io.iccm_dma_rvalid <= iccm_dma_rvalid_temp @[el2_ifu_mem_ctl.scala 661:22] + reg iccm_dma_ecc_error : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 662:74] + iccm_dma_ecc_error <= iccm_dma_ecc_error_in @[el2_ifu_mem_ctl.scala 662:74] + io.iccm_dma_ecc_error <= iccm_dma_ecc_error @[el2_ifu_mem_ctl.scala 663:25] + reg iccm_dma_rdata_temp : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 664:75] + iccm_dma_rdata_temp <= iccm_dma_rdata_in @[el2_ifu_mem_ctl.scala 664:75] + io.iccm_dma_rdata <= iccm_dma_rdata_temp @[el2_ifu_mem_ctl.scala 665:21] + wire iccm_ecc_corr_index_ff : UInt<14> + iccm_ecc_corr_index_ff <= UInt<1>("h00") + node _T_3059 = and(ifc_dma_access_q_ok, io.dma_iccm_req) @[el2_ifu_mem_ctl.scala 667:46] + node _T_3060 = eq(iccm_correct_ecc, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 667:67] + node _T_3061 = and(_T_3059, _T_3060) @[el2_ifu_mem_ctl.scala 667:65] + node _T_3062 = bits(io.dma_mem_addr, 15, 1) @[el2_ifu_mem_ctl.scala 667:101] + node _T_3063 = and(ifc_dma_access_q_ok, io.dma_iccm_req) @[el2_ifu_mem_ctl.scala 668:31] + node _T_3064 = eq(_T_3063, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 668:9] + node _T_3065 = and(_T_3064, iccm_correct_ecc) @[el2_ifu_mem_ctl.scala 668:50] + node _T_3066 = cat(iccm_ecc_corr_index_ff, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_3067 = bits(io.ifc_fetch_addr_bf, 14, 0) @[el2_ifu_mem_ctl.scala 668:124] + node _T_3068 = mux(_T_3065, _T_3066, _T_3067) @[el2_ifu_mem_ctl.scala 668:8] + node _T_3069 = mux(_T_3061, _T_3062, _T_3068) @[el2_ifu_mem_ctl.scala 667:25] + io.iccm_rw_addr <= _T_3069 @[el2_ifu_mem_ctl.scala 667:19] + node ic_fetch_val_int_f = cat(UInt<2>("h00"), io.ic_fetch_val_f) @[Cat.scala 29:58] + node _T_3070 = bits(ifu_fetch_addr_int_f, 0, 0) @[el2_ifu_mem_ctl.scala 670:76] + node ic_fetch_val_shift_right = dshl(ic_fetch_val_int_f, _T_3070) @[el2_ifu_mem_ctl.scala 670:53] + node _T_3071 = bits(ic_fetch_val_shift_right, 1, 0) @[el2_ifu_mem_ctl.scala 673:75] + node _T_3072 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 673:93] + node _T_3073 = and(_T_3071, _T_3072) @[el2_ifu_mem_ctl.scala 673:91] + node _T_3074 = and(_T_3073, fetch_req_iccm_f) @[el2_ifu_mem_ctl.scala 673:113] + node _T_3075 = or(_T_3074, iccm_dma_rvalid_in) @[el2_ifu_mem_ctl.scala 673:130] + node _T_3076 = eq(io.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 673:154] + node _T_3077 = and(_T_3075, _T_3076) @[el2_ifu_mem_ctl.scala 673:152] + node _T_3078 = bits(ic_fetch_val_shift_right, 3, 2) @[el2_ifu_mem_ctl.scala 673:75] + node _T_3079 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 673:93] + node _T_3080 = and(_T_3078, _T_3079) @[el2_ifu_mem_ctl.scala 673:91] + node _T_3081 = and(_T_3080, fetch_req_iccm_f) @[el2_ifu_mem_ctl.scala 673:113] + node _T_3082 = or(_T_3081, iccm_dma_rvalid_in) @[el2_ifu_mem_ctl.scala 673:130] + node _T_3083 = eq(io.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 673:154] + node _T_3084 = and(_T_3082, _T_3083) @[el2_ifu_mem_ctl.scala 673:152] + node iccm_ecc_word_enable = cat(_T_3084, _T_3077) @[Cat.scala 29:58] + node _T_3085 = bits(iccm_ecc_word_enable, 0, 0) @[el2_ifu_mem_ctl.scala 674:73] + node _T_3086 = bits(io.iccm_rd_data_ecc, 31, 0) @[el2_ifu_mem_ctl.scala 674:93] + node _T_3087 = bits(io.iccm_rd_data_ecc, 38, 32) @[el2_ifu_mem_ctl.scala 674:128] + wire _T_3088 : UInt<1>[18] @[el2_lib.scala 313:18] + wire _T_3089 : UInt<1>[18] @[el2_lib.scala 314:18] + wire _T_3090 : UInt<1>[18] @[el2_lib.scala 315:18] + wire _T_3091 : UInt<1>[15] @[el2_lib.scala 316:18] + wire _T_3092 : UInt<1>[15] @[el2_lib.scala 317:18] + wire _T_3093 : UInt<1>[6] @[el2_lib.scala 318:18] + node _T_3094 = bits(_T_3086, 0, 0) @[el2_lib.scala 325:36] + _T_3088[0] <= _T_3094 @[el2_lib.scala 325:30] + node _T_3095 = bits(_T_3086, 0, 0) @[el2_lib.scala 326:36] + _T_3089[0] <= _T_3095 @[el2_lib.scala 326:30] + node _T_3096 = bits(_T_3086, 1, 1) @[el2_lib.scala 325:36] + _T_3088[1] <= _T_3096 @[el2_lib.scala 325:30] + node _T_3097 = bits(_T_3086, 1, 1) @[el2_lib.scala 327:36] + _T_3090[0] <= _T_3097 @[el2_lib.scala 327:30] + node _T_3098 = bits(_T_3086, 2, 2) @[el2_lib.scala 326:36] + _T_3089[1] <= _T_3098 @[el2_lib.scala 326:30] + node _T_3099 = bits(_T_3086, 2, 2) @[el2_lib.scala 327:36] + _T_3090[1] <= _T_3099 @[el2_lib.scala 327:30] + node _T_3100 = bits(_T_3086, 3, 3) @[el2_lib.scala 325:36] + _T_3088[2] <= _T_3100 @[el2_lib.scala 325:30] + node _T_3101 = bits(_T_3086, 3, 3) @[el2_lib.scala 326:36] + _T_3089[2] <= _T_3101 @[el2_lib.scala 326:30] + node _T_3102 = bits(_T_3086, 3, 3) @[el2_lib.scala 327:36] + _T_3090[2] <= _T_3102 @[el2_lib.scala 327:30] + node _T_3103 = bits(_T_3086, 4, 4) @[el2_lib.scala 325:36] + _T_3088[3] <= _T_3103 @[el2_lib.scala 325:30] + node _T_3104 = bits(_T_3086, 4, 4) @[el2_lib.scala 328:36] + _T_3091[0] <= _T_3104 @[el2_lib.scala 328:30] + node _T_3105 = bits(_T_3086, 5, 5) @[el2_lib.scala 326:36] + _T_3089[3] <= _T_3105 @[el2_lib.scala 326:30] + node _T_3106 = bits(_T_3086, 5, 5) @[el2_lib.scala 328:36] + _T_3091[1] <= _T_3106 @[el2_lib.scala 328:30] + node _T_3107 = bits(_T_3086, 6, 6) @[el2_lib.scala 325:36] + _T_3088[4] <= _T_3107 @[el2_lib.scala 325:30] + node _T_3108 = bits(_T_3086, 6, 6) @[el2_lib.scala 326:36] + _T_3089[4] <= _T_3108 @[el2_lib.scala 326:30] + node _T_3109 = bits(_T_3086, 6, 6) @[el2_lib.scala 328:36] + _T_3091[2] <= _T_3109 @[el2_lib.scala 328:30] + node _T_3110 = bits(_T_3086, 7, 7) @[el2_lib.scala 327:36] + _T_3090[3] <= _T_3110 @[el2_lib.scala 327:30] + node _T_3111 = bits(_T_3086, 7, 7) @[el2_lib.scala 328:36] + _T_3091[3] <= _T_3111 @[el2_lib.scala 328:30] + node _T_3112 = bits(_T_3086, 8, 8) @[el2_lib.scala 325:36] + _T_3088[5] <= _T_3112 @[el2_lib.scala 325:30] + node _T_3113 = bits(_T_3086, 8, 8) @[el2_lib.scala 327:36] + _T_3090[4] <= _T_3113 @[el2_lib.scala 327:30] + node _T_3114 = bits(_T_3086, 8, 8) @[el2_lib.scala 328:36] + _T_3091[4] <= _T_3114 @[el2_lib.scala 328:30] + node _T_3115 = bits(_T_3086, 9, 9) @[el2_lib.scala 326:36] + _T_3089[5] <= _T_3115 @[el2_lib.scala 326:30] + node _T_3116 = bits(_T_3086, 9, 9) @[el2_lib.scala 327:36] + _T_3090[5] <= _T_3116 @[el2_lib.scala 327:30] + node _T_3117 = bits(_T_3086, 9, 9) @[el2_lib.scala 328:36] + _T_3091[5] <= _T_3117 @[el2_lib.scala 328:30] + node _T_3118 = bits(_T_3086, 10, 10) @[el2_lib.scala 325:36] + _T_3088[6] <= _T_3118 @[el2_lib.scala 325:30] + node _T_3119 = bits(_T_3086, 10, 10) @[el2_lib.scala 326:36] + _T_3089[6] <= _T_3119 @[el2_lib.scala 326:30] + node _T_3120 = bits(_T_3086, 10, 10) @[el2_lib.scala 327:36] + _T_3090[6] <= _T_3120 @[el2_lib.scala 327:30] + node _T_3121 = bits(_T_3086, 10, 10) @[el2_lib.scala 328:36] + _T_3091[6] <= _T_3121 @[el2_lib.scala 328:30] + node _T_3122 = bits(_T_3086, 11, 11) @[el2_lib.scala 325:36] + _T_3088[7] <= _T_3122 @[el2_lib.scala 325:30] + node _T_3123 = bits(_T_3086, 11, 11) @[el2_lib.scala 329:36] + _T_3092[0] <= _T_3123 @[el2_lib.scala 329:30] + node _T_3124 = bits(_T_3086, 12, 12) @[el2_lib.scala 326:36] + _T_3089[7] <= _T_3124 @[el2_lib.scala 326:30] + node _T_3125 = bits(_T_3086, 12, 12) @[el2_lib.scala 329:36] + _T_3092[1] <= _T_3125 @[el2_lib.scala 329:30] + node _T_3126 = bits(_T_3086, 13, 13) @[el2_lib.scala 325:36] + _T_3088[8] <= _T_3126 @[el2_lib.scala 325:30] + node _T_3127 = bits(_T_3086, 13, 13) @[el2_lib.scala 326:36] + _T_3089[8] <= _T_3127 @[el2_lib.scala 326:30] + node _T_3128 = bits(_T_3086, 13, 13) @[el2_lib.scala 329:36] + _T_3092[2] <= _T_3128 @[el2_lib.scala 329:30] + node _T_3129 = bits(_T_3086, 14, 14) @[el2_lib.scala 327:36] + _T_3090[7] <= _T_3129 @[el2_lib.scala 327:30] + node _T_3130 = bits(_T_3086, 14, 14) @[el2_lib.scala 329:36] + _T_3092[3] <= _T_3130 @[el2_lib.scala 329:30] + node _T_3131 = bits(_T_3086, 15, 15) @[el2_lib.scala 325:36] + _T_3088[9] <= _T_3131 @[el2_lib.scala 325:30] + node _T_3132 = bits(_T_3086, 15, 15) @[el2_lib.scala 327:36] + _T_3090[8] <= _T_3132 @[el2_lib.scala 327:30] + node _T_3133 = bits(_T_3086, 15, 15) @[el2_lib.scala 329:36] + _T_3092[4] <= _T_3133 @[el2_lib.scala 329:30] + node _T_3134 = bits(_T_3086, 16, 16) @[el2_lib.scala 326:36] + _T_3089[9] <= _T_3134 @[el2_lib.scala 326:30] + node _T_3135 = bits(_T_3086, 16, 16) @[el2_lib.scala 327:36] + _T_3090[9] <= _T_3135 @[el2_lib.scala 327:30] + node _T_3136 = bits(_T_3086, 16, 16) @[el2_lib.scala 329:36] + _T_3092[5] <= _T_3136 @[el2_lib.scala 329:30] + node _T_3137 = bits(_T_3086, 17, 17) @[el2_lib.scala 325:36] + _T_3088[10] <= _T_3137 @[el2_lib.scala 325:30] + node _T_3138 = bits(_T_3086, 17, 17) @[el2_lib.scala 326:36] + _T_3089[10] <= _T_3138 @[el2_lib.scala 326:30] + node _T_3139 = bits(_T_3086, 17, 17) @[el2_lib.scala 327:36] + _T_3090[10] <= _T_3139 @[el2_lib.scala 327:30] + node _T_3140 = bits(_T_3086, 17, 17) @[el2_lib.scala 329:36] + _T_3092[6] <= _T_3140 @[el2_lib.scala 329:30] + node _T_3141 = bits(_T_3086, 18, 18) @[el2_lib.scala 328:36] + _T_3091[7] <= _T_3141 @[el2_lib.scala 328:30] + node _T_3142 = bits(_T_3086, 18, 18) @[el2_lib.scala 329:36] + _T_3092[7] <= _T_3142 @[el2_lib.scala 329:30] + node _T_3143 = bits(_T_3086, 19, 19) @[el2_lib.scala 325:36] + _T_3088[11] <= _T_3143 @[el2_lib.scala 325:30] + node _T_3144 = bits(_T_3086, 19, 19) @[el2_lib.scala 328:36] + _T_3091[8] <= _T_3144 @[el2_lib.scala 328:30] + node _T_3145 = bits(_T_3086, 19, 19) @[el2_lib.scala 329:36] + _T_3092[8] <= _T_3145 @[el2_lib.scala 329:30] + node _T_3146 = bits(_T_3086, 20, 20) @[el2_lib.scala 326:36] + _T_3089[11] <= _T_3146 @[el2_lib.scala 326:30] + node _T_3147 = bits(_T_3086, 20, 20) @[el2_lib.scala 328:36] + _T_3091[9] <= _T_3147 @[el2_lib.scala 328:30] + node _T_3148 = bits(_T_3086, 20, 20) @[el2_lib.scala 329:36] + _T_3092[9] <= _T_3148 @[el2_lib.scala 329:30] + node _T_3149 = bits(_T_3086, 21, 21) @[el2_lib.scala 325:36] + _T_3088[12] <= _T_3149 @[el2_lib.scala 325:30] + node _T_3150 = bits(_T_3086, 21, 21) @[el2_lib.scala 326:36] + _T_3089[12] <= _T_3150 @[el2_lib.scala 326:30] + node _T_3151 = bits(_T_3086, 21, 21) @[el2_lib.scala 328:36] + _T_3091[10] <= _T_3151 @[el2_lib.scala 328:30] + node _T_3152 = bits(_T_3086, 21, 21) @[el2_lib.scala 329:36] + _T_3092[10] <= _T_3152 @[el2_lib.scala 329:30] + node _T_3153 = bits(_T_3086, 22, 22) @[el2_lib.scala 327:36] + _T_3090[11] <= _T_3153 @[el2_lib.scala 327:30] + node _T_3154 = bits(_T_3086, 22, 22) @[el2_lib.scala 328:36] + _T_3091[11] <= _T_3154 @[el2_lib.scala 328:30] + node _T_3155 = bits(_T_3086, 22, 22) @[el2_lib.scala 329:36] + _T_3092[11] <= _T_3155 @[el2_lib.scala 329:30] + node _T_3156 = bits(_T_3086, 23, 23) @[el2_lib.scala 325:36] + _T_3088[13] <= _T_3156 @[el2_lib.scala 325:30] + node _T_3157 = bits(_T_3086, 23, 23) @[el2_lib.scala 327:36] + _T_3090[12] <= _T_3157 @[el2_lib.scala 327:30] + node _T_3158 = bits(_T_3086, 23, 23) @[el2_lib.scala 328:36] + _T_3091[12] <= _T_3158 @[el2_lib.scala 328:30] + node _T_3159 = bits(_T_3086, 23, 23) @[el2_lib.scala 329:36] + _T_3092[12] <= _T_3159 @[el2_lib.scala 329:30] + node _T_3160 = bits(_T_3086, 24, 24) @[el2_lib.scala 326:36] + _T_3089[13] <= _T_3160 @[el2_lib.scala 326:30] + node _T_3161 = bits(_T_3086, 24, 24) @[el2_lib.scala 327:36] + _T_3090[13] <= _T_3161 @[el2_lib.scala 327:30] + node _T_3162 = bits(_T_3086, 24, 24) @[el2_lib.scala 328:36] + _T_3091[13] <= _T_3162 @[el2_lib.scala 328:30] + node _T_3163 = bits(_T_3086, 24, 24) @[el2_lib.scala 329:36] + _T_3092[13] <= _T_3163 @[el2_lib.scala 329:30] + node _T_3164 = bits(_T_3086, 25, 25) @[el2_lib.scala 325:36] + _T_3088[14] <= _T_3164 @[el2_lib.scala 325:30] + node _T_3165 = bits(_T_3086, 25, 25) @[el2_lib.scala 326:36] + _T_3089[14] <= _T_3165 @[el2_lib.scala 326:30] + node _T_3166 = bits(_T_3086, 25, 25) @[el2_lib.scala 327:36] + _T_3090[14] <= _T_3166 @[el2_lib.scala 327:30] + node _T_3167 = bits(_T_3086, 25, 25) @[el2_lib.scala 328:36] + _T_3091[14] <= _T_3167 @[el2_lib.scala 328:30] + node _T_3168 = bits(_T_3086, 25, 25) @[el2_lib.scala 329:36] + _T_3092[14] <= _T_3168 @[el2_lib.scala 329:30] + node _T_3169 = bits(_T_3086, 26, 26) @[el2_lib.scala 325:36] + _T_3088[15] <= _T_3169 @[el2_lib.scala 325:30] + node _T_3170 = bits(_T_3086, 26, 26) @[el2_lib.scala 330:36] + _T_3093[0] <= _T_3170 @[el2_lib.scala 330:30] + node _T_3171 = bits(_T_3086, 27, 27) @[el2_lib.scala 326:36] + _T_3089[15] <= _T_3171 @[el2_lib.scala 326:30] + node _T_3172 = bits(_T_3086, 27, 27) @[el2_lib.scala 330:36] + _T_3093[1] <= _T_3172 @[el2_lib.scala 330:30] + node _T_3173 = bits(_T_3086, 28, 28) @[el2_lib.scala 325:36] + _T_3088[16] <= _T_3173 @[el2_lib.scala 325:30] + node _T_3174 = bits(_T_3086, 28, 28) @[el2_lib.scala 326:36] + _T_3089[16] <= _T_3174 @[el2_lib.scala 326:30] + node _T_3175 = bits(_T_3086, 28, 28) @[el2_lib.scala 330:36] + _T_3093[2] <= _T_3175 @[el2_lib.scala 330:30] + node _T_3176 = bits(_T_3086, 29, 29) @[el2_lib.scala 327:36] + _T_3090[15] <= _T_3176 @[el2_lib.scala 327:30] + node _T_3177 = bits(_T_3086, 29, 29) @[el2_lib.scala 330:36] + _T_3093[3] <= _T_3177 @[el2_lib.scala 330:30] + node _T_3178 = bits(_T_3086, 30, 30) @[el2_lib.scala 325:36] + _T_3088[17] <= _T_3178 @[el2_lib.scala 325:30] + node _T_3179 = bits(_T_3086, 30, 30) @[el2_lib.scala 327:36] + _T_3090[16] <= _T_3179 @[el2_lib.scala 327:30] + node _T_3180 = bits(_T_3086, 30, 30) @[el2_lib.scala 330:36] + _T_3093[4] <= _T_3180 @[el2_lib.scala 330:30] + node _T_3181 = bits(_T_3086, 31, 31) @[el2_lib.scala 326:36] + _T_3089[17] <= _T_3181 @[el2_lib.scala 326:30] + node _T_3182 = bits(_T_3086, 31, 31) @[el2_lib.scala 327:36] + _T_3090[17] <= _T_3182 @[el2_lib.scala 327:30] + node _T_3183 = bits(_T_3086, 31, 31) @[el2_lib.scala 330:36] + _T_3093[5] <= _T_3183 @[el2_lib.scala 330:30] + node _T_3184 = xorr(_T_3086) @[el2_lib.scala 333:30] + node _T_3185 = xorr(_T_3087) @[el2_lib.scala 333:44] + node _T_3186 = xor(_T_3184, _T_3185) @[el2_lib.scala 333:35] + node _T_3187 = not(UInt<1>("h00")) @[el2_lib.scala 333:52] + node _T_3188 = and(_T_3186, _T_3187) @[el2_lib.scala 333:50] + node _T_3189 = bits(_T_3087, 5, 5) @[el2_lib.scala 333:68] + node _T_3190 = cat(_T_3093[2], _T_3093[1]) @[el2_lib.scala 333:76] + node _T_3191 = cat(_T_3190, _T_3093[0]) @[el2_lib.scala 333:76] + node _T_3192 = cat(_T_3093[5], _T_3093[4]) @[el2_lib.scala 333:76] + node _T_3193 = cat(_T_3192, _T_3093[3]) @[el2_lib.scala 333:76] + node _T_3194 = cat(_T_3193, _T_3191) @[el2_lib.scala 333:76] + node _T_3195 = xorr(_T_3194) @[el2_lib.scala 333:83] + node _T_3196 = xor(_T_3189, _T_3195) @[el2_lib.scala 333:71] + node _T_3197 = bits(_T_3087, 4, 4) @[el2_lib.scala 333:95] + node _T_3198 = cat(_T_3092[2], _T_3092[1]) @[el2_lib.scala 333:103] + node _T_3199 = cat(_T_3198, _T_3092[0]) @[el2_lib.scala 333:103] + node _T_3200 = cat(_T_3092[4], _T_3092[3]) @[el2_lib.scala 333:103] + node _T_3201 = cat(_T_3092[6], _T_3092[5]) @[el2_lib.scala 333:103] + node _T_3202 = cat(_T_3201, _T_3200) @[el2_lib.scala 333:103] + node _T_3203 = cat(_T_3202, _T_3199) @[el2_lib.scala 333:103] + node _T_3204 = cat(_T_3092[8], _T_3092[7]) @[el2_lib.scala 333:103] + node _T_3205 = cat(_T_3092[10], _T_3092[9]) @[el2_lib.scala 333:103] + node _T_3206 = cat(_T_3205, _T_3204) @[el2_lib.scala 333:103] + node _T_3207 = cat(_T_3092[12], _T_3092[11]) @[el2_lib.scala 333:103] + node _T_3208 = cat(_T_3092[14], _T_3092[13]) @[el2_lib.scala 333:103] + node _T_3209 = cat(_T_3208, _T_3207) @[el2_lib.scala 333:103] + node _T_3210 = cat(_T_3209, _T_3206) @[el2_lib.scala 333:103] + node _T_3211 = cat(_T_3210, _T_3203) @[el2_lib.scala 333:103] + node _T_3212 = xorr(_T_3211) @[el2_lib.scala 333:110] + node _T_3213 = xor(_T_3197, _T_3212) @[el2_lib.scala 333:98] + node _T_3214 = bits(_T_3087, 3, 3) @[el2_lib.scala 333:122] + node _T_3215 = cat(_T_3091[2], _T_3091[1]) @[el2_lib.scala 333:130] + node _T_3216 = cat(_T_3215, _T_3091[0]) @[el2_lib.scala 333:130] + node _T_3217 = cat(_T_3091[4], _T_3091[3]) @[el2_lib.scala 333:130] + node _T_3218 = cat(_T_3091[6], _T_3091[5]) @[el2_lib.scala 333:130] + node _T_3219 = cat(_T_3218, _T_3217) @[el2_lib.scala 333:130] + node _T_3220 = cat(_T_3219, _T_3216) @[el2_lib.scala 333:130] + node _T_3221 = cat(_T_3091[8], _T_3091[7]) @[el2_lib.scala 333:130] + node _T_3222 = cat(_T_3091[10], _T_3091[9]) @[el2_lib.scala 333:130] + node _T_3223 = cat(_T_3222, _T_3221) @[el2_lib.scala 333:130] + node _T_3224 = cat(_T_3091[12], _T_3091[11]) @[el2_lib.scala 333:130] + node _T_3225 = cat(_T_3091[14], _T_3091[13]) @[el2_lib.scala 333:130] + node _T_3226 = cat(_T_3225, _T_3224) @[el2_lib.scala 333:130] + node _T_3227 = cat(_T_3226, _T_3223) @[el2_lib.scala 333:130] + node _T_3228 = cat(_T_3227, _T_3220) @[el2_lib.scala 333:130] + node _T_3229 = xorr(_T_3228) @[el2_lib.scala 333:137] + node _T_3230 = xor(_T_3214, _T_3229) @[el2_lib.scala 333:125] + node _T_3231 = bits(_T_3087, 2, 2) @[el2_lib.scala 333:149] + node _T_3232 = cat(_T_3090[1], _T_3090[0]) @[el2_lib.scala 333:157] + node _T_3233 = cat(_T_3090[3], _T_3090[2]) @[el2_lib.scala 333:157] + node _T_3234 = cat(_T_3233, _T_3232) @[el2_lib.scala 333:157] + node _T_3235 = cat(_T_3090[5], _T_3090[4]) @[el2_lib.scala 333:157] + node _T_3236 = cat(_T_3090[8], _T_3090[7]) @[el2_lib.scala 333:157] + node _T_3237 = cat(_T_3236, _T_3090[6]) @[el2_lib.scala 333:157] + node _T_3238 = cat(_T_3237, _T_3235) @[el2_lib.scala 333:157] + node _T_3239 = cat(_T_3238, _T_3234) @[el2_lib.scala 333:157] + node _T_3240 = cat(_T_3090[10], _T_3090[9]) @[el2_lib.scala 333:157] + node _T_3241 = cat(_T_3090[12], _T_3090[11]) @[el2_lib.scala 333:157] + node _T_3242 = cat(_T_3241, _T_3240) @[el2_lib.scala 333:157] + node _T_3243 = cat(_T_3090[14], _T_3090[13]) @[el2_lib.scala 333:157] + node _T_3244 = cat(_T_3090[17], _T_3090[16]) @[el2_lib.scala 333:157] + node _T_3245 = cat(_T_3244, _T_3090[15]) @[el2_lib.scala 333:157] + node _T_3246 = cat(_T_3245, _T_3243) @[el2_lib.scala 333:157] + node _T_3247 = cat(_T_3246, _T_3242) @[el2_lib.scala 333:157] + node _T_3248 = cat(_T_3247, _T_3239) @[el2_lib.scala 333:157] + node _T_3249 = xorr(_T_3248) @[el2_lib.scala 333:164] + node _T_3250 = xor(_T_3231, _T_3249) @[el2_lib.scala 333:152] + node _T_3251 = bits(_T_3087, 1, 1) @[el2_lib.scala 333:176] + node _T_3252 = cat(_T_3089[1], _T_3089[0]) @[el2_lib.scala 333:184] + node _T_3253 = cat(_T_3089[3], _T_3089[2]) @[el2_lib.scala 333:184] + node _T_3254 = cat(_T_3253, _T_3252) @[el2_lib.scala 333:184] + node _T_3255 = cat(_T_3089[5], _T_3089[4]) @[el2_lib.scala 333:184] + node _T_3256 = cat(_T_3089[8], _T_3089[7]) @[el2_lib.scala 333:184] + node _T_3257 = cat(_T_3256, _T_3089[6]) @[el2_lib.scala 333:184] + node _T_3258 = cat(_T_3257, _T_3255) @[el2_lib.scala 333:184] + node _T_3259 = cat(_T_3258, _T_3254) @[el2_lib.scala 333:184] + node _T_3260 = cat(_T_3089[10], _T_3089[9]) @[el2_lib.scala 333:184] + node _T_3261 = cat(_T_3089[12], _T_3089[11]) @[el2_lib.scala 333:184] + node _T_3262 = cat(_T_3261, _T_3260) @[el2_lib.scala 333:184] + node _T_3263 = cat(_T_3089[14], _T_3089[13]) @[el2_lib.scala 333:184] + node _T_3264 = cat(_T_3089[17], _T_3089[16]) @[el2_lib.scala 333:184] + node _T_3265 = cat(_T_3264, _T_3089[15]) @[el2_lib.scala 333:184] + node _T_3266 = cat(_T_3265, _T_3263) @[el2_lib.scala 333:184] + node _T_3267 = cat(_T_3266, _T_3262) @[el2_lib.scala 333:184] + node _T_3268 = cat(_T_3267, _T_3259) @[el2_lib.scala 333:184] + node _T_3269 = xorr(_T_3268) @[el2_lib.scala 333:191] + node _T_3270 = xor(_T_3251, _T_3269) @[el2_lib.scala 333:179] + node _T_3271 = bits(_T_3087, 0, 0) @[el2_lib.scala 333:203] + node _T_3272 = cat(_T_3088[1], _T_3088[0]) @[el2_lib.scala 333:211] + node _T_3273 = cat(_T_3088[3], _T_3088[2]) @[el2_lib.scala 333:211] + node _T_3274 = cat(_T_3273, _T_3272) @[el2_lib.scala 333:211] + node _T_3275 = cat(_T_3088[5], _T_3088[4]) @[el2_lib.scala 333:211] + node _T_3276 = cat(_T_3088[8], _T_3088[7]) @[el2_lib.scala 333:211] + node _T_3277 = cat(_T_3276, _T_3088[6]) @[el2_lib.scala 333:211] + node _T_3278 = cat(_T_3277, _T_3275) @[el2_lib.scala 333:211] + node _T_3279 = cat(_T_3278, _T_3274) @[el2_lib.scala 333:211] + node _T_3280 = cat(_T_3088[10], _T_3088[9]) @[el2_lib.scala 333:211] + node _T_3281 = cat(_T_3088[12], _T_3088[11]) @[el2_lib.scala 333:211] + node _T_3282 = cat(_T_3281, _T_3280) @[el2_lib.scala 333:211] + node _T_3283 = cat(_T_3088[14], _T_3088[13]) @[el2_lib.scala 333:211] + node _T_3284 = cat(_T_3088[17], _T_3088[16]) @[el2_lib.scala 333:211] + node _T_3285 = cat(_T_3284, _T_3088[15]) @[el2_lib.scala 333:211] + node _T_3286 = cat(_T_3285, _T_3283) @[el2_lib.scala 333:211] + node _T_3287 = cat(_T_3286, _T_3282) @[el2_lib.scala 333:211] + node _T_3288 = cat(_T_3287, _T_3279) @[el2_lib.scala 333:211] + node _T_3289 = xorr(_T_3288) @[el2_lib.scala 333:218] + node _T_3290 = xor(_T_3271, _T_3289) @[el2_lib.scala 333:206] + node _T_3291 = cat(_T_3250, _T_3270) @[Cat.scala 29:58] + node _T_3292 = cat(_T_3291, _T_3290) @[Cat.scala 29:58] + node _T_3293 = cat(_T_3213, _T_3230) @[Cat.scala 29:58] + node _T_3294 = cat(_T_3188, _T_3196) @[Cat.scala 29:58] + node _T_3295 = cat(_T_3294, _T_3293) @[Cat.scala 29:58] + node _T_3296 = cat(_T_3295, _T_3292) @[Cat.scala 29:58] + node _T_3297 = neq(_T_3296, UInt<1>("h00")) @[el2_lib.scala 334:44] + node _T_3298 = and(_T_3085, _T_3297) @[el2_lib.scala 334:32] + node _T_3299 = bits(_T_3296, 6, 6) @[el2_lib.scala 334:64] + node _T_3300 = and(_T_3298, _T_3299) @[el2_lib.scala 334:53] + node _T_3301 = neq(_T_3296, UInt<1>("h00")) @[el2_lib.scala 335:44] + node _T_3302 = and(_T_3085, _T_3301) @[el2_lib.scala 335:32] + node _T_3303 = bits(_T_3296, 6, 6) @[el2_lib.scala 335:65] + node _T_3304 = not(_T_3303) @[el2_lib.scala 335:55] + node _T_3305 = and(_T_3302, _T_3304) @[el2_lib.scala 335:53] + wire _T_3306 : UInt<1>[39] @[el2_lib.scala 336:26] + node _T_3307 = bits(_T_3296, 5, 0) @[el2_lib.scala 339:35] + node _T_3308 = eq(_T_3307, UInt<1>("h01")) @[el2_lib.scala 339:41] + _T_3306[0] <= _T_3308 @[el2_lib.scala 339:23] + node _T_3309 = bits(_T_3296, 5, 0) @[el2_lib.scala 339:35] + node _T_3310 = eq(_T_3309, UInt<2>("h02")) @[el2_lib.scala 339:41] + _T_3306[1] <= _T_3310 @[el2_lib.scala 339:23] + node _T_3311 = bits(_T_3296, 5, 0) @[el2_lib.scala 339:35] + node _T_3312 = eq(_T_3311, UInt<2>("h03")) @[el2_lib.scala 339:41] + _T_3306[2] <= _T_3312 @[el2_lib.scala 339:23] + node _T_3313 = bits(_T_3296, 5, 0) @[el2_lib.scala 339:35] + node _T_3314 = eq(_T_3313, UInt<3>("h04")) @[el2_lib.scala 339:41] + _T_3306[3] <= _T_3314 @[el2_lib.scala 339:23] + node _T_3315 = bits(_T_3296, 5, 0) @[el2_lib.scala 339:35] + node _T_3316 = eq(_T_3315, UInt<3>("h05")) @[el2_lib.scala 339:41] + _T_3306[4] <= _T_3316 @[el2_lib.scala 339:23] + node _T_3317 = bits(_T_3296, 5, 0) @[el2_lib.scala 339:35] + node _T_3318 = eq(_T_3317, UInt<3>("h06")) @[el2_lib.scala 339:41] + _T_3306[5] <= _T_3318 @[el2_lib.scala 339:23] + node _T_3319 = bits(_T_3296, 5, 0) @[el2_lib.scala 339:35] + node _T_3320 = eq(_T_3319, UInt<3>("h07")) @[el2_lib.scala 339:41] + _T_3306[6] <= _T_3320 @[el2_lib.scala 339:23] + node _T_3321 = bits(_T_3296, 5, 0) @[el2_lib.scala 339:35] + node _T_3322 = eq(_T_3321, UInt<4>("h08")) @[el2_lib.scala 339:41] + _T_3306[7] <= _T_3322 @[el2_lib.scala 339:23] + node _T_3323 = bits(_T_3296, 5, 0) @[el2_lib.scala 339:35] + node _T_3324 = eq(_T_3323, UInt<4>("h09")) @[el2_lib.scala 339:41] + _T_3306[8] <= _T_3324 @[el2_lib.scala 339:23] + node _T_3325 = bits(_T_3296, 5, 0) @[el2_lib.scala 339:35] + node _T_3326 = eq(_T_3325, UInt<4>("h0a")) @[el2_lib.scala 339:41] + _T_3306[9] <= _T_3326 @[el2_lib.scala 339:23] + node _T_3327 = bits(_T_3296, 5, 0) @[el2_lib.scala 339:35] + node _T_3328 = eq(_T_3327, UInt<4>("h0b")) @[el2_lib.scala 339:41] + _T_3306[10] <= _T_3328 @[el2_lib.scala 339:23] + node _T_3329 = bits(_T_3296, 5, 0) @[el2_lib.scala 339:35] + node _T_3330 = eq(_T_3329, UInt<4>("h0c")) @[el2_lib.scala 339:41] + _T_3306[11] <= _T_3330 @[el2_lib.scala 339:23] + node _T_3331 = bits(_T_3296, 5, 0) @[el2_lib.scala 339:35] + node _T_3332 = eq(_T_3331, UInt<4>("h0d")) @[el2_lib.scala 339:41] + _T_3306[12] <= _T_3332 @[el2_lib.scala 339:23] + node _T_3333 = bits(_T_3296, 5, 0) @[el2_lib.scala 339:35] + node _T_3334 = eq(_T_3333, UInt<4>("h0e")) @[el2_lib.scala 339:41] + _T_3306[13] <= _T_3334 @[el2_lib.scala 339:23] + node _T_3335 = bits(_T_3296, 5, 0) @[el2_lib.scala 339:35] + node _T_3336 = eq(_T_3335, UInt<4>("h0f")) @[el2_lib.scala 339:41] + _T_3306[14] <= _T_3336 @[el2_lib.scala 339:23] + node _T_3337 = bits(_T_3296, 5, 0) @[el2_lib.scala 339:35] + node _T_3338 = eq(_T_3337, UInt<5>("h010")) @[el2_lib.scala 339:41] + _T_3306[15] <= _T_3338 @[el2_lib.scala 339:23] + node _T_3339 = bits(_T_3296, 5, 0) @[el2_lib.scala 339:35] + node _T_3340 = eq(_T_3339, UInt<5>("h011")) @[el2_lib.scala 339:41] + _T_3306[16] <= _T_3340 @[el2_lib.scala 339:23] + node _T_3341 = bits(_T_3296, 5, 0) @[el2_lib.scala 339:35] + node _T_3342 = eq(_T_3341, UInt<5>("h012")) @[el2_lib.scala 339:41] + _T_3306[17] <= _T_3342 @[el2_lib.scala 339:23] + node _T_3343 = bits(_T_3296, 5, 0) @[el2_lib.scala 339:35] + node _T_3344 = eq(_T_3343, UInt<5>("h013")) @[el2_lib.scala 339:41] + _T_3306[18] <= _T_3344 @[el2_lib.scala 339:23] + node _T_3345 = bits(_T_3296, 5, 0) @[el2_lib.scala 339:35] + node _T_3346 = eq(_T_3345, UInt<5>("h014")) @[el2_lib.scala 339:41] + _T_3306[19] <= _T_3346 @[el2_lib.scala 339:23] + node _T_3347 = bits(_T_3296, 5, 0) @[el2_lib.scala 339:35] + node _T_3348 = eq(_T_3347, UInt<5>("h015")) @[el2_lib.scala 339:41] + _T_3306[20] <= _T_3348 @[el2_lib.scala 339:23] + node _T_3349 = bits(_T_3296, 5, 0) @[el2_lib.scala 339:35] + node _T_3350 = eq(_T_3349, UInt<5>("h016")) @[el2_lib.scala 339:41] + _T_3306[21] <= _T_3350 @[el2_lib.scala 339:23] + node _T_3351 = bits(_T_3296, 5, 0) @[el2_lib.scala 339:35] + node _T_3352 = eq(_T_3351, UInt<5>("h017")) @[el2_lib.scala 339:41] + _T_3306[22] <= _T_3352 @[el2_lib.scala 339:23] + node _T_3353 = bits(_T_3296, 5, 0) @[el2_lib.scala 339:35] + node _T_3354 = eq(_T_3353, UInt<5>("h018")) @[el2_lib.scala 339:41] + _T_3306[23] <= _T_3354 @[el2_lib.scala 339:23] + node _T_3355 = bits(_T_3296, 5, 0) @[el2_lib.scala 339:35] + node _T_3356 = eq(_T_3355, UInt<5>("h019")) @[el2_lib.scala 339:41] + _T_3306[24] <= _T_3356 @[el2_lib.scala 339:23] + node _T_3357 = bits(_T_3296, 5, 0) @[el2_lib.scala 339:35] + node _T_3358 = eq(_T_3357, UInt<5>("h01a")) @[el2_lib.scala 339:41] + _T_3306[25] <= _T_3358 @[el2_lib.scala 339:23] + node _T_3359 = bits(_T_3296, 5, 0) @[el2_lib.scala 339:35] + node _T_3360 = eq(_T_3359, UInt<5>("h01b")) @[el2_lib.scala 339:41] + _T_3306[26] <= _T_3360 @[el2_lib.scala 339:23] + node _T_3361 = bits(_T_3296, 5, 0) @[el2_lib.scala 339:35] + node _T_3362 = eq(_T_3361, UInt<5>("h01c")) @[el2_lib.scala 339:41] + _T_3306[27] <= _T_3362 @[el2_lib.scala 339:23] + node _T_3363 = bits(_T_3296, 5, 0) @[el2_lib.scala 339:35] + node _T_3364 = eq(_T_3363, UInt<5>("h01d")) @[el2_lib.scala 339:41] + _T_3306[28] <= _T_3364 @[el2_lib.scala 339:23] + node _T_3365 = bits(_T_3296, 5, 0) @[el2_lib.scala 339:35] + node _T_3366 = eq(_T_3365, UInt<5>("h01e")) @[el2_lib.scala 339:41] + _T_3306[29] <= _T_3366 @[el2_lib.scala 339:23] + node _T_3367 = bits(_T_3296, 5, 0) @[el2_lib.scala 339:35] + node _T_3368 = eq(_T_3367, UInt<5>("h01f")) @[el2_lib.scala 339:41] + _T_3306[30] <= _T_3368 @[el2_lib.scala 339:23] + node _T_3369 = bits(_T_3296, 5, 0) @[el2_lib.scala 339:35] + node _T_3370 = eq(_T_3369, UInt<6>("h020")) @[el2_lib.scala 339:41] + _T_3306[31] <= _T_3370 @[el2_lib.scala 339:23] + node _T_3371 = bits(_T_3296, 5, 0) @[el2_lib.scala 339:35] + node _T_3372 = eq(_T_3371, UInt<6>("h021")) @[el2_lib.scala 339:41] + _T_3306[32] <= _T_3372 @[el2_lib.scala 339:23] + node _T_3373 = bits(_T_3296, 5, 0) @[el2_lib.scala 339:35] + node _T_3374 = eq(_T_3373, UInt<6>("h022")) @[el2_lib.scala 339:41] + _T_3306[33] <= _T_3374 @[el2_lib.scala 339:23] + node _T_3375 = bits(_T_3296, 5, 0) @[el2_lib.scala 339:35] + node _T_3376 = eq(_T_3375, UInt<6>("h023")) @[el2_lib.scala 339:41] + _T_3306[34] <= _T_3376 @[el2_lib.scala 339:23] + node _T_3377 = bits(_T_3296, 5, 0) @[el2_lib.scala 339:35] + node _T_3378 = eq(_T_3377, UInt<6>("h024")) @[el2_lib.scala 339:41] + _T_3306[35] <= _T_3378 @[el2_lib.scala 339:23] + node _T_3379 = bits(_T_3296, 5, 0) @[el2_lib.scala 339:35] + node _T_3380 = eq(_T_3379, UInt<6>("h025")) @[el2_lib.scala 339:41] + _T_3306[36] <= _T_3380 @[el2_lib.scala 339:23] + node _T_3381 = bits(_T_3296, 5, 0) @[el2_lib.scala 339:35] + node _T_3382 = eq(_T_3381, UInt<6>("h026")) @[el2_lib.scala 339:41] + _T_3306[37] <= _T_3382 @[el2_lib.scala 339:23] + node _T_3383 = bits(_T_3296, 5, 0) @[el2_lib.scala 339:35] + node _T_3384 = eq(_T_3383, UInt<6>("h027")) @[el2_lib.scala 339:41] + _T_3306[38] <= _T_3384 @[el2_lib.scala 339:23] + node _T_3385 = bits(_T_3087, 6, 6) @[el2_lib.scala 341:37] + node _T_3386 = bits(_T_3086, 31, 26) @[el2_lib.scala 341:45] + node _T_3387 = bits(_T_3087, 5, 5) @[el2_lib.scala 341:60] + node _T_3388 = bits(_T_3086, 25, 11) @[el2_lib.scala 341:68] + node _T_3389 = bits(_T_3087, 4, 4) @[el2_lib.scala 341:83] + node _T_3390 = bits(_T_3086, 10, 4) @[el2_lib.scala 341:91] + node _T_3391 = bits(_T_3087, 3, 3) @[el2_lib.scala 341:105] + node _T_3392 = bits(_T_3086, 3, 1) @[el2_lib.scala 341:113] + node _T_3393 = bits(_T_3087, 2, 2) @[el2_lib.scala 341:126] + node _T_3394 = bits(_T_3086, 0, 0) @[el2_lib.scala 341:134] + node _T_3395 = bits(_T_3087, 1, 0) @[el2_lib.scala 341:145] + node _T_3396 = cat(_T_3394, _T_3395) @[Cat.scala 29:58] + node _T_3397 = cat(_T_3391, _T_3392) @[Cat.scala 29:58] + node _T_3398 = cat(_T_3397, _T_3393) @[Cat.scala 29:58] + node _T_3399 = cat(_T_3398, _T_3396) @[Cat.scala 29:58] + node _T_3400 = cat(_T_3388, _T_3389) @[Cat.scala 29:58] + node _T_3401 = cat(_T_3400, _T_3390) @[Cat.scala 29:58] + node _T_3402 = cat(_T_3385, _T_3386) @[Cat.scala 29:58] + node _T_3403 = cat(_T_3402, _T_3387) @[Cat.scala 29:58] + node _T_3404 = cat(_T_3403, _T_3401) @[Cat.scala 29:58] + node _T_3405 = cat(_T_3404, _T_3399) @[Cat.scala 29:58] + node _T_3406 = bits(_T_3300, 0, 0) @[el2_lib.scala 342:49] + node _T_3407 = cat(_T_3306[1], _T_3306[0]) @[el2_lib.scala 342:69] + node _T_3408 = cat(_T_3306[3], _T_3306[2]) @[el2_lib.scala 342:69] + node _T_3409 = cat(_T_3408, _T_3407) @[el2_lib.scala 342:69] + node _T_3410 = cat(_T_3306[5], _T_3306[4]) @[el2_lib.scala 342:69] + node _T_3411 = cat(_T_3306[8], _T_3306[7]) @[el2_lib.scala 342:69] + node _T_3412 = cat(_T_3411, _T_3306[6]) @[el2_lib.scala 342:69] + node _T_3413 = cat(_T_3412, _T_3410) @[el2_lib.scala 342:69] + node _T_3414 = cat(_T_3413, _T_3409) @[el2_lib.scala 342:69] + node _T_3415 = cat(_T_3306[10], _T_3306[9]) @[el2_lib.scala 342:69] + node _T_3416 = cat(_T_3306[13], _T_3306[12]) @[el2_lib.scala 342:69] + node _T_3417 = cat(_T_3416, _T_3306[11]) @[el2_lib.scala 342:69] + node _T_3418 = cat(_T_3417, _T_3415) @[el2_lib.scala 342:69] + node _T_3419 = cat(_T_3306[15], _T_3306[14]) @[el2_lib.scala 342:69] + node _T_3420 = cat(_T_3306[18], _T_3306[17]) @[el2_lib.scala 342:69] + node _T_3421 = cat(_T_3420, _T_3306[16]) @[el2_lib.scala 342:69] + node _T_3422 = cat(_T_3421, _T_3419) @[el2_lib.scala 342:69] + node _T_3423 = cat(_T_3422, _T_3418) @[el2_lib.scala 342:69] + node _T_3424 = cat(_T_3423, _T_3414) @[el2_lib.scala 342:69] + node _T_3425 = cat(_T_3306[20], _T_3306[19]) @[el2_lib.scala 342:69] + node _T_3426 = cat(_T_3306[23], _T_3306[22]) @[el2_lib.scala 342:69] + node _T_3427 = cat(_T_3426, _T_3306[21]) @[el2_lib.scala 342:69] + node _T_3428 = cat(_T_3427, _T_3425) @[el2_lib.scala 342:69] + node _T_3429 = cat(_T_3306[25], _T_3306[24]) @[el2_lib.scala 342:69] + node _T_3430 = cat(_T_3306[28], _T_3306[27]) @[el2_lib.scala 342:69] + node _T_3431 = cat(_T_3430, _T_3306[26]) @[el2_lib.scala 342:69] + node _T_3432 = cat(_T_3431, _T_3429) @[el2_lib.scala 342:69] + node _T_3433 = cat(_T_3432, _T_3428) @[el2_lib.scala 342:69] + node _T_3434 = cat(_T_3306[30], _T_3306[29]) @[el2_lib.scala 342:69] + node _T_3435 = cat(_T_3306[33], _T_3306[32]) @[el2_lib.scala 342:69] + node _T_3436 = cat(_T_3435, _T_3306[31]) @[el2_lib.scala 342:69] + node _T_3437 = cat(_T_3436, _T_3434) @[el2_lib.scala 342:69] + node _T_3438 = cat(_T_3306[35], _T_3306[34]) @[el2_lib.scala 342:69] + node _T_3439 = cat(_T_3306[38], _T_3306[37]) @[el2_lib.scala 342:69] + node _T_3440 = cat(_T_3439, _T_3306[36]) @[el2_lib.scala 342:69] + node _T_3441 = cat(_T_3440, _T_3438) @[el2_lib.scala 342:69] + node _T_3442 = cat(_T_3441, _T_3437) @[el2_lib.scala 342:69] + node _T_3443 = cat(_T_3442, _T_3433) @[el2_lib.scala 342:69] + node _T_3444 = cat(_T_3443, _T_3424) @[el2_lib.scala 342:69] + node _T_3445 = xor(_T_3444, _T_3405) @[el2_lib.scala 342:76] + node _T_3446 = mux(_T_3406, _T_3445, _T_3405) @[el2_lib.scala 342:31] + node _T_3447 = bits(_T_3446, 37, 32) @[el2_lib.scala 344:37] + node _T_3448 = bits(_T_3446, 30, 16) @[el2_lib.scala 344:61] + node _T_3449 = bits(_T_3446, 14, 8) @[el2_lib.scala 344:86] + node _T_3450 = bits(_T_3446, 6, 4) @[el2_lib.scala 344:110] + node _T_3451 = bits(_T_3446, 2, 2) @[el2_lib.scala 344:133] + node _T_3452 = cat(_T_3450, _T_3451) @[Cat.scala 29:58] + node _T_3453 = cat(_T_3447, _T_3448) @[Cat.scala 29:58] + node _T_3454 = cat(_T_3453, _T_3449) @[Cat.scala 29:58] + node _T_3455 = cat(_T_3454, _T_3452) @[Cat.scala 29:58] + node _T_3456 = bits(_T_3446, 38, 38) @[el2_lib.scala 345:39] + node _T_3457 = bits(_T_3296, 6, 0) @[el2_lib.scala 345:56] + node _T_3458 = eq(_T_3457, UInt<7>("h040")) @[el2_lib.scala 345:62] + node _T_3459 = xor(_T_3456, _T_3458) @[el2_lib.scala 345:44] + node _T_3460 = bits(_T_3446, 31, 31) @[el2_lib.scala 345:102] + node _T_3461 = bits(_T_3446, 15, 15) @[el2_lib.scala 345:124] + node _T_3462 = bits(_T_3446, 7, 7) @[el2_lib.scala 345:146] + node _T_3463 = bits(_T_3446, 3, 3) @[el2_lib.scala 345:167] + node _T_3464 = bits(_T_3446, 1, 0) @[el2_lib.scala 345:188] + node _T_3465 = cat(_T_3462, _T_3463) @[Cat.scala 29:58] + node _T_3466 = cat(_T_3465, _T_3464) @[Cat.scala 29:58] + node _T_3467 = cat(_T_3459, _T_3460) @[Cat.scala 29:58] + node _T_3468 = cat(_T_3467, _T_3461) @[Cat.scala 29:58] + node _T_3469 = cat(_T_3468, _T_3466) @[Cat.scala 29:58] + node _T_3470 = bits(iccm_ecc_word_enable, 1, 1) @[el2_ifu_mem_ctl.scala 674:73] + node _T_3471 = bits(io.iccm_rd_data_ecc, 70, 39) @[el2_ifu_mem_ctl.scala 674:93] + node _T_3472 = bits(io.iccm_rd_data_ecc, 77, 71) @[el2_ifu_mem_ctl.scala 674:128] + wire _T_3473 : UInt<1>[18] @[el2_lib.scala 313:18] + wire _T_3474 : UInt<1>[18] @[el2_lib.scala 314:18] + wire _T_3475 : UInt<1>[18] @[el2_lib.scala 315:18] + wire _T_3476 : UInt<1>[15] @[el2_lib.scala 316:18] + wire _T_3477 : UInt<1>[15] @[el2_lib.scala 317:18] + wire _T_3478 : UInt<1>[6] @[el2_lib.scala 318:18] + node _T_3479 = bits(_T_3471, 0, 0) @[el2_lib.scala 325:36] + _T_3473[0] <= _T_3479 @[el2_lib.scala 325:30] + node _T_3480 = bits(_T_3471, 0, 0) @[el2_lib.scala 326:36] + _T_3474[0] <= _T_3480 @[el2_lib.scala 326:30] + node _T_3481 = bits(_T_3471, 1, 1) @[el2_lib.scala 325:36] + _T_3473[1] <= _T_3481 @[el2_lib.scala 325:30] + node _T_3482 = bits(_T_3471, 1, 1) @[el2_lib.scala 327:36] + _T_3475[0] <= _T_3482 @[el2_lib.scala 327:30] + node _T_3483 = bits(_T_3471, 2, 2) @[el2_lib.scala 326:36] + _T_3474[1] <= _T_3483 @[el2_lib.scala 326:30] + node _T_3484 = bits(_T_3471, 2, 2) @[el2_lib.scala 327:36] + _T_3475[1] <= _T_3484 @[el2_lib.scala 327:30] + node _T_3485 = bits(_T_3471, 3, 3) @[el2_lib.scala 325:36] + _T_3473[2] <= _T_3485 @[el2_lib.scala 325:30] + node _T_3486 = bits(_T_3471, 3, 3) @[el2_lib.scala 326:36] + _T_3474[2] <= _T_3486 @[el2_lib.scala 326:30] + node _T_3487 = bits(_T_3471, 3, 3) @[el2_lib.scala 327:36] + _T_3475[2] <= _T_3487 @[el2_lib.scala 327:30] + node _T_3488 = bits(_T_3471, 4, 4) @[el2_lib.scala 325:36] + _T_3473[3] <= _T_3488 @[el2_lib.scala 325:30] + node _T_3489 = bits(_T_3471, 4, 4) @[el2_lib.scala 328:36] + _T_3476[0] <= _T_3489 @[el2_lib.scala 328:30] + node _T_3490 = bits(_T_3471, 5, 5) @[el2_lib.scala 326:36] + _T_3474[3] <= _T_3490 @[el2_lib.scala 326:30] + node _T_3491 = bits(_T_3471, 5, 5) @[el2_lib.scala 328:36] + _T_3476[1] <= _T_3491 @[el2_lib.scala 328:30] + node _T_3492 = bits(_T_3471, 6, 6) @[el2_lib.scala 325:36] + _T_3473[4] <= _T_3492 @[el2_lib.scala 325:30] + node _T_3493 = bits(_T_3471, 6, 6) @[el2_lib.scala 326:36] + _T_3474[4] <= _T_3493 @[el2_lib.scala 326:30] + node _T_3494 = bits(_T_3471, 6, 6) @[el2_lib.scala 328:36] + _T_3476[2] <= _T_3494 @[el2_lib.scala 328:30] + node _T_3495 = bits(_T_3471, 7, 7) @[el2_lib.scala 327:36] + _T_3475[3] <= _T_3495 @[el2_lib.scala 327:30] + node _T_3496 = bits(_T_3471, 7, 7) @[el2_lib.scala 328:36] + _T_3476[3] <= _T_3496 @[el2_lib.scala 328:30] + node _T_3497 = bits(_T_3471, 8, 8) @[el2_lib.scala 325:36] + _T_3473[5] <= _T_3497 @[el2_lib.scala 325:30] + node _T_3498 = bits(_T_3471, 8, 8) @[el2_lib.scala 327:36] + _T_3475[4] <= _T_3498 @[el2_lib.scala 327:30] + node _T_3499 = bits(_T_3471, 8, 8) @[el2_lib.scala 328:36] + _T_3476[4] <= _T_3499 @[el2_lib.scala 328:30] + node _T_3500 = bits(_T_3471, 9, 9) @[el2_lib.scala 326:36] + _T_3474[5] <= _T_3500 @[el2_lib.scala 326:30] + node _T_3501 = bits(_T_3471, 9, 9) @[el2_lib.scala 327:36] + _T_3475[5] <= _T_3501 @[el2_lib.scala 327:30] + node _T_3502 = bits(_T_3471, 9, 9) @[el2_lib.scala 328:36] + _T_3476[5] <= _T_3502 @[el2_lib.scala 328:30] + node _T_3503 = bits(_T_3471, 10, 10) @[el2_lib.scala 325:36] + _T_3473[6] <= _T_3503 @[el2_lib.scala 325:30] + node _T_3504 = bits(_T_3471, 10, 10) @[el2_lib.scala 326:36] + _T_3474[6] <= _T_3504 @[el2_lib.scala 326:30] + node _T_3505 = bits(_T_3471, 10, 10) @[el2_lib.scala 327:36] + _T_3475[6] <= _T_3505 @[el2_lib.scala 327:30] + node _T_3506 = bits(_T_3471, 10, 10) @[el2_lib.scala 328:36] + _T_3476[6] <= _T_3506 @[el2_lib.scala 328:30] + node _T_3507 = bits(_T_3471, 11, 11) @[el2_lib.scala 325:36] + _T_3473[7] <= _T_3507 @[el2_lib.scala 325:30] + node _T_3508 = bits(_T_3471, 11, 11) @[el2_lib.scala 329:36] + _T_3477[0] <= _T_3508 @[el2_lib.scala 329:30] + node _T_3509 = bits(_T_3471, 12, 12) @[el2_lib.scala 326:36] + _T_3474[7] <= _T_3509 @[el2_lib.scala 326:30] + node _T_3510 = bits(_T_3471, 12, 12) @[el2_lib.scala 329:36] + _T_3477[1] <= _T_3510 @[el2_lib.scala 329:30] + node _T_3511 = bits(_T_3471, 13, 13) @[el2_lib.scala 325:36] + _T_3473[8] <= _T_3511 @[el2_lib.scala 325:30] + node _T_3512 = bits(_T_3471, 13, 13) @[el2_lib.scala 326:36] + _T_3474[8] <= _T_3512 @[el2_lib.scala 326:30] + node _T_3513 = bits(_T_3471, 13, 13) @[el2_lib.scala 329:36] + _T_3477[2] <= _T_3513 @[el2_lib.scala 329:30] + node _T_3514 = bits(_T_3471, 14, 14) @[el2_lib.scala 327:36] + _T_3475[7] <= _T_3514 @[el2_lib.scala 327:30] + node _T_3515 = bits(_T_3471, 14, 14) @[el2_lib.scala 329:36] + _T_3477[3] <= _T_3515 @[el2_lib.scala 329:30] + node _T_3516 = bits(_T_3471, 15, 15) @[el2_lib.scala 325:36] + _T_3473[9] <= _T_3516 @[el2_lib.scala 325:30] + node _T_3517 = bits(_T_3471, 15, 15) @[el2_lib.scala 327:36] + _T_3475[8] <= _T_3517 @[el2_lib.scala 327:30] + node _T_3518 = bits(_T_3471, 15, 15) @[el2_lib.scala 329:36] + _T_3477[4] <= _T_3518 @[el2_lib.scala 329:30] + node _T_3519 = bits(_T_3471, 16, 16) @[el2_lib.scala 326:36] + _T_3474[9] <= _T_3519 @[el2_lib.scala 326:30] + node _T_3520 = bits(_T_3471, 16, 16) @[el2_lib.scala 327:36] + _T_3475[9] <= _T_3520 @[el2_lib.scala 327:30] + node _T_3521 = bits(_T_3471, 16, 16) @[el2_lib.scala 329:36] + _T_3477[5] <= _T_3521 @[el2_lib.scala 329:30] + node _T_3522 = bits(_T_3471, 17, 17) @[el2_lib.scala 325:36] + _T_3473[10] <= _T_3522 @[el2_lib.scala 325:30] + node _T_3523 = bits(_T_3471, 17, 17) @[el2_lib.scala 326:36] + _T_3474[10] <= _T_3523 @[el2_lib.scala 326:30] + node _T_3524 = bits(_T_3471, 17, 17) @[el2_lib.scala 327:36] + _T_3475[10] <= _T_3524 @[el2_lib.scala 327:30] + node _T_3525 = bits(_T_3471, 17, 17) @[el2_lib.scala 329:36] + _T_3477[6] <= _T_3525 @[el2_lib.scala 329:30] + node _T_3526 = bits(_T_3471, 18, 18) @[el2_lib.scala 328:36] + _T_3476[7] <= _T_3526 @[el2_lib.scala 328:30] + node _T_3527 = bits(_T_3471, 18, 18) @[el2_lib.scala 329:36] + _T_3477[7] <= _T_3527 @[el2_lib.scala 329:30] + node _T_3528 = bits(_T_3471, 19, 19) @[el2_lib.scala 325:36] + _T_3473[11] <= _T_3528 @[el2_lib.scala 325:30] + node _T_3529 = bits(_T_3471, 19, 19) @[el2_lib.scala 328:36] + _T_3476[8] <= _T_3529 @[el2_lib.scala 328:30] + node _T_3530 = bits(_T_3471, 19, 19) @[el2_lib.scala 329:36] + _T_3477[8] <= _T_3530 @[el2_lib.scala 329:30] + node _T_3531 = bits(_T_3471, 20, 20) @[el2_lib.scala 326:36] + _T_3474[11] <= _T_3531 @[el2_lib.scala 326:30] + node _T_3532 = bits(_T_3471, 20, 20) @[el2_lib.scala 328:36] + _T_3476[9] <= _T_3532 @[el2_lib.scala 328:30] + node _T_3533 = bits(_T_3471, 20, 20) @[el2_lib.scala 329:36] + _T_3477[9] <= _T_3533 @[el2_lib.scala 329:30] + node _T_3534 = bits(_T_3471, 21, 21) @[el2_lib.scala 325:36] + _T_3473[12] <= _T_3534 @[el2_lib.scala 325:30] + node _T_3535 = bits(_T_3471, 21, 21) @[el2_lib.scala 326:36] + _T_3474[12] <= _T_3535 @[el2_lib.scala 326:30] + node _T_3536 = bits(_T_3471, 21, 21) @[el2_lib.scala 328:36] + _T_3476[10] <= _T_3536 @[el2_lib.scala 328:30] + node _T_3537 = bits(_T_3471, 21, 21) @[el2_lib.scala 329:36] + _T_3477[10] <= _T_3537 @[el2_lib.scala 329:30] + node _T_3538 = bits(_T_3471, 22, 22) @[el2_lib.scala 327:36] + _T_3475[11] <= _T_3538 @[el2_lib.scala 327:30] + node _T_3539 = bits(_T_3471, 22, 22) @[el2_lib.scala 328:36] + _T_3476[11] <= _T_3539 @[el2_lib.scala 328:30] + node _T_3540 = bits(_T_3471, 22, 22) @[el2_lib.scala 329:36] + _T_3477[11] <= _T_3540 @[el2_lib.scala 329:30] + node _T_3541 = bits(_T_3471, 23, 23) @[el2_lib.scala 325:36] + _T_3473[13] <= _T_3541 @[el2_lib.scala 325:30] + node _T_3542 = bits(_T_3471, 23, 23) @[el2_lib.scala 327:36] + _T_3475[12] <= _T_3542 @[el2_lib.scala 327:30] + node _T_3543 = bits(_T_3471, 23, 23) @[el2_lib.scala 328:36] + _T_3476[12] <= _T_3543 @[el2_lib.scala 328:30] + node _T_3544 = bits(_T_3471, 23, 23) @[el2_lib.scala 329:36] + _T_3477[12] <= _T_3544 @[el2_lib.scala 329:30] + node _T_3545 = bits(_T_3471, 24, 24) @[el2_lib.scala 326:36] + _T_3474[13] <= _T_3545 @[el2_lib.scala 326:30] + node _T_3546 = bits(_T_3471, 24, 24) @[el2_lib.scala 327:36] + _T_3475[13] <= _T_3546 @[el2_lib.scala 327:30] + node _T_3547 = bits(_T_3471, 24, 24) @[el2_lib.scala 328:36] + _T_3476[13] <= _T_3547 @[el2_lib.scala 328:30] + node _T_3548 = bits(_T_3471, 24, 24) @[el2_lib.scala 329:36] + _T_3477[13] <= _T_3548 @[el2_lib.scala 329:30] + node _T_3549 = bits(_T_3471, 25, 25) @[el2_lib.scala 325:36] + _T_3473[14] <= _T_3549 @[el2_lib.scala 325:30] + node _T_3550 = bits(_T_3471, 25, 25) @[el2_lib.scala 326:36] + _T_3474[14] <= _T_3550 @[el2_lib.scala 326:30] + node _T_3551 = bits(_T_3471, 25, 25) @[el2_lib.scala 327:36] + _T_3475[14] <= _T_3551 @[el2_lib.scala 327:30] + node _T_3552 = bits(_T_3471, 25, 25) @[el2_lib.scala 328:36] + _T_3476[14] <= _T_3552 @[el2_lib.scala 328:30] + node _T_3553 = bits(_T_3471, 25, 25) @[el2_lib.scala 329:36] + _T_3477[14] <= _T_3553 @[el2_lib.scala 329:30] + node _T_3554 = bits(_T_3471, 26, 26) @[el2_lib.scala 325:36] + _T_3473[15] <= _T_3554 @[el2_lib.scala 325:30] + node _T_3555 = bits(_T_3471, 26, 26) @[el2_lib.scala 330:36] + _T_3478[0] <= _T_3555 @[el2_lib.scala 330:30] + node _T_3556 = bits(_T_3471, 27, 27) @[el2_lib.scala 326:36] + _T_3474[15] <= _T_3556 @[el2_lib.scala 326:30] + node _T_3557 = bits(_T_3471, 27, 27) @[el2_lib.scala 330:36] + _T_3478[1] <= _T_3557 @[el2_lib.scala 330:30] + node _T_3558 = bits(_T_3471, 28, 28) @[el2_lib.scala 325:36] + _T_3473[16] <= _T_3558 @[el2_lib.scala 325:30] + node _T_3559 = bits(_T_3471, 28, 28) @[el2_lib.scala 326:36] + _T_3474[16] <= _T_3559 @[el2_lib.scala 326:30] + node _T_3560 = bits(_T_3471, 28, 28) @[el2_lib.scala 330:36] + _T_3478[2] <= _T_3560 @[el2_lib.scala 330:30] + node _T_3561 = bits(_T_3471, 29, 29) @[el2_lib.scala 327:36] + _T_3475[15] <= _T_3561 @[el2_lib.scala 327:30] + node _T_3562 = bits(_T_3471, 29, 29) @[el2_lib.scala 330:36] + _T_3478[3] <= _T_3562 @[el2_lib.scala 330:30] + node _T_3563 = bits(_T_3471, 30, 30) @[el2_lib.scala 325:36] + _T_3473[17] <= _T_3563 @[el2_lib.scala 325:30] + node _T_3564 = bits(_T_3471, 30, 30) @[el2_lib.scala 327:36] + _T_3475[16] <= _T_3564 @[el2_lib.scala 327:30] + node _T_3565 = bits(_T_3471, 30, 30) @[el2_lib.scala 330:36] + _T_3478[4] <= _T_3565 @[el2_lib.scala 330:30] + node _T_3566 = bits(_T_3471, 31, 31) @[el2_lib.scala 326:36] + _T_3474[17] <= _T_3566 @[el2_lib.scala 326:30] + node _T_3567 = bits(_T_3471, 31, 31) @[el2_lib.scala 327:36] + _T_3475[17] <= _T_3567 @[el2_lib.scala 327:30] + node _T_3568 = bits(_T_3471, 31, 31) @[el2_lib.scala 330:36] + _T_3478[5] <= _T_3568 @[el2_lib.scala 330:30] + node _T_3569 = xorr(_T_3471) @[el2_lib.scala 333:30] + node _T_3570 = xorr(_T_3472) @[el2_lib.scala 333:44] + node _T_3571 = xor(_T_3569, _T_3570) @[el2_lib.scala 333:35] + node _T_3572 = not(UInt<1>("h00")) @[el2_lib.scala 333:52] + node _T_3573 = and(_T_3571, _T_3572) @[el2_lib.scala 333:50] + node _T_3574 = bits(_T_3472, 5, 5) @[el2_lib.scala 333:68] + node _T_3575 = cat(_T_3478[2], _T_3478[1]) @[el2_lib.scala 333:76] + node _T_3576 = cat(_T_3575, _T_3478[0]) @[el2_lib.scala 333:76] + node _T_3577 = cat(_T_3478[5], _T_3478[4]) @[el2_lib.scala 333:76] + node _T_3578 = cat(_T_3577, _T_3478[3]) @[el2_lib.scala 333:76] + node _T_3579 = cat(_T_3578, _T_3576) @[el2_lib.scala 333:76] + node _T_3580 = xorr(_T_3579) @[el2_lib.scala 333:83] + node _T_3581 = xor(_T_3574, _T_3580) @[el2_lib.scala 333:71] + node _T_3582 = bits(_T_3472, 4, 4) @[el2_lib.scala 333:95] + node _T_3583 = cat(_T_3477[2], _T_3477[1]) @[el2_lib.scala 333:103] + node _T_3584 = cat(_T_3583, _T_3477[0]) @[el2_lib.scala 333:103] + node _T_3585 = cat(_T_3477[4], _T_3477[3]) @[el2_lib.scala 333:103] + node _T_3586 = cat(_T_3477[6], _T_3477[5]) @[el2_lib.scala 333:103] + node _T_3587 = cat(_T_3586, _T_3585) @[el2_lib.scala 333:103] + node _T_3588 = cat(_T_3587, _T_3584) @[el2_lib.scala 333:103] + node _T_3589 = cat(_T_3477[8], _T_3477[7]) @[el2_lib.scala 333:103] + node _T_3590 = cat(_T_3477[10], _T_3477[9]) @[el2_lib.scala 333:103] + node _T_3591 = cat(_T_3590, _T_3589) @[el2_lib.scala 333:103] + node _T_3592 = cat(_T_3477[12], _T_3477[11]) @[el2_lib.scala 333:103] + node _T_3593 = cat(_T_3477[14], _T_3477[13]) @[el2_lib.scala 333:103] + node _T_3594 = cat(_T_3593, _T_3592) @[el2_lib.scala 333:103] + node _T_3595 = cat(_T_3594, _T_3591) @[el2_lib.scala 333:103] + node _T_3596 = cat(_T_3595, _T_3588) @[el2_lib.scala 333:103] + node _T_3597 = xorr(_T_3596) @[el2_lib.scala 333:110] + node _T_3598 = xor(_T_3582, _T_3597) @[el2_lib.scala 333:98] + node _T_3599 = bits(_T_3472, 3, 3) @[el2_lib.scala 333:122] + node _T_3600 = cat(_T_3476[2], _T_3476[1]) @[el2_lib.scala 333:130] + node _T_3601 = cat(_T_3600, _T_3476[0]) @[el2_lib.scala 333:130] + node _T_3602 = cat(_T_3476[4], _T_3476[3]) @[el2_lib.scala 333:130] + node _T_3603 = cat(_T_3476[6], _T_3476[5]) @[el2_lib.scala 333:130] + node _T_3604 = cat(_T_3603, _T_3602) @[el2_lib.scala 333:130] + node _T_3605 = cat(_T_3604, _T_3601) @[el2_lib.scala 333:130] + node _T_3606 = cat(_T_3476[8], _T_3476[7]) @[el2_lib.scala 333:130] + node _T_3607 = cat(_T_3476[10], _T_3476[9]) @[el2_lib.scala 333:130] + node _T_3608 = cat(_T_3607, _T_3606) @[el2_lib.scala 333:130] + node _T_3609 = cat(_T_3476[12], _T_3476[11]) @[el2_lib.scala 333:130] + node _T_3610 = cat(_T_3476[14], _T_3476[13]) @[el2_lib.scala 333:130] + node _T_3611 = cat(_T_3610, _T_3609) @[el2_lib.scala 333:130] + node _T_3612 = cat(_T_3611, _T_3608) @[el2_lib.scala 333:130] + node _T_3613 = cat(_T_3612, _T_3605) @[el2_lib.scala 333:130] + node _T_3614 = xorr(_T_3613) @[el2_lib.scala 333:137] + node _T_3615 = xor(_T_3599, _T_3614) @[el2_lib.scala 333:125] + node _T_3616 = bits(_T_3472, 2, 2) @[el2_lib.scala 333:149] + node _T_3617 = cat(_T_3475[1], _T_3475[0]) @[el2_lib.scala 333:157] + node _T_3618 = cat(_T_3475[3], _T_3475[2]) @[el2_lib.scala 333:157] + node _T_3619 = cat(_T_3618, _T_3617) @[el2_lib.scala 333:157] + node _T_3620 = cat(_T_3475[5], _T_3475[4]) @[el2_lib.scala 333:157] + node _T_3621 = cat(_T_3475[8], _T_3475[7]) @[el2_lib.scala 333:157] + node _T_3622 = cat(_T_3621, _T_3475[6]) @[el2_lib.scala 333:157] + node _T_3623 = cat(_T_3622, _T_3620) @[el2_lib.scala 333:157] + node _T_3624 = cat(_T_3623, _T_3619) @[el2_lib.scala 333:157] + node _T_3625 = cat(_T_3475[10], _T_3475[9]) @[el2_lib.scala 333:157] + node _T_3626 = cat(_T_3475[12], _T_3475[11]) @[el2_lib.scala 333:157] + node _T_3627 = cat(_T_3626, _T_3625) @[el2_lib.scala 333:157] + node _T_3628 = cat(_T_3475[14], _T_3475[13]) @[el2_lib.scala 333:157] + node _T_3629 = cat(_T_3475[17], _T_3475[16]) @[el2_lib.scala 333:157] + node _T_3630 = cat(_T_3629, _T_3475[15]) @[el2_lib.scala 333:157] + node _T_3631 = cat(_T_3630, _T_3628) @[el2_lib.scala 333:157] + node _T_3632 = cat(_T_3631, _T_3627) @[el2_lib.scala 333:157] + node _T_3633 = cat(_T_3632, _T_3624) @[el2_lib.scala 333:157] + node _T_3634 = xorr(_T_3633) @[el2_lib.scala 333:164] + node _T_3635 = xor(_T_3616, _T_3634) @[el2_lib.scala 333:152] + node _T_3636 = bits(_T_3472, 1, 1) @[el2_lib.scala 333:176] + node _T_3637 = cat(_T_3474[1], _T_3474[0]) @[el2_lib.scala 333:184] + node _T_3638 = cat(_T_3474[3], _T_3474[2]) @[el2_lib.scala 333:184] + node _T_3639 = cat(_T_3638, _T_3637) @[el2_lib.scala 333:184] + node _T_3640 = cat(_T_3474[5], _T_3474[4]) @[el2_lib.scala 333:184] + node _T_3641 = cat(_T_3474[8], _T_3474[7]) @[el2_lib.scala 333:184] + node _T_3642 = cat(_T_3641, _T_3474[6]) @[el2_lib.scala 333:184] + node _T_3643 = cat(_T_3642, _T_3640) @[el2_lib.scala 333:184] + node _T_3644 = cat(_T_3643, _T_3639) @[el2_lib.scala 333:184] + node _T_3645 = cat(_T_3474[10], _T_3474[9]) @[el2_lib.scala 333:184] + node _T_3646 = cat(_T_3474[12], _T_3474[11]) @[el2_lib.scala 333:184] + node _T_3647 = cat(_T_3646, _T_3645) @[el2_lib.scala 333:184] + node _T_3648 = cat(_T_3474[14], _T_3474[13]) @[el2_lib.scala 333:184] + node _T_3649 = cat(_T_3474[17], _T_3474[16]) @[el2_lib.scala 333:184] + node _T_3650 = cat(_T_3649, _T_3474[15]) @[el2_lib.scala 333:184] + node _T_3651 = cat(_T_3650, _T_3648) @[el2_lib.scala 333:184] + node _T_3652 = cat(_T_3651, _T_3647) @[el2_lib.scala 333:184] + node _T_3653 = cat(_T_3652, _T_3644) @[el2_lib.scala 333:184] + node _T_3654 = xorr(_T_3653) @[el2_lib.scala 333:191] + node _T_3655 = xor(_T_3636, _T_3654) @[el2_lib.scala 333:179] + node _T_3656 = bits(_T_3472, 0, 0) @[el2_lib.scala 333:203] + node _T_3657 = cat(_T_3473[1], _T_3473[0]) @[el2_lib.scala 333:211] + node _T_3658 = cat(_T_3473[3], _T_3473[2]) @[el2_lib.scala 333:211] + node _T_3659 = cat(_T_3658, _T_3657) @[el2_lib.scala 333:211] + node _T_3660 = cat(_T_3473[5], _T_3473[4]) @[el2_lib.scala 333:211] + node _T_3661 = cat(_T_3473[8], _T_3473[7]) @[el2_lib.scala 333:211] + node _T_3662 = cat(_T_3661, _T_3473[6]) @[el2_lib.scala 333:211] + node _T_3663 = cat(_T_3662, _T_3660) @[el2_lib.scala 333:211] + node _T_3664 = cat(_T_3663, _T_3659) @[el2_lib.scala 333:211] + node _T_3665 = cat(_T_3473[10], _T_3473[9]) @[el2_lib.scala 333:211] + node _T_3666 = cat(_T_3473[12], _T_3473[11]) @[el2_lib.scala 333:211] + node _T_3667 = cat(_T_3666, _T_3665) @[el2_lib.scala 333:211] + node _T_3668 = cat(_T_3473[14], _T_3473[13]) @[el2_lib.scala 333:211] + node _T_3669 = cat(_T_3473[17], _T_3473[16]) @[el2_lib.scala 333:211] + node _T_3670 = cat(_T_3669, _T_3473[15]) @[el2_lib.scala 333:211] + node _T_3671 = cat(_T_3670, _T_3668) @[el2_lib.scala 333:211] + node _T_3672 = cat(_T_3671, _T_3667) @[el2_lib.scala 333:211] + node _T_3673 = cat(_T_3672, _T_3664) @[el2_lib.scala 333:211] + node _T_3674 = xorr(_T_3673) @[el2_lib.scala 333:218] + node _T_3675 = xor(_T_3656, _T_3674) @[el2_lib.scala 333:206] + node _T_3676 = cat(_T_3635, _T_3655) @[Cat.scala 29:58] + node _T_3677 = cat(_T_3676, _T_3675) @[Cat.scala 29:58] + node _T_3678 = cat(_T_3598, _T_3615) @[Cat.scala 29:58] + node _T_3679 = cat(_T_3573, _T_3581) @[Cat.scala 29:58] + node _T_3680 = cat(_T_3679, _T_3678) @[Cat.scala 29:58] + node _T_3681 = cat(_T_3680, _T_3677) @[Cat.scala 29:58] + node _T_3682 = neq(_T_3681, UInt<1>("h00")) @[el2_lib.scala 334:44] + node _T_3683 = and(_T_3470, _T_3682) @[el2_lib.scala 334:32] + node _T_3684 = bits(_T_3681, 6, 6) @[el2_lib.scala 334:64] + node _T_3685 = and(_T_3683, _T_3684) @[el2_lib.scala 334:53] + node _T_3686 = neq(_T_3681, UInt<1>("h00")) @[el2_lib.scala 335:44] + node _T_3687 = and(_T_3470, _T_3686) @[el2_lib.scala 335:32] + node _T_3688 = bits(_T_3681, 6, 6) @[el2_lib.scala 335:65] + node _T_3689 = not(_T_3688) @[el2_lib.scala 335:55] + node _T_3690 = and(_T_3687, _T_3689) @[el2_lib.scala 335:53] + wire _T_3691 : UInt<1>[39] @[el2_lib.scala 336:26] + node _T_3692 = bits(_T_3681, 5, 0) @[el2_lib.scala 339:35] + node _T_3693 = eq(_T_3692, UInt<1>("h01")) @[el2_lib.scala 339:41] + _T_3691[0] <= _T_3693 @[el2_lib.scala 339:23] + node _T_3694 = bits(_T_3681, 5, 0) @[el2_lib.scala 339:35] + node _T_3695 = eq(_T_3694, UInt<2>("h02")) @[el2_lib.scala 339:41] + _T_3691[1] <= _T_3695 @[el2_lib.scala 339:23] + node _T_3696 = bits(_T_3681, 5, 0) @[el2_lib.scala 339:35] + node _T_3697 = eq(_T_3696, UInt<2>("h03")) @[el2_lib.scala 339:41] + _T_3691[2] <= _T_3697 @[el2_lib.scala 339:23] + node _T_3698 = bits(_T_3681, 5, 0) @[el2_lib.scala 339:35] + node _T_3699 = eq(_T_3698, UInt<3>("h04")) @[el2_lib.scala 339:41] + _T_3691[3] <= _T_3699 @[el2_lib.scala 339:23] + node _T_3700 = bits(_T_3681, 5, 0) @[el2_lib.scala 339:35] + node _T_3701 = eq(_T_3700, UInt<3>("h05")) @[el2_lib.scala 339:41] + _T_3691[4] <= _T_3701 @[el2_lib.scala 339:23] + node _T_3702 = bits(_T_3681, 5, 0) @[el2_lib.scala 339:35] + node _T_3703 = eq(_T_3702, UInt<3>("h06")) @[el2_lib.scala 339:41] + _T_3691[5] <= _T_3703 @[el2_lib.scala 339:23] + node _T_3704 = bits(_T_3681, 5, 0) @[el2_lib.scala 339:35] + node _T_3705 = eq(_T_3704, UInt<3>("h07")) @[el2_lib.scala 339:41] + _T_3691[6] <= _T_3705 @[el2_lib.scala 339:23] + node _T_3706 = bits(_T_3681, 5, 0) @[el2_lib.scala 339:35] + node _T_3707 = eq(_T_3706, UInt<4>("h08")) @[el2_lib.scala 339:41] + _T_3691[7] <= _T_3707 @[el2_lib.scala 339:23] + node _T_3708 = bits(_T_3681, 5, 0) @[el2_lib.scala 339:35] + node _T_3709 = eq(_T_3708, UInt<4>("h09")) @[el2_lib.scala 339:41] + _T_3691[8] <= _T_3709 @[el2_lib.scala 339:23] + node _T_3710 = bits(_T_3681, 5, 0) @[el2_lib.scala 339:35] + node _T_3711 = eq(_T_3710, UInt<4>("h0a")) @[el2_lib.scala 339:41] + _T_3691[9] <= _T_3711 @[el2_lib.scala 339:23] + node _T_3712 = bits(_T_3681, 5, 0) @[el2_lib.scala 339:35] + node _T_3713 = eq(_T_3712, UInt<4>("h0b")) @[el2_lib.scala 339:41] + _T_3691[10] <= _T_3713 @[el2_lib.scala 339:23] + node _T_3714 = bits(_T_3681, 5, 0) @[el2_lib.scala 339:35] + node _T_3715 = eq(_T_3714, UInt<4>("h0c")) @[el2_lib.scala 339:41] + _T_3691[11] <= _T_3715 @[el2_lib.scala 339:23] + node _T_3716 = bits(_T_3681, 5, 0) @[el2_lib.scala 339:35] + node _T_3717 = eq(_T_3716, UInt<4>("h0d")) @[el2_lib.scala 339:41] + _T_3691[12] <= _T_3717 @[el2_lib.scala 339:23] + node _T_3718 = bits(_T_3681, 5, 0) @[el2_lib.scala 339:35] + node _T_3719 = eq(_T_3718, UInt<4>("h0e")) @[el2_lib.scala 339:41] + _T_3691[13] <= _T_3719 @[el2_lib.scala 339:23] + node _T_3720 = bits(_T_3681, 5, 0) @[el2_lib.scala 339:35] + node _T_3721 = eq(_T_3720, UInt<4>("h0f")) @[el2_lib.scala 339:41] + _T_3691[14] <= _T_3721 @[el2_lib.scala 339:23] + node _T_3722 = bits(_T_3681, 5, 0) @[el2_lib.scala 339:35] + node _T_3723 = eq(_T_3722, UInt<5>("h010")) @[el2_lib.scala 339:41] + _T_3691[15] <= _T_3723 @[el2_lib.scala 339:23] + node _T_3724 = bits(_T_3681, 5, 0) @[el2_lib.scala 339:35] + node _T_3725 = eq(_T_3724, UInt<5>("h011")) @[el2_lib.scala 339:41] + _T_3691[16] <= _T_3725 @[el2_lib.scala 339:23] + node _T_3726 = bits(_T_3681, 5, 0) @[el2_lib.scala 339:35] + node _T_3727 = eq(_T_3726, UInt<5>("h012")) @[el2_lib.scala 339:41] + _T_3691[17] <= _T_3727 @[el2_lib.scala 339:23] + node _T_3728 = bits(_T_3681, 5, 0) @[el2_lib.scala 339:35] + node _T_3729 = eq(_T_3728, UInt<5>("h013")) @[el2_lib.scala 339:41] + _T_3691[18] <= _T_3729 @[el2_lib.scala 339:23] + node _T_3730 = bits(_T_3681, 5, 0) @[el2_lib.scala 339:35] + node _T_3731 = eq(_T_3730, UInt<5>("h014")) @[el2_lib.scala 339:41] + _T_3691[19] <= _T_3731 @[el2_lib.scala 339:23] + node _T_3732 = bits(_T_3681, 5, 0) @[el2_lib.scala 339:35] + node _T_3733 = eq(_T_3732, UInt<5>("h015")) @[el2_lib.scala 339:41] + _T_3691[20] <= _T_3733 @[el2_lib.scala 339:23] + node _T_3734 = bits(_T_3681, 5, 0) @[el2_lib.scala 339:35] + node _T_3735 = eq(_T_3734, UInt<5>("h016")) @[el2_lib.scala 339:41] + _T_3691[21] <= _T_3735 @[el2_lib.scala 339:23] + node _T_3736 = bits(_T_3681, 5, 0) @[el2_lib.scala 339:35] + node _T_3737 = eq(_T_3736, UInt<5>("h017")) @[el2_lib.scala 339:41] + _T_3691[22] <= _T_3737 @[el2_lib.scala 339:23] + node _T_3738 = bits(_T_3681, 5, 0) @[el2_lib.scala 339:35] + node _T_3739 = eq(_T_3738, UInt<5>("h018")) @[el2_lib.scala 339:41] + _T_3691[23] <= _T_3739 @[el2_lib.scala 339:23] + node _T_3740 = bits(_T_3681, 5, 0) @[el2_lib.scala 339:35] + node _T_3741 = eq(_T_3740, UInt<5>("h019")) @[el2_lib.scala 339:41] + _T_3691[24] <= _T_3741 @[el2_lib.scala 339:23] + node _T_3742 = bits(_T_3681, 5, 0) @[el2_lib.scala 339:35] + node _T_3743 = eq(_T_3742, UInt<5>("h01a")) @[el2_lib.scala 339:41] + _T_3691[25] <= _T_3743 @[el2_lib.scala 339:23] + node _T_3744 = bits(_T_3681, 5, 0) @[el2_lib.scala 339:35] + node _T_3745 = eq(_T_3744, UInt<5>("h01b")) @[el2_lib.scala 339:41] + _T_3691[26] <= _T_3745 @[el2_lib.scala 339:23] + node _T_3746 = bits(_T_3681, 5, 0) @[el2_lib.scala 339:35] + node _T_3747 = eq(_T_3746, UInt<5>("h01c")) @[el2_lib.scala 339:41] + _T_3691[27] <= _T_3747 @[el2_lib.scala 339:23] + node _T_3748 = bits(_T_3681, 5, 0) @[el2_lib.scala 339:35] + node _T_3749 = eq(_T_3748, UInt<5>("h01d")) @[el2_lib.scala 339:41] + _T_3691[28] <= _T_3749 @[el2_lib.scala 339:23] + node _T_3750 = bits(_T_3681, 5, 0) @[el2_lib.scala 339:35] + node _T_3751 = eq(_T_3750, UInt<5>("h01e")) @[el2_lib.scala 339:41] + _T_3691[29] <= _T_3751 @[el2_lib.scala 339:23] + node _T_3752 = bits(_T_3681, 5, 0) @[el2_lib.scala 339:35] + node _T_3753 = eq(_T_3752, UInt<5>("h01f")) @[el2_lib.scala 339:41] + _T_3691[30] <= _T_3753 @[el2_lib.scala 339:23] + node _T_3754 = bits(_T_3681, 5, 0) @[el2_lib.scala 339:35] + node _T_3755 = eq(_T_3754, UInt<6>("h020")) @[el2_lib.scala 339:41] + _T_3691[31] <= _T_3755 @[el2_lib.scala 339:23] + node _T_3756 = bits(_T_3681, 5, 0) @[el2_lib.scala 339:35] + node _T_3757 = eq(_T_3756, UInt<6>("h021")) @[el2_lib.scala 339:41] + _T_3691[32] <= _T_3757 @[el2_lib.scala 339:23] + node _T_3758 = bits(_T_3681, 5, 0) @[el2_lib.scala 339:35] + node _T_3759 = eq(_T_3758, UInt<6>("h022")) @[el2_lib.scala 339:41] + _T_3691[33] <= _T_3759 @[el2_lib.scala 339:23] + node _T_3760 = bits(_T_3681, 5, 0) @[el2_lib.scala 339:35] + node _T_3761 = eq(_T_3760, UInt<6>("h023")) @[el2_lib.scala 339:41] + _T_3691[34] <= _T_3761 @[el2_lib.scala 339:23] + node _T_3762 = bits(_T_3681, 5, 0) @[el2_lib.scala 339:35] + node _T_3763 = eq(_T_3762, UInt<6>("h024")) @[el2_lib.scala 339:41] + _T_3691[35] <= _T_3763 @[el2_lib.scala 339:23] + node _T_3764 = bits(_T_3681, 5, 0) @[el2_lib.scala 339:35] + node _T_3765 = eq(_T_3764, UInt<6>("h025")) @[el2_lib.scala 339:41] + _T_3691[36] <= _T_3765 @[el2_lib.scala 339:23] + node _T_3766 = bits(_T_3681, 5, 0) @[el2_lib.scala 339:35] + node _T_3767 = eq(_T_3766, UInt<6>("h026")) @[el2_lib.scala 339:41] + _T_3691[37] <= _T_3767 @[el2_lib.scala 339:23] + node _T_3768 = bits(_T_3681, 5, 0) @[el2_lib.scala 339:35] + node _T_3769 = eq(_T_3768, UInt<6>("h027")) @[el2_lib.scala 339:41] + _T_3691[38] <= _T_3769 @[el2_lib.scala 339:23] + node _T_3770 = bits(_T_3472, 6, 6) @[el2_lib.scala 341:37] + node _T_3771 = bits(_T_3471, 31, 26) @[el2_lib.scala 341:45] + node _T_3772 = bits(_T_3472, 5, 5) @[el2_lib.scala 341:60] + node _T_3773 = bits(_T_3471, 25, 11) @[el2_lib.scala 341:68] + node _T_3774 = bits(_T_3472, 4, 4) @[el2_lib.scala 341:83] + node _T_3775 = bits(_T_3471, 10, 4) @[el2_lib.scala 341:91] + node _T_3776 = bits(_T_3472, 3, 3) @[el2_lib.scala 341:105] + node _T_3777 = bits(_T_3471, 3, 1) @[el2_lib.scala 341:113] + node _T_3778 = bits(_T_3472, 2, 2) @[el2_lib.scala 341:126] + node _T_3779 = bits(_T_3471, 0, 0) @[el2_lib.scala 341:134] + node _T_3780 = bits(_T_3472, 1, 0) @[el2_lib.scala 341:145] + node _T_3781 = cat(_T_3779, _T_3780) @[Cat.scala 29:58] + node _T_3782 = cat(_T_3776, _T_3777) @[Cat.scala 29:58] + node _T_3783 = cat(_T_3782, _T_3778) @[Cat.scala 29:58] + node _T_3784 = cat(_T_3783, _T_3781) @[Cat.scala 29:58] + node _T_3785 = cat(_T_3773, _T_3774) @[Cat.scala 29:58] + node _T_3786 = cat(_T_3785, _T_3775) @[Cat.scala 29:58] + node _T_3787 = cat(_T_3770, _T_3771) @[Cat.scala 29:58] + node _T_3788 = cat(_T_3787, _T_3772) @[Cat.scala 29:58] + node _T_3789 = cat(_T_3788, _T_3786) @[Cat.scala 29:58] + node _T_3790 = cat(_T_3789, _T_3784) @[Cat.scala 29:58] + node _T_3791 = bits(_T_3685, 0, 0) @[el2_lib.scala 342:49] + node _T_3792 = cat(_T_3691[1], _T_3691[0]) @[el2_lib.scala 342:69] + node _T_3793 = cat(_T_3691[3], _T_3691[2]) @[el2_lib.scala 342:69] + node _T_3794 = cat(_T_3793, _T_3792) @[el2_lib.scala 342:69] + node _T_3795 = cat(_T_3691[5], _T_3691[4]) @[el2_lib.scala 342:69] + node _T_3796 = cat(_T_3691[8], _T_3691[7]) @[el2_lib.scala 342:69] + node _T_3797 = cat(_T_3796, _T_3691[6]) @[el2_lib.scala 342:69] + node _T_3798 = cat(_T_3797, _T_3795) @[el2_lib.scala 342:69] + node _T_3799 = cat(_T_3798, _T_3794) @[el2_lib.scala 342:69] + node _T_3800 = cat(_T_3691[10], _T_3691[9]) @[el2_lib.scala 342:69] + node _T_3801 = cat(_T_3691[13], _T_3691[12]) @[el2_lib.scala 342:69] + node _T_3802 = cat(_T_3801, _T_3691[11]) @[el2_lib.scala 342:69] + node _T_3803 = cat(_T_3802, _T_3800) @[el2_lib.scala 342:69] + node _T_3804 = cat(_T_3691[15], _T_3691[14]) @[el2_lib.scala 342:69] + node _T_3805 = cat(_T_3691[18], _T_3691[17]) @[el2_lib.scala 342:69] + node _T_3806 = cat(_T_3805, _T_3691[16]) @[el2_lib.scala 342:69] + node _T_3807 = cat(_T_3806, _T_3804) @[el2_lib.scala 342:69] + node _T_3808 = cat(_T_3807, _T_3803) @[el2_lib.scala 342:69] + node _T_3809 = cat(_T_3808, _T_3799) @[el2_lib.scala 342:69] + node _T_3810 = cat(_T_3691[20], _T_3691[19]) @[el2_lib.scala 342:69] + node _T_3811 = cat(_T_3691[23], _T_3691[22]) @[el2_lib.scala 342:69] + node _T_3812 = cat(_T_3811, _T_3691[21]) @[el2_lib.scala 342:69] + node _T_3813 = cat(_T_3812, _T_3810) @[el2_lib.scala 342:69] + node _T_3814 = cat(_T_3691[25], _T_3691[24]) @[el2_lib.scala 342:69] + node _T_3815 = cat(_T_3691[28], _T_3691[27]) @[el2_lib.scala 342:69] + node _T_3816 = cat(_T_3815, _T_3691[26]) @[el2_lib.scala 342:69] + node _T_3817 = cat(_T_3816, _T_3814) @[el2_lib.scala 342:69] + node _T_3818 = cat(_T_3817, _T_3813) @[el2_lib.scala 342:69] + node _T_3819 = cat(_T_3691[30], _T_3691[29]) @[el2_lib.scala 342:69] + node _T_3820 = cat(_T_3691[33], _T_3691[32]) @[el2_lib.scala 342:69] + node _T_3821 = cat(_T_3820, _T_3691[31]) @[el2_lib.scala 342:69] + node _T_3822 = cat(_T_3821, _T_3819) @[el2_lib.scala 342:69] + node _T_3823 = cat(_T_3691[35], _T_3691[34]) @[el2_lib.scala 342:69] + node _T_3824 = cat(_T_3691[38], _T_3691[37]) @[el2_lib.scala 342:69] + node _T_3825 = cat(_T_3824, _T_3691[36]) @[el2_lib.scala 342:69] + node _T_3826 = cat(_T_3825, _T_3823) @[el2_lib.scala 342:69] + node _T_3827 = cat(_T_3826, _T_3822) @[el2_lib.scala 342:69] + node _T_3828 = cat(_T_3827, _T_3818) @[el2_lib.scala 342:69] + node _T_3829 = cat(_T_3828, _T_3809) @[el2_lib.scala 342:69] + node _T_3830 = xor(_T_3829, _T_3790) @[el2_lib.scala 342:76] + node _T_3831 = mux(_T_3791, _T_3830, _T_3790) @[el2_lib.scala 342:31] + node _T_3832 = bits(_T_3831, 37, 32) @[el2_lib.scala 344:37] + node _T_3833 = bits(_T_3831, 30, 16) @[el2_lib.scala 344:61] + node _T_3834 = bits(_T_3831, 14, 8) @[el2_lib.scala 344:86] + node _T_3835 = bits(_T_3831, 6, 4) @[el2_lib.scala 344:110] + node _T_3836 = bits(_T_3831, 2, 2) @[el2_lib.scala 344:133] + node _T_3837 = cat(_T_3835, _T_3836) @[Cat.scala 29:58] + node _T_3838 = cat(_T_3832, _T_3833) @[Cat.scala 29:58] + node _T_3839 = cat(_T_3838, _T_3834) @[Cat.scala 29:58] + node _T_3840 = cat(_T_3839, _T_3837) @[Cat.scala 29:58] + node _T_3841 = bits(_T_3831, 38, 38) @[el2_lib.scala 345:39] + node _T_3842 = bits(_T_3681, 6, 0) @[el2_lib.scala 345:56] + node _T_3843 = eq(_T_3842, UInt<7>("h040")) @[el2_lib.scala 345:62] + node _T_3844 = xor(_T_3841, _T_3843) @[el2_lib.scala 345:44] + node _T_3845 = bits(_T_3831, 31, 31) @[el2_lib.scala 345:102] + node _T_3846 = bits(_T_3831, 15, 15) @[el2_lib.scala 345:124] + node _T_3847 = bits(_T_3831, 7, 7) @[el2_lib.scala 345:146] + node _T_3848 = bits(_T_3831, 3, 3) @[el2_lib.scala 345:167] + node _T_3849 = bits(_T_3831, 1, 0) @[el2_lib.scala 345:188] + node _T_3850 = cat(_T_3847, _T_3848) @[Cat.scala 29:58] + node _T_3851 = cat(_T_3850, _T_3849) @[Cat.scala 29:58] + node _T_3852 = cat(_T_3844, _T_3845) @[Cat.scala 29:58] + node _T_3853 = cat(_T_3852, _T_3846) @[Cat.scala 29:58] + node _T_3854 = cat(_T_3853, _T_3851) @[Cat.scala 29:58] + wire iccm_corrected_ecc : UInt<7>[2] @[el2_ifu_mem_ctl.scala 675:32] + wire _T_3855 : UInt<7>[2] @[el2_ifu_mem_ctl.scala 676:32] + _T_3855[0] <= _T_3469 @[el2_ifu_mem_ctl.scala 676:32] + _T_3855[1] <= _T_3854 @[el2_ifu_mem_ctl.scala 676:32] + iccm_corrected_ecc[0] <= _T_3855[0] @[el2_ifu_mem_ctl.scala 676:22] + iccm_corrected_ecc[1] <= _T_3855[1] @[el2_ifu_mem_ctl.scala 676:22] + wire _T_3856 : UInt<32>[2] @[el2_ifu_mem_ctl.scala 677:33] + _T_3856[0] <= _T_3455 @[el2_ifu_mem_ctl.scala 677:33] + _T_3856[1] <= _T_3840 @[el2_ifu_mem_ctl.scala 677:33] + iccm_corrected_data[0] <= _T_3856[0] @[el2_ifu_mem_ctl.scala 677:23] + iccm_corrected_data[1] <= _T_3856[1] @[el2_ifu_mem_ctl.scala 677:23] + node _T_3857 = cat(_T_3300, _T_3685) @[Cat.scala 29:58] + iccm_single_ecc_error <= _T_3857 @[el2_ifu_mem_ctl.scala 678:25] + node _T_3858 = cat(_T_3305, _T_3690) @[Cat.scala 29:58] + iccm_double_ecc_error <= _T_3858 @[el2_ifu_mem_ctl.scala 679:25] + node _T_3859 = orr(iccm_single_ecc_error) @[el2_ifu_mem_ctl.scala 680:54] + node _T_3860 = and(_T_3859, ifc_iccm_access_f) @[el2_ifu_mem_ctl.scala 680:58] + node _T_3861 = and(_T_3860, ifc_fetch_req_f) @[el2_ifu_mem_ctl.scala 680:78] + io.iccm_rd_ecc_single_err <= _T_3861 @[el2_ifu_mem_ctl.scala 680:29] + node _T_3862 = orr(iccm_double_ecc_error) @[el2_ifu_mem_ctl.scala 681:54] + node _T_3863 = and(_T_3862, ifc_iccm_access_f) @[el2_ifu_mem_ctl.scala 681:58] + io.iccm_rd_ecc_double_err <= _T_3863 @[el2_ifu_mem_ctl.scala 681:29] + node _T_3864 = bits(iccm_single_ecc_error, 0, 0) @[el2_ifu_mem_ctl.scala 682:60] + node _T_3865 = bits(_T_3864, 0, 0) @[el2_ifu_mem_ctl.scala 682:64] + node iccm_corrected_data_f_mux = mux(_T_3865, iccm_corrected_data[0], iccm_corrected_data[1]) @[el2_ifu_mem_ctl.scala 682:38] + node _T_3866 = bits(iccm_single_ecc_error, 0, 0) @[el2_ifu_mem_ctl.scala 683:59] + node _T_3867 = bits(_T_3866, 0, 0) @[el2_ifu_mem_ctl.scala 683:63] + node iccm_corrected_ecc_f_mux = mux(_T_3867, iccm_corrected_ecc[0], iccm_corrected_ecc[1]) @[el2_ifu_mem_ctl.scala 683:37] + wire iccm_rd_ecc_single_err_ff : UInt<1> + iccm_rd_ecc_single_err_ff <= UInt<1>("h00") + node _T_3868 = eq(iccm_rd_ecc_single_err_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 685:76] + node _T_3869 = and(io.iccm_rd_ecc_single_err, _T_3868) @[el2_ifu_mem_ctl.scala 685:74] + node _T_3870 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 685:106] + node _T_3871 = and(_T_3869, _T_3870) @[el2_ifu_mem_ctl.scala 685:104] + node iccm_ecc_write_status = or(_T_3871, io.iccm_dma_sb_error) @[el2_ifu_mem_ctl.scala 685:127] + node _T_3872 = or(io.iccm_rd_ecc_single_err, iccm_rd_ecc_single_err_ff) @[el2_ifu_mem_ctl.scala 686:67] + node _T_3873 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 686:98] + node iccm_rd_ecc_single_err_hold_in = and(_T_3872, _T_3873) @[el2_ifu_mem_ctl.scala 686:96] + iccm_error_start <= io.iccm_rd_ecc_single_err @[el2_ifu_mem_ctl.scala 687:20] + wire iccm_rw_addr_f : UInt<14> + iccm_rw_addr_f <= UInt<1>("h00") + node _T_3874 = bits(iccm_single_ecc_error, 0, 0) @[el2_ifu_mem_ctl.scala 689:57] + node _T_3875 = bits(_T_3874, 0, 0) @[el2_ifu_mem_ctl.scala 689:67] + node _T_3876 = add(iccm_rw_addr_f, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 689:102] + node _T_3877 = tail(_T_3876, 1) @[el2_ifu_mem_ctl.scala 689:102] + node iccm_ecc_corr_index_in = mux(_T_3875, iccm_rw_addr_f, _T_3877) @[el2_ifu_mem_ctl.scala 689:35] + node _T_3878 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_mem_ctl.scala 690:67] + reg _T_3879 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 690:51] + _T_3879 <= _T_3878 @[el2_ifu_mem_ctl.scala 690:51] + iccm_rw_addr_f <= _T_3879 @[el2_ifu_mem_ctl.scala 690:18] + reg _T_3880 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 691:62] + _T_3880 <= iccm_rd_ecc_single_err_hold_in @[el2_ifu_mem_ctl.scala 691:62] + iccm_rd_ecc_single_err_ff <= _T_3880 @[el2_ifu_mem_ctl.scala 691:29] + node _T_3881 = cat(iccm_corrected_ecc_f_mux, iccm_corrected_data_f_mux) @[Cat.scala 29:58] + node _T_3882 = bits(iccm_ecc_write_status, 0, 0) @[el2_ifu_mem_ctl.scala 692:152] + reg _T_3883 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3882 : @[Reg.scala 28:19] + _T_3883 <= _T_3881 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + iccm_ecc_corr_data_ff <= _T_3883 @[el2_ifu_mem_ctl.scala 692:25] + node _T_3884 = bits(iccm_ecc_write_status, 0, 0) @[el2_ifu_mem_ctl.scala 693:119] + reg _T_3885 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3884 : @[Reg.scala 28:19] + _T_3885 <= iccm_ecc_corr_index_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + iccm_ecc_corr_index_ff <= _T_3885 @[el2_ifu_mem_ctl.scala 693:26] + node _T_3886 = eq(io.ifc_fetch_uncacheable_bf, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 694:41] + node _T_3887 = and(io.ifc_fetch_req_bf, _T_3886) @[el2_ifu_mem_ctl.scala 694:39] + node _T_3888 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 694:72] + node _T_3889 = and(_T_3887, _T_3888) @[el2_ifu_mem_ctl.scala 694:70] + node _T_3890 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 695:19] + node _T_3891 = eq(miss_state_en, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 695:34] + node _T_3892 = and(_T_3890, _T_3891) @[el2_ifu_mem_ctl.scala 695:32] + node _T_3893 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 696:19] + node _T_3894 = eq(miss_state_en, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 696:39] + node _T_3895 = and(_T_3893, _T_3894) @[el2_ifu_mem_ctl.scala 696:37] + node _T_3896 = or(_T_3892, _T_3895) @[el2_ifu_mem_ctl.scala 695:88] + node _T_3897 = eq(miss_state, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 697:19] + node _T_3898 = eq(miss_state_en, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 697:43] + node _T_3899 = and(_T_3897, _T_3898) @[el2_ifu_mem_ctl.scala 697:41] + node _T_3900 = or(_T_3896, _T_3899) @[el2_ifu_mem_ctl.scala 696:88] + node _T_3901 = eq(miss_state, UInt<3>("h03")) @[el2_ifu_mem_ctl.scala 698:19] + node _T_3902 = eq(miss_state_en, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 698:37] + node _T_3903 = and(_T_3901, _T_3902) @[el2_ifu_mem_ctl.scala 698:35] + node _T_3904 = or(_T_3900, _T_3903) @[el2_ifu_mem_ctl.scala 697:88] + node _T_3905 = eq(miss_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 699:19] + node _T_3906 = eq(miss_state_en, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 699:40] + node _T_3907 = and(_T_3905, _T_3906) @[el2_ifu_mem_ctl.scala 699:38] + node _T_3908 = or(_T_3904, _T_3907) @[el2_ifu_mem_ctl.scala 698:88] + node _T_3909 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 700:19] + node _T_3910 = and(_T_3909, miss_state_en) @[el2_ifu_mem_ctl.scala 700:37] + node _T_3911 = eq(miss_nxtstate, UInt<3>("h03")) @[el2_ifu_mem_ctl.scala 700:71] + node _T_3912 = and(_T_3910, _T_3911) @[el2_ifu_mem_ctl.scala 700:54] + node _T_3913 = or(_T_3908, _T_3912) @[el2_ifu_mem_ctl.scala 699:57] + node _T_3914 = eq(_T_3913, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 695:5] + node _T_3915 = and(_T_3889, _T_3914) @[el2_ifu_mem_ctl.scala 694:96] + node _T_3916 = and(io.ifc_fetch_req_bf, io.exu_flush_final) @[el2_ifu_mem_ctl.scala 701:26] + node _T_3917 = eq(io.ifc_fetch_uncacheable_bf, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 701:50] + node _T_3918 = and(_T_3916, _T_3917) @[el2_ifu_mem_ctl.scala 701:48] + node _T_3919 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 701:81] + node _T_3920 = and(_T_3918, _T_3919) @[el2_ifu_mem_ctl.scala 701:79] + node _T_3921 = or(_T_3915, _T_3920) @[el2_ifu_mem_ctl.scala 700:93] + io.ic_rd_en <= _T_3921 @[el2_ifu_mem_ctl.scala 694:15] + wire bus_ic_wr_en : UInt<2> + bus_ic_wr_en <= UInt<1>("h00") + node _T_3922 = bits(write_ic_16_bytes, 0, 0) @[Bitwise.scala 72:15] + node _T_3923 = mux(_T_3922, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_3924 = and(bus_ic_wr_en, _T_3923) @[el2_ifu_mem_ctl.scala 703:31] + io.ic_wr_en <= _T_3924 @[el2_ifu_mem_ctl.scala 703:15] + node _T_3925 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 704:59] + node _T_3926 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 704:91] + node _T_3927 = or(io.exu_flush_final, ifu_bp_hit_taken_q_f) @[el2_ifu_mem_ctl.scala 704:127] + node _T_3928 = or(_T_3927, stream_eol_f) @[el2_ifu_mem_ctl.scala 704:151] + node _T_3929 = eq(_T_3928, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 704:106] + node _T_3930 = and(_T_3926, _T_3929) @[el2_ifu_mem_ctl.scala 704:104] + node _T_3931 = or(_T_3925, _T_3930) @[el2_ifu_mem_ctl.scala 704:77] + node _T_3932 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 704:191] + node _T_3933 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 704:205] + node _T_3934 = and(_T_3932, _T_3933) @[el2_ifu_mem_ctl.scala 704:203] + node _T_3935 = eq(_T_3934, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 704:172] + node _T_3936 = and(_T_3931, _T_3935) @[el2_ifu_mem_ctl.scala 704:170] + node _T_3937 = eq(_T_3936, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 704:44] + node _T_3938 = and(write_ic_16_bytes, _T_3937) @[el2_ifu_mem_ctl.scala 704:42] + io.ic_write_stall <= _T_3938 @[el2_ifu_mem_ctl.scala 704:21] + reg _T_3939 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 705:53] + _T_3939 <= io.dec_tlu_fence_i_wb @[el2_ifu_mem_ctl.scala 705:53] + reset_all_tags <= _T_3939 @[el2_ifu_mem_ctl.scala 705:18] + node _T_3940 = eq(ifu_wr_cumulative_err_data, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 707:18] + node _T_3941 = or(reset_ic_in, reset_ic_ff) @[el2_ifu_mem_ctl.scala 707:62] + node _T_3942 = eq(_T_3941, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 707:48] + node _T_3943 = and(_T_3940, _T_3942) @[el2_ifu_mem_ctl.scala 707:46] + node _T_3944 = eq(reset_tag_valid_for_miss, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 707:79] + node ic_valid = and(_T_3943, _T_3944) @[el2_ifu_mem_ctl.scala 707:77] + node _T_3945 = or(io.ic_debug_rd_en, io.ic_debug_wr_en) @[el2_ifu_mem_ctl.scala 708:59] + node _T_3946 = and(_T_3945, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 708:80] + node _T_3947 = bits(io.ic_debug_addr, 9, 3) @[el2_ifu_mem_ctl.scala 708:121] + node _T_3948 = bits(ifu_status_wr_addr, 11, 5) @[el2_ifu_mem_ctl.scala 709:23] + node ifu_status_wr_addr_w_debug = mux(_T_3946, _T_3947, _T_3948) @[el2_ifu_mem_ctl.scala 708:39] + reg ifu_status_wr_addr_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 711:12] + ifu_status_wr_addr_ff <= ifu_status_wr_addr_w_debug @[el2_ifu_mem_ctl.scala 711:12] + wire way_status_wr_en : UInt<1> + way_status_wr_en <= UInt<1>("h00") + node _T_3949 = and(io.ic_debug_wr_en, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 714:72] + node way_status_wr_en_w_debug = or(way_status_wr_en, _T_3949) @[el2_ifu_mem_ctl.scala 714:51] + reg way_status_wr_en_ff : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 716:12] + way_status_wr_en_ff <= way_status_wr_en_w_debug @[el2_ifu_mem_ctl.scala 716:12] + wire way_status_new : UInt<1> + way_status_new <= UInt<1>("h00") + node _T_3950 = and(io.ic_debug_wr_en, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 719:54] + node _T_3951 = bits(io.ic_debug_wr_data, 4, 4) @[el2_ifu_mem_ctl.scala 720:53] + node way_status_new_w_debug = mux(_T_3950, _T_3951, way_status_new) @[el2_ifu_mem_ctl.scala 719:35] + reg way_status_new_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 722:12] + way_status_new_ff <= way_status_new_w_debug @[el2_ifu_mem_ctl.scala 722:12] + node _T_3952 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 724:87] + node way_status_clken_0 = eq(_T_3952, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 724:130] + node _T_3953 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 724:87] + node way_status_clken_1 = eq(_T_3953, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 724:130] + node _T_3954 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 724:87] + node way_status_clken_2 = eq(_T_3954, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 724:130] + node _T_3955 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 724:87] + node way_status_clken_3 = eq(_T_3955, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 724:130] + node _T_3956 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 724:87] + node way_status_clken_4 = eq(_T_3956, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 724:130] + node _T_3957 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 724:87] + node way_status_clken_5 = eq(_T_3957, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 724:130] + node _T_3958 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 724:87] + node way_status_clken_6 = eq(_T_3958, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 724:130] + node _T_3959 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 724:87] + node way_status_clken_7 = eq(_T_3959, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 724:130] + node _T_3960 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 724:87] + node way_status_clken_8 = eq(_T_3960, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 724:130] + node _T_3961 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 724:87] + node way_status_clken_9 = eq(_T_3961, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 724:130] + node _T_3962 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 724:87] + node way_status_clken_10 = eq(_T_3962, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 724:130] + node _T_3963 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 724:87] + node way_status_clken_11 = eq(_T_3963, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 724:130] + node _T_3964 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 724:87] + node way_status_clken_12 = eq(_T_3964, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 724:130] + node _T_3965 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 724:87] + node way_status_clken_13 = eq(_T_3965, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 724:130] + node _T_3966 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 724:87] + node way_status_clken_14 = eq(_T_3966, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 724:130] + node _T_3967 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 724:87] + node way_status_clken_15 = eq(_T_3967, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 724:130] + inst rvclkhdr_70 of rvclkhdr_70 @[el2_lib.scala 483:22] + rvclkhdr_70.clock <= clock + rvclkhdr_70.reset <= reset + rvclkhdr_70.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_70.io.en <= way_status_clken_0 @[el2_lib.scala 485:16] + rvclkhdr_70.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_71 of rvclkhdr_71 @[el2_lib.scala 483:22] + rvclkhdr_71.clock <= clock + rvclkhdr_71.reset <= reset + rvclkhdr_71.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_71.io.en <= way_status_clken_1 @[el2_lib.scala 485:16] + rvclkhdr_71.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_72 of rvclkhdr_72 @[el2_lib.scala 483:22] + rvclkhdr_72.clock <= clock + rvclkhdr_72.reset <= reset + rvclkhdr_72.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_72.io.en <= way_status_clken_2 @[el2_lib.scala 485:16] + rvclkhdr_72.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_73 of rvclkhdr_73 @[el2_lib.scala 483:22] + rvclkhdr_73.clock <= clock + rvclkhdr_73.reset <= reset + rvclkhdr_73.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_73.io.en <= way_status_clken_3 @[el2_lib.scala 485:16] + rvclkhdr_73.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_74 of rvclkhdr_74 @[el2_lib.scala 483:22] + rvclkhdr_74.clock <= clock + rvclkhdr_74.reset <= reset + rvclkhdr_74.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_74.io.en <= way_status_clken_4 @[el2_lib.scala 485:16] + rvclkhdr_74.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_75 of rvclkhdr_75 @[el2_lib.scala 483:22] + rvclkhdr_75.clock <= clock + rvclkhdr_75.reset <= reset + rvclkhdr_75.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_75.io.en <= way_status_clken_5 @[el2_lib.scala 485:16] + rvclkhdr_75.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_76 of rvclkhdr_76 @[el2_lib.scala 483:22] + rvclkhdr_76.clock <= clock + rvclkhdr_76.reset <= reset + rvclkhdr_76.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_76.io.en <= way_status_clken_6 @[el2_lib.scala 485:16] + rvclkhdr_76.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_77 of rvclkhdr_77 @[el2_lib.scala 483:22] + rvclkhdr_77.clock <= clock + rvclkhdr_77.reset <= reset + rvclkhdr_77.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_77.io.en <= way_status_clken_7 @[el2_lib.scala 485:16] + rvclkhdr_77.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_78 of rvclkhdr_78 @[el2_lib.scala 483:22] + rvclkhdr_78.clock <= clock + rvclkhdr_78.reset <= reset + rvclkhdr_78.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_78.io.en <= way_status_clken_8 @[el2_lib.scala 485:16] + rvclkhdr_78.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_79 of rvclkhdr_79 @[el2_lib.scala 483:22] + rvclkhdr_79.clock <= clock + rvclkhdr_79.reset <= reset + rvclkhdr_79.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_79.io.en <= way_status_clken_9 @[el2_lib.scala 485:16] + rvclkhdr_79.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_80 of rvclkhdr_80 @[el2_lib.scala 483:22] + rvclkhdr_80.clock <= clock + rvclkhdr_80.reset <= reset + rvclkhdr_80.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_80.io.en <= way_status_clken_10 @[el2_lib.scala 485:16] + rvclkhdr_80.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_81 of rvclkhdr_81 @[el2_lib.scala 483:22] + rvclkhdr_81.clock <= clock + rvclkhdr_81.reset <= reset + rvclkhdr_81.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_81.io.en <= way_status_clken_11 @[el2_lib.scala 485:16] + rvclkhdr_81.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_82 of rvclkhdr_82 @[el2_lib.scala 483:22] + rvclkhdr_82.clock <= clock + rvclkhdr_82.reset <= reset + rvclkhdr_82.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_82.io.en <= way_status_clken_12 @[el2_lib.scala 485:16] + rvclkhdr_82.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_83 of rvclkhdr_83 @[el2_lib.scala 483:22] + rvclkhdr_83.clock <= clock + rvclkhdr_83.reset <= reset + rvclkhdr_83.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_83.io.en <= way_status_clken_13 @[el2_lib.scala 485:16] + rvclkhdr_83.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_84 of rvclkhdr_84 @[el2_lib.scala 483:22] + rvclkhdr_84.clock <= clock + rvclkhdr_84.reset <= reset + rvclkhdr_84.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_84.io.en <= way_status_clken_14 @[el2_lib.scala 485:16] + rvclkhdr_84.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_85 of rvclkhdr_85 @[el2_lib.scala 483:22] + rvclkhdr_85.clock <= clock + rvclkhdr_85.reset <= reset + rvclkhdr_85.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_85.io.en <= way_status_clken_15 @[el2_lib.scala 485:16] + rvclkhdr_85.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + wire way_status_out : UInt<1>[128] @[el2_ifu_mem_ctl.scala 726:28] + node _T_3968 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_3969 = eq(_T_3968, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_3970 = and(_T_3969, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_3971 : UInt, rvclkhdr_70.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3970 : @[Reg.scala 28:19] + _T_3971 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[0] <= _T_3971 @[el2_ifu_mem_ctl.scala 728:33] + node _T_3972 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_3973 = eq(_T_3972, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_3974 = and(_T_3973, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_3975 : UInt, rvclkhdr_70.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3974 : @[Reg.scala 28:19] + _T_3975 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[1] <= _T_3975 @[el2_ifu_mem_ctl.scala 728:33] + node _T_3976 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_3977 = eq(_T_3976, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_3978 = and(_T_3977, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_3979 : UInt, rvclkhdr_70.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3978 : @[Reg.scala 28:19] + _T_3979 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[2] <= _T_3979 @[el2_ifu_mem_ctl.scala 728:33] + node _T_3980 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_3981 = eq(_T_3980, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_3982 = and(_T_3981, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_3983 : UInt, rvclkhdr_70.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3982 : @[Reg.scala 28:19] + _T_3983 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[3] <= _T_3983 @[el2_ifu_mem_ctl.scala 728:33] + node _T_3984 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_3985 = eq(_T_3984, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_3986 = and(_T_3985, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_3987 : UInt, rvclkhdr_70.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3986 : @[Reg.scala 28:19] + _T_3987 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[4] <= _T_3987 @[el2_ifu_mem_ctl.scala 728:33] + node _T_3988 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_3989 = eq(_T_3988, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_3990 = and(_T_3989, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_3991 : UInt, rvclkhdr_70.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3990 : @[Reg.scala 28:19] + _T_3991 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[5] <= _T_3991 @[el2_ifu_mem_ctl.scala 728:33] + node _T_3992 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_3993 = eq(_T_3992, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_3994 = and(_T_3993, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_3995 : UInt, rvclkhdr_70.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3994 : @[Reg.scala 28:19] + _T_3995 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[6] <= _T_3995 @[el2_ifu_mem_ctl.scala 728:33] + node _T_3996 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_3997 = eq(_T_3996, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_3998 = and(_T_3997, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_3999 : UInt, rvclkhdr_70.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3998 : @[Reg.scala 28:19] + _T_3999 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[7] <= _T_3999 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4000 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4001 = eq(_T_4000, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4002 = and(_T_4001, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4003 : UInt, rvclkhdr_71.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4002 : @[Reg.scala 28:19] + _T_4003 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[8] <= _T_4003 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4004 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4005 = eq(_T_4004, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4006 = and(_T_4005, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4007 : UInt, rvclkhdr_71.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4006 : @[Reg.scala 28:19] + _T_4007 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[9] <= _T_4007 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4008 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4009 = eq(_T_4008, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4010 = and(_T_4009, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4011 : UInt, rvclkhdr_71.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4010 : @[Reg.scala 28:19] + _T_4011 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[10] <= _T_4011 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4012 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4013 = eq(_T_4012, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4014 = and(_T_4013, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4015 : UInt, rvclkhdr_71.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4014 : @[Reg.scala 28:19] + _T_4015 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[11] <= _T_4015 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4016 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4017 = eq(_T_4016, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4018 = and(_T_4017, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4019 : UInt, rvclkhdr_71.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4018 : @[Reg.scala 28:19] + _T_4019 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[12] <= _T_4019 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4020 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4021 = eq(_T_4020, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4022 = and(_T_4021, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4023 : UInt, rvclkhdr_71.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4022 : @[Reg.scala 28:19] + _T_4023 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[13] <= _T_4023 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4024 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4025 = eq(_T_4024, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4026 = and(_T_4025, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4027 : UInt, rvclkhdr_71.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4026 : @[Reg.scala 28:19] + _T_4027 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[14] <= _T_4027 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4028 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4029 = eq(_T_4028, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4030 = and(_T_4029, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4031 : UInt, rvclkhdr_71.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4030 : @[Reg.scala 28:19] + _T_4031 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[15] <= _T_4031 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4032 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4033 = eq(_T_4032, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4034 = and(_T_4033, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4035 : UInt, rvclkhdr_72.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4034 : @[Reg.scala 28:19] + _T_4035 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[16] <= _T_4035 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4036 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4037 = eq(_T_4036, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4038 = and(_T_4037, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4039 : UInt, rvclkhdr_72.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4038 : @[Reg.scala 28:19] + _T_4039 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[17] <= _T_4039 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4040 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4041 = eq(_T_4040, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4042 = and(_T_4041, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4043 : UInt, rvclkhdr_72.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4042 : @[Reg.scala 28:19] + _T_4043 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[18] <= _T_4043 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4044 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4045 = eq(_T_4044, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4046 = and(_T_4045, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4047 : UInt, rvclkhdr_72.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4046 : @[Reg.scala 28:19] + _T_4047 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[19] <= _T_4047 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4048 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4049 = eq(_T_4048, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4050 = and(_T_4049, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4051 : UInt, rvclkhdr_72.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4050 : @[Reg.scala 28:19] + _T_4051 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[20] <= _T_4051 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4052 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4053 = eq(_T_4052, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4054 = and(_T_4053, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4055 : UInt, rvclkhdr_72.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4054 : @[Reg.scala 28:19] + _T_4055 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[21] <= _T_4055 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4056 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4057 = eq(_T_4056, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4058 = and(_T_4057, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4059 : UInt, rvclkhdr_72.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4058 : @[Reg.scala 28:19] + _T_4059 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[22] <= _T_4059 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4060 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4061 = eq(_T_4060, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4062 = and(_T_4061, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4063 : UInt, rvclkhdr_72.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4062 : @[Reg.scala 28:19] + _T_4063 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[23] <= _T_4063 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4064 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4065 = eq(_T_4064, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4066 = and(_T_4065, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4067 : UInt, rvclkhdr_73.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4066 : @[Reg.scala 28:19] + _T_4067 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[24] <= _T_4067 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4068 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4069 = eq(_T_4068, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4070 = and(_T_4069, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4071 : UInt, rvclkhdr_73.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4070 : @[Reg.scala 28:19] + _T_4071 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[25] <= _T_4071 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4072 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4073 = eq(_T_4072, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4074 = and(_T_4073, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4075 : UInt, rvclkhdr_73.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4074 : @[Reg.scala 28:19] + _T_4075 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[26] <= _T_4075 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4076 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4077 = eq(_T_4076, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4078 = and(_T_4077, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4079 : UInt, rvclkhdr_73.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4078 : @[Reg.scala 28:19] + _T_4079 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[27] <= _T_4079 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4080 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4081 = eq(_T_4080, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4082 = and(_T_4081, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4083 : UInt, rvclkhdr_73.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4082 : @[Reg.scala 28:19] + _T_4083 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[28] <= _T_4083 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4084 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4085 = eq(_T_4084, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4086 = and(_T_4085, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4087 : UInt, rvclkhdr_73.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4086 : @[Reg.scala 28:19] + _T_4087 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[29] <= _T_4087 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4088 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4089 = eq(_T_4088, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4090 = and(_T_4089, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4091 : UInt, rvclkhdr_73.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4090 : @[Reg.scala 28:19] + _T_4091 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[30] <= _T_4091 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4092 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4093 = eq(_T_4092, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4094 = and(_T_4093, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4095 : UInt, rvclkhdr_73.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4094 : @[Reg.scala 28:19] + _T_4095 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[31] <= _T_4095 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4096 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4097 = eq(_T_4096, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4098 = and(_T_4097, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4099 : UInt, rvclkhdr_74.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4098 : @[Reg.scala 28:19] + _T_4099 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[32] <= _T_4099 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4100 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4101 = eq(_T_4100, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4102 = and(_T_4101, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4103 : UInt, rvclkhdr_74.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4102 : @[Reg.scala 28:19] + _T_4103 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[33] <= _T_4103 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4104 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4105 = eq(_T_4104, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4106 = and(_T_4105, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4107 : UInt, rvclkhdr_74.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4106 : @[Reg.scala 28:19] + _T_4107 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[34] <= _T_4107 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4108 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4109 = eq(_T_4108, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4110 = and(_T_4109, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4111 : UInt, rvclkhdr_74.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4110 : @[Reg.scala 28:19] + _T_4111 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[35] <= _T_4111 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4112 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4113 = eq(_T_4112, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4114 = and(_T_4113, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4115 : UInt, rvclkhdr_74.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4114 : @[Reg.scala 28:19] + _T_4115 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[36] <= _T_4115 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4116 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4117 = eq(_T_4116, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4118 = and(_T_4117, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4119 : UInt, rvclkhdr_74.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4118 : @[Reg.scala 28:19] + _T_4119 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[37] <= _T_4119 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4120 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4121 = eq(_T_4120, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4122 = and(_T_4121, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4123 : UInt, rvclkhdr_74.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4122 : @[Reg.scala 28:19] + _T_4123 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[38] <= _T_4123 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4124 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4125 = eq(_T_4124, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4126 = and(_T_4125, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4127 : UInt, rvclkhdr_74.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4126 : @[Reg.scala 28:19] + _T_4127 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[39] <= _T_4127 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4128 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4129 = eq(_T_4128, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4130 = and(_T_4129, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4131 : UInt, rvclkhdr_75.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4130 : @[Reg.scala 28:19] + _T_4131 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[40] <= _T_4131 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4132 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4133 = eq(_T_4132, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4134 = and(_T_4133, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4135 : UInt, rvclkhdr_75.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4134 : @[Reg.scala 28:19] + _T_4135 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[41] <= _T_4135 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4136 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4137 = eq(_T_4136, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4138 = and(_T_4137, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4139 : UInt, rvclkhdr_75.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4138 : @[Reg.scala 28:19] + _T_4139 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[42] <= _T_4139 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4140 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4141 = eq(_T_4140, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4142 = and(_T_4141, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4143 : UInt, rvclkhdr_75.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4142 : @[Reg.scala 28:19] + _T_4143 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[43] <= _T_4143 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4144 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4145 = eq(_T_4144, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4146 = and(_T_4145, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4147 : UInt, rvclkhdr_75.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4146 : @[Reg.scala 28:19] + _T_4147 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[44] <= _T_4147 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4148 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4149 = eq(_T_4148, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4150 = and(_T_4149, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4151 : UInt, rvclkhdr_75.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4150 : @[Reg.scala 28:19] + _T_4151 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[45] <= _T_4151 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4152 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4153 = eq(_T_4152, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4154 = and(_T_4153, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4155 : UInt, rvclkhdr_75.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4154 : @[Reg.scala 28:19] + _T_4155 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[46] <= _T_4155 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4156 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4157 = eq(_T_4156, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4158 = and(_T_4157, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4159 : UInt, rvclkhdr_75.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4158 : @[Reg.scala 28:19] + _T_4159 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[47] <= _T_4159 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4160 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4161 = eq(_T_4160, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4162 = and(_T_4161, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4163 : UInt, rvclkhdr_76.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4162 : @[Reg.scala 28:19] + _T_4163 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[48] <= _T_4163 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4164 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4165 = eq(_T_4164, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4166 = and(_T_4165, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4167 : UInt, rvclkhdr_76.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4166 : @[Reg.scala 28:19] + _T_4167 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[49] <= _T_4167 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4168 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4169 = eq(_T_4168, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4170 = and(_T_4169, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4171 : UInt, rvclkhdr_76.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4170 : @[Reg.scala 28:19] + _T_4171 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[50] <= _T_4171 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4172 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4173 = eq(_T_4172, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4174 = and(_T_4173, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4175 : UInt, rvclkhdr_76.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4174 : @[Reg.scala 28:19] + _T_4175 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[51] <= _T_4175 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4176 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4177 = eq(_T_4176, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4178 = and(_T_4177, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4179 : UInt, rvclkhdr_76.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4178 : @[Reg.scala 28:19] + _T_4179 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[52] <= _T_4179 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4180 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4181 = eq(_T_4180, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4182 = and(_T_4181, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4183 : UInt, rvclkhdr_76.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4182 : @[Reg.scala 28:19] + _T_4183 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[53] <= _T_4183 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4184 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4185 = eq(_T_4184, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4186 = and(_T_4185, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4187 : UInt, rvclkhdr_76.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4186 : @[Reg.scala 28:19] + _T_4187 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[54] <= _T_4187 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4188 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4189 = eq(_T_4188, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4190 = and(_T_4189, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4191 : UInt, rvclkhdr_76.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4190 : @[Reg.scala 28:19] + _T_4191 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[55] <= _T_4191 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4192 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4193 = eq(_T_4192, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4194 = and(_T_4193, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4195 : UInt, rvclkhdr_77.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4194 : @[Reg.scala 28:19] + _T_4195 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[56] <= _T_4195 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4196 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4197 = eq(_T_4196, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4198 = and(_T_4197, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4199 : UInt, rvclkhdr_77.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4198 : @[Reg.scala 28:19] + _T_4199 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[57] <= _T_4199 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4200 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4201 = eq(_T_4200, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4202 = and(_T_4201, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4203 : UInt, rvclkhdr_77.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4202 : @[Reg.scala 28:19] + _T_4203 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[58] <= _T_4203 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4204 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4205 = eq(_T_4204, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4206 = and(_T_4205, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4207 : UInt, rvclkhdr_77.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4206 : @[Reg.scala 28:19] + _T_4207 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[59] <= _T_4207 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4208 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4209 = eq(_T_4208, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4210 = and(_T_4209, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4211 : UInt, rvclkhdr_77.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4210 : @[Reg.scala 28:19] + _T_4211 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[60] <= _T_4211 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4212 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4213 = eq(_T_4212, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4214 = and(_T_4213, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4215 : UInt, rvclkhdr_77.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4214 : @[Reg.scala 28:19] + _T_4215 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[61] <= _T_4215 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4216 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4217 = eq(_T_4216, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4218 = and(_T_4217, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4219 : UInt, rvclkhdr_77.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4218 : @[Reg.scala 28:19] + _T_4219 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[62] <= _T_4219 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4220 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4221 = eq(_T_4220, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4222 = and(_T_4221, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4223 : UInt, rvclkhdr_77.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4222 : @[Reg.scala 28:19] + _T_4223 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[63] <= _T_4223 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4224 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4225 = eq(_T_4224, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4226 = and(_T_4225, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4227 : UInt, rvclkhdr_78.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4226 : @[Reg.scala 28:19] + _T_4227 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[64] <= _T_4227 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4228 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4229 = eq(_T_4228, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4230 = and(_T_4229, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4231 : UInt, rvclkhdr_78.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4230 : @[Reg.scala 28:19] + _T_4231 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[65] <= _T_4231 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4232 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4233 = eq(_T_4232, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4234 = and(_T_4233, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4235 : UInt, rvclkhdr_78.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4234 : @[Reg.scala 28:19] + _T_4235 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[66] <= _T_4235 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4236 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4237 = eq(_T_4236, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4238 = and(_T_4237, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4239 : UInt, rvclkhdr_78.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4238 : @[Reg.scala 28:19] + _T_4239 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[67] <= _T_4239 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4240 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4241 = eq(_T_4240, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4242 = and(_T_4241, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4243 : UInt, rvclkhdr_78.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4242 : @[Reg.scala 28:19] + _T_4243 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[68] <= _T_4243 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4244 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4245 = eq(_T_4244, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4246 = and(_T_4245, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4247 : UInt, rvclkhdr_78.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4246 : @[Reg.scala 28:19] + _T_4247 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[69] <= _T_4247 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4248 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4249 = eq(_T_4248, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4250 = and(_T_4249, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4251 : UInt, rvclkhdr_78.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4250 : @[Reg.scala 28:19] + _T_4251 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[70] <= _T_4251 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4252 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4253 = eq(_T_4252, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4254 = and(_T_4253, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4255 : UInt, rvclkhdr_78.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4254 : @[Reg.scala 28:19] + _T_4255 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[71] <= _T_4255 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4256 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4257 = eq(_T_4256, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4258 = and(_T_4257, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4259 : UInt, rvclkhdr_79.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4258 : @[Reg.scala 28:19] + _T_4259 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[72] <= _T_4259 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4260 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4261 = eq(_T_4260, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4262 = and(_T_4261, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4263 : UInt, rvclkhdr_79.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4262 : @[Reg.scala 28:19] + _T_4263 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[73] <= _T_4263 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4264 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4265 = eq(_T_4264, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4266 = and(_T_4265, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4267 : UInt, rvclkhdr_79.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4266 : @[Reg.scala 28:19] + _T_4267 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[74] <= _T_4267 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4268 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4269 = eq(_T_4268, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4270 = and(_T_4269, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4271 : UInt, rvclkhdr_79.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4270 : @[Reg.scala 28:19] + _T_4271 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[75] <= _T_4271 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4272 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4273 = eq(_T_4272, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4274 = and(_T_4273, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4275 : UInt, rvclkhdr_79.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4274 : @[Reg.scala 28:19] + _T_4275 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[76] <= _T_4275 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4276 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4277 = eq(_T_4276, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4278 = and(_T_4277, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4279 : UInt, rvclkhdr_79.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4278 : @[Reg.scala 28:19] + _T_4279 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[77] <= _T_4279 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4280 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4281 = eq(_T_4280, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4282 = and(_T_4281, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4283 : UInt, rvclkhdr_79.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4282 : @[Reg.scala 28:19] + _T_4283 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[78] <= _T_4283 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4284 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4285 = eq(_T_4284, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4286 = and(_T_4285, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4287 : UInt, rvclkhdr_79.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4286 : @[Reg.scala 28:19] + _T_4287 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[79] <= _T_4287 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4288 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4289 = eq(_T_4288, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4290 = and(_T_4289, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4291 : UInt, rvclkhdr_80.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4290 : @[Reg.scala 28:19] + _T_4291 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[80] <= _T_4291 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4292 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4293 = eq(_T_4292, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4294 = and(_T_4293, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4295 : UInt, rvclkhdr_80.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4294 : @[Reg.scala 28:19] + _T_4295 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[81] <= _T_4295 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4296 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4297 = eq(_T_4296, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4298 = and(_T_4297, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4299 : UInt, rvclkhdr_80.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4298 : @[Reg.scala 28:19] + _T_4299 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[82] <= _T_4299 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4300 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4301 = eq(_T_4300, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4302 = and(_T_4301, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4303 : UInt, rvclkhdr_80.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4302 : @[Reg.scala 28:19] + _T_4303 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[83] <= _T_4303 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4304 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4305 = eq(_T_4304, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4306 = and(_T_4305, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4307 : UInt, rvclkhdr_80.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4306 : @[Reg.scala 28:19] + _T_4307 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[84] <= _T_4307 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4308 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4309 = eq(_T_4308, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4310 = and(_T_4309, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4311 : UInt, rvclkhdr_80.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4310 : @[Reg.scala 28:19] + _T_4311 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[85] <= _T_4311 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4312 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4313 = eq(_T_4312, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4314 = and(_T_4313, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4315 : UInt, rvclkhdr_80.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4314 : @[Reg.scala 28:19] + _T_4315 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[86] <= _T_4315 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4316 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4317 = eq(_T_4316, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4318 = and(_T_4317, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4319 : UInt, rvclkhdr_80.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4318 : @[Reg.scala 28:19] + _T_4319 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[87] <= _T_4319 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4320 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4321 = eq(_T_4320, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4322 = and(_T_4321, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4323 : UInt, rvclkhdr_81.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4322 : @[Reg.scala 28:19] + _T_4323 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[88] <= _T_4323 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4324 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4325 = eq(_T_4324, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4326 = and(_T_4325, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4327 : UInt, rvclkhdr_81.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4326 : @[Reg.scala 28:19] + _T_4327 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[89] <= _T_4327 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4328 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4329 = eq(_T_4328, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4330 = and(_T_4329, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4331 : UInt, rvclkhdr_81.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4330 : @[Reg.scala 28:19] + _T_4331 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[90] <= _T_4331 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4332 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4333 = eq(_T_4332, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4334 = and(_T_4333, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4335 : UInt, rvclkhdr_81.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4334 : @[Reg.scala 28:19] + _T_4335 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[91] <= _T_4335 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4336 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4337 = eq(_T_4336, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4338 = and(_T_4337, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4339 : UInt, rvclkhdr_81.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4338 : @[Reg.scala 28:19] + _T_4339 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[92] <= _T_4339 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4340 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4341 = eq(_T_4340, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4342 = and(_T_4341, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4343 : UInt, rvclkhdr_81.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4342 : @[Reg.scala 28:19] + _T_4343 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[93] <= _T_4343 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4344 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4345 = eq(_T_4344, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4346 = and(_T_4345, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4347 : UInt, rvclkhdr_81.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4346 : @[Reg.scala 28:19] + _T_4347 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[94] <= _T_4347 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4348 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4349 = eq(_T_4348, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4350 = and(_T_4349, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4351 : UInt, rvclkhdr_81.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4350 : @[Reg.scala 28:19] + _T_4351 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[95] <= _T_4351 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4352 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4353 = eq(_T_4352, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4354 = and(_T_4353, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4355 : UInt, rvclkhdr_82.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4354 : @[Reg.scala 28:19] + _T_4355 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[96] <= _T_4355 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4356 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4357 = eq(_T_4356, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4358 = and(_T_4357, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4359 : UInt, rvclkhdr_82.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4358 : @[Reg.scala 28:19] + _T_4359 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[97] <= _T_4359 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4360 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4361 = eq(_T_4360, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4362 = and(_T_4361, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4363 : UInt, rvclkhdr_82.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4362 : @[Reg.scala 28:19] + _T_4363 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[98] <= _T_4363 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4364 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4365 = eq(_T_4364, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4366 = and(_T_4365, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4367 : UInt, rvclkhdr_82.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4366 : @[Reg.scala 28:19] + _T_4367 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[99] <= _T_4367 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4368 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4369 = eq(_T_4368, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4370 = and(_T_4369, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4371 : UInt, rvclkhdr_82.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4370 : @[Reg.scala 28:19] + _T_4371 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[100] <= _T_4371 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4372 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4373 = eq(_T_4372, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4374 = and(_T_4373, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4375 : UInt, rvclkhdr_82.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4374 : @[Reg.scala 28:19] + _T_4375 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[101] <= _T_4375 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4376 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4377 = eq(_T_4376, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4378 = and(_T_4377, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4379 : UInt, rvclkhdr_82.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4378 : @[Reg.scala 28:19] + _T_4379 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[102] <= _T_4379 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4380 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4381 = eq(_T_4380, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4382 = and(_T_4381, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4383 : UInt, rvclkhdr_82.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4382 : @[Reg.scala 28:19] + _T_4383 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[103] <= _T_4383 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4384 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4385 = eq(_T_4384, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4386 = and(_T_4385, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4387 : UInt, rvclkhdr_83.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4386 : @[Reg.scala 28:19] + _T_4387 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[104] <= _T_4387 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4388 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4389 = eq(_T_4388, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4390 = and(_T_4389, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4391 : UInt, rvclkhdr_83.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4390 : @[Reg.scala 28:19] + _T_4391 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[105] <= _T_4391 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4392 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4393 = eq(_T_4392, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4394 = and(_T_4393, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4395 : UInt, rvclkhdr_83.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4394 : @[Reg.scala 28:19] + _T_4395 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[106] <= _T_4395 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4396 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4397 = eq(_T_4396, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4398 = and(_T_4397, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4399 : UInt, rvclkhdr_83.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4398 : @[Reg.scala 28:19] + _T_4399 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[107] <= _T_4399 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4400 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4401 = eq(_T_4400, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4402 = and(_T_4401, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4403 : UInt, rvclkhdr_83.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4402 : @[Reg.scala 28:19] + _T_4403 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[108] <= _T_4403 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4404 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4405 = eq(_T_4404, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4406 = and(_T_4405, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4407 : UInt, rvclkhdr_83.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4406 : @[Reg.scala 28:19] + _T_4407 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[109] <= _T_4407 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4408 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4409 = eq(_T_4408, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4410 = and(_T_4409, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4411 : UInt, rvclkhdr_83.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4410 : @[Reg.scala 28:19] + _T_4411 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[110] <= _T_4411 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4412 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4413 = eq(_T_4412, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4414 = and(_T_4413, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4415 : UInt, rvclkhdr_83.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4414 : @[Reg.scala 28:19] + _T_4415 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[111] <= _T_4415 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4416 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4417 = eq(_T_4416, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4418 = and(_T_4417, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4419 : UInt, rvclkhdr_84.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4418 : @[Reg.scala 28:19] + _T_4419 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[112] <= _T_4419 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4420 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4421 = eq(_T_4420, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4422 = and(_T_4421, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4423 : UInt, rvclkhdr_84.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4422 : @[Reg.scala 28:19] + _T_4423 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[113] <= _T_4423 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4424 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4425 = eq(_T_4424, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4426 = and(_T_4425, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4427 : UInt, rvclkhdr_84.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4426 : @[Reg.scala 28:19] + _T_4427 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[114] <= _T_4427 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4428 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4429 = eq(_T_4428, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4430 = and(_T_4429, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4431 : UInt, rvclkhdr_84.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4430 : @[Reg.scala 28:19] + _T_4431 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[115] <= _T_4431 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4432 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4433 = eq(_T_4432, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4434 = and(_T_4433, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4435 : UInt, rvclkhdr_84.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4434 : @[Reg.scala 28:19] + _T_4435 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[116] <= _T_4435 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4436 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4437 = eq(_T_4436, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4438 = and(_T_4437, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4439 : UInt, rvclkhdr_84.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4438 : @[Reg.scala 28:19] + _T_4439 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[117] <= _T_4439 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4440 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4441 = eq(_T_4440, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4442 = and(_T_4441, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4443 : UInt, rvclkhdr_84.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4442 : @[Reg.scala 28:19] + _T_4443 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[118] <= _T_4443 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4444 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4445 = eq(_T_4444, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4446 = and(_T_4445, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4447 : UInt, rvclkhdr_84.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4446 : @[Reg.scala 28:19] + _T_4447 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[119] <= _T_4447 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4448 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4449 = eq(_T_4448, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4450 = and(_T_4449, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4451 : UInt, rvclkhdr_85.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4450 : @[Reg.scala 28:19] + _T_4451 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[120] <= _T_4451 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4452 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4453 = eq(_T_4452, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4454 = and(_T_4453, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4455 : UInt, rvclkhdr_85.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4454 : @[Reg.scala 28:19] + _T_4455 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[121] <= _T_4455 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4456 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4457 = eq(_T_4456, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4458 = and(_T_4457, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4459 : UInt, rvclkhdr_85.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4458 : @[Reg.scala 28:19] + _T_4459 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[122] <= _T_4459 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4460 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4461 = eq(_T_4460, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4462 = and(_T_4461, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4463 : UInt, rvclkhdr_85.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4462 : @[Reg.scala 28:19] + _T_4463 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[123] <= _T_4463 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4464 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4465 = eq(_T_4464, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4466 = and(_T_4465, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4467 : UInt, rvclkhdr_85.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4466 : @[Reg.scala 28:19] + _T_4467 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[124] <= _T_4467 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4468 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4469 = eq(_T_4468, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4470 = and(_T_4469, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4471 : UInt, rvclkhdr_85.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4470 : @[Reg.scala 28:19] + _T_4471 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[125] <= _T_4471 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4472 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4473 = eq(_T_4472, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4474 = and(_T_4473, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4475 : UInt, rvclkhdr_85.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4474 : @[Reg.scala 28:19] + _T_4475 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[126] <= _T_4475 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4476 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 728:121] + node _T_4477 = eq(_T_4476, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 728:126] + node _T_4478 = and(_T_4477, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 728:134] + reg _T_4479 : UInt, rvclkhdr_85.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4478 : @[Reg.scala 28:19] + _T_4479 <= way_status_new_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + way_status_out[127] <= _T_4479 @[el2_ifu_mem_ctl.scala 728:33] + node _T_4480 = cat(way_status_out[127], way_status_out[126]) @[Cat.scala 29:58] + node _T_4481 = cat(_T_4480, way_status_out[125]) @[Cat.scala 29:58] + node _T_4482 = cat(_T_4481, way_status_out[124]) @[Cat.scala 29:58] + node _T_4483 = cat(_T_4482, way_status_out[123]) @[Cat.scala 29:58] + node _T_4484 = cat(_T_4483, way_status_out[122]) @[Cat.scala 29:58] + node _T_4485 = cat(_T_4484, way_status_out[121]) @[Cat.scala 29:58] + node _T_4486 = cat(_T_4485, way_status_out[120]) @[Cat.scala 29:58] + node _T_4487 = cat(_T_4486, way_status_out[119]) @[Cat.scala 29:58] + node _T_4488 = cat(_T_4487, way_status_out[118]) @[Cat.scala 29:58] + node _T_4489 = cat(_T_4488, way_status_out[117]) @[Cat.scala 29:58] + node _T_4490 = cat(_T_4489, way_status_out[116]) @[Cat.scala 29:58] + node _T_4491 = cat(_T_4490, way_status_out[115]) @[Cat.scala 29:58] + node _T_4492 = cat(_T_4491, way_status_out[114]) @[Cat.scala 29:58] + node _T_4493 = cat(_T_4492, way_status_out[113]) @[Cat.scala 29:58] + node _T_4494 = cat(_T_4493, way_status_out[112]) @[Cat.scala 29:58] + node _T_4495 = cat(_T_4494, way_status_out[111]) @[Cat.scala 29:58] + node _T_4496 = cat(_T_4495, way_status_out[110]) @[Cat.scala 29:58] + node _T_4497 = cat(_T_4496, way_status_out[109]) @[Cat.scala 29:58] + node _T_4498 = cat(_T_4497, way_status_out[108]) @[Cat.scala 29:58] + node _T_4499 = cat(_T_4498, way_status_out[107]) @[Cat.scala 29:58] + node _T_4500 = cat(_T_4499, way_status_out[106]) @[Cat.scala 29:58] + node _T_4501 = cat(_T_4500, way_status_out[105]) @[Cat.scala 29:58] + node _T_4502 = cat(_T_4501, way_status_out[104]) @[Cat.scala 29:58] + node _T_4503 = cat(_T_4502, way_status_out[103]) @[Cat.scala 29:58] + node _T_4504 = cat(_T_4503, way_status_out[102]) @[Cat.scala 29:58] + node _T_4505 = cat(_T_4504, way_status_out[101]) @[Cat.scala 29:58] + node _T_4506 = cat(_T_4505, way_status_out[100]) @[Cat.scala 29:58] + node _T_4507 = cat(_T_4506, way_status_out[99]) @[Cat.scala 29:58] + node _T_4508 = cat(_T_4507, way_status_out[98]) @[Cat.scala 29:58] + node _T_4509 = cat(_T_4508, way_status_out[97]) @[Cat.scala 29:58] + node _T_4510 = cat(_T_4509, way_status_out[96]) @[Cat.scala 29:58] + node _T_4511 = cat(_T_4510, way_status_out[95]) @[Cat.scala 29:58] + node _T_4512 = cat(_T_4511, way_status_out[94]) @[Cat.scala 29:58] + node _T_4513 = cat(_T_4512, way_status_out[93]) @[Cat.scala 29:58] + node _T_4514 = cat(_T_4513, way_status_out[92]) @[Cat.scala 29:58] + node _T_4515 = cat(_T_4514, way_status_out[91]) @[Cat.scala 29:58] + node _T_4516 = cat(_T_4515, way_status_out[90]) @[Cat.scala 29:58] + node _T_4517 = cat(_T_4516, way_status_out[89]) @[Cat.scala 29:58] + node _T_4518 = cat(_T_4517, way_status_out[88]) @[Cat.scala 29:58] + node _T_4519 = cat(_T_4518, way_status_out[87]) @[Cat.scala 29:58] + node _T_4520 = cat(_T_4519, way_status_out[86]) @[Cat.scala 29:58] + node _T_4521 = cat(_T_4520, way_status_out[85]) @[Cat.scala 29:58] + node _T_4522 = cat(_T_4521, way_status_out[84]) @[Cat.scala 29:58] + node _T_4523 = cat(_T_4522, way_status_out[83]) @[Cat.scala 29:58] + node _T_4524 = cat(_T_4523, way_status_out[82]) @[Cat.scala 29:58] + node _T_4525 = cat(_T_4524, way_status_out[81]) @[Cat.scala 29:58] + node _T_4526 = cat(_T_4525, way_status_out[80]) @[Cat.scala 29:58] + node _T_4527 = cat(_T_4526, way_status_out[79]) @[Cat.scala 29:58] + node _T_4528 = cat(_T_4527, way_status_out[78]) @[Cat.scala 29:58] + node _T_4529 = cat(_T_4528, way_status_out[77]) @[Cat.scala 29:58] + node _T_4530 = cat(_T_4529, way_status_out[76]) @[Cat.scala 29:58] + node _T_4531 = cat(_T_4530, way_status_out[75]) @[Cat.scala 29:58] + node _T_4532 = cat(_T_4531, way_status_out[74]) @[Cat.scala 29:58] + node _T_4533 = cat(_T_4532, way_status_out[73]) @[Cat.scala 29:58] + node _T_4534 = cat(_T_4533, way_status_out[72]) @[Cat.scala 29:58] + node _T_4535 = cat(_T_4534, way_status_out[71]) @[Cat.scala 29:58] + node _T_4536 = cat(_T_4535, way_status_out[70]) @[Cat.scala 29:58] + node _T_4537 = cat(_T_4536, way_status_out[69]) @[Cat.scala 29:58] + node _T_4538 = cat(_T_4537, way_status_out[68]) @[Cat.scala 29:58] + node _T_4539 = cat(_T_4538, way_status_out[67]) @[Cat.scala 29:58] + node _T_4540 = cat(_T_4539, way_status_out[66]) @[Cat.scala 29:58] + node _T_4541 = cat(_T_4540, way_status_out[65]) @[Cat.scala 29:58] + node _T_4542 = cat(_T_4541, way_status_out[64]) @[Cat.scala 29:58] + node _T_4543 = cat(_T_4542, way_status_out[63]) @[Cat.scala 29:58] + node _T_4544 = cat(_T_4543, way_status_out[62]) @[Cat.scala 29:58] + node _T_4545 = cat(_T_4544, way_status_out[61]) @[Cat.scala 29:58] + node _T_4546 = cat(_T_4545, way_status_out[60]) @[Cat.scala 29:58] + node _T_4547 = cat(_T_4546, way_status_out[59]) @[Cat.scala 29:58] + node _T_4548 = cat(_T_4547, way_status_out[58]) @[Cat.scala 29:58] + node _T_4549 = cat(_T_4548, way_status_out[57]) @[Cat.scala 29:58] + node _T_4550 = cat(_T_4549, way_status_out[56]) @[Cat.scala 29:58] + node _T_4551 = cat(_T_4550, way_status_out[55]) @[Cat.scala 29:58] + node _T_4552 = cat(_T_4551, way_status_out[54]) @[Cat.scala 29:58] + node _T_4553 = cat(_T_4552, way_status_out[53]) @[Cat.scala 29:58] + node _T_4554 = cat(_T_4553, way_status_out[52]) @[Cat.scala 29:58] + node _T_4555 = cat(_T_4554, way_status_out[51]) @[Cat.scala 29:58] + node _T_4556 = cat(_T_4555, way_status_out[50]) @[Cat.scala 29:58] + node _T_4557 = cat(_T_4556, way_status_out[49]) @[Cat.scala 29:58] + node _T_4558 = cat(_T_4557, way_status_out[48]) @[Cat.scala 29:58] + node _T_4559 = cat(_T_4558, way_status_out[47]) @[Cat.scala 29:58] + node _T_4560 = cat(_T_4559, way_status_out[46]) @[Cat.scala 29:58] + node _T_4561 = cat(_T_4560, way_status_out[45]) @[Cat.scala 29:58] + node _T_4562 = cat(_T_4561, way_status_out[44]) @[Cat.scala 29:58] + node _T_4563 = cat(_T_4562, way_status_out[43]) @[Cat.scala 29:58] + node _T_4564 = cat(_T_4563, way_status_out[42]) @[Cat.scala 29:58] + node _T_4565 = cat(_T_4564, way_status_out[41]) @[Cat.scala 29:58] + node _T_4566 = cat(_T_4565, way_status_out[40]) @[Cat.scala 29:58] + node _T_4567 = cat(_T_4566, way_status_out[39]) @[Cat.scala 29:58] + node _T_4568 = cat(_T_4567, way_status_out[38]) @[Cat.scala 29:58] + node _T_4569 = cat(_T_4568, way_status_out[37]) @[Cat.scala 29:58] + node _T_4570 = cat(_T_4569, way_status_out[36]) @[Cat.scala 29:58] + node _T_4571 = cat(_T_4570, way_status_out[35]) @[Cat.scala 29:58] + node _T_4572 = cat(_T_4571, way_status_out[34]) @[Cat.scala 29:58] + node _T_4573 = cat(_T_4572, way_status_out[33]) @[Cat.scala 29:58] + node _T_4574 = cat(_T_4573, way_status_out[32]) @[Cat.scala 29:58] + node _T_4575 = cat(_T_4574, way_status_out[31]) @[Cat.scala 29:58] + node _T_4576 = cat(_T_4575, way_status_out[30]) @[Cat.scala 29:58] + node _T_4577 = cat(_T_4576, way_status_out[29]) @[Cat.scala 29:58] + node _T_4578 = cat(_T_4577, way_status_out[28]) @[Cat.scala 29:58] + node _T_4579 = cat(_T_4578, way_status_out[27]) @[Cat.scala 29:58] + node _T_4580 = cat(_T_4579, way_status_out[26]) @[Cat.scala 29:58] + node _T_4581 = cat(_T_4580, way_status_out[25]) @[Cat.scala 29:58] + node _T_4582 = cat(_T_4581, way_status_out[24]) @[Cat.scala 29:58] + node _T_4583 = cat(_T_4582, way_status_out[23]) @[Cat.scala 29:58] + node _T_4584 = cat(_T_4583, way_status_out[22]) @[Cat.scala 29:58] + node _T_4585 = cat(_T_4584, way_status_out[21]) @[Cat.scala 29:58] + node _T_4586 = cat(_T_4585, way_status_out[20]) @[Cat.scala 29:58] + node _T_4587 = cat(_T_4586, way_status_out[19]) @[Cat.scala 29:58] + node _T_4588 = cat(_T_4587, way_status_out[18]) @[Cat.scala 29:58] + node _T_4589 = cat(_T_4588, way_status_out[17]) @[Cat.scala 29:58] + node _T_4590 = cat(_T_4589, way_status_out[16]) @[Cat.scala 29:58] + node _T_4591 = cat(_T_4590, way_status_out[15]) @[Cat.scala 29:58] + node _T_4592 = cat(_T_4591, way_status_out[14]) @[Cat.scala 29:58] + node _T_4593 = cat(_T_4592, way_status_out[13]) @[Cat.scala 29:58] + node _T_4594 = cat(_T_4593, way_status_out[12]) @[Cat.scala 29:58] + node _T_4595 = cat(_T_4594, way_status_out[11]) @[Cat.scala 29:58] + node _T_4596 = cat(_T_4595, way_status_out[10]) @[Cat.scala 29:58] + node _T_4597 = cat(_T_4596, way_status_out[9]) @[Cat.scala 29:58] + node _T_4598 = cat(_T_4597, way_status_out[8]) @[Cat.scala 29:58] + node _T_4599 = cat(_T_4598, way_status_out[7]) @[Cat.scala 29:58] + node _T_4600 = cat(_T_4599, way_status_out[6]) @[Cat.scala 29:58] + node _T_4601 = cat(_T_4600, way_status_out[5]) @[Cat.scala 29:58] + node _T_4602 = cat(_T_4601, way_status_out[4]) @[Cat.scala 29:58] + node _T_4603 = cat(_T_4602, way_status_out[3]) @[Cat.scala 29:58] + node _T_4604 = cat(_T_4603, way_status_out[2]) @[Cat.scala 29:58] + node _T_4605 = cat(_T_4604, way_status_out[1]) @[Cat.scala 29:58] + node test_way_status_out = cat(_T_4605, way_status_out[0]) @[Cat.scala 29:58] + node _T_4606 = cat(way_status_clken_15, way_status_clken_14) @[Cat.scala 29:58] + node _T_4607 = cat(_T_4606, way_status_clken_13) @[Cat.scala 29:58] + node _T_4608 = cat(_T_4607, way_status_clken_12) @[Cat.scala 29:58] + node _T_4609 = cat(_T_4608, way_status_clken_11) @[Cat.scala 29:58] + node _T_4610 = cat(_T_4609, way_status_clken_10) @[Cat.scala 29:58] + node _T_4611 = cat(_T_4610, way_status_clken_9) @[Cat.scala 29:58] + node _T_4612 = cat(_T_4611, way_status_clken_8) @[Cat.scala 29:58] + node _T_4613 = cat(_T_4612, way_status_clken_7) @[Cat.scala 29:58] + node _T_4614 = cat(_T_4613, way_status_clken_6) @[Cat.scala 29:58] + node _T_4615 = cat(_T_4614, way_status_clken_5) @[Cat.scala 29:58] + node _T_4616 = cat(_T_4615, way_status_clken_4) @[Cat.scala 29:58] + node _T_4617 = cat(_T_4616, way_status_clken_3) @[Cat.scala 29:58] + node _T_4618 = cat(_T_4617, way_status_clken_2) @[Cat.scala 29:58] + node _T_4619 = cat(_T_4618, way_status_clken_1) @[Cat.scala 29:58] + node test_way_status_clken = cat(_T_4619, way_status_clken_0) @[Cat.scala 29:58] + node _T_4620 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4621 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4622 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4623 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4624 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4625 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4626 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4627 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4628 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4629 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4630 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4631 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4632 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4633 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4634 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4635 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4636 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h010")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4637 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h011")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4638 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h012")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4639 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h013")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4640 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h014")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4641 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h015")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4642 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h016")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4643 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h017")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4644 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h018")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4645 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h019")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4646 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01a")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4647 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01b")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4648 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01c")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4649 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01d")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4650 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01e")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4651 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01f")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4652 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h020")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4653 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h021")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4654 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h022")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4655 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h023")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4656 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h024")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4657 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h025")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4658 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h026")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4659 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h027")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4660 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h028")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4661 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h029")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4662 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02a")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4663 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02b")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4664 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02c")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4665 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02d")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4666 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02e")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4667 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02f")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4668 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h030")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4669 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h031")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4670 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h032")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4671 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h033")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4672 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h034")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4673 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h035")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4674 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h036")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4675 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h037")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4676 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h038")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4677 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h039")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4678 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03a")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4679 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03b")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4680 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03c")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4681 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03d")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4682 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03e")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4683 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03f")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4684 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h040")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4685 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h041")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4686 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h042")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4687 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h043")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4688 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h044")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4689 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h045")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4690 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h046")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4691 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h047")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4692 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h048")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4693 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h049")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4694 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04a")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4695 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04b")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4696 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04c")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4697 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04d")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4698 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04e")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4699 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04f")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4700 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h050")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4701 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h051")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4702 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h052")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4703 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h053")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4704 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h054")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4705 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h055")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4706 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h056")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4707 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h057")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4708 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h058")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4709 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h059")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4710 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05a")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4711 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05b")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4712 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05c")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4713 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05d")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4714 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05e")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4715 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05f")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4716 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h060")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4717 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h061")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4718 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h062")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4719 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h063")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4720 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h064")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4721 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h065")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4722 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h066")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4723 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h067")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4724 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h068")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4725 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h069")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4726 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06a")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4727 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06b")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4728 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06c")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4729 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06d")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4730 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06e")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4731 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06f")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4732 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h070")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4733 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h071")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4734 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h072")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4735 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h073")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4736 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h074")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4737 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h075")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4738 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h076")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4739 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h077")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4740 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h078")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4741 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h079")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4742 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07a")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4743 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07b")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4744 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07c")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4745 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07d")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4746 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07e")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4747 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07f")) @[el2_ifu_mem_ctl.scala 733:80] + node _T_4748 = mux(_T_4620, way_status_out[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4749 = mux(_T_4621, way_status_out[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4750 = mux(_T_4622, way_status_out[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4751 = mux(_T_4623, way_status_out[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4752 = mux(_T_4624, way_status_out[4], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4753 = mux(_T_4625, way_status_out[5], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4754 = mux(_T_4626, way_status_out[6], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4755 = mux(_T_4627, way_status_out[7], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4756 = mux(_T_4628, way_status_out[8], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4757 = mux(_T_4629, way_status_out[9], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4758 = mux(_T_4630, way_status_out[10], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4759 = mux(_T_4631, way_status_out[11], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4760 = mux(_T_4632, way_status_out[12], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4761 = mux(_T_4633, way_status_out[13], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4762 = mux(_T_4634, way_status_out[14], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4763 = mux(_T_4635, way_status_out[15], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4764 = mux(_T_4636, way_status_out[16], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4765 = mux(_T_4637, way_status_out[17], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4766 = mux(_T_4638, way_status_out[18], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4767 = mux(_T_4639, way_status_out[19], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4768 = mux(_T_4640, way_status_out[20], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4769 = mux(_T_4641, way_status_out[21], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4770 = mux(_T_4642, way_status_out[22], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4771 = mux(_T_4643, way_status_out[23], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4772 = mux(_T_4644, way_status_out[24], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4773 = mux(_T_4645, way_status_out[25], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4774 = mux(_T_4646, way_status_out[26], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4775 = mux(_T_4647, way_status_out[27], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4776 = mux(_T_4648, way_status_out[28], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4777 = mux(_T_4649, way_status_out[29], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4778 = mux(_T_4650, way_status_out[30], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4779 = mux(_T_4651, way_status_out[31], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4780 = mux(_T_4652, way_status_out[32], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4781 = mux(_T_4653, way_status_out[33], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4782 = mux(_T_4654, way_status_out[34], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4783 = mux(_T_4655, way_status_out[35], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4784 = mux(_T_4656, way_status_out[36], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4785 = mux(_T_4657, way_status_out[37], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4786 = mux(_T_4658, way_status_out[38], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4787 = mux(_T_4659, way_status_out[39], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4788 = mux(_T_4660, way_status_out[40], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4789 = mux(_T_4661, way_status_out[41], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4790 = mux(_T_4662, way_status_out[42], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4791 = mux(_T_4663, way_status_out[43], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4792 = mux(_T_4664, way_status_out[44], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4793 = mux(_T_4665, way_status_out[45], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4794 = mux(_T_4666, way_status_out[46], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4795 = mux(_T_4667, way_status_out[47], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4796 = mux(_T_4668, way_status_out[48], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4797 = mux(_T_4669, way_status_out[49], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4798 = mux(_T_4670, way_status_out[50], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4799 = mux(_T_4671, way_status_out[51], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4800 = mux(_T_4672, way_status_out[52], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4801 = mux(_T_4673, way_status_out[53], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4802 = mux(_T_4674, way_status_out[54], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4803 = mux(_T_4675, way_status_out[55], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4804 = mux(_T_4676, way_status_out[56], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4805 = mux(_T_4677, way_status_out[57], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4806 = mux(_T_4678, way_status_out[58], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4807 = mux(_T_4679, way_status_out[59], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4808 = mux(_T_4680, way_status_out[60], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4809 = mux(_T_4681, way_status_out[61], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4810 = mux(_T_4682, way_status_out[62], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4811 = mux(_T_4683, way_status_out[63], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4812 = mux(_T_4684, way_status_out[64], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4813 = mux(_T_4685, way_status_out[65], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4814 = mux(_T_4686, way_status_out[66], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4815 = mux(_T_4687, way_status_out[67], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4816 = mux(_T_4688, way_status_out[68], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4817 = mux(_T_4689, way_status_out[69], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4818 = mux(_T_4690, way_status_out[70], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4819 = mux(_T_4691, way_status_out[71], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4820 = mux(_T_4692, way_status_out[72], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4821 = mux(_T_4693, way_status_out[73], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4822 = mux(_T_4694, way_status_out[74], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4823 = mux(_T_4695, way_status_out[75], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4824 = mux(_T_4696, way_status_out[76], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4825 = mux(_T_4697, way_status_out[77], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4826 = mux(_T_4698, way_status_out[78], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4827 = mux(_T_4699, way_status_out[79], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4828 = mux(_T_4700, way_status_out[80], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4829 = mux(_T_4701, way_status_out[81], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4830 = mux(_T_4702, way_status_out[82], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4831 = mux(_T_4703, way_status_out[83], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4832 = mux(_T_4704, way_status_out[84], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4833 = mux(_T_4705, way_status_out[85], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4834 = mux(_T_4706, way_status_out[86], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4835 = mux(_T_4707, way_status_out[87], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4836 = mux(_T_4708, way_status_out[88], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4837 = mux(_T_4709, way_status_out[89], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4838 = mux(_T_4710, way_status_out[90], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4839 = mux(_T_4711, way_status_out[91], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4840 = mux(_T_4712, way_status_out[92], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4841 = mux(_T_4713, way_status_out[93], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4842 = mux(_T_4714, way_status_out[94], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4843 = mux(_T_4715, way_status_out[95], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4844 = mux(_T_4716, way_status_out[96], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4845 = mux(_T_4717, way_status_out[97], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4846 = mux(_T_4718, way_status_out[98], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4847 = mux(_T_4719, way_status_out[99], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4848 = mux(_T_4720, way_status_out[100], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4849 = mux(_T_4721, way_status_out[101], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4850 = mux(_T_4722, way_status_out[102], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4851 = mux(_T_4723, way_status_out[103], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4852 = mux(_T_4724, way_status_out[104], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4853 = mux(_T_4725, way_status_out[105], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4854 = mux(_T_4726, way_status_out[106], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4855 = mux(_T_4727, way_status_out[107], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4856 = mux(_T_4728, way_status_out[108], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4857 = mux(_T_4729, way_status_out[109], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4858 = mux(_T_4730, way_status_out[110], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4859 = mux(_T_4731, way_status_out[111], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4860 = mux(_T_4732, way_status_out[112], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4861 = mux(_T_4733, way_status_out[113], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4862 = mux(_T_4734, way_status_out[114], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4863 = mux(_T_4735, way_status_out[115], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4864 = mux(_T_4736, way_status_out[116], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4865 = mux(_T_4737, way_status_out[117], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4866 = mux(_T_4738, way_status_out[118], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4867 = mux(_T_4739, way_status_out[119], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4868 = mux(_T_4740, way_status_out[120], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4869 = mux(_T_4741, way_status_out[121], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4870 = mux(_T_4742, way_status_out[122], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4871 = mux(_T_4743, way_status_out[123], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4872 = mux(_T_4744, way_status_out[124], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4873 = mux(_T_4745, way_status_out[125], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4874 = mux(_T_4746, way_status_out[126], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4875 = mux(_T_4747, way_status_out[127], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4876 = or(_T_4748, _T_4749) @[Mux.scala 27:72] + node _T_4877 = or(_T_4876, _T_4750) @[Mux.scala 27:72] + node _T_4878 = or(_T_4877, _T_4751) @[Mux.scala 27:72] + node _T_4879 = or(_T_4878, _T_4752) @[Mux.scala 27:72] + node _T_4880 = or(_T_4879, _T_4753) @[Mux.scala 27:72] + node _T_4881 = or(_T_4880, _T_4754) @[Mux.scala 27:72] + node _T_4882 = or(_T_4881, _T_4755) @[Mux.scala 27:72] + node _T_4883 = or(_T_4882, _T_4756) @[Mux.scala 27:72] + node _T_4884 = or(_T_4883, _T_4757) @[Mux.scala 27:72] + node _T_4885 = or(_T_4884, _T_4758) @[Mux.scala 27:72] + node _T_4886 = or(_T_4885, _T_4759) @[Mux.scala 27:72] + node _T_4887 = or(_T_4886, _T_4760) @[Mux.scala 27:72] + node _T_4888 = or(_T_4887, _T_4761) @[Mux.scala 27:72] + node _T_4889 = or(_T_4888, _T_4762) @[Mux.scala 27:72] + node _T_4890 = or(_T_4889, _T_4763) @[Mux.scala 27:72] + node _T_4891 = or(_T_4890, _T_4764) @[Mux.scala 27:72] + node _T_4892 = or(_T_4891, _T_4765) @[Mux.scala 27:72] + node _T_4893 = or(_T_4892, _T_4766) @[Mux.scala 27:72] + node _T_4894 = or(_T_4893, _T_4767) @[Mux.scala 27:72] + node _T_4895 = or(_T_4894, _T_4768) @[Mux.scala 27:72] + node _T_4896 = or(_T_4895, _T_4769) @[Mux.scala 27:72] + node _T_4897 = or(_T_4896, _T_4770) @[Mux.scala 27:72] + node _T_4898 = or(_T_4897, _T_4771) @[Mux.scala 27:72] + node _T_4899 = or(_T_4898, _T_4772) @[Mux.scala 27:72] + node _T_4900 = or(_T_4899, _T_4773) @[Mux.scala 27:72] + node _T_4901 = or(_T_4900, _T_4774) @[Mux.scala 27:72] + node _T_4902 = or(_T_4901, _T_4775) @[Mux.scala 27:72] + node _T_4903 = or(_T_4902, _T_4776) @[Mux.scala 27:72] + node _T_4904 = or(_T_4903, _T_4777) @[Mux.scala 27:72] + node _T_4905 = or(_T_4904, _T_4778) @[Mux.scala 27:72] + node _T_4906 = or(_T_4905, _T_4779) @[Mux.scala 27:72] + node _T_4907 = or(_T_4906, _T_4780) @[Mux.scala 27:72] + node _T_4908 = or(_T_4907, _T_4781) @[Mux.scala 27:72] + node _T_4909 = or(_T_4908, _T_4782) @[Mux.scala 27:72] + node _T_4910 = or(_T_4909, _T_4783) @[Mux.scala 27:72] + node _T_4911 = or(_T_4910, _T_4784) @[Mux.scala 27:72] + node _T_4912 = or(_T_4911, _T_4785) @[Mux.scala 27:72] + node _T_4913 = or(_T_4912, _T_4786) @[Mux.scala 27:72] + node _T_4914 = or(_T_4913, _T_4787) @[Mux.scala 27:72] + node _T_4915 = or(_T_4914, _T_4788) @[Mux.scala 27:72] + node _T_4916 = or(_T_4915, _T_4789) @[Mux.scala 27:72] + node _T_4917 = or(_T_4916, _T_4790) @[Mux.scala 27:72] + node _T_4918 = or(_T_4917, _T_4791) @[Mux.scala 27:72] + node _T_4919 = or(_T_4918, _T_4792) @[Mux.scala 27:72] + node _T_4920 = or(_T_4919, _T_4793) @[Mux.scala 27:72] + node _T_4921 = or(_T_4920, _T_4794) @[Mux.scala 27:72] + node _T_4922 = or(_T_4921, _T_4795) @[Mux.scala 27:72] + node _T_4923 = or(_T_4922, _T_4796) @[Mux.scala 27:72] + node _T_4924 = or(_T_4923, _T_4797) @[Mux.scala 27:72] + node _T_4925 = or(_T_4924, _T_4798) @[Mux.scala 27:72] + node _T_4926 = or(_T_4925, _T_4799) @[Mux.scala 27:72] + node _T_4927 = or(_T_4926, _T_4800) @[Mux.scala 27:72] + node _T_4928 = or(_T_4927, _T_4801) @[Mux.scala 27:72] + node _T_4929 = or(_T_4928, _T_4802) @[Mux.scala 27:72] + node _T_4930 = or(_T_4929, _T_4803) @[Mux.scala 27:72] + node _T_4931 = or(_T_4930, _T_4804) @[Mux.scala 27:72] + node _T_4932 = or(_T_4931, _T_4805) @[Mux.scala 27:72] + node _T_4933 = or(_T_4932, _T_4806) @[Mux.scala 27:72] + node _T_4934 = or(_T_4933, _T_4807) @[Mux.scala 27:72] + node _T_4935 = or(_T_4934, _T_4808) @[Mux.scala 27:72] + node _T_4936 = or(_T_4935, _T_4809) @[Mux.scala 27:72] + node _T_4937 = or(_T_4936, _T_4810) @[Mux.scala 27:72] + node _T_4938 = or(_T_4937, _T_4811) @[Mux.scala 27:72] + node _T_4939 = or(_T_4938, _T_4812) @[Mux.scala 27:72] + node _T_4940 = or(_T_4939, _T_4813) @[Mux.scala 27:72] + node _T_4941 = or(_T_4940, _T_4814) @[Mux.scala 27:72] + node _T_4942 = or(_T_4941, _T_4815) @[Mux.scala 27:72] + node _T_4943 = or(_T_4942, _T_4816) @[Mux.scala 27:72] + node _T_4944 = or(_T_4943, _T_4817) @[Mux.scala 27:72] + node _T_4945 = or(_T_4944, _T_4818) @[Mux.scala 27:72] + node _T_4946 = or(_T_4945, _T_4819) @[Mux.scala 27:72] + node _T_4947 = or(_T_4946, _T_4820) @[Mux.scala 27:72] + node _T_4948 = or(_T_4947, _T_4821) @[Mux.scala 27:72] + node _T_4949 = or(_T_4948, _T_4822) @[Mux.scala 27:72] + node _T_4950 = or(_T_4949, _T_4823) @[Mux.scala 27:72] + node _T_4951 = or(_T_4950, _T_4824) @[Mux.scala 27:72] + node _T_4952 = or(_T_4951, _T_4825) @[Mux.scala 27:72] + node _T_4953 = or(_T_4952, _T_4826) @[Mux.scala 27:72] + node _T_4954 = or(_T_4953, _T_4827) @[Mux.scala 27:72] + node _T_4955 = or(_T_4954, _T_4828) @[Mux.scala 27:72] + node _T_4956 = or(_T_4955, _T_4829) @[Mux.scala 27:72] + node _T_4957 = or(_T_4956, _T_4830) @[Mux.scala 27:72] + node _T_4958 = or(_T_4957, _T_4831) @[Mux.scala 27:72] + node _T_4959 = or(_T_4958, _T_4832) @[Mux.scala 27:72] + node _T_4960 = or(_T_4959, _T_4833) @[Mux.scala 27:72] + node _T_4961 = or(_T_4960, _T_4834) @[Mux.scala 27:72] + node _T_4962 = or(_T_4961, _T_4835) @[Mux.scala 27:72] + node _T_4963 = or(_T_4962, _T_4836) @[Mux.scala 27:72] + node _T_4964 = or(_T_4963, _T_4837) @[Mux.scala 27:72] + node _T_4965 = or(_T_4964, _T_4838) @[Mux.scala 27:72] + node _T_4966 = or(_T_4965, _T_4839) @[Mux.scala 27:72] + node _T_4967 = or(_T_4966, _T_4840) @[Mux.scala 27:72] + node _T_4968 = or(_T_4967, _T_4841) @[Mux.scala 27:72] + node _T_4969 = or(_T_4968, _T_4842) @[Mux.scala 27:72] + node _T_4970 = or(_T_4969, _T_4843) @[Mux.scala 27:72] + node _T_4971 = or(_T_4970, _T_4844) @[Mux.scala 27:72] + node _T_4972 = or(_T_4971, _T_4845) @[Mux.scala 27:72] + node _T_4973 = or(_T_4972, _T_4846) @[Mux.scala 27:72] + node _T_4974 = or(_T_4973, _T_4847) @[Mux.scala 27:72] + node _T_4975 = or(_T_4974, _T_4848) @[Mux.scala 27:72] + node _T_4976 = or(_T_4975, _T_4849) @[Mux.scala 27:72] + node _T_4977 = or(_T_4976, _T_4850) @[Mux.scala 27:72] + node _T_4978 = or(_T_4977, _T_4851) @[Mux.scala 27:72] + node _T_4979 = or(_T_4978, _T_4852) @[Mux.scala 27:72] + node _T_4980 = or(_T_4979, _T_4853) @[Mux.scala 27:72] + node _T_4981 = or(_T_4980, _T_4854) @[Mux.scala 27:72] + node _T_4982 = or(_T_4981, _T_4855) @[Mux.scala 27:72] + node _T_4983 = or(_T_4982, _T_4856) @[Mux.scala 27:72] + node _T_4984 = or(_T_4983, _T_4857) @[Mux.scala 27:72] + node _T_4985 = or(_T_4984, _T_4858) @[Mux.scala 27:72] + node _T_4986 = or(_T_4985, _T_4859) @[Mux.scala 27:72] + node _T_4987 = or(_T_4986, _T_4860) @[Mux.scala 27:72] + node _T_4988 = or(_T_4987, _T_4861) @[Mux.scala 27:72] + node _T_4989 = or(_T_4988, _T_4862) @[Mux.scala 27:72] + node _T_4990 = or(_T_4989, _T_4863) @[Mux.scala 27:72] + node _T_4991 = or(_T_4990, _T_4864) @[Mux.scala 27:72] + node _T_4992 = or(_T_4991, _T_4865) @[Mux.scala 27:72] + node _T_4993 = or(_T_4992, _T_4866) @[Mux.scala 27:72] + node _T_4994 = or(_T_4993, _T_4867) @[Mux.scala 27:72] + node _T_4995 = or(_T_4994, _T_4868) @[Mux.scala 27:72] + node _T_4996 = or(_T_4995, _T_4869) @[Mux.scala 27:72] + node _T_4997 = or(_T_4996, _T_4870) @[Mux.scala 27:72] + node _T_4998 = or(_T_4997, _T_4871) @[Mux.scala 27:72] + node _T_4999 = or(_T_4998, _T_4872) @[Mux.scala 27:72] + node _T_5000 = or(_T_4999, _T_4873) @[Mux.scala 27:72] + node _T_5001 = or(_T_5000, _T_4874) @[Mux.scala 27:72] + node _T_5002 = or(_T_5001, _T_4875) @[Mux.scala 27:72] + wire _T_5003 : UInt<1> @[Mux.scala 27:72] + _T_5003 <= _T_5002 @[Mux.scala 27:72] + way_status <= _T_5003 @[el2_ifu_mem_ctl.scala 733:14] + node _T_5004 = or(io.ic_debug_rd_en, io.ic_debug_wr_en) @[el2_ifu_mem_ctl.scala 734:59] + node _T_5005 = and(_T_5004, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 734:80] + node _T_5006 = bits(io.ic_debug_addr, 9, 3) @[el2_ifu_mem_ctl.scala 735:21] + node _T_5007 = bits(ifu_ic_rw_int_addr, 11, 5) @[el2_ifu_mem_ctl.scala 735:87] + node ifu_ic_rw_int_addr_w_debug = mux(_T_5005, _T_5006, _T_5007) @[el2_ifu_mem_ctl.scala 734:39] + reg _T_5008 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 737:12] + _T_5008 <= ifu_ic_rw_int_addr_w_debug @[el2_ifu_mem_ctl.scala 737:12] + ifu_ic_rw_int_addr_ff <= _T_5008 @[el2_ifu_mem_ctl.scala 736:25] + wire ifu_tag_wren : UInt<2> + ifu_tag_wren <= UInt<1>("h00") + wire ic_debug_tag_wr_en : UInt<2> + ic_debug_tag_wr_en <= UInt<1>("h00") + node ifu_tag_wren_w_debug = or(ifu_tag_wren, ic_debug_tag_wr_en) @[el2_ifu_mem_ctl.scala 741:43] + reg ifu_tag_wren_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 743:12] + ifu_tag_wren_ff <= ifu_tag_wren_w_debug @[el2_ifu_mem_ctl.scala 743:12] + node _T_5009 = and(io.ic_debug_wr_en, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 745:48] + node _T_5010 = bits(io.ic_debug_wr_data, 0, 0) @[el2_ifu_mem_ctl.scala 745:92] + node ic_valid_w_debug = mux(_T_5009, _T_5010, ic_valid) @[el2_ifu_mem_ctl.scala 745:29] + reg ic_valid_ff : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 747:12] + ic_valid_ff <= ic_valid_w_debug @[el2_ifu_mem_ctl.scala 747:12] + node _T_5011 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[el2_ifu_mem_ctl.scala 751:33] + node _T_5012 = eq(_T_5011, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 751:76] + node _T_5013 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 751:102] + node _T_5014 = and(_T_5012, _T_5013) @[el2_ifu_mem_ctl.scala 751:85] + node _T_5015 = bits(perr_ic_index_ff, 6, 5) @[el2_ifu_mem_ctl.scala 752:25] + node _T_5016 = eq(_T_5015, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 752:68] + node _T_5017 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 752:95] + node _T_5018 = and(_T_5016, _T_5017) @[el2_ifu_mem_ctl.scala 752:77] + node _T_5019 = or(_T_5014, _T_5018) @[el2_ifu_mem_ctl.scala 751:107] + node _T_5020 = or(_T_5019, reset_all_tags) @[el2_ifu_mem_ctl.scala 752:100] + node _T_5021 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[el2_ifu_mem_ctl.scala 751:33] + node _T_5022 = eq(_T_5021, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 751:76] + node _T_5023 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 751:102] + node _T_5024 = and(_T_5022, _T_5023) @[el2_ifu_mem_ctl.scala 751:85] + node _T_5025 = bits(perr_ic_index_ff, 6, 5) @[el2_ifu_mem_ctl.scala 752:25] + node _T_5026 = eq(_T_5025, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 752:68] + node _T_5027 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 752:95] + node _T_5028 = and(_T_5026, _T_5027) @[el2_ifu_mem_ctl.scala 752:77] + node _T_5029 = or(_T_5024, _T_5028) @[el2_ifu_mem_ctl.scala 751:107] + node _T_5030 = or(_T_5029, reset_all_tags) @[el2_ifu_mem_ctl.scala 752:100] + node tag_valid_clken_0 = cat(_T_5030, _T_5020) @[Cat.scala 29:58] + node _T_5031 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[el2_ifu_mem_ctl.scala 751:33] + node _T_5032 = eq(_T_5031, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 751:76] + node _T_5033 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 751:102] + node _T_5034 = and(_T_5032, _T_5033) @[el2_ifu_mem_ctl.scala 751:85] + node _T_5035 = bits(perr_ic_index_ff, 6, 5) @[el2_ifu_mem_ctl.scala 752:25] + node _T_5036 = eq(_T_5035, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 752:68] + node _T_5037 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 752:95] + node _T_5038 = and(_T_5036, _T_5037) @[el2_ifu_mem_ctl.scala 752:77] + node _T_5039 = or(_T_5034, _T_5038) @[el2_ifu_mem_ctl.scala 751:107] + node _T_5040 = or(_T_5039, reset_all_tags) @[el2_ifu_mem_ctl.scala 752:100] + node _T_5041 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[el2_ifu_mem_ctl.scala 751:33] + node _T_5042 = eq(_T_5041, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 751:76] + node _T_5043 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 751:102] + node _T_5044 = and(_T_5042, _T_5043) @[el2_ifu_mem_ctl.scala 751:85] + node _T_5045 = bits(perr_ic_index_ff, 6, 5) @[el2_ifu_mem_ctl.scala 752:25] + node _T_5046 = eq(_T_5045, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 752:68] + node _T_5047 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 752:95] + node _T_5048 = and(_T_5046, _T_5047) @[el2_ifu_mem_ctl.scala 752:77] + node _T_5049 = or(_T_5044, _T_5048) @[el2_ifu_mem_ctl.scala 751:107] + node _T_5050 = or(_T_5049, reset_all_tags) @[el2_ifu_mem_ctl.scala 752:100] + node tag_valid_clken_1 = cat(_T_5050, _T_5040) @[Cat.scala 29:58] + node _T_5051 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[el2_ifu_mem_ctl.scala 751:33] + node _T_5052 = eq(_T_5051, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 751:76] + node _T_5053 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 751:102] + node _T_5054 = and(_T_5052, _T_5053) @[el2_ifu_mem_ctl.scala 751:85] + node _T_5055 = bits(perr_ic_index_ff, 6, 5) @[el2_ifu_mem_ctl.scala 752:25] + node _T_5056 = eq(_T_5055, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 752:68] + node _T_5057 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 752:95] + node _T_5058 = and(_T_5056, _T_5057) @[el2_ifu_mem_ctl.scala 752:77] + node _T_5059 = or(_T_5054, _T_5058) @[el2_ifu_mem_ctl.scala 751:107] + node _T_5060 = or(_T_5059, reset_all_tags) @[el2_ifu_mem_ctl.scala 752:100] + node _T_5061 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[el2_ifu_mem_ctl.scala 751:33] + node _T_5062 = eq(_T_5061, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 751:76] + node _T_5063 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 751:102] + node _T_5064 = and(_T_5062, _T_5063) @[el2_ifu_mem_ctl.scala 751:85] + node _T_5065 = bits(perr_ic_index_ff, 6, 5) @[el2_ifu_mem_ctl.scala 752:25] + node _T_5066 = eq(_T_5065, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 752:68] + node _T_5067 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 752:95] + node _T_5068 = and(_T_5066, _T_5067) @[el2_ifu_mem_ctl.scala 752:77] + node _T_5069 = or(_T_5064, _T_5068) @[el2_ifu_mem_ctl.scala 751:107] + node _T_5070 = or(_T_5069, reset_all_tags) @[el2_ifu_mem_ctl.scala 752:100] + node tag_valid_clken_2 = cat(_T_5070, _T_5060) @[Cat.scala 29:58] + node _T_5071 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[el2_ifu_mem_ctl.scala 751:33] + node _T_5072 = eq(_T_5071, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 751:76] + node _T_5073 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 751:102] + node _T_5074 = and(_T_5072, _T_5073) @[el2_ifu_mem_ctl.scala 751:85] + node _T_5075 = bits(perr_ic_index_ff, 6, 5) @[el2_ifu_mem_ctl.scala 752:25] + node _T_5076 = eq(_T_5075, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 752:68] + node _T_5077 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 752:95] + node _T_5078 = and(_T_5076, _T_5077) @[el2_ifu_mem_ctl.scala 752:77] + node _T_5079 = or(_T_5074, _T_5078) @[el2_ifu_mem_ctl.scala 751:107] + node _T_5080 = or(_T_5079, reset_all_tags) @[el2_ifu_mem_ctl.scala 752:100] + node _T_5081 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[el2_ifu_mem_ctl.scala 751:33] + node _T_5082 = eq(_T_5081, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 751:76] + node _T_5083 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 751:102] + node _T_5084 = and(_T_5082, _T_5083) @[el2_ifu_mem_ctl.scala 751:85] + node _T_5085 = bits(perr_ic_index_ff, 6, 5) @[el2_ifu_mem_ctl.scala 752:25] + node _T_5086 = eq(_T_5085, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 752:68] + node _T_5087 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 752:95] + node _T_5088 = and(_T_5086, _T_5087) @[el2_ifu_mem_ctl.scala 752:77] + node _T_5089 = or(_T_5084, _T_5088) @[el2_ifu_mem_ctl.scala 751:107] + node _T_5090 = or(_T_5089, reset_all_tags) @[el2_ifu_mem_ctl.scala 752:100] + node tag_valid_clken_3 = cat(_T_5090, _T_5080) @[Cat.scala 29:58] + node _T_5091 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 754:133] + inst rvclkhdr_86 of rvclkhdr_86 @[el2_lib.scala 483:22] + rvclkhdr_86.clock <= clock + rvclkhdr_86.reset <= reset + rvclkhdr_86.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_86.io.en <= _T_5091 @[el2_lib.scala 485:16] + rvclkhdr_86.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + node _T_5092 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 754:133] + inst rvclkhdr_87 of rvclkhdr_87 @[el2_lib.scala 483:22] + rvclkhdr_87.clock <= clock + rvclkhdr_87.reset <= reset + rvclkhdr_87.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_87.io.en <= _T_5092 @[el2_lib.scala 485:16] + rvclkhdr_87.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + node _T_5093 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 754:133] + inst rvclkhdr_88 of rvclkhdr_88 @[el2_lib.scala 483:22] + rvclkhdr_88.clock <= clock + rvclkhdr_88.reset <= reset + rvclkhdr_88.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_88.io.en <= _T_5093 @[el2_lib.scala 485:16] + rvclkhdr_88.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + node _T_5094 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 754:133] + inst rvclkhdr_89 of rvclkhdr_89 @[el2_lib.scala 483:22] + rvclkhdr_89.clock <= clock + rvclkhdr_89.reset <= reset + rvclkhdr_89.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_89.io.en <= _T_5094 @[el2_lib.scala 485:16] + rvclkhdr_89.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + node _T_5095 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 754:133] + inst rvclkhdr_90 of rvclkhdr_90 @[el2_lib.scala 483:22] + rvclkhdr_90.clock <= clock + rvclkhdr_90.reset <= reset + rvclkhdr_90.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_90.io.en <= _T_5095 @[el2_lib.scala 485:16] + rvclkhdr_90.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + node _T_5096 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 754:133] + inst rvclkhdr_91 of rvclkhdr_91 @[el2_lib.scala 483:22] + rvclkhdr_91.clock <= clock + rvclkhdr_91.reset <= reset + rvclkhdr_91.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_91.io.en <= _T_5096 @[el2_lib.scala 485:16] + rvclkhdr_91.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + node _T_5097 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 754:133] + inst rvclkhdr_92 of rvclkhdr_92 @[el2_lib.scala 483:22] + rvclkhdr_92.clock <= clock + rvclkhdr_92.reset <= reset + rvclkhdr_92.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_92.io.en <= _T_5097 @[el2_lib.scala 485:16] + rvclkhdr_92.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + node _T_5098 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 754:133] + inst rvclkhdr_93 of rvclkhdr_93 @[el2_lib.scala 483:22] + rvclkhdr_93.clock <= clock + rvclkhdr_93.reset <= reset + rvclkhdr_93.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_93.io.en <= _T_5098 @[el2_lib.scala 485:16] + rvclkhdr_93.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + wire ic_tag_valid_out : UInt<1>[128][2] @[el2_ifu_mem_ctl.scala 755:30] + node _T_5099 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5100 = eq(_T_5099, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5101 = and(ic_valid_ff, _T_5100) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5102 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5103 = and(_T_5101, _T_5102) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5104 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5105 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5106 = and(_T_5104, _T_5105) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5107 = eq(perr_ic_index_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5108 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5109 = and(_T_5107, _T_5108) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5110 = or(_T_5106, _T_5109) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5111 = or(_T_5110, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5112 = bits(_T_5111, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5113 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5112 : @[Reg.scala 28:19] + _T_5113 <= _T_5103 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][0] <= _T_5113 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5114 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5115 = eq(_T_5114, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5116 = and(ic_valid_ff, _T_5115) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5117 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5118 = and(_T_5116, _T_5117) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5119 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5120 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5121 = and(_T_5119, _T_5120) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5122 = eq(perr_ic_index_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5123 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5124 = and(_T_5122, _T_5123) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5125 = or(_T_5121, _T_5124) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5126 = or(_T_5125, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5127 = bits(_T_5126, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5128 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5127 : @[Reg.scala 28:19] + _T_5128 <= _T_5118 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][1] <= _T_5128 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5129 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5130 = eq(_T_5129, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5131 = and(ic_valid_ff, _T_5130) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5132 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5133 = and(_T_5131, _T_5132) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5134 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5135 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5136 = and(_T_5134, _T_5135) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5137 = eq(perr_ic_index_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5138 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5139 = and(_T_5137, _T_5138) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5140 = or(_T_5136, _T_5139) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5141 = or(_T_5140, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5142 = bits(_T_5141, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5143 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5142 : @[Reg.scala 28:19] + _T_5143 <= _T_5133 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][2] <= _T_5143 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5144 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5145 = eq(_T_5144, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5146 = and(ic_valid_ff, _T_5145) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5147 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5148 = and(_T_5146, _T_5147) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5149 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5150 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5151 = and(_T_5149, _T_5150) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5152 = eq(perr_ic_index_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5153 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5154 = and(_T_5152, _T_5153) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5155 = or(_T_5151, _T_5154) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5156 = or(_T_5155, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5157 = bits(_T_5156, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5158 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5157 : @[Reg.scala 28:19] + _T_5158 <= _T_5148 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][3] <= _T_5158 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5159 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5160 = eq(_T_5159, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5161 = and(ic_valid_ff, _T_5160) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5162 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5163 = and(_T_5161, _T_5162) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5164 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5165 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5166 = and(_T_5164, _T_5165) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5167 = eq(perr_ic_index_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5168 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5169 = and(_T_5167, _T_5168) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5170 = or(_T_5166, _T_5169) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5171 = or(_T_5170, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5172 = bits(_T_5171, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5173 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5172 : @[Reg.scala 28:19] + _T_5173 <= _T_5163 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][4] <= _T_5173 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5174 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5175 = eq(_T_5174, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5176 = and(ic_valid_ff, _T_5175) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5177 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5178 = and(_T_5176, _T_5177) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5179 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5180 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5181 = and(_T_5179, _T_5180) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5182 = eq(perr_ic_index_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5183 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5184 = and(_T_5182, _T_5183) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5185 = or(_T_5181, _T_5184) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5186 = or(_T_5185, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5187 = bits(_T_5186, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5188 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5187 : @[Reg.scala 28:19] + _T_5188 <= _T_5178 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][5] <= _T_5188 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5189 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5190 = eq(_T_5189, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5191 = and(ic_valid_ff, _T_5190) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5192 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5193 = and(_T_5191, _T_5192) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5194 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5195 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5196 = and(_T_5194, _T_5195) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5197 = eq(perr_ic_index_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5198 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5199 = and(_T_5197, _T_5198) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5200 = or(_T_5196, _T_5199) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5201 = or(_T_5200, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5202 = bits(_T_5201, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5203 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5202 : @[Reg.scala 28:19] + _T_5203 <= _T_5193 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][6] <= _T_5203 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5204 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5205 = eq(_T_5204, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5206 = and(ic_valid_ff, _T_5205) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5207 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5208 = and(_T_5206, _T_5207) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5209 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5210 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5211 = and(_T_5209, _T_5210) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5212 = eq(perr_ic_index_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5213 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5214 = and(_T_5212, _T_5213) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5215 = or(_T_5211, _T_5214) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5216 = or(_T_5215, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5217 = bits(_T_5216, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5218 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5217 : @[Reg.scala 28:19] + _T_5218 <= _T_5208 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][7] <= _T_5218 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5219 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5220 = eq(_T_5219, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5221 = and(ic_valid_ff, _T_5220) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5222 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5223 = and(_T_5221, _T_5222) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5224 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5225 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5226 = and(_T_5224, _T_5225) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5227 = eq(perr_ic_index_ff, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5228 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5229 = and(_T_5227, _T_5228) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5230 = or(_T_5226, _T_5229) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5231 = or(_T_5230, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5232 = bits(_T_5231, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5233 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5232 : @[Reg.scala 28:19] + _T_5233 <= _T_5223 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][8] <= _T_5233 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5234 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5235 = eq(_T_5234, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5236 = and(ic_valid_ff, _T_5235) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5237 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5238 = and(_T_5236, _T_5237) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5239 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5240 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5241 = and(_T_5239, _T_5240) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5242 = eq(perr_ic_index_ff, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5243 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5244 = and(_T_5242, _T_5243) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5245 = or(_T_5241, _T_5244) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5246 = or(_T_5245, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5247 = bits(_T_5246, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5248 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5247 : @[Reg.scala 28:19] + _T_5248 <= _T_5238 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][9] <= _T_5248 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5249 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5250 = eq(_T_5249, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5251 = and(ic_valid_ff, _T_5250) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5252 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5253 = and(_T_5251, _T_5252) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5254 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5255 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5256 = and(_T_5254, _T_5255) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5257 = eq(perr_ic_index_ff, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5258 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5259 = and(_T_5257, _T_5258) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5260 = or(_T_5256, _T_5259) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5261 = or(_T_5260, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5262 = bits(_T_5261, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5263 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5262 : @[Reg.scala 28:19] + _T_5263 <= _T_5253 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][10] <= _T_5263 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5264 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5265 = eq(_T_5264, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5266 = and(ic_valid_ff, _T_5265) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5267 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5268 = and(_T_5266, _T_5267) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5269 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5270 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5271 = and(_T_5269, _T_5270) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5272 = eq(perr_ic_index_ff, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5273 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5274 = and(_T_5272, _T_5273) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5275 = or(_T_5271, _T_5274) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5276 = or(_T_5275, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5277 = bits(_T_5276, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5278 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5277 : @[Reg.scala 28:19] + _T_5278 <= _T_5268 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][11] <= _T_5278 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5279 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5280 = eq(_T_5279, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5281 = and(ic_valid_ff, _T_5280) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5282 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5283 = and(_T_5281, _T_5282) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5284 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5285 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5286 = and(_T_5284, _T_5285) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5287 = eq(perr_ic_index_ff, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5288 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5289 = and(_T_5287, _T_5288) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5290 = or(_T_5286, _T_5289) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5291 = or(_T_5290, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5292 = bits(_T_5291, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5293 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5292 : @[Reg.scala 28:19] + _T_5293 <= _T_5283 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][12] <= _T_5293 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5294 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5295 = eq(_T_5294, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5296 = and(ic_valid_ff, _T_5295) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5297 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5298 = and(_T_5296, _T_5297) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5299 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5300 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5301 = and(_T_5299, _T_5300) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5302 = eq(perr_ic_index_ff, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5303 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5304 = and(_T_5302, _T_5303) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5305 = or(_T_5301, _T_5304) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5306 = or(_T_5305, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5307 = bits(_T_5306, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5308 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5307 : @[Reg.scala 28:19] + _T_5308 <= _T_5298 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][13] <= _T_5308 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5309 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5310 = eq(_T_5309, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5311 = and(ic_valid_ff, _T_5310) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5312 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5313 = and(_T_5311, _T_5312) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5314 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5315 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5316 = and(_T_5314, _T_5315) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5317 = eq(perr_ic_index_ff, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5318 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5319 = and(_T_5317, _T_5318) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5320 = or(_T_5316, _T_5319) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5321 = or(_T_5320, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5322 = bits(_T_5321, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5323 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5322 : @[Reg.scala 28:19] + _T_5323 <= _T_5313 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][14] <= _T_5323 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5324 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5325 = eq(_T_5324, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5326 = and(ic_valid_ff, _T_5325) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5327 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5328 = and(_T_5326, _T_5327) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5329 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5330 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5331 = and(_T_5329, _T_5330) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5332 = eq(perr_ic_index_ff, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5333 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5334 = and(_T_5332, _T_5333) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5335 = or(_T_5331, _T_5334) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5336 = or(_T_5335, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5337 = bits(_T_5336, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5338 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5337 : @[Reg.scala 28:19] + _T_5338 <= _T_5328 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][15] <= _T_5338 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5339 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5340 = eq(_T_5339, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5341 = and(ic_valid_ff, _T_5340) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5342 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5343 = and(_T_5341, _T_5342) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5344 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h010")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5345 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5346 = and(_T_5344, _T_5345) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5347 = eq(perr_ic_index_ff, UInt<5>("h010")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5348 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5349 = and(_T_5347, _T_5348) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5350 = or(_T_5346, _T_5349) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5351 = or(_T_5350, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5352 = bits(_T_5351, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5353 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5352 : @[Reg.scala 28:19] + _T_5353 <= _T_5343 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][16] <= _T_5353 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5354 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5355 = eq(_T_5354, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5356 = and(ic_valid_ff, _T_5355) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5357 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5358 = and(_T_5356, _T_5357) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5359 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h011")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5360 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5361 = and(_T_5359, _T_5360) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5362 = eq(perr_ic_index_ff, UInt<5>("h011")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5363 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5364 = and(_T_5362, _T_5363) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5365 = or(_T_5361, _T_5364) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5366 = or(_T_5365, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5367 = bits(_T_5366, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5368 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5367 : @[Reg.scala 28:19] + _T_5368 <= _T_5358 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][17] <= _T_5368 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5369 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5370 = eq(_T_5369, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5371 = and(ic_valid_ff, _T_5370) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5372 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5373 = and(_T_5371, _T_5372) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5374 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h012")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5375 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5376 = and(_T_5374, _T_5375) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5377 = eq(perr_ic_index_ff, UInt<5>("h012")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5378 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5379 = and(_T_5377, _T_5378) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5380 = or(_T_5376, _T_5379) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5381 = or(_T_5380, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5382 = bits(_T_5381, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5383 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5382 : @[Reg.scala 28:19] + _T_5383 <= _T_5373 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][18] <= _T_5383 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5384 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5385 = eq(_T_5384, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5386 = and(ic_valid_ff, _T_5385) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5387 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5388 = and(_T_5386, _T_5387) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5389 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h013")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5390 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5391 = and(_T_5389, _T_5390) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5392 = eq(perr_ic_index_ff, UInt<5>("h013")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5393 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5394 = and(_T_5392, _T_5393) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5395 = or(_T_5391, _T_5394) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5396 = or(_T_5395, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5397 = bits(_T_5396, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5398 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5397 : @[Reg.scala 28:19] + _T_5398 <= _T_5388 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][19] <= _T_5398 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5399 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5400 = eq(_T_5399, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5401 = and(ic_valid_ff, _T_5400) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5402 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5403 = and(_T_5401, _T_5402) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5404 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h014")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5405 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5406 = and(_T_5404, _T_5405) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5407 = eq(perr_ic_index_ff, UInt<5>("h014")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5408 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5409 = and(_T_5407, _T_5408) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5410 = or(_T_5406, _T_5409) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5411 = or(_T_5410, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5412 = bits(_T_5411, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5413 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5412 : @[Reg.scala 28:19] + _T_5413 <= _T_5403 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][20] <= _T_5413 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5414 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5415 = eq(_T_5414, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5416 = and(ic_valid_ff, _T_5415) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5417 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5418 = and(_T_5416, _T_5417) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5419 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h015")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5420 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5421 = and(_T_5419, _T_5420) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5422 = eq(perr_ic_index_ff, UInt<5>("h015")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5423 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5424 = and(_T_5422, _T_5423) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5425 = or(_T_5421, _T_5424) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5426 = or(_T_5425, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5427 = bits(_T_5426, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5428 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5427 : @[Reg.scala 28:19] + _T_5428 <= _T_5418 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][21] <= _T_5428 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5429 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5430 = eq(_T_5429, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5431 = and(ic_valid_ff, _T_5430) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5432 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5433 = and(_T_5431, _T_5432) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5434 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h016")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5435 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5436 = and(_T_5434, _T_5435) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5437 = eq(perr_ic_index_ff, UInt<5>("h016")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5438 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5439 = and(_T_5437, _T_5438) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5440 = or(_T_5436, _T_5439) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5441 = or(_T_5440, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5442 = bits(_T_5441, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5443 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5442 : @[Reg.scala 28:19] + _T_5443 <= _T_5433 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][22] <= _T_5443 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5444 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5445 = eq(_T_5444, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5446 = and(ic_valid_ff, _T_5445) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5447 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5448 = and(_T_5446, _T_5447) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5449 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h017")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5450 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5451 = and(_T_5449, _T_5450) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5452 = eq(perr_ic_index_ff, UInt<5>("h017")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5453 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5454 = and(_T_5452, _T_5453) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5455 = or(_T_5451, _T_5454) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5456 = or(_T_5455, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5457 = bits(_T_5456, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5458 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5457 : @[Reg.scala 28:19] + _T_5458 <= _T_5448 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][23] <= _T_5458 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5459 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5460 = eq(_T_5459, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5461 = and(ic_valid_ff, _T_5460) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5462 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5463 = and(_T_5461, _T_5462) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5464 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h018")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5465 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5466 = and(_T_5464, _T_5465) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5467 = eq(perr_ic_index_ff, UInt<5>("h018")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5468 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5469 = and(_T_5467, _T_5468) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5470 = or(_T_5466, _T_5469) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5471 = or(_T_5470, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5472 = bits(_T_5471, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5473 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5472 : @[Reg.scala 28:19] + _T_5473 <= _T_5463 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][24] <= _T_5473 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5474 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5475 = eq(_T_5474, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5476 = and(ic_valid_ff, _T_5475) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5477 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5478 = and(_T_5476, _T_5477) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5479 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h019")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5480 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5481 = and(_T_5479, _T_5480) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5482 = eq(perr_ic_index_ff, UInt<5>("h019")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5483 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5484 = and(_T_5482, _T_5483) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5485 = or(_T_5481, _T_5484) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5486 = or(_T_5485, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5487 = bits(_T_5486, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5488 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5487 : @[Reg.scala 28:19] + _T_5488 <= _T_5478 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][25] <= _T_5488 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5489 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5490 = eq(_T_5489, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5491 = and(ic_valid_ff, _T_5490) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5492 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5493 = and(_T_5491, _T_5492) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5494 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01a")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5495 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5496 = and(_T_5494, _T_5495) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5497 = eq(perr_ic_index_ff, UInt<5>("h01a")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5498 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5499 = and(_T_5497, _T_5498) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5500 = or(_T_5496, _T_5499) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5501 = or(_T_5500, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5502 = bits(_T_5501, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5503 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5502 : @[Reg.scala 28:19] + _T_5503 <= _T_5493 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][26] <= _T_5503 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5504 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5505 = eq(_T_5504, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5506 = and(ic_valid_ff, _T_5505) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5507 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5508 = and(_T_5506, _T_5507) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5509 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01b")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5510 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5511 = and(_T_5509, _T_5510) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5512 = eq(perr_ic_index_ff, UInt<5>("h01b")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5513 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5514 = and(_T_5512, _T_5513) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5515 = or(_T_5511, _T_5514) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5516 = or(_T_5515, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5517 = bits(_T_5516, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5518 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5517 : @[Reg.scala 28:19] + _T_5518 <= _T_5508 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][27] <= _T_5518 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5519 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5520 = eq(_T_5519, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5521 = and(ic_valid_ff, _T_5520) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5522 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5523 = and(_T_5521, _T_5522) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5524 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01c")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5525 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5526 = and(_T_5524, _T_5525) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5527 = eq(perr_ic_index_ff, UInt<5>("h01c")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5528 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5529 = and(_T_5527, _T_5528) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5530 = or(_T_5526, _T_5529) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5531 = or(_T_5530, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5532 = bits(_T_5531, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5533 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5532 : @[Reg.scala 28:19] + _T_5533 <= _T_5523 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][28] <= _T_5533 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5534 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5535 = eq(_T_5534, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5536 = and(ic_valid_ff, _T_5535) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5537 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5538 = and(_T_5536, _T_5537) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5539 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01d")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5540 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5541 = and(_T_5539, _T_5540) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5542 = eq(perr_ic_index_ff, UInt<5>("h01d")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5543 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5544 = and(_T_5542, _T_5543) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5545 = or(_T_5541, _T_5544) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5546 = or(_T_5545, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5547 = bits(_T_5546, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5548 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5547 : @[Reg.scala 28:19] + _T_5548 <= _T_5538 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][29] <= _T_5548 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5549 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5550 = eq(_T_5549, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5551 = and(ic_valid_ff, _T_5550) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5552 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5553 = and(_T_5551, _T_5552) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5554 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01e")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5555 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5556 = and(_T_5554, _T_5555) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5557 = eq(perr_ic_index_ff, UInt<5>("h01e")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5558 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5559 = and(_T_5557, _T_5558) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5560 = or(_T_5556, _T_5559) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5561 = or(_T_5560, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5562 = bits(_T_5561, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5563 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5562 : @[Reg.scala 28:19] + _T_5563 <= _T_5553 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][30] <= _T_5563 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5564 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5565 = eq(_T_5564, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5566 = and(ic_valid_ff, _T_5565) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5567 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5568 = and(_T_5566, _T_5567) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5569 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01f")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5570 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5571 = and(_T_5569, _T_5570) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5572 = eq(perr_ic_index_ff, UInt<5>("h01f")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5573 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5574 = and(_T_5572, _T_5573) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5575 = or(_T_5571, _T_5574) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5576 = or(_T_5575, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5577 = bits(_T_5576, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5578 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5577 : @[Reg.scala 28:19] + _T_5578 <= _T_5568 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][31] <= _T_5578 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5579 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5580 = eq(_T_5579, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5581 = and(ic_valid_ff, _T_5580) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5582 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5583 = and(_T_5581, _T_5582) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5584 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5585 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5586 = and(_T_5584, _T_5585) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5587 = eq(perr_ic_index_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5588 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5589 = and(_T_5587, _T_5588) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5590 = or(_T_5586, _T_5589) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5591 = or(_T_5590, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5592 = bits(_T_5591, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5593 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5592 : @[Reg.scala 28:19] + _T_5593 <= _T_5583 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][0] <= _T_5593 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5594 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5595 = eq(_T_5594, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5596 = and(ic_valid_ff, _T_5595) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5597 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5598 = and(_T_5596, _T_5597) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5599 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5600 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5601 = and(_T_5599, _T_5600) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5602 = eq(perr_ic_index_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5603 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5604 = and(_T_5602, _T_5603) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5605 = or(_T_5601, _T_5604) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5606 = or(_T_5605, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5607 = bits(_T_5606, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5608 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5607 : @[Reg.scala 28:19] + _T_5608 <= _T_5598 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][1] <= _T_5608 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5609 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5610 = eq(_T_5609, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5611 = and(ic_valid_ff, _T_5610) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5612 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5613 = and(_T_5611, _T_5612) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5614 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5615 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5616 = and(_T_5614, _T_5615) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5617 = eq(perr_ic_index_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5618 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5619 = and(_T_5617, _T_5618) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5620 = or(_T_5616, _T_5619) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5621 = or(_T_5620, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5622 = bits(_T_5621, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5623 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5622 : @[Reg.scala 28:19] + _T_5623 <= _T_5613 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][2] <= _T_5623 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5624 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5625 = eq(_T_5624, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5626 = and(ic_valid_ff, _T_5625) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5627 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5628 = and(_T_5626, _T_5627) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5629 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5630 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5631 = and(_T_5629, _T_5630) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5632 = eq(perr_ic_index_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5633 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5634 = and(_T_5632, _T_5633) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5635 = or(_T_5631, _T_5634) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5636 = or(_T_5635, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5637 = bits(_T_5636, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5638 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5637 : @[Reg.scala 28:19] + _T_5638 <= _T_5628 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][3] <= _T_5638 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5639 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5640 = eq(_T_5639, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5641 = and(ic_valid_ff, _T_5640) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5642 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5643 = and(_T_5641, _T_5642) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5644 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5645 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5646 = and(_T_5644, _T_5645) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5647 = eq(perr_ic_index_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5648 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5649 = and(_T_5647, _T_5648) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5650 = or(_T_5646, _T_5649) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5651 = or(_T_5650, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5652 = bits(_T_5651, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5653 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5652 : @[Reg.scala 28:19] + _T_5653 <= _T_5643 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][4] <= _T_5653 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5654 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5655 = eq(_T_5654, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5656 = and(ic_valid_ff, _T_5655) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5657 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5658 = and(_T_5656, _T_5657) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5659 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5660 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5661 = and(_T_5659, _T_5660) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5662 = eq(perr_ic_index_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5663 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5664 = and(_T_5662, _T_5663) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5665 = or(_T_5661, _T_5664) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5666 = or(_T_5665, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5667 = bits(_T_5666, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5668 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5667 : @[Reg.scala 28:19] + _T_5668 <= _T_5658 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][5] <= _T_5668 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5669 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5670 = eq(_T_5669, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5671 = and(ic_valid_ff, _T_5670) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5672 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5673 = and(_T_5671, _T_5672) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5674 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5675 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5676 = and(_T_5674, _T_5675) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5677 = eq(perr_ic_index_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5678 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5679 = and(_T_5677, _T_5678) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5680 = or(_T_5676, _T_5679) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5681 = or(_T_5680, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5682 = bits(_T_5681, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5683 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5682 : @[Reg.scala 28:19] + _T_5683 <= _T_5673 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][6] <= _T_5683 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5684 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5685 = eq(_T_5684, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5686 = and(ic_valid_ff, _T_5685) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5687 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5688 = and(_T_5686, _T_5687) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5689 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5690 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5691 = and(_T_5689, _T_5690) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5692 = eq(perr_ic_index_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5693 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5694 = and(_T_5692, _T_5693) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5695 = or(_T_5691, _T_5694) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5696 = or(_T_5695, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5697 = bits(_T_5696, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5698 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5697 : @[Reg.scala 28:19] + _T_5698 <= _T_5688 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][7] <= _T_5698 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5699 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5700 = eq(_T_5699, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5701 = and(ic_valid_ff, _T_5700) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5702 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5703 = and(_T_5701, _T_5702) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5704 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5705 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5706 = and(_T_5704, _T_5705) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5707 = eq(perr_ic_index_ff, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5708 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5709 = and(_T_5707, _T_5708) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5710 = or(_T_5706, _T_5709) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5711 = or(_T_5710, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5712 = bits(_T_5711, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5713 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5712 : @[Reg.scala 28:19] + _T_5713 <= _T_5703 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][8] <= _T_5713 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5714 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5715 = eq(_T_5714, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5716 = and(ic_valid_ff, _T_5715) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5717 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5718 = and(_T_5716, _T_5717) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5719 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5720 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5721 = and(_T_5719, _T_5720) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5722 = eq(perr_ic_index_ff, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5723 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5724 = and(_T_5722, _T_5723) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5725 = or(_T_5721, _T_5724) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5726 = or(_T_5725, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5727 = bits(_T_5726, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5728 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5727 : @[Reg.scala 28:19] + _T_5728 <= _T_5718 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][9] <= _T_5728 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5729 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5730 = eq(_T_5729, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5731 = and(ic_valid_ff, _T_5730) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5732 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5733 = and(_T_5731, _T_5732) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5734 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5735 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5736 = and(_T_5734, _T_5735) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5737 = eq(perr_ic_index_ff, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5738 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5739 = and(_T_5737, _T_5738) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5740 = or(_T_5736, _T_5739) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5741 = or(_T_5740, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5742 = bits(_T_5741, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5743 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5742 : @[Reg.scala 28:19] + _T_5743 <= _T_5733 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][10] <= _T_5743 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5744 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5745 = eq(_T_5744, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5746 = and(ic_valid_ff, _T_5745) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5747 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5748 = and(_T_5746, _T_5747) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5749 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5750 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5751 = and(_T_5749, _T_5750) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5752 = eq(perr_ic_index_ff, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5753 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5754 = and(_T_5752, _T_5753) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5755 = or(_T_5751, _T_5754) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5756 = or(_T_5755, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5757 = bits(_T_5756, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5758 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5757 : @[Reg.scala 28:19] + _T_5758 <= _T_5748 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][11] <= _T_5758 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5759 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5760 = eq(_T_5759, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5761 = and(ic_valid_ff, _T_5760) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5762 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5763 = and(_T_5761, _T_5762) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5764 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5765 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5766 = and(_T_5764, _T_5765) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5767 = eq(perr_ic_index_ff, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5768 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5769 = and(_T_5767, _T_5768) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5770 = or(_T_5766, _T_5769) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5771 = or(_T_5770, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5772 = bits(_T_5771, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5773 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5772 : @[Reg.scala 28:19] + _T_5773 <= _T_5763 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][12] <= _T_5773 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5774 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5775 = eq(_T_5774, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5776 = and(ic_valid_ff, _T_5775) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5777 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5778 = and(_T_5776, _T_5777) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5779 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5780 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5781 = and(_T_5779, _T_5780) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5782 = eq(perr_ic_index_ff, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5783 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5784 = and(_T_5782, _T_5783) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5785 = or(_T_5781, _T_5784) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5786 = or(_T_5785, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5787 = bits(_T_5786, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5788 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5787 : @[Reg.scala 28:19] + _T_5788 <= _T_5778 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][13] <= _T_5788 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5789 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5790 = eq(_T_5789, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5791 = and(ic_valid_ff, _T_5790) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5792 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5793 = and(_T_5791, _T_5792) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5794 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5795 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5796 = and(_T_5794, _T_5795) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5797 = eq(perr_ic_index_ff, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5798 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5799 = and(_T_5797, _T_5798) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5800 = or(_T_5796, _T_5799) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5801 = or(_T_5800, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5802 = bits(_T_5801, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5803 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5802 : @[Reg.scala 28:19] + _T_5803 <= _T_5793 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][14] <= _T_5803 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5804 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5805 = eq(_T_5804, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5806 = and(ic_valid_ff, _T_5805) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5807 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5808 = and(_T_5806, _T_5807) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5809 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5810 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5811 = and(_T_5809, _T_5810) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5812 = eq(perr_ic_index_ff, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5813 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5814 = and(_T_5812, _T_5813) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5815 = or(_T_5811, _T_5814) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5816 = or(_T_5815, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5817 = bits(_T_5816, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5818 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5817 : @[Reg.scala 28:19] + _T_5818 <= _T_5808 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][15] <= _T_5818 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5819 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5820 = eq(_T_5819, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5821 = and(ic_valid_ff, _T_5820) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5822 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5823 = and(_T_5821, _T_5822) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5824 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h010")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5825 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5826 = and(_T_5824, _T_5825) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5827 = eq(perr_ic_index_ff, UInt<5>("h010")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5828 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5829 = and(_T_5827, _T_5828) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5830 = or(_T_5826, _T_5829) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5831 = or(_T_5830, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5832 = bits(_T_5831, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5833 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5832 : @[Reg.scala 28:19] + _T_5833 <= _T_5823 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][16] <= _T_5833 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5834 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5835 = eq(_T_5834, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5836 = and(ic_valid_ff, _T_5835) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5837 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5838 = and(_T_5836, _T_5837) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5839 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h011")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5840 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5841 = and(_T_5839, _T_5840) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5842 = eq(perr_ic_index_ff, UInt<5>("h011")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5843 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5844 = and(_T_5842, _T_5843) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5845 = or(_T_5841, _T_5844) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5846 = or(_T_5845, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5847 = bits(_T_5846, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5848 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5847 : @[Reg.scala 28:19] + _T_5848 <= _T_5838 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][17] <= _T_5848 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5849 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5850 = eq(_T_5849, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5851 = and(ic_valid_ff, _T_5850) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5852 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5853 = and(_T_5851, _T_5852) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5854 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h012")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5855 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5856 = and(_T_5854, _T_5855) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5857 = eq(perr_ic_index_ff, UInt<5>("h012")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5858 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5859 = and(_T_5857, _T_5858) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5860 = or(_T_5856, _T_5859) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5861 = or(_T_5860, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5862 = bits(_T_5861, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5863 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5862 : @[Reg.scala 28:19] + _T_5863 <= _T_5853 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][18] <= _T_5863 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5864 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5865 = eq(_T_5864, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5866 = and(ic_valid_ff, _T_5865) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5867 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5868 = and(_T_5866, _T_5867) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5869 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h013")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5870 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5871 = and(_T_5869, _T_5870) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5872 = eq(perr_ic_index_ff, UInt<5>("h013")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5873 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5874 = and(_T_5872, _T_5873) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5875 = or(_T_5871, _T_5874) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5876 = or(_T_5875, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5877 = bits(_T_5876, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5878 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5877 : @[Reg.scala 28:19] + _T_5878 <= _T_5868 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][19] <= _T_5878 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5879 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5880 = eq(_T_5879, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5881 = and(ic_valid_ff, _T_5880) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5882 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5883 = and(_T_5881, _T_5882) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5884 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h014")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5885 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5886 = and(_T_5884, _T_5885) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5887 = eq(perr_ic_index_ff, UInt<5>("h014")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5888 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5889 = and(_T_5887, _T_5888) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5890 = or(_T_5886, _T_5889) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5891 = or(_T_5890, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5892 = bits(_T_5891, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5893 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5892 : @[Reg.scala 28:19] + _T_5893 <= _T_5883 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][20] <= _T_5893 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5894 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5895 = eq(_T_5894, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5896 = and(ic_valid_ff, _T_5895) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5897 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5898 = and(_T_5896, _T_5897) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5899 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h015")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5900 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5901 = and(_T_5899, _T_5900) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5902 = eq(perr_ic_index_ff, UInt<5>("h015")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5903 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5904 = and(_T_5902, _T_5903) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5905 = or(_T_5901, _T_5904) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5906 = or(_T_5905, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5907 = bits(_T_5906, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5908 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5907 : @[Reg.scala 28:19] + _T_5908 <= _T_5898 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][21] <= _T_5908 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5909 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5910 = eq(_T_5909, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5911 = and(ic_valid_ff, _T_5910) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5912 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5913 = and(_T_5911, _T_5912) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5914 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h016")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5915 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5916 = and(_T_5914, _T_5915) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5917 = eq(perr_ic_index_ff, UInt<5>("h016")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5918 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5919 = and(_T_5917, _T_5918) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5920 = or(_T_5916, _T_5919) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5921 = or(_T_5920, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5922 = bits(_T_5921, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5923 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5922 : @[Reg.scala 28:19] + _T_5923 <= _T_5913 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][22] <= _T_5923 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5924 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5925 = eq(_T_5924, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5926 = and(ic_valid_ff, _T_5925) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5927 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5928 = and(_T_5926, _T_5927) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5929 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h017")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5930 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5931 = and(_T_5929, _T_5930) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5932 = eq(perr_ic_index_ff, UInt<5>("h017")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5933 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5934 = and(_T_5932, _T_5933) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5935 = or(_T_5931, _T_5934) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5936 = or(_T_5935, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5937 = bits(_T_5936, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5938 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5937 : @[Reg.scala 28:19] + _T_5938 <= _T_5928 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][23] <= _T_5938 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5939 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5940 = eq(_T_5939, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5941 = and(ic_valid_ff, _T_5940) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5942 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5943 = and(_T_5941, _T_5942) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5944 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h018")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5945 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5946 = and(_T_5944, _T_5945) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5947 = eq(perr_ic_index_ff, UInt<5>("h018")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5948 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5949 = and(_T_5947, _T_5948) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5950 = or(_T_5946, _T_5949) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5951 = or(_T_5950, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5952 = bits(_T_5951, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5953 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5952 : @[Reg.scala 28:19] + _T_5953 <= _T_5943 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][24] <= _T_5953 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5954 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5955 = eq(_T_5954, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5956 = and(ic_valid_ff, _T_5955) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5957 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5958 = and(_T_5956, _T_5957) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5959 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h019")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5960 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5961 = and(_T_5959, _T_5960) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5962 = eq(perr_ic_index_ff, UInt<5>("h019")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5963 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5964 = and(_T_5962, _T_5963) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5965 = or(_T_5961, _T_5964) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5966 = or(_T_5965, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5967 = bits(_T_5966, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5968 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5967 : @[Reg.scala 28:19] + _T_5968 <= _T_5958 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][25] <= _T_5968 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5969 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5970 = eq(_T_5969, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5971 = and(ic_valid_ff, _T_5970) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5972 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5973 = and(_T_5971, _T_5972) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5974 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01a")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5975 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5976 = and(_T_5974, _T_5975) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5977 = eq(perr_ic_index_ff, UInt<5>("h01a")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5978 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5979 = and(_T_5977, _T_5978) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5980 = or(_T_5976, _T_5979) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5981 = or(_T_5980, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5982 = bits(_T_5981, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5983 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5982 : @[Reg.scala 28:19] + _T_5983 <= _T_5973 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][26] <= _T_5983 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5984 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_5985 = eq(_T_5984, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_5986 = and(ic_valid_ff, _T_5985) @[el2_ifu_mem_ctl.scala 760:95] + node _T_5987 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_5988 = and(_T_5986, _T_5987) @[el2_ifu_mem_ctl.scala 760:120] + node _T_5989 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01b")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_5990 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_5991 = and(_T_5989, _T_5990) @[el2_ifu_mem_ctl.scala 761:55] + node _T_5992 = eq(perr_ic_index_ff, UInt<5>("h01b")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_5993 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_5994 = and(_T_5992, _T_5993) @[el2_ifu_mem_ctl.scala 761:120] + node _T_5995 = or(_T_5991, _T_5994) @[el2_ifu_mem_ctl.scala 761:77] + node _T_5996 = or(_T_5995, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_5997 = bits(_T_5996, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_5998 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5997 : @[Reg.scala 28:19] + _T_5998 <= _T_5988 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][27] <= _T_5998 @[el2_ifu_mem_ctl.scala 760:39] + node _T_5999 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6000 = eq(_T_5999, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6001 = and(ic_valid_ff, _T_6000) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6002 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6003 = and(_T_6001, _T_6002) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6004 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01c")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6005 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6006 = and(_T_6004, _T_6005) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6007 = eq(perr_ic_index_ff, UInt<5>("h01c")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6008 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6009 = and(_T_6007, _T_6008) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6010 = or(_T_6006, _T_6009) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6011 = or(_T_6010, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6012 = bits(_T_6011, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6013 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6012 : @[Reg.scala 28:19] + _T_6013 <= _T_6003 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][28] <= _T_6013 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6014 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6015 = eq(_T_6014, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6016 = and(ic_valid_ff, _T_6015) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6017 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6018 = and(_T_6016, _T_6017) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6019 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01d")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6020 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6021 = and(_T_6019, _T_6020) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6022 = eq(perr_ic_index_ff, UInt<5>("h01d")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6023 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6024 = and(_T_6022, _T_6023) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6025 = or(_T_6021, _T_6024) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6026 = or(_T_6025, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6027 = bits(_T_6026, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6028 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6027 : @[Reg.scala 28:19] + _T_6028 <= _T_6018 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][29] <= _T_6028 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6029 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6030 = eq(_T_6029, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6031 = and(ic_valid_ff, _T_6030) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6032 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6033 = and(_T_6031, _T_6032) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6034 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01e")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6035 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6036 = and(_T_6034, _T_6035) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6037 = eq(perr_ic_index_ff, UInt<5>("h01e")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6038 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6039 = and(_T_6037, _T_6038) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6040 = or(_T_6036, _T_6039) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6041 = or(_T_6040, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6042 = bits(_T_6041, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6043 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6042 : @[Reg.scala 28:19] + _T_6043 <= _T_6033 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][30] <= _T_6043 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6044 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6045 = eq(_T_6044, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6046 = and(ic_valid_ff, _T_6045) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6047 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6048 = and(_T_6046, _T_6047) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6049 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01f")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6050 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6051 = and(_T_6049, _T_6050) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6052 = eq(perr_ic_index_ff, UInt<5>("h01f")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6053 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6054 = and(_T_6052, _T_6053) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6055 = or(_T_6051, _T_6054) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6056 = or(_T_6055, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6057 = bits(_T_6056, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6058 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6057 : @[Reg.scala 28:19] + _T_6058 <= _T_6048 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][31] <= _T_6058 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6059 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6060 = eq(_T_6059, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6061 = and(ic_valid_ff, _T_6060) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6062 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6063 = and(_T_6061, _T_6062) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6064 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h020")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6065 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6066 = and(_T_6064, _T_6065) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6067 = eq(perr_ic_index_ff, UInt<6>("h020")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6068 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6069 = and(_T_6067, _T_6068) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6070 = or(_T_6066, _T_6069) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6071 = or(_T_6070, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6072 = bits(_T_6071, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6073 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6072 : @[Reg.scala 28:19] + _T_6073 <= _T_6063 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][32] <= _T_6073 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6074 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6075 = eq(_T_6074, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6076 = and(ic_valid_ff, _T_6075) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6077 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6078 = and(_T_6076, _T_6077) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6079 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h021")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6080 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6081 = and(_T_6079, _T_6080) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6082 = eq(perr_ic_index_ff, UInt<6>("h021")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6083 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6084 = and(_T_6082, _T_6083) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6085 = or(_T_6081, _T_6084) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6086 = or(_T_6085, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6087 = bits(_T_6086, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6088 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6087 : @[Reg.scala 28:19] + _T_6088 <= _T_6078 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][33] <= _T_6088 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6089 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6090 = eq(_T_6089, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6091 = and(ic_valid_ff, _T_6090) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6092 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6093 = and(_T_6091, _T_6092) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6094 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h022")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6095 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6096 = and(_T_6094, _T_6095) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6097 = eq(perr_ic_index_ff, UInt<6>("h022")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6098 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6099 = and(_T_6097, _T_6098) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6100 = or(_T_6096, _T_6099) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6101 = or(_T_6100, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6102 = bits(_T_6101, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6103 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6102 : @[Reg.scala 28:19] + _T_6103 <= _T_6093 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][34] <= _T_6103 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6104 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6105 = eq(_T_6104, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6106 = and(ic_valid_ff, _T_6105) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6107 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6108 = and(_T_6106, _T_6107) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6109 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h023")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6110 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6111 = and(_T_6109, _T_6110) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6112 = eq(perr_ic_index_ff, UInt<6>("h023")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6113 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6114 = and(_T_6112, _T_6113) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6115 = or(_T_6111, _T_6114) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6116 = or(_T_6115, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6117 = bits(_T_6116, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6118 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6117 : @[Reg.scala 28:19] + _T_6118 <= _T_6108 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][35] <= _T_6118 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6119 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6120 = eq(_T_6119, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6121 = and(ic_valid_ff, _T_6120) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6122 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6123 = and(_T_6121, _T_6122) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6124 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h024")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6125 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6126 = and(_T_6124, _T_6125) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6127 = eq(perr_ic_index_ff, UInt<6>("h024")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6128 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6129 = and(_T_6127, _T_6128) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6130 = or(_T_6126, _T_6129) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6131 = or(_T_6130, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6132 = bits(_T_6131, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6133 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6132 : @[Reg.scala 28:19] + _T_6133 <= _T_6123 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][36] <= _T_6133 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6134 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6135 = eq(_T_6134, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6136 = and(ic_valid_ff, _T_6135) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6137 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6138 = and(_T_6136, _T_6137) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6139 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h025")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6140 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6141 = and(_T_6139, _T_6140) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6142 = eq(perr_ic_index_ff, UInt<6>("h025")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6143 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6144 = and(_T_6142, _T_6143) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6145 = or(_T_6141, _T_6144) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6146 = or(_T_6145, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6147 = bits(_T_6146, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6148 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6147 : @[Reg.scala 28:19] + _T_6148 <= _T_6138 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][37] <= _T_6148 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6149 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6150 = eq(_T_6149, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6151 = and(ic_valid_ff, _T_6150) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6152 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6153 = and(_T_6151, _T_6152) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6154 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h026")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6155 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6156 = and(_T_6154, _T_6155) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6157 = eq(perr_ic_index_ff, UInt<6>("h026")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6158 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6159 = and(_T_6157, _T_6158) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6160 = or(_T_6156, _T_6159) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6161 = or(_T_6160, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6162 = bits(_T_6161, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6163 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6162 : @[Reg.scala 28:19] + _T_6163 <= _T_6153 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][38] <= _T_6163 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6164 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6165 = eq(_T_6164, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6166 = and(ic_valid_ff, _T_6165) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6167 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6168 = and(_T_6166, _T_6167) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6169 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h027")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6170 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6171 = and(_T_6169, _T_6170) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6172 = eq(perr_ic_index_ff, UInt<6>("h027")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6173 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6174 = and(_T_6172, _T_6173) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6175 = or(_T_6171, _T_6174) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6176 = or(_T_6175, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6177 = bits(_T_6176, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6178 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6177 : @[Reg.scala 28:19] + _T_6178 <= _T_6168 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][39] <= _T_6178 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6179 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6180 = eq(_T_6179, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6181 = and(ic_valid_ff, _T_6180) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6182 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6183 = and(_T_6181, _T_6182) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6184 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h028")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6185 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6186 = and(_T_6184, _T_6185) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6187 = eq(perr_ic_index_ff, UInt<6>("h028")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6188 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6189 = and(_T_6187, _T_6188) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6190 = or(_T_6186, _T_6189) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6191 = or(_T_6190, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6192 = bits(_T_6191, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6193 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6192 : @[Reg.scala 28:19] + _T_6193 <= _T_6183 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][40] <= _T_6193 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6194 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6195 = eq(_T_6194, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6196 = and(ic_valid_ff, _T_6195) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6197 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6198 = and(_T_6196, _T_6197) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6199 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h029")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6200 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6201 = and(_T_6199, _T_6200) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6202 = eq(perr_ic_index_ff, UInt<6>("h029")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6203 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6204 = and(_T_6202, _T_6203) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6205 = or(_T_6201, _T_6204) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6206 = or(_T_6205, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6207 = bits(_T_6206, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6208 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6207 : @[Reg.scala 28:19] + _T_6208 <= _T_6198 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][41] <= _T_6208 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6209 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6210 = eq(_T_6209, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6211 = and(ic_valid_ff, _T_6210) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6212 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6213 = and(_T_6211, _T_6212) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6214 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02a")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6215 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6216 = and(_T_6214, _T_6215) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6217 = eq(perr_ic_index_ff, UInt<6>("h02a")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6218 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6219 = and(_T_6217, _T_6218) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6220 = or(_T_6216, _T_6219) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6221 = or(_T_6220, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6222 = bits(_T_6221, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6223 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6222 : @[Reg.scala 28:19] + _T_6223 <= _T_6213 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][42] <= _T_6223 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6224 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6225 = eq(_T_6224, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6226 = and(ic_valid_ff, _T_6225) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6227 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6228 = and(_T_6226, _T_6227) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6229 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02b")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6230 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6231 = and(_T_6229, _T_6230) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6232 = eq(perr_ic_index_ff, UInt<6>("h02b")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6233 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6234 = and(_T_6232, _T_6233) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6235 = or(_T_6231, _T_6234) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6236 = or(_T_6235, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6237 = bits(_T_6236, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6238 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6237 : @[Reg.scala 28:19] + _T_6238 <= _T_6228 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][43] <= _T_6238 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6239 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6240 = eq(_T_6239, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6241 = and(ic_valid_ff, _T_6240) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6242 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6243 = and(_T_6241, _T_6242) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6244 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02c")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6245 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6246 = and(_T_6244, _T_6245) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6247 = eq(perr_ic_index_ff, UInt<6>("h02c")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6248 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6249 = and(_T_6247, _T_6248) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6250 = or(_T_6246, _T_6249) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6251 = or(_T_6250, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6252 = bits(_T_6251, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6253 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6252 : @[Reg.scala 28:19] + _T_6253 <= _T_6243 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][44] <= _T_6253 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6254 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6255 = eq(_T_6254, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6256 = and(ic_valid_ff, _T_6255) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6257 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6258 = and(_T_6256, _T_6257) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6259 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02d")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6260 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6261 = and(_T_6259, _T_6260) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6262 = eq(perr_ic_index_ff, UInt<6>("h02d")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6263 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6264 = and(_T_6262, _T_6263) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6265 = or(_T_6261, _T_6264) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6266 = or(_T_6265, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6267 = bits(_T_6266, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6268 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6267 : @[Reg.scala 28:19] + _T_6268 <= _T_6258 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][45] <= _T_6268 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6269 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6270 = eq(_T_6269, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6271 = and(ic_valid_ff, _T_6270) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6272 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6273 = and(_T_6271, _T_6272) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6274 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02e")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6275 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6276 = and(_T_6274, _T_6275) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6277 = eq(perr_ic_index_ff, UInt<6>("h02e")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6278 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6279 = and(_T_6277, _T_6278) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6280 = or(_T_6276, _T_6279) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6281 = or(_T_6280, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6282 = bits(_T_6281, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6283 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6282 : @[Reg.scala 28:19] + _T_6283 <= _T_6273 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][46] <= _T_6283 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6284 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6285 = eq(_T_6284, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6286 = and(ic_valid_ff, _T_6285) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6287 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6288 = and(_T_6286, _T_6287) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6289 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02f")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6290 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6291 = and(_T_6289, _T_6290) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6292 = eq(perr_ic_index_ff, UInt<6>("h02f")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6293 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6294 = and(_T_6292, _T_6293) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6295 = or(_T_6291, _T_6294) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6296 = or(_T_6295, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6297 = bits(_T_6296, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6298 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6297 : @[Reg.scala 28:19] + _T_6298 <= _T_6288 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][47] <= _T_6298 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6299 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6300 = eq(_T_6299, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6301 = and(ic_valid_ff, _T_6300) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6302 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6303 = and(_T_6301, _T_6302) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6304 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h030")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6305 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6306 = and(_T_6304, _T_6305) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6307 = eq(perr_ic_index_ff, UInt<6>("h030")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6308 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6309 = and(_T_6307, _T_6308) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6310 = or(_T_6306, _T_6309) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6311 = or(_T_6310, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6312 = bits(_T_6311, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6313 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6312 : @[Reg.scala 28:19] + _T_6313 <= _T_6303 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][48] <= _T_6313 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6314 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6315 = eq(_T_6314, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6316 = and(ic_valid_ff, _T_6315) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6317 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6318 = and(_T_6316, _T_6317) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6319 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h031")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6320 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6321 = and(_T_6319, _T_6320) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6322 = eq(perr_ic_index_ff, UInt<6>("h031")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6323 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6324 = and(_T_6322, _T_6323) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6325 = or(_T_6321, _T_6324) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6326 = or(_T_6325, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6327 = bits(_T_6326, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6328 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6327 : @[Reg.scala 28:19] + _T_6328 <= _T_6318 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][49] <= _T_6328 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6329 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6330 = eq(_T_6329, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6331 = and(ic_valid_ff, _T_6330) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6332 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6333 = and(_T_6331, _T_6332) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6334 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h032")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6335 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6336 = and(_T_6334, _T_6335) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6337 = eq(perr_ic_index_ff, UInt<6>("h032")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6338 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6339 = and(_T_6337, _T_6338) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6340 = or(_T_6336, _T_6339) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6341 = or(_T_6340, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6342 = bits(_T_6341, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6343 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6342 : @[Reg.scala 28:19] + _T_6343 <= _T_6333 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][50] <= _T_6343 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6344 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6345 = eq(_T_6344, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6346 = and(ic_valid_ff, _T_6345) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6347 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6348 = and(_T_6346, _T_6347) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6349 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h033")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6350 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6351 = and(_T_6349, _T_6350) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6352 = eq(perr_ic_index_ff, UInt<6>("h033")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6353 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6354 = and(_T_6352, _T_6353) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6355 = or(_T_6351, _T_6354) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6356 = or(_T_6355, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6357 = bits(_T_6356, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6358 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6357 : @[Reg.scala 28:19] + _T_6358 <= _T_6348 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][51] <= _T_6358 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6359 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6360 = eq(_T_6359, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6361 = and(ic_valid_ff, _T_6360) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6362 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6363 = and(_T_6361, _T_6362) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6364 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h034")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6365 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6366 = and(_T_6364, _T_6365) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6367 = eq(perr_ic_index_ff, UInt<6>("h034")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6368 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6369 = and(_T_6367, _T_6368) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6370 = or(_T_6366, _T_6369) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6371 = or(_T_6370, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6372 = bits(_T_6371, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6373 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6372 : @[Reg.scala 28:19] + _T_6373 <= _T_6363 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][52] <= _T_6373 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6374 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6375 = eq(_T_6374, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6376 = and(ic_valid_ff, _T_6375) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6377 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6378 = and(_T_6376, _T_6377) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6379 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h035")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6380 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6381 = and(_T_6379, _T_6380) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6382 = eq(perr_ic_index_ff, UInt<6>("h035")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6383 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6384 = and(_T_6382, _T_6383) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6385 = or(_T_6381, _T_6384) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6386 = or(_T_6385, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6387 = bits(_T_6386, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6388 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6387 : @[Reg.scala 28:19] + _T_6388 <= _T_6378 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][53] <= _T_6388 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6389 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6390 = eq(_T_6389, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6391 = and(ic_valid_ff, _T_6390) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6392 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6393 = and(_T_6391, _T_6392) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6394 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h036")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6395 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6396 = and(_T_6394, _T_6395) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6397 = eq(perr_ic_index_ff, UInt<6>("h036")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6398 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6399 = and(_T_6397, _T_6398) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6400 = or(_T_6396, _T_6399) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6401 = or(_T_6400, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6402 = bits(_T_6401, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6403 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6402 : @[Reg.scala 28:19] + _T_6403 <= _T_6393 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][54] <= _T_6403 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6404 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6405 = eq(_T_6404, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6406 = and(ic_valid_ff, _T_6405) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6407 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6408 = and(_T_6406, _T_6407) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6409 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h037")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6410 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6411 = and(_T_6409, _T_6410) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6412 = eq(perr_ic_index_ff, UInt<6>("h037")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6413 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6414 = and(_T_6412, _T_6413) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6415 = or(_T_6411, _T_6414) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6416 = or(_T_6415, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6417 = bits(_T_6416, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6418 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6417 : @[Reg.scala 28:19] + _T_6418 <= _T_6408 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][55] <= _T_6418 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6419 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6420 = eq(_T_6419, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6421 = and(ic_valid_ff, _T_6420) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6422 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6423 = and(_T_6421, _T_6422) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6424 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h038")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6425 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6426 = and(_T_6424, _T_6425) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6427 = eq(perr_ic_index_ff, UInt<6>("h038")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6428 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6429 = and(_T_6427, _T_6428) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6430 = or(_T_6426, _T_6429) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6431 = or(_T_6430, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6432 = bits(_T_6431, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6433 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6432 : @[Reg.scala 28:19] + _T_6433 <= _T_6423 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][56] <= _T_6433 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6434 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6435 = eq(_T_6434, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6436 = and(ic_valid_ff, _T_6435) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6437 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6438 = and(_T_6436, _T_6437) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6439 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h039")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6440 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6441 = and(_T_6439, _T_6440) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6442 = eq(perr_ic_index_ff, UInt<6>("h039")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6443 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6444 = and(_T_6442, _T_6443) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6445 = or(_T_6441, _T_6444) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6446 = or(_T_6445, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6447 = bits(_T_6446, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6448 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6447 : @[Reg.scala 28:19] + _T_6448 <= _T_6438 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][57] <= _T_6448 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6449 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6450 = eq(_T_6449, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6451 = and(ic_valid_ff, _T_6450) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6452 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6453 = and(_T_6451, _T_6452) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6454 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03a")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6455 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6456 = and(_T_6454, _T_6455) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6457 = eq(perr_ic_index_ff, UInt<6>("h03a")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6458 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6459 = and(_T_6457, _T_6458) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6460 = or(_T_6456, _T_6459) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6461 = or(_T_6460, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6462 = bits(_T_6461, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6463 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6462 : @[Reg.scala 28:19] + _T_6463 <= _T_6453 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][58] <= _T_6463 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6464 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6465 = eq(_T_6464, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6466 = and(ic_valid_ff, _T_6465) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6467 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6468 = and(_T_6466, _T_6467) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6469 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03b")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6470 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6471 = and(_T_6469, _T_6470) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6472 = eq(perr_ic_index_ff, UInt<6>("h03b")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6473 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6474 = and(_T_6472, _T_6473) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6475 = or(_T_6471, _T_6474) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6476 = or(_T_6475, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6477 = bits(_T_6476, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6478 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6477 : @[Reg.scala 28:19] + _T_6478 <= _T_6468 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][59] <= _T_6478 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6479 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6480 = eq(_T_6479, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6481 = and(ic_valid_ff, _T_6480) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6482 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6483 = and(_T_6481, _T_6482) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6484 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03c")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6485 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6486 = and(_T_6484, _T_6485) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6487 = eq(perr_ic_index_ff, UInt<6>("h03c")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6488 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6489 = and(_T_6487, _T_6488) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6490 = or(_T_6486, _T_6489) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6491 = or(_T_6490, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6492 = bits(_T_6491, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6493 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6492 : @[Reg.scala 28:19] + _T_6493 <= _T_6483 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][60] <= _T_6493 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6494 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6495 = eq(_T_6494, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6496 = and(ic_valid_ff, _T_6495) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6497 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6498 = and(_T_6496, _T_6497) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6499 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03d")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6500 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6501 = and(_T_6499, _T_6500) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6502 = eq(perr_ic_index_ff, UInt<6>("h03d")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6503 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6504 = and(_T_6502, _T_6503) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6505 = or(_T_6501, _T_6504) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6506 = or(_T_6505, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6507 = bits(_T_6506, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6508 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6507 : @[Reg.scala 28:19] + _T_6508 <= _T_6498 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][61] <= _T_6508 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6509 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6510 = eq(_T_6509, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6511 = and(ic_valid_ff, _T_6510) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6512 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6513 = and(_T_6511, _T_6512) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6514 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03e")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6515 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6516 = and(_T_6514, _T_6515) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6517 = eq(perr_ic_index_ff, UInt<6>("h03e")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6518 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6519 = and(_T_6517, _T_6518) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6520 = or(_T_6516, _T_6519) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6521 = or(_T_6520, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6522 = bits(_T_6521, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6523 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6522 : @[Reg.scala 28:19] + _T_6523 <= _T_6513 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][62] <= _T_6523 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6524 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6525 = eq(_T_6524, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6526 = and(ic_valid_ff, _T_6525) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6527 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6528 = and(_T_6526, _T_6527) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6529 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03f")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6530 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6531 = and(_T_6529, _T_6530) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6532 = eq(perr_ic_index_ff, UInt<6>("h03f")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6533 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6534 = and(_T_6532, _T_6533) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6535 = or(_T_6531, _T_6534) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6536 = or(_T_6535, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6537 = bits(_T_6536, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6538 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6537 : @[Reg.scala 28:19] + _T_6538 <= _T_6528 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][63] <= _T_6538 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6539 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6540 = eq(_T_6539, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6541 = and(ic_valid_ff, _T_6540) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6542 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6543 = and(_T_6541, _T_6542) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6544 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h020")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6545 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6546 = and(_T_6544, _T_6545) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6547 = eq(perr_ic_index_ff, UInt<6>("h020")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6548 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6549 = and(_T_6547, _T_6548) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6550 = or(_T_6546, _T_6549) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6551 = or(_T_6550, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6552 = bits(_T_6551, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6553 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6552 : @[Reg.scala 28:19] + _T_6553 <= _T_6543 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][32] <= _T_6553 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6554 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6555 = eq(_T_6554, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6556 = and(ic_valid_ff, _T_6555) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6557 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6558 = and(_T_6556, _T_6557) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6559 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h021")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6560 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6561 = and(_T_6559, _T_6560) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6562 = eq(perr_ic_index_ff, UInt<6>("h021")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6563 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6564 = and(_T_6562, _T_6563) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6565 = or(_T_6561, _T_6564) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6566 = or(_T_6565, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6567 = bits(_T_6566, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6568 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6567 : @[Reg.scala 28:19] + _T_6568 <= _T_6558 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][33] <= _T_6568 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6569 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6570 = eq(_T_6569, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6571 = and(ic_valid_ff, _T_6570) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6572 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6573 = and(_T_6571, _T_6572) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6574 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h022")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6575 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6576 = and(_T_6574, _T_6575) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6577 = eq(perr_ic_index_ff, UInt<6>("h022")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6578 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6579 = and(_T_6577, _T_6578) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6580 = or(_T_6576, _T_6579) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6581 = or(_T_6580, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6582 = bits(_T_6581, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6583 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6582 : @[Reg.scala 28:19] + _T_6583 <= _T_6573 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][34] <= _T_6583 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6584 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6585 = eq(_T_6584, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6586 = and(ic_valid_ff, _T_6585) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6587 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6588 = and(_T_6586, _T_6587) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6589 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h023")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6590 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6591 = and(_T_6589, _T_6590) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6592 = eq(perr_ic_index_ff, UInt<6>("h023")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6593 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6594 = and(_T_6592, _T_6593) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6595 = or(_T_6591, _T_6594) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6596 = or(_T_6595, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6597 = bits(_T_6596, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6598 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6597 : @[Reg.scala 28:19] + _T_6598 <= _T_6588 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][35] <= _T_6598 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6599 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6600 = eq(_T_6599, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6601 = and(ic_valid_ff, _T_6600) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6602 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6603 = and(_T_6601, _T_6602) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6604 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h024")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6605 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6606 = and(_T_6604, _T_6605) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6607 = eq(perr_ic_index_ff, UInt<6>("h024")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6608 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6609 = and(_T_6607, _T_6608) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6610 = or(_T_6606, _T_6609) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6611 = or(_T_6610, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6612 = bits(_T_6611, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6613 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6612 : @[Reg.scala 28:19] + _T_6613 <= _T_6603 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][36] <= _T_6613 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6614 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6615 = eq(_T_6614, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6616 = and(ic_valid_ff, _T_6615) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6617 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6618 = and(_T_6616, _T_6617) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6619 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h025")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6620 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6621 = and(_T_6619, _T_6620) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6622 = eq(perr_ic_index_ff, UInt<6>("h025")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6623 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6624 = and(_T_6622, _T_6623) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6625 = or(_T_6621, _T_6624) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6626 = or(_T_6625, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6627 = bits(_T_6626, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6628 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6627 : @[Reg.scala 28:19] + _T_6628 <= _T_6618 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][37] <= _T_6628 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6629 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6630 = eq(_T_6629, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6631 = and(ic_valid_ff, _T_6630) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6632 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6633 = and(_T_6631, _T_6632) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6634 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h026")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6635 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6636 = and(_T_6634, _T_6635) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6637 = eq(perr_ic_index_ff, UInt<6>("h026")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6638 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6639 = and(_T_6637, _T_6638) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6640 = or(_T_6636, _T_6639) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6641 = or(_T_6640, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6642 = bits(_T_6641, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6643 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6642 : @[Reg.scala 28:19] + _T_6643 <= _T_6633 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][38] <= _T_6643 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6644 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6645 = eq(_T_6644, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6646 = and(ic_valid_ff, _T_6645) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6647 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6648 = and(_T_6646, _T_6647) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6649 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h027")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6650 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6651 = and(_T_6649, _T_6650) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6652 = eq(perr_ic_index_ff, UInt<6>("h027")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6653 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6654 = and(_T_6652, _T_6653) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6655 = or(_T_6651, _T_6654) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6656 = or(_T_6655, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6657 = bits(_T_6656, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6658 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6657 : @[Reg.scala 28:19] + _T_6658 <= _T_6648 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][39] <= _T_6658 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6659 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6660 = eq(_T_6659, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6661 = and(ic_valid_ff, _T_6660) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6662 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6663 = and(_T_6661, _T_6662) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6664 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h028")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6665 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6666 = and(_T_6664, _T_6665) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6667 = eq(perr_ic_index_ff, UInt<6>("h028")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6668 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6669 = and(_T_6667, _T_6668) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6670 = or(_T_6666, _T_6669) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6671 = or(_T_6670, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6672 = bits(_T_6671, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6673 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6672 : @[Reg.scala 28:19] + _T_6673 <= _T_6663 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][40] <= _T_6673 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6674 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6675 = eq(_T_6674, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6676 = and(ic_valid_ff, _T_6675) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6677 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6678 = and(_T_6676, _T_6677) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6679 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h029")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6680 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6681 = and(_T_6679, _T_6680) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6682 = eq(perr_ic_index_ff, UInt<6>("h029")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6683 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6684 = and(_T_6682, _T_6683) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6685 = or(_T_6681, _T_6684) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6686 = or(_T_6685, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6687 = bits(_T_6686, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6688 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6687 : @[Reg.scala 28:19] + _T_6688 <= _T_6678 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][41] <= _T_6688 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6689 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6690 = eq(_T_6689, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6691 = and(ic_valid_ff, _T_6690) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6692 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6693 = and(_T_6691, _T_6692) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6694 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02a")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6695 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6696 = and(_T_6694, _T_6695) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6697 = eq(perr_ic_index_ff, UInt<6>("h02a")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6698 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6699 = and(_T_6697, _T_6698) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6700 = or(_T_6696, _T_6699) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6701 = or(_T_6700, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6702 = bits(_T_6701, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6703 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6702 : @[Reg.scala 28:19] + _T_6703 <= _T_6693 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][42] <= _T_6703 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6704 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6705 = eq(_T_6704, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6706 = and(ic_valid_ff, _T_6705) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6707 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6708 = and(_T_6706, _T_6707) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6709 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02b")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6710 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6711 = and(_T_6709, _T_6710) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6712 = eq(perr_ic_index_ff, UInt<6>("h02b")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6713 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6714 = and(_T_6712, _T_6713) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6715 = or(_T_6711, _T_6714) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6716 = or(_T_6715, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6717 = bits(_T_6716, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6718 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6717 : @[Reg.scala 28:19] + _T_6718 <= _T_6708 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][43] <= _T_6718 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6719 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6720 = eq(_T_6719, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6721 = and(ic_valid_ff, _T_6720) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6722 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6723 = and(_T_6721, _T_6722) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6724 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02c")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6725 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6726 = and(_T_6724, _T_6725) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6727 = eq(perr_ic_index_ff, UInt<6>("h02c")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6728 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6729 = and(_T_6727, _T_6728) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6730 = or(_T_6726, _T_6729) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6731 = or(_T_6730, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6732 = bits(_T_6731, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6733 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6732 : @[Reg.scala 28:19] + _T_6733 <= _T_6723 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][44] <= _T_6733 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6734 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6735 = eq(_T_6734, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6736 = and(ic_valid_ff, _T_6735) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6737 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6738 = and(_T_6736, _T_6737) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6739 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02d")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6740 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6741 = and(_T_6739, _T_6740) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6742 = eq(perr_ic_index_ff, UInt<6>("h02d")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6743 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6744 = and(_T_6742, _T_6743) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6745 = or(_T_6741, _T_6744) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6746 = or(_T_6745, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6747 = bits(_T_6746, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6748 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6747 : @[Reg.scala 28:19] + _T_6748 <= _T_6738 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][45] <= _T_6748 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6749 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6750 = eq(_T_6749, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6751 = and(ic_valid_ff, _T_6750) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6752 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6753 = and(_T_6751, _T_6752) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6754 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02e")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6755 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6756 = and(_T_6754, _T_6755) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6757 = eq(perr_ic_index_ff, UInt<6>("h02e")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6758 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6759 = and(_T_6757, _T_6758) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6760 = or(_T_6756, _T_6759) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6761 = or(_T_6760, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6762 = bits(_T_6761, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6763 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6762 : @[Reg.scala 28:19] + _T_6763 <= _T_6753 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][46] <= _T_6763 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6764 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6765 = eq(_T_6764, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6766 = and(ic_valid_ff, _T_6765) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6767 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6768 = and(_T_6766, _T_6767) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6769 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02f")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6770 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6771 = and(_T_6769, _T_6770) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6772 = eq(perr_ic_index_ff, UInt<6>("h02f")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6773 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6774 = and(_T_6772, _T_6773) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6775 = or(_T_6771, _T_6774) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6776 = or(_T_6775, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6777 = bits(_T_6776, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6778 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6777 : @[Reg.scala 28:19] + _T_6778 <= _T_6768 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][47] <= _T_6778 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6779 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6780 = eq(_T_6779, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6781 = and(ic_valid_ff, _T_6780) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6782 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6783 = and(_T_6781, _T_6782) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6784 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h030")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6785 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6786 = and(_T_6784, _T_6785) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6787 = eq(perr_ic_index_ff, UInt<6>("h030")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6788 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6789 = and(_T_6787, _T_6788) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6790 = or(_T_6786, _T_6789) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6791 = or(_T_6790, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6792 = bits(_T_6791, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6793 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6792 : @[Reg.scala 28:19] + _T_6793 <= _T_6783 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][48] <= _T_6793 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6794 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6795 = eq(_T_6794, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6796 = and(ic_valid_ff, _T_6795) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6797 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6798 = and(_T_6796, _T_6797) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6799 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h031")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6800 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6801 = and(_T_6799, _T_6800) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6802 = eq(perr_ic_index_ff, UInt<6>("h031")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6803 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6804 = and(_T_6802, _T_6803) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6805 = or(_T_6801, _T_6804) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6806 = or(_T_6805, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6807 = bits(_T_6806, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6808 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6807 : @[Reg.scala 28:19] + _T_6808 <= _T_6798 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][49] <= _T_6808 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6809 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6810 = eq(_T_6809, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6811 = and(ic_valid_ff, _T_6810) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6812 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6813 = and(_T_6811, _T_6812) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6814 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h032")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6815 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6816 = and(_T_6814, _T_6815) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6817 = eq(perr_ic_index_ff, UInt<6>("h032")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6818 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6819 = and(_T_6817, _T_6818) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6820 = or(_T_6816, _T_6819) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6821 = or(_T_6820, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6822 = bits(_T_6821, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6823 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6822 : @[Reg.scala 28:19] + _T_6823 <= _T_6813 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][50] <= _T_6823 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6824 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6825 = eq(_T_6824, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6826 = and(ic_valid_ff, _T_6825) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6827 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6828 = and(_T_6826, _T_6827) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6829 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h033")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6830 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6831 = and(_T_6829, _T_6830) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6832 = eq(perr_ic_index_ff, UInt<6>("h033")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6833 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6834 = and(_T_6832, _T_6833) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6835 = or(_T_6831, _T_6834) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6836 = or(_T_6835, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6837 = bits(_T_6836, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6838 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6837 : @[Reg.scala 28:19] + _T_6838 <= _T_6828 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][51] <= _T_6838 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6839 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6840 = eq(_T_6839, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6841 = and(ic_valid_ff, _T_6840) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6842 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6843 = and(_T_6841, _T_6842) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6844 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h034")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6845 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6846 = and(_T_6844, _T_6845) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6847 = eq(perr_ic_index_ff, UInt<6>("h034")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6848 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6849 = and(_T_6847, _T_6848) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6850 = or(_T_6846, _T_6849) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6851 = or(_T_6850, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6852 = bits(_T_6851, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6853 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6852 : @[Reg.scala 28:19] + _T_6853 <= _T_6843 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][52] <= _T_6853 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6854 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6855 = eq(_T_6854, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6856 = and(ic_valid_ff, _T_6855) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6857 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6858 = and(_T_6856, _T_6857) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6859 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h035")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6860 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6861 = and(_T_6859, _T_6860) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6862 = eq(perr_ic_index_ff, UInt<6>("h035")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6863 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6864 = and(_T_6862, _T_6863) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6865 = or(_T_6861, _T_6864) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6866 = or(_T_6865, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6867 = bits(_T_6866, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6868 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6867 : @[Reg.scala 28:19] + _T_6868 <= _T_6858 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][53] <= _T_6868 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6869 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6870 = eq(_T_6869, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6871 = and(ic_valid_ff, _T_6870) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6872 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6873 = and(_T_6871, _T_6872) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6874 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h036")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6875 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6876 = and(_T_6874, _T_6875) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6877 = eq(perr_ic_index_ff, UInt<6>("h036")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6878 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6879 = and(_T_6877, _T_6878) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6880 = or(_T_6876, _T_6879) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6881 = or(_T_6880, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6882 = bits(_T_6881, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6883 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6882 : @[Reg.scala 28:19] + _T_6883 <= _T_6873 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][54] <= _T_6883 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6884 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6885 = eq(_T_6884, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6886 = and(ic_valid_ff, _T_6885) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6887 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6888 = and(_T_6886, _T_6887) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6889 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h037")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6890 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6891 = and(_T_6889, _T_6890) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6892 = eq(perr_ic_index_ff, UInt<6>("h037")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6893 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6894 = and(_T_6892, _T_6893) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6895 = or(_T_6891, _T_6894) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6896 = or(_T_6895, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6897 = bits(_T_6896, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6898 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6897 : @[Reg.scala 28:19] + _T_6898 <= _T_6888 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][55] <= _T_6898 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6899 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6900 = eq(_T_6899, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6901 = and(ic_valid_ff, _T_6900) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6902 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6903 = and(_T_6901, _T_6902) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6904 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h038")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6905 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6906 = and(_T_6904, _T_6905) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6907 = eq(perr_ic_index_ff, UInt<6>("h038")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6908 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6909 = and(_T_6907, _T_6908) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6910 = or(_T_6906, _T_6909) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6911 = or(_T_6910, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6912 = bits(_T_6911, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6913 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6912 : @[Reg.scala 28:19] + _T_6913 <= _T_6903 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][56] <= _T_6913 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6914 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6915 = eq(_T_6914, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6916 = and(ic_valid_ff, _T_6915) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6917 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6918 = and(_T_6916, _T_6917) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6919 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h039")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6920 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6921 = and(_T_6919, _T_6920) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6922 = eq(perr_ic_index_ff, UInt<6>("h039")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6923 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6924 = and(_T_6922, _T_6923) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6925 = or(_T_6921, _T_6924) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6926 = or(_T_6925, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6927 = bits(_T_6926, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6928 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6927 : @[Reg.scala 28:19] + _T_6928 <= _T_6918 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][57] <= _T_6928 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6929 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6930 = eq(_T_6929, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6931 = and(ic_valid_ff, _T_6930) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6932 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6933 = and(_T_6931, _T_6932) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6934 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03a")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6935 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6936 = and(_T_6934, _T_6935) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6937 = eq(perr_ic_index_ff, UInt<6>("h03a")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6938 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6939 = and(_T_6937, _T_6938) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6940 = or(_T_6936, _T_6939) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6941 = or(_T_6940, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6942 = bits(_T_6941, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6943 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6942 : @[Reg.scala 28:19] + _T_6943 <= _T_6933 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][58] <= _T_6943 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6944 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6945 = eq(_T_6944, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6946 = and(ic_valid_ff, _T_6945) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6947 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6948 = and(_T_6946, _T_6947) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6949 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03b")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6950 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6951 = and(_T_6949, _T_6950) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6952 = eq(perr_ic_index_ff, UInt<6>("h03b")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6953 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6954 = and(_T_6952, _T_6953) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6955 = or(_T_6951, _T_6954) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6956 = or(_T_6955, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6957 = bits(_T_6956, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6958 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6957 : @[Reg.scala 28:19] + _T_6958 <= _T_6948 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][59] <= _T_6958 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6959 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6960 = eq(_T_6959, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6961 = and(ic_valid_ff, _T_6960) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6962 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6963 = and(_T_6961, _T_6962) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6964 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03c")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6965 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6966 = and(_T_6964, _T_6965) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6967 = eq(perr_ic_index_ff, UInt<6>("h03c")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6968 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6969 = and(_T_6967, _T_6968) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6970 = or(_T_6966, _T_6969) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6971 = or(_T_6970, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6972 = bits(_T_6971, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6973 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6972 : @[Reg.scala 28:19] + _T_6973 <= _T_6963 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][60] <= _T_6973 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6974 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6975 = eq(_T_6974, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6976 = and(ic_valid_ff, _T_6975) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6977 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6978 = and(_T_6976, _T_6977) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6979 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03d")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6980 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6981 = and(_T_6979, _T_6980) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6982 = eq(perr_ic_index_ff, UInt<6>("h03d")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6983 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6984 = and(_T_6982, _T_6983) @[el2_ifu_mem_ctl.scala 761:120] + node _T_6985 = or(_T_6981, _T_6984) @[el2_ifu_mem_ctl.scala 761:77] + node _T_6986 = or(_T_6985, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_6987 = bits(_T_6986, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_6988 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6987 : @[Reg.scala 28:19] + _T_6988 <= _T_6978 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][61] <= _T_6988 @[el2_ifu_mem_ctl.scala 760:39] + node _T_6989 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_6990 = eq(_T_6989, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_6991 = and(ic_valid_ff, _T_6990) @[el2_ifu_mem_ctl.scala 760:95] + node _T_6992 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_6993 = and(_T_6991, _T_6992) @[el2_ifu_mem_ctl.scala 760:120] + node _T_6994 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03e")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_6995 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_6996 = and(_T_6994, _T_6995) @[el2_ifu_mem_ctl.scala 761:55] + node _T_6997 = eq(perr_ic_index_ff, UInt<6>("h03e")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_6998 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_6999 = and(_T_6997, _T_6998) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7000 = or(_T_6996, _T_6999) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7001 = or(_T_7000, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7002 = bits(_T_7001, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7003 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7002 : @[Reg.scala 28:19] + _T_7003 <= _T_6993 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][62] <= _T_7003 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7004 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7005 = eq(_T_7004, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7006 = and(ic_valid_ff, _T_7005) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7007 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7008 = and(_T_7006, _T_7007) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7009 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03f")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7010 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7011 = and(_T_7009, _T_7010) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7012 = eq(perr_ic_index_ff, UInt<6>("h03f")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7013 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7014 = and(_T_7012, _T_7013) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7015 = or(_T_7011, _T_7014) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7016 = or(_T_7015, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7017 = bits(_T_7016, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7018 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7017 : @[Reg.scala 28:19] + _T_7018 <= _T_7008 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][63] <= _T_7018 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7019 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7020 = eq(_T_7019, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7021 = and(ic_valid_ff, _T_7020) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7022 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7023 = and(_T_7021, _T_7022) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7024 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h040")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7025 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7026 = and(_T_7024, _T_7025) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7027 = eq(perr_ic_index_ff, UInt<7>("h040")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7028 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7029 = and(_T_7027, _T_7028) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7030 = or(_T_7026, _T_7029) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7031 = or(_T_7030, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7032 = bits(_T_7031, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7033 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7032 : @[Reg.scala 28:19] + _T_7033 <= _T_7023 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][64] <= _T_7033 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7034 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7035 = eq(_T_7034, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7036 = and(ic_valid_ff, _T_7035) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7037 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7038 = and(_T_7036, _T_7037) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7039 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h041")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7040 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7041 = and(_T_7039, _T_7040) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7042 = eq(perr_ic_index_ff, UInt<7>("h041")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7043 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7044 = and(_T_7042, _T_7043) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7045 = or(_T_7041, _T_7044) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7046 = or(_T_7045, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7047 = bits(_T_7046, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7048 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7047 : @[Reg.scala 28:19] + _T_7048 <= _T_7038 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][65] <= _T_7048 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7049 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7050 = eq(_T_7049, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7051 = and(ic_valid_ff, _T_7050) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7052 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7053 = and(_T_7051, _T_7052) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7054 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h042")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7055 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7056 = and(_T_7054, _T_7055) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7057 = eq(perr_ic_index_ff, UInt<7>("h042")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7058 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7059 = and(_T_7057, _T_7058) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7060 = or(_T_7056, _T_7059) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7061 = or(_T_7060, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7062 = bits(_T_7061, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7063 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7062 : @[Reg.scala 28:19] + _T_7063 <= _T_7053 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][66] <= _T_7063 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7064 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7065 = eq(_T_7064, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7066 = and(ic_valid_ff, _T_7065) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7067 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7068 = and(_T_7066, _T_7067) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7069 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h043")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7070 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7071 = and(_T_7069, _T_7070) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7072 = eq(perr_ic_index_ff, UInt<7>("h043")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7073 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7074 = and(_T_7072, _T_7073) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7075 = or(_T_7071, _T_7074) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7076 = or(_T_7075, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7077 = bits(_T_7076, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7078 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7077 : @[Reg.scala 28:19] + _T_7078 <= _T_7068 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][67] <= _T_7078 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7079 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7080 = eq(_T_7079, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7081 = and(ic_valid_ff, _T_7080) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7082 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7083 = and(_T_7081, _T_7082) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7084 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h044")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7085 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7086 = and(_T_7084, _T_7085) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7087 = eq(perr_ic_index_ff, UInt<7>("h044")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7088 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7089 = and(_T_7087, _T_7088) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7090 = or(_T_7086, _T_7089) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7091 = or(_T_7090, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7092 = bits(_T_7091, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7093 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7092 : @[Reg.scala 28:19] + _T_7093 <= _T_7083 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][68] <= _T_7093 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7094 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7095 = eq(_T_7094, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7096 = and(ic_valid_ff, _T_7095) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7097 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7098 = and(_T_7096, _T_7097) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7099 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h045")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7100 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7101 = and(_T_7099, _T_7100) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7102 = eq(perr_ic_index_ff, UInt<7>("h045")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7103 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7104 = and(_T_7102, _T_7103) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7105 = or(_T_7101, _T_7104) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7106 = or(_T_7105, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7107 = bits(_T_7106, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7108 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7107 : @[Reg.scala 28:19] + _T_7108 <= _T_7098 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][69] <= _T_7108 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7109 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7110 = eq(_T_7109, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7111 = and(ic_valid_ff, _T_7110) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7112 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7113 = and(_T_7111, _T_7112) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7114 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h046")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7115 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7116 = and(_T_7114, _T_7115) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7117 = eq(perr_ic_index_ff, UInt<7>("h046")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7118 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7119 = and(_T_7117, _T_7118) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7120 = or(_T_7116, _T_7119) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7121 = or(_T_7120, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7122 = bits(_T_7121, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7123 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7122 : @[Reg.scala 28:19] + _T_7123 <= _T_7113 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][70] <= _T_7123 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7124 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7125 = eq(_T_7124, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7126 = and(ic_valid_ff, _T_7125) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7127 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7128 = and(_T_7126, _T_7127) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7129 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h047")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7130 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7131 = and(_T_7129, _T_7130) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7132 = eq(perr_ic_index_ff, UInt<7>("h047")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7133 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7134 = and(_T_7132, _T_7133) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7135 = or(_T_7131, _T_7134) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7136 = or(_T_7135, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7137 = bits(_T_7136, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7138 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7137 : @[Reg.scala 28:19] + _T_7138 <= _T_7128 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][71] <= _T_7138 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7139 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7140 = eq(_T_7139, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7141 = and(ic_valid_ff, _T_7140) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7142 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7143 = and(_T_7141, _T_7142) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7144 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h048")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7145 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7146 = and(_T_7144, _T_7145) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7147 = eq(perr_ic_index_ff, UInt<7>("h048")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7148 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7149 = and(_T_7147, _T_7148) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7150 = or(_T_7146, _T_7149) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7151 = or(_T_7150, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7152 = bits(_T_7151, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7153 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7152 : @[Reg.scala 28:19] + _T_7153 <= _T_7143 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][72] <= _T_7153 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7154 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7155 = eq(_T_7154, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7156 = and(ic_valid_ff, _T_7155) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7157 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7158 = and(_T_7156, _T_7157) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7159 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h049")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7160 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7161 = and(_T_7159, _T_7160) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7162 = eq(perr_ic_index_ff, UInt<7>("h049")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7163 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7164 = and(_T_7162, _T_7163) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7165 = or(_T_7161, _T_7164) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7166 = or(_T_7165, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7167 = bits(_T_7166, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7168 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7167 : @[Reg.scala 28:19] + _T_7168 <= _T_7158 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][73] <= _T_7168 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7169 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7170 = eq(_T_7169, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7171 = and(ic_valid_ff, _T_7170) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7172 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7173 = and(_T_7171, _T_7172) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7174 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04a")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7175 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7176 = and(_T_7174, _T_7175) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7177 = eq(perr_ic_index_ff, UInt<7>("h04a")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7178 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7179 = and(_T_7177, _T_7178) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7180 = or(_T_7176, _T_7179) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7181 = or(_T_7180, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7182 = bits(_T_7181, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7183 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7182 : @[Reg.scala 28:19] + _T_7183 <= _T_7173 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][74] <= _T_7183 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7184 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7185 = eq(_T_7184, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7186 = and(ic_valid_ff, _T_7185) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7187 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7188 = and(_T_7186, _T_7187) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7189 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04b")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7190 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7191 = and(_T_7189, _T_7190) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7192 = eq(perr_ic_index_ff, UInt<7>("h04b")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7193 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7194 = and(_T_7192, _T_7193) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7195 = or(_T_7191, _T_7194) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7196 = or(_T_7195, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7197 = bits(_T_7196, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7198 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7197 : @[Reg.scala 28:19] + _T_7198 <= _T_7188 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][75] <= _T_7198 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7199 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7200 = eq(_T_7199, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7201 = and(ic_valid_ff, _T_7200) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7202 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7203 = and(_T_7201, _T_7202) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7204 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04c")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7205 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7206 = and(_T_7204, _T_7205) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7207 = eq(perr_ic_index_ff, UInt<7>("h04c")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7208 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7209 = and(_T_7207, _T_7208) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7210 = or(_T_7206, _T_7209) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7211 = or(_T_7210, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7212 = bits(_T_7211, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7213 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7212 : @[Reg.scala 28:19] + _T_7213 <= _T_7203 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][76] <= _T_7213 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7214 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7215 = eq(_T_7214, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7216 = and(ic_valid_ff, _T_7215) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7217 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7218 = and(_T_7216, _T_7217) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7219 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04d")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7220 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7221 = and(_T_7219, _T_7220) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7222 = eq(perr_ic_index_ff, UInt<7>("h04d")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7223 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7224 = and(_T_7222, _T_7223) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7225 = or(_T_7221, _T_7224) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7226 = or(_T_7225, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7227 = bits(_T_7226, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7228 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7227 : @[Reg.scala 28:19] + _T_7228 <= _T_7218 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][77] <= _T_7228 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7229 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7230 = eq(_T_7229, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7231 = and(ic_valid_ff, _T_7230) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7232 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7233 = and(_T_7231, _T_7232) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7234 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04e")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7235 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7236 = and(_T_7234, _T_7235) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7237 = eq(perr_ic_index_ff, UInt<7>("h04e")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7238 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7239 = and(_T_7237, _T_7238) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7240 = or(_T_7236, _T_7239) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7241 = or(_T_7240, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7242 = bits(_T_7241, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7243 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7242 : @[Reg.scala 28:19] + _T_7243 <= _T_7233 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][78] <= _T_7243 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7244 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7245 = eq(_T_7244, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7246 = and(ic_valid_ff, _T_7245) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7247 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7248 = and(_T_7246, _T_7247) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7249 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04f")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7250 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7251 = and(_T_7249, _T_7250) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7252 = eq(perr_ic_index_ff, UInt<7>("h04f")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7253 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7254 = and(_T_7252, _T_7253) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7255 = or(_T_7251, _T_7254) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7256 = or(_T_7255, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7257 = bits(_T_7256, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7258 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7257 : @[Reg.scala 28:19] + _T_7258 <= _T_7248 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][79] <= _T_7258 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7259 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7260 = eq(_T_7259, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7261 = and(ic_valid_ff, _T_7260) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7262 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7263 = and(_T_7261, _T_7262) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7264 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h050")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7265 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7266 = and(_T_7264, _T_7265) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7267 = eq(perr_ic_index_ff, UInt<7>("h050")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7268 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7269 = and(_T_7267, _T_7268) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7270 = or(_T_7266, _T_7269) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7271 = or(_T_7270, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7272 = bits(_T_7271, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7273 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7272 : @[Reg.scala 28:19] + _T_7273 <= _T_7263 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][80] <= _T_7273 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7274 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7275 = eq(_T_7274, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7276 = and(ic_valid_ff, _T_7275) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7277 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7278 = and(_T_7276, _T_7277) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7279 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h051")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7280 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7281 = and(_T_7279, _T_7280) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7282 = eq(perr_ic_index_ff, UInt<7>("h051")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7283 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7284 = and(_T_7282, _T_7283) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7285 = or(_T_7281, _T_7284) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7286 = or(_T_7285, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7287 = bits(_T_7286, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7288 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7287 : @[Reg.scala 28:19] + _T_7288 <= _T_7278 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][81] <= _T_7288 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7289 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7290 = eq(_T_7289, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7291 = and(ic_valid_ff, _T_7290) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7292 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7293 = and(_T_7291, _T_7292) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7294 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h052")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7295 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7296 = and(_T_7294, _T_7295) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7297 = eq(perr_ic_index_ff, UInt<7>("h052")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7298 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7299 = and(_T_7297, _T_7298) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7300 = or(_T_7296, _T_7299) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7301 = or(_T_7300, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7302 = bits(_T_7301, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7303 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7302 : @[Reg.scala 28:19] + _T_7303 <= _T_7293 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][82] <= _T_7303 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7304 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7305 = eq(_T_7304, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7306 = and(ic_valid_ff, _T_7305) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7307 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7308 = and(_T_7306, _T_7307) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7309 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h053")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7310 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7311 = and(_T_7309, _T_7310) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7312 = eq(perr_ic_index_ff, UInt<7>("h053")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7313 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7314 = and(_T_7312, _T_7313) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7315 = or(_T_7311, _T_7314) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7316 = or(_T_7315, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7317 = bits(_T_7316, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7318 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7317 : @[Reg.scala 28:19] + _T_7318 <= _T_7308 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][83] <= _T_7318 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7319 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7320 = eq(_T_7319, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7321 = and(ic_valid_ff, _T_7320) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7322 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7323 = and(_T_7321, _T_7322) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7324 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h054")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7325 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7326 = and(_T_7324, _T_7325) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7327 = eq(perr_ic_index_ff, UInt<7>("h054")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7328 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7329 = and(_T_7327, _T_7328) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7330 = or(_T_7326, _T_7329) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7331 = or(_T_7330, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7332 = bits(_T_7331, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7333 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7332 : @[Reg.scala 28:19] + _T_7333 <= _T_7323 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][84] <= _T_7333 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7334 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7335 = eq(_T_7334, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7336 = and(ic_valid_ff, _T_7335) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7337 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7338 = and(_T_7336, _T_7337) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7339 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h055")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7340 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7341 = and(_T_7339, _T_7340) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7342 = eq(perr_ic_index_ff, UInt<7>("h055")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7343 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7344 = and(_T_7342, _T_7343) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7345 = or(_T_7341, _T_7344) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7346 = or(_T_7345, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7347 = bits(_T_7346, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7348 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7347 : @[Reg.scala 28:19] + _T_7348 <= _T_7338 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][85] <= _T_7348 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7349 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7350 = eq(_T_7349, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7351 = and(ic_valid_ff, _T_7350) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7352 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7353 = and(_T_7351, _T_7352) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7354 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h056")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7355 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7356 = and(_T_7354, _T_7355) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7357 = eq(perr_ic_index_ff, UInt<7>("h056")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7358 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7359 = and(_T_7357, _T_7358) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7360 = or(_T_7356, _T_7359) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7361 = or(_T_7360, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7362 = bits(_T_7361, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7363 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7362 : @[Reg.scala 28:19] + _T_7363 <= _T_7353 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][86] <= _T_7363 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7364 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7365 = eq(_T_7364, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7366 = and(ic_valid_ff, _T_7365) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7367 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7368 = and(_T_7366, _T_7367) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7369 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h057")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7370 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7371 = and(_T_7369, _T_7370) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7372 = eq(perr_ic_index_ff, UInt<7>("h057")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7373 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7374 = and(_T_7372, _T_7373) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7375 = or(_T_7371, _T_7374) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7376 = or(_T_7375, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7377 = bits(_T_7376, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7378 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7377 : @[Reg.scala 28:19] + _T_7378 <= _T_7368 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][87] <= _T_7378 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7379 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7380 = eq(_T_7379, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7381 = and(ic_valid_ff, _T_7380) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7382 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7383 = and(_T_7381, _T_7382) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7384 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h058")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7385 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7386 = and(_T_7384, _T_7385) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7387 = eq(perr_ic_index_ff, UInt<7>("h058")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7388 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7389 = and(_T_7387, _T_7388) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7390 = or(_T_7386, _T_7389) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7391 = or(_T_7390, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7392 = bits(_T_7391, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7393 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7392 : @[Reg.scala 28:19] + _T_7393 <= _T_7383 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][88] <= _T_7393 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7394 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7395 = eq(_T_7394, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7396 = and(ic_valid_ff, _T_7395) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7397 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7398 = and(_T_7396, _T_7397) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7399 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h059")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7400 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7401 = and(_T_7399, _T_7400) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7402 = eq(perr_ic_index_ff, UInt<7>("h059")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7403 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7404 = and(_T_7402, _T_7403) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7405 = or(_T_7401, _T_7404) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7406 = or(_T_7405, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7407 = bits(_T_7406, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7408 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7407 : @[Reg.scala 28:19] + _T_7408 <= _T_7398 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][89] <= _T_7408 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7409 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7410 = eq(_T_7409, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7411 = and(ic_valid_ff, _T_7410) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7412 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7413 = and(_T_7411, _T_7412) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7414 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05a")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7415 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7416 = and(_T_7414, _T_7415) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7417 = eq(perr_ic_index_ff, UInt<7>("h05a")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7418 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7419 = and(_T_7417, _T_7418) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7420 = or(_T_7416, _T_7419) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7421 = or(_T_7420, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7422 = bits(_T_7421, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7423 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7422 : @[Reg.scala 28:19] + _T_7423 <= _T_7413 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][90] <= _T_7423 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7424 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7425 = eq(_T_7424, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7426 = and(ic_valid_ff, _T_7425) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7427 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7428 = and(_T_7426, _T_7427) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7429 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05b")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7430 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7431 = and(_T_7429, _T_7430) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7432 = eq(perr_ic_index_ff, UInt<7>("h05b")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7433 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7434 = and(_T_7432, _T_7433) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7435 = or(_T_7431, _T_7434) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7436 = or(_T_7435, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7437 = bits(_T_7436, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7438 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7437 : @[Reg.scala 28:19] + _T_7438 <= _T_7428 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][91] <= _T_7438 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7439 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7440 = eq(_T_7439, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7441 = and(ic_valid_ff, _T_7440) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7442 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7443 = and(_T_7441, _T_7442) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7444 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05c")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7445 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7446 = and(_T_7444, _T_7445) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7447 = eq(perr_ic_index_ff, UInt<7>("h05c")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7448 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7449 = and(_T_7447, _T_7448) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7450 = or(_T_7446, _T_7449) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7451 = or(_T_7450, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7452 = bits(_T_7451, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7453 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7452 : @[Reg.scala 28:19] + _T_7453 <= _T_7443 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][92] <= _T_7453 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7454 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7455 = eq(_T_7454, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7456 = and(ic_valid_ff, _T_7455) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7457 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7458 = and(_T_7456, _T_7457) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7459 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05d")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7460 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7461 = and(_T_7459, _T_7460) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7462 = eq(perr_ic_index_ff, UInt<7>("h05d")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7463 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7464 = and(_T_7462, _T_7463) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7465 = or(_T_7461, _T_7464) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7466 = or(_T_7465, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7467 = bits(_T_7466, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7468 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7467 : @[Reg.scala 28:19] + _T_7468 <= _T_7458 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][93] <= _T_7468 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7469 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7470 = eq(_T_7469, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7471 = and(ic_valid_ff, _T_7470) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7472 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7473 = and(_T_7471, _T_7472) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7474 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05e")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7475 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7476 = and(_T_7474, _T_7475) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7477 = eq(perr_ic_index_ff, UInt<7>("h05e")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7478 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7479 = and(_T_7477, _T_7478) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7480 = or(_T_7476, _T_7479) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7481 = or(_T_7480, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7482 = bits(_T_7481, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7483 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7482 : @[Reg.scala 28:19] + _T_7483 <= _T_7473 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][94] <= _T_7483 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7484 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7485 = eq(_T_7484, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7486 = and(ic_valid_ff, _T_7485) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7487 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7488 = and(_T_7486, _T_7487) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7489 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05f")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7490 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7491 = and(_T_7489, _T_7490) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7492 = eq(perr_ic_index_ff, UInt<7>("h05f")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7493 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7494 = and(_T_7492, _T_7493) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7495 = or(_T_7491, _T_7494) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7496 = or(_T_7495, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7497 = bits(_T_7496, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7498 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7497 : @[Reg.scala 28:19] + _T_7498 <= _T_7488 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][95] <= _T_7498 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7499 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7500 = eq(_T_7499, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7501 = and(ic_valid_ff, _T_7500) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7502 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7503 = and(_T_7501, _T_7502) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7504 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h040")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7505 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7506 = and(_T_7504, _T_7505) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7507 = eq(perr_ic_index_ff, UInt<7>("h040")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7508 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7509 = and(_T_7507, _T_7508) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7510 = or(_T_7506, _T_7509) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7511 = or(_T_7510, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7512 = bits(_T_7511, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7513 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7512 : @[Reg.scala 28:19] + _T_7513 <= _T_7503 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][64] <= _T_7513 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7514 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7515 = eq(_T_7514, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7516 = and(ic_valid_ff, _T_7515) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7517 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7518 = and(_T_7516, _T_7517) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7519 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h041")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7520 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7521 = and(_T_7519, _T_7520) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7522 = eq(perr_ic_index_ff, UInt<7>("h041")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7523 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7524 = and(_T_7522, _T_7523) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7525 = or(_T_7521, _T_7524) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7526 = or(_T_7525, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7527 = bits(_T_7526, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7528 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7527 : @[Reg.scala 28:19] + _T_7528 <= _T_7518 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][65] <= _T_7528 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7529 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7530 = eq(_T_7529, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7531 = and(ic_valid_ff, _T_7530) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7532 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7533 = and(_T_7531, _T_7532) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7534 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h042")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7535 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7536 = and(_T_7534, _T_7535) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7537 = eq(perr_ic_index_ff, UInt<7>("h042")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7538 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7539 = and(_T_7537, _T_7538) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7540 = or(_T_7536, _T_7539) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7541 = or(_T_7540, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7542 = bits(_T_7541, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7543 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7542 : @[Reg.scala 28:19] + _T_7543 <= _T_7533 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][66] <= _T_7543 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7544 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7545 = eq(_T_7544, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7546 = and(ic_valid_ff, _T_7545) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7547 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7548 = and(_T_7546, _T_7547) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7549 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h043")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7550 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7551 = and(_T_7549, _T_7550) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7552 = eq(perr_ic_index_ff, UInt<7>("h043")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7553 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7554 = and(_T_7552, _T_7553) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7555 = or(_T_7551, _T_7554) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7556 = or(_T_7555, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7557 = bits(_T_7556, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7558 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7557 : @[Reg.scala 28:19] + _T_7558 <= _T_7548 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][67] <= _T_7558 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7559 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7560 = eq(_T_7559, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7561 = and(ic_valid_ff, _T_7560) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7562 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7563 = and(_T_7561, _T_7562) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7564 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h044")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7565 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7566 = and(_T_7564, _T_7565) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7567 = eq(perr_ic_index_ff, UInt<7>("h044")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7568 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7569 = and(_T_7567, _T_7568) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7570 = or(_T_7566, _T_7569) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7571 = or(_T_7570, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7572 = bits(_T_7571, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7573 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7572 : @[Reg.scala 28:19] + _T_7573 <= _T_7563 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][68] <= _T_7573 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7574 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7575 = eq(_T_7574, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7576 = and(ic_valid_ff, _T_7575) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7577 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7578 = and(_T_7576, _T_7577) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7579 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h045")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7580 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7581 = and(_T_7579, _T_7580) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7582 = eq(perr_ic_index_ff, UInt<7>("h045")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7583 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7584 = and(_T_7582, _T_7583) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7585 = or(_T_7581, _T_7584) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7586 = or(_T_7585, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7587 = bits(_T_7586, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7588 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7587 : @[Reg.scala 28:19] + _T_7588 <= _T_7578 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][69] <= _T_7588 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7589 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7590 = eq(_T_7589, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7591 = and(ic_valid_ff, _T_7590) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7592 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7593 = and(_T_7591, _T_7592) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7594 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h046")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7595 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7596 = and(_T_7594, _T_7595) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7597 = eq(perr_ic_index_ff, UInt<7>("h046")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7598 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7599 = and(_T_7597, _T_7598) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7600 = or(_T_7596, _T_7599) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7601 = or(_T_7600, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7602 = bits(_T_7601, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7603 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7602 : @[Reg.scala 28:19] + _T_7603 <= _T_7593 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][70] <= _T_7603 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7604 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7605 = eq(_T_7604, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7606 = and(ic_valid_ff, _T_7605) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7607 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7608 = and(_T_7606, _T_7607) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7609 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h047")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7610 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7611 = and(_T_7609, _T_7610) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7612 = eq(perr_ic_index_ff, UInt<7>("h047")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7613 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7614 = and(_T_7612, _T_7613) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7615 = or(_T_7611, _T_7614) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7616 = or(_T_7615, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7617 = bits(_T_7616, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7618 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7617 : @[Reg.scala 28:19] + _T_7618 <= _T_7608 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][71] <= _T_7618 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7619 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7620 = eq(_T_7619, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7621 = and(ic_valid_ff, _T_7620) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7622 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7623 = and(_T_7621, _T_7622) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7624 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h048")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7625 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7626 = and(_T_7624, _T_7625) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7627 = eq(perr_ic_index_ff, UInt<7>("h048")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7628 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7629 = and(_T_7627, _T_7628) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7630 = or(_T_7626, _T_7629) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7631 = or(_T_7630, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7632 = bits(_T_7631, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7633 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7632 : @[Reg.scala 28:19] + _T_7633 <= _T_7623 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][72] <= _T_7633 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7634 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7635 = eq(_T_7634, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7636 = and(ic_valid_ff, _T_7635) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7637 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7638 = and(_T_7636, _T_7637) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7639 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h049")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7640 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7641 = and(_T_7639, _T_7640) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7642 = eq(perr_ic_index_ff, UInt<7>("h049")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7643 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7644 = and(_T_7642, _T_7643) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7645 = or(_T_7641, _T_7644) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7646 = or(_T_7645, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7647 = bits(_T_7646, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7648 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7647 : @[Reg.scala 28:19] + _T_7648 <= _T_7638 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][73] <= _T_7648 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7649 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7650 = eq(_T_7649, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7651 = and(ic_valid_ff, _T_7650) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7652 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7653 = and(_T_7651, _T_7652) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7654 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04a")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7655 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7656 = and(_T_7654, _T_7655) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7657 = eq(perr_ic_index_ff, UInt<7>("h04a")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7658 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7659 = and(_T_7657, _T_7658) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7660 = or(_T_7656, _T_7659) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7661 = or(_T_7660, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7662 = bits(_T_7661, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7663 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7662 : @[Reg.scala 28:19] + _T_7663 <= _T_7653 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][74] <= _T_7663 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7664 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7665 = eq(_T_7664, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7666 = and(ic_valid_ff, _T_7665) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7667 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7668 = and(_T_7666, _T_7667) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7669 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04b")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7670 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7671 = and(_T_7669, _T_7670) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7672 = eq(perr_ic_index_ff, UInt<7>("h04b")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7673 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7674 = and(_T_7672, _T_7673) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7675 = or(_T_7671, _T_7674) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7676 = or(_T_7675, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7677 = bits(_T_7676, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7678 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7677 : @[Reg.scala 28:19] + _T_7678 <= _T_7668 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][75] <= _T_7678 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7679 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7680 = eq(_T_7679, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7681 = and(ic_valid_ff, _T_7680) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7682 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7683 = and(_T_7681, _T_7682) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7684 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04c")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7685 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7686 = and(_T_7684, _T_7685) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7687 = eq(perr_ic_index_ff, UInt<7>("h04c")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7688 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7689 = and(_T_7687, _T_7688) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7690 = or(_T_7686, _T_7689) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7691 = or(_T_7690, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7692 = bits(_T_7691, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7693 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7692 : @[Reg.scala 28:19] + _T_7693 <= _T_7683 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][76] <= _T_7693 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7694 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7695 = eq(_T_7694, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7696 = and(ic_valid_ff, _T_7695) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7697 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7698 = and(_T_7696, _T_7697) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7699 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04d")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7700 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7701 = and(_T_7699, _T_7700) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7702 = eq(perr_ic_index_ff, UInt<7>("h04d")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7703 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7704 = and(_T_7702, _T_7703) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7705 = or(_T_7701, _T_7704) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7706 = or(_T_7705, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7707 = bits(_T_7706, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7708 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7707 : @[Reg.scala 28:19] + _T_7708 <= _T_7698 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][77] <= _T_7708 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7709 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7710 = eq(_T_7709, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7711 = and(ic_valid_ff, _T_7710) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7712 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7713 = and(_T_7711, _T_7712) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7714 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04e")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7715 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7716 = and(_T_7714, _T_7715) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7717 = eq(perr_ic_index_ff, UInt<7>("h04e")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7718 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7719 = and(_T_7717, _T_7718) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7720 = or(_T_7716, _T_7719) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7721 = or(_T_7720, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7722 = bits(_T_7721, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7723 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7722 : @[Reg.scala 28:19] + _T_7723 <= _T_7713 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][78] <= _T_7723 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7724 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7725 = eq(_T_7724, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7726 = and(ic_valid_ff, _T_7725) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7727 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7728 = and(_T_7726, _T_7727) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7729 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04f")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7730 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7731 = and(_T_7729, _T_7730) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7732 = eq(perr_ic_index_ff, UInt<7>("h04f")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7733 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7734 = and(_T_7732, _T_7733) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7735 = or(_T_7731, _T_7734) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7736 = or(_T_7735, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7737 = bits(_T_7736, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7738 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7737 : @[Reg.scala 28:19] + _T_7738 <= _T_7728 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][79] <= _T_7738 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7739 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7740 = eq(_T_7739, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7741 = and(ic_valid_ff, _T_7740) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7742 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7743 = and(_T_7741, _T_7742) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7744 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h050")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7745 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7746 = and(_T_7744, _T_7745) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7747 = eq(perr_ic_index_ff, UInt<7>("h050")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7748 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7749 = and(_T_7747, _T_7748) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7750 = or(_T_7746, _T_7749) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7751 = or(_T_7750, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7752 = bits(_T_7751, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7753 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7752 : @[Reg.scala 28:19] + _T_7753 <= _T_7743 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][80] <= _T_7753 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7754 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7755 = eq(_T_7754, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7756 = and(ic_valid_ff, _T_7755) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7757 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7758 = and(_T_7756, _T_7757) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7759 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h051")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7760 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7761 = and(_T_7759, _T_7760) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7762 = eq(perr_ic_index_ff, UInt<7>("h051")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7763 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7764 = and(_T_7762, _T_7763) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7765 = or(_T_7761, _T_7764) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7766 = or(_T_7765, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7767 = bits(_T_7766, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7768 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7767 : @[Reg.scala 28:19] + _T_7768 <= _T_7758 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][81] <= _T_7768 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7769 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7770 = eq(_T_7769, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7771 = and(ic_valid_ff, _T_7770) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7772 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7773 = and(_T_7771, _T_7772) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7774 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h052")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7775 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7776 = and(_T_7774, _T_7775) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7777 = eq(perr_ic_index_ff, UInt<7>("h052")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7778 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7779 = and(_T_7777, _T_7778) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7780 = or(_T_7776, _T_7779) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7781 = or(_T_7780, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7782 = bits(_T_7781, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7783 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7782 : @[Reg.scala 28:19] + _T_7783 <= _T_7773 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][82] <= _T_7783 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7784 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7785 = eq(_T_7784, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7786 = and(ic_valid_ff, _T_7785) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7787 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7788 = and(_T_7786, _T_7787) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7789 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h053")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7790 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7791 = and(_T_7789, _T_7790) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7792 = eq(perr_ic_index_ff, UInt<7>("h053")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7793 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7794 = and(_T_7792, _T_7793) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7795 = or(_T_7791, _T_7794) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7796 = or(_T_7795, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7797 = bits(_T_7796, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7798 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7797 : @[Reg.scala 28:19] + _T_7798 <= _T_7788 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][83] <= _T_7798 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7799 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7800 = eq(_T_7799, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7801 = and(ic_valid_ff, _T_7800) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7802 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7803 = and(_T_7801, _T_7802) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7804 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h054")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7805 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7806 = and(_T_7804, _T_7805) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7807 = eq(perr_ic_index_ff, UInt<7>("h054")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7808 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7809 = and(_T_7807, _T_7808) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7810 = or(_T_7806, _T_7809) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7811 = or(_T_7810, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7812 = bits(_T_7811, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7813 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7812 : @[Reg.scala 28:19] + _T_7813 <= _T_7803 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][84] <= _T_7813 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7814 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7815 = eq(_T_7814, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7816 = and(ic_valid_ff, _T_7815) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7817 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7818 = and(_T_7816, _T_7817) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7819 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h055")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7820 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7821 = and(_T_7819, _T_7820) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7822 = eq(perr_ic_index_ff, UInt<7>("h055")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7823 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7824 = and(_T_7822, _T_7823) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7825 = or(_T_7821, _T_7824) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7826 = or(_T_7825, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7827 = bits(_T_7826, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7828 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7827 : @[Reg.scala 28:19] + _T_7828 <= _T_7818 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][85] <= _T_7828 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7829 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7830 = eq(_T_7829, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7831 = and(ic_valid_ff, _T_7830) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7832 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7833 = and(_T_7831, _T_7832) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7834 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h056")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7835 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7836 = and(_T_7834, _T_7835) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7837 = eq(perr_ic_index_ff, UInt<7>("h056")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7838 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7839 = and(_T_7837, _T_7838) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7840 = or(_T_7836, _T_7839) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7841 = or(_T_7840, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7842 = bits(_T_7841, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7843 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7842 : @[Reg.scala 28:19] + _T_7843 <= _T_7833 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][86] <= _T_7843 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7844 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7845 = eq(_T_7844, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7846 = and(ic_valid_ff, _T_7845) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7847 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7848 = and(_T_7846, _T_7847) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7849 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h057")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7850 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7851 = and(_T_7849, _T_7850) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7852 = eq(perr_ic_index_ff, UInt<7>("h057")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7853 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7854 = and(_T_7852, _T_7853) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7855 = or(_T_7851, _T_7854) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7856 = or(_T_7855, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7857 = bits(_T_7856, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7858 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7857 : @[Reg.scala 28:19] + _T_7858 <= _T_7848 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][87] <= _T_7858 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7859 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7860 = eq(_T_7859, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7861 = and(ic_valid_ff, _T_7860) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7862 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7863 = and(_T_7861, _T_7862) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7864 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h058")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7865 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7866 = and(_T_7864, _T_7865) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7867 = eq(perr_ic_index_ff, UInt<7>("h058")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7868 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7869 = and(_T_7867, _T_7868) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7870 = or(_T_7866, _T_7869) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7871 = or(_T_7870, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7872 = bits(_T_7871, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7873 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7872 : @[Reg.scala 28:19] + _T_7873 <= _T_7863 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][88] <= _T_7873 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7874 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7875 = eq(_T_7874, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7876 = and(ic_valid_ff, _T_7875) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7877 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7878 = and(_T_7876, _T_7877) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7879 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h059")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7880 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7881 = and(_T_7879, _T_7880) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7882 = eq(perr_ic_index_ff, UInt<7>("h059")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7883 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7884 = and(_T_7882, _T_7883) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7885 = or(_T_7881, _T_7884) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7886 = or(_T_7885, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7887 = bits(_T_7886, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7888 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7887 : @[Reg.scala 28:19] + _T_7888 <= _T_7878 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][89] <= _T_7888 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7889 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7890 = eq(_T_7889, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7891 = and(ic_valid_ff, _T_7890) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7892 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7893 = and(_T_7891, _T_7892) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7894 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05a")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7895 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7896 = and(_T_7894, _T_7895) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7897 = eq(perr_ic_index_ff, UInt<7>("h05a")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7898 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7899 = and(_T_7897, _T_7898) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7900 = or(_T_7896, _T_7899) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7901 = or(_T_7900, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7902 = bits(_T_7901, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7903 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7902 : @[Reg.scala 28:19] + _T_7903 <= _T_7893 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][90] <= _T_7903 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7904 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7905 = eq(_T_7904, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7906 = and(ic_valid_ff, _T_7905) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7907 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7908 = and(_T_7906, _T_7907) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7909 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05b")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7910 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7911 = and(_T_7909, _T_7910) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7912 = eq(perr_ic_index_ff, UInt<7>("h05b")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7913 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7914 = and(_T_7912, _T_7913) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7915 = or(_T_7911, _T_7914) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7916 = or(_T_7915, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7917 = bits(_T_7916, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7918 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7917 : @[Reg.scala 28:19] + _T_7918 <= _T_7908 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][91] <= _T_7918 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7919 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7920 = eq(_T_7919, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7921 = and(ic_valid_ff, _T_7920) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7922 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7923 = and(_T_7921, _T_7922) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7924 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05c")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7925 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7926 = and(_T_7924, _T_7925) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7927 = eq(perr_ic_index_ff, UInt<7>("h05c")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7928 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7929 = and(_T_7927, _T_7928) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7930 = or(_T_7926, _T_7929) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7931 = or(_T_7930, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7932 = bits(_T_7931, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7933 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7932 : @[Reg.scala 28:19] + _T_7933 <= _T_7923 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][92] <= _T_7933 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7934 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7935 = eq(_T_7934, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7936 = and(ic_valid_ff, _T_7935) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7937 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7938 = and(_T_7936, _T_7937) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7939 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05d")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7940 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7941 = and(_T_7939, _T_7940) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7942 = eq(perr_ic_index_ff, UInt<7>("h05d")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7943 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7944 = and(_T_7942, _T_7943) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7945 = or(_T_7941, _T_7944) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7946 = or(_T_7945, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7947 = bits(_T_7946, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7948 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7947 : @[Reg.scala 28:19] + _T_7948 <= _T_7938 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][93] <= _T_7948 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7949 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7950 = eq(_T_7949, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7951 = and(ic_valid_ff, _T_7950) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7952 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7953 = and(_T_7951, _T_7952) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7954 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05e")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7955 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7956 = and(_T_7954, _T_7955) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7957 = eq(perr_ic_index_ff, UInt<7>("h05e")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7958 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7959 = and(_T_7957, _T_7958) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7960 = or(_T_7956, _T_7959) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7961 = or(_T_7960, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7962 = bits(_T_7961, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7963 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7962 : @[Reg.scala 28:19] + _T_7963 <= _T_7953 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][94] <= _T_7963 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7964 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7965 = eq(_T_7964, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7966 = and(ic_valid_ff, _T_7965) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7967 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7968 = and(_T_7966, _T_7967) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7969 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05f")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7970 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7971 = and(_T_7969, _T_7970) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7972 = eq(perr_ic_index_ff, UInt<7>("h05f")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7973 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7974 = and(_T_7972, _T_7973) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7975 = or(_T_7971, _T_7974) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7976 = or(_T_7975, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7977 = bits(_T_7976, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7978 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7977 : @[Reg.scala 28:19] + _T_7978 <= _T_7968 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][95] <= _T_7978 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7979 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7980 = eq(_T_7979, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7981 = and(ic_valid_ff, _T_7980) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7982 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7983 = and(_T_7981, _T_7982) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7984 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h060")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_7985 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_7986 = and(_T_7984, _T_7985) @[el2_ifu_mem_ctl.scala 761:55] + node _T_7987 = eq(perr_ic_index_ff, UInt<7>("h060")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_7988 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_7989 = and(_T_7987, _T_7988) @[el2_ifu_mem_ctl.scala 761:120] + node _T_7990 = or(_T_7986, _T_7989) @[el2_ifu_mem_ctl.scala 761:77] + node _T_7991 = or(_T_7990, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_7992 = bits(_T_7991, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_7993 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7992 : @[Reg.scala 28:19] + _T_7993 <= _T_7983 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][96] <= _T_7993 @[el2_ifu_mem_ctl.scala 760:39] + node _T_7994 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_7995 = eq(_T_7994, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_7996 = and(ic_valid_ff, _T_7995) @[el2_ifu_mem_ctl.scala 760:95] + node _T_7997 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_7998 = and(_T_7996, _T_7997) @[el2_ifu_mem_ctl.scala 760:120] + node _T_7999 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h061")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8000 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8001 = and(_T_7999, _T_8000) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8002 = eq(perr_ic_index_ff, UInt<7>("h061")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8003 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8004 = and(_T_8002, _T_8003) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8005 = or(_T_8001, _T_8004) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8006 = or(_T_8005, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8007 = bits(_T_8006, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8008 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8007 : @[Reg.scala 28:19] + _T_8008 <= _T_7998 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][97] <= _T_8008 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8009 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8010 = eq(_T_8009, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8011 = and(ic_valid_ff, _T_8010) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8012 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8013 = and(_T_8011, _T_8012) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8014 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h062")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8015 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8016 = and(_T_8014, _T_8015) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8017 = eq(perr_ic_index_ff, UInt<7>("h062")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8018 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8019 = and(_T_8017, _T_8018) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8020 = or(_T_8016, _T_8019) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8021 = or(_T_8020, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8022 = bits(_T_8021, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8023 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8022 : @[Reg.scala 28:19] + _T_8023 <= _T_8013 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][98] <= _T_8023 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8024 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8025 = eq(_T_8024, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8026 = and(ic_valid_ff, _T_8025) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8027 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8028 = and(_T_8026, _T_8027) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8029 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h063")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8030 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8031 = and(_T_8029, _T_8030) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8032 = eq(perr_ic_index_ff, UInt<7>("h063")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8033 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8034 = and(_T_8032, _T_8033) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8035 = or(_T_8031, _T_8034) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8036 = or(_T_8035, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8037 = bits(_T_8036, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8038 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8037 : @[Reg.scala 28:19] + _T_8038 <= _T_8028 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][99] <= _T_8038 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8039 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8040 = eq(_T_8039, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8041 = and(ic_valid_ff, _T_8040) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8042 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8043 = and(_T_8041, _T_8042) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8044 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h064")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8045 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8046 = and(_T_8044, _T_8045) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8047 = eq(perr_ic_index_ff, UInt<7>("h064")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8048 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8049 = and(_T_8047, _T_8048) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8050 = or(_T_8046, _T_8049) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8051 = or(_T_8050, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8052 = bits(_T_8051, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8053 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8052 : @[Reg.scala 28:19] + _T_8053 <= _T_8043 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][100] <= _T_8053 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8054 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8055 = eq(_T_8054, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8056 = and(ic_valid_ff, _T_8055) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8057 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8058 = and(_T_8056, _T_8057) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8059 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h065")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8060 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8061 = and(_T_8059, _T_8060) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8062 = eq(perr_ic_index_ff, UInt<7>("h065")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8063 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8064 = and(_T_8062, _T_8063) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8065 = or(_T_8061, _T_8064) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8066 = or(_T_8065, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8067 = bits(_T_8066, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8068 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8067 : @[Reg.scala 28:19] + _T_8068 <= _T_8058 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][101] <= _T_8068 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8069 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8070 = eq(_T_8069, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8071 = and(ic_valid_ff, _T_8070) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8072 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8073 = and(_T_8071, _T_8072) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8074 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h066")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8075 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8076 = and(_T_8074, _T_8075) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8077 = eq(perr_ic_index_ff, UInt<7>("h066")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8078 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8079 = and(_T_8077, _T_8078) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8080 = or(_T_8076, _T_8079) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8081 = or(_T_8080, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8082 = bits(_T_8081, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8083 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8082 : @[Reg.scala 28:19] + _T_8083 <= _T_8073 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][102] <= _T_8083 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8084 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8085 = eq(_T_8084, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8086 = and(ic_valid_ff, _T_8085) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8087 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8088 = and(_T_8086, _T_8087) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8089 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h067")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8090 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8091 = and(_T_8089, _T_8090) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8092 = eq(perr_ic_index_ff, UInt<7>("h067")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8093 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8094 = and(_T_8092, _T_8093) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8095 = or(_T_8091, _T_8094) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8096 = or(_T_8095, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8097 = bits(_T_8096, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8098 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8097 : @[Reg.scala 28:19] + _T_8098 <= _T_8088 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][103] <= _T_8098 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8099 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8100 = eq(_T_8099, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8101 = and(ic_valid_ff, _T_8100) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8102 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8103 = and(_T_8101, _T_8102) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8104 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h068")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8105 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8106 = and(_T_8104, _T_8105) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8107 = eq(perr_ic_index_ff, UInt<7>("h068")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8108 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8109 = and(_T_8107, _T_8108) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8110 = or(_T_8106, _T_8109) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8111 = or(_T_8110, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8112 = bits(_T_8111, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8113 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8112 : @[Reg.scala 28:19] + _T_8113 <= _T_8103 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][104] <= _T_8113 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8114 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8115 = eq(_T_8114, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8116 = and(ic_valid_ff, _T_8115) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8117 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8118 = and(_T_8116, _T_8117) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8119 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h069")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8120 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8121 = and(_T_8119, _T_8120) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8122 = eq(perr_ic_index_ff, UInt<7>("h069")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8123 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8124 = and(_T_8122, _T_8123) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8125 = or(_T_8121, _T_8124) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8126 = or(_T_8125, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8127 = bits(_T_8126, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8128 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8127 : @[Reg.scala 28:19] + _T_8128 <= _T_8118 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][105] <= _T_8128 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8129 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8130 = eq(_T_8129, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8131 = and(ic_valid_ff, _T_8130) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8132 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8133 = and(_T_8131, _T_8132) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8134 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06a")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8135 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8136 = and(_T_8134, _T_8135) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8137 = eq(perr_ic_index_ff, UInt<7>("h06a")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8138 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8139 = and(_T_8137, _T_8138) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8140 = or(_T_8136, _T_8139) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8141 = or(_T_8140, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8142 = bits(_T_8141, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8143 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8142 : @[Reg.scala 28:19] + _T_8143 <= _T_8133 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][106] <= _T_8143 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8144 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8145 = eq(_T_8144, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8146 = and(ic_valid_ff, _T_8145) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8147 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8148 = and(_T_8146, _T_8147) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8149 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06b")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8150 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8151 = and(_T_8149, _T_8150) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8152 = eq(perr_ic_index_ff, UInt<7>("h06b")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8153 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8154 = and(_T_8152, _T_8153) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8155 = or(_T_8151, _T_8154) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8156 = or(_T_8155, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8157 = bits(_T_8156, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8158 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8157 : @[Reg.scala 28:19] + _T_8158 <= _T_8148 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][107] <= _T_8158 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8159 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8160 = eq(_T_8159, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8161 = and(ic_valid_ff, _T_8160) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8162 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8163 = and(_T_8161, _T_8162) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8164 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06c")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8165 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8166 = and(_T_8164, _T_8165) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8167 = eq(perr_ic_index_ff, UInt<7>("h06c")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8168 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8169 = and(_T_8167, _T_8168) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8170 = or(_T_8166, _T_8169) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8171 = or(_T_8170, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8172 = bits(_T_8171, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8173 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8172 : @[Reg.scala 28:19] + _T_8173 <= _T_8163 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][108] <= _T_8173 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8174 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8175 = eq(_T_8174, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8176 = and(ic_valid_ff, _T_8175) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8177 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8178 = and(_T_8176, _T_8177) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8179 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06d")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8180 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8181 = and(_T_8179, _T_8180) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8182 = eq(perr_ic_index_ff, UInt<7>("h06d")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8183 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8184 = and(_T_8182, _T_8183) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8185 = or(_T_8181, _T_8184) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8186 = or(_T_8185, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8187 = bits(_T_8186, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8188 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8187 : @[Reg.scala 28:19] + _T_8188 <= _T_8178 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][109] <= _T_8188 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8189 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8190 = eq(_T_8189, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8191 = and(ic_valid_ff, _T_8190) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8192 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8193 = and(_T_8191, _T_8192) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8194 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06e")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8195 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8196 = and(_T_8194, _T_8195) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8197 = eq(perr_ic_index_ff, UInt<7>("h06e")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8198 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8199 = and(_T_8197, _T_8198) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8200 = or(_T_8196, _T_8199) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8201 = or(_T_8200, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8202 = bits(_T_8201, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8203 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8202 : @[Reg.scala 28:19] + _T_8203 <= _T_8193 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][110] <= _T_8203 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8204 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8205 = eq(_T_8204, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8206 = and(ic_valid_ff, _T_8205) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8207 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8208 = and(_T_8206, _T_8207) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8209 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06f")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8210 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8211 = and(_T_8209, _T_8210) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8212 = eq(perr_ic_index_ff, UInt<7>("h06f")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8213 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8214 = and(_T_8212, _T_8213) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8215 = or(_T_8211, _T_8214) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8216 = or(_T_8215, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8217 = bits(_T_8216, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8218 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8217 : @[Reg.scala 28:19] + _T_8218 <= _T_8208 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][111] <= _T_8218 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8219 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8220 = eq(_T_8219, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8221 = and(ic_valid_ff, _T_8220) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8222 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8223 = and(_T_8221, _T_8222) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8224 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h070")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8225 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8226 = and(_T_8224, _T_8225) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8227 = eq(perr_ic_index_ff, UInt<7>("h070")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8228 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8229 = and(_T_8227, _T_8228) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8230 = or(_T_8226, _T_8229) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8231 = or(_T_8230, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8232 = bits(_T_8231, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8233 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8232 : @[Reg.scala 28:19] + _T_8233 <= _T_8223 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][112] <= _T_8233 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8234 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8235 = eq(_T_8234, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8236 = and(ic_valid_ff, _T_8235) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8237 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8238 = and(_T_8236, _T_8237) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8239 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h071")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8240 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8241 = and(_T_8239, _T_8240) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8242 = eq(perr_ic_index_ff, UInt<7>("h071")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8243 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8244 = and(_T_8242, _T_8243) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8245 = or(_T_8241, _T_8244) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8246 = or(_T_8245, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8247 = bits(_T_8246, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8248 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8247 : @[Reg.scala 28:19] + _T_8248 <= _T_8238 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][113] <= _T_8248 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8249 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8250 = eq(_T_8249, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8251 = and(ic_valid_ff, _T_8250) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8252 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8253 = and(_T_8251, _T_8252) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8254 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h072")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8255 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8256 = and(_T_8254, _T_8255) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8257 = eq(perr_ic_index_ff, UInt<7>("h072")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8258 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8259 = and(_T_8257, _T_8258) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8260 = or(_T_8256, _T_8259) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8261 = or(_T_8260, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8262 = bits(_T_8261, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8263 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8262 : @[Reg.scala 28:19] + _T_8263 <= _T_8253 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][114] <= _T_8263 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8264 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8265 = eq(_T_8264, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8266 = and(ic_valid_ff, _T_8265) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8267 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8268 = and(_T_8266, _T_8267) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8269 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h073")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8270 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8271 = and(_T_8269, _T_8270) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8272 = eq(perr_ic_index_ff, UInt<7>("h073")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8273 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8274 = and(_T_8272, _T_8273) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8275 = or(_T_8271, _T_8274) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8276 = or(_T_8275, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8277 = bits(_T_8276, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8278 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8277 : @[Reg.scala 28:19] + _T_8278 <= _T_8268 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][115] <= _T_8278 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8279 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8280 = eq(_T_8279, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8281 = and(ic_valid_ff, _T_8280) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8282 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8283 = and(_T_8281, _T_8282) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8284 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h074")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8285 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8286 = and(_T_8284, _T_8285) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8287 = eq(perr_ic_index_ff, UInt<7>("h074")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8288 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8289 = and(_T_8287, _T_8288) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8290 = or(_T_8286, _T_8289) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8291 = or(_T_8290, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8292 = bits(_T_8291, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8293 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8292 : @[Reg.scala 28:19] + _T_8293 <= _T_8283 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][116] <= _T_8293 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8294 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8295 = eq(_T_8294, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8296 = and(ic_valid_ff, _T_8295) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8297 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8298 = and(_T_8296, _T_8297) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8299 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h075")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8300 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8301 = and(_T_8299, _T_8300) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8302 = eq(perr_ic_index_ff, UInt<7>("h075")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8303 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8304 = and(_T_8302, _T_8303) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8305 = or(_T_8301, _T_8304) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8306 = or(_T_8305, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8307 = bits(_T_8306, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8308 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8307 : @[Reg.scala 28:19] + _T_8308 <= _T_8298 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][117] <= _T_8308 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8309 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8310 = eq(_T_8309, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8311 = and(ic_valid_ff, _T_8310) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8312 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8313 = and(_T_8311, _T_8312) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8314 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h076")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8315 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8316 = and(_T_8314, _T_8315) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8317 = eq(perr_ic_index_ff, UInt<7>("h076")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8318 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8319 = and(_T_8317, _T_8318) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8320 = or(_T_8316, _T_8319) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8321 = or(_T_8320, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8322 = bits(_T_8321, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8323 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8322 : @[Reg.scala 28:19] + _T_8323 <= _T_8313 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][118] <= _T_8323 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8324 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8325 = eq(_T_8324, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8326 = and(ic_valid_ff, _T_8325) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8327 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8328 = and(_T_8326, _T_8327) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8329 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h077")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8330 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8331 = and(_T_8329, _T_8330) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8332 = eq(perr_ic_index_ff, UInt<7>("h077")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8333 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8334 = and(_T_8332, _T_8333) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8335 = or(_T_8331, _T_8334) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8336 = or(_T_8335, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8337 = bits(_T_8336, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8338 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8337 : @[Reg.scala 28:19] + _T_8338 <= _T_8328 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][119] <= _T_8338 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8339 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8340 = eq(_T_8339, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8341 = and(ic_valid_ff, _T_8340) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8342 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8343 = and(_T_8341, _T_8342) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8344 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h078")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8345 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8346 = and(_T_8344, _T_8345) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8347 = eq(perr_ic_index_ff, UInt<7>("h078")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8348 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8349 = and(_T_8347, _T_8348) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8350 = or(_T_8346, _T_8349) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8351 = or(_T_8350, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8352 = bits(_T_8351, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8353 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8352 : @[Reg.scala 28:19] + _T_8353 <= _T_8343 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][120] <= _T_8353 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8354 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8355 = eq(_T_8354, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8356 = and(ic_valid_ff, _T_8355) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8357 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8358 = and(_T_8356, _T_8357) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8359 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h079")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8360 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8361 = and(_T_8359, _T_8360) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8362 = eq(perr_ic_index_ff, UInt<7>("h079")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8363 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8364 = and(_T_8362, _T_8363) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8365 = or(_T_8361, _T_8364) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8366 = or(_T_8365, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8367 = bits(_T_8366, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8368 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8367 : @[Reg.scala 28:19] + _T_8368 <= _T_8358 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][121] <= _T_8368 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8369 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8370 = eq(_T_8369, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8371 = and(ic_valid_ff, _T_8370) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8372 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8373 = and(_T_8371, _T_8372) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8374 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07a")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8375 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8376 = and(_T_8374, _T_8375) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8377 = eq(perr_ic_index_ff, UInt<7>("h07a")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8378 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8379 = and(_T_8377, _T_8378) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8380 = or(_T_8376, _T_8379) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8381 = or(_T_8380, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8382 = bits(_T_8381, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8383 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8382 : @[Reg.scala 28:19] + _T_8383 <= _T_8373 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][122] <= _T_8383 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8384 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8385 = eq(_T_8384, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8386 = and(ic_valid_ff, _T_8385) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8387 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8388 = and(_T_8386, _T_8387) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8389 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07b")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8390 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8391 = and(_T_8389, _T_8390) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8392 = eq(perr_ic_index_ff, UInt<7>("h07b")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8393 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8394 = and(_T_8392, _T_8393) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8395 = or(_T_8391, _T_8394) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8396 = or(_T_8395, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8397 = bits(_T_8396, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8398 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8397 : @[Reg.scala 28:19] + _T_8398 <= _T_8388 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][123] <= _T_8398 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8399 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8400 = eq(_T_8399, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8401 = and(ic_valid_ff, _T_8400) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8402 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8403 = and(_T_8401, _T_8402) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8404 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07c")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8405 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8406 = and(_T_8404, _T_8405) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8407 = eq(perr_ic_index_ff, UInt<7>("h07c")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8408 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8409 = and(_T_8407, _T_8408) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8410 = or(_T_8406, _T_8409) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8411 = or(_T_8410, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8412 = bits(_T_8411, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8413 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8412 : @[Reg.scala 28:19] + _T_8413 <= _T_8403 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][124] <= _T_8413 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8414 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8415 = eq(_T_8414, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8416 = and(ic_valid_ff, _T_8415) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8417 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8418 = and(_T_8416, _T_8417) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8419 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07d")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8420 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8421 = and(_T_8419, _T_8420) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8422 = eq(perr_ic_index_ff, UInt<7>("h07d")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8423 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8424 = and(_T_8422, _T_8423) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8425 = or(_T_8421, _T_8424) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8426 = or(_T_8425, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8427 = bits(_T_8426, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8428 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8427 : @[Reg.scala 28:19] + _T_8428 <= _T_8418 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][125] <= _T_8428 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8429 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8430 = eq(_T_8429, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8431 = and(ic_valid_ff, _T_8430) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8432 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8433 = and(_T_8431, _T_8432) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8434 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07e")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8435 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8436 = and(_T_8434, _T_8435) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8437 = eq(perr_ic_index_ff, UInt<7>("h07e")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8438 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8439 = and(_T_8437, _T_8438) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8440 = or(_T_8436, _T_8439) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8441 = or(_T_8440, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8442 = bits(_T_8441, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8443 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8442 : @[Reg.scala 28:19] + _T_8443 <= _T_8433 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][126] <= _T_8443 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8444 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8445 = eq(_T_8444, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8446 = and(ic_valid_ff, _T_8445) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8447 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8448 = and(_T_8446, _T_8447) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8449 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07f")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8450 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8451 = and(_T_8449, _T_8450) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8452 = eq(perr_ic_index_ff, UInt<7>("h07f")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8453 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8454 = and(_T_8452, _T_8453) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8455 = or(_T_8451, _T_8454) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8456 = or(_T_8455, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8457 = bits(_T_8456, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8458 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8457 : @[Reg.scala 28:19] + _T_8458 <= _T_8448 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[0][127] <= _T_8458 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8459 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8460 = eq(_T_8459, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8461 = and(ic_valid_ff, _T_8460) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8462 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8463 = and(_T_8461, _T_8462) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8464 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h060")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8465 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8466 = and(_T_8464, _T_8465) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8467 = eq(perr_ic_index_ff, UInt<7>("h060")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8468 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8469 = and(_T_8467, _T_8468) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8470 = or(_T_8466, _T_8469) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8471 = or(_T_8470, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8472 = bits(_T_8471, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8473 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8472 : @[Reg.scala 28:19] + _T_8473 <= _T_8463 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][96] <= _T_8473 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8474 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8475 = eq(_T_8474, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8476 = and(ic_valid_ff, _T_8475) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8477 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8478 = and(_T_8476, _T_8477) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8479 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h061")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8480 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8481 = and(_T_8479, _T_8480) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8482 = eq(perr_ic_index_ff, UInt<7>("h061")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8483 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8484 = and(_T_8482, _T_8483) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8485 = or(_T_8481, _T_8484) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8486 = or(_T_8485, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8487 = bits(_T_8486, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8488 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8487 : @[Reg.scala 28:19] + _T_8488 <= _T_8478 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][97] <= _T_8488 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8489 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8490 = eq(_T_8489, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8491 = and(ic_valid_ff, _T_8490) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8492 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8493 = and(_T_8491, _T_8492) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8494 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h062")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8495 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8496 = and(_T_8494, _T_8495) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8497 = eq(perr_ic_index_ff, UInt<7>("h062")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8498 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8499 = and(_T_8497, _T_8498) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8500 = or(_T_8496, _T_8499) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8501 = or(_T_8500, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8502 = bits(_T_8501, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8503 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8502 : @[Reg.scala 28:19] + _T_8503 <= _T_8493 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][98] <= _T_8503 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8504 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8505 = eq(_T_8504, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8506 = and(ic_valid_ff, _T_8505) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8507 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8508 = and(_T_8506, _T_8507) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8509 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h063")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8510 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8511 = and(_T_8509, _T_8510) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8512 = eq(perr_ic_index_ff, UInt<7>("h063")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8513 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8514 = and(_T_8512, _T_8513) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8515 = or(_T_8511, _T_8514) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8516 = or(_T_8515, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8517 = bits(_T_8516, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8518 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8517 : @[Reg.scala 28:19] + _T_8518 <= _T_8508 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][99] <= _T_8518 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8519 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8520 = eq(_T_8519, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8521 = and(ic_valid_ff, _T_8520) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8522 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8523 = and(_T_8521, _T_8522) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8524 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h064")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8525 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8526 = and(_T_8524, _T_8525) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8527 = eq(perr_ic_index_ff, UInt<7>("h064")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8528 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8529 = and(_T_8527, _T_8528) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8530 = or(_T_8526, _T_8529) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8531 = or(_T_8530, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8532 = bits(_T_8531, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8533 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8532 : @[Reg.scala 28:19] + _T_8533 <= _T_8523 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][100] <= _T_8533 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8534 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8535 = eq(_T_8534, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8536 = and(ic_valid_ff, _T_8535) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8537 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8538 = and(_T_8536, _T_8537) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8539 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h065")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8540 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8541 = and(_T_8539, _T_8540) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8542 = eq(perr_ic_index_ff, UInt<7>("h065")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8543 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8544 = and(_T_8542, _T_8543) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8545 = or(_T_8541, _T_8544) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8546 = or(_T_8545, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8547 = bits(_T_8546, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8548 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8547 : @[Reg.scala 28:19] + _T_8548 <= _T_8538 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][101] <= _T_8548 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8549 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8550 = eq(_T_8549, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8551 = and(ic_valid_ff, _T_8550) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8552 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8553 = and(_T_8551, _T_8552) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8554 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h066")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8555 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8556 = and(_T_8554, _T_8555) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8557 = eq(perr_ic_index_ff, UInt<7>("h066")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8558 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8559 = and(_T_8557, _T_8558) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8560 = or(_T_8556, _T_8559) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8561 = or(_T_8560, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8562 = bits(_T_8561, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8563 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8562 : @[Reg.scala 28:19] + _T_8563 <= _T_8553 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][102] <= _T_8563 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8564 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8565 = eq(_T_8564, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8566 = and(ic_valid_ff, _T_8565) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8567 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8568 = and(_T_8566, _T_8567) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8569 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h067")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8570 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8571 = and(_T_8569, _T_8570) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8572 = eq(perr_ic_index_ff, UInt<7>("h067")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8573 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8574 = and(_T_8572, _T_8573) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8575 = or(_T_8571, _T_8574) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8576 = or(_T_8575, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8577 = bits(_T_8576, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8578 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8577 : @[Reg.scala 28:19] + _T_8578 <= _T_8568 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][103] <= _T_8578 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8579 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8580 = eq(_T_8579, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8581 = and(ic_valid_ff, _T_8580) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8582 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8583 = and(_T_8581, _T_8582) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8584 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h068")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8585 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8586 = and(_T_8584, _T_8585) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8587 = eq(perr_ic_index_ff, UInt<7>("h068")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8588 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8589 = and(_T_8587, _T_8588) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8590 = or(_T_8586, _T_8589) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8591 = or(_T_8590, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8592 = bits(_T_8591, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8593 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8592 : @[Reg.scala 28:19] + _T_8593 <= _T_8583 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][104] <= _T_8593 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8594 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8595 = eq(_T_8594, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8596 = and(ic_valid_ff, _T_8595) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8597 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8598 = and(_T_8596, _T_8597) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8599 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h069")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8600 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8601 = and(_T_8599, _T_8600) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8602 = eq(perr_ic_index_ff, UInt<7>("h069")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8603 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8604 = and(_T_8602, _T_8603) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8605 = or(_T_8601, _T_8604) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8606 = or(_T_8605, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8607 = bits(_T_8606, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8608 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8607 : @[Reg.scala 28:19] + _T_8608 <= _T_8598 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][105] <= _T_8608 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8609 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8610 = eq(_T_8609, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8611 = and(ic_valid_ff, _T_8610) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8612 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8613 = and(_T_8611, _T_8612) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8614 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06a")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8615 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8616 = and(_T_8614, _T_8615) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8617 = eq(perr_ic_index_ff, UInt<7>("h06a")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8618 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8619 = and(_T_8617, _T_8618) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8620 = or(_T_8616, _T_8619) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8621 = or(_T_8620, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8622 = bits(_T_8621, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8623 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8622 : @[Reg.scala 28:19] + _T_8623 <= _T_8613 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][106] <= _T_8623 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8624 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8625 = eq(_T_8624, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8626 = and(ic_valid_ff, _T_8625) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8627 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8628 = and(_T_8626, _T_8627) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8629 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06b")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8630 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8631 = and(_T_8629, _T_8630) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8632 = eq(perr_ic_index_ff, UInt<7>("h06b")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8633 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8634 = and(_T_8632, _T_8633) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8635 = or(_T_8631, _T_8634) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8636 = or(_T_8635, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8637 = bits(_T_8636, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8638 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8637 : @[Reg.scala 28:19] + _T_8638 <= _T_8628 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][107] <= _T_8638 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8639 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8640 = eq(_T_8639, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8641 = and(ic_valid_ff, _T_8640) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8642 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8643 = and(_T_8641, _T_8642) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8644 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06c")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8645 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8646 = and(_T_8644, _T_8645) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8647 = eq(perr_ic_index_ff, UInt<7>("h06c")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8648 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8649 = and(_T_8647, _T_8648) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8650 = or(_T_8646, _T_8649) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8651 = or(_T_8650, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8652 = bits(_T_8651, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8653 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8652 : @[Reg.scala 28:19] + _T_8653 <= _T_8643 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][108] <= _T_8653 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8654 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8655 = eq(_T_8654, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8656 = and(ic_valid_ff, _T_8655) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8657 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8658 = and(_T_8656, _T_8657) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8659 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06d")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8660 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8661 = and(_T_8659, _T_8660) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8662 = eq(perr_ic_index_ff, UInt<7>("h06d")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8663 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8664 = and(_T_8662, _T_8663) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8665 = or(_T_8661, _T_8664) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8666 = or(_T_8665, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8667 = bits(_T_8666, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8668 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8667 : @[Reg.scala 28:19] + _T_8668 <= _T_8658 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][109] <= _T_8668 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8669 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8670 = eq(_T_8669, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8671 = and(ic_valid_ff, _T_8670) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8672 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8673 = and(_T_8671, _T_8672) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8674 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06e")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8675 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8676 = and(_T_8674, _T_8675) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8677 = eq(perr_ic_index_ff, UInt<7>("h06e")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8678 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8679 = and(_T_8677, _T_8678) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8680 = or(_T_8676, _T_8679) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8681 = or(_T_8680, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8682 = bits(_T_8681, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8683 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8682 : @[Reg.scala 28:19] + _T_8683 <= _T_8673 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][110] <= _T_8683 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8684 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8685 = eq(_T_8684, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8686 = and(ic_valid_ff, _T_8685) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8687 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8688 = and(_T_8686, _T_8687) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8689 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06f")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8690 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8691 = and(_T_8689, _T_8690) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8692 = eq(perr_ic_index_ff, UInt<7>("h06f")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8693 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8694 = and(_T_8692, _T_8693) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8695 = or(_T_8691, _T_8694) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8696 = or(_T_8695, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8697 = bits(_T_8696, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8698 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8697 : @[Reg.scala 28:19] + _T_8698 <= _T_8688 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][111] <= _T_8698 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8699 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8700 = eq(_T_8699, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8701 = and(ic_valid_ff, _T_8700) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8702 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8703 = and(_T_8701, _T_8702) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8704 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h070")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8705 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8706 = and(_T_8704, _T_8705) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8707 = eq(perr_ic_index_ff, UInt<7>("h070")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8708 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8709 = and(_T_8707, _T_8708) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8710 = or(_T_8706, _T_8709) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8711 = or(_T_8710, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8712 = bits(_T_8711, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8713 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8712 : @[Reg.scala 28:19] + _T_8713 <= _T_8703 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][112] <= _T_8713 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8714 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8715 = eq(_T_8714, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8716 = and(ic_valid_ff, _T_8715) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8717 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8718 = and(_T_8716, _T_8717) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8719 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h071")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8720 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8721 = and(_T_8719, _T_8720) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8722 = eq(perr_ic_index_ff, UInt<7>("h071")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8723 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8724 = and(_T_8722, _T_8723) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8725 = or(_T_8721, _T_8724) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8726 = or(_T_8725, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8727 = bits(_T_8726, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8728 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8727 : @[Reg.scala 28:19] + _T_8728 <= _T_8718 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][113] <= _T_8728 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8729 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8730 = eq(_T_8729, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8731 = and(ic_valid_ff, _T_8730) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8732 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8733 = and(_T_8731, _T_8732) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8734 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h072")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8735 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8736 = and(_T_8734, _T_8735) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8737 = eq(perr_ic_index_ff, UInt<7>("h072")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8738 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8739 = and(_T_8737, _T_8738) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8740 = or(_T_8736, _T_8739) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8741 = or(_T_8740, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8742 = bits(_T_8741, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8743 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8742 : @[Reg.scala 28:19] + _T_8743 <= _T_8733 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][114] <= _T_8743 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8744 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8745 = eq(_T_8744, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8746 = and(ic_valid_ff, _T_8745) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8747 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8748 = and(_T_8746, _T_8747) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8749 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h073")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8750 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8751 = and(_T_8749, _T_8750) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8752 = eq(perr_ic_index_ff, UInt<7>("h073")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8753 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8754 = and(_T_8752, _T_8753) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8755 = or(_T_8751, _T_8754) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8756 = or(_T_8755, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8757 = bits(_T_8756, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8758 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8757 : @[Reg.scala 28:19] + _T_8758 <= _T_8748 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][115] <= _T_8758 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8759 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8760 = eq(_T_8759, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8761 = and(ic_valid_ff, _T_8760) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8762 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8763 = and(_T_8761, _T_8762) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8764 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h074")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8765 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8766 = and(_T_8764, _T_8765) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8767 = eq(perr_ic_index_ff, UInt<7>("h074")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8768 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8769 = and(_T_8767, _T_8768) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8770 = or(_T_8766, _T_8769) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8771 = or(_T_8770, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8772 = bits(_T_8771, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8773 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8772 : @[Reg.scala 28:19] + _T_8773 <= _T_8763 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][116] <= _T_8773 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8774 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8775 = eq(_T_8774, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8776 = and(ic_valid_ff, _T_8775) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8777 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8778 = and(_T_8776, _T_8777) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8779 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h075")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8780 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8781 = and(_T_8779, _T_8780) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8782 = eq(perr_ic_index_ff, UInt<7>("h075")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8783 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8784 = and(_T_8782, _T_8783) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8785 = or(_T_8781, _T_8784) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8786 = or(_T_8785, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8787 = bits(_T_8786, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8788 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8787 : @[Reg.scala 28:19] + _T_8788 <= _T_8778 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][117] <= _T_8788 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8789 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8790 = eq(_T_8789, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8791 = and(ic_valid_ff, _T_8790) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8792 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8793 = and(_T_8791, _T_8792) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8794 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h076")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8795 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8796 = and(_T_8794, _T_8795) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8797 = eq(perr_ic_index_ff, UInt<7>("h076")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8798 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8799 = and(_T_8797, _T_8798) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8800 = or(_T_8796, _T_8799) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8801 = or(_T_8800, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8802 = bits(_T_8801, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8803 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8802 : @[Reg.scala 28:19] + _T_8803 <= _T_8793 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][118] <= _T_8803 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8804 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8805 = eq(_T_8804, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8806 = and(ic_valid_ff, _T_8805) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8807 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8808 = and(_T_8806, _T_8807) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8809 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h077")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8810 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8811 = and(_T_8809, _T_8810) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8812 = eq(perr_ic_index_ff, UInt<7>("h077")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8813 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8814 = and(_T_8812, _T_8813) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8815 = or(_T_8811, _T_8814) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8816 = or(_T_8815, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8817 = bits(_T_8816, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8818 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8817 : @[Reg.scala 28:19] + _T_8818 <= _T_8808 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][119] <= _T_8818 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8819 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8820 = eq(_T_8819, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8821 = and(ic_valid_ff, _T_8820) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8822 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8823 = and(_T_8821, _T_8822) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8824 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h078")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8825 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8826 = and(_T_8824, _T_8825) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8827 = eq(perr_ic_index_ff, UInt<7>("h078")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8828 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8829 = and(_T_8827, _T_8828) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8830 = or(_T_8826, _T_8829) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8831 = or(_T_8830, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8832 = bits(_T_8831, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8833 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8832 : @[Reg.scala 28:19] + _T_8833 <= _T_8823 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][120] <= _T_8833 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8834 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8835 = eq(_T_8834, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8836 = and(ic_valid_ff, _T_8835) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8837 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8838 = and(_T_8836, _T_8837) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8839 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h079")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8840 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8841 = and(_T_8839, _T_8840) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8842 = eq(perr_ic_index_ff, UInt<7>("h079")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8843 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8844 = and(_T_8842, _T_8843) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8845 = or(_T_8841, _T_8844) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8846 = or(_T_8845, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8847 = bits(_T_8846, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8848 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8847 : @[Reg.scala 28:19] + _T_8848 <= _T_8838 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][121] <= _T_8848 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8849 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8850 = eq(_T_8849, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8851 = and(ic_valid_ff, _T_8850) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8852 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8853 = and(_T_8851, _T_8852) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8854 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07a")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8855 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8856 = and(_T_8854, _T_8855) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8857 = eq(perr_ic_index_ff, UInt<7>("h07a")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8858 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8859 = and(_T_8857, _T_8858) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8860 = or(_T_8856, _T_8859) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8861 = or(_T_8860, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8862 = bits(_T_8861, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8863 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8862 : @[Reg.scala 28:19] + _T_8863 <= _T_8853 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][122] <= _T_8863 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8864 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8865 = eq(_T_8864, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8866 = and(ic_valid_ff, _T_8865) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8867 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8868 = and(_T_8866, _T_8867) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8869 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07b")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8870 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8871 = and(_T_8869, _T_8870) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8872 = eq(perr_ic_index_ff, UInt<7>("h07b")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8873 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8874 = and(_T_8872, _T_8873) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8875 = or(_T_8871, _T_8874) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8876 = or(_T_8875, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8877 = bits(_T_8876, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8878 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8877 : @[Reg.scala 28:19] + _T_8878 <= _T_8868 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][123] <= _T_8878 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8879 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8880 = eq(_T_8879, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8881 = and(ic_valid_ff, _T_8880) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8882 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8883 = and(_T_8881, _T_8882) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8884 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07c")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8885 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8886 = and(_T_8884, _T_8885) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8887 = eq(perr_ic_index_ff, UInt<7>("h07c")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8888 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8889 = and(_T_8887, _T_8888) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8890 = or(_T_8886, _T_8889) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8891 = or(_T_8890, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8892 = bits(_T_8891, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8893 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8892 : @[Reg.scala 28:19] + _T_8893 <= _T_8883 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][124] <= _T_8893 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8894 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8895 = eq(_T_8894, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8896 = and(ic_valid_ff, _T_8895) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8897 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8898 = and(_T_8896, _T_8897) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8899 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07d")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8900 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8901 = and(_T_8899, _T_8900) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8902 = eq(perr_ic_index_ff, UInt<7>("h07d")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8903 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8904 = and(_T_8902, _T_8903) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8905 = or(_T_8901, _T_8904) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8906 = or(_T_8905, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8907 = bits(_T_8906, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8908 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8907 : @[Reg.scala 28:19] + _T_8908 <= _T_8898 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][125] <= _T_8908 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8909 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8910 = eq(_T_8909, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8911 = and(ic_valid_ff, _T_8910) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8912 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8913 = and(_T_8911, _T_8912) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8914 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07e")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8915 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8916 = and(_T_8914, _T_8915) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8917 = eq(perr_ic_index_ff, UInt<7>("h07e")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8918 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8919 = and(_T_8917, _T_8918) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8920 = or(_T_8916, _T_8919) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8921 = or(_T_8920, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8922 = bits(_T_8921, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8923 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8922 : @[Reg.scala 28:19] + _T_8923 <= _T_8913 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][126] <= _T_8923 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8924 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 760:113] + node _T_8925 = eq(_T_8924, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:97] + node _T_8926 = and(ic_valid_ff, _T_8925) @[el2_ifu_mem_ctl.scala 760:95] + node _T_8927 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 760:122] + node _T_8928 = and(_T_8926, _T_8927) @[el2_ifu_mem_ctl.scala 760:120] + node _T_8929 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07f")) @[el2_ifu_mem_ctl.scala 761:33] + node _T_8930 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 761:72] + node _T_8931 = and(_T_8929, _T_8930) @[el2_ifu_mem_ctl.scala 761:55] + node _T_8932 = eq(perr_ic_index_ff, UInt<7>("h07f")) @[el2_ifu_mem_ctl.scala 761:98] + node _T_8933 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 761:138] + node _T_8934 = and(_T_8932, _T_8933) @[el2_ifu_mem_ctl.scala 761:120] + node _T_8935 = or(_T_8931, _T_8934) @[el2_ifu_mem_ctl.scala 761:77] + node _T_8936 = or(_T_8935, reset_all_tags) @[el2_ifu_mem_ctl.scala 761:143] + node _T_8937 = bits(_T_8936, 0, 0) @[el2_ifu_mem_ctl.scala 761:162] + reg _T_8938 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8937 : @[Reg.scala 28:19] + _T_8938 <= _T_8928 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ic_tag_valid_out[1][127] <= _T_8938 @[el2_ifu_mem_ctl.scala 760:39] + node _T_8939 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_8940 = mux(_T_8939, ic_tag_valid_out[0][0], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_8941 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_8942 = mux(_T_8941, ic_tag_valid_out[0][1], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_8943 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_8944 = mux(_T_8943, ic_tag_valid_out[0][2], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_8945 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_8946 = mux(_T_8945, ic_tag_valid_out[0][3], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_8947 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_8948 = mux(_T_8947, ic_tag_valid_out[0][4], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_8949 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_8950 = mux(_T_8949, ic_tag_valid_out[0][5], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_8951 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_8952 = mux(_T_8951, ic_tag_valid_out[0][6], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_8953 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_8954 = mux(_T_8953, ic_tag_valid_out[0][7], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_8955 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_8956 = mux(_T_8955, ic_tag_valid_out[0][8], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_8957 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_8958 = mux(_T_8957, ic_tag_valid_out[0][9], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_8959 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_8960 = mux(_T_8959, ic_tag_valid_out[0][10], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_8961 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_8962 = mux(_T_8961, ic_tag_valid_out[0][11], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_8963 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_8964 = mux(_T_8963, ic_tag_valid_out[0][12], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_8965 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_8966 = mux(_T_8965, ic_tag_valid_out[0][13], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_8967 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_8968 = mux(_T_8967, ic_tag_valid_out[0][14], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_8969 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_8970 = mux(_T_8969, ic_tag_valid_out[0][15], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_8971 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h010")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_8972 = mux(_T_8971, ic_tag_valid_out[0][16], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_8973 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h011")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_8974 = mux(_T_8973, ic_tag_valid_out[0][17], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_8975 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h012")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_8976 = mux(_T_8975, ic_tag_valid_out[0][18], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_8977 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h013")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_8978 = mux(_T_8977, ic_tag_valid_out[0][19], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_8979 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h014")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_8980 = mux(_T_8979, ic_tag_valid_out[0][20], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_8981 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h015")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_8982 = mux(_T_8981, ic_tag_valid_out[0][21], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_8983 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h016")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_8984 = mux(_T_8983, ic_tag_valid_out[0][22], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_8985 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h017")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_8986 = mux(_T_8985, ic_tag_valid_out[0][23], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_8987 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h018")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_8988 = mux(_T_8987, ic_tag_valid_out[0][24], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_8989 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h019")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_8990 = mux(_T_8989, ic_tag_valid_out[0][25], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_8991 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01a")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_8992 = mux(_T_8991, ic_tag_valid_out[0][26], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_8993 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01b")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_8994 = mux(_T_8993, ic_tag_valid_out[0][27], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_8995 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01c")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_8996 = mux(_T_8995, ic_tag_valid_out[0][28], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_8997 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01d")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_8998 = mux(_T_8997, ic_tag_valid_out[0][29], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_8999 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01e")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9000 = mux(_T_8999, ic_tag_valid_out[0][30], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9001 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01f")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9002 = mux(_T_9001, ic_tag_valid_out[0][31], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9003 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h020")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9004 = mux(_T_9003, ic_tag_valid_out[0][32], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9005 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h021")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9006 = mux(_T_9005, ic_tag_valid_out[0][33], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9007 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h022")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9008 = mux(_T_9007, ic_tag_valid_out[0][34], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9009 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h023")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9010 = mux(_T_9009, ic_tag_valid_out[0][35], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9011 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h024")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9012 = mux(_T_9011, ic_tag_valid_out[0][36], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9013 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h025")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9014 = mux(_T_9013, ic_tag_valid_out[0][37], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9015 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h026")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9016 = mux(_T_9015, ic_tag_valid_out[0][38], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9017 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h027")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9018 = mux(_T_9017, ic_tag_valid_out[0][39], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9019 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h028")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9020 = mux(_T_9019, ic_tag_valid_out[0][40], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9021 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h029")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9022 = mux(_T_9021, ic_tag_valid_out[0][41], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9023 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02a")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9024 = mux(_T_9023, ic_tag_valid_out[0][42], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9025 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02b")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9026 = mux(_T_9025, ic_tag_valid_out[0][43], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9027 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02c")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9028 = mux(_T_9027, ic_tag_valid_out[0][44], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9029 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02d")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9030 = mux(_T_9029, ic_tag_valid_out[0][45], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9031 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02e")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9032 = mux(_T_9031, ic_tag_valid_out[0][46], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9033 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02f")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9034 = mux(_T_9033, ic_tag_valid_out[0][47], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9035 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h030")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9036 = mux(_T_9035, ic_tag_valid_out[0][48], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9037 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h031")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9038 = mux(_T_9037, ic_tag_valid_out[0][49], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9039 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h032")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9040 = mux(_T_9039, ic_tag_valid_out[0][50], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9041 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h033")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9042 = mux(_T_9041, ic_tag_valid_out[0][51], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9043 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h034")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9044 = mux(_T_9043, ic_tag_valid_out[0][52], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9045 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h035")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9046 = mux(_T_9045, ic_tag_valid_out[0][53], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9047 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h036")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9048 = mux(_T_9047, ic_tag_valid_out[0][54], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9049 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h037")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9050 = mux(_T_9049, ic_tag_valid_out[0][55], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9051 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h038")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9052 = mux(_T_9051, ic_tag_valid_out[0][56], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9053 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h039")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9054 = mux(_T_9053, ic_tag_valid_out[0][57], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9055 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03a")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9056 = mux(_T_9055, ic_tag_valid_out[0][58], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9057 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03b")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9058 = mux(_T_9057, ic_tag_valid_out[0][59], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9059 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03c")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9060 = mux(_T_9059, ic_tag_valid_out[0][60], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9061 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03d")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9062 = mux(_T_9061, ic_tag_valid_out[0][61], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9063 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03e")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9064 = mux(_T_9063, ic_tag_valid_out[0][62], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9065 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03f")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9066 = mux(_T_9065, ic_tag_valid_out[0][63], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9067 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h040")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9068 = mux(_T_9067, ic_tag_valid_out[0][64], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9069 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h041")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9070 = mux(_T_9069, ic_tag_valid_out[0][65], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9071 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h042")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9072 = mux(_T_9071, ic_tag_valid_out[0][66], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9073 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h043")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9074 = mux(_T_9073, ic_tag_valid_out[0][67], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9075 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h044")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9076 = mux(_T_9075, ic_tag_valid_out[0][68], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9077 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h045")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9078 = mux(_T_9077, ic_tag_valid_out[0][69], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9079 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h046")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9080 = mux(_T_9079, ic_tag_valid_out[0][70], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9081 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h047")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9082 = mux(_T_9081, ic_tag_valid_out[0][71], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9083 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h048")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9084 = mux(_T_9083, ic_tag_valid_out[0][72], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9085 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h049")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9086 = mux(_T_9085, ic_tag_valid_out[0][73], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9087 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04a")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9088 = mux(_T_9087, ic_tag_valid_out[0][74], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9089 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04b")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9090 = mux(_T_9089, ic_tag_valid_out[0][75], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9091 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04c")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9092 = mux(_T_9091, ic_tag_valid_out[0][76], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9093 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04d")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9094 = mux(_T_9093, ic_tag_valid_out[0][77], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9095 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04e")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9096 = mux(_T_9095, ic_tag_valid_out[0][78], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9097 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04f")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9098 = mux(_T_9097, ic_tag_valid_out[0][79], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9099 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h050")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9100 = mux(_T_9099, ic_tag_valid_out[0][80], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9101 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h051")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9102 = mux(_T_9101, ic_tag_valid_out[0][81], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9103 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h052")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9104 = mux(_T_9103, ic_tag_valid_out[0][82], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9105 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h053")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9106 = mux(_T_9105, ic_tag_valid_out[0][83], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9107 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h054")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9108 = mux(_T_9107, ic_tag_valid_out[0][84], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9109 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h055")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9110 = mux(_T_9109, ic_tag_valid_out[0][85], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9111 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h056")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9112 = mux(_T_9111, ic_tag_valid_out[0][86], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9113 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h057")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9114 = mux(_T_9113, ic_tag_valid_out[0][87], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9115 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h058")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9116 = mux(_T_9115, ic_tag_valid_out[0][88], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9117 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h059")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9118 = mux(_T_9117, ic_tag_valid_out[0][89], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9119 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05a")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9120 = mux(_T_9119, ic_tag_valid_out[0][90], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9121 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05b")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9122 = mux(_T_9121, ic_tag_valid_out[0][91], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9123 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05c")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9124 = mux(_T_9123, ic_tag_valid_out[0][92], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9125 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05d")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9126 = mux(_T_9125, ic_tag_valid_out[0][93], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9127 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05e")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9128 = mux(_T_9127, ic_tag_valid_out[0][94], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9129 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05f")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9130 = mux(_T_9129, ic_tag_valid_out[0][95], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9131 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h060")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9132 = mux(_T_9131, ic_tag_valid_out[0][96], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9133 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h061")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9134 = mux(_T_9133, ic_tag_valid_out[0][97], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9135 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h062")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9136 = mux(_T_9135, ic_tag_valid_out[0][98], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9137 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h063")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9138 = mux(_T_9137, ic_tag_valid_out[0][99], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9139 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h064")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9140 = mux(_T_9139, ic_tag_valid_out[0][100], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9141 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h065")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9142 = mux(_T_9141, ic_tag_valid_out[0][101], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9143 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h066")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9144 = mux(_T_9143, ic_tag_valid_out[0][102], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9145 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h067")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9146 = mux(_T_9145, ic_tag_valid_out[0][103], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9147 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h068")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9148 = mux(_T_9147, ic_tag_valid_out[0][104], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9149 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h069")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9150 = mux(_T_9149, ic_tag_valid_out[0][105], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9151 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06a")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9152 = mux(_T_9151, ic_tag_valid_out[0][106], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9153 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06b")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9154 = mux(_T_9153, ic_tag_valid_out[0][107], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9155 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06c")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9156 = mux(_T_9155, ic_tag_valid_out[0][108], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9157 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06d")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9158 = mux(_T_9157, ic_tag_valid_out[0][109], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9159 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06e")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9160 = mux(_T_9159, ic_tag_valid_out[0][110], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9161 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06f")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9162 = mux(_T_9161, ic_tag_valid_out[0][111], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9163 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h070")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9164 = mux(_T_9163, ic_tag_valid_out[0][112], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9165 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h071")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9166 = mux(_T_9165, ic_tag_valid_out[0][113], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9167 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h072")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9168 = mux(_T_9167, ic_tag_valid_out[0][114], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9169 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h073")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9170 = mux(_T_9169, ic_tag_valid_out[0][115], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9171 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h074")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9172 = mux(_T_9171, ic_tag_valid_out[0][116], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9173 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h075")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9174 = mux(_T_9173, ic_tag_valid_out[0][117], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9175 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h076")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9176 = mux(_T_9175, ic_tag_valid_out[0][118], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9177 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h077")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9178 = mux(_T_9177, ic_tag_valid_out[0][119], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9179 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h078")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9180 = mux(_T_9179, ic_tag_valid_out[0][120], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9181 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h079")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9182 = mux(_T_9181, ic_tag_valid_out[0][121], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9183 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07a")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9184 = mux(_T_9183, ic_tag_valid_out[0][122], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9185 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07b")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9186 = mux(_T_9185, ic_tag_valid_out[0][123], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9187 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07c")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9188 = mux(_T_9187, ic_tag_valid_out[0][124], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9189 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07d")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9190 = mux(_T_9189, ic_tag_valid_out[0][125], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9191 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07e")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9192 = mux(_T_9191, ic_tag_valid_out[0][126], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9193 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07f")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9194 = mux(_T_9193, ic_tag_valid_out[0][127], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9195 = or(_T_8940, _T_8942) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9196 = or(_T_9195, _T_8944) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9197 = or(_T_9196, _T_8946) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9198 = or(_T_9197, _T_8948) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9199 = or(_T_9198, _T_8950) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9200 = or(_T_9199, _T_8952) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9201 = or(_T_9200, _T_8954) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9202 = or(_T_9201, _T_8956) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9203 = or(_T_9202, _T_8958) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9204 = or(_T_9203, _T_8960) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9205 = or(_T_9204, _T_8962) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9206 = or(_T_9205, _T_8964) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9207 = or(_T_9206, _T_8966) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9208 = or(_T_9207, _T_8968) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9209 = or(_T_9208, _T_8970) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9210 = or(_T_9209, _T_8972) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9211 = or(_T_9210, _T_8974) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9212 = or(_T_9211, _T_8976) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9213 = or(_T_9212, _T_8978) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9214 = or(_T_9213, _T_8980) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9215 = or(_T_9214, _T_8982) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9216 = or(_T_9215, _T_8984) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9217 = or(_T_9216, _T_8986) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9218 = or(_T_9217, _T_8988) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9219 = or(_T_9218, _T_8990) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9220 = or(_T_9219, _T_8992) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9221 = or(_T_9220, _T_8994) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9222 = or(_T_9221, _T_8996) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9223 = or(_T_9222, _T_8998) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9224 = or(_T_9223, _T_9000) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9225 = or(_T_9224, _T_9002) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9226 = or(_T_9225, _T_9004) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9227 = or(_T_9226, _T_9006) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9228 = or(_T_9227, _T_9008) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9229 = or(_T_9228, _T_9010) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9230 = or(_T_9229, _T_9012) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9231 = or(_T_9230, _T_9014) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9232 = or(_T_9231, _T_9016) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9233 = or(_T_9232, _T_9018) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9234 = or(_T_9233, _T_9020) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9235 = or(_T_9234, _T_9022) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9236 = or(_T_9235, _T_9024) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9237 = or(_T_9236, _T_9026) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9238 = or(_T_9237, _T_9028) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9239 = or(_T_9238, _T_9030) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9240 = or(_T_9239, _T_9032) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9241 = or(_T_9240, _T_9034) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9242 = or(_T_9241, _T_9036) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9243 = or(_T_9242, _T_9038) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9244 = or(_T_9243, _T_9040) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9245 = or(_T_9244, _T_9042) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9246 = or(_T_9245, _T_9044) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9247 = or(_T_9246, _T_9046) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9248 = or(_T_9247, _T_9048) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9249 = or(_T_9248, _T_9050) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9250 = or(_T_9249, _T_9052) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9251 = or(_T_9250, _T_9054) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9252 = or(_T_9251, _T_9056) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9253 = or(_T_9252, _T_9058) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9254 = or(_T_9253, _T_9060) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9255 = or(_T_9254, _T_9062) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9256 = or(_T_9255, _T_9064) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9257 = or(_T_9256, _T_9066) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9258 = or(_T_9257, _T_9068) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9259 = or(_T_9258, _T_9070) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9260 = or(_T_9259, _T_9072) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9261 = or(_T_9260, _T_9074) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9262 = or(_T_9261, _T_9076) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9263 = or(_T_9262, _T_9078) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9264 = or(_T_9263, _T_9080) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9265 = or(_T_9264, _T_9082) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9266 = or(_T_9265, _T_9084) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9267 = or(_T_9266, _T_9086) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9268 = or(_T_9267, _T_9088) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9269 = or(_T_9268, _T_9090) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9270 = or(_T_9269, _T_9092) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9271 = or(_T_9270, _T_9094) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9272 = or(_T_9271, _T_9096) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9273 = or(_T_9272, _T_9098) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9274 = or(_T_9273, _T_9100) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9275 = or(_T_9274, _T_9102) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9276 = or(_T_9275, _T_9104) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9277 = or(_T_9276, _T_9106) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9278 = or(_T_9277, _T_9108) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9279 = or(_T_9278, _T_9110) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9280 = or(_T_9279, _T_9112) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9281 = or(_T_9280, _T_9114) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9282 = or(_T_9281, _T_9116) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9283 = or(_T_9282, _T_9118) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9284 = or(_T_9283, _T_9120) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9285 = or(_T_9284, _T_9122) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9286 = or(_T_9285, _T_9124) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9287 = or(_T_9286, _T_9126) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9288 = or(_T_9287, _T_9128) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9289 = or(_T_9288, _T_9130) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9290 = or(_T_9289, _T_9132) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9291 = or(_T_9290, _T_9134) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9292 = or(_T_9291, _T_9136) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9293 = or(_T_9292, _T_9138) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9294 = or(_T_9293, _T_9140) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9295 = or(_T_9294, _T_9142) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9296 = or(_T_9295, _T_9144) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9297 = or(_T_9296, _T_9146) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9298 = or(_T_9297, _T_9148) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9299 = or(_T_9298, _T_9150) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9300 = or(_T_9299, _T_9152) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9301 = or(_T_9300, _T_9154) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9302 = or(_T_9301, _T_9156) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9303 = or(_T_9302, _T_9158) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9304 = or(_T_9303, _T_9160) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9305 = or(_T_9304, _T_9162) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9306 = or(_T_9305, _T_9164) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9307 = or(_T_9306, _T_9166) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9308 = or(_T_9307, _T_9168) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9309 = or(_T_9308, _T_9170) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9310 = or(_T_9309, _T_9172) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9311 = or(_T_9310, _T_9174) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9312 = or(_T_9311, _T_9176) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9313 = or(_T_9312, _T_9178) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9314 = or(_T_9313, _T_9180) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9315 = or(_T_9314, _T_9182) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9316 = or(_T_9315, _T_9184) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9317 = or(_T_9316, _T_9186) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9318 = or(_T_9317, _T_9188) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9319 = or(_T_9318, _T_9190) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9320 = or(_T_9319, _T_9192) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9321 = or(_T_9320, _T_9194) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9322 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9323 = mux(_T_9322, ic_tag_valid_out[1][0], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9324 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9325 = mux(_T_9324, ic_tag_valid_out[1][1], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9326 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9327 = mux(_T_9326, ic_tag_valid_out[1][2], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9328 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9329 = mux(_T_9328, ic_tag_valid_out[1][3], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9330 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9331 = mux(_T_9330, ic_tag_valid_out[1][4], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9332 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9333 = mux(_T_9332, ic_tag_valid_out[1][5], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9334 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9335 = mux(_T_9334, ic_tag_valid_out[1][6], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9336 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9337 = mux(_T_9336, ic_tag_valid_out[1][7], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9338 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9339 = mux(_T_9338, ic_tag_valid_out[1][8], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9340 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9341 = mux(_T_9340, ic_tag_valid_out[1][9], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9342 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9343 = mux(_T_9342, ic_tag_valid_out[1][10], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9344 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9345 = mux(_T_9344, ic_tag_valid_out[1][11], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9346 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9347 = mux(_T_9346, ic_tag_valid_out[1][12], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9348 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9349 = mux(_T_9348, ic_tag_valid_out[1][13], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9350 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9351 = mux(_T_9350, ic_tag_valid_out[1][14], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9352 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9353 = mux(_T_9352, ic_tag_valid_out[1][15], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9354 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h010")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9355 = mux(_T_9354, ic_tag_valid_out[1][16], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9356 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h011")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9357 = mux(_T_9356, ic_tag_valid_out[1][17], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9358 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h012")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9359 = mux(_T_9358, ic_tag_valid_out[1][18], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9360 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h013")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9361 = mux(_T_9360, ic_tag_valid_out[1][19], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9362 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h014")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9363 = mux(_T_9362, ic_tag_valid_out[1][20], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9364 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h015")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9365 = mux(_T_9364, ic_tag_valid_out[1][21], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9366 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h016")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9367 = mux(_T_9366, ic_tag_valid_out[1][22], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9368 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h017")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9369 = mux(_T_9368, ic_tag_valid_out[1][23], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9370 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h018")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9371 = mux(_T_9370, ic_tag_valid_out[1][24], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9372 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h019")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9373 = mux(_T_9372, ic_tag_valid_out[1][25], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9374 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01a")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9375 = mux(_T_9374, ic_tag_valid_out[1][26], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9376 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01b")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9377 = mux(_T_9376, ic_tag_valid_out[1][27], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9378 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01c")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9379 = mux(_T_9378, ic_tag_valid_out[1][28], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9380 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01d")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9381 = mux(_T_9380, ic_tag_valid_out[1][29], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9382 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01e")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9383 = mux(_T_9382, ic_tag_valid_out[1][30], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9384 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01f")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9385 = mux(_T_9384, ic_tag_valid_out[1][31], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9386 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h020")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9387 = mux(_T_9386, ic_tag_valid_out[1][32], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9388 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h021")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9389 = mux(_T_9388, ic_tag_valid_out[1][33], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9390 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h022")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9391 = mux(_T_9390, ic_tag_valid_out[1][34], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9392 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h023")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9393 = mux(_T_9392, ic_tag_valid_out[1][35], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9394 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h024")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9395 = mux(_T_9394, ic_tag_valid_out[1][36], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9396 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h025")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9397 = mux(_T_9396, ic_tag_valid_out[1][37], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9398 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h026")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9399 = mux(_T_9398, ic_tag_valid_out[1][38], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9400 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h027")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9401 = mux(_T_9400, ic_tag_valid_out[1][39], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9402 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h028")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9403 = mux(_T_9402, ic_tag_valid_out[1][40], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9404 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h029")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9405 = mux(_T_9404, ic_tag_valid_out[1][41], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9406 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02a")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9407 = mux(_T_9406, ic_tag_valid_out[1][42], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9408 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02b")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9409 = mux(_T_9408, ic_tag_valid_out[1][43], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9410 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02c")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9411 = mux(_T_9410, ic_tag_valid_out[1][44], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9412 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02d")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9413 = mux(_T_9412, ic_tag_valid_out[1][45], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9414 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02e")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9415 = mux(_T_9414, ic_tag_valid_out[1][46], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9416 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02f")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9417 = mux(_T_9416, ic_tag_valid_out[1][47], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9418 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h030")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9419 = mux(_T_9418, ic_tag_valid_out[1][48], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9420 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h031")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9421 = mux(_T_9420, ic_tag_valid_out[1][49], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9422 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h032")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9423 = mux(_T_9422, ic_tag_valid_out[1][50], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9424 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h033")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9425 = mux(_T_9424, ic_tag_valid_out[1][51], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9426 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h034")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9427 = mux(_T_9426, ic_tag_valid_out[1][52], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9428 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h035")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9429 = mux(_T_9428, ic_tag_valid_out[1][53], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9430 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h036")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9431 = mux(_T_9430, ic_tag_valid_out[1][54], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9432 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h037")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9433 = mux(_T_9432, ic_tag_valid_out[1][55], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9434 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h038")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9435 = mux(_T_9434, ic_tag_valid_out[1][56], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9436 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h039")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9437 = mux(_T_9436, ic_tag_valid_out[1][57], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9438 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03a")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9439 = mux(_T_9438, ic_tag_valid_out[1][58], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9440 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03b")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9441 = mux(_T_9440, ic_tag_valid_out[1][59], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9442 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03c")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9443 = mux(_T_9442, ic_tag_valid_out[1][60], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9444 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03d")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9445 = mux(_T_9444, ic_tag_valid_out[1][61], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9446 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03e")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9447 = mux(_T_9446, ic_tag_valid_out[1][62], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9448 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03f")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9449 = mux(_T_9448, ic_tag_valid_out[1][63], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9450 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h040")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9451 = mux(_T_9450, ic_tag_valid_out[1][64], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9452 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h041")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9453 = mux(_T_9452, ic_tag_valid_out[1][65], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9454 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h042")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9455 = mux(_T_9454, ic_tag_valid_out[1][66], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9456 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h043")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9457 = mux(_T_9456, ic_tag_valid_out[1][67], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9458 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h044")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9459 = mux(_T_9458, ic_tag_valid_out[1][68], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9460 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h045")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9461 = mux(_T_9460, ic_tag_valid_out[1][69], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9462 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h046")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9463 = mux(_T_9462, ic_tag_valid_out[1][70], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9464 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h047")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9465 = mux(_T_9464, ic_tag_valid_out[1][71], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9466 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h048")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9467 = mux(_T_9466, ic_tag_valid_out[1][72], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9468 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h049")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9469 = mux(_T_9468, ic_tag_valid_out[1][73], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9470 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04a")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9471 = mux(_T_9470, ic_tag_valid_out[1][74], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9472 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04b")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9473 = mux(_T_9472, ic_tag_valid_out[1][75], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9474 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04c")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9475 = mux(_T_9474, ic_tag_valid_out[1][76], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9476 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04d")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9477 = mux(_T_9476, ic_tag_valid_out[1][77], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9478 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04e")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9479 = mux(_T_9478, ic_tag_valid_out[1][78], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9480 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04f")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9481 = mux(_T_9480, ic_tag_valid_out[1][79], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9482 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h050")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9483 = mux(_T_9482, ic_tag_valid_out[1][80], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9484 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h051")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9485 = mux(_T_9484, ic_tag_valid_out[1][81], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9486 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h052")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9487 = mux(_T_9486, ic_tag_valid_out[1][82], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9488 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h053")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9489 = mux(_T_9488, ic_tag_valid_out[1][83], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9490 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h054")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9491 = mux(_T_9490, ic_tag_valid_out[1][84], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9492 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h055")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9493 = mux(_T_9492, ic_tag_valid_out[1][85], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9494 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h056")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9495 = mux(_T_9494, ic_tag_valid_out[1][86], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9496 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h057")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9497 = mux(_T_9496, ic_tag_valid_out[1][87], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9498 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h058")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9499 = mux(_T_9498, ic_tag_valid_out[1][88], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9500 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h059")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9501 = mux(_T_9500, ic_tag_valid_out[1][89], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9502 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05a")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9503 = mux(_T_9502, ic_tag_valid_out[1][90], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9504 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05b")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9505 = mux(_T_9504, ic_tag_valid_out[1][91], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9506 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05c")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9507 = mux(_T_9506, ic_tag_valid_out[1][92], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9508 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05d")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9509 = mux(_T_9508, ic_tag_valid_out[1][93], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9510 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05e")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9511 = mux(_T_9510, ic_tag_valid_out[1][94], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9512 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05f")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9513 = mux(_T_9512, ic_tag_valid_out[1][95], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9514 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h060")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9515 = mux(_T_9514, ic_tag_valid_out[1][96], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9516 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h061")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9517 = mux(_T_9516, ic_tag_valid_out[1][97], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9518 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h062")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9519 = mux(_T_9518, ic_tag_valid_out[1][98], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9520 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h063")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9521 = mux(_T_9520, ic_tag_valid_out[1][99], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9522 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h064")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9523 = mux(_T_9522, ic_tag_valid_out[1][100], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9524 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h065")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9525 = mux(_T_9524, ic_tag_valid_out[1][101], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9526 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h066")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9527 = mux(_T_9526, ic_tag_valid_out[1][102], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9528 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h067")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9529 = mux(_T_9528, ic_tag_valid_out[1][103], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9530 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h068")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9531 = mux(_T_9530, ic_tag_valid_out[1][104], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9532 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h069")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9533 = mux(_T_9532, ic_tag_valid_out[1][105], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9534 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06a")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9535 = mux(_T_9534, ic_tag_valid_out[1][106], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9536 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06b")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9537 = mux(_T_9536, ic_tag_valid_out[1][107], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9538 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06c")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9539 = mux(_T_9538, ic_tag_valid_out[1][108], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9540 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06d")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9541 = mux(_T_9540, ic_tag_valid_out[1][109], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9542 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06e")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9543 = mux(_T_9542, ic_tag_valid_out[1][110], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9544 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06f")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9545 = mux(_T_9544, ic_tag_valid_out[1][111], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9546 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h070")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9547 = mux(_T_9546, ic_tag_valid_out[1][112], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9548 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h071")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9549 = mux(_T_9548, ic_tag_valid_out[1][113], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9550 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h072")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9551 = mux(_T_9550, ic_tag_valid_out[1][114], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9552 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h073")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9553 = mux(_T_9552, ic_tag_valid_out[1][115], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9554 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h074")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9555 = mux(_T_9554, ic_tag_valid_out[1][116], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9556 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h075")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9557 = mux(_T_9556, ic_tag_valid_out[1][117], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9558 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h076")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9559 = mux(_T_9558, ic_tag_valid_out[1][118], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9560 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h077")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9561 = mux(_T_9560, ic_tag_valid_out[1][119], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9562 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h078")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9563 = mux(_T_9562, ic_tag_valid_out[1][120], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9564 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h079")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9565 = mux(_T_9564, ic_tag_valid_out[1][121], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9566 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07a")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9567 = mux(_T_9566, ic_tag_valid_out[1][122], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9568 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07b")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9569 = mux(_T_9568, ic_tag_valid_out[1][123], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9570 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07c")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9571 = mux(_T_9570, ic_tag_valid_out[1][124], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9572 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07d")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9573 = mux(_T_9572, ic_tag_valid_out[1][125], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9574 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07e")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9575 = mux(_T_9574, ic_tag_valid_out[1][126], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9576 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07f")) @[el2_ifu_mem_ctl.scala 764:31] + node _T_9577 = mux(_T_9576, ic_tag_valid_out[1][127], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 764:8] + node _T_9578 = or(_T_9323, _T_9325) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9579 = or(_T_9578, _T_9327) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9580 = or(_T_9579, _T_9329) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9581 = or(_T_9580, _T_9331) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9582 = or(_T_9581, _T_9333) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9583 = or(_T_9582, _T_9335) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9584 = or(_T_9583, _T_9337) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9585 = or(_T_9584, _T_9339) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9586 = or(_T_9585, _T_9341) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9587 = or(_T_9586, _T_9343) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9588 = or(_T_9587, _T_9345) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9589 = or(_T_9588, _T_9347) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9590 = or(_T_9589, _T_9349) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9591 = or(_T_9590, _T_9351) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9592 = or(_T_9591, _T_9353) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9593 = or(_T_9592, _T_9355) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9594 = or(_T_9593, _T_9357) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9595 = or(_T_9594, _T_9359) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9596 = or(_T_9595, _T_9361) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9597 = or(_T_9596, _T_9363) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9598 = or(_T_9597, _T_9365) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9599 = or(_T_9598, _T_9367) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9600 = or(_T_9599, _T_9369) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9601 = or(_T_9600, _T_9371) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9602 = or(_T_9601, _T_9373) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9603 = or(_T_9602, _T_9375) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9604 = or(_T_9603, _T_9377) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9605 = or(_T_9604, _T_9379) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9606 = or(_T_9605, _T_9381) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9607 = or(_T_9606, _T_9383) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9608 = or(_T_9607, _T_9385) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9609 = or(_T_9608, _T_9387) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9610 = or(_T_9609, _T_9389) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9611 = or(_T_9610, _T_9391) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9612 = or(_T_9611, _T_9393) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9613 = or(_T_9612, _T_9395) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9614 = or(_T_9613, _T_9397) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9615 = or(_T_9614, _T_9399) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9616 = or(_T_9615, _T_9401) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9617 = or(_T_9616, _T_9403) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9618 = or(_T_9617, _T_9405) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9619 = or(_T_9618, _T_9407) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9620 = or(_T_9619, _T_9409) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9621 = or(_T_9620, _T_9411) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9622 = or(_T_9621, _T_9413) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9623 = or(_T_9622, _T_9415) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9624 = or(_T_9623, _T_9417) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9625 = or(_T_9624, _T_9419) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9626 = or(_T_9625, _T_9421) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9627 = or(_T_9626, _T_9423) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9628 = or(_T_9627, _T_9425) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9629 = or(_T_9628, _T_9427) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9630 = or(_T_9629, _T_9429) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9631 = or(_T_9630, _T_9431) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9632 = or(_T_9631, _T_9433) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9633 = or(_T_9632, _T_9435) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9634 = or(_T_9633, _T_9437) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9635 = or(_T_9634, _T_9439) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9636 = or(_T_9635, _T_9441) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9637 = or(_T_9636, _T_9443) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9638 = or(_T_9637, _T_9445) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9639 = or(_T_9638, _T_9447) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9640 = or(_T_9639, _T_9449) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9641 = or(_T_9640, _T_9451) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9642 = or(_T_9641, _T_9453) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9643 = or(_T_9642, _T_9455) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9644 = or(_T_9643, _T_9457) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9645 = or(_T_9644, _T_9459) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9646 = or(_T_9645, _T_9461) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9647 = or(_T_9646, _T_9463) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9648 = or(_T_9647, _T_9465) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9649 = or(_T_9648, _T_9467) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9650 = or(_T_9649, _T_9469) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9651 = or(_T_9650, _T_9471) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9652 = or(_T_9651, _T_9473) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9653 = or(_T_9652, _T_9475) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9654 = or(_T_9653, _T_9477) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9655 = or(_T_9654, _T_9479) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9656 = or(_T_9655, _T_9481) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9657 = or(_T_9656, _T_9483) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9658 = or(_T_9657, _T_9485) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9659 = or(_T_9658, _T_9487) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9660 = or(_T_9659, _T_9489) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9661 = or(_T_9660, _T_9491) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9662 = or(_T_9661, _T_9493) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9663 = or(_T_9662, _T_9495) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9664 = or(_T_9663, _T_9497) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9665 = or(_T_9664, _T_9499) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9666 = or(_T_9665, _T_9501) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9667 = or(_T_9666, _T_9503) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9668 = or(_T_9667, _T_9505) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9669 = or(_T_9668, _T_9507) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9670 = or(_T_9669, _T_9509) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9671 = or(_T_9670, _T_9511) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9672 = or(_T_9671, _T_9513) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9673 = or(_T_9672, _T_9515) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9674 = or(_T_9673, _T_9517) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9675 = or(_T_9674, _T_9519) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9676 = or(_T_9675, _T_9521) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9677 = or(_T_9676, _T_9523) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9678 = or(_T_9677, _T_9525) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9679 = or(_T_9678, _T_9527) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9680 = or(_T_9679, _T_9529) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9681 = or(_T_9680, _T_9531) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9682 = or(_T_9681, _T_9533) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9683 = or(_T_9682, _T_9535) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9684 = or(_T_9683, _T_9537) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9685 = or(_T_9684, _T_9539) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9686 = or(_T_9685, _T_9541) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9687 = or(_T_9686, _T_9543) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9688 = or(_T_9687, _T_9545) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9689 = or(_T_9688, _T_9547) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9690 = or(_T_9689, _T_9549) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9691 = or(_T_9690, _T_9551) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9692 = or(_T_9691, _T_9553) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9693 = or(_T_9692, _T_9555) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9694 = or(_T_9693, _T_9557) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9695 = or(_T_9694, _T_9559) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9696 = or(_T_9695, _T_9561) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9697 = or(_T_9696, _T_9563) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9698 = or(_T_9697, _T_9565) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9699 = or(_T_9698, _T_9567) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9700 = or(_T_9699, _T_9569) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9701 = or(_T_9700, _T_9571) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9702 = or(_T_9701, _T_9573) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9703 = or(_T_9702, _T_9575) @[el2_ifu_mem_ctl.scala 764:89] + node _T_9704 = or(_T_9703, _T_9577) @[el2_ifu_mem_ctl.scala 764:89] + node ic_tag_valid_unq = cat(_T_9704, _T_9321) @[Cat.scala 29:58] + wire way_status_hit_new : UInt<1> + way_status_hit_new <= UInt<1>("h00") + node _T_9705 = eq(way_status_mb_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 789:31] + node _T_9706 = bits(tagv_mb_ff, 0, 0) @[el2_ifu_mem_ctl.scala 789:61] + node _T_9707 = and(_T_9705, _T_9706) @[el2_ifu_mem_ctl.scala 789:49] + node _T_9708 = bits(tagv_mb_ff, 1, 1) @[el2_ifu_mem_ctl.scala 789:77] + node _T_9709 = and(_T_9707, _T_9708) @[el2_ifu_mem_ctl.scala 789:65] + node _T_9710 = bits(tagv_mb_ff, 0, 0) @[el2_ifu_mem_ctl.scala 789:95] + node _T_9711 = eq(_T_9710, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 789:84] + node _T_9712 = or(_T_9709, _T_9711) @[el2_ifu_mem_ctl.scala 789:82] + replace_way_mb_any[0] <= _T_9712 @[el2_ifu_mem_ctl.scala 789:27] + node _T_9713 = bits(tagv_mb_ff, 0, 0) @[el2_ifu_mem_ctl.scala 790:60] + node _T_9714 = and(way_status_mb_ff, _T_9713) @[el2_ifu_mem_ctl.scala 790:48] + node _T_9715 = bits(tagv_mb_ff, 1, 1) @[el2_ifu_mem_ctl.scala 790:76] + node _T_9716 = and(_T_9714, _T_9715) @[el2_ifu_mem_ctl.scala 790:64] + node _T_9717 = bits(tagv_mb_ff, 1, 1) @[el2_ifu_mem_ctl.scala 790:94] + node _T_9718 = eq(_T_9717, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 790:83] + node _T_9719 = bits(tagv_mb_ff, 0, 0) @[el2_ifu_mem_ctl.scala 790:110] + node _T_9720 = and(_T_9718, _T_9719) @[el2_ifu_mem_ctl.scala 790:98] + node _T_9721 = or(_T_9716, _T_9720) @[el2_ifu_mem_ctl.scala 790:81] + replace_way_mb_any[1] <= _T_9721 @[el2_ifu_mem_ctl.scala 790:27] + node _T_9722 = bits(io.ic_rd_hit, 0, 0) @[el2_ifu_mem_ctl.scala 791:39] + way_status_hit_new <= _T_9722 @[el2_ifu_mem_ctl.scala 791:24] + way_status_rep_new <= replace_way_mb_any[0] @[el2_ifu_mem_ctl.scala 792:24] + node _T_9723 = and(bus_ifu_wr_en_ff_q, last_beat) @[el2_ifu_mem_ctl.scala 794:45] + node _T_9724 = bits(_T_9723, 0, 0) @[el2_ifu_mem_ctl.scala 794:58] + node _T_9725 = mux(_T_9724, way_status_rep_new, way_status_hit_new) @[el2_ifu_mem_ctl.scala 794:24] + way_status_new <= _T_9725 @[el2_ifu_mem_ctl.scala 794:18] + node _T_9726 = and(bus_ifu_wr_en_ff_q, last_beat) @[el2_ifu_mem_ctl.scala 795:43] + node _T_9727 = or(_T_9726, ic_act_hit_f) @[el2_ifu_mem_ctl.scala 795:56] + way_status_wr_en <= _T_9727 @[el2_ifu_mem_ctl.scala 795:20] + node _T_9728 = and(bus_ifu_wr_en_ff_q, replace_way_mb_any[0]) @[el2_ifu_mem_ctl.scala 796:72] + node bus_wren_0 = and(_T_9728, miss_pending) @[el2_ifu_mem_ctl.scala 796:96] + node _T_9729 = and(bus_ifu_wr_en_ff_q, replace_way_mb_any[1]) @[el2_ifu_mem_ctl.scala 796:72] + node bus_wren_1 = and(_T_9729, miss_pending) @[el2_ifu_mem_ctl.scala 796:96] + node _T_9730 = and(bus_ifu_wr_en_ff_wo_err, replace_way_mb_any[0]) @[el2_ifu_mem_ctl.scala 798:82] + node _T_9731 = and(_T_9730, miss_pending) @[el2_ifu_mem_ctl.scala 798:106] + node bus_wren_last_0 = and(_T_9731, bus_last_data_beat) @[el2_ifu_mem_ctl.scala 798:121] + node _T_9732 = and(bus_ifu_wr_en_ff_wo_err, replace_way_mb_any[1]) @[el2_ifu_mem_ctl.scala 798:82] + node _T_9733 = and(_T_9732, miss_pending) @[el2_ifu_mem_ctl.scala 798:106] + node bus_wren_last_1 = and(_T_9733, bus_last_data_beat) @[el2_ifu_mem_ctl.scala 798:121] + node wren_reset_miss_0 = and(replace_way_mb_any[0], reset_tag_valid_for_miss) @[el2_ifu_mem_ctl.scala 799:82] + node wren_reset_miss_1 = and(replace_way_mb_any[1], reset_tag_valid_for_miss) @[el2_ifu_mem_ctl.scala 799:82] + node _T_9734 = or(bus_wren_last_0, wren_reset_miss_0) @[el2_ifu_mem_ctl.scala 800:71] + node _T_9735 = or(bus_wren_last_1, wren_reset_miss_1) @[el2_ifu_mem_ctl.scala 800:71] + node _T_9736 = cat(_T_9735, _T_9734) @[Cat.scala 29:58] + ifu_tag_wren <= _T_9736 @[el2_ifu_mem_ctl.scala 800:16] + node _T_9737 = cat(bus_wren_1, bus_wren_0) @[Cat.scala 29:58] + bus_ic_wr_en <= _T_9737 @[el2_ifu_mem_ctl.scala 802:16] + node _T_9738 = eq(fetch_uncacheable_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 816:63] + node _T_9739 = and(_T_9738, ifc_fetch_req_f) @[el2_ifu_mem_ctl.scala 816:85] + node _T_9740 = bits(_T_9739, 0, 0) @[Bitwise.scala 72:15] + node _T_9741 = mux(_T_9740, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_9742 = and(ic_tag_valid_unq, _T_9741) @[el2_ifu_mem_ctl.scala 816:39] + io.ic_tag_valid <= _T_9742 @[el2_ifu_mem_ctl.scala 816:19] + wire ic_debug_way_ff : UInt<2> + ic_debug_way_ff <= UInt<1>("h00") + node _T_9743 = bits(ic_debug_rd_en_ff, 0, 0) @[Bitwise.scala 72:15] + node _T_9744 = mux(_T_9743, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_9745 = and(ic_debug_way_ff, _T_9744) @[el2_ifu_mem_ctl.scala 819:67] + node _T_9746 = and(ic_tag_valid_unq, _T_9745) @[el2_ifu_mem_ctl.scala 819:48] + node _T_9747 = orr(_T_9746) @[el2_ifu_mem_ctl.scala 819:115] + ic_debug_tag_val_rd_out <= _T_9747 @[el2_ifu_mem_ctl.scala 819:27] + reg _T_9748 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 821:57] + _T_9748 <= ic_act_miss_f @[el2_ifu_mem_ctl.scala 821:57] + io.ifu_pmu_ic_miss <= _T_9748 @[el2_ifu_mem_ctl.scala 821:22] + reg _T_9749 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 822:56] + _T_9749 <= ic_act_hit_f @[el2_ifu_mem_ctl.scala 822:56] + io.ifu_pmu_ic_hit <= _T_9749 @[el2_ifu_mem_ctl.scala 822:21] + reg _T_9750 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 823:59] + _T_9750 <= ifc_bus_acc_fault_f @[el2_ifu_mem_ctl.scala 823:59] + io.ifu_pmu_bus_error <= _T_9750 @[el2_ifu_mem_ctl.scala 823:24] + node _T_9751 = eq(ifu_bus_arready_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 824:80] + node _T_9752 = and(ifu_bus_arvalid_ff, _T_9751) @[el2_ifu_mem_ctl.scala 824:78] + node _T_9753 = and(_T_9752, miss_pending) @[el2_ifu_mem_ctl.scala 824:100] + reg _T_9754 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 824:58] + _T_9754 <= _T_9753 @[el2_ifu_mem_ctl.scala 824:58] + io.ifu_pmu_bus_busy <= _T_9754 @[el2_ifu_mem_ctl.scala 824:23] + reg _T_9755 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 825:58] + _T_9755 <= bus_cmd_sent @[el2_ifu_mem_ctl.scala 825:58] + io.ifu_pmu_bus_trxn <= _T_9755 @[el2_ifu_mem_ctl.scala 825:23] + io.ic_debug_addr <= io.dec_tlu_ic_diag_pkt.icache_dicawics @[el2_ifu_mem_ctl.scala 828:20] + node _T_9756 = bits(io.dec_tlu_ic_diag_pkt.icache_dicawics, 16, 16) @[el2_ifu_mem_ctl.scala 829:66] + io.ic_debug_tag_array <= _T_9756 @[el2_ifu_mem_ctl.scala 829:25] + io.ic_debug_rd_en <= io.dec_tlu_ic_diag_pkt.icache_rd_valid @[el2_ifu_mem_ctl.scala 830:21] + io.ic_debug_wr_en <= io.dec_tlu_ic_diag_pkt.icache_wr_valid @[el2_ifu_mem_ctl.scala 831:21] + node _T_9757 = bits(io.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[el2_ifu_mem_ctl.scala 832:64] + node _T_9758 = eq(_T_9757, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 832:71] + node _T_9759 = bits(io.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[el2_ifu_mem_ctl.scala 832:117] + node _T_9760 = eq(_T_9759, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 832:124] + node _T_9761 = bits(io.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[el2_ifu_mem_ctl.scala 833:43] + node _T_9762 = eq(_T_9761, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 833:50] + node _T_9763 = bits(io.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[el2_ifu_mem_ctl.scala 833:96] + node _T_9764 = eq(_T_9763, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 833:103] + node _T_9765 = cat(_T_9762, _T_9764) @[Cat.scala 29:58] + node _T_9766 = cat(_T_9758, _T_9760) @[Cat.scala 29:58] + node _T_9767 = cat(_T_9766, _T_9765) @[Cat.scala 29:58] + io.ic_debug_way <= _T_9767 @[el2_ifu_mem_ctl.scala 832:19] + node _T_9768 = and(io.ic_debug_wr_en, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 834:65] + node _T_9769 = bits(_T_9768, 0, 0) @[Bitwise.scala 72:15] + node _T_9770 = mux(_T_9769, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_9771 = and(_T_9770, io.ic_debug_way) @[el2_ifu_mem_ctl.scala 834:90] + ic_debug_tag_wr_en <= _T_9771 @[el2_ifu_mem_ctl.scala 834:22] + node ic_debug_ict_array_sel_in = and(io.ic_debug_rd_en, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 835:53] + reg _T_9772 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 836:53] + _T_9772 <= io.ic_debug_way @[el2_ifu_mem_ctl.scala 836:53] + ic_debug_way_ff <= _T_9772 @[el2_ifu_mem_ctl.scala 836:19] + reg _T_9773 : UInt<1>, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 837:63] + _T_9773 <= ic_debug_ict_array_sel_in @[el2_ifu_mem_ctl.scala 837:63] + ic_debug_ict_array_sel_ff <= _T_9773 @[el2_ifu_mem_ctl.scala 837:29] + reg _T_9774 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 838:54] + _T_9774 <= io.ic_debug_rd_en @[el2_ifu_mem_ctl.scala 838:54] + ic_debug_rd_en_ff <= _T_9774 @[el2_ifu_mem_ctl.scala 838:21] + node _T_9775 = bits(ic_debug_rd_en_ff, 0, 0) @[el2_ifu_mem_ctl.scala 839:111] + reg _T_9776 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_9775 : @[Reg.scala 28:19] + _T_9776 <= ic_debug_rd_en_ff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.ifu_ic_debug_rd_data_valid <= _T_9776 @[el2_ifu_mem_ctl.scala 839:33] + node _T_9777 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58] + node _T_9778 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58] + node _T_9779 = cat(_T_9778, _T_9777) @[Cat.scala 29:58] + node _T_9780 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58] + node _T_9781 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58] + node _T_9782 = cat(_T_9781, _T_9780) @[Cat.scala 29:58] + node _T_9783 = cat(_T_9782, _T_9779) @[Cat.scala 29:58] + node _T_9784 = orr(_T_9783) @[el2_ifu_mem_ctl.scala 840:215] + node _T_9785 = eq(_T_9784, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 840:29] + node _T_9786 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_9787 = or(_T_9786, UInt<31>("h07fffffff")) @[el2_ifu_mem_ctl.scala 841:63] + node _T_9788 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[el2_ifu_mem_ctl.scala 841:127] + node _T_9789 = eq(_T_9787, _T_9788) @[el2_ifu_mem_ctl.scala 841:94] + node _T_9790 = and(UInt<1>("h01"), _T_9789) @[el2_ifu_mem_ctl.scala 841:28] + node _T_9791 = or(_T_9785, _T_9790) @[el2_ifu_mem_ctl.scala 840:219] + node _T_9792 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_9793 = or(_T_9792, UInt<30>("h03fffffff")) @[el2_ifu_mem_ctl.scala 842:63] + node _T_9794 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[el2_ifu_mem_ctl.scala 842:127] + node _T_9795 = eq(_T_9793, _T_9794) @[el2_ifu_mem_ctl.scala 842:94] + node _T_9796 = and(UInt<1>("h01"), _T_9795) @[el2_ifu_mem_ctl.scala 842:28] + node _T_9797 = or(_T_9791, _T_9796) @[el2_ifu_mem_ctl.scala 841:160] + node _T_9798 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_9799 = or(_T_9798, UInt<29>("h01fffffff")) @[el2_ifu_mem_ctl.scala 843:63] + node _T_9800 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[el2_ifu_mem_ctl.scala 843:127] + node _T_9801 = eq(_T_9799, _T_9800) @[el2_ifu_mem_ctl.scala 843:94] + node _T_9802 = and(UInt<1>("h01"), _T_9801) @[el2_ifu_mem_ctl.scala 843:28] + node _T_9803 = or(_T_9797, _T_9802) @[el2_ifu_mem_ctl.scala 842:160] + node _T_9804 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_9805 = or(_T_9804, UInt<28>("h0fffffff")) @[el2_ifu_mem_ctl.scala 844:63] + node _T_9806 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[el2_ifu_mem_ctl.scala 844:127] + node _T_9807 = eq(_T_9805, _T_9806) @[el2_ifu_mem_ctl.scala 844:94] + node _T_9808 = and(UInt<1>("h01"), _T_9807) @[el2_ifu_mem_ctl.scala 844:28] + node _T_9809 = or(_T_9803, _T_9808) @[el2_ifu_mem_ctl.scala 843:160] + node _T_9810 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_9811 = or(_T_9810, UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 845:63] + node _T_9812 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 845:127] + node _T_9813 = eq(_T_9811, _T_9812) @[el2_ifu_mem_ctl.scala 845:94] + node _T_9814 = and(UInt<1>("h00"), _T_9813) @[el2_ifu_mem_ctl.scala 845:28] + node _T_9815 = or(_T_9809, _T_9814) @[el2_ifu_mem_ctl.scala 844:160] + node _T_9816 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_9817 = or(_T_9816, UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 846:63] + node _T_9818 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 846:127] + node _T_9819 = eq(_T_9817, _T_9818) @[el2_ifu_mem_ctl.scala 846:94] + node _T_9820 = and(UInt<1>("h00"), _T_9819) @[el2_ifu_mem_ctl.scala 846:28] + node _T_9821 = or(_T_9815, _T_9820) @[el2_ifu_mem_ctl.scala 845:160] + node _T_9822 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_9823 = or(_T_9822, UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 847:63] + node _T_9824 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 847:127] + node _T_9825 = eq(_T_9823, _T_9824) @[el2_ifu_mem_ctl.scala 847:94] + node _T_9826 = and(UInt<1>("h00"), _T_9825) @[el2_ifu_mem_ctl.scala 847:28] + node _T_9827 = or(_T_9821, _T_9826) @[el2_ifu_mem_ctl.scala 846:160] + node _T_9828 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_9829 = or(_T_9828, UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 848:63] + node _T_9830 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 848:127] + node _T_9831 = eq(_T_9829, _T_9830) @[el2_ifu_mem_ctl.scala 848:94] + node _T_9832 = and(UInt<1>("h00"), _T_9831) @[el2_ifu_mem_ctl.scala 848:28] + node ifc_region_acc_okay = or(_T_9827, _T_9832) @[el2_ifu_mem_ctl.scala 847:160] + node _T_9833 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 849:40] + node _T_9834 = eq(ifc_region_acc_okay, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 849:65] + node _T_9835 = and(_T_9833, _T_9834) @[el2_ifu_mem_ctl.scala 849:63] + node ifc_region_acc_fault_memory_bf = and(_T_9835, io.ifc_fetch_req_bf) @[el2_ifu_mem_ctl.scala 849:86] + node _T_9836 = or(io.ifc_region_acc_fault_bf, ifc_region_acc_fault_memory_bf) @[el2_ifu_mem_ctl.scala 850:63] + ifc_region_acc_fault_final_bf <= _T_9836 @[el2_ifu_mem_ctl.scala 850:33] + reg _T_9837 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 851:66] + _T_9837 <= ifc_region_acc_fault_memory_bf @[el2_ifu_mem_ctl.scala 851:66] + ifc_region_acc_fault_memory_f <= _T_9837 @[el2_ifu_mem_ctl.scala 851:33] + diff --git a/el2_ifu_mem_ctl.v b/el2_ifu_mem_ctl.v new file mode 100644 index 00000000..bd2a2ee4 --- /dev/null +++ b/el2_ifu_mem_ctl.v @@ -0,0 +1,11916 @@ +module rvclkhdr( + output io_l1clk, + input io_clk, + input io_en, + input io_scan_mode +); + wire clkhdr_Q; // @[el2_lib.scala 474:26] + wire clkhdr_CK; // @[el2_lib.scala 474:26] + wire clkhdr_EN; // @[el2_lib.scala 474:26] + wire clkhdr_SE; // @[el2_lib.scala 474:26] + gated_latch clkhdr ( // @[el2_lib.scala 474:26] + .Q(clkhdr_Q), + .CK(clkhdr_CK), + .EN(clkhdr_EN), + .SE(clkhdr_SE) + ); + assign io_l1clk = clkhdr_Q; // @[el2_lib.scala 475:14] + assign clkhdr_CK = io_clk; // @[el2_lib.scala 476:18] + assign clkhdr_EN = io_en; // @[el2_lib.scala 477:18] + assign clkhdr_SE = io_scan_mode; // @[el2_lib.scala 478:18] +endmodule +module el2_ifu_mem_ctl( + input clock, + input reset, + input io_free_clk, + input io_active_clk, + input io_exu_flush_final, + input io_dec_tlu_flush_lower_wb, + input io_dec_tlu_flush_err_wb, + input io_dec_tlu_i0_commit_cmt, + input io_dec_tlu_force_halt, + input [30:0] io_ifc_fetch_addr_bf, + input io_ifc_fetch_uncacheable_bf, + input io_ifc_fetch_req_bf, + input io_ifc_fetch_req_bf_raw, + input io_ifc_iccm_access_bf, + input io_ifc_region_acc_fault_bf, + input io_ifc_dma_access_ok, + input io_dec_tlu_fence_i_wb, + input io_ifu_bp_hit_taken_f, + input io_ifu_bp_inst_mask_f, + input io_ifu_axi_arready, + input io_ifu_axi_rvalid, + input [2:0] io_ifu_axi_rid, + input [63:0] io_ifu_axi_rdata, + input [1:0] io_ifu_axi_rresp, + input io_ifu_bus_clk_en, + input io_dma_iccm_req, + input [31:0] io_dma_mem_addr, + input [2:0] io_dma_mem_sz, + input io_dma_mem_write, + input [63:0] io_dma_mem_wdata, + input [2:0] io_dma_mem_tag, + input [63:0] io_ic_rd_data, + input [70:0] io_ic_debug_rd_data, + input [25:0] io_ictag_debug_rd_data, + input [1:0] io_ic_eccerr, + input [1:0] io_ic_parerr, + input [1:0] io_ic_rd_hit, + input io_ic_tag_perr, + input [63:0] io_iccm_rd_data, + input [77:0] io_iccm_rd_data_ecc, + input [1:0] io_ifu_fetch_val, + input [70:0] io_dec_tlu_ic_diag_pkt_icache_wrdata, + input [16:0] io_dec_tlu_ic_diag_pkt_icache_dicawics, + input io_dec_tlu_ic_diag_pkt_icache_rd_valid, + input io_dec_tlu_ic_diag_pkt_icache_wr_valid, + output io_ifu_miss_state_idle, + output io_ifu_ic_mb_empty, + output io_ic_dma_active, + output io_ic_write_stall, + output io_ifu_pmu_ic_miss, + output io_ifu_pmu_ic_hit, + output io_ifu_pmu_bus_error, + output io_ifu_pmu_bus_busy, + output io_ifu_pmu_bus_trxn, + output io_ifu_axi_awvalid, + output [2:0] io_ifu_axi_awid, + output [31:0] io_ifu_axi_awaddr, + output [3:0] io_ifu_axi_awregion, + output [7:0] io_ifu_axi_awlen, + output [2:0] io_ifu_axi_awsize, + output [1:0] io_ifu_axi_awburst, + output io_ifu_axi_awlock, + output [3:0] io_ifu_axi_awcache, + output [2:0] io_ifu_axi_awprot, + output [3:0] io_ifu_axi_awqos, + output io_ifu_axi_wvalid, + output [63:0] io_ifu_axi_wdata, + output [7:0] io_ifu_axi_wstrb, + output io_ifu_axi_wlast, + output io_ifu_axi_bready, + output io_ifu_axi_arvalid, + output [2:0] io_ifu_axi_arid, + output [31:0] io_ifu_axi_araddr, + output [3:0] io_ifu_axi_arregion, + output [7:0] io_ifu_axi_arlen, + output [2:0] io_ifu_axi_arsize, + output [1:0] io_ifu_axi_arburst, + output io_ifu_axi_arlock, + output [3:0] io_ifu_axi_arcache, + output [2:0] io_ifu_axi_arprot, + output [3:0] io_ifu_axi_arqos, + output io_ifu_axi_rready, + output io_iccm_dma_ecc_error, + output io_iccm_dma_rvalid, + output [63:0] io_iccm_dma_rdata, + output [2:0] io_iccm_dma_rtag, + output io_iccm_ready, + output [30:0] io_ic_rw_addr, + output [1:0] io_ic_wr_en, + output io_ic_rd_en, + output [70:0] io_ic_wr_data_0, + output [70:0] io_ic_wr_data_1, + output [70:0] io_ic_debug_wr_data, + output [70:0] io_ifu_ic_debug_rd_data, + output [9:0] io_ic_debug_addr, + output io_ic_debug_rd_en, + output io_ic_debug_wr_en, + output io_ic_debug_tag_array, + output [1:0] io_ic_debug_way, + output [1:0] io_ic_tag_valid, + output [14:0] io_iccm_rw_addr, + output io_iccm_wren, + output io_iccm_rden, + output [77:0] io_iccm_wr_data, + output [2:0] io_iccm_wr_size, + output io_ic_hit_f, + output io_ic_access_fault_f, + output [1:0] io_ic_access_fault_type_f, + output io_iccm_rd_ecc_single_err, + output io_iccm_rd_ecc_double_err, + output io_ic_error_start, + output io_ifu_async_error_start, + output io_iccm_dma_sb_error, + output [1:0] io_ic_fetch_val_f, + output [31:0] io_ic_data_f, + output [63:0] io_ic_premux_data, + output io_ic_sel_premux_data, + input io_dec_tlu_core_ecc_disable, + output io_ifu_ic_debug_rd_data_valid, + output io_iccm_buf_correct_ecc, + output io_iccm_correction_state, + input io_scan_mode +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; + reg [31:0] _RAND_13; + reg [31:0] _RAND_14; + reg [31:0] _RAND_15; + reg [31:0] _RAND_16; + reg [31:0] _RAND_17; + reg [31:0] _RAND_18; + reg [31:0] _RAND_19; + reg [31:0] _RAND_20; + reg [31:0] _RAND_21; + reg [31:0] _RAND_22; + reg [31:0] _RAND_23; + reg [31:0] _RAND_24; + reg [31:0] _RAND_25; + reg [31:0] _RAND_26; + reg [31:0] _RAND_27; + reg [31:0] _RAND_28; + reg [31:0] _RAND_29; + reg [31:0] _RAND_30; + reg [31:0] _RAND_31; + reg [31:0] _RAND_32; + reg [31:0] _RAND_33; + reg [31:0] _RAND_34; + reg [31:0] _RAND_35; + reg [31:0] _RAND_36; + reg [31:0] _RAND_37; + reg [31:0] _RAND_38; + reg [31:0] _RAND_39; + reg [31:0] _RAND_40; + reg [31:0] _RAND_41; + reg [31:0] _RAND_42; + reg [31:0] _RAND_43; + reg [31:0] _RAND_44; + reg [31:0] _RAND_45; + reg [31:0] _RAND_46; + reg [31:0] _RAND_47; + reg [31:0] _RAND_48; + reg [31:0] _RAND_49; + reg [31:0] _RAND_50; + reg [31:0] _RAND_51; + reg [31:0] _RAND_52; + reg [31:0] _RAND_53; + reg [31:0] _RAND_54; + reg [31:0] _RAND_55; + reg [31:0] _RAND_56; + reg [31:0] _RAND_57; + reg [31:0] _RAND_58; + reg [31:0] _RAND_59; + reg [31:0] _RAND_60; + reg [31:0] _RAND_61; + reg [31:0] _RAND_62; + reg [31:0] _RAND_63; + reg [31:0] _RAND_64; + reg [31:0] _RAND_65; + reg [31:0] _RAND_66; + reg [31:0] _RAND_67; + reg [31:0] _RAND_68; + reg [31:0] _RAND_69; + reg [31:0] _RAND_70; + reg [31:0] _RAND_71; + reg [31:0] _RAND_72; + reg [31:0] _RAND_73; + reg [31:0] _RAND_74; + reg [31:0] _RAND_75; + reg [31:0] _RAND_76; + reg [31:0] _RAND_77; + reg [31:0] _RAND_78; + reg [31:0] _RAND_79; + reg [31:0] _RAND_80; + reg [31:0] _RAND_81; + reg [31:0] _RAND_82; + reg [31:0] _RAND_83; + reg [31:0] _RAND_84; + reg [31:0] _RAND_85; + reg [31:0] _RAND_86; + reg [31:0] _RAND_87; + reg [31:0] _RAND_88; + reg [31:0] _RAND_89; + reg [31:0] _RAND_90; + reg [31:0] _RAND_91; + reg [31:0] _RAND_92; + reg [31:0] _RAND_93; + reg [31:0] _RAND_94; + reg [31:0] _RAND_95; + reg [31:0] _RAND_96; + reg [31:0] _RAND_97; + reg [31:0] _RAND_98; + reg [31:0] _RAND_99; + reg [31:0] _RAND_100; + reg [31:0] _RAND_101; + reg [31:0] _RAND_102; + reg [31:0] _RAND_103; + reg [31:0] _RAND_104; + reg [31:0] _RAND_105; + reg [31:0] _RAND_106; + reg [31:0] _RAND_107; + reg [31:0] _RAND_108; + reg [31:0] _RAND_109; + reg [31:0] _RAND_110; + reg [31:0] _RAND_111; + reg [31:0] _RAND_112; + reg [31:0] _RAND_113; + reg [31:0] _RAND_114; + reg [31:0] _RAND_115; + reg [31:0] _RAND_116; + reg [31:0] _RAND_117; + reg [31:0] _RAND_118; + reg [31:0] _RAND_119; + reg [31:0] _RAND_120; + reg [31:0] _RAND_121; + reg [31:0] _RAND_122; + reg [31:0] _RAND_123; + reg [31:0] _RAND_124; + reg [31:0] _RAND_125; + reg [31:0] _RAND_126; + reg [31:0] _RAND_127; + reg [31:0] _RAND_128; + reg [31:0] _RAND_129; + reg [31:0] _RAND_130; + reg [31:0] _RAND_131; + reg [31:0] _RAND_132; + reg [31:0] _RAND_133; + reg [31:0] _RAND_134; + reg [31:0] _RAND_135; + reg [31:0] _RAND_136; + reg [31:0] _RAND_137; + reg [31:0] _RAND_138; + reg [31:0] _RAND_139; + reg [31:0] _RAND_140; + reg [31:0] _RAND_141; + reg [31:0] _RAND_142; + reg [31:0] _RAND_143; + reg [31:0] _RAND_144; + reg [31:0] _RAND_145; + reg [31:0] _RAND_146; + reg [31:0] _RAND_147; + reg [31:0] _RAND_148; + reg [31:0] _RAND_149; + reg [31:0] _RAND_150; + reg [31:0] _RAND_151; + reg [31:0] _RAND_152; + reg [31:0] _RAND_153; + reg [31:0] _RAND_154; + reg [31:0] _RAND_155; + reg [31:0] _RAND_156; + reg [31:0] _RAND_157; + reg [31:0] _RAND_158; + reg [31:0] _RAND_159; + reg [31:0] _RAND_160; + reg [31:0] _RAND_161; + reg [31:0] _RAND_162; + reg [31:0] _RAND_163; + reg [63:0] _RAND_164; + reg [31:0] _RAND_165; + reg [31:0] _RAND_166; + reg [31:0] _RAND_167; + reg [31:0] _RAND_168; + reg [31:0] _RAND_169; + reg [31:0] _RAND_170; + reg [31:0] _RAND_171; + reg [31:0] _RAND_172; + reg [31:0] _RAND_173; + reg [31:0] _RAND_174; + reg [31:0] _RAND_175; + reg [31:0] _RAND_176; + reg [31:0] _RAND_177; + reg [31:0] _RAND_178; + reg [31:0] _RAND_179; + reg [31:0] _RAND_180; + reg [31:0] _RAND_181; + reg [31:0] _RAND_182; + reg [31:0] _RAND_183; + reg [31:0] _RAND_184; + reg [31:0] _RAND_185; + reg [31:0] _RAND_186; + reg [31:0] _RAND_187; + reg [31:0] _RAND_188; + reg [31:0] _RAND_189; + reg [31:0] _RAND_190; + reg [31:0] _RAND_191; + reg [31:0] _RAND_192; + reg [31:0] _RAND_193; + reg [31:0] _RAND_194; + reg [31:0] _RAND_195; + reg [31:0] _RAND_196; + reg [31:0] _RAND_197; + reg [31:0] _RAND_198; + reg [31:0] _RAND_199; + reg [31:0] _RAND_200; + reg [31:0] _RAND_201; + reg [31:0] _RAND_202; + reg [31:0] _RAND_203; + reg [31:0] _RAND_204; + reg [31:0] _RAND_205; + reg [31:0] _RAND_206; + reg [31:0] _RAND_207; + reg [31:0] _RAND_208; + reg [31:0] _RAND_209; + reg [31:0] _RAND_210; + reg [31:0] _RAND_211; + reg [31:0] _RAND_212; + reg [31:0] _RAND_213; + reg [31:0] _RAND_214; + reg [31:0] _RAND_215; + reg [31:0] _RAND_216; + reg [31:0] _RAND_217; + reg [31:0] _RAND_218; + reg [31:0] _RAND_219; + reg [31:0] _RAND_220; + reg [31:0] _RAND_221; + reg [31:0] _RAND_222; + reg [31:0] _RAND_223; + reg [31:0] _RAND_224; + reg [31:0] _RAND_225; + reg [31:0] _RAND_226; + reg [31:0] _RAND_227; + reg [31:0] _RAND_228; + reg [31:0] _RAND_229; + reg [31:0] _RAND_230; + reg [31:0] _RAND_231; + reg [31:0] _RAND_232; + reg [31:0] _RAND_233; + reg [31:0] _RAND_234; + reg [31:0] _RAND_235; + reg [31:0] _RAND_236; + reg [31:0] _RAND_237; + reg [31:0] _RAND_238; + reg [31:0] _RAND_239; + reg [31:0] _RAND_240; + reg [31:0] _RAND_241; + reg [31:0] _RAND_242; + reg [31:0] _RAND_243; + reg [31:0] _RAND_244; + reg [31:0] _RAND_245; + reg [31:0] _RAND_246; + reg [31:0] _RAND_247; + reg [31:0] _RAND_248; + reg [31:0] _RAND_249; + reg [31:0] _RAND_250; + reg [31:0] _RAND_251; + reg [31:0] _RAND_252; + reg [31:0] _RAND_253; + reg [31:0] _RAND_254; + reg [31:0] _RAND_255; + reg [31:0] _RAND_256; + reg [31:0] _RAND_257; + reg [31:0] _RAND_258; + reg [31:0] _RAND_259; + reg [31:0] _RAND_260; + reg [31:0] _RAND_261; + reg [31:0] _RAND_262; + reg [31:0] _RAND_263; + reg [31:0] _RAND_264; + reg [31:0] _RAND_265; + reg [31:0] _RAND_266; + reg [31:0] _RAND_267; + reg [31:0] _RAND_268; + reg [31:0] _RAND_269; + reg [31:0] _RAND_270; + reg [31:0] _RAND_271; + reg [31:0] _RAND_272; + reg [31:0] _RAND_273; + reg [31:0] _RAND_274; + reg [31:0] _RAND_275; + reg [31:0] _RAND_276; + reg [31:0] _RAND_277; + reg [31:0] _RAND_278; + reg [31:0] _RAND_279; + reg [31:0] _RAND_280; + reg [31:0] _RAND_281; + reg [31:0] _RAND_282; + reg [31:0] _RAND_283; + reg [31:0] _RAND_284; + reg [31:0] _RAND_285; + reg [31:0] _RAND_286; + reg [31:0] _RAND_287; + reg [31:0] _RAND_288; + reg [31:0] _RAND_289; + reg [31:0] _RAND_290; + reg [31:0] _RAND_291; + reg [31:0] _RAND_292; + reg [31:0] _RAND_293; + reg [31:0] _RAND_294; + reg [31:0] _RAND_295; + reg [31:0] _RAND_296; + reg [31:0] _RAND_297; + reg [31:0] _RAND_298; + reg [31:0] _RAND_299; + reg [31:0] _RAND_300; + reg [31:0] _RAND_301; + reg [31:0] _RAND_302; + reg [31:0] _RAND_303; + reg [31:0] _RAND_304; + reg [31:0] _RAND_305; + reg [31:0] _RAND_306; + reg [31:0] _RAND_307; + reg [31:0] _RAND_308; + reg [31:0] _RAND_309; + reg [31:0] _RAND_310; + reg [31:0] _RAND_311; + reg [31:0] _RAND_312; + reg [31:0] _RAND_313; + reg [31:0] _RAND_314; + reg [31:0] _RAND_315; + reg [31:0] _RAND_316; + reg [31:0] _RAND_317; + reg [31:0] _RAND_318; + reg [31:0] _RAND_319; + reg [31:0] _RAND_320; + reg [31:0] _RAND_321; + reg [31:0] _RAND_322; + reg [31:0] _RAND_323; + reg [31:0] _RAND_324; + reg [31:0] _RAND_325; + reg [31:0] _RAND_326; + reg [31:0] _RAND_327; + reg [31:0] _RAND_328; + reg [31:0] _RAND_329; + reg [31:0] _RAND_330; + reg [31:0] _RAND_331; + reg [31:0] _RAND_332; + reg [31:0] _RAND_333; + reg [31:0] _RAND_334; + reg [31:0] _RAND_335; + reg [31:0] _RAND_336; + reg [31:0] _RAND_337; + reg [31:0] _RAND_338; + reg [31:0] _RAND_339; + reg [31:0] _RAND_340; + reg [31:0] _RAND_341; + reg [31:0] _RAND_342; + reg [31:0] _RAND_343; + reg [31:0] _RAND_344; + reg [31:0] _RAND_345; + reg [31:0] _RAND_346; + reg [31:0] _RAND_347; + reg [31:0] _RAND_348; + reg [31:0] _RAND_349; + reg [31:0] _RAND_350; + reg [31:0] _RAND_351; + reg [31:0] _RAND_352; + reg [31:0] _RAND_353; + reg [31:0] _RAND_354; + reg [31:0] _RAND_355; + reg [31:0] _RAND_356; + reg [31:0] _RAND_357; + reg [31:0] _RAND_358; + reg [31:0] _RAND_359; + reg [31:0] _RAND_360; + reg [31:0] _RAND_361; + reg [31:0] _RAND_362; + reg [31:0] _RAND_363; + reg [31:0] _RAND_364; + reg [31:0] _RAND_365; + reg [31:0] _RAND_366; + reg [31:0] _RAND_367; + reg [31:0] _RAND_368; + reg [31:0] _RAND_369; + reg [31:0] _RAND_370; + reg [31:0] _RAND_371; + reg [31:0] _RAND_372; + reg [31:0] _RAND_373; + reg [31:0] _RAND_374; + reg [31:0] _RAND_375; + reg [31:0] _RAND_376; + reg [31:0] _RAND_377; + reg [31:0] _RAND_378; + reg [31:0] _RAND_379; + reg [31:0] _RAND_380; + reg [31:0] _RAND_381; + reg [31:0] _RAND_382; + reg [31:0] _RAND_383; + reg [31:0] _RAND_384; + reg [31:0] _RAND_385; + reg [31:0] _RAND_386; + reg [31:0] _RAND_387; + reg [31:0] _RAND_388; + reg [31:0] _RAND_389; + reg [31:0] _RAND_390; + reg [31:0] _RAND_391; + reg [31:0] _RAND_392; + reg [31:0] _RAND_393; + reg [31:0] _RAND_394; + reg [31:0] _RAND_395; + reg [31:0] _RAND_396; + reg [31:0] _RAND_397; + reg [31:0] _RAND_398; + reg [31:0] _RAND_399; + reg [31:0] _RAND_400; + reg [31:0] _RAND_401; + reg [31:0] _RAND_402; + reg [31:0] _RAND_403; + reg [31:0] _RAND_404; + reg [31:0] _RAND_405; + reg [31:0] _RAND_406; + reg [31:0] _RAND_407; + reg [31:0] _RAND_408; + reg [31:0] _RAND_409; + reg [31:0] _RAND_410; + reg [31:0] _RAND_411; + reg [31:0] _RAND_412; + reg [31:0] _RAND_413; + reg [31:0] _RAND_414; + reg [31:0] _RAND_415; + reg [31:0] _RAND_416; + reg [31:0] _RAND_417; + reg [31:0] _RAND_418; + reg [31:0] _RAND_419; + reg [31:0] _RAND_420; + reg [31:0] _RAND_421; + reg [31:0] _RAND_422; + reg [31:0] _RAND_423; + reg [31:0] _RAND_424; + reg [31:0] _RAND_425; + reg [31:0] _RAND_426; + reg [31:0] _RAND_427; + reg [31:0] _RAND_428; + reg [31:0] _RAND_429; + reg [31:0] _RAND_430; + reg [31:0] _RAND_431; + reg [31:0] _RAND_432; + reg [31:0] _RAND_433; + reg [31:0] _RAND_434; + reg [31:0] _RAND_435; + reg [31:0] _RAND_436; + reg [31:0] _RAND_437; + reg [31:0] _RAND_438; + reg [31:0] _RAND_439; + reg [31:0] _RAND_440; + reg [31:0] _RAND_441; + reg [95:0] _RAND_442; + reg [31:0] _RAND_443; + reg [31:0] _RAND_444; + reg [31:0] _RAND_445; + reg [31:0] _RAND_446; + reg [31:0] _RAND_447; + reg [31:0] _RAND_448; + reg [31:0] _RAND_449; + reg [31:0] _RAND_450; + reg [31:0] _RAND_451; + reg [63:0] _RAND_452; + reg [31:0] _RAND_453; + reg [31:0] _RAND_454; + reg [31:0] _RAND_455; + reg [31:0] _RAND_456; + reg [31:0] _RAND_457; + reg [63:0] _RAND_458; + reg [31:0] _RAND_459; + reg [31:0] _RAND_460; + reg [31:0] _RAND_461; + reg [31:0] _RAND_462; + reg [31:0] _RAND_463; + reg [31:0] _RAND_464; + reg [31:0] _RAND_465; + reg [31:0] _RAND_466; + reg [31:0] _RAND_467; + reg [31:0] _RAND_468; + reg [31:0] _RAND_469; + reg [31:0] _RAND_470; + reg [31:0] _RAND_471; + reg [31:0] _RAND_472; +`endif // RANDOMIZE_REG_INIT + wire rvclkhdr_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_1_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_1_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_2_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_2_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_3_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_3_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_4_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_4_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_5_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_5_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_6_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_6_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_6_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_6_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_7_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_7_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_7_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_7_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_8_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_8_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_8_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_8_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_9_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_9_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_9_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_10_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_10_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_10_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_10_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_11_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_11_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_11_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_11_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_12_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_12_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_12_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_12_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_13_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_13_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_13_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_13_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_14_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_14_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_14_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_14_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_15_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_15_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_15_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_15_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_16_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_16_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_16_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_16_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_17_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_17_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_17_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_17_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_18_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_18_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_18_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_18_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_19_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_19_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_19_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_19_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_20_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_20_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_20_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_20_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_21_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_21_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_21_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_21_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_22_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_22_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_22_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_22_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_23_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_23_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_23_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_23_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_24_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_24_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_24_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_24_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_25_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_25_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_25_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_25_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_26_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_26_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_26_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_26_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_27_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_27_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_27_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_27_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_28_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_28_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_28_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_28_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_29_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_29_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_29_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_29_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_30_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_30_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_30_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_30_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_31_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_31_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_31_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_31_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_32_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_32_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_32_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_32_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_33_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_33_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_33_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_33_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_34_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_34_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_34_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_34_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_35_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_35_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_35_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_35_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_36_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_36_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_36_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_36_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_37_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_37_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_37_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_37_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_38_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_38_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_38_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_38_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_39_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_39_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_39_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_39_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_40_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_40_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_40_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_40_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_41_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_41_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_41_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_41_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_42_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_42_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_42_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_42_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_43_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_43_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_43_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_43_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_44_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_44_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_44_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_44_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_45_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_45_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_45_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_45_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_46_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_46_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_46_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_46_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_47_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_47_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_47_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_47_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_48_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_48_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_48_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_48_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_49_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_49_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_49_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_49_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_50_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_50_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_50_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_50_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_51_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_51_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_51_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_51_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_52_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_52_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_52_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_52_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_53_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_53_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_53_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_53_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_54_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_54_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_54_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_54_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_55_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_55_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_55_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_55_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_56_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_56_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_56_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_56_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_57_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_57_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_57_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_57_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_58_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_58_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_58_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_58_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_59_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_59_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_59_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_59_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_60_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_60_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_60_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_60_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_61_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_61_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_61_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_61_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_62_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_62_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_62_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_62_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_63_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_63_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_63_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_63_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_64_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_64_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_64_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_64_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_65_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_65_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_65_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_65_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_66_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_66_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_66_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_66_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_67_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_67_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_67_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_67_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_68_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_68_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_68_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_68_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_69_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_69_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_69_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_69_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_70_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_70_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_70_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_70_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_71_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_71_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_71_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_71_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_72_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_72_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_72_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_72_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_73_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_73_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_73_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_73_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_74_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_74_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_74_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_74_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_75_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_75_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_75_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_75_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_76_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_76_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_76_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_76_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_77_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_77_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_77_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_77_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_78_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_78_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_78_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_78_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_79_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_79_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_79_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_79_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_80_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_80_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_80_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_80_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_81_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_81_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_81_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_81_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_82_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_82_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_82_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_82_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_83_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_83_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_83_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_83_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_84_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_84_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_84_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_84_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_85_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_85_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_85_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_85_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_86_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_86_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_86_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_86_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_87_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_87_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_87_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_87_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_88_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_88_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_88_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_88_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_89_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_89_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_89_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_89_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_90_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_90_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_90_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_90_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_91_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_91_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_91_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_91_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_92_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_92_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_92_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_92_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_93_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_93_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_93_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_93_io_scan_mode; // @[el2_lib.scala 483:22] + reg flush_final_f; // @[el2_ifu_mem_ctl.scala 186:53] + reg ifc_fetch_req_f_raw; // @[el2_ifu_mem_ctl.scala 322:61] + wire _T_319 = ~io_exu_flush_final; // @[el2_ifu_mem_ctl.scala 323:44] + wire ifc_fetch_req_f = ifc_fetch_req_f_raw & _T_319; // @[el2_ifu_mem_ctl.scala 323:42] + wire _T = io_ifc_fetch_req_bf_raw | ifc_fetch_req_f; // @[el2_ifu_mem_ctl.scala 187:53] + reg [2:0] miss_state; // @[Reg.scala 27:20] + wire miss_pending = miss_state != 3'h0; // @[el2_ifu_mem_ctl.scala 254:30] + wire _T_1 = _T | miss_pending; // @[el2_ifu_mem_ctl.scala 187:71] + wire _T_2 = _T_1 | io_exu_flush_final; // @[el2_ifu_mem_ctl.scala 187:86] + reg scnd_miss_req_q; // @[el2_ifu_mem_ctl.scala 552:52] + wire scnd_miss_req = scnd_miss_req_q & _T_319; // @[el2_ifu_mem_ctl.scala 554:36] + wire debug_c1_clken = io_ic_debug_rd_en | io_ic_debug_wr_en; // @[el2_ifu_mem_ctl.scala 188:42] + wire [3:0] ic_fetch_val_int_f = {2'h0,io_ic_fetch_val_f}; // @[Cat.scala 29:58] + reg [30:0] ifu_fetch_addr_int_f; // @[el2_ifu_mem_ctl.scala 309:63] + wire [4:0] _GEN_437 = {{1'd0}, ic_fetch_val_int_f}; // @[el2_ifu_mem_ctl.scala 670:53] + wire [4:0] ic_fetch_val_shift_right = _GEN_437 << ifu_fetch_addr_int_f[0]; // @[el2_ifu_mem_ctl.scala 670:53] + wire [1:0] _GEN_438 = {{1'd0}, _T_319}; // @[el2_ifu_mem_ctl.scala 673:91] + wire [1:0] _T_3080 = ic_fetch_val_shift_right[3:2] & _GEN_438; // @[el2_ifu_mem_ctl.scala 673:91] + reg ifc_iccm_access_f; // @[el2_ifu_mem_ctl.scala 324:60] + wire fetch_req_iccm_f = ifc_fetch_req_f & ifc_iccm_access_f; // @[el2_ifu_mem_ctl.scala 276:46] + wire [1:0] _GEN_439 = {{1'd0}, fetch_req_iccm_f}; // @[el2_ifu_mem_ctl.scala 673:113] + wire [1:0] _T_3081 = _T_3080 & _GEN_439; // @[el2_ifu_mem_ctl.scala 673:113] + reg iccm_dma_rvalid_in; // @[el2_ifu_mem_ctl.scala 659:59] + wire [1:0] _GEN_440 = {{1'd0}, iccm_dma_rvalid_in}; // @[el2_ifu_mem_ctl.scala 673:130] + wire [1:0] _T_3082 = _T_3081 | _GEN_440; // @[el2_ifu_mem_ctl.scala 673:130] + wire _T_3083 = ~io_dec_tlu_core_ecc_disable; // @[el2_ifu_mem_ctl.scala 673:154] + wire [1:0] _GEN_441 = {{1'd0}, _T_3083}; // @[el2_ifu_mem_ctl.scala 673:152] + wire [1:0] _T_3084 = _T_3082 & _GEN_441; // @[el2_ifu_mem_ctl.scala 673:152] + wire [1:0] _T_3073 = ic_fetch_val_shift_right[1:0] & _GEN_438; // @[el2_ifu_mem_ctl.scala 673:91] + wire [1:0] _T_3074 = _T_3073 & _GEN_439; // @[el2_ifu_mem_ctl.scala 673:113] + wire [1:0] _T_3075 = _T_3074 | _GEN_440; // @[el2_ifu_mem_ctl.scala 673:130] + wire [1:0] _T_3077 = _T_3075 & _GEN_441; // @[el2_ifu_mem_ctl.scala 673:152] + wire [3:0] iccm_ecc_word_enable = {_T_3084,_T_3077}; // @[Cat.scala 29:58] + wire _T_3184 = ^io_iccm_rd_data_ecc[31:0]; // @[el2_lib.scala 333:30] + wire _T_3185 = ^io_iccm_rd_data_ecc[38:32]; // @[el2_lib.scala 333:44] + wire _T_3186 = _T_3184 ^ _T_3185; // @[el2_lib.scala 333:35] + wire [5:0] _T_3194 = {io_iccm_rd_data_ecc[31],io_iccm_rd_data_ecc[30],io_iccm_rd_data_ecc[29],io_iccm_rd_data_ecc[28],io_iccm_rd_data_ecc[27],io_iccm_rd_data_ecc[26]}; // @[el2_lib.scala 333:76] + wire _T_3195 = ^_T_3194; // @[el2_lib.scala 333:83] + wire _T_3196 = io_iccm_rd_data_ecc[37] ^ _T_3195; // @[el2_lib.scala 333:71] + wire [6:0] _T_3203 = {io_iccm_rd_data_ecc[17],io_iccm_rd_data_ecc[16],io_iccm_rd_data_ecc[15],io_iccm_rd_data_ecc[14],io_iccm_rd_data_ecc[13],io_iccm_rd_data_ecc[12],io_iccm_rd_data_ecc[11]}; // @[el2_lib.scala 333:103] + wire [14:0] _T_3211 = {io_iccm_rd_data_ecc[25],io_iccm_rd_data_ecc[24],io_iccm_rd_data_ecc[23],io_iccm_rd_data_ecc[22],io_iccm_rd_data_ecc[21],io_iccm_rd_data_ecc[20],io_iccm_rd_data_ecc[19],io_iccm_rd_data_ecc[18],_T_3203}; // @[el2_lib.scala 333:103] + wire _T_3212 = ^_T_3211; // @[el2_lib.scala 333:110] + wire _T_3213 = io_iccm_rd_data_ecc[36] ^ _T_3212; // @[el2_lib.scala 333:98] + wire [6:0] _T_3220 = {io_iccm_rd_data_ecc[10],io_iccm_rd_data_ecc[9],io_iccm_rd_data_ecc[8],io_iccm_rd_data_ecc[7],io_iccm_rd_data_ecc[6],io_iccm_rd_data_ecc[5],io_iccm_rd_data_ecc[4]}; // @[el2_lib.scala 333:130] + wire [14:0] _T_3228 = {io_iccm_rd_data_ecc[25],io_iccm_rd_data_ecc[24],io_iccm_rd_data_ecc[23],io_iccm_rd_data_ecc[22],io_iccm_rd_data_ecc[21],io_iccm_rd_data_ecc[20],io_iccm_rd_data_ecc[19],io_iccm_rd_data_ecc[18],_T_3220}; // @[el2_lib.scala 333:130] + wire _T_3229 = ^_T_3228; // @[el2_lib.scala 333:137] + wire _T_3230 = io_iccm_rd_data_ecc[35] ^ _T_3229; // @[el2_lib.scala 333:125] + wire [8:0] _T_3239 = {io_iccm_rd_data_ecc[15],io_iccm_rd_data_ecc[14],io_iccm_rd_data_ecc[10],io_iccm_rd_data_ecc[9],io_iccm_rd_data_ecc[8],io_iccm_rd_data_ecc[7],io_iccm_rd_data_ecc[3],io_iccm_rd_data_ecc[2],io_iccm_rd_data_ecc[1]}; // @[el2_lib.scala 333:157] + wire [17:0] _T_3248 = {io_iccm_rd_data_ecc[31],io_iccm_rd_data_ecc[30],io_iccm_rd_data_ecc[29],io_iccm_rd_data_ecc[25],io_iccm_rd_data_ecc[24],io_iccm_rd_data_ecc[23],io_iccm_rd_data_ecc[22],io_iccm_rd_data_ecc[17],io_iccm_rd_data_ecc[16],_T_3239}; // @[el2_lib.scala 333:157] + wire _T_3249 = ^_T_3248; // @[el2_lib.scala 333:164] + wire _T_3250 = io_iccm_rd_data_ecc[34] ^ _T_3249; // @[el2_lib.scala 333:152] + wire [8:0] _T_3259 = {io_iccm_rd_data_ecc[13],io_iccm_rd_data_ecc[12],io_iccm_rd_data_ecc[10],io_iccm_rd_data_ecc[9],io_iccm_rd_data_ecc[6],io_iccm_rd_data_ecc[5],io_iccm_rd_data_ecc[3],io_iccm_rd_data_ecc[2],io_iccm_rd_data_ecc[0]}; // @[el2_lib.scala 333:184] + wire [17:0] _T_3268 = {io_iccm_rd_data_ecc[31],io_iccm_rd_data_ecc[28],io_iccm_rd_data_ecc[27],io_iccm_rd_data_ecc[25],io_iccm_rd_data_ecc[24],io_iccm_rd_data_ecc[21],io_iccm_rd_data_ecc[20],io_iccm_rd_data_ecc[17],io_iccm_rd_data_ecc[16],_T_3259}; // @[el2_lib.scala 333:184] + wire _T_3269 = ^_T_3268; // @[el2_lib.scala 333:191] + wire _T_3270 = io_iccm_rd_data_ecc[33] ^ _T_3269; // @[el2_lib.scala 333:179] + wire [8:0] _T_3279 = {io_iccm_rd_data_ecc[13],io_iccm_rd_data_ecc[11],io_iccm_rd_data_ecc[10],io_iccm_rd_data_ecc[8],io_iccm_rd_data_ecc[6],io_iccm_rd_data_ecc[4],io_iccm_rd_data_ecc[3],io_iccm_rd_data_ecc[1],io_iccm_rd_data_ecc[0]}; // @[el2_lib.scala 333:211] + wire [17:0] _T_3288 = {io_iccm_rd_data_ecc[30],io_iccm_rd_data_ecc[28],io_iccm_rd_data_ecc[26],io_iccm_rd_data_ecc[25],io_iccm_rd_data_ecc[23],io_iccm_rd_data_ecc[21],io_iccm_rd_data_ecc[19],io_iccm_rd_data_ecc[17],io_iccm_rd_data_ecc[15],_T_3279}; // @[el2_lib.scala 333:211] + wire _T_3289 = ^_T_3288; // @[el2_lib.scala 333:218] + wire _T_3290 = io_iccm_rd_data_ecc[32] ^ _T_3289; // @[el2_lib.scala 333:206] + wire [6:0] _T_3296 = {_T_3186,_T_3196,_T_3213,_T_3230,_T_3250,_T_3270,_T_3290}; // @[Cat.scala 29:58] + wire _T_3297 = _T_3296 != 7'h0; // @[el2_lib.scala 334:44] + wire _T_3298 = iccm_ecc_word_enable[0] & _T_3297; // @[el2_lib.scala 334:32] + wire _T_3300 = _T_3298 & _T_3296[6]; // @[el2_lib.scala 334:53] + wire _T_3569 = ^io_iccm_rd_data_ecc[70:39]; // @[el2_lib.scala 333:30] + wire _T_3570 = ^io_iccm_rd_data_ecc[77:71]; // @[el2_lib.scala 333:44] + wire _T_3571 = _T_3569 ^ _T_3570; // @[el2_lib.scala 333:35] + wire [5:0] _T_3579 = {io_iccm_rd_data_ecc[70],io_iccm_rd_data_ecc[69],io_iccm_rd_data_ecc[68],io_iccm_rd_data_ecc[67],io_iccm_rd_data_ecc[66],io_iccm_rd_data_ecc[65]}; // @[el2_lib.scala 333:76] + wire _T_3580 = ^_T_3579; // @[el2_lib.scala 333:83] + wire _T_3581 = io_iccm_rd_data_ecc[76] ^ _T_3580; // @[el2_lib.scala 333:71] + wire [6:0] _T_3588 = {io_iccm_rd_data_ecc[56],io_iccm_rd_data_ecc[55],io_iccm_rd_data_ecc[54],io_iccm_rd_data_ecc[53],io_iccm_rd_data_ecc[52],io_iccm_rd_data_ecc[51],io_iccm_rd_data_ecc[50]}; // @[el2_lib.scala 333:103] + wire [14:0] _T_3596 = {io_iccm_rd_data_ecc[64],io_iccm_rd_data_ecc[63],io_iccm_rd_data_ecc[62],io_iccm_rd_data_ecc[61],io_iccm_rd_data_ecc[60],io_iccm_rd_data_ecc[59],io_iccm_rd_data_ecc[58],io_iccm_rd_data_ecc[57],_T_3588}; // @[el2_lib.scala 333:103] + wire _T_3597 = ^_T_3596; // @[el2_lib.scala 333:110] + wire _T_3598 = io_iccm_rd_data_ecc[75] ^ _T_3597; // @[el2_lib.scala 333:98] + wire [6:0] _T_3605 = {io_iccm_rd_data_ecc[49],io_iccm_rd_data_ecc[48],io_iccm_rd_data_ecc[47],io_iccm_rd_data_ecc[46],io_iccm_rd_data_ecc[45],io_iccm_rd_data_ecc[44],io_iccm_rd_data_ecc[43]}; // @[el2_lib.scala 333:130] + wire [14:0] _T_3613 = {io_iccm_rd_data_ecc[64],io_iccm_rd_data_ecc[63],io_iccm_rd_data_ecc[62],io_iccm_rd_data_ecc[61],io_iccm_rd_data_ecc[60],io_iccm_rd_data_ecc[59],io_iccm_rd_data_ecc[58],io_iccm_rd_data_ecc[57],_T_3605}; // @[el2_lib.scala 333:130] + wire _T_3614 = ^_T_3613; // @[el2_lib.scala 333:137] + wire _T_3615 = io_iccm_rd_data_ecc[74] ^ _T_3614; // @[el2_lib.scala 333:125] + wire [8:0] _T_3624 = {io_iccm_rd_data_ecc[54],io_iccm_rd_data_ecc[53],io_iccm_rd_data_ecc[49],io_iccm_rd_data_ecc[48],io_iccm_rd_data_ecc[47],io_iccm_rd_data_ecc[46],io_iccm_rd_data_ecc[42],io_iccm_rd_data_ecc[41],io_iccm_rd_data_ecc[40]}; // @[el2_lib.scala 333:157] + wire [17:0] _T_3633 = {io_iccm_rd_data_ecc[70],io_iccm_rd_data_ecc[69],io_iccm_rd_data_ecc[68],io_iccm_rd_data_ecc[64],io_iccm_rd_data_ecc[63],io_iccm_rd_data_ecc[62],io_iccm_rd_data_ecc[61],io_iccm_rd_data_ecc[56],io_iccm_rd_data_ecc[55],_T_3624}; // @[el2_lib.scala 333:157] + wire _T_3634 = ^_T_3633; // @[el2_lib.scala 333:164] + wire _T_3635 = io_iccm_rd_data_ecc[73] ^ _T_3634; // @[el2_lib.scala 333:152] + wire [8:0] _T_3644 = {io_iccm_rd_data_ecc[52],io_iccm_rd_data_ecc[51],io_iccm_rd_data_ecc[49],io_iccm_rd_data_ecc[48],io_iccm_rd_data_ecc[45],io_iccm_rd_data_ecc[44],io_iccm_rd_data_ecc[42],io_iccm_rd_data_ecc[41],io_iccm_rd_data_ecc[39]}; // @[el2_lib.scala 333:184] + wire [17:0] _T_3653 = {io_iccm_rd_data_ecc[70],io_iccm_rd_data_ecc[67],io_iccm_rd_data_ecc[66],io_iccm_rd_data_ecc[64],io_iccm_rd_data_ecc[63],io_iccm_rd_data_ecc[60],io_iccm_rd_data_ecc[59],io_iccm_rd_data_ecc[56],io_iccm_rd_data_ecc[55],_T_3644}; // @[el2_lib.scala 333:184] + wire _T_3654 = ^_T_3653; // @[el2_lib.scala 333:191] + wire _T_3655 = io_iccm_rd_data_ecc[72] ^ _T_3654; // @[el2_lib.scala 333:179] + wire [8:0] _T_3664 = {io_iccm_rd_data_ecc[52],io_iccm_rd_data_ecc[50],io_iccm_rd_data_ecc[49],io_iccm_rd_data_ecc[47],io_iccm_rd_data_ecc[45],io_iccm_rd_data_ecc[43],io_iccm_rd_data_ecc[42],io_iccm_rd_data_ecc[40],io_iccm_rd_data_ecc[39]}; // @[el2_lib.scala 333:211] + wire [17:0] _T_3673 = {io_iccm_rd_data_ecc[69],io_iccm_rd_data_ecc[67],io_iccm_rd_data_ecc[65],io_iccm_rd_data_ecc[64],io_iccm_rd_data_ecc[62],io_iccm_rd_data_ecc[60],io_iccm_rd_data_ecc[58],io_iccm_rd_data_ecc[56],io_iccm_rd_data_ecc[54],_T_3664}; // @[el2_lib.scala 333:211] + wire _T_3674 = ^_T_3673; // @[el2_lib.scala 333:218] + wire _T_3675 = io_iccm_rd_data_ecc[71] ^ _T_3674; // @[el2_lib.scala 333:206] + wire [6:0] _T_3681 = {_T_3571,_T_3581,_T_3598,_T_3615,_T_3635,_T_3655,_T_3675}; // @[Cat.scala 29:58] + wire _T_3682 = _T_3681 != 7'h0; // @[el2_lib.scala 334:44] + wire _T_3683 = iccm_ecc_word_enable[1] & _T_3682; // @[el2_lib.scala 334:32] + wire _T_3685 = _T_3683 & _T_3681[6]; // @[el2_lib.scala 334:53] + wire [1:0] iccm_single_ecc_error = {_T_3300,_T_3685}; // @[Cat.scala 29:58] + wire _T_3 = |iccm_single_ecc_error; // @[el2_ifu_mem_ctl.scala 191:52] + reg dma_iccm_req_f; // @[el2_ifu_mem_ctl.scala 636:51] + wire _T_6 = io_iccm_rd_ecc_single_err | io_ic_error_start; // @[el2_ifu_mem_ctl.scala 192:57] + reg [2:0] perr_state; // @[Reg.scala 27:20] + wire _T_7 = perr_state == 3'h4; // @[el2_ifu_mem_ctl.scala 193:54] + wire iccm_correct_ecc = perr_state == 3'h3; // @[el2_ifu_mem_ctl.scala 479:34] + wire _T_8 = iccm_correct_ecc | _T_7; // @[el2_ifu_mem_ctl.scala 193:40] + reg [1:0] err_stop_state; // @[Reg.scala 27:20] + wire _T_9 = err_stop_state == 2'h3; // @[el2_ifu_mem_ctl.scala 193:90] + wire _T_10 = _T_8 | _T_9; // @[el2_ifu_mem_ctl.scala 193:72] + wire _T_2477 = 2'h0 == err_stop_state; // @[Conditional.scala 37:30] + wire _T_2482 = 2'h1 == err_stop_state; // @[Conditional.scala 37:30] + wire _T_2502 = io_ifu_fetch_val == 2'h3; // @[el2_ifu_mem_ctl.scala 529:48] + wire two_byte_instr = io_ic_data_f[1:0] != 2'h3; // @[el2_ifu_mem_ctl.scala 392:42] + wire _T_2504 = io_ifu_fetch_val[0] & two_byte_instr; // @[el2_ifu_mem_ctl.scala 529:79] + wire _T_2505 = _T_2502 | _T_2504; // @[el2_ifu_mem_ctl.scala 529:56] + wire _T_2506 = io_exu_flush_final | io_dec_tlu_i0_commit_cmt; // @[el2_ifu_mem_ctl.scala 529:122] + wire _T_2507 = ~_T_2506; // @[el2_ifu_mem_ctl.scala 529:101] + wire _T_2508 = _T_2505 & _T_2507; // @[el2_ifu_mem_ctl.scala 529:99] + wire _T_2509 = 2'h2 == err_stop_state; // @[Conditional.scala 37:30] + wire _T_2523 = io_ifu_fetch_val[0] & _T_319; // @[el2_ifu_mem_ctl.scala 536:45] + wire _T_2524 = ~io_dec_tlu_i0_commit_cmt; // @[el2_ifu_mem_ctl.scala 536:69] + wire _T_2525 = _T_2523 & _T_2524; // @[el2_ifu_mem_ctl.scala 536:67] + wire _T_2526 = 2'h3 == err_stop_state; // @[Conditional.scala 37:30] + wire _GEN_38 = _T_2509 ? _T_2525 : _T_2526; // @[Conditional.scala 39:67] + wire _GEN_42 = _T_2482 ? _T_2508 : _GEN_38; // @[Conditional.scala 39:67] + wire err_stop_fetch = _T_2477 ? 1'h0 : _GEN_42; // @[Conditional.scala 40:58] + wire _T_11 = _T_10 | err_stop_fetch; // @[el2_ifu_mem_ctl.scala 193:112] + wire _T_13 = io_ifu_axi_rvalid & io_ifu_bus_clk_en; // @[el2_ifu_mem_ctl.scala 195:44] + wire _T_14 = _T_13 & io_ifu_axi_rready; // @[el2_ifu_mem_ctl.scala 195:65] + wire _T_227 = |io_ic_rd_hit; // @[el2_ifu_mem_ctl.scala 284:37] + wire _T_228 = ~_T_227; // @[el2_ifu_mem_ctl.scala 284:23] + reg reset_all_tags; // @[el2_ifu_mem_ctl.scala 705:53] + wire _T_229 = _T_228 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 284:41] + wire _T_207 = ~ifc_iccm_access_f; // @[el2_ifu_mem_ctl.scala 275:48] + wire _T_208 = ifc_fetch_req_f & _T_207; // @[el2_ifu_mem_ctl.scala 275:46] + reg ifc_region_acc_fault_final_f; // @[el2_ifu_mem_ctl.scala 326:71] + wire _T_209 = ~ifc_region_acc_fault_final_f; // @[el2_ifu_mem_ctl.scala 275:69] + wire fetch_req_icache_f = _T_208 & _T_209; // @[el2_ifu_mem_ctl.scala 275:67] + wire _T_230 = _T_229 & fetch_req_icache_f; // @[el2_ifu_mem_ctl.scala 284:59] + wire _T_231 = ~miss_pending; // @[el2_ifu_mem_ctl.scala 284:82] + wire _T_232 = _T_230 & _T_231; // @[el2_ifu_mem_ctl.scala 284:80] + wire _T_233 = _T_232 | scnd_miss_req; // @[el2_ifu_mem_ctl.scala 284:97] + wire ic_act_miss_f = _T_233 & _T_209; // @[el2_ifu_mem_ctl.scala 284:114] + reg ifu_bus_rvalid_unq_ff; // @[el2_ifu_mem_ctl.scala 579:56] + reg bus_ifu_bus_clk_en_ff; // @[el2_ifu_mem_ctl.scala 551:61] + wire ifu_bus_rvalid_ff = ifu_bus_rvalid_unq_ff & bus_ifu_bus_clk_en_ff; // @[el2_ifu_mem_ctl.scala 593:49] + wire bus_ifu_wr_en_ff = ifu_bus_rvalid_ff & miss_pending; // @[el2_ifu_mem_ctl.scala 620:41] + reg uncacheable_miss_ff; // @[el2_ifu_mem_ctl.scala 311:62] + reg [2:0] bus_data_beat_count; // @[el2_ifu_mem_ctl.scala 601:56] + wire _T_2623 = bus_data_beat_count == 3'h1; // @[el2_ifu_mem_ctl.scala 618:69] + wire _T_2624 = &bus_data_beat_count; // @[el2_ifu_mem_ctl.scala 618:101] + wire bus_last_data_beat = uncacheable_miss_ff ? _T_2623 : _T_2624; // @[el2_ifu_mem_ctl.scala 618:28] + wire _T_2575 = bus_ifu_wr_en_ff & bus_last_data_beat; // @[el2_ifu_mem_ctl.scala 597:68] + wire _T_2576 = ic_act_miss_f | _T_2575; // @[el2_ifu_mem_ctl.scala 597:48] + wire bus_reset_data_beat_cnt = _T_2576 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 597:91] + wire _T_2572 = ~bus_last_data_beat; // @[el2_ifu_mem_ctl.scala 596:50] + wire _T_2573 = bus_ifu_wr_en_ff & _T_2572; // @[el2_ifu_mem_ctl.scala 596:48] + wire _T_2574 = ~io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 596:72] + wire bus_inc_data_beat_cnt = _T_2573 & _T_2574; // @[el2_ifu_mem_ctl.scala 596:70] + wire [2:0] _T_2580 = bus_data_beat_count + 3'h1; // @[el2_ifu_mem_ctl.scala 600:115] + wire [2:0] _T_2582 = bus_inc_data_beat_cnt ? _T_2580 : 3'h0; // @[Mux.scala 27:72] + wire _T_2577 = ~bus_inc_data_beat_cnt; // @[el2_ifu_mem_ctl.scala 598:32] + wire _T_2578 = ~bus_reset_data_beat_cnt; // @[el2_ifu_mem_ctl.scala 598:57] + wire bus_hold_data_beat_cnt = _T_2577 & _T_2578; // @[el2_ifu_mem_ctl.scala 598:55] + wire [2:0] _T_2583 = bus_hold_data_beat_cnt ? bus_data_beat_count : 3'h0; // @[Mux.scala 27:72] + wire [2:0] bus_new_data_beat_count = _T_2582 | _T_2583; // @[Mux.scala 27:72] + wire _T_15 = &bus_new_data_beat_count; // @[el2_ifu_mem_ctl.scala 195:112] + wire _T_16 = _T_14 & _T_15; // @[el2_ifu_mem_ctl.scala 195:85] + wire _T_17 = ~uncacheable_miss_ff; // @[el2_ifu_mem_ctl.scala 196:5] + wire _T_18 = _T_16 & _T_17; // @[el2_ifu_mem_ctl.scala 195:118] + wire _T_19 = miss_state == 3'h5; // @[el2_ifu_mem_ctl.scala 196:41] + wire _T_24 = 3'h0 == miss_state; // @[Conditional.scala 37:30] + wire _T_26 = ic_act_miss_f & _T_319; // @[el2_ifu_mem_ctl.scala 202:43] + wire [2:0] _T_28 = _T_26 ? 3'h1 : 3'h2; // @[el2_ifu_mem_ctl.scala 202:27] + wire _T_31 = 3'h1 == miss_state; // @[Conditional.scala 37:30] + wire [4:0] byp_fetch_index = ifu_fetch_addr_int_f[4:0]; // @[el2_ifu_mem_ctl.scala 429:45] + wire _T_2106 = byp_fetch_index[4:2] == 3'h0; // @[el2_ifu_mem_ctl.scala 450:127] + reg [7:0] ic_miss_buff_data_valid; // @[el2_ifu_mem_ctl.scala 406:60] + wire _T_2137 = _T_2106 & ic_miss_buff_data_valid[0]; // @[Mux.scala 27:72] + wire _T_2110 = byp_fetch_index[4:2] == 3'h1; // @[el2_ifu_mem_ctl.scala 450:127] + wire _T_2138 = _T_2110 & ic_miss_buff_data_valid[1]; // @[Mux.scala 27:72] + wire _T_2145 = _T_2137 | _T_2138; // @[Mux.scala 27:72] + wire _T_2114 = byp_fetch_index[4:2] == 3'h2; // @[el2_ifu_mem_ctl.scala 450:127] + wire _T_2139 = _T_2114 & ic_miss_buff_data_valid[2]; // @[Mux.scala 27:72] + wire _T_2146 = _T_2145 | _T_2139; // @[Mux.scala 27:72] + wire _T_2118 = byp_fetch_index[4:2] == 3'h3; // @[el2_ifu_mem_ctl.scala 450:127] + wire _T_2140 = _T_2118 & ic_miss_buff_data_valid[3]; // @[Mux.scala 27:72] + wire _T_2147 = _T_2146 | _T_2140; // @[Mux.scala 27:72] + wire _T_2122 = byp_fetch_index[4:2] == 3'h4; // @[el2_ifu_mem_ctl.scala 450:127] + wire _T_2141 = _T_2122 & ic_miss_buff_data_valid[4]; // @[Mux.scala 27:72] + wire _T_2148 = _T_2147 | _T_2141; // @[Mux.scala 27:72] + wire _T_2126 = byp_fetch_index[4:2] == 3'h5; // @[el2_ifu_mem_ctl.scala 450:127] + wire _T_2142 = _T_2126 & ic_miss_buff_data_valid[5]; // @[Mux.scala 27:72] + wire _T_2149 = _T_2148 | _T_2142; // @[Mux.scala 27:72] + wire _T_2130 = byp_fetch_index[4:2] == 3'h6; // @[el2_ifu_mem_ctl.scala 450:127] + wire _T_2143 = _T_2130 & ic_miss_buff_data_valid[6]; // @[Mux.scala 27:72] + wire _T_2150 = _T_2149 | _T_2143; // @[Mux.scala 27:72] + wire _T_2134 = byp_fetch_index[4:2] == 3'h7; // @[el2_ifu_mem_ctl.scala 450:127] + wire _T_2144 = _T_2134 & ic_miss_buff_data_valid[7]; // @[Mux.scala 27:72] + wire ic_miss_buff_data_valid_bypass_index = _T_2150 | _T_2144; // @[Mux.scala 27:72] + wire _T_2192 = ~byp_fetch_index[1]; // @[el2_ifu_mem_ctl.scala 452:69] + wire _T_2193 = ic_miss_buff_data_valid_bypass_index & _T_2192; // @[el2_ifu_mem_ctl.scala 452:67] + wire _T_2195 = ~byp_fetch_index[0]; // @[el2_ifu_mem_ctl.scala 452:91] + wire _T_2196 = _T_2193 & _T_2195; // @[el2_ifu_mem_ctl.scala 452:89] + wire _T_2201 = _T_2193 & byp_fetch_index[0]; // @[el2_ifu_mem_ctl.scala 453:65] + wire _T_2202 = _T_2196 | _T_2201; // @[el2_ifu_mem_ctl.scala 452:112] + wire _T_2204 = ic_miss_buff_data_valid_bypass_index & byp_fetch_index[1]; // @[el2_ifu_mem_ctl.scala 454:43] + wire _T_2207 = _T_2204 & _T_2195; // @[el2_ifu_mem_ctl.scala 454:65] + wire _T_2208 = _T_2202 | _T_2207; // @[el2_ifu_mem_ctl.scala 453:88] + wire _T_2212 = _T_2204 & byp_fetch_index[0]; // @[el2_ifu_mem_ctl.scala 455:65] + wire [2:0] byp_fetch_index_inc = ifu_fetch_addr_int_f[4:2] + 3'h1; // @[el2_ifu_mem_ctl.scala 432:75] + wire _T_2152 = byp_fetch_index_inc == 3'h0; // @[el2_ifu_mem_ctl.scala 451:110] + wire _T_2176 = _T_2152 & ic_miss_buff_data_valid[0]; // @[Mux.scala 27:72] + wire _T_2155 = byp_fetch_index_inc == 3'h1; // @[el2_ifu_mem_ctl.scala 451:110] + wire _T_2177 = _T_2155 & ic_miss_buff_data_valid[1]; // @[Mux.scala 27:72] + wire _T_2184 = _T_2176 | _T_2177; // @[Mux.scala 27:72] + wire _T_2158 = byp_fetch_index_inc == 3'h2; // @[el2_ifu_mem_ctl.scala 451:110] + wire _T_2178 = _T_2158 & ic_miss_buff_data_valid[2]; // @[Mux.scala 27:72] + wire _T_2185 = _T_2184 | _T_2178; // @[Mux.scala 27:72] + wire _T_2161 = byp_fetch_index_inc == 3'h3; // @[el2_ifu_mem_ctl.scala 451:110] + wire _T_2179 = _T_2161 & ic_miss_buff_data_valid[3]; // @[Mux.scala 27:72] + wire _T_2186 = _T_2185 | _T_2179; // @[Mux.scala 27:72] + wire _T_2164 = byp_fetch_index_inc == 3'h4; // @[el2_ifu_mem_ctl.scala 451:110] + wire _T_2180 = _T_2164 & ic_miss_buff_data_valid[4]; // @[Mux.scala 27:72] + wire _T_2187 = _T_2186 | _T_2180; // @[Mux.scala 27:72] + wire _T_2167 = byp_fetch_index_inc == 3'h5; // @[el2_ifu_mem_ctl.scala 451:110] + wire _T_2181 = _T_2167 & ic_miss_buff_data_valid[5]; // @[Mux.scala 27:72] + wire _T_2188 = _T_2187 | _T_2181; // @[Mux.scala 27:72] + wire _T_2170 = byp_fetch_index_inc == 3'h6; // @[el2_ifu_mem_ctl.scala 451:110] + wire _T_2182 = _T_2170 & ic_miss_buff_data_valid[6]; // @[Mux.scala 27:72] + wire _T_2189 = _T_2188 | _T_2182; // @[Mux.scala 27:72] + wire _T_2173 = byp_fetch_index_inc == 3'h7; // @[el2_ifu_mem_ctl.scala 451:110] + wire _T_2183 = _T_2173 & ic_miss_buff_data_valid[7]; // @[Mux.scala 27:72] + wire ic_miss_buff_data_valid_inc_bypass_index = _T_2189 | _T_2183; // @[Mux.scala 27:72] + wire _T_2213 = _T_2212 & ic_miss_buff_data_valid_inc_bypass_index; // @[el2_ifu_mem_ctl.scala 455:87] + wire _T_2214 = _T_2208 | _T_2213; // @[el2_ifu_mem_ctl.scala 454:88] + wire _T_2218 = ic_miss_buff_data_valid_bypass_index & _T_2134; // @[el2_ifu_mem_ctl.scala 456:43] + wire miss_buff_hit_unq_f = _T_2214 | _T_2218; // @[el2_ifu_mem_ctl.scala 455:131] + wire _T_2234 = miss_state == 3'h4; // @[el2_ifu_mem_ctl.scala 461:55] + wire _T_2235 = miss_state == 3'h1; // @[el2_ifu_mem_ctl.scala 461:87] + wire _T_2236 = _T_2234 | _T_2235; // @[el2_ifu_mem_ctl.scala 461:74] + wire crit_byp_hit_f = miss_buff_hit_unq_f & _T_2236; // @[el2_ifu_mem_ctl.scala 461:41] + wire _T_2219 = miss_state == 3'h6; // @[el2_ifu_mem_ctl.scala 458:30] + reg [30:0] imb_ff; // @[el2_ifu_mem_ctl.scala 312:49] + wire miss_wrap_f = imb_ff[5] != ifu_fetch_addr_int_f[5]; // @[el2_ifu_mem_ctl.scala 449:51] + wire _T_2220 = ~miss_wrap_f; // @[el2_ifu_mem_ctl.scala 458:68] + wire _T_2221 = miss_buff_hit_unq_f & _T_2220; // @[el2_ifu_mem_ctl.scala 458:66] + wire stream_hit_f = _T_2219 & _T_2221; // @[el2_ifu_mem_ctl.scala 458:43] + wire _T_215 = crit_byp_hit_f | stream_hit_f; // @[el2_ifu_mem_ctl.scala 279:35] + wire _T_216 = _T_215 & fetch_req_icache_f; // @[el2_ifu_mem_ctl.scala 279:52] + wire ic_byp_hit_f = _T_216 & miss_pending; // @[el2_ifu_mem_ctl.scala 279:73] + reg last_data_recieved_ff; // @[el2_ifu_mem_ctl.scala 603:58] + wire last_beat = bus_last_data_beat & bus_ifu_wr_en_ff; // @[el2_ifu_mem_ctl.scala 630:35] + wire _T_32 = bus_ifu_wr_en_ff & last_beat; // @[el2_ifu_mem_ctl.scala 206:113] + wire _T_33 = last_data_recieved_ff | _T_32; // @[el2_ifu_mem_ctl.scala 206:93] + wire _T_34 = ic_byp_hit_f & _T_33; // @[el2_ifu_mem_ctl.scala 206:67] + wire _T_35 = _T_34 & uncacheable_miss_ff; // @[el2_ifu_mem_ctl.scala 206:127] + wire _T_36 = io_dec_tlu_force_halt | _T_35; // @[el2_ifu_mem_ctl.scala 206:51] + wire _T_38 = ~last_data_recieved_ff; // @[el2_ifu_mem_ctl.scala 207:30] + wire _T_39 = ic_byp_hit_f & _T_38; // @[el2_ifu_mem_ctl.scala 207:27] + wire _T_40 = _T_39 & uncacheable_miss_ff; // @[el2_ifu_mem_ctl.scala 207:53] + wire _T_42 = ~ic_byp_hit_f; // @[el2_ifu_mem_ctl.scala 208:16] + wire _T_44 = _T_42 & _T_319; // @[el2_ifu_mem_ctl.scala 208:30] + wire _T_46 = _T_44 & _T_32; // @[el2_ifu_mem_ctl.scala 208:52] + wire _T_47 = _T_46 & uncacheable_miss_ff; // @[el2_ifu_mem_ctl.scala 208:85] + wire _T_51 = _T_32 & _T_17; // @[el2_ifu_mem_ctl.scala 209:49] + wire _T_54 = ic_byp_hit_f & _T_319; // @[el2_ifu_mem_ctl.scala 210:33] + wire _T_56 = ~_T_32; // @[el2_ifu_mem_ctl.scala 210:57] + wire _T_57 = _T_54 & _T_56; // @[el2_ifu_mem_ctl.scala 210:55] + wire ifu_bp_hit_taken_q_f = io_ifu_bp_hit_taken_f & io_ic_hit_f; // @[el2_ifu_mem_ctl.scala 198:52] + wire _T_58 = ~ifu_bp_hit_taken_q_f; // @[el2_ifu_mem_ctl.scala 210:91] + wire _T_59 = _T_57 & _T_58; // @[el2_ifu_mem_ctl.scala 210:89] + wire _T_61 = _T_59 & _T_17; // @[el2_ifu_mem_ctl.scala 210:113] + wire _T_64 = bus_ifu_wr_en_ff & _T_319; // @[el2_ifu_mem_ctl.scala 211:39] + wire _T_67 = _T_64 & _T_56; // @[el2_ifu_mem_ctl.scala 211:61] + wire _T_69 = _T_67 & _T_58; // @[el2_ifu_mem_ctl.scala 211:95] + wire _T_71 = _T_69 & _T_17; // @[el2_ifu_mem_ctl.scala 211:119] + wire _T_79 = _T_46 & _T_17; // @[el2_ifu_mem_ctl.scala 212:102] + wire _T_81 = io_exu_flush_final | ifu_bp_hit_taken_q_f; // @[el2_ifu_mem_ctl.scala 213:46] + wire _T_84 = _T_81 & _T_56; // @[el2_ifu_mem_ctl.scala 213:70] + wire [2:0] _T_86 = _T_84 ? 3'h2 : 3'h0; // @[el2_ifu_mem_ctl.scala 213:24] + wire [2:0] _T_87 = _T_79 ? 3'h0 : _T_86; // @[el2_ifu_mem_ctl.scala 212:22] + wire [2:0] _T_88 = _T_71 ? 3'h6 : _T_87; // @[el2_ifu_mem_ctl.scala 211:20] + wire [2:0] _T_89 = _T_61 ? 3'h6 : _T_88; // @[el2_ifu_mem_ctl.scala 210:18] + wire [2:0] _T_90 = _T_51 ? 3'h0 : _T_89; // @[el2_ifu_mem_ctl.scala 209:16] + wire [2:0] _T_91 = _T_47 ? 3'h4 : _T_90; // @[el2_ifu_mem_ctl.scala 208:14] + wire [2:0] _T_92 = _T_40 ? 3'h3 : _T_91; // @[el2_ifu_mem_ctl.scala 207:12] + wire [2:0] _T_93 = _T_36 ? 3'h0 : _T_92; // @[el2_ifu_mem_ctl.scala 206:27] + wire _T_102 = 3'h4 == miss_state; // @[Conditional.scala 37:30] + wire _T_106 = 3'h6 == miss_state; // @[Conditional.scala 37:30] + wire _T_2231 = byp_fetch_index[4:1] == 4'hf; // @[el2_ifu_mem_ctl.scala 460:60] + wire _T_2232 = _T_2231 & ifc_fetch_req_f; // @[el2_ifu_mem_ctl.scala 460:94] + wire stream_eol_f = _T_2232 & stream_hit_f; // @[el2_ifu_mem_ctl.scala 460:112] + wire _T_108 = _T_81 | stream_eol_f; // @[el2_ifu_mem_ctl.scala 221:72] + wire _T_111 = _T_108 & _T_56; // @[el2_ifu_mem_ctl.scala 221:87] + wire _T_113 = _T_111 & _T_2574; // @[el2_ifu_mem_ctl.scala 221:122] + wire [2:0] _T_115 = _T_113 ? 3'h2 : 3'h0; // @[el2_ifu_mem_ctl.scala 221:27] + wire _T_121 = 3'h3 == miss_state; // @[Conditional.scala 37:30] + wire _T_124 = io_exu_flush_final & _T_56; // @[el2_ifu_mem_ctl.scala 225:48] + wire _T_126 = _T_124 & _T_2574; // @[el2_ifu_mem_ctl.scala 225:82] + wire [2:0] _T_128 = _T_126 ? 3'h2 : 3'h0; // @[el2_ifu_mem_ctl.scala 225:27] + wire _T_132 = 3'h2 == miss_state; // @[Conditional.scala 37:30] + wire _T_236 = io_ic_rd_hit == 2'h0; // @[el2_ifu_mem_ctl.scala 285:28] + wire _T_237 = _T_236 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 285:42] + wire _T_238 = _T_237 & fetch_req_icache_f; // @[el2_ifu_mem_ctl.scala 285:60] + wire _T_239 = miss_state == 3'h2; // @[el2_ifu_mem_ctl.scala 285:94] + wire _T_240 = _T_238 & _T_239; // @[el2_ifu_mem_ctl.scala 285:81] + wire _T_243 = imb_ff[30:5] != ifu_fetch_addr_int_f[30:5]; // @[el2_ifu_mem_ctl.scala 286:39] + wire _T_244 = _T_240 & _T_243; // @[el2_ifu_mem_ctl.scala 285:111] + wire _T_246 = _T_244 & _T_17; // @[el2_ifu_mem_ctl.scala 286:91] + reg sel_mb_addr_ff; // @[el2_ifu_mem_ctl.scala 340:51] + wire _T_247 = ~sel_mb_addr_ff; // @[el2_ifu_mem_ctl.scala 286:116] + wire _T_248 = _T_246 & _T_247; // @[el2_ifu_mem_ctl.scala 286:114] + wire ic_miss_under_miss_f = _T_248 & _T_209; // @[el2_ifu_mem_ctl.scala 286:132] + wire _T_135 = ic_miss_under_miss_f & _T_56; // @[el2_ifu_mem_ctl.scala 229:50] + wire _T_137 = _T_135 & _T_2574; // @[el2_ifu_mem_ctl.scala 229:84] + wire _T_256 = _T_230 & _T_239; // @[el2_ifu_mem_ctl.scala 287:85] + wire _T_259 = imb_ff[30:5] == ifu_fetch_addr_int_f[30:5]; // @[el2_ifu_mem_ctl.scala 288:39] + wire _T_260 = _T_259 | uncacheable_miss_ff; // @[el2_ifu_mem_ctl.scala 288:91] + wire ic_ignore_2nd_miss_f = _T_256 & _T_260; // @[el2_ifu_mem_ctl.scala 287:117] + wire _T_141 = ic_ignore_2nd_miss_f & _T_56; // @[el2_ifu_mem_ctl.scala 230:35] + wire _T_143 = _T_141 & _T_2574; // @[el2_ifu_mem_ctl.scala 230:69] + wire [2:0] _T_145 = _T_143 ? 3'h7 : 3'h0; // @[el2_ifu_mem_ctl.scala 230:12] + wire [2:0] _T_146 = _T_137 ? 3'h5 : _T_145; // @[el2_ifu_mem_ctl.scala 229:27] + wire _T_151 = 3'h5 == miss_state; // @[Conditional.scala 37:30] + wire [2:0] _T_154 = _T_32 ? 3'h0 : 3'h2; // @[el2_ifu_mem_ctl.scala 235:12] + wire [2:0] _T_155 = io_exu_flush_final ? _T_154 : 3'h1; // @[el2_ifu_mem_ctl.scala 234:62] + wire [2:0] _T_156 = io_dec_tlu_force_halt ? 3'h0 : _T_155; // @[el2_ifu_mem_ctl.scala 234:27] + wire _T_160 = 3'h7 == miss_state; // @[Conditional.scala 37:30] + wire [2:0] _T_164 = io_exu_flush_final ? _T_154 : 3'h0; // @[el2_ifu_mem_ctl.scala 239:62] + wire [2:0] _T_165 = io_dec_tlu_force_halt ? 3'h0 : _T_164; // @[el2_ifu_mem_ctl.scala 239:27] + wire [2:0] _GEN_0 = _T_160 ? _T_165 : 3'h0; // @[Conditional.scala 39:67] + wire [2:0] _GEN_2 = _T_151 ? _T_156 : _GEN_0; // @[Conditional.scala 39:67] + wire [2:0] _GEN_4 = _T_132 ? _T_146 : _GEN_2; // @[Conditional.scala 39:67] + wire [2:0] _GEN_6 = _T_121 ? _T_128 : _GEN_4; // @[Conditional.scala 39:67] + wire [2:0] _GEN_8 = _T_106 ? _T_115 : _GEN_6; // @[Conditional.scala 39:67] + wire [2:0] _GEN_10 = _T_102 ? 3'h0 : _GEN_8; // @[Conditional.scala 39:67] + wire [2:0] _GEN_12 = _T_31 ? _T_93 : _GEN_10; // @[Conditional.scala 39:67] + wire [2:0] miss_nxtstate = _T_24 ? _T_28 : _GEN_12; // @[Conditional.scala 40:58] + wire _T_20 = miss_nxtstate == 3'h5; // @[el2_ifu_mem_ctl.scala 196:73] + wire _T_21 = _T_19 | _T_20; // @[el2_ifu_mem_ctl.scala 196:57] + wire _T_22 = _T_18 & _T_21; // @[el2_ifu_mem_ctl.scala 196:26] + wire _T_30 = ic_act_miss_f & _T_2574; // @[el2_ifu_mem_ctl.scala 203:38] + wire _T_94 = io_dec_tlu_force_halt | io_exu_flush_final; // @[el2_ifu_mem_ctl.scala 214:46] + wire _T_95 = _T_94 | ic_byp_hit_f; // @[el2_ifu_mem_ctl.scala 214:67] + wire _T_96 = _T_95 | ifu_bp_hit_taken_q_f; // @[el2_ifu_mem_ctl.scala 214:82] + wire _T_98 = _T_96 | _T_32; // @[el2_ifu_mem_ctl.scala 214:105] + wire _T_100 = bus_ifu_wr_en_ff & _T_17; // @[el2_ifu_mem_ctl.scala 214:158] + wire _T_101 = _T_98 | _T_100; // @[el2_ifu_mem_ctl.scala 214:138] + wire _T_103 = io_exu_flush_final | flush_final_f; // @[el2_ifu_mem_ctl.scala 218:43] + wire _T_104 = _T_103 | ic_byp_hit_f; // @[el2_ifu_mem_ctl.scala 218:59] + wire _T_105 = _T_104 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 218:74] + wire _T_119 = _T_108 | _T_32; // @[el2_ifu_mem_ctl.scala 222:84] + wire _T_120 = _T_119 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 222:118] + wire _T_130 = io_exu_flush_final | _T_32; // @[el2_ifu_mem_ctl.scala 226:43] + wire _T_131 = _T_130 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 226:76] + wire _T_148 = _T_32 | ic_miss_under_miss_f; // @[el2_ifu_mem_ctl.scala 231:55] + wire _T_149 = _T_148 | ic_ignore_2nd_miss_f; // @[el2_ifu_mem_ctl.scala 231:78] + wire _T_150 = _T_149 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 231:101] + wire _T_158 = _T_32 | io_exu_flush_final; // @[el2_ifu_mem_ctl.scala 236:55] + wire _T_159 = _T_158 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 236:76] + wire _GEN_1 = _T_160 & _T_159; // @[Conditional.scala 39:67] + wire _GEN_3 = _T_151 ? _T_159 : _GEN_1; // @[Conditional.scala 39:67] + wire _GEN_5 = _T_132 ? _T_150 : _GEN_3; // @[Conditional.scala 39:67] + wire _GEN_7 = _T_121 ? _T_131 : _GEN_5; // @[Conditional.scala 39:67] + wire _GEN_9 = _T_106 ? _T_120 : _GEN_7; // @[Conditional.scala 39:67] + wire _GEN_11 = _T_102 ? _T_105 : _GEN_9; // @[Conditional.scala 39:67] + wire _GEN_13 = _T_31 ? _T_101 : _GEN_11; // @[Conditional.scala 39:67] + wire miss_state_en = _T_24 ? _T_30 : _GEN_13; // @[Conditional.scala 40:58] + wire _T_174 = ~flush_final_f; // @[el2_ifu_mem_ctl.scala 255:95] + wire _T_175 = _T_2234 & _T_174; // @[el2_ifu_mem_ctl.scala 255:93] + wire crit_wd_byp_ok_ff = _T_2235 | _T_175; // @[el2_ifu_mem_ctl.scala 255:58] + wire _T_178 = miss_pending & _T_56; // @[el2_ifu_mem_ctl.scala 256:36] + wire _T_180 = _T_2234 & io_exu_flush_final; // @[el2_ifu_mem_ctl.scala 256:106] + wire _T_181 = ~_T_180; // @[el2_ifu_mem_ctl.scala 256:72] + wire _T_182 = _T_178 & _T_181; // @[el2_ifu_mem_ctl.scala 256:70] + wire _T_184 = _T_2234 & crit_byp_hit_f; // @[el2_ifu_mem_ctl.scala 257:39] + wire _T_185 = ~_T_184; // @[el2_ifu_mem_ctl.scala 257:5] + wire _T_186 = _T_182 & _T_185; // @[el2_ifu_mem_ctl.scala 256:128] + wire _T_187 = _T_186 | ic_act_miss_f; // @[el2_ifu_mem_ctl.scala 257:59] + wire _T_188 = miss_nxtstate == 3'h4; // @[el2_ifu_mem_ctl.scala 258:36] + wire _T_189 = miss_pending & _T_188; // @[el2_ifu_mem_ctl.scala 258:19] + wire sel_hold_imb = _T_187 | _T_189; // @[el2_ifu_mem_ctl.scala 257:75] + wire _T_191 = _T_19 | ic_miss_under_miss_f; // @[el2_ifu_mem_ctl.scala 260:57] + wire sel_hold_imb_scnd = _T_191 & _T_174; // @[el2_ifu_mem_ctl.scala 260:81] + reg way_status_mb_scnd_ff; // @[el2_ifu_mem_ctl.scala 268:64] + reg [6:0] ifu_ic_rw_int_addr_ff; // @[el2_ifu_mem_ctl.scala 737:12] + wire _T_4620 = ifu_ic_rw_int_addr_ff == 7'h0; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_0; // @[Reg.scala 27:20] + wire _T_4748 = _T_4620 & way_status_out_0; // @[Mux.scala 27:72] + wire _T_4621 = ifu_ic_rw_int_addr_ff == 7'h1; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_1; // @[Reg.scala 27:20] + wire _T_4749 = _T_4621 & way_status_out_1; // @[Mux.scala 27:72] + wire _T_4876 = _T_4748 | _T_4749; // @[Mux.scala 27:72] + wire _T_4622 = ifu_ic_rw_int_addr_ff == 7'h2; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_2; // @[Reg.scala 27:20] + wire _T_4750 = _T_4622 & way_status_out_2; // @[Mux.scala 27:72] + wire _T_4877 = _T_4876 | _T_4750; // @[Mux.scala 27:72] + wire _T_4623 = ifu_ic_rw_int_addr_ff == 7'h3; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_3; // @[Reg.scala 27:20] + wire _T_4751 = _T_4623 & way_status_out_3; // @[Mux.scala 27:72] + wire _T_4878 = _T_4877 | _T_4751; // @[Mux.scala 27:72] + wire _T_4624 = ifu_ic_rw_int_addr_ff == 7'h4; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_4; // @[Reg.scala 27:20] + wire _T_4752 = _T_4624 & way_status_out_4; // @[Mux.scala 27:72] + wire _T_4879 = _T_4878 | _T_4752; // @[Mux.scala 27:72] + wire _T_4625 = ifu_ic_rw_int_addr_ff == 7'h5; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_5; // @[Reg.scala 27:20] + wire _T_4753 = _T_4625 & way_status_out_5; // @[Mux.scala 27:72] + wire _T_4880 = _T_4879 | _T_4753; // @[Mux.scala 27:72] + wire _T_4626 = ifu_ic_rw_int_addr_ff == 7'h6; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_6; // @[Reg.scala 27:20] + wire _T_4754 = _T_4626 & way_status_out_6; // @[Mux.scala 27:72] + wire _T_4881 = _T_4880 | _T_4754; // @[Mux.scala 27:72] + wire _T_4627 = ifu_ic_rw_int_addr_ff == 7'h7; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_7; // @[Reg.scala 27:20] + wire _T_4755 = _T_4627 & way_status_out_7; // @[Mux.scala 27:72] + wire _T_4882 = _T_4881 | _T_4755; // @[Mux.scala 27:72] + wire _T_4628 = ifu_ic_rw_int_addr_ff == 7'h8; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_8; // @[Reg.scala 27:20] + wire _T_4756 = _T_4628 & way_status_out_8; // @[Mux.scala 27:72] + wire _T_4883 = _T_4882 | _T_4756; // @[Mux.scala 27:72] + wire _T_4629 = ifu_ic_rw_int_addr_ff == 7'h9; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_9; // @[Reg.scala 27:20] + wire _T_4757 = _T_4629 & way_status_out_9; // @[Mux.scala 27:72] + wire _T_4884 = _T_4883 | _T_4757; // @[Mux.scala 27:72] + wire _T_4630 = ifu_ic_rw_int_addr_ff == 7'ha; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_10; // @[Reg.scala 27:20] + wire _T_4758 = _T_4630 & way_status_out_10; // @[Mux.scala 27:72] + wire _T_4885 = _T_4884 | _T_4758; // @[Mux.scala 27:72] + wire _T_4631 = ifu_ic_rw_int_addr_ff == 7'hb; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_11; // @[Reg.scala 27:20] + wire _T_4759 = _T_4631 & way_status_out_11; // @[Mux.scala 27:72] + wire _T_4886 = _T_4885 | _T_4759; // @[Mux.scala 27:72] + wire _T_4632 = ifu_ic_rw_int_addr_ff == 7'hc; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_12; // @[Reg.scala 27:20] + wire _T_4760 = _T_4632 & way_status_out_12; // @[Mux.scala 27:72] + wire _T_4887 = _T_4886 | _T_4760; // @[Mux.scala 27:72] + wire _T_4633 = ifu_ic_rw_int_addr_ff == 7'hd; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_13; // @[Reg.scala 27:20] + wire _T_4761 = _T_4633 & way_status_out_13; // @[Mux.scala 27:72] + wire _T_4888 = _T_4887 | _T_4761; // @[Mux.scala 27:72] + wire _T_4634 = ifu_ic_rw_int_addr_ff == 7'he; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_14; // @[Reg.scala 27:20] + wire _T_4762 = _T_4634 & way_status_out_14; // @[Mux.scala 27:72] + wire _T_4889 = _T_4888 | _T_4762; // @[Mux.scala 27:72] + wire _T_4635 = ifu_ic_rw_int_addr_ff == 7'hf; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_15; // @[Reg.scala 27:20] + wire _T_4763 = _T_4635 & way_status_out_15; // @[Mux.scala 27:72] + wire _T_4890 = _T_4889 | _T_4763; // @[Mux.scala 27:72] + wire _T_4636 = ifu_ic_rw_int_addr_ff == 7'h10; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_16; // @[Reg.scala 27:20] + wire _T_4764 = _T_4636 & way_status_out_16; // @[Mux.scala 27:72] + wire _T_4891 = _T_4890 | _T_4764; // @[Mux.scala 27:72] + wire _T_4637 = ifu_ic_rw_int_addr_ff == 7'h11; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_17; // @[Reg.scala 27:20] + wire _T_4765 = _T_4637 & way_status_out_17; // @[Mux.scala 27:72] + wire _T_4892 = _T_4891 | _T_4765; // @[Mux.scala 27:72] + wire _T_4638 = ifu_ic_rw_int_addr_ff == 7'h12; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_18; // @[Reg.scala 27:20] + wire _T_4766 = _T_4638 & way_status_out_18; // @[Mux.scala 27:72] + wire _T_4893 = _T_4892 | _T_4766; // @[Mux.scala 27:72] + wire _T_4639 = ifu_ic_rw_int_addr_ff == 7'h13; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_19; // @[Reg.scala 27:20] + wire _T_4767 = _T_4639 & way_status_out_19; // @[Mux.scala 27:72] + wire _T_4894 = _T_4893 | _T_4767; // @[Mux.scala 27:72] + wire _T_4640 = ifu_ic_rw_int_addr_ff == 7'h14; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_20; // @[Reg.scala 27:20] + wire _T_4768 = _T_4640 & way_status_out_20; // @[Mux.scala 27:72] + wire _T_4895 = _T_4894 | _T_4768; // @[Mux.scala 27:72] + wire _T_4641 = ifu_ic_rw_int_addr_ff == 7'h15; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_21; // @[Reg.scala 27:20] + wire _T_4769 = _T_4641 & way_status_out_21; // @[Mux.scala 27:72] + wire _T_4896 = _T_4895 | _T_4769; // @[Mux.scala 27:72] + wire _T_4642 = ifu_ic_rw_int_addr_ff == 7'h16; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_22; // @[Reg.scala 27:20] + wire _T_4770 = _T_4642 & way_status_out_22; // @[Mux.scala 27:72] + wire _T_4897 = _T_4896 | _T_4770; // @[Mux.scala 27:72] + wire _T_4643 = ifu_ic_rw_int_addr_ff == 7'h17; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_23; // @[Reg.scala 27:20] + wire _T_4771 = _T_4643 & way_status_out_23; // @[Mux.scala 27:72] + wire _T_4898 = _T_4897 | _T_4771; // @[Mux.scala 27:72] + wire _T_4644 = ifu_ic_rw_int_addr_ff == 7'h18; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_24; // @[Reg.scala 27:20] + wire _T_4772 = _T_4644 & way_status_out_24; // @[Mux.scala 27:72] + wire _T_4899 = _T_4898 | _T_4772; // @[Mux.scala 27:72] + wire _T_4645 = ifu_ic_rw_int_addr_ff == 7'h19; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_25; // @[Reg.scala 27:20] + wire _T_4773 = _T_4645 & way_status_out_25; // @[Mux.scala 27:72] + wire _T_4900 = _T_4899 | _T_4773; // @[Mux.scala 27:72] + wire _T_4646 = ifu_ic_rw_int_addr_ff == 7'h1a; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_26; // @[Reg.scala 27:20] + wire _T_4774 = _T_4646 & way_status_out_26; // @[Mux.scala 27:72] + wire _T_4901 = _T_4900 | _T_4774; // @[Mux.scala 27:72] + wire _T_4647 = ifu_ic_rw_int_addr_ff == 7'h1b; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_27; // @[Reg.scala 27:20] + wire _T_4775 = _T_4647 & way_status_out_27; // @[Mux.scala 27:72] + wire _T_4902 = _T_4901 | _T_4775; // @[Mux.scala 27:72] + wire _T_4648 = ifu_ic_rw_int_addr_ff == 7'h1c; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_28; // @[Reg.scala 27:20] + wire _T_4776 = _T_4648 & way_status_out_28; // @[Mux.scala 27:72] + wire _T_4903 = _T_4902 | _T_4776; // @[Mux.scala 27:72] + wire _T_4649 = ifu_ic_rw_int_addr_ff == 7'h1d; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_29; // @[Reg.scala 27:20] + wire _T_4777 = _T_4649 & way_status_out_29; // @[Mux.scala 27:72] + wire _T_4904 = _T_4903 | _T_4777; // @[Mux.scala 27:72] + wire _T_4650 = ifu_ic_rw_int_addr_ff == 7'h1e; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_30; // @[Reg.scala 27:20] + wire _T_4778 = _T_4650 & way_status_out_30; // @[Mux.scala 27:72] + wire _T_4905 = _T_4904 | _T_4778; // @[Mux.scala 27:72] + wire _T_4651 = ifu_ic_rw_int_addr_ff == 7'h1f; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_31; // @[Reg.scala 27:20] + wire _T_4779 = _T_4651 & way_status_out_31; // @[Mux.scala 27:72] + wire _T_4906 = _T_4905 | _T_4779; // @[Mux.scala 27:72] + wire _T_4652 = ifu_ic_rw_int_addr_ff == 7'h20; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_32; // @[Reg.scala 27:20] + wire _T_4780 = _T_4652 & way_status_out_32; // @[Mux.scala 27:72] + wire _T_4907 = _T_4906 | _T_4780; // @[Mux.scala 27:72] + wire _T_4653 = ifu_ic_rw_int_addr_ff == 7'h21; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_33; // @[Reg.scala 27:20] + wire _T_4781 = _T_4653 & way_status_out_33; // @[Mux.scala 27:72] + wire _T_4908 = _T_4907 | _T_4781; // @[Mux.scala 27:72] + wire _T_4654 = ifu_ic_rw_int_addr_ff == 7'h22; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_34; // @[Reg.scala 27:20] + wire _T_4782 = _T_4654 & way_status_out_34; // @[Mux.scala 27:72] + wire _T_4909 = _T_4908 | _T_4782; // @[Mux.scala 27:72] + wire _T_4655 = ifu_ic_rw_int_addr_ff == 7'h23; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_35; // @[Reg.scala 27:20] + wire _T_4783 = _T_4655 & way_status_out_35; // @[Mux.scala 27:72] + wire _T_4910 = _T_4909 | _T_4783; // @[Mux.scala 27:72] + wire _T_4656 = ifu_ic_rw_int_addr_ff == 7'h24; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_36; // @[Reg.scala 27:20] + wire _T_4784 = _T_4656 & way_status_out_36; // @[Mux.scala 27:72] + wire _T_4911 = _T_4910 | _T_4784; // @[Mux.scala 27:72] + wire _T_4657 = ifu_ic_rw_int_addr_ff == 7'h25; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_37; // @[Reg.scala 27:20] + wire _T_4785 = _T_4657 & way_status_out_37; // @[Mux.scala 27:72] + wire _T_4912 = _T_4911 | _T_4785; // @[Mux.scala 27:72] + wire _T_4658 = ifu_ic_rw_int_addr_ff == 7'h26; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_38; // @[Reg.scala 27:20] + wire _T_4786 = _T_4658 & way_status_out_38; // @[Mux.scala 27:72] + wire _T_4913 = _T_4912 | _T_4786; // @[Mux.scala 27:72] + wire _T_4659 = ifu_ic_rw_int_addr_ff == 7'h27; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_39; // @[Reg.scala 27:20] + wire _T_4787 = _T_4659 & way_status_out_39; // @[Mux.scala 27:72] + wire _T_4914 = _T_4913 | _T_4787; // @[Mux.scala 27:72] + wire _T_4660 = ifu_ic_rw_int_addr_ff == 7'h28; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_40; // @[Reg.scala 27:20] + wire _T_4788 = _T_4660 & way_status_out_40; // @[Mux.scala 27:72] + wire _T_4915 = _T_4914 | _T_4788; // @[Mux.scala 27:72] + wire _T_4661 = ifu_ic_rw_int_addr_ff == 7'h29; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_41; // @[Reg.scala 27:20] + wire _T_4789 = _T_4661 & way_status_out_41; // @[Mux.scala 27:72] + wire _T_4916 = _T_4915 | _T_4789; // @[Mux.scala 27:72] + wire _T_4662 = ifu_ic_rw_int_addr_ff == 7'h2a; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_42; // @[Reg.scala 27:20] + wire _T_4790 = _T_4662 & way_status_out_42; // @[Mux.scala 27:72] + wire _T_4917 = _T_4916 | _T_4790; // @[Mux.scala 27:72] + wire _T_4663 = ifu_ic_rw_int_addr_ff == 7'h2b; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_43; // @[Reg.scala 27:20] + wire _T_4791 = _T_4663 & way_status_out_43; // @[Mux.scala 27:72] + wire _T_4918 = _T_4917 | _T_4791; // @[Mux.scala 27:72] + wire _T_4664 = ifu_ic_rw_int_addr_ff == 7'h2c; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_44; // @[Reg.scala 27:20] + wire _T_4792 = _T_4664 & way_status_out_44; // @[Mux.scala 27:72] + wire _T_4919 = _T_4918 | _T_4792; // @[Mux.scala 27:72] + wire _T_4665 = ifu_ic_rw_int_addr_ff == 7'h2d; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_45; // @[Reg.scala 27:20] + wire _T_4793 = _T_4665 & way_status_out_45; // @[Mux.scala 27:72] + wire _T_4920 = _T_4919 | _T_4793; // @[Mux.scala 27:72] + wire _T_4666 = ifu_ic_rw_int_addr_ff == 7'h2e; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_46; // @[Reg.scala 27:20] + wire _T_4794 = _T_4666 & way_status_out_46; // @[Mux.scala 27:72] + wire _T_4921 = _T_4920 | _T_4794; // @[Mux.scala 27:72] + wire _T_4667 = ifu_ic_rw_int_addr_ff == 7'h2f; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_47; // @[Reg.scala 27:20] + wire _T_4795 = _T_4667 & way_status_out_47; // @[Mux.scala 27:72] + wire _T_4922 = _T_4921 | _T_4795; // @[Mux.scala 27:72] + wire _T_4668 = ifu_ic_rw_int_addr_ff == 7'h30; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_48; // @[Reg.scala 27:20] + wire _T_4796 = _T_4668 & way_status_out_48; // @[Mux.scala 27:72] + wire _T_4923 = _T_4922 | _T_4796; // @[Mux.scala 27:72] + wire _T_4669 = ifu_ic_rw_int_addr_ff == 7'h31; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_49; // @[Reg.scala 27:20] + wire _T_4797 = _T_4669 & way_status_out_49; // @[Mux.scala 27:72] + wire _T_4924 = _T_4923 | _T_4797; // @[Mux.scala 27:72] + wire _T_4670 = ifu_ic_rw_int_addr_ff == 7'h32; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_50; // @[Reg.scala 27:20] + wire _T_4798 = _T_4670 & way_status_out_50; // @[Mux.scala 27:72] + wire _T_4925 = _T_4924 | _T_4798; // @[Mux.scala 27:72] + wire _T_4671 = ifu_ic_rw_int_addr_ff == 7'h33; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_51; // @[Reg.scala 27:20] + wire _T_4799 = _T_4671 & way_status_out_51; // @[Mux.scala 27:72] + wire _T_4926 = _T_4925 | _T_4799; // @[Mux.scala 27:72] + wire _T_4672 = ifu_ic_rw_int_addr_ff == 7'h34; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_52; // @[Reg.scala 27:20] + wire _T_4800 = _T_4672 & way_status_out_52; // @[Mux.scala 27:72] + wire _T_4927 = _T_4926 | _T_4800; // @[Mux.scala 27:72] + wire _T_4673 = ifu_ic_rw_int_addr_ff == 7'h35; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_53; // @[Reg.scala 27:20] + wire _T_4801 = _T_4673 & way_status_out_53; // @[Mux.scala 27:72] + wire _T_4928 = _T_4927 | _T_4801; // @[Mux.scala 27:72] + wire _T_4674 = ifu_ic_rw_int_addr_ff == 7'h36; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_54; // @[Reg.scala 27:20] + wire _T_4802 = _T_4674 & way_status_out_54; // @[Mux.scala 27:72] + wire _T_4929 = _T_4928 | _T_4802; // @[Mux.scala 27:72] + wire _T_4675 = ifu_ic_rw_int_addr_ff == 7'h37; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_55; // @[Reg.scala 27:20] + wire _T_4803 = _T_4675 & way_status_out_55; // @[Mux.scala 27:72] + wire _T_4930 = _T_4929 | _T_4803; // @[Mux.scala 27:72] + wire _T_4676 = ifu_ic_rw_int_addr_ff == 7'h38; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_56; // @[Reg.scala 27:20] + wire _T_4804 = _T_4676 & way_status_out_56; // @[Mux.scala 27:72] + wire _T_4931 = _T_4930 | _T_4804; // @[Mux.scala 27:72] + wire _T_4677 = ifu_ic_rw_int_addr_ff == 7'h39; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_57; // @[Reg.scala 27:20] + wire _T_4805 = _T_4677 & way_status_out_57; // @[Mux.scala 27:72] + wire _T_4932 = _T_4931 | _T_4805; // @[Mux.scala 27:72] + wire _T_4678 = ifu_ic_rw_int_addr_ff == 7'h3a; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_58; // @[Reg.scala 27:20] + wire _T_4806 = _T_4678 & way_status_out_58; // @[Mux.scala 27:72] + wire _T_4933 = _T_4932 | _T_4806; // @[Mux.scala 27:72] + wire _T_4679 = ifu_ic_rw_int_addr_ff == 7'h3b; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_59; // @[Reg.scala 27:20] + wire _T_4807 = _T_4679 & way_status_out_59; // @[Mux.scala 27:72] + wire _T_4934 = _T_4933 | _T_4807; // @[Mux.scala 27:72] + wire _T_4680 = ifu_ic_rw_int_addr_ff == 7'h3c; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_60; // @[Reg.scala 27:20] + wire _T_4808 = _T_4680 & way_status_out_60; // @[Mux.scala 27:72] + wire _T_4935 = _T_4934 | _T_4808; // @[Mux.scala 27:72] + wire _T_4681 = ifu_ic_rw_int_addr_ff == 7'h3d; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_61; // @[Reg.scala 27:20] + wire _T_4809 = _T_4681 & way_status_out_61; // @[Mux.scala 27:72] + wire _T_4936 = _T_4935 | _T_4809; // @[Mux.scala 27:72] + wire _T_4682 = ifu_ic_rw_int_addr_ff == 7'h3e; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_62; // @[Reg.scala 27:20] + wire _T_4810 = _T_4682 & way_status_out_62; // @[Mux.scala 27:72] + wire _T_4937 = _T_4936 | _T_4810; // @[Mux.scala 27:72] + wire _T_4683 = ifu_ic_rw_int_addr_ff == 7'h3f; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_63; // @[Reg.scala 27:20] + wire _T_4811 = _T_4683 & way_status_out_63; // @[Mux.scala 27:72] + wire _T_4938 = _T_4937 | _T_4811; // @[Mux.scala 27:72] + wire _T_4684 = ifu_ic_rw_int_addr_ff == 7'h40; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_64; // @[Reg.scala 27:20] + wire _T_4812 = _T_4684 & way_status_out_64; // @[Mux.scala 27:72] + wire _T_4939 = _T_4938 | _T_4812; // @[Mux.scala 27:72] + wire _T_4685 = ifu_ic_rw_int_addr_ff == 7'h41; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_65; // @[Reg.scala 27:20] + wire _T_4813 = _T_4685 & way_status_out_65; // @[Mux.scala 27:72] + wire _T_4940 = _T_4939 | _T_4813; // @[Mux.scala 27:72] + wire _T_4686 = ifu_ic_rw_int_addr_ff == 7'h42; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_66; // @[Reg.scala 27:20] + wire _T_4814 = _T_4686 & way_status_out_66; // @[Mux.scala 27:72] + wire _T_4941 = _T_4940 | _T_4814; // @[Mux.scala 27:72] + wire _T_4687 = ifu_ic_rw_int_addr_ff == 7'h43; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_67; // @[Reg.scala 27:20] + wire _T_4815 = _T_4687 & way_status_out_67; // @[Mux.scala 27:72] + wire _T_4942 = _T_4941 | _T_4815; // @[Mux.scala 27:72] + wire _T_4688 = ifu_ic_rw_int_addr_ff == 7'h44; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_68; // @[Reg.scala 27:20] + wire _T_4816 = _T_4688 & way_status_out_68; // @[Mux.scala 27:72] + wire _T_4943 = _T_4942 | _T_4816; // @[Mux.scala 27:72] + wire _T_4689 = ifu_ic_rw_int_addr_ff == 7'h45; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_69; // @[Reg.scala 27:20] + wire _T_4817 = _T_4689 & way_status_out_69; // @[Mux.scala 27:72] + wire _T_4944 = _T_4943 | _T_4817; // @[Mux.scala 27:72] + wire _T_4690 = ifu_ic_rw_int_addr_ff == 7'h46; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_70; // @[Reg.scala 27:20] + wire _T_4818 = _T_4690 & way_status_out_70; // @[Mux.scala 27:72] + wire _T_4945 = _T_4944 | _T_4818; // @[Mux.scala 27:72] + wire _T_4691 = ifu_ic_rw_int_addr_ff == 7'h47; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_71; // @[Reg.scala 27:20] + wire _T_4819 = _T_4691 & way_status_out_71; // @[Mux.scala 27:72] + wire _T_4946 = _T_4945 | _T_4819; // @[Mux.scala 27:72] + wire _T_4692 = ifu_ic_rw_int_addr_ff == 7'h48; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_72; // @[Reg.scala 27:20] + wire _T_4820 = _T_4692 & way_status_out_72; // @[Mux.scala 27:72] + wire _T_4947 = _T_4946 | _T_4820; // @[Mux.scala 27:72] + wire _T_4693 = ifu_ic_rw_int_addr_ff == 7'h49; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_73; // @[Reg.scala 27:20] + wire _T_4821 = _T_4693 & way_status_out_73; // @[Mux.scala 27:72] + wire _T_4948 = _T_4947 | _T_4821; // @[Mux.scala 27:72] + wire _T_4694 = ifu_ic_rw_int_addr_ff == 7'h4a; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_74; // @[Reg.scala 27:20] + wire _T_4822 = _T_4694 & way_status_out_74; // @[Mux.scala 27:72] + wire _T_4949 = _T_4948 | _T_4822; // @[Mux.scala 27:72] + wire _T_4695 = ifu_ic_rw_int_addr_ff == 7'h4b; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_75; // @[Reg.scala 27:20] + wire _T_4823 = _T_4695 & way_status_out_75; // @[Mux.scala 27:72] + wire _T_4950 = _T_4949 | _T_4823; // @[Mux.scala 27:72] + wire _T_4696 = ifu_ic_rw_int_addr_ff == 7'h4c; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_76; // @[Reg.scala 27:20] + wire _T_4824 = _T_4696 & way_status_out_76; // @[Mux.scala 27:72] + wire _T_4951 = _T_4950 | _T_4824; // @[Mux.scala 27:72] + wire _T_4697 = ifu_ic_rw_int_addr_ff == 7'h4d; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_77; // @[Reg.scala 27:20] + wire _T_4825 = _T_4697 & way_status_out_77; // @[Mux.scala 27:72] + wire _T_4952 = _T_4951 | _T_4825; // @[Mux.scala 27:72] + wire _T_4698 = ifu_ic_rw_int_addr_ff == 7'h4e; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_78; // @[Reg.scala 27:20] + wire _T_4826 = _T_4698 & way_status_out_78; // @[Mux.scala 27:72] + wire _T_4953 = _T_4952 | _T_4826; // @[Mux.scala 27:72] + wire _T_4699 = ifu_ic_rw_int_addr_ff == 7'h4f; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_79; // @[Reg.scala 27:20] + wire _T_4827 = _T_4699 & way_status_out_79; // @[Mux.scala 27:72] + wire _T_4954 = _T_4953 | _T_4827; // @[Mux.scala 27:72] + wire _T_4700 = ifu_ic_rw_int_addr_ff == 7'h50; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_80; // @[Reg.scala 27:20] + wire _T_4828 = _T_4700 & way_status_out_80; // @[Mux.scala 27:72] + wire _T_4955 = _T_4954 | _T_4828; // @[Mux.scala 27:72] + wire _T_4701 = ifu_ic_rw_int_addr_ff == 7'h51; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_81; // @[Reg.scala 27:20] + wire _T_4829 = _T_4701 & way_status_out_81; // @[Mux.scala 27:72] + wire _T_4956 = _T_4955 | _T_4829; // @[Mux.scala 27:72] + wire _T_4702 = ifu_ic_rw_int_addr_ff == 7'h52; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_82; // @[Reg.scala 27:20] + wire _T_4830 = _T_4702 & way_status_out_82; // @[Mux.scala 27:72] + wire _T_4957 = _T_4956 | _T_4830; // @[Mux.scala 27:72] + wire _T_4703 = ifu_ic_rw_int_addr_ff == 7'h53; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_83; // @[Reg.scala 27:20] + wire _T_4831 = _T_4703 & way_status_out_83; // @[Mux.scala 27:72] + wire _T_4958 = _T_4957 | _T_4831; // @[Mux.scala 27:72] + wire _T_4704 = ifu_ic_rw_int_addr_ff == 7'h54; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_84; // @[Reg.scala 27:20] + wire _T_4832 = _T_4704 & way_status_out_84; // @[Mux.scala 27:72] + wire _T_4959 = _T_4958 | _T_4832; // @[Mux.scala 27:72] + wire _T_4705 = ifu_ic_rw_int_addr_ff == 7'h55; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_85; // @[Reg.scala 27:20] + wire _T_4833 = _T_4705 & way_status_out_85; // @[Mux.scala 27:72] + wire _T_4960 = _T_4959 | _T_4833; // @[Mux.scala 27:72] + wire _T_4706 = ifu_ic_rw_int_addr_ff == 7'h56; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_86; // @[Reg.scala 27:20] + wire _T_4834 = _T_4706 & way_status_out_86; // @[Mux.scala 27:72] + wire _T_4961 = _T_4960 | _T_4834; // @[Mux.scala 27:72] + wire _T_4707 = ifu_ic_rw_int_addr_ff == 7'h57; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_87; // @[Reg.scala 27:20] + wire _T_4835 = _T_4707 & way_status_out_87; // @[Mux.scala 27:72] + wire _T_4962 = _T_4961 | _T_4835; // @[Mux.scala 27:72] + wire _T_4708 = ifu_ic_rw_int_addr_ff == 7'h58; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_88; // @[Reg.scala 27:20] + wire _T_4836 = _T_4708 & way_status_out_88; // @[Mux.scala 27:72] + wire _T_4963 = _T_4962 | _T_4836; // @[Mux.scala 27:72] + wire _T_4709 = ifu_ic_rw_int_addr_ff == 7'h59; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_89; // @[Reg.scala 27:20] + wire _T_4837 = _T_4709 & way_status_out_89; // @[Mux.scala 27:72] + wire _T_4964 = _T_4963 | _T_4837; // @[Mux.scala 27:72] + wire _T_4710 = ifu_ic_rw_int_addr_ff == 7'h5a; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_90; // @[Reg.scala 27:20] + wire _T_4838 = _T_4710 & way_status_out_90; // @[Mux.scala 27:72] + wire _T_4965 = _T_4964 | _T_4838; // @[Mux.scala 27:72] + wire _T_4711 = ifu_ic_rw_int_addr_ff == 7'h5b; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_91; // @[Reg.scala 27:20] + wire _T_4839 = _T_4711 & way_status_out_91; // @[Mux.scala 27:72] + wire _T_4966 = _T_4965 | _T_4839; // @[Mux.scala 27:72] + wire _T_4712 = ifu_ic_rw_int_addr_ff == 7'h5c; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_92; // @[Reg.scala 27:20] + wire _T_4840 = _T_4712 & way_status_out_92; // @[Mux.scala 27:72] + wire _T_4967 = _T_4966 | _T_4840; // @[Mux.scala 27:72] + wire _T_4713 = ifu_ic_rw_int_addr_ff == 7'h5d; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_93; // @[Reg.scala 27:20] + wire _T_4841 = _T_4713 & way_status_out_93; // @[Mux.scala 27:72] + wire _T_4968 = _T_4967 | _T_4841; // @[Mux.scala 27:72] + wire _T_4714 = ifu_ic_rw_int_addr_ff == 7'h5e; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_94; // @[Reg.scala 27:20] + wire _T_4842 = _T_4714 & way_status_out_94; // @[Mux.scala 27:72] + wire _T_4969 = _T_4968 | _T_4842; // @[Mux.scala 27:72] + wire _T_4715 = ifu_ic_rw_int_addr_ff == 7'h5f; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_95; // @[Reg.scala 27:20] + wire _T_4843 = _T_4715 & way_status_out_95; // @[Mux.scala 27:72] + wire _T_4970 = _T_4969 | _T_4843; // @[Mux.scala 27:72] + wire _T_4716 = ifu_ic_rw_int_addr_ff == 7'h60; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_96; // @[Reg.scala 27:20] + wire _T_4844 = _T_4716 & way_status_out_96; // @[Mux.scala 27:72] + wire _T_4971 = _T_4970 | _T_4844; // @[Mux.scala 27:72] + wire _T_4717 = ifu_ic_rw_int_addr_ff == 7'h61; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_97; // @[Reg.scala 27:20] + wire _T_4845 = _T_4717 & way_status_out_97; // @[Mux.scala 27:72] + wire _T_4972 = _T_4971 | _T_4845; // @[Mux.scala 27:72] + wire _T_4718 = ifu_ic_rw_int_addr_ff == 7'h62; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_98; // @[Reg.scala 27:20] + wire _T_4846 = _T_4718 & way_status_out_98; // @[Mux.scala 27:72] + wire _T_4973 = _T_4972 | _T_4846; // @[Mux.scala 27:72] + wire _T_4719 = ifu_ic_rw_int_addr_ff == 7'h63; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_99; // @[Reg.scala 27:20] + wire _T_4847 = _T_4719 & way_status_out_99; // @[Mux.scala 27:72] + wire _T_4974 = _T_4973 | _T_4847; // @[Mux.scala 27:72] + wire _T_4720 = ifu_ic_rw_int_addr_ff == 7'h64; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_100; // @[Reg.scala 27:20] + wire _T_4848 = _T_4720 & way_status_out_100; // @[Mux.scala 27:72] + wire _T_4975 = _T_4974 | _T_4848; // @[Mux.scala 27:72] + wire _T_4721 = ifu_ic_rw_int_addr_ff == 7'h65; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_101; // @[Reg.scala 27:20] + wire _T_4849 = _T_4721 & way_status_out_101; // @[Mux.scala 27:72] + wire _T_4976 = _T_4975 | _T_4849; // @[Mux.scala 27:72] + wire _T_4722 = ifu_ic_rw_int_addr_ff == 7'h66; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_102; // @[Reg.scala 27:20] + wire _T_4850 = _T_4722 & way_status_out_102; // @[Mux.scala 27:72] + wire _T_4977 = _T_4976 | _T_4850; // @[Mux.scala 27:72] + wire _T_4723 = ifu_ic_rw_int_addr_ff == 7'h67; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_103; // @[Reg.scala 27:20] + wire _T_4851 = _T_4723 & way_status_out_103; // @[Mux.scala 27:72] + wire _T_4978 = _T_4977 | _T_4851; // @[Mux.scala 27:72] + wire _T_4724 = ifu_ic_rw_int_addr_ff == 7'h68; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_104; // @[Reg.scala 27:20] + wire _T_4852 = _T_4724 & way_status_out_104; // @[Mux.scala 27:72] + wire _T_4979 = _T_4978 | _T_4852; // @[Mux.scala 27:72] + wire _T_4725 = ifu_ic_rw_int_addr_ff == 7'h69; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_105; // @[Reg.scala 27:20] + wire _T_4853 = _T_4725 & way_status_out_105; // @[Mux.scala 27:72] + wire _T_4980 = _T_4979 | _T_4853; // @[Mux.scala 27:72] + wire _T_4726 = ifu_ic_rw_int_addr_ff == 7'h6a; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_106; // @[Reg.scala 27:20] + wire _T_4854 = _T_4726 & way_status_out_106; // @[Mux.scala 27:72] + wire _T_4981 = _T_4980 | _T_4854; // @[Mux.scala 27:72] + wire _T_4727 = ifu_ic_rw_int_addr_ff == 7'h6b; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_107; // @[Reg.scala 27:20] + wire _T_4855 = _T_4727 & way_status_out_107; // @[Mux.scala 27:72] + wire _T_4982 = _T_4981 | _T_4855; // @[Mux.scala 27:72] + wire _T_4728 = ifu_ic_rw_int_addr_ff == 7'h6c; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_108; // @[Reg.scala 27:20] + wire _T_4856 = _T_4728 & way_status_out_108; // @[Mux.scala 27:72] + wire _T_4983 = _T_4982 | _T_4856; // @[Mux.scala 27:72] + wire _T_4729 = ifu_ic_rw_int_addr_ff == 7'h6d; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_109; // @[Reg.scala 27:20] + wire _T_4857 = _T_4729 & way_status_out_109; // @[Mux.scala 27:72] + wire _T_4984 = _T_4983 | _T_4857; // @[Mux.scala 27:72] + wire _T_4730 = ifu_ic_rw_int_addr_ff == 7'h6e; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_110; // @[Reg.scala 27:20] + wire _T_4858 = _T_4730 & way_status_out_110; // @[Mux.scala 27:72] + wire _T_4985 = _T_4984 | _T_4858; // @[Mux.scala 27:72] + wire _T_4731 = ifu_ic_rw_int_addr_ff == 7'h6f; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_111; // @[Reg.scala 27:20] + wire _T_4859 = _T_4731 & way_status_out_111; // @[Mux.scala 27:72] + wire _T_4986 = _T_4985 | _T_4859; // @[Mux.scala 27:72] + wire _T_4732 = ifu_ic_rw_int_addr_ff == 7'h70; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_112; // @[Reg.scala 27:20] + wire _T_4860 = _T_4732 & way_status_out_112; // @[Mux.scala 27:72] + wire _T_4987 = _T_4986 | _T_4860; // @[Mux.scala 27:72] + wire _T_4733 = ifu_ic_rw_int_addr_ff == 7'h71; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_113; // @[Reg.scala 27:20] + wire _T_4861 = _T_4733 & way_status_out_113; // @[Mux.scala 27:72] + wire _T_4988 = _T_4987 | _T_4861; // @[Mux.scala 27:72] + wire _T_4734 = ifu_ic_rw_int_addr_ff == 7'h72; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_114; // @[Reg.scala 27:20] + wire _T_4862 = _T_4734 & way_status_out_114; // @[Mux.scala 27:72] + wire _T_4989 = _T_4988 | _T_4862; // @[Mux.scala 27:72] + wire _T_4735 = ifu_ic_rw_int_addr_ff == 7'h73; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_115; // @[Reg.scala 27:20] + wire _T_4863 = _T_4735 & way_status_out_115; // @[Mux.scala 27:72] + wire _T_4990 = _T_4989 | _T_4863; // @[Mux.scala 27:72] + wire _T_4736 = ifu_ic_rw_int_addr_ff == 7'h74; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_116; // @[Reg.scala 27:20] + wire _T_4864 = _T_4736 & way_status_out_116; // @[Mux.scala 27:72] + wire _T_4991 = _T_4990 | _T_4864; // @[Mux.scala 27:72] + wire _T_4737 = ifu_ic_rw_int_addr_ff == 7'h75; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_117; // @[Reg.scala 27:20] + wire _T_4865 = _T_4737 & way_status_out_117; // @[Mux.scala 27:72] + wire _T_4992 = _T_4991 | _T_4865; // @[Mux.scala 27:72] + wire _T_4738 = ifu_ic_rw_int_addr_ff == 7'h76; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_118; // @[Reg.scala 27:20] + wire _T_4866 = _T_4738 & way_status_out_118; // @[Mux.scala 27:72] + wire _T_4993 = _T_4992 | _T_4866; // @[Mux.scala 27:72] + wire _T_4739 = ifu_ic_rw_int_addr_ff == 7'h77; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_119; // @[Reg.scala 27:20] + wire _T_4867 = _T_4739 & way_status_out_119; // @[Mux.scala 27:72] + wire _T_4994 = _T_4993 | _T_4867; // @[Mux.scala 27:72] + wire _T_4740 = ifu_ic_rw_int_addr_ff == 7'h78; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_120; // @[Reg.scala 27:20] + wire _T_4868 = _T_4740 & way_status_out_120; // @[Mux.scala 27:72] + wire _T_4995 = _T_4994 | _T_4868; // @[Mux.scala 27:72] + wire _T_4741 = ifu_ic_rw_int_addr_ff == 7'h79; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_121; // @[Reg.scala 27:20] + wire _T_4869 = _T_4741 & way_status_out_121; // @[Mux.scala 27:72] + wire _T_4996 = _T_4995 | _T_4869; // @[Mux.scala 27:72] + wire _T_4742 = ifu_ic_rw_int_addr_ff == 7'h7a; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_122; // @[Reg.scala 27:20] + wire _T_4870 = _T_4742 & way_status_out_122; // @[Mux.scala 27:72] + wire _T_4997 = _T_4996 | _T_4870; // @[Mux.scala 27:72] + wire _T_4743 = ifu_ic_rw_int_addr_ff == 7'h7b; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_123; // @[Reg.scala 27:20] + wire _T_4871 = _T_4743 & way_status_out_123; // @[Mux.scala 27:72] + wire _T_4998 = _T_4997 | _T_4871; // @[Mux.scala 27:72] + wire _T_4744 = ifu_ic_rw_int_addr_ff == 7'h7c; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_124; // @[Reg.scala 27:20] + wire _T_4872 = _T_4744 & way_status_out_124; // @[Mux.scala 27:72] + wire _T_4999 = _T_4998 | _T_4872; // @[Mux.scala 27:72] + wire _T_4745 = ifu_ic_rw_int_addr_ff == 7'h7d; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_125; // @[Reg.scala 27:20] + wire _T_4873 = _T_4745 & way_status_out_125; // @[Mux.scala 27:72] + wire _T_5000 = _T_4999 | _T_4873; // @[Mux.scala 27:72] + wire _T_4746 = ifu_ic_rw_int_addr_ff == 7'h7e; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_126; // @[Reg.scala 27:20] + wire _T_4874 = _T_4746 & way_status_out_126; // @[Mux.scala 27:72] + wire _T_5001 = _T_5000 | _T_4874; // @[Mux.scala 27:72] + wire _T_4747 = ifu_ic_rw_int_addr_ff == 7'h7f; // @[el2_ifu_mem_ctl.scala 733:80] + reg way_status_out_127; // @[Reg.scala 27:20] + wire _T_4875 = _T_4747 & way_status_out_127; // @[Mux.scala 27:72] + wire way_status = _T_5001 | _T_4875; // @[Mux.scala 27:72] + wire _T_195 = ~reset_all_tags; // @[el2_ifu_mem_ctl.scala 263:96] + wire [1:0] _T_197 = _T_195 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_198 = _T_197 & io_ic_tag_valid; // @[el2_ifu_mem_ctl.scala 263:113] + reg [1:0] tagv_mb_scnd_ff; // @[el2_ifu_mem_ctl.scala 269:58] + reg uncacheable_miss_scnd_ff; // @[el2_ifu_mem_ctl.scala 265:67] + reg [30:0] imb_scnd_ff; // @[el2_ifu_mem_ctl.scala 267:54] + wire [2:0] _T_206 = bus_ifu_wr_en_ff ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + reg [2:0] ifu_bus_rid_ff; // @[el2_ifu_mem_ctl.scala 583:46] + wire [2:0] ic_wr_addr_bits_hi_3 = ifu_bus_rid_ff & _T_206; // @[el2_ifu_mem_ctl.scala 272:45] + wire _T_212 = _T_231 | _T_239; // @[el2_ifu_mem_ctl.scala 277:59] + wire _T_214 = _T_212 | _T_2219; // @[el2_ifu_mem_ctl.scala 277:91] + wire ic_iccm_hit_f = fetch_req_iccm_f & _T_214; // @[el2_ifu_mem_ctl.scala 277:41] + wire _T_219 = _T_227 & fetch_req_icache_f; // @[el2_ifu_mem_ctl.scala 283:39] + wire _T_221 = _T_219 & _T_195; // @[el2_ifu_mem_ctl.scala 283:60] + wire _T_225 = _T_221 & _T_212; // @[el2_ifu_mem_ctl.scala 283:78] + wire ic_act_hit_f = _T_225 & _T_247; // @[el2_ifu_mem_ctl.scala 283:126] + wire _T_262 = ic_act_hit_f | ic_byp_hit_f; // @[el2_ifu_mem_ctl.scala 290:31] + wire _T_263 = _T_262 | ic_iccm_hit_f; // @[el2_ifu_mem_ctl.scala 290:46] + wire _T_264 = ifc_region_acc_fault_final_f & ifc_fetch_req_f; // @[el2_ifu_mem_ctl.scala 290:94] + wire _T_268 = sel_hold_imb ? uncacheable_miss_ff : io_ifc_fetch_uncacheable_bf; // @[el2_ifu_mem_ctl.scala 291:84] + wire uncacheable_miss_in = scnd_miss_req ? uncacheable_miss_scnd_ff : _T_268; // @[el2_ifu_mem_ctl.scala 291:32] + wire _T_274 = imb_ff[11:5] == imb_scnd_ff[11:5]; // @[el2_ifu_mem_ctl.scala 294:79] + wire _T_275 = _T_274 & scnd_miss_req; // @[el2_ifu_mem_ctl.scala 294:135] + reg [1:0] ifu_bus_rresp_ff; // @[el2_ifu_mem_ctl.scala 581:51] + wire _T_2644 = |ifu_bus_rresp_ff; // @[el2_ifu_mem_ctl.scala 626:48] + wire _T_2645 = _T_2644 & ifu_bus_rvalid_ff; // @[el2_ifu_mem_ctl.scala 626:52] + wire bus_ifu_wr_data_error_ff = _T_2645 & miss_pending; // @[el2_ifu_mem_ctl.scala 626:73] + reg ifu_wr_data_comb_err_ff; // @[el2_ifu_mem_ctl.scala 368:61] + wire ifu_wr_cumulative_err_data = bus_ifu_wr_data_error_ff | ifu_wr_data_comb_err_ff; // @[el2_ifu_mem_ctl.scala 367:55] + wire _T_276 = ~ifu_wr_cumulative_err_data; // @[el2_ifu_mem_ctl.scala 294:153] + wire scnd_miss_index_match = _T_275 & _T_276; // @[el2_ifu_mem_ctl.scala 294:151] + wire _T_277 = ~scnd_miss_index_match; // @[el2_ifu_mem_ctl.scala 297:47] + wire _T_278 = scnd_miss_req & _T_277; // @[el2_ifu_mem_ctl.scala 297:45] + wire _T_280 = scnd_miss_req & scnd_miss_index_match; // @[el2_ifu_mem_ctl.scala 298:24] + reg way_status_mb_ff; // @[el2_ifu_mem_ctl.scala 318:59] + wire _T_9705 = ~way_status_mb_ff; // @[el2_ifu_mem_ctl.scala 789:31] + reg [1:0] tagv_mb_ff; // @[el2_ifu_mem_ctl.scala 319:53] + wire _T_9707 = _T_9705 & tagv_mb_ff[0]; // @[el2_ifu_mem_ctl.scala 789:49] + wire _T_9709 = _T_9707 & tagv_mb_ff[1]; // @[el2_ifu_mem_ctl.scala 789:65] + wire _T_9711 = ~tagv_mb_ff[0]; // @[el2_ifu_mem_ctl.scala 789:84] + wire replace_way_mb_any_0 = _T_9709 | _T_9711; // @[el2_ifu_mem_ctl.scala 789:82] + wire [1:0] _T_287 = scnd_miss_index_match ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire _T_9714 = way_status_mb_ff & tagv_mb_ff[0]; // @[el2_ifu_mem_ctl.scala 790:48] + wire _T_9716 = _T_9714 & tagv_mb_ff[1]; // @[el2_ifu_mem_ctl.scala 790:64] + wire _T_9718 = ~tagv_mb_ff[1]; // @[el2_ifu_mem_ctl.scala 790:83] + wire _T_9720 = _T_9718 & tagv_mb_ff[0]; // @[el2_ifu_mem_ctl.scala 790:98] + wire replace_way_mb_any_1 = _T_9716 | _T_9720; // @[el2_ifu_mem_ctl.scala 790:81] + wire [1:0] _T_288 = {replace_way_mb_any_1,replace_way_mb_any_0}; // @[Cat.scala 29:58] + wire [1:0] _T_289 = _T_287 & _T_288; // @[el2_ifu_mem_ctl.scala 302:110] + wire [1:0] _T_290 = tagv_mb_scnd_ff | _T_289; // @[el2_ifu_mem_ctl.scala 302:62] + wire [1:0] _T_295 = io_ic_tag_valid & _T_197; // @[el2_ifu_mem_ctl.scala 303:58] + wire _T_297 = ~scnd_miss_req_q; // @[el2_ifu_mem_ctl.scala 306:36] + wire _T_298 = miss_pending & _T_297; // @[el2_ifu_mem_ctl.scala 306:34] + reg reset_ic_ff; // @[el2_ifu_mem_ctl.scala 307:48] + wire _T_299 = reset_all_tags | reset_ic_ff; // @[el2_ifu_mem_ctl.scala 306:72] + wire reset_ic_in = _T_298 & _T_299; // @[el2_ifu_mem_ctl.scala 306:53] + reg fetch_uncacheable_ff; // @[el2_ifu_mem_ctl.scala 308:62] + reg [25:0] miss_addr; // @[el2_ifu_mem_ctl.scala 317:48] + wire _T_309 = io_ifu_bus_clk_en | ic_act_miss_f; // @[el2_ifu_mem_ctl.scala 316:57] + wire _T_315 = _T_2234 & flush_final_f; // @[el2_ifu_mem_ctl.scala 321:87] + wire _T_316 = ~_T_315; // @[el2_ifu_mem_ctl.scala 321:55] + wire _T_317 = io_ifc_fetch_req_bf & _T_316; // @[el2_ifu_mem_ctl.scala 321:53] + wire _T_2226 = ~_T_2221; // @[el2_ifu_mem_ctl.scala 459:46] + wire _T_2227 = _T_2219 & _T_2226; // @[el2_ifu_mem_ctl.scala 459:44] + wire stream_miss_f = _T_2227 & ifc_fetch_req_f; // @[el2_ifu_mem_ctl.scala 459:84] + wire _T_318 = ~stream_miss_f; // @[el2_ifu_mem_ctl.scala 321:106] + reg ifc_region_acc_fault_f; // @[el2_ifu_mem_ctl.scala 327:68] + reg [2:0] bus_rd_addr_count; // @[el2_ifu_mem_ctl.scala 608:55] + wire [28:0] ifu_ic_req_addr_f = {miss_addr,bus_rd_addr_count}; // @[Cat.scala 29:58] + wire _T_325 = _T_239 | _T_2219; // @[el2_ifu_mem_ctl.scala 329:55] + wire _T_328 = _T_325 & _T_56; // @[el2_ifu_mem_ctl.scala 329:82] + wire _T_2240 = ~ifu_bus_rid_ff[0]; // @[el2_ifu_mem_ctl.scala 464:55] + wire [2:0] other_tag = {ifu_bus_rid_ff[2:1],_T_2240}; // @[Cat.scala 29:58] + wire _T_2241 = other_tag == 3'h0; // @[el2_ifu_mem_ctl.scala 465:81] + wire _T_2265 = _T_2241 & ic_miss_buff_data_valid[0]; // @[Mux.scala 27:72] + wire _T_2244 = other_tag == 3'h1; // @[el2_ifu_mem_ctl.scala 465:81] + wire _T_2266 = _T_2244 & ic_miss_buff_data_valid[1]; // @[Mux.scala 27:72] + wire _T_2273 = _T_2265 | _T_2266; // @[Mux.scala 27:72] + wire _T_2247 = other_tag == 3'h2; // @[el2_ifu_mem_ctl.scala 465:81] + wire _T_2267 = _T_2247 & ic_miss_buff_data_valid[2]; // @[Mux.scala 27:72] + wire _T_2274 = _T_2273 | _T_2267; // @[Mux.scala 27:72] + wire _T_2250 = other_tag == 3'h3; // @[el2_ifu_mem_ctl.scala 465:81] + wire _T_2268 = _T_2250 & ic_miss_buff_data_valid[3]; // @[Mux.scala 27:72] + wire _T_2275 = _T_2274 | _T_2268; // @[Mux.scala 27:72] + wire _T_2253 = other_tag == 3'h4; // @[el2_ifu_mem_ctl.scala 465:81] + wire _T_2269 = _T_2253 & ic_miss_buff_data_valid[4]; // @[Mux.scala 27:72] + wire _T_2276 = _T_2275 | _T_2269; // @[Mux.scala 27:72] + wire _T_2256 = other_tag == 3'h5; // @[el2_ifu_mem_ctl.scala 465:81] + wire _T_2270 = _T_2256 & ic_miss_buff_data_valid[5]; // @[Mux.scala 27:72] + wire _T_2277 = _T_2276 | _T_2270; // @[Mux.scala 27:72] + wire _T_2259 = other_tag == 3'h6; // @[el2_ifu_mem_ctl.scala 465:81] + wire _T_2271 = _T_2259 & ic_miss_buff_data_valid[6]; // @[Mux.scala 27:72] + wire _T_2278 = _T_2277 | _T_2271; // @[Mux.scala 27:72] + wire _T_2262 = other_tag == 3'h7; // @[el2_ifu_mem_ctl.scala 465:81] + wire _T_2272 = _T_2262 & ic_miss_buff_data_valid[7]; // @[Mux.scala 27:72] + wire second_half_available = _T_2278 | _T_2272; // @[Mux.scala 27:72] + wire write_ic_16_bytes = second_half_available & bus_ifu_wr_en_ff; // @[el2_ifu_mem_ctl.scala 466:46] + wire _T_332 = miss_pending & write_ic_16_bytes; // @[el2_ifu_mem_ctl.scala 333:35] + wire _T_334 = _T_332 & _T_17; // @[el2_ifu_mem_ctl.scala 333:55] + reg ic_act_miss_f_delayed; // @[el2_ifu_mem_ctl.scala 623:61] + wire _T_2638 = ic_act_miss_f_delayed & _T_2235; // @[el2_ifu_mem_ctl.scala 624:53] + wire reset_tag_valid_for_miss = _T_2638 & _T_17; // @[el2_ifu_mem_ctl.scala 624:84] + wire sel_mb_addr = _T_334 | reset_tag_valid_for_miss; // @[el2_ifu_mem_ctl.scala 333:79] + wire [30:0] _T_338 = {imb_ff[30:5],ic_wr_addr_bits_hi_3,imb_ff[1:0]}; // @[Cat.scala 29:58] + wire _T_339 = ~sel_mb_addr; // @[el2_ifu_mem_ctl.scala 335:5] + wire [30:0] _T_340 = sel_mb_addr ? _T_338 : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_341 = _T_339 ? io_ifc_fetch_addr_bf : 31'h0; // @[Mux.scala 27:72] + wire [30:0] ifu_ic_rw_int_addr = _T_340 | _T_341; // @[Mux.scala 27:72] + wire _T_346 = _T_334 & last_beat; // @[el2_ifu_mem_ctl.scala 337:84] + wire _T_2632 = ~_T_2644; // @[el2_ifu_mem_ctl.scala 621:84] + wire _T_2633 = _T_100 & _T_2632; // @[el2_ifu_mem_ctl.scala 621:82] + wire bus_ifu_wr_en_ff_q = _T_2633 & write_ic_16_bytes; // @[el2_ifu_mem_ctl.scala 621:108] + wire sel_mb_status_addr = _T_346 & bus_ifu_wr_en_ff_q; // @[el2_ifu_mem_ctl.scala 337:96] + wire [30:0] ifu_status_wr_addr = sel_mb_status_addr ? _T_338 : ifu_fetch_addr_int_f; // @[el2_ifu_mem_ctl.scala 338:31] + reg [63:0] ifu_bus_rdata_ff; // @[el2_ifu_mem_ctl.scala 582:48] + wire [6:0] _T_569 = {ifu_bus_rdata_ff[63],ifu_bus_rdata_ff[62],ifu_bus_rdata_ff[61],ifu_bus_rdata_ff[60],ifu_bus_rdata_ff[59],ifu_bus_rdata_ff[58],ifu_bus_rdata_ff[57]}; // @[el2_lib.scala 416:13] + wire _T_570 = ^_T_569; // @[el2_lib.scala 416:20] + wire [6:0] _T_576 = {ifu_bus_rdata_ff[32],ifu_bus_rdata_ff[31],ifu_bus_rdata_ff[30],ifu_bus_rdata_ff[29],ifu_bus_rdata_ff[28],ifu_bus_rdata_ff[27],ifu_bus_rdata_ff[26]}; // @[el2_lib.scala 416:30] + wire [7:0] _T_583 = {ifu_bus_rdata_ff[40],ifu_bus_rdata_ff[39],ifu_bus_rdata_ff[38],ifu_bus_rdata_ff[37],ifu_bus_rdata_ff[36],ifu_bus_rdata_ff[35],ifu_bus_rdata_ff[34],ifu_bus_rdata_ff[33]}; // @[el2_lib.scala 416:30] + wire [14:0] _T_584 = {ifu_bus_rdata_ff[40],ifu_bus_rdata_ff[39],ifu_bus_rdata_ff[38],ifu_bus_rdata_ff[37],ifu_bus_rdata_ff[36],ifu_bus_rdata_ff[35],ifu_bus_rdata_ff[34],ifu_bus_rdata_ff[33],_T_576}; // @[el2_lib.scala 416:30] + wire [7:0] _T_591 = {ifu_bus_rdata_ff[48],ifu_bus_rdata_ff[47],ifu_bus_rdata_ff[46],ifu_bus_rdata_ff[45],ifu_bus_rdata_ff[44],ifu_bus_rdata_ff[43],ifu_bus_rdata_ff[42],ifu_bus_rdata_ff[41]}; // @[el2_lib.scala 416:30] + wire [30:0] _T_600 = {ifu_bus_rdata_ff[56],ifu_bus_rdata_ff[55],ifu_bus_rdata_ff[54],ifu_bus_rdata_ff[53],ifu_bus_rdata_ff[52],ifu_bus_rdata_ff[51],ifu_bus_rdata_ff[50],ifu_bus_rdata_ff[49],_T_591,_T_584}; // @[el2_lib.scala 416:30] + wire _T_601 = ^_T_600; // @[el2_lib.scala 416:37] + wire [6:0] _T_607 = {ifu_bus_rdata_ff[17],ifu_bus_rdata_ff[16],ifu_bus_rdata_ff[15],ifu_bus_rdata_ff[14],ifu_bus_rdata_ff[13],ifu_bus_rdata_ff[12],ifu_bus_rdata_ff[11]}; // @[el2_lib.scala 416:47] + wire [14:0] _T_615 = {ifu_bus_rdata_ff[25],ifu_bus_rdata_ff[24],ifu_bus_rdata_ff[23],ifu_bus_rdata_ff[22],ifu_bus_rdata_ff[21],ifu_bus_rdata_ff[20],ifu_bus_rdata_ff[19],ifu_bus_rdata_ff[18],_T_607}; // @[el2_lib.scala 416:47] + wire [30:0] _T_631 = {ifu_bus_rdata_ff[56],ifu_bus_rdata_ff[55],ifu_bus_rdata_ff[54],ifu_bus_rdata_ff[53],ifu_bus_rdata_ff[52],ifu_bus_rdata_ff[51],ifu_bus_rdata_ff[50],ifu_bus_rdata_ff[49],_T_591,_T_615}; // @[el2_lib.scala 416:47] + wire _T_632 = ^_T_631; // @[el2_lib.scala 416:54] + wire [6:0] _T_638 = {ifu_bus_rdata_ff[10],ifu_bus_rdata_ff[9],ifu_bus_rdata_ff[8],ifu_bus_rdata_ff[7],ifu_bus_rdata_ff[6],ifu_bus_rdata_ff[5],ifu_bus_rdata_ff[4]}; // @[el2_lib.scala 416:64] + wire [14:0] _T_646 = {ifu_bus_rdata_ff[25],ifu_bus_rdata_ff[24],ifu_bus_rdata_ff[23],ifu_bus_rdata_ff[22],ifu_bus_rdata_ff[21],ifu_bus_rdata_ff[20],ifu_bus_rdata_ff[19],ifu_bus_rdata_ff[18],_T_638}; // @[el2_lib.scala 416:64] + wire [30:0] _T_662 = {ifu_bus_rdata_ff[56],ifu_bus_rdata_ff[55],ifu_bus_rdata_ff[54],ifu_bus_rdata_ff[53],ifu_bus_rdata_ff[52],ifu_bus_rdata_ff[51],ifu_bus_rdata_ff[50],ifu_bus_rdata_ff[49],_T_583,_T_646}; // @[el2_lib.scala 416:64] + wire _T_663 = ^_T_662; // @[el2_lib.scala 416:71] + wire [7:0] _T_670 = {ifu_bus_rdata_ff[14],ifu_bus_rdata_ff[10],ifu_bus_rdata_ff[9],ifu_bus_rdata_ff[8],ifu_bus_rdata_ff[7],ifu_bus_rdata_ff[3],ifu_bus_rdata_ff[2],ifu_bus_rdata_ff[1]}; // @[el2_lib.scala 416:81] + wire [16:0] _T_679 = {ifu_bus_rdata_ff[30],ifu_bus_rdata_ff[29],ifu_bus_rdata_ff[25],ifu_bus_rdata_ff[24],ifu_bus_rdata_ff[23],ifu_bus_rdata_ff[22],ifu_bus_rdata_ff[17],ifu_bus_rdata_ff[16],ifu_bus_rdata_ff[15],_T_670}; // @[el2_lib.scala 416:81] + wire [8:0] _T_687 = {ifu_bus_rdata_ff[47],ifu_bus_rdata_ff[46],ifu_bus_rdata_ff[45],ifu_bus_rdata_ff[40],ifu_bus_rdata_ff[39],ifu_bus_rdata_ff[38],ifu_bus_rdata_ff[37],ifu_bus_rdata_ff[32],ifu_bus_rdata_ff[31]}; // @[el2_lib.scala 416:81] + wire [17:0] _T_696 = {ifu_bus_rdata_ff[63],ifu_bus_rdata_ff[62],ifu_bus_rdata_ff[61],ifu_bus_rdata_ff[60],ifu_bus_rdata_ff[56],ifu_bus_rdata_ff[55],ifu_bus_rdata_ff[54],ifu_bus_rdata_ff[53],ifu_bus_rdata_ff[48],_T_687}; // @[el2_lib.scala 416:81] + wire [34:0] _T_697 = {_T_696,_T_679}; // @[el2_lib.scala 416:81] + wire _T_698 = ^_T_697; // @[el2_lib.scala 416:88] + wire [7:0] _T_705 = {ifu_bus_rdata_ff[12],ifu_bus_rdata_ff[10],ifu_bus_rdata_ff[9],ifu_bus_rdata_ff[6],ifu_bus_rdata_ff[5],ifu_bus_rdata_ff[3],ifu_bus_rdata_ff[2],ifu_bus_rdata_ff[0]}; // @[el2_lib.scala 416:98] + wire [16:0] _T_714 = {ifu_bus_rdata_ff[28],ifu_bus_rdata_ff[27],ifu_bus_rdata_ff[25],ifu_bus_rdata_ff[24],ifu_bus_rdata_ff[21],ifu_bus_rdata_ff[20],ifu_bus_rdata_ff[17],ifu_bus_rdata_ff[16],ifu_bus_rdata_ff[13],_T_705}; // @[el2_lib.scala 416:98] + wire [8:0] _T_722 = {ifu_bus_rdata_ff[47],ifu_bus_rdata_ff[44],ifu_bus_rdata_ff[43],ifu_bus_rdata_ff[40],ifu_bus_rdata_ff[39],ifu_bus_rdata_ff[36],ifu_bus_rdata_ff[35],ifu_bus_rdata_ff[32],ifu_bus_rdata_ff[31]}; // @[el2_lib.scala 416:98] + wire [17:0] _T_731 = {ifu_bus_rdata_ff[63],ifu_bus_rdata_ff[62],ifu_bus_rdata_ff[59],ifu_bus_rdata_ff[58],ifu_bus_rdata_ff[56],ifu_bus_rdata_ff[55],ifu_bus_rdata_ff[52],ifu_bus_rdata_ff[51],ifu_bus_rdata_ff[48],_T_722}; // @[el2_lib.scala 416:98] + wire [34:0] _T_732 = {_T_731,_T_714}; // @[el2_lib.scala 416:98] + wire _T_733 = ^_T_732; // @[el2_lib.scala 416:105] + wire [7:0] _T_740 = {ifu_bus_rdata_ff[11],ifu_bus_rdata_ff[10],ifu_bus_rdata_ff[8],ifu_bus_rdata_ff[6],ifu_bus_rdata_ff[4],ifu_bus_rdata_ff[3],ifu_bus_rdata_ff[1],ifu_bus_rdata_ff[0]}; // @[el2_lib.scala 416:115] + wire [16:0] _T_749 = {ifu_bus_rdata_ff[28],ifu_bus_rdata_ff[26],ifu_bus_rdata_ff[25],ifu_bus_rdata_ff[23],ifu_bus_rdata_ff[21],ifu_bus_rdata_ff[19],ifu_bus_rdata_ff[17],ifu_bus_rdata_ff[15],ifu_bus_rdata_ff[13],_T_740}; // @[el2_lib.scala 416:115] + wire [8:0] _T_757 = {ifu_bus_rdata_ff[46],ifu_bus_rdata_ff[44],ifu_bus_rdata_ff[42],ifu_bus_rdata_ff[40],ifu_bus_rdata_ff[38],ifu_bus_rdata_ff[36],ifu_bus_rdata_ff[34],ifu_bus_rdata_ff[32],ifu_bus_rdata_ff[30]}; // @[el2_lib.scala 416:115] + wire [17:0] _T_766 = {ifu_bus_rdata_ff[63],ifu_bus_rdata_ff[61],ifu_bus_rdata_ff[59],ifu_bus_rdata_ff[57],ifu_bus_rdata_ff[56],ifu_bus_rdata_ff[54],ifu_bus_rdata_ff[52],ifu_bus_rdata_ff[50],ifu_bus_rdata_ff[48],_T_757}; // @[el2_lib.scala 416:115] + wire [34:0] _T_767 = {_T_766,_T_749}; // @[el2_lib.scala 416:115] + wire _T_768 = ^_T_767; // @[el2_lib.scala 416:122] + wire [3:0] _T_2281 = {ifu_bus_rid_ff[2:1],_T_2240,1'h1}; // @[Cat.scala 29:58] + wire _T_2282 = _T_2281 == 4'h0; // @[el2_ifu_mem_ctl.scala 467:89] + reg [31:0] ic_miss_buff_data_0; // @[el2_ifu_mem_ctl.scala 402:67] + wire [31:0] _T_2329 = _T_2282 ? ic_miss_buff_data_0 : 32'h0; // @[Mux.scala 27:72] + wire _T_2285 = _T_2281 == 4'h1; // @[el2_ifu_mem_ctl.scala 467:89] + reg [31:0] ic_miss_buff_data_1; // @[el2_ifu_mem_ctl.scala 403:69] + wire [31:0] _T_2330 = _T_2285 ? ic_miss_buff_data_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2345 = _T_2329 | _T_2330; // @[Mux.scala 27:72] + wire _T_2288 = _T_2281 == 4'h2; // @[el2_ifu_mem_ctl.scala 467:89] + reg [31:0] ic_miss_buff_data_2; // @[el2_ifu_mem_ctl.scala 402:67] + wire [31:0] _T_2331 = _T_2288 ? ic_miss_buff_data_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2346 = _T_2345 | _T_2331; // @[Mux.scala 27:72] + wire _T_2291 = _T_2281 == 4'h3; // @[el2_ifu_mem_ctl.scala 467:89] + reg [31:0] ic_miss_buff_data_3; // @[el2_ifu_mem_ctl.scala 403:69] + wire [31:0] _T_2332 = _T_2291 ? ic_miss_buff_data_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2347 = _T_2346 | _T_2332; // @[Mux.scala 27:72] + wire _T_2294 = _T_2281 == 4'h4; // @[el2_ifu_mem_ctl.scala 467:89] + reg [31:0] ic_miss_buff_data_4; // @[el2_ifu_mem_ctl.scala 402:67] + wire [31:0] _T_2333 = _T_2294 ? ic_miss_buff_data_4 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2348 = _T_2347 | _T_2333; // @[Mux.scala 27:72] + wire _T_2297 = _T_2281 == 4'h5; // @[el2_ifu_mem_ctl.scala 467:89] + reg [31:0] ic_miss_buff_data_5; // @[el2_ifu_mem_ctl.scala 403:69] + wire [31:0] _T_2334 = _T_2297 ? ic_miss_buff_data_5 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2349 = _T_2348 | _T_2334; // @[Mux.scala 27:72] + wire _T_2300 = _T_2281 == 4'h6; // @[el2_ifu_mem_ctl.scala 467:89] + reg [31:0] ic_miss_buff_data_6; // @[el2_ifu_mem_ctl.scala 402:67] + wire [31:0] _T_2335 = _T_2300 ? ic_miss_buff_data_6 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2350 = _T_2349 | _T_2335; // @[Mux.scala 27:72] + wire _T_2303 = _T_2281 == 4'h7; // @[el2_ifu_mem_ctl.scala 467:89] + reg [31:0] ic_miss_buff_data_7; // @[el2_ifu_mem_ctl.scala 403:69] + wire [31:0] _T_2336 = _T_2303 ? ic_miss_buff_data_7 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2351 = _T_2350 | _T_2336; // @[Mux.scala 27:72] + wire _T_2306 = _T_2281 == 4'h8; // @[el2_ifu_mem_ctl.scala 467:89] + reg [31:0] ic_miss_buff_data_8; // @[el2_ifu_mem_ctl.scala 402:67] + wire [31:0] _T_2337 = _T_2306 ? ic_miss_buff_data_8 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2352 = _T_2351 | _T_2337; // @[Mux.scala 27:72] + wire _T_2309 = _T_2281 == 4'h9; // @[el2_ifu_mem_ctl.scala 467:89] + reg [31:0] ic_miss_buff_data_9; // @[el2_ifu_mem_ctl.scala 403:69] + wire [31:0] _T_2338 = _T_2309 ? ic_miss_buff_data_9 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2353 = _T_2352 | _T_2338; // @[Mux.scala 27:72] + wire _T_2312 = _T_2281 == 4'ha; // @[el2_ifu_mem_ctl.scala 467:89] + reg [31:0] ic_miss_buff_data_10; // @[el2_ifu_mem_ctl.scala 402:67] + wire [31:0] _T_2339 = _T_2312 ? ic_miss_buff_data_10 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2354 = _T_2353 | _T_2339; // @[Mux.scala 27:72] + wire _T_2315 = _T_2281 == 4'hb; // @[el2_ifu_mem_ctl.scala 467:89] + reg [31:0] ic_miss_buff_data_11; // @[el2_ifu_mem_ctl.scala 403:69] + wire [31:0] _T_2340 = _T_2315 ? ic_miss_buff_data_11 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2355 = _T_2354 | _T_2340; // @[Mux.scala 27:72] + wire _T_2318 = _T_2281 == 4'hc; // @[el2_ifu_mem_ctl.scala 467:89] + reg [31:0] ic_miss_buff_data_12; // @[el2_ifu_mem_ctl.scala 402:67] + wire [31:0] _T_2341 = _T_2318 ? ic_miss_buff_data_12 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2356 = _T_2355 | _T_2341; // @[Mux.scala 27:72] + wire _T_2321 = _T_2281 == 4'hd; // @[el2_ifu_mem_ctl.scala 467:89] + reg [31:0] ic_miss_buff_data_13; // @[el2_ifu_mem_ctl.scala 403:69] + wire [31:0] _T_2342 = _T_2321 ? ic_miss_buff_data_13 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2357 = _T_2356 | _T_2342; // @[Mux.scala 27:72] + wire _T_2324 = _T_2281 == 4'he; // @[el2_ifu_mem_ctl.scala 467:89] + reg [31:0] ic_miss_buff_data_14; // @[el2_ifu_mem_ctl.scala 402:67] + wire [31:0] _T_2343 = _T_2324 ? ic_miss_buff_data_14 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2358 = _T_2357 | _T_2343; // @[Mux.scala 27:72] + wire _T_2327 = _T_2281 == 4'hf; // @[el2_ifu_mem_ctl.scala 467:89] + reg [31:0] ic_miss_buff_data_15; // @[el2_ifu_mem_ctl.scala 403:69] + wire [31:0] _T_2344 = _T_2327 ? ic_miss_buff_data_15 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2359 = _T_2358 | _T_2344; // @[Mux.scala 27:72] + wire [3:0] _T_2361 = {ifu_bus_rid_ff[2:1],_T_2240,1'h0}; // @[Cat.scala 29:58] + wire _T_2362 = _T_2361 == 4'h0; // @[el2_ifu_mem_ctl.scala 468:66] + wire [31:0] _T_2409 = _T_2362 ? ic_miss_buff_data_0 : 32'h0; // @[Mux.scala 27:72] + wire _T_2365 = _T_2361 == 4'h1; // @[el2_ifu_mem_ctl.scala 468:66] + wire [31:0] _T_2410 = _T_2365 ? ic_miss_buff_data_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2425 = _T_2409 | _T_2410; // @[Mux.scala 27:72] + wire _T_2368 = _T_2361 == 4'h2; // @[el2_ifu_mem_ctl.scala 468:66] + wire [31:0] _T_2411 = _T_2368 ? ic_miss_buff_data_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2426 = _T_2425 | _T_2411; // @[Mux.scala 27:72] + wire _T_2371 = _T_2361 == 4'h3; // @[el2_ifu_mem_ctl.scala 468:66] + wire [31:0] _T_2412 = _T_2371 ? ic_miss_buff_data_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2427 = _T_2426 | _T_2412; // @[Mux.scala 27:72] + wire _T_2374 = _T_2361 == 4'h4; // @[el2_ifu_mem_ctl.scala 468:66] + wire [31:0] _T_2413 = _T_2374 ? ic_miss_buff_data_4 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2428 = _T_2427 | _T_2413; // @[Mux.scala 27:72] + wire _T_2377 = _T_2361 == 4'h5; // @[el2_ifu_mem_ctl.scala 468:66] + wire [31:0] _T_2414 = _T_2377 ? ic_miss_buff_data_5 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2429 = _T_2428 | _T_2414; // @[Mux.scala 27:72] + wire _T_2380 = _T_2361 == 4'h6; // @[el2_ifu_mem_ctl.scala 468:66] + wire [31:0] _T_2415 = _T_2380 ? ic_miss_buff_data_6 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2430 = _T_2429 | _T_2415; // @[Mux.scala 27:72] + wire _T_2383 = _T_2361 == 4'h7; // @[el2_ifu_mem_ctl.scala 468:66] + wire [31:0] _T_2416 = _T_2383 ? ic_miss_buff_data_7 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2431 = _T_2430 | _T_2416; // @[Mux.scala 27:72] + wire _T_2386 = _T_2361 == 4'h8; // @[el2_ifu_mem_ctl.scala 468:66] + wire [31:0] _T_2417 = _T_2386 ? ic_miss_buff_data_8 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2432 = _T_2431 | _T_2417; // @[Mux.scala 27:72] + wire _T_2389 = _T_2361 == 4'h9; // @[el2_ifu_mem_ctl.scala 468:66] + wire [31:0] _T_2418 = _T_2389 ? ic_miss_buff_data_9 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2433 = _T_2432 | _T_2418; // @[Mux.scala 27:72] + wire _T_2392 = _T_2361 == 4'ha; // @[el2_ifu_mem_ctl.scala 468:66] + wire [31:0] _T_2419 = _T_2392 ? ic_miss_buff_data_10 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2434 = _T_2433 | _T_2419; // @[Mux.scala 27:72] + wire _T_2395 = _T_2361 == 4'hb; // @[el2_ifu_mem_ctl.scala 468:66] + wire [31:0] _T_2420 = _T_2395 ? ic_miss_buff_data_11 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2435 = _T_2434 | _T_2420; // @[Mux.scala 27:72] + wire _T_2398 = _T_2361 == 4'hc; // @[el2_ifu_mem_ctl.scala 468:66] + wire [31:0] _T_2421 = _T_2398 ? ic_miss_buff_data_12 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2436 = _T_2435 | _T_2421; // @[Mux.scala 27:72] + wire _T_2401 = _T_2361 == 4'hd; // @[el2_ifu_mem_ctl.scala 468:66] + wire [31:0] _T_2422 = _T_2401 ? ic_miss_buff_data_13 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2437 = _T_2436 | _T_2422; // @[Mux.scala 27:72] + wire _T_2404 = _T_2361 == 4'he; // @[el2_ifu_mem_ctl.scala 468:66] + wire [31:0] _T_2423 = _T_2404 ? ic_miss_buff_data_14 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2438 = _T_2437 | _T_2423; // @[Mux.scala 27:72] + wire _T_2407 = _T_2361 == 4'hf; // @[el2_ifu_mem_ctl.scala 468:66] + wire [31:0] _T_2424 = _T_2407 ? ic_miss_buff_data_15 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2439 = _T_2438 | _T_2424; // @[Mux.scala 27:72] + wire [63:0] ic_miss_buff_half = {_T_2359,_T_2439}; // @[Cat.scala 29:58] + wire [6:0] _T_991 = {ic_miss_buff_half[63],ic_miss_buff_half[62],ic_miss_buff_half[61],ic_miss_buff_half[60],ic_miss_buff_half[59],ic_miss_buff_half[58],ic_miss_buff_half[57]}; // @[el2_lib.scala 416:13] + wire _T_992 = ^_T_991; // @[el2_lib.scala 416:20] + wire [6:0] _T_998 = {ic_miss_buff_half[32],ic_miss_buff_half[31],ic_miss_buff_half[30],ic_miss_buff_half[29],ic_miss_buff_half[28],ic_miss_buff_half[27],ic_miss_buff_half[26]}; // @[el2_lib.scala 416:30] + wire [7:0] _T_1005 = {ic_miss_buff_half[40],ic_miss_buff_half[39],ic_miss_buff_half[38],ic_miss_buff_half[37],ic_miss_buff_half[36],ic_miss_buff_half[35],ic_miss_buff_half[34],ic_miss_buff_half[33]}; // @[el2_lib.scala 416:30] + wire [14:0] _T_1006 = {ic_miss_buff_half[40],ic_miss_buff_half[39],ic_miss_buff_half[38],ic_miss_buff_half[37],ic_miss_buff_half[36],ic_miss_buff_half[35],ic_miss_buff_half[34],ic_miss_buff_half[33],_T_998}; // @[el2_lib.scala 416:30] + wire [7:0] _T_1013 = {ic_miss_buff_half[48],ic_miss_buff_half[47],ic_miss_buff_half[46],ic_miss_buff_half[45],ic_miss_buff_half[44],ic_miss_buff_half[43],ic_miss_buff_half[42],ic_miss_buff_half[41]}; // @[el2_lib.scala 416:30] + wire [30:0] _T_1022 = {ic_miss_buff_half[56],ic_miss_buff_half[55],ic_miss_buff_half[54],ic_miss_buff_half[53],ic_miss_buff_half[52],ic_miss_buff_half[51],ic_miss_buff_half[50],ic_miss_buff_half[49],_T_1013,_T_1006}; // @[el2_lib.scala 416:30] + wire _T_1023 = ^_T_1022; // @[el2_lib.scala 416:37] + wire [6:0] _T_1029 = {ic_miss_buff_half[17],ic_miss_buff_half[16],ic_miss_buff_half[15],ic_miss_buff_half[14],ic_miss_buff_half[13],ic_miss_buff_half[12],ic_miss_buff_half[11]}; // @[el2_lib.scala 416:47] + wire [14:0] _T_1037 = {ic_miss_buff_half[25],ic_miss_buff_half[24],ic_miss_buff_half[23],ic_miss_buff_half[22],ic_miss_buff_half[21],ic_miss_buff_half[20],ic_miss_buff_half[19],ic_miss_buff_half[18],_T_1029}; // @[el2_lib.scala 416:47] + wire [30:0] _T_1053 = {ic_miss_buff_half[56],ic_miss_buff_half[55],ic_miss_buff_half[54],ic_miss_buff_half[53],ic_miss_buff_half[52],ic_miss_buff_half[51],ic_miss_buff_half[50],ic_miss_buff_half[49],_T_1013,_T_1037}; // @[el2_lib.scala 416:47] + wire _T_1054 = ^_T_1053; // @[el2_lib.scala 416:54] + wire [6:0] _T_1060 = {ic_miss_buff_half[10],ic_miss_buff_half[9],ic_miss_buff_half[8],ic_miss_buff_half[7],ic_miss_buff_half[6],ic_miss_buff_half[5],ic_miss_buff_half[4]}; // @[el2_lib.scala 416:64] + wire [14:0] _T_1068 = {ic_miss_buff_half[25],ic_miss_buff_half[24],ic_miss_buff_half[23],ic_miss_buff_half[22],ic_miss_buff_half[21],ic_miss_buff_half[20],ic_miss_buff_half[19],ic_miss_buff_half[18],_T_1060}; // @[el2_lib.scala 416:64] + wire [30:0] _T_1084 = {ic_miss_buff_half[56],ic_miss_buff_half[55],ic_miss_buff_half[54],ic_miss_buff_half[53],ic_miss_buff_half[52],ic_miss_buff_half[51],ic_miss_buff_half[50],ic_miss_buff_half[49],_T_1005,_T_1068}; // @[el2_lib.scala 416:64] + wire _T_1085 = ^_T_1084; // @[el2_lib.scala 416:71] + wire [7:0] _T_1092 = {ic_miss_buff_half[14],ic_miss_buff_half[10],ic_miss_buff_half[9],ic_miss_buff_half[8],ic_miss_buff_half[7],ic_miss_buff_half[3],ic_miss_buff_half[2],ic_miss_buff_half[1]}; // @[el2_lib.scala 416:81] + wire [16:0] _T_1101 = {ic_miss_buff_half[30],ic_miss_buff_half[29],ic_miss_buff_half[25],ic_miss_buff_half[24],ic_miss_buff_half[23],ic_miss_buff_half[22],ic_miss_buff_half[17],ic_miss_buff_half[16],ic_miss_buff_half[15],_T_1092}; // @[el2_lib.scala 416:81] + wire [8:0] _T_1109 = {ic_miss_buff_half[47],ic_miss_buff_half[46],ic_miss_buff_half[45],ic_miss_buff_half[40],ic_miss_buff_half[39],ic_miss_buff_half[38],ic_miss_buff_half[37],ic_miss_buff_half[32],ic_miss_buff_half[31]}; // @[el2_lib.scala 416:81] + wire [17:0] _T_1118 = {ic_miss_buff_half[63],ic_miss_buff_half[62],ic_miss_buff_half[61],ic_miss_buff_half[60],ic_miss_buff_half[56],ic_miss_buff_half[55],ic_miss_buff_half[54],ic_miss_buff_half[53],ic_miss_buff_half[48],_T_1109}; // @[el2_lib.scala 416:81] + wire [34:0] _T_1119 = {_T_1118,_T_1101}; // @[el2_lib.scala 416:81] + wire _T_1120 = ^_T_1119; // @[el2_lib.scala 416:88] + wire [7:0] _T_1127 = {ic_miss_buff_half[12],ic_miss_buff_half[10],ic_miss_buff_half[9],ic_miss_buff_half[6],ic_miss_buff_half[5],ic_miss_buff_half[3],ic_miss_buff_half[2],ic_miss_buff_half[0]}; // @[el2_lib.scala 416:98] + wire [16:0] _T_1136 = {ic_miss_buff_half[28],ic_miss_buff_half[27],ic_miss_buff_half[25],ic_miss_buff_half[24],ic_miss_buff_half[21],ic_miss_buff_half[20],ic_miss_buff_half[17],ic_miss_buff_half[16],ic_miss_buff_half[13],_T_1127}; // @[el2_lib.scala 416:98] + wire [8:0] _T_1144 = {ic_miss_buff_half[47],ic_miss_buff_half[44],ic_miss_buff_half[43],ic_miss_buff_half[40],ic_miss_buff_half[39],ic_miss_buff_half[36],ic_miss_buff_half[35],ic_miss_buff_half[32],ic_miss_buff_half[31]}; // @[el2_lib.scala 416:98] + wire [17:0] _T_1153 = {ic_miss_buff_half[63],ic_miss_buff_half[62],ic_miss_buff_half[59],ic_miss_buff_half[58],ic_miss_buff_half[56],ic_miss_buff_half[55],ic_miss_buff_half[52],ic_miss_buff_half[51],ic_miss_buff_half[48],_T_1144}; // @[el2_lib.scala 416:98] + wire [34:0] _T_1154 = {_T_1153,_T_1136}; // @[el2_lib.scala 416:98] + wire _T_1155 = ^_T_1154; // @[el2_lib.scala 416:105] + wire [7:0] _T_1162 = {ic_miss_buff_half[11],ic_miss_buff_half[10],ic_miss_buff_half[8],ic_miss_buff_half[6],ic_miss_buff_half[4],ic_miss_buff_half[3],ic_miss_buff_half[1],ic_miss_buff_half[0]}; // @[el2_lib.scala 416:115] + wire [16:0] _T_1171 = {ic_miss_buff_half[28],ic_miss_buff_half[26],ic_miss_buff_half[25],ic_miss_buff_half[23],ic_miss_buff_half[21],ic_miss_buff_half[19],ic_miss_buff_half[17],ic_miss_buff_half[15],ic_miss_buff_half[13],_T_1162}; // @[el2_lib.scala 416:115] + wire [8:0] _T_1179 = {ic_miss_buff_half[46],ic_miss_buff_half[44],ic_miss_buff_half[42],ic_miss_buff_half[40],ic_miss_buff_half[38],ic_miss_buff_half[36],ic_miss_buff_half[34],ic_miss_buff_half[32],ic_miss_buff_half[30]}; // @[el2_lib.scala 416:115] + wire [17:0] _T_1188 = {ic_miss_buff_half[63],ic_miss_buff_half[61],ic_miss_buff_half[59],ic_miss_buff_half[57],ic_miss_buff_half[56],ic_miss_buff_half[54],ic_miss_buff_half[52],ic_miss_buff_half[50],ic_miss_buff_half[48],_T_1179}; // @[el2_lib.scala 416:115] + wire [34:0] _T_1189 = {_T_1188,_T_1171}; // @[el2_lib.scala 416:115] + wire _T_1190 = ^_T_1189; // @[el2_lib.scala 416:122] + wire [70:0] _T_1235 = {_T_570,_T_601,_T_632,_T_663,_T_698,_T_733,_T_768,ifu_bus_rdata_ff}; // @[Cat.scala 29:58] + wire [70:0] _T_1234 = {_T_992,_T_1023,_T_1054,_T_1085,_T_1120,_T_1155,_T_1190,_T_2359,_T_2439}; // @[Cat.scala 29:58] + wire [141:0] _T_1236 = {_T_570,_T_601,_T_632,_T_663,_T_698,_T_733,_T_768,ifu_bus_rdata_ff,_T_1234}; // @[Cat.scala 29:58] + wire [141:0] _T_1239 = {_T_992,_T_1023,_T_1054,_T_1085,_T_1120,_T_1155,_T_1190,_T_2359,_T_2439,_T_1235}; // @[Cat.scala 29:58] + wire [141:0] ic_wr_16bytes_data = ifu_bus_rid_ff[0] ? _T_1236 : _T_1239; // @[el2_ifu_mem_ctl.scala 359:28] + wire _T_1198 = |io_ic_eccerr; // @[el2_ifu_mem_ctl.scala 349:56] + wire _T_1199 = _T_1198 & ic_act_hit_f; // @[el2_ifu_mem_ctl.scala 349:83] + wire [4:0] bypass_index = imb_ff[4:0]; // @[el2_ifu_mem_ctl.scala 414:28] + wire _T_1399 = bypass_index[4:2] == 3'h0; // @[el2_ifu_mem_ctl.scala 416:114] + wire bus_ifu_wr_en = _T_13 & miss_pending; // @[el2_ifu_mem_ctl.scala 619:35] + wire _T_1284 = io_ifu_axi_rid == 3'h0; // @[el2_ifu_mem_ctl.scala 398:91] + wire write_fill_data_0 = bus_ifu_wr_en & _T_1284; // @[el2_ifu_mem_ctl.scala 398:73] + wire _T_1325 = ~ic_act_miss_f; // @[el2_ifu_mem_ctl.scala 405:118] + wire _T_1326 = ic_miss_buff_data_valid[0] & _T_1325; // @[el2_ifu_mem_ctl.scala 405:116] + wire ic_miss_buff_data_valid_in_0 = write_fill_data_0 | _T_1326; // @[el2_ifu_mem_ctl.scala 405:88] + wire _T_1422 = _T_1399 & ic_miss_buff_data_valid_in_0; // @[Mux.scala 27:72] + wire _T_1402 = bypass_index[4:2] == 3'h1; // @[el2_ifu_mem_ctl.scala 416:114] + wire _T_1285 = io_ifu_axi_rid == 3'h1; // @[el2_ifu_mem_ctl.scala 398:91] + wire write_fill_data_1 = bus_ifu_wr_en & _T_1285; // @[el2_ifu_mem_ctl.scala 398:73] + wire _T_1329 = ic_miss_buff_data_valid[1] & _T_1325; // @[el2_ifu_mem_ctl.scala 405:116] + wire ic_miss_buff_data_valid_in_1 = write_fill_data_1 | _T_1329; // @[el2_ifu_mem_ctl.scala 405:88] + wire _T_1423 = _T_1402 & ic_miss_buff_data_valid_in_1; // @[Mux.scala 27:72] + wire _T_1430 = _T_1422 | _T_1423; // @[Mux.scala 27:72] + wire _T_1405 = bypass_index[4:2] == 3'h2; // @[el2_ifu_mem_ctl.scala 416:114] + wire _T_1286 = io_ifu_axi_rid == 3'h2; // @[el2_ifu_mem_ctl.scala 398:91] + wire write_fill_data_2 = bus_ifu_wr_en & _T_1286; // @[el2_ifu_mem_ctl.scala 398:73] + wire _T_1332 = ic_miss_buff_data_valid[2] & _T_1325; // @[el2_ifu_mem_ctl.scala 405:116] + wire ic_miss_buff_data_valid_in_2 = write_fill_data_2 | _T_1332; // @[el2_ifu_mem_ctl.scala 405:88] + wire _T_1424 = _T_1405 & ic_miss_buff_data_valid_in_2; // @[Mux.scala 27:72] + wire _T_1431 = _T_1430 | _T_1424; // @[Mux.scala 27:72] + wire _T_1408 = bypass_index[4:2] == 3'h3; // @[el2_ifu_mem_ctl.scala 416:114] + wire _T_1287 = io_ifu_axi_rid == 3'h3; // @[el2_ifu_mem_ctl.scala 398:91] + wire write_fill_data_3 = bus_ifu_wr_en & _T_1287; // @[el2_ifu_mem_ctl.scala 398:73] + wire _T_1335 = ic_miss_buff_data_valid[3] & _T_1325; // @[el2_ifu_mem_ctl.scala 405:116] + wire ic_miss_buff_data_valid_in_3 = write_fill_data_3 | _T_1335; // @[el2_ifu_mem_ctl.scala 405:88] + wire _T_1425 = _T_1408 & ic_miss_buff_data_valid_in_3; // @[Mux.scala 27:72] + wire _T_1432 = _T_1431 | _T_1425; // @[Mux.scala 27:72] + wire _T_1411 = bypass_index[4:2] == 3'h4; // @[el2_ifu_mem_ctl.scala 416:114] + wire _T_1288 = io_ifu_axi_rid == 3'h4; // @[el2_ifu_mem_ctl.scala 398:91] + wire write_fill_data_4 = bus_ifu_wr_en & _T_1288; // @[el2_ifu_mem_ctl.scala 398:73] + wire _T_1338 = ic_miss_buff_data_valid[4] & _T_1325; // @[el2_ifu_mem_ctl.scala 405:116] + wire ic_miss_buff_data_valid_in_4 = write_fill_data_4 | _T_1338; // @[el2_ifu_mem_ctl.scala 405:88] + wire _T_1426 = _T_1411 & ic_miss_buff_data_valid_in_4; // @[Mux.scala 27:72] + wire _T_1433 = _T_1432 | _T_1426; // @[Mux.scala 27:72] + wire _T_1414 = bypass_index[4:2] == 3'h5; // @[el2_ifu_mem_ctl.scala 416:114] + wire _T_1289 = io_ifu_axi_rid == 3'h5; // @[el2_ifu_mem_ctl.scala 398:91] + wire write_fill_data_5 = bus_ifu_wr_en & _T_1289; // @[el2_ifu_mem_ctl.scala 398:73] + wire _T_1341 = ic_miss_buff_data_valid[5] & _T_1325; // @[el2_ifu_mem_ctl.scala 405:116] + wire ic_miss_buff_data_valid_in_5 = write_fill_data_5 | _T_1341; // @[el2_ifu_mem_ctl.scala 405:88] + wire _T_1427 = _T_1414 & ic_miss_buff_data_valid_in_5; // @[Mux.scala 27:72] + wire _T_1434 = _T_1433 | _T_1427; // @[Mux.scala 27:72] + wire _T_1417 = bypass_index[4:2] == 3'h6; // @[el2_ifu_mem_ctl.scala 416:114] + wire _T_1290 = io_ifu_axi_rid == 3'h6; // @[el2_ifu_mem_ctl.scala 398:91] + wire write_fill_data_6 = bus_ifu_wr_en & _T_1290; // @[el2_ifu_mem_ctl.scala 398:73] + wire _T_1344 = ic_miss_buff_data_valid[6] & _T_1325; // @[el2_ifu_mem_ctl.scala 405:116] + wire ic_miss_buff_data_valid_in_6 = write_fill_data_6 | _T_1344; // @[el2_ifu_mem_ctl.scala 405:88] + wire _T_1428 = _T_1417 & ic_miss_buff_data_valid_in_6; // @[Mux.scala 27:72] + wire _T_1435 = _T_1434 | _T_1428; // @[Mux.scala 27:72] + wire _T_1420 = bypass_index[4:2] == 3'h7; // @[el2_ifu_mem_ctl.scala 416:114] + wire _T_1291 = io_ifu_axi_rid == 3'h7; // @[el2_ifu_mem_ctl.scala 398:91] + wire write_fill_data_7 = bus_ifu_wr_en & _T_1291; // @[el2_ifu_mem_ctl.scala 398:73] + wire _T_1347 = ic_miss_buff_data_valid[7] & _T_1325; // @[el2_ifu_mem_ctl.scala 405:116] + wire ic_miss_buff_data_valid_in_7 = write_fill_data_7 | _T_1347; // @[el2_ifu_mem_ctl.scala 405:88] + wire _T_1429 = _T_1420 & ic_miss_buff_data_valid_in_7; // @[Mux.scala 27:72] + wire bypass_valid_value_check = _T_1435 | _T_1429; // @[Mux.scala 27:72] + wire _T_1438 = ~bypass_index[1]; // @[el2_ifu_mem_ctl.scala 417:58] + wire _T_1439 = bypass_valid_value_check & _T_1438; // @[el2_ifu_mem_ctl.scala 417:56] + wire _T_1441 = ~bypass_index[0]; // @[el2_ifu_mem_ctl.scala 417:77] + wire _T_1442 = _T_1439 & _T_1441; // @[el2_ifu_mem_ctl.scala 417:75] + wire _T_1447 = _T_1439 & bypass_index[0]; // @[el2_ifu_mem_ctl.scala 418:50] + wire _T_1448 = _T_1442 | _T_1447; // @[el2_ifu_mem_ctl.scala 417:95] + wire _T_1450 = bypass_valid_value_check & bypass_index[1]; // @[el2_ifu_mem_ctl.scala 419:31] + wire _T_1453 = _T_1450 & _T_1441; // @[el2_ifu_mem_ctl.scala 419:49] + wire _T_1454 = _T_1448 | _T_1453; // @[el2_ifu_mem_ctl.scala 418:69] + wire _T_1458 = _T_1450 & bypass_index[0]; // @[el2_ifu_mem_ctl.scala 420:49] + wire [2:0] bypass_index_5_3_inc = bypass_index[4:2] + 3'h1; // @[el2_ifu_mem_ctl.scala 415:70] + wire _T_1459 = bypass_index_5_3_inc == 3'h0; // @[el2_ifu_mem_ctl.scala 420:130] + wire _T_1475 = _T_1459 & ic_miss_buff_data_valid_in_0; // @[Mux.scala 27:72] + wire _T_1461 = bypass_index_5_3_inc == 3'h1; // @[el2_ifu_mem_ctl.scala 420:130] + wire _T_1476 = _T_1461 & ic_miss_buff_data_valid_in_1; // @[Mux.scala 27:72] + wire _T_1483 = _T_1475 | _T_1476; // @[Mux.scala 27:72] + wire _T_1463 = bypass_index_5_3_inc == 3'h2; // @[el2_ifu_mem_ctl.scala 420:130] + wire _T_1477 = _T_1463 & ic_miss_buff_data_valid_in_2; // @[Mux.scala 27:72] + wire _T_1484 = _T_1483 | _T_1477; // @[Mux.scala 27:72] + wire _T_1465 = bypass_index_5_3_inc == 3'h3; // @[el2_ifu_mem_ctl.scala 420:130] + wire _T_1478 = _T_1465 & ic_miss_buff_data_valid_in_3; // @[Mux.scala 27:72] + wire _T_1485 = _T_1484 | _T_1478; // @[Mux.scala 27:72] + wire _T_1467 = bypass_index_5_3_inc == 3'h4; // @[el2_ifu_mem_ctl.scala 420:130] + wire _T_1479 = _T_1467 & ic_miss_buff_data_valid_in_4; // @[Mux.scala 27:72] + wire _T_1486 = _T_1485 | _T_1479; // @[Mux.scala 27:72] + wire _T_1469 = bypass_index_5_3_inc == 3'h5; // @[el2_ifu_mem_ctl.scala 420:130] + wire _T_1480 = _T_1469 & ic_miss_buff_data_valid_in_5; // @[Mux.scala 27:72] + wire _T_1487 = _T_1486 | _T_1480; // @[Mux.scala 27:72] + wire _T_1471 = bypass_index_5_3_inc == 3'h6; // @[el2_ifu_mem_ctl.scala 420:130] + wire _T_1481 = _T_1471 & ic_miss_buff_data_valid_in_6; // @[Mux.scala 27:72] + wire _T_1488 = _T_1487 | _T_1481; // @[Mux.scala 27:72] + wire _T_1473 = bypass_index_5_3_inc == 3'h7; // @[el2_ifu_mem_ctl.scala 420:130] + wire _T_1482 = _T_1473 & ic_miss_buff_data_valid_in_7; // @[Mux.scala 27:72] + wire _T_1489 = _T_1488 | _T_1482; // @[Mux.scala 27:72] + wire _T_1491 = _T_1458 & _T_1489; // @[el2_ifu_mem_ctl.scala 420:67] + wire _T_1492 = _T_1454 | _T_1491; // @[el2_ifu_mem_ctl.scala 419:69] + wire [4:0] _GEN_446 = {{2'd0}, bypass_index[4:2]}; // @[el2_ifu_mem_ctl.scala 421:70] + wire _T_1495 = _GEN_446 == 5'h1f; // @[el2_ifu_mem_ctl.scala 421:70] + wire _T_1496 = bypass_valid_value_check & _T_1495; // @[el2_ifu_mem_ctl.scala 421:31] + wire bypass_data_ready_in = _T_1492 | _T_1496; // @[el2_ifu_mem_ctl.scala 420:179] + wire _T_1497 = bypass_data_ready_in & crit_wd_byp_ok_ff; // @[el2_ifu_mem_ctl.scala 425:53] + wire _T_1498 = _T_1497 & uncacheable_miss_ff; // @[el2_ifu_mem_ctl.scala 425:73] + wire _T_1500 = _T_1498 & _T_319; // @[el2_ifu_mem_ctl.scala 425:96] + wire _T_1502 = _T_1500 & _T_58; // @[el2_ifu_mem_ctl.scala 425:118] + wire _T_1504 = crit_wd_byp_ok_ff & _T_17; // @[el2_ifu_mem_ctl.scala 426:47] + wire _T_1506 = _T_1504 & _T_319; // @[el2_ifu_mem_ctl.scala 426:70] + wire _T_1508 = _T_1506 & _T_58; // @[el2_ifu_mem_ctl.scala 426:92] + wire _T_1509 = _T_1502 | _T_1508; // @[el2_ifu_mem_ctl.scala 425:143] + reg ic_crit_wd_rdy_new_ff; // @[el2_ifu_mem_ctl.scala 428:58] + wire _T_1510 = ic_crit_wd_rdy_new_ff & crit_wd_byp_ok_ff; // @[el2_ifu_mem_ctl.scala 427:28] + wire _T_1511 = ~fetch_req_icache_f; // @[el2_ifu_mem_ctl.scala 427:50] + wire _T_1512 = _T_1510 & _T_1511; // @[el2_ifu_mem_ctl.scala 427:48] + wire _T_1514 = _T_1512 & _T_319; // @[el2_ifu_mem_ctl.scala 427:70] + wire ic_crit_wd_rdy_new_in = _T_1509 | _T_1514; // @[el2_ifu_mem_ctl.scala 426:117] + wire ic_crit_wd_rdy = ic_crit_wd_rdy_new_in | ic_crit_wd_rdy_new_ff; // @[el2_ifu_mem_ctl.scala 629:43] + wire _T_1251 = ic_crit_wd_rdy | _T_2219; // @[el2_ifu_mem_ctl.scala 372:38] + wire _T_1253 = _T_1251 | _T_2235; // @[el2_ifu_mem_ctl.scala 372:64] + wire _T_1254 = ~_T_1253; // @[el2_ifu_mem_ctl.scala 372:21] + wire _T_1255 = ~fetch_req_iccm_f; // @[el2_ifu_mem_ctl.scala 372:98] + wire sel_ic_data = _T_1254 & _T_1255; // @[el2_ifu_mem_ctl.scala 372:96] + wire _T_2442 = io_ic_tag_perr & sel_ic_data; // @[el2_ifu_mem_ctl.scala 472:44] + wire _T_1608 = ifu_fetch_addr_int_f[1] & ifu_fetch_addr_int_f[0]; // @[el2_ifu_mem_ctl.scala 439:31] + reg [7:0] ic_miss_buff_data_error; // @[el2_ifu_mem_ctl.scala 411:60] + wire _T_1552 = _T_1399 & ic_miss_buff_data_error[0]; // @[Mux.scala 27:72] + wire _T_1553 = _T_1402 & ic_miss_buff_data_error[1]; // @[Mux.scala 27:72] + wire _T_1560 = _T_1552 | _T_1553; // @[Mux.scala 27:72] + wire _T_1554 = _T_1405 & ic_miss_buff_data_error[2]; // @[Mux.scala 27:72] + wire _T_1561 = _T_1560 | _T_1554; // @[Mux.scala 27:72] + wire _T_1555 = _T_1408 & ic_miss_buff_data_error[3]; // @[Mux.scala 27:72] + wire _T_1562 = _T_1561 | _T_1555; // @[Mux.scala 27:72] + wire _T_1556 = _T_1411 & ic_miss_buff_data_error[4]; // @[Mux.scala 27:72] + wire _T_1563 = _T_1562 | _T_1556; // @[Mux.scala 27:72] + wire _T_1557 = _T_1414 & ic_miss_buff_data_error[5]; // @[Mux.scala 27:72] + wire _T_1564 = _T_1563 | _T_1557; // @[Mux.scala 27:72] + wire _T_1558 = _T_1417 & ic_miss_buff_data_error[6]; // @[Mux.scala 27:72] + wire _T_1565 = _T_1564 | _T_1558; // @[Mux.scala 27:72] + wire _T_1559 = _T_1420 & ic_miss_buff_data_error[7]; // @[Mux.scala 27:72] + wire ic_miss_buff_data_error_bypass = _T_1565 | _T_1559; // @[Mux.scala 27:72] + wire _T_1591 = _T_2152 & ic_miss_buff_data_error[0]; // @[Mux.scala 27:72] + wire _T_1592 = _T_2155 & ic_miss_buff_data_error[1]; // @[Mux.scala 27:72] + wire _T_1599 = _T_1591 | _T_1592; // @[Mux.scala 27:72] + wire _T_1593 = _T_2158 & ic_miss_buff_data_error[2]; // @[Mux.scala 27:72] + wire _T_1600 = _T_1599 | _T_1593; // @[Mux.scala 27:72] + wire _T_1594 = _T_2161 & ic_miss_buff_data_error[3]; // @[Mux.scala 27:72] + wire _T_1601 = _T_1600 | _T_1594; // @[Mux.scala 27:72] + wire _T_1595 = _T_2164 & ic_miss_buff_data_error[4]; // @[Mux.scala 27:72] + wire _T_1602 = _T_1601 | _T_1595; // @[Mux.scala 27:72] + wire _T_1596 = _T_2167 & ic_miss_buff_data_error[5]; // @[Mux.scala 27:72] + wire _T_1603 = _T_1602 | _T_1596; // @[Mux.scala 27:72] + wire _T_1597 = _T_2170 & ic_miss_buff_data_error[6]; // @[Mux.scala 27:72] + wire _T_1604 = _T_1603 | _T_1597; // @[Mux.scala 27:72] + wire _T_1598 = _T_2173 & ic_miss_buff_data_error[7]; // @[Mux.scala 27:72] + wire ic_miss_buff_data_error_bypass_inc = _T_1604 | _T_1598; // @[Mux.scala 27:72] + wire _T_1609 = ic_miss_buff_data_error_bypass | ic_miss_buff_data_error_bypass_inc; // @[el2_ifu_mem_ctl.scala 441:70] + wire ifu_byp_data_err_new = _T_1608 ? ic_miss_buff_data_error_bypass : _T_1609; // @[el2_ifu_mem_ctl.scala 439:56] + wire ifc_bus_acc_fault_f = ic_byp_hit_f & ifu_byp_data_err_new; // @[el2_ifu_mem_ctl.scala 383:42] + wire _T_2443 = ifc_region_acc_fault_final_f | ifc_bus_acc_fault_f; // @[el2_ifu_mem_ctl.scala 472:91] + wire _T_2444 = ~_T_2443; // @[el2_ifu_mem_ctl.scala 472:60] + wire ic_rd_parity_final_err = _T_2442 & _T_2444; // @[el2_ifu_mem_ctl.scala 472:58] + reg ic_debug_ict_array_sel_ff; // @[el2_ifu_mem_ctl.scala 837:63] + reg ic_tag_valid_out_1_0; // @[Reg.scala 27:20] + wire _T_9323 = _T_4620 & ic_tag_valid_out_1_0; // @[el2_ifu_mem_ctl.scala 764:8] + reg ic_tag_valid_out_1_1; // @[Reg.scala 27:20] + wire _T_9325 = _T_4621 & ic_tag_valid_out_1_1; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9578 = _T_9323 | _T_9325; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_2; // @[Reg.scala 27:20] + wire _T_9327 = _T_4622 & ic_tag_valid_out_1_2; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9579 = _T_9578 | _T_9327; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_3; // @[Reg.scala 27:20] + wire _T_9329 = _T_4623 & ic_tag_valid_out_1_3; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9580 = _T_9579 | _T_9329; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_4; // @[Reg.scala 27:20] + wire _T_9331 = _T_4624 & ic_tag_valid_out_1_4; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9581 = _T_9580 | _T_9331; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_5; // @[Reg.scala 27:20] + wire _T_9333 = _T_4625 & ic_tag_valid_out_1_5; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9582 = _T_9581 | _T_9333; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_6; // @[Reg.scala 27:20] + wire _T_9335 = _T_4626 & ic_tag_valid_out_1_6; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9583 = _T_9582 | _T_9335; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_7; // @[Reg.scala 27:20] + wire _T_9337 = _T_4627 & ic_tag_valid_out_1_7; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9584 = _T_9583 | _T_9337; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_8; // @[Reg.scala 27:20] + wire _T_9339 = _T_4628 & ic_tag_valid_out_1_8; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9585 = _T_9584 | _T_9339; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_9; // @[Reg.scala 27:20] + wire _T_9341 = _T_4629 & ic_tag_valid_out_1_9; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9586 = _T_9585 | _T_9341; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_10; // @[Reg.scala 27:20] + wire _T_9343 = _T_4630 & ic_tag_valid_out_1_10; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9587 = _T_9586 | _T_9343; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_11; // @[Reg.scala 27:20] + wire _T_9345 = _T_4631 & ic_tag_valid_out_1_11; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9588 = _T_9587 | _T_9345; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_12; // @[Reg.scala 27:20] + wire _T_9347 = _T_4632 & ic_tag_valid_out_1_12; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9589 = _T_9588 | _T_9347; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_13; // @[Reg.scala 27:20] + wire _T_9349 = _T_4633 & ic_tag_valid_out_1_13; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9590 = _T_9589 | _T_9349; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_14; // @[Reg.scala 27:20] + wire _T_9351 = _T_4634 & ic_tag_valid_out_1_14; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9591 = _T_9590 | _T_9351; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_15; // @[Reg.scala 27:20] + wire _T_9353 = _T_4635 & ic_tag_valid_out_1_15; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9592 = _T_9591 | _T_9353; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_16; // @[Reg.scala 27:20] + wire _T_9355 = _T_4636 & ic_tag_valid_out_1_16; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9593 = _T_9592 | _T_9355; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_17; // @[Reg.scala 27:20] + wire _T_9357 = _T_4637 & ic_tag_valid_out_1_17; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9594 = _T_9593 | _T_9357; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_18; // @[Reg.scala 27:20] + wire _T_9359 = _T_4638 & ic_tag_valid_out_1_18; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9595 = _T_9594 | _T_9359; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_19; // @[Reg.scala 27:20] + wire _T_9361 = _T_4639 & ic_tag_valid_out_1_19; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9596 = _T_9595 | _T_9361; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_20; // @[Reg.scala 27:20] + wire _T_9363 = _T_4640 & ic_tag_valid_out_1_20; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9597 = _T_9596 | _T_9363; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_21; // @[Reg.scala 27:20] + wire _T_9365 = _T_4641 & ic_tag_valid_out_1_21; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9598 = _T_9597 | _T_9365; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_22; // @[Reg.scala 27:20] + wire _T_9367 = _T_4642 & ic_tag_valid_out_1_22; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9599 = _T_9598 | _T_9367; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_23; // @[Reg.scala 27:20] + wire _T_9369 = _T_4643 & ic_tag_valid_out_1_23; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9600 = _T_9599 | _T_9369; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_24; // @[Reg.scala 27:20] + wire _T_9371 = _T_4644 & ic_tag_valid_out_1_24; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9601 = _T_9600 | _T_9371; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_25; // @[Reg.scala 27:20] + wire _T_9373 = _T_4645 & ic_tag_valid_out_1_25; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9602 = _T_9601 | _T_9373; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_26; // @[Reg.scala 27:20] + wire _T_9375 = _T_4646 & ic_tag_valid_out_1_26; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9603 = _T_9602 | _T_9375; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_27; // @[Reg.scala 27:20] + wire _T_9377 = _T_4647 & ic_tag_valid_out_1_27; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9604 = _T_9603 | _T_9377; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_28; // @[Reg.scala 27:20] + wire _T_9379 = _T_4648 & ic_tag_valid_out_1_28; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9605 = _T_9604 | _T_9379; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_29; // @[Reg.scala 27:20] + wire _T_9381 = _T_4649 & ic_tag_valid_out_1_29; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9606 = _T_9605 | _T_9381; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_30; // @[Reg.scala 27:20] + wire _T_9383 = _T_4650 & ic_tag_valid_out_1_30; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9607 = _T_9606 | _T_9383; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_31; // @[Reg.scala 27:20] + wire _T_9385 = _T_4651 & ic_tag_valid_out_1_31; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9608 = _T_9607 | _T_9385; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_32; // @[Reg.scala 27:20] + wire _T_9387 = _T_4652 & ic_tag_valid_out_1_32; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9609 = _T_9608 | _T_9387; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_33; // @[Reg.scala 27:20] + wire _T_9389 = _T_4653 & ic_tag_valid_out_1_33; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9610 = _T_9609 | _T_9389; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_34; // @[Reg.scala 27:20] + wire _T_9391 = _T_4654 & ic_tag_valid_out_1_34; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9611 = _T_9610 | _T_9391; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_35; // @[Reg.scala 27:20] + wire _T_9393 = _T_4655 & ic_tag_valid_out_1_35; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9612 = _T_9611 | _T_9393; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_36; // @[Reg.scala 27:20] + wire _T_9395 = _T_4656 & ic_tag_valid_out_1_36; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9613 = _T_9612 | _T_9395; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_37; // @[Reg.scala 27:20] + wire _T_9397 = _T_4657 & ic_tag_valid_out_1_37; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9614 = _T_9613 | _T_9397; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_38; // @[Reg.scala 27:20] + wire _T_9399 = _T_4658 & ic_tag_valid_out_1_38; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9615 = _T_9614 | _T_9399; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_39; // @[Reg.scala 27:20] + wire _T_9401 = _T_4659 & ic_tag_valid_out_1_39; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9616 = _T_9615 | _T_9401; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_40; // @[Reg.scala 27:20] + wire _T_9403 = _T_4660 & ic_tag_valid_out_1_40; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9617 = _T_9616 | _T_9403; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_41; // @[Reg.scala 27:20] + wire _T_9405 = _T_4661 & ic_tag_valid_out_1_41; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9618 = _T_9617 | _T_9405; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_42; // @[Reg.scala 27:20] + wire _T_9407 = _T_4662 & ic_tag_valid_out_1_42; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9619 = _T_9618 | _T_9407; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_43; // @[Reg.scala 27:20] + wire _T_9409 = _T_4663 & ic_tag_valid_out_1_43; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9620 = _T_9619 | _T_9409; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_44; // @[Reg.scala 27:20] + wire _T_9411 = _T_4664 & ic_tag_valid_out_1_44; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9621 = _T_9620 | _T_9411; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_45; // @[Reg.scala 27:20] + wire _T_9413 = _T_4665 & ic_tag_valid_out_1_45; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9622 = _T_9621 | _T_9413; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_46; // @[Reg.scala 27:20] + wire _T_9415 = _T_4666 & ic_tag_valid_out_1_46; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9623 = _T_9622 | _T_9415; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_47; // @[Reg.scala 27:20] + wire _T_9417 = _T_4667 & ic_tag_valid_out_1_47; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9624 = _T_9623 | _T_9417; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_48; // @[Reg.scala 27:20] + wire _T_9419 = _T_4668 & ic_tag_valid_out_1_48; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9625 = _T_9624 | _T_9419; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_49; // @[Reg.scala 27:20] + wire _T_9421 = _T_4669 & ic_tag_valid_out_1_49; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9626 = _T_9625 | _T_9421; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_50; // @[Reg.scala 27:20] + wire _T_9423 = _T_4670 & ic_tag_valid_out_1_50; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9627 = _T_9626 | _T_9423; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_51; // @[Reg.scala 27:20] + wire _T_9425 = _T_4671 & ic_tag_valid_out_1_51; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9628 = _T_9627 | _T_9425; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_52; // @[Reg.scala 27:20] + wire _T_9427 = _T_4672 & ic_tag_valid_out_1_52; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9629 = _T_9628 | _T_9427; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_53; // @[Reg.scala 27:20] + wire _T_9429 = _T_4673 & ic_tag_valid_out_1_53; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9630 = _T_9629 | _T_9429; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_54; // @[Reg.scala 27:20] + wire _T_9431 = _T_4674 & ic_tag_valid_out_1_54; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9631 = _T_9630 | _T_9431; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_55; // @[Reg.scala 27:20] + wire _T_9433 = _T_4675 & ic_tag_valid_out_1_55; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9632 = _T_9631 | _T_9433; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_56; // @[Reg.scala 27:20] + wire _T_9435 = _T_4676 & ic_tag_valid_out_1_56; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9633 = _T_9632 | _T_9435; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_57; // @[Reg.scala 27:20] + wire _T_9437 = _T_4677 & ic_tag_valid_out_1_57; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9634 = _T_9633 | _T_9437; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_58; // @[Reg.scala 27:20] + wire _T_9439 = _T_4678 & ic_tag_valid_out_1_58; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9635 = _T_9634 | _T_9439; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_59; // @[Reg.scala 27:20] + wire _T_9441 = _T_4679 & ic_tag_valid_out_1_59; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9636 = _T_9635 | _T_9441; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_60; // @[Reg.scala 27:20] + wire _T_9443 = _T_4680 & ic_tag_valid_out_1_60; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9637 = _T_9636 | _T_9443; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_61; // @[Reg.scala 27:20] + wire _T_9445 = _T_4681 & ic_tag_valid_out_1_61; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9638 = _T_9637 | _T_9445; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_62; // @[Reg.scala 27:20] + wire _T_9447 = _T_4682 & ic_tag_valid_out_1_62; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9639 = _T_9638 | _T_9447; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_63; // @[Reg.scala 27:20] + wire _T_9449 = _T_4683 & ic_tag_valid_out_1_63; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9640 = _T_9639 | _T_9449; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_64; // @[Reg.scala 27:20] + wire _T_9451 = _T_4684 & ic_tag_valid_out_1_64; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9641 = _T_9640 | _T_9451; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_65; // @[Reg.scala 27:20] + wire _T_9453 = _T_4685 & ic_tag_valid_out_1_65; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9642 = _T_9641 | _T_9453; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_66; // @[Reg.scala 27:20] + wire _T_9455 = _T_4686 & ic_tag_valid_out_1_66; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9643 = _T_9642 | _T_9455; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_67; // @[Reg.scala 27:20] + wire _T_9457 = _T_4687 & ic_tag_valid_out_1_67; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9644 = _T_9643 | _T_9457; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_68; // @[Reg.scala 27:20] + wire _T_9459 = _T_4688 & ic_tag_valid_out_1_68; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9645 = _T_9644 | _T_9459; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_69; // @[Reg.scala 27:20] + wire _T_9461 = _T_4689 & ic_tag_valid_out_1_69; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9646 = _T_9645 | _T_9461; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_70; // @[Reg.scala 27:20] + wire _T_9463 = _T_4690 & ic_tag_valid_out_1_70; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9647 = _T_9646 | _T_9463; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_71; // @[Reg.scala 27:20] + wire _T_9465 = _T_4691 & ic_tag_valid_out_1_71; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9648 = _T_9647 | _T_9465; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_72; // @[Reg.scala 27:20] + wire _T_9467 = _T_4692 & ic_tag_valid_out_1_72; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9649 = _T_9648 | _T_9467; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_73; // @[Reg.scala 27:20] + wire _T_9469 = _T_4693 & ic_tag_valid_out_1_73; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9650 = _T_9649 | _T_9469; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_74; // @[Reg.scala 27:20] + wire _T_9471 = _T_4694 & ic_tag_valid_out_1_74; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9651 = _T_9650 | _T_9471; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_75; // @[Reg.scala 27:20] + wire _T_9473 = _T_4695 & ic_tag_valid_out_1_75; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9652 = _T_9651 | _T_9473; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_76; // @[Reg.scala 27:20] + wire _T_9475 = _T_4696 & ic_tag_valid_out_1_76; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9653 = _T_9652 | _T_9475; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_77; // @[Reg.scala 27:20] + wire _T_9477 = _T_4697 & ic_tag_valid_out_1_77; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9654 = _T_9653 | _T_9477; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_78; // @[Reg.scala 27:20] + wire _T_9479 = _T_4698 & ic_tag_valid_out_1_78; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9655 = _T_9654 | _T_9479; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_79; // @[Reg.scala 27:20] + wire _T_9481 = _T_4699 & ic_tag_valid_out_1_79; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9656 = _T_9655 | _T_9481; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_80; // @[Reg.scala 27:20] + wire _T_9483 = _T_4700 & ic_tag_valid_out_1_80; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9657 = _T_9656 | _T_9483; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_81; // @[Reg.scala 27:20] + wire _T_9485 = _T_4701 & ic_tag_valid_out_1_81; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9658 = _T_9657 | _T_9485; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_82; // @[Reg.scala 27:20] + wire _T_9487 = _T_4702 & ic_tag_valid_out_1_82; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9659 = _T_9658 | _T_9487; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_83; // @[Reg.scala 27:20] + wire _T_9489 = _T_4703 & ic_tag_valid_out_1_83; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9660 = _T_9659 | _T_9489; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_84; // @[Reg.scala 27:20] + wire _T_9491 = _T_4704 & ic_tag_valid_out_1_84; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9661 = _T_9660 | _T_9491; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_85; // @[Reg.scala 27:20] + wire _T_9493 = _T_4705 & ic_tag_valid_out_1_85; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9662 = _T_9661 | _T_9493; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_86; // @[Reg.scala 27:20] + wire _T_9495 = _T_4706 & ic_tag_valid_out_1_86; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9663 = _T_9662 | _T_9495; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_87; // @[Reg.scala 27:20] + wire _T_9497 = _T_4707 & ic_tag_valid_out_1_87; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9664 = _T_9663 | _T_9497; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_88; // @[Reg.scala 27:20] + wire _T_9499 = _T_4708 & ic_tag_valid_out_1_88; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9665 = _T_9664 | _T_9499; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_89; // @[Reg.scala 27:20] + wire _T_9501 = _T_4709 & ic_tag_valid_out_1_89; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9666 = _T_9665 | _T_9501; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_90; // @[Reg.scala 27:20] + wire _T_9503 = _T_4710 & ic_tag_valid_out_1_90; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9667 = _T_9666 | _T_9503; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_91; // @[Reg.scala 27:20] + wire _T_9505 = _T_4711 & ic_tag_valid_out_1_91; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9668 = _T_9667 | _T_9505; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_92; // @[Reg.scala 27:20] + wire _T_9507 = _T_4712 & ic_tag_valid_out_1_92; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9669 = _T_9668 | _T_9507; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_93; // @[Reg.scala 27:20] + wire _T_9509 = _T_4713 & ic_tag_valid_out_1_93; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9670 = _T_9669 | _T_9509; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_94; // @[Reg.scala 27:20] + wire _T_9511 = _T_4714 & ic_tag_valid_out_1_94; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9671 = _T_9670 | _T_9511; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_95; // @[Reg.scala 27:20] + wire _T_9513 = _T_4715 & ic_tag_valid_out_1_95; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9672 = _T_9671 | _T_9513; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_96; // @[Reg.scala 27:20] + wire _T_9515 = _T_4716 & ic_tag_valid_out_1_96; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9673 = _T_9672 | _T_9515; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_97; // @[Reg.scala 27:20] + wire _T_9517 = _T_4717 & ic_tag_valid_out_1_97; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9674 = _T_9673 | _T_9517; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_98; // @[Reg.scala 27:20] + wire _T_9519 = _T_4718 & ic_tag_valid_out_1_98; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9675 = _T_9674 | _T_9519; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_99; // @[Reg.scala 27:20] + wire _T_9521 = _T_4719 & ic_tag_valid_out_1_99; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9676 = _T_9675 | _T_9521; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_100; // @[Reg.scala 27:20] + wire _T_9523 = _T_4720 & ic_tag_valid_out_1_100; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9677 = _T_9676 | _T_9523; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_101; // @[Reg.scala 27:20] + wire _T_9525 = _T_4721 & ic_tag_valid_out_1_101; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9678 = _T_9677 | _T_9525; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_102; // @[Reg.scala 27:20] + wire _T_9527 = _T_4722 & ic_tag_valid_out_1_102; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9679 = _T_9678 | _T_9527; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_103; // @[Reg.scala 27:20] + wire _T_9529 = _T_4723 & ic_tag_valid_out_1_103; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9680 = _T_9679 | _T_9529; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_104; // @[Reg.scala 27:20] + wire _T_9531 = _T_4724 & ic_tag_valid_out_1_104; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9681 = _T_9680 | _T_9531; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_105; // @[Reg.scala 27:20] + wire _T_9533 = _T_4725 & ic_tag_valid_out_1_105; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9682 = _T_9681 | _T_9533; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_106; // @[Reg.scala 27:20] + wire _T_9535 = _T_4726 & ic_tag_valid_out_1_106; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9683 = _T_9682 | _T_9535; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_107; // @[Reg.scala 27:20] + wire _T_9537 = _T_4727 & ic_tag_valid_out_1_107; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9684 = _T_9683 | _T_9537; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_108; // @[Reg.scala 27:20] + wire _T_9539 = _T_4728 & ic_tag_valid_out_1_108; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9685 = _T_9684 | _T_9539; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_109; // @[Reg.scala 27:20] + wire _T_9541 = _T_4729 & ic_tag_valid_out_1_109; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9686 = _T_9685 | _T_9541; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_110; // @[Reg.scala 27:20] + wire _T_9543 = _T_4730 & ic_tag_valid_out_1_110; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9687 = _T_9686 | _T_9543; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_111; // @[Reg.scala 27:20] + wire _T_9545 = _T_4731 & ic_tag_valid_out_1_111; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9688 = _T_9687 | _T_9545; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_112; // @[Reg.scala 27:20] + wire _T_9547 = _T_4732 & ic_tag_valid_out_1_112; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9689 = _T_9688 | _T_9547; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_113; // @[Reg.scala 27:20] + wire _T_9549 = _T_4733 & ic_tag_valid_out_1_113; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9690 = _T_9689 | _T_9549; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_114; // @[Reg.scala 27:20] + wire _T_9551 = _T_4734 & ic_tag_valid_out_1_114; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9691 = _T_9690 | _T_9551; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_115; // @[Reg.scala 27:20] + wire _T_9553 = _T_4735 & ic_tag_valid_out_1_115; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9692 = _T_9691 | _T_9553; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_116; // @[Reg.scala 27:20] + wire _T_9555 = _T_4736 & ic_tag_valid_out_1_116; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9693 = _T_9692 | _T_9555; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_117; // @[Reg.scala 27:20] + wire _T_9557 = _T_4737 & ic_tag_valid_out_1_117; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9694 = _T_9693 | _T_9557; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_118; // @[Reg.scala 27:20] + wire _T_9559 = _T_4738 & ic_tag_valid_out_1_118; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9695 = _T_9694 | _T_9559; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_119; // @[Reg.scala 27:20] + wire _T_9561 = _T_4739 & ic_tag_valid_out_1_119; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9696 = _T_9695 | _T_9561; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_120; // @[Reg.scala 27:20] + wire _T_9563 = _T_4740 & ic_tag_valid_out_1_120; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9697 = _T_9696 | _T_9563; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_121; // @[Reg.scala 27:20] + wire _T_9565 = _T_4741 & ic_tag_valid_out_1_121; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9698 = _T_9697 | _T_9565; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_122; // @[Reg.scala 27:20] + wire _T_9567 = _T_4742 & ic_tag_valid_out_1_122; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9699 = _T_9698 | _T_9567; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_123; // @[Reg.scala 27:20] + wire _T_9569 = _T_4743 & ic_tag_valid_out_1_123; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9700 = _T_9699 | _T_9569; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_124; // @[Reg.scala 27:20] + wire _T_9571 = _T_4744 & ic_tag_valid_out_1_124; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9701 = _T_9700 | _T_9571; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_125; // @[Reg.scala 27:20] + wire _T_9573 = _T_4745 & ic_tag_valid_out_1_125; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9702 = _T_9701 | _T_9573; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_126; // @[Reg.scala 27:20] + wire _T_9575 = _T_4746 & ic_tag_valid_out_1_126; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9703 = _T_9702 | _T_9575; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_1_127; // @[Reg.scala 27:20] + wire _T_9577 = _T_4747 & ic_tag_valid_out_1_127; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9704 = _T_9703 | _T_9577; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_0; // @[Reg.scala 27:20] + wire _T_8940 = _T_4620 & ic_tag_valid_out_0_0; // @[el2_ifu_mem_ctl.scala 764:8] + reg ic_tag_valid_out_0_1; // @[Reg.scala 27:20] + wire _T_8942 = _T_4621 & ic_tag_valid_out_0_1; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9195 = _T_8940 | _T_8942; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_2; // @[Reg.scala 27:20] + wire _T_8944 = _T_4622 & ic_tag_valid_out_0_2; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9196 = _T_9195 | _T_8944; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_3; // @[Reg.scala 27:20] + wire _T_8946 = _T_4623 & ic_tag_valid_out_0_3; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9197 = _T_9196 | _T_8946; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_4; // @[Reg.scala 27:20] + wire _T_8948 = _T_4624 & ic_tag_valid_out_0_4; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9198 = _T_9197 | _T_8948; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_5; // @[Reg.scala 27:20] + wire _T_8950 = _T_4625 & ic_tag_valid_out_0_5; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9199 = _T_9198 | _T_8950; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_6; // @[Reg.scala 27:20] + wire _T_8952 = _T_4626 & ic_tag_valid_out_0_6; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9200 = _T_9199 | _T_8952; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_7; // @[Reg.scala 27:20] + wire _T_8954 = _T_4627 & ic_tag_valid_out_0_7; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9201 = _T_9200 | _T_8954; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_8; // @[Reg.scala 27:20] + wire _T_8956 = _T_4628 & ic_tag_valid_out_0_8; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9202 = _T_9201 | _T_8956; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_9; // @[Reg.scala 27:20] + wire _T_8958 = _T_4629 & ic_tag_valid_out_0_9; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9203 = _T_9202 | _T_8958; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_10; // @[Reg.scala 27:20] + wire _T_8960 = _T_4630 & ic_tag_valid_out_0_10; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9204 = _T_9203 | _T_8960; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_11; // @[Reg.scala 27:20] + wire _T_8962 = _T_4631 & ic_tag_valid_out_0_11; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9205 = _T_9204 | _T_8962; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_12; // @[Reg.scala 27:20] + wire _T_8964 = _T_4632 & ic_tag_valid_out_0_12; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9206 = _T_9205 | _T_8964; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_13; // @[Reg.scala 27:20] + wire _T_8966 = _T_4633 & ic_tag_valid_out_0_13; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9207 = _T_9206 | _T_8966; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_14; // @[Reg.scala 27:20] + wire _T_8968 = _T_4634 & ic_tag_valid_out_0_14; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9208 = _T_9207 | _T_8968; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_15; // @[Reg.scala 27:20] + wire _T_8970 = _T_4635 & ic_tag_valid_out_0_15; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9209 = _T_9208 | _T_8970; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_16; // @[Reg.scala 27:20] + wire _T_8972 = _T_4636 & ic_tag_valid_out_0_16; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9210 = _T_9209 | _T_8972; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_17; // @[Reg.scala 27:20] + wire _T_8974 = _T_4637 & ic_tag_valid_out_0_17; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9211 = _T_9210 | _T_8974; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_18; // @[Reg.scala 27:20] + wire _T_8976 = _T_4638 & ic_tag_valid_out_0_18; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9212 = _T_9211 | _T_8976; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_19; // @[Reg.scala 27:20] + wire _T_8978 = _T_4639 & ic_tag_valid_out_0_19; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9213 = _T_9212 | _T_8978; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_20; // @[Reg.scala 27:20] + wire _T_8980 = _T_4640 & ic_tag_valid_out_0_20; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9214 = _T_9213 | _T_8980; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_21; // @[Reg.scala 27:20] + wire _T_8982 = _T_4641 & ic_tag_valid_out_0_21; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9215 = _T_9214 | _T_8982; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_22; // @[Reg.scala 27:20] + wire _T_8984 = _T_4642 & ic_tag_valid_out_0_22; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9216 = _T_9215 | _T_8984; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_23; // @[Reg.scala 27:20] + wire _T_8986 = _T_4643 & ic_tag_valid_out_0_23; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9217 = _T_9216 | _T_8986; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_24; // @[Reg.scala 27:20] + wire _T_8988 = _T_4644 & ic_tag_valid_out_0_24; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9218 = _T_9217 | _T_8988; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_25; // @[Reg.scala 27:20] + wire _T_8990 = _T_4645 & ic_tag_valid_out_0_25; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9219 = _T_9218 | _T_8990; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_26; // @[Reg.scala 27:20] + wire _T_8992 = _T_4646 & ic_tag_valid_out_0_26; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9220 = _T_9219 | _T_8992; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_27; // @[Reg.scala 27:20] + wire _T_8994 = _T_4647 & ic_tag_valid_out_0_27; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9221 = _T_9220 | _T_8994; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_28; // @[Reg.scala 27:20] + wire _T_8996 = _T_4648 & ic_tag_valid_out_0_28; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9222 = _T_9221 | _T_8996; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_29; // @[Reg.scala 27:20] + wire _T_8998 = _T_4649 & ic_tag_valid_out_0_29; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9223 = _T_9222 | _T_8998; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_30; // @[Reg.scala 27:20] + wire _T_9000 = _T_4650 & ic_tag_valid_out_0_30; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9224 = _T_9223 | _T_9000; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_31; // @[Reg.scala 27:20] + wire _T_9002 = _T_4651 & ic_tag_valid_out_0_31; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9225 = _T_9224 | _T_9002; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_32; // @[Reg.scala 27:20] + wire _T_9004 = _T_4652 & ic_tag_valid_out_0_32; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9226 = _T_9225 | _T_9004; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_33; // @[Reg.scala 27:20] + wire _T_9006 = _T_4653 & ic_tag_valid_out_0_33; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9227 = _T_9226 | _T_9006; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_34; // @[Reg.scala 27:20] + wire _T_9008 = _T_4654 & ic_tag_valid_out_0_34; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9228 = _T_9227 | _T_9008; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_35; // @[Reg.scala 27:20] + wire _T_9010 = _T_4655 & ic_tag_valid_out_0_35; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9229 = _T_9228 | _T_9010; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_36; // @[Reg.scala 27:20] + wire _T_9012 = _T_4656 & ic_tag_valid_out_0_36; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9230 = _T_9229 | _T_9012; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_37; // @[Reg.scala 27:20] + wire _T_9014 = _T_4657 & ic_tag_valid_out_0_37; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9231 = _T_9230 | _T_9014; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_38; // @[Reg.scala 27:20] + wire _T_9016 = _T_4658 & ic_tag_valid_out_0_38; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9232 = _T_9231 | _T_9016; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_39; // @[Reg.scala 27:20] + wire _T_9018 = _T_4659 & ic_tag_valid_out_0_39; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9233 = _T_9232 | _T_9018; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_40; // @[Reg.scala 27:20] + wire _T_9020 = _T_4660 & ic_tag_valid_out_0_40; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9234 = _T_9233 | _T_9020; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_41; // @[Reg.scala 27:20] + wire _T_9022 = _T_4661 & ic_tag_valid_out_0_41; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9235 = _T_9234 | _T_9022; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_42; // @[Reg.scala 27:20] + wire _T_9024 = _T_4662 & ic_tag_valid_out_0_42; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9236 = _T_9235 | _T_9024; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_43; // @[Reg.scala 27:20] + wire _T_9026 = _T_4663 & ic_tag_valid_out_0_43; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9237 = _T_9236 | _T_9026; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_44; // @[Reg.scala 27:20] + wire _T_9028 = _T_4664 & ic_tag_valid_out_0_44; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9238 = _T_9237 | _T_9028; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_45; // @[Reg.scala 27:20] + wire _T_9030 = _T_4665 & ic_tag_valid_out_0_45; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9239 = _T_9238 | _T_9030; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_46; // @[Reg.scala 27:20] + wire _T_9032 = _T_4666 & ic_tag_valid_out_0_46; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9240 = _T_9239 | _T_9032; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_47; // @[Reg.scala 27:20] + wire _T_9034 = _T_4667 & ic_tag_valid_out_0_47; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9241 = _T_9240 | _T_9034; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_48; // @[Reg.scala 27:20] + wire _T_9036 = _T_4668 & ic_tag_valid_out_0_48; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9242 = _T_9241 | _T_9036; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_49; // @[Reg.scala 27:20] + wire _T_9038 = _T_4669 & ic_tag_valid_out_0_49; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9243 = _T_9242 | _T_9038; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_50; // @[Reg.scala 27:20] + wire _T_9040 = _T_4670 & ic_tag_valid_out_0_50; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9244 = _T_9243 | _T_9040; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_51; // @[Reg.scala 27:20] + wire _T_9042 = _T_4671 & ic_tag_valid_out_0_51; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9245 = _T_9244 | _T_9042; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_52; // @[Reg.scala 27:20] + wire _T_9044 = _T_4672 & ic_tag_valid_out_0_52; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9246 = _T_9245 | _T_9044; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_53; // @[Reg.scala 27:20] + wire _T_9046 = _T_4673 & ic_tag_valid_out_0_53; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9247 = _T_9246 | _T_9046; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_54; // @[Reg.scala 27:20] + wire _T_9048 = _T_4674 & ic_tag_valid_out_0_54; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9248 = _T_9247 | _T_9048; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_55; // @[Reg.scala 27:20] + wire _T_9050 = _T_4675 & ic_tag_valid_out_0_55; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9249 = _T_9248 | _T_9050; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_56; // @[Reg.scala 27:20] + wire _T_9052 = _T_4676 & ic_tag_valid_out_0_56; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9250 = _T_9249 | _T_9052; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_57; // @[Reg.scala 27:20] + wire _T_9054 = _T_4677 & ic_tag_valid_out_0_57; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9251 = _T_9250 | _T_9054; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_58; // @[Reg.scala 27:20] + wire _T_9056 = _T_4678 & ic_tag_valid_out_0_58; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9252 = _T_9251 | _T_9056; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_59; // @[Reg.scala 27:20] + wire _T_9058 = _T_4679 & ic_tag_valid_out_0_59; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9253 = _T_9252 | _T_9058; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_60; // @[Reg.scala 27:20] + wire _T_9060 = _T_4680 & ic_tag_valid_out_0_60; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9254 = _T_9253 | _T_9060; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_61; // @[Reg.scala 27:20] + wire _T_9062 = _T_4681 & ic_tag_valid_out_0_61; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9255 = _T_9254 | _T_9062; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_62; // @[Reg.scala 27:20] + wire _T_9064 = _T_4682 & ic_tag_valid_out_0_62; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9256 = _T_9255 | _T_9064; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_63; // @[Reg.scala 27:20] + wire _T_9066 = _T_4683 & ic_tag_valid_out_0_63; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9257 = _T_9256 | _T_9066; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_64; // @[Reg.scala 27:20] + wire _T_9068 = _T_4684 & ic_tag_valid_out_0_64; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9258 = _T_9257 | _T_9068; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_65; // @[Reg.scala 27:20] + wire _T_9070 = _T_4685 & ic_tag_valid_out_0_65; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9259 = _T_9258 | _T_9070; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_66; // @[Reg.scala 27:20] + wire _T_9072 = _T_4686 & ic_tag_valid_out_0_66; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9260 = _T_9259 | _T_9072; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_67; // @[Reg.scala 27:20] + wire _T_9074 = _T_4687 & ic_tag_valid_out_0_67; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9261 = _T_9260 | _T_9074; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_68; // @[Reg.scala 27:20] + wire _T_9076 = _T_4688 & ic_tag_valid_out_0_68; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9262 = _T_9261 | _T_9076; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_69; // @[Reg.scala 27:20] + wire _T_9078 = _T_4689 & ic_tag_valid_out_0_69; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9263 = _T_9262 | _T_9078; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_70; // @[Reg.scala 27:20] + wire _T_9080 = _T_4690 & ic_tag_valid_out_0_70; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9264 = _T_9263 | _T_9080; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_71; // @[Reg.scala 27:20] + wire _T_9082 = _T_4691 & ic_tag_valid_out_0_71; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9265 = _T_9264 | _T_9082; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_72; // @[Reg.scala 27:20] + wire _T_9084 = _T_4692 & ic_tag_valid_out_0_72; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9266 = _T_9265 | _T_9084; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_73; // @[Reg.scala 27:20] + wire _T_9086 = _T_4693 & ic_tag_valid_out_0_73; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9267 = _T_9266 | _T_9086; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_74; // @[Reg.scala 27:20] + wire _T_9088 = _T_4694 & ic_tag_valid_out_0_74; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9268 = _T_9267 | _T_9088; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_75; // @[Reg.scala 27:20] + wire _T_9090 = _T_4695 & ic_tag_valid_out_0_75; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9269 = _T_9268 | _T_9090; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_76; // @[Reg.scala 27:20] + wire _T_9092 = _T_4696 & ic_tag_valid_out_0_76; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9270 = _T_9269 | _T_9092; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_77; // @[Reg.scala 27:20] + wire _T_9094 = _T_4697 & ic_tag_valid_out_0_77; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9271 = _T_9270 | _T_9094; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_78; // @[Reg.scala 27:20] + wire _T_9096 = _T_4698 & ic_tag_valid_out_0_78; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9272 = _T_9271 | _T_9096; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_79; // @[Reg.scala 27:20] + wire _T_9098 = _T_4699 & ic_tag_valid_out_0_79; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9273 = _T_9272 | _T_9098; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_80; // @[Reg.scala 27:20] + wire _T_9100 = _T_4700 & ic_tag_valid_out_0_80; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9274 = _T_9273 | _T_9100; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_81; // @[Reg.scala 27:20] + wire _T_9102 = _T_4701 & ic_tag_valid_out_0_81; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9275 = _T_9274 | _T_9102; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_82; // @[Reg.scala 27:20] + wire _T_9104 = _T_4702 & ic_tag_valid_out_0_82; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9276 = _T_9275 | _T_9104; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_83; // @[Reg.scala 27:20] + wire _T_9106 = _T_4703 & ic_tag_valid_out_0_83; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9277 = _T_9276 | _T_9106; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_84; // @[Reg.scala 27:20] + wire _T_9108 = _T_4704 & ic_tag_valid_out_0_84; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9278 = _T_9277 | _T_9108; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_85; // @[Reg.scala 27:20] + wire _T_9110 = _T_4705 & ic_tag_valid_out_0_85; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9279 = _T_9278 | _T_9110; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_86; // @[Reg.scala 27:20] + wire _T_9112 = _T_4706 & ic_tag_valid_out_0_86; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9280 = _T_9279 | _T_9112; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_87; // @[Reg.scala 27:20] + wire _T_9114 = _T_4707 & ic_tag_valid_out_0_87; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9281 = _T_9280 | _T_9114; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_88; // @[Reg.scala 27:20] + wire _T_9116 = _T_4708 & ic_tag_valid_out_0_88; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9282 = _T_9281 | _T_9116; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_89; // @[Reg.scala 27:20] + wire _T_9118 = _T_4709 & ic_tag_valid_out_0_89; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9283 = _T_9282 | _T_9118; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_90; // @[Reg.scala 27:20] + wire _T_9120 = _T_4710 & ic_tag_valid_out_0_90; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9284 = _T_9283 | _T_9120; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_91; // @[Reg.scala 27:20] + wire _T_9122 = _T_4711 & ic_tag_valid_out_0_91; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9285 = _T_9284 | _T_9122; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_92; // @[Reg.scala 27:20] + wire _T_9124 = _T_4712 & ic_tag_valid_out_0_92; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9286 = _T_9285 | _T_9124; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_93; // @[Reg.scala 27:20] + wire _T_9126 = _T_4713 & ic_tag_valid_out_0_93; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9287 = _T_9286 | _T_9126; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_94; // @[Reg.scala 27:20] + wire _T_9128 = _T_4714 & ic_tag_valid_out_0_94; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9288 = _T_9287 | _T_9128; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_95; // @[Reg.scala 27:20] + wire _T_9130 = _T_4715 & ic_tag_valid_out_0_95; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9289 = _T_9288 | _T_9130; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_96; // @[Reg.scala 27:20] + wire _T_9132 = _T_4716 & ic_tag_valid_out_0_96; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9290 = _T_9289 | _T_9132; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_97; // @[Reg.scala 27:20] + wire _T_9134 = _T_4717 & ic_tag_valid_out_0_97; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9291 = _T_9290 | _T_9134; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_98; // @[Reg.scala 27:20] + wire _T_9136 = _T_4718 & ic_tag_valid_out_0_98; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9292 = _T_9291 | _T_9136; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_99; // @[Reg.scala 27:20] + wire _T_9138 = _T_4719 & ic_tag_valid_out_0_99; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9293 = _T_9292 | _T_9138; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_100; // @[Reg.scala 27:20] + wire _T_9140 = _T_4720 & ic_tag_valid_out_0_100; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9294 = _T_9293 | _T_9140; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_101; // @[Reg.scala 27:20] + wire _T_9142 = _T_4721 & ic_tag_valid_out_0_101; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9295 = _T_9294 | _T_9142; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_102; // @[Reg.scala 27:20] + wire _T_9144 = _T_4722 & ic_tag_valid_out_0_102; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9296 = _T_9295 | _T_9144; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_103; // @[Reg.scala 27:20] + wire _T_9146 = _T_4723 & ic_tag_valid_out_0_103; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9297 = _T_9296 | _T_9146; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_104; // @[Reg.scala 27:20] + wire _T_9148 = _T_4724 & ic_tag_valid_out_0_104; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9298 = _T_9297 | _T_9148; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_105; // @[Reg.scala 27:20] + wire _T_9150 = _T_4725 & ic_tag_valid_out_0_105; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9299 = _T_9298 | _T_9150; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_106; // @[Reg.scala 27:20] + wire _T_9152 = _T_4726 & ic_tag_valid_out_0_106; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9300 = _T_9299 | _T_9152; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_107; // @[Reg.scala 27:20] + wire _T_9154 = _T_4727 & ic_tag_valid_out_0_107; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9301 = _T_9300 | _T_9154; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_108; // @[Reg.scala 27:20] + wire _T_9156 = _T_4728 & ic_tag_valid_out_0_108; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9302 = _T_9301 | _T_9156; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_109; // @[Reg.scala 27:20] + wire _T_9158 = _T_4729 & ic_tag_valid_out_0_109; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9303 = _T_9302 | _T_9158; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_110; // @[Reg.scala 27:20] + wire _T_9160 = _T_4730 & ic_tag_valid_out_0_110; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9304 = _T_9303 | _T_9160; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_111; // @[Reg.scala 27:20] + wire _T_9162 = _T_4731 & ic_tag_valid_out_0_111; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9305 = _T_9304 | _T_9162; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_112; // @[Reg.scala 27:20] + wire _T_9164 = _T_4732 & ic_tag_valid_out_0_112; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9306 = _T_9305 | _T_9164; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_113; // @[Reg.scala 27:20] + wire _T_9166 = _T_4733 & ic_tag_valid_out_0_113; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9307 = _T_9306 | _T_9166; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_114; // @[Reg.scala 27:20] + wire _T_9168 = _T_4734 & ic_tag_valid_out_0_114; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9308 = _T_9307 | _T_9168; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_115; // @[Reg.scala 27:20] + wire _T_9170 = _T_4735 & ic_tag_valid_out_0_115; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9309 = _T_9308 | _T_9170; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_116; // @[Reg.scala 27:20] + wire _T_9172 = _T_4736 & ic_tag_valid_out_0_116; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9310 = _T_9309 | _T_9172; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_117; // @[Reg.scala 27:20] + wire _T_9174 = _T_4737 & ic_tag_valid_out_0_117; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9311 = _T_9310 | _T_9174; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_118; // @[Reg.scala 27:20] + wire _T_9176 = _T_4738 & ic_tag_valid_out_0_118; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9312 = _T_9311 | _T_9176; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_119; // @[Reg.scala 27:20] + wire _T_9178 = _T_4739 & ic_tag_valid_out_0_119; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9313 = _T_9312 | _T_9178; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_120; // @[Reg.scala 27:20] + wire _T_9180 = _T_4740 & ic_tag_valid_out_0_120; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9314 = _T_9313 | _T_9180; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_121; // @[Reg.scala 27:20] + wire _T_9182 = _T_4741 & ic_tag_valid_out_0_121; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9315 = _T_9314 | _T_9182; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_122; // @[Reg.scala 27:20] + wire _T_9184 = _T_4742 & ic_tag_valid_out_0_122; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9316 = _T_9315 | _T_9184; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_123; // @[Reg.scala 27:20] + wire _T_9186 = _T_4743 & ic_tag_valid_out_0_123; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9317 = _T_9316 | _T_9186; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_124; // @[Reg.scala 27:20] + wire _T_9188 = _T_4744 & ic_tag_valid_out_0_124; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9318 = _T_9317 | _T_9188; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_125; // @[Reg.scala 27:20] + wire _T_9190 = _T_4745 & ic_tag_valid_out_0_125; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9319 = _T_9318 | _T_9190; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_126; // @[Reg.scala 27:20] + wire _T_9192 = _T_4746 & ic_tag_valid_out_0_126; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9320 = _T_9319 | _T_9192; // @[el2_ifu_mem_ctl.scala 764:89] + reg ic_tag_valid_out_0_127; // @[Reg.scala 27:20] + wire _T_9194 = _T_4747 & ic_tag_valid_out_0_127; // @[el2_ifu_mem_ctl.scala 764:8] + wire _T_9321 = _T_9320 | _T_9194; // @[el2_ifu_mem_ctl.scala 764:89] + wire [1:0] ic_tag_valid_unq = {_T_9704,_T_9321}; // @[Cat.scala 29:58] + reg [1:0] ic_debug_way_ff; // @[el2_ifu_mem_ctl.scala 836:53] + reg ic_debug_rd_en_ff; // @[el2_ifu_mem_ctl.scala 838:54] + wire [1:0] _T_9744 = ic_debug_rd_en_ff ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_9745 = ic_debug_way_ff & _T_9744; // @[el2_ifu_mem_ctl.scala 819:67] + wire [1:0] _T_9746 = ic_tag_valid_unq & _T_9745; // @[el2_ifu_mem_ctl.scala 819:48] + wire ic_debug_tag_val_rd_out = |_T_9746; // @[el2_ifu_mem_ctl.scala 819:115] + wire [70:0] _T_1210 = {2'h0,io_ictag_debug_rd_data[25:21],32'h0,io_ictag_debug_rd_data[20:0],6'h0,way_status,3'h0,ic_debug_tag_val_rd_out}; // @[Cat.scala 29:58] + reg [70:0] _T_1211; // @[el2_ifu_mem_ctl.scala 355:63] + wire _T_1249 = ~ifu_byp_data_err_new; // @[el2_ifu_mem_ctl.scala 371:98] + wire sel_byp_data = _T_1253 & _T_1249; // @[el2_ifu_mem_ctl.scala 371:96] + wire [63:0] _T_1260 = fetch_req_iccm_f ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12] + wire [63:0] _T_1261 = _T_1260 & io_iccm_rd_data; // @[el2_ifu_mem_ctl.scala 378:69] + wire [63:0] _T_1263 = sel_byp_data ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12] + wire _T_2099 = ~ifu_fetch_addr_int_f[0]; // @[el2_ifu_mem_ctl.scala 447:31] + wire _T_1612 = ~ifu_fetch_addr_int_f[1]; // @[el2_ifu_mem_ctl.scala 443:38] + wire [3:0] byp_fetch_index_inc_0 = {byp_fetch_index_inc,1'h0}; // @[Cat.scala 29:58] + wire _T_1613 = byp_fetch_index_inc_0 == 4'h0; // @[el2_ifu_mem_ctl.scala 444:73] + wire [15:0] _T_1661 = _T_1613 ? ic_miss_buff_data_0[15:0] : 16'h0; // @[Mux.scala 27:72] + wire _T_1616 = byp_fetch_index_inc_0 == 4'h1; // @[el2_ifu_mem_ctl.scala 444:73] + wire [15:0] _T_1662 = _T_1616 ? ic_miss_buff_data_1[15:0] : 16'h0; // @[Mux.scala 27:72] + wire [15:0] _T_1677 = _T_1661 | _T_1662; // @[Mux.scala 27:72] + wire _T_1619 = byp_fetch_index_inc_0 == 4'h2; // @[el2_ifu_mem_ctl.scala 444:73] + wire [15:0] _T_1663 = _T_1619 ? ic_miss_buff_data_2[15:0] : 16'h0; // @[Mux.scala 27:72] + wire [15:0] _T_1678 = _T_1677 | _T_1663; // @[Mux.scala 27:72] + wire _T_1622 = byp_fetch_index_inc_0 == 4'h3; // @[el2_ifu_mem_ctl.scala 444:73] + wire [15:0] _T_1664 = _T_1622 ? ic_miss_buff_data_3[15:0] : 16'h0; // @[Mux.scala 27:72] + wire [15:0] _T_1679 = _T_1678 | _T_1664; // @[Mux.scala 27:72] + wire _T_1625 = byp_fetch_index_inc_0 == 4'h4; // @[el2_ifu_mem_ctl.scala 444:73] + wire [15:0] _T_1665 = _T_1625 ? ic_miss_buff_data_4[15:0] : 16'h0; // @[Mux.scala 27:72] + wire [15:0] _T_1680 = _T_1679 | _T_1665; // @[Mux.scala 27:72] + wire _T_1628 = byp_fetch_index_inc_0 == 4'h5; // @[el2_ifu_mem_ctl.scala 444:73] + wire [15:0] _T_1666 = _T_1628 ? ic_miss_buff_data_5[15:0] : 16'h0; // @[Mux.scala 27:72] + wire [15:0] _T_1681 = _T_1680 | _T_1666; // @[Mux.scala 27:72] + wire _T_1631 = byp_fetch_index_inc_0 == 4'h6; // @[el2_ifu_mem_ctl.scala 444:73] + wire [15:0] _T_1667 = _T_1631 ? ic_miss_buff_data_6[15:0] : 16'h0; // @[Mux.scala 27:72] + wire [15:0] _T_1682 = _T_1681 | _T_1667; // @[Mux.scala 27:72] + wire _T_1634 = byp_fetch_index_inc_0 == 4'h7; // @[el2_ifu_mem_ctl.scala 444:73] + wire [15:0] _T_1668 = _T_1634 ? ic_miss_buff_data_7[15:0] : 16'h0; // @[Mux.scala 27:72] + wire [15:0] _T_1683 = _T_1682 | _T_1668; // @[Mux.scala 27:72] + wire _T_1637 = byp_fetch_index_inc_0 == 4'h8; // @[el2_ifu_mem_ctl.scala 444:73] + wire [15:0] _T_1669 = _T_1637 ? ic_miss_buff_data_8[15:0] : 16'h0; // @[Mux.scala 27:72] + wire [15:0] _T_1684 = _T_1683 | _T_1669; // @[Mux.scala 27:72] + wire _T_1640 = byp_fetch_index_inc_0 == 4'h9; // @[el2_ifu_mem_ctl.scala 444:73] + wire [15:0] _T_1670 = _T_1640 ? ic_miss_buff_data_9[15:0] : 16'h0; // @[Mux.scala 27:72] + wire [15:0] _T_1685 = _T_1684 | _T_1670; // @[Mux.scala 27:72] + wire _T_1643 = byp_fetch_index_inc_0 == 4'ha; // @[el2_ifu_mem_ctl.scala 444:73] + wire [15:0] _T_1671 = _T_1643 ? ic_miss_buff_data_10[15:0] : 16'h0; // @[Mux.scala 27:72] + wire [15:0] _T_1686 = _T_1685 | _T_1671; // @[Mux.scala 27:72] + wire _T_1646 = byp_fetch_index_inc_0 == 4'hb; // @[el2_ifu_mem_ctl.scala 444:73] + wire [15:0] _T_1672 = _T_1646 ? ic_miss_buff_data_11[15:0] : 16'h0; // @[Mux.scala 27:72] + wire [15:0] _T_1687 = _T_1686 | _T_1672; // @[Mux.scala 27:72] + wire _T_1649 = byp_fetch_index_inc_0 == 4'hc; // @[el2_ifu_mem_ctl.scala 444:73] + wire [15:0] _T_1673 = _T_1649 ? ic_miss_buff_data_12[15:0] : 16'h0; // @[Mux.scala 27:72] + wire [15:0] _T_1688 = _T_1687 | _T_1673; // @[Mux.scala 27:72] + wire _T_1652 = byp_fetch_index_inc_0 == 4'hd; // @[el2_ifu_mem_ctl.scala 444:73] + wire [15:0] _T_1674 = _T_1652 ? ic_miss_buff_data_13[15:0] : 16'h0; // @[Mux.scala 27:72] + wire [15:0] _T_1689 = _T_1688 | _T_1674; // @[Mux.scala 27:72] + wire _T_1655 = byp_fetch_index_inc_0 == 4'he; // @[el2_ifu_mem_ctl.scala 444:73] + wire [15:0] _T_1675 = _T_1655 ? ic_miss_buff_data_14[15:0] : 16'h0; // @[Mux.scala 27:72] + wire [15:0] _T_1690 = _T_1689 | _T_1675; // @[Mux.scala 27:72] + wire _T_1658 = byp_fetch_index_inc_0 == 4'hf; // @[el2_ifu_mem_ctl.scala 444:73] + wire [15:0] _T_1676 = _T_1658 ? ic_miss_buff_data_15[15:0] : 16'h0; // @[Mux.scala 27:72] + wire [15:0] _T_1691 = _T_1690 | _T_1676; // @[Mux.scala 27:72] + wire [3:0] byp_fetch_index_1 = {ifu_fetch_addr_int_f[4:2],1'h1}; // @[Cat.scala 29:58] + wire _T_1693 = byp_fetch_index_1 == 4'h0; // @[el2_ifu_mem_ctl.scala 444:179] + wire [31:0] _T_1741 = _T_1693 ? ic_miss_buff_data_0 : 32'h0; // @[Mux.scala 27:72] + wire _T_1696 = byp_fetch_index_1 == 4'h1; // @[el2_ifu_mem_ctl.scala 444:179] + wire [31:0] _T_1742 = _T_1696 ? ic_miss_buff_data_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1757 = _T_1741 | _T_1742; // @[Mux.scala 27:72] + wire _T_1699 = byp_fetch_index_1 == 4'h2; // @[el2_ifu_mem_ctl.scala 444:179] + wire [31:0] _T_1743 = _T_1699 ? ic_miss_buff_data_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1758 = _T_1757 | _T_1743; // @[Mux.scala 27:72] + wire _T_1702 = byp_fetch_index_1 == 4'h3; // @[el2_ifu_mem_ctl.scala 444:179] + wire [31:0] _T_1744 = _T_1702 ? ic_miss_buff_data_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1759 = _T_1758 | _T_1744; // @[Mux.scala 27:72] + wire _T_1705 = byp_fetch_index_1 == 4'h4; // @[el2_ifu_mem_ctl.scala 444:179] + wire [31:0] _T_1745 = _T_1705 ? ic_miss_buff_data_4 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1760 = _T_1759 | _T_1745; // @[Mux.scala 27:72] + wire _T_1708 = byp_fetch_index_1 == 4'h5; // @[el2_ifu_mem_ctl.scala 444:179] + wire [31:0] _T_1746 = _T_1708 ? ic_miss_buff_data_5 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1761 = _T_1760 | _T_1746; // @[Mux.scala 27:72] + wire _T_1711 = byp_fetch_index_1 == 4'h6; // @[el2_ifu_mem_ctl.scala 444:179] + wire [31:0] _T_1747 = _T_1711 ? ic_miss_buff_data_6 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1762 = _T_1761 | _T_1747; // @[Mux.scala 27:72] + wire _T_1714 = byp_fetch_index_1 == 4'h7; // @[el2_ifu_mem_ctl.scala 444:179] + wire [31:0] _T_1748 = _T_1714 ? ic_miss_buff_data_7 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1763 = _T_1762 | _T_1748; // @[Mux.scala 27:72] + wire _T_1717 = byp_fetch_index_1 == 4'h8; // @[el2_ifu_mem_ctl.scala 444:179] + wire [31:0] _T_1749 = _T_1717 ? ic_miss_buff_data_8 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1764 = _T_1763 | _T_1749; // @[Mux.scala 27:72] + wire _T_1720 = byp_fetch_index_1 == 4'h9; // @[el2_ifu_mem_ctl.scala 444:179] + wire [31:0] _T_1750 = _T_1720 ? ic_miss_buff_data_9 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1765 = _T_1764 | _T_1750; // @[Mux.scala 27:72] + wire _T_1723 = byp_fetch_index_1 == 4'ha; // @[el2_ifu_mem_ctl.scala 444:179] + wire [31:0] _T_1751 = _T_1723 ? ic_miss_buff_data_10 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1766 = _T_1765 | _T_1751; // @[Mux.scala 27:72] + wire _T_1726 = byp_fetch_index_1 == 4'hb; // @[el2_ifu_mem_ctl.scala 444:179] + wire [31:0] _T_1752 = _T_1726 ? ic_miss_buff_data_11 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1767 = _T_1766 | _T_1752; // @[Mux.scala 27:72] + wire _T_1729 = byp_fetch_index_1 == 4'hc; // @[el2_ifu_mem_ctl.scala 444:179] + wire [31:0] _T_1753 = _T_1729 ? ic_miss_buff_data_12 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1768 = _T_1767 | _T_1753; // @[Mux.scala 27:72] + wire _T_1732 = byp_fetch_index_1 == 4'hd; // @[el2_ifu_mem_ctl.scala 444:179] + wire [31:0] _T_1754 = _T_1732 ? ic_miss_buff_data_13 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1769 = _T_1768 | _T_1754; // @[Mux.scala 27:72] + wire _T_1735 = byp_fetch_index_1 == 4'he; // @[el2_ifu_mem_ctl.scala 444:179] + wire [31:0] _T_1755 = _T_1735 ? ic_miss_buff_data_14 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1770 = _T_1769 | _T_1755; // @[Mux.scala 27:72] + wire _T_1738 = byp_fetch_index_1 == 4'hf; // @[el2_ifu_mem_ctl.scala 444:179] + wire [31:0] _T_1756 = _T_1738 ? ic_miss_buff_data_15 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1771 = _T_1770 | _T_1756; // @[Mux.scala 27:72] + wire [3:0] byp_fetch_index_0 = {ifu_fetch_addr_int_f[4:2],1'h0}; // @[Cat.scala 29:58] + wire _T_1773 = byp_fetch_index_0 == 4'h0; // @[el2_ifu_mem_ctl.scala 444:285] + wire [31:0] _T_1821 = _T_1773 ? ic_miss_buff_data_0 : 32'h0; // @[Mux.scala 27:72] + wire _T_1776 = byp_fetch_index_0 == 4'h1; // @[el2_ifu_mem_ctl.scala 444:285] + wire [31:0] _T_1822 = _T_1776 ? ic_miss_buff_data_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1837 = _T_1821 | _T_1822; // @[Mux.scala 27:72] + wire _T_1779 = byp_fetch_index_0 == 4'h2; // @[el2_ifu_mem_ctl.scala 444:285] + wire [31:0] _T_1823 = _T_1779 ? ic_miss_buff_data_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1838 = _T_1837 | _T_1823; // @[Mux.scala 27:72] + wire _T_1782 = byp_fetch_index_0 == 4'h3; // @[el2_ifu_mem_ctl.scala 444:285] + wire [31:0] _T_1824 = _T_1782 ? ic_miss_buff_data_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1839 = _T_1838 | _T_1824; // @[Mux.scala 27:72] + wire _T_1785 = byp_fetch_index_0 == 4'h4; // @[el2_ifu_mem_ctl.scala 444:285] + wire [31:0] _T_1825 = _T_1785 ? ic_miss_buff_data_4 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1840 = _T_1839 | _T_1825; // @[Mux.scala 27:72] + wire _T_1788 = byp_fetch_index_0 == 4'h5; // @[el2_ifu_mem_ctl.scala 444:285] + wire [31:0] _T_1826 = _T_1788 ? ic_miss_buff_data_5 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1841 = _T_1840 | _T_1826; // @[Mux.scala 27:72] + wire _T_1791 = byp_fetch_index_0 == 4'h6; // @[el2_ifu_mem_ctl.scala 444:285] + wire [31:0] _T_1827 = _T_1791 ? ic_miss_buff_data_6 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1842 = _T_1841 | _T_1827; // @[Mux.scala 27:72] + wire _T_1794 = byp_fetch_index_0 == 4'h7; // @[el2_ifu_mem_ctl.scala 444:285] + wire [31:0] _T_1828 = _T_1794 ? ic_miss_buff_data_7 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1843 = _T_1842 | _T_1828; // @[Mux.scala 27:72] + wire _T_1797 = byp_fetch_index_0 == 4'h8; // @[el2_ifu_mem_ctl.scala 444:285] + wire [31:0] _T_1829 = _T_1797 ? ic_miss_buff_data_8 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1844 = _T_1843 | _T_1829; // @[Mux.scala 27:72] + wire _T_1800 = byp_fetch_index_0 == 4'h9; // @[el2_ifu_mem_ctl.scala 444:285] + wire [31:0] _T_1830 = _T_1800 ? ic_miss_buff_data_9 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1845 = _T_1844 | _T_1830; // @[Mux.scala 27:72] + wire _T_1803 = byp_fetch_index_0 == 4'ha; // @[el2_ifu_mem_ctl.scala 444:285] + wire [31:0] _T_1831 = _T_1803 ? ic_miss_buff_data_10 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1846 = _T_1845 | _T_1831; // @[Mux.scala 27:72] + wire _T_1806 = byp_fetch_index_0 == 4'hb; // @[el2_ifu_mem_ctl.scala 444:285] + wire [31:0] _T_1832 = _T_1806 ? ic_miss_buff_data_11 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1847 = _T_1846 | _T_1832; // @[Mux.scala 27:72] + wire _T_1809 = byp_fetch_index_0 == 4'hc; // @[el2_ifu_mem_ctl.scala 444:285] + wire [31:0] _T_1833 = _T_1809 ? ic_miss_buff_data_12 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1848 = _T_1847 | _T_1833; // @[Mux.scala 27:72] + wire _T_1812 = byp_fetch_index_0 == 4'hd; // @[el2_ifu_mem_ctl.scala 444:285] + wire [31:0] _T_1834 = _T_1812 ? ic_miss_buff_data_13 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1849 = _T_1848 | _T_1834; // @[Mux.scala 27:72] + wire _T_1815 = byp_fetch_index_0 == 4'he; // @[el2_ifu_mem_ctl.scala 444:285] + wire [31:0] _T_1835 = _T_1815 ? ic_miss_buff_data_14 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1850 = _T_1849 | _T_1835; // @[Mux.scala 27:72] + wire _T_1818 = byp_fetch_index_0 == 4'hf; // @[el2_ifu_mem_ctl.scala 444:285] + wire [31:0] _T_1836 = _T_1818 ? ic_miss_buff_data_15 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1851 = _T_1850 | _T_1836; // @[Mux.scala 27:72] + wire [79:0] _T_1854 = {_T_1691,_T_1771,_T_1851}; // @[Cat.scala 29:58] + wire [3:0] byp_fetch_index_inc_1 = {byp_fetch_index_inc,1'h1}; // @[Cat.scala 29:58] + wire _T_1855 = byp_fetch_index_inc_1 == 4'h0; // @[el2_ifu_mem_ctl.scala 445:73] + wire [15:0] _T_1903 = _T_1855 ? ic_miss_buff_data_0[15:0] : 16'h0; // @[Mux.scala 27:72] + wire _T_1858 = byp_fetch_index_inc_1 == 4'h1; // @[el2_ifu_mem_ctl.scala 445:73] + wire [15:0] _T_1904 = _T_1858 ? ic_miss_buff_data_1[15:0] : 16'h0; // @[Mux.scala 27:72] + wire [15:0] _T_1919 = _T_1903 | _T_1904; // @[Mux.scala 27:72] + wire _T_1861 = byp_fetch_index_inc_1 == 4'h2; // @[el2_ifu_mem_ctl.scala 445:73] + wire [15:0] _T_1905 = _T_1861 ? ic_miss_buff_data_2[15:0] : 16'h0; // @[Mux.scala 27:72] + wire [15:0] _T_1920 = _T_1919 | _T_1905; // @[Mux.scala 27:72] + wire _T_1864 = byp_fetch_index_inc_1 == 4'h3; // @[el2_ifu_mem_ctl.scala 445:73] + wire [15:0] _T_1906 = _T_1864 ? ic_miss_buff_data_3[15:0] : 16'h0; // @[Mux.scala 27:72] + wire [15:0] _T_1921 = _T_1920 | _T_1906; // @[Mux.scala 27:72] + wire _T_1867 = byp_fetch_index_inc_1 == 4'h4; // @[el2_ifu_mem_ctl.scala 445:73] + wire [15:0] _T_1907 = _T_1867 ? ic_miss_buff_data_4[15:0] : 16'h0; // @[Mux.scala 27:72] + wire [15:0] _T_1922 = _T_1921 | _T_1907; // @[Mux.scala 27:72] + wire _T_1870 = byp_fetch_index_inc_1 == 4'h5; // @[el2_ifu_mem_ctl.scala 445:73] + wire [15:0] _T_1908 = _T_1870 ? ic_miss_buff_data_5[15:0] : 16'h0; // @[Mux.scala 27:72] + wire [15:0] _T_1923 = _T_1922 | _T_1908; // @[Mux.scala 27:72] + wire _T_1873 = byp_fetch_index_inc_1 == 4'h6; // @[el2_ifu_mem_ctl.scala 445:73] + wire [15:0] _T_1909 = _T_1873 ? ic_miss_buff_data_6[15:0] : 16'h0; // @[Mux.scala 27:72] + wire [15:0] _T_1924 = _T_1923 | _T_1909; // @[Mux.scala 27:72] + wire _T_1876 = byp_fetch_index_inc_1 == 4'h7; // @[el2_ifu_mem_ctl.scala 445:73] + wire [15:0] _T_1910 = _T_1876 ? ic_miss_buff_data_7[15:0] : 16'h0; // @[Mux.scala 27:72] + wire [15:0] _T_1925 = _T_1924 | _T_1910; // @[Mux.scala 27:72] + wire _T_1879 = byp_fetch_index_inc_1 == 4'h8; // @[el2_ifu_mem_ctl.scala 445:73] + wire [15:0] _T_1911 = _T_1879 ? ic_miss_buff_data_8[15:0] : 16'h0; // @[Mux.scala 27:72] + wire [15:0] _T_1926 = _T_1925 | _T_1911; // @[Mux.scala 27:72] + wire _T_1882 = byp_fetch_index_inc_1 == 4'h9; // @[el2_ifu_mem_ctl.scala 445:73] + wire [15:0] _T_1912 = _T_1882 ? ic_miss_buff_data_9[15:0] : 16'h0; // @[Mux.scala 27:72] + wire [15:0] _T_1927 = _T_1926 | _T_1912; // @[Mux.scala 27:72] + wire _T_1885 = byp_fetch_index_inc_1 == 4'ha; // @[el2_ifu_mem_ctl.scala 445:73] + wire [15:0] _T_1913 = _T_1885 ? ic_miss_buff_data_10[15:0] : 16'h0; // @[Mux.scala 27:72] + wire [15:0] _T_1928 = _T_1927 | _T_1913; // @[Mux.scala 27:72] + wire _T_1888 = byp_fetch_index_inc_1 == 4'hb; // @[el2_ifu_mem_ctl.scala 445:73] + wire [15:0] _T_1914 = _T_1888 ? ic_miss_buff_data_11[15:0] : 16'h0; // @[Mux.scala 27:72] + wire [15:0] _T_1929 = _T_1928 | _T_1914; // @[Mux.scala 27:72] + wire _T_1891 = byp_fetch_index_inc_1 == 4'hc; // @[el2_ifu_mem_ctl.scala 445:73] + wire [15:0] _T_1915 = _T_1891 ? ic_miss_buff_data_12[15:0] : 16'h0; // @[Mux.scala 27:72] + wire [15:0] _T_1930 = _T_1929 | _T_1915; // @[Mux.scala 27:72] + wire _T_1894 = byp_fetch_index_inc_1 == 4'hd; // @[el2_ifu_mem_ctl.scala 445:73] + wire [15:0] _T_1916 = _T_1894 ? ic_miss_buff_data_13[15:0] : 16'h0; // @[Mux.scala 27:72] + wire [15:0] _T_1931 = _T_1930 | _T_1916; // @[Mux.scala 27:72] + wire _T_1897 = byp_fetch_index_inc_1 == 4'he; // @[el2_ifu_mem_ctl.scala 445:73] + wire [15:0] _T_1917 = _T_1897 ? ic_miss_buff_data_14[15:0] : 16'h0; // @[Mux.scala 27:72] + wire [15:0] _T_1932 = _T_1931 | _T_1917; // @[Mux.scala 27:72] + wire _T_1900 = byp_fetch_index_inc_1 == 4'hf; // @[el2_ifu_mem_ctl.scala 445:73] + wire [15:0] _T_1918 = _T_1900 ? ic_miss_buff_data_15[15:0] : 16'h0; // @[Mux.scala 27:72] + wire [15:0] _T_1933 = _T_1932 | _T_1918; // @[Mux.scala 27:72] + wire [31:0] _T_1983 = _T_1613 ? ic_miss_buff_data_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1984 = _T_1616 ? ic_miss_buff_data_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1999 = _T_1983 | _T_1984; // @[Mux.scala 27:72] + wire [31:0] _T_1985 = _T_1619 ? ic_miss_buff_data_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2000 = _T_1999 | _T_1985; // @[Mux.scala 27:72] + wire [31:0] _T_1986 = _T_1622 ? ic_miss_buff_data_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2001 = _T_2000 | _T_1986; // @[Mux.scala 27:72] + wire [31:0] _T_1987 = _T_1625 ? ic_miss_buff_data_4 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2002 = _T_2001 | _T_1987; // @[Mux.scala 27:72] + wire [31:0] _T_1988 = _T_1628 ? ic_miss_buff_data_5 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2003 = _T_2002 | _T_1988; // @[Mux.scala 27:72] + wire [31:0] _T_1989 = _T_1631 ? ic_miss_buff_data_6 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2004 = _T_2003 | _T_1989; // @[Mux.scala 27:72] + wire [31:0] _T_1990 = _T_1634 ? ic_miss_buff_data_7 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2005 = _T_2004 | _T_1990; // @[Mux.scala 27:72] + wire [31:0] _T_1991 = _T_1637 ? ic_miss_buff_data_8 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2006 = _T_2005 | _T_1991; // @[Mux.scala 27:72] + wire [31:0] _T_1992 = _T_1640 ? ic_miss_buff_data_9 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2007 = _T_2006 | _T_1992; // @[Mux.scala 27:72] + wire [31:0] _T_1993 = _T_1643 ? ic_miss_buff_data_10 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2008 = _T_2007 | _T_1993; // @[Mux.scala 27:72] + wire [31:0] _T_1994 = _T_1646 ? ic_miss_buff_data_11 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2009 = _T_2008 | _T_1994; // @[Mux.scala 27:72] + wire [31:0] _T_1995 = _T_1649 ? ic_miss_buff_data_12 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2010 = _T_2009 | _T_1995; // @[Mux.scala 27:72] + wire [31:0] _T_1996 = _T_1652 ? ic_miss_buff_data_13 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2011 = _T_2010 | _T_1996; // @[Mux.scala 27:72] + wire [31:0] _T_1997 = _T_1655 ? ic_miss_buff_data_14 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2012 = _T_2011 | _T_1997; // @[Mux.scala 27:72] + wire [31:0] _T_1998 = _T_1658 ? ic_miss_buff_data_15 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2013 = _T_2012 | _T_1998; // @[Mux.scala 27:72] + wire [79:0] _T_2096 = {_T_1933,_T_2013,_T_1771}; // @[Cat.scala 29:58] + wire [79:0] ic_byp_data_only_pre_new = _T_1612 ? _T_1854 : _T_2096; // @[el2_ifu_mem_ctl.scala 443:37] + wire [79:0] _T_2101 = {16'h0,ic_byp_data_only_pre_new[79:16]}; // @[Cat.scala 29:58] + wire [79:0] ic_byp_data_only_new = _T_2099 ? ic_byp_data_only_pre_new : _T_2101; // @[el2_ifu_mem_ctl.scala 447:30] + wire [79:0] _GEN_447 = {{16'd0}, _T_1263}; // @[el2_ifu_mem_ctl.scala 378:114] + wire [79:0] _T_1264 = _GEN_447 & ic_byp_data_only_new; // @[el2_ifu_mem_ctl.scala 378:114] + wire [79:0] _GEN_448 = {{16'd0}, _T_1261}; // @[el2_ifu_mem_ctl.scala 378:88] + wire [79:0] ic_premux_data_temp = _GEN_448 | _T_1264; // @[el2_ifu_mem_ctl.scala 378:88] + wire fetch_req_f_qual = io_ic_hit_f & _T_319; // @[el2_ifu_mem_ctl.scala 385:38] + reg ifc_region_acc_fault_memory_f; // @[el2_ifu_mem_ctl.scala 851:66] + wire [1:0] _T_1272 = ifc_region_acc_fault_memory_f ? 2'h3 : 2'h0; // @[el2_ifu_mem_ctl.scala 390:10] + wire [1:0] _T_1273 = ifc_region_acc_fault_f ? 2'h2 : _T_1272; // @[el2_ifu_mem_ctl.scala 389:8] + wire _T_1275 = fetch_req_f_qual & io_ifu_bp_inst_mask_f; // @[el2_ifu_mem_ctl.scala 391:45] + wire _T_1277 = byp_fetch_index == 5'h1f; // @[el2_ifu_mem_ctl.scala 391:80] + wire _T_1278 = ~_T_1277; // @[el2_ifu_mem_ctl.scala 391:71] + wire _T_1279 = _T_1275 & _T_1278; // @[el2_ifu_mem_ctl.scala 391:69] + wire _T_1280 = err_stop_state != 2'h2; // @[el2_ifu_mem_ctl.scala 391:131] + wire _T_1281 = _T_1279 & _T_1280; // @[el2_ifu_mem_ctl.scala 391:114] + wire [6:0] _T_1353 = {ic_miss_buff_data_valid_in_7,ic_miss_buff_data_valid_in_6,ic_miss_buff_data_valid_in_5,ic_miss_buff_data_valid_in_4,ic_miss_buff_data_valid_in_3,ic_miss_buff_data_valid_in_2,ic_miss_buff_data_valid_in_1}; // @[Cat.scala 29:58] + wire _T_1359 = ic_miss_buff_data_error[0] & _T_1325; // @[el2_ifu_mem_ctl.scala 410:32] + wire _T_2641 = |io_ifu_axi_rresp; // @[el2_ifu_mem_ctl.scala 625:47] + wire _T_2642 = _T_2641 & _T_13; // @[el2_ifu_mem_ctl.scala 625:50] + wire bus_ifu_wr_data_error = _T_2642 & miss_pending; // @[el2_ifu_mem_ctl.scala 625:68] + wire ic_miss_buff_data_error_in_0 = write_fill_data_0 ? bus_ifu_wr_data_error : _T_1359; // @[el2_ifu_mem_ctl.scala 409:72] + wire _T_1363 = ic_miss_buff_data_error[1] & _T_1325; // @[el2_ifu_mem_ctl.scala 410:32] + wire ic_miss_buff_data_error_in_1 = write_fill_data_1 ? bus_ifu_wr_data_error : _T_1363; // @[el2_ifu_mem_ctl.scala 409:72] + wire _T_1367 = ic_miss_buff_data_error[2] & _T_1325; // @[el2_ifu_mem_ctl.scala 410:32] + wire ic_miss_buff_data_error_in_2 = write_fill_data_2 ? bus_ifu_wr_data_error : _T_1367; // @[el2_ifu_mem_ctl.scala 409:72] + wire _T_1371 = ic_miss_buff_data_error[3] & _T_1325; // @[el2_ifu_mem_ctl.scala 410:32] + wire ic_miss_buff_data_error_in_3 = write_fill_data_3 ? bus_ifu_wr_data_error : _T_1371; // @[el2_ifu_mem_ctl.scala 409:72] + wire _T_1375 = ic_miss_buff_data_error[4] & _T_1325; // @[el2_ifu_mem_ctl.scala 410:32] + wire ic_miss_buff_data_error_in_4 = write_fill_data_4 ? bus_ifu_wr_data_error : _T_1375; // @[el2_ifu_mem_ctl.scala 409:72] + wire _T_1379 = ic_miss_buff_data_error[5] & _T_1325; // @[el2_ifu_mem_ctl.scala 410:32] + wire ic_miss_buff_data_error_in_5 = write_fill_data_5 ? bus_ifu_wr_data_error : _T_1379; // @[el2_ifu_mem_ctl.scala 409:72] + wire _T_1383 = ic_miss_buff_data_error[6] & _T_1325; // @[el2_ifu_mem_ctl.scala 410:32] + wire ic_miss_buff_data_error_in_6 = write_fill_data_6 ? bus_ifu_wr_data_error : _T_1383; // @[el2_ifu_mem_ctl.scala 409:72] + wire _T_1387 = ic_miss_buff_data_error[7] & _T_1325; // @[el2_ifu_mem_ctl.scala 410:32] + wire ic_miss_buff_data_error_in_7 = write_fill_data_7 ? bus_ifu_wr_data_error : _T_1387; // @[el2_ifu_mem_ctl.scala 409:72] + wire [6:0] _T_1393 = {ic_miss_buff_data_error_in_7,ic_miss_buff_data_error_in_6,ic_miss_buff_data_error_in_5,ic_miss_buff_data_error_in_4,ic_miss_buff_data_error_in_3,ic_miss_buff_data_error_in_2,ic_miss_buff_data_error_in_1}; // @[Cat.scala 29:58] + reg [6:0] perr_ic_index_ff; // @[Reg.scala 27:20] + wire _T_2451 = 3'h0 == perr_state; // @[Conditional.scala 37:30] + wire _T_2459 = _T_6 & _T_319; // @[el2_ifu_mem_ctl.scala 492:65] + wire _T_2460 = _T_2459 | io_iccm_dma_sb_error; // @[el2_ifu_mem_ctl.scala 492:88] + wire _T_2462 = _T_2460 & _T_2574; // @[el2_ifu_mem_ctl.scala 492:112] + wire _T_2463 = 3'h1 == perr_state; // @[Conditional.scala 37:30] + wire _T_2464 = io_dec_tlu_flush_lower_wb | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 497:50] + wire _T_2466 = 3'h2 == perr_state; // @[Conditional.scala 37:30] + wire _T_2473 = 3'h4 == perr_state; // @[Conditional.scala 37:30] + wire _T_2475 = 3'h3 == perr_state; // @[Conditional.scala 37:30] + wire _GEN_22 = _T_2473 | _T_2475; // @[Conditional.scala 39:67] + wire _GEN_24 = _T_2466 ? _T_2464 : _GEN_22; // @[Conditional.scala 39:67] + wire _GEN_26 = _T_2463 ? _T_2464 : _GEN_24; // @[Conditional.scala 39:67] + wire perr_state_en = _T_2451 ? _T_2462 : _GEN_26; // @[Conditional.scala 40:58] + wire perr_sb_write_status = _T_2451 & perr_state_en; // @[Conditional.scala 40:58] + wire _T_2465 = io_dec_tlu_flush_lower_wb & io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 498:56] + wire _GEN_27 = _T_2463 & _T_2465; // @[Conditional.scala 39:67] + wire perr_sel_invalidate = _T_2451 ? 1'h0 : _GEN_27; // @[Conditional.scala 40:58] + wire [1:0] perr_err_inv_way = perr_sel_invalidate ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + reg dma_sb_err_state_ff; // @[el2_ifu_mem_ctl.scala 483:58] + wire _T_2448 = ~dma_sb_err_state_ff; // @[el2_ifu_mem_ctl.scala 482:49] + wire _T_2453 = io_ic_error_start & _T_319; // @[el2_ifu_mem_ctl.scala 491:87] + wire _T_2467 = ~io_dec_tlu_flush_err_wb; // @[el2_ifu_mem_ctl.scala 501:30] + wire _T_2468 = _T_2467 & io_dec_tlu_flush_lower_wb; // @[el2_ifu_mem_ctl.scala 501:55] + wire _T_2469 = _T_2468 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 501:85] + wire _T_2478 = perr_state == 3'h2; // @[el2_ifu_mem_ctl.scala 522:66] + wire _T_2479 = io_dec_tlu_flush_err_wb & _T_2478; // @[el2_ifu_mem_ctl.scala 522:52] + wire _T_2481 = _T_2479 & _T_2574; // @[el2_ifu_mem_ctl.scala 522:81] + wire _T_2483 = io_dec_tlu_flush_lower_wb | io_dec_tlu_i0_commit_cmt; // @[el2_ifu_mem_ctl.scala 525:59] + wire _T_2484 = _T_2483 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 525:86] + wire _T_2498 = _T_2483 | io_ifu_fetch_val[0]; // @[el2_ifu_mem_ctl.scala 528:81] + wire _T_2499 = _T_2498 | ifu_bp_hit_taken_q_f; // @[el2_ifu_mem_ctl.scala 528:103] + wire _T_2500 = _T_2499 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 528:126] + wire _T_2520 = _T_2498 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 535:103] + wire _T_2528 = io_dec_tlu_flush_lower_wb & _T_2467; // @[el2_ifu_mem_ctl.scala 540:60] + wire _T_2529 = _T_2528 | io_dec_tlu_i0_commit_cmt; // @[el2_ifu_mem_ctl.scala 540:88] + wire _T_2530 = _T_2529 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 540:115] + wire _GEN_34 = _T_2526 & _T_2484; // @[Conditional.scala 39:67] + wire _GEN_37 = _T_2509 ? _T_2520 : _GEN_34; // @[Conditional.scala 39:67] + wire _GEN_39 = _T_2509 | _T_2526; // @[Conditional.scala 39:67] + wire _GEN_41 = _T_2482 ? _T_2500 : _GEN_37; // @[Conditional.scala 39:67] + wire _GEN_43 = _T_2482 | _GEN_39; // @[Conditional.scala 39:67] + wire err_stop_state_en = _T_2477 ? _T_2481 : _GEN_41; // @[Conditional.scala 40:58] + reg bus_cmd_req_hold; // @[el2_ifu_mem_ctl.scala 563:53] + wire _T_2542 = ic_act_miss_f | bus_cmd_req_hold; // @[el2_ifu_mem_ctl.scala 559:45] + reg ifu_bus_cmd_valid; // @[el2_ifu_mem_ctl.scala 560:55] + wire _T_2543 = _T_2542 | ifu_bus_cmd_valid; // @[el2_ifu_mem_ctl.scala 559:64] + wire _T_2545 = _T_2543 & _T_2574; // @[el2_ifu_mem_ctl.scala 559:85] + reg [2:0] bus_cmd_beat_count; // @[Reg.scala 27:20] + wire _T_2547 = bus_cmd_beat_count == 3'h7; // @[el2_ifu_mem_ctl.scala 559:133] + wire _T_2548 = _T_2547 & ifu_bus_cmd_valid; // @[el2_ifu_mem_ctl.scala 559:164] + wire _T_2549 = _T_2548 & io_ifu_axi_arready; // @[el2_ifu_mem_ctl.scala 559:184] + wire _T_2550 = _T_2549 & miss_pending; // @[el2_ifu_mem_ctl.scala 559:204] + wire _T_2551 = ~_T_2550; // @[el2_ifu_mem_ctl.scala 559:112] + wire ifu_bus_arready = io_ifu_axi_arready & io_ifu_bus_clk_en; // @[el2_ifu_mem_ctl.scala 591:45] + wire _T_2568 = io_ifu_axi_arvalid & ifu_bus_arready; // @[el2_ifu_mem_ctl.scala 594:35] + wire _T_2569 = _T_2568 & miss_pending; // @[el2_ifu_mem_ctl.scala 594:53] + wire bus_cmd_sent = _T_2569 & _T_2574; // @[el2_ifu_mem_ctl.scala 594:68] + wire _T_2554 = ~bus_cmd_sent; // @[el2_ifu_mem_ctl.scala 562:61] + wire _T_2555 = _T_2542 & _T_2554; // @[el2_ifu_mem_ctl.scala 562:59] + wire [2:0] _T_2559 = ifu_bus_cmd_valid ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_2561 = {miss_addr,bus_rd_addr_count,3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2563 = ifu_bus_cmd_valid ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + reg ifu_bus_arready_unq_ff; // @[el2_ifu_mem_ctl.scala 578:57] + reg ifu_bus_arvalid_ff; // @[el2_ifu_mem_ctl.scala 580:53] + wire ifu_bus_arready_ff = ifu_bus_arready_unq_ff & bus_ifu_bus_clk_en_ff; // @[el2_ifu_mem_ctl.scala 592:51] + wire _T_2589 = ~scnd_miss_req; // @[el2_ifu_mem_ctl.scala 602:73] + wire _T_2590 = _T_2575 & _T_2589; // @[el2_ifu_mem_ctl.scala 602:71] + wire _T_2592 = last_data_recieved_ff & _T_1325; // @[el2_ifu_mem_ctl.scala 602:114] + wire [2:0] _T_2598 = bus_rd_addr_count + 3'h1; // @[el2_ifu_mem_ctl.scala 607:43] + wire _T_2602 = ifu_bus_cmd_valid & io_ifu_axi_arready; // @[el2_ifu_mem_ctl.scala 610:48] + wire _T_2603 = _T_2602 & miss_pending; // @[el2_ifu_mem_ctl.scala 610:68] + wire bus_inc_cmd_beat_cnt = _T_2603 & _T_2574; // @[el2_ifu_mem_ctl.scala 610:83] + wire bus_reset_cmd_beat_cnt_secondlast = ic_act_miss_f & uncacheable_miss_in; // @[el2_ifu_mem_ctl.scala 612:57] + wire _T_2607 = ~bus_inc_cmd_beat_cnt; // @[el2_ifu_mem_ctl.scala 613:31] + wire _T_2608 = ic_act_miss_f | scnd_miss_req; // @[el2_ifu_mem_ctl.scala 613:71] + wire _T_2609 = _T_2608 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 613:87] + wire _T_2610 = ~_T_2609; // @[el2_ifu_mem_ctl.scala 613:55] + wire bus_hold_cmd_beat_cnt = _T_2607 & _T_2610; // @[el2_ifu_mem_ctl.scala 613:53] + wire _T_2611 = bus_inc_cmd_beat_cnt | ic_act_miss_f; // @[el2_ifu_mem_ctl.scala 614:46] + wire bus_cmd_beat_en = _T_2611 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 614:62] + wire [2:0] _T_2614 = bus_cmd_beat_count + 3'h1; // @[el2_ifu_mem_ctl.scala 616:46] + wire [2:0] _T_2616 = bus_reset_cmd_beat_cnt_secondlast ? 3'h6 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_2617 = bus_inc_cmd_beat_cnt ? _T_2614 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_2618 = bus_hold_cmd_beat_cnt ? bus_cmd_beat_count : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_2620 = _T_2616 | _T_2617; // @[Mux.scala 27:72] + wire [2:0] bus_new_cmd_beat_count = _T_2620 | _T_2618; // @[Mux.scala 27:72] + reg ifc_dma_access_ok_prev; // @[el2_ifu_mem_ctl.scala 628:62] + wire _T_2649 = ~iccm_correct_ecc; // @[el2_ifu_mem_ctl.scala 633:50] + wire _T_2650 = io_ifc_dma_access_ok & _T_2649; // @[el2_ifu_mem_ctl.scala 633:47] + wire _T_2651 = ~io_iccm_dma_sb_error; // @[el2_ifu_mem_ctl.scala 633:70] + wire _T_2655 = _T_2650 & ifc_dma_access_ok_prev; // @[el2_ifu_mem_ctl.scala 634:72] + wire _T_2656 = perr_state == 3'h0; // @[el2_ifu_mem_ctl.scala 634:111] + wire _T_2657 = _T_2655 & _T_2656; // @[el2_ifu_mem_ctl.scala 634:97] + wire ifc_dma_access_q_ok = _T_2657 & _T_2651; // @[el2_ifu_mem_ctl.scala 634:127] + wire _T_2660 = ifc_dma_access_q_ok & io_dma_iccm_req; // @[el2_ifu_mem_ctl.scala 637:40] + wire _T_2661 = _T_2660 & io_dma_mem_write; // @[el2_ifu_mem_ctl.scala 637:58] + wire _T_2664 = ~io_dma_mem_write; // @[el2_ifu_mem_ctl.scala 638:60] + wire _T_2665 = _T_2660 & _T_2664; // @[el2_ifu_mem_ctl.scala 638:58] + wire _T_2666 = io_ifc_iccm_access_bf & io_ifc_fetch_req_bf; // @[el2_ifu_mem_ctl.scala 638:104] + wire [2:0] _T_2671 = io_dma_iccm_req ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire _T_2692 = io_dma_mem_wdata[32] ^ io_dma_mem_wdata[33]; // @[el2_lib.scala 259:74] + wire _T_2693 = _T_2692 ^ io_dma_mem_wdata[35]; // @[el2_lib.scala 259:74] + wire _T_2694 = _T_2693 ^ io_dma_mem_wdata[36]; // @[el2_lib.scala 259:74] + wire _T_2695 = _T_2694 ^ io_dma_mem_wdata[38]; // @[el2_lib.scala 259:74] + wire _T_2696 = _T_2695 ^ io_dma_mem_wdata[40]; // @[el2_lib.scala 259:74] + wire _T_2697 = _T_2696 ^ io_dma_mem_wdata[42]; // @[el2_lib.scala 259:74] + wire _T_2698 = _T_2697 ^ io_dma_mem_wdata[43]; // @[el2_lib.scala 259:74] + wire _T_2699 = _T_2698 ^ io_dma_mem_wdata[45]; // @[el2_lib.scala 259:74] + wire _T_2700 = _T_2699 ^ io_dma_mem_wdata[47]; // @[el2_lib.scala 259:74] + wire _T_2701 = _T_2700 ^ io_dma_mem_wdata[49]; // @[el2_lib.scala 259:74] + wire _T_2702 = _T_2701 ^ io_dma_mem_wdata[51]; // @[el2_lib.scala 259:74] + wire _T_2703 = _T_2702 ^ io_dma_mem_wdata[53]; // @[el2_lib.scala 259:74] + wire _T_2704 = _T_2703 ^ io_dma_mem_wdata[55]; // @[el2_lib.scala 259:74] + wire _T_2705 = _T_2704 ^ io_dma_mem_wdata[57]; // @[el2_lib.scala 259:74] + wire _T_2706 = _T_2705 ^ io_dma_mem_wdata[58]; // @[el2_lib.scala 259:74] + wire _T_2707 = _T_2706 ^ io_dma_mem_wdata[60]; // @[el2_lib.scala 259:74] + wire _T_2708 = _T_2707 ^ io_dma_mem_wdata[62]; // @[el2_lib.scala 259:74] + wire _T_2727 = io_dma_mem_wdata[32] ^ io_dma_mem_wdata[34]; // @[el2_lib.scala 259:74] + wire _T_2728 = _T_2727 ^ io_dma_mem_wdata[35]; // @[el2_lib.scala 259:74] + wire _T_2729 = _T_2728 ^ io_dma_mem_wdata[37]; // @[el2_lib.scala 259:74] + wire _T_2730 = _T_2729 ^ io_dma_mem_wdata[38]; // @[el2_lib.scala 259:74] + wire _T_2731 = _T_2730 ^ io_dma_mem_wdata[41]; // @[el2_lib.scala 259:74] + wire _T_2732 = _T_2731 ^ io_dma_mem_wdata[42]; // @[el2_lib.scala 259:74] + wire _T_2733 = _T_2732 ^ io_dma_mem_wdata[44]; // @[el2_lib.scala 259:74] + wire _T_2734 = _T_2733 ^ io_dma_mem_wdata[45]; // @[el2_lib.scala 259:74] + wire _T_2735 = _T_2734 ^ io_dma_mem_wdata[48]; // @[el2_lib.scala 259:74] + wire _T_2736 = _T_2735 ^ io_dma_mem_wdata[49]; // @[el2_lib.scala 259:74] + wire _T_2737 = _T_2736 ^ io_dma_mem_wdata[52]; // @[el2_lib.scala 259:74] + wire _T_2738 = _T_2737 ^ io_dma_mem_wdata[53]; // @[el2_lib.scala 259:74] + wire _T_2739 = _T_2738 ^ io_dma_mem_wdata[56]; // @[el2_lib.scala 259:74] + wire _T_2740 = _T_2739 ^ io_dma_mem_wdata[57]; // @[el2_lib.scala 259:74] + wire _T_2741 = _T_2740 ^ io_dma_mem_wdata[59]; // @[el2_lib.scala 259:74] + wire _T_2742 = _T_2741 ^ io_dma_mem_wdata[60]; // @[el2_lib.scala 259:74] + wire _T_2743 = _T_2742 ^ io_dma_mem_wdata[63]; // @[el2_lib.scala 259:74] + wire _T_2762 = io_dma_mem_wdata[33] ^ io_dma_mem_wdata[34]; // @[el2_lib.scala 259:74] + wire _T_2763 = _T_2762 ^ io_dma_mem_wdata[35]; // @[el2_lib.scala 259:74] + wire _T_2764 = _T_2763 ^ io_dma_mem_wdata[39]; // @[el2_lib.scala 259:74] + wire _T_2765 = _T_2764 ^ io_dma_mem_wdata[40]; // @[el2_lib.scala 259:74] + wire _T_2766 = _T_2765 ^ io_dma_mem_wdata[41]; // @[el2_lib.scala 259:74] + wire _T_2767 = _T_2766 ^ io_dma_mem_wdata[42]; // @[el2_lib.scala 259:74] + wire _T_2768 = _T_2767 ^ io_dma_mem_wdata[46]; // @[el2_lib.scala 259:74] + wire _T_2769 = _T_2768 ^ io_dma_mem_wdata[47]; // @[el2_lib.scala 259:74] + wire _T_2770 = _T_2769 ^ io_dma_mem_wdata[48]; // @[el2_lib.scala 259:74] + wire _T_2771 = _T_2770 ^ io_dma_mem_wdata[49]; // @[el2_lib.scala 259:74] + wire _T_2772 = _T_2771 ^ io_dma_mem_wdata[54]; // @[el2_lib.scala 259:74] + wire _T_2773 = _T_2772 ^ io_dma_mem_wdata[55]; // @[el2_lib.scala 259:74] + wire _T_2774 = _T_2773 ^ io_dma_mem_wdata[56]; // @[el2_lib.scala 259:74] + wire _T_2775 = _T_2774 ^ io_dma_mem_wdata[57]; // @[el2_lib.scala 259:74] + wire _T_2776 = _T_2775 ^ io_dma_mem_wdata[61]; // @[el2_lib.scala 259:74] + wire _T_2777 = _T_2776 ^ io_dma_mem_wdata[62]; // @[el2_lib.scala 259:74] + wire _T_2778 = _T_2777 ^ io_dma_mem_wdata[63]; // @[el2_lib.scala 259:74] + wire _T_2794 = io_dma_mem_wdata[36] ^ io_dma_mem_wdata[37]; // @[el2_lib.scala 259:74] + wire _T_2795 = _T_2794 ^ io_dma_mem_wdata[38]; // @[el2_lib.scala 259:74] + wire _T_2796 = _T_2795 ^ io_dma_mem_wdata[39]; // @[el2_lib.scala 259:74] + wire _T_2797 = _T_2796 ^ io_dma_mem_wdata[40]; // @[el2_lib.scala 259:74] + wire _T_2798 = _T_2797 ^ io_dma_mem_wdata[41]; // @[el2_lib.scala 259:74] + wire _T_2799 = _T_2798 ^ io_dma_mem_wdata[42]; // @[el2_lib.scala 259:74] + wire _T_2800 = _T_2799 ^ io_dma_mem_wdata[50]; // @[el2_lib.scala 259:74] + wire _T_2801 = _T_2800 ^ io_dma_mem_wdata[51]; // @[el2_lib.scala 259:74] + wire _T_2802 = _T_2801 ^ io_dma_mem_wdata[52]; // @[el2_lib.scala 259:74] + wire _T_2803 = _T_2802 ^ io_dma_mem_wdata[53]; // @[el2_lib.scala 259:74] + wire _T_2804 = _T_2803 ^ io_dma_mem_wdata[54]; // @[el2_lib.scala 259:74] + wire _T_2805 = _T_2804 ^ io_dma_mem_wdata[55]; // @[el2_lib.scala 259:74] + wire _T_2806 = _T_2805 ^ io_dma_mem_wdata[56]; // @[el2_lib.scala 259:74] + wire _T_2807 = _T_2806 ^ io_dma_mem_wdata[57]; // @[el2_lib.scala 259:74] + wire _T_2823 = io_dma_mem_wdata[43] ^ io_dma_mem_wdata[44]; // @[el2_lib.scala 259:74] + wire _T_2824 = _T_2823 ^ io_dma_mem_wdata[45]; // @[el2_lib.scala 259:74] + wire _T_2825 = _T_2824 ^ io_dma_mem_wdata[46]; // @[el2_lib.scala 259:74] + wire _T_2826 = _T_2825 ^ io_dma_mem_wdata[47]; // @[el2_lib.scala 259:74] + wire _T_2827 = _T_2826 ^ io_dma_mem_wdata[48]; // @[el2_lib.scala 259:74] + wire _T_2828 = _T_2827 ^ io_dma_mem_wdata[49]; // @[el2_lib.scala 259:74] + wire _T_2829 = _T_2828 ^ io_dma_mem_wdata[50]; // @[el2_lib.scala 259:74] + wire _T_2830 = _T_2829 ^ io_dma_mem_wdata[51]; // @[el2_lib.scala 259:74] + wire _T_2831 = _T_2830 ^ io_dma_mem_wdata[52]; // @[el2_lib.scala 259:74] + wire _T_2832 = _T_2831 ^ io_dma_mem_wdata[53]; // @[el2_lib.scala 259:74] + wire _T_2833 = _T_2832 ^ io_dma_mem_wdata[54]; // @[el2_lib.scala 259:74] + wire _T_2834 = _T_2833 ^ io_dma_mem_wdata[55]; // @[el2_lib.scala 259:74] + wire _T_2835 = _T_2834 ^ io_dma_mem_wdata[56]; // @[el2_lib.scala 259:74] + wire _T_2836 = _T_2835 ^ io_dma_mem_wdata[57]; // @[el2_lib.scala 259:74] + wire _T_2843 = io_dma_mem_wdata[58] ^ io_dma_mem_wdata[59]; // @[el2_lib.scala 259:74] + wire _T_2844 = _T_2843 ^ io_dma_mem_wdata[60]; // @[el2_lib.scala 259:74] + wire _T_2845 = _T_2844 ^ io_dma_mem_wdata[61]; // @[el2_lib.scala 259:74] + wire _T_2846 = _T_2845 ^ io_dma_mem_wdata[62]; // @[el2_lib.scala 259:74] + wire _T_2847 = _T_2846 ^ io_dma_mem_wdata[63]; // @[el2_lib.scala 259:74] + wire [5:0] _T_2852 = {_T_2847,_T_2836,_T_2807,_T_2778,_T_2743,_T_2708}; // @[Cat.scala 29:58] + wire _T_2853 = ^io_dma_mem_wdata[63:32]; // @[el2_lib.scala 267:13] + wire _T_2854 = ^_T_2852; // @[el2_lib.scala 267:23] + wire _T_2855 = _T_2853 ^ _T_2854; // @[el2_lib.scala 267:18] + wire _T_2876 = io_dma_mem_wdata[0] ^ io_dma_mem_wdata[1]; // @[el2_lib.scala 259:74] + wire _T_2877 = _T_2876 ^ io_dma_mem_wdata[3]; // @[el2_lib.scala 259:74] + wire _T_2878 = _T_2877 ^ io_dma_mem_wdata[4]; // @[el2_lib.scala 259:74] + wire _T_2879 = _T_2878 ^ io_dma_mem_wdata[6]; // @[el2_lib.scala 259:74] + wire _T_2880 = _T_2879 ^ io_dma_mem_wdata[8]; // @[el2_lib.scala 259:74] + wire _T_2881 = _T_2880 ^ io_dma_mem_wdata[10]; // @[el2_lib.scala 259:74] + wire _T_2882 = _T_2881 ^ io_dma_mem_wdata[11]; // @[el2_lib.scala 259:74] + wire _T_2883 = _T_2882 ^ io_dma_mem_wdata[13]; // @[el2_lib.scala 259:74] + wire _T_2884 = _T_2883 ^ io_dma_mem_wdata[15]; // @[el2_lib.scala 259:74] + wire _T_2885 = _T_2884 ^ io_dma_mem_wdata[17]; // @[el2_lib.scala 259:74] + wire _T_2886 = _T_2885 ^ io_dma_mem_wdata[19]; // @[el2_lib.scala 259:74] + wire _T_2887 = _T_2886 ^ io_dma_mem_wdata[21]; // @[el2_lib.scala 259:74] + wire _T_2888 = _T_2887 ^ io_dma_mem_wdata[23]; // @[el2_lib.scala 259:74] + wire _T_2889 = _T_2888 ^ io_dma_mem_wdata[25]; // @[el2_lib.scala 259:74] + wire _T_2890 = _T_2889 ^ io_dma_mem_wdata[26]; // @[el2_lib.scala 259:74] + wire _T_2891 = _T_2890 ^ io_dma_mem_wdata[28]; // @[el2_lib.scala 259:74] + wire _T_2892 = _T_2891 ^ io_dma_mem_wdata[30]; // @[el2_lib.scala 259:74] + wire _T_2911 = io_dma_mem_wdata[0] ^ io_dma_mem_wdata[2]; // @[el2_lib.scala 259:74] + wire _T_2912 = _T_2911 ^ io_dma_mem_wdata[3]; // @[el2_lib.scala 259:74] + wire _T_2913 = _T_2912 ^ io_dma_mem_wdata[5]; // @[el2_lib.scala 259:74] + wire _T_2914 = _T_2913 ^ io_dma_mem_wdata[6]; // @[el2_lib.scala 259:74] + wire _T_2915 = _T_2914 ^ io_dma_mem_wdata[9]; // @[el2_lib.scala 259:74] + wire _T_2916 = _T_2915 ^ io_dma_mem_wdata[10]; // @[el2_lib.scala 259:74] + wire _T_2917 = _T_2916 ^ io_dma_mem_wdata[12]; // @[el2_lib.scala 259:74] + wire _T_2918 = _T_2917 ^ io_dma_mem_wdata[13]; // @[el2_lib.scala 259:74] + wire _T_2919 = _T_2918 ^ io_dma_mem_wdata[16]; // @[el2_lib.scala 259:74] + wire _T_2920 = _T_2919 ^ io_dma_mem_wdata[17]; // @[el2_lib.scala 259:74] + wire _T_2921 = _T_2920 ^ io_dma_mem_wdata[20]; // @[el2_lib.scala 259:74] + wire _T_2922 = _T_2921 ^ io_dma_mem_wdata[21]; // @[el2_lib.scala 259:74] + wire _T_2923 = _T_2922 ^ io_dma_mem_wdata[24]; // @[el2_lib.scala 259:74] + wire _T_2924 = _T_2923 ^ io_dma_mem_wdata[25]; // @[el2_lib.scala 259:74] + wire _T_2925 = _T_2924 ^ io_dma_mem_wdata[27]; // @[el2_lib.scala 259:74] + wire _T_2926 = _T_2925 ^ io_dma_mem_wdata[28]; // @[el2_lib.scala 259:74] + wire _T_2927 = _T_2926 ^ io_dma_mem_wdata[31]; // @[el2_lib.scala 259:74] + wire _T_2946 = io_dma_mem_wdata[1] ^ io_dma_mem_wdata[2]; // @[el2_lib.scala 259:74] + wire _T_2947 = _T_2946 ^ io_dma_mem_wdata[3]; // @[el2_lib.scala 259:74] + wire _T_2948 = _T_2947 ^ io_dma_mem_wdata[7]; // @[el2_lib.scala 259:74] + wire _T_2949 = _T_2948 ^ io_dma_mem_wdata[8]; // @[el2_lib.scala 259:74] + wire _T_2950 = _T_2949 ^ io_dma_mem_wdata[9]; // @[el2_lib.scala 259:74] + wire _T_2951 = _T_2950 ^ io_dma_mem_wdata[10]; // @[el2_lib.scala 259:74] + wire _T_2952 = _T_2951 ^ io_dma_mem_wdata[14]; // @[el2_lib.scala 259:74] + wire _T_2953 = _T_2952 ^ io_dma_mem_wdata[15]; // @[el2_lib.scala 259:74] + wire _T_2954 = _T_2953 ^ io_dma_mem_wdata[16]; // @[el2_lib.scala 259:74] + wire _T_2955 = _T_2954 ^ io_dma_mem_wdata[17]; // @[el2_lib.scala 259:74] + wire _T_2956 = _T_2955 ^ io_dma_mem_wdata[22]; // @[el2_lib.scala 259:74] + wire _T_2957 = _T_2956 ^ io_dma_mem_wdata[23]; // @[el2_lib.scala 259:74] + wire _T_2958 = _T_2957 ^ io_dma_mem_wdata[24]; // @[el2_lib.scala 259:74] + wire _T_2959 = _T_2958 ^ io_dma_mem_wdata[25]; // @[el2_lib.scala 259:74] + wire _T_2960 = _T_2959 ^ io_dma_mem_wdata[29]; // @[el2_lib.scala 259:74] + wire _T_2961 = _T_2960 ^ io_dma_mem_wdata[30]; // @[el2_lib.scala 259:74] + wire _T_2962 = _T_2961 ^ io_dma_mem_wdata[31]; // @[el2_lib.scala 259:74] + wire _T_2978 = io_dma_mem_wdata[4] ^ io_dma_mem_wdata[5]; // @[el2_lib.scala 259:74] + wire _T_2979 = _T_2978 ^ io_dma_mem_wdata[6]; // @[el2_lib.scala 259:74] + wire _T_2980 = _T_2979 ^ io_dma_mem_wdata[7]; // @[el2_lib.scala 259:74] + wire _T_2981 = _T_2980 ^ io_dma_mem_wdata[8]; // @[el2_lib.scala 259:74] + wire _T_2982 = _T_2981 ^ io_dma_mem_wdata[9]; // @[el2_lib.scala 259:74] + wire _T_2983 = _T_2982 ^ io_dma_mem_wdata[10]; // @[el2_lib.scala 259:74] + wire _T_2984 = _T_2983 ^ io_dma_mem_wdata[18]; // @[el2_lib.scala 259:74] + wire _T_2985 = _T_2984 ^ io_dma_mem_wdata[19]; // @[el2_lib.scala 259:74] + wire _T_2986 = _T_2985 ^ io_dma_mem_wdata[20]; // @[el2_lib.scala 259:74] + wire _T_2987 = _T_2986 ^ io_dma_mem_wdata[21]; // @[el2_lib.scala 259:74] + wire _T_2988 = _T_2987 ^ io_dma_mem_wdata[22]; // @[el2_lib.scala 259:74] + wire _T_2989 = _T_2988 ^ io_dma_mem_wdata[23]; // @[el2_lib.scala 259:74] + wire _T_2990 = _T_2989 ^ io_dma_mem_wdata[24]; // @[el2_lib.scala 259:74] + wire _T_2991 = _T_2990 ^ io_dma_mem_wdata[25]; // @[el2_lib.scala 259:74] + wire _T_3007 = io_dma_mem_wdata[11] ^ io_dma_mem_wdata[12]; // @[el2_lib.scala 259:74] + wire _T_3008 = _T_3007 ^ io_dma_mem_wdata[13]; // @[el2_lib.scala 259:74] + wire _T_3009 = _T_3008 ^ io_dma_mem_wdata[14]; // @[el2_lib.scala 259:74] + wire _T_3010 = _T_3009 ^ io_dma_mem_wdata[15]; // @[el2_lib.scala 259:74] + wire _T_3011 = _T_3010 ^ io_dma_mem_wdata[16]; // @[el2_lib.scala 259:74] + wire _T_3012 = _T_3011 ^ io_dma_mem_wdata[17]; // @[el2_lib.scala 259:74] + wire _T_3013 = _T_3012 ^ io_dma_mem_wdata[18]; // @[el2_lib.scala 259:74] + wire _T_3014 = _T_3013 ^ io_dma_mem_wdata[19]; // @[el2_lib.scala 259:74] + wire _T_3015 = _T_3014 ^ io_dma_mem_wdata[20]; // @[el2_lib.scala 259:74] + wire _T_3016 = _T_3015 ^ io_dma_mem_wdata[21]; // @[el2_lib.scala 259:74] + wire _T_3017 = _T_3016 ^ io_dma_mem_wdata[22]; // @[el2_lib.scala 259:74] + wire _T_3018 = _T_3017 ^ io_dma_mem_wdata[23]; // @[el2_lib.scala 259:74] + wire _T_3019 = _T_3018 ^ io_dma_mem_wdata[24]; // @[el2_lib.scala 259:74] + wire _T_3020 = _T_3019 ^ io_dma_mem_wdata[25]; // @[el2_lib.scala 259:74] + wire _T_3027 = io_dma_mem_wdata[26] ^ io_dma_mem_wdata[27]; // @[el2_lib.scala 259:74] + wire _T_3028 = _T_3027 ^ io_dma_mem_wdata[28]; // @[el2_lib.scala 259:74] + wire _T_3029 = _T_3028 ^ io_dma_mem_wdata[29]; // @[el2_lib.scala 259:74] + wire _T_3030 = _T_3029 ^ io_dma_mem_wdata[30]; // @[el2_lib.scala 259:74] + wire _T_3031 = _T_3030 ^ io_dma_mem_wdata[31]; // @[el2_lib.scala 259:74] + wire [5:0] _T_3036 = {_T_3031,_T_3020,_T_2991,_T_2962,_T_2927,_T_2892}; // @[Cat.scala 29:58] + wire _T_3037 = ^io_dma_mem_wdata[31:0]; // @[el2_lib.scala 267:13] + wire _T_3038 = ^_T_3036; // @[el2_lib.scala 267:23] + wire _T_3039 = _T_3037 ^ _T_3038; // @[el2_lib.scala 267:18] + wire [6:0] _T_3040 = {_T_3039,_T_3031,_T_3020,_T_2991,_T_2962,_T_2927,_T_2892}; // @[Cat.scala 29:58] + wire [13:0] dma_mem_ecc = {_T_2855,_T_2847,_T_2836,_T_2807,_T_2778,_T_2743,_T_2708,_T_3040}; // @[Cat.scala 29:58] + wire _T_3042 = ~_T_2660; // @[el2_ifu_mem_ctl.scala 644:45] + wire _T_3043 = iccm_correct_ecc & _T_3042; // @[el2_ifu_mem_ctl.scala 644:43] + reg [38:0] iccm_ecc_corr_data_ff; // @[Reg.scala 27:20] + wire [77:0] _T_3044 = {iccm_ecc_corr_data_ff,iccm_ecc_corr_data_ff}; // @[Cat.scala 29:58] + wire [77:0] _T_3051 = {dma_mem_ecc[13:7],io_dma_mem_wdata[63:32],dma_mem_ecc[6:0],io_dma_mem_wdata[31:0]}; // @[Cat.scala 29:58] + reg [1:0] dma_mem_addr_ff; // @[el2_ifu_mem_ctl.scala 658:53] + wire _T_3384 = _T_3296[5:0] == 6'h27; // @[el2_lib.scala 339:41] + wire _T_3382 = _T_3296[5:0] == 6'h26; // @[el2_lib.scala 339:41] + wire _T_3380 = _T_3296[5:0] == 6'h25; // @[el2_lib.scala 339:41] + wire _T_3378 = _T_3296[5:0] == 6'h24; // @[el2_lib.scala 339:41] + wire _T_3376 = _T_3296[5:0] == 6'h23; // @[el2_lib.scala 339:41] + wire _T_3374 = _T_3296[5:0] == 6'h22; // @[el2_lib.scala 339:41] + wire _T_3372 = _T_3296[5:0] == 6'h21; // @[el2_lib.scala 339:41] + wire _T_3370 = _T_3296[5:0] == 6'h20; // @[el2_lib.scala 339:41] + wire _T_3368 = _T_3296[5:0] == 6'h1f; // @[el2_lib.scala 339:41] + wire _T_3366 = _T_3296[5:0] == 6'h1e; // @[el2_lib.scala 339:41] + wire [9:0] _T_3442 = {_T_3384,_T_3382,_T_3380,_T_3378,_T_3376,_T_3374,_T_3372,_T_3370,_T_3368,_T_3366}; // @[el2_lib.scala 342:69] + wire _T_3364 = _T_3296[5:0] == 6'h1d; // @[el2_lib.scala 339:41] + wire _T_3362 = _T_3296[5:0] == 6'h1c; // @[el2_lib.scala 339:41] + wire _T_3360 = _T_3296[5:0] == 6'h1b; // @[el2_lib.scala 339:41] + wire _T_3358 = _T_3296[5:0] == 6'h1a; // @[el2_lib.scala 339:41] + wire _T_3356 = _T_3296[5:0] == 6'h19; // @[el2_lib.scala 339:41] + wire _T_3354 = _T_3296[5:0] == 6'h18; // @[el2_lib.scala 339:41] + wire _T_3352 = _T_3296[5:0] == 6'h17; // @[el2_lib.scala 339:41] + wire _T_3350 = _T_3296[5:0] == 6'h16; // @[el2_lib.scala 339:41] + wire _T_3348 = _T_3296[5:0] == 6'h15; // @[el2_lib.scala 339:41] + wire _T_3346 = _T_3296[5:0] == 6'h14; // @[el2_lib.scala 339:41] + wire [9:0] _T_3433 = {_T_3364,_T_3362,_T_3360,_T_3358,_T_3356,_T_3354,_T_3352,_T_3350,_T_3348,_T_3346}; // @[el2_lib.scala 342:69] + wire _T_3344 = _T_3296[5:0] == 6'h13; // @[el2_lib.scala 339:41] + wire _T_3342 = _T_3296[5:0] == 6'h12; // @[el2_lib.scala 339:41] + wire _T_3340 = _T_3296[5:0] == 6'h11; // @[el2_lib.scala 339:41] + wire _T_3338 = _T_3296[5:0] == 6'h10; // @[el2_lib.scala 339:41] + wire _T_3336 = _T_3296[5:0] == 6'hf; // @[el2_lib.scala 339:41] + wire _T_3334 = _T_3296[5:0] == 6'he; // @[el2_lib.scala 339:41] + wire _T_3332 = _T_3296[5:0] == 6'hd; // @[el2_lib.scala 339:41] + wire _T_3330 = _T_3296[5:0] == 6'hc; // @[el2_lib.scala 339:41] + wire _T_3328 = _T_3296[5:0] == 6'hb; // @[el2_lib.scala 339:41] + wire _T_3326 = _T_3296[5:0] == 6'ha; // @[el2_lib.scala 339:41] + wire [9:0] _T_3423 = {_T_3344,_T_3342,_T_3340,_T_3338,_T_3336,_T_3334,_T_3332,_T_3330,_T_3328,_T_3326}; // @[el2_lib.scala 342:69] + wire _T_3324 = _T_3296[5:0] == 6'h9; // @[el2_lib.scala 339:41] + wire _T_3322 = _T_3296[5:0] == 6'h8; // @[el2_lib.scala 339:41] + wire _T_3320 = _T_3296[5:0] == 6'h7; // @[el2_lib.scala 339:41] + wire _T_3318 = _T_3296[5:0] == 6'h6; // @[el2_lib.scala 339:41] + wire _T_3316 = _T_3296[5:0] == 6'h5; // @[el2_lib.scala 339:41] + wire _T_3314 = _T_3296[5:0] == 6'h4; // @[el2_lib.scala 339:41] + wire _T_3312 = _T_3296[5:0] == 6'h3; // @[el2_lib.scala 339:41] + wire _T_3310 = _T_3296[5:0] == 6'h2; // @[el2_lib.scala 339:41] + wire _T_3308 = _T_3296[5:0] == 6'h1; // @[el2_lib.scala 339:41] + wire [18:0] _T_3424 = {_T_3423,_T_3324,_T_3322,_T_3320,_T_3318,_T_3316,_T_3314,_T_3312,_T_3310,_T_3308}; // @[el2_lib.scala 342:69] + wire [38:0] _T_3444 = {_T_3442,_T_3433,_T_3424}; // @[el2_lib.scala 342:69] + wire [7:0] _T_3399 = {io_iccm_rd_data_ecc[35],io_iccm_rd_data_ecc[3:1],io_iccm_rd_data_ecc[34],io_iccm_rd_data_ecc[0],io_iccm_rd_data_ecc[33:32]}; // @[Cat.scala 29:58] + wire [38:0] _T_3405 = {io_iccm_rd_data_ecc[38],io_iccm_rd_data_ecc[31:26],io_iccm_rd_data_ecc[37],io_iccm_rd_data_ecc[25:11],io_iccm_rd_data_ecc[36],io_iccm_rd_data_ecc[10:4],_T_3399}; // @[Cat.scala 29:58] + wire [38:0] _T_3445 = _T_3444 ^ _T_3405; // @[el2_lib.scala 342:76] + wire [38:0] _T_3446 = _T_3300 ? _T_3445 : _T_3405; // @[el2_lib.scala 342:31] + wire [31:0] iccm_corrected_data_0 = {_T_3446[37:32],_T_3446[30:16],_T_3446[14:8],_T_3446[6:4],_T_3446[2]}; // @[Cat.scala 29:58] + wire _T_3769 = _T_3681[5:0] == 6'h27; // @[el2_lib.scala 339:41] + wire _T_3767 = _T_3681[5:0] == 6'h26; // @[el2_lib.scala 339:41] + wire _T_3765 = _T_3681[5:0] == 6'h25; // @[el2_lib.scala 339:41] + wire _T_3763 = _T_3681[5:0] == 6'h24; // @[el2_lib.scala 339:41] + wire _T_3761 = _T_3681[5:0] == 6'h23; // @[el2_lib.scala 339:41] + wire _T_3759 = _T_3681[5:0] == 6'h22; // @[el2_lib.scala 339:41] + wire _T_3757 = _T_3681[5:0] == 6'h21; // @[el2_lib.scala 339:41] + wire _T_3755 = _T_3681[5:0] == 6'h20; // @[el2_lib.scala 339:41] + wire _T_3753 = _T_3681[5:0] == 6'h1f; // @[el2_lib.scala 339:41] + wire _T_3751 = _T_3681[5:0] == 6'h1e; // @[el2_lib.scala 339:41] + wire [9:0] _T_3827 = {_T_3769,_T_3767,_T_3765,_T_3763,_T_3761,_T_3759,_T_3757,_T_3755,_T_3753,_T_3751}; // @[el2_lib.scala 342:69] + wire _T_3749 = _T_3681[5:0] == 6'h1d; // @[el2_lib.scala 339:41] + wire _T_3747 = _T_3681[5:0] == 6'h1c; // @[el2_lib.scala 339:41] + wire _T_3745 = _T_3681[5:0] == 6'h1b; // @[el2_lib.scala 339:41] + wire _T_3743 = _T_3681[5:0] == 6'h1a; // @[el2_lib.scala 339:41] + wire _T_3741 = _T_3681[5:0] == 6'h19; // @[el2_lib.scala 339:41] + wire _T_3739 = _T_3681[5:0] == 6'h18; // @[el2_lib.scala 339:41] + wire _T_3737 = _T_3681[5:0] == 6'h17; // @[el2_lib.scala 339:41] + wire _T_3735 = _T_3681[5:0] == 6'h16; // @[el2_lib.scala 339:41] + wire _T_3733 = _T_3681[5:0] == 6'h15; // @[el2_lib.scala 339:41] + wire _T_3731 = _T_3681[5:0] == 6'h14; // @[el2_lib.scala 339:41] + wire [9:0] _T_3818 = {_T_3749,_T_3747,_T_3745,_T_3743,_T_3741,_T_3739,_T_3737,_T_3735,_T_3733,_T_3731}; // @[el2_lib.scala 342:69] + wire _T_3729 = _T_3681[5:0] == 6'h13; // @[el2_lib.scala 339:41] + wire _T_3727 = _T_3681[5:0] == 6'h12; // @[el2_lib.scala 339:41] + wire _T_3725 = _T_3681[5:0] == 6'h11; // @[el2_lib.scala 339:41] + wire _T_3723 = _T_3681[5:0] == 6'h10; // @[el2_lib.scala 339:41] + wire _T_3721 = _T_3681[5:0] == 6'hf; // @[el2_lib.scala 339:41] + wire _T_3719 = _T_3681[5:0] == 6'he; // @[el2_lib.scala 339:41] + wire _T_3717 = _T_3681[5:0] == 6'hd; // @[el2_lib.scala 339:41] + wire _T_3715 = _T_3681[5:0] == 6'hc; // @[el2_lib.scala 339:41] + wire _T_3713 = _T_3681[5:0] == 6'hb; // @[el2_lib.scala 339:41] + wire _T_3711 = _T_3681[5:0] == 6'ha; // @[el2_lib.scala 339:41] + wire [9:0] _T_3808 = {_T_3729,_T_3727,_T_3725,_T_3723,_T_3721,_T_3719,_T_3717,_T_3715,_T_3713,_T_3711}; // @[el2_lib.scala 342:69] + wire _T_3709 = _T_3681[5:0] == 6'h9; // @[el2_lib.scala 339:41] + wire _T_3707 = _T_3681[5:0] == 6'h8; // @[el2_lib.scala 339:41] + wire _T_3705 = _T_3681[5:0] == 6'h7; // @[el2_lib.scala 339:41] + wire _T_3703 = _T_3681[5:0] == 6'h6; // @[el2_lib.scala 339:41] + wire _T_3701 = _T_3681[5:0] == 6'h5; // @[el2_lib.scala 339:41] + wire _T_3699 = _T_3681[5:0] == 6'h4; // @[el2_lib.scala 339:41] + wire _T_3697 = _T_3681[5:0] == 6'h3; // @[el2_lib.scala 339:41] + wire _T_3695 = _T_3681[5:0] == 6'h2; // @[el2_lib.scala 339:41] + wire _T_3693 = _T_3681[5:0] == 6'h1; // @[el2_lib.scala 339:41] + wire [18:0] _T_3809 = {_T_3808,_T_3709,_T_3707,_T_3705,_T_3703,_T_3701,_T_3699,_T_3697,_T_3695,_T_3693}; // @[el2_lib.scala 342:69] + wire [38:0] _T_3829 = {_T_3827,_T_3818,_T_3809}; // @[el2_lib.scala 342:69] + wire [7:0] _T_3784 = {io_iccm_rd_data_ecc[74],io_iccm_rd_data_ecc[42:40],io_iccm_rd_data_ecc[73],io_iccm_rd_data_ecc[39],io_iccm_rd_data_ecc[72:71]}; // @[Cat.scala 29:58] + wire [38:0] _T_3790 = {io_iccm_rd_data_ecc[77],io_iccm_rd_data_ecc[70:65],io_iccm_rd_data_ecc[76],io_iccm_rd_data_ecc[64:50],io_iccm_rd_data_ecc[75],io_iccm_rd_data_ecc[49:43],_T_3784}; // @[Cat.scala 29:58] + wire [38:0] _T_3830 = _T_3829 ^ _T_3790; // @[el2_lib.scala 342:76] + wire [38:0] _T_3831 = _T_3685 ? _T_3830 : _T_3790; // @[el2_lib.scala 342:31] + wire [31:0] iccm_corrected_data_1 = {_T_3831[37:32],_T_3831[30:16],_T_3831[14:8],_T_3831[6:4],_T_3831[2]}; // @[Cat.scala 29:58] + wire [31:0] iccm_dma_rdata_1_muxed = dma_mem_addr_ff[0] ? iccm_corrected_data_0 : iccm_corrected_data_1; // @[el2_ifu_mem_ctl.scala 650:35] + wire _T_3304 = ~_T_3296[6]; // @[el2_lib.scala 335:55] + wire _T_3305 = _T_3298 & _T_3304; // @[el2_lib.scala 335:53] + wire _T_3689 = ~_T_3681[6]; // @[el2_lib.scala 335:55] + wire _T_3690 = _T_3683 & _T_3689; // @[el2_lib.scala 335:53] + wire [1:0] iccm_double_ecc_error = {_T_3305,_T_3690}; // @[Cat.scala 29:58] + wire iccm_dma_ecc_error_in = |iccm_double_ecc_error; // @[el2_ifu_mem_ctl.scala 652:53] + wire [63:0] _T_3055 = {io_dma_mem_addr,io_dma_mem_addr}; // @[Cat.scala 29:58] + wire [63:0] _T_3056 = {iccm_dma_rdata_1_muxed,_T_3446[37:32],_T_3446[30:16],_T_3446[14:8],_T_3446[6:4],_T_3446[2]}; // @[Cat.scala 29:58] + reg [2:0] dma_mem_tag_ff; // @[el2_ifu_mem_ctl.scala 654:54] + reg [2:0] iccm_dma_rtag_temp; // @[el2_ifu_mem_ctl.scala 655:74] + reg iccm_dma_rvalid_temp; // @[el2_ifu_mem_ctl.scala 660:76] + reg iccm_dma_ecc_error; // @[el2_ifu_mem_ctl.scala 662:74] + reg [63:0] iccm_dma_rdata_temp; // @[el2_ifu_mem_ctl.scala 664:75] + wire _T_3061 = _T_2660 & _T_2649; // @[el2_ifu_mem_ctl.scala 667:65] + wire _T_3065 = _T_3042 & iccm_correct_ecc; // @[el2_ifu_mem_ctl.scala 668:50] + reg [13:0] iccm_ecc_corr_index_ff; // @[Reg.scala 27:20] + wire [14:0] _T_3066 = {iccm_ecc_corr_index_ff,1'h0}; // @[Cat.scala 29:58] + wire [14:0] _T_3068 = _T_3065 ? _T_3066 : io_ifc_fetch_addr_bf[14:0]; // @[el2_ifu_mem_ctl.scala 668:8] + wire _T_3458 = _T_3296 == 7'h40; // @[el2_lib.scala 345:62] + wire _T_3459 = _T_3446[38] ^ _T_3458; // @[el2_lib.scala 345:44] + wire [6:0] iccm_corrected_ecc_0 = {_T_3459,_T_3446[31],_T_3446[15],_T_3446[7],_T_3446[3],_T_3446[1:0]}; // @[Cat.scala 29:58] + wire _T_3843 = _T_3681 == 7'h40; // @[el2_lib.scala 345:62] + wire _T_3844 = _T_3831[38] ^ _T_3843; // @[el2_lib.scala 345:44] + wire [6:0] iccm_corrected_ecc_1 = {_T_3844,_T_3831[31],_T_3831[15],_T_3831[7],_T_3831[3],_T_3831[1:0]}; // @[Cat.scala 29:58] + wire _T_3860 = _T_3 & ifc_iccm_access_f; // @[el2_ifu_mem_ctl.scala 680:58] + wire [31:0] iccm_corrected_data_f_mux = iccm_single_ecc_error[0] ? iccm_corrected_data_0 : iccm_corrected_data_1; // @[el2_ifu_mem_ctl.scala 682:38] + wire [6:0] iccm_corrected_ecc_f_mux = iccm_single_ecc_error[0] ? iccm_corrected_ecc_0 : iccm_corrected_ecc_1; // @[el2_ifu_mem_ctl.scala 683:37] + reg iccm_rd_ecc_single_err_ff; // @[el2_ifu_mem_ctl.scala 691:62] + wire _T_3868 = ~iccm_rd_ecc_single_err_ff; // @[el2_ifu_mem_ctl.scala 685:76] + wire _T_3869 = io_iccm_rd_ecc_single_err & _T_3868; // @[el2_ifu_mem_ctl.scala 685:74] + wire _T_3871 = _T_3869 & _T_319; // @[el2_ifu_mem_ctl.scala 685:104] + wire iccm_ecc_write_status = _T_3871 | io_iccm_dma_sb_error; // @[el2_ifu_mem_ctl.scala 685:127] + wire _T_3872 = io_iccm_rd_ecc_single_err | iccm_rd_ecc_single_err_ff; // @[el2_ifu_mem_ctl.scala 686:67] + reg [13:0] iccm_rw_addr_f; // @[el2_ifu_mem_ctl.scala 690:51] + wire [13:0] _T_3877 = iccm_rw_addr_f + 14'h1; // @[el2_ifu_mem_ctl.scala 689:102] + wire [38:0] _T_3881 = {iccm_corrected_ecc_f_mux,iccm_corrected_data_f_mux}; // @[Cat.scala 29:58] + wire _T_3886 = ~io_ifc_fetch_uncacheable_bf; // @[el2_ifu_mem_ctl.scala 694:41] + wire _T_3887 = io_ifc_fetch_req_bf & _T_3886; // @[el2_ifu_mem_ctl.scala 694:39] + wire _T_3888 = ~io_ifc_iccm_access_bf; // @[el2_ifu_mem_ctl.scala 694:72] + wire _T_3889 = _T_3887 & _T_3888; // @[el2_ifu_mem_ctl.scala 694:70] + wire _T_3891 = ~miss_state_en; // @[el2_ifu_mem_ctl.scala 695:34] + wire _T_3892 = _T_2219 & _T_3891; // @[el2_ifu_mem_ctl.scala 695:32] + wire _T_3895 = _T_2235 & _T_3891; // @[el2_ifu_mem_ctl.scala 696:37] + wire _T_3896 = _T_3892 | _T_3895; // @[el2_ifu_mem_ctl.scala 695:88] + wire _T_3897 = miss_state == 3'h7; // @[el2_ifu_mem_ctl.scala 697:19] + wire _T_3899 = _T_3897 & _T_3891; // @[el2_ifu_mem_ctl.scala 697:41] + wire _T_3900 = _T_3896 | _T_3899; // @[el2_ifu_mem_ctl.scala 696:88] + wire _T_3901 = miss_state == 3'h3; // @[el2_ifu_mem_ctl.scala 698:19] + wire _T_3903 = _T_3901 & _T_3891; // @[el2_ifu_mem_ctl.scala 698:35] + wire _T_3904 = _T_3900 | _T_3903; // @[el2_ifu_mem_ctl.scala 697:88] + wire _T_3907 = _T_2234 & _T_3891; // @[el2_ifu_mem_ctl.scala 699:38] + wire _T_3908 = _T_3904 | _T_3907; // @[el2_ifu_mem_ctl.scala 698:88] + wire _T_3910 = _T_2235 & miss_state_en; // @[el2_ifu_mem_ctl.scala 700:37] + wire _T_3911 = miss_nxtstate == 3'h3; // @[el2_ifu_mem_ctl.scala 700:71] + wire _T_3912 = _T_3910 & _T_3911; // @[el2_ifu_mem_ctl.scala 700:54] + wire _T_3913 = _T_3908 | _T_3912; // @[el2_ifu_mem_ctl.scala 699:57] + wire _T_3914 = ~_T_3913; // @[el2_ifu_mem_ctl.scala 695:5] + wire _T_3915 = _T_3889 & _T_3914; // @[el2_ifu_mem_ctl.scala 694:96] + wire _T_3916 = io_ifc_fetch_req_bf & io_exu_flush_final; // @[el2_ifu_mem_ctl.scala 701:26] + wire _T_3918 = _T_3916 & _T_3886; // @[el2_ifu_mem_ctl.scala 701:48] + wire _T_3920 = _T_3918 & _T_3888; // @[el2_ifu_mem_ctl.scala 701:79] + wire [1:0] _T_3923 = write_ic_16_bytes ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire _T_9729 = bus_ifu_wr_en_ff_q & replace_way_mb_any_1; // @[el2_ifu_mem_ctl.scala 796:72] + wire bus_wren_1 = _T_9729 & miss_pending; // @[el2_ifu_mem_ctl.scala 796:96] + wire _T_9728 = bus_ifu_wr_en_ff_q & replace_way_mb_any_0; // @[el2_ifu_mem_ctl.scala 796:72] + wire bus_wren_0 = _T_9728 & miss_pending; // @[el2_ifu_mem_ctl.scala 796:96] + wire [1:0] bus_ic_wr_en = {bus_wren_1,bus_wren_0}; // @[Cat.scala 29:58] + wire _T_3929 = ~_T_108; // @[el2_ifu_mem_ctl.scala 704:106] + wire _T_3930 = _T_2219 & _T_3929; // @[el2_ifu_mem_ctl.scala 704:104] + wire _T_3931 = _T_2235 | _T_3930; // @[el2_ifu_mem_ctl.scala 704:77] + wire _T_3935 = ~_T_51; // @[el2_ifu_mem_ctl.scala 704:172] + wire _T_3936 = _T_3931 & _T_3935; // @[el2_ifu_mem_ctl.scala 704:170] + wire _T_3937 = ~_T_3936; // @[el2_ifu_mem_ctl.scala 704:44] + wire _T_3941 = reset_ic_in | reset_ic_ff; // @[el2_ifu_mem_ctl.scala 707:62] + wire _T_3942 = ~_T_3941; // @[el2_ifu_mem_ctl.scala 707:48] + wire _T_3943 = _T_276 & _T_3942; // @[el2_ifu_mem_ctl.scala 707:46] + wire _T_3944 = ~reset_tag_valid_for_miss; // @[el2_ifu_mem_ctl.scala 707:79] + wire ic_valid = _T_3943 & _T_3944; // @[el2_ifu_mem_ctl.scala 707:77] + wire _T_3946 = debug_c1_clken & io_ic_debug_tag_array; // @[el2_ifu_mem_ctl.scala 708:80] + reg [6:0] ifu_status_wr_addr_ff; // @[el2_ifu_mem_ctl.scala 711:12] + wire _T_3949 = io_ic_debug_wr_en & io_ic_debug_tag_array; // @[el2_ifu_mem_ctl.scala 714:72] + wire _T_9726 = bus_ifu_wr_en_ff_q & last_beat; // @[el2_ifu_mem_ctl.scala 795:43] + wire way_status_wr_en = _T_9726 | ic_act_hit_f; // @[el2_ifu_mem_ctl.scala 795:56] + reg way_status_wr_en_ff; // @[el2_ifu_mem_ctl.scala 716:12] + wire way_status_hit_new = io_ic_rd_hit[0]; // @[el2_ifu_mem_ctl.scala 791:39] + reg way_status_new_ff; // @[el2_ifu_mem_ctl.scala 722:12] + wire _T_3969 = ifu_status_wr_addr_ff[2:0] == 3'h0; // @[el2_ifu_mem_ctl.scala 728:126] + wire _T_3970 = _T_3969 & way_status_wr_en_ff; // @[el2_ifu_mem_ctl.scala 728:134] + wire _T_3973 = ifu_status_wr_addr_ff[2:0] == 3'h1; // @[el2_ifu_mem_ctl.scala 728:126] + wire _T_3974 = _T_3973 & way_status_wr_en_ff; // @[el2_ifu_mem_ctl.scala 728:134] + wire _T_3977 = ifu_status_wr_addr_ff[2:0] == 3'h2; // @[el2_ifu_mem_ctl.scala 728:126] + wire _T_3978 = _T_3977 & way_status_wr_en_ff; // @[el2_ifu_mem_ctl.scala 728:134] + wire _T_3981 = ifu_status_wr_addr_ff[2:0] == 3'h3; // @[el2_ifu_mem_ctl.scala 728:126] + wire _T_3982 = _T_3981 & way_status_wr_en_ff; // @[el2_ifu_mem_ctl.scala 728:134] + wire _T_3985 = ifu_status_wr_addr_ff[2:0] == 3'h4; // @[el2_ifu_mem_ctl.scala 728:126] + wire _T_3986 = _T_3985 & way_status_wr_en_ff; // @[el2_ifu_mem_ctl.scala 728:134] + wire _T_3989 = ifu_status_wr_addr_ff[2:0] == 3'h5; // @[el2_ifu_mem_ctl.scala 728:126] + wire _T_3990 = _T_3989 & way_status_wr_en_ff; // @[el2_ifu_mem_ctl.scala 728:134] + wire _T_3993 = ifu_status_wr_addr_ff[2:0] == 3'h6; // @[el2_ifu_mem_ctl.scala 728:126] + wire _T_3994 = _T_3993 & way_status_wr_en_ff; // @[el2_ifu_mem_ctl.scala 728:134] + wire _T_3997 = ifu_status_wr_addr_ff[2:0] == 3'h7; // @[el2_ifu_mem_ctl.scala 728:126] + wire _T_3998 = _T_3997 & way_status_wr_en_ff; // @[el2_ifu_mem_ctl.scala 728:134] + wire _T_9732 = _T_100 & replace_way_mb_any_1; // @[el2_ifu_mem_ctl.scala 798:82] + wire _T_9733 = _T_9732 & miss_pending; // @[el2_ifu_mem_ctl.scala 798:106] + wire bus_wren_last_1 = _T_9733 & bus_last_data_beat; // @[el2_ifu_mem_ctl.scala 798:121] + wire wren_reset_miss_1 = replace_way_mb_any_1 & reset_tag_valid_for_miss; // @[el2_ifu_mem_ctl.scala 799:82] + wire _T_9735 = bus_wren_last_1 | wren_reset_miss_1; // @[el2_ifu_mem_ctl.scala 800:71] + wire _T_9730 = _T_100 & replace_way_mb_any_0; // @[el2_ifu_mem_ctl.scala 798:82] + wire _T_9731 = _T_9730 & miss_pending; // @[el2_ifu_mem_ctl.scala 798:106] + wire bus_wren_last_0 = _T_9731 & bus_last_data_beat; // @[el2_ifu_mem_ctl.scala 798:121] + wire wren_reset_miss_0 = replace_way_mb_any_0 & reset_tag_valid_for_miss; // @[el2_ifu_mem_ctl.scala 799:82] + wire _T_9734 = bus_wren_last_0 | wren_reset_miss_0; // @[el2_ifu_mem_ctl.scala 800:71] + wire [1:0] ifu_tag_wren = {_T_9735,_T_9734}; // @[Cat.scala 29:58] + wire [1:0] _T_9770 = _T_3949 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] ic_debug_tag_wr_en = _T_9770 & io_ic_debug_way; // @[el2_ifu_mem_ctl.scala 834:90] + reg [1:0] ifu_tag_wren_ff; // @[el2_ifu_mem_ctl.scala 743:12] + reg ic_valid_ff; // @[el2_ifu_mem_ctl.scala 747:12] + wire _T_5012 = ifu_ic_rw_int_addr_ff[6:5] == 2'h0; // @[el2_ifu_mem_ctl.scala 751:76] + wire _T_5014 = _T_5012 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 751:85] + wire _T_5016 = perr_ic_index_ff[6:5] == 2'h0; // @[el2_ifu_mem_ctl.scala 752:68] + wire _T_5018 = _T_5016 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 752:77] + wire _T_5019 = _T_5014 | _T_5018; // @[el2_ifu_mem_ctl.scala 751:107] + wire _T_5020 = _T_5019 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 752:100] + wire _T_5024 = _T_5012 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 751:85] + wire _T_5028 = _T_5016 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 752:77] + wire _T_5029 = _T_5024 | _T_5028; // @[el2_ifu_mem_ctl.scala 751:107] + wire _T_5030 = _T_5029 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 752:100] + wire [1:0] tag_valid_clken_0 = {_T_5030,_T_5020}; // @[Cat.scala 29:58] + wire _T_5032 = ifu_ic_rw_int_addr_ff[6:5] == 2'h1; // @[el2_ifu_mem_ctl.scala 751:76] + wire _T_5034 = _T_5032 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 751:85] + wire _T_5036 = perr_ic_index_ff[6:5] == 2'h1; // @[el2_ifu_mem_ctl.scala 752:68] + wire _T_5038 = _T_5036 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 752:77] + wire _T_5039 = _T_5034 | _T_5038; // @[el2_ifu_mem_ctl.scala 751:107] + wire _T_5040 = _T_5039 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 752:100] + wire _T_5044 = _T_5032 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 751:85] + wire _T_5048 = _T_5036 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 752:77] + wire _T_5049 = _T_5044 | _T_5048; // @[el2_ifu_mem_ctl.scala 751:107] + wire _T_5050 = _T_5049 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 752:100] + wire [1:0] tag_valid_clken_1 = {_T_5050,_T_5040}; // @[Cat.scala 29:58] + wire _T_5052 = ifu_ic_rw_int_addr_ff[6:5] == 2'h2; // @[el2_ifu_mem_ctl.scala 751:76] + wire _T_5054 = _T_5052 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 751:85] + wire _T_5056 = perr_ic_index_ff[6:5] == 2'h2; // @[el2_ifu_mem_ctl.scala 752:68] + wire _T_5058 = _T_5056 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 752:77] + wire _T_5059 = _T_5054 | _T_5058; // @[el2_ifu_mem_ctl.scala 751:107] + wire _T_5060 = _T_5059 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 752:100] + wire _T_5064 = _T_5052 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 751:85] + wire _T_5068 = _T_5056 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 752:77] + wire _T_5069 = _T_5064 | _T_5068; // @[el2_ifu_mem_ctl.scala 751:107] + wire _T_5070 = _T_5069 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 752:100] + wire [1:0] tag_valid_clken_2 = {_T_5070,_T_5060}; // @[Cat.scala 29:58] + wire _T_5072 = ifu_ic_rw_int_addr_ff[6:5] == 2'h3; // @[el2_ifu_mem_ctl.scala 751:76] + wire _T_5074 = _T_5072 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 751:85] + wire _T_5076 = perr_ic_index_ff[6:5] == 2'h3; // @[el2_ifu_mem_ctl.scala 752:68] + wire _T_5078 = _T_5076 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 752:77] + wire _T_5079 = _T_5074 | _T_5078; // @[el2_ifu_mem_ctl.scala 751:107] + wire _T_5080 = _T_5079 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 752:100] + wire _T_5084 = _T_5072 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 751:85] + wire _T_5088 = _T_5076 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 752:77] + wire _T_5089 = _T_5084 | _T_5088; // @[el2_ifu_mem_ctl.scala 751:107] + wire _T_5090 = _T_5089 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 752:100] + wire [1:0] tag_valid_clken_3 = {_T_5090,_T_5080}; // @[Cat.scala 29:58] + wire _T_5101 = ic_valid_ff & _T_195; // @[el2_ifu_mem_ctl.scala 760:95] + wire _T_5102 = ~perr_sel_invalidate; // @[el2_ifu_mem_ctl.scala 760:122] + wire _T_5103 = _T_5101 & _T_5102; // @[el2_ifu_mem_ctl.scala 760:120] + wire _T_5106 = _T_4620 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5107 = perr_ic_index_ff == 7'h0; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_5109 = _T_5107 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5110 = _T_5106 | _T_5109; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5111 = _T_5110 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5121 = _T_4621 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5122 = perr_ic_index_ff == 7'h1; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_5124 = _T_5122 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5125 = _T_5121 | _T_5124; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5126 = _T_5125 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5136 = _T_4622 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5137 = perr_ic_index_ff == 7'h2; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_5139 = _T_5137 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5140 = _T_5136 | _T_5139; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5141 = _T_5140 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5151 = _T_4623 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5152 = perr_ic_index_ff == 7'h3; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_5154 = _T_5152 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5155 = _T_5151 | _T_5154; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5156 = _T_5155 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5166 = _T_4624 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5167 = perr_ic_index_ff == 7'h4; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_5169 = _T_5167 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5170 = _T_5166 | _T_5169; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5171 = _T_5170 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5181 = _T_4625 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5182 = perr_ic_index_ff == 7'h5; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_5184 = _T_5182 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5185 = _T_5181 | _T_5184; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5186 = _T_5185 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5196 = _T_4626 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5197 = perr_ic_index_ff == 7'h6; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_5199 = _T_5197 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5200 = _T_5196 | _T_5199; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5201 = _T_5200 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5211 = _T_4627 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5212 = perr_ic_index_ff == 7'h7; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_5214 = _T_5212 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5215 = _T_5211 | _T_5214; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5216 = _T_5215 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5226 = _T_4628 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5227 = perr_ic_index_ff == 7'h8; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_5229 = _T_5227 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5230 = _T_5226 | _T_5229; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5231 = _T_5230 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5241 = _T_4629 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5242 = perr_ic_index_ff == 7'h9; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_5244 = _T_5242 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5245 = _T_5241 | _T_5244; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5246 = _T_5245 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5256 = _T_4630 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5257 = perr_ic_index_ff == 7'ha; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_5259 = _T_5257 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5260 = _T_5256 | _T_5259; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5261 = _T_5260 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5271 = _T_4631 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5272 = perr_ic_index_ff == 7'hb; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_5274 = _T_5272 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5275 = _T_5271 | _T_5274; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5276 = _T_5275 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5286 = _T_4632 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5287 = perr_ic_index_ff == 7'hc; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_5289 = _T_5287 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5290 = _T_5286 | _T_5289; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5291 = _T_5290 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5301 = _T_4633 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5302 = perr_ic_index_ff == 7'hd; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_5304 = _T_5302 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5305 = _T_5301 | _T_5304; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5306 = _T_5305 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5316 = _T_4634 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5317 = perr_ic_index_ff == 7'he; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_5319 = _T_5317 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5320 = _T_5316 | _T_5319; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5321 = _T_5320 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5331 = _T_4635 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5332 = perr_ic_index_ff == 7'hf; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_5334 = _T_5332 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5335 = _T_5331 | _T_5334; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5336 = _T_5335 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5346 = _T_4636 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5347 = perr_ic_index_ff == 7'h10; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_5349 = _T_5347 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5350 = _T_5346 | _T_5349; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5351 = _T_5350 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5361 = _T_4637 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5362 = perr_ic_index_ff == 7'h11; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_5364 = _T_5362 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5365 = _T_5361 | _T_5364; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5366 = _T_5365 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5376 = _T_4638 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5377 = perr_ic_index_ff == 7'h12; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_5379 = _T_5377 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5380 = _T_5376 | _T_5379; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5381 = _T_5380 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5391 = _T_4639 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5392 = perr_ic_index_ff == 7'h13; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_5394 = _T_5392 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5395 = _T_5391 | _T_5394; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5396 = _T_5395 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5406 = _T_4640 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5407 = perr_ic_index_ff == 7'h14; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_5409 = _T_5407 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5410 = _T_5406 | _T_5409; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5411 = _T_5410 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5421 = _T_4641 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5422 = perr_ic_index_ff == 7'h15; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_5424 = _T_5422 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5425 = _T_5421 | _T_5424; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5426 = _T_5425 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5436 = _T_4642 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5437 = perr_ic_index_ff == 7'h16; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_5439 = _T_5437 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5440 = _T_5436 | _T_5439; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5441 = _T_5440 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5451 = _T_4643 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5452 = perr_ic_index_ff == 7'h17; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_5454 = _T_5452 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5455 = _T_5451 | _T_5454; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5456 = _T_5455 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5466 = _T_4644 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5467 = perr_ic_index_ff == 7'h18; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_5469 = _T_5467 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5470 = _T_5466 | _T_5469; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5471 = _T_5470 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5481 = _T_4645 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5482 = perr_ic_index_ff == 7'h19; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_5484 = _T_5482 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5485 = _T_5481 | _T_5484; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5486 = _T_5485 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5496 = _T_4646 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5497 = perr_ic_index_ff == 7'h1a; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_5499 = _T_5497 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5500 = _T_5496 | _T_5499; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5501 = _T_5500 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5511 = _T_4647 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5512 = perr_ic_index_ff == 7'h1b; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_5514 = _T_5512 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5515 = _T_5511 | _T_5514; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5516 = _T_5515 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5526 = _T_4648 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5527 = perr_ic_index_ff == 7'h1c; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_5529 = _T_5527 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5530 = _T_5526 | _T_5529; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5531 = _T_5530 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5541 = _T_4649 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5542 = perr_ic_index_ff == 7'h1d; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_5544 = _T_5542 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5545 = _T_5541 | _T_5544; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5546 = _T_5545 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5556 = _T_4650 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5557 = perr_ic_index_ff == 7'h1e; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_5559 = _T_5557 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5560 = _T_5556 | _T_5559; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5561 = _T_5560 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5571 = _T_4651 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5572 = perr_ic_index_ff == 7'h1f; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_5574 = _T_5572 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5575 = _T_5571 | _T_5574; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5576 = _T_5575 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5586 = _T_4620 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5589 = _T_5107 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5590 = _T_5586 | _T_5589; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5591 = _T_5590 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5601 = _T_4621 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5604 = _T_5122 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5605 = _T_5601 | _T_5604; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5606 = _T_5605 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5616 = _T_4622 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5619 = _T_5137 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5620 = _T_5616 | _T_5619; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5621 = _T_5620 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5631 = _T_4623 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5634 = _T_5152 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5635 = _T_5631 | _T_5634; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5636 = _T_5635 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5646 = _T_4624 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5649 = _T_5167 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5650 = _T_5646 | _T_5649; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5651 = _T_5650 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5661 = _T_4625 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5664 = _T_5182 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5665 = _T_5661 | _T_5664; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5666 = _T_5665 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5676 = _T_4626 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5679 = _T_5197 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5680 = _T_5676 | _T_5679; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5681 = _T_5680 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5691 = _T_4627 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5694 = _T_5212 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5695 = _T_5691 | _T_5694; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5696 = _T_5695 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5706 = _T_4628 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5709 = _T_5227 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5710 = _T_5706 | _T_5709; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5711 = _T_5710 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5721 = _T_4629 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5724 = _T_5242 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5725 = _T_5721 | _T_5724; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5726 = _T_5725 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5736 = _T_4630 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5739 = _T_5257 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5740 = _T_5736 | _T_5739; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5741 = _T_5740 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5751 = _T_4631 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5754 = _T_5272 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5755 = _T_5751 | _T_5754; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5756 = _T_5755 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5766 = _T_4632 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5769 = _T_5287 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5770 = _T_5766 | _T_5769; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5771 = _T_5770 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5781 = _T_4633 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5784 = _T_5302 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5785 = _T_5781 | _T_5784; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5786 = _T_5785 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5796 = _T_4634 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5799 = _T_5317 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5800 = _T_5796 | _T_5799; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5801 = _T_5800 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5811 = _T_4635 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5814 = _T_5332 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5815 = _T_5811 | _T_5814; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5816 = _T_5815 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5826 = _T_4636 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5829 = _T_5347 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5830 = _T_5826 | _T_5829; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5831 = _T_5830 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5841 = _T_4637 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5844 = _T_5362 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5845 = _T_5841 | _T_5844; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5846 = _T_5845 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5856 = _T_4638 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5859 = _T_5377 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5860 = _T_5856 | _T_5859; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5861 = _T_5860 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5871 = _T_4639 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5874 = _T_5392 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5875 = _T_5871 | _T_5874; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5876 = _T_5875 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5886 = _T_4640 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5889 = _T_5407 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5890 = _T_5886 | _T_5889; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5891 = _T_5890 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5901 = _T_4641 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5904 = _T_5422 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5905 = _T_5901 | _T_5904; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5906 = _T_5905 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5916 = _T_4642 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5919 = _T_5437 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5920 = _T_5916 | _T_5919; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5921 = _T_5920 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5931 = _T_4643 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5934 = _T_5452 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5935 = _T_5931 | _T_5934; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5936 = _T_5935 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5946 = _T_4644 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5949 = _T_5467 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5950 = _T_5946 | _T_5949; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5951 = _T_5950 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5961 = _T_4645 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5964 = _T_5482 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5965 = _T_5961 | _T_5964; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5966 = _T_5965 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5976 = _T_4646 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5979 = _T_5497 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5980 = _T_5976 | _T_5979; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5981 = _T_5980 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_5991 = _T_4647 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_5994 = _T_5512 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_5995 = _T_5991 | _T_5994; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_5996 = _T_5995 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6006 = _T_4648 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6009 = _T_5527 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6010 = _T_6006 | _T_6009; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6011 = _T_6010 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6021 = _T_4649 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6024 = _T_5542 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6025 = _T_6021 | _T_6024; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6026 = _T_6025 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6036 = _T_4650 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6039 = _T_5557 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6040 = _T_6036 | _T_6039; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6041 = _T_6040 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6051 = _T_4651 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6054 = _T_5572 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6055 = _T_6051 | _T_6054; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6056 = _T_6055 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6066 = _T_4652 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6067 = perr_ic_index_ff == 7'h20; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_6069 = _T_6067 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6070 = _T_6066 | _T_6069; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6071 = _T_6070 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6081 = _T_4653 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6082 = perr_ic_index_ff == 7'h21; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_6084 = _T_6082 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6085 = _T_6081 | _T_6084; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6086 = _T_6085 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6096 = _T_4654 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6097 = perr_ic_index_ff == 7'h22; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_6099 = _T_6097 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6100 = _T_6096 | _T_6099; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6101 = _T_6100 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6111 = _T_4655 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6112 = perr_ic_index_ff == 7'h23; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_6114 = _T_6112 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6115 = _T_6111 | _T_6114; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6116 = _T_6115 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6126 = _T_4656 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6127 = perr_ic_index_ff == 7'h24; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_6129 = _T_6127 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6130 = _T_6126 | _T_6129; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6131 = _T_6130 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6141 = _T_4657 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6142 = perr_ic_index_ff == 7'h25; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_6144 = _T_6142 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6145 = _T_6141 | _T_6144; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6146 = _T_6145 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6156 = _T_4658 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6157 = perr_ic_index_ff == 7'h26; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_6159 = _T_6157 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6160 = _T_6156 | _T_6159; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6161 = _T_6160 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6171 = _T_4659 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6172 = perr_ic_index_ff == 7'h27; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_6174 = _T_6172 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6175 = _T_6171 | _T_6174; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6176 = _T_6175 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6186 = _T_4660 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6187 = perr_ic_index_ff == 7'h28; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_6189 = _T_6187 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6190 = _T_6186 | _T_6189; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6191 = _T_6190 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6201 = _T_4661 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6202 = perr_ic_index_ff == 7'h29; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_6204 = _T_6202 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6205 = _T_6201 | _T_6204; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6206 = _T_6205 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6216 = _T_4662 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6217 = perr_ic_index_ff == 7'h2a; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_6219 = _T_6217 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6220 = _T_6216 | _T_6219; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6221 = _T_6220 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6231 = _T_4663 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6232 = perr_ic_index_ff == 7'h2b; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_6234 = _T_6232 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6235 = _T_6231 | _T_6234; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6236 = _T_6235 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6246 = _T_4664 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6247 = perr_ic_index_ff == 7'h2c; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_6249 = _T_6247 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6250 = _T_6246 | _T_6249; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6251 = _T_6250 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6261 = _T_4665 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6262 = perr_ic_index_ff == 7'h2d; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_6264 = _T_6262 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6265 = _T_6261 | _T_6264; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6266 = _T_6265 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6276 = _T_4666 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6277 = perr_ic_index_ff == 7'h2e; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_6279 = _T_6277 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6280 = _T_6276 | _T_6279; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6281 = _T_6280 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6291 = _T_4667 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6292 = perr_ic_index_ff == 7'h2f; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_6294 = _T_6292 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6295 = _T_6291 | _T_6294; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6296 = _T_6295 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6306 = _T_4668 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6307 = perr_ic_index_ff == 7'h30; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_6309 = _T_6307 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6310 = _T_6306 | _T_6309; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6311 = _T_6310 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6321 = _T_4669 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6322 = perr_ic_index_ff == 7'h31; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_6324 = _T_6322 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6325 = _T_6321 | _T_6324; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6326 = _T_6325 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6336 = _T_4670 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6337 = perr_ic_index_ff == 7'h32; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_6339 = _T_6337 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6340 = _T_6336 | _T_6339; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6341 = _T_6340 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6351 = _T_4671 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6352 = perr_ic_index_ff == 7'h33; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_6354 = _T_6352 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6355 = _T_6351 | _T_6354; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6356 = _T_6355 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6366 = _T_4672 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6367 = perr_ic_index_ff == 7'h34; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_6369 = _T_6367 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6370 = _T_6366 | _T_6369; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6371 = _T_6370 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6381 = _T_4673 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6382 = perr_ic_index_ff == 7'h35; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_6384 = _T_6382 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6385 = _T_6381 | _T_6384; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6386 = _T_6385 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6396 = _T_4674 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6397 = perr_ic_index_ff == 7'h36; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_6399 = _T_6397 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6400 = _T_6396 | _T_6399; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6401 = _T_6400 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6411 = _T_4675 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6412 = perr_ic_index_ff == 7'h37; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_6414 = _T_6412 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6415 = _T_6411 | _T_6414; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6416 = _T_6415 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6426 = _T_4676 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6427 = perr_ic_index_ff == 7'h38; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_6429 = _T_6427 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6430 = _T_6426 | _T_6429; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6431 = _T_6430 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6441 = _T_4677 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6442 = perr_ic_index_ff == 7'h39; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_6444 = _T_6442 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6445 = _T_6441 | _T_6444; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6446 = _T_6445 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6456 = _T_4678 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6457 = perr_ic_index_ff == 7'h3a; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_6459 = _T_6457 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6460 = _T_6456 | _T_6459; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6461 = _T_6460 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6471 = _T_4679 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6472 = perr_ic_index_ff == 7'h3b; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_6474 = _T_6472 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6475 = _T_6471 | _T_6474; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6476 = _T_6475 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6486 = _T_4680 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6487 = perr_ic_index_ff == 7'h3c; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_6489 = _T_6487 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6490 = _T_6486 | _T_6489; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6491 = _T_6490 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6501 = _T_4681 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6502 = perr_ic_index_ff == 7'h3d; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_6504 = _T_6502 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6505 = _T_6501 | _T_6504; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6506 = _T_6505 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6516 = _T_4682 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6517 = perr_ic_index_ff == 7'h3e; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_6519 = _T_6517 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6520 = _T_6516 | _T_6519; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6521 = _T_6520 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6531 = _T_4683 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6532 = perr_ic_index_ff == 7'h3f; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_6534 = _T_6532 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6535 = _T_6531 | _T_6534; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6536 = _T_6535 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6546 = _T_4652 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6549 = _T_6067 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6550 = _T_6546 | _T_6549; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6551 = _T_6550 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6561 = _T_4653 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6564 = _T_6082 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6565 = _T_6561 | _T_6564; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6566 = _T_6565 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6576 = _T_4654 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6579 = _T_6097 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6580 = _T_6576 | _T_6579; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6581 = _T_6580 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6591 = _T_4655 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6594 = _T_6112 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6595 = _T_6591 | _T_6594; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6596 = _T_6595 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6606 = _T_4656 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6609 = _T_6127 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6610 = _T_6606 | _T_6609; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6611 = _T_6610 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6621 = _T_4657 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6624 = _T_6142 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6625 = _T_6621 | _T_6624; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6626 = _T_6625 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6636 = _T_4658 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6639 = _T_6157 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6640 = _T_6636 | _T_6639; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6641 = _T_6640 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6651 = _T_4659 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6654 = _T_6172 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6655 = _T_6651 | _T_6654; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6656 = _T_6655 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6666 = _T_4660 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6669 = _T_6187 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6670 = _T_6666 | _T_6669; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6671 = _T_6670 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6681 = _T_4661 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6684 = _T_6202 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6685 = _T_6681 | _T_6684; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6686 = _T_6685 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6696 = _T_4662 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6699 = _T_6217 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6700 = _T_6696 | _T_6699; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6701 = _T_6700 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6711 = _T_4663 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6714 = _T_6232 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6715 = _T_6711 | _T_6714; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6716 = _T_6715 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6726 = _T_4664 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6729 = _T_6247 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6730 = _T_6726 | _T_6729; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6731 = _T_6730 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6741 = _T_4665 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6744 = _T_6262 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6745 = _T_6741 | _T_6744; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6746 = _T_6745 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6756 = _T_4666 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6759 = _T_6277 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6760 = _T_6756 | _T_6759; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6761 = _T_6760 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6771 = _T_4667 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6774 = _T_6292 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6775 = _T_6771 | _T_6774; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6776 = _T_6775 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6786 = _T_4668 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6789 = _T_6307 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6790 = _T_6786 | _T_6789; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6791 = _T_6790 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6801 = _T_4669 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6804 = _T_6322 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6805 = _T_6801 | _T_6804; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6806 = _T_6805 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6816 = _T_4670 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6819 = _T_6337 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6820 = _T_6816 | _T_6819; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6821 = _T_6820 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6831 = _T_4671 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6834 = _T_6352 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6835 = _T_6831 | _T_6834; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6836 = _T_6835 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6846 = _T_4672 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6849 = _T_6367 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6850 = _T_6846 | _T_6849; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6851 = _T_6850 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6861 = _T_4673 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6864 = _T_6382 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6865 = _T_6861 | _T_6864; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6866 = _T_6865 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6876 = _T_4674 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6879 = _T_6397 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6880 = _T_6876 | _T_6879; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6881 = _T_6880 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6891 = _T_4675 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6894 = _T_6412 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6895 = _T_6891 | _T_6894; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6896 = _T_6895 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6906 = _T_4676 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6909 = _T_6427 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6910 = _T_6906 | _T_6909; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6911 = _T_6910 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6921 = _T_4677 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6924 = _T_6442 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6925 = _T_6921 | _T_6924; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6926 = _T_6925 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6936 = _T_4678 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6939 = _T_6457 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6940 = _T_6936 | _T_6939; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6941 = _T_6940 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6951 = _T_4679 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6954 = _T_6472 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6955 = _T_6951 | _T_6954; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6956 = _T_6955 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6966 = _T_4680 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6969 = _T_6487 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6970 = _T_6966 | _T_6969; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6971 = _T_6970 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6981 = _T_4681 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6984 = _T_6502 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_6985 = _T_6981 | _T_6984; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_6986 = _T_6985 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_6996 = _T_4682 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_6999 = _T_6517 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7000 = _T_6996 | _T_6999; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7001 = _T_7000 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7011 = _T_4683 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7014 = _T_6532 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7015 = _T_7011 | _T_7014; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7016 = _T_7015 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7026 = _T_4684 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7027 = perr_ic_index_ff == 7'h40; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_7029 = _T_7027 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7030 = _T_7026 | _T_7029; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7031 = _T_7030 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7041 = _T_4685 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7042 = perr_ic_index_ff == 7'h41; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_7044 = _T_7042 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7045 = _T_7041 | _T_7044; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7046 = _T_7045 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7056 = _T_4686 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7057 = perr_ic_index_ff == 7'h42; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_7059 = _T_7057 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7060 = _T_7056 | _T_7059; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7061 = _T_7060 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7071 = _T_4687 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7072 = perr_ic_index_ff == 7'h43; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_7074 = _T_7072 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7075 = _T_7071 | _T_7074; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7076 = _T_7075 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7086 = _T_4688 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7087 = perr_ic_index_ff == 7'h44; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_7089 = _T_7087 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7090 = _T_7086 | _T_7089; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7091 = _T_7090 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7101 = _T_4689 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7102 = perr_ic_index_ff == 7'h45; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_7104 = _T_7102 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7105 = _T_7101 | _T_7104; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7106 = _T_7105 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7116 = _T_4690 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7117 = perr_ic_index_ff == 7'h46; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_7119 = _T_7117 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7120 = _T_7116 | _T_7119; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7121 = _T_7120 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7131 = _T_4691 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7132 = perr_ic_index_ff == 7'h47; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_7134 = _T_7132 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7135 = _T_7131 | _T_7134; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7136 = _T_7135 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7146 = _T_4692 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7147 = perr_ic_index_ff == 7'h48; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_7149 = _T_7147 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7150 = _T_7146 | _T_7149; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7151 = _T_7150 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7161 = _T_4693 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7162 = perr_ic_index_ff == 7'h49; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_7164 = _T_7162 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7165 = _T_7161 | _T_7164; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7166 = _T_7165 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7176 = _T_4694 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7177 = perr_ic_index_ff == 7'h4a; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_7179 = _T_7177 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7180 = _T_7176 | _T_7179; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7181 = _T_7180 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7191 = _T_4695 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7192 = perr_ic_index_ff == 7'h4b; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_7194 = _T_7192 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7195 = _T_7191 | _T_7194; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7196 = _T_7195 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7206 = _T_4696 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7207 = perr_ic_index_ff == 7'h4c; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_7209 = _T_7207 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7210 = _T_7206 | _T_7209; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7211 = _T_7210 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7221 = _T_4697 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7222 = perr_ic_index_ff == 7'h4d; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_7224 = _T_7222 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7225 = _T_7221 | _T_7224; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7226 = _T_7225 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7236 = _T_4698 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7237 = perr_ic_index_ff == 7'h4e; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_7239 = _T_7237 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7240 = _T_7236 | _T_7239; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7241 = _T_7240 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7251 = _T_4699 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7252 = perr_ic_index_ff == 7'h4f; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_7254 = _T_7252 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7255 = _T_7251 | _T_7254; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7256 = _T_7255 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7266 = _T_4700 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7267 = perr_ic_index_ff == 7'h50; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_7269 = _T_7267 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7270 = _T_7266 | _T_7269; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7271 = _T_7270 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7281 = _T_4701 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7282 = perr_ic_index_ff == 7'h51; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_7284 = _T_7282 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7285 = _T_7281 | _T_7284; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7286 = _T_7285 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7296 = _T_4702 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7297 = perr_ic_index_ff == 7'h52; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_7299 = _T_7297 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7300 = _T_7296 | _T_7299; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7301 = _T_7300 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7311 = _T_4703 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7312 = perr_ic_index_ff == 7'h53; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_7314 = _T_7312 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7315 = _T_7311 | _T_7314; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7316 = _T_7315 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7326 = _T_4704 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7327 = perr_ic_index_ff == 7'h54; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_7329 = _T_7327 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7330 = _T_7326 | _T_7329; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7331 = _T_7330 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7341 = _T_4705 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7342 = perr_ic_index_ff == 7'h55; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_7344 = _T_7342 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7345 = _T_7341 | _T_7344; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7346 = _T_7345 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7356 = _T_4706 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7357 = perr_ic_index_ff == 7'h56; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_7359 = _T_7357 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7360 = _T_7356 | _T_7359; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7361 = _T_7360 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7371 = _T_4707 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7372 = perr_ic_index_ff == 7'h57; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_7374 = _T_7372 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7375 = _T_7371 | _T_7374; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7376 = _T_7375 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7386 = _T_4708 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7387 = perr_ic_index_ff == 7'h58; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_7389 = _T_7387 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7390 = _T_7386 | _T_7389; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7391 = _T_7390 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7401 = _T_4709 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7402 = perr_ic_index_ff == 7'h59; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_7404 = _T_7402 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7405 = _T_7401 | _T_7404; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7406 = _T_7405 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7416 = _T_4710 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7417 = perr_ic_index_ff == 7'h5a; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_7419 = _T_7417 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7420 = _T_7416 | _T_7419; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7421 = _T_7420 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7431 = _T_4711 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7432 = perr_ic_index_ff == 7'h5b; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_7434 = _T_7432 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7435 = _T_7431 | _T_7434; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7436 = _T_7435 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7446 = _T_4712 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7447 = perr_ic_index_ff == 7'h5c; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_7449 = _T_7447 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7450 = _T_7446 | _T_7449; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7451 = _T_7450 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7461 = _T_4713 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7462 = perr_ic_index_ff == 7'h5d; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_7464 = _T_7462 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7465 = _T_7461 | _T_7464; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7466 = _T_7465 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7476 = _T_4714 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7477 = perr_ic_index_ff == 7'h5e; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_7479 = _T_7477 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7480 = _T_7476 | _T_7479; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7481 = _T_7480 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7491 = _T_4715 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7492 = perr_ic_index_ff == 7'h5f; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_7494 = _T_7492 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7495 = _T_7491 | _T_7494; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7496 = _T_7495 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7506 = _T_4684 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7509 = _T_7027 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7510 = _T_7506 | _T_7509; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7511 = _T_7510 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7521 = _T_4685 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7524 = _T_7042 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7525 = _T_7521 | _T_7524; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7526 = _T_7525 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7536 = _T_4686 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7539 = _T_7057 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7540 = _T_7536 | _T_7539; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7541 = _T_7540 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7551 = _T_4687 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7554 = _T_7072 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7555 = _T_7551 | _T_7554; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7556 = _T_7555 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7566 = _T_4688 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7569 = _T_7087 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7570 = _T_7566 | _T_7569; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7571 = _T_7570 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7581 = _T_4689 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7584 = _T_7102 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7585 = _T_7581 | _T_7584; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7586 = _T_7585 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7596 = _T_4690 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7599 = _T_7117 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7600 = _T_7596 | _T_7599; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7601 = _T_7600 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7611 = _T_4691 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7614 = _T_7132 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7615 = _T_7611 | _T_7614; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7616 = _T_7615 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7626 = _T_4692 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7629 = _T_7147 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7630 = _T_7626 | _T_7629; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7631 = _T_7630 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7641 = _T_4693 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7644 = _T_7162 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7645 = _T_7641 | _T_7644; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7646 = _T_7645 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7656 = _T_4694 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7659 = _T_7177 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7660 = _T_7656 | _T_7659; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7661 = _T_7660 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7671 = _T_4695 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7674 = _T_7192 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7675 = _T_7671 | _T_7674; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7676 = _T_7675 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7686 = _T_4696 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7689 = _T_7207 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7690 = _T_7686 | _T_7689; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7691 = _T_7690 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7701 = _T_4697 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7704 = _T_7222 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7705 = _T_7701 | _T_7704; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7706 = _T_7705 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7716 = _T_4698 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7719 = _T_7237 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7720 = _T_7716 | _T_7719; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7721 = _T_7720 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7731 = _T_4699 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7734 = _T_7252 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7735 = _T_7731 | _T_7734; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7736 = _T_7735 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7746 = _T_4700 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7749 = _T_7267 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7750 = _T_7746 | _T_7749; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7751 = _T_7750 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7761 = _T_4701 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7764 = _T_7282 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7765 = _T_7761 | _T_7764; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7766 = _T_7765 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7776 = _T_4702 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7779 = _T_7297 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7780 = _T_7776 | _T_7779; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7781 = _T_7780 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7791 = _T_4703 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7794 = _T_7312 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7795 = _T_7791 | _T_7794; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7796 = _T_7795 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7806 = _T_4704 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7809 = _T_7327 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7810 = _T_7806 | _T_7809; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7811 = _T_7810 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7821 = _T_4705 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7824 = _T_7342 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7825 = _T_7821 | _T_7824; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7826 = _T_7825 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7836 = _T_4706 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7839 = _T_7357 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7840 = _T_7836 | _T_7839; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7841 = _T_7840 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7851 = _T_4707 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7854 = _T_7372 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7855 = _T_7851 | _T_7854; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7856 = _T_7855 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7866 = _T_4708 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7869 = _T_7387 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7870 = _T_7866 | _T_7869; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7871 = _T_7870 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7881 = _T_4709 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7884 = _T_7402 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7885 = _T_7881 | _T_7884; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7886 = _T_7885 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7896 = _T_4710 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7899 = _T_7417 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7900 = _T_7896 | _T_7899; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7901 = _T_7900 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7911 = _T_4711 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7914 = _T_7432 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7915 = _T_7911 | _T_7914; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7916 = _T_7915 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7926 = _T_4712 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7929 = _T_7447 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7930 = _T_7926 | _T_7929; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7931 = _T_7930 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7941 = _T_4713 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7944 = _T_7462 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7945 = _T_7941 | _T_7944; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7946 = _T_7945 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7956 = _T_4714 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7959 = _T_7477 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7960 = _T_7956 | _T_7959; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7961 = _T_7960 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7971 = _T_4715 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7974 = _T_7492 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7975 = _T_7971 | _T_7974; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7976 = _T_7975 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_7986 = _T_4716 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_7987 = perr_ic_index_ff == 7'h60; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_7989 = _T_7987 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_7990 = _T_7986 | _T_7989; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_7991 = _T_7990 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8001 = _T_4717 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8002 = perr_ic_index_ff == 7'h61; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_8004 = _T_8002 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8005 = _T_8001 | _T_8004; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8006 = _T_8005 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8016 = _T_4718 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8017 = perr_ic_index_ff == 7'h62; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_8019 = _T_8017 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8020 = _T_8016 | _T_8019; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8021 = _T_8020 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8031 = _T_4719 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8032 = perr_ic_index_ff == 7'h63; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_8034 = _T_8032 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8035 = _T_8031 | _T_8034; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8036 = _T_8035 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8046 = _T_4720 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8047 = perr_ic_index_ff == 7'h64; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_8049 = _T_8047 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8050 = _T_8046 | _T_8049; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8051 = _T_8050 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8061 = _T_4721 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8062 = perr_ic_index_ff == 7'h65; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_8064 = _T_8062 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8065 = _T_8061 | _T_8064; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8066 = _T_8065 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8076 = _T_4722 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8077 = perr_ic_index_ff == 7'h66; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_8079 = _T_8077 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8080 = _T_8076 | _T_8079; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8081 = _T_8080 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8091 = _T_4723 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8092 = perr_ic_index_ff == 7'h67; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_8094 = _T_8092 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8095 = _T_8091 | _T_8094; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8096 = _T_8095 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8106 = _T_4724 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8107 = perr_ic_index_ff == 7'h68; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_8109 = _T_8107 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8110 = _T_8106 | _T_8109; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8111 = _T_8110 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8121 = _T_4725 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8122 = perr_ic_index_ff == 7'h69; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_8124 = _T_8122 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8125 = _T_8121 | _T_8124; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8126 = _T_8125 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8136 = _T_4726 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8137 = perr_ic_index_ff == 7'h6a; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_8139 = _T_8137 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8140 = _T_8136 | _T_8139; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8141 = _T_8140 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8151 = _T_4727 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8152 = perr_ic_index_ff == 7'h6b; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_8154 = _T_8152 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8155 = _T_8151 | _T_8154; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8156 = _T_8155 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8166 = _T_4728 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8167 = perr_ic_index_ff == 7'h6c; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_8169 = _T_8167 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8170 = _T_8166 | _T_8169; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8171 = _T_8170 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8181 = _T_4729 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8182 = perr_ic_index_ff == 7'h6d; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_8184 = _T_8182 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8185 = _T_8181 | _T_8184; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8186 = _T_8185 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8196 = _T_4730 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8197 = perr_ic_index_ff == 7'h6e; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_8199 = _T_8197 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8200 = _T_8196 | _T_8199; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8201 = _T_8200 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8211 = _T_4731 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8212 = perr_ic_index_ff == 7'h6f; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_8214 = _T_8212 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8215 = _T_8211 | _T_8214; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8216 = _T_8215 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8226 = _T_4732 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8227 = perr_ic_index_ff == 7'h70; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_8229 = _T_8227 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8230 = _T_8226 | _T_8229; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8231 = _T_8230 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8241 = _T_4733 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8242 = perr_ic_index_ff == 7'h71; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_8244 = _T_8242 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8245 = _T_8241 | _T_8244; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8246 = _T_8245 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8256 = _T_4734 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8257 = perr_ic_index_ff == 7'h72; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_8259 = _T_8257 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8260 = _T_8256 | _T_8259; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8261 = _T_8260 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8271 = _T_4735 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8272 = perr_ic_index_ff == 7'h73; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_8274 = _T_8272 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8275 = _T_8271 | _T_8274; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8276 = _T_8275 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8286 = _T_4736 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8287 = perr_ic_index_ff == 7'h74; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_8289 = _T_8287 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8290 = _T_8286 | _T_8289; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8291 = _T_8290 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8301 = _T_4737 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8302 = perr_ic_index_ff == 7'h75; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_8304 = _T_8302 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8305 = _T_8301 | _T_8304; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8306 = _T_8305 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8316 = _T_4738 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8317 = perr_ic_index_ff == 7'h76; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_8319 = _T_8317 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8320 = _T_8316 | _T_8319; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8321 = _T_8320 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8331 = _T_4739 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8332 = perr_ic_index_ff == 7'h77; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_8334 = _T_8332 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8335 = _T_8331 | _T_8334; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8336 = _T_8335 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8346 = _T_4740 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8347 = perr_ic_index_ff == 7'h78; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_8349 = _T_8347 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8350 = _T_8346 | _T_8349; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8351 = _T_8350 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8361 = _T_4741 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8362 = perr_ic_index_ff == 7'h79; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_8364 = _T_8362 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8365 = _T_8361 | _T_8364; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8366 = _T_8365 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8376 = _T_4742 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8377 = perr_ic_index_ff == 7'h7a; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_8379 = _T_8377 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8380 = _T_8376 | _T_8379; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8381 = _T_8380 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8391 = _T_4743 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8392 = perr_ic_index_ff == 7'h7b; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_8394 = _T_8392 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8395 = _T_8391 | _T_8394; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8396 = _T_8395 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8406 = _T_4744 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8407 = perr_ic_index_ff == 7'h7c; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_8409 = _T_8407 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8410 = _T_8406 | _T_8409; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8411 = _T_8410 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8421 = _T_4745 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8422 = perr_ic_index_ff == 7'h7d; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_8424 = _T_8422 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8425 = _T_8421 | _T_8424; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8426 = _T_8425 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8436 = _T_4746 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8437 = perr_ic_index_ff == 7'h7e; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_8439 = _T_8437 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8440 = _T_8436 | _T_8439; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8441 = _T_8440 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8451 = _T_4747 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8452 = perr_ic_index_ff == 7'h7f; // @[el2_ifu_mem_ctl.scala 761:98] + wire _T_8454 = _T_8452 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8455 = _T_8451 | _T_8454; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8456 = _T_8455 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8466 = _T_4716 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8469 = _T_7987 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8470 = _T_8466 | _T_8469; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8471 = _T_8470 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8481 = _T_4717 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8484 = _T_8002 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8485 = _T_8481 | _T_8484; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8486 = _T_8485 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8496 = _T_4718 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8499 = _T_8017 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8500 = _T_8496 | _T_8499; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8501 = _T_8500 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8511 = _T_4719 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8514 = _T_8032 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8515 = _T_8511 | _T_8514; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8516 = _T_8515 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8526 = _T_4720 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8529 = _T_8047 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8530 = _T_8526 | _T_8529; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8531 = _T_8530 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8541 = _T_4721 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8544 = _T_8062 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8545 = _T_8541 | _T_8544; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8546 = _T_8545 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8556 = _T_4722 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8559 = _T_8077 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8560 = _T_8556 | _T_8559; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8561 = _T_8560 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8571 = _T_4723 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8574 = _T_8092 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8575 = _T_8571 | _T_8574; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8576 = _T_8575 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8586 = _T_4724 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8589 = _T_8107 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8590 = _T_8586 | _T_8589; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8591 = _T_8590 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8601 = _T_4725 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8604 = _T_8122 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8605 = _T_8601 | _T_8604; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8606 = _T_8605 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8616 = _T_4726 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8619 = _T_8137 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8620 = _T_8616 | _T_8619; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8621 = _T_8620 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8631 = _T_4727 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8634 = _T_8152 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8635 = _T_8631 | _T_8634; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8636 = _T_8635 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8646 = _T_4728 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8649 = _T_8167 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8650 = _T_8646 | _T_8649; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8651 = _T_8650 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8661 = _T_4729 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8664 = _T_8182 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8665 = _T_8661 | _T_8664; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8666 = _T_8665 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8676 = _T_4730 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8679 = _T_8197 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8680 = _T_8676 | _T_8679; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8681 = _T_8680 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8691 = _T_4731 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8694 = _T_8212 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8695 = _T_8691 | _T_8694; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8696 = _T_8695 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8706 = _T_4732 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8709 = _T_8227 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8710 = _T_8706 | _T_8709; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8711 = _T_8710 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8721 = _T_4733 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8724 = _T_8242 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8725 = _T_8721 | _T_8724; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8726 = _T_8725 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8736 = _T_4734 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8739 = _T_8257 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8740 = _T_8736 | _T_8739; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8741 = _T_8740 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8751 = _T_4735 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8754 = _T_8272 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8755 = _T_8751 | _T_8754; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8756 = _T_8755 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8766 = _T_4736 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8769 = _T_8287 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8770 = _T_8766 | _T_8769; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8771 = _T_8770 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8781 = _T_4737 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8784 = _T_8302 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8785 = _T_8781 | _T_8784; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8786 = _T_8785 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8796 = _T_4738 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8799 = _T_8317 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8800 = _T_8796 | _T_8799; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8801 = _T_8800 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8811 = _T_4739 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8814 = _T_8332 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8815 = _T_8811 | _T_8814; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8816 = _T_8815 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8826 = _T_4740 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8829 = _T_8347 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8830 = _T_8826 | _T_8829; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8831 = _T_8830 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8841 = _T_4741 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8844 = _T_8362 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8845 = _T_8841 | _T_8844; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8846 = _T_8845 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8856 = _T_4742 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8859 = _T_8377 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8860 = _T_8856 | _T_8859; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8861 = _T_8860 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8871 = _T_4743 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8874 = _T_8392 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8875 = _T_8871 | _T_8874; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8876 = _T_8875 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8886 = _T_4744 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8889 = _T_8407 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8890 = _T_8886 | _T_8889; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8891 = _T_8890 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8901 = _T_4745 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8904 = _T_8422 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8905 = _T_8901 | _T_8904; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8906 = _T_8905 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8916 = _T_4746 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8919 = _T_8437 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8920 = _T_8916 | _T_8919; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8921 = _T_8920 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_8931 = _T_4747 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 761:55] + wire _T_8934 = _T_8452 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 761:120] + wire _T_8935 = _T_8931 | _T_8934; // @[el2_ifu_mem_ctl.scala 761:77] + wire _T_8936 = _T_8935 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 761:143] + wire _T_9738 = ~fetch_uncacheable_ff; // @[el2_ifu_mem_ctl.scala 816:63] + wire _T_9739 = _T_9738 & ifc_fetch_req_f; // @[el2_ifu_mem_ctl.scala 816:85] + wire [1:0] _T_9741 = _T_9739 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + reg _T_9748; // @[el2_ifu_mem_ctl.scala 821:57] + reg _T_9749; // @[el2_ifu_mem_ctl.scala 822:56] + reg _T_9750; // @[el2_ifu_mem_ctl.scala 823:59] + wire _T_9751 = ~ifu_bus_arready_ff; // @[el2_ifu_mem_ctl.scala 824:80] + wire _T_9752 = ifu_bus_arvalid_ff & _T_9751; // @[el2_ifu_mem_ctl.scala 824:78] + reg _T_9754; // @[el2_ifu_mem_ctl.scala 824:58] + reg _T_9755; // @[el2_ifu_mem_ctl.scala 825:58] + wire _T_9758 = io_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h3; // @[el2_ifu_mem_ctl.scala 832:71] + wire _T_9760 = io_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h2; // @[el2_ifu_mem_ctl.scala 832:124] + wire _T_9762 = io_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h1; // @[el2_ifu_mem_ctl.scala 833:50] + wire _T_9764 = io_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h0; // @[el2_ifu_mem_ctl.scala 833:103] + wire [3:0] _T_9767 = {_T_9758,_T_9760,_T_9762,_T_9764}; // @[Cat.scala 29:58] + reg _T_9776; // @[Reg.scala 27:20] + wire [31:0] _T_9786 = {io_ifc_fetch_addr_bf,1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_9787 = _T_9786 | 32'h7fffffff; // @[el2_ifu_mem_ctl.scala 841:63] + wire _T_9789 = _T_9787 == 32'h7fffffff; // @[el2_ifu_mem_ctl.scala 841:94] + wire [31:0] _T_9793 = _T_9786 | 32'h3fffffff; // @[el2_ifu_mem_ctl.scala 842:63] + wire _T_9795 = _T_9793 == 32'hffffffff; // @[el2_ifu_mem_ctl.scala 842:94] + wire _T_9797 = _T_9789 | _T_9795; // @[el2_ifu_mem_ctl.scala 841:160] + wire [31:0] _T_9799 = _T_9786 | 32'h1fffffff; // @[el2_ifu_mem_ctl.scala 843:63] + wire _T_9801 = _T_9799 == 32'hbfffffff; // @[el2_ifu_mem_ctl.scala 843:94] + wire _T_9803 = _T_9797 | _T_9801; // @[el2_ifu_mem_ctl.scala 842:160] + wire [31:0] _T_9805 = _T_9786 | 32'hfffffff; // @[el2_ifu_mem_ctl.scala 844:63] + wire _T_9807 = _T_9805 == 32'h8fffffff; // @[el2_ifu_mem_ctl.scala 844:94] + wire ifc_region_acc_okay = _T_9803 | _T_9807; // @[el2_ifu_mem_ctl.scala 843:160] + wire _T_9834 = ~ifc_region_acc_okay; // @[el2_ifu_mem_ctl.scala 849:65] + wire _T_9835 = _T_3888 & _T_9834; // @[el2_ifu_mem_ctl.scala 849:63] + wire ifc_region_acc_fault_memory_bf = _T_9835 & io_ifc_fetch_req_bf; // @[el2_ifu_mem_ctl.scala 849:86] + rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_io_l1clk), + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en), + .io_scan_mode(rvclkhdr_io_scan_mode) + ); + rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_1_io_l1clk), + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en), + .io_scan_mode(rvclkhdr_1_io_scan_mode) + ); + rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_2_io_l1clk), + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en), + .io_scan_mode(rvclkhdr_2_io_scan_mode) + ); + rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_3_io_l1clk), + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en), + .io_scan_mode(rvclkhdr_3_io_scan_mode) + ); + rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_4_io_l1clk), + .io_clk(rvclkhdr_4_io_clk), + .io_en(rvclkhdr_4_io_en), + .io_scan_mode(rvclkhdr_4_io_scan_mode) + ); + rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_5_io_l1clk), + .io_clk(rvclkhdr_5_io_clk), + .io_en(rvclkhdr_5_io_en), + .io_scan_mode(rvclkhdr_5_io_scan_mode) + ); + rvclkhdr rvclkhdr_6 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_6_io_l1clk), + .io_clk(rvclkhdr_6_io_clk), + .io_en(rvclkhdr_6_io_en), + .io_scan_mode(rvclkhdr_6_io_scan_mode) + ); + rvclkhdr rvclkhdr_7 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_7_io_l1clk), + .io_clk(rvclkhdr_7_io_clk), + .io_en(rvclkhdr_7_io_en), + .io_scan_mode(rvclkhdr_7_io_scan_mode) + ); + rvclkhdr rvclkhdr_8 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_8_io_l1clk), + .io_clk(rvclkhdr_8_io_clk), + .io_en(rvclkhdr_8_io_en), + .io_scan_mode(rvclkhdr_8_io_scan_mode) + ); + rvclkhdr rvclkhdr_9 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_9_io_l1clk), + .io_clk(rvclkhdr_9_io_clk), + .io_en(rvclkhdr_9_io_en), + .io_scan_mode(rvclkhdr_9_io_scan_mode) + ); + rvclkhdr rvclkhdr_10 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_10_io_l1clk), + .io_clk(rvclkhdr_10_io_clk), + .io_en(rvclkhdr_10_io_en), + .io_scan_mode(rvclkhdr_10_io_scan_mode) + ); + rvclkhdr rvclkhdr_11 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_11_io_l1clk), + .io_clk(rvclkhdr_11_io_clk), + .io_en(rvclkhdr_11_io_en), + .io_scan_mode(rvclkhdr_11_io_scan_mode) + ); + rvclkhdr rvclkhdr_12 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_12_io_l1clk), + .io_clk(rvclkhdr_12_io_clk), + .io_en(rvclkhdr_12_io_en), + .io_scan_mode(rvclkhdr_12_io_scan_mode) + ); + rvclkhdr rvclkhdr_13 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_13_io_l1clk), + .io_clk(rvclkhdr_13_io_clk), + .io_en(rvclkhdr_13_io_en), + .io_scan_mode(rvclkhdr_13_io_scan_mode) + ); + rvclkhdr rvclkhdr_14 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_14_io_l1clk), + .io_clk(rvclkhdr_14_io_clk), + .io_en(rvclkhdr_14_io_en), + .io_scan_mode(rvclkhdr_14_io_scan_mode) + ); + rvclkhdr rvclkhdr_15 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_15_io_l1clk), + .io_clk(rvclkhdr_15_io_clk), + .io_en(rvclkhdr_15_io_en), + .io_scan_mode(rvclkhdr_15_io_scan_mode) + ); + rvclkhdr rvclkhdr_16 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_16_io_l1clk), + .io_clk(rvclkhdr_16_io_clk), + .io_en(rvclkhdr_16_io_en), + .io_scan_mode(rvclkhdr_16_io_scan_mode) + ); + rvclkhdr rvclkhdr_17 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_17_io_l1clk), + .io_clk(rvclkhdr_17_io_clk), + .io_en(rvclkhdr_17_io_en), + .io_scan_mode(rvclkhdr_17_io_scan_mode) + ); + rvclkhdr rvclkhdr_18 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_18_io_l1clk), + .io_clk(rvclkhdr_18_io_clk), + .io_en(rvclkhdr_18_io_en), + .io_scan_mode(rvclkhdr_18_io_scan_mode) + ); + rvclkhdr rvclkhdr_19 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_19_io_l1clk), + .io_clk(rvclkhdr_19_io_clk), + .io_en(rvclkhdr_19_io_en), + .io_scan_mode(rvclkhdr_19_io_scan_mode) + ); + rvclkhdr rvclkhdr_20 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_20_io_l1clk), + .io_clk(rvclkhdr_20_io_clk), + .io_en(rvclkhdr_20_io_en), + .io_scan_mode(rvclkhdr_20_io_scan_mode) + ); + rvclkhdr rvclkhdr_21 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_21_io_l1clk), + .io_clk(rvclkhdr_21_io_clk), + .io_en(rvclkhdr_21_io_en), + .io_scan_mode(rvclkhdr_21_io_scan_mode) + ); + rvclkhdr rvclkhdr_22 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_22_io_l1clk), + .io_clk(rvclkhdr_22_io_clk), + .io_en(rvclkhdr_22_io_en), + .io_scan_mode(rvclkhdr_22_io_scan_mode) + ); + rvclkhdr rvclkhdr_23 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_23_io_l1clk), + .io_clk(rvclkhdr_23_io_clk), + .io_en(rvclkhdr_23_io_en), + .io_scan_mode(rvclkhdr_23_io_scan_mode) + ); + rvclkhdr rvclkhdr_24 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_24_io_l1clk), + .io_clk(rvclkhdr_24_io_clk), + .io_en(rvclkhdr_24_io_en), + .io_scan_mode(rvclkhdr_24_io_scan_mode) + ); + rvclkhdr rvclkhdr_25 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_25_io_l1clk), + .io_clk(rvclkhdr_25_io_clk), + .io_en(rvclkhdr_25_io_en), + .io_scan_mode(rvclkhdr_25_io_scan_mode) + ); + rvclkhdr rvclkhdr_26 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_26_io_l1clk), + .io_clk(rvclkhdr_26_io_clk), + .io_en(rvclkhdr_26_io_en), + .io_scan_mode(rvclkhdr_26_io_scan_mode) + ); + rvclkhdr rvclkhdr_27 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_27_io_l1clk), + .io_clk(rvclkhdr_27_io_clk), + .io_en(rvclkhdr_27_io_en), + .io_scan_mode(rvclkhdr_27_io_scan_mode) + ); + rvclkhdr rvclkhdr_28 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_28_io_l1clk), + .io_clk(rvclkhdr_28_io_clk), + .io_en(rvclkhdr_28_io_en), + .io_scan_mode(rvclkhdr_28_io_scan_mode) + ); + rvclkhdr rvclkhdr_29 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_29_io_l1clk), + .io_clk(rvclkhdr_29_io_clk), + .io_en(rvclkhdr_29_io_en), + .io_scan_mode(rvclkhdr_29_io_scan_mode) + ); + rvclkhdr rvclkhdr_30 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_30_io_l1clk), + .io_clk(rvclkhdr_30_io_clk), + .io_en(rvclkhdr_30_io_en), + .io_scan_mode(rvclkhdr_30_io_scan_mode) + ); + rvclkhdr rvclkhdr_31 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_31_io_l1clk), + .io_clk(rvclkhdr_31_io_clk), + .io_en(rvclkhdr_31_io_en), + .io_scan_mode(rvclkhdr_31_io_scan_mode) + ); + rvclkhdr rvclkhdr_32 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_32_io_l1clk), + .io_clk(rvclkhdr_32_io_clk), + .io_en(rvclkhdr_32_io_en), + .io_scan_mode(rvclkhdr_32_io_scan_mode) + ); + rvclkhdr rvclkhdr_33 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_33_io_l1clk), + .io_clk(rvclkhdr_33_io_clk), + .io_en(rvclkhdr_33_io_en), + .io_scan_mode(rvclkhdr_33_io_scan_mode) + ); + rvclkhdr rvclkhdr_34 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_34_io_l1clk), + .io_clk(rvclkhdr_34_io_clk), + .io_en(rvclkhdr_34_io_en), + .io_scan_mode(rvclkhdr_34_io_scan_mode) + ); + rvclkhdr rvclkhdr_35 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_35_io_l1clk), + .io_clk(rvclkhdr_35_io_clk), + .io_en(rvclkhdr_35_io_en), + .io_scan_mode(rvclkhdr_35_io_scan_mode) + ); + rvclkhdr rvclkhdr_36 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_36_io_l1clk), + .io_clk(rvclkhdr_36_io_clk), + .io_en(rvclkhdr_36_io_en), + .io_scan_mode(rvclkhdr_36_io_scan_mode) + ); + rvclkhdr rvclkhdr_37 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_37_io_l1clk), + .io_clk(rvclkhdr_37_io_clk), + .io_en(rvclkhdr_37_io_en), + .io_scan_mode(rvclkhdr_37_io_scan_mode) + ); + rvclkhdr rvclkhdr_38 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_38_io_l1clk), + .io_clk(rvclkhdr_38_io_clk), + .io_en(rvclkhdr_38_io_en), + .io_scan_mode(rvclkhdr_38_io_scan_mode) + ); + rvclkhdr rvclkhdr_39 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_39_io_l1clk), + .io_clk(rvclkhdr_39_io_clk), + .io_en(rvclkhdr_39_io_en), + .io_scan_mode(rvclkhdr_39_io_scan_mode) + ); + rvclkhdr rvclkhdr_40 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_40_io_l1clk), + .io_clk(rvclkhdr_40_io_clk), + .io_en(rvclkhdr_40_io_en), + .io_scan_mode(rvclkhdr_40_io_scan_mode) + ); + rvclkhdr rvclkhdr_41 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_41_io_l1clk), + .io_clk(rvclkhdr_41_io_clk), + .io_en(rvclkhdr_41_io_en), + .io_scan_mode(rvclkhdr_41_io_scan_mode) + ); + rvclkhdr rvclkhdr_42 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_42_io_l1clk), + .io_clk(rvclkhdr_42_io_clk), + .io_en(rvclkhdr_42_io_en), + .io_scan_mode(rvclkhdr_42_io_scan_mode) + ); + rvclkhdr rvclkhdr_43 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_43_io_l1clk), + .io_clk(rvclkhdr_43_io_clk), + .io_en(rvclkhdr_43_io_en), + .io_scan_mode(rvclkhdr_43_io_scan_mode) + ); + rvclkhdr rvclkhdr_44 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_44_io_l1clk), + .io_clk(rvclkhdr_44_io_clk), + .io_en(rvclkhdr_44_io_en), + .io_scan_mode(rvclkhdr_44_io_scan_mode) + ); + rvclkhdr rvclkhdr_45 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_45_io_l1clk), + .io_clk(rvclkhdr_45_io_clk), + .io_en(rvclkhdr_45_io_en), + .io_scan_mode(rvclkhdr_45_io_scan_mode) + ); + rvclkhdr rvclkhdr_46 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_46_io_l1clk), + .io_clk(rvclkhdr_46_io_clk), + .io_en(rvclkhdr_46_io_en), + .io_scan_mode(rvclkhdr_46_io_scan_mode) + ); + rvclkhdr rvclkhdr_47 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_47_io_l1clk), + .io_clk(rvclkhdr_47_io_clk), + .io_en(rvclkhdr_47_io_en), + .io_scan_mode(rvclkhdr_47_io_scan_mode) + ); + rvclkhdr rvclkhdr_48 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_48_io_l1clk), + .io_clk(rvclkhdr_48_io_clk), + .io_en(rvclkhdr_48_io_en), + .io_scan_mode(rvclkhdr_48_io_scan_mode) + ); + rvclkhdr rvclkhdr_49 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_49_io_l1clk), + .io_clk(rvclkhdr_49_io_clk), + .io_en(rvclkhdr_49_io_en), + .io_scan_mode(rvclkhdr_49_io_scan_mode) + ); + rvclkhdr rvclkhdr_50 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_50_io_l1clk), + .io_clk(rvclkhdr_50_io_clk), + .io_en(rvclkhdr_50_io_en), + .io_scan_mode(rvclkhdr_50_io_scan_mode) + ); + rvclkhdr rvclkhdr_51 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_51_io_l1clk), + .io_clk(rvclkhdr_51_io_clk), + .io_en(rvclkhdr_51_io_en), + .io_scan_mode(rvclkhdr_51_io_scan_mode) + ); + rvclkhdr rvclkhdr_52 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_52_io_l1clk), + .io_clk(rvclkhdr_52_io_clk), + .io_en(rvclkhdr_52_io_en), + .io_scan_mode(rvclkhdr_52_io_scan_mode) + ); + rvclkhdr rvclkhdr_53 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_53_io_l1clk), + .io_clk(rvclkhdr_53_io_clk), + .io_en(rvclkhdr_53_io_en), + .io_scan_mode(rvclkhdr_53_io_scan_mode) + ); + rvclkhdr rvclkhdr_54 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_54_io_l1clk), + .io_clk(rvclkhdr_54_io_clk), + .io_en(rvclkhdr_54_io_en), + .io_scan_mode(rvclkhdr_54_io_scan_mode) + ); + rvclkhdr rvclkhdr_55 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_55_io_l1clk), + .io_clk(rvclkhdr_55_io_clk), + .io_en(rvclkhdr_55_io_en), + .io_scan_mode(rvclkhdr_55_io_scan_mode) + ); + rvclkhdr rvclkhdr_56 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_56_io_l1clk), + .io_clk(rvclkhdr_56_io_clk), + .io_en(rvclkhdr_56_io_en), + .io_scan_mode(rvclkhdr_56_io_scan_mode) + ); + rvclkhdr rvclkhdr_57 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_57_io_l1clk), + .io_clk(rvclkhdr_57_io_clk), + .io_en(rvclkhdr_57_io_en), + .io_scan_mode(rvclkhdr_57_io_scan_mode) + ); + rvclkhdr rvclkhdr_58 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_58_io_l1clk), + .io_clk(rvclkhdr_58_io_clk), + .io_en(rvclkhdr_58_io_en), + .io_scan_mode(rvclkhdr_58_io_scan_mode) + ); + rvclkhdr rvclkhdr_59 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_59_io_l1clk), + .io_clk(rvclkhdr_59_io_clk), + .io_en(rvclkhdr_59_io_en), + .io_scan_mode(rvclkhdr_59_io_scan_mode) + ); + rvclkhdr rvclkhdr_60 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_60_io_l1clk), + .io_clk(rvclkhdr_60_io_clk), + .io_en(rvclkhdr_60_io_en), + .io_scan_mode(rvclkhdr_60_io_scan_mode) + ); + rvclkhdr rvclkhdr_61 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_61_io_l1clk), + .io_clk(rvclkhdr_61_io_clk), + .io_en(rvclkhdr_61_io_en), + .io_scan_mode(rvclkhdr_61_io_scan_mode) + ); + rvclkhdr rvclkhdr_62 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_62_io_l1clk), + .io_clk(rvclkhdr_62_io_clk), + .io_en(rvclkhdr_62_io_en), + .io_scan_mode(rvclkhdr_62_io_scan_mode) + ); + rvclkhdr rvclkhdr_63 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_63_io_l1clk), + .io_clk(rvclkhdr_63_io_clk), + .io_en(rvclkhdr_63_io_en), + .io_scan_mode(rvclkhdr_63_io_scan_mode) + ); + rvclkhdr rvclkhdr_64 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_64_io_l1clk), + .io_clk(rvclkhdr_64_io_clk), + .io_en(rvclkhdr_64_io_en), + .io_scan_mode(rvclkhdr_64_io_scan_mode) + ); + rvclkhdr rvclkhdr_65 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_65_io_l1clk), + .io_clk(rvclkhdr_65_io_clk), + .io_en(rvclkhdr_65_io_en), + .io_scan_mode(rvclkhdr_65_io_scan_mode) + ); + rvclkhdr rvclkhdr_66 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_66_io_l1clk), + .io_clk(rvclkhdr_66_io_clk), + .io_en(rvclkhdr_66_io_en), + .io_scan_mode(rvclkhdr_66_io_scan_mode) + ); + rvclkhdr rvclkhdr_67 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_67_io_l1clk), + .io_clk(rvclkhdr_67_io_clk), + .io_en(rvclkhdr_67_io_en), + .io_scan_mode(rvclkhdr_67_io_scan_mode) + ); + rvclkhdr rvclkhdr_68 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_68_io_l1clk), + .io_clk(rvclkhdr_68_io_clk), + .io_en(rvclkhdr_68_io_en), + .io_scan_mode(rvclkhdr_68_io_scan_mode) + ); + rvclkhdr rvclkhdr_69 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_69_io_l1clk), + .io_clk(rvclkhdr_69_io_clk), + .io_en(rvclkhdr_69_io_en), + .io_scan_mode(rvclkhdr_69_io_scan_mode) + ); + rvclkhdr rvclkhdr_70 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_70_io_l1clk), + .io_clk(rvclkhdr_70_io_clk), + .io_en(rvclkhdr_70_io_en), + .io_scan_mode(rvclkhdr_70_io_scan_mode) + ); + rvclkhdr rvclkhdr_71 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_71_io_l1clk), + .io_clk(rvclkhdr_71_io_clk), + .io_en(rvclkhdr_71_io_en), + .io_scan_mode(rvclkhdr_71_io_scan_mode) + ); + rvclkhdr rvclkhdr_72 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_72_io_l1clk), + .io_clk(rvclkhdr_72_io_clk), + .io_en(rvclkhdr_72_io_en), + .io_scan_mode(rvclkhdr_72_io_scan_mode) + ); + rvclkhdr rvclkhdr_73 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_73_io_l1clk), + .io_clk(rvclkhdr_73_io_clk), + .io_en(rvclkhdr_73_io_en), + .io_scan_mode(rvclkhdr_73_io_scan_mode) + ); + rvclkhdr rvclkhdr_74 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_74_io_l1clk), + .io_clk(rvclkhdr_74_io_clk), + .io_en(rvclkhdr_74_io_en), + .io_scan_mode(rvclkhdr_74_io_scan_mode) + ); + rvclkhdr rvclkhdr_75 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_75_io_l1clk), + .io_clk(rvclkhdr_75_io_clk), + .io_en(rvclkhdr_75_io_en), + .io_scan_mode(rvclkhdr_75_io_scan_mode) + ); + rvclkhdr rvclkhdr_76 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_76_io_l1clk), + .io_clk(rvclkhdr_76_io_clk), + .io_en(rvclkhdr_76_io_en), + .io_scan_mode(rvclkhdr_76_io_scan_mode) + ); + rvclkhdr rvclkhdr_77 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_77_io_l1clk), + .io_clk(rvclkhdr_77_io_clk), + .io_en(rvclkhdr_77_io_en), + .io_scan_mode(rvclkhdr_77_io_scan_mode) + ); + rvclkhdr rvclkhdr_78 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_78_io_l1clk), + .io_clk(rvclkhdr_78_io_clk), + .io_en(rvclkhdr_78_io_en), + .io_scan_mode(rvclkhdr_78_io_scan_mode) + ); + rvclkhdr rvclkhdr_79 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_79_io_l1clk), + .io_clk(rvclkhdr_79_io_clk), + .io_en(rvclkhdr_79_io_en), + .io_scan_mode(rvclkhdr_79_io_scan_mode) + ); + rvclkhdr rvclkhdr_80 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_80_io_l1clk), + .io_clk(rvclkhdr_80_io_clk), + .io_en(rvclkhdr_80_io_en), + .io_scan_mode(rvclkhdr_80_io_scan_mode) + ); + rvclkhdr rvclkhdr_81 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_81_io_l1clk), + .io_clk(rvclkhdr_81_io_clk), + .io_en(rvclkhdr_81_io_en), + .io_scan_mode(rvclkhdr_81_io_scan_mode) + ); + rvclkhdr rvclkhdr_82 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_82_io_l1clk), + .io_clk(rvclkhdr_82_io_clk), + .io_en(rvclkhdr_82_io_en), + .io_scan_mode(rvclkhdr_82_io_scan_mode) + ); + rvclkhdr rvclkhdr_83 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_83_io_l1clk), + .io_clk(rvclkhdr_83_io_clk), + .io_en(rvclkhdr_83_io_en), + .io_scan_mode(rvclkhdr_83_io_scan_mode) + ); + rvclkhdr rvclkhdr_84 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_84_io_l1clk), + .io_clk(rvclkhdr_84_io_clk), + .io_en(rvclkhdr_84_io_en), + .io_scan_mode(rvclkhdr_84_io_scan_mode) + ); + rvclkhdr rvclkhdr_85 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_85_io_l1clk), + .io_clk(rvclkhdr_85_io_clk), + .io_en(rvclkhdr_85_io_en), + .io_scan_mode(rvclkhdr_85_io_scan_mode) + ); + rvclkhdr rvclkhdr_86 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_86_io_l1clk), + .io_clk(rvclkhdr_86_io_clk), + .io_en(rvclkhdr_86_io_en), + .io_scan_mode(rvclkhdr_86_io_scan_mode) + ); + rvclkhdr rvclkhdr_87 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_87_io_l1clk), + .io_clk(rvclkhdr_87_io_clk), + .io_en(rvclkhdr_87_io_en), + .io_scan_mode(rvclkhdr_87_io_scan_mode) + ); + rvclkhdr rvclkhdr_88 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_88_io_l1clk), + .io_clk(rvclkhdr_88_io_clk), + .io_en(rvclkhdr_88_io_en), + .io_scan_mode(rvclkhdr_88_io_scan_mode) + ); + rvclkhdr rvclkhdr_89 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_89_io_l1clk), + .io_clk(rvclkhdr_89_io_clk), + .io_en(rvclkhdr_89_io_en), + .io_scan_mode(rvclkhdr_89_io_scan_mode) + ); + rvclkhdr rvclkhdr_90 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_90_io_l1clk), + .io_clk(rvclkhdr_90_io_clk), + .io_en(rvclkhdr_90_io_en), + .io_scan_mode(rvclkhdr_90_io_scan_mode) + ); + rvclkhdr rvclkhdr_91 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_91_io_l1clk), + .io_clk(rvclkhdr_91_io_clk), + .io_en(rvclkhdr_91_io_en), + .io_scan_mode(rvclkhdr_91_io_scan_mode) + ); + rvclkhdr rvclkhdr_92 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_92_io_l1clk), + .io_clk(rvclkhdr_92_io_clk), + .io_en(rvclkhdr_92_io_en), + .io_scan_mode(rvclkhdr_92_io_scan_mode) + ); + rvclkhdr rvclkhdr_93 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_93_io_l1clk), + .io_clk(rvclkhdr_93_io_clk), + .io_en(rvclkhdr_93_io_en), + .io_scan_mode(rvclkhdr_93_io_scan_mode) + ); + assign io_ifu_miss_state_idle = miss_state == 3'h0; // @[el2_ifu_mem_ctl.scala 330:26] + assign io_ifu_ic_mb_empty = _T_328 | _T_231; // @[el2_ifu_mem_ctl.scala 329:22] + assign io_ic_dma_active = _T_11 | io_dec_tlu_flush_err_wb; // @[el2_ifu_mem_ctl.scala 193:20] + assign io_ic_write_stall = write_ic_16_bytes & _T_3937; // @[el2_ifu_mem_ctl.scala 704:21] + assign io_ifu_pmu_ic_miss = _T_9748; // @[el2_ifu_mem_ctl.scala 821:22] + assign io_ifu_pmu_ic_hit = _T_9749; // @[el2_ifu_mem_ctl.scala 822:21] + assign io_ifu_pmu_bus_error = _T_9750; // @[el2_ifu_mem_ctl.scala 823:24] + assign io_ifu_pmu_bus_busy = _T_9754; // @[el2_ifu_mem_ctl.scala 824:23] + assign io_ifu_pmu_bus_trxn = _T_9755; // @[el2_ifu_mem_ctl.scala 825:23] + assign io_ifu_axi_awvalid = 1'h0; // @[el2_ifu_mem_ctl.scala 144:22] + assign io_ifu_axi_awid = 3'h0; // @[el2_ifu_mem_ctl.scala 143:19] + assign io_ifu_axi_awaddr = 32'h0; // @[el2_ifu_mem_ctl.scala 138:21] + assign io_ifu_axi_awregion = 4'h0; // @[el2_ifu_mem_ctl.scala 142:23] + assign io_ifu_axi_awlen = 8'h0; // @[el2_ifu_mem_ctl.scala 140:20] + assign io_ifu_axi_awsize = 3'h0; // @[el2_ifu_mem_ctl.scala 151:21] + assign io_ifu_axi_awburst = 2'h0; // @[el2_ifu_mem_ctl.scala 153:22] + assign io_ifu_axi_awlock = 1'h0; // @[el2_ifu_mem_ctl.scala 148:21] + assign io_ifu_axi_awcache = 4'h0; // @[el2_ifu_mem_ctl.scala 146:22] + assign io_ifu_axi_awprot = 3'h0; // @[el2_ifu_mem_ctl.scala 139:21] + assign io_ifu_axi_awqos = 4'h0; // @[el2_ifu_mem_ctl.scala 137:20] + assign io_ifu_axi_wvalid = 1'h0; // @[el2_ifu_mem_ctl.scala 135:21] + assign io_ifu_axi_wdata = 64'h0; // @[el2_ifu_mem_ctl.scala 136:20] + assign io_ifu_axi_wstrb = 8'h0; // @[el2_ifu_mem_ctl.scala 145:20] + assign io_ifu_axi_wlast = 1'h0; // @[el2_ifu_mem_ctl.scala 154:20] + assign io_ifu_axi_bready = 1'h0; // @[el2_ifu_mem_ctl.scala 149:21] + assign io_ifu_axi_arvalid = ifu_bus_cmd_valid; // @[el2_ifu_mem_ctl.scala 565:22] + assign io_ifu_axi_arid = bus_rd_addr_count & _T_2559; // @[el2_ifu_mem_ctl.scala 566:19] + assign io_ifu_axi_araddr = _T_2561 & _T_2563; // @[el2_ifu_mem_ctl.scala 567:21] + assign io_ifu_axi_arregion = ifu_ic_req_addr_f[28:25]; // @[el2_ifu_mem_ctl.scala 570:23] + assign io_ifu_axi_arlen = 8'h0; // @[el2_ifu_mem_ctl.scala 150:20] + assign io_ifu_axi_arsize = 3'h3; // @[el2_ifu_mem_ctl.scala 568:21] + assign io_ifu_axi_arburst = 2'h1; // @[el2_ifu_mem_ctl.scala 571:22] + assign io_ifu_axi_arlock = 1'h0; // @[el2_ifu_mem_ctl.scala 141:21] + assign io_ifu_axi_arcache = 4'hf; // @[el2_ifu_mem_ctl.scala 569:22] + assign io_ifu_axi_arprot = 3'h0; // @[el2_ifu_mem_ctl.scala 152:21] + assign io_ifu_axi_arqos = 4'h0; // @[el2_ifu_mem_ctl.scala 147:20] + assign io_ifu_axi_rready = 1'h1; // @[el2_ifu_mem_ctl.scala 572:21] + assign io_iccm_dma_ecc_error = iccm_dma_ecc_error; // @[el2_ifu_mem_ctl.scala 663:25] + assign io_iccm_dma_rvalid = iccm_dma_rvalid_temp; // @[el2_ifu_mem_ctl.scala 661:22] + assign io_iccm_dma_rdata = iccm_dma_rdata_temp; // @[el2_ifu_mem_ctl.scala 665:21] + assign io_iccm_dma_rtag = iccm_dma_rtag_temp; // @[el2_ifu_mem_ctl.scala 656:20] + assign io_iccm_ready = _T_2657 & _T_2651; // @[el2_ifu_mem_ctl.scala 635:17] + assign io_ic_rw_addr = _T_340 | _T_341; // @[el2_ifu_mem_ctl.scala 339:17] + assign io_ic_wr_en = bus_ic_wr_en & _T_3923; // @[el2_ifu_mem_ctl.scala 703:15] + assign io_ic_rd_en = _T_3915 | _T_3920; // @[el2_ifu_mem_ctl.scala 694:15] + assign io_ic_wr_data_0 = ic_wr_16bytes_data[70:0]; // @[el2_ifu_mem_ctl.scala 346:17] + assign io_ic_wr_data_1 = ic_wr_16bytes_data[141:71]; // @[el2_ifu_mem_ctl.scala 346:17] + assign io_ic_debug_wr_data = io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[el2_ifu_mem_ctl.scala 347:23] + assign io_ifu_ic_debug_rd_data = _T_1211; // @[el2_ifu_mem_ctl.scala 355:27] + assign io_ic_debug_addr = io_dec_tlu_ic_diag_pkt_icache_dicawics[9:0]; // @[el2_ifu_mem_ctl.scala 828:20] + assign io_ic_debug_rd_en = io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[el2_ifu_mem_ctl.scala 830:21] + assign io_ic_debug_wr_en = io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[el2_ifu_mem_ctl.scala 831:21] + assign io_ic_debug_tag_array = io_dec_tlu_ic_diag_pkt_icache_dicawics[16]; // @[el2_ifu_mem_ctl.scala 829:25] + assign io_ic_debug_way = _T_9767[1:0]; // @[el2_ifu_mem_ctl.scala 832:19] + assign io_ic_tag_valid = ic_tag_valid_unq & _T_9741; // @[el2_ifu_mem_ctl.scala 816:19] + assign io_iccm_rw_addr = _T_3061 ? io_dma_mem_addr[15:1] : _T_3068; // @[el2_ifu_mem_ctl.scala 667:19] + assign io_iccm_wren = _T_2661 | iccm_correct_ecc; // @[el2_ifu_mem_ctl.scala 637:16] + assign io_iccm_rden = _T_2665 | _T_2666; // @[el2_ifu_mem_ctl.scala 638:16] + assign io_iccm_wr_data = _T_3043 ? _T_3044 : _T_3051; // @[el2_ifu_mem_ctl.scala 644:19] + assign io_iccm_wr_size = _T_2671 & io_dma_mem_sz; // @[el2_ifu_mem_ctl.scala 640:19] + assign io_ic_hit_f = _T_263 | _T_264; // @[el2_ifu_mem_ctl.scala 290:15] + assign io_ic_access_fault_f = _T_2443 & _T_319; // @[el2_ifu_mem_ctl.scala 387:24] + assign io_ic_access_fault_type_f = io_iccm_rd_ecc_double_err ? 2'h1 : _T_1273; // @[el2_ifu_mem_ctl.scala 388:29] + assign io_iccm_rd_ecc_single_err = _T_3860 & ifc_fetch_req_f; // @[el2_ifu_mem_ctl.scala 680:29] + assign io_iccm_rd_ecc_double_err = iccm_dma_ecc_error_in & ifc_iccm_access_f; // @[el2_ifu_mem_ctl.scala 681:29] + assign io_ic_error_start = _T_1199 | ic_rd_parity_final_err; // @[el2_ifu_mem_ctl.scala 349:21] + assign io_ifu_async_error_start = io_iccm_rd_ecc_single_err | io_ic_error_start; // @[el2_ifu_mem_ctl.scala 192:28] + assign io_iccm_dma_sb_error = _T_3 & dma_iccm_req_f; // @[el2_ifu_mem_ctl.scala 191:24] + assign io_ic_fetch_val_f = {_T_1281,fetch_req_f_qual}; // @[el2_ifu_mem_ctl.scala 391:21] + assign io_ic_data_f = io_ic_rd_data[31:0]; // @[el2_ifu_mem_ctl.scala 384:16] + assign io_ic_premux_data = ic_premux_data_temp[63:0]; // @[el2_ifu_mem_ctl.scala 381:21] + assign io_ic_sel_premux_data = fetch_req_iccm_f | sel_byp_data; // @[el2_ifu_mem_ctl.scala 382:25] + assign io_ifu_ic_debug_rd_data_valid = _T_9776; // @[el2_ifu_mem_ctl.scala 839:33] + assign io_iccm_buf_correct_ecc = iccm_correct_ecc & _T_2448; // @[el2_ifu_mem_ctl.scala 482:27] + assign io_iccm_correction_state = _T_2477 ? 1'h0 : _GEN_43; // @[el2_ifu_mem_ctl.scala 517:28 el2_ifu_mem_ctl.scala 530:32 el2_ifu_mem_ctl.scala 537:32 el2_ifu_mem_ctl.scala 544:32] + assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_io_en = ic_debug_rd_en_ff; // @[el2_lib.scala 485:16] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_1_io_en = io_ic_debug_rd_en | io_ic_debug_wr_en; // @[el2_lib.scala 485:16] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_2_io_en = _T_2 | scnd_miss_req; // @[el2_lib.scala 485:16] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_3_io_en = _T_309 | io_dec_tlu_force_halt; // @[el2_lib.scala 485:16] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_4_io_en = bus_ifu_wr_en & _T_1284; // @[el2_lib.scala 485:16] + assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_5_io_en = bus_ifu_wr_en & _T_1285; // @[el2_lib.scala 485:16] + assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_6_io_en = bus_ifu_wr_en & _T_1286; // @[el2_lib.scala 485:16] + assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_7_io_en = bus_ifu_wr_en & _T_1287; // @[el2_lib.scala 485:16] + assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_8_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_8_io_en = bus_ifu_wr_en & _T_1288; // @[el2_lib.scala 485:16] + assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_9_io_en = bus_ifu_wr_en & _T_1289; // @[el2_lib.scala 485:16] + assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_10_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_10_io_en = bus_ifu_wr_en & _T_1290; // @[el2_lib.scala 485:16] + assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_11_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_11_io_en = bus_ifu_wr_en & _T_1291; // @[el2_lib.scala 485:16] + assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_12_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_12_io_en = bus_ifu_wr_en & _T_1284; // @[el2_lib.scala 485:16] + assign rvclkhdr_12_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_13_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_13_io_en = bus_ifu_wr_en & _T_1285; // @[el2_lib.scala 485:16] + assign rvclkhdr_13_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_14_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_14_io_en = bus_ifu_wr_en & _T_1286; // @[el2_lib.scala 485:16] + assign rvclkhdr_14_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_15_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_15_io_en = bus_ifu_wr_en & _T_1287; // @[el2_lib.scala 485:16] + assign rvclkhdr_15_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_16_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_16_io_en = bus_ifu_wr_en & _T_1288; // @[el2_lib.scala 485:16] + assign rvclkhdr_16_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_17_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_17_io_en = bus_ifu_wr_en & _T_1289; // @[el2_lib.scala 485:16] + assign rvclkhdr_17_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_18_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_18_io_en = bus_ifu_wr_en & _T_1290; // @[el2_lib.scala 485:16] + assign rvclkhdr_18_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_19_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_19_io_en = bus_ifu_wr_en & _T_1291; // @[el2_lib.scala 485:16] + assign rvclkhdr_19_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_20_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_20_io_en = bus_ifu_wr_en & _T_1284; // @[el2_lib.scala 485:16] + assign rvclkhdr_20_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_21_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_21_io_en = bus_ifu_wr_en & _T_1285; // @[el2_lib.scala 485:16] + assign rvclkhdr_21_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_22_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_22_io_en = bus_ifu_wr_en & _T_1286; // @[el2_lib.scala 485:16] + assign rvclkhdr_22_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_23_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_23_io_en = bus_ifu_wr_en & _T_1287; // @[el2_lib.scala 485:16] + assign rvclkhdr_23_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_24_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_24_io_en = bus_ifu_wr_en & _T_1288; // @[el2_lib.scala 485:16] + assign rvclkhdr_24_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_25_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_25_io_en = bus_ifu_wr_en & _T_1289; // @[el2_lib.scala 485:16] + assign rvclkhdr_25_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_26_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_26_io_en = bus_ifu_wr_en & _T_1290; // @[el2_lib.scala 485:16] + assign rvclkhdr_26_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_27_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_27_io_en = bus_ifu_wr_en & _T_1291; // @[el2_lib.scala 485:16] + assign rvclkhdr_27_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_28_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_28_io_en = bus_ifu_wr_en & _T_1284; // @[el2_lib.scala 485:16] + assign rvclkhdr_28_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_29_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_29_io_en = bus_ifu_wr_en & _T_1285; // @[el2_lib.scala 485:16] + assign rvclkhdr_29_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_30_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_30_io_en = bus_ifu_wr_en & _T_1286; // @[el2_lib.scala 485:16] + assign rvclkhdr_30_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_31_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_31_io_en = bus_ifu_wr_en & _T_1287; // @[el2_lib.scala 485:16] + assign rvclkhdr_31_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_32_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_32_io_en = bus_ifu_wr_en & _T_1288; // @[el2_lib.scala 485:16] + assign rvclkhdr_32_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_33_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_33_io_en = bus_ifu_wr_en & _T_1289; // @[el2_lib.scala 485:16] + assign rvclkhdr_33_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_34_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_34_io_en = bus_ifu_wr_en & _T_1290; // @[el2_lib.scala 485:16] + assign rvclkhdr_34_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_35_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_35_io_en = bus_ifu_wr_en & _T_1291; // @[el2_lib.scala 485:16] + assign rvclkhdr_35_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_36_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_36_io_en = bus_ifu_wr_en & _T_1284; // @[el2_lib.scala 485:16] + assign rvclkhdr_36_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_37_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_37_io_en = bus_ifu_wr_en & _T_1285; // @[el2_lib.scala 485:16] + assign rvclkhdr_37_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_38_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_38_io_en = bus_ifu_wr_en & _T_1286; // @[el2_lib.scala 485:16] + assign rvclkhdr_38_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_39_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_39_io_en = bus_ifu_wr_en & _T_1287; // @[el2_lib.scala 485:16] + assign rvclkhdr_39_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_40_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_40_io_en = bus_ifu_wr_en & _T_1288; // @[el2_lib.scala 485:16] + assign rvclkhdr_40_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_41_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_41_io_en = bus_ifu_wr_en & _T_1289; // @[el2_lib.scala 485:16] + assign rvclkhdr_41_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_42_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_42_io_en = bus_ifu_wr_en & _T_1290; // @[el2_lib.scala 485:16] + assign rvclkhdr_42_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_43_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_43_io_en = bus_ifu_wr_en & _T_1291; // @[el2_lib.scala 485:16] + assign rvclkhdr_43_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_44_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_44_io_en = bus_ifu_wr_en & _T_1284; // @[el2_lib.scala 485:16] + assign rvclkhdr_44_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_45_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_45_io_en = bus_ifu_wr_en & _T_1285; // @[el2_lib.scala 485:16] + assign rvclkhdr_45_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_46_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_46_io_en = bus_ifu_wr_en & _T_1286; // @[el2_lib.scala 485:16] + assign rvclkhdr_46_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_47_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_47_io_en = bus_ifu_wr_en & _T_1287; // @[el2_lib.scala 485:16] + assign rvclkhdr_47_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_48_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_48_io_en = bus_ifu_wr_en & _T_1288; // @[el2_lib.scala 485:16] + assign rvclkhdr_48_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_49_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_49_io_en = bus_ifu_wr_en & _T_1289; // @[el2_lib.scala 485:16] + assign rvclkhdr_49_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_50_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_50_io_en = bus_ifu_wr_en & _T_1290; // @[el2_lib.scala 485:16] + assign rvclkhdr_50_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_51_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_51_io_en = bus_ifu_wr_en & _T_1291; // @[el2_lib.scala 485:16] + assign rvclkhdr_51_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_52_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_52_io_en = bus_ifu_wr_en & _T_1284; // @[el2_lib.scala 485:16] + assign rvclkhdr_52_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_53_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_53_io_en = bus_ifu_wr_en & _T_1285; // @[el2_lib.scala 485:16] + assign rvclkhdr_53_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_54_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_54_io_en = bus_ifu_wr_en & _T_1286; // @[el2_lib.scala 485:16] + assign rvclkhdr_54_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_55_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_55_io_en = bus_ifu_wr_en & _T_1287; // @[el2_lib.scala 485:16] + assign rvclkhdr_55_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_56_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_56_io_en = bus_ifu_wr_en & _T_1288; // @[el2_lib.scala 485:16] + assign rvclkhdr_56_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_57_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_57_io_en = bus_ifu_wr_en & _T_1289; // @[el2_lib.scala 485:16] + assign rvclkhdr_57_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_58_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_58_io_en = bus_ifu_wr_en & _T_1290; // @[el2_lib.scala 485:16] + assign rvclkhdr_58_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_59_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_59_io_en = bus_ifu_wr_en & _T_1291; // @[el2_lib.scala 485:16] + assign rvclkhdr_59_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_60_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_60_io_en = bus_ifu_wr_en & _T_1284; // @[el2_lib.scala 485:16] + assign rvclkhdr_60_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_61_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_61_io_en = bus_ifu_wr_en & _T_1285; // @[el2_lib.scala 485:16] + assign rvclkhdr_61_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_62_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_62_io_en = bus_ifu_wr_en & _T_1286; // @[el2_lib.scala 485:16] + assign rvclkhdr_62_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_63_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_63_io_en = bus_ifu_wr_en & _T_1287; // @[el2_lib.scala 485:16] + assign rvclkhdr_63_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_64_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_64_io_en = bus_ifu_wr_en & _T_1288; // @[el2_lib.scala 485:16] + assign rvclkhdr_64_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_65_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_65_io_en = bus_ifu_wr_en & _T_1289; // @[el2_lib.scala 485:16] + assign rvclkhdr_65_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_66_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_66_io_en = bus_ifu_wr_en & _T_1290; // @[el2_lib.scala 485:16] + assign rvclkhdr_66_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_67_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_67_io_en = bus_ifu_wr_en & _T_1291; // @[el2_lib.scala 485:16] + assign rvclkhdr_67_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_68_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_68_io_en = io_ifu_bus_clk_en; // @[el2_lib.scala 485:16] + assign rvclkhdr_68_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_69_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_69_io_en = io_ifu_bus_clk_en | io_dec_tlu_force_halt; // @[el2_lib.scala 485:16] + assign rvclkhdr_69_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_70_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_70_io_en = ifu_status_wr_addr_ff[6:3] == 4'h0; // @[el2_lib.scala 485:16] + assign rvclkhdr_70_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_71_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_71_io_en = ifu_status_wr_addr_ff[6:3] == 4'h1; // @[el2_lib.scala 485:16] + assign rvclkhdr_71_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_72_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_72_io_en = ifu_status_wr_addr_ff[6:3] == 4'h2; // @[el2_lib.scala 485:16] + assign rvclkhdr_72_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_73_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_73_io_en = ifu_status_wr_addr_ff[6:3] == 4'h3; // @[el2_lib.scala 485:16] + assign rvclkhdr_73_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_74_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_74_io_en = ifu_status_wr_addr_ff[6:3] == 4'h4; // @[el2_lib.scala 485:16] + assign rvclkhdr_74_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_75_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_75_io_en = ifu_status_wr_addr_ff[6:3] == 4'h5; // @[el2_lib.scala 485:16] + assign rvclkhdr_75_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_76_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_76_io_en = ifu_status_wr_addr_ff[6:3] == 4'h6; // @[el2_lib.scala 485:16] + assign rvclkhdr_76_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_77_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_77_io_en = ifu_status_wr_addr_ff[6:3] == 4'h7; // @[el2_lib.scala 485:16] + assign rvclkhdr_77_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_78_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_78_io_en = ifu_status_wr_addr_ff[6:3] == 4'h8; // @[el2_lib.scala 485:16] + assign rvclkhdr_78_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_79_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_79_io_en = ifu_status_wr_addr_ff[6:3] == 4'h9; // @[el2_lib.scala 485:16] + assign rvclkhdr_79_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_80_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_80_io_en = ifu_status_wr_addr_ff[6:3] == 4'ha; // @[el2_lib.scala 485:16] + assign rvclkhdr_80_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_81_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_81_io_en = ifu_status_wr_addr_ff[6:3] == 4'hb; // @[el2_lib.scala 485:16] + assign rvclkhdr_81_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_82_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_82_io_en = ifu_status_wr_addr_ff[6:3] == 4'hc; // @[el2_lib.scala 485:16] + assign rvclkhdr_82_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_83_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_83_io_en = ifu_status_wr_addr_ff[6:3] == 4'hd; // @[el2_lib.scala 485:16] + assign rvclkhdr_83_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_84_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_84_io_en = ifu_status_wr_addr_ff[6:3] == 4'he; // @[el2_lib.scala 485:16] + assign rvclkhdr_84_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_85_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_85_io_en = ifu_status_wr_addr_ff[6:3] == 4'hf; // @[el2_lib.scala 485:16] + assign rvclkhdr_85_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_86_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_86_io_en = tag_valid_clken_0[0]; // @[el2_lib.scala 485:16] + assign rvclkhdr_86_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_87_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_87_io_en = tag_valid_clken_0[1]; // @[el2_lib.scala 485:16] + assign rvclkhdr_87_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_88_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_88_io_en = tag_valid_clken_1[0]; // @[el2_lib.scala 485:16] + assign rvclkhdr_88_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_89_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_89_io_en = tag_valid_clken_1[1]; // @[el2_lib.scala 485:16] + assign rvclkhdr_89_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_90_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_90_io_en = tag_valid_clken_2[0]; // @[el2_lib.scala 485:16] + assign rvclkhdr_90_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_91_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_91_io_en = tag_valid_clken_2[1]; // @[el2_lib.scala 485:16] + assign rvclkhdr_91_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_92_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_92_io_en = tag_valid_clken_3[0]; // @[el2_lib.scala 485:16] + assign rvclkhdr_92_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_93_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_93_io_en = tag_valid_clken_3[1]; // @[el2_lib.scala 485:16] + assign rvclkhdr_93_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + flush_final_f = _RAND_0[0:0]; + _RAND_1 = {1{`RANDOM}}; + ifc_fetch_req_f_raw = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + miss_state = _RAND_2[2:0]; + _RAND_3 = {1{`RANDOM}}; + scnd_miss_req_q = _RAND_3[0:0]; + _RAND_4 = {1{`RANDOM}}; + ifu_fetch_addr_int_f = _RAND_4[30:0]; + _RAND_5 = {1{`RANDOM}}; + ifc_iccm_access_f = _RAND_5[0:0]; + _RAND_6 = {1{`RANDOM}}; + iccm_dma_rvalid_in = _RAND_6[0:0]; + _RAND_7 = {1{`RANDOM}}; + dma_iccm_req_f = _RAND_7[0:0]; + _RAND_8 = {1{`RANDOM}}; + perr_state = _RAND_8[2:0]; + _RAND_9 = {1{`RANDOM}}; + err_stop_state = _RAND_9[1:0]; + _RAND_10 = {1{`RANDOM}}; + reset_all_tags = _RAND_10[0:0]; + _RAND_11 = {1{`RANDOM}}; + ifc_region_acc_fault_final_f = _RAND_11[0:0]; + _RAND_12 = {1{`RANDOM}}; + ifu_bus_rvalid_unq_ff = _RAND_12[0:0]; + _RAND_13 = {1{`RANDOM}}; + bus_ifu_bus_clk_en_ff = _RAND_13[0:0]; + _RAND_14 = {1{`RANDOM}}; + uncacheable_miss_ff = _RAND_14[0:0]; + _RAND_15 = {1{`RANDOM}}; + bus_data_beat_count = _RAND_15[2:0]; + _RAND_16 = {1{`RANDOM}}; + ic_miss_buff_data_valid = _RAND_16[7:0]; + _RAND_17 = {1{`RANDOM}}; + imb_ff = _RAND_17[30:0]; + _RAND_18 = {1{`RANDOM}}; + last_data_recieved_ff = _RAND_18[0:0]; + _RAND_19 = {1{`RANDOM}}; + sel_mb_addr_ff = _RAND_19[0:0]; + _RAND_20 = {1{`RANDOM}}; + way_status_mb_scnd_ff = _RAND_20[0:0]; + _RAND_21 = {1{`RANDOM}}; + ifu_ic_rw_int_addr_ff = _RAND_21[6:0]; + _RAND_22 = {1{`RANDOM}}; + way_status_out_0 = _RAND_22[0:0]; + _RAND_23 = {1{`RANDOM}}; + way_status_out_1 = _RAND_23[0:0]; + _RAND_24 = {1{`RANDOM}}; + way_status_out_2 = _RAND_24[0:0]; + _RAND_25 = {1{`RANDOM}}; + way_status_out_3 = _RAND_25[0:0]; + _RAND_26 = {1{`RANDOM}}; + way_status_out_4 = _RAND_26[0:0]; + _RAND_27 = {1{`RANDOM}}; + way_status_out_5 = _RAND_27[0:0]; + _RAND_28 = {1{`RANDOM}}; + way_status_out_6 = _RAND_28[0:0]; + _RAND_29 = {1{`RANDOM}}; + way_status_out_7 = _RAND_29[0:0]; + _RAND_30 = {1{`RANDOM}}; + way_status_out_8 = _RAND_30[0:0]; + _RAND_31 = {1{`RANDOM}}; + way_status_out_9 = _RAND_31[0:0]; + _RAND_32 = {1{`RANDOM}}; + way_status_out_10 = _RAND_32[0:0]; + _RAND_33 = {1{`RANDOM}}; + way_status_out_11 = _RAND_33[0:0]; + _RAND_34 = {1{`RANDOM}}; + way_status_out_12 = _RAND_34[0:0]; + _RAND_35 = {1{`RANDOM}}; + way_status_out_13 = _RAND_35[0:0]; + _RAND_36 = {1{`RANDOM}}; + way_status_out_14 = _RAND_36[0:0]; + _RAND_37 = {1{`RANDOM}}; + way_status_out_15 = _RAND_37[0:0]; + _RAND_38 = {1{`RANDOM}}; + way_status_out_16 = _RAND_38[0:0]; + _RAND_39 = {1{`RANDOM}}; + way_status_out_17 = _RAND_39[0:0]; + _RAND_40 = {1{`RANDOM}}; + way_status_out_18 = _RAND_40[0:0]; + _RAND_41 = {1{`RANDOM}}; + way_status_out_19 = _RAND_41[0:0]; + _RAND_42 = {1{`RANDOM}}; + way_status_out_20 = _RAND_42[0:0]; + _RAND_43 = {1{`RANDOM}}; + way_status_out_21 = _RAND_43[0:0]; + _RAND_44 = {1{`RANDOM}}; + way_status_out_22 = _RAND_44[0:0]; + _RAND_45 = {1{`RANDOM}}; + way_status_out_23 = _RAND_45[0:0]; + _RAND_46 = {1{`RANDOM}}; + way_status_out_24 = _RAND_46[0:0]; + _RAND_47 = {1{`RANDOM}}; + way_status_out_25 = _RAND_47[0:0]; + _RAND_48 = {1{`RANDOM}}; + way_status_out_26 = _RAND_48[0:0]; + _RAND_49 = {1{`RANDOM}}; + way_status_out_27 = _RAND_49[0:0]; + _RAND_50 = {1{`RANDOM}}; + way_status_out_28 = _RAND_50[0:0]; + _RAND_51 = {1{`RANDOM}}; + way_status_out_29 = _RAND_51[0:0]; + _RAND_52 = {1{`RANDOM}}; + way_status_out_30 = _RAND_52[0:0]; + _RAND_53 = {1{`RANDOM}}; + way_status_out_31 = _RAND_53[0:0]; + _RAND_54 = {1{`RANDOM}}; + way_status_out_32 = _RAND_54[0:0]; + _RAND_55 = {1{`RANDOM}}; + way_status_out_33 = _RAND_55[0:0]; + _RAND_56 = {1{`RANDOM}}; + way_status_out_34 = _RAND_56[0:0]; + _RAND_57 = {1{`RANDOM}}; + way_status_out_35 = _RAND_57[0:0]; + _RAND_58 = {1{`RANDOM}}; + way_status_out_36 = _RAND_58[0:0]; + _RAND_59 = {1{`RANDOM}}; + way_status_out_37 = _RAND_59[0:0]; + _RAND_60 = {1{`RANDOM}}; + way_status_out_38 = _RAND_60[0:0]; + _RAND_61 = {1{`RANDOM}}; + way_status_out_39 = _RAND_61[0:0]; + _RAND_62 = {1{`RANDOM}}; + way_status_out_40 = _RAND_62[0:0]; + _RAND_63 = {1{`RANDOM}}; + way_status_out_41 = _RAND_63[0:0]; + _RAND_64 = {1{`RANDOM}}; + way_status_out_42 = _RAND_64[0:0]; + _RAND_65 = {1{`RANDOM}}; + way_status_out_43 = _RAND_65[0:0]; + _RAND_66 = {1{`RANDOM}}; + way_status_out_44 = _RAND_66[0:0]; + _RAND_67 = {1{`RANDOM}}; + way_status_out_45 = _RAND_67[0:0]; + _RAND_68 = {1{`RANDOM}}; + way_status_out_46 = _RAND_68[0:0]; + _RAND_69 = {1{`RANDOM}}; + way_status_out_47 = _RAND_69[0:0]; + _RAND_70 = {1{`RANDOM}}; + way_status_out_48 = _RAND_70[0:0]; + _RAND_71 = {1{`RANDOM}}; + way_status_out_49 = _RAND_71[0:0]; + _RAND_72 = {1{`RANDOM}}; + way_status_out_50 = _RAND_72[0:0]; + _RAND_73 = {1{`RANDOM}}; + way_status_out_51 = _RAND_73[0:0]; + _RAND_74 = {1{`RANDOM}}; + way_status_out_52 = _RAND_74[0:0]; + _RAND_75 = {1{`RANDOM}}; + way_status_out_53 = _RAND_75[0:0]; + _RAND_76 = {1{`RANDOM}}; + way_status_out_54 = _RAND_76[0:0]; + _RAND_77 = {1{`RANDOM}}; + way_status_out_55 = _RAND_77[0:0]; + _RAND_78 = {1{`RANDOM}}; + way_status_out_56 = _RAND_78[0:0]; + _RAND_79 = {1{`RANDOM}}; + way_status_out_57 = _RAND_79[0:0]; + _RAND_80 = {1{`RANDOM}}; + way_status_out_58 = _RAND_80[0:0]; + _RAND_81 = {1{`RANDOM}}; + way_status_out_59 = _RAND_81[0:0]; + _RAND_82 = {1{`RANDOM}}; + way_status_out_60 = _RAND_82[0:0]; + _RAND_83 = {1{`RANDOM}}; + way_status_out_61 = _RAND_83[0:0]; + _RAND_84 = {1{`RANDOM}}; + way_status_out_62 = _RAND_84[0:0]; + _RAND_85 = {1{`RANDOM}}; + way_status_out_63 = _RAND_85[0:0]; + _RAND_86 = {1{`RANDOM}}; + way_status_out_64 = _RAND_86[0:0]; + _RAND_87 = {1{`RANDOM}}; + way_status_out_65 = _RAND_87[0:0]; + _RAND_88 = {1{`RANDOM}}; + way_status_out_66 = _RAND_88[0:0]; + _RAND_89 = {1{`RANDOM}}; + way_status_out_67 = _RAND_89[0:0]; + _RAND_90 = {1{`RANDOM}}; + way_status_out_68 = _RAND_90[0:0]; + _RAND_91 = {1{`RANDOM}}; + way_status_out_69 = _RAND_91[0:0]; + _RAND_92 = {1{`RANDOM}}; + way_status_out_70 = _RAND_92[0:0]; + _RAND_93 = {1{`RANDOM}}; + way_status_out_71 = _RAND_93[0:0]; + _RAND_94 = {1{`RANDOM}}; + way_status_out_72 = _RAND_94[0:0]; + _RAND_95 = {1{`RANDOM}}; + way_status_out_73 = _RAND_95[0:0]; + _RAND_96 = {1{`RANDOM}}; + way_status_out_74 = _RAND_96[0:0]; + _RAND_97 = {1{`RANDOM}}; + way_status_out_75 = _RAND_97[0:0]; + _RAND_98 = {1{`RANDOM}}; + way_status_out_76 = _RAND_98[0:0]; + _RAND_99 = {1{`RANDOM}}; + way_status_out_77 = _RAND_99[0:0]; + _RAND_100 = {1{`RANDOM}}; + way_status_out_78 = _RAND_100[0:0]; + _RAND_101 = {1{`RANDOM}}; + way_status_out_79 = _RAND_101[0:0]; + _RAND_102 = {1{`RANDOM}}; + way_status_out_80 = _RAND_102[0:0]; + _RAND_103 = {1{`RANDOM}}; + way_status_out_81 = _RAND_103[0:0]; + _RAND_104 = {1{`RANDOM}}; + way_status_out_82 = _RAND_104[0:0]; + _RAND_105 = {1{`RANDOM}}; + way_status_out_83 = _RAND_105[0:0]; + _RAND_106 = {1{`RANDOM}}; + way_status_out_84 = _RAND_106[0:0]; + _RAND_107 = {1{`RANDOM}}; + way_status_out_85 = _RAND_107[0:0]; + _RAND_108 = {1{`RANDOM}}; + way_status_out_86 = _RAND_108[0:0]; + _RAND_109 = {1{`RANDOM}}; + way_status_out_87 = _RAND_109[0:0]; + _RAND_110 = {1{`RANDOM}}; + way_status_out_88 = _RAND_110[0:0]; + _RAND_111 = {1{`RANDOM}}; + way_status_out_89 = _RAND_111[0:0]; + _RAND_112 = {1{`RANDOM}}; + way_status_out_90 = _RAND_112[0:0]; + _RAND_113 = {1{`RANDOM}}; + way_status_out_91 = _RAND_113[0:0]; + _RAND_114 = {1{`RANDOM}}; + way_status_out_92 = _RAND_114[0:0]; + _RAND_115 = {1{`RANDOM}}; + way_status_out_93 = _RAND_115[0:0]; + _RAND_116 = {1{`RANDOM}}; + way_status_out_94 = _RAND_116[0:0]; + _RAND_117 = {1{`RANDOM}}; + way_status_out_95 = _RAND_117[0:0]; + _RAND_118 = {1{`RANDOM}}; + way_status_out_96 = _RAND_118[0:0]; + _RAND_119 = {1{`RANDOM}}; + way_status_out_97 = _RAND_119[0:0]; + _RAND_120 = {1{`RANDOM}}; + way_status_out_98 = _RAND_120[0:0]; + _RAND_121 = {1{`RANDOM}}; + way_status_out_99 = _RAND_121[0:0]; + _RAND_122 = {1{`RANDOM}}; + way_status_out_100 = _RAND_122[0:0]; + _RAND_123 = {1{`RANDOM}}; + way_status_out_101 = _RAND_123[0:0]; + _RAND_124 = {1{`RANDOM}}; + way_status_out_102 = _RAND_124[0:0]; + _RAND_125 = {1{`RANDOM}}; + way_status_out_103 = _RAND_125[0:0]; + _RAND_126 = {1{`RANDOM}}; + way_status_out_104 = _RAND_126[0:0]; + _RAND_127 = {1{`RANDOM}}; + way_status_out_105 = _RAND_127[0:0]; + _RAND_128 = {1{`RANDOM}}; + way_status_out_106 = _RAND_128[0:0]; + _RAND_129 = {1{`RANDOM}}; + way_status_out_107 = _RAND_129[0:0]; + _RAND_130 = {1{`RANDOM}}; + way_status_out_108 = _RAND_130[0:0]; + _RAND_131 = {1{`RANDOM}}; + way_status_out_109 = _RAND_131[0:0]; + _RAND_132 = {1{`RANDOM}}; + way_status_out_110 = _RAND_132[0:0]; + _RAND_133 = {1{`RANDOM}}; + way_status_out_111 = _RAND_133[0:0]; + _RAND_134 = {1{`RANDOM}}; + way_status_out_112 = _RAND_134[0:0]; + _RAND_135 = {1{`RANDOM}}; + way_status_out_113 = _RAND_135[0:0]; + _RAND_136 = {1{`RANDOM}}; + way_status_out_114 = _RAND_136[0:0]; + _RAND_137 = {1{`RANDOM}}; + way_status_out_115 = _RAND_137[0:0]; + _RAND_138 = {1{`RANDOM}}; + way_status_out_116 = _RAND_138[0:0]; + _RAND_139 = {1{`RANDOM}}; + way_status_out_117 = _RAND_139[0:0]; + _RAND_140 = {1{`RANDOM}}; + way_status_out_118 = _RAND_140[0:0]; + _RAND_141 = {1{`RANDOM}}; + way_status_out_119 = _RAND_141[0:0]; + _RAND_142 = {1{`RANDOM}}; + way_status_out_120 = _RAND_142[0:0]; + _RAND_143 = {1{`RANDOM}}; + way_status_out_121 = _RAND_143[0:0]; + _RAND_144 = {1{`RANDOM}}; + way_status_out_122 = _RAND_144[0:0]; + _RAND_145 = {1{`RANDOM}}; + way_status_out_123 = _RAND_145[0:0]; + _RAND_146 = {1{`RANDOM}}; + way_status_out_124 = _RAND_146[0:0]; + _RAND_147 = {1{`RANDOM}}; + way_status_out_125 = _RAND_147[0:0]; + _RAND_148 = {1{`RANDOM}}; + way_status_out_126 = _RAND_148[0:0]; + _RAND_149 = {1{`RANDOM}}; + way_status_out_127 = _RAND_149[0:0]; + _RAND_150 = {1{`RANDOM}}; + tagv_mb_scnd_ff = _RAND_150[1:0]; + _RAND_151 = {1{`RANDOM}}; + uncacheable_miss_scnd_ff = _RAND_151[0:0]; + _RAND_152 = {1{`RANDOM}}; + imb_scnd_ff = _RAND_152[30:0]; + _RAND_153 = {1{`RANDOM}}; + ifu_bus_rid_ff = _RAND_153[2:0]; + _RAND_154 = {1{`RANDOM}}; + ifu_bus_rresp_ff = _RAND_154[1:0]; + _RAND_155 = {1{`RANDOM}}; + ifu_wr_data_comb_err_ff = _RAND_155[0:0]; + _RAND_156 = {1{`RANDOM}}; + way_status_mb_ff = _RAND_156[0:0]; + _RAND_157 = {1{`RANDOM}}; + tagv_mb_ff = _RAND_157[1:0]; + _RAND_158 = {1{`RANDOM}}; + reset_ic_ff = _RAND_158[0:0]; + _RAND_159 = {1{`RANDOM}}; + fetch_uncacheable_ff = _RAND_159[0:0]; + _RAND_160 = {1{`RANDOM}}; + miss_addr = _RAND_160[25:0]; + _RAND_161 = {1{`RANDOM}}; + ifc_region_acc_fault_f = _RAND_161[0:0]; + _RAND_162 = {1{`RANDOM}}; + bus_rd_addr_count = _RAND_162[2:0]; + _RAND_163 = {1{`RANDOM}}; + ic_act_miss_f_delayed = _RAND_163[0:0]; + _RAND_164 = {2{`RANDOM}}; + ifu_bus_rdata_ff = _RAND_164[63:0]; + _RAND_165 = {1{`RANDOM}}; + ic_miss_buff_data_0 = _RAND_165[31:0]; + _RAND_166 = {1{`RANDOM}}; + ic_miss_buff_data_1 = _RAND_166[31:0]; + _RAND_167 = {1{`RANDOM}}; + ic_miss_buff_data_2 = _RAND_167[31:0]; + _RAND_168 = {1{`RANDOM}}; + ic_miss_buff_data_3 = _RAND_168[31:0]; + _RAND_169 = {1{`RANDOM}}; + ic_miss_buff_data_4 = _RAND_169[31:0]; + _RAND_170 = {1{`RANDOM}}; + ic_miss_buff_data_5 = _RAND_170[31:0]; + _RAND_171 = {1{`RANDOM}}; + ic_miss_buff_data_6 = _RAND_171[31:0]; + _RAND_172 = {1{`RANDOM}}; + ic_miss_buff_data_7 = _RAND_172[31:0]; + _RAND_173 = {1{`RANDOM}}; + ic_miss_buff_data_8 = _RAND_173[31:0]; + _RAND_174 = {1{`RANDOM}}; + ic_miss_buff_data_9 = _RAND_174[31:0]; + _RAND_175 = {1{`RANDOM}}; + ic_miss_buff_data_10 = _RAND_175[31:0]; + _RAND_176 = {1{`RANDOM}}; + ic_miss_buff_data_11 = _RAND_176[31:0]; + _RAND_177 = {1{`RANDOM}}; + ic_miss_buff_data_12 = _RAND_177[31:0]; + _RAND_178 = {1{`RANDOM}}; + ic_miss_buff_data_13 = _RAND_178[31:0]; + _RAND_179 = {1{`RANDOM}}; + ic_miss_buff_data_14 = _RAND_179[31:0]; + _RAND_180 = {1{`RANDOM}}; + ic_miss_buff_data_15 = _RAND_180[31:0]; + _RAND_181 = {1{`RANDOM}}; + ic_crit_wd_rdy_new_ff = _RAND_181[0:0]; + _RAND_182 = {1{`RANDOM}}; + ic_miss_buff_data_error = _RAND_182[7:0]; + _RAND_183 = {1{`RANDOM}}; + ic_debug_ict_array_sel_ff = _RAND_183[0:0]; + _RAND_184 = {1{`RANDOM}}; + ic_tag_valid_out_1_0 = _RAND_184[0:0]; + _RAND_185 = {1{`RANDOM}}; + ic_tag_valid_out_1_1 = _RAND_185[0:0]; + _RAND_186 = {1{`RANDOM}}; + ic_tag_valid_out_1_2 = _RAND_186[0:0]; + _RAND_187 = {1{`RANDOM}}; + ic_tag_valid_out_1_3 = _RAND_187[0:0]; + _RAND_188 = {1{`RANDOM}}; + ic_tag_valid_out_1_4 = _RAND_188[0:0]; + _RAND_189 = {1{`RANDOM}}; + ic_tag_valid_out_1_5 = _RAND_189[0:0]; + _RAND_190 = {1{`RANDOM}}; + ic_tag_valid_out_1_6 = _RAND_190[0:0]; + _RAND_191 = {1{`RANDOM}}; + ic_tag_valid_out_1_7 = _RAND_191[0:0]; + _RAND_192 = {1{`RANDOM}}; + ic_tag_valid_out_1_8 = _RAND_192[0:0]; + _RAND_193 = {1{`RANDOM}}; + ic_tag_valid_out_1_9 = _RAND_193[0:0]; + _RAND_194 = {1{`RANDOM}}; + ic_tag_valid_out_1_10 = _RAND_194[0:0]; + _RAND_195 = {1{`RANDOM}}; + ic_tag_valid_out_1_11 = _RAND_195[0:0]; + _RAND_196 = {1{`RANDOM}}; + ic_tag_valid_out_1_12 = _RAND_196[0:0]; + _RAND_197 = {1{`RANDOM}}; + ic_tag_valid_out_1_13 = _RAND_197[0:0]; + _RAND_198 = {1{`RANDOM}}; + ic_tag_valid_out_1_14 = _RAND_198[0:0]; + _RAND_199 = {1{`RANDOM}}; + ic_tag_valid_out_1_15 = _RAND_199[0:0]; + _RAND_200 = {1{`RANDOM}}; + ic_tag_valid_out_1_16 = _RAND_200[0:0]; + _RAND_201 = {1{`RANDOM}}; + ic_tag_valid_out_1_17 = _RAND_201[0:0]; + _RAND_202 = {1{`RANDOM}}; + ic_tag_valid_out_1_18 = _RAND_202[0:0]; + _RAND_203 = {1{`RANDOM}}; + ic_tag_valid_out_1_19 = _RAND_203[0:0]; + _RAND_204 = {1{`RANDOM}}; + ic_tag_valid_out_1_20 = _RAND_204[0:0]; + _RAND_205 = {1{`RANDOM}}; + ic_tag_valid_out_1_21 = _RAND_205[0:0]; + _RAND_206 = {1{`RANDOM}}; + ic_tag_valid_out_1_22 = _RAND_206[0:0]; + _RAND_207 = {1{`RANDOM}}; + ic_tag_valid_out_1_23 = _RAND_207[0:0]; + _RAND_208 = {1{`RANDOM}}; + ic_tag_valid_out_1_24 = _RAND_208[0:0]; + _RAND_209 = {1{`RANDOM}}; + ic_tag_valid_out_1_25 = _RAND_209[0:0]; + _RAND_210 = {1{`RANDOM}}; + ic_tag_valid_out_1_26 = _RAND_210[0:0]; + _RAND_211 = {1{`RANDOM}}; + ic_tag_valid_out_1_27 = _RAND_211[0:0]; + _RAND_212 = {1{`RANDOM}}; + ic_tag_valid_out_1_28 = _RAND_212[0:0]; + _RAND_213 = {1{`RANDOM}}; + ic_tag_valid_out_1_29 = _RAND_213[0:0]; + _RAND_214 = {1{`RANDOM}}; + ic_tag_valid_out_1_30 = _RAND_214[0:0]; + _RAND_215 = {1{`RANDOM}}; + ic_tag_valid_out_1_31 = _RAND_215[0:0]; + _RAND_216 = {1{`RANDOM}}; + ic_tag_valid_out_1_32 = _RAND_216[0:0]; + _RAND_217 = {1{`RANDOM}}; + ic_tag_valid_out_1_33 = _RAND_217[0:0]; + _RAND_218 = {1{`RANDOM}}; + ic_tag_valid_out_1_34 = _RAND_218[0:0]; + _RAND_219 = {1{`RANDOM}}; + ic_tag_valid_out_1_35 = _RAND_219[0:0]; + _RAND_220 = {1{`RANDOM}}; + ic_tag_valid_out_1_36 = _RAND_220[0:0]; + _RAND_221 = {1{`RANDOM}}; + ic_tag_valid_out_1_37 = _RAND_221[0:0]; + _RAND_222 = {1{`RANDOM}}; + ic_tag_valid_out_1_38 = _RAND_222[0:0]; + _RAND_223 = {1{`RANDOM}}; + ic_tag_valid_out_1_39 = _RAND_223[0:0]; + _RAND_224 = {1{`RANDOM}}; + ic_tag_valid_out_1_40 = _RAND_224[0:0]; + _RAND_225 = {1{`RANDOM}}; + ic_tag_valid_out_1_41 = _RAND_225[0:0]; + _RAND_226 = {1{`RANDOM}}; + ic_tag_valid_out_1_42 = _RAND_226[0:0]; + _RAND_227 = {1{`RANDOM}}; + ic_tag_valid_out_1_43 = _RAND_227[0:0]; + _RAND_228 = {1{`RANDOM}}; + ic_tag_valid_out_1_44 = _RAND_228[0:0]; + _RAND_229 = {1{`RANDOM}}; + ic_tag_valid_out_1_45 = _RAND_229[0:0]; + _RAND_230 = {1{`RANDOM}}; + ic_tag_valid_out_1_46 = _RAND_230[0:0]; + _RAND_231 = {1{`RANDOM}}; + ic_tag_valid_out_1_47 = _RAND_231[0:0]; + _RAND_232 = {1{`RANDOM}}; + ic_tag_valid_out_1_48 = _RAND_232[0:0]; + _RAND_233 = {1{`RANDOM}}; + ic_tag_valid_out_1_49 = _RAND_233[0:0]; + _RAND_234 = {1{`RANDOM}}; + ic_tag_valid_out_1_50 = _RAND_234[0:0]; + _RAND_235 = {1{`RANDOM}}; + ic_tag_valid_out_1_51 = _RAND_235[0:0]; + _RAND_236 = {1{`RANDOM}}; + ic_tag_valid_out_1_52 = _RAND_236[0:0]; + _RAND_237 = {1{`RANDOM}}; + ic_tag_valid_out_1_53 = _RAND_237[0:0]; + _RAND_238 = {1{`RANDOM}}; + ic_tag_valid_out_1_54 = _RAND_238[0:0]; + _RAND_239 = {1{`RANDOM}}; + ic_tag_valid_out_1_55 = _RAND_239[0:0]; + _RAND_240 = {1{`RANDOM}}; + ic_tag_valid_out_1_56 = _RAND_240[0:0]; + _RAND_241 = {1{`RANDOM}}; + ic_tag_valid_out_1_57 = _RAND_241[0:0]; + _RAND_242 = {1{`RANDOM}}; + ic_tag_valid_out_1_58 = _RAND_242[0:0]; + _RAND_243 = {1{`RANDOM}}; + ic_tag_valid_out_1_59 = _RAND_243[0:0]; + _RAND_244 = {1{`RANDOM}}; + ic_tag_valid_out_1_60 = _RAND_244[0:0]; + _RAND_245 = {1{`RANDOM}}; + ic_tag_valid_out_1_61 = _RAND_245[0:0]; + _RAND_246 = {1{`RANDOM}}; + ic_tag_valid_out_1_62 = _RAND_246[0:0]; + _RAND_247 = {1{`RANDOM}}; + ic_tag_valid_out_1_63 = _RAND_247[0:0]; + _RAND_248 = {1{`RANDOM}}; + ic_tag_valid_out_1_64 = _RAND_248[0:0]; + _RAND_249 = {1{`RANDOM}}; + ic_tag_valid_out_1_65 = _RAND_249[0:0]; + _RAND_250 = {1{`RANDOM}}; + ic_tag_valid_out_1_66 = _RAND_250[0:0]; + _RAND_251 = {1{`RANDOM}}; + ic_tag_valid_out_1_67 = _RAND_251[0:0]; + _RAND_252 = {1{`RANDOM}}; + ic_tag_valid_out_1_68 = _RAND_252[0:0]; + _RAND_253 = {1{`RANDOM}}; + ic_tag_valid_out_1_69 = _RAND_253[0:0]; + _RAND_254 = {1{`RANDOM}}; + ic_tag_valid_out_1_70 = _RAND_254[0:0]; + _RAND_255 = {1{`RANDOM}}; + ic_tag_valid_out_1_71 = _RAND_255[0:0]; + _RAND_256 = {1{`RANDOM}}; + ic_tag_valid_out_1_72 = _RAND_256[0:0]; + _RAND_257 = {1{`RANDOM}}; + ic_tag_valid_out_1_73 = _RAND_257[0:0]; + _RAND_258 = {1{`RANDOM}}; + ic_tag_valid_out_1_74 = _RAND_258[0:0]; + _RAND_259 = {1{`RANDOM}}; + ic_tag_valid_out_1_75 = _RAND_259[0:0]; + _RAND_260 = {1{`RANDOM}}; + ic_tag_valid_out_1_76 = _RAND_260[0:0]; + _RAND_261 = {1{`RANDOM}}; + ic_tag_valid_out_1_77 = _RAND_261[0:0]; + _RAND_262 = {1{`RANDOM}}; + ic_tag_valid_out_1_78 = _RAND_262[0:0]; + _RAND_263 = {1{`RANDOM}}; + ic_tag_valid_out_1_79 = _RAND_263[0:0]; + _RAND_264 = {1{`RANDOM}}; + ic_tag_valid_out_1_80 = _RAND_264[0:0]; + _RAND_265 = {1{`RANDOM}}; + ic_tag_valid_out_1_81 = _RAND_265[0:0]; + _RAND_266 = {1{`RANDOM}}; + ic_tag_valid_out_1_82 = _RAND_266[0:0]; + _RAND_267 = {1{`RANDOM}}; + ic_tag_valid_out_1_83 = _RAND_267[0:0]; + _RAND_268 = {1{`RANDOM}}; + ic_tag_valid_out_1_84 = _RAND_268[0:0]; + _RAND_269 = {1{`RANDOM}}; + ic_tag_valid_out_1_85 = _RAND_269[0:0]; + _RAND_270 = {1{`RANDOM}}; + ic_tag_valid_out_1_86 = _RAND_270[0:0]; + _RAND_271 = {1{`RANDOM}}; + ic_tag_valid_out_1_87 = _RAND_271[0:0]; + _RAND_272 = {1{`RANDOM}}; + ic_tag_valid_out_1_88 = _RAND_272[0:0]; + _RAND_273 = {1{`RANDOM}}; + ic_tag_valid_out_1_89 = _RAND_273[0:0]; + _RAND_274 = {1{`RANDOM}}; + ic_tag_valid_out_1_90 = _RAND_274[0:0]; + _RAND_275 = {1{`RANDOM}}; + ic_tag_valid_out_1_91 = _RAND_275[0:0]; + _RAND_276 = {1{`RANDOM}}; + ic_tag_valid_out_1_92 = _RAND_276[0:0]; + _RAND_277 = {1{`RANDOM}}; + ic_tag_valid_out_1_93 = _RAND_277[0:0]; + _RAND_278 = {1{`RANDOM}}; + ic_tag_valid_out_1_94 = _RAND_278[0:0]; + _RAND_279 = {1{`RANDOM}}; + ic_tag_valid_out_1_95 = _RAND_279[0:0]; + _RAND_280 = {1{`RANDOM}}; + ic_tag_valid_out_1_96 = _RAND_280[0:0]; + _RAND_281 = {1{`RANDOM}}; + ic_tag_valid_out_1_97 = _RAND_281[0:0]; + _RAND_282 = {1{`RANDOM}}; + ic_tag_valid_out_1_98 = _RAND_282[0:0]; + _RAND_283 = {1{`RANDOM}}; + ic_tag_valid_out_1_99 = _RAND_283[0:0]; + _RAND_284 = {1{`RANDOM}}; + ic_tag_valid_out_1_100 = _RAND_284[0:0]; + _RAND_285 = {1{`RANDOM}}; + ic_tag_valid_out_1_101 = _RAND_285[0:0]; + _RAND_286 = {1{`RANDOM}}; + ic_tag_valid_out_1_102 = _RAND_286[0:0]; + _RAND_287 = {1{`RANDOM}}; + ic_tag_valid_out_1_103 = _RAND_287[0:0]; + _RAND_288 = {1{`RANDOM}}; + ic_tag_valid_out_1_104 = _RAND_288[0:0]; + _RAND_289 = {1{`RANDOM}}; + ic_tag_valid_out_1_105 = _RAND_289[0:0]; + _RAND_290 = {1{`RANDOM}}; + ic_tag_valid_out_1_106 = _RAND_290[0:0]; + _RAND_291 = {1{`RANDOM}}; + ic_tag_valid_out_1_107 = _RAND_291[0:0]; + _RAND_292 = {1{`RANDOM}}; + ic_tag_valid_out_1_108 = _RAND_292[0:0]; + _RAND_293 = {1{`RANDOM}}; + ic_tag_valid_out_1_109 = _RAND_293[0:0]; + _RAND_294 = {1{`RANDOM}}; + ic_tag_valid_out_1_110 = _RAND_294[0:0]; + _RAND_295 = {1{`RANDOM}}; + ic_tag_valid_out_1_111 = _RAND_295[0:0]; + _RAND_296 = {1{`RANDOM}}; + ic_tag_valid_out_1_112 = _RAND_296[0:0]; + _RAND_297 = {1{`RANDOM}}; + ic_tag_valid_out_1_113 = _RAND_297[0:0]; + _RAND_298 = {1{`RANDOM}}; + ic_tag_valid_out_1_114 = _RAND_298[0:0]; + _RAND_299 = {1{`RANDOM}}; + ic_tag_valid_out_1_115 = _RAND_299[0:0]; + _RAND_300 = {1{`RANDOM}}; + ic_tag_valid_out_1_116 = _RAND_300[0:0]; + _RAND_301 = {1{`RANDOM}}; + ic_tag_valid_out_1_117 = _RAND_301[0:0]; + _RAND_302 = {1{`RANDOM}}; + ic_tag_valid_out_1_118 = _RAND_302[0:0]; + _RAND_303 = {1{`RANDOM}}; + ic_tag_valid_out_1_119 = _RAND_303[0:0]; + _RAND_304 = {1{`RANDOM}}; + ic_tag_valid_out_1_120 = _RAND_304[0:0]; + _RAND_305 = {1{`RANDOM}}; + ic_tag_valid_out_1_121 = _RAND_305[0:0]; + _RAND_306 = {1{`RANDOM}}; + ic_tag_valid_out_1_122 = _RAND_306[0:0]; + _RAND_307 = {1{`RANDOM}}; + ic_tag_valid_out_1_123 = _RAND_307[0:0]; + _RAND_308 = {1{`RANDOM}}; + ic_tag_valid_out_1_124 = _RAND_308[0:0]; + _RAND_309 = {1{`RANDOM}}; + ic_tag_valid_out_1_125 = _RAND_309[0:0]; + _RAND_310 = {1{`RANDOM}}; + ic_tag_valid_out_1_126 = _RAND_310[0:0]; + _RAND_311 = {1{`RANDOM}}; + ic_tag_valid_out_1_127 = _RAND_311[0:0]; + _RAND_312 = {1{`RANDOM}}; + ic_tag_valid_out_0_0 = _RAND_312[0:0]; + _RAND_313 = {1{`RANDOM}}; + ic_tag_valid_out_0_1 = _RAND_313[0:0]; + _RAND_314 = {1{`RANDOM}}; + ic_tag_valid_out_0_2 = _RAND_314[0:0]; + _RAND_315 = {1{`RANDOM}}; + ic_tag_valid_out_0_3 = _RAND_315[0:0]; + _RAND_316 = {1{`RANDOM}}; + ic_tag_valid_out_0_4 = _RAND_316[0:0]; + _RAND_317 = {1{`RANDOM}}; + ic_tag_valid_out_0_5 = _RAND_317[0:0]; + _RAND_318 = {1{`RANDOM}}; + ic_tag_valid_out_0_6 = _RAND_318[0:0]; + _RAND_319 = {1{`RANDOM}}; + ic_tag_valid_out_0_7 = _RAND_319[0:0]; + _RAND_320 = {1{`RANDOM}}; + ic_tag_valid_out_0_8 = _RAND_320[0:0]; + _RAND_321 = {1{`RANDOM}}; + ic_tag_valid_out_0_9 = _RAND_321[0:0]; + _RAND_322 = {1{`RANDOM}}; + ic_tag_valid_out_0_10 = _RAND_322[0:0]; + _RAND_323 = {1{`RANDOM}}; + ic_tag_valid_out_0_11 = _RAND_323[0:0]; + _RAND_324 = {1{`RANDOM}}; + ic_tag_valid_out_0_12 = _RAND_324[0:0]; + _RAND_325 = {1{`RANDOM}}; + ic_tag_valid_out_0_13 = _RAND_325[0:0]; + _RAND_326 = {1{`RANDOM}}; + ic_tag_valid_out_0_14 = _RAND_326[0:0]; + _RAND_327 = {1{`RANDOM}}; + ic_tag_valid_out_0_15 = _RAND_327[0:0]; + _RAND_328 = {1{`RANDOM}}; + ic_tag_valid_out_0_16 = _RAND_328[0:0]; + _RAND_329 = {1{`RANDOM}}; + ic_tag_valid_out_0_17 = _RAND_329[0:0]; + _RAND_330 = {1{`RANDOM}}; + ic_tag_valid_out_0_18 = _RAND_330[0:0]; + _RAND_331 = {1{`RANDOM}}; + ic_tag_valid_out_0_19 = _RAND_331[0:0]; + _RAND_332 = {1{`RANDOM}}; + ic_tag_valid_out_0_20 = _RAND_332[0:0]; + _RAND_333 = {1{`RANDOM}}; + ic_tag_valid_out_0_21 = _RAND_333[0:0]; + _RAND_334 = {1{`RANDOM}}; + ic_tag_valid_out_0_22 = _RAND_334[0:0]; + _RAND_335 = {1{`RANDOM}}; + ic_tag_valid_out_0_23 = _RAND_335[0:0]; + _RAND_336 = {1{`RANDOM}}; + ic_tag_valid_out_0_24 = _RAND_336[0:0]; + _RAND_337 = {1{`RANDOM}}; + ic_tag_valid_out_0_25 = _RAND_337[0:0]; + _RAND_338 = {1{`RANDOM}}; + ic_tag_valid_out_0_26 = _RAND_338[0:0]; + _RAND_339 = {1{`RANDOM}}; + ic_tag_valid_out_0_27 = _RAND_339[0:0]; + _RAND_340 = {1{`RANDOM}}; + ic_tag_valid_out_0_28 = _RAND_340[0:0]; + _RAND_341 = {1{`RANDOM}}; + ic_tag_valid_out_0_29 = _RAND_341[0:0]; + _RAND_342 = {1{`RANDOM}}; + ic_tag_valid_out_0_30 = _RAND_342[0:0]; + _RAND_343 = {1{`RANDOM}}; + ic_tag_valid_out_0_31 = _RAND_343[0:0]; + _RAND_344 = {1{`RANDOM}}; + ic_tag_valid_out_0_32 = _RAND_344[0:0]; + _RAND_345 = {1{`RANDOM}}; + ic_tag_valid_out_0_33 = _RAND_345[0:0]; + _RAND_346 = {1{`RANDOM}}; + ic_tag_valid_out_0_34 = _RAND_346[0:0]; + _RAND_347 = {1{`RANDOM}}; + ic_tag_valid_out_0_35 = _RAND_347[0:0]; + _RAND_348 = {1{`RANDOM}}; + ic_tag_valid_out_0_36 = _RAND_348[0:0]; + _RAND_349 = {1{`RANDOM}}; + ic_tag_valid_out_0_37 = _RAND_349[0:0]; + _RAND_350 = {1{`RANDOM}}; + ic_tag_valid_out_0_38 = _RAND_350[0:0]; + _RAND_351 = {1{`RANDOM}}; + ic_tag_valid_out_0_39 = _RAND_351[0:0]; + _RAND_352 = {1{`RANDOM}}; + ic_tag_valid_out_0_40 = _RAND_352[0:0]; + _RAND_353 = {1{`RANDOM}}; + ic_tag_valid_out_0_41 = _RAND_353[0:0]; + _RAND_354 = {1{`RANDOM}}; + ic_tag_valid_out_0_42 = _RAND_354[0:0]; + _RAND_355 = {1{`RANDOM}}; + ic_tag_valid_out_0_43 = _RAND_355[0:0]; + _RAND_356 = {1{`RANDOM}}; + ic_tag_valid_out_0_44 = _RAND_356[0:0]; + _RAND_357 = {1{`RANDOM}}; + ic_tag_valid_out_0_45 = _RAND_357[0:0]; + _RAND_358 = {1{`RANDOM}}; + ic_tag_valid_out_0_46 = _RAND_358[0:0]; + _RAND_359 = {1{`RANDOM}}; + ic_tag_valid_out_0_47 = _RAND_359[0:0]; + _RAND_360 = {1{`RANDOM}}; + ic_tag_valid_out_0_48 = _RAND_360[0:0]; + _RAND_361 = {1{`RANDOM}}; + ic_tag_valid_out_0_49 = _RAND_361[0:0]; + _RAND_362 = {1{`RANDOM}}; + ic_tag_valid_out_0_50 = _RAND_362[0:0]; + _RAND_363 = {1{`RANDOM}}; + ic_tag_valid_out_0_51 = _RAND_363[0:0]; + _RAND_364 = {1{`RANDOM}}; + ic_tag_valid_out_0_52 = _RAND_364[0:0]; + _RAND_365 = {1{`RANDOM}}; + ic_tag_valid_out_0_53 = _RAND_365[0:0]; + _RAND_366 = {1{`RANDOM}}; + ic_tag_valid_out_0_54 = _RAND_366[0:0]; + _RAND_367 = {1{`RANDOM}}; + ic_tag_valid_out_0_55 = _RAND_367[0:0]; + _RAND_368 = {1{`RANDOM}}; + ic_tag_valid_out_0_56 = _RAND_368[0:0]; + _RAND_369 = {1{`RANDOM}}; + ic_tag_valid_out_0_57 = _RAND_369[0:0]; + _RAND_370 = {1{`RANDOM}}; + ic_tag_valid_out_0_58 = _RAND_370[0:0]; + _RAND_371 = {1{`RANDOM}}; + ic_tag_valid_out_0_59 = _RAND_371[0:0]; + _RAND_372 = {1{`RANDOM}}; + ic_tag_valid_out_0_60 = _RAND_372[0:0]; + _RAND_373 = {1{`RANDOM}}; + ic_tag_valid_out_0_61 = _RAND_373[0:0]; + _RAND_374 = {1{`RANDOM}}; + ic_tag_valid_out_0_62 = _RAND_374[0:0]; + _RAND_375 = {1{`RANDOM}}; + ic_tag_valid_out_0_63 = _RAND_375[0:0]; + _RAND_376 = {1{`RANDOM}}; + ic_tag_valid_out_0_64 = _RAND_376[0:0]; + _RAND_377 = {1{`RANDOM}}; + ic_tag_valid_out_0_65 = _RAND_377[0:0]; + _RAND_378 = {1{`RANDOM}}; + ic_tag_valid_out_0_66 = _RAND_378[0:0]; + _RAND_379 = {1{`RANDOM}}; + ic_tag_valid_out_0_67 = _RAND_379[0:0]; + _RAND_380 = {1{`RANDOM}}; + ic_tag_valid_out_0_68 = _RAND_380[0:0]; + _RAND_381 = {1{`RANDOM}}; + ic_tag_valid_out_0_69 = _RAND_381[0:0]; + _RAND_382 = {1{`RANDOM}}; + ic_tag_valid_out_0_70 = _RAND_382[0:0]; + _RAND_383 = {1{`RANDOM}}; + ic_tag_valid_out_0_71 = _RAND_383[0:0]; + _RAND_384 = {1{`RANDOM}}; + ic_tag_valid_out_0_72 = _RAND_384[0:0]; + _RAND_385 = {1{`RANDOM}}; + ic_tag_valid_out_0_73 = _RAND_385[0:0]; + _RAND_386 = {1{`RANDOM}}; + ic_tag_valid_out_0_74 = _RAND_386[0:0]; + _RAND_387 = {1{`RANDOM}}; + ic_tag_valid_out_0_75 = _RAND_387[0:0]; + _RAND_388 = {1{`RANDOM}}; + ic_tag_valid_out_0_76 = _RAND_388[0:0]; + _RAND_389 = {1{`RANDOM}}; + ic_tag_valid_out_0_77 = _RAND_389[0:0]; + _RAND_390 = {1{`RANDOM}}; + ic_tag_valid_out_0_78 = _RAND_390[0:0]; + _RAND_391 = {1{`RANDOM}}; + ic_tag_valid_out_0_79 = _RAND_391[0:0]; + _RAND_392 = {1{`RANDOM}}; + ic_tag_valid_out_0_80 = _RAND_392[0:0]; + _RAND_393 = {1{`RANDOM}}; + ic_tag_valid_out_0_81 = _RAND_393[0:0]; + _RAND_394 = {1{`RANDOM}}; + ic_tag_valid_out_0_82 = _RAND_394[0:0]; + _RAND_395 = {1{`RANDOM}}; + ic_tag_valid_out_0_83 = _RAND_395[0:0]; + _RAND_396 = {1{`RANDOM}}; + ic_tag_valid_out_0_84 = _RAND_396[0:0]; + _RAND_397 = {1{`RANDOM}}; + ic_tag_valid_out_0_85 = _RAND_397[0:0]; + _RAND_398 = {1{`RANDOM}}; + ic_tag_valid_out_0_86 = _RAND_398[0:0]; + _RAND_399 = {1{`RANDOM}}; + ic_tag_valid_out_0_87 = _RAND_399[0:0]; + _RAND_400 = {1{`RANDOM}}; + ic_tag_valid_out_0_88 = _RAND_400[0:0]; + _RAND_401 = {1{`RANDOM}}; + ic_tag_valid_out_0_89 = _RAND_401[0:0]; + _RAND_402 = {1{`RANDOM}}; + ic_tag_valid_out_0_90 = _RAND_402[0:0]; + _RAND_403 = {1{`RANDOM}}; + ic_tag_valid_out_0_91 = _RAND_403[0:0]; + _RAND_404 = {1{`RANDOM}}; + ic_tag_valid_out_0_92 = _RAND_404[0:0]; + _RAND_405 = {1{`RANDOM}}; + ic_tag_valid_out_0_93 = _RAND_405[0:0]; + _RAND_406 = {1{`RANDOM}}; + ic_tag_valid_out_0_94 = _RAND_406[0:0]; + _RAND_407 = {1{`RANDOM}}; + ic_tag_valid_out_0_95 = _RAND_407[0:0]; + _RAND_408 = {1{`RANDOM}}; + ic_tag_valid_out_0_96 = _RAND_408[0:0]; + _RAND_409 = {1{`RANDOM}}; + ic_tag_valid_out_0_97 = _RAND_409[0:0]; + _RAND_410 = {1{`RANDOM}}; + ic_tag_valid_out_0_98 = _RAND_410[0:0]; + _RAND_411 = {1{`RANDOM}}; + ic_tag_valid_out_0_99 = _RAND_411[0:0]; + _RAND_412 = {1{`RANDOM}}; + ic_tag_valid_out_0_100 = _RAND_412[0:0]; + _RAND_413 = {1{`RANDOM}}; + ic_tag_valid_out_0_101 = _RAND_413[0:0]; + _RAND_414 = {1{`RANDOM}}; + ic_tag_valid_out_0_102 = _RAND_414[0:0]; + _RAND_415 = {1{`RANDOM}}; + ic_tag_valid_out_0_103 = _RAND_415[0:0]; + _RAND_416 = {1{`RANDOM}}; + ic_tag_valid_out_0_104 = _RAND_416[0:0]; + _RAND_417 = {1{`RANDOM}}; + ic_tag_valid_out_0_105 = _RAND_417[0:0]; + _RAND_418 = {1{`RANDOM}}; + ic_tag_valid_out_0_106 = _RAND_418[0:0]; + _RAND_419 = {1{`RANDOM}}; + ic_tag_valid_out_0_107 = _RAND_419[0:0]; + _RAND_420 = {1{`RANDOM}}; + ic_tag_valid_out_0_108 = _RAND_420[0:0]; + _RAND_421 = {1{`RANDOM}}; + ic_tag_valid_out_0_109 = _RAND_421[0:0]; + _RAND_422 = {1{`RANDOM}}; + ic_tag_valid_out_0_110 = _RAND_422[0:0]; + _RAND_423 = {1{`RANDOM}}; + ic_tag_valid_out_0_111 = _RAND_423[0:0]; + _RAND_424 = {1{`RANDOM}}; + ic_tag_valid_out_0_112 = _RAND_424[0:0]; + _RAND_425 = {1{`RANDOM}}; + ic_tag_valid_out_0_113 = _RAND_425[0:0]; + _RAND_426 = {1{`RANDOM}}; + ic_tag_valid_out_0_114 = _RAND_426[0:0]; + _RAND_427 = {1{`RANDOM}}; + ic_tag_valid_out_0_115 = _RAND_427[0:0]; + _RAND_428 = {1{`RANDOM}}; + ic_tag_valid_out_0_116 = _RAND_428[0:0]; + _RAND_429 = {1{`RANDOM}}; + ic_tag_valid_out_0_117 = _RAND_429[0:0]; + _RAND_430 = {1{`RANDOM}}; + ic_tag_valid_out_0_118 = _RAND_430[0:0]; + _RAND_431 = {1{`RANDOM}}; + ic_tag_valid_out_0_119 = _RAND_431[0:0]; + _RAND_432 = {1{`RANDOM}}; + ic_tag_valid_out_0_120 = _RAND_432[0:0]; + _RAND_433 = {1{`RANDOM}}; + ic_tag_valid_out_0_121 = _RAND_433[0:0]; + _RAND_434 = {1{`RANDOM}}; + ic_tag_valid_out_0_122 = _RAND_434[0:0]; + _RAND_435 = {1{`RANDOM}}; + ic_tag_valid_out_0_123 = _RAND_435[0:0]; + _RAND_436 = {1{`RANDOM}}; + ic_tag_valid_out_0_124 = _RAND_436[0:0]; + _RAND_437 = {1{`RANDOM}}; + ic_tag_valid_out_0_125 = _RAND_437[0:0]; + _RAND_438 = {1{`RANDOM}}; + ic_tag_valid_out_0_126 = _RAND_438[0:0]; + _RAND_439 = {1{`RANDOM}}; + ic_tag_valid_out_0_127 = _RAND_439[0:0]; + _RAND_440 = {1{`RANDOM}}; + ic_debug_way_ff = _RAND_440[1:0]; + _RAND_441 = {1{`RANDOM}}; + ic_debug_rd_en_ff = _RAND_441[0:0]; + _RAND_442 = {3{`RANDOM}}; + _T_1211 = _RAND_442[70:0]; + _RAND_443 = {1{`RANDOM}}; + ifc_region_acc_fault_memory_f = _RAND_443[0:0]; + _RAND_444 = {1{`RANDOM}}; + perr_ic_index_ff = _RAND_444[6:0]; + _RAND_445 = {1{`RANDOM}}; + dma_sb_err_state_ff = _RAND_445[0:0]; + _RAND_446 = {1{`RANDOM}}; + bus_cmd_req_hold = _RAND_446[0:0]; + _RAND_447 = {1{`RANDOM}}; + ifu_bus_cmd_valid = _RAND_447[0:0]; + _RAND_448 = {1{`RANDOM}}; + bus_cmd_beat_count = _RAND_448[2:0]; + _RAND_449 = {1{`RANDOM}}; + ifu_bus_arready_unq_ff = _RAND_449[0:0]; + _RAND_450 = {1{`RANDOM}}; + ifu_bus_arvalid_ff = _RAND_450[0:0]; + _RAND_451 = {1{`RANDOM}}; + ifc_dma_access_ok_prev = _RAND_451[0:0]; + _RAND_452 = {2{`RANDOM}}; + iccm_ecc_corr_data_ff = _RAND_452[38:0]; + _RAND_453 = {1{`RANDOM}}; + dma_mem_addr_ff = _RAND_453[1:0]; + _RAND_454 = {1{`RANDOM}}; + dma_mem_tag_ff = _RAND_454[2:0]; + _RAND_455 = {1{`RANDOM}}; + iccm_dma_rtag_temp = _RAND_455[2:0]; + _RAND_456 = {1{`RANDOM}}; + iccm_dma_rvalid_temp = _RAND_456[0:0]; + _RAND_457 = {1{`RANDOM}}; + iccm_dma_ecc_error = _RAND_457[0:0]; + _RAND_458 = {2{`RANDOM}}; + iccm_dma_rdata_temp = _RAND_458[63:0]; + _RAND_459 = {1{`RANDOM}}; + iccm_ecc_corr_index_ff = _RAND_459[13:0]; + _RAND_460 = {1{`RANDOM}}; + iccm_rd_ecc_single_err_ff = _RAND_460[0:0]; + _RAND_461 = {1{`RANDOM}}; + iccm_rw_addr_f = _RAND_461[13:0]; + _RAND_462 = {1{`RANDOM}}; + ifu_status_wr_addr_ff = _RAND_462[6:0]; + _RAND_463 = {1{`RANDOM}}; + way_status_wr_en_ff = _RAND_463[0:0]; + _RAND_464 = {1{`RANDOM}}; + way_status_new_ff = _RAND_464[0:0]; + _RAND_465 = {1{`RANDOM}}; + ifu_tag_wren_ff = _RAND_465[1:0]; + _RAND_466 = {1{`RANDOM}}; + ic_valid_ff = _RAND_466[0:0]; + _RAND_467 = {1{`RANDOM}}; + _T_9748 = _RAND_467[0:0]; + _RAND_468 = {1{`RANDOM}}; + _T_9749 = _RAND_468[0:0]; + _RAND_469 = {1{`RANDOM}}; + _T_9750 = _RAND_469[0:0]; + _RAND_470 = {1{`RANDOM}}; + _T_9754 = _RAND_470[0:0]; + _RAND_471 = {1{`RANDOM}}; + _T_9755 = _RAND_471[0:0]; + _RAND_472 = {1{`RANDOM}}; + _T_9776 = _RAND_472[0:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + flush_final_f = 1'h0; + end + if (reset) begin + ifc_fetch_req_f_raw = 1'h0; + end + if (reset) begin + miss_state = 3'h0; + end + if (reset) begin + scnd_miss_req_q = 1'h0; + end + if (reset) begin + ifu_fetch_addr_int_f = 31'h0; + end + if (reset) begin + ifc_iccm_access_f = 1'h0; + end + if (reset) begin + iccm_dma_rvalid_in = 1'h0; + end + if (reset) begin + dma_iccm_req_f = 1'h0; + end + if (reset) begin + perr_state = 3'h0; + end + if (reset) begin + err_stop_state = 2'h0; + end + if (reset) begin + reset_all_tags = 1'h0; + end + if (reset) begin + ifc_region_acc_fault_final_f = 1'h0; + end + if (reset) begin + ifu_bus_rvalid_unq_ff = 1'h0; + end + if (reset) begin + bus_ifu_bus_clk_en_ff = 1'h0; + end + if (reset) begin + uncacheable_miss_ff = 1'h0; + end + if (reset) begin + bus_data_beat_count = 3'h0; + end + if (reset) begin + ic_miss_buff_data_valid = 8'h0; + end + if (reset) begin + last_data_recieved_ff = 1'h0; + end + if (reset) begin + sel_mb_addr_ff = 1'h0; + end + if (reset) begin + way_status_mb_scnd_ff = 1'h0; + end + if (reset) begin + ifu_ic_rw_int_addr_ff = 7'h0; + end + if (reset) begin + way_status_out_0 = 1'h0; + end + if (reset) begin + way_status_out_1 = 1'h0; + end + if (reset) begin + way_status_out_2 = 1'h0; + end + if (reset) begin + way_status_out_3 = 1'h0; + end + if (reset) begin + way_status_out_4 = 1'h0; + end + if (reset) begin + way_status_out_5 = 1'h0; + end + if (reset) begin + way_status_out_6 = 1'h0; + end + if (reset) begin + way_status_out_7 = 1'h0; + end + if (reset) begin + way_status_out_8 = 1'h0; + end + if (reset) begin + way_status_out_9 = 1'h0; + end + if (reset) begin + way_status_out_10 = 1'h0; + end + if (reset) begin + way_status_out_11 = 1'h0; + end + if (reset) begin + way_status_out_12 = 1'h0; + end + if (reset) begin + way_status_out_13 = 1'h0; + end + if (reset) begin + way_status_out_14 = 1'h0; + end + if (reset) begin + way_status_out_15 = 1'h0; + end + if (reset) begin + way_status_out_16 = 1'h0; + end + if (reset) begin + way_status_out_17 = 1'h0; + end + if (reset) begin + way_status_out_18 = 1'h0; + end + if (reset) begin + way_status_out_19 = 1'h0; + end + if (reset) begin + way_status_out_20 = 1'h0; + end + if (reset) begin + way_status_out_21 = 1'h0; + end + if (reset) begin + way_status_out_22 = 1'h0; + end + if (reset) begin + way_status_out_23 = 1'h0; + end + if (reset) begin + way_status_out_24 = 1'h0; + end + if (reset) begin + way_status_out_25 = 1'h0; + end + if (reset) begin + way_status_out_26 = 1'h0; + end + if (reset) begin + way_status_out_27 = 1'h0; + end + if (reset) begin + way_status_out_28 = 1'h0; + end + if (reset) begin + way_status_out_29 = 1'h0; + end + if (reset) begin + way_status_out_30 = 1'h0; + end + if (reset) begin + way_status_out_31 = 1'h0; + end + if (reset) begin + way_status_out_32 = 1'h0; + end + if (reset) begin + way_status_out_33 = 1'h0; + end + if (reset) begin + way_status_out_34 = 1'h0; + end + if (reset) begin + way_status_out_35 = 1'h0; + end + if (reset) begin + way_status_out_36 = 1'h0; + end + if (reset) begin + way_status_out_37 = 1'h0; + end + if (reset) begin + way_status_out_38 = 1'h0; + end + if (reset) begin + way_status_out_39 = 1'h0; + end + if (reset) begin + way_status_out_40 = 1'h0; + end + if (reset) begin + way_status_out_41 = 1'h0; + end + if (reset) begin + way_status_out_42 = 1'h0; + end + if (reset) begin + way_status_out_43 = 1'h0; + end + if (reset) begin + way_status_out_44 = 1'h0; + end + if (reset) begin + way_status_out_45 = 1'h0; + end + if (reset) begin + way_status_out_46 = 1'h0; + end + if (reset) begin + way_status_out_47 = 1'h0; + end + if (reset) begin + way_status_out_48 = 1'h0; + end + if (reset) begin + way_status_out_49 = 1'h0; + end + if (reset) begin + way_status_out_50 = 1'h0; + end + if (reset) begin + way_status_out_51 = 1'h0; + end + if (reset) begin + way_status_out_52 = 1'h0; + end + if (reset) begin + way_status_out_53 = 1'h0; + end + if (reset) begin + way_status_out_54 = 1'h0; + end + if (reset) begin + way_status_out_55 = 1'h0; + end + if (reset) begin + way_status_out_56 = 1'h0; + end + if (reset) begin + way_status_out_57 = 1'h0; + end + if (reset) begin + way_status_out_58 = 1'h0; + end + if (reset) begin + way_status_out_59 = 1'h0; + end + if (reset) begin + way_status_out_60 = 1'h0; + end + if (reset) begin + way_status_out_61 = 1'h0; + end + if (reset) begin + way_status_out_62 = 1'h0; + end + if (reset) begin + way_status_out_63 = 1'h0; + end + if (reset) begin + way_status_out_64 = 1'h0; + end + if (reset) begin + way_status_out_65 = 1'h0; + end + if (reset) begin + way_status_out_66 = 1'h0; + end + if (reset) begin + way_status_out_67 = 1'h0; + end + if (reset) begin + way_status_out_68 = 1'h0; + end + if (reset) begin + way_status_out_69 = 1'h0; + end + if (reset) begin + way_status_out_70 = 1'h0; + end + if (reset) begin + way_status_out_71 = 1'h0; + end + if (reset) begin + way_status_out_72 = 1'h0; + end + if (reset) begin + way_status_out_73 = 1'h0; + end + if (reset) begin + way_status_out_74 = 1'h0; + end + if (reset) begin + way_status_out_75 = 1'h0; + end + if (reset) begin + way_status_out_76 = 1'h0; + end + if (reset) begin + way_status_out_77 = 1'h0; + end + if (reset) begin + way_status_out_78 = 1'h0; + end + if (reset) begin + way_status_out_79 = 1'h0; + end + if (reset) begin + way_status_out_80 = 1'h0; + end + if (reset) begin + way_status_out_81 = 1'h0; + end + if (reset) begin + way_status_out_82 = 1'h0; + end + if (reset) begin + way_status_out_83 = 1'h0; + end + if (reset) begin + way_status_out_84 = 1'h0; + end + if (reset) begin + way_status_out_85 = 1'h0; + end + if (reset) begin + way_status_out_86 = 1'h0; + end + if (reset) begin + way_status_out_87 = 1'h0; + end + if (reset) begin + way_status_out_88 = 1'h0; + end + if (reset) begin + way_status_out_89 = 1'h0; + end + if (reset) begin + way_status_out_90 = 1'h0; + end + if (reset) begin + way_status_out_91 = 1'h0; + end + if (reset) begin + way_status_out_92 = 1'h0; + end + if (reset) begin + way_status_out_93 = 1'h0; + end + if (reset) begin + way_status_out_94 = 1'h0; + end + if (reset) begin + way_status_out_95 = 1'h0; + end + if (reset) begin + way_status_out_96 = 1'h0; + end + if (reset) begin + way_status_out_97 = 1'h0; + end + if (reset) begin + way_status_out_98 = 1'h0; + end + if (reset) begin + way_status_out_99 = 1'h0; + end + if (reset) begin + way_status_out_100 = 1'h0; + end + if (reset) begin + way_status_out_101 = 1'h0; + end + if (reset) begin + way_status_out_102 = 1'h0; + end + if (reset) begin + way_status_out_103 = 1'h0; + end + if (reset) begin + way_status_out_104 = 1'h0; + end + if (reset) begin + way_status_out_105 = 1'h0; + end + if (reset) begin + way_status_out_106 = 1'h0; + end + if (reset) begin + way_status_out_107 = 1'h0; + end + if (reset) begin + way_status_out_108 = 1'h0; + end + if (reset) begin + way_status_out_109 = 1'h0; + end + if (reset) begin + way_status_out_110 = 1'h0; + end + if (reset) begin + way_status_out_111 = 1'h0; + end + if (reset) begin + way_status_out_112 = 1'h0; + end + if (reset) begin + way_status_out_113 = 1'h0; + end + if (reset) begin + way_status_out_114 = 1'h0; + end + if (reset) begin + way_status_out_115 = 1'h0; + end + if (reset) begin + way_status_out_116 = 1'h0; + end + if (reset) begin + way_status_out_117 = 1'h0; + end + if (reset) begin + way_status_out_118 = 1'h0; + end + if (reset) begin + way_status_out_119 = 1'h0; + end + if (reset) begin + way_status_out_120 = 1'h0; + end + if (reset) begin + way_status_out_121 = 1'h0; + end + if (reset) begin + way_status_out_122 = 1'h0; + end + if (reset) begin + way_status_out_123 = 1'h0; + end + if (reset) begin + way_status_out_124 = 1'h0; + end + if (reset) begin + way_status_out_125 = 1'h0; + end + if (reset) begin + way_status_out_126 = 1'h0; + end + if (reset) begin + way_status_out_127 = 1'h0; + end + if (reset) begin + tagv_mb_scnd_ff = 2'h0; + end + if (reset) begin + uncacheable_miss_scnd_ff = 1'h0; + end + if (reset) begin + imb_scnd_ff = 31'h0; + end + if (reset) begin + ifu_bus_rid_ff = 3'h0; + end + if (reset) begin + ifu_bus_rresp_ff = 2'h0; + end + if (reset) begin + ifu_wr_data_comb_err_ff = 1'h0; + end + if (reset) begin + way_status_mb_ff = 1'h0; + end + if (reset) begin + tagv_mb_ff = 2'h0; + end + if (reset) begin + fetch_uncacheable_ff = 1'h0; + end + if (reset) begin + miss_addr = 26'h0; + end + if (reset) begin + ifc_region_acc_fault_f = 1'h0; + end + if (reset) begin + bus_rd_addr_count = 3'h0; + end + if (reset) begin + ic_act_miss_f_delayed = 1'h0; + end + if (reset) begin + ifu_bus_rdata_ff = 64'h0; + end + if (reset) begin + ic_miss_buff_data_0 = 32'h0; + end + if (reset) begin + ic_miss_buff_data_1 = 32'h0; + end + if (reset) begin + ic_miss_buff_data_2 = 32'h0; + end + if (reset) begin + ic_miss_buff_data_3 = 32'h0; + end + if (reset) begin + ic_miss_buff_data_4 = 32'h0; + end + if (reset) begin + ic_miss_buff_data_5 = 32'h0; + end + if (reset) begin + ic_miss_buff_data_6 = 32'h0; + end + if (reset) begin + ic_miss_buff_data_7 = 32'h0; + end + if (reset) begin + ic_miss_buff_data_8 = 32'h0; + end + if (reset) begin + ic_miss_buff_data_9 = 32'h0; + end + if (reset) begin + ic_miss_buff_data_10 = 32'h0; + end + if (reset) begin + ic_miss_buff_data_11 = 32'h0; + end + if (reset) begin + ic_miss_buff_data_12 = 32'h0; + end + if (reset) begin + ic_miss_buff_data_13 = 32'h0; + end + if (reset) begin + ic_miss_buff_data_14 = 32'h0; + end + if (reset) begin + ic_miss_buff_data_15 = 32'h0; + end + if (reset) begin + ic_crit_wd_rdy_new_ff = 1'h0; + end + if (reset) begin + ic_miss_buff_data_error = 8'h0; + end + if (reset) begin + ic_debug_ict_array_sel_ff = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_0 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_1 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_2 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_3 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_4 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_5 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_6 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_7 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_8 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_9 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_10 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_11 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_12 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_13 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_14 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_15 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_16 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_17 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_18 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_19 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_20 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_21 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_22 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_23 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_24 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_25 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_26 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_27 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_28 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_29 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_30 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_31 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_32 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_33 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_34 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_35 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_36 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_37 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_38 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_39 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_40 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_41 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_42 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_43 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_44 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_45 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_46 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_47 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_48 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_49 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_50 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_51 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_52 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_53 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_54 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_55 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_56 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_57 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_58 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_59 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_60 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_61 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_62 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_63 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_64 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_65 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_66 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_67 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_68 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_69 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_70 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_71 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_72 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_73 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_74 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_75 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_76 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_77 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_78 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_79 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_80 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_81 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_82 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_83 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_84 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_85 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_86 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_87 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_88 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_89 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_90 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_91 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_92 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_93 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_94 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_95 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_96 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_97 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_98 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_99 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_100 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_101 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_102 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_103 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_104 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_105 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_106 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_107 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_108 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_109 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_110 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_111 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_112 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_113 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_114 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_115 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_116 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_117 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_118 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_119 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_120 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_121 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_122 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_123 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_124 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_125 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_126 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_1_127 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_0 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_1 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_2 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_3 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_4 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_5 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_6 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_7 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_8 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_9 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_10 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_11 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_12 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_13 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_14 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_15 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_16 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_17 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_18 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_19 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_20 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_21 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_22 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_23 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_24 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_25 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_26 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_27 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_28 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_29 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_30 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_31 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_32 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_33 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_34 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_35 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_36 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_37 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_38 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_39 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_40 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_41 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_42 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_43 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_44 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_45 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_46 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_47 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_48 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_49 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_50 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_51 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_52 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_53 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_54 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_55 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_56 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_57 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_58 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_59 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_60 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_61 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_62 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_63 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_64 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_65 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_66 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_67 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_68 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_69 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_70 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_71 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_72 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_73 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_74 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_75 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_76 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_77 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_78 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_79 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_80 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_81 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_82 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_83 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_84 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_85 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_86 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_87 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_88 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_89 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_90 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_91 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_92 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_93 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_94 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_95 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_96 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_97 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_98 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_99 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_100 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_101 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_102 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_103 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_104 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_105 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_106 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_107 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_108 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_109 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_110 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_111 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_112 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_113 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_114 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_115 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_116 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_117 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_118 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_119 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_120 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_121 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_122 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_123 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_124 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_125 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_126 = 1'h0; + end + if (reset) begin + ic_tag_valid_out_0_127 = 1'h0; + end + if (reset) begin + ic_debug_way_ff = 2'h0; + end + if (reset) begin + ic_debug_rd_en_ff = 1'h0; + end + if (reset) begin + _T_1211 = 71'h0; + end + if (reset) begin + ifc_region_acc_fault_memory_f = 1'h0; + end + if (reset) begin + perr_ic_index_ff = 7'h0; + end + if (reset) begin + dma_sb_err_state_ff = 1'h0; + end + if (reset) begin + bus_cmd_req_hold = 1'h0; + end + if (reset) begin + ifu_bus_cmd_valid = 1'h0; + end + if (reset) begin + bus_cmd_beat_count = 3'h0; + end + if (reset) begin + ifu_bus_arready_unq_ff = 1'h0; + end + if (reset) begin + ifu_bus_arvalid_ff = 1'h0; + end + if (reset) begin + ifc_dma_access_ok_prev = 1'h0; + end + if (reset) begin + iccm_ecc_corr_data_ff = 39'h0; + end + if (reset) begin + dma_mem_addr_ff = 2'h0; + end + if (reset) begin + dma_mem_tag_ff = 3'h0; + end + if (reset) begin + iccm_dma_rtag_temp = 3'h0; + end + if (reset) begin + iccm_dma_rvalid_temp = 1'h0; + end + if (reset) begin + iccm_dma_ecc_error = 1'h0; + end + if (reset) begin + iccm_dma_rdata_temp = 64'h0; + end + if (reset) begin + iccm_ecc_corr_index_ff = 14'h0; + end + if (reset) begin + iccm_rd_ecc_single_err_ff = 1'h0; + end + if (reset) begin + iccm_rw_addr_f = 14'h0; + end + if (reset) begin + ifu_status_wr_addr_ff = 7'h0; + end + if (reset) begin + way_status_wr_en_ff = 1'h0; + end + if (reset) begin + way_status_new_ff = 1'h0; + end + if (reset) begin + ifu_tag_wren_ff = 2'h0; + end + if (reset) begin + ic_valid_ff = 1'h0; + end + if (reset) begin + _T_9748 = 1'h0; + end + if (reset) begin + _T_9749 = 1'h0; + end + if (reset) begin + _T_9750 = 1'h0; + end + if (reset) begin + _T_9754 = 1'h0; + end + if (reset) begin + _T_9755 = 1'h0; + end + if (reset) begin + _T_9776 = 1'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge rvclkhdr_2_io_l1clk) begin + if (scnd_miss_req) begin + imb_ff <= imb_scnd_ff; + end else if (!(sel_hold_imb)) begin + imb_ff <= io_ifc_fetch_addr_bf; + end + end + always @(posedge io_free_clk) begin + reset_ic_ff <= _T_298 & _T_299; + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + flush_final_f <= 1'h0; + end else begin + flush_final_f <= io_exu_flush_final; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + ifc_fetch_req_f_raw <= 1'h0; + end else begin + ifc_fetch_req_f_raw <= _T_317 & _T_318; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + miss_state <= 3'h0; + end else if (miss_state_en) begin + if (_T_24) begin + if (_T_26) begin + miss_state <= 3'h1; + end else begin + miss_state <= 3'h2; + end + end else if (_T_31) begin + if (_T_36) begin + miss_state <= 3'h0; + end else if (_T_40) begin + miss_state <= 3'h3; + end else if (_T_47) begin + miss_state <= 3'h4; + end else if (_T_51) begin + miss_state <= 3'h0; + end else if (_T_61) begin + miss_state <= 3'h6; + end else if (_T_71) begin + miss_state <= 3'h6; + end else if (_T_79) begin + miss_state <= 3'h0; + end else if (_T_84) begin + miss_state <= 3'h2; + end else begin + miss_state <= 3'h0; + end + end else if (_T_102) begin + miss_state <= 3'h0; + end else if (_T_106) begin + if (_T_113) begin + miss_state <= 3'h2; + end else begin + miss_state <= 3'h0; + end + end else if (_T_121) begin + if (_T_126) begin + miss_state <= 3'h2; + end else begin + miss_state <= 3'h0; + end + end else if (_T_132) begin + if (_T_137) begin + miss_state <= 3'h5; + end else if (_T_143) begin + miss_state <= 3'h7; + end else begin + miss_state <= 3'h0; + end + end else if (_T_151) begin + if (io_dec_tlu_force_halt) begin + miss_state <= 3'h0; + end else if (io_exu_flush_final) begin + if (_T_32) begin + miss_state <= 3'h0; + end else begin + miss_state <= 3'h2; + end + end else begin + miss_state <= 3'h1; + end + end else if (_T_160) begin + if (io_dec_tlu_force_halt) begin + miss_state <= 3'h0; + end else if (io_exu_flush_final) begin + if (_T_32) begin + miss_state <= 3'h0; + end else begin + miss_state <= 3'h2; + end + end else begin + miss_state <= 3'h0; + end + end else begin + miss_state <= 3'h0; + end + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + scnd_miss_req_q <= 1'h0; + end else begin + scnd_miss_req_q <= _T_22 & _T_319; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + ifu_fetch_addr_int_f <= 31'h0; + end else begin + ifu_fetch_addr_int_f <= io_ifc_fetch_addr_bf; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + ifc_iccm_access_f <= 1'h0; + end else begin + ifc_iccm_access_f <= io_ifc_iccm_access_bf; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + iccm_dma_rvalid_in <= 1'h0; + end else begin + iccm_dma_rvalid_in <= _T_2660 & _T_2664; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + dma_iccm_req_f <= 1'h0; + end else begin + dma_iccm_req_f <= io_dma_iccm_req; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + perr_state <= 3'h0; + end else if (perr_state_en) begin + if (_T_2451) begin + if (io_iccm_dma_sb_error) begin + perr_state <= 3'h4; + end else if (_T_2453) begin + perr_state <= 3'h1; + end else begin + perr_state <= 3'h2; + end + end else if (_T_2463) begin + perr_state <= 3'h0; + end else if (_T_2466) begin + if (_T_2469) begin + perr_state <= 3'h0; + end else begin + perr_state <= 3'h3; + end + end else if (_T_2473) begin + if (io_dec_tlu_force_halt) begin + perr_state <= 3'h0; + end else begin + perr_state <= 3'h3; + end + end else begin + perr_state <= 3'h0; + end + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + err_stop_state <= 2'h0; + end else if (err_stop_state_en) begin + if (_T_2477) begin + err_stop_state <= 2'h1; + end else if (_T_2482) begin + if (_T_2484) begin + err_stop_state <= 2'h0; + end else if (_T_2505) begin + err_stop_state <= 2'h3; + end else if (io_ifu_fetch_val[0]) begin + err_stop_state <= 2'h2; + end else begin + err_stop_state <= 2'h1; + end + end else if (_T_2509) begin + if (_T_2484) begin + err_stop_state <= 2'h0; + end else if (io_ifu_fetch_val[0]) begin + err_stop_state <= 2'h3; + end else begin + err_stop_state <= 2'h2; + end + end else if (_T_2526) begin + if (_T_2530) begin + err_stop_state <= 2'h0; + end else if (io_dec_tlu_flush_err_wb) begin + err_stop_state <= 2'h1; + end else begin + err_stop_state <= 2'h3; + end + end else begin + err_stop_state <= 2'h0; + end + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + reset_all_tags <= 1'h0; + end else begin + reset_all_tags <= io_dec_tlu_fence_i_wb; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + ifc_region_acc_fault_final_f <= 1'h0; + end else begin + ifc_region_acc_fault_final_f <= io_ifc_region_acc_fault_bf | ifc_region_acc_fault_memory_bf; + end + end + always @(posedge rvclkhdr_68_io_l1clk or posedge reset) begin + if (reset) begin + ifu_bus_rvalid_unq_ff <= 1'h0; + end else begin + ifu_bus_rvalid_unq_ff <= io_ifu_axi_rvalid; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + bus_ifu_bus_clk_en_ff <= 1'h0; + end else begin + bus_ifu_bus_clk_en_ff <= io_ifu_bus_clk_en; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + uncacheable_miss_ff <= 1'h0; + end else if (scnd_miss_req) begin + uncacheable_miss_ff <= uncacheable_miss_scnd_ff; + end else if (!(sel_hold_imb)) begin + uncacheable_miss_ff <= io_ifc_fetch_uncacheable_bf; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + bus_data_beat_count <= 3'h0; + end else begin + bus_data_beat_count <= _T_2582 | _T_2583; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + ic_miss_buff_data_valid <= 8'h0; + end else begin + ic_miss_buff_data_valid <= {_T_1353,ic_miss_buff_data_valid_in_0}; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + last_data_recieved_ff <= 1'h0; + end else begin + last_data_recieved_ff <= _T_2590 | _T_2592; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + sel_mb_addr_ff <= 1'h0; + end else begin + sel_mb_addr_ff <= _T_334 | reset_tag_valid_for_miss; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + way_status_mb_scnd_ff <= 1'h0; + end else if (!(_T_19)) begin + way_status_mb_scnd_ff <= way_status; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + ifu_ic_rw_int_addr_ff <= 7'h0; + end else if (_T_3946) begin + ifu_ic_rw_int_addr_ff <= io_ic_debug_addr[9:3]; + end else begin + ifu_ic_rw_int_addr_ff <= ifu_ic_rw_int_addr[11:5]; + end + end + always @(posedge rvclkhdr_70_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_0 <= 1'h0; + end else if (_T_3970) begin + way_status_out_0 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_70_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_1 <= 1'h0; + end else if (_T_3974) begin + way_status_out_1 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_70_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_2 <= 1'h0; + end else if (_T_3978) begin + way_status_out_2 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_70_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_3 <= 1'h0; + end else if (_T_3982) begin + way_status_out_3 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_70_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_4 <= 1'h0; + end else if (_T_3986) begin + way_status_out_4 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_70_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_5 <= 1'h0; + end else if (_T_3990) begin + way_status_out_5 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_70_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_6 <= 1'h0; + end else if (_T_3994) begin + way_status_out_6 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_70_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_7 <= 1'h0; + end else if (_T_3998) begin + way_status_out_7 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_71_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_8 <= 1'h0; + end else if (_T_3970) begin + way_status_out_8 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_71_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_9 <= 1'h0; + end else if (_T_3974) begin + way_status_out_9 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_71_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_10 <= 1'h0; + end else if (_T_3978) begin + way_status_out_10 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_71_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_11 <= 1'h0; + end else if (_T_3982) begin + way_status_out_11 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_71_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_12 <= 1'h0; + end else if (_T_3986) begin + way_status_out_12 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_71_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_13 <= 1'h0; + end else if (_T_3990) begin + way_status_out_13 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_71_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_14 <= 1'h0; + end else if (_T_3994) begin + way_status_out_14 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_71_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_15 <= 1'h0; + end else if (_T_3998) begin + way_status_out_15 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_72_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_16 <= 1'h0; + end else if (_T_3970) begin + way_status_out_16 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_72_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_17 <= 1'h0; + end else if (_T_3974) begin + way_status_out_17 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_72_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_18 <= 1'h0; + end else if (_T_3978) begin + way_status_out_18 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_72_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_19 <= 1'h0; + end else if (_T_3982) begin + way_status_out_19 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_72_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_20 <= 1'h0; + end else if (_T_3986) begin + way_status_out_20 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_72_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_21 <= 1'h0; + end else if (_T_3990) begin + way_status_out_21 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_72_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_22 <= 1'h0; + end else if (_T_3994) begin + way_status_out_22 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_72_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_23 <= 1'h0; + end else if (_T_3998) begin + way_status_out_23 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_73_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_24 <= 1'h0; + end else if (_T_3970) begin + way_status_out_24 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_73_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_25 <= 1'h0; + end else if (_T_3974) begin + way_status_out_25 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_73_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_26 <= 1'h0; + end else if (_T_3978) begin + way_status_out_26 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_73_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_27 <= 1'h0; + end else if (_T_3982) begin + way_status_out_27 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_73_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_28 <= 1'h0; + end else if (_T_3986) begin + way_status_out_28 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_73_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_29 <= 1'h0; + end else if (_T_3990) begin + way_status_out_29 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_73_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_30 <= 1'h0; + end else if (_T_3994) begin + way_status_out_30 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_73_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_31 <= 1'h0; + end else if (_T_3998) begin + way_status_out_31 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_74_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_32 <= 1'h0; + end else if (_T_3970) begin + way_status_out_32 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_74_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_33 <= 1'h0; + end else if (_T_3974) begin + way_status_out_33 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_74_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_34 <= 1'h0; + end else if (_T_3978) begin + way_status_out_34 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_74_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_35 <= 1'h0; + end else if (_T_3982) begin + way_status_out_35 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_74_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_36 <= 1'h0; + end else if (_T_3986) begin + way_status_out_36 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_74_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_37 <= 1'h0; + end else if (_T_3990) begin + way_status_out_37 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_74_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_38 <= 1'h0; + end else if (_T_3994) begin + way_status_out_38 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_74_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_39 <= 1'h0; + end else if (_T_3998) begin + way_status_out_39 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_75_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_40 <= 1'h0; + end else if (_T_3970) begin + way_status_out_40 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_75_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_41 <= 1'h0; + end else if (_T_3974) begin + way_status_out_41 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_75_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_42 <= 1'h0; + end else if (_T_3978) begin + way_status_out_42 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_75_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_43 <= 1'h0; + end else if (_T_3982) begin + way_status_out_43 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_75_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_44 <= 1'h0; + end else if (_T_3986) begin + way_status_out_44 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_75_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_45 <= 1'h0; + end else if (_T_3990) begin + way_status_out_45 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_75_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_46 <= 1'h0; + end else if (_T_3994) begin + way_status_out_46 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_75_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_47 <= 1'h0; + end else if (_T_3998) begin + way_status_out_47 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_76_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_48 <= 1'h0; + end else if (_T_3970) begin + way_status_out_48 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_76_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_49 <= 1'h0; + end else if (_T_3974) begin + way_status_out_49 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_76_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_50 <= 1'h0; + end else if (_T_3978) begin + way_status_out_50 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_76_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_51 <= 1'h0; + end else if (_T_3982) begin + way_status_out_51 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_76_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_52 <= 1'h0; + end else if (_T_3986) begin + way_status_out_52 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_76_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_53 <= 1'h0; + end else if (_T_3990) begin + way_status_out_53 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_76_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_54 <= 1'h0; + end else if (_T_3994) begin + way_status_out_54 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_76_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_55 <= 1'h0; + end else if (_T_3998) begin + way_status_out_55 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_77_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_56 <= 1'h0; + end else if (_T_3970) begin + way_status_out_56 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_77_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_57 <= 1'h0; + end else if (_T_3974) begin + way_status_out_57 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_77_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_58 <= 1'h0; + end else if (_T_3978) begin + way_status_out_58 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_77_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_59 <= 1'h0; + end else if (_T_3982) begin + way_status_out_59 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_77_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_60 <= 1'h0; + end else if (_T_3986) begin + way_status_out_60 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_77_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_61 <= 1'h0; + end else if (_T_3990) begin + way_status_out_61 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_77_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_62 <= 1'h0; + end else if (_T_3994) begin + way_status_out_62 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_77_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_63 <= 1'h0; + end else if (_T_3998) begin + way_status_out_63 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_78_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_64 <= 1'h0; + end else if (_T_3970) begin + way_status_out_64 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_78_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_65 <= 1'h0; + end else if (_T_3974) begin + way_status_out_65 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_78_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_66 <= 1'h0; + end else if (_T_3978) begin + way_status_out_66 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_78_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_67 <= 1'h0; + end else if (_T_3982) begin + way_status_out_67 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_78_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_68 <= 1'h0; + end else if (_T_3986) begin + way_status_out_68 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_78_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_69 <= 1'h0; + end else if (_T_3990) begin + way_status_out_69 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_78_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_70 <= 1'h0; + end else if (_T_3994) begin + way_status_out_70 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_78_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_71 <= 1'h0; + end else if (_T_3998) begin + way_status_out_71 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_79_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_72 <= 1'h0; + end else if (_T_3970) begin + way_status_out_72 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_79_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_73 <= 1'h0; + end else if (_T_3974) begin + way_status_out_73 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_79_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_74 <= 1'h0; + end else if (_T_3978) begin + way_status_out_74 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_79_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_75 <= 1'h0; + end else if (_T_3982) begin + way_status_out_75 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_79_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_76 <= 1'h0; + end else if (_T_3986) begin + way_status_out_76 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_79_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_77 <= 1'h0; + end else if (_T_3990) begin + way_status_out_77 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_79_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_78 <= 1'h0; + end else if (_T_3994) begin + way_status_out_78 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_79_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_79 <= 1'h0; + end else if (_T_3998) begin + way_status_out_79 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_80_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_80 <= 1'h0; + end else if (_T_3970) begin + way_status_out_80 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_80_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_81 <= 1'h0; + end else if (_T_3974) begin + way_status_out_81 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_80_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_82 <= 1'h0; + end else if (_T_3978) begin + way_status_out_82 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_80_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_83 <= 1'h0; + end else if (_T_3982) begin + way_status_out_83 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_80_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_84 <= 1'h0; + end else if (_T_3986) begin + way_status_out_84 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_80_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_85 <= 1'h0; + end else if (_T_3990) begin + way_status_out_85 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_80_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_86 <= 1'h0; + end else if (_T_3994) begin + way_status_out_86 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_80_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_87 <= 1'h0; + end else if (_T_3998) begin + way_status_out_87 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_81_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_88 <= 1'h0; + end else if (_T_3970) begin + way_status_out_88 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_81_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_89 <= 1'h0; + end else if (_T_3974) begin + way_status_out_89 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_81_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_90 <= 1'h0; + end else if (_T_3978) begin + way_status_out_90 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_81_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_91 <= 1'h0; + end else if (_T_3982) begin + way_status_out_91 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_81_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_92 <= 1'h0; + end else if (_T_3986) begin + way_status_out_92 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_81_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_93 <= 1'h0; + end else if (_T_3990) begin + way_status_out_93 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_81_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_94 <= 1'h0; + end else if (_T_3994) begin + way_status_out_94 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_81_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_95 <= 1'h0; + end else if (_T_3998) begin + way_status_out_95 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_82_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_96 <= 1'h0; + end else if (_T_3970) begin + way_status_out_96 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_82_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_97 <= 1'h0; + end else if (_T_3974) begin + way_status_out_97 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_82_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_98 <= 1'h0; + end else if (_T_3978) begin + way_status_out_98 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_82_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_99 <= 1'h0; + end else if (_T_3982) begin + way_status_out_99 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_82_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_100 <= 1'h0; + end else if (_T_3986) begin + way_status_out_100 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_82_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_101 <= 1'h0; + end else if (_T_3990) begin + way_status_out_101 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_82_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_102 <= 1'h0; + end else if (_T_3994) begin + way_status_out_102 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_82_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_103 <= 1'h0; + end else if (_T_3998) begin + way_status_out_103 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_83_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_104 <= 1'h0; + end else if (_T_3970) begin + way_status_out_104 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_83_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_105 <= 1'h0; + end else if (_T_3974) begin + way_status_out_105 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_83_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_106 <= 1'h0; + end else if (_T_3978) begin + way_status_out_106 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_83_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_107 <= 1'h0; + end else if (_T_3982) begin + way_status_out_107 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_83_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_108 <= 1'h0; + end else if (_T_3986) begin + way_status_out_108 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_83_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_109 <= 1'h0; + end else if (_T_3990) begin + way_status_out_109 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_83_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_110 <= 1'h0; + end else if (_T_3994) begin + way_status_out_110 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_83_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_111 <= 1'h0; + end else if (_T_3998) begin + way_status_out_111 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_84_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_112 <= 1'h0; + end else if (_T_3970) begin + way_status_out_112 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_84_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_113 <= 1'h0; + end else if (_T_3974) begin + way_status_out_113 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_84_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_114 <= 1'h0; + end else if (_T_3978) begin + way_status_out_114 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_84_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_115 <= 1'h0; + end else if (_T_3982) begin + way_status_out_115 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_84_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_116 <= 1'h0; + end else if (_T_3986) begin + way_status_out_116 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_84_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_117 <= 1'h0; + end else if (_T_3990) begin + way_status_out_117 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_84_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_118 <= 1'h0; + end else if (_T_3994) begin + way_status_out_118 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_84_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_119 <= 1'h0; + end else if (_T_3998) begin + way_status_out_119 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_85_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_120 <= 1'h0; + end else if (_T_3970) begin + way_status_out_120 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_85_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_121 <= 1'h0; + end else if (_T_3974) begin + way_status_out_121 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_85_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_122 <= 1'h0; + end else if (_T_3978) begin + way_status_out_122 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_85_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_123 <= 1'h0; + end else if (_T_3982) begin + way_status_out_123 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_85_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_124 <= 1'h0; + end else if (_T_3986) begin + way_status_out_124 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_85_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_125 <= 1'h0; + end else if (_T_3990) begin + way_status_out_125 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_85_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_126 <= 1'h0; + end else if (_T_3994) begin + way_status_out_126 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_85_io_l1clk or posedge reset) begin + if (reset) begin + way_status_out_127 <= 1'h0; + end else if (_T_3998) begin + way_status_out_127 <= way_status_new_ff; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + tagv_mb_scnd_ff <= 2'h0; + end else if (!(_T_19)) begin + tagv_mb_scnd_ff <= _T_198; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + uncacheable_miss_scnd_ff <= 1'h0; + end else if (!(sel_hold_imb_scnd)) begin + uncacheable_miss_scnd_ff <= io_ifc_fetch_uncacheable_bf; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + imb_scnd_ff <= 31'h0; + end else if (!(sel_hold_imb_scnd)) begin + imb_scnd_ff <= io_ifc_fetch_addr_bf; + end + end + always @(posedge rvclkhdr_68_io_l1clk or posedge reset) begin + if (reset) begin + ifu_bus_rid_ff <= 3'h0; + end else begin + ifu_bus_rid_ff <= io_ifu_axi_rid; + end + end + always @(posedge rvclkhdr_68_io_l1clk or posedge reset) begin + if (reset) begin + ifu_bus_rresp_ff <= 2'h0; + end else begin + ifu_bus_rresp_ff <= io_ifu_axi_rresp; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + ifu_wr_data_comb_err_ff <= 1'h0; + end else begin + ifu_wr_data_comb_err_ff <= ifu_wr_cumulative_err_data & _T_2578; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + way_status_mb_ff <= 1'h0; + end else if (_T_278) begin + way_status_mb_ff <= way_status_mb_scnd_ff; + end else if (_T_280) begin + way_status_mb_ff <= replace_way_mb_any_0; + end else if (!(miss_pending)) begin + way_status_mb_ff <= way_status; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + tagv_mb_ff <= 2'h0; + end else if (scnd_miss_req) begin + tagv_mb_ff <= _T_290; + end else if (!(miss_pending)) begin + tagv_mb_ff <= _T_295; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + fetch_uncacheable_ff <= 1'h0; + end else begin + fetch_uncacheable_ff <= io_ifc_fetch_uncacheable_bf; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + miss_addr <= 26'h0; + end else if (_T_231) begin + miss_addr <= imb_ff[30:5]; + end else if (scnd_miss_req_q) begin + miss_addr <= imb_scnd_ff[30:5]; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + ifc_region_acc_fault_f <= 1'h0; + end else begin + ifc_region_acc_fault_f <= io_ifc_region_acc_fault_bf; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + bus_rd_addr_count <= 3'h0; + end else if (_T_231) begin + bus_rd_addr_count <= imb_ff[4:2]; + end else if (scnd_miss_req_q) begin + bus_rd_addr_count <= imb_scnd_ff[4:2]; + end else if (bus_cmd_sent) begin + bus_rd_addr_count <= _T_2598; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + ic_act_miss_f_delayed <= 1'h0; + end else begin + ic_act_miss_f_delayed <= _T_233 & _T_209; + end + end + always @(posedge rvclkhdr_68_io_l1clk or posedge reset) begin + if (reset) begin + ifu_bus_rdata_ff <= 64'h0; + end else begin + ifu_bus_rdata_ff <= io_ifu_axi_rdata; + end + end + always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + if (reset) begin + ic_miss_buff_data_0 <= 32'h0; + end else begin + ic_miss_buff_data_0 <= io_ifu_axi_rdata[31:0]; + end + end + always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + if (reset) begin + ic_miss_buff_data_1 <= 32'h0; + end else begin + ic_miss_buff_data_1 <= io_ifu_axi_rdata[63:32]; + end + end + always @(posedge rvclkhdr_13_io_l1clk or posedge reset) begin + if (reset) begin + ic_miss_buff_data_2 <= 32'h0; + end else begin + ic_miss_buff_data_2 <= io_ifu_axi_rdata[31:0]; + end + end + always @(posedge rvclkhdr_13_io_l1clk or posedge reset) begin + if (reset) begin + ic_miss_buff_data_3 <= 32'h0; + end else begin + ic_miss_buff_data_3 <= io_ifu_axi_rdata[63:32]; + end + end + always @(posedge rvclkhdr_22_io_l1clk or posedge reset) begin + if (reset) begin + ic_miss_buff_data_4 <= 32'h0; + end else begin + ic_miss_buff_data_4 <= io_ifu_axi_rdata[31:0]; + end + end + always @(posedge rvclkhdr_22_io_l1clk or posedge reset) begin + if (reset) begin + ic_miss_buff_data_5 <= 32'h0; + end else begin + ic_miss_buff_data_5 <= io_ifu_axi_rdata[63:32]; + end + end + always @(posedge rvclkhdr_31_io_l1clk or posedge reset) begin + if (reset) begin + ic_miss_buff_data_6 <= 32'h0; + end else begin + ic_miss_buff_data_6 <= io_ifu_axi_rdata[31:0]; + end + end + always @(posedge rvclkhdr_31_io_l1clk or posedge reset) begin + if (reset) begin + ic_miss_buff_data_7 <= 32'h0; + end else begin + ic_miss_buff_data_7 <= io_ifu_axi_rdata[63:32]; + end + end + always @(posedge rvclkhdr_40_io_l1clk or posedge reset) begin + if (reset) begin + ic_miss_buff_data_8 <= 32'h0; + end else begin + ic_miss_buff_data_8 <= io_ifu_axi_rdata[31:0]; + end + end + always @(posedge rvclkhdr_40_io_l1clk or posedge reset) begin + if (reset) begin + ic_miss_buff_data_9 <= 32'h0; + end else begin + ic_miss_buff_data_9 <= io_ifu_axi_rdata[63:32]; + end + end + always @(posedge rvclkhdr_49_io_l1clk or posedge reset) begin + if (reset) begin + ic_miss_buff_data_10 <= 32'h0; + end else begin + ic_miss_buff_data_10 <= io_ifu_axi_rdata[31:0]; + end + end + always @(posedge rvclkhdr_49_io_l1clk or posedge reset) begin + if (reset) begin + ic_miss_buff_data_11 <= 32'h0; + end else begin + ic_miss_buff_data_11 <= io_ifu_axi_rdata[63:32]; + end + end + always @(posedge rvclkhdr_58_io_l1clk or posedge reset) begin + if (reset) begin + ic_miss_buff_data_12 <= 32'h0; + end else begin + ic_miss_buff_data_12 <= io_ifu_axi_rdata[31:0]; + end + end + always @(posedge rvclkhdr_58_io_l1clk or posedge reset) begin + if (reset) begin + ic_miss_buff_data_13 <= 32'h0; + end else begin + ic_miss_buff_data_13 <= io_ifu_axi_rdata[63:32]; + end + end + always @(posedge rvclkhdr_67_io_l1clk or posedge reset) begin + if (reset) begin + ic_miss_buff_data_14 <= 32'h0; + end else begin + ic_miss_buff_data_14 <= io_ifu_axi_rdata[31:0]; + end + end + always @(posedge rvclkhdr_67_io_l1clk or posedge reset) begin + if (reset) begin + ic_miss_buff_data_15 <= 32'h0; + end else begin + ic_miss_buff_data_15 <= io_ifu_axi_rdata[63:32]; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + ic_crit_wd_rdy_new_ff <= 1'h0; + end else begin + ic_crit_wd_rdy_new_ff <= _T_1509 | _T_1514; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + ic_miss_buff_data_error <= 8'h0; + end else begin + ic_miss_buff_data_error <= {_T_1393,ic_miss_buff_data_error_in_0}; + end + end + always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin + if (reset) begin + ic_debug_ict_array_sel_ff <= 1'h0; + end else begin + ic_debug_ict_array_sel_ff <= io_ic_debug_rd_en & io_ic_debug_tag_array; + end + end + always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_0 <= 1'h0; + end else if (_T_5591) begin + ic_tag_valid_out_1_0 <= _T_5103; + end + end + always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_1 <= 1'h0; + end else if (_T_5606) begin + ic_tag_valid_out_1_1 <= _T_5103; + end + end + always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_2 <= 1'h0; + end else if (_T_5621) begin + ic_tag_valid_out_1_2 <= _T_5103; + end + end + always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_3 <= 1'h0; + end else if (_T_5636) begin + ic_tag_valid_out_1_3 <= _T_5103; + end + end + always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_4 <= 1'h0; + end else if (_T_5651) begin + ic_tag_valid_out_1_4 <= _T_5103; + end + end + always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_5 <= 1'h0; + end else if (_T_5666) begin + ic_tag_valid_out_1_5 <= _T_5103; + end + end + always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_6 <= 1'h0; + end else if (_T_5681) begin + ic_tag_valid_out_1_6 <= _T_5103; + end + end + always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_7 <= 1'h0; + end else if (_T_5696) begin + ic_tag_valid_out_1_7 <= _T_5103; + end + end + always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_8 <= 1'h0; + end else if (_T_5711) begin + ic_tag_valid_out_1_8 <= _T_5103; + end + end + always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_9 <= 1'h0; + end else if (_T_5726) begin + ic_tag_valid_out_1_9 <= _T_5103; + end + end + always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_10 <= 1'h0; + end else if (_T_5741) begin + ic_tag_valid_out_1_10 <= _T_5103; + end + end + always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_11 <= 1'h0; + end else if (_T_5756) begin + ic_tag_valid_out_1_11 <= _T_5103; + end + end + always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_12 <= 1'h0; + end else if (_T_5771) begin + ic_tag_valid_out_1_12 <= _T_5103; + end + end + always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_13 <= 1'h0; + end else if (_T_5786) begin + ic_tag_valid_out_1_13 <= _T_5103; + end + end + always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_14 <= 1'h0; + end else if (_T_5801) begin + ic_tag_valid_out_1_14 <= _T_5103; + end + end + always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_15 <= 1'h0; + end else if (_T_5816) begin + ic_tag_valid_out_1_15 <= _T_5103; + end + end + always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_16 <= 1'h0; + end else if (_T_5831) begin + ic_tag_valid_out_1_16 <= _T_5103; + end + end + always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_17 <= 1'h0; + end else if (_T_5846) begin + ic_tag_valid_out_1_17 <= _T_5103; + end + end + always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_18 <= 1'h0; + end else if (_T_5861) begin + ic_tag_valid_out_1_18 <= _T_5103; + end + end + always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_19 <= 1'h0; + end else if (_T_5876) begin + ic_tag_valid_out_1_19 <= _T_5103; + end + end + always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_20 <= 1'h0; + end else if (_T_5891) begin + ic_tag_valid_out_1_20 <= _T_5103; + end + end + always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_21 <= 1'h0; + end else if (_T_5906) begin + ic_tag_valid_out_1_21 <= _T_5103; + end + end + always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_22 <= 1'h0; + end else if (_T_5921) begin + ic_tag_valid_out_1_22 <= _T_5103; + end + end + always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_23 <= 1'h0; + end else if (_T_5936) begin + ic_tag_valid_out_1_23 <= _T_5103; + end + end + always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_24 <= 1'h0; + end else if (_T_5951) begin + ic_tag_valid_out_1_24 <= _T_5103; + end + end + always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_25 <= 1'h0; + end else if (_T_5966) begin + ic_tag_valid_out_1_25 <= _T_5103; + end + end + always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_26 <= 1'h0; + end else if (_T_5981) begin + ic_tag_valid_out_1_26 <= _T_5103; + end + end + always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_27 <= 1'h0; + end else if (_T_5996) begin + ic_tag_valid_out_1_27 <= _T_5103; + end + end + always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_28 <= 1'h0; + end else if (_T_6011) begin + ic_tag_valid_out_1_28 <= _T_5103; + end + end + always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_29 <= 1'h0; + end else if (_T_6026) begin + ic_tag_valid_out_1_29 <= _T_5103; + end + end + always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_30 <= 1'h0; + end else if (_T_6041) begin + ic_tag_valid_out_1_30 <= _T_5103; + end + end + always @(posedge rvclkhdr_87_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_31 <= 1'h0; + end else if (_T_6056) begin + ic_tag_valid_out_1_31 <= _T_5103; + end + end + always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_32 <= 1'h0; + end else if (_T_6551) begin + ic_tag_valid_out_1_32 <= _T_5103; + end + end + always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_33 <= 1'h0; + end else if (_T_6566) begin + ic_tag_valid_out_1_33 <= _T_5103; + end + end + always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_34 <= 1'h0; + end else if (_T_6581) begin + ic_tag_valid_out_1_34 <= _T_5103; + end + end + always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_35 <= 1'h0; + end else if (_T_6596) begin + ic_tag_valid_out_1_35 <= _T_5103; + end + end + always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_36 <= 1'h0; + end else if (_T_6611) begin + ic_tag_valid_out_1_36 <= _T_5103; + end + end + always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_37 <= 1'h0; + end else if (_T_6626) begin + ic_tag_valid_out_1_37 <= _T_5103; + end + end + always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_38 <= 1'h0; + end else if (_T_6641) begin + ic_tag_valid_out_1_38 <= _T_5103; + end + end + always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_39 <= 1'h0; + end else if (_T_6656) begin + ic_tag_valid_out_1_39 <= _T_5103; + end + end + always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_40 <= 1'h0; + end else if (_T_6671) begin + ic_tag_valid_out_1_40 <= _T_5103; + end + end + always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_41 <= 1'h0; + end else if (_T_6686) begin + ic_tag_valid_out_1_41 <= _T_5103; + end + end + always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_42 <= 1'h0; + end else if (_T_6701) begin + ic_tag_valid_out_1_42 <= _T_5103; + end + end + always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_43 <= 1'h0; + end else if (_T_6716) begin + ic_tag_valid_out_1_43 <= _T_5103; + end + end + always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_44 <= 1'h0; + end else if (_T_6731) begin + ic_tag_valid_out_1_44 <= _T_5103; + end + end + always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_45 <= 1'h0; + end else if (_T_6746) begin + ic_tag_valid_out_1_45 <= _T_5103; + end + end + always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_46 <= 1'h0; + end else if (_T_6761) begin + ic_tag_valid_out_1_46 <= _T_5103; + end + end + always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_47 <= 1'h0; + end else if (_T_6776) begin + ic_tag_valid_out_1_47 <= _T_5103; + end + end + always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_48 <= 1'h0; + end else if (_T_6791) begin + ic_tag_valid_out_1_48 <= _T_5103; + end + end + always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_49 <= 1'h0; + end else if (_T_6806) begin + ic_tag_valid_out_1_49 <= _T_5103; + end + end + always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_50 <= 1'h0; + end else if (_T_6821) begin + ic_tag_valid_out_1_50 <= _T_5103; + end + end + always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_51 <= 1'h0; + end else if (_T_6836) begin + ic_tag_valid_out_1_51 <= _T_5103; + end + end + always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_52 <= 1'h0; + end else if (_T_6851) begin + ic_tag_valid_out_1_52 <= _T_5103; + end + end + always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_53 <= 1'h0; + end else if (_T_6866) begin + ic_tag_valid_out_1_53 <= _T_5103; + end + end + always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_54 <= 1'h0; + end else if (_T_6881) begin + ic_tag_valid_out_1_54 <= _T_5103; + end + end + always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_55 <= 1'h0; + end else if (_T_6896) begin + ic_tag_valid_out_1_55 <= _T_5103; + end + end + always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_56 <= 1'h0; + end else if (_T_6911) begin + ic_tag_valid_out_1_56 <= _T_5103; + end + end + always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_57 <= 1'h0; + end else if (_T_6926) begin + ic_tag_valid_out_1_57 <= _T_5103; + end + end + always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_58 <= 1'h0; + end else if (_T_6941) begin + ic_tag_valid_out_1_58 <= _T_5103; + end + end + always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_59 <= 1'h0; + end else if (_T_6956) begin + ic_tag_valid_out_1_59 <= _T_5103; + end + end + always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_60 <= 1'h0; + end else if (_T_6971) begin + ic_tag_valid_out_1_60 <= _T_5103; + end + end + always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_61 <= 1'h0; + end else if (_T_6986) begin + ic_tag_valid_out_1_61 <= _T_5103; + end + end + always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_62 <= 1'h0; + end else if (_T_7001) begin + ic_tag_valid_out_1_62 <= _T_5103; + end + end + always @(posedge rvclkhdr_89_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_63 <= 1'h0; + end else if (_T_7016) begin + ic_tag_valid_out_1_63 <= _T_5103; + end + end + always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_64 <= 1'h0; + end else if (_T_7511) begin + ic_tag_valid_out_1_64 <= _T_5103; + end + end + always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_65 <= 1'h0; + end else if (_T_7526) begin + ic_tag_valid_out_1_65 <= _T_5103; + end + end + always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_66 <= 1'h0; + end else if (_T_7541) begin + ic_tag_valid_out_1_66 <= _T_5103; + end + end + always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_67 <= 1'h0; + end else if (_T_7556) begin + ic_tag_valid_out_1_67 <= _T_5103; + end + end + always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_68 <= 1'h0; + end else if (_T_7571) begin + ic_tag_valid_out_1_68 <= _T_5103; + end + end + always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_69 <= 1'h0; + end else if (_T_7586) begin + ic_tag_valid_out_1_69 <= _T_5103; + end + end + always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_70 <= 1'h0; + end else if (_T_7601) begin + ic_tag_valid_out_1_70 <= _T_5103; + end + end + always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_71 <= 1'h0; + end else if (_T_7616) begin + ic_tag_valid_out_1_71 <= _T_5103; + end + end + always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_72 <= 1'h0; + end else if (_T_7631) begin + ic_tag_valid_out_1_72 <= _T_5103; + end + end + always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_73 <= 1'h0; + end else if (_T_7646) begin + ic_tag_valid_out_1_73 <= _T_5103; + end + end + always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_74 <= 1'h0; + end else if (_T_7661) begin + ic_tag_valid_out_1_74 <= _T_5103; + end + end + always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_75 <= 1'h0; + end else if (_T_7676) begin + ic_tag_valid_out_1_75 <= _T_5103; + end + end + always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_76 <= 1'h0; + end else if (_T_7691) begin + ic_tag_valid_out_1_76 <= _T_5103; + end + end + always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_77 <= 1'h0; + end else if (_T_7706) begin + ic_tag_valid_out_1_77 <= _T_5103; + end + end + always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_78 <= 1'h0; + end else if (_T_7721) begin + ic_tag_valid_out_1_78 <= _T_5103; + end + end + always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_79 <= 1'h0; + end else if (_T_7736) begin + ic_tag_valid_out_1_79 <= _T_5103; + end + end + always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_80 <= 1'h0; + end else if (_T_7751) begin + ic_tag_valid_out_1_80 <= _T_5103; + end + end + always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_81 <= 1'h0; + end else if (_T_7766) begin + ic_tag_valid_out_1_81 <= _T_5103; + end + end + always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_82 <= 1'h0; + end else if (_T_7781) begin + ic_tag_valid_out_1_82 <= _T_5103; + end + end + always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_83 <= 1'h0; + end else if (_T_7796) begin + ic_tag_valid_out_1_83 <= _T_5103; + end + end + always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_84 <= 1'h0; + end else if (_T_7811) begin + ic_tag_valid_out_1_84 <= _T_5103; + end + end + always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_85 <= 1'h0; + end else if (_T_7826) begin + ic_tag_valid_out_1_85 <= _T_5103; + end + end + always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_86 <= 1'h0; + end else if (_T_7841) begin + ic_tag_valid_out_1_86 <= _T_5103; + end + end + always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_87 <= 1'h0; + end else if (_T_7856) begin + ic_tag_valid_out_1_87 <= _T_5103; + end + end + always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_88 <= 1'h0; + end else if (_T_7871) begin + ic_tag_valid_out_1_88 <= _T_5103; + end + end + always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_89 <= 1'h0; + end else if (_T_7886) begin + ic_tag_valid_out_1_89 <= _T_5103; + end + end + always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_90 <= 1'h0; + end else if (_T_7901) begin + ic_tag_valid_out_1_90 <= _T_5103; + end + end + always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_91 <= 1'h0; + end else if (_T_7916) begin + ic_tag_valid_out_1_91 <= _T_5103; + end + end + always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_92 <= 1'h0; + end else if (_T_7931) begin + ic_tag_valid_out_1_92 <= _T_5103; + end + end + always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_93 <= 1'h0; + end else if (_T_7946) begin + ic_tag_valid_out_1_93 <= _T_5103; + end + end + always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_94 <= 1'h0; + end else if (_T_7961) begin + ic_tag_valid_out_1_94 <= _T_5103; + end + end + always @(posedge rvclkhdr_91_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_95 <= 1'h0; + end else if (_T_7976) begin + ic_tag_valid_out_1_95 <= _T_5103; + end + end + always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_96 <= 1'h0; + end else if (_T_8471) begin + ic_tag_valid_out_1_96 <= _T_5103; + end + end + always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_97 <= 1'h0; + end else if (_T_8486) begin + ic_tag_valid_out_1_97 <= _T_5103; + end + end + always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_98 <= 1'h0; + end else if (_T_8501) begin + ic_tag_valid_out_1_98 <= _T_5103; + end + end + always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_99 <= 1'h0; + end else if (_T_8516) begin + ic_tag_valid_out_1_99 <= _T_5103; + end + end + always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_100 <= 1'h0; + end else if (_T_8531) begin + ic_tag_valid_out_1_100 <= _T_5103; + end + end + always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_101 <= 1'h0; + end else if (_T_8546) begin + ic_tag_valid_out_1_101 <= _T_5103; + end + end + always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_102 <= 1'h0; + end else if (_T_8561) begin + ic_tag_valid_out_1_102 <= _T_5103; + end + end + always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_103 <= 1'h0; + end else if (_T_8576) begin + ic_tag_valid_out_1_103 <= _T_5103; + end + end + always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_104 <= 1'h0; + end else if (_T_8591) begin + ic_tag_valid_out_1_104 <= _T_5103; + end + end + always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_105 <= 1'h0; + end else if (_T_8606) begin + ic_tag_valid_out_1_105 <= _T_5103; + end + end + always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_106 <= 1'h0; + end else if (_T_8621) begin + ic_tag_valid_out_1_106 <= _T_5103; + end + end + always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_107 <= 1'h0; + end else if (_T_8636) begin + ic_tag_valid_out_1_107 <= _T_5103; + end + end + always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_108 <= 1'h0; + end else if (_T_8651) begin + ic_tag_valid_out_1_108 <= _T_5103; + end + end + always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_109 <= 1'h0; + end else if (_T_8666) begin + ic_tag_valid_out_1_109 <= _T_5103; + end + end + always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_110 <= 1'h0; + end else if (_T_8681) begin + ic_tag_valid_out_1_110 <= _T_5103; + end + end + always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_111 <= 1'h0; + end else if (_T_8696) begin + ic_tag_valid_out_1_111 <= _T_5103; + end + end + always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_112 <= 1'h0; + end else if (_T_8711) begin + ic_tag_valid_out_1_112 <= _T_5103; + end + end + always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_113 <= 1'h0; + end else if (_T_8726) begin + ic_tag_valid_out_1_113 <= _T_5103; + end + end + always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_114 <= 1'h0; + end else if (_T_8741) begin + ic_tag_valid_out_1_114 <= _T_5103; + end + end + always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_115 <= 1'h0; + end else if (_T_8756) begin + ic_tag_valid_out_1_115 <= _T_5103; + end + end + always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_116 <= 1'h0; + end else if (_T_8771) begin + ic_tag_valid_out_1_116 <= _T_5103; + end + end + always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_117 <= 1'h0; + end else if (_T_8786) begin + ic_tag_valid_out_1_117 <= _T_5103; + end + end + always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_118 <= 1'h0; + end else if (_T_8801) begin + ic_tag_valid_out_1_118 <= _T_5103; + end + end + always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_119 <= 1'h0; + end else if (_T_8816) begin + ic_tag_valid_out_1_119 <= _T_5103; + end + end + always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_120 <= 1'h0; + end else if (_T_8831) begin + ic_tag_valid_out_1_120 <= _T_5103; + end + end + always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_121 <= 1'h0; + end else if (_T_8846) begin + ic_tag_valid_out_1_121 <= _T_5103; + end + end + always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_122 <= 1'h0; + end else if (_T_8861) begin + ic_tag_valid_out_1_122 <= _T_5103; + end + end + always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_123 <= 1'h0; + end else if (_T_8876) begin + ic_tag_valid_out_1_123 <= _T_5103; + end + end + always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_124 <= 1'h0; + end else if (_T_8891) begin + ic_tag_valid_out_1_124 <= _T_5103; + end + end + always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_125 <= 1'h0; + end else if (_T_8906) begin + ic_tag_valid_out_1_125 <= _T_5103; + end + end + always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_126 <= 1'h0; + end else if (_T_8921) begin + ic_tag_valid_out_1_126 <= _T_5103; + end + end + always @(posedge rvclkhdr_93_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_1_127 <= 1'h0; + end else if (_T_8936) begin + ic_tag_valid_out_1_127 <= _T_5103; + end + end + always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_0 <= 1'h0; + end else if (_T_5111) begin + ic_tag_valid_out_0_0 <= _T_5103; + end + end + always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_1 <= 1'h0; + end else if (_T_5126) begin + ic_tag_valid_out_0_1 <= _T_5103; + end + end + always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_2 <= 1'h0; + end else if (_T_5141) begin + ic_tag_valid_out_0_2 <= _T_5103; + end + end + always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_3 <= 1'h0; + end else if (_T_5156) begin + ic_tag_valid_out_0_3 <= _T_5103; + end + end + always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_4 <= 1'h0; + end else if (_T_5171) begin + ic_tag_valid_out_0_4 <= _T_5103; + end + end + always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_5 <= 1'h0; + end else if (_T_5186) begin + ic_tag_valid_out_0_5 <= _T_5103; + end + end + always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_6 <= 1'h0; + end else if (_T_5201) begin + ic_tag_valid_out_0_6 <= _T_5103; + end + end + always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_7 <= 1'h0; + end else if (_T_5216) begin + ic_tag_valid_out_0_7 <= _T_5103; + end + end + always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_8 <= 1'h0; + end else if (_T_5231) begin + ic_tag_valid_out_0_8 <= _T_5103; + end + end + always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_9 <= 1'h0; + end else if (_T_5246) begin + ic_tag_valid_out_0_9 <= _T_5103; + end + end + always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_10 <= 1'h0; + end else if (_T_5261) begin + ic_tag_valid_out_0_10 <= _T_5103; + end + end + always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_11 <= 1'h0; + end else if (_T_5276) begin + ic_tag_valid_out_0_11 <= _T_5103; + end + end + always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_12 <= 1'h0; + end else if (_T_5291) begin + ic_tag_valid_out_0_12 <= _T_5103; + end + end + always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_13 <= 1'h0; + end else if (_T_5306) begin + ic_tag_valid_out_0_13 <= _T_5103; + end + end + always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_14 <= 1'h0; + end else if (_T_5321) begin + ic_tag_valid_out_0_14 <= _T_5103; + end + end + always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_15 <= 1'h0; + end else if (_T_5336) begin + ic_tag_valid_out_0_15 <= _T_5103; + end + end + always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_16 <= 1'h0; + end else if (_T_5351) begin + ic_tag_valid_out_0_16 <= _T_5103; + end + end + always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_17 <= 1'h0; + end else if (_T_5366) begin + ic_tag_valid_out_0_17 <= _T_5103; + end + end + always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_18 <= 1'h0; + end else if (_T_5381) begin + ic_tag_valid_out_0_18 <= _T_5103; + end + end + always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_19 <= 1'h0; + end else if (_T_5396) begin + ic_tag_valid_out_0_19 <= _T_5103; + end + end + always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_20 <= 1'h0; + end else if (_T_5411) begin + ic_tag_valid_out_0_20 <= _T_5103; + end + end + always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_21 <= 1'h0; + end else if (_T_5426) begin + ic_tag_valid_out_0_21 <= _T_5103; + end + end + always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_22 <= 1'h0; + end else if (_T_5441) begin + ic_tag_valid_out_0_22 <= _T_5103; + end + end + always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_23 <= 1'h0; + end else if (_T_5456) begin + ic_tag_valid_out_0_23 <= _T_5103; + end + end + always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_24 <= 1'h0; + end else if (_T_5471) begin + ic_tag_valid_out_0_24 <= _T_5103; + end + end + always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_25 <= 1'h0; + end else if (_T_5486) begin + ic_tag_valid_out_0_25 <= _T_5103; + end + end + always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_26 <= 1'h0; + end else if (_T_5501) begin + ic_tag_valid_out_0_26 <= _T_5103; + end + end + always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_27 <= 1'h0; + end else if (_T_5516) begin + ic_tag_valid_out_0_27 <= _T_5103; + end + end + always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_28 <= 1'h0; + end else if (_T_5531) begin + ic_tag_valid_out_0_28 <= _T_5103; + end + end + always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_29 <= 1'h0; + end else if (_T_5546) begin + ic_tag_valid_out_0_29 <= _T_5103; + end + end + always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_30 <= 1'h0; + end else if (_T_5561) begin + ic_tag_valid_out_0_30 <= _T_5103; + end + end + always @(posedge rvclkhdr_86_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_31 <= 1'h0; + end else if (_T_5576) begin + ic_tag_valid_out_0_31 <= _T_5103; + end + end + always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_32 <= 1'h0; + end else if (_T_6071) begin + ic_tag_valid_out_0_32 <= _T_5103; + end + end + always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_33 <= 1'h0; + end else if (_T_6086) begin + ic_tag_valid_out_0_33 <= _T_5103; + end + end + always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_34 <= 1'h0; + end else if (_T_6101) begin + ic_tag_valid_out_0_34 <= _T_5103; + end + end + always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_35 <= 1'h0; + end else if (_T_6116) begin + ic_tag_valid_out_0_35 <= _T_5103; + end + end + always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_36 <= 1'h0; + end else if (_T_6131) begin + ic_tag_valid_out_0_36 <= _T_5103; + end + end + always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_37 <= 1'h0; + end else if (_T_6146) begin + ic_tag_valid_out_0_37 <= _T_5103; + end + end + always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_38 <= 1'h0; + end else if (_T_6161) begin + ic_tag_valid_out_0_38 <= _T_5103; + end + end + always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_39 <= 1'h0; + end else if (_T_6176) begin + ic_tag_valid_out_0_39 <= _T_5103; + end + end + always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_40 <= 1'h0; + end else if (_T_6191) begin + ic_tag_valid_out_0_40 <= _T_5103; + end + end + always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_41 <= 1'h0; + end else if (_T_6206) begin + ic_tag_valid_out_0_41 <= _T_5103; + end + end + always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_42 <= 1'h0; + end else if (_T_6221) begin + ic_tag_valid_out_0_42 <= _T_5103; + end + end + always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_43 <= 1'h0; + end else if (_T_6236) begin + ic_tag_valid_out_0_43 <= _T_5103; + end + end + always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_44 <= 1'h0; + end else if (_T_6251) begin + ic_tag_valid_out_0_44 <= _T_5103; + end + end + always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_45 <= 1'h0; + end else if (_T_6266) begin + ic_tag_valid_out_0_45 <= _T_5103; + end + end + always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_46 <= 1'h0; + end else if (_T_6281) begin + ic_tag_valid_out_0_46 <= _T_5103; + end + end + always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_47 <= 1'h0; + end else if (_T_6296) begin + ic_tag_valid_out_0_47 <= _T_5103; + end + end + always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_48 <= 1'h0; + end else if (_T_6311) begin + ic_tag_valid_out_0_48 <= _T_5103; + end + end + always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_49 <= 1'h0; + end else if (_T_6326) begin + ic_tag_valid_out_0_49 <= _T_5103; + end + end + always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_50 <= 1'h0; + end else if (_T_6341) begin + ic_tag_valid_out_0_50 <= _T_5103; + end + end + always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_51 <= 1'h0; + end else if (_T_6356) begin + ic_tag_valid_out_0_51 <= _T_5103; + end + end + always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_52 <= 1'h0; + end else if (_T_6371) begin + ic_tag_valid_out_0_52 <= _T_5103; + end + end + always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_53 <= 1'h0; + end else if (_T_6386) begin + ic_tag_valid_out_0_53 <= _T_5103; + end + end + always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_54 <= 1'h0; + end else if (_T_6401) begin + ic_tag_valid_out_0_54 <= _T_5103; + end + end + always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_55 <= 1'h0; + end else if (_T_6416) begin + ic_tag_valid_out_0_55 <= _T_5103; + end + end + always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_56 <= 1'h0; + end else if (_T_6431) begin + ic_tag_valid_out_0_56 <= _T_5103; + end + end + always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_57 <= 1'h0; + end else if (_T_6446) begin + ic_tag_valid_out_0_57 <= _T_5103; + end + end + always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_58 <= 1'h0; + end else if (_T_6461) begin + ic_tag_valid_out_0_58 <= _T_5103; + end + end + always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_59 <= 1'h0; + end else if (_T_6476) begin + ic_tag_valid_out_0_59 <= _T_5103; + end + end + always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_60 <= 1'h0; + end else if (_T_6491) begin + ic_tag_valid_out_0_60 <= _T_5103; + end + end + always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_61 <= 1'h0; + end else if (_T_6506) begin + ic_tag_valid_out_0_61 <= _T_5103; + end + end + always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_62 <= 1'h0; + end else if (_T_6521) begin + ic_tag_valid_out_0_62 <= _T_5103; + end + end + always @(posedge rvclkhdr_88_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_63 <= 1'h0; + end else if (_T_6536) begin + ic_tag_valid_out_0_63 <= _T_5103; + end + end + always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_64 <= 1'h0; + end else if (_T_7031) begin + ic_tag_valid_out_0_64 <= _T_5103; + end + end + always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_65 <= 1'h0; + end else if (_T_7046) begin + ic_tag_valid_out_0_65 <= _T_5103; + end + end + always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_66 <= 1'h0; + end else if (_T_7061) begin + ic_tag_valid_out_0_66 <= _T_5103; + end + end + always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_67 <= 1'h0; + end else if (_T_7076) begin + ic_tag_valid_out_0_67 <= _T_5103; + end + end + always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_68 <= 1'h0; + end else if (_T_7091) begin + ic_tag_valid_out_0_68 <= _T_5103; + end + end + always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_69 <= 1'h0; + end else if (_T_7106) begin + ic_tag_valid_out_0_69 <= _T_5103; + end + end + always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_70 <= 1'h0; + end else if (_T_7121) begin + ic_tag_valid_out_0_70 <= _T_5103; + end + end + always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_71 <= 1'h0; + end else if (_T_7136) begin + ic_tag_valid_out_0_71 <= _T_5103; + end + end + always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_72 <= 1'h0; + end else if (_T_7151) begin + ic_tag_valid_out_0_72 <= _T_5103; + end + end + always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_73 <= 1'h0; + end else if (_T_7166) begin + ic_tag_valid_out_0_73 <= _T_5103; + end + end + always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_74 <= 1'h0; + end else if (_T_7181) begin + ic_tag_valid_out_0_74 <= _T_5103; + end + end + always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_75 <= 1'h0; + end else if (_T_7196) begin + ic_tag_valid_out_0_75 <= _T_5103; + end + end + always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_76 <= 1'h0; + end else if (_T_7211) begin + ic_tag_valid_out_0_76 <= _T_5103; + end + end + always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_77 <= 1'h0; + end else if (_T_7226) begin + ic_tag_valid_out_0_77 <= _T_5103; + end + end + always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_78 <= 1'h0; + end else if (_T_7241) begin + ic_tag_valid_out_0_78 <= _T_5103; + end + end + always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_79 <= 1'h0; + end else if (_T_7256) begin + ic_tag_valid_out_0_79 <= _T_5103; + end + end + always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_80 <= 1'h0; + end else if (_T_7271) begin + ic_tag_valid_out_0_80 <= _T_5103; + end + end + always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_81 <= 1'h0; + end else if (_T_7286) begin + ic_tag_valid_out_0_81 <= _T_5103; + end + end + always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_82 <= 1'h0; + end else if (_T_7301) begin + ic_tag_valid_out_0_82 <= _T_5103; + end + end + always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_83 <= 1'h0; + end else if (_T_7316) begin + ic_tag_valid_out_0_83 <= _T_5103; + end + end + always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_84 <= 1'h0; + end else if (_T_7331) begin + ic_tag_valid_out_0_84 <= _T_5103; + end + end + always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_85 <= 1'h0; + end else if (_T_7346) begin + ic_tag_valid_out_0_85 <= _T_5103; + end + end + always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_86 <= 1'h0; + end else if (_T_7361) begin + ic_tag_valid_out_0_86 <= _T_5103; + end + end + always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_87 <= 1'h0; + end else if (_T_7376) begin + ic_tag_valid_out_0_87 <= _T_5103; + end + end + always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_88 <= 1'h0; + end else if (_T_7391) begin + ic_tag_valid_out_0_88 <= _T_5103; + end + end + always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_89 <= 1'h0; + end else if (_T_7406) begin + ic_tag_valid_out_0_89 <= _T_5103; + end + end + always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_90 <= 1'h0; + end else if (_T_7421) begin + ic_tag_valid_out_0_90 <= _T_5103; + end + end + always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_91 <= 1'h0; + end else if (_T_7436) begin + ic_tag_valid_out_0_91 <= _T_5103; + end + end + always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_92 <= 1'h0; + end else if (_T_7451) begin + ic_tag_valid_out_0_92 <= _T_5103; + end + end + always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_93 <= 1'h0; + end else if (_T_7466) begin + ic_tag_valid_out_0_93 <= _T_5103; + end + end + always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_94 <= 1'h0; + end else if (_T_7481) begin + ic_tag_valid_out_0_94 <= _T_5103; + end + end + always @(posedge rvclkhdr_90_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_95 <= 1'h0; + end else if (_T_7496) begin + ic_tag_valid_out_0_95 <= _T_5103; + end + end + always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_96 <= 1'h0; + end else if (_T_7991) begin + ic_tag_valid_out_0_96 <= _T_5103; + end + end + always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_97 <= 1'h0; + end else if (_T_8006) begin + ic_tag_valid_out_0_97 <= _T_5103; + end + end + always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_98 <= 1'h0; + end else if (_T_8021) begin + ic_tag_valid_out_0_98 <= _T_5103; + end + end + always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_99 <= 1'h0; + end else if (_T_8036) begin + ic_tag_valid_out_0_99 <= _T_5103; + end + end + always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_100 <= 1'h0; + end else if (_T_8051) begin + ic_tag_valid_out_0_100 <= _T_5103; + end + end + always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_101 <= 1'h0; + end else if (_T_8066) begin + ic_tag_valid_out_0_101 <= _T_5103; + end + end + always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_102 <= 1'h0; + end else if (_T_8081) begin + ic_tag_valid_out_0_102 <= _T_5103; + end + end + always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_103 <= 1'h0; + end else if (_T_8096) begin + ic_tag_valid_out_0_103 <= _T_5103; + end + end + always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_104 <= 1'h0; + end else if (_T_8111) begin + ic_tag_valid_out_0_104 <= _T_5103; + end + end + always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_105 <= 1'h0; + end else if (_T_8126) begin + ic_tag_valid_out_0_105 <= _T_5103; + end + end + always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_106 <= 1'h0; + end else if (_T_8141) begin + ic_tag_valid_out_0_106 <= _T_5103; + end + end + always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_107 <= 1'h0; + end else if (_T_8156) begin + ic_tag_valid_out_0_107 <= _T_5103; + end + end + always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_108 <= 1'h0; + end else if (_T_8171) begin + ic_tag_valid_out_0_108 <= _T_5103; + end + end + always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_109 <= 1'h0; + end else if (_T_8186) begin + ic_tag_valid_out_0_109 <= _T_5103; + end + end + always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_110 <= 1'h0; + end else if (_T_8201) begin + ic_tag_valid_out_0_110 <= _T_5103; + end + end + always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_111 <= 1'h0; + end else if (_T_8216) begin + ic_tag_valid_out_0_111 <= _T_5103; + end + end + always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_112 <= 1'h0; + end else if (_T_8231) begin + ic_tag_valid_out_0_112 <= _T_5103; + end + end + always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_113 <= 1'h0; + end else if (_T_8246) begin + ic_tag_valid_out_0_113 <= _T_5103; + end + end + always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_114 <= 1'h0; + end else if (_T_8261) begin + ic_tag_valid_out_0_114 <= _T_5103; + end + end + always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_115 <= 1'h0; + end else if (_T_8276) begin + ic_tag_valid_out_0_115 <= _T_5103; + end + end + always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_116 <= 1'h0; + end else if (_T_8291) begin + ic_tag_valid_out_0_116 <= _T_5103; + end + end + always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_117 <= 1'h0; + end else if (_T_8306) begin + ic_tag_valid_out_0_117 <= _T_5103; + end + end + always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_118 <= 1'h0; + end else if (_T_8321) begin + ic_tag_valid_out_0_118 <= _T_5103; + end + end + always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_119 <= 1'h0; + end else if (_T_8336) begin + ic_tag_valid_out_0_119 <= _T_5103; + end + end + always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_120 <= 1'h0; + end else if (_T_8351) begin + ic_tag_valid_out_0_120 <= _T_5103; + end + end + always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_121 <= 1'h0; + end else if (_T_8366) begin + ic_tag_valid_out_0_121 <= _T_5103; + end + end + always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_122 <= 1'h0; + end else if (_T_8381) begin + ic_tag_valid_out_0_122 <= _T_5103; + end + end + always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_123 <= 1'h0; + end else if (_T_8396) begin + ic_tag_valid_out_0_123 <= _T_5103; + end + end + always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_124 <= 1'h0; + end else if (_T_8411) begin + ic_tag_valid_out_0_124 <= _T_5103; + end + end + always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_125 <= 1'h0; + end else if (_T_8426) begin + ic_tag_valid_out_0_125 <= _T_5103; + end + end + always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_126 <= 1'h0; + end else if (_T_8441) begin + ic_tag_valid_out_0_126 <= _T_5103; + end + end + always @(posedge rvclkhdr_92_io_l1clk or posedge reset) begin + if (reset) begin + ic_tag_valid_out_0_127 <= 1'h0; + end else if (_T_8456) begin + ic_tag_valid_out_0_127 <= _T_5103; + end + end + always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin + if (reset) begin + ic_debug_way_ff <= 2'h0; + end else begin + ic_debug_way_ff <= io_ic_debug_way; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + ic_debug_rd_en_ff <= 1'h0; + end else begin + ic_debug_rd_en_ff <= io_ic_debug_rd_en; + end + end + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin + if (reset) begin + _T_1211 <= 71'h0; + end else if (ic_debug_ict_array_sel_ff) begin + _T_1211 <= _T_1210; + end else begin + _T_1211 <= io_ic_debug_rd_data; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + ifc_region_acc_fault_memory_f <= 1'h0; + end else begin + ifc_region_acc_fault_memory_f <= _T_9835 & io_ifc_fetch_req_bf; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + perr_ic_index_ff <= 7'h0; + end else if (perr_sb_write_status) begin + perr_ic_index_ff <= ifu_ic_rw_int_addr_ff; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + dma_sb_err_state_ff <= 1'h0; + end else begin + dma_sb_err_state_ff <= perr_state == 3'h4; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + bus_cmd_req_hold <= 1'h0; + end else begin + bus_cmd_req_hold <= _T_2555 & _T_2574; + end + end + always @(posedge rvclkhdr_69_io_l1clk or posedge reset) begin + if (reset) begin + ifu_bus_cmd_valid <= 1'h0; + end else begin + ifu_bus_cmd_valid <= _T_2545 & _T_2551; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + bus_cmd_beat_count <= 3'h0; + end else if (bus_cmd_beat_en) begin + bus_cmd_beat_count <= bus_new_cmd_beat_count; + end + end + always @(posedge rvclkhdr_68_io_l1clk or posedge reset) begin + if (reset) begin + ifu_bus_arready_unq_ff <= 1'h0; + end else begin + ifu_bus_arready_unq_ff <= io_ifu_axi_arready; + end + end + always @(posedge rvclkhdr_68_io_l1clk or posedge reset) begin + if (reset) begin + ifu_bus_arvalid_ff <= 1'h0; + end else begin + ifu_bus_arvalid_ff <= io_ifu_axi_arvalid; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + ifc_dma_access_ok_prev <= 1'h0; + end else begin + ifc_dma_access_ok_prev <= _T_2650 & _T_2651; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + iccm_ecc_corr_data_ff <= 39'h0; + end else if (iccm_ecc_write_status) begin + iccm_ecc_corr_data_ff <= _T_3881; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + dma_mem_addr_ff <= 2'h0; + end else begin + dma_mem_addr_ff <= io_dma_mem_addr[3:2]; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + dma_mem_tag_ff <= 3'h0; + end else begin + dma_mem_tag_ff <= io_dma_mem_tag; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + iccm_dma_rtag_temp <= 3'h0; + end else begin + iccm_dma_rtag_temp <= dma_mem_tag_ff; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + iccm_dma_rvalid_temp <= 1'h0; + end else begin + iccm_dma_rvalid_temp <= iccm_dma_rvalid_in; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + iccm_dma_ecc_error <= 1'h0; + end else begin + iccm_dma_ecc_error <= |iccm_double_ecc_error; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + iccm_dma_rdata_temp <= 64'h0; + end else if (iccm_dma_ecc_error_in) begin + iccm_dma_rdata_temp <= _T_3055; + end else begin + iccm_dma_rdata_temp <= _T_3056; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + iccm_ecc_corr_index_ff <= 14'h0; + end else if (iccm_ecc_write_status) begin + if (iccm_single_ecc_error[0]) begin + iccm_ecc_corr_index_ff <= iccm_rw_addr_f; + end else begin + iccm_ecc_corr_index_ff <= _T_3877; + end + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + iccm_rd_ecc_single_err_ff <= 1'h0; + end else begin + iccm_rd_ecc_single_err_ff <= _T_3872 & _T_319; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + iccm_rw_addr_f <= 14'h0; + end else begin + iccm_rw_addr_f <= io_iccm_rw_addr[14:1]; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + ifu_status_wr_addr_ff <= 7'h0; + end else if (_T_3946) begin + ifu_status_wr_addr_ff <= io_ic_debug_addr[9:3]; + end else begin + ifu_status_wr_addr_ff <= ifu_status_wr_addr[11:5]; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + way_status_wr_en_ff <= 1'h0; + end else begin + way_status_wr_en_ff <= way_status_wr_en | _T_3949; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + way_status_new_ff <= 1'h0; + end else if (_T_3949) begin + way_status_new_ff <= io_ic_debug_wr_data[4]; + end else if (_T_9726) begin + way_status_new_ff <= replace_way_mb_any_0; + end else begin + way_status_new_ff <= way_status_hit_new; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + ifu_tag_wren_ff <= 2'h0; + end else begin + ifu_tag_wren_ff <= ifu_tag_wren | ic_debug_tag_wr_en; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + ic_valid_ff <= 1'h0; + end else if (_T_3949) begin + ic_valid_ff <= io_ic_debug_wr_data[0]; + end else begin + ic_valid_ff <= ic_valid; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + _T_9748 <= 1'h0; + end else begin + _T_9748 <= _T_233 & _T_209; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + _T_9749 <= 1'h0; + end else begin + _T_9749 <= _T_225 & _T_247; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + _T_9750 <= 1'h0; + end else begin + _T_9750 <= ic_byp_hit_f & ifu_byp_data_err_new; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + _T_9754 <= 1'h0; + end else begin + _T_9754 <= _T_9752 & miss_pending; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + _T_9755 <= 1'h0; + end else begin + _T_9755 <= _T_2569 & _T_2574; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + _T_9776 <= 1'h0; + end else if (ic_debug_rd_en_ff) begin + _T_9776 <= ic_debug_rd_en_ff; + end + end +endmodule diff --git a/el2_lsu.fir b/el2_lsu.fir index 27c949d2..727c35c8 100644 --- a/el2_lsu.fir +++ b/el2_lsu.fir @@ -15374,7 +15374,7 @@ circuit el2_lsu : dccm_ctl.io.lsu_c2_r_clk <= clkdomain.io.lsu_c2_m_clk @[el2_lsu.scala 241:46] dccm_ctl.io.lsu_free_c2_clk <= clkdomain.io.lsu_c2_r_clk @[el2_lsu.scala 242:46] dccm_ctl.io.lsu_c1_r_clk <= clkdomain.io.lsu_free_c2_clk @[el2_lsu.scala 243:46] - dccm_ctl.io.lsu_store_c1_r_clk <= clkdomain.io.lsu_c1_r_clk @[el2_lsu.scala 244:46] + dccm_ctl.io.lsu_store_c1_r_clk <= clkdomain.io.lsu_store_c1_r_clk @[el2_lsu.scala 244:46] dccm_ctl.io.lsu_pkt_d.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_d.bits.store_data_bypass_m @[el2_lsu.scala 246:46] dccm_ctl.io.lsu_pkt_d.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_d.bits.load_ldst_bypass_d @[el2_lsu.scala 246:46] dccm_ctl.io.lsu_pkt_d.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_d.bits.store_data_bypass_d @[el2_lsu.scala 246:46] diff --git a/el2_lsu.v b/el2_lsu.v index 6512bdc2..b521c6b5 100644 --- a/el2_lsu.v +++ b/el2_lsu.v @@ -4825,6 +4825,7 @@ module el2_lsu_clkdomain( output io_lsu_c2_m_clk, output io_lsu_c2_r_clk, output io_lsu_store_c1_m_clk, + output io_lsu_store_c1_r_clk, output io_lsu_stbuf_c1_clk, output io_lsu_bus_obuf_c1_clk, output io_lsu_bus_ibuf_c1_clk, @@ -4991,6 +4992,7 @@ module el2_lsu_clkdomain( assign io_lsu_c2_m_clk = rvclkhdr_2_io_l1clk; // @[el2_lsu_clkdomain.scala 88:26] assign io_lsu_c2_r_clk = rvclkhdr_3_io_l1clk; // @[el2_lsu_clkdomain.scala 89:26] assign io_lsu_store_c1_m_clk = rvclkhdr_4_io_l1clk; // @[el2_lsu_clkdomain.scala 90:26] + assign io_lsu_store_c1_r_clk = rvclkhdr_5_io_l1clk; // @[el2_lsu_clkdomain.scala 91:26] assign io_lsu_stbuf_c1_clk = rvclkhdr_6_io_l1clk; // @[el2_lsu_clkdomain.scala 92:26] assign io_lsu_bus_obuf_c1_clk = rvclkhdr_8_io_l1clk; // @[el2_lsu_clkdomain.scala 94:26] assign io_lsu_bus_ibuf_c1_clk = rvclkhdr_7_io_l1clk; // @[el2_lsu_clkdomain.scala 93:26] @@ -10840,6 +10842,7 @@ module el2_lsu( wire clkdomain_io_lsu_c2_m_clk; // @[el2_lsu.scala 161:30] wire clkdomain_io_lsu_c2_r_clk; // @[el2_lsu.scala 161:30] wire clkdomain_io_lsu_store_c1_m_clk; // @[el2_lsu.scala 161:30] + wire clkdomain_io_lsu_store_c1_r_clk; // @[el2_lsu.scala 161:30] wire clkdomain_io_lsu_stbuf_c1_clk; // @[el2_lsu.scala 161:30] wire clkdomain_io_lsu_bus_obuf_c1_clk; // @[el2_lsu.scala 161:30] wire clkdomain_io_lsu_bus_ibuf_c1_clk; // @[el2_lsu.scala 161:30] @@ -11324,6 +11327,7 @@ module el2_lsu( .io_lsu_c2_m_clk(clkdomain_io_lsu_c2_m_clk), .io_lsu_c2_r_clk(clkdomain_io_lsu_c2_r_clk), .io_lsu_store_c1_m_clk(clkdomain_io_lsu_store_c1_m_clk), + .io_lsu_store_c1_r_clk(clkdomain_io_lsu_store_c1_r_clk), .io_lsu_stbuf_c1_clk(clkdomain_io_lsu_stbuf_c1_clk), .io_lsu_bus_obuf_c1_clk(clkdomain_io_lsu_bus_obuf_c1_clk), .io_lsu_bus_ibuf_c1_clk(clkdomain_io_lsu_bus_ibuf_c1_clk), @@ -11545,7 +11549,7 @@ module el2_lsu( assign dccm_ctl_io_lsu_c2_m_clk = clkdomain_io_lsu_c2_m_clk; // @[el2_lsu.scala 240:46] assign dccm_ctl_io_lsu_c2_r_clk = clkdomain_io_lsu_c2_m_clk; // @[el2_lsu.scala 241:46] assign dccm_ctl_io_lsu_free_c2_clk = clkdomain_io_lsu_c2_r_clk; // @[el2_lsu.scala 242:46] - assign dccm_ctl_io_lsu_store_c1_r_clk = clkdomain_io_lsu_c1_r_clk; // @[el2_lsu.scala 244:46] + assign dccm_ctl_io_lsu_store_c1_r_clk = clkdomain_io_lsu_store_c1_r_clk; // @[el2_lsu.scala 244:46] assign dccm_ctl_io_lsu_pkt_d_valid = lsu_lsc_ctl_io_lsu_pkt_d_valid; // @[el2_lsu.scala 246:46] assign dccm_ctl_io_lsu_pkt_d_bits_word = lsu_lsc_ctl_io_lsu_pkt_d_bits_word; // @[el2_lsu.scala 246:46] assign dccm_ctl_io_lsu_pkt_d_bits_dword = lsu_lsc_ctl_io_lsu_pkt_d_bits_dword; // @[el2_lsu.scala 246:46] diff --git a/el2_lsu_bus_intf.anno.json b/el2_lsu_bus_intf.anno.json index 14c64584..2b1024d0 100644 --- a/el2_lsu_bus_intf.anno.json +++ b/el2_lsu_bus_intf.anno.json @@ -13,6 +13,26 @@ "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_commit_r" ] }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_nonblock_load_valid_m", + "sources":[ + "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_bits_load", + "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_flush_m_up", + "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_busreq_m", + "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_valid", + "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_is_sideeffects_m", + "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_addr_m", + "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_end_addr_m", + "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_bits_by", + "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_bits_store", + "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_bits_word", + "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_bits_half", + "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_valid", + "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_addr_r", + "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_end_addr_r" + ] + }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_bus_read_data_m", @@ -20,13 +40,13 @@ "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_addr_m", "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_busreq_m", "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_end_addr_m", - "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_store", + "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_bits_store", "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_store_data_r", - "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_by", + "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_bits_by", "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_valid", "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_addr_r", - "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_word", - "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_half", + "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_bits_word", + "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_bits_half", "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_end_addr_r" ] }, @@ -39,26 +59,6 @@ "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_axi_wready" ] }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_nonblock_load_valid_m", - "sources":[ - "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_load", - "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_flush_m_up", - "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_busreq_m", - "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_valid", - "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_is_sideeffects_m", - "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_addr_m", - "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_end_addr_m", - "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_by", - "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_store", - "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_word", - "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_half", - "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_valid", - "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_addr_r", - "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_end_addr_r" - ] - }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pmu_bus_busy", diff --git a/el2_lsu_bus_intf.fir b/el2_lsu_bus_intf.fir index 3f689d76..de2784cc 100644 --- a/el2_lsu_bus_intf.fir +++ b/el2_lsu_bus_intf.fir @@ -291,7 +291,7 @@ circuit el2_lsu_bus_intf : module el2_lsu_bus_buffer : input clock : Clock input reset : AsyncReset - output io : {flip scan_mode : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip lsu_c2_r_clk : Clock, flip lsu_bus_ibuf_c1_clk : Clock, flip lsu_bus_obuf_c1_clk : Clock, flip lsu_bus_buf_c1_clk : Clock, flip lsu_free_c2_clk : Clock, flip lsu_busm_clk : Clock, flip dec_lsu_valid_raw_d : UInt<1>, flip lsu_pkt_m : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip lsu_pkt_r : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip lsu_addr_m : UInt<32>, flip end_addr_m : UInt<32>, flip lsu_addr_r : UInt<32>, flip end_addr_r : UInt<32>, flip store_data_r : UInt<32>, flip no_word_merge_r : UInt<1>, flip no_dword_merge_r : UInt<1>, flip lsu_busreq_m : UInt<1>, flip ld_full_hit_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, flip lsu_commit_r : UInt<1>, flip is_sideeffects_r : UInt<1>, flip ldst_dual_d : UInt<1>, flip ldst_dual_m : UInt<1>, flip ldst_dual_r : UInt<1>, flip ldst_byteen_ext_m : UInt<8>, flip lsu_axi_wready : UInt<1>, flip lsu_axi_bvalid : UInt<1>, flip lsu_axi_bresp : UInt<2>, flip lsu_axi_bid : UInt<3>, flip lsu_axi_arready : UInt<1>, flip lsu_axi_rvalid : UInt<1>, flip lsu_axi_rid : UInt<3>, flip lsu_axi_rdata : UInt<64>, flip lsu_axi_rresp : UInt<2>, flip lsu_bus_clk_en : UInt<1>, flip lsu_bus_clk_en_q : UInt<1>, lsu_busreq_r : UInt<1>, lsu_bus_buffer_pend_any : UInt<1>, lsu_bus_buffer_full_any : UInt<1>, lsu_bus_buffer_empty_any : UInt<1>, lsu_bus_idle_any : UInt<1>, ld_byte_hit_buf_lo : UInt<4>, ld_byte_hit_buf_hi : UInt<4>, ld_fwddata_buf_lo : UInt<32>, ld_fwddata_buf_hi : UInt<32>, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>, lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>, lsu_nonblock_load_data : UInt<32>, lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, lsu_axi_awvalid : UInt<1>, flip lsu_axi_awready : UInt<1>, lsu_axi_awid : UInt<3>, lsu_axi_awaddr : UInt<32>, lsu_axi_awregion : UInt<4>, lsu_axi_awlen : UInt<8>, lsu_axi_awsize : UInt<3>, lsu_axi_awburst : UInt<2>, lsu_axi_awlock : UInt<1>, lsu_axi_awcache : UInt<4>, lsu_axi_awprot : UInt<3>, lsu_axi_awqos : UInt<4>, lsu_axi_wvalid : UInt<1>, lsu_axi_wdata : UInt<64>, lsu_axi_wstrb : UInt<8>, lsu_axi_wlast : UInt<1>, lsu_axi_bready : UInt<1>, lsu_axi_arvalid : UInt<1>, lsu_axi_arid : UInt<3>, lsu_axi_araddr : UInt<32>, lsu_axi_arregion : UInt<4>, lsu_axi_arlen : UInt<8>, lsu_axi_arsize : UInt<3>, lsu_axi_arburst : UInt<2>, lsu_axi_arlock : UInt<1>, lsu_axi_arcache : UInt<4>, lsu_axi_arprot : UInt<3>, lsu_axi_arqos : UInt<4>, lsu_axi_rready : UInt<1>} + output io : {flip scan_mode : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip lsu_c2_r_clk : Clock, flip lsu_bus_ibuf_c1_clk : Clock, flip lsu_bus_obuf_c1_clk : Clock, flip lsu_bus_buf_c1_clk : Clock, flip lsu_free_c2_clk : Clock, flip lsu_busm_clk : Clock, flip dec_lsu_valid_raw_d : UInt<1>, flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_addr_m : UInt<32>, flip end_addr_m : UInt<32>, flip lsu_addr_r : UInt<32>, flip end_addr_r : UInt<32>, flip store_data_r : UInt<32>, flip no_word_merge_r : UInt<1>, flip no_dword_merge_r : UInt<1>, flip lsu_busreq_m : UInt<1>, flip ld_full_hit_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, flip lsu_commit_r : UInt<1>, flip is_sideeffects_r : UInt<1>, flip ldst_dual_d : UInt<1>, flip ldst_dual_m : UInt<1>, flip ldst_dual_r : UInt<1>, flip ldst_byteen_ext_m : UInt<8>, flip lsu_axi_wready : UInt<1>, flip lsu_axi_bvalid : UInt<1>, flip lsu_axi_bresp : UInt<2>, flip lsu_axi_bid : UInt<3>, flip lsu_axi_arready : UInt<1>, flip lsu_axi_rvalid : UInt<1>, flip lsu_axi_rid : UInt<3>, flip lsu_axi_rdata : UInt<64>, flip lsu_axi_rresp : UInt<2>, flip lsu_bus_clk_en : UInt<1>, flip lsu_bus_clk_en_q : UInt<1>, lsu_busreq_r : UInt<1>, lsu_bus_buffer_pend_any : UInt<1>, lsu_bus_buffer_full_any : UInt<1>, lsu_bus_buffer_empty_any : UInt<1>, lsu_bus_idle_any : UInt<1>, ld_byte_hit_buf_lo : UInt<4>, ld_byte_hit_buf_hi : UInt<4>, ld_fwddata_buf_lo : UInt<32>, ld_fwddata_buf_hi : UInt<32>, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>, lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>, lsu_nonblock_load_data : UInt<32>, lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, lsu_axi_awvalid : UInt<1>, flip lsu_axi_awready : UInt<1>, lsu_axi_awid : UInt<3>, lsu_axi_awaddr : UInt<32>, lsu_axi_awregion : UInt<4>, lsu_axi_awlen : UInt<8>, lsu_axi_awsize : UInt<3>, lsu_axi_awburst : UInt<2>, lsu_axi_awlock : UInt<1>, lsu_axi_awcache : UInt<4>, lsu_axi_awprot : UInt<3>, lsu_axi_awqos : UInt<4>, lsu_axi_wvalid : UInt<1>, lsu_axi_wdata : UInt<64>, lsu_axi_wstrb : UInt<8>, lsu_axi_wlast : UInt<1>, lsu_axi_bready : UInt<1>, lsu_axi_arvalid : UInt<1>, lsu_axi_arid : UInt<3>, lsu_axi_araddr : UInt<32>, lsu_axi_arregion : UInt<4>, lsu_axi_arlen : UInt<8>, lsu_axi_arsize : UInt<3>, lsu_axi_arburst : UInt<2>, lsu_axi_arlock : UInt<1>, lsu_axi_arcache : UInt<4>, lsu_axi_arprot : UInt<3>, lsu_axi_arqos : UInt<4>, lsu_axi_rready : UInt<1>} wire buf_addr : UInt<32>[4] @[el2_lsu_bus_buffer.scala 121:22] wire buf_state : UInt<3>[4] @[el2_lsu_bus_buffer.scala 122:23] @@ -495,769 +495,771 @@ circuit el2_lsu_bus_intf : buf_unsign <= UInt<1>("h00") wire buf_error : UInt<4> buf_error <= UInt<1>("h00") + wire CmdPtr1 : UInt<2> + CmdPtr1 <= UInt<1>("h00") wire ibuf_data : UInt<32> ibuf_data <= UInt<1>("h00") - node _T_56 = orr(ld_byte_hitvecfn_lo[0]) @[el2_lsu_bus_buffer.scala 191:73] - node _T_57 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[el2_lsu_bus_buffer.scala 191:98] - node _T_58 = or(_T_56, _T_57) @[el2_lsu_bus_buffer.scala 191:77] - node _T_59 = orr(ld_byte_hitvecfn_lo[1]) @[el2_lsu_bus_buffer.scala 191:73] - node _T_60 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[el2_lsu_bus_buffer.scala 191:98] - node _T_61 = or(_T_59, _T_60) @[el2_lsu_bus_buffer.scala 191:77] - node _T_62 = orr(ld_byte_hitvecfn_lo[2]) @[el2_lsu_bus_buffer.scala 191:73] - node _T_63 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[el2_lsu_bus_buffer.scala 191:98] - node _T_64 = or(_T_62, _T_63) @[el2_lsu_bus_buffer.scala 191:77] - node _T_65 = orr(ld_byte_hitvecfn_lo[3]) @[el2_lsu_bus_buffer.scala 191:73] - node _T_66 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[el2_lsu_bus_buffer.scala 191:98] - node _T_67 = or(_T_65, _T_66) @[el2_lsu_bus_buffer.scala 191:77] + node _T_56 = orr(ld_byte_hitvecfn_lo[0]) @[el2_lsu_bus_buffer.scala 192:73] + node _T_57 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[el2_lsu_bus_buffer.scala 192:98] + node _T_58 = or(_T_56, _T_57) @[el2_lsu_bus_buffer.scala 192:77] + node _T_59 = orr(ld_byte_hitvecfn_lo[1]) @[el2_lsu_bus_buffer.scala 192:73] + node _T_60 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[el2_lsu_bus_buffer.scala 192:98] + node _T_61 = or(_T_59, _T_60) @[el2_lsu_bus_buffer.scala 192:77] + node _T_62 = orr(ld_byte_hitvecfn_lo[2]) @[el2_lsu_bus_buffer.scala 192:73] + node _T_63 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[el2_lsu_bus_buffer.scala 192:98] + node _T_64 = or(_T_62, _T_63) @[el2_lsu_bus_buffer.scala 192:77] + node _T_65 = orr(ld_byte_hitvecfn_lo[3]) @[el2_lsu_bus_buffer.scala 192:73] + node _T_66 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[el2_lsu_bus_buffer.scala 192:98] + node _T_67 = or(_T_65, _T_66) @[el2_lsu_bus_buffer.scala 192:77] node _T_68 = cat(_T_67, _T_64) @[Cat.scala 29:58] node _T_69 = cat(_T_68, _T_61) @[Cat.scala 29:58] node _T_70 = cat(_T_69, _T_58) @[Cat.scala 29:58] - io.ld_byte_hit_buf_lo <= _T_70 @[el2_lsu_bus_buffer.scala 191:25] - node _T_71 = orr(ld_byte_hitvecfn_hi[0]) @[el2_lsu_bus_buffer.scala 192:73] - node _T_72 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[el2_lsu_bus_buffer.scala 192:98] - node _T_73 = or(_T_71, _T_72) @[el2_lsu_bus_buffer.scala 192:77] - node _T_74 = orr(ld_byte_hitvecfn_hi[1]) @[el2_lsu_bus_buffer.scala 192:73] - node _T_75 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[el2_lsu_bus_buffer.scala 192:98] - node _T_76 = or(_T_74, _T_75) @[el2_lsu_bus_buffer.scala 192:77] - node _T_77 = orr(ld_byte_hitvecfn_hi[2]) @[el2_lsu_bus_buffer.scala 192:73] - node _T_78 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[el2_lsu_bus_buffer.scala 192:98] - node _T_79 = or(_T_77, _T_78) @[el2_lsu_bus_buffer.scala 192:77] - node _T_80 = orr(ld_byte_hitvecfn_hi[3]) @[el2_lsu_bus_buffer.scala 192:73] - node _T_81 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[el2_lsu_bus_buffer.scala 192:98] - node _T_82 = or(_T_80, _T_81) @[el2_lsu_bus_buffer.scala 192:77] + io.ld_byte_hit_buf_lo <= _T_70 @[el2_lsu_bus_buffer.scala 192:25] + node _T_71 = orr(ld_byte_hitvecfn_hi[0]) @[el2_lsu_bus_buffer.scala 193:73] + node _T_72 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[el2_lsu_bus_buffer.scala 193:98] + node _T_73 = or(_T_71, _T_72) @[el2_lsu_bus_buffer.scala 193:77] + node _T_74 = orr(ld_byte_hitvecfn_hi[1]) @[el2_lsu_bus_buffer.scala 193:73] + node _T_75 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[el2_lsu_bus_buffer.scala 193:98] + node _T_76 = or(_T_74, _T_75) @[el2_lsu_bus_buffer.scala 193:77] + node _T_77 = orr(ld_byte_hitvecfn_hi[2]) @[el2_lsu_bus_buffer.scala 193:73] + node _T_78 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[el2_lsu_bus_buffer.scala 193:98] + node _T_79 = or(_T_77, _T_78) @[el2_lsu_bus_buffer.scala 193:77] + node _T_80 = orr(ld_byte_hitvecfn_hi[3]) @[el2_lsu_bus_buffer.scala 193:73] + node _T_81 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[el2_lsu_bus_buffer.scala 193:98] + node _T_82 = or(_T_80, _T_81) @[el2_lsu_bus_buffer.scala 193:77] node _T_83 = cat(_T_82, _T_79) @[Cat.scala 29:58] node _T_84 = cat(_T_83, _T_76) @[Cat.scala 29:58] node _T_85 = cat(_T_84, _T_73) @[Cat.scala 29:58] - io.ld_byte_hit_buf_hi <= _T_85 @[el2_lsu_bus_buffer.scala 192:25] - node _T_86 = bits(buf_byteen[0], 0, 0) @[el2_lsu_bus_buffer.scala 194:110] - node _T_87 = and(ld_addr_hitvec_lo_0, _T_86) @[el2_lsu_bus_buffer.scala 194:95] - node _T_88 = bits(ldst_byteen_lo_m, 0, 0) @[el2_lsu_bus_buffer.scala 194:132] - node _T_89 = and(_T_87, _T_88) @[el2_lsu_bus_buffer.scala 194:114] - node _T_90 = bits(buf_byteen[1], 0, 0) @[el2_lsu_bus_buffer.scala 194:110] - node _T_91 = and(ld_addr_hitvec_lo_1, _T_90) @[el2_lsu_bus_buffer.scala 194:95] - node _T_92 = bits(ldst_byteen_lo_m, 0, 0) @[el2_lsu_bus_buffer.scala 194:132] - node _T_93 = and(_T_91, _T_92) @[el2_lsu_bus_buffer.scala 194:114] - node _T_94 = bits(buf_byteen[2], 0, 0) @[el2_lsu_bus_buffer.scala 194:110] - node _T_95 = and(ld_addr_hitvec_lo_2, _T_94) @[el2_lsu_bus_buffer.scala 194:95] - node _T_96 = bits(ldst_byteen_lo_m, 0, 0) @[el2_lsu_bus_buffer.scala 194:132] - node _T_97 = and(_T_95, _T_96) @[el2_lsu_bus_buffer.scala 194:114] - node _T_98 = bits(buf_byteen[3], 0, 0) @[el2_lsu_bus_buffer.scala 194:110] - node _T_99 = and(ld_addr_hitvec_lo_3, _T_98) @[el2_lsu_bus_buffer.scala 194:95] - node _T_100 = bits(ldst_byteen_lo_m, 0, 0) @[el2_lsu_bus_buffer.scala 194:132] - node _T_101 = and(_T_99, _T_100) @[el2_lsu_bus_buffer.scala 194:114] + io.ld_byte_hit_buf_hi <= _T_85 @[el2_lsu_bus_buffer.scala 193:25] + node _T_86 = bits(buf_byteen[0], 0, 0) @[el2_lsu_bus_buffer.scala 195:110] + node _T_87 = and(ld_addr_hitvec_lo_0, _T_86) @[el2_lsu_bus_buffer.scala 195:95] + node _T_88 = bits(ldst_byteen_lo_m, 0, 0) @[el2_lsu_bus_buffer.scala 195:132] + node _T_89 = and(_T_87, _T_88) @[el2_lsu_bus_buffer.scala 195:114] + node _T_90 = bits(buf_byteen[1], 0, 0) @[el2_lsu_bus_buffer.scala 195:110] + node _T_91 = and(ld_addr_hitvec_lo_1, _T_90) @[el2_lsu_bus_buffer.scala 195:95] + node _T_92 = bits(ldst_byteen_lo_m, 0, 0) @[el2_lsu_bus_buffer.scala 195:132] + node _T_93 = and(_T_91, _T_92) @[el2_lsu_bus_buffer.scala 195:114] + node _T_94 = bits(buf_byteen[2], 0, 0) @[el2_lsu_bus_buffer.scala 195:110] + node _T_95 = and(ld_addr_hitvec_lo_2, _T_94) @[el2_lsu_bus_buffer.scala 195:95] + node _T_96 = bits(ldst_byteen_lo_m, 0, 0) @[el2_lsu_bus_buffer.scala 195:132] + node _T_97 = and(_T_95, _T_96) @[el2_lsu_bus_buffer.scala 195:114] + node _T_98 = bits(buf_byteen[3], 0, 0) @[el2_lsu_bus_buffer.scala 195:110] + node _T_99 = and(ld_addr_hitvec_lo_3, _T_98) @[el2_lsu_bus_buffer.scala 195:95] + node _T_100 = bits(ldst_byteen_lo_m, 0, 0) @[el2_lsu_bus_buffer.scala 195:132] + node _T_101 = and(_T_99, _T_100) @[el2_lsu_bus_buffer.scala 195:114] node _T_102 = cat(_T_101, _T_97) @[Cat.scala 29:58] node _T_103 = cat(_T_102, _T_93) @[Cat.scala 29:58] node ld_byte_hitvec_lo_0 = cat(_T_103, _T_89) @[Cat.scala 29:58] - node _T_104 = bits(buf_byteen[0], 1, 1) @[el2_lsu_bus_buffer.scala 194:110] - node _T_105 = and(ld_addr_hitvec_lo_0, _T_104) @[el2_lsu_bus_buffer.scala 194:95] - node _T_106 = bits(ldst_byteen_lo_m, 1, 1) @[el2_lsu_bus_buffer.scala 194:132] - node _T_107 = and(_T_105, _T_106) @[el2_lsu_bus_buffer.scala 194:114] - node _T_108 = bits(buf_byteen[1], 1, 1) @[el2_lsu_bus_buffer.scala 194:110] - node _T_109 = and(ld_addr_hitvec_lo_1, _T_108) @[el2_lsu_bus_buffer.scala 194:95] - node _T_110 = bits(ldst_byteen_lo_m, 1, 1) @[el2_lsu_bus_buffer.scala 194:132] - node _T_111 = and(_T_109, _T_110) @[el2_lsu_bus_buffer.scala 194:114] - node _T_112 = bits(buf_byteen[2], 1, 1) @[el2_lsu_bus_buffer.scala 194:110] - node _T_113 = and(ld_addr_hitvec_lo_2, _T_112) @[el2_lsu_bus_buffer.scala 194:95] - node _T_114 = bits(ldst_byteen_lo_m, 1, 1) @[el2_lsu_bus_buffer.scala 194:132] - node _T_115 = and(_T_113, _T_114) @[el2_lsu_bus_buffer.scala 194:114] - node _T_116 = bits(buf_byteen[3], 1, 1) @[el2_lsu_bus_buffer.scala 194:110] - node _T_117 = and(ld_addr_hitvec_lo_3, _T_116) @[el2_lsu_bus_buffer.scala 194:95] - node _T_118 = bits(ldst_byteen_lo_m, 1, 1) @[el2_lsu_bus_buffer.scala 194:132] - node _T_119 = and(_T_117, _T_118) @[el2_lsu_bus_buffer.scala 194:114] + node _T_104 = bits(buf_byteen[0], 1, 1) @[el2_lsu_bus_buffer.scala 195:110] + node _T_105 = and(ld_addr_hitvec_lo_0, _T_104) @[el2_lsu_bus_buffer.scala 195:95] + node _T_106 = bits(ldst_byteen_lo_m, 1, 1) @[el2_lsu_bus_buffer.scala 195:132] + node _T_107 = and(_T_105, _T_106) @[el2_lsu_bus_buffer.scala 195:114] + node _T_108 = bits(buf_byteen[1], 1, 1) @[el2_lsu_bus_buffer.scala 195:110] + node _T_109 = and(ld_addr_hitvec_lo_1, _T_108) @[el2_lsu_bus_buffer.scala 195:95] + node _T_110 = bits(ldst_byteen_lo_m, 1, 1) @[el2_lsu_bus_buffer.scala 195:132] + node _T_111 = and(_T_109, _T_110) @[el2_lsu_bus_buffer.scala 195:114] + node _T_112 = bits(buf_byteen[2], 1, 1) @[el2_lsu_bus_buffer.scala 195:110] + node _T_113 = and(ld_addr_hitvec_lo_2, _T_112) @[el2_lsu_bus_buffer.scala 195:95] + node _T_114 = bits(ldst_byteen_lo_m, 1, 1) @[el2_lsu_bus_buffer.scala 195:132] + node _T_115 = and(_T_113, _T_114) @[el2_lsu_bus_buffer.scala 195:114] + node _T_116 = bits(buf_byteen[3], 1, 1) @[el2_lsu_bus_buffer.scala 195:110] + node _T_117 = and(ld_addr_hitvec_lo_3, _T_116) @[el2_lsu_bus_buffer.scala 195:95] + node _T_118 = bits(ldst_byteen_lo_m, 1, 1) @[el2_lsu_bus_buffer.scala 195:132] + node _T_119 = and(_T_117, _T_118) @[el2_lsu_bus_buffer.scala 195:114] node _T_120 = cat(_T_119, _T_115) @[Cat.scala 29:58] node _T_121 = cat(_T_120, _T_111) @[Cat.scala 29:58] node ld_byte_hitvec_lo_1 = cat(_T_121, _T_107) @[Cat.scala 29:58] - node _T_122 = bits(buf_byteen[0], 2, 2) @[el2_lsu_bus_buffer.scala 194:110] - node _T_123 = and(ld_addr_hitvec_lo_0, _T_122) @[el2_lsu_bus_buffer.scala 194:95] - node _T_124 = bits(ldst_byteen_lo_m, 2, 2) @[el2_lsu_bus_buffer.scala 194:132] - node _T_125 = and(_T_123, _T_124) @[el2_lsu_bus_buffer.scala 194:114] - node _T_126 = bits(buf_byteen[1], 2, 2) @[el2_lsu_bus_buffer.scala 194:110] - node _T_127 = and(ld_addr_hitvec_lo_1, _T_126) @[el2_lsu_bus_buffer.scala 194:95] - node _T_128 = bits(ldst_byteen_lo_m, 2, 2) @[el2_lsu_bus_buffer.scala 194:132] - node _T_129 = and(_T_127, _T_128) @[el2_lsu_bus_buffer.scala 194:114] - node _T_130 = bits(buf_byteen[2], 2, 2) @[el2_lsu_bus_buffer.scala 194:110] - node _T_131 = and(ld_addr_hitvec_lo_2, _T_130) @[el2_lsu_bus_buffer.scala 194:95] - node _T_132 = bits(ldst_byteen_lo_m, 2, 2) @[el2_lsu_bus_buffer.scala 194:132] - node _T_133 = and(_T_131, _T_132) @[el2_lsu_bus_buffer.scala 194:114] - node _T_134 = bits(buf_byteen[3], 2, 2) @[el2_lsu_bus_buffer.scala 194:110] - node _T_135 = and(ld_addr_hitvec_lo_3, _T_134) @[el2_lsu_bus_buffer.scala 194:95] - node _T_136 = bits(ldst_byteen_lo_m, 2, 2) @[el2_lsu_bus_buffer.scala 194:132] - node _T_137 = and(_T_135, _T_136) @[el2_lsu_bus_buffer.scala 194:114] + node _T_122 = bits(buf_byteen[0], 2, 2) @[el2_lsu_bus_buffer.scala 195:110] + node _T_123 = and(ld_addr_hitvec_lo_0, _T_122) @[el2_lsu_bus_buffer.scala 195:95] + node _T_124 = bits(ldst_byteen_lo_m, 2, 2) @[el2_lsu_bus_buffer.scala 195:132] + node _T_125 = and(_T_123, _T_124) @[el2_lsu_bus_buffer.scala 195:114] + node _T_126 = bits(buf_byteen[1], 2, 2) @[el2_lsu_bus_buffer.scala 195:110] + node _T_127 = and(ld_addr_hitvec_lo_1, _T_126) @[el2_lsu_bus_buffer.scala 195:95] + node _T_128 = bits(ldst_byteen_lo_m, 2, 2) @[el2_lsu_bus_buffer.scala 195:132] + node _T_129 = and(_T_127, _T_128) @[el2_lsu_bus_buffer.scala 195:114] + node _T_130 = bits(buf_byteen[2], 2, 2) @[el2_lsu_bus_buffer.scala 195:110] + node _T_131 = and(ld_addr_hitvec_lo_2, _T_130) @[el2_lsu_bus_buffer.scala 195:95] + node _T_132 = bits(ldst_byteen_lo_m, 2, 2) @[el2_lsu_bus_buffer.scala 195:132] + node _T_133 = and(_T_131, _T_132) @[el2_lsu_bus_buffer.scala 195:114] + node _T_134 = bits(buf_byteen[3], 2, 2) @[el2_lsu_bus_buffer.scala 195:110] + node _T_135 = and(ld_addr_hitvec_lo_3, _T_134) @[el2_lsu_bus_buffer.scala 195:95] + node _T_136 = bits(ldst_byteen_lo_m, 2, 2) @[el2_lsu_bus_buffer.scala 195:132] + node _T_137 = and(_T_135, _T_136) @[el2_lsu_bus_buffer.scala 195:114] node _T_138 = cat(_T_137, _T_133) @[Cat.scala 29:58] node _T_139 = cat(_T_138, _T_129) @[Cat.scala 29:58] node ld_byte_hitvec_lo_2 = cat(_T_139, _T_125) @[Cat.scala 29:58] - node _T_140 = bits(buf_byteen[0], 3, 3) @[el2_lsu_bus_buffer.scala 194:110] - node _T_141 = and(ld_addr_hitvec_lo_0, _T_140) @[el2_lsu_bus_buffer.scala 194:95] - node _T_142 = bits(ldst_byteen_lo_m, 3, 3) @[el2_lsu_bus_buffer.scala 194:132] - node _T_143 = and(_T_141, _T_142) @[el2_lsu_bus_buffer.scala 194:114] - node _T_144 = bits(buf_byteen[1], 3, 3) @[el2_lsu_bus_buffer.scala 194:110] - node _T_145 = and(ld_addr_hitvec_lo_1, _T_144) @[el2_lsu_bus_buffer.scala 194:95] - node _T_146 = bits(ldst_byteen_lo_m, 3, 3) @[el2_lsu_bus_buffer.scala 194:132] - node _T_147 = and(_T_145, _T_146) @[el2_lsu_bus_buffer.scala 194:114] - node _T_148 = bits(buf_byteen[2], 3, 3) @[el2_lsu_bus_buffer.scala 194:110] - node _T_149 = and(ld_addr_hitvec_lo_2, _T_148) @[el2_lsu_bus_buffer.scala 194:95] - node _T_150 = bits(ldst_byteen_lo_m, 3, 3) @[el2_lsu_bus_buffer.scala 194:132] - node _T_151 = and(_T_149, _T_150) @[el2_lsu_bus_buffer.scala 194:114] - node _T_152 = bits(buf_byteen[3], 3, 3) @[el2_lsu_bus_buffer.scala 194:110] - node _T_153 = and(ld_addr_hitvec_lo_3, _T_152) @[el2_lsu_bus_buffer.scala 194:95] - node _T_154 = bits(ldst_byteen_lo_m, 3, 3) @[el2_lsu_bus_buffer.scala 194:132] - node _T_155 = and(_T_153, _T_154) @[el2_lsu_bus_buffer.scala 194:114] + node _T_140 = bits(buf_byteen[0], 3, 3) @[el2_lsu_bus_buffer.scala 195:110] + node _T_141 = and(ld_addr_hitvec_lo_0, _T_140) @[el2_lsu_bus_buffer.scala 195:95] + node _T_142 = bits(ldst_byteen_lo_m, 3, 3) @[el2_lsu_bus_buffer.scala 195:132] + node _T_143 = and(_T_141, _T_142) @[el2_lsu_bus_buffer.scala 195:114] + node _T_144 = bits(buf_byteen[1], 3, 3) @[el2_lsu_bus_buffer.scala 195:110] + node _T_145 = and(ld_addr_hitvec_lo_1, _T_144) @[el2_lsu_bus_buffer.scala 195:95] + node _T_146 = bits(ldst_byteen_lo_m, 3, 3) @[el2_lsu_bus_buffer.scala 195:132] + node _T_147 = and(_T_145, _T_146) @[el2_lsu_bus_buffer.scala 195:114] + node _T_148 = bits(buf_byteen[2], 3, 3) @[el2_lsu_bus_buffer.scala 195:110] + node _T_149 = and(ld_addr_hitvec_lo_2, _T_148) @[el2_lsu_bus_buffer.scala 195:95] + node _T_150 = bits(ldst_byteen_lo_m, 3, 3) @[el2_lsu_bus_buffer.scala 195:132] + node _T_151 = and(_T_149, _T_150) @[el2_lsu_bus_buffer.scala 195:114] + node _T_152 = bits(buf_byteen[3], 3, 3) @[el2_lsu_bus_buffer.scala 195:110] + node _T_153 = and(ld_addr_hitvec_lo_3, _T_152) @[el2_lsu_bus_buffer.scala 195:95] + node _T_154 = bits(ldst_byteen_lo_m, 3, 3) @[el2_lsu_bus_buffer.scala 195:132] + node _T_155 = and(_T_153, _T_154) @[el2_lsu_bus_buffer.scala 195:114] node _T_156 = cat(_T_155, _T_151) @[Cat.scala 29:58] node _T_157 = cat(_T_156, _T_147) @[Cat.scala 29:58] node ld_byte_hitvec_lo_3 = cat(_T_157, _T_143) @[Cat.scala 29:58] - node _T_158 = bits(buf_byteen[0], 0, 0) @[el2_lsu_bus_buffer.scala 195:110] - node _T_159 = and(ld_addr_hitvec_hi_0, _T_158) @[el2_lsu_bus_buffer.scala 195:95] - node _T_160 = bits(ldst_byteen_hi_m, 0, 0) @[el2_lsu_bus_buffer.scala 195:132] - node _T_161 = and(_T_159, _T_160) @[el2_lsu_bus_buffer.scala 195:114] - node _T_162 = bits(buf_byteen[1], 0, 0) @[el2_lsu_bus_buffer.scala 195:110] - node _T_163 = and(ld_addr_hitvec_hi_1, _T_162) @[el2_lsu_bus_buffer.scala 195:95] - node _T_164 = bits(ldst_byteen_hi_m, 0, 0) @[el2_lsu_bus_buffer.scala 195:132] - node _T_165 = and(_T_163, _T_164) @[el2_lsu_bus_buffer.scala 195:114] - node _T_166 = bits(buf_byteen[2], 0, 0) @[el2_lsu_bus_buffer.scala 195:110] - node _T_167 = and(ld_addr_hitvec_hi_2, _T_166) @[el2_lsu_bus_buffer.scala 195:95] - node _T_168 = bits(ldst_byteen_hi_m, 0, 0) @[el2_lsu_bus_buffer.scala 195:132] - node _T_169 = and(_T_167, _T_168) @[el2_lsu_bus_buffer.scala 195:114] - node _T_170 = bits(buf_byteen[3], 0, 0) @[el2_lsu_bus_buffer.scala 195:110] - node _T_171 = and(ld_addr_hitvec_hi_3, _T_170) @[el2_lsu_bus_buffer.scala 195:95] - node _T_172 = bits(ldst_byteen_hi_m, 0, 0) @[el2_lsu_bus_buffer.scala 195:132] - node _T_173 = and(_T_171, _T_172) @[el2_lsu_bus_buffer.scala 195:114] + node _T_158 = bits(buf_byteen[0], 0, 0) @[el2_lsu_bus_buffer.scala 196:110] + node _T_159 = and(ld_addr_hitvec_hi_0, _T_158) @[el2_lsu_bus_buffer.scala 196:95] + node _T_160 = bits(ldst_byteen_hi_m, 0, 0) @[el2_lsu_bus_buffer.scala 196:132] + node _T_161 = and(_T_159, _T_160) @[el2_lsu_bus_buffer.scala 196:114] + node _T_162 = bits(buf_byteen[1], 0, 0) @[el2_lsu_bus_buffer.scala 196:110] + node _T_163 = and(ld_addr_hitvec_hi_1, _T_162) @[el2_lsu_bus_buffer.scala 196:95] + node _T_164 = bits(ldst_byteen_hi_m, 0, 0) @[el2_lsu_bus_buffer.scala 196:132] + node _T_165 = and(_T_163, _T_164) @[el2_lsu_bus_buffer.scala 196:114] + node _T_166 = bits(buf_byteen[2], 0, 0) @[el2_lsu_bus_buffer.scala 196:110] + node _T_167 = and(ld_addr_hitvec_hi_2, _T_166) @[el2_lsu_bus_buffer.scala 196:95] + node _T_168 = bits(ldst_byteen_hi_m, 0, 0) @[el2_lsu_bus_buffer.scala 196:132] + node _T_169 = and(_T_167, _T_168) @[el2_lsu_bus_buffer.scala 196:114] + node _T_170 = bits(buf_byteen[3], 0, 0) @[el2_lsu_bus_buffer.scala 196:110] + node _T_171 = and(ld_addr_hitvec_hi_3, _T_170) @[el2_lsu_bus_buffer.scala 196:95] + node _T_172 = bits(ldst_byteen_hi_m, 0, 0) @[el2_lsu_bus_buffer.scala 196:132] + node _T_173 = and(_T_171, _T_172) @[el2_lsu_bus_buffer.scala 196:114] node _T_174 = cat(_T_173, _T_169) @[Cat.scala 29:58] node _T_175 = cat(_T_174, _T_165) @[Cat.scala 29:58] node ld_byte_hitvec_hi_0 = cat(_T_175, _T_161) @[Cat.scala 29:58] - node _T_176 = bits(buf_byteen[0], 1, 1) @[el2_lsu_bus_buffer.scala 195:110] - node _T_177 = and(ld_addr_hitvec_hi_0, _T_176) @[el2_lsu_bus_buffer.scala 195:95] - node _T_178 = bits(ldst_byteen_hi_m, 1, 1) @[el2_lsu_bus_buffer.scala 195:132] - node _T_179 = and(_T_177, _T_178) @[el2_lsu_bus_buffer.scala 195:114] - node _T_180 = bits(buf_byteen[1], 1, 1) @[el2_lsu_bus_buffer.scala 195:110] - node _T_181 = and(ld_addr_hitvec_hi_1, _T_180) @[el2_lsu_bus_buffer.scala 195:95] - node _T_182 = bits(ldst_byteen_hi_m, 1, 1) @[el2_lsu_bus_buffer.scala 195:132] - node _T_183 = and(_T_181, _T_182) @[el2_lsu_bus_buffer.scala 195:114] - node _T_184 = bits(buf_byteen[2], 1, 1) @[el2_lsu_bus_buffer.scala 195:110] - node _T_185 = and(ld_addr_hitvec_hi_2, _T_184) @[el2_lsu_bus_buffer.scala 195:95] - node _T_186 = bits(ldst_byteen_hi_m, 1, 1) @[el2_lsu_bus_buffer.scala 195:132] - node _T_187 = and(_T_185, _T_186) @[el2_lsu_bus_buffer.scala 195:114] - node _T_188 = bits(buf_byteen[3], 1, 1) @[el2_lsu_bus_buffer.scala 195:110] - node _T_189 = and(ld_addr_hitvec_hi_3, _T_188) @[el2_lsu_bus_buffer.scala 195:95] - node _T_190 = bits(ldst_byteen_hi_m, 1, 1) @[el2_lsu_bus_buffer.scala 195:132] - node _T_191 = and(_T_189, _T_190) @[el2_lsu_bus_buffer.scala 195:114] + node _T_176 = bits(buf_byteen[0], 1, 1) @[el2_lsu_bus_buffer.scala 196:110] + node _T_177 = and(ld_addr_hitvec_hi_0, _T_176) @[el2_lsu_bus_buffer.scala 196:95] + node _T_178 = bits(ldst_byteen_hi_m, 1, 1) @[el2_lsu_bus_buffer.scala 196:132] + node _T_179 = and(_T_177, _T_178) @[el2_lsu_bus_buffer.scala 196:114] + node _T_180 = bits(buf_byteen[1], 1, 1) @[el2_lsu_bus_buffer.scala 196:110] + node _T_181 = and(ld_addr_hitvec_hi_1, _T_180) @[el2_lsu_bus_buffer.scala 196:95] + node _T_182 = bits(ldst_byteen_hi_m, 1, 1) @[el2_lsu_bus_buffer.scala 196:132] + node _T_183 = and(_T_181, _T_182) @[el2_lsu_bus_buffer.scala 196:114] + node _T_184 = bits(buf_byteen[2], 1, 1) @[el2_lsu_bus_buffer.scala 196:110] + node _T_185 = and(ld_addr_hitvec_hi_2, _T_184) @[el2_lsu_bus_buffer.scala 196:95] + node _T_186 = bits(ldst_byteen_hi_m, 1, 1) @[el2_lsu_bus_buffer.scala 196:132] + node _T_187 = and(_T_185, _T_186) @[el2_lsu_bus_buffer.scala 196:114] + node _T_188 = bits(buf_byteen[3], 1, 1) @[el2_lsu_bus_buffer.scala 196:110] + node _T_189 = and(ld_addr_hitvec_hi_3, _T_188) @[el2_lsu_bus_buffer.scala 196:95] + node _T_190 = bits(ldst_byteen_hi_m, 1, 1) @[el2_lsu_bus_buffer.scala 196:132] + node _T_191 = and(_T_189, _T_190) @[el2_lsu_bus_buffer.scala 196:114] node _T_192 = cat(_T_191, _T_187) @[Cat.scala 29:58] node _T_193 = cat(_T_192, _T_183) @[Cat.scala 29:58] node ld_byte_hitvec_hi_1 = cat(_T_193, _T_179) @[Cat.scala 29:58] - node _T_194 = bits(buf_byteen[0], 2, 2) @[el2_lsu_bus_buffer.scala 195:110] - node _T_195 = and(ld_addr_hitvec_hi_0, _T_194) @[el2_lsu_bus_buffer.scala 195:95] - node _T_196 = bits(ldst_byteen_hi_m, 2, 2) @[el2_lsu_bus_buffer.scala 195:132] - node _T_197 = and(_T_195, _T_196) @[el2_lsu_bus_buffer.scala 195:114] - node _T_198 = bits(buf_byteen[1], 2, 2) @[el2_lsu_bus_buffer.scala 195:110] - node _T_199 = and(ld_addr_hitvec_hi_1, _T_198) @[el2_lsu_bus_buffer.scala 195:95] - node _T_200 = bits(ldst_byteen_hi_m, 2, 2) @[el2_lsu_bus_buffer.scala 195:132] - node _T_201 = and(_T_199, _T_200) @[el2_lsu_bus_buffer.scala 195:114] - node _T_202 = bits(buf_byteen[2], 2, 2) @[el2_lsu_bus_buffer.scala 195:110] - node _T_203 = and(ld_addr_hitvec_hi_2, _T_202) @[el2_lsu_bus_buffer.scala 195:95] - node _T_204 = bits(ldst_byteen_hi_m, 2, 2) @[el2_lsu_bus_buffer.scala 195:132] - node _T_205 = and(_T_203, _T_204) @[el2_lsu_bus_buffer.scala 195:114] - node _T_206 = bits(buf_byteen[3], 2, 2) @[el2_lsu_bus_buffer.scala 195:110] - node _T_207 = and(ld_addr_hitvec_hi_3, _T_206) @[el2_lsu_bus_buffer.scala 195:95] - node _T_208 = bits(ldst_byteen_hi_m, 2, 2) @[el2_lsu_bus_buffer.scala 195:132] - node _T_209 = and(_T_207, _T_208) @[el2_lsu_bus_buffer.scala 195:114] + node _T_194 = bits(buf_byteen[0], 2, 2) @[el2_lsu_bus_buffer.scala 196:110] + node _T_195 = and(ld_addr_hitvec_hi_0, _T_194) @[el2_lsu_bus_buffer.scala 196:95] + node _T_196 = bits(ldst_byteen_hi_m, 2, 2) @[el2_lsu_bus_buffer.scala 196:132] + node _T_197 = and(_T_195, _T_196) @[el2_lsu_bus_buffer.scala 196:114] + node _T_198 = bits(buf_byteen[1], 2, 2) @[el2_lsu_bus_buffer.scala 196:110] + node _T_199 = and(ld_addr_hitvec_hi_1, _T_198) @[el2_lsu_bus_buffer.scala 196:95] + node _T_200 = bits(ldst_byteen_hi_m, 2, 2) @[el2_lsu_bus_buffer.scala 196:132] + node _T_201 = and(_T_199, _T_200) @[el2_lsu_bus_buffer.scala 196:114] + node _T_202 = bits(buf_byteen[2], 2, 2) @[el2_lsu_bus_buffer.scala 196:110] + node _T_203 = and(ld_addr_hitvec_hi_2, _T_202) @[el2_lsu_bus_buffer.scala 196:95] + node _T_204 = bits(ldst_byteen_hi_m, 2, 2) @[el2_lsu_bus_buffer.scala 196:132] + node _T_205 = and(_T_203, _T_204) @[el2_lsu_bus_buffer.scala 196:114] + node _T_206 = bits(buf_byteen[3], 2, 2) @[el2_lsu_bus_buffer.scala 196:110] + node _T_207 = and(ld_addr_hitvec_hi_3, _T_206) @[el2_lsu_bus_buffer.scala 196:95] + node _T_208 = bits(ldst_byteen_hi_m, 2, 2) @[el2_lsu_bus_buffer.scala 196:132] + node _T_209 = and(_T_207, _T_208) @[el2_lsu_bus_buffer.scala 196:114] node _T_210 = cat(_T_209, _T_205) @[Cat.scala 29:58] node _T_211 = cat(_T_210, _T_201) @[Cat.scala 29:58] node ld_byte_hitvec_hi_2 = cat(_T_211, _T_197) @[Cat.scala 29:58] - node _T_212 = bits(buf_byteen[0], 3, 3) @[el2_lsu_bus_buffer.scala 195:110] - node _T_213 = and(ld_addr_hitvec_hi_0, _T_212) @[el2_lsu_bus_buffer.scala 195:95] - node _T_214 = bits(ldst_byteen_hi_m, 3, 3) @[el2_lsu_bus_buffer.scala 195:132] - node _T_215 = and(_T_213, _T_214) @[el2_lsu_bus_buffer.scala 195:114] - node _T_216 = bits(buf_byteen[1], 3, 3) @[el2_lsu_bus_buffer.scala 195:110] - node _T_217 = and(ld_addr_hitvec_hi_1, _T_216) @[el2_lsu_bus_buffer.scala 195:95] - node _T_218 = bits(ldst_byteen_hi_m, 3, 3) @[el2_lsu_bus_buffer.scala 195:132] - node _T_219 = and(_T_217, _T_218) @[el2_lsu_bus_buffer.scala 195:114] - node _T_220 = bits(buf_byteen[2], 3, 3) @[el2_lsu_bus_buffer.scala 195:110] - node _T_221 = and(ld_addr_hitvec_hi_2, _T_220) @[el2_lsu_bus_buffer.scala 195:95] - node _T_222 = bits(ldst_byteen_hi_m, 3, 3) @[el2_lsu_bus_buffer.scala 195:132] - node _T_223 = and(_T_221, _T_222) @[el2_lsu_bus_buffer.scala 195:114] - node _T_224 = bits(buf_byteen[3], 3, 3) @[el2_lsu_bus_buffer.scala 195:110] - node _T_225 = and(ld_addr_hitvec_hi_3, _T_224) @[el2_lsu_bus_buffer.scala 195:95] - node _T_226 = bits(ldst_byteen_hi_m, 3, 3) @[el2_lsu_bus_buffer.scala 195:132] - node _T_227 = and(_T_225, _T_226) @[el2_lsu_bus_buffer.scala 195:114] + node _T_212 = bits(buf_byteen[0], 3, 3) @[el2_lsu_bus_buffer.scala 196:110] + node _T_213 = and(ld_addr_hitvec_hi_0, _T_212) @[el2_lsu_bus_buffer.scala 196:95] + node _T_214 = bits(ldst_byteen_hi_m, 3, 3) @[el2_lsu_bus_buffer.scala 196:132] + node _T_215 = and(_T_213, _T_214) @[el2_lsu_bus_buffer.scala 196:114] + node _T_216 = bits(buf_byteen[1], 3, 3) @[el2_lsu_bus_buffer.scala 196:110] + node _T_217 = and(ld_addr_hitvec_hi_1, _T_216) @[el2_lsu_bus_buffer.scala 196:95] + node _T_218 = bits(ldst_byteen_hi_m, 3, 3) @[el2_lsu_bus_buffer.scala 196:132] + node _T_219 = and(_T_217, _T_218) @[el2_lsu_bus_buffer.scala 196:114] + node _T_220 = bits(buf_byteen[2], 3, 3) @[el2_lsu_bus_buffer.scala 196:110] + node _T_221 = and(ld_addr_hitvec_hi_2, _T_220) @[el2_lsu_bus_buffer.scala 196:95] + node _T_222 = bits(ldst_byteen_hi_m, 3, 3) @[el2_lsu_bus_buffer.scala 196:132] + node _T_223 = and(_T_221, _T_222) @[el2_lsu_bus_buffer.scala 196:114] + node _T_224 = bits(buf_byteen[3], 3, 3) @[el2_lsu_bus_buffer.scala 196:110] + node _T_225 = and(ld_addr_hitvec_hi_3, _T_224) @[el2_lsu_bus_buffer.scala 196:95] + node _T_226 = bits(ldst_byteen_hi_m, 3, 3) @[el2_lsu_bus_buffer.scala 196:132] + node _T_227 = and(_T_225, _T_226) @[el2_lsu_bus_buffer.scala 196:114] node _T_228 = cat(_T_227, _T_223) @[Cat.scala 29:58] node _T_229 = cat(_T_228, _T_219) @[Cat.scala 29:58] node ld_byte_hitvec_hi_3 = cat(_T_229, _T_215) @[Cat.scala 29:58] - wire buf_age_younger : UInt<4>[4] @[el2_lsu_bus_buffer.scala 197:29] - buf_age_younger[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 198:19] - buf_age_younger[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 198:19] - buf_age_younger[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 198:19] - buf_age_younger[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 198:19] - node _T_230 = bits(ld_byte_hitvec_lo_0, 0, 0) @[el2_lsu_bus_buffer.scala 199:93] - node _T_231 = and(ld_byte_hitvec_lo_0, buf_age_younger[0]) @[el2_lsu_bus_buffer.scala 199:122] - node _T_232 = orr(_T_231) @[el2_lsu_bus_buffer.scala 199:144] - node _T_233 = eq(_T_232, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] - node _T_234 = and(_T_230, _T_233) @[el2_lsu_bus_buffer.scala 199:97] - node _T_235 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[el2_lsu_bus_buffer.scala 199:170] - node _T_236 = eq(_T_235, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] - node _T_237 = and(_T_234, _T_236) @[el2_lsu_bus_buffer.scala 199:148] - node _T_238 = bits(ld_byte_hitvec_lo_0, 1, 1) @[el2_lsu_bus_buffer.scala 199:93] - node _T_239 = and(ld_byte_hitvec_lo_0, buf_age_younger[1]) @[el2_lsu_bus_buffer.scala 199:122] - node _T_240 = orr(_T_239) @[el2_lsu_bus_buffer.scala 199:144] - node _T_241 = eq(_T_240, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] - node _T_242 = and(_T_238, _T_241) @[el2_lsu_bus_buffer.scala 199:97] - node _T_243 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[el2_lsu_bus_buffer.scala 199:170] - node _T_244 = eq(_T_243, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] - node _T_245 = and(_T_242, _T_244) @[el2_lsu_bus_buffer.scala 199:148] - node _T_246 = bits(ld_byte_hitvec_lo_0, 2, 2) @[el2_lsu_bus_buffer.scala 199:93] - node _T_247 = and(ld_byte_hitvec_lo_0, buf_age_younger[2]) @[el2_lsu_bus_buffer.scala 199:122] - node _T_248 = orr(_T_247) @[el2_lsu_bus_buffer.scala 199:144] - node _T_249 = eq(_T_248, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] - node _T_250 = and(_T_246, _T_249) @[el2_lsu_bus_buffer.scala 199:97] - node _T_251 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[el2_lsu_bus_buffer.scala 199:170] - node _T_252 = eq(_T_251, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] - node _T_253 = and(_T_250, _T_252) @[el2_lsu_bus_buffer.scala 199:148] - node _T_254 = bits(ld_byte_hitvec_lo_0, 3, 3) @[el2_lsu_bus_buffer.scala 199:93] - node _T_255 = and(ld_byte_hitvec_lo_0, buf_age_younger[3]) @[el2_lsu_bus_buffer.scala 199:122] - node _T_256 = orr(_T_255) @[el2_lsu_bus_buffer.scala 199:144] - node _T_257 = eq(_T_256, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] - node _T_258 = and(_T_254, _T_257) @[el2_lsu_bus_buffer.scala 199:97] - node _T_259 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[el2_lsu_bus_buffer.scala 199:170] - node _T_260 = eq(_T_259, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] - node _T_261 = and(_T_258, _T_260) @[el2_lsu_bus_buffer.scala 199:148] + wire buf_age_younger : UInt<4>[4] @[el2_lsu_bus_buffer.scala 198:29] + buf_age_younger[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 199:19] + buf_age_younger[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 199:19] + buf_age_younger[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 199:19] + buf_age_younger[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 199:19] + node _T_230 = bits(ld_byte_hitvec_lo_0, 0, 0) @[el2_lsu_bus_buffer.scala 200:93] + node _T_231 = and(ld_byte_hitvec_lo_0, buf_age_younger[0]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_232 = orr(_T_231) @[el2_lsu_bus_buffer.scala 200:144] + node _T_233 = eq(_T_232, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_234 = and(_T_230, _T_233) @[el2_lsu_bus_buffer.scala 200:97] + node _T_235 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[el2_lsu_bus_buffer.scala 200:170] + node _T_236 = eq(_T_235, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_237 = and(_T_234, _T_236) @[el2_lsu_bus_buffer.scala 200:148] + node _T_238 = bits(ld_byte_hitvec_lo_0, 1, 1) @[el2_lsu_bus_buffer.scala 200:93] + node _T_239 = and(ld_byte_hitvec_lo_0, buf_age_younger[1]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_240 = orr(_T_239) @[el2_lsu_bus_buffer.scala 200:144] + node _T_241 = eq(_T_240, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_242 = and(_T_238, _T_241) @[el2_lsu_bus_buffer.scala 200:97] + node _T_243 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[el2_lsu_bus_buffer.scala 200:170] + node _T_244 = eq(_T_243, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_245 = and(_T_242, _T_244) @[el2_lsu_bus_buffer.scala 200:148] + node _T_246 = bits(ld_byte_hitvec_lo_0, 2, 2) @[el2_lsu_bus_buffer.scala 200:93] + node _T_247 = and(ld_byte_hitvec_lo_0, buf_age_younger[2]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_248 = orr(_T_247) @[el2_lsu_bus_buffer.scala 200:144] + node _T_249 = eq(_T_248, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_250 = and(_T_246, _T_249) @[el2_lsu_bus_buffer.scala 200:97] + node _T_251 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[el2_lsu_bus_buffer.scala 200:170] + node _T_252 = eq(_T_251, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_253 = and(_T_250, _T_252) @[el2_lsu_bus_buffer.scala 200:148] + node _T_254 = bits(ld_byte_hitvec_lo_0, 3, 3) @[el2_lsu_bus_buffer.scala 200:93] + node _T_255 = and(ld_byte_hitvec_lo_0, buf_age_younger[3]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_256 = orr(_T_255) @[el2_lsu_bus_buffer.scala 200:144] + node _T_257 = eq(_T_256, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_258 = and(_T_254, _T_257) @[el2_lsu_bus_buffer.scala 200:97] + node _T_259 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[el2_lsu_bus_buffer.scala 200:170] + node _T_260 = eq(_T_259, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_261 = and(_T_258, _T_260) @[el2_lsu_bus_buffer.scala 200:148] node _T_262 = cat(_T_261, _T_253) @[Cat.scala 29:58] node _T_263 = cat(_T_262, _T_245) @[Cat.scala 29:58] node _T_264 = cat(_T_263, _T_237) @[Cat.scala 29:58] - node _T_265 = bits(ld_byte_hitvec_lo_1, 0, 0) @[el2_lsu_bus_buffer.scala 199:93] - node _T_266 = and(ld_byte_hitvec_lo_1, buf_age_younger[0]) @[el2_lsu_bus_buffer.scala 199:122] - node _T_267 = orr(_T_266) @[el2_lsu_bus_buffer.scala 199:144] - node _T_268 = eq(_T_267, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] - node _T_269 = and(_T_265, _T_268) @[el2_lsu_bus_buffer.scala 199:97] - node _T_270 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[el2_lsu_bus_buffer.scala 199:170] - node _T_271 = eq(_T_270, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] - node _T_272 = and(_T_269, _T_271) @[el2_lsu_bus_buffer.scala 199:148] - node _T_273 = bits(ld_byte_hitvec_lo_1, 1, 1) @[el2_lsu_bus_buffer.scala 199:93] - node _T_274 = and(ld_byte_hitvec_lo_1, buf_age_younger[1]) @[el2_lsu_bus_buffer.scala 199:122] - node _T_275 = orr(_T_274) @[el2_lsu_bus_buffer.scala 199:144] - node _T_276 = eq(_T_275, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] - node _T_277 = and(_T_273, _T_276) @[el2_lsu_bus_buffer.scala 199:97] - node _T_278 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[el2_lsu_bus_buffer.scala 199:170] - node _T_279 = eq(_T_278, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] - node _T_280 = and(_T_277, _T_279) @[el2_lsu_bus_buffer.scala 199:148] - node _T_281 = bits(ld_byte_hitvec_lo_1, 2, 2) @[el2_lsu_bus_buffer.scala 199:93] - node _T_282 = and(ld_byte_hitvec_lo_1, buf_age_younger[2]) @[el2_lsu_bus_buffer.scala 199:122] - node _T_283 = orr(_T_282) @[el2_lsu_bus_buffer.scala 199:144] - node _T_284 = eq(_T_283, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] - node _T_285 = and(_T_281, _T_284) @[el2_lsu_bus_buffer.scala 199:97] - node _T_286 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[el2_lsu_bus_buffer.scala 199:170] - node _T_287 = eq(_T_286, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] - node _T_288 = and(_T_285, _T_287) @[el2_lsu_bus_buffer.scala 199:148] - node _T_289 = bits(ld_byte_hitvec_lo_1, 3, 3) @[el2_lsu_bus_buffer.scala 199:93] - node _T_290 = and(ld_byte_hitvec_lo_1, buf_age_younger[3]) @[el2_lsu_bus_buffer.scala 199:122] - node _T_291 = orr(_T_290) @[el2_lsu_bus_buffer.scala 199:144] - node _T_292 = eq(_T_291, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] - node _T_293 = and(_T_289, _T_292) @[el2_lsu_bus_buffer.scala 199:97] - node _T_294 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[el2_lsu_bus_buffer.scala 199:170] - node _T_295 = eq(_T_294, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] - node _T_296 = and(_T_293, _T_295) @[el2_lsu_bus_buffer.scala 199:148] + node _T_265 = bits(ld_byte_hitvec_lo_1, 0, 0) @[el2_lsu_bus_buffer.scala 200:93] + node _T_266 = and(ld_byte_hitvec_lo_1, buf_age_younger[0]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_267 = orr(_T_266) @[el2_lsu_bus_buffer.scala 200:144] + node _T_268 = eq(_T_267, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_269 = and(_T_265, _T_268) @[el2_lsu_bus_buffer.scala 200:97] + node _T_270 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[el2_lsu_bus_buffer.scala 200:170] + node _T_271 = eq(_T_270, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_272 = and(_T_269, _T_271) @[el2_lsu_bus_buffer.scala 200:148] + node _T_273 = bits(ld_byte_hitvec_lo_1, 1, 1) @[el2_lsu_bus_buffer.scala 200:93] + node _T_274 = and(ld_byte_hitvec_lo_1, buf_age_younger[1]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_275 = orr(_T_274) @[el2_lsu_bus_buffer.scala 200:144] + node _T_276 = eq(_T_275, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_277 = and(_T_273, _T_276) @[el2_lsu_bus_buffer.scala 200:97] + node _T_278 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[el2_lsu_bus_buffer.scala 200:170] + node _T_279 = eq(_T_278, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_280 = and(_T_277, _T_279) @[el2_lsu_bus_buffer.scala 200:148] + node _T_281 = bits(ld_byte_hitvec_lo_1, 2, 2) @[el2_lsu_bus_buffer.scala 200:93] + node _T_282 = and(ld_byte_hitvec_lo_1, buf_age_younger[2]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_283 = orr(_T_282) @[el2_lsu_bus_buffer.scala 200:144] + node _T_284 = eq(_T_283, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_285 = and(_T_281, _T_284) @[el2_lsu_bus_buffer.scala 200:97] + node _T_286 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[el2_lsu_bus_buffer.scala 200:170] + node _T_287 = eq(_T_286, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_288 = and(_T_285, _T_287) @[el2_lsu_bus_buffer.scala 200:148] + node _T_289 = bits(ld_byte_hitvec_lo_1, 3, 3) @[el2_lsu_bus_buffer.scala 200:93] + node _T_290 = and(ld_byte_hitvec_lo_1, buf_age_younger[3]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_291 = orr(_T_290) @[el2_lsu_bus_buffer.scala 200:144] + node _T_292 = eq(_T_291, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_293 = and(_T_289, _T_292) @[el2_lsu_bus_buffer.scala 200:97] + node _T_294 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[el2_lsu_bus_buffer.scala 200:170] + node _T_295 = eq(_T_294, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_296 = and(_T_293, _T_295) @[el2_lsu_bus_buffer.scala 200:148] node _T_297 = cat(_T_296, _T_288) @[Cat.scala 29:58] node _T_298 = cat(_T_297, _T_280) @[Cat.scala 29:58] node _T_299 = cat(_T_298, _T_272) @[Cat.scala 29:58] - node _T_300 = bits(ld_byte_hitvec_lo_2, 0, 0) @[el2_lsu_bus_buffer.scala 199:93] - node _T_301 = and(ld_byte_hitvec_lo_2, buf_age_younger[0]) @[el2_lsu_bus_buffer.scala 199:122] - node _T_302 = orr(_T_301) @[el2_lsu_bus_buffer.scala 199:144] - node _T_303 = eq(_T_302, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] - node _T_304 = and(_T_300, _T_303) @[el2_lsu_bus_buffer.scala 199:97] - node _T_305 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[el2_lsu_bus_buffer.scala 199:170] - node _T_306 = eq(_T_305, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] - node _T_307 = and(_T_304, _T_306) @[el2_lsu_bus_buffer.scala 199:148] - node _T_308 = bits(ld_byte_hitvec_lo_2, 1, 1) @[el2_lsu_bus_buffer.scala 199:93] - node _T_309 = and(ld_byte_hitvec_lo_2, buf_age_younger[1]) @[el2_lsu_bus_buffer.scala 199:122] - node _T_310 = orr(_T_309) @[el2_lsu_bus_buffer.scala 199:144] - node _T_311 = eq(_T_310, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] - node _T_312 = and(_T_308, _T_311) @[el2_lsu_bus_buffer.scala 199:97] - node _T_313 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[el2_lsu_bus_buffer.scala 199:170] - node _T_314 = eq(_T_313, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] - node _T_315 = and(_T_312, _T_314) @[el2_lsu_bus_buffer.scala 199:148] - node _T_316 = bits(ld_byte_hitvec_lo_2, 2, 2) @[el2_lsu_bus_buffer.scala 199:93] - node _T_317 = and(ld_byte_hitvec_lo_2, buf_age_younger[2]) @[el2_lsu_bus_buffer.scala 199:122] - node _T_318 = orr(_T_317) @[el2_lsu_bus_buffer.scala 199:144] - node _T_319 = eq(_T_318, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] - node _T_320 = and(_T_316, _T_319) @[el2_lsu_bus_buffer.scala 199:97] - node _T_321 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[el2_lsu_bus_buffer.scala 199:170] - node _T_322 = eq(_T_321, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] - node _T_323 = and(_T_320, _T_322) @[el2_lsu_bus_buffer.scala 199:148] - node _T_324 = bits(ld_byte_hitvec_lo_2, 3, 3) @[el2_lsu_bus_buffer.scala 199:93] - node _T_325 = and(ld_byte_hitvec_lo_2, buf_age_younger[3]) @[el2_lsu_bus_buffer.scala 199:122] - node _T_326 = orr(_T_325) @[el2_lsu_bus_buffer.scala 199:144] - node _T_327 = eq(_T_326, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] - node _T_328 = and(_T_324, _T_327) @[el2_lsu_bus_buffer.scala 199:97] - node _T_329 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[el2_lsu_bus_buffer.scala 199:170] - node _T_330 = eq(_T_329, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] - node _T_331 = and(_T_328, _T_330) @[el2_lsu_bus_buffer.scala 199:148] + node _T_300 = bits(ld_byte_hitvec_lo_2, 0, 0) @[el2_lsu_bus_buffer.scala 200:93] + node _T_301 = and(ld_byte_hitvec_lo_2, buf_age_younger[0]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_302 = orr(_T_301) @[el2_lsu_bus_buffer.scala 200:144] + node _T_303 = eq(_T_302, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_304 = and(_T_300, _T_303) @[el2_lsu_bus_buffer.scala 200:97] + node _T_305 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[el2_lsu_bus_buffer.scala 200:170] + node _T_306 = eq(_T_305, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_307 = and(_T_304, _T_306) @[el2_lsu_bus_buffer.scala 200:148] + node _T_308 = bits(ld_byte_hitvec_lo_2, 1, 1) @[el2_lsu_bus_buffer.scala 200:93] + node _T_309 = and(ld_byte_hitvec_lo_2, buf_age_younger[1]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_310 = orr(_T_309) @[el2_lsu_bus_buffer.scala 200:144] + node _T_311 = eq(_T_310, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_312 = and(_T_308, _T_311) @[el2_lsu_bus_buffer.scala 200:97] + node _T_313 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[el2_lsu_bus_buffer.scala 200:170] + node _T_314 = eq(_T_313, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_315 = and(_T_312, _T_314) @[el2_lsu_bus_buffer.scala 200:148] + node _T_316 = bits(ld_byte_hitvec_lo_2, 2, 2) @[el2_lsu_bus_buffer.scala 200:93] + node _T_317 = and(ld_byte_hitvec_lo_2, buf_age_younger[2]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_318 = orr(_T_317) @[el2_lsu_bus_buffer.scala 200:144] + node _T_319 = eq(_T_318, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_320 = and(_T_316, _T_319) @[el2_lsu_bus_buffer.scala 200:97] + node _T_321 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[el2_lsu_bus_buffer.scala 200:170] + node _T_322 = eq(_T_321, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_323 = and(_T_320, _T_322) @[el2_lsu_bus_buffer.scala 200:148] + node _T_324 = bits(ld_byte_hitvec_lo_2, 3, 3) @[el2_lsu_bus_buffer.scala 200:93] + node _T_325 = and(ld_byte_hitvec_lo_2, buf_age_younger[3]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_326 = orr(_T_325) @[el2_lsu_bus_buffer.scala 200:144] + node _T_327 = eq(_T_326, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_328 = and(_T_324, _T_327) @[el2_lsu_bus_buffer.scala 200:97] + node _T_329 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[el2_lsu_bus_buffer.scala 200:170] + node _T_330 = eq(_T_329, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_331 = and(_T_328, _T_330) @[el2_lsu_bus_buffer.scala 200:148] node _T_332 = cat(_T_331, _T_323) @[Cat.scala 29:58] node _T_333 = cat(_T_332, _T_315) @[Cat.scala 29:58] node _T_334 = cat(_T_333, _T_307) @[Cat.scala 29:58] - node _T_335 = bits(ld_byte_hitvec_lo_3, 0, 0) @[el2_lsu_bus_buffer.scala 199:93] - node _T_336 = and(ld_byte_hitvec_lo_3, buf_age_younger[0]) @[el2_lsu_bus_buffer.scala 199:122] - node _T_337 = orr(_T_336) @[el2_lsu_bus_buffer.scala 199:144] - node _T_338 = eq(_T_337, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] - node _T_339 = and(_T_335, _T_338) @[el2_lsu_bus_buffer.scala 199:97] - node _T_340 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[el2_lsu_bus_buffer.scala 199:170] - node _T_341 = eq(_T_340, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] - node _T_342 = and(_T_339, _T_341) @[el2_lsu_bus_buffer.scala 199:148] - node _T_343 = bits(ld_byte_hitvec_lo_3, 1, 1) @[el2_lsu_bus_buffer.scala 199:93] - node _T_344 = and(ld_byte_hitvec_lo_3, buf_age_younger[1]) @[el2_lsu_bus_buffer.scala 199:122] - node _T_345 = orr(_T_344) @[el2_lsu_bus_buffer.scala 199:144] - node _T_346 = eq(_T_345, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] - node _T_347 = and(_T_343, _T_346) @[el2_lsu_bus_buffer.scala 199:97] - node _T_348 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[el2_lsu_bus_buffer.scala 199:170] - node _T_349 = eq(_T_348, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] - node _T_350 = and(_T_347, _T_349) @[el2_lsu_bus_buffer.scala 199:148] - node _T_351 = bits(ld_byte_hitvec_lo_3, 2, 2) @[el2_lsu_bus_buffer.scala 199:93] - node _T_352 = and(ld_byte_hitvec_lo_3, buf_age_younger[2]) @[el2_lsu_bus_buffer.scala 199:122] - node _T_353 = orr(_T_352) @[el2_lsu_bus_buffer.scala 199:144] - node _T_354 = eq(_T_353, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] - node _T_355 = and(_T_351, _T_354) @[el2_lsu_bus_buffer.scala 199:97] - node _T_356 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[el2_lsu_bus_buffer.scala 199:170] - node _T_357 = eq(_T_356, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] - node _T_358 = and(_T_355, _T_357) @[el2_lsu_bus_buffer.scala 199:148] - node _T_359 = bits(ld_byte_hitvec_lo_3, 3, 3) @[el2_lsu_bus_buffer.scala 199:93] - node _T_360 = and(ld_byte_hitvec_lo_3, buf_age_younger[3]) @[el2_lsu_bus_buffer.scala 199:122] - node _T_361 = orr(_T_360) @[el2_lsu_bus_buffer.scala 199:144] - node _T_362 = eq(_T_361, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] - node _T_363 = and(_T_359, _T_362) @[el2_lsu_bus_buffer.scala 199:97] - node _T_364 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[el2_lsu_bus_buffer.scala 199:170] - node _T_365 = eq(_T_364, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] - node _T_366 = and(_T_363, _T_365) @[el2_lsu_bus_buffer.scala 199:148] + node _T_335 = bits(ld_byte_hitvec_lo_3, 0, 0) @[el2_lsu_bus_buffer.scala 200:93] + node _T_336 = and(ld_byte_hitvec_lo_3, buf_age_younger[0]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_337 = orr(_T_336) @[el2_lsu_bus_buffer.scala 200:144] + node _T_338 = eq(_T_337, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_339 = and(_T_335, _T_338) @[el2_lsu_bus_buffer.scala 200:97] + node _T_340 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[el2_lsu_bus_buffer.scala 200:170] + node _T_341 = eq(_T_340, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_342 = and(_T_339, _T_341) @[el2_lsu_bus_buffer.scala 200:148] + node _T_343 = bits(ld_byte_hitvec_lo_3, 1, 1) @[el2_lsu_bus_buffer.scala 200:93] + node _T_344 = and(ld_byte_hitvec_lo_3, buf_age_younger[1]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_345 = orr(_T_344) @[el2_lsu_bus_buffer.scala 200:144] + node _T_346 = eq(_T_345, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_347 = and(_T_343, _T_346) @[el2_lsu_bus_buffer.scala 200:97] + node _T_348 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[el2_lsu_bus_buffer.scala 200:170] + node _T_349 = eq(_T_348, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_350 = and(_T_347, _T_349) @[el2_lsu_bus_buffer.scala 200:148] + node _T_351 = bits(ld_byte_hitvec_lo_3, 2, 2) @[el2_lsu_bus_buffer.scala 200:93] + node _T_352 = and(ld_byte_hitvec_lo_3, buf_age_younger[2]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_353 = orr(_T_352) @[el2_lsu_bus_buffer.scala 200:144] + node _T_354 = eq(_T_353, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_355 = and(_T_351, _T_354) @[el2_lsu_bus_buffer.scala 200:97] + node _T_356 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[el2_lsu_bus_buffer.scala 200:170] + node _T_357 = eq(_T_356, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_358 = and(_T_355, _T_357) @[el2_lsu_bus_buffer.scala 200:148] + node _T_359 = bits(ld_byte_hitvec_lo_3, 3, 3) @[el2_lsu_bus_buffer.scala 200:93] + node _T_360 = and(ld_byte_hitvec_lo_3, buf_age_younger[3]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_361 = orr(_T_360) @[el2_lsu_bus_buffer.scala 200:144] + node _T_362 = eq(_T_361, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_363 = and(_T_359, _T_362) @[el2_lsu_bus_buffer.scala 200:97] + node _T_364 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[el2_lsu_bus_buffer.scala 200:170] + node _T_365 = eq(_T_364, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_366 = and(_T_363, _T_365) @[el2_lsu_bus_buffer.scala 200:148] node _T_367 = cat(_T_366, _T_358) @[Cat.scala 29:58] node _T_368 = cat(_T_367, _T_350) @[Cat.scala 29:58] node _T_369 = cat(_T_368, _T_342) @[Cat.scala 29:58] - ld_byte_hitvecfn_lo[0] <= _T_264 @[el2_lsu_bus_buffer.scala 199:23] - ld_byte_hitvecfn_lo[1] <= _T_299 @[el2_lsu_bus_buffer.scala 199:23] - ld_byte_hitvecfn_lo[2] <= _T_334 @[el2_lsu_bus_buffer.scala 199:23] - ld_byte_hitvecfn_lo[3] <= _T_369 @[el2_lsu_bus_buffer.scala 199:23] - node _T_370 = bits(ld_byte_hitvec_hi_0, 0, 0) @[el2_lsu_bus_buffer.scala 200:93] - node _T_371 = and(ld_byte_hitvec_hi_0, buf_age_younger[0]) @[el2_lsu_bus_buffer.scala 200:122] - node _T_372 = orr(_T_371) @[el2_lsu_bus_buffer.scala 200:144] - node _T_373 = eq(_T_372, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] - node _T_374 = and(_T_370, _T_373) @[el2_lsu_bus_buffer.scala 200:97] - node _T_375 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[el2_lsu_bus_buffer.scala 200:170] - node _T_376 = eq(_T_375, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] - node _T_377 = and(_T_374, _T_376) @[el2_lsu_bus_buffer.scala 200:148] - node _T_378 = bits(ld_byte_hitvec_hi_0, 1, 1) @[el2_lsu_bus_buffer.scala 200:93] - node _T_379 = and(ld_byte_hitvec_hi_0, buf_age_younger[1]) @[el2_lsu_bus_buffer.scala 200:122] - node _T_380 = orr(_T_379) @[el2_lsu_bus_buffer.scala 200:144] - node _T_381 = eq(_T_380, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] - node _T_382 = and(_T_378, _T_381) @[el2_lsu_bus_buffer.scala 200:97] - node _T_383 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[el2_lsu_bus_buffer.scala 200:170] - node _T_384 = eq(_T_383, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] - node _T_385 = and(_T_382, _T_384) @[el2_lsu_bus_buffer.scala 200:148] - node _T_386 = bits(ld_byte_hitvec_hi_0, 2, 2) @[el2_lsu_bus_buffer.scala 200:93] - node _T_387 = and(ld_byte_hitvec_hi_0, buf_age_younger[2]) @[el2_lsu_bus_buffer.scala 200:122] - node _T_388 = orr(_T_387) @[el2_lsu_bus_buffer.scala 200:144] - node _T_389 = eq(_T_388, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] - node _T_390 = and(_T_386, _T_389) @[el2_lsu_bus_buffer.scala 200:97] - node _T_391 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[el2_lsu_bus_buffer.scala 200:170] - node _T_392 = eq(_T_391, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] - node _T_393 = and(_T_390, _T_392) @[el2_lsu_bus_buffer.scala 200:148] - node _T_394 = bits(ld_byte_hitvec_hi_0, 3, 3) @[el2_lsu_bus_buffer.scala 200:93] - node _T_395 = and(ld_byte_hitvec_hi_0, buf_age_younger[3]) @[el2_lsu_bus_buffer.scala 200:122] - node _T_396 = orr(_T_395) @[el2_lsu_bus_buffer.scala 200:144] - node _T_397 = eq(_T_396, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] - node _T_398 = and(_T_394, _T_397) @[el2_lsu_bus_buffer.scala 200:97] - node _T_399 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[el2_lsu_bus_buffer.scala 200:170] - node _T_400 = eq(_T_399, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] - node _T_401 = and(_T_398, _T_400) @[el2_lsu_bus_buffer.scala 200:148] + ld_byte_hitvecfn_lo[0] <= _T_264 @[el2_lsu_bus_buffer.scala 200:23] + ld_byte_hitvecfn_lo[1] <= _T_299 @[el2_lsu_bus_buffer.scala 200:23] + ld_byte_hitvecfn_lo[2] <= _T_334 @[el2_lsu_bus_buffer.scala 200:23] + ld_byte_hitvecfn_lo[3] <= _T_369 @[el2_lsu_bus_buffer.scala 200:23] + node _T_370 = bits(ld_byte_hitvec_hi_0, 0, 0) @[el2_lsu_bus_buffer.scala 201:93] + node _T_371 = and(ld_byte_hitvec_hi_0, buf_age_younger[0]) @[el2_lsu_bus_buffer.scala 201:122] + node _T_372 = orr(_T_371) @[el2_lsu_bus_buffer.scala 201:144] + node _T_373 = eq(_T_372, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 201:99] + node _T_374 = and(_T_370, _T_373) @[el2_lsu_bus_buffer.scala 201:97] + node _T_375 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[el2_lsu_bus_buffer.scala 201:170] + node _T_376 = eq(_T_375, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 201:150] + node _T_377 = and(_T_374, _T_376) @[el2_lsu_bus_buffer.scala 201:148] + node _T_378 = bits(ld_byte_hitvec_hi_0, 1, 1) @[el2_lsu_bus_buffer.scala 201:93] + node _T_379 = and(ld_byte_hitvec_hi_0, buf_age_younger[1]) @[el2_lsu_bus_buffer.scala 201:122] + node _T_380 = orr(_T_379) @[el2_lsu_bus_buffer.scala 201:144] + node _T_381 = eq(_T_380, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 201:99] + node _T_382 = and(_T_378, _T_381) @[el2_lsu_bus_buffer.scala 201:97] + node _T_383 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[el2_lsu_bus_buffer.scala 201:170] + node _T_384 = eq(_T_383, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 201:150] + node _T_385 = and(_T_382, _T_384) @[el2_lsu_bus_buffer.scala 201:148] + node _T_386 = bits(ld_byte_hitvec_hi_0, 2, 2) @[el2_lsu_bus_buffer.scala 201:93] + node _T_387 = and(ld_byte_hitvec_hi_0, buf_age_younger[2]) @[el2_lsu_bus_buffer.scala 201:122] + node _T_388 = orr(_T_387) @[el2_lsu_bus_buffer.scala 201:144] + node _T_389 = eq(_T_388, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 201:99] + node _T_390 = and(_T_386, _T_389) @[el2_lsu_bus_buffer.scala 201:97] + node _T_391 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[el2_lsu_bus_buffer.scala 201:170] + node _T_392 = eq(_T_391, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 201:150] + node _T_393 = and(_T_390, _T_392) @[el2_lsu_bus_buffer.scala 201:148] + node _T_394 = bits(ld_byte_hitvec_hi_0, 3, 3) @[el2_lsu_bus_buffer.scala 201:93] + node _T_395 = and(ld_byte_hitvec_hi_0, buf_age_younger[3]) @[el2_lsu_bus_buffer.scala 201:122] + node _T_396 = orr(_T_395) @[el2_lsu_bus_buffer.scala 201:144] + node _T_397 = eq(_T_396, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 201:99] + node _T_398 = and(_T_394, _T_397) @[el2_lsu_bus_buffer.scala 201:97] + node _T_399 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[el2_lsu_bus_buffer.scala 201:170] + node _T_400 = eq(_T_399, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 201:150] + node _T_401 = and(_T_398, _T_400) @[el2_lsu_bus_buffer.scala 201:148] node _T_402 = cat(_T_401, _T_393) @[Cat.scala 29:58] node _T_403 = cat(_T_402, _T_385) @[Cat.scala 29:58] node _T_404 = cat(_T_403, _T_377) @[Cat.scala 29:58] - node _T_405 = bits(ld_byte_hitvec_hi_1, 0, 0) @[el2_lsu_bus_buffer.scala 200:93] - node _T_406 = and(ld_byte_hitvec_hi_1, buf_age_younger[0]) @[el2_lsu_bus_buffer.scala 200:122] - node _T_407 = orr(_T_406) @[el2_lsu_bus_buffer.scala 200:144] - node _T_408 = eq(_T_407, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] - node _T_409 = and(_T_405, _T_408) @[el2_lsu_bus_buffer.scala 200:97] - node _T_410 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[el2_lsu_bus_buffer.scala 200:170] - node _T_411 = eq(_T_410, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] - node _T_412 = and(_T_409, _T_411) @[el2_lsu_bus_buffer.scala 200:148] - node _T_413 = bits(ld_byte_hitvec_hi_1, 1, 1) @[el2_lsu_bus_buffer.scala 200:93] - node _T_414 = and(ld_byte_hitvec_hi_1, buf_age_younger[1]) @[el2_lsu_bus_buffer.scala 200:122] - node _T_415 = orr(_T_414) @[el2_lsu_bus_buffer.scala 200:144] - node _T_416 = eq(_T_415, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] - node _T_417 = and(_T_413, _T_416) @[el2_lsu_bus_buffer.scala 200:97] - node _T_418 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[el2_lsu_bus_buffer.scala 200:170] - node _T_419 = eq(_T_418, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] - node _T_420 = and(_T_417, _T_419) @[el2_lsu_bus_buffer.scala 200:148] - node _T_421 = bits(ld_byte_hitvec_hi_1, 2, 2) @[el2_lsu_bus_buffer.scala 200:93] - node _T_422 = and(ld_byte_hitvec_hi_1, buf_age_younger[2]) @[el2_lsu_bus_buffer.scala 200:122] - node _T_423 = orr(_T_422) @[el2_lsu_bus_buffer.scala 200:144] - node _T_424 = eq(_T_423, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] - node _T_425 = and(_T_421, _T_424) @[el2_lsu_bus_buffer.scala 200:97] - node _T_426 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[el2_lsu_bus_buffer.scala 200:170] - node _T_427 = eq(_T_426, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] - node _T_428 = and(_T_425, _T_427) @[el2_lsu_bus_buffer.scala 200:148] - node _T_429 = bits(ld_byte_hitvec_hi_1, 3, 3) @[el2_lsu_bus_buffer.scala 200:93] - node _T_430 = and(ld_byte_hitvec_hi_1, buf_age_younger[3]) @[el2_lsu_bus_buffer.scala 200:122] - node _T_431 = orr(_T_430) @[el2_lsu_bus_buffer.scala 200:144] - node _T_432 = eq(_T_431, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] - node _T_433 = and(_T_429, _T_432) @[el2_lsu_bus_buffer.scala 200:97] - node _T_434 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[el2_lsu_bus_buffer.scala 200:170] - node _T_435 = eq(_T_434, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] - node _T_436 = and(_T_433, _T_435) @[el2_lsu_bus_buffer.scala 200:148] + node _T_405 = bits(ld_byte_hitvec_hi_1, 0, 0) @[el2_lsu_bus_buffer.scala 201:93] + node _T_406 = and(ld_byte_hitvec_hi_1, buf_age_younger[0]) @[el2_lsu_bus_buffer.scala 201:122] + node _T_407 = orr(_T_406) @[el2_lsu_bus_buffer.scala 201:144] + node _T_408 = eq(_T_407, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 201:99] + node _T_409 = and(_T_405, _T_408) @[el2_lsu_bus_buffer.scala 201:97] + node _T_410 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[el2_lsu_bus_buffer.scala 201:170] + node _T_411 = eq(_T_410, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 201:150] + node _T_412 = and(_T_409, _T_411) @[el2_lsu_bus_buffer.scala 201:148] + node _T_413 = bits(ld_byte_hitvec_hi_1, 1, 1) @[el2_lsu_bus_buffer.scala 201:93] + node _T_414 = and(ld_byte_hitvec_hi_1, buf_age_younger[1]) @[el2_lsu_bus_buffer.scala 201:122] + node _T_415 = orr(_T_414) @[el2_lsu_bus_buffer.scala 201:144] + node _T_416 = eq(_T_415, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 201:99] + node _T_417 = and(_T_413, _T_416) @[el2_lsu_bus_buffer.scala 201:97] + node _T_418 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[el2_lsu_bus_buffer.scala 201:170] + node _T_419 = eq(_T_418, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 201:150] + node _T_420 = and(_T_417, _T_419) @[el2_lsu_bus_buffer.scala 201:148] + node _T_421 = bits(ld_byte_hitvec_hi_1, 2, 2) @[el2_lsu_bus_buffer.scala 201:93] + node _T_422 = and(ld_byte_hitvec_hi_1, buf_age_younger[2]) @[el2_lsu_bus_buffer.scala 201:122] + node _T_423 = orr(_T_422) @[el2_lsu_bus_buffer.scala 201:144] + node _T_424 = eq(_T_423, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 201:99] + node _T_425 = and(_T_421, _T_424) @[el2_lsu_bus_buffer.scala 201:97] + node _T_426 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[el2_lsu_bus_buffer.scala 201:170] + node _T_427 = eq(_T_426, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 201:150] + node _T_428 = and(_T_425, _T_427) @[el2_lsu_bus_buffer.scala 201:148] + node _T_429 = bits(ld_byte_hitvec_hi_1, 3, 3) @[el2_lsu_bus_buffer.scala 201:93] + node _T_430 = and(ld_byte_hitvec_hi_1, buf_age_younger[3]) @[el2_lsu_bus_buffer.scala 201:122] + node _T_431 = orr(_T_430) @[el2_lsu_bus_buffer.scala 201:144] + node _T_432 = eq(_T_431, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 201:99] + node _T_433 = and(_T_429, _T_432) @[el2_lsu_bus_buffer.scala 201:97] + node _T_434 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[el2_lsu_bus_buffer.scala 201:170] + node _T_435 = eq(_T_434, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 201:150] + node _T_436 = and(_T_433, _T_435) @[el2_lsu_bus_buffer.scala 201:148] node _T_437 = cat(_T_436, _T_428) @[Cat.scala 29:58] node _T_438 = cat(_T_437, _T_420) @[Cat.scala 29:58] node _T_439 = cat(_T_438, _T_412) @[Cat.scala 29:58] - node _T_440 = bits(ld_byte_hitvec_hi_2, 0, 0) @[el2_lsu_bus_buffer.scala 200:93] - node _T_441 = and(ld_byte_hitvec_hi_2, buf_age_younger[0]) @[el2_lsu_bus_buffer.scala 200:122] - node _T_442 = orr(_T_441) @[el2_lsu_bus_buffer.scala 200:144] - node _T_443 = eq(_T_442, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] - node _T_444 = and(_T_440, _T_443) @[el2_lsu_bus_buffer.scala 200:97] - node _T_445 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[el2_lsu_bus_buffer.scala 200:170] - node _T_446 = eq(_T_445, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] - node _T_447 = and(_T_444, _T_446) @[el2_lsu_bus_buffer.scala 200:148] - node _T_448 = bits(ld_byte_hitvec_hi_2, 1, 1) @[el2_lsu_bus_buffer.scala 200:93] - node _T_449 = and(ld_byte_hitvec_hi_2, buf_age_younger[1]) @[el2_lsu_bus_buffer.scala 200:122] - node _T_450 = orr(_T_449) @[el2_lsu_bus_buffer.scala 200:144] - node _T_451 = eq(_T_450, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] - node _T_452 = and(_T_448, _T_451) @[el2_lsu_bus_buffer.scala 200:97] - node _T_453 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[el2_lsu_bus_buffer.scala 200:170] - node _T_454 = eq(_T_453, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] - node _T_455 = and(_T_452, _T_454) @[el2_lsu_bus_buffer.scala 200:148] - node _T_456 = bits(ld_byte_hitvec_hi_2, 2, 2) @[el2_lsu_bus_buffer.scala 200:93] - node _T_457 = and(ld_byte_hitvec_hi_2, buf_age_younger[2]) @[el2_lsu_bus_buffer.scala 200:122] - node _T_458 = orr(_T_457) @[el2_lsu_bus_buffer.scala 200:144] - node _T_459 = eq(_T_458, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] - node _T_460 = and(_T_456, _T_459) @[el2_lsu_bus_buffer.scala 200:97] - node _T_461 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[el2_lsu_bus_buffer.scala 200:170] - node _T_462 = eq(_T_461, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] - node _T_463 = and(_T_460, _T_462) @[el2_lsu_bus_buffer.scala 200:148] - node _T_464 = bits(ld_byte_hitvec_hi_2, 3, 3) @[el2_lsu_bus_buffer.scala 200:93] - node _T_465 = and(ld_byte_hitvec_hi_2, buf_age_younger[3]) @[el2_lsu_bus_buffer.scala 200:122] - node _T_466 = orr(_T_465) @[el2_lsu_bus_buffer.scala 200:144] - node _T_467 = eq(_T_466, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] - node _T_468 = and(_T_464, _T_467) @[el2_lsu_bus_buffer.scala 200:97] - node _T_469 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[el2_lsu_bus_buffer.scala 200:170] - node _T_470 = eq(_T_469, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] - node _T_471 = and(_T_468, _T_470) @[el2_lsu_bus_buffer.scala 200:148] + node _T_440 = bits(ld_byte_hitvec_hi_2, 0, 0) @[el2_lsu_bus_buffer.scala 201:93] + node _T_441 = and(ld_byte_hitvec_hi_2, buf_age_younger[0]) @[el2_lsu_bus_buffer.scala 201:122] + node _T_442 = orr(_T_441) @[el2_lsu_bus_buffer.scala 201:144] + node _T_443 = eq(_T_442, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 201:99] + node _T_444 = and(_T_440, _T_443) @[el2_lsu_bus_buffer.scala 201:97] + node _T_445 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[el2_lsu_bus_buffer.scala 201:170] + node _T_446 = eq(_T_445, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 201:150] + node _T_447 = and(_T_444, _T_446) @[el2_lsu_bus_buffer.scala 201:148] + node _T_448 = bits(ld_byte_hitvec_hi_2, 1, 1) @[el2_lsu_bus_buffer.scala 201:93] + node _T_449 = and(ld_byte_hitvec_hi_2, buf_age_younger[1]) @[el2_lsu_bus_buffer.scala 201:122] + node _T_450 = orr(_T_449) @[el2_lsu_bus_buffer.scala 201:144] + node _T_451 = eq(_T_450, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 201:99] + node _T_452 = and(_T_448, _T_451) @[el2_lsu_bus_buffer.scala 201:97] + node _T_453 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[el2_lsu_bus_buffer.scala 201:170] + node _T_454 = eq(_T_453, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 201:150] + node _T_455 = and(_T_452, _T_454) @[el2_lsu_bus_buffer.scala 201:148] + node _T_456 = bits(ld_byte_hitvec_hi_2, 2, 2) @[el2_lsu_bus_buffer.scala 201:93] + node _T_457 = and(ld_byte_hitvec_hi_2, buf_age_younger[2]) @[el2_lsu_bus_buffer.scala 201:122] + node _T_458 = orr(_T_457) @[el2_lsu_bus_buffer.scala 201:144] + node _T_459 = eq(_T_458, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 201:99] + node _T_460 = and(_T_456, _T_459) @[el2_lsu_bus_buffer.scala 201:97] + node _T_461 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[el2_lsu_bus_buffer.scala 201:170] + node _T_462 = eq(_T_461, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 201:150] + node _T_463 = and(_T_460, _T_462) @[el2_lsu_bus_buffer.scala 201:148] + node _T_464 = bits(ld_byte_hitvec_hi_2, 3, 3) @[el2_lsu_bus_buffer.scala 201:93] + node _T_465 = and(ld_byte_hitvec_hi_2, buf_age_younger[3]) @[el2_lsu_bus_buffer.scala 201:122] + node _T_466 = orr(_T_465) @[el2_lsu_bus_buffer.scala 201:144] + node _T_467 = eq(_T_466, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 201:99] + node _T_468 = and(_T_464, _T_467) @[el2_lsu_bus_buffer.scala 201:97] + node _T_469 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[el2_lsu_bus_buffer.scala 201:170] + node _T_470 = eq(_T_469, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 201:150] + node _T_471 = and(_T_468, _T_470) @[el2_lsu_bus_buffer.scala 201:148] node _T_472 = cat(_T_471, _T_463) @[Cat.scala 29:58] node _T_473 = cat(_T_472, _T_455) @[Cat.scala 29:58] node _T_474 = cat(_T_473, _T_447) @[Cat.scala 29:58] - node _T_475 = bits(ld_byte_hitvec_hi_3, 0, 0) @[el2_lsu_bus_buffer.scala 200:93] - node _T_476 = and(ld_byte_hitvec_hi_3, buf_age_younger[0]) @[el2_lsu_bus_buffer.scala 200:122] - node _T_477 = orr(_T_476) @[el2_lsu_bus_buffer.scala 200:144] - node _T_478 = eq(_T_477, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] - node _T_479 = and(_T_475, _T_478) @[el2_lsu_bus_buffer.scala 200:97] - node _T_480 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[el2_lsu_bus_buffer.scala 200:170] - node _T_481 = eq(_T_480, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] - node _T_482 = and(_T_479, _T_481) @[el2_lsu_bus_buffer.scala 200:148] - node _T_483 = bits(ld_byte_hitvec_hi_3, 1, 1) @[el2_lsu_bus_buffer.scala 200:93] - node _T_484 = and(ld_byte_hitvec_hi_3, buf_age_younger[1]) @[el2_lsu_bus_buffer.scala 200:122] - node _T_485 = orr(_T_484) @[el2_lsu_bus_buffer.scala 200:144] - node _T_486 = eq(_T_485, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] - node _T_487 = and(_T_483, _T_486) @[el2_lsu_bus_buffer.scala 200:97] - node _T_488 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[el2_lsu_bus_buffer.scala 200:170] - node _T_489 = eq(_T_488, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] - node _T_490 = and(_T_487, _T_489) @[el2_lsu_bus_buffer.scala 200:148] - node _T_491 = bits(ld_byte_hitvec_hi_3, 2, 2) @[el2_lsu_bus_buffer.scala 200:93] - node _T_492 = and(ld_byte_hitvec_hi_3, buf_age_younger[2]) @[el2_lsu_bus_buffer.scala 200:122] - node _T_493 = orr(_T_492) @[el2_lsu_bus_buffer.scala 200:144] - node _T_494 = eq(_T_493, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] - node _T_495 = and(_T_491, _T_494) @[el2_lsu_bus_buffer.scala 200:97] - node _T_496 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[el2_lsu_bus_buffer.scala 200:170] - node _T_497 = eq(_T_496, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] - node _T_498 = and(_T_495, _T_497) @[el2_lsu_bus_buffer.scala 200:148] - node _T_499 = bits(ld_byte_hitvec_hi_3, 3, 3) @[el2_lsu_bus_buffer.scala 200:93] - node _T_500 = and(ld_byte_hitvec_hi_3, buf_age_younger[3]) @[el2_lsu_bus_buffer.scala 200:122] - node _T_501 = orr(_T_500) @[el2_lsu_bus_buffer.scala 200:144] - node _T_502 = eq(_T_501, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] - node _T_503 = and(_T_499, _T_502) @[el2_lsu_bus_buffer.scala 200:97] - node _T_504 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[el2_lsu_bus_buffer.scala 200:170] - node _T_505 = eq(_T_504, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] - node _T_506 = and(_T_503, _T_505) @[el2_lsu_bus_buffer.scala 200:148] + node _T_475 = bits(ld_byte_hitvec_hi_3, 0, 0) @[el2_lsu_bus_buffer.scala 201:93] + node _T_476 = and(ld_byte_hitvec_hi_3, buf_age_younger[0]) @[el2_lsu_bus_buffer.scala 201:122] + node _T_477 = orr(_T_476) @[el2_lsu_bus_buffer.scala 201:144] + node _T_478 = eq(_T_477, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 201:99] + node _T_479 = and(_T_475, _T_478) @[el2_lsu_bus_buffer.scala 201:97] + node _T_480 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[el2_lsu_bus_buffer.scala 201:170] + node _T_481 = eq(_T_480, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 201:150] + node _T_482 = and(_T_479, _T_481) @[el2_lsu_bus_buffer.scala 201:148] + node _T_483 = bits(ld_byte_hitvec_hi_3, 1, 1) @[el2_lsu_bus_buffer.scala 201:93] + node _T_484 = and(ld_byte_hitvec_hi_3, buf_age_younger[1]) @[el2_lsu_bus_buffer.scala 201:122] + node _T_485 = orr(_T_484) @[el2_lsu_bus_buffer.scala 201:144] + node _T_486 = eq(_T_485, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 201:99] + node _T_487 = and(_T_483, _T_486) @[el2_lsu_bus_buffer.scala 201:97] + node _T_488 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[el2_lsu_bus_buffer.scala 201:170] + node _T_489 = eq(_T_488, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 201:150] + node _T_490 = and(_T_487, _T_489) @[el2_lsu_bus_buffer.scala 201:148] + node _T_491 = bits(ld_byte_hitvec_hi_3, 2, 2) @[el2_lsu_bus_buffer.scala 201:93] + node _T_492 = and(ld_byte_hitvec_hi_3, buf_age_younger[2]) @[el2_lsu_bus_buffer.scala 201:122] + node _T_493 = orr(_T_492) @[el2_lsu_bus_buffer.scala 201:144] + node _T_494 = eq(_T_493, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 201:99] + node _T_495 = and(_T_491, _T_494) @[el2_lsu_bus_buffer.scala 201:97] + node _T_496 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[el2_lsu_bus_buffer.scala 201:170] + node _T_497 = eq(_T_496, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 201:150] + node _T_498 = and(_T_495, _T_497) @[el2_lsu_bus_buffer.scala 201:148] + node _T_499 = bits(ld_byte_hitvec_hi_3, 3, 3) @[el2_lsu_bus_buffer.scala 201:93] + node _T_500 = and(ld_byte_hitvec_hi_3, buf_age_younger[3]) @[el2_lsu_bus_buffer.scala 201:122] + node _T_501 = orr(_T_500) @[el2_lsu_bus_buffer.scala 201:144] + node _T_502 = eq(_T_501, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 201:99] + node _T_503 = and(_T_499, _T_502) @[el2_lsu_bus_buffer.scala 201:97] + node _T_504 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[el2_lsu_bus_buffer.scala 201:170] + node _T_505 = eq(_T_504, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 201:150] + node _T_506 = and(_T_503, _T_505) @[el2_lsu_bus_buffer.scala 201:148] node _T_507 = cat(_T_506, _T_498) @[Cat.scala 29:58] node _T_508 = cat(_T_507, _T_490) @[Cat.scala 29:58] node _T_509 = cat(_T_508, _T_482) @[Cat.scala 29:58] - ld_byte_hitvecfn_hi[0] <= _T_404 @[el2_lsu_bus_buffer.scala 200:23] - ld_byte_hitvecfn_hi[1] <= _T_439 @[el2_lsu_bus_buffer.scala 200:23] - ld_byte_hitvecfn_hi[2] <= _T_474 @[el2_lsu_bus_buffer.scala 200:23] - ld_byte_hitvecfn_hi[3] <= _T_509 @[el2_lsu_bus_buffer.scala 200:23] + ld_byte_hitvecfn_hi[0] <= _T_404 @[el2_lsu_bus_buffer.scala 201:23] + ld_byte_hitvecfn_hi[1] <= _T_439 @[el2_lsu_bus_buffer.scala 201:23] + ld_byte_hitvecfn_hi[2] <= _T_474 @[el2_lsu_bus_buffer.scala 201:23] + ld_byte_hitvecfn_hi[3] <= _T_509 @[el2_lsu_bus_buffer.scala 201:23] wire ibuf_addr : UInt<32> ibuf_addr <= UInt<1>("h00") wire ibuf_write : UInt<1> ibuf_write <= UInt<1>("h00") wire ibuf_valid : UInt<1> ibuf_valid <= UInt<1>("h00") - node _T_510 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 205:43] - node _T_511 = bits(ibuf_addr, 31, 2) @[el2_lsu_bus_buffer.scala 205:64] - node _T_512 = eq(_T_510, _T_511) @[el2_lsu_bus_buffer.scala 205:51] - node _T_513 = and(_T_512, ibuf_write) @[el2_lsu_bus_buffer.scala 205:73] - node _T_514 = and(_T_513, ibuf_valid) @[el2_lsu_bus_buffer.scala 205:86] - node ld_addr_ibuf_hit_lo = and(_T_514, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 205:99] - node _T_515 = bits(io.end_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 206:43] - node _T_516 = bits(ibuf_addr, 31, 2) @[el2_lsu_bus_buffer.scala 206:64] - node _T_517 = eq(_T_515, _T_516) @[el2_lsu_bus_buffer.scala 206:51] - node _T_518 = and(_T_517, ibuf_write) @[el2_lsu_bus_buffer.scala 206:73] - node _T_519 = and(_T_518, ibuf_valid) @[el2_lsu_bus_buffer.scala 206:86] - node ld_addr_ibuf_hit_hi = and(_T_519, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 206:99] + node _T_510 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 206:43] + node _T_511 = bits(ibuf_addr, 31, 2) @[el2_lsu_bus_buffer.scala 206:64] + node _T_512 = eq(_T_510, _T_511) @[el2_lsu_bus_buffer.scala 206:51] + node _T_513 = and(_T_512, ibuf_write) @[el2_lsu_bus_buffer.scala 206:73] + node _T_514 = and(_T_513, ibuf_valid) @[el2_lsu_bus_buffer.scala 206:86] + node ld_addr_ibuf_hit_lo = and(_T_514, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 206:99] + node _T_515 = bits(io.end_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 207:43] + node _T_516 = bits(ibuf_addr, 31, 2) @[el2_lsu_bus_buffer.scala 207:64] + node _T_517 = eq(_T_515, _T_516) @[el2_lsu_bus_buffer.scala 207:51] + node _T_518 = and(_T_517, ibuf_write) @[el2_lsu_bus_buffer.scala 207:73] + node _T_519 = and(_T_518, ibuf_valid) @[el2_lsu_bus_buffer.scala 207:86] + node ld_addr_ibuf_hit_hi = and(_T_519, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 207:99] wire ibuf_byteen : UInt<4> ibuf_byteen <= UInt<1>("h00") node _T_520 = bits(ld_addr_ibuf_hit_lo, 0, 0) @[Bitwise.scala 72:15] node _T_521 = mux(_T_520, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_522 = and(_T_521, ibuf_byteen) @[el2_lsu_bus_buffer.scala 210:55] - node _T_523 = and(_T_522, ldst_byteen_lo_m) @[el2_lsu_bus_buffer.scala 210:69] - ld_byte_ibuf_hit_lo <= _T_523 @[el2_lsu_bus_buffer.scala 210:23] + node _T_522 = and(_T_521, ibuf_byteen) @[el2_lsu_bus_buffer.scala 211:55] + node _T_523 = and(_T_522, ldst_byteen_lo_m) @[el2_lsu_bus_buffer.scala 211:69] + ld_byte_ibuf_hit_lo <= _T_523 @[el2_lsu_bus_buffer.scala 211:23] node _T_524 = bits(ld_addr_ibuf_hit_hi, 0, 0) @[Bitwise.scala 72:15] node _T_525 = mux(_T_524, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_526 = and(_T_525, ibuf_byteen) @[el2_lsu_bus_buffer.scala 211:55] - node _T_527 = and(_T_526, ldst_byteen_hi_m) @[el2_lsu_bus_buffer.scala 211:69] - ld_byte_ibuf_hit_hi <= _T_527 @[el2_lsu_bus_buffer.scala 211:23] - wire buf_data : UInt<32>[4] @[el2_lsu_bus_buffer.scala 213:22] - buf_data[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 214:12] - buf_data[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 214:12] - buf_data[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 214:12] - buf_data[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 214:12] + node _T_526 = and(_T_525, ibuf_byteen) @[el2_lsu_bus_buffer.scala 212:55] + node _T_527 = and(_T_526, ldst_byteen_hi_m) @[el2_lsu_bus_buffer.scala 212:69] + ld_byte_ibuf_hit_hi <= _T_527 @[el2_lsu_bus_buffer.scala 212:23] + wire buf_data : UInt<32>[4] @[el2_lsu_bus_buffer.scala 214:22] + buf_data[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 215:12] + buf_data[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 215:12] + buf_data[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 215:12] + buf_data[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 215:12] wire fwd_data : UInt<32> fwd_data <= UInt<1>("h00") - node _T_528 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[el2_lsu_bus_buffer.scala 216:81] + node _T_528 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[el2_lsu_bus_buffer.scala 217:81] node _T_529 = bits(_T_528, 0, 0) @[Bitwise.scala 72:15] node _T_530 = mux(_T_529, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_531 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[el2_lsu_bus_buffer.scala 216:81] + node _T_531 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[el2_lsu_bus_buffer.scala 217:81] node _T_532 = bits(_T_531, 0, 0) @[Bitwise.scala 72:15] node _T_533 = mux(_T_532, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_534 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[el2_lsu_bus_buffer.scala 216:81] + node _T_534 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[el2_lsu_bus_buffer.scala 217:81] node _T_535 = bits(_T_534, 0, 0) @[Bitwise.scala 72:15] node _T_536 = mux(_T_535, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_537 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[el2_lsu_bus_buffer.scala 216:81] + node _T_537 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[el2_lsu_bus_buffer.scala 217:81] node _T_538 = bits(_T_537, 0, 0) @[Bitwise.scala 72:15] node _T_539 = mux(_T_538, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] node _T_540 = cat(_T_539, _T_536) @[Cat.scala 29:58] node _T_541 = cat(_T_540, _T_533) @[Cat.scala 29:58] node ld_fwddata_buf_lo_initial = cat(_T_541, _T_530) @[Cat.scala 29:58] - node _T_542 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[el2_lsu_bus_buffer.scala 217:81] + node _T_542 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[el2_lsu_bus_buffer.scala 218:81] node _T_543 = bits(_T_542, 0, 0) @[Bitwise.scala 72:15] node _T_544 = mux(_T_543, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_545 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[el2_lsu_bus_buffer.scala 217:81] + node _T_545 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[el2_lsu_bus_buffer.scala 218:81] node _T_546 = bits(_T_545, 0, 0) @[Bitwise.scala 72:15] node _T_547 = mux(_T_546, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_548 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[el2_lsu_bus_buffer.scala 217:81] + node _T_548 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[el2_lsu_bus_buffer.scala 218:81] node _T_549 = bits(_T_548, 0, 0) @[Bitwise.scala 72:15] node _T_550 = mux(_T_549, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_551 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[el2_lsu_bus_buffer.scala 217:81] + node _T_551 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[el2_lsu_bus_buffer.scala 218:81] node _T_552 = bits(_T_551, 0, 0) @[Bitwise.scala 72:15] node _T_553 = mux(_T_552, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] node _T_554 = cat(_T_553, _T_550) @[Cat.scala 29:58] node _T_555 = cat(_T_554, _T_547) @[Cat.scala 29:58] node ld_fwddata_buf_hi_initial = cat(_T_555, _T_544) @[Cat.scala 29:58] - node _T_556 = bits(ld_byte_hitvecfn_lo[3], 0, 0) @[el2_lsu_bus_buffer.scala 218:86] + node _T_556 = bits(ld_byte_hitvecfn_lo[3], 0, 0) @[el2_lsu_bus_buffer.scala 219:86] node _T_557 = bits(_T_556, 0, 0) @[Bitwise.scala 72:15] node _T_558 = mux(_T_557, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_559 = bits(buf_data[0], 31, 24) @[el2_lsu_bus_buffer.scala 218:104] - node _T_560 = and(_T_558, _T_559) @[el2_lsu_bus_buffer.scala 218:91] - node _T_561 = bits(ld_byte_hitvecfn_lo[3], 1, 1) @[el2_lsu_bus_buffer.scala 218:86] + node _T_559 = bits(buf_data[0], 31, 24) @[el2_lsu_bus_buffer.scala 219:104] + node _T_560 = and(_T_558, _T_559) @[el2_lsu_bus_buffer.scala 219:91] + node _T_561 = bits(ld_byte_hitvecfn_lo[3], 1, 1) @[el2_lsu_bus_buffer.scala 219:86] node _T_562 = bits(_T_561, 0, 0) @[Bitwise.scala 72:15] node _T_563 = mux(_T_562, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_564 = bits(buf_data[1], 31, 24) @[el2_lsu_bus_buffer.scala 218:104] - node _T_565 = and(_T_563, _T_564) @[el2_lsu_bus_buffer.scala 218:91] - node _T_566 = bits(ld_byte_hitvecfn_lo[3], 2, 2) @[el2_lsu_bus_buffer.scala 218:86] + node _T_564 = bits(buf_data[1], 31, 24) @[el2_lsu_bus_buffer.scala 219:104] + node _T_565 = and(_T_563, _T_564) @[el2_lsu_bus_buffer.scala 219:91] + node _T_566 = bits(ld_byte_hitvecfn_lo[3], 2, 2) @[el2_lsu_bus_buffer.scala 219:86] node _T_567 = bits(_T_566, 0, 0) @[Bitwise.scala 72:15] node _T_568 = mux(_T_567, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_569 = bits(buf_data[2], 31, 24) @[el2_lsu_bus_buffer.scala 218:104] - node _T_570 = and(_T_568, _T_569) @[el2_lsu_bus_buffer.scala 218:91] - node _T_571 = bits(ld_byte_hitvecfn_lo[3], 3, 3) @[el2_lsu_bus_buffer.scala 218:86] + node _T_569 = bits(buf_data[2], 31, 24) @[el2_lsu_bus_buffer.scala 219:104] + node _T_570 = and(_T_568, _T_569) @[el2_lsu_bus_buffer.scala 219:91] + node _T_571 = bits(ld_byte_hitvecfn_lo[3], 3, 3) @[el2_lsu_bus_buffer.scala 219:86] node _T_572 = bits(_T_571, 0, 0) @[Bitwise.scala 72:15] node _T_573 = mux(_T_572, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_574 = bits(buf_data[3], 31, 24) @[el2_lsu_bus_buffer.scala 218:104] - node _T_575 = and(_T_573, _T_574) @[el2_lsu_bus_buffer.scala 218:91] - node _T_576 = or(_T_560, _T_565) @[el2_lsu_bus_buffer.scala 218:123] - node _T_577 = or(_T_576, _T_570) @[el2_lsu_bus_buffer.scala 218:123] - node _T_578 = or(_T_577, _T_575) @[el2_lsu_bus_buffer.scala 218:123] - node _T_579 = bits(ld_byte_hitvecfn_lo[2], 0, 0) @[el2_lsu_bus_buffer.scala 219:60] + node _T_574 = bits(buf_data[3], 31, 24) @[el2_lsu_bus_buffer.scala 219:104] + node _T_575 = and(_T_573, _T_574) @[el2_lsu_bus_buffer.scala 219:91] + node _T_576 = or(_T_560, _T_565) @[el2_lsu_bus_buffer.scala 219:123] + node _T_577 = or(_T_576, _T_570) @[el2_lsu_bus_buffer.scala 219:123] + node _T_578 = or(_T_577, _T_575) @[el2_lsu_bus_buffer.scala 219:123] + node _T_579 = bits(ld_byte_hitvecfn_lo[2], 0, 0) @[el2_lsu_bus_buffer.scala 220:60] node _T_580 = bits(_T_579, 0, 0) @[Bitwise.scala 72:15] node _T_581 = mux(_T_580, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_582 = bits(buf_data[0], 23, 16) @[el2_lsu_bus_buffer.scala 219:78] - node _T_583 = and(_T_581, _T_582) @[el2_lsu_bus_buffer.scala 219:65] - node _T_584 = bits(ld_byte_hitvecfn_lo[2], 1, 1) @[el2_lsu_bus_buffer.scala 219:60] + node _T_582 = bits(buf_data[0], 23, 16) @[el2_lsu_bus_buffer.scala 220:78] + node _T_583 = and(_T_581, _T_582) @[el2_lsu_bus_buffer.scala 220:65] + node _T_584 = bits(ld_byte_hitvecfn_lo[2], 1, 1) @[el2_lsu_bus_buffer.scala 220:60] node _T_585 = bits(_T_584, 0, 0) @[Bitwise.scala 72:15] node _T_586 = mux(_T_585, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_587 = bits(buf_data[1], 23, 16) @[el2_lsu_bus_buffer.scala 219:78] - node _T_588 = and(_T_586, _T_587) @[el2_lsu_bus_buffer.scala 219:65] - node _T_589 = bits(ld_byte_hitvecfn_lo[2], 2, 2) @[el2_lsu_bus_buffer.scala 219:60] + node _T_587 = bits(buf_data[1], 23, 16) @[el2_lsu_bus_buffer.scala 220:78] + node _T_588 = and(_T_586, _T_587) @[el2_lsu_bus_buffer.scala 220:65] + node _T_589 = bits(ld_byte_hitvecfn_lo[2], 2, 2) @[el2_lsu_bus_buffer.scala 220:60] node _T_590 = bits(_T_589, 0, 0) @[Bitwise.scala 72:15] node _T_591 = mux(_T_590, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_592 = bits(buf_data[2], 23, 16) @[el2_lsu_bus_buffer.scala 219:78] - node _T_593 = and(_T_591, _T_592) @[el2_lsu_bus_buffer.scala 219:65] - node _T_594 = bits(ld_byte_hitvecfn_lo[2], 3, 3) @[el2_lsu_bus_buffer.scala 219:60] + node _T_592 = bits(buf_data[2], 23, 16) @[el2_lsu_bus_buffer.scala 220:78] + node _T_593 = and(_T_591, _T_592) @[el2_lsu_bus_buffer.scala 220:65] + node _T_594 = bits(ld_byte_hitvecfn_lo[2], 3, 3) @[el2_lsu_bus_buffer.scala 220:60] node _T_595 = bits(_T_594, 0, 0) @[Bitwise.scala 72:15] node _T_596 = mux(_T_595, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_597 = bits(buf_data[3], 23, 16) @[el2_lsu_bus_buffer.scala 219:78] - node _T_598 = and(_T_596, _T_597) @[el2_lsu_bus_buffer.scala 219:65] - node _T_599 = or(_T_583, _T_588) @[el2_lsu_bus_buffer.scala 219:97] - node _T_600 = or(_T_599, _T_593) @[el2_lsu_bus_buffer.scala 219:97] - node _T_601 = or(_T_600, _T_598) @[el2_lsu_bus_buffer.scala 219:97] - node _T_602 = bits(ld_byte_hitvecfn_lo[1], 0, 0) @[el2_lsu_bus_buffer.scala 220:60] + node _T_597 = bits(buf_data[3], 23, 16) @[el2_lsu_bus_buffer.scala 220:78] + node _T_598 = and(_T_596, _T_597) @[el2_lsu_bus_buffer.scala 220:65] + node _T_599 = or(_T_583, _T_588) @[el2_lsu_bus_buffer.scala 220:97] + node _T_600 = or(_T_599, _T_593) @[el2_lsu_bus_buffer.scala 220:97] + node _T_601 = or(_T_600, _T_598) @[el2_lsu_bus_buffer.scala 220:97] + node _T_602 = bits(ld_byte_hitvecfn_lo[1], 0, 0) @[el2_lsu_bus_buffer.scala 221:60] node _T_603 = bits(_T_602, 0, 0) @[Bitwise.scala 72:15] node _T_604 = mux(_T_603, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_605 = bits(buf_data[0], 15, 8) @[el2_lsu_bus_buffer.scala 220:78] - node _T_606 = and(_T_604, _T_605) @[el2_lsu_bus_buffer.scala 220:65] - node _T_607 = bits(ld_byte_hitvecfn_lo[1], 1, 1) @[el2_lsu_bus_buffer.scala 220:60] + node _T_605 = bits(buf_data[0], 15, 8) @[el2_lsu_bus_buffer.scala 221:78] + node _T_606 = and(_T_604, _T_605) @[el2_lsu_bus_buffer.scala 221:65] + node _T_607 = bits(ld_byte_hitvecfn_lo[1], 1, 1) @[el2_lsu_bus_buffer.scala 221:60] node _T_608 = bits(_T_607, 0, 0) @[Bitwise.scala 72:15] node _T_609 = mux(_T_608, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_610 = bits(buf_data[1], 15, 8) @[el2_lsu_bus_buffer.scala 220:78] - node _T_611 = and(_T_609, _T_610) @[el2_lsu_bus_buffer.scala 220:65] - node _T_612 = bits(ld_byte_hitvecfn_lo[1], 2, 2) @[el2_lsu_bus_buffer.scala 220:60] + node _T_610 = bits(buf_data[1], 15, 8) @[el2_lsu_bus_buffer.scala 221:78] + node _T_611 = and(_T_609, _T_610) @[el2_lsu_bus_buffer.scala 221:65] + node _T_612 = bits(ld_byte_hitvecfn_lo[1], 2, 2) @[el2_lsu_bus_buffer.scala 221:60] node _T_613 = bits(_T_612, 0, 0) @[Bitwise.scala 72:15] node _T_614 = mux(_T_613, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_615 = bits(buf_data[2], 15, 8) @[el2_lsu_bus_buffer.scala 220:78] - node _T_616 = and(_T_614, _T_615) @[el2_lsu_bus_buffer.scala 220:65] - node _T_617 = bits(ld_byte_hitvecfn_lo[1], 3, 3) @[el2_lsu_bus_buffer.scala 220:60] + node _T_615 = bits(buf_data[2], 15, 8) @[el2_lsu_bus_buffer.scala 221:78] + node _T_616 = and(_T_614, _T_615) @[el2_lsu_bus_buffer.scala 221:65] + node _T_617 = bits(ld_byte_hitvecfn_lo[1], 3, 3) @[el2_lsu_bus_buffer.scala 221:60] node _T_618 = bits(_T_617, 0, 0) @[Bitwise.scala 72:15] node _T_619 = mux(_T_618, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_620 = bits(buf_data[3], 15, 8) @[el2_lsu_bus_buffer.scala 220:78] - node _T_621 = and(_T_619, _T_620) @[el2_lsu_bus_buffer.scala 220:65] - node _T_622 = or(_T_606, _T_611) @[el2_lsu_bus_buffer.scala 220:97] - node _T_623 = or(_T_622, _T_616) @[el2_lsu_bus_buffer.scala 220:97] - node _T_624 = or(_T_623, _T_621) @[el2_lsu_bus_buffer.scala 220:97] - node _T_625 = bits(ld_byte_hitvecfn_lo[0], 0, 0) @[el2_lsu_bus_buffer.scala 221:60] + node _T_620 = bits(buf_data[3], 15, 8) @[el2_lsu_bus_buffer.scala 221:78] + node _T_621 = and(_T_619, _T_620) @[el2_lsu_bus_buffer.scala 221:65] + node _T_622 = or(_T_606, _T_611) @[el2_lsu_bus_buffer.scala 221:97] + node _T_623 = or(_T_622, _T_616) @[el2_lsu_bus_buffer.scala 221:97] + node _T_624 = or(_T_623, _T_621) @[el2_lsu_bus_buffer.scala 221:97] + node _T_625 = bits(ld_byte_hitvecfn_lo[0], 0, 0) @[el2_lsu_bus_buffer.scala 222:60] node _T_626 = bits(_T_625, 0, 0) @[Bitwise.scala 72:15] node _T_627 = mux(_T_626, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_628 = bits(buf_data[0], 7, 0) @[el2_lsu_bus_buffer.scala 221:78] - node _T_629 = and(_T_627, _T_628) @[el2_lsu_bus_buffer.scala 221:65] - node _T_630 = bits(ld_byte_hitvecfn_lo[0], 1, 1) @[el2_lsu_bus_buffer.scala 221:60] + node _T_628 = bits(buf_data[0], 7, 0) @[el2_lsu_bus_buffer.scala 222:78] + node _T_629 = and(_T_627, _T_628) @[el2_lsu_bus_buffer.scala 222:65] + node _T_630 = bits(ld_byte_hitvecfn_lo[0], 1, 1) @[el2_lsu_bus_buffer.scala 222:60] node _T_631 = bits(_T_630, 0, 0) @[Bitwise.scala 72:15] node _T_632 = mux(_T_631, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_633 = bits(buf_data[1], 7, 0) @[el2_lsu_bus_buffer.scala 221:78] - node _T_634 = and(_T_632, _T_633) @[el2_lsu_bus_buffer.scala 221:65] - node _T_635 = bits(ld_byte_hitvecfn_lo[0], 2, 2) @[el2_lsu_bus_buffer.scala 221:60] + node _T_633 = bits(buf_data[1], 7, 0) @[el2_lsu_bus_buffer.scala 222:78] + node _T_634 = and(_T_632, _T_633) @[el2_lsu_bus_buffer.scala 222:65] + node _T_635 = bits(ld_byte_hitvecfn_lo[0], 2, 2) @[el2_lsu_bus_buffer.scala 222:60] node _T_636 = bits(_T_635, 0, 0) @[Bitwise.scala 72:15] node _T_637 = mux(_T_636, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_638 = bits(buf_data[2], 7, 0) @[el2_lsu_bus_buffer.scala 221:78] - node _T_639 = and(_T_637, _T_638) @[el2_lsu_bus_buffer.scala 221:65] - node _T_640 = bits(ld_byte_hitvecfn_lo[0], 3, 3) @[el2_lsu_bus_buffer.scala 221:60] + node _T_638 = bits(buf_data[2], 7, 0) @[el2_lsu_bus_buffer.scala 222:78] + node _T_639 = and(_T_637, _T_638) @[el2_lsu_bus_buffer.scala 222:65] + node _T_640 = bits(ld_byte_hitvecfn_lo[0], 3, 3) @[el2_lsu_bus_buffer.scala 222:60] node _T_641 = bits(_T_640, 0, 0) @[Bitwise.scala 72:15] node _T_642 = mux(_T_641, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_643 = bits(buf_data[3], 7, 0) @[el2_lsu_bus_buffer.scala 221:78] - node _T_644 = and(_T_642, _T_643) @[el2_lsu_bus_buffer.scala 221:65] - node _T_645 = or(_T_629, _T_634) @[el2_lsu_bus_buffer.scala 221:97] - node _T_646 = or(_T_645, _T_639) @[el2_lsu_bus_buffer.scala 221:97] - node _T_647 = or(_T_646, _T_644) @[el2_lsu_bus_buffer.scala 221:97] + node _T_643 = bits(buf_data[3], 7, 0) @[el2_lsu_bus_buffer.scala 222:78] + node _T_644 = and(_T_642, _T_643) @[el2_lsu_bus_buffer.scala 222:65] + node _T_645 = or(_T_629, _T_634) @[el2_lsu_bus_buffer.scala 222:97] + node _T_646 = or(_T_645, _T_639) @[el2_lsu_bus_buffer.scala 222:97] + node _T_647 = or(_T_646, _T_644) @[el2_lsu_bus_buffer.scala 222:97] node _T_648 = cat(_T_624, _T_647) @[Cat.scala 29:58] node _T_649 = cat(_T_578, _T_601) @[Cat.scala 29:58] node _T_650 = cat(_T_649, _T_648) @[Cat.scala 29:58] - node _T_651 = and(ld_fwddata_buf_lo_initial, ibuf_data) @[el2_lsu_bus_buffer.scala 222:32] - node _T_652 = or(_T_650, _T_651) @[el2_lsu_bus_buffer.scala 221:103] - io.ld_fwddata_buf_lo <= _T_652 @[el2_lsu_bus_buffer.scala 218:24] - node _T_653 = bits(ld_byte_hitvecfn_hi[3], 0, 0) @[el2_lsu_bus_buffer.scala 224:86] + node _T_651 = and(ld_fwddata_buf_lo_initial, ibuf_data) @[el2_lsu_bus_buffer.scala 223:32] + node _T_652 = or(_T_650, _T_651) @[el2_lsu_bus_buffer.scala 222:103] + io.ld_fwddata_buf_lo <= _T_652 @[el2_lsu_bus_buffer.scala 219:24] + node _T_653 = bits(ld_byte_hitvecfn_hi[3], 0, 0) @[el2_lsu_bus_buffer.scala 225:86] node _T_654 = bits(_T_653, 0, 0) @[Bitwise.scala 72:15] node _T_655 = mux(_T_654, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_656 = bits(buf_data[0], 31, 24) @[el2_lsu_bus_buffer.scala 224:104] - node _T_657 = and(_T_655, _T_656) @[el2_lsu_bus_buffer.scala 224:91] - node _T_658 = bits(ld_byte_hitvecfn_hi[3], 1, 1) @[el2_lsu_bus_buffer.scala 224:86] + node _T_656 = bits(buf_data[0], 31, 24) @[el2_lsu_bus_buffer.scala 225:104] + node _T_657 = and(_T_655, _T_656) @[el2_lsu_bus_buffer.scala 225:91] + node _T_658 = bits(ld_byte_hitvecfn_hi[3], 1, 1) @[el2_lsu_bus_buffer.scala 225:86] node _T_659 = bits(_T_658, 0, 0) @[Bitwise.scala 72:15] node _T_660 = mux(_T_659, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_661 = bits(buf_data[1], 31, 24) @[el2_lsu_bus_buffer.scala 224:104] - node _T_662 = and(_T_660, _T_661) @[el2_lsu_bus_buffer.scala 224:91] - node _T_663 = bits(ld_byte_hitvecfn_hi[3], 2, 2) @[el2_lsu_bus_buffer.scala 224:86] + node _T_661 = bits(buf_data[1], 31, 24) @[el2_lsu_bus_buffer.scala 225:104] + node _T_662 = and(_T_660, _T_661) @[el2_lsu_bus_buffer.scala 225:91] + node _T_663 = bits(ld_byte_hitvecfn_hi[3], 2, 2) @[el2_lsu_bus_buffer.scala 225:86] node _T_664 = bits(_T_663, 0, 0) @[Bitwise.scala 72:15] node _T_665 = mux(_T_664, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_666 = bits(buf_data[2], 31, 24) @[el2_lsu_bus_buffer.scala 224:104] - node _T_667 = and(_T_665, _T_666) @[el2_lsu_bus_buffer.scala 224:91] - node _T_668 = bits(ld_byte_hitvecfn_hi[3], 3, 3) @[el2_lsu_bus_buffer.scala 224:86] + node _T_666 = bits(buf_data[2], 31, 24) @[el2_lsu_bus_buffer.scala 225:104] + node _T_667 = and(_T_665, _T_666) @[el2_lsu_bus_buffer.scala 225:91] + node _T_668 = bits(ld_byte_hitvecfn_hi[3], 3, 3) @[el2_lsu_bus_buffer.scala 225:86] node _T_669 = bits(_T_668, 0, 0) @[Bitwise.scala 72:15] node _T_670 = mux(_T_669, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_671 = bits(buf_data[3], 31, 24) @[el2_lsu_bus_buffer.scala 224:104] - node _T_672 = and(_T_670, _T_671) @[el2_lsu_bus_buffer.scala 224:91] - node _T_673 = or(_T_657, _T_662) @[el2_lsu_bus_buffer.scala 224:123] - node _T_674 = or(_T_673, _T_667) @[el2_lsu_bus_buffer.scala 224:123] - node _T_675 = or(_T_674, _T_672) @[el2_lsu_bus_buffer.scala 224:123] - node _T_676 = bits(ld_byte_hitvecfn_hi[2], 0, 0) @[el2_lsu_bus_buffer.scala 225:60] + node _T_671 = bits(buf_data[3], 31, 24) @[el2_lsu_bus_buffer.scala 225:104] + node _T_672 = and(_T_670, _T_671) @[el2_lsu_bus_buffer.scala 225:91] + node _T_673 = or(_T_657, _T_662) @[el2_lsu_bus_buffer.scala 225:123] + node _T_674 = or(_T_673, _T_667) @[el2_lsu_bus_buffer.scala 225:123] + node _T_675 = or(_T_674, _T_672) @[el2_lsu_bus_buffer.scala 225:123] + node _T_676 = bits(ld_byte_hitvecfn_hi[2], 0, 0) @[el2_lsu_bus_buffer.scala 226:60] node _T_677 = bits(_T_676, 0, 0) @[Bitwise.scala 72:15] node _T_678 = mux(_T_677, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_679 = bits(buf_data[0], 23, 16) @[el2_lsu_bus_buffer.scala 225:78] - node _T_680 = and(_T_678, _T_679) @[el2_lsu_bus_buffer.scala 225:65] - node _T_681 = bits(ld_byte_hitvecfn_hi[2], 1, 1) @[el2_lsu_bus_buffer.scala 225:60] + node _T_679 = bits(buf_data[0], 23, 16) @[el2_lsu_bus_buffer.scala 226:78] + node _T_680 = and(_T_678, _T_679) @[el2_lsu_bus_buffer.scala 226:65] + node _T_681 = bits(ld_byte_hitvecfn_hi[2], 1, 1) @[el2_lsu_bus_buffer.scala 226:60] node _T_682 = bits(_T_681, 0, 0) @[Bitwise.scala 72:15] node _T_683 = mux(_T_682, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_684 = bits(buf_data[1], 23, 16) @[el2_lsu_bus_buffer.scala 225:78] - node _T_685 = and(_T_683, _T_684) @[el2_lsu_bus_buffer.scala 225:65] - node _T_686 = bits(ld_byte_hitvecfn_hi[2], 2, 2) @[el2_lsu_bus_buffer.scala 225:60] + node _T_684 = bits(buf_data[1], 23, 16) @[el2_lsu_bus_buffer.scala 226:78] + node _T_685 = and(_T_683, _T_684) @[el2_lsu_bus_buffer.scala 226:65] + node _T_686 = bits(ld_byte_hitvecfn_hi[2], 2, 2) @[el2_lsu_bus_buffer.scala 226:60] node _T_687 = bits(_T_686, 0, 0) @[Bitwise.scala 72:15] node _T_688 = mux(_T_687, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_689 = bits(buf_data[2], 23, 16) @[el2_lsu_bus_buffer.scala 225:78] - node _T_690 = and(_T_688, _T_689) @[el2_lsu_bus_buffer.scala 225:65] - node _T_691 = bits(ld_byte_hitvecfn_hi[2], 3, 3) @[el2_lsu_bus_buffer.scala 225:60] + node _T_689 = bits(buf_data[2], 23, 16) @[el2_lsu_bus_buffer.scala 226:78] + node _T_690 = and(_T_688, _T_689) @[el2_lsu_bus_buffer.scala 226:65] + node _T_691 = bits(ld_byte_hitvecfn_hi[2], 3, 3) @[el2_lsu_bus_buffer.scala 226:60] node _T_692 = bits(_T_691, 0, 0) @[Bitwise.scala 72:15] node _T_693 = mux(_T_692, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_694 = bits(buf_data[3], 23, 16) @[el2_lsu_bus_buffer.scala 225:78] - node _T_695 = and(_T_693, _T_694) @[el2_lsu_bus_buffer.scala 225:65] - node _T_696 = or(_T_680, _T_685) @[el2_lsu_bus_buffer.scala 225:97] - node _T_697 = or(_T_696, _T_690) @[el2_lsu_bus_buffer.scala 225:97] - node _T_698 = or(_T_697, _T_695) @[el2_lsu_bus_buffer.scala 225:97] - node _T_699 = bits(ld_byte_hitvecfn_hi[1], 0, 0) @[el2_lsu_bus_buffer.scala 226:60] + node _T_694 = bits(buf_data[3], 23, 16) @[el2_lsu_bus_buffer.scala 226:78] + node _T_695 = and(_T_693, _T_694) @[el2_lsu_bus_buffer.scala 226:65] + node _T_696 = or(_T_680, _T_685) @[el2_lsu_bus_buffer.scala 226:97] + node _T_697 = or(_T_696, _T_690) @[el2_lsu_bus_buffer.scala 226:97] + node _T_698 = or(_T_697, _T_695) @[el2_lsu_bus_buffer.scala 226:97] + node _T_699 = bits(ld_byte_hitvecfn_hi[1], 0, 0) @[el2_lsu_bus_buffer.scala 227:60] node _T_700 = bits(_T_699, 0, 0) @[Bitwise.scala 72:15] node _T_701 = mux(_T_700, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_702 = bits(buf_data[0], 15, 8) @[el2_lsu_bus_buffer.scala 226:78] - node _T_703 = and(_T_701, _T_702) @[el2_lsu_bus_buffer.scala 226:65] - node _T_704 = bits(ld_byte_hitvecfn_hi[1], 1, 1) @[el2_lsu_bus_buffer.scala 226:60] + node _T_702 = bits(buf_data[0], 15, 8) @[el2_lsu_bus_buffer.scala 227:78] + node _T_703 = and(_T_701, _T_702) @[el2_lsu_bus_buffer.scala 227:65] + node _T_704 = bits(ld_byte_hitvecfn_hi[1], 1, 1) @[el2_lsu_bus_buffer.scala 227:60] node _T_705 = bits(_T_704, 0, 0) @[Bitwise.scala 72:15] node _T_706 = mux(_T_705, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_707 = bits(buf_data[1], 15, 8) @[el2_lsu_bus_buffer.scala 226:78] - node _T_708 = and(_T_706, _T_707) @[el2_lsu_bus_buffer.scala 226:65] - node _T_709 = bits(ld_byte_hitvecfn_hi[1], 2, 2) @[el2_lsu_bus_buffer.scala 226:60] + node _T_707 = bits(buf_data[1], 15, 8) @[el2_lsu_bus_buffer.scala 227:78] + node _T_708 = and(_T_706, _T_707) @[el2_lsu_bus_buffer.scala 227:65] + node _T_709 = bits(ld_byte_hitvecfn_hi[1], 2, 2) @[el2_lsu_bus_buffer.scala 227:60] node _T_710 = bits(_T_709, 0, 0) @[Bitwise.scala 72:15] node _T_711 = mux(_T_710, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_712 = bits(buf_data[2], 15, 8) @[el2_lsu_bus_buffer.scala 226:78] - node _T_713 = and(_T_711, _T_712) @[el2_lsu_bus_buffer.scala 226:65] - node _T_714 = bits(ld_byte_hitvecfn_hi[1], 3, 3) @[el2_lsu_bus_buffer.scala 226:60] + node _T_712 = bits(buf_data[2], 15, 8) @[el2_lsu_bus_buffer.scala 227:78] + node _T_713 = and(_T_711, _T_712) @[el2_lsu_bus_buffer.scala 227:65] + node _T_714 = bits(ld_byte_hitvecfn_hi[1], 3, 3) @[el2_lsu_bus_buffer.scala 227:60] node _T_715 = bits(_T_714, 0, 0) @[Bitwise.scala 72:15] node _T_716 = mux(_T_715, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_717 = bits(buf_data[3], 15, 8) @[el2_lsu_bus_buffer.scala 226:78] - node _T_718 = and(_T_716, _T_717) @[el2_lsu_bus_buffer.scala 226:65] - node _T_719 = or(_T_703, _T_708) @[el2_lsu_bus_buffer.scala 226:97] - node _T_720 = or(_T_719, _T_713) @[el2_lsu_bus_buffer.scala 226:97] - node _T_721 = or(_T_720, _T_718) @[el2_lsu_bus_buffer.scala 226:97] - node _T_722 = bits(ld_byte_hitvecfn_hi[0], 0, 0) @[el2_lsu_bus_buffer.scala 227:60] + node _T_717 = bits(buf_data[3], 15, 8) @[el2_lsu_bus_buffer.scala 227:78] + node _T_718 = and(_T_716, _T_717) @[el2_lsu_bus_buffer.scala 227:65] + node _T_719 = or(_T_703, _T_708) @[el2_lsu_bus_buffer.scala 227:97] + node _T_720 = or(_T_719, _T_713) @[el2_lsu_bus_buffer.scala 227:97] + node _T_721 = or(_T_720, _T_718) @[el2_lsu_bus_buffer.scala 227:97] + node _T_722 = bits(ld_byte_hitvecfn_hi[0], 0, 0) @[el2_lsu_bus_buffer.scala 228:60] node _T_723 = bits(_T_722, 0, 0) @[Bitwise.scala 72:15] node _T_724 = mux(_T_723, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_725 = bits(buf_data[0], 7, 0) @[el2_lsu_bus_buffer.scala 227:78] - node _T_726 = and(_T_724, _T_725) @[el2_lsu_bus_buffer.scala 227:65] - node _T_727 = bits(ld_byte_hitvecfn_hi[0], 1, 1) @[el2_lsu_bus_buffer.scala 227:60] + node _T_725 = bits(buf_data[0], 7, 0) @[el2_lsu_bus_buffer.scala 228:78] + node _T_726 = and(_T_724, _T_725) @[el2_lsu_bus_buffer.scala 228:65] + node _T_727 = bits(ld_byte_hitvecfn_hi[0], 1, 1) @[el2_lsu_bus_buffer.scala 228:60] node _T_728 = bits(_T_727, 0, 0) @[Bitwise.scala 72:15] node _T_729 = mux(_T_728, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_730 = bits(buf_data[1], 7, 0) @[el2_lsu_bus_buffer.scala 227:78] - node _T_731 = and(_T_729, _T_730) @[el2_lsu_bus_buffer.scala 227:65] - node _T_732 = bits(ld_byte_hitvecfn_hi[0], 2, 2) @[el2_lsu_bus_buffer.scala 227:60] + node _T_730 = bits(buf_data[1], 7, 0) @[el2_lsu_bus_buffer.scala 228:78] + node _T_731 = and(_T_729, _T_730) @[el2_lsu_bus_buffer.scala 228:65] + node _T_732 = bits(ld_byte_hitvecfn_hi[0], 2, 2) @[el2_lsu_bus_buffer.scala 228:60] node _T_733 = bits(_T_732, 0, 0) @[Bitwise.scala 72:15] node _T_734 = mux(_T_733, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_735 = bits(buf_data[2], 7, 0) @[el2_lsu_bus_buffer.scala 227:78] - node _T_736 = and(_T_734, _T_735) @[el2_lsu_bus_buffer.scala 227:65] - node _T_737 = bits(ld_byte_hitvecfn_hi[0], 3, 3) @[el2_lsu_bus_buffer.scala 227:60] + node _T_735 = bits(buf_data[2], 7, 0) @[el2_lsu_bus_buffer.scala 228:78] + node _T_736 = and(_T_734, _T_735) @[el2_lsu_bus_buffer.scala 228:65] + node _T_737 = bits(ld_byte_hitvecfn_hi[0], 3, 3) @[el2_lsu_bus_buffer.scala 228:60] node _T_738 = bits(_T_737, 0, 0) @[Bitwise.scala 72:15] node _T_739 = mux(_T_738, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_740 = bits(buf_data[3], 7, 0) @[el2_lsu_bus_buffer.scala 227:78] - node _T_741 = and(_T_739, _T_740) @[el2_lsu_bus_buffer.scala 227:65] - node _T_742 = or(_T_726, _T_731) @[el2_lsu_bus_buffer.scala 227:97] - node _T_743 = or(_T_742, _T_736) @[el2_lsu_bus_buffer.scala 227:97] - node _T_744 = or(_T_743, _T_741) @[el2_lsu_bus_buffer.scala 227:97] + node _T_740 = bits(buf_data[3], 7, 0) @[el2_lsu_bus_buffer.scala 228:78] + node _T_741 = and(_T_739, _T_740) @[el2_lsu_bus_buffer.scala 228:65] + node _T_742 = or(_T_726, _T_731) @[el2_lsu_bus_buffer.scala 228:97] + node _T_743 = or(_T_742, _T_736) @[el2_lsu_bus_buffer.scala 228:97] + node _T_744 = or(_T_743, _T_741) @[el2_lsu_bus_buffer.scala 228:97] node _T_745 = cat(_T_721, _T_744) @[Cat.scala 29:58] node _T_746 = cat(_T_675, _T_698) @[Cat.scala 29:58] node _T_747 = cat(_T_746, _T_745) @[Cat.scala 29:58] - node _T_748 = and(ld_fwddata_buf_hi_initial, ibuf_data) @[el2_lsu_bus_buffer.scala 228:32] - node _T_749 = or(_T_747, _T_748) @[el2_lsu_bus_buffer.scala 227:103] - io.ld_fwddata_buf_hi <= _T_749 @[el2_lsu_bus_buffer.scala 224:24] - node bus_coalescing_disable = or(io.dec_tlu_wb_coalescing_disable, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 230:65] - node _T_750 = mux(io.lsu_pkt_r.by, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_751 = mux(io.lsu_pkt_r.half, UInt<4>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_752 = mux(io.lsu_pkt_r.word, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_748 = and(ld_fwddata_buf_hi_initial, ibuf_data) @[el2_lsu_bus_buffer.scala 229:32] + node _T_749 = or(_T_747, _T_748) @[el2_lsu_bus_buffer.scala 228:103] + io.ld_fwddata_buf_hi <= _T_749 @[el2_lsu_bus_buffer.scala 225:24] + node bus_coalescing_disable = or(io.dec_tlu_wb_coalescing_disable, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 231:65] + node _T_750 = mux(io.lsu_pkt_r.bits.by, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_751 = mux(io.lsu_pkt_r.bits.half, UInt<4>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_752 = mux(io.lsu_pkt_r.bits.word, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_753 = or(_T_750, _T_751) @[Mux.scala 27:72] node _T_754 = or(_T_753, _T_752) @[Mux.scala 27:72] wire ldst_byteen_r : UInt<4> @[Mux.scala 27:72] ldst_byteen_r <= _T_754 @[Mux.scala 27:72] - node _T_755 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 235:50] - node _T_756 = eq(_T_755, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 235:55] - node _T_757 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 236:19] - node _T_758 = eq(_T_757, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 236:24] - node _T_759 = bits(ldst_byteen_r, 3, 3) @[el2_lsu_bus_buffer.scala 236:60] + node _T_755 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 236:50] + node _T_756 = eq(_T_755, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 236:55] + node _T_757 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 237:19] + node _T_758 = eq(_T_757, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 237:24] + node _T_759 = bits(ldst_byteen_r, 3, 3) @[el2_lsu_bus_buffer.scala 237:60] node _T_760 = cat(UInt<3>("h00"), _T_759) @[Cat.scala 29:58] - node _T_761 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 237:19] - node _T_762 = eq(_T_761, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 237:24] - node _T_763 = bits(ldst_byteen_r, 3, 2) @[el2_lsu_bus_buffer.scala 237:60] + node _T_761 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 238:19] + node _T_762 = eq(_T_761, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 238:24] + node _T_763 = bits(ldst_byteen_r, 3, 2) @[el2_lsu_bus_buffer.scala 238:60] node _T_764 = cat(UInt<2>("h00"), _T_763) @[Cat.scala 29:58] - node _T_765 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 238:19] - node _T_766 = eq(_T_765, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 238:24] - node _T_767 = bits(ldst_byteen_r, 3, 1) @[el2_lsu_bus_buffer.scala 238:60] + node _T_765 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 239:19] + node _T_766 = eq(_T_765, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 239:24] + node _T_767 = bits(ldst_byteen_r, 3, 1) @[el2_lsu_bus_buffer.scala 239:60] node _T_768 = cat(UInt<1>("h00"), _T_767) @[Cat.scala 29:58] node _T_769 = mux(_T_756, UInt<4>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_770 = mux(_T_758, _T_760, UInt<1>("h00")) @[Mux.scala 27:72] @@ -1268,19 +1270,19 @@ circuit el2_lsu_bus_intf : node _T_775 = or(_T_774, _T_772) @[Mux.scala 27:72] wire ldst_byteen_hi_r : UInt<4> @[Mux.scala 27:72] ldst_byteen_hi_r <= _T_775 @[Mux.scala 27:72] - node _T_776 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 239:50] - node _T_777 = eq(_T_776, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 239:55] - node _T_778 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 240:19] - node _T_779 = eq(_T_778, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 240:24] - node _T_780 = bits(ldst_byteen_r, 2, 0) @[el2_lsu_bus_buffer.scala 240:50] + node _T_776 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 240:50] + node _T_777 = eq(_T_776, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 240:55] + node _T_778 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 241:19] + node _T_779 = eq(_T_778, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 241:24] + node _T_780 = bits(ldst_byteen_r, 2, 0) @[el2_lsu_bus_buffer.scala 241:50] node _T_781 = cat(_T_780, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_782 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 241:19] - node _T_783 = eq(_T_782, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 241:24] - node _T_784 = bits(ldst_byteen_r, 1, 0) @[el2_lsu_bus_buffer.scala 241:50] + node _T_782 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 242:19] + node _T_783 = eq(_T_782, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 242:24] + node _T_784 = bits(ldst_byteen_r, 1, 0) @[el2_lsu_bus_buffer.scala 242:50] node _T_785 = cat(_T_784, UInt<2>("h00")) @[Cat.scala 29:58] - node _T_786 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 242:19] - node _T_787 = eq(_T_786, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 242:24] - node _T_788 = bits(ldst_byteen_r, 0, 0) @[el2_lsu_bus_buffer.scala 242:50] + node _T_786 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 243:19] + node _T_787 = eq(_T_786, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 243:24] + node _T_788 = bits(ldst_byteen_r, 0, 0) @[el2_lsu_bus_buffer.scala 243:50] node _T_789 = cat(_T_788, UInt<3>("h00")) @[Cat.scala 29:58] node _T_790 = mux(_T_777, ldst_byteen_r, UInt<1>("h00")) @[Mux.scala 27:72] node _T_791 = mux(_T_779, _T_781, UInt<1>("h00")) @[Mux.scala 27:72] @@ -1291,19 +1293,19 @@ circuit el2_lsu_bus_intf : node _T_796 = or(_T_795, _T_793) @[Mux.scala 27:72] wire ldst_byteen_lo_r : UInt<4> @[Mux.scala 27:72] ldst_byteen_lo_r <= _T_796 @[Mux.scala 27:72] - node _T_797 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 244:49] - node _T_798 = eq(_T_797, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 244:54] - node _T_799 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 245:19] - node _T_800 = eq(_T_799, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 245:24] - node _T_801 = bits(io.store_data_r, 31, 24) @[el2_lsu_bus_buffer.scala 245:64] + node _T_797 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 245:49] + node _T_798 = eq(_T_797, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 245:54] + node _T_799 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 246:19] + node _T_800 = eq(_T_799, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 246:24] + node _T_801 = bits(io.store_data_r, 31, 24) @[el2_lsu_bus_buffer.scala 246:64] node _T_802 = cat(UInt<24>("h00"), _T_801) @[Cat.scala 29:58] - node _T_803 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 246:19] - node _T_804 = eq(_T_803, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 246:24] - node _T_805 = bits(io.store_data_r, 31, 16) @[el2_lsu_bus_buffer.scala 246:63] + node _T_803 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 247:19] + node _T_804 = eq(_T_803, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 247:24] + node _T_805 = bits(io.store_data_r, 31, 16) @[el2_lsu_bus_buffer.scala 247:63] node _T_806 = cat(UInt<16>("h00"), _T_805) @[Cat.scala 29:58] - node _T_807 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 247:19] - node _T_808 = eq(_T_807, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 247:24] - node _T_809 = bits(io.store_data_r, 31, 8) @[el2_lsu_bus_buffer.scala 247:62] + node _T_807 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 248:19] + node _T_808 = eq(_T_807, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 248:24] + node _T_809 = bits(io.store_data_r, 31, 8) @[el2_lsu_bus_buffer.scala 248:62] node _T_810 = cat(UInt<8>("h00"), _T_809) @[Cat.scala 29:58] node _T_811 = mux(_T_798, UInt<32>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_812 = mux(_T_800, _T_802, UInt<1>("h00")) @[Mux.scala 27:72] @@ -1314,19 +1316,19 @@ circuit el2_lsu_bus_intf : node _T_817 = or(_T_816, _T_814) @[Mux.scala 27:72] wire store_data_hi_r : UInt<32> @[Mux.scala 27:72] store_data_hi_r <= _T_817 @[Mux.scala 27:72] - node _T_818 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 249:49] - node _T_819 = eq(_T_818, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 249:54] - node _T_820 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 250:19] - node _T_821 = eq(_T_820, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 250:24] - node _T_822 = bits(io.store_data_r, 23, 0) @[el2_lsu_bus_buffer.scala 250:52] + node _T_818 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 250:49] + node _T_819 = eq(_T_818, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 250:54] + node _T_820 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 251:19] + node _T_821 = eq(_T_820, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 251:24] + node _T_822 = bits(io.store_data_r, 23, 0) @[el2_lsu_bus_buffer.scala 251:52] node _T_823 = cat(_T_822, UInt<8>("h00")) @[Cat.scala 29:58] - node _T_824 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 251:19] - node _T_825 = eq(_T_824, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 251:24] - node _T_826 = bits(io.store_data_r, 15, 0) @[el2_lsu_bus_buffer.scala 251:52] + node _T_824 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 252:19] + node _T_825 = eq(_T_824, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 252:24] + node _T_826 = bits(io.store_data_r, 15, 0) @[el2_lsu_bus_buffer.scala 252:52] node _T_827 = cat(_T_826, UInt<16>("h00")) @[Cat.scala 29:58] - node _T_828 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 252:19] - node _T_829 = eq(_T_828, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 252:24] - node _T_830 = bits(io.store_data_r, 7, 0) @[el2_lsu_bus_buffer.scala 252:52] + node _T_828 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 253:19] + node _T_829 = eq(_T_828, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 253:24] + node _T_830 = bits(io.store_data_r, 7, 0) @[el2_lsu_bus_buffer.scala 253:52] node _T_831 = cat(_T_830, UInt<24>("h00")) @[Cat.scala 29:58] node _T_832 = mux(_T_819, io.store_data_r, UInt<1>("h00")) @[Mux.scala 27:72] node _T_833 = mux(_T_821, _T_823, UInt<1>("h00")) @[Mux.scala 27:72] @@ -1337,40 +1339,40 @@ circuit el2_lsu_bus_intf : node _T_838 = or(_T_837, _T_835) @[Mux.scala 27:72] wire store_data_lo_r : UInt<32> @[Mux.scala 27:72] store_data_lo_r <= _T_838 @[Mux.scala 27:72] - node _T_839 = bits(io.lsu_addr_r, 3, 3) @[el2_lsu_bus_buffer.scala 255:36] - node _T_840 = bits(io.end_addr_r, 3, 3) @[el2_lsu_bus_buffer.scala 255:57] - node ldst_samedw_r = eq(_T_839, _T_840) @[el2_lsu_bus_buffer.scala 255:40] - node _T_841 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 256:67] - node _T_842 = eq(_T_841, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 256:74] - node _T_843 = bits(io.lsu_addr_r, 0, 0) @[el2_lsu_bus_buffer.scala 257:40] - node _T_844 = eq(_T_843, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 257:26] - node _T_845 = mux(io.lsu_pkt_r.word, _T_842, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_846 = mux(io.lsu_pkt_r.half, _T_844, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_847 = mux(io.lsu_pkt_r.by, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_839 = bits(io.lsu_addr_r, 3, 3) @[el2_lsu_bus_buffer.scala 256:36] + node _T_840 = bits(io.end_addr_r, 3, 3) @[el2_lsu_bus_buffer.scala 256:57] + node ldst_samedw_r = eq(_T_839, _T_840) @[el2_lsu_bus_buffer.scala 256:40] + node _T_841 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 257:72] + node _T_842 = eq(_T_841, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 257:79] + node _T_843 = bits(io.lsu_addr_r, 0, 0) @[el2_lsu_bus_buffer.scala 258:45] + node _T_844 = eq(_T_843, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 258:31] + node _T_845 = mux(io.lsu_pkt_r.bits.word, _T_842, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_846 = mux(io.lsu_pkt_r.bits.half, _T_844, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_847 = mux(io.lsu_pkt_r.bits.by, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_848 = or(_T_845, _T_846) @[Mux.scala 27:72] node _T_849 = or(_T_848, _T_847) @[Mux.scala 27:72] wire is_aligned_r : UInt<1> @[Mux.scala 27:72] is_aligned_r <= _T_849 @[Mux.scala 27:72] - node _T_850 = or(io.lsu_pkt_r.load, io.no_word_merge_r) @[el2_lsu_bus_buffer.scala 259:55] - node _T_851 = and(io.lsu_busreq_r, _T_850) @[el2_lsu_bus_buffer.scala 259:34] - node _T_852 = eq(ibuf_valid, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 259:79] - node ibuf_byp = and(_T_851, _T_852) @[el2_lsu_bus_buffer.scala 259:77] - node _T_853 = and(io.lsu_busreq_r, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 260:36] - node _T_854 = eq(ibuf_byp, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 260:56] - node ibuf_wr_en = and(_T_853, _T_854) @[el2_lsu_bus_buffer.scala 260:54] + node _T_850 = or(io.lsu_pkt_r.bits.load, io.no_word_merge_r) @[el2_lsu_bus_buffer.scala 260:60] + node _T_851 = and(io.lsu_busreq_r, _T_850) @[el2_lsu_bus_buffer.scala 260:34] + node _T_852 = eq(ibuf_valid, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 260:84] + node ibuf_byp = and(_T_851, _T_852) @[el2_lsu_bus_buffer.scala 260:82] + node _T_853 = and(io.lsu_busreq_r, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 261:36] + node _T_854 = eq(ibuf_byp, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 261:56] + node ibuf_wr_en = and(_T_853, _T_854) @[el2_lsu_bus_buffer.scala 261:54] wire ibuf_drain_vld : UInt<1> ibuf_drain_vld <= UInt<1>("h00") - node _T_855 = eq(ibuf_wr_en, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 262:36] - node _T_856 = and(ibuf_drain_vld, _T_855) @[el2_lsu_bus_buffer.scala 262:34] - node ibuf_rst = or(_T_856, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 262:49] - node _T_857 = eq(io.lsu_busreq_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 263:44] - node _T_858 = and(io.lsu_busreq_m, _T_857) @[el2_lsu_bus_buffer.scala 263:42] - node _T_859 = and(_T_858, ibuf_valid) @[el2_lsu_bus_buffer.scala 263:61] - node _T_860 = bits(ibuf_addr, 31, 2) @[el2_lsu_bus_buffer.scala 263:107] - node _T_861 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 263:132] - node _T_862 = neq(_T_860, _T_861) @[el2_lsu_bus_buffer.scala 263:115] - node _T_863 = or(io.lsu_pkt_m.load, _T_862) @[el2_lsu_bus_buffer.scala 263:95] - node ibuf_force_drain = and(_T_859, _T_863) @[el2_lsu_bus_buffer.scala 263:74] + node _T_855 = eq(ibuf_wr_en, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 263:36] + node _T_856 = and(ibuf_drain_vld, _T_855) @[el2_lsu_bus_buffer.scala 263:34] + node ibuf_rst = or(_T_856, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 263:49] + node _T_857 = eq(io.lsu_busreq_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 264:44] + node _T_858 = and(io.lsu_busreq_m, _T_857) @[el2_lsu_bus_buffer.scala 264:42] + node _T_859 = and(_T_858, ibuf_valid) @[el2_lsu_bus_buffer.scala 264:61] + node _T_860 = bits(ibuf_addr, 31, 2) @[el2_lsu_bus_buffer.scala 264:112] + node _T_861 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 264:137] + node _T_862 = neq(_T_860, _T_861) @[el2_lsu_bus_buffer.scala 264:120] + node _T_863 = or(io.lsu_pkt_m.bits.load, _T_862) @[el2_lsu_bus_buffer.scala 264:100] + node ibuf_force_drain = and(_T_859, _T_863) @[el2_lsu_bus_buffer.scala 264:74] wire ibuf_sideeffect : UInt<1> ibuf_sideeffect <= UInt<1>("h00") wire ibuf_timer : UInt<3> @@ -1379,175 +1381,175 @@ circuit el2_lsu_bus_intf : ibuf_merge_en <= UInt<1>("h00") wire ibuf_merge_in : UInt<1> ibuf_merge_in <= UInt<1>("h00") - node _T_864 = eq(ibuf_timer, UInt<3>("h07")) @[el2_lsu_bus_buffer.scala 268:62] - node _T_865 = or(ibuf_wr_en, _T_864) @[el2_lsu_bus_buffer.scala 268:48] - node _T_866 = and(ibuf_merge_en, ibuf_merge_in) @[el2_lsu_bus_buffer.scala 268:98] - node _T_867 = eq(_T_866, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 268:82] - node _T_868 = and(_T_865, _T_867) @[el2_lsu_bus_buffer.scala 268:80] - node _T_869 = or(_T_868, ibuf_byp) @[el2_lsu_bus_buffer.scala 269:5] - node _T_870 = or(_T_869, ibuf_force_drain) @[el2_lsu_bus_buffer.scala 269:16] - node _T_871 = or(_T_870, ibuf_sideeffect) @[el2_lsu_bus_buffer.scala 269:35] - node _T_872 = eq(ibuf_write, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 269:55] - node _T_873 = or(_T_871, _T_872) @[el2_lsu_bus_buffer.scala 269:53] - node _T_874 = or(_T_873, bus_coalescing_disable) @[el2_lsu_bus_buffer.scala 269:67] - node _T_875 = and(ibuf_valid, _T_874) @[el2_lsu_bus_buffer.scala 268:32] - ibuf_drain_vld <= _T_875 @[el2_lsu_bus_buffer.scala 268:18] + node _T_864 = eq(ibuf_timer, UInt<3>("h07")) @[el2_lsu_bus_buffer.scala 269:62] + node _T_865 = or(ibuf_wr_en, _T_864) @[el2_lsu_bus_buffer.scala 269:48] + node _T_866 = and(ibuf_merge_en, ibuf_merge_in) @[el2_lsu_bus_buffer.scala 269:98] + node _T_867 = eq(_T_866, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 269:82] + node _T_868 = and(_T_865, _T_867) @[el2_lsu_bus_buffer.scala 269:80] + node _T_869 = or(_T_868, ibuf_byp) @[el2_lsu_bus_buffer.scala 270:5] + node _T_870 = or(_T_869, ibuf_force_drain) @[el2_lsu_bus_buffer.scala 270:16] + node _T_871 = or(_T_870, ibuf_sideeffect) @[el2_lsu_bus_buffer.scala 270:35] + node _T_872 = eq(ibuf_write, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 270:55] + node _T_873 = or(_T_871, _T_872) @[el2_lsu_bus_buffer.scala 270:53] + node _T_874 = or(_T_873, bus_coalescing_disable) @[el2_lsu_bus_buffer.scala 270:67] + node _T_875 = and(ibuf_valid, _T_874) @[el2_lsu_bus_buffer.scala 269:32] + ibuf_drain_vld <= _T_875 @[el2_lsu_bus_buffer.scala 269:18] wire ibuf_tag : UInt<2> ibuf_tag <= UInt<1>("h00") wire WrPtr1_r : UInt<2> WrPtr1_r <= UInt<1>("h00") wire WrPtr0_r : UInt<2> WrPtr0_r <= UInt<1>("h00") - node _T_876 = and(ibuf_merge_en, ibuf_merge_in) @[el2_lsu_bus_buffer.scala 274:39] - node _T_877 = mux(io.ldst_dual_r, WrPtr1_r, WrPtr0_r) @[el2_lsu_bus_buffer.scala 274:69] - node ibuf_tag_in = mux(_T_876, ibuf_tag, _T_877) @[el2_lsu_bus_buffer.scala 274:24] - node ibuf_sz_in = cat(io.lsu_pkt_r.word, io.lsu_pkt_r.half) @[Cat.scala 29:58] - node ibuf_addr_in = mux(io.ldst_dual_r, io.end_addr_r, io.lsu_addr_r) @[el2_lsu_bus_buffer.scala 277:25] - node _T_878 = and(ibuf_merge_en, ibuf_merge_in) @[el2_lsu_bus_buffer.scala 278:42] - node _T_879 = bits(ibuf_byteen, 3, 0) @[el2_lsu_bus_buffer.scala 278:70] - node _T_880 = bits(ldst_byteen_lo_r, 3, 0) @[el2_lsu_bus_buffer.scala 278:95] - node _T_881 = or(_T_879, _T_880) @[el2_lsu_bus_buffer.scala 278:77] - node _T_882 = bits(ldst_byteen_hi_r, 3, 0) @[el2_lsu_bus_buffer.scala 279:41] - node _T_883 = bits(ldst_byteen_lo_r, 3, 0) @[el2_lsu_bus_buffer.scala 279:65] - node _T_884 = mux(io.ldst_dual_r, _T_882, _T_883) @[el2_lsu_bus_buffer.scala 279:8] - node ibuf_byteen_in = mux(_T_878, _T_881, _T_884) @[el2_lsu_bus_buffer.scala 278:27] - node _T_885 = and(ibuf_merge_en, ibuf_merge_in) @[el2_lsu_bus_buffer.scala 282:61] - node _T_886 = bits(ldst_byteen_lo_r, 0, 0) @[el2_lsu_bus_buffer.scala 283:25] - node _T_887 = bits(store_data_lo_r, 7, 0) @[el2_lsu_bus_buffer.scala 283:45] - node _T_888 = bits(ibuf_data, 7, 0) @[el2_lsu_bus_buffer.scala 283:76] - node _T_889 = mux(_T_886, _T_887, _T_888) @[el2_lsu_bus_buffer.scala 283:8] - node _T_890 = bits(store_data_hi_r, 7, 0) @[el2_lsu_bus_buffer.scala 284:40] - node _T_891 = bits(store_data_lo_r, 7, 0) @[el2_lsu_bus_buffer.scala 284:77] - node _T_892 = mux(io.ldst_dual_r, _T_890, _T_891) @[el2_lsu_bus_buffer.scala 284:8] - node _T_893 = mux(_T_885, _T_889, _T_892) @[el2_lsu_bus_buffer.scala 282:46] - node _T_894 = and(ibuf_merge_en, ibuf_merge_in) @[el2_lsu_bus_buffer.scala 282:61] - node _T_895 = bits(ldst_byteen_lo_r, 1, 1) @[el2_lsu_bus_buffer.scala 283:25] - node _T_896 = bits(store_data_lo_r, 15, 8) @[el2_lsu_bus_buffer.scala 283:45] - node _T_897 = bits(ibuf_data, 15, 8) @[el2_lsu_bus_buffer.scala 283:76] - node _T_898 = mux(_T_895, _T_896, _T_897) @[el2_lsu_bus_buffer.scala 283:8] - node _T_899 = bits(store_data_hi_r, 15, 8) @[el2_lsu_bus_buffer.scala 284:40] - node _T_900 = bits(store_data_lo_r, 15, 8) @[el2_lsu_bus_buffer.scala 284:77] - node _T_901 = mux(io.ldst_dual_r, _T_899, _T_900) @[el2_lsu_bus_buffer.scala 284:8] - node _T_902 = mux(_T_894, _T_898, _T_901) @[el2_lsu_bus_buffer.scala 282:46] - node _T_903 = and(ibuf_merge_en, ibuf_merge_in) @[el2_lsu_bus_buffer.scala 282:61] - node _T_904 = bits(ldst_byteen_lo_r, 2, 2) @[el2_lsu_bus_buffer.scala 283:25] - node _T_905 = bits(store_data_lo_r, 23, 16) @[el2_lsu_bus_buffer.scala 283:45] - node _T_906 = bits(ibuf_data, 23, 16) @[el2_lsu_bus_buffer.scala 283:76] - node _T_907 = mux(_T_904, _T_905, _T_906) @[el2_lsu_bus_buffer.scala 283:8] - node _T_908 = bits(store_data_hi_r, 23, 16) @[el2_lsu_bus_buffer.scala 284:40] - node _T_909 = bits(store_data_lo_r, 23, 16) @[el2_lsu_bus_buffer.scala 284:77] - node _T_910 = mux(io.ldst_dual_r, _T_908, _T_909) @[el2_lsu_bus_buffer.scala 284:8] - node _T_911 = mux(_T_903, _T_907, _T_910) @[el2_lsu_bus_buffer.scala 282:46] - node _T_912 = and(ibuf_merge_en, ibuf_merge_in) @[el2_lsu_bus_buffer.scala 282:61] - node _T_913 = bits(ldst_byteen_lo_r, 3, 3) @[el2_lsu_bus_buffer.scala 283:25] - node _T_914 = bits(store_data_lo_r, 31, 24) @[el2_lsu_bus_buffer.scala 283:45] - node _T_915 = bits(ibuf_data, 31, 24) @[el2_lsu_bus_buffer.scala 283:76] - node _T_916 = mux(_T_913, _T_914, _T_915) @[el2_lsu_bus_buffer.scala 283:8] - node _T_917 = bits(store_data_hi_r, 31, 24) @[el2_lsu_bus_buffer.scala 284:40] - node _T_918 = bits(store_data_lo_r, 31, 24) @[el2_lsu_bus_buffer.scala 284:77] - node _T_919 = mux(io.ldst_dual_r, _T_917, _T_918) @[el2_lsu_bus_buffer.scala 284:8] - node _T_920 = mux(_T_912, _T_916, _T_919) @[el2_lsu_bus_buffer.scala 282:46] + node _T_876 = and(ibuf_merge_en, ibuf_merge_in) @[el2_lsu_bus_buffer.scala 275:39] + node _T_877 = mux(io.ldst_dual_r, WrPtr1_r, WrPtr0_r) @[el2_lsu_bus_buffer.scala 275:69] + node ibuf_tag_in = mux(_T_876, ibuf_tag, _T_877) @[el2_lsu_bus_buffer.scala 275:24] + node ibuf_sz_in = cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) @[Cat.scala 29:58] + node ibuf_addr_in = mux(io.ldst_dual_r, io.end_addr_r, io.lsu_addr_r) @[el2_lsu_bus_buffer.scala 278:25] + node _T_878 = and(ibuf_merge_en, ibuf_merge_in) @[el2_lsu_bus_buffer.scala 279:42] + node _T_879 = bits(ibuf_byteen, 3, 0) @[el2_lsu_bus_buffer.scala 279:70] + node _T_880 = bits(ldst_byteen_lo_r, 3, 0) @[el2_lsu_bus_buffer.scala 279:95] + node _T_881 = or(_T_879, _T_880) @[el2_lsu_bus_buffer.scala 279:77] + node _T_882 = bits(ldst_byteen_hi_r, 3, 0) @[el2_lsu_bus_buffer.scala 280:41] + node _T_883 = bits(ldst_byteen_lo_r, 3, 0) @[el2_lsu_bus_buffer.scala 280:65] + node _T_884 = mux(io.ldst_dual_r, _T_882, _T_883) @[el2_lsu_bus_buffer.scala 280:8] + node ibuf_byteen_in = mux(_T_878, _T_881, _T_884) @[el2_lsu_bus_buffer.scala 279:27] + node _T_885 = and(ibuf_merge_en, ibuf_merge_in) @[el2_lsu_bus_buffer.scala 283:61] + node _T_886 = bits(ldst_byteen_lo_r, 0, 0) @[el2_lsu_bus_buffer.scala 284:25] + node _T_887 = bits(store_data_lo_r, 7, 0) @[el2_lsu_bus_buffer.scala 284:45] + node _T_888 = bits(ibuf_data, 7, 0) @[el2_lsu_bus_buffer.scala 284:76] + node _T_889 = mux(_T_886, _T_887, _T_888) @[el2_lsu_bus_buffer.scala 284:8] + node _T_890 = bits(store_data_hi_r, 7, 0) @[el2_lsu_bus_buffer.scala 285:40] + node _T_891 = bits(store_data_lo_r, 7, 0) @[el2_lsu_bus_buffer.scala 285:77] + node _T_892 = mux(io.ldst_dual_r, _T_890, _T_891) @[el2_lsu_bus_buffer.scala 285:8] + node _T_893 = mux(_T_885, _T_889, _T_892) @[el2_lsu_bus_buffer.scala 283:46] + node _T_894 = and(ibuf_merge_en, ibuf_merge_in) @[el2_lsu_bus_buffer.scala 283:61] + node _T_895 = bits(ldst_byteen_lo_r, 1, 1) @[el2_lsu_bus_buffer.scala 284:25] + node _T_896 = bits(store_data_lo_r, 15, 8) @[el2_lsu_bus_buffer.scala 284:45] + node _T_897 = bits(ibuf_data, 15, 8) @[el2_lsu_bus_buffer.scala 284:76] + node _T_898 = mux(_T_895, _T_896, _T_897) @[el2_lsu_bus_buffer.scala 284:8] + node _T_899 = bits(store_data_hi_r, 15, 8) @[el2_lsu_bus_buffer.scala 285:40] + node _T_900 = bits(store_data_lo_r, 15, 8) @[el2_lsu_bus_buffer.scala 285:77] + node _T_901 = mux(io.ldst_dual_r, _T_899, _T_900) @[el2_lsu_bus_buffer.scala 285:8] + node _T_902 = mux(_T_894, _T_898, _T_901) @[el2_lsu_bus_buffer.scala 283:46] + node _T_903 = and(ibuf_merge_en, ibuf_merge_in) @[el2_lsu_bus_buffer.scala 283:61] + node _T_904 = bits(ldst_byteen_lo_r, 2, 2) @[el2_lsu_bus_buffer.scala 284:25] + node _T_905 = bits(store_data_lo_r, 23, 16) @[el2_lsu_bus_buffer.scala 284:45] + node _T_906 = bits(ibuf_data, 23, 16) @[el2_lsu_bus_buffer.scala 284:76] + node _T_907 = mux(_T_904, _T_905, _T_906) @[el2_lsu_bus_buffer.scala 284:8] + node _T_908 = bits(store_data_hi_r, 23, 16) @[el2_lsu_bus_buffer.scala 285:40] + node _T_909 = bits(store_data_lo_r, 23, 16) @[el2_lsu_bus_buffer.scala 285:77] + node _T_910 = mux(io.ldst_dual_r, _T_908, _T_909) @[el2_lsu_bus_buffer.scala 285:8] + node _T_911 = mux(_T_903, _T_907, _T_910) @[el2_lsu_bus_buffer.scala 283:46] + node _T_912 = and(ibuf_merge_en, ibuf_merge_in) @[el2_lsu_bus_buffer.scala 283:61] + node _T_913 = bits(ldst_byteen_lo_r, 3, 3) @[el2_lsu_bus_buffer.scala 284:25] + node _T_914 = bits(store_data_lo_r, 31, 24) @[el2_lsu_bus_buffer.scala 284:45] + node _T_915 = bits(ibuf_data, 31, 24) @[el2_lsu_bus_buffer.scala 284:76] + node _T_916 = mux(_T_913, _T_914, _T_915) @[el2_lsu_bus_buffer.scala 284:8] + node _T_917 = bits(store_data_hi_r, 31, 24) @[el2_lsu_bus_buffer.scala 285:40] + node _T_918 = bits(store_data_lo_r, 31, 24) @[el2_lsu_bus_buffer.scala 285:77] + node _T_919 = mux(io.ldst_dual_r, _T_917, _T_918) @[el2_lsu_bus_buffer.scala 285:8] + node _T_920 = mux(_T_912, _T_916, _T_919) @[el2_lsu_bus_buffer.scala 283:46] node _T_921 = cat(_T_920, _T_911) @[Cat.scala 29:58] node _T_922 = cat(_T_921, _T_902) @[Cat.scala 29:58] node ibuf_data_in = cat(_T_922, _T_893) @[Cat.scala 29:58] - node _T_923 = lt(ibuf_timer, UInt<3>("h07")) @[el2_lsu_bus_buffer.scala 285:59] - node _T_924 = bits(_T_923, 0, 0) @[el2_lsu_bus_buffer.scala 285:79] - node _T_925 = add(ibuf_timer, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 285:93] - node _T_926 = tail(_T_925, 1) @[el2_lsu_bus_buffer.scala 285:93] - node _T_927 = mux(_T_924, _T_926, ibuf_timer) @[el2_lsu_bus_buffer.scala 285:47] - node ibuf_timer_in = mux(ibuf_wr_en, UInt<1>("h00"), _T_927) @[el2_lsu_bus_buffer.scala 285:26] - node _T_928 = and(io.lsu_busreq_r, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 287:36] - node _T_929 = and(_T_928, io.lsu_pkt_r.store) @[el2_lsu_bus_buffer.scala 287:54] - node _T_930 = and(_T_929, ibuf_valid) @[el2_lsu_bus_buffer.scala 287:75] - node _T_931 = and(_T_930, ibuf_write) @[el2_lsu_bus_buffer.scala 287:88] - node _T_932 = bits(io.lsu_addr_r, 31, 2) @[el2_lsu_bus_buffer.scala 287:117] - node _T_933 = bits(ibuf_addr, 31, 2) @[el2_lsu_bus_buffer.scala 287:137] - node _T_934 = eq(_T_932, _T_933) @[el2_lsu_bus_buffer.scala 287:124] - node _T_935 = and(_T_931, _T_934) @[el2_lsu_bus_buffer.scala 287:101] - node _T_936 = eq(io.is_sideeffects_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 287:147] - node _T_937 = and(_T_935, _T_936) @[el2_lsu_bus_buffer.scala 287:145] - node _T_938 = eq(bus_coalescing_disable, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 287:170] - node _T_939 = and(_T_937, _T_938) @[el2_lsu_bus_buffer.scala 287:168] - ibuf_merge_en <= _T_939 @[el2_lsu_bus_buffer.scala 287:17] - node _T_940 = eq(io.ldst_dual_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 288:20] - ibuf_merge_in <= _T_940 @[el2_lsu_bus_buffer.scala 288:17] - node _T_941 = eq(ibuf_merge_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 289:65] - node _T_942 = and(ibuf_merge_en, _T_941) @[el2_lsu_bus_buffer.scala 289:63] - node _T_943 = bits(ibuf_byteen, 0, 0) @[el2_lsu_bus_buffer.scala 289:92] - node _T_944 = bits(ldst_byteen_lo_r, 0, 0) @[el2_lsu_bus_buffer.scala 289:114] - node _T_945 = or(_T_943, _T_944) @[el2_lsu_bus_buffer.scala 289:96] - node _T_946 = bits(ibuf_byteen, 0, 0) @[el2_lsu_bus_buffer.scala 289:130] - node _T_947 = mux(_T_942, _T_945, _T_946) @[el2_lsu_bus_buffer.scala 289:48] - node _T_948 = eq(ibuf_merge_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 289:65] - node _T_949 = and(ibuf_merge_en, _T_948) @[el2_lsu_bus_buffer.scala 289:63] - node _T_950 = bits(ibuf_byteen, 1, 1) @[el2_lsu_bus_buffer.scala 289:92] - node _T_951 = bits(ldst_byteen_lo_r, 1, 1) @[el2_lsu_bus_buffer.scala 289:114] - node _T_952 = or(_T_950, _T_951) @[el2_lsu_bus_buffer.scala 289:96] - node _T_953 = bits(ibuf_byteen, 1, 1) @[el2_lsu_bus_buffer.scala 289:130] - node _T_954 = mux(_T_949, _T_952, _T_953) @[el2_lsu_bus_buffer.scala 289:48] - node _T_955 = eq(ibuf_merge_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 289:65] - node _T_956 = and(ibuf_merge_en, _T_955) @[el2_lsu_bus_buffer.scala 289:63] - node _T_957 = bits(ibuf_byteen, 2, 2) @[el2_lsu_bus_buffer.scala 289:92] - node _T_958 = bits(ldst_byteen_lo_r, 2, 2) @[el2_lsu_bus_buffer.scala 289:114] - node _T_959 = or(_T_957, _T_958) @[el2_lsu_bus_buffer.scala 289:96] - node _T_960 = bits(ibuf_byteen, 2, 2) @[el2_lsu_bus_buffer.scala 289:130] - node _T_961 = mux(_T_956, _T_959, _T_960) @[el2_lsu_bus_buffer.scala 289:48] - node _T_962 = eq(ibuf_merge_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 289:65] - node _T_963 = and(ibuf_merge_en, _T_962) @[el2_lsu_bus_buffer.scala 289:63] - node _T_964 = bits(ibuf_byteen, 3, 3) @[el2_lsu_bus_buffer.scala 289:92] - node _T_965 = bits(ldst_byteen_lo_r, 3, 3) @[el2_lsu_bus_buffer.scala 289:114] - node _T_966 = or(_T_964, _T_965) @[el2_lsu_bus_buffer.scala 289:96] - node _T_967 = bits(ibuf_byteen, 3, 3) @[el2_lsu_bus_buffer.scala 289:130] - node _T_968 = mux(_T_963, _T_966, _T_967) @[el2_lsu_bus_buffer.scala 289:48] + node _T_923 = lt(ibuf_timer, UInt<3>("h07")) @[el2_lsu_bus_buffer.scala 286:59] + node _T_924 = bits(_T_923, 0, 0) @[el2_lsu_bus_buffer.scala 286:79] + node _T_925 = add(ibuf_timer, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 286:93] + node _T_926 = tail(_T_925, 1) @[el2_lsu_bus_buffer.scala 286:93] + node _T_927 = mux(_T_924, _T_926, ibuf_timer) @[el2_lsu_bus_buffer.scala 286:47] + node ibuf_timer_in = mux(ibuf_wr_en, UInt<1>("h00"), _T_927) @[el2_lsu_bus_buffer.scala 286:26] + node _T_928 = and(io.lsu_busreq_r, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 288:36] + node _T_929 = and(_T_928, io.lsu_pkt_r.bits.store) @[el2_lsu_bus_buffer.scala 288:54] + node _T_930 = and(_T_929, ibuf_valid) @[el2_lsu_bus_buffer.scala 288:80] + node _T_931 = and(_T_930, ibuf_write) @[el2_lsu_bus_buffer.scala 288:93] + node _T_932 = bits(io.lsu_addr_r, 31, 2) @[el2_lsu_bus_buffer.scala 288:122] + node _T_933 = bits(ibuf_addr, 31, 2) @[el2_lsu_bus_buffer.scala 288:142] + node _T_934 = eq(_T_932, _T_933) @[el2_lsu_bus_buffer.scala 288:129] + node _T_935 = and(_T_931, _T_934) @[el2_lsu_bus_buffer.scala 288:106] + node _T_936 = eq(io.is_sideeffects_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 288:152] + node _T_937 = and(_T_935, _T_936) @[el2_lsu_bus_buffer.scala 288:150] + node _T_938 = eq(bus_coalescing_disable, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 288:175] + node _T_939 = and(_T_937, _T_938) @[el2_lsu_bus_buffer.scala 288:173] + ibuf_merge_en <= _T_939 @[el2_lsu_bus_buffer.scala 288:17] + node _T_940 = eq(io.ldst_dual_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 289:20] + ibuf_merge_in <= _T_940 @[el2_lsu_bus_buffer.scala 289:17] + node _T_941 = eq(ibuf_merge_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 290:65] + node _T_942 = and(ibuf_merge_en, _T_941) @[el2_lsu_bus_buffer.scala 290:63] + node _T_943 = bits(ibuf_byteen, 0, 0) @[el2_lsu_bus_buffer.scala 290:92] + node _T_944 = bits(ldst_byteen_lo_r, 0, 0) @[el2_lsu_bus_buffer.scala 290:114] + node _T_945 = or(_T_943, _T_944) @[el2_lsu_bus_buffer.scala 290:96] + node _T_946 = bits(ibuf_byteen, 0, 0) @[el2_lsu_bus_buffer.scala 290:130] + node _T_947 = mux(_T_942, _T_945, _T_946) @[el2_lsu_bus_buffer.scala 290:48] + node _T_948 = eq(ibuf_merge_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 290:65] + node _T_949 = and(ibuf_merge_en, _T_948) @[el2_lsu_bus_buffer.scala 290:63] + node _T_950 = bits(ibuf_byteen, 1, 1) @[el2_lsu_bus_buffer.scala 290:92] + node _T_951 = bits(ldst_byteen_lo_r, 1, 1) @[el2_lsu_bus_buffer.scala 290:114] + node _T_952 = or(_T_950, _T_951) @[el2_lsu_bus_buffer.scala 290:96] + node _T_953 = bits(ibuf_byteen, 1, 1) @[el2_lsu_bus_buffer.scala 290:130] + node _T_954 = mux(_T_949, _T_952, _T_953) @[el2_lsu_bus_buffer.scala 290:48] + node _T_955 = eq(ibuf_merge_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 290:65] + node _T_956 = and(ibuf_merge_en, _T_955) @[el2_lsu_bus_buffer.scala 290:63] + node _T_957 = bits(ibuf_byteen, 2, 2) @[el2_lsu_bus_buffer.scala 290:92] + node _T_958 = bits(ldst_byteen_lo_r, 2, 2) @[el2_lsu_bus_buffer.scala 290:114] + node _T_959 = or(_T_957, _T_958) @[el2_lsu_bus_buffer.scala 290:96] + node _T_960 = bits(ibuf_byteen, 2, 2) @[el2_lsu_bus_buffer.scala 290:130] + node _T_961 = mux(_T_956, _T_959, _T_960) @[el2_lsu_bus_buffer.scala 290:48] + node _T_962 = eq(ibuf_merge_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 290:65] + node _T_963 = and(ibuf_merge_en, _T_962) @[el2_lsu_bus_buffer.scala 290:63] + node _T_964 = bits(ibuf_byteen, 3, 3) @[el2_lsu_bus_buffer.scala 290:92] + node _T_965 = bits(ldst_byteen_lo_r, 3, 3) @[el2_lsu_bus_buffer.scala 290:114] + node _T_966 = or(_T_964, _T_965) @[el2_lsu_bus_buffer.scala 290:96] + node _T_967 = bits(ibuf_byteen, 3, 3) @[el2_lsu_bus_buffer.scala 290:130] + node _T_968 = mux(_T_963, _T_966, _T_967) @[el2_lsu_bus_buffer.scala 290:48] node _T_969 = cat(_T_968, _T_961) @[Cat.scala 29:58] node _T_970 = cat(_T_969, _T_954) @[Cat.scala 29:58] node ibuf_byteen_out = cat(_T_970, _T_947) @[Cat.scala 29:58] - node _T_971 = eq(ibuf_merge_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 290:62] - node _T_972 = and(ibuf_merge_en, _T_971) @[el2_lsu_bus_buffer.scala 290:60] - node _T_973 = bits(ldst_byteen_lo_r, 0, 0) @[el2_lsu_bus_buffer.scala 290:98] - node _T_974 = bits(store_data_lo_r, 7, 0) @[el2_lsu_bus_buffer.scala 290:118] - node _T_975 = bits(ibuf_data, 7, 0) @[el2_lsu_bus_buffer.scala 290:143] - node _T_976 = mux(_T_973, _T_974, _T_975) @[el2_lsu_bus_buffer.scala 290:81] - node _T_977 = bits(ibuf_data, 7, 0) @[el2_lsu_bus_buffer.scala 290:169] - node _T_978 = mux(_T_972, _T_976, _T_977) @[el2_lsu_bus_buffer.scala 290:45] - node _T_979 = eq(ibuf_merge_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 290:62] - node _T_980 = and(ibuf_merge_en, _T_979) @[el2_lsu_bus_buffer.scala 290:60] - node _T_981 = bits(ldst_byteen_lo_r, 1, 1) @[el2_lsu_bus_buffer.scala 290:98] - node _T_982 = bits(store_data_lo_r, 15, 8) @[el2_lsu_bus_buffer.scala 290:118] - node _T_983 = bits(ibuf_data, 15, 8) @[el2_lsu_bus_buffer.scala 290:143] - node _T_984 = mux(_T_981, _T_982, _T_983) @[el2_lsu_bus_buffer.scala 290:81] - node _T_985 = bits(ibuf_data, 15, 8) @[el2_lsu_bus_buffer.scala 290:169] - node _T_986 = mux(_T_980, _T_984, _T_985) @[el2_lsu_bus_buffer.scala 290:45] - node _T_987 = eq(ibuf_merge_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 290:62] - node _T_988 = and(ibuf_merge_en, _T_987) @[el2_lsu_bus_buffer.scala 290:60] - node _T_989 = bits(ldst_byteen_lo_r, 2, 2) @[el2_lsu_bus_buffer.scala 290:98] - node _T_990 = bits(store_data_lo_r, 23, 16) @[el2_lsu_bus_buffer.scala 290:118] - node _T_991 = bits(ibuf_data, 23, 16) @[el2_lsu_bus_buffer.scala 290:143] - node _T_992 = mux(_T_989, _T_990, _T_991) @[el2_lsu_bus_buffer.scala 290:81] - node _T_993 = bits(ibuf_data, 23, 16) @[el2_lsu_bus_buffer.scala 290:169] - node _T_994 = mux(_T_988, _T_992, _T_993) @[el2_lsu_bus_buffer.scala 290:45] - node _T_995 = eq(ibuf_merge_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 290:62] - node _T_996 = and(ibuf_merge_en, _T_995) @[el2_lsu_bus_buffer.scala 290:60] - node _T_997 = bits(ldst_byteen_lo_r, 3, 3) @[el2_lsu_bus_buffer.scala 290:98] - node _T_998 = bits(store_data_lo_r, 31, 24) @[el2_lsu_bus_buffer.scala 290:118] - node _T_999 = bits(ibuf_data, 31, 24) @[el2_lsu_bus_buffer.scala 290:143] - node _T_1000 = mux(_T_997, _T_998, _T_999) @[el2_lsu_bus_buffer.scala 290:81] - node _T_1001 = bits(ibuf_data, 31, 24) @[el2_lsu_bus_buffer.scala 290:169] - node _T_1002 = mux(_T_996, _T_1000, _T_1001) @[el2_lsu_bus_buffer.scala 290:45] + node _T_971 = eq(ibuf_merge_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 291:62] + node _T_972 = and(ibuf_merge_en, _T_971) @[el2_lsu_bus_buffer.scala 291:60] + node _T_973 = bits(ldst_byteen_lo_r, 0, 0) @[el2_lsu_bus_buffer.scala 291:98] + node _T_974 = bits(store_data_lo_r, 7, 0) @[el2_lsu_bus_buffer.scala 291:118] + node _T_975 = bits(ibuf_data, 7, 0) @[el2_lsu_bus_buffer.scala 291:143] + node _T_976 = mux(_T_973, _T_974, _T_975) @[el2_lsu_bus_buffer.scala 291:81] + node _T_977 = bits(ibuf_data, 7, 0) @[el2_lsu_bus_buffer.scala 291:169] + node _T_978 = mux(_T_972, _T_976, _T_977) @[el2_lsu_bus_buffer.scala 291:45] + node _T_979 = eq(ibuf_merge_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 291:62] + node _T_980 = and(ibuf_merge_en, _T_979) @[el2_lsu_bus_buffer.scala 291:60] + node _T_981 = bits(ldst_byteen_lo_r, 1, 1) @[el2_lsu_bus_buffer.scala 291:98] + node _T_982 = bits(store_data_lo_r, 15, 8) @[el2_lsu_bus_buffer.scala 291:118] + node _T_983 = bits(ibuf_data, 15, 8) @[el2_lsu_bus_buffer.scala 291:143] + node _T_984 = mux(_T_981, _T_982, _T_983) @[el2_lsu_bus_buffer.scala 291:81] + node _T_985 = bits(ibuf_data, 15, 8) @[el2_lsu_bus_buffer.scala 291:169] + node _T_986 = mux(_T_980, _T_984, _T_985) @[el2_lsu_bus_buffer.scala 291:45] + node _T_987 = eq(ibuf_merge_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 291:62] + node _T_988 = and(ibuf_merge_en, _T_987) @[el2_lsu_bus_buffer.scala 291:60] + node _T_989 = bits(ldst_byteen_lo_r, 2, 2) @[el2_lsu_bus_buffer.scala 291:98] + node _T_990 = bits(store_data_lo_r, 23, 16) @[el2_lsu_bus_buffer.scala 291:118] + node _T_991 = bits(ibuf_data, 23, 16) @[el2_lsu_bus_buffer.scala 291:143] + node _T_992 = mux(_T_989, _T_990, _T_991) @[el2_lsu_bus_buffer.scala 291:81] + node _T_993 = bits(ibuf_data, 23, 16) @[el2_lsu_bus_buffer.scala 291:169] + node _T_994 = mux(_T_988, _T_992, _T_993) @[el2_lsu_bus_buffer.scala 291:45] + node _T_995 = eq(ibuf_merge_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 291:62] + node _T_996 = and(ibuf_merge_en, _T_995) @[el2_lsu_bus_buffer.scala 291:60] + node _T_997 = bits(ldst_byteen_lo_r, 3, 3) @[el2_lsu_bus_buffer.scala 291:98] + node _T_998 = bits(store_data_lo_r, 31, 24) @[el2_lsu_bus_buffer.scala 291:118] + node _T_999 = bits(ibuf_data, 31, 24) @[el2_lsu_bus_buffer.scala 291:143] + node _T_1000 = mux(_T_997, _T_998, _T_999) @[el2_lsu_bus_buffer.scala 291:81] + node _T_1001 = bits(ibuf_data, 31, 24) @[el2_lsu_bus_buffer.scala 291:169] + node _T_1002 = mux(_T_996, _T_1000, _T_1001) @[el2_lsu_bus_buffer.scala 291:45] node _T_1003 = cat(_T_1002, _T_994) @[Cat.scala 29:58] node _T_1004 = cat(_T_1003, _T_986) @[Cat.scala 29:58] node ibuf_data_out = cat(_T_1004, _T_978) @[Cat.scala 29:58] - node _T_1005 = mux(ibuf_wr_en, UInt<1>("h01"), ibuf_valid) @[el2_lsu_bus_buffer.scala 292:58] - node _T_1006 = eq(ibuf_rst, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 292:93] - node _T_1007 = and(_T_1005, _T_1006) @[el2_lsu_bus_buffer.scala 292:91] - reg _T_1008 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 292:54] - _T_1008 <= _T_1007 @[el2_lsu_bus_buffer.scala 292:54] - ibuf_valid <= _T_1008 @[el2_lsu_bus_buffer.scala 292:14] + node _T_1005 = mux(ibuf_wr_en, UInt<1>("h01"), ibuf_valid) @[el2_lsu_bus_buffer.scala 293:58] + node _T_1006 = eq(ibuf_rst, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 293:93] + node _T_1007 = and(_T_1005, _T_1006) @[el2_lsu_bus_buffer.scala 293:91] + reg _T_1008 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 293:54] + _T_1008 <= _T_1007 @[el2_lsu_bus_buffer.scala 293:54] + ibuf_valid <= _T_1008 @[el2_lsu_bus_buffer.scala 293:14] reg _T_1009 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when ibuf_wr_en : @[Reg.scala 28:19] _T_1009 <= ibuf_tag_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ibuf_tag <= _T_1009 @[el2_lsu_bus_buffer.scala 293:12] + ibuf_tag <= _T_1009 @[el2_lsu_bus_buffer.scala 294:12] reg ibuf_dualtag : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when ibuf_wr_en : @[Reg.scala 28:19] ibuf_dualtag <= WrPtr0_r @[Reg.scala 28:23] @@ -1568,16 +1570,16 @@ circuit el2_lsu_bus_intf : when ibuf_wr_en : @[Reg.scala 28:19] _T_1010 <= io.is_sideeffects_r @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ibuf_sideeffect <= _T_1010 @[el2_lsu_bus_buffer.scala 298:19] + ibuf_sideeffect <= _T_1010 @[el2_lsu_bus_buffer.scala 299:19] reg ibuf_unsign : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when ibuf_wr_en : @[Reg.scala 28:19] - ibuf_unsign <= io.lsu_pkt_r.unsign @[Reg.scala 28:23] + ibuf_unsign <= io.lsu_pkt_r.bits.unsign @[Reg.scala 28:23] skip @[Reg.scala 28:19] reg _T_1011 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when ibuf_wr_en : @[Reg.scala 28:19] - _T_1011 <= io.lsu_pkt_r.store @[Reg.scala 28:23] + _T_1011 <= io.lsu_pkt_r.bits.store @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ibuf_write <= _T_1011 @[el2_lsu_bus_buffer.scala 300:14] + ibuf_write <= _T_1011 @[el2_lsu_bus_buffer.scala 301:14] reg ibuf_sz : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when ibuf_wr_en : @[Reg.scala 28:19] ibuf_sz <= ibuf_sz_in @[Reg.scala 28:23] @@ -1590,12 +1592,12 @@ circuit el2_lsu_bus_intf : rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_1012 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_1012 <= ibuf_addr_in @[el2_lib.scala 514:16] - ibuf_addr <= _T_1012 @[el2_lsu_bus_buffer.scala 302:13] + ibuf_addr <= _T_1012 @[el2_lsu_bus_buffer.scala 303:13] reg _T_1013 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when ibuf_wr_en : @[Reg.scala 28:19] _T_1013 <= ibuf_byteen_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ibuf_byteen <= _T_1013 @[el2_lsu_bus_buffer.scala 303:15] + ibuf_byteen <= _T_1013 @[el2_lsu_bus_buffer.scala 304:15] inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 508:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset @@ -1604,38 +1606,38 @@ circuit el2_lsu_bus_intf : rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_1014 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_1014 <= ibuf_data_in @[el2_lib.scala 514:16] - ibuf_data <= _T_1014 @[el2_lsu_bus_buffer.scala 304:13] - reg _T_1015 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 305:55] - _T_1015 <= ibuf_timer_in @[el2_lsu_bus_buffer.scala 305:55] - ibuf_timer <= _T_1015 @[el2_lsu_bus_buffer.scala 305:14] + ibuf_data <= _T_1014 @[el2_lsu_bus_buffer.scala 305:13] + reg _T_1015 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 306:55] + _T_1015 <= ibuf_timer_in @[el2_lsu_bus_buffer.scala 306:55] + ibuf_timer <= _T_1015 @[el2_lsu_bus_buffer.scala 306:14] wire buf_numvld_wrcmd_any : UInt<4> buf_numvld_wrcmd_any <= UInt<1>("h00") wire buf_numvld_cmd_any : UInt<4> buf_numvld_cmd_any <= UInt<1>("h00") wire obuf_wr_timer : UInt<3> obuf_wr_timer <= UInt<1>("h00") - wire buf_nomerge : UInt<1>[4] @[el2_lsu_bus_buffer.scala 309:25] - buf_nomerge[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 310:15] - buf_nomerge[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 310:15] - buf_nomerge[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 310:15] - buf_nomerge[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 310:15] + wire buf_nomerge : UInt<1>[4] @[el2_lsu_bus_buffer.scala 310:25] + buf_nomerge[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 311:15] + buf_nomerge[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 311:15] + buf_nomerge[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 311:15] + buf_nomerge[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 311:15] wire buf_sideeffect : UInt<4> buf_sideeffect <= UInt<1>("h00") wire obuf_force_wr_en : UInt<1> obuf_force_wr_en <= UInt<1>("h00") wire obuf_wr_en : UInt<1> obuf_wr_en <= UInt<1>("h00") - node _T_1016 = eq(buf_numvld_wrcmd_any, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 315:43] - node _T_1017 = eq(buf_numvld_cmd_any, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 315:72] - node _T_1018 = and(_T_1016, _T_1017) @[el2_lsu_bus_buffer.scala 315:51] - node _T_1019 = neq(obuf_wr_timer, UInt<3>("h07")) @[el2_lsu_bus_buffer.scala 315:97] - node _T_1020 = and(_T_1018, _T_1019) @[el2_lsu_bus_buffer.scala 315:80] - node _T_1021 = eq(bus_coalescing_disable, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 316:5] - node _T_1022 = and(_T_1020, _T_1021) @[el2_lsu_bus_buffer.scala 315:114] - node _T_1023 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 316:114] - node _T_1024 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 316:114] - node _T_1025 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 316:114] - node _T_1026 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 316:114] + node _T_1016 = eq(buf_numvld_wrcmd_any, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 316:43] + node _T_1017 = eq(buf_numvld_cmd_any, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 316:72] + node _T_1018 = and(_T_1016, _T_1017) @[el2_lsu_bus_buffer.scala 316:51] + node _T_1019 = neq(obuf_wr_timer, UInt<3>("h07")) @[el2_lsu_bus_buffer.scala 316:97] + node _T_1020 = and(_T_1018, _T_1019) @[el2_lsu_bus_buffer.scala 316:80] + node _T_1021 = eq(bus_coalescing_disable, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 317:5] + node _T_1022 = and(_T_1020, _T_1021) @[el2_lsu_bus_buffer.scala 316:114] + node _T_1023 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 317:114] + node _T_1024 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 317:114] + node _T_1025 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 317:114] + node _T_1026 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 317:114] node _T_1027 = mux(_T_1023, buf_nomerge[0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1028 = mux(_T_1024, buf_nomerge[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1029 = mux(_T_1025, buf_nomerge[2], UInt<1>("h00")) @[Mux.scala 27:72] @@ -1645,16 +1647,16 @@ circuit el2_lsu_bus_intf : node _T_1033 = or(_T_1032, _T_1030) @[Mux.scala 27:72] wire _T_1034 : UInt<1> @[Mux.scala 27:72] _T_1034 <= _T_1033 @[Mux.scala 27:72] - node _T_1035 = eq(_T_1034, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 316:31] - node _T_1036 = and(_T_1022, _T_1035) @[el2_lsu_bus_buffer.scala 316:29] - node _T_1037 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 317:88] - node _T_1038 = bits(buf_sideeffect, 0, 0) @[el2_lsu_bus_buffer.scala 317:111] - node _T_1039 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 317:88] - node _T_1040 = bits(buf_sideeffect, 1, 1) @[el2_lsu_bus_buffer.scala 317:111] - node _T_1041 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 317:88] - node _T_1042 = bits(buf_sideeffect, 2, 2) @[el2_lsu_bus_buffer.scala 317:111] - node _T_1043 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 317:88] - node _T_1044 = bits(buf_sideeffect, 3, 3) @[el2_lsu_bus_buffer.scala 317:111] + node _T_1035 = eq(_T_1034, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 317:31] + node _T_1036 = and(_T_1022, _T_1035) @[el2_lsu_bus_buffer.scala 317:29] + node _T_1037 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 318:88] + node _T_1038 = bits(buf_sideeffect, 0, 0) @[el2_lsu_bus_buffer.scala 318:111] + node _T_1039 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 318:88] + node _T_1040 = bits(buf_sideeffect, 1, 1) @[el2_lsu_bus_buffer.scala 318:111] + node _T_1041 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 318:88] + node _T_1042 = bits(buf_sideeffect, 2, 2) @[el2_lsu_bus_buffer.scala 318:111] + node _T_1043 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 318:88] + node _T_1044 = bits(buf_sideeffect, 3, 3) @[el2_lsu_bus_buffer.scala 318:111] node _T_1045 = mux(_T_1037, _T_1038, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1046 = mux(_T_1039, _T_1040, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1047 = mux(_T_1041, _T_1042, UInt<1>("h00")) @[Mux.scala 27:72] @@ -1664,32 +1666,32 @@ circuit el2_lsu_bus_intf : node _T_1051 = or(_T_1050, _T_1048) @[Mux.scala 27:72] wire _T_1052 : UInt<1> @[Mux.scala 27:72] _T_1052 <= _T_1051 @[Mux.scala 27:72] - node _T_1053 = eq(_T_1052, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 317:5] - node _T_1054 = and(_T_1036, _T_1053) @[el2_lsu_bus_buffer.scala 316:140] - node _T_1055 = eq(obuf_force_wr_en, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 317:119] - node obuf_wr_wait = and(_T_1054, _T_1055) @[el2_lsu_bus_buffer.scala 317:117] - node _T_1056 = orr(buf_numvld_cmd_any) @[el2_lsu_bus_buffer.scala 318:75] - node _T_1057 = lt(obuf_wr_timer, UInt<3>("h07")) @[el2_lsu_bus_buffer.scala 318:95] - node _T_1058 = and(_T_1056, _T_1057) @[el2_lsu_bus_buffer.scala 318:79] - node _T_1059 = add(obuf_wr_timer, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 318:123] - node _T_1060 = tail(_T_1059, 1) @[el2_lsu_bus_buffer.scala 318:123] - node _T_1061 = mux(_T_1058, _T_1060, obuf_wr_timer) @[el2_lsu_bus_buffer.scala 318:55] - node obuf_wr_timer_in = mux(obuf_wr_en, UInt<3>("h00"), _T_1061) @[el2_lsu_bus_buffer.scala 318:29] - node _T_1062 = eq(io.lsu_busreq_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 319:41] - node _T_1063 = and(io.lsu_busreq_m, _T_1062) @[el2_lsu_bus_buffer.scala 319:39] - node _T_1064 = eq(ibuf_valid, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 319:60] - node _T_1065 = and(_T_1063, _T_1064) @[el2_lsu_bus_buffer.scala 319:58] - node _T_1066 = eq(buf_numvld_cmd_any, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 319:93] - node _T_1067 = and(_T_1065, _T_1066) @[el2_lsu_bus_buffer.scala 319:72] - node _T_1068 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 319:117] - node _T_1069 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 319:208] - node _T_1070 = bits(buf_addr[0], 31, 2) @[el2_lsu_bus_buffer.scala 319:228] - node _T_1071 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 319:208] - node _T_1072 = bits(buf_addr[1], 31, 2) @[el2_lsu_bus_buffer.scala 319:228] - node _T_1073 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 319:208] - node _T_1074 = bits(buf_addr[2], 31, 2) @[el2_lsu_bus_buffer.scala 319:228] - node _T_1075 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 319:208] - node _T_1076 = bits(buf_addr[3], 31, 2) @[el2_lsu_bus_buffer.scala 319:228] + node _T_1053 = eq(_T_1052, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 318:5] + node _T_1054 = and(_T_1036, _T_1053) @[el2_lsu_bus_buffer.scala 317:140] + node _T_1055 = eq(obuf_force_wr_en, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 318:119] + node obuf_wr_wait = and(_T_1054, _T_1055) @[el2_lsu_bus_buffer.scala 318:117] + node _T_1056 = orr(buf_numvld_cmd_any) @[el2_lsu_bus_buffer.scala 319:75] + node _T_1057 = lt(obuf_wr_timer, UInt<3>("h07")) @[el2_lsu_bus_buffer.scala 319:95] + node _T_1058 = and(_T_1056, _T_1057) @[el2_lsu_bus_buffer.scala 319:79] + node _T_1059 = add(obuf_wr_timer, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 319:123] + node _T_1060 = tail(_T_1059, 1) @[el2_lsu_bus_buffer.scala 319:123] + node _T_1061 = mux(_T_1058, _T_1060, obuf_wr_timer) @[el2_lsu_bus_buffer.scala 319:55] + node obuf_wr_timer_in = mux(obuf_wr_en, UInt<3>("h00"), _T_1061) @[el2_lsu_bus_buffer.scala 319:29] + node _T_1062 = eq(io.lsu_busreq_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 320:41] + node _T_1063 = and(io.lsu_busreq_m, _T_1062) @[el2_lsu_bus_buffer.scala 320:39] + node _T_1064 = eq(ibuf_valid, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 320:60] + node _T_1065 = and(_T_1063, _T_1064) @[el2_lsu_bus_buffer.scala 320:58] + node _T_1066 = eq(buf_numvld_cmd_any, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 320:93] + node _T_1067 = and(_T_1065, _T_1066) @[el2_lsu_bus_buffer.scala 320:72] + node _T_1068 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 320:117] + node _T_1069 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 320:208] + node _T_1070 = bits(buf_addr[0], 31, 2) @[el2_lsu_bus_buffer.scala 320:228] + node _T_1071 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 320:208] + node _T_1072 = bits(buf_addr[1], 31, 2) @[el2_lsu_bus_buffer.scala 320:228] + node _T_1073 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 320:208] + node _T_1074 = bits(buf_addr[2], 31, 2) @[el2_lsu_bus_buffer.scala 320:228] + node _T_1075 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 320:208] + node _T_1076 = bits(buf_addr[3], 31, 2) @[el2_lsu_bus_buffer.scala 320:228] node _T_1077 = mux(_T_1069, _T_1070, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1078 = mux(_T_1071, _T_1072, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1079 = mux(_T_1073, _T_1074, UInt<1>("h00")) @[Mux.scala 27:72] @@ -1699,35 +1701,35 @@ circuit el2_lsu_bus_intf : node _T_1083 = or(_T_1082, _T_1080) @[Mux.scala 27:72] wire _T_1084 : UInt<30> @[Mux.scala 27:72] _T_1084 <= _T_1083 @[Mux.scala 27:72] - node _T_1085 = neq(_T_1068, _T_1084) @[el2_lsu_bus_buffer.scala 319:123] - node _T_1086 = and(_T_1067, _T_1085) @[el2_lsu_bus_buffer.scala 319:101] - obuf_force_wr_en <= _T_1086 @[el2_lsu_bus_buffer.scala 319:20] + node _T_1085 = neq(_T_1068, _T_1084) @[el2_lsu_bus_buffer.scala 320:123] + node _T_1086 = and(_T_1067, _T_1085) @[el2_lsu_bus_buffer.scala 320:101] + obuf_force_wr_en <= _T_1086 @[el2_lsu_bus_buffer.scala 320:20] wire buf_numvld_pend_any : UInt<4> buf_numvld_pend_any <= UInt<1>("h00") - node _T_1087 = eq(buf_numvld_pend_any, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 321:53] - node _T_1088 = and(ibuf_byp, _T_1087) @[el2_lsu_bus_buffer.scala 321:31] - node _T_1089 = eq(io.lsu_pkt_r.store, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 321:64] - node _T_1090 = or(_T_1089, io.no_dword_merge_r) @[el2_lsu_bus_buffer.scala 321:84] - node ibuf_buf_byp = and(_T_1088, _T_1090) @[el2_lsu_bus_buffer.scala 321:61] + node _T_1087 = eq(buf_numvld_pend_any, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 322:53] + node _T_1088 = and(ibuf_byp, _T_1087) @[el2_lsu_bus_buffer.scala 322:31] + node _T_1089 = eq(io.lsu_pkt_r.bits.store, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 322:64] + node _T_1090 = or(_T_1089, io.no_dword_merge_r) @[el2_lsu_bus_buffer.scala 322:89] + node ibuf_buf_byp = and(_T_1088, _T_1090) @[el2_lsu_bus_buffer.scala 322:61] wire bus_sideeffect_pend : UInt<1> bus_sideeffect_pend <= UInt<1>("h00") wire found_cmdptr0 : UInt<1> found_cmdptr0 <= UInt<1>("h00") - wire buf_cmd_state_bus_en : UInt<1>[4] @[el2_lsu_bus_buffer.scala 324:34] - buf_cmd_state_bus_en[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 325:24] - buf_cmd_state_bus_en[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 325:24] - buf_cmd_state_bus_en[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 325:24] - buf_cmd_state_bus_en[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 325:24] - wire buf_dual : UInt<1>[4] @[el2_lsu_bus_buffer.scala 326:22] - buf_dual[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 327:12] - buf_dual[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 327:12] - buf_dual[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 327:12] - buf_dual[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 327:12] - wire buf_samedw : UInt<1>[4] @[el2_lsu_bus_buffer.scala 328:24] - buf_samedw[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 329:14] - buf_samedw[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 329:14] - buf_samedw[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 329:14] - buf_samedw[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 329:14] + wire buf_cmd_state_bus_en : UInt<1>[4] @[el2_lsu_bus_buffer.scala 325:34] + buf_cmd_state_bus_en[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 326:24] + buf_cmd_state_bus_en[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 326:24] + buf_cmd_state_bus_en[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 326:24] + buf_cmd_state_bus_en[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 326:24] + wire buf_dual : UInt<1>[4] @[el2_lsu_bus_buffer.scala 327:22] + buf_dual[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 328:12] + buf_dual[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 328:12] + buf_dual[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 328:12] + buf_dual[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 328:12] + wire buf_samedw : UInt<1>[4] @[el2_lsu_bus_buffer.scala 329:24] + buf_samedw[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 330:14] + buf_samedw[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 330:14] + buf_samedw[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 330:14] + buf_samedw[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 330:14] wire found_cmdptr1 : UInt<1> found_cmdptr1 <= UInt<1>("h00") wire bus_cmd_ready : UInt<1> @@ -1740,10 +1742,10 @@ circuit el2_lsu_bus_intf : lsu_bus_cntr_overflow <= UInt<1>("h00") wire bus_addr_match_pending : UInt<1> bus_addr_match_pending <= UInt<1>("h00") - node _T_1091 = and(ibuf_buf_byp, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 336:32] - node _T_1092 = and(io.is_sideeffects_r, bus_sideeffect_pend) @[el2_lsu_bus_buffer.scala 336:74] - node _T_1093 = eq(_T_1092, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 336:52] - node _T_1094 = and(_T_1091, _T_1093) @[el2_lsu_bus_buffer.scala 336:50] + node _T_1091 = and(ibuf_buf_byp, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 337:32] + node _T_1092 = and(io.is_sideeffects_r, bus_sideeffect_pend) @[el2_lsu_bus_buffer.scala 337:74] + node _T_1093 = eq(_T_1092, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 337:52] + node _T_1094 = and(_T_1091, _T_1093) @[el2_lsu_bus_buffer.scala 337:50] node _T_1095 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] node _T_1096 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] node _T_1097 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] @@ -1757,8 +1759,8 @@ circuit el2_lsu_bus_intf : node _T_1105 = or(_T_1104, _T_1102) @[Mux.scala 27:72] wire _T_1106 : UInt<3> @[Mux.scala 27:72] _T_1106 <= _T_1105 @[Mux.scala 27:72] - node _T_1107 = eq(_T_1106, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 337:36] - node _T_1108 = and(_T_1107, found_cmdptr0) @[el2_lsu_bus_buffer.scala 337:47] + node _T_1107 = eq(_T_1106, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 338:36] + node _T_1108 = and(_T_1107, found_cmdptr0) @[el2_lsu_bus_buffer.scala 338:47] node _T_1109 = cat(buf_cmd_state_bus_en[3], buf_cmd_state_bus_en[2]) @[Cat.scala 29:58] node _T_1110 = cat(_T_1109, buf_cmd_state_bus_en[1]) @[Cat.scala 29:58] node _T_1111 = cat(_T_1110, buf_cmd_state_bus_en[0]) @[Cat.scala 29:58] @@ -1779,8 +1781,8 @@ circuit el2_lsu_bus_intf : node _T_1126 = or(_T_1125, _T_1123) @[Mux.scala 27:72] wire _T_1127 : UInt<1> @[Mux.scala 27:72] _T_1127 <= _T_1126 @[Mux.scala 27:72] - node _T_1128 = eq(_T_1127, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 338:23] - node _T_1129 = and(_T_1108, _T_1128) @[el2_lsu_bus_buffer.scala 338:21] + node _T_1128 = eq(_T_1127, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 339:23] + node _T_1129 = and(_T_1108, _T_1128) @[el2_lsu_bus_buffer.scala 339:21] node _T_1130 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] node _T_1131 = bits(buf_sideeffect, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] node _T_1132 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] @@ -1798,9 +1800,9 @@ circuit el2_lsu_bus_intf : node _T_1144 = or(_T_1143, _T_1141) @[Mux.scala 27:72] wire _T_1145 : UInt<1> @[Mux.scala 27:72] _T_1145 <= _T_1144 @[Mux.scala 27:72] - node _T_1146 = and(_T_1145, bus_sideeffect_pend) @[el2_lsu_bus_buffer.scala 338:141] - node _T_1147 = eq(_T_1146, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 338:105] - node _T_1148 = and(_T_1129, _T_1147) @[el2_lsu_bus_buffer.scala 338:103] + node _T_1146 = and(_T_1145, bus_sideeffect_pend) @[el2_lsu_bus_buffer.scala 339:141] + node _T_1147 = eq(_T_1146, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 339:105] + node _T_1148 = and(_T_1129, _T_1147) @[el2_lsu_bus_buffer.scala 339:103] node _T_1149 = cat(buf_dual[3], buf_dual[2]) @[Cat.scala 29:58] node _T_1150 = cat(_T_1149, buf_dual[1]) @[Cat.scala 29:58] node _T_1151 = cat(_T_1150, buf_dual[0]) @[Cat.scala 29:58] @@ -1841,7 +1843,7 @@ circuit el2_lsu_bus_intf : node _T_1185 = or(_T_1184, _T_1182) @[Mux.scala 27:72] wire _T_1186 : UInt<1> @[Mux.scala 27:72] _T_1186 <= _T_1185 @[Mux.scala 27:72] - node _T_1187 = and(_T_1167, _T_1186) @[el2_lsu_bus_buffer.scala 339:77] + node _T_1187 = and(_T_1167, _T_1186) @[el2_lsu_bus_buffer.scala 340:77] node _T_1188 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] node _T_1189 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] node _T_1190 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] @@ -1859,10 +1861,10 @@ circuit el2_lsu_bus_intf : node _T_1202 = or(_T_1201, _T_1199) @[Mux.scala 27:72] wire _T_1203 : UInt<1> @[Mux.scala 27:72] _T_1203 <= _T_1202 @[Mux.scala 27:72] - node _T_1204 = eq(_T_1203, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 339:150] - node _T_1205 = and(_T_1187, _T_1204) @[el2_lsu_bus_buffer.scala 339:148] - node _T_1206 = eq(_T_1205, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 339:8] - node _T_1207 = or(_T_1206, found_cmdptr1) @[el2_lsu_bus_buffer.scala 339:181] + node _T_1204 = eq(_T_1203, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 340:150] + node _T_1205 = and(_T_1187, _T_1204) @[el2_lsu_bus_buffer.scala 340:148] + node _T_1206 = eq(_T_1205, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 340:8] + node _T_1207 = or(_T_1206, found_cmdptr1) @[el2_lsu_bus_buffer.scala 340:181] node _T_1208 = cat(buf_nomerge[3], buf_nomerge[2]) @[Cat.scala 29:58] node _T_1209 = cat(_T_1208, buf_nomerge[1]) @[Cat.scala 29:58] node _T_1210 = cat(_T_1209, buf_nomerge[0]) @[Cat.scala 29:58] @@ -1883,30 +1885,30 @@ circuit el2_lsu_bus_intf : node _T_1225 = or(_T_1224, _T_1222) @[Mux.scala 27:72] wire _T_1226 : UInt<1> @[Mux.scala 27:72] _T_1226 <= _T_1225 @[Mux.scala 27:72] - node _T_1227 = or(_T_1207, _T_1226) @[el2_lsu_bus_buffer.scala 339:197] - node _T_1228 = or(_T_1227, obuf_force_wr_en) @[el2_lsu_bus_buffer.scala 339:269] - node _T_1229 = and(_T_1148, _T_1228) @[el2_lsu_bus_buffer.scala 338:164] - node _T_1230 = or(_T_1094, _T_1229) @[el2_lsu_bus_buffer.scala 336:98] - node _T_1231 = eq(obuf_valid, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 340:48] - node _T_1232 = or(bus_cmd_ready, _T_1231) @[el2_lsu_bus_buffer.scala 340:46] - node _T_1233 = or(_T_1232, obuf_nosend) @[el2_lsu_bus_buffer.scala 340:60] - node _T_1234 = and(_T_1230, _T_1233) @[el2_lsu_bus_buffer.scala 340:29] - node _T_1235 = eq(obuf_wr_wait, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 340:77] - node _T_1236 = and(_T_1234, _T_1235) @[el2_lsu_bus_buffer.scala 340:75] - node _T_1237 = eq(lsu_bus_cntr_overflow, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 340:93] - node _T_1238 = and(_T_1236, _T_1237) @[el2_lsu_bus_buffer.scala 340:91] - node _T_1239 = eq(bus_addr_match_pending, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 340:118] - node _T_1240 = and(_T_1238, _T_1239) @[el2_lsu_bus_buffer.scala 340:116] - node _T_1241 = and(_T_1240, io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 340:142] - obuf_wr_en <= _T_1241 @[el2_lsu_bus_buffer.scala 336:14] + node _T_1227 = or(_T_1207, _T_1226) @[el2_lsu_bus_buffer.scala 340:197] + node _T_1228 = or(_T_1227, obuf_force_wr_en) @[el2_lsu_bus_buffer.scala 340:269] + node _T_1229 = and(_T_1148, _T_1228) @[el2_lsu_bus_buffer.scala 339:164] + node _T_1230 = or(_T_1094, _T_1229) @[el2_lsu_bus_buffer.scala 337:98] + node _T_1231 = eq(obuf_valid, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 341:48] + node _T_1232 = or(bus_cmd_ready, _T_1231) @[el2_lsu_bus_buffer.scala 341:46] + node _T_1233 = or(_T_1232, obuf_nosend) @[el2_lsu_bus_buffer.scala 341:60] + node _T_1234 = and(_T_1230, _T_1233) @[el2_lsu_bus_buffer.scala 341:29] + node _T_1235 = eq(obuf_wr_wait, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 341:77] + node _T_1236 = and(_T_1234, _T_1235) @[el2_lsu_bus_buffer.scala 341:75] + node _T_1237 = eq(lsu_bus_cntr_overflow, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 341:93] + node _T_1238 = and(_T_1236, _T_1237) @[el2_lsu_bus_buffer.scala 341:91] + node _T_1239 = eq(bus_addr_match_pending, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 341:118] + node _T_1240 = and(_T_1238, _T_1239) @[el2_lsu_bus_buffer.scala 341:116] + node _T_1241 = and(_T_1240, io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 341:142] + obuf_wr_en <= _T_1241 @[el2_lsu_bus_buffer.scala 337:14] wire bus_cmd_sent : UInt<1> bus_cmd_sent <= UInt<1>("h00") - node _T_1242 = and(obuf_valid, obuf_nosend) @[el2_lsu_bus_buffer.scala 342:47] - node _T_1243 = or(bus_cmd_sent, _T_1242) @[el2_lsu_bus_buffer.scala 342:33] - node _T_1244 = eq(obuf_wr_en, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 342:65] - node _T_1245 = and(_T_1243, _T_1244) @[el2_lsu_bus_buffer.scala 342:63] - node _T_1246 = and(_T_1245, io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 342:77] - node obuf_rst = or(_T_1246, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 342:98] + node _T_1242 = and(obuf_valid, obuf_nosend) @[el2_lsu_bus_buffer.scala 343:47] + node _T_1243 = or(bus_cmd_sent, _T_1242) @[el2_lsu_bus_buffer.scala 343:33] + node _T_1244 = eq(obuf_wr_en, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 343:65] + node _T_1245 = and(_T_1243, _T_1244) @[el2_lsu_bus_buffer.scala 343:63] + node _T_1246 = and(_T_1245, io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 343:77] + node obuf_rst = or(_T_1246, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 343:98] node _T_1247 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] node _T_1248 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] node _T_1249 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] @@ -1924,7 +1926,7 @@ circuit el2_lsu_bus_intf : node _T_1261 = or(_T_1260, _T_1258) @[Mux.scala 27:72] wire _T_1262 : UInt<1> @[Mux.scala 27:72] _T_1262 <= _T_1261 @[Mux.scala 27:72] - node obuf_write_in = mux(ibuf_buf_byp, io.lsu_pkt_r.store, _T_1262) @[el2_lsu_bus_buffer.scala 343:26] + node obuf_write_in = mux(ibuf_buf_byp, io.lsu_pkt_r.bits.store, _T_1262) @[el2_lsu_bus_buffer.scala 344:26] node _T_1263 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] node _T_1264 = bits(buf_sideeffect, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] node _T_1265 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] @@ -1942,7 +1944,7 @@ circuit el2_lsu_bus_intf : node _T_1277 = or(_T_1276, _T_1274) @[Mux.scala 27:72] wire _T_1278 : UInt<1> @[Mux.scala 27:72] _T_1278 <= _T_1277 @[Mux.scala 27:72] - node obuf_sideeffect_in = mux(ibuf_buf_byp, io.is_sideeffects_r, _T_1278) @[el2_lsu_bus_buffer.scala 344:31] + node obuf_sideeffect_in = mux(ibuf_buf_byp, io.is_sideeffects_r, _T_1278) @[el2_lsu_bus_buffer.scala 345:31] node _T_1279 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] node _T_1280 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] node _T_1281 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] @@ -1956,13 +1958,13 @@ circuit el2_lsu_bus_intf : node _T_1289 = or(_T_1288, _T_1286) @[Mux.scala 27:72] wire _T_1290 : UInt<32> @[Mux.scala 27:72] _T_1290 <= _T_1289 @[Mux.scala 27:72] - node obuf_addr_in = mux(ibuf_buf_byp, io.lsu_addr_r, _T_1290) @[el2_lsu_bus_buffer.scala 345:25] - wire buf_sz : UInt<2>[4] @[el2_lsu_bus_buffer.scala 346:20] - buf_sz[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 347:10] - buf_sz[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 347:10] - buf_sz[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 347:10] - buf_sz[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 347:10] - node _T_1291 = cat(io.lsu_pkt_r.word, io.lsu_pkt_r.half) @[Cat.scala 29:58] + node obuf_addr_in = mux(ibuf_buf_byp, io.lsu_addr_r, _T_1290) @[el2_lsu_bus_buffer.scala 346:25] + wire buf_sz : UInt<2>[4] @[el2_lsu_bus_buffer.scala 347:20] + buf_sz[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 348:10] + buf_sz[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 348:10] + buf_sz[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 348:10] + buf_sz[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 348:10] + node _T_1291 = cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) @[Cat.scala 29:58] node _T_1292 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] node _T_1293 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] node _T_1294 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] @@ -1976,43 +1978,41 @@ circuit el2_lsu_bus_intf : node _T_1302 = or(_T_1301, _T_1299) @[Mux.scala 27:72] wire _T_1303 : UInt<2> @[Mux.scala 27:72] _T_1303 <= _T_1302 @[Mux.scala 27:72] - node obuf_sz_in = mux(ibuf_buf_byp, _T_1291, _T_1303) @[el2_lsu_bus_buffer.scala 348:23] + node obuf_sz_in = mux(ibuf_buf_byp, _T_1291, _T_1303) @[el2_lsu_bus_buffer.scala 349:23] wire obuf_merge_en : UInt<1> obuf_merge_en <= UInt<1>("h00") - node obuf_tag0_in = mux(ibuf_buf_byp, WrPtr0_r, CmdPtr0) @[el2_lsu_bus_buffer.scala 351:25] - wire Cmdptr1 : UInt<2> - Cmdptr1 <= UInt<1>("h00") - node obuf_tag1_in = mux(ibuf_buf_byp, WrPtr1_r, Cmdptr1) @[el2_lsu_bus_buffer.scala 354:25] + node obuf_tag0_in = mux(ibuf_buf_byp, WrPtr0_r, CmdPtr0) @[el2_lsu_bus_buffer.scala 352:25] + node obuf_tag1_in = mux(ibuf_buf_byp, WrPtr1_r, CmdPtr1) @[el2_lsu_bus_buffer.scala 355:25] wire obuf_cmd_done : UInt<1> obuf_cmd_done <= UInt<1>("h00") wire bus_wcmd_sent : UInt<1> bus_wcmd_sent <= UInt<1>("h00") - node _T_1304 = or(obuf_wr_en, obuf_rst) @[el2_lsu_bus_buffer.scala 357:39] - node _T_1305 = eq(_T_1304, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 357:26] - node _T_1306 = or(obuf_cmd_done, bus_wcmd_sent) @[el2_lsu_bus_buffer.scala 357:68] - node obuf_cmd_done_in = and(_T_1305, _T_1306) @[el2_lsu_bus_buffer.scala 357:51] + node _T_1304 = or(obuf_wr_en, obuf_rst) @[el2_lsu_bus_buffer.scala 358:39] + node _T_1305 = eq(_T_1304, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 358:26] + node _T_1306 = or(obuf_cmd_done, bus_wcmd_sent) @[el2_lsu_bus_buffer.scala 358:68] + node obuf_cmd_done_in = and(_T_1305, _T_1306) @[el2_lsu_bus_buffer.scala 358:51] wire obuf_data_done : UInt<1> obuf_data_done <= UInt<1>("h00") wire bus_wdata_sent : UInt<1> bus_wdata_sent <= UInt<1>("h00") - node _T_1307 = or(obuf_wr_en, obuf_rst) @[el2_lsu_bus_buffer.scala 360:40] - node _T_1308 = eq(_T_1307, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 360:27] - node _T_1309 = or(obuf_data_done, bus_wdata_sent) @[el2_lsu_bus_buffer.scala 360:70] - node obuf_data_done_in = and(_T_1308, _T_1309) @[el2_lsu_bus_buffer.scala 360:52] - node _T_1310 = bits(obuf_sz_in, 1, 0) @[el2_lsu_bus_buffer.scala 361:67] - node _T_1311 = eq(_T_1310, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 361:72] - node _T_1312 = bits(obuf_sz_in, 0, 0) @[el2_lsu_bus_buffer.scala 361:92] - node _T_1313 = bits(obuf_addr_in, 0, 0) @[el2_lsu_bus_buffer.scala 361:111] - node _T_1314 = eq(_T_1313, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 361:98] - node _T_1315 = and(_T_1312, _T_1314) @[el2_lsu_bus_buffer.scala 361:96] - node _T_1316 = or(_T_1311, _T_1315) @[el2_lsu_bus_buffer.scala 361:79] - node _T_1317 = bits(obuf_sz_in, 1, 1) @[el2_lsu_bus_buffer.scala 361:129] - node _T_1318 = bits(obuf_addr_in, 1, 0) @[el2_lsu_bus_buffer.scala 361:147] - node _T_1319 = orr(_T_1318) @[el2_lsu_bus_buffer.scala 361:153] - node _T_1320 = eq(_T_1319, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 361:134] - node _T_1321 = and(_T_1317, _T_1320) @[el2_lsu_bus_buffer.scala 361:132] - node _T_1322 = or(_T_1316, _T_1321) @[el2_lsu_bus_buffer.scala 361:116] - node obuf_aligned_in = mux(ibuf_buf_byp, is_aligned_r, _T_1322) @[el2_lsu_bus_buffer.scala 361:28] + node _T_1307 = or(obuf_wr_en, obuf_rst) @[el2_lsu_bus_buffer.scala 361:40] + node _T_1308 = eq(_T_1307, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 361:27] + node _T_1309 = or(obuf_data_done, bus_wdata_sent) @[el2_lsu_bus_buffer.scala 361:70] + node obuf_data_done_in = and(_T_1308, _T_1309) @[el2_lsu_bus_buffer.scala 361:52] + node _T_1310 = bits(obuf_sz_in, 1, 0) @[el2_lsu_bus_buffer.scala 362:67] + node _T_1311 = eq(_T_1310, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 362:72] + node _T_1312 = bits(obuf_sz_in, 0, 0) @[el2_lsu_bus_buffer.scala 362:92] + node _T_1313 = bits(obuf_addr_in, 0, 0) @[el2_lsu_bus_buffer.scala 362:111] + node _T_1314 = eq(_T_1313, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 362:98] + node _T_1315 = and(_T_1312, _T_1314) @[el2_lsu_bus_buffer.scala 362:96] + node _T_1316 = or(_T_1311, _T_1315) @[el2_lsu_bus_buffer.scala 362:79] + node _T_1317 = bits(obuf_sz_in, 1, 1) @[el2_lsu_bus_buffer.scala 362:129] + node _T_1318 = bits(obuf_addr_in, 1, 0) @[el2_lsu_bus_buffer.scala 362:147] + node _T_1319 = orr(_T_1318) @[el2_lsu_bus_buffer.scala 362:153] + node _T_1320 = eq(_T_1319, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 362:134] + node _T_1321 = and(_T_1317, _T_1320) @[el2_lsu_bus_buffer.scala 362:132] + node _T_1322 = or(_T_1316, _T_1321) @[el2_lsu_bus_buffer.scala 362:116] + node obuf_aligned_in = mux(ibuf_buf_byp, is_aligned_r, _T_1322) @[el2_lsu_bus_buffer.scala 362:28] wire obuf_nosend_in : UInt<1> obuf_nosend_in <= UInt<1>("h00") wire obuf_rdrsp_pend : UInt<1> @@ -2025,53 +2025,53 @@ circuit el2_lsu_bus_intf : obuf_rdrsp_tag <= UInt<1>("h00") wire obuf_write : UInt<1> obuf_write <= UInt<1>("h00") - node _T_1323 = eq(obuf_nosend_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 369:44] - node _T_1324 = and(obuf_wr_en, _T_1323) @[el2_lsu_bus_buffer.scala 369:42] - node _T_1325 = eq(_T_1324, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 369:29] - node _T_1326 = and(_T_1325, obuf_rdrsp_pend) @[el2_lsu_bus_buffer.scala 369:61] - node _T_1327 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[el2_lsu_bus_buffer.scala 369:116] - node _T_1328 = and(bus_rsp_read, _T_1327) @[el2_lsu_bus_buffer.scala 369:96] - node _T_1329 = eq(_T_1328, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 369:81] - node _T_1330 = and(_T_1326, _T_1329) @[el2_lsu_bus_buffer.scala 369:79] - node _T_1331 = eq(obuf_write, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 370:22] - node _T_1332 = and(bus_cmd_sent, _T_1331) @[el2_lsu_bus_buffer.scala 370:20] - node _T_1333 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 370:37] - node _T_1334 = and(_T_1332, _T_1333) @[el2_lsu_bus_buffer.scala 370:35] - node obuf_rdrsp_pend_in = or(_T_1330, _T_1334) @[el2_lsu_bus_buffer.scala 369:138] + node _T_1323 = eq(obuf_nosend_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 370:44] + node _T_1324 = and(obuf_wr_en, _T_1323) @[el2_lsu_bus_buffer.scala 370:42] + node _T_1325 = eq(_T_1324, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 370:29] + node _T_1326 = and(_T_1325, obuf_rdrsp_pend) @[el2_lsu_bus_buffer.scala 370:61] + node _T_1327 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[el2_lsu_bus_buffer.scala 370:116] + node _T_1328 = and(bus_rsp_read, _T_1327) @[el2_lsu_bus_buffer.scala 370:96] + node _T_1329 = eq(_T_1328, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 370:81] + node _T_1330 = and(_T_1326, _T_1329) @[el2_lsu_bus_buffer.scala 370:79] + node _T_1331 = eq(obuf_write, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 371:22] + node _T_1332 = and(bus_cmd_sent, _T_1331) @[el2_lsu_bus_buffer.scala 371:20] + node _T_1333 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 371:37] + node _T_1334 = and(_T_1332, _T_1333) @[el2_lsu_bus_buffer.scala 371:35] + node obuf_rdrsp_pend_in = or(_T_1330, _T_1334) @[el2_lsu_bus_buffer.scala 370:138] wire obuf_tag0 : UInt<3> obuf_tag0 <= UInt<1>("h00") - node _T_1335 = eq(obuf_write, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 372:46] - node _T_1336 = and(bus_cmd_sent, _T_1335) @[el2_lsu_bus_buffer.scala 372:44] - node obuf_rdrsp_tag_in = mux(_T_1336, obuf_tag0, obuf_rdrsp_tag) @[el2_lsu_bus_buffer.scala 372:30] + node _T_1335 = eq(obuf_write, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 373:46] + node _T_1336 = and(bus_cmd_sent, _T_1335) @[el2_lsu_bus_buffer.scala 373:44] + node obuf_rdrsp_tag_in = mux(_T_1336, obuf_tag0, obuf_rdrsp_tag) @[el2_lsu_bus_buffer.scala 373:30] wire obuf_addr : UInt<32> obuf_addr <= UInt<1>("h00") wire obuf_sideeffect : UInt<1> obuf_sideeffect <= UInt<1>("h00") - node _T_1337 = bits(obuf_addr_in, 31, 3) @[el2_lsu_bus_buffer.scala 375:34] - node _T_1338 = bits(obuf_addr, 31, 3) @[el2_lsu_bus_buffer.scala 375:52] - node _T_1339 = eq(_T_1337, _T_1338) @[el2_lsu_bus_buffer.scala 375:40] - node _T_1340 = and(_T_1339, obuf_aligned_in) @[el2_lsu_bus_buffer.scala 375:60] - node _T_1341 = eq(obuf_sideeffect, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 375:80] - node _T_1342 = and(_T_1340, _T_1341) @[el2_lsu_bus_buffer.scala 375:78] - node _T_1343 = eq(obuf_write, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 375:99] - node _T_1344 = and(_T_1342, _T_1343) @[el2_lsu_bus_buffer.scala 375:97] - node _T_1345 = eq(obuf_write_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 375:113] - node _T_1346 = and(_T_1344, _T_1345) @[el2_lsu_bus_buffer.scala 375:111] - node _T_1347 = eq(io.dec_tlu_external_ldfwd_disable, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 375:130] - node _T_1348 = and(_T_1346, _T_1347) @[el2_lsu_bus_buffer.scala 375:128] - node _T_1349 = eq(obuf_nosend, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 376:20] - node _T_1350 = and(obuf_valid, _T_1349) @[el2_lsu_bus_buffer.scala 376:18] - node _T_1351 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[el2_lsu_bus_buffer.scala 376:90] - node _T_1352 = and(bus_rsp_read, _T_1351) @[el2_lsu_bus_buffer.scala 376:70] - node _T_1353 = eq(_T_1352, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 376:55] - node _T_1354 = and(obuf_rdrsp_pend, _T_1353) @[el2_lsu_bus_buffer.scala 376:53] - node _T_1355 = or(_T_1350, _T_1354) @[el2_lsu_bus_buffer.scala 376:34] - node _T_1356 = and(_T_1348, _T_1355) @[el2_lsu_bus_buffer.scala 375:165] - obuf_nosend_in <= _T_1356 @[el2_lsu_bus_buffer.scala 375:18] - node _T_1357 = bits(io.lsu_addr_r, 2, 2) @[el2_lsu_bus_buffer.scala 377:60] + node _T_1337 = bits(obuf_addr_in, 31, 3) @[el2_lsu_bus_buffer.scala 376:34] + node _T_1338 = bits(obuf_addr, 31, 3) @[el2_lsu_bus_buffer.scala 376:52] + node _T_1339 = eq(_T_1337, _T_1338) @[el2_lsu_bus_buffer.scala 376:40] + node _T_1340 = and(_T_1339, obuf_aligned_in) @[el2_lsu_bus_buffer.scala 376:60] + node _T_1341 = eq(obuf_sideeffect, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 376:80] + node _T_1342 = and(_T_1340, _T_1341) @[el2_lsu_bus_buffer.scala 376:78] + node _T_1343 = eq(obuf_write, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 376:99] + node _T_1344 = and(_T_1342, _T_1343) @[el2_lsu_bus_buffer.scala 376:97] + node _T_1345 = eq(obuf_write_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 376:113] + node _T_1346 = and(_T_1344, _T_1345) @[el2_lsu_bus_buffer.scala 376:111] + node _T_1347 = eq(io.dec_tlu_external_ldfwd_disable, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 376:130] + node _T_1348 = and(_T_1346, _T_1347) @[el2_lsu_bus_buffer.scala 376:128] + node _T_1349 = eq(obuf_nosend, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 377:20] + node _T_1350 = and(obuf_valid, _T_1349) @[el2_lsu_bus_buffer.scala 377:18] + node _T_1351 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[el2_lsu_bus_buffer.scala 377:90] + node _T_1352 = and(bus_rsp_read, _T_1351) @[el2_lsu_bus_buffer.scala 377:70] + node _T_1353 = eq(_T_1352, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 377:55] + node _T_1354 = and(obuf_rdrsp_pend, _T_1353) @[el2_lsu_bus_buffer.scala 377:53] + node _T_1355 = or(_T_1350, _T_1354) @[el2_lsu_bus_buffer.scala 377:34] + node _T_1356 = and(_T_1348, _T_1355) @[el2_lsu_bus_buffer.scala 376:165] + obuf_nosend_in <= _T_1356 @[el2_lsu_bus_buffer.scala 376:18] + node _T_1357 = bits(io.lsu_addr_r, 2, 2) @[el2_lsu_bus_buffer.scala 378:60] node _T_1358 = cat(ldst_byteen_lo_r, UInt<4>("h00")) @[Cat.scala 29:58] node _T_1359 = cat(UInt<4>("h00"), ldst_byteen_lo_r) @[Cat.scala 29:58] - node _T_1360 = mux(_T_1357, _T_1358, _T_1359) @[el2_lsu_bus_buffer.scala 377:46] + node _T_1360 = mux(_T_1357, _T_1358, _T_1359) @[el2_lsu_bus_buffer.scala 378:46] node _T_1361 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] node _T_1362 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] node _T_1363 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] @@ -2085,8 +2085,8 @@ circuit el2_lsu_bus_intf : node _T_1371 = or(_T_1370, _T_1368) @[Mux.scala 27:72] wire _T_1372 : UInt<32> @[Mux.scala 27:72] _T_1372 <= _T_1371 @[Mux.scala 27:72] - node _T_1373 = bits(_T_1372, 2, 2) @[el2_lsu_bus_buffer.scala 378:36] - node _T_1374 = bits(_T_1373, 0, 0) @[el2_lsu_bus_buffer.scala 378:46] + node _T_1373 = bits(_T_1372, 2, 2) @[el2_lsu_bus_buffer.scala 379:36] + node _T_1374 = bits(_T_1373, 0, 0) @[el2_lsu_bus_buffer.scala 379:46] node _T_1375 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] node _T_1376 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] node _T_1377 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] @@ -2115,16 +2115,16 @@ circuit el2_lsu_bus_intf : wire _T_1399 : UInt<4> @[Mux.scala 27:72] _T_1399 <= _T_1398 @[Mux.scala 27:72] node _T_1400 = cat(UInt<4>("h00"), _T_1399) @[Cat.scala 29:58] - node _T_1401 = mux(_T_1374, _T_1387, _T_1400) @[el2_lsu_bus_buffer.scala 378:8] - node obuf_byteen0_in = mux(ibuf_buf_byp, _T_1360, _T_1401) @[el2_lsu_bus_buffer.scala 377:28] - node _T_1402 = bits(io.end_addr_r, 2, 2) @[el2_lsu_bus_buffer.scala 379:60] + node _T_1401 = mux(_T_1374, _T_1387, _T_1400) @[el2_lsu_bus_buffer.scala 379:8] + node obuf_byteen0_in = mux(ibuf_buf_byp, _T_1360, _T_1401) @[el2_lsu_bus_buffer.scala 378:28] + node _T_1402 = bits(io.end_addr_r, 2, 2) @[el2_lsu_bus_buffer.scala 380:60] node _T_1403 = cat(ldst_byteen_hi_r, UInt<4>("h00")) @[Cat.scala 29:58] node _T_1404 = cat(UInt<4>("h00"), ldst_byteen_hi_r) @[Cat.scala 29:58] - node _T_1405 = mux(_T_1402, _T_1403, _T_1404) @[el2_lsu_bus_buffer.scala 379:46] - node _T_1406 = eq(Cmdptr1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] - node _T_1407 = eq(Cmdptr1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] - node _T_1408 = eq(Cmdptr1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] - node _T_1409 = eq(Cmdptr1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1405 = mux(_T_1402, _T_1403, _T_1404) @[el2_lsu_bus_buffer.scala 380:46] + node _T_1406 = eq(CmdPtr1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1407 = eq(CmdPtr1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1408 = eq(CmdPtr1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1409 = eq(CmdPtr1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] node _T_1410 = mux(_T_1406, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1411 = mux(_T_1407, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1412 = mux(_T_1408, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] @@ -2134,12 +2134,12 @@ circuit el2_lsu_bus_intf : node _T_1416 = or(_T_1415, _T_1413) @[Mux.scala 27:72] wire _T_1417 : UInt<32> @[Mux.scala 27:72] _T_1417 <= _T_1416 @[Mux.scala 27:72] - node _T_1418 = bits(_T_1417, 2, 2) @[el2_lsu_bus_buffer.scala 380:36] - node _T_1419 = bits(_T_1418, 0, 0) @[el2_lsu_bus_buffer.scala 380:46] - node _T_1420 = eq(Cmdptr1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] - node _T_1421 = eq(Cmdptr1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] - node _T_1422 = eq(Cmdptr1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] - node _T_1423 = eq(Cmdptr1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1418 = bits(_T_1417, 2, 2) @[el2_lsu_bus_buffer.scala 381:36] + node _T_1419 = bits(_T_1418, 0, 0) @[el2_lsu_bus_buffer.scala 381:46] + node _T_1420 = eq(CmdPtr1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1421 = eq(CmdPtr1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1422 = eq(CmdPtr1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1423 = eq(CmdPtr1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] node _T_1424 = mux(_T_1420, buf_byteen[0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1425 = mux(_T_1421, buf_byteen[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1426 = mux(_T_1422, buf_byteen[2], UInt<1>("h00")) @[Mux.scala 27:72] @@ -2150,10 +2150,10 @@ circuit el2_lsu_bus_intf : wire _T_1431 : UInt<4> @[Mux.scala 27:72] _T_1431 <= _T_1430 @[Mux.scala 27:72] node _T_1432 = cat(_T_1431, UInt<4>("h00")) @[Cat.scala 29:58] - node _T_1433 = eq(Cmdptr1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] - node _T_1434 = eq(Cmdptr1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] - node _T_1435 = eq(Cmdptr1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] - node _T_1436 = eq(Cmdptr1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1433 = eq(CmdPtr1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1434 = eq(CmdPtr1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1435 = eq(CmdPtr1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1436 = eq(CmdPtr1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] node _T_1437 = mux(_T_1433, buf_byteen[0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1438 = mux(_T_1434, buf_byteen[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1439 = mux(_T_1435, buf_byteen[2], UInt<1>("h00")) @[Mux.scala 27:72] @@ -2164,12 +2164,12 @@ circuit el2_lsu_bus_intf : wire _T_1444 : UInt<4> @[Mux.scala 27:72] _T_1444 <= _T_1443 @[Mux.scala 27:72] node _T_1445 = cat(UInt<4>("h00"), _T_1444) @[Cat.scala 29:58] - node _T_1446 = mux(_T_1419, _T_1432, _T_1445) @[el2_lsu_bus_buffer.scala 380:8] - node obuf_byteen1_in = mux(ibuf_buf_byp, _T_1405, _T_1446) @[el2_lsu_bus_buffer.scala 379:28] - node _T_1447 = bits(io.lsu_addr_r, 2, 2) @[el2_lsu_bus_buffer.scala 382:58] + node _T_1446 = mux(_T_1419, _T_1432, _T_1445) @[el2_lsu_bus_buffer.scala 381:8] + node obuf_byteen1_in = mux(ibuf_buf_byp, _T_1405, _T_1446) @[el2_lsu_bus_buffer.scala 380:28] + node _T_1447 = bits(io.lsu_addr_r, 2, 2) @[el2_lsu_bus_buffer.scala 383:58] node _T_1448 = cat(store_data_lo_r, UInt<32>("h00")) @[Cat.scala 29:58] node _T_1449 = cat(UInt<32>("h00"), store_data_lo_r) @[Cat.scala 29:58] - node _T_1450 = mux(_T_1447, _T_1448, _T_1449) @[el2_lsu_bus_buffer.scala 382:44] + node _T_1450 = mux(_T_1447, _T_1448, _T_1449) @[el2_lsu_bus_buffer.scala 383:44] node _T_1451 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] node _T_1452 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] node _T_1453 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] @@ -2183,8 +2183,8 @@ circuit el2_lsu_bus_intf : node _T_1461 = or(_T_1460, _T_1458) @[Mux.scala 27:72] wire _T_1462 : UInt<32> @[Mux.scala 27:72] _T_1462 <= _T_1461 @[Mux.scala 27:72] - node _T_1463 = bits(_T_1462, 2, 2) @[el2_lsu_bus_buffer.scala 383:36] - node _T_1464 = bits(_T_1463, 0, 0) @[el2_lsu_bus_buffer.scala 383:46] + node _T_1463 = bits(_T_1462, 2, 2) @[el2_lsu_bus_buffer.scala 384:36] + node _T_1464 = bits(_T_1463, 0, 0) @[el2_lsu_bus_buffer.scala 384:46] node _T_1465 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] node _T_1466 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] node _T_1467 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] @@ -2213,16 +2213,16 @@ circuit el2_lsu_bus_intf : wire _T_1489 : UInt<32> @[Mux.scala 27:72] _T_1489 <= _T_1488 @[Mux.scala 27:72] node _T_1490 = cat(UInt<32>("h00"), _T_1489) @[Cat.scala 29:58] - node _T_1491 = mux(_T_1464, _T_1477, _T_1490) @[el2_lsu_bus_buffer.scala 383:8] - node obuf_data0_in = mux(ibuf_buf_byp, _T_1450, _T_1491) @[el2_lsu_bus_buffer.scala 382:26] - node _T_1492 = bits(io.lsu_addr_r, 2, 2) @[el2_lsu_bus_buffer.scala 384:58] + node _T_1491 = mux(_T_1464, _T_1477, _T_1490) @[el2_lsu_bus_buffer.scala 384:8] + node obuf_data0_in = mux(ibuf_buf_byp, _T_1450, _T_1491) @[el2_lsu_bus_buffer.scala 383:26] + node _T_1492 = bits(io.lsu_addr_r, 2, 2) @[el2_lsu_bus_buffer.scala 385:58] node _T_1493 = cat(store_data_hi_r, UInt<32>("h00")) @[Cat.scala 29:58] node _T_1494 = cat(UInt<32>("h00"), store_data_hi_r) @[Cat.scala 29:58] - node _T_1495 = mux(_T_1492, _T_1493, _T_1494) @[el2_lsu_bus_buffer.scala 384:44] - node _T_1496 = eq(Cmdptr1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] - node _T_1497 = eq(Cmdptr1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] - node _T_1498 = eq(Cmdptr1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] - node _T_1499 = eq(Cmdptr1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1495 = mux(_T_1492, _T_1493, _T_1494) @[el2_lsu_bus_buffer.scala 385:44] + node _T_1496 = eq(CmdPtr1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1497 = eq(CmdPtr1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1498 = eq(CmdPtr1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1499 = eq(CmdPtr1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] node _T_1500 = mux(_T_1496, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1501 = mux(_T_1497, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1502 = mux(_T_1498, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] @@ -2232,12 +2232,12 @@ circuit el2_lsu_bus_intf : node _T_1506 = or(_T_1505, _T_1503) @[Mux.scala 27:72] wire _T_1507 : UInt<32> @[Mux.scala 27:72] _T_1507 <= _T_1506 @[Mux.scala 27:72] - node _T_1508 = bits(_T_1507, 2, 2) @[el2_lsu_bus_buffer.scala 385:36] - node _T_1509 = bits(_T_1508, 0, 0) @[el2_lsu_bus_buffer.scala 385:46] - node _T_1510 = eq(Cmdptr1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] - node _T_1511 = eq(Cmdptr1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] - node _T_1512 = eq(Cmdptr1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] - node _T_1513 = eq(Cmdptr1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1508 = bits(_T_1507, 2, 2) @[el2_lsu_bus_buffer.scala 386:36] + node _T_1509 = bits(_T_1508, 0, 0) @[el2_lsu_bus_buffer.scala 386:46] + node _T_1510 = eq(CmdPtr1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1511 = eq(CmdPtr1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1512 = eq(CmdPtr1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1513 = eq(CmdPtr1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] node _T_1514 = mux(_T_1510, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1515 = mux(_T_1511, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1516 = mux(_T_1512, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] @@ -2248,10 +2248,10 @@ circuit el2_lsu_bus_intf : wire _T_1521 : UInt<32> @[Mux.scala 27:72] _T_1521 <= _T_1520 @[Mux.scala 27:72] node _T_1522 = cat(_T_1521, UInt<32>("h00")) @[Cat.scala 29:58] - node _T_1523 = eq(Cmdptr1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] - node _T_1524 = eq(Cmdptr1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] - node _T_1525 = eq(Cmdptr1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] - node _T_1526 = eq(Cmdptr1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1523 = eq(CmdPtr1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1524 = eq(CmdPtr1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1525 = eq(CmdPtr1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1526 = eq(CmdPtr1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] node _T_1527 = mux(_T_1523, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1528 = mux(_T_1524, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1529 = mux(_T_1525, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] @@ -2262,40 +2262,40 @@ circuit el2_lsu_bus_intf : wire _T_1534 : UInt<32> @[Mux.scala 27:72] _T_1534 <= _T_1533 @[Mux.scala 27:72] node _T_1535 = cat(UInt<32>("h00"), _T_1534) @[Cat.scala 29:58] - node _T_1536 = mux(_T_1509, _T_1522, _T_1535) @[el2_lsu_bus_buffer.scala 385:8] - node obuf_data1_in = mux(ibuf_buf_byp, _T_1495, _T_1536) @[el2_lsu_bus_buffer.scala 384:26] - node _T_1537 = bits(obuf_byteen0_in, 0, 0) @[el2_lsu_bus_buffer.scala 386:59] - node _T_1538 = bits(obuf_byteen1_in, 0, 0) @[el2_lsu_bus_buffer.scala 386:97] - node _T_1539 = and(obuf_merge_en, _T_1538) @[el2_lsu_bus_buffer.scala 386:80] - node _T_1540 = or(_T_1537, _T_1539) @[el2_lsu_bus_buffer.scala 386:63] - node _T_1541 = bits(obuf_byteen0_in, 1, 1) @[el2_lsu_bus_buffer.scala 386:59] - node _T_1542 = bits(obuf_byteen1_in, 1, 1) @[el2_lsu_bus_buffer.scala 386:97] - node _T_1543 = and(obuf_merge_en, _T_1542) @[el2_lsu_bus_buffer.scala 386:80] - node _T_1544 = or(_T_1541, _T_1543) @[el2_lsu_bus_buffer.scala 386:63] - node _T_1545 = bits(obuf_byteen0_in, 2, 2) @[el2_lsu_bus_buffer.scala 386:59] - node _T_1546 = bits(obuf_byteen1_in, 2, 2) @[el2_lsu_bus_buffer.scala 386:97] - node _T_1547 = and(obuf_merge_en, _T_1546) @[el2_lsu_bus_buffer.scala 386:80] - node _T_1548 = or(_T_1545, _T_1547) @[el2_lsu_bus_buffer.scala 386:63] - node _T_1549 = bits(obuf_byteen0_in, 3, 3) @[el2_lsu_bus_buffer.scala 386:59] - node _T_1550 = bits(obuf_byteen1_in, 3, 3) @[el2_lsu_bus_buffer.scala 386:97] - node _T_1551 = and(obuf_merge_en, _T_1550) @[el2_lsu_bus_buffer.scala 386:80] - node _T_1552 = or(_T_1549, _T_1551) @[el2_lsu_bus_buffer.scala 386:63] - node _T_1553 = bits(obuf_byteen0_in, 4, 4) @[el2_lsu_bus_buffer.scala 386:59] - node _T_1554 = bits(obuf_byteen1_in, 4, 4) @[el2_lsu_bus_buffer.scala 386:97] - node _T_1555 = and(obuf_merge_en, _T_1554) @[el2_lsu_bus_buffer.scala 386:80] - node _T_1556 = or(_T_1553, _T_1555) @[el2_lsu_bus_buffer.scala 386:63] - node _T_1557 = bits(obuf_byteen0_in, 5, 5) @[el2_lsu_bus_buffer.scala 386:59] - node _T_1558 = bits(obuf_byteen1_in, 5, 5) @[el2_lsu_bus_buffer.scala 386:97] - node _T_1559 = and(obuf_merge_en, _T_1558) @[el2_lsu_bus_buffer.scala 386:80] - node _T_1560 = or(_T_1557, _T_1559) @[el2_lsu_bus_buffer.scala 386:63] - node _T_1561 = bits(obuf_byteen0_in, 6, 6) @[el2_lsu_bus_buffer.scala 386:59] - node _T_1562 = bits(obuf_byteen1_in, 6, 6) @[el2_lsu_bus_buffer.scala 386:97] - node _T_1563 = and(obuf_merge_en, _T_1562) @[el2_lsu_bus_buffer.scala 386:80] - node _T_1564 = or(_T_1561, _T_1563) @[el2_lsu_bus_buffer.scala 386:63] - node _T_1565 = bits(obuf_byteen0_in, 7, 7) @[el2_lsu_bus_buffer.scala 386:59] - node _T_1566 = bits(obuf_byteen1_in, 7, 7) @[el2_lsu_bus_buffer.scala 386:97] - node _T_1567 = and(obuf_merge_en, _T_1566) @[el2_lsu_bus_buffer.scala 386:80] - node _T_1568 = or(_T_1565, _T_1567) @[el2_lsu_bus_buffer.scala 386:63] + node _T_1536 = mux(_T_1509, _T_1522, _T_1535) @[el2_lsu_bus_buffer.scala 386:8] + node obuf_data1_in = mux(ibuf_buf_byp, _T_1495, _T_1536) @[el2_lsu_bus_buffer.scala 385:26] + node _T_1537 = bits(obuf_byteen0_in, 0, 0) @[el2_lsu_bus_buffer.scala 387:59] + node _T_1538 = bits(obuf_byteen1_in, 0, 0) @[el2_lsu_bus_buffer.scala 387:97] + node _T_1539 = and(obuf_merge_en, _T_1538) @[el2_lsu_bus_buffer.scala 387:80] + node _T_1540 = or(_T_1537, _T_1539) @[el2_lsu_bus_buffer.scala 387:63] + node _T_1541 = bits(obuf_byteen0_in, 1, 1) @[el2_lsu_bus_buffer.scala 387:59] + node _T_1542 = bits(obuf_byteen1_in, 1, 1) @[el2_lsu_bus_buffer.scala 387:97] + node _T_1543 = and(obuf_merge_en, _T_1542) @[el2_lsu_bus_buffer.scala 387:80] + node _T_1544 = or(_T_1541, _T_1543) @[el2_lsu_bus_buffer.scala 387:63] + node _T_1545 = bits(obuf_byteen0_in, 2, 2) @[el2_lsu_bus_buffer.scala 387:59] + node _T_1546 = bits(obuf_byteen1_in, 2, 2) @[el2_lsu_bus_buffer.scala 387:97] + node _T_1547 = and(obuf_merge_en, _T_1546) @[el2_lsu_bus_buffer.scala 387:80] + node _T_1548 = or(_T_1545, _T_1547) @[el2_lsu_bus_buffer.scala 387:63] + node _T_1549 = bits(obuf_byteen0_in, 3, 3) @[el2_lsu_bus_buffer.scala 387:59] + node _T_1550 = bits(obuf_byteen1_in, 3, 3) @[el2_lsu_bus_buffer.scala 387:97] + node _T_1551 = and(obuf_merge_en, _T_1550) @[el2_lsu_bus_buffer.scala 387:80] + node _T_1552 = or(_T_1549, _T_1551) @[el2_lsu_bus_buffer.scala 387:63] + node _T_1553 = bits(obuf_byteen0_in, 4, 4) @[el2_lsu_bus_buffer.scala 387:59] + node _T_1554 = bits(obuf_byteen1_in, 4, 4) @[el2_lsu_bus_buffer.scala 387:97] + node _T_1555 = and(obuf_merge_en, _T_1554) @[el2_lsu_bus_buffer.scala 387:80] + node _T_1556 = or(_T_1553, _T_1555) @[el2_lsu_bus_buffer.scala 387:63] + node _T_1557 = bits(obuf_byteen0_in, 5, 5) @[el2_lsu_bus_buffer.scala 387:59] + node _T_1558 = bits(obuf_byteen1_in, 5, 5) @[el2_lsu_bus_buffer.scala 387:97] + node _T_1559 = and(obuf_merge_en, _T_1558) @[el2_lsu_bus_buffer.scala 387:80] + node _T_1560 = or(_T_1557, _T_1559) @[el2_lsu_bus_buffer.scala 387:63] + node _T_1561 = bits(obuf_byteen0_in, 6, 6) @[el2_lsu_bus_buffer.scala 387:59] + node _T_1562 = bits(obuf_byteen1_in, 6, 6) @[el2_lsu_bus_buffer.scala 387:97] + node _T_1563 = and(obuf_merge_en, _T_1562) @[el2_lsu_bus_buffer.scala 387:80] + node _T_1564 = or(_T_1561, _T_1563) @[el2_lsu_bus_buffer.scala 387:63] + node _T_1565 = bits(obuf_byteen0_in, 7, 7) @[el2_lsu_bus_buffer.scala 387:59] + node _T_1566 = bits(obuf_byteen1_in, 7, 7) @[el2_lsu_bus_buffer.scala 387:97] + node _T_1567 = and(obuf_merge_en, _T_1566) @[el2_lsu_bus_buffer.scala 387:80] + node _T_1568 = or(_T_1565, _T_1567) @[el2_lsu_bus_buffer.scala 387:63] node _T_1569 = cat(_T_1568, _T_1564) @[Cat.scala 29:58] node _T_1570 = cat(_T_1569, _T_1560) @[Cat.scala 29:58] node _T_1571 = cat(_T_1570, _T_1556) @[Cat.scala 29:58] @@ -2303,46 +2303,46 @@ circuit el2_lsu_bus_intf : node _T_1573 = cat(_T_1572, _T_1548) @[Cat.scala 29:58] node _T_1574 = cat(_T_1573, _T_1544) @[Cat.scala 29:58] node obuf_byteen_in = cat(_T_1574, _T_1540) @[Cat.scala 29:58] - node _T_1575 = bits(obuf_byteen1_in, 0, 0) @[el2_lsu_bus_buffer.scala 387:76] - node _T_1576 = and(obuf_merge_en, _T_1575) @[el2_lsu_bus_buffer.scala 387:59] - node _T_1577 = bits(obuf_data1_in, 7, 0) @[el2_lsu_bus_buffer.scala 387:94] - node _T_1578 = bits(obuf_data0_in, 7, 0) @[el2_lsu_bus_buffer.scala 387:123] - node _T_1579 = mux(_T_1576, _T_1577, _T_1578) @[el2_lsu_bus_buffer.scala 387:44] - node _T_1580 = bits(obuf_byteen1_in, 1, 1) @[el2_lsu_bus_buffer.scala 387:76] - node _T_1581 = and(obuf_merge_en, _T_1580) @[el2_lsu_bus_buffer.scala 387:59] - node _T_1582 = bits(obuf_data1_in, 15, 8) @[el2_lsu_bus_buffer.scala 387:94] - node _T_1583 = bits(obuf_data0_in, 15, 8) @[el2_lsu_bus_buffer.scala 387:123] - node _T_1584 = mux(_T_1581, _T_1582, _T_1583) @[el2_lsu_bus_buffer.scala 387:44] - node _T_1585 = bits(obuf_byteen1_in, 2, 2) @[el2_lsu_bus_buffer.scala 387:76] - node _T_1586 = and(obuf_merge_en, _T_1585) @[el2_lsu_bus_buffer.scala 387:59] - node _T_1587 = bits(obuf_data1_in, 23, 16) @[el2_lsu_bus_buffer.scala 387:94] - node _T_1588 = bits(obuf_data0_in, 23, 16) @[el2_lsu_bus_buffer.scala 387:123] - node _T_1589 = mux(_T_1586, _T_1587, _T_1588) @[el2_lsu_bus_buffer.scala 387:44] - node _T_1590 = bits(obuf_byteen1_in, 3, 3) @[el2_lsu_bus_buffer.scala 387:76] - node _T_1591 = and(obuf_merge_en, _T_1590) @[el2_lsu_bus_buffer.scala 387:59] - node _T_1592 = bits(obuf_data1_in, 31, 24) @[el2_lsu_bus_buffer.scala 387:94] - node _T_1593 = bits(obuf_data0_in, 31, 24) @[el2_lsu_bus_buffer.scala 387:123] - node _T_1594 = mux(_T_1591, _T_1592, _T_1593) @[el2_lsu_bus_buffer.scala 387:44] - node _T_1595 = bits(obuf_byteen1_in, 4, 4) @[el2_lsu_bus_buffer.scala 387:76] - node _T_1596 = and(obuf_merge_en, _T_1595) @[el2_lsu_bus_buffer.scala 387:59] - node _T_1597 = bits(obuf_data1_in, 39, 32) @[el2_lsu_bus_buffer.scala 387:94] - node _T_1598 = bits(obuf_data0_in, 39, 32) @[el2_lsu_bus_buffer.scala 387:123] - node _T_1599 = mux(_T_1596, _T_1597, _T_1598) @[el2_lsu_bus_buffer.scala 387:44] - node _T_1600 = bits(obuf_byteen1_in, 5, 5) @[el2_lsu_bus_buffer.scala 387:76] - node _T_1601 = and(obuf_merge_en, _T_1600) @[el2_lsu_bus_buffer.scala 387:59] - node _T_1602 = bits(obuf_data1_in, 47, 40) @[el2_lsu_bus_buffer.scala 387:94] - node _T_1603 = bits(obuf_data0_in, 47, 40) @[el2_lsu_bus_buffer.scala 387:123] - node _T_1604 = mux(_T_1601, _T_1602, _T_1603) @[el2_lsu_bus_buffer.scala 387:44] - node _T_1605 = bits(obuf_byteen1_in, 6, 6) @[el2_lsu_bus_buffer.scala 387:76] - node _T_1606 = and(obuf_merge_en, _T_1605) @[el2_lsu_bus_buffer.scala 387:59] - node _T_1607 = bits(obuf_data1_in, 55, 48) @[el2_lsu_bus_buffer.scala 387:94] - node _T_1608 = bits(obuf_data0_in, 55, 48) @[el2_lsu_bus_buffer.scala 387:123] - node _T_1609 = mux(_T_1606, _T_1607, _T_1608) @[el2_lsu_bus_buffer.scala 387:44] - node _T_1610 = bits(obuf_byteen1_in, 7, 7) @[el2_lsu_bus_buffer.scala 387:76] - node _T_1611 = and(obuf_merge_en, _T_1610) @[el2_lsu_bus_buffer.scala 387:59] - node _T_1612 = bits(obuf_data1_in, 63, 56) @[el2_lsu_bus_buffer.scala 387:94] - node _T_1613 = bits(obuf_data0_in, 63, 56) @[el2_lsu_bus_buffer.scala 387:123] - node _T_1614 = mux(_T_1611, _T_1612, _T_1613) @[el2_lsu_bus_buffer.scala 387:44] + node _T_1575 = bits(obuf_byteen1_in, 0, 0) @[el2_lsu_bus_buffer.scala 388:76] + node _T_1576 = and(obuf_merge_en, _T_1575) @[el2_lsu_bus_buffer.scala 388:59] + node _T_1577 = bits(obuf_data1_in, 7, 0) @[el2_lsu_bus_buffer.scala 388:94] + node _T_1578 = bits(obuf_data0_in, 7, 0) @[el2_lsu_bus_buffer.scala 388:123] + node _T_1579 = mux(_T_1576, _T_1577, _T_1578) @[el2_lsu_bus_buffer.scala 388:44] + node _T_1580 = bits(obuf_byteen1_in, 1, 1) @[el2_lsu_bus_buffer.scala 388:76] + node _T_1581 = and(obuf_merge_en, _T_1580) @[el2_lsu_bus_buffer.scala 388:59] + node _T_1582 = bits(obuf_data1_in, 15, 8) @[el2_lsu_bus_buffer.scala 388:94] + node _T_1583 = bits(obuf_data0_in, 15, 8) @[el2_lsu_bus_buffer.scala 388:123] + node _T_1584 = mux(_T_1581, _T_1582, _T_1583) @[el2_lsu_bus_buffer.scala 388:44] + node _T_1585 = bits(obuf_byteen1_in, 2, 2) @[el2_lsu_bus_buffer.scala 388:76] + node _T_1586 = and(obuf_merge_en, _T_1585) @[el2_lsu_bus_buffer.scala 388:59] + node _T_1587 = bits(obuf_data1_in, 23, 16) @[el2_lsu_bus_buffer.scala 388:94] + node _T_1588 = bits(obuf_data0_in, 23, 16) @[el2_lsu_bus_buffer.scala 388:123] + node _T_1589 = mux(_T_1586, _T_1587, _T_1588) @[el2_lsu_bus_buffer.scala 388:44] + node _T_1590 = bits(obuf_byteen1_in, 3, 3) @[el2_lsu_bus_buffer.scala 388:76] + node _T_1591 = and(obuf_merge_en, _T_1590) @[el2_lsu_bus_buffer.scala 388:59] + node _T_1592 = bits(obuf_data1_in, 31, 24) @[el2_lsu_bus_buffer.scala 388:94] + node _T_1593 = bits(obuf_data0_in, 31, 24) @[el2_lsu_bus_buffer.scala 388:123] + node _T_1594 = mux(_T_1591, _T_1592, _T_1593) @[el2_lsu_bus_buffer.scala 388:44] + node _T_1595 = bits(obuf_byteen1_in, 4, 4) @[el2_lsu_bus_buffer.scala 388:76] + node _T_1596 = and(obuf_merge_en, _T_1595) @[el2_lsu_bus_buffer.scala 388:59] + node _T_1597 = bits(obuf_data1_in, 39, 32) @[el2_lsu_bus_buffer.scala 388:94] + node _T_1598 = bits(obuf_data0_in, 39, 32) @[el2_lsu_bus_buffer.scala 388:123] + node _T_1599 = mux(_T_1596, _T_1597, _T_1598) @[el2_lsu_bus_buffer.scala 388:44] + node _T_1600 = bits(obuf_byteen1_in, 5, 5) @[el2_lsu_bus_buffer.scala 388:76] + node _T_1601 = and(obuf_merge_en, _T_1600) @[el2_lsu_bus_buffer.scala 388:59] + node _T_1602 = bits(obuf_data1_in, 47, 40) @[el2_lsu_bus_buffer.scala 388:94] + node _T_1603 = bits(obuf_data0_in, 47, 40) @[el2_lsu_bus_buffer.scala 388:123] + node _T_1604 = mux(_T_1601, _T_1602, _T_1603) @[el2_lsu_bus_buffer.scala 388:44] + node _T_1605 = bits(obuf_byteen1_in, 6, 6) @[el2_lsu_bus_buffer.scala 388:76] + node _T_1606 = and(obuf_merge_en, _T_1605) @[el2_lsu_bus_buffer.scala 388:59] + node _T_1607 = bits(obuf_data1_in, 55, 48) @[el2_lsu_bus_buffer.scala 388:94] + node _T_1608 = bits(obuf_data0_in, 55, 48) @[el2_lsu_bus_buffer.scala 388:123] + node _T_1609 = mux(_T_1606, _T_1607, _T_1608) @[el2_lsu_bus_buffer.scala 388:44] + node _T_1610 = bits(obuf_byteen1_in, 7, 7) @[el2_lsu_bus_buffer.scala 388:76] + node _T_1611 = and(obuf_merge_en, _T_1610) @[el2_lsu_bus_buffer.scala 388:59] + node _T_1612 = bits(obuf_data1_in, 63, 56) @[el2_lsu_bus_buffer.scala 388:94] + node _T_1613 = bits(obuf_data0_in, 63, 56) @[el2_lsu_bus_buffer.scala 388:123] + node _T_1614 = mux(_T_1611, _T_1612, _T_1613) @[el2_lsu_bus_buffer.scala 388:44] node _T_1615 = cat(_T_1614, _T_1609) @[Cat.scala 29:58] node _T_1616 = cat(_T_1615, _T_1604) @[Cat.scala 29:58] node _T_1617 = cat(_T_1616, _T_1599) @[Cat.scala 29:58] @@ -2350,14 +2350,14 @@ circuit el2_lsu_bus_intf : node _T_1619 = cat(_T_1618, _T_1589) @[Cat.scala 29:58] node _T_1620 = cat(_T_1619, _T_1584) @[Cat.scala 29:58] node obuf_data_in = cat(_T_1620, _T_1579) @[Cat.scala 29:58] - wire buf_dualhi : UInt<1>[4] @[el2_lsu_bus_buffer.scala 389:24] - buf_dualhi[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 390:14] - buf_dualhi[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 390:14] - buf_dualhi[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 390:14] - buf_dualhi[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 390:14] - node _T_1621 = neq(CmdPtr0, Cmdptr1) @[el2_lsu_bus_buffer.scala 391:30] - node _T_1622 = and(_T_1621, found_cmdptr0) @[el2_lsu_bus_buffer.scala 391:43] - node _T_1623 = and(_T_1622, found_cmdptr1) @[el2_lsu_bus_buffer.scala 391:59] + wire buf_dualhi : UInt<1>[4] @[el2_lsu_bus_buffer.scala 390:24] + buf_dualhi[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 391:14] + buf_dualhi[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 391:14] + buf_dualhi[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 391:14] + buf_dualhi[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 391:14] + node _T_1621 = neq(CmdPtr0, CmdPtr1) @[el2_lsu_bus_buffer.scala 392:30] + node _T_1622 = and(_T_1621, found_cmdptr0) @[el2_lsu_bus_buffer.scala 392:43] + node _T_1623 = and(_T_1622, found_cmdptr1) @[el2_lsu_bus_buffer.scala 392:59] node _T_1624 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] node _T_1625 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] node _T_1626 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] @@ -2371,12 +2371,12 @@ circuit el2_lsu_bus_intf : node _T_1634 = or(_T_1633, _T_1631) @[Mux.scala 27:72] wire _T_1635 : UInt<3> @[Mux.scala 27:72] _T_1635 <= _T_1634 @[Mux.scala 27:72] - node _T_1636 = eq(_T_1635, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 391:107] - node _T_1637 = and(_T_1623, _T_1636) @[el2_lsu_bus_buffer.scala 391:75] - node _T_1638 = eq(Cmdptr1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] - node _T_1639 = eq(Cmdptr1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] - node _T_1640 = eq(Cmdptr1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] - node _T_1641 = eq(Cmdptr1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1636 = eq(_T_1635, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 392:107] + node _T_1637 = and(_T_1623, _T_1636) @[el2_lsu_bus_buffer.scala 392:75] + node _T_1638 = eq(CmdPtr1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1639 = eq(CmdPtr1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1640 = eq(CmdPtr1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1641 = eq(CmdPtr1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] node _T_1642 = mux(_T_1638, buf_state[0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1643 = mux(_T_1639, buf_state[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1644 = mux(_T_1640, buf_state[2], UInt<1>("h00")) @[Mux.scala 27:72] @@ -2386,8 +2386,8 @@ circuit el2_lsu_bus_intf : node _T_1648 = or(_T_1647, _T_1645) @[Mux.scala 27:72] wire _T_1649 : UInt<3> @[Mux.scala 27:72] _T_1649 <= _T_1648 @[Mux.scala 27:72] - node _T_1650 = eq(_T_1649, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 391:150] - node _T_1651 = and(_T_1637, _T_1650) @[el2_lsu_bus_buffer.scala 391:118] + node _T_1650 = eq(_T_1649, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 392:150] + node _T_1651 = and(_T_1637, _T_1650) @[el2_lsu_bus_buffer.scala 392:118] node _T_1652 = cat(buf_cmd_state_bus_en[3], buf_cmd_state_bus_en[2]) @[Cat.scala 29:58] node _T_1653 = cat(_T_1652, buf_cmd_state_bus_en[1]) @[Cat.scala 29:58] node _T_1654 = cat(_T_1653, buf_cmd_state_bus_en[0]) @[Cat.scala 29:58] @@ -2408,8 +2408,8 @@ circuit el2_lsu_bus_intf : node _T_1669 = or(_T_1668, _T_1666) @[Mux.scala 27:72] wire _T_1670 : UInt<1> @[Mux.scala 27:72] _T_1670 <= _T_1669 @[Mux.scala 27:72] - node _T_1671 = eq(_T_1670, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 392:5] - node _T_1672 = and(_T_1651, _T_1671) @[el2_lsu_bus_buffer.scala 391:161] + node _T_1671 = eq(_T_1670, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 393:5] + node _T_1672 = and(_T_1651, _T_1671) @[el2_lsu_bus_buffer.scala 392:161] node _T_1673 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] node _T_1674 = bits(buf_sideeffect, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] node _T_1675 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] @@ -2427,8 +2427,8 @@ circuit el2_lsu_bus_intf : node _T_1687 = or(_T_1686, _T_1684) @[Mux.scala 27:72] wire _T_1688 : UInt<1> @[Mux.scala 27:72] _T_1688 <= _T_1687 @[Mux.scala 27:72] - node _T_1689 = eq(_T_1688, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 392:87] - node _T_1690 = and(_T_1672, _T_1689) @[el2_lsu_bus_buffer.scala 392:85] + node _T_1689 = eq(_T_1688, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 393:87] + node _T_1690 = and(_T_1672, _T_1689) @[el2_lsu_bus_buffer.scala 393:85] node _T_1691 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] node _T_1692 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] node _T_1693 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] @@ -2446,13 +2446,13 @@ circuit el2_lsu_bus_intf : node _T_1705 = or(_T_1704, _T_1702) @[Mux.scala 27:72] wire _T_1706 : UInt<1> @[Mux.scala 27:72] _T_1706 <= _T_1705 @[Mux.scala 27:72] - node _T_1707 = eq(Cmdptr1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1707 = eq(CmdPtr1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] node _T_1708 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] - node _T_1709 = eq(Cmdptr1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1709 = eq(CmdPtr1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] node _T_1710 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] - node _T_1711 = eq(Cmdptr1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1711 = eq(CmdPtr1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] node _T_1712 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] - node _T_1713 = eq(Cmdptr1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1713 = eq(CmdPtr1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] node _T_1714 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] node _T_1715 = mux(_T_1707, _T_1708, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1716 = mux(_T_1709, _T_1710, UInt<1>("h00")) @[Mux.scala 27:72] @@ -2463,7 +2463,7 @@ circuit el2_lsu_bus_intf : node _T_1721 = or(_T_1720, _T_1718) @[Mux.scala 27:72] wire _T_1722 : UInt<1> @[Mux.scala 27:72] _T_1722 <= _T_1721 @[Mux.scala 27:72] - node _T_1723 = and(_T_1706, _T_1722) @[el2_lsu_bus_buffer.scala 393:36] + node _T_1723 = and(_T_1706, _T_1722) @[el2_lsu_bus_buffer.scala 394:36] node _T_1724 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] node _T_1725 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] node _T_1726 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] @@ -2477,11 +2477,11 @@ circuit el2_lsu_bus_intf : node _T_1734 = or(_T_1733, _T_1731) @[Mux.scala 27:72] wire _T_1735 : UInt<32> @[Mux.scala 27:72] _T_1735 <= _T_1734 @[Mux.scala 27:72] - node _T_1736 = bits(_T_1735, 31, 3) @[el2_lsu_bus_buffer.scala 394:35] - node _T_1737 = eq(Cmdptr1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] - node _T_1738 = eq(Cmdptr1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] - node _T_1739 = eq(Cmdptr1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] - node _T_1740 = eq(Cmdptr1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1736 = bits(_T_1735, 31, 3) @[el2_lsu_bus_buffer.scala 395:35] + node _T_1737 = eq(CmdPtr1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1738 = eq(CmdPtr1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1739 = eq(CmdPtr1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1740 = eq(CmdPtr1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] node _T_1741 = mux(_T_1737, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1742 = mux(_T_1738, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1743 = mux(_T_1739, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] @@ -2491,13 +2491,13 @@ circuit el2_lsu_bus_intf : node _T_1747 = or(_T_1746, _T_1744) @[Mux.scala 27:72] wire _T_1748 : UInt<32> @[Mux.scala 27:72] _T_1748 <= _T_1747 @[Mux.scala 27:72] - node _T_1749 = bits(_T_1748, 31, 3) @[el2_lsu_bus_buffer.scala 394:71] - node _T_1750 = eq(_T_1736, _T_1749) @[el2_lsu_bus_buffer.scala 394:41] - node _T_1751 = and(_T_1723, _T_1750) @[el2_lsu_bus_buffer.scala 393:67] - node _T_1752 = eq(bus_coalescing_disable, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 394:81] - node _T_1753 = and(_T_1751, _T_1752) @[el2_lsu_bus_buffer.scala 394:79] - node _T_1754 = eq(UInt<1>("h01"), UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 394:107] - node _T_1755 = and(_T_1753, _T_1754) @[el2_lsu_bus_buffer.scala 394:105] + node _T_1749 = bits(_T_1748, 31, 3) @[el2_lsu_bus_buffer.scala 395:71] + node _T_1750 = eq(_T_1736, _T_1749) @[el2_lsu_bus_buffer.scala 395:41] + node _T_1751 = and(_T_1723, _T_1750) @[el2_lsu_bus_buffer.scala 394:67] + node _T_1752 = eq(bus_coalescing_disable, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 395:81] + node _T_1753 = and(_T_1751, _T_1752) @[el2_lsu_bus_buffer.scala 395:79] + node _T_1754 = eq(UInt<1>("h01"), UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 395:107] + node _T_1755 = and(_T_1753, _T_1754) @[el2_lsu_bus_buffer.scala 395:105] node _T_1756 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] node _T_1757 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] node _T_1758 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] @@ -2515,7 +2515,7 @@ circuit el2_lsu_bus_intf : node _T_1770 = or(_T_1769, _T_1767) @[Mux.scala 27:72] wire _T_1771 : UInt<1> @[Mux.scala 27:72] _T_1771 <= _T_1770 @[Mux.scala 27:72] - node _T_1772 = eq(_T_1771, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 395:8] + node _T_1772 = eq(_T_1771, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 396:8] node _T_1773 = cat(buf_dual[3], buf_dual[2]) @[Cat.scala 29:58] node _T_1774 = cat(_T_1773, buf_dual[1]) @[Cat.scala 29:58] node _T_1775 = cat(_T_1774, buf_dual[0]) @[Cat.scala 29:58] @@ -2536,7 +2536,7 @@ circuit el2_lsu_bus_intf : node _T_1790 = or(_T_1789, _T_1787) @[Mux.scala 27:72] wire _T_1791 : UInt<1> @[Mux.scala 27:72] _T_1791 <= _T_1790 @[Mux.scala 27:72] - node _T_1792 = and(_T_1772, _T_1791) @[el2_lsu_bus_buffer.scala 395:38] + node _T_1792 = and(_T_1772, _T_1791) @[el2_lsu_bus_buffer.scala 396:38] node _T_1793 = cat(buf_dualhi[3], buf_dualhi[2]) @[Cat.scala 29:58] node _T_1794 = cat(_T_1793, buf_dualhi[1]) @[Cat.scala 29:58] node _T_1795 = cat(_T_1794, buf_dualhi[0]) @[Cat.scala 29:58] @@ -2557,8 +2557,8 @@ circuit el2_lsu_bus_intf : node _T_1810 = or(_T_1809, _T_1807) @[Mux.scala 27:72] wire _T_1811 : UInt<1> @[Mux.scala 27:72] _T_1811 <= _T_1810 @[Mux.scala 27:72] - node _T_1812 = eq(_T_1811, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 395:109] - node _T_1813 = and(_T_1792, _T_1812) @[el2_lsu_bus_buffer.scala 395:107] + node _T_1812 = eq(_T_1811, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 396:109] + node _T_1813 = and(_T_1792, _T_1812) @[el2_lsu_bus_buffer.scala 396:107] node _T_1814 = cat(buf_samedw[3], buf_samedw[2]) @[Cat.scala 29:58] node _T_1815 = cat(_T_1814, buf_samedw[1]) @[Cat.scala 29:58] node _T_1816 = cat(_T_1815, buf_samedw[0]) @[Cat.scala 29:58] @@ -2579,43 +2579,43 @@ circuit el2_lsu_bus_intf : node _T_1831 = or(_T_1830, _T_1828) @[Mux.scala 27:72] wire _T_1832 : UInt<1> @[Mux.scala 27:72] _T_1832 <= _T_1831 @[Mux.scala 27:72] - node _T_1833 = and(_T_1813, _T_1832) @[el2_lsu_bus_buffer.scala 395:179] - node _T_1834 = or(_T_1755, _T_1833) @[el2_lsu_bus_buffer.scala 394:128] - node _T_1835 = and(_T_1690, _T_1834) @[el2_lsu_bus_buffer.scala 392:122] - node _T_1836 = and(ibuf_buf_byp, ldst_samedw_r) @[el2_lsu_bus_buffer.scala 396:19] - node _T_1837 = and(_T_1836, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 396:35] - node _T_1838 = or(_T_1835, _T_1837) @[el2_lsu_bus_buffer.scala 395:253] - obuf_merge_en <= _T_1838 @[el2_lsu_bus_buffer.scala 391:17] - reg obuf_wr_enQ : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 398:55] - obuf_wr_enQ <= obuf_wr_en @[el2_lsu_bus_buffer.scala 398:55] - node _T_1839 = mux(obuf_wr_en, UInt<1>("h01"), obuf_valid) @[el2_lsu_bus_buffer.scala 399:58] - node _T_1840 = eq(obuf_rst, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 399:93] - node _T_1841 = and(_T_1839, _T_1840) @[el2_lsu_bus_buffer.scala 399:91] - reg _T_1842 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 399:54] - _T_1842 <= _T_1841 @[el2_lsu_bus_buffer.scala 399:54] - obuf_valid <= _T_1842 @[el2_lsu_bus_buffer.scala 399:14] + node _T_1833 = and(_T_1813, _T_1832) @[el2_lsu_bus_buffer.scala 396:179] + node _T_1834 = or(_T_1755, _T_1833) @[el2_lsu_bus_buffer.scala 395:128] + node _T_1835 = and(_T_1690, _T_1834) @[el2_lsu_bus_buffer.scala 393:122] + node _T_1836 = and(ibuf_buf_byp, ldst_samedw_r) @[el2_lsu_bus_buffer.scala 397:19] + node _T_1837 = and(_T_1836, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 397:35] + node _T_1838 = or(_T_1835, _T_1837) @[el2_lsu_bus_buffer.scala 396:253] + obuf_merge_en <= _T_1838 @[el2_lsu_bus_buffer.scala 392:17] + reg obuf_wr_enQ : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 399:55] + obuf_wr_enQ <= obuf_wr_en @[el2_lsu_bus_buffer.scala 399:55] + node _T_1839 = mux(obuf_wr_en, UInt<1>("h01"), obuf_valid) @[el2_lsu_bus_buffer.scala 400:58] + node _T_1840 = eq(obuf_rst, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 400:93] + node _T_1841 = and(_T_1839, _T_1840) @[el2_lsu_bus_buffer.scala 400:91] + reg _T_1842 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 400:54] + _T_1842 <= _T_1841 @[el2_lsu_bus_buffer.scala 400:54] + obuf_valid <= _T_1842 @[el2_lsu_bus_buffer.scala 400:14] reg _T_1843 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when obuf_wr_en : @[Reg.scala 28:19] _T_1843 <= obuf_nosend_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - obuf_nosend <= _T_1843 @[el2_lsu_bus_buffer.scala 400:15] - reg _T_1844 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 401:54] - _T_1844 <= obuf_cmd_done_in @[el2_lsu_bus_buffer.scala 401:54] - obuf_cmd_done <= _T_1844 @[el2_lsu_bus_buffer.scala 401:17] - reg _T_1845 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 402:55] - _T_1845 <= obuf_data_done_in @[el2_lsu_bus_buffer.scala 402:55] - obuf_data_done <= _T_1845 @[el2_lsu_bus_buffer.scala 402:18] - reg _T_1846 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 403:56] - _T_1846 <= obuf_rdrsp_pend_in @[el2_lsu_bus_buffer.scala 403:56] - obuf_rdrsp_pend <= _T_1846 @[el2_lsu_bus_buffer.scala 403:19] - reg _T_1847 : UInt, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 404:55] - _T_1847 <= obuf_rdrsp_tag_in @[el2_lsu_bus_buffer.scala 404:55] - obuf_rdrsp_tag <= _T_1847 @[el2_lsu_bus_buffer.scala 404:18] + obuf_nosend <= _T_1843 @[el2_lsu_bus_buffer.scala 401:15] + reg _T_1844 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 402:54] + _T_1844 <= obuf_cmd_done_in @[el2_lsu_bus_buffer.scala 402:54] + obuf_cmd_done <= _T_1844 @[el2_lsu_bus_buffer.scala 402:17] + reg _T_1845 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 403:55] + _T_1845 <= obuf_data_done_in @[el2_lsu_bus_buffer.scala 403:55] + obuf_data_done <= _T_1845 @[el2_lsu_bus_buffer.scala 403:18] + reg _T_1846 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 404:56] + _T_1846 <= obuf_rdrsp_pend_in @[el2_lsu_bus_buffer.scala 404:56] + obuf_rdrsp_pend <= _T_1846 @[el2_lsu_bus_buffer.scala 404:19] + reg _T_1847 : UInt, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 405:55] + _T_1847 <= obuf_rdrsp_tag_in @[el2_lsu_bus_buffer.scala 405:55] + obuf_rdrsp_tag <= _T_1847 @[el2_lsu_bus_buffer.scala 405:18] reg _T_1848 : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when obuf_wr_en : @[Reg.scala 28:19] _T_1848 <= obuf_tag0_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - obuf_tag0 <= _T_1848 @[el2_lsu_bus_buffer.scala 405:13] + obuf_tag0 <= _T_1848 @[el2_lsu_bus_buffer.scala 406:13] reg obuf_tag1 : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when obuf_wr_en : @[Reg.scala 28:19] obuf_tag1 <= obuf_tag1_in @[Reg.scala 28:23] @@ -2628,12 +2628,12 @@ circuit el2_lsu_bus_intf : when obuf_wr_en : @[Reg.scala 28:19] _T_1849 <= obuf_write_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - obuf_write <= _T_1849 @[el2_lsu_bus_buffer.scala 408:14] + obuf_write <= _T_1849 @[el2_lsu_bus_buffer.scala 409:14] reg _T_1850 : UInt<1>, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when obuf_wr_en : @[Reg.scala 28:19] _T_1850 <= obuf_sideeffect_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - obuf_sideeffect <= _T_1850 @[el2_lsu_bus_buffer.scala 409:19] + obuf_sideeffect <= _T_1850 @[el2_lsu_bus_buffer.scala 410:19] reg obuf_sz : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when obuf_wr_en : @[Reg.scala 28:19] obuf_sz <= obuf_sz_in @[Reg.scala 28:23] @@ -2646,7 +2646,7 @@ circuit el2_lsu_bus_intf : rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_1851 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_1851 <= obuf_addr_in @[el2_lib.scala 514:16] - obuf_addr <= _T_1851 @[el2_lsu_bus_buffer.scala 411:13] + obuf_addr <= _T_1851 @[el2_lsu_bus_buffer.scala 412:13] reg obuf_byteen : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when obuf_wr_en : @[Reg.scala 28:19] obuf_byteen <= obuf_byteen_in @[Reg.scala 28:23] @@ -2659,1903 +2659,1901 @@ circuit el2_lsu_bus_intf : rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg obuf_data : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] obuf_data <= obuf_data_in @[el2_lib.scala 514:16] - reg _T_1852 : UInt, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 414:54] - _T_1852 <= obuf_wr_timer_in @[el2_lsu_bus_buffer.scala 414:54] - obuf_wr_timer <= _T_1852 @[el2_lsu_bus_buffer.scala 414:17] + reg _T_1852 : UInt, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 415:54] + _T_1852 <= obuf_wr_timer_in @[el2_lsu_bus_buffer.scala 415:54] + obuf_wr_timer <= _T_1852 @[el2_lsu_bus_buffer.scala 415:17] wire WrPtr0_m : UInt<2> WrPtr0_m <= UInt<1>("h00") - node _T_1853 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 417:65] - node _T_1854 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 418:30] - node _T_1855 = and(ibuf_valid, _T_1854) @[el2_lsu_bus_buffer.scala 418:19] - node _T_1856 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 419:18] - node _T_1857 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 419:57] - node _T_1858 = and(io.ldst_dual_r, _T_1857) @[el2_lsu_bus_buffer.scala 419:45] - node _T_1859 = or(_T_1856, _T_1858) @[el2_lsu_bus_buffer.scala 419:27] - node _T_1860 = and(io.lsu_busreq_r, _T_1859) @[el2_lsu_bus_buffer.scala 418:58] - node _T_1861 = or(_T_1855, _T_1860) @[el2_lsu_bus_buffer.scala 418:39] - node _T_1862 = eq(_T_1861, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 418:5] - node _T_1863 = and(_T_1853, _T_1862) @[el2_lsu_bus_buffer.scala 417:76] - node _T_1864 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 417:65] - node _T_1865 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 418:30] - node _T_1866 = and(ibuf_valid, _T_1865) @[el2_lsu_bus_buffer.scala 418:19] - node _T_1867 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 419:18] - node _T_1868 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 419:57] - node _T_1869 = and(io.ldst_dual_r, _T_1868) @[el2_lsu_bus_buffer.scala 419:45] - node _T_1870 = or(_T_1867, _T_1869) @[el2_lsu_bus_buffer.scala 419:27] - node _T_1871 = and(io.lsu_busreq_r, _T_1870) @[el2_lsu_bus_buffer.scala 418:58] - node _T_1872 = or(_T_1866, _T_1871) @[el2_lsu_bus_buffer.scala 418:39] - node _T_1873 = eq(_T_1872, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 418:5] - node _T_1874 = and(_T_1864, _T_1873) @[el2_lsu_bus_buffer.scala 417:76] - node _T_1875 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 417:65] - node _T_1876 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 418:30] - node _T_1877 = and(ibuf_valid, _T_1876) @[el2_lsu_bus_buffer.scala 418:19] - node _T_1878 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 419:18] - node _T_1879 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 419:57] - node _T_1880 = and(io.ldst_dual_r, _T_1879) @[el2_lsu_bus_buffer.scala 419:45] - node _T_1881 = or(_T_1878, _T_1880) @[el2_lsu_bus_buffer.scala 419:27] - node _T_1882 = and(io.lsu_busreq_r, _T_1881) @[el2_lsu_bus_buffer.scala 418:58] - node _T_1883 = or(_T_1877, _T_1882) @[el2_lsu_bus_buffer.scala 418:39] - node _T_1884 = eq(_T_1883, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 418:5] - node _T_1885 = and(_T_1875, _T_1884) @[el2_lsu_bus_buffer.scala 417:76] - node _T_1886 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 417:65] - node _T_1887 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 418:30] - node _T_1888 = and(ibuf_valid, _T_1887) @[el2_lsu_bus_buffer.scala 418:19] - node _T_1889 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 419:18] - node _T_1890 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 419:57] - node _T_1891 = and(io.ldst_dual_r, _T_1890) @[el2_lsu_bus_buffer.scala 419:45] - node _T_1892 = or(_T_1889, _T_1891) @[el2_lsu_bus_buffer.scala 419:27] - node _T_1893 = and(io.lsu_busreq_r, _T_1892) @[el2_lsu_bus_buffer.scala 418:58] - node _T_1894 = or(_T_1888, _T_1893) @[el2_lsu_bus_buffer.scala 418:39] - node _T_1895 = eq(_T_1894, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 418:5] - node _T_1896 = and(_T_1886, _T_1895) @[el2_lsu_bus_buffer.scala 417:76] + node _T_1853 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 418:65] + node _T_1854 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 419:30] + node _T_1855 = and(ibuf_valid, _T_1854) @[el2_lsu_bus_buffer.scala 419:19] + node _T_1856 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 420:18] + node _T_1857 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 420:57] + node _T_1858 = and(io.ldst_dual_r, _T_1857) @[el2_lsu_bus_buffer.scala 420:45] + node _T_1859 = or(_T_1856, _T_1858) @[el2_lsu_bus_buffer.scala 420:27] + node _T_1860 = and(io.lsu_busreq_r, _T_1859) @[el2_lsu_bus_buffer.scala 419:58] + node _T_1861 = or(_T_1855, _T_1860) @[el2_lsu_bus_buffer.scala 419:39] + node _T_1862 = eq(_T_1861, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 419:5] + node _T_1863 = and(_T_1853, _T_1862) @[el2_lsu_bus_buffer.scala 418:76] + node _T_1864 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 418:65] + node _T_1865 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 419:30] + node _T_1866 = and(ibuf_valid, _T_1865) @[el2_lsu_bus_buffer.scala 419:19] + node _T_1867 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 420:18] + node _T_1868 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 420:57] + node _T_1869 = and(io.ldst_dual_r, _T_1868) @[el2_lsu_bus_buffer.scala 420:45] + node _T_1870 = or(_T_1867, _T_1869) @[el2_lsu_bus_buffer.scala 420:27] + node _T_1871 = and(io.lsu_busreq_r, _T_1870) @[el2_lsu_bus_buffer.scala 419:58] + node _T_1872 = or(_T_1866, _T_1871) @[el2_lsu_bus_buffer.scala 419:39] + node _T_1873 = eq(_T_1872, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 419:5] + node _T_1874 = and(_T_1864, _T_1873) @[el2_lsu_bus_buffer.scala 418:76] + node _T_1875 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 418:65] + node _T_1876 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 419:30] + node _T_1877 = and(ibuf_valid, _T_1876) @[el2_lsu_bus_buffer.scala 419:19] + node _T_1878 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 420:18] + node _T_1879 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 420:57] + node _T_1880 = and(io.ldst_dual_r, _T_1879) @[el2_lsu_bus_buffer.scala 420:45] + node _T_1881 = or(_T_1878, _T_1880) @[el2_lsu_bus_buffer.scala 420:27] + node _T_1882 = and(io.lsu_busreq_r, _T_1881) @[el2_lsu_bus_buffer.scala 419:58] + node _T_1883 = or(_T_1877, _T_1882) @[el2_lsu_bus_buffer.scala 419:39] + node _T_1884 = eq(_T_1883, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 419:5] + node _T_1885 = and(_T_1875, _T_1884) @[el2_lsu_bus_buffer.scala 418:76] + node _T_1886 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 418:65] + node _T_1887 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 419:30] + node _T_1888 = and(ibuf_valid, _T_1887) @[el2_lsu_bus_buffer.scala 419:19] + node _T_1889 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 420:18] + node _T_1890 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 420:57] + node _T_1891 = and(io.ldst_dual_r, _T_1890) @[el2_lsu_bus_buffer.scala 420:45] + node _T_1892 = or(_T_1889, _T_1891) @[el2_lsu_bus_buffer.scala 420:27] + node _T_1893 = and(io.lsu_busreq_r, _T_1892) @[el2_lsu_bus_buffer.scala 419:58] + node _T_1894 = or(_T_1888, _T_1893) @[el2_lsu_bus_buffer.scala 419:39] + node _T_1895 = eq(_T_1894, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 419:5] + node _T_1896 = and(_T_1886, _T_1895) @[el2_lsu_bus_buffer.scala 418:76] node _T_1897 = mux(_T_1896, UInt<2>("h03"), UInt<2>("h03")) @[Mux.scala 98:16] node _T_1898 = mux(_T_1885, UInt<2>("h02"), _T_1897) @[Mux.scala 98:16] node _T_1899 = mux(_T_1874, UInt<1>("h01"), _T_1898) @[Mux.scala 98:16] node _T_1900 = mux(_T_1863, UInt<1>("h00"), _T_1899) @[Mux.scala 98:16] - WrPtr0_m <= _T_1900 @[el2_lsu_bus_buffer.scala 417:12] + WrPtr0_m <= _T_1900 @[el2_lsu_bus_buffer.scala 418:12] wire WrPtr1_m : UInt<2> WrPtr1_m <= UInt<1>("h00") - node _T_1901 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 423:65] - node _T_1902 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 423:103] - node _T_1903 = and(ibuf_valid, _T_1902) @[el2_lsu_bus_buffer.scala 423:92] - node _T_1904 = eq(WrPtr0_m, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 424:33] - node _T_1905 = and(io.lsu_busreq_m, _T_1904) @[el2_lsu_bus_buffer.scala 424:22] - node _T_1906 = or(_T_1903, _T_1905) @[el2_lsu_bus_buffer.scala 423:112] - node _T_1907 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 425:36] - node _T_1908 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 426:34] - node _T_1909 = and(io.ldst_dual_r, _T_1908) @[el2_lsu_bus_buffer.scala 426:23] - node _T_1910 = or(_T_1907, _T_1909) @[el2_lsu_bus_buffer.scala 425:46] - node _T_1911 = and(io.lsu_busreq_r, _T_1910) @[el2_lsu_bus_buffer.scala 425:22] - node _T_1912 = or(_T_1906, _T_1911) @[el2_lsu_bus_buffer.scala 424:42] - node _T_1913 = eq(_T_1912, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 423:78] - node _T_1914 = and(_T_1901, _T_1913) @[el2_lsu_bus_buffer.scala 423:76] - node _T_1915 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 423:65] - node _T_1916 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 423:103] - node _T_1917 = and(ibuf_valid, _T_1916) @[el2_lsu_bus_buffer.scala 423:92] - node _T_1918 = eq(WrPtr0_m, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 424:33] - node _T_1919 = and(io.lsu_busreq_m, _T_1918) @[el2_lsu_bus_buffer.scala 424:22] - node _T_1920 = or(_T_1917, _T_1919) @[el2_lsu_bus_buffer.scala 423:112] - node _T_1921 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 425:36] - node _T_1922 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 426:34] - node _T_1923 = and(io.ldst_dual_r, _T_1922) @[el2_lsu_bus_buffer.scala 426:23] - node _T_1924 = or(_T_1921, _T_1923) @[el2_lsu_bus_buffer.scala 425:46] - node _T_1925 = and(io.lsu_busreq_r, _T_1924) @[el2_lsu_bus_buffer.scala 425:22] - node _T_1926 = or(_T_1920, _T_1925) @[el2_lsu_bus_buffer.scala 424:42] - node _T_1927 = eq(_T_1926, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 423:78] - node _T_1928 = and(_T_1915, _T_1927) @[el2_lsu_bus_buffer.scala 423:76] - node _T_1929 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 423:65] - node _T_1930 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 423:103] - node _T_1931 = and(ibuf_valid, _T_1930) @[el2_lsu_bus_buffer.scala 423:92] - node _T_1932 = eq(WrPtr0_m, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 424:33] - node _T_1933 = and(io.lsu_busreq_m, _T_1932) @[el2_lsu_bus_buffer.scala 424:22] - node _T_1934 = or(_T_1931, _T_1933) @[el2_lsu_bus_buffer.scala 423:112] - node _T_1935 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 425:36] - node _T_1936 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 426:34] - node _T_1937 = and(io.ldst_dual_r, _T_1936) @[el2_lsu_bus_buffer.scala 426:23] - node _T_1938 = or(_T_1935, _T_1937) @[el2_lsu_bus_buffer.scala 425:46] - node _T_1939 = and(io.lsu_busreq_r, _T_1938) @[el2_lsu_bus_buffer.scala 425:22] - node _T_1940 = or(_T_1934, _T_1939) @[el2_lsu_bus_buffer.scala 424:42] - node _T_1941 = eq(_T_1940, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 423:78] - node _T_1942 = and(_T_1929, _T_1941) @[el2_lsu_bus_buffer.scala 423:76] - node _T_1943 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 423:65] - node _T_1944 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 423:103] - node _T_1945 = and(ibuf_valid, _T_1944) @[el2_lsu_bus_buffer.scala 423:92] - node _T_1946 = eq(WrPtr0_m, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 424:33] - node _T_1947 = and(io.lsu_busreq_m, _T_1946) @[el2_lsu_bus_buffer.scala 424:22] - node _T_1948 = or(_T_1945, _T_1947) @[el2_lsu_bus_buffer.scala 423:112] - node _T_1949 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 425:36] - node _T_1950 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 426:34] - node _T_1951 = and(io.ldst_dual_r, _T_1950) @[el2_lsu_bus_buffer.scala 426:23] - node _T_1952 = or(_T_1949, _T_1951) @[el2_lsu_bus_buffer.scala 425:46] - node _T_1953 = and(io.lsu_busreq_r, _T_1952) @[el2_lsu_bus_buffer.scala 425:22] - node _T_1954 = or(_T_1948, _T_1953) @[el2_lsu_bus_buffer.scala 424:42] - node _T_1955 = eq(_T_1954, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 423:78] - node _T_1956 = and(_T_1943, _T_1955) @[el2_lsu_bus_buffer.scala 423:76] + node _T_1901 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 424:65] + node _T_1902 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 424:103] + node _T_1903 = and(ibuf_valid, _T_1902) @[el2_lsu_bus_buffer.scala 424:92] + node _T_1904 = eq(WrPtr0_m, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 425:33] + node _T_1905 = and(io.lsu_busreq_m, _T_1904) @[el2_lsu_bus_buffer.scala 425:22] + node _T_1906 = or(_T_1903, _T_1905) @[el2_lsu_bus_buffer.scala 424:112] + node _T_1907 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 426:36] + node _T_1908 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 427:34] + node _T_1909 = and(io.ldst_dual_r, _T_1908) @[el2_lsu_bus_buffer.scala 427:23] + node _T_1910 = or(_T_1907, _T_1909) @[el2_lsu_bus_buffer.scala 426:46] + node _T_1911 = and(io.lsu_busreq_r, _T_1910) @[el2_lsu_bus_buffer.scala 426:22] + node _T_1912 = or(_T_1906, _T_1911) @[el2_lsu_bus_buffer.scala 425:42] + node _T_1913 = eq(_T_1912, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 424:78] + node _T_1914 = and(_T_1901, _T_1913) @[el2_lsu_bus_buffer.scala 424:76] + node _T_1915 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 424:65] + node _T_1916 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 424:103] + node _T_1917 = and(ibuf_valid, _T_1916) @[el2_lsu_bus_buffer.scala 424:92] + node _T_1918 = eq(WrPtr0_m, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 425:33] + node _T_1919 = and(io.lsu_busreq_m, _T_1918) @[el2_lsu_bus_buffer.scala 425:22] + node _T_1920 = or(_T_1917, _T_1919) @[el2_lsu_bus_buffer.scala 424:112] + node _T_1921 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 426:36] + node _T_1922 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 427:34] + node _T_1923 = and(io.ldst_dual_r, _T_1922) @[el2_lsu_bus_buffer.scala 427:23] + node _T_1924 = or(_T_1921, _T_1923) @[el2_lsu_bus_buffer.scala 426:46] + node _T_1925 = and(io.lsu_busreq_r, _T_1924) @[el2_lsu_bus_buffer.scala 426:22] + node _T_1926 = or(_T_1920, _T_1925) @[el2_lsu_bus_buffer.scala 425:42] + node _T_1927 = eq(_T_1926, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 424:78] + node _T_1928 = and(_T_1915, _T_1927) @[el2_lsu_bus_buffer.scala 424:76] + node _T_1929 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 424:65] + node _T_1930 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 424:103] + node _T_1931 = and(ibuf_valid, _T_1930) @[el2_lsu_bus_buffer.scala 424:92] + node _T_1932 = eq(WrPtr0_m, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 425:33] + node _T_1933 = and(io.lsu_busreq_m, _T_1932) @[el2_lsu_bus_buffer.scala 425:22] + node _T_1934 = or(_T_1931, _T_1933) @[el2_lsu_bus_buffer.scala 424:112] + node _T_1935 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 426:36] + node _T_1936 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 427:34] + node _T_1937 = and(io.ldst_dual_r, _T_1936) @[el2_lsu_bus_buffer.scala 427:23] + node _T_1938 = or(_T_1935, _T_1937) @[el2_lsu_bus_buffer.scala 426:46] + node _T_1939 = and(io.lsu_busreq_r, _T_1938) @[el2_lsu_bus_buffer.scala 426:22] + node _T_1940 = or(_T_1934, _T_1939) @[el2_lsu_bus_buffer.scala 425:42] + node _T_1941 = eq(_T_1940, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 424:78] + node _T_1942 = and(_T_1929, _T_1941) @[el2_lsu_bus_buffer.scala 424:76] + node _T_1943 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 424:65] + node _T_1944 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 424:103] + node _T_1945 = and(ibuf_valid, _T_1944) @[el2_lsu_bus_buffer.scala 424:92] + node _T_1946 = eq(WrPtr0_m, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 425:33] + node _T_1947 = and(io.lsu_busreq_m, _T_1946) @[el2_lsu_bus_buffer.scala 425:22] + node _T_1948 = or(_T_1945, _T_1947) @[el2_lsu_bus_buffer.scala 424:112] + node _T_1949 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 426:36] + node _T_1950 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 427:34] + node _T_1951 = and(io.ldst_dual_r, _T_1950) @[el2_lsu_bus_buffer.scala 427:23] + node _T_1952 = or(_T_1949, _T_1951) @[el2_lsu_bus_buffer.scala 426:46] + node _T_1953 = and(io.lsu_busreq_r, _T_1952) @[el2_lsu_bus_buffer.scala 426:22] + node _T_1954 = or(_T_1948, _T_1953) @[el2_lsu_bus_buffer.scala 425:42] + node _T_1955 = eq(_T_1954, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 424:78] + node _T_1956 = and(_T_1943, _T_1955) @[el2_lsu_bus_buffer.scala 424:76] node _T_1957 = mux(_T_1956, UInt<2>("h03"), UInt<2>("h03")) @[Mux.scala 98:16] node _T_1958 = mux(_T_1942, UInt<2>("h02"), _T_1957) @[Mux.scala 98:16] node _T_1959 = mux(_T_1928, UInt<1>("h01"), _T_1958) @[Mux.scala 98:16] node _T_1960 = mux(_T_1914, UInt<1>("h00"), _T_1959) @[Mux.scala 98:16] - WrPtr1_m <= _T_1960 @[el2_lsu_bus_buffer.scala 423:12] - wire buf_age : UInt<4>[4] @[el2_lsu_bus_buffer.scala 428:21] - buf_age[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 429:11] - buf_age[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 429:11] - buf_age[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 429:11] - buf_age[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 429:11] - node _T_1961 = orr(buf_age[0]) @[el2_lsu_bus_buffer.scala 431:58] - node _T_1962 = eq(_T_1961, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 431:45] - node _T_1963 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 431:78] - node _T_1964 = and(_T_1962, _T_1963) @[el2_lsu_bus_buffer.scala 431:63] - node _T_1965 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 431:90] - node _T_1966 = and(_T_1964, _T_1965) @[el2_lsu_bus_buffer.scala 431:88] - node _T_1967 = orr(buf_age[1]) @[el2_lsu_bus_buffer.scala 431:58] - node _T_1968 = eq(_T_1967, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 431:45] - node _T_1969 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 431:78] - node _T_1970 = and(_T_1968, _T_1969) @[el2_lsu_bus_buffer.scala 431:63] - node _T_1971 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 431:90] - node _T_1972 = and(_T_1970, _T_1971) @[el2_lsu_bus_buffer.scala 431:88] - node _T_1973 = orr(buf_age[2]) @[el2_lsu_bus_buffer.scala 431:58] - node _T_1974 = eq(_T_1973, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 431:45] - node _T_1975 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 431:78] - node _T_1976 = and(_T_1974, _T_1975) @[el2_lsu_bus_buffer.scala 431:63] - node _T_1977 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 431:90] - node _T_1978 = and(_T_1976, _T_1977) @[el2_lsu_bus_buffer.scala 431:88] - node _T_1979 = orr(buf_age[3]) @[el2_lsu_bus_buffer.scala 431:58] - node _T_1980 = eq(_T_1979, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 431:45] - node _T_1981 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 431:78] - node _T_1982 = and(_T_1980, _T_1981) @[el2_lsu_bus_buffer.scala 431:63] - node _T_1983 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 431:90] - node _T_1984 = and(_T_1982, _T_1983) @[el2_lsu_bus_buffer.scala 431:88] + WrPtr1_m <= _T_1960 @[el2_lsu_bus_buffer.scala 424:12] + wire buf_age : UInt<4>[4] @[el2_lsu_bus_buffer.scala 429:21] + buf_age[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 430:11] + buf_age[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 430:11] + buf_age[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 430:11] + buf_age[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 430:11] + node _T_1961 = orr(buf_age[0]) @[el2_lsu_bus_buffer.scala 432:58] + node _T_1962 = eq(_T_1961, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 432:45] + node _T_1963 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 432:78] + node _T_1964 = and(_T_1962, _T_1963) @[el2_lsu_bus_buffer.scala 432:63] + node _T_1965 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 432:90] + node _T_1966 = and(_T_1964, _T_1965) @[el2_lsu_bus_buffer.scala 432:88] + node _T_1967 = orr(buf_age[1]) @[el2_lsu_bus_buffer.scala 432:58] + node _T_1968 = eq(_T_1967, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 432:45] + node _T_1969 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 432:78] + node _T_1970 = and(_T_1968, _T_1969) @[el2_lsu_bus_buffer.scala 432:63] + node _T_1971 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 432:90] + node _T_1972 = and(_T_1970, _T_1971) @[el2_lsu_bus_buffer.scala 432:88] + node _T_1973 = orr(buf_age[2]) @[el2_lsu_bus_buffer.scala 432:58] + node _T_1974 = eq(_T_1973, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 432:45] + node _T_1975 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 432:78] + node _T_1976 = and(_T_1974, _T_1975) @[el2_lsu_bus_buffer.scala 432:63] + node _T_1977 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 432:90] + node _T_1978 = and(_T_1976, _T_1977) @[el2_lsu_bus_buffer.scala 432:88] + node _T_1979 = orr(buf_age[3]) @[el2_lsu_bus_buffer.scala 432:58] + node _T_1980 = eq(_T_1979, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 432:45] + node _T_1981 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 432:78] + node _T_1982 = and(_T_1980, _T_1981) @[el2_lsu_bus_buffer.scala 432:63] + node _T_1983 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 432:90] + node _T_1984 = and(_T_1982, _T_1983) @[el2_lsu_bus_buffer.scala 432:88] node _T_1985 = cat(_T_1984, _T_1978) @[Cat.scala 29:58] node _T_1986 = cat(_T_1985, _T_1972) @[Cat.scala 29:58] node CmdPtr0Dec = cat(_T_1986, _T_1966) @[Cat.scala 29:58] - node _T_1987 = not(CmdPtr0Dec) @[el2_lsu_bus_buffer.scala 432:62] - node _T_1988 = and(buf_age[0], _T_1987) @[el2_lsu_bus_buffer.scala 432:59] - node _T_1989 = orr(_T_1988) @[el2_lsu_bus_buffer.scala 432:76] - node _T_1990 = eq(_T_1989, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 432:45] - node _T_1991 = bits(CmdPtr0Dec, 0, 0) @[el2_lsu_bus_buffer.scala 432:94] - node _T_1992 = eq(_T_1991, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 432:83] - node _T_1993 = and(_T_1990, _T_1992) @[el2_lsu_bus_buffer.scala 432:81] - node _T_1994 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 432:113] - node _T_1995 = and(_T_1993, _T_1994) @[el2_lsu_bus_buffer.scala 432:98] - node _T_1996 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 432:125] - node _T_1997 = and(_T_1995, _T_1996) @[el2_lsu_bus_buffer.scala 432:123] - node _T_1998 = not(CmdPtr0Dec) @[el2_lsu_bus_buffer.scala 432:62] - node _T_1999 = and(buf_age[1], _T_1998) @[el2_lsu_bus_buffer.scala 432:59] - node _T_2000 = orr(_T_1999) @[el2_lsu_bus_buffer.scala 432:76] - node _T_2001 = eq(_T_2000, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 432:45] - node _T_2002 = bits(CmdPtr0Dec, 1, 1) @[el2_lsu_bus_buffer.scala 432:94] - node _T_2003 = eq(_T_2002, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 432:83] - node _T_2004 = and(_T_2001, _T_2003) @[el2_lsu_bus_buffer.scala 432:81] - node _T_2005 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 432:113] - node _T_2006 = and(_T_2004, _T_2005) @[el2_lsu_bus_buffer.scala 432:98] - node _T_2007 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 432:125] - node _T_2008 = and(_T_2006, _T_2007) @[el2_lsu_bus_buffer.scala 432:123] - node _T_2009 = not(CmdPtr0Dec) @[el2_lsu_bus_buffer.scala 432:62] - node _T_2010 = and(buf_age[2], _T_2009) @[el2_lsu_bus_buffer.scala 432:59] - node _T_2011 = orr(_T_2010) @[el2_lsu_bus_buffer.scala 432:76] - node _T_2012 = eq(_T_2011, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 432:45] - node _T_2013 = bits(CmdPtr0Dec, 2, 2) @[el2_lsu_bus_buffer.scala 432:94] - node _T_2014 = eq(_T_2013, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 432:83] - node _T_2015 = and(_T_2012, _T_2014) @[el2_lsu_bus_buffer.scala 432:81] - node _T_2016 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 432:113] - node _T_2017 = and(_T_2015, _T_2016) @[el2_lsu_bus_buffer.scala 432:98] - node _T_2018 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 432:125] - node _T_2019 = and(_T_2017, _T_2018) @[el2_lsu_bus_buffer.scala 432:123] - node _T_2020 = not(CmdPtr0Dec) @[el2_lsu_bus_buffer.scala 432:62] - node _T_2021 = and(buf_age[3], _T_2020) @[el2_lsu_bus_buffer.scala 432:59] - node _T_2022 = orr(_T_2021) @[el2_lsu_bus_buffer.scala 432:76] - node _T_2023 = eq(_T_2022, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 432:45] - node _T_2024 = bits(CmdPtr0Dec, 3, 3) @[el2_lsu_bus_buffer.scala 432:94] - node _T_2025 = eq(_T_2024, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 432:83] - node _T_2026 = and(_T_2023, _T_2025) @[el2_lsu_bus_buffer.scala 432:81] - node _T_2027 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 432:113] - node _T_2028 = and(_T_2026, _T_2027) @[el2_lsu_bus_buffer.scala 432:98] - node _T_2029 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 432:125] - node _T_2030 = and(_T_2028, _T_2029) @[el2_lsu_bus_buffer.scala 432:123] + node _T_1987 = not(CmdPtr0Dec) @[el2_lsu_bus_buffer.scala 433:62] + node _T_1988 = and(buf_age[0], _T_1987) @[el2_lsu_bus_buffer.scala 433:59] + node _T_1989 = orr(_T_1988) @[el2_lsu_bus_buffer.scala 433:76] + node _T_1990 = eq(_T_1989, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 433:45] + node _T_1991 = bits(CmdPtr0Dec, 0, 0) @[el2_lsu_bus_buffer.scala 433:94] + node _T_1992 = eq(_T_1991, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 433:83] + node _T_1993 = and(_T_1990, _T_1992) @[el2_lsu_bus_buffer.scala 433:81] + node _T_1994 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 433:113] + node _T_1995 = and(_T_1993, _T_1994) @[el2_lsu_bus_buffer.scala 433:98] + node _T_1996 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 433:125] + node _T_1997 = and(_T_1995, _T_1996) @[el2_lsu_bus_buffer.scala 433:123] + node _T_1998 = not(CmdPtr0Dec) @[el2_lsu_bus_buffer.scala 433:62] + node _T_1999 = and(buf_age[1], _T_1998) @[el2_lsu_bus_buffer.scala 433:59] + node _T_2000 = orr(_T_1999) @[el2_lsu_bus_buffer.scala 433:76] + node _T_2001 = eq(_T_2000, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 433:45] + node _T_2002 = bits(CmdPtr0Dec, 1, 1) @[el2_lsu_bus_buffer.scala 433:94] + node _T_2003 = eq(_T_2002, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 433:83] + node _T_2004 = and(_T_2001, _T_2003) @[el2_lsu_bus_buffer.scala 433:81] + node _T_2005 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 433:113] + node _T_2006 = and(_T_2004, _T_2005) @[el2_lsu_bus_buffer.scala 433:98] + node _T_2007 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 433:125] + node _T_2008 = and(_T_2006, _T_2007) @[el2_lsu_bus_buffer.scala 433:123] + node _T_2009 = not(CmdPtr0Dec) @[el2_lsu_bus_buffer.scala 433:62] + node _T_2010 = and(buf_age[2], _T_2009) @[el2_lsu_bus_buffer.scala 433:59] + node _T_2011 = orr(_T_2010) @[el2_lsu_bus_buffer.scala 433:76] + node _T_2012 = eq(_T_2011, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 433:45] + node _T_2013 = bits(CmdPtr0Dec, 2, 2) @[el2_lsu_bus_buffer.scala 433:94] + node _T_2014 = eq(_T_2013, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 433:83] + node _T_2015 = and(_T_2012, _T_2014) @[el2_lsu_bus_buffer.scala 433:81] + node _T_2016 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 433:113] + node _T_2017 = and(_T_2015, _T_2016) @[el2_lsu_bus_buffer.scala 433:98] + node _T_2018 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 433:125] + node _T_2019 = and(_T_2017, _T_2018) @[el2_lsu_bus_buffer.scala 433:123] + node _T_2020 = not(CmdPtr0Dec) @[el2_lsu_bus_buffer.scala 433:62] + node _T_2021 = and(buf_age[3], _T_2020) @[el2_lsu_bus_buffer.scala 433:59] + node _T_2022 = orr(_T_2021) @[el2_lsu_bus_buffer.scala 433:76] + node _T_2023 = eq(_T_2022, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 433:45] + node _T_2024 = bits(CmdPtr0Dec, 3, 3) @[el2_lsu_bus_buffer.scala 433:94] + node _T_2025 = eq(_T_2024, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 433:83] + node _T_2026 = and(_T_2023, _T_2025) @[el2_lsu_bus_buffer.scala 433:81] + node _T_2027 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 433:113] + node _T_2028 = and(_T_2026, _T_2027) @[el2_lsu_bus_buffer.scala 433:98] + node _T_2029 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 433:125] + node _T_2030 = and(_T_2028, _T_2029) @[el2_lsu_bus_buffer.scala 433:123] node _T_2031 = cat(_T_2030, _T_2019) @[Cat.scala 29:58] node _T_2032 = cat(_T_2031, _T_2008) @[Cat.scala 29:58] node CmdPtr1Dec = cat(_T_2032, _T_1997) @[Cat.scala 29:58] - wire buf_rsp_pickage : UInt<4>[4] @[el2_lsu_bus_buffer.scala 433:29] - buf_rsp_pickage[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 434:19] - buf_rsp_pickage[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 434:19] - buf_rsp_pickage[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 434:19] - buf_rsp_pickage[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 434:19] - node _T_2033 = orr(buf_rsp_pickage[0]) @[el2_lsu_bus_buffer.scala 435:65] - node _T_2034 = eq(_T_2033, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 435:44] - node _T_2035 = eq(buf_state[0], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 435:85] - node _T_2036 = and(_T_2034, _T_2035) @[el2_lsu_bus_buffer.scala 435:70] - node _T_2037 = orr(buf_rsp_pickage[1]) @[el2_lsu_bus_buffer.scala 435:65] - node _T_2038 = eq(_T_2037, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 435:44] - node _T_2039 = eq(buf_state[1], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 435:85] - node _T_2040 = and(_T_2038, _T_2039) @[el2_lsu_bus_buffer.scala 435:70] - node _T_2041 = orr(buf_rsp_pickage[2]) @[el2_lsu_bus_buffer.scala 435:65] - node _T_2042 = eq(_T_2041, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 435:44] - node _T_2043 = eq(buf_state[2], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 435:85] - node _T_2044 = and(_T_2042, _T_2043) @[el2_lsu_bus_buffer.scala 435:70] - node _T_2045 = orr(buf_rsp_pickage[3]) @[el2_lsu_bus_buffer.scala 435:65] - node _T_2046 = eq(_T_2045, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 435:44] - node _T_2047 = eq(buf_state[3], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 435:85] - node _T_2048 = and(_T_2046, _T_2047) @[el2_lsu_bus_buffer.scala 435:70] + wire buf_rsp_pickage : UInt<4>[4] @[el2_lsu_bus_buffer.scala 434:29] + buf_rsp_pickage[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 435:19] + buf_rsp_pickage[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 435:19] + buf_rsp_pickage[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 435:19] + buf_rsp_pickage[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 435:19] + node _T_2033 = orr(buf_rsp_pickage[0]) @[el2_lsu_bus_buffer.scala 436:65] + node _T_2034 = eq(_T_2033, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 436:44] + node _T_2035 = eq(buf_state[0], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 436:85] + node _T_2036 = and(_T_2034, _T_2035) @[el2_lsu_bus_buffer.scala 436:70] + node _T_2037 = orr(buf_rsp_pickage[1]) @[el2_lsu_bus_buffer.scala 436:65] + node _T_2038 = eq(_T_2037, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 436:44] + node _T_2039 = eq(buf_state[1], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 436:85] + node _T_2040 = and(_T_2038, _T_2039) @[el2_lsu_bus_buffer.scala 436:70] + node _T_2041 = orr(buf_rsp_pickage[2]) @[el2_lsu_bus_buffer.scala 436:65] + node _T_2042 = eq(_T_2041, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 436:44] + node _T_2043 = eq(buf_state[2], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 436:85] + node _T_2044 = and(_T_2042, _T_2043) @[el2_lsu_bus_buffer.scala 436:70] + node _T_2045 = orr(buf_rsp_pickage[3]) @[el2_lsu_bus_buffer.scala 436:65] + node _T_2046 = eq(_T_2045, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 436:44] + node _T_2047 = eq(buf_state[3], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 436:85] + node _T_2048 = and(_T_2046, _T_2047) @[el2_lsu_bus_buffer.scala 436:70] node _T_2049 = cat(_T_2048, _T_2044) @[Cat.scala 29:58] node _T_2050 = cat(_T_2049, _T_2040) @[Cat.scala 29:58] node RspPtrDec = cat(_T_2050, _T_2036) @[Cat.scala 29:58] - node _T_2051 = orr(CmdPtr0Dec) @[el2_lsu_bus_buffer.scala 436:31] - found_cmdptr0 <= _T_2051 @[el2_lsu_bus_buffer.scala 436:17] - node _T_2052 = orr(CmdPtr1Dec) @[el2_lsu_bus_buffer.scala 437:31] - found_cmdptr1 <= _T_2052 @[el2_lsu_bus_buffer.scala 437:17] - wire CmdPtr1 : UInt<2> - CmdPtr1 <= UInt<1>("h00") + node _T_2051 = orr(CmdPtr0Dec) @[el2_lsu_bus_buffer.scala 437:31] + found_cmdptr0 <= _T_2051 @[el2_lsu_bus_buffer.scala 437:17] + node _T_2052 = orr(CmdPtr1Dec) @[el2_lsu_bus_buffer.scala 438:31] + found_cmdptr1 <= _T_2052 @[el2_lsu_bus_buffer.scala 438:17] wire RspPtr : UInt<2> RspPtr <= UInt<1>("h00") node _T_2053 = mux(UInt<1>("h00"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] node _T_2054 = cat(_T_2053, CmdPtr0Dec) @[Cat.scala 29:58] - node _T_2055 = bits(_T_2054, 4, 4) @[el2_lsu_bus_buffer.scala 439:39] - node _T_2056 = bits(_T_2054, 5, 5) @[el2_lsu_bus_buffer.scala 439:45] - node _T_2057 = or(_T_2055, _T_2056) @[el2_lsu_bus_buffer.scala 439:42] - node _T_2058 = bits(_T_2054, 6, 6) @[el2_lsu_bus_buffer.scala 439:51] - node _T_2059 = or(_T_2057, _T_2058) @[el2_lsu_bus_buffer.scala 439:48] - node _T_2060 = bits(_T_2054, 7, 7) @[el2_lsu_bus_buffer.scala 439:57] - node _T_2061 = or(_T_2059, _T_2060) @[el2_lsu_bus_buffer.scala 439:54] - node _T_2062 = bits(_T_2054, 2, 2) @[el2_lsu_bus_buffer.scala 439:64] - node _T_2063 = bits(_T_2054, 3, 3) @[el2_lsu_bus_buffer.scala 439:70] - node _T_2064 = or(_T_2062, _T_2063) @[el2_lsu_bus_buffer.scala 439:67] - node _T_2065 = bits(_T_2054, 6, 6) @[el2_lsu_bus_buffer.scala 439:76] - node _T_2066 = or(_T_2064, _T_2065) @[el2_lsu_bus_buffer.scala 439:73] - node _T_2067 = bits(_T_2054, 7, 7) @[el2_lsu_bus_buffer.scala 439:82] - node _T_2068 = or(_T_2066, _T_2067) @[el2_lsu_bus_buffer.scala 439:79] - node _T_2069 = bits(_T_2054, 1, 1) @[el2_lsu_bus_buffer.scala 439:89] - node _T_2070 = bits(_T_2054, 3, 3) @[el2_lsu_bus_buffer.scala 439:95] - node _T_2071 = or(_T_2069, _T_2070) @[el2_lsu_bus_buffer.scala 439:92] - node _T_2072 = bits(_T_2054, 5, 5) @[el2_lsu_bus_buffer.scala 439:101] - node _T_2073 = or(_T_2071, _T_2072) @[el2_lsu_bus_buffer.scala 439:98] - node _T_2074 = bits(_T_2054, 7, 7) @[el2_lsu_bus_buffer.scala 439:107] - node _T_2075 = or(_T_2073, _T_2074) @[el2_lsu_bus_buffer.scala 439:104] + node _T_2055 = bits(_T_2054, 4, 4) @[el2_lsu_bus_buffer.scala 440:39] + node _T_2056 = bits(_T_2054, 5, 5) @[el2_lsu_bus_buffer.scala 440:45] + node _T_2057 = or(_T_2055, _T_2056) @[el2_lsu_bus_buffer.scala 440:42] + node _T_2058 = bits(_T_2054, 6, 6) @[el2_lsu_bus_buffer.scala 440:51] + node _T_2059 = or(_T_2057, _T_2058) @[el2_lsu_bus_buffer.scala 440:48] + node _T_2060 = bits(_T_2054, 7, 7) @[el2_lsu_bus_buffer.scala 440:57] + node _T_2061 = or(_T_2059, _T_2060) @[el2_lsu_bus_buffer.scala 440:54] + node _T_2062 = bits(_T_2054, 2, 2) @[el2_lsu_bus_buffer.scala 440:64] + node _T_2063 = bits(_T_2054, 3, 3) @[el2_lsu_bus_buffer.scala 440:70] + node _T_2064 = or(_T_2062, _T_2063) @[el2_lsu_bus_buffer.scala 440:67] + node _T_2065 = bits(_T_2054, 6, 6) @[el2_lsu_bus_buffer.scala 440:76] + node _T_2066 = or(_T_2064, _T_2065) @[el2_lsu_bus_buffer.scala 440:73] + node _T_2067 = bits(_T_2054, 7, 7) @[el2_lsu_bus_buffer.scala 440:82] + node _T_2068 = or(_T_2066, _T_2067) @[el2_lsu_bus_buffer.scala 440:79] + node _T_2069 = bits(_T_2054, 1, 1) @[el2_lsu_bus_buffer.scala 440:89] + node _T_2070 = bits(_T_2054, 3, 3) @[el2_lsu_bus_buffer.scala 440:95] + node _T_2071 = or(_T_2069, _T_2070) @[el2_lsu_bus_buffer.scala 440:92] + node _T_2072 = bits(_T_2054, 5, 5) @[el2_lsu_bus_buffer.scala 440:101] + node _T_2073 = or(_T_2071, _T_2072) @[el2_lsu_bus_buffer.scala 440:98] + node _T_2074 = bits(_T_2054, 7, 7) @[el2_lsu_bus_buffer.scala 440:107] + node _T_2075 = or(_T_2073, _T_2074) @[el2_lsu_bus_buffer.scala 440:104] node _T_2076 = cat(_T_2061, _T_2068) @[Cat.scala 29:58] node _T_2077 = cat(_T_2076, _T_2075) @[Cat.scala 29:58] - CmdPtr0 <= _T_2077 @[el2_lsu_bus_buffer.scala 444:11] + CmdPtr0 <= _T_2077 @[el2_lsu_bus_buffer.scala 445:11] node _T_2078 = mux(UInt<1>("h00"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] node _T_2079 = cat(_T_2078, CmdPtr1Dec) @[Cat.scala 29:58] - node _T_2080 = bits(_T_2079, 4, 4) @[el2_lsu_bus_buffer.scala 439:39] - node _T_2081 = bits(_T_2079, 5, 5) @[el2_lsu_bus_buffer.scala 439:45] - node _T_2082 = or(_T_2080, _T_2081) @[el2_lsu_bus_buffer.scala 439:42] - node _T_2083 = bits(_T_2079, 6, 6) @[el2_lsu_bus_buffer.scala 439:51] - node _T_2084 = or(_T_2082, _T_2083) @[el2_lsu_bus_buffer.scala 439:48] - node _T_2085 = bits(_T_2079, 7, 7) @[el2_lsu_bus_buffer.scala 439:57] - node _T_2086 = or(_T_2084, _T_2085) @[el2_lsu_bus_buffer.scala 439:54] - node _T_2087 = bits(_T_2079, 2, 2) @[el2_lsu_bus_buffer.scala 439:64] - node _T_2088 = bits(_T_2079, 3, 3) @[el2_lsu_bus_buffer.scala 439:70] - node _T_2089 = or(_T_2087, _T_2088) @[el2_lsu_bus_buffer.scala 439:67] - node _T_2090 = bits(_T_2079, 6, 6) @[el2_lsu_bus_buffer.scala 439:76] - node _T_2091 = or(_T_2089, _T_2090) @[el2_lsu_bus_buffer.scala 439:73] - node _T_2092 = bits(_T_2079, 7, 7) @[el2_lsu_bus_buffer.scala 439:82] - node _T_2093 = or(_T_2091, _T_2092) @[el2_lsu_bus_buffer.scala 439:79] - node _T_2094 = bits(_T_2079, 1, 1) @[el2_lsu_bus_buffer.scala 439:89] - node _T_2095 = bits(_T_2079, 3, 3) @[el2_lsu_bus_buffer.scala 439:95] - node _T_2096 = or(_T_2094, _T_2095) @[el2_lsu_bus_buffer.scala 439:92] - node _T_2097 = bits(_T_2079, 5, 5) @[el2_lsu_bus_buffer.scala 439:101] - node _T_2098 = or(_T_2096, _T_2097) @[el2_lsu_bus_buffer.scala 439:98] - node _T_2099 = bits(_T_2079, 7, 7) @[el2_lsu_bus_buffer.scala 439:107] - node _T_2100 = or(_T_2098, _T_2099) @[el2_lsu_bus_buffer.scala 439:104] + node _T_2080 = bits(_T_2079, 4, 4) @[el2_lsu_bus_buffer.scala 440:39] + node _T_2081 = bits(_T_2079, 5, 5) @[el2_lsu_bus_buffer.scala 440:45] + node _T_2082 = or(_T_2080, _T_2081) @[el2_lsu_bus_buffer.scala 440:42] + node _T_2083 = bits(_T_2079, 6, 6) @[el2_lsu_bus_buffer.scala 440:51] + node _T_2084 = or(_T_2082, _T_2083) @[el2_lsu_bus_buffer.scala 440:48] + node _T_2085 = bits(_T_2079, 7, 7) @[el2_lsu_bus_buffer.scala 440:57] + node _T_2086 = or(_T_2084, _T_2085) @[el2_lsu_bus_buffer.scala 440:54] + node _T_2087 = bits(_T_2079, 2, 2) @[el2_lsu_bus_buffer.scala 440:64] + node _T_2088 = bits(_T_2079, 3, 3) @[el2_lsu_bus_buffer.scala 440:70] + node _T_2089 = or(_T_2087, _T_2088) @[el2_lsu_bus_buffer.scala 440:67] + node _T_2090 = bits(_T_2079, 6, 6) @[el2_lsu_bus_buffer.scala 440:76] + node _T_2091 = or(_T_2089, _T_2090) @[el2_lsu_bus_buffer.scala 440:73] + node _T_2092 = bits(_T_2079, 7, 7) @[el2_lsu_bus_buffer.scala 440:82] + node _T_2093 = or(_T_2091, _T_2092) @[el2_lsu_bus_buffer.scala 440:79] + node _T_2094 = bits(_T_2079, 1, 1) @[el2_lsu_bus_buffer.scala 440:89] + node _T_2095 = bits(_T_2079, 3, 3) @[el2_lsu_bus_buffer.scala 440:95] + node _T_2096 = or(_T_2094, _T_2095) @[el2_lsu_bus_buffer.scala 440:92] + node _T_2097 = bits(_T_2079, 5, 5) @[el2_lsu_bus_buffer.scala 440:101] + node _T_2098 = or(_T_2096, _T_2097) @[el2_lsu_bus_buffer.scala 440:98] + node _T_2099 = bits(_T_2079, 7, 7) @[el2_lsu_bus_buffer.scala 440:107] + node _T_2100 = or(_T_2098, _T_2099) @[el2_lsu_bus_buffer.scala 440:104] node _T_2101 = cat(_T_2086, _T_2093) @[Cat.scala 29:58] node _T_2102 = cat(_T_2101, _T_2100) @[Cat.scala 29:58] - CmdPtr1 <= _T_2102 @[el2_lsu_bus_buffer.scala 446:11] + CmdPtr1 <= _T_2102 @[el2_lsu_bus_buffer.scala 447:11] node _T_2103 = mux(UInt<1>("h00"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] node _T_2104 = cat(_T_2103, RspPtrDec) @[Cat.scala 29:58] - node _T_2105 = bits(_T_2104, 4, 4) @[el2_lsu_bus_buffer.scala 439:39] - node _T_2106 = bits(_T_2104, 5, 5) @[el2_lsu_bus_buffer.scala 439:45] - node _T_2107 = or(_T_2105, _T_2106) @[el2_lsu_bus_buffer.scala 439:42] - node _T_2108 = bits(_T_2104, 6, 6) @[el2_lsu_bus_buffer.scala 439:51] - node _T_2109 = or(_T_2107, _T_2108) @[el2_lsu_bus_buffer.scala 439:48] - node _T_2110 = bits(_T_2104, 7, 7) @[el2_lsu_bus_buffer.scala 439:57] - node _T_2111 = or(_T_2109, _T_2110) @[el2_lsu_bus_buffer.scala 439:54] - node _T_2112 = bits(_T_2104, 2, 2) @[el2_lsu_bus_buffer.scala 439:64] - node _T_2113 = bits(_T_2104, 3, 3) @[el2_lsu_bus_buffer.scala 439:70] - node _T_2114 = or(_T_2112, _T_2113) @[el2_lsu_bus_buffer.scala 439:67] - node _T_2115 = bits(_T_2104, 6, 6) @[el2_lsu_bus_buffer.scala 439:76] - node _T_2116 = or(_T_2114, _T_2115) @[el2_lsu_bus_buffer.scala 439:73] - node _T_2117 = bits(_T_2104, 7, 7) @[el2_lsu_bus_buffer.scala 439:82] - node _T_2118 = or(_T_2116, _T_2117) @[el2_lsu_bus_buffer.scala 439:79] - node _T_2119 = bits(_T_2104, 1, 1) @[el2_lsu_bus_buffer.scala 439:89] - node _T_2120 = bits(_T_2104, 3, 3) @[el2_lsu_bus_buffer.scala 439:95] - node _T_2121 = or(_T_2119, _T_2120) @[el2_lsu_bus_buffer.scala 439:92] - node _T_2122 = bits(_T_2104, 5, 5) @[el2_lsu_bus_buffer.scala 439:101] - node _T_2123 = or(_T_2121, _T_2122) @[el2_lsu_bus_buffer.scala 439:98] - node _T_2124 = bits(_T_2104, 7, 7) @[el2_lsu_bus_buffer.scala 439:107] - node _T_2125 = or(_T_2123, _T_2124) @[el2_lsu_bus_buffer.scala 439:104] + node _T_2105 = bits(_T_2104, 4, 4) @[el2_lsu_bus_buffer.scala 440:39] + node _T_2106 = bits(_T_2104, 5, 5) @[el2_lsu_bus_buffer.scala 440:45] + node _T_2107 = or(_T_2105, _T_2106) @[el2_lsu_bus_buffer.scala 440:42] + node _T_2108 = bits(_T_2104, 6, 6) @[el2_lsu_bus_buffer.scala 440:51] + node _T_2109 = or(_T_2107, _T_2108) @[el2_lsu_bus_buffer.scala 440:48] + node _T_2110 = bits(_T_2104, 7, 7) @[el2_lsu_bus_buffer.scala 440:57] + node _T_2111 = or(_T_2109, _T_2110) @[el2_lsu_bus_buffer.scala 440:54] + node _T_2112 = bits(_T_2104, 2, 2) @[el2_lsu_bus_buffer.scala 440:64] + node _T_2113 = bits(_T_2104, 3, 3) @[el2_lsu_bus_buffer.scala 440:70] + node _T_2114 = or(_T_2112, _T_2113) @[el2_lsu_bus_buffer.scala 440:67] + node _T_2115 = bits(_T_2104, 6, 6) @[el2_lsu_bus_buffer.scala 440:76] + node _T_2116 = or(_T_2114, _T_2115) @[el2_lsu_bus_buffer.scala 440:73] + node _T_2117 = bits(_T_2104, 7, 7) @[el2_lsu_bus_buffer.scala 440:82] + node _T_2118 = or(_T_2116, _T_2117) @[el2_lsu_bus_buffer.scala 440:79] + node _T_2119 = bits(_T_2104, 1, 1) @[el2_lsu_bus_buffer.scala 440:89] + node _T_2120 = bits(_T_2104, 3, 3) @[el2_lsu_bus_buffer.scala 440:95] + node _T_2121 = or(_T_2119, _T_2120) @[el2_lsu_bus_buffer.scala 440:92] + node _T_2122 = bits(_T_2104, 5, 5) @[el2_lsu_bus_buffer.scala 440:101] + node _T_2123 = or(_T_2121, _T_2122) @[el2_lsu_bus_buffer.scala 440:98] + node _T_2124 = bits(_T_2104, 7, 7) @[el2_lsu_bus_buffer.scala 440:107] + node _T_2125 = or(_T_2123, _T_2124) @[el2_lsu_bus_buffer.scala 440:104] node _T_2126 = cat(_T_2111, _T_2118) @[Cat.scala 29:58] node _T_2127 = cat(_T_2126, _T_2125) @[Cat.scala 29:58] - RspPtr <= _T_2127 @[el2_lsu_bus_buffer.scala 447:10] - wire buf_state_en : UInt<1>[4] @[el2_lsu_bus_buffer.scala 448:26] - buf_state_en[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 449:16] - buf_state_en[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 449:16] - buf_state_en[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 449:16] - buf_state_en[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 449:16] - wire buf_rspageQ : UInt<4>[4] @[el2_lsu_bus_buffer.scala 450:25] - buf_rspageQ[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 451:15] - buf_rspageQ[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 451:15] - buf_rspageQ[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 451:15] - buf_rspageQ[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 451:15] - wire buf_rspage_set : UInt<4>[4] @[el2_lsu_bus_buffer.scala 452:28] - buf_rspage_set[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 453:18] - buf_rspage_set[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 453:18] - buf_rspage_set[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 453:18] - buf_rspage_set[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 453:18] - wire buf_rspage_in : UInt<4>[4] @[el2_lsu_bus_buffer.scala 454:27] - buf_rspage_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 455:17] - buf_rspage_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 455:17] - buf_rspage_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 455:17] - buf_rspage_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 455:17] - wire buf_rspage : UInt<4>[4] @[el2_lsu_bus_buffer.scala 456:24] - buf_rspage[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 457:14] - buf_rspage[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 457:14] - buf_rspage[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 457:14] - buf_rspage[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 457:14] - node _T_2128 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] - node _T_2129 = and(_T_2128, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 459:94] - node _T_2130 = eq(buf_state[0], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] - node _T_2131 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] - node _T_2132 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] - node _T_2133 = and(_T_2131, _T_2132) @[el2_lsu_bus_buffer.scala 460:57] - node _T_2134 = or(_T_2130, _T_2133) @[el2_lsu_bus_buffer.scala 460:31] - node _T_2135 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] - node _T_2136 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] - node _T_2137 = and(_T_2135, _T_2136) @[el2_lsu_bus_buffer.scala 461:41] - node _T_2138 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 461:83] - node _T_2139 = and(_T_2137, _T_2138) @[el2_lsu_bus_buffer.scala 461:71] - node _T_2140 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 461:104] - node _T_2141 = and(_T_2139, _T_2140) @[el2_lsu_bus_buffer.scala 461:92] - node _T_2142 = or(_T_2134, _T_2141) @[el2_lsu_bus_buffer.scala 460:86] - node _T_2143 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] - node _T_2144 = and(_T_2143, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] - node _T_2145 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 462:64] - node _T_2146 = and(_T_2144, _T_2145) @[el2_lsu_bus_buffer.scala 462:52] - node _T_2147 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 462:85] - node _T_2148 = and(_T_2146, _T_2147) @[el2_lsu_bus_buffer.scala 462:73] - node _T_2149 = or(_T_2142, _T_2148) @[el2_lsu_bus_buffer.scala 461:114] - node _T_2150 = and(_T_2129, _T_2149) @[el2_lsu_bus_buffer.scala 459:113] - node _T_2151 = bits(buf_age[0], 0, 0) @[el2_lsu_bus_buffer.scala 462:109] - node _T_2152 = or(_T_2150, _T_2151) @[el2_lsu_bus_buffer.scala 462:97] - node _T_2153 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] - node _T_2154 = and(_T_2153, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 459:94] - node _T_2155 = eq(buf_state[1], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] - node _T_2156 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] - node _T_2157 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] - node _T_2158 = and(_T_2156, _T_2157) @[el2_lsu_bus_buffer.scala 460:57] - node _T_2159 = or(_T_2155, _T_2158) @[el2_lsu_bus_buffer.scala 460:31] - node _T_2160 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] - node _T_2161 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] - node _T_2162 = and(_T_2160, _T_2161) @[el2_lsu_bus_buffer.scala 461:41] - node _T_2163 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 461:83] - node _T_2164 = and(_T_2162, _T_2163) @[el2_lsu_bus_buffer.scala 461:71] - node _T_2165 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 461:104] - node _T_2166 = and(_T_2164, _T_2165) @[el2_lsu_bus_buffer.scala 461:92] - node _T_2167 = or(_T_2159, _T_2166) @[el2_lsu_bus_buffer.scala 460:86] - node _T_2168 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] - node _T_2169 = and(_T_2168, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] - node _T_2170 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 462:64] - node _T_2171 = and(_T_2169, _T_2170) @[el2_lsu_bus_buffer.scala 462:52] - node _T_2172 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 462:85] - node _T_2173 = and(_T_2171, _T_2172) @[el2_lsu_bus_buffer.scala 462:73] - node _T_2174 = or(_T_2167, _T_2173) @[el2_lsu_bus_buffer.scala 461:114] - node _T_2175 = and(_T_2154, _T_2174) @[el2_lsu_bus_buffer.scala 459:113] - node _T_2176 = bits(buf_age[0], 1, 1) @[el2_lsu_bus_buffer.scala 462:109] - node _T_2177 = or(_T_2175, _T_2176) @[el2_lsu_bus_buffer.scala 462:97] - node _T_2178 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] - node _T_2179 = and(_T_2178, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 459:94] - node _T_2180 = eq(buf_state[2], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] - node _T_2181 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] - node _T_2182 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] - node _T_2183 = and(_T_2181, _T_2182) @[el2_lsu_bus_buffer.scala 460:57] - node _T_2184 = or(_T_2180, _T_2183) @[el2_lsu_bus_buffer.scala 460:31] - node _T_2185 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] - node _T_2186 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] - node _T_2187 = and(_T_2185, _T_2186) @[el2_lsu_bus_buffer.scala 461:41] - node _T_2188 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 461:83] - node _T_2189 = and(_T_2187, _T_2188) @[el2_lsu_bus_buffer.scala 461:71] - node _T_2190 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 461:104] - node _T_2191 = and(_T_2189, _T_2190) @[el2_lsu_bus_buffer.scala 461:92] - node _T_2192 = or(_T_2184, _T_2191) @[el2_lsu_bus_buffer.scala 460:86] - node _T_2193 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] - node _T_2194 = and(_T_2193, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] - node _T_2195 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 462:64] - node _T_2196 = and(_T_2194, _T_2195) @[el2_lsu_bus_buffer.scala 462:52] - node _T_2197 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 462:85] - node _T_2198 = and(_T_2196, _T_2197) @[el2_lsu_bus_buffer.scala 462:73] - node _T_2199 = or(_T_2192, _T_2198) @[el2_lsu_bus_buffer.scala 461:114] - node _T_2200 = and(_T_2179, _T_2199) @[el2_lsu_bus_buffer.scala 459:113] - node _T_2201 = bits(buf_age[0], 2, 2) @[el2_lsu_bus_buffer.scala 462:109] - node _T_2202 = or(_T_2200, _T_2201) @[el2_lsu_bus_buffer.scala 462:97] - node _T_2203 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] - node _T_2204 = and(_T_2203, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 459:94] - node _T_2205 = eq(buf_state[3], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] - node _T_2206 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] - node _T_2207 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] - node _T_2208 = and(_T_2206, _T_2207) @[el2_lsu_bus_buffer.scala 460:57] - node _T_2209 = or(_T_2205, _T_2208) @[el2_lsu_bus_buffer.scala 460:31] - node _T_2210 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] - node _T_2211 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] - node _T_2212 = and(_T_2210, _T_2211) @[el2_lsu_bus_buffer.scala 461:41] - node _T_2213 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 461:83] - node _T_2214 = and(_T_2212, _T_2213) @[el2_lsu_bus_buffer.scala 461:71] - node _T_2215 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 461:104] - node _T_2216 = and(_T_2214, _T_2215) @[el2_lsu_bus_buffer.scala 461:92] - node _T_2217 = or(_T_2209, _T_2216) @[el2_lsu_bus_buffer.scala 460:86] - node _T_2218 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] - node _T_2219 = and(_T_2218, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] - node _T_2220 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 462:64] - node _T_2221 = and(_T_2219, _T_2220) @[el2_lsu_bus_buffer.scala 462:52] - node _T_2222 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 462:85] - node _T_2223 = and(_T_2221, _T_2222) @[el2_lsu_bus_buffer.scala 462:73] - node _T_2224 = or(_T_2217, _T_2223) @[el2_lsu_bus_buffer.scala 461:114] - node _T_2225 = and(_T_2204, _T_2224) @[el2_lsu_bus_buffer.scala 459:113] - node _T_2226 = bits(buf_age[0], 3, 3) @[el2_lsu_bus_buffer.scala 462:109] - node _T_2227 = or(_T_2225, _T_2226) @[el2_lsu_bus_buffer.scala 462:97] + RspPtr <= _T_2127 @[el2_lsu_bus_buffer.scala 448:10] + wire buf_state_en : UInt<1>[4] @[el2_lsu_bus_buffer.scala 449:26] + buf_state_en[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 450:16] + buf_state_en[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 450:16] + buf_state_en[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 450:16] + buf_state_en[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 450:16] + wire buf_rspageQ : UInt<4>[4] @[el2_lsu_bus_buffer.scala 451:25] + buf_rspageQ[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 452:15] + buf_rspageQ[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 452:15] + buf_rspageQ[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 452:15] + buf_rspageQ[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 452:15] + wire buf_rspage_set : UInt<4>[4] @[el2_lsu_bus_buffer.scala 453:28] + buf_rspage_set[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 454:18] + buf_rspage_set[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 454:18] + buf_rspage_set[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 454:18] + buf_rspage_set[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 454:18] + wire buf_rspage_in : UInt<4>[4] @[el2_lsu_bus_buffer.scala 455:27] + buf_rspage_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 456:17] + buf_rspage_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 456:17] + buf_rspage_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 456:17] + buf_rspage_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 456:17] + wire buf_rspage : UInt<4>[4] @[el2_lsu_bus_buffer.scala 457:24] + buf_rspage[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 458:14] + buf_rspage[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 458:14] + buf_rspage[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 458:14] + buf_rspage[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 458:14] + node _T_2128 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 460:83] + node _T_2129 = and(_T_2128, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 460:94] + node _T_2130 = eq(buf_state[0], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 461:20] + node _T_2131 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 461:47] + node _T_2132 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 461:59] + node _T_2133 = and(_T_2131, _T_2132) @[el2_lsu_bus_buffer.scala 461:57] + node _T_2134 = or(_T_2130, _T_2133) @[el2_lsu_bus_buffer.scala 461:31] + node _T_2135 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:23] + node _T_2136 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:53] + node _T_2137 = and(_T_2135, _T_2136) @[el2_lsu_bus_buffer.scala 462:41] + node _T_2138 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 462:83] + node _T_2139 = and(_T_2137, _T_2138) @[el2_lsu_bus_buffer.scala 462:71] + node _T_2140 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 462:104] + node _T_2141 = and(_T_2139, _T_2140) @[el2_lsu_bus_buffer.scala 462:92] + node _T_2142 = or(_T_2134, _T_2141) @[el2_lsu_bus_buffer.scala 461:86] + node _T_2143 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 463:17] + node _T_2144 = and(_T_2143, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 463:35] + node _T_2145 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 463:64] + node _T_2146 = and(_T_2144, _T_2145) @[el2_lsu_bus_buffer.scala 463:52] + node _T_2147 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 463:85] + node _T_2148 = and(_T_2146, _T_2147) @[el2_lsu_bus_buffer.scala 463:73] + node _T_2149 = or(_T_2142, _T_2148) @[el2_lsu_bus_buffer.scala 462:114] + node _T_2150 = and(_T_2129, _T_2149) @[el2_lsu_bus_buffer.scala 460:113] + node _T_2151 = bits(buf_age[0], 0, 0) @[el2_lsu_bus_buffer.scala 463:109] + node _T_2152 = or(_T_2150, _T_2151) @[el2_lsu_bus_buffer.scala 463:97] + node _T_2153 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 460:83] + node _T_2154 = and(_T_2153, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 460:94] + node _T_2155 = eq(buf_state[1], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 461:20] + node _T_2156 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 461:47] + node _T_2157 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 461:59] + node _T_2158 = and(_T_2156, _T_2157) @[el2_lsu_bus_buffer.scala 461:57] + node _T_2159 = or(_T_2155, _T_2158) @[el2_lsu_bus_buffer.scala 461:31] + node _T_2160 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:23] + node _T_2161 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:53] + node _T_2162 = and(_T_2160, _T_2161) @[el2_lsu_bus_buffer.scala 462:41] + node _T_2163 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 462:83] + node _T_2164 = and(_T_2162, _T_2163) @[el2_lsu_bus_buffer.scala 462:71] + node _T_2165 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 462:104] + node _T_2166 = and(_T_2164, _T_2165) @[el2_lsu_bus_buffer.scala 462:92] + node _T_2167 = or(_T_2159, _T_2166) @[el2_lsu_bus_buffer.scala 461:86] + node _T_2168 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 463:17] + node _T_2169 = and(_T_2168, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 463:35] + node _T_2170 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 463:64] + node _T_2171 = and(_T_2169, _T_2170) @[el2_lsu_bus_buffer.scala 463:52] + node _T_2172 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 463:85] + node _T_2173 = and(_T_2171, _T_2172) @[el2_lsu_bus_buffer.scala 463:73] + node _T_2174 = or(_T_2167, _T_2173) @[el2_lsu_bus_buffer.scala 462:114] + node _T_2175 = and(_T_2154, _T_2174) @[el2_lsu_bus_buffer.scala 460:113] + node _T_2176 = bits(buf_age[0], 1, 1) @[el2_lsu_bus_buffer.scala 463:109] + node _T_2177 = or(_T_2175, _T_2176) @[el2_lsu_bus_buffer.scala 463:97] + node _T_2178 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 460:83] + node _T_2179 = and(_T_2178, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 460:94] + node _T_2180 = eq(buf_state[2], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 461:20] + node _T_2181 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 461:47] + node _T_2182 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 461:59] + node _T_2183 = and(_T_2181, _T_2182) @[el2_lsu_bus_buffer.scala 461:57] + node _T_2184 = or(_T_2180, _T_2183) @[el2_lsu_bus_buffer.scala 461:31] + node _T_2185 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:23] + node _T_2186 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:53] + node _T_2187 = and(_T_2185, _T_2186) @[el2_lsu_bus_buffer.scala 462:41] + node _T_2188 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 462:83] + node _T_2189 = and(_T_2187, _T_2188) @[el2_lsu_bus_buffer.scala 462:71] + node _T_2190 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 462:104] + node _T_2191 = and(_T_2189, _T_2190) @[el2_lsu_bus_buffer.scala 462:92] + node _T_2192 = or(_T_2184, _T_2191) @[el2_lsu_bus_buffer.scala 461:86] + node _T_2193 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 463:17] + node _T_2194 = and(_T_2193, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 463:35] + node _T_2195 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 463:64] + node _T_2196 = and(_T_2194, _T_2195) @[el2_lsu_bus_buffer.scala 463:52] + node _T_2197 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 463:85] + node _T_2198 = and(_T_2196, _T_2197) @[el2_lsu_bus_buffer.scala 463:73] + node _T_2199 = or(_T_2192, _T_2198) @[el2_lsu_bus_buffer.scala 462:114] + node _T_2200 = and(_T_2179, _T_2199) @[el2_lsu_bus_buffer.scala 460:113] + node _T_2201 = bits(buf_age[0], 2, 2) @[el2_lsu_bus_buffer.scala 463:109] + node _T_2202 = or(_T_2200, _T_2201) @[el2_lsu_bus_buffer.scala 463:97] + node _T_2203 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 460:83] + node _T_2204 = and(_T_2203, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 460:94] + node _T_2205 = eq(buf_state[3], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 461:20] + node _T_2206 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 461:47] + node _T_2207 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 461:59] + node _T_2208 = and(_T_2206, _T_2207) @[el2_lsu_bus_buffer.scala 461:57] + node _T_2209 = or(_T_2205, _T_2208) @[el2_lsu_bus_buffer.scala 461:31] + node _T_2210 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:23] + node _T_2211 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:53] + node _T_2212 = and(_T_2210, _T_2211) @[el2_lsu_bus_buffer.scala 462:41] + node _T_2213 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 462:83] + node _T_2214 = and(_T_2212, _T_2213) @[el2_lsu_bus_buffer.scala 462:71] + node _T_2215 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 462:104] + node _T_2216 = and(_T_2214, _T_2215) @[el2_lsu_bus_buffer.scala 462:92] + node _T_2217 = or(_T_2209, _T_2216) @[el2_lsu_bus_buffer.scala 461:86] + node _T_2218 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 463:17] + node _T_2219 = and(_T_2218, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 463:35] + node _T_2220 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 463:64] + node _T_2221 = and(_T_2219, _T_2220) @[el2_lsu_bus_buffer.scala 463:52] + node _T_2222 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 463:85] + node _T_2223 = and(_T_2221, _T_2222) @[el2_lsu_bus_buffer.scala 463:73] + node _T_2224 = or(_T_2217, _T_2223) @[el2_lsu_bus_buffer.scala 462:114] + node _T_2225 = and(_T_2204, _T_2224) @[el2_lsu_bus_buffer.scala 460:113] + node _T_2226 = bits(buf_age[0], 3, 3) @[el2_lsu_bus_buffer.scala 463:109] + node _T_2227 = or(_T_2225, _T_2226) @[el2_lsu_bus_buffer.scala 463:97] node _T_2228 = cat(_T_2227, _T_2202) @[Cat.scala 29:58] node _T_2229 = cat(_T_2228, _T_2177) @[Cat.scala 29:58] node buf_age_in_0 = cat(_T_2229, _T_2152) @[Cat.scala 29:58] - node _T_2230 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] - node _T_2231 = and(_T_2230, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 459:94] - node _T_2232 = eq(buf_state[0], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] - node _T_2233 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] - node _T_2234 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] - node _T_2235 = and(_T_2233, _T_2234) @[el2_lsu_bus_buffer.scala 460:57] - node _T_2236 = or(_T_2232, _T_2235) @[el2_lsu_bus_buffer.scala 460:31] - node _T_2237 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] - node _T_2238 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] - node _T_2239 = and(_T_2237, _T_2238) @[el2_lsu_bus_buffer.scala 461:41] - node _T_2240 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 461:83] - node _T_2241 = and(_T_2239, _T_2240) @[el2_lsu_bus_buffer.scala 461:71] - node _T_2242 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 461:104] - node _T_2243 = and(_T_2241, _T_2242) @[el2_lsu_bus_buffer.scala 461:92] - node _T_2244 = or(_T_2236, _T_2243) @[el2_lsu_bus_buffer.scala 460:86] - node _T_2245 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] - node _T_2246 = and(_T_2245, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] - node _T_2247 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 462:64] - node _T_2248 = and(_T_2246, _T_2247) @[el2_lsu_bus_buffer.scala 462:52] - node _T_2249 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 462:85] - node _T_2250 = and(_T_2248, _T_2249) @[el2_lsu_bus_buffer.scala 462:73] - node _T_2251 = or(_T_2244, _T_2250) @[el2_lsu_bus_buffer.scala 461:114] - node _T_2252 = and(_T_2231, _T_2251) @[el2_lsu_bus_buffer.scala 459:113] - node _T_2253 = bits(buf_age[1], 0, 0) @[el2_lsu_bus_buffer.scala 462:109] - node _T_2254 = or(_T_2252, _T_2253) @[el2_lsu_bus_buffer.scala 462:97] - node _T_2255 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] - node _T_2256 = and(_T_2255, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 459:94] - node _T_2257 = eq(buf_state[1], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] - node _T_2258 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] - node _T_2259 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] - node _T_2260 = and(_T_2258, _T_2259) @[el2_lsu_bus_buffer.scala 460:57] - node _T_2261 = or(_T_2257, _T_2260) @[el2_lsu_bus_buffer.scala 460:31] - node _T_2262 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] - node _T_2263 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] - node _T_2264 = and(_T_2262, _T_2263) @[el2_lsu_bus_buffer.scala 461:41] - node _T_2265 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 461:83] - node _T_2266 = and(_T_2264, _T_2265) @[el2_lsu_bus_buffer.scala 461:71] - node _T_2267 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 461:104] - node _T_2268 = and(_T_2266, _T_2267) @[el2_lsu_bus_buffer.scala 461:92] - node _T_2269 = or(_T_2261, _T_2268) @[el2_lsu_bus_buffer.scala 460:86] - node _T_2270 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] - node _T_2271 = and(_T_2270, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] - node _T_2272 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 462:64] - node _T_2273 = and(_T_2271, _T_2272) @[el2_lsu_bus_buffer.scala 462:52] - node _T_2274 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 462:85] - node _T_2275 = and(_T_2273, _T_2274) @[el2_lsu_bus_buffer.scala 462:73] - node _T_2276 = or(_T_2269, _T_2275) @[el2_lsu_bus_buffer.scala 461:114] - node _T_2277 = and(_T_2256, _T_2276) @[el2_lsu_bus_buffer.scala 459:113] - node _T_2278 = bits(buf_age[1], 1, 1) @[el2_lsu_bus_buffer.scala 462:109] - node _T_2279 = or(_T_2277, _T_2278) @[el2_lsu_bus_buffer.scala 462:97] - node _T_2280 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] - node _T_2281 = and(_T_2280, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 459:94] - node _T_2282 = eq(buf_state[2], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] - node _T_2283 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] - node _T_2284 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] - node _T_2285 = and(_T_2283, _T_2284) @[el2_lsu_bus_buffer.scala 460:57] - node _T_2286 = or(_T_2282, _T_2285) @[el2_lsu_bus_buffer.scala 460:31] - node _T_2287 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] - node _T_2288 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] - node _T_2289 = and(_T_2287, _T_2288) @[el2_lsu_bus_buffer.scala 461:41] - node _T_2290 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 461:83] - node _T_2291 = and(_T_2289, _T_2290) @[el2_lsu_bus_buffer.scala 461:71] - node _T_2292 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 461:104] - node _T_2293 = and(_T_2291, _T_2292) @[el2_lsu_bus_buffer.scala 461:92] - node _T_2294 = or(_T_2286, _T_2293) @[el2_lsu_bus_buffer.scala 460:86] - node _T_2295 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] - node _T_2296 = and(_T_2295, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] - node _T_2297 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 462:64] - node _T_2298 = and(_T_2296, _T_2297) @[el2_lsu_bus_buffer.scala 462:52] - node _T_2299 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 462:85] - node _T_2300 = and(_T_2298, _T_2299) @[el2_lsu_bus_buffer.scala 462:73] - node _T_2301 = or(_T_2294, _T_2300) @[el2_lsu_bus_buffer.scala 461:114] - node _T_2302 = and(_T_2281, _T_2301) @[el2_lsu_bus_buffer.scala 459:113] - node _T_2303 = bits(buf_age[1], 2, 2) @[el2_lsu_bus_buffer.scala 462:109] - node _T_2304 = or(_T_2302, _T_2303) @[el2_lsu_bus_buffer.scala 462:97] - node _T_2305 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] - node _T_2306 = and(_T_2305, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 459:94] - node _T_2307 = eq(buf_state[3], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] - node _T_2308 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] - node _T_2309 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] - node _T_2310 = and(_T_2308, _T_2309) @[el2_lsu_bus_buffer.scala 460:57] - node _T_2311 = or(_T_2307, _T_2310) @[el2_lsu_bus_buffer.scala 460:31] - node _T_2312 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] - node _T_2313 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] - node _T_2314 = and(_T_2312, _T_2313) @[el2_lsu_bus_buffer.scala 461:41] - node _T_2315 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 461:83] - node _T_2316 = and(_T_2314, _T_2315) @[el2_lsu_bus_buffer.scala 461:71] - node _T_2317 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 461:104] - node _T_2318 = and(_T_2316, _T_2317) @[el2_lsu_bus_buffer.scala 461:92] - node _T_2319 = or(_T_2311, _T_2318) @[el2_lsu_bus_buffer.scala 460:86] - node _T_2320 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] - node _T_2321 = and(_T_2320, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] - node _T_2322 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 462:64] - node _T_2323 = and(_T_2321, _T_2322) @[el2_lsu_bus_buffer.scala 462:52] - node _T_2324 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 462:85] - node _T_2325 = and(_T_2323, _T_2324) @[el2_lsu_bus_buffer.scala 462:73] - node _T_2326 = or(_T_2319, _T_2325) @[el2_lsu_bus_buffer.scala 461:114] - node _T_2327 = and(_T_2306, _T_2326) @[el2_lsu_bus_buffer.scala 459:113] - node _T_2328 = bits(buf_age[1], 3, 3) @[el2_lsu_bus_buffer.scala 462:109] - node _T_2329 = or(_T_2327, _T_2328) @[el2_lsu_bus_buffer.scala 462:97] + node _T_2230 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 460:83] + node _T_2231 = and(_T_2230, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 460:94] + node _T_2232 = eq(buf_state[0], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 461:20] + node _T_2233 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 461:47] + node _T_2234 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 461:59] + node _T_2235 = and(_T_2233, _T_2234) @[el2_lsu_bus_buffer.scala 461:57] + node _T_2236 = or(_T_2232, _T_2235) @[el2_lsu_bus_buffer.scala 461:31] + node _T_2237 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:23] + node _T_2238 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:53] + node _T_2239 = and(_T_2237, _T_2238) @[el2_lsu_bus_buffer.scala 462:41] + node _T_2240 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 462:83] + node _T_2241 = and(_T_2239, _T_2240) @[el2_lsu_bus_buffer.scala 462:71] + node _T_2242 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 462:104] + node _T_2243 = and(_T_2241, _T_2242) @[el2_lsu_bus_buffer.scala 462:92] + node _T_2244 = or(_T_2236, _T_2243) @[el2_lsu_bus_buffer.scala 461:86] + node _T_2245 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 463:17] + node _T_2246 = and(_T_2245, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 463:35] + node _T_2247 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 463:64] + node _T_2248 = and(_T_2246, _T_2247) @[el2_lsu_bus_buffer.scala 463:52] + node _T_2249 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 463:85] + node _T_2250 = and(_T_2248, _T_2249) @[el2_lsu_bus_buffer.scala 463:73] + node _T_2251 = or(_T_2244, _T_2250) @[el2_lsu_bus_buffer.scala 462:114] + node _T_2252 = and(_T_2231, _T_2251) @[el2_lsu_bus_buffer.scala 460:113] + node _T_2253 = bits(buf_age[1], 0, 0) @[el2_lsu_bus_buffer.scala 463:109] + node _T_2254 = or(_T_2252, _T_2253) @[el2_lsu_bus_buffer.scala 463:97] + node _T_2255 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 460:83] + node _T_2256 = and(_T_2255, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 460:94] + node _T_2257 = eq(buf_state[1], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 461:20] + node _T_2258 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 461:47] + node _T_2259 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 461:59] + node _T_2260 = and(_T_2258, _T_2259) @[el2_lsu_bus_buffer.scala 461:57] + node _T_2261 = or(_T_2257, _T_2260) @[el2_lsu_bus_buffer.scala 461:31] + node _T_2262 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:23] + node _T_2263 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:53] + node _T_2264 = and(_T_2262, _T_2263) @[el2_lsu_bus_buffer.scala 462:41] + node _T_2265 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 462:83] + node _T_2266 = and(_T_2264, _T_2265) @[el2_lsu_bus_buffer.scala 462:71] + node _T_2267 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 462:104] + node _T_2268 = and(_T_2266, _T_2267) @[el2_lsu_bus_buffer.scala 462:92] + node _T_2269 = or(_T_2261, _T_2268) @[el2_lsu_bus_buffer.scala 461:86] + node _T_2270 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 463:17] + node _T_2271 = and(_T_2270, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 463:35] + node _T_2272 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 463:64] + node _T_2273 = and(_T_2271, _T_2272) @[el2_lsu_bus_buffer.scala 463:52] + node _T_2274 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 463:85] + node _T_2275 = and(_T_2273, _T_2274) @[el2_lsu_bus_buffer.scala 463:73] + node _T_2276 = or(_T_2269, _T_2275) @[el2_lsu_bus_buffer.scala 462:114] + node _T_2277 = and(_T_2256, _T_2276) @[el2_lsu_bus_buffer.scala 460:113] + node _T_2278 = bits(buf_age[1], 1, 1) @[el2_lsu_bus_buffer.scala 463:109] + node _T_2279 = or(_T_2277, _T_2278) @[el2_lsu_bus_buffer.scala 463:97] + node _T_2280 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 460:83] + node _T_2281 = and(_T_2280, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 460:94] + node _T_2282 = eq(buf_state[2], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 461:20] + node _T_2283 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 461:47] + node _T_2284 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 461:59] + node _T_2285 = and(_T_2283, _T_2284) @[el2_lsu_bus_buffer.scala 461:57] + node _T_2286 = or(_T_2282, _T_2285) @[el2_lsu_bus_buffer.scala 461:31] + node _T_2287 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:23] + node _T_2288 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:53] + node _T_2289 = and(_T_2287, _T_2288) @[el2_lsu_bus_buffer.scala 462:41] + node _T_2290 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 462:83] + node _T_2291 = and(_T_2289, _T_2290) @[el2_lsu_bus_buffer.scala 462:71] + node _T_2292 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 462:104] + node _T_2293 = and(_T_2291, _T_2292) @[el2_lsu_bus_buffer.scala 462:92] + node _T_2294 = or(_T_2286, _T_2293) @[el2_lsu_bus_buffer.scala 461:86] + node _T_2295 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 463:17] + node _T_2296 = and(_T_2295, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 463:35] + node _T_2297 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 463:64] + node _T_2298 = and(_T_2296, _T_2297) @[el2_lsu_bus_buffer.scala 463:52] + node _T_2299 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 463:85] + node _T_2300 = and(_T_2298, _T_2299) @[el2_lsu_bus_buffer.scala 463:73] + node _T_2301 = or(_T_2294, _T_2300) @[el2_lsu_bus_buffer.scala 462:114] + node _T_2302 = and(_T_2281, _T_2301) @[el2_lsu_bus_buffer.scala 460:113] + node _T_2303 = bits(buf_age[1], 2, 2) @[el2_lsu_bus_buffer.scala 463:109] + node _T_2304 = or(_T_2302, _T_2303) @[el2_lsu_bus_buffer.scala 463:97] + node _T_2305 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 460:83] + node _T_2306 = and(_T_2305, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 460:94] + node _T_2307 = eq(buf_state[3], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 461:20] + node _T_2308 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 461:47] + node _T_2309 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 461:59] + node _T_2310 = and(_T_2308, _T_2309) @[el2_lsu_bus_buffer.scala 461:57] + node _T_2311 = or(_T_2307, _T_2310) @[el2_lsu_bus_buffer.scala 461:31] + node _T_2312 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:23] + node _T_2313 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:53] + node _T_2314 = and(_T_2312, _T_2313) @[el2_lsu_bus_buffer.scala 462:41] + node _T_2315 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 462:83] + node _T_2316 = and(_T_2314, _T_2315) @[el2_lsu_bus_buffer.scala 462:71] + node _T_2317 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 462:104] + node _T_2318 = and(_T_2316, _T_2317) @[el2_lsu_bus_buffer.scala 462:92] + node _T_2319 = or(_T_2311, _T_2318) @[el2_lsu_bus_buffer.scala 461:86] + node _T_2320 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 463:17] + node _T_2321 = and(_T_2320, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 463:35] + node _T_2322 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 463:64] + node _T_2323 = and(_T_2321, _T_2322) @[el2_lsu_bus_buffer.scala 463:52] + node _T_2324 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 463:85] + node _T_2325 = and(_T_2323, _T_2324) @[el2_lsu_bus_buffer.scala 463:73] + node _T_2326 = or(_T_2319, _T_2325) @[el2_lsu_bus_buffer.scala 462:114] + node _T_2327 = and(_T_2306, _T_2326) @[el2_lsu_bus_buffer.scala 460:113] + node _T_2328 = bits(buf_age[1], 3, 3) @[el2_lsu_bus_buffer.scala 463:109] + node _T_2329 = or(_T_2327, _T_2328) @[el2_lsu_bus_buffer.scala 463:97] node _T_2330 = cat(_T_2329, _T_2304) @[Cat.scala 29:58] node _T_2331 = cat(_T_2330, _T_2279) @[Cat.scala 29:58] node buf_age_in_1 = cat(_T_2331, _T_2254) @[Cat.scala 29:58] - node _T_2332 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] - node _T_2333 = and(_T_2332, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 459:94] - node _T_2334 = eq(buf_state[0], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] - node _T_2335 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] - node _T_2336 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] - node _T_2337 = and(_T_2335, _T_2336) @[el2_lsu_bus_buffer.scala 460:57] - node _T_2338 = or(_T_2334, _T_2337) @[el2_lsu_bus_buffer.scala 460:31] - node _T_2339 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] - node _T_2340 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] - node _T_2341 = and(_T_2339, _T_2340) @[el2_lsu_bus_buffer.scala 461:41] - node _T_2342 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 461:83] - node _T_2343 = and(_T_2341, _T_2342) @[el2_lsu_bus_buffer.scala 461:71] - node _T_2344 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 461:104] - node _T_2345 = and(_T_2343, _T_2344) @[el2_lsu_bus_buffer.scala 461:92] - node _T_2346 = or(_T_2338, _T_2345) @[el2_lsu_bus_buffer.scala 460:86] - node _T_2347 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] - node _T_2348 = and(_T_2347, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] - node _T_2349 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 462:64] - node _T_2350 = and(_T_2348, _T_2349) @[el2_lsu_bus_buffer.scala 462:52] - node _T_2351 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 462:85] - node _T_2352 = and(_T_2350, _T_2351) @[el2_lsu_bus_buffer.scala 462:73] - node _T_2353 = or(_T_2346, _T_2352) @[el2_lsu_bus_buffer.scala 461:114] - node _T_2354 = and(_T_2333, _T_2353) @[el2_lsu_bus_buffer.scala 459:113] - node _T_2355 = bits(buf_age[2], 0, 0) @[el2_lsu_bus_buffer.scala 462:109] - node _T_2356 = or(_T_2354, _T_2355) @[el2_lsu_bus_buffer.scala 462:97] - node _T_2357 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] - node _T_2358 = and(_T_2357, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 459:94] - node _T_2359 = eq(buf_state[1], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] - node _T_2360 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] - node _T_2361 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] - node _T_2362 = and(_T_2360, _T_2361) @[el2_lsu_bus_buffer.scala 460:57] - node _T_2363 = or(_T_2359, _T_2362) @[el2_lsu_bus_buffer.scala 460:31] - node _T_2364 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] - node _T_2365 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] - node _T_2366 = and(_T_2364, _T_2365) @[el2_lsu_bus_buffer.scala 461:41] - node _T_2367 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 461:83] - node _T_2368 = and(_T_2366, _T_2367) @[el2_lsu_bus_buffer.scala 461:71] - node _T_2369 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 461:104] - node _T_2370 = and(_T_2368, _T_2369) @[el2_lsu_bus_buffer.scala 461:92] - node _T_2371 = or(_T_2363, _T_2370) @[el2_lsu_bus_buffer.scala 460:86] - node _T_2372 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] - node _T_2373 = and(_T_2372, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] - node _T_2374 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 462:64] - node _T_2375 = and(_T_2373, _T_2374) @[el2_lsu_bus_buffer.scala 462:52] - node _T_2376 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 462:85] - node _T_2377 = and(_T_2375, _T_2376) @[el2_lsu_bus_buffer.scala 462:73] - node _T_2378 = or(_T_2371, _T_2377) @[el2_lsu_bus_buffer.scala 461:114] - node _T_2379 = and(_T_2358, _T_2378) @[el2_lsu_bus_buffer.scala 459:113] - node _T_2380 = bits(buf_age[2], 1, 1) @[el2_lsu_bus_buffer.scala 462:109] - node _T_2381 = or(_T_2379, _T_2380) @[el2_lsu_bus_buffer.scala 462:97] - node _T_2382 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] - node _T_2383 = and(_T_2382, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 459:94] - node _T_2384 = eq(buf_state[2], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] - node _T_2385 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] - node _T_2386 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] - node _T_2387 = and(_T_2385, _T_2386) @[el2_lsu_bus_buffer.scala 460:57] - node _T_2388 = or(_T_2384, _T_2387) @[el2_lsu_bus_buffer.scala 460:31] - node _T_2389 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] - node _T_2390 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] - node _T_2391 = and(_T_2389, _T_2390) @[el2_lsu_bus_buffer.scala 461:41] - node _T_2392 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 461:83] - node _T_2393 = and(_T_2391, _T_2392) @[el2_lsu_bus_buffer.scala 461:71] - node _T_2394 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 461:104] - node _T_2395 = and(_T_2393, _T_2394) @[el2_lsu_bus_buffer.scala 461:92] - node _T_2396 = or(_T_2388, _T_2395) @[el2_lsu_bus_buffer.scala 460:86] - node _T_2397 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] - node _T_2398 = and(_T_2397, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] - node _T_2399 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 462:64] - node _T_2400 = and(_T_2398, _T_2399) @[el2_lsu_bus_buffer.scala 462:52] - node _T_2401 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 462:85] - node _T_2402 = and(_T_2400, _T_2401) @[el2_lsu_bus_buffer.scala 462:73] - node _T_2403 = or(_T_2396, _T_2402) @[el2_lsu_bus_buffer.scala 461:114] - node _T_2404 = and(_T_2383, _T_2403) @[el2_lsu_bus_buffer.scala 459:113] - node _T_2405 = bits(buf_age[2], 2, 2) @[el2_lsu_bus_buffer.scala 462:109] - node _T_2406 = or(_T_2404, _T_2405) @[el2_lsu_bus_buffer.scala 462:97] - node _T_2407 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] - node _T_2408 = and(_T_2407, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 459:94] - node _T_2409 = eq(buf_state[3], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] - node _T_2410 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] - node _T_2411 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] - node _T_2412 = and(_T_2410, _T_2411) @[el2_lsu_bus_buffer.scala 460:57] - node _T_2413 = or(_T_2409, _T_2412) @[el2_lsu_bus_buffer.scala 460:31] - node _T_2414 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] - node _T_2415 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] - node _T_2416 = and(_T_2414, _T_2415) @[el2_lsu_bus_buffer.scala 461:41] - node _T_2417 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 461:83] - node _T_2418 = and(_T_2416, _T_2417) @[el2_lsu_bus_buffer.scala 461:71] - node _T_2419 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 461:104] - node _T_2420 = and(_T_2418, _T_2419) @[el2_lsu_bus_buffer.scala 461:92] - node _T_2421 = or(_T_2413, _T_2420) @[el2_lsu_bus_buffer.scala 460:86] - node _T_2422 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] - node _T_2423 = and(_T_2422, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] - node _T_2424 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 462:64] - node _T_2425 = and(_T_2423, _T_2424) @[el2_lsu_bus_buffer.scala 462:52] - node _T_2426 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 462:85] - node _T_2427 = and(_T_2425, _T_2426) @[el2_lsu_bus_buffer.scala 462:73] - node _T_2428 = or(_T_2421, _T_2427) @[el2_lsu_bus_buffer.scala 461:114] - node _T_2429 = and(_T_2408, _T_2428) @[el2_lsu_bus_buffer.scala 459:113] - node _T_2430 = bits(buf_age[2], 3, 3) @[el2_lsu_bus_buffer.scala 462:109] - node _T_2431 = or(_T_2429, _T_2430) @[el2_lsu_bus_buffer.scala 462:97] + node _T_2332 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 460:83] + node _T_2333 = and(_T_2332, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 460:94] + node _T_2334 = eq(buf_state[0], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 461:20] + node _T_2335 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 461:47] + node _T_2336 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 461:59] + node _T_2337 = and(_T_2335, _T_2336) @[el2_lsu_bus_buffer.scala 461:57] + node _T_2338 = or(_T_2334, _T_2337) @[el2_lsu_bus_buffer.scala 461:31] + node _T_2339 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:23] + node _T_2340 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:53] + node _T_2341 = and(_T_2339, _T_2340) @[el2_lsu_bus_buffer.scala 462:41] + node _T_2342 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 462:83] + node _T_2343 = and(_T_2341, _T_2342) @[el2_lsu_bus_buffer.scala 462:71] + node _T_2344 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 462:104] + node _T_2345 = and(_T_2343, _T_2344) @[el2_lsu_bus_buffer.scala 462:92] + node _T_2346 = or(_T_2338, _T_2345) @[el2_lsu_bus_buffer.scala 461:86] + node _T_2347 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 463:17] + node _T_2348 = and(_T_2347, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 463:35] + node _T_2349 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 463:64] + node _T_2350 = and(_T_2348, _T_2349) @[el2_lsu_bus_buffer.scala 463:52] + node _T_2351 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 463:85] + node _T_2352 = and(_T_2350, _T_2351) @[el2_lsu_bus_buffer.scala 463:73] + node _T_2353 = or(_T_2346, _T_2352) @[el2_lsu_bus_buffer.scala 462:114] + node _T_2354 = and(_T_2333, _T_2353) @[el2_lsu_bus_buffer.scala 460:113] + node _T_2355 = bits(buf_age[2], 0, 0) @[el2_lsu_bus_buffer.scala 463:109] + node _T_2356 = or(_T_2354, _T_2355) @[el2_lsu_bus_buffer.scala 463:97] + node _T_2357 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 460:83] + node _T_2358 = and(_T_2357, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 460:94] + node _T_2359 = eq(buf_state[1], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 461:20] + node _T_2360 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 461:47] + node _T_2361 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 461:59] + node _T_2362 = and(_T_2360, _T_2361) @[el2_lsu_bus_buffer.scala 461:57] + node _T_2363 = or(_T_2359, _T_2362) @[el2_lsu_bus_buffer.scala 461:31] + node _T_2364 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:23] + node _T_2365 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:53] + node _T_2366 = and(_T_2364, _T_2365) @[el2_lsu_bus_buffer.scala 462:41] + node _T_2367 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 462:83] + node _T_2368 = and(_T_2366, _T_2367) @[el2_lsu_bus_buffer.scala 462:71] + node _T_2369 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 462:104] + node _T_2370 = and(_T_2368, _T_2369) @[el2_lsu_bus_buffer.scala 462:92] + node _T_2371 = or(_T_2363, _T_2370) @[el2_lsu_bus_buffer.scala 461:86] + node _T_2372 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 463:17] + node _T_2373 = and(_T_2372, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 463:35] + node _T_2374 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 463:64] + node _T_2375 = and(_T_2373, _T_2374) @[el2_lsu_bus_buffer.scala 463:52] + node _T_2376 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 463:85] + node _T_2377 = and(_T_2375, _T_2376) @[el2_lsu_bus_buffer.scala 463:73] + node _T_2378 = or(_T_2371, _T_2377) @[el2_lsu_bus_buffer.scala 462:114] + node _T_2379 = and(_T_2358, _T_2378) @[el2_lsu_bus_buffer.scala 460:113] + node _T_2380 = bits(buf_age[2], 1, 1) @[el2_lsu_bus_buffer.scala 463:109] + node _T_2381 = or(_T_2379, _T_2380) @[el2_lsu_bus_buffer.scala 463:97] + node _T_2382 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 460:83] + node _T_2383 = and(_T_2382, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 460:94] + node _T_2384 = eq(buf_state[2], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 461:20] + node _T_2385 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 461:47] + node _T_2386 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 461:59] + node _T_2387 = and(_T_2385, _T_2386) @[el2_lsu_bus_buffer.scala 461:57] + node _T_2388 = or(_T_2384, _T_2387) @[el2_lsu_bus_buffer.scala 461:31] + node _T_2389 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:23] + node _T_2390 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:53] + node _T_2391 = and(_T_2389, _T_2390) @[el2_lsu_bus_buffer.scala 462:41] + node _T_2392 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 462:83] + node _T_2393 = and(_T_2391, _T_2392) @[el2_lsu_bus_buffer.scala 462:71] + node _T_2394 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 462:104] + node _T_2395 = and(_T_2393, _T_2394) @[el2_lsu_bus_buffer.scala 462:92] + node _T_2396 = or(_T_2388, _T_2395) @[el2_lsu_bus_buffer.scala 461:86] + node _T_2397 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 463:17] + node _T_2398 = and(_T_2397, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 463:35] + node _T_2399 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 463:64] + node _T_2400 = and(_T_2398, _T_2399) @[el2_lsu_bus_buffer.scala 463:52] + node _T_2401 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 463:85] + node _T_2402 = and(_T_2400, _T_2401) @[el2_lsu_bus_buffer.scala 463:73] + node _T_2403 = or(_T_2396, _T_2402) @[el2_lsu_bus_buffer.scala 462:114] + node _T_2404 = and(_T_2383, _T_2403) @[el2_lsu_bus_buffer.scala 460:113] + node _T_2405 = bits(buf_age[2], 2, 2) @[el2_lsu_bus_buffer.scala 463:109] + node _T_2406 = or(_T_2404, _T_2405) @[el2_lsu_bus_buffer.scala 463:97] + node _T_2407 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 460:83] + node _T_2408 = and(_T_2407, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 460:94] + node _T_2409 = eq(buf_state[3], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 461:20] + node _T_2410 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 461:47] + node _T_2411 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 461:59] + node _T_2412 = and(_T_2410, _T_2411) @[el2_lsu_bus_buffer.scala 461:57] + node _T_2413 = or(_T_2409, _T_2412) @[el2_lsu_bus_buffer.scala 461:31] + node _T_2414 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:23] + node _T_2415 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:53] + node _T_2416 = and(_T_2414, _T_2415) @[el2_lsu_bus_buffer.scala 462:41] + node _T_2417 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 462:83] + node _T_2418 = and(_T_2416, _T_2417) @[el2_lsu_bus_buffer.scala 462:71] + node _T_2419 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 462:104] + node _T_2420 = and(_T_2418, _T_2419) @[el2_lsu_bus_buffer.scala 462:92] + node _T_2421 = or(_T_2413, _T_2420) @[el2_lsu_bus_buffer.scala 461:86] + node _T_2422 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 463:17] + node _T_2423 = and(_T_2422, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 463:35] + node _T_2424 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 463:64] + node _T_2425 = and(_T_2423, _T_2424) @[el2_lsu_bus_buffer.scala 463:52] + node _T_2426 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 463:85] + node _T_2427 = and(_T_2425, _T_2426) @[el2_lsu_bus_buffer.scala 463:73] + node _T_2428 = or(_T_2421, _T_2427) @[el2_lsu_bus_buffer.scala 462:114] + node _T_2429 = and(_T_2408, _T_2428) @[el2_lsu_bus_buffer.scala 460:113] + node _T_2430 = bits(buf_age[2], 3, 3) @[el2_lsu_bus_buffer.scala 463:109] + node _T_2431 = or(_T_2429, _T_2430) @[el2_lsu_bus_buffer.scala 463:97] node _T_2432 = cat(_T_2431, _T_2406) @[Cat.scala 29:58] node _T_2433 = cat(_T_2432, _T_2381) @[Cat.scala 29:58] node buf_age_in_2 = cat(_T_2433, _T_2356) @[Cat.scala 29:58] - node _T_2434 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] - node _T_2435 = and(_T_2434, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 459:94] - node _T_2436 = eq(buf_state[0], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] - node _T_2437 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] - node _T_2438 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] - node _T_2439 = and(_T_2437, _T_2438) @[el2_lsu_bus_buffer.scala 460:57] - node _T_2440 = or(_T_2436, _T_2439) @[el2_lsu_bus_buffer.scala 460:31] - node _T_2441 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] - node _T_2442 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] - node _T_2443 = and(_T_2441, _T_2442) @[el2_lsu_bus_buffer.scala 461:41] - node _T_2444 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 461:83] - node _T_2445 = and(_T_2443, _T_2444) @[el2_lsu_bus_buffer.scala 461:71] - node _T_2446 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 461:104] - node _T_2447 = and(_T_2445, _T_2446) @[el2_lsu_bus_buffer.scala 461:92] - node _T_2448 = or(_T_2440, _T_2447) @[el2_lsu_bus_buffer.scala 460:86] - node _T_2449 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] - node _T_2450 = and(_T_2449, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] - node _T_2451 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 462:64] - node _T_2452 = and(_T_2450, _T_2451) @[el2_lsu_bus_buffer.scala 462:52] - node _T_2453 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 462:85] - node _T_2454 = and(_T_2452, _T_2453) @[el2_lsu_bus_buffer.scala 462:73] - node _T_2455 = or(_T_2448, _T_2454) @[el2_lsu_bus_buffer.scala 461:114] - node _T_2456 = and(_T_2435, _T_2455) @[el2_lsu_bus_buffer.scala 459:113] - node _T_2457 = bits(buf_age[3], 0, 0) @[el2_lsu_bus_buffer.scala 462:109] - node _T_2458 = or(_T_2456, _T_2457) @[el2_lsu_bus_buffer.scala 462:97] - node _T_2459 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] - node _T_2460 = and(_T_2459, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 459:94] - node _T_2461 = eq(buf_state[1], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] - node _T_2462 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] - node _T_2463 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] - node _T_2464 = and(_T_2462, _T_2463) @[el2_lsu_bus_buffer.scala 460:57] - node _T_2465 = or(_T_2461, _T_2464) @[el2_lsu_bus_buffer.scala 460:31] - node _T_2466 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] - node _T_2467 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] - node _T_2468 = and(_T_2466, _T_2467) @[el2_lsu_bus_buffer.scala 461:41] - node _T_2469 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 461:83] - node _T_2470 = and(_T_2468, _T_2469) @[el2_lsu_bus_buffer.scala 461:71] - node _T_2471 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 461:104] - node _T_2472 = and(_T_2470, _T_2471) @[el2_lsu_bus_buffer.scala 461:92] - node _T_2473 = or(_T_2465, _T_2472) @[el2_lsu_bus_buffer.scala 460:86] - node _T_2474 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] - node _T_2475 = and(_T_2474, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] - node _T_2476 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 462:64] - node _T_2477 = and(_T_2475, _T_2476) @[el2_lsu_bus_buffer.scala 462:52] - node _T_2478 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 462:85] - node _T_2479 = and(_T_2477, _T_2478) @[el2_lsu_bus_buffer.scala 462:73] - node _T_2480 = or(_T_2473, _T_2479) @[el2_lsu_bus_buffer.scala 461:114] - node _T_2481 = and(_T_2460, _T_2480) @[el2_lsu_bus_buffer.scala 459:113] - node _T_2482 = bits(buf_age[3], 1, 1) @[el2_lsu_bus_buffer.scala 462:109] - node _T_2483 = or(_T_2481, _T_2482) @[el2_lsu_bus_buffer.scala 462:97] - node _T_2484 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] - node _T_2485 = and(_T_2484, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 459:94] - node _T_2486 = eq(buf_state[2], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] - node _T_2487 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] - node _T_2488 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] - node _T_2489 = and(_T_2487, _T_2488) @[el2_lsu_bus_buffer.scala 460:57] - node _T_2490 = or(_T_2486, _T_2489) @[el2_lsu_bus_buffer.scala 460:31] - node _T_2491 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] - node _T_2492 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] - node _T_2493 = and(_T_2491, _T_2492) @[el2_lsu_bus_buffer.scala 461:41] - node _T_2494 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 461:83] - node _T_2495 = and(_T_2493, _T_2494) @[el2_lsu_bus_buffer.scala 461:71] - node _T_2496 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 461:104] - node _T_2497 = and(_T_2495, _T_2496) @[el2_lsu_bus_buffer.scala 461:92] - node _T_2498 = or(_T_2490, _T_2497) @[el2_lsu_bus_buffer.scala 460:86] - node _T_2499 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] - node _T_2500 = and(_T_2499, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] - node _T_2501 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 462:64] - node _T_2502 = and(_T_2500, _T_2501) @[el2_lsu_bus_buffer.scala 462:52] - node _T_2503 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 462:85] - node _T_2504 = and(_T_2502, _T_2503) @[el2_lsu_bus_buffer.scala 462:73] - node _T_2505 = or(_T_2498, _T_2504) @[el2_lsu_bus_buffer.scala 461:114] - node _T_2506 = and(_T_2485, _T_2505) @[el2_lsu_bus_buffer.scala 459:113] - node _T_2507 = bits(buf_age[3], 2, 2) @[el2_lsu_bus_buffer.scala 462:109] - node _T_2508 = or(_T_2506, _T_2507) @[el2_lsu_bus_buffer.scala 462:97] - node _T_2509 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] - node _T_2510 = and(_T_2509, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 459:94] - node _T_2511 = eq(buf_state[3], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] - node _T_2512 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] - node _T_2513 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] - node _T_2514 = and(_T_2512, _T_2513) @[el2_lsu_bus_buffer.scala 460:57] - node _T_2515 = or(_T_2511, _T_2514) @[el2_lsu_bus_buffer.scala 460:31] - node _T_2516 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] - node _T_2517 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] - node _T_2518 = and(_T_2516, _T_2517) @[el2_lsu_bus_buffer.scala 461:41] - node _T_2519 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 461:83] - node _T_2520 = and(_T_2518, _T_2519) @[el2_lsu_bus_buffer.scala 461:71] - node _T_2521 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 461:104] - node _T_2522 = and(_T_2520, _T_2521) @[el2_lsu_bus_buffer.scala 461:92] - node _T_2523 = or(_T_2515, _T_2522) @[el2_lsu_bus_buffer.scala 460:86] - node _T_2524 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] - node _T_2525 = and(_T_2524, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] - node _T_2526 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 462:64] - node _T_2527 = and(_T_2525, _T_2526) @[el2_lsu_bus_buffer.scala 462:52] - node _T_2528 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 462:85] - node _T_2529 = and(_T_2527, _T_2528) @[el2_lsu_bus_buffer.scala 462:73] - node _T_2530 = or(_T_2523, _T_2529) @[el2_lsu_bus_buffer.scala 461:114] - node _T_2531 = and(_T_2510, _T_2530) @[el2_lsu_bus_buffer.scala 459:113] - node _T_2532 = bits(buf_age[3], 3, 3) @[el2_lsu_bus_buffer.scala 462:109] - node _T_2533 = or(_T_2531, _T_2532) @[el2_lsu_bus_buffer.scala 462:97] + node _T_2434 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 460:83] + node _T_2435 = and(_T_2434, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 460:94] + node _T_2436 = eq(buf_state[0], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 461:20] + node _T_2437 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 461:47] + node _T_2438 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 461:59] + node _T_2439 = and(_T_2437, _T_2438) @[el2_lsu_bus_buffer.scala 461:57] + node _T_2440 = or(_T_2436, _T_2439) @[el2_lsu_bus_buffer.scala 461:31] + node _T_2441 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:23] + node _T_2442 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:53] + node _T_2443 = and(_T_2441, _T_2442) @[el2_lsu_bus_buffer.scala 462:41] + node _T_2444 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 462:83] + node _T_2445 = and(_T_2443, _T_2444) @[el2_lsu_bus_buffer.scala 462:71] + node _T_2446 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 462:104] + node _T_2447 = and(_T_2445, _T_2446) @[el2_lsu_bus_buffer.scala 462:92] + node _T_2448 = or(_T_2440, _T_2447) @[el2_lsu_bus_buffer.scala 461:86] + node _T_2449 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 463:17] + node _T_2450 = and(_T_2449, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 463:35] + node _T_2451 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 463:64] + node _T_2452 = and(_T_2450, _T_2451) @[el2_lsu_bus_buffer.scala 463:52] + node _T_2453 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 463:85] + node _T_2454 = and(_T_2452, _T_2453) @[el2_lsu_bus_buffer.scala 463:73] + node _T_2455 = or(_T_2448, _T_2454) @[el2_lsu_bus_buffer.scala 462:114] + node _T_2456 = and(_T_2435, _T_2455) @[el2_lsu_bus_buffer.scala 460:113] + node _T_2457 = bits(buf_age[3], 0, 0) @[el2_lsu_bus_buffer.scala 463:109] + node _T_2458 = or(_T_2456, _T_2457) @[el2_lsu_bus_buffer.scala 463:97] + node _T_2459 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 460:83] + node _T_2460 = and(_T_2459, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 460:94] + node _T_2461 = eq(buf_state[1], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 461:20] + node _T_2462 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 461:47] + node _T_2463 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 461:59] + node _T_2464 = and(_T_2462, _T_2463) @[el2_lsu_bus_buffer.scala 461:57] + node _T_2465 = or(_T_2461, _T_2464) @[el2_lsu_bus_buffer.scala 461:31] + node _T_2466 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:23] + node _T_2467 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:53] + node _T_2468 = and(_T_2466, _T_2467) @[el2_lsu_bus_buffer.scala 462:41] + node _T_2469 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 462:83] + node _T_2470 = and(_T_2468, _T_2469) @[el2_lsu_bus_buffer.scala 462:71] + node _T_2471 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 462:104] + node _T_2472 = and(_T_2470, _T_2471) @[el2_lsu_bus_buffer.scala 462:92] + node _T_2473 = or(_T_2465, _T_2472) @[el2_lsu_bus_buffer.scala 461:86] + node _T_2474 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 463:17] + node _T_2475 = and(_T_2474, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 463:35] + node _T_2476 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 463:64] + node _T_2477 = and(_T_2475, _T_2476) @[el2_lsu_bus_buffer.scala 463:52] + node _T_2478 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 463:85] + node _T_2479 = and(_T_2477, _T_2478) @[el2_lsu_bus_buffer.scala 463:73] + node _T_2480 = or(_T_2473, _T_2479) @[el2_lsu_bus_buffer.scala 462:114] + node _T_2481 = and(_T_2460, _T_2480) @[el2_lsu_bus_buffer.scala 460:113] + node _T_2482 = bits(buf_age[3], 1, 1) @[el2_lsu_bus_buffer.scala 463:109] + node _T_2483 = or(_T_2481, _T_2482) @[el2_lsu_bus_buffer.scala 463:97] + node _T_2484 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 460:83] + node _T_2485 = and(_T_2484, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 460:94] + node _T_2486 = eq(buf_state[2], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 461:20] + node _T_2487 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 461:47] + node _T_2488 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 461:59] + node _T_2489 = and(_T_2487, _T_2488) @[el2_lsu_bus_buffer.scala 461:57] + node _T_2490 = or(_T_2486, _T_2489) @[el2_lsu_bus_buffer.scala 461:31] + node _T_2491 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:23] + node _T_2492 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:53] + node _T_2493 = and(_T_2491, _T_2492) @[el2_lsu_bus_buffer.scala 462:41] + node _T_2494 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 462:83] + node _T_2495 = and(_T_2493, _T_2494) @[el2_lsu_bus_buffer.scala 462:71] + node _T_2496 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 462:104] + node _T_2497 = and(_T_2495, _T_2496) @[el2_lsu_bus_buffer.scala 462:92] + node _T_2498 = or(_T_2490, _T_2497) @[el2_lsu_bus_buffer.scala 461:86] + node _T_2499 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 463:17] + node _T_2500 = and(_T_2499, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 463:35] + node _T_2501 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 463:64] + node _T_2502 = and(_T_2500, _T_2501) @[el2_lsu_bus_buffer.scala 463:52] + node _T_2503 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 463:85] + node _T_2504 = and(_T_2502, _T_2503) @[el2_lsu_bus_buffer.scala 463:73] + node _T_2505 = or(_T_2498, _T_2504) @[el2_lsu_bus_buffer.scala 462:114] + node _T_2506 = and(_T_2485, _T_2505) @[el2_lsu_bus_buffer.scala 460:113] + node _T_2507 = bits(buf_age[3], 2, 2) @[el2_lsu_bus_buffer.scala 463:109] + node _T_2508 = or(_T_2506, _T_2507) @[el2_lsu_bus_buffer.scala 463:97] + node _T_2509 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 460:83] + node _T_2510 = and(_T_2509, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 460:94] + node _T_2511 = eq(buf_state[3], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 461:20] + node _T_2512 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 461:47] + node _T_2513 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 461:59] + node _T_2514 = and(_T_2512, _T_2513) @[el2_lsu_bus_buffer.scala 461:57] + node _T_2515 = or(_T_2511, _T_2514) @[el2_lsu_bus_buffer.scala 461:31] + node _T_2516 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:23] + node _T_2517 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:53] + node _T_2518 = and(_T_2516, _T_2517) @[el2_lsu_bus_buffer.scala 462:41] + node _T_2519 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 462:83] + node _T_2520 = and(_T_2518, _T_2519) @[el2_lsu_bus_buffer.scala 462:71] + node _T_2521 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 462:104] + node _T_2522 = and(_T_2520, _T_2521) @[el2_lsu_bus_buffer.scala 462:92] + node _T_2523 = or(_T_2515, _T_2522) @[el2_lsu_bus_buffer.scala 461:86] + node _T_2524 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 463:17] + node _T_2525 = and(_T_2524, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 463:35] + node _T_2526 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 463:64] + node _T_2527 = and(_T_2525, _T_2526) @[el2_lsu_bus_buffer.scala 463:52] + node _T_2528 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 463:85] + node _T_2529 = and(_T_2527, _T_2528) @[el2_lsu_bus_buffer.scala 463:73] + node _T_2530 = or(_T_2523, _T_2529) @[el2_lsu_bus_buffer.scala 462:114] + node _T_2531 = and(_T_2510, _T_2530) @[el2_lsu_bus_buffer.scala 460:113] + node _T_2532 = bits(buf_age[3], 3, 3) @[el2_lsu_bus_buffer.scala 463:109] + node _T_2533 = or(_T_2531, _T_2532) @[el2_lsu_bus_buffer.scala 463:97] node _T_2534 = cat(_T_2533, _T_2508) @[Cat.scala 29:58] node _T_2535 = cat(_T_2534, _T_2483) @[Cat.scala 29:58] node buf_age_in_3 = cat(_T_2535, _T_2458) @[Cat.scala 29:58] - wire buf_ageQ : UInt<4>[4] @[el2_lsu_bus_buffer.scala 463:22] - buf_ageQ[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 464:12] - buf_ageQ[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 464:12] - buf_ageQ[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 464:12] - buf_ageQ[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 464:12] - node _T_2536 = bits(buf_ageQ[0], 0, 0) @[el2_lsu_bus_buffer.scala 465:72] - node _T_2537 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] - node _T_2538 = and(_T_2537, buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 465:103] - node _T_2539 = eq(_T_2538, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] - node _T_2540 = and(_T_2536, _T_2539) @[el2_lsu_bus_buffer.scala 465:76] - node _T_2541 = bits(buf_ageQ[0], 1, 1) @[el2_lsu_bus_buffer.scala 465:72] - node _T_2542 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] - node _T_2543 = and(_T_2542, buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 465:103] - node _T_2544 = eq(_T_2543, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] - node _T_2545 = and(_T_2541, _T_2544) @[el2_lsu_bus_buffer.scala 465:76] - node _T_2546 = bits(buf_ageQ[0], 2, 2) @[el2_lsu_bus_buffer.scala 465:72] - node _T_2547 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] - node _T_2548 = and(_T_2547, buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 465:103] - node _T_2549 = eq(_T_2548, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] - node _T_2550 = and(_T_2546, _T_2549) @[el2_lsu_bus_buffer.scala 465:76] - node _T_2551 = bits(buf_ageQ[0], 3, 3) @[el2_lsu_bus_buffer.scala 465:72] - node _T_2552 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] - node _T_2553 = and(_T_2552, buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 465:103] - node _T_2554 = eq(_T_2553, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] - node _T_2555 = and(_T_2551, _T_2554) @[el2_lsu_bus_buffer.scala 465:76] + wire buf_ageQ : UInt<4>[4] @[el2_lsu_bus_buffer.scala 464:22] + buf_ageQ[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 465:12] + buf_ageQ[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 465:12] + buf_ageQ[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 465:12] + buf_ageQ[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 465:12] + node _T_2536 = bits(buf_ageQ[0], 0, 0) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2537 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 466:93] + node _T_2538 = and(_T_2537, buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 466:103] + node _T_2539 = eq(_T_2538, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:78] + node _T_2540 = and(_T_2536, _T_2539) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2541 = bits(buf_ageQ[0], 1, 1) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2542 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 466:93] + node _T_2543 = and(_T_2542, buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 466:103] + node _T_2544 = eq(_T_2543, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:78] + node _T_2545 = and(_T_2541, _T_2544) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2546 = bits(buf_ageQ[0], 2, 2) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2547 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 466:93] + node _T_2548 = and(_T_2547, buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 466:103] + node _T_2549 = eq(_T_2548, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:78] + node _T_2550 = and(_T_2546, _T_2549) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2551 = bits(buf_ageQ[0], 3, 3) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2552 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 466:93] + node _T_2553 = and(_T_2552, buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 466:103] + node _T_2554 = eq(_T_2553, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:78] + node _T_2555 = and(_T_2551, _T_2554) @[el2_lsu_bus_buffer.scala 466:76] node _T_2556 = cat(_T_2555, _T_2550) @[Cat.scala 29:58] node _T_2557 = cat(_T_2556, _T_2545) @[Cat.scala 29:58] node _T_2558 = cat(_T_2557, _T_2540) @[Cat.scala 29:58] - node _T_2559 = bits(buf_ageQ[1], 0, 0) @[el2_lsu_bus_buffer.scala 465:72] - node _T_2560 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] - node _T_2561 = and(_T_2560, buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 465:103] - node _T_2562 = eq(_T_2561, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] - node _T_2563 = and(_T_2559, _T_2562) @[el2_lsu_bus_buffer.scala 465:76] - node _T_2564 = bits(buf_ageQ[1], 1, 1) @[el2_lsu_bus_buffer.scala 465:72] - node _T_2565 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] - node _T_2566 = and(_T_2565, buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 465:103] - node _T_2567 = eq(_T_2566, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] - node _T_2568 = and(_T_2564, _T_2567) @[el2_lsu_bus_buffer.scala 465:76] - node _T_2569 = bits(buf_ageQ[1], 2, 2) @[el2_lsu_bus_buffer.scala 465:72] - node _T_2570 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] - node _T_2571 = and(_T_2570, buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 465:103] - node _T_2572 = eq(_T_2571, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] - node _T_2573 = and(_T_2569, _T_2572) @[el2_lsu_bus_buffer.scala 465:76] - node _T_2574 = bits(buf_ageQ[1], 3, 3) @[el2_lsu_bus_buffer.scala 465:72] - node _T_2575 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] - node _T_2576 = and(_T_2575, buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 465:103] - node _T_2577 = eq(_T_2576, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] - node _T_2578 = and(_T_2574, _T_2577) @[el2_lsu_bus_buffer.scala 465:76] + node _T_2559 = bits(buf_ageQ[1], 0, 0) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2560 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 466:93] + node _T_2561 = and(_T_2560, buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 466:103] + node _T_2562 = eq(_T_2561, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:78] + node _T_2563 = and(_T_2559, _T_2562) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2564 = bits(buf_ageQ[1], 1, 1) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2565 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 466:93] + node _T_2566 = and(_T_2565, buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 466:103] + node _T_2567 = eq(_T_2566, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:78] + node _T_2568 = and(_T_2564, _T_2567) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2569 = bits(buf_ageQ[1], 2, 2) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2570 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 466:93] + node _T_2571 = and(_T_2570, buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 466:103] + node _T_2572 = eq(_T_2571, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:78] + node _T_2573 = and(_T_2569, _T_2572) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2574 = bits(buf_ageQ[1], 3, 3) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2575 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 466:93] + node _T_2576 = and(_T_2575, buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 466:103] + node _T_2577 = eq(_T_2576, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:78] + node _T_2578 = and(_T_2574, _T_2577) @[el2_lsu_bus_buffer.scala 466:76] node _T_2579 = cat(_T_2578, _T_2573) @[Cat.scala 29:58] node _T_2580 = cat(_T_2579, _T_2568) @[Cat.scala 29:58] node _T_2581 = cat(_T_2580, _T_2563) @[Cat.scala 29:58] - node _T_2582 = bits(buf_ageQ[2], 0, 0) @[el2_lsu_bus_buffer.scala 465:72] - node _T_2583 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] - node _T_2584 = and(_T_2583, buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 465:103] - node _T_2585 = eq(_T_2584, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] - node _T_2586 = and(_T_2582, _T_2585) @[el2_lsu_bus_buffer.scala 465:76] - node _T_2587 = bits(buf_ageQ[2], 1, 1) @[el2_lsu_bus_buffer.scala 465:72] - node _T_2588 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] - node _T_2589 = and(_T_2588, buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 465:103] - node _T_2590 = eq(_T_2589, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] - node _T_2591 = and(_T_2587, _T_2590) @[el2_lsu_bus_buffer.scala 465:76] - node _T_2592 = bits(buf_ageQ[2], 2, 2) @[el2_lsu_bus_buffer.scala 465:72] - node _T_2593 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] - node _T_2594 = and(_T_2593, buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 465:103] - node _T_2595 = eq(_T_2594, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] - node _T_2596 = and(_T_2592, _T_2595) @[el2_lsu_bus_buffer.scala 465:76] - node _T_2597 = bits(buf_ageQ[2], 3, 3) @[el2_lsu_bus_buffer.scala 465:72] - node _T_2598 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] - node _T_2599 = and(_T_2598, buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 465:103] - node _T_2600 = eq(_T_2599, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] - node _T_2601 = and(_T_2597, _T_2600) @[el2_lsu_bus_buffer.scala 465:76] + node _T_2582 = bits(buf_ageQ[2], 0, 0) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2583 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 466:93] + node _T_2584 = and(_T_2583, buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 466:103] + node _T_2585 = eq(_T_2584, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:78] + node _T_2586 = and(_T_2582, _T_2585) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2587 = bits(buf_ageQ[2], 1, 1) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2588 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 466:93] + node _T_2589 = and(_T_2588, buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 466:103] + node _T_2590 = eq(_T_2589, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:78] + node _T_2591 = and(_T_2587, _T_2590) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2592 = bits(buf_ageQ[2], 2, 2) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2593 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 466:93] + node _T_2594 = and(_T_2593, buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 466:103] + node _T_2595 = eq(_T_2594, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:78] + node _T_2596 = and(_T_2592, _T_2595) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2597 = bits(buf_ageQ[2], 3, 3) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2598 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 466:93] + node _T_2599 = and(_T_2598, buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 466:103] + node _T_2600 = eq(_T_2599, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:78] + node _T_2601 = and(_T_2597, _T_2600) @[el2_lsu_bus_buffer.scala 466:76] node _T_2602 = cat(_T_2601, _T_2596) @[Cat.scala 29:58] node _T_2603 = cat(_T_2602, _T_2591) @[Cat.scala 29:58] node _T_2604 = cat(_T_2603, _T_2586) @[Cat.scala 29:58] - node _T_2605 = bits(buf_ageQ[3], 0, 0) @[el2_lsu_bus_buffer.scala 465:72] - node _T_2606 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] - node _T_2607 = and(_T_2606, buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 465:103] - node _T_2608 = eq(_T_2607, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] - node _T_2609 = and(_T_2605, _T_2608) @[el2_lsu_bus_buffer.scala 465:76] - node _T_2610 = bits(buf_ageQ[3], 1, 1) @[el2_lsu_bus_buffer.scala 465:72] - node _T_2611 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] - node _T_2612 = and(_T_2611, buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 465:103] - node _T_2613 = eq(_T_2612, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] - node _T_2614 = and(_T_2610, _T_2613) @[el2_lsu_bus_buffer.scala 465:76] - node _T_2615 = bits(buf_ageQ[3], 2, 2) @[el2_lsu_bus_buffer.scala 465:72] - node _T_2616 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] - node _T_2617 = and(_T_2616, buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 465:103] - node _T_2618 = eq(_T_2617, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] - node _T_2619 = and(_T_2615, _T_2618) @[el2_lsu_bus_buffer.scala 465:76] - node _T_2620 = bits(buf_ageQ[3], 3, 3) @[el2_lsu_bus_buffer.scala 465:72] - node _T_2621 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] - node _T_2622 = and(_T_2621, buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 465:103] - node _T_2623 = eq(_T_2622, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] - node _T_2624 = and(_T_2620, _T_2623) @[el2_lsu_bus_buffer.scala 465:76] + node _T_2605 = bits(buf_ageQ[3], 0, 0) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2606 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 466:93] + node _T_2607 = and(_T_2606, buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 466:103] + node _T_2608 = eq(_T_2607, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:78] + node _T_2609 = and(_T_2605, _T_2608) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2610 = bits(buf_ageQ[3], 1, 1) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2611 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 466:93] + node _T_2612 = and(_T_2611, buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 466:103] + node _T_2613 = eq(_T_2612, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:78] + node _T_2614 = and(_T_2610, _T_2613) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2615 = bits(buf_ageQ[3], 2, 2) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2616 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 466:93] + node _T_2617 = and(_T_2616, buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 466:103] + node _T_2618 = eq(_T_2617, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:78] + node _T_2619 = and(_T_2615, _T_2618) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2620 = bits(buf_ageQ[3], 3, 3) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2621 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 466:93] + node _T_2622 = and(_T_2621, buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 466:103] + node _T_2623 = eq(_T_2622, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:78] + node _T_2624 = and(_T_2620, _T_2623) @[el2_lsu_bus_buffer.scala 466:76] node _T_2625 = cat(_T_2624, _T_2619) @[Cat.scala 29:58] node _T_2626 = cat(_T_2625, _T_2614) @[Cat.scala 29:58] node _T_2627 = cat(_T_2626, _T_2609) @[Cat.scala 29:58] - buf_age[0] <= _T_2558 @[el2_lsu_bus_buffer.scala 465:11] - buf_age[1] <= _T_2581 @[el2_lsu_bus_buffer.scala 465:11] - buf_age[2] <= _T_2604 @[el2_lsu_bus_buffer.scala 465:11] - buf_age[3] <= _T_2627 @[el2_lsu_bus_buffer.scala 465:11] - node _T_2628 = eq(UInt<1>("h00"), UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:76] - node _T_2629 = bits(buf_age[0], 0, 0) @[el2_lsu_bus_buffer.scala 466:100] - node _T_2630 = eq(_T_2629, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] - node _T_2631 = neq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] - node _T_2632 = and(_T_2630, _T_2631) @[el2_lsu_bus_buffer.scala 466:104] - node _T_2633 = mux(_T_2628, UInt<1>("h00"), _T_2632) @[el2_lsu_bus_buffer.scala 466:72] - node _T_2634 = eq(UInt<1>("h00"), UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 466:76] - node _T_2635 = bits(buf_age[0], 1, 1) @[el2_lsu_bus_buffer.scala 466:100] - node _T_2636 = eq(_T_2635, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] - node _T_2637 = neq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] - node _T_2638 = and(_T_2636, _T_2637) @[el2_lsu_bus_buffer.scala 466:104] - node _T_2639 = mux(_T_2634, UInt<1>("h00"), _T_2638) @[el2_lsu_bus_buffer.scala 466:72] - node _T_2640 = eq(UInt<1>("h00"), UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 466:76] - node _T_2641 = bits(buf_age[0], 2, 2) @[el2_lsu_bus_buffer.scala 466:100] - node _T_2642 = eq(_T_2641, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] - node _T_2643 = neq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] - node _T_2644 = and(_T_2642, _T_2643) @[el2_lsu_bus_buffer.scala 466:104] - node _T_2645 = mux(_T_2640, UInt<1>("h00"), _T_2644) @[el2_lsu_bus_buffer.scala 466:72] - node _T_2646 = eq(UInt<1>("h00"), UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 466:76] - node _T_2647 = bits(buf_age[0], 3, 3) @[el2_lsu_bus_buffer.scala 466:100] - node _T_2648 = eq(_T_2647, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] - node _T_2649 = neq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] - node _T_2650 = and(_T_2648, _T_2649) @[el2_lsu_bus_buffer.scala 466:104] - node _T_2651 = mux(_T_2646, UInt<1>("h00"), _T_2650) @[el2_lsu_bus_buffer.scala 466:72] + buf_age[0] <= _T_2558 @[el2_lsu_bus_buffer.scala 466:11] + buf_age[1] <= _T_2581 @[el2_lsu_bus_buffer.scala 466:11] + buf_age[2] <= _T_2604 @[el2_lsu_bus_buffer.scala 466:11] + buf_age[3] <= _T_2627 @[el2_lsu_bus_buffer.scala 466:11] + node _T_2628 = eq(UInt<1>("h00"), UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 467:76] + node _T_2629 = bits(buf_age[0], 0, 0) @[el2_lsu_bus_buffer.scala 467:100] + node _T_2630 = eq(_T_2629, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 467:89] + node _T_2631 = neq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 467:119] + node _T_2632 = and(_T_2630, _T_2631) @[el2_lsu_bus_buffer.scala 467:104] + node _T_2633 = mux(_T_2628, UInt<1>("h00"), _T_2632) @[el2_lsu_bus_buffer.scala 467:72] + node _T_2634 = eq(UInt<1>("h00"), UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 467:76] + node _T_2635 = bits(buf_age[0], 1, 1) @[el2_lsu_bus_buffer.scala 467:100] + node _T_2636 = eq(_T_2635, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 467:89] + node _T_2637 = neq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 467:119] + node _T_2638 = and(_T_2636, _T_2637) @[el2_lsu_bus_buffer.scala 467:104] + node _T_2639 = mux(_T_2634, UInt<1>("h00"), _T_2638) @[el2_lsu_bus_buffer.scala 467:72] + node _T_2640 = eq(UInt<1>("h00"), UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 467:76] + node _T_2641 = bits(buf_age[0], 2, 2) @[el2_lsu_bus_buffer.scala 467:100] + node _T_2642 = eq(_T_2641, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 467:89] + node _T_2643 = neq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 467:119] + node _T_2644 = and(_T_2642, _T_2643) @[el2_lsu_bus_buffer.scala 467:104] + node _T_2645 = mux(_T_2640, UInt<1>("h00"), _T_2644) @[el2_lsu_bus_buffer.scala 467:72] + node _T_2646 = eq(UInt<1>("h00"), UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 467:76] + node _T_2647 = bits(buf_age[0], 3, 3) @[el2_lsu_bus_buffer.scala 467:100] + node _T_2648 = eq(_T_2647, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 467:89] + node _T_2649 = neq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 467:119] + node _T_2650 = and(_T_2648, _T_2649) @[el2_lsu_bus_buffer.scala 467:104] + node _T_2651 = mux(_T_2646, UInt<1>("h00"), _T_2650) @[el2_lsu_bus_buffer.scala 467:72] node _T_2652 = cat(_T_2651, _T_2645) @[Cat.scala 29:58] node _T_2653 = cat(_T_2652, _T_2639) @[Cat.scala 29:58] node _T_2654 = cat(_T_2653, _T_2633) @[Cat.scala 29:58] - node _T_2655 = eq(UInt<1>("h01"), UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:76] - node _T_2656 = bits(buf_age[1], 0, 0) @[el2_lsu_bus_buffer.scala 466:100] - node _T_2657 = eq(_T_2656, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] - node _T_2658 = neq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] - node _T_2659 = and(_T_2657, _T_2658) @[el2_lsu_bus_buffer.scala 466:104] - node _T_2660 = mux(_T_2655, UInt<1>("h00"), _T_2659) @[el2_lsu_bus_buffer.scala 466:72] - node _T_2661 = eq(UInt<1>("h01"), UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 466:76] - node _T_2662 = bits(buf_age[1], 1, 1) @[el2_lsu_bus_buffer.scala 466:100] - node _T_2663 = eq(_T_2662, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] - node _T_2664 = neq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] - node _T_2665 = and(_T_2663, _T_2664) @[el2_lsu_bus_buffer.scala 466:104] - node _T_2666 = mux(_T_2661, UInt<1>("h00"), _T_2665) @[el2_lsu_bus_buffer.scala 466:72] - node _T_2667 = eq(UInt<1>("h01"), UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 466:76] - node _T_2668 = bits(buf_age[1], 2, 2) @[el2_lsu_bus_buffer.scala 466:100] - node _T_2669 = eq(_T_2668, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] - node _T_2670 = neq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] - node _T_2671 = and(_T_2669, _T_2670) @[el2_lsu_bus_buffer.scala 466:104] - node _T_2672 = mux(_T_2667, UInt<1>("h00"), _T_2671) @[el2_lsu_bus_buffer.scala 466:72] - node _T_2673 = eq(UInt<1>("h01"), UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 466:76] - node _T_2674 = bits(buf_age[1], 3, 3) @[el2_lsu_bus_buffer.scala 466:100] - node _T_2675 = eq(_T_2674, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] - node _T_2676 = neq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] - node _T_2677 = and(_T_2675, _T_2676) @[el2_lsu_bus_buffer.scala 466:104] - node _T_2678 = mux(_T_2673, UInt<1>("h00"), _T_2677) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2655 = eq(UInt<1>("h01"), UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 467:76] + node _T_2656 = bits(buf_age[1], 0, 0) @[el2_lsu_bus_buffer.scala 467:100] + node _T_2657 = eq(_T_2656, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 467:89] + node _T_2658 = neq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 467:119] + node _T_2659 = and(_T_2657, _T_2658) @[el2_lsu_bus_buffer.scala 467:104] + node _T_2660 = mux(_T_2655, UInt<1>("h00"), _T_2659) @[el2_lsu_bus_buffer.scala 467:72] + node _T_2661 = eq(UInt<1>("h01"), UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 467:76] + node _T_2662 = bits(buf_age[1], 1, 1) @[el2_lsu_bus_buffer.scala 467:100] + node _T_2663 = eq(_T_2662, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 467:89] + node _T_2664 = neq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 467:119] + node _T_2665 = and(_T_2663, _T_2664) @[el2_lsu_bus_buffer.scala 467:104] + node _T_2666 = mux(_T_2661, UInt<1>("h00"), _T_2665) @[el2_lsu_bus_buffer.scala 467:72] + node _T_2667 = eq(UInt<1>("h01"), UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 467:76] + node _T_2668 = bits(buf_age[1], 2, 2) @[el2_lsu_bus_buffer.scala 467:100] + node _T_2669 = eq(_T_2668, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 467:89] + node _T_2670 = neq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 467:119] + node _T_2671 = and(_T_2669, _T_2670) @[el2_lsu_bus_buffer.scala 467:104] + node _T_2672 = mux(_T_2667, UInt<1>("h00"), _T_2671) @[el2_lsu_bus_buffer.scala 467:72] + node _T_2673 = eq(UInt<1>("h01"), UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 467:76] + node _T_2674 = bits(buf_age[1], 3, 3) @[el2_lsu_bus_buffer.scala 467:100] + node _T_2675 = eq(_T_2674, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 467:89] + node _T_2676 = neq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 467:119] + node _T_2677 = and(_T_2675, _T_2676) @[el2_lsu_bus_buffer.scala 467:104] + node _T_2678 = mux(_T_2673, UInt<1>("h00"), _T_2677) @[el2_lsu_bus_buffer.scala 467:72] node _T_2679 = cat(_T_2678, _T_2672) @[Cat.scala 29:58] node _T_2680 = cat(_T_2679, _T_2666) @[Cat.scala 29:58] node _T_2681 = cat(_T_2680, _T_2660) @[Cat.scala 29:58] - node _T_2682 = eq(UInt<2>("h02"), UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:76] - node _T_2683 = bits(buf_age[2], 0, 0) @[el2_lsu_bus_buffer.scala 466:100] - node _T_2684 = eq(_T_2683, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] - node _T_2685 = neq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] - node _T_2686 = and(_T_2684, _T_2685) @[el2_lsu_bus_buffer.scala 466:104] - node _T_2687 = mux(_T_2682, UInt<1>("h00"), _T_2686) @[el2_lsu_bus_buffer.scala 466:72] - node _T_2688 = eq(UInt<2>("h02"), UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 466:76] - node _T_2689 = bits(buf_age[2], 1, 1) @[el2_lsu_bus_buffer.scala 466:100] - node _T_2690 = eq(_T_2689, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] - node _T_2691 = neq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] - node _T_2692 = and(_T_2690, _T_2691) @[el2_lsu_bus_buffer.scala 466:104] - node _T_2693 = mux(_T_2688, UInt<1>("h00"), _T_2692) @[el2_lsu_bus_buffer.scala 466:72] - node _T_2694 = eq(UInt<2>("h02"), UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 466:76] - node _T_2695 = bits(buf_age[2], 2, 2) @[el2_lsu_bus_buffer.scala 466:100] - node _T_2696 = eq(_T_2695, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] - node _T_2697 = neq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] - node _T_2698 = and(_T_2696, _T_2697) @[el2_lsu_bus_buffer.scala 466:104] - node _T_2699 = mux(_T_2694, UInt<1>("h00"), _T_2698) @[el2_lsu_bus_buffer.scala 466:72] - node _T_2700 = eq(UInt<2>("h02"), UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 466:76] - node _T_2701 = bits(buf_age[2], 3, 3) @[el2_lsu_bus_buffer.scala 466:100] - node _T_2702 = eq(_T_2701, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] - node _T_2703 = neq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] - node _T_2704 = and(_T_2702, _T_2703) @[el2_lsu_bus_buffer.scala 466:104] - node _T_2705 = mux(_T_2700, UInt<1>("h00"), _T_2704) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2682 = eq(UInt<2>("h02"), UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 467:76] + node _T_2683 = bits(buf_age[2], 0, 0) @[el2_lsu_bus_buffer.scala 467:100] + node _T_2684 = eq(_T_2683, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 467:89] + node _T_2685 = neq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 467:119] + node _T_2686 = and(_T_2684, _T_2685) @[el2_lsu_bus_buffer.scala 467:104] + node _T_2687 = mux(_T_2682, UInt<1>("h00"), _T_2686) @[el2_lsu_bus_buffer.scala 467:72] + node _T_2688 = eq(UInt<2>("h02"), UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 467:76] + node _T_2689 = bits(buf_age[2], 1, 1) @[el2_lsu_bus_buffer.scala 467:100] + node _T_2690 = eq(_T_2689, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 467:89] + node _T_2691 = neq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 467:119] + node _T_2692 = and(_T_2690, _T_2691) @[el2_lsu_bus_buffer.scala 467:104] + node _T_2693 = mux(_T_2688, UInt<1>("h00"), _T_2692) @[el2_lsu_bus_buffer.scala 467:72] + node _T_2694 = eq(UInt<2>("h02"), UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 467:76] + node _T_2695 = bits(buf_age[2], 2, 2) @[el2_lsu_bus_buffer.scala 467:100] + node _T_2696 = eq(_T_2695, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 467:89] + node _T_2697 = neq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 467:119] + node _T_2698 = and(_T_2696, _T_2697) @[el2_lsu_bus_buffer.scala 467:104] + node _T_2699 = mux(_T_2694, UInt<1>("h00"), _T_2698) @[el2_lsu_bus_buffer.scala 467:72] + node _T_2700 = eq(UInt<2>("h02"), UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 467:76] + node _T_2701 = bits(buf_age[2], 3, 3) @[el2_lsu_bus_buffer.scala 467:100] + node _T_2702 = eq(_T_2701, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 467:89] + node _T_2703 = neq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 467:119] + node _T_2704 = and(_T_2702, _T_2703) @[el2_lsu_bus_buffer.scala 467:104] + node _T_2705 = mux(_T_2700, UInt<1>("h00"), _T_2704) @[el2_lsu_bus_buffer.scala 467:72] node _T_2706 = cat(_T_2705, _T_2699) @[Cat.scala 29:58] node _T_2707 = cat(_T_2706, _T_2693) @[Cat.scala 29:58] node _T_2708 = cat(_T_2707, _T_2687) @[Cat.scala 29:58] - node _T_2709 = eq(UInt<2>("h03"), UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:76] - node _T_2710 = bits(buf_age[3], 0, 0) @[el2_lsu_bus_buffer.scala 466:100] - node _T_2711 = eq(_T_2710, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] - node _T_2712 = neq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] - node _T_2713 = and(_T_2711, _T_2712) @[el2_lsu_bus_buffer.scala 466:104] - node _T_2714 = mux(_T_2709, UInt<1>("h00"), _T_2713) @[el2_lsu_bus_buffer.scala 466:72] - node _T_2715 = eq(UInt<2>("h03"), UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 466:76] - node _T_2716 = bits(buf_age[3], 1, 1) @[el2_lsu_bus_buffer.scala 466:100] - node _T_2717 = eq(_T_2716, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] - node _T_2718 = neq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] - node _T_2719 = and(_T_2717, _T_2718) @[el2_lsu_bus_buffer.scala 466:104] - node _T_2720 = mux(_T_2715, UInt<1>("h00"), _T_2719) @[el2_lsu_bus_buffer.scala 466:72] - node _T_2721 = eq(UInt<2>("h03"), UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 466:76] - node _T_2722 = bits(buf_age[3], 2, 2) @[el2_lsu_bus_buffer.scala 466:100] - node _T_2723 = eq(_T_2722, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] - node _T_2724 = neq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] - node _T_2725 = and(_T_2723, _T_2724) @[el2_lsu_bus_buffer.scala 466:104] - node _T_2726 = mux(_T_2721, UInt<1>("h00"), _T_2725) @[el2_lsu_bus_buffer.scala 466:72] - node _T_2727 = eq(UInt<2>("h03"), UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 466:76] - node _T_2728 = bits(buf_age[3], 3, 3) @[el2_lsu_bus_buffer.scala 466:100] - node _T_2729 = eq(_T_2728, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] - node _T_2730 = neq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] - node _T_2731 = and(_T_2729, _T_2730) @[el2_lsu_bus_buffer.scala 466:104] - node _T_2732 = mux(_T_2727, UInt<1>("h00"), _T_2731) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2709 = eq(UInt<2>("h03"), UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 467:76] + node _T_2710 = bits(buf_age[3], 0, 0) @[el2_lsu_bus_buffer.scala 467:100] + node _T_2711 = eq(_T_2710, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 467:89] + node _T_2712 = neq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 467:119] + node _T_2713 = and(_T_2711, _T_2712) @[el2_lsu_bus_buffer.scala 467:104] + node _T_2714 = mux(_T_2709, UInt<1>("h00"), _T_2713) @[el2_lsu_bus_buffer.scala 467:72] + node _T_2715 = eq(UInt<2>("h03"), UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 467:76] + node _T_2716 = bits(buf_age[3], 1, 1) @[el2_lsu_bus_buffer.scala 467:100] + node _T_2717 = eq(_T_2716, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 467:89] + node _T_2718 = neq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 467:119] + node _T_2719 = and(_T_2717, _T_2718) @[el2_lsu_bus_buffer.scala 467:104] + node _T_2720 = mux(_T_2715, UInt<1>("h00"), _T_2719) @[el2_lsu_bus_buffer.scala 467:72] + node _T_2721 = eq(UInt<2>("h03"), UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 467:76] + node _T_2722 = bits(buf_age[3], 2, 2) @[el2_lsu_bus_buffer.scala 467:100] + node _T_2723 = eq(_T_2722, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 467:89] + node _T_2724 = neq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 467:119] + node _T_2725 = and(_T_2723, _T_2724) @[el2_lsu_bus_buffer.scala 467:104] + node _T_2726 = mux(_T_2721, UInt<1>("h00"), _T_2725) @[el2_lsu_bus_buffer.scala 467:72] + node _T_2727 = eq(UInt<2>("h03"), UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 467:76] + node _T_2728 = bits(buf_age[3], 3, 3) @[el2_lsu_bus_buffer.scala 467:100] + node _T_2729 = eq(_T_2728, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 467:89] + node _T_2730 = neq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 467:119] + node _T_2731 = and(_T_2729, _T_2730) @[el2_lsu_bus_buffer.scala 467:104] + node _T_2732 = mux(_T_2727, UInt<1>("h00"), _T_2731) @[el2_lsu_bus_buffer.scala 467:72] node _T_2733 = cat(_T_2732, _T_2726) @[Cat.scala 29:58] node _T_2734 = cat(_T_2733, _T_2720) @[Cat.scala 29:58] node _T_2735 = cat(_T_2734, _T_2714) @[Cat.scala 29:58] - buf_age_younger[0] <= _T_2654 @[el2_lsu_bus_buffer.scala 466:19] - buf_age_younger[1] <= _T_2681 @[el2_lsu_bus_buffer.scala 466:19] - buf_age_younger[2] <= _T_2708 @[el2_lsu_bus_buffer.scala 466:19] - buf_age_younger[3] <= _T_2735 @[el2_lsu_bus_buffer.scala 466:19] - node _T_2736 = bits(buf_rspageQ[0], 0, 0) @[el2_lsu_bus_buffer.scala 467:83] - node _T_2737 = eq(buf_state[0], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] - node _T_2738 = and(_T_2736, _T_2737) @[el2_lsu_bus_buffer.scala 467:87] - node _T_2739 = bits(buf_rspageQ[0], 1, 1) @[el2_lsu_bus_buffer.scala 467:83] - node _T_2740 = eq(buf_state[1], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] - node _T_2741 = and(_T_2739, _T_2740) @[el2_lsu_bus_buffer.scala 467:87] - node _T_2742 = bits(buf_rspageQ[0], 2, 2) @[el2_lsu_bus_buffer.scala 467:83] - node _T_2743 = eq(buf_state[2], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] - node _T_2744 = and(_T_2742, _T_2743) @[el2_lsu_bus_buffer.scala 467:87] - node _T_2745 = bits(buf_rspageQ[0], 3, 3) @[el2_lsu_bus_buffer.scala 467:83] - node _T_2746 = eq(buf_state[3], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] - node _T_2747 = and(_T_2745, _T_2746) @[el2_lsu_bus_buffer.scala 467:87] + buf_age_younger[0] <= _T_2654 @[el2_lsu_bus_buffer.scala 467:19] + buf_age_younger[1] <= _T_2681 @[el2_lsu_bus_buffer.scala 467:19] + buf_age_younger[2] <= _T_2708 @[el2_lsu_bus_buffer.scala 467:19] + buf_age_younger[3] <= _T_2735 @[el2_lsu_bus_buffer.scala 467:19] + node _T_2736 = bits(buf_rspageQ[0], 0, 0) @[el2_lsu_bus_buffer.scala 468:83] + node _T_2737 = eq(buf_state[0], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 468:102] + node _T_2738 = and(_T_2736, _T_2737) @[el2_lsu_bus_buffer.scala 468:87] + node _T_2739 = bits(buf_rspageQ[0], 1, 1) @[el2_lsu_bus_buffer.scala 468:83] + node _T_2740 = eq(buf_state[1], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 468:102] + node _T_2741 = and(_T_2739, _T_2740) @[el2_lsu_bus_buffer.scala 468:87] + node _T_2742 = bits(buf_rspageQ[0], 2, 2) @[el2_lsu_bus_buffer.scala 468:83] + node _T_2743 = eq(buf_state[2], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 468:102] + node _T_2744 = and(_T_2742, _T_2743) @[el2_lsu_bus_buffer.scala 468:87] + node _T_2745 = bits(buf_rspageQ[0], 3, 3) @[el2_lsu_bus_buffer.scala 468:83] + node _T_2746 = eq(buf_state[3], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 468:102] + node _T_2747 = and(_T_2745, _T_2746) @[el2_lsu_bus_buffer.scala 468:87] node _T_2748 = cat(_T_2747, _T_2744) @[Cat.scala 29:58] node _T_2749 = cat(_T_2748, _T_2741) @[Cat.scala 29:58] node _T_2750 = cat(_T_2749, _T_2738) @[Cat.scala 29:58] - node _T_2751 = bits(buf_rspageQ[1], 0, 0) @[el2_lsu_bus_buffer.scala 467:83] - node _T_2752 = eq(buf_state[0], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] - node _T_2753 = and(_T_2751, _T_2752) @[el2_lsu_bus_buffer.scala 467:87] - node _T_2754 = bits(buf_rspageQ[1], 1, 1) @[el2_lsu_bus_buffer.scala 467:83] - node _T_2755 = eq(buf_state[1], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] - node _T_2756 = and(_T_2754, _T_2755) @[el2_lsu_bus_buffer.scala 467:87] - node _T_2757 = bits(buf_rspageQ[1], 2, 2) @[el2_lsu_bus_buffer.scala 467:83] - node _T_2758 = eq(buf_state[2], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] - node _T_2759 = and(_T_2757, _T_2758) @[el2_lsu_bus_buffer.scala 467:87] - node _T_2760 = bits(buf_rspageQ[1], 3, 3) @[el2_lsu_bus_buffer.scala 467:83] - node _T_2761 = eq(buf_state[3], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] - node _T_2762 = and(_T_2760, _T_2761) @[el2_lsu_bus_buffer.scala 467:87] + node _T_2751 = bits(buf_rspageQ[1], 0, 0) @[el2_lsu_bus_buffer.scala 468:83] + node _T_2752 = eq(buf_state[0], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 468:102] + node _T_2753 = and(_T_2751, _T_2752) @[el2_lsu_bus_buffer.scala 468:87] + node _T_2754 = bits(buf_rspageQ[1], 1, 1) @[el2_lsu_bus_buffer.scala 468:83] + node _T_2755 = eq(buf_state[1], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 468:102] + node _T_2756 = and(_T_2754, _T_2755) @[el2_lsu_bus_buffer.scala 468:87] + node _T_2757 = bits(buf_rspageQ[1], 2, 2) @[el2_lsu_bus_buffer.scala 468:83] + node _T_2758 = eq(buf_state[2], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 468:102] + node _T_2759 = and(_T_2757, _T_2758) @[el2_lsu_bus_buffer.scala 468:87] + node _T_2760 = bits(buf_rspageQ[1], 3, 3) @[el2_lsu_bus_buffer.scala 468:83] + node _T_2761 = eq(buf_state[3], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 468:102] + node _T_2762 = and(_T_2760, _T_2761) @[el2_lsu_bus_buffer.scala 468:87] node _T_2763 = cat(_T_2762, _T_2759) @[Cat.scala 29:58] node _T_2764 = cat(_T_2763, _T_2756) @[Cat.scala 29:58] node _T_2765 = cat(_T_2764, _T_2753) @[Cat.scala 29:58] - node _T_2766 = bits(buf_rspageQ[2], 0, 0) @[el2_lsu_bus_buffer.scala 467:83] - node _T_2767 = eq(buf_state[0], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] - node _T_2768 = and(_T_2766, _T_2767) @[el2_lsu_bus_buffer.scala 467:87] - node _T_2769 = bits(buf_rspageQ[2], 1, 1) @[el2_lsu_bus_buffer.scala 467:83] - node _T_2770 = eq(buf_state[1], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] - node _T_2771 = and(_T_2769, _T_2770) @[el2_lsu_bus_buffer.scala 467:87] - node _T_2772 = bits(buf_rspageQ[2], 2, 2) @[el2_lsu_bus_buffer.scala 467:83] - node _T_2773 = eq(buf_state[2], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] - node _T_2774 = and(_T_2772, _T_2773) @[el2_lsu_bus_buffer.scala 467:87] - node _T_2775 = bits(buf_rspageQ[2], 3, 3) @[el2_lsu_bus_buffer.scala 467:83] - node _T_2776 = eq(buf_state[3], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] - node _T_2777 = and(_T_2775, _T_2776) @[el2_lsu_bus_buffer.scala 467:87] + node _T_2766 = bits(buf_rspageQ[2], 0, 0) @[el2_lsu_bus_buffer.scala 468:83] + node _T_2767 = eq(buf_state[0], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 468:102] + node _T_2768 = and(_T_2766, _T_2767) @[el2_lsu_bus_buffer.scala 468:87] + node _T_2769 = bits(buf_rspageQ[2], 1, 1) @[el2_lsu_bus_buffer.scala 468:83] + node _T_2770 = eq(buf_state[1], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 468:102] + node _T_2771 = and(_T_2769, _T_2770) @[el2_lsu_bus_buffer.scala 468:87] + node _T_2772 = bits(buf_rspageQ[2], 2, 2) @[el2_lsu_bus_buffer.scala 468:83] + node _T_2773 = eq(buf_state[2], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 468:102] + node _T_2774 = and(_T_2772, _T_2773) @[el2_lsu_bus_buffer.scala 468:87] + node _T_2775 = bits(buf_rspageQ[2], 3, 3) @[el2_lsu_bus_buffer.scala 468:83] + node _T_2776 = eq(buf_state[3], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 468:102] + node _T_2777 = and(_T_2775, _T_2776) @[el2_lsu_bus_buffer.scala 468:87] node _T_2778 = cat(_T_2777, _T_2774) @[Cat.scala 29:58] node _T_2779 = cat(_T_2778, _T_2771) @[Cat.scala 29:58] node _T_2780 = cat(_T_2779, _T_2768) @[Cat.scala 29:58] - node _T_2781 = bits(buf_rspageQ[3], 0, 0) @[el2_lsu_bus_buffer.scala 467:83] - node _T_2782 = eq(buf_state[0], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] - node _T_2783 = and(_T_2781, _T_2782) @[el2_lsu_bus_buffer.scala 467:87] - node _T_2784 = bits(buf_rspageQ[3], 1, 1) @[el2_lsu_bus_buffer.scala 467:83] - node _T_2785 = eq(buf_state[1], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] - node _T_2786 = and(_T_2784, _T_2785) @[el2_lsu_bus_buffer.scala 467:87] - node _T_2787 = bits(buf_rspageQ[3], 2, 2) @[el2_lsu_bus_buffer.scala 467:83] - node _T_2788 = eq(buf_state[2], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] - node _T_2789 = and(_T_2787, _T_2788) @[el2_lsu_bus_buffer.scala 467:87] - node _T_2790 = bits(buf_rspageQ[3], 3, 3) @[el2_lsu_bus_buffer.scala 467:83] - node _T_2791 = eq(buf_state[3], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] - node _T_2792 = and(_T_2790, _T_2791) @[el2_lsu_bus_buffer.scala 467:87] + node _T_2781 = bits(buf_rspageQ[3], 0, 0) @[el2_lsu_bus_buffer.scala 468:83] + node _T_2782 = eq(buf_state[0], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 468:102] + node _T_2783 = and(_T_2781, _T_2782) @[el2_lsu_bus_buffer.scala 468:87] + node _T_2784 = bits(buf_rspageQ[3], 1, 1) @[el2_lsu_bus_buffer.scala 468:83] + node _T_2785 = eq(buf_state[1], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 468:102] + node _T_2786 = and(_T_2784, _T_2785) @[el2_lsu_bus_buffer.scala 468:87] + node _T_2787 = bits(buf_rspageQ[3], 2, 2) @[el2_lsu_bus_buffer.scala 468:83] + node _T_2788 = eq(buf_state[2], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 468:102] + node _T_2789 = and(_T_2787, _T_2788) @[el2_lsu_bus_buffer.scala 468:87] + node _T_2790 = bits(buf_rspageQ[3], 3, 3) @[el2_lsu_bus_buffer.scala 468:83] + node _T_2791 = eq(buf_state[3], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 468:102] + node _T_2792 = and(_T_2790, _T_2791) @[el2_lsu_bus_buffer.scala 468:87] node _T_2793 = cat(_T_2792, _T_2789) @[Cat.scala 29:58] node _T_2794 = cat(_T_2793, _T_2786) @[Cat.scala 29:58] node _T_2795 = cat(_T_2794, _T_2783) @[Cat.scala 29:58] - buf_rsp_pickage[0] <= _T_2750 @[el2_lsu_bus_buffer.scala 467:19] - buf_rsp_pickage[1] <= _T_2765 @[el2_lsu_bus_buffer.scala 467:19] - buf_rsp_pickage[2] <= _T_2780 @[el2_lsu_bus_buffer.scala 467:19] - buf_rsp_pickage[3] <= _T_2795 @[el2_lsu_bus_buffer.scala 467:19] - node _T_2796 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] - node _T_2797 = and(_T_2796, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 469:93] - node _T_2798 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] - node _T_2799 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] - node _T_2800 = or(_T_2798, _T_2799) @[el2_lsu_bus_buffer.scala 470:32] - node _T_2801 = eq(_T_2800, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] - node _T_2802 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] - node _T_2803 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] - node _T_2804 = and(_T_2802, _T_2803) @[el2_lsu_bus_buffer.scala 471:41] - node _T_2805 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 471:82] - node _T_2806 = and(_T_2804, _T_2805) @[el2_lsu_bus_buffer.scala 471:71] - node _T_2807 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 471:101] - node _T_2808 = and(_T_2806, _T_2807) @[el2_lsu_bus_buffer.scala 471:90] - node _T_2809 = or(_T_2801, _T_2808) @[el2_lsu_bus_buffer.scala 470:59] - node _T_2810 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] - node _T_2811 = and(_T_2810, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] - node _T_2812 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 472:63] - node _T_2813 = and(_T_2811, _T_2812) @[el2_lsu_bus_buffer.scala 472:52] - node _T_2814 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 472:82] - node _T_2815 = and(_T_2813, _T_2814) @[el2_lsu_bus_buffer.scala 472:71] - node _T_2816 = or(_T_2809, _T_2815) @[el2_lsu_bus_buffer.scala 471:110] - node _T_2817 = and(_T_2797, _T_2816) @[el2_lsu_bus_buffer.scala 469:112] - node _T_2818 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] - node _T_2819 = and(_T_2818, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 469:93] - node _T_2820 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] - node _T_2821 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] - node _T_2822 = or(_T_2820, _T_2821) @[el2_lsu_bus_buffer.scala 470:32] - node _T_2823 = eq(_T_2822, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] - node _T_2824 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] - node _T_2825 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] - node _T_2826 = and(_T_2824, _T_2825) @[el2_lsu_bus_buffer.scala 471:41] - node _T_2827 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 471:82] - node _T_2828 = and(_T_2826, _T_2827) @[el2_lsu_bus_buffer.scala 471:71] - node _T_2829 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 471:101] - node _T_2830 = and(_T_2828, _T_2829) @[el2_lsu_bus_buffer.scala 471:90] - node _T_2831 = or(_T_2823, _T_2830) @[el2_lsu_bus_buffer.scala 470:59] - node _T_2832 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] - node _T_2833 = and(_T_2832, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] - node _T_2834 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 472:63] - node _T_2835 = and(_T_2833, _T_2834) @[el2_lsu_bus_buffer.scala 472:52] - node _T_2836 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 472:82] - node _T_2837 = and(_T_2835, _T_2836) @[el2_lsu_bus_buffer.scala 472:71] - node _T_2838 = or(_T_2831, _T_2837) @[el2_lsu_bus_buffer.scala 471:110] - node _T_2839 = and(_T_2819, _T_2838) @[el2_lsu_bus_buffer.scala 469:112] - node _T_2840 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] - node _T_2841 = and(_T_2840, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 469:93] - node _T_2842 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] - node _T_2843 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] - node _T_2844 = or(_T_2842, _T_2843) @[el2_lsu_bus_buffer.scala 470:32] - node _T_2845 = eq(_T_2844, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] - node _T_2846 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] - node _T_2847 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] - node _T_2848 = and(_T_2846, _T_2847) @[el2_lsu_bus_buffer.scala 471:41] - node _T_2849 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 471:82] - node _T_2850 = and(_T_2848, _T_2849) @[el2_lsu_bus_buffer.scala 471:71] - node _T_2851 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 471:101] - node _T_2852 = and(_T_2850, _T_2851) @[el2_lsu_bus_buffer.scala 471:90] - node _T_2853 = or(_T_2845, _T_2852) @[el2_lsu_bus_buffer.scala 470:59] - node _T_2854 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] - node _T_2855 = and(_T_2854, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] - node _T_2856 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 472:63] - node _T_2857 = and(_T_2855, _T_2856) @[el2_lsu_bus_buffer.scala 472:52] - node _T_2858 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 472:82] - node _T_2859 = and(_T_2857, _T_2858) @[el2_lsu_bus_buffer.scala 472:71] - node _T_2860 = or(_T_2853, _T_2859) @[el2_lsu_bus_buffer.scala 471:110] - node _T_2861 = and(_T_2841, _T_2860) @[el2_lsu_bus_buffer.scala 469:112] - node _T_2862 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] - node _T_2863 = and(_T_2862, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 469:93] - node _T_2864 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] - node _T_2865 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] - node _T_2866 = or(_T_2864, _T_2865) @[el2_lsu_bus_buffer.scala 470:32] - node _T_2867 = eq(_T_2866, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] - node _T_2868 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] - node _T_2869 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] - node _T_2870 = and(_T_2868, _T_2869) @[el2_lsu_bus_buffer.scala 471:41] - node _T_2871 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 471:82] - node _T_2872 = and(_T_2870, _T_2871) @[el2_lsu_bus_buffer.scala 471:71] - node _T_2873 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 471:101] - node _T_2874 = and(_T_2872, _T_2873) @[el2_lsu_bus_buffer.scala 471:90] - node _T_2875 = or(_T_2867, _T_2874) @[el2_lsu_bus_buffer.scala 470:59] - node _T_2876 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] - node _T_2877 = and(_T_2876, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] - node _T_2878 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 472:63] - node _T_2879 = and(_T_2877, _T_2878) @[el2_lsu_bus_buffer.scala 472:52] - node _T_2880 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 472:82] - node _T_2881 = and(_T_2879, _T_2880) @[el2_lsu_bus_buffer.scala 472:71] - node _T_2882 = or(_T_2875, _T_2881) @[el2_lsu_bus_buffer.scala 471:110] - node _T_2883 = and(_T_2863, _T_2882) @[el2_lsu_bus_buffer.scala 469:112] + buf_rsp_pickage[0] <= _T_2750 @[el2_lsu_bus_buffer.scala 468:19] + buf_rsp_pickage[1] <= _T_2765 @[el2_lsu_bus_buffer.scala 468:19] + buf_rsp_pickage[2] <= _T_2780 @[el2_lsu_bus_buffer.scala 468:19] + buf_rsp_pickage[3] <= _T_2795 @[el2_lsu_bus_buffer.scala 468:19] + node _T_2796 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:82] + node _T_2797 = and(_T_2796, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 470:93] + node _T_2798 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 471:21] + node _T_2799 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 471:47] + node _T_2800 = or(_T_2798, _T_2799) @[el2_lsu_bus_buffer.scala 471:32] + node _T_2801 = eq(_T_2800, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 471:6] + node _T_2802 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:23] + node _T_2803 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:53] + node _T_2804 = and(_T_2802, _T_2803) @[el2_lsu_bus_buffer.scala 472:41] + node _T_2805 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_2806 = and(_T_2804, _T_2805) @[el2_lsu_bus_buffer.scala 472:71] + node _T_2807 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 472:101] + node _T_2808 = and(_T_2806, _T_2807) @[el2_lsu_bus_buffer.scala 472:90] + node _T_2809 = or(_T_2801, _T_2808) @[el2_lsu_bus_buffer.scala 471:59] + node _T_2810 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 473:17] + node _T_2811 = and(_T_2810, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 473:35] + node _T_2812 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 473:63] + node _T_2813 = and(_T_2811, _T_2812) @[el2_lsu_bus_buffer.scala 473:52] + node _T_2814 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 473:82] + node _T_2815 = and(_T_2813, _T_2814) @[el2_lsu_bus_buffer.scala 473:71] + node _T_2816 = or(_T_2809, _T_2815) @[el2_lsu_bus_buffer.scala 472:110] + node _T_2817 = and(_T_2797, _T_2816) @[el2_lsu_bus_buffer.scala 470:112] + node _T_2818 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:82] + node _T_2819 = and(_T_2818, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 470:93] + node _T_2820 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 471:21] + node _T_2821 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 471:47] + node _T_2822 = or(_T_2820, _T_2821) @[el2_lsu_bus_buffer.scala 471:32] + node _T_2823 = eq(_T_2822, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 471:6] + node _T_2824 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:23] + node _T_2825 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:53] + node _T_2826 = and(_T_2824, _T_2825) @[el2_lsu_bus_buffer.scala 472:41] + node _T_2827 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_2828 = and(_T_2826, _T_2827) @[el2_lsu_bus_buffer.scala 472:71] + node _T_2829 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 472:101] + node _T_2830 = and(_T_2828, _T_2829) @[el2_lsu_bus_buffer.scala 472:90] + node _T_2831 = or(_T_2823, _T_2830) @[el2_lsu_bus_buffer.scala 471:59] + node _T_2832 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 473:17] + node _T_2833 = and(_T_2832, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 473:35] + node _T_2834 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 473:63] + node _T_2835 = and(_T_2833, _T_2834) @[el2_lsu_bus_buffer.scala 473:52] + node _T_2836 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 473:82] + node _T_2837 = and(_T_2835, _T_2836) @[el2_lsu_bus_buffer.scala 473:71] + node _T_2838 = or(_T_2831, _T_2837) @[el2_lsu_bus_buffer.scala 472:110] + node _T_2839 = and(_T_2819, _T_2838) @[el2_lsu_bus_buffer.scala 470:112] + node _T_2840 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:82] + node _T_2841 = and(_T_2840, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 470:93] + node _T_2842 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 471:21] + node _T_2843 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 471:47] + node _T_2844 = or(_T_2842, _T_2843) @[el2_lsu_bus_buffer.scala 471:32] + node _T_2845 = eq(_T_2844, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 471:6] + node _T_2846 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:23] + node _T_2847 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:53] + node _T_2848 = and(_T_2846, _T_2847) @[el2_lsu_bus_buffer.scala 472:41] + node _T_2849 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_2850 = and(_T_2848, _T_2849) @[el2_lsu_bus_buffer.scala 472:71] + node _T_2851 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 472:101] + node _T_2852 = and(_T_2850, _T_2851) @[el2_lsu_bus_buffer.scala 472:90] + node _T_2853 = or(_T_2845, _T_2852) @[el2_lsu_bus_buffer.scala 471:59] + node _T_2854 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 473:17] + node _T_2855 = and(_T_2854, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 473:35] + node _T_2856 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 473:63] + node _T_2857 = and(_T_2855, _T_2856) @[el2_lsu_bus_buffer.scala 473:52] + node _T_2858 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 473:82] + node _T_2859 = and(_T_2857, _T_2858) @[el2_lsu_bus_buffer.scala 473:71] + node _T_2860 = or(_T_2853, _T_2859) @[el2_lsu_bus_buffer.scala 472:110] + node _T_2861 = and(_T_2841, _T_2860) @[el2_lsu_bus_buffer.scala 470:112] + node _T_2862 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:82] + node _T_2863 = and(_T_2862, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 470:93] + node _T_2864 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 471:21] + node _T_2865 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 471:47] + node _T_2866 = or(_T_2864, _T_2865) @[el2_lsu_bus_buffer.scala 471:32] + node _T_2867 = eq(_T_2866, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 471:6] + node _T_2868 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:23] + node _T_2869 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:53] + node _T_2870 = and(_T_2868, _T_2869) @[el2_lsu_bus_buffer.scala 472:41] + node _T_2871 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_2872 = and(_T_2870, _T_2871) @[el2_lsu_bus_buffer.scala 472:71] + node _T_2873 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 472:101] + node _T_2874 = and(_T_2872, _T_2873) @[el2_lsu_bus_buffer.scala 472:90] + node _T_2875 = or(_T_2867, _T_2874) @[el2_lsu_bus_buffer.scala 471:59] + node _T_2876 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 473:17] + node _T_2877 = and(_T_2876, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 473:35] + node _T_2878 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 473:63] + node _T_2879 = and(_T_2877, _T_2878) @[el2_lsu_bus_buffer.scala 473:52] + node _T_2880 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 473:82] + node _T_2881 = and(_T_2879, _T_2880) @[el2_lsu_bus_buffer.scala 473:71] + node _T_2882 = or(_T_2875, _T_2881) @[el2_lsu_bus_buffer.scala 472:110] + node _T_2883 = and(_T_2863, _T_2882) @[el2_lsu_bus_buffer.scala 470:112] node _T_2884 = cat(_T_2883, _T_2861) @[Cat.scala 29:58] node _T_2885 = cat(_T_2884, _T_2839) @[Cat.scala 29:58] node _T_2886 = cat(_T_2885, _T_2817) @[Cat.scala 29:58] - node _T_2887 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] - node _T_2888 = and(_T_2887, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 469:93] - node _T_2889 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] - node _T_2890 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] - node _T_2891 = or(_T_2889, _T_2890) @[el2_lsu_bus_buffer.scala 470:32] - node _T_2892 = eq(_T_2891, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] - node _T_2893 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] - node _T_2894 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] - node _T_2895 = and(_T_2893, _T_2894) @[el2_lsu_bus_buffer.scala 471:41] - node _T_2896 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 471:82] - node _T_2897 = and(_T_2895, _T_2896) @[el2_lsu_bus_buffer.scala 471:71] - node _T_2898 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 471:101] - node _T_2899 = and(_T_2897, _T_2898) @[el2_lsu_bus_buffer.scala 471:90] - node _T_2900 = or(_T_2892, _T_2899) @[el2_lsu_bus_buffer.scala 470:59] - node _T_2901 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] - node _T_2902 = and(_T_2901, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] - node _T_2903 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 472:63] - node _T_2904 = and(_T_2902, _T_2903) @[el2_lsu_bus_buffer.scala 472:52] - node _T_2905 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 472:82] - node _T_2906 = and(_T_2904, _T_2905) @[el2_lsu_bus_buffer.scala 472:71] - node _T_2907 = or(_T_2900, _T_2906) @[el2_lsu_bus_buffer.scala 471:110] - node _T_2908 = and(_T_2888, _T_2907) @[el2_lsu_bus_buffer.scala 469:112] - node _T_2909 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] - node _T_2910 = and(_T_2909, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 469:93] - node _T_2911 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] - node _T_2912 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] - node _T_2913 = or(_T_2911, _T_2912) @[el2_lsu_bus_buffer.scala 470:32] - node _T_2914 = eq(_T_2913, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] - node _T_2915 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] - node _T_2916 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] - node _T_2917 = and(_T_2915, _T_2916) @[el2_lsu_bus_buffer.scala 471:41] - node _T_2918 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 471:82] - node _T_2919 = and(_T_2917, _T_2918) @[el2_lsu_bus_buffer.scala 471:71] - node _T_2920 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 471:101] - node _T_2921 = and(_T_2919, _T_2920) @[el2_lsu_bus_buffer.scala 471:90] - node _T_2922 = or(_T_2914, _T_2921) @[el2_lsu_bus_buffer.scala 470:59] - node _T_2923 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] - node _T_2924 = and(_T_2923, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] - node _T_2925 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 472:63] - node _T_2926 = and(_T_2924, _T_2925) @[el2_lsu_bus_buffer.scala 472:52] - node _T_2927 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 472:82] - node _T_2928 = and(_T_2926, _T_2927) @[el2_lsu_bus_buffer.scala 472:71] - node _T_2929 = or(_T_2922, _T_2928) @[el2_lsu_bus_buffer.scala 471:110] - node _T_2930 = and(_T_2910, _T_2929) @[el2_lsu_bus_buffer.scala 469:112] - node _T_2931 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] - node _T_2932 = and(_T_2931, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 469:93] - node _T_2933 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] - node _T_2934 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] - node _T_2935 = or(_T_2933, _T_2934) @[el2_lsu_bus_buffer.scala 470:32] - node _T_2936 = eq(_T_2935, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] - node _T_2937 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] - node _T_2938 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] - node _T_2939 = and(_T_2937, _T_2938) @[el2_lsu_bus_buffer.scala 471:41] - node _T_2940 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 471:82] - node _T_2941 = and(_T_2939, _T_2940) @[el2_lsu_bus_buffer.scala 471:71] - node _T_2942 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 471:101] - node _T_2943 = and(_T_2941, _T_2942) @[el2_lsu_bus_buffer.scala 471:90] - node _T_2944 = or(_T_2936, _T_2943) @[el2_lsu_bus_buffer.scala 470:59] - node _T_2945 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] - node _T_2946 = and(_T_2945, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] - node _T_2947 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 472:63] - node _T_2948 = and(_T_2946, _T_2947) @[el2_lsu_bus_buffer.scala 472:52] - node _T_2949 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 472:82] - node _T_2950 = and(_T_2948, _T_2949) @[el2_lsu_bus_buffer.scala 472:71] - node _T_2951 = or(_T_2944, _T_2950) @[el2_lsu_bus_buffer.scala 471:110] - node _T_2952 = and(_T_2932, _T_2951) @[el2_lsu_bus_buffer.scala 469:112] - node _T_2953 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] - node _T_2954 = and(_T_2953, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 469:93] - node _T_2955 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] - node _T_2956 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] - node _T_2957 = or(_T_2955, _T_2956) @[el2_lsu_bus_buffer.scala 470:32] - node _T_2958 = eq(_T_2957, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] - node _T_2959 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] - node _T_2960 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] - node _T_2961 = and(_T_2959, _T_2960) @[el2_lsu_bus_buffer.scala 471:41] - node _T_2962 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 471:82] - node _T_2963 = and(_T_2961, _T_2962) @[el2_lsu_bus_buffer.scala 471:71] - node _T_2964 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 471:101] - node _T_2965 = and(_T_2963, _T_2964) @[el2_lsu_bus_buffer.scala 471:90] - node _T_2966 = or(_T_2958, _T_2965) @[el2_lsu_bus_buffer.scala 470:59] - node _T_2967 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] - node _T_2968 = and(_T_2967, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] - node _T_2969 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 472:63] - node _T_2970 = and(_T_2968, _T_2969) @[el2_lsu_bus_buffer.scala 472:52] - node _T_2971 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 472:82] - node _T_2972 = and(_T_2970, _T_2971) @[el2_lsu_bus_buffer.scala 472:71] - node _T_2973 = or(_T_2966, _T_2972) @[el2_lsu_bus_buffer.scala 471:110] - node _T_2974 = and(_T_2954, _T_2973) @[el2_lsu_bus_buffer.scala 469:112] + node _T_2887 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:82] + node _T_2888 = and(_T_2887, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 470:93] + node _T_2889 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 471:21] + node _T_2890 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 471:47] + node _T_2891 = or(_T_2889, _T_2890) @[el2_lsu_bus_buffer.scala 471:32] + node _T_2892 = eq(_T_2891, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 471:6] + node _T_2893 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:23] + node _T_2894 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:53] + node _T_2895 = and(_T_2893, _T_2894) @[el2_lsu_bus_buffer.scala 472:41] + node _T_2896 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_2897 = and(_T_2895, _T_2896) @[el2_lsu_bus_buffer.scala 472:71] + node _T_2898 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 472:101] + node _T_2899 = and(_T_2897, _T_2898) @[el2_lsu_bus_buffer.scala 472:90] + node _T_2900 = or(_T_2892, _T_2899) @[el2_lsu_bus_buffer.scala 471:59] + node _T_2901 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 473:17] + node _T_2902 = and(_T_2901, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 473:35] + node _T_2903 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 473:63] + node _T_2904 = and(_T_2902, _T_2903) @[el2_lsu_bus_buffer.scala 473:52] + node _T_2905 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 473:82] + node _T_2906 = and(_T_2904, _T_2905) @[el2_lsu_bus_buffer.scala 473:71] + node _T_2907 = or(_T_2900, _T_2906) @[el2_lsu_bus_buffer.scala 472:110] + node _T_2908 = and(_T_2888, _T_2907) @[el2_lsu_bus_buffer.scala 470:112] + node _T_2909 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:82] + node _T_2910 = and(_T_2909, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 470:93] + node _T_2911 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 471:21] + node _T_2912 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 471:47] + node _T_2913 = or(_T_2911, _T_2912) @[el2_lsu_bus_buffer.scala 471:32] + node _T_2914 = eq(_T_2913, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 471:6] + node _T_2915 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:23] + node _T_2916 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:53] + node _T_2917 = and(_T_2915, _T_2916) @[el2_lsu_bus_buffer.scala 472:41] + node _T_2918 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_2919 = and(_T_2917, _T_2918) @[el2_lsu_bus_buffer.scala 472:71] + node _T_2920 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 472:101] + node _T_2921 = and(_T_2919, _T_2920) @[el2_lsu_bus_buffer.scala 472:90] + node _T_2922 = or(_T_2914, _T_2921) @[el2_lsu_bus_buffer.scala 471:59] + node _T_2923 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 473:17] + node _T_2924 = and(_T_2923, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 473:35] + node _T_2925 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 473:63] + node _T_2926 = and(_T_2924, _T_2925) @[el2_lsu_bus_buffer.scala 473:52] + node _T_2927 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 473:82] + node _T_2928 = and(_T_2926, _T_2927) @[el2_lsu_bus_buffer.scala 473:71] + node _T_2929 = or(_T_2922, _T_2928) @[el2_lsu_bus_buffer.scala 472:110] + node _T_2930 = and(_T_2910, _T_2929) @[el2_lsu_bus_buffer.scala 470:112] + node _T_2931 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:82] + node _T_2932 = and(_T_2931, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 470:93] + node _T_2933 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 471:21] + node _T_2934 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 471:47] + node _T_2935 = or(_T_2933, _T_2934) @[el2_lsu_bus_buffer.scala 471:32] + node _T_2936 = eq(_T_2935, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 471:6] + node _T_2937 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:23] + node _T_2938 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:53] + node _T_2939 = and(_T_2937, _T_2938) @[el2_lsu_bus_buffer.scala 472:41] + node _T_2940 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_2941 = and(_T_2939, _T_2940) @[el2_lsu_bus_buffer.scala 472:71] + node _T_2942 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 472:101] + node _T_2943 = and(_T_2941, _T_2942) @[el2_lsu_bus_buffer.scala 472:90] + node _T_2944 = or(_T_2936, _T_2943) @[el2_lsu_bus_buffer.scala 471:59] + node _T_2945 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 473:17] + node _T_2946 = and(_T_2945, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 473:35] + node _T_2947 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 473:63] + node _T_2948 = and(_T_2946, _T_2947) @[el2_lsu_bus_buffer.scala 473:52] + node _T_2949 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 473:82] + node _T_2950 = and(_T_2948, _T_2949) @[el2_lsu_bus_buffer.scala 473:71] + node _T_2951 = or(_T_2944, _T_2950) @[el2_lsu_bus_buffer.scala 472:110] + node _T_2952 = and(_T_2932, _T_2951) @[el2_lsu_bus_buffer.scala 470:112] + node _T_2953 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:82] + node _T_2954 = and(_T_2953, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 470:93] + node _T_2955 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 471:21] + node _T_2956 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 471:47] + node _T_2957 = or(_T_2955, _T_2956) @[el2_lsu_bus_buffer.scala 471:32] + node _T_2958 = eq(_T_2957, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 471:6] + node _T_2959 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:23] + node _T_2960 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:53] + node _T_2961 = and(_T_2959, _T_2960) @[el2_lsu_bus_buffer.scala 472:41] + node _T_2962 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_2963 = and(_T_2961, _T_2962) @[el2_lsu_bus_buffer.scala 472:71] + node _T_2964 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 472:101] + node _T_2965 = and(_T_2963, _T_2964) @[el2_lsu_bus_buffer.scala 472:90] + node _T_2966 = or(_T_2958, _T_2965) @[el2_lsu_bus_buffer.scala 471:59] + node _T_2967 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 473:17] + node _T_2968 = and(_T_2967, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 473:35] + node _T_2969 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 473:63] + node _T_2970 = and(_T_2968, _T_2969) @[el2_lsu_bus_buffer.scala 473:52] + node _T_2971 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 473:82] + node _T_2972 = and(_T_2970, _T_2971) @[el2_lsu_bus_buffer.scala 473:71] + node _T_2973 = or(_T_2966, _T_2972) @[el2_lsu_bus_buffer.scala 472:110] + node _T_2974 = and(_T_2954, _T_2973) @[el2_lsu_bus_buffer.scala 470:112] node _T_2975 = cat(_T_2974, _T_2952) @[Cat.scala 29:58] node _T_2976 = cat(_T_2975, _T_2930) @[Cat.scala 29:58] node _T_2977 = cat(_T_2976, _T_2908) @[Cat.scala 29:58] - node _T_2978 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] - node _T_2979 = and(_T_2978, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 469:93] - node _T_2980 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] - node _T_2981 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] - node _T_2982 = or(_T_2980, _T_2981) @[el2_lsu_bus_buffer.scala 470:32] - node _T_2983 = eq(_T_2982, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] - node _T_2984 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] - node _T_2985 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] - node _T_2986 = and(_T_2984, _T_2985) @[el2_lsu_bus_buffer.scala 471:41] - node _T_2987 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 471:82] - node _T_2988 = and(_T_2986, _T_2987) @[el2_lsu_bus_buffer.scala 471:71] - node _T_2989 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 471:101] - node _T_2990 = and(_T_2988, _T_2989) @[el2_lsu_bus_buffer.scala 471:90] - node _T_2991 = or(_T_2983, _T_2990) @[el2_lsu_bus_buffer.scala 470:59] - node _T_2992 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] - node _T_2993 = and(_T_2992, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] - node _T_2994 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 472:63] - node _T_2995 = and(_T_2993, _T_2994) @[el2_lsu_bus_buffer.scala 472:52] - node _T_2996 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 472:82] - node _T_2997 = and(_T_2995, _T_2996) @[el2_lsu_bus_buffer.scala 472:71] - node _T_2998 = or(_T_2991, _T_2997) @[el2_lsu_bus_buffer.scala 471:110] - node _T_2999 = and(_T_2979, _T_2998) @[el2_lsu_bus_buffer.scala 469:112] - node _T_3000 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] - node _T_3001 = and(_T_3000, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 469:93] - node _T_3002 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] - node _T_3003 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] - node _T_3004 = or(_T_3002, _T_3003) @[el2_lsu_bus_buffer.scala 470:32] - node _T_3005 = eq(_T_3004, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] - node _T_3006 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] - node _T_3007 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] - node _T_3008 = and(_T_3006, _T_3007) @[el2_lsu_bus_buffer.scala 471:41] - node _T_3009 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 471:82] - node _T_3010 = and(_T_3008, _T_3009) @[el2_lsu_bus_buffer.scala 471:71] - node _T_3011 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 471:101] - node _T_3012 = and(_T_3010, _T_3011) @[el2_lsu_bus_buffer.scala 471:90] - node _T_3013 = or(_T_3005, _T_3012) @[el2_lsu_bus_buffer.scala 470:59] - node _T_3014 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] - node _T_3015 = and(_T_3014, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] - node _T_3016 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 472:63] - node _T_3017 = and(_T_3015, _T_3016) @[el2_lsu_bus_buffer.scala 472:52] - node _T_3018 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 472:82] - node _T_3019 = and(_T_3017, _T_3018) @[el2_lsu_bus_buffer.scala 472:71] - node _T_3020 = or(_T_3013, _T_3019) @[el2_lsu_bus_buffer.scala 471:110] - node _T_3021 = and(_T_3001, _T_3020) @[el2_lsu_bus_buffer.scala 469:112] - node _T_3022 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] - node _T_3023 = and(_T_3022, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 469:93] - node _T_3024 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] - node _T_3025 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] - node _T_3026 = or(_T_3024, _T_3025) @[el2_lsu_bus_buffer.scala 470:32] - node _T_3027 = eq(_T_3026, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] - node _T_3028 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] - node _T_3029 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] - node _T_3030 = and(_T_3028, _T_3029) @[el2_lsu_bus_buffer.scala 471:41] - node _T_3031 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 471:82] - node _T_3032 = and(_T_3030, _T_3031) @[el2_lsu_bus_buffer.scala 471:71] - node _T_3033 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 471:101] - node _T_3034 = and(_T_3032, _T_3033) @[el2_lsu_bus_buffer.scala 471:90] - node _T_3035 = or(_T_3027, _T_3034) @[el2_lsu_bus_buffer.scala 470:59] - node _T_3036 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] - node _T_3037 = and(_T_3036, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] - node _T_3038 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 472:63] - node _T_3039 = and(_T_3037, _T_3038) @[el2_lsu_bus_buffer.scala 472:52] - node _T_3040 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 472:82] - node _T_3041 = and(_T_3039, _T_3040) @[el2_lsu_bus_buffer.scala 472:71] - node _T_3042 = or(_T_3035, _T_3041) @[el2_lsu_bus_buffer.scala 471:110] - node _T_3043 = and(_T_3023, _T_3042) @[el2_lsu_bus_buffer.scala 469:112] - node _T_3044 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] - node _T_3045 = and(_T_3044, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 469:93] - node _T_3046 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] - node _T_3047 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] - node _T_3048 = or(_T_3046, _T_3047) @[el2_lsu_bus_buffer.scala 470:32] - node _T_3049 = eq(_T_3048, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] - node _T_3050 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] - node _T_3051 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] - node _T_3052 = and(_T_3050, _T_3051) @[el2_lsu_bus_buffer.scala 471:41] - node _T_3053 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 471:82] - node _T_3054 = and(_T_3052, _T_3053) @[el2_lsu_bus_buffer.scala 471:71] - node _T_3055 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 471:101] - node _T_3056 = and(_T_3054, _T_3055) @[el2_lsu_bus_buffer.scala 471:90] - node _T_3057 = or(_T_3049, _T_3056) @[el2_lsu_bus_buffer.scala 470:59] - node _T_3058 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] - node _T_3059 = and(_T_3058, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] - node _T_3060 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 472:63] - node _T_3061 = and(_T_3059, _T_3060) @[el2_lsu_bus_buffer.scala 472:52] - node _T_3062 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 472:82] - node _T_3063 = and(_T_3061, _T_3062) @[el2_lsu_bus_buffer.scala 472:71] - node _T_3064 = or(_T_3057, _T_3063) @[el2_lsu_bus_buffer.scala 471:110] - node _T_3065 = and(_T_3045, _T_3064) @[el2_lsu_bus_buffer.scala 469:112] + node _T_2978 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:82] + node _T_2979 = and(_T_2978, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 470:93] + node _T_2980 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 471:21] + node _T_2981 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 471:47] + node _T_2982 = or(_T_2980, _T_2981) @[el2_lsu_bus_buffer.scala 471:32] + node _T_2983 = eq(_T_2982, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 471:6] + node _T_2984 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:23] + node _T_2985 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:53] + node _T_2986 = and(_T_2984, _T_2985) @[el2_lsu_bus_buffer.scala 472:41] + node _T_2987 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_2988 = and(_T_2986, _T_2987) @[el2_lsu_bus_buffer.scala 472:71] + node _T_2989 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 472:101] + node _T_2990 = and(_T_2988, _T_2989) @[el2_lsu_bus_buffer.scala 472:90] + node _T_2991 = or(_T_2983, _T_2990) @[el2_lsu_bus_buffer.scala 471:59] + node _T_2992 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 473:17] + node _T_2993 = and(_T_2992, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 473:35] + node _T_2994 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 473:63] + node _T_2995 = and(_T_2993, _T_2994) @[el2_lsu_bus_buffer.scala 473:52] + node _T_2996 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 473:82] + node _T_2997 = and(_T_2995, _T_2996) @[el2_lsu_bus_buffer.scala 473:71] + node _T_2998 = or(_T_2991, _T_2997) @[el2_lsu_bus_buffer.scala 472:110] + node _T_2999 = and(_T_2979, _T_2998) @[el2_lsu_bus_buffer.scala 470:112] + node _T_3000 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:82] + node _T_3001 = and(_T_3000, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 470:93] + node _T_3002 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 471:21] + node _T_3003 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 471:47] + node _T_3004 = or(_T_3002, _T_3003) @[el2_lsu_bus_buffer.scala 471:32] + node _T_3005 = eq(_T_3004, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 471:6] + node _T_3006 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:23] + node _T_3007 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:53] + node _T_3008 = and(_T_3006, _T_3007) @[el2_lsu_bus_buffer.scala 472:41] + node _T_3009 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_3010 = and(_T_3008, _T_3009) @[el2_lsu_bus_buffer.scala 472:71] + node _T_3011 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 472:101] + node _T_3012 = and(_T_3010, _T_3011) @[el2_lsu_bus_buffer.scala 472:90] + node _T_3013 = or(_T_3005, _T_3012) @[el2_lsu_bus_buffer.scala 471:59] + node _T_3014 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 473:17] + node _T_3015 = and(_T_3014, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 473:35] + node _T_3016 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 473:63] + node _T_3017 = and(_T_3015, _T_3016) @[el2_lsu_bus_buffer.scala 473:52] + node _T_3018 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 473:82] + node _T_3019 = and(_T_3017, _T_3018) @[el2_lsu_bus_buffer.scala 473:71] + node _T_3020 = or(_T_3013, _T_3019) @[el2_lsu_bus_buffer.scala 472:110] + node _T_3021 = and(_T_3001, _T_3020) @[el2_lsu_bus_buffer.scala 470:112] + node _T_3022 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:82] + node _T_3023 = and(_T_3022, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 470:93] + node _T_3024 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 471:21] + node _T_3025 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 471:47] + node _T_3026 = or(_T_3024, _T_3025) @[el2_lsu_bus_buffer.scala 471:32] + node _T_3027 = eq(_T_3026, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 471:6] + node _T_3028 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:23] + node _T_3029 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:53] + node _T_3030 = and(_T_3028, _T_3029) @[el2_lsu_bus_buffer.scala 472:41] + node _T_3031 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_3032 = and(_T_3030, _T_3031) @[el2_lsu_bus_buffer.scala 472:71] + node _T_3033 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 472:101] + node _T_3034 = and(_T_3032, _T_3033) @[el2_lsu_bus_buffer.scala 472:90] + node _T_3035 = or(_T_3027, _T_3034) @[el2_lsu_bus_buffer.scala 471:59] + node _T_3036 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 473:17] + node _T_3037 = and(_T_3036, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 473:35] + node _T_3038 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 473:63] + node _T_3039 = and(_T_3037, _T_3038) @[el2_lsu_bus_buffer.scala 473:52] + node _T_3040 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 473:82] + node _T_3041 = and(_T_3039, _T_3040) @[el2_lsu_bus_buffer.scala 473:71] + node _T_3042 = or(_T_3035, _T_3041) @[el2_lsu_bus_buffer.scala 472:110] + node _T_3043 = and(_T_3023, _T_3042) @[el2_lsu_bus_buffer.scala 470:112] + node _T_3044 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:82] + node _T_3045 = and(_T_3044, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 470:93] + node _T_3046 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 471:21] + node _T_3047 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 471:47] + node _T_3048 = or(_T_3046, _T_3047) @[el2_lsu_bus_buffer.scala 471:32] + node _T_3049 = eq(_T_3048, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 471:6] + node _T_3050 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:23] + node _T_3051 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:53] + node _T_3052 = and(_T_3050, _T_3051) @[el2_lsu_bus_buffer.scala 472:41] + node _T_3053 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_3054 = and(_T_3052, _T_3053) @[el2_lsu_bus_buffer.scala 472:71] + node _T_3055 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 472:101] + node _T_3056 = and(_T_3054, _T_3055) @[el2_lsu_bus_buffer.scala 472:90] + node _T_3057 = or(_T_3049, _T_3056) @[el2_lsu_bus_buffer.scala 471:59] + node _T_3058 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 473:17] + node _T_3059 = and(_T_3058, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 473:35] + node _T_3060 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 473:63] + node _T_3061 = and(_T_3059, _T_3060) @[el2_lsu_bus_buffer.scala 473:52] + node _T_3062 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 473:82] + node _T_3063 = and(_T_3061, _T_3062) @[el2_lsu_bus_buffer.scala 473:71] + node _T_3064 = or(_T_3057, _T_3063) @[el2_lsu_bus_buffer.scala 472:110] + node _T_3065 = and(_T_3045, _T_3064) @[el2_lsu_bus_buffer.scala 470:112] node _T_3066 = cat(_T_3065, _T_3043) @[Cat.scala 29:58] node _T_3067 = cat(_T_3066, _T_3021) @[Cat.scala 29:58] node _T_3068 = cat(_T_3067, _T_2999) @[Cat.scala 29:58] - node _T_3069 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] - node _T_3070 = and(_T_3069, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 469:93] - node _T_3071 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] - node _T_3072 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] - node _T_3073 = or(_T_3071, _T_3072) @[el2_lsu_bus_buffer.scala 470:32] - node _T_3074 = eq(_T_3073, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] - node _T_3075 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] - node _T_3076 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] - node _T_3077 = and(_T_3075, _T_3076) @[el2_lsu_bus_buffer.scala 471:41] - node _T_3078 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 471:82] - node _T_3079 = and(_T_3077, _T_3078) @[el2_lsu_bus_buffer.scala 471:71] - node _T_3080 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 471:101] - node _T_3081 = and(_T_3079, _T_3080) @[el2_lsu_bus_buffer.scala 471:90] - node _T_3082 = or(_T_3074, _T_3081) @[el2_lsu_bus_buffer.scala 470:59] - node _T_3083 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] - node _T_3084 = and(_T_3083, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] - node _T_3085 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 472:63] - node _T_3086 = and(_T_3084, _T_3085) @[el2_lsu_bus_buffer.scala 472:52] - node _T_3087 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 472:82] - node _T_3088 = and(_T_3086, _T_3087) @[el2_lsu_bus_buffer.scala 472:71] - node _T_3089 = or(_T_3082, _T_3088) @[el2_lsu_bus_buffer.scala 471:110] - node _T_3090 = and(_T_3070, _T_3089) @[el2_lsu_bus_buffer.scala 469:112] - node _T_3091 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] - node _T_3092 = and(_T_3091, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 469:93] - node _T_3093 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] - node _T_3094 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] - node _T_3095 = or(_T_3093, _T_3094) @[el2_lsu_bus_buffer.scala 470:32] - node _T_3096 = eq(_T_3095, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] - node _T_3097 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] - node _T_3098 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] - node _T_3099 = and(_T_3097, _T_3098) @[el2_lsu_bus_buffer.scala 471:41] - node _T_3100 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 471:82] - node _T_3101 = and(_T_3099, _T_3100) @[el2_lsu_bus_buffer.scala 471:71] - node _T_3102 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 471:101] - node _T_3103 = and(_T_3101, _T_3102) @[el2_lsu_bus_buffer.scala 471:90] - node _T_3104 = or(_T_3096, _T_3103) @[el2_lsu_bus_buffer.scala 470:59] - node _T_3105 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] - node _T_3106 = and(_T_3105, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] - node _T_3107 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 472:63] - node _T_3108 = and(_T_3106, _T_3107) @[el2_lsu_bus_buffer.scala 472:52] - node _T_3109 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 472:82] - node _T_3110 = and(_T_3108, _T_3109) @[el2_lsu_bus_buffer.scala 472:71] - node _T_3111 = or(_T_3104, _T_3110) @[el2_lsu_bus_buffer.scala 471:110] - node _T_3112 = and(_T_3092, _T_3111) @[el2_lsu_bus_buffer.scala 469:112] - node _T_3113 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] - node _T_3114 = and(_T_3113, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 469:93] - node _T_3115 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] - node _T_3116 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] - node _T_3117 = or(_T_3115, _T_3116) @[el2_lsu_bus_buffer.scala 470:32] - node _T_3118 = eq(_T_3117, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] - node _T_3119 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] - node _T_3120 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] - node _T_3121 = and(_T_3119, _T_3120) @[el2_lsu_bus_buffer.scala 471:41] - node _T_3122 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 471:82] - node _T_3123 = and(_T_3121, _T_3122) @[el2_lsu_bus_buffer.scala 471:71] - node _T_3124 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 471:101] - node _T_3125 = and(_T_3123, _T_3124) @[el2_lsu_bus_buffer.scala 471:90] - node _T_3126 = or(_T_3118, _T_3125) @[el2_lsu_bus_buffer.scala 470:59] - node _T_3127 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] - node _T_3128 = and(_T_3127, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] - node _T_3129 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 472:63] - node _T_3130 = and(_T_3128, _T_3129) @[el2_lsu_bus_buffer.scala 472:52] - node _T_3131 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 472:82] - node _T_3132 = and(_T_3130, _T_3131) @[el2_lsu_bus_buffer.scala 472:71] - node _T_3133 = or(_T_3126, _T_3132) @[el2_lsu_bus_buffer.scala 471:110] - node _T_3134 = and(_T_3114, _T_3133) @[el2_lsu_bus_buffer.scala 469:112] - node _T_3135 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] - node _T_3136 = and(_T_3135, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 469:93] - node _T_3137 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] - node _T_3138 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] - node _T_3139 = or(_T_3137, _T_3138) @[el2_lsu_bus_buffer.scala 470:32] - node _T_3140 = eq(_T_3139, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] - node _T_3141 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] - node _T_3142 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] - node _T_3143 = and(_T_3141, _T_3142) @[el2_lsu_bus_buffer.scala 471:41] - node _T_3144 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 471:82] - node _T_3145 = and(_T_3143, _T_3144) @[el2_lsu_bus_buffer.scala 471:71] - node _T_3146 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 471:101] - node _T_3147 = and(_T_3145, _T_3146) @[el2_lsu_bus_buffer.scala 471:90] - node _T_3148 = or(_T_3140, _T_3147) @[el2_lsu_bus_buffer.scala 470:59] - node _T_3149 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] - node _T_3150 = and(_T_3149, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] - node _T_3151 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 472:63] - node _T_3152 = and(_T_3150, _T_3151) @[el2_lsu_bus_buffer.scala 472:52] - node _T_3153 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 472:82] - node _T_3154 = and(_T_3152, _T_3153) @[el2_lsu_bus_buffer.scala 472:71] - node _T_3155 = or(_T_3148, _T_3154) @[el2_lsu_bus_buffer.scala 471:110] - node _T_3156 = and(_T_3136, _T_3155) @[el2_lsu_bus_buffer.scala 469:112] + node _T_3069 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:82] + node _T_3070 = and(_T_3069, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 470:93] + node _T_3071 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 471:21] + node _T_3072 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 471:47] + node _T_3073 = or(_T_3071, _T_3072) @[el2_lsu_bus_buffer.scala 471:32] + node _T_3074 = eq(_T_3073, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 471:6] + node _T_3075 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:23] + node _T_3076 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:53] + node _T_3077 = and(_T_3075, _T_3076) @[el2_lsu_bus_buffer.scala 472:41] + node _T_3078 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_3079 = and(_T_3077, _T_3078) @[el2_lsu_bus_buffer.scala 472:71] + node _T_3080 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 472:101] + node _T_3081 = and(_T_3079, _T_3080) @[el2_lsu_bus_buffer.scala 472:90] + node _T_3082 = or(_T_3074, _T_3081) @[el2_lsu_bus_buffer.scala 471:59] + node _T_3083 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 473:17] + node _T_3084 = and(_T_3083, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 473:35] + node _T_3085 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 473:63] + node _T_3086 = and(_T_3084, _T_3085) @[el2_lsu_bus_buffer.scala 473:52] + node _T_3087 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 473:82] + node _T_3088 = and(_T_3086, _T_3087) @[el2_lsu_bus_buffer.scala 473:71] + node _T_3089 = or(_T_3082, _T_3088) @[el2_lsu_bus_buffer.scala 472:110] + node _T_3090 = and(_T_3070, _T_3089) @[el2_lsu_bus_buffer.scala 470:112] + node _T_3091 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:82] + node _T_3092 = and(_T_3091, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 470:93] + node _T_3093 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 471:21] + node _T_3094 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 471:47] + node _T_3095 = or(_T_3093, _T_3094) @[el2_lsu_bus_buffer.scala 471:32] + node _T_3096 = eq(_T_3095, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 471:6] + node _T_3097 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:23] + node _T_3098 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:53] + node _T_3099 = and(_T_3097, _T_3098) @[el2_lsu_bus_buffer.scala 472:41] + node _T_3100 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_3101 = and(_T_3099, _T_3100) @[el2_lsu_bus_buffer.scala 472:71] + node _T_3102 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 472:101] + node _T_3103 = and(_T_3101, _T_3102) @[el2_lsu_bus_buffer.scala 472:90] + node _T_3104 = or(_T_3096, _T_3103) @[el2_lsu_bus_buffer.scala 471:59] + node _T_3105 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 473:17] + node _T_3106 = and(_T_3105, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 473:35] + node _T_3107 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 473:63] + node _T_3108 = and(_T_3106, _T_3107) @[el2_lsu_bus_buffer.scala 473:52] + node _T_3109 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 473:82] + node _T_3110 = and(_T_3108, _T_3109) @[el2_lsu_bus_buffer.scala 473:71] + node _T_3111 = or(_T_3104, _T_3110) @[el2_lsu_bus_buffer.scala 472:110] + node _T_3112 = and(_T_3092, _T_3111) @[el2_lsu_bus_buffer.scala 470:112] + node _T_3113 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:82] + node _T_3114 = and(_T_3113, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 470:93] + node _T_3115 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 471:21] + node _T_3116 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 471:47] + node _T_3117 = or(_T_3115, _T_3116) @[el2_lsu_bus_buffer.scala 471:32] + node _T_3118 = eq(_T_3117, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 471:6] + node _T_3119 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:23] + node _T_3120 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:53] + node _T_3121 = and(_T_3119, _T_3120) @[el2_lsu_bus_buffer.scala 472:41] + node _T_3122 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_3123 = and(_T_3121, _T_3122) @[el2_lsu_bus_buffer.scala 472:71] + node _T_3124 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 472:101] + node _T_3125 = and(_T_3123, _T_3124) @[el2_lsu_bus_buffer.scala 472:90] + node _T_3126 = or(_T_3118, _T_3125) @[el2_lsu_bus_buffer.scala 471:59] + node _T_3127 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 473:17] + node _T_3128 = and(_T_3127, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 473:35] + node _T_3129 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 473:63] + node _T_3130 = and(_T_3128, _T_3129) @[el2_lsu_bus_buffer.scala 473:52] + node _T_3131 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 473:82] + node _T_3132 = and(_T_3130, _T_3131) @[el2_lsu_bus_buffer.scala 473:71] + node _T_3133 = or(_T_3126, _T_3132) @[el2_lsu_bus_buffer.scala 472:110] + node _T_3134 = and(_T_3114, _T_3133) @[el2_lsu_bus_buffer.scala 470:112] + node _T_3135 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:82] + node _T_3136 = and(_T_3135, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 470:93] + node _T_3137 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 471:21] + node _T_3138 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 471:47] + node _T_3139 = or(_T_3137, _T_3138) @[el2_lsu_bus_buffer.scala 471:32] + node _T_3140 = eq(_T_3139, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 471:6] + node _T_3141 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:23] + node _T_3142 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:53] + node _T_3143 = and(_T_3141, _T_3142) @[el2_lsu_bus_buffer.scala 472:41] + node _T_3144 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_3145 = and(_T_3143, _T_3144) @[el2_lsu_bus_buffer.scala 472:71] + node _T_3146 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 472:101] + node _T_3147 = and(_T_3145, _T_3146) @[el2_lsu_bus_buffer.scala 472:90] + node _T_3148 = or(_T_3140, _T_3147) @[el2_lsu_bus_buffer.scala 471:59] + node _T_3149 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 473:17] + node _T_3150 = and(_T_3149, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 473:35] + node _T_3151 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 473:63] + node _T_3152 = and(_T_3150, _T_3151) @[el2_lsu_bus_buffer.scala 473:52] + node _T_3153 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 473:82] + node _T_3154 = and(_T_3152, _T_3153) @[el2_lsu_bus_buffer.scala 473:71] + node _T_3155 = or(_T_3148, _T_3154) @[el2_lsu_bus_buffer.scala 472:110] + node _T_3156 = and(_T_3136, _T_3155) @[el2_lsu_bus_buffer.scala 470:112] node _T_3157 = cat(_T_3156, _T_3134) @[Cat.scala 29:58] node _T_3158 = cat(_T_3157, _T_3112) @[Cat.scala 29:58] node _T_3159 = cat(_T_3158, _T_3090) @[Cat.scala 29:58] - buf_rspage_set[0] <= _T_2886 @[el2_lsu_bus_buffer.scala 469:18] - buf_rspage_set[1] <= _T_2977 @[el2_lsu_bus_buffer.scala 469:18] - buf_rspage_set[2] <= _T_3068 @[el2_lsu_bus_buffer.scala 469:18] - buf_rspage_set[3] <= _T_3159 @[el2_lsu_bus_buffer.scala 469:18] - node _T_3160 = bits(buf_rspage_set[0], 0, 0) @[el2_lsu_bus_buffer.scala 473:84] - node _T_3161 = bits(buf_rspage[0], 0, 0) @[el2_lsu_bus_buffer.scala 473:103] - node _T_3162 = or(_T_3160, _T_3161) @[el2_lsu_bus_buffer.scala 473:88] - node _T_3163 = bits(buf_rspage_set[0], 1, 1) @[el2_lsu_bus_buffer.scala 473:84] - node _T_3164 = bits(buf_rspage[0], 1, 1) @[el2_lsu_bus_buffer.scala 473:103] - node _T_3165 = or(_T_3163, _T_3164) @[el2_lsu_bus_buffer.scala 473:88] - node _T_3166 = bits(buf_rspage_set[0], 2, 2) @[el2_lsu_bus_buffer.scala 473:84] - node _T_3167 = bits(buf_rspage[0], 2, 2) @[el2_lsu_bus_buffer.scala 473:103] - node _T_3168 = or(_T_3166, _T_3167) @[el2_lsu_bus_buffer.scala 473:88] - node _T_3169 = bits(buf_rspage_set[0], 3, 3) @[el2_lsu_bus_buffer.scala 473:84] - node _T_3170 = bits(buf_rspage[0], 3, 3) @[el2_lsu_bus_buffer.scala 473:103] - node _T_3171 = or(_T_3169, _T_3170) @[el2_lsu_bus_buffer.scala 473:88] + buf_rspage_set[0] <= _T_2886 @[el2_lsu_bus_buffer.scala 470:18] + buf_rspage_set[1] <= _T_2977 @[el2_lsu_bus_buffer.scala 470:18] + buf_rspage_set[2] <= _T_3068 @[el2_lsu_bus_buffer.scala 470:18] + buf_rspage_set[3] <= _T_3159 @[el2_lsu_bus_buffer.scala 470:18] + node _T_3160 = bits(buf_rspage_set[0], 0, 0) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3161 = bits(buf_rspage[0], 0, 0) @[el2_lsu_bus_buffer.scala 474:103] + node _T_3162 = or(_T_3160, _T_3161) @[el2_lsu_bus_buffer.scala 474:88] + node _T_3163 = bits(buf_rspage_set[0], 1, 1) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3164 = bits(buf_rspage[0], 1, 1) @[el2_lsu_bus_buffer.scala 474:103] + node _T_3165 = or(_T_3163, _T_3164) @[el2_lsu_bus_buffer.scala 474:88] + node _T_3166 = bits(buf_rspage_set[0], 2, 2) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3167 = bits(buf_rspage[0], 2, 2) @[el2_lsu_bus_buffer.scala 474:103] + node _T_3168 = or(_T_3166, _T_3167) @[el2_lsu_bus_buffer.scala 474:88] + node _T_3169 = bits(buf_rspage_set[0], 3, 3) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3170 = bits(buf_rspage[0], 3, 3) @[el2_lsu_bus_buffer.scala 474:103] + node _T_3171 = or(_T_3169, _T_3170) @[el2_lsu_bus_buffer.scala 474:88] node _T_3172 = cat(_T_3171, _T_3168) @[Cat.scala 29:58] node _T_3173 = cat(_T_3172, _T_3165) @[Cat.scala 29:58] node _T_3174 = cat(_T_3173, _T_3162) @[Cat.scala 29:58] - node _T_3175 = bits(buf_rspage_set[1], 0, 0) @[el2_lsu_bus_buffer.scala 473:84] - node _T_3176 = bits(buf_rspage[1], 0, 0) @[el2_lsu_bus_buffer.scala 473:103] - node _T_3177 = or(_T_3175, _T_3176) @[el2_lsu_bus_buffer.scala 473:88] - node _T_3178 = bits(buf_rspage_set[1], 1, 1) @[el2_lsu_bus_buffer.scala 473:84] - node _T_3179 = bits(buf_rspage[1], 1, 1) @[el2_lsu_bus_buffer.scala 473:103] - node _T_3180 = or(_T_3178, _T_3179) @[el2_lsu_bus_buffer.scala 473:88] - node _T_3181 = bits(buf_rspage_set[1], 2, 2) @[el2_lsu_bus_buffer.scala 473:84] - node _T_3182 = bits(buf_rspage[1], 2, 2) @[el2_lsu_bus_buffer.scala 473:103] - node _T_3183 = or(_T_3181, _T_3182) @[el2_lsu_bus_buffer.scala 473:88] - node _T_3184 = bits(buf_rspage_set[1], 3, 3) @[el2_lsu_bus_buffer.scala 473:84] - node _T_3185 = bits(buf_rspage[1], 3, 3) @[el2_lsu_bus_buffer.scala 473:103] - node _T_3186 = or(_T_3184, _T_3185) @[el2_lsu_bus_buffer.scala 473:88] + node _T_3175 = bits(buf_rspage_set[1], 0, 0) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3176 = bits(buf_rspage[1], 0, 0) @[el2_lsu_bus_buffer.scala 474:103] + node _T_3177 = or(_T_3175, _T_3176) @[el2_lsu_bus_buffer.scala 474:88] + node _T_3178 = bits(buf_rspage_set[1], 1, 1) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3179 = bits(buf_rspage[1], 1, 1) @[el2_lsu_bus_buffer.scala 474:103] + node _T_3180 = or(_T_3178, _T_3179) @[el2_lsu_bus_buffer.scala 474:88] + node _T_3181 = bits(buf_rspage_set[1], 2, 2) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3182 = bits(buf_rspage[1], 2, 2) @[el2_lsu_bus_buffer.scala 474:103] + node _T_3183 = or(_T_3181, _T_3182) @[el2_lsu_bus_buffer.scala 474:88] + node _T_3184 = bits(buf_rspage_set[1], 3, 3) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3185 = bits(buf_rspage[1], 3, 3) @[el2_lsu_bus_buffer.scala 474:103] + node _T_3186 = or(_T_3184, _T_3185) @[el2_lsu_bus_buffer.scala 474:88] node _T_3187 = cat(_T_3186, _T_3183) @[Cat.scala 29:58] node _T_3188 = cat(_T_3187, _T_3180) @[Cat.scala 29:58] node _T_3189 = cat(_T_3188, _T_3177) @[Cat.scala 29:58] - node _T_3190 = bits(buf_rspage_set[2], 0, 0) @[el2_lsu_bus_buffer.scala 473:84] - node _T_3191 = bits(buf_rspage[2], 0, 0) @[el2_lsu_bus_buffer.scala 473:103] - node _T_3192 = or(_T_3190, _T_3191) @[el2_lsu_bus_buffer.scala 473:88] - node _T_3193 = bits(buf_rspage_set[2], 1, 1) @[el2_lsu_bus_buffer.scala 473:84] - node _T_3194 = bits(buf_rspage[2], 1, 1) @[el2_lsu_bus_buffer.scala 473:103] - node _T_3195 = or(_T_3193, _T_3194) @[el2_lsu_bus_buffer.scala 473:88] - node _T_3196 = bits(buf_rspage_set[2], 2, 2) @[el2_lsu_bus_buffer.scala 473:84] - node _T_3197 = bits(buf_rspage[2], 2, 2) @[el2_lsu_bus_buffer.scala 473:103] - node _T_3198 = or(_T_3196, _T_3197) @[el2_lsu_bus_buffer.scala 473:88] - node _T_3199 = bits(buf_rspage_set[2], 3, 3) @[el2_lsu_bus_buffer.scala 473:84] - node _T_3200 = bits(buf_rspage[2], 3, 3) @[el2_lsu_bus_buffer.scala 473:103] - node _T_3201 = or(_T_3199, _T_3200) @[el2_lsu_bus_buffer.scala 473:88] + node _T_3190 = bits(buf_rspage_set[2], 0, 0) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3191 = bits(buf_rspage[2], 0, 0) @[el2_lsu_bus_buffer.scala 474:103] + node _T_3192 = or(_T_3190, _T_3191) @[el2_lsu_bus_buffer.scala 474:88] + node _T_3193 = bits(buf_rspage_set[2], 1, 1) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3194 = bits(buf_rspage[2], 1, 1) @[el2_lsu_bus_buffer.scala 474:103] + node _T_3195 = or(_T_3193, _T_3194) @[el2_lsu_bus_buffer.scala 474:88] + node _T_3196 = bits(buf_rspage_set[2], 2, 2) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3197 = bits(buf_rspage[2], 2, 2) @[el2_lsu_bus_buffer.scala 474:103] + node _T_3198 = or(_T_3196, _T_3197) @[el2_lsu_bus_buffer.scala 474:88] + node _T_3199 = bits(buf_rspage_set[2], 3, 3) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3200 = bits(buf_rspage[2], 3, 3) @[el2_lsu_bus_buffer.scala 474:103] + node _T_3201 = or(_T_3199, _T_3200) @[el2_lsu_bus_buffer.scala 474:88] node _T_3202 = cat(_T_3201, _T_3198) @[Cat.scala 29:58] node _T_3203 = cat(_T_3202, _T_3195) @[Cat.scala 29:58] node _T_3204 = cat(_T_3203, _T_3192) @[Cat.scala 29:58] - node _T_3205 = bits(buf_rspage_set[3], 0, 0) @[el2_lsu_bus_buffer.scala 473:84] - node _T_3206 = bits(buf_rspage[3], 0, 0) @[el2_lsu_bus_buffer.scala 473:103] - node _T_3207 = or(_T_3205, _T_3206) @[el2_lsu_bus_buffer.scala 473:88] - node _T_3208 = bits(buf_rspage_set[3], 1, 1) @[el2_lsu_bus_buffer.scala 473:84] - node _T_3209 = bits(buf_rspage[3], 1, 1) @[el2_lsu_bus_buffer.scala 473:103] - node _T_3210 = or(_T_3208, _T_3209) @[el2_lsu_bus_buffer.scala 473:88] - node _T_3211 = bits(buf_rspage_set[3], 2, 2) @[el2_lsu_bus_buffer.scala 473:84] - node _T_3212 = bits(buf_rspage[3], 2, 2) @[el2_lsu_bus_buffer.scala 473:103] - node _T_3213 = or(_T_3211, _T_3212) @[el2_lsu_bus_buffer.scala 473:88] - node _T_3214 = bits(buf_rspage_set[3], 3, 3) @[el2_lsu_bus_buffer.scala 473:84] - node _T_3215 = bits(buf_rspage[3], 3, 3) @[el2_lsu_bus_buffer.scala 473:103] - node _T_3216 = or(_T_3214, _T_3215) @[el2_lsu_bus_buffer.scala 473:88] + node _T_3205 = bits(buf_rspage_set[3], 0, 0) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3206 = bits(buf_rspage[3], 0, 0) @[el2_lsu_bus_buffer.scala 474:103] + node _T_3207 = or(_T_3205, _T_3206) @[el2_lsu_bus_buffer.scala 474:88] + node _T_3208 = bits(buf_rspage_set[3], 1, 1) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3209 = bits(buf_rspage[3], 1, 1) @[el2_lsu_bus_buffer.scala 474:103] + node _T_3210 = or(_T_3208, _T_3209) @[el2_lsu_bus_buffer.scala 474:88] + node _T_3211 = bits(buf_rspage_set[3], 2, 2) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3212 = bits(buf_rspage[3], 2, 2) @[el2_lsu_bus_buffer.scala 474:103] + node _T_3213 = or(_T_3211, _T_3212) @[el2_lsu_bus_buffer.scala 474:88] + node _T_3214 = bits(buf_rspage_set[3], 3, 3) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3215 = bits(buf_rspage[3], 3, 3) @[el2_lsu_bus_buffer.scala 474:103] + node _T_3216 = or(_T_3214, _T_3215) @[el2_lsu_bus_buffer.scala 474:88] node _T_3217 = cat(_T_3216, _T_3213) @[Cat.scala 29:58] node _T_3218 = cat(_T_3217, _T_3210) @[Cat.scala 29:58] node _T_3219 = cat(_T_3218, _T_3207) @[Cat.scala 29:58] - buf_rspage_in[0] <= _T_3174 @[el2_lsu_bus_buffer.scala 473:17] - buf_rspage_in[1] <= _T_3189 @[el2_lsu_bus_buffer.scala 473:17] - buf_rspage_in[2] <= _T_3204 @[el2_lsu_bus_buffer.scala 473:17] - buf_rspage_in[3] <= _T_3219 @[el2_lsu_bus_buffer.scala 473:17] - node _T_3220 = bits(buf_rspageQ[0], 0, 0) @[el2_lsu_bus_buffer.scala 474:78] - node _T_3221 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] - node _T_3222 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] - node _T_3223 = or(_T_3221, _T_3222) @[el2_lsu_bus_buffer.scala 474:110] - node _T_3224 = eq(_T_3223, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] - node _T_3225 = and(_T_3220, _T_3224) @[el2_lsu_bus_buffer.scala 474:82] - node _T_3226 = bits(buf_rspageQ[0], 1, 1) @[el2_lsu_bus_buffer.scala 474:78] - node _T_3227 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] - node _T_3228 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] - node _T_3229 = or(_T_3227, _T_3228) @[el2_lsu_bus_buffer.scala 474:110] - node _T_3230 = eq(_T_3229, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] - node _T_3231 = and(_T_3226, _T_3230) @[el2_lsu_bus_buffer.scala 474:82] - node _T_3232 = bits(buf_rspageQ[0], 2, 2) @[el2_lsu_bus_buffer.scala 474:78] - node _T_3233 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] - node _T_3234 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] - node _T_3235 = or(_T_3233, _T_3234) @[el2_lsu_bus_buffer.scala 474:110] - node _T_3236 = eq(_T_3235, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] - node _T_3237 = and(_T_3232, _T_3236) @[el2_lsu_bus_buffer.scala 474:82] - node _T_3238 = bits(buf_rspageQ[0], 3, 3) @[el2_lsu_bus_buffer.scala 474:78] - node _T_3239 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] - node _T_3240 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] - node _T_3241 = or(_T_3239, _T_3240) @[el2_lsu_bus_buffer.scala 474:110] - node _T_3242 = eq(_T_3241, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] - node _T_3243 = and(_T_3238, _T_3242) @[el2_lsu_bus_buffer.scala 474:82] + buf_rspage_in[0] <= _T_3174 @[el2_lsu_bus_buffer.scala 474:17] + buf_rspage_in[1] <= _T_3189 @[el2_lsu_bus_buffer.scala 474:17] + buf_rspage_in[2] <= _T_3204 @[el2_lsu_bus_buffer.scala 474:17] + buf_rspage_in[3] <= _T_3219 @[el2_lsu_bus_buffer.scala 474:17] + node _T_3220 = bits(buf_rspageQ[0], 0, 0) @[el2_lsu_bus_buffer.scala 475:78] + node _T_3221 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 475:99] + node _T_3222 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 475:125] + node _T_3223 = or(_T_3221, _T_3222) @[el2_lsu_bus_buffer.scala 475:110] + node _T_3224 = eq(_T_3223, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 475:84] + node _T_3225 = and(_T_3220, _T_3224) @[el2_lsu_bus_buffer.scala 475:82] + node _T_3226 = bits(buf_rspageQ[0], 1, 1) @[el2_lsu_bus_buffer.scala 475:78] + node _T_3227 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 475:99] + node _T_3228 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 475:125] + node _T_3229 = or(_T_3227, _T_3228) @[el2_lsu_bus_buffer.scala 475:110] + node _T_3230 = eq(_T_3229, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 475:84] + node _T_3231 = and(_T_3226, _T_3230) @[el2_lsu_bus_buffer.scala 475:82] + node _T_3232 = bits(buf_rspageQ[0], 2, 2) @[el2_lsu_bus_buffer.scala 475:78] + node _T_3233 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 475:99] + node _T_3234 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 475:125] + node _T_3235 = or(_T_3233, _T_3234) @[el2_lsu_bus_buffer.scala 475:110] + node _T_3236 = eq(_T_3235, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 475:84] + node _T_3237 = and(_T_3232, _T_3236) @[el2_lsu_bus_buffer.scala 475:82] + node _T_3238 = bits(buf_rspageQ[0], 3, 3) @[el2_lsu_bus_buffer.scala 475:78] + node _T_3239 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 475:99] + node _T_3240 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 475:125] + node _T_3241 = or(_T_3239, _T_3240) @[el2_lsu_bus_buffer.scala 475:110] + node _T_3242 = eq(_T_3241, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 475:84] + node _T_3243 = and(_T_3238, _T_3242) @[el2_lsu_bus_buffer.scala 475:82] node _T_3244 = cat(_T_3243, _T_3237) @[Cat.scala 29:58] node _T_3245 = cat(_T_3244, _T_3231) @[Cat.scala 29:58] node _T_3246 = cat(_T_3245, _T_3225) @[Cat.scala 29:58] - node _T_3247 = bits(buf_rspageQ[1], 0, 0) @[el2_lsu_bus_buffer.scala 474:78] - node _T_3248 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] - node _T_3249 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] - node _T_3250 = or(_T_3248, _T_3249) @[el2_lsu_bus_buffer.scala 474:110] - node _T_3251 = eq(_T_3250, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] - node _T_3252 = and(_T_3247, _T_3251) @[el2_lsu_bus_buffer.scala 474:82] - node _T_3253 = bits(buf_rspageQ[1], 1, 1) @[el2_lsu_bus_buffer.scala 474:78] - node _T_3254 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] - node _T_3255 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] - node _T_3256 = or(_T_3254, _T_3255) @[el2_lsu_bus_buffer.scala 474:110] - node _T_3257 = eq(_T_3256, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] - node _T_3258 = and(_T_3253, _T_3257) @[el2_lsu_bus_buffer.scala 474:82] - node _T_3259 = bits(buf_rspageQ[1], 2, 2) @[el2_lsu_bus_buffer.scala 474:78] - node _T_3260 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] - node _T_3261 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] - node _T_3262 = or(_T_3260, _T_3261) @[el2_lsu_bus_buffer.scala 474:110] - node _T_3263 = eq(_T_3262, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] - node _T_3264 = and(_T_3259, _T_3263) @[el2_lsu_bus_buffer.scala 474:82] - node _T_3265 = bits(buf_rspageQ[1], 3, 3) @[el2_lsu_bus_buffer.scala 474:78] - node _T_3266 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] - node _T_3267 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] - node _T_3268 = or(_T_3266, _T_3267) @[el2_lsu_bus_buffer.scala 474:110] - node _T_3269 = eq(_T_3268, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] - node _T_3270 = and(_T_3265, _T_3269) @[el2_lsu_bus_buffer.scala 474:82] + node _T_3247 = bits(buf_rspageQ[1], 0, 0) @[el2_lsu_bus_buffer.scala 475:78] + node _T_3248 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 475:99] + node _T_3249 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 475:125] + node _T_3250 = or(_T_3248, _T_3249) @[el2_lsu_bus_buffer.scala 475:110] + node _T_3251 = eq(_T_3250, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 475:84] + node _T_3252 = and(_T_3247, _T_3251) @[el2_lsu_bus_buffer.scala 475:82] + node _T_3253 = bits(buf_rspageQ[1], 1, 1) @[el2_lsu_bus_buffer.scala 475:78] + node _T_3254 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 475:99] + node _T_3255 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 475:125] + node _T_3256 = or(_T_3254, _T_3255) @[el2_lsu_bus_buffer.scala 475:110] + node _T_3257 = eq(_T_3256, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 475:84] + node _T_3258 = and(_T_3253, _T_3257) @[el2_lsu_bus_buffer.scala 475:82] + node _T_3259 = bits(buf_rspageQ[1], 2, 2) @[el2_lsu_bus_buffer.scala 475:78] + node _T_3260 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 475:99] + node _T_3261 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 475:125] + node _T_3262 = or(_T_3260, _T_3261) @[el2_lsu_bus_buffer.scala 475:110] + node _T_3263 = eq(_T_3262, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 475:84] + node _T_3264 = and(_T_3259, _T_3263) @[el2_lsu_bus_buffer.scala 475:82] + node _T_3265 = bits(buf_rspageQ[1], 3, 3) @[el2_lsu_bus_buffer.scala 475:78] + node _T_3266 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 475:99] + node _T_3267 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 475:125] + node _T_3268 = or(_T_3266, _T_3267) @[el2_lsu_bus_buffer.scala 475:110] + node _T_3269 = eq(_T_3268, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 475:84] + node _T_3270 = and(_T_3265, _T_3269) @[el2_lsu_bus_buffer.scala 475:82] node _T_3271 = cat(_T_3270, _T_3264) @[Cat.scala 29:58] node _T_3272 = cat(_T_3271, _T_3258) @[Cat.scala 29:58] node _T_3273 = cat(_T_3272, _T_3252) @[Cat.scala 29:58] - node _T_3274 = bits(buf_rspageQ[2], 0, 0) @[el2_lsu_bus_buffer.scala 474:78] - node _T_3275 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] - node _T_3276 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] - node _T_3277 = or(_T_3275, _T_3276) @[el2_lsu_bus_buffer.scala 474:110] - node _T_3278 = eq(_T_3277, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] - node _T_3279 = and(_T_3274, _T_3278) @[el2_lsu_bus_buffer.scala 474:82] - node _T_3280 = bits(buf_rspageQ[2], 1, 1) @[el2_lsu_bus_buffer.scala 474:78] - node _T_3281 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] - node _T_3282 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] - node _T_3283 = or(_T_3281, _T_3282) @[el2_lsu_bus_buffer.scala 474:110] - node _T_3284 = eq(_T_3283, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] - node _T_3285 = and(_T_3280, _T_3284) @[el2_lsu_bus_buffer.scala 474:82] - node _T_3286 = bits(buf_rspageQ[2], 2, 2) @[el2_lsu_bus_buffer.scala 474:78] - node _T_3287 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] - node _T_3288 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] - node _T_3289 = or(_T_3287, _T_3288) @[el2_lsu_bus_buffer.scala 474:110] - node _T_3290 = eq(_T_3289, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] - node _T_3291 = and(_T_3286, _T_3290) @[el2_lsu_bus_buffer.scala 474:82] - node _T_3292 = bits(buf_rspageQ[2], 3, 3) @[el2_lsu_bus_buffer.scala 474:78] - node _T_3293 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] - node _T_3294 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] - node _T_3295 = or(_T_3293, _T_3294) @[el2_lsu_bus_buffer.scala 474:110] - node _T_3296 = eq(_T_3295, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] - node _T_3297 = and(_T_3292, _T_3296) @[el2_lsu_bus_buffer.scala 474:82] + node _T_3274 = bits(buf_rspageQ[2], 0, 0) @[el2_lsu_bus_buffer.scala 475:78] + node _T_3275 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 475:99] + node _T_3276 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 475:125] + node _T_3277 = or(_T_3275, _T_3276) @[el2_lsu_bus_buffer.scala 475:110] + node _T_3278 = eq(_T_3277, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 475:84] + node _T_3279 = and(_T_3274, _T_3278) @[el2_lsu_bus_buffer.scala 475:82] + node _T_3280 = bits(buf_rspageQ[2], 1, 1) @[el2_lsu_bus_buffer.scala 475:78] + node _T_3281 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 475:99] + node _T_3282 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 475:125] + node _T_3283 = or(_T_3281, _T_3282) @[el2_lsu_bus_buffer.scala 475:110] + node _T_3284 = eq(_T_3283, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 475:84] + node _T_3285 = and(_T_3280, _T_3284) @[el2_lsu_bus_buffer.scala 475:82] + node _T_3286 = bits(buf_rspageQ[2], 2, 2) @[el2_lsu_bus_buffer.scala 475:78] + node _T_3287 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 475:99] + node _T_3288 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 475:125] + node _T_3289 = or(_T_3287, _T_3288) @[el2_lsu_bus_buffer.scala 475:110] + node _T_3290 = eq(_T_3289, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 475:84] + node _T_3291 = and(_T_3286, _T_3290) @[el2_lsu_bus_buffer.scala 475:82] + node _T_3292 = bits(buf_rspageQ[2], 3, 3) @[el2_lsu_bus_buffer.scala 475:78] + node _T_3293 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 475:99] + node _T_3294 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 475:125] + node _T_3295 = or(_T_3293, _T_3294) @[el2_lsu_bus_buffer.scala 475:110] + node _T_3296 = eq(_T_3295, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 475:84] + node _T_3297 = and(_T_3292, _T_3296) @[el2_lsu_bus_buffer.scala 475:82] node _T_3298 = cat(_T_3297, _T_3291) @[Cat.scala 29:58] node _T_3299 = cat(_T_3298, _T_3285) @[Cat.scala 29:58] node _T_3300 = cat(_T_3299, _T_3279) @[Cat.scala 29:58] - node _T_3301 = bits(buf_rspageQ[3], 0, 0) @[el2_lsu_bus_buffer.scala 474:78] - node _T_3302 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] - node _T_3303 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] - node _T_3304 = or(_T_3302, _T_3303) @[el2_lsu_bus_buffer.scala 474:110] - node _T_3305 = eq(_T_3304, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] - node _T_3306 = and(_T_3301, _T_3305) @[el2_lsu_bus_buffer.scala 474:82] - node _T_3307 = bits(buf_rspageQ[3], 1, 1) @[el2_lsu_bus_buffer.scala 474:78] - node _T_3308 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] - node _T_3309 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] - node _T_3310 = or(_T_3308, _T_3309) @[el2_lsu_bus_buffer.scala 474:110] - node _T_3311 = eq(_T_3310, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] - node _T_3312 = and(_T_3307, _T_3311) @[el2_lsu_bus_buffer.scala 474:82] - node _T_3313 = bits(buf_rspageQ[3], 2, 2) @[el2_lsu_bus_buffer.scala 474:78] - node _T_3314 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] - node _T_3315 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] - node _T_3316 = or(_T_3314, _T_3315) @[el2_lsu_bus_buffer.scala 474:110] - node _T_3317 = eq(_T_3316, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] - node _T_3318 = and(_T_3313, _T_3317) @[el2_lsu_bus_buffer.scala 474:82] - node _T_3319 = bits(buf_rspageQ[3], 3, 3) @[el2_lsu_bus_buffer.scala 474:78] - node _T_3320 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] - node _T_3321 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] - node _T_3322 = or(_T_3320, _T_3321) @[el2_lsu_bus_buffer.scala 474:110] - node _T_3323 = eq(_T_3322, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] - node _T_3324 = and(_T_3319, _T_3323) @[el2_lsu_bus_buffer.scala 474:82] + node _T_3301 = bits(buf_rspageQ[3], 0, 0) @[el2_lsu_bus_buffer.scala 475:78] + node _T_3302 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 475:99] + node _T_3303 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 475:125] + node _T_3304 = or(_T_3302, _T_3303) @[el2_lsu_bus_buffer.scala 475:110] + node _T_3305 = eq(_T_3304, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 475:84] + node _T_3306 = and(_T_3301, _T_3305) @[el2_lsu_bus_buffer.scala 475:82] + node _T_3307 = bits(buf_rspageQ[3], 1, 1) @[el2_lsu_bus_buffer.scala 475:78] + node _T_3308 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 475:99] + node _T_3309 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 475:125] + node _T_3310 = or(_T_3308, _T_3309) @[el2_lsu_bus_buffer.scala 475:110] + node _T_3311 = eq(_T_3310, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 475:84] + node _T_3312 = and(_T_3307, _T_3311) @[el2_lsu_bus_buffer.scala 475:82] + node _T_3313 = bits(buf_rspageQ[3], 2, 2) @[el2_lsu_bus_buffer.scala 475:78] + node _T_3314 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 475:99] + node _T_3315 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 475:125] + node _T_3316 = or(_T_3314, _T_3315) @[el2_lsu_bus_buffer.scala 475:110] + node _T_3317 = eq(_T_3316, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 475:84] + node _T_3318 = and(_T_3313, _T_3317) @[el2_lsu_bus_buffer.scala 475:82] + node _T_3319 = bits(buf_rspageQ[3], 3, 3) @[el2_lsu_bus_buffer.scala 475:78] + node _T_3320 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 475:99] + node _T_3321 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 475:125] + node _T_3322 = or(_T_3320, _T_3321) @[el2_lsu_bus_buffer.scala 475:110] + node _T_3323 = eq(_T_3322, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 475:84] + node _T_3324 = and(_T_3319, _T_3323) @[el2_lsu_bus_buffer.scala 475:82] node _T_3325 = cat(_T_3324, _T_3318) @[Cat.scala 29:58] node _T_3326 = cat(_T_3325, _T_3312) @[Cat.scala 29:58] node _T_3327 = cat(_T_3326, _T_3306) @[Cat.scala 29:58] - buf_rspage[0] <= _T_3246 @[el2_lsu_bus_buffer.scala 474:14] - buf_rspage[1] <= _T_3273 @[el2_lsu_bus_buffer.scala 474:14] - buf_rspage[2] <= _T_3300 @[el2_lsu_bus_buffer.scala 474:14] - buf_rspage[3] <= _T_3327 @[el2_lsu_bus_buffer.scala 474:14] - node _T_3328 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 479:75] - node _T_3329 = and(ibuf_drain_vld, _T_3328) @[el2_lsu_bus_buffer.scala 479:63] - node _T_3330 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 479:75] - node _T_3331 = and(ibuf_drain_vld, _T_3330) @[el2_lsu_bus_buffer.scala 479:63] - node _T_3332 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 479:75] - node _T_3333 = and(ibuf_drain_vld, _T_3332) @[el2_lsu_bus_buffer.scala 479:63] - node _T_3334 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 479:75] - node _T_3335 = and(ibuf_drain_vld, _T_3334) @[el2_lsu_bus_buffer.scala 479:63] + buf_rspage[0] <= _T_3246 @[el2_lsu_bus_buffer.scala 475:14] + buf_rspage[1] <= _T_3273 @[el2_lsu_bus_buffer.scala 475:14] + buf_rspage[2] <= _T_3300 @[el2_lsu_bus_buffer.scala 475:14] + buf_rspage[3] <= _T_3327 @[el2_lsu_bus_buffer.scala 475:14] + node _T_3328 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 480:75] + node _T_3329 = and(ibuf_drain_vld, _T_3328) @[el2_lsu_bus_buffer.scala 480:63] + node _T_3330 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 480:75] + node _T_3331 = and(ibuf_drain_vld, _T_3330) @[el2_lsu_bus_buffer.scala 480:63] + node _T_3332 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 480:75] + node _T_3333 = and(ibuf_drain_vld, _T_3332) @[el2_lsu_bus_buffer.scala 480:63] + node _T_3334 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 480:75] + node _T_3335 = and(ibuf_drain_vld, _T_3334) @[el2_lsu_bus_buffer.scala 480:63] node _T_3336 = cat(_T_3335, _T_3333) @[Cat.scala 29:58] node _T_3337 = cat(_T_3336, _T_3331) @[Cat.scala 29:58] node _T_3338 = cat(_T_3337, _T_3329) @[Cat.scala 29:58] - ibuf_drainvec_vld <= _T_3338 @[el2_lsu_bus_buffer.scala 479:21] - node _T_3339 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 480:64] - node _T_3340 = bits(ibuf_byteen_out, 3, 0) @[el2_lsu_bus_buffer.scala 480:84] - node _T_3341 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 481:18] - node _T_3342 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 481:46] - node _T_3343 = and(_T_3341, _T_3342) @[el2_lsu_bus_buffer.scala 481:35] - node _T_3344 = bits(ldst_byteen_hi_r, 3, 0) @[el2_lsu_bus_buffer.scala 481:71] - node _T_3345 = bits(ldst_byteen_lo_r, 3, 0) @[el2_lsu_bus_buffer.scala 481:94] - node _T_3346 = mux(_T_3343, _T_3344, _T_3345) @[el2_lsu_bus_buffer.scala 481:8] - node _T_3347 = mux(_T_3339, _T_3340, _T_3346) @[el2_lsu_bus_buffer.scala 480:46] - node _T_3348 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 480:64] - node _T_3349 = bits(ibuf_byteen_out, 3, 0) @[el2_lsu_bus_buffer.scala 480:84] - node _T_3350 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 481:18] - node _T_3351 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 481:46] - node _T_3352 = and(_T_3350, _T_3351) @[el2_lsu_bus_buffer.scala 481:35] - node _T_3353 = bits(ldst_byteen_hi_r, 3, 0) @[el2_lsu_bus_buffer.scala 481:71] - node _T_3354 = bits(ldst_byteen_lo_r, 3, 0) @[el2_lsu_bus_buffer.scala 481:94] - node _T_3355 = mux(_T_3352, _T_3353, _T_3354) @[el2_lsu_bus_buffer.scala 481:8] - node _T_3356 = mux(_T_3348, _T_3349, _T_3355) @[el2_lsu_bus_buffer.scala 480:46] - node _T_3357 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 480:64] - node _T_3358 = bits(ibuf_byteen_out, 3, 0) @[el2_lsu_bus_buffer.scala 480:84] - node _T_3359 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 481:18] - node _T_3360 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 481:46] - node _T_3361 = and(_T_3359, _T_3360) @[el2_lsu_bus_buffer.scala 481:35] - node _T_3362 = bits(ldst_byteen_hi_r, 3, 0) @[el2_lsu_bus_buffer.scala 481:71] - node _T_3363 = bits(ldst_byteen_lo_r, 3, 0) @[el2_lsu_bus_buffer.scala 481:94] - node _T_3364 = mux(_T_3361, _T_3362, _T_3363) @[el2_lsu_bus_buffer.scala 481:8] - node _T_3365 = mux(_T_3357, _T_3358, _T_3364) @[el2_lsu_bus_buffer.scala 480:46] - node _T_3366 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 480:64] - node _T_3367 = bits(ibuf_byteen_out, 3, 0) @[el2_lsu_bus_buffer.scala 480:84] - node _T_3368 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 481:18] - node _T_3369 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 481:46] - node _T_3370 = and(_T_3368, _T_3369) @[el2_lsu_bus_buffer.scala 481:35] - node _T_3371 = bits(ldst_byteen_hi_r, 3, 0) @[el2_lsu_bus_buffer.scala 481:71] - node _T_3372 = bits(ldst_byteen_lo_r, 3, 0) @[el2_lsu_bus_buffer.scala 481:94] - node _T_3373 = mux(_T_3370, _T_3371, _T_3372) @[el2_lsu_bus_buffer.scala 481:8] - node _T_3374 = mux(_T_3366, _T_3367, _T_3373) @[el2_lsu_bus_buffer.scala 480:46] - buf_byteen_in[0] <= _T_3347 @[el2_lsu_bus_buffer.scala 480:17] - buf_byteen_in[1] <= _T_3356 @[el2_lsu_bus_buffer.scala 480:17] - buf_byteen_in[2] <= _T_3365 @[el2_lsu_bus_buffer.scala 480:17] - buf_byteen_in[3] <= _T_3374 @[el2_lsu_bus_buffer.scala 480:17] - node _T_3375 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 482:62] - node _T_3376 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 482:91] - node _T_3377 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 482:119] - node _T_3378 = and(_T_3376, _T_3377) @[el2_lsu_bus_buffer.scala 482:108] - node _T_3379 = mux(_T_3378, io.end_addr_r, io.lsu_addr_r) @[el2_lsu_bus_buffer.scala 482:81] - node _T_3380 = mux(_T_3375, ibuf_addr, _T_3379) @[el2_lsu_bus_buffer.scala 482:44] - node _T_3381 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 482:62] - node _T_3382 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 482:91] - node _T_3383 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 482:119] - node _T_3384 = and(_T_3382, _T_3383) @[el2_lsu_bus_buffer.scala 482:108] - node _T_3385 = mux(_T_3384, io.end_addr_r, io.lsu_addr_r) @[el2_lsu_bus_buffer.scala 482:81] - node _T_3386 = mux(_T_3381, ibuf_addr, _T_3385) @[el2_lsu_bus_buffer.scala 482:44] - node _T_3387 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 482:62] - node _T_3388 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 482:91] - node _T_3389 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 482:119] - node _T_3390 = and(_T_3388, _T_3389) @[el2_lsu_bus_buffer.scala 482:108] - node _T_3391 = mux(_T_3390, io.end_addr_r, io.lsu_addr_r) @[el2_lsu_bus_buffer.scala 482:81] - node _T_3392 = mux(_T_3387, ibuf_addr, _T_3391) @[el2_lsu_bus_buffer.scala 482:44] - node _T_3393 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 482:62] - node _T_3394 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 482:91] - node _T_3395 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 482:119] - node _T_3396 = and(_T_3394, _T_3395) @[el2_lsu_bus_buffer.scala 482:108] - node _T_3397 = mux(_T_3396, io.end_addr_r, io.lsu_addr_r) @[el2_lsu_bus_buffer.scala 482:81] - node _T_3398 = mux(_T_3393, ibuf_addr, _T_3397) @[el2_lsu_bus_buffer.scala 482:44] - buf_addr_in[0] <= _T_3380 @[el2_lsu_bus_buffer.scala 482:15] - buf_addr_in[1] <= _T_3386 @[el2_lsu_bus_buffer.scala 482:15] - buf_addr_in[2] <= _T_3392 @[el2_lsu_bus_buffer.scala 482:15] - buf_addr_in[3] <= _T_3398 @[el2_lsu_bus_buffer.scala 482:15] - node _T_3399 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 483:63] - node _T_3400 = mux(_T_3399, ibuf_dual, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 483:45] - node _T_3401 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 483:63] - node _T_3402 = mux(_T_3401, ibuf_dual, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 483:45] - node _T_3403 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 483:63] - node _T_3404 = mux(_T_3403, ibuf_dual, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 483:45] - node _T_3405 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 483:63] - node _T_3406 = mux(_T_3405, ibuf_dual, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 483:45] + ibuf_drainvec_vld <= _T_3338 @[el2_lsu_bus_buffer.scala 480:21] + node _T_3339 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 481:64] + node _T_3340 = bits(ibuf_byteen_out, 3, 0) @[el2_lsu_bus_buffer.scala 481:84] + node _T_3341 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 482:18] + node _T_3342 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 482:46] + node _T_3343 = and(_T_3341, _T_3342) @[el2_lsu_bus_buffer.scala 482:35] + node _T_3344 = bits(ldst_byteen_hi_r, 3, 0) @[el2_lsu_bus_buffer.scala 482:71] + node _T_3345 = bits(ldst_byteen_lo_r, 3, 0) @[el2_lsu_bus_buffer.scala 482:94] + node _T_3346 = mux(_T_3343, _T_3344, _T_3345) @[el2_lsu_bus_buffer.scala 482:8] + node _T_3347 = mux(_T_3339, _T_3340, _T_3346) @[el2_lsu_bus_buffer.scala 481:46] + node _T_3348 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 481:64] + node _T_3349 = bits(ibuf_byteen_out, 3, 0) @[el2_lsu_bus_buffer.scala 481:84] + node _T_3350 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 482:18] + node _T_3351 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 482:46] + node _T_3352 = and(_T_3350, _T_3351) @[el2_lsu_bus_buffer.scala 482:35] + node _T_3353 = bits(ldst_byteen_hi_r, 3, 0) @[el2_lsu_bus_buffer.scala 482:71] + node _T_3354 = bits(ldst_byteen_lo_r, 3, 0) @[el2_lsu_bus_buffer.scala 482:94] + node _T_3355 = mux(_T_3352, _T_3353, _T_3354) @[el2_lsu_bus_buffer.scala 482:8] + node _T_3356 = mux(_T_3348, _T_3349, _T_3355) @[el2_lsu_bus_buffer.scala 481:46] + node _T_3357 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 481:64] + node _T_3358 = bits(ibuf_byteen_out, 3, 0) @[el2_lsu_bus_buffer.scala 481:84] + node _T_3359 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 482:18] + node _T_3360 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 482:46] + node _T_3361 = and(_T_3359, _T_3360) @[el2_lsu_bus_buffer.scala 482:35] + node _T_3362 = bits(ldst_byteen_hi_r, 3, 0) @[el2_lsu_bus_buffer.scala 482:71] + node _T_3363 = bits(ldst_byteen_lo_r, 3, 0) @[el2_lsu_bus_buffer.scala 482:94] + node _T_3364 = mux(_T_3361, _T_3362, _T_3363) @[el2_lsu_bus_buffer.scala 482:8] + node _T_3365 = mux(_T_3357, _T_3358, _T_3364) @[el2_lsu_bus_buffer.scala 481:46] + node _T_3366 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 481:64] + node _T_3367 = bits(ibuf_byteen_out, 3, 0) @[el2_lsu_bus_buffer.scala 481:84] + node _T_3368 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 482:18] + node _T_3369 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 482:46] + node _T_3370 = and(_T_3368, _T_3369) @[el2_lsu_bus_buffer.scala 482:35] + node _T_3371 = bits(ldst_byteen_hi_r, 3, 0) @[el2_lsu_bus_buffer.scala 482:71] + node _T_3372 = bits(ldst_byteen_lo_r, 3, 0) @[el2_lsu_bus_buffer.scala 482:94] + node _T_3373 = mux(_T_3370, _T_3371, _T_3372) @[el2_lsu_bus_buffer.scala 482:8] + node _T_3374 = mux(_T_3366, _T_3367, _T_3373) @[el2_lsu_bus_buffer.scala 481:46] + buf_byteen_in[0] <= _T_3347 @[el2_lsu_bus_buffer.scala 481:17] + buf_byteen_in[1] <= _T_3356 @[el2_lsu_bus_buffer.scala 481:17] + buf_byteen_in[2] <= _T_3365 @[el2_lsu_bus_buffer.scala 481:17] + buf_byteen_in[3] <= _T_3374 @[el2_lsu_bus_buffer.scala 481:17] + node _T_3375 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 483:62] + node _T_3376 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 483:91] + node _T_3377 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 483:119] + node _T_3378 = and(_T_3376, _T_3377) @[el2_lsu_bus_buffer.scala 483:108] + node _T_3379 = mux(_T_3378, io.end_addr_r, io.lsu_addr_r) @[el2_lsu_bus_buffer.scala 483:81] + node _T_3380 = mux(_T_3375, ibuf_addr, _T_3379) @[el2_lsu_bus_buffer.scala 483:44] + node _T_3381 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 483:62] + node _T_3382 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 483:91] + node _T_3383 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 483:119] + node _T_3384 = and(_T_3382, _T_3383) @[el2_lsu_bus_buffer.scala 483:108] + node _T_3385 = mux(_T_3384, io.end_addr_r, io.lsu_addr_r) @[el2_lsu_bus_buffer.scala 483:81] + node _T_3386 = mux(_T_3381, ibuf_addr, _T_3385) @[el2_lsu_bus_buffer.scala 483:44] + node _T_3387 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 483:62] + node _T_3388 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 483:91] + node _T_3389 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 483:119] + node _T_3390 = and(_T_3388, _T_3389) @[el2_lsu_bus_buffer.scala 483:108] + node _T_3391 = mux(_T_3390, io.end_addr_r, io.lsu_addr_r) @[el2_lsu_bus_buffer.scala 483:81] + node _T_3392 = mux(_T_3387, ibuf_addr, _T_3391) @[el2_lsu_bus_buffer.scala 483:44] + node _T_3393 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 483:62] + node _T_3394 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 483:91] + node _T_3395 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 483:119] + node _T_3396 = and(_T_3394, _T_3395) @[el2_lsu_bus_buffer.scala 483:108] + node _T_3397 = mux(_T_3396, io.end_addr_r, io.lsu_addr_r) @[el2_lsu_bus_buffer.scala 483:81] + node _T_3398 = mux(_T_3393, ibuf_addr, _T_3397) @[el2_lsu_bus_buffer.scala 483:44] + buf_addr_in[0] <= _T_3380 @[el2_lsu_bus_buffer.scala 483:15] + buf_addr_in[1] <= _T_3386 @[el2_lsu_bus_buffer.scala 483:15] + buf_addr_in[2] <= _T_3392 @[el2_lsu_bus_buffer.scala 483:15] + buf_addr_in[3] <= _T_3398 @[el2_lsu_bus_buffer.scala 483:15] + node _T_3399 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 484:63] + node _T_3400 = mux(_T_3399, ibuf_dual, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 484:45] + node _T_3401 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 484:63] + node _T_3402 = mux(_T_3401, ibuf_dual, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 484:45] + node _T_3403 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 484:63] + node _T_3404 = mux(_T_3403, ibuf_dual, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 484:45] + node _T_3405 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 484:63] + node _T_3406 = mux(_T_3405, ibuf_dual, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 484:45] node _T_3407 = cat(_T_3406, _T_3404) @[Cat.scala 29:58] node _T_3408 = cat(_T_3407, _T_3402) @[Cat.scala 29:58] node _T_3409 = cat(_T_3408, _T_3400) @[Cat.scala 29:58] - buf_dual_in <= _T_3409 @[el2_lsu_bus_buffer.scala 483:15] - node _T_3410 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 484:65] - node _T_3411 = mux(_T_3410, ibuf_samedw, ldst_samedw_r) @[el2_lsu_bus_buffer.scala 484:47] - node _T_3412 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 484:65] - node _T_3413 = mux(_T_3412, ibuf_samedw, ldst_samedw_r) @[el2_lsu_bus_buffer.scala 484:47] - node _T_3414 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 484:65] - node _T_3415 = mux(_T_3414, ibuf_samedw, ldst_samedw_r) @[el2_lsu_bus_buffer.scala 484:47] - node _T_3416 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 484:65] - node _T_3417 = mux(_T_3416, ibuf_samedw, ldst_samedw_r) @[el2_lsu_bus_buffer.scala 484:47] + buf_dual_in <= _T_3409 @[el2_lsu_bus_buffer.scala 484:15] + node _T_3410 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 485:65] + node _T_3411 = mux(_T_3410, ibuf_samedw, ldst_samedw_r) @[el2_lsu_bus_buffer.scala 485:47] + node _T_3412 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 485:65] + node _T_3413 = mux(_T_3412, ibuf_samedw, ldst_samedw_r) @[el2_lsu_bus_buffer.scala 485:47] + node _T_3414 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 485:65] + node _T_3415 = mux(_T_3414, ibuf_samedw, ldst_samedw_r) @[el2_lsu_bus_buffer.scala 485:47] + node _T_3416 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 485:65] + node _T_3417 = mux(_T_3416, ibuf_samedw, ldst_samedw_r) @[el2_lsu_bus_buffer.scala 485:47] node _T_3418 = cat(_T_3417, _T_3415) @[Cat.scala 29:58] node _T_3419 = cat(_T_3418, _T_3413) @[Cat.scala 29:58] node _T_3420 = cat(_T_3419, _T_3411) @[Cat.scala 29:58] - buf_samedw_in <= _T_3420 @[el2_lsu_bus_buffer.scala 484:17] - node _T_3421 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 485:66] - node _T_3422 = or(ibuf_nomerge, ibuf_force_drain) @[el2_lsu_bus_buffer.scala 485:84] - node _T_3423 = mux(_T_3421, _T_3422, io.no_dword_merge_r) @[el2_lsu_bus_buffer.scala 485:48] - node _T_3424 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 485:66] - node _T_3425 = or(ibuf_nomerge, ibuf_force_drain) @[el2_lsu_bus_buffer.scala 485:84] - node _T_3426 = mux(_T_3424, _T_3425, io.no_dword_merge_r) @[el2_lsu_bus_buffer.scala 485:48] - node _T_3427 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 485:66] - node _T_3428 = or(ibuf_nomerge, ibuf_force_drain) @[el2_lsu_bus_buffer.scala 485:84] - node _T_3429 = mux(_T_3427, _T_3428, io.no_dword_merge_r) @[el2_lsu_bus_buffer.scala 485:48] - node _T_3430 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 485:66] - node _T_3431 = or(ibuf_nomerge, ibuf_force_drain) @[el2_lsu_bus_buffer.scala 485:84] - node _T_3432 = mux(_T_3430, _T_3431, io.no_dword_merge_r) @[el2_lsu_bus_buffer.scala 485:48] + buf_samedw_in <= _T_3420 @[el2_lsu_bus_buffer.scala 485:17] + node _T_3421 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 486:66] + node _T_3422 = or(ibuf_nomerge, ibuf_force_drain) @[el2_lsu_bus_buffer.scala 486:84] + node _T_3423 = mux(_T_3421, _T_3422, io.no_dword_merge_r) @[el2_lsu_bus_buffer.scala 486:48] + node _T_3424 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 486:66] + node _T_3425 = or(ibuf_nomerge, ibuf_force_drain) @[el2_lsu_bus_buffer.scala 486:84] + node _T_3426 = mux(_T_3424, _T_3425, io.no_dword_merge_r) @[el2_lsu_bus_buffer.scala 486:48] + node _T_3427 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 486:66] + node _T_3428 = or(ibuf_nomerge, ibuf_force_drain) @[el2_lsu_bus_buffer.scala 486:84] + node _T_3429 = mux(_T_3427, _T_3428, io.no_dword_merge_r) @[el2_lsu_bus_buffer.scala 486:48] + node _T_3430 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 486:66] + node _T_3431 = or(ibuf_nomerge, ibuf_force_drain) @[el2_lsu_bus_buffer.scala 486:84] + node _T_3432 = mux(_T_3430, _T_3431, io.no_dword_merge_r) @[el2_lsu_bus_buffer.scala 486:48] node _T_3433 = cat(_T_3432, _T_3429) @[Cat.scala 29:58] node _T_3434 = cat(_T_3433, _T_3426) @[Cat.scala 29:58] node _T_3435 = cat(_T_3434, _T_3423) @[Cat.scala 29:58] - buf_nomerge_in <= _T_3435 @[el2_lsu_bus_buffer.scala 485:18] - node _T_3436 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 486:65] - node _T_3437 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 486:90] - node _T_3438 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 486:118] - node _T_3439 = and(_T_3437, _T_3438) @[el2_lsu_bus_buffer.scala 486:107] - node _T_3440 = mux(_T_3436, ibuf_dual, _T_3439) @[el2_lsu_bus_buffer.scala 486:47] - node _T_3441 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 486:65] - node _T_3442 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 486:90] - node _T_3443 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 486:118] - node _T_3444 = and(_T_3442, _T_3443) @[el2_lsu_bus_buffer.scala 486:107] - node _T_3445 = mux(_T_3441, ibuf_dual, _T_3444) @[el2_lsu_bus_buffer.scala 486:47] - node _T_3446 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 486:65] - node _T_3447 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 486:90] - node _T_3448 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 486:118] - node _T_3449 = and(_T_3447, _T_3448) @[el2_lsu_bus_buffer.scala 486:107] - node _T_3450 = mux(_T_3446, ibuf_dual, _T_3449) @[el2_lsu_bus_buffer.scala 486:47] - node _T_3451 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 486:65] - node _T_3452 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 486:90] - node _T_3453 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 486:118] - node _T_3454 = and(_T_3452, _T_3453) @[el2_lsu_bus_buffer.scala 486:107] - node _T_3455 = mux(_T_3451, ibuf_dual, _T_3454) @[el2_lsu_bus_buffer.scala 486:47] + buf_nomerge_in <= _T_3435 @[el2_lsu_bus_buffer.scala 486:18] + node _T_3436 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 487:65] + node _T_3437 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 487:90] + node _T_3438 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 487:118] + node _T_3439 = and(_T_3437, _T_3438) @[el2_lsu_bus_buffer.scala 487:107] + node _T_3440 = mux(_T_3436, ibuf_dual, _T_3439) @[el2_lsu_bus_buffer.scala 487:47] + node _T_3441 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 487:65] + node _T_3442 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 487:90] + node _T_3443 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 487:118] + node _T_3444 = and(_T_3442, _T_3443) @[el2_lsu_bus_buffer.scala 487:107] + node _T_3445 = mux(_T_3441, ibuf_dual, _T_3444) @[el2_lsu_bus_buffer.scala 487:47] + node _T_3446 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 487:65] + node _T_3447 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 487:90] + node _T_3448 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 487:118] + node _T_3449 = and(_T_3447, _T_3448) @[el2_lsu_bus_buffer.scala 487:107] + node _T_3450 = mux(_T_3446, ibuf_dual, _T_3449) @[el2_lsu_bus_buffer.scala 487:47] + node _T_3451 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 487:65] + node _T_3452 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 487:90] + node _T_3453 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 487:118] + node _T_3454 = and(_T_3452, _T_3453) @[el2_lsu_bus_buffer.scala 487:107] + node _T_3455 = mux(_T_3451, ibuf_dual, _T_3454) @[el2_lsu_bus_buffer.scala 487:47] node _T_3456 = cat(_T_3455, _T_3450) @[Cat.scala 29:58] node _T_3457 = cat(_T_3456, _T_3445) @[Cat.scala 29:58] node _T_3458 = cat(_T_3457, _T_3440) @[Cat.scala 29:58] - buf_dualhi_in <= _T_3458 @[el2_lsu_bus_buffer.scala 486:17] - node _T_3459 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 487:65] - node _T_3460 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 487:97] - node _T_3461 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 487:125] - node _T_3462 = and(_T_3460, _T_3461) @[el2_lsu_bus_buffer.scala 487:114] - node _T_3463 = mux(_T_3462, WrPtr0_r, WrPtr1_r) @[el2_lsu_bus_buffer.scala 487:87] - node _T_3464 = mux(_T_3459, ibuf_dualtag, _T_3463) @[el2_lsu_bus_buffer.scala 487:47] - node _T_3465 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 487:65] - node _T_3466 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 487:97] - node _T_3467 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 487:125] - node _T_3468 = and(_T_3466, _T_3467) @[el2_lsu_bus_buffer.scala 487:114] - node _T_3469 = mux(_T_3468, WrPtr0_r, WrPtr1_r) @[el2_lsu_bus_buffer.scala 487:87] - node _T_3470 = mux(_T_3465, ibuf_dualtag, _T_3469) @[el2_lsu_bus_buffer.scala 487:47] - node _T_3471 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 487:65] - node _T_3472 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 487:97] - node _T_3473 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 487:125] - node _T_3474 = and(_T_3472, _T_3473) @[el2_lsu_bus_buffer.scala 487:114] - node _T_3475 = mux(_T_3474, WrPtr0_r, WrPtr1_r) @[el2_lsu_bus_buffer.scala 487:87] - node _T_3476 = mux(_T_3471, ibuf_dualtag, _T_3475) @[el2_lsu_bus_buffer.scala 487:47] - node _T_3477 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 487:65] - node _T_3478 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 487:97] - node _T_3479 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 487:125] - node _T_3480 = and(_T_3478, _T_3479) @[el2_lsu_bus_buffer.scala 487:114] - node _T_3481 = mux(_T_3480, WrPtr0_r, WrPtr1_r) @[el2_lsu_bus_buffer.scala 487:87] - node _T_3482 = mux(_T_3477, ibuf_dualtag, _T_3481) @[el2_lsu_bus_buffer.scala 487:47] - buf_dualtag_in[0] <= _T_3464 @[el2_lsu_bus_buffer.scala 487:18] - buf_dualtag_in[1] <= _T_3470 @[el2_lsu_bus_buffer.scala 487:18] - buf_dualtag_in[2] <= _T_3476 @[el2_lsu_bus_buffer.scala 487:18] - buf_dualtag_in[3] <= _T_3482 @[el2_lsu_bus_buffer.scala 487:18] - node _T_3483 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 488:69] - node _T_3484 = mux(_T_3483, ibuf_sideeffect, io.is_sideeffects_r) @[el2_lsu_bus_buffer.scala 488:51] - node _T_3485 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 488:69] - node _T_3486 = mux(_T_3485, ibuf_sideeffect, io.is_sideeffects_r) @[el2_lsu_bus_buffer.scala 488:51] - node _T_3487 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 488:69] - node _T_3488 = mux(_T_3487, ibuf_sideeffect, io.is_sideeffects_r) @[el2_lsu_bus_buffer.scala 488:51] - node _T_3489 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 488:69] - node _T_3490 = mux(_T_3489, ibuf_sideeffect, io.is_sideeffects_r) @[el2_lsu_bus_buffer.scala 488:51] + buf_dualhi_in <= _T_3458 @[el2_lsu_bus_buffer.scala 487:17] + node _T_3459 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 488:65] + node _T_3460 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 488:97] + node _T_3461 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 488:125] + node _T_3462 = and(_T_3460, _T_3461) @[el2_lsu_bus_buffer.scala 488:114] + node _T_3463 = mux(_T_3462, WrPtr0_r, WrPtr1_r) @[el2_lsu_bus_buffer.scala 488:87] + node _T_3464 = mux(_T_3459, ibuf_dualtag, _T_3463) @[el2_lsu_bus_buffer.scala 488:47] + node _T_3465 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 488:65] + node _T_3466 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 488:97] + node _T_3467 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 488:125] + node _T_3468 = and(_T_3466, _T_3467) @[el2_lsu_bus_buffer.scala 488:114] + node _T_3469 = mux(_T_3468, WrPtr0_r, WrPtr1_r) @[el2_lsu_bus_buffer.scala 488:87] + node _T_3470 = mux(_T_3465, ibuf_dualtag, _T_3469) @[el2_lsu_bus_buffer.scala 488:47] + node _T_3471 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 488:65] + node _T_3472 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 488:97] + node _T_3473 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 488:125] + node _T_3474 = and(_T_3472, _T_3473) @[el2_lsu_bus_buffer.scala 488:114] + node _T_3475 = mux(_T_3474, WrPtr0_r, WrPtr1_r) @[el2_lsu_bus_buffer.scala 488:87] + node _T_3476 = mux(_T_3471, ibuf_dualtag, _T_3475) @[el2_lsu_bus_buffer.scala 488:47] + node _T_3477 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 488:65] + node _T_3478 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 488:97] + node _T_3479 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 488:125] + node _T_3480 = and(_T_3478, _T_3479) @[el2_lsu_bus_buffer.scala 488:114] + node _T_3481 = mux(_T_3480, WrPtr0_r, WrPtr1_r) @[el2_lsu_bus_buffer.scala 488:87] + node _T_3482 = mux(_T_3477, ibuf_dualtag, _T_3481) @[el2_lsu_bus_buffer.scala 488:47] + buf_dualtag_in[0] <= _T_3464 @[el2_lsu_bus_buffer.scala 488:18] + buf_dualtag_in[1] <= _T_3470 @[el2_lsu_bus_buffer.scala 488:18] + buf_dualtag_in[2] <= _T_3476 @[el2_lsu_bus_buffer.scala 488:18] + buf_dualtag_in[3] <= _T_3482 @[el2_lsu_bus_buffer.scala 488:18] + node _T_3483 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 489:69] + node _T_3484 = mux(_T_3483, ibuf_sideeffect, io.is_sideeffects_r) @[el2_lsu_bus_buffer.scala 489:51] + node _T_3485 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 489:69] + node _T_3486 = mux(_T_3485, ibuf_sideeffect, io.is_sideeffects_r) @[el2_lsu_bus_buffer.scala 489:51] + node _T_3487 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 489:69] + node _T_3488 = mux(_T_3487, ibuf_sideeffect, io.is_sideeffects_r) @[el2_lsu_bus_buffer.scala 489:51] + node _T_3489 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 489:69] + node _T_3490 = mux(_T_3489, ibuf_sideeffect, io.is_sideeffects_r) @[el2_lsu_bus_buffer.scala 489:51] node _T_3491 = cat(_T_3490, _T_3488) @[Cat.scala 29:58] node _T_3492 = cat(_T_3491, _T_3486) @[Cat.scala 29:58] node _T_3493 = cat(_T_3492, _T_3484) @[Cat.scala 29:58] - buf_sideeffect_in <= _T_3493 @[el2_lsu_bus_buffer.scala 488:21] - node _T_3494 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 489:65] - node _T_3495 = mux(_T_3494, ibuf_unsign, io.lsu_pkt_r.unsign) @[el2_lsu_bus_buffer.scala 489:47] - node _T_3496 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 489:65] - node _T_3497 = mux(_T_3496, ibuf_unsign, io.lsu_pkt_r.unsign) @[el2_lsu_bus_buffer.scala 489:47] - node _T_3498 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 489:65] - node _T_3499 = mux(_T_3498, ibuf_unsign, io.lsu_pkt_r.unsign) @[el2_lsu_bus_buffer.scala 489:47] - node _T_3500 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 489:65] - node _T_3501 = mux(_T_3500, ibuf_unsign, io.lsu_pkt_r.unsign) @[el2_lsu_bus_buffer.scala 489:47] + buf_sideeffect_in <= _T_3493 @[el2_lsu_bus_buffer.scala 489:21] + node _T_3494 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 490:65] + node _T_3495 = mux(_T_3494, ibuf_unsign, io.lsu_pkt_r.bits.unsign) @[el2_lsu_bus_buffer.scala 490:47] + node _T_3496 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 490:65] + node _T_3497 = mux(_T_3496, ibuf_unsign, io.lsu_pkt_r.bits.unsign) @[el2_lsu_bus_buffer.scala 490:47] + node _T_3498 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 490:65] + node _T_3499 = mux(_T_3498, ibuf_unsign, io.lsu_pkt_r.bits.unsign) @[el2_lsu_bus_buffer.scala 490:47] + node _T_3500 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 490:65] + node _T_3501 = mux(_T_3500, ibuf_unsign, io.lsu_pkt_r.bits.unsign) @[el2_lsu_bus_buffer.scala 490:47] node _T_3502 = cat(_T_3501, _T_3499) @[Cat.scala 29:58] node _T_3503 = cat(_T_3502, _T_3497) @[Cat.scala 29:58] node _T_3504 = cat(_T_3503, _T_3495) @[Cat.scala 29:58] - buf_unsign_in <= _T_3504 @[el2_lsu_bus_buffer.scala 489:17] - node _T_3505 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 490:60] - node _T_3506 = cat(io.lsu_pkt_r.word, io.lsu_pkt_r.half) @[Cat.scala 29:58] - node _T_3507 = mux(_T_3505, ibuf_sz, _T_3506) @[el2_lsu_bus_buffer.scala 490:42] - node _T_3508 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 490:60] - node _T_3509 = cat(io.lsu_pkt_r.word, io.lsu_pkt_r.half) @[Cat.scala 29:58] - node _T_3510 = mux(_T_3508, ibuf_sz, _T_3509) @[el2_lsu_bus_buffer.scala 490:42] - node _T_3511 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 490:60] - node _T_3512 = cat(io.lsu_pkt_r.word, io.lsu_pkt_r.half) @[Cat.scala 29:58] - node _T_3513 = mux(_T_3511, ibuf_sz, _T_3512) @[el2_lsu_bus_buffer.scala 490:42] - node _T_3514 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 490:60] - node _T_3515 = cat(io.lsu_pkt_r.word, io.lsu_pkt_r.half) @[Cat.scala 29:58] - node _T_3516 = mux(_T_3514, ibuf_sz, _T_3515) @[el2_lsu_bus_buffer.scala 490:42] - buf_sz_in[0] <= _T_3507 @[el2_lsu_bus_buffer.scala 490:13] - buf_sz_in[1] <= _T_3510 @[el2_lsu_bus_buffer.scala 490:13] - buf_sz_in[2] <= _T_3513 @[el2_lsu_bus_buffer.scala 490:13] - buf_sz_in[3] <= _T_3516 @[el2_lsu_bus_buffer.scala 490:13] - node _T_3517 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 491:64] - node _T_3518 = mux(_T_3517, ibuf_write, io.lsu_pkt_r.store) @[el2_lsu_bus_buffer.scala 491:46] - node _T_3519 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 491:64] - node _T_3520 = mux(_T_3519, ibuf_write, io.lsu_pkt_r.store) @[el2_lsu_bus_buffer.scala 491:46] - node _T_3521 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 491:64] - node _T_3522 = mux(_T_3521, ibuf_write, io.lsu_pkt_r.store) @[el2_lsu_bus_buffer.scala 491:46] - node _T_3523 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 491:64] - node _T_3524 = mux(_T_3523, ibuf_write, io.lsu_pkt_r.store) @[el2_lsu_bus_buffer.scala 491:46] + buf_unsign_in <= _T_3504 @[el2_lsu_bus_buffer.scala 490:17] + node _T_3505 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 491:60] + node _T_3506 = cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) @[Cat.scala 29:58] + node _T_3507 = mux(_T_3505, ibuf_sz, _T_3506) @[el2_lsu_bus_buffer.scala 491:42] + node _T_3508 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 491:60] + node _T_3509 = cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) @[Cat.scala 29:58] + node _T_3510 = mux(_T_3508, ibuf_sz, _T_3509) @[el2_lsu_bus_buffer.scala 491:42] + node _T_3511 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 491:60] + node _T_3512 = cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) @[Cat.scala 29:58] + node _T_3513 = mux(_T_3511, ibuf_sz, _T_3512) @[el2_lsu_bus_buffer.scala 491:42] + node _T_3514 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 491:60] + node _T_3515 = cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) @[Cat.scala 29:58] + node _T_3516 = mux(_T_3514, ibuf_sz, _T_3515) @[el2_lsu_bus_buffer.scala 491:42] + buf_sz_in[0] <= _T_3507 @[el2_lsu_bus_buffer.scala 491:13] + buf_sz_in[1] <= _T_3510 @[el2_lsu_bus_buffer.scala 491:13] + buf_sz_in[2] <= _T_3513 @[el2_lsu_bus_buffer.scala 491:13] + buf_sz_in[3] <= _T_3516 @[el2_lsu_bus_buffer.scala 491:13] + node _T_3517 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 492:64] + node _T_3518 = mux(_T_3517, ibuf_write, io.lsu_pkt_r.bits.store) @[el2_lsu_bus_buffer.scala 492:46] + node _T_3519 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 492:64] + node _T_3520 = mux(_T_3519, ibuf_write, io.lsu_pkt_r.bits.store) @[el2_lsu_bus_buffer.scala 492:46] + node _T_3521 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 492:64] + node _T_3522 = mux(_T_3521, ibuf_write, io.lsu_pkt_r.bits.store) @[el2_lsu_bus_buffer.scala 492:46] + node _T_3523 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 492:64] + node _T_3524 = mux(_T_3523, ibuf_write, io.lsu_pkt_r.bits.store) @[el2_lsu_bus_buffer.scala 492:46] node _T_3525 = cat(_T_3524, _T_3522) @[Cat.scala 29:58] node _T_3526 = cat(_T_3525, _T_3520) @[Cat.scala 29:58] node _T_3527 = cat(_T_3526, _T_3518) @[Cat.scala 29:58] - buf_write_in <= _T_3527 @[el2_lsu_bus_buffer.scala 491:16] + buf_write_in <= _T_3527 @[el2_lsu_bus_buffer.scala 492:16] node _T_3528 = eq(UInt<3>("h00"), buf_state[0]) @[Conditional.scala 37:30] when _T_3528 : @[Conditional.scala 40:58] - node _T_3529 = bits(io.lsu_bus_clk_en, 0, 0) @[el2_lsu_bus_buffer.scala 496:56] - node _T_3530 = mux(_T_3529, UInt<3>("h02"), UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 496:31] - buf_nxtstate[0] <= _T_3530 @[el2_lsu_bus_buffer.scala 496:25] - node _T_3531 = and(io.lsu_busreq_r, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 497:45] - node _T_3532 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 497:77] - node _T_3533 = eq(ibuf_merge_en, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 497:97] - node _T_3534 = and(_T_3532, _T_3533) @[el2_lsu_bus_buffer.scala 497:95] - node _T_3535 = eq(UInt<1>("h00"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 497:117] - node _T_3536 = and(_T_3534, _T_3535) @[el2_lsu_bus_buffer.scala 497:112] - node _T_3537 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 497:144] - node _T_3538 = eq(UInt<1>("h00"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 497:166] - node _T_3539 = and(_T_3537, _T_3538) @[el2_lsu_bus_buffer.scala 497:161] - node _T_3540 = or(_T_3536, _T_3539) @[el2_lsu_bus_buffer.scala 497:132] - node _T_3541 = and(_T_3531, _T_3540) @[el2_lsu_bus_buffer.scala 497:63] - node _T_3542 = eq(UInt<1>("h00"), ibuf_tag) @[el2_lsu_bus_buffer.scala 497:206] - node _T_3543 = and(ibuf_drain_vld, _T_3542) @[el2_lsu_bus_buffer.scala 497:201] - node _T_3544 = or(_T_3541, _T_3543) @[el2_lsu_bus_buffer.scala 497:183] - buf_state_en[0] <= _T_3544 @[el2_lsu_bus_buffer.scala 497:25] - buf_wr_en[0] <= buf_state_en[0] @[el2_lsu_bus_buffer.scala 498:22] - buf_data_en[0] <= buf_state_en[0] @[el2_lsu_bus_buffer.scala 499:24] - node _T_3545 = eq(UInt<1>("h00"), ibuf_tag) @[el2_lsu_bus_buffer.scala 500:52] - node _T_3546 = and(ibuf_drain_vld, _T_3545) @[el2_lsu_bus_buffer.scala 500:47] - node _T_3547 = bits(_T_3546, 0, 0) @[el2_lsu_bus_buffer.scala 500:73] - node _T_3548 = bits(ibuf_data_out, 31, 0) @[el2_lsu_bus_buffer.scala 500:90] - node _T_3549 = bits(store_data_lo_r, 31, 0) @[el2_lsu_bus_buffer.scala 500:114] - node _T_3550 = mux(_T_3547, _T_3548, _T_3549) @[el2_lsu_bus_buffer.scala 500:30] - buf_data_in[0] <= _T_3550 @[el2_lsu_bus_buffer.scala 500:24] + node _T_3529 = bits(io.lsu_bus_clk_en, 0, 0) @[el2_lsu_bus_buffer.scala 497:56] + node _T_3530 = mux(_T_3529, UInt<3>("h02"), UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 497:31] + buf_nxtstate[0] <= _T_3530 @[el2_lsu_bus_buffer.scala 497:25] + node _T_3531 = and(io.lsu_busreq_r, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 498:45] + node _T_3532 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 498:77] + node _T_3533 = eq(ibuf_merge_en, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 498:97] + node _T_3534 = and(_T_3532, _T_3533) @[el2_lsu_bus_buffer.scala 498:95] + node _T_3535 = eq(UInt<1>("h00"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 498:117] + node _T_3536 = and(_T_3534, _T_3535) @[el2_lsu_bus_buffer.scala 498:112] + node _T_3537 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 498:144] + node _T_3538 = eq(UInt<1>("h00"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 498:166] + node _T_3539 = and(_T_3537, _T_3538) @[el2_lsu_bus_buffer.scala 498:161] + node _T_3540 = or(_T_3536, _T_3539) @[el2_lsu_bus_buffer.scala 498:132] + node _T_3541 = and(_T_3531, _T_3540) @[el2_lsu_bus_buffer.scala 498:63] + node _T_3542 = eq(UInt<1>("h00"), ibuf_tag) @[el2_lsu_bus_buffer.scala 498:206] + node _T_3543 = and(ibuf_drain_vld, _T_3542) @[el2_lsu_bus_buffer.scala 498:201] + node _T_3544 = or(_T_3541, _T_3543) @[el2_lsu_bus_buffer.scala 498:183] + buf_state_en[0] <= _T_3544 @[el2_lsu_bus_buffer.scala 498:25] + buf_wr_en[0] <= buf_state_en[0] @[el2_lsu_bus_buffer.scala 499:22] + buf_data_en[0] <= buf_state_en[0] @[el2_lsu_bus_buffer.scala 500:24] + node _T_3545 = eq(UInt<1>("h00"), ibuf_tag) @[el2_lsu_bus_buffer.scala 501:52] + node _T_3546 = and(ibuf_drain_vld, _T_3545) @[el2_lsu_bus_buffer.scala 501:47] + node _T_3547 = bits(_T_3546, 0, 0) @[el2_lsu_bus_buffer.scala 501:73] + node _T_3548 = bits(ibuf_data_out, 31, 0) @[el2_lsu_bus_buffer.scala 501:90] + node _T_3549 = bits(store_data_lo_r, 31, 0) @[el2_lsu_bus_buffer.scala 501:114] + node _T_3550 = mux(_T_3547, _T_3548, _T_3549) @[el2_lsu_bus_buffer.scala 501:30] + buf_data_in[0] <= _T_3550 @[el2_lsu_bus_buffer.scala 501:24] skip @[Conditional.scala 40:58] else : @[Conditional.scala 39:67] node _T_3551 = eq(UInt<3>("h01"), buf_state[0]) @[Conditional.scala 37:30] when _T_3551 : @[Conditional.scala 39:67] - node _T_3552 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 503:60] - node _T_3553 = mux(_T_3552, UInt<3>("h00"), UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 503:31] - buf_nxtstate[0] <= _T_3553 @[el2_lsu_bus_buffer.scala 503:25] - node _T_3554 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 504:46] - buf_state_en[0] <= _T_3554 @[el2_lsu_bus_buffer.scala 504:25] + node _T_3552 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 504:60] + node _T_3553 = mux(_T_3552, UInt<3>("h00"), UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 504:31] + buf_nxtstate[0] <= _T_3553 @[el2_lsu_bus_buffer.scala 504:25] + node _T_3554 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 505:46] + buf_state_en[0] <= _T_3554 @[el2_lsu_bus_buffer.scala 505:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_3555 = eq(UInt<3>("h02"), buf_state[0]) @[Conditional.scala 37:30] when _T_3555 : @[Conditional.scala 39:67] - node _T_3556 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 507:60] - node _T_3557 = and(obuf_nosend, bus_rsp_read) @[el2_lsu_bus_buffer.scala 507:89] - node _T_3558 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[el2_lsu_bus_buffer.scala 507:124] - node _T_3559 = and(_T_3557, _T_3558) @[el2_lsu_bus_buffer.scala 507:104] - node _T_3560 = mux(_T_3559, UInt<3>("h05"), UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 507:75] - node _T_3561 = mux(_T_3556, UInt<3>("h00"), _T_3560) @[el2_lsu_bus_buffer.scala 507:31] - buf_nxtstate[0] <= _T_3561 @[el2_lsu_bus_buffer.scala 507:25] - node _T_3562 = eq(obuf_tag0, UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 508:48] - node _T_3563 = eq(obuf_tag1, UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 508:104] - node _T_3564 = and(obuf_merge, _T_3563) @[el2_lsu_bus_buffer.scala 508:91] - node _T_3565 = or(_T_3562, _T_3564) @[el2_lsu_bus_buffer.scala 508:77] - node _T_3566 = and(_T_3565, obuf_valid) @[el2_lsu_bus_buffer.scala 508:135] - node _T_3567 = and(_T_3566, obuf_wr_enQ) @[el2_lsu_bus_buffer.scala 508:148] - buf_cmd_state_bus_en[0] <= _T_3567 @[el2_lsu_bus_buffer.scala 508:33] - buf_state_bus_en[0] <= buf_cmd_state_bus_en[0] @[el2_lsu_bus_buffer.scala 509:29] - node _T_3568 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 510:49] - node _T_3569 = or(_T_3568, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 510:70] - buf_state_en[0] <= _T_3569 @[el2_lsu_bus_buffer.scala 510:25] - buf_ldfwd_in[0] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 511:25] - node _T_3570 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 512:56] - node _T_3571 = eq(_T_3570, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 512:46] - node _T_3572 = and(buf_state_en[0], _T_3571) @[el2_lsu_bus_buffer.scala 512:44] - node _T_3573 = and(_T_3572, obuf_nosend) @[el2_lsu_bus_buffer.scala 512:60] - node _T_3574 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 512:76] - node _T_3575 = and(_T_3573, _T_3574) @[el2_lsu_bus_buffer.scala 512:74] - buf_ldfwd_en[0] <= _T_3575 @[el2_lsu_bus_buffer.scala 512:25] - node _T_3576 = bits(obuf_rdrsp_tag, 1, 0) @[el2_lsu_bus_buffer.scala 513:46] - buf_ldfwdtag_in[0] <= _T_3576 @[el2_lsu_bus_buffer.scala 513:28] - node _T_3577 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 514:47] - node _T_3578 = and(_T_3577, obuf_nosend) @[el2_lsu_bus_buffer.scala 514:67] - node _T_3579 = and(_T_3578, bus_rsp_read) @[el2_lsu_bus_buffer.scala 514:81] - buf_data_en[0] <= _T_3579 @[el2_lsu_bus_buffer.scala 514:24] - node _T_3580 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 515:48] - node _T_3581 = and(_T_3580, obuf_nosend) @[el2_lsu_bus_buffer.scala 515:68] - node _T_3582 = and(_T_3581, bus_rsp_read_error) @[el2_lsu_bus_buffer.scala 515:82] - buf_error_en[0] <= _T_3582 @[el2_lsu_bus_buffer.scala 515:25] - node _T_3583 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 516:61] - node _T_3584 = bits(buf_addr[0], 2, 2) @[el2_lsu_bus_buffer.scala 516:85] - node _T_3585 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 516:103] - node _T_3586 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 516:126] - node _T_3587 = mux(_T_3584, _T_3585, _T_3586) @[el2_lsu_bus_buffer.scala 516:73] - node _T_3588 = mux(buf_error_en[0], _T_3583, _T_3587) @[el2_lsu_bus_buffer.scala 516:30] - buf_data_in[0] <= _T_3588 @[el2_lsu_bus_buffer.scala 516:24] + node _T_3556 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 508:60] + node _T_3557 = and(obuf_nosend, bus_rsp_read) @[el2_lsu_bus_buffer.scala 508:89] + node _T_3558 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[el2_lsu_bus_buffer.scala 508:124] + node _T_3559 = and(_T_3557, _T_3558) @[el2_lsu_bus_buffer.scala 508:104] + node _T_3560 = mux(_T_3559, UInt<3>("h05"), UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 508:75] + node _T_3561 = mux(_T_3556, UInt<3>("h00"), _T_3560) @[el2_lsu_bus_buffer.scala 508:31] + buf_nxtstate[0] <= _T_3561 @[el2_lsu_bus_buffer.scala 508:25] + node _T_3562 = eq(obuf_tag0, UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 509:48] + node _T_3563 = eq(obuf_tag1, UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 509:104] + node _T_3564 = and(obuf_merge, _T_3563) @[el2_lsu_bus_buffer.scala 509:91] + node _T_3565 = or(_T_3562, _T_3564) @[el2_lsu_bus_buffer.scala 509:77] + node _T_3566 = and(_T_3565, obuf_valid) @[el2_lsu_bus_buffer.scala 509:135] + node _T_3567 = and(_T_3566, obuf_wr_enQ) @[el2_lsu_bus_buffer.scala 509:148] + buf_cmd_state_bus_en[0] <= _T_3567 @[el2_lsu_bus_buffer.scala 509:33] + buf_state_bus_en[0] <= buf_cmd_state_bus_en[0] @[el2_lsu_bus_buffer.scala 510:29] + node _T_3568 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 511:49] + node _T_3569 = or(_T_3568, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 511:70] + buf_state_en[0] <= _T_3569 @[el2_lsu_bus_buffer.scala 511:25] + buf_ldfwd_in[0] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 512:25] + node _T_3570 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 513:56] + node _T_3571 = eq(_T_3570, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 513:46] + node _T_3572 = and(buf_state_en[0], _T_3571) @[el2_lsu_bus_buffer.scala 513:44] + node _T_3573 = and(_T_3572, obuf_nosend) @[el2_lsu_bus_buffer.scala 513:60] + node _T_3574 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 513:76] + node _T_3575 = and(_T_3573, _T_3574) @[el2_lsu_bus_buffer.scala 513:74] + buf_ldfwd_en[0] <= _T_3575 @[el2_lsu_bus_buffer.scala 513:25] + node _T_3576 = bits(obuf_rdrsp_tag, 1, 0) @[el2_lsu_bus_buffer.scala 514:46] + buf_ldfwdtag_in[0] <= _T_3576 @[el2_lsu_bus_buffer.scala 514:28] + node _T_3577 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 515:47] + node _T_3578 = and(_T_3577, obuf_nosend) @[el2_lsu_bus_buffer.scala 515:67] + node _T_3579 = and(_T_3578, bus_rsp_read) @[el2_lsu_bus_buffer.scala 515:81] + buf_data_en[0] <= _T_3579 @[el2_lsu_bus_buffer.scala 515:24] + node _T_3580 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 516:48] + node _T_3581 = and(_T_3580, obuf_nosend) @[el2_lsu_bus_buffer.scala 516:68] + node _T_3582 = and(_T_3581, bus_rsp_read_error) @[el2_lsu_bus_buffer.scala 516:82] + buf_error_en[0] <= _T_3582 @[el2_lsu_bus_buffer.scala 516:25] + node _T_3583 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 517:61] + node _T_3584 = bits(buf_addr[0], 2, 2) @[el2_lsu_bus_buffer.scala 517:85] + node _T_3585 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 517:103] + node _T_3586 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 517:126] + node _T_3587 = mux(_T_3584, _T_3585, _T_3586) @[el2_lsu_bus_buffer.scala 517:73] + node _T_3588 = mux(buf_error_en[0], _T_3583, _T_3587) @[el2_lsu_bus_buffer.scala 517:30] + buf_data_in[0] <= _T_3588 @[el2_lsu_bus_buffer.scala 517:24] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_3589 = eq(UInt<3>("h03"), buf_state[0]) @[Conditional.scala 37:30] when _T_3589 : @[Conditional.scala 39:67] - node _T_3590 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 519:67] - node _T_3591 = and(UInt<1>("h01"), bus_rsp_write_error) @[el2_lsu_bus_buffer.scala 519:94] - node _T_3592 = eq(_T_3591, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 519:73] - node _T_3593 = and(_T_3590, _T_3592) @[el2_lsu_bus_buffer.scala 519:71] - node _T_3594 = or(io.dec_tlu_force_halt, _T_3593) @[el2_lsu_bus_buffer.scala 519:55] - node _T_3595 = bits(_T_3594, 0, 0) @[el2_lsu_bus_buffer.scala 519:125] - node _T_3596 = eq(buf_samedw[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 520:30] - node _T_3597 = and(buf_dual[0], _T_3596) @[el2_lsu_bus_buffer.scala 520:28] - node _T_3598 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 520:57] - node _T_3599 = eq(_T_3598, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 520:47] - node _T_3600 = and(_T_3597, _T_3599) @[el2_lsu_bus_buffer.scala 520:45] - node _T_3601 = neq(buf_state[buf_dualtag[0]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 520:90] - node _T_3602 = and(_T_3600, _T_3601) @[el2_lsu_bus_buffer.scala 520:61] - node _T_3603 = bits(buf_ldfwd, 0, 0) @[el2_lsu_bus_buffer.scala 521:27] - node _T_3604 = or(_T_3603, any_done_wait_state) @[el2_lsu_bus_buffer.scala 521:31] - node _T_3605 = eq(buf_samedw[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 521:70] - node _T_3606 = and(buf_dual[0], _T_3605) @[el2_lsu_bus_buffer.scala 521:68] - node _T_3607 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 521:97] - node _T_3608 = eq(_T_3607, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 521:87] - node _T_3609 = and(_T_3606, _T_3608) @[el2_lsu_bus_buffer.scala 521:85] + node _T_3590 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 520:67] + node _T_3591 = and(UInt<1>("h01"), bus_rsp_write_error) @[el2_lsu_bus_buffer.scala 520:94] + node _T_3592 = eq(_T_3591, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 520:73] + node _T_3593 = and(_T_3590, _T_3592) @[el2_lsu_bus_buffer.scala 520:71] + node _T_3594 = or(io.dec_tlu_force_halt, _T_3593) @[el2_lsu_bus_buffer.scala 520:55] + node _T_3595 = bits(_T_3594, 0, 0) @[el2_lsu_bus_buffer.scala 520:125] + node _T_3596 = eq(buf_samedw[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 521:30] + node _T_3597 = and(buf_dual[0], _T_3596) @[el2_lsu_bus_buffer.scala 521:28] + node _T_3598 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 521:57] + node _T_3599 = eq(_T_3598, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 521:47] + node _T_3600 = and(_T_3597, _T_3599) @[el2_lsu_bus_buffer.scala 521:45] + node _T_3601 = neq(buf_state[buf_dualtag[0]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 521:90] + node _T_3602 = and(_T_3600, _T_3601) @[el2_lsu_bus_buffer.scala 521:61] + node _T_3603 = bits(buf_ldfwd, 0, 0) @[el2_lsu_bus_buffer.scala 522:27] + node _T_3604 = or(_T_3603, any_done_wait_state) @[el2_lsu_bus_buffer.scala 522:31] + node _T_3605 = eq(buf_samedw[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 522:70] + node _T_3606 = and(buf_dual[0], _T_3605) @[el2_lsu_bus_buffer.scala 522:68] + node _T_3607 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 522:97] + node _T_3608 = eq(_T_3607, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 522:87] + node _T_3609 = and(_T_3606, _T_3608) @[el2_lsu_bus_buffer.scala 522:85] node _T_3610 = eq(buf_dualtag[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] node _T_3611 = bits(buf_ldfwd, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] node _T_3612 = eq(buf_dualtag[0], UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] @@ -4573,265 +4571,265 @@ circuit el2_lsu_bus_intf : node _T_3624 = or(_T_3623, _T_3621) @[Mux.scala 27:72] wire _T_3625 : UInt<1> @[Mux.scala 27:72] _T_3625 <= _T_3624 @[Mux.scala 27:72] - node _T_3626 = and(_T_3609, _T_3625) @[el2_lsu_bus_buffer.scala 521:101] - node _T_3627 = eq(buf_state[buf_dualtag[0]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 521:167] - node _T_3628 = and(_T_3626, _T_3627) @[el2_lsu_bus_buffer.scala 521:138] - node _T_3629 = and(_T_3628, any_done_wait_state) @[el2_lsu_bus_buffer.scala 521:187] - node _T_3630 = or(_T_3604, _T_3629) @[el2_lsu_bus_buffer.scala 521:53] - node _T_3631 = mux(_T_3630, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 521:16] - node _T_3632 = mux(_T_3602, UInt<3>("h04"), _T_3631) @[el2_lsu_bus_buffer.scala 520:14] - node _T_3633 = mux(_T_3595, UInt<3>("h00"), _T_3632) @[el2_lsu_bus_buffer.scala 519:31] - buf_nxtstate[0] <= _T_3633 @[el2_lsu_bus_buffer.scala 519:25] - node _T_3634 = eq(bus_rsp_write_tag, UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 522:73] - node _T_3635 = and(bus_rsp_write, _T_3634) @[el2_lsu_bus_buffer.scala 522:52] - node _T_3636 = eq(bus_rsp_read_tag, UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 523:46] - node _T_3637 = bits(buf_ldfwd, 0, 0) @[el2_lsu_bus_buffer.scala 524:23] - node _T_3638 = eq(bus_rsp_read_tag, buf_ldfwdtag[0]) @[el2_lsu_bus_buffer.scala 524:47] - node _T_3639 = and(_T_3637, _T_3638) @[el2_lsu_bus_buffer.scala 524:27] - node _T_3640 = or(_T_3636, _T_3639) @[el2_lsu_bus_buffer.scala 523:77] - node _T_3641 = and(buf_dual[0], buf_dualhi[0]) @[el2_lsu_bus_buffer.scala 525:26] - node _T_3642 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 525:54] - node _T_3643 = not(_T_3642) @[el2_lsu_bus_buffer.scala 525:44] - node _T_3644 = and(_T_3641, _T_3643) @[el2_lsu_bus_buffer.scala 525:42] - node _T_3645 = and(_T_3644, buf_samedw[0]) @[el2_lsu_bus_buffer.scala 525:58] - node _T_3646 = eq(bus_rsp_read_tag, buf_dualtag[0]) @[el2_lsu_bus_buffer.scala 525:94] - node _T_3647 = and(_T_3645, _T_3646) @[el2_lsu_bus_buffer.scala 525:74] - node _T_3648 = or(_T_3640, _T_3647) @[el2_lsu_bus_buffer.scala 524:71] - node _T_3649 = and(bus_rsp_read, _T_3648) @[el2_lsu_bus_buffer.scala 523:25] - node _T_3650 = or(_T_3635, _T_3649) @[el2_lsu_bus_buffer.scala 522:105] - buf_resp_state_bus_en[0] <= _T_3650 @[el2_lsu_bus_buffer.scala 522:34] - buf_state_bus_en[0] <= buf_resp_state_bus_en[0] @[el2_lsu_bus_buffer.scala 526:29] - node _T_3651 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 527:49] - node _T_3652 = or(_T_3651, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 527:70] - buf_state_en[0] <= _T_3652 @[el2_lsu_bus_buffer.scala 527:25] - node _T_3653 = and(buf_state_bus_en[0], bus_rsp_read) @[el2_lsu_bus_buffer.scala 528:47] - node _T_3654 = and(_T_3653, io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 528:62] - buf_data_en[0] <= _T_3654 @[el2_lsu_bus_buffer.scala 528:24] - node _T_3655 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 529:48] - node _T_3656 = eq(bus_rsp_read_tag, UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 529:111] - node _T_3657 = and(bus_rsp_read_error, _T_3656) @[el2_lsu_bus_buffer.scala 529:91] - node _T_3658 = bits(buf_ldfwd, 0, 0) @[el2_lsu_bus_buffer.scala 530:42] - node _T_3659 = and(bus_rsp_read_error, _T_3658) @[el2_lsu_bus_buffer.scala 530:31] - node _T_3660 = eq(bus_rsp_read_tag, buf_ldfwdtag[0]) @[el2_lsu_bus_buffer.scala 530:66] - node _T_3661 = and(_T_3659, _T_3660) @[el2_lsu_bus_buffer.scala 530:46] - node _T_3662 = or(_T_3657, _T_3661) @[el2_lsu_bus_buffer.scala 529:143] - node _T_3663 = and(bus_rsp_write_error, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 531:32] - node _T_3664 = eq(bus_rsp_write_tag, UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 531:74] - node _T_3665 = and(_T_3663, _T_3664) @[el2_lsu_bus_buffer.scala 531:53] - node _T_3666 = or(_T_3662, _T_3665) @[el2_lsu_bus_buffer.scala 530:88] - node _T_3667 = and(_T_3655, _T_3666) @[el2_lsu_bus_buffer.scala 529:68] - buf_error_en[0] <= _T_3667 @[el2_lsu_bus_buffer.scala 529:25] - node _T_3668 = eq(buf_error_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 532:50] - node _T_3669 = and(buf_state_en[0], _T_3668) @[el2_lsu_bus_buffer.scala 532:48] - node _T_3670 = bits(buf_addr[0], 2, 2) @[el2_lsu_bus_buffer.scala 532:84] - node _T_3671 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 532:102] - node _T_3672 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 532:125] - node _T_3673 = mux(_T_3670, _T_3671, _T_3672) @[el2_lsu_bus_buffer.scala 532:72] - node _T_3674 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 532:148] - node _T_3675 = mux(_T_3669, _T_3673, _T_3674) @[el2_lsu_bus_buffer.scala 532:30] - buf_data_in[0] <= _T_3675 @[el2_lsu_bus_buffer.scala 532:24] + node _T_3626 = and(_T_3609, _T_3625) @[el2_lsu_bus_buffer.scala 522:101] + node _T_3627 = eq(buf_state[buf_dualtag[0]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 522:167] + node _T_3628 = and(_T_3626, _T_3627) @[el2_lsu_bus_buffer.scala 522:138] + node _T_3629 = and(_T_3628, any_done_wait_state) @[el2_lsu_bus_buffer.scala 522:187] + node _T_3630 = or(_T_3604, _T_3629) @[el2_lsu_bus_buffer.scala 522:53] + node _T_3631 = mux(_T_3630, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 522:16] + node _T_3632 = mux(_T_3602, UInt<3>("h04"), _T_3631) @[el2_lsu_bus_buffer.scala 521:14] + node _T_3633 = mux(_T_3595, UInt<3>("h00"), _T_3632) @[el2_lsu_bus_buffer.scala 520:31] + buf_nxtstate[0] <= _T_3633 @[el2_lsu_bus_buffer.scala 520:25] + node _T_3634 = eq(bus_rsp_write_tag, UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 523:73] + node _T_3635 = and(bus_rsp_write, _T_3634) @[el2_lsu_bus_buffer.scala 523:52] + node _T_3636 = eq(bus_rsp_read_tag, UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 524:46] + node _T_3637 = bits(buf_ldfwd, 0, 0) @[el2_lsu_bus_buffer.scala 525:23] + node _T_3638 = eq(bus_rsp_read_tag, buf_ldfwdtag[0]) @[el2_lsu_bus_buffer.scala 525:47] + node _T_3639 = and(_T_3637, _T_3638) @[el2_lsu_bus_buffer.scala 525:27] + node _T_3640 = or(_T_3636, _T_3639) @[el2_lsu_bus_buffer.scala 524:77] + node _T_3641 = and(buf_dual[0], buf_dualhi[0]) @[el2_lsu_bus_buffer.scala 526:26] + node _T_3642 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 526:54] + node _T_3643 = not(_T_3642) @[el2_lsu_bus_buffer.scala 526:44] + node _T_3644 = and(_T_3641, _T_3643) @[el2_lsu_bus_buffer.scala 526:42] + node _T_3645 = and(_T_3644, buf_samedw[0]) @[el2_lsu_bus_buffer.scala 526:58] + node _T_3646 = eq(bus_rsp_read_tag, buf_dualtag[0]) @[el2_lsu_bus_buffer.scala 526:94] + node _T_3647 = and(_T_3645, _T_3646) @[el2_lsu_bus_buffer.scala 526:74] + node _T_3648 = or(_T_3640, _T_3647) @[el2_lsu_bus_buffer.scala 525:71] + node _T_3649 = and(bus_rsp_read, _T_3648) @[el2_lsu_bus_buffer.scala 524:25] + node _T_3650 = or(_T_3635, _T_3649) @[el2_lsu_bus_buffer.scala 523:105] + buf_resp_state_bus_en[0] <= _T_3650 @[el2_lsu_bus_buffer.scala 523:34] + buf_state_bus_en[0] <= buf_resp_state_bus_en[0] @[el2_lsu_bus_buffer.scala 527:29] + node _T_3651 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 528:49] + node _T_3652 = or(_T_3651, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 528:70] + buf_state_en[0] <= _T_3652 @[el2_lsu_bus_buffer.scala 528:25] + node _T_3653 = and(buf_state_bus_en[0], bus_rsp_read) @[el2_lsu_bus_buffer.scala 529:47] + node _T_3654 = and(_T_3653, io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 529:62] + buf_data_en[0] <= _T_3654 @[el2_lsu_bus_buffer.scala 529:24] + node _T_3655 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 530:48] + node _T_3656 = eq(bus_rsp_read_tag, UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 530:111] + node _T_3657 = and(bus_rsp_read_error, _T_3656) @[el2_lsu_bus_buffer.scala 530:91] + node _T_3658 = bits(buf_ldfwd, 0, 0) @[el2_lsu_bus_buffer.scala 531:42] + node _T_3659 = and(bus_rsp_read_error, _T_3658) @[el2_lsu_bus_buffer.scala 531:31] + node _T_3660 = eq(bus_rsp_read_tag, buf_ldfwdtag[0]) @[el2_lsu_bus_buffer.scala 531:66] + node _T_3661 = and(_T_3659, _T_3660) @[el2_lsu_bus_buffer.scala 531:46] + node _T_3662 = or(_T_3657, _T_3661) @[el2_lsu_bus_buffer.scala 530:143] + node _T_3663 = and(bus_rsp_write_error, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 532:32] + node _T_3664 = eq(bus_rsp_write_tag, UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 532:74] + node _T_3665 = and(_T_3663, _T_3664) @[el2_lsu_bus_buffer.scala 532:53] + node _T_3666 = or(_T_3662, _T_3665) @[el2_lsu_bus_buffer.scala 531:88] + node _T_3667 = and(_T_3655, _T_3666) @[el2_lsu_bus_buffer.scala 530:68] + buf_error_en[0] <= _T_3667 @[el2_lsu_bus_buffer.scala 530:25] + node _T_3668 = eq(buf_error_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 533:50] + node _T_3669 = and(buf_state_en[0], _T_3668) @[el2_lsu_bus_buffer.scala 533:48] + node _T_3670 = bits(buf_addr[0], 2, 2) @[el2_lsu_bus_buffer.scala 533:84] + node _T_3671 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 533:102] + node _T_3672 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 533:125] + node _T_3673 = mux(_T_3670, _T_3671, _T_3672) @[el2_lsu_bus_buffer.scala 533:72] + node _T_3674 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 533:148] + node _T_3675 = mux(_T_3669, _T_3673, _T_3674) @[el2_lsu_bus_buffer.scala 533:30] + buf_data_in[0] <= _T_3675 @[el2_lsu_bus_buffer.scala 533:24] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_3676 = eq(UInt<3>("h04"), buf_state[0]) @[Conditional.scala 37:30] when _T_3676 : @[Conditional.scala 39:67] - node _T_3677 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 535:60] - node _T_3678 = bits(buf_ldfwd, 0, 0) @[el2_lsu_bus_buffer.scala 535:86] - node _T_3679 = dshr(buf_ldfwd, buf_dualtag[0]) @[el2_lsu_bus_buffer.scala 535:101] - node _T_3680 = bits(_T_3679, 0, 0) @[el2_lsu_bus_buffer.scala 535:101] - node _T_3681 = or(_T_3678, _T_3680) @[el2_lsu_bus_buffer.scala 535:90] - node _T_3682 = or(_T_3681, any_done_wait_state) @[el2_lsu_bus_buffer.scala 535:118] - node _T_3683 = mux(_T_3682, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 535:75] - node _T_3684 = mux(_T_3677, UInt<3>("h00"), _T_3683) @[el2_lsu_bus_buffer.scala 535:31] - buf_nxtstate[0] <= _T_3684 @[el2_lsu_bus_buffer.scala 535:25] - node _T_3685 = eq(bus_rsp_read_tag, buf_dualtag[0]) @[el2_lsu_bus_buffer.scala 536:66] - node _T_3686 = dshr(buf_ldfwd, buf_dualtag[0]) @[el2_lsu_bus_buffer.scala 537:21] - node _T_3687 = bits(_T_3686, 0, 0) @[el2_lsu_bus_buffer.scala 537:21] - node _T_3688 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[0]]) @[el2_lsu_bus_buffer.scala 537:58] - node _T_3689 = and(_T_3687, _T_3688) @[el2_lsu_bus_buffer.scala 537:38] - node _T_3690 = or(_T_3685, _T_3689) @[el2_lsu_bus_buffer.scala 536:95] - node _T_3691 = and(bus_rsp_read, _T_3690) @[el2_lsu_bus_buffer.scala 536:45] - buf_state_bus_en[0] <= _T_3691 @[el2_lsu_bus_buffer.scala 536:29] - node _T_3692 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 538:49] - node _T_3693 = or(_T_3692, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 538:70] - buf_state_en[0] <= _T_3693 @[el2_lsu_bus_buffer.scala 538:25] + node _T_3677 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 536:60] + node _T_3678 = bits(buf_ldfwd, 0, 0) @[el2_lsu_bus_buffer.scala 536:86] + node _T_3679 = dshr(buf_ldfwd, buf_dualtag[0]) @[el2_lsu_bus_buffer.scala 536:101] + node _T_3680 = bits(_T_3679, 0, 0) @[el2_lsu_bus_buffer.scala 536:101] + node _T_3681 = or(_T_3678, _T_3680) @[el2_lsu_bus_buffer.scala 536:90] + node _T_3682 = or(_T_3681, any_done_wait_state) @[el2_lsu_bus_buffer.scala 536:118] + node _T_3683 = mux(_T_3682, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 536:75] + node _T_3684 = mux(_T_3677, UInt<3>("h00"), _T_3683) @[el2_lsu_bus_buffer.scala 536:31] + buf_nxtstate[0] <= _T_3684 @[el2_lsu_bus_buffer.scala 536:25] + node _T_3685 = eq(bus_rsp_read_tag, buf_dualtag[0]) @[el2_lsu_bus_buffer.scala 537:66] + node _T_3686 = dshr(buf_ldfwd, buf_dualtag[0]) @[el2_lsu_bus_buffer.scala 538:21] + node _T_3687 = bits(_T_3686, 0, 0) @[el2_lsu_bus_buffer.scala 538:21] + node _T_3688 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[0]]) @[el2_lsu_bus_buffer.scala 538:58] + node _T_3689 = and(_T_3687, _T_3688) @[el2_lsu_bus_buffer.scala 538:38] + node _T_3690 = or(_T_3685, _T_3689) @[el2_lsu_bus_buffer.scala 537:95] + node _T_3691 = and(bus_rsp_read, _T_3690) @[el2_lsu_bus_buffer.scala 537:45] + buf_state_bus_en[0] <= _T_3691 @[el2_lsu_bus_buffer.scala 537:29] + node _T_3692 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 539:49] + node _T_3693 = or(_T_3692, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 539:70] + buf_state_en[0] <= _T_3693 @[el2_lsu_bus_buffer.scala 539:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_3694 = eq(UInt<3>("h05"), buf_state[0]) @[Conditional.scala 37:30] when _T_3694 : @[Conditional.scala 39:67] - node _T_3695 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 541:60] - node _T_3696 = mux(_T_3695, UInt<3>("h00"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 541:31] - buf_nxtstate[0] <= _T_3696 @[el2_lsu_bus_buffer.scala 541:25] - node _T_3697 = eq(RspPtr, UInt<2>("h00")) @[el2_lsu_bus_buffer.scala 542:37] - node _T_3698 = eq(buf_dualtag[0], RspPtr) @[el2_lsu_bus_buffer.scala 542:98] - node _T_3699 = and(buf_dual[0], _T_3698) @[el2_lsu_bus_buffer.scala 542:80] - node _T_3700 = or(_T_3697, _T_3699) @[el2_lsu_bus_buffer.scala 542:65] - node _T_3701 = or(_T_3700, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 542:112] - buf_state_en[0] <= _T_3701 @[el2_lsu_bus_buffer.scala 542:25] + node _T_3695 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 542:60] + node _T_3696 = mux(_T_3695, UInt<3>("h00"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 542:31] + buf_nxtstate[0] <= _T_3696 @[el2_lsu_bus_buffer.scala 542:25] + node _T_3697 = eq(RspPtr, UInt<2>("h00")) @[el2_lsu_bus_buffer.scala 543:37] + node _T_3698 = eq(buf_dualtag[0], RspPtr) @[el2_lsu_bus_buffer.scala 543:98] + node _T_3699 = and(buf_dual[0], _T_3698) @[el2_lsu_bus_buffer.scala 543:80] + node _T_3700 = or(_T_3697, _T_3699) @[el2_lsu_bus_buffer.scala 543:65] + node _T_3701 = or(_T_3700, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 543:112] + buf_state_en[0] <= _T_3701 @[el2_lsu_bus_buffer.scala 543:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_3702 = eq(UInt<3>("h06"), buf_state[0]) @[Conditional.scala 37:30] when _T_3702 : @[Conditional.scala 39:67] - buf_nxtstate[0] <= UInt<3>("h00") @[el2_lsu_bus_buffer.scala 545:25] - buf_rst[0] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 546:20] - buf_state_en[0] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 547:25] - buf_ldfwd_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 548:25] - buf_ldfwd_en[0] <= buf_state_en[0] @[el2_lsu_bus_buffer.scala 549:25] + buf_nxtstate[0] <= UInt<3>("h00") @[el2_lsu_bus_buffer.scala 546:25] + buf_rst[0] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 547:20] + buf_state_en[0] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 548:25] + buf_ldfwd_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 549:25] + buf_ldfwd_en[0] <= buf_state_en[0] @[el2_lsu_bus_buffer.scala 550:25] skip @[Conditional.scala 39:67] - node _T_3703 = bits(buf_state_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 552:108] + node _T_3703 = bits(buf_state_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 553:108] reg _T_3704 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_3703 : @[Reg.scala 28:19] _T_3704 <= buf_nxtstate[0] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_state[0] <= _T_3704 @[el2_lsu_bus_buffer.scala 552:18] - reg _T_3705 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 553:60] - _T_3705 <= buf_age_in_0 @[el2_lsu_bus_buffer.scala 553:60] - buf_ageQ[0] <= _T_3705 @[el2_lsu_bus_buffer.scala 553:17] - reg _T_3706 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 554:63] - _T_3706 <= buf_rspage_in[0] @[el2_lsu_bus_buffer.scala 554:63] - buf_rspageQ[0] <= _T_3706 @[el2_lsu_bus_buffer.scala 554:20] - node _T_3707 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 555:109] + buf_state[0] <= _T_3704 @[el2_lsu_bus_buffer.scala 553:18] + reg _T_3705 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 554:60] + _T_3705 <= buf_age_in_0 @[el2_lsu_bus_buffer.scala 554:60] + buf_ageQ[0] <= _T_3705 @[el2_lsu_bus_buffer.scala 554:17] + reg _T_3706 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 555:63] + _T_3706 <= buf_rspage_in[0] @[el2_lsu_bus_buffer.scala 555:63] + buf_rspageQ[0] <= _T_3706 @[el2_lsu_bus_buffer.scala 555:20] + node _T_3707 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 556:109] reg _T_3708 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_3707 : @[Reg.scala 28:19] _T_3708 <= buf_dualtag_in[0] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_dualtag[0] <= _T_3708 @[el2_lsu_bus_buffer.scala 555:20] - node _T_3709 = bits(buf_dual_in, 0, 0) @[el2_lsu_bus_buffer.scala 556:74] - node _T_3710 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 556:107] + buf_dualtag[0] <= _T_3708 @[el2_lsu_bus_buffer.scala 556:20] + node _T_3709 = bits(buf_dual_in, 0, 0) @[el2_lsu_bus_buffer.scala 557:74] + node _T_3710 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 557:107] reg _T_3711 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_3710 : @[Reg.scala 28:19] _T_3711 <= _T_3709 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_dual[0] <= _T_3711 @[el2_lsu_bus_buffer.scala 556:17] - node _T_3712 = bits(buf_samedw_in, 0, 0) @[el2_lsu_bus_buffer.scala 557:78] - node _T_3713 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 557:111] + buf_dual[0] <= _T_3711 @[el2_lsu_bus_buffer.scala 557:17] + node _T_3712 = bits(buf_samedw_in, 0, 0) @[el2_lsu_bus_buffer.scala 558:78] + node _T_3713 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 558:111] reg _T_3714 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_3713 : @[Reg.scala 28:19] _T_3714 <= _T_3712 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_samedw[0] <= _T_3714 @[el2_lsu_bus_buffer.scala 557:19] - node _T_3715 = bits(buf_nomerge_in, 0, 0) @[el2_lsu_bus_buffer.scala 558:80] - node _T_3716 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 558:113] + buf_samedw[0] <= _T_3714 @[el2_lsu_bus_buffer.scala 558:19] + node _T_3715 = bits(buf_nomerge_in, 0, 0) @[el2_lsu_bus_buffer.scala 559:80] + node _T_3716 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 559:113] reg _T_3717 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_3716 : @[Reg.scala 28:19] _T_3717 <= _T_3715 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_nomerge[0] <= _T_3717 @[el2_lsu_bus_buffer.scala 558:20] - node _T_3718 = bits(buf_dualhi_in, 0, 0) @[el2_lsu_bus_buffer.scala 559:78] - node _T_3719 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 559:111] + buf_nomerge[0] <= _T_3717 @[el2_lsu_bus_buffer.scala 559:20] + node _T_3718 = bits(buf_dualhi_in, 0, 0) @[el2_lsu_bus_buffer.scala 560:78] + node _T_3719 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 560:111] reg _T_3720 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_3719 : @[Reg.scala 28:19] _T_3720 <= _T_3718 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_dualhi[0] <= _T_3720 @[el2_lsu_bus_buffer.scala 559:19] + buf_dualhi[0] <= _T_3720 @[el2_lsu_bus_buffer.scala 560:19] node _T_3721 = eq(UInt<3>("h00"), buf_state[1]) @[Conditional.scala 37:30] when _T_3721 : @[Conditional.scala 40:58] - node _T_3722 = bits(io.lsu_bus_clk_en, 0, 0) @[el2_lsu_bus_buffer.scala 496:56] - node _T_3723 = mux(_T_3722, UInt<3>("h02"), UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 496:31] - buf_nxtstate[1] <= _T_3723 @[el2_lsu_bus_buffer.scala 496:25] - node _T_3724 = and(io.lsu_busreq_r, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 497:45] - node _T_3725 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 497:77] - node _T_3726 = eq(ibuf_merge_en, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 497:97] - node _T_3727 = and(_T_3725, _T_3726) @[el2_lsu_bus_buffer.scala 497:95] - node _T_3728 = eq(UInt<1>("h01"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 497:117] - node _T_3729 = and(_T_3727, _T_3728) @[el2_lsu_bus_buffer.scala 497:112] - node _T_3730 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 497:144] - node _T_3731 = eq(UInt<1>("h01"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 497:166] - node _T_3732 = and(_T_3730, _T_3731) @[el2_lsu_bus_buffer.scala 497:161] - node _T_3733 = or(_T_3729, _T_3732) @[el2_lsu_bus_buffer.scala 497:132] - node _T_3734 = and(_T_3724, _T_3733) @[el2_lsu_bus_buffer.scala 497:63] - node _T_3735 = eq(UInt<1>("h01"), ibuf_tag) @[el2_lsu_bus_buffer.scala 497:206] - node _T_3736 = and(ibuf_drain_vld, _T_3735) @[el2_lsu_bus_buffer.scala 497:201] - node _T_3737 = or(_T_3734, _T_3736) @[el2_lsu_bus_buffer.scala 497:183] - buf_state_en[1] <= _T_3737 @[el2_lsu_bus_buffer.scala 497:25] - buf_wr_en[1] <= buf_state_en[1] @[el2_lsu_bus_buffer.scala 498:22] - buf_data_en[1] <= buf_state_en[1] @[el2_lsu_bus_buffer.scala 499:24] - node _T_3738 = eq(UInt<1>("h01"), ibuf_tag) @[el2_lsu_bus_buffer.scala 500:52] - node _T_3739 = and(ibuf_drain_vld, _T_3738) @[el2_lsu_bus_buffer.scala 500:47] - node _T_3740 = bits(_T_3739, 0, 0) @[el2_lsu_bus_buffer.scala 500:73] - node _T_3741 = bits(ibuf_data_out, 31, 0) @[el2_lsu_bus_buffer.scala 500:90] - node _T_3742 = bits(store_data_lo_r, 31, 0) @[el2_lsu_bus_buffer.scala 500:114] - node _T_3743 = mux(_T_3740, _T_3741, _T_3742) @[el2_lsu_bus_buffer.scala 500:30] - buf_data_in[1] <= _T_3743 @[el2_lsu_bus_buffer.scala 500:24] + node _T_3722 = bits(io.lsu_bus_clk_en, 0, 0) @[el2_lsu_bus_buffer.scala 497:56] + node _T_3723 = mux(_T_3722, UInt<3>("h02"), UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 497:31] + buf_nxtstate[1] <= _T_3723 @[el2_lsu_bus_buffer.scala 497:25] + node _T_3724 = and(io.lsu_busreq_r, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 498:45] + node _T_3725 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 498:77] + node _T_3726 = eq(ibuf_merge_en, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 498:97] + node _T_3727 = and(_T_3725, _T_3726) @[el2_lsu_bus_buffer.scala 498:95] + node _T_3728 = eq(UInt<1>("h01"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 498:117] + node _T_3729 = and(_T_3727, _T_3728) @[el2_lsu_bus_buffer.scala 498:112] + node _T_3730 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 498:144] + node _T_3731 = eq(UInt<1>("h01"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 498:166] + node _T_3732 = and(_T_3730, _T_3731) @[el2_lsu_bus_buffer.scala 498:161] + node _T_3733 = or(_T_3729, _T_3732) @[el2_lsu_bus_buffer.scala 498:132] + node _T_3734 = and(_T_3724, _T_3733) @[el2_lsu_bus_buffer.scala 498:63] + node _T_3735 = eq(UInt<1>("h01"), ibuf_tag) @[el2_lsu_bus_buffer.scala 498:206] + node _T_3736 = and(ibuf_drain_vld, _T_3735) @[el2_lsu_bus_buffer.scala 498:201] + node _T_3737 = or(_T_3734, _T_3736) @[el2_lsu_bus_buffer.scala 498:183] + buf_state_en[1] <= _T_3737 @[el2_lsu_bus_buffer.scala 498:25] + buf_wr_en[1] <= buf_state_en[1] @[el2_lsu_bus_buffer.scala 499:22] + buf_data_en[1] <= buf_state_en[1] @[el2_lsu_bus_buffer.scala 500:24] + node _T_3738 = eq(UInt<1>("h01"), ibuf_tag) @[el2_lsu_bus_buffer.scala 501:52] + node _T_3739 = and(ibuf_drain_vld, _T_3738) @[el2_lsu_bus_buffer.scala 501:47] + node _T_3740 = bits(_T_3739, 0, 0) @[el2_lsu_bus_buffer.scala 501:73] + node _T_3741 = bits(ibuf_data_out, 31, 0) @[el2_lsu_bus_buffer.scala 501:90] + node _T_3742 = bits(store_data_lo_r, 31, 0) @[el2_lsu_bus_buffer.scala 501:114] + node _T_3743 = mux(_T_3740, _T_3741, _T_3742) @[el2_lsu_bus_buffer.scala 501:30] + buf_data_in[1] <= _T_3743 @[el2_lsu_bus_buffer.scala 501:24] skip @[Conditional.scala 40:58] else : @[Conditional.scala 39:67] node _T_3744 = eq(UInt<3>("h01"), buf_state[1]) @[Conditional.scala 37:30] when _T_3744 : @[Conditional.scala 39:67] - node _T_3745 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 503:60] - node _T_3746 = mux(_T_3745, UInt<3>("h00"), UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 503:31] - buf_nxtstate[1] <= _T_3746 @[el2_lsu_bus_buffer.scala 503:25] - node _T_3747 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 504:46] - buf_state_en[1] <= _T_3747 @[el2_lsu_bus_buffer.scala 504:25] + node _T_3745 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 504:60] + node _T_3746 = mux(_T_3745, UInt<3>("h00"), UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 504:31] + buf_nxtstate[1] <= _T_3746 @[el2_lsu_bus_buffer.scala 504:25] + node _T_3747 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 505:46] + buf_state_en[1] <= _T_3747 @[el2_lsu_bus_buffer.scala 505:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_3748 = eq(UInt<3>("h02"), buf_state[1]) @[Conditional.scala 37:30] when _T_3748 : @[Conditional.scala 39:67] - node _T_3749 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 507:60] - node _T_3750 = and(obuf_nosend, bus_rsp_read) @[el2_lsu_bus_buffer.scala 507:89] - node _T_3751 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[el2_lsu_bus_buffer.scala 507:124] - node _T_3752 = and(_T_3750, _T_3751) @[el2_lsu_bus_buffer.scala 507:104] - node _T_3753 = mux(_T_3752, UInt<3>("h05"), UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 507:75] - node _T_3754 = mux(_T_3749, UInt<3>("h00"), _T_3753) @[el2_lsu_bus_buffer.scala 507:31] - buf_nxtstate[1] <= _T_3754 @[el2_lsu_bus_buffer.scala 507:25] - node _T_3755 = eq(obuf_tag0, UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 508:48] - node _T_3756 = eq(obuf_tag1, UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 508:104] - node _T_3757 = and(obuf_merge, _T_3756) @[el2_lsu_bus_buffer.scala 508:91] - node _T_3758 = or(_T_3755, _T_3757) @[el2_lsu_bus_buffer.scala 508:77] - node _T_3759 = and(_T_3758, obuf_valid) @[el2_lsu_bus_buffer.scala 508:135] - node _T_3760 = and(_T_3759, obuf_wr_enQ) @[el2_lsu_bus_buffer.scala 508:148] - buf_cmd_state_bus_en[1] <= _T_3760 @[el2_lsu_bus_buffer.scala 508:33] - buf_state_bus_en[1] <= buf_cmd_state_bus_en[1] @[el2_lsu_bus_buffer.scala 509:29] - node _T_3761 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 510:49] - node _T_3762 = or(_T_3761, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 510:70] - buf_state_en[1] <= _T_3762 @[el2_lsu_bus_buffer.scala 510:25] - buf_ldfwd_in[1] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 511:25] - node _T_3763 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 512:56] - node _T_3764 = eq(_T_3763, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 512:46] - node _T_3765 = and(buf_state_en[1], _T_3764) @[el2_lsu_bus_buffer.scala 512:44] - node _T_3766 = and(_T_3765, obuf_nosend) @[el2_lsu_bus_buffer.scala 512:60] - node _T_3767 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 512:76] - node _T_3768 = and(_T_3766, _T_3767) @[el2_lsu_bus_buffer.scala 512:74] - buf_ldfwd_en[1] <= _T_3768 @[el2_lsu_bus_buffer.scala 512:25] - node _T_3769 = bits(obuf_rdrsp_tag, 1, 0) @[el2_lsu_bus_buffer.scala 513:46] - buf_ldfwdtag_in[1] <= _T_3769 @[el2_lsu_bus_buffer.scala 513:28] - node _T_3770 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 514:47] - node _T_3771 = and(_T_3770, obuf_nosend) @[el2_lsu_bus_buffer.scala 514:67] - node _T_3772 = and(_T_3771, bus_rsp_read) @[el2_lsu_bus_buffer.scala 514:81] - buf_data_en[1] <= _T_3772 @[el2_lsu_bus_buffer.scala 514:24] - node _T_3773 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 515:48] - node _T_3774 = and(_T_3773, obuf_nosend) @[el2_lsu_bus_buffer.scala 515:68] - node _T_3775 = and(_T_3774, bus_rsp_read_error) @[el2_lsu_bus_buffer.scala 515:82] - buf_error_en[1] <= _T_3775 @[el2_lsu_bus_buffer.scala 515:25] - node _T_3776 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 516:61] - node _T_3777 = bits(buf_addr[1], 2, 2) @[el2_lsu_bus_buffer.scala 516:85] - node _T_3778 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 516:103] - node _T_3779 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 516:126] - node _T_3780 = mux(_T_3777, _T_3778, _T_3779) @[el2_lsu_bus_buffer.scala 516:73] - node _T_3781 = mux(buf_error_en[1], _T_3776, _T_3780) @[el2_lsu_bus_buffer.scala 516:30] - buf_data_in[1] <= _T_3781 @[el2_lsu_bus_buffer.scala 516:24] + node _T_3749 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 508:60] + node _T_3750 = and(obuf_nosend, bus_rsp_read) @[el2_lsu_bus_buffer.scala 508:89] + node _T_3751 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[el2_lsu_bus_buffer.scala 508:124] + node _T_3752 = and(_T_3750, _T_3751) @[el2_lsu_bus_buffer.scala 508:104] + node _T_3753 = mux(_T_3752, UInt<3>("h05"), UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 508:75] + node _T_3754 = mux(_T_3749, UInt<3>("h00"), _T_3753) @[el2_lsu_bus_buffer.scala 508:31] + buf_nxtstate[1] <= _T_3754 @[el2_lsu_bus_buffer.scala 508:25] + node _T_3755 = eq(obuf_tag0, UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 509:48] + node _T_3756 = eq(obuf_tag1, UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 509:104] + node _T_3757 = and(obuf_merge, _T_3756) @[el2_lsu_bus_buffer.scala 509:91] + node _T_3758 = or(_T_3755, _T_3757) @[el2_lsu_bus_buffer.scala 509:77] + node _T_3759 = and(_T_3758, obuf_valid) @[el2_lsu_bus_buffer.scala 509:135] + node _T_3760 = and(_T_3759, obuf_wr_enQ) @[el2_lsu_bus_buffer.scala 509:148] + buf_cmd_state_bus_en[1] <= _T_3760 @[el2_lsu_bus_buffer.scala 509:33] + buf_state_bus_en[1] <= buf_cmd_state_bus_en[1] @[el2_lsu_bus_buffer.scala 510:29] + node _T_3761 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 511:49] + node _T_3762 = or(_T_3761, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 511:70] + buf_state_en[1] <= _T_3762 @[el2_lsu_bus_buffer.scala 511:25] + buf_ldfwd_in[1] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 512:25] + node _T_3763 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 513:56] + node _T_3764 = eq(_T_3763, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 513:46] + node _T_3765 = and(buf_state_en[1], _T_3764) @[el2_lsu_bus_buffer.scala 513:44] + node _T_3766 = and(_T_3765, obuf_nosend) @[el2_lsu_bus_buffer.scala 513:60] + node _T_3767 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 513:76] + node _T_3768 = and(_T_3766, _T_3767) @[el2_lsu_bus_buffer.scala 513:74] + buf_ldfwd_en[1] <= _T_3768 @[el2_lsu_bus_buffer.scala 513:25] + node _T_3769 = bits(obuf_rdrsp_tag, 1, 0) @[el2_lsu_bus_buffer.scala 514:46] + buf_ldfwdtag_in[1] <= _T_3769 @[el2_lsu_bus_buffer.scala 514:28] + node _T_3770 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 515:47] + node _T_3771 = and(_T_3770, obuf_nosend) @[el2_lsu_bus_buffer.scala 515:67] + node _T_3772 = and(_T_3771, bus_rsp_read) @[el2_lsu_bus_buffer.scala 515:81] + buf_data_en[1] <= _T_3772 @[el2_lsu_bus_buffer.scala 515:24] + node _T_3773 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 516:48] + node _T_3774 = and(_T_3773, obuf_nosend) @[el2_lsu_bus_buffer.scala 516:68] + node _T_3775 = and(_T_3774, bus_rsp_read_error) @[el2_lsu_bus_buffer.scala 516:82] + buf_error_en[1] <= _T_3775 @[el2_lsu_bus_buffer.scala 516:25] + node _T_3776 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 517:61] + node _T_3777 = bits(buf_addr[1], 2, 2) @[el2_lsu_bus_buffer.scala 517:85] + node _T_3778 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 517:103] + node _T_3779 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 517:126] + node _T_3780 = mux(_T_3777, _T_3778, _T_3779) @[el2_lsu_bus_buffer.scala 517:73] + node _T_3781 = mux(buf_error_en[1], _T_3776, _T_3780) @[el2_lsu_bus_buffer.scala 517:30] + buf_data_in[1] <= _T_3781 @[el2_lsu_bus_buffer.scala 517:24] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_3782 = eq(UInt<3>("h03"), buf_state[1]) @[Conditional.scala 37:30] when _T_3782 : @[Conditional.scala 39:67] - node _T_3783 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 519:67] - node _T_3784 = and(UInt<1>("h01"), bus_rsp_write_error) @[el2_lsu_bus_buffer.scala 519:94] - node _T_3785 = eq(_T_3784, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 519:73] - node _T_3786 = and(_T_3783, _T_3785) @[el2_lsu_bus_buffer.scala 519:71] - node _T_3787 = or(io.dec_tlu_force_halt, _T_3786) @[el2_lsu_bus_buffer.scala 519:55] - node _T_3788 = bits(_T_3787, 0, 0) @[el2_lsu_bus_buffer.scala 519:125] - node _T_3789 = eq(buf_samedw[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 520:30] - node _T_3790 = and(buf_dual[1], _T_3789) @[el2_lsu_bus_buffer.scala 520:28] - node _T_3791 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 520:57] - node _T_3792 = eq(_T_3791, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 520:47] - node _T_3793 = and(_T_3790, _T_3792) @[el2_lsu_bus_buffer.scala 520:45] - node _T_3794 = neq(buf_state[buf_dualtag[1]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 520:90] - node _T_3795 = and(_T_3793, _T_3794) @[el2_lsu_bus_buffer.scala 520:61] - node _T_3796 = bits(buf_ldfwd, 1, 1) @[el2_lsu_bus_buffer.scala 521:27] - node _T_3797 = or(_T_3796, any_done_wait_state) @[el2_lsu_bus_buffer.scala 521:31] - node _T_3798 = eq(buf_samedw[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 521:70] - node _T_3799 = and(buf_dual[1], _T_3798) @[el2_lsu_bus_buffer.scala 521:68] - node _T_3800 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 521:97] - node _T_3801 = eq(_T_3800, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 521:87] - node _T_3802 = and(_T_3799, _T_3801) @[el2_lsu_bus_buffer.scala 521:85] + node _T_3783 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 520:67] + node _T_3784 = and(UInt<1>("h01"), bus_rsp_write_error) @[el2_lsu_bus_buffer.scala 520:94] + node _T_3785 = eq(_T_3784, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 520:73] + node _T_3786 = and(_T_3783, _T_3785) @[el2_lsu_bus_buffer.scala 520:71] + node _T_3787 = or(io.dec_tlu_force_halt, _T_3786) @[el2_lsu_bus_buffer.scala 520:55] + node _T_3788 = bits(_T_3787, 0, 0) @[el2_lsu_bus_buffer.scala 520:125] + node _T_3789 = eq(buf_samedw[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 521:30] + node _T_3790 = and(buf_dual[1], _T_3789) @[el2_lsu_bus_buffer.scala 521:28] + node _T_3791 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 521:57] + node _T_3792 = eq(_T_3791, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 521:47] + node _T_3793 = and(_T_3790, _T_3792) @[el2_lsu_bus_buffer.scala 521:45] + node _T_3794 = neq(buf_state[buf_dualtag[1]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 521:90] + node _T_3795 = and(_T_3793, _T_3794) @[el2_lsu_bus_buffer.scala 521:61] + node _T_3796 = bits(buf_ldfwd, 1, 1) @[el2_lsu_bus_buffer.scala 522:27] + node _T_3797 = or(_T_3796, any_done_wait_state) @[el2_lsu_bus_buffer.scala 522:31] + node _T_3798 = eq(buf_samedw[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 522:70] + node _T_3799 = and(buf_dual[1], _T_3798) @[el2_lsu_bus_buffer.scala 522:68] + node _T_3800 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 522:97] + node _T_3801 = eq(_T_3800, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 522:87] + node _T_3802 = and(_T_3799, _T_3801) @[el2_lsu_bus_buffer.scala 522:85] node _T_3803 = eq(buf_dualtag[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] node _T_3804 = bits(buf_ldfwd, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] node _T_3805 = eq(buf_dualtag[1], UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] @@ -4849,265 +4847,265 @@ circuit el2_lsu_bus_intf : node _T_3817 = or(_T_3816, _T_3814) @[Mux.scala 27:72] wire _T_3818 : UInt<1> @[Mux.scala 27:72] _T_3818 <= _T_3817 @[Mux.scala 27:72] - node _T_3819 = and(_T_3802, _T_3818) @[el2_lsu_bus_buffer.scala 521:101] - node _T_3820 = eq(buf_state[buf_dualtag[1]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 521:167] - node _T_3821 = and(_T_3819, _T_3820) @[el2_lsu_bus_buffer.scala 521:138] - node _T_3822 = and(_T_3821, any_done_wait_state) @[el2_lsu_bus_buffer.scala 521:187] - node _T_3823 = or(_T_3797, _T_3822) @[el2_lsu_bus_buffer.scala 521:53] - node _T_3824 = mux(_T_3823, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 521:16] - node _T_3825 = mux(_T_3795, UInt<3>("h04"), _T_3824) @[el2_lsu_bus_buffer.scala 520:14] - node _T_3826 = mux(_T_3788, UInt<3>("h00"), _T_3825) @[el2_lsu_bus_buffer.scala 519:31] - buf_nxtstate[1] <= _T_3826 @[el2_lsu_bus_buffer.scala 519:25] - node _T_3827 = eq(bus_rsp_write_tag, UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 522:73] - node _T_3828 = and(bus_rsp_write, _T_3827) @[el2_lsu_bus_buffer.scala 522:52] - node _T_3829 = eq(bus_rsp_read_tag, UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 523:46] - node _T_3830 = bits(buf_ldfwd, 1, 1) @[el2_lsu_bus_buffer.scala 524:23] - node _T_3831 = eq(bus_rsp_read_tag, buf_ldfwdtag[1]) @[el2_lsu_bus_buffer.scala 524:47] - node _T_3832 = and(_T_3830, _T_3831) @[el2_lsu_bus_buffer.scala 524:27] - node _T_3833 = or(_T_3829, _T_3832) @[el2_lsu_bus_buffer.scala 523:77] - node _T_3834 = and(buf_dual[1], buf_dualhi[1]) @[el2_lsu_bus_buffer.scala 525:26] - node _T_3835 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 525:54] - node _T_3836 = not(_T_3835) @[el2_lsu_bus_buffer.scala 525:44] - node _T_3837 = and(_T_3834, _T_3836) @[el2_lsu_bus_buffer.scala 525:42] - node _T_3838 = and(_T_3837, buf_samedw[1]) @[el2_lsu_bus_buffer.scala 525:58] - node _T_3839 = eq(bus_rsp_read_tag, buf_dualtag[1]) @[el2_lsu_bus_buffer.scala 525:94] - node _T_3840 = and(_T_3838, _T_3839) @[el2_lsu_bus_buffer.scala 525:74] - node _T_3841 = or(_T_3833, _T_3840) @[el2_lsu_bus_buffer.scala 524:71] - node _T_3842 = and(bus_rsp_read, _T_3841) @[el2_lsu_bus_buffer.scala 523:25] - node _T_3843 = or(_T_3828, _T_3842) @[el2_lsu_bus_buffer.scala 522:105] - buf_resp_state_bus_en[1] <= _T_3843 @[el2_lsu_bus_buffer.scala 522:34] - buf_state_bus_en[1] <= buf_resp_state_bus_en[1] @[el2_lsu_bus_buffer.scala 526:29] - node _T_3844 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 527:49] - node _T_3845 = or(_T_3844, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 527:70] - buf_state_en[1] <= _T_3845 @[el2_lsu_bus_buffer.scala 527:25] - node _T_3846 = and(buf_state_bus_en[1], bus_rsp_read) @[el2_lsu_bus_buffer.scala 528:47] - node _T_3847 = and(_T_3846, io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 528:62] - buf_data_en[1] <= _T_3847 @[el2_lsu_bus_buffer.scala 528:24] - node _T_3848 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 529:48] - node _T_3849 = eq(bus_rsp_read_tag, UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 529:111] - node _T_3850 = and(bus_rsp_read_error, _T_3849) @[el2_lsu_bus_buffer.scala 529:91] - node _T_3851 = bits(buf_ldfwd, 1, 1) @[el2_lsu_bus_buffer.scala 530:42] - node _T_3852 = and(bus_rsp_read_error, _T_3851) @[el2_lsu_bus_buffer.scala 530:31] - node _T_3853 = eq(bus_rsp_read_tag, buf_ldfwdtag[1]) @[el2_lsu_bus_buffer.scala 530:66] - node _T_3854 = and(_T_3852, _T_3853) @[el2_lsu_bus_buffer.scala 530:46] - node _T_3855 = or(_T_3850, _T_3854) @[el2_lsu_bus_buffer.scala 529:143] - node _T_3856 = and(bus_rsp_write_error, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 531:32] - node _T_3857 = eq(bus_rsp_write_tag, UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 531:74] - node _T_3858 = and(_T_3856, _T_3857) @[el2_lsu_bus_buffer.scala 531:53] - node _T_3859 = or(_T_3855, _T_3858) @[el2_lsu_bus_buffer.scala 530:88] - node _T_3860 = and(_T_3848, _T_3859) @[el2_lsu_bus_buffer.scala 529:68] - buf_error_en[1] <= _T_3860 @[el2_lsu_bus_buffer.scala 529:25] - node _T_3861 = eq(buf_error_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 532:50] - node _T_3862 = and(buf_state_en[1], _T_3861) @[el2_lsu_bus_buffer.scala 532:48] - node _T_3863 = bits(buf_addr[1], 2, 2) @[el2_lsu_bus_buffer.scala 532:84] - node _T_3864 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 532:102] - node _T_3865 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 532:125] - node _T_3866 = mux(_T_3863, _T_3864, _T_3865) @[el2_lsu_bus_buffer.scala 532:72] - node _T_3867 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 532:148] - node _T_3868 = mux(_T_3862, _T_3866, _T_3867) @[el2_lsu_bus_buffer.scala 532:30] - buf_data_in[1] <= _T_3868 @[el2_lsu_bus_buffer.scala 532:24] + node _T_3819 = and(_T_3802, _T_3818) @[el2_lsu_bus_buffer.scala 522:101] + node _T_3820 = eq(buf_state[buf_dualtag[1]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 522:167] + node _T_3821 = and(_T_3819, _T_3820) @[el2_lsu_bus_buffer.scala 522:138] + node _T_3822 = and(_T_3821, any_done_wait_state) @[el2_lsu_bus_buffer.scala 522:187] + node _T_3823 = or(_T_3797, _T_3822) @[el2_lsu_bus_buffer.scala 522:53] + node _T_3824 = mux(_T_3823, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 522:16] + node _T_3825 = mux(_T_3795, UInt<3>("h04"), _T_3824) @[el2_lsu_bus_buffer.scala 521:14] + node _T_3826 = mux(_T_3788, UInt<3>("h00"), _T_3825) @[el2_lsu_bus_buffer.scala 520:31] + buf_nxtstate[1] <= _T_3826 @[el2_lsu_bus_buffer.scala 520:25] + node _T_3827 = eq(bus_rsp_write_tag, UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 523:73] + node _T_3828 = and(bus_rsp_write, _T_3827) @[el2_lsu_bus_buffer.scala 523:52] + node _T_3829 = eq(bus_rsp_read_tag, UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 524:46] + node _T_3830 = bits(buf_ldfwd, 1, 1) @[el2_lsu_bus_buffer.scala 525:23] + node _T_3831 = eq(bus_rsp_read_tag, buf_ldfwdtag[1]) @[el2_lsu_bus_buffer.scala 525:47] + node _T_3832 = and(_T_3830, _T_3831) @[el2_lsu_bus_buffer.scala 525:27] + node _T_3833 = or(_T_3829, _T_3832) @[el2_lsu_bus_buffer.scala 524:77] + node _T_3834 = and(buf_dual[1], buf_dualhi[1]) @[el2_lsu_bus_buffer.scala 526:26] + node _T_3835 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 526:54] + node _T_3836 = not(_T_3835) @[el2_lsu_bus_buffer.scala 526:44] + node _T_3837 = and(_T_3834, _T_3836) @[el2_lsu_bus_buffer.scala 526:42] + node _T_3838 = and(_T_3837, buf_samedw[1]) @[el2_lsu_bus_buffer.scala 526:58] + node _T_3839 = eq(bus_rsp_read_tag, buf_dualtag[1]) @[el2_lsu_bus_buffer.scala 526:94] + node _T_3840 = and(_T_3838, _T_3839) @[el2_lsu_bus_buffer.scala 526:74] + node _T_3841 = or(_T_3833, _T_3840) @[el2_lsu_bus_buffer.scala 525:71] + node _T_3842 = and(bus_rsp_read, _T_3841) @[el2_lsu_bus_buffer.scala 524:25] + node _T_3843 = or(_T_3828, _T_3842) @[el2_lsu_bus_buffer.scala 523:105] + buf_resp_state_bus_en[1] <= _T_3843 @[el2_lsu_bus_buffer.scala 523:34] + buf_state_bus_en[1] <= buf_resp_state_bus_en[1] @[el2_lsu_bus_buffer.scala 527:29] + node _T_3844 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 528:49] + node _T_3845 = or(_T_3844, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 528:70] + buf_state_en[1] <= _T_3845 @[el2_lsu_bus_buffer.scala 528:25] + node _T_3846 = and(buf_state_bus_en[1], bus_rsp_read) @[el2_lsu_bus_buffer.scala 529:47] + node _T_3847 = and(_T_3846, io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 529:62] + buf_data_en[1] <= _T_3847 @[el2_lsu_bus_buffer.scala 529:24] + node _T_3848 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 530:48] + node _T_3849 = eq(bus_rsp_read_tag, UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 530:111] + node _T_3850 = and(bus_rsp_read_error, _T_3849) @[el2_lsu_bus_buffer.scala 530:91] + node _T_3851 = bits(buf_ldfwd, 1, 1) @[el2_lsu_bus_buffer.scala 531:42] + node _T_3852 = and(bus_rsp_read_error, _T_3851) @[el2_lsu_bus_buffer.scala 531:31] + node _T_3853 = eq(bus_rsp_read_tag, buf_ldfwdtag[1]) @[el2_lsu_bus_buffer.scala 531:66] + node _T_3854 = and(_T_3852, _T_3853) @[el2_lsu_bus_buffer.scala 531:46] + node _T_3855 = or(_T_3850, _T_3854) @[el2_lsu_bus_buffer.scala 530:143] + node _T_3856 = and(bus_rsp_write_error, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 532:32] + node _T_3857 = eq(bus_rsp_write_tag, UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 532:74] + node _T_3858 = and(_T_3856, _T_3857) @[el2_lsu_bus_buffer.scala 532:53] + node _T_3859 = or(_T_3855, _T_3858) @[el2_lsu_bus_buffer.scala 531:88] + node _T_3860 = and(_T_3848, _T_3859) @[el2_lsu_bus_buffer.scala 530:68] + buf_error_en[1] <= _T_3860 @[el2_lsu_bus_buffer.scala 530:25] + node _T_3861 = eq(buf_error_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 533:50] + node _T_3862 = and(buf_state_en[1], _T_3861) @[el2_lsu_bus_buffer.scala 533:48] + node _T_3863 = bits(buf_addr[1], 2, 2) @[el2_lsu_bus_buffer.scala 533:84] + node _T_3864 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 533:102] + node _T_3865 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 533:125] + node _T_3866 = mux(_T_3863, _T_3864, _T_3865) @[el2_lsu_bus_buffer.scala 533:72] + node _T_3867 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 533:148] + node _T_3868 = mux(_T_3862, _T_3866, _T_3867) @[el2_lsu_bus_buffer.scala 533:30] + buf_data_in[1] <= _T_3868 @[el2_lsu_bus_buffer.scala 533:24] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_3869 = eq(UInt<3>("h04"), buf_state[1]) @[Conditional.scala 37:30] when _T_3869 : @[Conditional.scala 39:67] - node _T_3870 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 535:60] - node _T_3871 = bits(buf_ldfwd, 1, 1) @[el2_lsu_bus_buffer.scala 535:86] - node _T_3872 = dshr(buf_ldfwd, buf_dualtag[1]) @[el2_lsu_bus_buffer.scala 535:101] - node _T_3873 = bits(_T_3872, 0, 0) @[el2_lsu_bus_buffer.scala 535:101] - node _T_3874 = or(_T_3871, _T_3873) @[el2_lsu_bus_buffer.scala 535:90] - node _T_3875 = or(_T_3874, any_done_wait_state) @[el2_lsu_bus_buffer.scala 535:118] - node _T_3876 = mux(_T_3875, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 535:75] - node _T_3877 = mux(_T_3870, UInt<3>("h00"), _T_3876) @[el2_lsu_bus_buffer.scala 535:31] - buf_nxtstate[1] <= _T_3877 @[el2_lsu_bus_buffer.scala 535:25] - node _T_3878 = eq(bus_rsp_read_tag, buf_dualtag[1]) @[el2_lsu_bus_buffer.scala 536:66] - node _T_3879 = dshr(buf_ldfwd, buf_dualtag[1]) @[el2_lsu_bus_buffer.scala 537:21] - node _T_3880 = bits(_T_3879, 0, 0) @[el2_lsu_bus_buffer.scala 537:21] - node _T_3881 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[1]]) @[el2_lsu_bus_buffer.scala 537:58] - node _T_3882 = and(_T_3880, _T_3881) @[el2_lsu_bus_buffer.scala 537:38] - node _T_3883 = or(_T_3878, _T_3882) @[el2_lsu_bus_buffer.scala 536:95] - node _T_3884 = and(bus_rsp_read, _T_3883) @[el2_lsu_bus_buffer.scala 536:45] - buf_state_bus_en[1] <= _T_3884 @[el2_lsu_bus_buffer.scala 536:29] - node _T_3885 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 538:49] - node _T_3886 = or(_T_3885, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 538:70] - buf_state_en[1] <= _T_3886 @[el2_lsu_bus_buffer.scala 538:25] + node _T_3870 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 536:60] + node _T_3871 = bits(buf_ldfwd, 1, 1) @[el2_lsu_bus_buffer.scala 536:86] + node _T_3872 = dshr(buf_ldfwd, buf_dualtag[1]) @[el2_lsu_bus_buffer.scala 536:101] + node _T_3873 = bits(_T_3872, 0, 0) @[el2_lsu_bus_buffer.scala 536:101] + node _T_3874 = or(_T_3871, _T_3873) @[el2_lsu_bus_buffer.scala 536:90] + node _T_3875 = or(_T_3874, any_done_wait_state) @[el2_lsu_bus_buffer.scala 536:118] + node _T_3876 = mux(_T_3875, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 536:75] + node _T_3877 = mux(_T_3870, UInt<3>("h00"), _T_3876) @[el2_lsu_bus_buffer.scala 536:31] + buf_nxtstate[1] <= _T_3877 @[el2_lsu_bus_buffer.scala 536:25] + node _T_3878 = eq(bus_rsp_read_tag, buf_dualtag[1]) @[el2_lsu_bus_buffer.scala 537:66] + node _T_3879 = dshr(buf_ldfwd, buf_dualtag[1]) @[el2_lsu_bus_buffer.scala 538:21] + node _T_3880 = bits(_T_3879, 0, 0) @[el2_lsu_bus_buffer.scala 538:21] + node _T_3881 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[1]]) @[el2_lsu_bus_buffer.scala 538:58] + node _T_3882 = and(_T_3880, _T_3881) @[el2_lsu_bus_buffer.scala 538:38] + node _T_3883 = or(_T_3878, _T_3882) @[el2_lsu_bus_buffer.scala 537:95] + node _T_3884 = and(bus_rsp_read, _T_3883) @[el2_lsu_bus_buffer.scala 537:45] + buf_state_bus_en[1] <= _T_3884 @[el2_lsu_bus_buffer.scala 537:29] + node _T_3885 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 539:49] + node _T_3886 = or(_T_3885, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 539:70] + buf_state_en[1] <= _T_3886 @[el2_lsu_bus_buffer.scala 539:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_3887 = eq(UInt<3>("h05"), buf_state[1]) @[Conditional.scala 37:30] when _T_3887 : @[Conditional.scala 39:67] - node _T_3888 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 541:60] - node _T_3889 = mux(_T_3888, UInt<3>("h00"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 541:31] - buf_nxtstate[1] <= _T_3889 @[el2_lsu_bus_buffer.scala 541:25] - node _T_3890 = eq(RspPtr, UInt<2>("h01")) @[el2_lsu_bus_buffer.scala 542:37] - node _T_3891 = eq(buf_dualtag[1], RspPtr) @[el2_lsu_bus_buffer.scala 542:98] - node _T_3892 = and(buf_dual[1], _T_3891) @[el2_lsu_bus_buffer.scala 542:80] - node _T_3893 = or(_T_3890, _T_3892) @[el2_lsu_bus_buffer.scala 542:65] - node _T_3894 = or(_T_3893, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 542:112] - buf_state_en[1] <= _T_3894 @[el2_lsu_bus_buffer.scala 542:25] + node _T_3888 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 542:60] + node _T_3889 = mux(_T_3888, UInt<3>("h00"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 542:31] + buf_nxtstate[1] <= _T_3889 @[el2_lsu_bus_buffer.scala 542:25] + node _T_3890 = eq(RspPtr, UInt<2>("h01")) @[el2_lsu_bus_buffer.scala 543:37] + node _T_3891 = eq(buf_dualtag[1], RspPtr) @[el2_lsu_bus_buffer.scala 543:98] + node _T_3892 = and(buf_dual[1], _T_3891) @[el2_lsu_bus_buffer.scala 543:80] + node _T_3893 = or(_T_3890, _T_3892) @[el2_lsu_bus_buffer.scala 543:65] + node _T_3894 = or(_T_3893, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 543:112] + buf_state_en[1] <= _T_3894 @[el2_lsu_bus_buffer.scala 543:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_3895 = eq(UInt<3>("h06"), buf_state[1]) @[Conditional.scala 37:30] when _T_3895 : @[Conditional.scala 39:67] - buf_nxtstate[1] <= UInt<3>("h00") @[el2_lsu_bus_buffer.scala 545:25] - buf_rst[1] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 546:20] - buf_state_en[1] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 547:25] - buf_ldfwd_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 548:25] - buf_ldfwd_en[1] <= buf_state_en[1] @[el2_lsu_bus_buffer.scala 549:25] + buf_nxtstate[1] <= UInt<3>("h00") @[el2_lsu_bus_buffer.scala 546:25] + buf_rst[1] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 547:20] + buf_state_en[1] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 548:25] + buf_ldfwd_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 549:25] + buf_ldfwd_en[1] <= buf_state_en[1] @[el2_lsu_bus_buffer.scala 550:25] skip @[Conditional.scala 39:67] - node _T_3896 = bits(buf_state_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 552:108] + node _T_3896 = bits(buf_state_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 553:108] reg _T_3897 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_3896 : @[Reg.scala 28:19] _T_3897 <= buf_nxtstate[1] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_state[1] <= _T_3897 @[el2_lsu_bus_buffer.scala 552:18] - reg _T_3898 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 553:60] - _T_3898 <= buf_age_in_1 @[el2_lsu_bus_buffer.scala 553:60] - buf_ageQ[1] <= _T_3898 @[el2_lsu_bus_buffer.scala 553:17] - reg _T_3899 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 554:63] - _T_3899 <= buf_rspage_in[1] @[el2_lsu_bus_buffer.scala 554:63] - buf_rspageQ[1] <= _T_3899 @[el2_lsu_bus_buffer.scala 554:20] - node _T_3900 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 555:109] + buf_state[1] <= _T_3897 @[el2_lsu_bus_buffer.scala 553:18] + reg _T_3898 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 554:60] + _T_3898 <= buf_age_in_1 @[el2_lsu_bus_buffer.scala 554:60] + buf_ageQ[1] <= _T_3898 @[el2_lsu_bus_buffer.scala 554:17] + reg _T_3899 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 555:63] + _T_3899 <= buf_rspage_in[1] @[el2_lsu_bus_buffer.scala 555:63] + buf_rspageQ[1] <= _T_3899 @[el2_lsu_bus_buffer.scala 555:20] + node _T_3900 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 556:109] reg _T_3901 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_3900 : @[Reg.scala 28:19] _T_3901 <= buf_dualtag_in[1] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_dualtag[1] <= _T_3901 @[el2_lsu_bus_buffer.scala 555:20] - node _T_3902 = bits(buf_dual_in, 1, 1) @[el2_lsu_bus_buffer.scala 556:74] - node _T_3903 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 556:107] + buf_dualtag[1] <= _T_3901 @[el2_lsu_bus_buffer.scala 556:20] + node _T_3902 = bits(buf_dual_in, 1, 1) @[el2_lsu_bus_buffer.scala 557:74] + node _T_3903 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 557:107] reg _T_3904 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_3903 : @[Reg.scala 28:19] _T_3904 <= _T_3902 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_dual[1] <= _T_3904 @[el2_lsu_bus_buffer.scala 556:17] - node _T_3905 = bits(buf_samedw_in, 1, 1) @[el2_lsu_bus_buffer.scala 557:78] - node _T_3906 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 557:111] + buf_dual[1] <= _T_3904 @[el2_lsu_bus_buffer.scala 557:17] + node _T_3905 = bits(buf_samedw_in, 1, 1) @[el2_lsu_bus_buffer.scala 558:78] + node _T_3906 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 558:111] reg _T_3907 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_3906 : @[Reg.scala 28:19] _T_3907 <= _T_3905 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_samedw[1] <= _T_3907 @[el2_lsu_bus_buffer.scala 557:19] - node _T_3908 = bits(buf_nomerge_in, 1, 1) @[el2_lsu_bus_buffer.scala 558:80] - node _T_3909 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 558:113] + buf_samedw[1] <= _T_3907 @[el2_lsu_bus_buffer.scala 558:19] + node _T_3908 = bits(buf_nomerge_in, 1, 1) @[el2_lsu_bus_buffer.scala 559:80] + node _T_3909 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 559:113] reg _T_3910 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_3909 : @[Reg.scala 28:19] _T_3910 <= _T_3908 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_nomerge[1] <= _T_3910 @[el2_lsu_bus_buffer.scala 558:20] - node _T_3911 = bits(buf_dualhi_in, 1, 1) @[el2_lsu_bus_buffer.scala 559:78] - node _T_3912 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 559:111] + buf_nomerge[1] <= _T_3910 @[el2_lsu_bus_buffer.scala 559:20] + node _T_3911 = bits(buf_dualhi_in, 1, 1) @[el2_lsu_bus_buffer.scala 560:78] + node _T_3912 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 560:111] reg _T_3913 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_3912 : @[Reg.scala 28:19] _T_3913 <= _T_3911 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_dualhi[1] <= _T_3913 @[el2_lsu_bus_buffer.scala 559:19] + buf_dualhi[1] <= _T_3913 @[el2_lsu_bus_buffer.scala 560:19] node _T_3914 = eq(UInt<3>("h00"), buf_state[2]) @[Conditional.scala 37:30] when _T_3914 : @[Conditional.scala 40:58] - node _T_3915 = bits(io.lsu_bus_clk_en, 0, 0) @[el2_lsu_bus_buffer.scala 496:56] - node _T_3916 = mux(_T_3915, UInt<3>("h02"), UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 496:31] - buf_nxtstate[2] <= _T_3916 @[el2_lsu_bus_buffer.scala 496:25] - node _T_3917 = and(io.lsu_busreq_r, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 497:45] - node _T_3918 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 497:77] - node _T_3919 = eq(ibuf_merge_en, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 497:97] - node _T_3920 = and(_T_3918, _T_3919) @[el2_lsu_bus_buffer.scala 497:95] - node _T_3921 = eq(UInt<2>("h02"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 497:117] - node _T_3922 = and(_T_3920, _T_3921) @[el2_lsu_bus_buffer.scala 497:112] - node _T_3923 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 497:144] - node _T_3924 = eq(UInt<2>("h02"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 497:166] - node _T_3925 = and(_T_3923, _T_3924) @[el2_lsu_bus_buffer.scala 497:161] - node _T_3926 = or(_T_3922, _T_3925) @[el2_lsu_bus_buffer.scala 497:132] - node _T_3927 = and(_T_3917, _T_3926) @[el2_lsu_bus_buffer.scala 497:63] - node _T_3928 = eq(UInt<2>("h02"), ibuf_tag) @[el2_lsu_bus_buffer.scala 497:206] - node _T_3929 = and(ibuf_drain_vld, _T_3928) @[el2_lsu_bus_buffer.scala 497:201] - node _T_3930 = or(_T_3927, _T_3929) @[el2_lsu_bus_buffer.scala 497:183] - buf_state_en[2] <= _T_3930 @[el2_lsu_bus_buffer.scala 497:25] - buf_wr_en[2] <= buf_state_en[2] @[el2_lsu_bus_buffer.scala 498:22] - buf_data_en[2] <= buf_state_en[2] @[el2_lsu_bus_buffer.scala 499:24] - node _T_3931 = eq(UInt<2>("h02"), ibuf_tag) @[el2_lsu_bus_buffer.scala 500:52] - node _T_3932 = and(ibuf_drain_vld, _T_3931) @[el2_lsu_bus_buffer.scala 500:47] - node _T_3933 = bits(_T_3932, 0, 0) @[el2_lsu_bus_buffer.scala 500:73] - node _T_3934 = bits(ibuf_data_out, 31, 0) @[el2_lsu_bus_buffer.scala 500:90] - node _T_3935 = bits(store_data_lo_r, 31, 0) @[el2_lsu_bus_buffer.scala 500:114] - node _T_3936 = mux(_T_3933, _T_3934, _T_3935) @[el2_lsu_bus_buffer.scala 500:30] - buf_data_in[2] <= _T_3936 @[el2_lsu_bus_buffer.scala 500:24] + node _T_3915 = bits(io.lsu_bus_clk_en, 0, 0) @[el2_lsu_bus_buffer.scala 497:56] + node _T_3916 = mux(_T_3915, UInt<3>("h02"), UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 497:31] + buf_nxtstate[2] <= _T_3916 @[el2_lsu_bus_buffer.scala 497:25] + node _T_3917 = and(io.lsu_busreq_r, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 498:45] + node _T_3918 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 498:77] + node _T_3919 = eq(ibuf_merge_en, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 498:97] + node _T_3920 = and(_T_3918, _T_3919) @[el2_lsu_bus_buffer.scala 498:95] + node _T_3921 = eq(UInt<2>("h02"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 498:117] + node _T_3922 = and(_T_3920, _T_3921) @[el2_lsu_bus_buffer.scala 498:112] + node _T_3923 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 498:144] + node _T_3924 = eq(UInt<2>("h02"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 498:166] + node _T_3925 = and(_T_3923, _T_3924) @[el2_lsu_bus_buffer.scala 498:161] + node _T_3926 = or(_T_3922, _T_3925) @[el2_lsu_bus_buffer.scala 498:132] + node _T_3927 = and(_T_3917, _T_3926) @[el2_lsu_bus_buffer.scala 498:63] + node _T_3928 = eq(UInt<2>("h02"), ibuf_tag) @[el2_lsu_bus_buffer.scala 498:206] + node _T_3929 = and(ibuf_drain_vld, _T_3928) @[el2_lsu_bus_buffer.scala 498:201] + node _T_3930 = or(_T_3927, _T_3929) @[el2_lsu_bus_buffer.scala 498:183] + buf_state_en[2] <= _T_3930 @[el2_lsu_bus_buffer.scala 498:25] + buf_wr_en[2] <= buf_state_en[2] @[el2_lsu_bus_buffer.scala 499:22] + buf_data_en[2] <= buf_state_en[2] @[el2_lsu_bus_buffer.scala 500:24] + node _T_3931 = eq(UInt<2>("h02"), ibuf_tag) @[el2_lsu_bus_buffer.scala 501:52] + node _T_3932 = and(ibuf_drain_vld, _T_3931) @[el2_lsu_bus_buffer.scala 501:47] + node _T_3933 = bits(_T_3932, 0, 0) @[el2_lsu_bus_buffer.scala 501:73] + node _T_3934 = bits(ibuf_data_out, 31, 0) @[el2_lsu_bus_buffer.scala 501:90] + node _T_3935 = bits(store_data_lo_r, 31, 0) @[el2_lsu_bus_buffer.scala 501:114] + node _T_3936 = mux(_T_3933, _T_3934, _T_3935) @[el2_lsu_bus_buffer.scala 501:30] + buf_data_in[2] <= _T_3936 @[el2_lsu_bus_buffer.scala 501:24] skip @[Conditional.scala 40:58] else : @[Conditional.scala 39:67] node _T_3937 = eq(UInt<3>("h01"), buf_state[2]) @[Conditional.scala 37:30] when _T_3937 : @[Conditional.scala 39:67] - node _T_3938 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 503:60] - node _T_3939 = mux(_T_3938, UInt<3>("h00"), UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 503:31] - buf_nxtstate[2] <= _T_3939 @[el2_lsu_bus_buffer.scala 503:25] - node _T_3940 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 504:46] - buf_state_en[2] <= _T_3940 @[el2_lsu_bus_buffer.scala 504:25] + node _T_3938 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 504:60] + node _T_3939 = mux(_T_3938, UInt<3>("h00"), UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 504:31] + buf_nxtstate[2] <= _T_3939 @[el2_lsu_bus_buffer.scala 504:25] + node _T_3940 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 505:46] + buf_state_en[2] <= _T_3940 @[el2_lsu_bus_buffer.scala 505:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_3941 = eq(UInt<3>("h02"), buf_state[2]) @[Conditional.scala 37:30] when _T_3941 : @[Conditional.scala 39:67] - node _T_3942 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 507:60] - node _T_3943 = and(obuf_nosend, bus_rsp_read) @[el2_lsu_bus_buffer.scala 507:89] - node _T_3944 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[el2_lsu_bus_buffer.scala 507:124] - node _T_3945 = and(_T_3943, _T_3944) @[el2_lsu_bus_buffer.scala 507:104] - node _T_3946 = mux(_T_3945, UInt<3>("h05"), UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 507:75] - node _T_3947 = mux(_T_3942, UInt<3>("h00"), _T_3946) @[el2_lsu_bus_buffer.scala 507:31] - buf_nxtstate[2] <= _T_3947 @[el2_lsu_bus_buffer.scala 507:25] - node _T_3948 = eq(obuf_tag0, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 508:48] - node _T_3949 = eq(obuf_tag1, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 508:104] - node _T_3950 = and(obuf_merge, _T_3949) @[el2_lsu_bus_buffer.scala 508:91] - node _T_3951 = or(_T_3948, _T_3950) @[el2_lsu_bus_buffer.scala 508:77] - node _T_3952 = and(_T_3951, obuf_valid) @[el2_lsu_bus_buffer.scala 508:135] - node _T_3953 = and(_T_3952, obuf_wr_enQ) @[el2_lsu_bus_buffer.scala 508:148] - buf_cmd_state_bus_en[2] <= _T_3953 @[el2_lsu_bus_buffer.scala 508:33] - buf_state_bus_en[2] <= buf_cmd_state_bus_en[2] @[el2_lsu_bus_buffer.scala 509:29] - node _T_3954 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 510:49] - node _T_3955 = or(_T_3954, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 510:70] - buf_state_en[2] <= _T_3955 @[el2_lsu_bus_buffer.scala 510:25] - buf_ldfwd_in[2] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 511:25] - node _T_3956 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 512:56] - node _T_3957 = eq(_T_3956, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 512:46] - node _T_3958 = and(buf_state_en[2], _T_3957) @[el2_lsu_bus_buffer.scala 512:44] - node _T_3959 = and(_T_3958, obuf_nosend) @[el2_lsu_bus_buffer.scala 512:60] - node _T_3960 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 512:76] - node _T_3961 = and(_T_3959, _T_3960) @[el2_lsu_bus_buffer.scala 512:74] - buf_ldfwd_en[2] <= _T_3961 @[el2_lsu_bus_buffer.scala 512:25] - node _T_3962 = bits(obuf_rdrsp_tag, 1, 0) @[el2_lsu_bus_buffer.scala 513:46] - buf_ldfwdtag_in[2] <= _T_3962 @[el2_lsu_bus_buffer.scala 513:28] - node _T_3963 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 514:47] - node _T_3964 = and(_T_3963, obuf_nosend) @[el2_lsu_bus_buffer.scala 514:67] - node _T_3965 = and(_T_3964, bus_rsp_read) @[el2_lsu_bus_buffer.scala 514:81] - buf_data_en[2] <= _T_3965 @[el2_lsu_bus_buffer.scala 514:24] - node _T_3966 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 515:48] - node _T_3967 = and(_T_3966, obuf_nosend) @[el2_lsu_bus_buffer.scala 515:68] - node _T_3968 = and(_T_3967, bus_rsp_read_error) @[el2_lsu_bus_buffer.scala 515:82] - buf_error_en[2] <= _T_3968 @[el2_lsu_bus_buffer.scala 515:25] - node _T_3969 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 516:61] - node _T_3970 = bits(buf_addr[2], 2, 2) @[el2_lsu_bus_buffer.scala 516:85] - node _T_3971 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 516:103] - node _T_3972 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 516:126] - node _T_3973 = mux(_T_3970, _T_3971, _T_3972) @[el2_lsu_bus_buffer.scala 516:73] - node _T_3974 = mux(buf_error_en[2], _T_3969, _T_3973) @[el2_lsu_bus_buffer.scala 516:30] - buf_data_in[2] <= _T_3974 @[el2_lsu_bus_buffer.scala 516:24] + node _T_3942 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 508:60] + node _T_3943 = and(obuf_nosend, bus_rsp_read) @[el2_lsu_bus_buffer.scala 508:89] + node _T_3944 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[el2_lsu_bus_buffer.scala 508:124] + node _T_3945 = and(_T_3943, _T_3944) @[el2_lsu_bus_buffer.scala 508:104] + node _T_3946 = mux(_T_3945, UInt<3>("h05"), UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 508:75] + node _T_3947 = mux(_T_3942, UInt<3>("h00"), _T_3946) @[el2_lsu_bus_buffer.scala 508:31] + buf_nxtstate[2] <= _T_3947 @[el2_lsu_bus_buffer.scala 508:25] + node _T_3948 = eq(obuf_tag0, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 509:48] + node _T_3949 = eq(obuf_tag1, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 509:104] + node _T_3950 = and(obuf_merge, _T_3949) @[el2_lsu_bus_buffer.scala 509:91] + node _T_3951 = or(_T_3948, _T_3950) @[el2_lsu_bus_buffer.scala 509:77] + node _T_3952 = and(_T_3951, obuf_valid) @[el2_lsu_bus_buffer.scala 509:135] + node _T_3953 = and(_T_3952, obuf_wr_enQ) @[el2_lsu_bus_buffer.scala 509:148] + buf_cmd_state_bus_en[2] <= _T_3953 @[el2_lsu_bus_buffer.scala 509:33] + buf_state_bus_en[2] <= buf_cmd_state_bus_en[2] @[el2_lsu_bus_buffer.scala 510:29] + node _T_3954 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 511:49] + node _T_3955 = or(_T_3954, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 511:70] + buf_state_en[2] <= _T_3955 @[el2_lsu_bus_buffer.scala 511:25] + buf_ldfwd_in[2] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 512:25] + node _T_3956 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 513:56] + node _T_3957 = eq(_T_3956, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 513:46] + node _T_3958 = and(buf_state_en[2], _T_3957) @[el2_lsu_bus_buffer.scala 513:44] + node _T_3959 = and(_T_3958, obuf_nosend) @[el2_lsu_bus_buffer.scala 513:60] + node _T_3960 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 513:76] + node _T_3961 = and(_T_3959, _T_3960) @[el2_lsu_bus_buffer.scala 513:74] + buf_ldfwd_en[2] <= _T_3961 @[el2_lsu_bus_buffer.scala 513:25] + node _T_3962 = bits(obuf_rdrsp_tag, 1, 0) @[el2_lsu_bus_buffer.scala 514:46] + buf_ldfwdtag_in[2] <= _T_3962 @[el2_lsu_bus_buffer.scala 514:28] + node _T_3963 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 515:47] + node _T_3964 = and(_T_3963, obuf_nosend) @[el2_lsu_bus_buffer.scala 515:67] + node _T_3965 = and(_T_3964, bus_rsp_read) @[el2_lsu_bus_buffer.scala 515:81] + buf_data_en[2] <= _T_3965 @[el2_lsu_bus_buffer.scala 515:24] + node _T_3966 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 516:48] + node _T_3967 = and(_T_3966, obuf_nosend) @[el2_lsu_bus_buffer.scala 516:68] + node _T_3968 = and(_T_3967, bus_rsp_read_error) @[el2_lsu_bus_buffer.scala 516:82] + buf_error_en[2] <= _T_3968 @[el2_lsu_bus_buffer.scala 516:25] + node _T_3969 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 517:61] + node _T_3970 = bits(buf_addr[2], 2, 2) @[el2_lsu_bus_buffer.scala 517:85] + node _T_3971 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 517:103] + node _T_3972 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 517:126] + node _T_3973 = mux(_T_3970, _T_3971, _T_3972) @[el2_lsu_bus_buffer.scala 517:73] + node _T_3974 = mux(buf_error_en[2], _T_3969, _T_3973) @[el2_lsu_bus_buffer.scala 517:30] + buf_data_in[2] <= _T_3974 @[el2_lsu_bus_buffer.scala 517:24] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_3975 = eq(UInt<3>("h03"), buf_state[2]) @[Conditional.scala 37:30] when _T_3975 : @[Conditional.scala 39:67] - node _T_3976 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 519:67] - node _T_3977 = and(UInt<1>("h01"), bus_rsp_write_error) @[el2_lsu_bus_buffer.scala 519:94] - node _T_3978 = eq(_T_3977, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 519:73] - node _T_3979 = and(_T_3976, _T_3978) @[el2_lsu_bus_buffer.scala 519:71] - node _T_3980 = or(io.dec_tlu_force_halt, _T_3979) @[el2_lsu_bus_buffer.scala 519:55] - node _T_3981 = bits(_T_3980, 0, 0) @[el2_lsu_bus_buffer.scala 519:125] - node _T_3982 = eq(buf_samedw[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 520:30] - node _T_3983 = and(buf_dual[2], _T_3982) @[el2_lsu_bus_buffer.scala 520:28] - node _T_3984 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 520:57] - node _T_3985 = eq(_T_3984, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 520:47] - node _T_3986 = and(_T_3983, _T_3985) @[el2_lsu_bus_buffer.scala 520:45] - node _T_3987 = neq(buf_state[buf_dualtag[2]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 520:90] - node _T_3988 = and(_T_3986, _T_3987) @[el2_lsu_bus_buffer.scala 520:61] - node _T_3989 = bits(buf_ldfwd, 2, 2) @[el2_lsu_bus_buffer.scala 521:27] - node _T_3990 = or(_T_3989, any_done_wait_state) @[el2_lsu_bus_buffer.scala 521:31] - node _T_3991 = eq(buf_samedw[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 521:70] - node _T_3992 = and(buf_dual[2], _T_3991) @[el2_lsu_bus_buffer.scala 521:68] - node _T_3993 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 521:97] - node _T_3994 = eq(_T_3993, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 521:87] - node _T_3995 = and(_T_3992, _T_3994) @[el2_lsu_bus_buffer.scala 521:85] + node _T_3976 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 520:67] + node _T_3977 = and(UInt<1>("h01"), bus_rsp_write_error) @[el2_lsu_bus_buffer.scala 520:94] + node _T_3978 = eq(_T_3977, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 520:73] + node _T_3979 = and(_T_3976, _T_3978) @[el2_lsu_bus_buffer.scala 520:71] + node _T_3980 = or(io.dec_tlu_force_halt, _T_3979) @[el2_lsu_bus_buffer.scala 520:55] + node _T_3981 = bits(_T_3980, 0, 0) @[el2_lsu_bus_buffer.scala 520:125] + node _T_3982 = eq(buf_samedw[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 521:30] + node _T_3983 = and(buf_dual[2], _T_3982) @[el2_lsu_bus_buffer.scala 521:28] + node _T_3984 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 521:57] + node _T_3985 = eq(_T_3984, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 521:47] + node _T_3986 = and(_T_3983, _T_3985) @[el2_lsu_bus_buffer.scala 521:45] + node _T_3987 = neq(buf_state[buf_dualtag[2]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 521:90] + node _T_3988 = and(_T_3986, _T_3987) @[el2_lsu_bus_buffer.scala 521:61] + node _T_3989 = bits(buf_ldfwd, 2, 2) @[el2_lsu_bus_buffer.scala 522:27] + node _T_3990 = or(_T_3989, any_done_wait_state) @[el2_lsu_bus_buffer.scala 522:31] + node _T_3991 = eq(buf_samedw[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 522:70] + node _T_3992 = and(buf_dual[2], _T_3991) @[el2_lsu_bus_buffer.scala 522:68] + node _T_3993 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 522:97] + node _T_3994 = eq(_T_3993, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 522:87] + node _T_3995 = and(_T_3992, _T_3994) @[el2_lsu_bus_buffer.scala 522:85] node _T_3996 = eq(buf_dualtag[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] node _T_3997 = bits(buf_ldfwd, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] node _T_3998 = eq(buf_dualtag[2], UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] @@ -5125,265 +5123,265 @@ circuit el2_lsu_bus_intf : node _T_4010 = or(_T_4009, _T_4007) @[Mux.scala 27:72] wire _T_4011 : UInt<1> @[Mux.scala 27:72] _T_4011 <= _T_4010 @[Mux.scala 27:72] - node _T_4012 = and(_T_3995, _T_4011) @[el2_lsu_bus_buffer.scala 521:101] - node _T_4013 = eq(buf_state[buf_dualtag[2]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 521:167] - node _T_4014 = and(_T_4012, _T_4013) @[el2_lsu_bus_buffer.scala 521:138] - node _T_4015 = and(_T_4014, any_done_wait_state) @[el2_lsu_bus_buffer.scala 521:187] - node _T_4016 = or(_T_3990, _T_4015) @[el2_lsu_bus_buffer.scala 521:53] - node _T_4017 = mux(_T_4016, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 521:16] - node _T_4018 = mux(_T_3988, UInt<3>("h04"), _T_4017) @[el2_lsu_bus_buffer.scala 520:14] - node _T_4019 = mux(_T_3981, UInt<3>("h00"), _T_4018) @[el2_lsu_bus_buffer.scala 519:31] - buf_nxtstate[2] <= _T_4019 @[el2_lsu_bus_buffer.scala 519:25] - node _T_4020 = eq(bus_rsp_write_tag, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 522:73] - node _T_4021 = and(bus_rsp_write, _T_4020) @[el2_lsu_bus_buffer.scala 522:52] - node _T_4022 = eq(bus_rsp_read_tag, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 523:46] - node _T_4023 = bits(buf_ldfwd, 2, 2) @[el2_lsu_bus_buffer.scala 524:23] - node _T_4024 = eq(bus_rsp_read_tag, buf_ldfwdtag[2]) @[el2_lsu_bus_buffer.scala 524:47] - node _T_4025 = and(_T_4023, _T_4024) @[el2_lsu_bus_buffer.scala 524:27] - node _T_4026 = or(_T_4022, _T_4025) @[el2_lsu_bus_buffer.scala 523:77] - node _T_4027 = and(buf_dual[2], buf_dualhi[2]) @[el2_lsu_bus_buffer.scala 525:26] - node _T_4028 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 525:54] - node _T_4029 = not(_T_4028) @[el2_lsu_bus_buffer.scala 525:44] - node _T_4030 = and(_T_4027, _T_4029) @[el2_lsu_bus_buffer.scala 525:42] - node _T_4031 = and(_T_4030, buf_samedw[2]) @[el2_lsu_bus_buffer.scala 525:58] - node _T_4032 = eq(bus_rsp_read_tag, buf_dualtag[2]) @[el2_lsu_bus_buffer.scala 525:94] - node _T_4033 = and(_T_4031, _T_4032) @[el2_lsu_bus_buffer.scala 525:74] - node _T_4034 = or(_T_4026, _T_4033) @[el2_lsu_bus_buffer.scala 524:71] - node _T_4035 = and(bus_rsp_read, _T_4034) @[el2_lsu_bus_buffer.scala 523:25] - node _T_4036 = or(_T_4021, _T_4035) @[el2_lsu_bus_buffer.scala 522:105] - buf_resp_state_bus_en[2] <= _T_4036 @[el2_lsu_bus_buffer.scala 522:34] - buf_state_bus_en[2] <= buf_resp_state_bus_en[2] @[el2_lsu_bus_buffer.scala 526:29] - node _T_4037 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 527:49] - node _T_4038 = or(_T_4037, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 527:70] - buf_state_en[2] <= _T_4038 @[el2_lsu_bus_buffer.scala 527:25] - node _T_4039 = and(buf_state_bus_en[2], bus_rsp_read) @[el2_lsu_bus_buffer.scala 528:47] - node _T_4040 = and(_T_4039, io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 528:62] - buf_data_en[2] <= _T_4040 @[el2_lsu_bus_buffer.scala 528:24] - node _T_4041 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 529:48] - node _T_4042 = eq(bus_rsp_read_tag, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 529:111] - node _T_4043 = and(bus_rsp_read_error, _T_4042) @[el2_lsu_bus_buffer.scala 529:91] - node _T_4044 = bits(buf_ldfwd, 2, 2) @[el2_lsu_bus_buffer.scala 530:42] - node _T_4045 = and(bus_rsp_read_error, _T_4044) @[el2_lsu_bus_buffer.scala 530:31] - node _T_4046 = eq(bus_rsp_read_tag, buf_ldfwdtag[2]) @[el2_lsu_bus_buffer.scala 530:66] - node _T_4047 = and(_T_4045, _T_4046) @[el2_lsu_bus_buffer.scala 530:46] - node _T_4048 = or(_T_4043, _T_4047) @[el2_lsu_bus_buffer.scala 529:143] - node _T_4049 = and(bus_rsp_write_error, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 531:32] - node _T_4050 = eq(bus_rsp_write_tag, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 531:74] - node _T_4051 = and(_T_4049, _T_4050) @[el2_lsu_bus_buffer.scala 531:53] - node _T_4052 = or(_T_4048, _T_4051) @[el2_lsu_bus_buffer.scala 530:88] - node _T_4053 = and(_T_4041, _T_4052) @[el2_lsu_bus_buffer.scala 529:68] - buf_error_en[2] <= _T_4053 @[el2_lsu_bus_buffer.scala 529:25] - node _T_4054 = eq(buf_error_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 532:50] - node _T_4055 = and(buf_state_en[2], _T_4054) @[el2_lsu_bus_buffer.scala 532:48] - node _T_4056 = bits(buf_addr[2], 2, 2) @[el2_lsu_bus_buffer.scala 532:84] - node _T_4057 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 532:102] - node _T_4058 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 532:125] - node _T_4059 = mux(_T_4056, _T_4057, _T_4058) @[el2_lsu_bus_buffer.scala 532:72] - node _T_4060 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 532:148] - node _T_4061 = mux(_T_4055, _T_4059, _T_4060) @[el2_lsu_bus_buffer.scala 532:30] - buf_data_in[2] <= _T_4061 @[el2_lsu_bus_buffer.scala 532:24] + node _T_4012 = and(_T_3995, _T_4011) @[el2_lsu_bus_buffer.scala 522:101] + node _T_4013 = eq(buf_state[buf_dualtag[2]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 522:167] + node _T_4014 = and(_T_4012, _T_4013) @[el2_lsu_bus_buffer.scala 522:138] + node _T_4015 = and(_T_4014, any_done_wait_state) @[el2_lsu_bus_buffer.scala 522:187] + node _T_4016 = or(_T_3990, _T_4015) @[el2_lsu_bus_buffer.scala 522:53] + node _T_4017 = mux(_T_4016, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 522:16] + node _T_4018 = mux(_T_3988, UInt<3>("h04"), _T_4017) @[el2_lsu_bus_buffer.scala 521:14] + node _T_4019 = mux(_T_3981, UInt<3>("h00"), _T_4018) @[el2_lsu_bus_buffer.scala 520:31] + buf_nxtstate[2] <= _T_4019 @[el2_lsu_bus_buffer.scala 520:25] + node _T_4020 = eq(bus_rsp_write_tag, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 523:73] + node _T_4021 = and(bus_rsp_write, _T_4020) @[el2_lsu_bus_buffer.scala 523:52] + node _T_4022 = eq(bus_rsp_read_tag, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 524:46] + node _T_4023 = bits(buf_ldfwd, 2, 2) @[el2_lsu_bus_buffer.scala 525:23] + node _T_4024 = eq(bus_rsp_read_tag, buf_ldfwdtag[2]) @[el2_lsu_bus_buffer.scala 525:47] + node _T_4025 = and(_T_4023, _T_4024) @[el2_lsu_bus_buffer.scala 525:27] + node _T_4026 = or(_T_4022, _T_4025) @[el2_lsu_bus_buffer.scala 524:77] + node _T_4027 = and(buf_dual[2], buf_dualhi[2]) @[el2_lsu_bus_buffer.scala 526:26] + node _T_4028 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 526:54] + node _T_4029 = not(_T_4028) @[el2_lsu_bus_buffer.scala 526:44] + node _T_4030 = and(_T_4027, _T_4029) @[el2_lsu_bus_buffer.scala 526:42] + node _T_4031 = and(_T_4030, buf_samedw[2]) @[el2_lsu_bus_buffer.scala 526:58] + node _T_4032 = eq(bus_rsp_read_tag, buf_dualtag[2]) @[el2_lsu_bus_buffer.scala 526:94] + node _T_4033 = and(_T_4031, _T_4032) @[el2_lsu_bus_buffer.scala 526:74] + node _T_4034 = or(_T_4026, _T_4033) @[el2_lsu_bus_buffer.scala 525:71] + node _T_4035 = and(bus_rsp_read, _T_4034) @[el2_lsu_bus_buffer.scala 524:25] + node _T_4036 = or(_T_4021, _T_4035) @[el2_lsu_bus_buffer.scala 523:105] + buf_resp_state_bus_en[2] <= _T_4036 @[el2_lsu_bus_buffer.scala 523:34] + buf_state_bus_en[2] <= buf_resp_state_bus_en[2] @[el2_lsu_bus_buffer.scala 527:29] + node _T_4037 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 528:49] + node _T_4038 = or(_T_4037, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 528:70] + buf_state_en[2] <= _T_4038 @[el2_lsu_bus_buffer.scala 528:25] + node _T_4039 = and(buf_state_bus_en[2], bus_rsp_read) @[el2_lsu_bus_buffer.scala 529:47] + node _T_4040 = and(_T_4039, io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 529:62] + buf_data_en[2] <= _T_4040 @[el2_lsu_bus_buffer.scala 529:24] + node _T_4041 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 530:48] + node _T_4042 = eq(bus_rsp_read_tag, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 530:111] + node _T_4043 = and(bus_rsp_read_error, _T_4042) @[el2_lsu_bus_buffer.scala 530:91] + node _T_4044 = bits(buf_ldfwd, 2, 2) @[el2_lsu_bus_buffer.scala 531:42] + node _T_4045 = and(bus_rsp_read_error, _T_4044) @[el2_lsu_bus_buffer.scala 531:31] + node _T_4046 = eq(bus_rsp_read_tag, buf_ldfwdtag[2]) @[el2_lsu_bus_buffer.scala 531:66] + node _T_4047 = and(_T_4045, _T_4046) @[el2_lsu_bus_buffer.scala 531:46] + node _T_4048 = or(_T_4043, _T_4047) @[el2_lsu_bus_buffer.scala 530:143] + node _T_4049 = and(bus_rsp_write_error, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 532:32] + node _T_4050 = eq(bus_rsp_write_tag, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 532:74] + node _T_4051 = and(_T_4049, _T_4050) @[el2_lsu_bus_buffer.scala 532:53] + node _T_4052 = or(_T_4048, _T_4051) @[el2_lsu_bus_buffer.scala 531:88] + node _T_4053 = and(_T_4041, _T_4052) @[el2_lsu_bus_buffer.scala 530:68] + buf_error_en[2] <= _T_4053 @[el2_lsu_bus_buffer.scala 530:25] + node _T_4054 = eq(buf_error_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 533:50] + node _T_4055 = and(buf_state_en[2], _T_4054) @[el2_lsu_bus_buffer.scala 533:48] + node _T_4056 = bits(buf_addr[2], 2, 2) @[el2_lsu_bus_buffer.scala 533:84] + node _T_4057 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 533:102] + node _T_4058 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 533:125] + node _T_4059 = mux(_T_4056, _T_4057, _T_4058) @[el2_lsu_bus_buffer.scala 533:72] + node _T_4060 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 533:148] + node _T_4061 = mux(_T_4055, _T_4059, _T_4060) @[el2_lsu_bus_buffer.scala 533:30] + buf_data_in[2] <= _T_4061 @[el2_lsu_bus_buffer.scala 533:24] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_4062 = eq(UInt<3>("h04"), buf_state[2]) @[Conditional.scala 37:30] when _T_4062 : @[Conditional.scala 39:67] - node _T_4063 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 535:60] - node _T_4064 = bits(buf_ldfwd, 2, 2) @[el2_lsu_bus_buffer.scala 535:86] - node _T_4065 = dshr(buf_ldfwd, buf_dualtag[2]) @[el2_lsu_bus_buffer.scala 535:101] - node _T_4066 = bits(_T_4065, 0, 0) @[el2_lsu_bus_buffer.scala 535:101] - node _T_4067 = or(_T_4064, _T_4066) @[el2_lsu_bus_buffer.scala 535:90] - node _T_4068 = or(_T_4067, any_done_wait_state) @[el2_lsu_bus_buffer.scala 535:118] - node _T_4069 = mux(_T_4068, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 535:75] - node _T_4070 = mux(_T_4063, UInt<3>("h00"), _T_4069) @[el2_lsu_bus_buffer.scala 535:31] - buf_nxtstate[2] <= _T_4070 @[el2_lsu_bus_buffer.scala 535:25] - node _T_4071 = eq(bus_rsp_read_tag, buf_dualtag[2]) @[el2_lsu_bus_buffer.scala 536:66] - node _T_4072 = dshr(buf_ldfwd, buf_dualtag[2]) @[el2_lsu_bus_buffer.scala 537:21] - node _T_4073 = bits(_T_4072, 0, 0) @[el2_lsu_bus_buffer.scala 537:21] - node _T_4074 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[2]]) @[el2_lsu_bus_buffer.scala 537:58] - node _T_4075 = and(_T_4073, _T_4074) @[el2_lsu_bus_buffer.scala 537:38] - node _T_4076 = or(_T_4071, _T_4075) @[el2_lsu_bus_buffer.scala 536:95] - node _T_4077 = and(bus_rsp_read, _T_4076) @[el2_lsu_bus_buffer.scala 536:45] - buf_state_bus_en[2] <= _T_4077 @[el2_lsu_bus_buffer.scala 536:29] - node _T_4078 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 538:49] - node _T_4079 = or(_T_4078, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 538:70] - buf_state_en[2] <= _T_4079 @[el2_lsu_bus_buffer.scala 538:25] + node _T_4063 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 536:60] + node _T_4064 = bits(buf_ldfwd, 2, 2) @[el2_lsu_bus_buffer.scala 536:86] + node _T_4065 = dshr(buf_ldfwd, buf_dualtag[2]) @[el2_lsu_bus_buffer.scala 536:101] + node _T_4066 = bits(_T_4065, 0, 0) @[el2_lsu_bus_buffer.scala 536:101] + node _T_4067 = or(_T_4064, _T_4066) @[el2_lsu_bus_buffer.scala 536:90] + node _T_4068 = or(_T_4067, any_done_wait_state) @[el2_lsu_bus_buffer.scala 536:118] + node _T_4069 = mux(_T_4068, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 536:75] + node _T_4070 = mux(_T_4063, UInt<3>("h00"), _T_4069) @[el2_lsu_bus_buffer.scala 536:31] + buf_nxtstate[2] <= _T_4070 @[el2_lsu_bus_buffer.scala 536:25] + node _T_4071 = eq(bus_rsp_read_tag, buf_dualtag[2]) @[el2_lsu_bus_buffer.scala 537:66] + node _T_4072 = dshr(buf_ldfwd, buf_dualtag[2]) @[el2_lsu_bus_buffer.scala 538:21] + node _T_4073 = bits(_T_4072, 0, 0) @[el2_lsu_bus_buffer.scala 538:21] + node _T_4074 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[2]]) @[el2_lsu_bus_buffer.scala 538:58] + node _T_4075 = and(_T_4073, _T_4074) @[el2_lsu_bus_buffer.scala 538:38] + node _T_4076 = or(_T_4071, _T_4075) @[el2_lsu_bus_buffer.scala 537:95] + node _T_4077 = and(bus_rsp_read, _T_4076) @[el2_lsu_bus_buffer.scala 537:45] + buf_state_bus_en[2] <= _T_4077 @[el2_lsu_bus_buffer.scala 537:29] + node _T_4078 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 539:49] + node _T_4079 = or(_T_4078, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 539:70] + buf_state_en[2] <= _T_4079 @[el2_lsu_bus_buffer.scala 539:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_4080 = eq(UInt<3>("h05"), buf_state[2]) @[Conditional.scala 37:30] when _T_4080 : @[Conditional.scala 39:67] - node _T_4081 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 541:60] - node _T_4082 = mux(_T_4081, UInt<3>("h00"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 541:31] - buf_nxtstate[2] <= _T_4082 @[el2_lsu_bus_buffer.scala 541:25] - node _T_4083 = eq(RspPtr, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 542:37] - node _T_4084 = eq(buf_dualtag[2], RspPtr) @[el2_lsu_bus_buffer.scala 542:98] - node _T_4085 = and(buf_dual[2], _T_4084) @[el2_lsu_bus_buffer.scala 542:80] - node _T_4086 = or(_T_4083, _T_4085) @[el2_lsu_bus_buffer.scala 542:65] - node _T_4087 = or(_T_4086, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 542:112] - buf_state_en[2] <= _T_4087 @[el2_lsu_bus_buffer.scala 542:25] + node _T_4081 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 542:60] + node _T_4082 = mux(_T_4081, UInt<3>("h00"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 542:31] + buf_nxtstate[2] <= _T_4082 @[el2_lsu_bus_buffer.scala 542:25] + node _T_4083 = eq(RspPtr, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 543:37] + node _T_4084 = eq(buf_dualtag[2], RspPtr) @[el2_lsu_bus_buffer.scala 543:98] + node _T_4085 = and(buf_dual[2], _T_4084) @[el2_lsu_bus_buffer.scala 543:80] + node _T_4086 = or(_T_4083, _T_4085) @[el2_lsu_bus_buffer.scala 543:65] + node _T_4087 = or(_T_4086, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 543:112] + buf_state_en[2] <= _T_4087 @[el2_lsu_bus_buffer.scala 543:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_4088 = eq(UInt<3>("h06"), buf_state[2]) @[Conditional.scala 37:30] when _T_4088 : @[Conditional.scala 39:67] - buf_nxtstate[2] <= UInt<3>("h00") @[el2_lsu_bus_buffer.scala 545:25] - buf_rst[2] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 546:20] - buf_state_en[2] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 547:25] - buf_ldfwd_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 548:25] - buf_ldfwd_en[2] <= buf_state_en[2] @[el2_lsu_bus_buffer.scala 549:25] + buf_nxtstate[2] <= UInt<3>("h00") @[el2_lsu_bus_buffer.scala 546:25] + buf_rst[2] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 547:20] + buf_state_en[2] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 548:25] + buf_ldfwd_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 549:25] + buf_ldfwd_en[2] <= buf_state_en[2] @[el2_lsu_bus_buffer.scala 550:25] skip @[Conditional.scala 39:67] - node _T_4089 = bits(buf_state_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 552:108] + node _T_4089 = bits(buf_state_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 553:108] reg _T_4090 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4089 : @[Reg.scala 28:19] _T_4090 <= buf_nxtstate[2] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_state[2] <= _T_4090 @[el2_lsu_bus_buffer.scala 552:18] - reg _T_4091 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 553:60] - _T_4091 <= buf_age_in_2 @[el2_lsu_bus_buffer.scala 553:60] - buf_ageQ[2] <= _T_4091 @[el2_lsu_bus_buffer.scala 553:17] - reg _T_4092 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 554:63] - _T_4092 <= buf_rspage_in[2] @[el2_lsu_bus_buffer.scala 554:63] - buf_rspageQ[2] <= _T_4092 @[el2_lsu_bus_buffer.scala 554:20] - node _T_4093 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 555:109] + buf_state[2] <= _T_4090 @[el2_lsu_bus_buffer.scala 553:18] + reg _T_4091 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 554:60] + _T_4091 <= buf_age_in_2 @[el2_lsu_bus_buffer.scala 554:60] + buf_ageQ[2] <= _T_4091 @[el2_lsu_bus_buffer.scala 554:17] + reg _T_4092 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 555:63] + _T_4092 <= buf_rspage_in[2] @[el2_lsu_bus_buffer.scala 555:63] + buf_rspageQ[2] <= _T_4092 @[el2_lsu_bus_buffer.scala 555:20] + node _T_4093 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 556:109] reg _T_4094 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4093 : @[Reg.scala 28:19] _T_4094 <= buf_dualtag_in[2] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_dualtag[2] <= _T_4094 @[el2_lsu_bus_buffer.scala 555:20] - node _T_4095 = bits(buf_dual_in, 2, 2) @[el2_lsu_bus_buffer.scala 556:74] - node _T_4096 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 556:107] + buf_dualtag[2] <= _T_4094 @[el2_lsu_bus_buffer.scala 556:20] + node _T_4095 = bits(buf_dual_in, 2, 2) @[el2_lsu_bus_buffer.scala 557:74] + node _T_4096 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 557:107] reg _T_4097 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4096 : @[Reg.scala 28:19] _T_4097 <= _T_4095 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_dual[2] <= _T_4097 @[el2_lsu_bus_buffer.scala 556:17] - node _T_4098 = bits(buf_samedw_in, 2, 2) @[el2_lsu_bus_buffer.scala 557:78] - node _T_4099 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 557:111] + buf_dual[2] <= _T_4097 @[el2_lsu_bus_buffer.scala 557:17] + node _T_4098 = bits(buf_samedw_in, 2, 2) @[el2_lsu_bus_buffer.scala 558:78] + node _T_4099 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 558:111] reg _T_4100 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4099 : @[Reg.scala 28:19] _T_4100 <= _T_4098 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_samedw[2] <= _T_4100 @[el2_lsu_bus_buffer.scala 557:19] - node _T_4101 = bits(buf_nomerge_in, 2, 2) @[el2_lsu_bus_buffer.scala 558:80] - node _T_4102 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 558:113] + buf_samedw[2] <= _T_4100 @[el2_lsu_bus_buffer.scala 558:19] + node _T_4101 = bits(buf_nomerge_in, 2, 2) @[el2_lsu_bus_buffer.scala 559:80] + node _T_4102 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 559:113] reg _T_4103 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4102 : @[Reg.scala 28:19] _T_4103 <= _T_4101 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_nomerge[2] <= _T_4103 @[el2_lsu_bus_buffer.scala 558:20] - node _T_4104 = bits(buf_dualhi_in, 2, 2) @[el2_lsu_bus_buffer.scala 559:78] - node _T_4105 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 559:111] + buf_nomerge[2] <= _T_4103 @[el2_lsu_bus_buffer.scala 559:20] + node _T_4104 = bits(buf_dualhi_in, 2, 2) @[el2_lsu_bus_buffer.scala 560:78] + node _T_4105 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 560:111] reg _T_4106 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4105 : @[Reg.scala 28:19] _T_4106 <= _T_4104 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_dualhi[2] <= _T_4106 @[el2_lsu_bus_buffer.scala 559:19] + buf_dualhi[2] <= _T_4106 @[el2_lsu_bus_buffer.scala 560:19] node _T_4107 = eq(UInt<3>("h00"), buf_state[3]) @[Conditional.scala 37:30] when _T_4107 : @[Conditional.scala 40:58] - node _T_4108 = bits(io.lsu_bus_clk_en, 0, 0) @[el2_lsu_bus_buffer.scala 496:56] - node _T_4109 = mux(_T_4108, UInt<3>("h02"), UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 496:31] - buf_nxtstate[3] <= _T_4109 @[el2_lsu_bus_buffer.scala 496:25] - node _T_4110 = and(io.lsu_busreq_r, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 497:45] - node _T_4111 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 497:77] - node _T_4112 = eq(ibuf_merge_en, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 497:97] - node _T_4113 = and(_T_4111, _T_4112) @[el2_lsu_bus_buffer.scala 497:95] - node _T_4114 = eq(UInt<2>("h03"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 497:117] - node _T_4115 = and(_T_4113, _T_4114) @[el2_lsu_bus_buffer.scala 497:112] - node _T_4116 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 497:144] - node _T_4117 = eq(UInt<2>("h03"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 497:166] - node _T_4118 = and(_T_4116, _T_4117) @[el2_lsu_bus_buffer.scala 497:161] - node _T_4119 = or(_T_4115, _T_4118) @[el2_lsu_bus_buffer.scala 497:132] - node _T_4120 = and(_T_4110, _T_4119) @[el2_lsu_bus_buffer.scala 497:63] - node _T_4121 = eq(UInt<2>("h03"), ibuf_tag) @[el2_lsu_bus_buffer.scala 497:206] - node _T_4122 = and(ibuf_drain_vld, _T_4121) @[el2_lsu_bus_buffer.scala 497:201] - node _T_4123 = or(_T_4120, _T_4122) @[el2_lsu_bus_buffer.scala 497:183] - buf_state_en[3] <= _T_4123 @[el2_lsu_bus_buffer.scala 497:25] - buf_wr_en[3] <= buf_state_en[3] @[el2_lsu_bus_buffer.scala 498:22] - buf_data_en[3] <= buf_state_en[3] @[el2_lsu_bus_buffer.scala 499:24] - node _T_4124 = eq(UInt<2>("h03"), ibuf_tag) @[el2_lsu_bus_buffer.scala 500:52] - node _T_4125 = and(ibuf_drain_vld, _T_4124) @[el2_lsu_bus_buffer.scala 500:47] - node _T_4126 = bits(_T_4125, 0, 0) @[el2_lsu_bus_buffer.scala 500:73] - node _T_4127 = bits(ibuf_data_out, 31, 0) @[el2_lsu_bus_buffer.scala 500:90] - node _T_4128 = bits(store_data_lo_r, 31, 0) @[el2_lsu_bus_buffer.scala 500:114] - node _T_4129 = mux(_T_4126, _T_4127, _T_4128) @[el2_lsu_bus_buffer.scala 500:30] - buf_data_in[3] <= _T_4129 @[el2_lsu_bus_buffer.scala 500:24] + node _T_4108 = bits(io.lsu_bus_clk_en, 0, 0) @[el2_lsu_bus_buffer.scala 497:56] + node _T_4109 = mux(_T_4108, UInt<3>("h02"), UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 497:31] + buf_nxtstate[3] <= _T_4109 @[el2_lsu_bus_buffer.scala 497:25] + node _T_4110 = and(io.lsu_busreq_r, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 498:45] + node _T_4111 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 498:77] + node _T_4112 = eq(ibuf_merge_en, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 498:97] + node _T_4113 = and(_T_4111, _T_4112) @[el2_lsu_bus_buffer.scala 498:95] + node _T_4114 = eq(UInt<2>("h03"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 498:117] + node _T_4115 = and(_T_4113, _T_4114) @[el2_lsu_bus_buffer.scala 498:112] + node _T_4116 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 498:144] + node _T_4117 = eq(UInt<2>("h03"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 498:166] + node _T_4118 = and(_T_4116, _T_4117) @[el2_lsu_bus_buffer.scala 498:161] + node _T_4119 = or(_T_4115, _T_4118) @[el2_lsu_bus_buffer.scala 498:132] + node _T_4120 = and(_T_4110, _T_4119) @[el2_lsu_bus_buffer.scala 498:63] + node _T_4121 = eq(UInt<2>("h03"), ibuf_tag) @[el2_lsu_bus_buffer.scala 498:206] + node _T_4122 = and(ibuf_drain_vld, _T_4121) @[el2_lsu_bus_buffer.scala 498:201] + node _T_4123 = or(_T_4120, _T_4122) @[el2_lsu_bus_buffer.scala 498:183] + buf_state_en[3] <= _T_4123 @[el2_lsu_bus_buffer.scala 498:25] + buf_wr_en[3] <= buf_state_en[3] @[el2_lsu_bus_buffer.scala 499:22] + buf_data_en[3] <= buf_state_en[3] @[el2_lsu_bus_buffer.scala 500:24] + node _T_4124 = eq(UInt<2>("h03"), ibuf_tag) @[el2_lsu_bus_buffer.scala 501:52] + node _T_4125 = and(ibuf_drain_vld, _T_4124) @[el2_lsu_bus_buffer.scala 501:47] + node _T_4126 = bits(_T_4125, 0, 0) @[el2_lsu_bus_buffer.scala 501:73] + node _T_4127 = bits(ibuf_data_out, 31, 0) @[el2_lsu_bus_buffer.scala 501:90] + node _T_4128 = bits(store_data_lo_r, 31, 0) @[el2_lsu_bus_buffer.scala 501:114] + node _T_4129 = mux(_T_4126, _T_4127, _T_4128) @[el2_lsu_bus_buffer.scala 501:30] + buf_data_in[3] <= _T_4129 @[el2_lsu_bus_buffer.scala 501:24] skip @[Conditional.scala 40:58] else : @[Conditional.scala 39:67] node _T_4130 = eq(UInt<3>("h01"), buf_state[3]) @[Conditional.scala 37:30] when _T_4130 : @[Conditional.scala 39:67] - node _T_4131 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 503:60] - node _T_4132 = mux(_T_4131, UInt<3>("h00"), UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 503:31] - buf_nxtstate[3] <= _T_4132 @[el2_lsu_bus_buffer.scala 503:25] - node _T_4133 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 504:46] - buf_state_en[3] <= _T_4133 @[el2_lsu_bus_buffer.scala 504:25] + node _T_4131 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 504:60] + node _T_4132 = mux(_T_4131, UInt<3>("h00"), UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 504:31] + buf_nxtstate[3] <= _T_4132 @[el2_lsu_bus_buffer.scala 504:25] + node _T_4133 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 505:46] + buf_state_en[3] <= _T_4133 @[el2_lsu_bus_buffer.scala 505:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_4134 = eq(UInt<3>("h02"), buf_state[3]) @[Conditional.scala 37:30] when _T_4134 : @[Conditional.scala 39:67] - node _T_4135 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 507:60] - node _T_4136 = and(obuf_nosend, bus_rsp_read) @[el2_lsu_bus_buffer.scala 507:89] - node _T_4137 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[el2_lsu_bus_buffer.scala 507:124] - node _T_4138 = and(_T_4136, _T_4137) @[el2_lsu_bus_buffer.scala 507:104] - node _T_4139 = mux(_T_4138, UInt<3>("h05"), UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 507:75] - node _T_4140 = mux(_T_4135, UInt<3>("h00"), _T_4139) @[el2_lsu_bus_buffer.scala 507:31] - buf_nxtstate[3] <= _T_4140 @[el2_lsu_bus_buffer.scala 507:25] - node _T_4141 = eq(obuf_tag0, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 508:48] - node _T_4142 = eq(obuf_tag1, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 508:104] - node _T_4143 = and(obuf_merge, _T_4142) @[el2_lsu_bus_buffer.scala 508:91] - node _T_4144 = or(_T_4141, _T_4143) @[el2_lsu_bus_buffer.scala 508:77] - node _T_4145 = and(_T_4144, obuf_valid) @[el2_lsu_bus_buffer.scala 508:135] - node _T_4146 = and(_T_4145, obuf_wr_enQ) @[el2_lsu_bus_buffer.scala 508:148] - buf_cmd_state_bus_en[3] <= _T_4146 @[el2_lsu_bus_buffer.scala 508:33] - buf_state_bus_en[3] <= buf_cmd_state_bus_en[3] @[el2_lsu_bus_buffer.scala 509:29] - node _T_4147 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 510:49] - node _T_4148 = or(_T_4147, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 510:70] - buf_state_en[3] <= _T_4148 @[el2_lsu_bus_buffer.scala 510:25] - buf_ldfwd_in[3] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 511:25] - node _T_4149 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 512:56] - node _T_4150 = eq(_T_4149, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 512:46] - node _T_4151 = and(buf_state_en[3], _T_4150) @[el2_lsu_bus_buffer.scala 512:44] - node _T_4152 = and(_T_4151, obuf_nosend) @[el2_lsu_bus_buffer.scala 512:60] - node _T_4153 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 512:76] - node _T_4154 = and(_T_4152, _T_4153) @[el2_lsu_bus_buffer.scala 512:74] - buf_ldfwd_en[3] <= _T_4154 @[el2_lsu_bus_buffer.scala 512:25] - node _T_4155 = bits(obuf_rdrsp_tag, 1, 0) @[el2_lsu_bus_buffer.scala 513:46] - buf_ldfwdtag_in[3] <= _T_4155 @[el2_lsu_bus_buffer.scala 513:28] - node _T_4156 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 514:47] - node _T_4157 = and(_T_4156, obuf_nosend) @[el2_lsu_bus_buffer.scala 514:67] - node _T_4158 = and(_T_4157, bus_rsp_read) @[el2_lsu_bus_buffer.scala 514:81] - buf_data_en[3] <= _T_4158 @[el2_lsu_bus_buffer.scala 514:24] - node _T_4159 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 515:48] - node _T_4160 = and(_T_4159, obuf_nosend) @[el2_lsu_bus_buffer.scala 515:68] - node _T_4161 = and(_T_4160, bus_rsp_read_error) @[el2_lsu_bus_buffer.scala 515:82] - buf_error_en[3] <= _T_4161 @[el2_lsu_bus_buffer.scala 515:25] - node _T_4162 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 516:61] - node _T_4163 = bits(buf_addr[3], 2, 2) @[el2_lsu_bus_buffer.scala 516:85] - node _T_4164 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 516:103] - node _T_4165 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 516:126] - node _T_4166 = mux(_T_4163, _T_4164, _T_4165) @[el2_lsu_bus_buffer.scala 516:73] - node _T_4167 = mux(buf_error_en[3], _T_4162, _T_4166) @[el2_lsu_bus_buffer.scala 516:30] - buf_data_in[3] <= _T_4167 @[el2_lsu_bus_buffer.scala 516:24] + node _T_4135 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 508:60] + node _T_4136 = and(obuf_nosend, bus_rsp_read) @[el2_lsu_bus_buffer.scala 508:89] + node _T_4137 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[el2_lsu_bus_buffer.scala 508:124] + node _T_4138 = and(_T_4136, _T_4137) @[el2_lsu_bus_buffer.scala 508:104] + node _T_4139 = mux(_T_4138, UInt<3>("h05"), UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 508:75] + node _T_4140 = mux(_T_4135, UInt<3>("h00"), _T_4139) @[el2_lsu_bus_buffer.scala 508:31] + buf_nxtstate[3] <= _T_4140 @[el2_lsu_bus_buffer.scala 508:25] + node _T_4141 = eq(obuf_tag0, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 509:48] + node _T_4142 = eq(obuf_tag1, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 509:104] + node _T_4143 = and(obuf_merge, _T_4142) @[el2_lsu_bus_buffer.scala 509:91] + node _T_4144 = or(_T_4141, _T_4143) @[el2_lsu_bus_buffer.scala 509:77] + node _T_4145 = and(_T_4144, obuf_valid) @[el2_lsu_bus_buffer.scala 509:135] + node _T_4146 = and(_T_4145, obuf_wr_enQ) @[el2_lsu_bus_buffer.scala 509:148] + buf_cmd_state_bus_en[3] <= _T_4146 @[el2_lsu_bus_buffer.scala 509:33] + buf_state_bus_en[3] <= buf_cmd_state_bus_en[3] @[el2_lsu_bus_buffer.scala 510:29] + node _T_4147 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 511:49] + node _T_4148 = or(_T_4147, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 511:70] + buf_state_en[3] <= _T_4148 @[el2_lsu_bus_buffer.scala 511:25] + buf_ldfwd_in[3] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 512:25] + node _T_4149 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 513:56] + node _T_4150 = eq(_T_4149, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 513:46] + node _T_4151 = and(buf_state_en[3], _T_4150) @[el2_lsu_bus_buffer.scala 513:44] + node _T_4152 = and(_T_4151, obuf_nosend) @[el2_lsu_bus_buffer.scala 513:60] + node _T_4153 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 513:76] + node _T_4154 = and(_T_4152, _T_4153) @[el2_lsu_bus_buffer.scala 513:74] + buf_ldfwd_en[3] <= _T_4154 @[el2_lsu_bus_buffer.scala 513:25] + node _T_4155 = bits(obuf_rdrsp_tag, 1, 0) @[el2_lsu_bus_buffer.scala 514:46] + buf_ldfwdtag_in[3] <= _T_4155 @[el2_lsu_bus_buffer.scala 514:28] + node _T_4156 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 515:47] + node _T_4157 = and(_T_4156, obuf_nosend) @[el2_lsu_bus_buffer.scala 515:67] + node _T_4158 = and(_T_4157, bus_rsp_read) @[el2_lsu_bus_buffer.scala 515:81] + buf_data_en[3] <= _T_4158 @[el2_lsu_bus_buffer.scala 515:24] + node _T_4159 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 516:48] + node _T_4160 = and(_T_4159, obuf_nosend) @[el2_lsu_bus_buffer.scala 516:68] + node _T_4161 = and(_T_4160, bus_rsp_read_error) @[el2_lsu_bus_buffer.scala 516:82] + buf_error_en[3] <= _T_4161 @[el2_lsu_bus_buffer.scala 516:25] + node _T_4162 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 517:61] + node _T_4163 = bits(buf_addr[3], 2, 2) @[el2_lsu_bus_buffer.scala 517:85] + node _T_4164 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 517:103] + node _T_4165 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 517:126] + node _T_4166 = mux(_T_4163, _T_4164, _T_4165) @[el2_lsu_bus_buffer.scala 517:73] + node _T_4167 = mux(buf_error_en[3], _T_4162, _T_4166) @[el2_lsu_bus_buffer.scala 517:30] + buf_data_in[3] <= _T_4167 @[el2_lsu_bus_buffer.scala 517:24] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_4168 = eq(UInt<3>("h03"), buf_state[3]) @[Conditional.scala 37:30] when _T_4168 : @[Conditional.scala 39:67] - node _T_4169 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 519:67] - node _T_4170 = and(UInt<1>("h01"), bus_rsp_write_error) @[el2_lsu_bus_buffer.scala 519:94] - node _T_4171 = eq(_T_4170, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 519:73] - node _T_4172 = and(_T_4169, _T_4171) @[el2_lsu_bus_buffer.scala 519:71] - node _T_4173 = or(io.dec_tlu_force_halt, _T_4172) @[el2_lsu_bus_buffer.scala 519:55] - node _T_4174 = bits(_T_4173, 0, 0) @[el2_lsu_bus_buffer.scala 519:125] - node _T_4175 = eq(buf_samedw[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 520:30] - node _T_4176 = and(buf_dual[3], _T_4175) @[el2_lsu_bus_buffer.scala 520:28] - node _T_4177 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 520:57] - node _T_4178 = eq(_T_4177, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 520:47] - node _T_4179 = and(_T_4176, _T_4178) @[el2_lsu_bus_buffer.scala 520:45] - node _T_4180 = neq(buf_state[buf_dualtag[3]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 520:90] - node _T_4181 = and(_T_4179, _T_4180) @[el2_lsu_bus_buffer.scala 520:61] - node _T_4182 = bits(buf_ldfwd, 3, 3) @[el2_lsu_bus_buffer.scala 521:27] - node _T_4183 = or(_T_4182, any_done_wait_state) @[el2_lsu_bus_buffer.scala 521:31] - node _T_4184 = eq(buf_samedw[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 521:70] - node _T_4185 = and(buf_dual[3], _T_4184) @[el2_lsu_bus_buffer.scala 521:68] - node _T_4186 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 521:97] - node _T_4187 = eq(_T_4186, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 521:87] - node _T_4188 = and(_T_4185, _T_4187) @[el2_lsu_bus_buffer.scala 521:85] + node _T_4169 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 520:67] + node _T_4170 = and(UInt<1>("h01"), bus_rsp_write_error) @[el2_lsu_bus_buffer.scala 520:94] + node _T_4171 = eq(_T_4170, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 520:73] + node _T_4172 = and(_T_4169, _T_4171) @[el2_lsu_bus_buffer.scala 520:71] + node _T_4173 = or(io.dec_tlu_force_halt, _T_4172) @[el2_lsu_bus_buffer.scala 520:55] + node _T_4174 = bits(_T_4173, 0, 0) @[el2_lsu_bus_buffer.scala 520:125] + node _T_4175 = eq(buf_samedw[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 521:30] + node _T_4176 = and(buf_dual[3], _T_4175) @[el2_lsu_bus_buffer.scala 521:28] + node _T_4177 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 521:57] + node _T_4178 = eq(_T_4177, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 521:47] + node _T_4179 = and(_T_4176, _T_4178) @[el2_lsu_bus_buffer.scala 521:45] + node _T_4180 = neq(buf_state[buf_dualtag[3]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 521:90] + node _T_4181 = and(_T_4179, _T_4180) @[el2_lsu_bus_buffer.scala 521:61] + node _T_4182 = bits(buf_ldfwd, 3, 3) @[el2_lsu_bus_buffer.scala 522:27] + node _T_4183 = or(_T_4182, any_done_wait_state) @[el2_lsu_bus_buffer.scala 522:31] + node _T_4184 = eq(buf_samedw[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 522:70] + node _T_4185 = and(buf_dual[3], _T_4184) @[el2_lsu_bus_buffer.scala 522:68] + node _T_4186 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 522:97] + node _T_4187 = eq(_T_4186, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 522:87] + node _T_4188 = and(_T_4185, _T_4187) @[el2_lsu_bus_buffer.scala 522:85] node _T_4189 = eq(buf_dualtag[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] node _T_4190 = bits(buf_ldfwd, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] node _T_4191 = eq(buf_dualtag[3], UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] @@ -5401,172 +5399,172 @@ circuit el2_lsu_bus_intf : node _T_4203 = or(_T_4202, _T_4200) @[Mux.scala 27:72] wire _T_4204 : UInt<1> @[Mux.scala 27:72] _T_4204 <= _T_4203 @[Mux.scala 27:72] - node _T_4205 = and(_T_4188, _T_4204) @[el2_lsu_bus_buffer.scala 521:101] - node _T_4206 = eq(buf_state[buf_dualtag[3]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 521:167] - node _T_4207 = and(_T_4205, _T_4206) @[el2_lsu_bus_buffer.scala 521:138] - node _T_4208 = and(_T_4207, any_done_wait_state) @[el2_lsu_bus_buffer.scala 521:187] - node _T_4209 = or(_T_4183, _T_4208) @[el2_lsu_bus_buffer.scala 521:53] - node _T_4210 = mux(_T_4209, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 521:16] - node _T_4211 = mux(_T_4181, UInt<3>("h04"), _T_4210) @[el2_lsu_bus_buffer.scala 520:14] - node _T_4212 = mux(_T_4174, UInt<3>("h00"), _T_4211) @[el2_lsu_bus_buffer.scala 519:31] - buf_nxtstate[3] <= _T_4212 @[el2_lsu_bus_buffer.scala 519:25] - node _T_4213 = eq(bus_rsp_write_tag, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 522:73] - node _T_4214 = and(bus_rsp_write, _T_4213) @[el2_lsu_bus_buffer.scala 522:52] - node _T_4215 = eq(bus_rsp_read_tag, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 523:46] - node _T_4216 = bits(buf_ldfwd, 3, 3) @[el2_lsu_bus_buffer.scala 524:23] - node _T_4217 = eq(bus_rsp_read_tag, buf_ldfwdtag[3]) @[el2_lsu_bus_buffer.scala 524:47] - node _T_4218 = and(_T_4216, _T_4217) @[el2_lsu_bus_buffer.scala 524:27] - node _T_4219 = or(_T_4215, _T_4218) @[el2_lsu_bus_buffer.scala 523:77] - node _T_4220 = and(buf_dual[3], buf_dualhi[3]) @[el2_lsu_bus_buffer.scala 525:26] - node _T_4221 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 525:54] - node _T_4222 = not(_T_4221) @[el2_lsu_bus_buffer.scala 525:44] - node _T_4223 = and(_T_4220, _T_4222) @[el2_lsu_bus_buffer.scala 525:42] - node _T_4224 = and(_T_4223, buf_samedw[3]) @[el2_lsu_bus_buffer.scala 525:58] - node _T_4225 = eq(bus_rsp_read_tag, buf_dualtag[3]) @[el2_lsu_bus_buffer.scala 525:94] - node _T_4226 = and(_T_4224, _T_4225) @[el2_lsu_bus_buffer.scala 525:74] - node _T_4227 = or(_T_4219, _T_4226) @[el2_lsu_bus_buffer.scala 524:71] - node _T_4228 = and(bus_rsp_read, _T_4227) @[el2_lsu_bus_buffer.scala 523:25] - node _T_4229 = or(_T_4214, _T_4228) @[el2_lsu_bus_buffer.scala 522:105] - buf_resp_state_bus_en[3] <= _T_4229 @[el2_lsu_bus_buffer.scala 522:34] - buf_state_bus_en[3] <= buf_resp_state_bus_en[3] @[el2_lsu_bus_buffer.scala 526:29] - node _T_4230 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 527:49] - node _T_4231 = or(_T_4230, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 527:70] - buf_state_en[3] <= _T_4231 @[el2_lsu_bus_buffer.scala 527:25] - node _T_4232 = and(buf_state_bus_en[3], bus_rsp_read) @[el2_lsu_bus_buffer.scala 528:47] - node _T_4233 = and(_T_4232, io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 528:62] - buf_data_en[3] <= _T_4233 @[el2_lsu_bus_buffer.scala 528:24] - node _T_4234 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 529:48] - node _T_4235 = eq(bus_rsp_read_tag, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 529:111] - node _T_4236 = and(bus_rsp_read_error, _T_4235) @[el2_lsu_bus_buffer.scala 529:91] - node _T_4237 = bits(buf_ldfwd, 3, 3) @[el2_lsu_bus_buffer.scala 530:42] - node _T_4238 = and(bus_rsp_read_error, _T_4237) @[el2_lsu_bus_buffer.scala 530:31] - node _T_4239 = eq(bus_rsp_read_tag, buf_ldfwdtag[3]) @[el2_lsu_bus_buffer.scala 530:66] - node _T_4240 = and(_T_4238, _T_4239) @[el2_lsu_bus_buffer.scala 530:46] - node _T_4241 = or(_T_4236, _T_4240) @[el2_lsu_bus_buffer.scala 529:143] - node _T_4242 = and(bus_rsp_write_error, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 531:32] - node _T_4243 = eq(bus_rsp_write_tag, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 531:74] - node _T_4244 = and(_T_4242, _T_4243) @[el2_lsu_bus_buffer.scala 531:53] - node _T_4245 = or(_T_4241, _T_4244) @[el2_lsu_bus_buffer.scala 530:88] - node _T_4246 = and(_T_4234, _T_4245) @[el2_lsu_bus_buffer.scala 529:68] - buf_error_en[3] <= _T_4246 @[el2_lsu_bus_buffer.scala 529:25] - node _T_4247 = eq(buf_error_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 532:50] - node _T_4248 = and(buf_state_en[3], _T_4247) @[el2_lsu_bus_buffer.scala 532:48] - node _T_4249 = bits(buf_addr[3], 2, 2) @[el2_lsu_bus_buffer.scala 532:84] - node _T_4250 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 532:102] - node _T_4251 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 532:125] - node _T_4252 = mux(_T_4249, _T_4250, _T_4251) @[el2_lsu_bus_buffer.scala 532:72] - node _T_4253 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 532:148] - node _T_4254 = mux(_T_4248, _T_4252, _T_4253) @[el2_lsu_bus_buffer.scala 532:30] - buf_data_in[3] <= _T_4254 @[el2_lsu_bus_buffer.scala 532:24] + node _T_4205 = and(_T_4188, _T_4204) @[el2_lsu_bus_buffer.scala 522:101] + node _T_4206 = eq(buf_state[buf_dualtag[3]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 522:167] + node _T_4207 = and(_T_4205, _T_4206) @[el2_lsu_bus_buffer.scala 522:138] + node _T_4208 = and(_T_4207, any_done_wait_state) @[el2_lsu_bus_buffer.scala 522:187] + node _T_4209 = or(_T_4183, _T_4208) @[el2_lsu_bus_buffer.scala 522:53] + node _T_4210 = mux(_T_4209, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 522:16] + node _T_4211 = mux(_T_4181, UInt<3>("h04"), _T_4210) @[el2_lsu_bus_buffer.scala 521:14] + node _T_4212 = mux(_T_4174, UInt<3>("h00"), _T_4211) @[el2_lsu_bus_buffer.scala 520:31] + buf_nxtstate[3] <= _T_4212 @[el2_lsu_bus_buffer.scala 520:25] + node _T_4213 = eq(bus_rsp_write_tag, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 523:73] + node _T_4214 = and(bus_rsp_write, _T_4213) @[el2_lsu_bus_buffer.scala 523:52] + node _T_4215 = eq(bus_rsp_read_tag, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 524:46] + node _T_4216 = bits(buf_ldfwd, 3, 3) @[el2_lsu_bus_buffer.scala 525:23] + node _T_4217 = eq(bus_rsp_read_tag, buf_ldfwdtag[3]) @[el2_lsu_bus_buffer.scala 525:47] + node _T_4218 = and(_T_4216, _T_4217) @[el2_lsu_bus_buffer.scala 525:27] + node _T_4219 = or(_T_4215, _T_4218) @[el2_lsu_bus_buffer.scala 524:77] + node _T_4220 = and(buf_dual[3], buf_dualhi[3]) @[el2_lsu_bus_buffer.scala 526:26] + node _T_4221 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 526:54] + node _T_4222 = not(_T_4221) @[el2_lsu_bus_buffer.scala 526:44] + node _T_4223 = and(_T_4220, _T_4222) @[el2_lsu_bus_buffer.scala 526:42] + node _T_4224 = and(_T_4223, buf_samedw[3]) @[el2_lsu_bus_buffer.scala 526:58] + node _T_4225 = eq(bus_rsp_read_tag, buf_dualtag[3]) @[el2_lsu_bus_buffer.scala 526:94] + node _T_4226 = and(_T_4224, _T_4225) @[el2_lsu_bus_buffer.scala 526:74] + node _T_4227 = or(_T_4219, _T_4226) @[el2_lsu_bus_buffer.scala 525:71] + node _T_4228 = and(bus_rsp_read, _T_4227) @[el2_lsu_bus_buffer.scala 524:25] + node _T_4229 = or(_T_4214, _T_4228) @[el2_lsu_bus_buffer.scala 523:105] + buf_resp_state_bus_en[3] <= _T_4229 @[el2_lsu_bus_buffer.scala 523:34] + buf_state_bus_en[3] <= buf_resp_state_bus_en[3] @[el2_lsu_bus_buffer.scala 527:29] + node _T_4230 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 528:49] + node _T_4231 = or(_T_4230, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 528:70] + buf_state_en[3] <= _T_4231 @[el2_lsu_bus_buffer.scala 528:25] + node _T_4232 = and(buf_state_bus_en[3], bus_rsp_read) @[el2_lsu_bus_buffer.scala 529:47] + node _T_4233 = and(_T_4232, io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 529:62] + buf_data_en[3] <= _T_4233 @[el2_lsu_bus_buffer.scala 529:24] + node _T_4234 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 530:48] + node _T_4235 = eq(bus_rsp_read_tag, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 530:111] + node _T_4236 = and(bus_rsp_read_error, _T_4235) @[el2_lsu_bus_buffer.scala 530:91] + node _T_4237 = bits(buf_ldfwd, 3, 3) @[el2_lsu_bus_buffer.scala 531:42] + node _T_4238 = and(bus_rsp_read_error, _T_4237) @[el2_lsu_bus_buffer.scala 531:31] + node _T_4239 = eq(bus_rsp_read_tag, buf_ldfwdtag[3]) @[el2_lsu_bus_buffer.scala 531:66] + node _T_4240 = and(_T_4238, _T_4239) @[el2_lsu_bus_buffer.scala 531:46] + node _T_4241 = or(_T_4236, _T_4240) @[el2_lsu_bus_buffer.scala 530:143] + node _T_4242 = and(bus_rsp_write_error, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 532:32] + node _T_4243 = eq(bus_rsp_write_tag, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 532:74] + node _T_4244 = and(_T_4242, _T_4243) @[el2_lsu_bus_buffer.scala 532:53] + node _T_4245 = or(_T_4241, _T_4244) @[el2_lsu_bus_buffer.scala 531:88] + node _T_4246 = and(_T_4234, _T_4245) @[el2_lsu_bus_buffer.scala 530:68] + buf_error_en[3] <= _T_4246 @[el2_lsu_bus_buffer.scala 530:25] + node _T_4247 = eq(buf_error_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 533:50] + node _T_4248 = and(buf_state_en[3], _T_4247) @[el2_lsu_bus_buffer.scala 533:48] + node _T_4249 = bits(buf_addr[3], 2, 2) @[el2_lsu_bus_buffer.scala 533:84] + node _T_4250 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 533:102] + node _T_4251 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 533:125] + node _T_4252 = mux(_T_4249, _T_4250, _T_4251) @[el2_lsu_bus_buffer.scala 533:72] + node _T_4253 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 533:148] + node _T_4254 = mux(_T_4248, _T_4252, _T_4253) @[el2_lsu_bus_buffer.scala 533:30] + buf_data_in[3] <= _T_4254 @[el2_lsu_bus_buffer.scala 533:24] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_4255 = eq(UInt<3>("h04"), buf_state[3]) @[Conditional.scala 37:30] when _T_4255 : @[Conditional.scala 39:67] - node _T_4256 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 535:60] - node _T_4257 = bits(buf_ldfwd, 3, 3) @[el2_lsu_bus_buffer.scala 535:86] - node _T_4258 = dshr(buf_ldfwd, buf_dualtag[3]) @[el2_lsu_bus_buffer.scala 535:101] - node _T_4259 = bits(_T_4258, 0, 0) @[el2_lsu_bus_buffer.scala 535:101] - node _T_4260 = or(_T_4257, _T_4259) @[el2_lsu_bus_buffer.scala 535:90] - node _T_4261 = or(_T_4260, any_done_wait_state) @[el2_lsu_bus_buffer.scala 535:118] - node _T_4262 = mux(_T_4261, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 535:75] - node _T_4263 = mux(_T_4256, UInt<3>("h00"), _T_4262) @[el2_lsu_bus_buffer.scala 535:31] - buf_nxtstate[3] <= _T_4263 @[el2_lsu_bus_buffer.scala 535:25] - node _T_4264 = eq(bus_rsp_read_tag, buf_dualtag[3]) @[el2_lsu_bus_buffer.scala 536:66] - node _T_4265 = dshr(buf_ldfwd, buf_dualtag[3]) @[el2_lsu_bus_buffer.scala 537:21] - node _T_4266 = bits(_T_4265, 0, 0) @[el2_lsu_bus_buffer.scala 537:21] - node _T_4267 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[3]]) @[el2_lsu_bus_buffer.scala 537:58] - node _T_4268 = and(_T_4266, _T_4267) @[el2_lsu_bus_buffer.scala 537:38] - node _T_4269 = or(_T_4264, _T_4268) @[el2_lsu_bus_buffer.scala 536:95] - node _T_4270 = and(bus_rsp_read, _T_4269) @[el2_lsu_bus_buffer.scala 536:45] - buf_state_bus_en[3] <= _T_4270 @[el2_lsu_bus_buffer.scala 536:29] - node _T_4271 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 538:49] - node _T_4272 = or(_T_4271, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 538:70] - buf_state_en[3] <= _T_4272 @[el2_lsu_bus_buffer.scala 538:25] + node _T_4256 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 536:60] + node _T_4257 = bits(buf_ldfwd, 3, 3) @[el2_lsu_bus_buffer.scala 536:86] + node _T_4258 = dshr(buf_ldfwd, buf_dualtag[3]) @[el2_lsu_bus_buffer.scala 536:101] + node _T_4259 = bits(_T_4258, 0, 0) @[el2_lsu_bus_buffer.scala 536:101] + node _T_4260 = or(_T_4257, _T_4259) @[el2_lsu_bus_buffer.scala 536:90] + node _T_4261 = or(_T_4260, any_done_wait_state) @[el2_lsu_bus_buffer.scala 536:118] + node _T_4262 = mux(_T_4261, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 536:75] + node _T_4263 = mux(_T_4256, UInt<3>("h00"), _T_4262) @[el2_lsu_bus_buffer.scala 536:31] + buf_nxtstate[3] <= _T_4263 @[el2_lsu_bus_buffer.scala 536:25] + node _T_4264 = eq(bus_rsp_read_tag, buf_dualtag[3]) @[el2_lsu_bus_buffer.scala 537:66] + node _T_4265 = dshr(buf_ldfwd, buf_dualtag[3]) @[el2_lsu_bus_buffer.scala 538:21] + node _T_4266 = bits(_T_4265, 0, 0) @[el2_lsu_bus_buffer.scala 538:21] + node _T_4267 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[3]]) @[el2_lsu_bus_buffer.scala 538:58] + node _T_4268 = and(_T_4266, _T_4267) @[el2_lsu_bus_buffer.scala 538:38] + node _T_4269 = or(_T_4264, _T_4268) @[el2_lsu_bus_buffer.scala 537:95] + node _T_4270 = and(bus_rsp_read, _T_4269) @[el2_lsu_bus_buffer.scala 537:45] + buf_state_bus_en[3] <= _T_4270 @[el2_lsu_bus_buffer.scala 537:29] + node _T_4271 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 539:49] + node _T_4272 = or(_T_4271, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 539:70] + buf_state_en[3] <= _T_4272 @[el2_lsu_bus_buffer.scala 539:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_4273 = eq(UInt<3>("h05"), buf_state[3]) @[Conditional.scala 37:30] when _T_4273 : @[Conditional.scala 39:67] - node _T_4274 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 541:60] - node _T_4275 = mux(_T_4274, UInt<3>("h00"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 541:31] - buf_nxtstate[3] <= _T_4275 @[el2_lsu_bus_buffer.scala 541:25] - node _T_4276 = eq(RspPtr, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 542:37] - node _T_4277 = eq(buf_dualtag[3], RspPtr) @[el2_lsu_bus_buffer.scala 542:98] - node _T_4278 = and(buf_dual[3], _T_4277) @[el2_lsu_bus_buffer.scala 542:80] - node _T_4279 = or(_T_4276, _T_4278) @[el2_lsu_bus_buffer.scala 542:65] - node _T_4280 = or(_T_4279, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 542:112] - buf_state_en[3] <= _T_4280 @[el2_lsu_bus_buffer.scala 542:25] + node _T_4274 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 542:60] + node _T_4275 = mux(_T_4274, UInt<3>("h00"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 542:31] + buf_nxtstate[3] <= _T_4275 @[el2_lsu_bus_buffer.scala 542:25] + node _T_4276 = eq(RspPtr, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 543:37] + node _T_4277 = eq(buf_dualtag[3], RspPtr) @[el2_lsu_bus_buffer.scala 543:98] + node _T_4278 = and(buf_dual[3], _T_4277) @[el2_lsu_bus_buffer.scala 543:80] + node _T_4279 = or(_T_4276, _T_4278) @[el2_lsu_bus_buffer.scala 543:65] + node _T_4280 = or(_T_4279, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 543:112] + buf_state_en[3] <= _T_4280 @[el2_lsu_bus_buffer.scala 543:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_4281 = eq(UInt<3>("h06"), buf_state[3]) @[Conditional.scala 37:30] when _T_4281 : @[Conditional.scala 39:67] - buf_nxtstate[3] <= UInt<3>("h00") @[el2_lsu_bus_buffer.scala 545:25] - buf_rst[3] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 546:20] - buf_state_en[3] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 547:25] - buf_ldfwd_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 548:25] - buf_ldfwd_en[3] <= buf_state_en[3] @[el2_lsu_bus_buffer.scala 549:25] + buf_nxtstate[3] <= UInt<3>("h00") @[el2_lsu_bus_buffer.scala 546:25] + buf_rst[3] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 547:20] + buf_state_en[3] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 548:25] + buf_ldfwd_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 549:25] + buf_ldfwd_en[3] <= buf_state_en[3] @[el2_lsu_bus_buffer.scala 550:25] skip @[Conditional.scala 39:67] - node _T_4282 = bits(buf_state_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 552:108] + node _T_4282 = bits(buf_state_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 553:108] reg _T_4283 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4282 : @[Reg.scala 28:19] _T_4283 <= buf_nxtstate[3] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_state[3] <= _T_4283 @[el2_lsu_bus_buffer.scala 552:18] - reg _T_4284 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 553:60] - _T_4284 <= buf_age_in_3 @[el2_lsu_bus_buffer.scala 553:60] - buf_ageQ[3] <= _T_4284 @[el2_lsu_bus_buffer.scala 553:17] - reg _T_4285 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 554:63] - _T_4285 <= buf_rspage_in[3] @[el2_lsu_bus_buffer.scala 554:63] - buf_rspageQ[3] <= _T_4285 @[el2_lsu_bus_buffer.scala 554:20] - node _T_4286 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 555:109] + buf_state[3] <= _T_4283 @[el2_lsu_bus_buffer.scala 553:18] + reg _T_4284 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 554:60] + _T_4284 <= buf_age_in_3 @[el2_lsu_bus_buffer.scala 554:60] + buf_ageQ[3] <= _T_4284 @[el2_lsu_bus_buffer.scala 554:17] + reg _T_4285 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 555:63] + _T_4285 <= buf_rspage_in[3] @[el2_lsu_bus_buffer.scala 555:63] + buf_rspageQ[3] <= _T_4285 @[el2_lsu_bus_buffer.scala 555:20] + node _T_4286 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 556:109] reg _T_4287 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4286 : @[Reg.scala 28:19] _T_4287 <= buf_dualtag_in[3] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_dualtag[3] <= _T_4287 @[el2_lsu_bus_buffer.scala 555:20] - node _T_4288 = bits(buf_dual_in, 3, 3) @[el2_lsu_bus_buffer.scala 556:74] - node _T_4289 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 556:107] + buf_dualtag[3] <= _T_4287 @[el2_lsu_bus_buffer.scala 556:20] + node _T_4288 = bits(buf_dual_in, 3, 3) @[el2_lsu_bus_buffer.scala 557:74] + node _T_4289 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 557:107] reg _T_4290 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4289 : @[Reg.scala 28:19] _T_4290 <= _T_4288 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_dual[3] <= _T_4290 @[el2_lsu_bus_buffer.scala 556:17] - node _T_4291 = bits(buf_samedw_in, 3, 3) @[el2_lsu_bus_buffer.scala 557:78] - node _T_4292 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 557:111] + buf_dual[3] <= _T_4290 @[el2_lsu_bus_buffer.scala 557:17] + node _T_4291 = bits(buf_samedw_in, 3, 3) @[el2_lsu_bus_buffer.scala 558:78] + node _T_4292 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 558:111] reg _T_4293 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4292 : @[Reg.scala 28:19] _T_4293 <= _T_4291 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_samedw[3] <= _T_4293 @[el2_lsu_bus_buffer.scala 557:19] - node _T_4294 = bits(buf_nomerge_in, 3, 3) @[el2_lsu_bus_buffer.scala 558:80] - node _T_4295 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 558:113] + buf_samedw[3] <= _T_4293 @[el2_lsu_bus_buffer.scala 558:19] + node _T_4294 = bits(buf_nomerge_in, 3, 3) @[el2_lsu_bus_buffer.scala 559:80] + node _T_4295 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 559:113] reg _T_4296 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4295 : @[Reg.scala 28:19] _T_4296 <= _T_4294 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_nomerge[3] <= _T_4296 @[el2_lsu_bus_buffer.scala 558:20] - node _T_4297 = bits(buf_dualhi_in, 3, 3) @[el2_lsu_bus_buffer.scala 559:78] - node _T_4298 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 559:111] + buf_nomerge[3] <= _T_4296 @[el2_lsu_bus_buffer.scala 559:20] + node _T_4297 = bits(buf_dualhi_in, 3, 3) @[el2_lsu_bus_buffer.scala 560:78] + node _T_4298 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 560:111] reg _T_4299 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4298 : @[Reg.scala 28:19] _T_4299 <= _T_4297 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_dualhi[3] <= _T_4299 @[el2_lsu_bus_buffer.scala 559:19] - node _T_4300 = bits(buf_ldfwd_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 562:131] + buf_dualhi[3] <= _T_4299 @[el2_lsu_bus_buffer.scala 560:19] + node _T_4300 = bits(buf_ldfwd_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 563:131] reg _T_4301 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4300 : @[Reg.scala 28:19] _T_4301 <= buf_ldfwd_in[0] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_4302 = bits(buf_ldfwd_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 562:131] + node _T_4302 = bits(buf_ldfwd_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 563:131] reg _T_4303 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4302 : @[Reg.scala 28:19] _T_4303 <= buf_ldfwd_in[1] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_4304 = bits(buf_ldfwd_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 562:131] + node _T_4304 = bits(buf_ldfwd_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 563:131] reg _T_4305 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4304 : @[Reg.scala 28:19] _T_4305 <= buf_ldfwd_in[2] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_4306 = bits(buf_ldfwd_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 562:131] + node _T_4306 = bits(buf_ldfwd_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 563:131] reg _T_4307 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4306 : @[Reg.scala 28:19] _T_4307 <= buf_ldfwd_in[3] @[Reg.scala 28:23] @@ -5574,51 +5572,51 @@ circuit el2_lsu_bus_intf : node _T_4308 = cat(_T_4307, _T_4305) @[Cat.scala 29:58] node _T_4309 = cat(_T_4308, _T_4303) @[Cat.scala 29:58] node _T_4310 = cat(_T_4309, _T_4301) @[Cat.scala 29:58] - buf_ldfwd <= _T_4310 @[el2_lsu_bus_buffer.scala 562:13] - node _T_4311 = bits(buf_ldfwd_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 563:132] + buf_ldfwd <= _T_4310 @[el2_lsu_bus_buffer.scala 563:13] + node _T_4311 = bits(buf_ldfwd_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 564:132] reg _T_4312 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4311 : @[Reg.scala 28:19] _T_4312 <= buf_ldfwdtag_in[0] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_4313 = bits(buf_ldfwd_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 563:132] + node _T_4313 = bits(buf_ldfwd_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 564:132] reg _T_4314 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4313 : @[Reg.scala 28:19] _T_4314 <= buf_ldfwdtag_in[1] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_4315 = bits(buf_ldfwd_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 563:132] + node _T_4315 = bits(buf_ldfwd_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 564:132] reg _T_4316 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4315 : @[Reg.scala 28:19] _T_4316 <= buf_ldfwdtag_in[2] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_4317 = bits(buf_ldfwd_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 563:132] + node _T_4317 = bits(buf_ldfwd_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 564:132] reg _T_4318 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4317 : @[Reg.scala 28:19] _T_4318 <= buf_ldfwdtag_in[3] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_ldfwdtag[0] <= _T_4312 @[el2_lsu_bus_buffer.scala 563:16] - buf_ldfwdtag[1] <= _T_4314 @[el2_lsu_bus_buffer.scala 563:16] - buf_ldfwdtag[2] <= _T_4316 @[el2_lsu_bus_buffer.scala 563:16] - buf_ldfwdtag[3] <= _T_4318 @[el2_lsu_bus_buffer.scala 563:16] - node _T_4319 = bits(buf_sideeffect_in, 0, 0) @[el2_lsu_bus_buffer.scala 564:105] - node _T_4320 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 564:138] + buf_ldfwdtag[0] <= _T_4312 @[el2_lsu_bus_buffer.scala 564:16] + buf_ldfwdtag[1] <= _T_4314 @[el2_lsu_bus_buffer.scala 564:16] + buf_ldfwdtag[2] <= _T_4316 @[el2_lsu_bus_buffer.scala 564:16] + buf_ldfwdtag[3] <= _T_4318 @[el2_lsu_bus_buffer.scala 564:16] + node _T_4319 = bits(buf_sideeffect_in, 0, 0) @[el2_lsu_bus_buffer.scala 565:105] + node _T_4320 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 565:138] reg _T_4321 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4320 : @[Reg.scala 28:19] _T_4321 <= _T_4319 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_4322 = bits(buf_sideeffect_in, 1, 1) @[el2_lsu_bus_buffer.scala 564:105] - node _T_4323 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 564:138] + node _T_4322 = bits(buf_sideeffect_in, 1, 1) @[el2_lsu_bus_buffer.scala 565:105] + node _T_4323 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 565:138] reg _T_4324 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4323 : @[Reg.scala 28:19] _T_4324 <= _T_4322 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_4325 = bits(buf_sideeffect_in, 2, 2) @[el2_lsu_bus_buffer.scala 564:105] - node _T_4326 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 564:138] + node _T_4325 = bits(buf_sideeffect_in, 2, 2) @[el2_lsu_bus_buffer.scala 565:105] + node _T_4326 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 565:138] reg _T_4327 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4326 : @[Reg.scala 28:19] _T_4327 <= _T_4325 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_4328 = bits(buf_sideeffect_in, 3, 3) @[el2_lsu_bus_buffer.scala 564:105] - node _T_4329 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 564:138] + node _T_4328 = bits(buf_sideeffect_in, 3, 3) @[el2_lsu_bus_buffer.scala 565:105] + node _T_4329 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 565:138] reg _T_4330 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4329 : @[Reg.scala 28:19] _T_4330 <= _T_4328 @[Reg.scala 28:23] @@ -5626,27 +5624,27 @@ circuit el2_lsu_bus_intf : node _T_4331 = cat(_T_4330, _T_4327) @[Cat.scala 29:58] node _T_4332 = cat(_T_4331, _T_4324) @[Cat.scala 29:58] node _T_4333 = cat(_T_4332, _T_4321) @[Cat.scala 29:58] - buf_sideeffect <= _T_4333 @[el2_lsu_bus_buffer.scala 564:18] - node _T_4334 = bits(buf_unsign_in, 0, 0) @[el2_lsu_bus_buffer.scala 565:97] - node _T_4335 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 565:130] + buf_sideeffect <= _T_4333 @[el2_lsu_bus_buffer.scala 565:18] + node _T_4334 = bits(buf_unsign_in, 0, 0) @[el2_lsu_bus_buffer.scala 566:97] + node _T_4335 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 566:130] reg _T_4336 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4335 : @[Reg.scala 28:19] _T_4336 <= _T_4334 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_4337 = bits(buf_unsign_in, 1, 1) @[el2_lsu_bus_buffer.scala 565:97] - node _T_4338 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 565:130] + node _T_4337 = bits(buf_unsign_in, 1, 1) @[el2_lsu_bus_buffer.scala 566:97] + node _T_4338 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 566:130] reg _T_4339 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4338 : @[Reg.scala 28:19] _T_4339 <= _T_4337 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_4340 = bits(buf_unsign_in, 2, 2) @[el2_lsu_bus_buffer.scala 565:97] - node _T_4341 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 565:130] + node _T_4340 = bits(buf_unsign_in, 2, 2) @[el2_lsu_bus_buffer.scala 566:97] + node _T_4341 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 566:130] reg _T_4342 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4341 : @[Reg.scala 28:19] _T_4342 <= _T_4340 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_4343 = bits(buf_unsign_in, 3, 3) @[el2_lsu_bus_buffer.scala 565:97] - node _T_4344 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 565:130] + node _T_4343 = bits(buf_unsign_in, 3, 3) @[el2_lsu_bus_buffer.scala 566:97] + node _T_4344 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 566:130] reg _T_4345 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4344 : @[Reg.scala 28:19] _T_4345 <= _T_4343 @[Reg.scala 28:23] @@ -5654,27 +5652,27 @@ circuit el2_lsu_bus_intf : node _T_4346 = cat(_T_4345, _T_4342) @[Cat.scala 29:58] node _T_4347 = cat(_T_4346, _T_4339) @[Cat.scala 29:58] node _T_4348 = cat(_T_4347, _T_4336) @[Cat.scala 29:58] - buf_unsign <= _T_4348 @[el2_lsu_bus_buffer.scala 565:14] - node _T_4349 = bits(buf_write_in, 0, 0) @[el2_lsu_bus_buffer.scala 566:95] - node _T_4350 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 566:128] + buf_unsign <= _T_4348 @[el2_lsu_bus_buffer.scala 566:14] + node _T_4349 = bits(buf_write_in, 0, 0) @[el2_lsu_bus_buffer.scala 567:95] + node _T_4350 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 567:128] reg _T_4351 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4350 : @[Reg.scala 28:19] _T_4351 <= _T_4349 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_4352 = bits(buf_write_in, 1, 1) @[el2_lsu_bus_buffer.scala 566:95] - node _T_4353 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 566:128] + node _T_4352 = bits(buf_write_in, 1, 1) @[el2_lsu_bus_buffer.scala 567:95] + node _T_4353 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 567:128] reg _T_4354 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4353 : @[Reg.scala 28:19] _T_4354 <= _T_4352 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_4355 = bits(buf_write_in, 2, 2) @[el2_lsu_bus_buffer.scala 566:95] - node _T_4356 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 566:128] + node _T_4355 = bits(buf_write_in, 2, 2) @[el2_lsu_bus_buffer.scala 567:95] + node _T_4356 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 567:128] reg _T_4357 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4356 : @[Reg.scala 28:19] _T_4357 <= _T_4355 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_4358 = bits(buf_write_in, 3, 3) @[el2_lsu_bus_buffer.scala 566:95] - node _T_4359 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 566:128] + node _T_4358 = bits(buf_write_in, 3, 3) @[el2_lsu_bus_buffer.scala 567:95] + node _T_4359 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 567:128] reg _T_4360 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4359 : @[Reg.scala 28:19] _T_4360 <= _T_4358 @[Reg.scala 28:23] @@ -5682,32 +5680,32 @@ circuit el2_lsu_bus_intf : node _T_4361 = cat(_T_4360, _T_4357) @[Cat.scala 29:58] node _T_4362 = cat(_T_4361, _T_4354) @[Cat.scala 29:58] node _T_4363 = cat(_T_4362, _T_4351) @[Cat.scala 29:58] - buf_write <= _T_4363 @[el2_lsu_bus_buffer.scala 566:13] - node _T_4364 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 567:117] + buf_write <= _T_4363 @[el2_lsu_bus_buffer.scala 567:13] + node _T_4364 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 568:117] reg _T_4365 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4364 : @[Reg.scala 28:19] _T_4365 <= buf_sz_in[0] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_4366 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 567:117] + node _T_4366 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 568:117] reg _T_4367 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4366 : @[Reg.scala 28:19] _T_4367 <= buf_sz_in[1] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_4368 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 567:117] + node _T_4368 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 568:117] reg _T_4369 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4368 : @[Reg.scala 28:19] _T_4369 <= buf_sz_in[2] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_4370 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 567:117] + node _T_4370 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 568:117] reg _T_4371 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4370 : @[Reg.scala 28:19] _T_4371 <= buf_sz_in[3] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_sz[0] <= _T_4365 @[el2_lsu_bus_buffer.scala 567:10] - buf_sz[1] <= _T_4367 @[el2_lsu_bus_buffer.scala 567:10] - buf_sz[2] <= _T_4369 @[el2_lsu_bus_buffer.scala 567:10] - buf_sz[3] <= _T_4371 @[el2_lsu_bus_buffer.scala 567:10] - node _T_4372 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 568:80] + buf_sz[0] <= _T_4365 @[el2_lsu_bus_buffer.scala 568:10] + buf_sz[1] <= _T_4367 @[el2_lsu_bus_buffer.scala 568:10] + buf_sz[2] <= _T_4369 @[el2_lsu_bus_buffer.scala 568:10] + buf_sz[3] <= _T_4371 @[el2_lsu_bus_buffer.scala 568:10] + node _T_4372 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 569:80] inst rvclkhdr_4 of rvclkhdr_4 @[el2_lib.scala 508:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset @@ -5716,7 +5714,7 @@ circuit el2_lsu_bus_intf : rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_4373 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_4373 <= buf_addr_in[0] @[el2_lib.scala 514:16] - node _T_4374 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 568:80] + node _T_4374 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 569:80] inst rvclkhdr_5 of rvclkhdr_5 @[el2_lib.scala 508:23] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset @@ -5725,7 +5723,7 @@ circuit el2_lsu_bus_intf : rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_4375 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_4375 <= buf_addr_in[1] @[el2_lib.scala 514:16] - node _T_4376 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 568:80] + node _T_4376 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 569:80] inst rvclkhdr_6 of rvclkhdr_6 @[el2_lib.scala 508:23] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset @@ -5734,7 +5732,7 @@ circuit el2_lsu_bus_intf : rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_4377 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_4377 <= buf_addr_in[2] @[el2_lib.scala 514:16] - node _T_4378 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 568:80] + node _T_4378 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 569:80] inst rvclkhdr_7 of rvclkhdr_7 @[el2_lib.scala 508:23] rvclkhdr_7.clock <= clock rvclkhdr_7.reset <= reset @@ -5743,34 +5741,34 @@ circuit el2_lsu_bus_intf : rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_4379 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_4379 <= buf_addr_in[3] @[el2_lib.scala 514:16] - buf_addr[0] <= _T_4373 @[el2_lsu_bus_buffer.scala 568:12] - buf_addr[1] <= _T_4375 @[el2_lsu_bus_buffer.scala 568:12] - buf_addr[2] <= _T_4377 @[el2_lsu_bus_buffer.scala 568:12] - buf_addr[3] <= _T_4379 @[el2_lsu_bus_buffer.scala 568:12] - node _T_4380 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 569:125] + buf_addr[0] <= _T_4373 @[el2_lsu_bus_buffer.scala 569:12] + buf_addr[1] <= _T_4375 @[el2_lsu_bus_buffer.scala 569:12] + buf_addr[2] <= _T_4377 @[el2_lsu_bus_buffer.scala 569:12] + buf_addr[3] <= _T_4379 @[el2_lsu_bus_buffer.scala 569:12] + node _T_4380 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 570:125] reg _T_4381 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4380 : @[Reg.scala 28:19] _T_4381 <= buf_byteen_in[0] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_4382 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 569:125] + node _T_4382 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 570:125] reg _T_4383 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4382 : @[Reg.scala 28:19] _T_4383 <= buf_byteen_in[1] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_4384 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 569:125] + node _T_4384 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 570:125] reg _T_4385 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4384 : @[Reg.scala 28:19] _T_4385 <= buf_byteen_in[2] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_4386 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 569:125] + node _T_4386 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 570:125] reg _T_4387 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4386 : @[Reg.scala 28:19] _T_4387 <= buf_byteen_in[3] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_byteen[0] <= _T_4381 @[el2_lsu_bus_buffer.scala 569:14] - buf_byteen[1] <= _T_4383 @[el2_lsu_bus_buffer.scala 569:14] - buf_byteen[2] <= _T_4385 @[el2_lsu_bus_buffer.scala 569:14] - buf_byteen[3] <= _T_4387 @[el2_lsu_bus_buffer.scala 569:14] + buf_byteen[0] <= _T_4381 @[el2_lsu_bus_buffer.scala 570:14] + buf_byteen[1] <= _T_4383 @[el2_lsu_bus_buffer.scala 570:14] + buf_byteen[2] <= _T_4385 @[el2_lsu_bus_buffer.scala 570:14] + buf_byteen[3] <= _T_4387 @[el2_lsu_bus_buffer.scala 570:14] inst rvclkhdr_8 of rvclkhdr_8 @[el2_lib.scala 508:23] rvclkhdr_8.clock <= clock rvclkhdr_8.reset <= reset @@ -5803,175 +5801,175 @@ circuit el2_lsu_bus_intf : rvclkhdr_11.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_4391 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_4391 <= buf_data_in[3] @[el2_lib.scala 514:16] - buf_data[0] <= _T_4388 @[el2_lsu_bus_buffer.scala 570:12] - buf_data[1] <= _T_4389 @[el2_lsu_bus_buffer.scala 570:12] - buf_data[2] <= _T_4390 @[el2_lsu_bus_buffer.scala 570:12] - buf_data[3] <= _T_4391 @[el2_lsu_bus_buffer.scala 570:12] - node _T_4392 = bits(buf_error, 0, 0) @[el2_lsu_bus_buffer.scala 571:119] - node _T_4393 = mux(buf_error_en[0], UInt<1>("h01"), _T_4392) @[el2_lsu_bus_buffer.scala 571:84] - node _T_4394 = eq(buf_rst[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 571:126] - node _T_4395 = and(_T_4393, _T_4394) @[el2_lsu_bus_buffer.scala 571:124] - reg _T_4396 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 571:80] - _T_4396 <= _T_4395 @[el2_lsu_bus_buffer.scala 571:80] - node _T_4397 = bits(buf_error, 1, 1) @[el2_lsu_bus_buffer.scala 571:119] - node _T_4398 = mux(buf_error_en[1], UInt<1>("h01"), _T_4397) @[el2_lsu_bus_buffer.scala 571:84] - node _T_4399 = eq(buf_rst[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 571:126] - node _T_4400 = and(_T_4398, _T_4399) @[el2_lsu_bus_buffer.scala 571:124] - reg _T_4401 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 571:80] - _T_4401 <= _T_4400 @[el2_lsu_bus_buffer.scala 571:80] - node _T_4402 = bits(buf_error, 2, 2) @[el2_lsu_bus_buffer.scala 571:119] - node _T_4403 = mux(buf_error_en[2], UInt<1>("h01"), _T_4402) @[el2_lsu_bus_buffer.scala 571:84] - node _T_4404 = eq(buf_rst[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 571:126] - node _T_4405 = and(_T_4403, _T_4404) @[el2_lsu_bus_buffer.scala 571:124] - reg _T_4406 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 571:80] - _T_4406 <= _T_4405 @[el2_lsu_bus_buffer.scala 571:80] - node _T_4407 = bits(buf_error, 3, 3) @[el2_lsu_bus_buffer.scala 571:119] - node _T_4408 = mux(buf_error_en[3], UInt<1>("h01"), _T_4407) @[el2_lsu_bus_buffer.scala 571:84] - node _T_4409 = eq(buf_rst[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 571:126] - node _T_4410 = and(_T_4408, _T_4409) @[el2_lsu_bus_buffer.scala 571:124] - reg _T_4411 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 571:80] - _T_4411 <= _T_4410 @[el2_lsu_bus_buffer.scala 571:80] + buf_data[0] <= _T_4388 @[el2_lsu_bus_buffer.scala 571:12] + buf_data[1] <= _T_4389 @[el2_lsu_bus_buffer.scala 571:12] + buf_data[2] <= _T_4390 @[el2_lsu_bus_buffer.scala 571:12] + buf_data[3] <= _T_4391 @[el2_lsu_bus_buffer.scala 571:12] + node _T_4392 = bits(buf_error, 0, 0) @[el2_lsu_bus_buffer.scala 572:119] + node _T_4393 = mux(buf_error_en[0], UInt<1>("h01"), _T_4392) @[el2_lsu_bus_buffer.scala 572:84] + node _T_4394 = eq(buf_rst[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 572:126] + node _T_4395 = and(_T_4393, _T_4394) @[el2_lsu_bus_buffer.scala 572:124] + reg _T_4396 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 572:80] + _T_4396 <= _T_4395 @[el2_lsu_bus_buffer.scala 572:80] + node _T_4397 = bits(buf_error, 1, 1) @[el2_lsu_bus_buffer.scala 572:119] + node _T_4398 = mux(buf_error_en[1], UInt<1>("h01"), _T_4397) @[el2_lsu_bus_buffer.scala 572:84] + node _T_4399 = eq(buf_rst[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 572:126] + node _T_4400 = and(_T_4398, _T_4399) @[el2_lsu_bus_buffer.scala 572:124] + reg _T_4401 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 572:80] + _T_4401 <= _T_4400 @[el2_lsu_bus_buffer.scala 572:80] + node _T_4402 = bits(buf_error, 2, 2) @[el2_lsu_bus_buffer.scala 572:119] + node _T_4403 = mux(buf_error_en[2], UInt<1>("h01"), _T_4402) @[el2_lsu_bus_buffer.scala 572:84] + node _T_4404 = eq(buf_rst[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 572:126] + node _T_4405 = and(_T_4403, _T_4404) @[el2_lsu_bus_buffer.scala 572:124] + reg _T_4406 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 572:80] + _T_4406 <= _T_4405 @[el2_lsu_bus_buffer.scala 572:80] + node _T_4407 = bits(buf_error, 3, 3) @[el2_lsu_bus_buffer.scala 572:119] + node _T_4408 = mux(buf_error_en[3], UInt<1>("h01"), _T_4407) @[el2_lsu_bus_buffer.scala 572:84] + node _T_4409 = eq(buf_rst[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 572:126] + node _T_4410 = and(_T_4408, _T_4409) @[el2_lsu_bus_buffer.scala 572:124] + reg _T_4411 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 572:80] + _T_4411 <= _T_4410 @[el2_lsu_bus_buffer.scala 572:80] node _T_4412 = cat(_T_4411, _T_4406) @[Cat.scala 29:58] node _T_4413 = cat(_T_4412, _T_4401) @[Cat.scala 29:58] node _T_4414 = cat(_T_4413, _T_4396) @[Cat.scala 29:58] - buf_error <= _T_4414 @[el2_lsu_bus_buffer.scala 571:13] + buf_error <= _T_4414 @[el2_lsu_bus_buffer.scala 572:13] node _T_4415 = cat(io.lsu_busreq_m, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_4416 = mux(io.ldst_dual_m, _T_4415, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 574:28] + node _T_4416 = mux(io.ldst_dual_m, _T_4415, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 575:28] node _T_4417 = cat(io.lsu_busreq_r, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_4418 = mux(io.ldst_dual_r, _T_4417, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 574:94] - node _T_4419 = add(_T_4416, _T_4418) @[el2_lsu_bus_buffer.scala 574:88] - node _T_4420 = add(_T_4419, ibuf_valid) @[el2_lsu_bus_buffer.scala 574:154] - node _T_4421 = neq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 574:190] - node _T_4422 = neq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 574:190] - node _T_4423 = neq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 574:190] - node _T_4424 = neq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 574:190] - node _T_4425 = add(_T_4421, _T_4422) @[el2_lsu_bus_buffer.scala 574:217] - node _T_4426 = add(_T_4425, _T_4423) @[el2_lsu_bus_buffer.scala 574:217] - node _T_4427 = add(_T_4426, _T_4424) @[el2_lsu_bus_buffer.scala 574:217] - node _T_4428 = add(_T_4420, _T_4427) @[el2_lsu_bus_buffer.scala 574:169] - node buf_numvld_any = tail(_T_4428, 1) @[el2_lsu_bus_buffer.scala 574:169] - node _T_4429 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 575:60] - node _T_4430 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 575:79] - node _T_4431 = and(_T_4429, _T_4430) @[el2_lsu_bus_buffer.scala 575:64] - node _T_4432 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 575:91] - node _T_4433 = and(_T_4431, _T_4432) @[el2_lsu_bus_buffer.scala 575:89] - node _T_4434 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 575:60] - node _T_4435 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 575:79] - node _T_4436 = and(_T_4434, _T_4435) @[el2_lsu_bus_buffer.scala 575:64] - node _T_4437 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 575:91] - node _T_4438 = and(_T_4436, _T_4437) @[el2_lsu_bus_buffer.scala 575:89] - node _T_4439 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 575:60] - node _T_4440 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 575:79] - node _T_4441 = and(_T_4439, _T_4440) @[el2_lsu_bus_buffer.scala 575:64] - node _T_4442 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 575:91] - node _T_4443 = and(_T_4441, _T_4442) @[el2_lsu_bus_buffer.scala 575:89] - node _T_4444 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 575:60] - node _T_4445 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 575:79] - node _T_4446 = and(_T_4444, _T_4445) @[el2_lsu_bus_buffer.scala 575:64] - node _T_4447 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 575:91] - node _T_4448 = and(_T_4446, _T_4447) @[el2_lsu_bus_buffer.scala 575:89] - node _T_4449 = add(_T_4448, _T_4443) @[el2_lsu_bus_buffer.scala 575:142] - node _T_4450 = add(_T_4449, _T_4438) @[el2_lsu_bus_buffer.scala 575:142] - node _T_4451 = add(_T_4450, _T_4433) @[el2_lsu_bus_buffer.scala 575:142] - buf_numvld_wrcmd_any <= _T_4451 @[el2_lsu_bus_buffer.scala 575:24] - node _T_4452 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 576:63] - node _T_4453 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 576:75] - node _T_4454 = and(_T_4452, _T_4453) @[el2_lsu_bus_buffer.scala 576:73] - node _T_4455 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 576:63] - node _T_4456 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 576:75] - node _T_4457 = and(_T_4455, _T_4456) @[el2_lsu_bus_buffer.scala 576:73] - node _T_4458 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 576:63] - node _T_4459 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 576:75] - node _T_4460 = and(_T_4458, _T_4459) @[el2_lsu_bus_buffer.scala 576:73] - node _T_4461 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 576:63] - node _T_4462 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 576:75] - node _T_4463 = and(_T_4461, _T_4462) @[el2_lsu_bus_buffer.scala 576:73] - node _T_4464 = add(_T_4463, _T_4460) @[el2_lsu_bus_buffer.scala 576:126] - node _T_4465 = add(_T_4464, _T_4457) @[el2_lsu_bus_buffer.scala 576:126] - node _T_4466 = add(_T_4465, _T_4454) @[el2_lsu_bus_buffer.scala 576:126] - buf_numvld_cmd_any <= _T_4466 @[el2_lsu_bus_buffer.scala 576:22] - node _T_4467 = eq(buf_state[0], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 577:63] - node _T_4468 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 577:90] - node _T_4469 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 577:102] - node _T_4470 = and(_T_4468, _T_4469) @[el2_lsu_bus_buffer.scala 577:100] - node _T_4471 = or(_T_4467, _T_4470) @[el2_lsu_bus_buffer.scala 577:74] - node _T_4472 = eq(buf_state[1], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 577:63] - node _T_4473 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 577:90] - node _T_4474 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 577:102] - node _T_4475 = and(_T_4473, _T_4474) @[el2_lsu_bus_buffer.scala 577:100] - node _T_4476 = or(_T_4472, _T_4475) @[el2_lsu_bus_buffer.scala 577:74] - node _T_4477 = eq(buf_state[2], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 577:63] - node _T_4478 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 577:90] - node _T_4479 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 577:102] - node _T_4480 = and(_T_4478, _T_4479) @[el2_lsu_bus_buffer.scala 577:100] - node _T_4481 = or(_T_4477, _T_4480) @[el2_lsu_bus_buffer.scala 577:74] - node _T_4482 = eq(buf_state[3], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 577:63] - node _T_4483 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 577:90] - node _T_4484 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 577:102] - node _T_4485 = and(_T_4483, _T_4484) @[el2_lsu_bus_buffer.scala 577:100] - node _T_4486 = or(_T_4482, _T_4485) @[el2_lsu_bus_buffer.scala 577:74] - node _T_4487 = add(_T_4486, _T_4481) @[el2_lsu_bus_buffer.scala 577:154] - node _T_4488 = add(_T_4487, _T_4476) @[el2_lsu_bus_buffer.scala 577:154] - node _T_4489 = add(_T_4488, _T_4471) @[el2_lsu_bus_buffer.scala 577:154] - buf_numvld_pend_any <= _T_4489 @[el2_lsu_bus_buffer.scala 577:23] - node _T_4490 = eq(buf_state[0], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 578:61] - node _T_4491 = eq(buf_state[1], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 578:61] - node _T_4492 = eq(buf_state[2], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 578:61] - node _T_4493 = eq(buf_state[3], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 578:61] - node _T_4494 = or(_T_4493, _T_4492) @[el2_lsu_bus_buffer.scala 578:93] - node _T_4495 = or(_T_4494, _T_4491) @[el2_lsu_bus_buffer.scala 578:93] - node _T_4496 = or(_T_4495, _T_4490) @[el2_lsu_bus_buffer.scala 578:93] - any_done_wait_state <= _T_4496 @[el2_lsu_bus_buffer.scala 578:23] - node _T_4497 = orr(buf_numvld_pend_any) @[el2_lsu_bus_buffer.scala 579:53] - io.lsu_bus_buffer_pend_any <= _T_4497 @[el2_lsu_bus_buffer.scala 579:30] - node _T_4498 = and(io.ldst_dual_d, io.dec_lsu_valid_raw_d) @[el2_lsu_bus_buffer.scala 580:52] - node _T_4499 = geq(buf_numvld_any, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 580:92] - node _T_4500 = eq(buf_numvld_any, UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 580:121] - node _T_4501 = mux(_T_4498, _T_4499, _T_4500) @[el2_lsu_bus_buffer.scala 580:36] - io.lsu_bus_buffer_full_any <= _T_4501 @[el2_lsu_bus_buffer.scala 580:30] - node _T_4502 = orr(buf_state[0]) @[el2_lsu_bus_buffer.scala 581:52] - node _T_4503 = orr(buf_state[1]) @[el2_lsu_bus_buffer.scala 581:52] - node _T_4504 = orr(buf_state[2]) @[el2_lsu_bus_buffer.scala 581:52] - node _T_4505 = orr(buf_state[3]) @[el2_lsu_bus_buffer.scala 581:52] - node _T_4506 = or(_T_4502, _T_4503) @[el2_lsu_bus_buffer.scala 581:65] - node _T_4507 = or(_T_4506, _T_4504) @[el2_lsu_bus_buffer.scala 581:65] - node _T_4508 = or(_T_4507, _T_4505) @[el2_lsu_bus_buffer.scala 581:65] - node _T_4509 = eq(_T_4508, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 581:34] - node _T_4510 = eq(ibuf_valid, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 581:72] - node _T_4511 = and(_T_4509, _T_4510) @[el2_lsu_bus_buffer.scala 581:70] - node _T_4512 = eq(obuf_valid, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 581:86] - node _T_4513 = and(_T_4511, _T_4512) @[el2_lsu_bus_buffer.scala 581:84] - io.lsu_bus_buffer_empty_any <= _T_4513 @[el2_lsu_bus_buffer.scala 581:31] - node _T_4514 = and(io.lsu_busreq_m, io.lsu_pkt_m.valid) @[el2_lsu_bus_buffer.scala 583:51] - node _T_4515 = and(_T_4514, io.lsu_pkt_m.load) @[el2_lsu_bus_buffer.scala 583:72] - node _T_4516 = eq(io.flush_m_up, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 583:94] - node _T_4517 = and(_T_4515, _T_4516) @[el2_lsu_bus_buffer.scala 583:92] - node _T_4518 = eq(io.ld_full_hit_m, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 583:111] - node _T_4519 = and(_T_4517, _T_4518) @[el2_lsu_bus_buffer.scala 583:109] - io.lsu_nonblock_load_valid_m <= _T_4519 @[el2_lsu_bus_buffer.scala 583:32] - io.lsu_nonblock_load_tag_m <= WrPtr0_m @[el2_lsu_bus_buffer.scala 584:30] + node _T_4418 = mux(io.ldst_dual_r, _T_4417, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 575:94] + node _T_4419 = add(_T_4416, _T_4418) @[el2_lsu_bus_buffer.scala 575:88] + node _T_4420 = add(_T_4419, ibuf_valid) @[el2_lsu_bus_buffer.scala 575:154] + node _T_4421 = neq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 575:190] + node _T_4422 = neq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 575:190] + node _T_4423 = neq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 575:190] + node _T_4424 = neq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 575:190] + node _T_4425 = add(_T_4421, _T_4422) @[el2_lsu_bus_buffer.scala 575:217] + node _T_4426 = add(_T_4425, _T_4423) @[el2_lsu_bus_buffer.scala 575:217] + node _T_4427 = add(_T_4426, _T_4424) @[el2_lsu_bus_buffer.scala 575:217] + node _T_4428 = add(_T_4420, _T_4427) @[el2_lsu_bus_buffer.scala 575:169] + node buf_numvld_any = tail(_T_4428, 1) @[el2_lsu_bus_buffer.scala 575:169] + node _T_4429 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 576:60] + node _T_4430 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 576:79] + node _T_4431 = and(_T_4429, _T_4430) @[el2_lsu_bus_buffer.scala 576:64] + node _T_4432 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 576:91] + node _T_4433 = and(_T_4431, _T_4432) @[el2_lsu_bus_buffer.scala 576:89] + node _T_4434 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 576:60] + node _T_4435 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 576:79] + node _T_4436 = and(_T_4434, _T_4435) @[el2_lsu_bus_buffer.scala 576:64] + node _T_4437 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 576:91] + node _T_4438 = and(_T_4436, _T_4437) @[el2_lsu_bus_buffer.scala 576:89] + node _T_4439 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 576:60] + node _T_4440 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 576:79] + node _T_4441 = and(_T_4439, _T_4440) @[el2_lsu_bus_buffer.scala 576:64] + node _T_4442 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 576:91] + node _T_4443 = and(_T_4441, _T_4442) @[el2_lsu_bus_buffer.scala 576:89] + node _T_4444 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 576:60] + node _T_4445 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 576:79] + node _T_4446 = and(_T_4444, _T_4445) @[el2_lsu_bus_buffer.scala 576:64] + node _T_4447 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 576:91] + node _T_4448 = and(_T_4446, _T_4447) @[el2_lsu_bus_buffer.scala 576:89] + node _T_4449 = add(_T_4448, _T_4443) @[el2_lsu_bus_buffer.scala 576:142] + node _T_4450 = add(_T_4449, _T_4438) @[el2_lsu_bus_buffer.scala 576:142] + node _T_4451 = add(_T_4450, _T_4433) @[el2_lsu_bus_buffer.scala 576:142] + buf_numvld_wrcmd_any <= _T_4451 @[el2_lsu_bus_buffer.scala 576:24] + node _T_4452 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 577:63] + node _T_4453 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 577:75] + node _T_4454 = and(_T_4452, _T_4453) @[el2_lsu_bus_buffer.scala 577:73] + node _T_4455 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 577:63] + node _T_4456 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 577:75] + node _T_4457 = and(_T_4455, _T_4456) @[el2_lsu_bus_buffer.scala 577:73] + node _T_4458 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 577:63] + node _T_4459 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 577:75] + node _T_4460 = and(_T_4458, _T_4459) @[el2_lsu_bus_buffer.scala 577:73] + node _T_4461 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 577:63] + node _T_4462 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 577:75] + node _T_4463 = and(_T_4461, _T_4462) @[el2_lsu_bus_buffer.scala 577:73] + node _T_4464 = add(_T_4463, _T_4460) @[el2_lsu_bus_buffer.scala 577:126] + node _T_4465 = add(_T_4464, _T_4457) @[el2_lsu_bus_buffer.scala 577:126] + node _T_4466 = add(_T_4465, _T_4454) @[el2_lsu_bus_buffer.scala 577:126] + buf_numvld_cmd_any <= _T_4466 @[el2_lsu_bus_buffer.scala 577:22] + node _T_4467 = eq(buf_state[0], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 578:63] + node _T_4468 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 578:90] + node _T_4469 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 578:102] + node _T_4470 = and(_T_4468, _T_4469) @[el2_lsu_bus_buffer.scala 578:100] + node _T_4471 = or(_T_4467, _T_4470) @[el2_lsu_bus_buffer.scala 578:74] + node _T_4472 = eq(buf_state[1], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 578:63] + node _T_4473 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 578:90] + node _T_4474 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 578:102] + node _T_4475 = and(_T_4473, _T_4474) @[el2_lsu_bus_buffer.scala 578:100] + node _T_4476 = or(_T_4472, _T_4475) @[el2_lsu_bus_buffer.scala 578:74] + node _T_4477 = eq(buf_state[2], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 578:63] + node _T_4478 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 578:90] + node _T_4479 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 578:102] + node _T_4480 = and(_T_4478, _T_4479) @[el2_lsu_bus_buffer.scala 578:100] + node _T_4481 = or(_T_4477, _T_4480) @[el2_lsu_bus_buffer.scala 578:74] + node _T_4482 = eq(buf_state[3], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 578:63] + node _T_4483 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 578:90] + node _T_4484 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 578:102] + node _T_4485 = and(_T_4483, _T_4484) @[el2_lsu_bus_buffer.scala 578:100] + node _T_4486 = or(_T_4482, _T_4485) @[el2_lsu_bus_buffer.scala 578:74] + node _T_4487 = add(_T_4486, _T_4481) @[el2_lsu_bus_buffer.scala 578:154] + node _T_4488 = add(_T_4487, _T_4476) @[el2_lsu_bus_buffer.scala 578:154] + node _T_4489 = add(_T_4488, _T_4471) @[el2_lsu_bus_buffer.scala 578:154] + buf_numvld_pend_any <= _T_4489 @[el2_lsu_bus_buffer.scala 578:23] + node _T_4490 = eq(buf_state[0], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 579:61] + node _T_4491 = eq(buf_state[1], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 579:61] + node _T_4492 = eq(buf_state[2], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 579:61] + node _T_4493 = eq(buf_state[3], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 579:61] + node _T_4494 = or(_T_4493, _T_4492) @[el2_lsu_bus_buffer.scala 579:93] + node _T_4495 = or(_T_4494, _T_4491) @[el2_lsu_bus_buffer.scala 579:93] + node _T_4496 = or(_T_4495, _T_4490) @[el2_lsu_bus_buffer.scala 579:93] + any_done_wait_state <= _T_4496 @[el2_lsu_bus_buffer.scala 579:23] + node _T_4497 = orr(buf_numvld_pend_any) @[el2_lsu_bus_buffer.scala 580:53] + io.lsu_bus_buffer_pend_any <= _T_4497 @[el2_lsu_bus_buffer.scala 580:30] + node _T_4498 = and(io.ldst_dual_d, io.dec_lsu_valid_raw_d) @[el2_lsu_bus_buffer.scala 581:52] + node _T_4499 = geq(buf_numvld_any, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 581:92] + node _T_4500 = eq(buf_numvld_any, UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 581:121] + node _T_4501 = mux(_T_4498, _T_4499, _T_4500) @[el2_lsu_bus_buffer.scala 581:36] + io.lsu_bus_buffer_full_any <= _T_4501 @[el2_lsu_bus_buffer.scala 581:30] + node _T_4502 = orr(buf_state[0]) @[el2_lsu_bus_buffer.scala 582:52] + node _T_4503 = orr(buf_state[1]) @[el2_lsu_bus_buffer.scala 582:52] + node _T_4504 = orr(buf_state[2]) @[el2_lsu_bus_buffer.scala 582:52] + node _T_4505 = orr(buf_state[3]) @[el2_lsu_bus_buffer.scala 582:52] + node _T_4506 = or(_T_4502, _T_4503) @[el2_lsu_bus_buffer.scala 582:65] + node _T_4507 = or(_T_4506, _T_4504) @[el2_lsu_bus_buffer.scala 582:65] + node _T_4508 = or(_T_4507, _T_4505) @[el2_lsu_bus_buffer.scala 582:65] + node _T_4509 = eq(_T_4508, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 582:34] + node _T_4510 = eq(ibuf_valid, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 582:72] + node _T_4511 = and(_T_4509, _T_4510) @[el2_lsu_bus_buffer.scala 582:70] + node _T_4512 = eq(obuf_valid, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 582:86] + node _T_4513 = and(_T_4511, _T_4512) @[el2_lsu_bus_buffer.scala 582:84] + io.lsu_bus_buffer_empty_any <= _T_4513 @[el2_lsu_bus_buffer.scala 582:31] + node _T_4514 = and(io.lsu_busreq_m, io.lsu_pkt_m.valid) @[el2_lsu_bus_buffer.scala 584:51] + node _T_4515 = and(_T_4514, io.lsu_pkt_m.bits.load) @[el2_lsu_bus_buffer.scala 584:72] + node _T_4516 = eq(io.flush_m_up, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 584:99] + node _T_4517 = and(_T_4515, _T_4516) @[el2_lsu_bus_buffer.scala 584:97] + node _T_4518 = eq(io.ld_full_hit_m, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 584:116] + node _T_4519 = and(_T_4517, _T_4518) @[el2_lsu_bus_buffer.scala 584:114] + io.lsu_nonblock_load_valid_m <= _T_4519 @[el2_lsu_bus_buffer.scala 584:32] + io.lsu_nonblock_load_tag_m <= WrPtr0_m @[el2_lsu_bus_buffer.scala 585:30] wire lsu_nonblock_load_valid_r : UInt<1> lsu_nonblock_load_valid_r <= UInt<1>("h00") - node _T_4520 = eq(io.lsu_commit_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 586:61] - node _T_4521 = and(lsu_nonblock_load_valid_r, _T_4520) @[el2_lsu_bus_buffer.scala 586:59] - io.lsu_nonblock_load_inv_r <= _T_4521 @[el2_lsu_bus_buffer.scala 586:30] - io.lsu_nonblock_load_inv_tag_r <= WrPtr0_r @[el2_lsu_bus_buffer.scala 587:34] - node _T_4522 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 588:80] - node _T_4523 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 588:127] - node _T_4524 = and(UInt<1>("h01"), _T_4523) @[el2_lsu_bus_buffer.scala 588:116] - node _T_4525 = eq(_T_4524, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 588:95] - node _T_4526 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 588:80] - node _T_4527 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 588:127] - node _T_4528 = and(UInt<1>("h01"), _T_4527) @[el2_lsu_bus_buffer.scala 588:116] - node _T_4529 = eq(_T_4528, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 588:95] - node _T_4530 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 588:80] - node _T_4531 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 588:127] - node _T_4532 = and(UInt<1>("h01"), _T_4531) @[el2_lsu_bus_buffer.scala 588:116] - node _T_4533 = eq(_T_4532, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 588:95] - node _T_4534 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 588:80] - node _T_4535 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 588:127] - node _T_4536 = and(UInt<1>("h01"), _T_4535) @[el2_lsu_bus_buffer.scala 588:116] - node _T_4537 = eq(_T_4536, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 588:95] + node _T_4520 = eq(io.lsu_commit_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 587:61] + node _T_4521 = and(lsu_nonblock_load_valid_r, _T_4520) @[el2_lsu_bus_buffer.scala 587:59] + io.lsu_nonblock_load_inv_r <= _T_4521 @[el2_lsu_bus_buffer.scala 587:30] + io.lsu_nonblock_load_inv_tag_r <= WrPtr0_r @[el2_lsu_bus_buffer.scala 588:34] + node _T_4522 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 589:80] + node _T_4523 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 589:127] + node _T_4524 = and(UInt<1>("h01"), _T_4523) @[el2_lsu_bus_buffer.scala 589:116] + node _T_4525 = eq(_T_4524, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 589:95] + node _T_4526 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 589:80] + node _T_4527 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 589:127] + node _T_4528 = and(UInt<1>("h01"), _T_4527) @[el2_lsu_bus_buffer.scala 589:116] + node _T_4529 = eq(_T_4528, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 589:95] + node _T_4530 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 589:80] + node _T_4531 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 589:127] + node _T_4532 = and(UInt<1>("h01"), _T_4531) @[el2_lsu_bus_buffer.scala 589:116] + node _T_4533 = eq(_T_4532, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 589:95] + node _T_4534 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 589:80] + node _T_4535 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 589:127] + node _T_4536 = and(UInt<1>("h01"), _T_4535) @[el2_lsu_bus_buffer.scala 589:116] + node _T_4537 = eq(_T_4536, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 589:95] node _T_4538 = mux(_T_4522, _T_4525, UInt<1>("h00")) @[Mux.scala 27:72] node _T_4539 = mux(_T_4526, _T_4529, UInt<1>("h00")) @[Mux.scala 27:72] node _T_4540 = mux(_T_4530, _T_4533, UInt<1>("h00")) @[Mux.scala 27:72] @@ -5981,26 +5979,26 @@ circuit el2_lsu_bus_intf : node _T_4544 = or(_T_4543, _T_4541) @[Mux.scala 27:72] wire lsu_nonblock_load_data_ready : UInt<1> @[Mux.scala 27:72] lsu_nonblock_load_data_ready <= _T_4544 @[Mux.scala 27:72] - node _T_4545 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 589:80] - node _T_4546 = bits(buf_error, 0, 0) @[el2_lsu_bus_buffer.scala 589:104] - node _T_4547 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 589:120] - node _T_4548 = eq(_T_4547, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 589:110] - node _T_4549 = and(_T_4546, _T_4548) @[el2_lsu_bus_buffer.scala 589:108] - node _T_4550 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 589:80] - node _T_4551 = bits(buf_error, 1, 1) @[el2_lsu_bus_buffer.scala 589:104] - node _T_4552 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 589:120] - node _T_4553 = eq(_T_4552, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 589:110] - node _T_4554 = and(_T_4551, _T_4553) @[el2_lsu_bus_buffer.scala 589:108] - node _T_4555 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 589:80] - node _T_4556 = bits(buf_error, 2, 2) @[el2_lsu_bus_buffer.scala 589:104] - node _T_4557 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 589:120] - node _T_4558 = eq(_T_4557, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 589:110] - node _T_4559 = and(_T_4556, _T_4558) @[el2_lsu_bus_buffer.scala 589:108] - node _T_4560 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 589:80] - node _T_4561 = bits(buf_error, 3, 3) @[el2_lsu_bus_buffer.scala 589:104] - node _T_4562 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 589:120] - node _T_4563 = eq(_T_4562, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 589:110] - node _T_4564 = and(_T_4561, _T_4563) @[el2_lsu_bus_buffer.scala 589:108] + node _T_4545 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 590:80] + node _T_4546 = bits(buf_error, 0, 0) @[el2_lsu_bus_buffer.scala 590:104] + node _T_4547 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 590:120] + node _T_4548 = eq(_T_4547, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 590:110] + node _T_4549 = and(_T_4546, _T_4548) @[el2_lsu_bus_buffer.scala 590:108] + node _T_4550 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 590:80] + node _T_4551 = bits(buf_error, 1, 1) @[el2_lsu_bus_buffer.scala 590:104] + node _T_4552 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 590:120] + node _T_4553 = eq(_T_4552, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 590:110] + node _T_4554 = and(_T_4551, _T_4553) @[el2_lsu_bus_buffer.scala 590:108] + node _T_4555 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 590:80] + node _T_4556 = bits(buf_error, 2, 2) @[el2_lsu_bus_buffer.scala 590:104] + node _T_4557 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 590:120] + node _T_4558 = eq(_T_4557, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 590:110] + node _T_4559 = and(_T_4556, _T_4558) @[el2_lsu_bus_buffer.scala 590:108] + node _T_4560 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 590:80] + node _T_4561 = bits(buf_error, 3, 3) @[el2_lsu_bus_buffer.scala 590:104] + node _T_4562 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 590:120] + node _T_4563 = eq(_T_4562, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 590:110] + node _T_4564 = and(_T_4561, _T_4563) @[el2_lsu_bus_buffer.scala 590:108] node _T_4565 = mux(_T_4545, _T_4549, UInt<1>("h00")) @[Mux.scala 27:72] node _T_4566 = mux(_T_4550, _T_4554, UInt<1>("h00")) @[Mux.scala 27:72] node _T_4567 = mux(_T_4555, _T_4559, UInt<1>("h00")) @[Mux.scala 27:72] @@ -6010,39 +6008,39 @@ circuit el2_lsu_bus_intf : node _T_4571 = or(_T_4570, _T_4568) @[Mux.scala 27:72] wire _T_4572 : UInt<1> @[Mux.scala 27:72] _T_4572 <= _T_4571 @[Mux.scala 27:72] - io.lsu_nonblock_load_data_error <= _T_4572 @[el2_lsu_bus_buffer.scala 589:35] - node _T_4573 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 590:79] - node _T_4574 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 590:102] - node _T_4575 = eq(_T_4574, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 590:92] - node _T_4576 = and(_T_4573, _T_4575) @[el2_lsu_bus_buffer.scala 590:90] - node _T_4577 = eq(buf_dual[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 590:109] - node _T_4578 = eq(buf_dualhi[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 590:124] - node _T_4579 = or(_T_4577, _T_4578) @[el2_lsu_bus_buffer.scala 590:122] - node _T_4580 = and(_T_4576, _T_4579) @[el2_lsu_bus_buffer.scala 590:106] - node _T_4581 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 590:79] - node _T_4582 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 590:102] - node _T_4583 = eq(_T_4582, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 590:92] - node _T_4584 = and(_T_4581, _T_4583) @[el2_lsu_bus_buffer.scala 590:90] - node _T_4585 = eq(buf_dual[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 590:109] - node _T_4586 = eq(buf_dualhi[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 590:124] - node _T_4587 = or(_T_4585, _T_4586) @[el2_lsu_bus_buffer.scala 590:122] - node _T_4588 = and(_T_4584, _T_4587) @[el2_lsu_bus_buffer.scala 590:106] - node _T_4589 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 590:79] - node _T_4590 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 590:102] - node _T_4591 = eq(_T_4590, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 590:92] - node _T_4592 = and(_T_4589, _T_4591) @[el2_lsu_bus_buffer.scala 590:90] - node _T_4593 = eq(buf_dual[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 590:109] - node _T_4594 = eq(buf_dualhi[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 590:124] - node _T_4595 = or(_T_4593, _T_4594) @[el2_lsu_bus_buffer.scala 590:122] - node _T_4596 = and(_T_4592, _T_4595) @[el2_lsu_bus_buffer.scala 590:106] - node _T_4597 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 590:79] - node _T_4598 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 590:102] - node _T_4599 = eq(_T_4598, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 590:92] - node _T_4600 = and(_T_4597, _T_4599) @[el2_lsu_bus_buffer.scala 590:90] - node _T_4601 = eq(buf_dual[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 590:109] - node _T_4602 = eq(buf_dualhi[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 590:124] - node _T_4603 = or(_T_4601, _T_4602) @[el2_lsu_bus_buffer.scala 590:122] - node _T_4604 = and(_T_4600, _T_4603) @[el2_lsu_bus_buffer.scala 590:106] + io.lsu_nonblock_load_data_error <= _T_4572 @[el2_lsu_bus_buffer.scala 590:35] + node _T_4573 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 591:79] + node _T_4574 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 591:102] + node _T_4575 = eq(_T_4574, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:92] + node _T_4576 = and(_T_4573, _T_4575) @[el2_lsu_bus_buffer.scala 591:90] + node _T_4577 = eq(buf_dual[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:109] + node _T_4578 = eq(buf_dualhi[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:124] + node _T_4579 = or(_T_4577, _T_4578) @[el2_lsu_bus_buffer.scala 591:122] + node _T_4580 = and(_T_4576, _T_4579) @[el2_lsu_bus_buffer.scala 591:106] + node _T_4581 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 591:79] + node _T_4582 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 591:102] + node _T_4583 = eq(_T_4582, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:92] + node _T_4584 = and(_T_4581, _T_4583) @[el2_lsu_bus_buffer.scala 591:90] + node _T_4585 = eq(buf_dual[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:109] + node _T_4586 = eq(buf_dualhi[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:124] + node _T_4587 = or(_T_4585, _T_4586) @[el2_lsu_bus_buffer.scala 591:122] + node _T_4588 = and(_T_4584, _T_4587) @[el2_lsu_bus_buffer.scala 591:106] + node _T_4589 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 591:79] + node _T_4590 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 591:102] + node _T_4591 = eq(_T_4590, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:92] + node _T_4592 = and(_T_4589, _T_4591) @[el2_lsu_bus_buffer.scala 591:90] + node _T_4593 = eq(buf_dual[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:109] + node _T_4594 = eq(buf_dualhi[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:124] + node _T_4595 = or(_T_4593, _T_4594) @[el2_lsu_bus_buffer.scala 591:122] + node _T_4596 = and(_T_4592, _T_4595) @[el2_lsu_bus_buffer.scala 591:106] + node _T_4597 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 591:79] + node _T_4598 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 591:102] + node _T_4599 = eq(_T_4598, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:92] + node _T_4600 = and(_T_4597, _T_4599) @[el2_lsu_bus_buffer.scala 591:90] + node _T_4601 = eq(buf_dual[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:109] + node _T_4602 = eq(buf_dualhi[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:124] + node _T_4603 = or(_T_4601, _T_4602) @[el2_lsu_bus_buffer.scala 591:122] + node _T_4604 = and(_T_4600, _T_4603) @[el2_lsu_bus_buffer.scala 591:106] node _T_4605 = mux(_T_4580, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_4606 = mux(_T_4588, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_4607 = mux(_T_4596, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] @@ -6052,39 +6050,39 @@ circuit el2_lsu_bus_intf : node _T_4611 = or(_T_4610, _T_4608) @[Mux.scala 27:72] wire _T_4612 : UInt<2> @[Mux.scala 27:72] _T_4612 <= _T_4611 @[Mux.scala 27:72] - io.lsu_nonblock_load_data_tag <= _T_4612 @[el2_lsu_bus_buffer.scala 590:33] - node _T_4613 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 591:78] - node _T_4614 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 591:101] - node _T_4615 = eq(_T_4614, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:91] - node _T_4616 = and(_T_4613, _T_4615) @[el2_lsu_bus_buffer.scala 591:89] - node _T_4617 = eq(buf_dual[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:108] - node _T_4618 = eq(buf_dualhi[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:123] - node _T_4619 = or(_T_4617, _T_4618) @[el2_lsu_bus_buffer.scala 591:121] - node _T_4620 = and(_T_4616, _T_4619) @[el2_lsu_bus_buffer.scala 591:105] - node _T_4621 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 591:78] - node _T_4622 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 591:101] - node _T_4623 = eq(_T_4622, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:91] - node _T_4624 = and(_T_4621, _T_4623) @[el2_lsu_bus_buffer.scala 591:89] - node _T_4625 = eq(buf_dual[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:108] - node _T_4626 = eq(buf_dualhi[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:123] - node _T_4627 = or(_T_4625, _T_4626) @[el2_lsu_bus_buffer.scala 591:121] - node _T_4628 = and(_T_4624, _T_4627) @[el2_lsu_bus_buffer.scala 591:105] - node _T_4629 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 591:78] - node _T_4630 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 591:101] - node _T_4631 = eq(_T_4630, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:91] - node _T_4632 = and(_T_4629, _T_4631) @[el2_lsu_bus_buffer.scala 591:89] - node _T_4633 = eq(buf_dual[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:108] - node _T_4634 = eq(buf_dualhi[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:123] - node _T_4635 = or(_T_4633, _T_4634) @[el2_lsu_bus_buffer.scala 591:121] - node _T_4636 = and(_T_4632, _T_4635) @[el2_lsu_bus_buffer.scala 591:105] - node _T_4637 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 591:78] - node _T_4638 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 591:101] - node _T_4639 = eq(_T_4638, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:91] - node _T_4640 = and(_T_4637, _T_4639) @[el2_lsu_bus_buffer.scala 591:89] - node _T_4641 = eq(buf_dual[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:108] - node _T_4642 = eq(buf_dualhi[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:123] - node _T_4643 = or(_T_4641, _T_4642) @[el2_lsu_bus_buffer.scala 591:121] - node _T_4644 = and(_T_4640, _T_4643) @[el2_lsu_bus_buffer.scala 591:105] + io.lsu_nonblock_load_data_tag <= _T_4612 @[el2_lsu_bus_buffer.scala 591:33] + node _T_4613 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 592:78] + node _T_4614 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 592:101] + node _T_4615 = eq(_T_4614, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 592:91] + node _T_4616 = and(_T_4613, _T_4615) @[el2_lsu_bus_buffer.scala 592:89] + node _T_4617 = eq(buf_dual[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 592:108] + node _T_4618 = eq(buf_dualhi[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 592:123] + node _T_4619 = or(_T_4617, _T_4618) @[el2_lsu_bus_buffer.scala 592:121] + node _T_4620 = and(_T_4616, _T_4619) @[el2_lsu_bus_buffer.scala 592:105] + node _T_4621 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 592:78] + node _T_4622 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 592:101] + node _T_4623 = eq(_T_4622, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 592:91] + node _T_4624 = and(_T_4621, _T_4623) @[el2_lsu_bus_buffer.scala 592:89] + node _T_4625 = eq(buf_dual[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 592:108] + node _T_4626 = eq(buf_dualhi[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 592:123] + node _T_4627 = or(_T_4625, _T_4626) @[el2_lsu_bus_buffer.scala 592:121] + node _T_4628 = and(_T_4624, _T_4627) @[el2_lsu_bus_buffer.scala 592:105] + node _T_4629 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 592:78] + node _T_4630 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 592:101] + node _T_4631 = eq(_T_4630, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 592:91] + node _T_4632 = and(_T_4629, _T_4631) @[el2_lsu_bus_buffer.scala 592:89] + node _T_4633 = eq(buf_dual[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 592:108] + node _T_4634 = eq(buf_dualhi[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 592:123] + node _T_4635 = or(_T_4633, _T_4634) @[el2_lsu_bus_buffer.scala 592:121] + node _T_4636 = and(_T_4632, _T_4635) @[el2_lsu_bus_buffer.scala 592:105] + node _T_4637 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 592:78] + node _T_4638 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 592:101] + node _T_4639 = eq(_T_4638, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 592:91] + node _T_4640 = and(_T_4637, _T_4639) @[el2_lsu_bus_buffer.scala 592:89] + node _T_4641 = eq(buf_dual[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 592:108] + node _T_4642 = eq(buf_dualhi[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 592:123] + node _T_4643 = or(_T_4641, _T_4642) @[el2_lsu_bus_buffer.scala 592:121] + node _T_4644 = and(_T_4640, _T_4643) @[el2_lsu_bus_buffer.scala 592:105] node _T_4645 = mux(_T_4620, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_4646 = mux(_T_4628, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_4647 = mux(_T_4636, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] @@ -6094,30 +6092,30 @@ circuit el2_lsu_bus_intf : node _T_4651 = or(_T_4650, _T_4648) @[Mux.scala 27:72] wire lsu_nonblock_load_data_lo : UInt<32> @[Mux.scala 27:72] lsu_nonblock_load_data_lo <= _T_4651 @[Mux.scala 27:72] - node _T_4652 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 592:78] - node _T_4653 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 592:101] - node _T_4654 = eq(_T_4653, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 592:91] - node _T_4655 = and(_T_4652, _T_4654) @[el2_lsu_bus_buffer.scala 592:89] - node _T_4656 = and(buf_dual[0], buf_dualhi[0]) @[el2_lsu_bus_buffer.scala 592:120] - node _T_4657 = and(_T_4655, _T_4656) @[el2_lsu_bus_buffer.scala 592:105] - node _T_4658 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 592:78] - node _T_4659 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 592:101] - node _T_4660 = eq(_T_4659, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 592:91] - node _T_4661 = and(_T_4658, _T_4660) @[el2_lsu_bus_buffer.scala 592:89] - node _T_4662 = and(buf_dual[1], buf_dualhi[1]) @[el2_lsu_bus_buffer.scala 592:120] - node _T_4663 = and(_T_4661, _T_4662) @[el2_lsu_bus_buffer.scala 592:105] - node _T_4664 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 592:78] - node _T_4665 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 592:101] - node _T_4666 = eq(_T_4665, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 592:91] - node _T_4667 = and(_T_4664, _T_4666) @[el2_lsu_bus_buffer.scala 592:89] - node _T_4668 = and(buf_dual[2], buf_dualhi[2]) @[el2_lsu_bus_buffer.scala 592:120] - node _T_4669 = and(_T_4667, _T_4668) @[el2_lsu_bus_buffer.scala 592:105] - node _T_4670 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 592:78] - node _T_4671 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 592:101] - node _T_4672 = eq(_T_4671, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 592:91] - node _T_4673 = and(_T_4670, _T_4672) @[el2_lsu_bus_buffer.scala 592:89] - node _T_4674 = and(buf_dual[3], buf_dualhi[3]) @[el2_lsu_bus_buffer.scala 592:120] - node _T_4675 = and(_T_4673, _T_4674) @[el2_lsu_bus_buffer.scala 592:105] + node _T_4652 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 593:78] + node _T_4653 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 593:101] + node _T_4654 = eq(_T_4653, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 593:91] + node _T_4655 = and(_T_4652, _T_4654) @[el2_lsu_bus_buffer.scala 593:89] + node _T_4656 = and(buf_dual[0], buf_dualhi[0]) @[el2_lsu_bus_buffer.scala 593:120] + node _T_4657 = and(_T_4655, _T_4656) @[el2_lsu_bus_buffer.scala 593:105] + node _T_4658 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 593:78] + node _T_4659 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 593:101] + node _T_4660 = eq(_T_4659, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 593:91] + node _T_4661 = and(_T_4658, _T_4660) @[el2_lsu_bus_buffer.scala 593:89] + node _T_4662 = and(buf_dual[1], buf_dualhi[1]) @[el2_lsu_bus_buffer.scala 593:120] + node _T_4663 = and(_T_4661, _T_4662) @[el2_lsu_bus_buffer.scala 593:105] + node _T_4664 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 593:78] + node _T_4665 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 593:101] + node _T_4666 = eq(_T_4665, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 593:91] + node _T_4667 = and(_T_4664, _T_4666) @[el2_lsu_bus_buffer.scala 593:89] + node _T_4668 = and(buf_dual[2], buf_dualhi[2]) @[el2_lsu_bus_buffer.scala 593:120] + node _T_4669 = and(_T_4667, _T_4668) @[el2_lsu_bus_buffer.scala 593:105] + node _T_4670 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 593:78] + node _T_4671 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 593:101] + node _T_4672 = eq(_T_4671, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 593:91] + node _T_4673 = and(_T_4670, _T_4672) @[el2_lsu_bus_buffer.scala 593:89] + node _T_4674 = and(buf_dual[3], buf_dualhi[3]) @[el2_lsu_bus_buffer.scala 593:120] + node _T_4675 = and(_T_4673, _T_4674) @[el2_lsu_bus_buffer.scala 593:105] node _T_4676 = mux(_T_4657, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_4677 = mux(_T_4663, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_4678 = mux(_T_4669, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] @@ -6140,7 +6138,7 @@ circuit el2_lsu_bus_intf : node _T_4693 = or(_T_4692, _T_4690) @[Mux.scala 27:72] wire _T_4694 : UInt<32> @[Mux.scala 27:72] _T_4694 <= _T_4693 @[Mux.scala 27:72] - node lsu_nonblock_addr_offset = bits(_T_4694, 1, 0) @[el2_lsu_bus_buffer.scala 593:83] + node lsu_nonblock_addr_offset = bits(_T_4694, 1, 0) @[el2_lsu_bus_buffer.scala 594:83] node _T_4695 = eq(io.lsu_nonblock_load_data_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] node _T_4696 = eq(io.lsu_nonblock_load_data_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] node _T_4697 = eq(io.lsu_nonblock_load_data_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] @@ -6192,36 +6190,36 @@ circuit el2_lsu_bus_intf : wire lsu_nonblock_dual : UInt<1> @[Mux.scala 27:72] lsu_nonblock_dual <= _T_4738 @[Mux.scala 27:72] node _T_4739 = cat(lsu_nonblock_load_data_hi, lsu_nonblock_load_data_lo) @[Cat.scala 29:58] - node _T_4740 = mul(lsu_nonblock_addr_offset, UInt<4>("h08")) @[el2_lsu_bus_buffer.scala 597:121] - node lsu_nonblock_data_unalgn = dshr(_T_4739, _T_4740) @[el2_lsu_bus_buffer.scala 597:92] - node _T_4741 = eq(io.lsu_nonblock_load_data_error, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 599:69] - node _T_4742 = and(lsu_nonblock_load_data_ready, _T_4741) @[el2_lsu_bus_buffer.scala 599:67] - io.lsu_nonblock_load_data_valid <= _T_4742 @[el2_lsu_bus_buffer.scala 599:35] - node _T_4743 = eq(lsu_nonblock_sz, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 600:81] - node _T_4744 = and(lsu_nonblock_unsign, _T_4743) @[el2_lsu_bus_buffer.scala 600:63] - node _T_4745 = bits(lsu_nonblock_data_unalgn, 7, 0) @[el2_lsu_bus_buffer.scala 600:131] + node _T_4740 = mul(lsu_nonblock_addr_offset, UInt<4>("h08")) @[el2_lsu_bus_buffer.scala 598:121] + node lsu_nonblock_data_unalgn = dshr(_T_4739, _T_4740) @[el2_lsu_bus_buffer.scala 598:92] + node _T_4741 = eq(io.lsu_nonblock_load_data_error, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 600:69] + node _T_4742 = and(lsu_nonblock_load_data_ready, _T_4741) @[el2_lsu_bus_buffer.scala 600:67] + io.lsu_nonblock_load_data_valid <= _T_4742 @[el2_lsu_bus_buffer.scala 600:35] + node _T_4743 = eq(lsu_nonblock_sz, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 601:81] + node _T_4744 = and(lsu_nonblock_unsign, _T_4743) @[el2_lsu_bus_buffer.scala 601:63] + node _T_4745 = bits(lsu_nonblock_data_unalgn, 7, 0) @[el2_lsu_bus_buffer.scala 601:131] node _T_4746 = cat(UInt<24>("h00"), _T_4745) @[Cat.scala 29:58] - node _T_4747 = eq(lsu_nonblock_sz, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 601:45] - node _T_4748 = and(lsu_nonblock_unsign, _T_4747) @[el2_lsu_bus_buffer.scala 601:26] - node _T_4749 = bits(lsu_nonblock_data_unalgn, 15, 0) @[el2_lsu_bus_buffer.scala 601:95] + node _T_4747 = eq(lsu_nonblock_sz, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 602:45] + node _T_4748 = and(lsu_nonblock_unsign, _T_4747) @[el2_lsu_bus_buffer.scala 602:26] + node _T_4749 = bits(lsu_nonblock_data_unalgn, 15, 0) @[el2_lsu_bus_buffer.scala 602:95] node _T_4750 = cat(UInt<16>("h00"), _T_4749) @[Cat.scala 29:58] - node _T_4751 = eq(lsu_nonblock_unsign, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 602:6] - node _T_4752 = eq(lsu_nonblock_sz, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 602:45] - node _T_4753 = and(_T_4751, _T_4752) @[el2_lsu_bus_buffer.scala 602:27] - node _T_4754 = bits(lsu_nonblock_data_unalgn, 7, 7) @[el2_lsu_bus_buffer.scala 602:93] + node _T_4751 = eq(lsu_nonblock_unsign, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 603:6] + node _T_4752 = eq(lsu_nonblock_sz, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 603:45] + node _T_4753 = and(_T_4751, _T_4752) @[el2_lsu_bus_buffer.scala 603:27] + node _T_4754 = bits(lsu_nonblock_data_unalgn, 7, 7) @[el2_lsu_bus_buffer.scala 603:93] node _T_4755 = bits(_T_4754, 0, 0) @[Bitwise.scala 72:15] node _T_4756 = mux(_T_4755, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12] - node _T_4757 = bits(lsu_nonblock_data_unalgn, 7, 0) @[el2_lsu_bus_buffer.scala 602:123] + node _T_4757 = bits(lsu_nonblock_data_unalgn, 7, 0) @[el2_lsu_bus_buffer.scala 603:123] node _T_4758 = cat(_T_4756, _T_4757) @[Cat.scala 29:58] - node _T_4759 = eq(lsu_nonblock_unsign, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 603:6] - node _T_4760 = eq(lsu_nonblock_sz, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 603:45] - node _T_4761 = and(_T_4759, _T_4760) @[el2_lsu_bus_buffer.scala 603:27] - node _T_4762 = bits(lsu_nonblock_data_unalgn, 15, 15) @[el2_lsu_bus_buffer.scala 603:93] + node _T_4759 = eq(lsu_nonblock_unsign, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 604:6] + node _T_4760 = eq(lsu_nonblock_sz, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 604:45] + node _T_4761 = and(_T_4759, _T_4760) @[el2_lsu_bus_buffer.scala 604:27] + node _T_4762 = bits(lsu_nonblock_data_unalgn, 15, 15) @[el2_lsu_bus_buffer.scala 604:93] node _T_4763 = bits(_T_4762, 0, 0) @[Bitwise.scala 72:15] node _T_4764 = mux(_T_4763, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12] - node _T_4765 = bits(lsu_nonblock_data_unalgn, 15, 0) @[el2_lsu_bus_buffer.scala 603:124] + node _T_4765 = bits(lsu_nonblock_data_unalgn, 15, 0) @[el2_lsu_bus_buffer.scala 604:124] node _T_4766 = cat(_T_4764, _T_4765) @[Cat.scala 29:58] - node _T_4767 = eq(lsu_nonblock_sz, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 604:21] + node _T_4767 = eq(lsu_nonblock_sz, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 605:21] node _T_4768 = mux(_T_4744, _T_4746, UInt<1>("h00")) @[Mux.scala 27:72] node _T_4769 = mux(_T_4748, _T_4750, UInt<1>("h00")) @[Mux.scala 27:72] node _T_4770 = mux(_T_4753, _T_4758, UInt<1>("h00")) @[Mux.scala 27:72] @@ -6233,75 +6231,75 @@ circuit el2_lsu_bus_intf : node _T_4776 = or(_T_4775, _T_4772) @[Mux.scala 27:72] wire _T_4777 : UInt<64> @[Mux.scala 27:72] _T_4777 <= _T_4776 @[Mux.scala 27:72] - io.lsu_nonblock_load_data <= _T_4777 @[el2_lsu_bus_buffer.scala 600:29] - node _T_4778 = eq(buf_state[0], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 605:62] - node _T_4779 = bits(buf_sideeffect, 0, 0) @[el2_lsu_bus_buffer.scala 605:89] - node _T_4780 = and(_T_4778, _T_4779) @[el2_lsu_bus_buffer.scala 605:73] - node _T_4781 = and(_T_4780, io.dec_tlu_sideeffect_posted_disable) @[el2_lsu_bus_buffer.scala 605:93] - node _T_4782 = eq(buf_state[1], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 605:62] - node _T_4783 = bits(buf_sideeffect, 1, 1) @[el2_lsu_bus_buffer.scala 605:89] - node _T_4784 = and(_T_4782, _T_4783) @[el2_lsu_bus_buffer.scala 605:73] - node _T_4785 = and(_T_4784, io.dec_tlu_sideeffect_posted_disable) @[el2_lsu_bus_buffer.scala 605:93] - node _T_4786 = eq(buf_state[2], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 605:62] - node _T_4787 = bits(buf_sideeffect, 2, 2) @[el2_lsu_bus_buffer.scala 605:89] - node _T_4788 = and(_T_4786, _T_4787) @[el2_lsu_bus_buffer.scala 605:73] - node _T_4789 = and(_T_4788, io.dec_tlu_sideeffect_posted_disable) @[el2_lsu_bus_buffer.scala 605:93] - node _T_4790 = eq(buf_state[3], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 605:62] - node _T_4791 = bits(buf_sideeffect, 3, 3) @[el2_lsu_bus_buffer.scala 605:89] - node _T_4792 = and(_T_4790, _T_4791) @[el2_lsu_bus_buffer.scala 605:73] - node _T_4793 = and(_T_4792, io.dec_tlu_sideeffect_posted_disable) @[el2_lsu_bus_buffer.scala 605:93] - node _T_4794 = or(_T_4781, _T_4785) @[el2_lsu_bus_buffer.scala 605:141] - node _T_4795 = or(_T_4794, _T_4789) @[el2_lsu_bus_buffer.scala 605:141] - node _T_4796 = or(_T_4795, _T_4793) @[el2_lsu_bus_buffer.scala 605:141] - bus_sideeffect_pend <= _T_4796 @[el2_lsu_bus_buffer.scala 605:23] - node _T_4797 = eq(buf_state[0], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 606:71] - node _T_4798 = and(UInt<1>("h01"), obuf_valid) @[el2_lsu_bus_buffer.scala 607:25] - node _T_4799 = bits(obuf_addr, 31, 3) @[el2_lsu_bus_buffer.scala 607:50] - node _T_4800 = bits(buf_addr[0], 31, 3) @[el2_lsu_bus_buffer.scala 607:70] - node _T_4801 = eq(_T_4799, _T_4800) @[el2_lsu_bus_buffer.scala 607:56] - node _T_4802 = and(_T_4798, _T_4801) @[el2_lsu_bus_buffer.scala 607:38] - node _T_4803 = eq(obuf_tag0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 607:92] - node _T_4804 = eq(obuf_tag1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 607:126] - node _T_4805 = and(obuf_merge, _T_4804) @[el2_lsu_bus_buffer.scala 607:114] - node _T_4806 = or(_T_4803, _T_4805) @[el2_lsu_bus_buffer.scala 607:100] - node _T_4807 = eq(_T_4806, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 607:80] - node _T_4808 = and(_T_4802, _T_4807) @[el2_lsu_bus_buffer.scala 607:78] - node _T_4809 = eq(buf_state[1], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 606:71] - node _T_4810 = and(UInt<1>("h01"), obuf_valid) @[el2_lsu_bus_buffer.scala 607:25] - node _T_4811 = bits(obuf_addr, 31, 3) @[el2_lsu_bus_buffer.scala 607:50] - node _T_4812 = bits(buf_addr[1], 31, 3) @[el2_lsu_bus_buffer.scala 607:70] - node _T_4813 = eq(_T_4811, _T_4812) @[el2_lsu_bus_buffer.scala 607:56] - node _T_4814 = and(_T_4810, _T_4813) @[el2_lsu_bus_buffer.scala 607:38] - node _T_4815 = eq(obuf_tag0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 607:92] - node _T_4816 = eq(obuf_tag1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 607:126] - node _T_4817 = and(obuf_merge, _T_4816) @[el2_lsu_bus_buffer.scala 607:114] - node _T_4818 = or(_T_4815, _T_4817) @[el2_lsu_bus_buffer.scala 607:100] - node _T_4819 = eq(_T_4818, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 607:80] - node _T_4820 = and(_T_4814, _T_4819) @[el2_lsu_bus_buffer.scala 607:78] - node _T_4821 = eq(buf_state[2], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 606:71] - node _T_4822 = and(UInt<1>("h01"), obuf_valid) @[el2_lsu_bus_buffer.scala 607:25] - node _T_4823 = bits(obuf_addr, 31, 3) @[el2_lsu_bus_buffer.scala 607:50] - node _T_4824 = bits(buf_addr[2], 31, 3) @[el2_lsu_bus_buffer.scala 607:70] - node _T_4825 = eq(_T_4823, _T_4824) @[el2_lsu_bus_buffer.scala 607:56] - node _T_4826 = and(_T_4822, _T_4825) @[el2_lsu_bus_buffer.scala 607:38] - node _T_4827 = eq(obuf_tag0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 607:92] - node _T_4828 = eq(obuf_tag1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 607:126] - node _T_4829 = and(obuf_merge, _T_4828) @[el2_lsu_bus_buffer.scala 607:114] - node _T_4830 = or(_T_4827, _T_4829) @[el2_lsu_bus_buffer.scala 607:100] - node _T_4831 = eq(_T_4830, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 607:80] - node _T_4832 = and(_T_4826, _T_4831) @[el2_lsu_bus_buffer.scala 607:78] - node _T_4833 = eq(buf_state[3], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 606:71] - node _T_4834 = and(UInt<1>("h01"), obuf_valid) @[el2_lsu_bus_buffer.scala 607:25] - node _T_4835 = bits(obuf_addr, 31, 3) @[el2_lsu_bus_buffer.scala 607:50] - node _T_4836 = bits(buf_addr[3], 31, 3) @[el2_lsu_bus_buffer.scala 607:70] - node _T_4837 = eq(_T_4835, _T_4836) @[el2_lsu_bus_buffer.scala 607:56] - node _T_4838 = and(_T_4834, _T_4837) @[el2_lsu_bus_buffer.scala 607:38] - node _T_4839 = eq(obuf_tag0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 607:92] - node _T_4840 = eq(obuf_tag1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 607:126] - node _T_4841 = and(obuf_merge, _T_4840) @[el2_lsu_bus_buffer.scala 607:114] - node _T_4842 = or(_T_4839, _T_4841) @[el2_lsu_bus_buffer.scala 607:100] - node _T_4843 = eq(_T_4842, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 607:80] - node _T_4844 = and(_T_4838, _T_4843) @[el2_lsu_bus_buffer.scala 607:78] + io.lsu_nonblock_load_data <= _T_4777 @[el2_lsu_bus_buffer.scala 601:29] + node _T_4778 = eq(buf_state[0], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 606:62] + node _T_4779 = bits(buf_sideeffect, 0, 0) @[el2_lsu_bus_buffer.scala 606:89] + node _T_4780 = and(_T_4778, _T_4779) @[el2_lsu_bus_buffer.scala 606:73] + node _T_4781 = and(_T_4780, io.dec_tlu_sideeffect_posted_disable) @[el2_lsu_bus_buffer.scala 606:93] + node _T_4782 = eq(buf_state[1], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 606:62] + node _T_4783 = bits(buf_sideeffect, 1, 1) @[el2_lsu_bus_buffer.scala 606:89] + node _T_4784 = and(_T_4782, _T_4783) @[el2_lsu_bus_buffer.scala 606:73] + node _T_4785 = and(_T_4784, io.dec_tlu_sideeffect_posted_disable) @[el2_lsu_bus_buffer.scala 606:93] + node _T_4786 = eq(buf_state[2], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 606:62] + node _T_4787 = bits(buf_sideeffect, 2, 2) @[el2_lsu_bus_buffer.scala 606:89] + node _T_4788 = and(_T_4786, _T_4787) @[el2_lsu_bus_buffer.scala 606:73] + node _T_4789 = and(_T_4788, io.dec_tlu_sideeffect_posted_disable) @[el2_lsu_bus_buffer.scala 606:93] + node _T_4790 = eq(buf_state[3], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 606:62] + node _T_4791 = bits(buf_sideeffect, 3, 3) @[el2_lsu_bus_buffer.scala 606:89] + node _T_4792 = and(_T_4790, _T_4791) @[el2_lsu_bus_buffer.scala 606:73] + node _T_4793 = and(_T_4792, io.dec_tlu_sideeffect_posted_disable) @[el2_lsu_bus_buffer.scala 606:93] + node _T_4794 = or(_T_4781, _T_4785) @[el2_lsu_bus_buffer.scala 606:141] + node _T_4795 = or(_T_4794, _T_4789) @[el2_lsu_bus_buffer.scala 606:141] + node _T_4796 = or(_T_4795, _T_4793) @[el2_lsu_bus_buffer.scala 606:141] + bus_sideeffect_pend <= _T_4796 @[el2_lsu_bus_buffer.scala 606:23] + node _T_4797 = eq(buf_state[0], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 607:71] + node _T_4798 = and(UInt<1>("h01"), obuf_valid) @[el2_lsu_bus_buffer.scala 608:25] + node _T_4799 = bits(obuf_addr, 31, 3) @[el2_lsu_bus_buffer.scala 608:50] + node _T_4800 = bits(buf_addr[0], 31, 3) @[el2_lsu_bus_buffer.scala 608:70] + node _T_4801 = eq(_T_4799, _T_4800) @[el2_lsu_bus_buffer.scala 608:56] + node _T_4802 = and(_T_4798, _T_4801) @[el2_lsu_bus_buffer.scala 608:38] + node _T_4803 = eq(obuf_tag0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 608:92] + node _T_4804 = eq(obuf_tag1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 608:126] + node _T_4805 = and(obuf_merge, _T_4804) @[el2_lsu_bus_buffer.scala 608:114] + node _T_4806 = or(_T_4803, _T_4805) @[el2_lsu_bus_buffer.scala 608:100] + node _T_4807 = eq(_T_4806, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 608:80] + node _T_4808 = and(_T_4802, _T_4807) @[el2_lsu_bus_buffer.scala 608:78] + node _T_4809 = eq(buf_state[1], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 607:71] + node _T_4810 = and(UInt<1>("h01"), obuf_valid) @[el2_lsu_bus_buffer.scala 608:25] + node _T_4811 = bits(obuf_addr, 31, 3) @[el2_lsu_bus_buffer.scala 608:50] + node _T_4812 = bits(buf_addr[1], 31, 3) @[el2_lsu_bus_buffer.scala 608:70] + node _T_4813 = eq(_T_4811, _T_4812) @[el2_lsu_bus_buffer.scala 608:56] + node _T_4814 = and(_T_4810, _T_4813) @[el2_lsu_bus_buffer.scala 608:38] + node _T_4815 = eq(obuf_tag0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 608:92] + node _T_4816 = eq(obuf_tag1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 608:126] + node _T_4817 = and(obuf_merge, _T_4816) @[el2_lsu_bus_buffer.scala 608:114] + node _T_4818 = or(_T_4815, _T_4817) @[el2_lsu_bus_buffer.scala 608:100] + node _T_4819 = eq(_T_4818, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 608:80] + node _T_4820 = and(_T_4814, _T_4819) @[el2_lsu_bus_buffer.scala 608:78] + node _T_4821 = eq(buf_state[2], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 607:71] + node _T_4822 = and(UInt<1>("h01"), obuf_valid) @[el2_lsu_bus_buffer.scala 608:25] + node _T_4823 = bits(obuf_addr, 31, 3) @[el2_lsu_bus_buffer.scala 608:50] + node _T_4824 = bits(buf_addr[2], 31, 3) @[el2_lsu_bus_buffer.scala 608:70] + node _T_4825 = eq(_T_4823, _T_4824) @[el2_lsu_bus_buffer.scala 608:56] + node _T_4826 = and(_T_4822, _T_4825) @[el2_lsu_bus_buffer.scala 608:38] + node _T_4827 = eq(obuf_tag0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 608:92] + node _T_4828 = eq(obuf_tag1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 608:126] + node _T_4829 = and(obuf_merge, _T_4828) @[el2_lsu_bus_buffer.scala 608:114] + node _T_4830 = or(_T_4827, _T_4829) @[el2_lsu_bus_buffer.scala 608:100] + node _T_4831 = eq(_T_4830, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 608:80] + node _T_4832 = and(_T_4826, _T_4831) @[el2_lsu_bus_buffer.scala 608:78] + node _T_4833 = eq(buf_state[3], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 607:71] + node _T_4834 = and(UInt<1>("h01"), obuf_valid) @[el2_lsu_bus_buffer.scala 608:25] + node _T_4835 = bits(obuf_addr, 31, 3) @[el2_lsu_bus_buffer.scala 608:50] + node _T_4836 = bits(buf_addr[3], 31, 3) @[el2_lsu_bus_buffer.scala 608:70] + node _T_4837 = eq(_T_4835, _T_4836) @[el2_lsu_bus_buffer.scala 608:56] + node _T_4838 = and(_T_4834, _T_4837) @[el2_lsu_bus_buffer.scala 608:38] + node _T_4839 = eq(obuf_tag0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 608:92] + node _T_4840 = eq(obuf_tag1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 608:126] + node _T_4841 = and(obuf_merge, _T_4840) @[el2_lsu_bus_buffer.scala 608:114] + node _T_4842 = or(_T_4839, _T_4841) @[el2_lsu_bus_buffer.scala 608:100] + node _T_4843 = eq(_T_4842, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 608:80] + node _T_4844 = and(_T_4838, _T_4843) @[el2_lsu_bus_buffer.scala 608:78] node _T_4845 = mux(_T_4797, _T_4808, UInt<1>("h00")) @[Mux.scala 27:72] node _T_4846 = mux(_T_4809, _T_4820, UInt<1>("h00")) @[Mux.scala 27:72] node _T_4847 = mux(_T_4821, _T_4832, UInt<1>("h00")) @[Mux.scala 27:72] @@ -6311,117 +6309,117 @@ circuit el2_lsu_bus_intf : node _T_4851 = or(_T_4850, _T_4848) @[Mux.scala 27:72] wire _T_4852 : UInt<1> @[Mux.scala 27:72] _T_4852 <= _T_4851 @[Mux.scala 27:72] - bus_addr_match_pending <= _T_4852 @[el2_lsu_bus_buffer.scala 606:26] - node _T_4853 = or(obuf_cmd_done, obuf_data_done) @[el2_lsu_bus_buffer.scala 609:54] - node _T_4854 = mux(obuf_cmd_done, io.lsu_axi_wready, io.lsu_axi_awready) @[el2_lsu_bus_buffer.scala 609:75] - node _T_4855 = and(io.lsu_axi_awready, io.lsu_axi_awready) @[el2_lsu_bus_buffer.scala 609:150] - node _T_4856 = mux(_T_4853, _T_4854, _T_4855) @[el2_lsu_bus_buffer.scala 609:39] - node _T_4857 = mux(obuf_write, _T_4856, io.lsu_axi_arready) @[el2_lsu_bus_buffer.scala 609:23] - bus_cmd_ready <= _T_4857 @[el2_lsu_bus_buffer.scala 609:17] - node _T_4858 = and(io.lsu_axi_awvalid, io.lsu_axi_awready) @[el2_lsu_bus_buffer.scala 610:39] - bus_wcmd_sent <= _T_4858 @[el2_lsu_bus_buffer.scala 610:17] - node _T_4859 = and(io.lsu_axi_wvalid, io.lsu_axi_wready) @[el2_lsu_bus_buffer.scala 611:39] - bus_wdata_sent <= _T_4859 @[el2_lsu_bus_buffer.scala 611:18] - node _T_4860 = or(obuf_cmd_done, bus_wcmd_sent) @[el2_lsu_bus_buffer.scala 612:35] - node _T_4861 = or(obuf_data_done, bus_wdata_sent) @[el2_lsu_bus_buffer.scala 612:70] - node _T_4862 = and(_T_4860, _T_4861) @[el2_lsu_bus_buffer.scala 612:52] - node _T_4863 = and(io.lsu_axi_arvalid, io.lsu_axi_arready) @[el2_lsu_bus_buffer.scala 612:111] - node _T_4864 = or(_T_4862, _T_4863) @[el2_lsu_bus_buffer.scala 612:89] - bus_cmd_sent <= _T_4864 @[el2_lsu_bus_buffer.scala 612:16] - node _T_4865 = and(io.lsu_axi_rvalid, io.lsu_axi_rready) @[el2_lsu_bus_buffer.scala 613:37] - bus_rsp_read <= _T_4865 @[el2_lsu_bus_buffer.scala 613:16] - node _T_4866 = and(io.lsu_axi_bvalid, io.lsu_axi_bready) @[el2_lsu_bus_buffer.scala 614:38] - bus_rsp_write <= _T_4866 @[el2_lsu_bus_buffer.scala 614:17] - bus_rsp_read_tag <= io.lsu_axi_rid @[el2_lsu_bus_buffer.scala 615:20] - bus_rsp_write_tag <= io.lsu_axi_bid @[el2_lsu_bus_buffer.scala 616:21] - node _T_4867 = neq(io.lsu_axi_bresp, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 617:60] - node _T_4868 = and(bus_rsp_write, _T_4867) @[el2_lsu_bus_buffer.scala 617:40] - bus_rsp_write_error <= _T_4868 @[el2_lsu_bus_buffer.scala 617:23] - node _T_4869 = neq(io.lsu_axi_bresp, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 618:58] - node _T_4870 = and(bus_rsp_read, _T_4869) @[el2_lsu_bus_buffer.scala 618:38] - bus_rsp_read_error <= _T_4870 @[el2_lsu_bus_buffer.scala 618:22] - bus_rsp_rdata <= io.lsu_axi_rdata @[el2_lsu_bus_buffer.scala 619:17] - node _T_4871 = and(obuf_valid, obuf_write) @[el2_lsu_bus_buffer.scala 622:36] - node _T_4872 = eq(obuf_cmd_done, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 622:51] - node _T_4873 = and(_T_4871, _T_4872) @[el2_lsu_bus_buffer.scala 622:49] - node _T_4874 = eq(bus_addr_match_pending, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 622:68] - node _T_4875 = and(_T_4873, _T_4874) @[el2_lsu_bus_buffer.scala 622:66] - io.lsu_axi_awvalid <= _T_4875 @[el2_lsu_bus_buffer.scala 622:22] - io.lsu_axi_awid <= obuf_tag0 @[el2_lsu_bus_buffer.scala 623:19] - node _T_4876 = bits(obuf_addr, 31, 3) @[el2_lsu_bus_buffer.scala 624:69] + bus_addr_match_pending <= _T_4852 @[el2_lsu_bus_buffer.scala 607:26] + node _T_4853 = or(obuf_cmd_done, obuf_data_done) @[el2_lsu_bus_buffer.scala 610:54] + node _T_4854 = mux(obuf_cmd_done, io.lsu_axi_wready, io.lsu_axi_awready) @[el2_lsu_bus_buffer.scala 610:75] + node _T_4855 = and(io.lsu_axi_awready, io.lsu_axi_awready) @[el2_lsu_bus_buffer.scala 610:150] + node _T_4856 = mux(_T_4853, _T_4854, _T_4855) @[el2_lsu_bus_buffer.scala 610:39] + node _T_4857 = mux(obuf_write, _T_4856, io.lsu_axi_arready) @[el2_lsu_bus_buffer.scala 610:23] + bus_cmd_ready <= _T_4857 @[el2_lsu_bus_buffer.scala 610:17] + node _T_4858 = and(io.lsu_axi_awvalid, io.lsu_axi_awready) @[el2_lsu_bus_buffer.scala 611:39] + bus_wcmd_sent <= _T_4858 @[el2_lsu_bus_buffer.scala 611:17] + node _T_4859 = and(io.lsu_axi_wvalid, io.lsu_axi_wready) @[el2_lsu_bus_buffer.scala 612:39] + bus_wdata_sent <= _T_4859 @[el2_lsu_bus_buffer.scala 612:18] + node _T_4860 = or(obuf_cmd_done, bus_wcmd_sent) @[el2_lsu_bus_buffer.scala 613:35] + node _T_4861 = or(obuf_data_done, bus_wdata_sent) @[el2_lsu_bus_buffer.scala 613:70] + node _T_4862 = and(_T_4860, _T_4861) @[el2_lsu_bus_buffer.scala 613:52] + node _T_4863 = and(io.lsu_axi_arvalid, io.lsu_axi_arready) @[el2_lsu_bus_buffer.scala 613:111] + node _T_4864 = or(_T_4862, _T_4863) @[el2_lsu_bus_buffer.scala 613:89] + bus_cmd_sent <= _T_4864 @[el2_lsu_bus_buffer.scala 613:16] + node _T_4865 = and(io.lsu_axi_rvalid, io.lsu_axi_rready) @[el2_lsu_bus_buffer.scala 614:37] + bus_rsp_read <= _T_4865 @[el2_lsu_bus_buffer.scala 614:16] + node _T_4866 = and(io.lsu_axi_bvalid, io.lsu_axi_bready) @[el2_lsu_bus_buffer.scala 615:38] + bus_rsp_write <= _T_4866 @[el2_lsu_bus_buffer.scala 615:17] + bus_rsp_read_tag <= io.lsu_axi_rid @[el2_lsu_bus_buffer.scala 616:20] + bus_rsp_write_tag <= io.lsu_axi_bid @[el2_lsu_bus_buffer.scala 617:21] + node _T_4867 = neq(io.lsu_axi_bresp, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 618:60] + node _T_4868 = and(bus_rsp_write, _T_4867) @[el2_lsu_bus_buffer.scala 618:40] + bus_rsp_write_error <= _T_4868 @[el2_lsu_bus_buffer.scala 618:23] + node _T_4869 = neq(io.lsu_axi_bresp, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 619:58] + node _T_4870 = and(bus_rsp_read, _T_4869) @[el2_lsu_bus_buffer.scala 619:38] + bus_rsp_read_error <= _T_4870 @[el2_lsu_bus_buffer.scala 619:22] + bus_rsp_rdata <= io.lsu_axi_rdata @[el2_lsu_bus_buffer.scala 620:17] + node _T_4871 = and(obuf_valid, obuf_write) @[el2_lsu_bus_buffer.scala 623:36] + node _T_4872 = eq(obuf_cmd_done, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 623:51] + node _T_4873 = and(_T_4871, _T_4872) @[el2_lsu_bus_buffer.scala 623:49] + node _T_4874 = eq(bus_addr_match_pending, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 623:68] + node _T_4875 = and(_T_4873, _T_4874) @[el2_lsu_bus_buffer.scala 623:66] + io.lsu_axi_awvalid <= _T_4875 @[el2_lsu_bus_buffer.scala 623:22] + io.lsu_axi_awid <= obuf_tag0 @[el2_lsu_bus_buffer.scala 624:19] + node _T_4876 = bits(obuf_addr, 31, 3) @[el2_lsu_bus_buffer.scala 625:69] node _T_4877 = cat(_T_4876, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_4878 = mux(obuf_sideeffect, obuf_addr, _T_4877) @[el2_lsu_bus_buffer.scala 624:27] - io.lsu_axi_awaddr <= _T_4878 @[el2_lsu_bus_buffer.scala 624:21] + node _T_4878 = mux(obuf_sideeffect, obuf_addr, _T_4877) @[el2_lsu_bus_buffer.scala 625:27] + io.lsu_axi_awaddr <= _T_4878 @[el2_lsu_bus_buffer.scala 625:21] node _T_4879 = cat(UInt<1>("h00"), obuf_sz) @[Cat.scala 29:58] - node _T_4880 = mux(obuf_sideeffect, _T_4879, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 625:27] - io.lsu_axi_awsize <= _T_4880 @[el2_lsu_bus_buffer.scala 625:21] - io.lsu_axi_awprot <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 626:21] - node _T_4881 = mux(obuf_sideeffect, UInt<1>("h00"), UInt<4>("h0f")) @[el2_lsu_bus_buffer.scala 627:28] - io.lsu_axi_awcache <= _T_4881 @[el2_lsu_bus_buffer.scala 627:22] - node _T_4882 = bits(obuf_addr, 31, 28) @[el2_lsu_bus_buffer.scala 628:35] - io.lsu_axi_awregion <= _T_4882 @[el2_lsu_bus_buffer.scala 628:23] - io.lsu_axi_awlen <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 629:20] - io.lsu_axi_awburst <= UInt<2>("h01") @[el2_lsu_bus_buffer.scala 630:22] - io.lsu_axi_awqos <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 631:20] - io.lsu_axi_awlock <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 632:21] - node _T_4883 = and(obuf_valid, obuf_write) @[el2_lsu_bus_buffer.scala 634:35] - node _T_4884 = eq(obuf_data_done, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 634:50] - node _T_4885 = and(_T_4883, _T_4884) @[el2_lsu_bus_buffer.scala 634:48] - node _T_4886 = eq(bus_addr_match_pending, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 634:68] - node _T_4887 = and(_T_4885, _T_4886) @[el2_lsu_bus_buffer.scala 634:66] - io.lsu_axi_wvalid <= _T_4887 @[el2_lsu_bus_buffer.scala 634:21] + node _T_4880 = mux(obuf_sideeffect, _T_4879, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 626:27] + io.lsu_axi_awsize <= _T_4880 @[el2_lsu_bus_buffer.scala 626:21] + io.lsu_axi_awprot <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 627:21] + node _T_4881 = mux(obuf_sideeffect, UInt<1>("h00"), UInt<4>("h0f")) @[el2_lsu_bus_buffer.scala 628:28] + io.lsu_axi_awcache <= _T_4881 @[el2_lsu_bus_buffer.scala 628:22] + node _T_4882 = bits(obuf_addr, 31, 28) @[el2_lsu_bus_buffer.scala 629:35] + io.lsu_axi_awregion <= _T_4882 @[el2_lsu_bus_buffer.scala 629:23] + io.lsu_axi_awlen <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 630:20] + io.lsu_axi_awburst <= UInt<2>("h01") @[el2_lsu_bus_buffer.scala 631:22] + io.lsu_axi_awqos <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 632:20] + io.lsu_axi_awlock <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 633:21] + node _T_4883 = and(obuf_valid, obuf_write) @[el2_lsu_bus_buffer.scala 635:35] + node _T_4884 = eq(obuf_data_done, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 635:50] + node _T_4885 = and(_T_4883, _T_4884) @[el2_lsu_bus_buffer.scala 635:48] + node _T_4886 = eq(bus_addr_match_pending, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 635:68] + node _T_4887 = and(_T_4885, _T_4886) @[el2_lsu_bus_buffer.scala 635:66] + io.lsu_axi_wvalid <= _T_4887 @[el2_lsu_bus_buffer.scala 635:21] node _T_4888 = bits(obuf_write, 0, 0) @[Bitwise.scala 72:15] node _T_4889 = mux(_T_4888, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_4890 = and(obuf_byteen, _T_4889) @[el2_lsu_bus_buffer.scala 635:35] - io.lsu_axi_wstrb <= _T_4890 @[el2_lsu_bus_buffer.scala 635:20] - io.lsu_axi_wdata <= obuf_data @[el2_lsu_bus_buffer.scala 636:20] - io.lsu_axi_wlast <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 637:20] - node _T_4891 = eq(obuf_write, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 639:38] - node _T_4892 = and(obuf_valid, _T_4891) @[el2_lsu_bus_buffer.scala 639:36] - node _T_4893 = eq(obuf_nosend, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 639:52] - node _T_4894 = and(_T_4892, _T_4893) @[el2_lsu_bus_buffer.scala 639:50] - node _T_4895 = eq(bus_addr_match_pending, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 639:67] - node _T_4896 = and(_T_4894, _T_4895) @[el2_lsu_bus_buffer.scala 639:65] - io.lsu_axi_arvalid <= _T_4896 @[el2_lsu_bus_buffer.scala 639:22] - io.lsu_axi_arid <= obuf_tag0 @[el2_lsu_bus_buffer.scala 640:19] - node _T_4897 = bits(obuf_addr, 31, 3) @[el2_lsu_bus_buffer.scala 641:69] + node _T_4890 = and(obuf_byteen, _T_4889) @[el2_lsu_bus_buffer.scala 636:35] + io.lsu_axi_wstrb <= _T_4890 @[el2_lsu_bus_buffer.scala 636:20] + io.lsu_axi_wdata <= obuf_data @[el2_lsu_bus_buffer.scala 637:20] + io.lsu_axi_wlast <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 638:20] + node _T_4891 = eq(obuf_write, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 640:38] + node _T_4892 = and(obuf_valid, _T_4891) @[el2_lsu_bus_buffer.scala 640:36] + node _T_4893 = eq(obuf_nosend, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 640:52] + node _T_4894 = and(_T_4892, _T_4893) @[el2_lsu_bus_buffer.scala 640:50] + node _T_4895 = eq(bus_addr_match_pending, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 640:67] + node _T_4896 = and(_T_4894, _T_4895) @[el2_lsu_bus_buffer.scala 640:65] + io.lsu_axi_arvalid <= _T_4896 @[el2_lsu_bus_buffer.scala 640:22] + io.lsu_axi_arid <= obuf_tag0 @[el2_lsu_bus_buffer.scala 641:19] + node _T_4897 = bits(obuf_addr, 31, 3) @[el2_lsu_bus_buffer.scala 642:69] node _T_4898 = cat(_T_4897, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_4899 = mux(obuf_sideeffect, obuf_addr, _T_4898) @[el2_lsu_bus_buffer.scala 641:27] - io.lsu_axi_araddr <= _T_4899 @[el2_lsu_bus_buffer.scala 641:21] + node _T_4899 = mux(obuf_sideeffect, obuf_addr, _T_4898) @[el2_lsu_bus_buffer.scala 642:27] + io.lsu_axi_araddr <= _T_4899 @[el2_lsu_bus_buffer.scala 642:21] node _T_4900 = cat(UInt<1>("h00"), obuf_sz) @[Cat.scala 29:58] - node _T_4901 = mux(obuf_sideeffect, _T_4900, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 642:27] - io.lsu_axi_arsize <= _T_4901 @[el2_lsu_bus_buffer.scala 642:21] - io.lsu_axi_arprot <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 643:21] - node _T_4902 = mux(obuf_sideeffect, UInt<4>("h00"), UInt<4>("h0f")) @[el2_lsu_bus_buffer.scala 644:28] - io.lsu_axi_arcache <= _T_4902 @[el2_lsu_bus_buffer.scala 644:22] - node _T_4903 = bits(obuf_addr, 31, 28) @[el2_lsu_bus_buffer.scala 645:35] - io.lsu_axi_arregion <= _T_4903 @[el2_lsu_bus_buffer.scala 645:23] - io.lsu_axi_arlen <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 646:20] - io.lsu_axi_arburst <= UInt<2>("h01") @[el2_lsu_bus_buffer.scala 647:22] - io.lsu_axi_arqos <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 648:20] - io.lsu_axi_arlock <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 649:21] - io.lsu_axi_bready <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 650:21] - io.lsu_axi_rready <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 651:21] - node _T_4904 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 652:81] - node _T_4905 = bits(buf_error, 0, 0) @[el2_lsu_bus_buffer.scala 652:125] - node _T_4906 = and(io.lsu_bus_clk_en_q, _T_4905) @[el2_lsu_bus_buffer.scala 652:114] - node _T_4907 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 652:140] - node _T_4908 = and(_T_4906, _T_4907) @[el2_lsu_bus_buffer.scala 652:129] - node _T_4909 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 652:81] - node _T_4910 = bits(buf_error, 1, 1) @[el2_lsu_bus_buffer.scala 652:125] - node _T_4911 = and(io.lsu_bus_clk_en_q, _T_4910) @[el2_lsu_bus_buffer.scala 652:114] - node _T_4912 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 652:140] - node _T_4913 = and(_T_4911, _T_4912) @[el2_lsu_bus_buffer.scala 652:129] - node _T_4914 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 652:81] - node _T_4915 = bits(buf_error, 2, 2) @[el2_lsu_bus_buffer.scala 652:125] - node _T_4916 = and(io.lsu_bus_clk_en_q, _T_4915) @[el2_lsu_bus_buffer.scala 652:114] - node _T_4917 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 652:140] - node _T_4918 = and(_T_4916, _T_4917) @[el2_lsu_bus_buffer.scala 652:129] - node _T_4919 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 652:81] - node _T_4920 = bits(buf_error, 3, 3) @[el2_lsu_bus_buffer.scala 652:125] - node _T_4921 = and(io.lsu_bus_clk_en_q, _T_4920) @[el2_lsu_bus_buffer.scala 652:114] - node _T_4922 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 652:140] - node _T_4923 = and(_T_4921, _T_4922) @[el2_lsu_bus_buffer.scala 652:129] + node _T_4901 = mux(obuf_sideeffect, _T_4900, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 643:27] + io.lsu_axi_arsize <= _T_4901 @[el2_lsu_bus_buffer.scala 643:21] + io.lsu_axi_arprot <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 644:21] + node _T_4902 = mux(obuf_sideeffect, UInt<4>("h00"), UInt<4>("h0f")) @[el2_lsu_bus_buffer.scala 645:28] + io.lsu_axi_arcache <= _T_4902 @[el2_lsu_bus_buffer.scala 645:22] + node _T_4903 = bits(obuf_addr, 31, 28) @[el2_lsu_bus_buffer.scala 646:35] + io.lsu_axi_arregion <= _T_4903 @[el2_lsu_bus_buffer.scala 646:23] + io.lsu_axi_arlen <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 647:20] + io.lsu_axi_arburst <= UInt<2>("h01") @[el2_lsu_bus_buffer.scala 648:22] + io.lsu_axi_arqos <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 649:20] + io.lsu_axi_arlock <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 650:21] + io.lsu_axi_bready <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 651:21] + io.lsu_axi_rready <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 652:21] + node _T_4904 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 653:81] + node _T_4905 = bits(buf_error, 0, 0) @[el2_lsu_bus_buffer.scala 653:125] + node _T_4906 = and(io.lsu_bus_clk_en_q, _T_4905) @[el2_lsu_bus_buffer.scala 653:114] + node _T_4907 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 653:140] + node _T_4908 = and(_T_4906, _T_4907) @[el2_lsu_bus_buffer.scala 653:129] + node _T_4909 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 653:81] + node _T_4910 = bits(buf_error, 1, 1) @[el2_lsu_bus_buffer.scala 653:125] + node _T_4911 = and(io.lsu_bus_clk_en_q, _T_4910) @[el2_lsu_bus_buffer.scala 653:114] + node _T_4912 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 653:140] + node _T_4913 = and(_T_4911, _T_4912) @[el2_lsu_bus_buffer.scala 653:129] + node _T_4914 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 653:81] + node _T_4915 = bits(buf_error, 2, 2) @[el2_lsu_bus_buffer.scala 653:125] + node _T_4916 = and(io.lsu_bus_clk_en_q, _T_4915) @[el2_lsu_bus_buffer.scala 653:114] + node _T_4917 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 653:140] + node _T_4918 = and(_T_4916, _T_4917) @[el2_lsu_bus_buffer.scala 653:129] + node _T_4919 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 653:81] + node _T_4920 = bits(buf_error, 3, 3) @[el2_lsu_bus_buffer.scala 653:125] + node _T_4921 = and(io.lsu_bus_clk_en_q, _T_4920) @[el2_lsu_bus_buffer.scala 653:114] + node _T_4922 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 653:140] + node _T_4923 = and(_T_4921, _T_4922) @[el2_lsu_bus_buffer.scala 653:129] node _T_4924 = mux(_T_4904, _T_4908, UInt<1>("h00")) @[Mux.scala 27:72] node _T_4925 = mux(_T_4909, _T_4913, UInt<1>("h00")) @[Mux.scala 27:72] node _T_4926 = mux(_T_4914, _T_4918, UInt<1>("h00")) @[Mux.scala 27:72] @@ -6431,27 +6429,27 @@ circuit el2_lsu_bus_intf : node _T_4930 = or(_T_4929, _T_4927) @[Mux.scala 27:72] wire _T_4931 : UInt<1> @[Mux.scala 27:72] _T_4931 <= _T_4930 @[Mux.scala 27:72] - io.lsu_imprecise_error_store_any <= _T_4931 @[el2_lsu_bus_buffer.scala 652:36] - node _T_4932 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 653:82] - node _T_4933 = bits(buf_error, 0, 0) @[el2_lsu_bus_buffer.scala 653:104] - node _T_4934 = and(_T_4932, _T_4933) @[el2_lsu_bus_buffer.scala 653:93] - node _T_4935 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 653:119] - node _T_4936 = and(_T_4934, _T_4935) @[el2_lsu_bus_buffer.scala 653:108] - node _T_4937 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 653:82] - node _T_4938 = bits(buf_error, 1, 1) @[el2_lsu_bus_buffer.scala 653:104] - node _T_4939 = and(_T_4937, _T_4938) @[el2_lsu_bus_buffer.scala 653:93] - node _T_4940 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 653:119] - node _T_4941 = and(_T_4939, _T_4940) @[el2_lsu_bus_buffer.scala 653:108] - node _T_4942 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 653:82] - node _T_4943 = bits(buf_error, 2, 2) @[el2_lsu_bus_buffer.scala 653:104] - node _T_4944 = and(_T_4942, _T_4943) @[el2_lsu_bus_buffer.scala 653:93] - node _T_4945 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 653:119] - node _T_4946 = and(_T_4944, _T_4945) @[el2_lsu_bus_buffer.scala 653:108] - node _T_4947 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 653:82] - node _T_4948 = bits(buf_error, 3, 3) @[el2_lsu_bus_buffer.scala 653:104] - node _T_4949 = and(_T_4947, _T_4948) @[el2_lsu_bus_buffer.scala 653:93] - node _T_4950 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 653:119] - node _T_4951 = and(_T_4949, _T_4950) @[el2_lsu_bus_buffer.scala 653:108] + io.lsu_imprecise_error_store_any <= _T_4931 @[el2_lsu_bus_buffer.scala 653:36] + node _T_4932 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 654:82] + node _T_4933 = bits(buf_error, 0, 0) @[el2_lsu_bus_buffer.scala 654:104] + node _T_4934 = and(_T_4932, _T_4933) @[el2_lsu_bus_buffer.scala 654:93] + node _T_4935 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 654:119] + node _T_4936 = and(_T_4934, _T_4935) @[el2_lsu_bus_buffer.scala 654:108] + node _T_4937 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 654:82] + node _T_4938 = bits(buf_error, 1, 1) @[el2_lsu_bus_buffer.scala 654:104] + node _T_4939 = and(_T_4937, _T_4938) @[el2_lsu_bus_buffer.scala 654:93] + node _T_4940 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 654:119] + node _T_4941 = and(_T_4939, _T_4940) @[el2_lsu_bus_buffer.scala 654:108] + node _T_4942 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 654:82] + node _T_4943 = bits(buf_error, 2, 2) @[el2_lsu_bus_buffer.scala 654:104] + node _T_4944 = and(_T_4942, _T_4943) @[el2_lsu_bus_buffer.scala 654:93] + node _T_4945 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 654:119] + node _T_4946 = and(_T_4944, _T_4945) @[el2_lsu_bus_buffer.scala 654:108] + node _T_4947 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 654:82] + node _T_4948 = bits(buf_error, 3, 3) @[el2_lsu_bus_buffer.scala 654:104] + node _T_4949 = and(_T_4947, _T_4948) @[el2_lsu_bus_buffer.scala 654:93] + node _T_4950 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 654:119] + node _T_4951 = and(_T_4949, _T_4950) @[el2_lsu_bus_buffer.scala 654:108] node _T_4952 = mux(_T_4936, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_4953 = mux(_T_4941, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_4954 = mux(_T_4946, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] @@ -6461,54 +6459,54 @@ circuit el2_lsu_bus_intf : node _T_4958 = or(_T_4957, _T_4955) @[Mux.scala 27:72] wire lsu_imprecise_error_store_tag : UInt<2> @[Mux.scala 27:72] lsu_imprecise_error_store_tag <= _T_4958 @[Mux.scala 27:72] - node _T_4959 = eq(io.lsu_imprecise_error_store_any, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 655:72] - node _T_4960 = and(io.lsu_nonblock_load_data_error, _T_4959) @[el2_lsu_bus_buffer.scala 655:70] - io.lsu_imprecise_error_load_any <= _T_4960 @[el2_lsu_bus_buffer.scala 655:35] - node _T_4961 = mux(io.lsu_imprecise_error_store_any, buf_addr[lsu_imprecise_error_store_tag], buf_addr[io.lsu_nonblock_load_data_tag]) @[el2_lsu_bus_buffer.scala 656:41] - io.lsu_imprecise_error_addr_any <= _T_4961 @[el2_lsu_bus_buffer.scala 656:35] - lsu_bus_cntr_overflow <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 657:25] - io.lsu_bus_idle_any <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 659:23] - node _T_4962 = and(io.lsu_axi_awvalid, io.lsu_axi_awready) @[el2_lsu_bus_buffer.scala 662:46] - node _T_4963 = and(io.lsu_axi_wvalid, io.lsu_axi_wready) @[el2_lsu_bus_buffer.scala 662:89] - node _T_4964 = or(_T_4962, _T_4963) @[el2_lsu_bus_buffer.scala 662:68] - node _T_4965 = and(io.lsu_axi_arvalid, io.lsu_axi_arready) @[el2_lsu_bus_buffer.scala 662:132] - node _T_4966 = or(_T_4964, _T_4965) @[el2_lsu_bus_buffer.scala 662:110] - io.lsu_pmu_bus_trxn <= _T_4966 @[el2_lsu_bus_buffer.scala 662:23] - node _T_4967 = and(io.lsu_busreq_r, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 663:48] - node _T_4968 = and(_T_4967, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 663:65] - io.lsu_pmu_bus_misaligned <= _T_4968 @[el2_lsu_bus_buffer.scala 663:29] - node _T_4969 = or(io.lsu_imprecise_error_load_any, io.lsu_imprecise_error_store_any) @[el2_lsu_bus_buffer.scala 664:59] - io.lsu_pmu_bus_error <= _T_4969 @[el2_lsu_bus_buffer.scala 664:24] - node _T_4970 = eq(io.lsu_axi_awready, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 666:48] - node _T_4971 = and(io.lsu_axi_awvalid, _T_4970) @[el2_lsu_bus_buffer.scala 666:46] - node _T_4972 = eq(io.lsu_axi_wready, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 666:92] - node _T_4973 = and(io.lsu_axi_wvalid, _T_4972) @[el2_lsu_bus_buffer.scala 666:90] - node _T_4974 = or(_T_4971, _T_4973) @[el2_lsu_bus_buffer.scala 666:69] - node _T_4975 = eq(io.lsu_axi_arready, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 666:136] - node _T_4976 = and(io.lsu_axi_arvalid, _T_4975) @[el2_lsu_bus_buffer.scala 666:134] - node _T_4977 = or(_T_4974, _T_4976) @[el2_lsu_bus_buffer.scala 666:112] - io.lsu_pmu_bus_busy <= _T_4977 @[el2_lsu_bus_buffer.scala 666:23] - reg _T_4978 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 668:49] - _T_4978 <= WrPtr0_m @[el2_lsu_bus_buffer.scala 668:49] - WrPtr0_r <= _T_4978 @[el2_lsu_bus_buffer.scala 668:12] - reg _T_4979 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 669:49] - _T_4979 <= WrPtr1_m @[el2_lsu_bus_buffer.scala 669:49] - WrPtr1_r <= _T_4979 @[el2_lsu_bus_buffer.scala 669:12] - node _T_4980 = eq(io.flush_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 670:75] - node _T_4981 = and(io.lsu_busreq_m, _T_4980) @[el2_lsu_bus_buffer.scala 670:73] - node _T_4982 = eq(io.ld_full_hit_m, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 670:89] - node _T_4983 = and(_T_4981, _T_4982) @[el2_lsu_bus_buffer.scala 670:87] - reg _T_4984 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 670:56] - _T_4984 <= _T_4983 @[el2_lsu_bus_buffer.scala 670:56] - io.lsu_busreq_r <= _T_4984 @[el2_lsu_bus_buffer.scala 670:19] - reg _T_4985 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 671:66] - _T_4985 <= io.lsu_nonblock_load_valid_m @[el2_lsu_bus_buffer.scala 671:66] - lsu_nonblock_load_valid_r <= _T_4985 @[el2_lsu_bus_buffer.scala 671:29] + node _T_4959 = eq(io.lsu_imprecise_error_store_any, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 656:72] + node _T_4960 = and(io.lsu_nonblock_load_data_error, _T_4959) @[el2_lsu_bus_buffer.scala 656:70] + io.lsu_imprecise_error_load_any <= _T_4960 @[el2_lsu_bus_buffer.scala 656:35] + node _T_4961 = mux(io.lsu_imprecise_error_store_any, buf_addr[lsu_imprecise_error_store_tag], buf_addr[io.lsu_nonblock_load_data_tag]) @[el2_lsu_bus_buffer.scala 657:41] + io.lsu_imprecise_error_addr_any <= _T_4961 @[el2_lsu_bus_buffer.scala 657:35] + lsu_bus_cntr_overflow <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 658:25] + io.lsu_bus_idle_any <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 660:23] + node _T_4962 = and(io.lsu_axi_awvalid, io.lsu_axi_awready) @[el2_lsu_bus_buffer.scala 663:46] + node _T_4963 = and(io.lsu_axi_wvalid, io.lsu_axi_wready) @[el2_lsu_bus_buffer.scala 663:89] + node _T_4964 = or(_T_4962, _T_4963) @[el2_lsu_bus_buffer.scala 663:68] + node _T_4965 = and(io.lsu_axi_arvalid, io.lsu_axi_arready) @[el2_lsu_bus_buffer.scala 663:132] + node _T_4966 = or(_T_4964, _T_4965) @[el2_lsu_bus_buffer.scala 663:110] + io.lsu_pmu_bus_trxn <= _T_4966 @[el2_lsu_bus_buffer.scala 663:23] + node _T_4967 = and(io.lsu_busreq_r, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 664:48] + node _T_4968 = and(_T_4967, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 664:65] + io.lsu_pmu_bus_misaligned <= _T_4968 @[el2_lsu_bus_buffer.scala 664:29] + node _T_4969 = or(io.lsu_imprecise_error_load_any, io.lsu_imprecise_error_store_any) @[el2_lsu_bus_buffer.scala 665:59] + io.lsu_pmu_bus_error <= _T_4969 @[el2_lsu_bus_buffer.scala 665:24] + node _T_4970 = eq(io.lsu_axi_awready, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 667:48] + node _T_4971 = and(io.lsu_axi_awvalid, _T_4970) @[el2_lsu_bus_buffer.scala 667:46] + node _T_4972 = eq(io.lsu_axi_wready, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 667:92] + node _T_4973 = and(io.lsu_axi_wvalid, _T_4972) @[el2_lsu_bus_buffer.scala 667:90] + node _T_4974 = or(_T_4971, _T_4973) @[el2_lsu_bus_buffer.scala 667:69] + node _T_4975 = eq(io.lsu_axi_arready, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 667:136] + node _T_4976 = and(io.lsu_axi_arvalid, _T_4975) @[el2_lsu_bus_buffer.scala 667:134] + node _T_4977 = or(_T_4974, _T_4976) @[el2_lsu_bus_buffer.scala 667:112] + io.lsu_pmu_bus_busy <= _T_4977 @[el2_lsu_bus_buffer.scala 667:23] + reg _T_4978 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 669:49] + _T_4978 <= WrPtr0_m @[el2_lsu_bus_buffer.scala 669:49] + WrPtr0_r <= _T_4978 @[el2_lsu_bus_buffer.scala 669:12] + reg _T_4979 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 670:49] + _T_4979 <= WrPtr1_m @[el2_lsu_bus_buffer.scala 670:49] + WrPtr1_r <= _T_4979 @[el2_lsu_bus_buffer.scala 670:12] + node _T_4980 = eq(io.flush_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 671:75] + node _T_4981 = and(io.lsu_busreq_m, _T_4980) @[el2_lsu_bus_buffer.scala 671:73] + node _T_4982 = eq(io.ld_full_hit_m, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 671:89] + node _T_4983 = and(_T_4981, _T_4982) @[el2_lsu_bus_buffer.scala 671:87] + reg _T_4984 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 671:56] + _T_4984 <= _T_4983 @[el2_lsu_bus_buffer.scala 671:56] + io.lsu_busreq_r <= _T_4984 @[el2_lsu_bus_buffer.scala 671:19] + reg _T_4985 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 672:66] + _T_4985 <= io.lsu_nonblock_load_valid_m @[el2_lsu_bus_buffer.scala 672:66] + lsu_nonblock_load_valid_r <= _T_4985 @[el2_lsu_bus_buffer.scala 672:29] module el2_lsu_bus_intf : input clock : Clock input reset : AsyncReset - output io : {flip scan_mode : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, flip lsu_c1_m_clk : Clock, flip lsu_c1_r_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_bus_ibuf_c1_clk : Clock, flip lsu_bus_obuf_c1_clk : Clock, flip lsu_bus_buf_c1_clk : Clock, flip lsu_free_c2_clk : Clock, flip free_clk : Clock, flip lsu_busm_clk : Clock, flip dec_lsu_valid_raw_d : UInt<1>, flip lsu_busreq_m : UInt<1>, flip lsu_pkt_m : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip lsu_pkt_r : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip lsu_addr_d : UInt<32>, flip lsu_addr_m : UInt<32>, flip lsu_addr_r : UInt<32>, flip end_addr_d : UInt<32>, flip end_addr_m : UInt<32>, flip end_addr_r : UInt<32>, flip store_data_r : UInt<32>, flip dec_tlu_force_halt : UInt<1>, flip lsu_commit_r : UInt<1>, flip is_sideeffects_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, lsu_busreq_r : UInt<1>, lsu_bus_buffer_pend_any : UInt<1>, lsu_bus_buffer_full_any : UInt<1>, lsu_bus_buffer_empty_any : UInt<1>, lsu_bus_idle_any : UInt<1>, bus_read_data_m : UInt<32>, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>, lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>, lsu_nonblock_load_data : UInt<32>, lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, lsu_axi_awvalid : UInt<1>, flip lsu_axi_awready : UInt<1>, lsu_axi_awid : UInt<3>, lsu_axi_awaddr : UInt<32>, lsu_axi_awregion : UInt<4>, lsu_axi_awlen : UInt<8>, lsu_axi_awsize : UInt<3>, lsu_axi_awburst : UInt<2>, lsu_axi_awlock : UInt<1>, lsu_axi_awcache : UInt<4>, lsu_axi_awprot : UInt<3>, lsu_axi_awqos : UInt<4>, lsu_axi_wvalid : UInt<1>, flip lsu_axi_wready : UInt<1>, lsu_axi_wdata : UInt<64>, lsu_axi_wstrb : UInt<8>, lsu_axi_wlast : UInt<1>, flip lsu_axi_bvalid : UInt<1>, lsu_axi_bready : UInt<1>, flip lsu_axi_bresp : UInt<2>, flip lsu_axi_bid : UInt<3>, lsu_axi_arvalid : UInt<1>, flip lsu_axi_arready : UInt<1>, lsu_axi_arid : UInt<3>, lsu_axi_araddr : UInt<32>, lsu_axi_arregion : UInt<4>, lsu_axi_arlen : UInt<8>, lsu_axi_arsize : UInt<3>, lsu_axi_arburst : UInt<2>, lsu_axi_arlock : UInt<1>, lsu_axi_arcache : UInt<4>, lsu_axi_arprot : UInt<3>, lsu_axi_arqos : UInt<4>, flip lsu_axi_rvalid : UInt<1>, lsu_axi_rready : UInt<1>, flip lsu_axi_rid : UInt<3>, flip lsu_axi_rdata : UInt<64>, flip lsu_axi_rresp : UInt<2>, flip lsu_axi_rlast : UInt<1>, flip lsu_bus_clk_en : UInt<1>} + output io : {flip scan_mode : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, flip lsu_c1_m_clk : Clock, flip lsu_c1_r_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_bus_ibuf_c1_clk : Clock, flip lsu_bus_obuf_c1_clk : Clock, flip lsu_bus_buf_c1_clk : Clock, flip lsu_free_c2_clk : Clock, flip free_clk : Clock, flip lsu_busm_clk : Clock, flip dec_lsu_valid_raw_d : UInt<1>, flip lsu_busreq_m : UInt<1>, flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_addr_d : UInt<32>, flip lsu_addr_m : UInt<32>, flip lsu_addr_r : UInt<32>, flip end_addr_d : UInt<32>, flip end_addr_m : UInt<32>, flip end_addr_r : UInt<32>, flip store_data_r : UInt<32>, flip dec_tlu_force_halt : UInt<1>, flip lsu_commit_r : UInt<1>, flip is_sideeffects_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, lsu_busreq_r : UInt<1>, lsu_bus_buffer_pend_any : UInt<1>, lsu_bus_buffer_full_any : UInt<1>, lsu_bus_buffer_empty_any : UInt<1>, lsu_bus_idle_any : UInt<1>, bus_read_data_m : UInt<32>, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>, lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>, lsu_nonblock_load_data : UInt<32>, lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, lsu_axi_awvalid : UInt<1>, flip lsu_axi_awready : UInt<1>, lsu_axi_awid : UInt<3>, lsu_axi_awaddr : UInt<32>, lsu_axi_awregion : UInt<4>, lsu_axi_awlen : UInt<8>, lsu_axi_awsize : UInt<3>, lsu_axi_awburst : UInt<2>, lsu_axi_awlock : UInt<1>, lsu_axi_awcache : UInt<4>, lsu_axi_awprot : UInt<3>, lsu_axi_awqos : UInt<4>, lsu_axi_wvalid : UInt<1>, flip lsu_axi_wready : UInt<1>, lsu_axi_wdata : UInt<64>, lsu_axi_wstrb : UInt<8>, lsu_axi_wlast : UInt<1>, flip lsu_axi_bvalid : UInt<1>, lsu_axi_bready : UInt<1>, flip lsu_axi_bresp : UInt<2>, flip lsu_axi_bid : UInt<3>, lsu_axi_arvalid : UInt<1>, flip lsu_axi_arready : UInt<1>, lsu_axi_arid : UInt<3>, lsu_axi_araddr : UInt<32>, lsu_axi_arregion : UInt<4>, lsu_axi_arlen : UInt<8>, lsu_axi_arsize : UInt<3>, lsu_axi_arburst : UInt<2>, lsu_axi_arlock : UInt<1>, lsu_axi_arcache : UInt<4>, lsu_axi_arprot : UInt<3>, lsu_axi_arqos : UInt<4>, flip lsu_axi_rvalid : UInt<1>, lsu_axi_rready : UInt<1>, flip lsu_axi_rid : UInt<3>, flip lsu_axi_rdata : UInt<64>, flip lsu_axi_rresp : UInt<2>, flip lsu_axi_rlast : UInt<1>, flip lsu_bus_clk_en : UInt<1>} wire lsu_bus_clk_en_q : UInt<1> lsu_bus_clk_en_q <= UInt<1>("h00") @@ -6613,32 +6611,32 @@ circuit el2_lsu_bus_intf : bus_buffer.io.lsu_free_c2_clk <= io.lsu_free_c2_clk @[el2_lsu_bus_intf.scala 179:51] bus_buffer.io.lsu_busm_clk <= io.lsu_busm_clk @[el2_lsu_bus_intf.scala 180:51] bus_buffer.io.dec_lsu_valid_raw_d <= io.dec_lsu_valid_raw_d @[el2_lsu_bus_intf.scala 181:51] + bus_buffer.io.lsu_pkt_m.bits.store_data_bypass_m <= io.lsu_pkt_m.bits.store_data_bypass_m @[el2_lsu_bus_intf.scala 184:27] + bus_buffer.io.lsu_pkt_m.bits.load_ldst_bypass_d <= io.lsu_pkt_m.bits.load_ldst_bypass_d @[el2_lsu_bus_intf.scala 184:27] + bus_buffer.io.lsu_pkt_m.bits.store_data_bypass_d <= io.lsu_pkt_m.bits.store_data_bypass_d @[el2_lsu_bus_intf.scala 184:27] + bus_buffer.io.lsu_pkt_m.bits.dma <= io.lsu_pkt_m.bits.dma @[el2_lsu_bus_intf.scala 184:27] + bus_buffer.io.lsu_pkt_m.bits.unsign <= io.lsu_pkt_m.bits.unsign @[el2_lsu_bus_intf.scala 184:27] + bus_buffer.io.lsu_pkt_m.bits.store <= io.lsu_pkt_m.bits.store @[el2_lsu_bus_intf.scala 184:27] + bus_buffer.io.lsu_pkt_m.bits.load <= io.lsu_pkt_m.bits.load @[el2_lsu_bus_intf.scala 184:27] + bus_buffer.io.lsu_pkt_m.bits.dword <= io.lsu_pkt_m.bits.dword @[el2_lsu_bus_intf.scala 184:27] + bus_buffer.io.lsu_pkt_m.bits.word <= io.lsu_pkt_m.bits.word @[el2_lsu_bus_intf.scala 184:27] + bus_buffer.io.lsu_pkt_m.bits.half <= io.lsu_pkt_m.bits.half @[el2_lsu_bus_intf.scala 184:27] + bus_buffer.io.lsu_pkt_m.bits.by <= io.lsu_pkt_m.bits.by @[el2_lsu_bus_intf.scala 184:27] + bus_buffer.io.lsu_pkt_m.bits.fast_int <= io.lsu_pkt_m.bits.fast_int @[el2_lsu_bus_intf.scala 184:27] bus_buffer.io.lsu_pkt_m.valid <= io.lsu_pkt_m.valid @[el2_lsu_bus_intf.scala 184:27] - bus_buffer.io.lsu_pkt_m.store_data_bypass_m <= io.lsu_pkt_m.store_data_bypass_m @[el2_lsu_bus_intf.scala 184:27] - bus_buffer.io.lsu_pkt_m.load_ldst_bypass_d <= io.lsu_pkt_m.load_ldst_bypass_d @[el2_lsu_bus_intf.scala 184:27] - bus_buffer.io.lsu_pkt_m.store_data_bypass_d <= io.lsu_pkt_m.store_data_bypass_d @[el2_lsu_bus_intf.scala 184:27] - bus_buffer.io.lsu_pkt_m.dma <= io.lsu_pkt_m.dma @[el2_lsu_bus_intf.scala 184:27] - bus_buffer.io.lsu_pkt_m.unsign <= io.lsu_pkt_m.unsign @[el2_lsu_bus_intf.scala 184:27] - bus_buffer.io.lsu_pkt_m.store <= io.lsu_pkt_m.store @[el2_lsu_bus_intf.scala 184:27] - bus_buffer.io.lsu_pkt_m.load <= io.lsu_pkt_m.load @[el2_lsu_bus_intf.scala 184:27] - bus_buffer.io.lsu_pkt_m.dword <= io.lsu_pkt_m.dword @[el2_lsu_bus_intf.scala 184:27] - bus_buffer.io.lsu_pkt_m.word <= io.lsu_pkt_m.word @[el2_lsu_bus_intf.scala 184:27] - bus_buffer.io.lsu_pkt_m.half <= io.lsu_pkt_m.half @[el2_lsu_bus_intf.scala 184:27] - bus_buffer.io.lsu_pkt_m.by <= io.lsu_pkt_m.by @[el2_lsu_bus_intf.scala 184:27] - bus_buffer.io.lsu_pkt_m.fast_int <= io.lsu_pkt_m.fast_int @[el2_lsu_bus_intf.scala 184:27] + bus_buffer.io.lsu_pkt_r.bits.store_data_bypass_m <= io.lsu_pkt_r.bits.store_data_bypass_m @[el2_lsu_bus_intf.scala 185:27] + bus_buffer.io.lsu_pkt_r.bits.load_ldst_bypass_d <= io.lsu_pkt_r.bits.load_ldst_bypass_d @[el2_lsu_bus_intf.scala 185:27] + bus_buffer.io.lsu_pkt_r.bits.store_data_bypass_d <= io.lsu_pkt_r.bits.store_data_bypass_d @[el2_lsu_bus_intf.scala 185:27] + bus_buffer.io.lsu_pkt_r.bits.dma <= io.lsu_pkt_r.bits.dma @[el2_lsu_bus_intf.scala 185:27] + bus_buffer.io.lsu_pkt_r.bits.unsign <= io.lsu_pkt_r.bits.unsign @[el2_lsu_bus_intf.scala 185:27] + bus_buffer.io.lsu_pkt_r.bits.store <= io.lsu_pkt_r.bits.store @[el2_lsu_bus_intf.scala 185:27] + bus_buffer.io.lsu_pkt_r.bits.load <= io.lsu_pkt_r.bits.load @[el2_lsu_bus_intf.scala 185:27] + bus_buffer.io.lsu_pkt_r.bits.dword <= io.lsu_pkt_r.bits.dword @[el2_lsu_bus_intf.scala 185:27] + bus_buffer.io.lsu_pkt_r.bits.word <= io.lsu_pkt_r.bits.word @[el2_lsu_bus_intf.scala 185:27] + bus_buffer.io.lsu_pkt_r.bits.half <= io.lsu_pkt_r.bits.half @[el2_lsu_bus_intf.scala 185:27] + bus_buffer.io.lsu_pkt_r.bits.by <= io.lsu_pkt_r.bits.by @[el2_lsu_bus_intf.scala 185:27] + bus_buffer.io.lsu_pkt_r.bits.fast_int <= io.lsu_pkt_r.bits.fast_int @[el2_lsu_bus_intf.scala 185:27] bus_buffer.io.lsu_pkt_r.valid <= io.lsu_pkt_r.valid @[el2_lsu_bus_intf.scala 185:27] - bus_buffer.io.lsu_pkt_r.store_data_bypass_m <= io.lsu_pkt_r.store_data_bypass_m @[el2_lsu_bus_intf.scala 185:27] - bus_buffer.io.lsu_pkt_r.load_ldst_bypass_d <= io.lsu_pkt_r.load_ldst_bypass_d @[el2_lsu_bus_intf.scala 185:27] - bus_buffer.io.lsu_pkt_r.store_data_bypass_d <= io.lsu_pkt_r.store_data_bypass_d @[el2_lsu_bus_intf.scala 185:27] - bus_buffer.io.lsu_pkt_r.dma <= io.lsu_pkt_r.dma @[el2_lsu_bus_intf.scala 185:27] - bus_buffer.io.lsu_pkt_r.unsign <= io.lsu_pkt_r.unsign @[el2_lsu_bus_intf.scala 185:27] - bus_buffer.io.lsu_pkt_r.store <= io.lsu_pkt_r.store @[el2_lsu_bus_intf.scala 185:27] - bus_buffer.io.lsu_pkt_r.load <= io.lsu_pkt_r.load @[el2_lsu_bus_intf.scala 185:27] - bus_buffer.io.lsu_pkt_r.dword <= io.lsu_pkt_r.dword @[el2_lsu_bus_intf.scala 185:27] - bus_buffer.io.lsu_pkt_r.word <= io.lsu_pkt_r.word @[el2_lsu_bus_intf.scala 185:27] - bus_buffer.io.lsu_pkt_r.half <= io.lsu_pkt_r.half @[el2_lsu_bus_intf.scala 185:27] - bus_buffer.io.lsu_pkt_r.by <= io.lsu_pkt_r.by @[el2_lsu_bus_intf.scala 185:27] - bus_buffer.io.lsu_pkt_r.fast_int <= io.lsu_pkt_r.fast_int @[el2_lsu_bus_intf.scala 185:27] bus_buffer.io.lsu_addr_m <= io.lsu_addr_m @[el2_lsu_bus_intf.scala 188:51] bus_buffer.io.end_addr_m <= io.end_addr_m @[el2_lsu_bus_intf.scala 189:51] bus_buffer.io.lsu_addr_r <= io.lsu_addr_r @[el2_lsu_bus_intf.scala 190:51] @@ -6720,9 +6718,9 @@ circuit el2_lsu_bus_intf : bus_buffer.io.ldst_byteen_ext_m <= ldst_byteen_ext_m @[el2_lsu_bus_intf.scala 269:51] bus_buffer.io.ld_full_hit_m <= ld_full_hit_m @[el2_lsu_bus_intf.scala 270:51] bus_buffer.io.lsu_bus_clk_en_q <= lsu_bus_clk_en_q @[el2_lsu_bus_intf.scala 271:51] - node _T = bits(io.lsu_pkt_m.word, 0, 0) @[el2_lsu_bus_intf.scala 276:58] - node _T_1 = bits(io.lsu_pkt_m.half, 0, 0) @[el2_lsu_bus_intf.scala 276:97] - node _T_2 = bits(io.lsu_pkt_m.by, 0, 0) @[el2_lsu_bus_intf.scala 276:133] + node _T = bits(io.lsu_pkt_m.bits.word, 0, 0) @[el2_lsu_bus_intf.scala 276:63] + node _T_1 = bits(io.lsu_pkt_m.bits.half, 0, 0) @[el2_lsu_bus_intf.scala 276:107] + node _T_2 = bits(io.lsu_pkt_m.bits.by, 0, 0) @[el2_lsu_bus_intf.scala 276:148] node _T_3 = mux(_T, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_4 = mux(_T_1, UInt<4>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_5 = mux(_T_2, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] @@ -6748,15 +6746,15 @@ circuit el2_lsu_bus_intf : node _T_20 = eq(ldst_dual_r, UInt<1>("h00")) @[el2_lsu_bus_intf.scala 280:48] node _T_21 = and(io.lsu_busreq_r, _T_20) @[el2_lsu_bus_intf.scala 280:46] node _T_22 = and(_T_21, io.lsu_busreq_m) @[el2_lsu_bus_intf.scala 280:61] - node _T_23 = eq(addr_match_word_lo_r_m, UInt<1>("h00")) @[el2_lsu_bus_intf.scala 280:102] - node _T_24 = or(io.lsu_pkt_m.load, _T_23) @[el2_lsu_bus_intf.scala 280:100] + node _T_23 = eq(addr_match_word_lo_r_m, UInt<1>("h00")) @[el2_lsu_bus_intf.scala 280:107] + node _T_24 = or(io.lsu_pkt_m.bits.load, _T_23) @[el2_lsu_bus_intf.scala 280:105] node _T_25 = and(_T_22, _T_24) @[el2_lsu_bus_intf.scala 280:79] no_word_merge_r <= _T_25 @[el2_lsu_bus_intf.scala 280:27] node _T_26 = eq(ldst_dual_r, UInt<1>("h00")) @[el2_lsu_bus_intf.scala 281:48] node _T_27 = and(io.lsu_busreq_r, _T_26) @[el2_lsu_bus_intf.scala 281:46] node _T_28 = and(_T_27, io.lsu_busreq_m) @[el2_lsu_bus_intf.scala 281:61] - node _T_29 = eq(addr_match_dw_lo_r_m, UInt<1>("h00")) @[el2_lsu_bus_intf.scala 281:102] - node _T_30 = or(io.lsu_pkt_m.load, _T_29) @[el2_lsu_bus_intf.scala 281:100] + node _T_29 = eq(addr_match_dw_lo_r_m, UInt<1>("h00")) @[el2_lsu_bus_intf.scala 281:107] + node _T_30 = or(io.lsu_pkt_m.bits.load, _T_29) @[el2_lsu_bus_intf.scala 281:105] node _T_31 = and(_T_28, _T_30) @[el2_lsu_bus_intf.scala 281:79] no_dword_merge_r <= _T_31 @[el2_lsu_bus_intf.scala 281:27] node _T_32 = bits(ldst_byteen_m, 3, 0) @[el2_lsu_bus_intf.scala 283:43] @@ -6788,29 +6786,29 @@ circuit el2_lsu_bus_intf : node _T_49 = bits(io.lsu_addr_r, 31, 2) @[el2_lsu_bus_intf.scala 293:68] node _T_50 = eq(_T_48, _T_49) @[el2_lsu_bus_intf.scala 293:51] node _T_51 = and(_T_50, io.lsu_pkt_r.valid) @[el2_lsu_bus_intf.scala 293:76] - node _T_52 = and(_T_51, io.lsu_pkt_r.store) @[el2_lsu_bus_intf.scala 293:97] - node _T_53 = and(_T_52, io.lsu_busreq_m) @[el2_lsu_bus_intf.scala 293:118] + node _T_52 = and(_T_51, io.lsu_pkt_r.bits.store) @[el2_lsu_bus_intf.scala 293:97] + node _T_53 = and(_T_52, io.lsu_busreq_m) @[el2_lsu_bus_intf.scala 293:123] ld_addr_rhit_lo_lo <= _T_53 @[el2_lsu_bus_intf.scala 293:27] node _T_54 = bits(io.end_addr_m, 31, 2) @[el2_lsu_bus_intf.scala 294:44] node _T_55 = bits(io.lsu_addr_r, 31, 2) @[el2_lsu_bus_intf.scala 294:68] node _T_56 = eq(_T_54, _T_55) @[el2_lsu_bus_intf.scala 294:51] node _T_57 = and(_T_56, io.lsu_pkt_r.valid) @[el2_lsu_bus_intf.scala 294:76] - node _T_58 = and(_T_57, io.lsu_pkt_r.store) @[el2_lsu_bus_intf.scala 294:97] - node _T_59 = and(_T_58, io.lsu_busreq_m) @[el2_lsu_bus_intf.scala 294:118] + node _T_58 = and(_T_57, io.lsu_pkt_r.bits.store) @[el2_lsu_bus_intf.scala 294:97] + node _T_59 = and(_T_58, io.lsu_busreq_m) @[el2_lsu_bus_intf.scala 294:123] ld_addr_rhit_lo_hi <= _T_59 @[el2_lsu_bus_intf.scala 294:27] node _T_60 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_bus_intf.scala 295:44] node _T_61 = bits(io.end_addr_r, 31, 2) @[el2_lsu_bus_intf.scala 295:68] node _T_62 = eq(_T_60, _T_61) @[el2_lsu_bus_intf.scala 295:51] node _T_63 = and(_T_62, io.lsu_pkt_r.valid) @[el2_lsu_bus_intf.scala 295:76] - node _T_64 = and(_T_63, io.lsu_pkt_r.store) @[el2_lsu_bus_intf.scala 295:97] - node _T_65 = and(_T_64, io.lsu_busreq_m) @[el2_lsu_bus_intf.scala 295:118] + node _T_64 = and(_T_63, io.lsu_pkt_r.bits.store) @[el2_lsu_bus_intf.scala 295:97] + node _T_65 = and(_T_64, io.lsu_busreq_m) @[el2_lsu_bus_intf.scala 295:123] ld_addr_rhit_hi_lo <= _T_65 @[el2_lsu_bus_intf.scala 295:27] node _T_66 = bits(io.end_addr_m, 31, 2) @[el2_lsu_bus_intf.scala 296:44] node _T_67 = bits(io.end_addr_r, 31, 2) @[el2_lsu_bus_intf.scala 296:68] node _T_68 = eq(_T_66, _T_67) @[el2_lsu_bus_intf.scala 296:51] node _T_69 = and(_T_68, io.lsu_pkt_r.valid) @[el2_lsu_bus_intf.scala 296:76] - node _T_70 = and(_T_69, io.lsu_pkt_r.store) @[el2_lsu_bus_intf.scala 296:97] - node _T_71 = and(_T_70, io.lsu_busreq_m) @[el2_lsu_bus_intf.scala 296:118] + node _T_70 = and(_T_69, io.lsu_pkt_r.bits.store) @[el2_lsu_bus_intf.scala 296:97] + node _T_71 = and(_T_70, io.lsu_busreq_m) @[el2_lsu_bus_intf.scala 296:123] ld_addr_rhit_hi_hi <= _T_71 @[el2_lsu_bus_intf.scala 296:27] node _T_72 = bits(ldst_byteen_lo_r, 0, 0) @[el2_lsu_bus_intf.scala 298:88] node _T_73 = and(ld_addr_rhit_lo_lo, _T_72) @[el2_lsu_bus_intf.scala 298:70] @@ -7134,9 +7132,9 @@ circuit el2_lsu_bus_intf : ld_full_hit_hi_m <= _T_369 @[el2_lsu_bus_intf.scala 312:27] node _T_370 = and(ld_full_hit_lo_m, ld_full_hit_hi_m) @[el2_lsu_bus_intf.scala 313:47] node _T_371 = and(_T_370, io.lsu_busreq_m) @[el2_lsu_bus_intf.scala 313:66] - node _T_372 = and(_T_371, io.lsu_pkt_m.load) @[el2_lsu_bus_intf.scala 313:84] - node _T_373 = eq(io.is_sideeffects_m, UInt<1>("h00")) @[el2_lsu_bus_intf.scala 313:106] - node _T_374 = and(_T_372, _T_373) @[el2_lsu_bus_intf.scala 313:104] + node _T_372 = and(_T_371, io.lsu_pkt_m.bits.load) @[el2_lsu_bus_intf.scala 313:84] + node _T_373 = eq(io.is_sideeffects_m, UInt<1>("h00")) @[el2_lsu_bus_intf.scala 313:111] + node _T_374 = and(_T_372, _T_373) @[el2_lsu_bus_intf.scala 313:109] ld_full_hit_m <= _T_374 @[el2_lsu_bus_intf.scala 313:27] node _T_375 = bits(ld_fwddata_hi, 31, 0) @[el2_lsu_bus_intf.scala 314:47] node _T_376 = bits(ld_fwddata_lo, 31, 0) @[el2_lsu_bus_intf.scala 314:68] diff --git a/el2_lsu_bus_intf.v b/el2_lsu_bus_intf.v index 5987290c..0cb28b84 100644 --- a/el2_lsu_bus_intf.v +++ b/el2_lsu_bus_intf.v @@ -34,14 +34,14 @@ module el2_lsu_bus_buffer( input io_lsu_free_c2_clk, input io_lsu_busm_clk, input io_dec_lsu_valid_raw_d, - input io_lsu_pkt_m_load, input io_lsu_pkt_m_valid, - input io_lsu_pkt_r_by, - input io_lsu_pkt_r_half, - input io_lsu_pkt_r_word, - input io_lsu_pkt_r_load, - input io_lsu_pkt_r_store, - input io_lsu_pkt_r_unsign, + input io_lsu_pkt_m_bits_load, + input io_lsu_pkt_r_bits_by, + input io_lsu_pkt_r_bits_half, + input io_lsu_pkt_r_bits_word, + input io_lsu_pkt_r_bits_load, + input io_lsu_pkt_r_bits_store, + input io_lsu_pkt_r_bits_unsign, input [31:0] io_lsu_addr_m, input [31:0] io_end_addr_m, input [31:0] io_lsu_addr_r, @@ -320,411 +320,411 @@ module el2_lsu_bus_buffer( wire _T_55 = _T_53 & _T_26; // @[el2_lsu_bus_buffer.scala 131:113] wire ld_addr_hitvec_hi_3 = _T_55 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 131:141] reg [3:0] buf_byteen_3; // @[Reg.scala 27:20] - wire _T_99 = ld_addr_hitvec_lo_3 & buf_byteen_3[0]; // @[el2_lsu_bus_buffer.scala 194:95] - wire _T_101 = _T_99 & ldst_byteen_lo_m[0]; // @[el2_lsu_bus_buffer.scala 194:114] + wire _T_99 = ld_addr_hitvec_lo_3 & buf_byteen_3[0]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_101 = _T_99 & ldst_byteen_lo_m[0]; // @[el2_lsu_bus_buffer.scala 195:114] reg [3:0] buf_byteen_2; // @[Reg.scala 27:20] - wire _T_95 = ld_addr_hitvec_lo_2 & buf_byteen_2[0]; // @[el2_lsu_bus_buffer.scala 194:95] - wire _T_97 = _T_95 & ldst_byteen_lo_m[0]; // @[el2_lsu_bus_buffer.scala 194:114] + wire _T_95 = ld_addr_hitvec_lo_2 & buf_byteen_2[0]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_97 = _T_95 & ldst_byteen_lo_m[0]; // @[el2_lsu_bus_buffer.scala 195:114] reg [3:0] buf_byteen_1; // @[Reg.scala 27:20] - wire _T_91 = ld_addr_hitvec_lo_1 & buf_byteen_1[0]; // @[el2_lsu_bus_buffer.scala 194:95] - wire _T_93 = _T_91 & ldst_byteen_lo_m[0]; // @[el2_lsu_bus_buffer.scala 194:114] + wire _T_91 = ld_addr_hitvec_lo_1 & buf_byteen_1[0]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_93 = _T_91 & ldst_byteen_lo_m[0]; // @[el2_lsu_bus_buffer.scala 195:114] reg [3:0] buf_byteen_0; // @[Reg.scala 27:20] - wire _T_87 = ld_addr_hitvec_lo_0 & buf_byteen_0[0]; // @[el2_lsu_bus_buffer.scala 194:95] - wire _T_89 = _T_87 & ldst_byteen_lo_m[0]; // @[el2_lsu_bus_buffer.scala 194:114] + wire _T_87 = ld_addr_hitvec_lo_0 & buf_byteen_0[0]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_89 = _T_87 & ldst_byteen_lo_m[0]; // @[el2_lsu_bus_buffer.scala 195:114] wire [3:0] ld_byte_hitvec_lo_0 = {_T_101,_T_97,_T_93,_T_89}; // @[Cat.scala 29:58] - reg [3:0] buf_ageQ_3; // @[el2_lsu_bus_buffer.scala 553:60] - wire _T_2621 = buf_state_3 == 3'h2; // @[el2_lsu_bus_buffer.scala 465:93] + reg [3:0] buf_ageQ_3; // @[el2_lsu_bus_buffer.scala 554:60] + wire _T_2621 = buf_state_3 == 3'h2; // @[el2_lsu_bus_buffer.scala 466:93] wire _T_4107 = 3'h0 == buf_state_3; // @[Conditional.scala 37:30] wire _T_4130 = 3'h1 == buf_state_3; // @[Conditional.scala 37:30] wire _T_4134 = 3'h2 == buf_state_3; // @[Conditional.scala 37:30] reg [1:0] _T_1848; // @[Reg.scala 27:20] - wire [2:0] obuf_tag0 = {{1'd0}, _T_1848}; // @[el2_lsu_bus_buffer.scala 405:13] - wire _T_4141 = obuf_tag0 == 3'h3; // @[el2_lsu_bus_buffer.scala 508:48] + wire [2:0] obuf_tag0 = {{1'd0}, _T_1848}; // @[el2_lsu_bus_buffer.scala 406:13] + wire _T_4141 = obuf_tag0 == 3'h3; // @[el2_lsu_bus_buffer.scala 509:48] reg obuf_merge; // @[Reg.scala 27:20] reg [1:0] obuf_tag1; // @[Reg.scala 27:20] - wire [2:0] _GEN_358 = {{1'd0}, obuf_tag1}; // @[el2_lsu_bus_buffer.scala 508:104] - wire _T_4142 = _GEN_358 == 3'h3; // @[el2_lsu_bus_buffer.scala 508:104] - wire _T_4143 = obuf_merge & _T_4142; // @[el2_lsu_bus_buffer.scala 508:91] - wire _T_4144 = _T_4141 | _T_4143; // @[el2_lsu_bus_buffer.scala 508:77] - reg obuf_valid; // @[el2_lsu_bus_buffer.scala 399:54] - wire _T_4145 = _T_4144 & obuf_valid; // @[el2_lsu_bus_buffer.scala 508:135] - reg obuf_wr_enQ; // @[el2_lsu_bus_buffer.scala 398:55] - wire _T_4146 = _T_4145 & obuf_wr_enQ; // @[el2_lsu_bus_buffer.scala 508:148] + wire [2:0] _GEN_358 = {{1'd0}, obuf_tag1}; // @[el2_lsu_bus_buffer.scala 509:104] + wire _T_4142 = _GEN_358 == 3'h3; // @[el2_lsu_bus_buffer.scala 509:104] + wire _T_4143 = obuf_merge & _T_4142; // @[el2_lsu_bus_buffer.scala 509:91] + wire _T_4144 = _T_4141 | _T_4143; // @[el2_lsu_bus_buffer.scala 509:77] + reg obuf_valid; // @[el2_lsu_bus_buffer.scala 400:54] + wire _T_4145 = _T_4144 & obuf_valid; // @[el2_lsu_bus_buffer.scala 509:135] + reg obuf_wr_enQ; // @[el2_lsu_bus_buffer.scala 399:55] + wire _T_4146 = _T_4145 & obuf_wr_enQ; // @[el2_lsu_bus_buffer.scala 509:148] wire _GEN_280 = _T_4134 & _T_4146; // @[Conditional.scala 39:67] wire _GEN_293 = _T_4130 ? 1'h0 : _GEN_280; // @[Conditional.scala 39:67] wire buf_cmd_state_bus_en_3 = _T_4107 ? 1'h0 : _GEN_293; // @[Conditional.scala 40:58] - wire _T_2622 = _T_2621 & buf_cmd_state_bus_en_3; // @[el2_lsu_bus_buffer.scala 465:103] - wire _T_2623 = ~_T_2622; // @[el2_lsu_bus_buffer.scala 465:78] - wire _T_2624 = buf_ageQ_3[3] & _T_2623; // @[el2_lsu_bus_buffer.scala 465:76] - wire _T_2616 = buf_state_2 == 3'h2; // @[el2_lsu_bus_buffer.scala 465:93] + wire _T_2622 = _T_2621 & buf_cmd_state_bus_en_3; // @[el2_lsu_bus_buffer.scala 466:103] + wire _T_2623 = ~_T_2622; // @[el2_lsu_bus_buffer.scala 466:78] + wire _T_2624 = buf_ageQ_3[3] & _T_2623; // @[el2_lsu_bus_buffer.scala 466:76] + wire _T_2616 = buf_state_2 == 3'h2; // @[el2_lsu_bus_buffer.scala 466:93] wire _T_3914 = 3'h0 == buf_state_2; // @[Conditional.scala 37:30] wire _T_3937 = 3'h1 == buf_state_2; // @[Conditional.scala 37:30] wire _T_3941 = 3'h2 == buf_state_2; // @[Conditional.scala 37:30] - wire _T_3948 = obuf_tag0 == 3'h2; // @[el2_lsu_bus_buffer.scala 508:48] - wire _T_3949 = _GEN_358 == 3'h2; // @[el2_lsu_bus_buffer.scala 508:104] - wire _T_3950 = obuf_merge & _T_3949; // @[el2_lsu_bus_buffer.scala 508:91] - wire _T_3951 = _T_3948 | _T_3950; // @[el2_lsu_bus_buffer.scala 508:77] - wire _T_3952 = _T_3951 & obuf_valid; // @[el2_lsu_bus_buffer.scala 508:135] - wire _T_3953 = _T_3952 & obuf_wr_enQ; // @[el2_lsu_bus_buffer.scala 508:148] + wire _T_3948 = obuf_tag0 == 3'h2; // @[el2_lsu_bus_buffer.scala 509:48] + wire _T_3949 = _GEN_358 == 3'h2; // @[el2_lsu_bus_buffer.scala 509:104] + wire _T_3950 = obuf_merge & _T_3949; // @[el2_lsu_bus_buffer.scala 509:91] + wire _T_3951 = _T_3948 | _T_3950; // @[el2_lsu_bus_buffer.scala 509:77] + wire _T_3952 = _T_3951 & obuf_valid; // @[el2_lsu_bus_buffer.scala 509:135] + wire _T_3953 = _T_3952 & obuf_wr_enQ; // @[el2_lsu_bus_buffer.scala 509:148] wire _GEN_204 = _T_3941 & _T_3953; // @[Conditional.scala 39:67] wire _GEN_217 = _T_3937 ? 1'h0 : _GEN_204; // @[Conditional.scala 39:67] wire buf_cmd_state_bus_en_2 = _T_3914 ? 1'h0 : _GEN_217; // @[Conditional.scala 40:58] - wire _T_2617 = _T_2616 & buf_cmd_state_bus_en_2; // @[el2_lsu_bus_buffer.scala 465:103] - wire _T_2618 = ~_T_2617; // @[el2_lsu_bus_buffer.scala 465:78] - wire _T_2619 = buf_ageQ_3[2] & _T_2618; // @[el2_lsu_bus_buffer.scala 465:76] - wire _T_2611 = buf_state_1 == 3'h2; // @[el2_lsu_bus_buffer.scala 465:93] + wire _T_2617 = _T_2616 & buf_cmd_state_bus_en_2; // @[el2_lsu_bus_buffer.scala 466:103] + wire _T_2618 = ~_T_2617; // @[el2_lsu_bus_buffer.scala 466:78] + wire _T_2619 = buf_ageQ_3[2] & _T_2618; // @[el2_lsu_bus_buffer.scala 466:76] + wire _T_2611 = buf_state_1 == 3'h2; // @[el2_lsu_bus_buffer.scala 466:93] wire _T_3721 = 3'h0 == buf_state_1; // @[Conditional.scala 37:30] wire _T_3744 = 3'h1 == buf_state_1; // @[Conditional.scala 37:30] wire _T_3748 = 3'h2 == buf_state_1; // @[Conditional.scala 37:30] - wire _T_3755 = obuf_tag0 == 3'h1; // @[el2_lsu_bus_buffer.scala 508:48] - wire _T_3756 = _GEN_358 == 3'h1; // @[el2_lsu_bus_buffer.scala 508:104] - wire _T_3757 = obuf_merge & _T_3756; // @[el2_lsu_bus_buffer.scala 508:91] - wire _T_3758 = _T_3755 | _T_3757; // @[el2_lsu_bus_buffer.scala 508:77] - wire _T_3759 = _T_3758 & obuf_valid; // @[el2_lsu_bus_buffer.scala 508:135] - wire _T_3760 = _T_3759 & obuf_wr_enQ; // @[el2_lsu_bus_buffer.scala 508:148] + wire _T_3755 = obuf_tag0 == 3'h1; // @[el2_lsu_bus_buffer.scala 509:48] + wire _T_3756 = _GEN_358 == 3'h1; // @[el2_lsu_bus_buffer.scala 509:104] + wire _T_3757 = obuf_merge & _T_3756; // @[el2_lsu_bus_buffer.scala 509:91] + wire _T_3758 = _T_3755 | _T_3757; // @[el2_lsu_bus_buffer.scala 509:77] + wire _T_3759 = _T_3758 & obuf_valid; // @[el2_lsu_bus_buffer.scala 509:135] + wire _T_3760 = _T_3759 & obuf_wr_enQ; // @[el2_lsu_bus_buffer.scala 509:148] wire _GEN_128 = _T_3748 & _T_3760; // @[Conditional.scala 39:67] wire _GEN_141 = _T_3744 ? 1'h0 : _GEN_128; // @[Conditional.scala 39:67] wire buf_cmd_state_bus_en_1 = _T_3721 ? 1'h0 : _GEN_141; // @[Conditional.scala 40:58] - wire _T_2612 = _T_2611 & buf_cmd_state_bus_en_1; // @[el2_lsu_bus_buffer.scala 465:103] - wire _T_2613 = ~_T_2612; // @[el2_lsu_bus_buffer.scala 465:78] - wire _T_2614 = buf_ageQ_3[1] & _T_2613; // @[el2_lsu_bus_buffer.scala 465:76] - wire _T_2606 = buf_state_0 == 3'h2; // @[el2_lsu_bus_buffer.scala 465:93] + wire _T_2612 = _T_2611 & buf_cmd_state_bus_en_1; // @[el2_lsu_bus_buffer.scala 466:103] + wire _T_2613 = ~_T_2612; // @[el2_lsu_bus_buffer.scala 466:78] + wire _T_2614 = buf_ageQ_3[1] & _T_2613; // @[el2_lsu_bus_buffer.scala 466:76] + wire _T_2606 = buf_state_0 == 3'h2; // @[el2_lsu_bus_buffer.scala 466:93] wire _T_3528 = 3'h0 == buf_state_0; // @[Conditional.scala 37:30] wire _T_3551 = 3'h1 == buf_state_0; // @[Conditional.scala 37:30] wire _T_3555 = 3'h2 == buf_state_0; // @[Conditional.scala 37:30] - wire _T_3562 = obuf_tag0 == 3'h0; // @[el2_lsu_bus_buffer.scala 508:48] - wire _T_3563 = _GEN_358 == 3'h0; // @[el2_lsu_bus_buffer.scala 508:104] - wire _T_3564 = obuf_merge & _T_3563; // @[el2_lsu_bus_buffer.scala 508:91] - wire _T_3565 = _T_3562 | _T_3564; // @[el2_lsu_bus_buffer.scala 508:77] - wire _T_3566 = _T_3565 & obuf_valid; // @[el2_lsu_bus_buffer.scala 508:135] - wire _T_3567 = _T_3566 & obuf_wr_enQ; // @[el2_lsu_bus_buffer.scala 508:148] + wire _T_3562 = obuf_tag0 == 3'h0; // @[el2_lsu_bus_buffer.scala 509:48] + wire _T_3563 = _GEN_358 == 3'h0; // @[el2_lsu_bus_buffer.scala 509:104] + wire _T_3564 = obuf_merge & _T_3563; // @[el2_lsu_bus_buffer.scala 509:91] + wire _T_3565 = _T_3562 | _T_3564; // @[el2_lsu_bus_buffer.scala 509:77] + wire _T_3566 = _T_3565 & obuf_valid; // @[el2_lsu_bus_buffer.scala 509:135] + wire _T_3567 = _T_3566 & obuf_wr_enQ; // @[el2_lsu_bus_buffer.scala 509:148] wire _GEN_52 = _T_3555 & _T_3567; // @[Conditional.scala 39:67] wire _GEN_65 = _T_3551 ? 1'h0 : _GEN_52; // @[Conditional.scala 39:67] wire buf_cmd_state_bus_en_0 = _T_3528 ? 1'h0 : _GEN_65; // @[Conditional.scala 40:58] - wire _T_2607 = _T_2606 & buf_cmd_state_bus_en_0; // @[el2_lsu_bus_buffer.scala 465:103] - wire _T_2608 = ~_T_2607; // @[el2_lsu_bus_buffer.scala 465:78] - wire _T_2609 = buf_ageQ_3[0] & _T_2608; // @[el2_lsu_bus_buffer.scala 465:76] + wire _T_2607 = _T_2606 & buf_cmd_state_bus_en_0; // @[el2_lsu_bus_buffer.scala 466:103] + wire _T_2608 = ~_T_2607; // @[el2_lsu_bus_buffer.scala 466:78] + wire _T_2609 = buf_ageQ_3[0] & _T_2608; // @[el2_lsu_bus_buffer.scala 466:76] wire [3:0] buf_age_3 = {_T_2624,_T_2619,_T_2614,_T_2609}; // @[Cat.scala 29:58] - wire _T_2723 = ~buf_age_3[2]; // @[el2_lsu_bus_buffer.scala 466:89] - wire _T_2725 = _T_2723 & _T_19; // @[el2_lsu_bus_buffer.scala 466:104] - wire _T_2717 = ~buf_age_3[1]; // @[el2_lsu_bus_buffer.scala 466:89] - wire _T_2719 = _T_2717 & _T_12; // @[el2_lsu_bus_buffer.scala 466:104] - wire _T_2711 = ~buf_age_3[0]; // @[el2_lsu_bus_buffer.scala 466:89] - wire _T_2713 = _T_2711 & _T_5; // @[el2_lsu_bus_buffer.scala 466:104] + wire _T_2723 = ~buf_age_3[2]; // @[el2_lsu_bus_buffer.scala 467:89] + wire _T_2725 = _T_2723 & _T_19; // @[el2_lsu_bus_buffer.scala 467:104] + wire _T_2717 = ~buf_age_3[1]; // @[el2_lsu_bus_buffer.scala 467:89] + wire _T_2719 = _T_2717 & _T_12; // @[el2_lsu_bus_buffer.scala 467:104] + wire _T_2711 = ~buf_age_3[0]; // @[el2_lsu_bus_buffer.scala 467:89] + wire _T_2713 = _T_2711 & _T_5; // @[el2_lsu_bus_buffer.scala 467:104] wire [3:0] buf_age_younger_3 = {1'h0,_T_2725,_T_2719,_T_2713}; // @[Cat.scala 29:58] - wire [3:0] _T_255 = ld_byte_hitvec_lo_0 & buf_age_younger_3; // @[el2_lsu_bus_buffer.scala 199:122] - wire _T_256 = |_T_255; // @[el2_lsu_bus_buffer.scala 199:144] - wire _T_257 = ~_T_256; // @[el2_lsu_bus_buffer.scala 199:99] - wire _T_258 = ld_byte_hitvec_lo_0[3] & _T_257; // @[el2_lsu_bus_buffer.scala 199:97] + wire [3:0] _T_255 = ld_byte_hitvec_lo_0 & buf_age_younger_3; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_256 = |_T_255; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_257 = ~_T_256; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_258 = ld_byte_hitvec_lo_0[3] & _T_257; // @[el2_lsu_bus_buffer.scala 200:97] reg [31:0] ibuf_addr; // @[el2_lib.scala 514:16] - wire _T_512 = io_lsu_addr_m[31:2] == ibuf_addr[31:2]; // @[el2_lsu_bus_buffer.scala 205:51] + wire _T_512 = io_lsu_addr_m[31:2] == ibuf_addr[31:2]; // @[el2_lsu_bus_buffer.scala 206:51] reg ibuf_write; // @[Reg.scala 27:20] - wire _T_513 = _T_512 & ibuf_write; // @[el2_lsu_bus_buffer.scala 205:73] - reg ibuf_valid; // @[el2_lsu_bus_buffer.scala 292:54] - wire _T_514 = _T_513 & ibuf_valid; // @[el2_lsu_bus_buffer.scala 205:86] - wire ld_addr_ibuf_hit_lo = _T_514 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 205:99] + wire _T_513 = _T_512 & ibuf_write; // @[el2_lsu_bus_buffer.scala 206:73] + reg ibuf_valid; // @[el2_lsu_bus_buffer.scala 293:54] + wire _T_514 = _T_513 & ibuf_valid; // @[el2_lsu_bus_buffer.scala 206:86] + wire ld_addr_ibuf_hit_lo = _T_514 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 206:99] wire [3:0] _T_521 = ld_addr_ibuf_hit_lo ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] reg [3:0] ibuf_byteen; // @[Reg.scala 27:20] - wire [3:0] _T_522 = _T_521 & ibuf_byteen; // @[el2_lsu_bus_buffer.scala 210:55] - wire [3:0] ld_byte_ibuf_hit_lo = _T_522 & ldst_byteen_lo_m; // @[el2_lsu_bus_buffer.scala 210:69] - wire _T_260 = ~ld_byte_ibuf_hit_lo[0]; // @[el2_lsu_bus_buffer.scala 199:150] - wire _T_261 = _T_258 & _T_260; // @[el2_lsu_bus_buffer.scala 199:148] - reg [3:0] buf_ageQ_2; // @[el2_lsu_bus_buffer.scala 553:60] - wire _T_2601 = buf_ageQ_2[3] & _T_2623; // @[el2_lsu_bus_buffer.scala 465:76] - wire _T_2596 = buf_ageQ_2[2] & _T_2618; // @[el2_lsu_bus_buffer.scala 465:76] - wire _T_2591 = buf_ageQ_2[1] & _T_2613; // @[el2_lsu_bus_buffer.scala 465:76] - wire _T_2586 = buf_ageQ_2[0] & _T_2608; // @[el2_lsu_bus_buffer.scala 465:76] + wire [3:0] _T_522 = _T_521 & ibuf_byteen; // @[el2_lsu_bus_buffer.scala 211:55] + wire [3:0] ld_byte_ibuf_hit_lo = _T_522 & ldst_byteen_lo_m; // @[el2_lsu_bus_buffer.scala 211:69] + wire _T_260 = ~ld_byte_ibuf_hit_lo[0]; // @[el2_lsu_bus_buffer.scala 200:150] + wire _T_261 = _T_258 & _T_260; // @[el2_lsu_bus_buffer.scala 200:148] + reg [3:0] buf_ageQ_2; // @[el2_lsu_bus_buffer.scala 554:60] + wire _T_2601 = buf_ageQ_2[3] & _T_2623; // @[el2_lsu_bus_buffer.scala 466:76] + wire _T_2596 = buf_ageQ_2[2] & _T_2618; // @[el2_lsu_bus_buffer.scala 466:76] + wire _T_2591 = buf_ageQ_2[1] & _T_2613; // @[el2_lsu_bus_buffer.scala 466:76] + wire _T_2586 = buf_ageQ_2[0] & _T_2608; // @[el2_lsu_bus_buffer.scala 466:76] wire [3:0] buf_age_2 = {_T_2601,_T_2596,_T_2591,_T_2586}; // @[Cat.scala 29:58] - wire _T_2702 = ~buf_age_2[3]; // @[el2_lsu_bus_buffer.scala 466:89] - wire _T_2704 = _T_2702 & _T_26; // @[el2_lsu_bus_buffer.scala 466:104] - wire _T_2690 = ~buf_age_2[1]; // @[el2_lsu_bus_buffer.scala 466:89] - wire _T_2692 = _T_2690 & _T_12; // @[el2_lsu_bus_buffer.scala 466:104] - wire _T_2684 = ~buf_age_2[0]; // @[el2_lsu_bus_buffer.scala 466:89] - wire _T_2686 = _T_2684 & _T_5; // @[el2_lsu_bus_buffer.scala 466:104] + wire _T_2702 = ~buf_age_2[3]; // @[el2_lsu_bus_buffer.scala 467:89] + wire _T_2704 = _T_2702 & _T_26; // @[el2_lsu_bus_buffer.scala 467:104] + wire _T_2690 = ~buf_age_2[1]; // @[el2_lsu_bus_buffer.scala 467:89] + wire _T_2692 = _T_2690 & _T_12; // @[el2_lsu_bus_buffer.scala 467:104] + wire _T_2684 = ~buf_age_2[0]; // @[el2_lsu_bus_buffer.scala 467:89] + wire _T_2686 = _T_2684 & _T_5; // @[el2_lsu_bus_buffer.scala 467:104] wire [3:0] buf_age_younger_2 = {_T_2704,1'h0,_T_2692,_T_2686}; // @[Cat.scala 29:58] - wire [3:0] _T_247 = ld_byte_hitvec_lo_0 & buf_age_younger_2; // @[el2_lsu_bus_buffer.scala 199:122] - wire _T_248 = |_T_247; // @[el2_lsu_bus_buffer.scala 199:144] - wire _T_249 = ~_T_248; // @[el2_lsu_bus_buffer.scala 199:99] - wire _T_250 = ld_byte_hitvec_lo_0[2] & _T_249; // @[el2_lsu_bus_buffer.scala 199:97] - wire _T_253 = _T_250 & _T_260; // @[el2_lsu_bus_buffer.scala 199:148] - reg [3:0] buf_ageQ_1; // @[el2_lsu_bus_buffer.scala 553:60] - wire _T_2578 = buf_ageQ_1[3] & _T_2623; // @[el2_lsu_bus_buffer.scala 465:76] - wire _T_2573 = buf_ageQ_1[2] & _T_2618; // @[el2_lsu_bus_buffer.scala 465:76] - wire _T_2568 = buf_ageQ_1[1] & _T_2613; // @[el2_lsu_bus_buffer.scala 465:76] - wire _T_2563 = buf_ageQ_1[0] & _T_2608; // @[el2_lsu_bus_buffer.scala 465:76] + wire [3:0] _T_247 = ld_byte_hitvec_lo_0 & buf_age_younger_2; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_248 = |_T_247; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_249 = ~_T_248; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_250 = ld_byte_hitvec_lo_0[2] & _T_249; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_253 = _T_250 & _T_260; // @[el2_lsu_bus_buffer.scala 200:148] + reg [3:0] buf_ageQ_1; // @[el2_lsu_bus_buffer.scala 554:60] + wire _T_2578 = buf_ageQ_1[3] & _T_2623; // @[el2_lsu_bus_buffer.scala 466:76] + wire _T_2573 = buf_ageQ_1[2] & _T_2618; // @[el2_lsu_bus_buffer.scala 466:76] + wire _T_2568 = buf_ageQ_1[1] & _T_2613; // @[el2_lsu_bus_buffer.scala 466:76] + wire _T_2563 = buf_ageQ_1[0] & _T_2608; // @[el2_lsu_bus_buffer.scala 466:76] wire [3:0] buf_age_1 = {_T_2578,_T_2573,_T_2568,_T_2563}; // @[Cat.scala 29:58] - wire _T_2675 = ~buf_age_1[3]; // @[el2_lsu_bus_buffer.scala 466:89] - wire _T_2677 = _T_2675 & _T_26; // @[el2_lsu_bus_buffer.scala 466:104] - wire _T_2669 = ~buf_age_1[2]; // @[el2_lsu_bus_buffer.scala 466:89] - wire _T_2671 = _T_2669 & _T_19; // @[el2_lsu_bus_buffer.scala 466:104] - wire _T_2657 = ~buf_age_1[0]; // @[el2_lsu_bus_buffer.scala 466:89] - wire _T_2659 = _T_2657 & _T_5; // @[el2_lsu_bus_buffer.scala 466:104] + wire _T_2675 = ~buf_age_1[3]; // @[el2_lsu_bus_buffer.scala 467:89] + wire _T_2677 = _T_2675 & _T_26; // @[el2_lsu_bus_buffer.scala 467:104] + wire _T_2669 = ~buf_age_1[2]; // @[el2_lsu_bus_buffer.scala 467:89] + wire _T_2671 = _T_2669 & _T_19; // @[el2_lsu_bus_buffer.scala 467:104] + wire _T_2657 = ~buf_age_1[0]; // @[el2_lsu_bus_buffer.scala 467:89] + wire _T_2659 = _T_2657 & _T_5; // @[el2_lsu_bus_buffer.scala 467:104] wire [3:0] buf_age_younger_1 = {_T_2677,_T_2671,1'h0,_T_2659}; // @[Cat.scala 29:58] - wire [3:0] _T_239 = ld_byte_hitvec_lo_0 & buf_age_younger_1; // @[el2_lsu_bus_buffer.scala 199:122] - wire _T_240 = |_T_239; // @[el2_lsu_bus_buffer.scala 199:144] - wire _T_241 = ~_T_240; // @[el2_lsu_bus_buffer.scala 199:99] - wire _T_242 = ld_byte_hitvec_lo_0[1] & _T_241; // @[el2_lsu_bus_buffer.scala 199:97] - wire _T_245 = _T_242 & _T_260; // @[el2_lsu_bus_buffer.scala 199:148] - reg [3:0] buf_ageQ_0; // @[el2_lsu_bus_buffer.scala 553:60] - wire _T_2555 = buf_ageQ_0[3] & _T_2623; // @[el2_lsu_bus_buffer.scala 465:76] - wire _T_2550 = buf_ageQ_0[2] & _T_2618; // @[el2_lsu_bus_buffer.scala 465:76] - wire _T_2545 = buf_ageQ_0[1] & _T_2613; // @[el2_lsu_bus_buffer.scala 465:76] - wire _T_2540 = buf_ageQ_0[0] & _T_2608; // @[el2_lsu_bus_buffer.scala 465:76] + wire [3:0] _T_239 = ld_byte_hitvec_lo_0 & buf_age_younger_1; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_240 = |_T_239; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_241 = ~_T_240; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_242 = ld_byte_hitvec_lo_0[1] & _T_241; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_245 = _T_242 & _T_260; // @[el2_lsu_bus_buffer.scala 200:148] + reg [3:0] buf_ageQ_0; // @[el2_lsu_bus_buffer.scala 554:60] + wire _T_2555 = buf_ageQ_0[3] & _T_2623; // @[el2_lsu_bus_buffer.scala 466:76] + wire _T_2550 = buf_ageQ_0[2] & _T_2618; // @[el2_lsu_bus_buffer.scala 466:76] + wire _T_2545 = buf_ageQ_0[1] & _T_2613; // @[el2_lsu_bus_buffer.scala 466:76] + wire _T_2540 = buf_ageQ_0[0] & _T_2608; // @[el2_lsu_bus_buffer.scala 466:76] wire [3:0] buf_age_0 = {_T_2555,_T_2550,_T_2545,_T_2540}; // @[Cat.scala 29:58] - wire _T_2648 = ~buf_age_0[3]; // @[el2_lsu_bus_buffer.scala 466:89] - wire _T_2650 = _T_2648 & _T_26; // @[el2_lsu_bus_buffer.scala 466:104] - wire _T_2642 = ~buf_age_0[2]; // @[el2_lsu_bus_buffer.scala 466:89] - wire _T_2644 = _T_2642 & _T_19; // @[el2_lsu_bus_buffer.scala 466:104] - wire _T_2636 = ~buf_age_0[1]; // @[el2_lsu_bus_buffer.scala 466:89] - wire _T_2638 = _T_2636 & _T_12; // @[el2_lsu_bus_buffer.scala 466:104] + wire _T_2648 = ~buf_age_0[3]; // @[el2_lsu_bus_buffer.scala 467:89] + wire _T_2650 = _T_2648 & _T_26; // @[el2_lsu_bus_buffer.scala 467:104] + wire _T_2642 = ~buf_age_0[2]; // @[el2_lsu_bus_buffer.scala 467:89] + wire _T_2644 = _T_2642 & _T_19; // @[el2_lsu_bus_buffer.scala 467:104] + wire _T_2636 = ~buf_age_0[1]; // @[el2_lsu_bus_buffer.scala 467:89] + wire _T_2638 = _T_2636 & _T_12; // @[el2_lsu_bus_buffer.scala 467:104] wire [3:0] buf_age_younger_0 = {_T_2650,_T_2644,_T_2638,1'h0}; // @[Cat.scala 29:58] - wire [3:0] _T_231 = ld_byte_hitvec_lo_0 & buf_age_younger_0; // @[el2_lsu_bus_buffer.scala 199:122] - wire _T_232 = |_T_231; // @[el2_lsu_bus_buffer.scala 199:144] - wire _T_233 = ~_T_232; // @[el2_lsu_bus_buffer.scala 199:99] - wire _T_234 = ld_byte_hitvec_lo_0[0] & _T_233; // @[el2_lsu_bus_buffer.scala 199:97] - wire _T_237 = _T_234 & _T_260; // @[el2_lsu_bus_buffer.scala 199:148] + wire [3:0] _T_231 = ld_byte_hitvec_lo_0 & buf_age_younger_0; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_232 = |_T_231; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_233 = ~_T_232; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_234 = ld_byte_hitvec_lo_0[0] & _T_233; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_237 = _T_234 & _T_260; // @[el2_lsu_bus_buffer.scala 200:148] wire [3:0] ld_byte_hitvecfn_lo_0 = {_T_261,_T_253,_T_245,_T_237}; // @[Cat.scala 29:58] - wire _T_56 = |ld_byte_hitvecfn_lo_0; // @[el2_lsu_bus_buffer.scala 191:73] - wire _T_58 = _T_56 | ld_byte_ibuf_hit_lo[0]; // @[el2_lsu_bus_buffer.scala 191:77] - wire _T_117 = ld_addr_hitvec_lo_3 & buf_byteen_3[1]; // @[el2_lsu_bus_buffer.scala 194:95] - wire _T_119 = _T_117 & ldst_byteen_lo_m[1]; // @[el2_lsu_bus_buffer.scala 194:114] - wire _T_113 = ld_addr_hitvec_lo_2 & buf_byteen_2[1]; // @[el2_lsu_bus_buffer.scala 194:95] - wire _T_115 = _T_113 & ldst_byteen_lo_m[1]; // @[el2_lsu_bus_buffer.scala 194:114] - wire _T_109 = ld_addr_hitvec_lo_1 & buf_byteen_1[1]; // @[el2_lsu_bus_buffer.scala 194:95] - wire _T_111 = _T_109 & ldst_byteen_lo_m[1]; // @[el2_lsu_bus_buffer.scala 194:114] - wire _T_105 = ld_addr_hitvec_lo_0 & buf_byteen_0[1]; // @[el2_lsu_bus_buffer.scala 194:95] - wire _T_107 = _T_105 & ldst_byteen_lo_m[1]; // @[el2_lsu_bus_buffer.scala 194:114] + wire _T_56 = |ld_byte_hitvecfn_lo_0; // @[el2_lsu_bus_buffer.scala 192:73] + wire _T_58 = _T_56 | ld_byte_ibuf_hit_lo[0]; // @[el2_lsu_bus_buffer.scala 192:77] + wire _T_117 = ld_addr_hitvec_lo_3 & buf_byteen_3[1]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_119 = _T_117 & ldst_byteen_lo_m[1]; // @[el2_lsu_bus_buffer.scala 195:114] + wire _T_113 = ld_addr_hitvec_lo_2 & buf_byteen_2[1]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_115 = _T_113 & ldst_byteen_lo_m[1]; // @[el2_lsu_bus_buffer.scala 195:114] + wire _T_109 = ld_addr_hitvec_lo_1 & buf_byteen_1[1]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_111 = _T_109 & ldst_byteen_lo_m[1]; // @[el2_lsu_bus_buffer.scala 195:114] + wire _T_105 = ld_addr_hitvec_lo_0 & buf_byteen_0[1]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_107 = _T_105 & ldst_byteen_lo_m[1]; // @[el2_lsu_bus_buffer.scala 195:114] wire [3:0] ld_byte_hitvec_lo_1 = {_T_119,_T_115,_T_111,_T_107}; // @[Cat.scala 29:58] - wire [3:0] _T_290 = ld_byte_hitvec_lo_1 & buf_age_younger_3; // @[el2_lsu_bus_buffer.scala 199:122] - wire _T_291 = |_T_290; // @[el2_lsu_bus_buffer.scala 199:144] - wire _T_292 = ~_T_291; // @[el2_lsu_bus_buffer.scala 199:99] - wire _T_293 = ld_byte_hitvec_lo_1[3] & _T_292; // @[el2_lsu_bus_buffer.scala 199:97] - wire _T_295 = ~ld_byte_ibuf_hit_lo[1]; // @[el2_lsu_bus_buffer.scala 199:150] - wire _T_296 = _T_293 & _T_295; // @[el2_lsu_bus_buffer.scala 199:148] - wire [3:0] _T_282 = ld_byte_hitvec_lo_1 & buf_age_younger_2; // @[el2_lsu_bus_buffer.scala 199:122] - wire _T_283 = |_T_282; // @[el2_lsu_bus_buffer.scala 199:144] - wire _T_284 = ~_T_283; // @[el2_lsu_bus_buffer.scala 199:99] - wire _T_285 = ld_byte_hitvec_lo_1[2] & _T_284; // @[el2_lsu_bus_buffer.scala 199:97] - wire _T_288 = _T_285 & _T_295; // @[el2_lsu_bus_buffer.scala 199:148] - wire [3:0] _T_274 = ld_byte_hitvec_lo_1 & buf_age_younger_1; // @[el2_lsu_bus_buffer.scala 199:122] - wire _T_275 = |_T_274; // @[el2_lsu_bus_buffer.scala 199:144] - wire _T_276 = ~_T_275; // @[el2_lsu_bus_buffer.scala 199:99] - wire _T_277 = ld_byte_hitvec_lo_1[1] & _T_276; // @[el2_lsu_bus_buffer.scala 199:97] - wire _T_280 = _T_277 & _T_295; // @[el2_lsu_bus_buffer.scala 199:148] - wire [3:0] _T_266 = ld_byte_hitvec_lo_1 & buf_age_younger_0; // @[el2_lsu_bus_buffer.scala 199:122] - wire _T_267 = |_T_266; // @[el2_lsu_bus_buffer.scala 199:144] - wire _T_268 = ~_T_267; // @[el2_lsu_bus_buffer.scala 199:99] - wire _T_269 = ld_byte_hitvec_lo_1[0] & _T_268; // @[el2_lsu_bus_buffer.scala 199:97] - wire _T_272 = _T_269 & _T_295; // @[el2_lsu_bus_buffer.scala 199:148] + wire [3:0] _T_290 = ld_byte_hitvec_lo_1 & buf_age_younger_3; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_291 = |_T_290; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_292 = ~_T_291; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_293 = ld_byte_hitvec_lo_1[3] & _T_292; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_295 = ~ld_byte_ibuf_hit_lo[1]; // @[el2_lsu_bus_buffer.scala 200:150] + wire _T_296 = _T_293 & _T_295; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] _T_282 = ld_byte_hitvec_lo_1 & buf_age_younger_2; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_283 = |_T_282; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_284 = ~_T_283; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_285 = ld_byte_hitvec_lo_1[2] & _T_284; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_288 = _T_285 & _T_295; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] _T_274 = ld_byte_hitvec_lo_1 & buf_age_younger_1; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_275 = |_T_274; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_276 = ~_T_275; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_277 = ld_byte_hitvec_lo_1[1] & _T_276; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_280 = _T_277 & _T_295; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] _T_266 = ld_byte_hitvec_lo_1 & buf_age_younger_0; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_267 = |_T_266; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_268 = ~_T_267; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_269 = ld_byte_hitvec_lo_1[0] & _T_268; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_272 = _T_269 & _T_295; // @[el2_lsu_bus_buffer.scala 200:148] wire [3:0] ld_byte_hitvecfn_lo_1 = {_T_296,_T_288,_T_280,_T_272}; // @[Cat.scala 29:58] - wire _T_59 = |ld_byte_hitvecfn_lo_1; // @[el2_lsu_bus_buffer.scala 191:73] - wire _T_61 = _T_59 | ld_byte_ibuf_hit_lo[1]; // @[el2_lsu_bus_buffer.scala 191:77] - wire _T_135 = ld_addr_hitvec_lo_3 & buf_byteen_3[2]; // @[el2_lsu_bus_buffer.scala 194:95] - wire _T_137 = _T_135 & ldst_byteen_lo_m[2]; // @[el2_lsu_bus_buffer.scala 194:114] - wire _T_131 = ld_addr_hitvec_lo_2 & buf_byteen_2[2]; // @[el2_lsu_bus_buffer.scala 194:95] - wire _T_133 = _T_131 & ldst_byteen_lo_m[2]; // @[el2_lsu_bus_buffer.scala 194:114] - wire _T_127 = ld_addr_hitvec_lo_1 & buf_byteen_1[2]; // @[el2_lsu_bus_buffer.scala 194:95] - wire _T_129 = _T_127 & ldst_byteen_lo_m[2]; // @[el2_lsu_bus_buffer.scala 194:114] - wire _T_123 = ld_addr_hitvec_lo_0 & buf_byteen_0[2]; // @[el2_lsu_bus_buffer.scala 194:95] - wire _T_125 = _T_123 & ldst_byteen_lo_m[2]; // @[el2_lsu_bus_buffer.scala 194:114] + wire _T_59 = |ld_byte_hitvecfn_lo_1; // @[el2_lsu_bus_buffer.scala 192:73] + wire _T_61 = _T_59 | ld_byte_ibuf_hit_lo[1]; // @[el2_lsu_bus_buffer.scala 192:77] + wire _T_135 = ld_addr_hitvec_lo_3 & buf_byteen_3[2]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_137 = _T_135 & ldst_byteen_lo_m[2]; // @[el2_lsu_bus_buffer.scala 195:114] + wire _T_131 = ld_addr_hitvec_lo_2 & buf_byteen_2[2]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_133 = _T_131 & ldst_byteen_lo_m[2]; // @[el2_lsu_bus_buffer.scala 195:114] + wire _T_127 = ld_addr_hitvec_lo_1 & buf_byteen_1[2]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_129 = _T_127 & ldst_byteen_lo_m[2]; // @[el2_lsu_bus_buffer.scala 195:114] + wire _T_123 = ld_addr_hitvec_lo_0 & buf_byteen_0[2]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_125 = _T_123 & ldst_byteen_lo_m[2]; // @[el2_lsu_bus_buffer.scala 195:114] wire [3:0] ld_byte_hitvec_lo_2 = {_T_137,_T_133,_T_129,_T_125}; // @[Cat.scala 29:58] - wire [3:0] _T_325 = ld_byte_hitvec_lo_2 & buf_age_younger_3; // @[el2_lsu_bus_buffer.scala 199:122] - wire _T_326 = |_T_325; // @[el2_lsu_bus_buffer.scala 199:144] - wire _T_327 = ~_T_326; // @[el2_lsu_bus_buffer.scala 199:99] - wire _T_328 = ld_byte_hitvec_lo_2[3] & _T_327; // @[el2_lsu_bus_buffer.scala 199:97] - wire _T_330 = ~ld_byte_ibuf_hit_lo[2]; // @[el2_lsu_bus_buffer.scala 199:150] - wire _T_331 = _T_328 & _T_330; // @[el2_lsu_bus_buffer.scala 199:148] - wire [3:0] _T_317 = ld_byte_hitvec_lo_2 & buf_age_younger_2; // @[el2_lsu_bus_buffer.scala 199:122] - wire _T_318 = |_T_317; // @[el2_lsu_bus_buffer.scala 199:144] - wire _T_319 = ~_T_318; // @[el2_lsu_bus_buffer.scala 199:99] - wire _T_320 = ld_byte_hitvec_lo_2[2] & _T_319; // @[el2_lsu_bus_buffer.scala 199:97] - wire _T_323 = _T_320 & _T_330; // @[el2_lsu_bus_buffer.scala 199:148] - wire [3:0] _T_309 = ld_byte_hitvec_lo_2 & buf_age_younger_1; // @[el2_lsu_bus_buffer.scala 199:122] - wire _T_310 = |_T_309; // @[el2_lsu_bus_buffer.scala 199:144] - wire _T_311 = ~_T_310; // @[el2_lsu_bus_buffer.scala 199:99] - wire _T_312 = ld_byte_hitvec_lo_2[1] & _T_311; // @[el2_lsu_bus_buffer.scala 199:97] - wire _T_315 = _T_312 & _T_330; // @[el2_lsu_bus_buffer.scala 199:148] - wire [3:0] _T_301 = ld_byte_hitvec_lo_2 & buf_age_younger_0; // @[el2_lsu_bus_buffer.scala 199:122] - wire _T_302 = |_T_301; // @[el2_lsu_bus_buffer.scala 199:144] - wire _T_303 = ~_T_302; // @[el2_lsu_bus_buffer.scala 199:99] - wire _T_304 = ld_byte_hitvec_lo_2[0] & _T_303; // @[el2_lsu_bus_buffer.scala 199:97] - wire _T_307 = _T_304 & _T_330; // @[el2_lsu_bus_buffer.scala 199:148] + wire [3:0] _T_325 = ld_byte_hitvec_lo_2 & buf_age_younger_3; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_326 = |_T_325; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_327 = ~_T_326; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_328 = ld_byte_hitvec_lo_2[3] & _T_327; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_330 = ~ld_byte_ibuf_hit_lo[2]; // @[el2_lsu_bus_buffer.scala 200:150] + wire _T_331 = _T_328 & _T_330; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] _T_317 = ld_byte_hitvec_lo_2 & buf_age_younger_2; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_318 = |_T_317; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_319 = ~_T_318; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_320 = ld_byte_hitvec_lo_2[2] & _T_319; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_323 = _T_320 & _T_330; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] _T_309 = ld_byte_hitvec_lo_2 & buf_age_younger_1; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_310 = |_T_309; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_311 = ~_T_310; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_312 = ld_byte_hitvec_lo_2[1] & _T_311; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_315 = _T_312 & _T_330; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] _T_301 = ld_byte_hitvec_lo_2 & buf_age_younger_0; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_302 = |_T_301; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_303 = ~_T_302; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_304 = ld_byte_hitvec_lo_2[0] & _T_303; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_307 = _T_304 & _T_330; // @[el2_lsu_bus_buffer.scala 200:148] wire [3:0] ld_byte_hitvecfn_lo_2 = {_T_331,_T_323,_T_315,_T_307}; // @[Cat.scala 29:58] - wire _T_62 = |ld_byte_hitvecfn_lo_2; // @[el2_lsu_bus_buffer.scala 191:73] - wire _T_64 = _T_62 | ld_byte_ibuf_hit_lo[2]; // @[el2_lsu_bus_buffer.scala 191:77] - wire _T_153 = ld_addr_hitvec_lo_3 & buf_byteen_3[3]; // @[el2_lsu_bus_buffer.scala 194:95] - wire _T_155 = _T_153 & ldst_byteen_lo_m[3]; // @[el2_lsu_bus_buffer.scala 194:114] - wire _T_149 = ld_addr_hitvec_lo_2 & buf_byteen_2[3]; // @[el2_lsu_bus_buffer.scala 194:95] - wire _T_151 = _T_149 & ldst_byteen_lo_m[3]; // @[el2_lsu_bus_buffer.scala 194:114] - wire _T_145 = ld_addr_hitvec_lo_1 & buf_byteen_1[3]; // @[el2_lsu_bus_buffer.scala 194:95] - wire _T_147 = _T_145 & ldst_byteen_lo_m[3]; // @[el2_lsu_bus_buffer.scala 194:114] - wire _T_141 = ld_addr_hitvec_lo_0 & buf_byteen_0[3]; // @[el2_lsu_bus_buffer.scala 194:95] - wire _T_143 = _T_141 & ldst_byteen_lo_m[3]; // @[el2_lsu_bus_buffer.scala 194:114] + wire _T_62 = |ld_byte_hitvecfn_lo_2; // @[el2_lsu_bus_buffer.scala 192:73] + wire _T_64 = _T_62 | ld_byte_ibuf_hit_lo[2]; // @[el2_lsu_bus_buffer.scala 192:77] + wire _T_153 = ld_addr_hitvec_lo_3 & buf_byteen_3[3]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_155 = _T_153 & ldst_byteen_lo_m[3]; // @[el2_lsu_bus_buffer.scala 195:114] + wire _T_149 = ld_addr_hitvec_lo_2 & buf_byteen_2[3]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_151 = _T_149 & ldst_byteen_lo_m[3]; // @[el2_lsu_bus_buffer.scala 195:114] + wire _T_145 = ld_addr_hitvec_lo_1 & buf_byteen_1[3]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_147 = _T_145 & ldst_byteen_lo_m[3]; // @[el2_lsu_bus_buffer.scala 195:114] + wire _T_141 = ld_addr_hitvec_lo_0 & buf_byteen_0[3]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_143 = _T_141 & ldst_byteen_lo_m[3]; // @[el2_lsu_bus_buffer.scala 195:114] wire [3:0] ld_byte_hitvec_lo_3 = {_T_155,_T_151,_T_147,_T_143}; // @[Cat.scala 29:58] - wire [3:0] _T_360 = ld_byte_hitvec_lo_3 & buf_age_younger_3; // @[el2_lsu_bus_buffer.scala 199:122] - wire _T_361 = |_T_360; // @[el2_lsu_bus_buffer.scala 199:144] - wire _T_362 = ~_T_361; // @[el2_lsu_bus_buffer.scala 199:99] - wire _T_363 = ld_byte_hitvec_lo_3[3] & _T_362; // @[el2_lsu_bus_buffer.scala 199:97] - wire _T_365 = ~ld_byte_ibuf_hit_lo[3]; // @[el2_lsu_bus_buffer.scala 199:150] - wire _T_366 = _T_363 & _T_365; // @[el2_lsu_bus_buffer.scala 199:148] - wire [3:0] _T_352 = ld_byte_hitvec_lo_3 & buf_age_younger_2; // @[el2_lsu_bus_buffer.scala 199:122] - wire _T_353 = |_T_352; // @[el2_lsu_bus_buffer.scala 199:144] - wire _T_354 = ~_T_353; // @[el2_lsu_bus_buffer.scala 199:99] - wire _T_355 = ld_byte_hitvec_lo_3[2] & _T_354; // @[el2_lsu_bus_buffer.scala 199:97] - wire _T_358 = _T_355 & _T_365; // @[el2_lsu_bus_buffer.scala 199:148] - wire [3:0] _T_344 = ld_byte_hitvec_lo_3 & buf_age_younger_1; // @[el2_lsu_bus_buffer.scala 199:122] - wire _T_345 = |_T_344; // @[el2_lsu_bus_buffer.scala 199:144] - wire _T_346 = ~_T_345; // @[el2_lsu_bus_buffer.scala 199:99] - wire _T_347 = ld_byte_hitvec_lo_3[1] & _T_346; // @[el2_lsu_bus_buffer.scala 199:97] - wire _T_350 = _T_347 & _T_365; // @[el2_lsu_bus_buffer.scala 199:148] - wire [3:0] _T_336 = ld_byte_hitvec_lo_3 & buf_age_younger_0; // @[el2_lsu_bus_buffer.scala 199:122] - wire _T_337 = |_T_336; // @[el2_lsu_bus_buffer.scala 199:144] - wire _T_338 = ~_T_337; // @[el2_lsu_bus_buffer.scala 199:99] - wire _T_339 = ld_byte_hitvec_lo_3[0] & _T_338; // @[el2_lsu_bus_buffer.scala 199:97] - wire _T_342 = _T_339 & _T_365; // @[el2_lsu_bus_buffer.scala 199:148] + wire [3:0] _T_360 = ld_byte_hitvec_lo_3 & buf_age_younger_3; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_361 = |_T_360; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_362 = ~_T_361; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_363 = ld_byte_hitvec_lo_3[3] & _T_362; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_365 = ~ld_byte_ibuf_hit_lo[3]; // @[el2_lsu_bus_buffer.scala 200:150] + wire _T_366 = _T_363 & _T_365; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] _T_352 = ld_byte_hitvec_lo_3 & buf_age_younger_2; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_353 = |_T_352; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_354 = ~_T_353; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_355 = ld_byte_hitvec_lo_3[2] & _T_354; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_358 = _T_355 & _T_365; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] _T_344 = ld_byte_hitvec_lo_3 & buf_age_younger_1; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_345 = |_T_344; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_346 = ~_T_345; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_347 = ld_byte_hitvec_lo_3[1] & _T_346; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_350 = _T_347 & _T_365; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] _T_336 = ld_byte_hitvec_lo_3 & buf_age_younger_0; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_337 = |_T_336; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_338 = ~_T_337; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_339 = ld_byte_hitvec_lo_3[0] & _T_338; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_342 = _T_339 & _T_365; // @[el2_lsu_bus_buffer.scala 200:148] wire [3:0] ld_byte_hitvecfn_lo_3 = {_T_366,_T_358,_T_350,_T_342}; // @[Cat.scala 29:58] - wire _T_65 = |ld_byte_hitvecfn_lo_3; // @[el2_lsu_bus_buffer.scala 191:73] - wire _T_67 = _T_65 | ld_byte_ibuf_hit_lo[3]; // @[el2_lsu_bus_buffer.scala 191:77] + wire _T_65 = |ld_byte_hitvecfn_lo_3; // @[el2_lsu_bus_buffer.scala 192:73] + wire _T_67 = _T_65 | ld_byte_ibuf_hit_lo[3]; // @[el2_lsu_bus_buffer.scala 192:77] wire [2:0] _T_69 = {_T_67,_T_64,_T_61}; // @[Cat.scala 29:58] - wire _T_171 = ld_addr_hitvec_hi_3 & buf_byteen_3[0]; // @[el2_lsu_bus_buffer.scala 195:95] - wire _T_173 = _T_171 & ldst_byteen_hi_m[0]; // @[el2_lsu_bus_buffer.scala 195:114] - wire _T_167 = ld_addr_hitvec_hi_2 & buf_byteen_2[0]; // @[el2_lsu_bus_buffer.scala 195:95] - wire _T_169 = _T_167 & ldst_byteen_hi_m[0]; // @[el2_lsu_bus_buffer.scala 195:114] - wire _T_163 = ld_addr_hitvec_hi_1 & buf_byteen_1[0]; // @[el2_lsu_bus_buffer.scala 195:95] - wire _T_165 = _T_163 & ldst_byteen_hi_m[0]; // @[el2_lsu_bus_buffer.scala 195:114] - wire _T_159 = ld_addr_hitvec_hi_0 & buf_byteen_0[0]; // @[el2_lsu_bus_buffer.scala 195:95] - wire _T_161 = _T_159 & ldst_byteen_hi_m[0]; // @[el2_lsu_bus_buffer.scala 195:114] + wire _T_171 = ld_addr_hitvec_hi_3 & buf_byteen_3[0]; // @[el2_lsu_bus_buffer.scala 196:95] + wire _T_173 = _T_171 & ldst_byteen_hi_m[0]; // @[el2_lsu_bus_buffer.scala 196:114] + wire _T_167 = ld_addr_hitvec_hi_2 & buf_byteen_2[0]; // @[el2_lsu_bus_buffer.scala 196:95] + wire _T_169 = _T_167 & ldst_byteen_hi_m[0]; // @[el2_lsu_bus_buffer.scala 196:114] + wire _T_163 = ld_addr_hitvec_hi_1 & buf_byteen_1[0]; // @[el2_lsu_bus_buffer.scala 196:95] + wire _T_165 = _T_163 & ldst_byteen_hi_m[0]; // @[el2_lsu_bus_buffer.scala 196:114] + wire _T_159 = ld_addr_hitvec_hi_0 & buf_byteen_0[0]; // @[el2_lsu_bus_buffer.scala 196:95] + wire _T_161 = _T_159 & ldst_byteen_hi_m[0]; // @[el2_lsu_bus_buffer.scala 196:114] wire [3:0] ld_byte_hitvec_hi_0 = {_T_173,_T_169,_T_165,_T_161}; // @[Cat.scala 29:58] - wire [3:0] _T_395 = ld_byte_hitvec_hi_0 & buf_age_younger_3; // @[el2_lsu_bus_buffer.scala 200:122] - wire _T_396 = |_T_395; // @[el2_lsu_bus_buffer.scala 200:144] - wire _T_397 = ~_T_396; // @[el2_lsu_bus_buffer.scala 200:99] - wire _T_398 = ld_byte_hitvec_hi_0[3] & _T_397; // @[el2_lsu_bus_buffer.scala 200:97] - wire _T_517 = io_end_addr_m[31:2] == ibuf_addr[31:2]; // @[el2_lsu_bus_buffer.scala 206:51] - wire _T_518 = _T_517 & ibuf_write; // @[el2_lsu_bus_buffer.scala 206:73] - wire _T_519 = _T_518 & ibuf_valid; // @[el2_lsu_bus_buffer.scala 206:86] - wire ld_addr_ibuf_hit_hi = _T_519 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 206:99] + wire [3:0] _T_395 = ld_byte_hitvec_hi_0 & buf_age_younger_3; // @[el2_lsu_bus_buffer.scala 201:122] + wire _T_396 = |_T_395; // @[el2_lsu_bus_buffer.scala 201:144] + wire _T_397 = ~_T_396; // @[el2_lsu_bus_buffer.scala 201:99] + wire _T_398 = ld_byte_hitvec_hi_0[3] & _T_397; // @[el2_lsu_bus_buffer.scala 201:97] + wire _T_517 = io_end_addr_m[31:2] == ibuf_addr[31:2]; // @[el2_lsu_bus_buffer.scala 207:51] + wire _T_518 = _T_517 & ibuf_write; // @[el2_lsu_bus_buffer.scala 207:73] + wire _T_519 = _T_518 & ibuf_valid; // @[el2_lsu_bus_buffer.scala 207:86] + wire ld_addr_ibuf_hit_hi = _T_519 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 207:99] wire [3:0] _T_525 = ld_addr_ibuf_hit_hi ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] _T_526 = _T_525 & ibuf_byteen; // @[el2_lsu_bus_buffer.scala 211:55] - wire [3:0] ld_byte_ibuf_hit_hi = _T_526 & ldst_byteen_hi_m; // @[el2_lsu_bus_buffer.scala 211:69] - wire _T_400 = ~ld_byte_ibuf_hit_hi[0]; // @[el2_lsu_bus_buffer.scala 200:150] - wire _T_401 = _T_398 & _T_400; // @[el2_lsu_bus_buffer.scala 200:148] - wire [3:0] _T_387 = ld_byte_hitvec_hi_0 & buf_age_younger_2; // @[el2_lsu_bus_buffer.scala 200:122] - wire _T_388 = |_T_387; // @[el2_lsu_bus_buffer.scala 200:144] - wire _T_389 = ~_T_388; // @[el2_lsu_bus_buffer.scala 200:99] - wire _T_390 = ld_byte_hitvec_hi_0[2] & _T_389; // @[el2_lsu_bus_buffer.scala 200:97] - wire _T_393 = _T_390 & _T_400; // @[el2_lsu_bus_buffer.scala 200:148] - wire [3:0] _T_379 = ld_byte_hitvec_hi_0 & buf_age_younger_1; // @[el2_lsu_bus_buffer.scala 200:122] - wire _T_380 = |_T_379; // @[el2_lsu_bus_buffer.scala 200:144] - wire _T_381 = ~_T_380; // @[el2_lsu_bus_buffer.scala 200:99] - wire _T_382 = ld_byte_hitvec_hi_0[1] & _T_381; // @[el2_lsu_bus_buffer.scala 200:97] - wire _T_385 = _T_382 & _T_400; // @[el2_lsu_bus_buffer.scala 200:148] - wire [3:0] _T_371 = ld_byte_hitvec_hi_0 & buf_age_younger_0; // @[el2_lsu_bus_buffer.scala 200:122] - wire _T_372 = |_T_371; // @[el2_lsu_bus_buffer.scala 200:144] - wire _T_373 = ~_T_372; // @[el2_lsu_bus_buffer.scala 200:99] - wire _T_374 = ld_byte_hitvec_hi_0[0] & _T_373; // @[el2_lsu_bus_buffer.scala 200:97] - wire _T_377 = _T_374 & _T_400; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] _T_526 = _T_525 & ibuf_byteen; // @[el2_lsu_bus_buffer.scala 212:55] + wire [3:0] ld_byte_ibuf_hit_hi = _T_526 & ldst_byteen_hi_m; // @[el2_lsu_bus_buffer.scala 212:69] + wire _T_400 = ~ld_byte_ibuf_hit_hi[0]; // @[el2_lsu_bus_buffer.scala 201:150] + wire _T_401 = _T_398 & _T_400; // @[el2_lsu_bus_buffer.scala 201:148] + wire [3:0] _T_387 = ld_byte_hitvec_hi_0 & buf_age_younger_2; // @[el2_lsu_bus_buffer.scala 201:122] + wire _T_388 = |_T_387; // @[el2_lsu_bus_buffer.scala 201:144] + wire _T_389 = ~_T_388; // @[el2_lsu_bus_buffer.scala 201:99] + wire _T_390 = ld_byte_hitvec_hi_0[2] & _T_389; // @[el2_lsu_bus_buffer.scala 201:97] + wire _T_393 = _T_390 & _T_400; // @[el2_lsu_bus_buffer.scala 201:148] + wire [3:0] _T_379 = ld_byte_hitvec_hi_0 & buf_age_younger_1; // @[el2_lsu_bus_buffer.scala 201:122] + wire _T_380 = |_T_379; // @[el2_lsu_bus_buffer.scala 201:144] + wire _T_381 = ~_T_380; // @[el2_lsu_bus_buffer.scala 201:99] + wire _T_382 = ld_byte_hitvec_hi_0[1] & _T_381; // @[el2_lsu_bus_buffer.scala 201:97] + wire _T_385 = _T_382 & _T_400; // @[el2_lsu_bus_buffer.scala 201:148] + wire [3:0] _T_371 = ld_byte_hitvec_hi_0 & buf_age_younger_0; // @[el2_lsu_bus_buffer.scala 201:122] + wire _T_372 = |_T_371; // @[el2_lsu_bus_buffer.scala 201:144] + wire _T_373 = ~_T_372; // @[el2_lsu_bus_buffer.scala 201:99] + wire _T_374 = ld_byte_hitvec_hi_0[0] & _T_373; // @[el2_lsu_bus_buffer.scala 201:97] + wire _T_377 = _T_374 & _T_400; // @[el2_lsu_bus_buffer.scala 201:148] wire [3:0] ld_byte_hitvecfn_hi_0 = {_T_401,_T_393,_T_385,_T_377}; // @[Cat.scala 29:58] - wire _T_71 = |ld_byte_hitvecfn_hi_0; // @[el2_lsu_bus_buffer.scala 192:73] - wire _T_73 = _T_71 | ld_byte_ibuf_hit_hi[0]; // @[el2_lsu_bus_buffer.scala 192:77] - wire _T_189 = ld_addr_hitvec_hi_3 & buf_byteen_3[1]; // @[el2_lsu_bus_buffer.scala 195:95] - wire _T_191 = _T_189 & ldst_byteen_hi_m[1]; // @[el2_lsu_bus_buffer.scala 195:114] - wire _T_185 = ld_addr_hitvec_hi_2 & buf_byteen_2[1]; // @[el2_lsu_bus_buffer.scala 195:95] - wire _T_187 = _T_185 & ldst_byteen_hi_m[1]; // @[el2_lsu_bus_buffer.scala 195:114] - wire _T_181 = ld_addr_hitvec_hi_1 & buf_byteen_1[1]; // @[el2_lsu_bus_buffer.scala 195:95] - wire _T_183 = _T_181 & ldst_byteen_hi_m[1]; // @[el2_lsu_bus_buffer.scala 195:114] - wire _T_177 = ld_addr_hitvec_hi_0 & buf_byteen_0[1]; // @[el2_lsu_bus_buffer.scala 195:95] - wire _T_179 = _T_177 & ldst_byteen_hi_m[1]; // @[el2_lsu_bus_buffer.scala 195:114] + wire _T_71 = |ld_byte_hitvecfn_hi_0; // @[el2_lsu_bus_buffer.scala 193:73] + wire _T_73 = _T_71 | ld_byte_ibuf_hit_hi[0]; // @[el2_lsu_bus_buffer.scala 193:77] + wire _T_189 = ld_addr_hitvec_hi_3 & buf_byteen_3[1]; // @[el2_lsu_bus_buffer.scala 196:95] + wire _T_191 = _T_189 & ldst_byteen_hi_m[1]; // @[el2_lsu_bus_buffer.scala 196:114] + wire _T_185 = ld_addr_hitvec_hi_2 & buf_byteen_2[1]; // @[el2_lsu_bus_buffer.scala 196:95] + wire _T_187 = _T_185 & ldst_byteen_hi_m[1]; // @[el2_lsu_bus_buffer.scala 196:114] + wire _T_181 = ld_addr_hitvec_hi_1 & buf_byteen_1[1]; // @[el2_lsu_bus_buffer.scala 196:95] + wire _T_183 = _T_181 & ldst_byteen_hi_m[1]; // @[el2_lsu_bus_buffer.scala 196:114] + wire _T_177 = ld_addr_hitvec_hi_0 & buf_byteen_0[1]; // @[el2_lsu_bus_buffer.scala 196:95] + wire _T_179 = _T_177 & ldst_byteen_hi_m[1]; // @[el2_lsu_bus_buffer.scala 196:114] wire [3:0] ld_byte_hitvec_hi_1 = {_T_191,_T_187,_T_183,_T_179}; // @[Cat.scala 29:58] - wire [3:0] _T_430 = ld_byte_hitvec_hi_1 & buf_age_younger_3; // @[el2_lsu_bus_buffer.scala 200:122] - wire _T_431 = |_T_430; // @[el2_lsu_bus_buffer.scala 200:144] - wire _T_432 = ~_T_431; // @[el2_lsu_bus_buffer.scala 200:99] - wire _T_433 = ld_byte_hitvec_hi_1[3] & _T_432; // @[el2_lsu_bus_buffer.scala 200:97] - wire _T_435 = ~ld_byte_ibuf_hit_hi[1]; // @[el2_lsu_bus_buffer.scala 200:150] - wire _T_436 = _T_433 & _T_435; // @[el2_lsu_bus_buffer.scala 200:148] - wire [3:0] _T_422 = ld_byte_hitvec_hi_1 & buf_age_younger_2; // @[el2_lsu_bus_buffer.scala 200:122] - wire _T_423 = |_T_422; // @[el2_lsu_bus_buffer.scala 200:144] - wire _T_424 = ~_T_423; // @[el2_lsu_bus_buffer.scala 200:99] - wire _T_425 = ld_byte_hitvec_hi_1[2] & _T_424; // @[el2_lsu_bus_buffer.scala 200:97] - wire _T_428 = _T_425 & _T_435; // @[el2_lsu_bus_buffer.scala 200:148] - wire [3:0] _T_414 = ld_byte_hitvec_hi_1 & buf_age_younger_1; // @[el2_lsu_bus_buffer.scala 200:122] - wire _T_415 = |_T_414; // @[el2_lsu_bus_buffer.scala 200:144] - wire _T_416 = ~_T_415; // @[el2_lsu_bus_buffer.scala 200:99] - wire _T_417 = ld_byte_hitvec_hi_1[1] & _T_416; // @[el2_lsu_bus_buffer.scala 200:97] - wire _T_420 = _T_417 & _T_435; // @[el2_lsu_bus_buffer.scala 200:148] - wire [3:0] _T_406 = ld_byte_hitvec_hi_1 & buf_age_younger_0; // @[el2_lsu_bus_buffer.scala 200:122] - wire _T_407 = |_T_406; // @[el2_lsu_bus_buffer.scala 200:144] - wire _T_408 = ~_T_407; // @[el2_lsu_bus_buffer.scala 200:99] - wire _T_409 = ld_byte_hitvec_hi_1[0] & _T_408; // @[el2_lsu_bus_buffer.scala 200:97] - wire _T_412 = _T_409 & _T_435; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] _T_430 = ld_byte_hitvec_hi_1 & buf_age_younger_3; // @[el2_lsu_bus_buffer.scala 201:122] + wire _T_431 = |_T_430; // @[el2_lsu_bus_buffer.scala 201:144] + wire _T_432 = ~_T_431; // @[el2_lsu_bus_buffer.scala 201:99] + wire _T_433 = ld_byte_hitvec_hi_1[3] & _T_432; // @[el2_lsu_bus_buffer.scala 201:97] + wire _T_435 = ~ld_byte_ibuf_hit_hi[1]; // @[el2_lsu_bus_buffer.scala 201:150] + wire _T_436 = _T_433 & _T_435; // @[el2_lsu_bus_buffer.scala 201:148] + wire [3:0] _T_422 = ld_byte_hitvec_hi_1 & buf_age_younger_2; // @[el2_lsu_bus_buffer.scala 201:122] + wire _T_423 = |_T_422; // @[el2_lsu_bus_buffer.scala 201:144] + wire _T_424 = ~_T_423; // @[el2_lsu_bus_buffer.scala 201:99] + wire _T_425 = ld_byte_hitvec_hi_1[2] & _T_424; // @[el2_lsu_bus_buffer.scala 201:97] + wire _T_428 = _T_425 & _T_435; // @[el2_lsu_bus_buffer.scala 201:148] + wire [3:0] _T_414 = ld_byte_hitvec_hi_1 & buf_age_younger_1; // @[el2_lsu_bus_buffer.scala 201:122] + wire _T_415 = |_T_414; // @[el2_lsu_bus_buffer.scala 201:144] + wire _T_416 = ~_T_415; // @[el2_lsu_bus_buffer.scala 201:99] + wire _T_417 = ld_byte_hitvec_hi_1[1] & _T_416; // @[el2_lsu_bus_buffer.scala 201:97] + wire _T_420 = _T_417 & _T_435; // @[el2_lsu_bus_buffer.scala 201:148] + wire [3:0] _T_406 = ld_byte_hitvec_hi_1 & buf_age_younger_0; // @[el2_lsu_bus_buffer.scala 201:122] + wire _T_407 = |_T_406; // @[el2_lsu_bus_buffer.scala 201:144] + wire _T_408 = ~_T_407; // @[el2_lsu_bus_buffer.scala 201:99] + wire _T_409 = ld_byte_hitvec_hi_1[0] & _T_408; // @[el2_lsu_bus_buffer.scala 201:97] + wire _T_412 = _T_409 & _T_435; // @[el2_lsu_bus_buffer.scala 201:148] wire [3:0] ld_byte_hitvecfn_hi_1 = {_T_436,_T_428,_T_420,_T_412}; // @[Cat.scala 29:58] - wire _T_74 = |ld_byte_hitvecfn_hi_1; // @[el2_lsu_bus_buffer.scala 192:73] - wire _T_76 = _T_74 | ld_byte_ibuf_hit_hi[1]; // @[el2_lsu_bus_buffer.scala 192:77] - wire _T_207 = ld_addr_hitvec_hi_3 & buf_byteen_3[2]; // @[el2_lsu_bus_buffer.scala 195:95] - wire _T_209 = _T_207 & ldst_byteen_hi_m[2]; // @[el2_lsu_bus_buffer.scala 195:114] - wire _T_203 = ld_addr_hitvec_hi_2 & buf_byteen_2[2]; // @[el2_lsu_bus_buffer.scala 195:95] - wire _T_205 = _T_203 & ldst_byteen_hi_m[2]; // @[el2_lsu_bus_buffer.scala 195:114] - wire _T_199 = ld_addr_hitvec_hi_1 & buf_byteen_1[2]; // @[el2_lsu_bus_buffer.scala 195:95] - wire _T_201 = _T_199 & ldst_byteen_hi_m[2]; // @[el2_lsu_bus_buffer.scala 195:114] - wire _T_195 = ld_addr_hitvec_hi_0 & buf_byteen_0[2]; // @[el2_lsu_bus_buffer.scala 195:95] - wire _T_197 = _T_195 & ldst_byteen_hi_m[2]; // @[el2_lsu_bus_buffer.scala 195:114] + wire _T_74 = |ld_byte_hitvecfn_hi_1; // @[el2_lsu_bus_buffer.scala 193:73] + wire _T_76 = _T_74 | ld_byte_ibuf_hit_hi[1]; // @[el2_lsu_bus_buffer.scala 193:77] + wire _T_207 = ld_addr_hitvec_hi_3 & buf_byteen_3[2]; // @[el2_lsu_bus_buffer.scala 196:95] + wire _T_209 = _T_207 & ldst_byteen_hi_m[2]; // @[el2_lsu_bus_buffer.scala 196:114] + wire _T_203 = ld_addr_hitvec_hi_2 & buf_byteen_2[2]; // @[el2_lsu_bus_buffer.scala 196:95] + wire _T_205 = _T_203 & ldst_byteen_hi_m[2]; // @[el2_lsu_bus_buffer.scala 196:114] + wire _T_199 = ld_addr_hitvec_hi_1 & buf_byteen_1[2]; // @[el2_lsu_bus_buffer.scala 196:95] + wire _T_201 = _T_199 & ldst_byteen_hi_m[2]; // @[el2_lsu_bus_buffer.scala 196:114] + wire _T_195 = ld_addr_hitvec_hi_0 & buf_byteen_0[2]; // @[el2_lsu_bus_buffer.scala 196:95] + wire _T_197 = _T_195 & ldst_byteen_hi_m[2]; // @[el2_lsu_bus_buffer.scala 196:114] wire [3:0] ld_byte_hitvec_hi_2 = {_T_209,_T_205,_T_201,_T_197}; // @[Cat.scala 29:58] - wire [3:0] _T_465 = ld_byte_hitvec_hi_2 & buf_age_younger_3; // @[el2_lsu_bus_buffer.scala 200:122] - wire _T_466 = |_T_465; // @[el2_lsu_bus_buffer.scala 200:144] - wire _T_467 = ~_T_466; // @[el2_lsu_bus_buffer.scala 200:99] - wire _T_468 = ld_byte_hitvec_hi_2[3] & _T_467; // @[el2_lsu_bus_buffer.scala 200:97] - wire _T_470 = ~ld_byte_ibuf_hit_hi[2]; // @[el2_lsu_bus_buffer.scala 200:150] - wire _T_471 = _T_468 & _T_470; // @[el2_lsu_bus_buffer.scala 200:148] - wire [3:0] _T_457 = ld_byte_hitvec_hi_2 & buf_age_younger_2; // @[el2_lsu_bus_buffer.scala 200:122] - wire _T_458 = |_T_457; // @[el2_lsu_bus_buffer.scala 200:144] - wire _T_459 = ~_T_458; // @[el2_lsu_bus_buffer.scala 200:99] - wire _T_460 = ld_byte_hitvec_hi_2[2] & _T_459; // @[el2_lsu_bus_buffer.scala 200:97] - wire _T_463 = _T_460 & _T_470; // @[el2_lsu_bus_buffer.scala 200:148] - wire [3:0] _T_449 = ld_byte_hitvec_hi_2 & buf_age_younger_1; // @[el2_lsu_bus_buffer.scala 200:122] - wire _T_450 = |_T_449; // @[el2_lsu_bus_buffer.scala 200:144] - wire _T_451 = ~_T_450; // @[el2_lsu_bus_buffer.scala 200:99] - wire _T_452 = ld_byte_hitvec_hi_2[1] & _T_451; // @[el2_lsu_bus_buffer.scala 200:97] - wire _T_455 = _T_452 & _T_470; // @[el2_lsu_bus_buffer.scala 200:148] - wire [3:0] _T_441 = ld_byte_hitvec_hi_2 & buf_age_younger_0; // @[el2_lsu_bus_buffer.scala 200:122] - wire _T_442 = |_T_441; // @[el2_lsu_bus_buffer.scala 200:144] - wire _T_443 = ~_T_442; // @[el2_lsu_bus_buffer.scala 200:99] - wire _T_444 = ld_byte_hitvec_hi_2[0] & _T_443; // @[el2_lsu_bus_buffer.scala 200:97] - wire _T_447 = _T_444 & _T_470; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] _T_465 = ld_byte_hitvec_hi_2 & buf_age_younger_3; // @[el2_lsu_bus_buffer.scala 201:122] + wire _T_466 = |_T_465; // @[el2_lsu_bus_buffer.scala 201:144] + wire _T_467 = ~_T_466; // @[el2_lsu_bus_buffer.scala 201:99] + wire _T_468 = ld_byte_hitvec_hi_2[3] & _T_467; // @[el2_lsu_bus_buffer.scala 201:97] + wire _T_470 = ~ld_byte_ibuf_hit_hi[2]; // @[el2_lsu_bus_buffer.scala 201:150] + wire _T_471 = _T_468 & _T_470; // @[el2_lsu_bus_buffer.scala 201:148] + wire [3:0] _T_457 = ld_byte_hitvec_hi_2 & buf_age_younger_2; // @[el2_lsu_bus_buffer.scala 201:122] + wire _T_458 = |_T_457; // @[el2_lsu_bus_buffer.scala 201:144] + wire _T_459 = ~_T_458; // @[el2_lsu_bus_buffer.scala 201:99] + wire _T_460 = ld_byte_hitvec_hi_2[2] & _T_459; // @[el2_lsu_bus_buffer.scala 201:97] + wire _T_463 = _T_460 & _T_470; // @[el2_lsu_bus_buffer.scala 201:148] + wire [3:0] _T_449 = ld_byte_hitvec_hi_2 & buf_age_younger_1; // @[el2_lsu_bus_buffer.scala 201:122] + wire _T_450 = |_T_449; // @[el2_lsu_bus_buffer.scala 201:144] + wire _T_451 = ~_T_450; // @[el2_lsu_bus_buffer.scala 201:99] + wire _T_452 = ld_byte_hitvec_hi_2[1] & _T_451; // @[el2_lsu_bus_buffer.scala 201:97] + wire _T_455 = _T_452 & _T_470; // @[el2_lsu_bus_buffer.scala 201:148] + wire [3:0] _T_441 = ld_byte_hitvec_hi_2 & buf_age_younger_0; // @[el2_lsu_bus_buffer.scala 201:122] + wire _T_442 = |_T_441; // @[el2_lsu_bus_buffer.scala 201:144] + wire _T_443 = ~_T_442; // @[el2_lsu_bus_buffer.scala 201:99] + wire _T_444 = ld_byte_hitvec_hi_2[0] & _T_443; // @[el2_lsu_bus_buffer.scala 201:97] + wire _T_447 = _T_444 & _T_470; // @[el2_lsu_bus_buffer.scala 201:148] wire [3:0] ld_byte_hitvecfn_hi_2 = {_T_471,_T_463,_T_455,_T_447}; // @[Cat.scala 29:58] - wire _T_77 = |ld_byte_hitvecfn_hi_2; // @[el2_lsu_bus_buffer.scala 192:73] - wire _T_79 = _T_77 | ld_byte_ibuf_hit_hi[2]; // @[el2_lsu_bus_buffer.scala 192:77] - wire _T_225 = ld_addr_hitvec_hi_3 & buf_byteen_3[3]; // @[el2_lsu_bus_buffer.scala 195:95] - wire _T_227 = _T_225 & ldst_byteen_hi_m[3]; // @[el2_lsu_bus_buffer.scala 195:114] - wire _T_221 = ld_addr_hitvec_hi_2 & buf_byteen_2[3]; // @[el2_lsu_bus_buffer.scala 195:95] - wire _T_223 = _T_221 & ldst_byteen_hi_m[3]; // @[el2_lsu_bus_buffer.scala 195:114] - wire _T_217 = ld_addr_hitvec_hi_1 & buf_byteen_1[3]; // @[el2_lsu_bus_buffer.scala 195:95] - wire _T_219 = _T_217 & ldst_byteen_hi_m[3]; // @[el2_lsu_bus_buffer.scala 195:114] - wire _T_213 = ld_addr_hitvec_hi_0 & buf_byteen_0[3]; // @[el2_lsu_bus_buffer.scala 195:95] - wire _T_215 = _T_213 & ldst_byteen_hi_m[3]; // @[el2_lsu_bus_buffer.scala 195:114] + wire _T_77 = |ld_byte_hitvecfn_hi_2; // @[el2_lsu_bus_buffer.scala 193:73] + wire _T_79 = _T_77 | ld_byte_ibuf_hit_hi[2]; // @[el2_lsu_bus_buffer.scala 193:77] + wire _T_225 = ld_addr_hitvec_hi_3 & buf_byteen_3[3]; // @[el2_lsu_bus_buffer.scala 196:95] + wire _T_227 = _T_225 & ldst_byteen_hi_m[3]; // @[el2_lsu_bus_buffer.scala 196:114] + wire _T_221 = ld_addr_hitvec_hi_2 & buf_byteen_2[3]; // @[el2_lsu_bus_buffer.scala 196:95] + wire _T_223 = _T_221 & ldst_byteen_hi_m[3]; // @[el2_lsu_bus_buffer.scala 196:114] + wire _T_217 = ld_addr_hitvec_hi_1 & buf_byteen_1[3]; // @[el2_lsu_bus_buffer.scala 196:95] + wire _T_219 = _T_217 & ldst_byteen_hi_m[3]; // @[el2_lsu_bus_buffer.scala 196:114] + wire _T_213 = ld_addr_hitvec_hi_0 & buf_byteen_0[3]; // @[el2_lsu_bus_buffer.scala 196:95] + wire _T_215 = _T_213 & ldst_byteen_hi_m[3]; // @[el2_lsu_bus_buffer.scala 196:114] wire [3:0] ld_byte_hitvec_hi_3 = {_T_227,_T_223,_T_219,_T_215}; // @[Cat.scala 29:58] - wire [3:0] _T_500 = ld_byte_hitvec_hi_3 & buf_age_younger_3; // @[el2_lsu_bus_buffer.scala 200:122] - wire _T_501 = |_T_500; // @[el2_lsu_bus_buffer.scala 200:144] - wire _T_502 = ~_T_501; // @[el2_lsu_bus_buffer.scala 200:99] - wire _T_503 = ld_byte_hitvec_hi_3[3] & _T_502; // @[el2_lsu_bus_buffer.scala 200:97] - wire _T_505 = ~ld_byte_ibuf_hit_hi[3]; // @[el2_lsu_bus_buffer.scala 200:150] - wire _T_506 = _T_503 & _T_505; // @[el2_lsu_bus_buffer.scala 200:148] - wire [3:0] _T_492 = ld_byte_hitvec_hi_3 & buf_age_younger_2; // @[el2_lsu_bus_buffer.scala 200:122] - wire _T_493 = |_T_492; // @[el2_lsu_bus_buffer.scala 200:144] - wire _T_494 = ~_T_493; // @[el2_lsu_bus_buffer.scala 200:99] - wire _T_495 = ld_byte_hitvec_hi_3[2] & _T_494; // @[el2_lsu_bus_buffer.scala 200:97] - wire _T_498 = _T_495 & _T_505; // @[el2_lsu_bus_buffer.scala 200:148] - wire [3:0] _T_484 = ld_byte_hitvec_hi_3 & buf_age_younger_1; // @[el2_lsu_bus_buffer.scala 200:122] - wire _T_485 = |_T_484; // @[el2_lsu_bus_buffer.scala 200:144] - wire _T_486 = ~_T_485; // @[el2_lsu_bus_buffer.scala 200:99] - wire _T_487 = ld_byte_hitvec_hi_3[1] & _T_486; // @[el2_lsu_bus_buffer.scala 200:97] - wire _T_490 = _T_487 & _T_505; // @[el2_lsu_bus_buffer.scala 200:148] - wire [3:0] _T_476 = ld_byte_hitvec_hi_3 & buf_age_younger_0; // @[el2_lsu_bus_buffer.scala 200:122] - wire _T_477 = |_T_476; // @[el2_lsu_bus_buffer.scala 200:144] - wire _T_478 = ~_T_477; // @[el2_lsu_bus_buffer.scala 200:99] - wire _T_479 = ld_byte_hitvec_hi_3[0] & _T_478; // @[el2_lsu_bus_buffer.scala 200:97] - wire _T_482 = _T_479 & _T_505; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] _T_500 = ld_byte_hitvec_hi_3 & buf_age_younger_3; // @[el2_lsu_bus_buffer.scala 201:122] + wire _T_501 = |_T_500; // @[el2_lsu_bus_buffer.scala 201:144] + wire _T_502 = ~_T_501; // @[el2_lsu_bus_buffer.scala 201:99] + wire _T_503 = ld_byte_hitvec_hi_3[3] & _T_502; // @[el2_lsu_bus_buffer.scala 201:97] + wire _T_505 = ~ld_byte_ibuf_hit_hi[3]; // @[el2_lsu_bus_buffer.scala 201:150] + wire _T_506 = _T_503 & _T_505; // @[el2_lsu_bus_buffer.scala 201:148] + wire [3:0] _T_492 = ld_byte_hitvec_hi_3 & buf_age_younger_2; // @[el2_lsu_bus_buffer.scala 201:122] + wire _T_493 = |_T_492; // @[el2_lsu_bus_buffer.scala 201:144] + wire _T_494 = ~_T_493; // @[el2_lsu_bus_buffer.scala 201:99] + wire _T_495 = ld_byte_hitvec_hi_3[2] & _T_494; // @[el2_lsu_bus_buffer.scala 201:97] + wire _T_498 = _T_495 & _T_505; // @[el2_lsu_bus_buffer.scala 201:148] + wire [3:0] _T_484 = ld_byte_hitvec_hi_3 & buf_age_younger_1; // @[el2_lsu_bus_buffer.scala 201:122] + wire _T_485 = |_T_484; // @[el2_lsu_bus_buffer.scala 201:144] + wire _T_486 = ~_T_485; // @[el2_lsu_bus_buffer.scala 201:99] + wire _T_487 = ld_byte_hitvec_hi_3[1] & _T_486; // @[el2_lsu_bus_buffer.scala 201:97] + wire _T_490 = _T_487 & _T_505; // @[el2_lsu_bus_buffer.scala 201:148] + wire [3:0] _T_476 = ld_byte_hitvec_hi_3 & buf_age_younger_0; // @[el2_lsu_bus_buffer.scala 201:122] + wire _T_477 = |_T_476; // @[el2_lsu_bus_buffer.scala 201:144] + wire _T_478 = ~_T_477; // @[el2_lsu_bus_buffer.scala 201:99] + wire _T_479 = ld_byte_hitvec_hi_3[0] & _T_478; // @[el2_lsu_bus_buffer.scala 201:97] + wire _T_482 = _T_479 & _T_505; // @[el2_lsu_bus_buffer.scala 201:148] wire [3:0] ld_byte_hitvecfn_hi_3 = {_T_506,_T_498,_T_490,_T_482}; // @[Cat.scala 29:58] - wire _T_80 = |ld_byte_hitvecfn_hi_3; // @[el2_lsu_bus_buffer.scala 192:73] - wire _T_82 = _T_80 | ld_byte_ibuf_hit_hi[3]; // @[el2_lsu_bus_buffer.scala 192:77] + wire _T_80 = |ld_byte_hitvecfn_hi_3; // @[el2_lsu_bus_buffer.scala 193:73] + wire _T_82 = _T_80 | ld_byte_ibuf_hit_hi[3]; // @[el2_lsu_bus_buffer.scala 193:77] wire [2:0] _T_84 = {_T_82,_T_79,_T_76}; // @[Cat.scala 29:58] wire [7:0] _T_530 = ld_byte_ibuf_hit_lo[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] wire [7:0] _T_533 = ld_byte_ibuf_hit_lo[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] @@ -738,112 +738,112 @@ module el2_lsu_bus_buffer( wire [31:0] ld_fwddata_buf_hi_initial = {_T_553,_T_550,_T_547,_T_544}; // @[Cat.scala 29:58] wire [7:0] _T_558 = ld_byte_hitvecfn_lo_3[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] reg [31:0] buf_data_0; // @[el2_lib.scala 514:16] - wire [7:0] _T_560 = _T_558 & buf_data_0[31:24]; // @[el2_lsu_bus_buffer.scala 218:91] + wire [7:0] _T_560 = _T_558 & buf_data_0[31:24]; // @[el2_lsu_bus_buffer.scala 219:91] wire [7:0] _T_563 = ld_byte_hitvecfn_lo_3[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] reg [31:0] buf_data_1; // @[el2_lib.scala 514:16] - wire [7:0] _T_565 = _T_563 & buf_data_1[31:24]; // @[el2_lsu_bus_buffer.scala 218:91] + wire [7:0] _T_565 = _T_563 & buf_data_1[31:24]; // @[el2_lsu_bus_buffer.scala 219:91] wire [7:0] _T_568 = ld_byte_hitvecfn_lo_3[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] reg [31:0] buf_data_2; // @[el2_lib.scala 514:16] - wire [7:0] _T_570 = _T_568 & buf_data_2[31:24]; // @[el2_lsu_bus_buffer.scala 218:91] + wire [7:0] _T_570 = _T_568 & buf_data_2[31:24]; // @[el2_lsu_bus_buffer.scala 219:91] wire [7:0] _T_573 = ld_byte_hitvecfn_lo_3[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] reg [31:0] buf_data_3; // @[el2_lib.scala 514:16] - wire [7:0] _T_575 = _T_573 & buf_data_3[31:24]; // @[el2_lsu_bus_buffer.scala 218:91] - wire [7:0] _T_576 = _T_560 | _T_565; // @[el2_lsu_bus_buffer.scala 218:123] - wire [7:0] _T_577 = _T_576 | _T_570; // @[el2_lsu_bus_buffer.scala 218:123] - wire [7:0] _T_578 = _T_577 | _T_575; // @[el2_lsu_bus_buffer.scala 218:123] + wire [7:0] _T_575 = _T_573 & buf_data_3[31:24]; // @[el2_lsu_bus_buffer.scala 219:91] + wire [7:0] _T_576 = _T_560 | _T_565; // @[el2_lsu_bus_buffer.scala 219:123] + wire [7:0] _T_577 = _T_576 | _T_570; // @[el2_lsu_bus_buffer.scala 219:123] + wire [7:0] _T_578 = _T_577 | _T_575; // @[el2_lsu_bus_buffer.scala 219:123] wire [7:0] _T_581 = ld_byte_hitvecfn_lo_2[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_583 = _T_581 & buf_data_0[23:16]; // @[el2_lsu_bus_buffer.scala 219:65] + wire [7:0] _T_583 = _T_581 & buf_data_0[23:16]; // @[el2_lsu_bus_buffer.scala 220:65] wire [7:0] _T_586 = ld_byte_hitvecfn_lo_2[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_588 = _T_586 & buf_data_1[23:16]; // @[el2_lsu_bus_buffer.scala 219:65] + wire [7:0] _T_588 = _T_586 & buf_data_1[23:16]; // @[el2_lsu_bus_buffer.scala 220:65] wire [7:0] _T_591 = ld_byte_hitvecfn_lo_2[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_593 = _T_591 & buf_data_2[23:16]; // @[el2_lsu_bus_buffer.scala 219:65] + wire [7:0] _T_593 = _T_591 & buf_data_2[23:16]; // @[el2_lsu_bus_buffer.scala 220:65] wire [7:0] _T_596 = ld_byte_hitvecfn_lo_2[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_598 = _T_596 & buf_data_3[23:16]; // @[el2_lsu_bus_buffer.scala 219:65] - wire [7:0] _T_599 = _T_583 | _T_588; // @[el2_lsu_bus_buffer.scala 219:97] - wire [7:0] _T_600 = _T_599 | _T_593; // @[el2_lsu_bus_buffer.scala 219:97] - wire [7:0] _T_601 = _T_600 | _T_598; // @[el2_lsu_bus_buffer.scala 219:97] + wire [7:0] _T_598 = _T_596 & buf_data_3[23:16]; // @[el2_lsu_bus_buffer.scala 220:65] + wire [7:0] _T_599 = _T_583 | _T_588; // @[el2_lsu_bus_buffer.scala 220:97] + wire [7:0] _T_600 = _T_599 | _T_593; // @[el2_lsu_bus_buffer.scala 220:97] + wire [7:0] _T_601 = _T_600 | _T_598; // @[el2_lsu_bus_buffer.scala 220:97] wire [7:0] _T_604 = ld_byte_hitvecfn_lo_1[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_606 = _T_604 & buf_data_0[15:8]; // @[el2_lsu_bus_buffer.scala 220:65] + wire [7:0] _T_606 = _T_604 & buf_data_0[15:8]; // @[el2_lsu_bus_buffer.scala 221:65] wire [7:0] _T_609 = ld_byte_hitvecfn_lo_1[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_611 = _T_609 & buf_data_1[15:8]; // @[el2_lsu_bus_buffer.scala 220:65] + wire [7:0] _T_611 = _T_609 & buf_data_1[15:8]; // @[el2_lsu_bus_buffer.scala 221:65] wire [7:0] _T_614 = ld_byte_hitvecfn_lo_1[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_616 = _T_614 & buf_data_2[15:8]; // @[el2_lsu_bus_buffer.scala 220:65] + wire [7:0] _T_616 = _T_614 & buf_data_2[15:8]; // @[el2_lsu_bus_buffer.scala 221:65] wire [7:0] _T_619 = ld_byte_hitvecfn_lo_1[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_621 = _T_619 & buf_data_3[15:8]; // @[el2_lsu_bus_buffer.scala 220:65] - wire [7:0] _T_622 = _T_606 | _T_611; // @[el2_lsu_bus_buffer.scala 220:97] - wire [7:0] _T_623 = _T_622 | _T_616; // @[el2_lsu_bus_buffer.scala 220:97] - wire [7:0] _T_624 = _T_623 | _T_621; // @[el2_lsu_bus_buffer.scala 220:97] + wire [7:0] _T_621 = _T_619 & buf_data_3[15:8]; // @[el2_lsu_bus_buffer.scala 221:65] + wire [7:0] _T_622 = _T_606 | _T_611; // @[el2_lsu_bus_buffer.scala 221:97] + wire [7:0] _T_623 = _T_622 | _T_616; // @[el2_lsu_bus_buffer.scala 221:97] + wire [7:0] _T_624 = _T_623 | _T_621; // @[el2_lsu_bus_buffer.scala 221:97] wire [7:0] _T_627 = ld_byte_hitvecfn_lo_0[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_629 = _T_627 & buf_data_0[7:0]; // @[el2_lsu_bus_buffer.scala 221:65] + wire [7:0] _T_629 = _T_627 & buf_data_0[7:0]; // @[el2_lsu_bus_buffer.scala 222:65] wire [7:0] _T_632 = ld_byte_hitvecfn_lo_0[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_634 = _T_632 & buf_data_1[7:0]; // @[el2_lsu_bus_buffer.scala 221:65] + wire [7:0] _T_634 = _T_632 & buf_data_1[7:0]; // @[el2_lsu_bus_buffer.scala 222:65] wire [7:0] _T_637 = ld_byte_hitvecfn_lo_0[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_639 = _T_637 & buf_data_2[7:0]; // @[el2_lsu_bus_buffer.scala 221:65] + wire [7:0] _T_639 = _T_637 & buf_data_2[7:0]; // @[el2_lsu_bus_buffer.scala 222:65] wire [7:0] _T_642 = ld_byte_hitvecfn_lo_0[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_644 = _T_642 & buf_data_3[7:0]; // @[el2_lsu_bus_buffer.scala 221:65] - wire [7:0] _T_645 = _T_629 | _T_634; // @[el2_lsu_bus_buffer.scala 221:97] - wire [7:0] _T_646 = _T_645 | _T_639; // @[el2_lsu_bus_buffer.scala 221:97] - wire [7:0] _T_647 = _T_646 | _T_644; // @[el2_lsu_bus_buffer.scala 221:97] + wire [7:0] _T_644 = _T_642 & buf_data_3[7:0]; // @[el2_lsu_bus_buffer.scala 222:65] + wire [7:0] _T_645 = _T_629 | _T_634; // @[el2_lsu_bus_buffer.scala 222:97] + wire [7:0] _T_646 = _T_645 | _T_639; // @[el2_lsu_bus_buffer.scala 222:97] + wire [7:0] _T_647 = _T_646 | _T_644; // @[el2_lsu_bus_buffer.scala 222:97] wire [31:0] _T_650 = {_T_578,_T_601,_T_624,_T_647}; // @[Cat.scala 29:58] reg [31:0] ibuf_data; // @[el2_lib.scala 514:16] - wire [31:0] _T_651 = ld_fwddata_buf_lo_initial & ibuf_data; // @[el2_lsu_bus_buffer.scala 222:32] + wire [31:0] _T_651 = ld_fwddata_buf_lo_initial & ibuf_data; // @[el2_lsu_bus_buffer.scala 223:32] wire [7:0] _T_655 = ld_byte_hitvecfn_hi_3[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_657 = _T_655 & buf_data_0[31:24]; // @[el2_lsu_bus_buffer.scala 224:91] + wire [7:0] _T_657 = _T_655 & buf_data_0[31:24]; // @[el2_lsu_bus_buffer.scala 225:91] wire [7:0] _T_660 = ld_byte_hitvecfn_hi_3[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_662 = _T_660 & buf_data_1[31:24]; // @[el2_lsu_bus_buffer.scala 224:91] + wire [7:0] _T_662 = _T_660 & buf_data_1[31:24]; // @[el2_lsu_bus_buffer.scala 225:91] wire [7:0] _T_665 = ld_byte_hitvecfn_hi_3[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_667 = _T_665 & buf_data_2[31:24]; // @[el2_lsu_bus_buffer.scala 224:91] + wire [7:0] _T_667 = _T_665 & buf_data_2[31:24]; // @[el2_lsu_bus_buffer.scala 225:91] wire [7:0] _T_670 = ld_byte_hitvecfn_hi_3[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_672 = _T_670 & buf_data_3[31:24]; // @[el2_lsu_bus_buffer.scala 224:91] - wire [7:0] _T_673 = _T_657 | _T_662; // @[el2_lsu_bus_buffer.scala 224:123] - wire [7:0] _T_674 = _T_673 | _T_667; // @[el2_lsu_bus_buffer.scala 224:123] - wire [7:0] _T_675 = _T_674 | _T_672; // @[el2_lsu_bus_buffer.scala 224:123] + wire [7:0] _T_672 = _T_670 & buf_data_3[31:24]; // @[el2_lsu_bus_buffer.scala 225:91] + wire [7:0] _T_673 = _T_657 | _T_662; // @[el2_lsu_bus_buffer.scala 225:123] + wire [7:0] _T_674 = _T_673 | _T_667; // @[el2_lsu_bus_buffer.scala 225:123] + wire [7:0] _T_675 = _T_674 | _T_672; // @[el2_lsu_bus_buffer.scala 225:123] wire [7:0] _T_678 = ld_byte_hitvecfn_hi_2[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_680 = _T_678 & buf_data_0[23:16]; // @[el2_lsu_bus_buffer.scala 225:65] + wire [7:0] _T_680 = _T_678 & buf_data_0[23:16]; // @[el2_lsu_bus_buffer.scala 226:65] wire [7:0] _T_683 = ld_byte_hitvecfn_hi_2[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_685 = _T_683 & buf_data_1[23:16]; // @[el2_lsu_bus_buffer.scala 225:65] + wire [7:0] _T_685 = _T_683 & buf_data_1[23:16]; // @[el2_lsu_bus_buffer.scala 226:65] wire [7:0] _T_688 = ld_byte_hitvecfn_hi_2[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_690 = _T_688 & buf_data_2[23:16]; // @[el2_lsu_bus_buffer.scala 225:65] + wire [7:0] _T_690 = _T_688 & buf_data_2[23:16]; // @[el2_lsu_bus_buffer.scala 226:65] wire [7:0] _T_693 = ld_byte_hitvecfn_hi_2[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_695 = _T_693 & buf_data_3[23:16]; // @[el2_lsu_bus_buffer.scala 225:65] - wire [7:0] _T_696 = _T_680 | _T_685; // @[el2_lsu_bus_buffer.scala 225:97] - wire [7:0] _T_697 = _T_696 | _T_690; // @[el2_lsu_bus_buffer.scala 225:97] - wire [7:0] _T_698 = _T_697 | _T_695; // @[el2_lsu_bus_buffer.scala 225:97] + wire [7:0] _T_695 = _T_693 & buf_data_3[23:16]; // @[el2_lsu_bus_buffer.scala 226:65] + wire [7:0] _T_696 = _T_680 | _T_685; // @[el2_lsu_bus_buffer.scala 226:97] + wire [7:0] _T_697 = _T_696 | _T_690; // @[el2_lsu_bus_buffer.scala 226:97] + wire [7:0] _T_698 = _T_697 | _T_695; // @[el2_lsu_bus_buffer.scala 226:97] wire [7:0] _T_701 = ld_byte_hitvecfn_hi_1[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_703 = _T_701 & buf_data_0[15:8]; // @[el2_lsu_bus_buffer.scala 226:65] + wire [7:0] _T_703 = _T_701 & buf_data_0[15:8]; // @[el2_lsu_bus_buffer.scala 227:65] wire [7:0] _T_706 = ld_byte_hitvecfn_hi_1[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_708 = _T_706 & buf_data_1[15:8]; // @[el2_lsu_bus_buffer.scala 226:65] + wire [7:0] _T_708 = _T_706 & buf_data_1[15:8]; // @[el2_lsu_bus_buffer.scala 227:65] wire [7:0] _T_711 = ld_byte_hitvecfn_hi_1[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_713 = _T_711 & buf_data_2[15:8]; // @[el2_lsu_bus_buffer.scala 226:65] + wire [7:0] _T_713 = _T_711 & buf_data_2[15:8]; // @[el2_lsu_bus_buffer.scala 227:65] wire [7:0] _T_716 = ld_byte_hitvecfn_hi_1[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_718 = _T_716 & buf_data_3[15:8]; // @[el2_lsu_bus_buffer.scala 226:65] - wire [7:0] _T_719 = _T_703 | _T_708; // @[el2_lsu_bus_buffer.scala 226:97] - wire [7:0] _T_720 = _T_719 | _T_713; // @[el2_lsu_bus_buffer.scala 226:97] - wire [7:0] _T_721 = _T_720 | _T_718; // @[el2_lsu_bus_buffer.scala 226:97] + wire [7:0] _T_718 = _T_716 & buf_data_3[15:8]; // @[el2_lsu_bus_buffer.scala 227:65] + wire [7:0] _T_719 = _T_703 | _T_708; // @[el2_lsu_bus_buffer.scala 227:97] + wire [7:0] _T_720 = _T_719 | _T_713; // @[el2_lsu_bus_buffer.scala 227:97] + wire [7:0] _T_721 = _T_720 | _T_718; // @[el2_lsu_bus_buffer.scala 227:97] wire [7:0] _T_724 = ld_byte_hitvecfn_hi_0[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_726 = _T_724 & buf_data_0[7:0]; // @[el2_lsu_bus_buffer.scala 227:65] + wire [7:0] _T_726 = _T_724 & buf_data_0[7:0]; // @[el2_lsu_bus_buffer.scala 228:65] wire [7:0] _T_729 = ld_byte_hitvecfn_hi_0[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_731 = _T_729 & buf_data_1[7:0]; // @[el2_lsu_bus_buffer.scala 227:65] + wire [7:0] _T_731 = _T_729 & buf_data_1[7:0]; // @[el2_lsu_bus_buffer.scala 228:65] wire [7:0] _T_734 = ld_byte_hitvecfn_hi_0[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_736 = _T_734 & buf_data_2[7:0]; // @[el2_lsu_bus_buffer.scala 227:65] + wire [7:0] _T_736 = _T_734 & buf_data_2[7:0]; // @[el2_lsu_bus_buffer.scala 228:65] wire [7:0] _T_739 = ld_byte_hitvecfn_hi_0[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_741 = _T_739 & buf_data_3[7:0]; // @[el2_lsu_bus_buffer.scala 227:65] - wire [7:0] _T_742 = _T_726 | _T_731; // @[el2_lsu_bus_buffer.scala 227:97] - wire [7:0] _T_743 = _T_742 | _T_736; // @[el2_lsu_bus_buffer.scala 227:97] - wire [7:0] _T_744 = _T_743 | _T_741; // @[el2_lsu_bus_buffer.scala 227:97] + wire [7:0] _T_741 = _T_739 & buf_data_3[7:0]; // @[el2_lsu_bus_buffer.scala 228:65] + wire [7:0] _T_742 = _T_726 | _T_731; // @[el2_lsu_bus_buffer.scala 228:97] + wire [7:0] _T_743 = _T_742 | _T_736; // @[el2_lsu_bus_buffer.scala 228:97] + wire [7:0] _T_744 = _T_743 | _T_741; // @[el2_lsu_bus_buffer.scala 228:97] wire [31:0] _T_747 = {_T_675,_T_698,_T_721,_T_744}; // @[Cat.scala 29:58] - wire [31:0] _T_748 = ld_fwddata_buf_hi_initial & ibuf_data; // @[el2_lsu_bus_buffer.scala 228:32] - wire [3:0] _T_750 = io_lsu_pkt_r_by ? 4'h1 : 4'h0; // @[Mux.scala 27:72] - wire [3:0] _T_751 = io_lsu_pkt_r_half ? 4'h3 : 4'h0; // @[Mux.scala 27:72] - wire [3:0] _T_752 = io_lsu_pkt_r_word ? 4'hf : 4'h0; // @[Mux.scala 27:72] + wire [31:0] _T_748 = ld_fwddata_buf_hi_initial & ibuf_data; // @[el2_lsu_bus_buffer.scala 229:32] + wire [3:0] _T_750 = io_lsu_pkt_r_bits_by ? 4'h1 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_751 = io_lsu_pkt_r_bits_half ? 4'h3 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_752 = io_lsu_pkt_r_bits_word ? 4'hf : 4'h0; // @[Mux.scala 27:72] wire [3:0] _T_753 = _T_750 | _T_751; // @[Mux.scala 27:72] wire [3:0] ldst_byteen_r = _T_753 | _T_752; // @[Mux.scala 27:72] - wire _T_756 = io_lsu_addr_r[1:0] == 2'h0; // @[el2_lsu_bus_buffer.scala 235:55] - wire _T_758 = io_lsu_addr_r[1:0] == 2'h1; // @[el2_lsu_bus_buffer.scala 236:24] + wire _T_756 = io_lsu_addr_r[1:0] == 2'h0; // @[el2_lsu_bus_buffer.scala 236:55] + wire _T_758 = io_lsu_addr_r[1:0] == 2'h1; // @[el2_lsu_bus_buffer.scala 237:24] wire [3:0] _T_760 = {3'h0,ldst_byteen_r[3]}; // @[Cat.scala 29:58] - wire _T_762 = io_lsu_addr_r[1:0] == 2'h2; // @[el2_lsu_bus_buffer.scala 237:24] + wire _T_762 = io_lsu_addr_r[1:0] == 2'h2; // @[el2_lsu_bus_buffer.scala 238:24] wire [3:0] _T_764 = {2'h0,ldst_byteen_r[3:2]}; // @[Cat.scala 29:58] - wire _T_766 = io_lsu_addr_r[1:0] == 2'h3; // @[el2_lsu_bus_buffer.scala 238:24] + wire _T_766 = io_lsu_addr_r[1:0] == 2'h3; // @[el2_lsu_bus_buffer.scala 239:24] wire [3:0] _T_768 = {1'h0,ldst_byteen_r[3:1]}; // @[Cat.scala 29:58] wire [3:0] _T_770 = _T_758 ? _T_760 : 4'h0; // @[Mux.scala 27:72] wire [3:0] _T_771 = _T_762 ? _T_764 : 4'h0; // @[Mux.scala 27:72] @@ -878,162 +878,162 @@ module el2_lsu_bus_buffer( wire [31:0] _T_836 = _T_832 | _T_833; // @[Mux.scala 27:72] wire [31:0] _T_837 = _T_836 | _T_834; // @[Mux.scala 27:72] wire [31:0] store_data_lo_r = _T_837 | _T_835; // @[Mux.scala 27:72] - wire ldst_samedw_r = io_lsu_addr_r[3] == io_end_addr_r[3]; // @[el2_lsu_bus_buffer.scala 255:40] - wire _T_844 = ~io_lsu_addr_r[0]; // @[el2_lsu_bus_buffer.scala 257:26] - wire _T_845 = io_lsu_pkt_r_word & _T_756; // @[Mux.scala 27:72] - wire _T_846 = io_lsu_pkt_r_half & _T_844; // @[Mux.scala 27:72] + wire ldst_samedw_r = io_lsu_addr_r[3] == io_end_addr_r[3]; // @[el2_lsu_bus_buffer.scala 256:40] + wire _T_844 = ~io_lsu_addr_r[0]; // @[el2_lsu_bus_buffer.scala 258:31] + wire _T_845 = io_lsu_pkt_r_bits_word & _T_756; // @[Mux.scala 27:72] + wire _T_846 = io_lsu_pkt_r_bits_half & _T_844; // @[Mux.scala 27:72] wire _T_848 = _T_845 | _T_846; // @[Mux.scala 27:72] - wire is_aligned_r = _T_848 | io_lsu_pkt_r_by; // @[Mux.scala 27:72] - wire _T_850 = io_lsu_pkt_r_load | io_no_word_merge_r; // @[el2_lsu_bus_buffer.scala 259:55] - wire _T_851 = io_lsu_busreq_r & _T_850; // @[el2_lsu_bus_buffer.scala 259:34] - wire _T_852 = ~ibuf_valid; // @[el2_lsu_bus_buffer.scala 259:79] - wire ibuf_byp = _T_851 & _T_852; // @[el2_lsu_bus_buffer.scala 259:77] - wire _T_853 = io_lsu_busreq_r & io_lsu_commit_r; // @[el2_lsu_bus_buffer.scala 260:36] - wire _T_854 = ~ibuf_byp; // @[el2_lsu_bus_buffer.scala 260:56] - wire ibuf_wr_en = _T_853 & _T_854; // @[el2_lsu_bus_buffer.scala 260:54] - wire _T_855 = ~ibuf_wr_en; // @[el2_lsu_bus_buffer.scala 262:36] - reg [2:0] ibuf_timer; // @[el2_lsu_bus_buffer.scala 305:55] - wire _T_864 = ibuf_timer == 3'h7; // @[el2_lsu_bus_buffer.scala 268:62] - wire _T_865 = ibuf_wr_en | _T_864; // @[el2_lsu_bus_buffer.scala 268:48] - wire _T_929 = _T_853 & io_lsu_pkt_r_store; // @[el2_lsu_bus_buffer.scala 287:54] - wire _T_930 = _T_929 & ibuf_valid; // @[el2_lsu_bus_buffer.scala 287:75] - wire _T_931 = _T_930 & ibuf_write; // @[el2_lsu_bus_buffer.scala 287:88] - wire _T_934 = io_lsu_addr_r[31:2] == ibuf_addr[31:2]; // @[el2_lsu_bus_buffer.scala 287:124] - wire _T_935 = _T_931 & _T_934; // @[el2_lsu_bus_buffer.scala 287:101] - wire _T_936 = ~io_is_sideeffects_r; // @[el2_lsu_bus_buffer.scala 287:147] - wire _T_937 = _T_935 & _T_936; // @[el2_lsu_bus_buffer.scala 287:145] - wire _T_938 = ~io_dec_tlu_wb_coalescing_disable; // @[el2_lsu_bus_buffer.scala 287:170] - wire ibuf_merge_en = _T_937 & _T_938; // @[el2_lsu_bus_buffer.scala 287:168] - wire ibuf_merge_in = ~io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 288:20] - wire _T_866 = ibuf_merge_en & ibuf_merge_in; // @[el2_lsu_bus_buffer.scala 268:98] - wire _T_867 = ~_T_866; // @[el2_lsu_bus_buffer.scala 268:82] - wire _T_868 = _T_865 & _T_867; // @[el2_lsu_bus_buffer.scala 268:80] - wire _T_869 = _T_868 | ibuf_byp; // @[el2_lsu_bus_buffer.scala 269:5] - wire _T_857 = ~io_lsu_busreq_r; // @[el2_lsu_bus_buffer.scala 263:44] - wire _T_858 = io_lsu_busreq_m & _T_857; // @[el2_lsu_bus_buffer.scala 263:42] - wire _T_859 = _T_858 & ibuf_valid; // @[el2_lsu_bus_buffer.scala 263:61] - wire _T_862 = ibuf_addr[31:2] != io_lsu_addr_m[31:2]; // @[el2_lsu_bus_buffer.scala 263:115] - wire _T_863 = io_lsu_pkt_m_load | _T_862; // @[el2_lsu_bus_buffer.scala 263:95] - wire ibuf_force_drain = _T_859 & _T_863; // @[el2_lsu_bus_buffer.scala 263:74] - wire _T_870 = _T_869 | ibuf_force_drain; // @[el2_lsu_bus_buffer.scala 269:16] + wire is_aligned_r = _T_848 | io_lsu_pkt_r_bits_by; // @[Mux.scala 27:72] + wire _T_850 = io_lsu_pkt_r_bits_load | io_no_word_merge_r; // @[el2_lsu_bus_buffer.scala 260:60] + wire _T_851 = io_lsu_busreq_r & _T_850; // @[el2_lsu_bus_buffer.scala 260:34] + wire _T_852 = ~ibuf_valid; // @[el2_lsu_bus_buffer.scala 260:84] + wire ibuf_byp = _T_851 & _T_852; // @[el2_lsu_bus_buffer.scala 260:82] + wire _T_853 = io_lsu_busreq_r & io_lsu_commit_r; // @[el2_lsu_bus_buffer.scala 261:36] + wire _T_854 = ~ibuf_byp; // @[el2_lsu_bus_buffer.scala 261:56] + wire ibuf_wr_en = _T_853 & _T_854; // @[el2_lsu_bus_buffer.scala 261:54] + wire _T_855 = ~ibuf_wr_en; // @[el2_lsu_bus_buffer.scala 263:36] + reg [2:0] ibuf_timer; // @[el2_lsu_bus_buffer.scala 306:55] + wire _T_864 = ibuf_timer == 3'h7; // @[el2_lsu_bus_buffer.scala 269:62] + wire _T_865 = ibuf_wr_en | _T_864; // @[el2_lsu_bus_buffer.scala 269:48] + wire _T_929 = _T_853 & io_lsu_pkt_r_bits_store; // @[el2_lsu_bus_buffer.scala 288:54] + wire _T_930 = _T_929 & ibuf_valid; // @[el2_lsu_bus_buffer.scala 288:80] + wire _T_931 = _T_930 & ibuf_write; // @[el2_lsu_bus_buffer.scala 288:93] + wire _T_934 = io_lsu_addr_r[31:2] == ibuf_addr[31:2]; // @[el2_lsu_bus_buffer.scala 288:129] + wire _T_935 = _T_931 & _T_934; // @[el2_lsu_bus_buffer.scala 288:106] + wire _T_936 = ~io_is_sideeffects_r; // @[el2_lsu_bus_buffer.scala 288:152] + wire _T_937 = _T_935 & _T_936; // @[el2_lsu_bus_buffer.scala 288:150] + wire _T_938 = ~io_dec_tlu_wb_coalescing_disable; // @[el2_lsu_bus_buffer.scala 288:175] + wire ibuf_merge_en = _T_937 & _T_938; // @[el2_lsu_bus_buffer.scala 288:173] + wire ibuf_merge_in = ~io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 289:20] + wire _T_866 = ibuf_merge_en & ibuf_merge_in; // @[el2_lsu_bus_buffer.scala 269:98] + wire _T_867 = ~_T_866; // @[el2_lsu_bus_buffer.scala 269:82] + wire _T_868 = _T_865 & _T_867; // @[el2_lsu_bus_buffer.scala 269:80] + wire _T_869 = _T_868 | ibuf_byp; // @[el2_lsu_bus_buffer.scala 270:5] + wire _T_857 = ~io_lsu_busreq_r; // @[el2_lsu_bus_buffer.scala 264:44] + wire _T_858 = io_lsu_busreq_m & _T_857; // @[el2_lsu_bus_buffer.scala 264:42] + wire _T_859 = _T_858 & ibuf_valid; // @[el2_lsu_bus_buffer.scala 264:61] + wire _T_862 = ibuf_addr[31:2] != io_lsu_addr_m[31:2]; // @[el2_lsu_bus_buffer.scala 264:120] + wire _T_863 = io_lsu_pkt_m_bits_load | _T_862; // @[el2_lsu_bus_buffer.scala 264:100] + wire ibuf_force_drain = _T_859 & _T_863; // @[el2_lsu_bus_buffer.scala 264:74] + wire _T_870 = _T_869 | ibuf_force_drain; // @[el2_lsu_bus_buffer.scala 270:16] reg ibuf_sideeffect; // @[Reg.scala 27:20] - wire _T_871 = _T_870 | ibuf_sideeffect; // @[el2_lsu_bus_buffer.scala 269:35] - wire _T_872 = ~ibuf_write; // @[el2_lsu_bus_buffer.scala 269:55] - wire _T_873 = _T_871 | _T_872; // @[el2_lsu_bus_buffer.scala 269:53] - wire _T_874 = _T_873 | io_dec_tlu_wb_coalescing_disable; // @[el2_lsu_bus_buffer.scala 269:67] - wire ibuf_drain_vld = ibuf_valid & _T_874; // @[el2_lsu_bus_buffer.scala 268:32] - wire _T_856 = ibuf_drain_vld & _T_855; // @[el2_lsu_bus_buffer.scala 262:34] - wire ibuf_rst = _T_856 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 262:49] - reg [1:0] WrPtr1_r; // @[el2_lsu_bus_buffer.scala 669:49] - reg [1:0] WrPtr0_r; // @[el2_lsu_bus_buffer.scala 668:49] + wire _T_871 = _T_870 | ibuf_sideeffect; // @[el2_lsu_bus_buffer.scala 270:35] + wire _T_872 = ~ibuf_write; // @[el2_lsu_bus_buffer.scala 270:55] + wire _T_873 = _T_871 | _T_872; // @[el2_lsu_bus_buffer.scala 270:53] + wire _T_874 = _T_873 | io_dec_tlu_wb_coalescing_disable; // @[el2_lsu_bus_buffer.scala 270:67] + wire ibuf_drain_vld = ibuf_valid & _T_874; // @[el2_lsu_bus_buffer.scala 269:32] + wire _T_856 = ibuf_drain_vld & _T_855; // @[el2_lsu_bus_buffer.scala 263:34] + wire ibuf_rst = _T_856 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 263:49] + reg [1:0] WrPtr1_r; // @[el2_lsu_bus_buffer.scala 670:49] + reg [1:0] WrPtr0_r; // @[el2_lsu_bus_buffer.scala 669:49] reg [1:0] ibuf_tag; // @[Reg.scala 27:20] - wire [1:0] ibuf_sz_in = {io_lsu_pkt_r_word,io_lsu_pkt_r_half}; // @[Cat.scala 29:58] - wire [3:0] _T_881 = ibuf_byteen | ldst_byteen_lo_r; // @[el2_lsu_bus_buffer.scala 278:77] - wire [7:0] _T_889 = ldst_byteen_lo_r[0] ? store_data_lo_r[7:0] : ibuf_data[7:0]; // @[el2_lsu_bus_buffer.scala 283:8] - wire [7:0] _T_892 = io_ldst_dual_r ? store_data_hi_r[7:0] : store_data_lo_r[7:0]; // @[el2_lsu_bus_buffer.scala 284:8] - wire [7:0] _T_893 = _T_866 ? _T_889 : _T_892; // @[el2_lsu_bus_buffer.scala 282:46] - wire [7:0] _T_898 = ldst_byteen_lo_r[1] ? store_data_lo_r[15:8] : ibuf_data[15:8]; // @[el2_lsu_bus_buffer.scala 283:8] - wire [7:0] _T_901 = io_ldst_dual_r ? store_data_hi_r[15:8] : store_data_lo_r[15:8]; // @[el2_lsu_bus_buffer.scala 284:8] - wire [7:0] _T_902 = _T_866 ? _T_898 : _T_901; // @[el2_lsu_bus_buffer.scala 282:46] - wire [7:0] _T_907 = ldst_byteen_lo_r[2] ? store_data_lo_r[23:16] : ibuf_data[23:16]; // @[el2_lsu_bus_buffer.scala 283:8] - wire [7:0] _T_910 = io_ldst_dual_r ? store_data_hi_r[23:16] : store_data_lo_r[23:16]; // @[el2_lsu_bus_buffer.scala 284:8] - wire [7:0] _T_911 = _T_866 ? _T_907 : _T_910; // @[el2_lsu_bus_buffer.scala 282:46] - wire [7:0] _T_916 = ldst_byteen_lo_r[3] ? store_data_lo_r[31:24] : ibuf_data[31:24]; // @[el2_lsu_bus_buffer.scala 283:8] - wire [7:0] _T_919 = io_ldst_dual_r ? store_data_hi_r[31:24] : store_data_lo_r[31:24]; // @[el2_lsu_bus_buffer.scala 284:8] - wire [7:0] _T_920 = _T_866 ? _T_916 : _T_919; // @[el2_lsu_bus_buffer.scala 282:46] + wire [1:0] ibuf_sz_in = {io_lsu_pkt_r_bits_word,io_lsu_pkt_r_bits_half}; // @[Cat.scala 29:58] + wire [3:0] _T_881 = ibuf_byteen | ldst_byteen_lo_r; // @[el2_lsu_bus_buffer.scala 279:77] + wire [7:0] _T_889 = ldst_byteen_lo_r[0] ? store_data_lo_r[7:0] : ibuf_data[7:0]; // @[el2_lsu_bus_buffer.scala 284:8] + wire [7:0] _T_892 = io_ldst_dual_r ? store_data_hi_r[7:0] : store_data_lo_r[7:0]; // @[el2_lsu_bus_buffer.scala 285:8] + wire [7:0] _T_893 = _T_866 ? _T_889 : _T_892; // @[el2_lsu_bus_buffer.scala 283:46] + wire [7:0] _T_898 = ldst_byteen_lo_r[1] ? store_data_lo_r[15:8] : ibuf_data[15:8]; // @[el2_lsu_bus_buffer.scala 284:8] + wire [7:0] _T_901 = io_ldst_dual_r ? store_data_hi_r[15:8] : store_data_lo_r[15:8]; // @[el2_lsu_bus_buffer.scala 285:8] + wire [7:0] _T_902 = _T_866 ? _T_898 : _T_901; // @[el2_lsu_bus_buffer.scala 283:46] + wire [7:0] _T_907 = ldst_byteen_lo_r[2] ? store_data_lo_r[23:16] : ibuf_data[23:16]; // @[el2_lsu_bus_buffer.scala 284:8] + wire [7:0] _T_910 = io_ldst_dual_r ? store_data_hi_r[23:16] : store_data_lo_r[23:16]; // @[el2_lsu_bus_buffer.scala 285:8] + wire [7:0] _T_911 = _T_866 ? _T_907 : _T_910; // @[el2_lsu_bus_buffer.scala 283:46] + wire [7:0] _T_916 = ldst_byteen_lo_r[3] ? store_data_lo_r[31:24] : ibuf_data[31:24]; // @[el2_lsu_bus_buffer.scala 284:8] + wire [7:0] _T_919 = io_ldst_dual_r ? store_data_hi_r[31:24] : store_data_lo_r[31:24]; // @[el2_lsu_bus_buffer.scala 285:8] + wire [7:0] _T_920 = _T_866 ? _T_916 : _T_919; // @[el2_lsu_bus_buffer.scala 283:46] wire [23:0] _T_922 = {_T_920,_T_911,_T_902}; // @[Cat.scala 29:58] - wire _T_923 = ibuf_timer < 3'h7; // @[el2_lsu_bus_buffer.scala 285:59] - wire [2:0] _T_926 = ibuf_timer + 3'h1; // @[el2_lsu_bus_buffer.scala 285:93] - wire _T_941 = ~ibuf_merge_in; // @[el2_lsu_bus_buffer.scala 289:65] - wire _T_942 = ibuf_merge_en & _T_941; // @[el2_lsu_bus_buffer.scala 289:63] - wire _T_945 = ibuf_byteen[0] | ldst_byteen_lo_r[0]; // @[el2_lsu_bus_buffer.scala 289:96] - wire _T_947 = _T_942 ? _T_945 : ibuf_byteen[0]; // @[el2_lsu_bus_buffer.scala 289:48] - wire _T_952 = ibuf_byteen[1] | ldst_byteen_lo_r[1]; // @[el2_lsu_bus_buffer.scala 289:96] - wire _T_954 = _T_942 ? _T_952 : ibuf_byteen[1]; // @[el2_lsu_bus_buffer.scala 289:48] - wire _T_959 = ibuf_byteen[2] | ldst_byteen_lo_r[2]; // @[el2_lsu_bus_buffer.scala 289:96] - wire _T_961 = _T_942 ? _T_959 : ibuf_byteen[2]; // @[el2_lsu_bus_buffer.scala 289:48] - wire _T_966 = ibuf_byteen[3] | ldst_byteen_lo_r[3]; // @[el2_lsu_bus_buffer.scala 289:96] - wire _T_968 = _T_942 ? _T_966 : ibuf_byteen[3]; // @[el2_lsu_bus_buffer.scala 289:48] + wire _T_923 = ibuf_timer < 3'h7; // @[el2_lsu_bus_buffer.scala 286:59] + wire [2:0] _T_926 = ibuf_timer + 3'h1; // @[el2_lsu_bus_buffer.scala 286:93] + wire _T_941 = ~ibuf_merge_in; // @[el2_lsu_bus_buffer.scala 290:65] + wire _T_942 = ibuf_merge_en & _T_941; // @[el2_lsu_bus_buffer.scala 290:63] + wire _T_945 = ibuf_byteen[0] | ldst_byteen_lo_r[0]; // @[el2_lsu_bus_buffer.scala 290:96] + wire _T_947 = _T_942 ? _T_945 : ibuf_byteen[0]; // @[el2_lsu_bus_buffer.scala 290:48] + wire _T_952 = ibuf_byteen[1] | ldst_byteen_lo_r[1]; // @[el2_lsu_bus_buffer.scala 290:96] + wire _T_954 = _T_942 ? _T_952 : ibuf_byteen[1]; // @[el2_lsu_bus_buffer.scala 290:48] + wire _T_959 = ibuf_byteen[2] | ldst_byteen_lo_r[2]; // @[el2_lsu_bus_buffer.scala 290:96] + wire _T_961 = _T_942 ? _T_959 : ibuf_byteen[2]; // @[el2_lsu_bus_buffer.scala 290:48] + wire _T_966 = ibuf_byteen[3] | ldst_byteen_lo_r[3]; // @[el2_lsu_bus_buffer.scala 290:96] + wire _T_968 = _T_942 ? _T_966 : ibuf_byteen[3]; // @[el2_lsu_bus_buffer.scala 290:48] wire [3:0] ibuf_byteen_out = {_T_968,_T_961,_T_954,_T_947}; // @[Cat.scala 29:58] - wire [7:0] _T_978 = _T_942 ? _T_889 : ibuf_data[7:0]; // @[el2_lsu_bus_buffer.scala 290:45] - wire [7:0] _T_986 = _T_942 ? _T_898 : ibuf_data[15:8]; // @[el2_lsu_bus_buffer.scala 290:45] - wire [7:0] _T_994 = _T_942 ? _T_907 : ibuf_data[23:16]; // @[el2_lsu_bus_buffer.scala 290:45] - wire [7:0] _T_1002 = _T_942 ? _T_916 : ibuf_data[31:24]; // @[el2_lsu_bus_buffer.scala 290:45] + wire [7:0] _T_978 = _T_942 ? _T_889 : ibuf_data[7:0]; // @[el2_lsu_bus_buffer.scala 291:45] + wire [7:0] _T_986 = _T_942 ? _T_898 : ibuf_data[15:8]; // @[el2_lsu_bus_buffer.scala 291:45] + wire [7:0] _T_994 = _T_942 ? _T_907 : ibuf_data[23:16]; // @[el2_lsu_bus_buffer.scala 291:45] + wire [7:0] _T_1002 = _T_942 ? _T_916 : ibuf_data[31:24]; // @[el2_lsu_bus_buffer.scala 291:45] wire [31:0] ibuf_data_out = {_T_1002,_T_994,_T_986,_T_978}; // @[Cat.scala 29:58] - wire _T_1005 = ibuf_wr_en | ibuf_valid; // @[el2_lsu_bus_buffer.scala 292:58] - wire _T_1006 = ~ibuf_rst; // @[el2_lsu_bus_buffer.scala 292:93] + wire _T_1005 = ibuf_wr_en | ibuf_valid; // @[el2_lsu_bus_buffer.scala 293:58] + wire _T_1006 = ~ibuf_rst; // @[el2_lsu_bus_buffer.scala 293:93] reg [1:0] ibuf_dualtag; // @[Reg.scala 27:20] reg ibuf_dual; // @[Reg.scala 27:20] reg ibuf_samedw; // @[Reg.scala 27:20] reg ibuf_nomerge; // @[Reg.scala 27:20] reg ibuf_unsign; // @[Reg.scala 27:20] reg [1:0] ibuf_sz; // @[Reg.scala 27:20] - wire _T_4446 = buf_write[3] & _T_2621; // @[el2_lsu_bus_buffer.scala 575:64] - wire _T_4447 = ~buf_cmd_state_bus_en_3; // @[el2_lsu_bus_buffer.scala 575:91] - wire _T_4448 = _T_4446 & _T_4447; // @[el2_lsu_bus_buffer.scala 575:89] - wire _T_4441 = buf_write[2] & _T_2616; // @[el2_lsu_bus_buffer.scala 575:64] - wire _T_4442 = ~buf_cmd_state_bus_en_2; // @[el2_lsu_bus_buffer.scala 575:91] - wire _T_4443 = _T_4441 & _T_4442; // @[el2_lsu_bus_buffer.scala 575:89] - wire [1:0] _T_4449 = _T_4448 + _T_4443; // @[el2_lsu_bus_buffer.scala 575:142] - wire _T_4436 = buf_write[1] & _T_2611; // @[el2_lsu_bus_buffer.scala 575:64] - wire _T_4437 = ~buf_cmd_state_bus_en_1; // @[el2_lsu_bus_buffer.scala 575:91] - wire _T_4438 = _T_4436 & _T_4437; // @[el2_lsu_bus_buffer.scala 575:89] - wire [1:0] _GEN_362 = {{1'd0}, _T_4438}; // @[el2_lsu_bus_buffer.scala 575:142] - wire [2:0] _T_4450 = _T_4449 + _GEN_362; // @[el2_lsu_bus_buffer.scala 575:142] - wire _T_4431 = buf_write[0] & _T_2606; // @[el2_lsu_bus_buffer.scala 575:64] - wire _T_4432 = ~buf_cmd_state_bus_en_0; // @[el2_lsu_bus_buffer.scala 575:91] - wire _T_4433 = _T_4431 & _T_4432; // @[el2_lsu_bus_buffer.scala 575:89] - wire [2:0] _GEN_363 = {{2'd0}, _T_4433}; // @[el2_lsu_bus_buffer.scala 575:142] - wire [3:0] buf_numvld_wrcmd_any = _T_4450 + _GEN_363; // @[el2_lsu_bus_buffer.scala 575:142] - wire _T_1016 = buf_numvld_wrcmd_any == 4'h1; // @[el2_lsu_bus_buffer.scala 315:43] - wire _T_4463 = _T_2621 & _T_4447; // @[el2_lsu_bus_buffer.scala 576:73] - wire _T_4460 = _T_2616 & _T_4442; // @[el2_lsu_bus_buffer.scala 576:73] - wire [1:0] _T_4464 = _T_4463 + _T_4460; // @[el2_lsu_bus_buffer.scala 576:126] - wire _T_4457 = _T_2611 & _T_4437; // @[el2_lsu_bus_buffer.scala 576:73] - wire [1:0] _GEN_364 = {{1'd0}, _T_4457}; // @[el2_lsu_bus_buffer.scala 576:126] - wire [2:0] _T_4465 = _T_4464 + _GEN_364; // @[el2_lsu_bus_buffer.scala 576:126] - wire _T_4454 = _T_2606 & _T_4432; // @[el2_lsu_bus_buffer.scala 576:73] - wire [2:0] _GEN_365 = {{2'd0}, _T_4454}; // @[el2_lsu_bus_buffer.scala 576:126] - wire [3:0] buf_numvld_cmd_any = _T_4465 + _GEN_365; // @[el2_lsu_bus_buffer.scala 576:126] - wire _T_1017 = buf_numvld_cmd_any == 4'h1; // @[el2_lsu_bus_buffer.scala 315:72] - wire _T_1018 = _T_1016 & _T_1017; // @[el2_lsu_bus_buffer.scala 315:51] - reg [2:0] obuf_wr_timer; // @[el2_lsu_bus_buffer.scala 414:54] - wire _T_1019 = obuf_wr_timer != 3'h7; // @[el2_lsu_bus_buffer.scala 315:97] - wire _T_1020 = _T_1018 & _T_1019; // @[el2_lsu_bus_buffer.scala 315:80] - wire _T_1022 = _T_1020 & _T_938; // @[el2_lsu_bus_buffer.scala 315:114] - wire _T_1979 = |buf_age_3; // @[el2_lsu_bus_buffer.scala 431:58] - wire _T_1980 = ~_T_1979; // @[el2_lsu_bus_buffer.scala 431:45] - wire _T_1982 = _T_1980 & _T_2621; // @[el2_lsu_bus_buffer.scala 431:63] - wire _T_1984 = _T_1982 & _T_4447; // @[el2_lsu_bus_buffer.scala 431:88] - wire _T_1973 = |buf_age_2; // @[el2_lsu_bus_buffer.scala 431:58] - wire _T_1974 = ~_T_1973; // @[el2_lsu_bus_buffer.scala 431:45] - wire _T_1976 = _T_1974 & _T_2616; // @[el2_lsu_bus_buffer.scala 431:63] - wire _T_1978 = _T_1976 & _T_4442; // @[el2_lsu_bus_buffer.scala 431:88] - wire _T_1967 = |buf_age_1; // @[el2_lsu_bus_buffer.scala 431:58] - wire _T_1968 = ~_T_1967; // @[el2_lsu_bus_buffer.scala 431:45] - wire _T_1970 = _T_1968 & _T_2611; // @[el2_lsu_bus_buffer.scala 431:63] - wire _T_1972 = _T_1970 & _T_4437; // @[el2_lsu_bus_buffer.scala 431:88] - wire _T_1961 = |buf_age_0; // @[el2_lsu_bus_buffer.scala 431:58] - wire _T_1962 = ~_T_1961; // @[el2_lsu_bus_buffer.scala 431:45] - wire _T_1964 = _T_1962 & _T_2606; // @[el2_lsu_bus_buffer.scala 431:63] - wire _T_1966 = _T_1964 & _T_4432; // @[el2_lsu_bus_buffer.scala 431:88] + wire _T_4446 = buf_write[3] & _T_2621; // @[el2_lsu_bus_buffer.scala 576:64] + wire _T_4447 = ~buf_cmd_state_bus_en_3; // @[el2_lsu_bus_buffer.scala 576:91] + wire _T_4448 = _T_4446 & _T_4447; // @[el2_lsu_bus_buffer.scala 576:89] + wire _T_4441 = buf_write[2] & _T_2616; // @[el2_lsu_bus_buffer.scala 576:64] + wire _T_4442 = ~buf_cmd_state_bus_en_2; // @[el2_lsu_bus_buffer.scala 576:91] + wire _T_4443 = _T_4441 & _T_4442; // @[el2_lsu_bus_buffer.scala 576:89] + wire [1:0] _T_4449 = _T_4448 + _T_4443; // @[el2_lsu_bus_buffer.scala 576:142] + wire _T_4436 = buf_write[1] & _T_2611; // @[el2_lsu_bus_buffer.scala 576:64] + wire _T_4437 = ~buf_cmd_state_bus_en_1; // @[el2_lsu_bus_buffer.scala 576:91] + wire _T_4438 = _T_4436 & _T_4437; // @[el2_lsu_bus_buffer.scala 576:89] + wire [1:0] _GEN_362 = {{1'd0}, _T_4438}; // @[el2_lsu_bus_buffer.scala 576:142] + wire [2:0] _T_4450 = _T_4449 + _GEN_362; // @[el2_lsu_bus_buffer.scala 576:142] + wire _T_4431 = buf_write[0] & _T_2606; // @[el2_lsu_bus_buffer.scala 576:64] + wire _T_4432 = ~buf_cmd_state_bus_en_0; // @[el2_lsu_bus_buffer.scala 576:91] + wire _T_4433 = _T_4431 & _T_4432; // @[el2_lsu_bus_buffer.scala 576:89] + wire [2:0] _GEN_363 = {{2'd0}, _T_4433}; // @[el2_lsu_bus_buffer.scala 576:142] + wire [3:0] buf_numvld_wrcmd_any = _T_4450 + _GEN_363; // @[el2_lsu_bus_buffer.scala 576:142] + wire _T_1016 = buf_numvld_wrcmd_any == 4'h1; // @[el2_lsu_bus_buffer.scala 316:43] + wire _T_4463 = _T_2621 & _T_4447; // @[el2_lsu_bus_buffer.scala 577:73] + wire _T_4460 = _T_2616 & _T_4442; // @[el2_lsu_bus_buffer.scala 577:73] + wire [1:0] _T_4464 = _T_4463 + _T_4460; // @[el2_lsu_bus_buffer.scala 577:126] + wire _T_4457 = _T_2611 & _T_4437; // @[el2_lsu_bus_buffer.scala 577:73] + wire [1:0] _GEN_364 = {{1'd0}, _T_4457}; // @[el2_lsu_bus_buffer.scala 577:126] + wire [2:0] _T_4465 = _T_4464 + _GEN_364; // @[el2_lsu_bus_buffer.scala 577:126] + wire _T_4454 = _T_2606 & _T_4432; // @[el2_lsu_bus_buffer.scala 577:73] + wire [2:0] _GEN_365 = {{2'd0}, _T_4454}; // @[el2_lsu_bus_buffer.scala 577:126] + wire [3:0] buf_numvld_cmd_any = _T_4465 + _GEN_365; // @[el2_lsu_bus_buffer.scala 577:126] + wire _T_1017 = buf_numvld_cmd_any == 4'h1; // @[el2_lsu_bus_buffer.scala 316:72] + wire _T_1018 = _T_1016 & _T_1017; // @[el2_lsu_bus_buffer.scala 316:51] + reg [2:0] obuf_wr_timer; // @[el2_lsu_bus_buffer.scala 415:54] + wire _T_1019 = obuf_wr_timer != 3'h7; // @[el2_lsu_bus_buffer.scala 316:97] + wire _T_1020 = _T_1018 & _T_1019; // @[el2_lsu_bus_buffer.scala 316:80] + wire _T_1022 = _T_1020 & _T_938; // @[el2_lsu_bus_buffer.scala 316:114] + wire _T_1979 = |buf_age_3; // @[el2_lsu_bus_buffer.scala 432:58] + wire _T_1980 = ~_T_1979; // @[el2_lsu_bus_buffer.scala 432:45] + wire _T_1982 = _T_1980 & _T_2621; // @[el2_lsu_bus_buffer.scala 432:63] + wire _T_1984 = _T_1982 & _T_4447; // @[el2_lsu_bus_buffer.scala 432:88] + wire _T_1973 = |buf_age_2; // @[el2_lsu_bus_buffer.scala 432:58] + wire _T_1974 = ~_T_1973; // @[el2_lsu_bus_buffer.scala 432:45] + wire _T_1976 = _T_1974 & _T_2616; // @[el2_lsu_bus_buffer.scala 432:63] + wire _T_1978 = _T_1976 & _T_4442; // @[el2_lsu_bus_buffer.scala 432:88] + wire _T_1967 = |buf_age_1; // @[el2_lsu_bus_buffer.scala 432:58] + wire _T_1968 = ~_T_1967; // @[el2_lsu_bus_buffer.scala 432:45] + wire _T_1970 = _T_1968 & _T_2611; // @[el2_lsu_bus_buffer.scala 432:63] + wire _T_1972 = _T_1970 & _T_4437; // @[el2_lsu_bus_buffer.scala 432:88] + wire _T_1961 = |buf_age_0; // @[el2_lsu_bus_buffer.scala 432:58] + wire _T_1962 = ~_T_1961; // @[el2_lsu_bus_buffer.scala 432:45] + wire _T_1964 = _T_1962 & _T_2606; // @[el2_lsu_bus_buffer.scala 432:63] + wire _T_1966 = _T_1964 & _T_4432; // @[el2_lsu_bus_buffer.scala 432:88] wire [3:0] CmdPtr0Dec = {_T_1984,_T_1978,_T_1972,_T_1966}; // @[Cat.scala 29:58] wire [7:0] _T_2054 = {4'h0,_T_1984,_T_1978,_T_1972,_T_1966}; // @[Cat.scala 29:58] - wire _T_2057 = _T_2054[4] | _T_2054[5]; // @[el2_lsu_bus_buffer.scala 439:42] - wire _T_2059 = _T_2057 | _T_2054[6]; // @[el2_lsu_bus_buffer.scala 439:48] - wire _T_2061 = _T_2059 | _T_2054[7]; // @[el2_lsu_bus_buffer.scala 439:54] - wire _T_2064 = _T_2054[2] | _T_2054[3]; // @[el2_lsu_bus_buffer.scala 439:67] - wire _T_2066 = _T_2064 | _T_2054[6]; // @[el2_lsu_bus_buffer.scala 439:73] - wire _T_2068 = _T_2066 | _T_2054[7]; // @[el2_lsu_bus_buffer.scala 439:79] - wire _T_2071 = _T_2054[1] | _T_2054[3]; // @[el2_lsu_bus_buffer.scala 439:92] - wire _T_2073 = _T_2071 | _T_2054[5]; // @[el2_lsu_bus_buffer.scala 439:98] - wire _T_2075 = _T_2073 | _T_2054[7]; // @[el2_lsu_bus_buffer.scala 439:104] + wire _T_2057 = _T_2054[4] | _T_2054[5]; // @[el2_lsu_bus_buffer.scala 440:42] + wire _T_2059 = _T_2057 | _T_2054[6]; // @[el2_lsu_bus_buffer.scala 440:48] + wire _T_2061 = _T_2059 | _T_2054[7]; // @[el2_lsu_bus_buffer.scala 440:54] + wire _T_2064 = _T_2054[2] | _T_2054[3]; // @[el2_lsu_bus_buffer.scala 440:67] + wire _T_2066 = _T_2064 | _T_2054[6]; // @[el2_lsu_bus_buffer.scala 440:73] + wire _T_2068 = _T_2066 | _T_2054[7]; // @[el2_lsu_bus_buffer.scala 440:79] + wire _T_2071 = _T_2054[1] | _T_2054[3]; // @[el2_lsu_bus_buffer.scala 440:92] + wire _T_2073 = _T_2071 | _T_2054[5]; // @[el2_lsu_bus_buffer.scala 440:98] + wire _T_2075 = _T_2073 | _T_2054[7]; // @[el2_lsu_bus_buffer.scala 440:104] wire [2:0] _T_2077 = {_T_2061,_T_2068,_T_2075}; // @[Cat.scala 29:58] - wire [1:0] CmdPtr0 = _T_2077[1:0]; // @[el2_lsu_bus_buffer.scala 444:11] - wire _T_1023 = CmdPtr0 == 2'h0; // @[el2_lsu_bus_buffer.scala 316:114] - wire _T_1024 = CmdPtr0 == 2'h1; // @[el2_lsu_bus_buffer.scala 316:114] - wire _T_1025 = CmdPtr0 == 2'h2; // @[el2_lsu_bus_buffer.scala 316:114] - wire _T_1026 = CmdPtr0 == 2'h3; // @[el2_lsu_bus_buffer.scala 316:114] + wire [1:0] CmdPtr0 = _T_2077[1:0]; // @[el2_lsu_bus_buffer.scala 445:11] + wire _T_1023 = CmdPtr0 == 2'h0; // @[el2_lsu_bus_buffer.scala 317:114] + wire _T_1024 = CmdPtr0 == 2'h1; // @[el2_lsu_bus_buffer.scala 317:114] + wire _T_1025 = CmdPtr0 == 2'h2; // @[el2_lsu_bus_buffer.scala 317:114] + wire _T_1026 = CmdPtr0 == 2'h3; // @[el2_lsu_bus_buffer.scala 317:114] reg buf_nomerge_0; // @[Reg.scala 27:20] wire _T_1027 = _T_1023 & buf_nomerge_0; // @[Mux.scala 27:72] reg buf_nomerge_1; // @[Reg.scala 27:20] @@ -1045,8 +1045,8 @@ module el2_lsu_bus_buffer( wire _T_1031 = _T_1027 | _T_1028; // @[Mux.scala 27:72] wire _T_1032 = _T_1031 | _T_1029; // @[Mux.scala 27:72] wire _T_1033 = _T_1032 | _T_1030; // @[Mux.scala 27:72] - wire _T_1035 = ~_T_1033; // @[el2_lsu_bus_buffer.scala 316:31] - wire _T_1036 = _T_1022 & _T_1035; // @[el2_lsu_bus_buffer.scala 316:29] + wire _T_1035 = ~_T_1033; // @[el2_lsu_bus_buffer.scala 317:31] + wire _T_1036 = _T_1022 & _T_1035; // @[el2_lsu_bus_buffer.scala 317:29] reg _T_4330; // @[Reg.scala 27:20] reg _T_4327; // @[Reg.scala 27:20] reg _T_4324; // @[Reg.scala 27:20] @@ -1059,10 +1059,10 @@ module el2_lsu_bus_buffer( wire _T_1049 = _T_1045 | _T_1046; // @[Mux.scala 27:72] wire _T_1050 = _T_1049 | _T_1047; // @[Mux.scala 27:72] wire _T_1051 = _T_1050 | _T_1048; // @[Mux.scala 27:72] - wire _T_1053 = ~_T_1051; // @[el2_lsu_bus_buffer.scala 317:5] - wire _T_1054 = _T_1036 & _T_1053; // @[el2_lsu_bus_buffer.scala 316:140] - wire _T_1065 = _T_858 & _T_852; // @[el2_lsu_bus_buffer.scala 319:58] - wire _T_1067 = _T_1065 & _T_1017; // @[el2_lsu_bus_buffer.scala 319:72] + wire _T_1053 = ~_T_1051; // @[el2_lsu_bus_buffer.scala 318:5] + wire _T_1054 = _T_1036 & _T_1053; // @[el2_lsu_bus_buffer.scala 317:140] + wire _T_1065 = _T_858 & _T_852; // @[el2_lsu_bus_buffer.scala 320:58] + wire _T_1067 = _T_1065 & _T_1017; // @[el2_lsu_bus_buffer.scala 320:72] wire [29:0] _T_1077 = _T_1023 ? buf_addr_0[31:2] : 30'h0; // @[Mux.scala 27:72] wire [29:0] _T_1078 = _T_1024 ? buf_addr_1[31:2] : 30'h0; // @[Mux.scala 27:72] wire [29:0] _T_1081 = _T_1077 | _T_1078; // @[Mux.scala 27:72] @@ -1070,51 +1070,51 @@ module el2_lsu_bus_buffer( wire [29:0] _T_1082 = _T_1081 | _T_1079; // @[Mux.scala 27:72] wire [29:0] _T_1080 = _T_1026 ? buf_addr_3[31:2] : 30'h0; // @[Mux.scala 27:72] wire [29:0] _T_1083 = _T_1082 | _T_1080; // @[Mux.scala 27:72] - wire _T_1085 = io_lsu_addr_m[31:2] != _T_1083; // @[el2_lsu_bus_buffer.scala 319:123] - wire obuf_force_wr_en = _T_1067 & _T_1085; // @[el2_lsu_bus_buffer.scala 319:101] - wire _T_1055 = ~obuf_force_wr_en; // @[el2_lsu_bus_buffer.scala 317:119] - wire obuf_wr_wait = _T_1054 & _T_1055; // @[el2_lsu_bus_buffer.scala 317:117] - wire _T_1056 = |buf_numvld_cmd_any; // @[el2_lsu_bus_buffer.scala 318:75] - wire _T_1057 = obuf_wr_timer < 3'h7; // @[el2_lsu_bus_buffer.scala 318:95] - wire _T_1058 = _T_1056 & _T_1057; // @[el2_lsu_bus_buffer.scala 318:79] - wire [2:0] _T_1060 = obuf_wr_timer + 3'h1; // @[el2_lsu_bus_buffer.scala 318:123] - wire _T_4482 = buf_state_3 == 3'h1; // @[el2_lsu_bus_buffer.scala 577:63] - wire _T_4486 = _T_4482 | _T_4463; // @[el2_lsu_bus_buffer.scala 577:74] - wire _T_4477 = buf_state_2 == 3'h1; // @[el2_lsu_bus_buffer.scala 577:63] - wire _T_4481 = _T_4477 | _T_4460; // @[el2_lsu_bus_buffer.scala 577:74] - wire [1:0] _T_4487 = _T_4486 + _T_4481; // @[el2_lsu_bus_buffer.scala 577:154] - wire _T_4472 = buf_state_1 == 3'h1; // @[el2_lsu_bus_buffer.scala 577:63] - wire _T_4476 = _T_4472 | _T_4457; // @[el2_lsu_bus_buffer.scala 577:74] - wire [1:0] _GEN_366 = {{1'd0}, _T_4476}; // @[el2_lsu_bus_buffer.scala 577:154] - wire [2:0] _T_4488 = _T_4487 + _GEN_366; // @[el2_lsu_bus_buffer.scala 577:154] - wire _T_4467 = buf_state_0 == 3'h1; // @[el2_lsu_bus_buffer.scala 577:63] - wire _T_4471 = _T_4467 | _T_4454; // @[el2_lsu_bus_buffer.scala 577:74] - wire [2:0] _GEN_367 = {{2'd0}, _T_4471}; // @[el2_lsu_bus_buffer.scala 577:154] - wire [3:0] buf_numvld_pend_any = _T_4488 + _GEN_367; // @[el2_lsu_bus_buffer.scala 577:154] - wire _T_1087 = buf_numvld_pend_any == 4'h0; // @[el2_lsu_bus_buffer.scala 321:53] - wire _T_1088 = ibuf_byp & _T_1087; // @[el2_lsu_bus_buffer.scala 321:31] - wire _T_1089 = ~io_lsu_pkt_r_store; // @[el2_lsu_bus_buffer.scala 321:64] - wire _T_1090 = _T_1089 | io_no_dword_merge_r; // @[el2_lsu_bus_buffer.scala 321:84] - wire ibuf_buf_byp = _T_1088 & _T_1090; // @[el2_lsu_bus_buffer.scala 321:61] - wire _T_1091 = ibuf_buf_byp & io_lsu_commit_r; // @[el2_lsu_bus_buffer.scala 336:32] - wire _T_4778 = buf_state_0 == 3'h3; // @[el2_lsu_bus_buffer.scala 605:62] - wire _T_4780 = _T_4778 & buf_sideeffect[0]; // @[el2_lsu_bus_buffer.scala 605:73] - wire _T_4781 = _T_4780 & io_dec_tlu_sideeffect_posted_disable; // @[el2_lsu_bus_buffer.scala 605:93] - wire _T_4782 = buf_state_1 == 3'h3; // @[el2_lsu_bus_buffer.scala 605:62] - wire _T_4784 = _T_4782 & buf_sideeffect[1]; // @[el2_lsu_bus_buffer.scala 605:73] - wire _T_4785 = _T_4784 & io_dec_tlu_sideeffect_posted_disable; // @[el2_lsu_bus_buffer.scala 605:93] - wire _T_4794 = _T_4781 | _T_4785; // @[el2_lsu_bus_buffer.scala 605:141] - wire _T_4786 = buf_state_2 == 3'h3; // @[el2_lsu_bus_buffer.scala 605:62] - wire _T_4788 = _T_4786 & buf_sideeffect[2]; // @[el2_lsu_bus_buffer.scala 605:73] - wire _T_4789 = _T_4788 & io_dec_tlu_sideeffect_posted_disable; // @[el2_lsu_bus_buffer.scala 605:93] - wire _T_4795 = _T_4794 | _T_4789; // @[el2_lsu_bus_buffer.scala 605:141] - wire _T_4790 = buf_state_3 == 3'h3; // @[el2_lsu_bus_buffer.scala 605:62] - wire _T_4792 = _T_4790 & buf_sideeffect[3]; // @[el2_lsu_bus_buffer.scala 605:73] - wire _T_4793 = _T_4792 & io_dec_tlu_sideeffect_posted_disable; // @[el2_lsu_bus_buffer.scala 605:93] - wire bus_sideeffect_pend = _T_4795 | _T_4793; // @[el2_lsu_bus_buffer.scala 605:141] - wire _T_1092 = io_is_sideeffects_r & bus_sideeffect_pend; // @[el2_lsu_bus_buffer.scala 336:74] - wire _T_1093 = ~_T_1092; // @[el2_lsu_bus_buffer.scala 336:52] - wire _T_1094 = _T_1091 & _T_1093; // @[el2_lsu_bus_buffer.scala 336:50] + wire _T_1085 = io_lsu_addr_m[31:2] != _T_1083; // @[el2_lsu_bus_buffer.scala 320:123] + wire obuf_force_wr_en = _T_1067 & _T_1085; // @[el2_lsu_bus_buffer.scala 320:101] + wire _T_1055 = ~obuf_force_wr_en; // @[el2_lsu_bus_buffer.scala 318:119] + wire obuf_wr_wait = _T_1054 & _T_1055; // @[el2_lsu_bus_buffer.scala 318:117] + wire _T_1056 = |buf_numvld_cmd_any; // @[el2_lsu_bus_buffer.scala 319:75] + wire _T_1057 = obuf_wr_timer < 3'h7; // @[el2_lsu_bus_buffer.scala 319:95] + wire _T_1058 = _T_1056 & _T_1057; // @[el2_lsu_bus_buffer.scala 319:79] + wire [2:0] _T_1060 = obuf_wr_timer + 3'h1; // @[el2_lsu_bus_buffer.scala 319:123] + wire _T_4482 = buf_state_3 == 3'h1; // @[el2_lsu_bus_buffer.scala 578:63] + wire _T_4486 = _T_4482 | _T_4463; // @[el2_lsu_bus_buffer.scala 578:74] + wire _T_4477 = buf_state_2 == 3'h1; // @[el2_lsu_bus_buffer.scala 578:63] + wire _T_4481 = _T_4477 | _T_4460; // @[el2_lsu_bus_buffer.scala 578:74] + wire [1:0] _T_4487 = _T_4486 + _T_4481; // @[el2_lsu_bus_buffer.scala 578:154] + wire _T_4472 = buf_state_1 == 3'h1; // @[el2_lsu_bus_buffer.scala 578:63] + wire _T_4476 = _T_4472 | _T_4457; // @[el2_lsu_bus_buffer.scala 578:74] + wire [1:0] _GEN_366 = {{1'd0}, _T_4476}; // @[el2_lsu_bus_buffer.scala 578:154] + wire [2:0] _T_4488 = _T_4487 + _GEN_366; // @[el2_lsu_bus_buffer.scala 578:154] + wire _T_4467 = buf_state_0 == 3'h1; // @[el2_lsu_bus_buffer.scala 578:63] + wire _T_4471 = _T_4467 | _T_4454; // @[el2_lsu_bus_buffer.scala 578:74] + wire [2:0] _GEN_367 = {{2'd0}, _T_4471}; // @[el2_lsu_bus_buffer.scala 578:154] + wire [3:0] buf_numvld_pend_any = _T_4488 + _GEN_367; // @[el2_lsu_bus_buffer.scala 578:154] + wire _T_1087 = buf_numvld_pend_any == 4'h0; // @[el2_lsu_bus_buffer.scala 322:53] + wire _T_1088 = ibuf_byp & _T_1087; // @[el2_lsu_bus_buffer.scala 322:31] + wire _T_1089 = ~io_lsu_pkt_r_bits_store; // @[el2_lsu_bus_buffer.scala 322:64] + wire _T_1090 = _T_1089 | io_no_dword_merge_r; // @[el2_lsu_bus_buffer.scala 322:89] + wire ibuf_buf_byp = _T_1088 & _T_1090; // @[el2_lsu_bus_buffer.scala 322:61] + wire _T_1091 = ibuf_buf_byp & io_lsu_commit_r; // @[el2_lsu_bus_buffer.scala 337:32] + wire _T_4778 = buf_state_0 == 3'h3; // @[el2_lsu_bus_buffer.scala 606:62] + wire _T_4780 = _T_4778 & buf_sideeffect[0]; // @[el2_lsu_bus_buffer.scala 606:73] + wire _T_4781 = _T_4780 & io_dec_tlu_sideeffect_posted_disable; // @[el2_lsu_bus_buffer.scala 606:93] + wire _T_4782 = buf_state_1 == 3'h3; // @[el2_lsu_bus_buffer.scala 606:62] + wire _T_4784 = _T_4782 & buf_sideeffect[1]; // @[el2_lsu_bus_buffer.scala 606:73] + wire _T_4785 = _T_4784 & io_dec_tlu_sideeffect_posted_disable; // @[el2_lsu_bus_buffer.scala 606:93] + wire _T_4794 = _T_4781 | _T_4785; // @[el2_lsu_bus_buffer.scala 606:141] + wire _T_4786 = buf_state_2 == 3'h3; // @[el2_lsu_bus_buffer.scala 606:62] + wire _T_4788 = _T_4786 & buf_sideeffect[2]; // @[el2_lsu_bus_buffer.scala 606:73] + wire _T_4789 = _T_4788 & io_dec_tlu_sideeffect_posted_disable; // @[el2_lsu_bus_buffer.scala 606:93] + wire _T_4795 = _T_4794 | _T_4789; // @[el2_lsu_bus_buffer.scala 606:141] + wire _T_4790 = buf_state_3 == 3'h3; // @[el2_lsu_bus_buffer.scala 606:62] + wire _T_4792 = _T_4790 & buf_sideeffect[3]; // @[el2_lsu_bus_buffer.scala 606:73] + wire _T_4793 = _T_4792 & io_dec_tlu_sideeffect_posted_disable; // @[el2_lsu_bus_buffer.scala 606:93] + wire bus_sideeffect_pend = _T_4795 | _T_4793; // @[el2_lsu_bus_buffer.scala 606:141] + wire _T_1092 = io_is_sideeffects_r & bus_sideeffect_pend; // @[el2_lsu_bus_buffer.scala 337:74] + wire _T_1093 = ~_T_1092; // @[el2_lsu_bus_buffer.scala 337:52] + wire _T_1094 = _T_1091 & _T_1093; // @[el2_lsu_bus_buffer.scala 337:50] wire [2:0] _T_1099 = _T_1023 ? buf_state_0 : 3'h0; // @[Mux.scala 27:72] wire [2:0] _T_1100 = _T_1024 ? buf_state_1 : 3'h0; // @[Mux.scala 27:72] wire [2:0] _T_1103 = _T_1099 | _T_1100; // @[Mux.scala 27:72] @@ -1122,9 +1122,9 @@ module el2_lsu_bus_buffer( wire [2:0] _T_1104 = _T_1103 | _T_1101; // @[Mux.scala 27:72] wire [2:0] _T_1102 = _T_1026 ? buf_state_3 : 3'h0; // @[Mux.scala 27:72] wire [2:0] _T_1105 = _T_1104 | _T_1102; // @[Mux.scala 27:72] - wire _T_1107 = _T_1105 == 3'h2; // @[el2_lsu_bus_buffer.scala 337:36] - wire found_cmdptr0 = |CmdPtr0Dec; // @[el2_lsu_bus_buffer.scala 436:31] - wire _T_1108 = _T_1107 & found_cmdptr0; // @[el2_lsu_bus_buffer.scala 337:47] + wire _T_1107 = _T_1105 == 3'h2; // @[el2_lsu_bus_buffer.scala 338:36] + wire found_cmdptr0 = |CmdPtr0Dec; // @[el2_lsu_bus_buffer.scala 437:31] + wire _T_1108 = _T_1107 & found_cmdptr0; // @[el2_lsu_bus_buffer.scala 338:47] wire [3:0] _T_1111 = {buf_cmd_state_bus_en_3,buf_cmd_state_bus_en_2,buf_cmd_state_bus_en_1,buf_cmd_state_bus_en_0}; // @[Cat.scala 29:58] wire _T_1120 = _T_1023 & _T_1111[0]; // @[Mux.scala 27:72] wire _T_1121 = _T_1024 & _T_1111[1]; // @[Mux.scala 27:72] @@ -1133,11 +1133,11 @@ module el2_lsu_bus_buffer( wire _T_1125 = _T_1124 | _T_1122; // @[Mux.scala 27:72] wire _T_1123 = _T_1026 & _T_1111[3]; // @[Mux.scala 27:72] wire _T_1126 = _T_1125 | _T_1123; // @[Mux.scala 27:72] - wire _T_1128 = ~_T_1126; // @[el2_lsu_bus_buffer.scala 338:23] - wire _T_1129 = _T_1108 & _T_1128; // @[el2_lsu_bus_buffer.scala 338:21] - wire _T_1146 = _T_1051 & bus_sideeffect_pend; // @[el2_lsu_bus_buffer.scala 338:141] - wire _T_1147 = ~_T_1146; // @[el2_lsu_bus_buffer.scala 338:105] - wire _T_1148 = _T_1129 & _T_1147; // @[el2_lsu_bus_buffer.scala 338:103] + wire _T_1128 = ~_T_1126; // @[el2_lsu_bus_buffer.scala 339:23] + wire _T_1129 = _T_1108 & _T_1128; // @[el2_lsu_bus_buffer.scala 339:21] + wire _T_1146 = _T_1051 & bus_sideeffect_pend; // @[el2_lsu_bus_buffer.scala 339:141] + wire _T_1147 = ~_T_1146; // @[el2_lsu_bus_buffer.scala 339:105] + wire _T_1148 = _T_1129 & _T_1147; // @[el2_lsu_bus_buffer.scala 339:103] reg buf_dual_3; // @[Reg.scala 27:20] reg buf_dual_2; // @[Reg.scala 27:20] reg buf_dual_1; // @[Reg.scala 27:20] @@ -1162,7 +1162,7 @@ module el2_lsu_bus_buffer( wire _T_1184 = _T_1183 | _T_1181; // @[Mux.scala 27:72] wire _T_1182 = _T_1026 & _T_1170[3]; // @[Mux.scala 27:72] wire _T_1185 = _T_1184 | _T_1182; // @[Mux.scala 27:72] - wire _T_1187 = _T_1166 & _T_1185; // @[el2_lsu_bus_buffer.scala 339:77] + wire _T_1187 = _T_1166 & _T_1185; // @[el2_lsu_bus_buffer.scala 340:77] wire _T_1196 = _T_1023 & buf_write[0]; // @[Mux.scala 27:72] wire _T_1197 = _T_1024 & buf_write[1]; // @[Mux.scala 27:72] wire _T_1200 = _T_1196 | _T_1197; // @[Mux.scala 27:72] @@ -1170,41 +1170,41 @@ module el2_lsu_bus_buffer( wire _T_1201 = _T_1200 | _T_1198; // @[Mux.scala 27:72] wire _T_1199 = _T_1026 & buf_write[3]; // @[Mux.scala 27:72] wire _T_1202 = _T_1201 | _T_1199; // @[Mux.scala 27:72] - wire _T_1204 = ~_T_1202; // @[el2_lsu_bus_buffer.scala 339:150] - wire _T_1205 = _T_1187 & _T_1204; // @[el2_lsu_bus_buffer.scala 339:148] - wire _T_1206 = ~_T_1205; // @[el2_lsu_bus_buffer.scala 339:8] - wire [3:0] _T_2020 = ~CmdPtr0Dec; // @[el2_lsu_bus_buffer.scala 432:62] - wire [3:0] _T_2021 = buf_age_3 & _T_2020; // @[el2_lsu_bus_buffer.scala 432:59] - wire _T_2022 = |_T_2021; // @[el2_lsu_bus_buffer.scala 432:76] - wire _T_2023 = ~_T_2022; // @[el2_lsu_bus_buffer.scala 432:45] - wire _T_2025 = ~CmdPtr0Dec[3]; // @[el2_lsu_bus_buffer.scala 432:83] - wire _T_2026 = _T_2023 & _T_2025; // @[el2_lsu_bus_buffer.scala 432:81] - wire _T_2028 = _T_2026 & _T_2621; // @[el2_lsu_bus_buffer.scala 432:98] - wire _T_2030 = _T_2028 & _T_4447; // @[el2_lsu_bus_buffer.scala 432:123] - wire [3:0] _T_2010 = buf_age_2 & _T_2020; // @[el2_lsu_bus_buffer.scala 432:59] - wire _T_2011 = |_T_2010; // @[el2_lsu_bus_buffer.scala 432:76] - wire _T_2012 = ~_T_2011; // @[el2_lsu_bus_buffer.scala 432:45] - wire _T_2014 = ~CmdPtr0Dec[2]; // @[el2_lsu_bus_buffer.scala 432:83] - wire _T_2015 = _T_2012 & _T_2014; // @[el2_lsu_bus_buffer.scala 432:81] - wire _T_2017 = _T_2015 & _T_2616; // @[el2_lsu_bus_buffer.scala 432:98] - wire _T_2019 = _T_2017 & _T_4442; // @[el2_lsu_bus_buffer.scala 432:123] - wire [3:0] _T_1999 = buf_age_1 & _T_2020; // @[el2_lsu_bus_buffer.scala 432:59] - wire _T_2000 = |_T_1999; // @[el2_lsu_bus_buffer.scala 432:76] - wire _T_2001 = ~_T_2000; // @[el2_lsu_bus_buffer.scala 432:45] - wire _T_2003 = ~CmdPtr0Dec[1]; // @[el2_lsu_bus_buffer.scala 432:83] - wire _T_2004 = _T_2001 & _T_2003; // @[el2_lsu_bus_buffer.scala 432:81] - wire _T_2006 = _T_2004 & _T_2611; // @[el2_lsu_bus_buffer.scala 432:98] - wire _T_2008 = _T_2006 & _T_4437; // @[el2_lsu_bus_buffer.scala 432:123] - wire [3:0] _T_1988 = buf_age_0 & _T_2020; // @[el2_lsu_bus_buffer.scala 432:59] - wire _T_1989 = |_T_1988; // @[el2_lsu_bus_buffer.scala 432:76] - wire _T_1990 = ~_T_1989; // @[el2_lsu_bus_buffer.scala 432:45] - wire _T_1992 = ~CmdPtr0Dec[0]; // @[el2_lsu_bus_buffer.scala 432:83] - wire _T_1993 = _T_1990 & _T_1992; // @[el2_lsu_bus_buffer.scala 432:81] - wire _T_1995 = _T_1993 & _T_2606; // @[el2_lsu_bus_buffer.scala 432:98] - wire _T_1997 = _T_1995 & _T_4432; // @[el2_lsu_bus_buffer.scala 432:123] + wire _T_1204 = ~_T_1202; // @[el2_lsu_bus_buffer.scala 340:150] + wire _T_1205 = _T_1187 & _T_1204; // @[el2_lsu_bus_buffer.scala 340:148] + wire _T_1206 = ~_T_1205; // @[el2_lsu_bus_buffer.scala 340:8] + wire [3:0] _T_2020 = ~CmdPtr0Dec; // @[el2_lsu_bus_buffer.scala 433:62] + wire [3:0] _T_2021 = buf_age_3 & _T_2020; // @[el2_lsu_bus_buffer.scala 433:59] + wire _T_2022 = |_T_2021; // @[el2_lsu_bus_buffer.scala 433:76] + wire _T_2023 = ~_T_2022; // @[el2_lsu_bus_buffer.scala 433:45] + wire _T_2025 = ~CmdPtr0Dec[3]; // @[el2_lsu_bus_buffer.scala 433:83] + wire _T_2026 = _T_2023 & _T_2025; // @[el2_lsu_bus_buffer.scala 433:81] + wire _T_2028 = _T_2026 & _T_2621; // @[el2_lsu_bus_buffer.scala 433:98] + wire _T_2030 = _T_2028 & _T_4447; // @[el2_lsu_bus_buffer.scala 433:123] + wire [3:0] _T_2010 = buf_age_2 & _T_2020; // @[el2_lsu_bus_buffer.scala 433:59] + wire _T_2011 = |_T_2010; // @[el2_lsu_bus_buffer.scala 433:76] + wire _T_2012 = ~_T_2011; // @[el2_lsu_bus_buffer.scala 433:45] + wire _T_2014 = ~CmdPtr0Dec[2]; // @[el2_lsu_bus_buffer.scala 433:83] + wire _T_2015 = _T_2012 & _T_2014; // @[el2_lsu_bus_buffer.scala 433:81] + wire _T_2017 = _T_2015 & _T_2616; // @[el2_lsu_bus_buffer.scala 433:98] + wire _T_2019 = _T_2017 & _T_4442; // @[el2_lsu_bus_buffer.scala 433:123] + wire [3:0] _T_1999 = buf_age_1 & _T_2020; // @[el2_lsu_bus_buffer.scala 433:59] + wire _T_2000 = |_T_1999; // @[el2_lsu_bus_buffer.scala 433:76] + wire _T_2001 = ~_T_2000; // @[el2_lsu_bus_buffer.scala 433:45] + wire _T_2003 = ~CmdPtr0Dec[1]; // @[el2_lsu_bus_buffer.scala 433:83] + wire _T_2004 = _T_2001 & _T_2003; // @[el2_lsu_bus_buffer.scala 433:81] + wire _T_2006 = _T_2004 & _T_2611; // @[el2_lsu_bus_buffer.scala 433:98] + wire _T_2008 = _T_2006 & _T_4437; // @[el2_lsu_bus_buffer.scala 433:123] + wire [3:0] _T_1988 = buf_age_0 & _T_2020; // @[el2_lsu_bus_buffer.scala 433:59] + wire _T_1989 = |_T_1988; // @[el2_lsu_bus_buffer.scala 433:76] + wire _T_1990 = ~_T_1989; // @[el2_lsu_bus_buffer.scala 433:45] + wire _T_1992 = ~CmdPtr0Dec[0]; // @[el2_lsu_bus_buffer.scala 433:83] + wire _T_1993 = _T_1990 & _T_1992; // @[el2_lsu_bus_buffer.scala 433:81] + wire _T_1995 = _T_1993 & _T_2606; // @[el2_lsu_bus_buffer.scala 433:98] + wire _T_1997 = _T_1995 & _T_4432; // @[el2_lsu_bus_buffer.scala 433:123] wire [3:0] CmdPtr1Dec = {_T_2030,_T_2019,_T_2008,_T_1997}; // @[Cat.scala 29:58] - wire found_cmdptr1 = |CmdPtr1Dec; // @[el2_lsu_bus_buffer.scala 437:31] - wire _T_1207 = _T_1206 | found_cmdptr1; // @[el2_lsu_bus_buffer.scala 339:181] + wire found_cmdptr1 = |CmdPtr1Dec; // @[el2_lsu_bus_buffer.scala 438:31] + wire _T_1207 = _T_1206 | found_cmdptr1; // @[el2_lsu_bus_buffer.scala 340:181] wire [3:0] _T_1210 = {buf_nomerge_3,buf_nomerge_2,buf_nomerge_1,buf_nomerge_0}; // @[Cat.scala 29:58] wire _T_1219 = _T_1023 & _T_1210[0]; // @[Mux.scala 27:72] wire _T_1220 = _T_1024 & _T_1210[1]; // @[Mux.scala 27:72] @@ -1213,77 +1213,77 @@ module el2_lsu_bus_buffer( wire _T_1224 = _T_1223 | _T_1221; // @[Mux.scala 27:72] wire _T_1222 = _T_1026 & _T_1210[3]; // @[Mux.scala 27:72] wire _T_1225 = _T_1224 | _T_1222; // @[Mux.scala 27:72] - wire _T_1227 = _T_1207 | _T_1225; // @[el2_lsu_bus_buffer.scala 339:197] - wire _T_1228 = _T_1227 | obuf_force_wr_en; // @[el2_lsu_bus_buffer.scala 339:269] - wire _T_1229 = _T_1148 & _T_1228; // @[el2_lsu_bus_buffer.scala 338:164] - wire _T_1230 = _T_1094 | _T_1229; // @[el2_lsu_bus_buffer.scala 336:98] + wire _T_1227 = _T_1207 | _T_1225; // @[el2_lsu_bus_buffer.scala 340:197] + wire _T_1228 = _T_1227 | obuf_force_wr_en; // @[el2_lsu_bus_buffer.scala 340:269] + wire _T_1229 = _T_1148 & _T_1228; // @[el2_lsu_bus_buffer.scala 339:164] + wire _T_1230 = _T_1094 | _T_1229; // @[el2_lsu_bus_buffer.scala 337:98] reg obuf_write; // @[Reg.scala 27:20] - reg obuf_cmd_done; // @[el2_lsu_bus_buffer.scala 401:54] - reg obuf_data_done; // @[el2_lsu_bus_buffer.scala 402:55] - wire _T_4853 = obuf_cmd_done | obuf_data_done; // @[el2_lsu_bus_buffer.scala 609:54] - wire _T_4854 = obuf_cmd_done ? io_lsu_axi_wready : io_lsu_axi_awready; // @[el2_lsu_bus_buffer.scala 609:75] - wire _T_4856 = _T_4853 ? _T_4854 : io_lsu_axi_awready; // @[el2_lsu_bus_buffer.scala 609:39] - wire bus_cmd_ready = obuf_write ? _T_4856 : io_lsu_axi_arready; // @[el2_lsu_bus_buffer.scala 609:23] - wire _T_1231 = ~obuf_valid; // @[el2_lsu_bus_buffer.scala 340:48] - wire _T_1232 = bus_cmd_ready | _T_1231; // @[el2_lsu_bus_buffer.scala 340:46] + reg obuf_cmd_done; // @[el2_lsu_bus_buffer.scala 402:54] + reg obuf_data_done; // @[el2_lsu_bus_buffer.scala 403:55] + wire _T_4853 = obuf_cmd_done | obuf_data_done; // @[el2_lsu_bus_buffer.scala 610:54] + wire _T_4854 = obuf_cmd_done ? io_lsu_axi_wready : io_lsu_axi_awready; // @[el2_lsu_bus_buffer.scala 610:75] + wire _T_4856 = _T_4853 ? _T_4854 : io_lsu_axi_awready; // @[el2_lsu_bus_buffer.scala 610:39] + wire bus_cmd_ready = obuf_write ? _T_4856 : io_lsu_axi_arready; // @[el2_lsu_bus_buffer.scala 610:23] + wire _T_1231 = ~obuf_valid; // @[el2_lsu_bus_buffer.scala 341:48] + wire _T_1232 = bus_cmd_ready | _T_1231; // @[el2_lsu_bus_buffer.scala 341:46] reg obuf_nosend; // @[Reg.scala 27:20] - wire _T_1233 = _T_1232 | obuf_nosend; // @[el2_lsu_bus_buffer.scala 340:60] - wire _T_1234 = _T_1230 & _T_1233; // @[el2_lsu_bus_buffer.scala 340:29] - wire _T_1235 = ~obuf_wr_wait; // @[el2_lsu_bus_buffer.scala 340:77] - wire _T_1236 = _T_1234 & _T_1235; // @[el2_lsu_bus_buffer.scala 340:75] + wire _T_1233 = _T_1232 | obuf_nosend; // @[el2_lsu_bus_buffer.scala 341:60] + wire _T_1234 = _T_1230 & _T_1233; // @[el2_lsu_bus_buffer.scala 341:29] + wire _T_1235 = ~obuf_wr_wait; // @[el2_lsu_bus_buffer.scala 341:77] + wire _T_1236 = _T_1234 & _T_1235; // @[el2_lsu_bus_buffer.scala 341:75] reg [31:0] obuf_addr; // @[el2_lib.scala 514:16] - wire _T_4801 = obuf_addr[31:3] == buf_addr_0[31:3]; // @[el2_lsu_bus_buffer.scala 607:56] - wire _T_4802 = obuf_valid & _T_4801; // @[el2_lsu_bus_buffer.scala 607:38] - wire _T_4804 = obuf_tag1 == 2'h0; // @[el2_lsu_bus_buffer.scala 607:126] - wire _T_4805 = obuf_merge & _T_4804; // @[el2_lsu_bus_buffer.scala 607:114] - wire _T_4806 = _T_3562 | _T_4805; // @[el2_lsu_bus_buffer.scala 607:100] - wire _T_4807 = ~_T_4806; // @[el2_lsu_bus_buffer.scala 607:80] - wire _T_4808 = _T_4802 & _T_4807; // @[el2_lsu_bus_buffer.scala 607:78] + wire _T_4801 = obuf_addr[31:3] == buf_addr_0[31:3]; // @[el2_lsu_bus_buffer.scala 608:56] + wire _T_4802 = obuf_valid & _T_4801; // @[el2_lsu_bus_buffer.scala 608:38] + wire _T_4804 = obuf_tag1 == 2'h0; // @[el2_lsu_bus_buffer.scala 608:126] + wire _T_4805 = obuf_merge & _T_4804; // @[el2_lsu_bus_buffer.scala 608:114] + wire _T_4806 = _T_3562 | _T_4805; // @[el2_lsu_bus_buffer.scala 608:100] + wire _T_4807 = ~_T_4806; // @[el2_lsu_bus_buffer.scala 608:80] + wire _T_4808 = _T_4802 & _T_4807; // @[el2_lsu_bus_buffer.scala 608:78] wire _T_4845 = _T_4778 & _T_4808; // @[Mux.scala 27:72] - wire _T_4813 = obuf_addr[31:3] == buf_addr_1[31:3]; // @[el2_lsu_bus_buffer.scala 607:56] - wire _T_4814 = obuf_valid & _T_4813; // @[el2_lsu_bus_buffer.scala 607:38] - wire _T_4816 = obuf_tag1 == 2'h1; // @[el2_lsu_bus_buffer.scala 607:126] - wire _T_4817 = obuf_merge & _T_4816; // @[el2_lsu_bus_buffer.scala 607:114] - wire _T_4818 = _T_3755 | _T_4817; // @[el2_lsu_bus_buffer.scala 607:100] - wire _T_4819 = ~_T_4818; // @[el2_lsu_bus_buffer.scala 607:80] - wire _T_4820 = _T_4814 & _T_4819; // @[el2_lsu_bus_buffer.scala 607:78] + wire _T_4813 = obuf_addr[31:3] == buf_addr_1[31:3]; // @[el2_lsu_bus_buffer.scala 608:56] + wire _T_4814 = obuf_valid & _T_4813; // @[el2_lsu_bus_buffer.scala 608:38] + wire _T_4816 = obuf_tag1 == 2'h1; // @[el2_lsu_bus_buffer.scala 608:126] + wire _T_4817 = obuf_merge & _T_4816; // @[el2_lsu_bus_buffer.scala 608:114] + wire _T_4818 = _T_3755 | _T_4817; // @[el2_lsu_bus_buffer.scala 608:100] + wire _T_4819 = ~_T_4818; // @[el2_lsu_bus_buffer.scala 608:80] + wire _T_4820 = _T_4814 & _T_4819; // @[el2_lsu_bus_buffer.scala 608:78] wire _T_4846 = _T_4782 & _T_4820; // @[Mux.scala 27:72] wire _T_4849 = _T_4845 | _T_4846; // @[Mux.scala 27:72] - wire _T_4825 = obuf_addr[31:3] == buf_addr_2[31:3]; // @[el2_lsu_bus_buffer.scala 607:56] - wire _T_4826 = obuf_valid & _T_4825; // @[el2_lsu_bus_buffer.scala 607:38] - wire _T_4828 = obuf_tag1 == 2'h2; // @[el2_lsu_bus_buffer.scala 607:126] - wire _T_4829 = obuf_merge & _T_4828; // @[el2_lsu_bus_buffer.scala 607:114] - wire _T_4830 = _T_3948 | _T_4829; // @[el2_lsu_bus_buffer.scala 607:100] - wire _T_4831 = ~_T_4830; // @[el2_lsu_bus_buffer.scala 607:80] - wire _T_4832 = _T_4826 & _T_4831; // @[el2_lsu_bus_buffer.scala 607:78] + wire _T_4825 = obuf_addr[31:3] == buf_addr_2[31:3]; // @[el2_lsu_bus_buffer.scala 608:56] + wire _T_4826 = obuf_valid & _T_4825; // @[el2_lsu_bus_buffer.scala 608:38] + wire _T_4828 = obuf_tag1 == 2'h2; // @[el2_lsu_bus_buffer.scala 608:126] + wire _T_4829 = obuf_merge & _T_4828; // @[el2_lsu_bus_buffer.scala 608:114] + wire _T_4830 = _T_3948 | _T_4829; // @[el2_lsu_bus_buffer.scala 608:100] + wire _T_4831 = ~_T_4830; // @[el2_lsu_bus_buffer.scala 608:80] + wire _T_4832 = _T_4826 & _T_4831; // @[el2_lsu_bus_buffer.scala 608:78] wire _T_4847 = _T_4786 & _T_4832; // @[Mux.scala 27:72] wire _T_4850 = _T_4849 | _T_4847; // @[Mux.scala 27:72] - wire _T_4837 = obuf_addr[31:3] == buf_addr_3[31:3]; // @[el2_lsu_bus_buffer.scala 607:56] - wire _T_4838 = obuf_valid & _T_4837; // @[el2_lsu_bus_buffer.scala 607:38] - wire _T_4840 = obuf_tag1 == 2'h3; // @[el2_lsu_bus_buffer.scala 607:126] - wire _T_4841 = obuf_merge & _T_4840; // @[el2_lsu_bus_buffer.scala 607:114] - wire _T_4842 = _T_4141 | _T_4841; // @[el2_lsu_bus_buffer.scala 607:100] - wire _T_4843 = ~_T_4842; // @[el2_lsu_bus_buffer.scala 607:80] - wire _T_4844 = _T_4838 & _T_4843; // @[el2_lsu_bus_buffer.scala 607:78] + wire _T_4837 = obuf_addr[31:3] == buf_addr_3[31:3]; // @[el2_lsu_bus_buffer.scala 608:56] + wire _T_4838 = obuf_valid & _T_4837; // @[el2_lsu_bus_buffer.scala 608:38] + wire _T_4840 = obuf_tag1 == 2'h3; // @[el2_lsu_bus_buffer.scala 608:126] + wire _T_4841 = obuf_merge & _T_4840; // @[el2_lsu_bus_buffer.scala 608:114] + wire _T_4842 = _T_4141 | _T_4841; // @[el2_lsu_bus_buffer.scala 608:100] + wire _T_4843 = ~_T_4842; // @[el2_lsu_bus_buffer.scala 608:80] + wire _T_4844 = _T_4838 & _T_4843; // @[el2_lsu_bus_buffer.scala 608:78] wire _T_4848 = _T_4790 & _T_4844; // @[Mux.scala 27:72] wire bus_addr_match_pending = _T_4850 | _T_4848; // @[Mux.scala 27:72] - wire _T_1239 = ~bus_addr_match_pending; // @[el2_lsu_bus_buffer.scala 340:118] - wire _T_1240 = _T_1236 & _T_1239; // @[el2_lsu_bus_buffer.scala 340:116] - wire obuf_wr_en = _T_1240 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 340:142] - wire _T_1242 = obuf_valid & obuf_nosend; // @[el2_lsu_bus_buffer.scala 342:47] - wire bus_wcmd_sent = io_lsu_axi_awvalid & io_lsu_axi_awready; // @[el2_lsu_bus_buffer.scala 610:39] - wire _T_4860 = obuf_cmd_done | bus_wcmd_sent; // @[el2_lsu_bus_buffer.scala 612:35] - wire bus_wdata_sent = io_lsu_axi_wvalid & io_lsu_axi_wready; // @[el2_lsu_bus_buffer.scala 611:39] - wire _T_4861 = obuf_data_done | bus_wdata_sent; // @[el2_lsu_bus_buffer.scala 612:70] - wire _T_4862 = _T_4860 & _T_4861; // @[el2_lsu_bus_buffer.scala 612:52] - wire _T_4863 = io_lsu_axi_arvalid & io_lsu_axi_arready; // @[el2_lsu_bus_buffer.scala 612:111] - wire bus_cmd_sent = _T_4862 | _T_4863; // @[el2_lsu_bus_buffer.scala 612:89] - wire _T_1243 = bus_cmd_sent | _T_1242; // @[el2_lsu_bus_buffer.scala 342:33] - wire _T_1244 = ~obuf_wr_en; // @[el2_lsu_bus_buffer.scala 342:65] - wire _T_1245 = _T_1243 & _T_1244; // @[el2_lsu_bus_buffer.scala 342:63] - wire _T_1246 = _T_1245 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 342:77] - wire obuf_rst = _T_1246 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 342:98] - wire obuf_write_in = ibuf_buf_byp ? io_lsu_pkt_r_store : _T_1202; // @[el2_lsu_bus_buffer.scala 343:26] + wire _T_1239 = ~bus_addr_match_pending; // @[el2_lsu_bus_buffer.scala 341:118] + wire _T_1240 = _T_1236 & _T_1239; // @[el2_lsu_bus_buffer.scala 341:116] + wire obuf_wr_en = _T_1240 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 341:142] + wire _T_1242 = obuf_valid & obuf_nosend; // @[el2_lsu_bus_buffer.scala 343:47] + wire bus_wcmd_sent = io_lsu_axi_awvalid & io_lsu_axi_awready; // @[el2_lsu_bus_buffer.scala 611:39] + wire _T_4860 = obuf_cmd_done | bus_wcmd_sent; // @[el2_lsu_bus_buffer.scala 613:35] + wire bus_wdata_sent = io_lsu_axi_wvalid & io_lsu_axi_wready; // @[el2_lsu_bus_buffer.scala 612:39] + wire _T_4861 = obuf_data_done | bus_wdata_sent; // @[el2_lsu_bus_buffer.scala 613:70] + wire _T_4862 = _T_4860 & _T_4861; // @[el2_lsu_bus_buffer.scala 613:52] + wire _T_4863 = io_lsu_axi_arvalid & io_lsu_axi_arready; // @[el2_lsu_bus_buffer.scala 613:111] + wire bus_cmd_sent = _T_4862 | _T_4863; // @[el2_lsu_bus_buffer.scala 613:89] + wire _T_1243 = bus_cmd_sent | _T_1242; // @[el2_lsu_bus_buffer.scala 343:33] + wire _T_1244 = ~obuf_wr_en; // @[el2_lsu_bus_buffer.scala 343:65] + wire _T_1245 = _T_1243 & _T_1244; // @[el2_lsu_bus_buffer.scala 343:63] + wire _T_1246 = _T_1245 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 343:77] + wire obuf_rst = _T_1246 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 343:98] + wire obuf_write_in = ibuf_buf_byp ? io_lsu_pkt_r_bits_store : _T_1202; // @[el2_lsu_bus_buffer.scala 344:26] wire [31:0] _T_1283 = _T_1023 ? buf_addr_0 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1284 = _T_1024 ? buf_addr_1 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1285 = _T_1025 ? buf_addr_2 : 32'h0; // @[Mux.scala 27:72] @@ -1291,7 +1291,7 @@ module el2_lsu_bus_buffer( wire [31:0] _T_1287 = _T_1283 | _T_1284; // @[Mux.scala 27:72] wire [31:0] _T_1288 = _T_1287 | _T_1285; // @[Mux.scala 27:72] wire [31:0] _T_1289 = _T_1288 | _T_1286; // @[Mux.scala 27:72] - wire [31:0] obuf_addr_in = ibuf_buf_byp ? io_lsu_addr_r : _T_1289; // @[el2_lsu_bus_buffer.scala 345:25] + wire [31:0] obuf_addr_in = ibuf_buf_byp ? io_lsu_addr_r : _T_1289; // @[el2_lsu_bus_buffer.scala 346:25] reg [1:0] buf_sz_0; // @[Reg.scala 27:20] wire [1:0] _T_1296 = _T_1023 ? buf_sz_0 : 2'h0; // @[Mux.scala 27:72] reg [1:0] buf_sz_1; // @[Reg.scala 27:20] @@ -1303,51 +1303,63 @@ module el2_lsu_bus_buffer( wire [1:0] _T_1300 = _T_1296 | _T_1297; // @[Mux.scala 27:72] wire [1:0] _T_1301 = _T_1300 | _T_1298; // @[Mux.scala 27:72] wire [1:0] _T_1302 = _T_1301 | _T_1299; // @[Mux.scala 27:72] - wire [1:0] obuf_sz_in = ibuf_buf_byp ? ibuf_sz_in : _T_1302; // @[el2_lsu_bus_buffer.scala 348:23] - wire _T_1304 = obuf_wr_en | obuf_rst; // @[el2_lsu_bus_buffer.scala 357:39] - wire _T_1305 = ~_T_1304; // @[el2_lsu_bus_buffer.scala 357:26] - wire _T_1311 = obuf_sz_in == 2'h0; // @[el2_lsu_bus_buffer.scala 361:72] - wire _T_1314 = ~obuf_addr_in[0]; // @[el2_lsu_bus_buffer.scala 361:98] - wire _T_1315 = obuf_sz_in[0] & _T_1314; // @[el2_lsu_bus_buffer.scala 361:96] - wire _T_1316 = _T_1311 | _T_1315; // @[el2_lsu_bus_buffer.scala 361:79] - wire _T_1319 = |obuf_addr_in[1:0]; // @[el2_lsu_bus_buffer.scala 361:153] - wire _T_1320 = ~_T_1319; // @[el2_lsu_bus_buffer.scala 361:134] - wire _T_1321 = obuf_sz_in[1] & _T_1320; // @[el2_lsu_bus_buffer.scala 361:132] - wire _T_1322 = _T_1316 | _T_1321; // @[el2_lsu_bus_buffer.scala 361:116] - wire obuf_aligned_in = ibuf_buf_byp ? is_aligned_r : _T_1322; // @[el2_lsu_bus_buffer.scala 361:28] - wire _T_1339 = obuf_addr_in[31:3] == obuf_addr[31:3]; // @[el2_lsu_bus_buffer.scala 375:40] - wire _T_1340 = _T_1339 & obuf_aligned_in; // @[el2_lsu_bus_buffer.scala 375:60] + wire [1:0] obuf_sz_in = ibuf_buf_byp ? ibuf_sz_in : _T_1302; // @[el2_lsu_bus_buffer.scala 349:23] + wire [7:0] _T_2079 = {4'h0,_T_2030,_T_2019,_T_2008,_T_1997}; // @[Cat.scala 29:58] + wire _T_2082 = _T_2079[4] | _T_2079[5]; // @[el2_lsu_bus_buffer.scala 440:42] + wire _T_2084 = _T_2082 | _T_2079[6]; // @[el2_lsu_bus_buffer.scala 440:48] + wire _T_2086 = _T_2084 | _T_2079[7]; // @[el2_lsu_bus_buffer.scala 440:54] + wire _T_2089 = _T_2079[2] | _T_2079[3]; // @[el2_lsu_bus_buffer.scala 440:67] + wire _T_2091 = _T_2089 | _T_2079[6]; // @[el2_lsu_bus_buffer.scala 440:73] + wire _T_2093 = _T_2091 | _T_2079[7]; // @[el2_lsu_bus_buffer.scala 440:79] + wire _T_2096 = _T_2079[1] | _T_2079[3]; // @[el2_lsu_bus_buffer.scala 440:92] + wire _T_2098 = _T_2096 | _T_2079[5]; // @[el2_lsu_bus_buffer.scala 440:98] + wire _T_2100 = _T_2098 | _T_2079[7]; // @[el2_lsu_bus_buffer.scala 440:104] + wire [2:0] _T_2102 = {_T_2086,_T_2093,_T_2100}; // @[Cat.scala 29:58] + wire [1:0] CmdPtr1 = _T_2102[1:0]; // @[el2_lsu_bus_buffer.scala 447:11] + wire _T_1304 = obuf_wr_en | obuf_rst; // @[el2_lsu_bus_buffer.scala 358:39] + wire _T_1305 = ~_T_1304; // @[el2_lsu_bus_buffer.scala 358:26] + wire _T_1311 = obuf_sz_in == 2'h0; // @[el2_lsu_bus_buffer.scala 362:72] + wire _T_1314 = ~obuf_addr_in[0]; // @[el2_lsu_bus_buffer.scala 362:98] + wire _T_1315 = obuf_sz_in[0] & _T_1314; // @[el2_lsu_bus_buffer.scala 362:96] + wire _T_1316 = _T_1311 | _T_1315; // @[el2_lsu_bus_buffer.scala 362:79] + wire _T_1319 = |obuf_addr_in[1:0]; // @[el2_lsu_bus_buffer.scala 362:153] + wire _T_1320 = ~_T_1319; // @[el2_lsu_bus_buffer.scala 362:134] + wire _T_1321 = obuf_sz_in[1] & _T_1320; // @[el2_lsu_bus_buffer.scala 362:132] + wire _T_1322 = _T_1316 | _T_1321; // @[el2_lsu_bus_buffer.scala 362:116] + wire obuf_aligned_in = ibuf_buf_byp ? is_aligned_r : _T_1322; // @[el2_lsu_bus_buffer.scala 362:28] + wire _T_1339 = obuf_addr_in[31:3] == obuf_addr[31:3]; // @[el2_lsu_bus_buffer.scala 376:40] + wire _T_1340 = _T_1339 & obuf_aligned_in; // @[el2_lsu_bus_buffer.scala 376:60] reg obuf_sideeffect; // @[Reg.scala 27:20] - wire _T_1341 = ~obuf_sideeffect; // @[el2_lsu_bus_buffer.scala 375:80] - wire _T_1342 = _T_1340 & _T_1341; // @[el2_lsu_bus_buffer.scala 375:78] - wire _T_1343 = ~obuf_write; // @[el2_lsu_bus_buffer.scala 375:99] - wire _T_1344 = _T_1342 & _T_1343; // @[el2_lsu_bus_buffer.scala 375:97] - wire _T_1345 = ~obuf_write_in; // @[el2_lsu_bus_buffer.scala 375:113] - wire _T_1346 = _T_1344 & _T_1345; // @[el2_lsu_bus_buffer.scala 375:111] - wire _T_1347 = ~io_dec_tlu_external_ldfwd_disable; // @[el2_lsu_bus_buffer.scala 375:130] - wire _T_1348 = _T_1346 & _T_1347; // @[el2_lsu_bus_buffer.scala 375:128] - wire _T_1349 = ~obuf_nosend; // @[el2_lsu_bus_buffer.scala 376:20] - wire _T_1350 = obuf_valid & _T_1349; // @[el2_lsu_bus_buffer.scala 376:18] - reg obuf_rdrsp_pend; // @[el2_lsu_bus_buffer.scala 403:56] - wire bus_rsp_read = io_lsu_axi_rvalid & io_lsu_axi_rready; // @[el2_lsu_bus_buffer.scala 613:37] - reg [2:0] obuf_rdrsp_tag; // @[el2_lsu_bus_buffer.scala 404:55] - wire _T_1351 = io_lsu_axi_rid == obuf_rdrsp_tag; // @[el2_lsu_bus_buffer.scala 376:90] - wire _T_1352 = bus_rsp_read & _T_1351; // @[el2_lsu_bus_buffer.scala 376:70] - wire _T_1353 = ~_T_1352; // @[el2_lsu_bus_buffer.scala 376:55] - wire _T_1354 = obuf_rdrsp_pend & _T_1353; // @[el2_lsu_bus_buffer.scala 376:53] - wire _T_1355 = _T_1350 | _T_1354; // @[el2_lsu_bus_buffer.scala 376:34] - wire obuf_nosend_in = _T_1348 & _T_1355; // @[el2_lsu_bus_buffer.scala 375:165] - wire _T_1323 = ~obuf_nosend_in; // @[el2_lsu_bus_buffer.scala 369:44] - wire _T_1324 = obuf_wr_en & _T_1323; // @[el2_lsu_bus_buffer.scala 369:42] - wire _T_1325 = ~_T_1324; // @[el2_lsu_bus_buffer.scala 369:29] - wire _T_1326 = _T_1325 & obuf_rdrsp_pend; // @[el2_lsu_bus_buffer.scala 369:61] - wire _T_1330 = _T_1326 & _T_1353; // @[el2_lsu_bus_buffer.scala 369:79] - wire _T_1332 = bus_cmd_sent & _T_1343; // @[el2_lsu_bus_buffer.scala 370:20] - wire _T_1333 = ~io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 370:37] - wire _T_1334 = _T_1332 & _T_1333; // @[el2_lsu_bus_buffer.scala 370:35] + wire _T_1341 = ~obuf_sideeffect; // @[el2_lsu_bus_buffer.scala 376:80] + wire _T_1342 = _T_1340 & _T_1341; // @[el2_lsu_bus_buffer.scala 376:78] + wire _T_1343 = ~obuf_write; // @[el2_lsu_bus_buffer.scala 376:99] + wire _T_1344 = _T_1342 & _T_1343; // @[el2_lsu_bus_buffer.scala 376:97] + wire _T_1345 = ~obuf_write_in; // @[el2_lsu_bus_buffer.scala 376:113] + wire _T_1346 = _T_1344 & _T_1345; // @[el2_lsu_bus_buffer.scala 376:111] + wire _T_1347 = ~io_dec_tlu_external_ldfwd_disable; // @[el2_lsu_bus_buffer.scala 376:130] + wire _T_1348 = _T_1346 & _T_1347; // @[el2_lsu_bus_buffer.scala 376:128] + wire _T_1349 = ~obuf_nosend; // @[el2_lsu_bus_buffer.scala 377:20] + wire _T_1350 = obuf_valid & _T_1349; // @[el2_lsu_bus_buffer.scala 377:18] + reg obuf_rdrsp_pend; // @[el2_lsu_bus_buffer.scala 404:56] + wire bus_rsp_read = io_lsu_axi_rvalid & io_lsu_axi_rready; // @[el2_lsu_bus_buffer.scala 614:37] + reg [2:0] obuf_rdrsp_tag; // @[el2_lsu_bus_buffer.scala 405:55] + wire _T_1351 = io_lsu_axi_rid == obuf_rdrsp_tag; // @[el2_lsu_bus_buffer.scala 377:90] + wire _T_1352 = bus_rsp_read & _T_1351; // @[el2_lsu_bus_buffer.scala 377:70] + wire _T_1353 = ~_T_1352; // @[el2_lsu_bus_buffer.scala 377:55] + wire _T_1354 = obuf_rdrsp_pend & _T_1353; // @[el2_lsu_bus_buffer.scala 377:53] + wire _T_1355 = _T_1350 | _T_1354; // @[el2_lsu_bus_buffer.scala 377:34] + wire obuf_nosend_in = _T_1348 & _T_1355; // @[el2_lsu_bus_buffer.scala 376:165] + wire _T_1323 = ~obuf_nosend_in; // @[el2_lsu_bus_buffer.scala 370:44] + wire _T_1324 = obuf_wr_en & _T_1323; // @[el2_lsu_bus_buffer.scala 370:42] + wire _T_1325 = ~_T_1324; // @[el2_lsu_bus_buffer.scala 370:29] + wire _T_1326 = _T_1325 & obuf_rdrsp_pend; // @[el2_lsu_bus_buffer.scala 370:61] + wire _T_1330 = _T_1326 & _T_1353; // @[el2_lsu_bus_buffer.scala 370:79] + wire _T_1332 = bus_cmd_sent & _T_1343; // @[el2_lsu_bus_buffer.scala 371:20] + wire _T_1333 = ~io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 371:37] + wire _T_1334 = _T_1332 & _T_1333; // @[el2_lsu_bus_buffer.scala 371:35] wire [7:0] _T_1358 = {ldst_byteen_lo_r,4'h0}; // @[Cat.scala 29:58] wire [7:0] _T_1359 = {4'h0,ldst_byteen_lo_r}; // @[Cat.scala 29:58] - wire [7:0] _T_1360 = io_lsu_addr_r[2] ? _T_1358 : _T_1359; // @[el2_lsu_bus_buffer.scala 377:46] + wire [7:0] _T_1360 = io_lsu_addr_r[2] ? _T_1358 : _T_1359; // @[el2_lsu_bus_buffer.scala 378:46] wire [3:0] _T_1379 = _T_1023 ? buf_byteen_0 : 4'h0; // @[Mux.scala 27:72] wire [3:0] _T_1380 = _T_1024 ? buf_byteen_1 : 4'h0; // @[Mux.scala 27:72] wire [3:0] _T_1381 = _T_1025 ? buf_byteen_2 : 4'h0; // @[Mux.scala 27:72] @@ -1357,18 +1369,36 @@ module el2_lsu_bus_buffer( wire [3:0] _T_1385 = _T_1384 | _T_1382; // @[Mux.scala 27:72] wire [7:0] _T_1387 = {_T_1385,4'h0}; // @[Cat.scala 29:58] wire [7:0] _T_1400 = {4'h0,_T_1385}; // @[Cat.scala 29:58] - wire [7:0] _T_1401 = _T_1289[2] ? _T_1387 : _T_1400; // @[el2_lsu_bus_buffer.scala 378:8] - wire [7:0] obuf_byteen0_in = ibuf_buf_byp ? _T_1360 : _T_1401; // @[el2_lsu_bus_buffer.scala 377:28] + wire [7:0] _T_1401 = _T_1289[2] ? _T_1387 : _T_1400; // @[el2_lsu_bus_buffer.scala 379:8] + wire [7:0] obuf_byteen0_in = ibuf_buf_byp ? _T_1360 : _T_1401; // @[el2_lsu_bus_buffer.scala 378:28] wire [7:0] _T_1403 = {ldst_byteen_hi_r,4'h0}; // @[Cat.scala 29:58] wire [7:0] _T_1404 = {4'h0,ldst_byteen_hi_r}; // @[Cat.scala 29:58] - wire [7:0] _T_1405 = io_end_addr_r[2] ? _T_1403 : _T_1404; // @[el2_lsu_bus_buffer.scala 379:46] - wire [7:0] _T_1432 = {buf_byteen_0,4'h0}; // @[Cat.scala 29:58] - wire [7:0] _T_1445 = {4'h0,buf_byteen_0}; // @[Cat.scala 29:58] - wire [7:0] _T_1446 = buf_addr_0[2] ? _T_1432 : _T_1445; // @[el2_lsu_bus_buffer.scala 380:8] - wire [7:0] obuf_byteen1_in = ibuf_buf_byp ? _T_1405 : _T_1446; // @[el2_lsu_bus_buffer.scala 379:28] + wire [7:0] _T_1405 = io_end_addr_r[2] ? _T_1403 : _T_1404; // @[el2_lsu_bus_buffer.scala 380:46] + wire _T_1406 = CmdPtr1 == 2'h0; // @[el2_lsu_bus_buffer.scala 112:123] + wire _T_1407 = CmdPtr1 == 2'h1; // @[el2_lsu_bus_buffer.scala 112:123] + wire _T_1408 = CmdPtr1 == 2'h2; // @[el2_lsu_bus_buffer.scala 112:123] + wire _T_1409 = CmdPtr1 == 2'h3; // @[el2_lsu_bus_buffer.scala 112:123] + wire [31:0] _T_1410 = _T_1406 ? buf_addr_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1411 = _T_1407 ? buf_addr_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1412 = _T_1408 ? buf_addr_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1413 = _T_1409 ? buf_addr_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1414 = _T_1410 | _T_1411; // @[Mux.scala 27:72] + wire [31:0] _T_1415 = _T_1414 | _T_1412; // @[Mux.scala 27:72] + wire [31:0] _T_1416 = _T_1415 | _T_1413; // @[Mux.scala 27:72] + wire [3:0] _T_1424 = _T_1406 ? buf_byteen_0 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1425 = _T_1407 ? buf_byteen_1 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1426 = _T_1408 ? buf_byteen_2 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1427 = _T_1409 ? buf_byteen_3 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1428 = _T_1424 | _T_1425; // @[Mux.scala 27:72] + wire [3:0] _T_1429 = _T_1428 | _T_1426; // @[Mux.scala 27:72] + wire [3:0] _T_1430 = _T_1429 | _T_1427; // @[Mux.scala 27:72] + wire [7:0] _T_1432 = {_T_1430,4'h0}; // @[Cat.scala 29:58] + wire [7:0] _T_1445 = {4'h0,_T_1430}; // @[Cat.scala 29:58] + wire [7:0] _T_1446 = _T_1416[2] ? _T_1432 : _T_1445; // @[el2_lsu_bus_buffer.scala 381:8] + wire [7:0] obuf_byteen1_in = ibuf_buf_byp ? _T_1405 : _T_1446; // @[el2_lsu_bus_buffer.scala 380:28] wire [63:0] _T_1448 = {store_data_lo_r,32'h0}; // @[Cat.scala 29:58] wire [63:0] _T_1449 = {32'h0,store_data_lo_r}; // @[Cat.scala 29:58] - wire [63:0] _T_1450 = io_lsu_addr_r[2] ? _T_1448 : _T_1449; // @[el2_lsu_bus_buffer.scala 382:44] + wire [63:0] _T_1450 = io_lsu_addr_r[2] ? _T_1448 : _T_1449; // @[el2_lsu_bus_buffer.scala 383:44] wire [31:0] _T_1469 = _T_1023 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1470 = _T_1024 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1471 = _T_1025 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72] @@ -1378,23 +1408,38 @@ module el2_lsu_bus_buffer( wire [31:0] _T_1475 = _T_1474 | _T_1472; // @[Mux.scala 27:72] wire [63:0] _T_1477 = {_T_1475,32'h0}; // @[Cat.scala 29:58] wire [63:0] _T_1490 = {32'h0,_T_1475}; // @[Cat.scala 29:58] - wire [63:0] _T_1491 = _T_1289[2] ? _T_1477 : _T_1490; // @[el2_lsu_bus_buffer.scala 383:8] - wire [63:0] obuf_data0_in = ibuf_buf_byp ? _T_1450 : _T_1491; // @[el2_lsu_bus_buffer.scala 382:26] + wire [63:0] _T_1491 = _T_1289[2] ? _T_1477 : _T_1490; // @[el2_lsu_bus_buffer.scala 384:8] + wire [63:0] obuf_data0_in = ibuf_buf_byp ? _T_1450 : _T_1491; // @[el2_lsu_bus_buffer.scala 383:26] wire [63:0] _T_1493 = {store_data_hi_r,32'h0}; // @[Cat.scala 29:58] wire [63:0] _T_1494 = {32'h0,store_data_hi_r}; // @[Cat.scala 29:58] - wire [63:0] _T_1495 = io_lsu_addr_r[2] ? _T_1493 : _T_1494; // @[el2_lsu_bus_buffer.scala 384:44] - wire [63:0] _T_1522 = {buf_data_0,32'h0}; // @[Cat.scala 29:58] - wire [63:0] _T_1535 = {32'h0,buf_data_0}; // @[Cat.scala 29:58] - wire [63:0] _T_1536 = buf_addr_0[2] ? _T_1522 : _T_1535; // @[el2_lsu_bus_buffer.scala 385:8] - wire [63:0] obuf_data1_in = ibuf_buf_byp ? _T_1495 : _T_1536; // @[el2_lsu_bus_buffer.scala 384:26] - wire _T_1621 = CmdPtr0 != 2'h0; // @[el2_lsu_bus_buffer.scala 391:30] - wire _T_1622 = _T_1621 & found_cmdptr0; // @[el2_lsu_bus_buffer.scala 391:43] - wire _T_1623 = _T_1622 & found_cmdptr1; // @[el2_lsu_bus_buffer.scala 391:59] - wire _T_1637 = _T_1623 & _T_1107; // @[el2_lsu_bus_buffer.scala 391:75] - wire _T_1651 = _T_1637 & _T_2606; // @[el2_lsu_bus_buffer.scala 391:118] - wire _T_1672 = _T_1651 & _T_1128; // @[el2_lsu_bus_buffer.scala 391:161] - wire _T_1690 = _T_1672 & _T_1053; // @[el2_lsu_bus_buffer.scala 392:85] - wire _T_1792 = _T_1204 & _T_1166; // @[el2_lsu_bus_buffer.scala 395:38] + wire [63:0] _T_1495 = io_lsu_addr_r[2] ? _T_1493 : _T_1494; // @[el2_lsu_bus_buffer.scala 385:44] + wire [31:0] _T_1514 = _T_1406 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1515 = _T_1407 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1516 = _T_1408 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1517 = _T_1409 ? buf_data_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1518 = _T_1514 | _T_1515; // @[Mux.scala 27:72] + wire [31:0] _T_1519 = _T_1518 | _T_1516; // @[Mux.scala 27:72] + wire [31:0] _T_1520 = _T_1519 | _T_1517; // @[Mux.scala 27:72] + wire [63:0] _T_1522 = {_T_1520,32'h0}; // @[Cat.scala 29:58] + wire [63:0] _T_1535 = {32'h0,_T_1520}; // @[Cat.scala 29:58] + wire [63:0] _T_1536 = _T_1416[2] ? _T_1522 : _T_1535; // @[el2_lsu_bus_buffer.scala 386:8] + wire [63:0] obuf_data1_in = ibuf_buf_byp ? _T_1495 : _T_1536; // @[el2_lsu_bus_buffer.scala 385:26] + wire _T_1621 = CmdPtr0 != CmdPtr1; // @[el2_lsu_bus_buffer.scala 392:30] + wire _T_1622 = _T_1621 & found_cmdptr0; // @[el2_lsu_bus_buffer.scala 392:43] + wire _T_1623 = _T_1622 & found_cmdptr1; // @[el2_lsu_bus_buffer.scala 392:59] + wire _T_1637 = _T_1623 & _T_1107; // @[el2_lsu_bus_buffer.scala 392:75] + wire [2:0] _T_1642 = _T_1406 ? buf_state_0 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1643 = _T_1407 ? buf_state_1 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1646 = _T_1642 | _T_1643; // @[Mux.scala 27:72] + wire [2:0] _T_1644 = _T_1408 ? buf_state_2 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1647 = _T_1646 | _T_1644; // @[Mux.scala 27:72] + wire [2:0] _T_1645 = _T_1409 ? buf_state_3 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1648 = _T_1647 | _T_1645; // @[Mux.scala 27:72] + wire _T_1650 = _T_1648 == 3'h2; // @[el2_lsu_bus_buffer.scala 392:150] + wire _T_1651 = _T_1637 & _T_1650; // @[el2_lsu_bus_buffer.scala 392:118] + wire _T_1672 = _T_1651 & _T_1128; // @[el2_lsu_bus_buffer.scala 392:161] + wire _T_1690 = _T_1672 & _T_1053; // @[el2_lsu_bus_buffer.scala 393:85] + wire _T_1792 = _T_1204 & _T_1166; // @[el2_lsu_bus_buffer.scala 396:38] reg buf_dualhi_3; // @[Reg.scala 27:20] reg buf_dualhi_2; // @[Reg.scala 27:20] reg buf_dualhi_1; // @[Reg.scala 27:20] @@ -1407,224 +1452,224 @@ module el2_lsu_bus_buffer( wire _T_1809 = _T_1808 | _T_1806; // @[Mux.scala 27:72] wire _T_1807 = _T_1026 & _T_1795[3]; // @[Mux.scala 27:72] wire _T_1810 = _T_1809 | _T_1807; // @[Mux.scala 27:72] - wire _T_1812 = ~_T_1810; // @[el2_lsu_bus_buffer.scala 395:109] - wire _T_1813 = _T_1792 & _T_1812; // @[el2_lsu_bus_buffer.scala 395:107] - wire _T_1833 = _T_1813 & _T_1185; // @[el2_lsu_bus_buffer.scala 395:179] - wire _T_1835 = _T_1690 & _T_1833; // @[el2_lsu_bus_buffer.scala 392:122] - wire _T_1836 = ibuf_buf_byp & ldst_samedw_r; // @[el2_lsu_bus_buffer.scala 396:19] - wire _T_1837 = _T_1836 & io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 396:35] - wire obuf_merge_en = _T_1835 | _T_1837; // @[el2_lsu_bus_buffer.scala 395:253] - wire _T_1539 = obuf_merge_en & obuf_byteen1_in[0]; // @[el2_lsu_bus_buffer.scala 386:80] - wire _T_1540 = obuf_byteen0_in[0] | _T_1539; // @[el2_lsu_bus_buffer.scala 386:63] - wire _T_1543 = obuf_merge_en & obuf_byteen1_in[1]; // @[el2_lsu_bus_buffer.scala 386:80] - wire _T_1544 = obuf_byteen0_in[1] | _T_1543; // @[el2_lsu_bus_buffer.scala 386:63] - wire _T_1547 = obuf_merge_en & obuf_byteen1_in[2]; // @[el2_lsu_bus_buffer.scala 386:80] - wire _T_1548 = obuf_byteen0_in[2] | _T_1547; // @[el2_lsu_bus_buffer.scala 386:63] - wire _T_1551 = obuf_merge_en & obuf_byteen1_in[3]; // @[el2_lsu_bus_buffer.scala 386:80] - wire _T_1552 = obuf_byteen0_in[3] | _T_1551; // @[el2_lsu_bus_buffer.scala 386:63] - wire _T_1555 = obuf_merge_en & obuf_byteen1_in[4]; // @[el2_lsu_bus_buffer.scala 386:80] - wire _T_1556 = obuf_byteen0_in[4] | _T_1555; // @[el2_lsu_bus_buffer.scala 386:63] - wire _T_1559 = obuf_merge_en & obuf_byteen1_in[5]; // @[el2_lsu_bus_buffer.scala 386:80] - wire _T_1560 = obuf_byteen0_in[5] | _T_1559; // @[el2_lsu_bus_buffer.scala 386:63] - wire _T_1563 = obuf_merge_en & obuf_byteen1_in[6]; // @[el2_lsu_bus_buffer.scala 386:80] - wire _T_1564 = obuf_byteen0_in[6] | _T_1563; // @[el2_lsu_bus_buffer.scala 386:63] - wire _T_1567 = obuf_merge_en & obuf_byteen1_in[7]; // @[el2_lsu_bus_buffer.scala 386:80] - wire _T_1568 = obuf_byteen0_in[7] | _T_1567; // @[el2_lsu_bus_buffer.scala 386:63] + wire _T_1812 = ~_T_1810; // @[el2_lsu_bus_buffer.scala 396:109] + wire _T_1813 = _T_1792 & _T_1812; // @[el2_lsu_bus_buffer.scala 396:107] + wire _T_1833 = _T_1813 & _T_1185; // @[el2_lsu_bus_buffer.scala 396:179] + wire _T_1835 = _T_1690 & _T_1833; // @[el2_lsu_bus_buffer.scala 393:122] + wire _T_1836 = ibuf_buf_byp & ldst_samedw_r; // @[el2_lsu_bus_buffer.scala 397:19] + wire _T_1837 = _T_1836 & io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 397:35] + wire obuf_merge_en = _T_1835 | _T_1837; // @[el2_lsu_bus_buffer.scala 396:253] + wire _T_1539 = obuf_merge_en & obuf_byteen1_in[0]; // @[el2_lsu_bus_buffer.scala 387:80] + wire _T_1540 = obuf_byteen0_in[0] | _T_1539; // @[el2_lsu_bus_buffer.scala 387:63] + wire _T_1543 = obuf_merge_en & obuf_byteen1_in[1]; // @[el2_lsu_bus_buffer.scala 387:80] + wire _T_1544 = obuf_byteen0_in[1] | _T_1543; // @[el2_lsu_bus_buffer.scala 387:63] + wire _T_1547 = obuf_merge_en & obuf_byteen1_in[2]; // @[el2_lsu_bus_buffer.scala 387:80] + wire _T_1548 = obuf_byteen0_in[2] | _T_1547; // @[el2_lsu_bus_buffer.scala 387:63] + wire _T_1551 = obuf_merge_en & obuf_byteen1_in[3]; // @[el2_lsu_bus_buffer.scala 387:80] + wire _T_1552 = obuf_byteen0_in[3] | _T_1551; // @[el2_lsu_bus_buffer.scala 387:63] + wire _T_1555 = obuf_merge_en & obuf_byteen1_in[4]; // @[el2_lsu_bus_buffer.scala 387:80] + wire _T_1556 = obuf_byteen0_in[4] | _T_1555; // @[el2_lsu_bus_buffer.scala 387:63] + wire _T_1559 = obuf_merge_en & obuf_byteen1_in[5]; // @[el2_lsu_bus_buffer.scala 387:80] + wire _T_1560 = obuf_byteen0_in[5] | _T_1559; // @[el2_lsu_bus_buffer.scala 387:63] + wire _T_1563 = obuf_merge_en & obuf_byteen1_in[6]; // @[el2_lsu_bus_buffer.scala 387:80] + wire _T_1564 = obuf_byteen0_in[6] | _T_1563; // @[el2_lsu_bus_buffer.scala 387:63] + wire _T_1567 = obuf_merge_en & obuf_byteen1_in[7]; // @[el2_lsu_bus_buffer.scala 387:80] + wire _T_1568 = obuf_byteen0_in[7] | _T_1567; // @[el2_lsu_bus_buffer.scala 387:63] wire [7:0] obuf_byteen_in = {_T_1568,_T_1564,_T_1560,_T_1556,_T_1552,_T_1548,_T_1544,_T_1540}; // @[Cat.scala 29:58] - wire [7:0] _T_1579 = _T_1539 ? obuf_data1_in[7:0] : obuf_data0_in[7:0]; // @[el2_lsu_bus_buffer.scala 387:44] - wire [7:0] _T_1584 = _T_1543 ? obuf_data1_in[15:8] : obuf_data0_in[15:8]; // @[el2_lsu_bus_buffer.scala 387:44] - wire [7:0] _T_1589 = _T_1547 ? obuf_data1_in[23:16] : obuf_data0_in[23:16]; // @[el2_lsu_bus_buffer.scala 387:44] - wire [7:0] _T_1594 = _T_1551 ? obuf_data1_in[31:24] : obuf_data0_in[31:24]; // @[el2_lsu_bus_buffer.scala 387:44] - wire [7:0] _T_1599 = _T_1555 ? obuf_data1_in[39:32] : obuf_data0_in[39:32]; // @[el2_lsu_bus_buffer.scala 387:44] - wire [7:0] _T_1604 = _T_1559 ? obuf_data1_in[47:40] : obuf_data0_in[47:40]; // @[el2_lsu_bus_buffer.scala 387:44] - wire [7:0] _T_1609 = _T_1563 ? obuf_data1_in[55:48] : obuf_data0_in[55:48]; // @[el2_lsu_bus_buffer.scala 387:44] - wire [7:0] _T_1614 = _T_1567 ? obuf_data1_in[63:56] : obuf_data0_in[63:56]; // @[el2_lsu_bus_buffer.scala 387:44] + wire [7:0] _T_1579 = _T_1539 ? obuf_data1_in[7:0] : obuf_data0_in[7:0]; // @[el2_lsu_bus_buffer.scala 388:44] + wire [7:0] _T_1584 = _T_1543 ? obuf_data1_in[15:8] : obuf_data0_in[15:8]; // @[el2_lsu_bus_buffer.scala 388:44] + wire [7:0] _T_1589 = _T_1547 ? obuf_data1_in[23:16] : obuf_data0_in[23:16]; // @[el2_lsu_bus_buffer.scala 388:44] + wire [7:0] _T_1594 = _T_1551 ? obuf_data1_in[31:24] : obuf_data0_in[31:24]; // @[el2_lsu_bus_buffer.scala 388:44] + wire [7:0] _T_1599 = _T_1555 ? obuf_data1_in[39:32] : obuf_data0_in[39:32]; // @[el2_lsu_bus_buffer.scala 388:44] + wire [7:0] _T_1604 = _T_1559 ? obuf_data1_in[47:40] : obuf_data0_in[47:40]; // @[el2_lsu_bus_buffer.scala 388:44] + wire [7:0] _T_1609 = _T_1563 ? obuf_data1_in[55:48] : obuf_data0_in[55:48]; // @[el2_lsu_bus_buffer.scala 388:44] + wire [7:0] _T_1614 = _T_1567 ? obuf_data1_in[63:56] : obuf_data0_in[63:56]; // @[el2_lsu_bus_buffer.scala 388:44] wire [55:0] _T_1620 = {_T_1614,_T_1609,_T_1604,_T_1599,_T_1594,_T_1589,_T_1584}; // @[Cat.scala 29:58] - wire _T_1839 = obuf_wr_en | obuf_valid; // @[el2_lsu_bus_buffer.scala 399:58] - wire _T_1840 = ~obuf_rst; // @[el2_lsu_bus_buffer.scala 399:93] + wire _T_1839 = obuf_wr_en | obuf_valid; // @[el2_lsu_bus_buffer.scala 400:58] + wire _T_1840 = ~obuf_rst; // @[el2_lsu_bus_buffer.scala 400:93] reg [1:0] obuf_sz; // @[Reg.scala 27:20] reg [7:0] obuf_byteen; // @[Reg.scala 27:20] reg [63:0] obuf_data; // @[el2_lib.scala 514:16] - wire _T_1853 = buf_state_0 == 3'h0; // @[el2_lsu_bus_buffer.scala 417:65] - wire _T_1854 = ibuf_tag == 2'h0; // @[el2_lsu_bus_buffer.scala 418:30] - wire _T_1855 = ibuf_valid & _T_1854; // @[el2_lsu_bus_buffer.scala 418:19] - wire _T_1856 = WrPtr0_r == 2'h0; // @[el2_lsu_bus_buffer.scala 419:18] - wire _T_1857 = WrPtr1_r == 2'h0; // @[el2_lsu_bus_buffer.scala 419:57] - wire _T_1858 = io_ldst_dual_r & _T_1857; // @[el2_lsu_bus_buffer.scala 419:45] - wire _T_1859 = _T_1856 | _T_1858; // @[el2_lsu_bus_buffer.scala 419:27] - wire _T_1860 = io_lsu_busreq_r & _T_1859; // @[el2_lsu_bus_buffer.scala 418:58] - wire _T_1861 = _T_1855 | _T_1860; // @[el2_lsu_bus_buffer.scala 418:39] - wire _T_1862 = ~_T_1861; // @[el2_lsu_bus_buffer.scala 418:5] - wire _T_1863 = _T_1853 & _T_1862; // @[el2_lsu_bus_buffer.scala 417:76] - wire _T_1864 = buf_state_1 == 3'h0; // @[el2_lsu_bus_buffer.scala 417:65] - wire _T_1865 = ibuf_tag == 2'h1; // @[el2_lsu_bus_buffer.scala 418:30] - wire _T_1866 = ibuf_valid & _T_1865; // @[el2_lsu_bus_buffer.scala 418:19] - wire _T_1867 = WrPtr0_r == 2'h1; // @[el2_lsu_bus_buffer.scala 419:18] - wire _T_1868 = WrPtr1_r == 2'h1; // @[el2_lsu_bus_buffer.scala 419:57] - wire _T_1869 = io_ldst_dual_r & _T_1868; // @[el2_lsu_bus_buffer.scala 419:45] - wire _T_1870 = _T_1867 | _T_1869; // @[el2_lsu_bus_buffer.scala 419:27] - wire _T_1871 = io_lsu_busreq_r & _T_1870; // @[el2_lsu_bus_buffer.scala 418:58] - wire _T_1872 = _T_1866 | _T_1871; // @[el2_lsu_bus_buffer.scala 418:39] - wire _T_1873 = ~_T_1872; // @[el2_lsu_bus_buffer.scala 418:5] - wire _T_1874 = _T_1864 & _T_1873; // @[el2_lsu_bus_buffer.scala 417:76] - wire _T_1875 = buf_state_2 == 3'h0; // @[el2_lsu_bus_buffer.scala 417:65] - wire _T_1876 = ibuf_tag == 2'h2; // @[el2_lsu_bus_buffer.scala 418:30] - wire _T_1877 = ibuf_valid & _T_1876; // @[el2_lsu_bus_buffer.scala 418:19] - wire _T_1878 = WrPtr0_r == 2'h2; // @[el2_lsu_bus_buffer.scala 419:18] - wire _T_1879 = WrPtr1_r == 2'h2; // @[el2_lsu_bus_buffer.scala 419:57] - wire _T_1880 = io_ldst_dual_r & _T_1879; // @[el2_lsu_bus_buffer.scala 419:45] - wire _T_1881 = _T_1878 | _T_1880; // @[el2_lsu_bus_buffer.scala 419:27] - wire _T_1882 = io_lsu_busreq_r & _T_1881; // @[el2_lsu_bus_buffer.scala 418:58] - wire _T_1883 = _T_1877 | _T_1882; // @[el2_lsu_bus_buffer.scala 418:39] - wire _T_1884 = ~_T_1883; // @[el2_lsu_bus_buffer.scala 418:5] - wire _T_1885 = _T_1875 & _T_1884; // @[el2_lsu_bus_buffer.scala 417:76] - wire _T_1886 = buf_state_3 == 3'h0; // @[el2_lsu_bus_buffer.scala 417:65] - wire _T_1887 = ibuf_tag == 2'h3; // @[el2_lsu_bus_buffer.scala 418:30] - wire _T_1889 = WrPtr0_r == 2'h3; // @[el2_lsu_bus_buffer.scala 419:18] - wire _T_1890 = WrPtr1_r == 2'h3; // @[el2_lsu_bus_buffer.scala 419:57] + wire _T_1853 = buf_state_0 == 3'h0; // @[el2_lsu_bus_buffer.scala 418:65] + wire _T_1854 = ibuf_tag == 2'h0; // @[el2_lsu_bus_buffer.scala 419:30] + wire _T_1855 = ibuf_valid & _T_1854; // @[el2_lsu_bus_buffer.scala 419:19] + wire _T_1856 = WrPtr0_r == 2'h0; // @[el2_lsu_bus_buffer.scala 420:18] + wire _T_1857 = WrPtr1_r == 2'h0; // @[el2_lsu_bus_buffer.scala 420:57] + wire _T_1858 = io_ldst_dual_r & _T_1857; // @[el2_lsu_bus_buffer.scala 420:45] + wire _T_1859 = _T_1856 | _T_1858; // @[el2_lsu_bus_buffer.scala 420:27] + wire _T_1860 = io_lsu_busreq_r & _T_1859; // @[el2_lsu_bus_buffer.scala 419:58] + wire _T_1861 = _T_1855 | _T_1860; // @[el2_lsu_bus_buffer.scala 419:39] + wire _T_1862 = ~_T_1861; // @[el2_lsu_bus_buffer.scala 419:5] + wire _T_1863 = _T_1853 & _T_1862; // @[el2_lsu_bus_buffer.scala 418:76] + wire _T_1864 = buf_state_1 == 3'h0; // @[el2_lsu_bus_buffer.scala 418:65] + wire _T_1865 = ibuf_tag == 2'h1; // @[el2_lsu_bus_buffer.scala 419:30] + wire _T_1866 = ibuf_valid & _T_1865; // @[el2_lsu_bus_buffer.scala 419:19] + wire _T_1867 = WrPtr0_r == 2'h1; // @[el2_lsu_bus_buffer.scala 420:18] + wire _T_1868 = WrPtr1_r == 2'h1; // @[el2_lsu_bus_buffer.scala 420:57] + wire _T_1869 = io_ldst_dual_r & _T_1868; // @[el2_lsu_bus_buffer.scala 420:45] + wire _T_1870 = _T_1867 | _T_1869; // @[el2_lsu_bus_buffer.scala 420:27] + wire _T_1871 = io_lsu_busreq_r & _T_1870; // @[el2_lsu_bus_buffer.scala 419:58] + wire _T_1872 = _T_1866 | _T_1871; // @[el2_lsu_bus_buffer.scala 419:39] + wire _T_1873 = ~_T_1872; // @[el2_lsu_bus_buffer.scala 419:5] + wire _T_1874 = _T_1864 & _T_1873; // @[el2_lsu_bus_buffer.scala 418:76] + wire _T_1875 = buf_state_2 == 3'h0; // @[el2_lsu_bus_buffer.scala 418:65] + wire _T_1876 = ibuf_tag == 2'h2; // @[el2_lsu_bus_buffer.scala 419:30] + wire _T_1877 = ibuf_valid & _T_1876; // @[el2_lsu_bus_buffer.scala 419:19] + wire _T_1878 = WrPtr0_r == 2'h2; // @[el2_lsu_bus_buffer.scala 420:18] + wire _T_1879 = WrPtr1_r == 2'h2; // @[el2_lsu_bus_buffer.scala 420:57] + wire _T_1880 = io_ldst_dual_r & _T_1879; // @[el2_lsu_bus_buffer.scala 420:45] + wire _T_1881 = _T_1878 | _T_1880; // @[el2_lsu_bus_buffer.scala 420:27] + wire _T_1882 = io_lsu_busreq_r & _T_1881; // @[el2_lsu_bus_buffer.scala 419:58] + wire _T_1883 = _T_1877 | _T_1882; // @[el2_lsu_bus_buffer.scala 419:39] + wire _T_1884 = ~_T_1883; // @[el2_lsu_bus_buffer.scala 419:5] + wire _T_1885 = _T_1875 & _T_1884; // @[el2_lsu_bus_buffer.scala 418:76] + wire _T_1886 = buf_state_3 == 3'h0; // @[el2_lsu_bus_buffer.scala 418:65] + wire _T_1887 = ibuf_tag == 2'h3; // @[el2_lsu_bus_buffer.scala 419:30] + wire _T_1889 = WrPtr0_r == 2'h3; // @[el2_lsu_bus_buffer.scala 420:18] + wire _T_1890 = WrPtr1_r == 2'h3; // @[el2_lsu_bus_buffer.scala 420:57] wire [1:0] _T_1898 = _T_1885 ? 2'h2 : 2'h3; // @[Mux.scala 98:16] wire [1:0] _T_1899 = _T_1874 ? 2'h1 : _T_1898; // @[Mux.scala 98:16] wire [1:0] WrPtr0_m = _T_1863 ? 2'h0 : _T_1899; // @[Mux.scala 98:16] - wire _T_1904 = WrPtr0_m == 2'h0; // @[el2_lsu_bus_buffer.scala 424:33] - wire _T_1905 = io_lsu_busreq_m & _T_1904; // @[el2_lsu_bus_buffer.scala 424:22] - wire _T_1906 = _T_1855 | _T_1905; // @[el2_lsu_bus_buffer.scala 423:112] - wire _T_1912 = _T_1906 | _T_1860; // @[el2_lsu_bus_buffer.scala 424:42] - wire _T_1913 = ~_T_1912; // @[el2_lsu_bus_buffer.scala 423:78] - wire _T_1914 = _T_1853 & _T_1913; // @[el2_lsu_bus_buffer.scala 423:76] - wire _T_1918 = WrPtr0_m == 2'h1; // @[el2_lsu_bus_buffer.scala 424:33] - wire _T_1919 = io_lsu_busreq_m & _T_1918; // @[el2_lsu_bus_buffer.scala 424:22] - wire _T_1920 = _T_1866 | _T_1919; // @[el2_lsu_bus_buffer.scala 423:112] - wire _T_1926 = _T_1920 | _T_1871; // @[el2_lsu_bus_buffer.scala 424:42] - wire _T_1927 = ~_T_1926; // @[el2_lsu_bus_buffer.scala 423:78] - wire _T_1928 = _T_1864 & _T_1927; // @[el2_lsu_bus_buffer.scala 423:76] - wire _T_1932 = WrPtr0_m == 2'h2; // @[el2_lsu_bus_buffer.scala 424:33] - wire _T_1933 = io_lsu_busreq_m & _T_1932; // @[el2_lsu_bus_buffer.scala 424:22] - wire _T_1934 = _T_1877 | _T_1933; // @[el2_lsu_bus_buffer.scala 423:112] - wire _T_1940 = _T_1934 | _T_1882; // @[el2_lsu_bus_buffer.scala 424:42] - wire _T_1941 = ~_T_1940; // @[el2_lsu_bus_buffer.scala 423:78] - wire _T_1942 = _T_1875 & _T_1941; // @[el2_lsu_bus_buffer.scala 423:76] - reg [3:0] buf_rspageQ_0; // @[el2_lsu_bus_buffer.scala 554:63] - wire _T_2746 = buf_state_3 == 3'h5; // @[el2_lsu_bus_buffer.scala 467:102] - wire _T_2747 = buf_rspageQ_0[3] & _T_2746; // @[el2_lsu_bus_buffer.scala 467:87] - wire _T_2743 = buf_state_2 == 3'h5; // @[el2_lsu_bus_buffer.scala 467:102] - wire _T_2744 = buf_rspageQ_0[2] & _T_2743; // @[el2_lsu_bus_buffer.scala 467:87] - wire _T_2740 = buf_state_1 == 3'h5; // @[el2_lsu_bus_buffer.scala 467:102] - wire _T_2741 = buf_rspageQ_0[1] & _T_2740; // @[el2_lsu_bus_buffer.scala 467:87] - wire _T_2737 = buf_state_0 == 3'h5; // @[el2_lsu_bus_buffer.scala 467:102] - wire _T_2738 = buf_rspageQ_0[0] & _T_2737; // @[el2_lsu_bus_buffer.scala 467:87] + wire _T_1904 = WrPtr0_m == 2'h0; // @[el2_lsu_bus_buffer.scala 425:33] + wire _T_1905 = io_lsu_busreq_m & _T_1904; // @[el2_lsu_bus_buffer.scala 425:22] + wire _T_1906 = _T_1855 | _T_1905; // @[el2_lsu_bus_buffer.scala 424:112] + wire _T_1912 = _T_1906 | _T_1860; // @[el2_lsu_bus_buffer.scala 425:42] + wire _T_1913 = ~_T_1912; // @[el2_lsu_bus_buffer.scala 424:78] + wire _T_1914 = _T_1853 & _T_1913; // @[el2_lsu_bus_buffer.scala 424:76] + wire _T_1918 = WrPtr0_m == 2'h1; // @[el2_lsu_bus_buffer.scala 425:33] + wire _T_1919 = io_lsu_busreq_m & _T_1918; // @[el2_lsu_bus_buffer.scala 425:22] + wire _T_1920 = _T_1866 | _T_1919; // @[el2_lsu_bus_buffer.scala 424:112] + wire _T_1926 = _T_1920 | _T_1871; // @[el2_lsu_bus_buffer.scala 425:42] + wire _T_1927 = ~_T_1926; // @[el2_lsu_bus_buffer.scala 424:78] + wire _T_1928 = _T_1864 & _T_1927; // @[el2_lsu_bus_buffer.scala 424:76] + wire _T_1932 = WrPtr0_m == 2'h2; // @[el2_lsu_bus_buffer.scala 425:33] + wire _T_1933 = io_lsu_busreq_m & _T_1932; // @[el2_lsu_bus_buffer.scala 425:22] + wire _T_1934 = _T_1877 | _T_1933; // @[el2_lsu_bus_buffer.scala 424:112] + wire _T_1940 = _T_1934 | _T_1882; // @[el2_lsu_bus_buffer.scala 425:42] + wire _T_1941 = ~_T_1940; // @[el2_lsu_bus_buffer.scala 424:78] + wire _T_1942 = _T_1875 & _T_1941; // @[el2_lsu_bus_buffer.scala 424:76] + reg [3:0] buf_rspageQ_0; // @[el2_lsu_bus_buffer.scala 555:63] + wire _T_2746 = buf_state_3 == 3'h5; // @[el2_lsu_bus_buffer.scala 468:102] + wire _T_2747 = buf_rspageQ_0[3] & _T_2746; // @[el2_lsu_bus_buffer.scala 468:87] + wire _T_2743 = buf_state_2 == 3'h5; // @[el2_lsu_bus_buffer.scala 468:102] + wire _T_2744 = buf_rspageQ_0[2] & _T_2743; // @[el2_lsu_bus_buffer.scala 468:87] + wire _T_2740 = buf_state_1 == 3'h5; // @[el2_lsu_bus_buffer.scala 468:102] + wire _T_2741 = buf_rspageQ_0[1] & _T_2740; // @[el2_lsu_bus_buffer.scala 468:87] + wire _T_2737 = buf_state_0 == 3'h5; // @[el2_lsu_bus_buffer.scala 468:102] + wire _T_2738 = buf_rspageQ_0[0] & _T_2737; // @[el2_lsu_bus_buffer.scala 468:87] wire [3:0] buf_rsp_pickage_0 = {_T_2747,_T_2744,_T_2741,_T_2738}; // @[Cat.scala 29:58] - wire _T_2033 = |buf_rsp_pickage_0; // @[el2_lsu_bus_buffer.scala 435:65] - wire _T_2034 = ~_T_2033; // @[el2_lsu_bus_buffer.scala 435:44] - wire _T_2036 = _T_2034 & _T_2737; // @[el2_lsu_bus_buffer.scala 435:70] - reg [3:0] buf_rspageQ_1; // @[el2_lsu_bus_buffer.scala 554:63] - wire _T_2762 = buf_rspageQ_1[3] & _T_2746; // @[el2_lsu_bus_buffer.scala 467:87] - wire _T_2759 = buf_rspageQ_1[2] & _T_2743; // @[el2_lsu_bus_buffer.scala 467:87] - wire _T_2756 = buf_rspageQ_1[1] & _T_2740; // @[el2_lsu_bus_buffer.scala 467:87] - wire _T_2753 = buf_rspageQ_1[0] & _T_2737; // @[el2_lsu_bus_buffer.scala 467:87] + wire _T_2033 = |buf_rsp_pickage_0; // @[el2_lsu_bus_buffer.scala 436:65] + wire _T_2034 = ~_T_2033; // @[el2_lsu_bus_buffer.scala 436:44] + wire _T_2036 = _T_2034 & _T_2737; // @[el2_lsu_bus_buffer.scala 436:70] + reg [3:0] buf_rspageQ_1; // @[el2_lsu_bus_buffer.scala 555:63] + wire _T_2762 = buf_rspageQ_1[3] & _T_2746; // @[el2_lsu_bus_buffer.scala 468:87] + wire _T_2759 = buf_rspageQ_1[2] & _T_2743; // @[el2_lsu_bus_buffer.scala 468:87] + wire _T_2756 = buf_rspageQ_1[1] & _T_2740; // @[el2_lsu_bus_buffer.scala 468:87] + wire _T_2753 = buf_rspageQ_1[0] & _T_2737; // @[el2_lsu_bus_buffer.scala 468:87] wire [3:0] buf_rsp_pickage_1 = {_T_2762,_T_2759,_T_2756,_T_2753}; // @[Cat.scala 29:58] - wire _T_2037 = |buf_rsp_pickage_1; // @[el2_lsu_bus_buffer.scala 435:65] - wire _T_2038 = ~_T_2037; // @[el2_lsu_bus_buffer.scala 435:44] - wire _T_2040 = _T_2038 & _T_2740; // @[el2_lsu_bus_buffer.scala 435:70] - reg [3:0] buf_rspageQ_2; // @[el2_lsu_bus_buffer.scala 554:63] - wire _T_2777 = buf_rspageQ_2[3] & _T_2746; // @[el2_lsu_bus_buffer.scala 467:87] - wire _T_2774 = buf_rspageQ_2[2] & _T_2743; // @[el2_lsu_bus_buffer.scala 467:87] - wire _T_2771 = buf_rspageQ_2[1] & _T_2740; // @[el2_lsu_bus_buffer.scala 467:87] - wire _T_2768 = buf_rspageQ_2[0] & _T_2737; // @[el2_lsu_bus_buffer.scala 467:87] + wire _T_2037 = |buf_rsp_pickage_1; // @[el2_lsu_bus_buffer.scala 436:65] + wire _T_2038 = ~_T_2037; // @[el2_lsu_bus_buffer.scala 436:44] + wire _T_2040 = _T_2038 & _T_2740; // @[el2_lsu_bus_buffer.scala 436:70] + reg [3:0] buf_rspageQ_2; // @[el2_lsu_bus_buffer.scala 555:63] + wire _T_2777 = buf_rspageQ_2[3] & _T_2746; // @[el2_lsu_bus_buffer.scala 468:87] + wire _T_2774 = buf_rspageQ_2[2] & _T_2743; // @[el2_lsu_bus_buffer.scala 468:87] + wire _T_2771 = buf_rspageQ_2[1] & _T_2740; // @[el2_lsu_bus_buffer.scala 468:87] + wire _T_2768 = buf_rspageQ_2[0] & _T_2737; // @[el2_lsu_bus_buffer.scala 468:87] wire [3:0] buf_rsp_pickage_2 = {_T_2777,_T_2774,_T_2771,_T_2768}; // @[Cat.scala 29:58] - wire _T_2041 = |buf_rsp_pickage_2; // @[el2_lsu_bus_buffer.scala 435:65] - wire _T_2042 = ~_T_2041; // @[el2_lsu_bus_buffer.scala 435:44] - wire _T_2044 = _T_2042 & _T_2743; // @[el2_lsu_bus_buffer.scala 435:70] - reg [3:0] buf_rspageQ_3; // @[el2_lsu_bus_buffer.scala 554:63] - wire _T_2792 = buf_rspageQ_3[3] & _T_2746; // @[el2_lsu_bus_buffer.scala 467:87] - wire _T_2789 = buf_rspageQ_3[2] & _T_2743; // @[el2_lsu_bus_buffer.scala 467:87] - wire _T_2786 = buf_rspageQ_3[1] & _T_2740; // @[el2_lsu_bus_buffer.scala 467:87] - wire _T_2783 = buf_rspageQ_3[0] & _T_2737; // @[el2_lsu_bus_buffer.scala 467:87] + wire _T_2041 = |buf_rsp_pickage_2; // @[el2_lsu_bus_buffer.scala 436:65] + wire _T_2042 = ~_T_2041; // @[el2_lsu_bus_buffer.scala 436:44] + wire _T_2044 = _T_2042 & _T_2743; // @[el2_lsu_bus_buffer.scala 436:70] + reg [3:0] buf_rspageQ_3; // @[el2_lsu_bus_buffer.scala 555:63] + wire _T_2792 = buf_rspageQ_3[3] & _T_2746; // @[el2_lsu_bus_buffer.scala 468:87] + wire _T_2789 = buf_rspageQ_3[2] & _T_2743; // @[el2_lsu_bus_buffer.scala 468:87] + wire _T_2786 = buf_rspageQ_3[1] & _T_2740; // @[el2_lsu_bus_buffer.scala 468:87] + wire _T_2783 = buf_rspageQ_3[0] & _T_2737; // @[el2_lsu_bus_buffer.scala 468:87] wire [3:0] buf_rsp_pickage_3 = {_T_2792,_T_2789,_T_2786,_T_2783}; // @[Cat.scala 29:58] - wire _T_2045 = |buf_rsp_pickage_3; // @[el2_lsu_bus_buffer.scala 435:65] - wire _T_2046 = ~_T_2045; // @[el2_lsu_bus_buffer.scala 435:44] - wire _T_2048 = _T_2046 & _T_2746; // @[el2_lsu_bus_buffer.scala 435:70] + wire _T_2045 = |buf_rsp_pickage_3; // @[el2_lsu_bus_buffer.scala 436:65] + wire _T_2046 = ~_T_2045; // @[el2_lsu_bus_buffer.scala 436:44] + wire _T_2048 = _T_2046 & _T_2746; // @[el2_lsu_bus_buffer.scala 436:70] wire [7:0] _T_2104 = {4'h0,_T_2048,_T_2044,_T_2040,_T_2036}; // @[Cat.scala 29:58] - wire _T_2107 = _T_2104[4] | _T_2104[5]; // @[el2_lsu_bus_buffer.scala 439:42] - wire _T_2109 = _T_2107 | _T_2104[6]; // @[el2_lsu_bus_buffer.scala 439:48] - wire _T_2111 = _T_2109 | _T_2104[7]; // @[el2_lsu_bus_buffer.scala 439:54] - wire _T_2114 = _T_2104[2] | _T_2104[3]; // @[el2_lsu_bus_buffer.scala 439:67] - wire _T_2116 = _T_2114 | _T_2104[6]; // @[el2_lsu_bus_buffer.scala 439:73] - wire _T_2118 = _T_2116 | _T_2104[7]; // @[el2_lsu_bus_buffer.scala 439:79] - wire _T_2121 = _T_2104[1] | _T_2104[3]; // @[el2_lsu_bus_buffer.scala 439:92] - wire _T_2123 = _T_2121 | _T_2104[5]; // @[el2_lsu_bus_buffer.scala 439:98] - wire _T_2125 = _T_2123 | _T_2104[7]; // @[el2_lsu_bus_buffer.scala 439:104] + wire _T_2107 = _T_2104[4] | _T_2104[5]; // @[el2_lsu_bus_buffer.scala 440:42] + wire _T_2109 = _T_2107 | _T_2104[6]; // @[el2_lsu_bus_buffer.scala 440:48] + wire _T_2111 = _T_2109 | _T_2104[7]; // @[el2_lsu_bus_buffer.scala 440:54] + wire _T_2114 = _T_2104[2] | _T_2104[3]; // @[el2_lsu_bus_buffer.scala 440:67] + wire _T_2116 = _T_2114 | _T_2104[6]; // @[el2_lsu_bus_buffer.scala 440:73] + wire _T_2118 = _T_2116 | _T_2104[7]; // @[el2_lsu_bus_buffer.scala 440:79] + wire _T_2121 = _T_2104[1] | _T_2104[3]; // @[el2_lsu_bus_buffer.scala 440:92] + wire _T_2123 = _T_2121 | _T_2104[5]; // @[el2_lsu_bus_buffer.scala 440:98] + wire _T_2125 = _T_2123 | _T_2104[7]; // @[el2_lsu_bus_buffer.scala 440:104] wire [2:0] _T_2127 = {_T_2111,_T_2118,_T_2125}; // @[Cat.scala 29:58] - wire _T_3532 = ibuf_byp | io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 497:77] - wire _T_3533 = ~ibuf_merge_en; // @[el2_lsu_bus_buffer.scala 497:97] - wire _T_3534 = _T_3532 & _T_3533; // @[el2_lsu_bus_buffer.scala 497:95] - wire _T_3535 = 2'h0 == WrPtr0_r; // @[el2_lsu_bus_buffer.scala 497:117] - wire _T_3536 = _T_3534 & _T_3535; // @[el2_lsu_bus_buffer.scala 497:112] - wire _T_3537 = ibuf_byp & io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 497:144] - wire _T_3538 = 2'h0 == WrPtr1_r; // @[el2_lsu_bus_buffer.scala 497:166] - wire _T_3539 = _T_3537 & _T_3538; // @[el2_lsu_bus_buffer.scala 497:161] - wire _T_3540 = _T_3536 | _T_3539; // @[el2_lsu_bus_buffer.scala 497:132] - wire _T_3541 = _T_853 & _T_3540; // @[el2_lsu_bus_buffer.scala 497:63] - wire _T_3542 = 2'h0 == ibuf_tag; // @[el2_lsu_bus_buffer.scala 497:206] - wire _T_3543 = ibuf_drain_vld & _T_3542; // @[el2_lsu_bus_buffer.scala 497:201] - wire _T_3544 = _T_3541 | _T_3543; // @[el2_lsu_bus_buffer.scala 497:183] - wire _T_3554 = io_lsu_bus_clk_en | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 504:46] + wire _T_3532 = ibuf_byp | io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 498:77] + wire _T_3533 = ~ibuf_merge_en; // @[el2_lsu_bus_buffer.scala 498:97] + wire _T_3534 = _T_3532 & _T_3533; // @[el2_lsu_bus_buffer.scala 498:95] + wire _T_3535 = 2'h0 == WrPtr0_r; // @[el2_lsu_bus_buffer.scala 498:117] + wire _T_3536 = _T_3534 & _T_3535; // @[el2_lsu_bus_buffer.scala 498:112] + wire _T_3537 = ibuf_byp & io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 498:144] + wire _T_3538 = 2'h0 == WrPtr1_r; // @[el2_lsu_bus_buffer.scala 498:166] + wire _T_3539 = _T_3537 & _T_3538; // @[el2_lsu_bus_buffer.scala 498:161] + wire _T_3540 = _T_3536 | _T_3539; // @[el2_lsu_bus_buffer.scala 498:132] + wire _T_3541 = _T_853 & _T_3540; // @[el2_lsu_bus_buffer.scala 498:63] + wire _T_3542 = 2'h0 == ibuf_tag; // @[el2_lsu_bus_buffer.scala 498:206] + wire _T_3543 = ibuf_drain_vld & _T_3542; // @[el2_lsu_bus_buffer.scala 498:201] + wire _T_3544 = _T_3541 | _T_3543; // @[el2_lsu_bus_buffer.scala 498:183] + wire _T_3554 = io_lsu_bus_clk_en | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 505:46] wire _T_3589 = 3'h3 == buf_state_0; // @[Conditional.scala 37:30] - wire bus_rsp_write = io_lsu_axi_bvalid & io_lsu_axi_bready; // @[el2_lsu_bus_buffer.scala 614:38] - wire _T_3634 = io_lsu_axi_bid == 3'h0; // @[el2_lsu_bus_buffer.scala 522:73] - wire _T_3635 = bus_rsp_write & _T_3634; // @[el2_lsu_bus_buffer.scala 522:52] - wire _T_3636 = io_lsu_axi_rid == 3'h0; // @[el2_lsu_bus_buffer.scala 523:46] + wire bus_rsp_write = io_lsu_axi_bvalid & io_lsu_axi_bready; // @[el2_lsu_bus_buffer.scala 615:38] + wire _T_3634 = io_lsu_axi_bid == 3'h0; // @[el2_lsu_bus_buffer.scala 523:73] + wire _T_3635 = bus_rsp_write & _T_3634; // @[el2_lsu_bus_buffer.scala 523:52] + wire _T_3636 = io_lsu_axi_rid == 3'h0; // @[el2_lsu_bus_buffer.scala 524:46] reg _T_4307; // @[Reg.scala 27:20] reg _T_4305; // @[Reg.scala 27:20] reg _T_4303; // @[Reg.scala 27:20] reg _T_4301; // @[Reg.scala 27:20] wire [3:0] buf_ldfwd = {_T_4307,_T_4305,_T_4303,_T_4301}; // @[Cat.scala 29:58] reg [1:0] buf_ldfwdtag_0; // @[Reg.scala 27:20] - wire [2:0] _GEN_368 = {{1'd0}, buf_ldfwdtag_0}; // @[el2_lsu_bus_buffer.scala 524:47] - wire _T_3638 = io_lsu_axi_rid == _GEN_368; // @[el2_lsu_bus_buffer.scala 524:47] - wire _T_3639 = buf_ldfwd[0] & _T_3638; // @[el2_lsu_bus_buffer.scala 524:27] - wire _T_3640 = _T_3636 | _T_3639; // @[el2_lsu_bus_buffer.scala 523:77] - wire _T_3641 = buf_dual_0 & buf_dualhi_0; // @[el2_lsu_bus_buffer.scala 525:26] - wire _T_3643 = ~buf_write[0]; // @[el2_lsu_bus_buffer.scala 525:44] - wire _T_3644 = _T_3641 & _T_3643; // @[el2_lsu_bus_buffer.scala 525:42] - wire _T_3645 = _T_3644 & buf_samedw_0; // @[el2_lsu_bus_buffer.scala 525:58] + wire [2:0] _GEN_368 = {{1'd0}, buf_ldfwdtag_0}; // @[el2_lsu_bus_buffer.scala 525:47] + wire _T_3638 = io_lsu_axi_rid == _GEN_368; // @[el2_lsu_bus_buffer.scala 525:47] + wire _T_3639 = buf_ldfwd[0] & _T_3638; // @[el2_lsu_bus_buffer.scala 525:27] + wire _T_3640 = _T_3636 | _T_3639; // @[el2_lsu_bus_buffer.scala 524:77] + wire _T_3641 = buf_dual_0 & buf_dualhi_0; // @[el2_lsu_bus_buffer.scala 526:26] + wire _T_3643 = ~buf_write[0]; // @[el2_lsu_bus_buffer.scala 526:44] + wire _T_3644 = _T_3641 & _T_3643; // @[el2_lsu_bus_buffer.scala 526:42] + wire _T_3645 = _T_3644 & buf_samedw_0; // @[el2_lsu_bus_buffer.scala 526:58] reg [1:0] buf_dualtag_0; // @[Reg.scala 27:20] - wire [2:0] _GEN_369 = {{1'd0}, buf_dualtag_0}; // @[el2_lsu_bus_buffer.scala 525:94] - wire _T_3646 = io_lsu_axi_rid == _GEN_369; // @[el2_lsu_bus_buffer.scala 525:94] - wire _T_3647 = _T_3645 & _T_3646; // @[el2_lsu_bus_buffer.scala 525:74] - wire _T_3648 = _T_3640 | _T_3647; // @[el2_lsu_bus_buffer.scala 524:71] - wire _T_3649 = bus_rsp_read & _T_3648; // @[el2_lsu_bus_buffer.scala 523:25] - wire _T_3650 = _T_3635 | _T_3649; // @[el2_lsu_bus_buffer.scala 522:105] + wire [2:0] _GEN_369 = {{1'd0}, buf_dualtag_0}; // @[el2_lsu_bus_buffer.scala 526:94] + wire _T_3646 = io_lsu_axi_rid == _GEN_369; // @[el2_lsu_bus_buffer.scala 526:94] + wire _T_3647 = _T_3645 & _T_3646; // @[el2_lsu_bus_buffer.scala 526:74] + wire _T_3648 = _T_3640 | _T_3647; // @[el2_lsu_bus_buffer.scala 525:71] + wire _T_3649 = bus_rsp_read & _T_3648; // @[el2_lsu_bus_buffer.scala 524:25] + wire _T_3650 = _T_3635 | _T_3649; // @[el2_lsu_bus_buffer.scala 523:105] wire _GEN_42 = _T_3589 & _T_3650; // @[Conditional.scala 39:67] wire _GEN_61 = _T_3555 ? 1'h0 : _GEN_42; // @[Conditional.scala 39:67] wire _GEN_73 = _T_3551 ? 1'h0 : _GEN_61; // @[Conditional.scala 39:67] wire buf_resp_state_bus_en_0 = _T_3528 ? 1'h0 : _GEN_73; // @[Conditional.scala 40:58] wire _T_3676 = 3'h4 == buf_state_0; // @[Conditional.scala 37:30] - wire [3:0] _T_3686 = buf_ldfwd >> buf_dualtag_0; // @[el2_lsu_bus_buffer.scala 537:21] + wire [3:0] _T_3686 = buf_ldfwd >> buf_dualtag_0; // @[el2_lsu_bus_buffer.scala 538:21] reg [1:0] buf_ldfwdtag_3; // @[Reg.scala 27:20] reg [1:0] buf_ldfwdtag_2; // @[Reg.scala 27:20] reg [1:0] buf_ldfwdtag_1; // @[Reg.scala 27:20] - wire [1:0] _GEN_23 = 2'h1 == buf_dualtag_0 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[el2_lsu_bus_buffer.scala 537:58] - wire [1:0] _GEN_24 = 2'h2 == buf_dualtag_0 ? buf_ldfwdtag_2 : _GEN_23; // @[el2_lsu_bus_buffer.scala 537:58] - wire [1:0] _GEN_25 = 2'h3 == buf_dualtag_0 ? buf_ldfwdtag_3 : _GEN_24; // @[el2_lsu_bus_buffer.scala 537:58] - wire [2:0] _GEN_371 = {{1'd0}, _GEN_25}; // @[el2_lsu_bus_buffer.scala 537:58] - wire _T_3688 = io_lsu_axi_rid == _GEN_371; // @[el2_lsu_bus_buffer.scala 537:58] - wire _T_3689 = _T_3686[0] & _T_3688; // @[el2_lsu_bus_buffer.scala 537:38] - wire _T_3690 = _T_3646 | _T_3689; // @[el2_lsu_bus_buffer.scala 536:95] - wire _T_3691 = bus_rsp_read & _T_3690; // @[el2_lsu_bus_buffer.scala 536:45] + wire [1:0] _GEN_23 = 2'h1 == buf_dualtag_0 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[el2_lsu_bus_buffer.scala 538:58] + wire [1:0] _GEN_24 = 2'h2 == buf_dualtag_0 ? buf_ldfwdtag_2 : _GEN_23; // @[el2_lsu_bus_buffer.scala 538:58] + wire [1:0] _GEN_25 = 2'h3 == buf_dualtag_0 ? buf_ldfwdtag_3 : _GEN_24; // @[el2_lsu_bus_buffer.scala 538:58] + wire [2:0] _GEN_371 = {{1'd0}, _GEN_25}; // @[el2_lsu_bus_buffer.scala 538:58] + wire _T_3688 = io_lsu_axi_rid == _GEN_371; // @[el2_lsu_bus_buffer.scala 538:58] + wire _T_3689 = _T_3686[0] & _T_3688; // @[el2_lsu_bus_buffer.scala 538:38] + wire _T_3690 = _T_3646 | _T_3689; // @[el2_lsu_bus_buffer.scala 537:95] + wire _T_3691 = bus_rsp_read & _T_3690; // @[el2_lsu_bus_buffer.scala 537:45] wire _GEN_36 = _T_3676 & _T_3691; // @[Conditional.scala 39:67] wire _GEN_43 = _T_3589 ? buf_resp_state_bus_en_0 : _GEN_36; // @[Conditional.scala 39:67] wire _GEN_53 = _T_3555 ? buf_cmd_state_bus_en_0 : _GEN_43; // @[Conditional.scala 39:67] wire _GEN_66 = _T_3551 ? 1'h0 : _GEN_53; // @[Conditional.scala 39:67] wire buf_state_bus_en_0 = _T_3528 ? 1'h0 : _GEN_66; // @[Conditional.scala 40:58] - wire _T_3568 = buf_state_bus_en_0 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 510:49] - wire _T_3569 = _T_3568 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 510:70] + wire _T_3568 = buf_state_bus_en_0 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 511:49] + wire _T_3569 = _T_3568 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 511:70] wire _T_3694 = 3'h5 == buf_state_0; // @[Conditional.scala 37:30] - wire [1:0] RspPtr = _T_2127[1:0]; // @[el2_lsu_bus_buffer.scala 447:10] - wire _T_3697 = RspPtr == 2'h0; // @[el2_lsu_bus_buffer.scala 542:37] - wire _T_3698 = buf_dualtag_0 == RspPtr; // @[el2_lsu_bus_buffer.scala 542:98] - wire _T_3699 = buf_dual_0 & _T_3698; // @[el2_lsu_bus_buffer.scala 542:80] - wire _T_3700 = _T_3697 | _T_3699; // @[el2_lsu_bus_buffer.scala 542:65] - wire _T_3701 = _T_3700 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 542:112] + wire [1:0] RspPtr = _T_2127[1:0]; // @[el2_lsu_bus_buffer.scala 448:10] + wire _T_3697 = RspPtr == 2'h0; // @[el2_lsu_bus_buffer.scala 543:37] + wire _T_3698 = buf_dualtag_0 == RspPtr; // @[el2_lsu_bus_buffer.scala 543:98] + wire _T_3699 = buf_dual_0 & _T_3698; // @[el2_lsu_bus_buffer.scala 543:80] + wire _T_3700 = _T_3697 | _T_3699; // @[el2_lsu_bus_buffer.scala 543:65] + wire _T_3701 = _T_3700 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 543:112] wire _T_3702 = 3'h6 == buf_state_0; // @[Conditional.scala 37:30] wire _GEN_31 = _T_3694 ? _T_3701 : _T_3702; // @[Conditional.scala 39:67] wire _GEN_37 = _T_3676 ? _T_3569 : _GEN_31; // @[Conditional.scala 39:67] @@ -1632,93 +1677,93 @@ module el2_lsu_bus_buffer( wire _GEN_54 = _T_3555 ? _T_3569 : _GEN_44; // @[Conditional.scala 39:67] wire _GEN_64 = _T_3551 ? _T_3554 : _GEN_54; // @[Conditional.scala 39:67] wire buf_state_en_0 = _T_3528 ? _T_3544 : _GEN_64; // @[Conditional.scala 40:58] - wire _T_2129 = _T_1853 & buf_state_en_0; // @[el2_lsu_bus_buffer.scala 459:94] - wire _T_2135 = ibuf_drain_vld & io_lsu_busreq_r; // @[el2_lsu_bus_buffer.scala 461:23] - wire _T_2137 = _T_2135 & _T_3532; // @[el2_lsu_bus_buffer.scala 461:41] - wire _T_2139 = _T_2137 & _T_1856; // @[el2_lsu_bus_buffer.scala 461:71] - wire _T_2141 = _T_2139 & _T_1854; // @[el2_lsu_bus_buffer.scala 461:92] - wire _T_2142 = _T_4471 | _T_2141; // @[el2_lsu_bus_buffer.scala 460:86] - wire _T_2143 = ibuf_byp & io_lsu_busreq_r; // @[el2_lsu_bus_buffer.scala 462:17] - wire _T_2144 = _T_2143 & io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 462:35] - wire _T_2146 = _T_2144 & _T_1857; // @[el2_lsu_bus_buffer.scala 462:52] - wire _T_2148 = _T_2146 & _T_1856; // @[el2_lsu_bus_buffer.scala 462:73] - wire _T_2149 = _T_2142 | _T_2148; // @[el2_lsu_bus_buffer.scala 461:114] - wire _T_2150 = _T_2129 & _T_2149; // @[el2_lsu_bus_buffer.scala 459:113] - wire _T_2152 = _T_2150 | buf_age_0[0]; // @[el2_lsu_bus_buffer.scala 462:97] - wire _T_2166 = _T_2139 & _T_1865; // @[el2_lsu_bus_buffer.scala 461:92] - wire _T_2167 = _T_4476 | _T_2166; // @[el2_lsu_bus_buffer.scala 460:86] - wire _T_2173 = _T_2146 & _T_1867; // @[el2_lsu_bus_buffer.scala 462:73] - wire _T_2174 = _T_2167 | _T_2173; // @[el2_lsu_bus_buffer.scala 461:114] - wire _T_2175 = _T_2129 & _T_2174; // @[el2_lsu_bus_buffer.scala 459:113] - wire _T_2177 = _T_2175 | buf_age_0[1]; // @[el2_lsu_bus_buffer.scala 462:97] - wire _T_2191 = _T_2139 & _T_1876; // @[el2_lsu_bus_buffer.scala 461:92] - wire _T_2192 = _T_4481 | _T_2191; // @[el2_lsu_bus_buffer.scala 460:86] - wire _T_2198 = _T_2146 & _T_1878; // @[el2_lsu_bus_buffer.scala 462:73] - wire _T_2199 = _T_2192 | _T_2198; // @[el2_lsu_bus_buffer.scala 461:114] - wire _T_2200 = _T_2129 & _T_2199; // @[el2_lsu_bus_buffer.scala 459:113] - wire _T_2202 = _T_2200 | buf_age_0[2]; // @[el2_lsu_bus_buffer.scala 462:97] - wire _T_2216 = _T_2139 & _T_1887; // @[el2_lsu_bus_buffer.scala 461:92] - wire _T_2217 = _T_4486 | _T_2216; // @[el2_lsu_bus_buffer.scala 460:86] - wire _T_2223 = _T_2146 & _T_1889; // @[el2_lsu_bus_buffer.scala 462:73] - wire _T_2224 = _T_2217 | _T_2223; // @[el2_lsu_bus_buffer.scala 461:114] - wire _T_2225 = _T_2129 & _T_2224; // @[el2_lsu_bus_buffer.scala 459:113] - wire _T_2227 = _T_2225 | buf_age_0[3]; // @[el2_lsu_bus_buffer.scala 462:97] + wire _T_2129 = _T_1853 & buf_state_en_0; // @[el2_lsu_bus_buffer.scala 460:94] + wire _T_2135 = ibuf_drain_vld & io_lsu_busreq_r; // @[el2_lsu_bus_buffer.scala 462:23] + wire _T_2137 = _T_2135 & _T_3532; // @[el2_lsu_bus_buffer.scala 462:41] + wire _T_2139 = _T_2137 & _T_1856; // @[el2_lsu_bus_buffer.scala 462:71] + wire _T_2141 = _T_2139 & _T_1854; // @[el2_lsu_bus_buffer.scala 462:92] + wire _T_2142 = _T_4471 | _T_2141; // @[el2_lsu_bus_buffer.scala 461:86] + wire _T_2143 = ibuf_byp & io_lsu_busreq_r; // @[el2_lsu_bus_buffer.scala 463:17] + wire _T_2144 = _T_2143 & io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 463:35] + wire _T_2146 = _T_2144 & _T_1857; // @[el2_lsu_bus_buffer.scala 463:52] + wire _T_2148 = _T_2146 & _T_1856; // @[el2_lsu_bus_buffer.scala 463:73] + wire _T_2149 = _T_2142 | _T_2148; // @[el2_lsu_bus_buffer.scala 462:114] + wire _T_2150 = _T_2129 & _T_2149; // @[el2_lsu_bus_buffer.scala 460:113] + wire _T_2152 = _T_2150 | buf_age_0[0]; // @[el2_lsu_bus_buffer.scala 463:97] + wire _T_2166 = _T_2139 & _T_1865; // @[el2_lsu_bus_buffer.scala 462:92] + wire _T_2167 = _T_4476 | _T_2166; // @[el2_lsu_bus_buffer.scala 461:86] + wire _T_2173 = _T_2146 & _T_1867; // @[el2_lsu_bus_buffer.scala 463:73] + wire _T_2174 = _T_2167 | _T_2173; // @[el2_lsu_bus_buffer.scala 462:114] + wire _T_2175 = _T_2129 & _T_2174; // @[el2_lsu_bus_buffer.scala 460:113] + wire _T_2177 = _T_2175 | buf_age_0[1]; // @[el2_lsu_bus_buffer.scala 463:97] + wire _T_2191 = _T_2139 & _T_1876; // @[el2_lsu_bus_buffer.scala 462:92] + wire _T_2192 = _T_4481 | _T_2191; // @[el2_lsu_bus_buffer.scala 461:86] + wire _T_2198 = _T_2146 & _T_1878; // @[el2_lsu_bus_buffer.scala 463:73] + wire _T_2199 = _T_2192 | _T_2198; // @[el2_lsu_bus_buffer.scala 462:114] + wire _T_2200 = _T_2129 & _T_2199; // @[el2_lsu_bus_buffer.scala 460:113] + wire _T_2202 = _T_2200 | buf_age_0[2]; // @[el2_lsu_bus_buffer.scala 463:97] + wire _T_2216 = _T_2139 & _T_1887; // @[el2_lsu_bus_buffer.scala 462:92] + wire _T_2217 = _T_4486 | _T_2216; // @[el2_lsu_bus_buffer.scala 461:86] + wire _T_2223 = _T_2146 & _T_1889; // @[el2_lsu_bus_buffer.scala 463:73] + wire _T_2224 = _T_2217 | _T_2223; // @[el2_lsu_bus_buffer.scala 462:114] + wire _T_2225 = _T_2129 & _T_2224; // @[el2_lsu_bus_buffer.scala 460:113] + wire _T_2227 = _T_2225 | buf_age_0[3]; // @[el2_lsu_bus_buffer.scala 463:97] wire [2:0] _T_2229 = {_T_2227,_T_2202,_T_2177}; // @[Cat.scala 29:58] - wire _T_3728 = 2'h1 == WrPtr0_r; // @[el2_lsu_bus_buffer.scala 497:117] - wire _T_3729 = _T_3534 & _T_3728; // @[el2_lsu_bus_buffer.scala 497:112] - wire _T_3731 = 2'h1 == WrPtr1_r; // @[el2_lsu_bus_buffer.scala 497:166] - wire _T_3732 = _T_3537 & _T_3731; // @[el2_lsu_bus_buffer.scala 497:161] - wire _T_3733 = _T_3729 | _T_3732; // @[el2_lsu_bus_buffer.scala 497:132] - wire _T_3734 = _T_853 & _T_3733; // @[el2_lsu_bus_buffer.scala 497:63] - wire _T_3735 = 2'h1 == ibuf_tag; // @[el2_lsu_bus_buffer.scala 497:206] - wire _T_3736 = ibuf_drain_vld & _T_3735; // @[el2_lsu_bus_buffer.scala 497:201] - wire _T_3737 = _T_3734 | _T_3736; // @[el2_lsu_bus_buffer.scala 497:183] + wire _T_3728 = 2'h1 == WrPtr0_r; // @[el2_lsu_bus_buffer.scala 498:117] + wire _T_3729 = _T_3534 & _T_3728; // @[el2_lsu_bus_buffer.scala 498:112] + wire _T_3731 = 2'h1 == WrPtr1_r; // @[el2_lsu_bus_buffer.scala 498:166] + wire _T_3732 = _T_3537 & _T_3731; // @[el2_lsu_bus_buffer.scala 498:161] + wire _T_3733 = _T_3729 | _T_3732; // @[el2_lsu_bus_buffer.scala 498:132] + wire _T_3734 = _T_853 & _T_3733; // @[el2_lsu_bus_buffer.scala 498:63] + wire _T_3735 = 2'h1 == ibuf_tag; // @[el2_lsu_bus_buffer.scala 498:206] + wire _T_3736 = ibuf_drain_vld & _T_3735; // @[el2_lsu_bus_buffer.scala 498:201] + wire _T_3737 = _T_3734 | _T_3736; // @[el2_lsu_bus_buffer.scala 498:183] wire _T_3782 = 3'h3 == buf_state_1; // @[Conditional.scala 37:30] - wire _T_3827 = io_lsu_axi_bid == 3'h1; // @[el2_lsu_bus_buffer.scala 522:73] - wire _T_3828 = bus_rsp_write & _T_3827; // @[el2_lsu_bus_buffer.scala 522:52] - wire _T_3829 = io_lsu_axi_rid == 3'h1; // @[el2_lsu_bus_buffer.scala 523:46] - wire [2:0] _GEN_372 = {{1'd0}, buf_ldfwdtag_1}; // @[el2_lsu_bus_buffer.scala 524:47] - wire _T_3831 = io_lsu_axi_rid == _GEN_372; // @[el2_lsu_bus_buffer.scala 524:47] - wire _T_3832 = buf_ldfwd[1] & _T_3831; // @[el2_lsu_bus_buffer.scala 524:27] - wire _T_3833 = _T_3829 | _T_3832; // @[el2_lsu_bus_buffer.scala 523:77] - wire _T_3834 = buf_dual_1 & buf_dualhi_1; // @[el2_lsu_bus_buffer.scala 525:26] - wire _T_3836 = ~buf_write[1]; // @[el2_lsu_bus_buffer.scala 525:44] - wire _T_3837 = _T_3834 & _T_3836; // @[el2_lsu_bus_buffer.scala 525:42] - wire _T_3838 = _T_3837 & buf_samedw_1; // @[el2_lsu_bus_buffer.scala 525:58] + wire _T_3827 = io_lsu_axi_bid == 3'h1; // @[el2_lsu_bus_buffer.scala 523:73] + wire _T_3828 = bus_rsp_write & _T_3827; // @[el2_lsu_bus_buffer.scala 523:52] + wire _T_3829 = io_lsu_axi_rid == 3'h1; // @[el2_lsu_bus_buffer.scala 524:46] + wire [2:0] _GEN_372 = {{1'd0}, buf_ldfwdtag_1}; // @[el2_lsu_bus_buffer.scala 525:47] + wire _T_3831 = io_lsu_axi_rid == _GEN_372; // @[el2_lsu_bus_buffer.scala 525:47] + wire _T_3832 = buf_ldfwd[1] & _T_3831; // @[el2_lsu_bus_buffer.scala 525:27] + wire _T_3833 = _T_3829 | _T_3832; // @[el2_lsu_bus_buffer.scala 524:77] + wire _T_3834 = buf_dual_1 & buf_dualhi_1; // @[el2_lsu_bus_buffer.scala 526:26] + wire _T_3836 = ~buf_write[1]; // @[el2_lsu_bus_buffer.scala 526:44] + wire _T_3837 = _T_3834 & _T_3836; // @[el2_lsu_bus_buffer.scala 526:42] + wire _T_3838 = _T_3837 & buf_samedw_1; // @[el2_lsu_bus_buffer.scala 526:58] reg [1:0] buf_dualtag_1; // @[Reg.scala 27:20] - wire [2:0] _GEN_373 = {{1'd0}, buf_dualtag_1}; // @[el2_lsu_bus_buffer.scala 525:94] - wire _T_3839 = io_lsu_axi_rid == _GEN_373; // @[el2_lsu_bus_buffer.scala 525:94] - wire _T_3840 = _T_3838 & _T_3839; // @[el2_lsu_bus_buffer.scala 525:74] - wire _T_3841 = _T_3833 | _T_3840; // @[el2_lsu_bus_buffer.scala 524:71] - wire _T_3842 = bus_rsp_read & _T_3841; // @[el2_lsu_bus_buffer.scala 523:25] - wire _T_3843 = _T_3828 | _T_3842; // @[el2_lsu_bus_buffer.scala 522:105] + wire [2:0] _GEN_373 = {{1'd0}, buf_dualtag_1}; // @[el2_lsu_bus_buffer.scala 526:94] + wire _T_3839 = io_lsu_axi_rid == _GEN_373; // @[el2_lsu_bus_buffer.scala 526:94] + wire _T_3840 = _T_3838 & _T_3839; // @[el2_lsu_bus_buffer.scala 526:74] + wire _T_3841 = _T_3833 | _T_3840; // @[el2_lsu_bus_buffer.scala 525:71] + wire _T_3842 = bus_rsp_read & _T_3841; // @[el2_lsu_bus_buffer.scala 524:25] + wire _T_3843 = _T_3828 | _T_3842; // @[el2_lsu_bus_buffer.scala 523:105] wire _GEN_118 = _T_3782 & _T_3843; // @[Conditional.scala 39:67] wire _GEN_137 = _T_3748 ? 1'h0 : _GEN_118; // @[Conditional.scala 39:67] wire _GEN_149 = _T_3744 ? 1'h0 : _GEN_137; // @[Conditional.scala 39:67] wire buf_resp_state_bus_en_1 = _T_3721 ? 1'h0 : _GEN_149; // @[Conditional.scala 40:58] wire _T_3869 = 3'h4 == buf_state_1; // @[Conditional.scala 37:30] - wire [3:0] _T_3879 = buf_ldfwd >> buf_dualtag_1; // @[el2_lsu_bus_buffer.scala 537:21] - wire [1:0] _GEN_99 = 2'h1 == buf_dualtag_1 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[el2_lsu_bus_buffer.scala 537:58] - wire [1:0] _GEN_100 = 2'h2 == buf_dualtag_1 ? buf_ldfwdtag_2 : _GEN_99; // @[el2_lsu_bus_buffer.scala 537:58] - wire [1:0] _GEN_101 = 2'h3 == buf_dualtag_1 ? buf_ldfwdtag_3 : _GEN_100; // @[el2_lsu_bus_buffer.scala 537:58] - wire [2:0] _GEN_375 = {{1'd0}, _GEN_101}; // @[el2_lsu_bus_buffer.scala 537:58] - wire _T_3881 = io_lsu_axi_rid == _GEN_375; // @[el2_lsu_bus_buffer.scala 537:58] - wire _T_3882 = _T_3879[0] & _T_3881; // @[el2_lsu_bus_buffer.scala 537:38] - wire _T_3883 = _T_3839 | _T_3882; // @[el2_lsu_bus_buffer.scala 536:95] - wire _T_3884 = bus_rsp_read & _T_3883; // @[el2_lsu_bus_buffer.scala 536:45] + wire [3:0] _T_3879 = buf_ldfwd >> buf_dualtag_1; // @[el2_lsu_bus_buffer.scala 538:21] + wire [1:0] _GEN_99 = 2'h1 == buf_dualtag_1 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[el2_lsu_bus_buffer.scala 538:58] + wire [1:0] _GEN_100 = 2'h2 == buf_dualtag_1 ? buf_ldfwdtag_2 : _GEN_99; // @[el2_lsu_bus_buffer.scala 538:58] + wire [1:0] _GEN_101 = 2'h3 == buf_dualtag_1 ? buf_ldfwdtag_3 : _GEN_100; // @[el2_lsu_bus_buffer.scala 538:58] + wire [2:0] _GEN_375 = {{1'd0}, _GEN_101}; // @[el2_lsu_bus_buffer.scala 538:58] + wire _T_3881 = io_lsu_axi_rid == _GEN_375; // @[el2_lsu_bus_buffer.scala 538:58] + wire _T_3882 = _T_3879[0] & _T_3881; // @[el2_lsu_bus_buffer.scala 538:38] + wire _T_3883 = _T_3839 | _T_3882; // @[el2_lsu_bus_buffer.scala 537:95] + wire _T_3884 = bus_rsp_read & _T_3883; // @[el2_lsu_bus_buffer.scala 537:45] wire _GEN_112 = _T_3869 & _T_3884; // @[Conditional.scala 39:67] wire _GEN_119 = _T_3782 ? buf_resp_state_bus_en_1 : _GEN_112; // @[Conditional.scala 39:67] wire _GEN_129 = _T_3748 ? buf_cmd_state_bus_en_1 : _GEN_119; // @[Conditional.scala 39:67] wire _GEN_142 = _T_3744 ? 1'h0 : _GEN_129; // @[Conditional.scala 39:67] wire buf_state_bus_en_1 = _T_3721 ? 1'h0 : _GEN_142; // @[Conditional.scala 40:58] - wire _T_3761 = buf_state_bus_en_1 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 510:49] - wire _T_3762 = _T_3761 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 510:70] + wire _T_3761 = buf_state_bus_en_1 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 511:49] + wire _T_3762 = _T_3761 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 511:70] wire _T_3887 = 3'h5 == buf_state_1; // @[Conditional.scala 37:30] - wire _T_3890 = RspPtr == 2'h1; // @[el2_lsu_bus_buffer.scala 542:37] - wire _T_3891 = buf_dualtag_1 == RspPtr; // @[el2_lsu_bus_buffer.scala 542:98] - wire _T_3892 = buf_dual_1 & _T_3891; // @[el2_lsu_bus_buffer.scala 542:80] - wire _T_3893 = _T_3890 | _T_3892; // @[el2_lsu_bus_buffer.scala 542:65] - wire _T_3894 = _T_3893 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 542:112] + wire _T_3890 = RspPtr == 2'h1; // @[el2_lsu_bus_buffer.scala 543:37] + wire _T_3891 = buf_dualtag_1 == RspPtr; // @[el2_lsu_bus_buffer.scala 543:98] + wire _T_3892 = buf_dual_1 & _T_3891; // @[el2_lsu_bus_buffer.scala 543:80] + wire _T_3893 = _T_3890 | _T_3892; // @[el2_lsu_bus_buffer.scala 543:65] + wire _T_3894 = _T_3893 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 543:112] wire _T_3895 = 3'h6 == buf_state_1; // @[Conditional.scala 37:30] wire _GEN_107 = _T_3887 ? _T_3894 : _T_3895; // @[Conditional.scala 39:67] wire _GEN_113 = _T_3869 ? _T_3762 : _GEN_107; // @[Conditional.scala 39:67] @@ -1726,89 +1771,89 @@ module el2_lsu_bus_buffer( wire _GEN_130 = _T_3748 ? _T_3762 : _GEN_120; // @[Conditional.scala 39:67] wire _GEN_140 = _T_3744 ? _T_3554 : _GEN_130; // @[Conditional.scala 39:67] wire buf_state_en_1 = _T_3721 ? _T_3737 : _GEN_140; // @[Conditional.scala 40:58] - wire _T_2231 = _T_1864 & buf_state_en_1; // @[el2_lsu_bus_buffer.scala 459:94] - wire _T_2241 = _T_2137 & _T_1867; // @[el2_lsu_bus_buffer.scala 461:71] - wire _T_2243 = _T_2241 & _T_1854; // @[el2_lsu_bus_buffer.scala 461:92] - wire _T_2244 = _T_4471 | _T_2243; // @[el2_lsu_bus_buffer.scala 460:86] - wire _T_2248 = _T_2144 & _T_1868; // @[el2_lsu_bus_buffer.scala 462:52] - wire _T_2250 = _T_2248 & _T_1856; // @[el2_lsu_bus_buffer.scala 462:73] - wire _T_2251 = _T_2244 | _T_2250; // @[el2_lsu_bus_buffer.scala 461:114] - wire _T_2252 = _T_2231 & _T_2251; // @[el2_lsu_bus_buffer.scala 459:113] - wire _T_2254 = _T_2252 | buf_age_1[0]; // @[el2_lsu_bus_buffer.scala 462:97] - wire _T_2268 = _T_2241 & _T_1865; // @[el2_lsu_bus_buffer.scala 461:92] - wire _T_2269 = _T_4476 | _T_2268; // @[el2_lsu_bus_buffer.scala 460:86] - wire _T_2275 = _T_2248 & _T_1867; // @[el2_lsu_bus_buffer.scala 462:73] - wire _T_2276 = _T_2269 | _T_2275; // @[el2_lsu_bus_buffer.scala 461:114] - wire _T_2277 = _T_2231 & _T_2276; // @[el2_lsu_bus_buffer.scala 459:113] - wire _T_2279 = _T_2277 | buf_age_1[1]; // @[el2_lsu_bus_buffer.scala 462:97] - wire _T_2293 = _T_2241 & _T_1876; // @[el2_lsu_bus_buffer.scala 461:92] - wire _T_2294 = _T_4481 | _T_2293; // @[el2_lsu_bus_buffer.scala 460:86] - wire _T_2300 = _T_2248 & _T_1878; // @[el2_lsu_bus_buffer.scala 462:73] - wire _T_2301 = _T_2294 | _T_2300; // @[el2_lsu_bus_buffer.scala 461:114] - wire _T_2302 = _T_2231 & _T_2301; // @[el2_lsu_bus_buffer.scala 459:113] - wire _T_2304 = _T_2302 | buf_age_1[2]; // @[el2_lsu_bus_buffer.scala 462:97] - wire _T_2318 = _T_2241 & _T_1887; // @[el2_lsu_bus_buffer.scala 461:92] - wire _T_2319 = _T_4486 | _T_2318; // @[el2_lsu_bus_buffer.scala 460:86] - wire _T_2325 = _T_2248 & _T_1889; // @[el2_lsu_bus_buffer.scala 462:73] - wire _T_2326 = _T_2319 | _T_2325; // @[el2_lsu_bus_buffer.scala 461:114] - wire _T_2327 = _T_2231 & _T_2326; // @[el2_lsu_bus_buffer.scala 459:113] - wire _T_2329 = _T_2327 | buf_age_1[3]; // @[el2_lsu_bus_buffer.scala 462:97] + wire _T_2231 = _T_1864 & buf_state_en_1; // @[el2_lsu_bus_buffer.scala 460:94] + wire _T_2241 = _T_2137 & _T_1867; // @[el2_lsu_bus_buffer.scala 462:71] + wire _T_2243 = _T_2241 & _T_1854; // @[el2_lsu_bus_buffer.scala 462:92] + wire _T_2244 = _T_4471 | _T_2243; // @[el2_lsu_bus_buffer.scala 461:86] + wire _T_2248 = _T_2144 & _T_1868; // @[el2_lsu_bus_buffer.scala 463:52] + wire _T_2250 = _T_2248 & _T_1856; // @[el2_lsu_bus_buffer.scala 463:73] + wire _T_2251 = _T_2244 | _T_2250; // @[el2_lsu_bus_buffer.scala 462:114] + wire _T_2252 = _T_2231 & _T_2251; // @[el2_lsu_bus_buffer.scala 460:113] + wire _T_2254 = _T_2252 | buf_age_1[0]; // @[el2_lsu_bus_buffer.scala 463:97] + wire _T_2268 = _T_2241 & _T_1865; // @[el2_lsu_bus_buffer.scala 462:92] + wire _T_2269 = _T_4476 | _T_2268; // @[el2_lsu_bus_buffer.scala 461:86] + wire _T_2275 = _T_2248 & _T_1867; // @[el2_lsu_bus_buffer.scala 463:73] + wire _T_2276 = _T_2269 | _T_2275; // @[el2_lsu_bus_buffer.scala 462:114] + wire _T_2277 = _T_2231 & _T_2276; // @[el2_lsu_bus_buffer.scala 460:113] + wire _T_2279 = _T_2277 | buf_age_1[1]; // @[el2_lsu_bus_buffer.scala 463:97] + wire _T_2293 = _T_2241 & _T_1876; // @[el2_lsu_bus_buffer.scala 462:92] + wire _T_2294 = _T_4481 | _T_2293; // @[el2_lsu_bus_buffer.scala 461:86] + wire _T_2300 = _T_2248 & _T_1878; // @[el2_lsu_bus_buffer.scala 463:73] + wire _T_2301 = _T_2294 | _T_2300; // @[el2_lsu_bus_buffer.scala 462:114] + wire _T_2302 = _T_2231 & _T_2301; // @[el2_lsu_bus_buffer.scala 460:113] + wire _T_2304 = _T_2302 | buf_age_1[2]; // @[el2_lsu_bus_buffer.scala 463:97] + wire _T_2318 = _T_2241 & _T_1887; // @[el2_lsu_bus_buffer.scala 462:92] + wire _T_2319 = _T_4486 | _T_2318; // @[el2_lsu_bus_buffer.scala 461:86] + wire _T_2325 = _T_2248 & _T_1889; // @[el2_lsu_bus_buffer.scala 463:73] + wire _T_2326 = _T_2319 | _T_2325; // @[el2_lsu_bus_buffer.scala 462:114] + wire _T_2327 = _T_2231 & _T_2326; // @[el2_lsu_bus_buffer.scala 460:113] + wire _T_2329 = _T_2327 | buf_age_1[3]; // @[el2_lsu_bus_buffer.scala 463:97] wire [2:0] _T_2331 = {_T_2329,_T_2304,_T_2279}; // @[Cat.scala 29:58] - wire _T_3921 = 2'h2 == WrPtr0_r; // @[el2_lsu_bus_buffer.scala 497:117] - wire _T_3922 = _T_3534 & _T_3921; // @[el2_lsu_bus_buffer.scala 497:112] - wire _T_3924 = 2'h2 == WrPtr1_r; // @[el2_lsu_bus_buffer.scala 497:166] - wire _T_3925 = _T_3537 & _T_3924; // @[el2_lsu_bus_buffer.scala 497:161] - wire _T_3926 = _T_3922 | _T_3925; // @[el2_lsu_bus_buffer.scala 497:132] - wire _T_3927 = _T_853 & _T_3926; // @[el2_lsu_bus_buffer.scala 497:63] - wire _T_3928 = 2'h2 == ibuf_tag; // @[el2_lsu_bus_buffer.scala 497:206] - wire _T_3929 = ibuf_drain_vld & _T_3928; // @[el2_lsu_bus_buffer.scala 497:201] - wire _T_3930 = _T_3927 | _T_3929; // @[el2_lsu_bus_buffer.scala 497:183] + wire _T_3921 = 2'h2 == WrPtr0_r; // @[el2_lsu_bus_buffer.scala 498:117] + wire _T_3922 = _T_3534 & _T_3921; // @[el2_lsu_bus_buffer.scala 498:112] + wire _T_3924 = 2'h2 == WrPtr1_r; // @[el2_lsu_bus_buffer.scala 498:166] + wire _T_3925 = _T_3537 & _T_3924; // @[el2_lsu_bus_buffer.scala 498:161] + wire _T_3926 = _T_3922 | _T_3925; // @[el2_lsu_bus_buffer.scala 498:132] + wire _T_3927 = _T_853 & _T_3926; // @[el2_lsu_bus_buffer.scala 498:63] + wire _T_3928 = 2'h2 == ibuf_tag; // @[el2_lsu_bus_buffer.scala 498:206] + wire _T_3929 = ibuf_drain_vld & _T_3928; // @[el2_lsu_bus_buffer.scala 498:201] + wire _T_3930 = _T_3927 | _T_3929; // @[el2_lsu_bus_buffer.scala 498:183] wire _T_3975 = 3'h3 == buf_state_2; // @[Conditional.scala 37:30] - wire _T_4020 = io_lsu_axi_bid == 3'h2; // @[el2_lsu_bus_buffer.scala 522:73] - wire _T_4021 = bus_rsp_write & _T_4020; // @[el2_lsu_bus_buffer.scala 522:52] - wire _T_4022 = io_lsu_axi_rid == 3'h2; // @[el2_lsu_bus_buffer.scala 523:46] - wire [2:0] _GEN_376 = {{1'd0}, buf_ldfwdtag_2}; // @[el2_lsu_bus_buffer.scala 524:47] - wire _T_4024 = io_lsu_axi_rid == _GEN_376; // @[el2_lsu_bus_buffer.scala 524:47] - wire _T_4025 = buf_ldfwd[2] & _T_4024; // @[el2_lsu_bus_buffer.scala 524:27] - wire _T_4026 = _T_4022 | _T_4025; // @[el2_lsu_bus_buffer.scala 523:77] - wire _T_4027 = buf_dual_2 & buf_dualhi_2; // @[el2_lsu_bus_buffer.scala 525:26] - wire _T_4029 = ~buf_write[2]; // @[el2_lsu_bus_buffer.scala 525:44] - wire _T_4030 = _T_4027 & _T_4029; // @[el2_lsu_bus_buffer.scala 525:42] - wire _T_4031 = _T_4030 & buf_samedw_2; // @[el2_lsu_bus_buffer.scala 525:58] + wire _T_4020 = io_lsu_axi_bid == 3'h2; // @[el2_lsu_bus_buffer.scala 523:73] + wire _T_4021 = bus_rsp_write & _T_4020; // @[el2_lsu_bus_buffer.scala 523:52] + wire _T_4022 = io_lsu_axi_rid == 3'h2; // @[el2_lsu_bus_buffer.scala 524:46] + wire [2:0] _GEN_376 = {{1'd0}, buf_ldfwdtag_2}; // @[el2_lsu_bus_buffer.scala 525:47] + wire _T_4024 = io_lsu_axi_rid == _GEN_376; // @[el2_lsu_bus_buffer.scala 525:47] + wire _T_4025 = buf_ldfwd[2] & _T_4024; // @[el2_lsu_bus_buffer.scala 525:27] + wire _T_4026 = _T_4022 | _T_4025; // @[el2_lsu_bus_buffer.scala 524:77] + wire _T_4027 = buf_dual_2 & buf_dualhi_2; // @[el2_lsu_bus_buffer.scala 526:26] + wire _T_4029 = ~buf_write[2]; // @[el2_lsu_bus_buffer.scala 526:44] + wire _T_4030 = _T_4027 & _T_4029; // @[el2_lsu_bus_buffer.scala 526:42] + wire _T_4031 = _T_4030 & buf_samedw_2; // @[el2_lsu_bus_buffer.scala 526:58] reg [1:0] buf_dualtag_2; // @[Reg.scala 27:20] - wire [2:0] _GEN_377 = {{1'd0}, buf_dualtag_2}; // @[el2_lsu_bus_buffer.scala 525:94] - wire _T_4032 = io_lsu_axi_rid == _GEN_377; // @[el2_lsu_bus_buffer.scala 525:94] - wire _T_4033 = _T_4031 & _T_4032; // @[el2_lsu_bus_buffer.scala 525:74] - wire _T_4034 = _T_4026 | _T_4033; // @[el2_lsu_bus_buffer.scala 524:71] - wire _T_4035 = bus_rsp_read & _T_4034; // @[el2_lsu_bus_buffer.scala 523:25] - wire _T_4036 = _T_4021 | _T_4035; // @[el2_lsu_bus_buffer.scala 522:105] + wire [2:0] _GEN_377 = {{1'd0}, buf_dualtag_2}; // @[el2_lsu_bus_buffer.scala 526:94] + wire _T_4032 = io_lsu_axi_rid == _GEN_377; // @[el2_lsu_bus_buffer.scala 526:94] + wire _T_4033 = _T_4031 & _T_4032; // @[el2_lsu_bus_buffer.scala 526:74] + wire _T_4034 = _T_4026 | _T_4033; // @[el2_lsu_bus_buffer.scala 525:71] + wire _T_4035 = bus_rsp_read & _T_4034; // @[el2_lsu_bus_buffer.scala 524:25] + wire _T_4036 = _T_4021 | _T_4035; // @[el2_lsu_bus_buffer.scala 523:105] wire _GEN_194 = _T_3975 & _T_4036; // @[Conditional.scala 39:67] wire _GEN_213 = _T_3941 ? 1'h0 : _GEN_194; // @[Conditional.scala 39:67] wire _GEN_225 = _T_3937 ? 1'h0 : _GEN_213; // @[Conditional.scala 39:67] wire buf_resp_state_bus_en_2 = _T_3914 ? 1'h0 : _GEN_225; // @[Conditional.scala 40:58] wire _T_4062 = 3'h4 == buf_state_2; // @[Conditional.scala 37:30] - wire [3:0] _T_4072 = buf_ldfwd >> buf_dualtag_2; // @[el2_lsu_bus_buffer.scala 537:21] - wire [1:0] _GEN_175 = 2'h1 == buf_dualtag_2 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[el2_lsu_bus_buffer.scala 537:58] - wire [1:0] _GEN_176 = 2'h2 == buf_dualtag_2 ? buf_ldfwdtag_2 : _GEN_175; // @[el2_lsu_bus_buffer.scala 537:58] - wire [1:0] _GEN_177 = 2'h3 == buf_dualtag_2 ? buf_ldfwdtag_3 : _GEN_176; // @[el2_lsu_bus_buffer.scala 537:58] - wire [2:0] _GEN_379 = {{1'd0}, _GEN_177}; // @[el2_lsu_bus_buffer.scala 537:58] - wire _T_4074 = io_lsu_axi_rid == _GEN_379; // @[el2_lsu_bus_buffer.scala 537:58] - wire _T_4075 = _T_4072[0] & _T_4074; // @[el2_lsu_bus_buffer.scala 537:38] - wire _T_4076 = _T_4032 | _T_4075; // @[el2_lsu_bus_buffer.scala 536:95] - wire _T_4077 = bus_rsp_read & _T_4076; // @[el2_lsu_bus_buffer.scala 536:45] + wire [3:0] _T_4072 = buf_ldfwd >> buf_dualtag_2; // @[el2_lsu_bus_buffer.scala 538:21] + wire [1:0] _GEN_175 = 2'h1 == buf_dualtag_2 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[el2_lsu_bus_buffer.scala 538:58] + wire [1:0] _GEN_176 = 2'h2 == buf_dualtag_2 ? buf_ldfwdtag_2 : _GEN_175; // @[el2_lsu_bus_buffer.scala 538:58] + wire [1:0] _GEN_177 = 2'h3 == buf_dualtag_2 ? buf_ldfwdtag_3 : _GEN_176; // @[el2_lsu_bus_buffer.scala 538:58] + wire [2:0] _GEN_379 = {{1'd0}, _GEN_177}; // @[el2_lsu_bus_buffer.scala 538:58] + wire _T_4074 = io_lsu_axi_rid == _GEN_379; // @[el2_lsu_bus_buffer.scala 538:58] + wire _T_4075 = _T_4072[0] & _T_4074; // @[el2_lsu_bus_buffer.scala 538:38] + wire _T_4076 = _T_4032 | _T_4075; // @[el2_lsu_bus_buffer.scala 537:95] + wire _T_4077 = bus_rsp_read & _T_4076; // @[el2_lsu_bus_buffer.scala 537:45] wire _GEN_188 = _T_4062 & _T_4077; // @[Conditional.scala 39:67] wire _GEN_195 = _T_3975 ? buf_resp_state_bus_en_2 : _GEN_188; // @[Conditional.scala 39:67] wire _GEN_205 = _T_3941 ? buf_cmd_state_bus_en_2 : _GEN_195; // @[Conditional.scala 39:67] wire _GEN_218 = _T_3937 ? 1'h0 : _GEN_205; // @[Conditional.scala 39:67] wire buf_state_bus_en_2 = _T_3914 ? 1'h0 : _GEN_218; // @[Conditional.scala 40:58] - wire _T_3954 = buf_state_bus_en_2 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 510:49] - wire _T_3955 = _T_3954 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 510:70] + wire _T_3954 = buf_state_bus_en_2 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 511:49] + wire _T_3955 = _T_3954 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 511:70] wire _T_4080 = 3'h5 == buf_state_2; // @[Conditional.scala 37:30] - wire _T_4083 = RspPtr == 2'h2; // @[el2_lsu_bus_buffer.scala 542:37] - wire _T_4084 = buf_dualtag_2 == RspPtr; // @[el2_lsu_bus_buffer.scala 542:98] - wire _T_4085 = buf_dual_2 & _T_4084; // @[el2_lsu_bus_buffer.scala 542:80] - wire _T_4086 = _T_4083 | _T_4085; // @[el2_lsu_bus_buffer.scala 542:65] - wire _T_4087 = _T_4086 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 542:112] + wire _T_4083 = RspPtr == 2'h2; // @[el2_lsu_bus_buffer.scala 543:37] + wire _T_4084 = buf_dualtag_2 == RspPtr; // @[el2_lsu_bus_buffer.scala 543:98] + wire _T_4085 = buf_dual_2 & _T_4084; // @[el2_lsu_bus_buffer.scala 543:80] + wire _T_4086 = _T_4083 | _T_4085; // @[el2_lsu_bus_buffer.scala 543:65] + wire _T_4087 = _T_4086 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 543:112] wire _T_4088 = 3'h6 == buf_state_2; // @[Conditional.scala 37:30] wire _GEN_183 = _T_4080 ? _T_4087 : _T_4088; // @[Conditional.scala 39:67] wire _GEN_189 = _T_4062 ? _T_3955 : _GEN_183; // @[Conditional.scala 39:67] @@ -1816,89 +1861,89 @@ module el2_lsu_bus_buffer( wire _GEN_206 = _T_3941 ? _T_3955 : _GEN_196; // @[Conditional.scala 39:67] wire _GEN_216 = _T_3937 ? _T_3554 : _GEN_206; // @[Conditional.scala 39:67] wire buf_state_en_2 = _T_3914 ? _T_3930 : _GEN_216; // @[Conditional.scala 40:58] - wire _T_2333 = _T_1875 & buf_state_en_2; // @[el2_lsu_bus_buffer.scala 459:94] - wire _T_2343 = _T_2137 & _T_1878; // @[el2_lsu_bus_buffer.scala 461:71] - wire _T_2345 = _T_2343 & _T_1854; // @[el2_lsu_bus_buffer.scala 461:92] - wire _T_2346 = _T_4471 | _T_2345; // @[el2_lsu_bus_buffer.scala 460:86] - wire _T_2350 = _T_2144 & _T_1879; // @[el2_lsu_bus_buffer.scala 462:52] - wire _T_2352 = _T_2350 & _T_1856; // @[el2_lsu_bus_buffer.scala 462:73] - wire _T_2353 = _T_2346 | _T_2352; // @[el2_lsu_bus_buffer.scala 461:114] - wire _T_2354 = _T_2333 & _T_2353; // @[el2_lsu_bus_buffer.scala 459:113] - wire _T_2356 = _T_2354 | buf_age_2[0]; // @[el2_lsu_bus_buffer.scala 462:97] - wire _T_2370 = _T_2343 & _T_1865; // @[el2_lsu_bus_buffer.scala 461:92] - wire _T_2371 = _T_4476 | _T_2370; // @[el2_lsu_bus_buffer.scala 460:86] - wire _T_2377 = _T_2350 & _T_1867; // @[el2_lsu_bus_buffer.scala 462:73] - wire _T_2378 = _T_2371 | _T_2377; // @[el2_lsu_bus_buffer.scala 461:114] - wire _T_2379 = _T_2333 & _T_2378; // @[el2_lsu_bus_buffer.scala 459:113] - wire _T_2381 = _T_2379 | buf_age_2[1]; // @[el2_lsu_bus_buffer.scala 462:97] - wire _T_2395 = _T_2343 & _T_1876; // @[el2_lsu_bus_buffer.scala 461:92] - wire _T_2396 = _T_4481 | _T_2395; // @[el2_lsu_bus_buffer.scala 460:86] - wire _T_2402 = _T_2350 & _T_1878; // @[el2_lsu_bus_buffer.scala 462:73] - wire _T_2403 = _T_2396 | _T_2402; // @[el2_lsu_bus_buffer.scala 461:114] - wire _T_2404 = _T_2333 & _T_2403; // @[el2_lsu_bus_buffer.scala 459:113] - wire _T_2406 = _T_2404 | buf_age_2[2]; // @[el2_lsu_bus_buffer.scala 462:97] - wire _T_2420 = _T_2343 & _T_1887; // @[el2_lsu_bus_buffer.scala 461:92] - wire _T_2421 = _T_4486 | _T_2420; // @[el2_lsu_bus_buffer.scala 460:86] - wire _T_2427 = _T_2350 & _T_1889; // @[el2_lsu_bus_buffer.scala 462:73] - wire _T_2428 = _T_2421 | _T_2427; // @[el2_lsu_bus_buffer.scala 461:114] - wire _T_2429 = _T_2333 & _T_2428; // @[el2_lsu_bus_buffer.scala 459:113] - wire _T_2431 = _T_2429 | buf_age_2[3]; // @[el2_lsu_bus_buffer.scala 462:97] + wire _T_2333 = _T_1875 & buf_state_en_2; // @[el2_lsu_bus_buffer.scala 460:94] + wire _T_2343 = _T_2137 & _T_1878; // @[el2_lsu_bus_buffer.scala 462:71] + wire _T_2345 = _T_2343 & _T_1854; // @[el2_lsu_bus_buffer.scala 462:92] + wire _T_2346 = _T_4471 | _T_2345; // @[el2_lsu_bus_buffer.scala 461:86] + wire _T_2350 = _T_2144 & _T_1879; // @[el2_lsu_bus_buffer.scala 463:52] + wire _T_2352 = _T_2350 & _T_1856; // @[el2_lsu_bus_buffer.scala 463:73] + wire _T_2353 = _T_2346 | _T_2352; // @[el2_lsu_bus_buffer.scala 462:114] + wire _T_2354 = _T_2333 & _T_2353; // @[el2_lsu_bus_buffer.scala 460:113] + wire _T_2356 = _T_2354 | buf_age_2[0]; // @[el2_lsu_bus_buffer.scala 463:97] + wire _T_2370 = _T_2343 & _T_1865; // @[el2_lsu_bus_buffer.scala 462:92] + wire _T_2371 = _T_4476 | _T_2370; // @[el2_lsu_bus_buffer.scala 461:86] + wire _T_2377 = _T_2350 & _T_1867; // @[el2_lsu_bus_buffer.scala 463:73] + wire _T_2378 = _T_2371 | _T_2377; // @[el2_lsu_bus_buffer.scala 462:114] + wire _T_2379 = _T_2333 & _T_2378; // @[el2_lsu_bus_buffer.scala 460:113] + wire _T_2381 = _T_2379 | buf_age_2[1]; // @[el2_lsu_bus_buffer.scala 463:97] + wire _T_2395 = _T_2343 & _T_1876; // @[el2_lsu_bus_buffer.scala 462:92] + wire _T_2396 = _T_4481 | _T_2395; // @[el2_lsu_bus_buffer.scala 461:86] + wire _T_2402 = _T_2350 & _T_1878; // @[el2_lsu_bus_buffer.scala 463:73] + wire _T_2403 = _T_2396 | _T_2402; // @[el2_lsu_bus_buffer.scala 462:114] + wire _T_2404 = _T_2333 & _T_2403; // @[el2_lsu_bus_buffer.scala 460:113] + wire _T_2406 = _T_2404 | buf_age_2[2]; // @[el2_lsu_bus_buffer.scala 463:97] + wire _T_2420 = _T_2343 & _T_1887; // @[el2_lsu_bus_buffer.scala 462:92] + wire _T_2421 = _T_4486 | _T_2420; // @[el2_lsu_bus_buffer.scala 461:86] + wire _T_2427 = _T_2350 & _T_1889; // @[el2_lsu_bus_buffer.scala 463:73] + wire _T_2428 = _T_2421 | _T_2427; // @[el2_lsu_bus_buffer.scala 462:114] + wire _T_2429 = _T_2333 & _T_2428; // @[el2_lsu_bus_buffer.scala 460:113] + wire _T_2431 = _T_2429 | buf_age_2[3]; // @[el2_lsu_bus_buffer.scala 463:97] wire [2:0] _T_2433 = {_T_2431,_T_2406,_T_2381}; // @[Cat.scala 29:58] - wire _T_4114 = 2'h3 == WrPtr0_r; // @[el2_lsu_bus_buffer.scala 497:117] - wire _T_4115 = _T_3534 & _T_4114; // @[el2_lsu_bus_buffer.scala 497:112] - wire _T_4117 = 2'h3 == WrPtr1_r; // @[el2_lsu_bus_buffer.scala 497:166] - wire _T_4118 = _T_3537 & _T_4117; // @[el2_lsu_bus_buffer.scala 497:161] - wire _T_4119 = _T_4115 | _T_4118; // @[el2_lsu_bus_buffer.scala 497:132] - wire _T_4120 = _T_853 & _T_4119; // @[el2_lsu_bus_buffer.scala 497:63] - wire _T_4121 = 2'h3 == ibuf_tag; // @[el2_lsu_bus_buffer.scala 497:206] - wire _T_4122 = ibuf_drain_vld & _T_4121; // @[el2_lsu_bus_buffer.scala 497:201] - wire _T_4123 = _T_4120 | _T_4122; // @[el2_lsu_bus_buffer.scala 497:183] + wire _T_4114 = 2'h3 == WrPtr0_r; // @[el2_lsu_bus_buffer.scala 498:117] + wire _T_4115 = _T_3534 & _T_4114; // @[el2_lsu_bus_buffer.scala 498:112] + wire _T_4117 = 2'h3 == WrPtr1_r; // @[el2_lsu_bus_buffer.scala 498:166] + wire _T_4118 = _T_3537 & _T_4117; // @[el2_lsu_bus_buffer.scala 498:161] + wire _T_4119 = _T_4115 | _T_4118; // @[el2_lsu_bus_buffer.scala 498:132] + wire _T_4120 = _T_853 & _T_4119; // @[el2_lsu_bus_buffer.scala 498:63] + wire _T_4121 = 2'h3 == ibuf_tag; // @[el2_lsu_bus_buffer.scala 498:206] + wire _T_4122 = ibuf_drain_vld & _T_4121; // @[el2_lsu_bus_buffer.scala 498:201] + wire _T_4123 = _T_4120 | _T_4122; // @[el2_lsu_bus_buffer.scala 498:183] wire _T_4168 = 3'h3 == buf_state_3; // @[Conditional.scala 37:30] - wire _T_4213 = io_lsu_axi_bid == 3'h3; // @[el2_lsu_bus_buffer.scala 522:73] - wire _T_4214 = bus_rsp_write & _T_4213; // @[el2_lsu_bus_buffer.scala 522:52] - wire _T_4215 = io_lsu_axi_rid == 3'h3; // @[el2_lsu_bus_buffer.scala 523:46] - wire [2:0] _GEN_380 = {{1'd0}, buf_ldfwdtag_3}; // @[el2_lsu_bus_buffer.scala 524:47] - wire _T_4217 = io_lsu_axi_rid == _GEN_380; // @[el2_lsu_bus_buffer.scala 524:47] - wire _T_4218 = buf_ldfwd[3] & _T_4217; // @[el2_lsu_bus_buffer.scala 524:27] - wire _T_4219 = _T_4215 | _T_4218; // @[el2_lsu_bus_buffer.scala 523:77] - wire _T_4220 = buf_dual_3 & buf_dualhi_3; // @[el2_lsu_bus_buffer.scala 525:26] - wire _T_4222 = ~buf_write[3]; // @[el2_lsu_bus_buffer.scala 525:44] - wire _T_4223 = _T_4220 & _T_4222; // @[el2_lsu_bus_buffer.scala 525:42] - wire _T_4224 = _T_4223 & buf_samedw_3; // @[el2_lsu_bus_buffer.scala 525:58] + wire _T_4213 = io_lsu_axi_bid == 3'h3; // @[el2_lsu_bus_buffer.scala 523:73] + wire _T_4214 = bus_rsp_write & _T_4213; // @[el2_lsu_bus_buffer.scala 523:52] + wire _T_4215 = io_lsu_axi_rid == 3'h3; // @[el2_lsu_bus_buffer.scala 524:46] + wire [2:0] _GEN_380 = {{1'd0}, buf_ldfwdtag_3}; // @[el2_lsu_bus_buffer.scala 525:47] + wire _T_4217 = io_lsu_axi_rid == _GEN_380; // @[el2_lsu_bus_buffer.scala 525:47] + wire _T_4218 = buf_ldfwd[3] & _T_4217; // @[el2_lsu_bus_buffer.scala 525:27] + wire _T_4219 = _T_4215 | _T_4218; // @[el2_lsu_bus_buffer.scala 524:77] + wire _T_4220 = buf_dual_3 & buf_dualhi_3; // @[el2_lsu_bus_buffer.scala 526:26] + wire _T_4222 = ~buf_write[3]; // @[el2_lsu_bus_buffer.scala 526:44] + wire _T_4223 = _T_4220 & _T_4222; // @[el2_lsu_bus_buffer.scala 526:42] + wire _T_4224 = _T_4223 & buf_samedw_3; // @[el2_lsu_bus_buffer.scala 526:58] reg [1:0] buf_dualtag_3; // @[Reg.scala 27:20] - wire [2:0] _GEN_381 = {{1'd0}, buf_dualtag_3}; // @[el2_lsu_bus_buffer.scala 525:94] - wire _T_4225 = io_lsu_axi_rid == _GEN_381; // @[el2_lsu_bus_buffer.scala 525:94] - wire _T_4226 = _T_4224 & _T_4225; // @[el2_lsu_bus_buffer.scala 525:74] - wire _T_4227 = _T_4219 | _T_4226; // @[el2_lsu_bus_buffer.scala 524:71] - wire _T_4228 = bus_rsp_read & _T_4227; // @[el2_lsu_bus_buffer.scala 523:25] - wire _T_4229 = _T_4214 | _T_4228; // @[el2_lsu_bus_buffer.scala 522:105] + wire [2:0] _GEN_381 = {{1'd0}, buf_dualtag_3}; // @[el2_lsu_bus_buffer.scala 526:94] + wire _T_4225 = io_lsu_axi_rid == _GEN_381; // @[el2_lsu_bus_buffer.scala 526:94] + wire _T_4226 = _T_4224 & _T_4225; // @[el2_lsu_bus_buffer.scala 526:74] + wire _T_4227 = _T_4219 | _T_4226; // @[el2_lsu_bus_buffer.scala 525:71] + wire _T_4228 = bus_rsp_read & _T_4227; // @[el2_lsu_bus_buffer.scala 524:25] + wire _T_4229 = _T_4214 | _T_4228; // @[el2_lsu_bus_buffer.scala 523:105] wire _GEN_270 = _T_4168 & _T_4229; // @[Conditional.scala 39:67] wire _GEN_289 = _T_4134 ? 1'h0 : _GEN_270; // @[Conditional.scala 39:67] wire _GEN_301 = _T_4130 ? 1'h0 : _GEN_289; // @[Conditional.scala 39:67] wire buf_resp_state_bus_en_3 = _T_4107 ? 1'h0 : _GEN_301; // @[Conditional.scala 40:58] wire _T_4255 = 3'h4 == buf_state_3; // @[Conditional.scala 37:30] - wire [3:0] _T_4265 = buf_ldfwd >> buf_dualtag_3; // @[el2_lsu_bus_buffer.scala 537:21] - wire [1:0] _GEN_251 = 2'h1 == buf_dualtag_3 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[el2_lsu_bus_buffer.scala 537:58] - wire [1:0] _GEN_252 = 2'h2 == buf_dualtag_3 ? buf_ldfwdtag_2 : _GEN_251; // @[el2_lsu_bus_buffer.scala 537:58] - wire [1:0] _GEN_253 = 2'h3 == buf_dualtag_3 ? buf_ldfwdtag_3 : _GEN_252; // @[el2_lsu_bus_buffer.scala 537:58] - wire [2:0] _GEN_383 = {{1'd0}, _GEN_253}; // @[el2_lsu_bus_buffer.scala 537:58] - wire _T_4267 = io_lsu_axi_rid == _GEN_383; // @[el2_lsu_bus_buffer.scala 537:58] - wire _T_4268 = _T_4265[0] & _T_4267; // @[el2_lsu_bus_buffer.scala 537:38] - wire _T_4269 = _T_4225 | _T_4268; // @[el2_lsu_bus_buffer.scala 536:95] - wire _T_4270 = bus_rsp_read & _T_4269; // @[el2_lsu_bus_buffer.scala 536:45] + wire [3:0] _T_4265 = buf_ldfwd >> buf_dualtag_3; // @[el2_lsu_bus_buffer.scala 538:21] + wire [1:0] _GEN_251 = 2'h1 == buf_dualtag_3 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[el2_lsu_bus_buffer.scala 538:58] + wire [1:0] _GEN_252 = 2'h2 == buf_dualtag_3 ? buf_ldfwdtag_2 : _GEN_251; // @[el2_lsu_bus_buffer.scala 538:58] + wire [1:0] _GEN_253 = 2'h3 == buf_dualtag_3 ? buf_ldfwdtag_3 : _GEN_252; // @[el2_lsu_bus_buffer.scala 538:58] + wire [2:0] _GEN_383 = {{1'd0}, _GEN_253}; // @[el2_lsu_bus_buffer.scala 538:58] + wire _T_4267 = io_lsu_axi_rid == _GEN_383; // @[el2_lsu_bus_buffer.scala 538:58] + wire _T_4268 = _T_4265[0] & _T_4267; // @[el2_lsu_bus_buffer.scala 538:38] + wire _T_4269 = _T_4225 | _T_4268; // @[el2_lsu_bus_buffer.scala 537:95] + wire _T_4270 = bus_rsp_read & _T_4269; // @[el2_lsu_bus_buffer.scala 537:45] wire _GEN_264 = _T_4255 & _T_4270; // @[Conditional.scala 39:67] wire _GEN_271 = _T_4168 ? buf_resp_state_bus_en_3 : _GEN_264; // @[Conditional.scala 39:67] wire _GEN_281 = _T_4134 ? buf_cmd_state_bus_en_3 : _GEN_271; // @[Conditional.scala 39:67] wire _GEN_294 = _T_4130 ? 1'h0 : _GEN_281; // @[Conditional.scala 39:67] wire buf_state_bus_en_3 = _T_4107 ? 1'h0 : _GEN_294; // @[Conditional.scala 40:58] - wire _T_4147 = buf_state_bus_en_3 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 510:49] - wire _T_4148 = _T_4147 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 510:70] + wire _T_4147 = buf_state_bus_en_3 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 511:49] + wire _T_4148 = _T_4147 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 511:70] wire _T_4273 = 3'h5 == buf_state_3; // @[Conditional.scala 37:30] - wire _T_4276 = RspPtr == 2'h3; // @[el2_lsu_bus_buffer.scala 542:37] - wire _T_4277 = buf_dualtag_3 == RspPtr; // @[el2_lsu_bus_buffer.scala 542:98] - wire _T_4278 = buf_dual_3 & _T_4277; // @[el2_lsu_bus_buffer.scala 542:80] - wire _T_4279 = _T_4276 | _T_4278; // @[el2_lsu_bus_buffer.scala 542:65] - wire _T_4280 = _T_4279 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 542:112] + wire _T_4276 = RspPtr == 2'h3; // @[el2_lsu_bus_buffer.scala 543:37] + wire _T_4277 = buf_dualtag_3 == RspPtr; // @[el2_lsu_bus_buffer.scala 543:98] + wire _T_4278 = buf_dual_3 & _T_4277; // @[el2_lsu_bus_buffer.scala 543:80] + wire _T_4279 = _T_4276 | _T_4278; // @[el2_lsu_bus_buffer.scala 543:65] + wire _T_4280 = _T_4279 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 543:112] wire _T_4281 = 3'h6 == buf_state_3; // @[Conditional.scala 37:30] wire _GEN_259 = _T_4273 ? _T_4280 : _T_4281; // @[Conditional.scala 39:67] wire _GEN_265 = _T_4255 ? _T_4148 : _GEN_259; // @[Conditional.scala 39:67] @@ -1906,228 +1951,228 @@ module el2_lsu_bus_buffer( wire _GEN_282 = _T_4134 ? _T_4148 : _GEN_272; // @[Conditional.scala 39:67] wire _GEN_292 = _T_4130 ? _T_3554 : _GEN_282; // @[Conditional.scala 39:67] wire buf_state_en_3 = _T_4107 ? _T_4123 : _GEN_292; // @[Conditional.scala 40:58] - wire _T_2435 = _T_1886 & buf_state_en_3; // @[el2_lsu_bus_buffer.scala 459:94] - wire _T_2445 = _T_2137 & _T_1889; // @[el2_lsu_bus_buffer.scala 461:71] - wire _T_2447 = _T_2445 & _T_1854; // @[el2_lsu_bus_buffer.scala 461:92] - wire _T_2448 = _T_4471 | _T_2447; // @[el2_lsu_bus_buffer.scala 460:86] - wire _T_2452 = _T_2144 & _T_1890; // @[el2_lsu_bus_buffer.scala 462:52] - wire _T_2454 = _T_2452 & _T_1856; // @[el2_lsu_bus_buffer.scala 462:73] - wire _T_2455 = _T_2448 | _T_2454; // @[el2_lsu_bus_buffer.scala 461:114] - wire _T_2456 = _T_2435 & _T_2455; // @[el2_lsu_bus_buffer.scala 459:113] - wire _T_2458 = _T_2456 | buf_age_3[0]; // @[el2_lsu_bus_buffer.scala 462:97] - wire _T_2472 = _T_2445 & _T_1865; // @[el2_lsu_bus_buffer.scala 461:92] - wire _T_2473 = _T_4476 | _T_2472; // @[el2_lsu_bus_buffer.scala 460:86] - wire _T_2479 = _T_2452 & _T_1867; // @[el2_lsu_bus_buffer.scala 462:73] - wire _T_2480 = _T_2473 | _T_2479; // @[el2_lsu_bus_buffer.scala 461:114] - wire _T_2481 = _T_2435 & _T_2480; // @[el2_lsu_bus_buffer.scala 459:113] - wire _T_2483 = _T_2481 | buf_age_3[1]; // @[el2_lsu_bus_buffer.scala 462:97] - wire _T_2497 = _T_2445 & _T_1876; // @[el2_lsu_bus_buffer.scala 461:92] - wire _T_2498 = _T_4481 | _T_2497; // @[el2_lsu_bus_buffer.scala 460:86] - wire _T_2504 = _T_2452 & _T_1878; // @[el2_lsu_bus_buffer.scala 462:73] - wire _T_2505 = _T_2498 | _T_2504; // @[el2_lsu_bus_buffer.scala 461:114] - wire _T_2506 = _T_2435 & _T_2505; // @[el2_lsu_bus_buffer.scala 459:113] - wire _T_2508 = _T_2506 | buf_age_3[2]; // @[el2_lsu_bus_buffer.scala 462:97] - wire _T_2522 = _T_2445 & _T_1887; // @[el2_lsu_bus_buffer.scala 461:92] - wire _T_2523 = _T_4486 | _T_2522; // @[el2_lsu_bus_buffer.scala 460:86] - wire _T_2529 = _T_2452 & _T_1889; // @[el2_lsu_bus_buffer.scala 462:73] - wire _T_2530 = _T_2523 | _T_2529; // @[el2_lsu_bus_buffer.scala 461:114] - wire _T_2531 = _T_2435 & _T_2530; // @[el2_lsu_bus_buffer.scala 459:113] - wire _T_2533 = _T_2531 | buf_age_3[3]; // @[el2_lsu_bus_buffer.scala 462:97] + wire _T_2435 = _T_1886 & buf_state_en_3; // @[el2_lsu_bus_buffer.scala 460:94] + wire _T_2445 = _T_2137 & _T_1889; // @[el2_lsu_bus_buffer.scala 462:71] + wire _T_2447 = _T_2445 & _T_1854; // @[el2_lsu_bus_buffer.scala 462:92] + wire _T_2448 = _T_4471 | _T_2447; // @[el2_lsu_bus_buffer.scala 461:86] + wire _T_2452 = _T_2144 & _T_1890; // @[el2_lsu_bus_buffer.scala 463:52] + wire _T_2454 = _T_2452 & _T_1856; // @[el2_lsu_bus_buffer.scala 463:73] + wire _T_2455 = _T_2448 | _T_2454; // @[el2_lsu_bus_buffer.scala 462:114] + wire _T_2456 = _T_2435 & _T_2455; // @[el2_lsu_bus_buffer.scala 460:113] + wire _T_2458 = _T_2456 | buf_age_3[0]; // @[el2_lsu_bus_buffer.scala 463:97] + wire _T_2472 = _T_2445 & _T_1865; // @[el2_lsu_bus_buffer.scala 462:92] + wire _T_2473 = _T_4476 | _T_2472; // @[el2_lsu_bus_buffer.scala 461:86] + wire _T_2479 = _T_2452 & _T_1867; // @[el2_lsu_bus_buffer.scala 463:73] + wire _T_2480 = _T_2473 | _T_2479; // @[el2_lsu_bus_buffer.scala 462:114] + wire _T_2481 = _T_2435 & _T_2480; // @[el2_lsu_bus_buffer.scala 460:113] + wire _T_2483 = _T_2481 | buf_age_3[1]; // @[el2_lsu_bus_buffer.scala 463:97] + wire _T_2497 = _T_2445 & _T_1876; // @[el2_lsu_bus_buffer.scala 462:92] + wire _T_2498 = _T_4481 | _T_2497; // @[el2_lsu_bus_buffer.scala 461:86] + wire _T_2504 = _T_2452 & _T_1878; // @[el2_lsu_bus_buffer.scala 463:73] + wire _T_2505 = _T_2498 | _T_2504; // @[el2_lsu_bus_buffer.scala 462:114] + wire _T_2506 = _T_2435 & _T_2505; // @[el2_lsu_bus_buffer.scala 460:113] + wire _T_2508 = _T_2506 | buf_age_3[2]; // @[el2_lsu_bus_buffer.scala 463:97] + wire _T_2522 = _T_2445 & _T_1887; // @[el2_lsu_bus_buffer.scala 462:92] + wire _T_2523 = _T_4486 | _T_2522; // @[el2_lsu_bus_buffer.scala 461:86] + wire _T_2529 = _T_2452 & _T_1889; // @[el2_lsu_bus_buffer.scala 463:73] + wire _T_2530 = _T_2523 | _T_2529; // @[el2_lsu_bus_buffer.scala 462:114] + wire _T_2531 = _T_2435 & _T_2530; // @[el2_lsu_bus_buffer.scala 460:113] + wire _T_2533 = _T_2531 | buf_age_3[3]; // @[el2_lsu_bus_buffer.scala 463:97] wire [2:0] _T_2535 = {_T_2533,_T_2508,_T_2483}; // @[Cat.scala 29:58] - wire _T_2799 = buf_state_0 == 3'h6; // @[el2_lsu_bus_buffer.scala 470:47] - wire _T_2800 = _T_1853 | _T_2799; // @[el2_lsu_bus_buffer.scala 470:32] - wire _T_2801 = ~_T_2800; // @[el2_lsu_bus_buffer.scala 470:6] - wire _T_2809 = _T_2801 | _T_2141; // @[el2_lsu_bus_buffer.scala 470:59] - wire _T_2816 = _T_2809 | _T_2148; // @[el2_lsu_bus_buffer.scala 471:110] - wire _T_2817 = _T_2129 & _T_2816; // @[el2_lsu_bus_buffer.scala 469:112] - wire _T_2821 = buf_state_1 == 3'h6; // @[el2_lsu_bus_buffer.scala 470:47] - wire _T_2822 = _T_1864 | _T_2821; // @[el2_lsu_bus_buffer.scala 470:32] - wire _T_2823 = ~_T_2822; // @[el2_lsu_bus_buffer.scala 470:6] - wire _T_2831 = _T_2823 | _T_2166; // @[el2_lsu_bus_buffer.scala 470:59] - wire _T_2838 = _T_2831 | _T_2173; // @[el2_lsu_bus_buffer.scala 471:110] - wire _T_2839 = _T_2129 & _T_2838; // @[el2_lsu_bus_buffer.scala 469:112] - wire _T_2843 = buf_state_2 == 3'h6; // @[el2_lsu_bus_buffer.scala 470:47] - wire _T_2844 = _T_1875 | _T_2843; // @[el2_lsu_bus_buffer.scala 470:32] - wire _T_2845 = ~_T_2844; // @[el2_lsu_bus_buffer.scala 470:6] - wire _T_2853 = _T_2845 | _T_2191; // @[el2_lsu_bus_buffer.scala 470:59] - wire _T_2860 = _T_2853 | _T_2198; // @[el2_lsu_bus_buffer.scala 471:110] - wire _T_2861 = _T_2129 & _T_2860; // @[el2_lsu_bus_buffer.scala 469:112] - wire _T_2865 = buf_state_3 == 3'h6; // @[el2_lsu_bus_buffer.scala 470:47] - wire _T_2866 = _T_1886 | _T_2865; // @[el2_lsu_bus_buffer.scala 470:32] - wire _T_2867 = ~_T_2866; // @[el2_lsu_bus_buffer.scala 470:6] - wire _T_2875 = _T_2867 | _T_2216; // @[el2_lsu_bus_buffer.scala 470:59] - wire _T_2882 = _T_2875 | _T_2223; // @[el2_lsu_bus_buffer.scala 471:110] - wire _T_2883 = _T_2129 & _T_2882; // @[el2_lsu_bus_buffer.scala 469:112] + wire _T_2799 = buf_state_0 == 3'h6; // @[el2_lsu_bus_buffer.scala 471:47] + wire _T_2800 = _T_1853 | _T_2799; // @[el2_lsu_bus_buffer.scala 471:32] + wire _T_2801 = ~_T_2800; // @[el2_lsu_bus_buffer.scala 471:6] + wire _T_2809 = _T_2801 | _T_2141; // @[el2_lsu_bus_buffer.scala 471:59] + wire _T_2816 = _T_2809 | _T_2148; // @[el2_lsu_bus_buffer.scala 472:110] + wire _T_2817 = _T_2129 & _T_2816; // @[el2_lsu_bus_buffer.scala 470:112] + wire _T_2821 = buf_state_1 == 3'h6; // @[el2_lsu_bus_buffer.scala 471:47] + wire _T_2822 = _T_1864 | _T_2821; // @[el2_lsu_bus_buffer.scala 471:32] + wire _T_2823 = ~_T_2822; // @[el2_lsu_bus_buffer.scala 471:6] + wire _T_2831 = _T_2823 | _T_2166; // @[el2_lsu_bus_buffer.scala 471:59] + wire _T_2838 = _T_2831 | _T_2173; // @[el2_lsu_bus_buffer.scala 472:110] + wire _T_2839 = _T_2129 & _T_2838; // @[el2_lsu_bus_buffer.scala 470:112] + wire _T_2843 = buf_state_2 == 3'h6; // @[el2_lsu_bus_buffer.scala 471:47] + wire _T_2844 = _T_1875 | _T_2843; // @[el2_lsu_bus_buffer.scala 471:32] + wire _T_2845 = ~_T_2844; // @[el2_lsu_bus_buffer.scala 471:6] + wire _T_2853 = _T_2845 | _T_2191; // @[el2_lsu_bus_buffer.scala 471:59] + wire _T_2860 = _T_2853 | _T_2198; // @[el2_lsu_bus_buffer.scala 472:110] + wire _T_2861 = _T_2129 & _T_2860; // @[el2_lsu_bus_buffer.scala 470:112] + wire _T_2865 = buf_state_3 == 3'h6; // @[el2_lsu_bus_buffer.scala 471:47] + wire _T_2866 = _T_1886 | _T_2865; // @[el2_lsu_bus_buffer.scala 471:32] + wire _T_2867 = ~_T_2866; // @[el2_lsu_bus_buffer.scala 471:6] + wire _T_2875 = _T_2867 | _T_2216; // @[el2_lsu_bus_buffer.scala 471:59] + wire _T_2882 = _T_2875 | _T_2223; // @[el2_lsu_bus_buffer.scala 472:110] + wire _T_2883 = _T_2129 & _T_2882; // @[el2_lsu_bus_buffer.scala 470:112] wire [3:0] buf_rspage_set_0 = {_T_2883,_T_2861,_T_2839,_T_2817}; // @[Cat.scala 29:58] - wire _T_2900 = _T_2801 | _T_2243; // @[el2_lsu_bus_buffer.scala 470:59] - wire _T_2907 = _T_2900 | _T_2250; // @[el2_lsu_bus_buffer.scala 471:110] - wire _T_2908 = _T_2231 & _T_2907; // @[el2_lsu_bus_buffer.scala 469:112] - wire _T_2922 = _T_2823 | _T_2268; // @[el2_lsu_bus_buffer.scala 470:59] - wire _T_2929 = _T_2922 | _T_2275; // @[el2_lsu_bus_buffer.scala 471:110] - wire _T_2930 = _T_2231 & _T_2929; // @[el2_lsu_bus_buffer.scala 469:112] - wire _T_2944 = _T_2845 | _T_2293; // @[el2_lsu_bus_buffer.scala 470:59] - wire _T_2951 = _T_2944 | _T_2300; // @[el2_lsu_bus_buffer.scala 471:110] - wire _T_2952 = _T_2231 & _T_2951; // @[el2_lsu_bus_buffer.scala 469:112] - wire _T_2966 = _T_2867 | _T_2318; // @[el2_lsu_bus_buffer.scala 470:59] - wire _T_2973 = _T_2966 | _T_2325; // @[el2_lsu_bus_buffer.scala 471:110] - wire _T_2974 = _T_2231 & _T_2973; // @[el2_lsu_bus_buffer.scala 469:112] + wire _T_2900 = _T_2801 | _T_2243; // @[el2_lsu_bus_buffer.scala 471:59] + wire _T_2907 = _T_2900 | _T_2250; // @[el2_lsu_bus_buffer.scala 472:110] + wire _T_2908 = _T_2231 & _T_2907; // @[el2_lsu_bus_buffer.scala 470:112] + wire _T_2922 = _T_2823 | _T_2268; // @[el2_lsu_bus_buffer.scala 471:59] + wire _T_2929 = _T_2922 | _T_2275; // @[el2_lsu_bus_buffer.scala 472:110] + wire _T_2930 = _T_2231 & _T_2929; // @[el2_lsu_bus_buffer.scala 470:112] + wire _T_2944 = _T_2845 | _T_2293; // @[el2_lsu_bus_buffer.scala 471:59] + wire _T_2951 = _T_2944 | _T_2300; // @[el2_lsu_bus_buffer.scala 472:110] + wire _T_2952 = _T_2231 & _T_2951; // @[el2_lsu_bus_buffer.scala 470:112] + wire _T_2966 = _T_2867 | _T_2318; // @[el2_lsu_bus_buffer.scala 471:59] + wire _T_2973 = _T_2966 | _T_2325; // @[el2_lsu_bus_buffer.scala 472:110] + wire _T_2974 = _T_2231 & _T_2973; // @[el2_lsu_bus_buffer.scala 470:112] wire [3:0] buf_rspage_set_1 = {_T_2974,_T_2952,_T_2930,_T_2908}; // @[Cat.scala 29:58] - wire _T_2991 = _T_2801 | _T_2345; // @[el2_lsu_bus_buffer.scala 470:59] - wire _T_2998 = _T_2991 | _T_2352; // @[el2_lsu_bus_buffer.scala 471:110] - wire _T_2999 = _T_2333 & _T_2998; // @[el2_lsu_bus_buffer.scala 469:112] - wire _T_3013 = _T_2823 | _T_2370; // @[el2_lsu_bus_buffer.scala 470:59] - wire _T_3020 = _T_3013 | _T_2377; // @[el2_lsu_bus_buffer.scala 471:110] - wire _T_3021 = _T_2333 & _T_3020; // @[el2_lsu_bus_buffer.scala 469:112] - wire _T_3035 = _T_2845 | _T_2395; // @[el2_lsu_bus_buffer.scala 470:59] - wire _T_3042 = _T_3035 | _T_2402; // @[el2_lsu_bus_buffer.scala 471:110] - wire _T_3043 = _T_2333 & _T_3042; // @[el2_lsu_bus_buffer.scala 469:112] - wire _T_3057 = _T_2867 | _T_2420; // @[el2_lsu_bus_buffer.scala 470:59] - wire _T_3064 = _T_3057 | _T_2427; // @[el2_lsu_bus_buffer.scala 471:110] - wire _T_3065 = _T_2333 & _T_3064; // @[el2_lsu_bus_buffer.scala 469:112] + wire _T_2991 = _T_2801 | _T_2345; // @[el2_lsu_bus_buffer.scala 471:59] + wire _T_2998 = _T_2991 | _T_2352; // @[el2_lsu_bus_buffer.scala 472:110] + wire _T_2999 = _T_2333 & _T_2998; // @[el2_lsu_bus_buffer.scala 470:112] + wire _T_3013 = _T_2823 | _T_2370; // @[el2_lsu_bus_buffer.scala 471:59] + wire _T_3020 = _T_3013 | _T_2377; // @[el2_lsu_bus_buffer.scala 472:110] + wire _T_3021 = _T_2333 & _T_3020; // @[el2_lsu_bus_buffer.scala 470:112] + wire _T_3035 = _T_2845 | _T_2395; // @[el2_lsu_bus_buffer.scala 471:59] + wire _T_3042 = _T_3035 | _T_2402; // @[el2_lsu_bus_buffer.scala 472:110] + wire _T_3043 = _T_2333 & _T_3042; // @[el2_lsu_bus_buffer.scala 470:112] + wire _T_3057 = _T_2867 | _T_2420; // @[el2_lsu_bus_buffer.scala 471:59] + wire _T_3064 = _T_3057 | _T_2427; // @[el2_lsu_bus_buffer.scala 472:110] + wire _T_3065 = _T_2333 & _T_3064; // @[el2_lsu_bus_buffer.scala 470:112] wire [3:0] buf_rspage_set_2 = {_T_3065,_T_3043,_T_3021,_T_2999}; // @[Cat.scala 29:58] - wire _T_3082 = _T_2801 | _T_2447; // @[el2_lsu_bus_buffer.scala 470:59] - wire _T_3089 = _T_3082 | _T_2454; // @[el2_lsu_bus_buffer.scala 471:110] - wire _T_3090 = _T_2435 & _T_3089; // @[el2_lsu_bus_buffer.scala 469:112] - wire _T_3104 = _T_2823 | _T_2472; // @[el2_lsu_bus_buffer.scala 470:59] - wire _T_3111 = _T_3104 | _T_2479; // @[el2_lsu_bus_buffer.scala 471:110] - wire _T_3112 = _T_2435 & _T_3111; // @[el2_lsu_bus_buffer.scala 469:112] - wire _T_3126 = _T_2845 | _T_2497; // @[el2_lsu_bus_buffer.scala 470:59] - wire _T_3133 = _T_3126 | _T_2504; // @[el2_lsu_bus_buffer.scala 471:110] - wire _T_3134 = _T_2435 & _T_3133; // @[el2_lsu_bus_buffer.scala 469:112] - wire _T_3148 = _T_2867 | _T_2522; // @[el2_lsu_bus_buffer.scala 470:59] - wire _T_3155 = _T_3148 | _T_2529; // @[el2_lsu_bus_buffer.scala 471:110] - wire _T_3156 = _T_2435 & _T_3155; // @[el2_lsu_bus_buffer.scala 469:112] + wire _T_3082 = _T_2801 | _T_2447; // @[el2_lsu_bus_buffer.scala 471:59] + wire _T_3089 = _T_3082 | _T_2454; // @[el2_lsu_bus_buffer.scala 472:110] + wire _T_3090 = _T_2435 & _T_3089; // @[el2_lsu_bus_buffer.scala 470:112] + wire _T_3104 = _T_2823 | _T_2472; // @[el2_lsu_bus_buffer.scala 471:59] + wire _T_3111 = _T_3104 | _T_2479; // @[el2_lsu_bus_buffer.scala 472:110] + wire _T_3112 = _T_2435 & _T_3111; // @[el2_lsu_bus_buffer.scala 470:112] + wire _T_3126 = _T_2845 | _T_2497; // @[el2_lsu_bus_buffer.scala 471:59] + wire _T_3133 = _T_3126 | _T_2504; // @[el2_lsu_bus_buffer.scala 472:110] + wire _T_3134 = _T_2435 & _T_3133; // @[el2_lsu_bus_buffer.scala 470:112] + wire _T_3148 = _T_2867 | _T_2522; // @[el2_lsu_bus_buffer.scala 471:59] + wire _T_3155 = _T_3148 | _T_2529; // @[el2_lsu_bus_buffer.scala 472:110] + wire _T_3156 = _T_2435 & _T_3155; // @[el2_lsu_bus_buffer.scala 470:112] wire [3:0] buf_rspage_set_3 = {_T_3156,_T_3134,_T_3112,_T_3090}; // @[Cat.scala 29:58] - wire _T_3241 = _T_2865 | _T_1886; // @[el2_lsu_bus_buffer.scala 474:110] - wire _T_3242 = ~_T_3241; // @[el2_lsu_bus_buffer.scala 474:84] - wire _T_3243 = buf_rspageQ_0[3] & _T_3242; // @[el2_lsu_bus_buffer.scala 474:82] - wire _T_3235 = _T_2843 | _T_1875; // @[el2_lsu_bus_buffer.scala 474:110] - wire _T_3236 = ~_T_3235; // @[el2_lsu_bus_buffer.scala 474:84] - wire _T_3237 = buf_rspageQ_0[2] & _T_3236; // @[el2_lsu_bus_buffer.scala 474:82] - wire _T_3229 = _T_2821 | _T_1864; // @[el2_lsu_bus_buffer.scala 474:110] - wire _T_3230 = ~_T_3229; // @[el2_lsu_bus_buffer.scala 474:84] - wire _T_3231 = buf_rspageQ_0[1] & _T_3230; // @[el2_lsu_bus_buffer.scala 474:82] - wire _T_3223 = _T_2799 | _T_1853; // @[el2_lsu_bus_buffer.scala 474:110] - wire _T_3224 = ~_T_3223; // @[el2_lsu_bus_buffer.scala 474:84] - wire _T_3225 = buf_rspageQ_0[0] & _T_3224; // @[el2_lsu_bus_buffer.scala 474:82] + wire _T_3241 = _T_2865 | _T_1886; // @[el2_lsu_bus_buffer.scala 475:110] + wire _T_3242 = ~_T_3241; // @[el2_lsu_bus_buffer.scala 475:84] + wire _T_3243 = buf_rspageQ_0[3] & _T_3242; // @[el2_lsu_bus_buffer.scala 475:82] + wire _T_3235 = _T_2843 | _T_1875; // @[el2_lsu_bus_buffer.scala 475:110] + wire _T_3236 = ~_T_3235; // @[el2_lsu_bus_buffer.scala 475:84] + wire _T_3237 = buf_rspageQ_0[2] & _T_3236; // @[el2_lsu_bus_buffer.scala 475:82] + wire _T_3229 = _T_2821 | _T_1864; // @[el2_lsu_bus_buffer.scala 475:110] + wire _T_3230 = ~_T_3229; // @[el2_lsu_bus_buffer.scala 475:84] + wire _T_3231 = buf_rspageQ_0[1] & _T_3230; // @[el2_lsu_bus_buffer.scala 475:82] + wire _T_3223 = _T_2799 | _T_1853; // @[el2_lsu_bus_buffer.scala 475:110] + wire _T_3224 = ~_T_3223; // @[el2_lsu_bus_buffer.scala 475:84] + wire _T_3225 = buf_rspageQ_0[0] & _T_3224; // @[el2_lsu_bus_buffer.scala 475:82] wire [3:0] buf_rspage_0 = {_T_3243,_T_3237,_T_3231,_T_3225}; // @[Cat.scala 29:58] - wire _T_3162 = buf_rspage_set_0[0] | buf_rspage_0[0]; // @[el2_lsu_bus_buffer.scala 473:88] - wire _T_3165 = buf_rspage_set_0[1] | buf_rspage_0[1]; // @[el2_lsu_bus_buffer.scala 473:88] - wire _T_3168 = buf_rspage_set_0[2] | buf_rspage_0[2]; // @[el2_lsu_bus_buffer.scala 473:88] - wire _T_3171 = buf_rspage_set_0[3] | buf_rspage_0[3]; // @[el2_lsu_bus_buffer.scala 473:88] + wire _T_3162 = buf_rspage_set_0[0] | buf_rspage_0[0]; // @[el2_lsu_bus_buffer.scala 474:88] + wire _T_3165 = buf_rspage_set_0[1] | buf_rspage_0[1]; // @[el2_lsu_bus_buffer.scala 474:88] + wire _T_3168 = buf_rspage_set_0[2] | buf_rspage_0[2]; // @[el2_lsu_bus_buffer.scala 474:88] + wire _T_3171 = buf_rspage_set_0[3] | buf_rspage_0[3]; // @[el2_lsu_bus_buffer.scala 474:88] wire [2:0] _T_3173 = {_T_3171,_T_3168,_T_3165}; // @[Cat.scala 29:58] - wire _T_3270 = buf_rspageQ_1[3] & _T_3242; // @[el2_lsu_bus_buffer.scala 474:82] - wire _T_3264 = buf_rspageQ_1[2] & _T_3236; // @[el2_lsu_bus_buffer.scala 474:82] - wire _T_3258 = buf_rspageQ_1[1] & _T_3230; // @[el2_lsu_bus_buffer.scala 474:82] - wire _T_3252 = buf_rspageQ_1[0] & _T_3224; // @[el2_lsu_bus_buffer.scala 474:82] + wire _T_3270 = buf_rspageQ_1[3] & _T_3242; // @[el2_lsu_bus_buffer.scala 475:82] + wire _T_3264 = buf_rspageQ_1[2] & _T_3236; // @[el2_lsu_bus_buffer.scala 475:82] + wire _T_3258 = buf_rspageQ_1[1] & _T_3230; // @[el2_lsu_bus_buffer.scala 475:82] + wire _T_3252 = buf_rspageQ_1[0] & _T_3224; // @[el2_lsu_bus_buffer.scala 475:82] wire [3:0] buf_rspage_1 = {_T_3270,_T_3264,_T_3258,_T_3252}; // @[Cat.scala 29:58] - wire _T_3177 = buf_rspage_set_1[0] | buf_rspage_1[0]; // @[el2_lsu_bus_buffer.scala 473:88] - wire _T_3180 = buf_rspage_set_1[1] | buf_rspage_1[1]; // @[el2_lsu_bus_buffer.scala 473:88] - wire _T_3183 = buf_rspage_set_1[2] | buf_rspage_1[2]; // @[el2_lsu_bus_buffer.scala 473:88] - wire _T_3186 = buf_rspage_set_1[3] | buf_rspage_1[3]; // @[el2_lsu_bus_buffer.scala 473:88] + wire _T_3177 = buf_rspage_set_1[0] | buf_rspage_1[0]; // @[el2_lsu_bus_buffer.scala 474:88] + wire _T_3180 = buf_rspage_set_1[1] | buf_rspage_1[1]; // @[el2_lsu_bus_buffer.scala 474:88] + wire _T_3183 = buf_rspage_set_1[2] | buf_rspage_1[2]; // @[el2_lsu_bus_buffer.scala 474:88] + wire _T_3186 = buf_rspage_set_1[3] | buf_rspage_1[3]; // @[el2_lsu_bus_buffer.scala 474:88] wire [2:0] _T_3188 = {_T_3186,_T_3183,_T_3180}; // @[Cat.scala 29:58] - wire _T_3297 = buf_rspageQ_2[3] & _T_3242; // @[el2_lsu_bus_buffer.scala 474:82] - wire _T_3291 = buf_rspageQ_2[2] & _T_3236; // @[el2_lsu_bus_buffer.scala 474:82] - wire _T_3285 = buf_rspageQ_2[1] & _T_3230; // @[el2_lsu_bus_buffer.scala 474:82] - wire _T_3279 = buf_rspageQ_2[0] & _T_3224; // @[el2_lsu_bus_buffer.scala 474:82] + wire _T_3297 = buf_rspageQ_2[3] & _T_3242; // @[el2_lsu_bus_buffer.scala 475:82] + wire _T_3291 = buf_rspageQ_2[2] & _T_3236; // @[el2_lsu_bus_buffer.scala 475:82] + wire _T_3285 = buf_rspageQ_2[1] & _T_3230; // @[el2_lsu_bus_buffer.scala 475:82] + wire _T_3279 = buf_rspageQ_2[0] & _T_3224; // @[el2_lsu_bus_buffer.scala 475:82] wire [3:0] buf_rspage_2 = {_T_3297,_T_3291,_T_3285,_T_3279}; // @[Cat.scala 29:58] - wire _T_3192 = buf_rspage_set_2[0] | buf_rspage_2[0]; // @[el2_lsu_bus_buffer.scala 473:88] - wire _T_3195 = buf_rspage_set_2[1] | buf_rspage_2[1]; // @[el2_lsu_bus_buffer.scala 473:88] - wire _T_3198 = buf_rspage_set_2[2] | buf_rspage_2[2]; // @[el2_lsu_bus_buffer.scala 473:88] - wire _T_3201 = buf_rspage_set_2[3] | buf_rspage_2[3]; // @[el2_lsu_bus_buffer.scala 473:88] + wire _T_3192 = buf_rspage_set_2[0] | buf_rspage_2[0]; // @[el2_lsu_bus_buffer.scala 474:88] + wire _T_3195 = buf_rspage_set_2[1] | buf_rspage_2[1]; // @[el2_lsu_bus_buffer.scala 474:88] + wire _T_3198 = buf_rspage_set_2[2] | buf_rspage_2[2]; // @[el2_lsu_bus_buffer.scala 474:88] + wire _T_3201 = buf_rspage_set_2[3] | buf_rspage_2[3]; // @[el2_lsu_bus_buffer.scala 474:88] wire [2:0] _T_3203 = {_T_3201,_T_3198,_T_3195}; // @[Cat.scala 29:58] - wire _T_3324 = buf_rspageQ_3[3] & _T_3242; // @[el2_lsu_bus_buffer.scala 474:82] - wire _T_3318 = buf_rspageQ_3[2] & _T_3236; // @[el2_lsu_bus_buffer.scala 474:82] - wire _T_3312 = buf_rspageQ_3[1] & _T_3230; // @[el2_lsu_bus_buffer.scala 474:82] - wire _T_3306 = buf_rspageQ_3[0] & _T_3224; // @[el2_lsu_bus_buffer.scala 474:82] + wire _T_3324 = buf_rspageQ_3[3] & _T_3242; // @[el2_lsu_bus_buffer.scala 475:82] + wire _T_3318 = buf_rspageQ_3[2] & _T_3236; // @[el2_lsu_bus_buffer.scala 475:82] + wire _T_3312 = buf_rspageQ_3[1] & _T_3230; // @[el2_lsu_bus_buffer.scala 475:82] + wire _T_3306 = buf_rspageQ_3[0] & _T_3224; // @[el2_lsu_bus_buffer.scala 475:82] wire [3:0] buf_rspage_3 = {_T_3324,_T_3318,_T_3312,_T_3306}; // @[Cat.scala 29:58] - wire _T_3207 = buf_rspage_set_3[0] | buf_rspage_3[0]; // @[el2_lsu_bus_buffer.scala 473:88] - wire _T_3210 = buf_rspage_set_3[1] | buf_rspage_3[1]; // @[el2_lsu_bus_buffer.scala 473:88] - wire _T_3213 = buf_rspage_set_3[2] | buf_rspage_3[2]; // @[el2_lsu_bus_buffer.scala 473:88] - wire _T_3216 = buf_rspage_set_3[3] | buf_rspage_3[3]; // @[el2_lsu_bus_buffer.scala 473:88] + wire _T_3207 = buf_rspage_set_3[0] | buf_rspage_3[0]; // @[el2_lsu_bus_buffer.scala 474:88] + wire _T_3210 = buf_rspage_set_3[1] | buf_rspage_3[1]; // @[el2_lsu_bus_buffer.scala 474:88] + wire _T_3213 = buf_rspage_set_3[2] | buf_rspage_3[2]; // @[el2_lsu_bus_buffer.scala 474:88] + wire _T_3216 = buf_rspage_set_3[3] | buf_rspage_3[3]; // @[el2_lsu_bus_buffer.scala 474:88] wire [2:0] _T_3218 = {_T_3216,_T_3213,_T_3210}; // @[Cat.scala 29:58] - wire _T_3329 = ibuf_drain_vld & _T_1854; // @[el2_lsu_bus_buffer.scala 479:63] - wire _T_3331 = ibuf_drain_vld & _T_1865; // @[el2_lsu_bus_buffer.scala 479:63] - wire _T_3333 = ibuf_drain_vld & _T_1876; // @[el2_lsu_bus_buffer.scala 479:63] - wire _T_3335 = ibuf_drain_vld & _T_1887; // @[el2_lsu_bus_buffer.scala 479:63] + wire _T_3329 = ibuf_drain_vld & _T_1854; // @[el2_lsu_bus_buffer.scala 480:63] + wire _T_3331 = ibuf_drain_vld & _T_1865; // @[el2_lsu_bus_buffer.scala 480:63] + wire _T_3333 = ibuf_drain_vld & _T_1876; // @[el2_lsu_bus_buffer.scala 480:63] + wire _T_3335 = ibuf_drain_vld & _T_1887; // @[el2_lsu_bus_buffer.scala 480:63] wire [3:0] ibuf_drainvec_vld = {_T_3335,_T_3333,_T_3331,_T_3329}; // @[Cat.scala 29:58] - wire _T_3343 = _T_3537 & _T_1857; // @[el2_lsu_bus_buffer.scala 481:35] - wire _T_3352 = _T_3537 & _T_1868; // @[el2_lsu_bus_buffer.scala 481:35] - wire _T_3361 = _T_3537 & _T_1879; // @[el2_lsu_bus_buffer.scala 481:35] - wire _T_3370 = _T_3537 & _T_1890; // @[el2_lsu_bus_buffer.scala 481:35] - wire _T_3400 = ibuf_drainvec_vld[0] ? ibuf_dual : io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 483:45] - wire _T_3402 = ibuf_drainvec_vld[1] ? ibuf_dual : io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 483:45] - wire _T_3404 = ibuf_drainvec_vld[2] ? ibuf_dual : io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 483:45] - wire _T_3406 = ibuf_drainvec_vld[3] ? ibuf_dual : io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 483:45] + wire _T_3343 = _T_3537 & _T_1857; // @[el2_lsu_bus_buffer.scala 482:35] + wire _T_3352 = _T_3537 & _T_1868; // @[el2_lsu_bus_buffer.scala 482:35] + wire _T_3361 = _T_3537 & _T_1879; // @[el2_lsu_bus_buffer.scala 482:35] + wire _T_3370 = _T_3537 & _T_1890; // @[el2_lsu_bus_buffer.scala 482:35] + wire _T_3400 = ibuf_drainvec_vld[0] ? ibuf_dual : io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 484:45] + wire _T_3402 = ibuf_drainvec_vld[1] ? ibuf_dual : io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 484:45] + wire _T_3404 = ibuf_drainvec_vld[2] ? ibuf_dual : io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 484:45] + wire _T_3406 = ibuf_drainvec_vld[3] ? ibuf_dual : io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 484:45] wire [3:0] buf_dual_in = {_T_3406,_T_3404,_T_3402,_T_3400}; // @[Cat.scala 29:58] - wire _T_3411 = ibuf_drainvec_vld[0] ? ibuf_samedw : ldst_samedw_r; // @[el2_lsu_bus_buffer.scala 484:47] - wire _T_3413 = ibuf_drainvec_vld[1] ? ibuf_samedw : ldst_samedw_r; // @[el2_lsu_bus_buffer.scala 484:47] - wire _T_3415 = ibuf_drainvec_vld[2] ? ibuf_samedw : ldst_samedw_r; // @[el2_lsu_bus_buffer.scala 484:47] - wire _T_3417 = ibuf_drainvec_vld[3] ? ibuf_samedw : ldst_samedw_r; // @[el2_lsu_bus_buffer.scala 484:47] + wire _T_3411 = ibuf_drainvec_vld[0] ? ibuf_samedw : ldst_samedw_r; // @[el2_lsu_bus_buffer.scala 485:47] + wire _T_3413 = ibuf_drainvec_vld[1] ? ibuf_samedw : ldst_samedw_r; // @[el2_lsu_bus_buffer.scala 485:47] + wire _T_3415 = ibuf_drainvec_vld[2] ? ibuf_samedw : ldst_samedw_r; // @[el2_lsu_bus_buffer.scala 485:47] + wire _T_3417 = ibuf_drainvec_vld[3] ? ibuf_samedw : ldst_samedw_r; // @[el2_lsu_bus_buffer.scala 485:47] wire [3:0] buf_samedw_in = {_T_3417,_T_3415,_T_3413,_T_3411}; // @[Cat.scala 29:58] - wire _T_3422 = ibuf_nomerge | ibuf_force_drain; // @[el2_lsu_bus_buffer.scala 485:84] - wire _T_3423 = ibuf_drainvec_vld[0] ? _T_3422 : io_no_dword_merge_r; // @[el2_lsu_bus_buffer.scala 485:48] - wire _T_3426 = ibuf_drainvec_vld[1] ? _T_3422 : io_no_dword_merge_r; // @[el2_lsu_bus_buffer.scala 485:48] - wire _T_3429 = ibuf_drainvec_vld[2] ? _T_3422 : io_no_dword_merge_r; // @[el2_lsu_bus_buffer.scala 485:48] - wire _T_3432 = ibuf_drainvec_vld[3] ? _T_3422 : io_no_dword_merge_r; // @[el2_lsu_bus_buffer.scala 485:48] + wire _T_3422 = ibuf_nomerge | ibuf_force_drain; // @[el2_lsu_bus_buffer.scala 486:84] + wire _T_3423 = ibuf_drainvec_vld[0] ? _T_3422 : io_no_dword_merge_r; // @[el2_lsu_bus_buffer.scala 486:48] + wire _T_3426 = ibuf_drainvec_vld[1] ? _T_3422 : io_no_dword_merge_r; // @[el2_lsu_bus_buffer.scala 486:48] + wire _T_3429 = ibuf_drainvec_vld[2] ? _T_3422 : io_no_dword_merge_r; // @[el2_lsu_bus_buffer.scala 486:48] + wire _T_3432 = ibuf_drainvec_vld[3] ? _T_3422 : io_no_dword_merge_r; // @[el2_lsu_bus_buffer.scala 486:48] wire [3:0] buf_nomerge_in = {_T_3432,_T_3429,_T_3426,_T_3423}; // @[Cat.scala 29:58] - wire _T_3440 = ibuf_drainvec_vld[0] ? ibuf_dual : _T_3343; // @[el2_lsu_bus_buffer.scala 486:47] - wire _T_3445 = ibuf_drainvec_vld[1] ? ibuf_dual : _T_3352; // @[el2_lsu_bus_buffer.scala 486:47] - wire _T_3450 = ibuf_drainvec_vld[2] ? ibuf_dual : _T_3361; // @[el2_lsu_bus_buffer.scala 486:47] - wire _T_3455 = ibuf_drainvec_vld[3] ? ibuf_dual : _T_3370; // @[el2_lsu_bus_buffer.scala 486:47] + wire _T_3440 = ibuf_drainvec_vld[0] ? ibuf_dual : _T_3343; // @[el2_lsu_bus_buffer.scala 487:47] + wire _T_3445 = ibuf_drainvec_vld[1] ? ibuf_dual : _T_3352; // @[el2_lsu_bus_buffer.scala 487:47] + wire _T_3450 = ibuf_drainvec_vld[2] ? ibuf_dual : _T_3361; // @[el2_lsu_bus_buffer.scala 487:47] + wire _T_3455 = ibuf_drainvec_vld[3] ? ibuf_dual : _T_3370; // @[el2_lsu_bus_buffer.scala 487:47] wire [3:0] buf_dualhi_in = {_T_3455,_T_3450,_T_3445,_T_3440}; // @[Cat.scala 29:58] - wire _T_3484 = ibuf_drainvec_vld[0] ? ibuf_sideeffect : io_is_sideeffects_r; // @[el2_lsu_bus_buffer.scala 488:51] - wire _T_3486 = ibuf_drainvec_vld[1] ? ibuf_sideeffect : io_is_sideeffects_r; // @[el2_lsu_bus_buffer.scala 488:51] - wire _T_3488 = ibuf_drainvec_vld[2] ? ibuf_sideeffect : io_is_sideeffects_r; // @[el2_lsu_bus_buffer.scala 488:51] - wire _T_3490 = ibuf_drainvec_vld[3] ? ibuf_sideeffect : io_is_sideeffects_r; // @[el2_lsu_bus_buffer.scala 488:51] + wire _T_3484 = ibuf_drainvec_vld[0] ? ibuf_sideeffect : io_is_sideeffects_r; // @[el2_lsu_bus_buffer.scala 489:51] + wire _T_3486 = ibuf_drainvec_vld[1] ? ibuf_sideeffect : io_is_sideeffects_r; // @[el2_lsu_bus_buffer.scala 489:51] + wire _T_3488 = ibuf_drainvec_vld[2] ? ibuf_sideeffect : io_is_sideeffects_r; // @[el2_lsu_bus_buffer.scala 489:51] + wire _T_3490 = ibuf_drainvec_vld[3] ? ibuf_sideeffect : io_is_sideeffects_r; // @[el2_lsu_bus_buffer.scala 489:51] wire [3:0] buf_sideeffect_in = {_T_3490,_T_3488,_T_3486,_T_3484}; // @[Cat.scala 29:58] - wire _T_3495 = ibuf_drainvec_vld[0] ? ibuf_unsign : io_lsu_pkt_r_unsign; // @[el2_lsu_bus_buffer.scala 489:47] - wire _T_3497 = ibuf_drainvec_vld[1] ? ibuf_unsign : io_lsu_pkt_r_unsign; // @[el2_lsu_bus_buffer.scala 489:47] - wire _T_3499 = ibuf_drainvec_vld[2] ? ibuf_unsign : io_lsu_pkt_r_unsign; // @[el2_lsu_bus_buffer.scala 489:47] - wire _T_3501 = ibuf_drainvec_vld[3] ? ibuf_unsign : io_lsu_pkt_r_unsign; // @[el2_lsu_bus_buffer.scala 489:47] + wire _T_3495 = ibuf_drainvec_vld[0] ? ibuf_unsign : io_lsu_pkt_r_bits_unsign; // @[el2_lsu_bus_buffer.scala 490:47] + wire _T_3497 = ibuf_drainvec_vld[1] ? ibuf_unsign : io_lsu_pkt_r_bits_unsign; // @[el2_lsu_bus_buffer.scala 490:47] + wire _T_3499 = ibuf_drainvec_vld[2] ? ibuf_unsign : io_lsu_pkt_r_bits_unsign; // @[el2_lsu_bus_buffer.scala 490:47] + wire _T_3501 = ibuf_drainvec_vld[3] ? ibuf_unsign : io_lsu_pkt_r_bits_unsign; // @[el2_lsu_bus_buffer.scala 490:47] wire [3:0] buf_unsign_in = {_T_3501,_T_3499,_T_3497,_T_3495}; // @[Cat.scala 29:58] - wire _T_3518 = ibuf_drainvec_vld[0] ? ibuf_write : io_lsu_pkt_r_store; // @[el2_lsu_bus_buffer.scala 491:46] - wire _T_3520 = ibuf_drainvec_vld[1] ? ibuf_write : io_lsu_pkt_r_store; // @[el2_lsu_bus_buffer.scala 491:46] - wire _T_3522 = ibuf_drainvec_vld[2] ? ibuf_write : io_lsu_pkt_r_store; // @[el2_lsu_bus_buffer.scala 491:46] - wire _T_3524 = ibuf_drainvec_vld[3] ? ibuf_write : io_lsu_pkt_r_store; // @[el2_lsu_bus_buffer.scala 491:46] + wire _T_3518 = ibuf_drainvec_vld[0] ? ibuf_write : io_lsu_pkt_r_bits_store; // @[el2_lsu_bus_buffer.scala 492:46] + wire _T_3520 = ibuf_drainvec_vld[1] ? ibuf_write : io_lsu_pkt_r_bits_store; // @[el2_lsu_bus_buffer.scala 492:46] + wire _T_3522 = ibuf_drainvec_vld[2] ? ibuf_write : io_lsu_pkt_r_bits_store; // @[el2_lsu_bus_buffer.scala 492:46] + wire _T_3524 = ibuf_drainvec_vld[3] ? ibuf_write : io_lsu_pkt_r_bits_store; // @[el2_lsu_bus_buffer.scala 492:46] wire [3:0] buf_write_in = {_T_3524,_T_3522,_T_3520,_T_3518}; // @[Cat.scala 29:58] - wire _T_3557 = obuf_nosend & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 507:89] - wire _T_3559 = _T_3557 & _T_1351; // @[el2_lsu_bus_buffer.scala 507:104] - wire _T_3572 = buf_state_en_0 & _T_3643; // @[el2_lsu_bus_buffer.scala 512:44] - wire _T_3573 = _T_3572 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 512:60] - wire _T_3575 = _T_3573 & _T_1333; // @[el2_lsu_bus_buffer.scala 512:74] - wire _T_3578 = _T_3568 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 514:67] - wire _T_3579 = _T_3578 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 514:81] - wire _T_4869 = io_lsu_axi_bresp != 2'h0; // @[el2_lsu_bus_buffer.scala 618:58] - wire bus_rsp_read_error = bus_rsp_read & _T_4869; // @[el2_lsu_bus_buffer.scala 618:38] - wire _T_3582 = _T_3578 & bus_rsp_read_error; // @[el2_lsu_bus_buffer.scala 515:82] - wire _T_3657 = bus_rsp_read_error & _T_3636; // @[el2_lsu_bus_buffer.scala 529:91] - wire _T_3659 = bus_rsp_read_error & buf_ldfwd[0]; // @[el2_lsu_bus_buffer.scala 530:31] - wire _T_3661 = _T_3659 & _T_3638; // @[el2_lsu_bus_buffer.scala 530:46] - wire _T_3662 = _T_3657 | _T_3661; // @[el2_lsu_bus_buffer.scala 529:143] - wire bus_rsp_write_error = bus_rsp_write & _T_4869; // @[el2_lsu_bus_buffer.scala 617:40] - wire _T_3665 = bus_rsp_write_error & _T_3634; // @[el2_lsu_bus_buffer.scala 531:53] - wire _T_3666 = _T_3662 | _T_3665; // @[el2_lsu_bus_buffer.scala 530:88] - wire _T_3667 = _T_3568 & _T_3666; // @[el2_lsu_bus_buffer.scala 529:68] + wire _T_3557 = obuf_nosend & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 508:89] + wire _T_3559 = _T_3557 & _T_1351; // @[el2_lsu_bus_buffer.scala 508:104] + wire _T_3572 = buf_state_en_0 & _T_3643; // @[el2_lsu_bus_buffer.scala 513:44] + wire _T_3573 = _T_3572 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 513:60] + wire _T_3575 = _T_3573 & _T_1333; // @[el2_lsu_bus_buffer.scala 513:74] + wire _T_3578 = _T_3568 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 515:67] + wire _T_3579 = _T_3578 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 515:81] + wire _T_4869 = io_lsu_axi_bresp != 2'h0; // @[el2_lsu_bus_buffer.scala 619:58] + wire bus_rsp_read_error = bus_rsp_read & _T_4869; // @[el2_lsu_bus_buffer.scala 619:38] + wire _T_3582 = _T_3578 & bus_rsp_read_error; // @[el2_lsu_bus_buffer.scala 516:82] + wire _T_3657 = bus_rsp_read_error & _T_3636; // @[el2_lsu_bus_buffer.scala 530:91] + wire _T_3659 = bus_rsp_read_error & buf_ldfwd[0]; // @[el2_lsu_bus_buffer.scala 531:31] + wire _T_3661 = _T_3659 & _T_3638; // @[el2_lsu_bus_buffer.scala 531:46] + wire _T_3662 = _T_3657 | _T_3661; // @[el2_lsu_bus_buffer.scala 530:143] + wire bus_rsp_write_error = bus_rsp_write & _T_4869; // @[el2_lsu_bus_buffer.scala 618:40] + wire _T_3665 = bus_rsp_write_error & _T_3634; // @[el2_lsu_bus_buffer.scala 532:53] + wire _T_3666 = _T_3662 | _T_3665; // @[el2_lsu_bus_buffer.scala 531:88] + wire _T_3667 = _T_3568 & _T_3666; // @[el2_lsu_bus_buffer.scala 530:68] wire _GEN_46 = _T_3589 & _T_3667; // @[Conditional.scala 39:67] wire _GEN_59 = _T_3555 ? _T_3582 : _GEN_46; // @[Conditional.scala 39:67] wire _GEN_71 = _T_3551 ? 1'h0 : _GEN_59; // @[Conditional.scala 39:67] wire buf_error_en_0 = _T_3528 ? 1'h0 : _GEN_71; // @[Conditional.scala 40:58] - wire _T_3592 = ~bus_rsp_write_error; // @[el2_lsu_bus_buffer.scala 519:73] - wire _T_3593 = buf_write[0] & _T_3592; // @[el2_lsu_bus_buffer.scala 519:71] - wire _T_3594 = io_dec_tlu_force_halt | _T_3593; // @[el2_lsu_bus_buffer.scala 519:55] - wire _T_3596 = ~buf_samedw_0; // @[el2_lsu_bus_buffer.scala 520:30] - wire _T_3597 = buf_dual_0 & _T_3596; // @[el2_lsu_bus_buffer.scala 520:28] - wire _T_3600 = _T_3597 & _T_3643; // @[el2_lsu_bus_buffer.scala 520:45] - wire [2:0] _GEN_19 = 2'h1 == buf_dualtag_0 ? buf_state_1 : buf_state_0; // @[el2_lsu_bus_buffer.scala 520:90] - wire [2:0] _GEN_20 = 2'h2 == buf_dualtag_0 ? buf_state_2 : _GEN_19; // @[el2_lsu_bus_buffer.scala 520:90] - wire [2:0] _GEN_21 = 2'h3 == buf_dualtag_0 ? buf_state_3 : _GEN_20; // @[el2_lsu_bus_buffer.scala 520:90] - wire _T_3601 = _GEN_21 != 3'h4; // @[el2_lsu_bus_buffer.scala 520:90] - wire _T_3602 = _T_3600 & _T_3601; // @[el2_lsu_bus_buffer.scala 520:61] - wire _T_4494 = _T_2746 | _T_2743; // @[el2_lsu_bus_buffer.scala 578:93] - wire _T_4495 = _T_4494 | _T_2740; // @[el2_lsu_bus_buffer.scala 578:93] - wire any_done_wait_state = _T_4495 | _T_2737; // @[el2_lsu_bus_buffer.scala 578:93] - wire _T_3604 = buf_ldfwd[0] | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 521:31] + wire _T_3592 = ~bus_rsp_write_error; // @[el2_lsu_bus_buffer.scala 520:73] + wire _T_3593 = buf_write[0] & _T_3592; // @[el2_lsu_bus_buffer.scala 520:71] + wire _T_3594 = io_dec_tlu_force_halt | _T_3593; // @[el2_lsu_bus_buffer.scala 520:55] + wire _T_3596 = ~buf_samedw_0; // @[el2_lsu_bus_buffer.scala 521:30] + wire _T_3597 = buf_dual_0 & _T_3596; // @[el2_lsu_bus_buffer.scala 521:28] + wire _T_3600 = _T_3597 & _T_3643; // @[el2_lsu_bus_buffer.scala 521:45] + wire [2:0] _GEN_19 = 2'h1 == buf_dualtag_0 ? buf_state_1 : buf_state_0; // @[el2_lsu_bus_buffer.scala 521:90] + wire [2:0] _GEN_20 = 2'h2 == buf_dualtag_0 ? buf_state_2 : _GEN_19; // @[el2_lsu_bus_buffer.scala 521:90] + wire [2:0] _GEN_21 = 2'h3 == buf_dualtag_0 ? buf_state_3 : _GEN_20; // @[el2_lsu_bus_buffer.scala 521:90] + wire _T_3601 = _GEN_21 != 3'h4; // @[el2_lsu_bus_buffer.scala 521:90] + wire _T_3602 = _T_3600 & _T_3601; // @[el2_lsu_bus_buffer.scala 521:61] + wire _T_4494 = _T_2746 | _T_2743; // @[el2_lsu_bus_buffer.scala 579:93] + wire _T_4495 = _T_4494 | _T_2740; // @[el2_lsu_bus_buffer.scala 579:93] + wire any_done_wait_state = _T_4495 | _T_2737; // @[el2_lsu_bus_buffer.scala 579:93] + wire _T_3604 = buf_ldfwd[0] | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 522:31] wire _T_3610 = buf_dualtag_0 == 2'h0; // @[el2_lsu_bus_buffer.scala 111:118] wire _T_3612 = buf_dualtag_0 == 2'h1; // @[el2_lsu_bus_buffer.scala 111:118] wire _T_3614 = buf_dualtag_0 == 2'h2; // @[el2_lsu_bus_buffer.scala 111:118] @@ -2139,17 +2184,17 @@ module el2_lsu_bus_buffer( wire _T_3622 = _T_3618 | _T_3619; // @[Mux.scala 27:72] wire _T_3623 = _T_3622 | _T_3620; // @[Mux.scala 27:72] wire _T_3624 = _T_3623 | _T_3621; // @[Mux.scala 27:72] - wire _T_3626 = _T_3600 & _T_3624; // @[el2_lsu_bus_buffer.scala 521:101] - wire _T_3627 = _GEN_21 == 3'h4; // @[el2_lsu_bus_buffer.scala 521:167] - wire _T_3628 = _T_3626 & _T_3627; // @[el2_lsu_bus_buffer.scala 521:138] - wire _T_3629 = _T_3628 & any_done_wait_state; // @[el2_lsu_bus_buffer.scala 521:187] - wire _T_3630 = _T_3604 | _T_3629; // @[el2_lsu_bus_buffer.scala 521:53] - wire _T_3653 = buf_state_bus_en_0 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 528:47] - wire _T_3654 = _T_3653 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 528:62] - wire _T_3668 = ~buf_error_en_0; // @[el2_lsu_bus_buffer.scala 532:50] - wire _T_3669 = buf_state_en_0 & _T_3668; // @[el2_lsu_bus_buffer.scala 532:48] - wire _T_3681 = buf_ldfwd[0] | _T_3686[0]; // @[el2_lsu_bus_buffer.scala 535:90] - wire _T_3682 = _T_3681 | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 535:118] + wire _T_3626 = _T_3600 & _T_3624; // @[el2_lsu_bus_buffer.scala 522:101] + wire _T_3627 = _GEN_21 == 3'h4; // @[el2_lsu_bus_buffer.scala 522:167] + wire _T_3628 = _T_3626 & _T_3627; // @[el2_lsu_bus_buffer.scala 522:138] + wire _T_3629 = _T_3628 & any_done_wait_state; // @[el2_lsu_bus_buffer.scala 522:187] + wire _T_3630 = _T_3604 | _T_3629; // @[el2_lsu_bus_buffer.scala 522:53] + wire _T_3653 = buf_state_bus_en_0 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 529:47] + wire _T_3654 = _T_3653 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 529:62] + wire _T_3668 = ~buf_error_en_0; // @[el2_lsu_bus_buffer.scala 533:50] + wire _T_3669 = buf_state_en_0 & _T_3668; // @[el2_lsu_bus_buffer.scala 533:48] + wire _T_3681 = buf_ldfwd[0] | _T_3686[0]; // @[el2_lsu_bus_buffer.scala 536:90] + wire _T_3682 = _T_3681 | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 536:118] wire _GEN_29 = _T_3702 & buf_state_en_0; // @[Conditional.scala 39:67] wire _GEN_32 = _T_3694 ? 1'h0 : _T_3702; // @[Conditional.scala 39:67] wire _GEN_34 = _T_3694 ? 1'h0 : _GEN_29; // @[Conditional.scala 39:67] @@ -2167,34 +2212,34 @@ module el2_lsu_bus_buffer( wire buf_wr_en_0 = _T_3528 & buf_state_en_0; // @[Conditional.scala 40:58] wire buf_ldfwd_en_0 = _T_3528 ? 1'h0 : _GEN_68; // @[Conditional.scala 40:58] wire buf_rst_0 = _T_3528 ? 1'h0 : _GEN_74; // @[Conditional.scala 40:58] - wire _T_3765 = buf_state_en_1 & _T_3836; // @[el2_lsu_bus_buffer.scala 512:44] - wire _T_3766 = _T_3765 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 512:60] - wire _T_3768 = _T_3766 & _T_1333; // @[el2_lsu_bus_buffer.scala 512:74] - wire _T_3771 = _T_3761 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 514:67] - wire _T_3772 = _T_3771 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 514:81] - wire _T_3775 = _T_3771 & bus_rsp_read_error; // @[el2_lsu_bus_buffer.scala 515:82] - wire _T_3850 = bus_rsp_read_error & _T_3829; // @[el2_lsu_bus_buffer.scala 529:91] - wire _T_3852 = bus_rsp_read_error & buf_ldfwd[1]; // @[el2_lsu_bus_buffer.scala 530:31] - wire _T_3854 = _T_3852 & _T_3831; // @[el2_lsu_bus_buffer.scala 530:46] - wire _T_3855 = _T_3850 | _T_3854; // @[el2_lsu_bus_buffer.scala 529:143] - wire _T_3858 = bus_rsp_write_error & _T_3827; // @[el2_lsu_bus_buffer.scala 531:53] - wire _T_3859 = _T_3855 | _T_3858; // @[el2_lsu_bus_buffer.scala 530:88] - wire _T_3860 = _T_3761 & _T_3859; // @[el2_lsu_bus_buffer.scala 529:68] + wire _T_3765 = buf_state_en_1 & _T_3836; // @[el2_lsu_bus_buffer.scala 513:44] + wire _T_3766 = _T_3765 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 513:60] + wire _T_3768 = _T_3766 & _T_1333; // @[el2_lsu_bus_buffer.scala 513:74] + wire _T_3771 = _T_3761 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 515:67] + wire _T_3772 = _T_3771 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 515:81] + wire _T_3775 = _T_3771 & bus_rsp_read_error; // @[el2_lsu_bus_buffer.scala 516:82] + wire _T_3850 = bus_rsp_read_error & _T_3829; // @[el2_lsu_bus_buffer.scala 530:91] + wire _T_3852 = bus_rsp_read_error & buf_ldfwd[1]; // @[el2_lsu_bus_buffer.scala 531:31] + wire _T_3854 = _T_3852 & _T_3831; // @[el2_lsu_bus_buffer.scala 531:46] + wire _T_3855 = _T_3850 | _T_3854; // @[el2_lsu_bus_buffer.scala 530:143] + wire _T_3858 = bus_rsp_write_error & _T_3827; // @[el2_lsu_bus_buffer.scala 532:53] + wire _T_3859 = _T_3855 | _T_3858; // @[el2_lsu_bus_buffer.scala 531:88] + wire _T_3860 = _T_3761 & _T_3859; // @[el2_lsu_bus_buffer.scala 530:68] wire _GEN_122 = _T_3782 & _T_3860; // @[Conditional.scala 39:67] wire _GEN_135 = _T_3748 ? _T_3775 : _GEN_122; // @[Conditional.scala 39:67] wire _GEN_147 = _T_3744 ? 1'h0 : _GEN_135; // @[Conditional.scala 39:67] wire buf_error_en_1 = _T_3721 ? 1'h0 : _GEN_147; // @[Conditional.scala 40:58] - wire _T_3786 = buf_write[1] & _T_3592; // @[el2_lsu_bus_buffer.scala 519:71] - wire _T_3787 = io_dec_tlu_force_halt | _T_3786; // @[el2_lsu_bus_buffer.scala 519:55] - wire _T_3789 = ~buf_samedw_1; // @[el2_lsu_bus_buffer.scala 520:30] - wire _T_3790 = buf_dual_1 & _T_3789; // @[el2_lsu_bus_buffer.scala 520:28] - wire _T_3793 = _T_3790 & _T_3836; // @[el2_lsu_bus_buffer.scala 520:45] - wire [2:0] _GEN_95 = 2'h1 == buf_dualtag_1 ? buf_state_1 : buf_state_0; // @[el2_lsu_bus_buffer.scala 520:90] - wire [2:0] _GEN_96 = 2'h2 == buf_dualtag_1 ? buf_state_2 : _GEN_95; // @[el2_lsu_bus_buffer.scala 520:90] - wire [2:0] _GEN_97 = 2'h3 == buf_dualtag_1 ? buf_state_3 : _GEN_96; // @[el2_lsu_bus_buffer.scala 520:90] - wire _T_3794 = _GEN_97 != 3'h4; // @[el2_lsu_bus_buffer.scala 520:90] - wire _T_3795 = _T_3793 & _T_3794; // @[el2_lsu_bus_buffer.scala 520:61] - wire _T_3797 = buf_ldfwd[1] | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 521:31] + wire _T_3786 = buf_write[1] & _T_3592; // @[el2_lsu_bus_buffer.scala 520:71] + wire _T_3787 = io_dec_tlu_force_halt | _T_3786; // @[el2_lsu_bus_buffer.scala 520:55] + wire _T_3789 = ~buf_samedw_1; // @[el2_lsu_bus_buffer.scala 521:30] + wire _T_3790 = buf_dual_1 & _T_3789; // @[el2_lsu_bus_buffer.scala 521:28] + wire _T_3793 = _T_3790 & _T_3836; // @[el2_lsu_bus_buffer.scala 521:45] + wire [2:0] _GEN_95 = 2'h1 == buf_dualtag_1 ? buf_state_1 : buf_state_0; // @[el2_lsu_bus_buffer.scala 521:90] + wire [2:0] _GEN_96 = 2'h2 == buf_dualtag_1 ? buf_state_2 : _GEN_95; // @[el2_lsu_bus_buffer.scala 521:90] + wire [2:0] _GEN_97 = 2'h3 == buf_dualtag_1 ? buf_state_3 : _GEN_96; // @[el2_lsu_bus_buffer.scala 521:90] + wire _T_3794 = _GEN_97 != 3'h4; // @[el2_lsu_bus_buffer.scala 521:90] + wire _T_3795 = _T_3793 & _T_3794; // @[el2_lsu_bus_buffer.scala 521:61] + wire _T_3797 = buf_ldfwd[1] | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 522:31] wire _T_3803 = buf_dualtag_1 == 2'h0; // @[el2_lsu_bus_buffer.scala 111:118] wire _T_3805 = buf_dualtag_1 == 2'h1; // @[el2_lsu_bus_buffer.scala 111:118] wire _T_3807 = buf_dualtag_1 == 2'h2; // @[el2_lsu_bus_buffer.scala 111:118] @@ -2206,17 +2251,17 @@ module el2_lsu_bus_buffer( wire _T_3815 = _T_3811 | _T_3812; // @[Mux.scala 27:72] wire _T_3816 = _T_3815 | _T_3813; // @[Mux.scala 27:72] wire _T_3817 = _T_3816 | _T_3814; // @[Mux.scala 27:72] - wire _T_3819 = _T_3793 & _T_3817; // @[el2_lsu_bus_buffer.scala 521:101] - wire _T_3820 = _GEN_97 == 3'h4; // @[el2_lsu_bus_buffer.scala 521:167] - wire _T_3821 = _T_3819 & _T_3820; // @[el2_lsu_bus_buffer.scala 521:138] - wire _T_3822 = _T_3821 & any_done_wait_state; // @[el2_lsu_bus_buffer.scala 521:187] - wire _T_3823 = _T_3797 | _T_3822; // @[el2_lsu_bus_buffer.scala 521:53] - wire _T_3846 = buf_state_bus_en_1 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 528:47] - wire _T_3847 = _T_3846 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 528:62] - wire _T_3861 = ~buf_error_en_1; // @[el2_lsu_bus_buffer.scala 532:50] - wire _T_3862 = buf_state_en_1 & _T_3861; // @[el2_lsu_bus_buffer.scala 532:48] - wire _T_3874 = buf_ldfwd[1] | _T_3879[0]; // @[el2_lsu_bus_buffer.scala 535:90] - wire _T_3875 = _T_3874 | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 535:118] + wire _T_3819 = _T_3793 & _T_3817; // @[el2_lsu_bus_buffer.scala 522:101] + wire _T_3820 = _GEN_97 == 3'h4; // @[el2_lsu_bus_buffer.scala 522:167] + wire _T_3821 = _T_3819 & _T_3820; // @[el2_lsu_bus_buffer.scala 522:138] + wire _T_3822 = _T_3821 & any_done_wait_state; // @[el2_lsu_bus_buffer.scala 522:187] + wire _T_3823 = _T_3797 | _T_3822; // @[el2_lsu_bus_buffer.scala 522:53] + wire _T_3846 = buf_state_bus_en_1 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 529:47] + wire _T_3847 = _T_3846 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 529:62] + wire _T_3861 = ~buf_error_en_1; // @[el2_lsu_bus_buffer.scala 533:50] + wire _T_3862 = buf_state_en_1 & _T_3861; // @[el2_lsu_bus_buffer.scala 533:48] + wire _T_3874 = buf_ldfwd[1] | _T_3879[0]; // @[el2_lsu_bus_buffer.scala 536:90] + wire _T_3875 = _T_3874 | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 536:118] wire _GEN_105 = _T_3895 & buf_state_en_1; // @[Conditional.scala 39:67] wire _GEN_108 = _T_3887 ? 1'h0 : _T_3895; // @[Conditional.scala 39:67] wire _GEN_110 = _T_3887 ? 1'h0 : _GEN_105; // @[Conditional.scala 39:67] @@ -2234,34 +2279,34 @@ module el2_lsu_bus_buffer( wire buf_wr_en_1 = _T_3721 & buf_state_en_1; // @[Conditional.scala 40:58] wire buf_ldfwd_en_1 = _T_3721 ? 1'h0 : _GEN_144; // @[Conditional.scala 40:58] wire buf_rst_1 = _T_3721 ? 1'h0 : _GEN_150; // @[Conditional.scala 40:58] - wire _T_3958 = buf_state_en_2 & _T_4029; // @[el2_lsu_bus_buffer.scala 512:44] - wire _T_3959 = _T_3958 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 512:60] - wire _T_3961 = _T_3959 & _T_1333; // @[el2_lsu_bus_buffer.scala 512:74] - wire _T_3964 = _T_3954 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 514:67] - wire _T_3965 = _T_3964 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 514:81] - wire _T_3968 = _T_3964 & bus_rsp_read_error; // @[el2_lsu_bus_buffer.scala 515:82] - wire _T_4043 = bus_rsp_read_error & _T_4022; // @[el2_lsu_bus_buffer.scala 529:91] - wire _T_4045 = bus_rsp_read_error & buf_ldfwd[2]; // @[el2_lsu_bus_buffer.scala 530:31] - wire _T_4047 = _T_4045 & _T_4024; // @[el2_lsu_bus_buffer.scala 530:46] - wire _T_4048 = _T_4043 | _T_4047; // @[el2_lsu_bus_buffer.scala 529:143] - wire _T_4051 = bus_rsp_write_error & _T_4020; // @[el2_lsu_bus_buffer.scala 531:53] - wire _T_4052 = _T_4048 | _T_4051; // @[el2_lsu_bus_buffer.scala 530:88] - wire _T_4053 = _T_3954 & _T_4052; // @[el2_lsu_bus_buffer.scala 529:68] + wire _T_3958 = buf_state_en_2 & _T_4029; // @[el2_lsu_bus_buffer.scala 513:44] + wire _T_3959 = _T_3958 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 513:60] + wire _T_3961 = _T_3959 & _T_1333; // @[el2_lsu_bus_buffer.scala 513:74] + wire _T_3964 = _T_3954 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 515:67] + wire _T_3965 = _T_3964 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 515:81] + wire _T_3968 = _T_3964 & bus_rsp_read_error; // @[el2_lsu_bus_buffer.scala 516:82] + wire _T_4043 = bus_rsp_read_error & _T_4022; // @[el2_lsu_bus_buffer.scala 530:91] + wire _T_4045 = bus_rsp_read_error & buf_ldfwd[2]; // @[el2_lsu_bus_buffer.scala 531:31] + wire _T_4047 = _T_4045 & _T_4024; // @[el2_lsu_bus_buffer.scala 531:46] + wire _T_4048 = _T_4043 | _T_4047; // @[el2_lsu_bus_buffer.scala 530:143] + wire _T_4051 = bus_rsp_write_error & _T_4020; // @[el2_lsu_bus_buffer.scala 532:53] + wire _T_4052 = _T_4048 | _T_4051; // @[el2_lsu_bus_buffer.scala 531:88] + wire _T_4053 = _T_3954 & _T_4052; // @[el2_lsu_bus_buffer.scala 530:68] wire _GEN_198 = _T_3975 & _T_4053; // @[Conditional.scala 39:67] wire _GEN_211 = _T_3941 ? _T_3968 : _GEN_198; // @[Conditional.scala 39:67] wire _GEN_223 = _T_3937 ? 1'h0 : _GEN_211; // @[Conditional.scala 39:67] wire buf_error_en_2 = _T_3914 ? 1'h0 : _GEN_223; // @[Conditional.scala 40:58] - wire _T_3979 = buf_write[2] & _T_3592; // @[el2_lsu_bus_buffer.scala 519:71] - wire _T_3980 = io_dec_tlu_force_halt | _T_3979; // @[el2_lsu_bus_buffer.scala 519:55] - wire _T_3982 = ~buf_samedw_2; // @[el2_lsu_bus_buffer.scala 520:30] - wire _T_3983 = buf_dual_2 & _T_3982; // @[el2_lsu_bus_buffer.scala 520:28] - wire _T_3986 = _T_3983 & _T_4029; // @[el2_lsu_bus_buffer.scala 520:45] - wire [2:0] _GEN_171 = 2'h1 == buf_dualtag_2 ? buf_state_1 : buf_state_0; // @[el2_lsu_bus_buffer.scala 520:90] - wire [2:0] _GEN_172 = 2'h2 == buf_dualtag_2 ? buf_state_2 : _GEN_171; // @[el2_lsu_bus_buffer.scala 520:90] - wire [2:0] _GEN_173 = 2'h3 == buf_dualtag_2 ? buf_state_3 : _GEN_172; // @[el2_lsu_bus_buffer.scala 520:90] - wire _T_3987 = _GEN_173 != 3'h4; // @[el2_lsu_bus_buffer.scala 520:90] - wire _T_3988 = _T_3986 & _T_3987; // @[el2_lsu_bus_buffer.scala 520:61] - wire _T_3990 = buf_ldfwd[2] | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 521:31] + wire _T_3979 = buf_write[2] & _T_3592; // @[el2_lsu_bus_buffer.scala 520:71] + wire _T_3980 = io_dec_tlu_force_halt | _T_3979; // @[el2_lsu_bus_buffer.scala 520:55] + wire _T_3982 = ~buf_samedw_2; // @[el2_lsu_bus_buffer.scala 521:30] + wire _T_3983 = buf_dual_2 & _T_3982; // @[el2_lsu_bus_buffer.scala 521:28] + wire _T_3986 = _T_3983 & _T_4029; // @[el2_lsu_bus_buffer.scala 521:45] + wire [2:0] _GEN_171 = 2'h1 == buf_dualtag_2 ? buf_state_1 : buf_state_0; // @[el2_lsu_bus_buffer.scala 521:90] + wire [2:0] _GEN_172 = 2'h2 == buf_dualtag_2 ? buf_state_2 : _GEN_171; // @[el2_lsu_bus_buffer.scala 521:90] + wire [2:0] _GEN_173 = 2'h3 == buf_dualtag_2 ? buf_state_3 : _GEN_172; // @[el2_lsu_bus_buffer.scala 521:90] + wire _T_3987 = _GEN_173 != 3'h4; // @[el2_lsu_bus_buffer.scala 521:90] + wire _T_3988 = _T_3986 & _T_3987; // @[el2_lsu_bus_buffer.scala 521:61] + wire _T_3990 = buf_ldfwd[2] | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 522:31] wire _T_3996 = buf_dualtag_2 == 2'h0; // @[el2_lsu_bus_buffer.scala 111:118] wire _T_3998 = buf_dualtag_2 == 2'h1; // @[el2_lsu_bus_buffer.scala 111:118] wire _T_4000 = buf_dualtag_2 == 2'h2; // @[el2_lsu_bus_buffer.scala 111:118] @@ -2273,17 +2318,17 @@ module el2_lsu_bus_buffer( wire _T_4008 = _T_4004 | _T_4005; // @[Mux.scala 27:72] wire _T_4009 = _T_4008 | _T_4006; // @[Mux.scala 27:72] wire _T_4010 = _T_4009 | _T_4007; // @[Mux.scala 27:72] - wire _T_4012 = _T_3986 & _T_4010; // @[el2_lsu_bus_buffer.scala 521:101] - wire _T_4013 = _GEN_173 == 3'h4; // @[el2_lsu_bus_buffer.scala 521:167] - wire _T_4014 = _T_4012 & _T_4013; // @[el2_lsu_bus_buffer.scala 521:138] - wire _T_4015 = _T_4014 & any_done_wait_state; // @[el2_lsu_bus_buffer.scala 521:187] - wire _T_4016 = _T_3990 | _T_4015; // @[el2_lsu_bus_buffer.scala 521:53] - wire _T_4039 = buf_state_bus_en_2 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 528:47] - wire _T_4040 = _T_4039 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 528:62] - wire _T_4054 = ~buf_error_en_2; // @[el2_lsu_bus_buffer.scala 532:50] - wire _T_4055 = buf_state_en_2 & _T_4054; // @[el2_lsu_bus_buffer.scala 532:48] - wire _T_4067 = buf_ldfwd[2] | _T_4072[0]; // @[el2_lsu_bus_buffer.scala 535:90] - wire _T_4068 = _T_4067 | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 535:118] + wire _T_4012 = _T_3986 & _T_4010; // @[el2_lsu_bus_buffer.scala 522:101] + wire _T_4013 = _GEN_173 == 3'h4; // @[el2_lsu_bus_buffer.scala 522:167] + wire _T_4014 = _T_4012 & _T_4013; // @[el2_lsu_bus_buffer.scala 522:138] + wire _T_4015 = _T_4014 & any_done_wait_state; // @[el2_lsu_bus_buffer.scala 522:187] + wire _T_4016 = _T_3990 | _T_4015; // @[el2_lsu_bus_buffer.scala 522:53] + wire _T_4039 = buf_state_bus_en_2 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 529:47] + wire _T_4040 = _T_4039 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 529:62] + wire _T_4054 = ~buf_error_en_2; // @[el2_lsu_bus_buffer.scala 533:50] + wire _T_4055 = buf_state_en_2 & _T_4054; // @[el2_lsu_bus_buffer.scala 533:48] + wire _T_4067 = buf_ldfwd[2] | _T_4072[0]; // @[el2_lsu_bus_buffer.scala 536:90] + wire _T_4068 = _T_4067 | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 536:118] wire _GEN_181 = _T_4088 & buf_state_en_2; // @[Conditional.scala 39:67] wire _GEN_184 = _T_4080 ? 1'h0 : _T_4088; // @[Conditional.scala 39:67] wire _GEN_186 = _T_4080 ? 1'h0 : _GEN_181; // @[Conditional.scala 39:67] @@ -2301,34 +2346,34 @@ module el2_lsu_bus_buffer( wire buf_wr_en_2 = _T_3914 & buf_state_en_2; // @[Conditional.scala 40:58] wire buf_ldfwd_en_2 = _T_3914 ? 1'h0 : _GEN_220; // @[Conditional.scala 40:58] wire buf_rst_2 = _T_3914 ? 1'h0 : _GEN_226; // @[Conditional.scala 40:58] - wire _T_4151 = buf_state_en_3 & _T_4222; // @[el2_lsu_bus_buffer.scala 512:44] - wire _T_4152 = _T_4151 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 512:60] - wire _T_4154 = _T_4152 & _T_1333; // @[el2_lsu_bus_buffer.scala 512:74] - wire _T_4157 = _T_4147 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 514:67] - wire _T_4158 = _T_4157 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 514:81] - wire _T_4161 = _T_4157 & bus_rsp_read_error; // @[el2_lsu_bus_buffer.scala 515:82] - wire _T_4236 = bus_rsp_read_error & _T_4215; // @[el2_lsu_bus_buffer.scala 529:91] - wire _T_4238 = bus_rsp_read_error & buf_ldfwd[3]; // @[el2_lsu_bus_buffer.scala 530:31] - wire _T_4240 = _T_4238 & _T_4217; // @[el2_lsu_bus_buffer.scala 530:46] - wire _T_4241 = _T_4236 | _T_4240; // @[el2_lsu_bus_buffer.scala 529:143] - wire _T_4244 = bus_rsp_write_error & _T_4213; // @[el2_lsu_bus_buffer.scala 531:53] - wire _T_4245 = _T_4241 | _T_4244; // @[el2_lsu_bus_buffer.scala 530:88] - wire _T_4246 = _T_4147 & _T_4245; // @[el2_lsu_bus_buffer.scala 529:68] + wire _T_4151 = buf_state_en_3 & _T_4222; // @[el2_lsu_bus_buffer.scala 513:44] + wire _T_4152 = _T_4151 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 513:60] + wire _T_4154 = _T_4152 & _T_1333; // @[el2_lsu_bus_buffer.scala 513:74] + wire _T_4157 = _T_4147 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 515:67] + wire _T_4158 = _T_4157 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 515:81] + wire _T_4161 = _T_4157 & bus_rsp_read_error; // @[el2_lsu_bus_buffer.scala 516:82] + wire _T_4236 = bus_rsp_read_error & _T_4215; // @[el2_lsu_bus_buffer.scala 530:91] + wire _T_4238 = bus_rsp_read_error & buf_ldfwd[3]; // @[el2_lsu_bus_buffer.scala 531:31] + wire _T_4240 = _T_4238 & _T_4217; // @[el2_lsu_bus_buffer.scala 531:46] + wire _T_4241 = _T_4236 | _T_4240; // @[el2_lsu_bus_buffer.scala 530:143] + wire _T_4244 = bus_rsp_write_error & _T_4213; // @[el2_lsu_bus_buffer.scala 532:53] + wire _T_4245 = _T_4241 | _T_4244; // @[el2_lsu_bus_buffer.scala 531:88] + wire _T_4246 = _T_4147 & _T_4245; // @[el2_lsu_bus_buffer.scala 530:68] wire _GEN_274 = _T_4168 & _T_4246; // @[Conditional.scala 39:67] wire _GEN_287 = _T_4134 ? _T_4161 : _GEN_274; // @[Conditional.scala 39:67] wire _GEN_299 = _T_4130 ? 1'h0 : _GEN_287; // @[Conditional.scala 39:67] wire buf_error_en_3 = _T_4107 ? 1'h0 : _GEN_299; // @[Conditional.scala 40:58] - wire _T_4172 = buf_write[3] & _T_3592; // @[el2_lsu_bus_buffer.scala 519:71] - wire _T_4173 = io_dec_tlu_force_halt | _T_4172; // @[el2_lsu_bus_buffer.scala 519:55] - wire _T_4175 = ~buf_samedw_3; // @[el2_lsu_bus_buffer.scala 520:30] - wire _T_4176 = buf_dual_3 & _T_4175; // @[el2_lsu_bus_buffer.scala 520:28] - wire _T_4179 = _T_4176 & _T_4222; // @[el2_lsu_bus_buffer.scala 520:45] - wire [2:0] _GEN_247 = 2'h1 == buf_dualtag_3 ? buf_state_1 : buf_state_0; // @[el2_lsu_bus_buffer.scala 520:90] - wire [2:0] _GEN_248 = 2'h2 == buf_dualtag_3 ? buf_state_2 : _GEN_247; // @[el2_lsu_bus_buffer.scala 520:90] - wire [2:0] _GEN_249 = 2'h3 == buf_dualtag_3 ? buf_state_3 : _GEN_248; // @[el2_lsu_bus_buffer.scala 520:90] - wire _T_4180 = _GEN_249 != 3'h4; // @[el2_lsu_bus_buffer.scala 520:90] - wire _T_4181 = _T_4179 & _T_4180; // @[el2_lsu_bus_buffer.scala 520:61] - wire _T_4183 = buf_ldfwd[3] | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 521:31] + wire _T_4172 = buf_write[3] & _T_3592; // @[el2_lsu_bus_buffer.scala 520:71] + wire _T_4173 = io_dec_tlu_force_halt | _T_4172; // @[el2_lsu_bus_buffer.scala 520:55] + wire _T_4175 = ~buf_samedw_3; // @[el2_lsu_bus_buffer.scala 521:30] + wire _T_4176 = buf_dual_3 & _T_4175; // @[el2_lsu_bus_buffer.scala 521:28] + wire _T_4179 = _T_4176 & _T_4222; // @[el2_lsu_bus_buffer.scala 521:45] + wire [2:0] _GEN_247 = 2'h1 == buf_dualtag_3 ? buf_state_1 : buf_state_0; // @[el2_lsu_bus_buffer.scala 521:90] + wire [2:0] _GEN_248 = 2'h2 == buf_dualtag_3 ? buf_state_2 : _GEN_247; // @[el2_lsu_bus_buffer.scala 521:90] + wire [2:0] _GEN_249 = 2'h3 == buf_dualtag_3 ? buf_state_3 : _GEN_248; // @[el2_lsu_bus_buffer.scala 521:90] + wire _T_4180 = _GEN_249 != 3'h4; // @[el2_lsu_bus_buffer.scala 521:90] + wire _T_4181 = _T_4179 & _T_4180; // @[el2_lsu_bus_buffer.scala 521:61] + wire _T_4183 = buf_ldfwd[3] | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 522:31] wire _T_4189 = buf_dualtag_3 == 2'h0; // @[el2_lsu_bus_buffer.scala 111:118] wire _T_4191 = buf_dualtag_3 == 2'h1; // @[el2_lsu_bus_buffer.scala 111:118] wire _T_4193 = buf_dualtag_3 == 2'h2; // @[el2_lsu_bus_buffer.scala 111:118] @@ -2340,17 +2385,17 @@ module el2_lsu_bus_buffer( wire _T_4201 = _T_4197 | _T_4198; // @[Mux.scala 27:72] wire _T_4202 = _T_4201 | _T_4199; // @[Mux.scala 27:72] wire _T_4203 = _T_4202 | _T_4200; // @[Mux.scala 27:72] - wire _T_4205 = _T_4179 & _T_4203; // @[el2_lsu_bus_buffer.scala 521:101] - wire _T_4206 = _GEN_249 == 3'h4; // @[el2_lsu_bus_buffer.scala 521:167] - wire _T_4207 = _T_4205 & _T_4206; // @[el2_lsu_bus_buffer.scala 521:138] - wire _T_4208 = _T_4207 & any_done_wait_state; // @[el2_lsu_bus_buffer.scala 521:187] - wire _T_4209 = _T_4183 | _T_4208; // @[el2_lsu_bus_buffer.scala 521:53] - wire _T_4232 = buf_state_bus_en_3 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 528:47] - wire _T_4233 = _T_4232 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 528:62] - wire _T_4247 = ~buf_error_en_3; // @[el2_lsu_bus_buffer.scala 532:50] - wire _T_4248 = buf_state_en_3 & _T_4247; // @[el2_lsu_bus_buffer.scala 532:48] - wire _T_4260 = buf_ldfwd[3] | _T_4265[0]; // @[el2_lsu_bus_buffer.scala 535:90] - wire _T_4261 = _T_4260 | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 535:118] + wire _T_4205 = _T_4179 & _T_4203; // @[el2_lsu_bus_buffer.scala 522:101] + wire _T_4206 = _GEN_249 == 3'h4; // @[el2_lsu_bus_buffer.scala 522:167] + wire _T_4207 = _T_4205 & _T_4206; // @[el2_lsu_bus_buffer.scala 522:138] + wire _T_4208 = _T_4207 & any_done_wait_state; // @[el2_lsu_bus_buffer.scala 522:187] + wire _T_4209 = _T_4183 | _T_4208; // @[el2_lsu_bus_buffer.scala 522:53] + wire _T_4232 = buf_state_bus_en_3 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 529:47] + wire _T_4233 = _T_4232 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 529:62] + wire _T_4247 = ~buf_error_en_3; // @[el2_lsu_bus_buffer.scala 533:50] + wire _T_4248 = buf_state_en_3 & _T_4247; // @[el2_lsu_bus_buffer.scala 533:48] + wire _T_4260 = buf_ldfwd[3] | _T_4265[0]; // @[el2_lsu_bus_buffer.scala 536:90] + wire _T_4261 = _T_4260 | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 536:118] wire _GEN_257 = _T_4281 & buf_state_en_3; // @[Conditional.scala 39:67] wire _GEN_260 = _T_4273 ? 1'h0 : _T_4281; // @[Conditional.scala 39:67] wire _GEN_262 = _T_4273 ? 1'h0 : _GEN_257; // @[Conditional.scala 39:67] @@ -2373,51 +2418,51 @@ module el2_lsu_bus_buffer( reg _T_4342; // @[Reg.scala 27:20] reg _T_4345; // @[Reg.scala 27:20] wire [3:0] buf_unsign = {_T_4345,_T_4342,_T_4339,_T_4336}; // @[Cat.scala 29:58] - reg _T_4411; // @[el2_lsu_bus_buffer.scala 571:80] - reg _T_4406; // @[el2_lsu_bus_buffer.scala 571:80] - reg _T_4401; // @[el2_lsu_bus_buffer.scala 571:80] - reg _T_4396; // @[el2_lsu_bus_buffer.scala 571:80] + reg _T_4411; // @[el2_lsu_bus_buffer.scala 572:80] + reg _T_4406; // @[el2_lsu_bus_buffer.scala 572:80] + reg _T_4401; // @[el2_lsu_bus_buffer.scala 572:80] + reg _T_4396; // @[el2_lsu_bus_buffer.scala 572:80] wire [3:0] buf_error = {_T_4411,_T_4406,_T_4401,_T_4396}; // @[Cat.scala 29:58] - wire _T_4393 = buf_error_en_0 | buf_error[0]; // @[el2_lsu_bus_buffer.scala 571:84] - wire _T_4394 = ~buf_rst_0; // @[el2_lsu_bus_buffer.scala 571:126] - wire _T_4398 = buf_error_en_1 | buf_error[1]; // @[el2_lsu_bus_buffer.scala 571:84] - wire _T_4399 = ~buf_rst_1; // @[el2_lsu_bus_buffer.scala 571:126] - wire _T_4403 = buf_error_en_2 | buf_error[2]; // @[el2_lsu_bus_buffer.scala 571:84] - wire _T_4404 = ~buf_rst_2; // @[el2_lsu_bus_buffer.scala 571:126] - wire _T_4408 = buf_error_en_3 | buf_error[3]; // @[el2_lsu_bus_buffer.scala 571:84] - wire _T_4409 = ~buf_rst_3; // @[el2_lsu_bus_buffer.scala 571:126] + wire _T_4393 = buf_error_en_0 | buf_error[0]; // @[el2_lsu_bus_buffer.scala 572:84] + wire _T_4394 = ~buf_rst_0; // @[el2_lsu_bus_buffer.scala 572:126] + wire _T_4398 = buf_error_en_1 | buf_error[1]; // @[el2_lsu_bus_buffer.scala 572:84] + wire _T_4399 = ~buf_rst_1; // @[el2_lsu_bus_buffer.scala 572:126] + wire _T_4403 = buf_error_en_2 | buf_error[2]; // @[el2_lsu_bus_buffer.scala 572:84] + wire _T_4404 = ~buf_rst_2; // @[el2_lsu_bus_buffer.scala 572:126] + wire _T_4408 = buf_error_en_3 | buf_error[3]; // @[el2_lsu_bus_buffer.scala 572:84] + wire _T_4409 = ~buf_rst_3; // @[el2_lsu_bus_buffer.scala 572:126] wire [1:0] _T_4415 = {io_lsu_busreq_m,1'h0}; // @[Cat.scala 29:58] - wire [1:0] _T_4416 = io_ldst_dual_m ? _T_4415 : {{1'd0}, io_lsu_busreq_m}; // @[el2_lsu_bus_buffer.scala 574:28] + wire [1:0] _T_4416 = io_ldst_dual_m ? _T_4415 : {{1'd0}, io_lsu_busreq_m}; // @[el2_lsu_bus_buffer.scala 575:28] wire [1:0] _T_4417 = {io_lsu_busreq_r,1'h0}; // @[Cat.scala 29:58] - wire [1:0] _T_4418 = io_ldst_dual_r ? _T_4417 : {{1'd0}, io_lsu_busreq_r}; // @[el2_lsu_bus_buffer.scala 574:94] - wire [2:0] _T_4419 = _T_4416 + _T_4418; // @[el2_lsu_bus_buffer.scala 574:88] - wire [2:0] _GEN_388 = {{2'd0}, ibuf_valid}; // @[el2_lsu_bus_buffer.scala 574:154] - wire [3:0] _T_4420 = _T_4419 + _GEN_388; // @[el2_lsu_bus_buffer.scala 574:154] - wire [1:0] _T_4425 = _T_5 + _T_12; // @[el2_lsu_bus_buffer.scala 574:217] - wire [1:0] _GEN_389 = {{1'd0}, _T_19}; // @[el2_lsu_bus_buffer.scala 574:217] - wire [2:0] _T_4426 = _T_4425 + _GEN_389; // @[el2_lsu_bus_buffer.scala 574:217] - wire [2:0] _GEN_390 = {{2'd0}, _T_26}; // @[el2_lsu_bus_buffer.scala 574:217] - wire [3:0] _T_4427 = _T_4426 + _GEN_390; // @[el2_lsu_bus_buffer.scala 574:217] - wire [3:0] buf_numvld_any = _T_4420 + _T_4427; // @[el2_lsu_bus_buffer.scala 574:169] - wire _T_4498 = io_ldst_dual_d & io_dec_lsu_valid_raw_d; // @[el2_lsu_bus_buffer.scala 580:52] - wire _T_4499 = buf_numvld_any >= 4'h3; // @[el2_lsu_bus_buffer.scala 580:92] - wire _T_4500 = buf_numvld_any == 4'h4; // @[el2_lsu_bus_buffer.scala 580:121] - wire _T_4502 = |buf_state_0; // @[el2_lsu_bus_buffer.scala 581:52] - wire _T_4503 = |buf_state_1; // @[el2_lsu_bus_buffer.scala 581:52] - wire _T_4504 = |buf_state_2; // @[el2_lsu_bus_buffer.scala 581:52] - wire _T_4505 = |buf_state_3; // @[el2_lsu_bus_buffer.scala 581:52] - wire _T_4506 = _T_4502 | _T_4503; // @[el2_lsu_bus_buffer.scala 581:65] - wire _T_4507 = _T_4506 | _T_4504; // @[el2_lsu_bus_buffer.scala 581:65] - wire _T_4508 = _T_4507 | _T_4505; // @[el2_lsu_bus_buffer.scala 581:65] - wire _T_4509 = ~_T_4508; // @[el2_lsu_bus_buffer.scala 581:34] - wire _T_4511 = _T_4509 & _T_852; // @[el2_lsu_bus_buffer.scala 581:70] - wire _T_4514 = io_lsu_busreq_m & io_lsu_pkt_m_valid; // @[el2_lsu_bus_buffer.scala 583:51] - wire _T_4515 = _T_4514 & io_lsu_pkt_m_load; // @[el2_lsu_bus_buffer.scala 583:72] - wire _T_4516 = ~io_flush_m_up; // @[el2_lsu_bus_buffer.scala 583:94] - wire _T_4517 = _T_4515 & _T_4516; // @[el2_lsu_bus_buffer.scala 583:92] - wire _T_4518 = ~io_ld_full_hit_m; // @[el2_lsu_bus_buffer.scala 583:111] - wire _T_4520 = ~io_lsu_commit_r; // @[el2_lsu_bus_buffer.scala 586:61] - reg lsu_nonblock_load_valid_r; // @[el2_lsu_bus_buffer.scala 671:66] + wire [1:0] _T_4418 = io_ldst_dual_r ? _T_4417 : {{1'd0}, io_lsu_busreq_r}; // @[el2_lsu_bus_buffer.scala 575:94] + wire [2:0] _T_4419 = _T_4416 + _T_4418; // @[el2_lsu_bus_buffer.scala 575:88] + wire [2:0] _GEN_388 = {{2'd0}, ibuf_valid}; // @[el2_lsu_bus_buffer.scala 575:154] + wire [3:0] _T_4420 = _T_4419 + _GEN_388; // @[el2_lsu_bus_buffer.scala 575:154] + wire [1:0] _T_4425 = _T_5 + _T_12; // @[el2_lsu_bus_buffer.scala 575:217] + wire [1:0] _GEN_389 = {{1'd0}, _T_19}; // @[el2_lsu_bus_buffer.scala 575:217] + wire [2:0] _T_4426 = _T_4425 + _GEN_389; // @[el2_lsu_bus_buffer.scala 575:217] + wire [2:0] _GEN_390 = {{2'd0}, _T_26}; // @[el2_lsu_bus_buffer.scala 575:217] + wire [3:0] _T_4427 = _T_4426 + _GEN_390; // @[el2_lsu_bus_buffer.scala 575:217] + wire [3:0] buf_numvld_any = _T_4420 + _T_4427; // @[el2_lsu_bus_buffer.scala 575:169] + wire _T_4498 = io_ldst_dual_d & io_dec_lsu_valid_raw_d; // @[el2_lsu_bus_buffer.scala 581:52] + wire _T_4499 = buf_numvld_any >= 4'h3; // @[el2_lsu_bus_buffer.scala 581:92] + wire _T_4500 = buf_numvld_any == 4'h4; // @[el2_lsu_bus_buffer.scala 581:121] + wire _T_4502 = |buf_state_0; // @[el2_lsu_bus_buffer.scala 582:52] + wire _T_4503 = |buf_state_1; // @[el2_lsu_bus_buffer.scala 582:52] + wire _T_4504 = |buf_state_2; // @[el2_lsu_bus_buffer.scala 582:52] + wire _T_4505 = |buf_state_3; // @[el2_lsu_bus_buffer.scala 582:52] + wire _T_4506 = _T_4502 | _T_4503; // @[el2_lsu_bus_buffer.scala 582:65] + wire _T_4507 = _T_4506 | _T_4504; // @[el2_lsu_bus_buffer.scala 582:65] + wire _T_4508 = _T_4507 | _T_4505; // @[el2_lsu_bus_buffer.scala 582:65] + wire _T_4509 = ~_T_4508; // @[el2_lsu_bus_buffer.scala 582:34] + wire _T_4511 = _T_4509 & _T_852; // @[el2_lsu_bus_buffer.scala 582:70] + wire _T_4514 = io_lsu_busreq_m & io_lsu_pkt_m_valid; // @[el2_lsu_bus_buffer.scala 584:51] + wire _T_4515 = _T_4514 & io_lsu_pkt_m_bits_load; // @[el2_lsu_bus_buffer.scala 584:72] + wire _T_4516 = ~io_flush_m_up; // @[el2_lsu_bus_buffer.scala 584:99] + wire _T_4517 = _T_4515 & _T_4516; // @[el2_lsu_bus_buffer.scala 584:97] + wire _T_4518 = ~io_ld_full_hit_m; // @[el2_lsu_bus_buffer.scala 584:116] + wire _T_4520 = ~io_lsu_commit_r; // @[el2_lsu_bus_buffer.scala 587:61] + reg lsu_nonblock_load_valid_r; // @[el2_lsu_bus_buffer.scala 672:66] wire _T_4538 = _T_2799 & _T_3643; // @[Mux.scala 27:72] wire _T_4539 = _T_2821 & _T_3836; // @[Mux.scala 27:72] wire _T_4540 = _T_2843 & _T_4029; // @[Mux.scala 27:72] @@ -2425,32 +2470,32 @@ module el2_lsu_bus_buffer( wire _T_4542 = _T_4538 | _T_4539; // @[Mux.scala 27:72] wire _T_4543 = _T_4542 | _T_4540; // @[Mux.scala 27:72] wire lsu_nonblock_load_data_ready = _T_4543 | _T_4541; // @[Mux.scala 27:72] - wire _T_4549 = buf_error[0] & _T_3643; // @[el2_lsu_bus_buffer.scala 589:108] - wire _T_4554 = buf_error[1] & _T_3836; // @[el2_lsu_bus_buffer.scala 589:108] - wire _T_4559 = buf_error[2] & _T_4029; // @[el2_lsu_bus_buffer.scala 589:108] - wire _T_4564 = buf_error[3] & _T_4222; // @[el2_lsu_bus_buffer.scala 589:108] + wire _T_4549 = buf_error[0] & _T_3643; // @[el2_lsu_bus_buffer.scala 590:108] + wire _T_4554 = buf_error[1] & _T_3836; // @[el2_lsu_bus_buffer.scala 590:108] + wire _T_4559 = buf_error[2] & _T_4029; // @[el2_lsu_bus_buffer.scala 590:108] + wire _T_4564 = buf_error[3] & _T_4222; // @[el2_lsu_bus_buffer.scala 590:108] wire _T_4565 = _T_2799 & _T_4549; // @[Mux.scala 27:72] wire _T_4566 = _T_2821 & _T_4554; // @[Mux.scala 27:72] wire _T_4567 = _T_2843 & _T_4559; // @[Mux.scala 27:72] wire _T_4568 = _T_2865 & _T_4564; // @[Mux.scala 27:72] wire _T_4569 = _T_4565 | _T_4566; // @[Mux.scala 27:72] wire _T_4570 = _T_4569 | _T_4567; // @[Mux.scala 27:72] - wire _T_4577 = ~buf_dual_0; // @[el2_lsu_bus_buffer.scala 590:109] - wire _T_4578 = ~buf_dualhi_0; // @[el2_lsu_bus_buffer.scala 590:124] - wire _T_4579 = _T_4577 | _T_4578; // @[el2_lsu_bus_buffer.scala 590:122] - wire _T_4580 = _T_4538 & _T_4579; // @[el2_lsu_bus_buffer.scala 590:106] - wire _T_4585 = ~buf_dual_1; // @[el2_lsu_bus_buffer.scala 590:109] - wire _T_4586 = ~buf_dualhi_1; // @[el2_lsu_bus_buffer.scala 590:124] - wire _T_4587 = _T_4585 | _T_4586; // @[el2_lsu_bus_buffer.scala 590:122] - wire _T_4588 = _T_4539 & _T_4587; // @[el2_lsu_bus_buffer.scala 590:106] - wire _T_4593 = ~buf_dual_2; // @[el2_lsu_bus_buffer.scala 590:109] - wire _T_4594 = ~buf_dualhi_2; // @[el2_lsu_bus_buffer.scala 590:124] - wire _T_4595 = _T_4593 | _T_4594; // @[el2_lsu_bus_buffer.scala 590:122] - wire _T_4596 = _T_4540 & _T_4595; // @[el2_lsu_bus_buffer.scala 590:106] - wire _T_4601 = ~buf_dual_3; // @[el2_lsu_bus_buffer.scala 590:109] - wire _T_4602 = ~buf_dualhi_3; // @[el2_lsu_bus_buffer.scala 590:124] - wire _T_4603 = _T_4601 | _T_4602; // @[el2_lsu_bus_buffer.scala 590:122] - wire _T_4604 = _T_4541 & _T_4603; // @[el2_lsu_bus_buffer.scala 590:106] + wire _T_4577 = ~buf_dual_0; // @[el2_lsu_bus_buffer.scala 591:109] + wire _T_4578 = ~buf_dualhi_0; // @[el2_lsu_bus_buffer.scala 591:124] + wire _T_4579 = _T_4577 | _T_4578; // @[el2_lsu_bus_buffer.scala 591:122] + wire _T_4580 = _T_4538 & _T_4579; // @[el2_lsu_bus_buffer.scala 591:106] + wire _T_4585 = ~buf_dual_1; // @[el2_lsu_bus_buffer.scala 591:109] + wire _T_4586 = ~buf_dualhi_1; // @[el2_lsu_bus_buffer.scala 591:124] + wire _T_4587 = _T_4585 | _T_4586; // @[el2_lsu_bus_buffer.scala 591:122] + wire _T_4588 = _T_4539 & _T_4587; // @[el2_lsu_bus_buffer.scala 591:106] + wire _T_4593 = ~buf_dual_2; // @[el2_lsu_bus_buffer.scala 591:109] + wire _T_4594 = ~buf_dualhi_2; // @[el2_lsu_bus_buffer.scala 591:124] + wire _T_4595 = _T_4593 | _T_4594; // @[el2_lsu_bus_buffer.scala 591:122] + wire _T_4596 = _T_4540 & _T_4595; // @[el2_lsu_bus_buffer.scala 591:106] + wire _T_4601 = ~buf_dual_3; // @[el2_lsu_bus_buffer.scala 591:109] + wire _T_4602 = ~buf_dualhi_3; // @[el2_lsu_bus_buffer.scala 591:124] + wire _T_4603 = _T_4601 | _T_4602; // @[el2_lsu_bus_buffer.scala 591:122] + wire _T_4604 = _T_4541 & _T_4603; // @[el2_lsu_bus_buffer.scala 591:106] wire [1:0] _T_4607 = _T_4596 ? 2'h2 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_4608 = _T_4604 ? 2'h3 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _GEN_391 = {{1'd0}, _T_4588}; // @[Mux.scala 27:72] @@ -2462,10 +2507,10 @@ module el2_lsu_bus_buffer( wire [31:0] _T_4649 = _T_4645 | _T_4646; // @[Mux.scala 27:72] wire [31:0] _T_4650 = _T_4649 | _T_4647; // @[Mux.scala 27:72] wire [31:0] lsu_nonblock_load_data_lo = _T_4650 | _T_4648; // @[Mux.scala 27:72] - wire _T_4657 = _T_4538 & _T_3641; // @[el2_lsu_bus_buffer.scala 592:105] - wire _T_4663 = _T_4539 & _T_3834; // @[el2_lsu_bus_buffer.scala 592:105] - wire _T_4669 = _T_4540 & _T_4027; // @[el2_lsu_bus_buffer.scala 592:105] - wire _T_4675 = _T_4541 & _T_4220; // @[el2_lsu_bus_buffer.scala 592:105] + wire _T_4657 = _T_4538 & _T_3641; // @[el2_lsu_bus_buffer.scala 593:105] + wire _T_4663 = _T_4539 & _T_3834; // @[el2_lsu_bus_buffer.scala 593:105] + wire _T_4669 = _T_4540 & _T_4027; // @[el2_lsu_bus_buffer.scala 593:105] + wire _T_4675 = _T_4541 & _T_4220; // @[el2_lsu_bus_buffer.scala 593:105] wire [31:0] _T_4676 = _T_4657 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_4677 = _T_4663 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_4678 = _T_4669 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72] @@ -2484,7 +2529,7 @@ module el2_lsu_bus_buffer( wire [31:0] _T_4691 = _T_4687 | _T_4688; // @[Mux.scala 27:72] wire [31:0] _T_4692 = _T_4691 | _T_4689; // @[Mux.scala 27:72] wire [31:0] _T_4693 = _T_4692 | _T_4690; // @[Mux.scala 27:72] - wire [1:0] lsu_nonblock_addr_offset = _T_4693[1:0]; // @[el2_lsu_bus_buffer.scala 593:83] + wire [1:0] lsu_nonblock_addr_offset = _T_4693[1:0]; // @[el2_lsu_bus_buffer.scala 594:83] wire [1:0] _T_4699 = _T_4683 ? buf_sz_0 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_4700 = _T_4684 ? buf_sz_1 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_4701 = _T_4685 ? buf_sz_2 : 2'h0; // @[Mux.scala 27:72] @@ -2500,24 +2545,24 @@ module el2_lsu_bus_buffer( wire _T_4719 = _T_4718 | _T_4716; // @[Mux.scala 27:72] wire lsu_nonblock_unsign = _T_4719 | _T_4717; // @[Mux.scala 27:72] wire [63:0] _T_4739 = {lsu_nonblock_load_data_hi,lsu_nonblock_load_data_lo}; // @[Cat.scala 29:58] - wire [3:0] _GEN_392 = {{2'd0}, lsu_nonblock_addr_offset}; // @[el2_lsu_bus_buffer.scala 597:121] - wire [5:0] _T_4740 = _GEN_392 * 4'h8; // @[el2_lsu_bus_buffer.scala 597:121] - wire [63:0] lsu_nonblock_data_unalgn = _T_4739 >> _T_4740; // @[el2_lsu_bus_buffer.scala 597:92] - wire _T_4741 = ~io_lsu_nonblock_load_data_error; // @[el2_lsu_bus_buffer.scala 599:69] - wire _T_4743 = lsu_nonblock_sz == 2'h0; // @[el2_lsu_bus_buffer.scala 600:81] - wire _T_4744 = lsu_nonblock_unsign & _T_4743; // @[el2_lsu_bus_buffer.scala 600:63] + wire [3:0] _GEN_392 = {{2'd0}, lsu_nonblock_addr_offset}; // @[el2_lsu_bus_buffer.scala 598:121] + wire [5:0] _T_4740 = _GEN_392 * 4'h8; // @[el2_lsu_bus_buffer.scala 598:121] + wire [63:0] lsu_nonblock_data_unalgn = _T_4739 >> _T_4740; // @[el2_lsu_bus_buffer.scala 598:92] + wire _T_4741 = ~io_lsu_nonblock_load_data_error; // @[el2_lsu_bus_buffer.scala 600:69] + wire _T_4743 = lsu_nonblock_sz == 2'h0; // @[el2_lsu_bus_buffer.scala 601:81] + wire _T_4744 = lsu_nonblock_unsign & _T_4743; // @[el2_lsu_bus_buffer.scala 601:63] wire [31:0] _T_4746 = {24'h0,lsu_nonblock_data_unalgn[7:0]}; // @[Cat.scala 29:58] - wire _T_4747 = lsu_nonblock_sz == 2'h1; // @[el2_lsu_bus_buffer.scala 601:45] - wire _T_4748 = lsu_nonblock_unsign & _T_4747; // @[el2_lsu_bus_buffer.scala 601:26] + wire _T_4747 = lsu_nonblock_sz == 2'h1; // @[el2_lsu_bus_buffer.scala 602:45] + wire _T_4748 = lsu_nonblock_unsign & _T_4747; // @[el2_lsu_bus_buffer.scala 602:26] wire [31:0] _T_4750 = {16'h0,lsu_nonblock_data_unalgn[15:0]}; // @[Cat.scala 29:58] - wire _T_4751 = ~lsu_nonblock_unsign; // @[el2_lsu_bus_buffer.scala 602:6] - wire _T_4753 = _T_4751 & _T_4743; // @[el2_lsu_bus_buffer.scala 602:27] + wire _T_4751 = ~lsu_nonblock_unsign; // @[el2_lsu_bus_buffer.scala 603:6] + wire _T_4753 = _T_4751 & _T_4743; // @[el2_lsu_bus_buffer.scala 603:27] wire [23:0] _T_4756 = lsu_nonblock_data_unalgn[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12] wire [31:0] _T_4758 = {_T_4756,lsu_nonblock_data_unalgn[7:0]}; // @[Cat.scala 29:58] - wire _T_4761 = _T_4751 & _T_4747; // @[el2_lsu_bus_buffer.scala 603:27] + wire _T_4761 = _T_4751 & _T_4747; // @[el2_lsu_bus_buffer.scala 604:27] wire [15:0] _T_4764 = lsu_nonblock_data_unalgn[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12] wire [31:0] _T_4766 = {_T_4764,lsu_nonblock_data_unalgn[15:0]}; // @[Cat.scala 29:58] - wire _T_4767 = lsu_nonblock_sz == 2'h2; // @[el2_lsu_bus_buffer.scala 604:21] + wire _T_4767 = lsu_nonblock_sz == 2'h2; // @[el2_lsu_bus_buffer.scala 605:21] wire [31:0] _T_4768 = _T_4744 ? _T_4746 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_4769 = _T_4748 ? _T_4750 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_4770 = _T_4753 ? _T_4758 : 32'h0; // @[Mux.scala 27:72] @@ -2528,60 +2573,60 @@ module el2_lsu_bus_buffer( wire [31:0] _T_4775 = _T_4774 | _T_4771; // @[Mux.scala 27:72] wire [63:0] _GEN_393 = {{32'd0}, _T_4775}; // @[Mux.scala 27:72] wire [63:0] _T_4776 = _GEN_393 | _T_4772; // @[Mux.scala 27:72] - wire _T_4871 = obuf_valid & obuf_write; // @[el2_lsu_bus_buffer.scala 622:36] - wire _T_4872 = ~obuf_cmd_done; // @[el2_lsu_bus_buffer.scala 622:51] - wire _T_4873 = _T_4871 & _T_4872; // @[el2_lsu_bus_buffer.scala 622:49] + wire _T_4871 = obuf_valid & obuf_write; // @[el2_lsu_bus_buffer.scala 623:36] + wire _T_4872 = ~obuf_cmd_done; // @[el2_lsu_bus_buffer.scala 623:51] + wire _T_4873 = _T_4871 & _T_4872; // @[el2_lsu_bus_buffer.scala 623:49] wire [31:0] _T_4877 = {obuf_addr[31:3],3'h0}; // @[Cat.scala 29:58] wire [2:0] _T_4879 = {1'h0,obuf_sz}; // @[Cat.scala 29:58] - wire _T_4884 = ~obuf_data_done; // @[el2_lsu_bus_buffer.scala 634:50] - wire _T_4885 = _T_4871 & _T_4884; // @[el2_lsu_bus_buffer.scala 634:48] + wire _T_4884 = ~obuf_data_done; // @[el2_lsu_bus_buffer.scala 635:50] + wire _T_4885 = _T_4871 & _T_4884; // @[el2_lsu_bus_buffer.scala 635:48] wire [7:0] _T_4889 = obuf_write ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire _T_4892 = obuf_valid & _T_1343; // @[el2_lsu_bus_buffer.scala 639:36] - wire _T_4894 = _T_4892 & _T_1349; // @[el2_lsu_bus_buffer.scala 639:50] - wire _T_4906 = io_lsu_bus_clk_en_q & buf_error[0]; // @[el2_lsu_bus_buffer.scala 652:114] - wire _T_4908 = _T_4906 & buf_write[0]; // @[el2_lsu_bus_buffer.scala 652:129] - wire _T_4911 = io_lsu_bus_clk_en_q & buf_error[1]; // @[el2_lsu_bus_buffer.scala 652:114] - wire _T_4913 = _T_4911 & buf_write[1]; // @[el2_lsu_bus_buffer.scala 652:129] - wire _T_4916 = io_lsu_bus_clk_en_q & buf_error[2]; // @[el2_lsu_bus_buffer.scala 652:114] - wire _T_4918 = _T_4916 & buf_write[2]; // @[el2_lsu_bus_buffer.scala 652:129] - wire _T_4921 = io_lsu_bus_clk_en_q & buf_error[3]; // @[el2_lsu_bus_buffer.scala 652:114] - wire _T_4923 = _T_4921 & buf_write[3]; // @[el2_lsu_bus_buffer.scala 652:129] + wire _T_4892 = obuf_valid & _T_1343; // @[el2_lsu_bus_buffer.scala 640:36] + wire _T_4894 = _T_4892 & _T_1349; // @[el2_lsu_bus_buffer.scala 640:50] + wire _T_4906 = io_lsu_bus_clk_en_q & buf_error[0]; // @[el2_lsu_bus_buffer.scala 653:114] + wire _T_4908 = _T_4906 & buf_write[0]; // @[el2_lsu_bus_buffer.scala 653:129] + wire _T_4911 = io_lsu_bus_clk_en_q & buf_error[1]; // @[el2_lsu_bus_buffer.scala 653:114] + wire _T_4913 = _T_4911 & buf_write[1]; // @[el2_lsu_bus_buffer.scala 653:129] + wire _T_4916 = io_lsu_bus_clk_en_q & buf_error[2]; // @[el2_lsu_bus_buffer.scala 653:114] + wire _T_4918 = _T_4916 & buf_write[2]; // @[el2_lsu_bus_buffer.scala 653:129] + wire _T_4921 = io_lsu_bus_clk_en_q & buf_error[3]; // @[el2_lsu_bus_buffer.scala 653:114] + wire _T_4923 = _T_4921 & buf_write[3]; // @[el2_lsu_bus_buffer.scala 653:129] wire _T_4924 = _T_2799 & _T_4908; // @[Mux.scala 27:72] wire _T_4925 = _T_2821 & _T_4913; // @[Mux.scala 27:72] wire _T_4926 = _T_2843 & _T_4918; // @[Mux.scala 27:72] wire _T_4927 = _T_2865 & _T_4923; // @[Mux.scala 27:72] wire _T_4928 = _T_4924 | _T_4925; // @[Mux.scala 27:72] wire _T_4929 = _T_4928 | _T_4926; // @[Mux.scala 27:72] - wire _T_4939 = _T_2821 & buf_error[1]; // @[el2_lsu_bus_buffer.scala 653:93] - wire _T_4941 = _T_4939 & buf_write[1]; // @[el2_lsu_bus_buffer.scala 653:108] - wire _T_4944 = _T_2843 & buf_error[2]; // @[el2_lsu_bus_buffer.scala 653:93] - wire _T_4946 = _T_4944 & buf_write[2]; // @[el2_lsu_bus_buffer.scala 653:108] - wire _T_4949 = _T_2865 & buf_error[3]; // @[el2_lsu_bus_buffer.scala 653:93] - wire _T_4951 = _T_4949 & buf_write[3]; // @[el2_lsu_bus_buffer.scala 653:108] + wire _T_4939 = _T_2821 & buf_error[1]; // @[el2_lsu_bus_buffer.scala 654:93] + wire _T_4941 = _T_4939 & buf_write[1]; // @[el2_lsu_bus_buffer.scala 654:108] + wire _T_4944 = _T_2843 & buf_error[2]; // @[el2_lsu_bus_buffer.scala 654:93] + wire _T_4946 = _T_4944 & buf_write[2]; // @[el2_lsu_bus_buffer.scala 654:108] + wire _T_4949 = _T_2865 & buf_error[3]; // @[el2_lsu_bus_buffer.scala 654:93] + wire _T_4951 = _T_4949 & buf_write[3]; // @[el2_lsu_bus_buffer.scala 654:108] wire [1:0] _T_4954 = _T_4946 ? 2'h2 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_4955 = _T_4951 ? 2'h3 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _GEN_394 = {{1'd0}, _T_4941}; // @[Mux.scala 27:72] wire [1:0] _T_4957 = _GEN_394 | _T_4954; // @[Mux.scala 27:72] wire [1:0] lsu_imprecise_error_store_tag = _T_4957 | _T_4955; // @[Mux.scala 27:72] - wire _T_4959 = ~io_lsu_imprecise_error_store_any; // @[el2_lsu_bus_buffer.scala 655:72] - wire [31:0] _GEN_351 = 2'h1 == lsu_imprecise_error_store_tag ? buf_addr_1 : buf_addr_0; // @[el2_lsu_bus_buffer.scala 656:41] - wire [31:0] _GEN_352 = 2'h2 == lsu_imprecise_error_store_tag ? buf_addr_2 : _GEN_351; // @[el2_lsu_bus_buffer.scala 656:41] - wire [31:0] _GEN_353 = 2'h3 == lsu_imprecise_error_store_tag ? buf_addr_3 : _GEN_352; // @[el2_lsu_bus_buffer.scala 656:41] - wire [31:0] _GEN_355 = 2'h1 == io_lsu_nonblock_load_data_tag ? buf_addr_1 : buf_addr_0; // @[el2_lsu_bus_buffer.scala 656:41] - wire [31:0] _GEN_356 = 2'h2 == io_lsu_nonblock_load_data_tag ? buf_addr_2 : _GEN_355; // @[el2_lsu_bus_buffer.scala 656:41] - wire [31:0] _GEN_357 = 2'h3 == io_lsu_nonblock_load_data_tag ? buf_addr_3 : _GEN_356; // @[el2_lsu_bus_buffer.scala 656:41] - wire _T_4964 = bus_wcmd_sent | bus_wdata_sent; // @[el2_lsu_bus_buffer.scala 662:68] - wire _T_4967 = io_lsu_busreq_r & io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 663:48] - wire _T_4970 = ~io_lsu_axi_awready; // @[el2_lsu_bus_buffer.scala 666:48] - wire _T_4971 = io_lsu_axi_awvalid & _T_4970; // @[el2_lsu_bus_buffer.scala 666:46] - wire _T_4972 = ~io_lsu_axi_wready; // @[el2_lsu_bus_buffer.scala 666:92] - wire _T_4973 = io_lsu_axi_wvalid & _T_4972; // @[el2_lsu_bus_buffer.scala 666:90] - wire _T_4974 = _T_4971 | _T_4973; // @[el2_lsu_bus_buffer.scala 666:69] - wire _T_4975 = ~io_lsu_axi_arready; // @[el2_lsu_bus_buffer.scala 666:136] - wire _T_4976 = io_lsu_axi_arvalid & _T_4975; // @[el2_lsu_bus_buffer.scala 666:134] - wire _T_4980 = ~io_flush_r; // @[el2_lsu_bus_buffer.scala 670:75] - wire _T_4981 = io_lsu_busreq_m & _T_4980; // @[el2_lsu_bus_buffer.scala 670:73] - reg _T_4984; // @[el2_lsu_bus_buffer.scala 670:56] + wire _T_4959 = ~io_lsu_imprecise_error_store_any; // @[el2_lsu_bus_buffer.scala 656:72] + wire [31:0] _GEN_351 = 2'h1 == lsu_imprecise_error_store_tag ? buf_addr_1 : buf_addr_0; // @[el2_lsu_bus_buffer.scala 657:41] + wire [31:0] _GEN_352 = 2'h2 == lsu_imprecise_error_store_tag ? buf_addr_2 : _GEN_351; // @[el2_lsu_bus_buffer.scala 657:41] + wire [31:0] _GEN_353 = 2'h3 == lsu_imprecise_error_store_tag ? buf_addr_3 : _GEN_352; // @[el2_lsu_bus_buffer.scala 657:41] + wire [31:0] _GEN_355 = 2'h1 == io_lsu_nonblock_load_data_tag ? buf_addr_1 : buf_addr_0; // @[el2_lsu_bus_buffer.scala 657:41] + wire [31:0] _GEN_356 = 2'h2 == io_lsu_nonblock_load_data_tag ? buf_addr_2 : _GEN_355; // @[el2_lsu_bus_buffer.scala 657:41] + wire [31:0] _GEN_357 = 2'h3 == io_lsu_nonblock_load_data_tag ? buf_addr_3 : _GEN_356; // @[el2_lsu_bus_buffer.scala 657:41] + wire _T_4964 = bus_wcmd_sent | bus_wdata_sent; // @[el2_lsu_bus_buffer.scala 663:68] + wire _T_4967 = io_lsu_busreq_r & io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 664:48] + wire _T_4970 = ~io_lsu_axi_awready; // @[el2_lsu_bus_buffer.scala 667:48] + wire _T_4971 = io_lsu_axi_awvalid & _T_4970; // @[el2_lsu_bus_buffer.scala 667:46] + wire _T_4972 = ~io_lsu_axi_wready; // @[el2_lsu_bus_buffer.scala 667:92] + wire _T_4973 = io_lsu_axi_wvalid & _T_4972; // @[el2_lsu_bus_buffer.scala 667:90] + wire _T_4974 = _T_4971 | _T_4973; // @[el2_lsu_bus_buffer.scala 667:69] + wire _T_4975 = ~io_lsu_axi_arready; // @[el2_lsu_bus_buffer.scala 667:136] + wire _T_4976 = io_lsu_axi_arvalid & _T_4975; // @[el2_lsu_bus_buffer.scala 667:134] + wire _T_4980 = ~io_flush_r; // @[el2_lsu_bus_buffer.scala 671:75] + wire _T_4981 = io_lsu_busreq_m & _T_4980; // @[el2_lsu_bus_buffer.scala 671:73] + reg _T_4984; // @[el2_lsu_bus_buffer.scala 671:56] rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), @@ -2654,46 +2699,46 @@ module el2_lsu_bus_buffer( .io_en(rvclkhdr_11_io_en), .io_scan_mode(rvclkhdr_11_io_scan_mode) ); - assign io_lsu_busreq_r = _T_4984; // @[el2_lsu_bus_buffer.scala 670:19] - assign io_lsu_bus_buffer_pend_any = |buf_numvld_pend_any; // @[el2_lsu_bus_buffer.scala 579:30] - assign io_lsu_bus_buffer_full_any = _T_4498 ? _T_4499 : _T_4500; // @[el2_lsu_bus_buffer.scala 580:30] - assign io_lsu_bus_buffer_empty_any = _T_4511 & _T_1231; // @[el2_lsu_bus_buffer.scala 581:31] - assign io_ld_byte_hit_buf_lo = {_T_69,_T_58}; // @[el2_lsu_bus_buffer.scala 191:25] - assign io_ld_byte_hit_buf_hi = {_T_84,_T_73}; // @[el2_lsu_bus_buffer.scala 192:25] - assign io_ld_fwddata_buf_lo = _T_650 | _T_651; // @[el2_lsu_bus_buffer.scala 218:24] - assign io_ld_fwddata_buf_hi = _T_747 | _T_748; // @[el2_lsu_bus_buffer.scala 224:24] - assign io_lsu_imprecise_error_load_any = io_lsu_nonblock_load_data_error & _T_4959; // @[el2_lsu_bus_buffer.scala 655:35] - assign io_lsu_imprecise_error_store_any = _T_4929 | _T_4927; // @[el2_lsu_bus_buffer.scala 652:36] - assign io_lsu_imprecise_error_addr_any = io_lsu_imprecise_error_store_any ? _GEN_353 : _GEN_357; // @[el2_lsu_bus_buffer.scala 656:35] - assign io_lsu_nonblock_load_valid_m = _T_4517 & _T_4518; // @[el2_lsu_bus_buffer.scala 583:32] - assign io_lsu_nonblock_load_tag_m = _T_1863 ? 2'h0 : _T_1899; // @[el2_lsu_bus_buffer.scala 584:30] - assign io_lsu_nonblock_load_inv_r = lsu_nonblock_load_valid_r & _T_4520; // @[el2_lsu_bus_buffer.scala 586:30] - assign io_lsu_nonblock_load_inv_tag_r = WrPtr0_r; // @[el2_lsu_bus_buffer.scala 587:34] - assign io_lsu_nonblock_load_data_valid = lsu_nonblock_load_data_ready & _T_4741; // @[el2_lsu_bus_buffer.scala 599:35] - assign io_lsu_nonblock_load_data_error = _T_4570 | _T_4568; // @[el2_lsu_bus_buffer.scala 589:35] - assign io_lsu_nonblock_load_data_tag = _T_4610 | _T_4608; // @[el2_lsu_bus_buffer.scala 590:33] - assign io_lsu_nonblock_load_data = _T_4776[31:0]; // @[el2_lsu_bus_buffer.scala 600:29] - assign io_lsu_pmu_bus_trxn = _T_4964 | _T_4863; // @[el2_lsu_bus_buffer.scala 662:23] - assign io_lsu_pmu_bus_misaligned = _T_4967 & io_lsu_commit_r; // @[el2_lsu_bus_buffer.scala 663:29] - assign io_lsu_pmu_bus_error = io_lsu_imprecise_error_load_any | io_lsu_imprecise_error_store_any; // @[el2_lsu_bus_buffer.scala 664:24] - assign io_lsu_pmu_bus_busy = _T_4974 | _T_4976; // @[el2_lsu_bus_buffer.scala 666:23] - assign io_lsu_axi_awvalid = _T_4873 & _T_1239; // @[el2_lsu_bus_buffer.scala 622:22] - assign io_lsu_axi_awid = {{1'd0}, _T_1848}; // @[el2_lsu_bus_buffer.scala 623:19] - assign io_lsu_axi_awaddr = obuf_sideeffect ? obuf_addr : _T_4877; // @[el2_lsu_bus_buffer.scala 624:21] - assign io_lsu_axi_awregion = obuf_addr[31:28]; // @[el2_lsu_bus_buffer.scala 628:23] - assign io_lsu_axi_awsize = obuf_sideeffect ? _T_4879 : 3'h3; // @[el2_lsu_bus_buffer.scala 625:21] - assign io_lsu_axi_awcache = obuf_sideeffect ? 4'h0 : 4'hf; // @[el2_lsu_bus_buffer.scala 627:22] - assign io_lsu_axi_wvalid = _T_4885 & _T_1239; // @[el2_lsu_bus_buffer.scala 634:21] - assign io_lsu_axi_wdata = obuf_data; // @[el2_lsu_bus_buffer.scala 636:20] - assign io_lsu_axi_wstrb = obuf_byteen & _T_4889; // @[el2_lsu_bus_buffer.scala 635:20] - assign io_lsu_axi_bready = 1'h1; // @[el2_lsu_bus_buffer.scala 650:21] - assign io_lsu_axi_arvalid = _T_4894 & _T_1239; // @[el2_lsu_bus_buffer.scala 639:22] - assign io_lsu_axi_arid = {{1'd0}, _T_1848}; // @[el2_lsu_bus_buffer.scala 640:19] - assign io_lsu_axi_araddr = obuf_sideeffect ? obuf_addr : _T_4877; // @[el2_lsu_bus_buffer.scala 641:21] - assign io_lsu_axi_arregion = obuf_addr[31:28]; // @[el2_lsu_bus_buffer.scala 645:23] - assign io_lsu_axi_arsize = obuf_sideeffect ? _T_4879 : 3'h3; // @[el2_lsu_bus_buffer.scala 642:21] - assign io_lsu_axi_arcache = obuf_sideeffect ? 4'h0 : 4'hf; // @[el2_lsu_bus_buffer.scala 644:22] - assign io_lsu_axi_rready = 1'h1; // @[el2_lsu_bus_buffer.scala 651:21] + assign io_lsu_busreq_r = _T_4984; // @[el2_lsu_bus_buffer.scala 671:19] + assign io_lsu_bus_buffer_pend_any = |buf_numvld_pend_any; // @[el2_lsu_bus_buffer.scala 580:30] + assign io_lsu_bus_buffer_full_any = _T_4498 ? _T_4499 : _T_4500; // @[el2_lsu_bus_buffer.scala 581:30] + assign io_lsu_bus_buffer_empty_any = _T_4511 & _T_1231; // @[el2_lsu_bus_buffer.scala 582:31] + assign io_ld_byte_hit_buf_lo = {_T_69,_T_58}; // @[el2_lsu_bus_buffer.scala 192:25] + assign io_ld_byte_hit_buf_hi = {_T_84,_T_73}; // @[el2_lsu_bus_buffer.scala 193:25] + assign io_ld_fwddata_buf_lo = _T_650 | _T_651; // @[el2_lsu_bus_buffer.scala 219:24] + assign io_ld_fwddata_buf_hi = _T_747 | _T_748; // @[el2_lsu_bus_buffer.scala 225:24] + assign io_lsu_imprecise_error_load_any = io_lsu_nonblock_load_data_error & _T_4959; // @[el2_lsu_bus_buffer.scala 656:35] + assign io_lsu_imprecise_error_store_any = _T_4929 | _T_4927; // @[el2_lsu_bus_buffer.scala 653:36] + assign io_lsu_imprecise_error_addr_any = io_lsu_imprecise_error_store_any ? _GEN_353 : _GEN_357; // @[el2_lsu_bus_buffer.scala 657:35] + assign io_lsu_nonblock_load_valid_m = _T_4517 & _T_4518; // @[el2_lsu_bus_buffer.scala 584:32] + assign io_lsu_nonblock_load_tag_m = _T_1863 ? 2'h0 : _T_1899; // @[el2_lsu_bus_buffer.scala 585:30] + assign io_lsu_nonblock_load_inv_r = lsu_nonblock_load_valid_r & _T_4520; // @[el2_lsu_bus_buffer.scala 587:30] + assign io_lsu_nonblock_load_inv_tag_r = WrPtr0_r; // @[el2_lsu_bus_buffer.scala 588:34] + assign io_lsu_nonblock_load_data_valid = lsu_nonblock_load_data_ready & _T_4741; // @[el2_lsu_bus_buffer.scala 600:35] + assign io_lsu_nonblock_load_data_error = _T_4570 | _T_4568; // @[el2_lsu_bus_buffer.scala 590:35] + assign io_lsu_nonblock_load_data_tag = _T_4610 | _T_4608; // @[el2_lsu_bus_buffer.scala 591:33] + assign io_lsu_nonblock_load_data = _T_4776[31:0]; // @[el2_lsu_bus_buffer.scala 601:29] + assign io_lsu_pmu_bus_trxn = _T_4964 | _T_4863; // @[el2_lsu_bus_buffer.scala 663:23] + assign io_lsu_pmu_bus_misaligned = _T_4967 & io_lsu_commit_r; // @[el2_lsu_bus_buffer.scala 664:29] + assign io_lsu_pmu_bus_error = io_lsu_imprecise_error_load_any | io_lsu_imprecise_error_store_any; // @[el2_lsu_bus_buffer.scala 665:24] + assign io_lsu_pmu_bus_busy = _T_4974 | _T_4976; // @[el2_lsu_bus_buffer.scala 667:23] + assign io_lsu_axi_awvalid = _T_4873 & _T_1239; // @[el2_lsu_bus_buffer.scala 623:22] + assign io_lsu_axi_awid = {{1'd0}, _T_1848}; // @[el2_lsu_bus_buffer.scala 624:19] + assign io_lsu_axi_awaddr = obuf_sideeffect ? obuf_addr : _T_4877; // @[el2_lsu_bus_buffer.scala 625:21] + assign io_lsu_axi_awregion = obuf_addr[31:28]; // @[el2_lsu_bus_buffer.scala 629:23] + assign io_lsu_axi_awsize = obuf_sideeffect ? _T_4879 : 3'h3; // @[el2_lsu_bus_buffer.scala 626:21] + assign io_lsu_axi_awcache = obuf_sideeffect ? 4'h0 : 4'hf; // @[el2_lsu_bus_buffer.scala 628:22] + assign io_lsu_axi_wvalid = _T_4885 & _T_1239; // @[el2_lsu_bus_buffer.scala 635:21] + assign io_lsu_axi_wdata = obuf_data; // @[el2_lsu_bus_buffer.scala 637:20] + assign io_lsu_axi_wstrb = obuf_byteen & _T_4889; // @[el2_lsu_bus_buffer.scala 636:20] + assign io_lsu_axi_bready = 1'h1; // @[el2_lsu_bus_buffer.scala 651:21] + assign io_lsu_axi_arvalid = _T_4894 & _T_1239; // @[el2_lsu_bus_buffer.scala 640:22] + assign io_lsu_axi_arid = {{1'd0}, _T_1848}; // @[el2_lsu_bus_buffer.scala 641:19] + assign io_lsu_axi_araddr = obuf_sideeffect ? obuf_addr : _T_4877; // @[el2_lsu_bus_buffer.scala 642:21] + assign io_lsu_axi_arregion = obuf_addr[31:28]; // @[el2_lsu_bus_buffer.scala 646:23] + assign io_lsu_axi_arsize = obuf_sideeffect ? _T_4879 : 3'h3; // @[el2_lsu_bus_buffer.scala 643:21] + assign io_lsu_axi_arcache = obuf_sideeffect ? 4'h0 : 4'hf; // @[el2_lsu_bus_buffer.scala 645:22] + assign io_lsu_axi_rready = 1'h1; // @[el2_lsu_bus_buffer.scala 652:21] assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18] assign rvclkhdr_io_en = _T_853 & _T_854; // @[el2_lib.scala 511:17] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] @@ -3675,7 +3720,7 @@ end // initial if (ibuf_buf_byp) begin obuf_tag1 <= WrPtr1_r; end else begin - obuf_tag1 <= 2'h0; + obuf_tag1 <= CmdPtr1; end end end @@ -3706,7 +3751,7 @@ end // initial if (reset) begin ibuf_write <= 1'h0; end else if (ibuf_wr_en) begin - ibuf_write <= io_lsu_pkt_r_store; + ibuf_write <= io_lsu_pkt_r_bits_store; end end always @(posedge io_lsu_free_c2_clk or posedge reset) begin @@ -3976,7 +4021,7 @@ end // initial if (reset) begin ibuf_unsign <= 1'h0; end else if (ibuf_wr_en) begin - ibuf_unsign <= io_lsu_pkt_r_unsign; + ibuf_unsign <= io_lsu_pkt_r_bits_unsign; end end always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin @@ -4112,7 +4157,7 @@ end // initial obuf_write <= 1'h0; end else if (obuf_wr_en) begin if (ibuf_buf_byp) begin - obuf_write <= io_lsu_pkt_r_store; + obuf_write <= io_lsu_pkt_r_bits_store; end else begin obuf_write <= _T_1202; end @@ -4551,32 +4596,32 @@ module el2_lsu_bus_intf( input io_lsu_busm_clk, input io_dec_lsu_valid_raw_d, input io_lsu_busreq_m, - input io_lsu_pkt_m_fast_int, - input io_lsu_pkt_m_by, - input io_lsu_pkt_m_half, - input io_lsu_pkt_m_word, - input io_lsu_pkt_m_dword, - input io_lsu_pkt_m_load, - input io_lsu_pkt_m_store, - input io_lsu_pkt_m_unsign, - input io_lsu_pkt_m_dma, - input io_lsu_pkt_m_store_data_bypass_d, - input io_lsu_pkt_m_load_ldst_bypass_d, - input io_lsu_pkt_m_store_data_bypass_m, input io_lsu_pkt_m_valid, - input io_lsu_pkt_r_fast_int, - input io_lsu_pkt_r_by, - input io_lsu_pkt_r_half, - input io_lsu_pkt_r_word, - input io_lsu_pkt_r_dword, - input io_lsu_pkt_r_load, - input io_lsu_pkt_r_store, - input io_lsu_pkt_r_unsign, - input io_lsu_pkt_r_dma, - input io_lsu_pkt_r_store_data_bypass_d, - input io_lsu_pkt_r_load_ldst_bypass_d, - input io_lsu_pkt_r_store_data_bypass_m, + input io_lsu_pkt_m_bits_fast_int, + input io_lsu_pkt_m_bits_by, + input io_lsu_pkt_m_bits_half, + input io_lsu_pkt_m_bits_word, + input io_lsu_pkt_m_bits_dword, + input io_lsu_pkt_m_bits_load, + input io_lsu_pkt_m_bits_store, + input io_lsu_pkt_m_bits_unsign, + input io_lsu_pkt_m_bits_dma, + input io_lsu_pkt_m_bits_store_data_bypass_d, + input io_lsu_pkt_m_bits_load_ldst_bypass_d, + input io_lsu_pkt_m_bits_store_data_bypass_m, input io_lsu_pkt_r_valid, + input io_lsu_pkt_r_bits_fast_int, + input io_lsu_pkt_r_bits_by, + input io_lsu_pkt_r_bits_half, + input io_lsu_pkt_r_bits_word, + input io_lsu_pkt_r_bits_dword, + input io_lsu_pkt_r_bits_load, + input io_lsu_pkt_r_bits_store, + input io_lsu_pkt_r_bits_unsign, + input io_lsu_pkt_r_bits_dma, + input io_lsu_pkt_r_bits_store_data_bypass_d, + input io_lsu_pkt_r_bits_load_ldst_bypass_d, + input io_lsu_pkt_r_bits_store_data_bypass_m, input [31:0] io_lsu_addr_d, input [31:0] io_lsu_addr_m, input [31:0] io_lsu_addr_r, @@ -4672,14 +4717,14 @@ module el2_lsu_bus_intf( wire bus_buffer_io_lsu_free_c2_clk; // @[el2_lsu_bus_intf.scala 167:39] wire bus_buffer_io_lsu_busm_clk; // @[el2_lsu_bus_intf.scala 167:39] wire bus_buffer_io_dec_lsu_valid_raw_d; // @[el2_lsu_bus_intf.scala 167:39] - wire bus_buffer_io_lsu_pkt_m_load; // @[el2_lsu_bus_intf.scala 167:39] wire bus_buffer_io_lsu_pkt_m_valid; // @[el2_lsu_bus_intf.scala 167:39] - wire bus_buffer_io_lsu_pkt_r_by; // @[el2_lsu_bus_intf.scala 167:39] - wire bus_buffer_io_lsu_pkt_r_half; // @[el2_lsu_bus_intf.scala 167:39] - wire bus_buffer_io_lsu_pkt_r_word; // @[el2_lsu_bus_intf.scala 167:39] - wire bus_buffer_io_lsu_pkt_r_load; // @[el2_lsu_bus_intf.scala 167:39] - wire bus_buffer_io_lsu_pkt_r_store; // @[el2_lsu_bus_intf.scala 167:39] - wire bus_buffer_io_lsu_pkt_r_unsign; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_pkt_m_bits_load; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_pkt_r_bits_by; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_pkt_r_bits_half; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_pkt_r_bits_word; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_pkt_r_bits_load; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_pkt_r_bits_store; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_pkt_r_bits_unsign; // @[el2_lsu_bus_intf.scala 167:39] wire [31:0] bus_buffer_io_lsu_addr_m; // @[el2_lsu_bus_intf.scala 167:39] wire [31:0] bus_buffer_io_end_addr_m; // @[el2_lsu_bus_intf.scala 167:39] wire [31:0] bus_buffer_io_lsu_addr_r; // @[el2_lsu_bus_intf.scala 167:39] @@ -4748,9 +4793,9 @@ module el2_lsu_bus_intf( wire [2:0] bus_buffer_io_lsu_axi_arsize; // @[el2_lsu_bus_intf.scala 167:39] wire [3:0] bus_buffer_io_lsu_axi_arcache; // @[el2_lsu_bus_intf.scala 167:39] wire bus_buffer_io_lsu_axi_rready; // @[el2_lsu_bus_intf.scala 167:39] - wire [3:0] _T_3 = io_lsu_pkt_m_word ? 4'hf : 4'h0; // @[Mux.scala 27:72] - wire [3:0] _T_4 = io_lsu_pkt_m_half ? 4'h3 : 4'h0; // @[Mux.scala 27:72] - wire [3:0] _T_5 = io_lsu_pkt_m_by ? 4'h1 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_3 = io_lsu_pkt_m_bits_word ? 4'hf : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_4 = io_lsu_pkt_m_bits_half ? 4'h3 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_5 = io_lsu_pkt_m_bits_by ? 4'h1 : 4'h0; // @[Mux.scala 27:72] wire [3:0] _T_6 = _T_3 | _T_4; // @[Mux.scala 27:72] wire [3:0] ldst_byteen_m = _T_6 | _T_5; // @[Mux.scala 27:72] wire addr_match_dw_lo_r_m = io_lsu_addr_r[31:3] == io_lsu_addr_m[31:3]; // @[el2_lsu_bus_intf.scala 278:51] @@ -4761,10 +4806,10 @@ module el2_lsu_bus_intf( wire _T_20 = ~ldst_dual_r; // @[el2_lsu_bus_intf.scala 280:48] wire _T_21 = io_lsu_busreq_r & _T_20; // @[el2_lsu_bus_intf.scala 280:46] wire _T_22 = _T_21 & io_lsu_busreq_m; // @[el2_lsu_bus_intf.scala 280:61] - wire _T_23 = ~addr_match_word_lo_r_m; // @[el2_lsu_bus_intf.scala 280:102] - wire _T_24 = io_lsu_pkt_m_load | _T_23; // @[el2_lsu_bus_intf.scala 280:100] - wire _T_29 = ~addr_match_dw_lo_r_m; // @[el2_lsu_bus_intf.scala 281:102] - wire _T_30 = io_lsu_pkt_m_load | _T_29; // @[el2_lsu_bus_intf.scala 281:100] + wire _T_23 = ~addr_match_word_lo_r_m; // @[el2_lsu_bus_intf.scala 280:107] + wire _T_24 = io_lsu_pkt_m_bits_load | _T_23; // @[el2_lsu_bus_intf.scala 280:105] + wire _T_29 = ~addr_match_dw_lo_r_m; // @[el2_lsu_bus_intf.scala 281:107] + wire _T_30 = io_lsu_pkt_m_bits_load | _T_29; // @[el2_lsu_bus_intf.scala 281:105] wire [6:0] _GEN_0 = {{3'd0}, ldst_byteen_m}; // @[el2_lsu_bus_intf.scala 283:49] wire [6:0] _T_34 = _GEN_0 << io_lsu_addr_m[1:0]; // @[el2_lsu_bus_intf.scala 283:49] reg [3:0] ldst_byteen_r; // @[el2_lsu_bus_intf.scala 326:33] @@ -4784,20 +4829,20 @@ module el2_lsu_bus_intf( wire [31:0] store_data_lo_r = store_data_ext_r[31:0]; // @[el2_lsu_bus_intf.scala 292:46] wire _T_50 = io_lsu_addr_m[31:2] == io_lsu_addr_r[31:2]; // @[el2_lsu_bus_intf.scala 293:51] wire _T_51 = _T_50 & io_lsu_pkt_r_valid; // @[el2_lsu_bus_intf.scala 293:76] - wire _T_52 = _T_51 & io_lsu_pkt_r_store; // @[el2_lsu_bus_intf.scala 293:97] - wire ld_addr_rhit_lo_lo = _T_52 & io_lsu_busreq_m; // @[el2_lsu_bus_intf.scala 293:118] + wire _T_52 = _T_51 & io_lsu_pkt_r_bits_store; // @[el2_lsu_bus_intf.scala 293:97] + wire ld_addr_rhit_lo_lo = _T_52 & io_lsu_busreq_m; // @[el2_lsu_bus_intf.scala 293:123] wire _T_56 = io_end_addr_m[31:2] == io_lsu_addr_r[31:2]; // @[el2_lsu_bus_intf.scala 294:51] wire _T_57 = _T_56 & io_lsu_pkt_r_valid; // @[el2_lsu_bus_intf.scala 294:76] - wire _T_58 = _T_57 & io_lsu_pkt_r_store; // @[el2_lsu_bus_intf.scala 294:97] - wire ld_addr_rhit_lo_hi = _T_58 & io_lsu_busreq_m; // @[el2_lsu_bus_intf.scala 294:118] + wire _T_58 = _T_57 & io_lsu_pkt_r_bits_store; // @[el2_lsu_bus_intf.scala 294:97] + wire ld_addr_rhit_lo_hi = _T_58 & io_lsu_busreq_m; // @[el2_lsu_bus_intf.scala 294:123] wire _T_62 = io_lsu_addr_m[31:2] == io_end_addr_r[31:2]; // @[el2_lsu_bus_intf.scala 295:51] wire _T_63 = _T_62 & io_lsu_pkt_r_valid; // @[el2_lsu_bus_intf.scala 295:76] - wire _T_64 = _T_63 & io_lsu_pkt_r_store; // @[el2_lsu_bus_intf.scala 295:97] - wire ld_addr_rhit_hi_lo = _T_64 & io_lsu_busreq_m; // @[el2_lsu_bus_intf.scala 295:118] + wire _T_64 = _T_63 & io_lsu_pkt_r_bits_store; // @[el2_lsu_bus_intf.scala 295:97] + wire ld_addr_rhit_hi_lo = _T_64 & io_lsu_busreq_m; // @[el2_lsu_bus_intf.scala 295:123] wire _T_68 = io_end_addr_m[31:2] == io_end_addr_r[31:2]; // @[el2_lsu_bus_intf.scala 296:51] wire _T_69 = _T_68 & io_lsu_pkt_r_valid; // @[el2_lsu_bus_intf.scala 296:76] - wire _T_70 = _T_69 & io_lsu_pkt_r_store; // @[el2_lsu_bus_intf.scala 296:97] - wire ld_addr_rhit_hi_hi = _T_70 & io_lsu_busreq_m; // @[el2_lsu_bus_intf.scala 296:118] + wire _T_70 = _T_69 & io_lsu_pkt_r_bits_store; // @[el2_lsu_bus_intf.scala 296:97] + wire ld_addr_rhit_hi_hi = _T_70 & io_lsu_busreq_m; // @[el2_lsu_bus_intf.scala 296:123] wire _T_73 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[0]; // @[el2_lsu_bus_intf.scala 298:70] wire _T_75 = _T_73 & ldst_byteen_lo_m[0]; // @[el2_lsu_bus_intf.scala 298:92] wire _T_77 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[1]; // @[el2_lsu_bus_intf.scala 298:70] @@ -4918,8 +4963,8 @@ module el2_lsu_bus_intf( wire ld_full_hit_hi_m = _T_368 & _T_366; // @[el2_lsu_bus_intf.scala 312:111] wire _T_370 = ld_full_hit_lo_m & ld_full_hit_hi_m; // @[el2_lsu_bus_intf.scala 313:47] wire _T_371 = _T_370 & io_lsu_busreq_m; // @[el2_lsu_bus_intf.scala 313:66] - wire _T_372 = _T_371 & io_lsu_pkt_m_load; // @[el2_lsu_bus_intf.scala 313:84] - wire _T_373 = ~io_is_sideeffects_m; // @[el2_lsu_bus_intf.scala 313:106] + wire _T_372 = _T_371 & io_lsu_pkt_m_bits_load; // @[el2_lsu_bus_intf.scala 313:84] + wire _T_373 = ~io_is_sideeffects_m; // @[el2_lsu_bus_intf.scala 313:111] wire [63:0] ld_fwddata_hi = {{32'd0}, _T_331}; // @[el2_lsu_bus_intf.scala 310:27] wire [63:0] ld_fwddata_lo = {{32'd0}, _T_312}; // @[el2_lsu_bus_intf.scala 309:27] wire [63:0] _T_377 = {ld_fwddata_hi[31:0],ld_fwddata_lo[31:0]}; // @[Cat.scala 29:58] @@ -4944,14 +4989,14 @@ module el2_lsu_bus_intf( .io_lsu_free_c2_clk(bus_buffer_io_lsu_free_c2_clk), .io_lsu_busm_clk(bus_buffer_io_lsu_busm_clk), .io_dec_lsu_valid_raw_d(bus_buffer_io_dec_lsu_valid_raw_d), - .io_lsu_pkt_m_load(bus_buffer_io_lsu_pkt_m_load), .io_lsu_pkt_m_valid(bus_buffer_io_lsu_pkt_m_valid), - .io_lsu_pkt_r_by(bus_buffer_io_lsu_pkt_r_by), - .io_lsu_pkt_r_half(bus_buffer_io_lsu_pkt_r_half), - .io_lsu_pkt_r_word(bus_buffer_io_lsu_pkt_r_word), - .io_lsu_pkt_r_load(bus_buffer_io_lsu_pkt_r_load), - .io_lsu_pkt_r_store(bus_buffer_io_lsu_pkt_r_store), - .io_lsu_pkt_r_unsign(bus_buffer_io_lsu_pkt_r_unsign), + .io_lsu_pkt_m_bits_load(bus_buffer_io_lsu_pkt_m_bits_load), + .io_lsu_pkt_r_bits_by(bus_buffer_io_lsu_pkt_r_bits_by), + .io_lsu_pkt_r_bits_half(bus_buffer_io_lsu_pkt_r_bits_half), + .io_lsu_pkt_r_bits_word(bus_buffer_io_lsu_pkt_r_bits_word), + .io_lsu_pkt_r_bits_load(bus_buffer_io_lsu_pkt_r_bits_load), + .io_lsu_pkt_r_bits_store(bus_buffer_io_lsu_pkt_r_bits_store), + .io_lsu_pkt_r_bits_unsign(bus_buffer_io_lsu_pkt_r_bits_unsign), .io_lsu_addr_m(bus_buffer_io_lsu_addr_m), .io_end_addr_m(bus_buffer_io_end_addr_m), .io_lsu_addr_r(bus_buffer_io_lsu_addr_r), @@ -5084,14 +5129,14 @@ module el2_lsu_bus_intf( assign bus_buffer_io_lsu_free_c2_clk = io_lsu_free_c2_clk; // @[el2_lsu_bus_intf.scala 179:51] assign bus_buffer_io_lsu_busm_clk = io_lsu_busm_clk; // @[el2_lsu_bus_intf.scala 180:51] assign bus_buffer_io_dec_lsu_valid_raw_d = io_dec_lsu_valid_raw_d; // @[el2_lsu_bus_intf.scala 181:51] - assign bus_buffer_io_lsu_pkt_m_load = io_lsu_pkt_m_load; // @[el2_lsu_bus_intf.scala 184:27] assign bus_buffer_io_lsu_pkt_m_valid = io_lsu_pkt_m_valid; // @[el2_lsu_bus_intf.scala 184:27] - assign bus_buffer_io_lsu_pkt_r_by = io_lsu_pkt_r_by; // @[el2_lsu_bus_intf.scala 185:27] - assign bus_buffer_io_lsu_pkt_r_half = io_lsu_pkt_r_half; // @[el2_lsu_bus_intf.scala 185:27] - assign bus_buffer_io_lsu_pkt_r_word = io_lsu_pkt_r_word; // @[el2_lsu_bus_intf.scala 185:27] - assign bus_buffer_io_lsu_pkt_r_load = io_lsu_pkt_r_load; // @[el2_lsu_bus_intf.scala 185:27] - assign bus_buffer_io_lsu_pkt_r_store = io_lsu_pkt_r_store; // @[el2_lsu_bus_intf.scala 185:27] - assign bus_buffer_io_lsu_pkt_r_unsign = io_lsu_pkt_r_unsign; // @[el2_lsu_bus_intf.scala 185:27] + assign bus_buffer_io_lsu_pkt_m_bits_load = io_lsu_pkt_m_bits_load; // @[el2_lsu_bus_intf.scala 184:27] + assign bus_buffer_io_lsu_pkt_r_bits_by = io_lsu_pkt_r_bits_by; // @[el2_lsu_bus_intf.scala 185:27] + assign bus_buffer_io_lsu_pkt_r_bits_half = io_lsu_pkt_r_bits_half; // @[el2_lsu_bus_intf.scala 185:27] + assign bus_buffer_io_lsu_pkt_r_bits_word = io_lsu_pkt_r_bits_word; // @[el2_lsu_bus_intf.scala 185:27] + assign bus_buffer_io_lsu_pkt_r_bits_load = io_lsu_pkt_r_bits_load; // @[el2_lsu_bus_intf.scala 185:27] + assign bus_buffer_io_lsu_pkt_r_bits_store = io_lsu_pkt_r_bits_store; // @[el2_lsu_bus_intf.scala 185:27] + assign bus_buffer_io_lsu_pkt_r_bits_unsign = io_lsu_pkt_r_bits_unsign; // @[el2_lsu_bus_intf.scala 185:27] assign bus_buffer_io_lsu_addr_m = io_lsu_addr_m; // @[el2_lsu_bus_intf.scala 188:51] assign bus_buffer_io_end_addr_m = io_end_addr_m; // @[el2_lsu_bus_intf.scala 189:51] assign bus_buffer_io_lsu_addr_r = io_lsu_addr_r; // @[el2_lsu_bus_intf.scala 190:51] diff --git a/el2_lsu_clkdomain.anno.json b/el2_lsu_clkdomain.anno.json index 7a2b0823..67d03e54 100644 --- a/el2_lsu_clkdomain.anno.json +++ b/el2_lsu_clkdomain.anno.json @@ -5,8 +5,8 @@ }, { "class":"firrtl.transforms.BlackBoxResourceAnno", - "target":"el2_lsu_clkdomain.TEC_RV_ICG", - "resourceId":"/vsrc/TEC_RV_ICG.v" + "target":"el2_lsu_clkdomain.gated_latch", + "resourceId":"/vsrc/gated_latch.v" }, { "class":"firrtl.options.TargetDirAnnotation", diff --git a/el2_lsu_clkdomain.fir b/el2_lsu_clkdomain.fir index 9cad0413..0a29df60 100644 --- a/el2_lsu_clkdomain.fir +++ b/el2_lsu_clkdomain.fir @@ -1,12 +1,12 @@ ;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 circuit el2_lsu_clkdomain : - extmodule TEC_RV_ICG : + extmodule gated_latch : output Q : Clock input CK : Clock input EN : UInt<1> input SE : UInt<1> - defname = TEC_RV_ICG + defname = gated_latch module rvclkhdr : @@ -14,23 +14,23 @@ circuit el2_lsu_clkdomain : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of TEC_RV_ICG @[beh_lib.scala 332:24] + inst clkhdr of gated_latch @[el2_lib.scala 474:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12] - clkhdr.CK <= io.clk @[beh_lib.scala 334:16] - clkhdr.EN <= io.en @[beh_lib.scala 335:16] - clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16] + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] - extmodule TEC_RV_ICG_1 : + extmodule gated_latch_1 : output Q : Clock input CK : Clock input EN : UInt<1> input SE : UInt<1> - defname = TEC_RV_ICG + defname = gated_latch module rvclkhdr_1 : @@ -38,23 +38,23 @@ circuit el2_lsu_clkdomain : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of TEC_RV_ICG_1 @[beh_lib.scala 332:24] + inst clkhdr of gated_latch_1 @[el2_lib.scala 474:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12] - clkhdr.CK <= io.clk @[beh_lib.scala 334:16] - clkhdr.EN <= io.en @[beh_lib.scala 335:16] - clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16] + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] - extmodule TEC_RV_ICG_2 : + extmodule gated_latch_2 : output Q : Clock input CK : Clock input EN : UInt<1> input SE : UInt<1> - defname = TEC_RV_ICG + defname = gated_latch module rvclkhdr_2 : @@ -62,23 +62,23 @@ circuit el2_lsu_clkdomain : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of TEC_RV_ICG_2 @[beh_lib.scala 332:24] + inst clkhdr of gated_latch_2 @[el2_lib.scala 474:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12] - clkhdr.CK <= io.clk @[beh_lib.scala 334:16] - clkhdr.EN <= io.en @[beh_lib.scala 335:16] - clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16] + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] - extmodule TEC_RV_ICG_3 : + extmodule gated_latch_3 : output Q : Clock input CK : Clock input EN : UInt<1> input SE : UInt<1> - defname = TEC_RV_ICG + defname = gated_latch module rvclkhdr_3 : @@ -86,23 +86,23 @@ circuit el2_lsu_clkdomain : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of TEC_RV_ICG_3 @[beh_lib.scala 332:24] + inst clkhdr of gated_latch_3 @[el2_lib.scala 474:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12] - clkhdr.CK <= io.clk @[beh_lib.scala 334:16] - clkhdr.EN <= io.en @[beh_lib.scala 335:16] - clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16] + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] - extmodule TEC_RV_ICG_4 : + extmodule gated_latch_4 : output Q : Clock input CK : Clock input EN : UInt<1> input SE : UInt<1> - defname = TEC_RV_ICG + defname = gated_latch module rvclkhdr_4 : @@ -110,23 +110,23 @@ circuit el2_lsu_clkdomain : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of TEC_RV_ICG_4 @[beh_lib.scala 332:24] + inst clkhdr of gated_latch_4 @[el2_lib.scala 474:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12] - clkhdr.CK <= io.clk @[beh_lib.scala 334:16] - clkhdr.EN <= io.en @[beh_lib.scala 335:16] - clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16] + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] - extmodule TEC_RV_ICG_5 : + extmodule gated_latch_5 : output Q : Clock input CK : Clock input EN : UInt<1> input SE : UInt<1> - defname = TEC_RV_ICG + defname = gated_latch module rvclkhdr_5 : @@ -134,23 +134,23 @@ circuit el2_lsu_clkdomain : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of TEC_RV_ICG_5 @[beh_lib.scala 332:24] + inst clkhdr of gated_latch_5 @[el2_lib.scala 474:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12] - clkhdr.CK <= io.clk @[beh_lib.scala 334:16] - clkhdr.EN <= io.en @[beh_lib.scala 335:16] - clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16] + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] - extmodule TEC_RV_ICG_6 : + extmodule gated_latch_6 : output Q : Clock input CK : Clock input EN : UInt<1> input SE : UInt<1> - defname = TEC_RV_ICG + defname = gated_latch module rvclkhdr_6 : @@ -158,23 +158,23 @@ circuit el2_lsu_clkdomain : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of TEC_RV_ICG_6 @[beh_lib.scala 332:24] + inst clkhdr of gated_latch_6 @[el2_lib.scala 474:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12] - clkhdr.CK <= io.clk @[beh_lib.scala 334:16] - clkhdr.EN <= io.en @[beh_lib.scala 335:16] - clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16] + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] - extmodule TEC_RV_ICG_7 : + extmodule gated_latch_7 : output Q : Clock input CK : Clock input EN : UInt<1> input SE : UInt<1> - defname = TEC_RV_ICG + defname = gated_latch module rvclkhdr_7 : @@ -182,23 +182,23 @@ circuit el2_lsu_clkdomain : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of TEC_RV_ICG_7 @[beh_lib.scala 332:24] + inst clkhdr of gated_latch_7 @[el2_lib.scala 474:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12] - clkhdr.CK <= io.clk @[beh_lib.scala 334:16] - clkhdr.EN <= io.en @[beh_lib.scala 335:16] - clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16] + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] - extmodule TEC_RV_ICG_8 : + extmodule gated_latch_8 : output Q : Clock input CK : Clock input EN : UInt<1> input SE : UInt<1> - defname = TEC_RV_ICG + defname = gated_latch module rvclkhdr_8 : @@ -206,23 +206,23 @@ circuit el2_lsu_clkdomain : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of TEC_RV_ICG_8 @[beh_lib.scala 332:24] + inst clkhdr of gated_latch_8 @[el2_lib.scala 474:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12] - clkhdr.CK <= io.clk @[beh_lib.scala 334:16] - clkhdr.EN <= io.en @[beh_lib.scala 335:16] - clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16] + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] - extmodule TEC_RV_ICG_9 : + extmodule gated_latch_9 : output Q : Clock input CK : Clock input EN : UInt<1> input SE : UInt<1> - defname = TEC_RV_ICG + defname = gated_latch module rvclkhdr_9 : @@ -230,23 +230,23 @@ circuit el2_lsu_clkdomain : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of TEC_RV_ICG_9 @[beh_lib.scala 332:24] + inst clkhdr of gated_latch_9 @[el2_lib.scala 474:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12] - clkhdr.CK <= io.clk @[beh_lib.scala 334:16] - clkhdr.EN <= io.en @[beh_lib.scala 335:16] - clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16] + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] - extmodule TEC_RV_ICG_10 : + extmodule gated_latch_10 : output Q : Clock input CK : Clock input EN : UInt<1> input SE : UInt<1> - defname = TEC_RV_ICG + defname = gated_latch module rvclkhdr_10 : @@ -254,23 +254,23 @@ circuit el2_lsu_clkdomain : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of TEC_RV_ICG_10 @[beh_lib.scala 332:24] + inst clkhdr of gated_latch_10 @[el2_lib.scala 474:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12] - clkhdr.CK <= io.clk @[beh_lib.scala 334:16] - clkhdr.EN <= io.en @[beh_lib.scala 335:16] - clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16] + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] - extmodule TEC_RV_ICG_11 : + extmodule gated_latch_11 : output Q : Clock input CK : Clock input EN : UInt<1> input SE : UInt<1> - defname = TEC_RV_ICG + defname = gated_latch module rvclkhdr_11 : @@ -278,166 +278,165 @@ circuit el2_lsu_clkdomain : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of TEC_RV_ICG_11 @[beh_lib.scala 332:24] + inst clkhdr of gated_latch_11 @[el2_lib.scala 474:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12] - clkhdr.CK <= io.clk @[beh_lib.scala 334:16] - clkhdr.EN <= io.en @[beh_lib.scala 335:16] - clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16] + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] module el2_lsu_clkdomain : input clock : Clock input reset : AsyncReset - output io : {flip free_clk : Clock, flip clk_override : UInt<1>, flip addr_in_dccm_m : UInt<1>, flip dma_dccm_req : UInt<1>, flip ldst_stbuf_reqvld_r : UInt<1>, flip stbuf_reqvld_any : UInt<1>, flip stbuf_reqvld_flushed_any : UInt<1>, flip lsu_busreq_r : UInt<1>, flip lsu_bus_buffer_pend_any : UInt<1>, flip lsu_bus_buffer_empty_any : UInt<1>, flip lsu_stbuf_empty_any : UInt<1>, flip lsu_bus_clk_en : UInt<1>, flip lsu_p : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip lsu_pkt_d : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip lsu_pkt_m : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip lsu_pkt_r : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, lsu_c1_m_clk : Clock, lsu_c1_r_clk : Clock, lsu_c2_m_clk : Clock, lsu_c2_r_clk : Clock, lsu_store_c1_m_clk : Clock, lsu_store_c1_r_clk : Clock, lsu_stbuf_c1_clk : Clock, lsu_bus_obuf_c1_clk : Clock, lsu_bus_ibuf_c1_clk : Clock, lsu_bus_buf_c1_clk : Clock, lsu_busm_clk : Clock, lsu_free_c2_clk : Clock, flip scan_mode : UInt<1>} + output io : {flip free_clk : Clock, flip clk_override : UInt<1>, flip addr_in_dccm_m : UInt<1>, flip dma_dccm_req : UInt<1>, flip ldst_stbuf_reqvld_r : UInt<1>, flip stbuf_reqvld_any : UInt<1>, flip stbuf_reqvld_flushed_any : UInt<1>, flip lsu_busreq_r : UInt<1>, flip lsu_bus_buffer_pend_any : UInt<1>, flip lsu_bus_buffer_empty_any : UInt<1>, flip lsu_stbuf_empty_any : UInt<1>, flip lsu_bus_clk_en : UInt<1>, flip lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_c1_m_clk : Clock, lsu_c1_r_clk : Clock, lsu_c2_m_clk : Clock, lsu_c2_r_clk : Clock, lsu_store_c1_m_clk : Clock, lsu_store_c1_r_clk : Clock, lsu_stbuf_c1_clk : Clock, lsu_bus_obuf_c1_clk : Clock, lsu_bus_ibuf_c1_clk : Clock, lsu_bus_buf_c1_clk : Clock, lsu_busm_clk : Clock, lsu_free_c2_clk : Clock, flip scan_mode : UInt<1>} - wire lsu_c1_d_clken_q : UInt<1> @[el2_lsu_clkdomain.scala 58:37] - wire lsu_c1_m_clken_q : UInt<1> @[el2_lsu_clkdomain.scala 59:37] - wire lsu_c1_r_clken_q : UInt<1> @[el2_lsu_clkdomain.scala 60:37] - wire lsu_free_c1_clken_q : UInt<1> @[el2_lsu_clkdomain.scala 61:37] - node _T = or(io.lsu_p.valid, io.dma_dccm_req) @[el2_lsu_clkdomain.scala 63:52] - node lsu_c1_d_clken = or(_T, io.clk_override) @[el2_lsu_clkdomain.scala 63:71] - node _T_1 = or(io.lsu_pkt_d.valid, lsu_c1_d_clken_q) @[el2_lsu_clkdomain.scala 64:52] - node lsu_c1_m_clken = or(_T_1, io.clk_override) @[el2_lsu_clkdomain.scala 64:71] - node _T_2 = or(io.lsu_pkt_m.valid, lsu_c1_m_clken_q) @[el2_lsu_clkdomain.scala 65:52] - node lsu_c1_r_clken = or(_T_2, io.clk_override) @[el2_lsu_clkdomain.scala 65:71] - node _T_3 = or(lsu_c1_m_clken, lsu_c1_m_clken_q) @[el2_lsu_clkdomain.scala 67:48] - node lsu_c2_m_clken = or(_T_3, io.clk_override) @[el2_lsu_clkdomain.scala 67:67] - node _T_4 = or(lsu_c1_r_clken, lsu_c1_r_clken_q) @[el2_lsu_clkdomain.scala 68:48] - node lsu_c2_r_clken = or(_T_4, io.clk_override) @[el2_lsu_clkdomain.scala 68:67] - node _T_5 = and(lsu_c1_m_clken, io.lsu_pkt_d.store) @[el2_lsu_clkdomain.scala 70:50] - node lsu_store_c1_m_clken = or(_T_5, io.clk_override) @[el2_lsu_clkdomain.scala 70:72] - node _T_6 = and(lsu_c1_r_clken, io.lsu_pkt_m.store) @[el2_lsu_clkdomain.scala 71:50] - node lsu_store_c1_r_clken = or(_T_6, io.clk_override) @[el2_lsu_clkdomain.scala 71:72] - node _T_7 = or(io.ldst_stbuf_reqvld_r, io.stbuf_reqvld_any) @[el2_lsu_clkdomain.scala 72:56] - node _T_8 = or(_T_7, io.stbuf_reqvld_flushed_any) @[el2_lsu_clkdomain.scala 72:78] - node lsu_stbuf_c1_clken = or(_T_8, io.clk_override) @[el2_lsu_clkdomain.scala 72:108] - node lsu_bus_ibuf_c1_clken = or(io.lsu_busreq_r, io.clk_override) @[el2_lsu_clkdomain.scala 73:50] - node _T_9 = or(io.lsu_bus_buffer_pend_any, io.lsu_busreq_r) @[el2_lsu_clkdomain.scala 74:62] - node _T_10 = or(_T_9, io.clk_override) @[el2_lsu_clkdomain.scala 74:80] - node lsu_bus_obuf_c1_clken = and(_T_10, io.lsu_bus_clk_en) @[el2_lsu_clkdomain.scala 74:99] - node _T_11 = eq(io.lsu_bus_buffer_empty_any, UInt<1>("h00")) @[el2_lsu_clkdomain.scala 75:34] - node _T_12 = or(_T_11, io.lsu_busreq_r) @[el2_lsu_clkdomain.scala 75:63] - node _T_13 = or(_T_12, io.clk_override) @[el2_lsu_clkdomain.scala 75:81] - node lsu_bus_buf_c1_clken = bits(_T_13, 0, 0) @[el2_lsu_clkdomain.scala 75:100] - node _T_14 = or(io.lsu_p.valid, io.lsu_pkt_d.valid) @[el2_lsu_clkdomain.scala 77:49] - node _T_15 = or(_T_14, io.lsu_pkt_m.valid) @[el2_lsu_clkdomain.scala 77:70] - node _T_16 = or(_T_15, io.lsu_pkt_r.valid) @[el2_lsu_clkdomain.scala 77:91] - node _T_17 = eq(io.lsu_bus_buffer_empty_any, UInt<1>("h00")) @[el2_lsu_clkdomain.scala 77:115] - node _T_18 = or(_T_16, _T_17) @[el2_lsu_clkdomain.scala 77:113] - node _T_19 = eq(io.lsu_stbuf_empty_any, UInt<1>("h00")) @[el2_lsu_clkdomain.scala 77:146] - node _T_20 = or(_T_18, _T_19) @[el2_lsu_clkdomain.scala 77:144] - node lsu_free_c1_clken = or(_T_20, io.clk_override) @[el2_lsu_clkdomain.scala 77:170] - node _T_21 = or(lsu_free_c1_clken, lsu_free_c1_clken_q) @[el2_lsu_clkdomain.scala 78:51] - node lsu_free_c2_clken = or(_T_21, io.clk_override) @[el2_lsu_clkdomain.scala 78:73] - reg _T_22 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_clkdomain.scala 81:61] - _T_22 <= lsu_free_c1_clken @[el2_lsu_clkdomain.scala 81:61] - lsu_free_c1_clken_q <= _T_22 @[el2_lsu_clkdomain.scala 81:27] - reg _T_23 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_clkdomain.scala 82:68] - _T_23 <= lsu_c1_d_clken @[el2_lsu_clkdomain.scala 82:68] - lsu_c1_d_clken_q <= _T_23 @[el2_lsu_clkdomain.scala 82:27] - reg _T_24 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_clkdomain.scala 83:68] - _T_24 <= lsu_c1_m_clken @[el2_lsu_clkdomain.scala 83:68] - lsu_c1_m_clken_q <= _T_24 @[el2_lsu_clkdomain.scala 83:27] - reg _T_25 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_clkdomain.scala 84:68] - _T_25 <= lsu_c1_r_clken @[el2_lsu_clkdomain.scala 84:68] - lsu_c1_r_clken_q <= _T_25 @[el2_lsu_clkdomain.scala 84:27] - node _T_26 = bits(lsu_c1_m_clken, 0, 0) @[el2_lsu_clkdomain.scala 86:60] - inst rvclkhdr of rvclkhdr @[beh_lib.scala 341:20] + wire lsu_c1_d_clken_q : UInt<1> @[el2_lsu_clkdomain.scala 58:36] + wire lsu_c1_m_clken_q : UInt<1> @[el2_lsu_clkdomain.scala 59:36] + wire lsu_c1_r_clken_q : UInt<1> @[el2_lsu_clkdomain.scala 60:36] + wire lsu_free_c1_clken_q : UInt<1> @[el2_lsu_clkdomain.scala 61:36] + node _T = or(io.lsu_p.valid, io.dma_dccm_req) @[el2_lsu_clkdomain.scala 63:51] + node lsu_c1_d_clken = or(_T, io.clk_override) @[el2_lsu_clkdomain.scala 63:70] + node _T_1 = or(io.lsu_pkt_d.valid, lsu_c1_d_clken_q) @[el2_lsu_clkdomain.scala 64:51] + node lsu_c1_m_clken = or(_T_1, io.clk_override) @[el2_lsu_clkdomain.scala 64:70] + node _T_2 = or(io.lsu_pkt_m.valid, lsu_c1_m_clken_q) @[el2_lsu_clkdomain.scala 65:51] + node lsu_c1_r_clken = or(_T_2, io.clk_override) @[el2_lsu_clkdomain.scala 65:70] + node _T_3 = or(lsu_c1_m_clken, lsu_c1_m_clken_q) @[el2_lsu_clkdomain.scala 67:47] + node lsu_c2_m_clken = or(_T_3, io.clk_override) @[el2_lsu_clkdomain.scala 67:66] + node _T_4 = or(lsu_c1_r_clken, lsu_c1_r_clken_q) @[el2_lsu_clkdomain.scala 68:47] + node lsu_c2_r_clken = or(_T_4, io.clk_override) @[el2_lsu_clkdomain.scala 68:66] + node _T_5 = and(lsu_c1_m_clken, io.lsu_pkt_d.bits.store) @[el2_lsu_clkdomain.scala 70:49] + node lsu_store_c1_m_clken = or(_T_5, io.clk_override) @[el2_lsu_clkdomain.scala 70:76] + node _T_6 = and(lsu_c1_r_clken, io.lsu_pkt_m.bits.store) @[el2_lsu_clkdomain.scala 71:49] + node lsu_store_c1_r_clken = or(_T_6, io.clk_override) @[el2_lsu_clkdomain.scala 71:76] + node _T_7 = or(io.ldst_stbuf_reqvld_r, io.stbuf_reqvld_any) @[el2_lsu_clkdomain.scala 72:55] + node _T_8 = or(_T_7, io.stbuf_reqvld_flushed_any) @[el2_lsu_clkdomain.scala 72:77] + node lsu_stbuf_c1_clken = or(_T_8, io.clk_override) @[el2_lsu_clkdomain.scala 72:107] + node lsu_bus_ibuf_c1_clken = or(io.lsu_busreq_r, io.clk_override) @[el2_lsu_clkdomain.scala 73:49] + node _T_9 = or(io.lsu_bus_buffer_pend_any, io.lsu_busreq_r) @[el2_lsu_clkdomain.scala 74:61] + node _T_10 = or(_T_9, io.clk_override) @[el2_lsu_clkdomain.scala 74:79] + node lsu_bus_obuf_c1_clken = and(_T_10, io.lsu_bus_clk_en) @[el2_lsu_clkdomain.scala 74:98] + node _T_11 = eq(io.lsu_bus_buffer_empty_any, UInt<1>("h00")) @[el2_lsu_clkdomain.scala 75:32] + node _T_12 = or(_T_11, io.lsu_busreq_r) @[el2_lsu_clkdomain.scala 75:61] + node lsu_bus_buf_c1_clken = or(_T_12, io.clk_override) @[el2_lsu_clkdomain.scala 75:79] + node _T_13 = or(io.lsu_p.valid, io.lsu_pkt_d.valid) @[el2_lsu_clkdomain.scala 77:48] + node _T_14 = or(_T_13, io.lsu_pkt_m.valid) @[el2_lsu_clkdomain.scala 77:69] + node _T_15 = or(_T_14, io.lsu_pkt_r.valid) @[el2_lsu_clkdomain.scala 77:90] + node _T_16 = eq(io.lsu_bus_buffer_empty_any, UInt<1>("h00")) @[el2_lsu_clkdomain.scala 77:114] + node _T_17 = or(_T_15, _T_16) @[el2_lsu_clkdomain.scala 77:112] + node _T_18 = eq(io.lsu_stbuf_empty_any, UInt<1>("h00")) @[el2_lsu_clkdomain.scala 77:145] + node _T_19 = or(_T_17, _T_18) @[el2_lsu_clkdomain.scala 77:143] + node lsu_free_c1_clken = or(_T_19, io.clk_override) @[el2_lsu_clkdomain.scala 77:169] + node _T_20 = or(lsu_free_c1_clken, lsu_free_c1_clken_q) @[el2_lsu_clkdomain.scala 78:50] + node lsu_free_c2_clken = or(_T_20, io.clk_override) @[el2_lsu_clkdomain.scala 78:72] + reg _T_21 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_clkdomain.scala 81:60] + _T_21 <= lsu_free_c1_clken @[el2_lsu_clkdomain.scala 81:60] + lsu_free_c1_clken_q <= _T_21 @[el2_lsu_clkdomain.scala 81:26] + reg _T_22 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_clkdomain.scala 82:67] + _T_22 <= lsu_c1_d_clken @[el2_lsu_clkdomain.scala 82:67] + lsu_c1_d_clken_q <= _T_22 @[el2_lsu_clkdomain.scala 82:26] + reg _T_23 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_clkdomain.scala 83:67] + _T_23 <= lsu_c1_m_clken @[el2_lsu_clkdomain.scala 83:67] + lsu_c1_m_clken_q <= _T_23 @[el2_lsu_clkdomain.scala 83:26] + reg _T_24 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_clkdomain.scala 84:67] + _T_24 <= lsu_c1_r_clken @[el2_lsu_clkdomain.scala 84:67] + lsu_c1_r_clken_q <= _T_24 @[el2_lsu_clkdomain.scala 84:26] + node _T_25 = bits(lsu_c1_m_clken, 0, 0) @[el2_lsu_clkdomain.scala 86:59] + inst rvclkhdr of rvclkhdr @[el2_lib.scala 483:22] rvclkhdr.clock <= clock rvclkhdr.reset <= reset - rvclkhdr.io.clk <= clock @[beh_lib.scala 342:15] - rvclkhdr.io.en <= _T_26 @[beh_lib.scala 343:14] - rvclkhdr.io.scan_mode <= io.scan_mode @[beh_lib.scala 344:21] - io.lsu_c1_m_clk <= rvclkhdr.io.l1clk @[el2_lsu_clkdomain.scala 86:27] - node _T_27 = bits(lsu_c1_r_clken, 0, 0) @[el2_lsu_clkdomain.scala 87:60] - inst rvclkhdr_1 of rvclkhdr_1 @[beh_lib.scala 341:20] + rvclkhdr.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr.io.en <= _T_25 @[el2_lib.scala 485:16] + rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + io.lsu_c1_m_clk <= rvclkhdr.io.l1clk @[el2_lsu_clkdomain.scala 86:26] + node _T_26 = bits(lsu_c1_r_clken, 0, 0) @[el2_lsu_clkdomain.scala 87:59] + inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 483:22] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset - rvclkhdr_1.io.clk <= clock @[beh_lib.scala 342:15] - rvclkhdr_1.io.en <= _T_27 @[beh_lib.scala 343:14] - rvclkhdr_1.io.scan_mode <= io.scan_mode @[beh_lib.scala 344:21] - io.lsu_c1_r_clk <= rvclkhdr_1.io.l1clk @[el2_lsu_clkdomain.scala 87:27] - node _T_28 = bits(lsu_c2_m_clken, 0, 0) @[el2_lsu_clkdomain.scala 88:60] - inst rvclkhdr_2 of rvclkhdr_2 @[beh_lib.scala 341:20] + rvclkhdr_1.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_1.io.en <= _T_26 @[el2_lib.scala 485:16] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + io.lsu_c1_r_clk <= rvclkhdr_1.io.l1clk @[el2_lsu_clkdomain.scala 87:26] + node _T_27 = bits(lsu_c2_m_clken, 0, 0) @[el2_lsu_clkdomain.scala 88:59] + inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 483:22] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset - rvclkhdr_2.io.clk <= clock @[beh_lib.scala 342:15] - rvclkhdr_2.io.en <= _T_28 @[beh_lib.scala 343:14] - rvclkhdr_2.io.scan_mode <= io.scan_mode @[beh_lib.scala 344:21] - io.lsu_c2_m_clk <= rvclkhdr_2.io.l1clk @[el2_lsu_clkdomain.scala 88:27] - node _T_29 = bits(lsu_c2_r_clken, 0, 0) @[el2_lsu_clkdomain.scala 89:60] - inst rvclkhdr_3 of rvclkhdr_3 @[beh_lib.scala 341:20] + rvclkhdr_2.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_2.io.en <= _T_27 @[el2_lib.scala 485:16] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + io.lsu_c2_m_clk <= rvclkhdr_2.io.l1clk @[el2_lsu_clkdomain.scala 88:26] + node _T_28 = bits(lsu_c2_r_clken, 0, 0) @[el2_lsu_clkdomain.scala 89:59] + inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 483:22] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset - rvclkhdr_3.io.clk <= clock @[beh_lib.scala 342:15] - rvclkhdr_3.io.en <= _T_29 @[beh_lib.scala 343:14] - rvclkhdr_3.io.scan_mode <= io.scan_mode @[beh_lib.scala 344:21] - io.lsu_c2_r_clk <= rvclkhdr_3.io.l1clk @[el2_lsu_clkdomain.scala 89:27] - node _T_30 = bits(lsu_store_c1_m_clken, 0, 0) @[el2_lsu_clkdomain.scala 90:66] - inst rvclkhdr_4 of rvclkhdr_4 @[beh_lib.scala 341:20] + rvclkhdr_3.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_3.io.en <= _T_28 @[el2_lib.scala 485:16] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + io.lsu_c2_r_clk <= rvclkhdr_3.io.l1clk @[el2_lsu_clkdomain.scala 89:26] + node _T_29 = bits(lsu_store_c1_m_clken, 0, 0) @[el2_lsu_clkdomain.scala 90:65] + inst rvclkhdr_4 of rvclkhdr_4 @[el2_lib.scala 483:22] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset - rvclkhdr_4.io.clk <= clock @[beh_lib.scala 342:15] - rvclkhdr_4.io.en <= _T_30 @[beh_lib.scala 343:14] - rvclkhdr_4.io.scan_mode <= io.scan_mode @[beh_lib.scala 344:21] - io.lsu_store_c1_m_clk <= rvclkhdr_4.io.l1clk @[el2_lsu_clkdomain.scala 90:27] - node _T_31 = bits(lsu_store_c1_r_clken, 0, 0) @[el2_lsu_clkdomain.scala 91:66] - inst rvclkhdr_5 of rvclkhdr_5 @[beh_lib.scala 341:20] + rvclkhdr_4.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_4.io.en <= _T_29 @[el2_lib.scala 485:16] + rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + io.lsu_store_c1_m_clk <= rvclkhdr_4.io.l1clk @[el2_lsu_clkdomain.scala 90:26] + node _T_30 = bits(lsu_store_c1_r_clken, 0, 0) @[el2_lsu_clkdomain.scala 91:65] + inst rvclkhdr_5 of rvclkhdr_5 @[el2_lib.scala 483:22] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset - rvclkhdr_5.io.clk <= clock @[beh_lib.scala 342:15] - rvclkhdr_5.io.en <= _T_31 @[beh_lib.scala 343:14] - rvclkhdr_5.io.scan_mode <= io.scan_mode @[beh_lib.scala 344:21] - io.lsu_store_c1_r_clk <= rvclkhdr_5.io.l1clk @[el2_lsu_clkdomain.scala 91:27] - node _T_32 = bits(lsu_stbuf_c1_clken, 0, 0) @[el2_lsu_clkdomain.scala 92:64] - inst rvclkhdr_6 of rvclkhdr_6 @[beh_lib.scala 341:20] + rvclkhdr_5.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_5.io.en <= _T_30 @[el2_lib.scala 485:16] + rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + io.lsu_store_c1_r_clk <= rvclkhdr_5.io.l1clk @[el2_lsu_clkdomain.scala 91:26] + node _T_31 = bits(lsu_stbuf_c1_clken, 0, 0) @[el2_lsu_clkdomain.scala 92:63] + inst rvclkhdr_6 of rvclkhdr_6 @[el2_lib.scala 483:22] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset - rvclkhdr_6.io.clk <= clock @[beh_lib.scala 342:15] - rvclkhdr_6.io.en <= _T_32 @[beh_lib.scala 343:14] - rvclkhdr_6.io.scan_mode <= io.scan_mode @[beh_lib.scala 344:21] - io.lsu_stbuf_c1_clk <= rvclkhdr_6.io.l1clk @[el2_lsu_clkdomain.scala 92:27] - node _T_33 = bits(lsu_bus_ibuf_c1_clken, 0, 0) @[el2_lsu_clkdomain.scala 93:67] - inst rvclkhdr_7 of rvclkhdr_7 @[beh_lib.scala 341:20] + rvclkhdr_6.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_6.io.en <= _T_31 @[el2_lib.scala 485:16] + rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + io.lsu_stbuf_c1_clk <= rvclkhdr_6.io.l1clk @[el2_lsu_clkdomain.scala 92:26] + node _T_32 = bits(lsu_bus_ibuf_c1_clken, 0, 0) @[el2_lsu_clkdomain.scala 93:66] + inst rvclkhdr_7 of rvclkhdr_7 @[el2_lib.scala 483:22] rvclkhdr_7.clock <= clock rvclkhdr_7.reset <= reset - rvclkhdr_7.io.clk <= clock @[beh_lib.scala 342:15] - rvclkhdr_7.io.en <= _T_33 @[beh_lib.scala 343:14] - rvclkhdr_7.io.scan_mode <= io.scan_mode @[beh_lib.scala 344:21] - io.lsu_bus_ibuf_c1_clk <= rvclkhdr_7.io.l1clk @[el2_lsu_clkdomain.scala 93:27] - node _T_34 = bits(lsu_bus_obuf_c1_clken, 0, 0) @[el2_lsu_clkdomain.scala 94:67] - inst rvclkhdr_8 of rvclkhdr_8 @[beh_lib.scala 341:20] + rvclkhdr_7.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_7.io.en <= _T_32 @[el2_lib.scala 485:16] + rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + io.lsu_bus_ibuf_c1_clk <= rvclkhdr_7.io.l1clk @[el2_lsu_clkdomain.scala 93:26] + node _T_33 = bits(lsu_bus_obuf_c1_clken, 0, 0) @[el2_lsu_clkdomain.scala 94:66] + inst rvclkhdr_8 of rvclkhdr_8 @[el2_lib.scala 483:22] rvclkhdr_8.clock <= clock rvclkhdr_8.reset <= reset - rvclkhdr_8.io.clk <= clock @[beh_lib.scala 342:15] - rvclkhdr_8.io.en <= _T_34 @[beh_lib.scala 343:14] - rvclkhdr_8.io.scan_mode <= io.scan_mode @[beh_lib.scala 344:21] - io.lsu_bus_obuf_c1_clk <= rvclkhdr_8.io.l1clk @[el2_lsu_clkdomain.scala 94:27] - node _T_35 = bits(lsu_bus_buf_c1_clken, 0, 0) @[el2_lsu_clkdomain.scala 95:66] - inst rvclkhdr_9 of rvclkhdr_9 @[beh_lib.scala 341:20] + rvclkhdr_8.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_8.io.en <= _T_33 @[el2_lib.scala 485:16] + rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + io.lsu_bus_obuf_c1_clk <= rvclkhdr_8.io.l1clk @[el2_lsu_clkdomain.scala 94:26] + node _T_34 = bits(lsu_bus_buf_c1_clken, 0, 0) @[el2_lsu_clkdomain.scala 95:65] + inst rvclkhdr_9 of rvclkhdr_9 @[el2_lib.scala 483:22] rvclkhdr_9.clock <= clock rvclkhdr_9.reset <= reset - rvclkhdr_9.io.clk <= clock @[beh_lib.scala 342:15] - rvclkhdr_9.io.en <= _T_35 @[beh_lib.scala 343:14] - rvclkhdr_9.io.scan_mode <= io.scan_mode @[beh_lib.scala 344:21] - io.lsu_bus_buf_c1_clk <= rvclkhdr_9.io.l1clk @[el2_lsu_clkdomain.scala 95:27] - node _T_36 = bits(io.lsu_bus_clk_en, 0, 0) @[el2_lsu_clkdomain.scala 96:63] - inst rvclkhdr_10 of rvclkhdr_10 @[beh_lib.scala 341:20] + rvclkhdr_9.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_9.io.en <= _T_34 @[el2_lib.scala 485:16] + rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + io.lsu_bus_buf_c1_clk <= rvclkhdr_9.io.l1clk @[el2_lsu_clkdomain.scala 95:26] + node _T_35 = bits(io.lsu_bus_clk_en, 0, 0) @[el2_lsu_clkdomain.scala 96:62] + inst rvclkhdr_10 of rvclkhdr_10 @[el2_lib.scala 483:22] rvclkhdr_10.clock <= clock rvclkhdr_10.reset <= reset - rvclkhdr_10.io.clk <= clock @[beh_lib.scala 342:15] - rvclkhdr_10.io.en <= _T_36 @[beh_lib.scala 343:14] - rvclkhdr_10.io.scan_mode <= io.scan_mode @[beh_lib.scala 344:21] - io.lsu_busm_clk <= rvclkhdr_10.io.l1clk @[el2_lsu_clkdomain.scala 96:27] - node _T_37 = bits(lsu_free_c2_clken, 0, 0) @[el2_lsu_clkdomain.scala 97:63] - inst rvclkhdr_11 of rvclkhdr_11 @[beh_lib.scala 341:20] + rvclkhdr_10.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_10.io.en <= _T_35 @[el2_lib.scala 485:16] + rvclkhdr_10.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + io.lsu_busm_clk <= rvclkhdr_10.io.l1clk @[el2_lsu_clkdomain.scala 96:26] + node _T_36 = bits(lsu_free_c2_clken, 0, 0) @[el2_lsu_clkdomain.scala 97:62] + inst rvclkhdr_11 of rvclkhdr_11 @[el2_lib.scala 483:22] rvclkhdr_11.clock <= clock rvclkhdr_11.reset <= reset - rvclkhdr_11.io.clk <= clock @[beh_lib.scala 342:15] - rvclkhdr_11.io.en <= _T_37 @[beh_lib.scala 343:14] - rvclkhdr_11.io.scan_mode <= io.scan_mode @[beh_lib.scala 344:21] - io.lsu_free_c2_clk <= rvclkhdr_11.io.l1clk @[el2_lsu_clkdomain.scala 97:27] + rvclkhdr_11.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_11.io.en <= _T_36 @[el2_lib.scala 485:16] + rvclkhdr_11.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + io.lsu_free_c2_clk <= rvclkhdr_11.io.l1clk @[el2_lsu_clkdomain.scala 97:26] diff --git a/el2_lsu_clkdomain.v b/el2_lsu_clkdomain.v index 4d1f9b1d..af62fe7c 100644 --- a/el2_lsu_clkdomain.v +++ b/el2_lsu_clkdomain.v @@ -4,20 +4,20 @@ module rvclkhdr( input io_en, input io_scan_mode ); - wire clkhdr_Q; // @[beh_lib.scala 332:24] - wire clkhdr_CK; // @[beh_lib.scala 332:24] - wire clkhdr_EN; // @[beh_lib.scala 332:24] - wire clkhdr_SE; // @[beh_lib.scala 332:24] - TEC_RV_ICG clkhdr ( // @[beh_lib.scala 332:24] + wire clkhdr_Q; // @[el2_lib.scala 474:26] + wire clkhdr_CK; // @[el2_lib.scala 474:26] + wire clkhdr_EN; // @[el2_lib.scala 474:26] + wire clkhdr_SE; // @[el2_lib.scala 474:26] + gated_latch clkhdr ( // @[el2_lib.scala 474:26] .Q(clkhdr_Q), .CK(clkhdr_CK), .EN(clkhdr_EN), .SE(clkhdr_SE) ); - assign io_l1clk = clkhdr_Q; // @[beh_lib.scala 333:12] - assign clkhdr_CK = io_clk; // @[beh_lib.scala 334:16] - assign clkhdr_EN = io_en; // @[beh_lib.scala 335:16] - assign clkhdr_SE = io_scan_mode; // @[beh_lib.scala 336:16] + assign io_l1clk = clkhdr_Q; // @[el2_lib.scala 475:14] + assign clkhdr_CK = io_clk; // @[el2_lib.scala 476:18] + assign clkhdr_EN = io_en; // @[el2_lib.scala 477:18] + assign clkhdr_SE = io_scan_mode; // @[el2_lib.scala 478:18] endmodule module el2_lsu_clkdomain( input clock, @@ -34,58 +34,58 @@ module el2_lsu_clkdomain( input io_lsu_bus_buffer_empty_any, input io_lsu_stbuf_empty_any, input io_lsu_bus_clk_en, - input io_lsu_p_fast_int, - input io_lsu_p_by, - input io_lsu_p_half, - input io_lsu_p_word, - input io_lsu_p_dword, - input io_lsu_p_load, - input io_lsu_p_store, - input io_lsu_p_unsign, - input io_lsu_p_dma, - input io_lsu_p_store_data_bypass_d, - input io_lsu_p_load_ldst_bypass_d, - input io_lsu_p_store_data_bypass_m, input io_lsu_p_valid, - input io_lsu_pkt_d_fast_int, - input io_lsu_pkt_d_by, - input io_lsu_pkt_d_half, - input io_lsu_pkt_d_word, - input io_lsu_pkt_d_dword, - input io_lsu_pkt_d_load, - input io_lsu_pkt_d_store, - input io_lsu_pkt_d_unsign, - input io_lsu_pkt_d_dma, - input io_lsu_pkt_d_store_data_bypass_d, - input io_lsu_pkt_d_load_ldst_bypass_d, - input io_lsu_pkt_d_store_data_bypass_m, + input io_lsu_p_bits_fast_int, + input io_lsu_p_bits_by, + input io_lsu_p_bits_half, + input io_lsu_p_bits_word, + input io_lsu_p_bits_dword, + input io_lsu_p_bits_load, + input io_lsu_p_bits_store, + input io_lsu_p_bits_unsign, + input io_lsu_p_bits_dma, + input io_lsu_p_bits_store_data_bypass_d, + input io_lsu_p_bits_load_ldst_bypass_d, + input io_lsu_p_bits_store_data_bypass_m, input io_lsu_pkt_d_valid, - input io_lsu_pkt_m_fast_int, - input io_lsu_pkt_m_by, - input io_lsu_pkt_m_half, - input io_lsu_pkt_m_word, - input io_lsu_pkt_m_dword, - input io_lsu_pkt_m_load, - input io_lsu_pkt_m_store, - input io_lsu_pkt_m_unsign, - input io_lsu_pkt_m_dma, - input io_lsu_pkt_m_store_data_bypass_d, - input io_lsu_pkt_m_load_ldst_bypass_d, - input io_lsu_pkt_m_store_data_bypass_m, + input io_lsu_pkt_d_bits_fast_int, + input io_lsu_pkt_d_bits_by, + input io_lsu_pkt_d_bits_half, + input io_lsu_pkt_d_bits_word, + input io_lsu_pkt_d_bits_dword, + input io_lsu_pkt_d_bits_load, + input io_lsu_pkt_d_bits_store, + input io_lsu_pkt_d_bits_unsign, + input io_lsu_pkt_d_bits_dma, + input io_lsu_pkt_d_bits_store_data_bypass_d, + input io_lsu_pkt_d_bits_load_ldst_bypass_d, + input io_lsu_pkt_d_bits_store_data_bypass_m, input io_lsu_pkt_m_valid, - input io_lsu_pkt_r_fast_int, - input io_lsu_pkt_r_by, - input io_lsu_pkt_r_half, - input io_lsu_pkt_r_word, - input io_lsu_pkt_r_dword, - input io_lsu_pkt_r_load, - input io_lsu_pkt_r_store, - input io_lsu_pkt_r_unsign, - input io_lsu_pkt_r_dma, - input io_lsu_pkt_r_store_data_bypass_d, - input io_lsu_pkt_r_load_ldst_bypass_d, - input io_lsu_pkt_r_store_data_bypass_m, + input io_lsu_pkt_m_bits_fast_int, + input io_lsu_pkt_m_bits_by, + input io_lsu_pkt_m_bits_half, + input io_lsu_pkt_m_bits_word, + input io_lsu_pkt_m_bits_dword, + input io_lsu_pkt_m_bits_load, + input io_lsu_pkt_m_bits_store, + input io_lsu_pkt_m_bits_unsign, + input io_lsu_pkt_m_bits_dma, + input io_lsu_pkt_m_bits_store_data_bypass_d, + input io_lsu_pkt_m_bits_load_ldst_bypass_d, + input io_lsu_pkt_m_bits_store_data_bypass_m, input io_lsu_pkt_r_valid, + input io_lsu_pkt_r_bits_fast_int, + input io_lsu_pkt_r_bits_by, + input io_lsu_pkt_r_bits_half, + input io_lsu_pkt_r_bits_word, + input io_lsu_pkt_r_bits_dword, + input io_lsu_pkt_r_bits_load, + input io_lsu_pkt_r_bits_store, + input io_lsu_pkt_r_bits_unsign, + input io_lsu_pkt_r_bits_dma, + input io_lsu_pkt_r_bits_store_data_bypass_d, + input io_lsu_pkt_r_bits_load_ldst_bypass_d, + input io_lsu_pkt_r_bits_store_data_bypass_m, output io_lsu_c1_m_clk, output io_lsu_c1_r_clk, output io_lsu_c2_m_clk, @@ -106,201 +106,201 @@ module el2_lsu_clkdomain( reg [31:0] _RAND_2; reg [31:0] _RAND_3; `endif // RANDOMIZE_REG_INIT - wire rvclkhdr_io_l1clk; // @[beh_lib.scala 341:20] - wire rvclkhdr_io_clk; // @[beh_lib.scala 341:20] - wire rvclkhdr_io_en; // @[beh_lib.scala 341:20] - wire rvclkhdr_io_scan_mode; // @[beh_lib.scala 341:20] - wire rvclkhdr_1_io_l1clk; // @[beh_lib.scala 341:20] - wire rvclkhdr_1_io_clk; // @[beh_lib.scala 341:20] - wire rvclkhdr_1_io_en; // @[beh_lib.scala 341:20] - wire rvclkhdr_1_io_scan_mode; // @[beh_lib.scala 341:20] - wire rvclkhdr_2_io_l1clk; // @[beh_lib.scala 341:20] - wire rvclkhdr_2_io_clk; // @[beh_lib.scala 341:20] - wire rvclkhdr_2_io_en; // @[beh_lib.scala 341:20] - wire rvclkhdr_2_io_scan_mode; // @[beh_lib.scala 341:20] - wire rvclkhdr_3_io_l1clk; // @[beh_lib.scala 341:20] - wire rvclkhdr_3_io_clk; // @[beh_lib.scala 341:20] - wire rvclkhdr_3_io_en; // @[beh_lib.scala 341:20] - wire rvclkhdr_3_io_scan_mode; // @[beh_lib.scala 341:20] - wire rvclkhdr_4_io_l1clk; // @[beh_lib.scala 341:20] - wire rvclkhdr_4_io_clk; // @[beh_lib.scala 341:20] - wire rvclkhdr_4_io_en; // @[beh_lib.scala 341:20] - wire rvclkhdr_4_io_scan_mode; // @[beh_lib.scala 341:20] - wire rvclkhdr_5_io_l1clk; // @[beh_lib.scala 341:20] - wire rvclkhdr_5_io_clk; // @[beh_lib.scala 341:20] - wire rvclkhdr_5_io_en; // @[beh_lib.scala 341:20] - wire rvclkhdr_5_io_scan_mode; // @[beh_lib.scala 341:20] - wire rvclkhdr_6_io_l1clk; // @[beh_lib.scala 341:20] - wire rvclkhdr_6_io_clk; // @[beh_lib.scala 341:20] - wire rvclkhdr_6_io_en; // @[beh_lib.scala 341:20] - wire rvclkhdr_6_io_scan_mode; // @[beh_lib.scala 341:20] - wire rvclkhdr_7_io_l1clk; // @[beh_lib.scala 341:20] - wire rvclkhdr_7_io_clk; // @[beh_lib.scala 341:20] - wire rvclkhdr_7_io_en; // @[beh_lib.scala 341:20] - wire rvclkhdr_7_io_scan_mode; // @[beh_lib.scala 341:20] - wire rvclkhdr_8_io_l1clk; // @[beh_lib.scala 341:20] - wire rvclkhdr_8_io_clk; // @[beh_lib.scala 341:20] - wire rvclkhdr_8_io_en; // @[beh_lib.scala 341:20] - wire rvclkhdr_8_io_scan_mode; // @[beh_lib.scala 341:20] - wire rvclkhdr_9_io_l1clk; // @[beh_lib.scala 341:20] - wire rvclkhdr_9_io_clk; // @[beh_lib.scala 341:20] - wire rvclkhdr_9_io_en; // @[beh_lib.scala 341:20] - wire rvclkhdr_9_io_scan_mode; // @[beh_lib.scala 341:20] - wire rvclkhdr_10_io_l1clk; // @[beh_lib.scala 341:20] - wire rvclkhdr_10_io_clk; // @[beh_lib.scala 341:20] - wire rvclkhdr_10_io_en; // @[beh_lib.scala 341:20] - wire rvclkhdr_10_io_scan_mode; // @[beh_lib.scala 341:20] - wire rvclkhdr_11_io_l1clk; // @[beh_lib.scala 341:20] - wire rvclkhdr_11_io_clk; // @[beh_lib.scala 341:20] - wire rvclkhdr_11_io_en; // @[beh_lib.scala 341:20] - wire rvclkhdr_11_io_scan_mode; // @[beh_lib.scala 341:20] - wire _T = io_lsu_p_valid | io_dma_dccm_req; // @[el2_lsu_clkdomain.scala 63:52] - reg lsu_c1_d_clken_q; // @[el2_lsu_clkdomain.scala 82:68] - wire _T_1 = io_lsu_pkt_d_valid | lsu_c1_d_clken_q; // @[el2_lsu_clkdomain.scala 64:52] - wire lsu_c1_m_clken = _T_1 | io_clk_override; // @[el2_lsu_clkdomain.scala 64:71] - reg lsu_c1_m_clken_q; // @[el2_lsu_clkdomain.scala 83:68] - wire _T_2 = io_lsu_pkt_m_valid | lsu_c1_m_clken_q; // @[el2_lsu_clkdomain.scala 65:52] - wire lsu_c1_r_clken = _T_2 | io_clk_override; // @[el2_lsu_clkdomain.scala 65:71] - wire _T_3 = lsu_c1_m_clken | lsu_c1_m_clken_q; // @[el2_lsu_clkdomain.scala 67:48] - reg lsu_c1_r_clken_q; // @[el2_lsu_clkdomain.scala 84:68] - wire _T_4 = lsu_c1_r_clken | lsu_c1_r_clken_q; // @[el2_lsu_clkdomain.scala 68:48] - wire _T_5 = lsu_c1_m_clken & io_lsu_pkt_d_store; // @[el2_lsu_clkdomain.scala 70:50] - wire _T_6 = lsu_c1_r_clken & io_lsu_pkt_m_store; // @[el2_lsu_clkdomain.scala 71:50] - wire _T_7 = io_ldst_stbuf_reqvld_r | io_stbuf_reqvld_any; // @[el2_lsu_clkdomain.scala 72:56] - wire _T_8 = _T_7 | io_stbuf_reqvld_flushed_any; // @[el2_lsu_clkdomain.scala 72:78] - wire _T_9 = io_lsu_bus_buffer_pend_any | io_lsu_busreq_r; // @[el2_lsu_clkdomain.scala 74:62] - wire _T_10 = _T_9 | io_clk_override; // @[el2_lsu_clkdomain.scala 74:80] - wire _T_11 = ~io_lsu_bus_buffer_empty_any; // @[el2_lsu_clkdomain.scala 75:34] - wire _T_12 = _T_11 | io_lsu_busreq_r; // @[el2_lsu_clkdomain.scala 75:63] - wire _T_14 = io_lsu_p_valid | io_lsu_pkt_d_valid; // @[el2_lsu_clkdomain.scala 77:49] - wire _T_15 = _T_14 | io_lsu_pkt_m_valid; // @[el2_lsu_clkdomain.scala 77:70] - wire _T_16 = _T_15 | io_lsu_pkt_r_valid; // @[el2_lsu_clkdomain.scala 77:91] - wire _T_18 = _T_16 | _T_11; // @[el2_lsu_clkdomain.scala 77:113] - wire _T_19 = ~io_lsu_stbuf_empty_any; // @[el2_lsu_clkdomain.scala 77:146] - wire _T_20 = _T_18 | _T_19; // @[el2_lsu_clkdomain.scala 77:144] - wire lsu_free_c1_clken = _T_20 | io_clk_override; // @[el2_lsu_clkdomain.scala 77:170] - reg lsu_free_c1_clken_q; // @[el2_lsu_clkdomain.scala 81:61] - wire _T_21 = lsu_free_c1_clken | lsu_free_c1_clken_q; // @[el2_lsu_clkdomain.scala 78:51] - rvclkhdr rvclkhdr ( // @[beh_lib.scala 341:20] + wire rvclkhdr_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_1_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_1_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_2_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_2_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_3_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_3_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_4_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_4_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_5_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_5_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_6_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_6_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_6_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_6_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_7_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_7_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_7_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_7_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_8_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_8_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_8_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_8_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_9_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_9_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_9_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_10_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_10_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_10_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_10_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_11_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_11_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_11_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_11_io_scan_mode; // @[el2_lib.scala 483:22] + wire _T = io_lsu_p_valid | io_dma_dccm_req; // @[el2_lsu_clkdomain.scala 63:51] + reg lsu_c1_d_clken_q; // @[el2_lsu_clkdomain.scala 82:67] + wire _T_1 = io_lsu_pkt_d_valid | lsu_c1_d_clken_q; // @[el2_lsu_clkdomain.scala 64:51] + wire lsu_c1_m_clken = _T_1 | io_clk_override; // @[el2_lsu_clkdomain.scala 64:70] + reg lsu_c1_m_clken_q; // @[el2_lsu_clkdomain.scala 83:67] + wire _T_2 = io_lsu_pkt_m_valid | lsu_c1_m_clken_q; // @[el2_lsu_clkdomain.scala 65:51] + wire lsu_c1_r_clken = _T_2 | io_clk_override; // @[el2_lsu_clkdomain.scala 65:70] + wire _T_3 = lsu_c1_m_clken | lsu_c1_m_clken_q; // @[el2_lsu_clkdomain.scala 67:47] + reg lsu_c1_r_clken_q; // @[el2_lsu_clkdomain.scala 84:67] + wire _T_4 = lsu_c1_r_clken | lsu_c1_r_clken_q; // @[el2_lsu_clkdomain.scala 68:47] + wire _T_5 = lsu_c1_m_clken & io_lsu_pkt_d_bits_store; // @[el2_lsu_clkdomain.scala 70:49] + wire _T_6 = lsu_c1_r_clken & io_lsu_pkt_m_bits_store; // @[el2_lsu_clkdomain.scala 71:49] + wire _T_7 = io_ldst_stbuf_reqvld_r | io_stbuf_reqvld_any; // @[el2_lsu_clkdomain.scala 72:55] + wire _T_8 = _T_7 | io_stbuf_reqvld_flushed_any; // @[el2_lsu_clkdomain.scala 72:77] + wire _T_9 = io_lsu_bus_buffer_pend_any | io_lsu_busreq_r; // @[el2_lsu_clkdomain.scala 74:61] + wire _T_10 = _T_9 | io_clk_override; // @[el2_lsu_clkdomain.scala 74:79] + wire _T_11 = ~io_lsu_bus_buffer_empty_any; // @[el2_lsu_clkdomain.scala 75:32] + wire _T_12 = _T_11 | io_lsu_busreq_r; // @[el2_lsu_clkdomain.scala 75:61] + wire _T_13 = io_lsu_p_valid | io_lsu_pkt_d_valid; // @[el2_lsu_clkdomain.scala 77:48] + wire _T_14 = _T_13 | io_lsu_pkt_m_valid; // @[el2_lsu_clkdomain.scala 77:69] + wire _T_15 = _T_14 | io_lsu_pkt_r_valid; // @[el2_lsu_clkdomain.scala 77:90] + wire _T_17 = _T_15 | _T_11; // @[el2_lsu_clkdomain.scala 77:112] + wire _T_18 = ~io_lsu_stbuf_empty_any; // @[el2_lsu_clkdomain.scala 77:145] + wire _T_19 = _T_17 | _T_18; // @[el2_lsu_clkdomain.scala 77:143] + wire lsu_free_c1_clken = _T_19 | io_clk_override; // @[el2_lsu_clkdomain.scala 77:169] + reg lsu_free_c1_clken_q; // @[el2_lsu_clkdomain.scala 81:60] + wire _T_20 = lsu_free_c1_clken | lsu_free_c1_clken_q; // @[el2_lsu_clkdomain.scala 78:50] + rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), .io_en(rvclkhdr_io_en), .io_scan_mode(rvclkhdr_io_scan_mode) ); - rvclkhdr rvclkhdr_1 ( // @[beh_lib.scala 341:20] + rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 483:22] .io_l1clk(rvclkhdr_1_io_l1clk), .io_clk(rvclkhdr_1_io_clk), .io_en(rvclkhdr_1_io_en), .io_scan_mode(rvclkhdr_1_io_scan_mode) ); - rvclkhdr rvclkhdr_2 ( // @[beh_lib.scala 341:20] + rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 483:22] .io_l1clk(rvclkhdr_2_io_l1clk), .io_clk(rvclkhdr_2_io_clk), .io_en(rvclkhdr_2_io_en), .io_scan_mode(rvclkhdr_2_io_scan_mode) ); - rvclkhdr rvclkhdr_3 ( // @[beh_lib.scala 341:20] + rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 483:22] .io_l1clk(rvclkhdr_3_io_l1clk), .io_clk(rvclkhdr_3_io_clk), .io_en(rvclkhdr_3_io_en), .io_scan_mode(rvclkhdr_3_io_scan_mode) ); - rvclkhdr rvclkhdr_4 ( // @[beh_lib.scala 341:20] + rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 483:22] .io_l1clk(rvclkhdr_4_io_l1clk), .io_clk(rvclkhdr_4_io_clk), .io_en(rvclkhdr_4_io_en), .io_scan_mode(rvclkhdr_4_io_scan_mode) ); - rvclkhdr rvclkhdr_5 ( // @[beh_lib.scala 341:20] + rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 483:22] .io_l1clk(rvclkhdr_5_io_l1clk), .io_clk(rvclkhdr_5_io_clk), .io_en(rvclkhdr_5_io_en), .io_scan_mode(rvclkhdr_5_io_scan_mode) ); - rvclkhdr rvclkhdr_6 ( // @[beh_lib.scala 341:20] + rvclkhdr rvclkhdr_6 ( // @[el2_lib.scala 483:22] .io_l1clk(rvclkhdr_6_io_l1clk), .io_clk(rvclkhdr_6_io_clk), .io_en(rvclkhdr_6_io_en), .io_scan_mode(rvclkhdr_6_io_scan_mode) ); - rvclkhdr rvclkhdr_7 ( // @[beh_lib.scala 341:20] + rvclkhdr rvclkhdr_7 ( // @[el2_lib.scala 483:22] .io_l1clk(rvclkhdr_7_io_l1clk), .io_clk(rvclkhdr_7_io_clk), .io_en(rvclkhdr_7_io_en), .io_scan_mode(rvclkhdr_7_io_scan_mode) ); - rvclkhdr rvclkhdr_8 ( // @[beh_lib.scala 341:20] + rvclkhdr rvclkhdr_8 ( // @[el2_lib.scala 483:22] .io_l1clk(rvclkhdr_8_io_l1clk), .io_clk(rvclkhdr_8_io_clk), .io_en(rvclkhdr_8_io_en), .io_scan_mode(rvclkhdr_8_io_scan_mode) ); - rvclkhdr rvclkhdr_9 ( // @[beh_lib.scala 341:20] + rvclkhdr rvclkhdr_9 ( // @[el2_lib.scala 483:22] .io_l1clk(rvclkhdr_9_io_l1clk), .io_clk(rvclkhdr_9_io_clk), .io_en(rvclkhdr_9_io_en), .io_scan_mode(rvclkhdr_9_io_scan_mode) ); - rvclkhdr rvclkhdr_10 ( // @[beh_lib.scala 341:20] + rvclkhdr rvclkhdr_10 ( // @[el2_lib.scala 483:22] .io_l1clk(rvclkhdr_10_io_l1clk), .io_clk(rvclkhdr_10_io_clk), .io_en(rvclkhdr_10_io_en), .io_scan_mode(rvclkhdr_10_io_scan_mode) ); - rvclkhdr rvclkhdr_11 ( // @[beh_lib.scala 341:20] + rvclkhdr rvclkhdr_11 ( // @[el2_lib.scala 483:22] .io_l1clk(rvclkhdr_11_io_l1clk), .io_clk(rvclkhdr_11_io_clk), .io_en(rvclkhdr_11_io_en), .io_scan_mode(rvclkhdr_11_io_scan_mode) ); - assign io_lsu_c1_m_clk = rvclkhdr_io_l1clk; // @[el2_lsu_clkdomain.scala 86:27] - assign io_lsu_c1_r_clk = rvclkhdr_1_io_l1clk; // @[el2_lsu_clkdomain.scala 87:27] - assign io_lsu_c2_m_clk = rvclkhdr_2_io_l1clk; // @[el2_lsu_clkdomain.scala 88:27] - assign io_lsu_c2_r_clk = rvclkhdr_3_io_l1clk; // @[el2_lsu_clkdomain.scala 89:27] - assign io_lsu_store_c1_m_clk = rvclkhdr_4_io_l1clk; // @[el2_lsu_clkdomain.scala 90:27] - assign io_lsu_store_c1_r_clk = rvclkhdr_5_io_l1clk; // @[el2_lsu_clkdomain.scala 91:27] - assign io_lsu_stbuf_c1_clk = rvclkhdr_6_io_l1clk; // @[el2_lsu_clkdomain.scala 92:27] - assign io_lsu_bus_obuf_c1_clk = rvclkhdr_8_io_l1clk; // @[el2_lsu_clkdomain.scala 94:27] - assign io_lsu_bus_ibuf_c1_clk = rvclkhdr_7_io_l1clk; // @[el2_lsu_clkdomain.scala 93:27] - assign io_lsu_bus_buf_c1_clk = rvclkhdr_9_io_l1clk; // @[el2_lsu_clkdomain.scala 95:27] - assign io_lsu_busm_clk = rvclkhdr_10_io_l1clk; // @[el2_lsu_clkdomain.scala 96:27] - assign io_lsu_free_c2_clk = rvclkhdr_11_io_l1clk; // @[el2_lsu_clkdomain.scala 97:27] - assign rvclkhdr_io_clk = clock; // @[beh_lib.scala 342:15] - assign rvclkhdr_io_en = _T_1 | io_clk_override; // @[beh_lib.scala 343:14] - assign rvclkhdr_io_scan_mode = io_scan_mode; // @[beh_lib.scala 344:21] - assign rvclkhdr_1_io_clk = clock; // @[beh_lib.scala 342:15] - assign rvclkhdr_1_io_en = _T_2 | io_clk_override; // @[beh_lib.scala 343:14] - assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[beh_lib.scala 344:21] - assign rvclkhdr_2_io_clk = clock; // @[beh_lib.scala 342:15] - assign rvclkhdr_2_io_en = _T_3 | io_clk_override; // @[beh_lib.scala 343:14] - assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[beh_lib.scala 344:21] - assign rvclkhdr_3_io_clk = clock; // @[beh_lib.scala 342:15] - assign rvclkhdr_3_io_en = _T_4 | io_clk_override; // @[beh_lib.scala 343:14] - assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[beh_lib.scala 344:21] - assign rvclkhdr_4_io_clk = clock; // @[beh_lib.scala 342:15] - assign rvclkhdr_4_io_en = _T_5 | io_clk_override; // @[beh_lib.scala 343:14] - assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[beh_lib.scala 344:21] - assign rvclkhdr_5_io_clk = clock; // @[beh_lib.scala 342:15] - assign rvclkhdr_5_io_en = _T_6 | io_clk_override; // @[beh_lib.scala 343:14] - assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[beh_lib.scala 344:21] - assign rvclkhdr_6_io_clk = clock; // @[beh_lib.scala 342:15] - assign rvclkhdr_6_io_en = _T_8 | io_clk_override; // @[beh_lib.scala 343:14] - assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[beh_lib.scala 344:21] - assign rvclkhdr_7_io_clk = clock; // @[beh_lib.scala 342:15] - assign rvclkhdr_7_io_en = io_lsu_busreq_r | io_clk_override; // @[beh_lib.scala 343:14] - assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[beh_lib.scala 344:21] - assign rvclkhdr_8_io_clk = clock; // @[beh_lib.scala 342:15] - assign rvclkhdr_8_io_en = _T_10 & io_lsu_bus_clk_en; // @[beh_lib.scala 343:14] - assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[beh_lib.scala 344:21] - assign rvclkhdr_9_io_clk = clock; // @[beh_lib.scala 342:15] - assign rvclkhdr_9_io_en = _T_12 | io_clk_override; // @[beh_lib.scala 343:14] - assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[beh_lib.scala 344:21] - assign rvclkhdr_10_io_clk = clock; // @[beh_lib.scala 342:15] - assign rvclkhdr_10_io_en = io_lsu_bus_clk_en; // @[beh_lib.scala 343:14] - assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[beh_lib.scala 344:21] - assign rvclkhdr_11_io_clk = clock; // @[beh_lib.scala 342:15] - assign rvclkhdr_11_io_en = _T_21 | io_clk_override; // @[beh_lib.scala 343:14] - assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[beh_lib.scala 344:21] + assign io_lsu_c1_m_clk = rvclkhdr_io_l1clk; // @[el2_lsu_clkdomain.scala 86:26] + assign io_lsu_c1_r_clk = rvclkhdr_1_io_l1clk; // @[el2_lsu_clkdomain.scala 87:26] + assign io_lsu_c2_m_clk = rvclkhdr_2_io_l1clk; // @[el2_lsu_clkdomain.scala 88:26] + assign io_lsu_c2_r_clk = rvclkhdr_3_io_l1clk; // @[el2_lsu_clkdomain.scala 89:26] + assign io_lsu_store_c1_m_clk = rvclkhdr_4_io_l1clk; // @[el2_lsu_clkdomain.scala 90:26] + assign io_lsu_store_c1_r_clk = rvclkhdr_5_io_l1clk; // @[el2_lsu_clkdomain.scala 91:26] + assign io_lsu_stbuf_c1_clk = rvclkhdr_6_io_l1clk; // @[el2_lsu_clkdomain.scala 92:26] + assign io_lsu_bus_obuf_c1_clk = rvclkhdr_8_io_l1clk; // @[el2_lsu_clkdomain.scala 94:26] + assign io_lsu_bus_ibuf_c1_clk = rvclkhdr_7_io_l1clk; // @[el2_lsu_clkdomain.scala 93:26] + assign io_lsu_bus_buf_c1_clk = rvclkhdr_9_io_l1clk; // @[el2_lsu_clkdomain.scala 95:26] + assign io_lsu_busm_clk = rvclkhdr_10_io_l1clk; // @[el2_lsu_clkdomain.scala 96:26] + assign io_lsu_free_c2_clk = rvclkhdr_11_io_l1clk; // @[el2_lsu_clkdomain.scala 97:26] + assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_io_en = _T_1 | io_clk_override; // @[el2_lib.scala 485:16] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_1_io_en = _T_2 | io_clk_override; // @[el2_lib.scala 485:16] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_2_io_en = _T_3 | io_clk_override; // @[el2_lib.scala 485:16] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_3_io_en = _T_4 | io_clk_override; // @[el2_lib.scala 485:16] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_4_io_en = _T_5 | io_clk_override; // @[el2_lib.scala 485:16] + assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_5_io_en = _T_6 | io_clk_override; // @[el2_lib.scala 485:16] + assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_6_io_en = _T_8 | io_clk_override; // @[el2_lib.scala 485:16] + assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_7_io_en = io_lsu_busreq_r | io_clk_override; // @[el2_lib.scala 485:16] + assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_8_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_8_io_en = _T_10 & io_lsu_bus_clk_en; // @[el2_lib.scala 485:16] + assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_9_io_en = _T_12 | io_clk_override; // @[el2_lib.scala 485:16] + assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_10_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_10_io_en = io_lsu_bus_clk_en; // @[el2_lib.scala 485:16] + assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_11_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_11_io_en = _T_20 | io_clk_override; // @[el2_lib.scala 485:16] + assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -388,7 +388,7 @@ end // initial if (reset) begin lsu_free_c1_clken_q <= 1'h0; end else begin - lsu_free_c1_clken_q <= _T_20 | io_clk_override; + lsu_free_c1_clken_q <= _T_19 | io_clk_override; end end endmodule diff --git a/el2_lsu_ecc.anno.json b/el2_lsu_ecc.anno.json index c4c5f0d0..29fa30bd 100644 --- a/el2_lsu_ecc.anno.json +++ b/el2_lsu_ecc.anno.json @@ -1,68 +1,4 @@ [ - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_single_ecc_error_r", - "sources":[ - "~el2_lsu_ecc|el2_lsu_ecc>io_single_ecc_error_hi_r", - "~el2_lsu_ecc|el2_lsu_ecc>io_single_ecc_error_lo_r", - "~el2_lsu_ecc|el2_lsu_ecc>io_dec_tlu_core_ecc_disable", - "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_hi_r", - "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_hi_m", - "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_r", - "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_m", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_dma", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_dma", - "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_r", - "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_m", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_r", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_m", - "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_lo_r", - "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_lo_m", - "~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_r", - "~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_m", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_valid", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_valid", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_addr_r", - "~el2_lsu_ecc|el2_lsu_ecc>io_end_addr_r", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_addr_m", - "~el2_lsu_ecc|el2_lsu_ecc>io_end_addr_m", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_load", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_store", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_load", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_store" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_double_ecc_error_m", - "sources":[ - "~el2_lsu_ecc|el2_lsu_ecc>io_dec_tlu_core_ecc_disable", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_dma", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_dma", - "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_hi_r", - "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_hi_m", - "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_r", - "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_m", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_r", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_m", - "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_r", - "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_m", - "~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_r", - "~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_m", - "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_lo_r", - "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_lo_m", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_valid", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_valid", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_addr_r", - "~el2_lsu_ecc|el2_lsu_ecc>io_end_addr_r", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_addr_m", - "~el2_lsu_ecc|el2_lsu_ecc>io_end_addr_m", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_load", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_store", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_load", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_store" - ] - }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_lsu_ecc|el2_lsu_ecc>io_sec_data_hi_r", @@ -72,8 +8,8 @@ "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_r", "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_m", "~el2_lsu_ecc|el2_lsu_ecc>io_dec_tlu_core_ecc_disable", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_dma", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_dma", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_bits_dma", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_bits_dma", "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_r", "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_m", "~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_r", @@ -84,10 +20,41 @@ "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_valid", "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_addr_m", "~el2_lsu_ecc|el2_lsu_ecc>io_end_addr_m", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_load", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_store", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_load", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_store" + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_bits_load", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_bits_store", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_bits_load", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_bits_store" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_double_ecc_error_r", + "sources":[ + "~el2_lsu_ecc|el2_lsu_ecc>io_dec_tlu_core_ecc_disable", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_bits_dma", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_bits_dma", + "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_hi_r", + "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_hi_m", + "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_r", + "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_m", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_r", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_m", + "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_r", + "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_m", + "~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_r", + "~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_m", + "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_lo_r", + "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_lo_m", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_valid", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_valid", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_addr_r", + "~el2_lsu_ecc|el2_lsu_ecc>io_end_addr_r", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_addr_m", + "~el2_lsu_ecc|el2_lsu_ecc>io_end_addr_m", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_bits_load", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_bits_store", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_bits_load", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_bits_store" ] }, { @@ -101,117 +68,6 @@ "~el2_lsu_ecc|el2_lsu_ecc>io_dma_dccm_wen" ] }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_lsu_ecc|el2_lsu_ecc>io_single_ecc_error_lo_r", - "sources":[ - "~el2_lsu_ecc|el2_lsu_ecc>io_dec_tlu_core_ecc_disable", - "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_r", - "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_m", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_r", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_m", - "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_lo_r", - "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_lo_m", - "~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_r", - "~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_m", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_valid", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_valid", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_load", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_store", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_load", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_store" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_lsu_ecc|el2_lsu_ecc>io_sec_data_lo_m", - "sources":[ - "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_r", - "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_m", - "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_lo_r", - "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_lo_m", - "~el2_lsu_ecc|el2_lsu_ecc>io_dec_tlu_core_ecc_disable", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_r", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_m", - "~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_r", - "~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_m", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_valid", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_valid", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_load", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_store", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_load", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_store" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_lsu_ecc|el2_lsu_ecc>io_sec_data_ecc_hi_r_ff", - "sources":[ - "~el2_lsu_ecc|el2_lsu_ecc>io_sec_data_hi_r_ff", - "~el2_lsu_ecc|el2_lsu_ecc>io_ld_single_ecc_error_r_ff", - "~el2_lsu_ecc|el2_lsu_ecc>io_dma_dccm_wdata_hi", - "~el2_lsu_ecc|el2_lsu_ecc>io_stbuf_data_any", - "~el2_lsu_ecc|el2_lsu_ecc>io_dma_dccm_wen" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_double_ecc_error_r", - "sources":[ - "~el2_lsu_ecc|el2_lsu_ecc>io_dec_tlu_core_ecc_disable", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_dma", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_dma", - "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_hi_r", - "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_hi_m", - "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_r", - "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_m", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_r", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_m", - "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_r", - "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_m", - "~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_r", - "~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_m", - "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_lo_r", - "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_lo_m", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_valid", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_valid", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_addr_r", - "~el2_lsu_ecc|el2_lsu_ecc>io_end_addr_r", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_addr_m", - "~el2_lsu_ecc|el2_lsu_ecc>io_end_addr_m", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_load", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_store", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_load", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_store" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_lsu_ecc|el2_lsu_ecc>io_single_ecc_error_hi_r", - "sources":[ - "~el2_lsu_ecc|el2_lsu_ecc>io_dec_tlu_core_ecc_disable", - "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_hi_r", - "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_hi_m", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_dma", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_dma", - "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_r", - "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_m", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_r", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_m", - "~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_r", - "~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_m", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_valid", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_addr_r", - "~el2_lsu_ecc|el2_lsu_ecc>io_end_addr_r", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_valid", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_addr_m", - "~el2_lsu_ecc|el2_lsu_ecc>io_end_addr_m", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_load", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_store", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_load", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_store" - ] - }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_lsu_ecc|el2_lsu_ecc>io_sec_data_lo_r", @@ -227,10 +83,31 @@ "~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_m", "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_valid", "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_valid", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_load", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_store", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_load", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_store" + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_bits_load", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_bits_store", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_bits_load", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_bits_store" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_lsu_ecc|el2_lsu_ecc>io_single_ecc_error_lo_r", + "sources":[ + "~el2_lsu_ecc|el2_lsu_ecc>io_dec_tlu_core_ecc_disable", + "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_r", + "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_m", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_r", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_m", + "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_lo_r", + "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_lo_m", + "~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_r", + "~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_m", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_valid", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_valid", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_bits_load", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_bits_store", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_bits_load", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_bits_store" ] }, { @@ -242,8 +119,8 @@ "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_r", "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_m", "~el2_lsu_ecc|el2_lsu_ecc>io_dec_tlu_core_ecc_disable", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_dma", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_dma", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_bits_dma", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_bits_dma", "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_r", "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_m", "~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_r", @@ -254,10 +131,10 @@ "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_valid", "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_addr_m", "~el2_lsu_ecc|el2_lsu_ecc>io_end_addr_m", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_load", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_store", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_load", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_store" + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_bits_load", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_bits_store", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_bits_load", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_bits_store" ] }, { @@ -269,8 +146,8 @@ "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_hi_m", "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_r", "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_m", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_dma", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_dma", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_bits_dma", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_bits_dma", "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_r", "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_m", "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_r", @@ -285,10 +162,133 @@ "~el2_lsu_ecc|el2_lsu_ecc>io_end_addr_r", "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_addr_m", "~el2_lsu_ecc|el2_lsu_ecc>io_end_addr_m", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_load", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_store", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_load", - "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_store" + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_bits_load", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_bits_store", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_bits_load", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_bits_store" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_lsu_ecc|el2_lsu_ecc>io_sec_data_ecc_hi_r_ff", + "sources":[ + "~el2_lsu_ecc|el2_lsu_ecc>io_sec_data_hi_r_ff", + "~el2_lsu_ecc|el2_lsu_ecc>io_ld_single_ecc_error_r_ff", + "~el2_lsu_ecc|el2_lsu_ecc>io_dma_dccm_wdata_hi", + "~el2_lsu_ecc|el2_lsu_ecc>io_stbuf_data_any", + "~el2_lsu_ecc|el2_lsu_ecc>io_dma_dccm_wen" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_double_ecc_error_m", + "sources":[ + "~el2_lsu_ecc|el2_lsu_ecc>io_dec_tlu_core_ecc_disable", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_bits_dma", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_bits_dma", + "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_hi_r", + "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_hi_m", + "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_r", + "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_m", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_r", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_m", + "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_r", + "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_m", + "~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_r", + "~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_m", + "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_lo_r", + "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_lo_m", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_valid", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_valid", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_addr_r", + "~el2_lsu_ecc|el2_lsu_ecc>io_end_addr_r", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_addr_m", + "~el2_lsu_ecc|el2_lsu_ecc>io_end_addr_m", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_bits_load", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_bits_store", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_bits_load", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_bits_store" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_lsu_ecc|el2_lsu_ecc>io_sec_data_lo_m", + "sources":[ + "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_r", + "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_m", + "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_lo_r", + "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_lo_m", + "~el2_lsu_ecc|el2_lsu_ecc>io_dec_tlu_core_ecc_disable", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_r", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_m", + "~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_r", + "~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_m", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_valid", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_valid", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_bits_load", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_bits_store", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_bits_load", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_bits_store" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_lsu_ecc|el2_lsu_ecc>io_single_ecc_error_hi_r", + "sources":[ + "~el2_lsu_ecc|el2_lsu_ecc>io_dec_tlu_core_ecc_disable", + "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_hi_r", + "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_hi_m", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_bits_dma", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_bits_dma", + "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_r", + "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_m", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_r", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_m", + "~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_r", + "~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_m", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_valid", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_addr_r", + "~el2_lsu_ecc|el2_lsu_ecc>io_end_addr_r", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_valid", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_addr_m", + "~el2_lsu_ecc|el2_lsu_ecc>io_end_addr_m", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_bits_load", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_bits_store", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_bits_load", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_bits_store" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_single_ecc_error_r", + "sources":[ + "~el2_lsu_ecc|el2_lsu_ecc>io_single_ecc_error_hi_r", + "~el2_lsu_ecc|el2_lsu_ecc>io_single_ecc_error_lo_r", + "~el2_lsu_ecc|el2_lsu_ecc>io_dec_tlu_core_ecc_disable", + "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_hi_r", + "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_hi_m", + "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_r", + "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_m", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_bits_dma", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_bits_dma", + "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_r", + "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_m", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_r", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_m", + "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_lo_r", + "~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_lo_m", + "~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_r", + "~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_m", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_valid", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_valid", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_addr_r", + "~el2_lsu_ecc|el2_lsu_ecc>io_end_addr_r", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_addr_m", + "~el2_lsu_ecc|el2_lsu_ecc>io_end_addr_m", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_bits_load", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_bits_store", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_bits_load", + "~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_bits_store" ] }, { @@ -330,8 +330,8 @@ }, { "class":"firrtl.transforms.BlackBoxResourceAnno", - "target":"el2_lsu_ecc.TEC_RV_ICG", - "resourceId":"/vsrc/TEC_RV_ICG.v" + "target":"el2_lsu_ecc.gated_latch", + "resourceId":"/vsrc/gated_latch.v" }, { "class":"firrtl.options.TargetDirAnnotation", diff --git a/el2_lsu_ecc.fir b/el2_lsu_ecc.fir index b544d028..5d65ba89 100644 --- a/el2_lsu_ecc.fir +++ b/el2_lsu_ecc.fir @@ -1,12 +1,12 @@ ;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 circuit el2_lsu_ecc : - extmodule TEC_RV_ICG : + extmodule gated_latch : output Q : Clock input CK : Clock input EN : UInt<1> input SE : UInt<1> - defname = TEC_RV_ICG + defname = gated_latch module rvclkhdr : @@ -14,23 +14,23 @@ circuit el2_lsu_ecc : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of TEC_RV_ICG @[beh_lib.scala 332:24] + inst clkhdr of gated_latch @[el2_lib.scala 474:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12] - clkhdr.CK <= io.clk @[beh_lib.scala 334:16] - clkhdr.EN <= io.en @[beh_lib.scala 335:16] - clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16] + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] - extmodule TEC_RV_ICG_1 : + extmodule gated_latch_1 : output Q : Clock input CK : Clock input EN : UInt<1> input SE : UInt<1> - defname = TEC_RV_ICG + defname = gated_latch module rvclkhdr_1 : @@ -38,20 +38,20 @@ circuit el2_lsu_ecc : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of TEC_RV_ICG_1 @[beh_lib.scala 332:24] + inst clkhdr of gated_latch_1 @[el2_lib.scala 474:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12] - clkhdr.CK <= io.clk @[beh_lib.scala 334:16] - clkhdr.EN <= io.en @[beh_lib.scala 335:16] - clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16] + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] module el2_lsu_ecc : input clock : Clock input reset : AsyncReset - output io : {flip lsu_c2_r_clk : Clock, flip lsu_pkt_m : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip lsu_pkt_r : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip stbuf_data_any : UInt<32>, flip dec_tlu_core_ecc_disable : UInt<1>, flip lsu_dccm_rden_r : UInt<1>, flip addr_in_dccm_r : UInt<1>, flip lsu_addr_r : UInt<16>, flip end_addr_r : UInt<16>, flip lsu_addr_m : UInt<16>, flip end_addr_m : UInt<16>, flip dccm_rdata_hi_r : UInt<32>, flip dccm_rdata_lo_r : UInt<32>, flip dccm_rdata_hi_m : UInt<32>, flip dccm_rdata_lo_m : UInt<32>, flip dccm_data_ecc_hi_r : UInt<7>, flip dccm_data_ecc_lo_r : UInt<7>, flip dccm_data_ecc_hi_m : UInt<7>, flip dccm_data_ecc_lo_m : UInt<7>, flip ld_single_ecc_error_r : UInt<1>, flip ld_single_ecc_error_r_ff : UInt<1>, flip lsu_dccm_rden_m : UInt<1>, flip addr_in_dccm_m : UInt<1>, flip dma_dccm_wen : UInt<1>, flip dma_dccm_wdata_lo : UInt<32>, flip dma_dccm_wdata_hi : UInt<32>, flip scan_mode : UInt<1>, sec_data_hi_r : UInt<32>, sec_data_lo_r : UInt<32>, sec_data_hi_m : UInt<32>, sec_data_lo_m : UInt<32>, sec_data_hi_r_ff : UInt<32>, sec_data_lo_r_ff : UInt<32>, dma_dccm_wdata_ecc_hi : UInt<7>, dma_dccm_wdata_ecc_lo : UInt<7>, stbuf_ecc_any : UInt<7>, sec_data_ecc_hi_r_ff : UInt<7>, sec_data_ecc_lo_r_ff : UInt<7>, single_ecc_error_hi_r : UInt<1>, single_ecc_error_lo_r : UInt<1>, lsu_single_ecc_error_r : UInt<1>, lsu_double_ecc_error_r : UInt<1>, lsu_single_ecc_error_m : UInt<1>, lsu_double_ecc_error_m : UInt<1>} + output io : {flip lsu_c2_r_clk : Clock, flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip stbuf_data_any : UInt<32>, flip dec_tlu_core_ecc_disable : UInt<1>, flip lsu_dccm_rden_r : UInt<1>, flip addr_in_dccm_r : UInt<1>, flip lsu_addr_r : UInt<16>, flip end_addr_r : UInt<16>, flip lsu_addr_m : UInt<16>, flip end_addr_m : UInt<16>, flip dccm_rdata_hi_r : UInt<32>, flip dccm_rdata_lo_r : UInt<32>, flip dccm_rdata_hi_m : UInt<32>, flip dccm_rdata_lo_m : UInt<32>, flip dccm_data_ecc_hi_r : UInt<7>, flip dccm_data_ecc_lo_r : UInt<7>, flip dccm_data_ecc_hi_m : UInt<7>, flip dccm_data_ecc_lo_m : UInt<7>, flip ld_single_ecc_error_r : UInt<1>, flip ld_single_ecc_error_r_ff : UInt<1>, flip lsu_dccm_rden_m : UInt<1>, flip addr_in_dccm_m : UInt<1>, flip dma_dccm_wen : UInt<1>, flip dma_dccm_wdata_lo : UInt<32>, flip dma_dccm_wdata_hi : UInt<32>, flip scan_mode : UInt<1>, sec_data_hi_r : UInt<32>, sec_data_lo_r : UInt<32>, sec_data_hi_m : UInt<32>, sec_data_lo_m : UInt<32>, sec_data_hi_r_ff : UInt<32>, sec_data_lo_r_ff : UInt<32>, dma_dccm_wdata_ecc_hi : UInt<7>, dma_dccm_wdata_ecc_lo : UInt<7>, stbuf_ecc_any : UInt<7>, sec_data_ecc_hi_r_ff : UInt<7>, sec_data_ecc_lo_r_ff : UInt<7>, single_ecc_error_hi_r : UInt<1>, single_ecc_error_lo_r : UInt<1>, lsu_single_ecc_error_r : UInt<1>, lsu_double_ecc_error_r : UInt<1>, lsu_single_ecc_error_m : UInt<1>, lsu_double_ecc_error_m : UInt<1>} wire is_ldst_r : UInt<1> is_ldst_r <= UInt<1>("h00") @@ -97,443 +97,443 @@ circuit el2_lsu_ecc : io.sec_data_lo_m <= UInt<1>("h00") @[el2_lsu_ecc.scala 91:32] io.lsu_single_ecc_error_m <= UInt<1>("h00") @[el2_lsu_ecc.scala 92:30] io.lsu_double_ecc_error_m <= UInt<1>("h00") @[el2_lsu_ecc.scala 93:30] - wire _T : UInt<1>[18] @[el2_lib.scala 304:18] - wire _T_1 : UInt<1>[18] @[el2_lib.scala 305:18] - wire _T_2 : UInt<1>[18] @[el2_lib.scala 306:18] - wire _T_3 : UInt<1>[15] @[el2_lib.scala 307:18] - wire _T_4 : UInt<1>[15] @[el2_lib.scala 308:18] - wire _T_5 : UInt<1>[6] @[el2_lib.scala 309:18] - node _T_6 = bits(dccm_rdata_hi_any, 0, 0) @[el2_lib.scala 316:36] - _T[0] <= _T_6 @[el2_lib.scala 316:30] - node _T_7 = bits(dccm_rdata_hi_any, 0, 0) @[el2_lib.scala 317:36] - _T_1[0] <= _T_7 @[el2_lib.scala 317:30] - node _T_8 = bits(dccm_rdata_hi_any, 1, 1) @[el2_lib.scala 316:36] - _T[1] <= _T_8 @[el2_lib.scala 316:30] - node _T_9 = bits(dccm_rdata_hi_any, 1, 1) @[el2_lib.scala 318:36] - _T_2[0] <= _T_9 @[el2_lib.scala 318:30] - node _T_10 = bits(dccm_rdata_hi_any, 2, 2) @[el2_lib.scala 317:36] - _T_1[1] <= _T_10 @[el2_lib.scala 317:30] - node _T_11 = bits(dccm_rdata_hi_any, 2, 2) @[el2_lib.scala 318:36] - _T_2[1] <= _T_11 @[el2_lib.scala 318:30] - node _T_12 = bits(dccm_rdata_hi_any, 3, 3) @[el2_lib.scala 316:36] - _T[2] <= _T_12 @[el2_lib.scala 316:30] - node _T_13 = bits(dccm_rdata_hi_any, 3, 3) @[el2_lib.scala 317:36] - _T_1[2] <= _T_13 @[el2_lib.scala 317:30] - node _T_14 = bits(dccm_rdata_hi_any, 3, 3) @[el2_lib.scala 318:36] - _T_2[2] <= _T_14 @[el2_lib.scala 318:30] - node _T_15 = bits(dccm_rdata_hi_any, 4, 4) @[el2_lib.scala 316:36] - _T[3] <= _T_15 @[el2_lib.scala 316:30] - node _T_16 = bits(dccm_rdata_hi_any, 4, 4) @[el2_lib.scala 319:36] - _T_3[0] <= _T_16 @[el2_lib.scala 319:30] - node _T_17 = bits(dccm_rdata_hi_any, 5, 5) @[el2_lib.scala 317:36] - _T_1[3] <= _T_17 @[el2_lib.scala 317:30] - node _T_18 = bits(dccm_rdata_hi_any, 5, 5) @[el2_lib.scala 319:36] - _T_3[1] <= _T_18 @[el2_lib.scala 319:30] - node _T_19 = bits(dccm_rdata_hi_any, 6, 6) @[el2_lib.scala 316:36] - _T[4] <= _T_19 @[el2_lib.scala 316:30] - node _T_20 = bits(dccm_rdata_hi_any, 6, 6) @[el2_lib.scala 317:36] - _T_1[4] <= _T_20 @[el2_lib.scala 317:30] - node _T_21 = bits(dccm_rdata_hi_any, 6, 6) @[el2_lib.scala 319:36] - _T_3[2] <= _T_21 @[el2_lib.scala 319:30] - node _T_22 = bits(dccm_rdata_hi_any, 7, 7) @[el2_lib.scala 318:36] - _T_2[3] <= _T_22 @[el2_lib.scala 318:30] - node _T_23 = bits(dccm_rdata_hi_any, 7, 7) @[el2_lib.scala 319:36] - _T_3[3] <= _T_23 @[el2_lib.scala 319:30] - node _T_24 = bits(dccm_rdata_hi_any, 8, 8) @[el2_lib.scala 316:36] - _T[5] <= _T_24 @[el2_lib.scala 316:30] - node _T_25 = bits(dccm_rdata_hi_any, 8, 8) @[el2_lib.scala 318:36] - _T_2[4] <= _T_25 @[el2_lib.scala 318:30] - node _T_26 = bits(dccm_rdata_hi_any, 8, 8) @[el2_lib.scala 319:36] - _T_3[4] <= _T_26 @[el2_lib.scala 319:30] - node _T_27 = bits(dccm_rdata_hi_any, 9, 9) @[el2_lib.scala 317:36] - _T_1[5] <= _T_27 @[el2_lib.scala 317:30] - node _T_28 = bits(dccm_rdata_hi_any, 9, 9) @[el2_lib.scala 318:36] - _T_2[5] <= _T_28 @[el2_lib.scala 318:30] - node _T_29 = bits(dccm_rdata_hi_any, 9, 9) @[el2_lib.scala 319:36] - _T_3[5] <= _T_29 @[el2_lib.scala 319:30] - node _T_30 = bits(dccm_rdata_hi_any, 10, 10) @[el2_lib.scala 316:36] - _T[6] <= _T_30 @[el2_lib.scala 316:30] - node _T_31 = bits(dccm_rdata_hi_any, 10, 10) @[el2_lib.scala 317:36] - _T_1[6] <= _T_31 @[el2_lib.scala 317:30] - node _T_32 = bits(dccm_rdata_hi_any, 10, 10) @[el2_lib.scala 318:36] - _T_2[6] <= _T_32 @[el2_lib.scala 318:30] - node _T_33 = bits(dccm_rdata_hi_any, 10, 10) @[el2_lib.scala 319:36] - _T_3[6] <= _T_33 @[el2_lib.scala 319:30] - node _T_34 = bits(dccm_rdata_hi_any, 11, 11) @[el2_lib.scala 316:36] - _T[7] <= _T_34 @[el2_lib.scala 316:30] - node _T_35 = bits(dccm_rdata_hi_any, 11, 11) @[el2_lib.scala 320:36] - _T_4[0] <= _T_35 @[el2_lib.scala 320:30] - node _T_36 = bits(dccm_rdata_hi_any, 12, 12) @[el2_lib.scala 317:36] - _T_1[7] <= _T_36 @[el2_lib.scala 317:30] - node _T_37 = bits(dccm_rdata_hi_any, 12, 12) @[el2_lib.scala 320:36] - _T_4[1] <= _T_37 @[el2_lib.scala 320:30] - node _T_38 = bits(dccm_rdata_hi_any, 13, 13) @[el2_lib.scala 316:36] - _T[8] <= _T_38 @[el2_lib.scala 316:30] - node _T_39 = bits(dccm_rdata_hi_any, 13, 13) @[el2_lib.scala 317:36] - _T_1[8] <= _T_39 @[el2_lib.scala 317:30] - node _T_40 = bits(dccm_rdata_hi_any, 13, 13) @[el2_lib.scala 320:36] - _T_4[2] <= _T_40 @[el2_lib.scala 320:30] - node _T_41 = bits(dccm_rdata_hi_any, 14, 14) @[el2_lib.scala 318:36] - _T_2[7] <= _T_41 @[el2_lib.scala 318:30] - node _T_42 = bits(dccm_rdata_hi_any, 14, 14) @[el2_lib.scala 320:36] - _T_4[3] <= _T_42 @[el2_lib.scala 320:30] - node _T_43 = bits(dccm_rdata_hi_any, 15, 15) @[el2_lib.scala 316:36] - _T[9] <= _T_43 @[el2_lib.scala 316:30] - node _T_44 = bits(dccm_rdata_hi_any, 15, 15) @[el2_lib.scala 318:36] - _T_2[8] <= _T_44 @[el2_lib.scala 318:30] - node _T_45 = bits(dccm_rdata_hi_any, 15, 15) @[el2_lib.scala 320:36] - _T_4[4] <= _T_45 @[el2_lib.scala 320:30] - node _T_46 = bits(dccm_rdata_hi_any, 16, 16) @[el2_lib.scala 317:36] - _T_1[9] <= _T_46 @[el2_lib.scala 317:30] - node _T_47 = bits(dccm_rdata_hi_any, 16, 16) @[el2_lib.scala 318:36] - _T_2[9] <= _T_47 @[el2_lib.scala 318:30] - node _T_48 = bits(dccm_rdata_hi_any, 16, 16) @[el2_lib.scala 320:36] - _T_4[5] <= _T_48 @[el2_lib.scala 320:30] - node _T_49 = bits(dccm_rdata_hi_any, 17, 17) @[el2_lib.scala 316:36] - _T[10] <= _T_49 @[el2_lib.scala 316:30] - node _T_50 = bits(dccm_rdata_hi_any, 17, 17) @[el2_lib.scala 317:36] - _T_1[10] <= _T_50 @[el2_lib.scala 317:30] - node _T_51 = bits(dccm_rdata_hi_any, 17, 17) @[el2_lib.scala 318:36] - _T_2[10] <= _T_51 @[el2_lib.scala 318:30] - node _T_52 = bits(dccm_rdata_hi_any, 17, 17) @[el2_lib.scala 320:36] - _T_4[6] <= _T_52 @[el2_lib.scala 320:30] - node _T_53 = bits(dccm_rdata_hi_any, 18, 18) @[el2_lib.scala 319:36] - _T_3[7] <= _T_53 @[el2_lib.scala 319:30] - node _T_54 = bits(dccm_rdata_hi_any, 18, 18) @[el2_lib.scala 320:36] - _T_4[7] <= _T_54 @[el2_lib.scala 320:30] - node _T_55 = bits(dccm_rdata_hi_any, 19, 19) @[el2_lib.scala 316:36] - _T[11] <= _T_55 @[el2_lib.scala 316:30] - node _T_56 = bits(dccm_rdata_hi_any, 19, 19) @[el2_lib.scala 319:36] - _T_3[8] <= _T_56 @[el2_lib.scala 319:30] - node _T_57 = bits(dccm_rdata_hi_any, 19, 19) @[el2_lib.scala 320:36] - _T_4[8] <= _T_57 @[el2_lib.scala 320:30] - node _T_58 = bits(dccm_rdata_hi_any, 20, 20) @[el2_lib.scala 317:36] - _T_1[11] <= _T_58 @[el2_lib.scala 317:30] - node _T_59 = bits(dccm_rdata_hi_any, 20, 20) @[el2_lib.scala 319:36] - _T_3[9] <= _T_59 @[el2_lib.scala 319:30] - node _T_60 = bits(dccm_rdata_hi_any, 20, 20) @[el2_lib.scala 320:36] - _T_4[9] <= _T_60 @[el2_lib.scala 320:30] - node _T_61 = bits(dccm_rdata_hi_any, 21, 21) @[el2_lib.scala 316:36] - _T[12] <= _T_61 @[el2_lib.scala 316:30] - node _T_62 = bits(dccm_rdata_hi_any, 21, 21) @[el2_lib.scala 317:36] - _T_1[12] <= _T_62 @[el2_lib.scala 317:30] - node _T_63 = bits(dccm_rdata_hi_any, 21, 21) @[el2_lib.scala 319:36] - _T_3[10] <= _T_63 @[el2_lib.scala 319:30] - node _T_64 = bits(dccm_rdata_hi_any, 21, 21) @[el2_lib.scala 320:36] - _T_4[10] <= _T_64 @[el2_lib.scala 320:30] - node _T_65 = bits(dccm_rdata_hi_any, 22, 22) @[el2_lib.scala 318:36] - _T_2[11] <= _T_65 @[el2_lib.scala 318:30] - node _T_66 = bits(dccm_rdata_hi_any, 22, 22) @[el2_lib.scala 319:36] - _T_3[11] <= _T_66 @[el2_lib.scala 319:30] - node _T_67 = bits(dccm_rdata_hi_any, 22, 22) @[el2_lib.scala 320:36] - _T_4[11] <= _T_67 @[el2_lib.scala 320:30] - node _T_68 = bits(dccm_rdata_hi_any, 23, 23) @[el2_lib.scala 316:36] - _T[13] <= _T_68 @[el2_lib.scala 316:30] - node _T_69 = bits(dccm_rdata_hi_any, 23, 23) @[el2_lib.scala 318:36] - _T_2[12] <= _T_69 @[el2_lib.scala 318:30] - node _T_70 = bits(dccm_rdata_hi_any, 23, 23) @[el2_lib.scala 319:36] - _T_3[12] <= _T_70 @[el2_lib.scala 319:30] - node _T_71 = bits(dccm_rdata_hi_any, 23, 23) @[el2_lib.scala 320:36] - _T_4[12] <= _T_71 @[el2_lib.scala 320:30] - node _T_72 = bits(dccm_rdata_hi_any, 24, 24) @[el2_lib.scala 317:36] - _T_1[13] <= _T_72 @[el2_lib.scala 317:30] - node _T_73 = bits(dccm_rdata_hi_any, 24, 24) @[el2_lib.scala 318:36] - _T_2[13] <= _T_73 @[el2_lib.scala 318:30] - node _T_74 = bits(dccm_rdata_hi_any, 24, 24) @[el2_lib.scala 319:36] - _T_3[13] <= _T_74 @[el2_lib.scala 319:30] - node _T_75 = bits(dccm_rdata_hi_any, 24, 24) @[el2_lib.scala 320:36] - _T_4[13] <= _T_75 @[el2_lib.scala 320:30] - node _T_76 = bits(dccm_rdata_hi_any, 25, 25) @[el2_lib.scala 316:36] - _T[14] <= _T_76 @[el2_lib.scala 316:30] - node _T_77 = bits(dccm_rdata_hi_any, 25, 25) @[el2_lib.scala 317:36] - _T_1[14] <= _T_77 @[el2_lib.scala 317:30] - node _T_78 = bits(dccm_rdata_hi_any, 25, 25) @[el2_lib.scala 318:36] - _T_2[14] <= _T_78 @[el2_lib.scala 318:30] - node _T_79 = bits(dccm_rdata_hi_any, 25, 25) @[el2_lib.scala 319:36] - _T_3[14] <= _T_79 @[el2_lib.scala 319:30] - node _T_80 = bits(dccm_rdata_hi_any, 25, 25) @[el2_lib.scala 320:36] - _T_4[14] <= _T_80 @[el2_lib.scala 320:30] - node _T_81 = bits(dccm_rdata_hi_any, 26, 26) @[el2_lib.scala 316:36] - _T[15] <= _T_81 @[el2_lib.scala 316:30] - node _T_82 = bits(dccm_rdata_hi_any, 26, 26) @[el2_lib.scala 321:36] - _T_5[0] <= _T_82 @[el2_lib.scala 321:30] - node _T_83 = bits(dccm_rdata_hi_any, 27, 27) @[el2_lib.scala 317:36] - _T_1[15] <= _T_83 @[el2_lib.scala 317:30] - node _T_84 = bits(dccm_rdata_hi_any, 27, 27) @[el2_lib.scala 321:36] - _T_5[1] <= _T_84 @[el2_lib.scala 321:30] - node _T_85 = bits(dccm_rdata_hi_any, 28, 28) @[el2_lib.scala 316:36] - _T[16] <= _T_85 @[el2_lib.scala 316:30] - node _T_86 = bits(dccm_rdata_hi_any, 28, 28) @[el2_lib.scala 317:36] - _T_1[16] <= _T_86 @[el2_lib.scala 317:30] - node _T_87 = bits(dccm_rdata_hi_any, 28, 28) @[el2_lib.scala 321:36] - _T_5[2] <= _T_87 @[el2_lib.scala 321:30] - node _T_88 = bits(dccm_rdata_hi_any, 29, 29) @[el2_lib.scala 318:36] - _T_2[15] <= _T_88 @[el2_lib.scala 318:30] - node _T_89 = bits(dccm_rdata_hi_any, 29, 29) @[el2_lib.scala 321:36] - _T_5[3] <= _T_89 @[el2_lib.scala 321:30] - node _T_90 = bits(dccm_rdata_hi_any, 30, 30) @[el2_lib.scala 316:36] - _T[17] <= _T_90 @[el2_lib.scala 316:30] - node _T_91 = bits(dccm_rdata_hi_any, 30, 30) @[el2_lib.scala 318:36] - _T_2[16] <= _T_91 @[el2_lib.scala 318:30] - node _T_92 = bits(dccm_rdata_hi_any, 30, 30) @[el2_lib.scala 321:36] - _T_5[4] <= _T_92 @[el2_lib.scala 321:30] - node _T_93 = bits(dccm_rdata_hi_any, 31, 31) @[el2_lib.scala 317:36] - _T_1[17] <= _T_93 @[el2_lib.scala 317:30] - node _T_94 = bits(dccm_rdata_hi_any, 31, 31) @[el2_lib.scala 318:36] - _T_2[17] <= _T_94 @[el2_lib.scala 318:30] - node _T_95 = bits(dccm_rdata_hi_any, 31, 31) @[el2_lib.scala 321:36] - _T_5[5] <= _T_95 @[el2_lib.scala 321:30] - node _T_96 = xorr(dccm_rdata_hi_any) @[el2_lib.scala 324:30] - node _T_97 = xorr(dccm_data_ecc_hi_any) @[el2_lib.scala 324:44] - node _T_98 = xor(_T_96, _T_97) @[el2_lib.scala 324:35] - node _T_99 = not(UInt<1>("h00")) @[el2_lib.scala 324:52] - node _T_100 = and(_T_98, _T_99) @[el2_lib.scala 324:50] - node _T_101 = bits(dccm_data_ecc_hi_any, 5, 5) @[el2_lib.scala 324:68] - node _T_102 = cat(_T_5[2], _T_5[1]) @[el2_lib.scala 324:76] - node _T_103 = cat(_T_102, _T_5[0]) @[el2_lib.scala 324:76] - node _T_104 = cat(_T_5[5], _T_5[4]) @[el2_lib.scala 324:76] - node _T_105 = cat(_T_104, _T_5[3]) @[el2_lib.scala 324:76] - node _T_106 = cat(_T_105, _T_103) @[el2_lib.scala 324:76] - node _T_107 = xorr(_T_106) @[el2_lib.scala 324:83] - node _T_108 = xor(_T_101, _T_107) @[el2_lib.scala 324:71] - node _T_109 = bits(dccm_data_ecc_hi_any, 4, 4) @[el2_lib.scala 324:95] - node _T_110 = cat(_T_4[2], _T_4[1]) @[el2_lib.scala 324:103] - node _T_111 = cat(_T_110, _T_4[0]) @[el2_lib.scala 324:103] - node _T_112 = cat(_T_4[4], _T_4[3]) @[el2_lib.scala 324:103] - node _T_113 = cat(_T_4[6], _T_4[5]) @[el2_lib.scala 324:103] - node _T_114 = cat(_T_113, _T_112) @[el2_lib.scala 324:103] - node _T_115 = cat(_T_114, _T_111) @[el2_lib.scala 324:103] - node _T_116 = cat(_T_4[8], _T_4[7]) @[el2_lib.scala 324:103] - node _T_117 = cat(_T_4[10], _T_4[9]) @[el2_lib.scala 324:103] - node _T_118 = cat(_T_117, _T_116) @[el2_lib.scala 324:103] - node _T_119 = cat(_T_4[12], _T_4[11]) @[el2_lib.scala 324:103] - node _T_120 = cat(_T_4[14], _T_4[13]) @[el2_lib.scala 324:103] - node _T_121 = cat(_T_120, _T_119) @[el2_lib.scala 324:103] - node _T_122 = cat(_T_121, _T_118) @[el2_lib.scala 324:103] - node _T_123 = cat(_T_122, _T_115) @[el2_lib.scala 324:103] - node _T_124 = xorr(_T_123) @[el2_lib.scala 324:110] - node _T_125 = xor(_T_109, _T_124) @[el2_lib.scala 324:98] - node _T_126 = bits(dccm_data_ecc_hi_any, 3, 3) @[el2_lib.scala 324:122] - node _T_127 = cat(_T_3[2], _T_3[1]) @[el2_lib.scala 324:130] - node _T_128 = cat(_T_127, _T_3[0]) @[el2_lib.scala 324:130] - node _T_129 = cat(_T_3[4], _T_3[3]) @[el2_lib.scala 324:130] - node _T_130 = cat(_T_3[6], _T_3[5]) @[el2_lib.scala 324:130] - node _T_131 = cat(_T_130, _T_129) @[el2_lib.scala 324:130] - node _T_132 = cat(_T_131, _T_128) @[el2_lib.scala 324:130] - node _T_133 = cat(_T_3[8], _T_3[7]) @[el2_lib.scala 324:130] - node _T_134 = cat(_T_3[10], _T_3[9]) @[el2_lib.scala 324:130] - node _T_135 = cat(_T_134, _T_133) @[el2_lib.scala 324:130] - node _T_136 = cat(_T_3[12], _T_3[11]) @[el2_lib.scala 324:130] - node _T_137 = cat(_T_3[14], _T_3[13]) @[el2_lib.scala 324:130] - node _T_138 = cat(_T_137, _T_136) @[el2_lib.scala 324:130] - node _T_139 = cat(_T_138, _T_135) @[el2_lib.scala 324:130] - node _T_140 = cat(_T_139, _T_132) @[el2_lib.scala 324:130] - node _T_141 = xorr(_T_140) @[el2_lib.scala 324:137] - node _T_142 = xor(_T_126, _T_141) @[el2_lib.scala 324:125] - node _T_143 = bits(dccm_data_ecc_hi_any, 2, 2) @[el2_lib.scala 324:149] - node _T_144 = cat(_T_2[1], _T_2[0]) @[el2_lib.scala 324:157] - node _T_145 = cat(_T_2[3], _T_2[2]) @[el2_lib.scala 324:157] - node _T_146 = cat(_T_145, _T_144) @[el2_lib.scala 324:157] - node _T_147 = cat(_T_2[5], _T_2[4]) @[el2_lib.scala 324:157] - node _T_148 = cat(_T_2[8], _T_2[7]) @[el2_lib.scala 324:157] - node _T_149 = cat(_T_148, _T_2[6]) @[el2_lib.scala 324:157] - node _T_150 = cat(_T_149, _T_147) @[el2_lib.scala 324:157] - node _T_151 = cat(_T_150, _T_146) @[el2_lib.scala 324:157] - node _T_152 = cat(_T_2[10], _T_2[9]) @[el2_lib.scala 324:157] - node _T_153 = cat(_T_2[12], _T_2[11]) @[el2_lib.scala 324:157] - node _T_154 = cat(_T_153, _T_152) @[el2_lib.scala 324:157] - node _T_155 = cat(_T_2[14], _T_2[13]) @[el2_lib.scala 324:157] - node _T_156 = cat(_T_2[17], _T_2[16]) @[el2_lib.scala 324:157] - node _T_157 = cat(_T_156, _T_2[15]) @[el2_lib.scala 324:157] - node _T_158 = cat(_T_157, _T_155) @[el2_lib.scala 324:157] - node _T_159 = cat(_T_158, _T_154) @[el2_lib.scala 324:157] - node _T_160 = cat(_T_159, _T_151) @[el2_lib.scala 324:157] - node _T_161 = xorr(_T_160) @[el2_lib.scala 324:164] - node _T_162 = xor(_T_143, _T_161) @[el2_lib.scala 324:152] - node _T_163 = bits(dccm_data_ecc_hi_any, 1, 1) @[el2_lib.scala 324:176] - node _T_164 = cat(_T_1[1], _T_1[0]) @[el2_lib.scala 324:184] - node _T_165 = cat(_T_1[3], _T_1[2]) @[el2_lib.scala 324:184] - node _T_166 = cat(_T_165, _T_164) @[el2_lib.scala 324:184] - node _T_167 = cat(_T_1[5], _T_1[4]) @[el2_lib.scala 324:184] - node _T_168 = cat(_T_1[8], _T_1[7]) @[el2_lib.scala 324:184] - node _T_169 = cat(_T_168, _T_1[6]) @[el2_lib.scala 324:184] - node _T_170 = cat(_T_169, _T_167) @[el2_lib.scala 324:184] - node _T_171 = cat(_T_170, _T_166) @[el2_lib.scala 324:184] - node _T_172 = cat(_T_1[10], _T_1[9]) @[el2_lib.scala 324:184] - node _T_173 = cat(_T_1[12], _T_1[11]) @[el2_lib.scala 324:184] - node _T_174 = cat(_T_173, _T_172) @[el2_lib.scala 324:184] - node _T_175 = cat(_T_1[14], _T_1[13]) @[el2_lib.scala 324:184] - node _T_176 = cat(_T_1[17], _T_1[16]) @[el2_lib.scala 324:184] - node _T_177 = cat(_T_176, _T_1[15]) @[el2_lib.scala 324:184] - node _T_178 = cat(_T_177, _T_175) @[el2_lib.scala 324:184] - node _T_179 = cat(_T_178, _T_174) @[el2_lib.scala 324:184] - node _T_180 = cat(_T_179, _T_171) @[el2_lib.scala 324:184] - node _T_181 = xorr(_T_180) @[el2_lib.scala 324:191] - node _T_182 = xor(_T_163, _T_181) @[el2_lib.scala 324:179] - node _T_183 = bits(dccm_data_ecc_hi_any, 0, 0) @[el2_lib.scala 324:203] - node _T_184 = cat(_T[1], _T[0]) @[el2_lib.scala 324:211] - node _T_185 = cat(_T[3], _T[2]) @[el2_lib.scala 324:211] - node _T_186 = cat(_T_185, _T_184) @[el2_lib.scala 324:211] - node _T_187 = cat(_T[5], _T[4]) @[el2_lib.scala 324:211] - node _T_188 = cat(_T[8], _T[7]) @[el2_lib.scala 324:211] - node _T_189 = cat(_T_188, _T[6]) @[el2_lib.scala 324:211] - node _T_190 = cat(_T_189, _T_187) @[el2_lib.scala 324:211] - node _T_191 = cat(_T_190, _T_186) @[el2_lib.scala 324:211] - node _T_192 = cat(_T[10], _T[9]) @[el2_lib.scala 324:211] - node _T_193 = cat(_T[12], _T[11]) @[el2_lib.scala 324:211] - node _T_194 = cat(_T_193, _T_192) @[el2_lib.scala 324:211] - node _T_195 = cat(_T[14], _T[13]) @[el2_lib.scala 324:211] - node _T_196 = cat(_T[17], _T[16]) @[el2_lib.scala 324:211] - node _T_197 = cat(_T_196, _T[15]) @[el2_lib.scala 324:211] - node _T_198 = cat(_T_197, _T_195) @[el2_lib.scala 324:211] - node _T_199 = cat(_T_198, _T_194) @[el2_lib.scala 324:211] - node _T_200 = cat(_T_199, _T_191) @[el2_lib.scala 324:211] - node _T_201 = xorr(_T_200) @[el2_lib.scala 324:218] - node _T_202 = xor(_T_183, _T_201) @[el2_lib.scala 324:206] + wire _T : UInt<1>[18] @[el2_lib.scala 313:18] + wire _T_1 : UInt<1>[18] @[el2_lib.scala 314:18] + wire _T_2 : UInt<1>[18] @[el2_lib.scala 315:18] + wire _T_3 : UInt<1>[15] @[el2_lib.scala 316:18] + wire _T_4 : UInt<1>[15] @[el2_lib.scala 317:18] + wire _T_5 : UInt<1>[6] @[el2_lib.scala 318:18] + node _T_6 = bits(dccm_rdata_hi_any, 0, 0) @[el2_lib.scala 325:36] + _T[0] <= _T_6 @[el2_lib.scala 325:30] + node _T_7 = bits(dccm_rdata_hi_any, 0, 0) @[el2_lib.scala 326:36] + _T_1[0] <= _T_7 @[el2_lib.scala 326:30] + node _T_8 = bits(dccm_rdata_hi_any, 1, 1) @[el2_lib.scala 325:36] + _T[1] <= _T_8 @[el2_lib.scala 325:30] + node _T_9 = bits(dccm_rdata_hi_any, 1, 1) @[el2_lib.scala 327:36] + _T_2[0] <= _T_9 @[el2_lib.scala 327:30] + node _T_10 = bits(dccm_rdata_hi_any, 2, 2) @[el2_lib.scala 326:36] + _T_1[1] <= _T_10 @[el2_lib.scala 326:30] + node _T_11 = bits(dccm_rdata_hi_any, 2, 2) @[el2_lib.scala 327:36] + _T_2[1] <= _T_11 @[el2_lib.scala 327:30] + node _T_12 = bits(dccm_rdata_hi_any, 3, 3) @[el2_lib.scala 325:36] + _T[2] <= _T_12 @[el2_lib.scala 325:30] + node _T_13 = bits(dccm_rdata_hi_any, 3, 3) @[el2_lib.scala 326:36] + _T_1[2] <= _T_13 @[el2_lib.scala 326:30] + node _T_14 = bits(dccm_rdata_hi_any, 3, 3) @[el2_lib.scala 327:36] + _T_2[2] <= _T_14 @[el2_lib.scala 327:30] + node _T_15 = bits(dccm_rdata_hi_any, 4, 4) @[el2_lib.scala 325:36] + _T[3] <= _T_15 @[el2_lib.scala 325:30] + node _T_16 = bits(dccm_rdata_hi_any, 4, 4) @[el2_lib.scala 328:36] + _T_3[0] <= _T_16 @[el2_lib.scala 328:30] + node _T_17 = bits(dccm_rdata_hi_any, 5, 5) @[el2_lib.scala 326:36] + _T_1[3] <= _T_17 @[el2_lib.scala 326:30] + node _T_18 = bits(dccm_rdata_hi_any, 5, 5) @[el2_lib.scala 328:36] + _T_3[1] <= _T_18 @[el2_lib.scala 328:30] + node _T_19 = bits(dccm_rdata_hi_any, 6, 6) @[el2_lib.scala 325:36] + _T[4] <= _T_19 @[el2_lib.scala 325:30] + node _T_20 = bits(dccm_rdata_hi_any, 6, 6) @[el2_lib.scala 326:36] + _T_1[4] <= _T_20 @[el2_lib.scala 326:30] + node _T_21 = bits(dccm_rdata_hi_any, 6, 6) @[el2_lib.scala 328:36] + _T_3[2] <= _T_21 @[el2_lib.scala 328:30] + node _T_22 = bits(dccm_rdata_hi_any, 7, 7) @[el2_lib.scala 327:36] + _T_2[3] <= _T_22 @[el2_lib.scala 327:30] + node _T_23 = bits(dccm_rdata_hi_any, 7, 7) @[el2_lib.scala 328:36] + _T_3[3] <= _T_23 @[el2_lib.scala 328:30] + node _T_24 = bits(dccm_rdata_hi_any, 8, 8) @[el2_lib.scala 325:36] + _T[5] <= _T_24 @[el2_lib.scala 325:30] + node _T_25 = bits(dccm_rdata_hi_any, 8, 8) @[el2_lib.scala 327:36] + _T_2[4] <= _T_25 @[el2_lib.scala 327:30] + node _T_26 = bits(dccm_rdata_hi_any, 8, 8) @[el2_lib.scala 328:36] + _T_3[4] <= _T_26 @[el2_lib.scala 328:30] + node _T_27 = bits(dccm_rdata_hi_any, 9, 9) @[el2_lib.scala 326:36] + _T_1[5] <= _T_27 @[el2_lib.scala 326:30] + node _T_28 = bits(dccm_rdata_hi_any, 9, 9) @[el2_lib.scala 327:36] + _T_2[5] <= _T_28 @[el2_lib.scala 327:30] + node _T_29 = bits(dccm_rdata_hi_any, 9, 9) @[el2_lib.scala 328:36] + _T_3[5] <= _T_29 @[el2_lib.scala 328:30] + node _T_30 = bits(dccm_rdata_hi_any, 10, 10) @[el2_lib.scala 325:36] + _T[6] <= _T_30 @[el2_lib.scala 325:30] + node _T_31 = bits(dccm_rdata_hi_any, 10, 10) @[el2_lib.scala 326:36] + _T_1[6] <= _T_31 @[el2_lib.scala 326:30] + node _T_32 = bits(dccm_rdata_hi_any, 10, 10) @[el2_lib.scala 327:36] + _T_2[6] <= _T_32 @[el2_lib.scala 327:30] + node _T_33 = bits(dccm_rdata_hi_any, 10, 10) @[el2_lib.scala 328:36] + _T_3[6] <= _T_33 @[el2_lib.scala 328:30] + node _T_34 = bits(dccm_rdata_hi_any, 11, 11) @[el2_lib.scala 325:36] + _T[7] <= _T_34 @[el2_lib.scala 325:30] + node _T_35 = bits(dccm_rdata_hi_any, 11, 11) @[el2_lib.scala 329:36] + _T_4[0] <= _T_35 @[el2_lib.scala 329:30] + node _T_36 = bits(dccm_rdata_hi_any, 12, 12) @[el2_lib.scala 326:36] + _T_1[7] <= _T_36 @[el2_lib.scala 326:30] + node _T_37 = bits(dccm_rdata_hi_any, 12, 12) @[el2_lib.scala 329:36] + _T_4[1] <= _T_37 @[el2_lib.scala 329:30] + node _T_38 = bits(dccm_rdata_hi_any, 13, 13) @[el2_lib.scala 325:36] + _T[8] <= _T_38 @[el2_lib.scala 325:30] + node _T_39 = bits(dccm_rdata_hi_any, 13, 13) @[el2_lib.scala 326:36] + _T_1[8] <= _T_39 @[el2_lib.scala 326:30] + node _T_40 = bits(dccm_rdata_hi_any, 13, 13) @[el2_lib.scala 329:36] + _T_4[2] <= _T_40 @[el2_lib.scala 329:30] + node _T_41 = bits(dccm_rdata_hi_any, 14, 14) @[el2_lib.scala 327:36] + _T_2[7] <= _T_41 @[el2_lib.scala 327:30] + node _T_42 = bits(dccm_rdata_hi_any, 14, 14) @[el2_lib.scala 329:36] + _T_4[3] <= _T_42 @[el2_lib.scala 329:30] + node _T_43 = bits(dccm_rdata_hi_any, 15, 15) @[el2_lib.scala 325:36] + _T[9] <= _T_43 @[el2_lib.scala 325:30] + node _T_44 = bits(dccm_rdata_hi_any, 15, 15) @[el2_lib.scala 327:36] + _T_2[8] <= _T_44 @[el2_lib.scala 327:30] + node _T_45 = bits(dccm_rdata_hi_any, 15, 15) @[el2_lib.scala 329:36] + _T_4[4] <= _T_45 @[el2_lib.scala 329:30] + node _T_46 = bits(dccm_rdata_hi_any, 16, 16) @[el2_lib.scala 326:36] + _T_1[9] <= _T_46 @[el2_lib.scala 326:30] + node _T_47 = bits(dccm_rdata_hi_any, 16, 16) @[el2_lib.scala 327:36] + _T_2[9] <= _T_47 @[el2_lib.scala 327:30] + node _T_48 = bits(dccm_rdata_hi_any, 16, 16) @[el2_lib.scala 329:36] + _T_4[5] <= _T_48 @[el2_lib.scala 329:30] + node _T_49 = bits(dccm_rdata_hi_any, 17, 17) @[el2_lib.scala 325:36] + _T[10] <= _T_49 @[el2_lib.scala 325:30] + node _T_50 = bits(dccm_rdata_hi_any, 17, 17) @[el2_lib.scala 326:36] + _T_1[10] <= _T_50 @[el2_lib.scala 326:30] + node _T_51 = bits(dccm_rdata_hi_any, 17, 17) @[el2_lib.scala 327:36] + _T_2[10] <= _T_51 @[el2_lib.scala 327:30] + node _T_52 = bits(dccm_rdata_hi_any, 17, 17) @[el2_lib.scala 329:36] + _T_4[6] <= _T_52 @[el2_lib.scala 329:30] + node _T_53 = bits(dccm_rdata_hi_any, 18, 18) @[el2_lib.scala 328:36] + _T_3[7] <= _T_53 @[el2_lib.scala 328:30] + node _T_54 = bits(dccm_rdata_hi_any, 18, 18) @[el2_lib.scala 329:36] + _T_4[7] <= _T_54 @[el2_lib.scala 329:30] + node _T_55 = bits(dccm_rdata_hi_any, 19, 19) @[el2_lib.scala 325:36] + _T[11] <= _T_55 @[el2_lib.scala 325:30] + node _T_56 = bits(dccm_rdata_hi_any, 19, 19) @[el2_lib.scala 328:36] + _T_3[8] <= _T_56 @[el2_lib.scala 328:30] + node _T_57 = bits(dccm_rdata_hi_any, 19, 19) @[el2_lib.scala 329:36] + _T_4[8] <= _T_57 @[el2_lib.scala 329:30] + node _T_58 = bits(dccm_rdata_hi_any, 20, 20) @[el2_lib.scala 326:36] + _T_1[11] <= _T_58 @[el2_lib.scala 326:30] + node _T_59 = bits(dccm_rdata_hi_any, 20, 20) @[el2_lib.scala 328:36] + _T_3[9] <= _T_59 @[el2_lib.scala 328:30] + node _T_60 = bits(dccm_rdata_hi_any, 20, 20) @[el2_lib.scala 329:36] + _T_4[9] <= _T_60 @[el2_lib.scala 329:30] + node _T_61 = bits(dccm_rdata_hi_any, 21, 21) @[el2_lib.scala 325:36] + _T[12] <= _T_61 @[el2_lib.scala 325:30] + node _T_62 = bits(dccm_rdata_hi_any, 21, 21) @[el2_lib.scala 326:36] + _T_1[12] <= _T_62 @[el2_lib.scala 326:30] + node _T_63 = bits(dccm_rdata_hi_any, 21, 21) @[el2_lib.scala 328:36] + _T_3[10] <= _T_63 @[el2_lib.scala 328:30] + node _T_64 = bits(dccm_rdata_hi_any, 21, 21) @[el2_lib.scala 329:36] + _T_4[10] <= _T_64 @[el2_lib.scala 329:30] + node _T_65 = bits(dccm_rdata_hi_any, 22, 22) @[el2_lib.scala 327:36] + _T_2[11] <= _T_65 @[el2_lib.scala 327:30] + node _T_66 = bits(dccm_rdata_hi_any, 22, 22) @[el2_lib.scala 328:36] + _T_3[11] <= _T_66 @[el2_lib.scala 328:30] + node _T_67 = bits(dccm_rdata_hi_any, 22, 22) @[el2_lib.scala 329:36] + _T_4[11] <= _T_67 @[el2_lib.scala 329:30] + node _T_68 = bits(dccm_rdata_hi_any, 23, 23) @[el2_lib.scala 325:36] + _T[13] <= _T_68 @[el2_lib.scala 325:30] + node _T_69 = bits(dccm_rdata_hi_any, 23, 23) @[el2_lib.scala 327:36] + _T_2[12] <= _T_69 @[el2_lib.scala 327:30] + node _T_70 = bits(dccm_rdata_hi_any, 23, 23) @[el2_lib.scala 328:36] + _T_3[12] <= _T_70 @[el2_lib.scala 328:30] + node _T_71 = bits(dccm_rdata_hi_any, 23, 23) @[el2_lib.scala 329:36] + _T_4[12] <= _T_71 @[el2_lib.scala 329:30] + node _T_72 = bits(dccm_rdata_hi_any, 24, 24) @[el2_lib.scala 326:36] + _T_1[13] <= _T_72 @[el2_lib.scala 326:30] + node _T_73 = bits(dccm_rdata_hi_any, 24, 24) @[el2_lib.scala 327:36] + _T_2[13] <= _T_73 @[el2_lib.scala 327:30] + node _T_74 = bits(dccm_rdata_hi_any, 24, 24) @[el2_lib.scala 328:36] + _T_3[13] <= _T_74 @[el2_lib.scala 328:30] + node _T_75 = bits(dccm_rdata_hi_any, 24, 24) @[el2_lib.scala 329:36] + _T_4[13] <= _T_75 @[el2_lib.scala 329:30] + node _T_76 = bits(dccm_rdata_hi_any, 25, 25) @[el2_lib.scala 325:36] + _T[14] <= _T_76 @[el2_lib.scala 325:30] + node _T_77 = bits(dccm_rdata_hi_any, 25, 25) @[el2_lib.scala 326:36] + _T_1[14] <= _T_77 @[el2_lib.scala 326:30] + node _T_78 = bits(dccm_rdata_hi_any, 25, 25) @[el2_lib.scala 327:36] + _T_2[14] <= _T_78 @[el2_lib.scala 327:30] + node _T_79 = bits(dccm_rdata_hi_any, 25, 25) @[el2_lib.scala 328:36] + _T_3[14] <= _T_79 @[el2_lib.scala 328:30] + node _T_80 = bits(dccm_rdata_hi_any, 25, 25) @[el2_lib.scala 329:36] + _T_4[14] <= _T_80 @[el2_lib.scala 329:30] + node _T_81 = bits(dccm_rdata_hi_any, 26, 26) @[el2_lib.scala 325:36] + _T[15] <= _T_81 @[el2_lib.scala 325:30] + node _T_82 = bits(dccm_rdata_hi_any, 26, 26) @[el2_lib.scala 330:36] + _T_5[0] <= _T_82 @[el2_lib.scala 330:30] + node _T_83 = bits(dccm_rdata_hi_any, 27, 27) @[el2_lib.scala 326:36] + _T_1[15] <= _T_83 @[el2_lib.scala 326:30] + node _T_84 = bits(dccm_rdata_hi_any, 27, 27) @[el2_lib.scala 330:36] + _T_5[1] <= _T_84 @[el2_lib.scala 330:30] + node _T_85 = bits(dccm_rdata_hi_any, 28, 28) @[el2_lib.scala 325:36] + _T[16] <= _T_85 @[el2_lib.scala 325:30] + node _T_86 = bits(dccm_rdata_hi_any, 28, 28) @[el2_lib.scala 326:36] + _T_1[16] <= _T_86 @[el2_lib.scala 326:30] + node _T_87 = bits(dccm_rdata_hi_any, 28, 28) @[el2_lib.scala 330:36] + _T_5[2] <= _T_87 @[el2_lib.scala 330:30] + node _T_88 = bits(dccm_rdata_hi_any, 29, 29) @[el2_lib.scala 327:36] + _T_2[15] <= _T_88 @[el2_lib.scala 327:30] + node _T_89 = bits(dccm_rdata_hi_any, 29, 29) @[el2_lib.scala 330:36] + _T_5[3] <= _T_89 @[el2_lib.scala 330:30] + node _T_90 = bits(dccm_rdata_hi_any, 30, 30) @[el2_lib.scala 325:36] + _T[17] <= _T_90 @[el2_lib.scala 325:30] + node _T_91 = bits(dccm_rdata_hi_any, 30, 30) @[el2_lib.scala 327:36] + _T_2[16] <= _T_91 @[el2_lib.scala 327:30] + node _T_92 = bits(dccm_rdata_hi_any, 30, 30) @[el2_lib.scala 330:36] + _T_5[4] <= _T_92 @[el2_lib.scala 330:30] + node _T_93 = bits(dccm_rdata_hi_any, 31, 31) @[el2_lib.scala 326:36] + _T_1[17] <= _T_93 @[el2_lib.scala 326:30] + node _T_94 = bits(dccm_rdata_hi_any, 31, 31) @[el2_lib.scala 327:36] + _T_2[17] <= _T_94 @[el2_lib.scala 327:30] + node _T_95 = bits(dccm_rdata_hi_any, 31, 31) @[el2_lib.scala 330:36] + _T_5[5] <= _T_95 @[el2_lib.scala 330:30] + node _T_96 = xorr(dccm_rdata_hi_any) @[el2_lib.scala 333:30] + node _T_97 = xorr(dccm_data_ecc_hi_any) @[el2_lib.scala 333:44] + node _T_98 = xor(_T_96, _T_97) @[el2_lib.scala 333:35] + node _T_99 = not(UInt<1>("h00")) @[el2_lib.scala 333:52] + node _T_100 = and(_T_98, _T_99) @[el2_lib.scala 333:50] + node _T_101 = bits(dccm_data_ecc_hi_any, 5, 5) @[el2_lib.scala 333:68] + node _T_102 = cat(_T_5[2], _T_5[1]) @[el2_lib.scala 333:76] + node _T_103 = cat(_T_102, _T_5[0]) @[el2_lib.scala 333:76] + node _T_104 = cat(_T_5[5], _T_5[4]) @[el2_lib.scala 333:76] + node _T_105 = cat(_T_104, _T_5[3]) @[el2_lib.scala 333:76] + node _T_106 = cat(_T_105, _T_103) @[el2_lib.scala 333:76] + node _T_107 = xorr(_T_106) @[el2_lib.scala 333:83] + node _T_108 = xor(_T_101, _T_107) @[el2_lib.scala 333:71] + node _T_109 = bits(dccm_data_ecc_hi_any, 4, 4) @[el2_lib.scala 333:95] + node _T_110 = cat(_T_4[2], _T_4[1]) @[el2_lib.scala 333:103] + node _T_111 = cat(_T_110, _T_4[0]) @[el2_lib.scala 333:103] + node _T_112 = cat(_T_4[4], _T_4[3]) @[el2_lib.scala 333:103] + node _T_113 = cat(_T_4[6], _T_4[5]) @[el2_lib.scala 333:103] + node _T_114 = cat(_T_113, _T_112) @[el2_lib.scala 333:103] + node _T_115 = cat(_T_114, _T_111) @[el2_lib.scala 333:103] + node _T_116 = cat(_T_4[8], _T_4[7]) @[el2_lib.scala 333:103] + node _T_117 = cat(_T_4[10], _T_4[9]) @[el2_lib.scala 333:103] + node _T_118 = cat(_T_117, _T_116) @[el2_lib.scala 333:103] + node _T_119 = cat(_T_4[12], _T_4[11]) @[el2_lib.scala 333:103] + node _T_120 = cat(_T_4[14], _T_4[13]) @[el2_lib.scala 333:103] + node _T_121 = cat(_T_120, _T_119) @[el2_lib.scala 333:103] + node _T_122 = cat(_T_121, _T_118) @[el2_lib.scala 333:103] + node _T_123 = cat(_T_122, _T_115) @[el2_lib.scala 333:103] + node _T_124 = xorr(_T_123) @[el2_lib.scala 333:110] + node _T_125 = xor(_T_109, _T_124) @[el2_lib.scala 333:98] + node _T_126 = bits(dccm_data_ecc_hi_any, 3, 3) @[el2_lib.scala 333:122] + node _T_127 = cat(_T_3[2], _T_3[1]) @[el2_lib.scala 333:130] + node _T_128 = cat(_T_127, _T_3[0]) @[el2_lib.scala 333:130] + node _T_129 = cat(_T_3[4], _T_3[3]) @[el2_lib.scala 333:130] + node _T_130 = cat(_T_3[6], _T_3[5]) @[el2_lib.scala 333:130] + node _T_131 = cat(_T_130, _T_129) @[el2_lib.scala 333:130] + node _T_132 = cat(_T_131, _T_128) @[el2_lib.scala 333:130] + node _T_133 = cat(_T_3[8], _T_3[7]) @[el2_lib.scala 333:130] + node _T_134 = cat(_T_3[10], _T_3[9]) @[el2_lib.scala 333:130] + node _T_135 = cat(_T_134, _T_133) @[el2_lib.scala 333:130] + node _T_136 = cat(_T_3[12], _T_3[11]) @[el2_lib.scala 333:130] + node _T_137 = cat(_T_3[14], _T_3[13]) @[el2_lib.scala 333:130] + node _T_138 = cat(_T_137, _T_136) @[el2_lib.scala 333:130] + node _T_139 = cat(_T_138, _T_135) @[el2_lib.scala 333:130] + node _T_140 = cat(_T_139, _T_132) @[el2_lib.scala 333:130] + node _T_141 = xorr(_T_140) @[el2_lib.scala 333:137] + node _T_142 = xor(_T_126, _T_141) @[el2_lib.scala 333:125] + node _T_143 = bits(dccm_data_ecc_hi_any, 2, 2) @[el2_lib.scala 333:149] + node _T_144 = cat(_T_2[1], _T_2[0]) @[el2_lib.scala 333:157] + node _T_145 = cat(_T_2[3], _T_2[2]) @[el2_lib.scala 333:157] + node _T_146 = cat(_T_145, _T_144) @[el2_lib.scala 333:157] + node _T_147 = cat(_T_2[5], _T_2[4]) @[el2_lib.scala 333:157] + node _T_148 = cat(_T_2[8], _T_2[7]) @[el2_lib.scala 333:157] + node _T_149 = cat(_T_148, _T_2[6]) @[el2_lib.scala 333:157] + node _T_150 = cat(_T_149, _T_147) @[el2_lib.scala 333:157] + node _T_151 = cat(_T_150, _T_146) @[el2_lib.scala 333:157] + node _T_152 = cat(_T_2[10], _T_2[9]) @[el2_lib.scala 333:157] + node _T_153 = cat(_T_2[12], _T_2[11]) @[el2_lib.scala 333:157] + node _T_154 = cat(_T_153, _T_152) @[el2_lib.scala 333:157] + node _T_155 = cat(_T_2[14], _T_2[13]) @[el2_lib.scala 333:157] + node _T_156 = cat(_T_2[17], _T_2[16]) @[el2_lib.scala 333:157] + node _T_157 = cat(_T_156, _T_2[15]) @[el2_lib.scala 333:157] + node _T_158 = cat(_T_157, _T_155) @[el2_lib.scala 333:157] + node _T_159 = cat(_T_158, _T_154) @[el2_lib.scala 333:157] + node _T_160 = cat(_T_159, _T_151) @[el2_lib.scala 333:157] + node _T_161 = xorr(_T_160) @[el2_lib.scala 333:164] + node _T_162 = xor(_T_143, _T_161) @[el2_lib.scala 333:152] + node _T_163 = bits(dccm_data_ecc_hi_any, 1, 1) @[el2_lib.scala 333:176] + node _T_164 = cat(_T_1[1], _T_1[0]) @[el2_lib.scala 333:184] + node _T_165 = cat(_T_1[3], _T_1[2]) @[el2_lib.scala 333:184] + node _T_166 = cat(_T_165, _T_164) @[el2_lib.scala 333:184] + node _T_167 = cat(_T_1[5], _T_1[4]) @[el2_lib.scala 333:184] + node _T_168 = cat(_T_1[8], _T_1[7]) @[el2_lib.scala 333:184] + node _T_169 = cat(_T_168, _T_1[6]) @[el2_lib.scala 333:184] + node _T_170 = cat(_T_169, _T_167) @[el2_lib.scala 333:184] + node _T_171 = cat(_T_170, _T_166) @[el2_lib.scala 333:184] + node _T_172 = cat(_T_1[10], _T_1[9]) @[el2_lib.scala 333:184] + node _T_173 = cat(_T_1[12], _T_1[11]) @[el2_lib.scala 333:184] + node _T_174 = cat(_T_173, _T_172) @[el2_lib.scala 333:184] + node _T_175 = cat(_T_1[14], _T_1[13]) @[el2_lib.scala 333:184] + node _T_176 = cat(_T_1[17], _T_1[16]) @[el2_lib.scala 333:184] + node _T_177 = cat(_T_176, _T_1[15]) @[el2_lib.scala 333:184] + node _T_178 = cat(_T_177, _T_175) @[el2_lib.scala 333:184] + node _T_179 = cat(_T_178, _T_174) @[el2_lib.scala 333:184] + node _T_180 = cat(_T_179, _T_171) @[el2_lib.scala 333:184] + node _T_181 = xorr(_T_180) @[el2_lib.scala 333:191] + node _T_182 = xor(_T_163, _T_181) @[el2_lib.scala 333:179] + node _T_183 = bits(dccm_data_ecc_hi_any, 0, 0) @[el2_lib.scala 333:203] + node _T_184 = cat(_T[1], _T[0]) @[el2_lib.scala 333:211] + node _T_185 = cat(_T[3], _T[2]) @[el2_lib.scala 333:211] + node _T_186 = cat(_T_185, _T_184) @[el2_lib.scala 333:211] + node _T_187 = cat(_T[5], _T[4]) @[el2_lib.scala 333:211] + node _T_188 = cat(_T[8], _T[7]) @[el2_lib.scala 333:211] + node _T_189 = cat(_T_188, _T[6]) @[el2_lib.scala 333:211] + node _T_190 = cat(_T_189, _T_187) @[el2_lib.scala 333:211] + node _T_191 = cat(_T_190, _T_186) @[el2_lib.scala 333:211] + node _T_192 = cat(_T[10], _T[9]) @[el2_lib.scala 333:211] + node _T_193 = cat(_T[12], _T[11]) @[el2_lib.scala 333:211] + node _T_194 = cat(_T_193, _T_192) @[el2_lib.scala 333:211] + node _T_195 = cat(_T[14], _T[13]) @[el2_lib.scala 333:211] + node _T_196 = cat(_T[17], _T[16]) @[el2_lib.scala 333:211] + node _T_197 = cat(_T_196, _T[15]) @[el2_lib.scala 333:211] + node _T_198 = cat(_T_197, _T_195) @[el2_lib.scala 333:211] + node _T_199 = cat(_T_198, _T_194) @[el2_lib.scala 333:211] + node _T_200 = cat(_T_199, _T_191) @[el2_lib.scala 333:211] + node _T_201 = xorr(_T_200) @[el2_lib.scala 333:218] + node _T_202 = xor(_T_183, _T_201) @[el2_lib.scala 333:206] node _T_203 = cat(_T_162, _T_182) @[Cat.scala 29:58] node _T_204 = cat(_T_203, _T_202) @[Cat.scala 29:58] node _T_205 = cat(_T_125, _T_142) @[Cat.scala 29:58] node _T_206 = cat(_T_100, _T_108) @[Cat.scala 29:58] node _T_207 = cat(_T_206, _T_205) @[Cat.scala 29:58] node _T_208 = cat(_T_207, _T_204) @[Cat.scala 29:58] - node _T_209 = neq(_T_208, UInt<1>("h00")) @[el2_lib.scala 325:44] - node _T_210 = and(is_ldst_hi_any, _T_209) @[el2_lib.scala 325:32] - node _T_211 = bits(_T_208, 6, 6) @[el2_lib.scala 325:64] - node single_ecc_error_hi_any = and(_T_210, _T_211) @[el2_lib.scala 325:53] - node _T_212 = neq(_T_208, UInt<1>("h00")) @[el2_lib.scala 326:44] - node _T_213 = and(is_ldst_hi_any, _T_212) @[el2_lib.scala 326:32] - node _T_214 = bits(_T_208, 6, 6) @[el2_lib.scala 326:65] - node _T_215 = not(_T_214) @[el2_lib.scala 326:55] - node double_ecc_error_hi_any = and(_T_213, _T_215) @[el2_lib.scala 326:53] - wire _T_216 : UInt<1>[39] @[el2_lib.scala 327:26] - node _T_217 = bits(_T_208, 5, 0) @[el2_lib.scala 330:35] - node _T_218 = eq(_T_217, UInt<1>("h01")) @[el2_lib.scala 330:41] - _T_216[0] <= _T_218 @[el2_lib.scala 330:23] - node _T_219 = bits(_T_208, 5, 0) @[el2_lib.scala 330:35] - node _T_220 = eq(_T_219, UInt<2>("h02")) @[el2_lib.scala 330:41] - _T_216[1] <= _T_220 @[el2_lib.scala 330:23] - node _T_221 = bits(_T_208, 5, 0) @[el2_lib.scala 330:35] - node _T_222 = eq(_T_221, UInt<2>("h03")) @[el2_lib.scala 330:41] - _T_216[2] <= _T_222 @[el2_lib.scala 330:23] - node _T_223 = bits(_T_208, 5, 0) @[el2_lib.scala 330:35] - node _T_224 = eq(_T_223, UInt<3>("h04")) @[el2_lib.scala 330:41] - _T_216[3] <= _T_224 @[el2_lib.scala 330:23] - node _T_225 = bits(_T_208, 5, 0) @[el2_lib.scala 330:35] - node _T_226 = eq(_T_225, UInt<3>("h05")) @[el2_lib.scala 330:41] - _T_216[4] <= _T_226 @[el2_lib.scala 330:23] - node _T_227 = bits(_T_208, 5, 0) @[el2_lib.scala 330:35] - node _T_228 = eq(_T_227, UInt<3>("h06")) @[el2_lib.scala 330:41] - _T_216[5] <= _T_228 @[el2_lib.scala 330:23] - node _T_229 = bits(_T_208, 5, 0) @[el2_lib.scala 330:35] - node _T_230 = eq(_T_229, UInt<3>("h07")) @[el2_lib.scala 330:41] - _T_216[6] <= _T_230 @[el2_lib.scala 330:23] - node _T_231 = bits(_T_208, 5, 0) @[el2_lib.scala 330:35] - node _T_232 = eq(_T_231, UInt<4>("h08")) @[el2_lib.scala 330:41] - _T_216[7] <= _T_232 @[el2_lib.scala 330:23] - node _T_233 = bits(_T_208, 5, 0) @[el2_lib.scala 330:35] - node _T_234 = eq(_T_233, UInt<4>("h09")) @[el2_lib.scala 330:41] - _T_216[8] <= _T_234 @[el2_lib.scala 330:23] - node _T_235 = bits(_T_208, 5, 0) @[el2_lib.scala 330:35] - node _T_236 = eq(_T_235, UInt<4>("h0a")) @[el2_lib.scala 330:41] - _T_216[9] <= _T_236 @[el2_lib.scala 330:23] - node _T_237 = bits(_T_208, 5, 0) @[el2_lib.scala 330:35] - node _T_238 = eq(_T_237, UInt<4>("h0b")) @[el2_lib.scala 330:41] - _T_216[10] <= _T_238 @[el2_lib.scala 330:23] - node _T_239 = bits(_T_208, 5, 0) @[el2_lib.scala 330:35] - node _T_240 = eq(_T_239, UInt<4>("h0c")) @[el2_lib.scala 330:41] - _T_216[11] <= _T_240 @[el2_lib.scala 330:23] - node _T_241 = bits(_T_208, 5, 0) @[el2_lib.scala 330:35] - node _T_242 = eq(_T_241, UInt<4>("h0d")) @[el2_lib.scala 330:41] - _T_216[12] <= _T_242 @[el2_lib.scala 330:23] - node _T_243 = bits(_T_208, 5, 0) @[el2_lib.scala 330:35] - node _T_244 = eq(_T_243, UInt<4>("h0e")) @[el2_lib.scala 330:41] - _T_216[13] <= _T_244 @[el2_lib.scala 330:23] - node _T_245 = bits(_T_208, 5, 0) @[el2_lib.scala 330:35] - node _T_246 = eq(_T_245, UInt<4>("h0f")) @[el2_lib.scala 330:41] - _T_216[14] <= _T_246 @[el2_lib.scala 330:23] - node _T_247 = bits(_T_208, 5, 0) @[el2_lib.scala 330:35] - node _T_248 = eq(_T_247, UInt<5>("h010")) @[el2_lib.scala 330:41] - _T_216[15] <= _T_248 @[el2_lib.scala 330:23] - node _T_249 = bits(_T_208, 5, 0) @[el2_lib.scala 330:35] - node _T_250 = eq(_T_249, UInt<5>("h011")) @[el2_lib.scala 330:41] - _T_216[16] <= _T_250 @[el2_lib.scala 330:23] - node _T_251 = bits(_T_208, 5, 0) @[el2_lib.scala 330:35] - node _T_252 = eq(_T_251, UInt<5>("h012")) @[el2_lib.scala 330:41] - _T_216[17] <= _T_252 @[el2_lib.scala 330:23] - node _T_253 = bits(_T_208, 5, 0) @[el2_lib.scala 330:35] - node _T_254 = eq(_T_253, UInt<5>("h013")) @[el2_lib.scala 330:41] - _T_216[18] <= _T_254 @[el2_lib.scala 330:23] - node _T_255 = bits(_T_208, 5, 0) @[el2_lib.scala 330:35] - node _T_256 = eq(_T_255, UInt<5>("h014")) @[el2_lib.scala 330:41] - _T_216[19] <= _T_256 @[el2_lib.scala 330:23] - node _T_257 = bits(_T_208, 5, 0) @[el2_lib.scala 330:35] - node _T_258 = eq(_T_257, UInt<5>("h015")) @[el2_lib.scala 330:41] - _T_216[20] <= _T_258 @[el2_lib.scala 330:23] - node _T_259 = bits(_T_208, 5, 0) @[el2_lib.scala 330:35] - node _T_260 = eq(_T_259, UInt<5>("h016")) @[el2_lib.scala 330:41] - _T_216[21] <= _T_260 @[el2_lib.scala 330:23] - node _T_261 = bits(_T_208, 5, 0) @[el2_lib.scala 330:35] - node _T_262 = eq(_T_261, UInt<5>("h017")) @[el2_lib.scala 330:41] - _T_216[22] <= _T_262 @[el2_lib.scala 330:23] - node _T_263 = bits(_T_208, 5, 0) @[el2_lib.scala 330:35] - node _T_264 = eq(_T_263, UInt<5>("h018")) @[el2_lib.scala 330:41] - _T_216[23] <= _T_264 @[el2_lib.scala 330:23] - node _T_265 = bits(_T_208, 5, 0) @[el2_lib.scala 330:35] - node _T_266 = eq(_T_265, UInt<5>("h019")) @[el2_lib.scala 330:41] - _T_216[24] <= _T_266 @[el2_lib.scala 330:23] - node _T_267 = bits(_T_208, 5, 0) @[el2_lib.scala 330:35] - node _T_268 = eq(_T_267, UInt<5>("h01a")) @[el2_lib.scala 330:41] - _T_216[25] <= _T_268 @[el2_lib.scala 330:23] - node _T_269 = bits(_T_208, 5, 0) @[el2_lib.scala 330:35] - node _T_270 = eq(_T_269, UInt<5>("h01b")) @[el2_lib.scala 330:41] - _T_216[26] <= _T_270 @[el2_lib.scala 330:23] - node _T_271 = bits(_T_208, 5, 0) @[el2_lib.scala 330:35] - node _T_272 = eq(_T_271, UInt<5>("h01c")) @[el2_lib.scala 330:41] - _T_216[27] <= _T_272 @[el2_lib.scala 330:23] - node _T_273 = bits(_T_208, 5, 0) @[el2_lib.scala 330:35] - node _T_274 = eq(_T_273, UInt<5>("h01d")) @[el2_lib.scala 330:41] - _T_216[28] <= _T_274 @[el2_lib.scala 330:23] - node _T_275 = bits(_T_208, 5, 0) @[el2_lib.scala 330:35] - node _T_276 = eq(_T_275, UInt<5>("h01e")) @[el2_lib.scala 330:41] - _T_216[29] <= _T_276 @[el2_lib.scala 330:23] - node _T_277 = bits(_T_208, 5, 0) @[el2_lib.scala 330:35] - node _T_278 = eq(_T_277, UInt<5>("h01f")) @[el2_lib.scala 330:41] - _T_216[30] <= _T_278 @[el2_lib.scala 330:23] - node _T_279 = bits(_T_208, 5, 0) @[el2_lib.scala 330:35] - node _T_280 = eq(_T_279, UInt<6>("h020")) @[el2_lib.scala 330:41] - _T_216[31] <= _T_280 @[el2_lib.scala 330:23] - node _T_281 = bits(_T_208, 5, 0) @[el2_lib.scala 330:35] - node _T_282 = eq(_T_281, UInt<6>("h021")) @[el2_lib.scala 330:41] - _T_216[32] <= _T_282 @[el2_lib.scala 330:23] - node _T_283 = bits(_T_208, 5, 0) @[el2_lib.scala 330:35] - node _T_284 = eq(_T_283, UInt<6>("h022")) @[el2_lib.scala 330:41] - _T_216[33] <= _T_284 @[el2_lib.scala 330:23] - node _T_285 = bits(_T_208, 5, 0) @[el2_lib.scala 330:35] - node _T_286 = eq(_T_285, UInt<6>("h023")) @[el2_lib.scala 330:41] - _T_216[34] <= _T_286 @[el2_lib.scala 330:23] - node _T_287 = bits(_T_208, 5, 0) @[el2_lib.scala 330:35] - node _T_288 = eq(_T_287, UInt<6>("h024")) @[el2_lib.scala 330:41] - _T_216[35] <= _T_288 @[el2_lib.scala 330:23] - node _T_289 = bits(_T_208, 5, 0) @[el2_lib.scala 330:35] - node _T_290 = eq(_T_289, UInt<6>("h025")) @[el2_lib.scala 330:41] - _T_216[36] <= _T_290 @[el2_lib.scala 330:23] - node _T_291 = bits(_T_208, 5, 0) @[el2_lib.scala 330:35] - node _T_292 = eq(_T_291, UInt<6>("h026")) @[el2_lib.scala 330:41] - _T_216[37] <= _T_292 @[el2_lib.scala 330:23] - node _T_293 = bits(_T_208, 5, 0) @[el2_lib.scala 330:35] - node _T_294 = eq(_T_293, UInt<6>("h027")) @[el2_lib.scala 330:41] - _T_216[38] <= _T_294 @[el2_lib.scala 330:23] - node _T_295 = bits(dccm_data_ecc_hi_any, 6, 6) @[el2_lib.scala 332:37] - node _T_296 = bits(dccm_rdata_hi_any, 31, 26) @[el2_lib.scala 332:45] - node _T_297 = bits(dccm_data_ecc_hi_any, 5, 5) @[el2_lib.scala 332:60] - node _T_298 = bits(dccm_rdata_hi_any, 25, 11) @[el2_lib.scala 332:68] - node _T_299 = bits(dccm_data_ecc_hi_any, 4, 4) @[el2_lib.scala 332:83] - node _T_300 = bits(dccm_rdata_hi_any, 10, 4) @[el2_lib.scala 332:91] - node _T_301 = bits(dccm_data_ecc_hi_any, 3, 3) @[el2_lib.scala 332:105] - node _T_302 = bits(dccm_rdata_hi_any, 3, 1) @[el2_lib.scala 332:113] - node _T_303 = bits(dccm_data_ecc_hi_any, 2, 2) @[el2_lib.scala 332:126] - node _T_304 = bits(dccm_rdata_hi_any, 0, 0) @[el2_lib.scala 332:134] - node _T_305 = bits(dccm_data_ecc_hi_any, 1, 0) @[el2_lib.scala 332:145] + node _T_209 = neq(_T_208, UInt<1>("h00")) @[el2_lib.scala 334:44] + node _T_210 = and(is_ldst_hi_any, _T_209) @[el2_lib.scala 334:32] + node _T_211 = bits(_T_208, 6, 6) @[el2_lib.scala 334:64] + node single_ecc_error_hi_any = and(_T_210, _T_211) @[el2_lib.scala 334:53] + node _T_212 = neq(_T_208, UInt<1>("h00")) @[el2_lib.scala 335:44] + node _T_213 = and(is_ldst_hi_any, _T_212) @[el2_lib.scala 335:32] + node _T_214 = bits(_T_208, 6, 6) @[el2_lib.scala 335:65] + node _T_215 = not(_T_214) @[el2_lib.scala 335:55] + node double_ecc_error_hi_any = and(_T_213, _T_215) @[el2_lib.scala 335:53] + wire _T_216 : UInt<1>[39] @[el2_lib.scala 336:26] + node _T_217 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_218 = eq(_T_217, UInt<1>("h01")) @[el2_lib.scala 339:41] + _T_216[0] <= _T_218 @[el2_lib.scala 339:23] + node _T_219 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_220 = eq(_T_219, UInt<2>("h02")) @[el2_lib.scala 339:41] + _T_216[1] <= _T_220 @[el2_lib.scala 339:23] + node _T_221 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_222 = eq(_T_221, UInt<2>("h03")) @[el2_lib.scala 339:41] + _T_216[2] <= _T_222 @[el2_lib.scala 339:23] + node _T_223 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_224 = eq(_T_223, UInt<3>("h04")) @[el2_lib.scala 339:41] + _T_216[3] <= _T_224 @[el2_lib.scala 339:23] + node _T_225 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_226 = eq(_T_225, UInt<3>("h05")) @[el2_lib.scala 339:41] + _T_216[4] <= _T_226 @[el2_lib.scala 339:23] + node _T_227 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_228 = eq(_T_227, UInt<3>("h06")) @[el2_lib.scala 339:41] + _T_216[5] <= _T_228 @[el2_lib.scala 339:23] + node _T_229 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_230 = eq(_T_229, UInt<3>("h07")) @[el2_lib.scala 339:41] + _T_216[6] <= _T_230 @[el2_lib.scala 339:23] + node _T_231 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_232 = eq(_T_231, UInt<4>("h08")) @[el2_lib.scala 339:41] + _T_216[7] <= _T_232 @[el2_lib.scala 339:23] + node _T_233 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_234 = eq(_T_233, UInt<4>("h09")) @[el2_lib.scala 339:41] + _T_216[8] <= _T_234 @[el2_lib.scala 339:23] + node _T_235 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_236 = eq(_T_235, UInt<4>("h0a")) @[el2_lib.scala 339:41] + _T_216[9] <= _T_236 @[el2_lib.scala 339:23] + node _T_237 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_238 = eq(_T_237, UInt<4>("h0b")) @[el2_lib.scala 339:41] + _T_216[10] <= _T_238 @[el2_lib.scala 339:23] + node _T_239 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_240 = eq(_T_239, UInt<4>("h0c")) @[el2_lib.scala 339:41] + _T_216[11] <= _T_240 @[el2_lib.scala 339:23] + node _T_241 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_242 = eq(_T_241, UInt<4>("h0d")) @[el2_lib.scala 339:41] + _T_216[12] <= _T_242 @[el2_lib.scala 339:23] + node _T_243 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_244 = eq(_T_243, UInt<4>("h0e")) @[el2_lib.scala 339:41] + _T_216[13] <= _T_244 @[el2_lib.scala 339:23] + node _T_245 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_246 = eq(_T_245, UInt<4>("h0f")) @[el2_lib.scala 339:41] + _T_216[14] <= _T_246 @[el2_lib.scala 339:23] + node _T_247 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_248 = eq(_T_247, UInt<5>("h010")) @[el2_lib.scala 339:41] + _T_216[15] <= _T_248 @[el2_lib.scala 339:23] + node _T_249 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_250 = eq(_T_249, UInt<5>("h011")) @[el2_lib.scala 339:41] + _T_216[16] <= _T_250 @[el2_lib.scala 339:23] + node _T_251 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_252 = eq(_T_251, UInt<5>("h012")) @[el2_lib.scala 339:41] + _T_216[17] <= _T_252 @[el2_lib.scala 339:23] + node _T_253 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_254 = eq(_T_253, UInt<5>("h013")) @[el2_lib.scala 339:41] + _T_216[18] <= _T_254 @[el2_lib.scala 339:23] + node _T_255 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_256 = eq(_T_255, UInt<5>("h014")) @[el2_lib.scala 339:41] + _T_216[19] <= _T_256 @[el2_lib.scala 339:23] + node _T_257 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_258 = eq(_T_257, UInt<5>("h015")) @[el2_lib.scala 339:41] + _T_216[20] <= _T_258 @[el2_lib.scala 339:23] + node _T_259 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_260 = eq(_T_259, UInt<5>("h016")) @[el2_lib.scala 339:41] + _T_216[21] <= _T_260 @[el2_lib.scala 339:23] + node _T_261 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_262 = eq(_T_261, UInt<5>("h017")) @[el2_lib.scala 339:41] + _T_216[22] <= _T_262 @[el2_lib.scala 339:23] + node _T_263 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_264 = eq(_T_263, UInt<5>("h018")) @[el2_lib.scala 339:41] + _T_216[23] <= _T_264 @[el2_lib.scala 339:23] + node _T_265 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_266 = eq(_T_265, UInt<5>("h019")) @[el2_lib.scala 339:41] + _T_216[24] <= _T_266 @[el2_lib.scala 339:23] + node _T_267 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_268 = eq(_T_267, UInt<5>("h01a")) @[el2_lib.scala 339:41] + _T_216[25] <= _T_268 @[el2_lib.scala 339:23] + node _T_269 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_270 = eq(_T_269, UInt<5>("h01b")) @[el2_lib.scala 339:41] + _T_216[26] <= _T_270 @[el2_lib.scala 339:23] + node _T_271 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_272 = eq(_T_271, UInt<5>("h01c")) @[el2_lib.scala 339:41] + _T_216[27] <= _T_272 @[el2_lib.scala 339:23] + node _T_273 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_274 = eq(_T_273, UInt<5>("h01d")) @[el2_lib.scala 339:41] + _T_216[28] <= _T_274 @[el2_lib.scala 339:23] + node _T_275 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_276 = eq(_T_275, UInt<5>("h01e")) @[el2_lib.scala 339:41] + _T_216[29] <= _T_276 @[el2_lib.scala 339:23] + node _T_277 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_278 = eq(_T_277, UInt<5>("h01f")) @[el2_lib.scala 339:41] + _T_216[30] <= _T_278 @[el2_lib.scala 339:23] + node _T_279 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_280 = eq(_T_279, UInt<6>("h020")) @[el2_lib.scala 339:41] + _T_216[31] <= _T_280 @[el2_lib.scala 339:23] + node _T_281 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_282 = eq(_T_281, UInt<6>("h021")) @[el2_lib.scala 339:41] + _T_216[32] <= _T_282 @[el2_lib.scala 339:23] + node _T_283 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_284 = eq(_T_283, UInt<6>("h022")) @[el2_lib.scala 339:41] + _T_216[33] <= _T_284 @[el2_lib.scala 339:23] + node _T_285 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_286 = eq(_T_285, UInt<6>("h023")) @[el2_lib.scala 339:41] + _T_216[34] <= _T_286 @[el2_lib.scala 339:23] + node _T_287 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_288 = eq(_T_287, UInt<6>("h024")) @[el2_lib.scala 339:41] + _T_216[35] <= _T_288 @[el2_lib.scala 339:23] + node _T_289 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_290 = eq(_T_289, UInt<6>("h025")) @[el2_lib.scala 339:41] + _T_216[36] <= _T_290 @[el2_lib.scala 339:23] + node _T_291 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_292 = eq(_T_291, UInt<6>("h026")) @[el2_lib.scala 339:41] + _T_216[37] <= _T_292 @[el2_lib.scala 339:23] + node _T_293 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_294 = eq(_T_293, UInt<6>("h027")) @[el2_lib.scala 339:41] + _T_216[38] <= _T_294 @[el2_lib.scala 339:23] + node _T_295 = bits(dccm_data_ecc_hi_any, 6, 6) @[el2_lib.scala 341:37] + node _T_296 = bits(dccm_rdata_hi_any, 31, 26) @[el2_lib.scala 341:45] + node _T_297 = bits(dccm_data_ecc_hi_any, 5, 5) @[el2_lib.scala 341:60] + node _T_298 = bits(dccm_rdata_hi_any, 25, 11) @[el2_lib.scala 341:68] + node _T_299 = bits(dccm_data_ecc_hi_any, 4, 4) @[el2_lib.scala 341:83] + node _T_300 = bits(dccm_rdata_hi_any, 10, 4) @[el2_lib.scala 341:91] + node _T_301 = bits(dccm_data_ecc_hi_any, 3, 3) @[el2_lib.scala 341:105] + node _T_302 = bits(dccm_rdata_hi_any, 3, 1) @[el2_lib.scala 341:113] + node _T_303 = bits(dccm_data_ecc_hi_any, 2, 2) @[el2_lib.scala 341:126] + node _T_304 = bits(dccm_rdata_hi_any, 0, 0) @[el2_lib.scala 341:134] + node _T_305 = bits(dccm_data_ecc_hi_any, 1, 0) @[el2_lib.scala 341:145] node _T_306 = cat(_T_304, _T_305) @[Cat.scala 29:58] node _T_307 = cat(_T_301, _T_302) @[Cat.scala 29:58] node _T_308 = cat(_T_307, _T_303) @[Cat.scala 29:58] @@ -544,507 +544,507 @@ circuit el2_lsu_ecc : node _T_313 = cat(_T_312, _T_297) @[Cat.scala 29:58] node _T_314 = cat(_T_313, _T_311) @[Cat.scala 29:58] node _T_315 = cat(_T_314, _T_309) @[Cat.scala 29:58] - node _T_316 = bits(single_ecc_error_hi_any, 0, 0) @[el2_lib.scala 333:49] - node _T_317 = cat(_T_216[1], _T_216[0]) @[el2_lib.scala 333:69] - node _T_318 = cat(_T_216[3], _T_216[2]) @[el2_lib.scala 333:69] - node _T_319 = cat(_T_318, _T_317) @[el2_lib.scala 333:69] - node _T_320 = cat(_T_216[5], _T_216[4]) @[el2_lib.scala 333:69] - node _T_321 = cat(_T_216[8], _T_216[7]) @[el2_lib.scala 333:69] - node _T_322 = cat(_T_321, _T_216[6]) @[el2_lib.scala 333:69] - node _T_323 = cat(_T_322, _T_320) @[el2_lib.scala 333:69] - node _T_324 = cat(_T_323, _T_319) @[el2_lib.scala 333:69] - node _T_325 = cat(_T_216[10], _T_216[9]) @[el2_lib.scala 333:69] - node _T_326 = cat(_T_216[13], _T_216[12]) @[el2_lib.scala 333:69] - node _T_327 = cat(_T_326, _T_216[11]) @[el2_lib.scala 333:69] - node _T_328 = cat(_T_327, _T_325) @[el2_lib.scala 333:69] - node _T_329 = cat(_T_216[15], _T_216[14]) @[el2_lib.scala 333:69] - node _T_330 = cat(_T_216[18], _T_216[17]) @[el2_lib.scala 333:69] - node _T_331 = cat(_T_330, _T_216[16]) @[el2_lib.scala 333:69] - node _T_332 = cat(_T_331, _T_329) @[el2_lib.scala 333:69] - node _T_333 = cat(_T_332, _T_328) @[el2_lib.scala 333:69] - node _T_334 = cat(_T_333, _T_324) @[el2_lib.scala 333:69] - node _T_335 = cat(_T_216[20], _T_216[19]) @[el2_lib.scala 333:69] - node _T_336 = cat(_T_216[23], _T_216[22]) @[el2_lib.scala 333:69] - node _T_337 = cat(_T_336, _T_216[21]) @[el2_lib.scala 333:69] - node _T_338 = cat(_T_337, _T_335) @[el2_lib.scala 333:69] - node _T_339 = cat(_T_216[25], _T_216[24]) @[el2_lib.scala 333:69] - node _T_340 = cat(_T_216[28], _T_216[27]) @[el2_lib.scala 333:69] - node _T_341 = cat(_T_340, _T_216[26]) @[el2_lib.scala 333:69] - node _T_342 = cat(_T_341, _T_339) @[el2_lib.scala 333:69] - node _T_343 = cat(_T_342, _T_338) @[el2_lib.scala 333:69] - node _T_344 = cat(_T_216[30], _T_216[29]) @[el2_lib.scala 333:69] - node _T_345 = cat(_T_216[33], _T_216[32]) @[el2_lib.scala 333:69] - node _T_346 = cat(_T_345, _T_216[31]) @[el2_lib.scala 333:69] - node _T_347 = cat(_T_346, _T_344) @[el2_lib.scala 333:69] - node _T_348 = cat(_T_216[35], _T_216[34]) @[el2_lib.scala 333:69] - node _T_349 = cat(_T_216[38], _T_216[37]) @[el2_lib.scala 333:69] - node _T_350 = cat(_T_349, _T_216[36]) @[el2_lib.scala 333:69] - node _T_351 = cat(_T_350, _T_348) @[el2_lib.scala 333:69] - node _T_352 = cat(_T_351, _T_347) @[el2_lib.scala 333:69] - node _T_353 = cat(_T_352, _T_343) @[el2_lib.scala 333:69] - node _T_354 = cat(_T_353, _T_334) @[el2_lib.scala 333:69] - node _T_355 = xor(_T_354, _T_315) @[el2_lib.scala 333:76] - node _T_356 = mux(_T_316, _T_355, _T_315) @[el2_lib.scala 333:31] - node _T_357 = bits(_T_356, 37, 32) @[el2_lib.scala 335:37] - node _T_358 = bits(_T_356, 30, 16) @[el2_lib.scala 335:61] - node _T_359 = bits(_T_356, 14, 8) @[el2_lib.scala 335:86] - node _T_360 = bits(_T_356, 6, 4) @[el2_lib.scala 335:110] - node _T_361 = bits(_T_356, 2, 2) @[el2_lib.scala 335:133] + node _T_316 = bits(single_ecc_error_hi_any, 0, 0) @[el2_lib.scala 342:49] + node _T_317 = cat(_T_216[1], _T_216[0]) @[el2_lib.scala 342:69] + node _T_318 = cat(_T_216[3], _T_216[2]) @[el2_lib.scala 342:69] + node _T_319 = cat(_T_318, _T_317) @[el2_lib.scala 342:69] + node _T_320 = cat(_T_216[5], _T_216[4]) @[el2_lib.scala 342:69] + node _T_321 = cat(_T_216[8], _T_216[7]) @[el2_lib.scala 342:69] + node _T_322 = cat(_T_321, _T_216[6]) @[el2_lib.scala 342:69] + node _T_323 = cat(_T_322, _T_320) @[el2_lib.scala 342:69] + node _T_324 = cat(_T_323, _T_319) @[el2_lib.scala 342:69] + node _T_325 = cat(_T_216[10], _T_216[9]) @[el2_lib.scala 342:69] + node _T_326 = cat(_T_216[13], _T_216[12]) @[el2_lib.scala 342:69] + node _T_327 = cat(_T_326, _T_216[11]) @[el2_lib.scala 342:69] + node _T_328 = cat(_T_327, _T_325) @[el2_lib.scala 342:69] + node _T_329 = cat(_T_216[15], _T_216[14]) @[el2_lib.scala 342:69] + node _T_330 = cat(_T_216[18], _T_216[17]) @[el2_lib.scala 342:69] + node _T_331 = cat(_T_330, _T_216[16]) @[el2_lib.scala 342:69] + node _T_332 = cat(_T_331, _T_329) @[el2_lib.scala 342:69] + node _T_333 = cat(_T_332, _T_328) @[el2_lib.scala 342:69] + node _T_334 = cat(_T_333, _T_324) @[el2_lib.scala 342:69] + node _T_335 = cat(_T_216[20], _T_216[19]) @[el2_lib.scala 342:69] + node _T_336 = cat(_T_216[23], _T_216[22]) @[el2_lib.scala 342:69] + node _T_337 = cat(_T_336, _T_216[21]) @[el2_lib.scala 342:69] + node _T_338 = cat(_T_337, _T_335) @[el2_lib.scala 342:69] + node _T_339 = cat(_T_216[25], _T_216[24]) @[el2_lib.scala 342:69] + node _T_340 = cat(_T_216[28], _T_216[27]) @[el2_lib.scala 342:69] + node _T_341 = cat(_T_340, _T_216[26]) @[el2_lib.scala 342:69] + node _T_342 = cat(_T_341, _T_339) @[el2_lib.scala 342:69] + node _T_343 = cat(_T_342, _T_338) @[el2_lib.scala 342:69] + node _T_344 = cat(_T_216[30], _T_216[29]) @[el2_lib.scala 342:69] + node _T_345 = cat(_T_216[33], _T_216[32]) @[el2_lib.scala 342:69] + node _T_346 = cat(_T_345, _T_216[31]) @[el2_lib.scala 342:69] + node _T_347 = cat(_T_346, _T_344) @[el2_lib.scala 342:69] + node _T_348 = cat(_T_216[35], _T_216[34]) @[el2_lib.scala 342:69] + node _T_349 = cat(_T_216[38], _T_216[37]) @[el2_lib.scala 342:69] + node _T_350 = cat(_T_349, _T_216[36]) @[el2_lib.scala 342:69] + node _T_351 = cat(_T_350, _T_348) @[el2_lib.scala 342:69] + node _T_352 = cat(_T_351, _T_347) @[el2_lib.scala 342:69] + node _T_353 = cat(_T_352, _T_343) @[el2_lib.scala 342:69] + node _T_354 = cat(_T_353, _T_334) @[el2_lib.scala 342:69] + node _T_355 = xor(_T_354, _T_315) @[el2_lib.scala 342:76] + node _T_356 = mux(_T_316, _T_355, _T_315) @[el2_lib.scala 342:31] + node _T_357 = bits(_T_356, 37, 32) @[el2_lib.scala 344:37] + node _T_358 = bits(_T_356, 30, 16) @[el2_lib.scala 344:61] + node _T_359 = bits(_T_356, 14, 8) @[el2_lib.scala 344:86] + node _T_360 = bits(_T_356, 6, 4) @[el2_lib.scala 344:110] + node _T_361 = bits(_T_356, 2, 2) @[el2_lib.scala 344:133] node _T_362 = cat(_T_360, _T_361) @[Cat.scala 29:58] node _T_363 = cat(_T_357, _T_358) @[Cat.scala 29:58] node _T_364 = cat(_T_363, _T_359) @[Cat.scala 29:58] node sec_data_hi_any = cat(_T_364, _T_362) @[Cat.scala 29:58] - node _T_365 = bits(_T_356, 38, 38) @[el2_lib.scala 336:39] - node _T_366 = bits(_T_208, 6, 0) @[el2_lib.scala 336:56] - node _T_367 = eq(_T_366, UInt<7>("h040")) @[el2_lib.scala 336:62] - node _T_368 = xor(_T_365, _T_367) @[el2_lib.scala 336:44] - node _T_369 = bits(_T_356, 31, 31) @[el2_lib.scala 336:102] - node _T_370 = bits(_T_356, 15, 15) @[el2_lib.scala 336:124] - node _T_371 = bits(_T_356, 7, 7) @[el2_lib.scala 336:146] - node _T_372 = bits(_T_356, 3, 3) @[el2_lib.scala 336:167] - node _T_373 = bits(_T_356, 1, 0) @[el2_lib.scala 336:188] + node _T_365 = bits(_T_356, 38, 38) @[el2_lib.scala 345:39] + node _T_366 = bits(_T_208, 6, 0) @[el2_lib.scala 345:56] + node _T_367 = eq(_T_366, UInt<7>("h040")) @[el2_lib.scala 345:62] + node _T_368 = xor(_T_365, _T_367) @[el2_lib.scala 345:44] + node _T_369 = bits(_T_356, 31, 31) @[el2_lib.scala 345:102] + node _T_370 = bits(_T_356, 15, 15) @[el2_lib.scala 345:124] + node _T_371 = bits(_T_356, 7, 7) @[el2_lib.scala 345:146] + node _T_372 = bits(_T_356, 3, 3) @[el2_lib.scala 345:167] + node _T_373 = bits(_T_356, 1, 0) @[el2_lib.scala 345:188] node _T_374 = cat(_T_371, _T_372) @[Cat.scala 29:58] node _T_375 = cat(_T_374, _T_373) @[Cat.scala 29:58] node _T_376 = cat(_T_368, _T_369) @[Cat.scala 29:58] node _T_377 = cat(_T_376, _T_370) @[Cat.scala 29:58] node ecc_out_hi_nc = cat(_T_377, _T_375) @[Cat.scala 29:58] - wire _T_378 : UInt<1>[18] @[el2_lib.scala 304:18] - wire _T_379 : UInt<1>[18] @[el2_lib.scala 305:18] - wire _T_380 : UInt<1>[18] @[el2_lib.scala 306:18] - wire _T_381 : UInt<1>[15] @[el2_lib.scala 307:18] - wire _T_382 : UInt<1>[15] @[el2_lib.scala 308:18] - wire _T_383 : UInt<1>[6] @[el2_lib.scala 309:18] - node _T_384 = bits(dccm_rdata_lo_any, 0, 0) @[el2_lib.scala 316:36] - _T_378[0] <= _T_384 @[el2_lib.scala 316:30] - node _T_385 = bits(dccm_rdata_lo_any, 0, 0) @[el2_lib.scala 317:36] - _T_379[0] <= _T_385 @[el2_lib.scala 317:30] - node _T_386 = bits(dccm_rdata_lo_any, 1, 1) @[el2_lib.scala 316:36] - _T_378[1] <= _T_386 @[el2_lib.scala 316:30] - node _T_387 = bits(dccm_rdata_lo_any, 1, 1) @[el2_lib.scala 318:36] - _T_380[0] <= _T_387 @[el2_lib.scala 318:30] - node _T_388 = bits(dccm_rdata_lo_any, 2, 2) @[el2_lib.scala 317:36] - _T_379[1] <= _T_388 @[el2_lib.scala 317:30] - node _T_389 = bits(dccm_rdata_lo_any, 2, 2) @[el2_lib.scala 318:36] - _T_380[1] <= _T_389 @[el2_lib.scala 318:30] - node _T_390 = bits(dccm_rdata_lo_any, 3, 3) @[el2_lib.scala 316:36] - _T_378[2] <= _T_390 @[el2_lib.scala 316:30] - node _T_391 = bits(dccm_rdata_lo_any, 3, 3) @[el2_lib.scala 317:36] - _T_379[2] <= _T_391 @[el2_lib.scala 317:30] - node _T_392 = bits(dccm_rdata_lo_any, 3, 3) @[el2_lib.scala 318:36] - _T_380[2] <= _T_392 @[el2_lib.scala 318:30] - node _T_393 = bits(dccm_rdata_lo_any, 4, 4) @[el2_lib.scala 316:36] - _T_378[3] <= _T_393 @[el2_lib.scala 316:30] - node _T_394 = bits(dccm_rdata_lo_any, 4, 4) @[el2_lib.scala 319:36] - _T_381[0] <= _T_394 @[el2_lib.scala 319:30] - node _T_395 = bits(dccm_rdata_lo_any, 5, 5) @[el2_lib.scala 317:36] - _T_379[3] <= _T_395 @[el2_lib.scala 317:30] - node _T_396 = bits(dccm_rdata_lo_any, 5, 5) @[el2_lib.scala 319:36] - _T_381[1] <= _T_396 @[el2_lib.scala 319:30] - node _T_397 = bits(dccm_rdata_lo_any, 6, 6) @[el2_lib.scala 316:36] - _T_378[4] <= _T_397 @[el2_lib.scala 316:30] - node _T_398 = bits(dccm_rdata_lo_any, 6, 6) @[el2_lib.scala 317:36] - _T_379[4] <= _T_398 @[el2_lib.scala 317:30] - node _T_399 = bits(dccm_rdata_lo_any, 6, 6) @[el2_lib.scala 319:36] - _T_381[2] <= _T_399 @[el2_lib.scala 319:30] - node _T_400 = bits(dccm_rdata_lo_any, 7, 7) @[el2_lib.scala 318:36] - _T_380[3] <= _T_400 @[el2_lib.scala 318:30] - node _T_401 = bits(dccm_rdata_lo_any, 7, 7) @[el2_lib.scala 319:36] - _T_381[3] <= _T_401 @[el2_lib.scala 319:30] - node _T_402 = bits(dccm_rdata_lo_any, 8, 8) @[el2_lib.scala 316:36] - _T_378[5] <= _T_402 @[el2_lib.scala 316:30] - node _T_403 = bits(dccm_rdata_lo_any, 8, 8) @[el2_lib.scala 318:36] - _T_380[4] <= _T_403 @[el2_lib.scala 318:30] - node _T_404 = bits(dccm_rdata_lo_any, 8, 8) @[el2_lib.scala 319:36] - _T_381[4] <= _T_404 @[el2_lib.scala 319:30] - node _T_405 = bits(dccm_rdata_lo_any, 9, 9) @[el2_lib.scala 317:36] - _T_379[5] <= _T_405 @[el2_lib.scala 317:30] - node _T_406 = bits(dccm_rdata_lo_any, 9, 9) @[el2_lib.scala 318:36] - _T_380[5] <= _T_406 @[el2_lib.scala 318:30] - node _T_407 = bits(dccm_rdata_lo_any, 9, 9) @[el2_lib.scala 319:36] - _T_381[5] <= _T_407 @[el2_lib.scala 319:30] - node _T_408 = bits(dccm_rdata_lo_any, 10, 10) @[el2_lib.scala 316:36] - _T_378[6] <= _T_408 @[el2_lib.scala 316:30] - node _T_409 = bits(dccm_rdata_lo_any, 10, 10) @[el2_lib.scala 317:36] - _T_379[6] <= _T_409 @[el2_lib.scala 317:30] - node _T_410 = bits(dccm_rdata_lo_any, 10, 10) @[el2_lib.scala 318:36] - _T_380[6] <= _T_410 @[el2_lib.scala 318:30] - node _T_411 = bits(dccm_rdata_lo_any, 10, 10) @[el2_lib.scala 319:36] - _T_381[6] <= _T_411 @[el2_lib.scala 319:30] - node _T_412 = bits(dccm_rdata_lo_any, 11, 11) @[el2_lib.scala 316:36] - _T_378[7] <= _T_412 @[el2_lib.scala 316:30] - node _T_413 = bits(dccm_rdata_lo_any, 11, 11) @[el2_lib.scala 320:36] - _T_382[0] <= _T_413 @[el2_lib.scala 320:30] - node _T_414 = bits(dccm_rdata_lo_any, 12, 12) @[el2_lib.scala 317:36] - _T_379[7] <= _T_414 @[el2_lib.scala 317:30] - node _T_415 = bits(dccm_rdata_lo_any, 12, 12) @[el2_lib.scala 320:36] - _T_382[1] <= _T_415 @[el2_lib.scala 320:30] - node _T_416 = bits(dccm_rdata_lo_any, 13, 13) @[el2_lib.scala 316:36] - _T_378[8] <= _T_416 @[el2_lib.scala 316:30] - node _T_417 = bits(dccm_rdata_lo_any, 13, 13) @[el2_lib.scala 317:36] - _T_379[8] <= _T_417 @[el2_lib.scala 317:30] - node _T_418 = bits(dccm_rdata_lo_any, 13, 13) @[el2_lib.scala 320:36] - _T_382[2] <= _T_418 @[el2_lib.scala 320:30] - node _T_419 = bits(dccm_rdata_lo_any, 14, 14) @[el2_lib.scala 318:36] - _T_380[7] <= _T_419 @[el2_lib.scala 318:30] - node _T_420 = bits(dccm_rdata_lo_any, 14, 14) @[el2_lib.scala 320:36] - _T_382[3] <= _T_420 @[el2_lib.scala 320:30] - node _T_421 = bits(dccm_rdata_lo_any, 15, 15) @[el2_lib.scala 316:36] - _T_378[9] <= _T_421 @[el2_lib.scala 316:30] - node _T_422 = bits(dccm_rdata_lo_any, 15, 15) @[el2_lib.scala 318:36] - _T_380[8] <= _T_422 @[el2_lib.scala 318:30] - node _T_423 = bits(dccm_rdata_lo_any, 15, 15) @[el2_lib.scala 320:36] - _T_382[4] <= _T_423 @[el2_lib.scala 320:30] - node _T_424 = bits(dccm_rdata_lo_any, 16, 16) @[el2_lib.scala 317:36] - _T_379[9] <= _T_424 @[el2_lib.scala 317:30] - node _T_425 = bits(dccm_rdata_lo_any, 16, 16) @[el2_lib.scala 318:36] - _T_380[9] <= _T_425 @[el2_lib.scala 318:30] - node _T_426 = bits(dccm_rdata_lo_any, 16, 16) @[el2_lib.scala 320:36] - _T_382[5] <= _T_426 @[el2_lib.scala 320:30] - node _T_427 = bits(dccm_rdata_lo_any, 17, 17) @[el2_lib.scala 316:36] - _T_378[10] <= _T_427 @[el2_lib.scala 316:30] - node _T_428 = bits(dccm_rdata_lo_any, 17, 17) @[el2_lib.scala 317:36] - _T_379[10] <= _T_428 @[el2_lib.scala 317:30] - node _T_429 = bits(dccm_rdata_lo_any, 17, 17) @[el2_lib.scala 318:36] - _T_380[10] <= _T_429 @[el2_lib.scala 318:30] - node _T_430 = bits(dccm_rdata_lo_any, 17, 17) @[el2_lib.scala 320:36] - _T_382[6] <= _T_430 @[el2_lib.scala 320:30] - node _T_431 = bits(dccm_rdata_lo_any, 18, 18) @[el2_lib.scala 319:36] - _T_381[7] <= _T_431 @[el2_lib.scala 319:30] - node _T_432 = bits(dccm_rdata_lo_any, 18, 18) @[el2_lib.scala 320:36] - _T_382[7] <= _T_432 @[el2_lib.scala 320:30] - node _T_433 = bits(dccm_rdata_lo_any, 19, 19) @[el2_lib.scala 316:36] - _T_378[11] <= _T_433 @[el2_lib.scala 316:30] - node _T_434 = bits(dccm_rdata_lo_any, 19, 19) @[el2_lib.scala 319:36] - _T_381[8] <= _T_434 @[el2_lib.scala 319:30] - node _T_435 = bits(dccm_rdata_lo_any, 19, 19) @[el2_lib.scala 320:36] - _T_382[8] <= _T_435 @[el2_lib.scala 320:30] - node _T_436 = bits(dccm_rdata_lo_any, 20, 20) @[el2_lib.scala 317:36] - _T_379[11] <= _T_436 @[el2_lib.scala 317:30] - node _T_437 = bits(dccm_rdata_lo_any, 20, 20) @[el2_lib.scala 319:36] - _T_381[9] <= _T_437 @[el2_lib.scala 319:30] - node _T_438 = bits(dccm_rdata_lo_any, 20, 20) @[el2_lib.scala 320:36] - _T_382[9] <= _T_438 @[el2_lib.scala 320:30] - node _T_439 = bits(dccm_rdata_lo_any, 21, 21) @[el2_lib.scala 316:36] - _T_378[12] <= _T_439 @[el2_lib.scala 316:30] - node _T_440 = bits(dccm_rdata_lo_any, 21, 21) @[el2_lib.scala 317:36] - _T_379[12] <= _T_440 @[el2_lib.scala 317:30] - node _T_441 = bits(dccm_rdata_lo_any, 21, 21) @[el2_lib.scala 319:36] - _T_381[10] <= _T_441 @[el2_lib.scala 319:30] - node _T_442 = bits(dccm_rdata_lo_any, 21, 21) @[el2_lib.scala 320:36] - _T_382[10] <= _T_442 @[el2_lib.scala 320:30] - node _T_443 = bits(dccm_rdata_lo_any, 22, 22) @[el2_lib.scala 318:36] - _T_380[11] <= _T_443 @[el2_lib.scala 318:30] - node _T_444 = bits(dccm_rdata_lo_any, 22, 22) @[el2_lib.scala 319:36] - _T_381[11] <= _T_444 @[el2_lib.scala 319:30] - node _T_445 = bits(dccm_rdata_lo_any, 22, 22) @[el2_lib.scala 320:36] - _T_382[11] <= _T_445 @[el2_lib.scala 320:30] - node _T_446 = bits(dccm_rdata_lo_any, 23, 23) @[el2_lib.scala 316:36] - _T_378[13] <= _T_446 @[el2_lib.scala 316:30] - node _T_447 = bits(dccm_rdata_lo_any, 23, 23) @[el2_lib.scala 318:36] - _T_380[12] <= _T_447 @[el2_lib.scala 318:30] - node _T_448 = bits(dccm_rdata_lo_any, 23, 23) @[el2_lib.scala 319:36] - _T_381[12] <= _T_448 @[el2_lib.scala 319:30] - node _T_449 = bits(dccm_rdata_lo_any, 23, 23) @[el2_lib.scala 320:36] - _T_382[12] <= _T_449 @[el2_lib.scala 320:30] - node _T_450 = bits(dccm_rdata_lo_any, 24, 24) @[el2_lib.scala 317:36] - _T_379[13] <= _T_450 @[el2_lib.scala 317:30] - node _T_451 = bits(dccm_rdata_lo_any, 24, 24) @[el2_lib.scala 318:36] - _T_380[13] <= _T_451 @[el2_lib.scala 318:30] - node _T_452 = bits(dccm_rdata_lo_any, 24, 24) @[el2_lib.scala 319:36] - _T_381[13] <= _T_452 @[el2_lib.scala 319:30] - node _T_453 = bits(dccm_rdata_lo_any, 24, 24) @[el2_lib.scala 320:36] - _T_382[13] <= _T_453 @[el2_lib.scala 320:30] - node _T_454 = bits(dccm_rdata_lo_any, 25, 25) @[el2_lib.scala 316:36] - _T_378[14] <= _T_454 @[el2_lib.scala 316:30] - node _T_455 = bits(dccm_rdata_lo_any, 25, 25) @[el2_lib.scala 317:36] - _T_379[14] <= _T_455 @[el2_lib.scala 317:30] - node _T_456 = bits(dccm_rdata_lo_any, 25, 25) @[el2_lib.scala 318:36] - _T_380[14] <= _T_456 @[el2_lib.scala 318:30] - node _T_457 = bits(dccm_rdata_lo_any, 25, 25) @[el2_lib.scala 319:36] - _T_381[14] <= _T_457 @[el2_lib.scala 319:30] - node _T_458 = bits(dccm_rdata_lo_any, 25, 25) @[el2_lib.scala 320:36] - _T_382[14] <= _T_458 @[el2_lib.scala 320:30] - node _T_459 = bits(dccm_rdata_lo_any, 26, 26) @[el2_lib.scala 316:36] - _T_378[15] <= _T_459 @[el2_lib.scala 316:30] - node _T_460 = bits(dccm_rdata_lo_any, 26, 26) @[el2_lib.scala 321:36] - _T_383[0] <= _T_460 @[el2_lib.scala 321:30] - node _T_461 = bits(dccm_rdata_lo_any, 27, 27) @[el2_lib.scala 317:36] - _T_379[15] <= _T_461 @[el2_lib.scala 317:30] - node _T_462 = bits(dccm_rdata_lo_any, 27, 27) @[el2_lib.scala 321:36] - _T_383[1] <= _T_462 @[el2_lib.scala 321:30] - node _T_463 = bits(dccm_rdata_lo_any, 28, 28) @[el2_lib.scala 316:36] - _T_378[16] <= _T_463 @[el2_lib.scala 316:30] - node _T_464 = bits(dccm_rdata_lo_any, 28, 28) @[el2_lib.scala 317:36] - _T_379[16] <= _T_464 @[el2_lib.scala 317:30] - node _T_465 = bits(dccm_rdata_lo_any, 28, 28) @[el2_lib.scala 321:36] - _T_383[2] <= _T_465 @[el2_lib.scala 321:30] - node _T_466 = bits(dccm_rdata_lo_any, 29, 29) @[el2_lib.scala 318:36] - _T_380[15] <= _T_466 @[el2_lib.scala 318:30] - node _T_467 = bits(dccm_rdata_lo_any, 29, 29) @[el2_lib.scala 321:36] - _T_383[3] <= _T_467 @[el2_lib.scala 321:30] - node _T_468 = bits(dccm_rdata_lo_any, 30, 30) @[el2_lib.scala 316:36] - _T_378[17] <= _T_468 @[el2_lib.scala 316:30] - node _T_469 = bits(dccm_rdata_lo_any, 30, 30) @[el2_lib.scala 318:36] - _T_380[16] <= _T_469 @[el2_lib.scala 318:30] - node _T_470 = bits(dccm_rdata_lo_any, 30, 30) @[el2_lib.scala 321:36] - _T_383[4] <= _T_470 @[el2_lib.scala 321:30] - node _T_471 = bits(dccm_rdata_lo_any, 31, 31) @[el2_lib.scala 317:36] - _T_379[17] <= _T_471 @[el2_lib.scala 317:30] - node _T_472 = bits(dccm_rdata_lo_any, 31, 31) @[el2_lib.scala 318:36] - _T_380[17] <= _T_472 @[el2_lib.scala 318:30] - node _T_473 = bits(dccm_rdata_lo_any, 31, 31) @[el2_lib.scala 321:36] - _T_383[5] <= _T_473 @[el2_lib.scala 321:30] - node _T_474 = xorr(dccm_rdata_lo_any) @[el2_lib.scala 324:30] - node _T_475 = xorr(dccm_data_ecc_lo_any) @[el2_lib.scala 324:44] - node _T_476 = xor(_T_474, _T_475) @[el2_lib.scala 324:35] - node _T_477 = not(UInt<1>("h00")) @[el2_lib.scala 324:52] - node _T_478 = and(_T_476, _T_477) @[el2_lib.scala 324:50] - node _T_479 = bits(dccm_data_ecc_lo_any, 5, 5) @[el2_lib.scala 324:68] - node _T_480 = cat(_T_383[2], _T_383[1]) @[el2_lib.scala 324:76] - node _T_481 = cat(_T_480, _T_383[0]) @[el2_lib.scala 324:76] - node _T_482 = cat(_T_383[5], _T_383[4]) @[el2_lib.scala 324:76] - node _T_483 = cat(_T_482, _T_383[3]) @[el2_lib.scala 324:76] - node _T_484 = cat(_T_483, _T_481) @[el2_lib.scala 324:76] - node _T_485 = xorr(_T_484) @[el2_lib.scala 324:83] - node _T_486 = xor(_T_479, _T_485) @[el2_lib.scala 324:71] - node _T_487 = bits(dccm_data_ecc_lo_any, 4, 4) @[el2_lib.scala 324:95] - node _T_488 = cat(_T_382[2], _T_382[1]) @[el2_lib.scala 324:103] - node _T_489 = cat(_T_488, _T_382[0]) @[el2_lib.scala 324:103] - node _T_490 = cat(_T_382[4], _T_382[3]) @[el2_lib.scala 324:103] - node _T_491 = cat(_T_382[6], _T_382[5]) @[el2_lib.scala 324:103] - node _T_492 = cat(_T_491, _T_490) @[el2_lib.scala 324:103] - node _T_493 = cat(_T_492, _T_489) @[el2_lib.scala 324:103] - node _T_494 = cat(_T_382[8], _T_382[7]) @[el2_lib.scala 324:103] - node _T_495 = cat(_T_382[10], _T_382[9]) @[el2_lib.scala 324:103] - node _T_496 = cat(_T_495, _T_494) @[el2_lib.scala 324:103] - node _T_497 = cat(_T_382[12], _T_382[11]) @[el2_lib.scala 324:103] - node _T_498 = cat(_T_382[14], _T_382[13]) @[el2_lib.scala 324:103] - node _T_499 = cat(_T_498, _T_497) @[el2_lib.scala 324:103] - node _T_500 = cat(_T_499, _T_496) @[el2_lib.scala 324:103] - node _T_501 = cat(_T_500, _T_493) @[el2_lib.scala 324:103] - node _T_502 = xorr(_T_501) @[el2_lib.scala 324:110] - node _T_503 = xor(_T_487, _T_502) @[el2_lib.scala 324:98] - node _T_504 = bits(dccm_data_ecc_lo_any, 3, 3) @[el2_lib.scala 324:122] - node _T_505 = cat(_T_381[2], _T_381[1]) @[el2_lib.scala 324:130] - node _T_506 = cat(_T_505, _T_381[0]) @[el2_lib.scala 324:130] - node _T_507 = cat(_T_381[4], _T_381[3]) @[el2_lib.scala 324:130] - node _T_508 = cat(_T_381[6], _T_381[5]) @[el2_lib.scala 324:130] - node _T_509 = cat(_T_508, _T_507) @[el2_lib.scala 324:130] - node _T_510 = cat(_T_509, _T_506) @[el2_lib.scala 324:130] - node _T_511 = cat(_T_381[8], _T_381[7]) @[el2_lib.scala 324:130] - node _T_512 = cat(_T_381[10], _T_381[9]) @[el2_lib.scala 324:130] - node _T_513 = cat(_T_512, _T_511) @[el2_lib.scala 324:130] - node _T_514 = cat(_T_381[12], _T_381[11]) @[el2_lib.scala 324:130] - node _T_515 = cat(_T_381[14], _T_381[13]) @[el2_lib.scala 324:130] - node _T_516 = cat(_T_515, _T_514) @[el2_lib.scala 324:130] - node _T_517 = cat(_T_516, _T_513) @[el2_lib.scala 324:130] - node _T_518 = cat(_T_517, _T_510) @[el2_lib.scala 324:130] - node _T_519 = xorr(_T_518) @[el2_lib.scala 324:137] - node _T_520 = xor(_T_504, _T_519) @[el2_lib.scala 324:125] - node _T_521 = bits(dccm_data_ecc_lo_any, 2, 2) @[el2_lib.scala 324:149] - node _T_522 = cat(_T_380[1], _T_380[0]) @[el2_lib.scala 324:157] - node _T_523 = cat(_T_380[3], _T_380[2]) @[el2_lib.scala 324:157] - node _T_524 = cat(_T_523, _T_522) @[el2_lib.scala 324:157] - node _T_525 = cat(_T_380[5], _T_380[4]) @[el2_lib.scala 324:157] - node _T_526 = cat(_T_380[8], _T_380[7]) @[el2_lib.scala 324:157] - node _T_527 = cat(_T_526, _T_380[6]) @[el2_lib.scala 324:157] - node _T_528 = cat(_T_527, _T_525) @[el2_lib.scala 324:157] - node _T_529 = cat(_T_528, _T_524) @[el2_lib.scala 324:157] - node _T_530 = cat(_T_380[10], _T_380[9]) @[el2_lib.scala 324:157] - node _T_531 = cat(_T_380[12], _T_380[11]) @[el2_lib.scala 324:157] - node _T_532 = cat(_T_531, _T_530) @[el2_lib.scala 324:157] - node _T_533 = cat(_T_380[14], _T_380[13]) @[el2_lib.scala 324:157] - node _T_534 = cat(_T_380[17], _T_380[16]) @[el2_lib.scala 324:157] - node _T_535 = cat(_T_534, _T_380[15]) @[el2_lib.scala 324:157] - node _T_536 = cat(_T_535, _T_533) @[el2_lib.scala 324:157] - node _T_537 = cat(_T_536, _T_532) @[el2_lib.scala 324:157] - node _T_538 = cat(_T_537, _T_529) @[el2_lib.scala 324:157] - node _T_539 = xorr(_T_538) @[el2_lib.scala 324:164] - node _T_540 = xor(_T_521, _T_539) @[el2_lib.scala 324:152] - node _T_541 = bits(dccm_data_ecc_lo_any, 1, 1) @[el2_lib.scala 324:176] - node _T_542 = cat(_T_379[1], _T_379[0]) @[el2_lib.scala 324:184] - node _T_543 = cat(_T_379[3], _T_379[2]) @[el2_lib.scala 324:184] - node _T_544 = cat(_T_543, _T_542) @[el2_lib.scala 324:184] - node _T_545 = cat(_T_379[5], _T_379[4]) @[el2_lib.scala 324:184] - node _T_546 = cat(_T_379[8], _T_379[7]) @[el2_lib.scala 324:184] - node _T_547 = cat(_T_546, _T_379[6]) @[el2_lib.scala 324:184] - node _T_548 = cat(_T_547, _T_545) @[el2_lib.scala 324:184] - node _T_549 = cat(_T_548, _T_544) @[el2_lib.scala 324:184] - node _T_550 = cat(_T_379[10], _T_379[9]) @[el2_lib.scala 324:184] - node _T_551 = cat(_T_379[12], _T_379[11]) @[el2_lib.scala 324:184] - node _T_552 = cat(_T_551, _T_550) @[el2_lib.scala 324:184] - node _T_553 = cat(_T_379[14], _T_379[13]) @[el2_lib.scala 324:184] - node _T_554 = cat(_T_379[17], _T_379[16]) @[el2_lib.scala 324:184] - node _T_555 = cat(_T_554, _T_379[15]) @[el2_lib.scala 324:184] - node _T_556 = cat(_T_555, _T_553) @[el2_lib.scala 324:184] - node _T_557 = cat(_T_556, _T_552) @[el2_lib.scala 324:184] - node _T_558 = cat(_T_557, _T_549) @[el2_lib.scala 324:184] - node _T_559 = xorr(_T_558) @[el2_lib.scala 324:191] - node _T_560 = xor(_T_541, _T_559) @[el2_lib.scala 324:179] - node _T_561 = bits(dccm_data_ecc_lo_any, 0, 0) @[el2_lib.scala 324:203] - node _T_562 = cat(_T_378[1], _T_378[0]) @[el2_lib.scala 324:211] - node _T_563 = cat(_T_378[3], _T_378[2]) @[el2_lib.scala 324:211] - node _T_564 = cat(_T_563, _T_562) @[el2_lib.scala 324:211] - node _T_565 = cat(_T_378[5], _T_378[4]) @[el2_lib.scala 324:211] - node _T_566 = cat(_T_378[8], _T_378[7]) @[el2_lib.scala 324:211] - node _T_567 = cat(_T_566, _T_378[6]) @[el2_lib.scala 324:211] - node _T_568 = cat(_T_567, _T_565) @[el2_lib.scala 324:211] - node _T_569 = cat(_T_568, _T_564) @[el2_lib.scala 324:211] - node _T_570 = cat(_T_378[10], _T_378[9]) @[el2_lib.scala 324:211] - node _T_571 = cat(_T_378[12], _T_378[11]) @[el2_lib.scala 324:211] - node _T_572 = cat(_T_571, _T_570) @[el2_lib.scala 324:211] - node _T_573 = cat(_T_378[14], _T_378[13]) @[el2_lib.scala 324:211] - node _T_574 = cat(_T_378[17], _T_378[16]) @[el2_lib.scala 324:211] - node _T_575 = cat(_T_574, _T_378[15]) @[el2_lib.scala 324:211] - node _T_576 = cat(_T_575, _T_573) @[el2_lib.scala 324:211] - node _T_577 = cat(_T_576, _T_572) @[el2_lib.scala 324:211] - node _T_578 = cat(_T_577, _T_569) @[el2_lib.scala 324:211] - node _T_579 = xorr(_T_578) @[el2_lib.scala 324:218] - node _T_580 = xor(_T_561, _T_579) @[el2_lib.scala 324:206] + wire _T_378 : UInt<1>[18] @[el2_lib.scala 313:18] + wire _T_379 : UInt<1>[18] @[el2_lib.scala 314:18] + wire _T_380 : UInt<1>[18] @[el2_lib.scala 315:18] + wire _T_381 : UInt<1>[15] @[el2_lib.scala 316:18] + wire _T_382 : UInt<1>[15] @[el2_lib.scala 317:18] + wire _T_383 : UInt<1>[6] @[el2_lib.scala 318:18] + node _T_384 = bits(dccm_rdata_lo_any, 0, 0) @[el2_lib.scala 325:36] + _T_378[0] <= _T_384 @[el2_lib.scala 325:30] + node _T_385 = bits(dccm_rdata_lo_any, 0, 0) @[el2_lib.scala 326:36] + _T_379[0] <= _T_385 @[el2_lib.scala 326:30] + node _T_386 = bits(dccm_rdata_lo_any, 1, 1) @[el2_lib.scala 325:36] + _T_378[1] <= _T_386 @[el2_lib.scala 325:30] + node _T_387 = bits(dccm_rdata_lo_any, 1, 1) @[el2_lib.scala 327:36] + _T_380[0] <= _T_387 @[el2_lib.scala 327:30] + node _T_388 = bits(dccm_rdata_lo_any, 2, 2) @[el2_lib.scala 326:36] + _T_379[1] <= _T_388 @[el2_lib.scala 326:30] + node _T_389 = bits(dccm_rdata_lo_any, 2, 2) @[el2_lib.scala 327:36] + _T_380[1] <= _T_389 @[el2_lib.scala 327:30] + node _T_390 = bits(dccm_rdata_lo_any, 3, 3) @[el2_lib.scala 325:36] + _T_378[2] <= _T_390 @[el2_lib.scala 325:30] + node _T_391 = bits(dccm_rdata_lo_any, 3, 3) @[el2_lib.scala 326:36] + _T_379[2] <= _T_391 @[el2_lib.scala 326:30] + node _T_392 = bits(dccm_rdata_lo_any, 3, 3) @[el2_lib.scala 327:36] + _T_380[2] <= _T_392 @[el2_lib.scala 327:30] + node _T_393 = bits(dccm_rdata_lo_any, 4, 4) @[el2_lib.scala 325:36] + _T_378[3] <= _T_393 @[el2_lib.scala 325:30] + node _T_394 = bits(dccm_rdata_lo_any, 4, 4) @[el2_lib.scala 328:36] + _T_381[0] <= _T_394 @[el2_lib.scala 328:30] + node _T_395 = bits(dccm_rdata_lo_any, 5, 5) @[el2_lib.scala 326:36] + _T_379[3] <= _T_395 @[el2_lib.scala 326:30] + node _T_396 = bits(dccm_rdata_lo_any, 5, 5) @[el2_lib.scala 328:36] + _T_381[1] <= _T_396 @[el2_lib.scala 328:30] + node _T_397 = bits(dccm_rdata_lo_any, 6, 6) @[el2_lib.scala 325:36] + _T_378[4] <= _T_397 @[el2_lib.scala 325:30] + node _T_398 = bits(dccm_rdata_lo_any, 6, 6) @[el2_lib.scala 326:36] + _T_379[4] <= _T_398 @[el2_lib.scala 326:30] + node _T_399 = bits(dccm_rdata_lo_any, 6, 6) @[el2_lib.scala 328:36] + _T_381[2] <= _T_399 @[el2_lib.scala 328:30] + node _T_400 = bits(dccm_rdata_lo_any, 7, 7) @[el2_lib.scala 327:36] + _T_380[3] <= _T_400 @[el2_lib.scala 327:30] + node _T_401 = bits(dccm_rdata_lo_any, 7, 7) @[el2_lib.scala 328:36] + _T_381[3] <= _T_401 @[el2_lib.scala 328:30] + node _T_402 = bits(dccm_rdata_lo_any, 8, 8) @[el2_lib.scala 325:36] + _T_378[5] <= _T_402 @[el2_lib.scala 325:30] + node _T_403 = bits(dccm_rdata_lo_any, 8, 8) @[el2_lib.scala 327:36] + _T_380[4] <= _T_403 @[el2_lib.scala 327:30] + node _T_404 = bits(dccm_rdata_lo_any, 8, 8) @[el2_lib.scala 328:36] + _T_381[4] <= _T_404 @[el2_lib.scala 328:30] + node _T_405 = bits(dccm_rdata_lo_any, 9, 9) @[el2_lib.scala 326:36] + _T_379[5] <= _T_405 @[el2_lib.scala 326:30] + node _T_406 = bits(dccm_rdata_lo_any, 9, 9) @[el2_lib.scala 327:36] + _T_380[5] <= _T_406 @[el2_lib.scala 327:30] + node _T_407 = bits(dccm_rdata_lo_any, 9, 9) @[el2_lib.scala 328:36] + _T_381[5] <= _T_407 @[el2_lib.scala 328:30] + node _T_408 = bits(dccm_rdata_lo_any, 10, 10) @[el2_lib.scala 325:36] + _T_378[6] <= _T_408 @[el2_lib.scala 325:30] + node _T_409 = bits(dccm_rdata_lo_any, 10, 10) @[el2_lib.scala 326:36] + _T_379[6] <= _T_409 @[el2_lib.scala 326:30] + node _T_410 = bits(dccm_rdata_lo_any, 10, 10) @[el2_lib.scala 327:36] + _T_380[6] <= _T_410 @[el2_lib.scala 327:30] + node _T_411 = bits(dccm_rdata_lo_any, 10, 10) @[el2_lib.scala 328:36] + _T_381[6] <= _T_411 @[el2_lib.scala 328:30] + node _T_412 = bits(dccm_rdata_lo_any, 11, 11) @[el2_lib.scala 325:36] + _T_378[7] <= _T_412 @[el2_lib.scala 325:30] + node _T_413 = bits(dccm_rdata_lo_any, 11, 11) @[el2_lib.scala 329:36] + _T_382[0] <= _T_413 @[el2_lib.scala 329:30] + node _T_414 = bits(dccm_rdata_lo_any, 12, 12) @[el2_lib.scala 326:36] + _T_379[7] <= _T_414 @[el2_lib.scala 326:30] + node _T_415 = bits(dccm_rdata_lo_any, 12, 12) @[el2_lib.scala 329:36] + _T_382[1] <= _T_415 @[el2_lib.scala 329:30] + node _T_416 = bits(dccm_rdata_lo_any, 13, 13) @[el2_lib.scala 325:36] + _T_378[8] <= _T_416 @[el2_lib.scala 325:30] + node _T_417 = bits(dccm_rdata_lo_any, 13, 13) @[el2_lib.scala 326:36] + _T_379[8] <= _T_417 @[el2_lib.scala 326:30] + node _T_418 = bits(dccm_rdata_lo_any, 13, 13) @[el2_lib.scala 329:36] + _T_382[2] <= _T_418 @[el2_lib.scala 329:30] + node _T_419 = bits(dccm_rdata_lo_any, 14, 14) @[el2_lib.scala 327:36] + _T_380[7] <= _T_419 @[el2_lib.scala 327:30] + node _T_420 = bits(dccm_rdata_lo_any, 14, 14) @[el2_lib.scala 329:36] + _T_382[3] <= _T_420 @[el2_lib.scala 329:30] + node _T_421 = bits(dccm_rdata_lo_any, 15, 15) @[el2_lib.scala 325:36] + _T_378[9] <= _T_421 @[el2_lib.scala 325:30] + node _T_422 = bits(dccm_rdata_lo_any, 15, 15) @[el2_lib.scala 327:36] + _T_380[8] <= _T_422 @[el2_lib.scala 327:30] + node _T_423 = bits(dccm_rdata_lo_any, 15, 15) @[el2_lib.scala 329:36] + _T_382[4] <= _T_423 @[el2_lib.scala 329:30] + node _T_424 = bits(dccm_rdata_lo_any, 16, 16) @[el2_lib.scala 326:36] + _T_379[9] <= _T_424 @[el2_lib.scala 326:30] + node _T_425 = bits(dccm_rdata_lo_any, 16, 16) @[el2_lib.scala 327:36] + _T_380[9] <= _T_425 @[el2_lib.scala 327:30] + node _T_426 = bits(dccm_rdata_lo_any, 16, 16) @[el2_lib.scala 329:36] + _T_382[5] <= _T_426 @[el2_lib.scala 329:30] + node _T_427 = bits(dccm_rdata_lo_any, 17, 17) @[el2_lib.scala 325:36] + _T_378[10] <= _T_427 @[el2_lib.scala 325:30] + node _T_428 = bits(dccm_rdata_lo_any, 17, 17) @[el2_lib.scala 326:36] + _T_379[10] <= _T_428 @[el2_lib.scala 326:30] + node _T_429 = bits(dccm_rdata_lo_any, 17, 17) @[el2_lib.scala 327:36] + _T_380[10] <= _T_429 @[el2_lib.scala 327:30] + node _T_430 = bits(dccm_rdata_lo_any, 17, 17) @[el2_lib.scala 329:36] + _T_382[6] <= _T_430 @[el2_lib.scala 329:30] + node _T_431 = bits(dccm_rdata_lo_any, 18, 18) @[el2_lib.scala 328:36] + _T_381[7] <= _T_431 @[el2_lib.scala 328:30] + node _T_432 = bits(dccm_rdata_lo_any, 18, 18) @[el2_lib.scala 329:36] + _T_382[7] <= _T_432 @[el2_lib.scala 329:30] + node _T_433 = bits(dccm_rdata_lo_any, 19, 19) @[el2_lib.scala 325:36] + _T_378[11] <= _T_433 @[el2_lib.scala 325:30] + node _T_434 = bits(dccm_rdata_lo_any, 19, 19) @[el2_lib.scala 328:36] + _T_381[8] <= _T_434 @[el2_lib.scala 328:30] + node _T_435 = bits(dccm_rdata_lo_any, 19, 19) @[el2_lib.scala 329:36] + _T_382[8] <= _T_435 @[el2_lib.scala 329:30] + node _T_436 = bits(dccm_rdata_lo_any, 20, 20) @[el2_lib.scala 326:36] + _T_379[11] <= _T_436 @[el2_lib.scala 326:30] + node _T_437 = bits(dccm_rdata_lo_any, 20, 20) @[el2_lib.scala 328:36] + _T_381[9] <= _T_437 @[el2_lib.scala 328:30] + node _T_438 = bits(dccm_rdata_lo_any, 20, 20) @[el2_lib.scala 329:36] + _T_382[9] <= _T_438 @[el2_lib.scala 329:30] + node _T_439 = bits(dccm_rdata_lo_any, 21, 21) @[el2_lib.scala 325:36] + _T_378[12] <= _T_439 @[el2_lib.scala 325:30] + node _T_440 = bits(dccm_rdata_lo_any, 21, 21) @[el2_lib.scala 326:36] + _T_379[12] <= _T_440 @[el2_lib.scala 326:30] + node _T_441 = bits(dccm_rdata_lo_any, 21, 21) @[el2_lib.scala 328:36] + _T_381[10] <= _T_441 @[el2_lib.scala 328:30] + node _T_442 = bits(dccm_rdata_lo_any, 21, 21) @[el2_lib.scala 329:36] + _T_382[10] <= _T_442 @[el2_lib.scala 329:30] + node _T_443 = bits(dccm_rdata_lo_any, 22, 22) @[el2_lib.scala 327:36] + _T_380[11] <= _T_443 @[el2_lib.scala 327:30] + node _T_444 = bits(dccm_rdata_lo_any, 22, 22) @[el2_lib.scala 328:36] + _T_381[11] <= _T_444 @[el2_lib.scala 328:30] + node _T_445 = bits(dccm_rdata_lo_any, 22, 22) @[el2_lib.scala 329:36] + _T_382[11] <= _T_445 @[el2_lib.scala 329:30] + node _T_446 = bits(dccm_rdata_lo_any, 23, 23) @[el2_lib.scala 325:36] + _T_378[13] <= _T_446 @[el2_lib.scala 325:30] + node _T_447 = bits(dccm_rdata_lo_any, 23, 23) @[el2_lib.scala 327:36] + _T_380[12] <= _T_447 @[el2_lib.scala 327:30] + node _T_448 = bits(dccm_rdata_lo_any, 23, 23) @[el2_lib.scala 328:36] + _T_381[12] <= _T_448 @[el2_lib.scala 328:30] + node _T_449 = bits(dccm_rdata_lo_any, 23, 23) @[el2_lib.scala 329:36] + _T_382[12] <= _T_449 @[el2_lib.scala 329:30] + node _T_450 = bits(dccm_rdata_lo_any, 24, 24) @[el2_lib.scala 326:36] + _T_379[13] <= _T_450 @[el2_lib.scala 326:30] + node _T_451 = bits(dccm_rdata_lo_any, 24, 24) @[el2_lib.scala 327:36] + _T_380[13] <= _T_451 @[el2_lib.scala 327:30] + node _T_452 = bits(dccm_rdata_lo_any, 24, 24) @[el2_lib.scala 328:36] + _T_381[13] <= _T_452 @[el2_lib.scala 328:30] + node _T_453 = bits(dccm_rdata_lo_any, 24, 24) @[el2_lib.scala 329:36] + _T_382[13] <= _T_453 @[el2_lib.scala 329:30] + node _T_454 = bits(dccm_rdata_lo_any, 25, 25) @[el2_lib.scala 325:36] + _T_378[14] <= _T_454 @[el2_lib.scala 325:30] + node _T_455 = bits(dccm_rdata_lo_any, 25, 25) @[el2_lib.scala 326:36] + _T_379[14] <= _T_455 @[el2_lib.scala 326:30] + node _T_456 = bits(dccm_rdata_lo_any, 25, 25) @[el2_lib.scala 327:36] + _T_380[14] <= _T_456 @[el2_lib.scala 327:30] + node _T_457 = bits(dccm_rdata_lo_any, 25, 25) @[el2_lib.scala 328:36] + _T_381[14] <= _T_457 @[el2_lib.scala 328:30] + node _T_458 = bits(dccm_rdata_lo_any, 25, 25) @[el2_lib.scala 329:36] + _T_382[14] <= _T_458 @[el2_lib.scala 329:30] + node _T_459 = bits(dccm_rdata_lo_any, 26, 26) @[el2_lib.scala 325:36] + _T_378[15] <= _T_459 @[el2_lib.scala 325:30] + node _T_460 = bits(dccm_rdata_lo_any, 26, 26) @[el2_lib.scala 330:36] + _T_383[0] <= _T_460 @[el2_lib.scala 330:30] + node _T_461 = bits(dccm_rdata_lo_any, 27, 27) @[el2_lib.scala 326:36] + _T_379[15] <= _T_461 @[el2_lib.scala 326:30] + node _T_462 = bits(dccm_rdata_lo_any, 27, 27) @[el2_lib.scala 330:36] + _T_383[1] <= _T_462 @[el2_lib.scala 330:30] + node _T_463 = bits(dccm_rdata_lo_any, 28, 28) @[el2_lib.scala 325:36] + _T_378[16] <= _T_463 @[el2_lib.scala 325:30] + node _T_464 = bits(dccm_rdata_lo_any, 28, 28) @[el2_lib.scala 326:36] + _T_379[16] <= _T_464 @[el2_lib.scala 326:30] + node _T_465 = bits(dccm_rdata_lo_any, 28, 28) @[el2_lib.scala 330:36] + _T_383[2] <= _T_465 @[el2_lib.scala 330:30] + node _T_466 = bits(dccm_rdata_lo_any, 29, 29) @[el2_lib.scala 327:36] + _T_380[15] <= _T_466 @[el2_lib.scala 327:30] + node _T_467 = bits(dccm_rdata_lo_any, 29, 29) @[el2_lib.scala 330:36] + _T_383[3] <= _T_467 @[el2_lib.scala 330:30] + node _T_468 = bits(dccm_rdata_lo_any, 30, 30) @[el2_lib.scala 325:36] + _T_378[17] <= _T_468 @[el2_lib.scala 325:30] + node _T_469 = bits(dccm_rdata_lo_any, 30, 30) @[el2_lib.scala 327:36] + _T_380[16] <= _T_469 @[el2_lib.scala 327:30] + node _T_470 = bits(dccm_rdata_lo_any, 30, 30) @[el2_lib.scala 330:36] + _T_383[4] <= _T_470 @[el2_lib.scala 330:30] + node _T_471 = bits(dccm_rdata_lo_any, 31, 31) @[el2_lib.scala 326:36] + _T_379[17] <= _T_471 @[el2_lib.scala 326:30] + node _T_472 = bits(dccm_rdata_lo_any, 31, 31) @[el2_lib.scala 327:36] + _T_380[17] <= _T_472 @[el2_lib.scala 327:30] + node _T_473 = bits(dccm_rdata_lo_any, 31, 31) @[el2_lib.scala 330:36] + _T_383[5] <= _T_473 @[el2_lib.scala 330:30] + node _T_474 = xorr(dccm_rdata_lo_any) @[el2_lib.scala 333:30] + node _T_475 = xorr(dccm_data_ecc_lo_any) @[el2_lib.scala 333:44] + node _T_476 = xor(_T_474, _T_475) @[el2_lib.scala 333:35] + node _T_477 = not(UInt<1>("h00")) @[el2_lib.scala 333:52] + node _T_478 = and(_T_476, _T_477) @[el2_lib.scala 333:50] + node _T_479 = bits(dccm_data_ecc_lo_any, 5, 5) @[el2_lib.scala 333:68] + node _T_480 = cat(_T_383[2], _T_383[1]) @[el2_lib.scala 333:76] + node _T_481 = cat(_T_480, _T_383[0]) @[el2_lib.scala 333:76] + node _T_482 = cat(_T_383[5], _T_383[4]) @[el2_lib.scala 333:76] + node _T_483 = cat(_T_482, _T_383[3]) @[el2_lib.scala 333:76] + node _T_484 = cat(_T_483, _T_481) @[el2_lib.scala 333:76] + node _T_485 = xorr(_T_484) @[el2_lib.scala 333:83] + node _T_486 = xor(_T_479, _T_485) @[el2_lib.scala 333:71] + node _T_487 = bits(dccm_data_ecc_lo_any, 4, 4) @[el2_lib.scala 333:95] + node _T_488 = cat(_T_382[2], _T_382[1]) @[el2_lib.scala 333:103] + node _T_489 = cat(_T_488, _T_382[0]) @[el2_lib.scala 333:103] + node _T_490 = cat(_T_382[4], _T_382[3]) @[el2_lib.scala 333:103] + node _T_491 = cat(_T_382[6], _T_382[5]) @[el2_lib.scala 333:103] + node _T_492 = cat(_T_491, _T_490) @[el2_lib.scala 333:103] + node _T_493 = cat(_T_492, _T_489) @[el2_lib.scala 333:103] + node _T_494 = cat(_T_382[8], _T_382[7]) @[el2_lib.scala 333:103] + node _T_495 = cat(_T_382[10], _T_382[9]) @[el2_lib.scala 333:103] + node _T_496 = cat(_T_495, _T_494) @[el2_lib.scala 333:103] + node _T_497 = cat(_T_382[12], _T_382[11]) @[el2_lib.scala 333:103] + node _T_498 = cat(_T_382[14], _T_382[13]) @[el2_lib.scala 333:103] + node _T_499 = cat(_T_498, _T_497) @[el2_lib.scala 333:103] + node _T_500 = cat(_T_499, _T_496) @[el2_lib.scala 333:103] + node _T_501 = cat(_T_500, _T_493) @[el2_lib.scala 333:103] + node _T_502 = xorr(_T_501) @[el2_lib.scala 333:110] + node _T_503 = xor(_T_487, _T_502) @[el2_lib.scala 333:98] + node _T_504 = bits(dccm_data_ecc_lo_any, 3, 3) @[el2_lib.scala 333:122] + node _T_505 = cat(_T_381[2], _T_381[1]) @[el2_lib.scala 333:130] + node _T_506 = cat(_T_505, _T_381[0]) @[el2_lib.scala 333:130] + node _T_507 = cat(_T_381[4], _T_381[3]) @[el2_lib.scala 333:130] + node _T_508 = cat(_T_381[6], _T_381[5]) @[el2_lib.scala 333:130] + node _T_509 = cat(_T_508, _T_507) @[el2_lib.scala 333:130] + node _T_510 = cat(_T_509, _T_506) @[el2_lib.scala 333:130] + node _T_511 = cat(_T_381[8], _T_381[7]) @[el2_lib.scala 333:130] + node _T_512 = cat(_T_381[10], _T_381[9]) @[el2_lib.scala 333:130] + node _T_513 = cat(_T_512, _T_511) @[el2_lib.scala 333:130] + node _T_514 = cat(_T_381[12], _T_381[11]) @[el2_lib.scala 333:130] + node _T_515 = cat(_T_381[14], _T_381[13]) @[el2_lib.scala 333:130] + node _T_516 = cat(_T_515, _T_514) @[el2_lib.scala 333:130] + node _T_517 = cat(_T_516, _T_513) @[el2_lib.scala 333:130] + node _T_518 = cat(_T_517, _T_510) @[el2_lib.scala 333:130] + node _T_519 = xorr(_T_518) @[el2_lib.scala 333:137] + node _T_520 = xor(_T_504, _T_519) @[el2_lib.scala 333:125] + node _T_521 = bits(dccm_data_ecc_lo_any, 2, 2) @[el2_lib.scala 333:149] + node _T_522 = cat(_T_380[1], _T_380[0]) @[el2_lib.scala 333:157] + node _T_523 = cat(_T_380[3], _T_380[2]) @[el2_lib.scala 333:157] + node _T_524 = cat(_T_523, _T_522) @[el2_lib.scala 333:157] + node _T_525 = cat(_T_380[5], _T_380[4]) @[el2_lib.scala 333:157] + node _T_526 = cat(_T_380[8], _T_380[7]) @[el2_lib.scala 333:157] + node _T_527 = cat(_T_526, _T_380[6]) @[el2_lib.scala 333:157] + node _T_528 = cat(_T_527, _T_525) @[el2_lib.scala 333:157] + node _T_529 = cat(_T_528, _T_524) @[el2_lib.scala 333:157] + node _T_530 = cat(_T_380[10], _T_380[9]) @[el2_lib.scala 333:157] + node _T_531 = cat(_T_380[12], _T_380[11]) @[el2_lib.scala 333:157] + node _T_532 = cat(_T_531, _T_530) @[el2_lib.scala 333:157] + node _T_533 = cat(_T_380[14], _T_380[13]) @[el2_lib.scala 333:157] + node _T_534 = cat(_T_380[17], _T_380[16]) @[el2_lib.scala 333:157] + node _T_535 = cat(_T_534, _T_380[15]) @[el2_lib.scala 333:157] + node _T_536 = cat(_T_535, _T_533) @[el2_lib.scala 333:157] + node _T_537 = cat(_T_536, _T_532) @[el2_lib.scala 333:157] + node _T_538 = cat(_T_537, _T_529) @[el2_lib.scala 333:157] + node _T_539 = xorr(_T_538) @[el2_lib.scala 333:164] + node _T_540 = xor(_T_521, _T_539) @[el2_lib.scala 333:152] + node _T_541 = bits(dccm_data_ecc_lo_any, 1, 1) @[el2_lib.scala 333:176] + node _T_542 = cat(_T_379[1], _T_379[0]) @[el2_lib.scala 333:184] + node _T_543 = cat(_T_379[3], _T_379[2]) @[el2_lib.scala 333:184] + node _T_544 = cat(_T_543, _T_542) @[el2_lib.scala 333:184] + node _T_545 = cat(_T_379[5], _T_379[4]) @[el2_lib.scala 333:184] + node _T_546 = cat(_T_379[8], _T_379[7]) @[el2_lib.scala 333:184] + node _T_547 = cat(_T_546, _T_379[6]) @[el2_lib.scala 333:184] + node _T_548 = cat(_T_547, _T_545) @[el2_lib.scala 333:184] + node _T_549 = cat(_T_548, _T_544) @[el2_lib.scala 333:184] + node _T_550 = cat(_T_379[10], _T_379[9]) @[el2_lib.scala 333:184] + node _T_551 = cat(_T_379[12], _T_379[11]) @[el2_lib.scala 333:184] + node _T_552 = cat(_T_551, _T_550) @[el2_lib.scala 333:184] + node _T_553 = cat(_T_379[14], _T_379[13]) @[el2_lib.scala 333:184] + node _T_554 = cat(_T_379[17], _T_379[16]) @[el2_lib.scala 333:184] + node _T_555 = cat(_T_554, _T_379[15]) @[el2_lib.scala 333:184] + node _T_556 = cat(_T_555, _T_553) @[el2_lib.scala 333:184] + node _T_557 = cat(_T_556, _T_552) @[el2_lib.scala 333:184] + node _T_558 = cat(_T_557, _T_549) @[el2_lib.scala 333:184] + node _T_559 = xorr(_T_558) @[el2_lib.scala 333:191] + node _T_560 = xor(_T_541, _T_559) @[el2_lib.scala 333:179] + node _T_561 = bits(dccm_data_ecc_lo_any, 0, 0) @[el2_lib.scala 333:203] + node _T_562 = cat(_T_378[1], _T_378[0]) @[el2_lib.scala 333:211] + node _T_563 = cat(_T_378[3], _T_378[2]) @[el2_lib.scala 333:211] + node _T_564 = cat(_T_563, _T_562) @[el2_lib.scala 333:211] + node _T_565 = cat(_T_378[5], _T_378[4]) @[el2_lib.scala 333:211] + node _T_566 = cat(_T_378[8], _T_378[7]) @[el2_lib.scala 333:211] + node _T_567 = cat(_T_566, _T_378[6]) @[el2_lib.scala 333:211] + node _T_568 = cat(_T_567, _T_565) @[el2_lib.scala 333:211] + node _T_569 = cat(_T_568, _T_564) @[el2_lib.scala 333:211] + node _T_570 = cat(_T_378[10], _T_378[9]) @[el2_lib.scala 333:211] + node _T_571 = cat(_T_378[12], _T_378[11]) @[el2_lib.scala 333:211] + node _T_572 = cat(_T_571, _T_570) @[el2_lib.scala 333:211] + node _T_573 = cat(_T_378[14], _T_378[13]) @[el2_lib.scala 333:211] + node _T_574 = cat(_T_378[17], _T_378[16]) @[el2_lib.scala 333:211] + node _T_575 = cat(_T_574, _T_378[15]) @[el2_lib.scala 333:211] + node _T_576 = cat(_T_575, _T_573) @[el2_lib.scala 333:211] + node _T_577 = cat(_T_576, _T_572) @[el2_lib.scala 333:211] + node _T_578 = cat(_T_577, _T_569) @[el2_lib.scala 333:211] + node _T_579 = xorr(_T_578) @[el2_lib.scala 333:218] + node _T_580 = xor(_T_561, _T_579) @[el2_lib.scala 333:206] node _T_581 = cat(_T_540, _T_560) @[Cat.scala 29:58] node _T_582 = cat(_T_581, _T_580) @[Cat.scala 29:58] node _T_583 = cat(_T_503, _T_520) @[Cat.scala 29:58] node _T_584 = cat(_T_478, _T_486) @[Cat.scala 29:58] node _T_585 = cat(_T_584, _T_583) @[Cat.scala 29:58] node _T_586 = cat(_T_585, _T_582) @[Cat.scala 29:58] - node _T_587 = neq(_T_586, UInt<1>("h00")) @[el2_lib.scala 325:44] - node _T_588 = and(is_ldst_lo_any, _T_587) @[el2_lib.scala 325:32] - node _T_589 = bits(_T_586, 6, 6) @[el2_lib.scala 325:64] - node single_ecc_error_lo_any = and(_T_588, _T_589) @[el2_lib.scala 325:53] - node _T_590 = neq(_T_586, UInt<1>("h00")) @[el2_lib.scala 326:44] - node _T_591 = and(is_ldst_lo_any, _T_590) @[el2_lib.scala 326:32] - node _T_592 = bits(_T_586, 6, 6) @[el2_lib.scala 326:65] - node _T_593 = not(_T_592) @[el2_lib.scala 326:55] - node double_ecc_error_lo_any = and(_T_591, _T_593) @[el2_lib.scala 326:53] - wire _T_594 : UInt<1>[39] @[el2_lib.scala 327:26] - node _T_595 = bits(_T_586, 5, 0) @[el2_lib.scala 330:35] - node _T_596 = eq(_T_595, UInt<1>("h01")) @[el2_lib.scala 330:41] - _T_594[0] <= _T_596 @[el2_lib.scala 330:23] - node _T_597 = bits(_T_586, 5, 0) @[el2_lib.scala 330:35] - node _T_598 = eq(_T_597, UInt<2>("h02")) @[el2_lib.scala 330:41] - _T_594[1] <= _T_598 @[el2_lib.scala 330:23] - node _T_599 = bits(_T_586, 5, 0) @[el2_lib.scala 330:35] - node _T_600 = eq(_T_599, UInt<2>("h03")) @[el2_lib.scala 330:41] - _T_594[2] <= _T_600 @[el2_lib.scala 330:23] - node _T_601 = bits(_T_586, 5, 0) @[el2_lib.scala 330:35] - node _T_602 = eq(_T_601, UInt<3>("h04")) @[el2_lib.scala 330:41] - _T_594[3] <= _T_602 @[el2_lib.scala 330:23] - node _T_603 = bits(_T_586, 5, 0) @[el2_lib.scala 330:35] - node _T_604 = eq(_T_603, UInt<3>("h05")) @[el2_lib.scala 330:41] - _T_594[4] <= _T_604 @[el2_lib.scala 330:23] - node _T_605 = bits(_T_586, 5, 0) @[el2_lib.scala 330:35] - node _T_606 = eq(_T_605, UInt<3>("h06")) @[el2_lib.scala 330:41] - _T_594[5] <= _T_606 @[el2_lib.scala 330:23] - node _T_607 = bits(_T_586, 5, 0) @[el2_lib.scala 330:35] - node _T_608 = eq(_T_607, UInt<3>("h07")) @[el2_lib.scala 330:41] - _T_594[6] <= _T_608 @[el2_lib.scala 330:23] - node _T_609 = bits(_T_586, 5, 0) @[el2_lib.scala 330:35] - node _T_610 = eq(_T_609, UInt<4>("h08")) @[el2_lib.scala 330:41] - _T_594[7] <= _T_610 @[el2_lib.scala 330:23] - node _T_611 = bits(_T_586, 5, 0) @[el2_lib.scala 330:35] - node _T_612 = eq(_T_611, UInt<4>("h09")) @[el2_lib.scala 330:41] - _T_594[8] <= _T_612 @[el2_lib.scala 330:23] - node _T_613 = bits(_T_586, 5, 0) @[el2_lib.scala 330:35] - node _T_614 = eq(_T_613, UInt<4>("h0a")) @[el2_lib.scala 330:41] - _T_594[9] <= _T_614 @[el2_lib.scala 330:23] - node _T_615 = bits(_T_586, 5, 0) @[el2_lib.scala 330:35] - node _T_616 = eq(_T_615, UInt<4>("h0b")) @[el2_lib.scala 330:41] - _T_594[10] <= _T_616 @[el2_lib.scala 330:23] - node _T_617 = bits(_T_586, 5, 0) @[el2_lib.scala 330:35] - node _T_618 = eq(_T_617, UInt<4>("h0c")) @[el2_lib.scala 330:41] - _T_594[11] <= _T_618 @[el2_lib.scala 330:23] - node _T_619 = bits(_T_586, 5, 0) @[el2_lib.scala 330:35] - node _T_620 = eq(_T_619, UInt<4>("h0d")) @[el2_lib.scala 330:41] - _T_594[12] <= _T_620 @[el2_lib.scala 330:23] - node _T_621 = bits(_T_586, 5, 0) @[el2_lib.scala 330:35] - node _T_622 = eq(_T_621, UInt<4>("h0e")) @[el2_lib.scala 330:41] - _T_594[13] <= _T_622 @[el2_lib.scala 330:23] - node _T_623 = bits(_T_586, 5, 0) @[el2_lib.scala 330:35] - node _T_624 = eq(_T_623, UInt<4>("h0f")) @[el2_lib.scala 330:41] - _T_594[14] <= _T_624 @[el2_lib.scala 330:23] - node _T_625 = bits(_T_586, 5, 0) @[el2_lib.scala 330:35] - node _T_626 = eq(_T_625, UInt<5>("h010")) @[el2_lib.scala 330:41] - _T_594[15] <= _T_626 @[el2_lib.scala 330:23] - node _T_627 = bits(_T_586, 5, 0) @[el2_lib.scala 330:35] - node _T_628 = eq(_T_627, UInt<5>("h011")) @[el2_lib.scala 330:41] - _T_594[16] <= _T_628 @[el2_lib.scala 330:23] - node _T_629 = bits(_T_586, 5, 0) @[el2_lib.scala 330:35] - node _T_630 = eq(_T_629, UInt<5>("h012")) @[el2_lib.scala 330:41] - _T_594[17] <= _T_630 @[el2_lib.scala 330:23] - node _T_631 = bits(_T_586, 5, 0) @[el2_lib.scala 330:35] - node _T_632 = eq(_T_631, UInt<5>("h013")) @[el2_lib.scala 330:41] - _T_594[18] <= _T_632 @[el2_lib.scala 330:23] - node _T_633 = bits(_T_586, 5, 0) @[el2_lib.scala 330:35] - node _T_634 = eq(_T_633, UInt<5>("h014")) @[el2_lib.scala 330:41] - _T_594[19] <= _T_634 @[el2_lib.scala 330:23] - node _T_635 = bits(_T_586, 5, 0) @[el2_lib.scala 330:35] - node _T_636 = eq(_T_635, UInt<5>("h015")) @[el2_lib.scala 330:41] - _T_594[20] <= _T_636 @[el2_lib.scala 330:23] - node _T_637 = bits(_T_586, 5, 0) @[el2_lib.scala 330:35] - node _T_638 = eq(_T_637, UInt<5>("h016")) @[el2_lib.scala 330:41] - _T_594[21] <= _T_638 @[el2_lib.scala 330:23] - node _T_639 = bits(_T_586, 5, 0) @[el2_lib.scala 330:35] - node _T_640 = eq(_T_639, UInt<5>("h017")) @[el2_lib.scala 330:41] - _T_594[22] <= _T_640 @[el2_lib.scala 330:23] - node _T_641 = bits(_T_586, 5, 0) @[el2_lib.scala 330:35] - node _T_642 = eq(_T_641, UInt<5>("h018")) @[el2_lib.scala 330:41] - _T_594[23] <= _T_642 @[el2_lib.scala 330:23] - node _T_643 = bits(_T_586, 5, 0) @[el2_lib.scala 330:35] - node _T_644 = eq(_T_643, UInt<5>("h019")) @[el2_lib.scala 330:41] - _T_594[24] <= _T_644 @[el2_lib.scala 330:23] - node _T_645 = bits(_T_586, 5, 0) @[el2_lib.scala 330:35] - node _T_646 = eq(_T_645, UInt<5>("h01a")) @[el2_lib.scala 330:41] - _T_594[25] <= _T_646 @[el2_lib.scala 330:23] - node _T_647 = bits(_T_586, 5, 0) @[el2_lib.scala 330:35] - node _T_648 = eq(_T_647, UInt<5>("h01b")) @[el2_lib.scala 330:41] - _T_594[26] <= _T_648 @[el2_lib.scala 330:23] - node _T_649 = bits(_T_586, 5, 0) @[el2_lib.scala 330:35] - node _T_650 = eq(_T_649, UInt<5>("h01c")) @[el2_lib.scala 330:41] - _T_594[27] <= _T_650 @[el2_lib.scala 330:23] - node _T_651 = bits(_T_586, 5, 0) @[el2_lib.scala 330:35] - node _T_652 = eq(_T_651, UInt<5>("h01d")) @[el2_lib.scala 330:41] - _T_594[28] <= _T_652 @[el2_lib.scala 330:23] - node _T_653 = bits(_T_586, 5, 0) @[el2_lib.scala 330:35] - node _T_654 = eq(_T_653, UInt<5>("h01e")) @[el2_lib.scala 330:41] - _T_594[29] <= _T_654 @[el2_lib.scala 330:23] - node _T_655 = bits(_T_586, 5, 0) @[el2_lib.scala 330:35] - node _T_656 = eq(_T_655, UInt<5>("h01f")) @[el2_lib.scala 330:41] - _T_594[30] <= _T_656 @[el2_lib.scala 330:23] - node _T_657 = bits(_T_586, 5, 0) @[el2_lib.scala 330:35] - node _T_658 = eq(_T_657, UInt<6>("h020")) @[el2_lib.scala 330:41] - _T_594[31] <= _T_658 @[el2_lib.scala 330:23] - node _T_659 = bits(_T_586, 5, 0) @[el2_lib.scala 330:35] - node _T_660 = eq(_T_659, UInt<6>("h021")) @[el2_lib.scala 330:41] - _T_594[32] <= _T_660 @[el2_lib.scala 330:23] - node _T_661 = bits(_T_586, 5, 0) @[el2_lib.scala 330:35] - node _T_662 = eq(_T_661, UInt<6>("h022")) @[el2_lib.scala 330:41] - _T_594[33] <= _T_662 @[el2_lib.scala 330:23] - node _T_663 = bits(_T_586, 5, 0) @[el2_lib.scala 330:35] - node _T_664 = eq(_T_663, UInt<6>("h023")) @[el2_lib.scala 330:41] - _T_594[34] <= _T_664 @[el2_lib.scala 330:23] - node _T_665 = bits(_T_586, 5, 0) @[el2_lib.scala 330:35] - node _T_666 = eq(_T_665, UInt<6>("h024")) @[el2_lib.scala 330:41] - _T_594[35] <= _T_666 @[el2_lib.scala 330:23] - node _T_667 = bits(_T_586, 5, 0) @[el2_lib.scala 330:35] - node _T_668 = eq(_T_667, UInt<6>("h025")) @[el2_lib.scala 330:41] - _T_594[36] <= _T_668 @[el2_lib.scala 330:23] - node _T_669 = bits(_T_586, 5, 0) @[el2_lib.scala 330:35] - node _T_670 = eq(_T_669, UInt<6>("h026")) @[el2_lib.scala 330:41] - _T_594[37] <= _T_670 @[el2_lib.scala 330:23] - node _T_671 = bits(_T_586, 5, 0) @[el2_lib.scala 330:35] - node _T_672 = eq(_T_671, UInt<6>("h027")) @[el2_lib.scala 330:41] - _T_594[38] <= _T_672 @[el2_lib.scala 330:23] - node _T_673 = bits(dccm_data_ecc_lo_any, 6, 6) @[el2_lib.scala 332:37] - node _T_674 = bits(dccm_rdata_lo_any, 31, 26) @[el2_lib.scala 332:45] - node _T_675 = bits(dccm_data_ecc_lo_any, 5, 5) @[el2_lib.scala 332:60] - node _T_676 = bits(dccm_rdata_lo_any, 25, 11) @[el2_lib.scala 332:68] - node _T_677 = bits(dccm_data_ecc_lo_any, 4, 4) @[el2_lib.scala 332:83] - node _T_678 = bits(dccm_rdata_lo_any, 10, 4) @[el2_lib.scala 332:91] - node _T_679 = bits(dccm_data_ecc_lo_any, 3, 3) @[el2_lib.scala 332:105] - node _T_680 = bits(dccm_rdata_lo_any, 3, 1) @[el2_lib.scala 332:113] - node _T_681 = bits(dccm_data_ecc_lo_any, 2, 2) @[el2_lib.scala 332:126] - node _T_682 = bits(dccm_rdata_lo_any, 0, 0) @[el2_lib.scala 332:134] - node _T_683 = bits(dccm_data_ecc_lo_any, 1, 0) @[el2_lib.scala 332:145] + node _T_587 = neq(_T_586, UInt<1>("h00")) @[el2_lib.scala 334:44] + node _T_588 = and(is_ldst_lo_any, _T_587) @[el2_lib.scala 334:32] + node _T_589 = bits(_T_586, 6, 6) @[el2_lib.scala 334:64] + node single_ecc_error_lo_any = and(_T_588, _T_589) @[el2_lib.scala 334:53] + node _T_590 = neq(_T_586, UInt<1>("h00")) @[el2_lib.scala 335:44] + node _T_591 = and(is_ldst_lo_any, _T_590) @[el2_lib.scala 335:32] + node _T_592 = bits(_T_586, 6, 6) @[el2_lib.scala 335:65] + node _T_593 = not(_T_592) @[el2_lib.scala 335:55] + node double_ecc_error_lo_any = and(_T_591, _T_593) @[el2_lib.scala 335:53] + wire _T_594 : UInt<1>[39] @[el2_lib.scala 336:26] + node _T_595 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_596 = eq(_T_595, UInt<1>("h01")) @[el2_lib.scala 339:41] + _T_594[0] <= _T_596 @[el2_lib.scala 339:23] + node _T_597 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_598 = eq(_T_597, UInt<2>("h02")) @[el2_lib.scala 339:41] + _T_594[1] <= _T_598 @[el2_lib.scala 339:23] + node _T_599 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_600 = eq(_T_599, UInt<2>("h03")) @[el2_lib.scala 339:41] + _T_594[2] <= _T_600 @[el2_lib.scala 339:23] + node _T_601 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_602 = eq(_T_601, UInt<3>("h04")) @[el2_lib.scala 339:41] + _T_594[3] <= _T_602 @[el2_lib.scala 339:23] + node _T_603 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_604 = eq(_T_603, UInt<3>("h05")) @[el2_lib.scala 339:41] + _T_594[4] <= _T_604 @[el2_lib.scala 339:23] + node _T_605 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_606 = eq(_T_605, UInt<3>("h06")) @[el2_lib.scala 339:41] + _T_594[5] <= _T_606 @[el2_lib.scala 339:23] + node _T_607 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_608 = eq(_T_607, UInt<3>("h07")) @[el2_lib.scala 339:41] + _T_594[6] <= _T_608 @[el2_lib.scala 339:23] + node _T_609 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_610 = eq(_T_609, UInt<4>("h08")) @[el2_lib.scala 339:41] + _T_594[7] <= _T_610 @[el2_lib.scala 339:23] + node _T_611 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_612 = eq(_T_611, UInt<4>("h09")) @[el2_lib.scala 339:41] + _T_594[8] <= _T_612 @[el2_lib.scala 339:23] + node _T_613 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_614 = eq(_T_613, UInt<4>("h0a")) @[el2_lib.scala 339:41] + _T_594[9] <= _T_614 @[el2_lib.scala 339:23] + node _T_615 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_616 = eq(_T_615, UInt<4>("h0b")) @[el2_lib.scala 339:41] + _T_594[10] <= _T_616 @[el2_lib.scala 339:23] + node _T_617 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_618 = eq(_T_617, UInt<4>("h0c")) @[el2_lib.scala 339:41] + _T_594[11] <= _T_618 @[el2_lib.scala 339:23] + node _T_619 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_620 = eq(_T_619, UInt<4>("h0d")) @[el2_lib.scala 339:41] + _T_594[12] <= _T_620 @[el2_lib.scala 339:23] + node _T_621 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_622 = eq(_T_621, UInt<4>("h0e")) @[el2_lib.scala 339:41] + _T_594[13] <= _T_622 @[el2_lib.scala 339:23] + node _T_623 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_624 = eq(_T_623, UInt<4>("h0f")) @[el2_lib.scala 339:41] + _T_594[14] <= _T_624 @[el2_lib.scala 339:23] + node _T_625 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_626 = eq(_T_625, UInt<5>("h010")) @[el2_lib.scala 339:41] + _T_594[15] <= _T_626 @[el2_lib.scala 339:23] + node _T_627 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_628 = eq(_T_627, UInt<5>("h011")) @[el2_lib.scala 339:41] + _T_594[16] <= _T_628 @[el2_lib.scala 339:23] + node _T_629 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_630 = eq(_T_629, UInt<5>("h012")) @[el2_lib.scala 339:41] + _T_594[17] <= _T_630 @[el2_lib.scala 339:23] + node _T_631 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_632 = eq(_T_631, UInt<5>("h013")) @[el2_lib.scala 339:41] + _T_594[18] <= _T_632 @[el2_lib.scala 339:23] + node _T_633 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_634 = eq(_T_633, UInt<5>("h014")) @[el2_lib.scala 339:41] + _T_594[19] <= _T_634 @[el2_lib.scala 339:23] + node _T_635 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_636 = eq(_T_635, UInt<5>("h015")) @[el2_lib.scala 339:41] + _T_594[20] <= _T_636 @[el2_lib.scala 339:23] + node _T_637 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_638 = eq(_T_637, UInt<5>("h016")) @[el2_lib.scala 339:41] + _T_594[21] <= _T_638 @[el2_lib.scala 339:23] + node _T_639 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_640 = eq(_T_639, UInt<5>("h017")) @[el2_lib.scala 339:41] + _T_594[22] <= _T_640 @[el2_lib.scala 339:23] + node _T_641 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_642 = eq(_T_641, UInt<5>("h018")) @[el2_lib.scala 339:41] + _T_594[23] <= _T_642 @[el2_lib.scala 339:23] + node _T_643 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_644 = eq(_T_643, UInt<5>("h019")) @[el2_lib.scala 339:41] + _T_594[24] <= _T_644 @[el2_lib.scala 339:23] + node _T_645 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_646 = eq(_T_645, UInt<5>("h01a")) @[el2_lib.scala 339:41] + _T_594[25] <= _T_646 @[el2_lib.scala 339:23] + node _T_647 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_648 = eq(_T_647, UInt<5>("h01b")) @[el2_lib.scala 339:41] + _T_594[26] <= _T_648 @[el2_lib.scala 339:23] + node _T_649 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_650 = eq(_T_649, UInt<5>("h01c")) @[el2_lib.scala 339:41] + _T_594[27] <= _T_650 @[el2_lib.scala 339:23] + node _T_651 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_652 = eq(_T_651, UInt<5>("h01d")) @[el2_lib.scala 339:41] + _T_594[28] <= _T_652 @[el2_lib.scala 339:23] + node _T_653 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_654 = eq(_T_653, UInt<5>("h01e")) @[el2_lib.scala 339:41] + _T_594[29] <= _T_654 @[el2_lib.scala 339:23] + node _T_655 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_656 = eq(_T_655, UInt<5>("h01f")) @[el2_lib.scala 339:41] + _T_594[30] <= _T_656 @[el2_lib.scala 339:23] + node _T_657 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_658 = eq(_T_657, UInt<6>("h020")) @[el2_lib.scala 339:41] + _T_594[31] <= _T_658 @[el2_lib.scala 339:23] + node _T_659 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_660 = eq(_T_659, UInt<6>("h021")) @[el2_lib.scala 339:41] + _T_594[32] <= _T_660 @[el2_lib.scala 339:23] + node _T_661 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_662 = eq(_T_661, UInt<6>("h022")) @[el2_lib.scala 339:41] + _T_594[33] <= _T_662 @[el2_lib.scala 339:23] + node _T_663 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_664 = eq(_T_663, UInt<6>("h023")) @[el2_lib.scala 339:41] + _T_594[34] <= _T_664 @[el2_lib.scala 339:23] + node _T_665 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_666 = eq(_T_665, UInt<6>("h024")) @[el2_lib.scala 339:41] + _T_594[35] <= _T_666 @[el2_lib.scala 339:23] + node _T_667 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_668 = eq(_T_667, UInt<6>("h025")) @[el2_lib.scala 339:41] + _T_594[36] <= _T_668 @[el2_lib.scala 339:23] + node _T_669 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_670 = eq(_T_669, UInt<6>("h026")) @[el2_lib.scala 339:41] + _T_594[37] <= _T_670 @[el2_lib.scala 339:23] + node _T_671 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_672 = eq(_T_671, UInt<6>("h027")) @[el2_lib.scala 339:41] + _T_594[38] <= _T_672 @[el2_lib.scala 339:23] + node _T_673 = bits(dccm_data_ecc_lo_any, 6, 6) @[el2_lib.scala 341:37] + node _T_674 = bits(dccm_rdata_lo_any, 31, 26) @[el2_lib.scala 341:45] + node _T_675 = bits(dccm_data_ecc_lo_any, 5, 5) @[el2_lib.scala 341:60] + node _T_676 = bits(dccm_rdata_lo_any, 25, 11) @[el2_lib.scala 341:68] + node _T_677 = bits(dccm_data_ecc_lo_any, 4, 4) @[el2_lib.scala 341:83] + node _T_678 = bits(dccm_rdata_lo_any, 10, 4) @[el2_lib.scala 341:91] + node _T_679 = bits(dccm_data_ecc_lo_any, 3, 3) @[el2_lib.scala 341:105] + node _T_680 = bits(dccm_rdata_lo_any, 3, 1) @[el2_lib.scala 341:113] + node _T_681 = bits(dccm_data_ecc_lo_any, 2, 2) @[el2_lib.scala 341:126] + node _T_682 = bits(dccm_rdata_lo_any, 0, 0) @[el2_lib.scala 341:134] + node _T_683 = bits(dccm_data_ecc_lo_any, 1, 0) @[el2_lib.scala 341:145] node _T_684 = cat(_T_682, _T_683) @[Cat.scala 29:58] node _T_685 = cat(_T_679, _T_680) @[Cat.scala 29:58] node _T_686 = cat(_T_685, _T_681) @[Cat.scala 29:58] @@ -1055,693 +1055,489 @@ circuit el2_lsu_ecc : node _T_691 = cat(_T_690, _T_675) @[Cat.scala 29:58] node _T_692 = cat(_T_691, _T_689) @[Cat.scala 29:58] node _T_693 = cat(_T_692, _T_687) @[Cat.scala 29:58] - node _T_694 = bits(single_ecc_error_lo_any, 0, 0) @[el2_lib.scala 333:49] - node _T_695 = cat(_T_594[1], _T_594[0]) @[el2_lib.scala 333:69] - node _T_696 = cat(_T_594[3], _T_594[2]) @[el2_lib.scala 333:69] - node _T_697 = cat(_T_696, _T_695) @[el2_lib.scala 333:69] - node _T_698 = cat(_T_594[5], _T_594[4]) @[el2_lib.scala 333:69] - node _T_699 = cat(_T_594[8], _T_594[7]) @[el2_lib.scala 333:69] - node _T_700 = cat(_T_699, _T_594[6]) @[el2_lib.scala 333:69] - node _T_701 = cat(_T_700, _T_698) @[el2_lib.scala 333:69] - node _T_702 = cat(_T_701, _T_697) @[el2_lib.scala 333:69] - node _T_703 = cat(_T_594[10], _T_594[9]) @[el2_lib.scala 333:69] - node _T_704 = cat(_T_594[13], _T_594[12]) @[el2_lib.scala 333:69] - node _T_705 = cat(_T_704, _T_594[11]) @[el2_lib.scala 333:69] - node _T_706 = cat(_T_705, _T_703) @[el2_lib.scala 333:69] - node _T_707 = cat(_T_594[15], _T_594[14]) @[el2_lib.scala 333:69] - node _T_708 = cat(_T_594[18], _T_594[17]) @[el2_lib.scala 333:69] - node _T_709 = cat(_T_708, _T_594[16]) @[el2_lib.scala 333:69] - node _T_710 = cat(_T_709, _T_707) @[el2_lib.scala 333:69] - node _T_711 = cat(_T_710, _T_706) @[el2_lib.scala 333:69] - node _T_712 = cat(_T_711, _T_702) @[el2_lib.scala 333:69] - node _T_713 = cat(_T_594[20], _T_594[19]) @[el2_lib.scala 333:69] - node _T_714 = cat(_T_594[23], _T_594[22]) @[el2_lib.scala 333:69] - node _T_715 = cat(_T_714, _T_594[21]) @[el2_lib.scala 333:69] - node _T_716 = cat(_T_715, _T_713) @[el2_lib.scala 333:69] - node _T_717 = cat(_T_594[25], _T_594[24]) @[el2_lib.scala 333:69] - node _T_718 = cat(_T_594[28], _T_594[27]) @[el2_lib.scala 333:69] - node _T_719 = cat(_T_718, _T_594[26]) @[el2_lib.scala 333:69] - node _T_720 = cat(_T_719, _T_717) @[el2_lib.scala 333:69] - node _T_721 = cat(_T_720, _T_716) @[el2_lib.scala 333:69] - node _T_722 = cat(_T_594[30], _T_594[29]) @[el2_lib.scala 333:69] - node _T_723 = cat(_T_594[33], _T_594[32]) @[el2_lib.scala 333:69] - node _T_724 = cat(_T_723, _T_594[31]) @[el2_lib.scala 333:69] - node _T_725 = cat(_T_724, _T_722) @[el2_lib.scala 333:69] - node _T_726 = cat(_T_594[35], _T_594[34]) @[el2_lib.scala 333:69] - node _T_727 = cat(_T_594[38], _T_594[37]) @[el2_lib.scala 333:69] - node _T_728 = cat(_T_727, _T_594[36]) @[el2_lib.scala 333:69] - node _T_729 = cat(_T_728, _T_726) @[el2_lib.scala 333:69] - node _T_730 = cat(_T_729, _T_725) @[el2_lib.scala 333:69] - node _T_731 = cat(_T_730, _T_721) @[el2_lib.scala 333:69] - node _T_732 = cat(_T_731, _T_712) @[el2_lib.scala 333:69] - node _T_733 = xor(_T_732, _T_693) @[el2_lib.scala 333:76] - node _T_734 = mux(_T_694, _T_733, _T_693) @[el2_lib.scala 333:31] - node _T_735 = bits(_T_734, 37, 32) @[el2_lib.scala 335:37] - node _T_736 = bits(_T_734, 30, 16) @[el2_lib.scala 335:61] - node _T_737 = bits(_T_734, 14, 8) @[el2_lib.scala 335:86] - node _T_738 = bits(_T_734, 6, 4) @[el2_lib.scala 335:110] - node _T_739 = bits(_T_734, 2, 2) @[el2_lib.scala 335:133] + node _T_694 = bits(single_ecc_error_lo_any, 0, 0) @[el2_lib.scala 342:49] + node _T_695 = cat(_T_594[1], _T_594[0]) @[el2_lib.scala 342:69] + node _T_696 = cat(_T_594[3], _T_594[2]) @[el2_lib.scala 342:69] + node _T_697 = cat(_T_696, _T_695) @[el2_lib.scala 342:69] + node _T_698 = cat(_T_594[5], _T_594[4]) @[el2_lib.scala 342:69] + node _T_699 = cat(_T_594[8], _T_594[7]) @[el2_lib.scala 342:69] + node _T_700 = cat(_T_699, _T_594[6]) @[el2_lib.scala 342:69] + node _T_701 = cat(_T_700, _T_698) @[el2_lib.scala 342:69] + node _T_702 = cat(_T_701, _T_697) @[el2_lib.scala 342:69] + node _T_703 = cat(_T_594[10], _T_594[9]) @[el2_lib.scala 342:69] + node _T_704 = cat(_T_594[13], _T_594[12]) @[el2_lib.scala 342:69] + node _T_705 = cat(_T_704, _T_594[11]) @[el2_lib.scala 342:69] + node _T_706 = cat(_T_705, _T_703) @[el2_lib.scala 342:69] + node _T_707 = cat(_T_594[15], _T_594[14]) @[el2_lib.scala 342:69] + node _T_708 = cat(_T_594[18], _T_594[17]) @[el2_lib.scala 342:69] + node _T_709 = cat(_T_708, _T_594[16]) @[el2_lib.scala 342:69] + node _T_710 = cat(_T_709, _T_707) @[el2_lib.scala 342:69] + node _T_711 = cat(_T_710, _T_706) @[el2_lib.scala 342:69] + node _T_712 = cat(_T_711, _T_702) @[el2_lib.scala 342:69] + node _T_713 = cat(_T_594[20], _T_594[19]) @[el2_lib.scala 342:69] + node _T_714 = cat(_T_594[23], _T_594[22]) @[el2_lib.scala 342:69] + node _T_715 = cat(_T_714, _T_594[21]) @[el2_lib.scala 342:69] + node _T_716 = cat(_T_715, _T_713) @[el2_lib.scala 342:69] + node _T_717 = cat(_T_594[25], _T_594[24]) @[el2_lib.scala 342:69] + node _T_718 = cat(_T_594[28], _T_594[27]) @[el2_lib.scala 342:69] + node _T_719 = cat(_T_718, _T_594[26]) @[el2_lib.scala 342:69] + node _T_720 = cat(_T_719, _T_717) @[el2_lib.scala 342:69] + node _T_721 = cat(_T_720, _T_716) @[el2_lib.scala 342:69] + node _T_722 = cat(_T_594[30], _T_594[29]) @[el2_lib.scala 342:69] + node _T_723 = cat(_T_594[33], _T_594[32]) @[el2_lib.scala 342:69] + node _T_724 = cat(_T_723, _T_594[31]) @[el2_lib.scala 342:69] + node _T_725 = cat(_T_724, _T_722) @[el2_lib.scala 342:69] + node _T_726 = cat(_T_594[35], _T_594[34]) @[el2_lib.scala 342:69] + node _T_727 = cat(_T_594[38], _T_594[37]) @[el2_lib.scala 342:69] + node _T_728 = cat(_T_727, _T_594[36]) @[el2_lib.scala 342:69] + node _T_729 = cat(_T_728, _T_726) @[el2_lib.scala 342:69] + node _T_730 = cat(_T_729, _T_725) @[el2_lib.scala 342:69] + node _T_731 = cat(_T_730, _T_721) @[el2_lib.scala 342:69] + node _T_732 = cat(_T_731, _T_712) @[el2_lib.scala 342:69] + node _T_733 = xor(_T_732, _T_693) @[el2_lib.scala 342:76] + node _T_734 = mux(_T_694, _T_733, _T_693) @[el2_lib.scala 342:31] + node _T_735 = bits(_T_734, 37, 32) @[el2_lib.scala 344:37] + node _T_736 = bits(_T_734, 30, 16) @[el2_lib.scala 344:61] + node _T_737 = bits(_T_734, 14, 8) @[el2_lib.scala 344:86] + node _T_738 = bits(_T_734, 6, 4) @[el2_lib.scala 344:110] + node _T_739 = bits(_T_734, 2, 2) @[el2_lib.scala 344:133] node _T_740 = cat(_T_738, _T_739) @[Cat.scala 29:58] node _T_741 = cat(_T_735, _T_736) @[Cat.scala 29:58] node _T_742 = cat(_T_741, _T_737) @[Cat.scala 29:58] node sec_data_lo_any = cat(_T_742, _T_740) @[Cat.scala 29:58] - node _T_743 = bits(_T_734, 38, 38) @[el2_lib.scala 336:39] - node _T_744 = bits(_T_586, 6, 0) @[el2_lib.scala 336:56] - node _T_745 = eq(_T_744, UInt<7>("h040")) @[el2_lib.scala 336:62] - node _T_746 = xor(_T_743, _T_745) @[el2_lib.scala 336:44] - node _T_747 = bits(_T_734, 31, 31) @[el2_lib.scala 336:102] - node _T_748 = bits(_T_734, 15, 15) @[el2_lib.scala 336:124] - node _T_749 = bits(_T_734, 7, 7) @[el2_lib.scala 336:146] - node _T_750 = bits(_T_734, 3, 3) @[el2_lib.scala 336:167] - node _T_751 = bits(_T_734, 1, 0) @[el2_lib.scala 336:188] + node _T_743 = bits(_T_734, 38, 38) @[el2_lib.scala 345:39] + node _T_744 = bits(_T_586, 6, 0) @[el2_lib.scala 345:56] + node _T_745 = eq(_T_744, UInt<7>("h040")) @[el2_lib.scala 345:62] + node _T_746 = xor(_T_743, _T_745) @[el2_lib.scala 345:44] + node _T_747 = bits(_T_734, 31, 31) @[el2_lib.scala 345:102] + node _T_748 = bits(_T_734, 15, 15) @[el2_lib.scala 345:124] + node _T_749 = bits(_T_734, 7, 7) @[el2_lib.scala 345:146] + node _T_750 = bits(_T_734, 3, 3) @[el2_lib.scala 345:167] + node _T_751 = bits(_T_734, 1, 0) @[el2_lib.scala 345:188] node _T_752 = cat(_T_749, _T_750) @[Cat.scala 29:58] node _T_753 = cat(_T_752, _T_751) @[Cat.scala 29:58] node _T_754 = cat(_T_746, _T_747) @[Cat.scala 29:58] node _T_755 = cat(_T_754, _T_748) @[Cat.scala 29:58] node ecc_out_lo_nc = cat(_T_755, _T_753) @[Cat.scala 29:58] - wire _T_756 : UInt<1>[18] @[el2_lib.scala 270:18] - wire _T_757 : UInt<1>[18] @[el2_lib.scala 271:18] - wire _T_758 : UInt<1>[18] @[el2_lib.scala 272:18] - wire _T_759 : UInt<1>[15] @[el2_lib.scala 273:18] - wire _T_760 : UInt<1>[15] @[el2_lib.scala 274:18] - wire _T_761 : UInt<1>[6] @[el2_lib.scala 275:18] - node _T_762 = bits(dccm_wdata_lo_any, 0, 0) @[el2_lib.scala 280:36] - _T_756[0] <= _T_762 @[el2_lib.scala 280:30] - node _T_763 = bits(dccm_wdata_lo_any, 0, 0) @[el2_lib.scala 281:36] - _T_757[0] <= _T_763 @[el2_lib.scala 281:30] - node _T_764 = bits(dccm_wdata_lo_any, 1, 1) @[el2_lib.scala 280:36] - _T_756[1] <= _T_764 @[el2_lib.scala 280:30] - node _T_765 = bits(dccm_wdata_lo_any, 1, 1) @[el2_lib.scala 282:36] - _T_758[0] <= _T_765 @[el2_lib.scala 282:30] - node _T_766 = bits(dccm_wdata_lo_any, 2, 2) @[el2_lib.scala 281:36] - _T_757[1] <= _T_766 @[el2_lib.scala 281:30] - node _T_767 = bits(dccm_wdata_lo_any, 2, 2) @[el2_lib.scala 282:36] - _T_758[1] <= _T_767 @[el2_lib.scala 282:30] - node _T_768 = bits(dccm_wdata_lo_any, 3, 3) @[el2_lib.scala 280:36] - _T_756[2] <= _T_768 @[el2_lib.scala 280:30] - node _T_769 = bits(dccm_wdata_lo_any, 3, 3) @[el2_lib.scala 281:36] - _T_757[2] <= _T_769 @[el2_lib.scala 281:30] - node _T_770 = bits(dccm_wdata_lo_any, 3, 3) @[el2_lib.scala 282:36] - _T_758[2] <= _T_770 @[el2_lib.scala 282:30] - node _T_771 = bits(dccm_wdata_lo_any, 4, 4) @[el2_lib.scala 280:36] - _T_756[3] <= _T_771 @[el2_lib.scala 280:30] - node _T_772 = bits(dccm_wdata_lo_any, 4, 4) @[el2_lib.scala 283:36] - _T_759[0] <= _T_772 @[el2_lib.scala 283:30] - node _T_773 = bits(dccm_wdata_lo_any, 5, 5) @[el2_lib.scala 281:36] - _T_757[3] <= _T_773 @[el2_lib.scala 281:30] - node _T_774 = bits(dccm_wdata_lo_any, 5, 5) @[el2_lib.scala 283:36] - _T_759[1] <= _T_774 @[el2_lib.scala 283:30] - node _T_775 = bits(dccm_wdata_lo_any, 6, 6) @[el2_lib.scala 280:36] - _T_756[4] <= _T_775 @[el2_lib.scala 280:30] - node _T_776 = bits(dccm_wdata_lo_any, 6, 6) @[el2_lib.scala 281:36] - _T_757[4] <= _T_776 @[el2_lib.scala 281:30] - node _T_777 = bits(dccm_wdata_lo_any, 6, 6) @[el2_lib.scala 283:36] - _T_759[2] <= _T_777 @[el2_lib.scala 283:30] - node _T_778 = bits(dccm_wdata_lo_any, 7, 7) @[el2_lib.scala 282:36] - _T_758[3] <= _T_778 @[el2_lib.scala 282:30] - node _T_779 = bits(dccm_wdata_lo_any, 7, 7) @[el2_lib.scala 283:36] - _T_759[3] <= _T_779 @[el2_lib.scala 283:30] - node _T_780 = bits(dccm_wdata_lo_any, 8, 8) @[el2_lib.scala 280:36] - _T_756[5] <= _T_780 @[el2_lib.scala 280:30] - node _T_781 = bits(dccm_wdata_lo_any, 8, 8) @[el2_lib.scala 282:36] - _T_758[4] <= _T_781 @[el2_lib.scala 282:30] - node _T_782 = bits(dccm_wdata_lo_any, 8, 8) @[el2_lib.scala 283:36] - _T_759[4] <= _T_782 @[el2_lib.scala 283:30] - node _T_783 = bits(dccm_wdata_lo_any, 9, 9) @[el2_lib.scala 281:36] - _T_757[5] <= _T_783 @[el2_lib.scala 281:30] - node _T_784 = bits(dccm_wdata_lo_any, 9, 9) @[el2_lib.scala 282:36] - _T_758[5] <= _T_784 @[el2_lib.scala 282:30] - node _T_785 = bits(dccm_wdata_lo_any, 9, 9) @[el2_lib.scala 283:36] - _T_759[5] <= _T_785 @[el2_lib.scala 283:30] - node _T_786 = bits(dccm_wdata_lo_any, 10, 10) @[el2_lib.scala 280:36] - _T_756[6] <= _T_786 @[el2_lib.scala 280:30] - node _T_787 = bits(dccm_wdata_lo_any, 10, 10) @[el2_lib.scala 281:36] - _T_757[6] <= _T_787 @[el2_lib.scala 281:30] - node _T_788 = bits(dccm_wdata_lo_any, 10, 10) @[el2_lib.scala 282:36] - _T_758[6] <= _T_788 @[el2_lib.scala 282:30] - node _T_789 = bits(dccm_wdata_lo_any, 10, 10) @[el2_lib.scala 283:36] - _T_759[6] <= _T_789 @[el2_lib.scala 283:30] - node _T_790 = bits(dccm_wdata_lo_any, 11, 11) @[el2_lib.scala 280:36] - _T_756[7] <= _T_790 @[el2_lib.scala 280:30] - node _T_791 = bits(dccm_wdata_lo_any, 11, 11) @[el2_lib.scala 284:36] - _T_760[0] <= _T_791 @[el2_lib.scala 284:30] - node _T_792 = bits(dccm_wdata_lo_any, 12, 12) @[el2_lib.scala 281:36] - _T_757[7] <= _T_792 @[el2_lib.scala 281:30] - node _T_793 = bits(dccm_wdata_lo_any, 12, 12) @[el2_lib.scala 284:36] - _T_760[1] <= _T_793 @[el2_lib.scala 284:30] - node _T_794 = bits(dccm_wdata_lo_any, 13, 13) @[el2_lib.scala 280:36] - _T_756[8] <= _T_794 @[el2_lib.scala 280:30] - node _T_795 = bits(dccm_wdata_lo_any, 13, 13) @[el2_lib.scala 281:36] - _T_757[8] <= _T_795 @[el2_lib.scala 281:30] - node _T_796 = bits(dccm_wdata_lo_any, 13, 13) @[el2_lib.scala 284:36] - _T_760[2] <= _T_796 @[el2_lib.scala 284:30] - node _T_797 = bits(dccm_wdata_lo_any, 14, 14) @[el2_lib.scala 282:36] - _T_758[7] <= _T_797 @[el2_lib.scala 282:30] - node _T_798 = bits(dccm_wdata_lo_any, 14, 14) @[el2_lib.scala 284:36] - _T_760[3] <= _T_798 @[el2_lib.scala 284:30] - node _T_799 = bits(dccm_wdata_lo_any, 15, 15) @[el2_lib.scala 280:36] - _T_756[9] <= _T_799 @[el2_lib.scala 280:30] - node _T_800 = bits(dccm_wdata_lo_any, 15, 15) @[el2_lib.scala 282:36] - _T_758[8] <= _T_800 @[el2_lib.scala 282:30] - node _T_801 = bits(dccm_wdata_lo_any, 15, 15) @[el2_lib.scala 284:36] - _T_760[4] <= _T_801 @[el2_lib.scala 284:30] - node _T_802 = bits(dccm_wdata_lo_any, 16, 16) @[el2_lib.scala 281:36] - _T_757[9] <= _T_802 @[el2_lib.scala 281:30] - node _T_803 = bits(dccm_wdata_lo_any, 16, 16) @[el2_lib.scala 282:36] - _T_758[9] <= _T_803 @[el2_lib.scala 282:30] - node _T_804 = bits(dccm_wdata_lo_any, 16, 16) @[el2_lib.scala 284:36] - _T_760[5] <= _T_804 @[el2_lib.scala 284:30] - node _T_805 = bits(dccm_wdata_lo_any, 17, 17) @[el2_lib.scala 280:36] - _T_756[10] <= _T_805 @[el2_lib.scala 280:30] - node _T_806 = bits(dccm_wdata_lo_any, 17, 17) @[el2_lib.scala 281:36] - _T_757[10] <= _T_806 @[el2_lib.scala 281:30] - node _T_807 = bits(dccm_wdata_lo_any, 17, 17) @[el2_lib.scala 282:36] - _T_758[10] <= _T_807 @[el2_lib.scala 282:30] - node _T_808 = bits(dccm_wdata_lo_any, 17, 17) @[el2_lib.scala 284:36] - _T_760[6] <= _T_808 @[el2_lib.scala 284:30] - node _T_809 = bits(dccm_wdata_lo_any, 18, 18) @[el2_lib.scala 283:36] - _T_759[7] <= _T_809 @[el2_lib.scala 283:30] - node _T_810 = bits(dccm_wdata_lo_any, 18, 18) @[el2_lib.scala 284:36] - _T_760[7] <= _T_810 @[el2_lib.scala 284:30] - node _T_811 = bits(dccm_wdata_lo_any, 19, 19) @[el2_lib.scala 280:36] - _T_756[11] <= _T_811 @[el2_lib.scala 280:30] - node _T_812 = bits(dccm_wdata_lo_any, 19, 19) @[el2_lib.scala 283:36] - _T_759[8] <= _T_812 @[el2_lib.scala 283:30] - node _T_813 = bits(dccm_wdata_lo_any, 19, 19) @[el2_lib.scala 284:36] - _T_760[8] <= _T_813 @[el2_lib.scala 284:30] - node _T_814 = bits(dccm_wdata_lo_any, 20, 20) @[el2_lib.scala 281:36] - _T_757[11] <= _T_814 @[el2_lib.scala 281:30] - node _T_815 = bits(dccm_wdata_lo_any, 20, 20) @[el2_lib.scala 283:36] - _T_759[9] <= _T_815 @[el2_lib.scala 283:30] - node _T_816 = bits(dccm_wdata_lo_any, 20, 20) @[el2_lib.scala 284:36] - _T_760[9] <= _T_816 @[el2_lib.scala 284:30] - node _T_817 = bits(dccm_wdata_lo_any, 21, 21) @[el2_lib.scala 280:36] - _T_756[12] <= _T_817 @[el2_lib.scala 280:30] - node _T_818 = bits(dccm_wdata_lo_any, 21, 21) @[el2_lib.scala 281:36] - _T_757[12] <= _T_818 @[el2_lib.scala 281:30] - node _T_819 = bits(dccm_wdata_lo_any, 21, 21) @[el2_lib.scala 283:36] - _T_759[10] <= _T_819 @[el2_lib.scala 283:30] - node _T_820 = bits(dccm_wdata_lo_any, 21, 21) @[el2_lib.scala 284:36] - _T_760[10] <= _T_820 @[el2_lib.scala 284:30] - node _T_821 = bits(dccm_wdata_lo_any, 22, 22) @[el2_lib.scala 282:36] - _T_758[11] <= _T_821 @[el2_lib.scala 282:30] - node _T_822 = bits(dccm_wdata_lo_any, 22, 22) @[el2_lib.scala 283:36] - _T_759[11] <= _T_822 @[el2_lib.scala 283:30] - node _T_823 = bits(dccm_wdata_lo_any, 22, 22) @[el2_lib.scala 284:36] - _T_760[11] <= _T_823 @[el2_lib.scala 284:30] - node _T_824 = bits(dccm_wdata_lo_any, 23, 23) @[el2_lib.scala 280:36] - _T_756[13] <= _T_824 @[el2_lib.scala 280:30] - node _T_825 = bits(dccm_wdata_lo_any, 23, 23) @[el2_lib.scala 282:36] - _T_758[12] <= _T_825 @[el2_lib.scala 282:30] - node _T_826 = bits(dccm_wdata_lo_any, 23, 23) @[el2_lib.scala 283:36] - _T_759[12] <= _T_826 @[el2_lib.scala 283:30] - node _T_827 = bits(dccm_wdata_lo_any, 23, 23) @[el2_lib.scala 284:36] - _T_760[12] <= _T_827 @[el2_lib.scala 284:30] - node _T_828 = bits(dccm_wdata_lo_any, 24, 24) @[el2_lib.scala 281:36] - _T_757[13] <= _T_828 @[el2_lib.scala 281:30] - node _T_829 = bits(dccm_wdata_lo_any, 24, 24) @[el2_lib.scala 282:36] - _T_758[13] <= _T_829 @[el2_lib.scala 282:30] - node _T_830 = bits(dccm_wdata_lo_any, 24, 24) @[el2_lib.scala 283:36] - _T_759[13] <= _T_830 @[el2_lib.scala 283:30] - node _T_831 = bits(dccm_wdata_lo_any, 24, 24) @[el2_lib.scala 284:36] - _T_760[13] <= _T_831 @[el2_lib.scala 284:30] - node _T_832 = bits(dccm_wdata_lo_any, 25, 25) @[el2_lib.scala 280:36] - _T_756[14] <= _T_832 @[el2_lib.scala 280:30] - node _T_833 = bits(dccm_wdata_lo_any, 25, 25) @[el2_lib.scala 281:36] - _T_757[14] <= _T_833 @[el2_lib.scala 281:30] - node _T_834 = bits(dccm_wdata_lo_any, 25, 25) @[el2_lib.scala 282:36] - _T_758[14] <= _T_834 @[el2_lib.scala 282:30] - node _T_835 = bits(dccm_wdata_lo_any, 25, 25) @[el2_lib.scala 283:36] - _T_759[14] <= _T_835 @[el2_lib.scala 283:30] - node _T_836 = bits(dccm_wdata_lo_any, 25, 25) @[el2_lib.scala 284:36] - _T_760[14] <= _T_836 @[el2_lib.scala 284:30] - node _T_837 = bits(dccm_wdata_lo_any, 26, 26) @[el2_lib.scala 280:36] - _T_756[15] <= _T_837 @[el2_lib.scala 280:30] - node _T_838 = bits(dccm_wdata_lo_any, 26, 26) @[el2_lib.scala 285:36] - _T_761[0] <= _T_838 @[el2_lib.scala 285:30] - node _T_839 = bits(dccm_wdata_lo_any, 27, 27) @[el2_lib.scala 281:36] - _T_757[15] <= _T_839 @[el2_lib.scala 281:30] - node _T_840 = bits(dccm_wdata_lo_any, 27, 27) @[el2_lib.scala 285:36] - _T_761[1] <= _T_840 @[el2_lib.scala 285:30] - node _T_841 = bits(dccm_wdata_lo_any, 28, 28) @[el2_lib.scala 280:36] - _T_756[16] <= _T_841 @[el2_lib.scala 280:30] - node _T_842 = bits(dccm_wdata_lo_any, 28, 28) @[el2_lib.scala 281:36] - _T_757[16] <= _T_842 @[el2_lib.scala 281:30] - node _T_843 = bits(dccm_wdata_lo_any, 28, 28) @[el2_lib.scala 285:36] - _T_761[2] <= _T_843 @[el2_lib.scala 285:30] - node _T_844 = bits(dccm_wdata_lo_any, 29, 29) @[el2_lib.scala 282:36] - _T_758[15] <= _T_844 @[el2_lib.scala 282:30] - node _T_845 = bits(dccm_wdata_lo_any, 29, 29) @[el2_lib.scala 285:36] - _T_761[3] <= _T_845 @[el2_lib.scala 285:30] - node _T_846 = bits(dccm_wdata_lo_any, 30, 30) @[el2_lib.scala 280:36] - _T_756[17] <= _T_846 @[el2_lib.scala 280:30] - node _T_847 = bits(dccm_wdata_lo_any, 30, 30) @[el2_lib.scala 282:36] - _T_758[16] <= _T_847 @[el2_lib.scala 282:30] - node _T_848 = bits(dccm_wdata_lo_any, 30, 30) @[el2_lib.scala 285:36] - _T_761[4] <= _T_848 @[el2_lib.scala 285:30] - node _T_849 = bits(dccm_wdata_lo_any, 31, 31) @[el2_lib.scala 281:36] - _T_757[17] <= _T_849 @[el2_lib.scala 281:30] - node _T_850 = bits(dccm_wdata_lo_any, 31, 31) @[el2_lib.scala 282:36] - _T_758[17] <= _T_850 @[el2_lib.scala 282:30] - node _T_851 = bits(dccm_wdata_lo_any, 31, 31) @[el2_lib.scala 285:36] - _T_761[5] <= _T_851 @[el2_lib.scala 285:30] - node _T_852 = cat(_T_761[2], _T_761[1]) @[el2_lib.scala 287:22] - node _T_853 = cat(_T_852, _T_761[0]) @[el2_lib.scala 287:22] - node _T_854 = cat(_T_761[5], _T_761[4]) @[el2_lib.scala 287:22] - node _T_855 = cat(_T_854, _T_761[3]) @[el2_lib.scala 287:22] - node _T_856 = cat(_T_855, _T_853) @[el2_lib.scala 287:22] - node _T_857 = xorr(_T_856) @[el2_lib.scala 287:29] - node _T_858 = cat(_T_760[2], _T_760[1]) @[el2_lib.scala 287:39] - node _T_859 = cat(_T_858, _T_760[0]) @[el2_lib.scala 287:39] - node _T_860 = cat(_T_760[4], _T_760[3]) @[el2_lib.scala 287:39] - node _T_861 = cat(_T_760[6], _T_760[5]) @[el2_lib.scala 287:39] - node _T_862 = cat(_T_861, _T_860) @[el2_lib.scala 287:39] - node _T_863 = cat(_T_862, _T_859) @[el2_lib.scala 287:39] - node _T_864 = cat(_T_760[8], _T_760[7]) @[el2_lib.scala 287:39] - node _T_865 = cat(_T_760[10], _T_760[9]) @[el2_lib.scala 287:39] - node _T_866 = cat(_T_865, _T_864) @[el2_lib.scala 287:39] - node _T_867 = cat(_T_760[12], _T_760[11]) @[el2_lib.scala 287:39] - node _T_868 = cat(_T_760[14], _T_760[13]) @[el2_lib.scala 287:39] - node _T_869 = cat(_T_868, _T_867) @[el2_lib.scala 287:39] - node _T_870 = cat(_T_869, _T_866) @[el2_lib.scala 287:39] - node _T_871 = cat(_T_870, _T_863) @[el2_lib.scala 287:39] - node _T_872 = xorr(_T_871) @[el2_lib.scala 287:46] - node _T_873 = cat(_T_759[2], _T_759[1]) @[el2_lib.scala 287:56] - node _T_874 = cat(_T_873, _T_759[0]) @[el2_lib.scala 287:56] - node _T_875 = cat(_T_759[4], _T_759[3]) @[el2_lib.scala 287:56] - node _T_876 = cat(_T_759[6], _T_759[5]) @[el2_lib.scala 287:56] - node _T_877 = cat(_T_876, _T_875) @[el2_lib.scala 287:56] - node _T_878 = cat(_T_877, _T_874) @[el2_lib.scala 287:56] - node _T_879 = cat(_T_759[8], _T_759[7]) @[el2_lib.scala 287:56] - node _T_880 = cat(_T_759[10], _T_759[9]) @[el2_lib.scala 287:56] - node _T_881 = cat(_T_880, _T_879) @[el2_lib.scala 287:56] - node _T_882 = cat(_T_759[12], _T_759[11]) @[el2_lib.scala 287:56] - node _T_883 = cat(_T_759[14], _T_759[13]) @[el2_lib.scala 287:56] - node _T_884 = cat(_T_883, _T_882) @[el2_lib.scala 287:56] - node _T_885 = cat(_T_884, _T_881) @[el2_lib.scala 287:56] - node _T_886 = cat(_T_885, _T_878) @[el2_lib.scala 287:56] - node _T_887 = xorr(_T_886) @[el2_lib.scala 287:63] - node _T_888 = cat(_T_758[1], _T_758[0]) @[el2_lib.scala 287:73] - node _T_889 = cat(_T_758[3], _T_758[2]) @[el2_lib.scala 287:73] - node _T_890 = cat(_T_889, _T_888) @[el2_lib.scala 287:73] - node _T_891 = cat(_T_758[5], _T_758[4]) @[el2_lib.scala 287:73] - node _T_892 = cat(_T_758[8], _T_758[7]) @[el2_lib.scala 287:73] - node _T_893 = cat(_T_892, _T_758[6]) @[el2_lib.scala 287:73] - node _T_894 = cat(_T_893, _T_891) @[el2_lib.scala 287:73] - node _T_895 = cat(_T_894, _T_890) @[el2_lib.scala 287:73] - node _T_896 = cat(_T_758[10], _T_758[9]) @[el2_lib.scala 287:73] - node _T_897 = cat(_T_758[12], _T_758[11]) @[el2_lib.scala 287:73] - node _T_898 = cat(_T_897, _T_896) @[el2_lib.scala 287:73] - node _T_899 = cat(_T_758[14], _T_758[13]) @[el2_lib.scala 287:73] - node _T_900 = cat(_T_758[17], _T_758[16]) @[el2_lib.scala 287:73] - node _T_901 = cat(_T_900, _T_758[15]) @[el2_lib.scala 287:73] - node _T_902 = cat(_T_901, _T_899) @[el2_lib.scala 287:73] - node _T_903 = cat(_T_902, _T_898) @[el2_lib.scala 287:73] - node _T_904 = cat(_T_903, _T_895) @[el2_lib.scala 287:73] - node _T_905 = xorr(_T_904) @[el2_lib.scala 287:80] - node _T_906 = cat(_T_757[1], _T_757[0]) @[el2_lib.scala 287:90] - node _T_907 = cat(_T_757[3], _T_757[2]) @[el2_lib.scala 287:90] - node _T_908 = cat(_T_907, _T_906) @[el2_lib.scala 287:90] - node _T_909 = cat(_T_757[5], _T_757[4]) @[el2_lib.scala 287:90] - node _T_910 = cat(_T_757[8], _T_757[7]) @[el2_lib.scala 287:90] - node _T_911 = cat(_T_910, _T_757[6]) @[el2_lib.scala 287:90] - node _T_912 = cat(_T_911, _T_909) @[el2_lib.scala 287:90] - node _T_913 = cat(_T_912, _T_908) @[el2_lib.scala 287:90] - node _T_914 = cat(_T_757[10], _T_757[9]) @[el2_lib.scala 287:90] - node _T_915 = cat(_T_757[12], _T_757[11]) @[el2_lib.scala 287:90] - node _T_916 = cat(_T_915, _T_914) @[el2_lib.scala 287:90] - node _T_917 = cat(_T_757[14], _T_757[13]) @[el2_lib.scala 287:90] - node _T_918 = cat(_T_757[17], _T_757[16]) @[el2_lib.scala 287:90] - node _T_919 = cat(_T_918, _T_757[15]) @[el2_lib.scala 287:90] - node _T_920 = cat(_T_919, _T_917) @[el2_lib.scala 287:90] - node _T_921 = cat(_T_920, _T_916) @[el2_lib.scala 287:90] - node _T_922 = cat(_T_921, _T_913) @[el2_lib.scala 287:90] - node _T_923 = xorr(_T_922) @[el2_lib.scala 287:97] - node _T_924 = cat(_T_756[1], _T_756[0]) @[el2_lib.scala 287:107] - node _T_925 = cat(_T_756[3], _T_756[2]) @[el2_lib.scala 287:107] - node _T_926 = cat(_T_925, _T_924) @[el2_lib.scala 287:107] - node _T_927 = cat(_T_756[5], _T_756[4]) @[el2_lib.scala 287:107] - node _T_928 = cat(_T_756[8], _T_756[7]) @[el2_lib.scala 287:107] - node _T_929 = cat(_T_928, _T_756[6]) @[el2_lib.scala 287:107] - node _T_930 = cat(_T_929, _T_927) @[el2_lib.scala 287:107] - node _T_931 = cat(_T_930, _T_926) @[el2_lib.scala 287:107] - node _T_932 = cat(_T_756[10], _T_756[9]) @[el2_lib.scala 287:107] - node _T_933 = cat(_T_756[12], _T_756[11]) @[el2_lib.scala 287:107] - node _T_934 = cat(_T_933, _T_932) @[el2_lib.scala 287:107] - node _T_935 = cat(_T_756[14], _T_756[13]) @[el2_lib.scala 287:107] - node _T_936 = cat(_T_756[17], _T_756[16]) @[el2_lib.scala 287:107] - node _T_937 = cat(_T_936, _T_756[15]) @[el2_lib.scala 287:107] - node _T_938 = cat(_T_937, _T_935) @[el2_lib.scala 287:107] - node _T_939 = cat(_T_938, _T_934) @[el2_lib.scala 287:107] - node _T_940 = cat(_T_939, _T_931) @[el2_lib.scala 287:107] - node _T_941 = xorr(_T_940) @[el2_lib.scala 287:114] - node _T_942 = cat(_T_905, _T_923) @[Cat.scala 29:58] - node _T_943 = cat(_T_942, _T_941) @[Cat.scala 29:58] - node _T_944 = cat(_T_857, _T_872) @[Cat.scala 29:58] - node _T_945 = cat(_T_944, _T_887) @[Cat.scala 29:58] - node _T_946 = cat(_T_945, _T_943) @[Cat.scala 29:58] - node _T_947 = xorr(dccm_wdata_lo_any) @[el2_lib.scala 288:27] - node _T_948 = xorr(_T_946) @[el2_lib.scala 288:37] - node _T_949 = xor(_T_947, _T_948) @[el2_lib.scala 288:32] - node dccm_wdata_ecc_lo_any = cat(_T_949, _T_946) @[Cat.scala 29:58] - wire _T_950 : UInt<1>[18] @[el2_lib.scala 270:18] - wire _T_951 : UInt<1>[18] @[el2_lib.scala 271:18] - wire _T_952 : UInt<1>[18] @[el2_lib.scala 272:18] - wire _T_953 : UInt<1>[15] @[el2_lib.scala 273:18] - wire _T_954 : UInt<1>[15] @[el2_lib.scala 274:18] - wire _T_955 : UInt<1>[6] @[el2_lib.scala 275:18] - node _T_956 = bits(dccm_wdata_hi_any, 0, 0) @[el2_lib.scala 280:36] - _T_950[0] <= _T_956 @[el2_lib.scala 280:30] - node _T_957 = bits(dccm_wdata_hi_any, 0, 0) @[el2_lib.scala 281:36] - _T_951[0] <= _T_957 @[el2_lib.scala 281:30] - node _T_958 = bits(dccm_wdata_hi_any, 1, 1) @[el2_lib.scala 280:36] - _T_950[1] <= _T_958 @[el2_lib.scala 280:30] - node _T_959 = bits(dccm_wdata_hi_any, 1, 1) @[el2_lib.scala 282:36] - _T_952[0] <= _T_959 @[el2_lib.scala 282:30] - node _T_960 = bits(dccm_wdata_hi_any, 2, 2) @[el2_lib.scala 281:36] - _T_951[1] <= _T_960 @[el2_lib.scala 281:30] - node _T_961 = bits(dccm_wdata_hi_any, 2, 2) @[el2_lib.scala 282:36] - _T_952[1] <= _T_961 @[el2_lib.scala 282:30] - node _T_962 = bits(dccm_wdata_hi_any, 3, 3) @[el2_lib.scala 280:36] - _T_950[2] <= _T_962 @[el2_lib.scala 280:30] - node _T_963 = bits(dccm_wdata_hi_any, 3, 3) @[el2_lib.scala 281:36] - _T_951[2] <= _T_963 @[el2_lib.scala 281:30] - node _T_964 = bits(dccm_wdata_hi_any, 3, 3) @[el2_lib.scala 282:36] - _T_952[2] <= _T_964 @[el2_lib.scala 282:30] - node _T_965 = bits(dccm_wdata_hi_any, 4, 4) @[el2_lib.scala 280:36] - _T_950[3] <= _T_965 @[el2_lib.scala 280:30] - node _T_966 = bits(dccm_wdata_hi_any, 4, 4) @[el2_lib.scala 283:36] - _T_953[0] <= _T_966 @[el2_lib.scala 283:30] - node _T_967 = bits(dccm_wdata_hi_any, 5, 5) @[el2_lib.scala 281:36] - _T_951[3] <= _T_967 @[el2_lib.scala 281:30] - node _T_968 = bits(dccm_wdata_hi_any, 5, 5) @[el2_lib.scala 283:36] - _T_953[1] <= _T_968 @[el2_lib.scala 283:30] - node _T_969 = bits(dccm_wdata_hi_any, 6, 6) @[el2_lib.scala 280:36] - _T_950[4] <= _T_969 @[el2_lib.scala 280:30] - node _T_970 = bits(dccm_wdata_hi_any, 6, 6) @[el2_lib.scala 281:36] - _T_951[4] <= _T_970 @[el2_lib.scala 281:30] - node _T_971 = bits(dccm_wdata_hi_any, 6, 6) @[el2_lib.scala 283:36] - _T_953[2] <= _T_971 @[el2_lib.scala 283:30] - node _T_972 = bits(dccm_wdata_hi_any, 7, 7) @[el2_lib.scala 282:36] - _T_952[3] <= _T_972 @[el2_lib.scala 282:30] - node _T_973 = bits(dccm_wdata_hi_any, 7, 7) @[el2_lib.scala 283:36] - _T_953[3] <= _T_973 @[el2_lib.scala 283:30] - node _T_974 = bits(dccm_wdata_hi_any, 8, 8) @[el2_lib.scala 280:36] - _T_950[5] <= _T_974 @[el2_lib.scala 280:30] - node _T_975 = bits(dccm_wdata_hi_any, 8, 8) @[el2_lib.scala 282:36] - _T_952[4] <= _T_975 @[el2_lib.scala 282:30] - node _T_976 = bits(dccm_wdata_hi_any, 8, 8) @[el2_lib.scala 283:36] - _T_953[4] <= _T_976 @[el2_lib.scala 283:30] - node _T_977 = bits(dccm_wdata_hi_any, 9, 9) @[el2_lib.scala 281:36] - _T_951[5] <= _T_977 @[el2_lib.scala 281:30] - node _T_978 = bits(dccm_wdata_hi_any, 9, 9) @[el2_lib.scala 282:36] - _T_952[5] <= _T_978 @[el2_lib.scala 282:30] - node _T_979 = bits(dccm_wdata_hi_any, 9, 9) @[el2_lib.scala 283:36] - _T_953[5] <= _T_979 @[el2_lib.scala 283:30] - node _T_980 = bits(dccm_wdata_hi_any, 10, 10) @[el2_lib.scala 280:36] - _T_950[6] <= _T_980 @[el2_lib.scala 280:30] - node _T_981 = bits(dccm_wdata_hi_any, 10, 10) @[el2_lib.scala 281:36] - _T_951[6] <= _T_981 @[el2_lib.scala 281:30] - node _T_982 = bits(dccm_wdata_hi_any, 10, 10) @[el2_lib.scala 282:36] - _T_952[6] <= _T_982 @[el2_lib.scala 282:30] - node _T_983 = bits(dccm_wdata_hi_any, 10, 10) @[el2_lib.scala 283:36] - _T_953[6] <= _T_983 @[el2_lib.scala 283:30] - node _T_984 = bits(dccm_wdata_hi_any, 11, 11) @[el2_lib.scala 280:36] - _T_950[7] <= _T_984 @[el2_lib.scala 280:30] - node _T_985 = bits(dccm_wdata_hi_any, 11, 11) @[el2_lib.scala 284:36] - _T_954[0] <= _T_985 @[el2_lib.scala 284:30] - node _T_986 = bits(dccm_wdata_hi_any, 12, 12) @[el2_lib.scala 281:36] - _T_951[7] <= _T_986 @[el2_lib.scala 281:30] - node _T_987 = bits(dccm_wdata_hi_any, 12, 12) @[el2_lib.scala 284:36] - _T_954[1] <= _T_987 @[el2_lib.scala 284:30] - node _T_988 = bits(dccm_wdata_hi_any, 13, 13) @[el2_lib.scala 280:36] - _T_950[8] <= _T_988 @[el2_lib.scala 280:30] - node _T_989 = bits(dccm_wdata_hi_any, 13, 13) @[el2_lib.scala 281:36] - _T_951[8] <= _T_989 @[el2_lib.scala 281:30] - node _T_990 = bits(dccm_wdata_hi_any, 13, 13) @[el2_lib.scala 284:36] - _T_954[2] <= _T_990 @[el2_lib.scala 284:30] - node _T_991 = bits(dccm_wdata_hi_any, 14, 14) @[el2_lib.scala 282:36] - _T_952[7] <= _T_991 @[el2_lib.scala 282:30] - node _T_992 = bits(dccm_wdata_hi_any, 14, 14) @[el2_lib.scala 284:36] - _T_954[3] <= _T_992 @[el2_lib.scala 284:30] - node _T_993 = bits(dccm_wdata_hi_any, 15, 15) @[el2_lib.scala 280:36] - _T_950[9] <= _T_993 @[el2_lib.scala 280:30] - node _T_994 = bits(dccm_wdata_hi_any, 15, 15) @[el2_lib.scala 282:36] - _T_952[8] <= _T_994 @[el2_lib.scala 282:30] - node _T_995 = bits(dccm_wdata_hi_any, 15, 15) @[el2_lib.scala 284:36] - _T_954[4] <= _T_995 @[el2_lib.scala 284:30] - node _T_996 = bits(dccm_wdata_hi_any, 16, 16) @[el2_lib.scala 281:36] - _T_951[9] <= _T_996 @[el2_lib.scala 281:30] - node _T_997 = bits(dccm_wdata_hi_any, 16, 16) @[el2_lib.scala 282:36] - _T_952[9] <= _T_997 @[el2_lib.scala 282:30] - node _T_998 = bits(dccm_wdata_hi_any, 16, 16) @[el2_lib.scala 284:36] - _T_954[5] <= _T_998 @[el2_lib.scala 284:30] - node _T_999 = bits(dccm_wdata_hi_any, 17, 17) @[el2_lib.scala 280:36] - _T_950[10] <= _T_999 @[el2_lib.scala 280:30] - node _T_1000 = bits(dccm_wdata_hi_any, 17, 17) @[el2_lib.scala 281:36] - _T_951[10] <= _T_1000 @[el2_lib.scala 281:30] - node _T_1001 = bits(dccm_wdata_hi_any, 17, 17) @[el2_lib.scala 282:36] - _T_952[10] <= _T_1001 @[el2_lib.scala 282:30] - node _T_1002 = bits(dccm_wdata_hi_any, 17, 17) @[el2_lib.scala 284:36] - _T_954[6] <= _T_1002 @[el2_lib.scala 284:30] - node _T_1003 = bits(dccm_wdata_hi_any, 18, 18) @[el2_lib.scala 283:36] - _T_953[7] <= _T_1003 @[el2_lib.scala 283:30] - node _T_1004 = bits(dccm_wdata_hi_any, 18, 18) @[el2_lib.scala 284:36] - _T_954[7] <= _T_1004 @[el2_lib.scala 284:30] - node _T_1005 = bits(dccm_wdata_hi_any, 19, 19) @[el2_lib.scala 280:36] - _T_950[11] <= _T_1005 @[el2_lib.scala 280:30] - node _T_1006 = bits(dccm_wdata_hi_any, 19, 19) @[el2_lib.scala 283:36] - _T_953[8] <= _T_1006 @[el2_lib.scala 283:30] - node _T_1007 = bits(dccm_wdata_hi_any, 19, 19) @[el2_lib.scala 284:36] - _T_954[8] <= _T_1007 @[el2_lib.scala 284:30] - node _T_1008 = bits(dccm_wdata_hi_any, 20, 20) @[el2_lib.scala 281:36] - _T_951[11] <= _T_1008 @[el2_lib.scala 281:30] - node _T_1009 = bits(dccm_wdata_hi_any, 20, 20) @[el2_lib.scala 283:36] - _T_953[9] <= _T_1009 @[el2_lib.scala 283:30] - node _T_1010 = bits(dccm_wdata_hi_any, 20, 20) @[el2_lib.scala 284:36] - _T_954[9] <= _T_1010 @[el2_lib.scala 284:30] - node _T_1011 = bits(dccm_wdata_hi_any, 21, 21) @[el2_lib.scala 280:36] - _T_950[12] <= _T_1011 @[el2_lib.scala 280:30] - node _T_1012 = bits(dccm_wdata_hi_any, 21, 21) @[el2_lib.scala 281:36] - _T_951[12] <= _T_1012 @[el2_lib.scala 281:30] - node _T_1013 = bits(dccm_wdata_hi_any, 21, 21) @[el2_lib.scala 283:36] - _T_953[10] <= _T_1013 @[el2_lib.scala 283:30] - node _T_1014 = bits(dccm_wdata_hi_any, 21, 21) @[el2_lib.scala 284:36] - _T_954[10] <= _T_1014 @[el2_lib.scala 284:30] - node _T_1015 = bits(dccm_wdata_hi_any, 22, 22) @[el2_lib.scala 282:36] - _T_952[11] <= _T_1015 @[el2_lib.scala 282:30] - node _T_1016 = bits(dccm_wdata_hi_any, 22, 22) @[el2_lib.scala 283:36] - _T_953[11] <= _T_1016 @[el2_lib.scala 283:30] - node _T_1017 = bits(dccm_wdata_hi_any, 22, 22) @[el2_lib.scala 284:36] - _T_954[11] <= _T_1017 @[el2_lib.scala 284:30] - node _T_1018 = bits(dccm_wdata_hi_any, 23, 23) @[el2_lib.scala 280:36] - _T_950[13] <= _T_1018 @[el2_lib.scala 280:30] - node _T_1019 = bits(dccm_wdata_hi_any, 23, 23) @[el2_lib.scala 282:36] - _T_952[12] <= _T_1019 @[el2_lib.scala 282:30] - node _T_1020 = bits(dccm_wdata_hi_any, 23, 23) @[el2_lib.scala 283:36] - _T_953[12] <= _T_1020 @[el2_lib.scala 283:30] - node _T_1021 = bits(dccm_wdata_hi_any, 23, 23) @[el2_lib.scala 284:36] - _T_954[12] <= _T_1021 @[el2_lib.scala 284:30] - node _T_1022 = bits(dccm_wdata_hi_any, 24, 24) @[el2_lib.scala 281:36] - _T_951[13] <= _T_1022 @[el2_lib.scala 281:30] - node _T_1023 = bits(dccm_wdata_hi_any, 24, 24) @[el2_lib.scala 282:36] - _T_952[13] <= _T_1023 @[el2_lib.scala 282:30] - node _T_1024 = bits(dccm_wdata_hi_any, 24, 24) @[el2_lib.scala 283:36] - _T_953[13] <= _T_1024 @[el2_lib.scala 283:30] - node _T_1025 = bits(dccm_wdata_hi_any, 24, 24) @[el2_lib.scala 284:36] - _T_954[13] <= _T_1025 @[el2_lib.scala 284:30] - node _T_1026 = bits(dccm_wdata_hi_any, 25, 25) @[el2_lib.scala 280:36] - _T_950[14] <= _T_1026 @[el2_lib.scala 280:30] - node _T_1027 = bits(dccm_wdata_hi_any, 25, 25) @[el2_lib.scala 281:36] - _T_951[14] <= _T_1027 @[el2_lib.scala 281:30] - node _T_1028 = bits(dccm_wdata_hi_any, 25, 25) @[el2_lib.scala 282:36] - _T_952[14] <= _T_1028 @[el2_lib.scala 282:30] - node _T_1029 = bits(dccm_wdata_hi_any, 25, 25) @[el2_lib.scala 283:36] - _T_953[14] <= _T_1029 @[el2_lib.scala 283:30] - node _T_1030 = bits(dccm_wdata_hi_any, 25, 25) @[el2_lib.scala 284:36] - _T_954[14] <= _T_1030 @[el2_lib.scala 284:30] - node _T_1031 = bits(dccm_wdata_hi_any, 26, 26) @[el2_lib.scala 280:36] - _T_950[15] <= _T_1031 @[el2_lib.scala 280:30] - node _T_1032 = bits(dccm_wdata_hi_any, 26, 26) @[el2_lib.scala 285:36] - _T_955[0] <= _T_1032 @[el2_lib.scala 285:30] - node _T_1033 = bits(dccm_wdata_hi_any, 27, 27) @[el2_lib.scala 281:36] - _T_951[15] <= _T_1033 @[el2_lib.scala 281:30] - node _T_1034 = bits(dccm_wdata_hi_any, 27, 27) @[el2_lib.scala 285:36] - _T_955[1] <= _T_1034 @[el2_lib.scala 285:30] - node _T_1035 = bits(dccm_wdata_hi_any, 28, 28) @[el2_lib.scala 280:36] - _T_950[16] <= _T_1035 @[el2_lib.scala 280:30] - node _T_1036 = bits(dccm_wdata_hi_any, 28, 28) @[el2_lib.scala 281:36] - _T_951[16] <= _T_1036 @[el2_lib.scala 281:30] - node _T_1037 = bits(dccm_wdata_hi_any, 28, 28) @[el2_lib.scala 285:36] - _T_955[2] <= _T_1037 @[el2_lib.scala 285:30] - node _T_1038 = bits(dccm_wdata_hi_any, 29, 29) @[el2_lib.scala 282:36] - _T_952[15] <= _T_1038 @[el2_lib.scala 282:30] - node _T_1039 = bits(dccm_wdata_hi_any, 29, 29) @[el2_lib.scala 285:36] - _T_955[3] <= _T_1039 @[el2_lib.scala 285:30] - node _T_1040 = bits(dccm_wdata_hi_any, 30, 30) @[el2_lib.scala 280:36] - _T_950[17] <= _T_1040 @[el2_lib.scala 280:30] - node _T_1041 = bits(dccm_wdata_hi_any, 30, 30) @[el2_lib.scala 282:36] - _T_952[16] <= _T_1041 @[el2_lib.scala 282:30] - node _T_1042 = bits(dccm_wdata_hi_any, 30, 30) @[el2_lib.scala 285:36] - _T_955[4] <= _T_1042 @[el2_lib.scala 285:30] - node _T_1043 = bits(dccm_wdata_hi_any, 31, 31) @[el2_lib.scala 281:36] - _T_951[17] <= _T_1043 @[el2_lib.scala 281:30] - node _T_1044 = bits(dccm_wdata_hi_any, 31, 31) @[el2_lib.scala 282:36] - _T_952[17] <= _T_1044 @[el2_lib.scala 282:30] - node _T_1045 = bits(dccm_wdata_hi_any, 31, 31) @[el2_lib.scala 285:36] - _T_955[5] <= _T_1045 @[el2_lib.scala 285:30] - node _T_1046 = cat(_T_955[2], _T_955[1]) @[el2_lib.scala 287:22] - node _T_1047 = cat(_T_1046, _T_955[0]) @[el2_lib.scala 287:22] - node _T_1048 = cat(_T_955[5], _T_955[4]) @[el2_lib.scala 287:22] - node _T_1049 = cat(_T_1048, _T_955[3]) @[el2_lib.scala 287:22] - node _T_1050 = cat(_T_1049, _T_1047) @[el2_lib.scala 287:22] - node _T_1051 = xorr(_T_1050) @[el2_lib.scala 287:29] - node _T_1052 = cat(_T_954[2], _T_954[1]) @[el2_lib.scala 287:39] - node _T_1053 = cat(_T_1052, _T_954[0]) @[el2_lib.scala 287:39] - node _T_1054 = cat(_T_954[4], _T_954[3]) @[el2_lib.scala 287:39] - node _T_1055 = cat(_T_954[6], _T_954[5]) @[el2_lib.scala 287:39] - node _T_1056 = cat(_T_1055, _T_1054) @[el2_lib.scala 287:39] - node _T_1057 = cat(_T_1056, _T_1053) @[el2_lib.scala 287:39] - node _T_1058 = cat(_T_954[8], _T_954[7]) @[el2_lib.scala 287:39] - node _T_1059 = cat(_T_954[10], _T_954[9]) @[el2_lib.scala 287:39] - node _T_1060 = cat(_T_1059, _T_1058) @[el2_lib.scala 287:39] - node _T_1061 = cat(_T_954[12], _T_954[11]) @[el2_lib.scala 287:39] - node _T_1062 = cat(_T_954[14], _T_954[13]) @[el2_lib.scala 287:39] - node _T_1063 = cat(_T_1062, _T_1061) @[el2_lib.scala 287:39] - node _T_1064 = cat(_T_1063, _T_1060) @[el2_lib.scala 287:39] - node _T_1065 = cat(_T_1064, _T_1057) @[el2_lib.scala 287:39] - node _T_1066 = xorr(_T_1065) @[el2_lib.scala 287:46] - node _T_1067 = cat(_T_953[2], _T_953[1]) @[el2_lib.scala 287:56] - node _T_1068 = cat(_T_1067, _T_953[0]) @[el2_lib.scala 287:56] - node _T_1069 = cat(_T_953[4], _T_953[3]) @[el2_lib.scala 287:56] - node _T_1070 = cat(_T_953[6], _T_953[5]) @[el2_lib.scala 287:56] - node _T_1071 = cat(_T_1070, _T_1069) @[el2_lib.scala 287:56] - node _T_1072 = cat(_T_1071, _T_1068) @[el2_lib.scala 287:56] - node _T_1073 = cat(_T_953[8], _T_953[7]) @[el2_lib.scala 287:56] - node _T_1074 = cat(_T_953[10], _T_953[9]) @[el2_lib.scala 287:56] - node _T_1075 = cat(_T_1074, _T_1073) @[el2_lib.scala 287:56] - node _T_1076 = cat(_T_953[12], _T_953[11]) @[el2_lib.scala 287:56] - node _T_1077 = cat(_T_953[14], _T_953[13]) @[el2_lib.scala 287:56] - node _T_1078 = cat(_T_1077, _T_1076) @[el2_lib.scala 287:56] - node _T_1079 = cat(_T_1078, _T_1075) @[el2_lib.scala 287:56] - node _T_1080 = cat(_T_1079, _T_1072) @[el2_lib.scala 287:56] - node _T_1081 = xorr(_T_1080) @[el2_lib.scala 287:63] - node _T_1082 = cat(_T_952[1], _T_952[0]) @[el2_lib.scala 287:73] - node _T_1083 = cat(_T_952[3], _T_952[2]) @[el2_lib.scala 287:73] - node _T_1084 = cat(_T_1083, _T_1082) @[el2_lib.scala 287:73] - node _T_1085 = cat(_T_952[5], _T_952[4]) @[el2_lib.scala 287:73] - node _T_1086 = cat(_T_952[8], _T_952[7]) @[el2_lib.scala 287:73] - node _T_1087 = cat(_T_1086, _T_952[6]) @[el2_lib.scala 287:73] - node _T_1088 = cat(_T_1087, _T_1085) @[el2_lib.scala 287:73] - node _T_1089 = cat(_T_1088, _T_1084) @[el2_lib.scala 287:73] - node _T_1090 = cat(_T_952[10], _T_952[9]) @[el2_lib.scala 287:73] - node _T_1091 = cat(_T_952[12], _T_952[11]) @[el2_lib.scala 287:73] - node _T_1092 = cat(_T_1091, _T_1090) @[el2_lib.scala 287:73] - node _T_1093 = cat(_T_952[14], _T_952[13]) @[el2_lib.scala 287:73] - node _T_1094 = cat(_T_952[17], _T_952[16]) @[el2_lib.scala 287:73] - node _T_1095 = cat(_T_1094, _T_952[15]) @[el2_lib.scala 287:73] - node _T_1096 = cat(_T_1095, _T_1093) @[el2_lib.scala 287:73] - node _T_1097 = cat(_T_1096, _T_1092) @[el2_lib.scala 287:73] - node _T_1098 = cat(_T_1097, _T_1089) @[el2_lib.scala 287:73] - node _T_1099 = xorr(_T_1098) @[el2_lib.scala 287:80] - node _T_1100 = cat(_T_951[1], _T_951[0]) @[el2_lib.scala 287:90] - node _T_1101 = cat(_T_951[3], _T_951[2]) @[el2_lib.scala 287:90] - node _T_1102 = cat(_T_1101, _T_1100) @[el2_lib.scala 287:90] - node _T_1103 = cat(_T_951[5], _T_951[4]) @[el2_lib.scala 287:90] - node _T_1104 = cat(_T_951[8], _T_951[7]) @[el2_lib.scala 287:90] - node _T_1105 = cat(_T_1104, _T_951[6]) @[el2_lib.scala 287:90] - node _T_1106 = cat(_T_1105, _T_1103) @[el2_lib.scala 287:90] - node _T_1107 = cat(_T_1106, _T_1102) @[el2_lib.scala 287:90] - node _T_1108 = cat(_T_951[10], _T_951[9]) @[el2_lib.scala 287:90] - node _T_1109 = cat(_T_951[12], _T_951[11]) @[el2_lib.scala 287:90] - node _T_1110 = cat(_T_1109, _T_1108) @[el2_lib.scala 287:90] - node _T_1111 = cat(_T_951[14], _T_951[13]) @[el2_lib.scala 287:90] - node _T_1112 = cat(_T_951[17], _T_951[16]) @[el2_lib.scala 287:90] - node _T_1113 = cat(_T_1112, _T_951[15]) @[el2_lib.scala 287:90] - node _T_1114 = cat(_T_1113, _T_1111) @[el2_lib.scala 287:90] - node _T_1115 = cat(_T_1114, _T_1110) @[el2_lib.scala 287:90] - node _T_1116 = cat(_T_1115, _T_1107) @[el2_lib.scala 287:90] - node _T_1117 = xorr(_T_1116) @[el2_lib.scala 287:97] - node _T_1118 = cat(_T_950[1], _T_950[0]) @[el2_lib.scala 287:107] - node _T_1119 = cat(_T_950[3], _T_950[2]) @[el2_lib.scala 287:107] - node _T_1120 = cat(_T_1119, _T_1118) @[el2_lib.scala 287:107] - node _T_1121 = cat(_T_950[5], _T_950[4]) @[el2_lib.scala 287:107] - node _T_1122 = cat(_T_950[8], _T_950[7]) @[el2_lib.scala 287:107] - node _T_1123 = cat(_T_1122, _T_950[6]) @[el2_lib.scala 287:107] - node _T_1124 = cat(_T_1123, _T_1121) @[el2_lib.scala 287:107] - node _T_1125 = cat(_T_1124, _T_1120) @[el2_lib.scala 287:107] - node _T_1126 = cat(_T_950[10], _T_950[9]) @[el2_lib.scala 287:107] - node _T_1127 = cat(_T_950[12], _T_950[11]) @[el2_lib.scala 287:107] - node _T_1128 = cat(_T_1127, _T_1126) @[el2_lib.scala 287:107] - node _T_1129 = cat(_T_950[14], _T_950[13]) @[el2_lib.scala 287:107] - node _T_1130 = cat(_T_950[17], _T_950[16]) @[el2_lib.scala 287:107] - node _T_1131 = cat(_T_1130, _T_950[15]) @[el2_lib.scala 287:107] - node _T_1132 = cat(_T_1131, _T_1129) @[el2_lib.scala 287:107] - node _T_1133 = cat(_T_1132, _T_1128) @[el2_lib.scala 287:107] - node _T_1134 = cat(_T_1133, _T_1125) @[el2_lib.scala 287:107] - node _T_1135 = xorr(_T_1134) @[el2_lib.scala 287:114] - node _T_1136 = cat(_T_1099, _T_1117) @[Cat.scala 29:58] - node _T_1137 = cat(_T_1136, _T_1135) @[Cat.scala 29:58] - node _T_1138 = cat(_T_1051, _T_1066) @[Cat.scala 29:58] - node _T_1139 = cat(_T_1138, _T_1081) @[Cat.scala 29:58] - node _T_1140 = cat(_T_1139, _T_1137) @[Cat.scala 29:58] - node _T_1141 = xorr(dccm_wdata_hi_any) @[el2_lib.scala 288:27] - node _T_1142 = xorr(_T_1140) @[el2_lib.scala 288:37] - node _T_1143 = xor(_T_1141, _T_1142) @[el2_lib.scala 288:32] - node dccm_wdata_ecc_hi_any = cat(_T_1143, _T_1140) @[Cat.scala 29:58] - when UInt<1>("h00") : @[el2_lsu_ecc.scala 103:32] - node _T_1144 = bits(io.lsu_addr_r, 2, 2) @[el2_lsu_ecc.scala 104:35] - node _T_1145 = bits(io.end_addr_r, 2, 2) @[el2_lsu_ecc.scala 104:56] - node _T_1146 = neq(_T_1144, _T_1145) @[el2_lsu_ecc.scala 104:39] - ldst_dual_r <= _T_1146 @[el2_lsu_ecc.scala 104:19] - node _T_1147 = or(io.lsu_pkt_r.load, io.lsu_pkt_r.store) @[el2_lsu_ecc.scala 105:60] - node _T_1148 = and(io.lsu_pkt_r.valid, _T_1147) @[el2_lsu_ecc.scala 105:39] - node _T_1149 = and(_T_1148, io.addr_in_dccm_r) @[el2_lsu_ecc.scala 105:82] - node _T_1150 = and(_T_1149, io.lsu_dccm_rden_r) @[el2_lsu_ecc.scala 105:102] - is_ldst_r <= _T_1150 @[el2_lsu_ecc.scala 105:17] - node _T_1151 = eq(io.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[el2_lsu_ecc.scala 106:35] - node _T_1152 = and(is_ldst_r, _T_1151) @[el2_lsu_ecc.scala 106:33] - is_ldst_lo_r <= _T_1152 @[el2_lsu_ecc.scala 106:20] - node _T_1153 = or(ldst_dual_r, io.lsu_pkt_r.dma) @[el2_lsu_ecc.scala 107:48] - node _T_1154 = and(is_ldst_r, _T_1153) @[el2_lsu_ecc.scala 107:33] - node _T_1155 = eq(io.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[el2_lsu_ecc.scala 107:70] - node _T_1156 = and(_T_1154, _T_1155) @[el2_lsu_ecc.scala 107:68] - is_ldst_hi_r <= _T_1156 @[el2_lsu_ecc.scala 107:20] - is_ldst_hi_any <= is_ldst_hi_r @[el2_lsu_ecc.scala 108:23] - dccm_rdata_hi_any <= io.dccm_rdata_hi_r @[el2_lsu_ecc.scala 109:26] - dccm_data_ecc_hi_any <= io.dccm_data_ecc_hi_r @[el2_lsu_ecc.scala 110:28] - is_ldst_lo_any <= is_ldst_lo_r @[el2_lsu_ecc.scala 111:22] - dccm_rdata_lo_any <= io.dccm_rdata_lo_r @[el2_lsu_ecc.scala 112:27] - dccm_data_ecc_lo_any <= io.dccm_data_ecc_lo_r @[el2_lsu_ecc.scala 113:28] - io.sec_data_hi_r <= sec_data_hi_any @[el2_lsu_ecc.scala 114:24] - io.single_ecc_error_hi_r <= single_ecc_error_hi_any @[el2_lsu_ecc.scala 115:33] - double_ecc_error_hi_r <= double_ecc_error_hi_any @[el2_lsu_ecc.scala 116:30] - io.sec_data_lo_r <= sec_data_lo_any @[el2_lsu_ecc.scala 117:27] - io.single_ecc_error_lo_r <= single_ecc_error_lo_any @[el2_lsu_ecc.scala 118:33] - double_ecc_error_lo_r <= double_ecc_error_lo_any @[el2_lsu_ecc.scala 119:30] - node _T_1157 = or(io.single_ecc_error_hi_r, io.single_ecc_error_lo_r) @[el2_lsu_ecc.scala 120:61] - io.lsu_single_ecc_error_r <= _T_1157 @[el2_lsu_ecc.scala 120:33] - node _T_1158 = or(double_ecc_error_hi_r, double_ecc_error_lo_r) @[el2_lsu_ecc.scala 121:58] - io.lsu_double_ecc_error_r <= _T_1158 @[el2_lsu_ecc.scala 121:33] - skip @[el2_lsu_ecc.scala 103:32] + node _T_756 = bits(dccm_wdata_lo_any, 0, 0) @[el2_lib.scala 259:58] + node _T_757 = bits(dccm_wdata_lo_any, 1, 1) @[el2_lib.scala 259:58] + node _T_758 = bits(dccm_wdata_lo_any, 3, 3) @[el2_lib.scala 259:58] + node _T_759 = bits(dccm_wdata_lo_any, 4, 4) @[el2_lib.scala 259:58] + node _T_760 = bits(dccm_wdata_lo_any, 6, 6) @[el2_lib.scala 259:58] + node _T_761 = bits(dccm_wdata_lo_any, 8, 8) @[el2_lib.scala 259:58] + node _T_762 = bits(dccm_wdata_lo_any, 10, 10) @[el2_lib.scala 259:58] + node _T_763 = bits(dccm_wdata_lo_any, 11, 11) @[el2_lib.scala 259:58] + node _T_764 = bits(dccm_wdata_lo_any, 13, 13) @[el2_lib.scala 259:58] + node _T_765 = bits(dccm_wdata_lo_any, 15, 15) @[el2_lib.scala 259:58] + node _T_766 = bits(dccm_wdata_lo_any, 17, 17) @[el2_lib.scala 259:58] + node _T_767 = bits(dccm_wdata_lo_any, 19, 19) @[el2_lib.scala 259:58] + node _T_768 = bits(dccm_wdata_lo_any, 21, 21) @[el2_lib.scala 259:58] + node _T_769 = bits(dccm_wdata_lo_any, 23, 23) @[el2_lib.scala 259:58] + node _T_770 = bits(dccm_wdata_lo_any, 25, 25) @[el2_lib.scala 259:58] + node _T_771 = bits(dccm_wdata_lo_any, 26, 26) @[el2_lib.scala 259:58] + node _T_772 = bits(dccm_wdata_lo_any, 28, 28) @[el2_lib.scala 259:58] + node _T_773 = bits(dccm_wdata_lo_any, 30, 30) @[el2_lib.scala 259:58] + node _T_774 = xor(_T_756, _T_757) @[el2_lib.scala 259:74] + node _T_775 = xor(_T_774, _T_758) @[el2_lib.scala 259:74] + node _T_776 = xor(_T_775, _T_759) @[el2_lib.scala 259:74] + node _T_777 = xor(_T_776, _T_760) @[el2_lib.scala 259:74] + node _T_778 = xor(_T_777, _T_761) @[el2_lib.scala 259:74] + node _T_779 = xor(_T_778, _T_762) @[el2_lib.scala 259:74] + node _T_780 = xor(_T_779, _T_763) @[el2_lib.scala 259:74] + node _T_781 = xor(_T_780, _T_764) @[el2_lib.scala 259:74] + node _T_782 = xor(_T_781, _T_765) @[el2_lib.scala 259:74] + node _T_783 = xor(_T_782, _T_766) @[el2_lib.scala 259:74] + node _T_784 = xor(_T_783, _T_767) @[el2_lib.scala 259:74] + node _T_785 = xor(_T_784, _T_768) @[el2_lib.scala 259:74] + node _T_786 = xor(_T_785, _T_769) @[el2_lib.scala 259:74] + node _T_787 = xor(_T_786, _T_770) @[el2_lib.scala 259:74] + node _T_788 = xor(_T_787, _T_771) @[el2_lib.scala 259:74] + node _T_789 = xor(_T_788, _T_772) @[el2_lib.scala 259:74] + node _T_790 = xor(_T_789, _T_773) @[el2_lib.scala 259:74] + node _T_791 = bits(dccm_wdata_lo_any, 0, 0) @[el2_lib.scala 259:58] + node _T_792 = bits(dccm_wdata_lo_any, 2, 2) @[el2_lib.scala 259:58] + node _T_793 = bits(dccm_wdata_lo_any, 3, 3) @[el2_lib.scala 259:58] + node _T_794 = bits(dccm_wdata_lo_any, 5, 5) @[el2_lib.scala 259:58] + node _T_795 = bits(dccm_wdata_lo_any, 6, 6) @[el2_lib.scala 259:58] + node _T_796 = bits(dccm_wdata_lo_any, 9, 9) @[el2_lib.scala 259:58] + node _T_797 = bits(dccm_wdata_lo_any, 10, 10) @[el2_lib.scala 259:58] + node _T_798 = bits(dccm_wdata_lo_any, 12, 12) @[el2_lib.scala 259:58] + node _T_799 = bits(dccm_wdata_lo_any, 13, 13) @[el2_lib.scala 259:58] + node _T_800 = bits(dccm_wdata_lo_any, 16, 16) @[el2_lib.scala 259:58] + node _T_801 = bits(dccm_wdata_lo_any, 17, 17) @[el2_lib.scala 259:58] + node _T_802 = bits(dccm_wdata_lo_any, 20, 20) @[el2_lib.scala 259:58] + node _T_803 = bits(dccm_wdata_lo_any, 21, 21) @[el2_lib.scala 259:58] + node _T_804 = bits(dccm_wdata_lo_any, 24, 24) @[el2_lib.scala 259:58] + node _T_805 = bits(dccm_wdata_lo_any, 25, 25) @[el2_lib.scala 259:58] + node _T_806 = bits(dccm_wdata_lo_any, 27, 27) @[el2_lib.scala 259:58] + node _T_807 = bits(dccm_wdata_lo_any, 28, 28) @[el2_lib.scala 259:58] + node _T_808 = bits(dccm_wdata_lo_any, 31, 31) @[el2_lib.scala 259:58] + node _T_809 = xor(_T_791, _T_792) @[el2_lib.scala 259:74] + node _T_810 = xor(_T_809, _T_793) @[el2_lib.scala 259:74] + node _T_811 = xor(_T_810, _T_794) @[el2_lib.scala 259:74] + node _T_812 = xor(_T_811, _T_795) @[el2_lib.scala 259:74] + node _T_813 = xor(_T_812, _T_796) @[el2_lib.scala 259:74] + node _T_814 = xor(_T_813, _T_797) @[el2_lib.scala 259:74] + node _T_815 = xor(_T_814, _T_798) @[el2_lib.scala 259:74] + node _T_816 = xor(_T_815, _T_799) @[el2_lib.scala 259:74] + node _T_817 = xor(_T_816, _T_800) @[el2_lib.scala 259:74] + node _T_818 = xor(_T_817, _T_801) @[el2_lib.scala 259:74] + node _T_819 = xor(_T_818, _T_802) @[el2_lib.scala 259:74] + node _T_820 = xor(_T_819, _T_803) @[el2_lib.scala 259:74] + node _T_821 = xor(_T_820, _T_804) @[el2_lib.scala 259:74] + node _T_822 = xor(_T_821, _T_805) @[el2_lib.scala 259:74] + node _T_823 = xor(_T_822, _T_806) @[el2_lib.scala 259:74] + node _T_824 = xor(_T_823, _T_807) @[el2_lib.scala 259:74] + node _T_825 = xor(_T_824, _T_808) @[el2_lib.scala 259:74] + node _T_826 = bits(dccm_wdata_lo_any, 1, 1) @[el2_lib.scala 259:58] + node _T_827 = bits(dccm_wdata_lo_any, 2, 2) @[el2_lib.scala 259:58] + node _T_828 = bits(dccm_wdata_lo_any, 3, 3) @[el2_lib.scala 259:58] + node _T_829 = bits(dccm_wdata_lo_any, 7, 7) @[el2_lib.scala 259:58] + node _T_830 = bits(dccm_wdata_lo_any, 8, 8) @[el2_lib.scala 259:58] + node _T_831 = bits(dccm_wdata_lo_any, 9, 9) @[el2_lib.scala 259:58] + node _T_832 = bits(dccm_wdata_lo_any, 10, 10) @[el2_lib.scala 259:58] + node _T_833 = bits(dccm_wdata_lo_any, 14, 14) @[el2_lib.scala 259:58] + node _T_834 = bits(dccm_wdata_lo_any, 15, 15) @[el2_lib.scala 259:58] + node _T_835 = bits(dccm_wdata_lo_any, 16, 16) @[el2_lib.scala 259:58] + node _T_836 = bits(dccm_wdata_lo_any, 17, 17) @[el2_lib.scala 259:58] + node _T_837 = bits(dccm_wdata_lo_any, 22, 22) @[el2_lib.scala 259:58] + node _T_838 = bits(dccm_wdata_lo_any, 23, 23) @[el2_lib.scala 259:58] + node _T_839 = bits(dccm_wdata_lo_any, 24, 24) @[el2_lib.scala 259:58] + node _T_840 = bits(dccm_wdata_lo_any, 25, 25) @[el2_lib.scala 259:58] + node _T_841 = bits(dccm_wdata_lo_any, 29, 29) @[el2_lib.scala 259:58] + node _T_842 = bits(dccm_wdata_lo_any, 30, 30) @[el2_lib.scala 259:58] + node _T_843 = bits(dccm_wdata_lo_any, 31, 31) @[el2_lib.scala 259:58] + node _T_844 = xor(_T_826, _T_827) @[el2_lib.scala 259:74] + node _T_845 = xor(_T_844, _T_828) @[el2_lib.scala 259:74] + node _T_846 = xor(_T_845, _T_829) @[el2_lib.scala 259:74] + node _T_847 = xor(_T_846, _T_830) @[el2_lib.scala 259:74] + node _T_848 = xor(_T_847, _T_831) @[el2_lib.scala 259:74] + node _T_849 = xor(_T_848, _T_832) @[el2_lib.scala 259:74] + node _T_850 = xor(_T_849, _T_833) @[el2_lib.scala 259:74] + node _T_851 = xor(_T_850, _T_834) @[el2_lib.scala 259:74] + node _T_852 = xor(_T_851, _T_835) @[el2_lib.scala 259:74] + node _T_853 = xor(_T_852, _T_836) @[el2_lib.scala 259:74] + node _T_854 = xor(_T_853, _T_837) @[el2_lib.scala 259:74] + node _T_855 = xor(_T_854, _T_838) @[el2_lib.scala 259:74] + node _T_856 = xor(_T_855, _T_839) @[el2_lib.scala 259:74] + node _T_857 = xor(_T_856, _T_840) @[el2_lib.scala 259:74] + node _T_858 = xor(_T_857, _T_841) @[el2_lib.scala 259:74] + node _T_859 = xor(_T_858, _T_842) @[el2_lib.scala 259:74] + node _T_860 = xor(_T_859, _T_843) @[el2_lib.scala 259:74] + node _T_861 = bits(dccm_wdata_lo_any, 4, 4) @[el2_lib.scala 259:58] + node _T_862 = bits(dccm_wdata_lo_any, 5, 5) @[el2_lib.scala 259:58] + node _T_863 = bits(dccm_wdata_lo_any, 6, 6) @[el2_lib.scala 259:58] + node _T_864 = bits(dccm_wdata_lo_any, 7, 7) @[el2_lib.scala 259:58] + node _T_865 = bits(dccm_wdata_lo_any, 8, 8) @[el2_lib.scala 259:58] + node _T_866 = bits(dccm_wdata_lo_any, 9, 9) @[el2_lib.scala 259:58] + node _T_867 = bits(dccm_wdata_lo_any, 10, 10) @[el2_lib.scala 259:58] + node _T_868 = bits(dccm_wdata_lo_any, 18, 18) @[el2_lib.scala 259:58] + node _T_869 = bits(dccm_wdata_lo_any, 19, 19) @[el2_lib.scala 259:58] + node _T_870 = bits(dccm_wdata_lo_any, 20, 20) @[el2_lib.scala 259:58] + node _T_871 = bits(dccm_wdata_lo_any, 21, 21) @[el2_lib.scala 259:58] + node _T_872 = bits(dccm_wdata_lo_any, 22, 22) @[el2_lib.scala 259:58] + node _T_873 = bits(dccm_wdata_lo_any, 23, 23) @[el2_lib.scala 259:58] + node _T_874 = bits(dccm_wdata_lo_any, 24, 24) @[el2_lib.scala 259:58] + node _T_875 = bits(dccm_wdata_lo_any, 25, 25) @[el2_lib.scala 259:58] + node _T_876 = xor(_T_861, _T_862) @[el2_lib.scala 259:74] + node _T_877 = xor(_T_876, _T_863) @[el2_lib.scala 259:74] + node _T_878 = xor(_T_877, _T_864) @[el2_lib.scala 259:74] + node _T_879 = xor(_T_878, _T_865) @[el2_lib.scala 259:74] + node _T_880 = xor(_T_879, _T_866) @[el2_lib.scala 259:74] + node _T_881 = xor(_T_880, _T_867) @[el2_lib.scala 259:74] + node _T_882 = xor(_T_881, _T_868) @[el2_lib.scala 259:74] + node _T_883 = xor(_T_882, _T_869) @[el2_lib.scala 259:74] + node _T_884 = xor(_T_883, _T_870) @[el2_lib.scala 259:74] + node _T_885 = xor(_T_884, _T_871) @[el2_lib.scala 259:74] + node _T_886 = xor(_T_885, _T_872) @[el2_lib.scala 259:74] + node _T_887 = xor(_T_886, _T_873) @[el2_lib.scala 259:74] + node _T_888 = xor(_T_887, _T_874) @[el2_lib.scala 259:74] + node _T_889 = xor(_T_888, _T_875) @[el2_lib.scala 259:74] + node _T_890 = bits(dccm_wdata_lo_any, 11, 11) @[el2_lib.scala 259:58] + node _T_891 = bits(dccm_wdata_lo_any, 12, 12) @[el2_lib.scala 259:58] + node _T_892 = bits(dccm_wdata_lo_any, 13, 13) @[el2_lib.scala 259:58] + node _T_893 = bits(dccm_wdata_lo_any, 14, 14) @[el2_lib.scala 259:58] + node _T_894 = bits(dccm_wdata_lo_any, 15, 15) @[el2_lib.scala 259:58] + node _T_895 = bits(dccm_wdata_lo_any, 16, 16) @[el2_lib.scala 259:58] + node _T_896 = bits(dccm_wdata_lo_any, 17, 17) @[el2_lib.scala 259:58] + node _T_897 = bits(dccm_wdata_lo_any, 18, 18) @[el2_lib.scala 259:58] + node _T_898 = bits(dccm_wdata_lo_any, 19, 19) @[el2_lib.scala 259:58] + node _T_899 = bits(dccm_wdata_lo_any, 20, 20) @[el2_lib.scala 259:58] + node _T_900 = bits(dccm_wdata_lo_any, 21, 21) @[el2_lib.scala 259:58] + node _T_901 = bits(dccm_wdata_lo_any, 22, 22) @[el2_lib.scala 259:58] + node _T_902 = bits(dccm_wdata_lo_any, 23, 23) @[el2_lib.scala 259:58] + node _T_903 = bits(dccm_wdata_lo_any, 24, 24) @[el2_lib.scala 259:58] + node _T_904 = bits(dccm_wdata_lo_any, 25, 25) @[el2_lib.scala 259:58] + node _T_905 = xor(_T_890, _T_891) @[el2_lib.scala 259:74] + node _T_906 = xor(_T_905, _T_892) @[el2_lib.scala 259:74] + node _T_907 = xor(_T_906, _T_893) @[el2_lib.scala 259:74] + node _T_908 = xor(_T_907, _T_894) @[el2_lib.scala 259:74] + node _T_909 = xor(_T_908, _T_895) @[el2_lib.scala 259:74] + node _T_910 = xor(_T_909, _T_896) @[el2_lib.scala 259:74] + node _T_911 = xor(_T_910, _T_897) @[el2_lib.scala 259:74] + node _T_912 = xor(_T_911, _T_898) @[el2_lib.scala 259:74] + node _T_913 = xor(_T_912, _T_899) @[el2_lib.scala 259:74] + node _T_914 = xor(_T_913, _T_900) @[el2_lib.scala 259:74] + node _T_915 = xor(_T_914, _T_901) @[el2_lib.scala 259:74] + node _T_916 = xor(_T_915, _T_902) @[el2_lib.scala 259:74] + node _T_917 = xor(_T_916, _T_903) @[el2_lib.scala 259:74] + node _T_918 = xor(_T_917, _T_904) @[el2_lib.scala 259:74] + node _T_919 = bits(dccm_wdata_lo_any, 26, 26) @[el2_lib.scala 259:58] + node _T_920 = bits(dccm_wdata_lo_any, 27, 27) @[el2_lib.scala 259:58] + node _T_921 = bits(dccm_wdata_lo_any, 28, 28) @[el2_lib.scala 259:58] + node _T_922 = bits(dccm_wdata_lo_any, 29, 29) @[el2_lib.scala 259:58] + node _T_923 = bits(dccm_wdata_lo_any, 30, 30) @[el2_lib.scala 259:58] + node _T_924 = bits(dccm_wdata_lo_any, 31, 31) @[el2_lib.scala 259:58] + node _T_925 = xor(_T_919, _T_920) @[el2_lib.scala 259:74] + node _T_926 = xor(_T_925, _T_921) @[el2_lib.scala 259:74] + node _T_927 = xor(_T_926, _T_922) @[el2_lib.scala 259:74] + node _T_928 = xor(_T_927, _T_923) @[el2_lib.scala 259:74] + node _T_929 = xor(_T_928, _T_924) @[el2_lib.scala 259:74] + node _T_930 = cat(_T_860, _T_825) @[Cat.scala 29:58] + node _T_931 = cat(_T_930, _T_790) @[Cat.scala 29:58] + node _T_932 = cat(_T_929, _T_918) @[Cat.scala 29:58] + node _T_933 = cat(_T_932, _T_889) @[Cat.scala 29:58] + node _T_934 = cat(_T_933, _T_931) @[Cat.scala 29:58] + node _T_935 = xorr(dccm_wdata_lo_any) @[el2_lib.scala 267:13] + node _T_936 = xorr(_T_934) @[el2_lib.scala 267:23] + node _T_937 = xor(_T_935, _T_936) @[el2_lib.scala 267:18] + node dccm_wdata_ecc_lo_any = cat(_T_937, _T_934) @[Cat.scala 29:58] + node _T_938 = bits(dccm_wdata_hi_any, 0, 0) @[el2_lib.scala 259:58] + node _T_939 = bits(dccm_wdata_hi_any, 1, 1) @[el2_lib.scala 259:58] + node _T_940 = bits(dccm_wdata_hi_any, 3, 3) @[el2_lib.scala 259:58] + node _T_941 = bits(dccm_wdata_hi_any, 4, 4) @[el2_lib.scala 259:58] + node _T_942 = bits(dccm_wdata_hi_any, 6, 6) @[el2_lib.scala 259:58] + node _T_943 = bits(dccm_wdata_hi_any, 8, 8) @[el2_lib.scala 259:58] + node _T_944 = bits(dccm_wdata_hi_any, 10, 10) @[el2_lib.scala 259:58] + node _T_945 = bits(dccm_wdata_hi_any, 11, 11) @[el2_lib.scala 259:58] + node _T_946 = bits(dccm_wdata_hi_any, 13, 13) @[el2_lib.scala 259:58] + node _T_947 = bits(dccm_wdata_hi_any, 15, 15) @[el2_lib.scala 259:58] + node _T_948 = bits(dccm_wdata_hi_any, 17, 17) @[el2_lib.scala 259:58] + node _T_949 = bits(dccm_wdata_hi_any, 19, 19) @[el2_lib.scala 259:58] + node _T_950 = bits(dccm_wdata_hi_any, 21, 21) @[el2_lib.scala 259:58] + node _T_951 = bits(dccm_wdata_hi_any, 23, 23) @[el2_lib.scala 259:58] + node _T_952 = bits(dccm_wdata_hi_any, 25, 25) @[el2_lib.scala 259:58] + node _T_953 = bits(dccm_wdata_hi_any, 26, 26) @[el2_lib.scala 259:58] + node _T_954 = bits(dccm_wdata_hi_any, 28, 28) @[el2_lib.scala 259:58] + node _T_955 = bits(dccm_wdata_hi_any, 30, 30) @[el2_lib.scala 259:58] + node _T_956 = xor(_T_938, _T_939) @[el2_lib.scala 259:74] + node _T_957 = xor(_T_956, _T_940) @[el2_lib.scala 259:74] + node _T_958 = xor(_T_957, _T_941) @[el2_lib.scala 259:74] + node _T_959 = xor(_T_958, _T_942) @[el2_lib.scala 259:74] + node _T_960 = xor(_T_959, _T_943) @[el2_lib.scala 259:74] + node _T_961 = xor(_T_960, _T_944) @[el2_lib.scala 259:74] + node _T_962 = xor(_T_961, _T_945) @[el2_lib.scala 259:74] + node _T_963 = xor(_T_962, _T_946) @[el2_lib.scala 259:74] + node _T_964 = xor(_T_963, _T_947) @[el2_lib.scala 259:74] + node _T_965 = xor(_T_964, _T_948) @[el2_lib.scala 259:74] + node _T_966 = xor(_T_965, _T_949) @[el2_lib.scala 259:74] + node _T_967 = xor(_T_966, _T_950) @[el2_lib.scala 259:74] + node _T_968 = xor(_T_967, _T_951) @[el2_lib.scala 259:74] + node _T_969 = xor(_T_968, _T_952) @[el2_lib.scala 259:74] + node _T_970 = xor(_T_969, _T_953) @[el2_lib.scala 259:74] + node _T_971 = xor(_T_970, _T_954) @[el2_lib.scala 259:74] + node _T_972 = xor(_T_971, _T_955) @[el2_lib.scala 259:74] + node _T_973 = bits(dccm_wdata_hi_any, 0, 0) @[el2_lib.scala 259:58] + node _T_974 = bits(dccm_wdata_hi_any, 2, 2) @[el2_lib.scala 259:58] + node _T_975 = bits(dccm_wdata_hi_any, 3, 3) @[el2_lib.scala 259:58] + node _T_976 = bits(dccm_wdata_hi_any, 5, 5) @[el2_lib.scala 259:58] + node _T_977 = bits(dccm_wdata_hi_any, 6, 6) @[el2_lib.scala 259:58] + node _T_978 = bits(dccm_wdata_hi_any, 9, 9) @[el2_lib.scala 259:58] + node _T_979 = bits(dccm_wdata_hi_any, 10, 10) @[el2_lib.scala 259:58] + node _T_980 = bits(dccm_wdata_hi_any, 12, 12) @[el2_lib.scala 259:58] + node _T_981 = bits(dccm_wdata_hi_any, 13, 13) @[el2_lib.scala 259:58] + node _T_982 = bits(dccm_wdata_hi_any, 16, 16) @[el2_lib.scala 259:58] + node _T_983 = bits(dccm_wdata_hi_any, 17, 17) @[el2_lib.scala 259:58] + node _T_984 = bits(dccm_wdata_hi_any, 20, 20) @[el2_lib.scala 259:58] + node _T_985 = bits(dccm_wdata_hi_any, 21, 21) @[el2_lib.scala 259:58] + node _T_986 = bits(dccm_wdata_hi_any, 24, 24) @[el2_lib.scala 259:58] + node _T_987 = bits(dccm_wdata_hi_any, 25, 25) @[el2_lib.scala 259:58] + node _T_988 = bits(dccm_wdata_hi_any, 27, 27) @[el2_lib.scala 259:58] + node _T_989 = bits(dccm_wdata_hi_any, 28, 28) @[el2_lib.scala 259:58] + node _T_990 = bits(dccm_wdata_hi_any, 31, 31) @[el2_lib.scala 259:58] + node _T_991 = xor(_T_973, _T_974) @[el2_lib.scala 259:74] + node _T_992 = xor(_T_991, _T_975) @[el2_lib.scala 259:74] + node _T_993 = xor(_T_992, _T_976) @[el2_lib.scala 259:74] + node _T_994 = xor(_T_993, _T_977) @[el2_lib.scala 259:74] + node _T_995 = xor(_T_994, _T_978) @[el2_lib.scala 259:74] + node _T_996 = xor(_T_995, _T_979) @[el2_lib.scala 259:74] + node _T_997 = xor(_T_996, _T_980) @[el2_lib.scala 259:74] + node _T_998 = xor(_T_997, _T_981) @[el2_lib.scala 259:74] + node _T_999 = xor(_T_998, _T_982) @[el2_lib.scala 259:74] + node _T_1000 = xor(_T_999, _T_983) @[el2_lib.scala 259:74] + node _T_1001 = xor(_T_1000, _T_984) @[el2_lib.scala 259:74] + node _T_1002 = xor(_T_1001, _T_985) @[el2_lib.scala 259:74] + node _T_1003 = xor(_T_1002, _T_986) @[el2_lib.scala 259:74] + node _T_1004 = xor(_T_1003, _T_987) @[el2_lib.scala 259:74] + node _T_1005 = xor(_T_1004, _T_988) @[el2_lib.scala 259:74] + node _T_1006 = xor(_T_1005, _T_989) @[el2_lib.scala 259:74] + node _T_1007 = xor(_T_1006, _T_990) @[el2_lib.scala 259:74] + node _T_1008 = bits(dccm_wdata_hi_any, 1, 1) @[el2_lib.scala 259:58] + node _T_1009 = bits(dccm_wdata_hi_any, 2, 2) @[el2_lib.scala 259:58] + node _T_1010 = bits(dccm_wdata_hi_any, 3, 3) @[el2_lib.scala 259:58] + node _T_1011 = bits(dccm_wdata_hi_any, 7, 7) @[el2_lib.scala 259:58] + node _T_1012 = bits(dccm_wdata_hi_any, 8, 8) @[el2_lib.scala 259:58] + node _T_1013 = bits(dccm_wdata_hi_any, 9, 9) @[el2_lib.scala 259:58] + node _T_1014 = bits(dccm_wdata_hi_any, 10, 10) @[el2_lib.scala 259:58] + node _T_1015 = bits(dccm_wdata_hi_any, 14, 14) @[el2_lib.scala 259:58] + node _T_1016 = bits(dccm_wdata_hi_any, 15, 15) @[el2_lib.scala 259:58] + node _T_1017 = bits(dccm_wdata_hi_any, 16, 16) @[el2_lib.scala 259:58] + node _T_1018 = bits(dccm_wdata_hi_any, 17, 17) @[el2_lib.scala 259:58] + node _T_1019 = bits(dccm_wdata_hi_any, 22, 22) @[el2_lib.scala 259:58] + node _T_1020 = bits(dccm_wdata_hi_any, 23, 23) @[el2_lib.scala 259:58] + node _T_1021 = bits(dccm_wdata_hi_any, 24, 24) @[el2_lib.scala 259:58] + node _T_1022 = bits(dccm_wdata_hi_any, 25, 25) @[el2_lib.scala 259:58] + node _T_1023 = bits(dccm_wdata_hi_any, 29, 29) @[el2_lib.scala 259:58] + node _T_1024 = bits(dccm_wdata_hi_any, 30, 30) @[el2_lib.scala 259:58] + node _T_1025 = bits(dccm_wdata_hi_any, 31, 31) @[el2_lib.scala 259:58] + node _T_1026 = xor(_T_1008, _T_1009) @[el2_lib.scala 259:74] + node _T_1027 = xor(_T_1026, _T_1010) @[el2_lib.scala 259:74] + node _T_1028 = xor(_T_1027, _T_1011) @[el2_lib.scala 259:74] + node _T_1029 = xor(_T_1028, _T_1012) @[el2_lib.scala 259:74] + node _T_1030 = xor(_T_1029, _T_1013) @[el2_lib.scala 259:74] + node _T_1031 = xor(_T_1030, _T_1014) @[el2_lib.scala 259:74] + node _T_1032 = xor(_T_1031, _T_1015) @[el2_lib.scala 259:74] + node _T_1033 = xor(_T_1032, _T_1016) @[el2_lib.scala 259:74] + node _T_1034 = xor(_T_1033, _T_1017) @[el2_lib.scala 259:74] + node _T_1035 = xor(_T_1034, _T_1018) @[el2_lib.scala 259:74] + node _T_1036 = xor(_T_1035, _T_1019) @[el2_lib.scala 259:74] + node _T_1037 = xor(_T_1036, _T_1020) @[el2_lib.scala 259:74] + node _T_1038 = xor(_T_1037, _T_1021) @[el2_lib.scala 259:74] + node _T_1039 = xor(_T_1038, _T_1022) @[el2_lib.scala 259:74] + node _T_1040 = xor(_T_1039, _T_1023) @[el2_lib.scala 259:74] + node _T_1041 = xor(_T_1040, _T_1024) @[el2_lib.scala 259:74] + node _T_1042 = xor(_T_1041, _T_1025) @[el2_lib.scala 259:74] + node _T_1043 = bits(dccm_wdata_hi_any, 4, 4) @[el2_lib.scala 259:58] + node _T_1044 = bits(dccm_wdata_hi_any, 5, 5) @[el2_lib.scala 259:58] + node _T_1045 = bits(dccm_wdata_hi_any, 6, 6) @[el2_lib.scala 259:58] + node _T_1046 = bits(dccm_wdata_hi_any, 7, 7) @[el2_lib.scala 259:58] + node _T_1047 = bits(dccm_wdata_hi_any, 8, 8) @[el2_lib.scala 259:58] + node _T_1048 = bits(dccm_wdata_hi_any, 9, 9) @[el2_lib.scala 259:58] + node _T_1049 = bits(dccm_wdata_hi_any, 10, 10) @[el2_lib.scala 259:58] + node _T_1050 = bits(dccm_wdata_hi_any, 18, 18) @[el2_lib.scala 259:58] + node _T_1051 = bits(dccm_wdata_hi_any, 19, 19) @[el2_lib.scala 259:58] + node _T_1052 = bits(dccm_wdata_hi_any, 20, 20) @[el2_lib.scala 259:58] + node _T_1053 = bits(dccm_wdata_hi_any, 21, 21) @[el2_lib.scala 259:58] + node _T_1054 = bits(dccm_wdata_hi_any, 22, 22) @[el2_lib.scala 259:58] + node _T_1055 = bits(dccm_wdata_hi_any, 23, 23) @[el2_lib.scala 259:58] + node _T_1056 = bits(dccm_wdata_hi_any, 24, 24) @[el2_lib.scala 259:58] + node _T_1057 = bits(dccm_wdata_hi_any, 25, 25) @[el2_lib.scala 259:58] + node _T_1058 = xor(_T_1043, _T_1044) @[el2_lib.scala 259:74] + node _T_1059 = xor(_T_1058, _T_1045) @[el2_lib.scala 259:74] + node _T_1060 = xor(_T_1059, _T_1046) @[el2_lib.scala 259:74] + node _T_1061 = xor(_T_1060, _T_1047) @[el2_lib.scala 259:74] + node _T_1062 = xor(_T_1061, _T_1048) @[el2_lib.scala 259:74] + node _T_1063 = xor(_T_1062, _T_1049) @[el2_lib.scala 259:74] + node _T_1064 = xor(_T_1063, _T_1050) @[el2_lib.scala 259:74] + node _T_1065 = xor(_T_1064, _T_1051) @[el2_lib.scala 259:74] + node _T_1066 = xor(_T_1065, _T_1052) @[el2_lib.scala 259:74] + node _T_1067 = xor(_T_1066, _T_1053) @[el2_lib.scala 259:74] + node _T_1068 = xor(_T_1067, _T_1054) @[el2_lib.scala 259:74] + node _T_1069 = xor(_T_1068, _T_1055) @[el2_lib.scala 259:74] + node _T_1070 = xor(_T_1069, _T_1056) @[el2_lib.scala 259:74] + node _T_1071 = xor(_T_1070, _T_1057) @[el2_lib.scala 259:74] + node _T_1072 = bits(dccm_wdata_hi_any, 11, 11) @[el2_lib.scala 259:58] + node _T_1073 = bits(dccm_wdata_hi_any, 12, 12) @[el2_lib.scala 259:58] + node _T_1074 = bits(dccm_wdata_hi_any, 13, 13) @[el2_lib.scala 259:58] + node _T_1075 = bits(dccm_wdata_hi_any, 14, 14) @[el2_lib.scala 259:58] + node _T_1076 = bits(dccm_wdata_hi_any, 15, 15) @[el2_lib.scala 259:58] + node _T_1077 = bits(dccm_wdata_hi_any, 16, 16) @[el2_lib.scala 259:58] + node _T_1078 = bits(dccm_wdata_hi_any, 17, 17) @[el2_lib.scala 259:58] + node _T_1079 = bits(dccm_wdata_hi_any, 18, 18) @[el2_lib.scala 259:58] + node _T_1080 = bits(dccm_wdata_hi_any, 19, 19) @[el2_lib.scala 259:58] + node _T_1081 = bits(dccm_wdata_hi_any, 20, 20) @[el2_lib.scala 259:58] + node _T_1082 = bits(dccm_wdata_hi_any, 21, 21) @[el2_lib.scala 259:58] + node _T_1083 = bits(dccm_wdata_hi_any, 22, 22) @[el2_lib.scala 259:58] + node _T_1084 = bits(dccm_wdata_hi_any, 23, 23) @[el2_lib.scala 259:58] + node _T_1085 = bits(dccm_wdata_hi_any, 24, 24) @[el2_lib.scala 259:58] + node _T_1086 = bits(dccm_wdata_hi_any, 25, 25) @[el2_lib.scala 259:58] + node _T_1087 = xor(_T_1072, _T_1073) @[el2_lib.scala 259:74] + node _T_1088 = xor(_T_1087, _T_1074) @[el2_lib.scala 259:74] + node _T_1089 = xor(_T_1088, _T_1075) @[el2_lib.scala 259:74] + node _T_1090 = xor(_T_1089, _T_1076) @[el2_lib.scala 259:74] + node _T_1091 = xor(_T_1090, _T_1077) @[el2_lib.scala 259:74] + node _T_1092 = xor(_T_1091, _T_1078) @[el2_lib.scala 259:74] + node _T_1093 = xor(_T_1092, _T_1079) @[el2_lib.scala 259:74] + node _T_1094 = xor(_T_1093, _T_1080) @[el2_lib.scala 259:74] + node _T_1095 = xor(_T_1094, _T_1081) @[el2_lib.scala 259:74] + node _T_1096 = xor(_T_1095, _T_1082) @[el2_lib.scala 259:74] + node _T_1097 = xor(_T_1096, _T_1083) @[el2_lib.scala 259:74] + node _T_1098 = xor(_T_1097, _T_1084) @[el2_lib.scala 259:74] + node _T_1099 = xor(_T_1098, _T_1085) @[el2_lib.scala 259:74] + node _T_1100 = xor(_T_1099, _T_1086) @[el2_lib.scala 259:74] + node _T_1101 = bits(dccm_wdata_hi_any, 26, 26) @[el2_lib.scala 259:58] + node _T_1102 = bits(dccm_wdata_hi_any, 27, 27) @[el2_lib.scala 259:58] + node _T_1103 = bits(dccm_wdata_hi_any, 28, 28) @[el2_lib.scala 259:58] + node _T_1104 = bits(dccm_wdata_hi_any, 29, 29) @[el2_lib.scala 259:58] + node _T_1105 = bits(dccm_wdata_hi_any, 30, 30) @[el2_lib.scala 259:58] + node _T_1106 = bits(dccm_wdata_hi_any, 31, 31) @[el2_lib.scala 259:58] + node _T_1107 = xor(_T_1101, _T_1102) @[el2_lib.scala 259:74] + node _T_1108 = xor(_T_1107, _T_1103) @[el2_lib.scala 259:74] + node _T_1109 = xor(_T_1108, _T_1104) @[el2_lib.scala 259:74] + node _T_1110 = xor(_T_1109, _T_1105) @[el2_lib.scala 259:74] + node _T_1111 = xor(_T_1110, _T_1106) @[el2_lib.scala 259:74] + node _T_1112 = cat(_T_1042, _T_1007) @[Cat.scala 29:58] + node _T_1113 = cat(_T_1112, _T_972) @[Cat.scala 29:58] + node _T_1114 = cat(_T_1111, _T_1100) @[Cat.scala 29:58] + node _T_1115 = cat(_T_1114, _T_1071) @[Cat.scala 29:58] + node _T_1116 = cat(_T_1115, _T_1113) @[Cat.scala 29:58] + node _T_1117 = xorr(dccm_wdata_hi_any) @[el2_lib.scala 267:13] + node _T_1118 = xorr(_T_1116) @[el2_lib.scala 267:23] + node _T_1119 = xor(_T_1117, _T_1118) @[el2_lib.scala 267:18] + node dccm_wdata_ecc_hi_any = cat(_T_1119, _T_1116) @[Cat.scala 29:58] + when UInt<1>("h00") : @[el2_lsu_ecc.scala 103:30] + node _T_1120 = bits(io.lsu_addr_r, 2, 2) @[el2_lsu_ecc.scala 104:33] + node _T_1121 = bits(io.end_addr_r, 2, 2) @[el2_lsu_ecc.scala 104:54] + node _T_1122 = neq(_T_1120, _T_1121) @[el2_lsu_ecc.scala 104:37] + ldst_dual_r <= _T_1122 @[el2_lsu_ecc.scala 104:17] + node _T_1123 = or(io.lsu_pkt_r.bits.load, io.lsu_pkt_r.bits.store) @[el2_lsu_ecc.scala 105:63] + node _T_1124 = and(io.lsu_pkt_r.valid, _T_1123) @[el2_lsu_ecc.scala 105:37] + node _T_1125 = and(_T_1124, io.addr_in_dccm_r) @[el2_lsu_ecc.scala 105:90] + node _T_1126 = and(_T_1125, io.lsu_dccm_rden_r) @[el2_lsu_ecc.scala 105:110] + is_ldst_r <= _T_1126 @[el2_lsu_ecc.scala 105:15] + node _T_1127 = eq(io.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[el2_lsu_ecc.scala 106:33] + node _T_1128 = and(is_ldst_r, _T_1127) @[el2_lsu_ecc.scala 106:31] + is_ldst_lo_r <= _T_1128 @[el2_lsu_ecc.scala 106:18] + node _T_1129 = or(ldst_dual_r, io.lsu_pkt_r.bits.dma) @[el2_lsu_ecc.scala 107:46] + node _T_1130 = and(is_ldst_r, _T_1129) @[el2_lsu_ecc.scala 107:31] + node _T_1131 = eq(io.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[el2_lsu_ecc.scala 107:73] + node _T_1132 = and(_T_1130, _T_1131) @[el2_lsu_ecc.scala 107:71] + is_ldst_hi_r <= _T_1132 @[el2_lsu_ecc.scala 107:18] + is_ldst_hi_any <= is_ldst_hi_r @[el2_lsu_ecc.scala 108:21] + dccm_rdata_hi_any <= io.dccm_rdata_hi_r @[el2_lsu_ecc.scala 109:24] + dccm_data_ecc_hi_any <= io.dccm_data_ecc_hi_r @[el2_lsu_ecc.scala 110:26] + is_ldst_lo_any <= is_ldst_lo_r @[el2_lsu_ecc.scala 111:20] + dccm_rdata_lo_any <= io.dccm_rdata_lo_r @[el2_lsu_ecc.scala 112:25] + dccm_data_ecc_lo_any <= io.dccm_data_ecc_lo_r @[el2_lsu_ecc.scala 113:26] + io.sec_data_hi_r <= sec_data_hi_any @[el2_lsu_ecc.scala 114:22] + io.single_ecc_error_hi_r <= single_ecc_error_hi_any @[el2_lsu_ecc.scala 115:31] + double_ecc_error_hi_r <= double_ecc_error_hi_any @[el2_lsu_ecc.scala 116:28] + io.sec_data_lo_r <= sec_data_lo_any @[el2_lsu_ecc.scala 117:25] + io.single_ecc_error_lo_r <= single_ecc_error_lo_any @[el2_lsu_ecc.scala 118:31] + double_ecc_error_lo_r <= double_ecc_error_lo_any @[el2_lsu_ecc.scala 119:28] + node _T_1133 = or(io.single_ecc_error_hi_r, io.single_ecc_error_lo_r) @[el2_lsu_ecc.scala 120:59] + io.lsu_single_ecc_error_r <= _T_1133 @[el2_lsu_ecc.scala 120:31] + node _T_1134 = or(double_ecc_error_hi_r, double_ecc_error_lo_r) @[el2_lsu_ecc.scala 121:56] + io.lsu_double_ecc_error_r <= _T_1134 @[el2_lsu_ecc.scala 121:31] + skip @[el2_lsu_ecc.scala 103:30] else : @[el2_lsu_ecc.scala 123:16] - node _T_1159 = bits(io.lsu_addr_m, 2, 2) @[el2_lsu_ecc.scala 124:35] - node _T_1160 = bits(io.end_addr_m, 2, 2) @[el2_lsu_ecc.scala 124:56] - node _T_1161 = neq(_T_1159, _T_1160) @[el2_lsu_ecc.scala 124:39] - ldst_dual_m <= _T_1161 @[el2_lsu_ecc.scala 124:19] - node _T_1162 = or(io.lsu_pkt_m.load, io.lsu_pkt_m.store) @[el2_lsu_ecc.scala 125:60] - node _T_1163 = and(io.lsu_pkt_m.valid, _T_1162) @[el2_lsu_ecc.scala 125:39] - node _T_1164 = and(_T_1163, io.addr_in_dccm_m) @[el2_lsu_ecc.scala 125:82] - node _T_1165 = and(_T_1164, io.lsu_dccm_rden_m) @[el2_lsu_ecc.scala 125:102] - is_ldst_m <= _T_1165 @[el2_lsu_ecc.scala 125:17] - node _T_1166 = eq(io.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[el2_lsu_ecc.scala 126:35] - node _T_1167 = and(is_ldst_m, _T_1166) @[el2_lsu_ecc.scala 126:33] - is_ldst_lo_m <= _T_1167 @[el2_lsu_ecc.scala 126:20] - node _T_1168 = or(ldst_dual_m, io.lsu_pkt_m.dma) @[el2_lsu_ecc.scala 127:48] - node _T_1169 = and(is_ldst_m, _T_1168) @[el2_lsu_ecc.scala 127:33] - node _T_1170 = eq(io.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[el2_lsu_ecc.scala 127:70] - node _T_1171 = and(_T_1169, _T_1170) @[el2_lsu_ecc.scala 127:68] - is_ldst_hi_m <= _T_1171 @[el2_lsu_ecc.scala 127:20] + node _T_1135 = bits(io.lsu_addr_m, 2, 2) @[el2_lsu_ecc.scala 124:35] + node _T_1136 = bits(io.end_addr_m, 2, 2) @[el2_lsu_ecc.scala 124:56] + node _T_1137 = neq(_T_1135, _T_1136) @[el2_lsu_ecc.scala 124:39] + ldst_dual_m <= _T_1137 @[el2_lsu_ecc.scala 124:19] + node _T_1138 = or(io.lsu_pkt_m.bits.load, io.lsu_pkt_m.bits.store) @[el2_lsu_ecc.scala 125:65] + node _T_1139 = and(io.lsu_pkt_m.valid, _T_1138) @[el2_lsu_ecc.scala 125:39] + node _T_1140 = and(_T_1139, io.addr_in_dccm_m) @[el2_lsu_ecc.scala 125:92] + node _T_1141 = and(_T_1140, io.lsu_dccm_rden_m) @[el2_lsu_ecc.scala 125:112] + is_ldst_m <= _T_1141 @[el2_lsu_ecc.scala 125:17] + node _T_1142 = eq(io.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[el2_lsu_ecc.scala 126:35] + node _T_1143 = and(is_ldst_m, _T_1142) @[el2_lsu_ecc.scala 126:33] + is_ldst_lo_m <= _T_1143 @[el2_lsu_ecc.scala 126:20] + node _T_1144 = or(ldst_dual_m, io.lsu_pkt_m.bits.dma) @[el2_lsu_ecc.scala 127:48] + node _T_1145 = and(is_ldst_m, _T_1144) @[el2_lsu_ecc.scala 127:33] + node _T_1146 = eq(io.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[el2_lsu_ecc.scala 127:75] + node _T_1147 = and(_T_1145, _T_1146) @[el2_lsu_ecc.scala 127:73] + is_ldst_hi_m <= _T_1147 @[el2_lsu_ecc.scala 127:20] is_ldst_hi_any <= is_ldst_hi_m @[el2_lsu_ecc.scala 128:23] dccm_rdata_hi_any <= io.dccm_rdata_hi_m @[el2_lsu_ecc.scala 129:26] dccm_data_ecc_hi_any <= io.dccm_data_ecc_hi_m @[el2_lsu_ecc.scala 130:28] @@ -1752,60 +1548,60 @@ circuit el2_lsu_ecc : double_ecc_error_hi_m <= double_ecc_error_hi_any @[el2_lsu_ecc.scala 135:30] io.sec_data_lo_m <= sec_data_lo_any @[el2_lsu_ecc.scala 136:27] double_ecc_error_lo_m <= double_ecc_error_lo_any @[el2_lsu_ecc.scala 137:30] - node _T_1172 = or(single_ecc_error_hi_any, single_ecc_error_lo_any) @[el2_lsu_ecc.scala 138:60] - io.lsu_single_ecc_error_m <= _T_1172 @[el2_lsu_ecc.scala 138:33] - node _T_1173 = or(double_ecc_error_hi_m, double_ecc_error_lo_m) @[el2_lsu_ecc.scala 139:58] - io.lsu_double_ecc_error_m <= _T_1173 @[el2_lsu_ecc.scala 139:33] - reg _T_1174 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_ecc.scala 141:72] - _T_1174 <= io.lsu_single_ecc_error_m @[el2_lsu_ecc.scala 141:72] - io.lsu_single_ecc_error_r <= _T_1174 @[el2_lsu_ecc.scala 141:62] - reg _T_1175 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_ecc.scala 142:72] - _T_1175 <= io.lsu_double_ecc_error_m @[el2_lsu_ecc.scala 142:72] - io.lsu_double_ecc_error_r <= _T_1175 @[el2_lsu_ecc.scala 142:62] - reg _T_1176 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_ecc.scala 143:72] - _T_1176 <= single_ecc_error_lo_any @[el2_lsu_ecc.scala 143:72] - io.single_ecc_error_lo_r <= _T_1176 @[el2_lsu_ecc.scala 143:62] - reg _T_1177 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_ecc.scala 144:72] - _T_1177 <= single_ecc_error_hi_any @[el2_lsu_ecc.scala 144:72] - io.single_ecc_error_hi_r <= _T_1177 @[el2_lsu_ecc.scala 144:62] - reg _T_1178 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_ecc.scala 145:72] - _T_1178 <= io.sec_data_hi_m @[el2_lsu_ecc.scala 145:72] - io.sec_data_hi_r <= _T_1178 @[el2_lsu_ecc.scala 145:62] - reg _T_1179 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_ecc.scala 146:72] - _T_1179 <= io.sec_data_lo_m @[el2_lsu_ecc.scala 146:72] - io.sec_data_lo_r <= _T_1179 @[el2_lsu_ecc.scala 146:62] + node _T_1148 = or(single_ecc_error_hi_any, single_ecc_error_lo_any) @[el2_lsu_ecc.scala 138:60] + io.lsu_single_ecc_error_m <= _T_1148 @[el2_lsu_ecc.scala 138:33] + node _T_1149 = or(double_ecc_error_hi_m, double_ecc_error_lo_m) @[el2_lsu_ecc.scala 139:58] + io.lsu_double_ecc_error_m <= _T_1149 @[el2_lsu_ecc.scala 139:33] + reg _T_1150 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_ecc.scala 141:72] + _T_1150 <= io.lsu_single_ecc_error_m @[el2_lsu_ecc.scala 141:72] + io.lsu_single_ecc_error_r <= _T_1150 @[el2_lsu_ecc.scala 141:62] + reg _T_1151 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_ecc.scala 142:72] + _T_1151 <= io.lsu_double_ecc_error_m @[el2_lsu_ecc.scala 142:72] + io.lsu_double_ecc_error_r <= _T_1151 @[el2_lsu_ecc.scala 142:62] + reg _T_1152 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_ecc.scala 143:72] + _T_1152 <= single_ecc_error_lo_any @[el2_lsu_ecc.scala 143:72] + io.single_ecc_error_lo_r <= _T_1152 @[el2_lsu_ecc.scala 143:62] + reg _T_1153 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_ecc.scala 144:72] + _T_1153 <= single_ecc_error_hi_any @[el2_lsu_ecc.scala 144:72] + io.single_ecc_error_hi_r <= _T_1153 @[el2_lsu_ecc.scala 144:62] + reg _T_1154 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_ecc.scala 145:72] + _T_1154 <= io.sec_data_hi_m @[el2_lsu_ecc.scala 145:72] + io.sec_data_hi_r <= _T_1154 @[el2_lsu_ecc.scala 145:62] + reg _T_1155 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_ecc.scala 146:72] + _T_1155 <= io.sec_data_lo_m @[el2_lsu_ecc.scala 146:72] + io.sec_data_lo_r <= _T_1155 @[el2_lsu_ecc.scala 146:62] skip @[el2_lsu_ecc.scala 123:16] - node _T_1180 = bits(io.ld_single_ecc_error_r_ff, 0, 0) @[el2_lsu_ecc.scala 149:58] - node _T_1181 = bits(io.dma_dccm_wen, 0, 0) @[el2_lsu_ecc.scala 149:106] - node _T_1182 = mux(_T_1181, io.dma_dccm_wdata_lo, io.stbuf_data_any) @[el2_lsu_ecc.scala 149:89] - node _T_1183 = mux(_T_1180, io.sec_data_lo_r_ff, _T_1182) @[el2_lsu_ecc.scala 149:29] - dccm_wdata_lo_any <= _T_1183 @[el2_lsu_ecc.scala 149:23] - node _T_1184 = bits(io.ld_single_ecc_error_r_ff, 0, 0) @[el2_lsu_ecc.scala 150:58] - node _T_1185 = bits(io.dma_dccm_wen, 0, 0) @[el2_lsu_ecc.scala 150:106] - node _T_1186 = mux(_T_1185, io.dma_dccm_wdata_hi, io.stbuf_data_any) @[el2_lsu_ecc.scala 150:89] - node _T_1187 = mux(_T_1184, io.sec_data_hi_r_ff, _T_1186) @[el2_lsu_ecc.scala 150:29] - dccm_wdata_hi_any <= _T_1187 @[el2_lsu_ecc.scala 150:23] - io.sec_data_ecc_hi_r_ff <= dccm_wdata_ecc_hi_any @[el2_lsu_ecc.scala 151:30] - io.sec_data_ecc_lo_r_ff <= dccm_wdata_ecc_lo_any @[el2_lsu_ecc.scala 152:30] - io.stbuf_ecc_any <= dccm_wdata_ecc_lo_any @[el2_lsu_ecc.scala 153:30] - io.dma_dccm_wdata_ecc_hi <= dccm_wdata_ecc_hi_any @[el2_lsu_ecc.scala 154:30] - io.dma_dccm_wdata_ecc_lo <= dccm_wdata_ecc_lo_any @[el2_lsu_ecc.scala 155:30] - inst rvclkhdr of rvclkhdr @[beh_lib.scala 352:21] + node _T_1156 = bits(io.ld_single_ecc_error_r_ff, 0, 0) @[el2_lsu_ecc.scala 149:56] + node _T_1157 = bits(io.dma_dccm_wen, 0, 0) @[el2_lsu_ecc.scala 149:104] + node _T_1158 = mux(_T_1157, io.dma_dccm_wdata_lo, io.stbuf_data_any) @[el2_lsu_ecc.scala 149:87] + node _T_1159 = mux(_T_1156, io.sec_data_lo_r_ff, _T_1158) @[el2_lsu_ecc.scala 149:27] + dccm_wdata_lo_any <= _T_1159 @[el2_lsu_ecc.scala 149:21] + node _T_1160 = bits(io.ld_single_ecc_error_r_ff, 0, 0) @[el2_lsu_ecc.scala 150:56] + node _T_1161 = bits(io.dma_dccm_wen, 0, 0) @[el2_lsu_ecc.scala 150:104] + node _T_1162 = mux(_T_1161, io.dma_dccm_wdata_hi, io.stbuf_data_any) @[el2_lsu_ecc.scala 150:87] + node _T_1163 = mux(_T_1160, io.sec_data_hi_r_ff, _T_1162) @[el2_lsu_ecc.scala 150:27] + dccm_wdata_hi_any <= _T_1163 @[el2_lsu_ecc.scala 150:21] + io.sec_data_ecc_hi_r_ff <= dccm_wdata_ecc_hi_any @[el2_lsu_ecc.scala 151:28] + io.sec_data_ecc_lo_r_ff <= dccm_wdata_ecc_lo_any @[el2_lsu_ecc.scala 152:28] + io.stbuf_ecc_any <= dccm_wdata_ecc_lo_any @[el2_lsu_ecc.scala 153:28] + io.dma_dccm_wdata_ecc_hi <= dccm_wdata_ecc_hi_any @[el2_lsu_ecc.scala 154:28] + io.dma_dccm_wdata_ecc_lo <= dccm_wdata_ecc_lo_any @[el2_lsu_ecc.scala 155:28] + inst rvclkhdr of rvclkhdr @[el2_lib.scala 508:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset - rvclkhdr.io.clk <= clock @[beh_lib.scala 354:16] - rvclkhdr.io.en <= io.ld_single_ecc_error_r @[beh_lib.scala 355:15] - rvclkhdr.io.scan_mode <= io.scan_mode @[beh_lib.scala 356:22] - reg _T_1188 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[beh_lib.scala 358:14] - _T_1188 <= io.sec_data_hi_r @[beh_lib.scala 358:14] - io.sec_data_hi_r_ff <= _T_1188 @[el2_lsu_ecc.scala 157:23] - inst rvclkhdr_1 of rvclkhdr_1 @[beh_lib.scala 352:21] + rvclkhdr.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr.io.en <= io.ld_single_ecc_error_r @[el2_lib.scala 511:17] + rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_1164 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_1164 <= io.sec_data_hi_r @[el2_lib.scala 514:16] + io.sec_data_hi_r_ff <= _T_1164 @[el2_lsu_ecc.scala 157:23] + inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 508:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset - rvclkhdr_1.io.clk <= clock @[beh_lib.scala 354:16] - rvclkhdr_1.io.en <= io.ld_single_ecc_error_r @[beh_lib.scala 355:15] - rvclkhdr_1.io.scan_mode <= io.scan_mode @[beh_lib.scala 356:22] - reg _T_1189 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[beh_lib.scala 358:14] - _T_1189 <= io.sec_data_lo_r @[beh_lib.scala 358:14] - io.sec_data_lo_r_ff <= _T_1189 @[el2_lsu_ecc.scala 158:23] + rvclkhdr_1.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_1.io.en <= io.ld_single_ecc_error_r @[el2_lib.scala 511:17] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_1165 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_1165 <= io.sec_data_lo_r @[el2_lib.scala 514:16] + io.sec_data_lo_r_ff <= _T_1165 @[el2_lsu_ecc.scala 158:23] diff --git a/el2_lsu_ecc.v b/el2_lsu_ecc.v index 8b4ca3c3..e381dff1 100644 --- a/el2_lsu_ecc.v +++ b/el2_lsu_ecc.v @@ -4,51 +4,51 @@ module rvclkhdr( input io_en, input io_scan_mode ); - wire clkhdr_Q; // @[beh_lib.scala 332:24] - wire clkhdr_CK; // @[beh_lib.scala 332:24] - wire clkhdr_EN; // @[beh_lib.scala 332:24] - wire clkhdr_SE; // @[beh_lib.scala 332:24] - TEC_RV_ICG clkhdr ( // @[beh_lib.scala 332:24] + wire clkhdr_Q; // @[el2_lib.scala 474:26] + wire clkhdr_CK; // @[el2_lib.scala 474:26] + wire clkhdr_EN; // @[el2_lib.scala 474:26] + wire clkhdr_SE; // @[el2_lib.scala 474:26] + gated_latch clkhdr ( // @[el2_lib.scala 474:26] .Q(clkhdr_Q), .CK(clkhdr_CK), .EN(clkhdr_EN), .SE(clkhdr_SE) ); - assign io_l1clk = clkhdr_Q; // @[beh_lib.scala 333:12] - assign clkhdr_CK = io_clk; // @[beh_lib.scala 334:16] - assign clkhdr_EN = io_en; // @[beh_lib.scala 335:16] - assign clkhdr_SE = io_scan_mode; // @[beh_lib.scala 336:16] + assign io_l1clk = clkhdr_Q; // @[el2_lib.scala 475:14] + assign clkhdr_CK = io_clk; // @[el2_lib.scala 476:18] + assign clkhdr_EN = io_en; // @[el2_lib.scala 477:18] + assign clkhdr_SE = io_scan_mode; // @[el2_lib.scala 478:18] endmodule module el2_lsu_ecc( input clock, input reset, input io_lsu_c2_r_clk, - input io_lsu_pkt_m_fast_int, - input io_lsu_pkt_m_by, - input io_lsu_pkt_m_half, - input io_lsu_pkt_m_word, - input io_lsu_pkt_m_dword, - input io_lsu_pkt_m_load, - input io_lsu_pkt_m_store, - input io_lsu_pkt_m_unsign, - input io_lsu_pkt_m_dma, - input io_lsu_pkt_m_store_data_bypass_d, - input io_lsu_pkt_m_load_ldst_bypass_d, - input io_lsu_pkt_m_store_data_bypass_m, input io_lsu_pkt_m_valid, - input io_lsu_pkt_r_fast_int, - input io_lsu_pkt_r_by, - input io_lsu_pkt_r_half, - input io_lsu_pkt_r_word, - input io_lsu_pkt_r_dword, - input io_lsu_pkt_r_load, - input io_lsu_pkt_r_store, - input io_lsu_pkt_r_unsign, - input io_lsu_pkt_r_dma, - input io_lsu_pkt_r_store_data_bypass_d, - input io_lsu_pkt_r_load_ldst_bypass_d, - input io_lsu_pkt_r_store_data_bypass_m, + input io_lsu_pkt_m_bits_fast_int, + input io_lsu_pkt_m_bits_by, + input io_lsu_pkt_m_bits_half, + input io_lsu_pkt_m_bits_word, + input io_lsu_pkt_m_bits_dword, + input io_lsu_pkt_m_bits_load, + input io_lsu_pkt_m_bits_store, + input io_lsu_pkt_m_bits_unsign, + input io_lsu_pkt_m_bits_dma, + input io_lsu_pkt_m_bits_store_data_bypass_d, + input io_lsu_pkt_m_bits_load_ldst_bypass_d, + input io_lsu_pkt_m_bits_store_data_bypass_m, input io_lsu_pkt_r_valid, + input io_lsu_pkt_r_bits_fast_int, + input io_lsu_pkt_r_bits_by, + input io_lsu_pkt_r_bits_half, + input io_lsu_pkt_r_bits_word, + input io_lsu_pkt_r_bits_dword, + input io_lsu_pkt_r_bits_load, + input io_lsu_pkt_r_bits_store, + input io_lsu_pkt_r_bits_unsign, + input io_lsu_pkt_r_bits_dma, + input io_lsu_pkt_r_bits_store_data_bypass_d, + input io_lsu_pkt_r_bits_load_ldst_bypass_d, + input io_lsu_pkt_r_bits_store_data_bypass_m, input [31:0] io_stbuf_data_any, input io_dec_tlu_core_ecc_disable, input io_lsu_dccm_rden_r, @@ -101,277 +101,411 @@ module el2_lsu_ecc( reg [31:0] _RAND_6; reg [31:0] _RAND_7; `endif // RANDOMIZE_REG_INIT - wire rvclkhdr_io_l1clk; // @[beh_lib.scala 352:21] - wire rvclkhdr_io_clk; // @[beh_lib.scala 352:21] - wire rvclkhdr_io_en; // @[beh_lib.scala 352:21] - wire rvclkhdr_io_scan_mode; // @[beh_lib.scala 352:21] - wire rvclkhdr_1_io_l1clk; // @[beh_lib.scala 352:21] - wire rvclkhdr_1_io_clk; // @[beh_lib.scala 352:21] - wire rvclkhdr_1_io_en; // @[beh_lib.scala 352:21] - wire rvclkhdr_1_io_scan_mode; // @[beh_lib.scala 352:21] - wire _T_96 = ^io_dccm_rdata_hi_m; // @[el2_lib.scala 324:30] - wire _T_97 = ^io_dccm_data_ecc_hi_m; // @[el2_lib.scala 324:44] - wire _T_98 = _T_96 ^ _T_97; // @[el2_lib.scala 324:35] - wire [5:0] _T_106 = {io_dccm_rdata_hi_m[31],io_dccm_rdata_hi_m[30],io_dccm_rdata_hi_m[29],io_dccm_rdata_hi_m[28],io_dccm_rdata_hi_m[27],io_dccm_rdata_hi_m[26]}; // @[el2_lib.scala 324:76] - wire _T_107 = ^_T_106; // @[el2_lib.scala 324:83] - wire _T_108 = io_dccm_data_ecc_hi_m[5] ^ _T_107; // @[el2_lib.scala 324:71] - wire [6:0] _T_115 = {io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[16],io_dccm_rdata_hi_m[15],io_dccm_rdata_hi_m[14],io_dccm_rdata_hi_m[13],io_dccm_rdata_hi_m[12],io_dccm_rdata_hi_m[11]}; // @[el2_lib.scala 324:103] - wire [14:0] _T_123 = {io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[22],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[20],io_dccm_rdata_hi_m[19],io_dccm_rdata_hi_m[18],_T_115}; // @[el2_lib.scala 324:103] - wire _T_124 = ^_T_123; // @[el2_lib.scala 324:110] - wire _T_125 = io_dccm_data_ecc_hi_m[4] ^ _T_124; // @[el2_lib.scala 324:98] - wire [6:0] _T_132 = {io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[9],io_dccm_rdata_hi_m[8],io_dccm_rdata_hi_m[7],io_dccm_rdata_hi_m[6],io_dccm_rdata_hi_m[5],io_dccm_rdata_hi_m[4]}; // @[el2_lib.scala 324:130] - wire [14:0] _T_140 = {io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[22],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[20],io_dccm_rdata_hi_m[19],io_dccm_rdata_hi_m[18],_T_132}; // @[el2_lib.scala 324:130] - wire _T_141 = ^_T_140; // @[el2_lib.scala 324:137] - wire _T_142 = io_dccm_data_ecc_hi_m[3] ^ _T_141; // @[el2_lib.scala 324:125] - wire [8:0] _T_151 = {io_dccm_rdata_hi_m[15],io_dccm_rdata_hi_m[14],io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[9],io_dccm_rdata_hi_m[8],io_dccm_rdata_hi_m[7],io_dccm_rdata_hi_m[3],io_dccm_rdata_hi_m[2],io_dccm_rdata_hi_m[1]}; // @[el2_lib.scala 324:157] - wire [17:0] _T_160 = {io_dccm_rdata_hi_m[31],io_dccm_rdata_hi_m[30],io_dccm_rdata_hi_m[29],io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[22],io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[16],_T_151}; // @[el2_lib.scala 324:157] - wire _T_161 = ^_T_160; // @[el2_lib.scala 324:164] - wire _T_162 = io_dccm_data_ecc_hi_m[2] ^ _T_161; // @[el2_lib.scala 324:152] - wire [8:0] _T_171 = {io_dccm_rdata_hi_m[13],io_dccm_rdata_hi_m[12],io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[9],io_dccm_rdata_hi_m[6],io_dccm_rdata_hi_m[5],io_dccm_rdata_hi_m[3],io_dccm_rdata_hi_m[2],io_dccm_rdata_hi_m[0]}; // @[el2_lib.scala 324:184] - wire [17:0] _T_180 = {io_dccm_rdata_hi_m[31],io_dccm_rdata_hi_m[28],io_dccm_rdata_hi_m[27],io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[20],io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[16],_T_171}; // @[el2_lib.scala 324:184] - wire _T_181 = ^_T_180; // @[el2_lib.scala 324:191] - wire _T_182 = io_dccm_data_ecc_hi_m[1] ^ _T_181; // @[el2_lib.scala 324:179] - wire [8:0] _T_191 = {io_dccm_rdata_hi_m[13],io_dccm_rdata_hi_m[11],io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[8],io_dccm_rdata_hi_m[6],io_dccm_rdata_hi_m[4],io_dccm_rdata_hi_m[3],io_dccm_rdata_hi_m[1],io_dccm_rdata_hi_m[0]}; // @[el2_lib.scala 324:211] - wire [17:0] _T_200 = {io_dccm_rdata_hi_m[30],io_dccm_rdata_hi_m[28],io_dccm_rdata_hi_m[26],io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[19],io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[15],_T_191}; // @[el2_lib.scala 324:211] - wire _T_201 = ^_T_200; // @[el2_lib.scala 324:218] - wire _T_202 = io_dccm_data_ecc_hi_m[0] ^ _T_201; // @[el2_lib.scala 324:206] + wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 508:23] + wire _T_96 = ^io_dccm_rdata_hi_m; // @[el2_lib.scala 333:30] + wire _T_97 = ^io_dccm_data_ecc_hi_m; // @[el2_lib.scala 333:44] + wire _T_98 = _T_96 ^ _T_97; // @[el2_lib.scala 333:35] + wire [5:0] _T_106 = {io_dccm_rdata_hi_m[31],io_dccm_rdata_hi_m[30],io_dccm_rdata_hi_m[29],io_dccm_rdata_hi_m[28],io_dccm_rdata_hi_m[27],io_dccm_rdata_hi_m[26]}; // @[el2_lib.scala 333:76] + wire _T_107 = ^_T_106; // @[el2_lib.scala 333:83] + wire _T_108 = io_dccm_data_ecc_hi_m[5] ^ _T_107; // @[el2_lib.scala 333:71] + wire [6:0] _T_115 = {io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[16],io_dccm_rdata_hi_m[15],io_dccm_rdata_hi_m[14],io_dccm_rdata_hi_m[13],io_dccm_rdata_hi_m[12],io_dccm_rdata_hi_m[11]}; // @[el2_lib.scala 333:103] + wire [14:0] _T_123 = {io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[22],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[20],io_dccm_rdata_hi_m[19],io_dccm_rdata_hi_m[18],_T_115}; // @[el2_lib.scala 333:103] + wire _T_124 = ^_T_123; // @[el2_lib.scala 333:110] + wire _T_125 = io_dccm_data_ecc_hi_m[4] ^ _T_124; // @[el2_lib.scala 333:98] + wire [6:0] _T_132 = {io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[9],io_dccm_rdata_hi_m[8],io_dccm_rdata_hi_m[7],io_dccm_rdata_hi_m[6],io_dccm_rdata_hi_m[5],io_dccm_rdata_hi_m[4]}; // @[el2_lib.scala 333:130] + wire [14:0] _T_140 = {io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[22],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[20],io_dccm_rdata_hi_m[19],io_dccm_rdata_hi_m[18],_T_132}; // @[el2_lib.scala 333:130] + wire _T_141 = ^_T_140; // @[el2_lib.scala 333:137] + wire _T_142 = io_dccm_data_ecc_hi_m[3] ^ _T_141; // @[el2_lib.scala 333:125] + wire [8:0] _T_151 = {io_dccm_rdata_hi_m[15],io_dccm_rdata_hi_m[14],io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[9],io_dccm_rdata_hi_m[8],io_dccm_rdata_hi_m[7],io_dccm_rdata_hi_m[3],io_dccm_rdata_hi_m[2],io_dccm_rdata_hi_m[1]}; // @[el2_lib.scala 333:157] + wire [17:0] _T_160 = {io_dccm_rdata_hi_m[31],io_dccm_rdata_hi_m[30],io_dccm_rdata_hi_m[29],io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[22],io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[16],_T_151}; // @[el2_lib.scala 333:157] + wire _T_161 = ^_T_160; // @[el2_lib.scala 333:164] + wire _T_162 = io_dccm_data_ecc_hi_m[2] ^ _T_161; // @[el2_lib.scala 333:152] + wire [8:0] _T_171 = {io_dccm_rdata_hi_m[13],io_dccm_rdata_hi_m[12],io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[9],io_dccm_rdata_hi_m[6],io_dccm_rdata_hi_m[5],io_dccm_rdata_hi_m[3],io_dccm_rdata_hi_m[2],io_dccm_rdata_hi_m[0]}; // @[el2_lib.scala 333:184] + wire [17:0] _T_180 = {io_dccm_rdata_hi_m[31],io_dccm_rdata_hi_m[28],io_dccm_rdata_hi_m[27],io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[20],io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[16],_T_171}; // @[el2_lib.scala 333:184] + wire _T_181 = ^_T_180; // @[el2_lib.scala 333:191] + wire _T_182 = io_dccm_data_ecc_hi_m[1] ^ _T_181; // @[el2_lib.scala 333:179] + wire [8:0] _T_191 = {io_dccm_rdata_hi_m[13],io_dccm_rdata_hi_m[11],io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[8],io_dccm_rdata_hi_m[6],io_dccm_rdata_hi_m[4],io_dccm_rdata_hi_m[3],io_dccm_rdata_hi_m[1],io_dccm_rdata_hi_m[0]}; // @[el2_lib.scala 333:211] + wire [17:0] _T_200 = {io_dccm_rdata_hi_m[30],io_dccm_rdata_hi_m[28],io_dccm_rdata_hi_m[26],io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[19],io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[15],_T_191}; // @[el2_lib.scala 333:211] + wire _T_201 = ^_T_200; // @[el2_lib.scala 333:218] + wire _T_202 = io_dccm_data_ecc_hi_m[0] ^ _T_201; // @[el2_lib.scala 333:206] wire [6:0] _T_208 = {_T_98,_T_108,_T_125,_T_142,_T_162,_T_182,_T_202}; // @[Cat.scala 29:58] - wire _T_209 = _T_208 != 7'h0; // @[el2_lib.scala 325:44] - wire _T_1155 = ~io_dec_tlu_core_ecc_disable; // @[el2_lsu_ecc.scala 107:70] - wire _T_1162 = io_lsu_pkt_m_load | io_lsu_pkt_m_store; // @[el2_lsu_ecc.scala 125:60] - wire _T_1163 = io_lsu_pkt_m_valid & _T_1162; // @[el2_lsu_ecc.scala 125:39] - wire _T_1164 = _T_1163 & io_addr_in_dccm_m; // @[el2_lsu_ecc.scala 125:82] - wire is_ldst_m = _T_1164 & io_lsu_dccm_rden_m; // @[el2_lsu_ecc.scala 125:102] + wire _T_209 = _T_208 != 7'h0; // @[el2_lib.scala 334:44] + wire _T_1131 = ~io_dec_tlu_core_ecc_disable; // @[el2_lsu_ecc.scala 107:73] + wire _T_1138 = io_lsu_pkt_m_bits_load | io_lsu_pkt_m_bits_store; // @[el2_lsu_ecc.scala 125:65] + wire _T_1139 = io_lsu_pkt_m_valid & _T_1138; // @[el2_lsu_ecc.scala 125:39] + wire _T_1140 = _T_1139 & io_addr_in_dccm_m; // @[el2_lsu_ecc.scala 125:92] + wire is_ldst_m = _T_1140 & io_lsu_dccm_rden_m; // @[el2_lsu_ecc.scala 125:112] wire ldst_dual_m = io_lsu_addr_m[2] != io_end_addr_m[2]; // @[el2_lsu_ecc.scala 124:39] - wire _T_1168 = ldst_dual_m | io_lsu_pkt_m_dma; // @[el2_lsu_ecc.scala 127:48] - wire _T_1169 = is_ldst_m & _T_1168; // @[el2_lsu_ecc.scala 127:33] - wire is_ldst_hi_m = _T_1169 & _T_1155; // @[el2_lsu_ecc.scala 127:68] - wire _T_210 = is_ldst_hi_m & _T_209; // @[el2_lib.scala 325:32] - wire single_ecc_error_hi_any = _T_210 & _T_208[6]; // @[el2_lib.scala 325:53] - wire _T_215 = ~_T_208[6]; // @[el2_lib.scala 326:55] - wire double_ecc_error_hi_any = _T_210 & _T_215; // @[el2_lib.scala 326:53] - wire _T_218 = _T_208[5:0] == 6'h1; // @[el2_lib.scala 330:41] - wire _T_220 = _T_208[5:0] == 6'h2; // @[el2_lib.scala 330:41] - wire _T_222 = _T_208[5:0] == 6'h3; // @[el2_lib.scala 330:41] - wire _T_224 = _T_208[5:0] == 6'h4; // @[el2_lib.scala 330:41] - wire _T_226 = _T_208[5:0] == 6'h5; // @[el2_lib.scala 330:41] - wire _T_228 = _T_208[5:0] == 6'h6; // @[el2_lib.scala 330:41] - wire _T_230 = _T_208[5:0] == 6'h7; // @[el2_lib.scala 330:41] - wire _T_232 = _T_208[5:0] == 6'h8; // @[el2_lib.scala 330:41] - wire _T_234 = _T_208[5:0] == 6'h9; // @[el2_lib.scala 330:41] - wire _T_236 = _T_208[5:0] == 6'ha; // @[el2_lib.scala 330:41] - wire _T_238 = _T_208[5:0] == 6'hb; // @[el2_lib.scala 330:41] - wire _T_240 = _T_208[5:0] == 6'hc; // @[el2_lib.scala 330:41] - wire _T_242 = _T_208[5:0] == 6'hd; // @[el2_lib.scala 330:41] - wire _T_244 = _T_208[5:0] == 6'he; // @[el2_lib.scala 330:41] - wire _T_246 = _T_208[5:0] == 6'hf; // @[el2_lib.scala 330:41] - wire _T_248 = _T_208[5:0] == 6'h10; // @[el2_lib.scala 330:41] - wire _T_250 = _T_208[5:0] == 6'h11; // @[el2_lib.scala 330:41] - wire _T_252 = _T_208[5:0] == 6'h12; // @[el2_lib.scala 330:41] - wire _T_254 = _T_208[5:0] == 6'h13; // @[el2_lib.scala 330:41] - wire _T_256 = _T_208[5:0] == 6'h14; // @[el2_lib.scala 330:41] - wire _T_258 = _T_208[5:0] == 6'h15; // @[el2_lib.scala 330:41] - wire _T_260 = _T_208[5:0] == 6'h16; // @[el2_lib.scala 330:41] - wire _T_262 = _T_208[5:0] == 6'h17; // @[el2_lib.scala 330:41] - wire _T_264 = _T_208[5:0] == 6'h18; // @[el2_lib.scala 330:41] - wire _T_266 = _T_208[5:0] == 6'h19; // @[el2_lib.scala 330:41] - wire _T_268 = _T_208[5:0] == 6'h1a; // @[el2_lib.scala 330:41] - wire _T_270 = _T_208[5:0] == 6'h1b; // @[el2_lib.scala 330:41] - wire _T_272 = _T_208[5:0] == 6'h1c; // @[el2_lib.scala 330:41] - wire _T_274 = _T_208[5:0] == 6'h1d; // @[el2_lib.scala 330:41] - wire _T_276 = _T_208[5:0] == 6'h1e; // @[el2_lib.scala 330:41] - wire _T_278 = _T_208[5:0] == 6'h1f; // @[el2_lib.scala 330:41] - wire _T_280 = _T_208[5:0] == 6'h20; // @[el2_lib.scala 330:41] - wire _T_282 = _T_208[5:0] == 6'h21; // @[el2_lib.scala 330:41] - wire _T_284 = _T_208[5:0] == 6'h22; // @[el2_lib.scala 330:41] - wire _T_286 = _T_208[5:0] == 6'h23; // @[el2_lib.scala 330:41] - wire _T_288 = _T_208[5:0] == 6'h24; // @[el2_lib.scala 330:41] - wire _T_290 = _T_208[5:0] == 6'h25; // @[el2_lib.scala 330:41] - wire _T_292 = _T_208[5:0] == 6'h26; // @[el2_lib.scala 330:41] - wire _T_294 = _T_208[5:0] == 6'h27; // @[el2_lib.scala 330:41] + wire _T_1144 = ldst_dual_m | io_lsu_pkt_m_bits_dma; // @[el2_lsu_ecc.scala 127:48] + wire _T_1145 = is_ldst_m & _T_1144; // @[el2_lsu_ecc.scala 127:33] + wire is_ldst_hi_m = _T_1145 & _T_1131; // @[el2_lsu_ecc.scala 127:73] + wire _T_210 = is_ldst_hi_m & _T_209; // @[el2_lib.scala 334:32] + wire single_ecc_error_hi_any = _T_210 & _T_208[6]; // @[el2_lib.scala 334:53] + wire _T_215 = ~_T_208[6]; // @[el2_lib.scala 335:55] + wire double_ecc_error_hi_any = _T_210 & _T_215; // @[el2_lib.scala 335:53] + wire _T_218 = _T_208[5:0] == 6'h1; // @[el2_lib.scala 339:41] + wire _T_220 = _T_208[5:0] == 6'h2; // @[el2_lib.scala 339:41] + wire _T_222 = _T_208[5:0] == 6'h3; // @[el2_lib.scala 339:41] + wire _T_224 = _T_208[5:0] == 6'h4; // @[el2_lib.scala 339:41] + wire _T_226 = _T_208[5:0] == 6'h5; // @[el2_lib.scala 339:41] + wire _T_228 = _T_208[5:0] == 6'h6; // @[el2_lib.scala 339:41] + wire _T_230 = _T_208[5:0] == 6'h7; // @[el2_lib.scala 339:41] + wire _T_232 = _T_208[5:0] == 6'h8; // @[el2_lib.scala 339:41] + wire _T_234 = _T_208[5:0] == 6'h9; // @[el2_lib.scala 339:41] + wire _T_236 = _T_208[5:0] == 6'ha; // @[el2_lib.scala 339:41] + wire _T_238 = _T_208[5:0] == 6'hb; // @[el2_lib.scala 339:41] + wire _T_240 = _T_208[5:0] == 6'hc; // @[el2_lib.scala 339:41] + wire _T_242 = _T_208[5:0] == 6'hd; // @[el2_lib.scala 339:41] + wire _T_244 = _T_208[5:0] == 6'he; // @[el2_lib.scala 339:41] + wire _T_246 = _T_208[5:0] == 6'hf; // @[el2_lib.scala 339:41] + wire _T_248 = _T_208[5:0] == 6'h10; // @[el2_lib.scala 339:41] + wire _T_250 = _T_208[5:0] == 6'h11; // @[el2_lib.scala 339:41] + wire _T_252 = _T_208[5:0] == 6'h12; // @[el2_lib.scala 339:41] + wire _T_254 = _T_208[5:0] == 6'h13; // @[el2_lib.scala 339:41] + wire _T_256 = _T_208[5:0] == 6'h14; // @[el2_lib.scala 339:41] + wire _T_258 = _T_208[5:0] == 6'h15; // @[el2_lib.scala 339:41] + wire _T_260 = _T_208[5:0] == 6'h16; // @[el2_lib.scala 339:41] + wire _T_262 = _T_208[5:0] == 6'h17; // @[el2_lib.scala 339:41] + wire _T_264 = _T_208[5:0] == 6'h18; // @[el2_lib.scala 339:41] + wire _T_266 = _T_208[5:0] == 6'h19; // @[el2_lib.scala 339:41] + wire _T_268 = _T_208[5:0] == 6'h1a; // @[el2_lib.scala 339:41] + wire _T_270 = _T_208[5:0] == 6'h1b; // @[el2_lib.scala 339:41] + wire _T_272 = _T_208[5:0] == 6'h1c; // @[el2_lib.scala 339:41] + wire _T_274 = _T_208[5:0] == 6'h1d; // @[el2_lib.scala 339:41] + wire _T_276 = _T_208[5:0] == 6'h1e; // @[el2_lib.scala 339:41] + wire _T_278 = _T_208[5:0] == 6'h1f; // @[el2_lib.scala 339:41] + wire _T_280 = _T_208[5:0] == 6'h20; // @[el2_lib.scala 339:41] + wire _T_282 = _T_208[5:0] == 6'h21; // @[el2_lib.scala 339:41] + wire _T_284 = _T_208[5:0] == 6'h22; // @[el2_lib.scala 339:41] + wire _T_286 = _T_208[5:0] == 6'h23; // @[el2_lib.scala 339:41] + wire _T_288 = _T_208[5:0] == 6'h24; // @[el2_lib.scala 339:41] + wire _T_290 = _T_208[5:0] == 6'h25; // @[el2_lib.scala 339:41] + wire _T_292 = _T_208[5:0] == 6'h26; // @[el2_lib.scala 339:41] + wire _T_294 = _T_208[5:0] == 6'h27; // @[el2_lib.scala 339:41] wire [7:0] _T_309 = {io_dccm_data_ecc_hi_m[3],io_dccm_rdata_hi_m[3:1],io_dccm_data_ecc_hi_m[2],io_dccm_rdata_hi_m[0],io_dccm_data_ecc_hi_m[1:0]}; // @[Cat.scala 29:58] wire [38:0] _T_315 = {io_dccm_data_ecc_hi_m[6],io_dccm_rdata_hi_m[31:26],io_dccm_data_ecc_hi_m[5],io_dccm_rdata_hi_m[25:11],io_dccm_data_ecc_hi_m[4],io_dccm_rdata_hi_m[10:4],_T_309}; // @[Cat.scala 29:58] - wire [9:0] _T_333 = {_T_254,_T_252,_T_250,_T_248,_T_246,_T_244,_T_242,_T_240,_T_238,_T_236}; // @[el2_lib.scala 333:69] - wire [18:0] _T_334 = {_T_333,_T_234,_T_232,_T_230,_T_228,_T_226,_T_224,_T_222,_T_220,_T_218}; // @[el2_lib.scala 333:69] - wire [9:0] _T_343 = {_T_274,_T_272,_T_270,_T_268,_T_266,_T_264,_T_262,_T_260,_T_258,_T_256}; // @[el2_lib.scala 333:69] - wire [9:0] _T_352 = {_T_294,_T_292,_T_290,_T_288,_T_286,_T_284,_T_282,_T_280,_T_278,_T_276}; // @[el2_lib.scala 333:69] - wire [38:0] _T_354 = {_T_352,_T_343,_T_334}; // @[el2_lib.scala 333:69] - wire [38:0] _T_355 = _T_354 ^ _T_315; // @[el2_lib.scala 333:76] - wire [38:0] _T_356 = single_ecc_error_hi_any ? _T_355 : _T_315; // @[el2_lib.scala 333:31] + wire [9:0] _T_333 = {_T_254,_T_252,_T_250,_T_248,_T_246,_T_244,_T_242,_T_240,_T_238,_T_236}; // @[el2_lib.scala 342:69] + wire [18:0] _T_334 = {_T_333,_T_234,_T_232,_T_230,_T_228,_T_226,_T_224,_T_222,_T_220,_T_218}; // @[el2_lib.scala 342:69] + wire [9:0] _T_343 = {_T_274,_T_272,_T_270,_T_268,_T_266,_T_264,_T_262,_T_260,_T_258,_T_256}; // @[el2_lib.scala 342:69] + wire [9:0] _T_352 = {_T_294,_T_292,_T_290,_T_288,_T_286,_T_284,_T_282,_T_280,_T_278,_T_276}; // @[el2_lib.scala 342:69] + wire [38:0] _T_354 = {_T_352,_T_343,_T_334}; // @[el2_lib.scala 342:69] + wire [38:0] _T_355 = _T_354 ^ _T_315; // @[el2_lib.scala 342:76] + wire [38:0] _T_356 = single_ecc_error_hi_any ? _T_355 : _T_315; // @[el2_lib.scala 342:31] wire [3:0] _T_362 = {_T_356[6:4],_T_356[2]}; // @[Cat.scala 29:58] wire [27:0] _T_364 = {_T_356[37:32],_T_356[30:16],_T_356[14:8]}; // @[Cat.scala 29:58] - wire _T_474 = ^io_dccm_rdata_lo_m; // @[el2_lib.scala 324:30] - wire _T_475 = ^io_dccm_data_ecc_lo_m; // @[el2_lib.scala 324:44] - wire _T_476 = _T_474 ^ _T_475; // @[el2_lib.scala 324:35] - wire [5:0] _T_484 = {io_dccm_rdata_lo_m[31],io_dccm_rdata_lo_m[30],io_dccm_rdata_lo_m[29],io_dccm_rdata_lo_m[28],io_dccm_rdata_lo_m[27],io_dccm_rdata_lo_m[26]}; // @[el2_lib.scala 324:76] - wire _T_485 = ^_T_484; // @[el2_lib.scala 324:83] - wire _T_486 = io_dccm_data_ecc_lo_m[5] ^ _T_485; // @[el2_lib.scala 324:71] - wire [6:0] _T_493 = {io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[16],io_dccm_rdata_lo_m[15],io_dccm_rdata_lo_m[14],io_dccm_rdata_lo_m[13],io_dccm_rdata_lo_m[12],io_dccm_rdata_lo_m[11]}; // @[el2_lib.scala 324:103] - wire [14:0] _T_501 = {io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[22],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[20],io_dccm_rdata_lo_m[19],io_dccm_rdata_lo_m[18],_T_493}; // @[el2_lib.scala 324:103] - wire _T_502 = ^_T_501; // @[el2_lib.scala 324:110] - wire _T_503 = io_dccm_data_ecc_lo_m[4] ^ _T_502; // @[el2_lib.scala 324:98] - wire [6:0] _T_510 = {io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[9],io_dccm_rdata_lo_m[8],io_dccm_rdata_lo_m[7],io_dccm_rdata_lo_m[6],io_dccm_rdata_lo_m[5],io_dccm_rdata_lo_m[4]}; // @[el2_lib.scala 324:130] - wire [14:0] _T_518 = {io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[22],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[20],io_dccm_rdata_lo_m[19],io_dccm_rdata_lo_m[18],_T_510}; // @[el2_lib.scala 324:130] - wire _T_519 = ^_T_518; // @[el2_lib.scala 324:137] - wire _T_520 = io_dccm_data_ecc_lo_m[3] ^ _T_519; // @[el2_lib.scala 324:125] - wire [8:0] _T_529 = {io_dccm_rdata_lo_m[15],io_dccm_rdata_lo_m[14],io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[9],io_dccm_rdata_lo_m[8],io_dccm_rdata_lo_m[7],io_dccm_rdata_lo_m[3],io_dccm_rdata_lo_m[2],io_dccm_rdata_lo_m[1]}; // @[el2_lib.scala 324:157] - wire [17:0] _T_538 = {io_dccm_rdata_lo_m[31],io_dccm_rdata_lo_m[30],io_dccm_rdata_lo_m[29],io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[22],io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[16],_T_529}; // @[el2_lib.scala 324:157] - wire _T_539 = ^_T_538; // @[el2_lib.scala 324:164] - wire _T_540 = io_dccm_data_ecc_lo_m[2] ^ _T_539; // @[el2_lib.scala 324:152] - wire [8:0] _T_549 = {io_dccm_rdata_lo_m[13],io_dccm_rdata_lo_m[12],io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[9],io_dccm_rdata_lo_m[6],io_dccm_rdata_lo_m[5],io_dccm_rdata_lo_m[3],io_dccm_rdata_lo_m[2],io_dccm_rdata_lo_m[0]}; // @[el2_lib.scala 324:184] - wire [17:0] _T_558 = {io_dccm_rdata_lo_m[31],io_dccm_rdata_lo_m[28],io_dccm_rdata_lo_m[27],io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[20],io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[16],_T_549}; // @[el2_lib.scala 324:184] - wire _T_559 = ^_T_558; // @[el2_lib.scala 324:191] - wire _T_560 = io_dccm_data_ecc_lo_m[1] ^ _T_559; // @[el2_lib.scala 324:179] - wire [8:0] _T_569 = {io_dccm_rdata_lo_m[13],io_dccm_rdata_lo_m[11],io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[8],io_dccm_rdata_lo_m[6],io_dccm_rdata_lo_m[4],io_dccm_rdata_lo_m[3],io_dccm_rdata_lo_m[1],io_dccm_rdata_lo_m[0]}; // @[el2_lib.scala 324:211] - wire [17:0] _T_578 = {io_dccm_rdata_lo_m[30],io_dccm_rdata_lo_m[28],io_dccm_rdata_lo_m[26],io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[19],io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[15],_T_569}; // @[el2_lib.scala 324:211] - wire _T_579 = ^_T_578; // @[el2_lib.scala 324:218] - wire _T_580 = io_dccm_data_ecc_lo_m[0] ^ _T_579; // @[el2_lib.scala 324:206] + wire _T_474 = ^io_dccm_rdata_lo_m; // @[el2_lib.scala 333:30] + wire _T_475 = ^io_dccm_data_ecc_lo_m; // @[el2_lib.scala 333:44] + wire _T_476 = _T_474 ^ _T_475; // @[el2_lib.scala 333:35] + wire [5:0] _T_484 = {io_dccm_rdata_lo_m[31],io_dccm_rdata_lo_m[30],io_dccm_rdata_lo_m[29],io_dccm_rdata_lo_m[28],io_dccm_rdata_lo_m[27],io_dccm_rdata_lo_m[26]}; // @[el2_lib.scala 333:76] + wire _T_485 = ^_T_484; // @[el2_lib.scala 333:83] + wire _T_486 = io_dccm_data_ecc_lo_m[5] ^ _T_485; // @[el2_lib.scala 333:71] + wire [6:0] _T_493 = {io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[16],io_dccm_rdata_lo_m[15],io_dccm_rdata_lo_m[14],io_dccm_rdata_lo_m[13],io_dccm_rdata_lo_m[12],io_dccm_rdata_lo_m[11]}; // @[el2_lib.scala 333:103] + wire [14:0] _T_501 = {io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[22],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[20],io_dccm_rdata_lo_m[19],io_dccm_rdata_lo_m[18],_T_493}; // @[el2_lib.scala 333:103] + wire _T_502 = ^_T_501; // @[el2_lib.scala 333:110] + wire _T_503 = io_dccm_data_ecc_lo_m[4] ^ _T_502; // @[el2_lib.scala 333:98] + wire [6:0] _T_510 = {io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[9],io_dccm_rdata_lo_m[8],io_dccm_rdata_lo_m[7],io_dccm_rdata_lo_m[6],io_dccm_rdata_lo_m[5],io_dccm_rdata_lo_m[4]}; // @[el2_lib.scala 333:130] + wire [14:0] _T_518 = {io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[22],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[20],io_dccm_rdata_lo_m[19],io_dccm_rdata_lo_m[18],_T_510}; // @[el2_lib.scala 333:130] + wire _T_519 = ^_T_518; // @[el2_lib.scala 333:137] + wire _T_520 = io_dccm_data_ecc_lo_m[3] ^ _T_519; // @[el2_lib.scala 333:125] + wire [8:0] _T_529 = {io_dccm_rdata_lo_m[15],io_dccm_rdata_lo_m[14],io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[9],io_dccm_rdata_lo_m[8],io_dccm_rdata_lo_m[7],io_dccm_rdata_lo_m[3],io_dccm_rdata_lo_m[2],io_dccm_rdata_lo_m[1]}; // @[el2_lib.scala 333:157] + wire [17:0] _T_538 = {io_dccm_rdata_lo_m[31],io_dccm_rdata_lo_m[30],io_dccm_rdata_lo_m[29],io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[22],io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[16],_T_529}; // @[el2_lib.scala 333:157] + wire _T_539 = ^_T_538; // @[el2_lib.scala 333:164] + wire _T_540 = io_dccm_data_ecc_lo_m[2] ^ _T_539; // @[el2_lib.scala 333:152] + wire [8:0] _T_549 = {io_dccm_rdata_lo_m[13],io_dccm_rdata_lo_m[12],io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[9],io_dccm_rdata_lo_m[6],io_dccm_rdata_lo_m[5],io_dccm_rdata_lo_m[3],io_dccm_rdata_lo_m[2],io_dccm_rdata_lo_m[0]}; // @[el2_lib.scala 333:184] + wire [17:0] _T_558 = {io_dccm_rdata_lo_m[31],io_dccm_rdata_lo_m[28],io_dccm_rdata_lo_m[27],io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[20],io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[16],_T_549}; // @[el2_lib.scala 333:184] + wire _T_559 = ^_T_558; // @[el2_lib.scala 333:191] + wire _T_560 = io_dccm_data_ecc_lo_m[1] ^ _T_559; // @[el2_lib.scala 333:179] + wire [8:0] _T_569 = {io_dccm_rdata_lo_m[13],io_dccm_rdata_lo_m[11],io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[8],io_dccm_rdata_lo_m[6],io_dccm_rdata_lo_m[4],io_dccm_rdata_lo_m[3],io_dccm_rdata_lo_m[1],io_dccm_rdata_lo_m[0]}; // @[el2_lib.scala 333:211] + wire [17:0] _T_578 = {io_dccm_rdata_lo_m[30],io_dccm_rdata_lo_m[28],io_dccm_rdata_lo_m[26],io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[19],io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[15],_T_569}; // @[el2_lib.scala 333:211] + wire _T_579 = ^_T_578; // @[el2_lib.scala 333:218] + wire _T_580 = io_dccm_data_ecc_lo_m[0] ^ _T_579; // @[el2_lib.scala 333:206] wire [6:0] _T_586 = {_T_476,_T_486,_T_503,_T_520,_T_540,_T_560,_T_580}; // @[Cat.scala 29:58] - wire _T_587 = _T_586 != 7'h0; // @[el2_lib.scala 325:44] - wire is_ldst_lo_m = is_ldst_m & _T_1155; // @[el2_lsu_ecc.scala 126:33] - wire _T_588 = is_ldst_lo_m & _T_587; // @[el2_lib.scala 325:32] - wire single_ecc_error_lo_any = _T_588 & _T_586[6]; // @[el2_lib.scala 325:53] - wire _T_593 = ~_T_586[6]; // @[el2_lib.scala 326:55] - wire double_ecc_error_lo_any = _T_588 & _T_593; // @[el2_lib.scala 326:53] - wire _T_596 = _T_586[5:0] == 6'h1; // @[el2_lib.scala 330:41] - wire _T_598 = _T_586[5:0] == 6'h2; // @[el2_lib.scala 330:41] - wire _T_600 = _T_586[5:0] == 6'h3; // @[el2_lib.scala 330:41] - wire _T_602 = _T_586[5:0] == 6'h4; // @[el2_lib.scala 330:41] - wire _T_604 = _T_586[5:0] == 6'h5; // @[el2_lib.scala 330:41] - wire _T_606 = _T_586[5:0] == 6'h6; // @[el2_lib.scala 330:41] - wire _T_608 = _T_586[5:0] == 6'h7; // @[el2_lib.scala 330:41] - wire _T_610 = _T_586[5:0] == 6'h8; // @[el2_lib.scala 330:41] - wire _T_612 = _T_586[5:0] == 6'h9; // @[el2_lib.scala 330:41] - wire _T_614 = _T_586[5:0] == 6'ha; // @[el2_lib.scala 330:41] - wire _T_616 = _T_586[5:0] == 6'hb; // @[el2_lib.scala 330:41] - wire _T_618 = _T_586[5:0] == 6'hc; // @[el2_lib.scala 330:41] - wire _T_620 = _T_586[5:0] == 6'hd; // @[el2_lib.scala 330:41] - wire _T_622 = _T_586[5:0] == 6'he; // @[el2_lib.scala 330:41] - wire _T_624 = _T_586[5:0] == 6'hf; // @[el2_lib.scala 330:41] - wire _T_626 = _T_586[5:0] == 6'h10; // @[el2_lib.scala 330:41] - wire _T_628 = _T_586[5:0] == 6'h11; // @[el2_lib.scala 330:41] - wire _T_630 = _T_586[5:0] == 6'h12; // @[el2_lib.scala 330:41] - wire _T_632 = _T_586[5:0] == 6'h13; // @[el2_lib.scala 330:41] - wire _T_634 = _T_586[5:0] == 6'h14; // @[el2_lib.scala 330:41] - wire _T_636 = _T_586[5:0] == 6'h15; // @[el2_lib.scala 330:41] - wire _T_638 = _T_586[5:0] == 6'h16; // @[el2_lib.scala 330:41] - wire _T_640 = _T_586[5:0] == 6'h17; // @[el2_lib.scala 330:41] - wire _T_642 = _T_586[5:0] == 6'h18; // @[el2_lib.scala 330:41] - wire _T_644 = _T_586[5:0] == 6'h19; // @[el2_lib.scala 330:41] - wire _T_646 = _T_586[5:0] == 6'h1a; // @[el2_lib.scala 330:41] - wire _T_648 = _T_586[5:0] == 6'h1b; // @[el2_lib.scala 330:41] - wire _T_650 = _T_586[5:0] == 6'h1c; // @[el2_lib.scala 330:41] - wire _T_652 = _T_586[5:0] == 6'h1d; // @[el2_lib.scala 330:41] - wire _T_654 = _T_586[5:0] == 6'h1e; // @[el2_lib.scala 330:41] - wire _T_656 = _T_586[5:0] == 6'h1f; // @[el2_lib.scala 330:41] - wire _T_658 = _T_586[5:0] == 6'h20; // @[el2_lib.scala 330:41] - wire _T_660 = _T_586[5:0] == 6'h21; // @[el2_lib.scala 330:41] - wire _T_662 = _T_586[5:0] == 6'h22; // @[el2_lib.scala 330:41] - wire _T_664 = _T_586[5:0] == 6'h23; // @[el2_lib.scala 330:41] - wire _T_666 = _T_586[5:0] == 6'h24; // @[el2_lib.scala 330:41] - wire _T_668 = _T_586[5:0] == 6'h25; // @[el2_lib.scala 330:41] - wire _T_670 = _T_586[5:0] == 6'h26; // @[el2_lib.scala 330:41] - wire _T_672 = _T_586[5:0] == 6'h27; // @[el2_lib.scala 330:41] + wire _T_587 = _T_586 != 7'h0; // @[el2_lib.scala 334:44] + wire is_ldst_lo_m = is_ldst_m & _T_1131; // @[el2_lsu_ecc.scala 126:33] + wire _T_588 = is_ldst_lo_m & _T_587; // @[el2_lib.scala 334:32] + wire single_ecc_error_lo_any = _T_588 & _T_586[6]; // @[el2_lib.scala 334:53] + wire _T_593 = ~_T_586[6]; // @[el2_lib.scala 335:55] + wire double_ecc_error_lo_any = _T_588 & _T_593; // @[el2_lib.scala 335:53] + wire _T_596 = _T_586[5:0] == 6'h1; // @[el2_lib.scala 339:41] + wire _T_598 = _T_586[5:0] == 6'h2; // @[el2_lib.scala 339:41] + wire _T_600 = _T_586[5:0] == 6'h3; // @[el2_lib.scala 339:41] + wire _T_602 = _T_586[5:0] == 6'h4; // @[el2_lib.scala 339:41] + wire _T_604 = _T_586[5:0] == 6'h5; // @[el2_lib.scala 339:41] + wire _T_606 = _T_586[5:0] == 6'h6; // @[el2_lib.scala 339:41] + wire _T_608 = _T_586[5:0] == 6'h7; // @[el2_lib.scala 339:41] + wire _T_610 = _T_586[5:0] == 6'h8; // @[el2_lib.scala 339:41] + wire _T_612 = _T_586[5:0] == 6'h9; // @[el2_lib.scala 339:41] + wire _T_614 = _T_586[5:0] == 6'ha; // @[el2_lib.scala 339:41] + wire _T_616 = _T_586[5:0] == 6'hb; // @[el2_lib.scala 339:41] + wire _T_618 = _T_586[5:0] == 6'hc; // @[el2_lib.scala 339:41] + wire _T_620 = _T_586[5:0] == 6'hd; // @[el2_lib.scala 339:41] + wire _T_622 = _T_586[5:0] == 6'he; // @[el2_lib.scala 339:41] + wire _T_624 = _T_586[5:0] == 6'hf; // @[el2_lib.scala 339:41] + wire _T_626 = _T_586[5:0] == 6'h10; // @[el2_lib.scala 339:41] + wire _T_628 = _T_586[5:0] == 6'h11; // @[el2_lib.scala 339:41] + wire _T_630 = _T_586[5:0] == 6'h12; // @[el2_lib.scala 339:41] + wire _T_632 = _T_586[5:0] == 6'h13; // @[el2_lib.scala 339:41] + wire _T_634 = _T_586[5:0] == 6'h14; // @[el2_lib.scala 339:41] + wire _T_636 = _T_586[5:0] == 6'h15; // @[el2_lib.scala 339:41] + wire _T_638 = _T_586[5:0] == 6'h16; // @[el2_lib.scala 339:41] + wire _T_640 = _T_586[5:0] == 6'h17; // @[el2_lib.scala 339:41] + wire _T_642 = _T_586[5:0] == 6'h18; // @[el2_lib.scala 339:41] + wire _T_644 = _T_586[5:0] == 6'h19; // @[el2_lib.scala 339:41] + wire _T_646 = _T_586[5:0] == 6'h1a; // @[el2_lib.scala 339:41] + wire _T_648 = _T_586[5:0] == 6'h1b; // @[el2_lib.scala 339:41] + wire _T_650 = _T_586[5:0] == 6'h1c; // @[el2_lib.scala 339:41] + wire _T_652 = _T_586[5:0] == 6'h1d; // @[el2_lib.scala 339:41] + wire _T_654 = _T_586[5:0] == 6'h1e; // @[el2_lib.scala 339:41] + wire _T_656 = _T_586[5:0] == 6'h1f; // @[el2_lib.scala 339:41] + wire _T_658 = _T_586[5:0] == 6'h20; // @[el2_lib.scala 339:41] + wire _T_660 = _T_586[5:0] == 6'h21; // @[el2_lib.scala 339:41] + wire _T_662 = _T_586[5:0] == 6'h22; // @[el2_lib.scala 339:41] + wire _T_664 = _T_586[5:0] == 6'h23; // @[el2_lib.scala 339:41] + wire _T_666 = _T_586[5:0] == 6'h24; // @[el2_lib.scala 339:41] + wire _T_668 = _T_586[5:0] == 6'h25; // @[el2_lib.scala 339:41] + wire _T_670 = _T_586[5:0] == 6'h26; // @[el2_lib.scala 339:41] + wire _T_672 = _T_586[5:0] == 6'h27; // @[el2_lib.scala 339:41] wire [7:0] _T_687 = {io_dccm_data_ecc_lo_m[3],io_dccm_rdata_lo_m[3:1],io_dccm_data_ecc_lo_m[2],io_dccm_rdata_lo_m[0],io_dccm_data_ecc_lo_m[1:0]}; // @[Cat.scala 29:58] wire [38:0] _T_693 = {io_dccm_data_ecc_lo_m[6],io_dccm_rdata_lo_m[31:26],io_dccm_data_ecc_lo_m[5],io_dccm_rdata_lo_m[25:11],io_dccm_data_ecc_lo_m[4],io_dccm_rdata_lo_m[10:4],_T_687}; // @[Cat.scala 29:58] - wire [9:0] _T_711 = {_T_632,_T_630,_T_628,_T_626,_T_624,_T_622,_T_620,_T_618,_T_616,_T_614}; // @[el2_lib.scala 333:69] - wire [18:0] _T_712 = {_T_711,_T_612,_T_610,_T_608,_T_606,_T_604,_T_602,_T_600,_T_598,_T_596}; // @[el2_lib.scala 333:69] - wire [9:0] _T_721 = {_T_652,_T_650,_T_648,_T_646,_T_644,_T_642,_T_640,_T_638,_T_636,_T_634}; // @[el2_lib.scala 333:69] - wire [9:0] _T_730 = {_T_672,_T_670,_T_668,_T_666,_T_664,_T_662,_T_660,_T_658,_T_656,_T_654}; // @[el2_lib.scala 333:69] - wire [38:0] _T_732 = {_T_730,_T_721,_T_712}; // @[el2_lib.scala 333:69] - wire [38:0] _T_733 = _T_732 ^ _T_693; // @[el2_lib.scala 333:76] - wire [38:0] _T_734 = single_ecc_error_lo_any ? _T_733 : _T_693; // @[el2_lib.scala 333:31] + wire [9:0] _T_711 = {_T_632,_T_630,_T_628,_T_626,_T_624,_T_622,_T_620,_T_618,_T_616,_T_614}; // @[el2_lib.scala 342:69] + wire [18:0] _T_712 = {_T_711,_T_612,_T_610,_T_608,_T_606,_T_604,_T_602,_T_600,_T_598,_T_596}; // @[el2_lib.scala 342:69] + wire [9:0] _T_721 = {_T_652,_T_650,_T_648,_T_646,_T_644,_T_642,_T_640,_T_638,_T_636,_T_634}; // @[el2_lib.scala 342:69] + wire [9:0] _T_730 = {_T_672,_T_670,_T_668,_T_666,_T_664,_T_662,_T_660,_T_658,_T_656,_T_654}; // @[el2_lib.scala 342:69] + wire [38:0] _T_732 = {_T_730,_T_721,_T_712}; // @[el2_lib.scala 342:69] + wire [38:0] _T_733 = _T_732 ^ _T_693; // @[el2_lib.scala 342:76] + wire [38:0] _T_734 = single_ecc_error_lo_any ? _T_733 : _T_693; // @[el2_lib.scala 342:31] wire [3:0] _T_740 = {_T_734[6:4],_T_734[2]}; // @[Cat.scala 29:58] wire [27:0] _T_742 = {_T_734[37:32],_T_734[30:16],_T_734[14:8]}; // @[Cat.scala 29:58] - wire [31:0] _T_1182 = io_dma_dccm_wen ? io_dma_dccm_wdata_lo : io_stbuf_data_any; // @[el2_lsu_ecc.scala 149:89] - wire [31:0] dccm_wdata_lo_any = io_ld_single_ecc_error_r_ff ? io_sec_data_lo_r_ff : _T_1182; // @[el2_lsu_ecc.scala 149:29] - wire [5:0] _T_856 = {dccm_wdata_lo_any[31],dccm_wdata_lo_any[30],dccm_wdata_lo_any[29],dccm_wdata_lo_any[28],dccm_wdata_lo_any[27],dccm_wdata_lo_any[26]}; // @[el2_lib.scala 287:22] - wire _T_857 = ^_T_856; // @[el2_lib.scala 287:29] - wire [6:0] _T_863 = {dccm_wdata_lo_any[17],dccm_wdata_lo_any[16],dccm_wdata_lo_any[15],dccm_wdata_lo_any[14],dccm_wdata_lo_any[13],dccm_wdata_lo_any[12],dccm_wdata_lo_any[11]}; // @[el2_lib.scala 287:39] - wire [14:0] _T_871 = {dccm_wdata_lo_any[25],dccm_wdata_lo_any[24],dccm_wdata_lo_any[23],dccm_wdata_lo_any[22],dccm_wdata_lo_any[21],dccm_wdata_lo_any[20],dccm_wdata_lo_any[19],dccm_wdata_lo_any[18],_T_863}; // @[el2_lib.scala 287:39] - wire _T_872 = ^_T_871; // @[el2_lib.scala 287:46] - wire [6:0] _T_878 = {dccm_wdata_lo_any[10],dccm_wdata_lo_any[9],dccm_wdata_lo_any[8],dccm_wdata_lo_any[7],dccm_wdata_lo_any[6],dccm_wdata_lo_any[5],dccm_wdata_lo_any[4]}; // @[el2_lib.scala 287:56] - wire [14:0] _T_886 = {dccm_wdata_lo_any[25],dccm_wdata_lo_any[24],dccm_wdata_lo_any[23],dccm_wdata_lo_any[22],dccm_wdata_lo_any[21],dccm_wdata_lo_any[20],dccm_wdata_lo_any[19],dccm_wdata_lo_any[18],_T_878}; // @[el2_lib.scala 287:56] - wire _T_887 = ^_T_886; // @[el2_lib.scala 287:63] - wire [8:0] _T_895 = {dccm_wdata_lo_any[15],dccm_wdata_lo_any[14],dccm_wdata_lo_any[10],dccm_wdata_lo_any[9],dccm_wdata_lo_any[8],dccm_wdata_lo_any[7],dccm_wdata_lo_any[3],dccm_wdata_lo_any[2],dccm_wdata_lo_any[1]}; // @[el2_lib.scala 287:73] - wire [17:0] _T_904 = {dccm_wdata_lo_any[31],dccm_wdata_lo_any[30],dccm_wdata_lo_any[29],dccm_wdata_lo_any[25],dccm_wdata_lo_any[24],dccm_wdata_lo_any[23],dccm_wdata_lo_any[22],dccm_wdata_lo_any[17],dccm_wdata_lo_any[16],_T_895}; // @[el2_lib.scala 287:73] - wire _T_905 = ^_T_904; // @[el2_lib.scala 287:80] - wire [8:0] _T_913 = {dccm_wdata_lo_any[13],dccm_wdata_lo_any[12],dccm_wdata_lo_any[10],dccm_wdata_lo_any[9],dccm_wdata_lo_any[6],dccm_wdata_lo_any[5],dccm_wdata_lo_any[3],dccm_wdata_lo_any[2],dccm_wdata_lo_any[0]}; // @[el2_lib.scala 287:90] - wire [17:0] _T_922 = {dccm_wdata_lo_any[31],dccm_wdata_lo_any[28],dccm_wdata_lo_any[27],dccm_wdata_lo_any[25],dccm_wdata_lo_any[24],dccm_wdata_lo_any[21],dccm_wdata_lo_any[20],dccm_wdata_lo_any[17],dccm_wdata_lo_any[16],_T_913}; // @[el2_lib.scala 287:90] - wire _T_923 = ^_T_922; // @[el2_lib.scala 287:97] - wire [8:0] _T_931 = {dccm_wdata_lo_any[13],dccm_wdata_lo_any[11],dccm_wdata_lo_any[10],dccm_wdata_lo_any[8],dccm_wdata_lo_any[6],dccm_wdata_lo_any[4],dccm_wdata_lo_any[3],dccm_wdata_lo_any[1],dccm_wdata_lo_any[0]}; // @[el2_lib.scala 287:107] - wire [17:0] _T_940 = {dccm_wdata_lo_any[30],dccm_wdata_lo_any[28],dccm_wdata_lo_any[26],dccm_wdata_lo_any[25],dccm_wdata_lo_any[23],dccm_wdata_lo_any[21],dccm_wdata_lo_any[19],dccm_wdata_lo_any[17],dccm_wdata_lo_any[15],_T_931}; // @[el2_lib.scala 287:107] - wire _T_941 = ^_T_940; // @[el2_lib.scala 287:114] - wire [5:0] _T_946 = {_T_857,_T_872,_T_887,_T_905,_T_923,_T_941}; // @[Cat.scala 29:58] - wire _T_947 = ^dccm_wdata_lo_any; // @[el2_lib.scala 288:27] - wire _T_948 = ^_T_946; // @[el2_lib.scala 288:37] - wire _T_949 = _T_947 ^ _T_948; // @[el2_lib.scala 288:32] - wire [31:0] _T_1186 = io_dma_dccm_wen ? io_dma_dccm_wdata_hi : io_stbuf_data_any; // @[el2_lsu_ecc.scala 150:89] - wire [31:0] dccm_wdata_hi_any = io_ld_single_ecc_error_r_ff ? io_sec_data_hi_r_ff : _T_1186; // @[el2_lsu_ecc.scala 150:29] - wire [5:0] _T_1050 = {dccm_wdata_hi_any[31],dccm_wdata_hi_any[30],dccm_wdata_hi_any[29],dccm_wdata_hi_any[28],dccm_wdata_hi_any[27],dccm_wdata_hi_any[26]}; // @[el2_lib.scala 287:22] - wire _T_1051 = ^_T_1050; // @[el2_lib.scala 287:29] - wire [6:0] _T_1057 = {dccm_wdata_hi_any[17],dccm_wdata_hi_any[16],dccm_wdata_hi_any[15],dccm_wdata_hi_any[14],dccm_wdata_hi_any[13],dccm_wdata_hi_any[12],dccm_wdata_hi_any[11]}; // @[el2_lib.scala 287:39] - wire [14:0] _T_1065 = {dccm_wdata_hi_any[25],dccm_wdata_hi_any[24],dccm_wdata_hi_any[23],dccm_wdata_hi_any[22],dccm_wdata_hi_any[21],dccm_wdata_hi_any[20],dccm_wdata_hi_any[19],dccm_wdata_hi_any[18],_T_1057}; // @[el2_lib.scala 287:39] - wire _T_1066 = ^_T_1065; // @[el2_lib.scala 287:46] - wire [6:0] _T_1072 = {dccm_wdata_hi_any[10],dccm_wdata_hi_any[9],dccm_wdata_hi_any[8],dccm_wdata_hi_any[7],dccm_wdata_hi_any[6],dccm_wdata_hi_any[5],dccm_wdata_hi_any[4]}; // @[el2_lib.scala 287:56] - wire [14:0] _T_1080 = {dccm_wdata_hi_any[25],dccm_wdata_hi_any[24],dccm_wdata_hi_any[23],dccm_wdata_hi_any[22],dccm_wdata_hi_any[21],dccm_wdata_hi_any[20],dccm_wdata_hi_any[19],dccm_wdata_hi_any[18],_T_1072}; // @[el2_lib.scala 287:56] - wire _T_1081 = ^_T_1080; // @[el2_lib.scala 287:63] - wire [8:0] _T_1089 = {dccm_wdata_hi_any[15],dccm_wdata_hi_any[14],dccm_wdata_hi_any[10],dccm_wdata_hi_any[9],dccm_wdata_hi_any[8],dccm_wdata_hi_any[7],dccm_wdata_hi_any[3],dccm_wdata_hi_any[2],dccm_wdata_hi_any[1]}; // @[el2_lib.scala 287:73] - wire [17:0] _T_1098 = {dccm_wdata_hi_any[31],dccm_wdata_hi_any[30],dccm_wdata_hi_any[29],dccm_wdata_hi_any[25],dccm_wdata_hi_any[24],dccm_wdata_hi_any[23],dccm_wdata_hi_any[22],dccm_wdata_hi_any[17],dccm_wdata_hi_any[16],_T_1089}; // @[el2_lib.scala 287:73] - wire _T_1099 = ^_T_1098; // @[el2_lib.scala 287:80] - wire [8:0] _T_1107 = {dccm_wdata_hi_any[13],dccm_wdata_hi_any[12],dccm_wdata_hi_any[10],dccm_wdata_hi_any[9],dccm_wdata_hi_any[6],dccm_wdata_hi_any[5],dccm_wdata_hi_any[3],dccm_wdata_hi_any[2],dccm_wdata_hi_any[0]}; // @[el2_lib.scala 287:90] - wire [17:0] _T_1116 = {dccm_wdata_hi_any[31],dccm_wdata_hi_any[28],dccm_wdata_hi_any[27],dccm_wdata_hi_any[25],dccm_wdata_hi_any[24],dccm_wdata_hi_any[21],dccm_wdata_hi_any[20],dccm_wdata_hi_any[17],dccm_wdata_hi_any[16],_T_1107}; // @[el2_lib.scala 287:90] - wire _T_1117 = ^_T_1116; // @[el2_lib.scala 287:97] - wire [8:0] _T_1125 = {dccm_wdata_hi_any[13],dccm_wdata_hi_any[11],dccm_wdata_hi_any[10],dccm_wdata_hi_any[8],dccm_wdata_hi_any[6],dccm_wdata_hi_any[4],dccm_wdata_hi_any[3],dccm_wdata_hi_any[1],dccm_wdata_hi_any[0]}; // @[el2_lib.scala 287:107] - wire [17:0] _T_1134 = {dccm_wdata_hi_any[30],dccm_wdata_hi_any[28],dccm_wdata_hi_any[26],dccm_wdata_hi_any[25],dccm_wdata_hi_any[23],dccm_wdata_hi_any[21],dccm_wdata_hi_any[19],dccm_wdata_hi_any[17],dccm_wdata_hi_any[15],_T_1125}; // @[el2_lib.scala 287:107] - wire _T_1135 = ^_T_1134; // @[el2_lib.scala 287:114] - wire [5:0] _T_1140 = {_T_1051,_T_1066,_T_1081,_T_1099,_T_1117,_T_1135}; // @[Cat.scala 29:58] - wire _T_1141 = ^dccm_wdata_hi_any; // @[el2_lib.scala 288:27] - wire _T_1142 = ^_T_1140; // @[el2_lib.scala 288:37] - wire _T_1143 = _T_1141 ^ _T_1142; // @[el2_lib.scala 288:32] - reg _T_1174; // @[el2_lsu_ecc.scala 141:72] - reg _T_1175; // @[el2_lsu_ecc.scala 142:72] - reg _T_1176; // @[el2_lsu_ecc.scala 143:72] - reg _T_1177; // @[el2_lsu_ecc.scala 144:72] - reg [31:0] _T_1178; // @[el2_lsu_ecc.scala 145:72] - reg [31:0] _T_1179; // @[el2_lsu_ecc.scala 146:72] - reg [31:0] _T_1188; // @[beh_lib.scala 358:14] - reg [31:0] _T_1189; // @[beh_lib.scala 358:14] - rvclkhdr rvclkhdr ( // @[beh_lib.scala 352:21] + wire [31:0] _T_1158 = io_dma_dccm_wen ? io_dma_dccm_wdata_lo : io_stbuf_data_any; // @[el2_lsu_ecc.scala 149:87] + wire [31:0] dccm_wdata_lo_any = io_ld_single_ecc_error_r_ff ? io_sec_data_lo_r_ff : _T_1158; // @[el2_lsu_ecc.scala 149:27] + wire _T_774 = dccm_wdata_lo_any[0] ^ dccm_wdata_lo_any[1]; // @[el2_lib.scala 259:74] + wire _T_775 = _T_774 ^ dccm_wdata_lo_any[3]; // @[el2_lib.scala 259:74] + wire _T_776 = _T_775 ^ dccm_wdata_lo_any[4]; // @[el2_lib.scala 259:74] + wire _T_777 = _T_776 ^ dccm_wdata_lo_any[6]; // @[el2_lib.scala 259:74] + wire _T_778 = _T_777 ^ dccm_wdata_lo_any[8]; // @[el2_lib.scala 259:74] + wire _T_779 = _T_778 ^ dccm_wdata_lo_any[10]; // @[el2_lib.scala 259:74] + wire _T_780 = _T_779 ^ dccm_wdata_lo_any[11]; // @[el2_lib.scala 259:74] + wire _T_781 = _T_780 ^ dccm_wdata_lo_any[13]; // @[el2_lib.scala 259:74] + wire _T_782 = _T_781 ^ dccm_wdata_lo_any[15]; // @[el2_lib.scala 259:74] + wire _T_783 = _T_782 ^ dccm_wdata_lo_any[17]; // @[el2_lib.scala 259:74] + wire _T_784 = _T_783 ^ dccm_wdata_lo_any[19]; // @[el2_lib.scala 259:74] + wire _T_785 = _T_784 ^ dccm_wdata_lo_any[21]; // @[el2_lib.scala 259:74] + wire _T_786 = _T_785 ^ dccm_wdata_lo_any[23]; // @[el2_lib.scala 259:74] + wire _T_787 = _T_786 ^ dccm_wdata_lo_any[25]; // @[el2_lib.scala 259:74] + wire _T_788 = _T_787 ^ dccm_wdata_lo_any[26]; // @[el2_lib.scala 259:74] + wire _T_789 = _T_788 ^ dccm_wdata_lo_any[28]; // @[el2_lib.scala 259:74] + wire _T_790 = _T_789 ^ dccm_wdata_lo_any[30]; // @[el2_lib.scala 259:74] + wire _T_809 = dccm_wdata_lo_any[0] ^ dccm_wdata_lo_any[2]; // @[el2_lib.scala 259:74] + wire _T_810 = _T_809 ^ dccm_wdata_lo_any[3]; // @[el2_lib.scala 259:74] + wire _T_811 = _T_810 ^ dccm_wdata_lo_any[5]; // @[el2_lib.scala 259:74] + wire _T_812 = _T_811 ^ dccm_wdata_lo_any[6]; // @[el2_lib.scala 259:74] + wire _T_813 = _T_812 ^ dccm_wdata_lo_any[9]; // @[el2_lib.scala 259:74] + wire _T_814 = _T_813 ^ dccm_wdata_lo_any[10]; // @[el2_lib.scala 259:74] + wire _T_815 = _T_814 ^ dccm_wdata_lo_any[12]; // @[el2_lib.scala 259:74] + wire _T_816 = _T_815 ^ dccm_wdata_lo_any[13]; // @[el2_lib.scala 259:74] + wire _T_817 = _T_816 ^ dccm_wdata_lo_any[16]; // @[el2_lib.scala 259:74] + wire _T_818 = _T_817 ^ dccm_wdata_lo_any[17]; // @[el2_lib.scala 259:74] + wire _T_819 = _T_818 ^ dccm_wdata_lo_any[20]; // @[el2_lib.scala 259:74] + wire _T_820 = _T_819 ^ dccm_wdata_lo_any[21]; // @[el2_lib.scala 259:74] + wire _T_821 = _T_820 ^ dccm_wdata_lo_any[24]; // @[el2_lib.scala 259:74] + wire _T_822 = _T_821 ^ dccm_wdata_lo_any[25]; // @[el2_lib.scala 259:74] + wire _T_823 = _T_822 ^ dccm_wdata_lo_any[27]; // @[el2_lib.scala 259:74] + wire _T_824 = _T_823 ^ dccm_wdata_lo_any[28]; // @[el2_lib.scala 259:74] + wire _T_825 = _T_824 ^ dccm_wdata_lo_any[31]; // @[el2_lib.scala 259:74] + wire _T_844 = dccm_wdata_lo_any[1] ^ dccm_wdata_lo_any[2]; // @[el2_lib.scala 259:74] + wire _T_845 = _T_844 ^ dccm_wdata_lo_any[3]; // @[el2_lib.scala 259:74] + wire _T_846 = _T_845 ^ dccm_wdata_lo_any[7]; // @[el2_lib.scala 259:74] + wire _T_847 = _T_846 ^ dccm_wdata_lo_any[8]; // @[el2_lib.scala 259:74] + wire _T_848 = _T_847 ^ dccm_wdata_lo_any[9]; // @[el2_lib.scala 259:74] + wire _T_849 = _T_848 ^ dccm_wdata_lo_any[10]; // @[el2_lib.scala 259:74] + wire _T_850 = _T_849 ^ dccm_wdata_lo_any[14]; // @[el2_lib.scala 259:74] + wire _T_851 = _T_850 ^ dccm_wdata_lo_any[15]; // @[el2_lib.scala 259:74] + wire _T_852 = _T_851 ^ dccm_wdata_lo_any[16]; // @[el2_lib.scala 259:74] + wire _T_853 = _T_852 ^ dccm_wdata_lo_any[17]; // @[el2_lib.scala 259:74] + wire _T_854 = _T_853 ^ dccm_wdata_lo_any[22]; // @[el2_lib.scala 259:74] + wire _T_855 = _T_854 ^ dccm_wdata_lo_any[23]; // @[el2_lib.scala 259:74] + wire _T_856 = _T_855 ^ dccm_wdata_lo_any[24]; // @[el2_lib.scala 259:74] + wire _T_857 = _T_856 ^ dccm_wdata_lo_any[25]; // @[el2_lib.scala 259:74] + wire _T_858 = _T_857 ^ dccm_wdata_lo_any[29]; // @[el2_lib.scala 259:74] + wire _T_859 = _T_858 ^ dccm_wdata_lo_any[30]; // @[el2_lib.scala 259:74] + wire _T_860 = _T_859 ^ dccm_wdata_lo_any[31]; // @[el2_lib.scala 259:74] + wire _T_876 = dccm_wdata_lo_any[4] ^ dccm_wdata_lo_any[5]; // @[el2_lib.scala 259:74] + wire _T_877 = _T_876 ^ dccm_wdata_lo_any[6]; // @[el2_lib.scala 259:74] + wire _T_878 = _T_877 ^ dccm_wdata_lo_any[7]; // @[el2_lib.scala 259:74] + wire _T_879 = _T_878 ^ dccm_wdata_lo_any[8]; // @[el2_lib.scala 259:74] + wire _T_880 = _T_879 ^ dccm_wdata_lo_any[9]; // @[el2_lib.scala 259:74] + wire _T_881 = _T_880 ^ dccm_wdata_lo_any[10]; // @[el2_lib.scala 259:74] + wire _T_882 = _T_881 ^ dccm_wdata_lo_any[18]; // @[el2_lib.scala 259:74] + wire _T_883 = _T_882 ^ dccm_wdata_lo_any[19]; // @[el2_lib.scala 259:74] + wire _T_884 = _T_883 ^ dccm_wdata_lo_any[20]; // @[el2_lib.scala 259:74] + wire _T_885 = _T_884 ^ dccm_wdata_lo_any[21]; // @[el2_lib.scala 259:74] + wire _T_886 = _T_885 ^ dccm_wdata_lo_any[22]; // @[el2_lib.scala 259:74] + wire _T_887 = _T_886 ^ dccm_wdata_lo_any[23]; // @[el2_lib.scala 259:74] + wire _T_888 = _T_887 ^ dccm_wdata_lo_any[24]; // @[el2_lib.scala 259:74] + wire _T_889 = _T_888 ^ dccm_wdata_lo_any[25]; // @[el2_lib.scala 259:74] + wire _T_905 = dccm_wdata_lo_any[11] ^ dccm_wdata_lo_any[12]; // @[el2_lib.scala 259:74] + wire _T_906 = _T_905 ^ dccm_wdata_lo_any[13]; // @[el2_lib.scala 259:74] + wire _T_907 = _T_906 ^ dccm_wdata_lo_any[14]; // @[el2_lib.scala 259:74] + wire _T_908 = _T_907 ^ dccm_wdata_lo_any[15]; // @[el2_lib.scala 259:74] + wire _T_909 = _T_908 ^ dccm_wdata_lo_any[16]; // @[el2_lib.scala 259:74] + wire _T_910 = _T_909 ^ dccm_wdata_lo_any[17]; // @[el2_lib.scala 259:74] + wire _T_911 = _T_910 ^ dccm_wdata_lo_any[18]; // @[el2_lib.scala 259:74] + wire _T_912 = _T_911 ^ dccm_wdata_lo_any[19]; // @[el2_lib.scala 259:74] + wire _T_913 = _T_912 ^ dccm_wdata_lo_any[20]; // @[el2_lib.scala 259:74] + wire _T_914 = _T_913 ^ dccm_wdata_lo_any[21]; // @[el2_lib.scala 259:74] + wire _T_915 = _T_914 ^ dccm_wdata_lo_any[22]; // @[el2_lib.scala 259:74] + wire _T_916 = _T_915 ^ dccm_wdata_lo_any[23]; // @[el2_lib.scala 259:74] + wire _T_917 = _T_916 ^ dccm_wdata_lo_any[24]; // @[el2_lib.scala 259:74] + wire _T_918 = _T_917 ^ dccm_wdata_lo_any[25]; // @[el2_lib.scala 259:74] + wire _T_925 = dccm_wdata_lo_any[26] ^ dccm_wdata_lo_any[27]; // @[el2_lib.scala 259:74] + wire _T_926 = _T_925 ^ dccm_wdata_lo_any[28]; // @[el2_lib.scala 259:74] + wire _T_927 = _T_926 ^ dccm_wdata_lo_any[29]; // @[el2_lib.scala 259:74] + wire _T_928 = _T_927 ^ dccm_wdata_lo_any[30]; // @[el2_lib.scala 259:74] + wire _T_929 = _T_928 ^ dccm_wdata_lo_any[31]; // @[el2_lib.scala 259:74] + wire [5:0] _T_934 = {_T_929,_T_918,_T_889,_T_860,_T_825,_T_790}; // @[Cat.scala 29:58] + wire _T_935 = ^dccm_wdata_lo_any; // @[el2_lib.scala 267:13] + wire _T_936 = ^_T_934; // @[el2_lib.scala 267:23] + wire _T_937 = _T_935 ^ _T_936; // @[el2_lib.scala 267:18] + wire [31:0] _T_1162 = io_dma_dccm_wen ? io_dma_dccm_wdata_hi : io_stbuf_data_any; // @[el2_lsu_ecc.scala 150:87] + wire [31:0] dccm_wdata_hi_any = io_ld_single_ecc_error_r_ff ? io_sec_data_hi_r_ff : _T_1162; // @[el2_lsu_ecc.scala 150:27] + wire _T_956 = dccm_wdata_hi_any[0] ^ dccm_wdata_hi_any[1]; // @[el2_lib.scala 259:74] + wire _T_957 = _T_956 ^ dccm_wdata_hi_any[3]; // @[el2_lib.scala 259:74] + wire _T_958 = _T_957 ^ dccm_wdata_hi_any[4]; // @[el2_lib.scala 259:74] + wire _T_959 = _T_958 ^ dccm_wdata_hi_any[6]; // @[el2_lib.scala 259:74] + wire _T_960 = _T_959 ^ dccm_wdata_hi_any[8]; // @[el2_lib.scala 259:74] + wire _T_961 = _T_960 ^ dccm_wdata_hi_any[10]; // @[el2_lib.scala 259:74] + wire _T_962 = _T_961 ^ dccm_wdata_hi_any[11]; // @[el2_lib.scala 259:74] + wire _T_963 = _T_962 ^ dccm_wdata_hi_any[13]; // @[el2_lib.scala 259:74] + wire _T_964 = _T_963 ^ dccm_wdata_hi_any[15]; // @[el2_lib.scala 259:74] + wire _T_965 = _T_964 ^ dccm_wdata_hi_any[17]; // @[el2_lib.scala 259:74] + wire _T_966 = _T_965 ^ dccm_wdata_hi_any[19]; // @[el2_lib.scala 259:74] + wire _T_967 = _T_966 ^ dccm_wdata_hi_any[21]; // @[el2_lib.scala 259:74] + wire _T_968 = _T_967 ^ dccm_wdata_hi_any[23]; // @[el2_lib.scala 259:74] + wire _T_969 = _T_968 ^ dccm_wdata_hi_any[25]; // @[el2_lib.scala 259:74] + wire _T_970 = _T_969 ^ dccm_wdata_hi_any[26]; // @[el2_lib.scala 259:74] + wire _T_971 = _T_970 ^ dccm_wdata_hi_any[28]; // @[el2_lib.scala 259:74] + wire _T_972 = _T_971 ^ dccm_wdata_hi_any[30]; // @[el2_lib.scala 259:74] + wire _T_991 = dccm_wdata_hi_any[0] ^ dccm_wdata_hi_any[2]; // @[el2_lib.scala 259:74] + wire _T_992 = _T_991 ^ dccm_wdata_hi_any[3]; // @[el2_lib.scala 259:74] + wire _T_993 = _T_992 ^ dccm_wdata_hi_any[5]; // @[el2_lib.scala 259:74] + wire _T_994 = _T_993 ^ dccm_wdata_hi_any[6]; // @[el2_lib.scala 259:74] + wire _T_995 = _T_994 ^ dccm_wdata_hi_any[9]; // @[el2_lib.scala 259:74] + wire _T_996 = _T_995 ^ dccm_wdata_hi_any[10]; // @[el2_lib.scala 259:74] + wire _T_997 = _T_996 ^ dccm_wdata_hi_any[12]; // @[el2_lib.scala 259:74] + wire _T_998 = _T_997 ^ dccm_wdata_hi_any[13]; // @[el2_lib.scala 259:74] + wire _T_999 = _T_998 ^ dccm_wdata_hi_any[16]; // @[el2_lib.scala 259:74] + wire _T_1000 = _T_999 ^ dccm_wdata_hi_any[17]; // @[el2_lib.scala 259:74] + wire _T_1001 = _T_1000 ^ dccm_wdata_hi_any[20]; // @[el2_lib.scala 259:74] + wire _T_1002 = _T_1001 ^ dccm_wdata_hi_any[21]; // @[el2_lib.scala 259:74] + wire _T_1003 = _T_1002 ^ dccm_wdata_hi_any[24]; // @[el2_lib.scala 259:74] + wire _T_1004 = _T_1003 ^ dccm_wdata_hi_any[25]; // @[el2_lib.scala 259:74] + wire _T_1005 = _T_1004 ^ dccm_wdata_hi_any[27]; // @[el2_lib.scala 259:74] + wire _T_1006 = _T_1005 ^ dccm_wdata_hi_any[28]; // @[el2_lib.scala 259:74] + wire _T_1007 = _T_1006 ^ dccm_wdata_hi_any[31]; // @[el2_lib.scala 259:74] + wire _T_1026 = dccm_wdata_hi_any[1] ^ dccm_wdata_hi_any[2]; // @[el2_lib.scala 259:74] + wire _T_1027 = _T_1026 ^ dccm_wdata_hi_any[3]; // @[el2_lib.scala 259:74] + wire _T_1028 = _T_1027 ^ dccm_wdata_hi_any[7]; // @[el2_lib.scala 259:74] + wire _T_1029 = _T_1028 ^ dccm_wdata_hi_any[8]; // @[el2_lib.scala 259:74] + wire _T_1030 = _T_1029 ^ dccm_wdata_hi_any[9]; // @[el2_lib.scala 259:74] + wire _T_1031 = _T_1030 ^ dccm_wdata_hi_any[10]; // @[el2_lib.scala 259:74] + wire _T_1032 = _T_1031 ^ dccm_wdata_hi_any[14]; // @[el2_lib.scala 259:74] + wire _T_1033 = _T_1032 ^ dccm_wdata_hi_any[15]; // @[el2_lib.scala 259:74] + wire _T_1034 = _T_1033 ^ dccm_wdata_hi_any[16]; // @[el2_lib.scala 259:74] + wire _T_1035 = _T_1034 ^ dccm_wdata_hi_any[17]; // @[el2_lib.scala 259:74] + wire _T_1036 = _T_1035 ^ dccm_wdata_hi_any[22]; // @[el2_lib.scala 259:74] + wire _T_1037 = _T_1036 ^ dccm_wdata_hi_any[23]; // @[el2_lib.scala 259:74] + wire _T_1038 = _T_1037 ^ dccm_wdata_hi_any[24]; // @[el2_lib.scala 259:74] + wire _T_1039 = _T_1038 ^ dccm_wdata_hi_any[25]; // @[el2_lib.scala 259:74] + wire _T_1040 = _T_1039 ^ dccm_wdata_hi_any[29]; // @[el2_lib.scala 259:74] + wire _T_1041 = _T_1040 ^ dccm_wdata_hi_any[30]; // @[el2_lib.scala 259:74] + wire _T_1042 = _T_1041 ^ dccm_wdata_hi_any[31]; // @[el2_lib.scala 259:74] + wire _T_1058 = dccm_wdata_hi_any[4] ^ dccm_wdata_hi_any[5]; // @[el2_lib.scala 259:74] + wire _T_1059 = _T_1058 ^ dccm_wdata_hi_any[6]; // @[el2_lib.scala 259:74] + wire _T_1060 = _T_1059 ^ dccm_wdata_hi_any[7]; // @[el2_lib.scala 259:74] + wire _T_1061 = _T_1060 ^ dccm_wdata_hi_any[8]; // @[el2_lib.scala 259:74] + wire _T_1062 = _T_1061 ^ dccm_wdata_hi_any[9]; // @[el2_lib.scala 259:74] + wire _T_1063 = _T_1062 ^ dccm_wdata_hi_any[10]; // @[el2_lib.scala 259:74] + wire _T_1064 = _T_1063 ^ dccm_wdata_hi_any[18]; // @[el2_lib.scala 259:74] + wire _T_1065 = _T_1064 ^ dccm_wdata_hi_any[19]; // @[el2_lib.scala 259:74] + wire _T_1066 = _T_1065 ^ dccm_wdata_hi_any[20]; // @[el2_lib.scala 259:74] + wire _T_1067 = _T_1066 ^ dccm_wdata_hi_any[21]; // @[el2_lib.scala 259:74] + wire _T_1068 = _T_1067 ^ dccm_wdata_hi_any[22]; // @[el2_lib.scala 259:74] + wire _T_1069 = _T_1068 ^ dccm_wdata_hi_any[23]; // @[el2_lib.scala 259:74] + wire _T_1070 = _T_1069 ^ dccm_wdata_hi_any[24]; // @[el2_lib.scala 259:74] + wire _T_1071 = _T_1070 ^ dccm_wdata_hi_any[25]; // @[el2_lib.scala 259:74] + wire _T_1087 = dccm_wdata_hi_any[11] ^ dccm_wdata_hi_any[12]; // @[el2_lib.scala 259:74] + wire _T_1088 = _T_1087 ^ dccm_wdata_hi_any[13]; // @[el2_lib.scala 259:74] + wire _T_1089 = _T_1088 ^ dccm_wdata_hi_any[14]; // @[el2_lib.scala 259:74] + wire _T_1090 = _T_1089 ^ dccm_wdata_hi_any[15]; // @[el2_lib.scala 259:74] + wire _T_1091 = _T_1090 ^ dccm_wdata_hi_any[16]; // @[el2_lib.scala 259:74] + wire _T_1092 = _T_1091 ^ dccm_wdata_hi_any[17]; // @[el2_lib.scala 259:74] + wire _T_1093 = _T_1092 ^ dccm_wdata_hi_any[18]; // @[el2_lib.scala 259:74] + wire _T_1094 = _T_1093 ^ dccm_wdata_hi_any[19]; // @[el2_lib.scala 259:74] + wire _T_1095 = _T_1094 ^ dccm_wdata_hi_any[20]; // @[el2_lib.scala 259:74] + wire _T_1096 = _T_1095 ^ dccm_wdata_hi_any[21]; // @[el2_lib.scala 259:74] + wire _T_1097 = _T_1096 ^ dccm_wdata_hi_any[22]; // @[el2_lib.scala 259:74] + wire _T_1098 = _T_1097 ^ dccm_wdata_hi_any[23]; // @[el2_lib.scala 259:74] + wire _T_1099 = _T_1098 ^ dccm_wdata_hi_any[24]; // @[el2_lib.scala 259:74] + wire _T_1100 = _T_1099 ^ dccm_wdata_hi_any[25]; // @[el2_lib.scala 259:74] + wire _T_1107 = dccm_wdata_hi_any[26] ^ dccm_wdata_hi_any[27]; // @[el2_lib.scala 259:74] + wire _T_1108 = _T_1107 ^ dccm_wdata_hi_any[28]; // @[el2_lib.scala 259:74] + wire _T_1109 = _T_1108 ^ dccm_wdata_hi_any[29]; // @[el2_lib.scala 259:74] + wire _T_1110 = _T_1109 ^ dccm_wdata_hi_any[30]; // @[el2_lib.scala 259:74] + wire _T_1111 = _T_1110 ^ dccm_wdata_hi_any[31]; // @[el2_lib.scala 259:74] + wire [5:0] _T_1116 = {_T_1111,_T_1100,_T_1071,_T_1042,_T_1007,_T_972}; // @[Cat.scala 29:58] + wire _T_1117 = ^dccm_wdata_hi_any; // @[el2_lib.scala 267:13] + wire _T_1118 = ^_T_1116; // @[el2_lib.scala 267:23] + wire _T_1119 = _T_1117 ^ _T_1118; // @[el2_lib.scala 267:18] + reg _T_1150; // @[el2_lsu_ecc.scala 141:72] + reg _T_1151; // @[el2_lsu_ecc.scala 142:72] + reg _T_1152; // @[el2_lsu_ecc.scala 143:72] + reg _T_1153; // @[el2_lsu_ecc.scala 144:72] + reg [31:0] _T_1154; // @[el2_lsu_ecc.scala 145:72] + reg [31:0] _T_1155; // @[el2_lsu_ecc.scala 146:72] + reg [31:0] _T_1164; // @[el2_lib.scala 514:16] + reg [31:0] _T_1165; // @[el2_lib.scala 514:16] + rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), .io_en(rvclkhdr_io_en), .io_scan_mode(rvclkhdr_io_scan_mode) ); - rvclkhdr rvclkhdr_1 ( // @[beh_lib.scala 352:21] + rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 508:23] .io_l1clk(rvclkhdr_1_io_l1clk), .io_clk(rvclkhdr_1_io_clk), .io_en(rvclkhdr_1_io_en), .io_scan_mode(rvclkhdr_1_io_scan_mode) ); - assign io_sec_data_hi_r = _T_1178; // @[el2_lsu_ecc.scala 114:24 el2_lsu_ecc.scala 145:62] - assign io_sec_data_lo_r = _T_1179; // @[el2_lsu_ecc.scala 117:27 el2_lsu_ecc.scala 146:62] + assign io_sec_data_hi_r = _T_1154; // @[el2_lsu_ecc.scala 114:22 el2_lsu_ecc.scala 145:62] + assign io_sec_data_lo_r = _T_1155; // @[el2_lsu_ecc.scala 117:25 el2_lsu_ecc.scala 146:62] assign io_sec_data_hi_m = {_T_364,_T_362}; // @[el2_lsu_ecc.scala 90:32 el2_lsu_ecc.scala 134:27] assign io_sec_data_lo_m = {_T_742,_T_740}; // @[el2_lsu_ecc.scala 91:32 el2_lsu_ecc.scala 136:27] - assign io_sec_data_hi_r_ff = _T_1188; // @[el2_lsu_ecc.scala 157:23] - assign io_sec_data_lo_r_ff = _T_1189; // @[el2_lsu_ecc.scala 158:23] - assign io_dma_dccm_wdata_ecc_hi = {_T_1143,_T_1140}; // @[el2_lsu_ecc.scala 154:30] - assign io_dma_dccm_wdata_ecc_lo = {_T_949,_T_946}; // @[el2_lsu_ecc.scala 155:30] - assign io_stbuf_ecc_any = {_T_949,_T_946}; // @[el2_lsu_ecc.scala 153:30] - assign io_sec_data_ecc_hi_r_ff = {_T_1143,_T_1140}; // @[el2_lsu_ecc.scala 151:30] - assign io_sec_data_ecc_lo_r_ff = {_T_949,_T_946}; // @[el2_lsu_ecc.scala 152:30] - assign io_single_ecc_error_hi_r = _T_1177; // @[el2_lsu_ecc.scala 115:33 el2_lsu_ecc.scala 144:62] - assign io_single_ecc_error_lo_r = _T_1176; // @[el2_lsu_ecc.scala 118:33 el2_lsu_ecc.scala 143:62] - assign io_lsu_single_ecc_error_r = _T_1174; // @[el2_lsu_ecc.scala 120:33 el2_lsu_ecc.scala 141:62] - assign io_lsu_double_ecc_error_r = _T_1175; // @[el2_lsu_ecc.scala 121:33 el2_lsu_ecc.scala 142:62] + assign io_sec_data_hi_r_ff = _T_1164; // @[el2_lsu_ecc.scala 157:23] + assign io_sec_data_lo_r_ff = _T_1165; // @[el2_lsu_ecc.scala 158:23] + assign io_dma_dccm_wdata_ecc_hi = {_T_1119,_T_1116}; // @[el2_lsu_ecc.scala 154:28] + assign io_dma_dccm_wdata_ecc_lo = {_T_937,_T_934}; // @[el2_lsu_ecc.scala 155:28] + assign io_stbuf_ecc_any = {_T_937,_T_934}; // @[el2_lsu_ecc.scala 153:28] + assign io_sec_data_ecc_hi_r_ff = {_T_1119,_T_1116}; // @[el2_lsu_ecc.scala 151:28] + assign io_sec_data_ecc_lo_r_ff = {_T_937,_T_934}; // @[el2_lsu_ecc.scala 152:28] + assign io_single_ecc_error_hi_r = _T_1153; // @[el2_lsu_ecc.scala 115:31 el2_lsu_ecc.scala 144:62] + assign io_single_ecc_error_lo_r = _T_1152; // @[el2_lsu_ecc.scala 118:31 el2_lsu_ecc.scala 143:62] + assign io_lsu_single_ecc_error_r = _T_1150; // @[el2_lsu_ecc.scala 120:31 el2_lsu_ecc.scala 141:62] + assign io_lsu_double_ecc_error_r = _T_1151; // @[el2_lsu_ecc.scala 121:31 el2_lsu_ecc.scala 142:62] assign io_lsu_single_ecc_error_m = single_ecc_error_hi_any | single_ecc_error_lo_any; // @[el2_lsu_ecc.scala 92:30 el2_lsu_ecc.scala 138:33] assign io_lsu_double_ecc_error_m = double_ecc_error_hi_any | double_ecc_error_lo_any; // @[el2_lsu_ecc.scala 93:30 el2_lsu_ecc.scala 139:33] - assign rvclkhdr_io_clk = clock; // @[beh_lib.scala 354:16] - assign rvclkhdr_io_en = io_ld_single_ecc_error_r; // @[beh_lib.scala 355:15] - assign rvclkhdr_io_scan_mode = io_scan_mode; // @[beh_lib.scala 356:22] - assign rvclkhdr_1_io_clk = clock; // @[beh_lib.scala 354:16] - assign rvclkhdr_1_io_en = io_ld_single_ecc_error_r; // @[beh_lib.scala 355:15] - assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[beh_lib.scala 356:22] + assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_io_en = io_ld_single_ecc_error_r; // @[el2_lib.scala 511:17] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_1_io_en = io_ld_single_ecc_error_r; // @[el2_lib.scala 511:17] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -408,45 +542,45 @@ initial begin `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; - _T_1174 = _RAND_0[0:0]; + _T_1150 = _RAND_0[0:0]; _RAND_1 = {1{`RANDOM}}; - _T_1175 = _RAND_1[0:0]; + _T_1151 = _RAND_1[0:0]; _RAND_2 = {1{`RANDOM}}; - _T_1176 = _RAND_2[0:0]; + _T_1152 = _RAND_2[0:0]; _RAND_3 = {1{`RANDOM}}; - _T_1177 = _RAND_3[0:0]; + _T_1153 = _RAND_3[0:0]; _RAND_4 = {1{`RANDOM}}; - _T_1178 = _RAND_4[31:0]; + _T_1154 = _RAND_4[31:0]; _RAND_5 = {1{`RANDOM}}; - _T_1179 = _RAND_5[31:0]; + _T_1155 = _RAND_5[31:0]; _RAND_6 = {1{`RANDOM}}; - _T_1188 = _RAND_6[31:0]; + _T_1164 = _RAND_6[31:0]; _RAND_7 = {1{`RANDOM}}; - _T_1189 = _RAND_7[31:0]; + _T_1165 = _RAND_7[31:0]; `endif // RANDOMIZE_REG_INIT if (reset) begin - _T_1174 = 1'h0; + _T_1150 = 1'h0; end if (reset) begin - _T_1175 = 1'h0; + _T_1151 = 1'h0; end if (reset) begin - _T_1176 = 1'h0; + _T_1152 = 1'h0; end if (reset) begin - _T_1177 = 1'h0; + _T_1153 = 1'h0; end if (reset) begin - _T_1178 = 32'h0; + _T_1154 = 32'h0; end if (reset) begin - _T_1179 = 32'h0; + _T_1155 = 32'h0; end if (reset) begin - _T_1188 = 32'h0; + _T_1164 = 32'h0; end if (reset) begin - _T_1189 = 32'h0; + _T_1165 = 32'h0; end `endif // RANDOMIZE end // initial @@ -456,58 +590,58 @@ end // initial `endif // SYNTHESIS always @(posedge io_lsu_c2_r_clk or posedge reset) begin if (reset) begin - _T_1174 <= 1'h0; + _T_1150 <= 1'h0; end else begin - _T_1174 <= io_lsu_single_ecc_error_m; + _T_1150 <= io_lsu_single_ecc_error_m; end end always @(posedge io_lsu_c2_r_clk or posedge reset) begin if (reset) begin - _T_1175 <= 1'h0; + _T_1151 <= 1'h0; end else begin - _T_1175 <= io_lsu_double_ecc_error_m; + _T_1151 <= io_lsu_double_ecc_error_m; end end always @(posedge io_lsu_c2_r_clk or posedge reset) begin if (reset) begin - _T_1176 <= 1'h0; + _T_1152 <= 1'h0; end else begin - _T_1176 <= _T_588 & _T_586[6]; + _T_1152 <= _T_588 & _T_586[6]; end end always @(posedge io_lsu_c2_r_clk or posedge reset) begin if (reset) begin - _T_1177 <= 1'h0; + _T_1153 <= 1'h0; end else begin - _T_1177 <= _T_210 & _T_208[6]; + _T_1153 <= _T_210 & _T_208[6]; end end always @(posedge io_lsu_c2_r_clk or posedge reset) begin if (reset) begin - _T_1178 <= 32'h0; + _T_1154 <= 32'h0; end else begin - _T_1178 <= io_sec_data_hi_m; + _T_1154 <= io_sec_data_hi_m; end end always @(posedge io_lsu_c2_r_clk or posedge reset) begin if (reset) begin - _T_1179 <= 32'h0; + _T_1155 <= 32'h0; end else begin - _T_1179 <= io_sec_data_lo_m; + _T_1155 <= io_sec_data_lo_m; end end always @(posedge rvclkhdr_io_l1clk or posedge reset) begin if (reset) begin - _T_1188 <= 32'h0; + _T_1164 <= 32'h0; end else begin - _T_1188 <= io_sec_data_hi_r; + _T_1164 <= io_sec_data_hi_r; end end always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin if (reset) begin - _T_1189 <= 32'h0; + _T_1165 <= 32'h0; end else begin - _T_1189 <= io_sec_data_lo_r; + _T_1165 <= io_sec_data_lo_r; end end endmodule diff --git a/el2_lsu_lsc_ctl.anno.json b/el2_lsu_lsc_ctl.anno.json index 2e83403b..ca75eee1 100644 --- a/el2_lsu_lsc_ctl.anno.json +++ b/el2_lsu_lsc_ctl.anno.json @@ -1,59 +1,109 @@ [ { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_by", + "sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_bits_by", "sources":[ - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_by", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_bits_by", "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d", "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_sz" ] }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_single_ecc_error_incr", + "sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_end_addr_d", "sources":[ - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_valid", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_single_ecc_error_r", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_commit_r", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_dma", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_double_ecc_error_r", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_flush_r", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_store", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_load" + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_result_m", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_bits_load_ldst_bypass_d", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_exu_lsu_rs1_d", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_addr", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_bits_load_ldst_bypass_d", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_bits_word", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_bus_read_data_m", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_ld_data_m", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_offset_d", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_bits_half", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_addr_external_m", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_bits_by", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_bits_unsign", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_bits_dword", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_bits_half", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_bits_word", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_bits_dword", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_bits_half", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_bits_word", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_sz" ] }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_word", + "sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_bits_load_ldst_bypass_d", "sources":[ - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_word", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_bits_load_ldst_bypass_d", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_bits_fast_int", + "sources":[ + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_bits_fast_int", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_bits_half", + "sources":[ + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_bits_half", "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d", "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_sz" ] }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_store", + "sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_addr_d", "sources":[ - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_store", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_result_m", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_bits_load_ldst_bypass_d", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_exu_lsu_rs1_d", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_addr", "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_write" + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_offset_d", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_bits_load_ldst_bypass_d", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_bits_word", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_bus_read_data_m", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_ld_data_m", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_bits_half", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_addr_external_m", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_bits_by", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_bits_unsign" ] }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_store_data_bypass_d", + "sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_bits_word", "sources":[ - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_store_data_bypass_d", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d" + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_bits_word", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_sz" ] }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_unsign", + "sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_store_data_m", "sources":[ - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_unsign", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d" + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_result_m", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_picm_mask_data_m", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_bits_store_data_bypass_m", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_addr_in_pic_m", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_bits_word", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_bus_read_data_m", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_ld_data_m", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_bits_half", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_addr_external_m", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_bits_by", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_bits_unsign" ] }, { @@ -65,223 +115,173 @@ }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_valid", + "sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_bits_load", "sources":[ - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_dccm_req", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_valid", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_flush_m_up", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_fast_int" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_store_data_m", - "sources":[ - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_result_m", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_picm_mask_data_m", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_store_data_bypass_m", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_addr_in_pic_m", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_word", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_bus_read_data_m", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_ld_data_m", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_half", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_addr_external_m", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_by", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_unsign" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_dword", - "sources":[ - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_dword", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_sz" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_addr_in_pic_d", - "sources":[ - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_result_m", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_load_ldst_bypass_d", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_exu_lsu_rs1_d", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_addr", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_load_ldst_bypass_d", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_offset_d", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_word", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_bus_read_data_m", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_ld_data_m", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_half", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_addr_external_m", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_by", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_unsign", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_dword", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_half", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_word", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_dword", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_half", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_word", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_sz" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_addr_d", - "sources":[ - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_result_m", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_load_ldst_bypass_d", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_exu_lsu_rs1_d", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_addr", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_offset_d", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_load_ldst_bypass_d", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_word", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_bus_read_data_m", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_ld_data_m", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_half", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_addr_external_m", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_by", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_unsign" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_result_m", - "sources":[ - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_word", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_bus_read_data_m", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_ld_data_m", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_half", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_addr_external_m", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_by", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_unsign" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_result_corr_r", - "sources":[ - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_word", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_ld_data_corr_r", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_half", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_by", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_unsign" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_half", - "sources":[ - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_half", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_sz" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_end_addr_d", - "sources":[ - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_result_m", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_load_ldst_bypass_d", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_exu_lsu_rs1_d", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_addr", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_load_ldst_bypass_d", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_word", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_bus_read_data_m", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_ld_data_m", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_offset_d", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_half", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_addr_external_m", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_by", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_unsign", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_dword", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_half", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_word", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_dword", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_half", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_word", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_sz" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_load", - "sources":[ - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_load", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_bits_load", "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d", "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_write" ] }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_load_ldst_bypass_d", + "sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_bits_store_data_bypass_d", "sources":[ - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_load_ldst_bypass_d", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_bits_store_data_bypass_d", "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d" ] }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_store_data_bypass_m", + "sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_bits_dma", "sources":[ - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_store_data_bypass_m", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_bits_dma", "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d" ] }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_dma", - "sources":[ - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_dma", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_fast_int", - "sources":[ - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_fast_int", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_commit_r", - "sources":[ - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_dma", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_valid", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_flush_r", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_store", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_load" - ] - }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_addr_in_dccm_d", "sources":[ "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_result_m", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_load_ldst_bypass_d", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_bits_load_ldst_bypass_d", "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_exu_lsu_rs1_d", "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_addr", "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_load_ldst_bypass_d", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_bits_load_ldst_bypass_d", "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_offset_d", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_word", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_bits_word", "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_bus_read_data_m", "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_ld_data_m", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_half", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_bits_half", "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_addr_external_m", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_by", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_unsign", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_dword", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_half", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_word", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_dword", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_half", - "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_word", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_bits_by", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_bits_unsign", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_bits_dword", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_bits_half", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_bits_word", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_bits_dword", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_bits_half", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_bits_word", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_sz" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_bits_store", + "sources":[ + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_bits_store", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_write" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_commit_r", + "sources":[ + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_bits_dma", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_valid", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_flush_r", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_bits_store", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_bits_load" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_bits_unsign", + "sources":[ + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_bits_unsign", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_addr_in_pic_d", + "sources":[ + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_result_m", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_bits_load_ldst_bypass_d", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_exu_lsu_rs1_d", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_addr", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_bits_load_ldst_bypass_d", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_offset_d", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_bits_word", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_bus_read_data_m", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_ld_data_m", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_bits_half", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_addr_external_m", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_bits_by", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_bits_unsign", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_bits_dword", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_bits_half", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_bits_word", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_bits_dword", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_bits_half", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_bits_word", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_sz" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_single_ecc_error_incr", + "sources":[ + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_valid", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_single_ecc_error_r", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_commit_r", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_bits_dma", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_double_ecc_error_r", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_flush_r", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_bits_store", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_bits_load" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_valid", + "sources":[ + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_dccm_req", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_valid", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_flush_m_up", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_bits_fast_int" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_result_m", + "sources":[ + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_bits_word", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_bus_read_data_m", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_ld_data_m", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_bits_half", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_addr_external_m", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_bits_by", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_bits_unsign" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_bits_store_data_bypass_m", + "sources":[ + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_bits_store_data_bypass_m", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_result_corr_r", + "sources":[ + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_bits_word", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_ld_data_corr_r", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_bits_half", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_bits_by", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_bits_unsign" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_bits_dword", + "sources":[ + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_bits_dword", + "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d", "~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_sz" ] }, diff --git a/el2_lsu_lsc_ctl.fir b/el2_lsu_lsc_ctl.fir index e0243006..cb7ebac9 100644 --- a/el2_lsu_lsc_ctl.fir +++ b/el2_lsu_lsc_ctl.fir @@ -3,7 +3,7 @@ circuit el2_lsu_lsc_ctl : module el2_lsu_addrcheck : input clock : Clock input reset : AsyncReset - output io : {flip lsu_c2_m_clk : Clock, flip start_addr_d : UInt<32>, flip end_addr_d : UInt<32>, flip lsu_pkt_d : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip dec_tlu_mrac_ff : UInt<32>, flip rs1_region_d : UInt<4>, flip rs1_d : UInt<32>, is_sideeffects_m : UInt<1>, addr_in_dccm_d : UInt<1>, addr_in_pic_d : UInt<1>, addr_external_d : UInt<1>, access_fault_d : UInt<1>, misaligned_fault_d : UInt<1>, exc_mscause_d : UInt<4>, fir_dccm_access_error_d : UInt<1>, fir_nondccm_access_error_d : UInt<1>, flip scan_mode : UInt<1>} + output io : {flip lsu_c2_m_clk : Clock, flip start_addr_d : UInt<32>, flip end_addr_d : UInt<32>, flip lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip dec_tlu_mrac_ff : UInt<32>, flip rs1_region_d : UInt<4>, flip rs1_d : UInt<32>, is_sideeffects_m : UInt<1>, addr_in_dccm_d : UInt<1>, addr_in_pic_d : UInt<1>, addr_external_d : UInt<1>, access_fault_d : UInt<1>, misaligned_fault_d : UInt<1>, exc_mscause_d : UInt<4>, fir_dccm_access_error_d : UInt<1>, fir_nondccm_access_error_d : UInt<1>, flip scan_mode : UInt<1>} node _T = bits(io.start_addr_d, 31, 28) @[el2_lib.scala 496:27] node start_addr_in_dccm_region_d = eq(_T, UInt<4>("h0f")) @[el2_lib.scala 496:49] @@ -58,16 +58,16 @@ circuit el2_lsu_lsc_ctl : node _T_29 = eq(_T_28, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 61:62] node _T_30 = and(_T_26, _T_29) @[el2_lsu_addrcheck.scala 61:60] node _T_31 = and(_T_30, io.lsu_pkt_d.valid) @[el2_lsu_addrcheck.scala 61:137] - node _T_32 = or(io.lsu_pkt_d.store, io.lsu_pkt_d.load) @[el2_lsu_addrcheck.scala 61:180] + node _T_32 = or(io.lsu_pkt_d.bits.store, io.lsu_pkt_d.bits.load) @[el2_lsu_addrcheck.scala 61:185] node is_sideeffects_d = and(_T_31, _T_32) @[el2_lsu_addrcheck.scala 61:158] - node _T_33 = bits(io.start_addr_d, 1, 0) @[el2_lsu_addrcheck.scala 62:69] - node _T_34 = eq(_T_33, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 62:75] - node _T_35 = and(io.lsu_pkt_d.word, _T_34) @[el2_lsu_addrcheck.scala 62:51] - node _T_36 = bits(io.start_addr_d, 0, 0) @[el2_lsu_addrcheck.scala 62:124] - node _T_37 = eq(_T_36, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 62:128] - node _T_38 = and(io.lsu_pkt_d.half, _T_37) @[el2_lsu_addrcheck.scala 62:106] - node _T_39 = or(_T_35, _T_38) @[el2_lsu_addrcheck.scala 62:85] - node is_aligned_d = or(_T_39, io.lsu_pkt_d.by) @[el2_lsu_addrcheck.scala 62:138] + node _T_33 = bits(io.start_addr_d, 1, 0) @[el2_lsu_addrcheck.scala 62:74] + node _T_34 = eq(_T_33, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 62:80] + node _T_35 = and(io.lsu_pkt_d.bits.word, _T_34) @[el2_lsu_addrcheck.scala 62:56] + node _T_36 = bits(io.start_addr_d, 0, 0) @[el2_lsu_addrcheck.scala 62:134] + node _T_37 = eq(_T_36, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 62:138] + node _T_38 = and(io.lsu_pkt_d.bits.half, _T_37) @[el2_lsu_addrcheck.scala 62:116] + node _T_39 = or(_T_35, _T_38) @[el2_lsu_addrcheck.scala 62:90] + node is_aligned_d = or(_T_39, io.lsu_pkt_d.bits.by) @[el2_lsu_addrcheck.scala 62:148] node _T_40 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58] node _T_41 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58] node _T_42 = cat(_T_41, _T_40) @[Cat.scala 29:58] @@ -176,7 +176,7 @@ circuit el2_lsu_lsc_ctl : node regpred_access_fault_d = xor(start_addr_dccm_or_pic, base_reg_dccm_or_pic) @[el2_lsu_addrcheck.scala 85:57] node _T_144 = bits(io.start_addr_d, 1, 0) @[el2_lsu_addrcheck.scala 86:70] node _T_145 = neq(_T_144, UInt<2>("h00")) @[el2_lsu_addrcheck.scala 86:76] - node _T_146 = eq(io.lsu_pkt_d.word, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 86:92] + node _T_146 = eq(io.lsu_pkt_d.bits.word, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 86:92] node _T_147 = or(_T_145, _T_146) @[el2_lsu_addrcheck.scala 86:90] node picm_access_fault_d = and(io.addr_in_pic_d, _T_147) @[el2_lsu_addrcheck.scala 86:51] wire unmapped_access_fault_d : UInt<1> @@ -203,7 +203,7 @@ circuit el2_lsu_lsc_ctl : node _T_163 = or(_T_162, picm_access_fault_d) @[el2_lsu_addrcheck.scala 111:70] node _T_164 = or(_T_163, regpred_access_fault_d) @[el2_lsu_addrcheck.scala 111:92] node _T_165 = and(_T_164, io.lsu_pkt_d.valid) @[el2_lsu_addrcheck.scala 111:118] - node _T_166 = eq(io.lsu_pkt_d.dma, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 111:141] + node _T_166 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 111:141] node _T_167 = and(_T_165, _T_166) @[el2_lsu_addrcheck.scala 111:139] io.access_fault_d <= _T_167 @[el2_lsu_addrcheck.scala 111:21] node _T_168 = bits(unmapped_access_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 112:60] @@ -222,7 +222,7 @@ circuit el2_lsu_lsc_ctl : node _T_178 = and(sideeffect_misaligned_fault_d, io.addr_external_d) @[el2_lsu_addrcheck.scala 115:90] node _T_179 = or(regcross_misaligned_fault_d, _T_178) @[el2_lsu_addrcheck.scala 115:57] node _T_180 = and(_T_179, io.lsu_pkt_d.valid) @[el2_lsu_addrcheck.scala 115:113] - node _T_181 = eq(io.lsu_pkt_d.dma, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 115:136] + node _T_181 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 115:136] node _T_182 = and(_T_180, _T_181) @[el2_lsu_addrcheck.scala 115:134] io.misaligned_fault_d <= _T_182 @[el2_lsu_addrcheck.scala 115:25] node _T_183 = bits(sideeffect_misaligned_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 116:111] @@ -239,12 +239,12 @@ circuit el2_lsu_lsc_ctl : node _T_192 = and(end_addr_in_dccm_region_d, _T_191) @[el2_lsu_addrcheck.scala 118:118] node _T_193 = or(_T_190, _T_192) @[el2_lsu_addrcheck.scala 118:88] node _T_194 = and(_T_193, io.lsu_pkt_d.valid) @[el2_lsu_addrcheck.scala 118:142] - node _T_195 = and(_T_194, io.lsu_pkt_d.fast_int) @[el2_lsu_addrcheck.scala 118:163] + node _T_195 = and(_T_194, io.lsu_pkt_d.bits.fast_int) @[el2_lsu_addrcheck.scala 118:163] io.fir_dccm_access_error_d <= _T_195 @[el2_lsu_addrcheck.scala 118:31] node _T_196 = and(start_addr_in_dccm_region_d, end_addr_in_dccm_region_d) @[el2_lsu_addrcheck.scala 119:66] node _T_197 = eq(_T_196, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 119:36] node _T_198 = and(_T_197, io.lsu_pkt_d.valid) @[el2_lsu_addrcheck.scala 119:95] - node _T_199 = and(_T_198, io.lsu_pkt_d.fast_int) @[el2_lsu_addrcheck.scala 119:116] + node _T_199 = and(_T_198, io.lsu_pkt_d.bits.fast_int) @[el2_lsu_addrcheck.scala 119:116] io.fir_nondccm_access_error_d <= _T_199 @[el2_lsu_addrcheck.scala 119:33] reg _T_200 : UInt<1>, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_addrcheck.scala 121:60] _T_200 <= is_sideeffects_d @[el2_lsu_addrcheck.scala 121:60] @@ -253,19 +253,19 @@ circuit el2_lsu_lsc_ctl : module el2_lsu_lsc_ctl : input clock : Clock input reset : AsyncReset - output io : {flip lsu_c1_m_clk : Clock, flip lsu_c1_r_clk : Clock, flip lsu_c2_m_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_store_c1_m_clk : Clock, flip lsu_ld_data_r : UInt<32>, flip lsu_ld_data_corr_r : UInt<32>, flip lsu_single_ecc_error_r : UInt<1>, flip lsu_double_ecc_error_r : UInt<1>, flip lsu_ld_data_m : UInt<32>, flip lsu_single_ecc_error_m : UInt<1>, flip lsu_double_ecc_error_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, flip exu_lsu_rs1_d : UInt<32>, flip exu_lsu_rs2_d : UInt<32>, flip lsu_p : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip dec_lsu_valid_raw_d : UInt<1>, flip dec_lsu_offset_d : UInt<12>, flip picm_mask_data_m : UInt<32>, flip bus_read_data_m : UInt<32>, lsu_result_m : UInt<32>, lsu_result_corr_r : UInt<32>, lsu_addr_d : UInt<32>, lsu_addr_m : UInt<32>, lsu_addr_r : UInt<32>, end_addr_d : UInt<32>, end_addr_m : UInt<32>, end_addr_r : UInt<32>, store_data_m : UInt<32>, flip dec_tlu_mrac_ff : UInt<32>, lsu_exc_m : UInt<1>, is_sideeffects_m : UInt<1>, lsu_commit_r : UInt<1>, lsu_single_ecc_error_incr : UInt<1>, lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<1>, addr : UInt<1>}}, lsu_fir_addr : UInt<31>, lsu_fir_error : UInt<2>, addr_in_dccm_d : UInt<1>, addr_in_dccm_m : UInt<1>, addr_in_dccm_r : UInt<1>, addr_in_pic_d : UInt<1>, addr_in_pic_m : UInt<1>, addr_in_pic_r : UInt<1>, addr_external_m : UInt<1>, flip dma_dccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>, lsu_pkt_d : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, lsu_pkt_m : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, lsu_pkt_r : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip scan_mode : UInt<1>} + output io : {flip lsu_c1_m_clk : Clock, flip lsu_c1_r_clk : Clock, flip lsu_c2_m_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_store_c1_m_clk : Clock, flip lsu_ld_data_r : UInt<32>, flip lsu_ld_data_corr_r : UInt<32>, flip lsu_single_ecc_error_r : UInt<1>, flip lsu_double_ecc_error_r : UInt<1>, flip lsu_ld_data_m : UInt<32>, flip lsu_single_ecc_error_m : UInt<1>, flip lsu_double_ecc_error_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, flip exu_lsu_rs1_d : UInt<32>, flip exu_lsu_rs2_d : UInt<32>, flip lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip dec_lsu_valid_raw_d : UInt<1>, flip dec_lsu_offset_d : UInt<12>, flip picm_mask_data_m : UInt<32>, flip bus_read_data_m : UInt<32>, lsu_result_m : UInt<32>, lsu_result_corr_r : UInt<32>, lsu_addr_d : UInt<32>, lsu_addr_m : UInt<32>, lsu_addr_r : UInt<32>, end_addr_d : UInt<32>, end_addr_m : UInt<32>, end_addr_r : UInt<32>, store_data_m : UInt<32>, flip dec_tlu_mrac_ff : UInt<32>, lsu_exc_m : UInt<1>, is_sideeffects_m : UInt<1>, lsu_commit_r : UInt<1>, lsu_single_ecc_error_incr : UInt<1>, lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, lsu_fir_addr : UInt<31>, lsu_fir_error : UInt<2>, addr_in_dccm_d : UInt<1>, addr_in_dccm_m : UInt<1>, addr_in_dccm_r : UInt<1>, addr_in_pic_d : UInt<1>, addr_in_pic_m : UInt<1>, addr_in_pic_r : UInt<1>, addr_external_m : UInt<1>, flip dma_dccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>, lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip scan_mode : UInt<1>} - wire dma_pkt_d : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>} @[el2_lsu_lsc_ctl.scala 96:29] - wire lsu_pkt_m_in : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>} @[el2_lsu_lsc_ctl.scala 97:29] - wire lsu_pkt_r_in : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>} @[el2_lsu_lsc_ctl.scala 98:29] - wire lsu_error_pkt_m : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<1>, addr : UInt<1>}} @[el2_lsu_lsc_ctl.scala 99:29] + wire dma_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[el2_lsu_lsc_ctl.scala 96:29] + wire lsu_pkt_m_in : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[el2_lsu_lsc_ctl.scala 97:29] + wire lsu_pkt_r_in : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[el2_lsu_lsc_ctl.scala 98:29] + wire lsu_error_pkt_m : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}} @[el2_lsu_lsc_ctl.scala 99:29] node _T = bits(io.dec_lsu_valid_raw_d, 0, 0) @[el2_lsu_lsc_ctl.scala 101:52] node lsu_rs1_d = mux(_T, io.exu_lsu_rs1_d, io.dma_mem_addr) @[el2_lsu_lsc_ctl.scala 101:28] node _T_1 = bits(io.dec_lsu_offset_d, 11, 0) @[el2_lsu_lsc_ctl.scala 102:44] node _T_2 = bits(io.dec_lsu_valid_raw_d, 0, 0) @[Bitwise.scala 72:15] node _T_3 = mux(_T_2, UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12] node lsu_offset_d = and(_T_1, _T_3) @[el2_lsu_lsc_ctl.scala 102:51] - node _T_4 = bits(io.lsu_pkt_d.load_ldst_bypass_d, 0, 0) @[el2_lsu_lsc_ctl.scala 105:61] + node _T_4 = bits(io.lsu_pkt_d.bits.load_ldst_bypass_d, 0, 0) @[el2_lsu_lsc_ctl.scala 105:66] node rs1_d = mux(_T_4, io.lsu_result_m, lsu_rs1_d) @[el2_lsu_lsc_ctl.scala 105:28] node _T_5 = bits(rs1_d, 11, 0) @[el2_lib.scala 232:31] node _T_6 = cat(UInt<1>("h00"), _T_5) @[Cat.scala 29:58] @@ -305,17 +305,17 @@ circuit el2_lsu_lsc_ctl : node _T_40 = or(_T_29, _T_39) @[el2_lib.scala 234:61] node _T_41 = bits(_T_10, 11, 0) @[el2_lib.scala 236:22] node full_addr_d = cat(_T_40, _T_41) @[Cat.scala 29:58] - node _T_42 = bits(io.lsu_pkt_d.half, 0, 0) @[Bitwise.scala 72:15] + node _T_42 = bits(io.lsu_pkt_d.bits.half, 0, 0) @[Bitwise.scala 72:15] node _T_43 = mux(_T_42, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_44 = and(_T_43, UInt<3>("h01")) @[el2_lsu_lsc_ctl.scala 110:53] - node _T_45 = bits(io.lsu_pkt_d.word, 0, 0) @[Bitwise.scala 72:15] + node _T_44 = and(_T_43, UInt<3>("h01")) @[el2_lsu_lsc_ctl.scala 110:58] + node _T_45 = bits(io.lsu_pkt_d.bits.word, 0, 0) @[Bitwise.scala 72:15] node _T_46 = mux(_T_45, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_47 = and(_T_46, UInt<3>("h03")) @[el2_lsu_lsc_ctl.scala 111:35] - node _T_48 = or(_T_44, _T_47) @[el2_lsu_lsc_ctl.scala 110:65] - node _T_49 = bits(io.lsu_pkt_d.dword, 0, 0) @[Bitwise.scala 72:15] + node _T_47 = and(_T_46, UInt<3>("h03")) @[el2_lsu_lsc_ctl.scala 111:40] + node _T_48 = or(_T_44, _T_47) @[el2_lsu_lsc_ctl.scala 110:70] + node _T_49 = bits(io.lsu_pkt_d.bits.dword, 0, 0) @[Bitwise.scala 72:15] node _T_50 = mux(_T_49, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_51 = and(_T_50, UInt<3>("h07")) @[el2_lsu_lsc_ctl.scala 112:35] - node addr_offset_d = or(_T_48, _T_51) @[el2_lsu_lsc_ctl.scala 111:47] + node _T_51 = and(_T_50, UInt<3>("h07")) @[el2_lsu_lsc_ctl.scala 112:40] + node addr_offset_d = or(_T_48, _T_51) @[el2_lsu_lsc_ctl.scala 111:52] node _T_52 = bits(lsu_offset_d, 11, 11) @[el2_lsu_lsc_ctl.scala 114:39] node _T_53 = bits(lsu_offset_d, 11, 0) @[el2_lsu_lsc_ctl.scala 114:52] node _T_54 = cat(_T_52, _T_53) @[Cat.scala 29:58] @@ -339,19 +339,19 @@ circuit el2_lsu_lsc_ctl : addrcheck.io.lsu_c2_m_clk <= io.lsu_c2_m_clk @[el2_lsu_lsc_ctl.scala 121:42] addrcheck.io.start_addr_d <= full_addr_d @[el2_lsu_lsc_ctl.scala 123:42] addrcheck.io.end_addr_d <= full_end_addr_d @[el2_lsu_lsc_ctl.scala 124:42] + addrcheck.io.lsu_pkt_d.bits.store_data_bypass_m <= io.lsu_pkt_d.bits.store_data_bypass_m @[el2_lsu_lsc_ctl.scala 125:42] + addrcheck.io.lsu_pkt_d.bits.load_ldst_bypass_d <= io.lsu_pkt_d.bits.load_ldst_bypass_d @[el2_lsu_lsc_ctl.scala 125:42] + addrcheck.io.lsu_pkt_d.bits.store_data_bypass_d <= io.lsu_pkt_d.bits.store_data_bypass_d @[el2_lsu_lsc_ctl.scala 125:42] + addrcheck.io.lsu_pkt_d.bits.dma <= io.lsu_pkt_d.bits.dma @[el2_lsu_lsc_ctl.scala 125:42] + addrcheck.io.lsu_pkt_d.bits.unsign <= io.lsu_pkt_d.bits.unsign @[el2_lsu_lsc_ctl.scala 125:42] + addrcheck.io.lsu_pkt_d.bits.store <= io.lsu_pkt_d.bits.store @[el2_lsu_lsc_ctl.scala 125:42] + addrcheck.io.lsu_pkt_d.bits.load <= io.lsu_pkt_d.bits.load @[el2_lsu_lsc_ctl.scala 125:42] + addrcheck.io.lsu_pkt_d.bits.dword <= io.lsu_pkt_d.bits.dword @[el2_lsu_lsc_ctl.scala 125:42] + addrcheck.io.lsu_pkt_d.bits.word <= io.lsu_pkt_d.bits.word @[el2_lsu_lsc_ctl.scala 125:42] + addrcheck.io.lsu_pkt_d.bits.half <= io.lsu_pkt_d.bits.half @[el2_lsu_lsc_ctl.scala 125:42] + addrcheck.io.lsu_pkt_d.bits.by <= io.lsu_pkt_d.bits.by @[el2_lsu_lsc_ctl.scala 125:42] + addrcheck.io.lsu_pkt_d.bits.fast_int <= io.lsu_pkt_d.bits.fast_int @[el2_lsu_lsc_ctl.scala 125:42] addrcheck.io.lsu_pkt_d.valid <= io.lsu_pkt_d.valid @[el2_lsu_lsc_ctl.scala 125:42] - addrcheck.io.lsu_pkt_d.store_data_bypass_m <= io.lsu_pkt_d.store_data_bypass_m @[el2_lsu_lsc_ctl.scala 125:42] - addrcheck.io.lsu_pkt_d.load_ldst_bypass_d <= io.lsu_pkt_d.load_ldst_bypass_d @[el2_lsu_lsc_ctl.scala 125:42] - addrcheck.io.lsu_pkt_d.store_data_bypass_d <= io.lsu_pkt_d.store_data_bypass_d @[el2_lsu_lsc_ctl.scala 125:42] - addrcheck.io.lsu_pkt_d.dma <= io.lsu_pkt_d.dma @[el2_lsu_lsc_ctl.scala 125:42] - addrcheck.io.lsu_pkt_d.unsign <= io.lsu_pkt_d.unsign @[el2_lsu_lsc_ctl.scala 125:42] - addrcheck.io.lsu_pkt_d.store <= io.lsu_pkt_d.store @[el2_lsu_lsc_ctl.scala 125:42] - addrcheck.io.lsu_pkt_d.load <= io.lsu_pkt_d.load @[el2_lsu_lsc_ctl.scala 125:42] - addrcheck.io.lsu_pkt_d.dword <= io.lsu_pkt_d.dword @[el2_lsu_lsc_ctl.scala 125:42] - addrcheck.io.lsu_pkt_d.word <= io.lsu_pkt_d.word @[el2_lsu_lsc_ctl.scala 125:42] - addrcheck.io.lsu_pkt_d.half <= io.lsu_pkt_d.half @[el2_lsu_lsc_ctl.scala 125:42] - addrcheck.io.lsu_pkt_d.by <= io.lsu_pkt_d.by @[el2_lsu_lsc_ctl.scala 125:42] - addrcheck.io.lsu_pkt_d.fast_int <= io.lsu_pkt_d.fast_int @[el2_lsu_lsc_ctl.scala 125:42] addrcheck.io.dec_tlu_mrac_ff <= io.dec_tlu_mrac_ff @[el2_lsu_lsc_ctl.scala 126:42] node _T_66 = bits(rs1_d, 31, 28) @[el2_lsu_lsc_ctl.scala 127:50] addrcheck.io.rs1_region_d <= _T_66 @[el2_lsu_lsc_ctl.scala 127:42] @@ -392,26 +392,26 @@ circuit el2_lsu_lsc_ctl : io.lsu_exc_m <= _T_69 @[el2_lsu_lsc_ctl.scala 156:16] node _T_70 = eq(io.lsu_double_ecc_error_r, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 157:64] node _T_71 = and(io.lsu_single_ecc_error_r, _T_70) @[el2_lsu_lsc_ctl.scala 157:62] - node _T_72 = or(io.lsu_commit_r, io.lsu_pkt_r.dma) @[el2_lsu_lsc_ctl.scala 157:111] + node _T_72 = or(io.lsu_commit_r, io.lsu_pkt_r.bits.dma) @[el2_lsu_lsc_ctl.scala 157:111] node _T_73 = and(_T_71, _T_72) @[el2_lsu_lsc_ctl.scala 157:92] - node _T_74 = and(_T_73, io.lsu_pkt_r.valid) @[el2_lsu_lsc_ctl.scala 157:131] + node _T_74 = and(_T_73, io.lsu_pkt_r.valid) @[el2_lsu_lsc_ctl.scala 157:136] io.lsu_single_ecc_error_incr <= _T_74 @[el2_lsu_lsc_ctl.scala 157:32] node _T_75 = or(access_fault_m, misaligned_fault_m) @[el2_lsu_lsc_ctl.scala 179:46] node _T_76 = or(_T_75, io.lsu_double_ecc_error_m) @[el2_lsu_lsc_ctl.scala 179:67] node _T_77 = and(_T_76, io.lsu_pkt_m.valid) @[el2_lsu_lsc_ctl.scala 179:96] - node _T_78 = eq(io.lsu_pkt_m.dma, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 179:119] + node _T_78 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 179:119] node _T_79 = and(_T_77, _T_78) @[el2_lsu_lsc_ctl.scala 179:117] - node _T_80 = eq(io.lsu_pkt_m.fast_int, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 179:139] - node _T_81 = and(_T_79, _T_80) @[el2_lsu_lsc_ctl.scala 179:137] - node _T_82 = eq(io.flush_m_up, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 179:164] - node _T_83 = and(_T_81, _T_82) @[el2_lsu_lsc_ctl.scala 179:162] + node _T_80 = eq(io.lsu_pkt_m.bits.fast_int, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 179:144] + node _T_81 = and(_T_79, _T_80) @[el2_lsu_lsc_ctl.scala 179:142] + node _T_82 = eq(io.flush_m_up, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 179:174] + node _T_83 = and(_T_81, _T_82) @[el2_lsu_lsc_ctl.scala 179:172] lsu_error_pkt_m.valid <= _T_83 @[el2_lsu_lsc_ctl.scala 179:27] node _T_84 = eq(lsu_error_pkt_m.valid, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 180:75] node _T_85 = and(io.lsu_single_ecc_error_m, _T_84) @[el2_lsu_lsc_ctl.scala 180:73] - node _T_86 = eq(io.lsu_pkt_m.dma, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 180:101] + node _T_86 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 180:101] node _T_87 = and(_T_85, _T_86) @[el2_lsu_lsc_ctl.scala 180:99] lsu_error_pkt_m.bits.single_ecc_error <= _T_87 @[el2_lsu_lsc_ctl.scala 180:43] - lsu_error_pkt_m.bits.inst_type <= io.lsu_pkt_m.store @[el2_lsu_lsc_ctl.scala 181:43] + lsu_error_pkt_m.bits.inst_type <= io.lsu_pkt_m.bits.store @[el2_lsu_lsc_ctl.scala 181:43] node _T_88 = not(misaligned_fault_m) @[el2_lsu_lsc_ctl.scala 182:46] lsu_error_pkt_m.bits.exc_type <= _T_88 @[el2_lsu_lsc_ctl.scala 182:43] node _T_89 = eq(misaligned_fault_m, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 183:80] @@ -426,20 +426,20 @@ circuit el2_lsu_lsc_ctl : lsu_error_pkt_m.bits.addr <= _T_96 @[el2_lsu_lsc_ctl.scala 184:43] node _T_97 = bits(fir_nondccm_access_error_m, 0, 0) @[el2_lsu_lsc_ctl.scala 185:72] node _T_98 = bits(fir_dccm_access_error_m, 0, 0) @[el2_lsu_lsc_ctl.scala 185:117] - node _T_99 = and(io.lsu_pkt_m.fast_int, io.lsu_double_ecc_error_m) @[el2_lsu_lsc_ctl.scala 185:161] - node _T_100 = bits(_T_99, 0, 0) @[el2_lsu_lsc_ctl.scala 185:190] + node _T_99 = and(io.lsu_pkt_m.bits.fast_int, io.lsu_double_ecc_error_m) @[el2_lsu_lsc_ctl.scala 185:166] + node _T_100 = bits(_T_99, 0, 0) @[el2_lsu_lsc_ctl.scala 185:195] node _T_101 = mux(_T_100, UInt<2>("h01"), UInt<2>("h00")) @[el2_lsu_lsc_ctl.scala 185:137] node _T_102 = mux(_T_98, UInt<2>("h02"), _T_101) @[el2_lsu_lsc_ctl.scala 185:92] node _T_103 = mux(_T_97, UInt<2>("h03"), _T_102) @[el2_lsu_lsc_ctl.scala 185:44] lsu_fir_error_m <= _T_103 @[el2_lsu_lsc_ctl.scala 185:38] - wire _T_104 : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<1>, addr : UInt<1>}} @[el2_lsu_lsc_ctl.scala 186:104] - _T_104.bits.addr <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 186:104] - _T_104.bits.mscause <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 186:104] + wire _T_104 : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}} @[el2_lsu_lsc_ctl.scala 186:104] + _T_104.bits.addr <= UInt<32>("h00") @[el2_lsu_lsc_ctl.scala 186:104] + _T_104.bits.mscause <= UInt<4>("h00") @[el2_lsu_lsc_ctl.scala 186:104] _T_104.bits.exc_type <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 186:104] _T_104.bits.inst_type <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 186:104] _T_104.bits.single_ecc_error <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 186:104] _T_104.valid <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 186:104] - reg _T_105 : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<1>, addr : UInt<1>}}, io.lsu_c2_r_clk with : (reset => (reset, _T_104)) @[el2_lsu_lsc_ctl.scala 186:75] + reg _T_105 : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, io.lsu_c2_r_clk with : (reset => (reset, _T_104)) @[el2_lsu_lsc_ctl.scala 186:75] _T_105.bits.addr <= lsu_error_pkt_m.bits.addr @[el2_lsu_lsc_ctl.scala 186:75] _T_105.bits.mscause <= lsu_error_pkt_m.bits.mscause @[el2_lsu_lsc_ctl.scala 186:75] _T_105.bits.exc_type <= lsu_error_pkt_m.bits.exc_type @[el2_lsu_lsc_ctl.scala 186:75] @@ -455,28 +455,28 @@ circuit el2_lsu_lsc_ctl : reg _T_106 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 187:75] _T_106 <= lsu_fir_error_m @[el2_lsu_lsc_ctl.scala 187:75] io.lsu_fir_error <= _T_106 @[el2_lsu_lsc_ctl.scala 187:38] - dma_pkt_d.unsign <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 189:22] - dma_pkt_d.fast_int <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 190:22] + dma_pkt_d.bits.unsign <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 189:27] + dma_pkt_d.bits.fast_int <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 190:27] dma_pkt_d.valid <= io.dma_dccm_req @[el2_lsu_lsc_ctl.scala 191:22] - dma_pkt_d.dma <= UInt<1>("h01") @[el2_lsu_lsc_ctl.scala 192:22] - dma_pkt_d.store <= io.dma_mem_write @[el2_lsu_lsc_ctl.scala 193:22] - node _T_107 = not(io.dma_mem_write) @[el2_lsu_lsc_ctl.scala 194:25] - dma_pkt_d.load <= _T_107 @[el2_lsu_lsc_ctl.scala 194:22] - node _T_108 = bits(io.dma_mem_sz, 2, 0) @[el2_lsu_lsc_ctl.scala 195:39] - node _T_109 = eq(_T_108, UInt<3>("h00")) @[el2_lsu_lsc_ctl.scala 195:45] - dma_pkt_d.by <= _T_109 @[el2_lsu_lsc_ctl.scala 195:22] - node _T_110 = bits(io.dma_mem_sz, 2, 0) @[el2_lsu_lsc_ctl.scala 196:39] - node _T_111 = eq(_T_110, UInt<3>("h01")) @[el2_lsu_lsc_ctl.scala 196:45] - dma_pkt_d.half <= _T_111 @[el2_lsu_lsc_ctl.scala 196:22] - node _T_112 = bits(io.dma_mem_sz, 2, 0) @[el2_lsu_lsc_ctl.scala 197:39] - node _T_113 = eq(_T_112, UInt<3>("h02")) @[el2_lsu_lsc_ctl.scala 197:45] - dma_pkt_d.word <= _T_113 @[el2_lsu_lsc_ctl.scala 197:22] - node _T_114 = bits(io.dma_mem_sz, 2, 0) @[el2_lsu_lsc_ctl.scala 198:39] - node _T_115 = eq(_T_114, UInt<3>("h03")) @[el2_lsu_lsc_ctl.scala 198:45] - dma_pkt_d.dword <= _T_115 @[el2_lsu_lsc_ctl.scala 198:22] - dma_pkt_d.store_data_bypass_d <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 199:34] - dma_pkt_d.load_ldst_bypass_d <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 200:34] - dma_pkt_d.store_data_bypass_m <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 201:34] + dma_pkt_d.bits.dma <= UInt<1>("h01") @[el2_lsu_lsc_ctl.scala 192:27] + dma_pkt_d.bits.store <= io.dma_mem_write @[el2_lsu_lsc_ctl.scala 193:27] + node _T_107 = not(io.dma_mem_write) @[el2_lsu_lsc_ctl.scala 194:30] + dma_pkt_d.bits.load <= _T_107 @[el2_lsu_lsc_ctl.scala 194:27] + node _T_108 = bits(io.dma_mem_sz, 2, 0) @[el2_lsu_lsc_ctl.scala 195:44] + node _T_109 = eq(_T_108, UInt<3>("h00")) @[el2_lsu_lsc_ctl.scala 195:50] + dma_pkt_d.bits.by <= _T_109 @[el2_lsu_lsc_ctl.scala 195:27] + node _T_110 = bits(io.dma_mem_sz, 2, 0) @[el2_lsu_lsc_ctl.scala 196:44] + node _T_111 = eq(_T_110, UInt<3>("h01")) @[el2_lsu_lsc_ctl.scala 196:50] + dma_pkt_d.bits.half <= _T_111 @[el2_lsu_lsc_ctl.scala 196:27] + node _T_112 = bits(io.dma_mem_sz, 2, 0) @[el2_lsu_lsc_ctl.scala 197:44] + node _T_113 = eq(_T_112, UInt<3>("h02")) @[el2_lsu_lsc_ctl.scala 197:50] + dma_pkt_d.bits.word <= _T_113 @[el2_lsu_lsc_ctl.scala 197:27] + node _T_114 = bits(io.dma_mem_sz, 2, 0) @[el2_lsu_lsc_ctl.scala 198:44] + node _T_115 = eq(_T_114, UInt<3>("h03")) @[el2_lsu_lsc_ctl.scala 198:50] + dma_pkt_d.bits.dword <= _T_115 @[el2_lsu_lsc_ctl.scala 198:27] + dma_pkt_d.bits.store_data_bypass_d <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 199:39] + dma_pkt_d.bits.load_ldst_bypass_d <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 200:39] + dma_pkt_d.bits.store_data_bypass_m <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 201:39] wire lsu_ld_datafn_r : UInt<32> lsu_ld_datafn_r <= UInt<32>("h00") wire lsu_ld_datafn_corr_r : UInt<32> @@ -485,143 +485,143 @@ circuit el2_lsu_lsc_ctl : lsu_ld_datafn_m <= UInt<32>("h00") node _T_116 = bits(io.dec_lsu_valid_raw_d, 0, 0) @[el2_lsu_lsc_ctl.scala 207:50] node _T_117 = mux(_T_116, io.lsu_p, dma_pkt_d) @[el2_lsu_lsc_ctl.scala 207:26] + io.lsu_pkt_d.bits.store_data_bypass_m <= _T_117.bits.store_data_bypass_m @[el2_lsu_lsc_ctl.scala 207:20] + io.lsu_pkt_d.bits.load_ldst_bypass_d <= _T_117.bits.load_ldst_bypass_d @[el2_lsu_lsc_ctl.scala 207:20] + io.lsu_pkt_d.bits.store_data_bypass_d <= _T_117.bits.store_data_bypass_d @[el2_lsu_lsc_ctl.scala 207:20] + io.lsu_pkt_d.bits.dma <= _T_117.bits.dma @[el2_lsu_lsc_ctl.scala 207:20] + io.lsu_pkt_d.bits.unsign <= _T_117.bits.unsign @[el2_lsu_lsc_ctl.scala 207:20] + io.lsu_pkt_d.bits.store <= _T_117.bits.store @[el2_lsu_lsc_ctl.scala 207:20] + io.lsu_pkt_d.bits.load <= _T_117.bits.load @[el2_lsu_lsc_ctl.scala 207:20] + io.lsu_pkt_d.bits.dword <= _T_117.bits.dword @[el2_lsu_lsc_ctl.scala 207:20] + io.lsu_pkt_d.bits.word <= _T_117.bits.word @[el2_lsu_lsc_ctl.scala 207:20] + io.lsu_pkt_d.bits.half <= _T_117.bits.half @[el2_lsu_lsc_ctl.scala 207:20] + io.lsu_pkt_d.bits.by <= _T_117.bits.by @[el2_lsu_lsc_ctl.scala 207:20] + io.lsu_pkt_d.bits.fast_int <= _T_117.bits.fast_int @[el2_lsu_lsc_ctl.scala 207:20] io.lsu_pkt_d.valid <= _T_117.valid @[el2_lsu_lsc_ctl.scala 207:20] - io.lsu_pkt_d.store_data_bypass_m <= _T_117.store_data_bypass_m @[el2_lsu_lsc_ctl.scala 207:20] - io.lsu_pkt_d.load_ldst_bypass_d <= _T_117.load_ldst_bypass_d @[el2_lsu_lsc_ctl.scala 207:20] - io.lsu_pkt_d.store_data_bypass_d <= _T_117.store_data_bypass_d @[el2_lsu_lsc_ctl.scala 207:20] - io.lsu_pkt_d.dma <= _T_117.dma @[el2_lsu_lsc_ctl.scala 207:20] - io.lsu_pkt_d.unsign <= _T_117.unsign @[el2_lsu_lsc_ctl.scala 207:20] - io.lsu_pkt_d.store <= _T_117.store @[el2_lsu_lsc_ctl.scala 207:20] - io.lsu_pkt_d.load <= _T_117.load @[el2_lsu_lsc_ctl.scala 207:20] - io.lsu_pkt_d.dword <= _T_117.dword @[el2_lsu_lsc_ctl.scala 207:20] - io.lsu_pkt_d.word <= _T_117.word @[el2_lsu_lsc_ctl.scala 207:20] - io.lsu_pkt_d.half <= _T_117.half @[el2_lsu_lsc_ctl.scala 207:20] - io.lsu_pkt_d.by <= _T_117.by @[el2_lsu_lsc_ctl.scala 207:20] - io.lsu_pkt_d.fast_int <= _T_117.fast_int @[el2_lsu_lsc_ctl.scala 207:20] + lsu_pkt_m_in.bits.store_data_bypass_m <= io.lsu_pkt_d.bits.store_data_bypass_m @[el2_lsu_lsc_ctl.scala 208:20] + lsu_pkt_m_in.bits.load_ldst_bypass_d <= io.lsu_pkt_d.bits.load_ldst_bypass_d @[el2_lsu_lsc_ctl.scala 208:20] + lsu_pkt_m_in.bits.store_data_bypass_d <= io.lsu_pkt_d.bits.store_data_bypass_d @[el2_lsu_lsc_ctl.scala 208:20] + lsu_pkt_m_in.bits.dma <= io.lsu_pkt_d.bits.dma @[el2_lsu_lsc_ctl.scala 208:20] + lsu_pkt_m_in.bits.unsign <= io.lsu_pkt_d.bits.unsign @[el2_lsu_lsc_ctl.scala 208:20] + lsu_pkt_m_in.bits.store <= io.lsu_pkt_d.bits.store @[el2_lsu_lsc_ctl.scala 208:20] + lsu_pkt_m_in.bits.load <= io.lsu_pkt_d.bits.load @[el2_lsu_lsc_ctl.scala 208:20] + lsu_pkt_m_in.bits.dword <= io.lsu_pkt_d.bits.dword @[el2_lsu_lsc_ctl.scala 208:20] + lsu_pkt_m_in.bits.word <= io.lsu_pkt_d.bits.word @[el2_lsu_lsc_ctl.scala 208:20] + lsu_pkt_m_in.bits.half <= io.lsu_pkt_d.bits.half @[el2_lsu_lsc_ctl.scala 208:20] + lsu_pkt_m_in.bits.by <= io.lsu_pkt_d.bits.by @[el2_lsu_lsc_ctl.scala 208:20] + lsu_pkt_m_in.bits.fast_int <= io.lsu_pkt_d.bits.fast_int @[el2_lsu_lsc_ctl.scala 208:20] lsu_pkt_m_in.valid <= io.lsu_pkt_d.valid @[el2_lsu_lsc_ctl.scala 208:20] - lsu_pkt_m_in.store_data_bypass_m <= io.lsu_pkt_d.store_data_bypass_m @[el2_lsu_lsc_ctl.scala 208:20] - lsu_pkt_m_in.load_ldst_bypass_d <= io.lsu_pkt_d.load_ldst_bypass_d @[el2_lsu_lsc_ctl.scala 208:20] - lsu_pkt_m_in.store_data_bypass_d <= io.lsu_pkt_d.store_data_bypass_d @[el2_lsu_lsc_ctl.scala 208:20] - lsu_pkt_m_in.dma <= io.lsu_pkt_d.dma @[el2_lsu_lsc_ctl.scala 208:20] - lsu_pkt_m_in.unsign <= io.lsu_pkt_d.unsign @[el2_lsu_lsc_ctl.scala 208:20] - lsu_pkt_m_in.store <= io.lsu_pkt_d.store @[el2_lsu_lsc_ctl.scala 208:20] - lsu_pkt_m_in.load <= io.lsu_pkt_d.load @[el2_lsu_lsc_ctl.scala 208:20] - lsu_pkt_m_in.dword <= io.lsu_pkt_d.dword @[el2_lsu_lsc_ctl.scala 208:20] - lsu_pkt_m_in.word <= io.lsu_pkt_d.word @[el2_lsu_lsc_ctl.scala 208:20] - lsu_pkt_m_in.half <= io.lsu_pkt_d.half @[el2_lsu_lsc_ctl.scala 208:20] - lsu_pkt_m_in.by <= io.lsu_pkt_d.by @[el2_lsu_lsc_ctl.scala 208:20] - lsu_pkt_m_in.fast_int <= io.lsu_pkt_d.fast_int @[el2_lsu_lsc_ctl.scala 208:20] + lsu_pkt_r_in.bits.store_data_bypass_m <= io.lsu_pkt_m.bits.store_data_bypass_m @[el2_lsu_lsc_ctl.scala 209:20] + lsu_pkt_r_in.bits.load_ldst_bypass_d <= io.lsu_pkt_m.bits.load_ldst_bypass_d @[el2_lsu_lsc_ctl.scala 209:20] + lsu_pkt_r_in.bits.store_data_bypass_d <= io.lsu_pkt_m.bits.store_data_bypass_d @[el2_lsu_lsc_ctl.scala 209:20] + lsu_pkt_r_in.bits.dma <= io.lsu_pkt_m.bits.dma @[el2_lsu_lsc_ctl.scala 209:20] + lsu_pkt_r_in.bits.unsign <= io.lsu_pkt_m.bits.unsign @[el2_lsu_lsc_ctl.scala 209:20] + lsu_pkt_r_in.bits.store <= io.lsu_pkt_m.bits.store @[el2_lsu_lsc_ctl.scala 209:20] + lsu_pkt_r_in.bits.load <= io.lsu_pkt_m.bits.load @[el2_lsu_lsc_ctl.scala 209:20] + lsu_pkt_r_in.bits.dword <= io.lsu_pkt_m.bits.dword @[el2_lsu_lsc_ctl.scala 209:20] + lsu_pkt_r_in.bits.word <= io.lsu_pkt_m.bits.word @[el2_lsu_lsc_ctl.scala 209:20] + lsu_pkt_r_in.bits.half <= io.lsu_pkt_m.bits.half @[el2_lsu_lsc_ctl.scala 209:20] + lsu_pkt_r_in.bits.by <= io.lsu_pkt_m.bits.by @[el2_lsu_lsc_ctl.scala 209:20] + lsu_pkt_r_in.bits.fast_int <= io.lsu_pkt_m.bits.fast_int @[el2_lsu_lsc_ctl.scala 209:20] lsu_pkt_r_in.valid <= io.lsu_pkt_m.valid @[el2_lsu_lsc_ctl.scala 209:20] - lsu_pkt_r_in.store_data_bypass_m <= io.lsu_pkt_m.store_data_bypass_m @[el2_lsu_lsc_ctl.scala 209:20] - lsu_pkt_r_in.load_ldst_bypass_d <= io.lsu_pkt_m.load_ldst_bypass_d @[el2_lsu_lsc_ctl.scala 209:20] - lsu_pkt_r_in.store_data_bypass_d <= io.lsu_pkt_m.store_data_bypass_d @[el2_lsu_lsc_ctl.scala 209:20] - lsu_pkt_r_in.dma <= io.lsu_pkt_m.dma @[el2_lsu_lsc_ctl.scala 209:20] - lsu_pkt_r_in.unsign <= io.lsu_pkt_m.unsign @[el2_lsu_lsc_ctl.scala 209:20] - lsu_pkt_r_in.store <= io.lsu_pkt_m.store @[el2_lsu_lsc_ctl.scala 209:20] - lsu_pkt_r_in.load <= io.lsu_pkt_m.load @[el2_lsu_lsc_ctl.scala 209:20] - lsu_pkt_r_in.dword <= io.lsu_pkt_m.dword @[el2_lsu_lsc_ctl.scala 209:20] - lsu_pkt_r_in.word <= io.lsu_pkt_m.word @[el2_lsu_lsc_ctl.scala 209:20] - lsu_pkt_r_in.half <= io.lsu_pkt_m.half @[el2_lsu_lsc_ctl.scala 209:20] - lsu_pkt_r_in.by <= io.lsu_pkt_m.by @[el2_lsu_lsc_ctl.scala 209:20] - lsu_pkt_r_in.fast_int <= io.lsu_pkt_m.fast_int @[el2_lsu_lsc_ctl.scala 209:20] - node _T_118 = eq(io.lsu_p.fast_int, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 211:64] + node _T_118 = eq(io.lsu_p.bits.fast_int, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 211:64] node _T_119 = and(io.flush_m_up, _T_118) @[el2_lsu_lsc_ctl.scala 211:61] node _T_120 = eq(_T_119, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 211:45] node _T_121 = and(io.lsu_p.valid, _T_120) @[el2_lsu_lsc_ctl.scala 211:43] - node _T_122 = or(_T_121, io.dma_dccm_req) @[el2_lsu_lsc_ctl.scala 211:85] + node _T_122 = or(_T_121, io.dma_dccm_req) @[el2_lsu_lsc_ctl.scala 211:90] io.lsu_pkt_d.valid <= _T_122 @[el2_lsu_lsc_ctl.scala 211:24] - node _T_123 = eq(io.lsu_pkt_d.dma, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 212:68] + node _T_123 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 212:68] node _T_124 = and(io.flush_m_up, _T_123) @[el2_lsu_lsc_ctl.scala 212:65] node _T_125 = eq(_T_124, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 212:49] node _T_126 = and(io.lsu_pkt_d.valid, _T_125) @[el2_lsu_lsc_ctl.scala 212:47] lsu_pkt_m_in.valid <= _T_126 @[el2_lsu_lsc_ctl.scala 212:24] - node _T_127 = eq(io.lsu_pkt_m.dma, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 213:68] + node _T_127 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 213:68] node _T_128 = and(io.flush_m_up, _T_127) @[el2_lsu_lsc_ctl.scala 213:65] node _T_129 = eq(_T_128, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 213:49] node _T_130 = and(io.lsu_pkt_m.valid, _T_129) @[el2_lsu_lsc_ctl.scala 213:47] lsu_pkt_r_in.valid <= _T_130 @[el2_lsu_lsc_ctl.scala 213:24] - wire _T_131 : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>} @[el2_lsu_lsc_ctl.scala 215:91] + wire _T_131 : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[el2_lsu_lsc_ctl.scala 215:91] + _T_131.bits.store_data_bypass_m <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91] + _T_131.bits.load_ldst_bypass_d <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91] + _T_131.bits.store_data_bypass_d <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91] + _T_131.bits.dma <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91] + _T_131.bits.unsign <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91] + _T_131.bits.store <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91] + _T_131.bits.load <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91] + _T_131.bits.dword <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91] + _T_131.bits.word <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91] + _T_131.bits.half <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91] + _T_131.bits.by <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91] + _T_131.bits.fast_int <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91] _T_131.valid <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91] - _T_131.store_data_bypass_m <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91] - _T_131.load_ldst_bypass_d <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91] - _T_131.store_data_bypass_d <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91] - _T_131.dma <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91] - _T_131.unsign <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91] - _T_131.store <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91] - _T_131.load <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91] - _T_131.dword <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91] - _T_131.word <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91] - _T_131.half <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91] - _T_131.by <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91] - _T_131.fast_int <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91] - reg _T_132 : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, io.lsu_c1_m_clk with : (reset => (reset, _T_131)) @[el2_lsu_lsc_ctl.scala 215:65] + reg _T_132 : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, io.lsu_c1_m_clk with : (reset => (reset, _T_131)) @[el2_lsu_lsc_ctl.scala 215:65] + _T_132.bits.store_data_bypass_m <= lsu_pkt_m_in.bits.store_data_bypass_m @[el2_lsu_lsc_ctl.scala 215:65] + _T_132.bits.load_ldst_bypass_d <= lsu_pkt_m_in.bits.load_ldst_bypass_d @[el2_lsu_lsc_ctl.scala 215:65] + _T_132.bits.store_data_bypass_d <= lsu_pkt_m_in.bits.store_data_bypass_d @[el2_lsu_lsc_ctl.scala 215:65] + _T_132.bits.dma <= lsu_pkt_m_in.bits.dma @[el2_lsu_lsc_ctl.scala 215:65] + _T_132.bits.unsign <= lsu_pkt_m_in.bits.unsign @[el2_lsu_lsc_ctl.scala 215:65] + _T_132.bits.store <= lsu_pkt_m_in.bits.store @[el2_lsu_lsc_ctl.scala 215:65] + _T_132.bits.load <= lsu_pkt_m_in.bits.load @[el2_lsu_lsc_ctl.scala 215:65] + _T_132.bits.dword <= lsu_pkt_m_in.bits.dword @[el2_lsu_lsc_ctl.scala 215:65] + _T_132.bits.word <= lsu_pkt_m_in.bits.word @[el2_lsu_lsc_ctl.scala 215:65] + _T_132.bits.half <= lsu_pkt_m_in.bits.half @[el2_lsu_lsc_ctl.scala 215:65] + _T_132.bits.by <= lsu_pkt_m_in.bits.by @[el2_lsu_lsc_ctl.scala 215:65] + _T_132.bits.fast_int <= lsu_pkt_m_in.bits.fast_int @[el2_lsu_lsc_ctl.scala 215:65] _T_132.valid <= lsu_pkt_m_in.valid @[el2_lsu_lsc_ctl.scala 215:65] - _T_132.store_data_bypass_m <= lsu_pkt_m_in.store_data_bypass_m @[el2_lsu_lsc_ctl.scala 215:65] - _T_132.load_ldst_bypass_d <= lsu_pkt_m_in.load_ldst_bypass_d @[el2_lsu_lsc_ctl.scala 215:65] - _T_132.store_data_bypass_d <= lsu_pkt_m_in.store_data_bypass_d @[el2_lsu_lsc_ctl.scala 215:65] - _T_132.dma <= lsu_pkt_m_in.dma @[el2_lsu_lsc_ctl.scala 215:65] - _T_132.unsign <= lsu_pkt_m_in.unsign @[el2_lsu_lsc_ctl.scala 215:65] - _T_132.store <= lsu_pkt_m_in.store @[el2_lsu_lsc_ctl.scala 215:65] - _T_132.load <= lsu_pkt_m_in.load @[el2_lsu_lsc_ctl.scala 215:65] - _T_132.dword <= lsu_pkt_m_in.dword @[el2_lsu_lsc_ctl.scala 215:65] - _T_132.word <= lsu_pkt_m_in.word @[el2_lsu_lsc_ctl.scala 215:65] - _T_132.half <= lsu_pkt_m_in.half @[el2_lsu_lsc_ctl.scala 215:65] - _T_132.by <= lsu_pkt_m_in.by @[el2_lsu_lsc_ctl.scala 215:65] - _T_132.fast_int <= lsu_pkt_m_in.fast_int @[el2_lsu_lsc_ctl.scala 215:65] + io.lsu_pkt_m.bits.store_data_bypass_m <= _T_132.bits.store_data_bypass_m @[el2_lsu_lsc_ctl.scala 215:28] + io.lsu_pkt_m.bits.load_ldst_bypass_d <= _T_132.bits.load_ldst_bypass_d @[el2_lsu_lsc_ctl.scala 215:28] + io.lsu_pkt_m.bits.store_data_bypass_d <= _T_132.bits.store_data_bypass_d @[el2_lsu_lsc_ctl.scala 215:28] + io.lsu_pkt_m.bits.dma <= _T_132.bits.dma @[el2_lsu_lsc_ctl.scala 215:28] + io.lsu_pkt_m.bits.unsign <= _T_132.bits.unsign @[el2_lsu_lsc_ctl.scala 215:28] + io.lsu_pkt_m.bits.store <= _T_132.bits.store @[el2_lsu_lsc_ctl.scala 215:28] + io.lsu_pkt_m.bits.load <= _T_132.bits.load @[el2_lsu_lsc_ctl.scala 215:28] + io.lsu_pkt_m.bits.dword <= _T_132.bits.dword @[el2_lsu_lsc_ctl.scala 215:28] + io.lsu_pkt_m.bits.word <= _T_132.bits.word @[el2_lsu_lsc_ctl.scala 215:28] + io.lsu_pkt_m.bits.half <= _T_132.bits.half @[el2_lsu_lsc_ctl.scala 215:28] + io.lsu_pkt_m.bits.by <= _T_132.bits.by @[el2_lsu_lsc_ctl.scala 215:28] + io.lsu_pkt_m.bits.fast_int <= _T_132.bits.fast_int @[el2_lsu_lsc_ctl.scala 215:28] io.lsu_pkt_m.valid <= _T_132.valid @[el2_lsu_lsc_ctl.scala 215:28] - io.lsu_pkt_m.store_data_bypass_m <= _T_132.store_data_bypass_m @[el2_lsu_lsc_ctl.scala 215:28] - io.lsu_pkt_m.load_ldst_bypass_d <= _T_132.load_ldst_bypass_d @[el2_lsu_lsc_ctl.scala 215:28] - io.lsu_pkt_m.store_data_bypass_d <= _T_132.store_data_bypass_d @[el2_lsu_lsc_ctl.scala 215:28] - io.lsu_pkt_m.dma <= _T_132.dma @[el2_lsu_lsc_ctl.scala 215:28] - io.lsu_pkt_m.unsign <= _T_132.unsign @[el2_lsu_lsc_ctl.scala 215:28] - io.lsu_pkt_m.store <= _T_132.store @[el2_lsu_lsc_ctl.scala 215:28] - io.lsu_pkt_m.load <= _T_132.load @[el2_lsu_lsc_ctl.scala 215:28] - io.lsu_pkt_m.dword <= _T_132.dword @[el2_lsu_lsc_ctl.scala 215:28] - io.lsu_pkt_m.word <= _T_132.word @[el2_lsu_lsc_ctl.scala 215:28] - io.lsu_pkt_m.half <= _T_132.half @[el2_lsu_lsc_ctl.scala 215:28] - io.lsu_pkt_m.by <= _T_132.by @[el2_lsu_lsc_ctl.scala 215:28] - io.lsu_pkt_m.fast_int <= _T_132.fast_int @[el2_lsu_lsc_ctl.scala 215:28] - wire _T_133 : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>} @[el2_lsu_lsc_ctl.scala 216:91] + wire _T_133 : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[el2_lsu_lsc_ctl.scala 216:91] + _T_133.bits.store_data_bypass_m <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91] + _T_133.bits.load_ldst_bypass_d <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91] + _T_133.bits.store_data_bypass_d <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91] + _T_133.bits.dma <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91] + _T_133.bits.unsign <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91] + _T_133.bits.store <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91] + _T_133.bits.load <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91] + _T_133.bits.dword <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91] + _T_133.bits.word <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91] + _T_133.bits.half <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91] + _T_133.bits.by <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91] + _T_133.bits.fast_int <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91] _T_133.valid <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91] - _T_133.store_data_bypass_m <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91] - _T_133.load_ldst_bypass_d <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91] - _T_133.store_data_bypass_d <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91] - _T_133.dma <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91] - _T_133.unsign <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91] - _T_133.store <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91] - _T_133.load <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91] - _T_133.dword <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91] - _T_133.word <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91] - _T_133.half <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91] - _T_133.by <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91] - _T_133.fast_int <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91] - reg _T_134 : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, io.lsu_c1_r_clk with : (reset => (reset, _T_133)) @[el2_lsu_lsc_ctl.scala 216:65] + reg _T_134 : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, io.lsu_c1_r_clk with : (reset => (reset, _T_133)) @[el2_lsu_lsc_ctl.scala 216:65] + _T_134.bits.store_data_bypass_m <= lsu_pkt_r_in.bits.store_data_bypass_m @[el2_lsu_lsc_ctl.scala 216:65] + _T_134.bits.load_ldst_bypass_d <= lsu_pkt_r_in.bits.load_ldst_bypass_d @[el2_lsu_lsc_ctl.scala 216:65] + _T_134.bits.store_data_bypass_d <= lsu_pkt_r_in.bits.store_data_bypass_d @[el2_lsu_lsc_ctl.scala 216:65] + _T_134.bits.dma <= lsu_pkt_r_in.bits.dma @[el2_lsu_lsc_ctl.scala 216:65] + _T_134.bits.unsign <= lsu_pkt_r_in.bits.unsign @[el2_lsu_lsc_ctl.scala 216:65] + _T_134.bits.store <= lsu_pkt_r_in.bits.store @[el2_lsu_lsc_ctl.scala 216:65] + _T_134.bits.load <= lsu_pkt_r_in.bits.load @[el2_lsu_lsc_ctl.scala 216:65] + _T_134.bits.dword <= lsu_pkt_r_in.bits.dword @[el2_lsu_lsc_ctl.scala 216:65] + _T_134.bits.word <= lsu_pkt_r_in.bits.word @[el2_lsu_lsc_ctl.scala 216:65] + _T_134.bits.half <= lsu_pkt_r_in.bits.half @[el2_lsu_lsc_ctl.scala 216:65] + _T_134.bits.by <= lsu_pkt_r_in.bits.by @[el2_lsu_lsc_ctl.scala 216:65] + _T_134.bits.fast_int <= lsu_pkt_r_in.bits.fast_int @[el2_lsu_lsc_ctl.scala 216:65] _T_134.valid <= lsu_pkt_r_in.valid @[el2_lsu_lsc_ctl.scala 216:65] - _T_134.store_data_bypass_m <= lsu_pkt_r_in.store_data_bypass_m @[el2_lsu_lsc_ctl.scala 216:65] - _T_134.load_ldst_bypass_d <= lsu_pkt_r_in.load_ldst_bypass_d @[el2_lsu_lsc_ctl.scala 216:65] - _T_134.store_data_bypass_d <= lsu_pkt_r_in.store_data_bypass_d @[el2_lsu_lsc_ctl.scala 216:65] - _T_134.dma <= lsu_pkt_r_in.dma @[el2_lsu_lsc_ctl.scala 216:65] - _T_134.unsign <= lsu_pkt_r_in.unsign @[el2_lsu_lsc_ctl.scala 216:65] - _T_134.store <= lsu_pkt_r_in.store @[el2_lsu_lsc_ctl.scala 216:65] - _T_134.load <= lsu_pkt_r_in.load @[el2_lsu_lsc_ctl.scala 216:65] - _T_134.dword <= lsu_pkt_r_in.dword @[el2_lsu_lsc_ctl.scala 216:65] - _T_134.word <= lsu_pkt_r_in.word @[el2_lsu_lsc_ctl.scala 216:65] - _T_134.half <= lsu_pkt_r_in.half @[el2_lsu_lsc_ctl.scala 216:65] - _T_134.by <= lsu_pkt_r_in.by @[el2_lsu_lsc_ctl.scala 216:65] - _T_134.fast_int <= lsu_pkt_r_in.fast_int @[el2_lsu_lsc_ctl.scala 216:65] + io.lsu_pkt_r.bits.store_data_bypass_m <= _T_134.bits.store_data_bypass_m @[el2_lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_r.bits.load_ldst_bypass_d <= _T_134.bits.load_ldst_bypass_d @[el2_lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_r.bits.store_data_bypass_d <= _T_134.bits.store_data_bypass_d @[el2_lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_r.bits.dma <= _T_134.bits.dma @[el2_lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_r.bits.unsign <= _T_134.bits.unsign @[el2_lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_r.bits.store <= _T_134.bits.store @[el2_lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_r.bits.load <= _T_134.bits.load @[el2_lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_r.bits.dword <= _T_134.bits.dword @[el2_lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_r.bits.word <= _T_134.bits.word @[el2_lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_r.bits.half <= _T_134.bits.half @[el2_lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_r.bits.by <= _T_134.bits.by @[el2_lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_r.bits.fast_int <= _T_134.bits.fast_int @[el2_lsu_lsc_ctl.scala 216:28] io.lsu_pkt_r.valid <= _T_134.valid @[el2_lsu_lsc_ctl.scala 216:28] - io.lsu_pkt_r.store_data_bypass_m <= _T_134.store_data_bypass_m @[el2_lsu_lsc_ctl.scala 216:28] - io.lsu_pkt_r.load_ldst_bypass_d <= _T_134.load_ldst_bypass_d @[el2_lsu_lsc_ctl.scala 216:28] - io.lsu_pkt_r.store_data_bypass_d <= _T_134.store_data_bypass_d @[el2_lsu_lsc_ctl.scala 216:28] - io.lsu_pkt_r.dma <= _T_134.dma @[el2_lsu_lsc_ctl.scala 216:28] - io.lsu_pkt_r.unsign <= _T_134.unsign @[el2_lsu_lsc_ctl.scala 216:28] - io.lsu_pkt_r.store <= _T_134.store @[el2_lsu_lsc_ctl.scala 216:28] - io.lsu_pkt_r.load <= _T_134.load @[el2_lsu_lsc_ctl.scala 216:28] - io.lsu_pkt_r.dword <= _T_134.dword @[el2_lsu_lsc_ctl.scala 216:28] - io.lsu_pkt_r.word <= _T_134.word @[el2_lsu_lsc_ctl.scala 216:28] - io.lsu_pkt_r.half <= _T_134.half @[el2_lsu_lsc_ctl.scala 216:28] - io.lsu_pkt_r.by <= _T_134.by @[el2_lsu_lsc_ctl.scala 216:28] - io.lsu_pkt_r.fast_int <= _T_134.fast_int @[el2_lsu_lsc_ctl.scala 216:28] reg _T_135 : UInt<1>, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 217:65] _T_135 <= lsu_pkt_m_in.valid @[el2_lsu_lsc_ctl.scala 217:65] io.lsu_pkt_m.valid <= _T_135 @[el2_lsu_lsc_ctl.scala 217:28] @@ -636,9 +636,9 @@ circuit el2_lsu_lsc_ctl : node _T_141 = bits(dma_mem_wdata_shifted, 31, 0) @[el2_lsu_lsc_ctl.scala 221:79] node _T_142 = bits(io.exu_lsu_rs2_d, 31, 0) @[el2_lsu_lsc_ctl.scala 221:102] node store_data_d = mux(_T_140, _T_141, _T_142) @[el2_lsu_lsc_ctl.scala 221:34] - node _T_143 = bits(io.lsu_pkt_d.store_data_bypass_d, 0, 0) @[el2_lsu_lsc_ctl.scala 222:68] - node _T_144 = bits(io.lsu_result_m, 31, 0) @[el2_lsu_lsc_ctl.scala 222:90] - node _T_145 = bits(store_data_d, 31, 0) @[el2_lsu_lsc_ctl.scala 222:109] + node _T_143 = bits(io.lsu_pkt_d.bits.store_data_bypass_d, 0, 0) @[el2_lsu_lsc_ctl.scala 222:73] + node _T_144 = bits(io.lsu_result_m, 31, 0) @[el2_lsu_lsc_ctl.scala 222:95] + node _T_145 = bits(store_data_d, 31, 0) @[el2_lsu_lsc_ctl.scala 222:114] node store_data_m_in = mux(_T_143, _T_144, _T_145) @[el2_lsu_lsc_ctl.scala 222:34] reg store_data_pre_m : UInt, io.lsu_store_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 224:72] store_data_pre_m <= store_data_m_in @[el2_lsu_lsc_ctl.scala 224:72] @@ -676,19 +676,19 @@ circuit el2_lsu_lsc_ctl : node _T_155 = bits(io.lsu_ld_data_corr_r, 31, 1) @[el2_lsu_lsc_ctl.scala 237:52] io.lsu_fir_addr <= _T_155 @[el2_lsu_lsc_ctl.scala 237:28] io.lsu_addr_d <= full_addr_d @[el2_lsu_lsc_ctl.scala 239:28] - node _T_156 = or(io.lsu_pkt_r.store, io.lsu_pkt_r.load) @[el2_lsu_lsc_ctl.scala 241:63] + node _T_156 = or(io.lsu_pkt_r.bits.store, io.lsu_pkt_r.bits.load) @[el2_lsu_lsc_ctl.scala 241:68] node _T_157 = and(io.lsu_pkt_r.valid, _T_156) @[el2_lsu_lsc_ctl.scala 241:41] - node _T_158 = eq(io.flush_r, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 241:86] - node _T_159 = and(_T_157, _T_158) @[el2_lsu_lsc_ctl.scala 241:84] - node _T_160 = eq(io.lsu_pkt_r.dma, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 241:100] - node _T_161 = and(_T_159, _T_160) @[el2_lsu_lsc_ctl.scala 241:98] + node _T_158 = eq(io.flush_r, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 241:96] + node _T_159 = and(_T_157, _T_158) @[el2_lsu_lsc_ctl.scala 241:94] + node _T_160 = eq(io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 241:110] + node _T_161 = and(_T_159, _T_160) @[el2_lsu_lsc_ctl.scala 241:108] io.lsu_commit_r <= _T_161 @[el2_lsu_lsc_ctl.scala 241:19] node _T_162 = bits(io.picm_mask_data_m, 31, 0) @[el2_lsu_lsc_ctl.scala 242:52] node _T_163 = eq(io.addr_in_pic_m, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 242:69] node _T_164 = bits(_T_163, 0, 0) @[Bitwise.scala 72:15] node _T_165 = mux(_T_164, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] node _T_166 = or(_T_162, _T_165) @[el2_lsu_lsc_ctl.scala 242:59] - node _T_167 = bits(io.lsu_pkt_m.store_data_bypass_m, 0, 0) @[el2_lsu_lsc_ctl.scala 242:128] + node _T_167 = bits(io.lsu_pkt_m.bits.store_data_bypass_m, 0, 0) @[el2_lsu_lsc_ctl.scala 242:133] node _T_168 = mux(_T_167, io.lsu_result_m, store_data_pre_m) @[el2_lsu_lsc_ctl.scala 242:94] node _T_169 = and(_T_166, _T_168) @[el2_lsu_lsc_ctl.scala 242:89] io.store_data_m <= _T_169 @[el2_lsu_lsc_ctl.scala 242:29] @@ -698,86 +698,86 @@ circuit el2_lsu_lsc_ctl : node _T_172 = eq(addr_external_r, UInt<1>("h01")) @[el2_lsu_lsc_ctl.scala 264:49] node _T_173 = mux(_T_172, bus_read_data_r, io.lsu_ld_data_corr_r) @[el2_lsu_lsc_ctl.scala 264:33] lsu_ld_datafn_corr_r <= _T_173 @[el2_lsu_lsc_ctl.scala 264:27] - node _T_174 = and(io.lsu_pkt_m.unsign, io.lsu_pkt_m.by) @[el2_lsu_lsc_ctl.scala 265:61] + node _T_174 = and(io.lsu_pkt_m.bits.unsign, io.lsu_pkt_m.bits.by) @[el2_lsu_lsc_ctl.scala 265:66] node _T_175 = bits(_T_174, 0, 0) @[Bitwise.scala 72:15] node _T_176 = mux(_T_175, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_177 = bits(lsu_ld_datafn_m, 7, 0) @[el2_lsu_lsc_ctl.scala 265:115] + node _T_177 = bits(lsu_ld_datafn_m, 7, 0) @[el2_lsu_lsc_ctl.scala 265:125] node _T_178 = cat(UInt<24>("h00"), _T_177) @[Cat.scala 29:58] - node _T_179 = and(_T_176, _T_178) @[el2_lsu_lsc_ctl.scala 265:84] - node _T_180 = and(io.lsu_pkt_m.unsign, io.lsu_pkt_m.half) @[el2_lsu_lsc_ctl.scala 266:38] + node _T_179 = and(_T_176, _T_178) @[el2_lsu_lsc_ctl.scala 265:94] + node _T_180 = and(io.lsu_pkt_m.bits.unsign, io.lsu_pkt_m.bits.half) @[el2_lsu_lsc_ctl.scala 266:43] node _T_181 = bits(_T_180, 0, 0) @[Bitwise.scala 72:15] node _T_182 = mux(_T_181, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_183 = bits(lsu_ld_datafn_m, 15, 0) @[el2_lsu_lsc_ctl.scala 266:92] + node _T_183 = bits(lsu_ld_datafn_m, 15, 0) @[el2_lsu_lsc_ctl.scala 266:102] node _T_184 = cat(UInt<16>("h00"), _T_183) @[Cat.scala 29:58] - node _T_185 = and(_T_182, _T_184) @[el2_lsu_lsc_ctl.scala 266:61] - node _T_186 = or(_T_179, _T_185) @[el2_lsu_lsc_ctl.scala 265:123] - node _T_187 = eq(io.lsu_pkt_m.unsign, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 267:17] - node _T_188 = and(_T_187, io.lsu_pkt_m.by) @[el2_lsu_lsc_ctl.scala 267:38] + node _T_185 = and(_T_182, _T_184) @[el2_lsu_lsc_ctl.scala 266:71] + node _T_186 = or(_T_179, _T_185) @[el2_lsu_lsc_ctl.scala 265:133] + node _T_187 = eq(io.lsu_pkt_m.bits.unsign, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 267:17] + node _T_188 = and(_T_187, io.lsu_pkt_m.bits.by) @[el2_lsu_lsc_ctl.scala 267:43] node _T_189 = bits(_T_188, 0, 0) @[Bitwise.scala 72:15] node _T_190 = mux(_T_189, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_191 = bits(lsu_ld_datafn_m, 7, 7) @[el2_lsu_lsc_ctl.scala 267:92] + node _T_191 = bits(lsu_ld_datafn_m, 7, 7) @[el2_lsu_lsc_ctl.scala 267:102] node _T_192 = bits(_T_191, 0, 0) @[Bitwise.scala 72:15] node _T_193 = mux(_T_192, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12] - node _T_194 = bits(lsu_ld_datafn_m, 7, 0) @[el2_lsu_lsc_ctl.scala 267:115] + node _T_194 = bits(lsu_ld_datafn_m, 7, 0) @[el2_lsu_lsc_ctl.scala 267:125] node _T_195 = cat(_T_193, _T_194) @[Cat.scala 29:58] - node _T_196 = and(_T_190, _T_195) @[el2_lsu_lsc_ctl.scala 267:61] - node _T_197 = or(_T_186, _T_196) @[el2_lsu_lsc_ctl.scala 266:104] - node _T_198 = eq(io.lsu_pkt_m.unsign, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 268:17] - node _T_199 = and(_T_198, io.lsu_pkt_m.half) @[el2_lsu_lsc_ctl.scala 268:38] + node _T_196 = and(_T_190, _T_195) @[el2_lsu_lsc_ctl.scala 267:71] + node _T_197 = or(_T_186, _T_196) @[el2_lsu_lsc_ctl.scala 266:114] + node _T_198 = eq(io.lsu_pkt_m.bits.unsign, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 268:17] + node _T_199 = and(_T_198, io.lsu_pkt_m.bits.half) @[el2_lsu_lsc_ctl.scala 268:43] node _T_200 = bits(_T_199, 0, 0) @[Bitwise.scala 72:15] node _T_201 = mux(_T_200, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_202 = bits(lsu_ld_datafn_m, 15, 15) @[el2_lsu_lsc_ctl.scala 268:91] + node _T_202 = bits(lsu_ld_datafn_m, 15, 15) @[el2_lsu_lsc_ctl.scala 268:101] node _T_203 = bits(_T_202, 0, 0) @[Bitwise.scala 72:15] node _T_204 = mux(_T_203, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12] - node _T_205 = bits(lsu_ld_datafn_m, 15, 0) @[el2_lsu_lsc_ctl.scala 268:115] + node _T_205 = bits(lsu_ld_datafn_m, 15, 0) @[el2_lsu_lsc_ctl.scala 268:125] node _T_206 = cat(_T_204, _T_205) @[Cat.scala 29:58] - node _T_207 = and(_T_201, _T_206) @[el2_lsu_lsc_ctl.scala 268:61] - node _T_208 = or(_T_197, _T_207) @[el2_lsu_lsc_ctl.scala 267:124] - node _T_209 = bits(io.lsu_pkt_m.word, 0, 0) @[Bitwise.scala 72:15] + node _T_207 = and(_T_201, _T_206) @[el2_lsu_lsc_ctl.scala 268:71] + node _T_208 = or(_T_197, _T_207) @[el2_lsu_lsc_ctl.scala 267:134] + node _T_209 = bits(io.lsu_pkt_m.bits.word, 0, 0) @[Bitwise.scala 72:15] node _T_210 = mux(_T_209, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_211 = bits(lsu_ld_datafn_m, 31, 0) @[el2_lsu_lsc_ctl.scala 269:55] - node _T_212 = and(_T_210, _T_211) @[el2_lsu_lsc_ctl.scala 269:38] - node _T_213 = or(_T_208, _T_212) @[el2_lsu_lsc_ctl.scala 268:124] + node _T_211 = bits(lsu_ld_datafn_m, 31, 0) @[el2_lsu_lsc_ctl.scala 269:60] + node _T_212 = and(_T_210, _T_211) @[el2_lsu_lsc_ctl.scala 269:43] + node _T_213 = or(_T_208, _T_212) @[el2_lsu_lsc_ctl.scala 268:134] io.lsu_result_m <= _T_213 @[el2_lsu_lsc_ctl.scala 265:27] - node _T_214 = and(io.lsu_pkt_r.unsign, io.lsu_pkt_r.by) @[el2_lsu_lsc_ctl.scala 270:61] + node _T_214 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.by) @[el2_lsu_lsc_ctl.scala 270:66] node _T_215 = bits(_T_214, 0, 0) @[Bitwise.scala 72:15] node _T_216 = mux(_T_215, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_217 = bits(lsu_ld_datafn_corr_r, 7, 0) @[el2_lsu_lsc_ctl.scala 270:120] + node _T_217 = bits(lsu_ld_datafn_corr_r, 7, 0) @[el2_lsu_lsc_ctl.scala 270:130] node _T_218 = cat(UInt<24>("h00"), _T_217) @[Cat.scala 29:58] - node _T_219 = and(_T_216, _T_218) @[el2_lsu_lsc_ctl.scala 270:84] - node _T_220 = and(io.lsu_pkt_r.unsign, io.lsu_pkt_r.half) @[el2_lsu_lsc_ctl.scala 271:38] + node _T_219 = and(_T_216, _T_218) @[el2_lsu_lsc_ctl.scala 270:94] + node _T_220 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.half) @[el2_lsu_lsc_ctl.scala 271:43] node _T_221 = bits(_T_220, 0, 0) @[Bitwise.scala 72:15] node _T_222 = mux(_T_221, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_223 = bits(lsu_ld_datafn_corr_r, 15, 0) @[el2_lsu_lsc_ctl.scala 271:97] + node _T_223 = bits(lsu_ld_datafn_corr_r, 15, 0) @[el2_lsu_lsc_ctl.scala 271:107] node _T_224 = cat(UInt<16>("h00"), _T_223) @[Cat.scala 29:58] - node _T_225 = and(_T_222, _T_224) @[el2_lsu_lsc_ctl.scala 271:61] - node _T_226 = or(_T_219, _T_225) @[el2_lsu_lsc_ctl.scala 270:128] - node _T_227 = eq(io.lsu_pkt_r.unsign, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 272:17] - node _T_228 = and(_T_227, io.lsu_pkt_r.by) @[el2_lsu_lsc_ctl.scala 272:38] + node _T_225 = and(_T_222, _T_224) @[el2_lsu_lsc_ctl.scala 271:71] + node _T_226 = or(_T_219, _T_225) @[el2_lsu_lsc_ctl.scala 270:138] + node _T_227 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 272:17] + node _T_228 = and(_T_227, io.lsu_pkt_r.bits.by) @[el2_lsu_lsc_ctl.scala 272:43] node _T_229 = bits(_T_228, 0, 0) @[Bitwise.scala 72:15] node _T_230 = mux(_T_229, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_231 = bits(lsu_ld_datafn_corr_r, 7, 7) @[el2_lsu_lsc_ctl.scala 272:97] + node _T_231 = bits(lsu_ld_datafn_corr_r, 7, 7) @[el2_lsu_lsc_ctl.scala 272:107] node _T_232 = bits(_T_231, 0, 0) @[Bitwise.scala 72:15] node _T_233 = mux(_T_232, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12] - node _T_234 = bits(lsu_ld_datafn_corr_r, 7, 0) @[el2_lsu_lsc_ctl.scala 272:125] + node _T_234 = bits(lsu_ld_datafn_corr_r, 7, 0) @[el2_lsu_lsc_ctl.scala 272:135] node _T_235 = cat(_T_233, _T_234) @[Cat.scala 29:58] - node _T_236 = and(_T_230, _T_235) @[el2_lsu_lsc_ctl.scala 272:61] - node _T_237 = or(_T_226, _T_236) @[el2_lsu_lsc_ctl.scala 271:109] - node _T_238 = eq(io.lsu_pkt_r.unsign, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 273:17] - node _T_239 = and(_T_238, io.lsu_pkt_r.half) @[el2_lsu_lsc_ctl.scala 273:38] + node _T_236 = and(_T_230, _T_235) @[el2_lsu_lsc_ctl.scala 272:71] + node _T_237 = or(_T_226, _T_236) @[el2_lsu_lsc_ctl.scala 271:119] + node _T_238 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 273:17] + node _T_239 = and(_T_238, io.lsu_pkt_r.bits.half) @[el2_lsu_lsc_ctl.scala 273:43] node _T_240 = bits(_T_239, 0, 0) @[Bitwise.scala 72:15] node _T_241 = mux(_T_240, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_242 = bits(lsu_ld_datafn_corr_r, 15, 15) @[el2_lsu_lsc_ctl.scala 273:96] + node _T_242 = bits(lsu_ld_datafn_corr_r, 15, 15) @[el2_lsu_lsc_ctl.scala 273:106] node _T_243 = bits(_T_242, 0, 0) @[Bitwise.scala 72:15] node _T_244 = mux(_T_243, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12] - node _T_245 = bits(lsu_ld_datafn_corr_r, 15, 0) @[el2_lsu_lsc_ctl.scala 273:125] + node _T_245 = bits(lsu_ld_datafn_corr_r, 15, 0) @[el2_lsu_lsc_ctl.scala 273:135] node _T_246 = cat(_T_244, _T_245) @[Cat.scala 29:58] - node _T_247 = and(_T_241, _T_246) @[el2_lsu_lsc_ctl.scala 273:61] - node _T_248 = or(_T_237, _T_247) @[el2_lsu_lsc_ctl.scala 272:134] - node _T_249 = bits(io.lsu_pkt_r.word, 0, 0) @[Bitwise.scala 72:15] + node _T_247 = and(_T_241, _T_246) @[el2_lsu_lsc_ctl.scala 273:71] + node _T_248 = or(_T_237, _T_247) @[el2_lsu_lsc_ctl.scala 272:144] + node _T_249 = bits(io.lsu_pkt_r.bits.word, 0, 0) @[Bitwise.scala 72:15] node _T_250 = mux(_T_249, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_251 = bits(lsu_ld_datafn_corr_r, 31, 0) @[el2_lsu_lsc_ctl.scala 274:60] - node _T_252 = and(_T_250, _T_251) @[el2_lsu_lsc_ctl.scala 274:38] - node _T_253 = or(_T_248, _T_252) @[el2_lsu_lsc_ctl.scala 273:134] + node _T_251 = bits(lsu_ld_datafn_corr_r, 31, 0) @[el2_lsu_lsc_ctl.scala 274:65] + node _T_252 = and(_T_250, _T_251) @[el2_lsu_lsc_ctl.scala 274:43] + node _T_253 = or(_T_248, _T_252) @[el2_lsu_lsc_ctl.scala 273:144] io.lsu_result_corr_r <= _T_253 @[el2_lsu_lsc_ctl.scala 270:27] diff --git a/el2_lsu_lsc_ctl.v b/el2_lsu_lsc_ctl.v index 8a8b395a..d70bf134 100644 --- a/el2_lsu_lsc_ctl.v +++ b/el2_lsu_lsc_ctl.v @@ -3,14 +3,14 @@ module el2_lsu_addrcheck( input io_lsu_c2_m_clk, input [31:0] io_start_addr_d, input [31:0] io_end_addr_d, - input io_lsu_pkt_d_fast_int, - input io_lsu_pkt_d_by, - input io_lsu_pkt_d_half, - input io_lsu_pkt_d_word, - input io_lsu_pkt_d_load, - input io_lsu_pkt_d_store, - input io_lsu_pkt_d_dma, input io_lsu_pkt_d_valid, + input io_lsu_pkt_d_bits_fast_int, + input io_lsu_pkt_d_bits_by, + input io_lsu_pkt_d_bits_half, + input io_lsu_pkt_d_bits_word, + input io_lsu_pkt_d_bits_load, + input io_lsu_pkt_d_bits_store, + input io_lsu_pkt_d_bits_dma, input [31:0] io_dec_tlu_mrac_ff, input [3:0] io_rs1_region_d, output io_is_sideeffects_m, @@ -42,14 +42,14 @@ module el2_lsu_addrcheck( wire _T_29 = ~_T_28; // @[el2_lsu_addrcheck.scala 61:62] wire _T_30 = _T_25[0] & _T_29; // @[el2_lsu_addrcheck.scala 61:60] wire _T_31 = _T_30 & io_lsu_pkt_d_valid; // @[el2_lsu_addrcheck.scala 61:137] - wire _T_32 = io_lsu_pkt_d_store | io_lsu_pkt_d_load; // @[el2_lsu_addrcheck.scala 61:180] + wire _T_32 = io_lsu_pkt_d_bits_store | io_lsu_pkt_d_bits_load; // @[el2_lsu_addrcheck.scala 61:185] wire is_sideeffects_d = _T_31 & _T_32; // @[el2_lsu_addrcheck.scala 61:158] - wire _T_34 = io_start_addr_d[1:0] == 2'h0; // @[el2_lsu_addrcheck.scala 62:75] - wire _T_35 = io_lsu_pkt_d_word & _T_34; // @[el2_lsu_addrcheck.scala 62:51] - wire _T_37 = ~io_start_addr_d[0]; // @[el2_lsu_addrcheck.scala 62:128] - wire _T_38 = io_lsu_pkt_d_half & _T_37; // @[el2_lsu_addrcheck.scala 62:106] - wire _T_39 = _T_35 | _T_38; // @[el2_lsu_addrcheck.scala 62:85] - wire is_aligned_d = _T_39 | io_lsu_pkt_d_by; // @[el2_lsu_addrcheck.scala 62:138] + wire _T_34 = io_start_addr_d[1:0] == 2'h0; // @[el2_lsu_addrcheck.scala 62:80] + wire _T_35 = io_lsu_pkt_d_bits_word & _T_34; // @[el2_lsu_addrcheck.scala 62:56] + wire _T_37 = ~io_start_addr_d[0]; // @[el2_lsu_addrcheck.scala 62:138] + wire _T_38 = io_lsu_pkt_d_bits_half & _T_37; // @[el2_lsu_addrcheck.scala 62:116] + wire _T_39 = _T_35 | _T_38; // @[el2_lsu_addrcheck.scala 62:90] + wire is_aligned_d = _T_39 | io_lsu_pkt_d_bits_by; // @[el2_lsu_addrcheck.scala 62:148] wire [31:0] _T_50 = io_start_addr_d | 32'h7fffffff; // @[el2_lsu_addrcheck.scala 67:56] wire _T_52 = _T_50 == 32'h7fffffff; // @[el2_lsu_addrcheck.scala 67:88] wire [31:0] _T_55 = io_start_addr_d | 32'h3fffffff; // @[el2_lsu_addrcheck.scala 68:56] @@ -75,7 +75,7 @@ module el2_lsu_addrcheck( wire non_dccm_access_ok = _T_71 & _T_118; // @[el2_lsu_addrcheck.scala 75:7] wire regpred_access_fault_d = start_addr_dccm_or_pic ^ base_reg_dccm_or_pic; // @[el2_lsu_addrcheck.scala 85:57] wire _T_145 = io_start_addr_d[1:0] != 2'h0; // @[el2_lsu_addrcheck.scala 86:76] - wire _T_146 = ~io_lsu_pkt_d_word; // @[el2_lsu_addrcheck.scala 86:92] + wire _T_146 = ~io_lsu_pkt_d_bits_word; // @[el2_lsu_addrcheck.scala 86:92] wire _T_147 = _T_145 | _T_146; // @[el2_lsu_addrcheck.scala 86:90] wire picm_access_fault_d = io_addr_in_pic_d & _T_147; // @[el2_lsu_addrcheck.scala 86:51] wire _T_148 = start_addr_in_dccm_d | start_addr_in_pic_d; // @[el2_lsu_addrcheck.scala 91:87] @@ -96,7 +96,7 @@ module el2_lsu_addrcheck( wire _T_163 = _T_162 | picm_access_fault_d; // @[el2_lsu_addrcheck.scala 111:70] wire _T_164 = _T_163 | regpred_access_fault_d; // @[el2_lsu_addrcheck.scala 111:92] wire _T_165 = _T_164 & io_lsu_pkt_d_valid; // @[el2_lsu_addrcheck.scala 111:118] - wire _T_166 = ~io_lsu_pkt_d_dma; // @[el2_lsu_addrcheck.scala 111:141] + wire _T_166 = ~io_lsu_pkt_d_bits_dma; // @[el2_lsu_addrcheck.scala 111:141] wire [3:0] _T_172 = picm_access_fault_d ? 4'h6 : 4'h0; // @[el2_lsu_addrcheck.scala 112:164] wire [3:0] _T_173 = regpred_access_fault_d ? 4'h5 : _T_172; // @[el2_lsu_addrcheck.scala 112:120] wire [3:0] _T_174 = mpu_access_fault_d ? 4'h3 : _T_173; // @[el2_lsu_addrcheck.scala 112:80] @@ -126,8 +126,8 @@ module el2_lsu_addrcheck( assign io_access_fault_d = _T_165 & _T_166; // @[el2_lsu_addrcheck.scala 111:21] assign io_misaligned_fault_d = _T_180 & _T_166; // @[el2_lsu_addrcheck.scala 115:25] assign io_exc_mscause_d = io_misaligned_fault_d ? misaligned_fault_mscause_d : access_fault_mscause_d; // @[el2_lsu_addrcheck.scala 117:21] - assign io_fir_dccm_access_error_d = _T_194 & io_lsu_pkt_d_fast_int; // @[el2_lsu_addrcheck.scala 118:31] - assign io_fir_nondccm_access_error_d = _T_198 & io_lsu_pkt_d_fast_int; // @[el2_lsu_addrcheck.scala 119:33] + assign io_fir_dccm_access_error_d = _T_194 & io_lsu_pkt_d_bits_fast_int; // @[el2_lsu_addrcheck.scala 118:31] + assign io_fir_nondccm_access_error_d = _T_198 & io_lsu_pkt_d_bits_fast_int; // @[el2_lsu_addrcheck.scala 119:33] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -202,19 +202,19 @@ module el2_lsu_lsc_ctl( input io_flush_r, input [31:0] io_exu_lsu_rs1_d, input [31:0] io_exu_lsu_rs2_d, - input io_lsu_p_fast_int, - input io_lsu_p_by, - input io_lsu_p_half, - input io_lsu_p_word, - input io_lsu_p_dword, - input io_lsu_p_load, - input io_lsu_p_store, - input io_lsu_p_unsign, - input io_lsu_p_dma, - input io_lsu_p_store_data_bypass_d, - input io_lsu_p_load_ldst_bypass_d, - input io_lsu_p_store_data_bypass_m, input io_lsu_p_valid, + input io_lsu_p_bits_fast_int, + input io_lsu_p_bits_by, + input io_lsu_p_bits_half, + input io_lsu_p_bits_word, + input io_lsu_p_bits_dword, + input io_lsu_p_bits_load, + input io_lsu_p_bits_store, + input io_lsu_p_bits_unsign, + input io_lsu_p_bits_dma, + input io_lsu_p_bits_store_data_bypass_d, + input io_lsu_p_bits_load_ldst_bypass_d, + input io_lsu_p_bits_store_data_bypass_m, input io_dec_lsu_valid_raw_d, input [11:0] io_dec_lsu_offset_d, input [31:0] io_picm_mask_data_m, @@ -237,8 +237,8 @@ module el2_lsu_lsc_ctl( output io_lsu_error_pkt_r_bits_single_ecc_error, output io_lsu_error_pkt_r_bits_inst_type, output io_lsu_error_pkt_r_bits_exc_type, - output io_lsu_error_pkt_r_bits_mscause, - output io_lsu_error_pkt_r_bits_addr, + output [3:0] io_lsu_error_pkt_r_bits_mscause, + output [31:0] io_lsu_error_pkt_r_bits_addr, output [30:0] io_lsu_fir_addr, output [1:0] io_lsu_fir_error, output io_addr_in_dccm_d, @@ -253,45 +253,45 @@ module el2_lsu_lsc_ctl( input [2:0] io_dma_mem_sz, input io_dma_mem_write, input [63:0] io_dma_mem_wdata, - output io_lsu_pkt_d_fast_int, - output io_lsu_pkt_d_by, - output io_lsu_pkt_d_half, - output io_lsu_pkt_d_word, - output io_lsu_pkt_d_dword, - output io_lsu_pkt_d_load, - output io_lsu_pkt_d_store, - output io_lsu_pkt_d_unsign, - output io_lsu_pkt_d_dma, - output io_lsu_pkt_d_store_data_bypass_d, - output io_lsu_pkt_d_load_ldst_bypass_d, - output io_lsu_pkt_d_store_data_bypass_m, output io_lsu_pkt_d_valid, - output io_lsu_pkt_m_fast_int, - output io_lsu_pkt_m_by, - output io_lsu_pkt_m_half, - output io_lsu_pkt_m_word, - output io_lsu_pkt_m_dword, - output io_lsu_pkt_m_load, - output io_lsu_pkt_m_store, - output io_lsu_pkt_m_unsign, - output io_lsu_pkt_m_dma, - output io_lsu_pkt_m_store_data_bypass_d, - output io_lsu_pkt_m_load_ldst_bypass_d, - output io_lsu_pkt_m_store_data_bypass_m, + output io_lsu_pkt_d_bits_fast_int, + output io_lsu_pkt_d_bits_by, + output io_lsu_pkt_d_bits_half, + output io_lsu_pkt_d_bits_word, + output io_lsu_pkt_d_bits_dword, + output io_lsu_pkt_d_bits_load, + output io_lsu_pkt_d_bits_store, + output io_lsu_pkt_d_bits_unsign, + output io_lsu_pkt_d_bits_dma, + output io_lsu_pkt_d_bits_store_data_bypass_d, + output io_lsu_pkt_d_bits_load_ldst_bypass_d, + output io_lsu_pkt_d_bits_store_data_bypass_m, output io_lsu_pkt_m_valid, - output io_lsu_pkt_r_fast_int, - output io_lsu_pkt_r_by, - output io_lsu_pkt_r_half, - output io_lsu_pkt_r_word, - output io_lsu_pkt_r_dword, - output io_lsu_pkt_r_load, - output io_lsu_pkt_r_store, - output io_lsu_pkt_r_unsign, - output io_lsu_pkt_r_dma, - output io_lsu_pkt_r_store_data_bypass_d, - output io_lsu_pkt_r_load_ldst_bypass_d, - output io_lsu_pkt_r_store_data_bypass_m, + output io_lsu_pkt_m_bits_fast_int, + output io_lsu_pkt_m_bits_by, + output io_lsu_pkt_m_bits_half, + output io_lsu_pkt_m_bits_word, + output io_lsu_pkt_m_bits_dword, + output io_lsu_pkt_m_bits_load, + output io_lsu_pkt_m_bits_store, + output io_lsu_pkt_m_bits_unsign, + output io_lsu_pkt_m_bits_dma, + output io_lsu_pkt_m_bits_store_data_bypass_d, + output io_lsu_pkt_m_bits_load_ldst_bypass_d, + output io_lsu_pkt_m_bits_store_data_bypass_m, output io_lsu_pkt_r_valid, + output io_lsu_pkt_r_bits_fast_int, + output io_lsu_pkt_r_bits_by, + output io_lsu_pkt_r_bits_half, + output io_lsu_pkt_r_bits_word, + output io_lsu_pkt_r_bits_dword, + output io_lsu_pkt_r_bits_load, + output io_lsu_pkt_r_bits_store, + output io_lsu_pkt_r_bits_unsign, + output io_lsu_pkt_r_bits_dma, + output io_lsu_pkt_r_bits_store_data_bypass_d, + output io_lsu_pkt_r_bits_load_ldst_bypass_d, + output io_lsu_pkt_r_bits_store_data_bypass_m, input io_scan_mode ); `ifdef RANDOMIZE_REG_INIT @@ -350,14 +350,14 @@ module el2_lsu_lsc_ctl( wire addrcheck_io_lsu_c2_m_clk; // @[el2_lsu_lsc_ctl.scala 119:25] wire [31:0] addrcheck_io_start_addr_d; // @[el2_lsu_lsc_ctl.scala 119:25] wire [31:0] addrcheck_io_end_addr_d; // @[el2_lsu_lsc_ctl.scala 119:25] - wire addrcheck_io_lsu_pkt_d_fast_int; // @[el2_lsu_lsc_ctl.scala 119:25] - wire addrcheck_io_lsu_pkt_d_by; // @[el2_lsu_lsc_ctl.scala 119:25] - wire addrcheck_io_lsu_pkt_d_half; // @[el2_lsu_lsc_ctl.scala 119:25] - wire addrcheck_io_lsu_pkt_d_word; // @[el2_lsu_lsc_ctl.scala 119:25] - wire addrcheck_io_lsu_pkt_d_load; // @[el2_lsu_lsc_ctl.scala 119:25] - wire addrcheck_io_lsu_pkt_d_store; // @[el2_lsu_lsc_ctl.scala 119:25] - wire addrcheck_io_lsu_pkt_d_dma; // @[el2_lsu_lsc_ctl.scala 119:25] wire addrcheck_io_lsu_pkt_d_valid; // @[el2_lsu_lsc_ctl.scala 119:25] + wire addrcheck_io_lsu_pkt_d_bits_fast_int; // @[el2_lsu_lsc_ctl.scala 119:25] + wire addrcheck_io_lsu_pkt_d_bits_by; // @[el2_lsu_lsc_ctl.scala 119:25] + wire addrcheck_io_lsu_pkt_d_bits_half; // @[el2_lsu_lsc_ctl.scala 119:25] + wire addrcheck_io_lsu_pkt_d_bits_word; // @[el2_lsu_lsc_ctl.scala 119:25] + wire addrcheck_io_lsu_pkt_d_bits_load; // @[el2_lsu_lsc_ctl.scala 119:25] + wire addrcheck_io_lsu_pkt_d_bits_store; // @[el2_lsu_lsc_ctl.scala 119:25] + wire addrcheck_io_lsu_pkt_d_bits_dma; // @[el2_lsu_lsc_ctl.scala 119:25] wire [31:0] addrcheck_io_dec_tlu_mrac_ff; // @[el2_lsu_lsc_ctl.scala 119:25] wire [3:0] addrcheck_io_rs1_region_d; // @[el2_lsu_lsc_ctl.scala 119:25] wire addrcheck_io_is_sideeffects_m; // @[el2_lsu_lsc_ctl.scala 119:25] @@ -372,7 +372,7 @@ module el2_lsu_lsc_ctl( wire [31:0] lsu_rs1_d = io_dec_lsu_valid_raw_d ? io_exu_lsu_rs1_d : io_dma_mem_addr; // @[el2_lsu_lsc_ctl.scala 101:28] wire [11:0] _T_3 = io_dec_lsu_valid_raw_d ? 12'hfff : 12'h0; // @[Bitwise.scala 72:12] wire [11:0] lsu_offset_d = io_dec_lsu_offset_d & _T_3; // @[el2_lsu_lsc_ctl.scala 102:51] - wire [31:0] rs1_d = io_lsu_pkt_d_load_ldst_bypass_d ? io_lsu_result_m : lsu_rs1_d; // @[el2_lsu_lsc_ctl.scala 105:28] + wire [31:0] rs1_d = io_lsu_pkt_d_bits_load_ldst_bypass_d ? io_lsu_result_m : lsu_rs1_d; // @[el2_lsu_lsc_ctl.scala 105:28] wire [12:0] _T_6 = {1'h0,rs1_d[11:0]}; // @[Cat.scala 29:58] wire [12:0] _T_8 = {1'h0,lsu_offset_d}; // @[Cat.scala 29:58] wire [12:0] _T_10 = _T_6 + _T_8; // @[el2_lib.scala 232:39] @@ -392,13 +392,13 @@ module el2_lsu_lsc_ctl( wire [19:0] _T_38 = rs1_d[31:12] - 20'h1; // @[el2_lib.scala 235:54] wire [19:0] _T_39 = _T_35 & _T_38; // @[el2_lib.scala 235:41] wire [19:0] _T_40 = _T_29 | _T_39; // @[el2_lib.scala 234:61] - wire [2:0] _T_43 = io_lsu_pkt_d_half ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_44 = _T_43 & 3'h1; // @[el2_lsu_lsc_ctl.scala 110:53] - wire [2:0] _T_46 = io_lsu_pkt_d_word ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_47 = _T_46 & 3'h3; // @[el2_lsu_lsc_ctl.scala 111:35] - wire [2:0] _T_48 = _T_44 | _T_47; // @[el2_lsu_lsc_ctl.scala 110:65] - wire [2:0] _T_50 = io_lsu_pkt_d_dword ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] addr_offset_d = _T_48 | _T_50; // @[el2_lsu_lsc_ctl.scala 111:47] + wire [2:0] _T_43 = io_lsu_pkt_d_bits_half ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_44 = _T_43 & 3'h1; // @[el2_lsu_lsc_ctl.scala 110:58] + wire [2:0] _T_46 = io_lsu_pkt_d_bits_word ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_47 = _T_46 & 3'h3; // @[el2_lsu_lsc_ctl.scala 111:40] + wire [2:0] _T_48 = _T_44 | _T_47; // @[el2_lsu_lsc_ctl.scala 110:70] + wire [2:0] _T_50 = io_lsu_pkt_d_bits_dword ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] addr_offset_d = _T_48 | _T_50; // @[el2_lsu_lsc_ctl.scala 111:52] wire [12:0] _T_54 = {lsu_offset_d[11],lsu_offset_d}; // @[Cat.scala 29:58] wire [11:0] _T_57 = {9'h0,addr_offset_d}; // @[Cat.scala 29:58] wire [12:0] _GEN_0 = {{1'd0}, _T_57}; // @[el2_lsu_lsc_ctl.scala 114:60] @@ -413,69 +413,68 @@ module el2_lsu_lsc_ctl( wire _T_69 = access_fault_m | misaligned_fault_m; // @[el2_lsu_lsc_ctl.scala 156:34] wire _T_70 = ~io_lsu_double_ecc_error_r; // @[el2_lsu_lsc_ctl.scala 157:64] wire _T_71 = io_lsu_single_ecc_error_r & _T_70; // @[el2_lsu_lsc_ctl.scala 157:62] - wire _T_72 = io_lsu_commit_r | io_lsu_pkt_r_dma; // @[el2_lsu_lsc_ctl.scala 157:111] + wire _T_72 = io_lsu_commit_r | io_lsu_pkt_r_bits_dma; // @[el2_lsu_lsc_ctl.scala 157:111] wire _T_73 = _T_71 & _T_72; // @[el2_lsu_lsc_ctl.scala 157:92] wire _T_76 = _T_69 | io_lsu_double_ecc_error_m; // @[el2_lsu_lsc_ctl.scala 179:67] wire _T_77 = _T_76 & io_lsu_pkt_m_valid; // @[el2_lsu_lsc_ctl.scala 179:96] - wire _T_78 = ~io_lsu_pkt_m_dma; // @[el2_lsu_lsc_ctl.scala 179:119] + wire _T_78 = ~io_lsu_pkt_m_bits_dma; // @[el2_lsu_lsc_ctl.scala 179:119] wire _T_79 = _T_77 & _T_78; // @[el2_lsu_lsc_ctl.scala 179:117] - wire _T_80 = ~io_lsu_pkt_m_fast_int; // @[el2_lsu_lsc_ctl.scala 179:139] - wire _T_81 = _T_79 & _T_80; // @[el2_lsu_lsc_ctl.scala 179:137] - wire _T_82 = ~io_flush_m_up; // @[el2_lsu_lsc_ctl.scala 179:164] - wire lsu_error_pkt_m_valid = _T_81 & _T_82; // @[el2_lsu_lsc_ctl.scala 179:162] + wire _T_80 = ~io_lsu_pkt_m_bits_fast_int; // @[el2_lsu_lsc_ctl.scala 179:144] + wire _T_81 = _T_79 & _T_80; // @[el2_lsu_lsc_ctl.scala 179:142] + wire _T_82 = ~io_flush_m_up; // @[el2_lsu_lsc_ctl.scala 179:174] + wire lsu_error_pkt_m_valid = _T_81 & _T_82; // @[el2_lsu_lsc_ctl.scala 179:172] wire _T_84 = ~lsu_error_pkt_m_valid; // @[el2_lsu_lsc_ctl.scala 180:75] wire _T_85 = io_lsu_single_ecc_error_m & _T_84; // @[el2_lsu_lsc_ctl.scala 180:73] wire lsu_error_pkt_m_bits_exc_type = ~misaligned_fault_m; // @[el2_lsu_lsc_ctl.scala 182:46] wire _T_90 = io_lsu_double_ecc_error_m & lsu_error_pkt_m_bits_exc_type; // @[el2_lsu_lsc_ctl.scala 183:78] wire _T_91 = ~access_fault_m; // @[el2_lsu_lsc_ctl.scala 183:102] wire _T_92 = _T_90 & _T_91; // @[el2_lsu_lsc_ctl.scala 183:100] - wire [3:0] _T_95 = _T_92 ? 4'h1 : exc_mscause_m; // @[el2_lsu_lsc_ctl.scala 183:49] - wire _T_99 = io_lsu_pkt_m_fast_int & io_lsu_double_ecc_error_m; // @[el2_lsu_lsc_ctl.scala 185:161] + wire _T_99 = io_lsu_pkt_m_bits_fast_int & io_lsu_double_ecc_error_m; // @[el2_lsu_lsc_ctl.scala 185:166] reg _T_105_valid; // @[el2_lsu_lsc_ctl.scala 186:75] reg _T_105_bits_single_ecc_error; // @[el2_lsu_lsc_ctl.scala 186:75] reg _T_105_bits_inst_type; // @[el2_lsu_lsc_ctl.scala 186:75] reg _T_105_bits_exc_type; // @[el2_lsu_lsc_ctl.scala 186:75] - reg _T_105_bits_mscause; // @[el2_lsu_lsc_ctl.scala 186:75] - reg _T_105_bits_addr; // @[el2_lsu_lsc_ctl.scala 186:75] + reg [3:0] _T_105_bits_mscause; // @[el2_lsu_lsc_ctl.scala 186:75] + reg [31:0] _T_105_bits_addr; // @[el2_lsu_lsc_ctl.scala 186:75] reg [1:0] _T_106; // @[el2_lsu_lsc_ctl.scala 187:75] - wire dma_pkt_d_load = ~io_dma_mem_write; // @[el2_lsu_lsc_ctl.scala 194:25] - wire dma_pkt_d_by = io_dma_mem_sz == 3'h0; // @[el2_lsu_lsc_ctl.scala 195:45] - wire dma_pkt_d_half = io_dma_mem_sz == 3'h1; // @[el2_lsu_lsc_ctl.scala 196:45] - wire dma_pkt_d_word = io_dma_mem_sz == 3'h2; // @[el2_lsu_lsc_ctl.scala 197:45] - wire dma_pkt_d_dword = io_dma_mem_sz == 3'h3; // @[el2_lsu_lsc_ctl.scala 198:45] - wire _T_118 = ~io_lsu_p_fast_int; // @[el2_lsu_lsc_ctl.scala 211:64] + wire dma_pkt_d_bits_load = ~io_dma_mem_write; // @[el2_lsu_lsc_ctl.scala 194:30] + wire dma_pkt_d_bits_by = io_dma_mem_sz == 3'h0; // @[el2_lsu_lsc_ctl.scala 195:50] + wire dma_pkt_d_bits_half = io_dma_mem_sz == 3'h1; // @[el2_lsu_lsc_ctl.scala 196:50] + wire dma_pkt_d_bits_word = io_dma_mem_sz == 3'h2; // @[el2_lsu_lsc_ctl.scala 197:50] + wire dma_pkt_d_bits_dword = io_dma_mem_sz == 3'h3; // @[el2_lsu_lsc_ctl.scala 198:50] + wire _T_118 = ~io_lsu_p_bits_fast_int; // @[el2_lsu_lsc_ctl.scala 211:64] wire _T_119 = io_flush_m_up & _T_118; // @[el2_lsu_lsc_ctl.scala 211:61] wire _T_120 = ~_T_119; // @[el2_lsu_lsc_ctl.scala 211:45] wire _T_121 = io_lsu_p_valid & _T_120; // @[el2_lsu_lsc_ctl.scala 211:43] - wire _T_123 = ~io_lsu_pkt_d_dma; // @[el2_lsu_lsc_ctl.scala 212:68] + wire _T_123 = ~io_lsu_pkt_d_bits_dma; // @[el2_lsu_lsc_ctl.scala 212:68] wire _T_124 = io_flush_m_up & _T_123; // @[el2_lsu_lsc_ctl.scala 212:65] wire _T_125 = ~_T_124; // @[el2_lsu_lsc_ctl.scala 212:49] wire _T_128 = io_flush_m_up & _T_78; // @[el2_lsu_lsc_ctl.scala 213:65] wire _T_129 = ~_T_128; // @[el2_lsu_lsc_ctl.scala 213:49] - reg _T_132_fast_int; // @[el2_lsu_lsc_ctl.scala 215:65] - reg _T_132_by; // @[el2_lsu_lsc_ctl.scala 215:65] - reg _T_132_half; // @[el2_lsu_lsc_ctl.scala 215:65] - reg _T_132_word; // @[el2_lsu_lsc_ctl.scala 215:65] - reg _T_132_dword; // @[el2_lsu_lsc_ctl.scala 215:65] - reg _T_132_load; // @[el2_lsu_lsc_ctl.scala 215:65] - reg _T_132_store; // @[el2_lsu_lsc_ctl.scala 215:65] - reg _T_132_unsign; // @[el2_lsu_lsc_ctl.scala 215:65] - reg _T_132_dma; // @[el2_lsu_lsc_ctl.scala 215:65] - reg _T_132_store_data_bypass_d; // @[el2_lsu_lsc_ctl.scala 215:65] - reg _T_132_load_ldst_bypass_d; // @[el2_lsu_lsc_ctl.scala 215:65] - reg _T_132_store_data_bypass_m; // @[el2_lsu_lsc_ctl.scala 215:65] - reg _T_134_fast_int; // @[el2_lsu_lsc_ctl.scala 216:65] - reg _T_134_by; // @[el2_lsu_lsc_ctl.scala 216:65] - reg _T_134_half; // @[el2_lsu_lsc_ctl.scala 216:65] - reg _T_134_word; // @[el2_lsu_lsc_ctl.scala 216:65] - reg _T_134_dword; // @[el2_lsu_lsc_ctl.scala 216:65] - reg _T_134_load; // @[el2_lsu_lsc_ctl.scala 216:65] - reg _T_134_store; // @[el2_lsu_lsc_ctl.scala 216:65] - reg _T_134_unsign; // @[el2_lsu_lsc_ctl.scala 216:65] - reg _T_134_dma; // @[el2_lsu_lsc_ctl.scala 216:65] - reg _T_134_store_data_bypass_d; // @[el2_lsu_lsc_ctl.scala 216:65] - reg _T_134_load_ldst_bypass_d; // @[el2_lsu_lsc_ctl.scala 216:65] - reg _T_134_store_data_bypass_m; // @[el2_lsu_lsc_ctl.scala 216:65] + reg _T_132_bits_fast_int; // @[el2_lsu_lsc_ctl.scala 215:65] + reg _T_132_bits_by; // @[el2_lsu_lsc_ctl.scala 215:65] + reg _T_132_bits_half; // @[el2_lsu_lsc_ctl.scala 215:65] + reg _T_132_bits_word; // @[el2_lsu_lsc_ctl.scala 215:65] + reg _T_132_bits_dword; // @[el2_lsu_lsc_ctl.scala 215:65] + reg _T_132_bits_load; // @[el2_lsu_lsc_ctl.scala 215:65] + reg _T_132_bits_store; // @[el2_lsu_lsc_ctl.scala 215:65] + reg _T_132_bits_unsign; // @[el2_lsu_lsc_ctl.scala 215:65] + reg _T_132_bits_dma; // @[el2_lsu_lsc_ctl.scala 215:65] + reg _T_132_bits_store_data_bypass_d; // @[el2_lsu_lsc_ctl.scala 215:65] + reg _T_132_bits_load_ldst_bypass_d; // @[el2_lsu_lsc_ctl.scala 215:65] + reg _T_132_bits_store_data_bypass_m; // @[el2_lsu_lsc_ctl.scala 215:65] + reg _T_134_bits_fast_int; // @[el2_lsu_lsc_ctl.scala 216:65] + reg _T_134_bits_by; // @[el2_lsu_lsc_ctl.scala 216:65] + reg _T_134_bits_half; // @[el2_lsu_lsc_ctl.scala 216:65] + reg _T_134_bits_word; // @[el2_lsu_lsc_ctl.scala 216:65] + reg _T_134_bits_dword; // @[el2_lsu_lsc_ctl.scala 216:65] + reg _T_134_bits_load; // @[el2_lsu_lsc_ctl.scala 216:65] + reg _T_134_bits_store; // @[el2_lsu_lsc_ctl.scala 216:65] + reg _T_134_bits_unsign; // @[el2_lsu_lsc_ctl.scala 216:65] + reg _T_134_bits_dma; // @[el2_lsu_lsc_ctl.scala 216:65] + reg _T_134_bits_store_data_bypass_d; // @[el2_lsu_lsc_ctl.scala 216:65] + reg _T_134_bits_load_ldst_bypass_d; // @[el2_lsu_lsc_ctl.scala 216:65] + reg _T_134_bits_store_data_bypass_m; // @[el2_lsu_lsc_ctl.scala 216:65] reg _T_135; // @[el2_lsu_lsc_ctl.scala 217:65] reg _T_136; // @[el2_lsu_lsc_ctl.scala 218:65] wire [5:0] _T_139 = {io_dma_mem_addr[2:0],3'h0}; // @[Cat.scala 29:58] @@ -492,78 +491,78 @@ module el2_lsu_lsc_ctl( reg _T_154; // @[el2_lsu_lsc_ctl.scala 233:62] reg addr_external_r; // @[el2_lsu_lsc_ctl.scala 234:66] reg [31:0] bus_read_data_r; // @[el2_lsu_lsc_ctl.scala 235:66] - wire _T_156 = io_lsu_pkt_r_store | io_lsu_pkt_r_load; // @[el2_lsu_lsc_ctl.scala 241:63] + wire _T_156 = io_lsu_pkt_r_bits_store | io_lsu_pkt_r_bits_load; // @[el2_lsu_lsc_ctl.scala 241:68] wire _T_157 = io_lsu_pkt_r_valid & _T_156; // @[el2_lsu_lsc_ctl.scala 241:41] - wire _T_158 = ~io_flush_r; // @[el2_lsu_lsc_ctl.scala 241:86] - wire _T_159 = _T_157 & _T_158; // @[el2_lsu_lsc_ctl.scala 241:84] - wire _T_160 = ~io_lsu_pkt_r_dma; // @[el2_lsu_lsc_ctl.scala 241:100] + wire _T_158 = ~io_flush_r; // @[el2_lsu_lsc_ctl.scala 241:96] + wire _T_159 = _T_157 & _T_158; // @[el2_lsu_lsc_ctl.scala 241:94] + wire _T_160 = ~io_lsu_pkt_r_bits_dma; // @[el2_lsu_lsc_ctl.scala 241:110] wire _T_163 = ~io_addr_in_pic_m; // @[el2_lsu_lsc_ctl.scala 242:69] wire [31:0] _T_165 = _T_163 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] wire [31:0] _T_166 = io_picm_mask_data_m | _T_165; // @[el2_lsu_lsc_ctl.scala 242:59] - wire [31:0] _T_168 = io_lsu_pkt_m_store_data_bypass_m ? io_lsu_result_m : store_data_pre_m; // @[el2_lsu_lsc_ctl.scala 242:94] + wire [31:0] _T_168 = io_lsu_pkt_m_bits_store_data_bypass_m ? io_lsu_result_m : store_data_pre_m; // @[el2_lsu_lsc_ctl.scala 242:94] wire [31:0] lsu_ld_datafn_m = io_addr_external_m ? io_bus_read_data_m : io_lsu_ld_data_m; // @[el2_lsu_lsc_ctl.scala 263:33] wire [31:0] lsu_ld_datafn_corr_r = addr_external_r ? bus_read_data_r : io_lsu_ld_data_corr_r; // @[el2_lsu_lsc_ctl.scala 264:33] - wire _T_174 = io_lsu_pkt_m_unsign & io_lsu_pkt_m_by; // @[el2_lsu_lsc_ctl.scala 265:61] + wire _T_174 = io_lsu_pkt_m_bits_unsign & io_lsu_pkt_m_bits_by; // @[el2_lsu_lsc_ctl.scala 265:66] wire [31:0] _T_176 = _T_174 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] wire [31:0] _T_178 = {24'h0,lsu_ld_datafn_m[7:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_179 = _T_176 & _T_178; // @[el2_lsu_lsc_ctl.scala 265:84] - wire _T_180 = io_lsu_pkt_m_unsign & io_lsu_pkt_m_half; // @[el2_lsu_lsc_ctl.scala 266:38] + wire [31:0] _T_179 = _T_176 & _T_178; // @[el2_lsu_lsc_ctl.scala 265:94] + wire _T_180 = io_lsu_pkt_m_bits_unsign & io_lsu_pkt_m_bits_half; // @[el2_lsu_lsc_ctl.scala 266:43] wire [31:0] _T_182 = _T_180 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] wire [31:0] _T_184 = {16'h0,lsu_ld_datafn_m[15:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_185 = _T_182 & _T_184; // @[el2_lsu_lsc_ctl.scala 266:61] - wire [31:0] _T_186 = _T_179 | _T_185; // @[el2_lsu_lsc_ctl.scala 265:123] - wire _T_187 = ~io_lsu_pkt_m_unsign; // @[el2_lsu_lsc_ctl.scala 267:17] - wire _T_188 = _T_187 & io_lsu_pkt_m_by; // @[el2_lsu_lsc_ctl.scala 267:38] + wire [31:0] _T_185 = _T_182 & _T_184; // @[el2_lsu_lsc_ctl.scala 266:71] + wire [31:0] _T_186 = _T_179 | _T_185; // @[el2_lsu_lsc_ctl.scala 265:133] + wire _T_187 = ~io_lsu_pkt_m_bits_unsign; // @[el2_lsu_lsc_ctl.scala 267:17] + wire _T_188 = _T_187 & io_lsu_pkt_m_bits_by; // @[el2_lsu_lsc_ctl.scala 267:43] wire [31:0] _T_190 = _T_188 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] wire [23:0] _T_193 = lsu_ld_datafn_m[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12] wire [31:0] _T_195 = {_T_193,lsu_ld_datafn_m[7:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_196 = _T_190 & _T_195; // @[el2_lsu_lsc_ctl.scala 267:61] - wire [31:0] _T_197 = _T_186 | _T_196; // @[el2_lsu_lsc_ctl.scala 266:104] - wire _T_199 = _T_187 & io_lsu_pkt_m_half; // @[el2_lsu_lsc_ctl.scala 268:38] + wire [31:0] _T_196 = _T_190 & _T_195; // @[el2_lsu_lsc_ctl.scala 267:71] + wire [31:0] _T_197 = _T_186 | _T_196; // @[el2_lsu_lsc_ctl.scala 266:114] + wire _T_199 = _T_187 & io_lsu_pkt_m_bits_half; // @[el2_lsu_lsc_ctl.scala 268:43] wire [31:0] _T_201 = _T_199 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] wire [15:0] _T_204 = lsu_ld_datafn_m[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12] wire [31:0] _T_206 = {_T_204,lsu_ld_datafn_m[15:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_207 = _T_201 & _T_206; // @[el2_lsu_lsc_ctl.scala 268:61] - wire [31:0] _T_208 = _T_197 | _T_207; // @[el2_lsu_lsc_ctl.scala 267:124] - wire [31:0] _T_210 = io_lsu_pkt_m_word ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_212 = _T_210 & lsu_ld_datafn_m; // @[el2_lsu_lsc_ctl.scala 269:38] - wire _T_214 = io_lsu_pkt_r_unsign & io_lsu_pkt_r_by; // @[el2_lsu_lsc_ctl.scala 270:61] + wire [31:0] _T_207 = _T_201 & _T_206; // @[el2_lsu_lsc_ctl.scala 268:71] + wire [31:0] _T_208 = _T_197 | _T_207; // @[el2_lsu_lsc_ctl.scala 267:134] + wire [31:0] _T_210 = io_lsu_pkt_m_bits_word ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_212 = _T_210 & lsu_ld_datafn_m; // @[el2_lsu_lsc_ctl.scala 269:43] + wire _T_214 = io_lsu_pkt_r_bits_unsign & io_lsu_pkt_r_bits_by; // @[el2_lsu_lsc_ctl.scala 270:66] wire [31:0] _T_216 = _T_214 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] wire [31:0] _T_218 = {24'h0,lsu_ld_datafn_corr_r[7:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_219 = _T_216 & _T_218; // @[el2_lsu_lsc_ctl.scala 270:84] - wire _T_220 = io_lsu_pkt_r_unsign & io_lsu_pkt_r_half; // @[el2_lsu_lsc_ctl.scala 271:38] + wire [31:0] _T_219 = _T_216 & _T_218; // @[el2_lsu_lsc_ctl.scala 270:94] + wire _T_220 = io_lsu_pkt_r_bits_unsign & io_lsu_pkt_r_bits_half; // @[el2_lsu_lsc_ctl.scala 271:43] wire [31:0] _T_222 = _T_220 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] wire [31:0] _T_224 = {16'h0,lsu_ld_datafn_corr_r[15:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_225 = _T_222 & _T_224; // @[el2_lsu_lsc_ctl.scala 271:61] - wire [31:0] _T_226 = _T_219 | _T_225; // @[el2_lsu_lsc_ctl.scala 270:128] - wire _T_227 = ~io_lsu_pkt_r_unsign; // @[el2_lsu_lsc_ctl.scala 272:17] - wire _T_228 = _T_227 & io_lsu_pkt_r_by; // @[el2_lsu_lsc_ctl.scala 272:38] + wire [31:0] _T_225 = _T_222 & _T_224; // @[el2_lsu_lsc_ctl.scala 271:71] + wire [31:0] _T_226 = _T_219 | _T_225; // @[el2_lsu_lsc_ctl.scala 270:138] + wire _T_227 = ~io_lsu_pkt_r_bits_unsign; // @[el2_lsu_lsc_ctl.scala 272:17] + wire _T_228 = _T_227 & io_lsu_pkt_r_bits_by; // @[el2_lsu_lsc_ctl.scala 272:43] wire [31:0] _T_230 = _T_228 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] wire [23:0] _T_233 = lsu_ld_datafn_corr_r[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12] wire [31:0] _T_235 = {_T_233,lsu_ld_datafn_corr_r[7:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_236 = _T_230 & _T_235; // @[el2_lsu_lsc_ctl.scala 272:61] - wire [31:0] _T_237 = _T_226 | _T_236; // @[el2_lsu_lsc_ctl.scala 271:109] - wire _T_239 = _T_227 & io_lsu_pkt_r_half; // @[el2_lsu_lsc_ctl.scala 273:38] + wire [31:0] _T_236 = _T_230 & _T_235; // @[el2_lsu_lsc_ctl.scala 272:71] + wire [31:0] _T_237 = _T_226 | _T_236; // @[el2_lsu_lsc_ctl.scala 271:119] + wire _T_239 = _T_227 & io_lsu_pkt_r_bits_half; // @[el2_lsu_lsc_ctl.scala 273:43] wire [31:0] _T_241 = _T_239 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] wire [15:0] _T_244 = lsu_ld_datafn_corr_r[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12] wire [31:0] _T_246 = {_T_244,lsu_ld_datafn_corr_r[15:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_247 = _T_241 & _T_246; // @[el2_lsu_lsc_ctl.scala 273:61] - wire [31:0] _T_248 = _T_237 | _T_247; // @[el2_lsu_lsc_ctl.scala 272:134] - wire [31:0] _T_250 = io_lsu_pkt_r_word ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_252 = _T_250 & lsu_ld_datafn_corr_r; // @[el2_lsu_lsc_ctl.scala 274:38] + wire [31:0] _T_247 = _T_241 & _T_246; // @[el2_lsu_lsc_ctl.scala 273:71] + wire [31:0] _T_248 = _T_237 | _T_247; // @[el2_lsu_lsc_ctl.scala 272:144] + wire [31:0] _T_250 = io_lsu_pkt_r_bits_word ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_252 = _T_250 & lsu_ld_datafn_corr_r; // @[el2_lsu_lsc_ctl.scala 274:43] el2_lsu_addrcheck addrcheck ( // @[el2_lsu_lsc_ctl.scala 119:25] .reset(addrcheck_reset), .io_lsu_c2_m_clk(addrcheck_io_lsu_c2_m_clk), .io_start_addr_d(addrcheck_io_start_addr_d), .io_end_addr_d(addrcheck_io_end_addr_d), - .io_lsu_pkt_d_fast_int(addrcheck_io_lsu_pkt_d_fast_int), - .io_lsu_pkt_d_by(addrcheck_io_lsu_pkt_d_by), - .io_lsu_pkt_d_half(addrcheck_io_lsu_pkt_d_half), - .io_lsu_pkt_d_word(addrcheck_io_lsu_pkt_d_word), - .io_lsu_pkt_d_load(addrcheck_io_lsu_pkt_d_load), - .io_lsu_pkt_d_store(addrcheck_io_lsu_pkt_d_store), - .io_lsu_pkt_d_dma(addrcheck_io_lsu_pkt_d_dma), .io_lsu_pkt_d_valid(addrcheck_io_lsu_pkt_d_valid), + .io_lsu_pkt_d_bits_fast_int(addrcheck_io_lsu_pkt_d_bits_fast_int), + .io_lsu_pkt_d_bits_by(addrcheck_io_lsu_pkt_d_bits_by), + .io_lsu_pkt_d_bits_half(addrcheck_io_lsu_pkt_d_bits_half), + .io_lsu_pkt_d_bits_word(addrcheck_io_lsu_pkt_d_bits_word), + .io_lsu_pkt_d_bits_load(addrcheck_io_lsu_pkt_d_bits_load), + .io_lsu_pkt_d_bits_store(addrcheck_io_lsu_pkt_d_bits_store), + .io_lsu_pkt_d_bits_dma(addrcheck_io_lsu_pkt_d_bits_dma), .io_dec_tlu_mrac_ff(addrcheck_io_dec_tlu_mrac_ff), .io_rs1_region_d(addrcheck_io_rs1_region_d), .io_is_sideeffects_m(addrcheck_io_is_sideeffects_m), @@ -604,57 +603,57 @@ module el2_lsu_lsc_ctl( assign io_addr_in_pic_m = _T_152; // @[el2_lsu_lsc_ctl.scala 231:24] assign io_addr_in_pic_r = _T_153; // @[el2_lsu_lsc_ctl.scala 232:24] assign io_addr_external_m = _T_154; // @[el2_lsu_lsc_ctl.scala 233:24] - assign io_lsu_pkt_d_fast_int = io_dec_lsu_valid_raw_d & io_lsu_p_fast_int; // @[el2_lsu_lsc_ctl.scala 207:20] - assign io_lsu_pkt_d_by = io_dec_lsu_valid_raw_d ? io_lsu_p_by : dma_pkt_d_by; // @[el2_lsu_lsc_ctl.scala 207:20] - assign io_lsu_pkt_d_half = io_dec_lsu_valid_raw_d ? io_lsu_p_half : dma_pkt_d_half; // @[el2_lsu_lsc_ctl.scala 207:20] - assign io_lsu_pkt_d_word = io_dec_lsu_valid_raw_d ? io_lsu_p_word : dma_pkt_d_word; // @[el2_lsu_lsc_ctl.scala 207:20] - assign io_lsu_pkt_d_dword = io_dec_lsu_valid_raw_d ? io_lsu_p_dword : dma_pkt_d_dword; // @[el2_lsu_lsc_ctl.scala 207:20] - assign io_lsu_pkt_d_load = io_dec_lsu_valid_raw_d ? io_lsu_p_load : dma_pkt_d_load; // @[el2_lsu_lsc_ctl.scala 207:20] - assign io_lsu_pkt_d_store = io_dec_lsu_valid_raw_d ? io_lsu_p_store : io_dma_mem_write; // @[el2_lsu_lsc_ctl.scala 207:20] - assign io_lsu_pkt_d_unsign = io_dec_lsu_valid_raw_d & io_lsu_p_unsign; // @[el2_lsu_lsc_ctl.scala 207:20] - assign io_lsu_pkt_d_dma = io_dec_lsu_valid_raw_d ? io_lsu_p_dma : 1'h1; // @[el2_lsu_lsc_ctl.scala 207:20] - assign io_lsu_pkt_d_store_data_bypass_d = io_dec_lsu_valid_raw_d & io_lsu_p_store_data_bypass_d; // @[el2_lsu_lsc_ctl.scala 207:20] - assign io_lsu_pkt_d_load_ldst_bypass_d = io_dec_lsu_valid_raw_d & io_lsu_p_load_ldst_bypass_d; // @[el2_lsu_lsc_ctl.scala 207:20] - assign io_lsu_pkt_d_store_data_bypass_m = io_dec_lsu_valid_raw_d & io_lsu_p_store_data_bypass_m; // @[el2_lsu_lsc_ctl.scala 207:20] assign io_lsu_pkt_d_valid = _T_121 | io_dma_dccm_req; // @[el2_lsu_lsc_ctl.scala 207:20 el2_lsu_lsc_ctl.scala 211:24] - assign io_lsu_pkt_m_fast_int = _T_132_fast_int; // @[el2_lsu_lsc_ctl.scala 215:28] - assign io_lsu_pkt_m_by = _T_132_by; // @[el2_lsu_lsc_ctl.scala 215:28] - assign io_lsu_pkt_m_half = _T_132_half; // @[el2_lsu_lsc_ctl.scala 215:28] - assign io_lsu_pkt_m_word = _T_132_word; // @[el2_lsu_lsc_ctl.scala 215:28] - assign io_lsu_pkt_m_dword = _T_132_dword; // @[el2_lsu_lsc_ctl.scala 215:28] - assign io_lsu_pkt_m_load = _T_132_load; // @[el2_lsu_lsc_ctl.scala 215:28] - assign io_lsu_pkt_m_store = _T_132_store; // @[el2_lsu_lsc_ctl.scala 215:28] - assign io_lsu_pkt_m_unsign = _T_132_unsign; // @[el2_lsu_lsc_ctl.scala 215:28] - assign io_lsu_pkt_m_dma = _T_132_dma; // @[el2_lsu_lsc_ctl.scala 215:28] - assign io_lsu_pkt_m_store_data_bypass_d = _T_132_store_data_bypass_d; // @[el2_lsu_lsc_ctl.scala 215:28] - assign io_lsu_pkt_m_load_ldst_bypass_d = _T_132_load_ldst_bypass_d; // @[el2_lsu_lsc_ctl.scala 215:28] - assign io_lsu_pkt_m_store_data_bypass_m = _T_132_store_data_bypass_m; // @[el2_lsu_lsc_ctl.scala 215:28] + assign io_lsu_pkt_d_bits_fast_int = io_dec_lsu_valid_raw_d & io_lsu_p_bits_fast_int; // @[el2_lsu_lsc_ctl.scala 207:20] + assign io_lsu_pkt_d_bits_by = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_by : dma_pkt_d_bits_by; // @[el2_lsu_lsc_ctl.scala 207:20] + assign io_lsu_pkt_d_bits_half = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_half : dma_pkt_d_bits_half; // @[el2_lsu_lsc_ctl.scala 207:20] + assign io_lsu_pkt_d_bits_word = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_word : dma_pkt_d_bits_word; // @[el2_lsu_lsc_ctl.scala 207:20] + assign io_lsu_pkt_d_bits_dword = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_dword : dma_pkt_d_bits_dword; // @[el2_lsu_lsc_ctl.scala 207:20] + assign io_lsu_pkt_d_bits_load = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_load : dma_pkt_d_bits_load; // @[el2_lsu_lsc_ctl.scala 207:20] + assign io_lsu_pkt_d_bits_store = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_store : io_dma_mem_write; // @[el2_lsu_lsc_ctl.scala 207:20] + assign io_lsu_pkt_d_bits_unsign = io_dec_lsu_valid_raw_d & io_lsu_p_bits_unsign; // @[el2_lsu_lsc_ctl.scala 207:20] + assign io_lsu_pkt_d_bits_dma = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_dma : 1'h1; // @[el2_lsu_lsc_ctl.scala 207:20] + assign io_lsu_pkt_d_bits_store_data_bypass_d = io_dec_lsu_valid_raw_d & io_lsu_p_bits_store_data_bypass_d; // @[el2_lsu_lsc_ctl.scala 207:20] + assign io_lsu_pkt_d_bits_load_ldst_bypass_d = io_dec_lsu_valid_raw_d & io_lsu_p_bits_load_ldst_bypass_d; // @[el2_lsu_lsc_ctl.scala 207:20] + assign io_lsu_pkt_d_bits_store_data_bypass_m = io_dec_lsu_valid_raw_d & io_lsu_p_bits_store_data_bypass_m; // @[el2_lsu_lsc_ctl.scala 207:20] assign io_lsu_pkt_m_valid = _T_135; // @[el2_lsu_lsc_ctl.scala 215:28 el2_lsu_lsc_ctl.scala 217:28] - assign io_lsu_pkt_r_fast_int = _T_134_fast_int; // @[el2_lsu_lsc_ctl.scala 216:28] - assign io_lsu_pkt_r_by = _T_134_by; // @[el2_lsu_lsc_ctl.scala 216:28] - assign io_lsu_pkt_r_half = _T_134_half; // @[el2_lsu_lsc_ctl.scala 216:28] - assign io_lsu_pkt_r_word = _T_134_word; // @[el2_lsu_lsc_ctl.scala 216:28] - assign io_lsu_pkt_r_dword = _T_134_dword; // @[el2_lsu_lsc_ctl.scala 216:28] - assign io_lsu_pkt_r_load = _T_134_load; // @[el2_lsu_lsc_ctl.scala 216:28] - assign io_lsu_pkt_r_store = _T_134_store; // @[el2_lsu_lsc_ctl.scala 216:28] - assign io_lsu_pkt_r_unsign = _T_134_unsign; // @[el2_lsu_lsc_ctl.scala 216:28] - assign io_lsu_pkt_r_dma = _T_134_dma; // @[el2_lsu_lsc_ctl.scala 216:28] - assign io_lsu_pkt_r_store_data_bypass_d = _T_134_store_data_bypass_d; // @[el2_lsu_lsc_ctl.scala 216:28] - assign io_lsu_pkt_r_load_ldst_bypass_d = _T_134_load_ldst_bypass_d; // @[el2_lsu_lsc_ctl.scala 216:28] - assign io_lsu_pkt_r_store_data_bypass_m = _T_134_store_data_bypass_m; // @[el2_lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_m_bits_fast_int = _T_132_bits_fast_int; // @[el2_lsu_lsc_ctl.scala 215:28] + assign io_lsu_pkt_m_bits_by = _T_132_bits_by; // @[el2_lsu_lsc_ctl.scala 215:28] + assign io_lsu_pkt_m_bits_half = _T_132_bits_half; // @[el2_lsu_lsc_ctl.scala 215:28] + assign io_lsu_pkt_m_bits_word = _T_132_bits_word; // @[el2_lsu_lsc_ctl.scala 215:28] + assign io_lsu_pkt_m_bits_dword = _T_132_bits_dword; // @[el2_lsu_lsc_ctl.scala 215:28] + assign io_lsu_pkt_m_bits_load = _T_132_bits_load; // @[el2_lsu_lsc_ctl.scala 215:28] + assign io_lsu_pkt_m_bits_store = _T_132_bits_store; // @[el2_lsu_lsc_ctl.scala 215:28] + assign io_lsu_pkt_m_bits_unsign = _T_132_bits_unsign; // @[el2_lsu_lsc_ctl.scala 215:28] + assign io_lsu_pkt_m_bits_dma = _T_132_bits_dma; // @[el2_lsu_lsc_ctl.scala 215:28] + assign io_lsu_pkt_m_bits_store_data_bypass_d = _T_132_bits_store_data_bypass_d; // @[el2_lsu_lsc_ctl.scala 215:28] + assign io_lsu_pkt_m_bits_load_ldst_bypass_d = _T_132_bits_load_ldst_bypass_d; // @[el2_lsu_lsc_ctl.scala 215:28] + assign io_lsu_pkt_m_bits_store_data_bypass_m = _T_132_bits_store_data_bypass_m; // @[el2_lsu_lsc_ctl.scala 215:28] assign io_lsu_pkt_r_valid = _T_136; // @[el2_lsu_lsc_ctl.scala 216:28 el2_lsu_lsc_ctl.scala 218:28] + assign io_lsu_pkt_r_bits_fast_int = _T_134_bits_fast_int; // @[el2_lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_r_bits_by = _T_134_bits_by; // @[el2_lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_r_bits_half = _T_134_bits_half; // @[el2_lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_r_bits_word = _T_134_bits_word; // @[el2_lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_r_bits_dword = _T_134_bits_dword; // @[el2_lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_r_bits_load = _T_134_bits_load; // @[el2_lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_r_bits_store = _T_134_bits_store; // @[el2_lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_r_bits_unsign = _T_134_bits_unsign; // @[el2_lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_r_bits_dma = _T_134_bits_dma; // @[el2_lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_r_bits_store_data_bypass_d = _T_134_bits_store_data_bypass_d; // @[el2_lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_r_bits_load_ldst_bypass_d = _T_134_bits_load_ldst_bypass_d; // @[el2_lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_r_bits_store_data_bypass_m = _T_134_bits_store_data_bypass_m; // @[el2_lsu_lsc_ctl.scala 216:28] assign addrcheck_reset = reset; assign addrcheck_io_lsu_c2_m_clk = io_lsu_c2_m_clk; // @[el2_lsu_lsc_ctl.scala 121:42] assign addrcheck_io_start_addr_d = {_T_40,_T_10[11:0]}; // @[el2_lsu_lsc_ctl.scala 123:42] assign addrcheck_io_end_addr_d = rs1_d + _T_64; // @[el2_lsu_lsc_ctl.scala 124:42] - assign addrcheck_io_lsu_pkt_d_fast_int = io_lsu_pkt_d_fast_int; // @[el2_lsu_lsc_ctl.scala 125:42] - assign addrcheck_io_lsu_pkt_d_by = io_lsu_pkt_d_by; // @[el2_lsu_lsc_ctl.scala 125:42] - assign addrcheck_io_lsu_pkt_d_half = io_lsu_pkt_d_half; // @[el2_lsu_lsc_ctl.scala 125:42] - assign addrcheck_io_lsu_pkt_d_word = io_lsu_pkt_d_word; // @[el2_lsu_lsc_ctl.scala 125:42] - assign addrcheck_io_lsu_pkt_d_load = io_lsu_pkt_d_load; // @[el2_lsu_lsc_ctl.scala 125:42] - assign addrcheck_io_lsu_pkt_d_store = io_lsu_pkt_d_store; // @[el2_lsu_lsc_ctl.scala 125:42] - assign addrcheck_io_lsu_pkt_d_dma = io_lsu_pkt_d_dma; // @[el2_lsu_lsc_ctl.scala 125:42] assign addrcheck_io_lsu_pkt_d_valid = io_lsu_pkt_d_valid; // @[el2_lsu_lsc_ctl.scala 125:42] + assign addrcheck_io_lsu_pkt_d_bits_fast_int = io_lsu_pkt_d_bits_fast_int; // @[el2_lsu_lsc_ctl.scala 125:42] + assign addrcheck_io_lsu_pkt_d_bits_by = io_lsu_pkt_d_bits_by; // @[el2_lsu_lsc_ctl.scala 125:42] + assign addrcheck_io_lsu_pkt_d_bits_half = io_lsu_pkt_d_bits_half; // @[el2_lsu_lsc_ctl.scala 125:42] + assign addrcheck_io_lsu_pkt_d_bits_word = io_lsu_pkt_d_bits_word; // @[el2_lsu_lsc_ctl.scala 125:42] + assign addrcheck_io_lsu_pkt_d_bits_load = io_lsu_pkt_d_bits_load; // @[el2_lsu_lsc_ctl.scala 125:42] + assign addrcheck_io_lsu_pkt_d_bits_store = io_lsu_pkt_d_bits_store; // @[el2_lsu_lsc_ctl.scala 125:42] + assign addrcheck_io_lsu_pkt_d_bits_dma = io_lsu_pkt_d_bits_dma; // @[el2_lsu_lsc_ctl.scala 125:42] assign addrcheck_io_dec_tlu_mrac_ff = io_dec_tlu_mrac_ff; // @[el2_lsu_lsc_ctl.scala 126:42] assign addrcheck_io_rs1_region_d = rs1_d[31:28]; // @[el2_lsu_lsc_ctl.scala 127:42] `ifdef RANDOMIZE_GARBAGE_ASSIGN @@ -711,59 +710,59 @@ initial begin _RAND_8 = {1{`RANDOM}}; _T_105_bits_exc_type = _RAND_8[0:0]; _RAND_9 = {1{`RANDOM}}; - _T_105_bits_mscause = _RAND_9[0:0]; + _T_105_bits_mscause = _RAND_9[3:0]; _RAND_10 = {1{`RANDOM}}; - _T_105_bits_addr = _RAND_10[0:0]; + _T_105_bits_addr = _RAND_10[31:0]; _RAND_11 = {1{`RANDOM}}; _T_106 = _RAND_11[1:0]; _RAND_12 = {1{`RANDOM}}; - _T_132_fast_int = _RAND_12[0:0]; + _T_132_bits_fast_int = _RAND_12[0:0]; _RAND_13 = {1{`RANDOM}}; - _T_132_by = _RAND_13[0:0]; + _T_132_bits_by = _RAND_13[0:0]; _RAND_14 = {1{`RANDOM}}; - _T_132_half = _RAND_14[0:0]; + _T_132_bits_half = _RAND_14[0:0]; _RAND_15 = {1{`RANDOM}}; - _T_132_word = _RAND_15[0:0]; + _T_132_bits_word = _RAND_15[0:0]; _RAND_16 = {1{`RANDOM}}; - _T_132_dword = _RAND_16[0:0]; + _T_132_bits_dword = _RAND_16[0:0]; _RAND_17 = {1{`RANDOM}}; - _T_132_load = _RAND_17[0:0]; + _T_132_bits_load = _RAND_17[0:0]; _RAND_18 = {1{`RANDOM}}; - _T_132_store = _RAND_18[0:0]; + _T_132_bits_store = _RAND_18[0:0]; _RAND_19 = {1{`RANDOM}}; - _T_132_unsign = _RAND_19[0:0]; + _T_132_bits_unsign = _RAND_19[0:0]; _RAND_20 = {1{`RANDOM}}; - _T_132_dma = _RAND_20[0:0]; + _T_132_bits_dma = _RAND_20[0:0]; _RAND_21 = {1{`RANDOM}}; - _T_132_store_data_bypass_d = _RAND_21[0:0]; + _T_132_bits_store_data_bypass_d = _RAND_21[0:0]; _RAND_22 = {1{`RANDOM}}; - _T_132_load_ldst_bypass_d = _RAND_22[0:0]; + _T_132_bits_load_ldst_bypass_d = _RAND_22[0:0]; _RAND_23 = {1{`RANDOM}}; - _T_132_store_data_bypass_m = _RAND_23[0:0]; + _T_132_bits_store_data_bypass_m = _RAND_23[0:0]; _RAND_24 = {1{`RANDOM}}; - _T_134_fast_int = _RAND_24[0:0]; + _T_134_bits_fast_int = _RAND_24[0:0]; _RAND_25 = {1{`RANDOM}}; - _T_134_by = _RAND_25[0:0]; + _T_134_bits_by = _RAND_25[0:0]; _RAND_26 = {1{`RANDOM}}; - _T_134_half = _RAND_26[0:0]; + _T_134_bits_half = _RAND_26[0:0]; _RAND_27 = {1{`RANDOM}}; - _T_134_word = _RAND_27[0:0]; + _T_134_bits_word = _RAND_27[0:0]; _RAND_28 = {1{`RANDOM}}; - _T_134_dword = _RAND_28[0:0]; + _T_134_bits_dword = _RAND_28[0:0]; _RAND_29 = {1{`RANDOM}}; - _T_134_load = _RAND_29[0:0]; + _T_134_bits_load = _RAND_29[0:0]; _RAND_30 = {1{`RANDOM}}; - _T_134_store = _RAND_30[0:0]; + _T_134_bits_store = _RAND_30[0:0]; _RAND_31 = {1{`RANDOM}}; - _T_134_unsign = _RAND_31[0:0]; + _T_134_bits_unsign = _RAND_31[0:0]; _RAND_32 = {1{`RANDOM}}; - _T_134_dma = _RAND_32[0:0]; + _T_134_bits_dma = _RAND_32[0:0]; _RAND_33 = {1{`RANDOM}}; - _T_134_store_data_bypass_d = _RAND_33[0:0]; + _T_134_bits_store_data_bypass_d = _RAND_33[0:0]; _RAND_34 = {1{`RANDOM}}; - _T_134_load_ldst_bypass_d = _RAND_34[0:0]; + _T_134_bits_load_ldst_bypass_d = _RAND_34[0:0]; _RAND_35 = {1{`RANDOM}}; - _T_134_store_data_bypass_m = _RAND_35[0:0]; + _T_134_bits_store_data_bypass_m = _RAND_35[0:0]; _RAND_36 = {1{`RANDOM}}; _T_135 = _RAND_36[0:0]; _RAND_37 = {1{`RANDOM}}; @@ -821,85 +820,85 @@ initial begin _T_105_bits_exc_type = 1'h0; end if (reset) begin - _T_105_bits_mscause = 1'h0; + _T_105_bits_mscause = 4'h0; end if (reset) begin - _T_105_bits_addr = 1'h0; + _T_105_bits_addr = 32'h0; end if (reset) begin _T_106 = 2'h0; end if (reset) begin - _T_132_fast_int = 1'h0; + _T_132_bits_fast_int = 1'h0; end if (reset) begin - _T_132_by = 1'h0; + _T_132_bits_by = 1'h0; end if (reset) begin - _T_132_half = 1'h0; + _T_132_bits_half = 1'h0; end if (reset) begin - _T_132_word = 1'h0; + _T_132_bits_word = 1'h0; end if (reset) begin - _T_132_dword = 1'h0; + _T_132_bits_dword = 1'h0; end if (reset) begin - _T_132_load = 1'h0; + _T_132_bits_load = 1'h0; end if (reset) begin - _T_132_store = 1'h0; + _T_132_bits_store = 1'h0; end if (reset) begin - _T_132_unsign = 1'h0; + _T_132_bits_unsign = 1'h0; end if (reset) begin - _T_132_dma = 1'h0; + _T_132_bits_dma = 1'h0; end if (reset) begin - _T_132_store_data_bypass_d = 1'h0; + _T_132_bits_store_data_bypass_d = 1'h0; end if (reset) begin - _T_132_load_ldst_bypass_d = 1'h0; + _T_132_bits_load_ldst_bypass_d = 1'h0; end if (reset) begin - _T_132_store_data_bypass_m = 1'h0; + _T_132_bits_store_data_bypass_m = 1'h0; end if (reset) begin - _T_134_fast_int = 1'h0; + _T_134_bits_fast_int = 1'h0; end if (reset) begin - _T_134_by = 1'h0; + _T_134_bits_by = 1'h0; end if (reset) begin - _T_134_half = 1'h0; + _T_134_bits_half = 1'h0; end if (reset) begin - _T_134_word = 1'h0; + _T_134_bits_word = 1'h0; end if (reset) begin - _T_134_dword = 1'h0; + _T_134_bits_dword = 1'h0; end if (reset) begin - _T_134_load = 1'h0; + _T_134_bits_load = 1'h0; end if (reset) begin - _T_134_store = 1'h0; + _T_134_bits_store = 1'h0; end if (reset) begin - _T_134_unsign = 1'h0; + _T_134_bits_unsign = 1'h0; end if (reset) begin - _T_134_dma = 1'h0; + _T_134_bits_dma = 1'h0; end if (reset) begin - _T_134_store_data_bypass_d = 1'h0; + _T_134_bits_store_data_bypass_d = 1'h0; end if (reset) begin - _T_134_load_ldst_bypass_d = 1'h0; + _T_134_bits_load_ldst_bypass_d = 1'h0; end if (reset) begin - _T_134_store_data_bypass_m = 1'h0; + _T_134_bits_store_data_bypass_m = 1'h0; end if (reset) begin _T_135 = 1'h0; @@ -1002,7 +1001,7 @@ end // initial if (reset) begin _T_105_bits_inst_type <= 1'h0; end else begin - _T_105_bits_inst_type <= io_lsu_pkt_m_store; + _T_105_bits_inst_type <= io_lsu_pkt_m_bits_store; end end always @(posedge io_lsu_c2_r_clk or posedge reset) begin @@ -1014,16 +1013,18 @@ end // initial end always @(posedge io_lsu_c2_r_clk or posedge reset) begin if (reset) begin - _T_105_bits_mscause <= 1'h0; + _T_105_bits_mscause <= 4'h0; + end else if (_T_92) begin + _T_105_bits_mscause <= 4'h1; end else begin - _T_105_bits_mscause <= _T_95[0]; + _T_105_bits_mscause <= exc_mscause_m; end end always @(posedge io_lsu_c2_r_clk or posedge reset) begin if (reset) begin - _T_105_bits_addr <= 1'h0; + _T_105_bits_addr <= 32'h0; end else begin - _T_105_bits_addr <= io_lsu_addr_m[0]; + _T_105_bits_addr <= io_lsu_addr_m; end end always @(posedge io_lsu_c2_r_clk or posedge reset) begin @@ -1041,170 +1042,170 @@ end // initial end always @(posedge io_lsu_c1_m_clk or posedge reset) begin if (reset) begin - _T_132_fast_int <= 1'h0; + _T_132_bits_fast_int <= 1'h0; end else begin - _T_132_fast_int <= io_lsu_pkt_d_fast_int; + _T_132_bits_fast_int <= io_lsu_pkt_d_bits_fast_int; end end always @(posedge io_lsu_c1_m_clk or posedge reset) begin if (reset) begin - _T_132_by <= 1'h0; + _T_132_bits_by <= 1'h0; end else begin - _T_132_by <= io_lsu_pkt_d_by; + _T_132_bits_by <= io_lsu_pkt_d_bits_by; end end always @(posedge io_lsu_c1_m_clk or posedge reset) begin if (reset) begin - _T_132_half <= 1'h0; + _T_132_bits_half <= 1'h0; end else begin - _T_132_half <= io_lsu_pkt_d_half; + _T_132_bits_half <= io_lsu_pkt_d_bits_half; end end always @(posedge io_lsu_c1_m_clk or posedge reset) begin if (reset) begin - _T_132_word <= 1'h0; + _T_132_bits_word <= 1'h0; end else begin - _T_132_word <= io_lsu_pkt_d_word; + _T_132_bits_word <= io_lsu_pkt_d_bits_word; end end always @(posedge io_lsu_c1_m_clk or posedge reset) begin if (reset) begin - _T_132_dword <= 1'h0; + _T_132_bits_dword <= 1'h0; end else begin - _T_132_dword <= io_lsu_pkt_d_dword; + _T_132_bits_dword <= io_lsu_pkt_d_bits_dword; end end always @(posedge io_lsu_c1_m_clk or posedge reset) begin if (reset) begin - _T_132_load <= 1'h0; + _T_132_bits_load <= 1'h0; end else begin - _T_132_load <= io_lsu_pkt_d_load; + _T_132_bits_load <= io_lsu_pkt_d_bits_load; end end always @(posedge io_lsu_c1_m_clk or posedge reset) begin if (reset) begin - _T_132_store <= 1'h0; + _T_132_bits_store <= 1'h0; end else begin - _T_132_store <= io_lsu_pkt_d_store; + _T_132_bits_store <= io_lsu_pkt_d_bits_store; end end always @(posedge io_lsu_c1_m_clk or posedge reset) begin if (reset) begin - _T_132_unsign <= 1'h0; + _T_132_bits_unsign <= 1'h0; end else begin - _T_132_unsign <= io_lsu_pkt_d_unsign; + _T_132_bits_unsign <= io_lsu_pkt_d_bits_unsign; end end always @(posedge io_lsu_c1_m_clk or posedge reset) begin if (reset) begin - _T_132_dma <= 1'h0; + _T_132_bits_dma <= 1'h0; end else begin - _T_132_dma <= io_lsu_pkt_d_dma; + _T_132_bits_dma <= io_lsu_pkt_d_bits_dma; end end always @(posedge io_lsu_c1_m_clk or posedge reset) begin if (reset) begin - _T_132_store_data_bypass_d <= 1'h0; + _T_132_bits_store_data_bypass_d <= 1'h0; end else begin - _T_132_store_data_bypass_d <= io_lsu_pkt_d_store_data_bypass_d; + _T_132_bits_store_data_bypass_d <= io_lsu_pkt_d_bits_store_data_bypass_d; end end always @(posedge io_lsu_c1_m_clk or posedge reset) begin if (reset) begin - _T_132_load_ldst_bypass_d <= 1'h0; + _T_132_bits_load_ldst_bypass_d <= 1'h0; end else begin - _T_132_load_ldst_bypass_d <= io_lsu_pkt_d_load_ldst_bypass_d; + _T_132_bits_load_ldst_bypass_d <= io_lsu_pkt_d_bits_load_ldst_bypass_d; end end always @(posedge io_lsu_c1_m_clk or posedge reset) begin if (reset) begin - _T_132_store_data_bypass_m <= 1'h0; + _T_132_bits_store_data_bypass_m <= 1'h0; end else begin - _T_132_store_data_bypass_m <= io_lsu_pkt_d_store_data_bypass_m; + _T_132_bits_store_data_bypass_m <= io_lsu_pkt_d_bits_store_data_bypass_m; end end always @(posedge io_lsu_c1_r_clk or posedge reset) begin if (reset) begin - _T_134_fast_int <= 1'h0; + _T_134_bits_fast_int <= 1'h0; end else begin - _T_134_fast_int <= io_lsu_pkt_m_fast_int; + _T_134_bits_fast_int <= io_lsu_pkt_m_bits_fast_int; end end always @(posedge io_lsu_c1_r_clk or posedge reset) begin if (reset) begin - _T_134_by <= 1'h0; + _T_134_bits_by <= 1'h0; end else begin - _T_134_by <= io_lsu_pkt_m_by; + _T_134_bits_by <= io_lsu_pkt_m_bits_by; end end always @(posedge io_lsu_c1_r_clk or posedge reset) begin if (reset) begin - _T_134_half <= 1'h0; + _T_134_bits_half <= 1'h0; end else begin - _T_134_half <= io_lsu_pkt_m_half; + _T_134_bits_half <= io_lsu_pkt_m_bits_half; end end always @(posedge io_lsu_c1_r_clk or posedge reset) begin if (reset) begin - _T_134_word <= 1'h0; + _T_134_bits_word <= 1'h0; end else begin - _T_134_word <= io_lsu_pkt_m_word; + _T_134_bits_word <= io_lsu_pkt_m_bits_word; end end always @(posedge io_lsu_c1_r_clk or posedge reset) begin if (reset) begin - _T_134_dword <= 1'h0; + _T_134_bits_dword <= 1'h0; end else begin - _T_134_dword <= io_lsu_pkt_m_dword; + _T_134_bits_dword <= io_lsu_pkt_m_bits_dword; end end always @(posedge io_lsu_c1_r_clk or posedge reset) begin if (reset) begin - _T_134_load <= 1'h0; + _T_134_bits_load <= 1'h0; end else begin - _T_134_load <= io_lsu_pkt_m_load; + _T_134_bits_load <= io_lsu_pkt_m_bits_load; end end always @(posedge io_lsu_c1_r_clk or posedge reset) begin if (reset) begin - _T_134_store <= 1'h0; + _T_134_bits_store <= 1'h0; end else begin - _T_134_store <= io_lsu_pkt_m_store; + _T_134_bits_store <= io_lsu_pkt_m_bits_store; end end always @(posedge io_lsu_c1_r_clk or posedge reset) begin if (reset) begin - _T_134_unsign <= 1'h0; + _T_134_bits_unsign <= 1'h0; end else begin - _T_134_unsign <= io_lsu_pkt_m_unsign; + _T_134_bits_unsign <= io_lsu_pkt_m_bits_unsign; end end always @(posedge io_lsu_c1_r_clk or posedge reset) begin if (reset) begin - _T_134_dma <= 1'h0; + _T_134_bits_dma <= 1'h0; end else begin - _T_134_dma <= io_lsu_pkt_m_dma; + _T_134_bits_dma <= io_lsu_pkt_m_bits_dma; end end always @(posedge io_lsu_c1_r_clk or posedge reset) begin if (reset) begin - _T_134_store_data_bypass_d <= 1'h0; + _T_134_bits_store_data_bypass_d <= 1'h0; end else begin - _T_134_store_data_bypass_d <= io_lsu_pkt_m_store_data_bypass_d; + _T_134_bits_store_data_bypass_d <= io_lsu_pkt_m_bits_store_data_bypass_d; end end always @(posedge io_lsu_c1_r_clk or posedge reset) begin if (reset) begin - _T_134_load_ldst_bypass_d <= 1'h0; + _T_134_bits_load_ldst_bypass_d <= 1'h0; end else begin - _T_134_load_ldst_bypass_d <= io_lsu_pkt_m_load_ldst_bypass_d; + _T_134_bits_load_ldst_bypass_d <= io_lsu_pkt_m_bits_load_ldst_bypass_d; end end always @(posedge io_lsu_c1_r_clk or posedge reset) begin if (reset) begin - _T_134_store_data_bypass_m <= 1'h0; + _T_134_bits_store_data_bypass_m <= 1'h0; end else begin - _T_134_store_data_bypass_m <= io_lsu_pkt_m_store_data_bypass_m; + _T_134_bits_store_data_bypass_m <= io_lsu_pkt_m_bits_store_data_bypass_m; end end always @(posedge io_lsu_c2_m_clk or posedge reset) begin @@ -1224,7 +1225,7 @@ end // initial always @(posedge io_lsu_store_c1_m_clk or posedge reset) begin if (reset) begin store_data_pre_m <= 32'h0; - end else if (io_lsu_pkt_d_store_data_bypass_d) begin + end else if (io_lsu_pkt_d_bits_store_data_bypass_d) begin store_data_pre_m <= io_lsu_result_m; end else if (io_dma_dccm_req) begin store_data_pre_m <= dma_mem_wdata_shifted[31:0]; diff --git a/el2_lsu_stbuf.anno.json b/el2_lsu_stbuf.anno.json index cca7506f..d4b191a3 100644 --- a/el2_lsu_stbuf.anno.json +++ b/el2_lsu_stbuf.anno.json @@ -1,22 +1,4 @@ [ - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_lsu_stbuf|el2_lsu_stbuf>io_stbuf_fwdbyteen_hi_m", - "sources":[ - "~el2_lsu_stbuf|el2_lsu_stbuf>io_addr_in_dccm_m", - "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_store", - "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_dma", - "~el2_lsu_stbuf|el2_lsu_stbuf>io_store_stbuf_reqvld_r", - "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_valid", - "~el2_lsu_stbuf|el2_lsu_stbuf>io_end_addr_m", - "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_addr_r", - "~el2_lsu_stbuf|el2_lsu_stbuf>io_end_addr_r", - "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_dword", - "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_word", - "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_by", - "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_half" - ] - }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_stbuf_full_any", @@ -25,25 +7,13 @@ "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_addr_d", "~el2_lsu_stbuf|el2_lsu_stbuf>io_end_addr_d", "~el2_lsu_stbuf|el2_lsu_stbuf>io_addr_in_dccm_r", - "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_dma", + "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_bits_dma", "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_valid", - "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_store", + "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_bits_store", "~el2_lsu_stbuf|el2_lsu_stbuf>io_addr_in_dccm_m", - "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_m_dma", + "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_m_bits_dma", "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_m_valid", - "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_m_store" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_lsu_stbuf|el2_lsu_stbuf>io_stbuf_reqvld_any", - "sources":[ - "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_m_store", - "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_m_dma", - "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_m_valid", - "~el2_lsu_stbuf|el2_lsu_stbuf>io_addr_in_dccm_m", - "~el2_lsu_stbuf|el2_lsu_stbuf>io_end_addr_m", - "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_addr_m" + "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_m_bits_store" ] }, { @@ -54,6 +24,36 @@ "~el2_lsu_stbuf|el2_lsu_stbuf>io_store_stbuf_reqvld_r" ] }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_lsu_stbuf|el2_lsu_stbuf>io_stbuf_reqvld_any", + "sources":[ + "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_m_bits_store", + "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_m_bits_dma", + "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_m_valid", + "~el2_lsu_stbuf|el2_lsu_stbuf>io_addr_in_dccm_m", + "~el2_lsu_stbuf|el2_lsu_stbuf>io_end_addr_m", + "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_addr_m" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_lsu_stbuf|el2_lsu_stbuf>io_stbuf_fwdbyteen_hi_m", + "sources":[ + "~el2_lsu_stbuf|el2_lsu_stbuf>io_addr_in_dccm_m", + "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_bits_store", + "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_bits_dma", + "~el2_lsu_stbuf|el2_lsu_stbuf>io_store_stbuf_reqvld_r", + "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_valid", + "~el2_lsu_stbuf|el2_lsu_stbuf>io_end_addr_m", + "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_addr_r", + "~el2_lsu_stbuf|el2_lsu_stbuf>io_end_addr_r", + "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_bits_dword", + "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_bits_word", + "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_bits_by", + "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_bits_half" + ] + }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_lsu_stbuf|el2_lsu_stbuf>io_stbuf_fwddata_lo_m", @@ -61,17 +61,35 @@ "~el2_lsu_stbuf|el2_lsu_stbuf>io_store_data_lo_r", "~el2_lsu_stbuf|el2_lsu_stbuf>io_store_data_hi_r", "~el2_lsu_stbuf|el2_lsu_stbuf>io_addr_in_dccm_m", - "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_store", - "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_dma", + "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_bits_store", + "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_bits_dma", "~el2_lsu_stbuf|el2_lsu_stbuf>io_store_stbuf_reqvld_r", "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_valid", "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_addr_m", "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_addr_r", "~el2_lsu_stbuf|el2_lsu_stbuf>io_end_addr_r", - "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_dword", - "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_word", - "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_by", - "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_half" + "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_bits_dword", + "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_bits_word", + "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_bits_by", + "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_bits_half" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_lsu_stbuf|el2_lsu_stbuf>io_stbuf_fwdbyteen_lo_m", + "sources":[ + "~el2_lsu_stbuf|el2_lsu_stbuf>io_addr_in_dccm_m", + "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_bits_store", + "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_bits_dma", + "~el2_lsu_stbuf|el2_lsu_stbuf>io_store_stbuf_reqvld_r", + "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_valid", + "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_addr_m", + "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_addr_r", + "~el2_lsu_stbuf|el2_lsu_stbuf>io_end_addr_r", + "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_bits_dword", + "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_bits_word", + "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_bits_by", + "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_bits_half" ] }, { @@ -81,35 +99,17 @@ "~el2_lsu_stbuf|el2_lsu_stbuf>io_store_data_lo_r", "~el2_lsu_stbuf|el2_lsu_stbuf>io_store_data_hi_r", "~el2_lsu_stbuf|el2_lsu_stbuf>io_addr_in_dccm_m", - "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_store", - "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_dma", + "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_bits_store", + "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_bits_dma", "~el2_lsu_stbuf|el2_lsu_stbuf>io_store_stbuf_reqvld_r", "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_valid", "~el2_lsu_stbuf|el2_lsu_stbuf>io_end_addr_m", "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_addr_r", "~el2_lsu_stbuf|el2_lsu_stbuf>io_end_addr_r", - "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_dword", - "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_word", - "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_by", - "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_half" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_lsu_stbuf|el2_lsu_stbuf>io_stbuf_fwdbyteen_lo_m", - "sources":[ - "~el2_lsu_stbuf|el2_lsu_stbuf>io_addr_in_dccm_m", - "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_store", - "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_dma", - "~el2_lsu_stbuf|el2_lsu_stbuf>io_store_stbuf_reqvld_r", - "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_valid", - "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_addr_m", - "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_addr_r", - "~el2_lsu_stbuf|el2_lsu_stbuf>io_end_addr_r", - "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_dword", - "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_word", - "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_by", - "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_half" + "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_bits_dword", + "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_bits_word", + "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_bits_by", + "~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_bits_half" ] }, { @@ -118,8 +118,8 @@ }, { "class":"firrtl.transforms.BlackBoxResourceAnno", - "target":"el2_lsu_stbuf.TEC_RV_ICG", - "resourceId":"/vsrc/TEC_RV_ICG.v" + "target":"el2_lsu_stbuf.gated_latch", + "resourceId":"/vsrc/gated_latch.v" }, { "class":"firrtl.options.TargetDirAnnotation", diff --git a/el2_lsu_stbuf.fir b/el2_lsu_stbuf.fir index 2b5fc9b0..46584b35 100644 --- a/el2_lsu_stbuf.fir +++ b/el2_lsu_stbuf.fir @@ -1,12 +1,12 @@ ;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 circuit el2_lsu_stbuf : - extmodule TEC_RV_ICG : + extmodule gated_latch : output Q : Clock input CK : Clock input EN : UInt<1> input SE : UInt<1> - defname = TEC_RV_ICG + defname = gated_latch module rvclkhdr : @@ -14,23 +14,23 @@ circuit el2_lsu_stbuf : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of TEC_RV_ICG @[beh_lib.scala 332:24] + inst clkhdr of gated_latch @[el2_lib.scala 474:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12] - clkhdr.CK <= io.clk @[beh_lib.scala 334:16] - clkhdr.EN <= io.en @[beh_lib.scala 335:16] - clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16] + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] - extmodule TEC_RV_ICG_1 : + extmodule gated_latch_1 : output Q : Clock input CK : Clock input EN : UInt<1> input SE : UInt<1> - defname = TEC_RV_ICG + defname = gated_latch module rvclkhdr_1 : @@ -38,23 +38,23 @@ circuit el2_lsu_stbuf : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of TEC_RV_ICG_1 @[beh_lib.scala 332:24] + inst clkhdr of gated_latch_1 @[el2_lib.scala 474:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12] - clkhdr.CK <= io.clk @[beh_lib.scala 334:16] - clkhdr.EN <= io.en @[beh_lib.scala 335:16] - clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16] + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] - extmodule TEC_RV_ICG_2 : + extmodule gated_latch_2 : output Q : Clock input CK : Clock input EN : UInt<1> input SE : UInt<1> - defname = TEC_RV_ICG + defname = gated_latch module rvclkhdr_2 : @@ -62,23 +62,23 @@ circuit el2_lsu_stbuf : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of TEC_RV_ICG_2 @[beh_lib.scala 332:24] + inst clkhdr of gated_latch_2 @[el2_lib.scala 474:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12] - clkhdr.CK <= io.clk @[beh_lib.scala 334:16] - clkhdr.EN <= io.en @[beh_lib.scala 335:16] - clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16] + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] - extmodule TEC_RV_ICG_3 : + extmodule gated_latch_3 : output Q : Clock input CK : Clock input EN : UInt<1> input SE : UInt<1> - defname = TEC_RV_ICG + defname = gated_latch module rvclkhdr_3 : @@ -86,23 +86,23 @@ circuit el2_lsu_stbuf : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of TEC_RV_ICG_3 @[beh_lib.scala 332:24] + inst clkhdr of gated_latch_3 @[el2_lib.scala 474:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12] - clkhdr.CK <= io.clk @[beh_lib.scala 334:16] - clkhdr.EN <= io.en @[beh_lib.scala 335:16] - clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16] + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] - extmodule TEC_RV_ICG_4 : + extmodule gated_latch_4 : output Q : Clock input CK : Clock input EN : UInt<1> input SE : UInt<1> - defname = TEC_RV_ICG + defname = gated_latch module rvclkhdr_4 : @@ -110,23 +110,23 @@ circuit el2_lsu_stbuf : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of TEC_RV_ICG_4 @[beh_lib.scala 332:24] + inst clkhdr of gated_latch_4 @[el2_lib.scala 474:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12] - clkhdr.CK <= io.clk @[beh_lib.scala 334:16] - clkhdr.EN <= io.en @[beh_lib.scala 335:16] - clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16] + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] - extmodule TEC_RV_ICG_5 : + extmodule gated_latch_5 : output Q : Clock input CK : Clock input EN : UInt<1> input SE : UInt<1> - defname = TEC_RV_ICG + defname = gated_latch module rvclkhdr_5 : @@ -134,23 +134,23 @@ circuit el2_lsu_stbuf : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of TEC_RV_ICG_5 @[beh_lib.scala 332:24] + inst clkhdr of gated_latch_5 @[el2_lib.scala 474:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12] - clkhdr.CK <= io.clk @[beh_lib.scala 334:16] - clkhdr.EN <= io.en @[beh_lib.scala 335:16] - clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16] + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] - extmodule TEC_RV_ICG_6 : + extmodule gated_latch_6 : output Q : Clock input CK : Clock input EN : UInt<1> input SE : UInt<1> - defname = TEC_RV_ICG + defname = gated_latch module rvclkhdr_6 : @@ -158,23 +158,23 @@ circuit el2_lsu_stbuf : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of TEC_RV_ICG_6 @[beh_lib.scala 332:24] + inst clkhdr of gated_latch_6 @[el2_lib.scala 474:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12] - clkhdr.CK <= io.clk @[beh_lib.scala 334:16] - clkhdr.EN <= io.en @[beh_lib.scala 335:16] - clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16] + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] - extmodule TEC_RV_ICG_7 : + extmodule gated_latch_7 : output Q : Clock input CK : Clock input EN : UInt<1> input SE : UInt<1> - defname = TEC_RV_ICG + defname = gated_latch module rvclkhdr_7 : @@ -182,32 +182,32 @@ circuit el2_lsu_stbuf : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of TEC_RV_ICG_7 @[beh_lib.scala 332:24] + inst clkhdr of gated_latch_7 @[el2_lib.scala 474:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12] - clkhdr.CK <= io.clk @[beh_lib.scala 334:16] - clkhdr.EN <= io.en @[beh_lib.scala 335:16] - clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16] + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] module el2_lsu_stbuf : input clock : Clock input reset : AsyncReset - output io : {flip lsu_c1_m_clk : Clock, flip lsu_c1_r_clk : Clock, flip lsu_stbuf_c1_clk : Clock, flip lsu_free_c2_clk : Clock, flip lsu_pkt_m : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip lsu_pkt_r : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip store_stbuf_reqvld_r : UInt<1>, flip lsu_commit_r : UInt<1>, flip dec_lsu_valid_raw_d : UInt<1>, flip store_data_hi_r : UInt<32>, flip store_data_lo_r : UInt<32>, flip store_datafn_hi_r : UInt<32>, flip store_datafn_lo_r : UInt<32>, flip lsu_stbuf_commit_any : UInt<1>, flip lsu_addr_d : UInt<16>, flip lsu_addr_m : UInt<32>, flip lsu_addr_r : UInt<32>, flip end_addr_d : UInt<16>, flip end_addr_m : UInt<32>, flip end_addr_r : UInt<32>, flip addr_in_dccm_m : UInt<1>, flip addr_in_dccm_r : UInt<1>, flip lsu_cmpen_m : UInt<1>, flip scan_mode : UInt<1>, stbuf_reqvld_any : UInt<1>, stbuf_reqvld_flushed_any : UInt<1>, stbuf_addr_any : UInt<16>, stbuf_data_any : UInt<32>, lsu_stbuf_full_any : UInt<1>, lsu_stbuf_empty_any : UInt<1>, ldst_stbuf_reqvld_r : UInt<1>, stbuf_fwddata_hi_m : UInt<32>, stbuf_fwddata_lo_m : UInt<32>, stbuf_fwdbyteen_hi_m : UInt<4>, stbuf_fwdbyteen_lo_m : UInt<4>} + output io : {flip lsu_c1_m_clk : Clock, flip lsu_c1_r_clk : Clock, flip lsu_stbuf_c1_clk : Clock, flip lsu_free_c2_clk : Clock, flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip store_stbuf_reqvld_r : UInt<1>, flip lsu_commit_r : UInt<1>, flip dec_lsu_valid_raw_d : UInt<1>, flip store_data_hi_r : UInt<32>, flip store_data_lo_r : UInt<32>, flip store_datafn_hi_r : UInt<32>, flip store_datafn_lo_r : UInt<32>, flip lsu_stbuf_commit_any : UInt<1>, flip lsu_addr_d : UInt<16>, flip lsu_addr_m : UInt<32>, flip lsu_addr_r : UInt<32>, flip end_addr_d : UInt<16>, flip end_addr_m : UInt<32>, flip end_addr_r : UInt<32>, flip addr_in_dccm_m : UInt<1>, flip addr_in_dccm_r : UInt<1>, flip lsu_cmpen_m : UInt<1>, flip scan_mode : UInt<1>, stbuf_reqvld_any : UInt<1>, stbuf_reqvld_flushed_any : UInt<1>, stbuf_addr_any : UInt<16>, stbuf_data_any : UInt<32>, lsu_stbuf_full_any : UInt<1>, lsu_stbuf_empty_any : UInt<1>, ldst_stbuf_reqvld_r : UInt<1>, stbuf_fwddata_hi_m : UInt<32>, stbuf_fwddata_lo_m : UInt<32>, stbuf_fwdbyteen_hi_m : UInt<4>, stbuf_fwdbyteen_lo_m : UInt<4>} - io.stbuf_reqvld_any <= UInt<1>("h00") @[el2_lsu_stbuf.scala 52:47] - io.stbuf_reqvld_flushed_any <= UInt<1>("h00") @[el2_lsu_stbuf.scala 53:36] - io.stbuf_addr_any <= UInt<1>("h00") @[el2_lsu_stbuf.scala 54:35] - io.stbuf_data_any <= UInt<1>("h00") @[el2_lsu_stbuf.scala 55:35] - io.lsu_stbuf_full_any <= UInt<1>("h00") @[el2_lsu_stbuf.scala 56:43] - io.lsu_stbuf_empty_any <= UInt<1>("h00") @[el2_lsu_stbuf.scala 57:43] - io.ldst_stbuf_reqvld_r <= UInt<1>("h00") @[el2_lsu_stbuf.scala 58:43] - io.stbuf_fwddata_hi_m <= UInt<1>("h00") @[el2_lsu_stbuf.scala 59:43] - io.stbuf_fwddata_lo_m <= UInt<1>("h00") @[el2_lsu_stbuf.scala 60:43] - io.stbuf_fwdbyteen_hi_m <= UInt<1>("h00") @[el2_lsu_stbuf.scala 61:37] - io.stbuf_fwdbyteen_lo_m <= UInt<1>("h00") @[el2_lsu_stbuf.scala 62:37] + io.stbuf_reqvld_any <= UInt<1>("h00") @[el2_lsu_stbuf.scala 51:47] + io.stbuf_reqvld_flushed_any <= UInt<1>("h00") @[el2_lsu_stbuf.scala 52:35] + io.stbuf_addr_any <= UInt<1>("h00") @[el2_lsu_stbuf.scala 53:35] + io.stbuf_data_any <= UInt<1>("h00") @[el2_lsu_stbuf.scala 54:35] + io.lsu_stbuf_full_any <= UInt<1>("h00") @[el2_lsu_stbuf.scala 55:43] + io.lsu_stbuf_empty_any <= UInt<1>("h00") @[el2_lsu_stbuf.scala 56:43] + io.ldst_stbuf_reqvld_r <= UInt<1>("h00") @[el2_lsu_stbuf.scala 57:43] + io.stbuf_fwddata_hi_m <= UInt<1>("h00") @[el2_lsu_stbuf.scala 58:43] + io.stbuf_fwddata_lo_m <= UInt<1>("h00") @[el2_lsu_stbuf.scala 59:43] + io.stbuf_fwdbyteen_hi_m <= UInt<1>("h00") @[el2_lsu_stbuf.scala 60:37] + io.stbuf_fwdbyteen_lo_m <= UInt<1>("h00") @[el2_lsu_stbuf.scala 61:37] wire stbuf_vld : UInt<4> stbuf_vld <= UInt<1>("h00") wire stbuf_wr_en : UInt<4> @@ -220,36 +220,36 @@ circuit el2_lsu_stbuf : stbuf_reset <= UInt<1>("h00") wire store_byteen_ext_r : UInt<8> store_byteen_ext_r <= UInt<1>("h00") - wire stbuf_addr : UInt<16>[4] @[el2_lsu_stbuf.scala 71:38] - stbuf_addr[0] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 72:14] - stbuf_addr[1] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 72:14] - stbuf_addr[2] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 72:14] - stbuf_addr[3] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 72:14] - wire stbuf_byteen : UInt<4>[4] @[el2_lsu_stbuf.scala 73:39] - stbuf_byteen[0] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 74:17] - stbuf_byteen[1] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 74:17] - stbuf_byteen[2] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 74:17] - stbuf_byteen[3] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 74:17] - wire stbuf_data : UInt<32>[4] @[el2_lsu_stbuf.scala 75:39] - stbuf_data[0] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 76:15] - stbuf_data[1] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 76:15] - stbuf_data[2] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 76:15] - stbuf_data[3] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 76:15] - wire stbuf_addrin : UInt<16>[4] @[el2_lsu_stbuf.scala 77:38] - stbuf_addrin[0] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 78:16] - stbuf_addrin[1] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 78:16] - stbuf_addrin[2] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 78:16] - stbuf_addrin[3] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 78:16] - wire stbuf_datain : UInt<32>[4] @[el2_lsu_stbuf.scala 79:39] - stbuf_datain[0] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 80:17] - stbuf_datain[1] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 80:17] - stbuf_datain[2] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 80:17] - stbuf_datain[3] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 80:17] - wire stbuf_byteenin : UInt<4>[4] @[el2_lsu_stbuf.scala 81:39] - stbuf_byteenin[0] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 82:19] - stbuf_byteenin[1] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 82:19] - stbuf_byteenin[2] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 82:19] - stbuf_byteenin[3] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 82:19] + wire stbuf_addr : UInt<16>[4] @[el2_lsu_stbuf.scala 70:38] + stbuf_addr[0] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 71:14] + stbuf_addr[1] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 71:14] + stbuf_addr[2] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 71:14] + stbuf_addr[3] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 71:14] + wire stbuf_byteen : UInt<4>[4] @[el2_lsu_stbuf.scala 72:38] + stbuf_byteen[0] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 73:16] + stbuf_byteen[1] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 73:16] + stbuf_byteen[2] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 73:16] + stbuf_byteen[3] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 73:16] + wire stbuf_data : UInt<32>[4] @[el2_lsu_stbuf.scala 74:38] + stbuf_data[0] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 75:14] + stbuf_data[1] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 75:14] + stbuf_data[2] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 75:14] + stbuf_data[3] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 75:14] + wire stbuf_addrin : UInt<16>[4] @[el2_lsu_stbuf.scala 76:38] + stbuf_addrin[0] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 77:16] + stbuf_addrin[1] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 77:16] + stbuf_addrin[2] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 77:16] + stbuf_addrin[3] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 77:16] + wire stbuf_datain : UInt<32>[4] @[el2_lsu_stbuf.scala 78:38] + stbuf_datain[0] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 79:16] + stbuf_datain[1] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 79:16] + stbuf_datain[2] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 79:16] + stbuf_datain[3] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 79:16] + wire stbuf_byteenin : UInt<4>[4] @[el2_lsu_stbuf.scala 80:38] + stbuf_byteenin[0] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 81:18] + stbuf_byteenin[1] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 81:18] + stbuf_byteenin[2] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 81:18] + stbuf_byteenin[3] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 81:18] wire WrPtr : UInt<2> WrPtr <= UInt<1>("h00") wire RdPtr : UInt<2> @@ -292,14 +292,14 @@ circuit el2_lsu_stbuf : ld_fwddata_rpipe_lo <= UInt<1>("h00") wire ld_fwddata_rpipe_hi : UInt<32> ld_fwddata_rpipe_hi <= UInt<1>("h00") - wire datain1 : UInt<8>[4] @[el2_lsu_stbuf.scala 106:34] - wire datain2 : UInt<8>[4] @[el2_lsu_stbuf.scala 107:34] - wire datain3 : UInt<8>[4] @[el2_lsu_stbuf.scala 108:34] - wire datain4 : UInt<8>[4] @[el2_lsu_stbuf.scala 109:34] - node _T = bits(io.lsu_pkt_r.by, 0, 0) @[el2_lsu_stbuf.scala 113:22] - node _T_1 = bits(io.lsu_pkt_r.half, 0, 0) @[el2_lsu_stbuf.scala 114:24] - node _T_2 = bits(io.lsu_pkt_r.word, 0, 0) @[el2_lsu_stbuf.scala 115:24] - node _T_3 = bits(io.lsu_pkt_r.dword, 0, 0) @[el2_lsu_stbuf.scala 116:25] + wire datain1 : UInt<8>[4] @[el2_lsu_stbuf.scala 105:33] + wire datain2 : UInt<8>[4] @[el2_lsu_stbuf.scala 106:33] + wire datain3 : UInt<8>[4] @[el2_lsu_stbuf.scala 107:33] + wire datain4 : UInt<8>[4] @[el2_lsu_stbuf.scala 108:33] + node _T = bits(io.lsu_pkt_r.bits.by, 0, 0) @[el2_lsu_stbuf.scala 112:26] + node _T_1 = bits(io.lsu_pkt_r.bits.half, 0, 0) @[el2_lsu_stbuf.scala 113:28] + node _T_2 = bits(io.lsu_pkt_r.bits.word, 0, 0) @[el2_lsu_stbuf.scala 114:28] + node _T_3 = bits(io.lsu_pkt_r.bits.dword, 0, 0) @[el2_lsu_stbuf.scala 115:29] node _T_4 = mux(_T, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_5 = mux(_T_1, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_6 = mux(_T_2, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72] @@ -309,580 +309,580 @@ circuit el2_lsu_stbuf : node _T_10 = or(_T_9, _T_7) @[Mux.scala 27:72] wire ldst_byteen_r : UInt<8> @[Mux.scala 27:72] ldst_byteen_r <= _T_10 @[Mux.scala 27:72] - node _T_11 = bits(io.lsu_addr_d, 2, 2) @[el2_lsu_stbuf.scala 118:36] - node _T_12 = bits(io.end_addr_d, 2, 2) @[el2_lsu_stbuf.scala 118:57] - node ldst_dual_d = neq(_T_11, _T_12) @[el2_lsu_stbuf.scala 118:40] - node dual_stbuf_write_r = and(ldst_dual_r, io.store_stbuf_reqvld_r) @[el2_lsu_stbuf.scala 119:41] - node _T_13 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_stbuf.scala 121:56] - node _T_14 = dshl(ldst_byteen_r, _T_13) @[el2_lsu_stbuf.scala 121:40] - store_byteen_ext_r <= _T_14 @[el2_lsu_stbuf.scala 121:23] - node _T_15 = bits(store_byteen_ext_r, 7, 4) @[el2_lsu_stbuf.scala 122:46] - node _T_16 = bits(io.lsu_pkt_r.store, 0, 0) @[Bitwise.scala 72:15] + node _T_11 = bits(io.lsu_addr_d, 2, 2) @[el2_lsu_stbuf.scala 117:35] + node _T_12 = bits(io.end_addr_d, 2, 2) @[el2_lsu_stbuf.scala 117:56] + node ldst_dual_d = neq(_T_11, _T_12) @[el2_lsu_stbuf.scala 117:39] + node dual_stbuf_write_r = and(ldst_dual_r, io.store_stbuf_reqvld_r) @[el2_lsu_stbuf.scala 118:40] + node _T_13 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_stbuf.scala 120:55] + node _T_14 = dshl(ldst_byteen_r, _T_13) @[el2_lsu_stbuf.scala 120:39] + store_byteen_ext_r <= _T_14 @[el2_lsu_stbuf.scala 120:22] + node _T_15 = bits(store_byteen_ext_r, 7, 4) @[el2_lsu_stbuf.scala 121:46] + node _T_16 = bits(io.lsu_pkt_r.bits.store, 0, 0) @[Bitwise.scala 72:15] node _T_17 = mux(_T_16, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node store_byteen_hi_r = and(_T_15, _T_17) @[el2_lsu_stbuf.scala 122:52] - node _T_18 = bits(store_byteen_ext_r, 3, 0) @[el2_lsu_stbuf.scala 123:46] - node _T_19 = bits(io.lsu_pkt_r.store, 0, 0) @[Bitwise.scala 72:15] + node store_byteen_hi_r = and(_T_15, _T_17) @[el2_lsu_stbuf.scala 121:52] + node _T_18 = bits(store_byteen_ext_r, 3, 0) @[el2_lsu_stbuf.scala 122:46] + node _T_19 = bits(io.lsu_pkt_r.bits.store, 0, 0) @[Bitwise.scala 72:15] node _T_20 = mux(_T_19, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node store_byteen_lo_r = and(_T_18, _T_20) @[el2_lsu_stbuf.scala 123:52] - node _T_21 = add(RdPtr, UInt<1>("h01")) @[el2_lsu_stbuf.scala 125:27] - node RdPtrPlus1 = tail(_T_21, 1) @[el2_lsu_stbuf.scala 125:27] - node _T_22 = add(WrPtr, UInt<1>("h01")) @[el2_lsu_stbuf.scala 126:27] - node WrPtrPlus1 = tail(_T_22, 1) @[el2_lsu_stbuf.scala 126:27] - node _T_23 = add(WrPtr, UInt<2>("h02")) @[el2_lsu_stbuf.scala 127:27] - node WrPtrPlus2 = tail(_T_23, 1) @[el2_lsu_stbuf.scala 127:27] - node _T_24 = and(io.lsu_commit_r, io.store_stbuf_reqvld_r) @[el2_lsu_stbuf.scala 129:46] - io.ldst_stbuf_reqvld_r <= _T_24 @[el2_lsu_stbuf.scala 129:27] - node _T_25 = bits(stbuf_addr[0], 15, 2) @[el2_lsu_stbuf.scala 131:78] - node _T_26 = bits(io.lsu_addr_r, 15, 2) @[el2_lsu_stbuf.scala 131:137] - node _T_27 = eq(_T_25, _T_26) @[el2_lsu_stbuf.scala 131:120] - node _T_28 = bits(stbuf_vld, 0, 0) @[el2_lsu_stbuf.scala 131:191] - node _T_29 = and(_T_27, _T_28) @[el2_lsu_stbuf.scala 131:179] - node _T_30 = bits(stbuf_dma_kill, 0, 0) @[el2_lsu_stbuf.scala 131:212] - node _T_31 = eq(_T_30, UInt<1>("h00")) @[el2_lsu_stbuf.scala 131:197] - node _T_32 = and(_T_29, _T_31) @[el2_lsu_stbuf.scala 131:195] - node _T_33 = bits(stbuf_reset, 0, 0) @[el2_lsu_stbuf.scala 131:230] - node _T_34 = eq(_T_33, UInt<1>("h00")) @[el2_lsu_stbuf.scala 131:218] - node _T_35 = and(_T_32, _T_34) @[el2_lsu_stbuf.scala 131:216] - node _T_36 = bits(stbuf_addr[1], 15, 2) @[el2_lsu_stbuf.scala 131:78] - node _T_37 = bits(io.lsu_addr_r, 15, 2) @[el2_lsu_stbuf.scala 131:137] - node _T_38 = eq(_T_36, _T_37) @[el2_lsu_stbuf.scala 131:120] - node _T_39 = bits(stbuf_vld, 1, 1) @[el2_lsu_stbuf.scala 131:191] - node _T_40 = and(_T_38, _T_39) @[el2_lsu_stbuf.scala 131:179] - node _T_41 = bits(stbuf_dma_kill, 1, 1) @[el2_lsu_stbuf.scala 131:212] - node _T_42 = eq(_T_41, UInt<1>("h00")) @[el2_lsu_stbuf.scala 131:197] - node _T_43 = and(_T_40, _T_42) @[el2_lsu_stbuf.scala 131:195] - node _T_44 = bits(stbuf_reset, 1, 1) @[el2_lsu_stbuf.scala 131:230] - node _T_45 = eq(_T_44, UInt<1>("h00")) @[el2_lsu_stbuf.scala 131:218] - node _T_46 = and(_T_43, _T_45) @[el2_lsu_stbuf.scala 131:216] - node _T_47 = bits(stbuf_addr[2], 15, 2) @[el2_lsu_stbuf.scala 131:78] - node _T_48 = bits(io.lsu_addr_r, 15, 2) @[el2_lsu_stbuf.scala 131:137] - node _T_49 = eq(_T_47, _T_48) @[el2_lsu_stbuf.scala 131:120] - node _T_50 = bits(stbuf_vld, 2, 2) @[el2_lsu_stbuf.scala 131:191] - node _T_51 = and(_T_49, _T_50) @[el2_lsu_stbuf.scala 131:179] - node _T_52 = bits(stbuf_dma_kill, 2, 2) @[el2_lsu_stbuf.scala 131:212] - node _T_53 = eq(_T_52, UInt<1>("h00")) @[el2_lsu_stbuf.scala 131:197] - node _T_54 = and(_T_51, _T_53) @[el2_lsu_stbuf.scala 131:195] - node _T_55 = bits(stbuf_reset, 2, 2) @[el2_lsu_stbuf.scala 131:230] - node _T_56 = eq(_T_55, UInt<1>("h00")) @[el2_lsu_stbuf.scala 131:218] - node _T_57 = and(_T_54, _T_56) @[el2_lsu_stbuf.scala 131:216] - node _T_58 = bits(stbuf_addr[3], 15, 2) @[el2_lsu_stbuf.scala 131:78] - node _T_59 = bits(io.lsu_addr_r, 15, 2) @[el2_lsu_stbuf.scala 131:137] - node _T_60 = eq(_T_58, _T_59) @[el2_lsu_stbuf.scala 131:120] - node _T_61 = bits(stbuf_vld, 3, 3) @[el2_lsu_stbuf.scala 131:191] - node _T_62 = and(_T_60, _T_61) @[el2_lsu_stbuf.scala 131:179] - node _T_63 = bits(stbuf_dma_kill, 3, 3) @[el2_lsu_stbuf.scala 131:212] - node _T_64 = eq(_T_63, UInt<1>("h00")) @[el2_lsu_stbuf.scala 131:197] - node _T_65 = and(_T_62, _T_64) @[el2_lsu_stbuf.scala 131:195] - node _T_66 = bits(stbuf_reset, 3, 3) @[el2_lsu_stbuf.scala 131:230] - node _T_67 = eq(_T_66, UInt<1>("h00")) @[el2_lsu_stbuf.scala 131:218] - node _T_68 = and(_T_65, _T_67) @[el2_lsu_stbuf.scala 131:216] + node store_byteen_lo_r = and(_T_18, _T_20) @[el2_lsu_stbuf.scala 122:52] + node _T_21 = add(RdPtr, UInt<1>("h01")) @[el2_lsu_stbuf.scala 124:26] + node RdPtrPlus1 = tail(_T_21, 1) @[el2_lsu_stbuf.scala 124:26] + node _T_22 = add(WrPtr, UInt<1>("h01")) @[el2_lsu_stbuf.scala 125:26] + node WrPtrPlus1 = tail(_T_22, 1) @[el2_lsu_stbuf.scala 125:26] + node _T_23 = add(WrPtr, UInt<2>("h02")) @[el2_lsu_stbuf.scala 126:26] + node WrPtrPlus2 = tail(_T_23, 1) @[el2_lsu_stbuf.scala 126:26] + node _T_24 = and(io.lsu_commit_r, io.store_stbuf_reqvld_r) @[el2_lsu_stbuf.scala 128:45] + io.ldst_stbuf_reqvld_r <= _T_24 @[el2_lsu_stbuf.scala 128:26] + node _T_25 = bits(stbuf_addr[0], 15, 2) @[el2_lsu_stbuf.scala 130:78] + node _T_26 = bits(io.lsu_addr_r, 15, 2) @[el2_lsu_stbuf.scala 130:137] + node _T_27 = eq(_T_25, _T_26) @[el2_lsu_stbuf.scala 130:120] + node _T_28 = bits(stbuf_vld, 0, 0) @[el2_lsu_stbuf.scala 130:191] + node _T_29 = and(_T_27, _T_28) @[el2_lsu_stbuf.scala 130:179] + node _T_30 = bits(stbuf_dma_kill, 0, 0) @[el2_lsu_stbuf.scala 130:212] + node _T_31 = eq(_T_30, UInt<1>("h00")) @[el2_lsu_stbuf.scala 130:197] + node _T_32 = and(_T_29, _T_31) @[el2_lsu_stbuf.scala 130:195] + node _T_33 = bits(stbuf_reset, 0, 0) @[el2_lsu_stbuf.scala 130:230] + node _T_34 = eq(_T_33, UInt<1>("h00")) @[el2_lsu_stbuf.scala 130:218] + node _T_35 = and(_T_32, _T_34) @[el2_lsu_stbuf.scala 130:216] + node _T_36 = bits(stbuf_addr[1], 15, 2) @[el2_lsu_stbuf.scala 130:78] + node _T_37 = bits(io.lsu_addr_r, 15, 2) @[el2_lsu_stbuf.scala 130:137] + node _T_38 = eq(_T_36, _T_37) @[el2_lsu_stbuf.scala 130:120] + node _T_39 = bits(stbuf_vld, 1, 1) @[el2_lsu_stbuf.scala 130:191] + node _T_40 = and(_T_38, _T_39) @[el2_lsu_stbuf.scala 130:179] + node _T_41 = bits(stbuf_dma_kill, 1, 1) @[el2_lsu_stbuf.scala 130:212] + node _T_42 = eq(_T_41, UInt<1>("h00")) @[el2_lsu_stbuf.scala 130:197] + node _T_43 = and(_T_40, _T_42) @[el2_lsu_stbuf.scala 130:195] + node _T_44 = bits(stbuf_reset, 1, 1) @[el2_lsu_stbuf.scala 130:230] + node _T_45 = eq(_T_44, UInt<1>("h00")) @[el2_lsu_stbuf.scala 130:218] + node _T_46 = and(_T_43, _T_45) @[el2_lsu_stbuf.scala 130:216] + node _T_47 = bits(stbuf_addr[2], 15, 2) @[el2_lsu_stbuf.scala 130:78] + node _T_48 = bits(io.lsu_addr_r, 15, 2) @[el2_lsu_stbuf.scala 130:137] + node _T_49 = eq(_T_47, _T_48) @[el2_lsu_stbuf.scala 130:120] + node _T_50 = bits(stbuf_vld, 2, 2) @[el2_lsu_stbuf.scala 130:191] + node _T_51 = and(_T_49, _T_50) @[el2_lsu_stbuf.scala 130:179] + node _T_52 = bits(stbuf_dma_kill, 2, 2) @[el2_lsu_stbuf.scala 130:212] + node _T_53 = eq(_T_52, UInt<1>("h00")) @[el2_lsu_stbuf.scala 130:197] + node _T_54 = and(_T_51, _T_53) @[el2_lsu_stbuf.scala 130:195] + node _T_55 = bits(stbuf_reset, 2, 2) @[el2_lsu_stbuf.scala 130:230] + node _T_56 = eq(_T_55, UInt<1>("h00")) @[el2_lsu_stbuf.scala 130:218] + node _T_57 = and(_T_54, _T_56) @[el2_lsu_stbuf.scala 130:216] + node _T_58 = bits(stbuf_addr[3], 15, 2) @[el2_lsu_stbuf.scala 130:78] + node _T_59 = bits(io.lsu_addr_r, 15, 2) @[el2_lsu_stbuf.scala 130:137] + node _T_60 = eq(_T_58, _T_59) @[el2_lsu_stbuf.scala 130:120] + node _T_61 = bits(stbuf_vld, 3, 3) @[el2_lsu_stbuf.scala 130:191] + node _T_62 = and(_T_60, _T_61) @[el2_lsu_stbuf.scala 130:179] + node _T_63 = bits(stbuf_dma_kill, 3, 3) @[el2_lsu_stbuf.scala 130:212] + node _T_64 = eq(_T_63, UInt<1>("h00")) @[el2_lsu_stbuf.scala 130:197] + node _T_65 = and(_T_62, _T_64) @[el2_lsu_stbuf.scala 130:195] + node _T_66 = bits(stbuf_reset, 3, 3) @[el2_lsu_stbuf.scala 130:230] + node _T_67 = eq(_T_66, UInt<1>("h00")) @[el2_lsu_stbuf.scala 130:218] + node _T_68 = and(_T_65, _T_67) @[el2_lsu_stbuf.scala 130:216] node _T_69 = cat(_T_68, _T_57) @[Cat.scala 29:58] node _T_70 = cat(_T_69, _T_46) @[Cat.scala 29:58] node store_matchvec_lo_r = cat(_T_70, _T_35) @[Cat.scala 29:58] - node _T_71 = bits(stbuf_addr[0], 15, 2) @[el2_lsu_stbuf.scala 132:78] - node _T_72 = bits(io.end_addr_r, 15, 2) @[el2_lsu_stbuf.scala 132:137] - node _T_73 = eq(_T_71, _T_72) @[el2_lsu_stbuf.scala 132:120] - node _T_74 = bits(stbuf_vld, 0, 0) @[el2_lsu_stbuf.scala 132:190] - node _T_75 = and(_T_73, _T_74) @[el2_lsu_stbuf.scala 132:179] - node _T_76 = bits(stbuf_dma_kill, 0, 0) @[el2_lsu_stbuf.scala 132:211] - node _T_77 = eq(_T_76, UInt<1>("h00")) @[el2_lsu_stbuf.scala 132:196] - node _T_78 = and(_T_75, _T_77) @[el2_lsu_stbuf.scala 132:194] - node _T_79 = and(_T_78, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 132:215] - node _T_80 = bits(stbuf_reset, 0, 0) @[el2_lsu_stbuf.scala 132:250] - node _T_81 = eq(_T_80, UInt<1>("h00")) @[el2_lsu_stbuf.scala 132:238] - node _T_82 = and(_T_79, _T_81) @[el2_lsu_stbuf.scala 132:236] - node _T_83 = bits(stbuf_addr[1], 15, 2) @[el2_lsu_stbuf.scala 132:78] - node _T_84 = bits(io.end_addr_r, 15, 2) @[el2_lsu_stbuf.scala 132:137] - node _T_85 = eq(_T_83, _T_84) @[el2_lsu_stbuf.scala 132:120] - node _T_86 = bits(stbuf_vld, 1, 1) @[el2_lsu_stbuf.scala 132:190] - node _T_87 = and(_T_85, _T_86) @[el2_lsu_stbuf.scala 132:179] - node _T_88 = bits(stbuf_dma_kill, 1, 1) @[el2_lsu_stbuf.scala 132:211] - node _T_89 = eq(_T_88, UInt<1>("h00")) @[el2_lsu_stbuf.scala 132:196] - node _T_90 = and(_T_87, _T_89) @[el2_lsu_stbuf.scala 132:194] - node _T_91 = and(_T_90, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 132:215] - node _T_92 = bits(stbuf_reset, 1, 1) @[el2_lsu_stbuf.scala 132:250] - node _T_93 = eq(_T_92, UInt<1>("h00")) @[el2_lsu_stbuf.scala 132:238] - node _T_94 = and(_T_91, _T_93) @[el2_lsu_stbuf.scala 132:236] - node _T_95 = bits(stbuf_addr[2], 15, 2) @[el2_lsu_stbuf.scala 132:78] - node _T_96 = bits(io.end_addr_r, 15, 2) @[el2_lsu_stbuf.scala 132:137] - node _T_97 = eq(_T_95, _T_96) @[el2_lsu_stbuf.scala 132:120] - node _T_98 = bits(stbuf_vld, 2, 2) @[el2_lsu_stbuf.scala 132:190] - node _T_99 = and(_T_97, _T_98) @[el2_lsu_stbuf.scala 132:179] - node _T_100 = bits(stbuf_dma_kill, 2, 2) @[el2_lsu_stbuf.scala 132:211] - node _T_101 = eq(_T_100, UInt<1>("h00")) @[el2_lsu_stbuf.scala 132:196] - node _T_102 = and(_T_99, _T_101) @[el2_lsu_stbuf.scala 132:194] - node _T_103 = and(_T_102, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 132:215] - node _T_104 = bits(stbuf_reset, 2, 2) @[el2_lsu_stbuf.scala 132:250] - node _T_105 = eq(_T_104, UInt<1>("h00")) @[el2_lsu_stbuf.scala 132:238] - node _T_106 = and(_T_103, _T_105) @[el2_lsu_stbuf.scala 132:236] - node _T_107 = bits(stbuf_addr[3], 15, 2) @[el2_lsu_stbuf.scala 132:78] - node _T_108 = bits(io.end_addr_r, 15, 2) @[el2_lsu_stbuf.scala 132:137] - node _T_109 = eq(_T_107, _T_108) @[el2_lsu_stbuf.scala 132:120] - node _T_110 = bits(stbuf_vld, 3, 3) @[el2_lsu_stbuf.scala 132:190] - node _T_111 = and(_T_109, _T_110) @[el2_lsu_stbuf.scala 132:179] - node _T_112 = bits(stbuf_dma_kill, 3, 3) @[el2_lsu_stbuf.scala 132:211] - node _T_113 = eq(_T_112, UInt<1>("h00")) @[el2_lsu_stbuf.scala 132:196] - node _T_114 = and(_T_111, _T_113) @[el2_lsu_stbuf.scala 132:194] - node _T_115 = and(_T_114, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 132:215] - node _T_116 = bits(stbuf_reset, 3, 3) @[el2_lsu_stbuf.scala 132:250] - node _T_117 = eq(_T_116, UInt<1>("h00")) @[el2_lsu_stbuf.scala 132:238] - node _T_118 = and(_T_115, _T_117) @[el2_lsu_stbuf.scala 132:236] + node _T_71 = bits(stbuf_addr[0], 15, 2) @[el2_lsu_stbuf.scala 131:78] + node _T_72 = bits(io.end_addr_r, 15, 2) @[el2_lsu_stbuf.scala 131:137] + node _T_73 = eq(_T_71, _T_72) @[el2_lsu_stbuf.scala 131:120] + node _T_74 = bits(stbuf_vld, 0, 0) @[el2_lsu_stbuf.scala 131:190] + node _T_75 = and(_T_73, _T_74) @[el2_lsu_stbuf.scala 131:179] + node _T_76 = bits(stbuf_dma_kill, 0, 0) @[el2_lsu_stbuf.scala 131:211] + node _T_77 = eq(_T_76, UInt<1>("h00")) @[el2_lsu_stbuf.scala 131:196] + node _T_78 = and(_T_75, _T_77) @[el2_lsu_stbuf.scala 131:194] + node _T_79 = and(_T_78, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 131:215] + node _T_80 = bits(stbuf_reset, 0, 0) @[el2_lsu_stbuf.scala 131:250] + node _T_81 = eq(_T_80, UInt<1>("h00")) @[el2_lsu_stbuf.scala 131:238] + node _T_82 = and(_T_79, _T_81) @[el2_lsu_stbuf.scala 131:236] + node _T_83 = bits(stbuf_addr[1], 15, 2) @[el2_lsu_stbuf.scala 131:78] + node _T_84 = bits(io.end_addr_r, 15, 2) @[el2_lsu_stbuf.scala 131:137] + node _T_85 = eq(_T_83, _T_84) @[el2_lsu_stbuf.scala 131:120] + node _T_86 = bits(stbuf_vld, 1, 1) @[el2_lsu_stbuf.scala 131:190] + node _T_87 = and(_T_85, _T_86) @[el2_lsu_stbuf.scala 131:179] + node _T_88 = bits(stbuf_dma_kill, 1, 1) @[el2_lsu_stbuf.scala 131:211] + node _T_89 = eq(_T_88, UInt<1>("h00")) @[el2_lsu_stbuf.scala 131:196] + node _T_90 = and(_T_87, _T_89) @[el2_lsu_stbuf.scala 131:194] + node _T_91 = and(_T_90, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 131:215] + node _T_92 = bits(stbuf_reset, 1, 1) @[el2_lsu_stbuf.scala 131:250] + node _T_93 = eq(_T_92, UInt<1>("h00")) @[el2_lsu_stbuf.scala 131:238] + node _T_94 = and(_T_91, _T_93) @[el2_lsu_stbuf.scala 131:236] + node _T_95 = bits(stbuf_addr[2], 15, 2) @[el2_lsu_stbuf.scala 131:78] + node _T_96 = bits(io.end_addr_r, 15, 2) @[el2_lsu_stbuf.scala 131:137] + node _T_97 = eq(_T_95, _T_96) @[el2_lsu_stbuf.scala 131:120] + node _T_98 = bits(stbuf_vld, 2, 2) @[el2_lsu_stbuf.scala 131:190] + node _T_99 = and(_T_97, _T_98) @[el2_lsu_stbuf.scala 131:179] + node _T_100 = bits(stbuf_dma_kill, 2, 2) @[el2_lsu_stbuf.scala 131:211] + node _T_101 = eq(_T_100, UInt<1>("h00")) @[el2_lsu_stbuf.scala 131:196] + node _T_102 = and(_T_99, _T_101) @[el2_lsu_stbuf.scala 131:194] + node _T_103 = and(_T_102, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 131:215] + node _T_104 = bits(stbuf_reset, 2, 2) @[el2_lsu_stbuf.scala 131:250] + node _T_105 = eq(_T_104, UInt<1>("h00")) @[el2_lsu_stbuf.scala 131:238] + node _T_106 = and(_T_103, _T_105) @[el2_lsu_stbuf.scala 131:236] + node _T_107 = bits(stbuf_addr[3], 15, 2) @[el2_lsu_stbuf.scala 131:78] + node _T_108 = bits(io.end_addr_r, 15, 2) @[el2_lsu_stbuf.scala 131:137] + node _T_109 = eq(_T_107, _T_108) @[el2_lsu_stbuf.scala 131:120] + node _T_110 = bits(stbuf_vld, 3, 3) @[el2_lsu_stbuf.scala 131:190] + node _T_111 = and(_T_109, _T_110) @[el2_lsu_stbuf.scala 131:179] + node _T_112 = bits(stbuf_dma_kill, 3, 3) @[el2_lsu_stbuf.scala 131:211] + node _T_113 = eq(_T_112, UInt<1>("h00")) @[el2_lsu_stbuf.scala 131:196] + node _T_114 = and(_T_111, _T_113) @[el2_lsu_stbuf.scala 131:194] + node _T_115 = and(_T_114, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 131:215] + node _T_116 = bits(stbuf_reset, 3, 3) @[el2_lsu_stbuf.scala 131:250] + node _T_117 = eq(_T_116, UInt<1>("h00")) @[el2_lsu_stbuf.scala 131:238] + node _T_118 = and(_T_115, _T_117) @[el2_lsu_stbuf.scala 131:236] node _T_119 = cat(_T_118, _T_106) @[Cat.scala 29:58] node _T_120 = cat(_T_119, _T_94) @[Cat.scala 29:58] node store_matchvec_hi_r = cat(_T_120, _T_82) @[Cat.scala 29:58] - node store_coalesce_lo_r = orr(store_matchvec_lo_r) @[el2_lsu_stbuf.scala 134:50] - node store_coalesce_hi_r = orr(store_matchvec_hi_r) @[el2_lsu_stbuf.scala 135:50] - node _T_121 = eq(UInt<1>("h00"), WrPtr) @[el2_lsu_stbuf.scala 138:64] - node _T_122 = eq(store_coalesce_lo_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 138:77] - node _T_123 = and(_T_121, _T_122) @[el2_lsu_stbuf.scala 138:75] - node _T_124 = eq(UInt<1>("h00"), WrPtr) @[el2_lsu_stbuf.scala 139:64] - node _T_125 = and(_T_124, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 139:75] - node _T_126 = eq(store_coalesce_hi_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 139:98] - node _T_127 = and(_T_125, _T_126) @[el2_lsu_stbuf.scala 139:96] - node _T_128 = or(_T_123, _T_127) @[el2_lsu_stbuf.scala 138:99] - node _T_129 = eq(UInt<1>("h00"), WrPtrPlus1) @[el2_lsu_stbuf.scala 140:64] - node _T_130 = and(_T_129, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 140:80] - node _T_131 = or(store_coalesce_lo_r, store_coalesce_hi_r) @[el2_lsu_stbuf.scala 140:125] - node _T_132 = eq(_T_131, UInt<1>("h00")) @[el2_lsu_stbuf.scala 140:103] - node _T_133 = and(_T_130, _T_132) @[el2_lsu_stbuf.scala 140:101] - node _T_134 = or(_T_128, _T_133) @[el2_lsu_stbuf.scala 139:120] - node _T_135 = bits(store_matchvec_lo_r, 0, 0) @[el2_lsu_stbuf.scala 141:72] - node _T_136 = or(_T_134, _T_135) @[el2_lsu_stbuf.scala 140:149] - node _T_137 = bits(store_matchvec_hi_r, 0, 0) @[el2_lsu_stbuf.scala 141:97] - node _T_138 = or(_T_136, _T_137) @[el2_lsu_stbuf.scala 141:76] - node _T_139 = and(io.ldst_stbuf_reqvld_r, _T_138) @[el2_lsu_stbuf.scala 137:77] - node _T_140 = eq(UInt<1>("h01"), WrPtr) @[el2_lsu_stbuf.scala 138:64] - node _T_141 = eq(store_coalesce_lo_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 138:77] - node _T_142 = and(_T_140, _T_141) @[el2_lsu_stbuf.scala 138:75] - node _T_143 = eq(UInt<1>("h01"), WrPtr) @[el2_lsu_stbuf.scala 139:64] - node _T_144 = and(_T_143, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 139:75] - node _T_145 = eq(store_coalesce_hi_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 139:98] - node _T_146 = and(_T_144, _T_145) @[el2_lsu_stbuf.scala 139:96] - node _T_147 = or(_T_142, _T_146) @[el2_lsu_stbuf.scala 138:99] - node _T_148 = eq(UInt<1>("h01"), WrPtrPlus1) @[el2_lsu_stbuf.scala 140:64] - node _T_149 = and(_T_148, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 140:80] - node _T_150 = or(store_coalesce_lo_r, store_coalesce_hi_r) @[el2_lsu_stbuf.scala 140:125] - node _T_151 = eq(_T_150, UInt<1>("h00")) @[el2_lsu_stbuf.scala 140:103] - node _T_152 = and(_T_149, _T_151) @[el2_lsu_stbuf.scala 140:101] - node _T_153 = or(_T_147, _T_152) @[el2_lsu_stbuf.scala 139:120] - node _T_154 = bits(store_matchvec_lo_r, 1, 1) @[el2_lsu_stbuf.scala 141:72] - node _T_155 = or(_T_153, _T_154) @[el2_lsu_stbuf.scala 140:149] - node _T_156 = bits(store_matchvec_hi_r, 1, 1) @[el2_lsu_stbuf.scala 141:97] - node _T_157 = or(_T_155, _T_156) @[el2_lsu_stbuf.scala 141:76] - node _T_158 = and(io.ldst_stbuf_reqvld_r, _T_157) @[el2_lsu_stbuf.scala 137:77] - node _T_159 = eq(UInt<2>("h02"), WrPtr) @[el2_lsu_stbuf.scala 138:64] - node _T_160 = eq(store_coalesce_lo_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 138:77] - node _T_161 = and(_T_159, _T_160) @[el2_lsu_stbuf.scala 138:75] - node _T_162 = eq(UInt<2>("h02"), WrPtr) @[el2_lsu_stbuf.scala 139:64] - node _T_163 = and(_T_162, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 139:75] - node _T_164 = eq(store_coalesce_hi_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 139:98] - node _T_165 = and(_T_163, _T_164) @[el2_lsu_stbuf.scala 139:96] - node _T_166 = or(_T_161, _T_165) @[el2_lsu_stbuf.scala 138:99] - node _T_167 = eq(UInt<2>("h02"), WrPtrPlus1) @[el2_lsu_stbuf.scala 140:64] - node _T_168 = and(_T_167, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 140:80] - node _T_169 = or(store_coalesce_lo_r, store_coalesce_hi_r) @[el2_lsu_stbuf.scala 140:125] - node _T_170 = eq(_T_169, UInt<1>("h00")) @[el2_lsu_stbuf.scala 140:103] - node _T_171 = and(_T_168, _T_170) @[el2_lsu_stbuf.scala 140:101] - node _T_172 = or(_T_166, _T_171) @[el2_lsu_stbuf.scala 139:120] - node _T_173 = bits(store_matchvec_lo_r, 2, 2) @[el2_lsu_stbuf.scala 141:72] - node _T_174 = or(_T_172, _T_173) @[el2_lsu_stbuf.scala 140:149] - node _T_175 = bits(store_matchvec_hi_r, 2, 2) @[el2_lsu_stbuf.scala 141:97] - node _T_176 = or(_T_174, _T_175) @[el2_lsu_stbuf.scala 141:76] - node _T_177 = and(io.ldst_stbuf_reqvld_r, _T_176) @[el2_lsu_stbuf.scala 137:77] - node _T_178 = eq(UInt<2>("h03"), WrPtr) @[el2_lsu_stbuf.scala 138:64] - node _T_179 = eq(store_coalesce_lo_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 138:77] - node _T_180 = and(_T_178, _T_179) @[el2_lsu_stbuf.scala 138:75] - node _T_181 = eq(UInt<2>("h03"), WrPtr) @[el2_lsu_stbuf.scala 139:64] - node _T_182 = and(_T_181, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 139:75] - node _T_183 = eq(store_coalesce_hi_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 139:98] - node _T_184 = and(_T_182, _T_183) @[el2_lsu_stbuf.scala 139:96] - node _T_185 = or(_T_180, _T_184) @[el2_lsu_stbuf.scala 138:99] - node _T_186 = eq(UInt<2>("h03"), WrPtrPlus1) @[el2_lsu_stbuf.scala 140:64] - node _T_187 = and(_T_186, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 140:80] - node _T_188 = or(store_coalesce_lo_r, store_coalesce_hi_r) @[el2_lsu_stbuf.scala 140:125] - node _T_189 = eq(_T_188, UInt<1>("h00")) @[el2_lsu_stbuf.scala 140:103] - node _T_190 = and(_T_187, _T_189) @[el2_lsu_stbuf.scala 140:101] - node _T_191 = or(_T_185, _T_190) @[el2_lsu_stbuf.scala 139:120] - node _T_192 = bits(store_matchvec_lo_r, 3, 3) @[el2_lsu_stbuf.scala 141:72] - node _T_193 = or(_T_191, _T_192) @[el2_lsu_stbuf.scala 140:149] - node _T_194 = bits(store_matchvec_hi_r, 3, 3) @[el2_lsu_stbuf.scala 141:97] - node _T_195 = or(_T_193, _T_194) @[el2_lsu_stbuf.scala 141:76] - node _T_196 = and(io.ldst_stbuf_reqvld_r, _T_195) @[el2_lsu_stbuf.scala 137:77] + node store_coalesce_lo_r = orr(store_matchvec_lo_r) @[el2_lsu_stbuf.scala 133:49] + node store_coalesce_hi_r = orr(store_matchvec_hi_r) @[el2_lsu_stbuf.scala 134:49] + node _T_121 = eq(UInt<1>("h00"), WrPtr) @[el2_lsu_stbuf.scala 137:16] + node _T_122 = eq(store_coalesce_lo_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 137:29] + node _T_123 = and(_T_121, _T_122) @[el2_lsu_stbuf.scala 137:27] + node _T_124 = eq(UInt<1>("h00"), WrPtr) @[el2_lsu_stbuf.scala 138:18] + node _T_125 = and(_T_124, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 138:29] + node _T_126 = eq(store_coalesce_hi_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 138:52] + node _T_127 = and(_T_125, _T_126) @[el2_lsu_stbuf.scala 138:50] + node _T_128 = or(_T_123, _T_127) @[el2_lsu_stbuf.scala 137:51] + node _T_129 = eq(UInt<1>("h00"), WrPtrPlus1) @[el2_lsu_stbuf.scala 139:18] + node _T_130 = and(_T_129, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 139:34] + node _T_131 = or(store_coalesce_lo_r, store_coalesce_hi_r) @[el2_lsu_stbuf.scala 139:79] + node _T_132 = eq(_T_131, UInt<1>("h00")) @[el2_lsu_stbuf.scala 139:57] + node _T_133 = and(_T_130, _T_132) @[el2_lsu_stbuf.scala 139:55] + node _T_134 = or(_T_128, _T_133) @[el2_lsu_stbuf.scala 138:74] + node _T_135 = bits(store_matchvec_lo_r, 0, 0) @[el2_lsu_stbuf.scala 140:26] + node _T_136 = or(_T_134, _T_135) @[el2_lsu_stbuf.scala 139:103] + node _T_137 = bits(store_matchvec_hi_r, 0, 0) @[el2_lsu_stbuf.scala 140:51] + node _T_138 = or(_T_136, _T_137) @[el2_lsu_stbuf.scala 140:30] + node _T_139 = and(io.ldst_stbuf_reqvld_r, _T_138) @[el2_lsu_stbuf.scala 136:76] + node _T_140 = eq(UInt<1>("h01"), WrPtr) @[el2_lsu_stbuf.scala 137:16] + node _T_141 = eq(store_coalesce_lo_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 137:29] + node _T_142 = and(_T_140, _T_141) @[el2_lsu_stbuf.scala 137:27] + node _T_143 = eq(UInt<1>("h01"), WrPtr) @[el2_lsu_stbuf.scala 138:18] + node _T_144 = and(_T_143, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 138:29] + node _T_145 = eq(store_coalesce_hi_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 138:52] + node _T_146 = and(_T_144, _T_145) @[el2_lsu_stbuf.scala 138:50] + node _T_147 = or(_T_142, _T_146) @[el2_lsu_stbuf.scala 137:51] + node _T_148 = eq(UInt<1>("h01"), WrPtrPlus1) @[el2_lsu_stbuf.scala 139:18] + node _T_149 = and(_T_148, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 139:34] + node _T_150 = or(store_coalesce_lo_r, store_coalesce_hi_r) @[el2_lsu_stbuf.scala 139:79] + node _T_151 = eq(_T_150, UInt<1>("h00")) @[el2_lsu_stbuf.scala 139:57] + node _T_152 = and(_T_149, _T_151) @[el2_lsu_stbuf.scala 139:55] + node _T_153 = or(_T_147, _T_152) @[el2_lsu_stbuf.scala 138:74] + node _T_154 = bits(store_matchvec_lo_r, 1, 1) @[el2_lsu_stbuf.scala 140:26] + node _T_155 = or(_T_153, _T_154) @[el2_lsu_stbuf.scala 139:103] + node _T_156 = bits(store_matchvec_hi_r, 1, 1) @[el2_lsu_stbuf.scala 140:51] + node _T_157 = or(_T_155, _T_156) @[el2_lsu_stbuf.scala 140:30] + node _T_158 = and(io.ldst_stbuf_reqvld_r, _T_157) @[el2_lsu_stbuf.scala 136:76] + node _T_159 = eq(UInt<2>("h02"), WrPtr) @[el2_lsu_stbuf.scala 137:16] + node _T_160 = eq(store_coalesce_lo_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 137:29] + node _T_161 = and(_T_159, _T_160) @[el2_lsu_stbuf.scala 137:27] + node _T_162 = eq(UInt<2>("h02"), WrPtr) @[el2_lsu_stbuf.scala 138:18] + node _T_163 = and(_T_162, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 138:29] + node _T_164 = eq(store_coalesce_hi_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 138:52] + node _T_165 = and(_T_163, _T_164) @[el2_lsu_stbuf.scala 138:50] + node _T_166 = or(_T_161, _T_165) @[el2_lsu_stbuf.scala 137:51] + node _T_167 = eq(UInt<2>("h02"), WrPtrPlus1) @[el2_lsu_stbuf.scala 139:18] + node _T_168 = and(_T_167, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 139:34] + node _T_169 = or(store_coalesce_lo_r, store_coalesce_hi_r) @[el2_lsu_stbuf.scala 139:79] + node _T_170 = eq(_T_169, UInt<1>("h00")) @[el2_lsu_stbuf.scala 139:57] + node _T_171 = and(_T_168, _T_170) @[el2_lsu_stbuf.scala 139:55] + node _T_172 = or(_T_166, _T_171) @[el2_lsu_stbuf.scala 138:74] + node _T_173 = bits(store_matchvec_lo_r, 2, 2) @[el2_lsu_stbuf.scala 140:26] + node _T_174 = or(_T_172, _T_173) @[el2_lsu_stbuf.scala 139:103] + node _T_175 = bits(store_matchvec_hi_r, 2, 2) @[el2_lsu_stbuf.scala 140:51] + node _T_176 = or(_T_174, _T_175) @[el2_lsu_stbuf.scala 140:30] + node _T_177 = and(io.ldst_stbuf_reqvld_r, _T_176) @[el2_lsu_stbuf.scala 136:76] + node _T_178 = eq(UInt<2>("h03"), WrPtr) @[el2_lsu_stbuf.scala 137:16] + node _T_179 = eq(store_coalesce_lo_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 137:29] + node _T_180 = and(_T_178, _T_179) @[el2_lsu_stbuf.scala 137:27] + node _T_181 = eq(UInt<2>("h03"), WrPtr) @[el2_lsu_stbuf.scala 138:18] + node _T_182 = and(_T_181, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 138:29] + node _T_183 = eq(store_coalesce_hi_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 138:52] + node _T_184 = and(_T_182, _T_183) @[el2_lsu_stbuf.scala 138:50] + node _T_185 = or(_T_180, _T_184) @[el2_lsu_stbuf.scala 137:51] + node _T_186 = eq(UInt<2>("h03"), WrPtrPlus1) @[el2_lsu_stbuf.scala 139:18] + node _T_187 = and(_T_186, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 139:34] + node _T_188 = or(store_coalesce_lo_r, store_coalesce_hi_r) @[el2_lsu_stbuf.scala 139:79] + node _T_189 = eq(_T_188, UInt<1>("h00")) @[el2_lsu_stbuf.scala 139:57] + node _T_190 = and(_T_187, _T_189) @[el2_lsu_stbuf.scala 139:55] + node _T_191 = or(_T_185, _T_190) @[el2_lsu_stbuf.scala 138:74] + node _T_192 = bits(store_matchvec_lo_r, 3, 3) @[el2_lsu_stbuf.scala 140:26] + node _T_193 = or(_T_191, _T_192) @[el2_lsu_stbuf.scala 139:103] + node _T_194 = bits(store_matchvec_hi_r, 3, 3) @[el2_lsu_stbuf.scala 140:51] + node _T_195 = or(_T_193, _T_194) @[el2_lsu_stbuf.scala 140:30] + node _T_196 = and(io.ldst_stbuf_reqvld_r, _T_195) @[el2_lsu_stbuf.scala 136:76] node _T_197 = cat(_T_196, _T_177) @[Cat.scala 29:58] node _T_198 = cat(_T_197, _T_158) @[Cat.scala 29:58] node _T_199 = cat(_T_198, _T_139) @[Cat.scala 29:58] - stbuf_wr_en <= _T_199 @[el2_lsu_stbuf.scala 137:16] - node _T_200 = or(io.lsu_stbuf_commit_any, io.stbuf_reqvld_flushed_any) @[el2_lsu_stbuf.scala 142:78] - node _T_201 = eq(UInt<1>("h00"), RdPtr) @[el2_lsu_stbuf.scala 142:121] - node _T_202 = bits(_T_201, 0, 0) @[el2_lsu_stbuf.scala 142:132] - node _T_203 = and(_T_200, _T_202) @[el2_lsu_stbuf.scala 142:109] - node _T_204 = or(io.lsu_stbuf_commit_any, io.stbuf_reqvld_flushed_any) @[el2_lsu_stbuf.scala 142:78] - node _T_205 = eq(UInt<1>("h01"), RdPtr) @[el2_lsu_stbuf.scala 142:121] - node _T_206 = bits(_T_205, 0, 0) @[el2_lsu_stbuf.scala 142:132] - node _T_207 = and(_T_204, _T_206) @[el2_lsu_stbuf.scala 142:109] - node _T_208 = or(io.lsu_stbuf_commit_any, io.stbuf_reqvld_flushed_any) @[el2_lsu_stbuf.scala 142:78] - node _T_209 = eq(UInt<2>("h02"), RdPtr) @[el2_lsu_stbuf.scala 142:121] - node _T_210 = bits(_T_209, 0, 0) @[el2_lsu_stbuf.scala 142:132] - node _T_211 = and(_T_208, _T_210) @[el2_lsu_stbuf.scala 142:109] - node _T_212 = or(io.lsu_stbuf_commit_any, io.stbuf_reqvld_flushed_any) @[el2_lsu_stbuf.scala 142:78] - node _T_213 = eq(UInt<2>("h03"), RdPtr) @[el2_lsu_stbuf.scala 142:121] - node _T_214 = bits(_T_213, 0, 0) @[el2_lsu_stbuf.scala 142:132] - node _T_215 = and(_T_212, _T_214) @[el2_lsu_stbuf.scala 142:109] + stbuf_wr_en <= _T_199 @[el2_lsu_stbuf.scala 136:15] + node _T_200 = or(io.lsu_stbuf_commit_any, io.stbuf_reqvld_flushed_any) @[el2_lsu_stbuf.scala 141:78] + node _T_201 = eq(UInt<1>("h00"), RdPtr) @[el2_lsu_stbuf.scala 141:121] + node _T_202 = bits(_T_201, 0, 0) @[el2_lsu_stbuf.scala 141:132] + node _T_203 = and(_T_200, _T_202) @[el2_lsu_stbuf.scala 141:109] + node _T_204 = or(io.lsu_stbuf_commit_any, io.stbuf_reqvld_flushed_any) @[el2_lsu_stbuf.scala 141:78] + node _T_205 = eq(UInt<1>("h01"), RdPtr) @[el2_lsu_stbuf.scala 141:121] + node _T_206 = bits(_T_205, 0, 0) @[el2_lsu_stbuf.scala 141:132] + node _T_207 = and(_T_204, _T_206) @[el2_lsu_stbuf.scala 141:109] + node _T_208 = or(io.lsu_stbuf_commit_any, io.stbuf_reqvld_flushed_any) @[el2_lsu_stbuf.scala 141:78] + node _T_209 = eq(UInt<2>("h02"), RdPtr) @[el2_lsu_stbuf.scala 141:121] + node _T_210 = bits(_T_209, 0, 0) @[el2_lsu_stbuf.scala 141:132] + node _T_211 = and(_T_208, _T_210) @[el2_lsu_stbuf.scala 141:109] + node _T_212 = or(io.lsu_stbuf_commit_any, io.stbuf_reqvld_flushed_any) @[el2_lsu_stbuf.scala 141:78] + node _T_213 = eq(UInt<2>("h03"), RdPtr) @[el2_lsu_stbuf.scala 141:121] + node _T_214 = bits(_T_213, 0, 0) @[el2_lsu_stbuf.scala 141:132] + node _T_215 = and(_T_212, _T_214) @[el2_lsu_stbuf.scala 141:109] node _T_216 = cat(_T_215, _T_211) @[Cat.scala 29:58] node _T_217 = cat(_T_216, _T_207) @[Cat.scala 29:58] node _T_218 = cat(_T_217, _T_203) @[Cat.scala 29:58] - stbuf_reset <= _T_218 @[el2_lsu_stbuf.scala 142:15] - node _T_219 = eq(ldst_dual_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 143:53] - node _T_220 = or(_T_219, io.store_stbuf_reqvld_r) @[el2_lsu_stbuf.scala 143:66] - node _T_221 = eq(UInt<1>("h00"), WrPtr) @[el2_lsu_stbuf.scala 143:105] - node _T_222 = bits(_T_221, 0, 0) @[el2_lsu_stbuf.scala 143:116] - node _T_223 = and(_T_220, _T_222) @[el2_lsu_stbuf.scala 143:93] - node _T_224 = eq(store_coalesce_lo_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 143:125] - node _T_225 = and(_T_223, _T_224) @[el2_lsu_stbuf.scala 143:123] - node _T_226 = bits(store_matchvec_lo_r, 0, 0) @[el2_lsu_stbuf.scala 143:168] - node _T_227 = or(_T_225, _T_226) @[el2_lsu_stbuf.scala 143:147] - node _T_228 = eq(ldst_dual_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 143:53] - node _T_229 = or(_T_228, io.store_stbuf_reqvld_r) @[el2_lsu_stbuf.scala 143:66] - node _T_230 = eq(UInt<1>("h01"), WrPtr) @[el2_lsu_stbuf.scala 143:105] - node _T_231 = bits(_T_230, 0, 0) @[el2_lsu_stbuf.scala 143:116] - node _T_232 = and(_T_229, _T_231) @[el2_lsu_stbuf.scala 143:93] - node _T_233 = eq(store_coalesce_lo_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 143:125] - node _T_234 = and(_T_232, _T_233) @[el2_lsu_stbuf.scala 143:123] - node _T_235 = bits(store_matchvec_lo_r, 1, 1) @[el2_lsu_stbuf.scala 143:168] - node _T_236 = or(_T_234, _T_235) @[el2_lsu_stbuf.scala 143:147] - node _T_237 = eq(ldst_dual_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 143:53] - node _T_238 = or(_T_237, io.store_stbuf_reqvld_r) @[el2_lsu_stbuf.scala 143:66] - node _T_239 = eq(UInt<2>("h02"), WrPtr) @[el2_lsu_stbuf.scala 143:105] - node _T_240 = bits(_T_239, 0, 0) @[el2_lsu_stbuf.scala 143:116] - node _T_241 = and(_T_238, _T_240) @[el2_lsu_stbuf.scala 143:93] - node _T_242 = eq(store_coalesce_lo_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 143:125] - node _T_243 = and(_T_241, _T_242) @[el2_lsu_stbuf.scala 143:123] - node _T_244 = bits(store_matchvec_lo_r, 2, 2) @[el2_lsu_stbuf.scala 143:168] - node _T_245 = or(_T_243, _T_244) @[el2_lsu_stbuf.scala 143:147] - node _T_246 = eq(ldst_dual_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 143:53] - node _T_247 = or(_T_246, io.store_stbuf_reqvld_r) @[el2_lsu_stbuf.scala 143:66] - node _T_248 = eq(UInt<2>("h03"), WrPtr) @[el2_lsu_stbuf.scala 143:105] - node _T_249 = bits(_T_248, 0, 0) @[el2_lsu_stbuf.scala 143:116] - node _T_250 = and(_T_247, _T_249) @[el2_lsu_stbuf.scala 143:93] - node _T_251 = eq(store_coalesce_lo_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 143:125] - node _T_252 = and(_T_250, _T_251) @[el2_lsu_stbuf.scala 143:123] - node _T_253 = bits(store_matchvec_lo_r, 3, 3) @[el2_lsu_stbuf.scala 143:168] - node _T_254 = or(_T_252, _T_253) @[el2_lsu_stbuf.scala 143:147] + stbuf_reset <= _T_218 @[el2_lsu_stbuf.scala 141:15] + node _T_219 = eq(ldst_dual_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 142:53] + node _T_220 = or(_T_219, io.store_stbuf_reqvld_r) @[el2_lsu_stbuf.scala 142:66] + node _T_221 = eq(UInt<1>("h00"), WrPtr) @[el2_lsu_stbuf.scala 142:105] + node _T_222 = bits(_T_221, 0, 0) @[el2_lsu_stbuf.scala 142:116] + node _T_223 = and(_T_220, _T_222) @[el2_lsu_stbuf.scala 142:93] + node _T_224 = eq(store_coalesce_lo_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 142:125] + node _T_225 = and(_T_223, _T_224) @[el2_lsu_stbuf.scala 142:123] + node _T_226 = bits(store_matchvec_lo_r, 0, 0) @[el2_lsu_stbuf.scala 142:168] + node _T_227 = or(_T_225, _T_226) @[el2_lsu_stbuf.scala 142:147] + node _T_228 = eq(ldst_dual_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 142:53] + node _T_229 = or(_T_228, io.store_stbuf_reqvld_r) @[el2_lsu_stbuf.scala 142:66] + node _T_230 = eq(UInt<1>("h01"), WrPtr) @[el2_lsu_stbuf.scala 142:105] + node _T_231 = bits(_T_230, 0, 0) @[el2_lsu_stbuf.scala 142:116] + node _T_232 = and(_T_229, _T_231) @[el2_lsu_stbuf.scala 142:93] + node _T_233 = eq(store_coalesce_lo_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 142:125] + node _T_234 = and(_T_232, _T_233) @[el2_lsu_stbuf.scala 142:123] + node _T_235 = bits(store_matchvec_lo_r, 1, 1) @[el2_lsu_stbuf.scala 142:168] + node _T_236 = or(_T_234, _T_235) @[el2_lsu_stbuf.scala 142:147] + node _T_237 = eq(ldst_dual_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 142:53] + node _T_238 = or(_T_237, io.store_stbuf_reqvld_r) @[el2_lsu_stbuf.scala 142:66] + node _T_239 = eq(UInt<2>("h02"), WrPtr) @[el2_lsu_stbuf.scala 142:105] + node _T_240 = bits(_T_239, 0, 0) @[el2_lsu_stbuf.scala 142:116] + node _T_241 = and(_T_238, _T_240) @[el2_lsu_stbuf.scala 142:93] + node _T_242 = eq(store_coalesce_lo_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 142:125] + node _T_243 = and(_T_241, _T_242) @[el2_lsu_stbuf.scala 142:123] + node _T_244 = bits(store_matchvec_lo_r, 2, 2) @[el2_lsu_stbuf.scala 142:168] + node _T_245 = or(_T_243, _T_244) @[el2_lsu_stbuf.scala 142:147] + node _T_246 = eq(ldst_dual_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 142:53] + node _T_247 = or(_T_246, io.store_stbuf_reqvld_r) @[el2_lsu_stbuf.scala 142:66] + node _T_248 = eq(UInt<2>("h03"), WrPtr) @[el2_lsu_stbuf.scala 142:105] + node _T_249 = bits(_T_248, 0, 0) @[el2_lsu_stbuf.scala 142:116] + node _T_250 = and(_T_247, _T_249) @[el2_lsu_stbuf.scala 142:93] + node _T_251 = eq(store_coalesce_lo_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 142:125] + node _T_252 = and(_T_250, _T_251) @[el2_lsu_stbuf.scala 142:123] + node _T_253 = bits(store_matchvec_lo_r, 3, 3) @[el2_lsu_stbuf.scala 142:168] + node _T_254 = or(_T_252, _T_253) @[el2_lsu_stbuf.scala 142:147] node _T_255 = cat(_T_254, _T_245) @[Cat.scala 29:58] node _T_256 = cat(_T_255, _T_236) @[Cat.scala 29:58] node sel_lo = cat(_T_256, _T_227) @[Cat.scala 29:58] - node _T_257 = bits(sel_lo, 0, 0) @[el2_lsu_stbuf.scala 145:64] - node _T_258 = bits(io.lsu_addr_r, 15, 0) @[el2_lsu_stbuf.scala 145:82] - node _T_259 = bits(io.end_addr_r, 15, 0) @[el2_lsu_stbuf.scala 145:114] - node _T_260 = mux(_T_257, _T_258, _T_259) @[el2_lsu_stbuf.scala 145:57] - node _T_261 = bits(sel_lo, 1, 1) @[el2_lsu_stbuf.scala 145:64] - node _T_262 = bits(io.lsu_addr_r, 15, 0) @[el2_lsu_stbuf.scala 145:82] - node _T_263 = bits(io.end_addr_r, 15, 0) @[el2_lsu_stbuf.scala 145:114] - node _T_264 = mux(_T_261, _T_262, _T_263) @[el2_lsu_stbuf.scala 145:57] - node _T_265 = bits(sel_lo, 2, 2) @[el2_lsu_stbuf.scala 145:64] - node _T_266 = bits(io.lsu_addr_r, 15, 0) @[el2_lsu_stbuf.scala 145:82] - node _T_267 = bits(io.end_addr_r, 15, 0) @[el2_lsu_stbuf.scala 145:114] - node _T_268 = mux(_T_265, _T_266, _T_267) @[el2_lsu_stbuf.scala 145:57] - node _T_269 = bits(sel_lo, 3, 3) @[el2_lsu_stbuf.scala 145:64] - node _T_270 = bits(io.lsu_addr_r, 15, 0) @[el2_lsu_stbuf.scala 145:82] - node _T_271 = bits(io.end_addr_r, 15, 0) @[el2_lsu_stbuf.scala 145:114] - node _T_272 = mux(_T_269, _T_270, _T_271) @[el2_lsu_stbuf.scala 145:57] - stbuf_addrin[0] <= _T_260 @[el2_lsu_stbuf.scala 145:17] - stbuf_addrin[1] <= _T_264 @[el2_lsu_stbuf.scala 145:17] - stbuf_addrin[2] <= _T_268 @[el2_lsu_stbuf.scala 145:17] - stbuf_addrin[3] <= _T_272 @[el2_lsu_stbuf.scala 145:17] - node _T_273 = bits(sel_lo, 0, 0) @[el2_lsu_stbuf.scala 146:66] - node _T_274 = or(stbuf_byteen[0], store_byteen_lo_r) @[el2_lsu_stbuf.scala 146:87] - node _T_275 = or(stbuf_byteen[0], store_byteen_hi_r) @[el2_lsu_stbuf.scala 146:124] - node _T_276 = mux(_T_273, _T_274, _T_275) @[el2_lsu_stbuf.scala 146:59] - node _T_277 = bits(sel_lo, 1, 1) @[el2_lsu_stbuf.scala 146:66] - node _T_278 = or(stbuf_byteen[1], store_byteen_lo_r) @[el2_lsu_stbuf.scala 146:87] - node _T_279 = or(stbuf_byteen[1], store_byteen_hi_r) @[el2_lsu_stbuf.scala 146:124] - node _T_280 = mux(_T_277, _T_278, _T_279) @[el2_lsu_stbuf.scala 146:59] - node _T_281 = bits(sel_lo, 2, 2) @[el2_lsu_stbuf.scala 146:66] - node _T_282 = or(stbuf_byteen[2], store_byteen_lo_r) @[el2_lsu_stbuf.scala 146:87] - node _T_283 = or(stbuf_byteen[2], store_byteen_hi_r) @[el2_lsu_stbuf.scala 146:124] - node _T_284 = mux(_T_281, _T_282, _T_283) @[el2_lsu_stbuf.scala 146:59] - node _T_285 = bits(sel_lo, 3, 3) @[el2_lsu_stbuf.scala 146:66] - node _T_286 = or(stbuf_byteen[3], store_byteen_lo_r) @[el2_lsu_stbuf.scala 146:87] - node _T_287 = or(stbuf_byteen[3], store_byteen_hi_r) @[el2_lsu_stbuf.scala 146:124] - node _T_288 = mux(_T_285, _T_286, _T_287) @[el2_lsu_stbuf.scala 146:59] - stbuf_byteenin[0] <= _T_276 @[el2_lsu_stbuf.scala 146:19] - stbuf_byteenin[1] <= _T_280 @[el2_lsu_stbuf.scala 146:19] - stbuf_byteenin[2] <= _T_284 @[el2_lsu_stbuf.scala 146:19] - stbuf_byteenin[3] <= _T_288 @[el2_lsu_stbuf.scala 146:19] - node _T_289 = bits(sel_lo, 0, 0) @[el2_lsu_stbuf.scala 148:59] - node _T_290 = bits(stbuf_byteen[0], 0, 0) @[el2_lsu_stbuf.scala 148:84] - node _T_291 = eq(_T_290, UInt<1>("h00")) @[el2_lsu_stbuf.scala 148:68] - node _T_292 = bits(store_byteen_lo_r, 0, 0) @[el2_lsu_stbuf.scala 148:107] - node _T_293 = or(_T_291, _T_292) @[el2_lsu_stbuf.scala 148:88] - node _T_294 = bits(io.store_datafn_lo_r, 7, 0) @[el2_lsu_stbuf.scala 148:132] - node _T_295 = bits(stbuf_data[0], 7, 0) @[el2_lsu_stbuf.scala 148:153] - node _T_296 = mux(_T_293, _T_294, _T_295) @[el2_lsu_stbuf.scala 148:67] - node _T_297 = bits(stbuf_byteen[0], 0, 0) @[el2_lsu_stbuf.scala 149:27] - node _T_298 = eq(_T_297, UInt<1>("h00")) @[el2_lsu_stbuf.scala 149:11] - node _T_299 = bits(store_byteen_hi_r, 0, 0) @[el2_lsu_stbuf.scala 149:50] - node _T_300 = or(_T_298, _T_299) @[el2_lsu_stbuf.scala 149:31] - node _T_301 = bits(io.store_datafn_hi_r, 7, 0) @[el2_lsu_stbuf.scala 149:75] - node _T_302 = bits(stbuf_data[0], 7, 0) @[el2_lsu_stbuf.scala 149:96] - node _T_303 = mux(_T_300, _T_301, _T_302) @[el2_lsu_stbuf.scala 149:10] - node _T_304 = mux(_T_289, _T_296, _T_303) @[el2_lsu_stbuf.scala 148:52] - node _T_305 = bits(sel_lo, 1, 1) @[el2_lsu_stbuf.scala 148:59] - node _T_306 = bits(stbuf_byteen[1], 0, 0) @[el2_lsu_stbuf.scala 148:84] - node _T_307 = eq(_T_306, UInt<1>("h00")) @[el2_lsu_stbuf.scala 148:68] - node _T_308 = bits(store_byteen_lo_r, 0, 0) @[el2_lsu_stbuf.scala 148:107] - node _T_309 = or(_T_307, _T_308) @[el2_lsu_stbuf.scala 148:88] - node _T_310 = bits(io.store_datafn_lo_r, 7, 0) @[el2_lsu_stbuf.scala 148:132] - node _T_311 = bits(stbuf_data[1], 7, 0) @[el2_lsu_stbuf.scala 148:153] - node _T_312 = mux(_T_309, _T_310, _T_311) @[el2_lsu_stbuf.scala 148:67] - node _T_313 = bits(stbuf_byteen[1], 0, 0) @[el2_lsu_stbuf.scala 149:27] - node _T_314 = eq(_T_313, UInt<1>("h00")) @[el2_lsu_stbuf.scala 149:11] - node _T_315 = bits(store_byteen_hi_r, 0, 0) @[el2_lsu_stbuf.scala 149:50] - node _T_316 = or(_T_314, _T_315) @[el2_lsu_stbuf.scala 149:31] - node _T_317 = bits(io.store_datafn_hi_r, 7, 0) @[el2_lsu_stbuf.scala 149:75] - node _T_318 = bits(stbuf_data[1], 7, 0) @[el2_lsu_stbuf.scala 149:96] - node _T_319 = mux(_T_316, _T_317, _T_318) @[el2_lsu_stbuf.scala 149:10] - node _T_320 = mux(_T_305, _T_312, _T_319) @[el2_lsu_stbuf.scala 148:52] - node _T_321 = bits(sel_lo, 2, 2) @[el2_lsu_stbuf.scala 148:59] - node _T_322 = bits(stbuf_byteen[2], 0, 0) @[el2_lsu_stbuf.scala 148:84] - node _T_323 = eq(_T_322, UInt<1>("h00")) @[el2_lsu_stbuf.scala 148:68] - node _T_324 = bits(store_byteen_lo_r, 0, 0) @[el2_lsu_stbuf.scala 148:107] - node _T_325 = or(_T_323, _T_324) @[el2_lsu_stbuf.scala 148:88] - node _T_326 = bits(io.store_datafn_lo_r, 7, 0) @[el2_lsu_stbuf.scala 148:132] - node _T_327 = bits(stbuf_data[2], 7, 0) @[el2_lsu_stbuf.scala 148:153] - node _T_328 = mux(_T_325, _T_326, _T_327) @[el2_lsu_stbuf.scala 148:67] - node _T_329 = bits(stbuf_byteen[2], 0, 0) @[el2_lsu_stbuf.scala 149:27] - node _T_330 = eq(_T_329, UInt<1>("h00")) @[el2_lsu_stbuf.scala 149:11] - node _T_331 = bits(store_byteen_hi_r, 0, 0) @[el2_lsu_stbuf.scala 149:50] - node _T_332 = or(_T_330, _T_331) @[el2_lsu_stbuf.scala 149:31] - node _T_333 = bits(io.store_datafn_hi_r, 7, 0) @[el2_lsu_stbuf.scala 149:75] - node _T_334 = bits(stbuf_data[2], 7, 0) @[el2_lsu_stbuf.scala 149:96] - node _T_335 = mux(_T_332, _T_333, _T_334) @[el2_lsu_stbuf.scala 149:10] - node _T_336 = mux(_T_321, _T_328, _T_335) @[el2_lsu_stbuf.scala 148:52] - node _T_337 = bits(sel_lo, 3, 3) @[el2_lsu_stbuf.scala 148:59] - node _T_338 = bits(stbuf_byteen[3], 0, 0) @[el2_lsu_stbuf.scala 148:84] - node _T_339 = eq(_T_338, UInt<1>("h00")) @[el2_lsu_stbuf.scala 148:68] - node _T_340 = bits(store_byteen_lo_r, 0, 0) @[el2_lsu_stbuf.scala 148:107] - node _T_341 = or(_T_339, _T_340) @[el2_lsu_stbuf.scala 148:88] - node _T_342 = bits(io.store_datafn_lo_r, 7, 0) @[el2_lsu_stbuf.scala 148:132] - node _T_343 = bits(stbuf_data[3], 7, 0) @[el2_lsu_stbuf.scala 148:153] - node _T_344 = mux(_T_341, _T_342, _T_343) @[el2_lsu_stbuf.scala 148:67] - node _T_345 = bits(stbuf_byteen[3], 0, 0) @[el2_lsu_stbuf.scala 149:27] - node _T_346 = eq(_T_345, UInt<1>("h00")) @[el2_lsu_stbuf.scala 149:11] - node _T_347 = bits(store_byteen_hi_r, 0, 0) @[el2_lsu_stbuf.scala 149:50] - node _T_348 = or(_T_346, _T_347) @[el2_lsu_stbuf.scala 149:31] - node _T_349 = bits(io.store_datafn_hi_r, 7, 0) @[el2_lsu_stbuf.scala 149:75] - node _T_350 = bits(stbuf_data[3], 7, 0) @[el2_lsu_stbuf.scala 149:96] - node _T_351 = mux(_T_348, _T_349, _T_350) @[el2_lsu_stbuf.scala 149:10] - node _T_352 = mux(_T_337, _T_344, _T_351) @[el2_lsu_stbuf.scala 148:52] - datain1[0] <= _T_304 @[el2_lsu_stbuf.scala 148:12] - datain1[1] <= _T_320 @[el2_lsu_stbuf.scala 148:12] - datain1[2] <= _T_336 @[el2_lsu_stbuf.scala 148:12] - datain1[3] <= _T_352 @[el2_lsu_stbuf.scala 148:12] - node _T_353 = bits(sel_lo, 0, 0) @[el2_lsu_stbuf.scala 151:60] - node _T_354 = bits(stbuf_byteen[0], 1, 1) @[el2_lsu_stbuf.scala 151:85] - node _T_355 = eq(_T_354, UInt<1>("h00")) @[el2_lsu_stbuf.scala 151:69] - node _T_356 = bits(store_byteen_lo_r, 1, 1) @[el2_lsu_stbuf.scala 151:108] - node _T_357 = or(_T_355, _T_356) @[el2_lsu_stbuf.scala 151:89] - node _T_358 = bits(io.store_datafn_lo_r, 15, 8) @[el2_lsu_stbuf.scala 151:133] - node _T_359 = bits(stbuf_data[0], 15, 8) @[el2_lsu_stbuf.scala 151:155] - node _T_360 = mux(_T_357, _T_358, _T_359) @[el2_lsu_stbuf.scala 151:68] - node _T_361 = bits(stbuf_byteen[0], 1, 1) @[el2_lsu_stbuf.scala 152:27] - node _T_362 = eq(_T_361, UInt<1>("h00")) @[el2_lsu_stbuf.scala 152:11] - node _T_363 = bits(store_byteen_hi_r, 1, 1) @[el2_lsu_stbuf.scala 152:50] - node _T_364 = or(_T_362, _T_363) @[el2_lsu_stbuf.scala 152:31] - node _T_365 = bits(io.store_datafn_hi_r, 15, 8) @[el2_lsu_stbuf.scala 152:75] - node _T_366 = bits(stbuf_data[0], 15, 8) @[el2_lsu_stbuf.scala 152:97] - node _T_367 = mux(_T_364, _T_365, _T_366) @[el2_lsu_stbuf.scala 152:10] - node _T_368 = mux(_T_353, _T_360, _T_367) @[el2_lsu_stbuf.scala 151:53] - node _T_369 = bits(sel_lo, 1, 1) @[el2_lsu_stbuf.scala 151:60] - node _T_370 = bits(stbuf_byteen[1], 1, 1) @[el2_lsu_stbuf.scala 151:85] - node _T_371 = eq(_T_370, UInt<1>("h00")) @[el2_lsu_stbuf.scala 151:69] - node _T_372 = bits(store_byteen_lo_r, 1, 1) @[el2_lsu_stbuf.scala 151:108] - node _T_373 = or(_T_371, _T_372) @[el2_lsu_stbuf.scala 151:89] - node _T_374 = bits(io.store_datafn_lo_r, 15, 8) @[el2_lsu_stbuf.scala 151:133] - node _T_375 = bits(stbuf_data[1], 15, 8) @[el2_lsu_stbuf.scala 151:155] - node _T_376 = mux(_T_373, _T_374, _T_375) @[el2_lsu_stbuf.scala 151:68] - node _T_377 = bits(stbuf_byteen[1], 1, 1) @[el2_lsu_stbuf.scala 152:27] - node _T_378 = eq(_T_377, UInt<1>("h00")) @[el2_lsu_stbuf.scala 152:11] - node _T_379 = bits(store_byteen_hi_r, 1, 1) @[el2_lsu_stbuf.scala 152:50] - node _T_380 = or(_T_378, _T_379) @[el2_lsu_stbuf.scala 152:31] - node _T_381 = bits(io.store_datafn_hi_r, 15, 8) @[el2_lsu_stbuf.scala 152:75] - node _T_382 = bits(stbuf_data[1], 15, 8) @[el2_lsu_stbuf.scala 152:97] - node _T_383 = mux(_T_380, _T_381, _T_382) @[el2_lsu_stbuf.scala 152:10] - node _T_384 = mux(_T_369, _T_376, _T_383) @[el2_lsu_stbuf.scala 151:53] - node _T_385 = bits(sel_lo, 2, 2) @[el2_lsu_stbuf.scala 151:60] - node _T_386 = bits(stbuf_byteen[2], 1, 1) @[el2_lsu_stbuf.scala 151:85] - node _T_387 = eq(_T_386, UInt<1>("h00")) @[el2_lsu_stbuf.scala 151:69] - node _T_388 = bits(store_byteen_lo_r, 1, 1) @[el2_lsu_stbuf.scala 151:108] - node _T_389 = or(_T_387, _T_388) @[el2_lsu_stbuf.scala 151:89] - node _T_390 = bits(io.store_datafn_lo_r, 15, 8) @[el2_lsu_stbuf.scala 151:133] - node _T_391 = bits(stbuf_data[2], 15, 8) @[el2_lsu_stbuf.scala 151:155] - node _T_392 = mux(_T_389, _T_390, _T_391) @[el2_lsu_stbuf.scala 151:68] - node _T_393 = bits(stbuf_byteen[2], 1, 1) @[el2_lsu_stbuf.scala 152:27] - node _T_394 = eq(_T_393, UInt<1>("h00")) @[el2_lsu_stbuf.scala 152:11] - node _T_395 = bits(store_byteen_hi_r, 1, 1) @[el2_lsu_stbuf.scala 152:50] - node _T_396 = or(_T_394, _T_395) @[el2_lsu_stbuf.scala 152:31] - node _T_397 = bits(io.store_datafn_hi_r, 15, 8) @[el2_lsu_stbuf.scala 152:75] - node _T_398 = bits(stbuf_data[2], 15, 8) @[el2_lsu_stbuf.scala 152:97] - node _T_399 = mux(_T_396, _T_397, _T_398) @[el2_lsu_stbuf.scala 152:10] - node _T_400 = mux(_T_385, _T_392, _T_399) @[el2_lsu_stbuf.scala 151:53] - node _T_401 = bits(sel_lo, 3, 3) @[el2_lsu_stbuf.scala 151:60] - node _T_402 = bits(stbuf_byteen[3], 1, 1) @[el2_lsu_stbuf.scala 151:85] - node _T_403 = eq(_T_402, UInt<1>("h00")) @[el2_lsu_stbuf.scala 151:69] - node _T_404 = bits(store_byteen_lo_r, 1, 1) @[el2_lsu_stbuf.scala 151:108] - node _T_405 = or(_T_403, _T_404) @[el2_lsu_stbuf.scala 151:89] - node _T_406 = bits(io.store_datafn_lo_r, 15, 8) @[el2_lsu_stbuf.scala 151:133] - node _T_407 = bits(stbuf_data[3], 15, 8) @[el2_lsu_stbuf.scala 151:155] - node _T_408 = mux(_T_405, _T_406, _T_407) @[el2_lsu_stbuf.scala 151:68] - node _T_409 = bits(stbuf_byteen[3], 1, 1) @[el2_lsu_stbuf.scala 152:27] - node _T_410 = eq(_T_409, UInt<1>("h00")) @[el2_lsu_stbuf.scala 152:11] - node _T_411 = bits(store_byteen_hi_r, 1, 1) @[el2_lsu_stbuf.scala 152:50] - node _T_412 = or(_T_410, _T_411) @[el2_lsu_stbuf.scala 152:31] - node _T_413 = bits(io.store_datafn_hi_r, 15, 8) @[el2_lsu_stbuf.scala 152:75] - node _T_414 = bits(stbuf_data[3], 15, 8) @[el2_lsu_stbuf.scala 152:97] - node _T_415 = mux(_T_412, _T_413, _T_414) @[el2_lsu_stbuf.scala 152:10] - node _T_416 = mux(_T_401, _T_408, _T_415) @[el2_lsu_stbuf.scala 151:53] - datain2[0] <= _T_368 @[el2_lsu_stbuf.scala 151:13] - datain2[1] <= _T_384 @[el2_lsu_stbuf.scala 151:13] - datain2[2] <= _T_400 @[el2_lsu_stbuf.scala 151:13] - datain2[3] <= _T_416 @[el2_lsu_stbuf.scala 151:13] - node _T_417 = bits(sel_lo, 0, 0) @[el2_lsu_stbuf.scala 154:60] - node _T_418 = bits(stbuf_byteen[0], 2, 2) @[el2_lsu_stbuf.scala 154:85] - node _T_419 = eq(_T_418, UInt<1>("h00")) @[el2_lsu_stbuf.scala 154:69] - node _T_420 = bits(store_byteen_lo_r, 2, 2) @[el2_lsu_stbuf.scala 154:108] - node _T_421 = or(_T_419, _T_420) @[el2_lsu_stbuf.scala 154:89] - node _T_422 = bits(io.store_datafn_lo_r, 23, 16) @[el2_lsu_stbuf.scala 154:133] - node _T_423 = bits(stbuf_data[0], 23, 16) @[el2_lsu_stbuf.scala 154:156] - node _T_424 = mux(_T_421, _T_422, _T_423) @[el2_lsu_stbuf.scala 154:68] - node _T_425 = bits(stbuf_byteen[0], 2, 2) @[el2_lsu_stbuf.scala 155:27] - node _T_426 = eq(_T_425, UInt<1>("h00")) @[el2_lsu_stbuf.scala 155:11] - node _T_427 = bits(store_byteen_hi_r, 2, 2) @[el2_lsu_stbuf.scala 155:50] - node _T_428 = or(_T_426, _T_427) @[el2_lsu_stbuf.scala 155:31] - node _T_429 = bits(io.store_datafn_hi_r, 23, 16) @[el2_lsu_stbuf.scala 155:75] - node _T_430 = bits(stbuf_data[0], 23, 16) @[el2_lsu_stbuf.scala 155:98] - node _T_431 = mux(_T_428, _T_429, _T_430) @[el2_lsu_stbuf.scala 155:10] - node _T_432 = mux(_T_417, _T_424, _T_431) @[el2_lsu_stbuf.scala 154:53] - node _T_433 = bits(sel_lo, 1, 1) @[el2_lsu_stbuf.scala 154:60] - node _T_434 = bits(stbuf_byteen[1], 2, 2) @[el2_lsu_stbuf.scala 154:85] - node _T_435 = eq(_T_434, UInt<1>("h00")) @[el2_lsu_stbuf.scala 154:69] - node _T_436 = bits(store_byteen_lo_r, 2, 2) @[el2_lsu_stbuf.scala 154:108] - node _T_437 = or(_T_435, _T_436) @[el2_lsu_stbuf.scala 154:89] - node _T_438 = bits(io.store_datafn_lo_r, 23, 16) @[el2_lsu_stbuf.scala 154:133] - node _T_439 = bits(stbuf_data[1], 23, 16) @[el2_lsu_stbuf.scala 154:156] - node _T_440 = mux(_T_437, _T_438, _T_439) @[el2_lsu_stbuf.scala 154:68] - node _T_441 = bits(stbuf_byteen[1], 2, 2) @[el2_lsu_stbuf.scala 155:27] - node _T_442 = eq(_T_441, UInt<1>("h00")) @[el2_lsu_stbuf.scala 155:11] - node _T_443 = bits(store_byteen_hi_r, 2, 2) @[el2_lsu_stbuf.scala 155:50] - node _T_444 = or(_T_442, _T_443) @[el2_lsu_stbuf.scala 155:31] - node _T_445 = bits(io.store_datafn_hi_r, 23, 16) @[el2_lsu_stbuf.scala 155:75] - node _T_446 = bits(stbuf_data[1], 23, 16) @[el2_lsu_stbuf.scala 155:98] - node _T_447 = mux(_T_444, _T_445, _T_446) @[el2_lsu_stbuf.scala 155:10] - node _T_448 = mux(_T_433, _T_440, _T_447) @[el2_lsu_stbuf.scala 154:53] - node _T_449 = bits(sel_lo, 2, 2) @[el2_lsu_stbuf.scala 154:60] - node _T_450 = bits(stbuf_byteen[2], 2, 2) @[el2_lsu_stbuf.scala 154:85] - node _T_451 = eq(_T_450, UInt<1>("h00")) @[el2_lsu_stbuf.scala 154:69] - node _T_452 = bits(store_byteen_lo_r, 2, 2) @[el2_lsu_stbuf.scala 154:108] - node _T_453 = or(_T_451, _T_452) @[el2_lsu_stbuf.scala 154:89] - node _T_454 = bits(io.store_datafn_lo_r, 23, 16) @[el2_lsu_stbuf.scala 154:133] - node _T_455 = bits(stbuf_data[2], 23, 16) @[el2_lsu_stbuf.scala 154:156] - node _T_456 = mux(_T_453, _T_454, _T_455) @[el2_lsu_stbuf.scala 154:68] - node _T_457 = bits(stbuf_byteen[2], 2, 2) @[el2_lsu_stbuf.scala 155:27] - node _T_458 = eq(_T_457, UInt<1>("h00")) @[el2_lsu_stbuf.scala 155:11] - node _T_459 = bits(store_byteen_hi_r, 2, 2) @[el2_lsu_stbuf.scala 155:50] - node _T_460 = or(_T_458, _T_459) @[el2_lsu_stbuf.scala 155:31] - node _T_461 = bits(io.store_datafn_hi_r, 23, 16) @[el2_lsu_stbuf.scala 155:75] - node _T_462 = bits(stbuf_data[2], 23, 16) @[el2_lsu_stbuf.scala 155:98] - node _T_463 = mux(_T_460, _T_461, _T_462) @[el2_lsu_stbuf.scala 155:10] - node _T_464 = mux(_T_449, _T_456, _T_463) @[el2_lsu_stbuf.scala 154:53] - node _T_465 = bits(sel_lo, 3, 3) @[el2_lsu_stbuf.scala 154:60] - node _T_466 = bits(stbuf_byteen[3], 2, 2) @[el2_lsu_stbuf.scala 154:85] - node _T_467 = eq(_T_466, UInt<1>("h00")) @[el2_lsu_stbuf.scala 154:69] - node _T_468 = bits(store_byteen_lo_r, 2, 2) @[el2_lsu_stbuf.scala 154:108] - node _T_469 = or(_T_467, _T_468) @[el2_lsu_stbuf.scala 154:89] - node _T_470 = bits(io.store_datafn_lo_r, 23, 16) @[el2_lsu_stbuf.scala 154:133] - node _T_471 = bits(stbuf_data[3], 23, 16) @[el2_lsu_stbuf.scala 154:156] - node _T_472 = mux(_T_469, _T_470, _T_471) @[el2_lsu_stbuf.scala 154:68] - node _T_473 = bits(stbuf_byteen[3], 2, 2) @[el2_lsu_stbuf.scala 155:27] - node _T_474 = eq(_T_473, UInt<1>("h00")) @[el2_lsu_stbuf.scala 155:11] - node _T_475 = bits(store_byteen_hi_r, 2, 2) @[el2_lsu_stbuf.scala 155:50] - node _T_476 = or(_T_474, _T_475) @[el2_lsu_stbuf.scala 155:31] - node _T_477 = bits(io.store_datafn_hi_r, 23, 16) @[el2_lsu_stbuf.scala 155:75] - node _T_478 = bits(stbuf_data[3], 23, 16) @[el2_lsu_stbuf.scala 155:98] - node _T_479 = mux(_T_476, _T_477, _T_478) @[el2_lsu_stbuf.scala 155:10] - node _T_480 = mux(_T_465, _T_472, _T_479) @[el2_lsu_stbuf.scala 154:53] - datain3[0] <= _T_432 @[el2_lsu_stbuf.scala 154:13] - datain3[1] <= _T_448 @[el2_lsu_stbuf.scala 154:13] - datain3[2] <= _T_464 @[el2_lsu_stbuf.scala 154:13] - datain3[3] <= _T_480 @[el2_lsu_stbuf.scala 154:13] - node _T_481 = bits(sel_lo, 0, 0) @[el2_lsu_stbuf.scala 157:60] - node _T_482 = bits(stbuf_byteen[0], 3, 3) @[el2_lsu_stbuf.scala 157:85] - node _T_483 = eq(_T_482, UInt<1>("h00")) @[el2_lsu_stbuf.scala 157:69] - node _T_484 = bits(store_byteen_lo_r, 3, 3) @[el2_lsu_stbuf.scala 157:108] - node _T_485 = or(_T_483, _T_484) @[el2_lsu_stbuf.scala 157:89] - node _T_486 = bits(io.store_datafn_lo_r, 31, 24) @[el2_lsu_stbuf.scala 157:133] - node _T_487 = bits(stbuf_data[0], 31, 24) @[el2_lsu_stbuf.scala 157:156] - node _T_488 = mux(_T_485, _T_486, _T_487) @[el2_lsu_stbuf.scala 157:68] - node _T_489 = bits(stbuf_byteen[0], 3, 3) @[el2_lsu_stbuf.scala 158:27] - node _T_490 = eq(_T_489, UInt<1>("h00")) @[el2_lsu_stbuf.scala 158:11] - node _T_491 = bits(store_byteen_hi_r, 3, 3) @[el2_lsu_stbuf.scala 158:50] - node _T_492 = or(_T_490, _T_491) @[el2_lsu_stbuf.scala 158:31] - node _T_493 = bits(io.store_datafn_hi_r, 31, 24) @[el2_lsu_stbuf.scala 158:75] - node _T_494 = bits(stbuf_data[0], 31, 24) @[el2_lsu_stbuf.scala 158:98] - node _T_495 = mux(_T_492, _T_493, _T_494) @[el2_lsu_stbuf.scala 158:10] - node _T_496 = mux(_T_481, _T_488, _T_495) @[el2_lsu_stbuf.scala 157:53] - node _T_497 = bits(sel_lo, 1, 1) @[el2_lsu_stbuf.scala 157:60] - node _T_498 = bits(stbuf_byteen[1], 3, 3) @[el2_lsu_stbuf.scala 157:85] - node _T_499 = eq(_T_498, UInt<1>("h00")) @[el2_lsu_stbuf.scala 157:69] - node _T_500 = bits(store_byteen_lo_r, 3, 3) @[el2_lsu_stbuf.scala 157:108] - node _T_501 = or(_T_499, _T_500) @[el2_lsu_stbuf.scala 157:89] - node _T_502 = bits(io.store_datafn_lo_r, 31, 24) @[el2_lsu_stbuf.scala 157:133] - node _T_503 = bits(stbuf_data[1], 31, 24) @[el2_lsu_stbuf.scala 157:156] - node _T_504 = mux(_T_501, _T_502, _T_503) @[el2_lsu_stbuf.scala 157:68] - node _T_505 = bits(stbuf_byteen[1], 3, 3) @[el2_lsu_stbuf.scala 158:27] - node _T_506 = eq(_T_505, UInt<1>("h00")) @[el2_lsu_stbuf.scala 158:11] - node _T_507 = bits(store_byteen_hi_r, 3, 3) @[el2_lsu_stbuf.scala 158:50] - node _T_508 = or(_T_506, _T_507) @[el2_lsu_stbuf.scala 158:31] - node _T_509 = bits(io.store_datafn_hi_r, 31, 24) @[el2_lsu_stbuf.scala 158:75] - node _T_510 = bits(stbuf_data[1], 31, 24) @[el2_lsu_stbuf.scala 158:98] - node _T_511 = mux(_T_508, _T_509, _T_510) @[el2_lsu_stbuf.scala 158:10] - node _T_512 = mux(_T_497, _T_504, _T_511) @[el2_lsu_stbuf.scala 157:53] - node _T_513 = bits(sel_lo, 2, 2) @[el2_lsu_stbuf.scala 157:60] - node _T_514 = bits(stbuf_byteen[2], 3, 3) @[el2_lsu_stbuf.scala 157:85] - node _T_515 = eq(_T_514, UInt<1>("h00")) @[el2_lsu_stbuf.scala 157:69] - node _T_516 = bits(store_byteen_lo_r, 3, 3) @[el2_lsu_stbuf.scala 157:108] - node _T_517 = or(_T_515, _T_516) @[el2_lsu_stbuf.scala 157:89] - node _T_518 = bits(io.store_datafn_lo_r, 31, 24) @[el2_lsu_stbuf.scala 157:133] - node _T_519 = bits(stbuf_data[2], 31, 24) @[el2_lsu_stbuf.scala 157:156] - node _T_520 = mux(_T_517, _T_518, _T_519) @[el2_lsu_stbuf.scala 157:68] - node _T_521 = bits(stbuf_byteen[2], 3, 3) @[el2_lsu_stbuf.scala 158:27] - node _T_522 = eq(_T_521, UInt<1>("h00")) @[el2_lsu_stbuf.scala 158:11] - node _T_523 = bits(store_byteen_hi_r, 3, 3) @[el2_lsu_stbuf.scala 158:50] - node _T_524 = or(_T_522, _T_523) @[el2_lsu_stbuf.scala 158:31] - node _T_525 = bits(io.store_datafn_hi_r, 31, 24) @[el2_lsu_stbuf.scala 158:75] - node _T_526 = bits(stbuf_data[2], 31, 24) @[el2_lsu_stbuf.scala 158:98] - node _T_527 = mux(_T_524, _T_525, _T_526) @[el2_lsu_stbuf.scala 158:10] - node _T_528 = mux(_T_513, _T_520, _T_527) @[el2_lsu_stbuf.scala 157:53] - node _T_529 = bits(sel_lo, 3, 3) @[el2_lsu_stbuf.scala 157:60] - node _T_530 = bits(stbuf_byteen[3], 3, 3) @[el2_lsu_stbuf.scala 157:85] - node _T_531 = eq(_T_530, UInt<1>("h00")) @[el2_lsu_stbuf.scala 157:69] - node _T_532 = bits(store_byteen_lo_r, 3, 3) @[el2_lsu_stbuf.scala 157:108] - node _T_533 = or(_T_531, _T_532) @[el2_lsu_stbuf.scala 157:89] - node _T_534 = bits(io.store_datafn_lo_r, 31, 24) @[el2_lsu_stbuf.scala 157:133] - node _T_535 = bits(stbuf_data[3], 31, 24) @[el2_lsu_stbuf.scala 157:156] - node _T_536 = mux(_T_533, _T_534, _T_535) @[el2_lsu_stbuf.scala 157:68] - node _T_537 = bits(stbuf_byteen[3], 3, 3) @[el2_lsu_stbuf.scala 158:27] - node _T_538 = eq(_T_537, UInt<1>("h00")) @[el2_lsu_stbuf.scala 158:11] - node _T_539 = bits(store_byteen_hi_r, 3, 3) @[el2_lsu_stbuf.scala 158:50] - node _T_540 = or(_T_538, _T_539) @[el2_lsu_stbuf.scala 158:31] - node _T_541 = bits(io.store_datafn_hi_r, 31, 24) @[el2_lsu_stbuf.scala 158:75] - node _T_542 = bits(stbuf_data[3], 31, 24) @[el2_lsu_stbuf.scala 158:98] - node _T_543 = mux(_T_540, _T_541, _T_542) @[el2_lsu_stbuf.scala 158:10] - node _T_544 = mux(_T_529, _T_536, _T_543) @[el2_lsu_stbuf.scala 157:53] - datain4[0] <= _T_496 @[el2_lsu_stbuf.scala 157:13] - datain4[1] <= _T_512 @[el2_lsu_stbuf.scala 157:13] - datain4[2] <= _T_528 @[el2_lsu_stbuf.scala 157:13] - datain4[3] <= _T_544 @[el2_lsu_stbuf.scala 157:13] + node _T_257 = bits(sel_lo, 0, 0) @[el2_lsu_stbuf.scala 144:63] + node _T_258 = bits(io.lsu_addr_r, 15, 0) @[el2_lsu_stbuf.scala 144:81] + node _T_259 = bits(io.end_addr_r, 15, 0) @[el2_lsu_stbuf.scala 144:113] + node _T_260 = mux(_T_257, _T_258, _T_259) @[el2_lsu_stbuf.scala 144:56] + node _T_261 = bits(sel_lo, 1, 1) @[el2_lsu_stbuf.scala 144:63] + node _T_262 = bits(io.lsu_addr_r, 15, 0) @[el2_lsu_stbuf.scala 144:81] + node _T_263 = bits(io.end_addr_r, 15, 0) @[el2_lsu_stbuf.scala 144:113] + node _T_264 = mux(_T_261, _T_262, _T_263) @[el2_lsu_stbuf.scala 144:56] + node _T_265 = bits(sel_lo, 2, 2) @[el2_lsu_stbuf.scala 144:63] + node _T_266 = bits(io.lsu_addr_r, 15, 0) @[el2_lsu_stbuf.scala 144:81] + node _T_267 = bits(io.end_addr_r, 15, 0) @[el2_lsu_stbuf.scala 144:113] + node _T_268 = mux(_T_265, _T_266, _T_267) @[el2_lsu_stbuf.scala 144:56] + node _T_269 = bits(sel_lo, 3, 3) @[el2_lsu_stbuf.scala 144:63] + node _T_270 = bits(io.lsu_addr_r, 15, 0) @[el2_lsu_stbuf.scala 144:81] + node _T_271 = bits(io.end_addr_r, 15, 0) @[el2_lsu_stbuf.scala 144:113] + node _T_272 = mux(_T_269, _T_270, _T_271) @[el2_lsu_stbuf.scala 144:56] + stbuf_addrin[0] <= _T_260 @[el2_lsu_stbuf.scala 144:16] + stbuf_addrin[1] <= _T_264 @[el2_lsu_stbuf.scala 144:16] + stbuf_addrin[2] <= _T_268 @[el2_lsu_stbuf.scala 144:16] + stbuf_addrin[3] <= _T_272 @[el2_lsu_stbuf.scala 144:16] + node _T_273 = bits(sel_lo, 0, 0) @[el2_lsu_stbuf.scala 145:65] + node _T_274 = or(stbuf_byteen[0], store_byteen_lo_r) @[el2_lsu_stbuf.scala 145:86] + node _T_275 = or(stbuf_byteen[0], store_byteen_hi_r) @[el2_lsu_stbuf.scala 145:123] + node _T_276 = mux(_T_273, _T_274, _T_275) @[el2_lsu_stbuf.scala 145:58] + node _T_277 = bits(sel_lo, 1, 1) @[el2_lsu_stbuf.scala 145:65] + node _T_278 = or(stbuf_byteen[1], store_byteen_lo_r) @[el2_lsu_stbuf.scala 145:86] + node _T_279 = or(stbuf_byteen[1], store_byteen_hi_r) @[el2_lsu_stbuf.scala 145:123] + node _T_280 = mux(_T_277, _T_278, _T_279) @[el2_lsu_stbuf.scala 145:58] + node _T_281 = bits(sel_lo, 2, 2) @[el2_lsu_stbuf.scala 145:65] + node _T_282 = or(stbuf_byteen[2], store_byteen_lo_r) @[el2_lsu_stbuf.scala 145:86] + node _T_283 = or(stbuf_byteen[2], store_byteen_hi_r) @[el2_lsu_stbuf.scala 145:123] + node _T_284 = mux(_T_281, _T_282, _T_283) @[el2_lsu_stbuf.scala 145:58] + node _T_285 = bits(sel_lo, 3, 3) @[el2_lsu_stbuf.scala 145:65] + node _T_286 = or(stbuf_byteen[3], store_byteen_lo_r) @[el2_lsu_stbuf.scala 145:86] + node _T_287 = or(stbuf_byteen[3], store_byteen_hi_r) @[el2_lsu_stbuf.scala 145:123] + node _T_288 = mux(_T_285, _T_286, _T_287) @[el2_lsu_stbuf.scala 145:58] + stbuf_byteenin[0] <= _T_276 @[el2_lsu_stbuf.scala 145:18] + stbuf_byteenin[1] <= _T_280 @[el2_lsu_stbuf.scala 145:18] + stbuf_byteenin[2] <= _T_284 @[el2_lsu_stbuf.scala 145:18] + stbuf_byteenin[3] <= _T_288 @[el2_lsu_stbuf.scala 145:18] + node _T_289 = bits(sel_lo, 0, 0) @[el2_lsu_stbuf.scala 147:58] + node _T_290 = bits(stbuf_byteen[0], 0, 0) @[el2_lsu_stbuf.scala 147:83] + node _T_291 = eq(_T_290, UInt<1>("h00")) @[el2_lsu_stbuf.scala 147:67] + node _T_292 = bits(store_byteen_lo_r, 0, 0) @[el2_lsu_stbuf.scala 147:106] + node _T_293 = or(_T_291, _T_292) @[el2_lsu_stbuf.scala 147:87] + node _T_294 = bits(io.store_datafn_lo_r, 7, 0) @[el2_lsu_stbuf.scala 147:131] + node _T_295 = bits(stbuf_data[0], 7, 0) @[el2_lsu_stbuf.scala 147:152] + node _T_296 = mux(_T_293, _T_294, _T_295) @[el2_lsu_stbuf.scala 147:66] + node _T_297 = bits(stbuf_byteen[0], 0, 0) @[el2_lsu_stbuf.scala 148:25] + node _T_298 = eq(_T_297, UInt<1>("h00")) @[el2_lsu_stbuf.scala 148:9] + node _T_299 = bits(store_byteen_hi_r, 0, 0) @[el2_lsu_stbuf.scala 148:48] + node _T_300 = or(_T_298, _T_299) @[el2_lsu_stbuf.scala 148:29] + node _T_301 = bits(io.store_datafn_hi_r, 7, 0) @[el2_lsu_stbuf.scala 148:73] + node _T_302 = bits(stbuf_data[0], 7, 0) @[el2_lsu_stbuf.scala 148:94] + node _T_303 = mux(_T_300, _T_301, _T_302) @[el2_lsu_stbuf.scala 148:8] + node _T_304 = mux(_T_289, _T_296, _T_303) @[el2_lsu_stbuf.scala 147:51] + node _T_305 = bits(sel_lo, 1, 1) @[el2_lsu_stbuf.scala 147:58] + node _T_306 = bits(stbuf_byteen[1], 0, 0) @[el2_lsu_stbuf.scala 147:83] + node _T_307 = eq(_T_306, UInt<1>("h00")) @[el2_lsu_stbuf.scala 147:67] + node _T_308 = bits(store_byteen_lo_r, 0, 0) @[el2_lsu_stbuf.scala 147:106] + node _T_309 = or(_T_307, _T_308) @[el2_lsu_stbuf.scala 147:87] + node _T_310 = bits(io.store_datafn_lo_r, 7, 0) @[el2_lsu_stbuf.scala 147:131] + node _T_311 = bits(stbuf_data[1], 7, 0) @[el2_lsu_stbuf.scala 147:152] + node _T_312 = mux(_T_309, _T_310, _T_311) @[el2_lsu_stbuf.scala 147:66] + node _T_313 = bits(stbuf_byteen[1], 0, 0) @[el2_lsu_stbuf.scala 148:25] + node _T_314 = eq(_T_313, UInt<1>("h00")) @[el2_lsu_stbuf.scala 148:9] + node _T_315 = bits(store_byteen_hi_r, 0, 0) @[el2_lsu_stbuf.scala 148:48] + node _T_316 = or(_T_314, _T_315) @[el2_lsu_stbuf.scala 148:29] + node _T_317 = bits(io.store_datafn_hi_r, 7, 0) @[el2_lsu_stbuf.scala 148:73] + node _T_318 = bits(stbuf_data[1], 7, 0) @[el2_lsu_stbuf.scala 148:94] + node _T_319 = mux(_T_316, _T_317, _T_318) @[el2_lsu_stbuf.scala 148:8] + node _T_320 = mux(_T_305, _T_312, _T_319) @[el2_lsu_stbuf.scala 147:51] + node _T_321 = bits(sel_lo, 2, 2) @[el2_lsu_stbuf.scala 147:58] + node _T_322 = bits(stbuf_byteen[2], 0, 0) @[el2_lsu_stbuf.scala 147:83] + node _T_323 = eq(_T_322, UInt<1>("h00")) @[el2_lsu_stbuf.scala 147:67] + node _T_324 = bits(store_byteen_lo_r, 0, 0) @[el2_lsu_stbuf.scala 147:106] + node _T_325 = or(_T_323, _T_324) @[el2_lsu_stbuf.scala 147:87] + node _T_326 = bits(io.store_datafn_lo_r, 7, 0) @[el2_lsu_stbuf.scala 147:131] + node _T_327 = bits(stbuf_data[2], 7, 0) @[el2_lsu_stbuf.scala 147:152] + node _T_328 = mux(_T_325, _T_326, _T_327) @[el2_lsu_stbuf.scala 147:66] + node _T_329 = bits(stbuf_byteen[2], 0, 0) @[el2_lsu_stbuf.scala 148:25] + node _T_330 = eq(_T_329, UInt<1>("h00")) @[el2_lsu_stbuf.scala 148:9] + node _T_331 = bits(store_byteen_hi_r, 0, 0) @[el2_lsu_stbuf.scala 148:48] + node _T_332 = or(_T_330, _T_331) @[el2_lsu_stbuf.scala 148:29] + node _T_333 = bits(io.store_datafn_hi_r, 7, 0) @[el2_lsu_stbuf.scala 148:73] + node _T_334 = bits(stbuf_data[2], 7, 0) @[el2_lsu_stbuf.scala 148:94] + node _T_335 = mux(_T_332, _T_333, _T_334) @[el2_lsu_stbuf.scala 148:8] + node _T_336 = mux(_T_321, _T_328, _T_335) @[el2_lsu_stbuf.scala 147:51] + node _T_337 = bits(sel_lo, 3, 3) @[el2_lsu_stbuf.scala 147:58] + node _T_338 = bits(stbuf_byteen[3], 0, 0) @[el2_lsu_stbuf.scala 147:83] + node _T_339 = eq(_T_338, UInt<1>("h00")) @[el2_lsu_stbuf.scala 147:67] + node _T_340 = bits(store_byteen_lo_r, 0, 0) @[el2_lsu_stbuf.scala 147:106] + node _T_341 = or(_T_339, _T_340) @[el2_lsu_stbuf.scala 147:87] + node _T_342 = bits(io.store_datafn_lo_r, 7, 0) @[el2_lsu_stbuf.scala 147:131] + node _T_343 = bits(stbuf_data[3], 7, 0) @[el2_lsu_stbuf.scala 147:152] + node _T_344 = mux(_T_341, _T_342, _T_343) @[el2_lsu_stbuf.scala 147:66] + node _T_345 = bits(stbuf_byteen[3], 0, 0) @[el2_lsu_stbuf.scala 148:25] + node _T_346 = eq(_T_345, UInt<1>("h00")) @[el2_lsu_stbuf.scala 148:9] + node _T_347 = bits(store_byteen_hi_r, 0, 0) @[el2_lsu_stbuf.scala 148:48] + node _T_348 = or(_T_346, _T_347) @[el2_lsu_stbuf.scala 148:29] + node _T_349 = bits(io.store_datafn_hi_r, 7, 0) @[el2_lsu_stbuf.scala 148:73] + node _T_350 = bits(stbuf_data[3], 7, 0) @[el2_lsu_stbuf.scala 148:94] + node _T_351 = mux(_T_348, _T_349, _T_350) @[el2_lsu_stbuf.scala 148:8] + node _T_352 = mux(_T_337, _T_344, _T_351) @[el2_lsu_stbuf.scala 147:51] + datain1[0] <= _T_304 @[el2_lsu_stbuf.scala 147:11] + datain1[1] <= _T_320 @[el2_lsu_stbuf.scala 147:11] + datain1[2] <= _T_336 @[el2_lsu_stbuf.scala 147:11] + datain1[3] <= _T_352 @[el2_lsu_stbuf.scala 147:11] + node _T_353 = bits(sel_lo, 0, 0) @[el2_lsu_stbuf.scala 150:59] + node _T_354 = bits(stbuf_byteen[0], 1, 1) @[el2_lsu_stbuf.scala 150:84] + node _T_355 = eq(_T_354, UInt<1>("h00")) @[el2_lsu_stbuf.scala 150:68] + node _T_356 = bits(store_byteen_lo_r, 1, 1) @[el2_lsu_stbuf.scala 150:107] + node _T_357 = or(_T_355, _T_356) @[el2_lsu_stbuf.scala 150:88] + node _T_358 = bits(io.store_datafn_lo_r, 15, 8) @[el2_lsu_stbuf.scala 150:132] + node _T_359 = bits(stbuf_data[0], 15, 8) @[el2_lsu_stbuf.scala 150:154] + node _T_360 = mux(_T_357, _T_358, _T_359) @[el2_lsu_stbuf.scala 150:67] + node _T_361 = bits(stbuf_byteen[0], 1, 1) @[el2_lsu_stbuf.scala 151:25] + node _T_362 = eq(_T_361, UInt<1>("h00")) @[el2_lsu_stbuf.scala 151:9] + node _T_363 = bits(store_byteen_hi_r, 1, 1) @[el2_lsu_stbuf.scala 151:48] + node _T_364 = or(_T_362, _T_363) @[el2_lsu_stbuf.scala 151:29] + node _T_365 = bits(io.store_datafn_hi_r, 15, 8) @[el2_lsu_stbuf.scala 151:73] + node _T_366 = bits(stbuf_data[0], 15, 8) @[el2_lsu_stbuf.scala 151:95] + node _T_367 = mux(_T_364, _T_365, _T_366) @[el2_lsu_stbuf.scala 151:8] + node _T_368 = mux(_T_353, _T_360, _T_367) @[el2_lsu_stbuf.scala 150:52] + node _T_369 = bits(sel_lo, 1, 1) @[el2_lsu_stbuf.scala 150:59] + node _T_370 = bits(stbuf_byteen[1], 1, 1) @[el2_lsu_stbuf.scala 150:84] + node _T_371 = eq(_T_370, UInt<1>("h00")) @[el2_lsu_stbuf.scala 150:68] + node _T_372 = bits(store_byteen_lo_r, 1, 1) @[el2_lsu_stbuf.scala 150:107] + node _T_373 = or(_T_371, _T_372) @[el2_lsu_stbuf.scala 150:88] + node _T_374 = bits(io.store_datafn_lo_r, 15, 8) @[el2_lsu_stbuf.scala 150:132] + node _T_375 = bits(stbuf_data[1], 15, 8) @[el2_lsu_stbuf.scala 150:154] + node _T_376 = mux(_T_373, _T_374, _T_375) @[el2_lsu_stbuf.scala 150:67] + node _T_377 = bits(stbuf_byteen[1], 1, 1) @[el2_lsu_stbuf.scala 151:25] + node _T_378 = eq(_T_377, UInt<1>("h00")) @[el2_lsu_stbuf.scala 151:9] + node _T_379 = bits(store_byteen_hi_r, 1, 1) @[el2_lsu_stbuf.scala 151:48] + node _T_380 = or(_T_378, _T_379) @[el2_lsu_stbuf.scala 151:29] + node _T_381 = bits(io.store_datafn_hi_r, 15, 8) @[el2_lsu_stbuf.scala 151:73] + node _T_382 = bits(stbuf_data[1], 15, 8) @[el2_lsu_stbuf.scala 151:95] + node _T_383 = mux(_T_380, _T_381, _T_382) @[el2_lsu_stbuf.scala 151:8] + node _T_384 = mux(_T_369, _T_376, _T_383) @[el2_lsu_stbuf.scala 150:52] + node _T_385 = bits(sel_lo, 2, 2) @[el2_lsu_stbuf.scala 150:59] + node _T_386 = bits(stbuf_byteen[2], 1, 1) @[el2_lsu_stbuf.scala 150:84] + node _T_387 = eq(_T_386, UInt<1>("h00")) @[el2_lsu_stbuf.scala 150:68] + node _T_388 = bits(store_byteen_lo_r, 1, 1) @[el2_lsu_stbuf.scala 150:107] + node _T_389 = or(_T_387, _T_388) @[el2_lsu_stbuf.scala 150:88] + node _T_390 = bits(io.store_datafn_lo_r, 15, 8) @[el2_lsu_stbuf.scala 150:132] + node _T_391 = bits(stbuf_data[2], 15, 8) @[el2_lsu_stbuf.scala 150:154] + node _T_392 = mux(_T_389, _T_390, _T_391) @[el2_lsu_stbuf.scala 150:67] + node _T_393 = bits(stbuf_byteen[2], 1, 1) @[el2_lsu_stbuf.scala 151:25] + node _T_394 = eq(_T_393, UInt<1>("h00")) @[el2_lsu_stbuf.scala 151:9] + node _T_395 = bits(store_byteen_hi_r, 1, 1) @[el2_lsu_stbuf.scala 151:48] + node _T_396 = or(_T_394, _T_395) @[el2_lsu_stbuf.scala 151:29] + node _T_397 = bits(io.store_datafn_hi_r, 15, 8) @[el2_lsu_stbuf.scala 151:73] + node _T_398 = bits(stbuf_data[2], 15, 8) @[el2_lsu_stbuf.scala 151:95] + node _T_399 = mux(_T_396, _T_397, _T_398) @[el2_lsu_stbuf.scala 151:8] + node _T_400 = mux(_T_385, _T_392, _T_399) @[el2_lsu_stbuf.scala 150:52] + node _T_401 = bits(sel_lo, 3, 3) @[el2_lsu_stbuf.scala 150:59] + node _T_402 = bits(stbuf_byteen[3], 1, 1) @[el2_lsu_stbuf.scala 150:84] + node _T_403 = eq(_T_402, UInt<1>("h00")) @[el2_lsu_stbuf.scala 150:68] + node _T_404 = bits(store_byteen_lo_r, 1, 1) @[el2_lsu_stbuf.scala 150:107] + node _T_405 = or(_T_403, _T_404) @[el2_lsu_stbuf.scala 150:88] + node _T_406 = bits(io.store_datafn_lo_r, 15, 8) @[el2_lsu_stbuf.scala 150:132] + node _T_407 = bits(stbuf_data[3], 15, 8) @[el2_lsu_stbuf.scala 150:154] + node _T_408 = mux(_T_405, _T_406, _T_407) @[el2_lsu_stbuf.scala 150:67] + node _T_409 = bits(stbuf_byteen[3], 1, 1) @[el2_lsu_stbuf.scala 151:25] + node _T_410 = eq(_T_409, UInt<1>("h00")) @[el2_lsu_stbuf.scala 151:9] + node _T_411 = bits(store_byteen_hi_r, 1, 1) @[el2_lsu_stbuf.scala 151:48] + node _T_412 = or(_T_410, _T_411) @[el2_lsu_stbuf.scala 151:29] + node _T_413 = bits(io.store_datafn_hi_r, 15, 8) @[el2_lsu_stbuf.scala 151:73] + node _T_414 = bits(stbuf_data[3], 15, 8) @[el2_lsu_stbuf.scala 151:95] + node _T_415 = mux(_T_412, _T_413, _T_414) @[el2_lsu_stbuf.scala 151:8] + node _T_416 = mux(_T_401, _T_408, _T_415) @[el2_lsu_stbuf.scala 150:52] + datain2[0] <= _T_368 @[el2_lsu_stbuf.scala 150:12] + datain2[1] <= _T_384 @[el2_lsu_stbuf.scala 150:12] + datain2[2] <= _T_400 @[el2_lsu_stbuf.scala 150:12] + datain2[3] <= _T_416 @[el2_lsu_stbuf.scala 150:12] + node _T_417 = bits(sel_lo, 0, 0) @[el2_lsu_stbuf.scala 153:59] + node _T_418 = bits(stbuf_byteen[0], 2, 2) @[el2_lsu_stbuf.scala 153:84] + node _T_419 = eq(_T_418, UInt<1>("h00")) @[el2_lsu_stbuf.scala 153:68] + node _T_420 = bits(store_byteen_lo_r, 2, 2) @[el2_lsu_stbuf.scala 153:107] + node _T_421 = or(_T_419, _T_420) @[el2_lsu_stbuf.scala 153:88] + node _T_422 = bits(io.store_datafn_lo_r, 23, 16) @[el2_lsu_stbuf.scala 153:132] + node _T_423 = bits(stbuf_data[0], 23, 16) @[el2_lsu_stbuf.scala 153:155] + node _T_424 = mux(_T_421, _T_422, _T_423) @[el2_lsu_stbuf.scala 153:67] + node _T_425 = bits(stbuf_byteen[0], 2, 2) @[el2_lsu_stbuf.scala 154:25] + node _T_426 = eq(_T_425, UInt<1>("h00")) @[el2_lsu_stbuf.scala 154:9] + node _T_427 = bits(store_byteen_hi_r, 2, 2) @[el2_lsu_stbuf.scala 154:48] + node _T_428 = or(_T_426, _T_427) @[el2_lsu_stbuf.scala 154:29] + node _T_429 = bits(io.store_datafn_hi_r, 23, 16) @[el2_lsu_stbuf.scala 154:73] + node _T_430 = bits(stbuf_data[0], 23, 16) @[el2_lsu_stbuf.scala 154:96] + node _T_431 = mux(_T_428, _T_429, _T_430) @[el2_lsu_stbuf.scala 154:8] + node _T_432 = mux(_T_417, _T_424, _T_431) @[el2_lsu_stbuf.scala 153:52] + node _T_433 = bits(sel_lo, 1, 1) @[el2_lsu_stbuf.scala 153:59] + node _T_434 = bits(stbuf_byteen[1], 2, 2) @[el2_lsu_stbuf.scala 153:84] + node _T_435 = eq(_T_434, UInt<1>("h00")) @[el2_lsu_stbuf.scala 153:68] + node _T_436 = bits(store_byteen_lo_r, 2, 2) @[el2_lsu_stbuf.scala 153:107] + node _T_437 = or(_T_435, _T_436) @[el2_lsu_stbuf.scala 153:88] + node _T_438 = bits(io.store_datafn_lo_r, 23, 16) @[el2_lsu_stbuf.scala 153:132] + node _T_439 = bits(stbuf_data[1], 23, 16) @[el2_lsu_stbuf.scala 153:155] + node _T_440 = mux(_T_437, _T_438, _T_439) @[el2_lsu_stbuf.scala 153:67] + node _T_441 = bits(stbuf_byteen[1], 2, 2) @[el2_lsu_stbuf.scala 154:25] + node _T_442 = eq(_T_441, UInt<1>("h00")) @[el2_lsu_stbuf.scala 154:9] + node _T_443 = bits(store_byteen_hi_r, 2, 2) @[el2_lsu_stbuf.scala 154:48] + node _T_444 = or(_T_442, _T_443) @[el2_lsu_stbuf.scala 154:29] + node _T_445 = bits(io.store_datafn_hi_r, 23, 16) @[el2_lsu_stbuf.scala 154:73] + node _T_446 = bits(stbuf_data[1], 23, 16) @[el2_lsu_stbuf.scala 154:96] + node _T_447 = mux(_T_444, _T_445, _T_446) @[el2_lsu_stbuf.scala 154:8] + node _T_448 = mux(_T_433, _T_440, _T_447) @[el2_lsu_stbuf.scala 153:52] + node _T_449 = bits(sel_lo, 2, 2) @[el2_lsu_stbuf.scala 153:59] + node _T_450 = bits(stbuf_byteen[2], 2, 2) @[el2_lsu_stbuf.scala 153:84] + node _T_451 = eq(_T_450, UInt<1>("h00")) @[el2_lsu_stbuf.scala 153:68] + node _T_452 = bits(store_byteen_lo_r, 2, 2) @[el2_lsu_stbuf.scala 153:107] + node _T_453 = or(_T_451, _T_452) @[el2_lsu_stbuf.scala 153:88] + node _T_454 = bits(io.store_datafn_lo_r, 23, 16) @[el2_lsu_stbuf.scala 153:132] + node _T_455 = bits(stbuf_data[2], 23, 16) @[el2_lsu_stbuf.scala 153:155] + node _T_456 = mux(_T_453, _T_454, _T_455) @[el2_lsu_stbuf.scala 153:67] + node _T_457 = bits(stbuf_byteen[2], 2, 2) @[el2_lsu_stbuf.scala 154:25] + node _T_458 = eq(_T_457, UInt<1>("h00")) @[el2_lsu_stbuf.scala 154:9] + node _T_459 = bits(store_byteen_hi_r, 2, 2) @[el2_lsu_stbuf.scala 154:48] + node _T_460 = or(_T_458, _T_459) @[el2_lsu_stbuf.scala 154:29] + node _T_461 = bits(io.store_datafn_hi_r, 23, 16) @[el2_lsu_stbuf.scala 154:73] + node _T_462 = bits(stbuf_data[2], 23, 16) @[el2_lsu_stbuf.scala 154:96] + node _T_463 = mux(_T_460, _T_461, _T_462) @[el2_lsu_stbuf.scala 154:8] + node _T_464 = mux(_T_449, _T_456, _T_463) @[el2_lsu_stbuf.scala 153:52] + node _T_465 = bits(sel_lo, 3, 3) @[el2_lsu_stbuf.scala 153:59] + node _T_466 = bits(stbuf_byteen[3], 2, 2) @[el2_lsu_stbuf.scala 153:84] + node _T_467 = eq(_T_466, UInt<1>("h00")) @[el2_lsu_stbuf.scala 153:68] + node _T_468 = bits(store_byteen_lo_r, 2, 2) @[el2_lsu_stbuf.scala 153:107] + node _T_469 = or(_T_467, _T_468) @[el2_lsu_stbuf.scala 153:88] + node _T_470 = bits(io.store_datafn_lo_r, 23, 16) @[el2_lsu_stbuf.scala 153:132] + node _T_471 = bits(stbuf_data[3], 23, 16) @[el2_lsu_stbuf.scala 153:155] + node _T_472 = mux(_T_469, _T_470, _T_471) @[el2_lsu_stbuf.scala 153:67] + node _T_473 = bits(stbuf_byteen[3], 2, 2) @[el2_lsu_stbuf.scala 154:25] + node _T_474 = eq(_T_473, UInt<1>("h00")) @[el2_lsu_stbuf.scala 154:9] + node _T_475 = bits(store_byteen_hi_r, 2, 2) @[el2_lsu_stbuf.scala 154:48] + node _T_476 = or(_T_474, _T_475) @[el2_lsu_stbuf.scala 154:29] + node _T_477 = bits(io.store_datafn_hi_r, 23, 16) @[el2_lsu_stbuf.scala 154:73] + node _T_478 = bits(stbuf_data[3], 23, 16) @[el2_lsu_stbuf.scala 154:96] + node _T_479 = mux(_T_476, _T_477, _T_478) @[el2_lsu_stbuf.scala 154:8] + node _T_480 = mux(_T_465, _T_472, _T_479) @[el2_lsu_stbuf.scala 153:52] + datain3[0] <= _T_432 @[el2_lsu_stbuf.scala 153:12] + datain3[1] <= _T_448 @[el2_lsu_stbuf.scala 153:12] + datain3[2] <= _T_464 @[el2_lsu_stbuf.scala 153:12] + datain3[3] <= _T_480 @[el2_lsu_stbuf.scala 153:12] + node _T_481 = bits(sel_lo, 0, 0) @[el2_lsu_stbuf.scala 156:59] + node _T_482 = bits(stbuf_byteen[0], 3, 3) @[el2_lsu_stbuf.scala 156:84] + node _T_483 = eq(_T_482, UInt<1>("h00")) @[el2_lsu_stbuf.scala 156:68] + node _T_484 = bits(store_byteen_lo_r, 3, 3) @[el2_lsu_stbuf.scala 156:107] + node _T_485 = or(_T_483, _T_484) @[el2_lsu_stbuf.scala 156:88] + node _T_486 = bits(io.store_datafn_lo_r, 31, 24) @[el2_lsu_stbuf.scala 156:132] + node _T_487 = bits(stbuf_data[0], 31, 24) @[el2_lsu_stbuf.scala 156:155] + node _T_488 = mux(_T_485, _T_486, _T_487) @[el2_lsu_stbuf.scala 156:67] + node _T_489 = bits(stbuf_byteen[0], 3, 3) @[el2_lsu_stbuf.scala 157:25] + node _T_490 = eq(_T_489, UInt<1>("h00")) @[el2_lsu_stbuf.scala 157:9] + node _T_491 = bits(store_byteen_hi_r, 3, 3) @[el2_lsu_stbuf.scala 157:48] + node _T_492 = or(_T_490, _T_491) @[el2_lsu_stbuf.scala 157:29] + node _T_493 = bits(io.store_datafn_hi_r, 31, 24) @[el2_lsu_stbuf.scala 157:73] + node _T_494 = bits(stbuf_data[0], 31, 24) @[el2_lsu_stbuf.scala 157:96] + node _T_495 = mux(_T_492, _T_493, _T_494) @[el2_lsu_stbuf.scala 157:8] + node _T_496 = mux(_T_481, _T_488, _T_495) @[el2_lsu_stbuf.scala 156:52] + node _T_497 = bits(sel_lo, 1, 1) @[el2_lsu_stbuf.scala 156:59] + node _T_498 = bits(stbuf_byteen[1], 3, 3) @[el2_lsu_stbuf.scala 156:84] + node _T_499 = eq(_T_498, UInt<1>("h00")) @[el2_lsu_stbuf.scala 156:68] + node _T_500 = bits(store_byteen_lo_r, 3, 3) @[el2_lsu_stbuf.scala 156:107] + node _T_501 = or(_T_499, _T_500) @[el2_lsu_stbuf.scala 156:88] + node _T_502 = bits(io.store_datafn_lo_r, 31, 24) @[el2_lsu_stbuf.scala 156:132] + node _T_503 = bits(stbuf_data[1], 31, 24) @[el2_lsu_stbuf.scala 156:155] + node _T_504 = mux(_T_501, _T_502, _T_503) @[el2_lsu_stbuf.scala 156:67] + node _T_505 = bits(stbuf_byteen[1], 3, 3) @[el2_lsu_stbuf.scala 157:25] + node _T_506 = eq(_T_505, UInt<1>("h00")) @[el2_lsu_stbuf.scala 157:9] + node _T_507 = bits(store_byteen_hi_r, 3, 3) @[el2_lsu_stbuf.scala 157:48] + node _T_508 = or(_T_506, _T_507) @[el2_lsu_stbuf.scala 157:29] + node _T_509 = bits(io.store_datafn_hi_r, 31, 24) @[el2_lsu_stbuf.scala 157:73] + node _T_510 = bits(stbuf_data[1], 31, 24) @[el2_lsu_stbuf.scala 157:96] + node _T_511 = mux(_T_508, _T_509, _T_510) @[el2_lsu_stbuf.scala 157:8] + node _T_512 = mux(_T_497, _T_504, _T_511) @[el2_lsu_stbuf.scala 156:52] + node _T_513 = bits(sel_lo, 2, 2) @[el2_lsu_stbuf.scala 156:59] + node _T_514 = bits(stbuf_byteen[2], 3, 3) @[el2_lsu_stbuf.scala 156:84] + node _T_515 = eq(_T_514, UInt<1>("h00")) @[el2_lsu_stbuf.scala 156:68] + node _T_516 = bits(store_byteen_lo_r, 3, 3) @[el2_lsu_stbuf.scala 156:107] + node _T_517 = or(_T_515, _T_516) @[el2_lsu_stbuf.scala 156:88] + node _T_518 = bits(io.store_datafn_lo_r, 31, 24) @[el2_lsu_stbuf.scala 156:132] + node _T_519 = bits(stbuf_data[2], 31, 24) @[el2_lsu_stbuf.scala 156:155] + node _T_520 = mux(_T_517, _T_518, _T_519) @[el2_lsu_stbuf.scala 156:67] + node _T_521 = bits(stbuf_byteen[2], 3, 3) @[el2_lsu_stbuf.scala 157:25] + node _T_522 = eq(_T_521, UInt<1>("h00")) @[el2_lsu_stbuf.scala 157:9] + node _T_523 = bits(store_byteen_hi_r, 3, 3) @[el2_lsu_stbuf.scala 157:48] + node _T_524 = or(_T_522, _T_523) @[el2_lsu_stbuf.scala 157:29] + node _T_525 = bits(io.store_datafn_hi_r, 31, 24) @[el2_lsu_stbuf.scala 157:73] + node _T_526 = bits(stbuf_data[2], 31, 24) @[el2_lsu_stbuf.scala 157:96] + node _T_527 = mux(_T_524, _T_525, _T_526) @[el2_lsu_stbuf.scala 157:8] + node _T_528 = mux(_T_513, _T_520, _T_527) @[el2_lsu_stbuf.scala 156:52] + node _T_529 = bits(sel_lo, 3, 3) @[el2_lsu_stbuf.scala 156:59] + node _T_530 = bits(stbuf_byteen[3], 3, 3) @[el2_lsu_stbuf.scala 156:84] + node _T_531 = eq(_T_530, UInt<1>("h00")) @[el2_lsu_stbuf.scala 156:68] + node _T_532 = bits(store_byteen_lo_r, 3, 3) @[el2_lsu_stbuf.scala 156:107] + node _T_533 = or(_T_531, _T_532) @[el2_lsu_stbuf.scala 156:88] + node _T_534 = bits(io.store_datafn_lo_r, 31, 24) @[el2_lsu_stbuf.scala 156:132] + node _T_535 = bits(stbuf_data[3], 31, 24) @[el2_lsu_stbuf.scala 156:155] + node _T_536 = mux(_T_533, _T_534, _T_535) @[el2_lsu_stbuf.scala 156:67] + node _T_537 = bits(stbuf_byteen[3], 3, 3) @[el2_lsu_stbuf.scala 157:25] + node _T_538 = eq(_T_537, UInt<1>("h00")) @[el2_lsu_stbuf.scala 157:9] + node _T_539 = bits(store_byteen_hi_r, 3, 3) @[el2_lsu_stbuf.scala 157:48] + node _T_540 = or(_T_538, _T_539) @[el2_lsu_stbuf.scala 157:29] + node _T_541 = bits(io.store_datafn_hi_r, 31, 24) @[el2_lsu_stbuf.scala 157:73] + node _T_542 = bits(stbuf_data[3], 31, 24) @[el2_lsu_stbuf.scala 157:96] + node _T_543 = mux(_T_540, _T_541, _T_542) @[el2_lsu_stbuf.scala 157:8] + node _T_544 = mux(_T_529, _T_536, _T_543) @[el2_lsu_stbuf.scala 156:52] + datain4[0] <= _T_496 @[el2_lsu_stbuf.scala 156:12] + datain4[1] <= _T_512 @[el2_lsu_stbuf.scala 156:12] + datain4[2] <= _T_528 @[el2_lsu_stbuf.scala 156:12] + datain4[3] <= _T_544 @[el2_lsu_stbuf.scala 156:12] node _T_545 = cat(datain2[0], datain1[0]) @[Cat.scala 29:58] node _T_546 = cat(datain4[0], datain3[0]) @[Cat.scala 29:58] node _T_547 = cat(_T_546, _T_545) @[Cat.scala 29:58] @@ -895,972 +895,972 @@ circuit el2_lsu_stbuf : node _T_554 = cat(datain2[3], datain1[3]) @[Cat.scala 29:58] node _T_555 = cat(datain4[3], datain3[3]) @[Cat.scala 29:58] node _T_556 = cat(_T_555, _T_554) @[Cat.scala 29:58] - stbuf_datain[0] <= _T_547 @[el2_lsu_stbuf.scala 160:17] - stbuf_datain[1] <= _T_550 @[el2_lsu_stbuf.scala 160:17] - stbuf_datain[2] <= _T_553 @[el2_lsu_stbuf.scala 160:17] - stbuf_datain[3] <= _T_556 @[el2_lsu_stbuf.scala 160:17] - node _T_557 = bits(stbuf_wr_en, 0, 0) @[el2_lsu_stbuf.scala 164:104] - node _T_558 = bits(_T_557, 0, 0) @[el2_lsu_stbuf.scala 164:114] - node _T_559 = bits(stbuf_vld, 0, 0) @[el2_lsu_stbuf.scala 164:131] - node _T_560 = mux(_T_558, UInt<1>("h01"), _T_559) @[el2_lsu_stbuf.scala 164:92] - node _T_561 = bits(stbuf_reset, 0, 0) @[el2_lsu_stbuf.scala 164:150] - node _T_562 = eq(_T_561, UInt<1>("h00")) @[el2_lsu_stbuf.scala 164:138] - node _T_563 = and(_T_560, _T_562) @[el2_lsu_stbuf.scala 164:136] - reg _T_564 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_stbuf.scala 164:88] - _T_564 <= _T_563 @[el2_lsu_stbuf.scala 164:88] - node _T_565 = bits(stbuf_wr_en, 1, 1) @[el2_lsu_stbuf.scala 164:104] - node _T_566 = bits(_T_565, 0, 0) @[el2_lsu_stbuf.scala 164:114] - node _T_567 = bits(stbuf_vld, 1, 1) @[el2_lsu_stbuf.scala 164:131] - node _T_568 = mux(_T_566, UInt<1>("h01"), _T_567) @[el2_lsu_stbuf.scala 164:92] - node _T_569 = bits(stbuf_reset, 1, 1) @[el2_lsu_stbuf.scala 164:150] - node _T_570 = eq(_T_569, UInt<1>("h00")) @[el2_lsu_stbuf.scala 164:138] - node _T_571 = and(_T_568, _T_570) @[el2_lsu_stbuf.scala 164:136] - reg _T_572 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_stbuf.scala 164:88] - _T_572 <= _T_571 @[el2_lsu_stbuf.scala 164:88] - node _T_573 = bits(stbuf_wr_en, 2, 2) @[el2_lsu_stbuf.scala 164:104] - node _T_574 = bits(_T_573, 0, 0) @[el2_lsu_stbuf.scala 164:114] - node _T_575 = bits(stbuf_vld, 2, 2) @[el2_lsu_stbuf.scala 164:131] - node _T_576 = mux(_T_574, UInt<1>("h01"), _T_575) @[el2_lsu_stbuf.scala 164:92] - node _T_577 = bits(stbuf_reset, 2, 2) @[el2_lsu_stbuf.scala 164:150] - node _T_578 = eq(_T_577, UInt<1>("h00")) @[el2_lsu_stbuf.scala 164:138] - node _T_579 = and(_T_576, _T_578) @[el2_lsu_stbuf.scala 164:136] - reg _T_580 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_stbuf.scala 164:88] - _T_580 <= _T_579 @[el2_lsu_stbuf.scala 164:88] - node _T_581 = bits(stbuf_wr_en, 3, 3) @[el2_lsu_stbuf.scala 164:104] - node _T_582 = bits(_T_581, 0, 0) @[el2_lsu_stbuf.scala 164:114] - node _T_583 = bits(stbuf_vld, 3, 3) @[el2_lsu_stbuf.scala 164:131] - node _T_584 = mux(_T_582, UInt<1>("h01"), _T_583) @[el2_lsu_stbuf.scala 164:92] - node _T_585 = bits(stbuf_reset, 3, 3) @[el2_lsu_stbuf.scala 164:150] - node _T_586 = eq(_T_585, UInt<1>("h00")) @[el2_lsu_stbuf.scala 164:138] - node _T_587 = and(_T_584, _T_586) @[el2_lsu_stbuf.scala 164:136] - reg _T_588 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_stbuf.scala 164:88] - _T_588 <= _T_587 @[el2_lsu_stbuf.scala 164:88] + stbuf_datain[0] <= _T_547 @[el2_lsu_stbuf.scala 159:16] + stbuf_datain[1] <= _T_550 @[el2_lsu_stbuf.scala 159:16] + stbuf_datain[2] <= _T_553 @[el2_lsu_stbuf.scala 159:16] + stbuf_datain[3] <= _T_556 @[el2_lsu_stbuf.scala 159:16] + node _T_557 = bits(stbuf_wr_en, 0, 0) @[el2_lsu_stbuf.scala 163:104] + node _T_558 = bits(_T_557, 0, 0) @[el2_lsu_stbuf.scala 163:114] + node _T_559 = bits(stbuf_vld, 0, 0) @[el2_lsu_stbuf.scala 163:131] + node _T_560 = mux(_T_558, UInt<1>("h01"), _T_559) @[el2_lsu_stbuf.scala 163:92] + node _T_561 = bits(stbuf_reset, 0, 0) @[el2_lsu_stbuf.scala 163:150] + node _T_562 = eq(_T_561, UInt<1>("h00")) @[el2_lsu_stbuf.scala 163:138] + node _T_563 = and(_T_560, _T_562) @[el2_lsu_stbuf.scala 163:136] + reg _T_564 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_stbuf.scala 163:88] + _T_564 <= _T_563 @[el2_lsu_stbuf.scala 163:88] + node _T_565 = bits(stbuf_wr_en, 1, 1) @[el2_lsu_stbuf.scala 163:104] + node _T_566 = bits(_T_565, 0, 0) @[el2_lsu_stbuf.scala 163:114] + node _T_567 = bits(stbuf_vld, 1, 1) @[el2_lsu_stbuf.scala 163:131] + node _T_568 = mux(_T_566, UInt<1>("h01"), _T_567) @[el2_lsu_stbuf.scala 163:92] + node _T_569 = bits(stbuf_reset, 1, 1) @[el2_lsu_stbuf.scala 163:150] + node _T_570 = eq(_T_569, UInt<1>("h00")) @[el2_lsu_stbuf.scala 163:138] + node _T_571 = and(_T_568, _T_570) @[el2_lsu_stbuf.scala 163:136] + reg _T_572 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_stbuf.scala 163:88] + _T_572 <= _T_571 @[el2_lsu_stbuf.scala 163:88] + node _T_573 = bits(stbuf_wr_en, 2, 2) @[el2_lsu_stbuf.scala 163:104] + node _T_574 = bits(_T_573, 0, 0) @[el2_lsu_stbuf.scala 163:114] + node _T_575 = bits(stbuf_vld, 2, 2) @[el2_lsu_stbuf.scala 163:131] + node _T_576 = mux(_T_574, UInt<1>("h01"), _T_575) @[el2_lsu_stbuf.scala 163:92] + node _T_577 = bits(stbuf_reset, 2, 2) @[el2_lsu_stbuf.scala 163:150] + node _T_578 = eq(_T_577, UInt<1>("h00")) @[el2_lsu_stbuf.scala 163:138] + node _T_579 = and(_T_576, _T_578) @[el2_lsu_stbuf.scala 163:136] + reg _T_580 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_stbuf.scala 163:88] + _T_580 <= _T_579 @[el2_lsu_stbuf.scala 163:88] + node _T_581 = bits(stbuf_wr_en, 3, 3) @[el2_lsu_stbuf.scala 163:104] + node _T_582 = bits(_T_581, 0, 0) @[el2_lsu_stbuf.scala 163:114] + node _T_583 = bits(stbuf_vld, 3, 3) @[el2_lsu_stbuf.scala 163:131] + node _T_584 = mux(_T_582, UInt<1>("h01"), _T_583) @[el2_lsu_stbuf.scala 163:92] + node _T_585 = bits(stbuf_reset, 3, 3) @[el2_lsu_stbuf.scala 163:150] + node _T_586 = eq(_T_585, UInt<1>("h00")) @[el2_lsu_stbuf.scala 163:138] + node _T_587 = and(_T_584, _T_586) @[el2_lsu_stbuf.scala 163:136] + reg _T_588 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_stbuf.scala 163:88] + _T_588 <= _T_587 @[el2_lsu_stbuf.scala 163:88] node _T_589 = cat(_T_588, _T_580) @[Cat.scala 29:58] node _T_590 = cat(_T_589, _T_572) @[Cat.scala 29:58] node _T_591 = cat(_T_590, _T_564) @[Cat.scala 29:58] - stbuf_vld <= _T_591 @[el2_lsu_stbuf.scala 164:13] - node _T_592 = bits(stbuf_dma_kill_en, 0, 0) @[el2_lsu_stbuf.scala 166:84] - node _T_593 = bits(_T_592, 0, 0) @[el2_lsu_stbuf.scala 166:88] - node _T_594 = bits(stbuf_dma_kill, 0, 0) @[el2_lsu_stbuf.scala 166:114] - node _T_595 = mux(_T_593, UInt<1>("h01"), _T_594) @[el2_lsu_stbuf.scala 166:66] - node _T_596 = bits(stbuf_reset, 0, 0) @[el2_lsu_stbuf.scala 166:133] - node _T_597 = eq(_T_596, UInt<1>("h00")) @[el2_lsu_stbuf.scala 166:121] - node _T_598 = and(_T_595, _T_597) @[el2_lsu_stbuf.scala 166:119] - reg _T_599 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_stbuf.scala 166:62] - _T_599 <= _T_598 @[el2_lsu_stbuf.scala 166:62] - node _T_600 = bits(stbuf_dma_kill_en, 1, 1) @[el2_lsu_stbuf.scala 166:84] - node _T_601 = bits(_T_600, 0, 0) @[el2_lsu_stbuf.scala 166:88] - node _T_602 = bits(stbuf_dma_kill, 1, 1) @[el2_lsu_stbuf.scala 166:114] - node _T_603 = mux(_T_601, UInt<1>("h01"), _T_602) @[el2_lsu_stbuf.scala 166:66] - node _T_604 = bits(stbuf_reset, 1, 1) @[el2_lsu_stbuf.scala 166:133] - node _T_605 = eq(_T_604, UInt<1>("h00")) @[el2_lsu_stbuf.scala 166:121] - node _T_606 = and(_T_603, _T_605) @[el2_lsu_stbuf.scala 166:119] - reg _T_607 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_stbuf.scala 166:62] - _T_607 <= _T_606 @[el2_lsu_stbuf.scala 166:62] - node _T_608 = bits(stbuf_dma_kill_en, 2, 2) @[el2_lsu_stbuf.scala 166:84] - node _T_609 = bits(_T_608, 0, 0) @[el2_lsu_stbuf.scala 166:88] - node _T_610 = bits(stbuf_dma_kill, 2, 2) @[el2_lsu_stbuf.scala 166:114] - node _T_611 = mux(_T_609, UInt<1>("h01"), _T_610) @[el2_lsu_stbuf.scala 166:66] - node _T_612 = bits(stbuf_reset, 2, 2) @[el2_lsu_stbuf.scala 166:133] - node _T_613 = eq(_T_612, UInt<1>("h00")) @[el2_lsu_stbuf.scala 166:121] - node _T_614 = and(_T_611, _T_613) @[el2_lsu_stbuf.scala 166:119] - reg _T_615 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_stbuf.scala 166:62] - _T_615 <= _T_614 @[el2_lsu_stbuf.scala 166:62] - node _T_616 = bits(stbuf_dma_kill_en, 3, 3) @[el2_lsu_stbuf.scala 166:84] - node _T_617 = bits(_T_616, 0, 0) @[el2_lsu_stbuf.scala 166:88] - node _T_618 = bits(stbuf_dma_kill, 3, 3) @[el2_lsu_stbuf.scala 166:114] - node _T_619 = mux(_T_617, UInt<1>("h01"), _T_618) @[el2_lsu_stbuf.scala 166:66] - node _T_620 = bits(stbuf_reset, 3, 3) @[el2_lsu_stbuf.scala 166:133] - node _T_621 = eq(_T_620, UInt<1>("h00")) @[el2_lsu_stbuf.scala 166:121] - node _T_622 = and(_T_619, _T_621) @[el2_lsu_stbuf.scala 166:119] - reg _T_623 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_stbuf.scala 166:62] - _T_623 <= _T_622 @[el2_lsu_stbuf.scala 166:62] + stbuf_vld <= _T_591 @[el2_lsu_stbuf.scala 163:13] + node _T_592 = bits(stbuf_dma_kill_en, 0, 0) @[el2_lsu_stbuf.scala 164:114] + node _T_593 = bits(_T_592, 0, 0) @[el2_lsu_stbuf.scala 164:118] + node _T_594 = bits(stbuf_dma_kill, 0, 0) @[el2_lsu_stbuf.scala 164:144] + node _T_595 = mux(_T_593, UInt<1>("h01"), _T_594) @[el2_lsu_stbuf.scala 164:96] + node _T_596 = bits(stbuf_reset, 0, 0) @[el2_lsu_stbuf.scala 164:163] + node _T_597 = eq(_T_596, UInt<1>("h00")) @[el2_lsu_stbuf.scala 164:151] + node _T_598 = and(_T_595, _T_597) @[el2_lsu_stbuf.scala 164:149] + reg _T_599 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_stbuf.scala 164:92] + _T_599 <= _T_598 @[el2_lsu_stbuf.scala 164:92] + node _T_600 = bits(stbuf_dma_kill_en, 1, 1) @[el2_lsu_stbuf.scala 164:114] + node _T_601 = bits(_T_600, 0, 0) @[el2_lsu_stbuf.scala 164:118] + node _T_602 = bits(stbuf_dma_kill, 1, 1) @[el2_lsu_stbuf.scala 164:144] + node _T_603 = mux(_T_601, UInt<1>("h01"), _T_602) @[el2_lsu_stbuf.scala 164:96] + node _T_604 = bits(stbuf_reset, 1, 1) @[el2_lsu_stbuf.scala 164:163] + node _T_605 = eq(_T_604, UInt<1>("h00")) @[el2_lsu_stbuf.scala 164:151] + node _T_606 = and(_T_603, _T_605) @[el2_lsu_stbuf.scala 164:149] + reg _T_607 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_stbuf.scala 164:92] + _T_607 <= _T_606 @[el2_lsu_stbuf.scala 164:92] + node _T_608 = bits(stbuf_dma_kill_en, 2, 2) @[el2_lsu_stbuf.scala 164:114] + node _T_609 = bits(_T_608, 0, 0) @[el2_lsu_stbuf.scala 164:118] + node _T_610 = bits(stbuf_dma_kill, 2, 2) @[el2_lsu_stbuf.scala 164:144] + node _T_611 = mux(_T_609, UInt<1>("h01"), _T_610) @[el2_lsu_stbuf.scala 164:96] + node _T_612 = bits(stbuf_reset, 2, 2) @[el2_lsu_stbuf.scala 164:163] + node _T_613 = eq(_T_612, UInt<1>("h00")) @[el2_lsu_stbuf.scala 164:151] + node _T_614 = and(_T_611, _T_613) @[el2_lsu_stbuf.scala 164:149] + reg _T_615 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_stbuf.scala 164:92] + _T_615 <= _T_614 @[el2_lsu_stbuf.scala 164:92] + node _T_616 = bits(stbuf_dma_kill_en, 3, 3) @[el2_lsu_stbuf.scala 164:114] + node _T_617 = bits(_T_616, 0, 0) @[el2_lsu_stbuf.scala 164:118] + node _T_618 = bits(stbuf_dma_kill, 3, 3) @[el2_lsu_stbuf.scala 164:144] + node _T_619 = mux(_T_617, UInt<1>("h01"), _T_618) @[el2_lsu_stbuf.scala 164:96] + node _T_620 = bits(stbuf_reset, 3, 3) @[el2_lsu_stbuf.scala 164:163] + node _T_621 = eq(_T_620, UInt<1>("h00")) @[el2_lsu_stbuf.scala 164:151] + node _T_622 = and(_T_619, _T_621) @[el2_lsu_stbuf.scala 164:149] + reg _T_623 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_stbuf.scala 164:92] + _T_623 <= _T_622 @[el2_lsu_stbuf.scala 164:92] node _T_624 = cat(_T_623, _T_615) @[Cat.scala 29:58] node _T_625 = cat(_T_624, _T_607) @[Cat.scala 29:58] node _T_626 = cat(_T_625, _T_599) @[Cat.scala 29:58] - stbuf_dma_kill <= _T_626 @[el2_lsu_stbuf.scala 166:18] - node _T_627 = bits(stbuf_wr_en, 0, 0) @[el2_lsu_stbuf.scala 167:108] - node _T_628 = bits(_T_627, 0, 0) @[el2_lsu_stbuf.scala 167:118] - node _T_629 = mux(_T_628, stbuf_byteenin[0], stbuf_byteen[0]) @[el2_lsu_stbuf.scala 167:96] - node _T_630 = bits(stbuf_reset, 0, 0) @[el2_lsu_stbuf.scala 167:206] - node _T_631 = eq(_T_630, UInt<1>("h00")) @[el2_lsu_stbuf.scala 167:194] + stbuf_dma_kill <= _T_626 @[el2_lsu_stbuf.scala 164:18] + node _T_627 = bits(stbuf_wr_en, 0, 0) @[el2_lsu_stbuf.scala 165:108] + node _T_628 = bits(_T_627, 0, 0) @[el2_lsu_stbuf.scala 165:118] + node _T_629 = mux(_T_628, stbuf_byteenin[0], stbuf_byteen[0]) @[el2_lsu_stbuf.scala 165:96] + node _T_630 = bits(stbuf_reset, 0, 0) @[el2_lsu_stbuf.scala 165:206] + node _T_631 = eq(_T_630, UInt<1>("h00")) @[el2_lsu_stbuf.scala 165:194] node _T_632 = bits(_T_631, 0, 0) @[Bitwise.scala 72:15] node _T_633 = mux(_T_632, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_634 = and(_T_629, _T_633) @[el2_lsu_stbuf.scala 167:158] - reg _T_635 : UInt, io.lsu_stbuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_stbuf.scala 167:92] - _T_635 <= _T_634 @[el2_lsu_stbuf.scala 167:92] - node _T_636 = bits(stbuf_wr_en, 1, 1) @[el2_lsu_stbuf.scala 167:108] - node _T_637 = bits(_T_636, 0, 0) @[el2_lsu_stbuf.scala 167:118] - node _T_638 = mux(_T_637, stbuf_byteenin[1], stbuf_byteen[1]) @[el2_lsu_stbuf.scala 167:96] - node _T_639 = bits(stbuf_reset, 1, 1) @[el2_lsu_stbuf.scala 167:206] - node _T_640 = eq(_T_639, UInt<1>("h00")) @[el2_lsu_stbuf.scala 167:194] + node _T_634 = and(_T_629, _T_633) @[el2_lsu_stbuf.scala 165:158] + reg _T_635 : UInt, io.lsu_stbuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_stbuf.scala 165:92] + _T_635 <= _T_634 @[el2_lsu_stbuf.scala 165:92] + node _T_636 = bits(stbuf_wr_en, 1, 1) @[el2_lsu_stbuf.scala 165:108] + node _T_637 = bits(_T_636, 0, 0) @[el2_lsu_stbuf.scala 165:118] + node _T_638 = mux(_T_637, stbuf_byteenin[1], stbuf_byteen[1]) @[el2_lsu_stbuf.scala 165:96] + node _T_639 = bits(stbuf_reset, 1, 1) @[el2_lsu_stbuf.scala 165:206] + node _T_640 = eq(_T_639, UInt<1>("h00")) @[el2_lsu_stbuf.scala 165:194] node _T_641 = bits(_T_640, 0, 0) @[Bitwise.scala 72:15] node _T_642 = mux(_T_641, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_643 = and(_T_638, _T_642) @[el2_lsu_stbuf.scala 167:158] - reg _T_644 : UInt, io.lsu_stbuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_stbuf.scala 167:92] - _T_644 <= _T_643 @[el2_lsu_stbuf.scala 167:92] - node _T_645 = bits(stbuf_wr_en, 2, 2) @[el2_lsu_stbuf.scala 167:108] - node _T_646 = bits(_T_645, 0, 0) @[el2_lsu_stbuf.scala 167:118] - node _T_647 = mux(_T_646, stbuf_byteenin[2], stbuf_byteen[2]) @[el2_lsu_stbuf.scala 167:96] - node _T_648 = bits(stbuf_reset, 2, 2) @[el2_lsu_stbuf.scala 167:206] - node _T_649 = eq(_T_648, UInt<1>("h00")) @[el2_lsu_stbuf.scala 167:194] + node _T_643 = and(_T_638, _T_642) @[el2_lsu_stbuf.scala 165:158] + reg _T_644 : UInt, io.lsu_stbuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_stbuf.scala 165:92] + _T_644 <= _T_643 @[el2_lsu_stbuf.scala 165:92] + node _T_645 = bits(stbuf_wr_en, 2, 2) @[el2_lsu_stbuf.scala 165:108] + node _T_646 = bits(_T_645, 0, 0) @[el2_lsu_stbuf.scala 165:118] + node _T_647 = mux(_T_646, stbuf_byteenin[2], stbuf_byteen[2]) @[el2_lsu_stbuf.scala 165:96] + node _T_648 = bits(stbuf_reset, 2, 2) @[el2_lsu_stbuf.scala 165:206] + node _T_649 = eq(_T_648, UInt<1>("h00")) @[el2_lsu_stbuf.scala 165:194] node _T_650 = bits(_T_649, 0, 0) @[Bitwise.scala 72:15] node _T_651 = mux(_T_650, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_652 = and(_T_647, _T_651) @[el2_lsu_stbuf.scala 167:158] - reg _T_653 : UInt, io.lsu_stbuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_stbuf.scala 167:92] - _T_653 <= _T_652 @[el2_lsu_stbuf.scala 167:92] - node _T_654 = bits(stbuf_wr_en, 3, 3) @[el2_lsu_stbuf.scala 167:108] - node _T_655 = bits(_T_654, 0, 0) @[el2_lsu_stbuf.scala 167:118] - node _T_656 = mux(_T_655, stbuf_byteenin[3], stbuf_byteen[3]) @[el2_lsu_stbuf.scala 167:96] - node _T_657 = bits(stbuf_reset, 3, 3) @[el2_lsu_stbuf.scala 167:206] - node _T_658 = eq(_T_657, UInt<1>("h00")) @[el2_lsu_stbuf.scala 167:194] + node _T_652 = and(_T_647, _T_651) @[el2_lsu_stbuf.scala 165:158] + reg _T_653 : UInt, io.lsu_stbuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_stbuf.scala 165:92] + _T_653 <= _T_652 @[el2_lsu_stbuf.scala 165:92] + node _T_654 = bits(stbuf_wr_en, 3, 3) @[el2_lsu_stbuf.scala 165:108] + node _T_655 = bits(_T_654, 0, 0) @[el2_lsu_stbuf.scala 165:118] + node _T_656 = mux(_T_655, stbuf_byteenin[3], stbuf_byteen[3]) @[el2_lsu_stbuf.scala 165:96] + node _T_657 = bits(stbuf_reset, 3, 3) @[el2_lsu_stbuf.scala 165:206] + node _T_658 = eq(_T_657, UInt<1>("h00")) @[el2_lsu_stbuf.scala 165:194] node _T_659 = bits(_T_658, 0, 0) @[Bitwise.scala 72:15] node _T_660 = mux(_T_659, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_661 = and(_T_656, _T_660) @[el2_lsu_stbuf.scala 167:158] - reg _T_662 : UInt, io.lsu_stbuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_stbuf.scala 167:92] - _T_662 <= _T_661 @[el2_lsu_stbuf.scala 167:92] - stbuf_byteen[0] <= _T_635 @[el2_lsu_stbuf.scala 167:16] - stbuf_byteen[1] <= _T_644 @[el2_lsu_stbuf.scala 167:16] - stbuf_byteen[2] <= _T_653 @[el2_lsu_stbuf.scala 167:16] - stbuf_byteen[3] <= _T_662 @[el2_lsu_stbuf.scala 167:16] - node _T_663 = bits(stbuf_wr_en, 0, 0) @[el2_lsu_stbuf.scala 172:58] - node _T_664 = bits(_T_663, 0, 0) @[el2_lsu_stbuf.scala 172:68] - inst rvclkhdr of rvclkhdr @[beh_lib.scala 352:21] + node _T_661 = and(_T_656, _T_660) @[el2_lsu_stbuf.scala 165:158] + reg _T_662 : UInt, io.lsu_stbuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_stbuf.scala 165:92] + _T_662 <= _T_661 @[el2_lsu_stbuf.scala 165:92] + stbuf_byteen[0] <= _T_635 @[el2_lsu_stbuf.scala 165:16] + stbuf_byteen[1] <= _T_644 @[el2_lsu_stbuf.scala 165:16] + stbuf_byteen[2] <= _T_653 @[el2_lsu_stbuf.scala 165:16] + stbuf_byteen[3] <= _T_662 @[el2_lsu_stbuf.scala 165:16] + node _T_663 = bits(stbuf_wr_en, 0, 0) @[el2_lsu_stbuf.scala 167:56] + node _T_664 = bits(_T_663, 0, 0) @[el2_lsu_stbuf.scala 167:66] + inst rvclkhdr of rvclkhdr @[el2_lib.scala 508:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset - rvclkhdr.io.clk <= clock @[beh_lib.scala 354:16] - rvclkhdr.io.en <= _T_664 @[beh_lib.scala 355:15] - rvclkhdr.io.scan_mode <= io.scan_mode @[beh_lib.scala 356:22] - reg _T_665 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[beh_lib.scala 358:14] - _T_665 <= stbuf_addrin[0] @[beh_lib.scala 358:14] - stbuf_addr[0] <= _T_665 @[el2_lsu_stbuf.scala 172:21] - node _T_666 = bits(stbuf_wr_en, 0, 0) @[el2_lsu_stbuf.scala 174:57] - node _T_667 = bits(_T_666, 0, 0) @[el2_lsu_stbuf.scala 174:67] - inst rvclkhdr_1 of rvclkhdr_1 @[beh_lib.scala 352:21] + rvclkhdr.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr.io.en <= _T_664 @[el2_lib.scala 511:17] + rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_665 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_665 <= stbuf_addrin[0] @[el2_lib.scala 514:16] + stbuf_addr[0] <= _T_665 @[el2_lsu_stbuf.scala 167:19] + node _T_666 = bits(stbuf_wr_en, 0, 0) @[el2_lsu_stbuf.scala 168:56] + node _T_667 = bits(_T_666, 0, 0) @[el2_lsu_stbuf.scala 168:66] + inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 508:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset - rvclkhdr_1.io.clk <= clock @[beh_lib.scala 354:16] - rvclkhdr_1.io.en <= _T_667 @[beh_lib.scala 355:15] - rvclkhdr_1.io.scan_mode <= io.scan_mode @[beh_lib.scala 356:22] - reg _T_668 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[beh_lib.scala 358:14] - _T_668 <= stbuf_datain[0] @[beh_lib.scala 358:14] - stbuf_data[0] <= _T_668 @[el2_lsu_stbuf.scala 174:20] - node _T_669 = bits(stbuf_wr_en, 1, 1) @[el2_lsu_stbuf.scala 172:58] - node _T_670 = bits(_T_669, 0, 0) @[el2_lsu_stbuf.scala 172:68] - inst rvclkhdr_2 of rvclkhdr_2 @[beh_lib.scala 352:21] + rvclkhdr_1.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_1.io.en <= _T_667 @[el2_lib.scala 511:17] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_668 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_668 <= stbuf_datain[0] @[el2_lib.scala 514:16] + stbuf_data[0] <= _T_668 @[el2_lsu_stbuf.scala 168:19] + node _T_669 = bits(stbuf_wr_en, 1, 1) @[el2_lsu_stbuf.scala 167:56] + node _T_670 = bits(_T_669, 0, 0) @[el2_lsu_stbuf.scala 167:66] + inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 508:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset - rvclkhdr_2.io.clk <= clock @[beh_lib.scala 354:16] - rvclkhdr_2.io.en <= _T_670 @[beh_lib.scala 355:15] - rvclkhdr_2.io.scan_mode <= io.scan_mode @[beh_lib.scala 356:22] - reg _T_671 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[beh_lib.scala 358:14] - _T_671 <= stbuf_addrin[1] @[beh_lib.scala 358:14] - stbuf_addr[1] <= _T_671 @[el2_lsu_stbuf.scala 172:21] - node _T_672 = bits(stbuf_wr_en, 1, 1) @[el2_lsu_stbuf.scala 174:57] - node _T_673 = bits(_T_672, 0, 0) @[el2_lsu_stbuf.scala 174:67] - inst rvclkhdr_3 of rvclkhdr_3 @[beh_lib.scala 352:21] + rvclkhdr_2.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_2.io.en <= _T_670 @[el2_lib.scala 511:17] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_671 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_671 <= stbuf_addrin[1] @[el2_lib.scala 514:16] + stbuf_addr[1] <= _T_671 @[el2_lsu_stbuf.scala 167:19] + node _T_672 = bits(stbuf_wr_en, 1, 1) @[el2_lsu_stbuf.scala 168:56] + node _T_673 = bits(_T_672, 0, 0) @[el2_lsu_stbuf.scala 168:66] + inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 508:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset - rvclkhdr_3.io.clk <= clock @[beh_lib.scala 354:16] - rvclkhdr_3.io.en <= _T_673 @[beh_lib.scala 355:15] - rvclkhdr_3.io.scan_mode <= io.scan_mode @[beh_lib.scala 356:22] - reg _T_674 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[beh_lib.scala 358:14] - _T_674 <= stbuf_datain[1] @[beh_lib.scala 358:14] - stbuf_data[1] <= _T_674 @[el2_lsu_stbuf.scala 174:20] - node _T_675 = bits(stbuf_wr_en, 2, 2) @[el2_lsu_stbuf.scala 172:58] - node _T_676 = bits(_T_675, 0, 0) @[el2_lsu_stbuf.scala 172:68] - inst rvclkhdr_4 of rvclkhdr_4 @[beh_lib.scala 352:21] + rvclkhdr_3.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_3.io.en <= _T_673 @[el2_lib.scala 511:17] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_674 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_674 <= stbuf_datain[1] @[el2_lib.scala 514:16] + stbuf_data[1] <= _T_674 @[el2_lsu_stbuf.scala 168:19] + node _T_675 = bits(stbuf_wr_en, 2, 2) @[el2_lsu_stbuf.scala 167:56] + node _T_676 = bits(_T_675, 0, 0) @[el2_lsu_stbuf.scala 167:66] + inst rvclkhdr_4 of rvclkhdr_4 @[el2_lib.scala 508:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset - rvclkhdr_4.io.clk <= clock @[beh_lib.scala 354:16] - rvclkhdr_4.io.en <= _T_676 @[beh_lib.scala 355:15] - rvclkhdr_4.io.scan_mode <= io.scan_mode @[beh_lib.scala 356:22] - reg _T_677 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[beh_lib.scala 358:14] - _T_677 <= stbuf_addrin[2] @[beh_lib.scala 358:14] - stbuf_addr[2] <= _T_677 @[el2_lsu_stbuf.scala 172:21] - node _T_678 = bits(stbuf_wr_en, 2, 2) @[el2_lsu_stbuf.scala 174:57] - node _T_679 = bits(_T_678, 0, 0) @[el2_lsu_stbuf.scala 174:67] - inst rvclkhdr_5 of rvclkhdr_5 @[beh_lib.scala 352:21] + rvclkhdr_4.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_4.io.en <= _T_676 @[el2_lib.scala 511:17] + rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_677 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_677 <= stbuf_addrin[2] @[el2_lib.scala 514:16] + stbuf_addr[2] <= _T_677 @[el2_lsu_stbuf.scala 167:19] + node _T_678 = bits(stbuf_wr_en, 2, 2) @[el2_lsu_stbuf.scala 168:56] + node _T_679 = bits(_T_678, 0, 0) @[el2_lsu_stbuf.scala 168:66] + inst rvclkhdr_5 of rvclkhdr_5 @[el2_lib.scala 508:23] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset - rvclkhdr_5.io.clk <= clock @[beh_lib.scala 354:16] - rvclkhdr_5.io.en <= _T_679 @[beh_lib.scala 355:15] - rvclkhdr_5.io.scan_mode <= io.scan_mode @[beh_lib.scala 356:22] - reg _T_680 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[beh_lib.scala 358:14] - _T_680 <= stbuf_datain[2] @[beh_lib.scala 358:14] - stbuf_data[2] <= _T_680 @[el2_lsu_stbuf.scala 174:20] - node _T_681 = bits(stbuf_wr_en, 3, 3) @[el2_lsu_stbuf.scala 172:58] - node _T_682 = bits(_T_681, 0, 0) @[el2_lsu_stbuf.scala 172:68] - inst rvclkhdr_6 of rvclkhdr_6 @[beh_lib.scala 352:21] + rvclkhdr_5.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_5.io.en <= _T_679 @[el2_lib.scala 511:17] + rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_680 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_680 <= stbuf_datain[2] @[el2_lib.scala 514:16] + stbuf_data[2] <= _T_680 @[el2_lsu_stbuf.scala 168:19] + node _T_681 = bits(stbuf_wr_en, 3, 3) @[el2_lsu_stbuf.scala 167:56] + node _T_682 = bits(_T_681, 0, 0) @[el2_lsu_stbuf.scala 167:66] + inst rvclkhdr_6 of rvclkhdr_6 @[el2_lib.scala 508:23] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset - rvclkhdr_6.io.clk <= clock @[beh_lib.scala 354:16] - rvclkhdr_6.io.en <= _T_682 @[beh_lib.scala 355:15] - rvclkhdr_6.io.scan_mode <= io.scan_mode @[beh_lib.scala 356:22] - reg _T_683 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[beh_lib.scala 358:14] - _T_683 <= stbuf_addrin[3] @[beh_lib.scala 358:14] - stbuf_addr[3] <= _T_683 @[el2_lsu_stbuf.scala 172:21] - node _T_684 = bits(stbuf_wr_en, 3, 3) @[el2_lsu_stbuf.scala 174:57] - node _T_685 = bits(_T_684, 0, 0) @[el2_lsu_stbuf.scala 174:67] - inst rvclkhdr_7 of rvclkhdr_7 @[beh_lib.scala 352:21] + rvclkhdr_6.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_6.io.en <= _T_682 @[el2_lib.scala 511:17] + rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_683 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_683 <= stbuf_addrin[3] @[el2_lib.scala 514:16] + stbuf_addr[3] <= _T_683 @[el2_lsu_stbuf.scala 167:19] + node _T_684 = bits(stbuf_wr_en, 3, 3) @[el2_lsu_stbuf.scala 168:56] + node _T_685 = bits(_T_684, 0, 0) @[el2_lsu_stbuf.scala 168:66] + inst rvclkhdr_7 of rvclkhdr_7 @[el2_lib.scala 508:23] rvclkhdr_7.clock <= clock rvclkhdr_7.reset <= reset - rvclkhdr_7.io.clk <= clock @[beh_lib.scala 354:16] - rvclkhdr_7.io.en <= _T_685 @[beh_lib.scala 355:15] - rvclkhdr_7.io.scan_mode <= io.scan_mode @[beh_lib.scala 356:22] - reg _T_686 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[beh_lib.scala 358:14] - _T_686 <= stbuf_datain[3] @[beh_lib.scala 358:14] - stbuf_data[3] <= _T_686 @[el2_lsu_stbuf.scala 174:20] - reg _T_687 : UInt<1>, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_stbuf.scala 176:53] - _T_687 <= ldst_dual_d @[el2_lsu_stbuf.scala 176:53] - ldst_dual_m <= _T_687 @[el2_lsu_stbuf.scala 176:43] - reg _T_688 : UInt<1>, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_stbuf.scala 177:53] - _T_688 <= ldst_dual_m @[el2_lsu_stbuf.scala 177:53] - ldst_dual_r <= _T_688 @[el2_lsu_stbuf.scala 177:43] - node _T_689 = dshr(stbuf_vld, RdPtr) @[el2_lsu_stbuf.scala 180:44] - node _T_690 = bits(_T_689, 0, 0) @[el2_lsu_stbuf.scala 180:44] - node _T_691 = dshr(stbuf_dma_kill, RdPtr) @[el2_lsu_stbuf.scala 180:68] - node _T_692 = bits(_T_691, 0, 0) @[el2_lsu_stbuf.scala 180:68] - node _T_693 = and(_T_690, _T_692) @[el2_lsu_stbuf.scala 180:52] - io.stbuf_reqvld_flushed_any <= _T_693 @[el2_lsu_stbuf.scala 180:32] - node _T_694 = dshr(stbuf_vld, RdPtr) @[el2_lsu_stbuf.scala 181:37] - node _T_695 = bits(_T_694, 0, 0) @[el2_lsu_stbuf.scala 181:37] - node _T_696 = dshr(stbuf_dma_kill, RdPtr) @[el2_lsu_stbuf.scala 181:62] - node _T_697 = bits(_T_696, 0, 0) @[el2_lsu_stbuf.scala 181:62] - node _T_698 = eq(_T_697, UInt<1>("h00")) @[el2_lsu_stbuf.scala 181:47] - node _T_699 = and(_T_695, _T_698) @[el2_lsu_stbuf.scala 181:45] - node _T_700 = orr(stbuf_dma_kill_en) @[el2_lsu_stbuf.scala 181:92] - node _T_701 = eq(_T_700, UInt<1>("h00")) @[el2_lsu_stbuf.scala 181:72] - node _T_702 = and(_T_699, _T_701) @[el2_lsu_stbuf.scala 181:70] - io.stbuf_reqvld_any <= _T_702 @[el2_lsu_stbuf.scala 181:25] - io.stbuf_addr_any <= stbuf_addr[RdPtr] @[el2_lsu_stbuf.scala 182:23] - io.stbuf_data_any <= stbuf_data[RdPtr] @[el2_lsu_stbuf.scala 183:23] - node _T_703 = eq(dual_stbuf_write_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 185:44] - node _T_704 = and(io.ldst_stbuf_reqvld_r, _T_703) @[el2_lsu_stbuf.scala 185:42] - node _T_705 = or(store_coalesce_hi_r, store_coalesce_lo_r) @[el2_lsu_stbuf.scala 185:88] - node _T_706 = eq(_T_705, UInt<1>("h00")) @[el2_lsu_stbuf.scala 185:66] - node _T_707 = and(_T_704, _T_706) @[el2_lsu_stbuf.scala 185:64] - node _T_708 = and(io.ldst_stbuf_reqvld_r, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 186:31] - node _T_709 = and(store_coalesce_hi_r, store_coalesce_lo_r) @[el2_lsu_stbuf.scala 186:77] - node _T_710 = eq(_T_709, UInt<1>("h00")) @[el2_lsu_stbuf.scala 186:55] - node _T_711 = and(_T_708, _T_710) @[el2_lsu_stbuf.scala 186:53] - node _T_712 = or(_T_707, _T_711) @[el2_lsu_stbuf.scala 185:113] - node WrPtrEn = bits(_T_712, 0, 0) @[el2_lsu_stbuf.scala 186:102] - node _T_713 = and(io.ldst_stbuf_reqvld_r, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 187:47] - node _T_714 = or(store_coalesce_hi_r, store_coalesce_lo_r) @[el2_lsu_stbuf.scala 187:92] - node _T_715 = eq(_T_714, UInt<1>("h00")) @[el2_lsu_stbuf.scala 187:70] - node _T_716 = and(_T_713, _T_715) @[el2_lsu_stbuf.scala 187:68] - node _T_717 = bits(_T_716, 0, 0) @[el2_lsu_stbuf.scala 187:116] - node NxtWrPtr = mux(_T_717, WrPtrPlus2, WrPtrPlus1) @[el2_lsu_stbuf.scala 187:22] - node RdPtrEn = or(io.lsu_stbuf_commit_any, io.stbuf_reqvld_flushed_any) @[el2_lsu_stbuf.scala 188:43] + rvclkhdr_7.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_7.io.en <= _T_685 @[el2_lib.scala 511:17] + rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_686 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_686 <= stbuf_datain[3] @[el2_lib.scala 514:16] + stbuf_data[3] <= _T_686 @[el2_lsu_stbuf.scala 168:19] + reg _T_687 : UInt<1>, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_stbuf.scala 170:52] + _T_687 <= ldst_dual_d @[el2_lsu_stbuf.scala 170:52] + ldst_dual_m <= _T_687 @[el2_lsu_stbuf.scala 170:42] + reg _T_688 : UInt<1>, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_stbuf.scala 171:52] + _T_688 <= ldst_dual_m @[el2_lsu_stbuf.scala 171:52] + ldst_dual_r <= _T_688 @[el2_lsu_stbuf.scala 171:42] + node _T_689 = dshr(stbuf_vld, RdPtr) @[el2_lsu_stbuf.scala 174:43] + node _T_690 = bits(_T_689, 0, 0) @[el2_lsu_stbuf.scala 174:43] + node _T_691 = dshr(stbuf_dma_kill, RdPtr) @[el2_lsu_stbuf.scala 174:67] + node _T_692 = bits(_T_691, 0, 0) @[el2_lsu_stbuf.scala 174:67] + node _T_693 = and(_T_690, _T_692) @[el2_lsu_stbuf.scala 174:51] + io.stbuf_reqvld_flushed_any <= _T_693 @[el2_lsu_stbuf.scala 174:31] + node _T_694 = dshr(stbuf_vld, RdPtr) @[el2_lsu_stbuf.scala 175:36] + node _T_695 = bits(_T_694, 0, 0) @[el2_lsu_stbuf.scala 175:36] + node _T_696 = dshr(stbuf_dma_kill, RdPtr) @[el2_lsu_stbuf.scala 175:61] + node _T_697 = bits(_T_696, 0, 0) @[el2_lsu_stbuf.scala 175:61] + node _T_698 = eq(_T_697, UInt<1>("h00")) @[el2_lsu_stbuf.scala 175:46] + node _T_699 = and(_T_695, _T_698) @[el2_lsu_stbuf.scala 175:44] + node _T_700 = orr(stbuf_dma_kill_en) @[el2_lsu_stbuf.scala 175:91] + node _T_701 = eq(_T_700, UInt<1>("h00")) @[el2_lsu_stbuf.scala 175:71] + node _T_702 = and(_T_699, _T_701) @[el2_lsu_stbuf.scala 175:69] + io.stbuf_reqvld_any <= _T_702 @[el2_lsu_stbuf.scala 175:24] + io.stbuf_addr_any <= stbuf_addr[RdPtr] @[el2_lsu_stbuf.scala 176:22] + io.stbuf_data_any <= stbuf_data[RdPtr] @[el2_lsu_stbuf.scala 177:22] + node _T_703 = eq(dual_stbuf_write_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 179:44] + node _T_704 = and(io.ldst_stbuf_reqvld_r, _T_703) @[el2_lsu_stbuf.scala 179:42] + node _T_705 = or(store_coalesce_hi_r, store_coalesce_lo_r) @[el2_lsu_stbuf.scala 179:88] + node _T_706 = eq(_T_705, UInt<1>("h00")) @[el2_lsu_stbuf.scala 179:66] + node _T_707 = and(_T_704, _T_706) @[el2_lsu_stbuf.scala 179:64] + node _T_708 = and(io.ldst_stbuf_reqvld_r, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 180:30] + node _T_709 = and(store_coalesce_hi_r, store_coalesce_lo_r) @[el2_lsu_stbuf.scala 180:76] + node _T_710 = eq(_T_709, UInt<1>("h00")) @[el2_lsu_stbuf.scala 180:54] + node _T_711 = and(_T_708, _T_710) @[el2_lsu_stbuf.scala 180:52] + node _T_712 = or(_T_707, _T_711) @[el2_lsu_stbuf.scala 179:113] + node WrPtrEn = bits(_T_712, 0, 0) @[el2_lsu_stbuf.scala 180:101] + node _T_713 = and(io.ldst_stbuf_reqvld_r, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 181:46] + node _T_714 = or(store_coalesce_hi_r, store_coalesce_lo_r) @[el2_lsu_stbuf.scala 181:91] + node _T_715 = eq(_T_714, UInt<1>("h00")) @[el2_lsu_stbuf.scala 181:69] + node _T_716 = and(_T_713, _T_715) @[el2_lsu_stbuf.scala 181:67] + node _T_717 = bits(_T_716, 0, 0) @[el2_lsu_stbuf.scala 181:115] + node NxtWrPtr = mux(_T_717, WrPtrPlus2, WrPtrPlus1) @[el2_lsu_stbuf.scala 181:21] + node RdPtrEn = or(io.lsu_stbuf_commit_any, io.stbuf_reqvld_flushed_any) @[el2_lsu_stbuf.scala 182:42] reg _T_718 : UInt, io.lsu_stbuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when WrPtrEn : @[Reg.scala 28:19] _T_718 <= NxtWrPtr @[Reg.scala 28:23] skip @[Reg.scala 28:19] - WrPtr <= _T_718 @[el2_lsu_stbuf.scala 191:41] + WrPtr <= _T_718 @[el2_lsu_stbuf.scala 185:41] reg _T_719 : UInt, io.lsu_stbuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when RdPtrEn : @[Reg.scala 28:19] _T_719 <= RdPtrPlus1 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - RdPtr <= _T_719 @[el2_lsu_stbuf.scala 192:41] - node _T_720 = bits(stbuf_vld, 0, 0) @[el2_lsu_stbuf.scala 194:87] + RdPtr <= _T_719 @[el2_lsu_stbuf.scala 186:41] + node _T_720 = bits(stbuf_vld, 0, 0) @[el2_lsu_stbuf.scala 188:86] node _T_721 = cat(UInt<3>("h00"), _T_720) @[Cat.scala 29:58] - node _T_722 = bits(stbuf_vld, 1, 1) @[el2_lsu_stbuf.scala 194:87] + node _T_722 = bits(stbuf_vld, 1, 1) @[el2_lsu_stbuf.scala 188:86] node _T_723 = cat(UInt<3>("h00"), _T_722) @[Cat.scala 29:58] - node _T_724 = bits(stbuf_vld, 2, 2) @[el2_lsu_stbuf.scala 194:87] + node _T_724 = bits(stbuf_vld, 2, 2) @[el2_lsu_stbuf.scala 188:86] node _T_725 = cat(UInt<3>("h00"), _T_724) @[Cat.scala 29:58] - node _T_726 = bits(stbuf_vld, 3, 3) @[el2_lsu_stbuf.scala 194:87] + node _T_726 = bits(stbuf_vld, 3, 3) @[el2_lsu_stbuf.scala 188:86] node _T_727 = cat(UInt<3>("h00"), _T_726) @[Cat.scala 29:58] - wire _T_728 : UInt<4>[4] @[el2_lsu_stbuf.scala 194:60] - _T_728[0] <= _T_721 @[el2_lsu_stbuf.scala 194:60] - _T_728[1] <= _T_723 @[el2_lsu_stbuf.scala 194:60] - _T_728[2] <= _T_725 @[el2_lsu_stbuf.scala 194:60] - _T_728[3] <= _T_727 @[el2_lsu_stbuf.scala 194:60] - node _T_729 = add(_T_728[0], _T_728[1]) @[el2_lsu_stbuf.scala 194:102] - node _T_730 = tail(_T_729, 1) @[el2_lsu_stbuf.scala 194:102] - node _T_731 = add(_T_730, _T_728[2]) @[el2_lsu_stbuf.scala 194:102] - node _T_732 = tail(_T_731, 1) @[el2_lsu_stbuf.scala 194:102] - node _T_733 = add(_T_732, _T_728[3]) @[el2_lsu_stbuf.scala 194:102] - node stbuf_numvld_any = tail(_T_733, 1) @[el2_lsu_stbuf.scala 194:102] - node _T_734 = and(io.lsu_pkt_m.valid, io.lsu_pkt_m.store) @[el2_lsu_stbuf.scala 195:40] - node _T_735 = and(_T_734, io.addr_in_dccm_m) @[el2_lsu_stbuf.scala 195:61] - node _T_736 = eq(io.lsu_pkt_m.dma, UInt<1>("h00")) @[el2_lsu_stbuf.scala 195:83] - node isdccmst_m = and(_T_735, _T_736) @[el2_lsu_stbuf.scala 195:81] - node _T_737 = and(io.lsu_pkt_r.valid, io.lsu_pkt_r.store) @[el2_lsu_stbuf.scala 196:40] - node _T_738 = and(_T_737, io.addr_in_dccm_r) @[el2_lsu_stbuf.scala 196:61] - node _T_739 = eq(io.lsu_pkt_r.dma, UInt<1>("h00")) @[el2_lsu_stbuf.scala 196:83] - node isdccmst_r = and(_T_738, _T_739) @[el2_lsu_stbuf.scala 196:81] + wire _T_728 : UInt<4>[4] @[el2_lsu_stbuf.scala 188:59] + _T_728[0] <= _T_721 @[el2_lsu_stbuf.scala 188:59] + _T_728[1] <= _T_723 @[el2_lsu_stbuf.scala 188:59] + _T_728[2] <= _T_725 @[el2_lsu_stbuf.scala 188:59] + _T_728[3] <= _T_727 @[el2_lsu_stbuf.scala 188:59] + node _T_729 = add(_T_728[0], _T_728[1]) @[el2_lsu_stbuf.scala 188:101] + node _T_730 = tail(_T_729, 1) @[el2_lsu_stbuf.scala 188:101] + node _T_731 = add(_T_730, _T_728[2]) @[el2_lsu_stbuf.scala 188:101] + node _T_732 = tail(_T_731, 1) @[el2_lsu_stbuf.scala 188:101] + node _T_733 = add(_T_732, _T_728[3]) @[el2_lsu_stbuf.scala 188:101] + node stbuf_numvld_any = tail(_T_733, 1) @[el2_lsu_stbuf.scala 188:101] + node _T_734 = and(io.lsu_pkt_m.valid, io.lsu_pkt_m.bits.store) @[el2_lsu_stbuf.scala 189:39] + node _T_735 = and(_T_734, io.addr_in_dccm_m) @[el2_lsu_stbuf.scala 189:65] + node _T_736 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[el2_lsu_stbuf.scala 189:87] + node isdccmst_m = and(_T_735, _T_736) @[el2_lsu_stbuf.scala 189:85] + node _T_737 = and(io.lsu_pkt_r.valid, io.lsu_pkt_r.bits.store) @[el2_lsu_stbuf.scala 190:39] + node _T_738 = and(_T_737, io.addr_in_dccm_r) @[el2_lsu_stbuf.scala 190:65] + node _T_739 = eq(io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[el2_lsu_stbuf.scala 190:87] + node isdccmst_r = and(_T_738, _T_739) @[el2_lsu_stbuf.scala 190:85] node _T_740 = cat(UInt<1>("h00"), isdccmst_m) @[Cat.scala 29:58] - node _T_741 = and(isdccmst_m, ldst_dual_m) @[el2_lsu_stbuf.scala 198:63] - node _T_742 = dshl(_T_740, _T_741) @[el2_lsu_stbuf.scala 198:48] - stbuf_specvld_m <= _T_742 @[el2_lsu_stbuf.scala 198:20] + node _T_741 = and(isdccmst_m, ldst_dual_m) @[el2_lsu_stbuf.scala 192:62] + node _T_742 = dshl(_T_740, _T_741) @[el2_lsu_stbuf.scala 192:47] + stbuf_specvld_m <= _T_742 @[el2_lsu_stbuf.scala 192:19] node _T_743 = cat(UInt<1>("h00"), isdccmst_r) @[Cat.scala 29:58] - node _T_744 = and(isdccmst_r, ldst_dual_r) @[el2_lsu_stbuf.scala 199:63] - node _T_745 = dshl(_T_743, _T_744) @[el2_lsu_stbuf.scala 199:48] - stbuf_specvld_r <= _T_745 @[el2_lsu_stbuf.scala 199:20] + node _T_744 = and(isdccmst_r, ldst_dual_r) @[el2_lsu_stbuf.scala 193:62] + node _T_745 = dshl(_T_743, _T_744) @[el2_lsu_stbuf.scala 193:47] + stbuf_specvld_r <= _T_745 @[el2_lsu_stbuf.scala 193:19] node _T_746 = cat(UInt<2>("h00"), stbuf_specvld_m) @[Cat.scala 29:58] - node _T_747 = add(stbuf_numvld_any, _T_746) @[el2_lsu_stbuf.scala 200:45] - node _T_748 = tail(_T_747, 1) @[el2_lsu_stbuf.scala 200:45] + node _T_747 = add(stbuf_numvld_any, _T_746) @[el2_lsu_stbuf.scala 194:44] + node _T_748 = tail(_T_747, 1) @[el2_lsu_stbuf.scala 194:44] node _T_749 = cat(UInt<2>("h00"), stbuf_specvld_r) @[Cat.scala 29:58] - node _T_750 = add(_T_748, _T_749) @[el2_lsu_stbuf.scala 200:79] - node stbuf_specvld_any = tail(_T_750, 1) @[el2_lsu_stbuf.scala 200:79] - node _T_751 = eq(ldst_dual_d, UInt<1>("h00")) @[el2_lsu_stbuf.scala 202:35] - node _T_752 = and(_T_751, io.dec_lsu_valid_raw_d) @[el2_lsu_stbuf.scala 202:48] - node _T_753 = bits(_T_752, 0, 0) @[el2_lsu_stbuf.scala 202:74] - node _T_754 = geq(stbuf_specvld_any, UInt<3>("h04")) @[el2_lsu_stbuf.scala 202:100] - node _T_755 = geq(stbuf_specvld_any, UInt<2>("h03")) @[el2_lsu_stbuf.scala 202:141] - node _T_756 = mux(_T_753, _T_754, _T_755) @[el2_lsu_stbuf.scala 202:33] - io.lsu_stbuf_full_any <= _T_756 @[el2_lsu_stbuf.scala 202:27] - node _T_757 = eq(stbuf_numvld_any, UInt<1>("h00")) @[el2_lsu_stbuf.scala 203:47] - io.lsu_stbuf_empty_any <= _T_757 @[el2_lsu_stbuf.scala 203:27] - node cmpen_hi_m = and(io.lsu_cmpen_m, ldst_dual_m) @[el2_lsu_stbuf.scala 205:37] - node _T_758 = bits(io.end_addr_m, 15, 2) @[el2_lsu_stbuf.scala 206:33] - cmpaddr_hi_m <= _T_758 @[el2_lsu_stbuf.scala 206:17] - node _T_759 = bits(io.lsu_addr_m, 15, 2) @[el2_lsu_stbuf.scala 209:34] - cmpaddr_lo_m <= _T_759 @[el2_lsu_stbuf.scala 209:18] - node _T_760 = bits(stbuf_addr[0], 15, 2) @[el2_lsu_stbuf.scala 212:74] - node _T_761 = bits(cmpaddr_hi_m, 13, 0) @[el2_lsu_stbuf.scala 212:132] - node _T_762 = eq(_T_760, _T_761) @[el2_lsu_stbuf.scala 212:116] - node _T_763 = bits(stbuf_vld, 0, 0) @[el2_lsu_stbuf.scala 212:151] - node _T_764 = and(_T_762, _T_763) @[el2_lsu_stbuf.scala 212:140] - node _T_765 = bits(stbuf_dma_kill, 0, 0) @[el2_lsu_stbuf.scala 212:172] - node _T_766 = eq(_T_765, UInt<1>("h00")) @[el2_lsu_stbuf.scala 212:157] - node _T_767 = and(_T_764, _T_766) @[el2_lsu_stbuf.scala 212:155] - node _T_768 = and(_T_767, io.addr_in_dccm_m) @[el2_lsu_stbuf.scala 212:176] - node _T_769 = bits(stbuf_addr[1], 15, 2) @[el2_lsu_stbuf.scala 212:74] - node _T_770 = bits(cmpaddr_hi_m, 13, 0) @[el2_lsu_stbuf.scala 212:132] - node _T_771 = eq(_T_769, _T_770) @[el2_lsu_stbuf.scala 212:116] - node _T_772 = bits(stbuf_vld, 1, 1) @[el2_lsu_stbuf.scala 212:151] - node _T_773 = and(_T_771, _T_772) @[el2_lsu_stbuf.scala 212:140] - node _T_774 = bits(stbuf_dma_kill, 1, 1) @[el2_lsu_stbuf.scala 212:172] - node _T_775 = eq(_T_774, UInt<1>("h00")) @[el2_lsu_stbuf.scala 212:157] - node _T_776 = and(_T_773, _T_775) @[el2_lsu_stbuf.scala 212:155] - node _T_777 = and(_T_776, io.addr_in_dccm_m) @[el2_lsu_stbuf.scala 212:176] - node _T_778 = bits(stbuf_addr[2], 15, 2) @[el2_lsu_stbuf.scala 212:74] - node _T_779 = bits(cmpaddr_hi_m, 13, 0) @[el2_lsu_stbuf.scala 212:132] - node _T_780 = eq(_T_778, _T_779) @[el2_lsu_stbuf.scala 212:116] - node _T_781 = bits(stbuf_vld, 2, 2) @[el2_lsu_stbuf.scala 212:151] - node _T_782 = and(_T_780, _T_781) @[el2_lsu_stbuf.scala 212:140] - node _T_783 = bits(stbuf_dma_kill, 2, 2) @[el2_lsu_stbuf.scala 212:172] - node _T_784 = eq(_T_783, UInt<1>("h00")) @[el2_lsu_stbuf.scala 212:157] - node _T_785 = and(_T_782, _T_784) @[el2_lsu_stbuf.scala 212:155] - node _T_786 = and(_T_785, io.addr_in_dccm_m) @[el2_lsu_stbuf.scala 212:176] - node _T_787 = bits(stbuf_addr[3], 15, 2) @[el2_lsu_stbuf.scala 212:74] - node _T_788 = bits(cmpaddr_hi_m, 13, 0) @[el2_lsu_stbuf.scala 212:132] - node _T_789 = eq(_T_787, _T_788) @[el2_lsu_stbuf.scala 212:116] - node _T_790 = bits(stbuf_vld, 3, 3) @[el2_lsu_stbuf.scala 212:151] - node _T_791 = and(_T_789, _T_790) @[el2_lsu_stbuf.scala 212:140] - node _T_792 = bits(stbuf_dma_kill, 3, 3) @[el2_lsu_stbuf.scala 212:172] - node _T_793 = eq(_T_792, UInt<1>("h00")) @[el2_lsu_stbuf.scala 212:157] - node _T_794 = and(_T_791, _T_793) @[el2_lsu_stbuf.scala 212:155] - node _T_795 = and(_T_794, io.addr_in_dccm_m) @[el2_lsu_stbuf.scala 212:176] + node _T_750 = add(_T_748, _T_749) @[el2_lsu_stbuf.scala 194:78] + node stbuf_specvld_any = tail(_T_750, 1) @[el2_lsu_stbuf.scala 194:78] + node _T_751 = eq(ldst_dual_d, UInt<1>("h00")) @[el2_lsu_stbuf.scala 196:34] + node _T_752 = and(_T_751, io.dec_lsu_valid_raw_d) @[el2_lsu_stbuf.scala 196:47] + node _T_753 = bits(_T_752, 0, 0) @[el2_lsu_stbuf.scala 196:73] + node _T_754 = geq(stbuf_specvld_any, UInt<3>("h04")) @[el2_lsu_stbuf.scala 196:99] + node _T_755 = geq(stbuf_specvld_any, UInt<2>("h03")) @[el2_lsu_stbuf.scala 196:140] + node _T_756 = mux(_T_753, _T_754, _T_755) @[el2_lsu_stbuf.scala 196:32] + io.lsu_stbuf_full_any <= _T_756 @[el2_lsu_stbuf.scala 196:26] + node _T_757 = eq(stbuf_numvld_any, UInt<1>("h00")) @[el2_lsu_stbuf.scala 197:46] + io.lsu_stbuf_empty_any <= _T_757 @[el2_lsu_stbuf.scala 197:26] + node cmpen_hi_m = and(io.lsu_cmpen_m, ldst_dual_m) @[el2_lsu_stbuf.scala 199:36] + node _T_758 = bits(io.end_addr_m, 15, 2) @[el2_lsu_stbuf.scala 200:32] + cmpaddr_hi_m <= _T_758 @[el2_lsu_stbuf.scala 200:16] + node _T_759 = bits(io.lsu_addr_m, 15, 2) @[el2_lsu_stbuf.scala 203:33] + cmpaddr_lo_m <= _T_759 @[el2_lsu_stbuf.scala 203:17] + node _T_760 = bits(stbuf_addr[0], 15, 2) @[el2_lsu_stbuf.scala 206:73] + node _T_761 = bits(cmpaddr_hi_m, 13, 0) @[el2_lsu_stbuf.scala 206:131] + node _T_762 = eq(_T_760, _T_761) @[el2_lsu_stbuf.scala 206:115] + node _T_763 = bits(stbuf_vld, 0, 0) @[el2_lsu_stbuf.scala 206:150] + node _T_764 = and(_T_762, _T_763) @[el2_lsu_stbuf.scala 206:139] + node _T_765 = bits(stbuf_dma_kill, 0, 0) @[el2_lsu_stbuf.scala 206:171] + node _T_766 = eq(_T_765, UInt<1>("h00")) @[el2_lsu_stbuf.scala 206:156] + node _T_767 = and(_T_764, _T_766) @[el2_lsu_stbuf.scala 206:154] + node _T_768 = and(_T_767, io.addr_in_dccm_m) @[el2_lsu_stbuf.scala 206:175] + node _T_769 = bits(stbuf_addr[1], 15, 2) @[el2_lsu_stbuf.scala 206:73] + node _T_770 = bits(cmpaddr_hi_m, 13, 0) @[el2_lsu_stbuf.scala 206:131] + node _T_771 = eq(_T_769, _T_770) @[el2_lsu_stbuf.scala 206:115] + node _T_772 = bits(stbuf_vld, 1, 1) @[el2_lsu_stbuf.scala 206:150] + node _T_773 = and(_T_771, _T_772) @[el2_lsu_stbuf.scala 206:139] + node _T_774 = bits(stbuf_dma_kill, 1, 1) @[el2_lsu_stbuf.scala 206:171] + node _T_775 = eq(_T_774, UInt<1>("h00")) @[el2_lsu_stbuf.scala 206:156] + node _T_776 = and(_T_773, _T_775) @[el2_lsu_stbuf.scala 206:154] + node _T_777 = and(_T_776, io.addr_in_dccm_m) @[el2_lsu_stbuf.scala 206:175] + node _T_778 = bits(stbuf_addr[2], 15, 2) @[el2_lsu_stbuf.scala 206:73] + node _T_779 = bits(cmpaddr_hi_m, 13, 0) @[el2_lsu_stbuf.scala 206:131] + node _T_780 = eq(_T_778, _T_779) @[el2_lsu_stbuf.scala 206:115] + node _T_781 = bits(stbuf_vld, 2, 2) @[el2_lsu_stbuf.scala 206:150] + node _T_782 = and(_T_780, _T_781) @[el2_lsu_stbuf.scala 206:139] + node _T_783 = bits(stbuf_dma_kill, 2, 2) @[el2_lsu_stbuf.scala 206:171] + node _T_784 = eq(_T_783, UInt<1>("h00")) @[el2_lsu_stbuf.scala 206:156] + node _T_785 = and(_T_782, _T_784) @[el2_lsu_stbuf.scala 206:154] + node _T_786 = and(_T_785, io.addr_in_dccm_m) @[el2_lsu_stbuf.scala 206:175] + node _T_787 = bits(stbuf_addr[3], 15, 2) @[el2_lsu_stbuf.scala 206:73] + node _T_788 = bits(cmpaddr_hi_m, 13, 0) @[el2_lsu_stbuf.scala 206:131] + node _T_789 = eq(_T_787, _T_788) @[el2_lsu_stbuf.scala 206:115] + node _T_790 = bits(stbuf_vld, 3, 3) @[el2_lsu_stbuf.scala 206:150] + node _T_791 = and(_T_789, _T_790) @[el2_lsu_stbuf.scala 206:139] + node _T_792 = bits(stbuf_dma_kill, 3, 3) @[el2_lsu_stbuf.scala 206:171] + node _T_793 = eq(_T_792, UInt<1>("h00")) @[el2_lsu_stbuf.scala 206:156] + node _T_794 = and(_T_791, _T_793) @[el2_lsu_stbuf.scala 206:154] + node _T_795 = and(_T_794, io.addr_in_dccm_m) @[el2_lsu_stbuf.scala 206:175] node _T_796 = cat(_T_795, _T_786) @[Cat.scala 29:58] node _T_797 = cat(_T_796, _T_777) @[Cat.scala 29:58] node stbuf_match_hi = cat(_T_797, _T_768) @[Cat.scala 29:58] - node _T_798 = bits(stbuf_addr[0], 15, 2) @[el2_lsu_stbuf.scala 213:74] - node _T_799 = bits(cmpaddr_lo_m, 13, 0) @[el2_lsu_stbuf.scala 213:132] - node _T_800 = eq(_T_798, _T_799) @[el2_lsu_stbuf.scala 213:116] - node _T_801 = bits(stbuf_vld, 0, 0) @[el2_lsu_stbuf.scala 213:151] - node _T_802 = and(_T_800, _T_801) @[el2_lsu_stbuf.scala 213:140] - node _T_803 = bits(stbuf_dma_kill, 0, 0) @[el2_lsu_stbuf.scala 213:172] - node _T_804 = eq(_T_803, UInt<1>("h00")) @[el2_lsu_stbuf.scala 213:157] - node _T_805 = and(_T_802, _T_804) @[el2_lsu_stbuf.scala 213:155] - node _T_806 = and(_T_805, io.addr_in_dccm_m) @[el2_lsu_stbuf.scala 213:176] - node _T_807 = bits(stbuf_addr[1], 15, 2) @[el2_lsu_stbuf.scala 213:74] - node _T_808 = bits(cmpaddr_lo_m, 13, 0) @[el2_lsu_stbuf.scala 213:132] - node _T_809 = eq(_T_807, _T_808) @[el2_lsu_stbuf.scala 213:116] - node _T_810 = bits(stbuf_vld, 1, 1) @[el2_lsu_stbuf.scala 213:151] - node _T_811 = and(_T_809, _T_810) @[el2_lsu_stbuf.scala 213:140] - node _T_812 = bits(stbuf_dma_kill, 1, 1) @[el2_lsu_stbuf.scala 213:172] - node _T_813 = eq(_T_812, UInt<1>("h00")) @[el2_lsu_stbuf.scala 213:157] - node _T_814 = and(_T_811, _T_813) @[el2_lsu_stbuf.scala 213:155] - node _T_815 = and(_T_814, io.addr_in_dccm_m) @[el2_lsu_stbuf.scala 213:176] - node _T_816 = bits(stbuf_addr[2], 15, 2) @[el2_lsu_stbuf.scala 213:74] - node _T_817 = bits(cmpaddr_lo_m, 13, 0) @[el2_lsu_stbuf.scala 213:132] - node _T_818 = eq(_T_816, _T_817) @[el2_lsu_stbuf.scala 213:116] - node _T_819 = bits(stbuf_vld, 2, 2) @[el2_lsu_stbuf.scala 213:151] - node _T_820 = and(_T_818, _T_819) @[el2_lsu_stbuf.scala 213:140] - node _T_821 = bits(stbuf_dma_kill, 2, 2) @[el2_lsu_stbuf.scala 213:172] - node _T_822 = eq(_T_821, UInt<1>("h00")) @[el2_lsu_stbuf.scala 213:157] - node _T_823 = and(_T_820, _T_822) @[el2_lsu_stbuf.scala 213:155] - node _T_824 = and(_T_823, io.addr_in_dccm_m) @[el2_lsu_stbuf.scala 213:176] - node _T_825 = bits(stbuf_addr[3], 15, 2) @[el2_lsu_stbuf.scala 213:74] - node _T_826 = bits(cmpaddr_lo_m, 13, 0) @[el2_lsu_stbuf.scala 213:132] - node _T_827 = eq(_T_825, _T_826) @[el2_lsu_stbuf.scala 213:116] - node _T_828 = bits(stbuf_vld, 3, 3) @[el2_lsu_stbuf.scala 213:151] - node _T_829 = and(_T_827, _T_828) @[el2_lsu_stbuf.scala 213:140] - node _T_830 = bits(stbuf_dma_kill, 3, 3) @[el2_lsu_stbuf.scala 213:172] - node _T_831 = eq(_T_830, UInt<1>("h00")) @[el2_lsu_stbuf.scala 213:157] - node _T_832 = and(_T_829, _T_831) @[el2_lsu_stbuf.scala 213:155] - node _T_833 = and(_T_832, io.addr_in_dccm_m) @[el2_lsu_stbuf.scala 213:176] + node _T_798 = bits(stbuf_addr[0], 15, 2) @[el2_lsu_stbuf.scala 207:73] + node _T_799 = bits(cmpaddr_lo_m, 13, 0) @[el2_lsu_stbuf.scala 207:131] + node _T_800 = eq(_T_798, _T_799) @[el2_lsu_stbuf.scala 207:115] + node _T_801 = bits(stbuf_vld, 0, 0) @[el2_lsu_stbuf.scala 207:150] + node _T_802 = and(_T_800, _T_801) @[el2_lsu_stbuf.scala 207:139] + node _T_803 = bits(stbuf_dma_kill, 0, 0) @[el2_lsu_stbuf.scala 207:171] + node _T_804 = eq(_T_803, UInt<1>("h00")) @[el2_lsu_stbuf.scala 207:156] + node _T_805 = and(_T_802, _T_804) @[el2_lsu_stbuf.scala 207:154] + node _T_806 = and(_T_805, io.addr_in_dccm_m) @[el2_lsu_stbuf.scala 207:175] + node _T_807 = bits(stbuf_addr[1], 15, 2) @[el2_lsu_stbuf.scala 207:73] + node _T_808 = bits(cmpaddr_lo_m, 13, 0) @[el2_lsu_stbuf.scala 207:131] + node _T_809 = eq(_T_807, _T_808) @[el2_lsu_stbuf.scala 207:115] + node _T_810 = bits(stbuf_vld, 1, 1) @[el2_lsu_stbuf.scala 207:150] + node _T_811 = and(_T_809, _T_810) @[el2_lsu_stbuf.scala 207:139] + node _T_812 = bits(stbuf_dma_kill, 1, 1) @[el2_lsu_stbuf.scala 207:171] + node _T_813 = eq(_T_812, UInt<1>("h00")) @[el2_lsu_stbuf.scala 207:156] + node _T_814 = and(_T_811, _T_813) @[el2_lsu_stbuf.scala 207:154] + node _T_815 = and(_T_814, io.addr_in_dccm_m) @[el2_lsu_stbuf.scala 207:175] + node _T_816 = bits(stbuf_addr[2], 15, 2) @[el2_lsu_stbuf.scala 207:73] + node _T_817 = bits(cmpaddr_lo_m, 13, 0) @[el2_lsu_stbuf.scala 207:131] + node _T_818 = eq(_T_816, _T_817) @[el2_lsu_stbuf.scala 207:115] + node _T_819 = bits(stbuf_vld, 2, 2) @[el2_lsu_stbuf.scala 207:150] + node _T_820 = and(_T_818, _T_819) @[el2_lsu_stbuf.scala 207:139] + node _T_821 = bits(stbuf_dma_kill, 2, 2) @[el2_lsu_stbuf.scala 207:171] + node _T_822 = eq(_T_821, UInt<1>("h00")) @[el2_lsu_stbuf.scala 207:156] + node _T_823 = and(_T_820, _T_822) @[el2_lsu_stbuf.scala 207:154] + node _T_824 = and(_T_823, io.addr_in_dccm_m) @[el2_lsu_stbuf.scala 207:175] + node _T_825 = bits(stbuf_addr[3], 15, 2) @[el2_lsu_stbuf.scala 207:73] + node _T_826 = bits(cmpaddr_lo_m, 13, 0) @[el2_lsu_stbuf.scala 207:131] + node _T_827 = eq(_T_825, _T_826) @[el2_lsu_stbuf.scala 207:115] + node _T_828 = bits(stbuf_vld, 3, 3) @[el2_lsu_stbuf.scala 207:150] + node _T_829 = and(_T_827, _T_828) @[el2_lsu_stbuf.scala 207:139] + node _T_830 = bits(stbuf_dma_kill, 3, 3) @[el2_lsu_stbuf.scala 207:171] + node _T_831 = eq(_T_830, UInt<1>("h00")) @[el2_lsu_stbuf.scala 207:156] + node _T_832 = and(_T_829, _T_831) @[el2_lsu_stbuf.scala 207:154] + node _T_833 = and(_T_832, io.addr_in_dccm_m) @[el2_lsu_stbuf.scala 207:175] node _T_834 = cat(_T_833, _T_824) @[Cat.scala 29:58] node _T_835 = cat(_T_834, _T_815) @[Cat.scala 29:58] node stbuf_match_lo = cat(_T_835, _T_806) @[Cat.scala 29:58] - node _T_836 = bits(stbuf_match_hi, 0, 0) @[el2_lsu_stbuf.scala 214:75] - node _T_837 = bits(stbuf_match_lo, 0, 0) @[el2_lsu_stbuf.scala 214:95] - node _T_838 = or(_T_836, _T_837) @[el2_lsu_stbuf.scala 214:79] - node _T_839 = and(_T_838, io.lsu_pkt_m.valid) @[el2_lsu_stbuf.scala 214:100] - node _T_840 = and(_T_839, io.lsu_pkt_m.dma) @[el2_lsu_stbuf.scala 214:121] - node _T_841 = and(_T_840, io.lsu_pkt_m.store) @[el2_lsu_stbuf.scala 214:140] - node _T_842 = bits(stbuf_match_hi, 1, 1) @[el2_lsu_stbuf.scala 214:75] - node _T_843 = bits(stbuf_match_lo, 1, 1) @[el2_lsu_stbuf.scala 214:95] - node _T_844 = or(_T_842, _T_843) @[el2_lsu_stbuf.scala 214:79] - node _T_845 = and(_T_844, io.lsu_pkt_m.valid) @[el2_lsu_stbuf.scala 214:100] - node _T_846 = and(_T_845, io.lsu_pkt_m.dma) @[el2_lsu_stbuf.scala 214:121] - node _T_847 = and(_T_846, io.lsu_pkt_m.store) @[el2_lsu_stbuf.scala 214:140] - node _T_848 = bits(stbuf_match_hi, 2, 2) @[el2_lsu_stbuf.scala 214:75] - node _T_849 = bits(stbuf_match_lo, 2, 2) @[el2_lsu_stbuf.scala 214:95] - node _T_850 = or(_T_848, _T_849) @[el2_lsu_stbuf.scala 214:79] - node _T_851 = and(_T_850, io.lsu_pkt_m.valid) @[el2_lsu_stbuf.scala 214:100] - node _T_852 = and(_T_851, io.lsu_pkt_m.dma) @[el2_lsu_stbuf.scala 214:121] - node _T_853 = and(_T_852, io.lsu_pkt_m.store) @[el2_lsu_stbuf.scala 214:140] - node _T_854 = bits(stbuf_match_hi, 3, 3) @[el2_lsu_stbuf.scala 214:75] - node _T_855 = bits(stbuf_match_lo, 3, 3) @[el2_lsu_stbuf.scala 214:95] - node _T_856 = or(_T_854, _T_855) @[el2_lsu_stbuf.scala 214:79] - node _T_857 = and(_T_856, io.lsu_pkt_m.valid) @[el2_lsu_stbuf.scala 214:100] - node _T_858 = and(_T_857, io.lsu_pkt_m.dma) @[el2_lsu_stbuf.scala 214:121] - node _T_859 = and(_T_858, io.lsu_pkt_m.store) @[el2_lsu_stbuf.scala 214:140] + node _T_836 = bits(stbuf_match_hi, 0, 0) @[el2_lsu_stbuf.scala 208:74] + node _T_837 = bits(stbuf_match_lo, 0, 0) @[el2_lsu_stbuf.scala 208:94] + node _T_838 = or(_T_836, _T_837) @[el2_lsu_stbuf.scala 208:78] + node _T_839 = and(_T_838, io.lsu_pkt_m.valid) @[el2_lsu_stbuf.scala 208:99] + node _T_840 = and(_T_839, io.lsu_pkt_m.bits.dma) @[el2_lsu_stbuf.scala 208:120] + node _T_841 = and(_T_840, io.lsu_pkt_m.bits.store) @[el2_lsu_stbuf.scala 208:144] + node _T_842 = bits(stbuf_match_hi, 1, 1) @[el2_lsu_stbuf.scala 208:74] + node _T_843 = bits(stbuf_match_lo, 1, 1) @[el2_lsu_stbuf.scala 208:94] + node _T_844 = or(_T_842, _T_843) @[el2_lsu_stbuf.scala 208:78] + node _T_845 = and(_T_844, io.lsu_pkt_m.valid) @[el2_lsu_stbuf.scala 208:99] + node _T_846 = and(_T_845, io.lsu_pkt_m.bits.dma) @[el2_lsu_stbuf.scala 208:120] + node _T_847 = and(_T_846, io.lsu_pkt_m.bits.store) @[el2_lsu_stbuf.scala 208:144] + node _T_848 = bits(stbuf_match_hi, 2, 2) @[el2_lsu_stbuf.scala 208:74] + node _T_849 = bits(stbuf_match_lo, 2, 2) @[el2_lsu_stbuf.scala 208:94] + node _T_850 = or(_T_848, _T_849) @[el2_lsu_stbuf.scala 208:78] + node _T_851 = and(_T_850, io.lsu_pkt_m.valid) @[el2_lsu_stbuf.scala 208:99] + node _T_852 = and(_T_851, io.lsu_pkt_m.bits.dma) @[el2_lsu_stbuf.scala 208:120] + node _T_853 = and(_T_852, io.lsu_pkt_m.bits.store) @[el2_lsu_stbuf.scala 208:144] + node _T_854 = bits(stbuf_match_hi, 3, 3) @[el2_lsu_stbuf.scala 208:74] + node _T_855 = bits(stbuf_match_lo, 3, 3) @[el2_lsu_stbuf.scala 208:94] + node _T_856 = or(_T_854, _T_855) @[el2_lsu_stbuf.scala 208:78] + node _T_857 = and(_T_856, io.lsu_pkt_m.valid) @[el2_lsu_stbuf.scala 208:99] + node _T_858 = and(_T_857, io.lsu_pkt_m.bits.dma) @[el2_lsu_stbuf.scala 208:120] + node _T_859 = and(_T_858, io.lsu_pkt_m.bits.store) @[el2_lsu_stbuf.scala 208:144] node _T_860 = cat(_T_859, _T_853) @[Cat.scala 29:58] node _T_861 = cat(_T_860, _T_847) @[Cat.scala 29:58] node _T_862 = cat(_T_861, _T_841) @[Cat.scala 29:58] - stbuf_dma_kill_en <= _T_862 @[el2_lsu_stbuf.scala 214:22] - node _T_863 = bits(stbuf_match_hi, 0, 0) @[el2_lsu_stbuf.scala 217:113] - node _T_864 = bits(stbuf_byteen[0], 0, 0) @[el2_lsu_stbuf.scala 217:134] - node _T_865 = and(_T_863, _T_864) @[el2_lsu_stbuf.scala 217:117] - node _T_866 = bits(stbuf_vld, 0, 0) @[el2_lsu_stbuf.scala 217:149] - node stbuf_fwdbyteenvec_hi_0_0 = and(_T_865, _T_866) @[el2_lsu_stbuf.scala 217:138] - node _T_867 = bits(stbuf_match_hi, 0, 0) @[el2_lsu_stbuf.scala 217:113] - node _T_868 = bits(stbuf_byteen[0], 1, 1) @[el2_lsu_stbuf.scala 217:134] - node _T_869 = and(_T_867, _T_868) @[el2_lsu_stbuf.scala 217:117] - node _T_870 = bits(stbuf_vld, 0, 0) @[el2_lsu_stbuf.scala 217:149] - node stbuf_fwdbyteenvec_hi_0_1 = and(_T_869, _T_870) @[el2_lsu_stbuf.scala 217:138] - node _T_871 = bits(stbuf_match_hi, 0, 0) @[el2_lsu_stbuf.scala 217:113] - node _T_872 = bits(stbuf_byteen[0], 2, 2) @[el2_lsu_stbuf.scala 217:134] - node _T_873 = and(_T_871, _T_872) @[el2_lsu_stbuf.scala 217:117] - node _T_874 = bits(stbuf_vld, 0, 0) @[el2_lsu_stbuf.scala 217:149] - node stbuf_fwdbyteenvec_hi_0_2 = and(_T_873, _T_874) @[el2_lsu_stbuf.scala 217:138] - node _T_875 = bits(stbuf_match_hi, 0, 0) @[el2_lsu_stbuf.scala 217:113] - node _T_876 = bits(stbuf_byteen[0], 3, 3) @[el2_lsu_stbuf.scala 217:134] - node _T_877 = and(_T_875, _T_876) @[el2_lsu_stbuf.scala 217:117] - node _T_878 = bits(stbuf_vld, 0, 0) @[el2_lsu_stbuf.scala 217:149] - node stbuf_fwdbyteenvec_hi_0_3 = and(_T_877, _T_878) @[el2_lsu_stbuf.scala 217:138] - node _T_879 = bits(stbuf_match_hi, 1, 1) @[el2_lsu_stbuf.scala 217:113] - node _T_880 = bits(stbuf_byteen[1], 0, 0) @[el2_lsu_stbuf.scala 217:134] - node _T_881 = and(_T_879, _T_880) @[el2_lsu_stbuf.scala 217:117] - node _T_882 = bits(stbuf_vld, 1, 1) @[el2_lsu_stbuf.scala 217:149] - node stbuf_fwdbyteenvec_hi_1_0 = and(_T_881, _T_882) @[el2_lsu_stbuf.scala 217:138] - node _T_883 = bits(stbuf_match_hi, 1, 1) @[el2_lsu_stbuf.scala 217:113] - node _T_884 = bits(stbuf_byteen[1], 1, 1) @[el2_lsu_stbuf.scala 217:134] - node _T_885 = and(_T_883, _T_884) @[el2_lsu_stbuf.scala 217:117] - node _T_886 = bits(stbuf_vld, 1, 1) @[el2_lsu_stbuf.scala 217:149] - node stbuf_fwdbyteenvec_hi_1_1 = and(_T_885, _T_886) @[el2_lsu_stbuf.scala 217:138] - node _T_887 = bits(stbuf_match_hi, 1, 1) @[el2_lsu_stbuf.scala 217:113] - node _T_888 = bits(stbuf_byteen[1], 2, 2) @[el2_lsu_stbuf.scala 217:134] - node _T_889 = and(_T_887, _T_888) @[el2_lsu_stbuf.scala 217:117] - node _T_890 = bits(stbuf_vld, 1, 1) @[el2_lsu_stbuf.scala 217:149] - node stbuf_fwdbyteenvec_hi_1_2 = and(_T_889, _T_890) @[el2_lsu_stbuf.scala 217:138] - node _T_891 = bits(stbuf_match_hi, 1, 1) @[el2_lsu_stbuf.scala 217:113] - node _T_892 = bits(stbuf_byteen[1], 3, 3) @[el2_lsu_stbuf.scala 217:134] - node _T_893 = and(_T_891, _T_892) @[el2_lsu_stbuf.scala 217:117] - node _T_894 = bits(stbuf_vld, 1, 1) @[el2_lsu_stbuf.scala 217:149] - node stbuf_fwdbyteenvec_hi_1_3 = and(_T_893, _T_894) @[el2_lsu_stbuf.scala 217:138] - node _T_895 = bits(stbuf_match_hi, 2, 2) @[el2_lsu_stbuf.scala 217:113] - node _T_896 = bits(stbuf_byteen[2], 0, 0) @[el2_lsu_stbuf.scala 217:134] - node _T_897 = and(_T_895, _T_896) @[el2_lsu_stbuf.scala 217:117] - node _T_898 = bits(stbuf_vld, 2, 2) @[el2_lsu_stbuf.scala 217:149] - node stbuf_fwdbyteenvec_hi_2_0 = and(_T_897, _T_898) @[el2_lsu_stbuf.scala 217:138] - node _T_899 = bits(stbuf_match_hi, 2, 2) @[el2_lsu_stbuf.scala 217:113] - node _T_900 = bits(stbuf_byteen[2], 1, 1) @[el2_lsu_stbuf.scala 217:134] - node _T_901 = and(_T_899, _T_900) @[el2_lsu_stbuf.scala 217:117] - node _T_902 = bits(stbuf_vld, 2, 2) @[el2_lsu_stbuf.scala 217:149] - node stbuf_fwdbyteenvec_hi_2_1 = and(_T_901, _T_902) @[el2_lsu_stbuf.scala 217:138] - node _T_903 = bits(stbuf_match_hi, 2, 2) @[el2_lsu_stbuf.scala 217:113] - node _T_904 = bits(stbuf_byteen[2], 2, 2) @[el2_lsu_stbuf.scala 217:134] - node _T_905 = and(_T_903, _T_904) @[el2_lsu_stbuf.scala 217:117] - node _T_906 = bits(stbuf_vld, 2, 2) @[el2_lsu_stbuf.scala 217:149] - node stbuf_fwdbyteenvec_hi_2_2 = and(_T_905, _T_906) @[el2_lsu_stbuf.scala 217:138] - node _T_907 = bits(stbuf_match_hi, 2, 2) @[el2_lsu_stbuf.scala 217:113] - node _T_908 = bits(stbuf_byteen[2], 3, 3) @[el2_lsu_stbuf.scala 217:134] - node _T_909 = and(_T_907, _T_908) @[el2_lsu_stbuf.scala 217:117] - node _T_910 = bits(stbuf_vld, 2, 2) @[el2_lsu_stbuf.scala 217:149] - node stbuf_fwdbyteenvec_hi_2_3 = and(_T_909, _T_910) @[el2_lsu_stbuf.scala 217:138] - node _T_911 = bits(stbuf_match_hi, 3, 3) @[el2_lsu_stbuf.scala 217:113] - node _T_912 = bits(stbuf_byteen[3], 0, 0) @[el2_lsu_stbuf.scala 217:134] - node _T_913 = and(_T_911, _T_912) @[el2_lsu_stbuf.scala 217:117] - node _T_914 = bits(stbuf_vld, 3, 3) @[el2_lsu_stbuf.scala 217:149] - node stbuf_fwdbyteenvec_hi_3_0 = and(_T_913, _T_914) @[el2_lsu_stbuf.scala 217:138] - node _T_915 = bits(stbuf_match_hi, 3, 3) @[el2_lsu_stbuf.scala 217:113] - node _T_916 = bits(stbuf_byteen[3], 1, 1) @[el2_lsu_stbuf.scala 217:134] - node _T_917 = and(_T_915, _T_916) @[el2_lsu_stbuf.scala 217:117] - node _T_918 = bits(stbuf_vld, 3, 3) @[el2_lsu_stbuf.scala 217:149] - node stbuf_fwdbyteenvec_hi_3_1 = and(_T_917, _T_918) @[el2_lsu_stbuf.scala 217:138] - node _T_919 = bits(stbuf_match_hi, 3, 3) @[el2_lsu_stbuf.scala 217:113] - node _T_920 = bits(stbuf_byteen[3], 2, 2) @[el2_lsu_stbuf.scala 217:134] - node _T_921 = and(_T_919, _T_920) @[el2_lsu_stbuf.scala 217:117] - node _T_922 = bits(stbuf_vld, 3, 3) @[el2_lsu_stbuf.scala 217:149] - node stbuf_fwdbyteenvec_hi_3_2 = and(_T_921, _T_922) @[el2_lsu_stbuf.scala 217:138] - node _T_923 = bits(stbuf_match_hi, 3, 3) @[el2_lsu_stbuf.scala 217:113] - node _T_924 = bits(stbuf_byteen[3], 3, 3) @[el2_lsu_stbuf.scala 217:134] - node _T_925 = and(_T_923, _T_924) @[el2_lsu_stbuf.scala 217:117] - node _T_926 = bits(stbuf_vld, 3, 3) @[el2_lsu_stbuf.scala 217:149] - node stbuf_fwdbyteenvec_hi_3_3 = and(_T_925, _T_926) @[el2_lsu_stbuf.scala 217:138] - node _T_927 = bits(stbuf_match_lo, 0, 0) @[el2_lsu_stbuf.scala 218:113] - node _T_928 = bits(stbuf_byteen[0], 0, 0) @[el2_lsu_stbuf.scala 218:134] - node _T_929 = and(_T_927, _T_928) @[el2_lsu_stbuf.scala 218:117] - node _T_930 = bits(stbuf_vld, 0, 0) @[el2_lsu_stbuf.scala 218:149] - node stbuf_fwdbyteenvec_lo_0_0 = and(_T_929, _T_930) @[el2_lsu_stbuf.scala 218:138] - node _T_931 = bits(stbuf_match_lo, 0, 0) @[el2_lsu_stbuf.scala 218:113] - node _T_932 = bits(stbuf_byteen[0], 1, 1) @[el2_lsu_stbuf.scala 218:134] - node _T_933 = and(_T_931, _T_932) @[el2_lsu_stbuf.scala 218:117] - node _T_934 = bits(stbuf_vld, 0, 0) @[el2_lsu_stbuf.scala 218:149] - node stbuf_fwdbyteenvec_lo_0_1 = and(_T_933, _T_934) @[el2_lsu_stbuf.scala 218:138] - node _T_935 = bits(stbuf_match_lo, 0, 0) @[el2_lsu_stbuf.scala 218:113] - node _T_936 = bits(stbuf_byteen[0], 2, 2) @[el2_lsu_stbuf.scala 218:134] - node _T_937 = and(_T_935, _T_936) @[el2_lsu_stbuf.scala 218:117] - node _T_938 = bits(stbuf_vld, 0, 0) @[el2_lsu_stbuf.scala 218:149] - node stbuf_fwdbyteenvec_lo_0_2 = and(_T_937, _T_938) @[el2_lsu_stbuf.scala 218:138] - node _T_939 = bits(stbuf_match_lo, 0, 0) @[el2_lsu_stbuf.scala 218:113] - node _T_940 = bits(stbuf_byteen[0], 3, 3) @[el2_lsu_stbuf.scala 218:134] - node _T_941 = and(_T_939, _T_940) @[el2_lsu_stbuf.scala 218:117] - node _T_942 = bits(stbuf_vld, 0, 0) @[el2_lsu_stbuf.scala 218:149] - node stbuf_fwdbyteenvec_lo_0_3 = and(_T_941, _T_942) @[el2_lsu_stbuf.scala 218:138] - node _T_943 = bits(stbuf_match_lo, 1, 1) @[el2_lsu_stbuf.scala 218:113] - node _T_944 = bits(stbuf_byteen[1], 0, 0) @[el2_lsu_stbuf.scala 218:134] - node _T_945 = and(_T_943, _T_944) @[el2_lsu_stbuf.scala 218:117] - node _T_946 = bits(stbuf_vld, 1, 1) @[el2_lsu_stbuf.scala 218:149] - node stbuf_fwdbyteenvec_lo_1_0 = and(_T_945, _T_946) @[el2_lsu_stbuf.scala 218:138] - node _T_947 = bits(stbuf_match_lo, 1, 1) @[el2_lsu_stbuf.scala 218:113] - node _T_948 = bits(stbuf_byteen[1], 1, 1) @[el2_lsu_stbuf.scala 218:134] - node _T_949 = and(_T_947, _T_948) @[el2_lsu_stbuf.scala 218:117] - node _T_950 = bits(stbuf_vld, 1, 1) @[el2_lsu_stbuf.scala 218:149] - node stbuf_fwdbyteenvec_lo_1_1 = and(_T_949, _T_950) @[el2_lsu_stbuf.scala 218:138] - node _T_951 = bits(stbuf_match_lo, 1, 1) @[el2_lsu_stbuf.scala 218:113] - node _T_952 = bits(stbuf_byteen[1], 2, 2) @[el2_lsu_stbuf.scala 218:134] - node _T_953 = and(_T_951, _T_952) @[el2_lsu_stbuf.scala 218:117] - node _T_954 = bits(stbuf_vld, 1, 1) @[el2_lsu_stbuf.scala 218:149] - node stbuf_fwdbyteenvec_lo_1_2 = and(_T_953, _T_954) @[el2_lsu_stbuf.scala 218:138] - node _T_955 = bits(stbuf_match_lo, 1, 1) @[el2_lsu_stbuf.scala 218:113] - node _T_956 = bits(stbuf_byteen[1], 3, 3) @[el2_lsu_stbuf.scala 218:134] - node _T_957 = and(_T_955, _T_956) @[el2_lsu_stbuf.scala 218:117] - node _T_958 = bits(stbuf_vld, 1, 1) @[el2_lsu_stbuf.scala 218:149] - node stbuf_fwdbyteenvec_lo_1_3 = and(_T_957, _T_958) @[el2_lsu_stbuf.scala 218:138] - node _T_959 = bits(stbuf_match_lo, 2, 2) @[el2_lsu_stbuf.scala 218:113] - node _T_960 = bits(stbuf_byteen[2], 0, 0) @[el2_lsu_stbuf.scala 218:134] - node _T_961 = and(_T_959, _T_960) @[el2_lsu_stbuf.scala 218:117] - node _T_962 = bits(stbuf_vld, 2, 2) @[el2_lsu_stbuf.scala 218:149] - node stbuf_fwdbyteenvec_lo_2_0 = and(_T_961, _T_962) @[el2_lsu_stbuf.scala 218:138] - node _T_963 = bits(stbuf_match_lo, 2, 2) @[el2_lsu_stbuf.scala 218:113] - node _T_964 = bits(stbuf_byteen[2], 1, 1) @[el2_lsu_stbuf.scala 218:134] - node _T_965 = and(_T_963, _T_964) @[el2_lsu_stbuf.scala 218:117] - node _T_966 = bits(stbuf_vld, 2, 2) @[el2_lsu_stbuf.scala 218:149] - node stbuf_fwdbyteenvec_lo_2_1 = and(_T_965, _T_966) @[el2_lsu_stbuf.scala 218:138] - node _T_967 = bits(stbuf_match_lo, 2, 2) @[el2_lsu_stbuf.scala 218:113] - node _T_968 = bits(stbuf_byteen[2], 2, 2) @[el2_lsu_stbuf.scala 218:134] - node _T_969 = and(_T_967, _T_968) @[el2_lsu_stbuf.scala 218:117] - node _T_970 = bits(stbuf_vld, 2, 2) @[el2_lsu_stbuf.scala 218:149] - node stbuf_fwdbyteenvec_lo_2_2 = and(_T_969, _T_970) @[el2_lsu_stbuf.scala 218:138] - node _T_971 = bits(stbuf_match_lo, 2, 2) @[el2_lsu_stbuf.scala 218:113] - node _T_972 = bits(stbuf_byteen[2], 3, 3) @[el2_lsu_stbuf.scala 218:134] - node _T_973 = and(_T_971, _T_972) @[el2_lsu_stbuf.scala 218:117] - node _T_974 = bits(stbuf_vld, 2, 2) @[el2_lsu_stbuf.scala 218:149] - node stbuf_fwdbyteenvec_lo_2_3 = and(_T_973, _T_974) @[el2_lsu_stbuf.scala 218:138] - node _T_975 = bits(stbuf_match_lo, 3, 3) @[el2_lsu_stbuf.scala 218:113] - node _T_976 = bits(stbuf_byteen[3], 0, 0) @[el2_lsu_stbuf.scala 218:134] - node _T_977 = and(_T_975, _T_976) @[el2_lsu_stbuf.scala 218:117] - node _T_978 = bits(stbuf_vld, 3, 3) @[el2_lsu_stbuf.scala 218:149] - node stbuf_fwdbyteenvec_lo_3_0 = and(_T_977, _T_978) @[el2_lsu_stbuf.scala 218:138] - node _T_979 = bits(stbuf_match_lo, 3, 3) @[el2_lsu_stbuf.scala 218:113] - node _T_980 = bits(stbuf_byteen[3], 1, 1) @[el2_lsu_stbuf.scala 218:134] - node _T_981 = and(_T_979, _T_980) @[el2_lsu_stbuf.scala 218:117] - node _T_982 = bits(stbuf_vld, 3, 3) @[el2_lsu_stbuf.scala 218:149] - node stbuf_fwdbyteenvec_lo_3_1 = and(_T_981, _T_982) @[el2_lsu_stbuf.scala 218:138] - node _T_983 = bits(stbuf_match_lo, 3, 3) @[el2_lsu_stbuf.scala 218:113] - node _T_984 = bits(stbuf_byteen[3], 2, 2) @[el2_lsu_stbuf.scala 218:134] - node _T_985 = and(_T_983, _T_984) @[el2_lsu_stbuf.scala 218:117] - node _T_986 = bits(stbuf_vld, 3, 3) @[el2_lsu_stbuf.scala 218:149] - node stbuf_fwdbyteenvec_lo_3_2 = and(_T_985, _T_986) @[el2_lsu_stbuf.scala 218:138] - node _T_987 = bits(stbuf_match_lo, 3, 3) @[el2_lsu_stbuf.scala 218:113] - node _T_988 = bits(stbuf_byteen[3], 3, 3) @[el2_lsu_stbuf.scala 218:134] - node _T_989 = and(_T_987, _T_988) @[el2_lsu_stbuf.scala 218:117] - node _T_990 = bits(stbuf_vld, 3, 3) @[el2_lsu_stbuf.scala 218:149] - node stbuf_fwdbyteenvec_lo_3_3 = and(_T_989, _T_990) @[el2_lsu_stbuf.scala 218:138] - node _T_991 = or(stbuf_fwdbyteenvec_hi_0_0, stbuf_fwdbyteenvec_hi_1_0) @[el2_lsu_stbuf.scala 219:148] - node _T_992 = or(_T_991, stbuf_fwdbyteenvec_hi_2_0) @[el2_lsu_stbuf.scala 219:148] - node stbuf_fwdbyteen_hi_pre_m_0 = or(_T_992, stbuf_fwdbyteenvec_hi_3_0) @[el2_lsu_stbuf.scala 219:148] - node _T_993 = or(stbuf_fwdbyteenvec_hi_0_1, stbuf_fwdbyteenvec_hi_1_1) @[el2_lsu_stbuf.scala 219:148] - node _T_994 = or(_T_993, stbuf_fwdbyteenvec_hi_2_1) @[el2_lsu_stbuf.scala 219:148] - node stbuf_fwdbyteen_hi_pre_m_1 = or(_T_994, stbuf_fwdbyteenvec_hi_3_1) @[el2_lsu_stbuf.scala 219:148] - node _T_995 = or(stbuf_fwdbyteenvec_hi_0_2, stbuf_fwdbyteenvec_hi_1_2) @[el2_lsu_stbuf.scala 219:148] - node _T_996 = or(_T_995, stbuf_fwdbyteenvec_hi_2_2) @[el2_lsu_stbuf.scala 219:148] - node stbuf_fwdbyteen_hi_pre_m_2 = or(_T_996, stbuf_fwdbyteenvec_hi_3_2) @[el2_lsu_stbuf.scala 219:148] - node _T_997 = or(stbuf_fwdbyteenvec_hi_0_3, stbuf_fwdbyteenvec_hi_1_3) @[el2_lsu_stbuf.scala 219:148] - node _T_998 = or(_T_997, stbuf_fwdbyteenvec_hi_2_3) @[el2_lsu_stbuf.scala 219:148] - node stbuf_fwdbyteen_hi_pre_m_3 = or(_T_998, stbuf_fwdbyteenvec_hi_3_3) @[el2_lsu_stbuf.scala 219:148] - node _T_999 = or(stbuf_fwdbyteenvec_lo_0_0, stbuf_fwdbyteenvec_lo_1_0) @[el2_lsu_stbuf.scala 220:148] - node _T_1000 = or(_T_999, stbuf_fwdbyteenvec_lo_2_0) @[el2_lsu_stbuf.scala 220:148] - node stbuf_fwdbyteen_lo_pre_m_0 = or(_T_1000, stbuf_fwdbyteenvec_lo_3_0) @[el2_lsu_stbuf.scala 220:148] - node _T_1001 = or(stbuf_fwdbyteenvec_lo_0_1, stbuf_fwdbyteenvec_lo_1_1) @[el2_lsu_stbuf.scala 220:148] - node _T_1002 = or(_T_1001, stbuf_fwdbyteenvec_lo_2_1) @[el2_lsu_stbuf.scala 220:148] - node stbuf_fwdbyteen_lo_pre_m_1 = or(_T_1002, stbuf_fwdbyteenvec_lo_3_1) @[el2_lsu_stbuf.scala 220:148] - node _T_1003 = or(stbuf_fwdbyteenvec_lo_0_2, stbuf_fwdbyteenvec_lo_1_2) @[el2_lsu_stbuf.scala 220:148] - node _T_1004 = or(_T_1003, stbuf_fwdbyteenvec_lo_2_2) @[el2_lsu_stbuf.scala 220:148] - node stbuf_fwdbyteen_lo_pre_m_2 = or(_T_1004, stbuf_fwdbyteenvec_lo_3_2) @[el2_lsu_stbuf.scala 220:148] - node _T_1005 = or(stbuf_fwdbyteenvec_lo_0_3, stbuf_fwdbyteenvec_lo_1_3) @[el2_lsu_stbuf.scala 220:148] - node _T_1006 = or(_T_1005, stbuf_fwdbyteenvec_lo_2_3) @[el2_lsu_stbuf.scala 220:148] - node stbuf_fwdbyteen_lo_pre_m_3 = or(_T_1006, stbuf_fwdbyteenvec_lo_3_3) @[el2_lsu_stbuf.scala 220:148] - node _T_1007 = bits(stbuf_match_hi, 0, 0) @[el2_lsu_stbuf.scala 222:93] + stbuf_dma_kill_en <= _T_862 @[el2_lsu_stbuf.scala 208:21] + node _T_863 = bits(stbuf_match_hi, 0, 0) @[el2_lsu_stbuf.scala 211:112] + node _T_864 = bits(stbuf_byteen[0], 0, 0) @[el2_lsu_stbuf.scala 211:133] + node _T_865 = and(_T_863, _T_864) @[el2_lsu_stbuf.scala 211:116] + node _T_866 = bits(stbuf_vld, 0, 0) @[el2_lsu_stbuf.scala 211:148] + node stbuf_fwdbyteenvec_hi_0_0 = and(_T_865, _T_866) @[el2_lsu_stbuf.scala 211:137] + node _T_867 = bits(stbuf_match_hi, 0, 0) @[el2_lsu_stbuf.scala 211:112] + node _T_868 = bits(stbuf_byteen[0], 1, 1) @[el2_lsu_stbuf.scala 211:133] + node _T_869 = and(_T_867, _T_868) @[el2_lsu_stbuf.scala 211:116] + node _T_870 = bits(stbuf_vld, 0, 0) @[el2_lsu_stbuf.scala 211:148] + node stbuf_fwdbyteenvec_hi_0_1 = and(_T_869, _T_870) @[el2_lsu_stbuf.scala 211:137] + node _T_871 = bits(stbuf_match_hi, 0, 0) @[el2_lsu_stbuf.scala 211:112] + node _T_872 = bits(stbuf_byteen[0], 2, 2) @[el2_lsu_stbuf.scala 211:133] + node _T_873 = and(_T_871, _T_872) @[el2_lsu_stbuf.scala 211:116] + node _T_874 = bits(stbuf_vld, 0, 0) @[el2_lsu_stbuf.scala 211:148] + node stbuf_fwdbyteenvec_hi_0_2 = and(_T_873, _T_874) @[el2_lsu_stbuf.scala 211:137] + node _T_875 = bits(stbuf_match_hi, 0, 0) @[el2_lsu_stbuf.scala 211:112] + node _T_876 = bits(stbuf_byteen[0], 3, 3) @[el2_lsu_stbuf.scala 211:133] + node _T_877 = and(_T_875, _T_876) @[el2_lsu_stbuf.scala 211:116] + node _T_878 = bits(stbuf_vld, 0, 0) @[el2_lsu_stbuf.scala 211:148] + node stbuf_fwdbyteenvec_hi_0_3 = and(_T_877, _T_878) @[el2_lsu_stbuf.scala 211:137] + node _T_879 = bits(stbuf_match_hi, 1, 1) @[el2_lsu_stbuf.scala 211:112] + node _T_880 = bits(stbuf_byteen[1], 0, 0) @[el2_lsu_stbuf.scala 211:133] + node _T_881 = and(_T_879, _T_880) @[el2_lsu_stbuf.scala 211:116] + node _T_882 = bits(stbuf_vld, 1, 1) @[el2_lsu_stbuf.scala 211:148] + node stbuf_fwdbyteenvec_hi_1_0 = and(_T_881, _T_882) @[el2_lsu_stbuf.scala 211:137] + node _T_883 = bits(stbuf_match_hi, 1, 1) @[el2_lsu_stbuf.scala 211:112] + node _T_884 = bits(stbuf_byteen[1], 1, 1) @[el2_lsu_stbuf.scala 211:133] + node _T_885 = and(_T_883, _T_884) @[el2_lsu_stbuf.scala 211:116] + node _T_886 = bits(stbuf_vld, 1, 1) @[el2_lsu_stbuf.scala 211:148] + node stbuf_fwdbyteenvec_hi_1_1 = and(_T_885, _T_886) @[el2_lsu_stbuf.scala 211:137] + node _T_887 = bits(stbuf_match_hi, 1, 1) @[el2_lsu_stbuf.scala 211:112] + node _T_888 = bits(stbuf_byteen[1], 2, 2) @[el2_lsu_stbuf.scala 211:133] + node _T_889 = and(_T_887, _T_888) @[el2_lsu_stbuf.scala 211:116] + node _T_890 = bits(stbuf_vld, 1, 1) @[el2_lsu_stbuf.scala 211:148] + node stbuf_fwdbyteenvec_hi_1_2 = and(_T_889, _T_890) @[el2_lsu_stbuf.scala 211:137] + node _T_891 = bits(stbuf_match_hi, 1, 1) @[el2_lsu_stbuf.scala 211:112] + node _T_892 = bits(stbuf_byteen[1], 3, 3) @[el2_lsu_stbuf.scala 211:133] + node _T_893 = and(_T_891, _T_892) @[el2_lsu_stbuf.scala 211:116] + node _T_894 = bits(stbuf_vld, 1, 1) @[el2_lsu_stbuf.scala 211:148] + node stbuf_fwdbyteenvec_hi_1_3 = and(_T_893, _T_894) @[el2_lsu_stbuf.scala 211:137] + node _T_895 = bits(stbuf_match_hi, 2, 2) @[el2_lsu_stbuf.scala 211:112] + node _T_896 = bits(stbuf_byteen[2], 0, 0) @[el2_lsu_stbuf.scala 211:133] + node _T_897 = and(_T_895, _T_896) @[el2_lsu_stbuf.scala 211:116] + node _T_898 = bits(stbuf_vld, 2, 2) @[el2_lsu_stbuf.scala 211:148] + node stbuf_fwdbyteenvec_hi_2_0 = and(_T_897, _T_898) @[el2_lsu_stbuf.scala 211:137] + node _T_899 = bits(stbuf_match_hi, 2, 2) @[el2_lsu_stbuf.scala 211:112] + node _T_900 = bits(stbuf_byteen[2], 1, 1) @[el2_lsu_stbuf.scala 211:133] + node _T_901 = and(_T_899, _T_900) @[el2_lsu_stbuf.scala 211:116] + node _T_902 = bits(stbuf_vld, 2, 2) @[el2_lsu_stbuf.scala 211:148] + node stbuf_fwdbyteenvec_hi_2_1 = and(_T_901, _T_902) @[el2_lsu_stbuf.scala 211:137] + node _T_903 = bits(stbuf_match_hi, 2, 2) @[el2_lsu_stbuf.scala 211:112] + node _T_904 = bits(stbuf_byteen[2], 2, 2) @[el2_lsu_stbuf.scala 211:133] + node _T_905 = and(_T_903, _T_904) @[el2_lsu_stbuf.scala 211:116] + node _T_906 = bits(stbuf_vld, 2, 2) @[el2_lsu_stbuf.scala 211:148] + node stbuf_fwdbyteenvec_hi_2_2 = and(_T_905, _T_906) @[el2_lsu_stbuf.scala 211:137] + node _T_907 = bits(stbuf_match_hi, 2, 2) @[el2_lsu_stbuf.scala 211:112] + node _T_908 = bits(stbuf_byteen[2], 3, 3) @[el2_lsu_stbuf.scala 211:133] + node _T_909 = and(_T_907, _T_908) @[el2_lsu_stbuf.scala 211:116] + node _T_910 = bits(stbuf_vld, 2, 2) @[el2_lsu_stbuf.scala 211:148] + node stbuf_fwdbyteenvec_hi_2_3 = and(_T_909, _T_910) @[el2_lsu_stbuf.scala 211:137] + node _T_911 = bits(stbuf_match_hi, 3, 3) @[el2_lsu_stbuf.scala 211:112] + node _T_912 = bits(stbuf_byteen[3], 0, 0) @[el2_lsu_stbuf.scala 211:133] + node _T_913 = and(_T_911, _T_912) @[el2_lsu_stbuf.scala 211:116] + node _T_914 = bits(stbuf_vld, 3, 3) @[el2_lsu_stbuf.scala 211:148] + node stbuf_fwdbyteenvec_hi_3_0 = and(_T_913, _T_914) @[el2_lsu_stbuf.scala 211:137] + node _T_915 = bits(stbuf_match_hi, 3, 3) @[el2_lsu_stbuf.scala 211:112] + node _T_916 = bits(stbuf_byteen[3], 1, 1) @[el2_lsu_stbuf.scala 211:133] + node _T_917 = and(_T_915, _T_916) @[el2_lsu_stbuf.scala 211:116] + node _T_918 = bits(stbuf_vld, 3, 3) @[el2_lsu_stbuf.scala 211:148] + node stbuf_fwdbyteenvec_hi_3_1 = and(_T_917, _T_918) @[el2_lsu_stbuf.scala 211:137] + node _T_919 = bits(stbuf_match_hi, 3, 3) @[el2_lsu_stbuf.scala 211:112] + node _T_920 = bits(stbuf_byteen[3], 2, 2) @[el2_lsu_stbuf.scala 211:133] + node _T_921 = and(_T_919, _T_920) @[el2_lsu_stbuf.scala 211:116] + node _T_922 = bits(stbuf_vld, 3, 3) @[el2_lsu_stbuf.scala 211:148] + node stbuf_fwdbyteenvec_hi_3_2 = and(_T_921, _T_922) @[el2_lsu_stbuf.scala 211:137] + node _T_923 = bits(stbuf_match_hi, 3, 3) @[el2_lsu_stbuf.scala 211:112] + node _T_924 = bits(stbuf_byteen[3], 3, 3) @[el2_lsu_stbuf.scala 211:133] + node _T_925 = and(_T_923, _T_924) @[el2_lsu_stbuf.scala 211:116] + node _T_926 = bits(stbuf_vld, 3, 3) @[el2_lsu_stbuf.scala 211:148] + node stbuf_fwdbyteenvec_hi_3_3 = and(_T_925, _T_926) @[el2_lsu_stbuf.scala 211:137] + node _T_927 = bits(stbuf_match_lo, 0, 0) @[el2_lsu_stbuf.scala 212:112] + node _T_928 = bits(stbuf_byteen[0], 0, 0) @[el2_lsu_stbuf.scala 212:133] + node _T_929 = and(_T_927, _T_928) @[el2_lsu_stbuf.scala 212:116] + node _T_930 = bits(stbuf_vld, 0, 0) @[el2_lsu_stbuf.scala 212:148] + node stbuf_fwdbyteenvec_lo_0_0 = and(_T_929, _T_930) @[el2_lsu_stbuf.scala 212:137] + node _T_931 = bits(stbuf_match_lo, 0, 0) @[el2_lsu_stbuf.scala 212:112] + node _T_932 = bits(stbuf_byteen[0], 1, 1) @[el2_lsu_stbuf.scala 212:133] + node _T_933 = and(_T_931, _T_932) @[el2_lsu_stbuf.scala 212:116] + node _T_934 = bits(stbuf_vld, 0, 0) @[el2_lsu_stbuf.scala 212:148] + node stbuf_fwdbyteenvec_lo_0_1 = and(_T_933, _T_934) @[el2_lsu_stbuf.scala 212:137] + node _T_935 = bits(stbuf_match_lo, 0, 0) @[el2_lsu_stbuf.scala 212:112] + node _T_936 = bits(stbuf_byteen[0], 2, 2) @[el2_lsu_stbuf.scala 212:133] + node _T_937 = and(_T_935, _T_936) @[el2_lsu_stbuf.scala 212:116] + node _T_938 = bits(stbuf_vld, 0, 0) @[el2_lsu_stbuf.scala 212:148] + node stbuf_fwdbyteenvec_lo_0_2 = and(_T_937, _T_938) @[el2_lsu_stbuf.scala 212:137] + node _T_939 = bits(stbuf_match_lo, 0, 0) @[el2_lsu_stbuf.scala 212:112] + node _T_940 = bits(stbuf_byteen[0], 3, 3) @[el2_lsu_stbuf.scala 212:133] + node _T_941 = and(_T_939, _T_940) @[el2_lsu_stbuf.scala 212:116] + node _T_942 = bits(stbuf_vld, 0, 0) @[el2_lsu_stbuf.scala 212:148] + node stbuf_fwdbyteenvec_lo_0_3 = and(_T_941, _T_942) @[el2_lsu_stbuf.scala 212:137] + node _T_943 = bits(stbuf_match_lo, 1, 1) @[el2_lsu_stbuf.scala 212:112] + node _T_944 = bits(stbuf_byteen[1], 0, 0) @[el2_lsu_stbuf.scala 212:133] + node _T_945 = and(_T_943, _T_944) @[el2_lsu_stbuf.scala 212:116] + node _T_946 = bits(stbuf_vld, 1, 1) @[el2_lsu_stbuf.scala 212:148] + node stbuf_fwdbyteenvec_lo_1_0 = and(_T_945, _T_946) @[el2_lsu_stbuf.scala 212:137] + node _T_947 = bits(stbuf_match_lo, 1, 1) @[el2_lsu_stbuf.scala 212:112] + node _T_948 = bits(stbuf_byteen[1], 1, 1) @[el2_lsu_stbuf.scala 212:133] + node _T_949 = and(_T_947, _T_948) @[el2_lsu_stbuf.scala 212:116] + node _T_950 = bits(stbuf_vld, 1, 1) @[el2_lsu_stbuf.scala 212:148] + node stbuf_fwdbyteenvec_lo_1_1 = and(_T_949, _T_950) @[el2_lsu_stbuf.scala 212:137] + node _T_951 = bits(stbuf_match_lo, 1, 1) @[el2_lsu_stbuf.scala 212:112] + node _T_952 = bits(stbuf_byteen[1], 2, 2) @[el2_lsu_stbuf.scala 212:133] + node _T_953 = and(_T_951, _T_952) @[el2_lsu_stbuf.scala 212:116] + node _T_954 = bits(stbuf_vld, 1, 1) @[el2_lsu_stbuf.scala 212:148] + node stbuf_fwdbyteenvec_lo_1_2 = and(_T_953, _T_954) @[el2_lsu_stbuf.scala 212:137] + node _T_955 = bits(stbuf_match_lo, 1, 1) @[el2_lsu_stbuf.scala 212:112] + node _T_956 = bits(stbuf_byteen[1], 3, 3) @[el2_lsu_stbuf.scala 212:133] + node _T_957 = and(_T_955, _T_956) @[el2_lsu_stbuf.scala 212:116] + node _T_958 = bits(stbuf_vld, 1, 1) @[el2_lsu_stbuf.scala 212:148] + node stbuf_fwdbyteenvec_lo_1_3 = and(_T_957, _T_958) @[el2_lsu_stbuf.scala 212:137] + node _T_959 = bits(stbuf_match_lo, 2, 2) @[el2_lsu_stbuf.scala 212:112] + node _T_960 = bits(stbuf_byteen[2], 0, 0) @[el2_lsu_stbuf.scala 212:133] + node _T_961 = and(_T_959, _T_960) @[el2_lsu_stbuf.scala 212:116] + node _T_962 = bits(stbuf_vld, 2, 2) @[el2_lsu_stbuf.scala 212:148] + node stbuf_fwdbyteenvec_lo_2_0 = and(_T_961, _T_962) @[el2_lsu_stbuf.scala 212:137] + node _T_963 = bits(stbuf_match_lo, 2, 2) @[el2_lsu_stbuf.scala 212:112] + node _T_964 = bits(stbuf_byteen[2], 1, 1) @[el2_lsu_stbuf.scala 212:133] + node _T_965 = and(_T_963, _T_964) @[el2_lsu_stbuf.scala 212:116] + node _T_966 = bits(stbuf_vld, 2, 2) @[el2_lsu_stbuf.scala 212:148] + node stbuf_fwdbyteenvec_lo_2_1 = and(_T_965, _T_966) @[el2_lsu_stbuf.scala 212:137] + node _T_967 = bits(stbuf_match_lo, 2, 2) @[el2_lsu_stbuf.scala 212:112] + node _T_968 = bits(stbuf_byteen[2], 2, 2) @[el2_lsu_stbuf.scala 212:133] + node _T_969 = and(_T_967, _T_968) @[el2_lsu_stbuf.scala 212:116] + node _T_970 = bits(stbuf_vld, 2, 2) @[el2_lsu_stbuf.scala 212:148] + node stbuf_fwdbyteenvec_lo_2_2 = and(_T_969, _T_970) @[el2_lsu_stbuf.scala 212:137] + node _T_971 = bits(stbuf_match_lo, 2, 2) @[el2_lsu_stbuf.scala 212:112] + node _T_972 = bits(stbuf_byteen[2], 3, 3) @[el2_lsu_stbuf.scala 212:133] + node _T_973 = and(_T_971, _T_972) @[el2_lsu_stbuf.scala 212:116] + node _T_974 = bits(stbuf_vld, 2, 2) @[el2_lsu_stbuf.scala 212:148] + node stbuf_fwdbyteenvec_lo_2_3 = and(_T_973, _T_974) @[el2_lsu_stbuf.scala 212:137] + node _T_975 = bits(stbuf_match_lo, 3, 3) @[el2_lsu_stbuf.scala 212:112] + node _T_976 = bits(stbuf_byteen[3], 0, 0) @[el2_lsu_stbuf.scala 212:133] + node _T_977 = and(_T_975, _T_976) @[el2_lsu_stbuf.scala 212:116] + node _T_978 = bits(stbuf_vld, 3, 3) @[el2_lsu_stbuf.scala 212:148] + node stbuf_fwdbyteenvec_lo_3_0 = and(_T_977, _T_978) @[el2_lsu_stbuf.scala 212:137] + node _T_979 = bits(stbuf_match_lo, 3, 3) @[el2_lsu_stbuf.scala 212:112] + node _T_980 = bits(stbuf_byteen[3], 1, 1) @[el2_lsu_stbuf.scala 212:133] + node _T_981 = and(_T_979, _T_980) @[el2_lsu_stbuf.scala 212:116] + node _T_982 = bits(stbuf_vld, 3, 3) @[el2_lsu_stbuf.scala 212:148] + node stbuf_fwdbyteenvec_lo_3_1 = and(_T_981, _T_982) @[el2_lsu_stbuf.scala 212:137] + node _T_983 = bits(stbuf_match_lo, 3, 3) @[el2_lsu_stbuf.scala 212:112] + node _T_984 = bits(stbuf_byteen[3], 2, 2) @[el2_lsu_stbuf.scala 212:133] + node _T_985 = and(_T_983, _T_984) @[el2_lsu_stbuf.scala 212:116] + node _T_986 = bits(stbuf_vld, 3, 3) @[el2_lsu_stbuf.scala 212:148] + node stbuf_fwdbyteenvec_lo_3_2 = and(_T_985, _T_986) @[el2_lsu_stbuf.scala 212:137] + node _T_987 = bits(stbuf_match_lo, 3, 3) @[el2_lsu_stbuf.scala 212:112] + node _T_988 = bits(stbuf_byteen[3], 3, 3) @[el2_lsu_stbuf.scala 212:133] + node _T_989 = and(_T_987, _T_988) @[el2_lsu_stbuf.scala 212:116] + node _T_990 = bits(stbuf_vld, 3, 3) @[el2_lsu_stbuf.scala 212:148] + node stbuf_fwdbyteenvec_lo_3_3 = and(_T_989, _T_990) @[el2_lsu_stbuf.scala 212:137] + node _T_991 = or(stbuf_fwdbyteenvec_hi_0_0, stbuf_fwdbyteenvec_hi_1_0) @[el2_lsu_stbuf.scala 213:147] + node _T_992 = or(_T_991, stbuf_fwdbyteenvec_hi_2_0) @[el2_lsu_stbuf.scala 213:147] + node stbuf_fwdbyteen_hi_pre_m_0 = or(_T_992, stbuf_fwdbyteenvec_hi_3_0) @[el2_lsu_stbuf.scala 213:147] + node _T_993 = or(stbuf_fwdbyteenvec_hi_0_1, stbuf_fwdbyteenvec_hi_1_1) @[el2_lsu_stbuf.scala 213:147] + node _T_994 = or(_T_993, stbuf_fwdbyteenvec_hi_2_1) @[el2_lsu_stbuf.scala 213:147] + node stbuf_fwdbyteen_hi_pre_m_1 = or(_T_994, stbuf_fwdbyteenvec_hi_3_1) @[el2_lsu_stbuf.scala 213:147] + node _T_995 = or(stbuf_fwdbyteenvec_hi_0_2, stbuf_fwdbyteenvec_hi_1_2) @[el2_lsu_stbuf.scala 213:147] + node _T_996 = or(_T_995, stbuf_fwdbyteenvec_hi_2_2) @[el2_lsu_stbuf.scala 213:147] + node stbuf_fwdbyteen_hi_pre_m_2 = or(_T_996, stbuf_fwdbyteenvec_hi_3_2) @[el2_lsu_stbuf.scala 213:147] + node _T_997 = or(stbuf_fwdbyteenvec_hi_0_3, stbuf_fwdbyteenvec_hi_1_3) @[el2_lsu_stbuf.scala 213:147] + node _T_998 = or(_T_997, stbuf_fwdbyteenvec_hi_2_3) @[el2_lsu_stbuf.scala 213:147] + node stbuf_fwdbyteen_hi_pre_m_3 = or(_T_998, stbuf_fwdbyteenvec_hi_3_3) @[el2_lsu_stbuf.scala 213:147] + node _T_999 = or(stbuf_fwdbyteenvec_lo_0_0, stbuf_fwdbyteenvec_lo_1_0) @[el2_lsu_stbuf.scala 214:147] + node _T_1000 = or(_T_999, stbuf_fwdbyteenvec_lo_2_0) @[el2_lsu_stbuf.scala 214:147] + node stbuf_fwdbyteen_lo_pre_m_0 = or(_T_1000, stbuf_fwdbyteenvec_lo_3_0) @[el2_lsu_stbuf.scala 214:147] + node _T_1001 = or(stbuf_fwdbyteenvec_lo_0_1, stbuf_fwdbyteenvec_lo_1_1) @[el2_lsu_stbuf.scala 214:147] + node _T_1002 = or(_T_1001, stbuf_fwdbyteenvec_lo_2_1) @[el2_lsu_stbuf.scala 214:147] + node stbuf_fwdbyteen_lo_pre_m_1 = or(_T_1002, stbuf_fwdbyteenvec_lo_3_1) @[el2_lsu_stbuf.scala 214:147] + node _T_1003 = or(stbuf_fwdbyteenvec_lo_0_2, stbuf_fwdbyteenvec_lo_1_2) @[el2_lsu_stbuf.scala 214:147] + node _T_1004 = or(_T_1003, stbuf_fwdbyteenvec_lo_2_2) @[el2_lsu_stbuf.scala 214:147] + node stbuf_fwdbyteen_lo_pre_m_2 = or(_T_1004, stbuf_fwdbyteenvec_lo_3_2) @[el2_lsu_stbuf.scala 214:147] + node _T_1005 = or(stbuf_fwdbyteenvec_lo_0_3, stbuf_fwdbyteenvec_lo_1_3) @[el2_lsu_stbuf.scala 214:147] + node _T_1006 = or(_T_1005, stbuf_fwdbyteenvec_lo_2_3) @[el2_lsu_stbuf.scala 214:147] + node stbuf_fwdbyteen_lo_pre_m_3 = or(_T_1006, stbuf_fwdbyteenvec_lo_3_3) @[el2_lsu_stbuf.scala 214:147] + node _T_1007 = bits(stbuf_match_hi, 0, 0) @[el2_lsu_stbuf.scala 216:92] node _T_1008 = bits(_T_1007, 0, 0) @[Bitwise.scala 72:15] node _T_1009 = mux(_T_1008, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_1010 = and(_T_1009, stbuf_data[0]) @[el2_lsu_stbuf.scala 222:98] - node _T_1011 = bits(stbuf_match_hi, 1, 1) @[el2_lsu_stbuf.scala 222:93] + node _T_1010 = and(_T_1009, stbuf_data[0]) @[el2_lsu_stbuf.scala 216:97] + node _T_1011 = bits(stbuf_match_hi, 1, 1) @[el2_lsu_stbuf.scala 216:92] node _T_1012 = bits(_T_1011, 0, 0) @[Bitwise.scala 72:15] node _T_1013 = mux(_T_1012, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_1014 = and(_T_1013, stbuf_data[1]) @[el2_lsu_stbuf.scala 222:98] - node _T_1015 = bits(stbuf_match_hi, 2, 2) @[el2_lsu_stbuf.scala 222:93] + node _T_1014 = and(_T_1013, stbuf_data[1]) @[el2_lsu_stbuf.scala 216:97] + node _T_1015 = bits(stbuf_match_hi, 2, 2) @[el2_lsu_stbuf.scala 216:92] node _T_1016 = bits(_T_1015, 0, 0) @[Bitwise.scala 72:15] node _T_1017 = mux(_T_1016, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_1018 = and(_T_1017, stbuf_data[2]) @[el2_lsu_stbuf.scala 222:98] - node _T_1019 = bits(stbuf_match_hi, 3, 3) @[el2_lsu_stbuf.scala 222:93] + node _T_1018 = and(_T_1017, stbuf_data[2]) @[el2_lsu_stbuf.scala 216:97] + node _T_1019 = bits(stbuf_match_hi, 3, 3) @[el2_lsu_stbuf.scala 216:92] node _T_1020 = bits(_T_1019, 0, 0) @[Bitwise.scala 72:15] node _T_1021 = mux(_T_1020, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_1022 = and(_T_1021, stbuf_data[3]) @[el2_lsu_stbuf.scala 222:98] - wire _T_1023 : UInt<32>[4] @[el2_lsu_stbuf.scala 222:66] - _T_1023[0] <= _T_1010 @[el2_lsu_stbuf.scala 222:66] - _T_1023[1] <= _T_1014 @[el2_lsu_stbuf.scala 222:66] - _T_1023[2] <= _T_1018 @[el2_lsu_stbuf.scala 222:66] - _T_1023[3] <= _T_1022 @[el2_lsu_stbuf.scala 222:66] - node _T_1024 = or(_T_1023[3], _T_1023[2]) @[el2_lsu_stbuf.scala 222:131] - node _T_1025 = or(_T_1024, _T_1023[1]) @[el2_lsu_stbuf.scala 222:131] - node stbuf_fwddata_hi_pre_m = or(_T_1025, _T_1023[0]) @[el2_lsu_stbuf.scala 222:131] - node _T_1026 = bits(stbuf_match_lo, 0, 0) @[el2_lsu_stbuf.scala 223:93] + node _T_1022 = and(_T_1021, stbuf_data[3]) @[el2_lsu_stbuf.scala 216:97] + wire _T_1023 : UInt<32>[4] @[el2_lsu_stbuf.scala 216:65] + _T_1023[0] <= _T_1010 @[el2_lsu_stbuf.scala 216:65] + _T_1023[1] <= _T_1014 @[el2_lsu_stbuf.scala 216:65] + _T_1023[2] <= _T_1018 @[el2_lsu_stbuf.scala 216:65] + _T_1023[3] <= _T_1022 @[el2_lsu_stbuf.scala 216:65] + node _T_1024 = or(_T_1023[3], _T_1023[2]) @[el2_lsu_stbuf.scala 216:130] + node _T_1025 = or(_T_1024, _T_1023[1]) @[el2_lsu_stbuf.scala 216:130] + node stbuf_fwddata_hi_pre_m = or(_T_1025, _T_1023[0]) @[el2_lsu_stbuf.scala 216:130] + node _T_1026 = bits(stbuf_match_lo, 0, 0) @[el2_lsu_stbuf.scala 217:92] node _T_1027 = bits(_T_1026, 0, 0) @[Bitwise.scala 72:15] node _T_1028 = mux(_T_1027, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_1029 = and(_T_1028, stbuf_data[0]) @[el2_lsu_stbuf.scala 223:98] - node _T_1030 = bits(stbuf_match_lo, 1, 1) @[el2_lsu_stbuf.scala 223:93] + node _T_1029 = and(_T_1028, stbuf_data[0]) @[el2_lsu_stbuf.scala 217:97] + node _T_1030 = bits(stbuf_match_lo, 1, 1) @[el2_lsu_stbuf.scala 217:92] node _T_1031 = bits(_T_1030, 0, 0) @[Bitwise.scala 72:15] node _T_1032 = mux(_T_1031, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_1033 = and(_T_1032, stbuf_data[1]) @[el2_lsu_stbuf.scala 223:98] - node _T_1034 = bits(stbuf_match_lo, 2, 2) @[el2_lsu_stbuf.scala 223:93] + node _T_1033 = and(_T_1032, stbuf_data[1]) @[el2_lsu_stbuf.scala 217:97] + node _T_1034 = bits(stbuf_match_lo, 2, 2) @[el2_lsu_stbuf.scala 217:92] node _T_1035 = bits(_T_1034, 0, 0) @[Bitwise.scala 72:15] node _T_1036 = mux(_T_1035, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_1037 = and(_T_1036, stbuf_data[2]) @[el2_lsu_stbuf.scala 223:98] - node _T_1038 = bits(stbuf_match_lo, 3, 3) @[el2_lsu_stbuf.scala 223:93] + node _T_1037 = and(_T_1036, stbuf_data[2]) @[el2_lsu_stbuf.scala 217:97] + node _T_1038 = bits(stbuf_match_lo, 3, 3) @[el2_lsu_stbuf.scala 217:92] node _T_1039 = bits(_T_1038, 0, 0) @[Bitwise.scala 72:15] node _T_1040 = mux(_T_1039, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_1041 = and(_T_1040, stbuf_data[3]) @[el2_lsu_stbuf.scala 223:98] - wire _T_1042 : UInt<32>[4] @[el2_lsu_stbuf.scala 223:66] - _T_1042[0] <= _T_1029 @[el2_lsu_stbuf.scala 223:66] - _T_1042[1] <= _T_1033 @[el2_lsu_stbuf.scala 223:66] - _T_1042[2] <= _T_1037 @[el2_lsu_stbuf.scala 223:66] - _T_1042[3] <= _T_1041 @[el2_lsu_stbuf.scala 223:66] - node _T_1043 = or(_T_1042[3], _T_1042[2]) @[el2_lsu_stbuf.scala 223:131] - node _T_1044 = or(_T_1043, _T_1042[1]) @[el2_lsu_stbuf.scala 223:131] - node stbuf_fwddata_lo_pre_m = or(_T_1044, _T_1042[0]) @[el2_lsu_stbuf.scala 223:131] - node _T_1045 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_stbuf.scala 226:55] - node _T_1046 = dshl(ldst_byteen_r, _T_1045) @[el2_lsu_stbuf.scala 226:39] - ldst_byteen_ext_r <= _T_1046 @[el2_lsu_stbuf.scala 226:22] - node ldst_byteen_hi_r = bits(ldst_byteen_ext_r, 7, 4) @[el2_lsu_stbuf.scala 227:44] - node ldst_byteen_lo_r = bits(ldst_byteen_ext_r, 3, 0) @[el2_lsu_stbuf.scala 228:44] - node _T_1047 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_stbuf.scala 230:43] - node _T_1048 = bits(io.lsu_addr_r, 31, 2) @[el2_lsu_stbuf.scala 230:67] - node _T_1049 = eq(_T_1047, _T_1048) @[el2_lsu_stbuf.scala 230:50] - node _T_1050 = and(_T_1049, io.lsu_pkt_r.valid) @[el2_lsu_stbuf.scala 230:75] - node _T_1051 = and(_T_1050, io.lsu_pkt_r.store) @[el2_lsu_stbuf.scala 230:96] - node _T_1052 = eq(io.lsu_pkt_r.dma, UInt<1>("h00")) @[el2_lsu_stbuf.scala 230:119] - node ld_addr_rhit_lo_lo = and(_T_1051, _T_1052) @[el2_lsu_stbuf.scala 230:117] - node _T_1053 = bits(io.end_addr_m, 31, 2) @[el2_lsu_stbuf.scala 231:43] - node _T_1054 = bits(io.lsu_addr_r, 31, 2) @[el2_lsu_stbuf.scala 231:67] - node _T_1055 = eq(_T_1053, _T_1054) @[el2_lsu_stbuf.scala 231:50] - node _T_1056 = and(_T_1055, io.lsu_pkt_r.valid) @[el2_lsu_stbuf.scala 231:75] - node _T_1057 = and(_T_1056, io.lsu_pkt_r.store) @[el2_lsu_stbuf.scala 231:96] - node _T_1058 = eq(io.lsu_pkt_r.dma, UInt<1>("h00")) @[el2_lsu_stbuf.scala 231:119] - node ld_addr_rhit_lo_hi = and(_T_1057, _T_1058) @[el2_lsu_stbuf.scala 231:117] - node _T_1059 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_stbuf.scala 232:43] - node _T_1060 = bits(io.end_addr_r, 31, 2) @[el2_lsu_stbuf.scala 232:67] - node _T_1061 = eq(_T_1059, _T_1060) @[el2_lsu_stbuf.scala 232:50] - node _T_1062 = and(_T_1061, io.lsu_pkt_r.valid) @[el2_lsu_stbuf.scala 232:75] - node _T_1063 = and(_T_1062, io.lsu_pkt_r.store) @[el2_lsu_stbuf.scala 232:96] - node _T_1064 = eq(io.lsu_pkt_r.dma, UInt<1>("h00")) @[el2_lsu_stbuf.scala 232:119] - node _T_1065 = and(_T_1063, _T_1064) @[el2_lsu_stbuf.scala 232:117] - node ld_addr_rhit_hi_lo = and(_T_1065, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 232:137] - node _T_1066 = bits(io.end_addr_m, 31, 2) @[el2_lsu_stbuf.scala 233:43] - node _T_1067 = bits(io.end_addr_r, 31, 2) @[el2_lsu_stbuf.scala 233:67] - node _T_1068 = eq(_T_1066, _T_1067) @[el2_lsu_stbuf.scala 233:50] - node _T_1069 = and(_T_1068, io.lsu_pkt_r.valid) @[el2_lsu_stbuf.scala 233:75] - node _T_1070 = and(_T_1069, io.lsu_pkt_r.store) @[el2_lsu_stbuf.scala 233:96] - node _T_1071 = eq(io.lsu_pkt_r.dma, UInt<1>("h00")) @[el2_lsu_stbuf.scala 233:119] - node _T_1072 = and(_T_1070, _T_1071) @[el2_lsu_stbuf.scala 233:117] - node ld_addr_rhit_hi_hi = and(_T_1072, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 233:137] - node _T_1073 = bits(ldst_byteen_lo_r, 0, 0) @[el2_lsu_stbuf.scala 235:98] - node _T_1074 = and(ld_addr_rhit_lo_lo, _T_1073) @[el2_lsu_stbuf.scala 235:80] - node _T_1075 = bits(ldst_byteen_lo_r, 1, 1) @[el2_lsu_stbuf.scala 235:98] - node _T_1076 = and(ld_addr_rhit_lo_lo, _T_1075) @[el2_lsu_stbuf.scala 235:80] - node _T_1077 = bits(ldst_byteen_lo_r, 2, 2) @[el2_lsu_stbuf.scala 235:98] - node _T_1078 = and(ld_addr_rhit_lo_lo, _T_1077) @[el2_lsu_stbuf.scala 235:80] - node _T_1079 = bits(ldst_byteen_lo_r, 3, 3) @[el2_lsu_stbuf.scala 235:98] - node _T_1080 = and(ld_addr_rhit_lo_lo, _T_1079) @[el2_lsu_stbuf.scala 235:80] + node _T_1041 = and(_T_1040, stbuf_data[3]) @[el2_lsu_stbuf.scala 217:97] + wire _T_1042 : UInt<32>[4] @[el2_lsu_stbuf.scala 217:65] + _T_1042[0] <= _T_1029 @[el2_lsu_stbuf.scala 217:65] + _T_1042[1] <= _T_1033 @[el2_lsu_stbuf.scala 217:65] + _T_1042[2] <= _T_1037 @[el2_lsu_stbuf.scala 217:65] + _T_1042[3] <= _T_1041 @[el2_lsu_stbuf.scala 217:65] + node _T_1043 = or(_T_1042[3], _T_1042[2]) @[el2_lsu_stbuf.scala 217:130] + node _T_1044 = or(_T_1043, _T_1042[1]) @[el2_lsu_stbuf.scala 217:130] + node stbuf_fwddata_lo_pre_m = or(_T_1044, _T_1042[0]) @[el2_lsu_stbuf.scala 217:130] + node _T_1045 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_stbuf.scala 220:54] + node _T_1046 = dshl(ldst_byteen_r, _T_1045) @[el2_lsu_stbuf.scala 220:38] + ldst_byteen_ext_r <= _T_1046 @[el2_lsu_stbuf.scala 220:21] + node ldst_byteen_hi_r = bits(ldst_byteen_ext_r, 7, 4) @[el2_lsu_stbuf.scala 221:43] + node ldst_byteen_lo_r = bits(ldst_byteen_ext_r, 3, 0) @[el2_lsu_stbuf.scala 222:43] + node _T_1047 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_stbuf.scala 224:42] + node _T_1048 = bits(io.lsu_addr_r, 31, 2) @[el2_lsu_stbuf.scala 224:66] + node _T_1049 = eq(_T_1047, _T_1048) @[el2_lsu_stbuf.scala 224:49] + node _T_1050 = and(_T_1049, io.lsu_pkt_r.valid) @[el2_lsu_stbuf.scala 224:74] + node _T_1051 = and(_T_1050, io.lsu_pkt_r.bits.store) @[el2_lsu_stbuf.scala 224:95] + node _T_1052 = eq(io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[el2_lsu_stbuf.scala 224:123] + node ld_addr_rhit_lo_lo = and(_T_1051, _T_1052) @[el2_lsu_stbuf.scala 224:121] + node _T_1053 = bits(io.end_addr_m, 31, 2) @[el2_lsu_stbuf.scala 225:42] + node _T_1054 = bits(io.lsu_addr_r, 31, 2) @[el2_lsu_stbuf.scala 225:66] + node _T_1055 = eq(_T_1053, _T_1054) @[el2_lsu_stbuf.scala 225:49] + node _T_1056 = and(_T_1055, io.lsu_pkt_r.valid) @[el2_lsu_stbuf.scala 225:74] + node _T_1057 = and(_T_1056, io.lsu_pkt_r.bits.store) @[el2_lsu_stbuf.scala 225:95] + node _T_1058 = eq(io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[el2_lsu_stbuf.scala 225:123] + node ld_addr_rhit_lo_hi = and(_T_1057, _T_1058) @[el2_lsu_stbuf.scala 225:121] + node _T_1059 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_stbuf.scala 226:42] + node _T_1060 = bits(io.end_addr_r, 31, 2) @[el2_lsu_stbuf.scala 226:66] + node _T_1061 = eq(_T_1059, _T_1060) @[el2_lsu_stbuf.scala 226:49] + node _T_1062 = and(_T_1061, io.lsu_pkt_r.valid) @[el2_lsu_stbuf.scala 226:74] + node _T_1063 = and(_T_1062, io.lsu_pkt_r.bits.store) @[el2_lsu_stbuf.scala 226:95] + node _T_1064 = eq(io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[el2_lsu_stbuf.scala 226:123] + node _T_1065 = and(_T_1063, _T_1064) @[el2_lsu_stbuf.scala 226:121] + node ld_addr_rhit_hi_lo = and(_T_1065, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 226:146] + node _T_1066 = bits(io.end_addr_m, 31, 2) @[el2_lsu_stbuf.scala 227:42] + node _T_1067 = bits(io.end_addr_r, 31, 2) @[el2_lsu_stbuf.scala 227:66] + node _T_1068 = eq(_T_1066, _T_1067) @[el2_lsu_stbuf.scala 227:49] + node _T_1069 = and(_T_1068, io.lsu_pkt_r.valid) @[el2_lsu_stbuf.scala 227:74] + node _T_1070 = and(_T_1069, io.lsu_pkt_r.bits.store) @[el2_lsu_stbuf.scala 227:95] + node _T_1071 = eq(io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[el2_lsu_stbuf.scala 227:123] + node _T_1072 = and(_T_1070, _T_1071) @[el2_lsu_stbuf.scala 227:121] + node ld_addr_rhit_hi_hi = and(_T_1072, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 227:146] + node _T_1073 = bits(ldst_byteen_lo_r, 0, 0) @[el2_lsu_stbuf.scala 229:97] + node _T_1074 = and(ld_addr_rhit_lo_lo, _T_1073) @[el2_lsu_stbuf.scala 229:79] + node _T_1075 = bits(ldst_byteen_lo_r, 1, 1) @[el2_lsu_stbuf.scala 229:97] + node _T_1076 = and(ld_addr_rhit_lo_lo, _T_1075) @[el2_lsu_stbuf.scala 229:79] + node _T_1077 = bits(ldst_byteen_lo_r, 2, 2) @[el2_lsu_stbuf.scala 229:97] + node _T_1078 = and(ld_addr_rhit_lo_lo, _T_1077) @[el2_lsu_stbuf.scala 229:79] + node _T_1079 = bits(ldst_byteen_lo_r, 3, 3) @[el2_lsu_stbuf.scala 229:97] + node _T_1080 = and(ld_addr_rhit_lo_lo, _T_1079) @[el2_lsu_stbuf.scala 229:79] node _T_1081 = cat(_T_1080, _T_1078) @[Cat.scala 29:58] node _T_1082 = cat(_T_1081, _T_1076) @[Cat.scala 29:58] node _T_1083 = cat(_T_1082, _T_1074) @[Cat.scala 29:58] - ld_byte_rhit_lo_lo <= _T_1083 @[el2_lsu_stbuf.scala 235:23] - node _T_1084 = bits(ldst_byteen_lo_r, 0, 0) @[el2_lsu_stbuf.scala 236:98] - node _T_1085 = and(ld_addr_rhit_lo_hi, _T_1084) @[el2_lsu_stbuf.scala 236:80] - node _T_1086 = bits(ldst_byteen_lo_r, 1, 1) @[el2_lsu_stbuf.scala 236:98] - node _T_1087 = and(ld_addr_rhit_lo_hi, _T_1086) @[el2_lsu_stbuf.scala 236:80] - node _T_1088 = bits(ldst_byteen_lo_r, 2, 2) @[el2_lsu_stbuf.scala 236:98] - node _T_1089 = and(ld_addr_rhit_lo_hi, _T_1088) @[el2_lsu_stbuf.scala 236:80] - node _T_1090 = bits(ldst_byteen_lo_r, 3, 3) @[el2_lsu_stbuf.scala 236:98] - node _T_1091 = and(ld_addr_rhit_lo_hi, _T_1090) @[el2_lsu_stbuf.scala 236:80] + ld_byte_rhit_lo_lo <= _T_1083 @[el2_lsu_stbuf.scala 229:22] + node _T_1084 = bits(ldst_byteen_lo_r, 0, 0) @[el2_lsu_stbuf.scala 230:97] + node _T_1085 = and(ld_addr_rhit_lo_hi, _T_1084) @[el2_lsu_stbuf.scala 230:79] + node _T_1086 = bits(ldst_byteen_lo_r, 1, 1) @[el2_lsu_stbuf.scala 230:97] + node _T_1087 = and(ld_addr_rhit_lo_hi, _T_1086) @[el2_lsu_stbuf.scala 230:79] + node _T_1088 = bits(ldst_byteen_lo_r, 2, 2) @[el2_lsu_stbuf.scala 230:97] + node _T_1089 = and(ld_addr_rhit_lo_hi, _T_1088) @[el2_lsu_stbuf.scala 230:79] + node _T_1090 = bits(ldst_byteen_lo_r, 3, 3) @[el2_lsu_stbuf.scala 230:97] + node _T_1091 = and(ld_addr_rhit_lo_hi, _T_1090) @[el2_lsu_stbuf.scala 230:79] node _T_1092 = cat(_T_1091, _T_1089) @[Cat.scala 29:58] node _T_1093 = cat(_T_1092, _T_1087) @[Cat.scala 29:58] node _T_1094 = cat(_T_1093, _T_1085) @[Cat.scala 29:58] - ld_byte_rhit_lo_hi <= _T_1094 @[el2_lsu_stbuf.scala 236:23] - node _T_1095 = bits(ldst_byteen_hi_r, 0, 0) @[el2_lsu_stbuf.scala 237:98] - node _T_1096 = and(ld_addr_rhit_hi_lo, _T_1095) @[el2_lsu_stbuf.scala 237:80] - node _T_1097 = bits(ldst_byteen_hi_r, 1, 1) @[el2_lsu_stbuf.scala 237:98] - node _T_1098 = and(ld_addr_rhit_hi_lo, _T_1097) @[el2_lsu_stbuf.scala 237:80] - node _T_1099 = bits(ldst_byteen_hi_r, 2, 2) @[el2_lsu_stbuf.scala 237:98] - node _T_1100 = and(ld_addr_rhit_hi_lo, _T_1099) @[el2_lsu_stbuf.scala 237:80] - node _T_1101 = bits(ldst_byteen_hi_r, 3, 3) @[el2_lsu_stbuf.scala 237:98] - node _T_1102 = and(ld_addr_rhit_hi_lo, _T_1101) @[el2_lsu_stbuf.scala 237:80] + ld_byte_rhit_lo_hi <= _T_1094 @[el2_lsu_stbuf.scala 230:22] + node _T_1095 = bits(ldst_byteen_hi_r, 0, 0) @[el2_lsu_stbuf.scala 231:97] + node _T_1096 = and(ld_addr_rhit_hi_lo, _T_1095) @[el2_lsu_stbuf.scala 231:79] + node _T_1097 = bits(ldst_byteen_hi_r, 1, 1) @[el2_lsu_stbuf.scala 231:97] + node _T_1098 = and(ld_addr_rhit_hi_lo, _T_1097) @[el2_lsu_stbuf.scala 231:79] + node _T_1099 = bits(ldst_byteen_hi_r, 2, 2) @[el2_lsu_stbuf.scala 231:97] + node _T_1100 = and(ld_addr_rhit_hi_lo, _T_1099) @[el2_lsu_stbuf.scala 231:79] + node _T_1101 = bits(ldst_byteen_hi_r, 3, 3) @[el2_lsu_stbuf.scala 231:97] + node _T_1102 = and(ld_addr_rhit_hi_lo, _T_1101) @[el2_lsu_stbuf.scala 231:79] node _T_1103 = cat(_T_1102, _T_1100) @[Cat.scala 29:58] node _T_1104 = cat(_T_1103, _T_1098) @[Cat.scala 29:58] node _T_1105 = cat(_T_1104, _T_1096) @[Cat.scala 29:58] - ld_byte_rhit_hi_lo <= _T_1105 @[el2_lsu_stbuf.scala 237:23] - node _T_1106 = bits(ldst_byteen_hi_r, 0, 0) @[el2_lsu_stbuf.scala 238:98] - node _T_1107 = and(ld_addr_rhit_hi_hi, _T_1106) @[el2_lsu_stbuf.scala 238:80] - node _T_1108 = bits(ldst_byteen_hi_r, 1, 1) @[el2_lsu_stbuf.scala 238:98] - node _T_1109 = and(ld_addr_rhit_hi_hi, _T_1108) @[el2_lsu_stbuf.scala 238:80] - node _T_1110 = bits(ldst_byteen_hi_r, 2, 2) @[el2_lsu_stbuf.scala 238:98] - node _T_1111 = and(ld_addr_rhit_hi_hi, _T_1110) @[el2_lsu_stbuf.scala 238:80] - node _T_1112 = bits(ldst_byteen_hi_r, 3, 3) @[el2_lsu_stbuf.scala 238:98] - node _T_1113 = and(ld_addr_rhit_hi_hi, _T_1112) @[el2_lsu_stbuf.scala 238:80] + ld_byte_rhit_hi_lo <= _T_1105 @[el2_lsu_stbuf.scala 231:22] + node _T_1106 = bits(ldst_byteen_hi_r, 0, 0) @[el2_lsu_stbuf.scala 232:97] + node _T_1107 = and(ld_addr_rhit_hi_hi, _T_1106) @[el2_lsu_stbuf.scala 232:79] + node _T_1108 = bits(ldst_byteen_hi_r, 1, 1) @[el2_lsu_stbuf.scala 232:97] + node _T_1109 = and(ld_addr_rhit_hi_hi, _T_1108) @[el2_lsu_stbuf.scala 232:79] + node _T_1110 = bits(ldst_byteen_hi_r, 2, 2) @[el2_lsu_stbuf.scala 232:97] + node _T_1111 = and(ld_addr_rhit_hi_hi, _T_1110) @[el2_lsu_stbuf.scala 232:79] + node _T_1112 = bits(ldst_byteen_hi_r, 3, 3) @[el2_lsu_stbuf.scala 232:97] + node _T_1113 = and(ld_addr_rhit_hi_hi, _T_1112) @[el2_lsu_stbuf.scala 232:79] node _T_1114 = cat(_T_1113, _T_1111) @[Cat.scala 29:58] node _T_1115 = cat(_T_1114, _T_1109) @[Cat.scala 29:58] node _T_1116 = cat(_T_1115, _T_1107) @[Cat.scala 29:58] - ld_byte_rhit_hi_hi <= _T_1116 @[el2_lsu_stbuf.scala 238:23] - node _T_1117 = bits(ld_byte_rhit_lo_lo, 0, 0) @[el2_lsu_stbuf.scala 240:76] - node _T_1118 = bits(ld_byte_rhit_hi_lo, 0, 0) @[el2_lsu_stbuf.scala 240:100] - node _T_1119 = or(_T_1117, _T_1118) @[el2_lsu_stbuf.scala 240:80] - node _T_1120 = bits(ld_byte_rhit_lo_lo, 1, 1) @[el2_lsu_stbuf.scala 240:76] - node _T_1121 = bits(ld_byte_rhit_hi_lo, 1, 1) @[el2_lsu_stbuf.scala 240:100] - node _T_1122 = or(_T_1120, _T_1121) @[el2_lsu_stbuf.scala 240:80] - node _T_1123 = bits(ld_byte_rhit_lo_lo, 2, 2) @[el2_lsu_stbuf.scala 240:76] - node _T_1124 = bits(ld_byte_rhit_hi_lo, 2, 2) @[el2_lsu_stbuf.scala 240:100] - node _T_1125 = or(_T_1123, _T_1124) @[el2_lsu_stbuf.scala 240:80] - node _T_1126 = bits(ld_byte_rhit_lo_lo, 3, 3) @[el2_lsu_stbuf.scala 240:76] - node _T_1127 = bits(ld_byte_rhit_hi_lo, 3, 3) @[el2_lsu_stbuf.scala 240:100] - node _T_1128 = or(_T_1126, _T_1127) @[el2_lsu_stbuf.scala 240:80] + ld_byte_rhit_hi_hi <= _T_1116 @[el2_lsu_stbuf.scala 232:22] + node _T_1117 = bits(ld_byte_rhit_lo_lo, 0, 0) @[el2_lsu_stbuf.scala 234:75] + node _T_1118 = bits(ld_byte_rhit_hi_lo, 0, 0) @[el2_lsu_stbuf.scala 234:99] + node _T_1119 = or(_T_1117, _T_1118) @[el2_lsu_stbuf.scala 234:79] + node _T_1120 = bits(ld_byte_rhit_lo_lo, 1, 1) @[el2_lsu_stbuf.scala 234:75] + node _T_1121 = bits(ld_byte_rhit_hi_lo, 1, 1) @[el2_lsu_stbuf.scala 234:99] + node _T_1122 = or(_T_1120, _T_1121) @[el2_lsu_stbuf.scala 234:79] + node _T_1123 = bits(ld_byte_rhit_lo_lo, 2, 2) @[el2_lsu_stbuf.scala 234:75] + node _T_1124 = bits(ld_byte_rhit_hi_lo, 2, 2) @[el2_lsu_stbuf.scala 234:99] + node _T_1125 = or(_T_1123, _T_1124) @[el2_lsu_stbuf.scala 234:79] + node _T_1126 = bits(ld_byte_rhit_lo_lo, 3, 3) @[el2_lsu_stbuf.scala 234:75] + node _T_1127 = bits(ld_byte_rhit_hi_lo, 3, 3) @[el2_lsu_stbuf.scala 234:99] + node _T_1128 = or(_T_1126, _T_1127) @[el2_lsu_stbuf.scala 234:79] node _T_1129 = cat(_T_1128, _T_1125) @[Cat.scala 29:58] node _T_1130 = cat(_T_1129, _T_1122) @[Cat.scala 29:58] node _T_1131 = cat(_T_1130, _T_1119) @[Cat.scala 29:58] - ld_byte_rhit_lo <= _T_1131 @[el2_lsu_stbuf.scala 240:20] - node _T_1132 = bits(ld_byte_rhit_lo_hi, 0, 0) @[el2_lsu_stbuf.scala 241:76] - node _T_1133 = bits(ld_byte_rhit_hi_hi, 0, 0) @[el2_lsu_stbuf.scala 241:100] - node _T_1134 = or(_T_1132, _T_1133) @[el2_lsu_stbuf.scala 241:80] - node _T_1135 = bits(ld_byte_rhit_lo_hi, 1, 1) @[el2_lsu_stbuf.scala 241:76] - node _T_1136 = bits(ld_byte_rhit_hi_hi, 1, 1) @[el2_lsu_stbuf.scala 241:100] - node _T_1137 = or(_T_1135, _T_1136) @[el2_lsu_stbuf.scala 241:80] - node _T_1138 = bits(ld_byte_rhit_lo_hi, 2, 2) @[el2_lsu_stbuf.scala 241:76] - node _T_1139 = bits(ld_byte_rhit_hi_hi, 2, 2) @[el2_lsu_stbuf.scala 241:100] - node _T_1140 = or(_T_1138, _T_1139) @[el2_lsu_stbuf.scala 241:80] - node _T_1141 = bits(ld_byte_rhit_lo_hi, 3, 3) @[el2_lsu_stbuf.scala 241:76] - node _T_1142 = bits(ld_byte_rhit_hi_hi, 3, 3) @[el2_lsu_stbuf.scala 241:100] - node _T_1143 = or(_T_1141, _T_1142) @[el2_lsu_stbuf.scala 241:80] + ld_byte_rhit_lo <= _T_1131 @[el2_lsu_stbuf.scala 234:19] + node _T_1132 = bits(ld_byte_rhit_lo_hi, 0, 0) @[el2_lsu_stbuf.scala 235:75] + node _T_1133 = bits(ld_byte_rhit_hi_hi, 0, 0) @[el2_lsu_stbuf.scala 235:99] + node _T_1134 = or(_T_1132, _T_1133) @[el2_lsu_stbuf.scala 235:79] + node _T_1135 = bits(ld_byte_rhit_lo_hi, 1, 1) @[el2_lsu_stbuf.scala 235:75] + node _T_1136 = bits(ld_byte_rhit_hi_hi, 1, 1) @[el2_lsu_stbuf.scala 235:99] + node _T_1137 = or(_T_1135, _T_1136) @[el2_lsu_stbuf.scala 235:79] + node _T_1138 = bits(ld_byte_rhit_lo_hi, 2, 2) @[el2_lsu_stbuf.scala 235:75] + node _T_1139 = bits(ld_byte_rhit_hi_hi, 2, 2) @[el2_lsu_stbuf.scala 235:99] + node _T_1140 = or(_T_1138, _T_1139) @[el2_lsu_stbuf.scala 235:79] + node _T_1141 = bits(ld_byte_rhit_lo_hi, 3, 3) @[el2_lsu_stbuf.scala 235:75] + node _T_1142 = bits(ld_byte_rhit_hi_hi, 3, 3) @[el2_lsu_stbuf.scala 235:99] + node _T_1143 = or(_T_1141, _T_1142) @[el2_lsu_stbuf.scala 235:79] node _T_1144 = cat(_T_1143, _T_1140) @[Cat.scala 29:58] node _T_1145 = cat(_T_1144, _T_1137) @[Cat.scala 29:58] node _T_1146 = cat(_T_1145, _T_1134) @[Cat.scala 29:58] - ld_byte_rhit_hi <= _T_1146 @[el2_lsu_stbuf.scala 241:20] - node _T_1147 = bits(ld_byte_rhit_lo_lo, 0, 0) @[el2_lsu_stbuf.scala 243:49] + ld_byte_rhit_hi <= _T_1146 @[el2_lsu_stbuf.scala 235:19] + node _T_1147 = bits(ld_byte_rhit_lo_lo, 0, 0) @[el2_lsu_stbuf.scala 237:48] node _T_1148 = bits(_T_1147, 0, 0) @[Bitwise.scala 72:15] node _T_1149 = mux(_T_1148, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_1150 = bits(io.store_data_lo_r, 7, 0) @[el2_lsu_stbuf.scala 243:74] - node _T_1151 = and(_T_1149, _T_1150) @[el2_lsu_stbuf.scala 243:54] - node _T_1152 = bits(ld_byte_rhit_hi_lo, 0, 0) @[el2_lsu_stbuf.scala 243:110] + node _T_1150 = bits(io.store_data_lo_r, 7, 0) @[el2_lsu_stbuf.scala 237:73] + node _T_1151 = and(_T_1149, _T_1150) @[el2_lsu_stbuf.scala 237:53] + node _T_1152 = bits(ld_byte_rhit_hi_lo, 0, 0) @[el2_lsu_stbuf.scala 237:109] node _T_1153 = bits(_T_1152, 0, 0) @[Bitwise.scala 72:15] node _T_1154 = mux(_T_1153, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_1155 = bits(io.store_data_hi_r, 7, 0) @[el2_lsu_stbuf.scala 243:135] - node _T_1156 = and(_T_1154, _T_1155) @[el2_lsu_stbuf.scala 243:115] - node fwdpipe1_lo = or(_T_1151, _T_1156) @[el2_lsu_stbuf.scala 243:81] - node _T_1157 = bits(ld_byte_rhit_lo_lo, 1, 1) @[el2_lsu_stbuf.scala 244:49] + node _T_1155 = bits(io.store_data_hi_r, 7, 0) @[el2_lsu_stbuf.scala 237:134] + node _T_1156 = and(_T_1154, _T_1155) @[el2_lsu_stbuf.scala 237:114] + node fwdpipe1_lo = or(_T_1151, _T_1156) @[el2_lsu_stbuf.scala 237:80] + node _T_1157 = bits(ld_byte_rhit_lo_lo, 1, 1) @[el2_lsu_stbuf.scala 238:48] node _T_1158 = bits(_T_1157, 0, 0) @[Bitwise.scala 72:15] node _T_1159 = mux(_T_1158, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_1160 = bits(io.store_data_lo_r, 15, 8) @[el2_lsu_stbuf.scala 244:74] - node _T_1161 = and(_T_1159, _T_1160) @[el2_lsu_stbuf.scala 244:54] - node _T_1162 = bits(ld_byte_rhit_hi_lo, 1, 1) @[el2_lsu_stbuf.scala 244:111] + node _T_1160 = bits(io.store_data_lo_r, 15, 8) @[el2_lsu_stbuf.scala 238:73] + node _T_1161 = and(_T_1159, _T_1160) @[el2_lsu_stbuf.scala 238:53] + node _T_1162 = bits(ld_byte_rhit_hi_lo, 1, 1) @[el2_lsu_stbuf.scala 238:110] node _T_1163 = bits(_T_1162, 0, 0) @[Bitwise.scala 72:15] node _T_1164 = mux(_T_1163, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_1165 = bits(io.store_data_hi_r, 15, 8) @[el2_lsu_stbuf.scala 244:136] - node _T_1166 = and(_T_1164, _T_1165) @[el2_lsu_stbuf.scala 244:116] - node fwdpipe2_lo = or(_T_1161, _T_1166) @[el2_lsu_stbuf.scala 244:82] - node _T_1167 = bits(ld_byte_rhit_lo_lo, 2, 2) @[el2_lsu_stbuf.scala 245:49] + node _T_1165 = bits(io.store_data_hi_r, 15, 8) @[el2_lsu_stbuf.scala 238:135] + node _T_1166 = and(_T_1164, _T_1165) @[el2_lsu_stbuf.scala 238:115] + node fwdpipe2_lo = or(_T_1161, _T_1166) @[el2_lsu_stbuf.scala 238:81] + node _T_1167 = bits(ld_byte_rhit_lo_lo, 2, 2) @[el2_lsu_stbuf.scala 239:48] node _T_1168 = bits(_T_1167, 0, 0) @[Bitwise.scala 72:15] node _T_1169 = mux(_T_1168, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_1170 = bits(io.store_data_lo_r, 23, 16) @[el2_lsu_stbuf.scala 245:74] - node _T_1171 = and(_T_1169, _T_1170) @[el2_lsu_stbuf.scala 245:54] - node _T_1172 = bits(ld_byte_rhit_hi_lo, 2, 2) @[el2_lsu_stbuf.scala 245:112] + node _T_1170 = bits(io.store_data_lo_r, 23, 16) @[el2_lsu_stbuf.scala 239:73] + node _T_1171 = and(_T_1169, _T_1170) @[el2_lsu_stbuf.scala 239:53] + node _T_1172 = bits(ld_byte_rhit_hi_lo, 2, 2) @[el2_lsu_stbuf.scala 239:111] node _T_1173 = bits(_T_1172, 0, 0) @[Bitwise.scala 72:15] node _T_1174 = mux(_T_1173, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_1175 = bits(io.store_data_hi_r, 23, 16) @[el2_lsu_stbuf.scala 245:137] - node _T_1176 = and(_T_1174, _T_1175) @[el2_lsu_stbuf.scala 245:117] - node fwdpipe3_lo = or(_T_1171, _T_1176) @[el2_lsu_stbuf.scala 245:83] - node _T_1177 = bits(ld_byte_rhit_lo_lo, 3, 3) @[el2_lsu_stbuf.scala 246:49] + node _T_1175 = bits(io.store_data_hi_r, 23, 16) @[el2_lsu_stbuf.scala 239:136] + node _T_1176 = and(_T_1174, _T_1175) @[el2_lsu_stbuf.scala 239:116] + node fwdpipe3_lo = or(_T_1171, _T_1176) @[el2_lsu_stbuf.scala 239:82] + node _T_1177 = bits(ld_byte_rhit_lo_lo, 3, 3) @[el2_lsu_stbuf.scala 240:48] node _T_1178 = bits(_T_1177, 0, 0) @[Bitwise.scala 72:15] node _T_1179 = mux(_T_1178, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_1180 = bits(io.store_data_lo_r, 31, 24) @[el2_lsu_stbuf.scala 246:74] - node _T_1181 = and(_T_1179, _T_1180) @[el2_lsu_stbuf.scala 246:54] - node _T_1182 = bits(ld_byte_rhit_hi_lo, 3, 3) @[el2_lsu_stbuf.scala 246:112] + node _T_1180 = bits(io.store_data_lo_r, 31, 24) @[el2_lsu_stbuf.scala 240:73] + node _T_1181 = and(_T_1179, _T_1180) @[el2_lsu_stbuf.scala 240:53] + node _T_1182 = bits(ld_byte_rhit_hi_lo, 3, 3) @[el2_lsu_stbuf.scala 240:111] node _T_1183 = bits(_T_1182, 0, 0) @[Bitwise.scala 72:15] node _T_1184 = mux(_T_1183, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_1185 = bits(io.store_data_hi_r, 31, 8) @[el2_lsu_stbuf.scala 246:137] - node _T_1186 = and(_T_1184, _T_1185) @[el2_lsu_stbuf.scala 246:117] - node fwdpipe4_lo = or(_T_1181, _T_1186) @[el2_lsu_stbuf.scala 246:83] + node _T_1185 = bits(io.store_data_hi_r, 31, 24) @[el2_lsu_stbuf.scala 240:136] + node _T_1186 = and(_T_1184, _T_1185) @[el2_lsu_stbuf.scala 240:116] + node fwdpipe4_lo = or(_T_1181, _T_1186) @[el2_lsu_stbuf.scala 240:82] node _T_1187 = cat(fwdpipe2_lo, fwdpipe1_lo) @[Cat.scala 29:58] node _T_1188 = cat(fwdpipe4_lo, fwdpipe3_lo) @[Cat.scala 29:58] node _T_1189 = cat(_T_1188, _T_1187) @[Cat.scala 29:58] - ld_fwddata_rpipe_lo <= _T_1189 @[el2_lsu_stbuf.scala 247:24] - node _T_1190 = bits(ld_byte_rhit_lo_hi, 0, 0) @[el2_lsu_stbuf.scala 249:49] + ld_fwddata_rpipe_lo <= _T_1189 @[el2_lsu_stbuf.scala 241:23] + node _T_1190 = bits(ld_byte_rhit_lo_hi, 0, 0) @[el2_lsu_stbuf.scala 243:48] node _T_1191 = bits(_T_1190, 0, 0) @[Bitwise.scala 72:15] node _T_1192 = mux(_T_1191, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_1193 = bits(io.store_data_lo_r, 7, 0) @[el2_lsu_stbuf.scala 249:74] - node _T_1194 = and(_T_1192, _T_1193) @[el2_lsu_stbuf.scala 249:54] - node _T_1195 = bits(ld_byte_rhit_hi_hi, 0, 0) @[el2_lsu_stbuf.scala 249:110] + node _T_1193 = bits(io.store_data_lo_r, 7, 0) @[el2_lsu_stbuf.scala 243:73] + node _T_1194 = and(_T_1192, _T_1193) @[el2_lsu_stbuf.scala 243:53] + node _T_1195 = bits(ld_byte_rhit_hi_hi, 0, 0) @[el2_lsu_stbuf.scala 243:109] node _T_1196 = bits(_T_1195, 0, 0) @[Bitwise.scala 72:15] node _T_1197 = mux(_T_1196, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_1198 = bits(io.store_data_hi_r, 7, 0) @[el2_lsu_stbuf.scala 249:135] - node _T_1199 = and(_T_1197, _T_1198) @[el2_lsu_stbuf.scala 249:115] - node fwdpipe1_hi = or(_T_1194, _T_1199) @[el2_lsu_stbuf.scala 249:81] - node _T_1200 = bits(ld_byte_rhit_lo_hi, 1, 1) @[el2_lsu_stbuf.scala 250:49] + node _T_1198 = bits(io.store_data_hi_r, 7, 0) @[el2_lsu_stbuf.scala 243:134] + node _T_1199 = and(_T_1197, _T_1198) @[el2_lsu_stbuf.scala 243:114] + node fwdpipe1_hi = or(_T_1194, _T_1199) @[el2_lsu_stbuf.scala 243:80] + node _T_1200 = bits(ld_byte_rhit_lo_hi, 1, 1) @[el2_lsu_stbuf.scala 244:48] node _T_1201 = bits(_T_1200, 0, 0) @[Bitwise.scala 72:15] node _T_1202 = mux(_T_1201, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_1203 = bits(io.store_data_lo_r, 15, 8) @[el2_lsu_stbuf.scala 250:74] - node _T_1204 = and(_T_1202, _T_1203) @[el2_lsu_stbuf.scala 250:54] - node _T_1205 = bits(ld_byte_rhit_hi_hi, 1, 1) @[el2_lsu_stbuf.scala 250:111] + node _T_1203 = bits(io.store_data_lo_r, 15, 8) @[el2_lsu_stbuf.scala 244:73] + node _T_1204 = and(_T_1202, _T_1203) @[el2_lsu_stbuf.scala 244:53] + node _T_1205 = bits(ld_byte_rhit_hi_hi, 1, 1) @[el2_lsu_stbuf.scala 244:110] node _T_1206 = bits(_T_1205, 0, 0) @[Bitwise.scala 72:15] node _T_1207 = mux(_T_1206, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_1208 = bits(io.store_data_hi_r, 15, 8) @[el2_lsu_stbuf.scala 250:136] - node _T_1209 = and(_T_1207, _T_1208) @[el2_lsu_stbuf.scala 250:116] - node fwdpipe2_hi = or(_T_1204, _T_1209) @[el2_lsu_stbuf.scala 250:82] - node _T_1210 = bits(ld_byte_rhit_lo_hi, 2, 2) @[el2_lsu_stbuf.scala 251:49] + node _T_1208 = bits(io.store_data_hi_r, 15, 8) @[el2_lsu_stbuf.scala 244:135] + node _T_1209 = and(_T_1207, _T_1208) @[el2_lsu_stbuf.scala 244:115] + node fwdpipe2_hi = or(_T_1204, _T_1209) @[el2_lsu_stbuf.scala 244:81] + node _T_1210 = bits(ld_byte_rhit_lo_hi, 2, 2) @[el2_lsu_stbuf.scala 245:48] node _T_1211 = bits(_T_1210, 0, 0) @[Bitwise.scala 72:15] node _T_1212 = mux(_T_1211, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_1213 = bits(io.store_data_lo_r, 23, 16) @[el2_lsu_stbuf.scala 251:74] - node _T_1214 = and(_T_1212, _T_1213) @[el2_lsu_stbuf.scala 251:54] - node _T_1215 = bits(ld_byte_rhit_hi_hi, 2, 2) @[el2_lsu_stbuf.scala 251:112] + node _T_1213 = bits(io.store_data_lo_r, 23, 16) @[el2_lsu_stbuf.scala 245:73] + node _T_1214 = and(_T_1212, _T_1213) @[el2_lsu_stbuf.scala 245:53] + node _T_1215 = bits(ld_byte_rhit_hi_hi, 2, 2) @[el2_lsu_stbuf.scala 245:111] node _T_1216 = bits(_T_1215, 0, 0) @[Bitwise.scala 72:15] node _T_1217 = mux(_T_1216, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_1218 = bits(io.store_data_hi_r, 23, 16) @[el2_lsu_stbuf.scala 251:137] - node _T_1219 = and(_T_1217, _T_1218) @[el2_lsu_stbuf.scala 251:117] - node fwdpipe3_hi = or(_T_1214, _T_1219) @[el2_lsu_stbuf.scala 251:83] - node _T_1220 = bits(ld_byte_rhit_lo_hi, 3, 3) @[el2_lsu_stbuf.scala 252:49] + node _T_1218 = bits(io.store_data_hi_r, 23, 16) @[el2_lsu_stbuf.scala 245:136] + node _T_1219 = and(_T_1217, _T_1218) @[el2_lsu_stbuf.scala 245:116] + node fwdpipe3_hi = or(_T_1214, _T_1219) @[el2_lsu_stbuf.scala 245:82] + node _T_1220 = bits(ld_byte_rhit_lo_hi, 3, 3) @[el2_lsu_stbuf.scala 246:48] node _T_1221 = bits(_T_1220, 0, 0) @[Bitwise.scala 72:15] node _T_1222 = mux(_T_1221, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_1223 = bits(io.store_data_lo_r, 31, 24) @[el2_lsu_stbuf.scala 252:74] - node _T_1224 = and(_T_1222, _T_1223) @[el2_lsu_stbuf.scala 252:54] - node _T_1225 = bits(ld_byte_rhit_hi_hi, 3, 3) @[el2_lsu_stbuf.scala 252:112] + node _T_1223 = bits(io.store_data_lo_r, 31, 24) @[el2_lsu_stbuf.scala 246:73] + node _T_1224 = and(_T_1222, _T_1223) @[el2_lsu_stbuf.scala 246:53] + node _T_1225 = bits(ld_byte_rhit_hi_hi, 3, 3) @[el2_lsu_stbuf.scala 246:111] node _T_1226 = bits(_T_1225, 0, 0) @[Bitwise.scala 72:15] node _T_1227 = mux(_T_1226, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_1228 = bits(io.store_data_hi_r, 31, 8) @[el2_lsu_stbuf.scala 252:137] - node _T_1229 = and(_T_1227, _T_1228) @[el2_lsu_stbuf.scala 252:117] - node fwdpipe4_hi = or(_T_1224, _T_1229) @[el2_lsu_stbuf.scala 252:83] + node _T_1228 = bits(io.store_data_hi_r, 31, 24) @[el2_lsu_stbuf.scala 246:136] + node _T_1229 = and(_T_1227, _T_1228) @[el2_lsu_stbuf.scala 246:116] + node fwdpipe4_hi = or(_T_1224, _T_1229) @[el2_lsu_stbuf.scala 246:82] node _T_1230 = cat(fwdpipe2_hi, fwdpipe1_hi) @[Cat.scala 29:58] node _T_1231 = cat(fwdpipe4_hi, fwdpipe3_hi) @[Cat.scala 29:58] node _T_1232 = cat(_T_1231, _T_1230) @[Cat.scala 29:58] - ld_fwddata_rpipe_hi <= _T_1232 @[el2_lsu_stbuf.scala 253:24] - node _T_1233 = bits(ld_byte_rhit_lo_lo, 0, 0) @[el2_lsu_stbuf.scala 255:74] - node _T_1234 = bits(ld_byte_rhit_hi_lo, 0, 0) @[el2_lsu_stbuf.scala 255:98] - node _T_1235 = or(_T_1233, _T_1234) @[el2_lsu_stbuf.scala 255:78] - node _T_1236 = bits(ld_byte_rhit_lo_lo, 1, 1) @[el2_lsu_stbuf.scala 255:74] - node _T_1237 = bits(ld_byte_rhit_hi_lo, 1, 1) @[el2_lsu_stbuf.scala 255:98] - node _T_1238 = or(_T_1236, _T_1237) @[el2_lsu_stbuf.scala 255:78] - node _T_1239 = bits(ld_byte_rhit_lo_lo, 2, 2) @[el2_lsu_stbuf.scala 255:74] - node _T_1240 = bits(ld_byte_rhit_hi_lo, 2, 2) @[el2_lsu_stbuf.scala 255:98] - node _T_1241 = or(_T_1239, _T_1240) @[el2_lsu_stbuf.scala 255:78] - node _T_1242 = bits(ld_byte_rhit_lo_lo, 3, 3) @[el2_lsu_stbuf.scala 255:74] - node _T_1243 = bits(ld_byte_rhit_hi_lo, 3, 3) @[el2_lsu_stbuf.scala 255:98] - node _T_1244 = or(_T_1242, _T_1243) @[el2_lsu_stbuf.scala 255:78] + ld_fwddata_rpipe_hi <= _T_1232 @[el2_lsu_stbuf.scala 247:23] + node _T_1233 = bits(ld_byte_rhit_lo_lo, 0, 0) @[el2_lsu_stbuf.scala 249:74] + node _T_1234 = bits(ld_byte_rhit_hi_lo, 0, 0) @[el2_lsu_stbuf.scala 249:98] + node _T_1235 = or(_T_1233, _T_1234) @[el2_lsu_stbuf.scala 249:78] + node _T_1236 = bits(ld_byte_rhit_lo_lo, 1, 1) @[el2_lsu_stbuf.scala 249:74] + node _T_1237 = bits(ld_byte_rhit_hi_lo, 1, 1) @[el2_lsu_stbuf.scala 249:98] + node _T_1238 = or(_T_1236, _T_1237) @[el2_lsu_stbuf.scala 249:78] + node _T_1239 = bits(ld_byte_rhit_lo_lo, 2, 2) @[el2_lsu_stbuf.scala 249:74] + node _T_1240 = bits(ld_byte_rhit_hi_lo, 2, 2) @[el2_lsu_stbuf.scala 249:98] + node _T_1241 = or(_T_1239, _T_1240) @[el2_lsu_stbuf.scala 249:78] + node _T_1242 = bits(ld_byte_rhit_lo_lo, 3, 3) @[el2_lsu_stbuf.scala 249:74] + node _T_1243 = bits(ld_byte_rhit_hi_lo, 3, 3) @[el2_lsu_stbuf.scala 249:98] + node _T_1244 = or(_T_1242, _T_1243) @[el2_lsu_stbuf.scala 249:78] node _T_1245 = cat(_T_1244, _T_1241) @[Cat.scala 29:58] node _T_1246 = cat(_T_1245, _T_1238) @[Cat.scala 29:58] node _T_1247 = cat(_T_1246, _T_1235) @[Cat.scala 29:58] - ld_byte_hit_lo <= _T_1247 @[el2_lsu_stbuf.scala 255:18] - node _T_1248 = bits(ld_byte_rhit_lo_hi, 0, 0) @[el2_lsu_stbuf.scala 256:74] - node _T_1249 = bits(ld_byte_rhit_hi_hi, 0, 0) @[el2_lsu_stbuf.scala 256:98] - node _T_1250 = or(_T_1248, _T_1249) @[el2_lsu_stbuf.scala 256:78] - node _T_1251 = bits(ld_byte_rhit_lo_hi, 1, 1) @[el2_lsu_stbuf.scala 256:74] - node _T_1252 = bits(ld_byte_rhit_hi_hi, 1, 1) @[el2_lsu_stbuf.scala 256:98] - node _T_1253 = or(_T_1251, _T_1252) @[el2_lsu_stbuf.scala 256:78] - node _T_1254 = bits(ld_byte_rhit_lo_hi, 2, 2) @[el2_lsu_stbuf.scala 256:74] - node _T_1255 = bits(ld_byte_rhit_hi_hi, 2, 2) @[el2_lsu_stbuf.scala 256:98] - node _T_1256 = or(_T_1254, _T_1255) @[el2_lsu_stbuf.scala 256:78] - node _T_1257 = bits(ld_byte_rhit_lo_hi, 3, 3) @[el2_lsu_stbuf.scala 256:74] - node _T_1258 = bits(ld_byte_rhit_hi_hi, 3, 3) @[el2_lsu_stbuf.scala 256:98] - node _T_1259 = or(_T_1257, _T_1258) @[el2_lsu_stbuf.scala 256:78] + ld_byte_hit_lo <= _T_1247 @[el2_lsu_stbuf.scala 249:18] + node _T_1248 = bits(ld_byte_rhit_lo_hi, 0, 0) @[el2_lsu_stbuf.scala 250:74] + node _T_1249 = bits(ld_byte_rhit_hi_hi, 0, 0) @[el2_lsu_stbuf.scala 250:98] + node _T_1250 = or(_T_1248, _T_1249) @[el2_lsu_stbuf.scala 250:78] + node _T_1251 = bits(ld_byte_rhit_lo_hi, 1, 1) @[el2_lsu_stbuf.scala 250:74] + node _T_1252 = bits(ld_byte_rhit_hi_hi, 1, 1) @[el2_lsu_stbuf.scala 250:98] + node _T_1253 = or(_T_1251, _T_1252) @[el2_lsu_stbuf.scala 250:78] + node _T_1254 = bits(ld_byte_rhit_lo_hi, 2, 2) @[el2_lsu_stbuf.scala 250:74] + node _T_1255 = bits(ld_byte_rhit_hi_hi, 2, 2) @[el2_lsu_stbuf.scala 250:98] + node _T_1256 = or(_T_1254, _T_1255) @[el2_lsu_stbuf.scala 250:78] + node _T_1257 = bits(ld_byte_rhit_lo_hi, 3, 3) @[el2_lsu_stbuf.scala 250:74] + node _T_1258 = bits(ld_byte_rhit_hi_hi, 3, 3) @[el2_lsu_stbuf.scala 250:98] + node _T_1259 = or(_T_1257, _T_1258) @[el2_lsu_stbuf.scala 250:78] node _T_1260 = cat(_T_1259, _T_1256) @[Cat.scala 29:58] node _T_1261 = cat(_T_1260, _T_1253) @[Cat.scala 29:58] node _T_1262 = cat(_T_1261, _T_1250) @[Cat.scala 29:58] - ld_byte_hit_hi <= _T_1262 @[el2_lsu_stbuf.scala 256:18] - node _T_1263 = bits(ld_byte_hit_hi, 0, 0) @[el2_lsu_stbuf.scala 258:80] - node _T_1264 = or(_T_1263, stbuf_fwdbyteen_hi_pre_m_0) @[el2_lsu_stbuf.scala 258:84] - node _T_1265 = bits(ld_byte_hit_hi, 1, 1) @[el2_lsu_stbuf.scala 258:80] - node _T_1266 = or(_T_1265, stbuf_fwdbyteen_hi_pre_m_1) @[el2_lsu_stbuf.scala 258:84] - node _T_1267 = bits(ld_byte_hit_hi, 2, 2) @[el2_lsu_stbuf.scala 258:80] - node _T_1268 = or(_T_1267, stbuf_fwdbyteen_hi_pre_m_2) @[el2_lsu_stbuf.scala 258:84] - node _T_1269 = bits(ld_byte_hit_hi, 3, 3) @[el2_lsu_stbuf.scala 258:80] - node _T_1270 = or(_T_1269, stbuf_fwdbyteen_hi_pre_m_3) @[el2_lsu_stbuf.scala 258:84] + ld_byte_hit_hi <= _T_1262 @[el2_lsu_stbuf.scala 250:18] + node _T_1263 = bits(ld_byte_hit_hi, 0, 0) @[el2_lsu_stbuf.scala 252:79] + node _T_1264 = or(_T_1263, stbuf_fwdbyteen_hi_pre_m_0) @[el2_lsu_stbuf.scala 252:83] + node _T_1265 = bits(ld_byte_hit_hi, 1, 1) @[el2_lsu_stbuf.scala 252:79] + node _T_1266 = or(_T_1265, stbuf_fwdbyteen_hi_pre_m_1) @[el2_lsu_stbuf.scala 252:83] + node _T_1267 = bits(ld_byte_hit_hi, 2, 2) @[el2_lsu_stbuf.scala 252:79] + node _T_1268 = or(_T_1267, stbuf_fwdbyteen_hi_pre_m_2) @[el2_lsu_stbuf.scala 252:83] + node _T_1269 = bits(ld_byte_hit_hi, 3, 3) @[el2_lsu_stbuf.scala 252:79] + node _T_1270 = or(_T_1269, stbuf_fwdbyteen_hi_pre_m_3) @[el2_lsu_stbuf.scala 252:83] node _T_1271 = cat(_T_1270, _T_1268) @[Cat.scala 29:58] node _T_1272 = cat(_T_1271, _T_1266) @[Cat.scala 29:58] node _T_1273 = cat(_T_1272, _T_1264) @[Cat.scala 29:58] - io.stbuf_fwdbyteen_hi_m <= _T_1273 @[el2_lsu_stbuf.scala 258:28] - node _T_1274 = bits(ld_byte_hit_lo, 0, 0) @[el2_lsu_stbuf.scala 259:80] - node _T_1275 = or(_T_1274, stbuf_fwdbyteen_lo_pre_m_0) @[el2_lsu_stbuf.scala 259:84] - node _T_1276 = bits(ld_byte_hit_lo, 1, 1) @[el2_lsu_stbuf.scala 259:80] - node _T_1277 = or(_T_1276, stbuf_fwdbyteen_lo_pre_m_1) @[el2_lsu_stbuf.scala 259:84] - node _T_1278 = bits(ld_byte_hit_lo, 2, 2) @[el2_lsu_stbuf.scala 259:80] - node _T_1279 = or(_T_1278, stbuf_fwdbyteen_lo_pre_m_2) @[el2_lsu_stbuf.scala 259:84] - node _T_1280 = bits(ld_byte_hit_lo, 3, 3) @[el2_lsu_stbuf.scala 259:80] - node _T_1281 = or(_T_1280, stbuf_fwdbyteen_lo_pre_m_3) @[el2_lsu_stbuf.scala 259:84] + io.stbuf_fwdbyteen_hi_m <= _T_1273 @[el2_lsu_stbuf.scala 252:27] + node _T_1274 = bits(ld_byte_hit_lo, 0, 0) @[el2_lsu_stbuf.scala 253:79] + node _T_1275 = or(_T_1274, stbuf_fwdbyteen_lo_pre_m_0) @[el2_lsu_stbuf.scala 253:83] + node _T_1276 = bits(ld_byte_hit_lo, 1, 1) @[el2_lsu_stbuf.scala 253:79] + node _T_1277 = or(_T_1276, stbuf_fwdbyteen_lo_pre_m_1) @[el2_lsu_stbuf.scala 253:83] + node _T_1278 = bits(ld_byte_hit_lo, 2, 2) @[el2_lsu_stbuf.scala 253:79] + node _T_1279 = or(_T_1278, stbuf_fwdbyteen_lo_pre_m_2) @[el2_lsu_stbuf.scala 253:83] + node _T_1280 = bits(ld_byte_hit_lo, 3, 3) @[el2_lsu_stbuf.scala 253:79] + node _T_1281 = or(_T_1280, stbuf_fwdbyteen_lo_pre_m_3) @[el2_lsu_stbuf.scala 253:83] node _T_1282 = cat(_T_1281, _T_1279) @[Cat.scala 29:58] node _T_1283 = cat(_T_1282, _T_1277) @[Cat.scala 29:58] node _T_1284 = cat(_T_1283, _T_1275) @[Cat.scala 29:58] - io.stbuf_fwdbyteen_lo_m <= _T_1284 @[el2_lsu_stbuf.scala 259:28] - node _T_1285 = bits(ld_byte_rhit_lo, 0, 0) @[el2_lsu_stbuf.scala 262:47] - node _T_1286 = bits(ld_fwddata_rpipe_lo, 7, 0) @[el2_lsu_stbuf.scala 262:70] - node _T_1287 = bits(stbuf_fwddata_lo_pre_m, 7, 0) @[el2_lsu_stbuf.scala 262:98] - node stbuf_fwdpipe1_lo = mux(_T_1285, _T_1286, _T_1287) @[el2_lsu_stbuf.scala 262:31] - node _T_1288 = bits(ld_byte_rhit_lo, 1, 1) @[el2_lsu_stbuf.scala 263:47] - node _T_1289 = bits(ld_fwddata_rpipe_lo, 15, 8) @[el2_lsu_stbuf.scala 263:70] - node _T_1290 = bits(stbuf_fwddata_lo_pre_m, 15, 8) @[el2_lsu_stbuf.scala 263:99] - node stbuf_fwdpipe2_lo = mux(_T_1288, _T_1289, _T_1290) @[el2_lsu_stbuf.scala 263:31] - node _T_1291 = bits(ld_byte_rhit_lo, 2, 2) @[el2_lsu_stbuf.scala 264:47] - node _T_1292 = bits(ld_fwddata_rpipe_lo, 23, 16) @[el2_lsu_stbuf.scala 264:70] - node _T_1293 = bits(stbuf_fwddata_lo_pre_m, 23, 16) @[el2_lsu_stbuf.scala 264:100] - node stbuf_fwdpipe3_lo = mux(_T_1291, _T_1292, _T_1293) @[el2_lsu_stbuf.scala 264:31] - node _T_1294 = bits(ld_byte_rhit_lo, 3, 3) @[el2_lsu_stbuf.scala 265:47] - node _T_1295 = bits(ld_fwddata_rpipe_lo, 31, 24) @[el2_lsu_stbuf.scala 265:70] - node _T_1296 = bits(stbuf_fwddata_lo_pre_m, 31, 24) @[el2_lsu_stbuf.scala 265:100] - node stbuf_fwdpipe4_lo = mux(_T_1294, _T_1295, _T_1296) @[el2_lsu_stbuf.scala 265:31] + io.stbuf_fwdbyteen_lo_m <= _T_1284 @[el2_lsu_stbuf.scala 253:27] + node _T_1285 = bits(ld_byte_rhit_lo, 0, 0) @[el2_lsu_stbuf.scala 256:46] + node _T_1286 = bits(ld_fwddata_rpipe_lo, 7, 0) @[el2_lsu_stbuf.scala 256:69] + node _T_1287 = bits(stbuf_fwddata_lo_pre_m, 7, 0) @[el2_lsu_stbuf.scala 256:97] + node stbuf_fwdpipe1_lo = mux(_T_1285, _T_1286, _T_1287) @[el2_lsu_stbuf.scala 256:30] + node _T_1288 = bits(ld_byte_rhit_lo, 1, 1) @[el2_lsu_stbuf.scala 257:46] + node _T_1289 = bits(ld_fwddata_rpipe_lo, 15, 8) @[el2_lsu_stbuf.scala 257:69] + node _T_1290 = bits(stbuf_fwddata_lo_pre_m, 15, 8) @[el2_lsu_stbuf.scala 257:98] + node stbuf_fwdpipe2_lo = mux(_T_1288, _T_1289, _T_1290) @[el2_lsu_stbuf.scala 257:30] + node _T_1291 = bits(ld_byte_rhit_lo, 2, 2) @[el2_lsu_stbuf.scala 258:46] + node _T_1292 = bits(ld_fwddata_rpipe_lo, 23, 16) @[el2_lsu_stbuf.scala 258:69] + node _T_1293 = bits(stbuf_fwddata_lo_pre_m, 23, 16) @[el2_lsu_stbuf.scala 258:99] + node stbuf_fwdpipe3_lo = mux(_T_1291, _T_1292, _T_1293) @[el2_lsu_stbuf.scala 258:30] + node _T_1294 = bits(ld_byte_rhit_lo, 3, 3) @[el2_lsu_stbuf.scala 259:46] + node _T_1295 = bits(ld_fwddata_rpipe_lo, 31, 24) @[el2_lsu_stbuf.scala 259:69] + node _T_1296 = bits(stbuf_fwddata_lo_pre_m, 31, 24) @[el2_lsu_stbuf.scala 259:99] + node stbuf_fwdpipe4_lo = mux(_T_1294, _T_1295, _T_1296) @[el2_lsu_stbuf.scala 259:30] node _T_1297 = cat(stbuf_fwdpipe2_lo, stbuf_fwdpipe1_lo) @[Cat.scala 29:58] node _T_1298 = cat(stbuf_fwdpipe4_lo, stbuf_fwdpipe3_lo) @[Cat.scala 29:58] node _T_1299 = cat(_T_1298, _T_1297) @[Cat.scala 29:58] - io.stbuf_fwddata_lo_m <= _T_1299 @[el2_lsu_stbuf.scala 266:26] - node _T_1300 = bits(ld_byte_rhit_hi, 0, 0) @[el2_lsu_stbuf.scala 268:47] - node _T_1301 = bits(ld_fwddata_rpipe_hi, 7, 0) @[el2_lsu_stbuf.scala 268:70] - node _T_1302 = bits(stbuf_fwddata_hi_pre_m, 7, 0) @[el2_lsu_stbuf.scala 268:98] - node stbuf_fwdpipe1_hi = mux(_T_1300, _T_1301, _T_1302) @[el2_lsu_stbuf.scala 268:31] - node _T_1303 = bits(ld_byte_rhit_hi, 1, 1) @[el2_lsu_stbuf.scala 269:47] - node _T_1304 = bits(ld_fwddata_rpipe_hi, 15, 8) @[el2_lsu_stbuf.scala 269:70] - node _T_1305 = bits(stbuf_fwddata_hi_pre_m, 15, 8) @[el2_lsu_stbuf.scala 269:99] - node stbuf_fwdpipe2_hi = mux(_T_1303, _T_1304, _T_1305) @[el2_lsu_stbuf.scala 269:31] - node _T_1306 = bits(ld_byte_rhit_hi, 2, 2) @[el2_lsu_stbuf.scala 270:47] - node _T_1307 = bits(ld_fwddata_rpipe_hi, 23, 16) @[el2_lsu_stbuf.scala 270:70] - node _T_1308 = bits(stbuf_fwddata_hi_pre_m, 23, 16) @[el2_lsu_stbuf.scala 270:100] - node stbuf_fwdpipe3_hi = mux(_T_1306, _T_1307, _T_1308) @[el2_lsu_stbuf.scala 270:31] - node _T_1309 = bits(ld_byte_rhit_hi, 3, 3) @[el2_lsu_stbuf.scala 271:47] - node _T_1310 = bits(ld_fwddata_rpipe_hi, 31, 24) @[el2_lsu_stbuf.scala 271:70] - node _T_1311 = bits(stbuf_fwddata_hi_pre_m, 31, 24) @[el2_lsu_stbuf.scala 271:100] - node stbuf_fwdpipe4_hi = mux(_T_1309, _T_1310, _T_1311) @[el2_lsu_stbuf.scala 271:31] + io.stbuf_fwddata_lo_m <= _T_1299 @[el2_lsu_stbuf.scala 260:25] + node _T_1300 = bits(ld_byte_rhit_hi, 0, 0) @[el2_lsu_stbuf.scala 262:46] + node _T_1301 = bits(ld_fwddata_rpipe_hi, 7, 0) @[el2_lsu_stbuf.scala 262:69] + node _T_1302 = bits(stbuf_fwddata_hi_pre_m, 7, 0) @[el2_lsu_stbuf.scala 262:97] + node stbuf_fwdpipe1_hi = mux(_T_1300, _T_1301, _T_1302) @[el2_lsu_stbuf.scala 262:30] + node _T_1303 = bits(ld_byte_rhit_hi, 1, 1) @[el2_lsu_stbuf.scala 263:46] + node _T_1304 = bits(ld_fwddata_rpipe_hi, 15, 8) @[el2_lsu_stbuf.scala 263:69] + node _T_1305 = bits(stbuf_fwddata_hi_pre_m, 15, 8) @[el2_lsu_stbuf.scala 263:98] + node stbuf_fwdpipe2_hi = mux(_T_1303, _T_1304, _T_1305) @[el2_lsu_stbuf.scala 263:30] + node _T_1306 = bits(ld_byte_rhit_hi, 2, 2) @[el2_lsu_stbuf.scala 264:46] + node _T_1307 = bits(ld_fwddata_rpipe_hi, 23, 16) @[el2_lsu_stbuf.scala 264:69] + node _T_1308 = bits(stbuf_fwddata_hi_pre_m, 23, 16) @[el2_lsu_stbuf.scala 264:99] + node stbuf_fwdpipe3_hi = mux(_T_1306, _T_1307, _T_1308) @[el2_lsu_stbuf.scala 264:30] + node _T_1309 = bits(ld_byte_rhit_hi, 3, 3) @[el2_lsu_stbuf.scala 265:46] + node _T_1310 = bits(ld_fwddata_rpipe_hi, 31, 24) @[el2_lsu_stbuf.scala 265:69] + node _T_1311 = bits(stbuf_fwddata_hi_pre_m, 31, 24) @[el2_lsu_stbuf.scala 265:99] + node stbuf_fwdpipe4_hi = mux(_T_1309, _T_1310, _T_1311) @[el2_lsu_stbuf.scala 265:30] node _T_1312 = cat(stbuf_fwdpipe2_hi, stbuf_fwdpipe1_hi) @[Cat.scala 29:58] node _T_1313 = cat(stbuf_fwdpipe4_hi, stbuf_fwdpipe3_hi) @[Cat.scala 29:58] node _T_1314 = cat(_T_1313, _T_1312) @[Cat.scala 29:58] - io.stbuf_fwddata_hi_m <= _T_1314 @[el2_lsu_stbuf.scala 272:26] + io.stbuf_fwddata_hi_m <= _T_1314 @[el2_lsu_stbuf.scala 266:25] diff --git a/el2_lsu_stbuf.v b/el2_lsu_stbuf.v index 440356f4..7f643353 100644 --- a/el2_lsu_stbuf.v +++ b/el2_lsu_stbuf.v @@ -4,20 +4,20 @@ module rvclkhdr( input io_en, input io_scan_mode ); - wire clkhdr_Q; // @[beh_lib.scala 332:24] - wire clkhdr_CK; // @[beh_lib.scala 332:24] - wire clkhdr_EN; // @[beh_lib.scala 332:24] - wire clkhdr_SE; // @[beh_lib.scala 332:24] - TEC_RV_ICG clkhdr ( // @[beh_lib.scala 332:24] + wire clkhdr_Q; // @[el2_lib.scala 474:26] + wire clkhdr_CK; // @[el2_lib.scala 474:26] + wire clkhdr_EN; // @[el2_lib.scala 474:26] + wire clkhdr_SE; // @[el2_lib.scala 474:26] + gated_latch clkhdr ( // @[el2_lib.scala 474:26] .Q(clkhdr_Q), .CK(clkhdr_CK), .EN(clkhdr_EN), .SE(clkhdr_SE) ); - assign io_l1clk = clkhdr_Q; // @[beh_lib.scala 333:12] - assign clkhdr_CK = io_clk; // @[beh_lib.scala 334:16] - assign clkhdr_EN = io_en; // @[beh_lib.scala 335:16] - assign clkhdr_SE = io_scan_mode; // @[beh_lib.scala 336:16] + assign io_l1clk = clkhdr_Q; // @[el2_lib.scala 475:14] + assign clkhdr_CK = io_clk; // @[el2_lib.scala 476:18] + assign clkhdr_EN = io_en; // @[el2_lib.scala 477:18] + assign clkhdr_SE = io_scan_mode; // @[el2_lib.scala 478:18] endmodule module el2_lsu_stbuf( input clock, @@ -26,32 +26,32 @@ module el2_lsu_stbuf( input io_lsu_c1_r_clk, input io_lsu_stbuf_c1_clk, input io_lsu_free_c2_clk, - input io_lsu_pkt_m_fast_int, - input io_lsu_pkt_m_by, - input io_lsu_pkt_m_half, - input io_lsu_pkt_m_word, - input io_lsu_pkt_m_dword, - input io_lsu_pkt_m_load, - input io_lsu_pkt_m_store, - input io_lsu_pkt_m_unsign, - input io_lsu_pkt_m_dma, - input io_lsu_pkt_m_store_data_bypass_d, - input io_lsu_pkt_m_load_ldst_bypass_d, - input io_lsu_pkt_m_store_data_bypass_m, input io_lsu_pkt_m_valid, - input io_lsu_pkt_r_fast_int, - input io_lsu_pkt_r_by, - input io_lsu_pkt_r_half, - input io_lsu_pkt_r_word, - input io_lsu_pkt_r_dword, - input io_lsu_pkt_r_load, - input io_lsu_pkt_r_store, - input io_lsu_pkt_r_unsign, - input io_lsu_pkt_r_dma, - input io_lsu_pkt_r_store_data_bypass_d, - input io_lsu_pkt_r_load_ldst_bypass_d, - input io_lsu_pkt_r_store_data_bypass_m, + input io_lsu_pkt_m_bits_fast_int, + input io_lsu_pkt_m_bits_by, + input io_lsu_pkt_m_bits_half, + input io_lsu_pkt_m_bits_word, + input io_lsu_pkt_m_bits_dword, + input io_lsu_pkt_m_bits_load, + input io_lsu_pkt_m_bits_store, + input io_lsu_pkt_m_bits_unsign, + input io_lsu_pkt_m_bits_dma, + input io_lsu_pkt_m_bits_store_data_bypass_d, + input io_lsu_pkt_m_bits_load_ldst_bypass_d, + input io_lsu_pkt_m_bits_store_data_bypass_m, input io_lsu_pkt_r_valid, + input io_lsu_pkt_r_bits_fast_int, + input io_lsu_pkt_r_bits_by, + input io_lsu_pkt_r_bits_half, + input io_lsu_pkt_r_bits_word, + input io_lsu_pkt_r_bits_dword, + input io_lsu_pkt_r_bits_load, + input io_lsu_pkt_r_bits_store, + input io_lsu_pkt_r_bits_unsign, + input io_lsu_pkt_r_bits_dma, + input io_lsu_pkt_r_bits_store_data_bypass_d, + input io_lsu_pkt_r_bits_load_ldst_bypass_d, + input io_lsu_pkt_r_bits_store_data_bypass_m, input io_store_stbuf_reqvld_r, input io_lsu_commit_r, input io_dec_lsu_valid_raw_d, @@ -108,317 +108,317 @@ module el2_lsu_stbuf( reg [31:0] _RAND_22; reg [31:0] _RAND_23; `endif // RANDOMIZE_REG_INIT - wire rvclkhdr_io_l1clk; // @[beh_lib.scala 352:21] - wire rvclkhdr_io_clk; // @[beh_lib.scala 352:21] - wire rvclkhdr_io_en; // @[beh_lib.scala 352:21] - wire rvclkhdr_io_scan_mode; // @[beh_lib.scala 352:21] - wire rvclkhdr_1_io_l1clk; // @[beh_lib.scala 352:21] - wire rvclkhdr_1_io_clk; // @[beh_lib.scala 352:21] - wire rvclkhdr_1_io_en; // @[beh_lib.scala 352:21] - wire rvclkhdr_1_io_scan_mode; // @[beh_lib.scala 352:21] - wire rvclkhdr_2_io_l1clk; // @[beh_lib.scala 352:21] - wire rvclkhdr_2_io_clk; // @[beh_lib.scala 352:21] - wire rvclkhdr_2_io_en; // @[beh_lib.scala 352:21] - wire rvclkhdr_2_io_scan_mode; // @[beh_lib.scala 352:21] - wire rvclkhdr_3_io_l1clk; // @[beh_lib.scala 352:21] - wire rvclkhdr_3_io_clk; // @[beh_lib.scala 352:21] - wire rvclkhdr_3_io_en; // @[beh_lib.scala 352:21] - wire rvclkhdr_3_io_scan_mode; // @[beh_lib.scala 352:21] - wire rvclkhdr_4_io_l1clk; // @[beh_lib.scala 352:21] - wire rvclkhdr_4_io_clk; // @[beh_lib.scala 352:21] - wire rvclkhdr_4_io_en; // @[beh_lib.scala 352:21] - wire rvclkhdr_4_io_scan_mode; // @[beh_lib.scala 352:21] - wire rvclkhdr_5_io_l1clk; // @[beh_lib.scala 352:21] - wire rvclkhdr_5_io_clk; // @[beh_lib.scala 352:21] - wire rvclkhdr_5_io_en; // @[beh_lib.scala 352:21] - wire rvclkhdr_5_io_scan_mode; // @[beh_lib.scala 352:21] - wire rvclkhdr_6_io_l1clk; // @[beh_lib.scala 352:21] - wire rvclkhdr_6_io_clk; // @[beh_lib.scala 352:21] - wire rvclkhdr_6_io_en; // @[beh_lib.scala 352:21] - wire rvclkhdr_6_io_scan_mode; // @[beh_lib.scala 352:21] - wire rvclkhdr_7_io_l1clk; // @[beh_lib.scala 352:21] - wire rvclkhdr_7_io_clk; // @[beh_lib.scala 352:21] - wire rvclkhdr_7_io_en; // @[beh_lib.scala 352:21] - wire rvclkhdr_7_io_scan_mode; // @[beh_lib.scala 352:21] - wire [1:0] _T_5 = io_lsu_pkt_r_half ? 2'h3 : 2'h0; // @[Mux.scala 27:72] - wire [3:0] _T_6 = io_lsu_pkt_r_word ? 4'hf : 4'h0; // @[Mux.scala 27:72] - wire [7:0] _T_7 = io_lsu_pkt_r_dword ? 8'hff : 8'h0; // @[Mux.scala 27:72] - wire [1:0] _GEN_10 = {{1'd0}, io_lsu_pkt_r_by}; // @[Mux.scala 27:72] + wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_2_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_2_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_4_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_4_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_5_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_5_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_6_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_6_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_6_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_6_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_7_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_7_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_7_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_7_io_scan_mode; // @[el2_lib.scala 508:23] + wire [1:0] _T_5 = io_lsu_pkt_r_bits_half ? 2'h3 : 2'h0; // @[Mux.scala 27:72] + wire [3:0] _T_6 = io_lsu_pkt_r_bits_word ? 4'hf : 4'h0; // @[Mux.scala 27:72] + wire [7:0] _T_7 = io_lsu_pkt_r_bits_dword ? 8'hff : 8'h0; // @[Mux.scala 27:72] + wire [1:0] _GEN_10 = {{1'd0}, io_lsu_pkt_r_bits_by}; // @[Mux.scala 27:72] wire [1:0] _T_8 = _GEN_10 | _T_5; // @[Mux.scala 27:72] wire [3:0] _GEN_11 = {{2'd0}, _T_8}; // @[Mux.scala 27:72] wire [3:0] _T_9 = _GEN_11 | _T_6; // @[Mux.scala 27:72] wire [7:0] _GEN_12 = {{4'd0}, _T_9}; // @[Mux.scala 27:72] wire [7:0] ldst_byteen_r = _GEN_12 | _T_7; // @[Mux.scala 27:72] - wire ldst_dual_d = io_lsu_addr_d[2] != io_end_addr_d[2]; // @[el2_lsu_stbuf.scala 118:40] - reg ldst_dual_r; // @[el2_lsu_stbuf.scala 177:53] - wire dual_stbuf_write_r = ldst_dual_r & io_store_stbuf_reqvld_r; // @[el2_lsu_stbuf.scala 119:41] - wire [10:0] _GEN_13 = {{3'd0}, ldst_byteen_r}; // @[el2_lsu_stbuf.scala 121:40] - wire [10:0] _T_14 = _GEN_13 << io_lsu_addr_r[1:0]; // @[el2_lsu_stbuf.scala 121:40] - wire [7:0] store_byteen_ext_r = _T_14[7:0]; // @[el2_lsu_stbuf.scala 121:23] - wire [3:0] _T_17 = io_lsu_pkt_r_store ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] store_byteen_hi_r = store_byteen_ext_r[7:4] & _T_17; // @[el2_lsu_stbuf.scala 122:52] - wire [3:0] store_byteen_lo_r = store_byteen_ext_r[3:0] & _T_17; // @[el2_lsu_stbuf.scala 123:52] + wire ldst_dual_d = io_lsu_addr_d[2] != io_end_addr_d[2]; // @[el2_lsu_stbuf.scala 117:39] + reg ldst_dual_r; // @[el2_lsu_stbuf.scala 171:52] + wire dual_stbuf_write_r = ldst_dual_r & io_store_stbuf_reqvld_r; // @[el2_lsu_stbuf.scala 118:40] + wire [10:0] _GEN_13 = {{3'd0}, ldst_byteen_r}; // @[el2_lsu_stbuf.scala 120:39] + wire [10:0] _T_14 = _GEN_13 << io_lsu_addr_r[1:0]; // @[el2_lsu_stbuf.scala 120:39] + wire [7:0] store_byteen_ext_r = _T_14[7:0]; // @[el2_lsu_stbuf.scala 120:22] + wire [3:0] _T_17 = io_lsu_pkt_r_bits_store ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] store_byteen_hi_r = store_byteen_ext_r[7:4] & _T_17; // @[el2_lsu_stbuf.scala 121:52] + wire [3:0] store_byteen_lo_r = store_byteen_ext_r[3:0] & _T_17; // @[el2_lsu_stbuf.scala 122:52] reg [1:0] RdPtr; // @[Reg.scala 27:20] - wire [1:0] RdPtrPlus1 = RdPtr + 2'h1; // @[el2_lsu_stbuf.scala 125:27] + wire [1:0] RdPtrPlus1 = RdPtr + 2'h1; // @[el2_lsu_stbuf.scala 124:26] reg [1:0] WrPtr; // @[Reg.scala 27:20] - wire [1:0] WrPtrPlus1 = WrPtr + 2'h1; // @[el2_lsu_stbuf.scala 126:27] - wire [1:0] WrPtrPlus2 = WrPtr + 2'h2; // @[el2_lsu_stbuf.scala 127:27] - reg [15:0] stbuf_addr_0; // @[beh_lib.scala 358:14] - wire _T_27 = stbuf_addr_0[15:2] == io_lsu_addr_r[15:2]; // @[el2_lsu_stbuf.scala 131:120] - reg _T_588; // @[el2_lsu_stbuf.scala 164:88] - reg _T_580; // @[el2_lsu_stbuf.scala 164:88] - reg _T_572; // @[el2_lsu_stbuf.scala 164:88] - reg _T_564; // @[el2_lsu_stbuf.scala 164:88] + wire [1:0] WrPtrPlus1 = WrPtr + 2'h1; // @[el2_lsu_stbuf.scala 125:26] + wire [1:0] WrPtrPlus2 = WrPtr + 2'h2; // @[el2_lsu_stbuf.scala 126:26] + reg [15:0] stbuf_addr_0; // @[el2_lib.scala 514:16] + wire _T_27 = stbuf_addr_0[15:2] == io_lsu_addr_r[15:2]; // @[el2_lsu_stbuf.scala 130:120] + reg _T_588; // @[el2_lsu_stbuf.scala 163:88] + reg _T_580; // @[el2_lsu_stbuf.scala 163:88] + reg _T_572; // @[el2_lsu_stbuf.scala 163:88] + reg _T_564; // @[el2_lsu_stbuf.scala 163:88] wire [3:0] stbuf_vld = {_T_588,_T_580,_T_572,_T_564}; // @[Cat.scala 29:58] - wire _T_29 = _T_27 & stbuf_vld[0]; // @[el2_lsu_stbuf.scala 131:179] - reg _T_623; // @[el2_lsu_stbuf.scala 166:62] - reg _T_615; // @[el2_lsu_stbuf.scala 166:62] - reg _T_607; // @[el2_lsu_stbuf.scala 166:62] - reg _T_599; // @[el2_lsu_stbuf.scala 166:62] + wire _T_29 = _T_27 & stbuf_vld[0]; // @[el2_lsu_stbuf.scala 130:179] + reg _T_623; // @[el2_lsu_stbuf.scala 164:92] + reg _T_615; // @[el2_lsu_stbuf.scala 164:92] + reg _T_607; // @[el2_lsu_stbuf.scala 164:92] + reg _T_599; // @[el2_lsu_stbuf.scala 164:92] wire [3:0] stbuf_dma_kill = {_T_623,_T_615,_T_607,_T_599}; // @[Cat.scala 29:58] - wire _T_31 = ~stbuf_dma_kill[0]; // @[el2_lsu_stbuf.scala 131:197] - wire _T_32 = _T_29 & _T_31; // @[el2_lsu_stbuf.scala 131:195] - wire _T_212 = io_lsu_stbuf_commit_any | io_stbuf_reqvld_flushed_any; // @[el2_lsu_stbuf.scala 142:78] - wire _T_213 = 2'h3 == RdPtr; // @[el2_lsu_stbuf.scala 142:121] - wire _T_215 = _T_212 & _T_213; // @[el2_lsu_stbuf.scala 142:109] - wire _T_209 = 2'h2 == RdPtr; // @[el2_lsu_stbuf.scala 142:121] - wire _T_211 = _T_212 & _T_209; // @[el2_lsu_stbuf.scala 142:109] - wire _T_205 = 2'h1 == RdPtr; // @[el2_lsu_stbuf.scala 142:121] - wire _T_207 = _T_212 & _T_205; // @[el2_lsu_stbuf.scala 142:109] - wire _T_201 = 2'h0 == RdPtr; // @[el2_lsu_stbuf.scala 142:121] - wire _T_203 = _T_212 & _T_201; // @[el2_lsu_stbuf.scala 142:109] + wire _T_31 = ~stbuf_dma_kill[0]; // @[el2_lsu_stbuf.scala 130:197] + wire _T_32 = _T_29 & _T_31; // @[el2_lsu_stbuf.scala 130:195] + wire _T_212 = io_lsu_stbuf_commit_any | io_stbuf_reqvld_flushed_any; // @[el2_lsu_stbuf.scala 141:78] + wire _T_213 = 2'h3 == RdPtr; // @[el2_lsu_stbuf.scala 141:121] + wire _T_215 = _T_212 & _T_213; // @[el2_lsu_stbuf.scala 141:109] + wire _T_209 = 2'h2 == RdPtr; // @[el2_lsu_stbuf.scala 141:121] + wire _T_211 = _T_212 & _T_209; // @[el2_lsu_stbuf.scala 141:109] + wire _T_205 = 2'h1 == RdPtr; // @[el2_lsu_stbuf.scala 141:121] + wire _T_207 = _T_212 & _T_205; // @[el2_lsu_stbuf.scala 141:109] + wire _T_201 = 2'h0 == RdPtr; // @[el2_lsu_stbuf.scala 141:121] + wire _T_203 = _T_212 & _T_201; // @[el2_lsu_stbuf.scala 141:109] wire [3:0] stbuf_reset = {_T_215,_T_211,_T_207,_T_203}; // @[Cat.scala 29:58] - wire _T_34 = ~stbuf_reset[0]; // @[el2_lsu_stbuf.scala 131:218] - wire _T_35 = _T_32 & _T_34; // @[el2_lsu_stbuf.scala 131:216] - reg [15:0] stbuf_addr_1; // @[beh_lib.scala 358:14] - wire _T_38 = stbuf_addr_1[15:2] == io_lsu_addr_r[15:2]; // @[el2_lsu_stbuf.scala 131:120] - wire _T_40 = _T_38 & stbuf_vld[1]; // @[el2_lsu_stbuf.scala 131:179] - wire _T_42 = ~stbuf_dma_kill[1]; // @[el2_lsu_stbuf.scala 131:197] - wire _T_43 = _T_40 & _T_42; // @[el2_lsu_stbuf.scala 131:195] - wire _T_45 = ~stbuf_reset[1]; // @[el2_lsu_stbuf.scala 131:218] - wire _T_46 = _T_43 & _T_45; // @[el2_lsu_stbuf.scala 131:216] - reg [15:0] stbuf_addr_2; // @[beh_lib.scala 358:14] - wire _T_49 = stbuf_addr_2[15:2] == io_lsu_addr_r[15:2]; // @[el2_lsu_stbuf.scala 131:120] - wire _T_51 = _T_49 & stbuf_vld[2]; // @[el2_lsu_stbuf.scala 131:179] - wire _T_53 = ~stbuf_dma_kill[2]; // @[el2_lsu_stbuf.scala 131:197] - wire _T_54 = _T_51 & _T_53; // @[el2_lsu_stbuf.scala 131:195] - wire _T_56 = ~stbuf_reset[2]; // @[el2_lsu_stbuf.scala 131:218] - wire _T_57 = _T_54 & _T_56; // @[el2_lsu_stbuf.scala 131:216] - reg [15:0] stbuf_addr_3; // @[beh_lib.scala 358:14] - wire _T_60 = stbuf_addr_3[15:2] == io_lsu_addr_r[15:2]; // @[el2_lsu_stbuf.scala 131:120] - wire _T_62 = _T_60 & stbuf_vld[3]; // @[el2_lsu_stbuf.scala 131:179] - wire _T_64 = ~stbuf_dma_kill[3]; // @[el2_lsu_stbuf.scala 131:197] - wire _T_65 = _T_62 & _T_64; // @[el2_lsu_stbuf.scala 131:195] - wire _T_67 = ~stbuf_reset[3]; // @[el2_lsu_stbuf.scala 131:218] - wire _T_68 = _T_65 & _T_67; // @[el2_lsu_stbuf.scala 131:216] + wire _T_34 = ~stbuf_reset[0]; // @[el2_lsu_stbuf.scala 130:218] + wire _T_35 = _T_32 & _T_34; // @[el2_lsu_stbuf.scala 130:216] + reg [15:0] stbuf_addr_1; // @[el2_lib.scala 514:16] + wire _T_38 = stbuf_addr_1[15:2] == io_lsu_addr_r[15:2]; // @[el2_lsu_stbuf.scala 130:120] + wire _T_40 = _T_38 & stbuf_vld[1]; // @[el2_lsu_stbuf.scala 130:179] + wire _T_42 = ~stbuf_dma_kill[1]; // @[el2_lsu_stbuf.scala 130:197] + wire _T_43 = _T_40 & _T_42; // @[el2_lsu_stbuf.scala 130:195] + wire _T_45 = ~stbuf_reset[1]; // @[el2_lsu_stbuf.scala 130:218] + wire _T_46 = _T_43 & _T_45; // @[el2_lsu_stbuf.scala 130:216] + reg [15:0] stbuf_addr_2; // @[el2_lib.scala 514:16] + wire _T_49 = stbuf_addr_2[15:2] == io_lsu_addr_r[15:2]; // @[el2_lsu_stbuf.scala 130:120] + wire _T_51 = _T_49 & stbuf_vld[2]; // @[el2_lsu_stbuf.scala 130:179] + wire _T_53 = ~stbuf_dma_kill[2]; // @[el2_lsu_stbuf.scala 130:197] + wire _T_54 = _T_51 & _T_53; // @[el2_lsu_stbuf.scala 130:195] + wire _T_56 = ~stbuf_reset[2]; // @[el2_lsu_stbuf.scala 130:218] + wire _T_57 = _T_54 & _T_56; // @[el2_lsu_stbuf.scala 130:216] + reg [15:0] stbuf_addr_3; // @[el2_lib.scala 514:16] + wire _T_60 = stbuf_addr_3[15:2] == io_lsu_addr_r[15:2]; // @[el2_lsu_stbuf.scala 130:120] + wire _T_62 = _T_60 & stbuf_vld[3]; // @[el2_lsu_stbuf.scala 130:179] + wire _T_64 = ~stbuf_dma_kill[3]; // @[el2_lsu_stbuf.scala 130:197] + wire _T_65 = _T_62 & _T_64; // @[el2_lsu_stbuf.scala 130:195] + wire _T_67 = ~stbuf_reset[3]; // @[el2_lsu_stbuf.scala 130:218] + wire _T_68 = _T_65 & _T_67; // @[el2_lsu_stbuf.scala 130:216] wire [3:0] store_matchvec_lo_r = {_T_68,_T_57,_T_46,_T_35}; // @[Cat.scala 29:58] - wire _T_73 = stbuf_addr_0[15:2] == io_end_addr_r[15:2]; // @[el2_lsu_stbuf.scala 132:120] - wire _T_75 = _T_73 & stbuf_vld[0]; // @[el2_lsu_stbuf.scala 132:179] - wire _T_78 = _T_75 & _T_31; // @[el2_lsu_stbuf.scala 132:194] - wire _T_79 = _T_78 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 132:215] - wire _T_82 = _T_79 & _T_34; // @[el2_lsu_stbuf.scala 132:236] - wire _T_85 = stbuf_addr_1[15:2] == io_end_addr_r[15:2]; // @[el2_lsu_stbuf.scala 132:120] - wire _T_87 = _T_85 & stbuf_vld[1]; // @[el2_lsu_stbuf.scala 132:179] - wire _T_90 = _T_87 & _T_42; // @[el2_lsu_stbuf.scala 132:194] - wire _T_91 = _T_90 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 132:215] - wire _T_94 = _T_91 & _T_45; // @[el2_lsu_stbuf.scala 132:236] - wire _T_97 = stbuf_addr_2[15:2] == io_end_addr_r[15:2]; // @[el2_lsu_stbuf.scala 132:120] - wire _T_99 = _T_97 & stbuf_vld[2]; // @[el2_lsu_stbuf.scala 132:179] - wire _T_102 = _T_99 & _T_53; // @[el2_lsu_stbuf.scala 132:194] - wire _T_103 = _T_102 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 132:215] - wire _T_106 = _T_103 & _T_56; // @[el2_lsu_stbuf.scala 132:236] - wire _T_109 = stbuf_addr_3[15:2] == io_end_addr_r[15:2]; // @[el2_lsu_stbuf.scala 132:120] - wire _T_111 = _T_109 & stbuf_vld[3]; // @[el2_lsu_stbuf.scala 132:179] - wire _T_114 = _T_111 & _T_64; // @[el2_lsu_stbuf.scala 132:194] - wire _T_115 = _T_114 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 132:215] - wire _T_118 = _T_115 & _T_67; // @[el2_lsu_stbuf.scala 132:236] + wire _T_73 = stbuf_addr_0[15:2] == io_end_addr_r[15:2]; // @[el2_lsu_stbuf.scala 131:120] + wire _T_75 = _T_73 & stbuf_vld[0]; // @[el2_lsu_stbuf.scala 131:179] + wire _T_78 = _T_75 & _T_31; // @[el2_lsu_stbuf.scala 131:194] + wire _T_79 = _T_78 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 131:215] + wire _T_82 = _T_79 & _T_34; // @[el2_lsu_stbuf.scala 131:236] + wire _T_85 = stbuf_addr_1[15:2] == io_end_addr_r[15:2]; // @[el2_lsu_stbuf.scala 131:120] + wire _T_87 = _T_85 & stbuf_vld[1]; // @[el2_lsu_stbuf.scala 131:179] + wire _T_90 = _T_87 & _T_42; // @[el2_lsu_stbuf.scala 131:194] + wire _T_91 = _T_90 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 131:215] + wire _T_94 = _T_91 & _T_45; // @[el2_lsu_stbuf.scala 131:236] + wire _T_97 = stbuf_addr_2[15:2] == io_end_addr_r[15:2]; // @[el2_lsu_stbuf.scala 131:120] + wire _T_99 = _T_97 & stbuf_vld[2]; // @[el2_lsu_stbuf.scala 131:179] + wire _T_102 = _T_99 & _T_53; // @[el2_lsu_stbuf.scala 131:194] + wire _T_103 = _T_102 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 131:215] + wire _T_106 = _T_103 & _T_56; // @[el2_lsu_stbuf.scala 131:236] + wire _T_109 = stbuf_addr_3[15:2] == io_end_addr_r[15:2]; // @[el2_lsu_stbuf.scala 131:120] + wire _T_111 = _T_109 & stbuf_vld[3]; // @[el2_lsu_stbuf.scala 131:179] + wire _T_114 = _T_111 & _T_64; // @[el2_lsu_stbuf.scala 131:194] + wire _T_115 = _T_114 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 131:215] + wire _T_118 = _T_115 & _T_67; // @[el2_lsu_stbuf.scala 131:236] wire [3:0] store_matchvec_hi_r = {_T_118,_T_106,_T_94,_T_82}; // @[Cat.scala 29:58] - wire store_coalesce_lo_r = |store_matchvec_lo_r; // @[el2_lsu_stbuf.scala 134:50] - wire store_coalesce_hi_r = |store_matchvec_hi_r; // @[el2_lsu_stbuf.scala 135:50] - wire _T_121 = 2'h0 == WrPtr; // @[el2_lsu_stbuf.scala 138:64] - wire _T_122 = ~store_coalesce_lo_r; // @[el2_lsu_stbuf.scala 138:77] - wire _T_123 = _T_121 & _T_122; // @[el2_lsu_stbuf.scala 138:75] - wire _T_125 = _T_121 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 139:75] - wire _T_126 = ~store_coalesce_hi_r; // @[el2_lsu_stbuf.scala 139:98] - wire _T_127 = _T_125 & _T_126; // @[el2_lsu_stbuf.scala 139:96] - wire _T_128 = _T_123 | _T_127; // @[el2_lsu_stbuf.scala 138:99] - wire _T_129 = 2'h0 == WrPtrPlus1; // @[el2_lsu_stbuf.scala 140:64] - wire _T_130 = _T_129 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 140:80] - wire _T_131 = store_coalesce_lo_r | store_coalesce_hi_r; // @[el2_lsu_stbuf.scala 140:125] - wire _T_132 = ~_T_131; // @[el2_lsu_stbuf.scala 140:103] - wire _T_133 = _T_130 & _T_132; // @[el2_lsu_stbuf.scala 140:101] - wire _T_134 = _T_128 | _T_133; // @[el2_lsu_stbuf.scala 139:120] - wire _T_136 = _T_134 | store_matchvec_lo_r[0]; // @[el2_lsu_stbuf.scala 140:149] - wire _T_138 = _T_136 | store_matchvec_hi_r[0]; // @[el2_lsu_stbuf.scala 141:76] - wire _T_139 = io_ldst_stbuf_reqvld_r & _T_138; // @[el2_lsu_stbuf.scala 137:77] - wire _T_140 = 2'h1 == WrPtr; // @[el2_lsu_stbuf.scala 138:64] - wire _T_142 = _T_140 & _T_122; // @[el2_lsu_stbuf.scala 138:75] - wire _T_144 = _T_140 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 139:75] - wire _T_146 = _T_144 & _T_126; // @[el2_lsu_stbuf.scala 139:96] - wire _T_147 = _T_142 | _T_146; // @[el2_lsu_stbuf.scala 138:99] - wire _T_148 = 2'h1 == WrPtrPlus1; // @[el2_lsu_stbuf.scala 140:64] - wire _T_149 = _T_148 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 140:80] - wire _T_152 = _T_149 & _T_132; // @[el2_lsu_stbuf.scala 140:101] - wire _T_153 = _T_147 | _T_152; // @[el2_lsu_stbuf.scala 139:120] - wire _T_155 = _T_153 | store_matchvec_lo_r[1]; // @[el2_lsu_stbuf.scala 140:149] - wire _T_157 = _T_155 | store_matchvec_hi_r[1]; // @[el2_lsu_stbuf.scala 141:76] - wire _T_158 = io_ldst_stbuf_reqvld_r & _T_157; // @[el2_lsu_stbuf.scala 137:77] - wire _T_159 = 2'h2 == WrPtr; // @[el2_lsu_stbuf.scala 138:64] - wire _T_161 = _T_159 & _T_122; // @[el2_lsu_stbuf.scala 138:75] - wire _T_163 = _T_159 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 139:75] - wire _T_165 = _T_163 & _T_126; // @[el2_lsu_stbuf.scala 139:96] - wire _T_166 = _T_161 | _T_165; // @[el2_lsu_stbuf.scala 138:99] - wire _T_167 = 2'h2 == WrPtrPlus1; // @[el2_lsu_stbuf.scala 140:64] - wire _T_168 = _T_167 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 140:80] - wire _T_171 = _T_168 & _T_132; // @[el2_lsu_stbuf.scala 140:101] - wire _T_172 = _T_166 | _T_171; // @[el2_lsu_stbuf.scala 139:120] - wire _T_174 = _T_172 | store_matchvec_lo_r[2]; // @[el2_lsu_stbuf.scala 140:149] - wire _T_176 = _T_174 | store_matchvec_hi_r[2]; // @[el2_lsu_stbuf.scala 141:76] - wire _T_177 = io_ldst_stbuf_reqvld_r & _T_176; // @[el2_lsu_stbuf.scala 137:77] - wire _T_178 = 2'h3 == WrPtr; // @[el2_lsu_stbuf.scala 138:64] - wire _T_180 = _T_178 & _T_122; // @[el2_lsu_stbuf.scala 138:75] - wire _T_182 = _T_178 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 139:75] - wire _T_184 = _T_182 & _T_126; // @[el2_lsu_stbuf.scala 139:96] - wire _T_185 = _T_180 | _T_184; // @[el2_lsu_stbuf.scala 138:99] - wire _T_186 = 2'h3 == WrPtrPlus1; // @[el2_lsu_stbuf.scala 140:64] - wire _T_187 = _T_186 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 140:80] - wire _T_190 = _T_187 & _T_132; // @[el2_lsu_stbuf.scala 140:101] - wire _T_191 = _T_185 | _T_190; // @[el2_lsu_stbuf.scala 139:120] - wire _T_193 = _T_191 | store_matchvec_lo_r[3]; // @[el2_lsu_stbuf.scala 140:149] - wire _T_195 = _T_193 | store_matchvec_hi_r[3]; // @[el2_lsu_stbuf.scala 141:76] - wire _T_196 = io_ldst_stbuf_reqvld_r & _T_195; // @[el2_lsu_stbuf.scala 137:77] + wire store_coalesce_lo_r = |store_matchvec_lo_r; // @[el2_lsu_stbuf.scala 133:49] + wire store_coalesce_hi_r = |store_matchvec_hi_r; // @[el2_lsu_stbuf.scala 134:49] + wire _T_121 = 2'h0 == WrPtr; // @[el2_lsu_stbuf.scala 137:16] + wire _T_122 = ~store_coalesce_lo_r; // @[el2_lsu_stbuf.scala 137:29] + wire _T_123 = _T_121 & _T_122; // @[el2_lsu_stbuf.scala 137:27] + wire _T_125 = _T_121 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 138:29] + wire _T_126 = ~store_coalesce_hi_r; // @[el2_lsu_stbuf.scala 138:52] + wire _T_127 = _T_125 & _T_126; // @[el2_lsu_stbuf.scala 138:50] + wire _T_128 = _T_123 | _T_127; // @[el2_lsu_stbuf.scala 137:51] + wire _T_129 = 2'h0 == WrPtrPlus1; // @[el2_lsu_stbuf.scala 139:18] + wire _T_130 = _T_129 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 139:34] + wire _T_131 = store_coalesce_lo_r | store_coalesce_hi_r; // @[el2_lsu_stbuf.scala 139:79] + wire _T_132 = ~_T_131; // @[el2_lsu_stbuf.scala 139:57] + wire _T_133 = _T_130 & _T_132; // @[el2_lsu_stbuf.scala 139:55] + wire _T_134 = _T_128 | _T_133; // @[el2_lsu_stbuf.scala 138:74] + wire _T_136 = _T_134 | store_matchvec_lo_r[0]; // @[el2_lsu_stbuf.scala 139:103] + wire _T_138 = _T_136 | store_matchvec_hi_r[0]; // @[el2_lsu_stbuf.scala 140:30] + wire _T_139 = io_ldst_stbuf_reqvld_r & _T_138; // @[el2_lsu_stbuf.scala 136:76] + wire _T_140 = 2'h1 == WrPtr; // @[el2_lsu_stbuf.scala 137:16] + wire _T_142 = _T_140 & _T_122; // @[el2_lsu_stbuf.scala 137:27] + wire _T_144 = _T_140 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 138:29] + wire _T_146 = _T_144 & _T_126; // @[el2_lsu_stbuf.scala 138:50] + wire _T_147 = _T_142 | _T_146; // @[el2_lsu_stbuf.scala 137:51] + wire _T_148 = 2'h1 == WrPtrPlus1; // @[el2_lsu_stbuf.scala 139:18] + wire _T_149 = _T_148 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 139:34] + wire _T_152 = _T_149 & _T_132; // @[el2_lsu_stbuf.scala 139:55] + wire _T_153 = _T_147 | _T_152; // @[el2_lsu_stbuf.scala 138:74] + wire _T_155 = _T_153 | store_matchvec_lo_r[1]; // @[el2_lsu_stbuf.scala 139:103] + wire _T_157 = _T_155 | store_matchvec_hi_r[1]; // @[el2_lsu_stbuf.scala 140:30] + wire _T_158 = io_ldst_stbuf_reqvld_r & _T_157; // @[el2_lsu_stbuf.scala 136:76] + wire _T_159 = 2'h2 == WrPtr; // @[el2_lsu_stbuf.scala 137:16] + wire _T_161 = _T_159 & _T_122; // @[el2_lsu_stbuf.scala 137:27] + wire _T_163 = _T_159 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 138:29] + wire _T_165 = _T_163 & _T_126; // @[el2_lsu_stbuf.scala 138:50] + wire _T_166 = _T_161 | _T_165; // @[el2_lsu_stbuf.scala 137:51] + wire _T_167 = 2'h2 == WrPtrPlus1; // @[el2_lsu_stbuf.scala 139:18] + wire _T_168 = _T_167 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 139:34] + wire _T_171 = _T_168 & _T_132; // @[el2_lsu_stbuf.scala 139:55] + wire _T_172 = _T_166 | _T_171; // @[el2_lsu_stbuf.scala 138:74] + wire _T_174 = _T_172 | store_matchvec_lo_r[2]; // @[el2_lsu_stbuf.scala 139:103] + wire _T_176 = _T_174 | store_matchvec_hi_r[2]; // @[el2_lsu_stbuf.scala 140:30] + wire _T_177 = io_ldst_stbuf_reqvld_r & _T_176; // @[el2_lsu_stbuf.scala 136:76] + wire _T_178 = 2'h3 == WrPtr; // @[el2_lsu_stbuf.scala 137:16] + wire _T_180 = _T_178 & _T_122; // @[el2_lsu_stbuf.scala 137:27] + wire _T_182 = _T_178 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 138:29] + wire _T_184 = _T_182 & _T_126; // @[el2_lsu_stbuf.scala 138:50] + wire _T_185 = _T_180 | _T_184; // @[el2_lsu_stbuf.scala 137:51] + wire _T_186 = 2'h3 == WrPtrPlus1; // @[el2_lsu_stbuf.scala 139:18] + wire _T_187 = _T_186 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 139:34] + wire _T_190 = _T_187 & _T_132; // @[el2_lsu_stbuf.scala 139:55] + wire _T_191 = _T_185 | _T_190; // @[el2_lsu_stbuf.scala 138:74] + wire _T_193 = _T_191 | store_matchvec_lo_r[3]; // @[el2_lsu_stbuf.scala 139:103] + wire _T_195 = _T_193 | store_matchvec_hi_r[3]; // @[el2_lsu_stbuf.scala 140:30] + wire _T_196 = io_ldst_stbuf_reqvld_r & _T_195; // @[el2_lsu_stbuf.scala 136:76] wire [3:0] stbuf_wr_en = {_T_196,_T_177,_T_158,_T_139}; // @[Cat.scala 29:58] - wire _T_219 = ~ldst_dual_r; // @[el2_lsu_stbuf.scala 143:53] - wire _T_220 = _T_219 | io_store_stbuf_reqvld_r; // @[el2_lsu_stbuf.scala 143:66] - wire _T_223 = _T_220 & _T_121; // @[el2_lsu_stbuf.scala 143:93] - wire _T_225 = _T_223 & _T_122; // @[el2_lsu_stbuf.scala 143:123] - wire _T_227 = _T_225 | store_matchvec_lo_r[0]; // @[el2_lsu_stbuf.scala 143:147] - wire _T_232 = _T_220 & _T_140; // @[el2_lsu_stbuf.scala 143:93] - wire _T_234 = _T_232 & _T_122; // @[el2_lsu_stbuf.scala 143:123] - wire _T_236 = _T_234 | store_matchvec_lo_r[1]; // @[el2_lsu_stbuf.scala 143:147] - wire _T_241 = _T_220 & _T_159; // @[el2_lsu_stbuf.scala 143:93] - wire _T_243 = _T_241 & _T_122; // @[el2_lsu_stbuf.scala 143:123] - wire _T_245 = _T_243 | store_matchvec_lo_r[2]; // @[el2_lsu_stbuf.scala 143:147] - wire _T_250 = _T_220 & _T_178; // @[el2_lsu_stbuf.scala 143:93] - wire _T_252 = _T_250 & _T_122; // @[el2_lsu_stbuf.scala 143:123] - wire _T_254 = _T_252 | store_matchvec_lo_r[3]; // @[el2_lsu_stbuf.scala 143:147] + wire _T_219 = ~ldst_dual_r; // @[el2_lsu_stbuf.scala 142:53] + wire _T_220 = _T_219 | io_store_stbuf_reqvld_r; // @[el2_lsu_stbuf.scala 142:66] + wire _T_223 = _T_220 & _T_121; // @[el2_lsu_stbuf.scala 142:93] + wire _T_225 = _T_223 & _T_122; // @[el2_lsu_stbuf.scala 142:123] + wire _T_227 = _T_225 | store_matchvec_lo_r[0]; // @[el2_lsu_stbuf.scala 142:147] + wire _T_232 = _T_220 & _T_140; // @[el2_lsu_stbuf.scala 142:93] + wire _T_234 = _T_232 & _T_122; // @[el2_lsu_stbuf.scala 142:123] + wire _T_236 = _T_234 | store_matchvec_lo_r[1]; // @[el2_lsu_stbuf.scala 142:147] + wire _T_241 = _T_220 & _T_159; // @[el2_lsu_stbuf.scala 142:93] + wire _T_243 = _T_241 & _T_122; // @[el2_lsu_stbuf.scala 142:123] + wire _T_245 = _T_243 | store_matchvec_lo_r[2]; // @[el2_lsu_stbuf.scala 142:147] + wire _T_250 = _T_220 & _T_178; // @[el2_lsu_stbuf.scala 142:93] + wire _T_252 = _T_250 & _T_122; // @[el2_lsu_stbuf.scala 142:123] + wire _T_254 = _T_252 | store_matchvec_lo_r[3]; // @[el2_lsu_stbuf.scala 142:147] wire [3:0] sel_lo = {_T_254,_T_245,_T_236,_T_227}; // @[Cat.scala 29:58] - reg [3:0] stbuf_byteen_0; // @[el2_lsu_stbuf.scala 167:92] - wire [3:0] _T_274 = stbuf_byteen_0 | store_byteen_lo_r; // @[el2_lsu_stbuf.scala 146:87] - wire [3:0] _T_275 = stbuf_byteen_0 | store_byteen_hi_r; // @[el2_lsu_stbuf.scala 146:124] - wire [3:0] stbuf_byteenin_0 = sel_lo[0] ? _T_274 : _T_275; // @[el2_lsu_stbuf.scala 146:59] - reg [3:0] stbuf_byteen_1; // @[el2_lsu_stbuf.scala 167:92] - wire [3:0] _T_278 = stbuf_byteen_1 | store_byteen_lo_r; // @[el2_lsu_stbuf.scala 146:87] - wire [3:0] _T_279 = stbuf_byteen_1 | store_byteen_hi_r; // @[el2_lsu_stbuf.scala 146:124] - wire [3:0] stbuf_byteenin_1 = sel_lo[1] ? _T_278 : _T_279; // @[el2_lsu_stbuf.scala 146:59] - reg [3:0] stbuf_byteen_2; // @[el2_lsu_stbuf.scala 167:92] - wire [3:0] _T_282 = stbuf_byteen_2 | store_byteen_lo_r; // @[el2_lsu_stbuf.scala 146:87] - wire [3:0] _T_283 = stbuf_byteen_2 | store_byteen_hi_r; // @[el2_lsu_stbuf.scala 146:124] - wire [3:0] stbuf_byteenin_2 = sel_lo[2] ? _T_282 : _T_283; // @[el2_lsu_stbuf.scala 146:59] - reg [3:0] stbuf_byteen_3; // @[el2_lsu_stbuf.scala 167:92] - wire [3:0] _T_286 = stbuf_byteen_3 | store_byteen_lo_r; // @[el2_lsu_stbuf.scala 146:87] - wire [3:0] _T_287 = stbuf_byteen_3 | store_byteen_hi_r; // @[el2_lsu_stbuf.scala 146:124] - wire [3:0] stbuf_byteenin_3 = sel_lo[3] ? _T_286 : _T_287; // @[el2_lsu_stbuf.scala 146:59] - wire _T_291 = ~stbuf_byteen_0[0]; // @[el2_lsu_stbuf.scala 148:68] - wire _T_293 = _T_291 | store_byteen_lo_r[0]; // @[el2_lsu_stbuf.scala 148:88] - reg [31:0] stbuf_data_0; // @[beh_lib.scala 358:14] - wire [7:0] _T_296 = _T_293 ? io_store_datafn_lo_r[7:0] : stbuf_data_0[7:0]; // @[el2_lsu_stbuf.scala 148:67] - wire _T_300 = _T_291 | store_byteen_hi_r[0]; // @[el2_lsu_stbuf.scala 149:31] - wire [7:0] _T_303 = _T_300 ? io_store_datafn_hi_r[7:0] : stbuf_data_0[7:0]; // @[el2_lsu_stbuf.scala 149:10] - wire [7:0] datain1_0 = sel_lo[0] ? _T_296 : _T_303; // @[el2_lsu_stbuf.scala 148:52] - wire _T_307 = ~stbuf_byteen_1[0]; // @[el2_lsu_stbuf.scala 148:68] - wire _T_309 = _T_307 | store_byteen_lo_r[0]; // @[el2_lsu_stbuf.scala 148:88] - reg [31:0] stbuf_data_1; // @[beh_lib.scala 358:14] - wire [7:0] _T_312 = _T_309 ? io_store_datafn_lo_r[7:0] : stbuf_data_1[7:0]; // @[el2_lsu_stbuf.scala 148:67] - wire _T_316 = _T_307 | store_byteen_hi_r[0]; // @[el2_lsu_stbuf.scala 149:31] - wire [7:0] _T_319 = _T_316 ? io_store_datafn_hi_r[7:0] : stbuf_data_1[7:0]; // @[el2_lsu_stbuf.scala 149:10] - wire [7:0] datain1_1 = sel_lo[1] ? _T_312 : _T_319; // @[el2_lsu_stbuf.scala 148:52] - wire _T_323 = ~stbuf_byteen_2[0]; // @[el2_lsu_stbuf.scala 148:68] - wire _T_325 = _T_323 | store_byteen_lo_r[0]; // @[el2_lsu_stbuf.scala 148:88] - reg [31:0] stbuf_data_2; // @[beh_lib.scala 358:14] - wire [7:0] _T_328 = _T_325 ? io_store_datafn_lo_r[7:0] : stbuf_data_2[7:0]; // @[el2_lsu_stbuf.scala 148:67] - wire _T_332 = _T_323 | store_byteen_hi_r[0]; // @[el2_lsu_stbuf.scala 149:31] - wire [7:0] _T_335 = _T_332 ? io_store_datafn_hi_r[7:0] : stbuf_data_2[7:0]; // @[el2_lsu_stbuf.scala 149:10] - wire [7:0] datain1_2 = sel_lo[2] ? _T_328 : _T_335; // @[el2_lsu_stbuf.scala 148:52] - wire _T_339 = ~stbuf_byteen_3[0]; // @[el2_lsu_stbuf.scala 148:68] - wire _T_341 = _T_339 | store_byteen_lo_r[0]; // @[el2_lsu_stbuf.scala 148:88] - reg [31:0] stbuf_data_3; // @[beh_lib.scala 358:14] - wire [7:0] _T_344 = _T_341 ? io_store_datafn_lo_r[7:0] : stbuf_data_3[7:0]; // @[el2_lsu_stbuf.scala 148:67] - wire _T_348 = _T_339 | store_byteen_hi_r[0]; // @[el2_lsu_stbuf.scala 149:31] - wire [7:0] _T_351 = _T_348 ? io_store_datafn_hi_r[7:0] : stbuf_data_3[7:0]; // @[el2_lsu_stbuf.scala 149:10] - wire [7:0] datain1_3 = sel_lo[3] ? _T_344 : _T_351; // @[el2_lsu_stbuf.scala 148:52] - wire _T_355 = ~stbuf_byteen_0[1]; // @[el2_lsu_stbuf.scala 151:69] - wire _T_357 = _T_355 | store_byteen_lo_r[1]; // @[el2_lsu_stbuf.scala 151:89] - wire [7:0] _T_360 = _T_357 ? io_store_datafn_lo_r[15:8] : stbuf_data_0[15:8]; // @[el2_lsu_stbuf.scala 151:68] - wire _T_364 = _T_355 | store_byteen_hi_r[1]; // @[el2_lsu_stbuf.scala 152:31] - wire [7:0] _T_367 = _T_364 ? io_store_datafn_hi_r[15:8] : stbuf_data_0[15:8]; // @[el2_lsu_stbuf.scala 152:10] - wire [7:0] datain2_0 = sel_lo[0] ? _T_360 : _T_367; // @[el2_lsu_stbuf.scala 151:53] - wire _T_371 = ~stbuf_byteen_1[1]; // @[el2_lsu_stbuf.scala 151:69] - wire _T_373 = _T_371 | store_byteen_lo_r[1]; // @[el2_lsu_stbuf.scala 151:89] - wire [7:0] _T_376 = _T_373 ? io_store_datafn_lo_r[15:8] : stbuf_data_1[15:8]; // @[el2_lsu_stbuf.scala 151:68] - wire _T_380 = _T_371 | store_byteen_hi_r[1]; // @[el2_lsu_stbuf.scala 152:31] - wire [7:0] _T_383 = _T_380 ? io_store_datafn_hi_r[15:8] : stbuf_data_1[15:8]; // @[el2_lsu_stbuf.scala 152:10] - wire [7:0] datain2_1 = sel_lo[1] ? _T_376 : _T_383; // @[el2_lsu_stbuf.scala 151:53] - wire _T_387 = ~stbuf_byteen_2[1]; // @[el2_lsu_stbuf.scala 151:69] - wire _T_389 = _T_387 | store_byteen_lo_r[1]; // @[el2_lsu_stbuf.scala 151:89] - wire [7:0] _T_392 = _T_389 ? io_store_datafn_lo_r[15:8] : stbuf_data_2[15:8]; // @[el2_lsu_stbuf.scala 151:68] - wire _T_396 = _T_387 | store_byteen_hi_r[1]; // @[el2_lsu_stbuf.scala 152:31] - wire [7:0] _T_399 = _T_396 ? io_store_datafn_hi_r[15:8] : stbuf_data_2[15:8]; // @[el2_lsu_stbuf.scala 152:10] - wire [7:0] datain2_2 = sel_lo[2] ? _T_392 : _T_399; // @[el2_lsu_stbuf.scala 151:53] - wire _T_403 = ~stbuf_byteen_3[1]; // @[el2_lsu_stbuf.scala 151:69] - wire _T_405 = _T_403 | store_byteen_lo_r[1]; // @[el2_lsu_stbuf.scala 151:89] - wire [7:0] _T_408 = _T_405 ? io_store_datafn_lo_r[15:8] : stbuf_data_3[15:8]; // @[el2_lsu_stbuf.scala 151:68] - wire _T_412 = _T_403 | store_byteen_hi_r[1]; // @[el2_lsu_stbuf.scala 152:31] - wire [7:0] _T_415 = _T_412 ? io_store_datafn_hi_r[15:8] : stbuf_data_3[15:8]; // @[el2_lsu_stbuf.scala 152:10] - wire [7:0] datain2_3 = sel_lo[3] ? _T_408 : _T_415; // @[el2_lsu_stbuf.scala 151:53] - wire _T_419 = ~stbuf_byteen_0[2]; // @[el2_lsu_stbuf.scala 154:69] - wire _T_421 = _T_419 | store_byteen_lo_r[2]; // @[el2_lsu_stbuf.scala 154:89] - wire [7:0] _T_424 = _T_421 ? io_store_datafn_lo_r[23:16] : stbuf_data_0[23:16]; // @[el2_lsu_stbuf.scala 154:68] - wire _T_428 = _T_419 | store_byteen_hi_r[2]; // @[el2_lsu_stbuf.scala 155:31] - wire [7:0] _T_431 = _T_428 ? io_store_datafn_hi_r[23:16] : stbuf_data_0[23:16]; // @[el2_lsu_stbuf.scala 155:10] - wire [7:0] datain3_0 = sel_lo[0] ? _T_424 : _T_431; // @[el2_lsu_stbuf.scala 154:53] - wire _T_435 = ~stbuf_byteen_1[2]; // @[el2_lsu_stbuf.scala 154:69] - wire _T_437 = _T_435 | store_byteen_lo_r[2]; // @[el2_lsu_stbuf.scala 154:89] - wire [7:0] _T_440 = _T_437 ? io_store_datafn_lo_r[23:16] : stbuf_data_1[23:16]; // @[el2_lsu_stbuf.scala 154:68] - wire _T_444 = _T_435 | store_byteen_hi_r[2]; // @[el2_lsu_stbuf.scala 155:31] - wire [7:0] _T_447 = _T_444 ? io_store_datafn_hi_r[23:16] : stbuf_data_1[23:16]; // @[el2_lsu_stbuf.scala 155:10] - wire [7:0] datain3_1 = sel_lo[1] ? _T_440 : _T_447; // @[el2_lsu_stbuf.scala 154:53] - wire _T_451 = ~stbuf_byteen_2[2]; // @[el2_lsu_stbuf.scala 154:69] - wire _T_453 = _T_451 | store_byteen_lo_r[2]; // @[el2_lsu_stbuf.scala 154:89] - wire [7:0] _T_456 = _T_453 ? io_store_datafn_lo_r[23:16] : stbuf_data_2[23:16]; // @[el2_lsu_stbuf.scala 154:68] - wire _T_460 = _T_451 | store_byteen_hi_r[2]; // @[el2_lsu_stbuf.scala 155:31] - wire [7:0] _T_463 = _T_460 ? io_store_datafn_hi_r[23:16] : stbuf_data_2[23:16]; // @[el2_lsu_stbuf.scala 155:10] - wire [7:0] datain3_2 = sel_lo[2] ? _T_456 : _T_463; // @[el2_lsu_stbuf.scala 154:53] - wire _T_467 = ~stbuf_byteen_3[2]; // @[el2_lsu_stbuf.scala 154:69] - wire _T_469 = _T_467 | store_byteen_lo_r[2]; // @[el2_lsu_stbuf.scala 154:89] - wire [7:0] _T_472 = _T_469 ? io_store_datafn_lo_r[23:16] : stbuf_data_3[23:16]; // @[el2_lsu_stbuf.scala 154:68] - wire _T_476 = _T_467 | store_byteen_hi_r[2]; // @[el2_lsu_stbuf.scala 155:31] - wire [7:0] _T_479 = _T_476 ? io_store_datafn_hi_r[23:16] : stbuf_data_3[23:16]; // @[el2_lsu_stbuf.scala 155:10] - wire [7:0] datain3_3 = sel_lo[3] ? _T_472 : _T_479; // @[el2_lsu_stbuf.scala 154:53] - wire _T_483 = ~stbuf_byteen_0[3]; // @[el2_lsu_stbuf.scala 157:69] - wire _T_485 = _T_483 | store_byteen_lo_r[3]; // @[el2_lsu_stbuf.scala 157:89] - wire [7:0] _T_488 = _T_485 ? io_store_datafn_lo_r[31:24] : stbuf_data_0[31:24]; // @[el2_lsu_stbuf.scala 157:68] - wire _T_492 = _T_483 | store_byteen_hi_r[3]; // @[el2_lsu_stbuf.scala 158:31] - wire [7:0] _T_495 = _T_492 ? io_store_datafn_hi_r[31:24] : stbuf_data_0[31:24]; // @[el2_lsu_stbuf.scala 158:10] - wire [7:0] datain4_0 = sel_lo[0] ? _T_488 : _T_495; // @[el2_lsu_stbuf.scala 157:53] - wire _T_499 = ~stbuf_byteen_1[3]; // @[el2_lsu_stbuf.scala 157:69] - wire _T_501 = _T_499 | store_byteen_lo_r[3]; // @[el2_lsu_stbuf.scala 157:89] - wire [7:0] _T_504 = _T_501 ? io_store_datafn_lo_r[31:24] : stbuf_data_1[31:24]; // @[el2_lsu_stbuf.scala 157:68] - wire _T_508 = _T_499 | store_byteen_hi_r[3]; // @[el2_lsu_stbuf.scala 158:31] - wire [7:0] _T_511 = _T_508 ? io_store_datafn_hi_r[31:24] : stbuf_data_1[31:24]; // @[el2_lsu_stbuf.scala 158:10] - wire [7:0] datain4_1 = sel_lo[1] ? _T_504 : _T_511; // @[el2_lsu_stbuf.scala 157:53] - wire _T_515 = ~stbuf_byteen_2[3]; // @[el2_lsu_stbuf.scala 157:69] - wire _T_517 = _T_515 | store_byteen_lo_r[3]; // @[el2_lsu_stbuf.scala 157:89] - wire [7:0] _T_520 = _T_517 ? io_store_datafn_lo_r[31:24] : stbuf_data_2[31:24]; // @[el2_lsu_stbuf.scala 157:68] - wire _T_524 = _T_515 | store_byteen_hi_r[3]; // @[el2_lsu_stbuf.scala 158:31] - wire [7:0] _T_527 = _T_524 ? io_store_datafn_hi_r[31:24] : stbuf_data_2[31:24]; // @[el2_lsu_stbuf.scala 158:10] - wire [7:0] datain4_2 = sel_lo[2] ? _T_520 : _T_527; // @[el2_lsu_stbuf.scala 157:53] - wire _T_531 = ~stbuf_byteen_3[3]; // @[el2_lsu_stbuf.scala 157:69] - wire _T_533 = _T_531 | store_byteen_lo_r[3]; // @[el2_lsu_stbuf.scala 157:89] - wire [7:0] _T_536 = _T_533 ? io_store_datafn_lo_r[31:24] : stbuf_data_3[31:24]; // @[el2_lsu_stbuf.scala 157:68] - wire _T_540 = _T_531 | store_byteen_hi_r[3]; // @[el2_lsu_stbuf.scala 158:31] - wire [7:0] _T_543 = _T_540 ? io_store_datafn_hi_r[31:24] : stbuf_data_3[31:24]; // @[el2_lsu_stbuf.scala 158:10] - wire [7:0] datain4_3 = sel_lo[3] ? _T_536 : _T_543; // @[el2_lsu_stbuf.scala 157:53] + reg [3:0] stbuf_byteen_0; // @[el2_lsu_stbuf.scala 165:92] + wire [3:0] _T_274 = stbuf_byteen_0 | store_byteen_lo_r; // @[el2_lsu_stbuf.scala 145:86] + wire [3:0] _T_275 = stbuf_byteen_0 | store_byteen_hi_r; // @[el2_lsu_stbuf.scala 145:123] + wire [3:0] stbuf_byteenin_0 = sel_lo[0] ? _T_274 : _T_275; // @[el2_lsu_stbuf.scala 145:58] + reg [3:0] stbuf_byteen_1; // @[el2_lsu_stbuf.scala 165:92] + wire [3:0] _T_278 = stbuf_byteen_1 | store_byteen_lo_r; // @[el2_lsu_stbuf.scala 145:86] + wire [3:0] _T_279 = stbuf_byteen_1 | store_byteen_hi_r; // @[el2_lsu_stbuf.scala 145:123] + wire [3:0] stbuf_byteenin_1 = sel_lo[1] ? _T_278 : _T_279; // @[el2_lsu_stbuf.scala 145:58] + reg [3:0] stbuf_byteen_2; // @[el2_lsu_stbuf.scala 165:92] + wire [3:0] _T_282 = stbuf_byteen_2 | store_byteen_lo_r; // @[el2_lsu_stbuf.scala 145:86] + wire [3:0] _T_283 = stbuf_byteen_2 | store_byteen_hi_r; // @[el2_lsu_stbuf.scala 145:123] + wire [3:0] stbuf_byteenin_2 = sel_lo[2] ? _T_282 : _T_283; // @[el2_lsu_stbuf.scala 145:58] + reg [3:0] stbuf_byteen_3; // @[el2_lsu_stbuf.scala 165:92] + wire [3:0] _T_286 = stbuf_byteen_3 | store_byteen_lo_r; // @[el2_lsu_stbuf.scala 145:86] + wire [3:0] _T_287 = stbuf_byteen_3 | store_byteen_hi_r; // @[el2_lsu_stbuf.scala 145:123] + wire [3:0] stbuf_byteenin_3 = sel_lo[3] ? _T_286 : _T_287; // @[el2_lsu_stbuf.scala 145:58] + wire _T_291 = ~stbuf_byteen_0[0]; // @[el2_lsu_stbuf.scala 147:67] + wire _T_293 = _T_291 | store_byteen_lo_r[0]; // @[el2_lsu_stbuf.scala 147:87] + reg [31:0] stbuf_data_0; // @[el2_lib.scala 514:16] + wire [7:0] _T_296 = _T_293 ? io_store_datafn_lo_r[7:0] : stbuf_data_0[7:0]; // @[el2_lsu_stbuf.scala 147:66] + wire _T_300 = _T_291 | store_byteen_hi_r[0]; // @[el2_lsu_stbuf.scala 148:29] + wire [7:0] _T_303 = _T_300 ? io_store_datafn_hi_r[7:0] : stbuf_data_0[7:0]; // @[el2_lsu_stbuf.scala 148:8] + wire [7:0] datain1_0 = sel_lo[0] ? _T_296 : _T_303; // @[el2_lsu_stbuf.scala 147:51] + wire _T_307 = ~stbuf_byteen_1[0]; // @[el2_lsu_stbuf.scala 147:67] + wire _T_309 = _T_307 | store_byteen_lo_r[0]; // @[el2_lsu_stbuf.scala 147:87] + reg [31:0] stbuf_data_1; // @[el2_lib.scala 514:16] + wire [7:0] _T_312 = _T_309 ? io_store_datafn_lo_r[7:0] : stbuf_data_1[7:0]; // @[el2_lsu_stbuf.scala 147:66] + wire _T_316 = _T_307 | store_byteen_hi_r[0]; // @[el2_lsu_stbuf.scala 148:29] + wire [7:0] _T_319 = _T_316 ? io_store_datafn_hi_r[7:0] : stbuf_data_1[7:0]; // @[el2_lsu_stbuf.scala 148:8] + wire [7:0] datain1_1 = sel_lo[1] ? _T_312 : _T_319; // @[el2_lsu_stbuf.scala 147:51] + wire _T_323 = ~stbuf_byteen_2[0]; // @[el2_lsu_stbuf.scala 147:67] + wire _T_325 = _T_323 | store_byteen_lo_r[0]; // @[el2_lsu_stbuf.scala 147:87] + reg [31:0] stbuf_data_2; // @[el2_lib.scala 514:16] + wire [7:0] _T_328 = _T_325 ? io_store_datafn_lo_r[7:0] : stbuf_data_2[7:0]; // @[el2_lsu_stbuf.scala 147:66] + wire _T_332 = _T_323 | store_byteen_hi_r[0]; // @[el2_lsu_stbuf.scala 148:29] + wire [7:0] _T_335 = _T_332 ? io_store_datafn_hi_r[7:0] : stbuf_data_2[7:0]; // @[el2_lsu_stbuf.scala 148:8] + wire [7:0] datain1_2 = sel_lo[2] ? _T_328 : _T_335; // @[el2_lsu_stbuf.scala 147:51] + wire _T_339 = ~stbuf_byteen_3[0]; // @[el2_lsu_stbuf.scala 147:67] + wire _T_341 = _T_339 | store_byteen_lo_r[0]; // @[el2_lsu_stbuf.scala 147:87] + reg [31:0] stbuf_data_3; // @[el2_lib.scala 514:16] + wire [7:0] _T_344 = _T_341 ? io_store_datafn_lo_r[7:0] : stbuf_data_3[7:0]; // @[el2_lsu_stbuf.scala 147:66] + wire _T_348 = _T_339 | store_byteen_hi_r[0]; // @[el2_lsu_stbuf.scala 148:29] + wire [7:0] _T_351 = _T_348 ? io_store_datafn_hi_r[7:0] : stbuf_data_3[7:0]; // @[el2_lsu_stbuf.scala 148:8] + wire [7:0] datain1_3 = sel_lo[3] ? _T_344 : _T_351; // @[el2_lsu_stbuf.scala 147:51] + wire _T_355 = ~stbuf_byteen_0[1]; // @[el2_lsu_stbuf.scala 150:68] + wire _T_357 = _T_355 | store_byteen_lo_r[1]; // @[el2_lsu_stbuf.scala 150:88] + wire [7:0] _T_360 = _T_357 ? io_store_datafn_lo_r[15:8] : stbuf_data_0[15:8]; // @[el2_lsu_stbuf.scala 150:67] + wire _T_364 = _T_355 | store_byteen_hi_r[1]; // @[el2_lsu_stbuf.scala 151:29] + wire [7:0] _T_367 = _T_364 ? io_store_datafn_hi_r[15:8] : stbuf_data_0[15:8]; // @[el2_lsu_stbuf.scala 151:8] + wire [7:0] datain2_0 = sel_lo[0] ? _T_360 : _T_367; // @[el2_lsu_stbuf.scala 150:52] + wire _T_371 = ~stbuf_byteen_1[1]; // @[el2_lsu_stbuf.scala 150:68] + wire _T_373 = _T_371 | store_byteen_lo_r[1]; // @[el2_lsu_stbuf.scala 150:88] + wire [7:0] _T_376 = _T_373 ? io_store_datafn_lo_r[15:8] : stbuf_data_1[15:8]; // @[el2_lsu_stbuf.scala 150:67] + wire _T_380 = _T_371 | store_byteen_hi_r[1]; // @[el2_lsu_stbuf.scala 151:29] + wire [7:0] _T_383 = _T_380 ? io_store_datafn_hi_r[15:8] : stbuf_data_1[15:8]; // @[el2_lsu_stbuf.scala 151:8] + wire [7:0] datain2_1 = sel_lo[1] ? _T_376 : _T_383; // @[el2_lsu_stbuf.scala 150:52] + wire _T_387 = ~stbuf_byteen_2[1]; // @[el2_lsu_stbuf.scala 150:68] + wire _T_389 = _T_387 | store_byteen_lo_r[1]; // @[el2_lsu_stbuf.scala 150:88] + wire [7:0] _T_392 = _T_389 ? io_store_datafn_lo_r[15:8] : stbuf_data_2[15:8]; // @[el2_lsu_stbuf.scala 150:67] + wire _T_396 = _T_387 | store_byteen_hi_r[1]; // @[el2_lsu_stbuf.scala 151:29] + wire [7:0] _T_399 = _T_396 ? io_store_datafn_hi_r[15:8] : stbuf_data_2[15:8]; // @[el2_lsu_stbuf.scala 151:8] + wire [7:0] datain2_2 = sel_lo[2] ? _T_392 : _T_399; // @[el2_lsu_stbuf.scala 150:52] + wire _T_403 = ~stbuf_byteen_3[1]; // @[el2_lsu_stbuf.scala 150:68] + wire _T_405 = _T_403 | store_byteen_lo_r[1]; // @[el2_lsu_stbuf.scala 150:88] + wire [7:0] _T_408 = _T_405 ? io_store_datafn_lo_r[15:8] : stbuf_data_3[15:8]; // @[el2_lsu_stbuf.scala 150:67] + wire _T_412 = _T_403 | store_byteen_hi_r[1]; // @[el2_lsu_stbuf.scala 151:29] + wire [7:0] _T_415 = _T_412 ? io_store_datafn_hi_r[15:8] : stbuf_data_3[15:8]; // @[el2_lsu_stbuf.scala 151:8] + wire [7:0] datain2_3 = sel_lo[3] ? _T_408 : _T_415; // @[el2_lsu_stbuf.scala 150:52] + wire _T_419 = ~stbuf_byteen_0[2]; // @[el2_lsu_stbuf.scala 153:68] + wire _T_421 = _T_419 | store_byteen_lo_r[2]; // @[el2_lsu_stbuf.scala 153:88] + wire [7:0] _T_424 = _T_421 ? io_store_datafn_lo_r[23:16] : stbuf_data_0[23:16]; // @[el2_lsu_stbuf.scala 153:67] + wire _T_428 = _T_419 | store_byteen_hi_r[2]; // @[el2_lsu_stbuf.scala 154:29] + wire [7:0] _T_431 = _T_428 ? io_store_datafn_hi_r[23:16] : stbuf_data_0[23:16]; // @[el2_lsu_stbuf.scala 154:8] + wire [7:0] datain3_0 = sel_lo[0] ? _T_424 : _T_431; // @[el2_lsu_stbuf.scala 153:52] + wire _T_435 = ~stbuf_byteen_1[2]; // @[el2_lsu_stbuf.scala 153:68] + wire _T_437 = _T_435 | store_byteen_lo_r[2]; // @[el2_lsu_stbuf.scala 153:88] + wire [7:0] _T_440 = _T_437 ? io_store_datafn_lo_r[23:16] : stbuf_data_1[23:16]; // @[el2_lsu_stbuf.scala 153:67] + wire _T_444 = _T_435 | store_byteen_hi_r[2]; // @[el2_lsu_stbuf.scala 154:29] + wire [7:0] _T_447 = _T_444 ? io_store_datafn_hi_r[23:16] : stbuf_data_1[23:16]; // @[el2_lsu_stbuf.scala 154:8] + wire [7:0] datain3_1 = sel_lo[1] ? _T_440 : _T_447; // @[el2_lsu_stbuf.scala 153:52] + wire _T_451 = ~stbuf_byteen_2[2]; // @[el2_lsu_stbuf.scala 153:68] + wire _T_453 = _T_451 | store_byteen_lo_r[2]; // @[el2_lsu_stbuf.scala 153:88] + wire [7:0] _T_456 = _T_453 ? io_store_datafn_lo_r[23:16] : stbuf_data_2[23:16]; // @[el2_lsu_stbuf.scala 153:67] + wire _T_460 = _T_451 | store_byteen_hi_r[2]; // @[el2_lsu_stbuf.scala 154:29] + wire [7:0] _T_463 = _T_460 ? io_store_datafn_hi_r[23:16] : stbuf_data_2[23:16]; // @[el2_lsu_stbuf.scala 154:8] + wire [7:0] datain3_2 = sel_lo[2] ? _T_456 : _T_463; // @[el2_lsu_stbuf.scala 153:52] + wire _T_467 = ~stbuf_byteen_3[2]; // @[el2_lsu_stbuf.scala 153:68] + wire _T_469 = _T_467 | store_byteen_lo_r[2]; // @[el2_lsu_stbuf.scala 153:88] + wire [7:0] _T_472 = _T_469 ? io_store_datafn_lo_r[23:16] : stbuf_data_3[23:16]; // @[el2_lsu_stbuf.scala 153:67] + wire _T_476 = _T_467 | store_byteen_hi_r[2]; // @[el2_lsu_stbuf.scala 154:29] + wire [7:0] _T_479 = _T_476 ? io_store_datafn_hi_r[23:16] : stbuf_data_3[23:16]; // @[el2_lsu_stbuf.scala 154:8] + wire [7:0] datain3_3 = sel_lo[3] ? _T_472 : _T_479; // @[el2_lsu_stbuf.scala 153:52] + wire _T_483 = ~stbuf_byteen_0[3]; // @[el2_lsu_stbuf.scala 156:68] + wire _T_485 = _T_483 | store_byteen_lo_r[3]; // @[el2_lsu_stbuf.scala 156:88] + wire [7:0] _T_488 = _T_485 ? io_store_datafn_lo_r[31:24] : stbuf_data_0[31:24]; // @[el2_lsu_stbuf.scala 156:67] + wire _T_492 = _T_483 | store_byteen_hi_r[3]; // @[el2_lsu_stbuf.scala 157:29] + wire [7:0] _T_495 = _T_492 ? io_store_datafn_hi_r[31:24] : stbuf_data_0[31:24]; // @[el2_lsu_stbuf.scala 157:8] + wire [7:0] datain4_0 = sel_lo[0] ? _T_488 : _T_495; // @[el2_lsu_stbuf.scala 156:52] + wire _T_499 = ~stbuf_byteen_1[3]; // @[el2_lsu_stbuf.scala 156:68] + wire _T_501 = _T_499 | store_byteen_lo_r[3]; // @[el2_lsu_stbuf.scala 156:88] + wire [7:0] _T_504 = _T_501 ? io_store_datafn_lo_r[31:24] : stbuf_data_1[31:24]; // @[el2_lsu_stbuf.scala 156:67] + wire _T_508 = _T_499 | store_byteen_hi_r[3]; // @[el2_lsu_stbuf.scala 157:29] + wire [7:0] _T_511 = _T_508 ? io_store_datafn_hi_r[31:24] : stbuf_data_1[31:24]; // @[el2_lsu_stbuf.scala 157:8] + wire [7:0] datain4_1 = sel_lo[1] ? _T_504 : _T_511; // @[el2_lsu_stbuf.scala 156:52] + wire _T_515 = ~stbuf_byteen_2[3]; // @[el2_lsu_stbuf.scala 156:68] + wire _T_517 = _T_515 | store_byteen_lo_r[3]; // @[el2_lsu_stbuf.scala 156:88] + wire [7:0] _T_520 = _T_517 ? io_store_datafn_lo_r[31:24] : stbuf_data_2[31:24]; // @[el2_lsu_stbuf.scala 156:67] + wire _T_524 = _T_515 | store_byteen_hi_r[3]; // @[el2_lsu_stbuf.scala 157:29] + wire [7:0] _T_527 = _T_524 ? io_store_datafn_hi_r[31:24] : stbuf_data_2[31:24]; // @[el2_lsu_stbuf.scala 157:8] + wire [7:0] datain4_2 = sel_lo[2] ? _T_520 : _T_527; // @[el2_lsu_stbuf.scala 156:52] + wire _T_531 = ~stbuf_byteen_3[3]; // @[el2_lsu_stbuf.scala 156:68] + wire _T_533 = _T_531 | store_byteen_lo_r[3]; // @[el2_lsu_stbuf.scala 156:88] + wire [7:0] _T_536 = _T_533 ? io_store_datafn_lo_r[31:24] : stbuf_data_3[31:24]; // @[el2_lsu_stbuf.scala 156:67] + wire _T_540 = _T_531 | store_byteen_hi_r[3]; // @[el2_lsu_stbuf.scala 157:29] + wire [7:0] _T_543 = _T_540 ? io_store_datafn_hi_r[31:24] : stbuf_data_3[31:24]; // @[el2_lsu_stbuf.scala 157:8] + wire [7:0] datain4_3 = sel_lo[3] ? _T_536 : _T_543; // @[el2_lsu_stbuf.scala 156:52] wire [15:0] _T_545 = {datain2_0,datain1_0}; // @[Cat.scala 29:58] wire [15:0] _T_546 = {datain4_0,datain3_0}; // @[Cat.scala 29:58] wire [15:0] _T_548 = {datain2_1,datain1_1}; // @[Cat.scala 29:58] @@ -427,441 +427,435 @@ module el2_lsu_stbuf( wire [15:0] _T_552 = {datain4_2,datain3_2}; // @[Cat.scala 29:58] wire [15:0] _T_554 = {datain2_3,datain1_3}; // @[Cat.scala 29:58] wire [15:0] _T_555 = {datain4_3,datain3_3}; // @[Cat.scala 29:58] - wire _T_560 = stbuf_wr_en[0] | stbuf_vld[0]; // @[el2_lsu_stbuf.scala 164:92] - wire _T_568 = stbuf_wr_en[1] | stbuf_vld[1]; // @[el2_lsu_stbuf.scala 164:92] - wire _T_576 = stbuf_wr_en[2] | stbuf_vld[2]; // @[el2_lsu_stbuf.scala 164:92] - wire _T_584 = stbuf_wr_en[3] | stbuf_vld[3]; // @[el2_lsu_stbuf.scala 164:92] - wire [15:0] cmpaddr_hi_m = {{2'd0}, io_end_addr_m[15:2]}; // @[el2_lsu_stbuf.scala 206:17] - wire _T_789 = stbuf_addr_3[15:2] == cmpaddr_hi_m[13:0]; // @[el2_lsu_stbuf.scala 212:116] - wire _T_791 = _T_789 & stbuf_vld[3]; // @[el2_lsu_stbuf.scala 212:140] - wire _T_794 = _T_791 & _T_64; // @[el2_lsu_stbuf.scala 212:155] - wire _T_795 = _T_794 & io_addr_in_dccm_m; // @[el2_lsu_stbuf.scala 212:176] - wire _T_780 = stbuf_addr_2[15:2] == cmpaddr_hi_m[13:0]; // @[el2_lsu_stbuf.scala 212:116] - wire _T_782 = _T_780 & stbuf_vld[2]; // @[el2_lsu_stbuf.scala 212:140] - wire _T_785 = _T_782 & _T_53; // @[el2_lsu_stbuf.scala 212:155] - wire _T_786 = _T_785 & io_addr_in_dccm_m; // @[el2_lsu_stbuf.scala 212:176] - wire _T_771 = stbuf_addr_1[15:2] == cmpaddr_hi_m[13:0]; // @[el2_lsu_stbuf.scala 212:116] - wire _T_773 = _T_771 & stbuf_vld[1]; // @[el2_lsu_stbuf.scala 212:140] - wire _T_776 = _T_773 & _T_42; // @[el2_lsu_stbuf.scala 212:155] - wire _T_777 = _T_776 & io_addr_in_dccm_m; // @[el2_lsu_stbuf.scala 212:176] - wire _T_762 = stbuf_addr_0[15:2] == cmpaddr_hi_m[13:0]; // @[el2_lsu_stbuf.scala 212:116] - wire _T_764 = _T_762 & stbuf_vld[0]; // @[el2_lsu_stbuf.scala 212:140] - wire _T_767 = _T_764 & _T_31; // @[el2_lsu_stbuf.scala 212:155] - wire _T_768 = _T_767 & io_addr_in_dccm_m; // @[el2_lsu_stbuf.scala 212:176] + wire _T_560 = stbuf_wr_en[0] | stbuf_vld[0]; // @[el2_lsu_stbuf.scala 163:92] + wire _T_568 = stbuf_wr_en[1] | stbuf_vld[1]; // @[el2_lsu_stbuf.scala 163:92] + wire _T_576 = stbuf_wr_en[2] | stbuf_vld[2]; // @[el2_lsu_stbuf.scala 163:92] + wire _T_584 = stbuf_wr_en[3] | stbuf_vld[3]; // @[el2_lsu_stbuf.scala 163:92] + wire [15:0] cmpaddr_hi_m = {{2'd0}, io_end_addr_m[15:2]}; // @[el2_lsu_stbuf.scala 200:16] + wire _T_789 = stbuf_addr_3[15:2] == cmpaddr_hi_m[13:0]; // @[el2_lsu_stbuf.scala 206:115] + wire _T_791 = _T_789 & stbuf_vld[3]; // @[el2_lsu_stbuf.scala 206:139] + wire _T_794 = _T_791 & _T_64; // @[el2_lsu_stbuf.scala 206:154] + wire _T_795 = _T_794 & io_addr_in_dccm_m; // @[el2_lsu_stbuf.scala 206:175] + wire _T_780 = stbuf_addr_2[15:2] == cmpaddr_hi_m[13:0]; // @[el2_lsu_stbuf.scala 206:115] + wire _T_782 = _T_780 & stbuf_vld[2]; // @[el2_lsu_stbuf.scala 206:139] + wire _T_785 = _T_782 & _T_53; // @[el2_lsu_stbuf.scala 206:154] + wire _T_786 = _T_785 & io_addr_in_dccm_m; // @[el2_lsu_stbuf.scala 206:175] + wire _T_771 = stbuf_addr_1[15:2] == cmpaddr_hi_m[13:0]; // @[el2_lsu_stbuf.scala 206:115] + wire _T_773 = _T_771 & stbuf_vld[1]; // @[el2_lsu_stbuf.scala 206:139] + wire _T_776 = _T_773 & _T_42; // @[el2_lsu_stbuf.scala 206:154] + wire _T_777 = _T_776 & io_addr_in_dccm_m; // @[el2_lsu_stbuf.scala 206:175] + wire _T_762 = stbuf_addr_0[15:2] == cmpaddr_hi_m[13:0]; // @[el2_lsu_stbuf.scala 206:115] + wire _T_764 = _T_762 & stbuf_vld[0]; // @[el2_lsu_stbuf.scala 206:139] + wire _T_767 = _T_764 & _T_31; // @[el2_lsu_stbuf.scala 206:154] + wire _T_768 = _T_767 & io_addr_in_dccm_m; // @[el2_lsu_stbuf.scala 206:175] wire [3:0] stbuf_match_hi = {_T_795,_T_786,_T_777,_T_768}; // @[Cat.scala 29:58] - wire [15:0] cmpaddr_lo_m = {{2'd0}, io_lsu_addr_m[15:2]}; // @[el2_lsu_stbuf.scala 209:18] - wire _T_827 = stbuf_addr_3[15:2] == cmpaddr_lo_m[13:0]; // @[el2_lsu_stbuf.scala 213:116] - wire _T_829 = _T_827 & stbuf_vld[3]; // @[el2_lsu_stbuf.scala 213:140] - wire _T_832 = _T_829 & _T_64; // @[el2_lsu_stbuf.scala 213:155] - wire _T_833 = _T_832 & io_addr_in_dccm_m; // @[el2_lsu_stbuf.scala 213:176] - wire _T_818 = stbuf_addr_2[15:2] == cmpaddr_lo_m[13:0]; // @[el2_lsu_stbuf.scala 213:116] - wire _T_820 = _T_818 & stbuf_vld[2]; // @[el2_lsu_stbuf.scala 213:140] - wire _T_823 = _T_820 & _T_53; // @[el2_lsu_stbuf.scala 213:155] - wire _T_824 = _T_823 & io_addr_in_dccm_m; // @[el2_lsu_stbuf.scala 213:176] - wire _T_809 = stbuf_addr_1[15:2] == cmpaddr_lo_m[13:0]; // @[el2_lsu_stbuf.scala 213:116] - wire _T_811 = _T_809 & stbuf_vld[1]; // @[el2_lsu_stbuf.scala 213:140] - wire _T_814 = _T_811 & _T_42; // @[el2_lsu_stbuf.scala 213:155] - wire _T_815 = _T_814 & io_addr_in_dccm_m; // @[el2_lsu_stbuf.scala 213:176] - wire _T_800 = stbuf_addr_0[15:2] == cmpaddr_lo_m[13:0]; // @[el2_lsu_stbuf.scala 213:116] - wire _T_802 = _T_800 & stbuf_vld[0]; // @[el2_lsu_stbuf.scala 213:140] - wire _T_805 = _T_802 & _T_31; // @[el2_lsu_stbuf.scala 213:155] - wire _T_806 = _T_805 & io_addr_in_dccm_m; // @[el2_lsu_stbuf.scala 213:176] + wire [15:0] cmpaddr_lo_m = {{2'd0}, io_lsu_addr_m[15:2]}; // @[el2_lsu_stbuf.scala 203:17] + wire _T_827 = stbuf_addr_3[15:2] == cmpaddr_lo_m[13:0]; // @[el2_lsu_stbuf.scala 207:115] + wire _T_829 = _T_827 & stbuf_vld[3]; // @[el2_lsu_stbuf.scala 207:139] + wire _T_832 = _T_829 & _T_64; // @[el2_lsu_stbuf.scala 207:154] + wire _T_833 = _T_832 & io_addr_in_dccm_m; // @[el2_lsu_stbuf.scala 207:175] + wire _T_818 = stbuf_addr_2[15:2] == cmpaddr_lo_m[13:0]; // @[el2_lsu_stbuf.scala 207:115] + wire _T_820 = _T_818 & stbuf_vld[2]; // @[el2_lsu_stbuf.scala 207:139] + wire _T_823 = _T_820 & _T_53; // @[el2_lsu_stbuf.scala 207:154] + wire _T_824 = _T_823 & io_addr_in_dccm_m; // @[el2_lsu_stbuf.scala 207:175] + wire _T_809 = stbuf_addr_1[15:2] == cmpaddr_lo_m[13:0]; // @[el2_lsu_stbuf.scala 207:115] + wire _T_811 = _T_809 & stbuf_vld[1]; // @[el2_lsu_stbuf.scala 207:139] + wire _T_814 = _T_811 & _T_42; // @[el2_lsu_stbuf.scala 207:154] + wire _T_815 = _T_814 & io_addr_in_dccm_m; // @[el2_lsu_stbuf.scala 207:175] + wire _T_800 = stbuf_addr_0[15:2] == cmpaddr_lo_m[13:0]; // @[el2_lsu_stbuf.scala 207:115] + wire _T_802 = _T_800 & stbuf_vld[0]; // @[el2_lsu_stbuf.scala 207:139] + wire _T_805 = _T_802 & _T_31; // @[el2_lsu_stbuf.scala 207:154] + wire _T_806 = _T_805 & io_addr_in_dccm_m; // @[el2_lsu_stbuf.scala 207:175] wire [3:0] stbuf_match_lo = {_T_833,_T_824,_T_815,_T_806}; // @[Cat.scala 29:58] - wire _T_856 = stbuf_match_hi[3] | stbuf_match_lo[3]; // @[el2_lsu_stbuf.scala 214:79] - wire _T_857 = _T_856 & io_lsu_pkt_m_valid; // @[el2_lsu_stbuf.scala 214:100] - wire _T_858 = _T_857 & io_lsu_pkt_m_dma; // @[el2_lsu_stbuf.scala 214:121] - wire _T_859 = _T_858 & io_lsu_pkt_m_store; // @[el2_lsu_stbuf.scala 214:140] - wire _T_850 = stbuf_match_hi[2] | stbuf_match_lo[2]; // @[el2_lsu_stbuf.scala 214:79] - wire _T_851 = _T_850 & io_lsu_pkt_m_valid; // @[el2_lsu_stbuf.scala 214:100] - wire _T_852 = _T_851 & io_lsu_pkt_m_dma; // @[el2_lsu_stbuf.scala 214:121] - wire _T_853 = _T_852 & io_lsu_pkt_m_store; // @[el2_lsu_stbuf.scala 214:140] - wire _T_844 = stbuf_match_hi[1] | stbuf_match_lo[1]; // @[el2_lsu_stbuf.scala 214:79] - wire _T_845 = _T_844 & io_lsu_pkt_m_valid; // @[el2_lsu_stbuf.scala 214:100] - wire _T_846 = _T_845 & io_lsu_pkt_m_dma; // @[el2_lsu_stbuf.scala 214:121] - wire _T_847 = _T_846 & io_lsu_pkt_m_store; // @[el2_lsu_stbuf.scala 214:140] - wire _T_838 = stbuf_match_hi[0] | stbuf_match_lo[0]; // @[el2_lsu_stbuf.scala 214:79] - wire _T_839 = _T_838 & io_lsu_pkt_m_valid; // @[el2_lsu_stbuf.scala 214:100] - wire _T_840 = _T_839 & io_lsu_pkt_m_dma; // @[el2_lsu_stbuf.scala 214:121] - wire _T_841 = _T_840 & io_lsu_pkt_m_store; // @[el2_lsu_stbuf.scala 214:140] + wire _T_856 = stbuf_match_hi[3] | stbuf_match_lo[3]; // @[el2_lsu_stbuf.scala 208:78] + wire _T_857 = _T_856 & io_lsu_pkt_m_valid; // @[el2_lsu_stbuf.scala 208:99] + wire _T_858 = _T_857 & io_lsu_pkt_m_bits_dma; // @[el2_lsu_stbuf.scala 208:120] + wire _T_859 = _T_858 & io_lsu_pkt_m_bits_store; // @[el2_lsu_stbuf.scala 208:144] + wire _T_850 = stbuf_match_hi[2] | stbuf_match_lo[2]; // @[el2_lsu_stbuf.scala 208:78] + wire _T_851 = _T_850 & io_lsu_pkt_m_valid; // @[el2_lsu_stbuf.scala 208:99] + wire _T_852 = _T_851 & io_lsu_pkt_m_bits_dma; // @[el2_lsu_stbuf.scala 208:120] + wire _T_853 = _T_852 & io_lsu_pkt_m_bits_store; // @[el2_lsu_stbuf.scala 208:144] + wire _T_844 = stbuf_match_hi[1] | stbuf_match_lo[1]; // @[el2_lsu_stbuf.scala 208:78] + wire _T_845 = _T_844 & io_lsu_pkt_m_valid; // @[el2_lsu_stbuf.scala 208:99] + wire _T_846 = _T_845 & io_lsu_pkt_m_bits_dma; // @[el2_lsu_stbuf.scala 208:120] + wire _T_847 = _T_846 & io_lsu_pkt_m_bits_store; // @[el2_lsu_stbuf.scala 208:144] + wire _T_838 = stbuf_match_hi[0] | stbuf_match_lo[0]; // @[el2_lsu_stbuf.scala 208:78] + wire _T_839 = _T_838 & io_lsu_pkt_m_valid; // @[el2_lsu_stbuf.scala 208:99] + wire _T_840 = _T_839 & io_lsu_pkt_m_bits_dma; // @[el2_lsu_stbuf.scala 208:120] + wire _T_841 = _T_840 & io_lsu_pkt_m_bits_store; // @[el2_lsu_stbuf.scala 208:144] wire [3:0] stbuf_dma_kill_en = {_T_859,_T_853,_T_847,_T_841}; // @[Cat.scala 29:58] - wire _T_595 = stbuf_dma_kill_en[0] | stbuf_dma_kill[0]; // @[el2_lsu_stbuf.scala 166:66] - wire _T_603 = stbuf_dma_kill_en[1] | stbuf_dma_kill[1]; // @[el2_lsu_stbuf.scala 166:66] - wire _T_611 = stbuf_dma_kill_en[2] | stbuf_dma_kill[2]; // @[el2_lsu_stbuf.scala 166:66] - wire _T_619 = stbuf_dma_kill_en[3] | stbuf_dma_kill[3]; // @[el2_lsu_stbuf.scala 166:66] - wire [3:0] _T_629 = stbuf_wr_en[0] ? stbuf_byteenin_0 : stbuf_byteen_0; // @[el2_lsu_stbuf.scala 167:96] + wire _T_595 = stbuf_dma_kill_en[0] | stbuf_dma_kill[0]; // @[el2_lsu_stbuf.scala 164:96] + wire _T_603 = stbuf_dma_kill_en[1] | stbuf_dma_kill[1]; // @[el2_lsu_stbuf.scala 164:96] + wire _T_611 = stbuf_dma_kill_en[2] | stbuf_dma_kill[2]; // @[el2_lsu_stbuf.scala 164:96] + wire _T_619 = stbuf_dma_kill_en[3] | stbuf_dma_kill[3]; // @[el2_lsu_stbuf.scala 164:96] + wire [3:0] _T_629 = stbuf_wr_en[0] ? stbuf_byteenin_0 : stbuf_byteen_0; // @[el2_lsu_stbuf.scala 165:96] wire [3:0] _T_633 = _T_34 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] _T_638 = stbuf_wr_en[1] ? stbuf_byteenin_1 : stbuf_byteen_1; // @[el2_lsu_stbuf.scala 167:96] + wire [3:0] _T_638 = stbuf_wr_en[1] ? stbuf_byteenin_1 : stbuf_byteen_1; // @[el2_lsu_stbuf.scala 165:96] wire [3:0] _T_642 = _T_45 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] _T_647 = stbuf_wr_en[2] ? stbuf_byteenin_2 : stbuf_byteen_2; // @[el2_lsu_stbuf.scala 167:96] + wire [3:0] _T_647 = stbuf_wr_en[2] ? stbuf_byteenin_2 : stbuf_byteen_2; // @[el2_lsu_stbuf.scala 165:96] wire [3:0] _T_651 = _T_56 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] _T_656 = stbuf_wr_en[3] ? stbuf_byteenin_3 : stbuf_byteen_3; // @[el2_lsu_stbuf.scala 167:96] + wire [3:0] _T_656 = stbuf_wr_en[3] ? stbuf_byteenin_3 : stbuf_byteen_3; // @[el2_lsu_stbuf.scala 165:96] wire [3:0] _T_660 = _T_67 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - reg ldst_dual_m; // @[el2_lsu_stbuf.scala 176:53] - wire [3:0] _T_689 = stbuf_vld >> RdPtr; // @[el2_lsu_stbuf.scala 180:44] - wire [3:0] _T_691 = stbuf_dma_kill >> RdPtr; // @[el2_lsu_stbuf.scala 180:68] - wire _T_698 = ~_T_691[0]; // @[el2_lsu_stbuf.scala 181:47] - wire _T_699 = _T_689[0] & _T_698; // @[el2_lsu_stbuf.scala 181:45] - wire _T_700 = |stbuf_dma_kill_en; // @[el2_lsu_stbuf.scala 181:92] - wire _T_701 = ~_T_700; // @[el2_lsu_stbuf.scala 181:72] - wire [15:0] _GEN_1 = 2'h1 == RdPtr ? stbuf_addr_1 : stbuf_addr_0; // @[el2_lsu_stbuf.scala 182:23] - wire [15:0] _GEN_2 = 2'h2 == RdPtr ? stbuf_addr_2 : _GEN_1; // @[el2_lsu_stbuf.scala 182:23] - wire [31:0] _GEN_5 = 2'h1 == RdPtr ? stbuf_data_1 : stbuf_data_0; // @[el2_lsu_stbuf.scala 183:23] - wire [31:0] _GEN_6 = 2'h2 == RdPtr ? stbuf_data_2 : _GEN_5; // @[el2_lsu_stbuf.scala 183:23] - wire _T_703 = ~dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 185:44] - wire _T_704 = io_ldst_stbuf_reqvld_r & _T_703; // @[el2_lsu_stbuf.scala 185:42] - wire _T_705 = store_coalesce_hi_r | store_coalesce_lo_r; // @[el2_lsu_stbuf.scala 185:88] - wire _T_706 = ~_T_705; // @[el2_lsu_stbuf.scala 185:66] - wire _T_707 = _T_704 & _T_706; // @[el2_lsu_stbuf.scala 185:64] - wire _T_708 = io_ldst_stbuf_reqvld_r & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 186:31] - wire _T_709 = store_coalesce_hi_r & store_coalesce_lo_r; // @[el2_lsu_stbuf.scala 186:77] - wire _T_710 = ~_T_709; // @[el2_lsu_stbuf.scala 186:55] - wire _T_711 = _T_708 & _T_710; // @[el2_lsu_stbuf.scala 186:53] - wire WrPtrEn = _T_707 | _T_711; // @[el2_lsu_stbuf.scala 185:113] - wire _T_716 = _T_708 & _T_706; // @[el2_lsu_stbuf.scala 187:68] + reg ldst_dual_m; // @[el2_lsu_stbuf.scala 170:52] + wire [3:0] _T_689 = stbuf_vld >> RdPtr; // @[el2_lsu_stbuf.scala 174:43] + wire [3:0] _T_691 = stbuf_dma_kill >> RdPtr; // @[el2_lsu_stbuf.scala 174:67] + wire _T_698 = ~_T_691[0]; // @[el2_lsu_stbuf.scala 175:46] + wire _T_699 = _T_689[0] & _T_698; // @[el2_lsu_stbuf.scala 175:44] + wire _T_700 = |stbuf_dma_kill_en; // @[el2_lsu_stbuf.scala 175:91] + wire _T_701 = ~_T_700; // @[el2_lsu_stbuf.scala 175:71] + wire [15:0] _GEN_1 = 2'h1 == RdPtr ? stbuf_addr_1 : stbuf_addr_0; // @[el2_lsu_stbuf.scala 176:22] + wire [15:0] _GEN_2 = 2'h2 == RdPtr ? stbuf_addr_2 : _GEN_1; // @[el2_lsu_stbuf.scala 176:22] + wire [31:0] _GEN_5 = 2'h1 == RdPtr ? stbuf_data_1 : stbuf_data_0; // @[el2_lsu_stbuf.scala 177:22] + wire [31:0] _GEN_6 = 2'h2 == RdPtr ? stbuf_data_2 : _GEN_5; // @[el2_lsu_stbuf.scala 177:22] + wire _T_703 = ~dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 179:44] + wire _T_704 = io_ldst_stbuf_reqvld_r & _T_703; // @[el2_lsu_stbuf.scala 179:42] + wire _T_705 = store_coalesce_hi_r | store_coalesce_lo_r; // @[el2_lsu_stbuf.scala 179:88] + wire _T_706 = ~_T_705; // @[el2_lsu_stbuf.scala 179:66] + wire _T_707 = _T_704 & _T_706; // @[el2_lsu_stbuf.scala 179:64] + wire _T_708 = io_ldst_stbuf_reqvld_r & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 180:30] + wire _T_709 = store_coalesce_hi_r & store_coalesce_lo_r; // @[el2_lsu_stbuf.scala 180:76] + wire _T_710 = ~_T_709; // @[el2_lsu_stbuf.scala 180:54] + wire _T_711 = _T_708 & _T_710; // @[el2_lsu_stbuf.scala 180:52] + wire WrPtrEn = _T_707 | _T_711; // @[el2_lsu_stbuf.scala 179:113] + wire _T_716 = _T_708 & _T_706; // @[el2_lsu_stbuf.scala 181:67] wire [3:0] _T_721 = {3'h0,stbuf_vld[0]}; // @[Cat.scala 29:58] wire [3:0] _T_723 = {3'h0,stbuf_vld[1]}; // @[Cat.scala 29:58] wire [3:0] _T_725 = {3'h0,stbuf_vld[2]}; // @[Cat.scala 29:58] wire [3:0] _T_727 = {3'h0,stbuf_vld[3]}; // @[Cat.scala 29:58] - wire [3:0] _T_730 = _T_721 + _T_723; // @[el2_lsu_stbuf.scala 194:102] - wire [3:0] _T_732 = _T_730 + _T_725; // @[el2_lsu_stbuf.scala 194:102] - wire [3:0] stbuf_numvld_any = _T_732 + _T_727; // @[el2_lsu_stbuf.scala 194:102] - wire _T_734 = io_lsu_pkt_m_valid & io_lsu_pkt_m_store; // @[el2_lsu_stbuf.scala 195:40] - wire _T_735 = _T_734 & io_addr_in_dccm_m; // @[el2_lsu_stbuf.scala 195:61] - wire _T_736 = ~io_lsu_pkt_m_dma; // @[el2_lsu_stbuf.scala 195:83] - wire isdccmst_m = _T_735 & _T_736; // @[el2_lsu_stbuf.scala 195:81] - wire _T_737 = io_lsu_pkt_r_valid & io_lsu_pkt_r_store; // @[el2_lsu_stbuf.scala 196:40] - wire _T_738 = _T_737 & io_addr_in_dccm_r; // @[el2_lsu_stbuf.scala 196:61] - wire _T_739 = ~io_lsu_pkt_r_dma; // @[el2_lsu_stbuf.scala 196:83] - wire isdccmst_r = _T_738 & _T_739; // @[el2_lsu_stbuf.scala 196:81] + wire [3:0] _T_730 = _T_721 + _T_723; // @[el2_lsu_stbuf.scala 188:101] + wire [3:0] _T_732 = _T_730 + _T_725; // @[el2_lsu_stbuf.scala 188:101] + wire [3:0] stbuf_numvld_any = _T_732 + _T_727; // @[el2_lsu_stbuf.scala 188:101] + wire _T_734 = io_lsu_pkt_m_valid & io_lsu_pkt_m_bits_store; // @[el2_lsu_stbuf.scala 189:39] + wire _T_735 = _T_734 & io_addr_in_dccm_m; // @[el2_lsu_stbuf.scala 189:65] + wire _T_736 = ~io_lsu_pkt_m_bits_dma; // @[el2_lsu_stbuf.scala 189:87] + wire isdccmst_m = _T_735 & _T_736; // @[el2_lsu_stbuf.scala 189:85] + wire _T_737 = io_lsu_pkt_r_valid & io_lsu_pkt_r_bits_store; // @[el2_lsu_stbuf.scala 190:39] + wire _T_738 = _T_737 & io_addr_in_dccm_r; // @[el2_lsu_stbuf.scala 190:65] + wire _T_739 = ~io_lsu_pkt_r_bits_dma; // @[el2_lsu_stbuf.scala 190:87] + wire isdccmst_r = _T_738 & _T_739; // @[el2_lsu_stbuf.scala 190:85] wire [1:0] _T_740 = {1'h0,isdccmst_m}; // @[Cat.scala 29:58] - wire _T_741 = isdccmst_m & ldst_dual_m; // @[el2_lsu_stbuf.scala 198:63] - wire [2:0] _GEN_14 = {{1'd0}, _T_740}; // @[el2_lsu_stbuf.scala 198:48] - wire [2:0] _T_742 = _GEN_14 << _T_741; // @[el2_lsu_stbuf.scala 198:48] + wire _T_741 = isdccmst_m & ldst_dual_m; // @[el2_lsu_stbuf.scala 192:62] + wire [2:0] _GEN_14 = {{1'd0}, _T_740}; // @[el2_lsu_stbuf.scala 192:47] + wire [2:0] _T_742 = _GEN_14 << _T_741; // @[el2_lsu_stbuf.scala 192:47] wire [1:0] _T_743 = {1'h0,isdccmst_r}; // @[Cat.scala 29:58] - wire _T_744 = isdccmst_r & ldst_dual_r; // @[el2_lsu_stbuf.scala 199:63] - wire [2:0] _GEN_15 = {{1'd0}, _T_743}; // @[el2_lsu_stbuf.scala 199:48] - wire [2:0] _T_745 = _GEN_15 << _T_744; // @[el2_lsu_stbuf.scala 199:48] - wire [1:0] stbuf_specvld_m = _T_742[1:0]; // @[el2_lsu_stbuf.scala 198:20] + wire _T_744 = isdccmst_r & ldst_dual_r; // @[el2_lsu_stbuf.scala 193:62] + wire [2:0] _GEN_15 = {{1'd0}, _T_743}; // @[el2_lsu_stbuf.scala 193:47] + wire [2:0] _T_745 = _GEN_15 << _T_744; // @[el2_lsu_stbuf.scala 193:47] + wire [1:0] stbuf_specvld_m = _T_742[1:0]; // @[el2_lsu_stbuf.scala 192:19] wire [3:0] _T_746 = {2'h0,stbuf_specvld_m}; // @[Cat.scala 29:58] - wire [3:0] _T_748 = stbuf_numvld_any + _T_746; // @[el2_lsu_stbuf.scala 200:45] - wire [1:0] stbuf_specvld_r = _T_745[1:0]; // @[el2_lsu_stbuf.scala 199:20] + wire [3:0] _T_748 = stbuf_numvld_any + _T_746; // @[el2_lsu_stbuf.scala 194:44] + wire [1:0] stbuf_specvld_r = _T_745[1:0]; // @[el2_lsu_stbuf.scala 193:19] wire [3:0] _T_749 = {2'h0,stbuf_specvld_r}; // @[Cat.scala 29:58] - wire [3:0] stbuf_specvld_any = _T_748 + _T_749; // @[el2_lsu_stbuf.scala 200:79] - wire _T_751 = ~ldst_dual_d; // @[el2_lsu_stbuf.scala 202:35] - wire _T_752 = _T_751 & io_dec_lsu_valid_raw_d; // @[el2_lsu_stbuf.scala 202:48] - wire _T_754 = stbuf_specvld_any >= 4'h4; // @[el2_lsu_stbuf.scala 202:100] - wire _T_755 = stbuf_specvld_any >= 4'h3; // @[el2_lsu_stbuf.scala 202:141] - wire _T_865 = stbuf_match_hi[0] & stbuf_byteen_0[0]; // @[el2_lsu_stbuf.scala 217:117] - wire stbuf_fwdbyteenvec_hi_0_0 = _T_865 & stbuf_vld[0]; // @[el2_lsu_stbuf.scala 217:138] - wire _T_869 = stbuf_match_hi[0] & stbuf_byteen_0[1]; // @[el2_lsu_stbuf.scala 217:117] - wire stbuf_fwdbyteenvec_hi_0_1 = _T_869 & stbuf_vld[0]; // @[el2_lsu_stbuf.scala 217:138] - wire _T_873 = stbuf_match_hi[0] & stbuf_byteen_0[2]; // @[el2_lsu_stbuf.scala 217:117] - wire stbuf_fwdbyteenvec_hi_0_2 = _T_873 & stbuf_vld[0]; // @[el2_lsu_stbuf.scala 217:138] - wire _T_877 = stbuf_match_hi[0] & stbuf_byteen_0[3]; // @[el2_lsu_stbuf.scala 217:117] - wire stbuf_fwdbyteenvec_hi_0_3 = _T_877 & stbuf_vld[0]; // @[el2_lsu_stbuf.scala 217:138] - wire _T_881 = stbuf_match_hi[1] & stbuf_byteen_1[0]; // @[el2_lsu_stbuf.scala 217:117] - wire stbuf_fwdbyteenvec_hi_1_0 = _T_881 & stbuf_vld[1]; // @[el2_lsu_stbuf.scala 217:138] - wire _T_885 = stbuf_match_hi[1] & stbuf_byteen_1[1]; // @[el2_lsu_stbuf.scala 217:117] - wire stbuf_fwdbyteenvec_hi_1_1 = _T_885 & stbuf_vld[1]; // @[el2_lsu_stbuf.scala 217:138] - wire _T_889 = stbuf_match_hi[1] & stbuf_byteen_1[2]; // @[el2_lsu_stbuf.scala 217:117] - wire stbuf_fwdbyteenvec_hi_1_2 = _T_889 & stbuf_vld[1]; // @[el2_lsu_stbuf.scala 217:138] - wire _T_893 = stbuf_match_hi[1] & stbuf_byteen_1[3]; // @[el2_lsu_stbuf.scala 217:117] - wire stbuf_fwdbyteenvec_hi_1_3 = _T_893 & stbuf_vld[1]; // @[el2_lsu_stbuf.scala 217:138] - wire _T_897 = stbuf_match_hi[2] & stbuf_byteen_2[0]; // @[el2_lsu_stbuf.scala 217:117] - wire stbuf_fwdbyteenvec_hi_2_0 = _T_897 & stbuf_vld[2]; // @[el2_lsu_stbuf.scala 217:138] - wire _T_901 = stbuf_match_hi[2] & stbuf_byteen_2[1]; // @[el2_lsu_stbuf.scala 217:117] - wire stbuf_fwdbyteenvec_hi_2_1 = _T_901 & stbuf_vld[2]; // @[el2_lsu_stbuf.scala 217:138] - wire _T_905 = stbuf_match_hi[2] & stbuf_byteen_2[2]; // @[el2_lsu_stbuf.scala 217:117] - wire stbuf_fwdbyteenvec_hi_2_2 = _T_905 & stbuf_vld[2]; // @[el2_lsu_stbuf.scala 217:138] - wire _T_909 = stbuf_match_hi[2] & stbuf_byteen_2[3]; // @[el2_lsu_stbuf.scala 217:117] - wire stbuf_fwdbyteenvec_hi_2_3 = _T_909 & stbuf_vld[2]; // @[el2_lsu_stbuf.scala 217:138] - wire _T_913 = stbuf_match_hi[3] & stbuf_byteen_3[0]; // @[el2_lsu_stbuf.scala 217:117] - wire stbuf_fwdbyteenvec_hi_3_0 = _T_913 & stbuf_vld[3]; // @[el2_lsu_stbuf.scala 217:138] - wire _T_917 = stbuf_match_hi[3] & stbuf_byteen_3[1]; // @[el2_lsu_stbuf.scala 217:117] - wire stbuf_fwdbyteenvec_hi_3_1 = _T_917 & stbuf_vld[3]; // @[el2_lsu_stbuf.scala 217:138] - wire _T_921 = stbuf_match_hi[3] & stbuf_byteen_3[2]; // @[el2_lsu_stbuf.scala 217:117] - wire stbuf_fwdbyteenvec_hi_3_2 = _T_921 & stbuf_vld[3]; // @[el2_lsu_stbuf.scala 217:138] - wire _T_925 = stbuf_match_hi[3] & stbuf_byteen_3[3]; // @[el2_lsu_stbuf.scala 217:117] - wire stbuf_fwdbyteenvec_hi_3_3 = _T_925 & stbuf_vld[3]; // @[el2_lsu_stbuf.scala 217:138] - wire _T_929 = stbuf_match_lo[0] & stbuf_byteen_0[0]; // @[el2_lsu_stbuf.scala 218:117] - wire stbuf_fwdbyteenvec_lo_0_0 = _T_929 & stbuf_vld[0]; // @[el2_lsu_stbuf.scala 218:138] - wire _T_933 = stbuf_match_lo[0] & stbuf_byteen_0[1]; // @[el2_lsu_stbuf.scala 218:117] - wire stbuf_fwdbyteenvec_lo_0_1 = _T_933 & stbuf_vld[0]; // @[el2_lsu_stbuf.scala 218:138] - wire _T_937 = stbuf_match_lo[0] & stbuf_byteen_0[2]; // @[el2_lsu_stbuf.scala 218:117] - wire stbuf_fwdbyteenvec_lo_0_2 = _T_937 & stbuf_vld[0]; // @[el2_lsu_stbuf.scala 218:138] - wire _T_941 = stbuf_match_lo[0] & stbuf_byteen_0[3]; // @[el2_lsu_stbuf.scala 218:117] - wire stbuf_fwdbyteenvec_lo_0_3 = _T_941 & stbuf_vld[0]; // @[el2_lsu_stbuf.scala 218:138] - wire _T_945 = stbuf_match_lo[1] & stbuf_byteen_1[0]; // @[el2_lsu_stbuf.scala 218:117] - wire stbuf_fwdbyteenvec_lo_1_0 = _T_945 & stbuf_vld[1]; // @[el2_lsu_stbuf.scala 218:138] - wire _T_949 = stbuf_match_lo[1] & stbuf_byteen_1[1]; // @[el2_lsu_stbuf.scala 218:117] - wire stbuf_fwdbyteenvec_lo_1_1 = _T_949 & stbuf_vld[1]; // @[el2_lsu_stbuf.scala 218:138] - wire _T_953 = stbuf_match_lo[1] & stbuf_byteen_1[2]; // @[el2_lsu_stbuf.scala 218:117] - wire stbuf_fwdbyteenvec_lo_1_2 = _T_953 & stbuf_vld[1]; // @[el2_lsu_stbuf.scala 218:138] - wire _T_957 = stbuf_match_lo[1] & stbuf_byteen_1[3]; // @[el2_lsu_stbuf.scala 218:117] - wire stbuf_fwdbyteenvec_lo_1_3 = _T_957 & stbuf_vld[1]; // @[el2_lsu_stbuf.scala 218:138] - wire _T_961 = stbuf_match_lo[2] & stbuf_byteen_2[0]; // @[el2_lsu_stbuf.scala 218:117] - wire stbuf_fwdbyteenvec_lo_2_0 = _T_961 & stbuf_vld[2]; // @[el2_lsu_stbuf.scala 218:138] - wire _T_965 = stbuf_match_lo[2] & stbuf_byteen_2[1]; // @[el2_lsu_stbuf.scala 218:117] - wire stbuf_fwdbyteenvec_lo_2_1 = _T_965 & stbuf_vld[2]; // @[el2_lsu_stbuf.scala 218:138] - wire _T_969 = stbuf_match_lo[2] & stbuf_byteen_2[2]; // @[el2_lsu_stbuf.scala 218:117] - wire stbuf_fwdbyteenvec_lo_2_2 = _T_969 & stbuf_vld[2]; // @[el2_lsu_stbuf.scala 218:138] - wire _T_973 = stbuf_match_lo[2] & stbuf_byteen_2[3]; // @[el2_lsu_stbuf.scala 218:117] - wire stbuf_fwdbyteenvec_lo_2_3 = _T_973 & stbuf_vld[2]; // @[el2_lsu_stbuf.scala 218:138] - wire _T_977 = stbuf_match_lo[3] & stbuf_byteen_3[0]; // @[el2_lsu_stbuf.scala 218:117] - wire stbuf_fwdbyteenvec_lo_3_0 = _T_977 & stbuf_vld[3]; // @[el2_lsu_stbuf.scala 218:138] - wire _T_981 = stbuf_match_lo[3] & stbuf_byteen_3[1]; // @[el2_lsu_stbuf.scala 218:117] - wire stbuf_fwdbyteenvec_lo_3_1 = _T_981 & stbuf_vld[3]; // @[el2_lsu_stbuf.scala 218:138] - wire _T_985 = stbuf_match_lo[3] & stbuf_byteen_3[2]; // @[el2_lsu_stbuf.scala 218:117] - wire stbuf_fwdbyteenvec_lo_3_2 = _T_985 & stbuf_vld[3]; // @[el2_lsu_stbuf.scala 218:138] - wire _T_989 = stbuf_match_lo[3] & stbuf_byteen_3[3]; // @[el2_lsu_stbuf.scala 218:117] - wire stbuf_fwdbyteenvec_lo_3_3 = _T_989 & stbuf_vld[3]; // @[el2_lsu_stbuf.scala 218:138] - wire _T_991 = stbuf_fwdbyteenvec_hi_0_0 | stbuf_fwdbyteenvec_hi_1_0; // @[el2_lsu_stbuf.scala 219:148] - wire _T_992 = _T_991 | stbuf_fwdbyteenvec_hi_2_0; // @[el2_lsu_stbuf.scala 219:148] - wire stbuf_fwdbyteen_hi_pre_m_0 = _T_992 | stbuf_fwdbyteenvec_hi_3_0; // @[el2_lsu_stbuf.scala 219:148] - wire _T_993 = stbuf_fwdbyteenvec_hi_0_1 | stbuf_fwdbyteenvec_hi_1_1; // @[el2_lsu_stbuf.scala 219:148] - wire _T_994 = _T_993 | stbuf_fwdbyteenvec_hi_2_1; // @[el2_lsu_stbuf.scala 219:148] - wire stbuf_fwdbyteen_hi_pre_m_1 = _T_994 | stbuf_fwdbyteenvec_hi_3_1; // @[el2_lsu_stbuf.scala 219:148] - wire _T_995 = stbuf_fwdbyteenvec_hi_0_2 | stbuf_fwdbyteenvec_hi_1_2; // @[el2_lsu_stbuf.scala 219:148] - wire _T_996 = _T_995 | stbuf_fwdbyteenvec_hi_2_2; // @[el2_lsu_stbuf.scala 219:148] - wire stbuf_fwdbyteen_hi_pre_m_2 = _T_996 | stbuf_fwdbyteenvec_hi_3_2; // @[el2_lsu_stbuf.scala 219:148] - wire _T_997 = stbuf_fwdbyteenvec_hi_0_3 | stbuf_fwdbyteenvec_hi_1_3; // @[el2_lsu_stbuf.scala 219:148] - wire _T_998 = _T_997 | stbuf_fwdbyteenvec_hi_2_3; // @[el2_lsu_stbuf.scala 219:148] - wire stbuf_fwdbyteen_hi_pre_m_3 = _T_998 | stbuf_fwdbyteenvec_hi_3_3; // @[el2_lsu_stbuf.scala 219:148] - wire _T_999 = stbuf_fwdbyteenvec_lo_0_0 | stbuf_fwdbyteenvec_lo_1_0; // @[el2_lsu_stbuf.scala 220:148] - wire _T_1000 = _T_999 | stbuf_fwdbyteenvec_lo_2_0; // @[el2_lsu_stbuf.scala 220:148] - wire stbuf_fwdbyteen_lo_pre_m_0 = _T_1000 | stbuf_fwdbyteenvec_lo_3_0; // @[el2_lsu_stbuf.scala 220:148] - wire _T_1001 = stbuf_fwdbyteenvec_lo_0_1 | stbuf_fwdbyteenvec_lo_1_1; // @[el2_lsu_stbuf.scala 220:148] - wire _T_1002 = _T_1001 | stbuf_fwdbyteenvec_lo_2_1; // @[el2_lsu_stbuf.scala 220:148] - wire stbuf_fwdbyteen_lo_pre_m_1 = _T_1002 | stbuf_fwdbyteenvec_lo_3_1; // @[el2_lsu_stbuf.scala 220:148] - wire _T_1003 = stbuf_fwdbyteenvec_lo_0_2 | stbuf_fwdbyteenvec_lo_1_2; // @[el2_lsu_stbuf.scala 220:148] - wire _T_1004 = _T_1003 | stbuf_fwdbyteenvec_lo_2_2; // @[el2_lsu_stbuf.scala 220:148] - wire stbuf_fwdbyteen_lo_pre_m_2 = _T_1004 | stbuf_fwdbyteenvec_lo_3_2; // @[el2_lsu_stbuf.scala 220:148] - wire _T_1005 = stbuf_fwdbyteenvec_lo_0_3 | stbuf_fwdbyteenvec_lo_1_3; // @[el2_lsu_stbuf.scala 220:148] - wire _T_1006 = _T_1005 | stbuf_fwdbyteenvec_lo_2_3; // @[el2_lsu_stbuf.scala 220:148] - wire stbuf_fwdbyteen_lo_pre_m_3 = _T_1006 | stbuf_fwdbyteenvec_lo_3_3; // @[el2_lsu_stbuf.scala 220:148] + wire [3:0] stbuf_specvld_any = _T_748 + _T_749; // @[el2_lsu_stbuf.scala 194:78] + wire _T_751 = ~ldst_dual_d; // @[el2_lsu_stbuf.scala 196:34] + wire _T_752 = _T_751 & io_dec_lsu_valid_raw_d; // @[el2_lsu_stbuf.scala 196:47] + wire _T_754 = stbuf_specvld_any >= 4'h4; // @[el2_lsu_stbuf.scala 196:99] + wire _T_755 = stbuf_specvld_any >= 4'h3; // @[el2_lsu_stbuf.scala 196:140] + wire _T_865 = stbuf_match_hi[0] & stbuf_byteen_0[0]; // @[el2_lsu_stbuf.scala 211:116] + wire stbuf_fwdbyteenvec_hi_0_0 = _T_865 & stbuf_vld[0]; // @[el2_lsu_stbuf.scala 211:137] + wire _T_869 = stbuf_match_hi[0] & stbuf_byteen_0[1]; // @[el2_lsu_stbuf.scala 211:116] + wire stbuf_fwdbyteenvec_hi_0_1 = _T_869 & stbuf_vld[0]; // @[el2_lsu_stbuf.scala 211:137] + wire _T_873 = stbuf_match_hi[0] & stbuf_byteen_0[2]; // @[el2_lsu_stbuf.scala 211:116] + wire stbuf_fwdbyteenvec_hi_0_2 = _T_873 & stbuf_vld[0]; // @[el2_lsu_stbuf.scala 211:137] + wire _T_877 = stbuf_match_hi[0] & stbuf_byteen_0[3]; // @[el2_lsu_stbuf.scala 211:116] + wire stbuf_fwdbyteenvec_hi_0_3 = _T_877 & stbuf_vld[0]; // @[el2_lsu_stbuf.scala 211:137] + wire _T_881 = stbuf_match_hi[1] & stbuf_byteen_1[0]; // @[el2_lsu_stbuf.scala 211:116] + wire stbuf_fwdbyteenvec_hi_1_0 = _T_881 & stbuf_vld[1]; // @[el2_lsu_stbuf.scala 211:137] + wire _T_885 = stbuf_match_hi[1] & stbuf_byteen_1[1]; // @[el2_lsu_stbuf.scala 211:116] + wire stbuf_fwdbyteenvec_hi_1_1 = _T_885 & stbuf_vld[1]; // @[el2_lsu_stbuf.scala 211:137] + wire _T_889 = stbuf_match_hi[1] & stbuf_byteen_1[2]; // @[el2_lsu_stbuf.scala 211:116] + wire stbuf_fwdbyteenvec_hi_1_2 = _T_889 & stbuf_vld[1]; // @[el2_lsu_stbuf.scala 211:137] + wire _T_893 = stbuf_match_hi[1] & stbuf_byteen_1[3]; // @[el2_lsu_stbuf.scala 211:116] + wire stbuf_fwdbyteenvec_hi_1_3 = _T_893 & stbuf_vld[1]; // @[el2_lsu_stbuf.scala 211:137] + wire _T_897 = stbuf_match_hi[2] & stbuf_byteen_2[0]; // @[el2_lsu_stbuf.scala 211:116] + wire stbuf_fwdbyteenvec_hi_2_0 = _T_897 & stbuf_vld[2]; // @[el2_lsu_stbuf.scala 211:137] + wire _T_901 = stbuf_match_hi[2] & stbuf_byteen_2[1]; // @[el2_lsu_stbuf.scala 211:116] + wire stbuf_fwdbyteenvec_hi_2_1 = _T_901 & stbuf_vld[2]; // @[el2_lsu_stbuf.scala 211:137] + wire _T_905 = stbuf_match_hi[2] & stbuf_byteen_2[2]; // @[el2_lsu_stbuf.scala 211:116] + wire stbuf_fwdbyteenvec_hi_2_2 = _T_905 & stbuf_vld[2]; // @[el2_lsu_stbuf.scala 211:137] + wire _T_909 = stbuf_match_hi[2] & stbuf_byteen_2[3]; // @[el2_lsu_stbuf.scala 211:116] + wire stbuf_fwdbyteenvec_hi_2_3 = _T_909 & stbuf_vld[2]; // @[el2_lsu_stbuf.scala 211:137] + wire _T_913 = stbuf_match_hi[3] & stbuf_byteen_3[0]; // @[el2_lsu_stbuf.scala 211:116] + wire stbuf_fwdbyteenvec_hi_3_0 = _T_913 & stbuf_vld[3]; // @[el2_lsu_stbuf.scala 211:137] + wire _T_917 = stbuf_match_hi[3] & stbuf_byteen_3[1]; // @[el2_lsu_stbuf.scala 211:116] + wire stbuf_fwdbyteenvec_hi_3_1 = _T_917 & stbuf_vld[3]; // @[el2_lsu_stbuf.scala 211:137] + wire _T_921 = stbuf_match_hi[3] & stbuf_byteen_3[2]; // @[el2_lsu_stbuf.scala 211:116] + wire stbuf_fwdbyteenvec_hi_3_2 = _T_921 & stbuf_vld[3]; // @[el2_lsu_stbuf.scala 211:137] + wire _T_925 = stbuf_match_hi[3] & stbuf_byteen_3[3]; // @[el2_lsu_stbuf.scala 211:116] + wire stbuf_fwdbyteenvec_hi_3_3 = _T_925 & stbuf_vld[3]; // @[el2_lsu_stbuf.scala 211:137] + wire _T_929 = stbuf_match_lo[0] & stbuf_byteen_0[0]; // @[el2_lsu_stbuf.scala 212:116] + wire stbuf_fwdbyteenvec_lo_0_0 = _T_929 & stbuf_vld[0]; // @[el2_lsu_stbuf.scala 212:137] + wire _T_933 = stbuf_match_lo[0] & stbuf_byteen_0[1]; // @[el2_lsu_stbuf.scala 212:116] + wire stbuf_fwdbyteenvec_lo_0_1 = _T_933 & stbuf_vld[0]; // @[el2_lsu_stbuf.scala 212:137] + wire _T_937 = stbuf_match_lo[0] & stbuf_byteen_0[2]; // @[el2_lsu_stbuf.scala 212:116] + wire stbuf_fwdbyteenvec_lo_0_2 = _T_937 & stbuf_vld[0]; // @[el2_lsu_stbuf.scala 212:137] + wire _T_941 = stbuf_match_lo[0] & stbuf_byteen_0[3]; // @[el2_lsu_stbuf.scala 212:116] + wire stbuf_fwdbyteenvec_lo_0_3 = _T_941 & stbuf_vld[0]; // @[el2_lsu_stbuf.scala 212:137] + wire _T_945 = stbuf_match_lo[1] & stbuf_byteen_1[0]; // @[el2_lsu_stbuf.scala 212:116] + wire stbuf_fwdbyteenvec_lo_1_0 = _T_945 & stbuf_vld[1]; // @[el2_lsu_stbuf.scala 212:137] + wire _T_949 = stbuf_match_lo[1] & stbuf_byteen_1[1]; // @[el2_lsu_stbuf.scala 212:116] + wire stbuf_fwdbyteenvec_lo_1_1 = _T_949 & stbuf_vld[1]; // @[el2_lsu_stbuf.scala 212:137] + wire _T_953 = stbuf_match_lo[1] & stbuf_byteen_1[2]; // @[el2_lsu_stbuf.scala 212:116] + wire stbuf_fwdbyteenvec_lo_1_2 = _T_953 & stbuf_vld[1]; // @[el2_lsu_stbuf.scala 212:137] + wire _T_957 = stbuf_match_lo[1] & stbuf_byteen_1[3]; // @[el2_lsu_stbuf.scala 212:116] + wire stbuf_fwdbyteenvec_lo_1_3 = _T_957 & stbuf_vld[1]; // @[el2_lsu_stbuf.scala 212:137] + wire _T_961 = stbuf_match_lo[2] & stbuf_byteen_2[0]; // @[el2_lsu_stbuf.scala 212:116] + wire stbuf_fwdbyteenvec_lo_2_0 = _T_961 & stbuf_vld[2]; // @[el2_lsu_stbuf.scala 212:137] + wire _T_965 = stbuf_match_lo[2] & stbuf_byteen_2[1]; // @[el2_lsu_stbuf.scala 212:116] + wire stbuf_fwdbyteenvec_lo_2_1 = _T_965 & stbuf_vld[2]; // @[el2_lsu_stbuf.scala 212:137] + wire _T_969 = stbuf_match_lo[2] & stbuf_byteen_2[2]; // @[el2_lsu_stbuf.scala 212:116] + wire stbuf_fwdbyteenvec_lo_2_2 = _T_969 & stbuf_vld[2]; // @[el2_lsu_stbuf.scala 212:137] + wire _T_973 = stbuf_match_lo[2] & stbuf_byteen_2[3]; // @[el2_lsu_stbuf.scala 212:116] + wire stbuf_fwdbyteenvec_lo_2_3 = _T_973 & stbuf_vld[2]; // @[el2_lsu_stbuf.scala 212:137] + wire _T_977 = stbuf_match_lo[3] & stbuf_byteen_3[0]; // @[el2_lsu_stbuf.scala 212:116] + wire stbuf_fwdbyteenvec_lo_3_0 = _T_977 & stbuf_vld[3]; // @[el2_lsu_stbuf.scala 212:137] + wire _T_981 = stbuf_match_lo[3] & stbuf_byteen_3[1]; // @[el2_lsu_stbuf.scala 212:116] + wire stbuf_fwdbyteenvec_lo_3_1 = _T_981 & stbuf_vld[3]; // @[el2_lsu_stbuf.scala 212:137] + wire _T_985 = stbuf_match_lo[3] & stbuf_byteen_3[2]; // @[el2_lsu_stbuf.scala 212:116] + wire stbuf_fwdbyteenvec_lo_3_2 = _T_985 & stbuf_vld[3]; // @[el2_lsu_stbuf.scala 212:137] + wire _T_989 = stbuf_match_lo[3] & stbuf_byteen_3[3]; // @[el2_lsu_stbuf.scala 212:116] + wire stbuf_fwdbyteenvec_lo_3_3 = _T_989 & stbuf_vld[3]; // @[el2_lsu_stbuf.scala 212:137] + wire _T_991 = stbuf_fwdbyteenvec_hi_0_0 | stbuf_fwdbyteenvec_hi_1_0; // @[el2_lsu_stbuf.scala 213:147] + wire _T_992 = _T_991 | stbuf_fwdbyteenvec_hi_2_0; // @[el2_lsu_stbuf.scala 213:147] + wire stbuf_fwdbyteen_hi_pre_m_0 = _T_992 | stbuf_fwdbyteenvec_hi_3_0; // @[el2_lsu_stbuf.scala 213:147] + wire _T_993 = stbuf_fwdbyteenvec_hi_0_1 | stbuf_fwdbyteenvec_hi_1_1; // @[el2_lsu_stbuf.scala 213:147] + wire _T_994 = _T_993 | stbuf_fwdbyteenvec_hi_2_1; // @[el2_lsu_stbuf.scala 213:147] + wire stbuf_fwdbyteen_hi_pre_m_1 = _T_994 | stbuf_fwdbyteenvec_hi_3_1; // @[el2_lsu_stbuf.scala 213:147] + wire _T_995 = stbuf_fwdbyteenvec_hi_0_2 | stbuf_fwdbyteenvec_hi_1_2; // @[el2_lsu_stbuf.scala 213:147] + wire _T_996 = _T_995 | stbuf_fwdbyteenvec_hi_2_2; // @[el2_lsu_stbuf.scala 213:147] + wire stbuf_fwdbyteen_hi_pre_m_2 = _T_996 | stbuf_fwdbyteenvec_hi_3_2; // @[el2_lsu_stbuf.scala 213:147] + wire _T_997 = stbuf_fwdbyteenvec_hi_0_3 | stbuf_fwdbyteenvec_hi_1_3; // @[el2_lsu_stbuf.scala 213:147] + wire _T_998 = _T_997 | stbuf_fwdbyteenvec_hi_2_3; // @[el2_lsu_stbuf.scala 213:147] + wire stbuf_fwdbyteen_hi_pre_m_3 = _T_998 | stbuf_fwdbyteenvec_hi_3_3; // @[el2_lsu_stbuf.scala 213:147] + wire _T_999 = stbuf_fwdbyteenvec_lo_0_0 | stbuf_fwdbyteenvec_lo_1_0; // @[el2_lsu_stbuf.scala 214:147] + wire _T_1000 = _T_999 | stbuf_fwdbyteenvec_lo_2_0; // @[el2_lsu_stbuf.scala 214:147] + wire stbuf_fwdbyteen_lo_pre_m_0 = _T_1000 | stbuf_fwdbyteenvec_lo_3_0; // @[el2_lsu_stbuf.scala 214:147] + wire _T_1001 = stbuf_fwdbyteenvec_lo_0_1 | stbuf_fwdbyteenvec_lo_1_1; // @[el2_lsu_stbuf.scala 214:147] + wire _T_1002 = _T_1001 | stbuf_fwdbyteenvec_lo_2_1; // @[el2_lsu_stbuf.scala 214:147] + wire stbuf_fwdbyteen_lo_pre_m_1 = _T_1002 | stbuf_fwdbyteenvec_lo_3_1; // @[el2_lsu_stbuf.scala 214:147] + wire _T_1003 = stbuf_fwdbyteenvec_lo_0_2 | stbuf_fwdbyteenvec_lo_1_2; // @[el2_lsu_stbuf.scala 214:147] + wire _T_1004 = _T_1003 | stbuf_fwdbyteenvec_lo_2_2; // @[el2_lsu_stbuf.scala 214:147] + wire stbuf_fwdbyteen_lo_pre_m_2 = _T_1004 | stbuf_fwdbyteenvec_lo_3_2; // @[el2_lsu_stbuf.scala 214:147] + wire _T_1005 = stbuf_fwdbyteenvec_lo_0_3 | stbuf_fwdbyteenvec_lo_1_3; // @[el2_lsu_stbuf.scala 214:147] + wire _T_1006 = _T_1005 | stbuf_fwdbyteenvec_lo_2_3; // @[el2_lsu_stbuf.scala 214:147] + wire stbuf_fwdbyteen_lo_pre_m_3 = _T_1006 | stbuf_fwdbyteenvec_lo_3_3; // @[el2_lsu_stbuf.scala 214:147] wire [31:0] _T_1009 = stbuf_match_hi[0] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_1010 = _T_1009 & stbuf_data_0; // @[el2_lsu_stbuf.scala 222:98] + wire [31:0] _T_1010 = _T_1009 & stbuf_data_0; // @[el2_lsu_stbuf.scala 216:97] wire [31:0] _T_1013 = stbuf_match_hi[1] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_1014 = _T_1013 & stbuf_data_1; // @[el2_lsu_stbuf.scala 222:98] + wire [31:0] _T_1014 = _T_1013 & stbuf_data_1; // @[el2_lsu_stbuf.scala 216:97] wire [31:0] _T_1017 = stbuf_match_hi[2] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_1018 = _T_1017 & stbuf_data_2; // @[el2_lsu_stbuf.scala 222:98] + wire [31:0] _T_1018 = _T_1017 & stbuf_data_2; // @[el2_lsu_stbuf.scala 216:97] wire [31:0] _T_1021 = stbuf_match_hi[3] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_1022 = _T_1021 & stbuf_data_3; // @[el2_lsu_stbuf.scala 222:98] - wire [31:0] _T_1024 = _T_1022 | _T_1018; // @[el2_lsu_stbuf.scala 222:131] - wire [31:0] _T_1025 = _T_1024 | _T_1014; // @[el2_lsu_stbuf.scala 222:131] - wire [31:0] stbuf_fwddata_hi_pre_m = _T_1025 | _T_1010; // @[el2_lsu_stbuf.scala 222:131] + wire [31:0] _T_1022 = _T_1021 & stbuf_data_3; // @[el2_lsu_stbuf.scala 216:97] + wire [31:0] _T_1024 = _T_1022 | _T_1018; // @[el2_lsu_stbuf.scala 216:130] + wire [31:0] _T_1025 = _T_1024 | _T_1014; // @[el2_lsu_stbuf.scala 216:130] + wire [31:0] stbuf_fwddata_hi_pre_m = _T_1025 | _T_1010; // @[el2_lsu_stbuf.scala 216:130] wire [31:0] _T_1028 = stbuf_match_lo[0] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_1029 = _T_1028 & stbuf_data_0; // @[el2_lsu_stbuf.scala 223:98] + wire [31:0] _T_1029 = _T_1028 & stbuf_data_0; // @[el2_lsu_stbuf.scala 217:97] wire [31:0] _T_1032 = stbuf_match_lo[1] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_1033 = _T_1032 & stbuf_data_1; // @[el2_lsu_stbuf.scala 223:98] + wire [31:0] _T_1033 = _T_1032 & stbuf_data_1; // @[el2_lsu_stbuf.scala 217:97] wire [31:0] _T_1036 = stbuf_match_lo[2] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_1037 = _T_1036 & stbuf_data_2; // @[el2_lsu_stbuf.scala 223:98] + wire [31:0] _T_1037 = _T_1036 & stbuf_data_2; // @[el2_lsu_stbuf.scala 217:97] wire [31:0] _T_1040 = stbuf_match_lo[3] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_1041 = _T_1040 & stbuf_data_3; // @[el2_lsu_stbuf.scala 223:98] - wire [31:0] _T_1043 = _T_1041 | _T_1037; // @[el2_lsu_stbuf.scala 223:131] - wire [31:0] _T_1044 = _T_1043 | _T_1033; // @[el2_lsu_stbuf.scala 223:131] - wire [31:0] stbuf_fwddata_lo_pre_m = _T_1044 | _T_1029; // @[el2_lsu_stbuf.scala 223:131] - wire _T_1049 = io_lsu_addr_m[31:2] == io_lsu_addr_r[31:2]; // @[el2_lsu_stbuf.scala 230:50] - wire _T_1050 = _T_1049 & io_lsu_pkt_r_valid; // @[el2_lsu_stbuf.scala 230:75] - wire _T_1051 = _T_1050 & io_lsu_pkt_r_store; // @[el2_lsu_stbuf.scala 230:96] - wire ld_addr_rhit_lo_lo = _T_1051 & _T_739; // @[el2_lsu_stbuf.scala 230:117] - wire _T_1055 = io_end_addr_m[31:2] == io_lsu_addr_r[31:2]; // @[el2_lsu_stbuf.scala 231:50] - wire _T_1056 = _T_1055 & io_lsu_pkt_r_valid; // @[el2_lsu_stbuf.scala 231:75] - wire _T_1057 = _T_1056 & io_lsu_pkt_r_store; // @[el2_lsu_stbuf.scala 231:96] - wire ld_addr_rhit_lo_hi = _T_1057 & _T_739; // @[el2_lsu_stbuf.scala 231:117] - wire _T_1061 = io_lsu_addr_m[31:2] == io_end_addr_r[31:2]; // @[el2_lsu_stbuf.scala 232:50] - wire _T_1062 = _T_1061 & io_lsu_pkt_r_valid; // @[el2_lsu_stbuf.scala 232:75] - wire _T_1063 = _T_1062 & io_lsu_pkt_r_store; // @[el2_lsu_stbuf.scala 232:96] - wire _T_1065 = _T_1063 & _T_739; // @[el2_lsu_stbuf.scala 232:117] - wire ld_addr_rhit_hi_lo = _T_1065 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 232:137] - wire _T_1068 = io_end_addr_m[31:2] == io_end_addr_r[31:2]; // @[el2_lsu_stbuf.scala 233:50] - wire _T_1069 = _T_1068 & io_lsu_pkt_r_valid; // @[el2_lsu_stbuf.scala 233:75] - wire _T_1070 = _T_1069 & io_lsu_pkt_r_store; // @[el2_lsu_stbuf.scala 233:96] - wire _T_1072 = _T_1070 & _T_739; // @[el2_lsu_stbuf.scala 233:117] - wire ld_addr_rhit_hi_hi = _T_1072 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 233:137] - wire _T_1074 = ld_addr_rhit_lo_lo & store_byteen_ext_r[0]; // @[el2_lsu_stbuf.scala 235:80] - wire _T_1076 = ld_addr_rhit_lo_lo & store_byteen_ext_r[1]; // @[el2_lsu_stbuf.scala 235:80] - wire _T_1078 = ld_addr_rhit_lo_lo & store_byteen_ext_r[2]; // @[el2_lsu_stbuf.scala 235:80] - wire _T_1080 = ld_addr_rhit_lo_lo & store_byteen_ext_r[3]; // @[el2_lsu_stbuf.scala 235:80] + wire [31:0] _T_1041 = _T_1040 & stbuf_data_3; // @[el2_lsu_stbuf.scala 217:97] + wire [31:0] _T_1043 = _T_1041 | _T_1037; // @[el2_lsu_stbuf.scala 217:130] + wire [31:0] _T_1044 = _T_1043 | _T_1033; // @[el2_lsu_stbuf.scala 217:130] + wire [31:0] stbuf_fwddata_lo_pre_m = _T_1044 | _T_1029; // @[el2_lsu_stbuf.scala 217:130] + wire _T_1049 = io_lsu_addr_m[31:2] == io_lsu_addr_r[31:2]; // @[el2_lsu_stbuf.scala 224:49] + wire _T_1050 = _T_1049 & io_lsu_pkt_r_valid; // @[el2_lsu_stbuf.scala 224:74] + wire _T_1051 = _T_1050 & io_lsu_pkt_r_bits_store; // @[el2_lsu_stbuf.scala 224:95] + wire ld_addr_rhit_lo_lo = _T_1051 & _T_739; // @[el2_lsu_stbuf.scala 224:121] + wire _T_1055 = io_end_addr_m[31:2] == io_lsu_addr_r[31:2]; // @[el2_lsu_stbuf.scala 225:49] + wire _T_1056 = _T_1055 & io_lsu_pkt_r_valid; // @[el2_lsu_stbuf.scala 225:74] + wire _T_1057 = _T_1056 & io_lsu_pkt_r_bits_store; // @[el2_lsu_stbuf.scala 225:95] + wire ld_addr_rhit_lo_hi = _T_1057 & _T_739; // @[el2_lsu_stbuf.scala 225:121] + wire _T_1061 = io_lsu_addr_m[31:2] == io_end_addr_r[31:2]; // @[el2_lsu_stbuf.scala 226:49] + wire _T_1062 = _T_1061 & io_lsu_pkt_r_valid; // @[el2_lsu_stbuf.scala 226:74] + wire _T_1063 = _T_1062 & io_lsu_pkt_r_bits_store; // @[el2_lsu_stbuf.scala 226:95] + wire _T_1065 = _T_1063 & _T_739; // @[el2_lsu_stbuf.scala 226:121] + wire ld_addr_rhit_hi_lo = _T_1065 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 226:146] + wire _T_1068 = io_end_addr_m[31:2] == io_end_addr_r[31:2]; // @[el2_lsu_stbuf.scala 227:49] + wire _T_1069 = _T_1068 & io_lsu_pkt_r_valid; // @[el2_lsu_stbuf.scala 227:74] + wire _T_1070 = _T_1069 & io_lsu_pkt_r_bits_store; // @[el2_lsu_stbuf.scala 227:95] + wire _T_1072 = _T_1070 & _T_739; // @[el2_lsu_stbuf.scala 227:121] + wire ld_addr_rhit_hi_hi = _T_1072 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 227:146] + wire _T_1074 = ld_addr_rhit_lo_lo & store_byteen_ext_r[0]; // @[el2_lsu_stbuf.scala 229:79] + wire _T_1076 = ld_addr_rhit_lo_lo & store_byteen_ext_r[1]; // @[el2_lsu_stbuf.scala 229:79] + wire _T_1078 = ld_addr_rhit_lo_lo & store_byteen_ext_r[2]; // @[el2_lsu_stbuf.scala 229:79] + wire _T_1080 = ld_addr_rhit_lo_lo & store_byteen_ext_r[3]; // @[el2_lsu_stbuf.scala 229:79] wire [3:0] ld_byte_rhit_lo_lo = {_T_1080,_T_1078,_T_1076,_T_1074}; // @[Cat.scala 29:58] - wire _T_1085 = ld_addr_rhit_lo_hi & store_byteen_ext_r[0]; // @[el2_lsu_stbuf.scala 236:80] - wire _T_1087 = ld_addr_rhit_lo_hi & store_byteen_ext_r[1]; // @[el2_lsu_stbuf.scala 236:80] - wire _T_1089 = ld_addr_rhit_lo_hi & store_byteen_ext_r[2]; // @[el2_lsu_stbuf.scala 236:80] - wire _T_1091 = ld_addr_rhit_lo_hi & store_byteen_ext_r[3]; // @[el2_lsu_stbuf.scala 236:80] + wire _T_1085 = ld_addr_rhit_lo_hi & store_byteen_ext_r[0]; // @[el2_lsu_stbuf.scala 230:79] + wire _T_1087 = ld_addr_rhit_lo_hi & store_byteen_ext_r[1]; // @[el2_lsu_stbuf.scala 230:79] + wire _T_1089 = ld_addr_rhit_lo_hi & store_byteen_ext_r[2]; // @[el2_lsu_stbuf.scala 230:79] + wire _T_1091 = ld_addr_rhit_lo_hi & store_byteen_ext_r[3]; // @[el2_lsu_stbuf.scala 230:79] wire [3:0] ld_byte_rhit_lo_hi = {_T_1091,_T_1089,_T_1087,_T_1085}; // @[Cat.scala 29:58] - wire _T_1096 = ld_addr_rhit_hi_lo & store_byteen_ext_r[4]; // @[el2_lsu_stbuf.scala 237:80] - wire _T_1098 = ld_addr_rhit_hi_lo & store_byteen_ext_r[5]; // @[el2_lsu_stbuf.scala 237:80] - wire _T_1100 = ld_addr_rhit_hi_lo & store_byteen_ext_r[6]; // @[el2_lsu_stbuf.scala 237:80] - wire _T_1102 = ld_addr_rhit_hi_lo & store_byteen_ext_r[7]; // @[el2_lsu_stbuf.scala 237:80] + wire _T_1096 = ld_addr_rhit_hi_lo & store_byteen_ext_r[4]; // @[el2_lsu_stbuf.scala 231:79] + wire _T_1098 = ld_addr_rhit_hi_lo & store_byteen_ext_r[5]; // @[el2_lsu_stbuf.scala 231:79] + wire _T_1100 = ld_addr_rhit_hi_lo & store_byteen_ext_r[6]; // @[el2_lsu_stbuf.scala 231:79] + wire _T_1102 = ld_addr_rhit_hi_lo & store_byteen_ext_r[7]; // @[el2_lsu_stbuf.scala 231:79] wire [3:0] ld_byte_rhit_hi_lo = {_T_1102,_T_1100,_T_1098,_T_1096}; // @[Cat.scala 29:58] - wire _T_1107 = ld_addr_rhit_hi_hi & store_byteen_ext_r[4]; // @[el2_lsu_stbuf.scala 238:80] - wire _T_1109 = ld_addr_rhit_hi_hi & store_byteen_ext_r[5]; // @[el2_lsu_stbuf.scala 238:80] - wire _T_1111 = ld_addr_rhit_hi_hi & store_byteen_ext_r[6]; // @[el2_lsu_stbuf.scala 238:80] - wire _T_1113 = ld_addr_rhit_hi_hi & store_byteen_ext_r[7]; // @[el2_lsu_stbuf.scala 238:80] + wire _T_1107 = ld_addr_rhit_hi_hi & store_byteen_ext_r[4]; // @[el2_lsu_stbuf.scala 232:79] + wire _T_1109 = ld_addr_rhit_hi_hi & store_byteen_ext_r[5]; // @[el2_lsu_stbuf.scala 232:79] + wire _T_1111 = ld_addr_rhit_hi_hi & store_byteen_ext_r[6]; // @[el2_lsu_stbuf.scala 232:79] + wire _T_1113 = ld_addr_rhit_hi_hi & store_byteen_ext_r[7]; // @[el2_lsu_stbuf.scala 232:79] wire [3:0] ld_byte_rhit_hi_hi = {_T_1113,_T_1111,_T_1109,_T_1107}; // @[Cat.scala 29:58] - wire _T_1119 = ld_byte_rhit_lo_lo[0] | ld_byte_rhit_hi_lo[0]; // @[el2_lsu_stbuf.scala 240:80] - wire _T_1122 = ld_byte_rhit_lo_lo[1] | ld_byte_rhit_hi_lo[1]; // @[el2_lsu_stbuf.scala 240:80] - wire _T_1125 = ld_byte_rhit_lo_lo[2] | ld_byte_rhit_hi_lo[2]; // @[el2_lsu_stbuf.scala 240:80] - wire _T_1128 = ld_byte_rhit_lo_lo[3] | ld_byte_rhit_hi_lo[3]; // @[el2_lsu_stbuf.scala 240:80] + wire _T_1119 = ld_byte_rhit_lo_lo[0] | ld_byte_rhit_hi_lo[0]; // @[el2_lsu_stbuf.scala 234:79] + wire _T_1122 = ld_byte_rhit_lo_lo[1] | ld_byte_rhit_hi_lo[1]; // @[el2_lsu_stbuf.scala 234:79] + wire _T_1125 = ld_byte_rhit_lo_lo[2] | ld_byte_rhit_hi_lo[2]; // @[el2_lsu_stbuf.scala 234:79] + wire _T_1128 = ld_byte_rhit_lo_lo[3] | ld_byte_rhit_hi_lo[3]; // @[el2_lsu_stbuf.scala 234:79] wire [3:0] ld_byte_rhit_lo = {_T_1128,_T_1125,_T_1122,_T_1119}; // @[Cat.scala 29:58] - wire _T_1134 = ld_byte_rhit_lo_hi[0] | ld_byte_rhit_hi_hi[0]; // @[el2_lsu_stbuf.scala 241:80] - wire _T_1137 = ld_byte_rhit_lo_hi[1] | ld_byte_rhit_hi_hi[1]; // @[el2_lsu_stbuf.scala 241:80] - wire _T_1140 = ld_byte_rhit_lo_hi[2] | ld_byte_rhit_hi_hi[2]; // @[el2_lsu_stbuf.scala 241:80] - wire _T_1143 = ld_byte_rhit_lo_hi[3] | ld_byte_rhit_hi_hi[3]; // @[el2_lsu_stbuf.scala 241:80] + wire _T_1134 = ld_byte_rhit_lo_hi[0] | ld_byte_rhit_hi_hi[0]; // @[el2_lsu_stbuf.scala 235:79] + wire _T_1137 = ld_byte_rhit_lo_hi[1] | ld_byte_rhit_hi_hi[1]; // @[el2_lsu_stbuf.scala 235:79] + wire _T_1140 = ld_byte_rhit_lo_hi[2] | ld_byte_rhit_hi_hi[2]; // @[el2_lsu_stbuf.scala 235:79] + wire _T_1143 = ld_byte_rhit_lo_hi[3] | ld_byte_rhit_hi_hi[3]; // @[el2_lsu_stbuf.scala 235:79] wire [3:0] ld_byte_rhit_hi = {_T_1143,_T_1140,_T_1137,_T_1134}; // @[Cat.scala 29:58] wire [7:0] _T_1149 = ld_byte_rhit_lo_lo[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_1151 = _T_1149 & io_store_data_lo_r[7:0]; // @[el2_lsu_stbuf.scala 243:54] + wire [7:0] _T_1151 = _T_1149 & io_store_data_lo_r[7:0]; // @[el2_lsu_stbuf.scala 237:53] wire [7:0] _T_1154 = ld_byte_rhit_hi_lo[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_1156 = _T_1154 & io_store_data_hi_r[7:0]; // @[el2_lsu_stbuf.scala 243:115] - wire [7:0] fwdpipe1_lo = _T_1151 | _T_1156; // @[el2_lsu_stbuf.scala 243:81] + wire [7:0] _T_1156 = _T_1154 & io_store_data_hi_r[7:0]; // @[el2_lsu_stbuf.scala 237:114] + wire [7:0] fwdpipe1_lo = _T_1151 | _T_1156; // @[el2_lsu_stbuf.scala 237:80] wire [7:0] _T_1159 = ld_byte_rhit_lo_lo[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_1161 = _T_1159 & io_store_data_lo_r[15:8]; // @[el2_lsu_stbuf.scala 244:54] + wire [7:0] _T_1161 = _T_1159 & io_store_data_lo_r[15:8]; // @[el2_lsu_stbuf.scala 238:53] wire [7:0] _T_1164 = ld_byte_rhit_hi_lo[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_1166 = _T_1164 & io_store_data_hi_r[15:8]; // @[el2_lsu_stbuf.scala 244:116] - wire [7:0] fwdpipe2_lo = _T_1161 | _T_1166; // @[el2_lsu_stbuf.scala 244:82] + wire [7:0] _T_1166 = _T_1164 & io_store_data_hi_r[15:8]; // @[el2_lsu_stbuf.scala 238:115] + wire [7:0] fwdpipe2_lo = _T_1161 | _T_1166; // @[el2_lsu_stbuf.scala 238:81] wire [7:0] _T_1169 = ld_byte_rhit_lo_lo[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_1171 = _T_1169 & io_store_data_lo_r[23:16]; // @[el2_lsu_stbuf.scala 245:54] + wire [7:0] _T_1171 = _T_1169 & io_store_data_lo_r[23:16]; // @[el2_lsu_stbuf.scala 239:53] wire [7:0] _T_1174 = ld_byte_rhit_hi_lo[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_1176 = _T_1174 & io_store_data_hi_r[23:16]; // @[el2_lsu_stbuf.scala 245:117] - wire [7:0] fwdpipe3_lo = _T_1171 | _T_1176; // @[el2_lsu_stbuf.scala 245:83] + wire [7:0] _T_1176 = _T_1174 & io_store_data_hi_r[23:16]; // @[el2_lsu_stbuf.scala 239:116] + wire [7:0] fwdpipe3_lo = _T_1171 | _T_1176; // @[el2_lsu_stbuf.scala 239:82] wire [7:0] _T_1179 = ld_byte_rhit_lo_lo[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_1181 = _T_1179 & io_store_data_lo_r[31:24]; // @[el2_lsu_stbuf.scala 246:54] + wire [7:0] _T_1181 = _T_1179 & io_store_data_lo_r[31:24]; // @[el2_lsu_stbuf.scala 240:53] wire [7:0] _T_1184 = ld_byte_rhit_hi_lo[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [23:0] _GEN_17 = {{16'd0}, _T_1184}; // @[el2_lsu_stbuf.scala 246:117] - wire [23:0] _T_1186 = _GEN_17 & io_store_data_hi_r[31:8]; // @[el2_lsu_stbuf.scala 246:117] - wire [23:0] _GEN_18 = {{16'd0}, _T_1181}; // @[el2_lsu_stbuf.scala 246:83] - wire [23:0] fwdpipe4_lo = _GEN_18 | _T_1186; // @[el2_lsu_stbuf.scala 246:83] - wire [47:0] _T_1189 = {fwdpipe4_lo,fwdpipe3_lo,fwdpipe2_lo,fwdpipe1_lo}; // @[Cat.scala 29:58] + wire [7:0] _T_1186 = _T_1184 & io_store_data_hi_r[31:24]; // @[el2_lsu_stbuf.scala 240:116] + wire [7:0] fwdpipe4_lo = _T_1181 | _T_1186; // @[el2_lsu_stbuf.scala 240:82] + wire [31:0] ld_fwddata_rpipe_lo = {fwdpipe4_lo,fwdpipe3_lo,fwdpipe2_lo,fwdpipe1_lo}; // @[Cat.scala 29:58] wire [7:0] _T_1192 = ld_byte_rhit_lo_hi[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_1194 = _T_1192 & io_store_data_lo_r[7:0]; // @[el2_lsu_stbuf.scala 249:54] + wire [7:0] _T_1194 = _T_1192 & io_store_data_lo_r[7:0]; // @[el2_lsu_stbuf.scala 243:53] wire [7:0] _T_1197 = ld_byte_rhit_hi_hi[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_1199 = _T_1197 & io_store_data_hi_r[7:0]; // @[el2_lsu_stbuf.scala 249:115] - wire [7:0] fwdpipe1_hi = _T_1194 | _T_1199; // @[el2_lsu_stbuf.scala 249:81] + wire [7:0] _T_1199 = _T_1197 & io_store_data_hi_r[7:0]; // @[el2_lsu_stbuf.scala 243:114] + wire [7:0] fwdpipe1_hi = _T_1194 | _T_1199; // @[el2_lsu_stbuf.scala 243:80] wire [7:0] _T_1202 = ld_byte_rhit_lo_hi[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_1204 = _T_1202 & io_store_data_lo_r[15:8]; // @[el2_lsu_stbuf.scala 250:54] + wire [7:0] _T_1204 = _T_1202 & io_store_data_lo_r[15:8]; // @[el2_lsu_stbuf.scala 244:53] wire [7:0] _T_1207 = ld_byte_rhit_hi_hi[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_1209 = _T_1207 & io_store_data_hi_r[15:8]; // @[el2_lsu_stbuf.scala 250:116] - wire [7:0] fwdpipe2_hi = _T_1204 | _T_1209; // @[el2_lsu_stbuf.scala 250:82] + wire [7:0] _T_1209 = _T_1207 & io_store_data_hi_r[15:8]; // @[el2_lsu_stbuf.scala 244:115] + wire [7:0] fwdpipe2_hi = _T_1204 | _T_1209; // @[el2_lsu_stbuf.scala 244:81] wire [7:0] _T_1212 = ld_byte_rhit_lo_hi[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_1214 = _T_1212 & io_store_data_lo_r[23:16]; // @[el2_lsu_stbuf.scala 251:54] + wire [7:0] _T_1214 = _T_1212 & io_store_data_lo_r[23:16]; // @[el2_lsu_stbuf.scala 245:53] wire [7:0] _T_1217 = ld_byte_rhit_hi_hi[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_1219 = _T_1217 & io_store_data_hi_r[23:16]; // @[el2_lsu_stbuf.scala 251:117] - wire [7:0] fwdpipe3_hi = _T_1214 | _T_1219; // @[el2_lsu_stbuf.scala 251:83] + wire [7:0] _T_1219 = _T_1217 & io_store_data_hi_r[23:16]; // @[el2_lsu_stbuf.scala 245:116] + wire [7:0] fwdpipe3_hi = _T_1214 | _T_1219; // @[el2_lsu_stbuf.scala 245:82] wire [7:0] _T_1222 = ld_byte_rhit_lo_hi[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_1224 = _T_1222 & io_store_data_lo_r[31:24]; // @[el2_lsu_stbuf.scala 252:54] + wire [7:0] _T_1224 = _T_1222 & io_store_data_lo_r[31:24]; // @[el2_lsu_stbuf.scala 246:53] wire [7:0] _T_1227 = ld_byte_rhit_hi_hi[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [23:0] _GEN_19 = {{16'd0}, _T_1227}; // @[el2_lsu_stbuf.scala 252:117] - wire [23:0] _T_1229 = _GEN_19 & io_store_data_hi_r[31:8]; // @[el2_lsu_stbuf.scala 252:117] - wire [23:0] _GEN_20 = {{16'd0}, _T_1224}; // @[el2_lsu_stbuf.scala 252:83] - wire [23:0] fwdpipe4_hi = _GEN_20 | _T_1229; // @[el2_lsu_stbuf.scala 252:83] - wire [47:0] _T_1232 = {fwdpipe4_hi,fwdpipe3_hi,fwdpipe2_hi,fwdpipe1_hi}; // @[Cat.scala 29:58] - wire _T_1264 = ld_byte_rhit_hi[0] | stbuf_fwdbyteen_hi_pre_m_0; // @[el2_lsu_stbuf.scala 258:84] - wire _T_1266 = ld_byte_rhit_hi[1] | stbuf_fwdbyteen_hi_pre_m_1; // @[el2_lsu_stbuf.scala 258:84] - wire _T_1268 = ld_byte_rhit_hi[2] | stbuf_fwdbyteen_hi_pre_m_2; // @[el2_lsu_stbuf.scala 258:84] - wire _T_1270 = ld_byte_rhit_hi[3] | stbuf_fwdbyteen_hi_pre_m_3; // @[el2_lsu_stbuf.scala 258:84] + wire [7:0] _T_1229 = _T_1227 & io_store_data_hi_r[31:24]; // @[el2_lsu_stbuf.scala 246:116] + wire [7:0] fwdpipe4_hi = _T_1224 | _T_1229; // @[el2_lsu_stbuf.scala 246:82] + wire [31:0] ld_fwddata_rpipe_hi = {fwdpipe4_hi,fwdpipe3_hi,fwdpipe2_hi,fwdpipe1_hi}; // @[Cat.scala 29:58] + wire _T_1264 = ld_byte_rhit_hi[0] | stbuf_fwdbyteen_hi_pre_m_0; // @[el2_lsu_stbuf.scala 252:83] + wire _T_1266 = ld_byte_rhit_hi[1] | stbuf_fwdbyteen_hi_pre_m_1; // @[el2_lsu_stbuf.scala 252:83] + wire _T_1268 = ld_byte_rhit_hi[2] | stbuf_fwdbyteen_hi_pre_m_2; // @[el2_lsu_stbuf.scala 252:83] + wire _T_1270 = ld_byte_rhit_hi[3] | stbuf_fwdbyteen_hi_pre_m_3; // @[el2_lsu_stbuf.scala 252:83] wire [2:0] _T_1272 = {_T_1270,_T_1268,_T_1266}; // @[Cat.scala 29:58] - wire _T_1275 = ld_byte_rhit_lo[0] | stbuf_fwdbyteen_lo_pre_m_0; // @[el2_lsu_stbuf.scala 259:84] - wire _T_1277 = ld_byte_rhit_lo[1] | stbuf_fwdbyteen_lo_pre_m_1; // @[el2_lsu_stbuf.scala 259:84] - wire _T_1279 = ld_byte_rhit_lo[2] | stbuf_fwdbyteen_lo_pre_m_2; // @[el2_lsu_stbuf.scala 259:84] - wire _T_1281 = ld_byte_rhit_lo[3] | stbuf_fwdbyteen_lo_pre_m_3; // @[el2_lsu_stbuf.scala 259:84] + wire _T_1275 = ld_byte_rhit_lo[0] | stbuf_fwdbyteen_lo_pre_m_0; // @[el2_lsu_stbuf.scala 253:83] + wire _T_1277 = ld_byte_rhit_lo[1] | stbuf_fwdbyteen_lo_pre_m_1; // @[el2_lsu_stbuf.scala 253:83] + wire _T_1279 = ld_byte_rhit_lo[2] | stbuf_fwdbyteen_lo_pre_m_2; // @[el2_lsu_stbuf.scala 253:83] + wire _T_1281 = ld_byte_rhit_lo[3] | stbuf_fwdbyteen_lo_pre_m_3; // @[el2_lsu_stbuf.scala 253:83] wire [2:0] _T_1283 = {_T_1281,_T_1279,_T_1277}; // @[Cat.scala 29:58] - wire [31:0] ld_fwddata_rpipe_lo = _T_1189[31:0]; // @[el2_lsu_stbuf.scala 247:24] - wire [7:0] stbuf_fwdpipe1_lo = ld_byte_rhit_lo[0] ? ld_fwddata_rpipe_lo[7:0] : stbuf_fwddata_lo_pre_m[7:0]; // @[el2_lsu_stbuf.scala 262:31] - wire [7:0] stbuf_fwdpipe2_lo = ld_byte_rhit_lo[1] ? ld_fwddata_rpipe_lo[15:8] : stbuf_fwddata_lo_pre_m[15:8]; // @[el2_lsu_stbuf.scala 263:31] - wire [7:0] stbuf_fwdpipe3_lo = ld_byte_rhit_lo[2] ? ld_fwddata_rpipe_lo[23:16] : stbuf_fwddata_lo_pre_m[23:16]; // @[el2_lsu_stbuf.scala 264:31] - wire [7:0] stbuf_fwdpipe4_lo = ld_byte_rhit_lo[3] ? ld_fwddata_rpipe_lo[31:24] : stbuf_fwddata_lo_pre_m[31:24]; // @[el2_lsu_stbuf.scala 265:31] + wire [7:0] stbuf_fwdpipe1_lo = ld_byte_rhit_lo[0] ? ld_fwddata_rpipe_lo[7:0] : stbuf_fwddata_lo_pre_m[7:0]; // @[el2_lsu_stbuf.scala 256:30] + wire [7:0] stbuf_fwdpipe2_lo = ld_byte_rhit_lo[1] ? ld_fwddata_rpipe_lo[15:8] : stbuf_fwddata_lo_pre_m[15:8]; // @[el2_lsu_stbuf.scala 257:30] + wire [7:0] stbuf_fwdpipe3_lo = ld_byte_rhit_lo[2] ? ld_fwddata_rpipe_lo[23:16] : stbuf_fwddata_lo_pre_m[23:16]; // @[el2_lsu_stbuf.scala 258:30] + wire [7:0] stbuf_fwdpipe4_lo = ld_byte_rhit_lo[3] ? ld_fwddata_rpipe_lo[31:24] : stbuf_fwddata_lo_pre_m[31:24]; // @[el2_lsu_stbuf.scala 259:30] wire [15:0] _T_1297 = {stbuf_fwdpipe2_lo,stbuf_fwdpipe1_lo}; // @[Cat.scala 29:58] wire [15:0] _T_1298 = {stbuf_fwdpipe4_lo,stbuf_fwdpipe3_lo}; // @[Cat.scala 29:58] - wire [31:0] ld_fwddata_rpipe_hi = _T_1232[31:0]; // @[el2_lsu_stbuf.scala 253:24] - wire [7:0] stbuf_fwdpipe1_hi = ld_byte_rhit_hi[0] ? ld_fwddata_rpipe_hi[7:0] : stbuf_fwddata_hi_pre_m[7:0]; // @[el2_lsu_stbuf.scala 268:31] - wire [7:0] stbuf_fwdpipe2_hi = ld_byte_rhit_hi[1] ? ld_fwddata_rpipe_hi[15:8] : stbuf_fwddata_hi_pre_m[15:8]; // @[el2_lsu_stbuf.scala 269:31] - wire [7:0] stbuf_fwdpipe3_hi = ld_byte_rhit_hi[2] ? ld_fwddata_rpipe_hi[23:16] : stbuf_fwddata_hi_pre_m[23:16]; // @[el2_lsu_stbuf.scala 270:31] - wire [7:0] stbuf_fwdpipe4_hi = ld_byte_rhit_hi[3] ? ld_fwddata_rpipe_hi[31:24] : stbuf_fwddata_hi_pre_m[31:24]; // @[el2_lsu_stbuf.scala 271:31] + wire [7:0] stbuf_fwdpipe1_hi = ld_byte_rhit_hi[0] ? ld_fwddata_rpipe_hi[7:0] : stbuf_fwddata_hi_pre_m[7:0]; // @[el2_lsu_stbuf.scala 262:30] + wire [7:0] stbuf_fwdpipe2_hi = ld_byte_rhit_hi[1] ? ld_fwddata_rpipe_hi[15:8] : stbuf_fwddata_hi_pre_m[15:8]; // @[el2_lsu_stbuf.scala 263:30] + wire [7:0] stbuf_fwdpipe3_hi = ld_byte_rhit_hi[2] ? ld_fwddata_rpipe_hi[23:16] : stbuf_fwddata_hi_pre_m[23:16]; // @[el2_lsu_stbuf.scala 264:30] + wire [7:0] stbuf_fwdpipe4_hi = ld_byte_rhit_hi[3] ? ld_fwddata_rpipe_hi[31:24] : stbuf_fwddata_hi_pre_m[31:24]; // @[el2_lsu_stbuf.scala 265:30] wire [15:0] _T_1312 = {stbuf_fwdpipe2_hi,stbuf_fwdpipe1_hi}; // @[Cat.scala 29:58] wire [15:0] _T_1313 = {stbuf_fwdpipe4_hi,stbuf_fwdpipe3_hi}; // @[Cat.scala 29:58] - rvclkhdr rvclkhdr ( // @[beh_lib.scala 352:21] + rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), .io_en(rvclkhdr_io_en), .io_scan_mode(rvclkhdr_io_scan_mode) ); - rvclkhdr rvclkhdr_1 ( // @[beh_lib.scala 352:21] + rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 508:23] .io_l1clk(rvclkhdr_1_io_l1clk), .io_clk(rvclkhdr_1_io_clk), .io_en(rvclkhdr_1_io_en), .io_scan_mode(rvclkhdr_1_io_scan_mode) ); - rvclkhdr rvclkhdr_2 ( // @[beh_lib.scala 352:21] + rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 508:23] .io_l1clk(rvclkhdr_2_io_l1clk), .io_clk(rvclkhdr_2_io_clk), .io_en(rvclkhdr_2_io_en), .io_scan_mode(rvclkhdr_2_io_scan_mode) ); - rvclkhdr rvclkhdr_3 ( // @[beh_lib.scala 352:21] + rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 508:23] .io_l1clk(rvclkhdr_3_io_l1clk), .io_clk(rvclkhdr_3_io_clk), .io_en(rvclkhdr_3_io_en), .io_scan_mode(rvclkhdr_3_io_scan_mode) ); - rvclkhdr rvclkhdr_4 ( // @[beh_lib.scala 352:21] + rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 508:23] .io_l1clk(rvclkhdr_4_io_l1clk), .io_clk(rvclkhdr_4_io_clk), .io_en(rvclkhdr_4_io_en), .io_scan_mode(rvclkhdr_4_io_scan_mode) ); - rvclkhdr rvclkhdr_5 ( // @[beh_lib.scala 352:21] + rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 508:23] .io_l1clk(rvclkhdr_5_io_l1clk), .io_clk(rvclkhdr_5_io_clk), .io_en(rvclkhdr_5_io_en), .io_scan_mode(rvclkhdr_5_io_scan_mode) ); - rvclkhdr rvclkhdr_6 ( // @[beh_lib.scala 352:21] + rvclkhdr rvclkhdr_6 ( // @[el2_lib.scala 508:23] .io_l1clk(rvclkhdr_6_io_l1clk), .io_clk(rvclkhdr_6_io_clk), .io_en(rvclkhdr_6_io_en), .io_scan_mode(rvclkhdr_6_io_scan_mode) ); - rvclkhdr rvclkhdr_7 ( // @[beh_lib.scala 352:21] + rvclkhdr rvclkhdr_7 ( // @[el2_lib.scala 508:23] .io_l1clk(rvclkhdr_7_io_l1clk), .io_clk(rvclkhdr_7_io_clk), .io_en(rvclkhdr_7_io_en), .io_scan_mode(rvclkhdr_7_io_scan_mode) ); - assign io_stbuf_reqvld_any = _T_699 & _T_701; // @[el2_lsu_stbuf.scala 52:47 el2_lsu_stbuf.scala 181:25] - assign io_stbuf_reqvld_flushed_any = _T_689[0] & _T_691[0]; // @[el2_lsu_stbuf.scala 53:36 el2_lsu_stbuf.scala 180:32] - assign io_stbuf_addr_any = 2'h3 == RdPtr ? stbuf_addr_3 : _GEN_2; // @[el2_lsu_stbuf.scala 54:35 el2_lsu_stbuf.scala 182:23] - assign io_stbuf_data_any = 2'h3 == RdPtr ? stbuf_data_3 : _GEN_6; // @[el2_lsu_stbuf.scala 55:35 el2_lsu_stbuf.scala 183:23] - assign io_lsu_stbuf_full_any = _T_752 ? _T_754 : _T_755; // @[el2_lsu_stbuf.scala 56:43 el2_lsu_stbuf.scala 202:27] - assign io_lsu_stbuf_empty_any = stbuf_numvld_any == 4'h0; // @[el2_lsu_stbuf.scala 57:43 el2_lsu_stbuf.scala 203:27] - assign io_ldst_stbuf_reqvld_r = io_lsu_commit_r & io_store_stbuf_reqvld_r; // @[el2_lsu_stbuf.scala 58:43 el2_lsu_stbuf.scala 129:27] - assign io_stbuf_fwddata_hi_m = {_T_1313,_T_1312}; // @[el2_lsu_stbuf.scala 59:43 el2_lsu_stbuf.scala 272:26] - assign io_stbuf_fwddata_lo_m = {_T_1298,_T_1297}; // @[el2_lsu_stbuf.scala 60:43 el2_lsu_stbuf.scala 266:26] - assign io_stbuf_fwdbyteen_hi_m = {_T_1272,_T_1264}; // @[el2_lsu_stbuf.scala 61:37 el2_lsu_stbuf.scala 258:28] - assign io_stbuf_fwdbyteen_lo_m = {_T_1283,_T_1275}; // @[el2_lsu_stbuf.scala 62:37 el2_lsu_stbuf.scala 259:28] - assign rvclkhdr_io_clk = clock; // @[beh_lib.scala 354:16] - assign rvclkhdr_io_en = stbuf_wr_en[0]; // @[beh_lib.scala 355:15] - assign rvclkhdr_io_scan_mode = io_scan_mode; // @[beh_lib.scala 356:22] - assign rvclkhdr_1_io_clk = clock; // @[beh_lib.scala 354:16] - assign rvclkhdr_1_io_en = stbuf_wr_en[0]; // @[beh_lib.scala 355:15] - assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[beh_lib.scala 356:22] - assign rvclkhdr_2_io_clk = clock; // @[beh_lib.scala 354:16] - assign rvclkhdr_2_io_en = stbuf_wr_en[1]; // @[beh_lib.scala 355:15] - assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[beh_lib.scala 356:22] - assign rvclkhdr_3_io_clk = clock; // @[beh_lib.scala 354:16] - assign rvclkhdr_3_io_en = stbuf_wr_en[1]; // @[beh_lib.scala 355:15] - assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[beh_lib.scala 356:22] - assign rvclkhdr_4_io_clk = clock; // @[beh_lib.scala 354:16] - assign rvclkhdr_4_io_en = stbuf_wr_en[2]; // @[beh_lib.scala 355:15] - assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[beh_lib.scala 356:22] - assign rvclkhdr_5_io_clk = clock; // @[beh_lib.scala 354:16] - assign rvclkhdr_5_io_en = stbuf_wr_en[2]; // @[beh_lib.scala 355:15] - assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[beh_lib.scala 356:22] - assign rvclkhdr_6_io_clk = clock; // @[beh_lib.scala 354:16] - assign rvclkhdr_6_io_en = stbuf_wr_en[3]; // @[beh_lib.scala 355:15] - assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[beh_lib.scala 356:22] - assign rvclkhdr_7_io_clk = clock; // @[beh_lib.scala 354:16] - assign rvclkhdr_7_io_en = stbuf_wr_en[3]; // @[beh_lib.scala 355:15] - assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[beh_lib.scala 356:22] + assign io_stbuf_reqvld_any = _T_699 & _T_701; // @[el2_lsu_stbuf.scala 51:47 el2_lsu_stbuf.scala 175:24] + assign io_stbuf_reqvld_flushed_any = _T_689[0] & _T_691[0]; // @[el2_lsu_stbuf.scala 52:35 el2_lsu_stbuf.scala 174:31] + assign io_stbuf_addr_any = 2'h3 == RdPtr ? stbuf_addr_3 : _GEN_2; // @[el2_lsu_stbuf.scala 53:35 el2_lsu_stbuf.scala 176:22] + assign io_stbuf_data_any = 2'h3 == RdPtr ? stbuf_data_3 : _GEN_6; // @[el2_lsu_stbuf.scala 54:35 el2_lsu_stbuf.scala 177:22] + assign io_lsu_stbuf_full_any = _T_752 ? _T_754 : _T_755; // @[el2_lsu_stbuf.scala 55:43 el2_lsu_stbuf.scala 196:26] + assign io_lsu_stbuf_empty_any = stbuf_numvld_any == 4'h0; // @[el2_lsu_stbuf.scala 56:43 el2_lsu_stbuf.scala 197:26] + assign io_ldst_stbuf_reqvld_r = io_lsu_commit_r & io_store_stbuf_reqvld_r; // @[el2_lsu_stbuf.scala 57:43 el2_lsu_stbuf.scala 128:26] + assign io_stbuf_fwddata_hi_m = {_T_1313,_T_1312}; // @[el2_lsu_stbuf.scala 58:43 el2_lsu_stbuf.scala 266:25] + assign io_stbuf_fwddata_lo_m = {_T_1298,_T_1297}; // @[el2_lsu_stbuf.scala 59:43 el2_lsu_stbuf.scala 260:25] + assign io_stbuf_fwdbyteen_hi_m = {_T_1272,_T_1264}; // @[el2_lsu_stbuf.scala 60:37 el2_lsu_stbuf.scala 252:27] + assign io_stbuf_fwdbyteen_lo_m = {_T_1283,_T_1275}; // @[el2_lsu_stbuf.scala 61:37 el2_lsu_stbuf.scala 253:27] + assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_io_en = stbuf_wr_en[0]; // @[el2_lib.scala 511:17] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_1_io_en = stbuf_wr_en[0]; // @[el2_lib.scala 511:17] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_2_io_en = stbuf_wr_en[1]; // @[el2_lib.scala 511:17] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_3_io_en = stbuf_wr_en[1]; // @[el2_lib.scala 511:17] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_4_io_en = stbuf_wr_en[2]; // @[el2_lib.scala 511:17] + assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_5_io_en = stbuf_wr_en[2]; // @[el2_lib.scala 511:17] + assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_6_io_en = stbuf_wr_en[3]; // @[el2_lib.scala 511:17] + assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_7_io_en = stbuf_wr_en[3]; // @[el2_lib.scala 511:17] + assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -1086,28 +1080,28 @@ end // initial _T_564 <= _T_560 & _T_34; end end - always @(posedge clock or posedge reset) begin + always @(posedge io_lsu_free_c2_clk or posedge reset) begin if (reset) begin _T_623 <= 1'h0; end else begin _T_623 <= _T_619 & _T_67; end end - always @(posedge clock or posedge reset) begin + always @(posedge io_lsu_free_c2_clk or posedge reset) begin if (reset) begin _T_615 <= 1'h0; end else begin _T_615 <= _T_611 & _T_56; end end - always @(posedge clock or posedge reset) begin + always @(posedge io_lsu_free_c2_clk or posedge reset) begin if (reset) begin _T_607 <= 1'h0; end else begin _T_607 <= _T_603 & _T_45; end end - always @(posedge clock or posedge reset) begin + always @(posedge io_lsu_free_c2_clk or posedge reset) begin if (reset) begin _T_599 <= 1'h0; end else begin diff --git a/el2_lsu_trigger.anno.json b/el2_lsu_trigger.anno.json index 66a5a1ad..065a1cdb 100644 --- a/el2_lsu_trigger.anno.json +++ b/el2_lsu_trigger.anno.json @@ -4,12 +4,12 @@ "sink":"~el2_lsu_trigger|el2_lsu_trigger>io_lsu_trigger_match_m", "sources":[ "~el2_lsu_trigger|el2_lsu_trigger>io_lsu_pkt_m_valid", - "~el2_lsu_trigger|el2_lsu_trigger>io_lsu_pkt_m_dma", + "~el2_lsu_trigger|el2_lsu_trigger>io_lsu_pkt_m_bits_dma", "~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_0_store", - "~el2_lsu_trigger|el2_lsu_trigger>io_lsu_pkt_m_store", + "~el2_lsu_trigger|el2_lsu_trigger>io_lsu_pkt_m_bits_store", "~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_1_store", "~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_0_load", - "~el2_lsu_trigger|el2_lsu_trigger>io_lsu_pkt_m_load", + "~el2_lsu_trigger|el2_lsu_trigger>io_lsu_pkt_m_bits_load", "~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_0_select", "~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_3_store", "~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_2_store", @@ -20,17 +20,17 @@ "~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_2_load", "~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_2_select", "~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_0_tdata2", + "~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_0_match_pkt", "~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_1_tdata2", - "~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_0_match_", + "~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_1_match_pkt", "~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_3_tdata2", + "~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_3_match_pkt", "~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_2_tdata2", - "~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_1_match_", - "~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_3_match_", - "~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_2_match_", + "~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_2_match_pkt", "~el2_lsu_trigger|el2_lsu_trigger>io_lsu_addr_m", "~el2_lsu_trigger|el2_lsu_trigger>io_store_data_m", - "~el2_lsu_trigger|el2_lsu_trigger>io_lsu_pkt_m_word", - "~el2_lsu_trigger|el2_lsu_trigger>io_lsu_pkt_m_half" + "~el2_lsu_trigger|el2_lsu_trigger>io_lsu_pkt_m_bits_word", + "~el2_lsu_trigger|el2_lsu_trigger>io_lsu_pkt_m_bits_half" ] }, { diff --git a/el2_lsu_trigger.fir b/el2_lsu_trigger.fir index 0cab0a14..4c99a3e9 100644 --- a/el2_lsu_trigger.fir +++ b/el2_lsu_trigger.fir @@ -3,18 +3,18 @@ circuit el2_lsu_trigger : module el2_lsu_trigger : input clock : Clock input reset : AsyncReset - output io : {flip trigger_pkt_any : {select : UInt<1>, match_ : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip lsu_pkt_m : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip lsu_addr_m : UInt<32>, flip store_data_m : UInt<32>, lsu_trigger_match_m : UInt<4>} + output io : {flip trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_addr_m : UInt<32>, flip store_data_m : UInt<32>, lsu_trigger_match_m : UInt<4>} - node _T = bits(io.lsu_pkt_m.word, 0, 0) @[Bitwise.scala 72:15] + node _T = bits(io.lsu_pkt_m.bits.word, 0, 0) @[Bitwise.scala 72:15] node _T_1 = mux(_T, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12] - node _T_2 = bits(io.store_data_m, 31, 16) @[el2_lsu_trigger.scala 16:78] - node _T_3 = and(_T_1, _T_2) @[el2_lsu_trigger.scala 16:61] - node _T_4 = or(io.lsu_pkt_m.half, io.lsu_pkt_m.word) @[el2_lsu_trigger.scala 16:114] + node _T_2 = bits(io.store_data_m, 31, 16) @[el2_lsu_trigger.scala 16:83] + node _T_3 = and(_T_1, _T_2) @[el2_lsu_trigger.scala 16:66] + node _T_4 = or(io.lsu_pkt_m.bits.half, io.lsu_pkt_m.bits.word) @[el2_lsu_trigger.scala 16:124] node _T_5 = bits(_T_4, 0, 0) @[Bitwise.scala 72:15] node _T_6 = mux(_T_5, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_7 = bits(io.store_data_m, 15, 8) @[el2_lsu_trigger.scala 16:153] - node _T_8 = and(_T_6, _T_7) @[el2_lsu_trigger.scala 16:136] - node _T_9 = bits(io.store_data_m, 7, 0) @[el2_lsu_trigger.scala 16:177] + node _T_7 = bits(io.store_data_m, 15, 8) @[el2_lsu_trigger.scala 16:168] + node _T_8 = and(_T_6, _T_7) @[el2_lsu_trigger.scala 16:151] + node _T_9 = bits(io.store_data_m, 7, 0) @[el2_lsu_trigger.scala 16:192] node _T_10 = cat(_T_3, _T_8) @[Cat.scala 29:58] node store_data_trigger_m = cat(_T_10, _T_9) @[Cat.scala 29:58] node _T_11 = bits(io.trigger_pkt_any[0].select, 0, 0) @[el2_lsu_trigger.scala 17:83] @@ -53,1212 +53,1200 @@ circuit el2_lsu_trigger : node _T_38 = or(_T_36, _T_37) @[Mux.scala 27:72] wire lsu_match_data_3 : UInt<32> @[Mux.scala 27:72] lsu_match_data_3 <= _T_38 @[Mux.scala 27:72] - node _T_39 = eq(io.lsu_pkt_m.dma, UInt<1>("h00")) @[el2_lsu_trigger.scala 18:71] + node _T_39 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[el2_lsu_trigger.scala 18:71] node _T_40 = and(io.lsu_pkt_m.valid, _T_39) @[el2_lsu_trigger.scala 18:69] - node _T_41 = and(io.trigger_pkt_any[0].store, io.lsu_pkt_m.store) @[el2_lsu_trigger.scala 18:121] - node _T_42 = and(io.trigger_pkt_any[0].load, io.lsu_pkt_m.load) @[el2_lsu_trigger.scala 19:33] - node _T_43 = eq(io.trigger_pkt_any[0].select, UInt<1>("h00")) @[el2_lsu_trigger.scala 19:55] - node _T_44 = and(_T_42, _T_43) @[el2_lsu_trigger.scala 19:53] - node _T_45 = or(_T_41, _T_44) @[el2_lsu_trigger.scala 18:142] - node _T_46 = and(_T_40, _T_45) @[el2_lsu_trigger.scala 18:89] - node _T_47 = bits(io.trigger_pkt_any[0].match_, 0, 0) @[el2_lsu_trigger.scala 20:106] - wire _T_48 : UInt<1>[32] @[el2_lib.scala 239:24] - node _T_49 = bits(_T_47, 0, 0) @[el2_lib.scala 240:37] - node _T_50 = bits(io.trigger_pkt_any[0].tdata2, 31, 0) @[el2_lib.scala 240:53] - node _T_51 = andr(_T_50) @[el2_lib.scala 240:73] - node _T_52 = not(_T_51) @[el2_lib.scala 240:47] - node _T_53 = and(_T_49, _T_52) @[el2_lib.scala 240:44] - node _T_54 = bits(io.trigger_pkt_any[0].tdata2, 0, 0) @[el2_lib.scala 241:48] - node _T_55 = bits(lsu_match_data_0, 0, 0) @[el2_lib.scala 241:60] - node _T_56 = eq(_T_54, _T_55) @[el2_lib.scala 241:52] - node _T_57 = or(_T_53, _T_56) @[el2_lib.scala 241:41] - _T_48[0] <= _T_57 @[el2_lib.scala 241:18] - node _T_58 = bits(io.trigger_pkt_any[0].tdata2, 0, 0) @[el2_lib.scala 243:29] - node _T_59 = andr(_T_58) @[el2_lib.scala 243:37] - node _T_60 = and(_T_59, _T_53) @[el2_lib.scala 243:42] - node _T_61 = bits(io.trigger_pkt_any[0].tdata2, 1, 1) @[el2_lib.scala 243:75] - node _T_62 = bits(lsu_match_data_0, 1, 1) @[el2_lib.scala 243:87] - node _T_63 = eq(_T_61, _T_62) @[el2_lib.scala 243:79] - node _T_64 = mux(_T_60, UInt<1>("h01"), _T_63) @[el2_lib.scala 243:24] - _T_48[1] <= _T_64 @[el2_lib.scala 243:18] - node _T_65 = bits(io.trigger_pkt_any[0].tdata2, 1, 0) @[el2_lib.scala 243:29] - node _T_66 = andr(_T_65) @[el2_lib.scala 243:37] - node _T_67 = and(_T_66, _T_53) @[el2_lib.scala 243:42] - node _T_68 = bits(io.trigger_pkt_any[0].tdata2, 2, 2) @[el2_lib.scala 243:75] - node _T_69 = bits(lsu_match_data_0, 2, 2) @[el2_lib.scala 243:87] - node _T_70 = eq(_T_68, _T_69) @[el2_lib.scala 243:79] - node _T_71 = mux(_T_67, UInt<1>("h01"), _T_70) @[el2_lib.scala 243:24] - _T_48[2] <= _T_71 @[el2_lib.scala 243:18] - node _T_72 = bits(io.trigger_pkt_any[0].tdata2, 2, 0) @[el2_lib.scala 243:29] - node _T_73 = andr(_T_72) @[el2_lib.scala 243:37] - node _T_74 = and(_T_73, _T_53) @[el2_lib.scala 243:42] - node _T_75 = bits(io.trigger_pkt_any[0].tdata2, 3, 3) @[el2_lib.scala 243:75] - node _T_76 = bits(lsu_match_data_0, 3, 3) @[el2_lib.scala 243:87] - node _T_77 = eq(_T_75, _T_76) @[el2_lib.scala 243:79] - node _T_78 = mux(_T_74, UInt<1>("h01"), _T_77) @[el2_lib.scala 243:24] - _T_48[3] <= _T_78 @[el2_lib.scala 243:18] - node _T_79 = bits(io.trigger_pkt_any[0].tdata2, 3, 0) @[el2_lib.scala 243:29] - node _T_80 = andr(_T_79) @[el2_lib.scala 243:37] - node _T_81 = and(_T_80, _T_53) @[el2_lib.scala 243:42] - node _T_82 = bits(io.trigger_pkt_any[0].tdata2, 4, 4) @[el2_lib.scala 243:75] - node _T_83 = bits(lsu_match_data_0, 4, 4) @[el2_lib.scala 243:87] - node _T_84 = eq(_T_82, _T_83) @[el2_lib.scala 243:79] - node _T_85 = mux(_T_81, UInt<1>("h01"), _T_84) @[el2_lib.scala 243:24] - _T_48[4] <= _T_85 @[el2_lib.scala 243:18] - node _T_86 = bits(io.trigger_pkt_any[0].tdata2, 4, 0) @[el2_lib.scala 243:29] - node _T_87 = andr(_T_86) @[el2_lib.scala 243:37] - node _T_88 = and(_T_87, _T_53) @[el2_lib.scala 243:42] - node _T_89 = bits(io.trigger_pkt_any[0].tdata2, 5, 5) @[el2_lib.scala 243:75] - node _T_90 = bits(lsu_match_data_0, 5, 5) @[el2_lib.scala 243:87] - node _T_91 = eq(_T_89, _T_90) @[el2_lib.scala 243:79] - node _T_92 = mux(_T_88, UInt<1>("h01"), _T_91) @[el2_lib.scala 243:24] - _T_48[5] <= _T_92 @[el2_lib.scala 243:18] - node _T_93 = bits(io.trigger_pkt_any[0].tdata2, 5, 0) @[el2_lib.scala 243:29] - node _T_94 = andr(_T_93) @[el2_lib.scala 243:37] - node _T_95 = and(_T_94, _T_53) @[el2_lib.scala 243:42] - node _T_96 = bits(io.trigger_pkt_any[0].tdata2, 6, 6) @[el2_lib.scala 243:75] - node _T_97 = bits(lsu_match_data_0, 6, 6) @[el2_lib.scala 243:87] - node _T_98 = eq(_T_96, _T_97) @[el2_lib.scala 243:79] - node _T_99 = mux(_T_95, UInt<1>("h01"), _T_98) @[el2_lib.scala 243:24] - _T_48[6] <= _T_99 @[el2_lib.scala 243:18] - node _T_100 = bits(io.trigger_pkt_any[0].tdata2, 6, 0) @[el2_lib.scala 243:29] - node _T_101 = andr(_T_100) @[el2_lib.scala 243:37] - node _T_102 = and(_T_101, _T_53) @[el2_lib.scala 243:42] - node _T_103 = bits(io.trigger_pkt_any[0].tdata2, 7, 7) @[el2_lib.scala 243:75] - node _T_104 = bits(lsu_match_data_0, 7, 7) @[el2_lib.scala 243:87] - node _T_105 = eq(_T_103, _T_104) @[el2_lib.scala 243:79] - node _T_106 = mux(_T_102, UInt<1>("h01"), _T_105) @[el2_lib.scala 243:24] - _T_48[7] <= _T_106 @[el2_lib.scala 243:18] - node _T_107 = bits(io.trigger_pkt_any[0].tdata2, 7, 0) @[el2_lib.scala 243:29] - node _T_108 = andr(_T_107) @[el2_lib.scala 243:37] - node _T_109 = and(_T_108, _T_53) @[el2_lib.scala 243:42] - node _T_110 = bits(io.trigger_pkt_any[0].tdata2, 8, 8) @[el2_lib.scala 243:75] - node _T_111 = bits(lsu_match_data_0, 8, 8) @[el2_lib.scala 243:87] - node _T_112 = eq(_T_110, _T_111) @[el2_lib.scala 243:79] - node _T_113 = mux(_T_109, UInt<1>("h01"), _T_112) @[el2_lib.scala 243:24] - _T_48[8] <= _T_113 @[el2_lib.scala 243:18] - node _T_114 = bits(io.trigger_pkt_any[0].tdata2, 8, 0) @[el2_lib.scala 243:29] - node _T_115 = andr(_T_114) @[el2_lib.scala 243:37] - node _T_116 = and(_T_115, _T_53) @[el2_lib.scala 243:42] - node _T_117 = bits(io.trigger_pkt_any[0].tdata2, 9, 9) @[el2_lib.scala 243:75] - node _T_118 = bits(lsu_match_data_0, 9, 9) @[el2_lib.scala 243:87] - node _T_119 = eq(_T_117, _T_118) @[el2_lib.scala 243:79] - node _T_120 = mux(_T_116, UInt<1>("h01"), _T_119) @[el2_lib.scala 243:24] - _T_48[9] <= _T_120 @[el2_lib.scala 243:18] - node _T_121 = bits(io.trigger_pkt_any[0].tdata2, 9, 0) @[el2_lib.scala 243:29] - node _T_122 = andr(_T_121) @[el2_lib.scala 243:37] - node _T_123 = and(_T_122, _T_53) @[el2_lib.scala 243:42] - node _T_124 = bits(io.trigger_pkt_any[0].tdata2, 10, 10) @[el2_lib.scala 243:75] - node _T_125 = bits(lsu_match_data_0, 10, 10) @[el2_lib.scala 243:87] - node _T_126 = eq(_T_124, _T_125) @[el2_lib.scala 243:79] - node _T_127 = mux(_T_123, UInt<1>("h01"), _T_126) @[el2_lib.scala 243:24] - _T_48[10] <= _T_127 @[el2_lib.scala 243:18] - node _T_128 = bits(io.trigger_pkt_any[0].tdata2, 10, 0) @[el2_lib.scala 243:29] - node _T_129 = andr(_T_128) @[el2_lib.scala 243:37] - node _T_130 = and(_T_129, _T_53) @[el2_lib.scala 243:42] - node _T_131 = bits(io.trigger_pkt_any[0].tdata2, 11, 11) @[el2_lib.scala 243:75] - node _T_132 = bits(lsu_match_data_0, 11, 11) @[el2_lib.scala 243:87] - node _T_133 = eq(_T_131, _T_132) @[el2_lib.scala 243:79] - node _T_134 = mux(_T_130, UInt<1>("h01"), _T_133) @[el2_lib.scala 243:24] - _T_48[11] <= _T_134 @[el2_lib.scala 243:18] - node _T_135 = bits(io.trigger_pkt_any[0].tdata2, 11, 0) @[el2_lib.scala 243:29] - node _T_136 = andr(_T_135) @[el2_lib.scala 243:37] - node _T_137 = and(_T_136, _T_53) @[el2_lib.scala 243:42] - node _T_138 = bits(io.trigger_pkt_any[0].tdata2, 12, 12) @[el2_lib.scala 243:75] - node _T_139 = bits(lsu_match_data_0, 12, 12) @[el2_lib.scala 243:87] - node _T_140 = eq(_T_138, _T_139) @[el2_lib.scala 243:79] - node _T_141 = mux(_T_137, UInt<1>("h01"), _T_140) @[el2_lib.scala 243:24] - _T_48[12] <= _T_141 @[el2_lib.scala 243:18] - node _T_142 = bits(io.trigger_pkt_any[0].tdata2, 12, 0) @[el2_lib.scala 243:29] - node _T_143 = andr(_T_142) @[el2_lib.scala 243:37] - node _T_144 = and(_T_143, _T_53) @[el2_lib.scala 243:42] - node _T_145 = bits(io.trigger_pkt_any[0].tdata2, 13, 13) @[el2_lib.scala 243:75] - node _T_146 = bits(lsu_match_data_0, 13, 13) @[el2_lib.scala 243:87] - node _T_147 = eq(_T_145, _T_146) @[el2_lib.scala 243:79] - node _T_148 = mux(_T_144, UInt<1>("h01"), _T_147) @[el2_lib.scala 243:24] - _T_48[13] <= _T_148 @[el2_lib.scala 243:18] - node _T_149 = bits(io.trigger_pkt_any[0].tdata2, 13, 0) @[el2_lib.scala 243:29] - node _T_150 = andr(_T_149) @[el2_lib.scala 243:37] - node _T_151 = and(_T_150, _T_53) @[el2_lib.scala 243:42] - node _T_152 = bits(io.trigger_pkt_any[0].tdata2, 14, 14) @[el2_lib.scala 243:75] - node _T_153 = bits(lsu_match_data_0, 14, 14) @[el2_lib.scala 243:87] - node _T_154 = eq(_T_152, _T_153) @[el2_lib.scala 243:79] - node _T_155 = mux(_T_151, UInt<1>("h01"), _T_154) @[el2_lib.scala 243:24] - _T_48[14] <= _T_155 @[el2_lib.scala 243:18] - node _T_156 = bits(io.trigger_pkt_any[0].tdata2, 14, 0) @[el2_lib.scala 243:29] - node _T_157 = andr(_T_156) @[el2_lib.scala 243:37] - node _T_158 = and(_T_157, _T_53) @[el2_lib.scala 243:42] - node _T_159 = bits(io.trigger_pkt_any[0].tdata2, 15, 15) @[el2_lib.scala 243:75] - node _T_160 = bits(lsu_match_data_0, 15, 15) @[el2_lib.scala 243:87] - node _T_161 = eq(_T_159, _T_160) @[el2_lib.scala 243:79] - node _T_162 = mux(_T_158, UInt<1>("h01"), _T_161) @[el2_lib.scala 243:24] - _T_48[15] <= _T_162 @[el2_lib.scala 243:18] - node _T_163 = bits(io.trigger_pkt_any[0].tdata2, 15, 0) @[el2_lib.scala 243:29] - node _T_164 = andr(_T_163) @[el2_lib.scala 243:37] - node _T_165 = and(_T_164, _T_53) @[el2_lib.scala 243:42] - node _T_166 = bits(io.trigger_pkt_any[0].tdata2, 16, 16) @[el2_lib.scala 243:75] - node _T_167 = bits(lsu_match_data_0, 16, 16) @[el2_lib.scala 243:87] - node _T_168 = eq(_T_166, _T_167) @[el2_lib.scala 243:79] - node _T_169 = mux(_T_165, UInt<1>("h01"), _T_168) @[el2_lib.scala 243:24] - _T_48[16] <= _T_169 @[el2_lib.scala 243:18] - node _T_170 = bits(io.trigger_pkt_any[0].tdata2, 16, 0) @[el2_lib.scala 243:29] - node _T_171 = andr(_T_170) @[el2_lib.scala 243:37] - node _T_172 = and(_T_171, _T_53) @[el2_lib.scala 243:42] - node _T_173 = bits(io.trigger_pkt_any[0].tdata2, 17, 17) @[el2_lib.scala 243:75] - node _T_174 = bits(lsu_match_data_0, 17, 17) @[el2_lib.scala 243:87] - node _T_175 = eq(_T_173, _T_174) @[el2_lib.scala 243:79] - node _T_176 = mux(_T_172, UInt<1>("h01"), _T_175) @[el2_lib.scala 243:24] - _T_48[17] <= _T_176 @[el2_lib.scala 243:18] - node _T_177 = bits(io.trigger_pkt_any[0].tdata2, 17, 0) @[el2_lib.scala 243:29] - node _T_178 = andr(_T_177) @[el2_lib.scala 243:37] - node _T_179 = and(_T_178, _T_53) @[el2_lib.scala 243:42] - node _T_180 = bits(io.trigger_pkt_any[0].tdata2, 18, 18) @[el2_lib.scala 243:75] - node _T_181 = bits(lsu_match_data_0, 18, 18) @[el2_lib.scala 243:87] - node _T_182 = eq(_T_180, _T_181) @[el2_lib.scala 243:79] - node _T_183 = mux(_T_179, UInt<1>("h01"), _T_182) @[el2_lib.scala 243:24] - _T_48[18] <= _T_183 @[el2_lib.scala 243:18] - node _T_184 = bits(io.trigger_pkt_any[0].tdata2, 18, 0) @[el2_lib.scala 243:29] - node _T_185 = andr(_T_184) @[el2_lib.scala 243:37] - node _T_186 = and(_T_185, _T_53) @[el2_lib.scala 243:42] - node _T_187 = bits(io.trigger_pkt_any[0].tdata2, 19, 19) @[el2_lib.scala 243:75] - node _T_188 = bits(lsu_match_data_0, 19, 19) @[el2_lib.scala 243:87] - node _T_189 = eq(_T_187, _T_188) @[el2_lib.scala 243:79] - node _T_190 = mux(_T_186, UInt<1>("h01"), _T_189) @[el2_lib.scala 243:24] - _T_48[19] <= _T_190 @[el2_lib.scala 243:18] - node _T_191 = bits(io.trigger_pkt_any[0].tdata2, 19, 0) @[el2_lib.scala 243:29] - node _T_192 = andr(_T_191) @[el2_lib.scala 243:37] - node _T_193 = and(_T_192, _T_53) @[el2_lib.scala 243:42] - node _T_194 = bits(io.trigger_pkt_any[0].tdata2, 20, 20) @[el2_lib.scala 243:75] - node _T_195 = bits(lsu_match_data_0, 20, 20) @[el2_lib.scala 243:87] - node _T_196 = eq(_T_194, _T_195) @[el2_lib.scala 243:79] - node _T_197 = mux(_T_193, UInt<1>("h01"), _T_196) @[el2_lib.scala 243:24] - _T_48[20] <= _T_197 @[el2_lib.scala 243:18] - node _T_198 = bits(io.trigger_pkt_any[0].tdata2, 20, 0) @[el2_lib.scala 243:29] - node _T_199 = andr(_T_198) @[el2_lib.scala 243:37] - node _T_200 = and(_T_199, _T_53) @[el2_lib.scala 243:42] - node _T_201 = bits(io.trigger_pkt_any[0].tdata2, 21, 21) @[el2_lib.scala 243:75] - node _T_202 = bits(lsu_match_data_0, 21, 21) @[el2_lib.scala 243:87] - node _T_203 = eq(_T_201, _T_202) @[el2_lib.scala 243:79] - node _T_204 = mux(_T_200, UInt<1>("h01"), _T_203) @[el2_lib.scala 243:24] - _T_48[21] <= _T_204 @[el2_lib.scala 243:18] - node _T_205 = bits(io.trigger_pkt_any[0].tdata2, 21, 0) @[el2_lib.scala 243:29] - node _T_206 = andr(_T_205) @[el2_lib.scala 243:37] - node _T_207 = and(_T_206, _T_53) @[el2_lib.scala 243:42] - node _T_208 = bits(io.trigger_pkt_any[0].tdata2, 22, 22) @[el2_lib.scala 243:75] - node _T_209 = bits(lsu_match_data_0, 22, 22) @[el2_lib.scala 243:87] - node _T_210 = eq(_T_208, _T_209) @[el2_lib.scala 243:79] - node _T_211 = mux(_T_207, UInt<1>("h01"), _T_210) @[el2_lib.scala 243:24] - _T_48[22] <= _T_211 @[el2_lib.scala 243:18] - node _T_212 = bits(io.trigger_pkt_any[0].tdata2, 22, 0) @[el2_lib.scala 243:29] - node _T_213 = andr(_T_212) @[el2_lib.scala 243:37] - node _T_214 = and(_T_213, _T_53) @[el2_lib.scala 243:42] - node _T_215 = bits(io.trigger_pkt_any[0].tdata2, 23, 23) @[el2_lib.scala 243:75] - node _T_216 = bits(lsu_match_data_0, 23, 23) @[el2_lib.scala 243:87] - node _T_217 = eq(_T_215, _T_216) @[el2_lib.scala 243:79] - node _T_218 = mux(_T_214, UInt<1>("h01"), _T_217) @[el2_lib.scala 243:24] - _T_48[23] <= _T_218 @[el2_lib.scala 243:18] - node _T_219 = bits(io.trigger_pkt_any[0].tdata2, 23, 0) @[el2_lib.scala 243:29] - node _T_220 = andr(_T_219) @[el2_lib.scala 243:37] - node _T_221 = and(_T_220, _T_53) @[el2_lib.scala 243:42] - node _T_222 = bits(io.trigger_pkt_any[0].tdata2, 24, 24) @[el2_lib.scala 243:75] - node _T_223 = bits(lsu_match_data_0, 24, 24) @[el2_lib.scala 243:87] - node _T_224 = eq(_T_222, _T_223) @[el2_lib.scala 243:79] - node _T_225 = mux(_T_221, UInt<1>("h01"), _T_224) @[el2_lib.scala 243:24] - _T_48[24] <= _T_225 @[el2_lib.scala 243:18] - node _T_226 = bits(io.trigger_pkt_any[0].tdata2, 24, 0) @[el2_lib.scala 243:29] - node _T_227 = andr(_T_226) @[el2_lib.scala 243:37] - node _T_228 = and(_T_227, _T_53) @[el2_lib.scala 243:42] - node _T_229 = bits(io.trigger_pkt_any[0].tdata2, 25, 25) @[el2_lib.scala 243:75] - node _T_230 = bits(lsu_match_data_0, 25, 25) @[el2_lib.scala 243:87] - node _T_231 = eq(_T_229, _T_230) @[el2_lib.scala 243:79] - node _T_232 = mux(_T_228, UInt<1>("h01"), _T_231) @[el2_lib.scala 243:24] - _T_48[25] <= _T_232 @[el2_lib.scala 243:18] - node _T_233 = bits(io.trigger_pkt_any[0].tdata2, 25, 0) @[el2_lib.scala 243:29] - node _T_234 = andr(_T_233) @[el2_lib.scala 243:37] - node _T_235 = and(_T_234, _T_53) @[el2_lib.scala 243:42] - node _T_236 = bits(io.trigger_pkt_any[0].tdata2, 26, 26) @[el2_lib.scala 243:75] - node _T_237 = bits(lsu_match_data_0, 26, 26) @[el2_lib.scala 243:87] - node _T_238 = eq(_T_236, _T_237) @[el2_lib.scala 243:79] - node _T_239 = mux(_T_235, UInt<1>("h01"), _T_238) @[el2_lib.scala 243:24] - _T_48[26] <= _T_239 @[el2_lib.scala 243:18] - node _T_240 = bits(io.trigger_pkt_any[0].tdata2, 26, 0) @[el2_lib.scala 243:29] - node _T_241 = andr(_T_240) @[el2_lib.scala 243:37] - node _T_242 = and(_T_241, _T_53) @[el2_lib.scala 243:42] - node _T_243 = bits(io.trigger_pkt_any[0].tdata2, 27, 27) @[el2_lib.scala 243:75] - node _T_244 = bits(lsu_match_data_0, 27, 27) @[el2_lib.scala 243:87] - node _T_245 = eq(_T_243, _T_244) @[el2_lib.scala 243:79] - node _T_246 = mux(_T_242, UInt<1>("h01"), _T_245) @[el2_lib.scala 243:24] - _T_48[27] <= _T_246 @[el2_lib.scala 243:18] - node _T_247 = bits(io.trigger_pkt_any[0].tdata2, 27, 0) @[el2_lib.scala 243:29] - node _T_248 = andr(_T_247) @[el2_lib.scala 243:37] - node _T_249 = and(_T_248, _T_53) @[el2_lib.scala 243:42] - node _T_250 = bits(io.trigger_pkt_any[0].tdata2, 28, 28) @[el2_lib.scala 243:75] - node _T_251 = bits(lsu_match_data_0, 28, 28) @[el2_lib.scala 243:87] - node _T_252 = eq(_T_250, _T_251) @[el2_lib.scala 243:79] - node _T_253 = mux(_T_249, UInt<1>("h01"), _T_252) @[el2_lib.scala 243:24] - _T_48[28] <= _T_253 @[el2_lib.scala 243:18] - node _T_254 = bits(io.trigger_pkt_any[0].tdata2, 28, 0) @[el2_lib.scala 243:29] - node _T_255 = andr(_T_254) @[el2_lib.scala 243:37] - node _T_256 = and(_T_255, _T_53) @[el2_lib.scala 243:42] - node _T_257 = bits(io.trigger_pkt_any[0].tdata2, 29, 29) @[el2_lib.scala 243:75] - node _T_258 = bits(lsu_match_data_0, 29, 29) @[el2_lib.scala 243:87] - node _T_259 = eq(_T_257, _T_258) @[el2_lib.scala 243:79] - node _T_260 = mux(_T_256, UInt<1>("h01"), _T_259) @[el2_lib.scala 243:24] - _T_48[29] <= _T_260 @[el2_lib.scala 243:18] - node _T_261 = bits(io.trigger_pkt_any[0].tdata2, 29, 0) @[el2_lib.scala 243:29] - node _T_262 = andr(_T_261) @[el2_lib.scala 243:37] - node _T_263 = and(_T_262, _T_53) @[el2_lib.scala 243:42] - node _T_264 = bits(io.trigger_pkt_any[0].tdata2, 30, 30) @[el2_lib.scala 243:75] - node _T_265 = bits(lsu_match_data_0, 30, 30) @[el2_lib.scala 243:87] - node _T_266 = eq(_T_264, _T_265) @[el2_lib.scala 243:79] - node _T_267 = mux(_T_263, UInt<1>("h01"), _T_266) @[el2_lib.scala 243:24] - _T_48[30] <= _T_267 @[el2_lib.scala 243:18] - node _T_268 = bits(io.trigger_pkt_any[0].tdata2, 30, 0) @[el2_lib.scala 243:29] - node _T_269 = andr(_T_268) @[el2_lib.scala 243:37] - node _T_270 = and(_T_269, _T_53) @[el2_lib.scala 243:42] - node _T_271 = bits(io.trigger_pkt_any[0].tdata2, 31, 31) @[el2_lib.scala 243:75] - node _T_272 = bits(lsu_match_data_0, 31, 31) @[el2_lib.scala 243:87] - node _T_273 = eq(_T_271, _T_272) @[el2_lib.scala 243:79] - node _T_274 = mux(_T_270, UInt<1>("h01"), _T_273) @[el2_lib.scala 243:24] - _T_48[31] <= _T_274 @[el2_lib.scala 243:18] - node _T_275 = cat(_T_48[1], _T_48[0]) @[el2_lib.scala 244:14] - node _T_276 = cat(_T_48[3], _T_48[2]) @[el2_lib.scala 244:14] - node _T_277 = cat(_T_276, _T_275) @[el2_lib.scala 244:14] - node _T_278 = cat(_T_48[5], _T_48[4]) @[el2_lib.scala 244:14] - node _T_279 = cat(_T_48[7], _T_48[6]) @[el2_lib.scala 244:14] - node _T_280 = cat(_T_279, _T_278) @[el2_lib.scala 244:14] - node _T_281 = cat(_T_280, _T_277) @[el2_lib.scala 244:14] - node _T_282 = cat(_T_48[9], _T_48[8]) @[el2_lib.scala 244:14] - node _T_283 = cat(_T_48[11], _T_48[10]) @[el2_lib.scala 244:14] - node _T_284 = cat(_T_283, _T_282) @[el2_lib.scala 244:14] - node _T_285 = cat(_T_48[13], _T_48[12]) @[el2_lib.scala 244:14] - node _T_286 = cat(_T_48[15], _T_48[14]) @[el2_lib.scala 244:14] - node _T_287 = cat(_T_286, _T_285) @[el2_lib.scala 244:14] - node _T_288 = cat(_T_287, _T_284) @[el2_lib.scala 244:14] - node _T_289 = cat(_T_288, _T_281) @[el2_lib.scala 244:14] - node _T_290 = cat(_T_48[17], _T_48[16]) @[el2_lib.scala 244:14] - node _T_291 = cat(_T_48[19], _T_48[18]) @[el2_lib.scala 244:14] - node _T_292 = cat(_T_291, _T_290) @[el2_lib.scala 244:14] - node _T_293 = cat(_T_48[21], _T_48[20]) @[el2_lib.scala 244:14] - node _T_294 = cat(_T_48[23], _T_48[22]) @[el2_lib.scala 244:14] - node _T_295 = cat(_T_294, _T_293) @[el2_lib.scala 244:14] - node _T_296 = cat(_T_295, _T_292) @[el2_lib.scala 244:14] - node _T_297 = cat(_T_48[25], _T_48[24]) @[el2_lib.scala 244:14] - node _T_298 = cat(_T_48[27], _T_48[26]) @[el2_lib.scala 244:14] - node _T_299 = cat(_T_298, _T_297) @[el2_lib.scala 244:14] - node _T_300 = cat(_T_48[29], _T_48[28]) @[el2_lib.scala 244:14] - node _T_301 = cat(_T_48[31], _T_48[30]) @[el2_lib.scala 244:14] - node _T_302 = cat(_T_301, _T_300) @[el2_lib.scala 244:14] - node _T_303 = cat(_T_302, _T_299) @[el2_lib.scala 244:14] - node _T_304 = cat(_T_303, _T_296) @[el2_lib.scala 244:14] - node _T_305 = cat(_T_304, _T_289) @[el2_lib.scala 244:14] - node _T_306 = andr(_T_305) @[el2_lib.scala 244:21] - node _T_307 = and(_T_46, _T_306) @[el2_lsu_trigger.scala 19:87] - node _T_308 = eq(io.lsu_pkt_m.dma, UInt<1>("h00")) @[el2_lsu_trigger.scala 18:71] - node _T_309 = and(io.lsu_pkt_m.valid, _T_308) @[el2_lsu_trigger.scala 18:69] - node _T_310 = and(io.trigger_pkt_any[1].store, io.lsu_pkt_m.store) @[el2_lsu_trigger.scala 18:121] - node _T_311 = and(io.trigger_pkt_any[1].load, io.lsu_pkt_m.load) @[el2_lsu_trigger.scala 19:33] - node _T_312 = eq(io.trigger_pkt_any[1].select, UInt<1>("h00")) @[el2_lsu_trigger.scala 19:55] - node _T_313 = and(_T_311, _T_312) @[el2_lsu_trigger.scala 19:53] - node _T_314 = or(_T_310, _T_313) @[el2_lsu_trigger.scala 18:142] - node _T_315 = and(_T_309, _T_314) @[el2_lsu_trigger.scala 18:89] - node _T_316 = bits(io.trigger_pkt_any[1].match_, 0, 0) @[el2_lsu_trigger.scala 20:106] - wire _T_317 : UInt<1>[32] @[el2_lib.scala 239:24] - node _T_318 = bits(_T_316, 0, 0) @[el2_lib.scala 240:37] - node _T_319 = bits(io.trigger_pkt_any[1].tdata2, 31, 0) @[el2_lib.scala 240:53] - node _T_320 = andr(_T_319) @[el2_lib.scala 240:73] - node _T_321 = not(_T_320) @[el2_lib.scala 240:47] - node _T_322 = and(_T_318, _T_321) @[el2_lib.scala 240:44] - node _T_323 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[el2_lib.scala 241:48] - node _T_324 = bits(lsu_match_data_1, 0, 0) @[el2_lib.scala 241:60] - node _T_325 = eq(_T_323, _T_324) @[el2_lib.scala 241:52] - node _T_326 = or(_T_322, _T_325) @[el2_lib.scala 241:41] - _T_317[0] <= _T_326 @[el2_lib.scala 241:18] - node _T_327 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[el2_lib.scala 243:29] - node _T_328 = andr(_T_327) @[el2_lib.scala 243:37] - node _T_329 = and(_T_328, _T_322) @[el2_lib.scala 243:42] - node _T_330 = bits(io.trigger_pkt_any[1].tdata2, 1, 1) @[el2_lib.scala 243:75] - node _T_331 = bits(lsu_match_data_1, 1, 1) @[el2_lib.scala 243:87] - node _T_332 = eq(_T_330, _T_331) @[el2_lib.scala 243:79] - node _T_333 = mux(_T_329, UInt<1>("h01"), _T_332) @[el2_lib.scala 243:24] - _T_317[1] <= _T_333 @[el2_lib.scala 243:18] - node _T_334 = bits(io.trigger_pkt_any[1].tdata2, 1, 0) @[el2_lib.scala 243:29] - node _T_335 = andr(_T_334) @[el2_lib.scala 243:37] - node _T_336 = and(_T_335, _T_322) @[el2_lib.scala 243:42] - node _T_337 = bits(io.trigger_pkt_any[1].tdata2, 2, 2) @[el2_lib.scala 243:75] - node _T_338 = bits(lsu_match_data_1, 2, 2) @[el2_lib.scala 243:87] - node _T_339 = eq(_T_337, _T_338) @[el2_lib.scala 243:79] - node _T_340 = mux(_T_336, UInt<1>("h01"), _T_339) @[el2_lib.scala 243:24] - _T_317[2] <= _T_340 @[el2_lib.scala 243:18] - node _T_341 = bits(io.trigger_pkt_any[1].tdata2, 2, 0) @[el2_lib.scala 243:29] - node _T_342 = andr(_T_341) @[el2_lib.scala 243:37] - node _T_343 = and(_T_342, _T_322) @[el2_lib.scala 243:42] - node _T_344 = bits(io.trigger_pkt_any[1].tdata2, 3, 3) @[el2_lib.scala 243:75] - node _T_345 = bits(lsu_match_data_1, 3, 3) @[el2_lib.scala 243:87] - node _T_346 = eq(_T_344, _T_345) @[el2_lib.scala 243:79] - node _T_347 = mux(_T_343, UInt<1>("h01"), _T_346) @[el2_lib.scala 243:24] - _T_317[3] <= _T_347 @[el2_lib.scala 243:18] - node _T_348 = bits(io.trigger_pkt_any[1].tdata2, 3, 0) @[el2_lib.scala 243:29] - node _T_349 = andr(_T_348) @[el2_lib.scala 243:37] - node _T_350 = and(_T_349, _T_322) @[el2_lib.scala 243:42] - node _T_351 = bits(io.trigger_pkt_any[1].tdata2, 4, 4) @[el2_lib.scala 243:75] - node _T_352 = bits(lsu_match_data_1, 4, 4) @[el2_lib.scala 243:87] - node _T_353 = eq(_T_351, _T_352) @[el2_lib.scala 243:79] - node _T_354 = mux(_T_350, UInt<1>("h01"), _T_353) @[el2_lib.scala 243:24] - _T_317[4] <= _T_354 @[el2_lib.scala 243:18] - node _T_355 = bits(io.trigger_pkt_any[1].tdata2, 4, 0) @[el2_lib.scala 243:29] - node _T_356 = andr(_T_355) @[el2_lib.scala 243:37] - node _T_357 = and(_T_356, _T_322) @[el2_lib.scala 243:42] - node _T_358 = bits(io.trigger_pkt_any[1].tdata2, 5, 5) @[el2_lib.scala 243:75] - node _T_359 = bits(lsu_match_data_1, 5, 5) @[el2_lib.scala 243:87] - node _T_360 = eq(_T_358, _T_359) @[el2_lib.scala 243:79] - node _T_361 = mux(_T_357, UInt<1>("h01"), _T_360) @[el2_lib.scala 243:24] - _T_317[5] <= _T_361 @[el2_lib.scala 243:18] - node _T_362 = bits(io.trigger_pkt_any[1].tdata2, 5, 0) @[el2_lib.scala 243:29] - node _T_363 = andr(_T_362) @[el2_lib.scala 243:37] - node _T_364 = and(_T_363, _T_322) @[el2_lib.scala 243:42] - node _T_365 = bits(io.trigger_pkt_any[1].tdata2, 6, 6) @[el2_lib.scala 243:75] - node _T_366 = bits(lsu_match_data_1, 6, 6) @[el2_lib.scala 243:87] - node _T_367 = eq(_T_365, _T_366) @[el2_lib.scala 243:79] - node _T_368 = mux(_T_364, UInt<1>("h01"), _T_367) @[el2_lib.scala 243:24] - _T_317[6] <= _T_368 @[el2_lib.scala 243:18] - node _T_369 = bits(io.trigger_pkt_any[1].tdata2, 6, 0) @[el2_lib.scala 243:29] - node _T_370 = andr(_T_369) @[el2_lib.scala 243:37] - node _T_371 = and(_T_370, _T_322) @[el2_lib.scala 243:42] - node _T_372 = bits(io.trigger_pkt_any[1].tdata2, 7, 7) @[el2_lib.scala 243:75] - node _T_373 = bits(lsu_match_data_1, 7, 7) @[el2_lib.scala 243:87] - node _T_374 = eq(_T_372, _T_373) @[el2_lib.scala 243:79] - node _T_375 = mux(_T_371, UInt<1>("h01"), _T_374) @[el2_lib.scala 243:24] - _T_317[7] <= _T_375 @[el2_lib.scala 243:18] - node _T_376 = bits(io.trigger_pkt_any[1].tdata2, 7, 0) @[el2_lib.scala 243:29] - node _T_377 = andr(_T_376) @[el2_lib.scala 243:37] - node _T_378 = and(_T_377, _T_322) @[el2_lib.scala 243:42] - node _T_379 = bits(io.trigger_pkt_any[1].tdata2, 8, 8) @[el2_lib.scala 243:75] - node _T_380 = bits(lsu_match_data_1, 8, 8) @[el2_lib.scala 243:87] - node _T_381 = eq(_T_379, _T_380) @[el2_lib.scala 243:79] - node _T_382 = mux(_T_378, UInt<1>("h01"), _T_381) @[el2_lib.scala 243:24] - _T_317[8] <= _T_382 @[el2_lib.scala 243:18] - node _T_383 = bits(io.trigger_pkt_any[1].tdata2, 8, 0) @[el2_lib.scala 243:29] - node _T_384 = andr(_T_383) @[el2_lib.scala 243:37] - node _T_385 = and(_T_384, _T_322) @[el2_lib.scala 243:42] - node _T_386 = bits(io.trigger_pkt_any[1].tdata2, 9, 9) @[el2_lib.scala 243:75] - node _T_387 = bits(lsu_match_data_1, 9, 9) @[el2_lib.scala 243:87] - node _T_388 = eq(_T_386, _T_387) @[el2_lib.scala 243:79] - node _T_389 = mux(_T_385, UInt<1>("h01"), _T_388) @[el2_lib.scala 243:24] - _T_317[9] <= _T_389 @[el2_lib.scala 243:18] - node _T_390 = bits(io.trigger_pkt_any[1].tdata2, 9, 0) @[el2_lib.scala 243:29] - node _T_391 = andr(_T_390) @[el2_lib.scala 243:37] - node _T_392 = and(_T_391, _T_322) @[el2_lib.scala 243:42] - node _T_393 = bits(io.trigger_pkt_any[1].tdata2, 10, 10) @[el2_lib.scala 243:75] - node _T_394 = bits(lsu_match_data_1, 10, 10) @[el2_lib.scala 243:87] - node _T_395 = eq(_T_393, _T_394) @[el2_lib.scala 243:79] - node _T_396 = mux(_T_392, UInt<1>("h01"), _T_395) @[el2_lib.scala 243:24] - _T_317[10] <= _T_396 @[el2_lib.scala 243:18] - node _T_397 = bits(io.trigger_pkt_any[1].tdata2, 10, 0) @[el2_lib.scala 243:29] - node _T_398 = andr(_T_397) @[el2_lib.scala 243:37] - node _T_399 = and(_T_398, _T_322) @[el2_lib.scala 243:42] - node _T_400 = bits(io.trigger_pkt_any[1].tdata2, 11, 11) @[el2_lib.scala 243:75] - node _T_401 = bits(lsu_match_data_1, 11, 11) @[el2_lib.scala 243:87] - node _T_402 = eq(_T_400, _T_401) @[el2_lib.scala 243:79] - node _T_403 = mux(_T_399, UInt<1>("h01"), _T_402) @[el2_lib.scala 243:24] - _T_317[11] <= _T_403 @[el2_lib.scala 243:18] - node _T_404 = bits(io.trigger_pkt_any[1].tdata2, 11, 0) @[el2_lib.scala 243:29] - node _T_405 = andr(_T_404) @[el2_lib.scala 243:37] - node _T_406 = and(_T_405, _T_322) @[el2_lib.scala 243:42] - node _T_407 = bits(io.trigger_pkt_any[1].tdata2, 12, 12) @[el2_lib.scala 243:75] - node _T_408 = bits(lsu_match_data_1, 12, 12) @[el2_lib.scala 243:87] - node _T_409 = eq(_T_407, _T_408) @[el2_lib.scala 243:79] - node _T_410 = mux(_T_406, UInt<1>("h01"), _T_409) @[el2_lib.scala 243:24] - _T_317[12] <= _T_410 @[el2_lib.scala 243:18] - node _T_411 = bits(io.trigger_pkt_any[1].tdata2, 12, 0) @[el2_lib.scala 243:29] - node _T_412 = andr(_T_411) @[el2_lib.scala 243:37] - node _T_413 = and(_T_412, _T_322) @[el2_lib.scala 243:42] - node _T_414 = bits(io.trigger_pkt_any[1].tdata2, 13, 13) @[el2_lib.scala 243:75] - node _T_415 = bits(lsu_match_data_1, 13, 13) @[el2_lib.scala 243:87] - node _T_416 = eq(_T_414, _T_415) @[el2_lib.scala 243:79] - node _T_417 = mux(_T_413, UInt<1>("h01"), _T_416) @[el2_lib.scala 243:24] - _T_317[13] <= _T_417 @[el2_lib.scala 243:18] - node _T_418 = bits(io.trigger_pkt_any[1].tdata2, 13, 0) @[el2_lib.scala 243:29] - node _T_419 = andr(_T_418) @[el2_lib.scala 243:37] - node _T_420 = and(_T_419, _T_322) @[el2_lib.scala 243:42] - node _T_421 = bits(io.trigger_pkt_any[1].tdata2, 14, 14) @[el2_lib.scala 243:75] - node _T_422 = bits(lsu_match_data_1, 14, 14) @[el2_lib.scala 243:87] - node _T_423 = eq(_T_421, _T_422) @[el2_lib.scala 243:79] - node _T_424 = mux(_T_420, UInt<1>("h01"), _T_423) @[el2_lib.scala 243:24] - _T_317[14] <= _T_424 @[el2_lib.scala 243:18] - node _T_425 = bits(io.trigger_pkt_any[1].tdata2, 14, 0) @[el2_lib.scala 243:29] - node _T_426 = andr(_T_425) @[el2_lib.scala 243:37] - node _T_427 = and(_T_426, _T_322) @[el2_lib.scala 243:42] - node _T_428 = bits(io.trigger_pkt_any[1].tdata2, 15, 15) @[el2_lib.scala 243:75] - node _T_429 = bits(lsu_match_data_1, 15, 15) @[el2_lib.scala 243:87] - node _T_430 = eq(_T_428, _T_429) @[el2_lib.scala 243:79] - node _T_431 = mux(_T_427, UInt<1>("h01"), _T_430) @[el2_lib.scala 243:24] - _T_317[15] <= _T_431 @[el2_lib.scala 243:18] - node _T_432 = bits(io.trigger_pkt_any[1].tdata2, 15, 0) @[el2_lib.scala 243:29] - node _T_433 = andr(_T_432) @[el2_lib.scala 243:37] - node _T_434 = and(_T_433, _T_322) @[el2_lib.scala 243:42] - node _T_435 = bits(io.trigger_pkt_any[1].tdata2, 16, 16) @[el2_lib.scala 243:75] - node _T_436 = bits(lsu_match_data_1, 16, 16) @[el2_lib.scala 243:87] - node _T_437 = eq(_T_435, _T_436) @[el2_lib.scala 243:79] - node _T_438 = mux(_T_434, UInt<1>("h01"), _T_437) @[el2_lib.scala 243:24] - _T_317[16] <= _T_438 @[el2_lib.scala 243:18] - node _T_439 = bits(io.trigger_pkt_any[1].tdata2, 16, 0) @[el2_lib.scala 243:29] - node _T_440 = andr(_T_439) @[el2_lib.scala 243:37] - node _T_441 = and(_T_440, _T_322) @[el2_lib.scala 243:42] - node _T_442 = bits(io.trigger_pkt_any[1].tdata2, 17, 17) @[el2_lib.scala 243:75] - node _T_443 = bits(lsu_match_data_1, 17, 17) @[el2_lib.scala 243:87] - node _T_444 = eq(_T_442, _T_443) @[el2_lib.scala 243:79] - node _T_445 = mux(_T_441, UInt<1>("h01"), _T_444) @[el2_lib.scala 243:24] - _T_317[17] <= _T_445 @[el2_lib.scala 243:18] - node _T_446 = bits(io.trigger_pkt_any[1].tdata2, 17, 0) @[el2_lib.scala 243:29] - node _T_447 = andr(_T_446) @[el2_lib.scala 243:37] - node _T_448 = and(_T_447, _T_322) @[el2_lib.scala 243:42] - node _T_449 = bits(io.trigger_pkt_any[1].tdata2, 18, 18) @[el2_lib.scala 243:75] - node _T_450 = bits(lsu_match_data_1, 18, 18) @[el2_lib.scala 243:87] - node _T_451 = eq(_T_449, _T_450) @[el2_lib.scala 243:79] - node _T_452 = mux(_T_448, UInt<1>("h01"), _T_451) @[el2_lib.scala 243:24] - _T_317[18] <= _T_452 @[el2_lib.scala 243:18] - node _T_453 = bits(io.trigger_pkt_any[1].tdata2, 18, 0) @[el2_lib.scala 243:29] - node _T_454 = andr(_T_453) @[el2_lib.scala 243:37] - node _T_455 = and(_T_454, _T_322) @[el2_lib.scala 243:42] - node _T_456 = bits(io.trigger_pkt_any[1].tdata2, 19, 19) @[el2_lib.scala 243:75] - node _T_457 = bits(lsu_match_data_1, 19, 19) @[el2_lib.scala 243:87] - node _T_458 = eq(_T_456, _T_457) @[el2_lib.scala 243:79] - node _T_459 = mux(_T_455, UInt<1>("h01"), _T_458) @[el2_lib.scala 243:24] - _T_317[19] <= _T_459 @[el2_lib.scala 243:18] - node _T_460 = bits(io.trigger_pkt_any[1].tdata2, 19, 0) @[el2_lib.scala 243:29] - node _T_461 = andr(_T_460) @[el2_lib.scala 243:37] - node _T_462 = and(_T_461, _T_322) @[el2_lib.scala 243:42] - node _T_463 = bits(io.trigger_pkt_any[1].tdata2, 20, 20) @[el2_lib.scala 243:75] - node _T_464 = bits(lsu_match_data_1, 20, 20) @[el2_lib.scala 243:87] - node _T_465 = eq(_T_463, _T_464) @[el2_lib.scala 243:79] - node _T_466 = mux(_T_462, UInt<1>("h01"), _T_465) @[el2_lib.scala 243:24] - _T_317[20] <= _T_466 @[el2_lib.scala 243:18] - node _T_467 = bits(io.trigger_pkt_any[1].tdata2, 20, 0) @[el2_lib.scala 243:29] - node _T_468 = andr(_T_467) @[el2_lib.scala 243:37] - node _T_469 = and(_T_468, _T_322) @[el2_lib.scala 243:42] - node _T_470 = bits(io.trigger_pkt_any[1].tdata2, 21, 21) @[el2_lib.scala 243:75] - node _T_471 = bits(lsu_match_data_1, 21, 21) @[el2_lib.scala 243:87] - node _T_472 = eq(_T_470, _T_471) @[el2_lib.scala 243:79] - node _T_473 = mux(_T_469, UInt<1>("h01"), _T_472) @[el2_lib.scala 243:24] - _T_317[21] <= _T_473 @[el2_lib.scala 243:18] - node _T_474 = bits(io.trigger_pkt_any[1].tdata2, 21, 0) @[el2_lib.scala 243:29] - node _T_475 = andr(_T_474) @[el2_lib.scala 243:37] - node _T_476 = and(_T_475, _T_322) @[el2_lib.scala 243:42] - node _T_477 = bits(io.trigger_pkt_any[1].tdata2, 22, 22) @[el2_lib.scala 243:75] - node _T_478 = bits(lsu_match_data_1, 22, 22) @[el2_lib.scala 243:87] - node _T_479 = eq(_T_477, _T_478) @[el2_lib.scala 243:79] - node _T_480 = mux(_T_476, UInt<1>("h01"), _T_479) @[el2_lib.scala 243:24] - _T_317[22] <= _T_480 @[el2_lib.scala 243:18] - node _T_481 = bits(io.trigger_pkt_any[1].tdata2, 22, 0) @[el2_lib.scala 243:29] - node _T_482 = andr(_T_481) @[el2_lib.scala 243:37] - node _T_483 = and(_T_482, _T_322) @[el2_lib.scala 243:42] - node _T_484 = bits(io.trigger_pkt_any[1].tdata2, 23, 23) @[el2_lib.scala 243:75] - node _T_485 = bits(lsu_match_data_1, 23, 23) @[el2_lib.scala 243:87] - node _T_486 = eq(_T_484, _T_485) @[el2_lib.scala 243:79] - node _T_487 = mux(_T_483, UInt<1>("h01"), _T_486) @[el2_lib.scala 243:24] - _T_317[23] <= _T_487 @[el2_lib.scala 243:18] - node _T_488 = bits(io.trigger_pkt_any[1].tdata2, 23, 0) @[el2_lib.scala 243:29] - node _T_489 = andr(_T_488) @[el2_lib.scala 243:37] - node _T_490 = and(_T_489, _T_322) @[el2_lib.scala 243:42] - node _T_491 = bits(io.trigger_pkt_any[1].tdata2, 24, 24) @[el2_lib.scala 243:75] - node _T_492 = bits(lsu_match_data_1, 24, 24) @[el2_lib.scala 243:87] - node _T_493 = eq(_T_491, _T_492) @[el2_lib.scala 243:79] - node _T_494 = mux(_T_490, UInt<1>("h01"), _T_493) @[el2_lib.scala 243:24] - _T_317[24] <= _T_494 @[el2_lib.scala 243:18] - node _T_495 = bits(io.trigger_pkt_any[1].tdata2, 24, 0) @[el2_lib.scala 243:29] - node _T_496 = andr(_T_495) @[el2_lib.scala 243:37] - node _T_497 = and(_T_496, _T_322) @[el2_lib.scala 243:42] - node _T_498 = bits(io.trigger_pkt_any[1].tdata2, 25, 25) @[el2_lib.scala 243:75] - node _T_499 = bits(lsu_match_data_1, 25, 25) @[el2_lib.scala 243:87] - node _T_500 = eq(_T_498, _T_499) @[el2_lib.scala 243:79] - node _T_501 = mux(_T_497, UInt<1>("h01"), _T_500) @[el2_lib.scala 243:24] - _T_317[25] <= _T_501 @[el2_lib.scala 243:18] - node _T_502 = bits(io.trigger_pkt_any[1].tdata2, 25, 0) @[el2_lib.scala 243:29] - node _T_503 = andr(_T_502) @[el2_lib.scala 243:37] - node _T_504 = and(_T_503, _T_322) @[el2_lib.scala 243:42] - node _T_505 = bits(io.trigger_pkt_any[1].tdata2, 26, 26) @[el2_lib.scala 243:75] - node _T_506 = bits(lsu_match_data_1, 26, 26) @[el2_lib.scala 243:87] - node _T_507 = eq(_T_505, _T_506) @[el2_lib.scala 243:79] - node _T_508 = mux(_T_504, UInt<1>("h01"), _T_507) @[el2_lib.scala 243:24] - _T_317[26] <= _T_508 @[el2_lib.scala 243:18] - node _T_509 = bits(io.trigger_pkt_any[1].tdata2, 26, 0) @[el2_lib.scala 243:29] - node _T_510 = andr(_T_509) @[el2_lib.scala 243:37] - node _T_511 = and(_T_510, _T_322) @[el2_lib.scala 243:42] - node _T_512 = bits(io.trigger_pkt_any[1].tdata2, 27, 27) @[el2_lib.scala 243:75] - node _T_513 = bits(lsu_match_data_1, 27, 27) @[el2_lib.scala 243:87] - node _T_514 = eq(_T_512, _T_513) @[el2_lib.scala 243:79] - node _T_515 = mux(_T_511, UInt<1>("h01"), _T_514) @[el2_lib.scala 243:24] - _T_317[27] <= _T_515 @[el2_lib.scala 243:18] - node _T_516 = bits(io.trigger_pkt_any[1].tdata2, 27, 0) @[el2_lib.scala 243:29] - node _T_517 = andr(_T_516) @[el2_lib.scala 243:37] - node _T_518 = and(_T_517, _T_322) @[el2_lib.scala 243:42] - node _T_519 = bits(io.trigger_pkt_any[1].tdata2, 28, 28) @[el2_lib.scala 243:75] - node _T_520 = bits(lsu_match_data_1, 28, 28) @[el2_lib.scala 243:87] - node _T_521 = eq(_T_519, _T_520) @[el2_lib.scala 243:79] - node _T_522 = mux(_T_518, UInt<1>("h01"), _T_521) @[el2_lib.scala 243:24] - _T_317[28] <= _T_522 @[el2_lib.scala 243:18] - node _T_523 = bits(io.trigger_pkt_any[1].tdata2, 28, 0) @[el2_lib.scala 243:29] - node _T_524 = andr(_T_523) @[el2_lib.scala 243:37] - node _T_525 = and(_T_524, _T_322) @[el2_lib.scala 243:42] - node _T_526 = bits(io.trigger_pkt_any[1].tdata2, 29, 29) @[el2_lib.scala 243:75] - node _T_527 = bits(lsu_match_data_1, 29, 29) @[el2_lib.scala 243:87] - node _T_528 = eq(_T_526, _T_527) @[el2_lib.scala 243:79] - node _T_529 = mux(_T_525, UInt<1>("h01"), _T_528) @[el2_lib.scala 243:24] - _T_317[29] <= _T_529 @[el2_lib.scala 243:18] - node _T_530 = bits(io.trigger_pkt_any[1].tdata2, 29, 0) @[el2_lib.scala 243:29] - node _T_531 = andr(_T_530) @[el2_lib.scala 243:37] - node _T_532 = and(_T_531, _T_322) @[el2_lib.scala 243:42] - node _T_533 = bits(io.trigger_pkt_any[1].tdata2, 30, 30) @[el2_lib.scala 243:75] - node _T_534 = bits(lsu_match_data_1, 30, 30) @[el2_lib.scala 243:87] - node _T_535 = eq(_T_533, _T_534) @[el2_lib.scala 243:79] - node _T_536 = mux(_T_532, UInt<1>("h01"), _T_535) @[el2_lib.scala 243:24] - _T_317[30] <= _T_536 @[el2_lib.scala 243:18] - node _T_537 = bits(io.trigger_pkt_any[1].tdata2, 30, 0) @[el2_lib.scala 243:29] - node _T_538 = andr(_T_537) @[el2_lib.scala 243:37] - node _T_539 = and(_T_538, _T_322) @[el2_lib.scala 243:42] - node _T_540 = bits(io.trigger_pkt_any[1].tdata2, 31, 31) @[el2_lib.scala 243:75] - node _T_541 = bits(lsu_match_data_1, 31, 31) @[el2_lib.scala 243:87] - node _T_542 = eq(_T_540, _T_541) @[el2_lib.scala 243:79] - node _T_543 = mux(_T_539, UInt<1>("h01"), _T_542) @[el2_lib.scala 243:24] - _T_317[31] <= _T_543 @[el2_lib.scala 243:18] - node _T_544 = cat(_T_317[1], _T_317[0]) @[el2_lib.scala 244:14] - node _T_545 = cat(_T_317[3], _T_317[2]) @[el2_lib.scala 244:14] - node _T_546 = cat(_T_545, _T_544) @[el2_lib.scala 244:14] - node _T_547 = cat(_T_317[5], _T_317[4]) @[el2_lib.scala 244:14] - node _T_548 = cat(_T_317[7], _T_317[6]) @[el2_lib.scala 244:14] - node _T_549 = cat(_T_548, _T_547) @[el2_lib.scala 244:14] - node _T_550 = cat(_T_549, _T_546) @[el2_lib.scala 244:14] - node _T_551 = cat(_T_317[9], _T_317[8]) @[el2_lib.scala 244:14] - node _T_552 = cat(_T_317[11], _T_317[10]) @[el2_lib.scala 244:14] - node _T_553 = cat(_T_552, _T_551) @[el2_lib.scala 244:14] - node _T_554 = cat(_T_317[13], _T_317[12]) @[el2_lib.scala 244:14] - node _T_555 = cat(_T_317[15], _T_317[14]) @[el2_lib.scala 244:14] - node _T_556 = cat(_T_555, _T_554) @[el2_lib.scala 244:14] - node _T_557 = cat(_T_556, _T_553) @[el2_lib.scala 244:14] - node _T_558 = cat(_T_557, _T_550) @[el2_lib.scala 244:14] - node _T_559 = cat(_T_317[17], _T_317[16]) @[el2_lib.scala 244:14] - node _T_560 = cat(_T_317[19], _T_317[18]) @[el2_lib.scala 244:14] - node _T_561 = cat(_T_560, _T_559) @[el2_lib.scala 244:14] - node _T_562 = cat(_T_317[21], _T_317[20]) @[el2_lib.scala 244:14] - node _T_563 = cat(_T_317[23], _T_317[22]) @[el2_lib.scala 244:14] - node _T_564 = cat(_T_563, _T_562) @[el2_lib.scala 244:14] - node _T_565 = cat(_T_564, _T_561) @[el2_lib.scala 244:14] - node _T_566 = cat(_T_317[25], _T_317[24]) @[el2_lib.scala 244:14] - node _T_567 = cat(_T_317[27], _T_317[26]) @[el2_lib.scala 244:14] - node _T_568 = cat(_T_567, _T_566) @[el2_lib.scala 244:14] - node _T_569 = cat(_T_317[29], _T_317[28]) @[el2_lib.scala 244:14] - node _T_570 = cat(_T_317[31], _T_317[30]) @[el2_lib.scala 244:14] - node _T_571 = cat(_T_570, _T_569) @[el2_lib.scala 244:14] - node _T_572 = cat(_T_571, _T_568) @[el2_lib.scala 244:14] - node _T_573 = cat(_T_572, _T_565) @[el2_lib.scala 244:14] - node _T_574 = cat(_T_573, _T_558) @[el2_lib.scala 244:14] - node _T_575 = andr(_T_574) @[el2_lib.scala 244:21] - node _T_576 = and(_T_315, _T_575) @[el2_lsu_trigger.scala 19:87] - node _T_577 = eq(io.lsu_pkt_m.dma, UInt<1>("h00")) @[el2_lsu_trigger.scala 18:71] - node _T_578 = and(io.lsu_pkt_m.valid, _T_577) @[el2_lsu_trigger.scala 18:69] - node _T_579 = and(io.trigger_pkt_any[2].store, io.lsu_pkt_m.store) @[el2_lsu_trigger.scala 18:121] - node _T_580 = and(io.trigger_pkt_any[2].load, io.lsu_pkt_m.load) @[el2_lsu_trigger.scala 19:33] - node _T_581 = eq(io.trigger_pkt_any[2].select, UInt<1>("h00")) @[el2_lsu_trigger.scala 19:55] - node _T_582 = and(_T_580, _T_581) @[el2_lsu_trigger.scala 19:53] - node _T_583 = or(_T_579, _T_582) @[el2_lsu_trigger.scala 18:142] - node _T_584 = and(_T_578, _T_583) @[el2_lsu_trigger.scala 18:89] - node _T_585 = bits(io.trigger_pkt_any[2].match_, 0, 0) @[el2_lsu_trigger.scala 20:106] - wire _T_586 : UInt<1>[32] @[el2_lib.scala 239:24] - node _T_587 = bits(_T_585, 0, 0) @[el2_lib.scala 240:37] - node _T_588 = bits(io.trigger_pkt_any[2].tdata2, 31, 0) @[el2_lib.scala 240:53] - node _T_589 = andr(_T_588) @[el2_lib.scala 240:73] - node _T_590 = not(_T_589) @[el2_lib.scala 240:47] - node _T_591 = and(_T_587, _T_590) @[el2_lib.scala 240:44] - node _T_592 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[el2_lib.scala 241:48] - node _T_593 = bits(lsu_match_data_2, 0, 0) @[el2_lib.scala 241:60] - node _T_594 = eq(_T_592, _T_593) @[el2_lib.scala 241:52] - node _T_595 = or(_T_591, _T_594) @[el2_lib.scala 241:41] - _T_586[0] <= _T_595 @[el2_lib.scala 241:18] - node _T_596 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[el2_lib.scala 243:29] - node _T_597 = andr(_T_596) @[el2_lib.scala 243:37] - node _T_598 = and(_T_597, _T_591) @[el2_lib.scala 243:42] - node _T_599 = bits(io.trigger_pkt_any[2].tdata2, 1, 1) @[el2_lib.scala 243:75] - node _T_600 = bits(lsu_match_data_2, 1, 1) @[el2_lib.scala 243:87] - node _T_601 = eq(_T_599, _T_600) @[el2_lib.scala 243:79] - node _T_602 = mux(_T_598, UInt<1>("h01"), _T_601) @[el2_lib.scala 243:24] - _T_586[1] <= _T_602 @[el2_lib.scala 243:18] - node _T_603 = bits(io.trigger_pkt_any[2].tdata2, 1, 0) @[el2_lib.scala 243:29] - node _T_604 = andr(_T_603) @[el2_lib.scala 243:37] - node _T_605 = and(_T_604, _T_591) @[el2_lib.scala 243:42] - node _T_606 = bits(io.trigger_pkt_any[2].tdata2, 2, 2) @[el2_lib.scala 243:75] - node _T_607 = bits(lsu_match_data_2, 2, 2) @[el2_lib.scala 243:87] - node _T_608 = eq(_T_606, _T_607) @[el2_lib.scala 243:79] - node _T_609 = mux(_T_605, UInt<1>("h01"), _T_608) @[el2_lib.scala 243:24] - _T_586[2] <= _T_609 @[el2_lib.scala 243:18] - node _T_610 = bits(io.trigger_pkt_any[2].tdata2, 2, 0) @[el2_lib.scala 243:29] - node _T_611 = andr(_T_610) @[el2_lib.scala 243:37] - node _T_612 = and(_T_611, _T_591) @[el2_lib.scala 243:42] - node _T_613 = bits(io.trigger_pkt_any[2].tdata2, 3, 3) @[el2_lib.scala 243:75] - node _T_614 = bits(lsu_match_data_2, 3, 3) @[el2_lib.scala 243:87] - node _T_615 = eq(_T_613, _T_614) @[el2_lib.scala 243:79] - node _T_616 = mux(_T_612, UInt<1>("h01"), _T_615) @[el2_lib.scala 243:24] - _T_586[3] <= _T_616 @[el2_lib.scala 243:18] - node _T_617 = bits(io.trigger_pkt_any[2].tdata2, 3, 0) @[el2_lib.scala 243:29] - node _T_618 = andr(_T_617) @[el2_lib.scala 243:37] - node _T_619 = and(_T_618, _T_591) @[el2_lib.scala 243:42] - node _T_620 = bits(io.trigger_pkt_any[2].tdata2, 4, 4) @[el2_lib.scala 243:75] - node _T_621 = bits(lsu_match_data_2, 4, 4) @[el2_lib.scala 243:87] - node _T_622 = eq(_T_620, _T_621) @[el2_lib.scala 243:79] - node _T_623 = mux(_T_619, UInt<1>("h01"), _T_622) @[el2_lib.scala 243:24] - _T_586[4] <= _T_623 @[el2_lib.scala 243:18] - node _T_624 = bits(io.trigger_pkt_any[2].tdata2, 4, 0) @[el2_lib.scala 243:29] - node _T_625 = andr(_T_624) @[el2_lib.scala 243:37] - node _T_626 = and(_T_625, _T_591) @[el2_lib.scala 243:42] - node _T_627 = bits(io.trigger_pkt_any[2].tdata2, 5, 5) @[el2_lib.scala 243:75] - node _T_628 = bits(lsu_match_data_2, 5, 5) @[el2_lib.scala 243:87] - node _T_629 = eq(_T_627, _T_628) @[el2_lib.scala 243:79] - node _T_630 = mux(_T_626, UInt<1>("h01"), _T_629) @[el2_lib.scala 243:24] - _T_586[5] <= _T_630 @[el2_lib.scala 243:18] - node _T_631 = bits(io.trigger_pkt_any[2].tdata2, 5, 0) @[el2_lib.scala 243:29] - node _T_632 = andr(_T_631) @[el2_lib.scala 243:37] - node _T_633 = and(_T_632, _T_591) @[el2_lib.scala 243:42] - node _T_634 = bits(io.trigger_pkt_any[2].tdata2, 6, 6) @[el2_lib.scala 243:75] - node _T_635 = bits(lsu_match_data_2, 6, 6) @[el2_lib.scala 243:87] - node _T_636 = eq(_T_634, _T_635) @[el2_lib.scala 243:79] - node _T_637 = mux(_T_633, UInt<1>("h01"), _T_636) @[el2_lib.scala 243:24] - _T_586[6] <= _T_637 @[el2_lib.scala 243:18] - node _T_638 = bits(io.trigger_pkt_any[2].tdata2, 6, 0) @[el2_lib.scala 243:29] - node _T_639 = andr(_T_638) @[el2_lib.scala 243:37] - node _T_640 = and(_T_639, _T_591) @[el2_lib.scala 243:42] - node _T_641 = bits(io.trigger_pkt_any[2].tdata2, 7, 7) @[el2_lib.scala 243:75] - node _T_642 = bits(lsu_match_data_2, 7, 7) @[el2_lib.scala 243:87] - node _T_643 = eq(_T_641, _T_642) @[el2_lib.scala 243:79] - node _T_644 = mux(_T_640, UInt<1>("h01"), _T_643) @[el2_lib.scala 243:24] - _T_586[7] <= _T_644 @[el2_lib.scala 243:18] - node _T_645 = bits(io.trigger_pkt_any[2].tdata2, 7, 0) @[el2_lib.scala 243:29] - node _T_646 = andr(_T_645) @[el2_lib.scala 243:37] - node _T_647 = and(_T_646, _T_591) @[el2_lib.scala 243:42] - node _T_648 = bits(io.trigger_pkt_any[2].tdata2, 8, 8) @[el2_lib.scala 243:75] - node _T_649 = bits(lsu_match_data_2, 8, 8) @[el2_lib.scala 243:87] - node _T_650 = eq(_T_648, _T_649) @[el2_lib.scala 243:79] - node _T_651 = mux(_T_647, UInt<1>("h01"), _T_650) @[el2_lib.scala 243:24] - _T_586[8] <= _T_651 @[el2_lib.scala 243:18] - node _T_652 = bits(io.trigger_pkt_any[2].tdata2, 8, 0) @[el2_lib.scala 243:29] - node _T_653 = andr(_T_652) @[el2_lib.scala 243:37] - node _T_654 = and(_T_653, _T_591) @[el2_lib.scala 243:42] - node _T_655 = bits(io.trigger_pkt_any[2].tdata2, 9, 9) @[el2_lib.scala 243:75] - node _T_656 = bits(lsu_match_data_2, 9, 9) @[el2_lib.scala 243:87] - node _T_657 = eq(_T_655, _T_656) @[el2_lib.scala 243:79] - node _T_658 = mux(_T_654, UInt<1>("h01"), _T_657) @[el2_lib.scala 243:24] - _T_586[9] <= _T_658 @[el2_lib.scala 243:18] - node _T_659 = bits(io.trigger_pkt_any[2].tdata2, 9, 0) @[el2_lib.scala 243:29] - node _T_660 = andr(_T_659) @[el2_lib.scala 243:37] - node _T_661 = and(_T_660, _T_591) @[el2_lib.scala 243:42] - node _T_662 = bits(io.trigger_pkt_any[2].tdata2, 10, 10) @[el2_lib.scala 243:75] - node _T_663 = bits(lsu_match_data_2, 10, 10) @[el2_lib.scala 243:87] - node _T_664 = eq(_T_662, _T_663) @[el2_lib.scala 243:79] - node _T_665 = mux(_T_661, UInt<1>("h01"), _T_664) @[el2_lib.scala 243:24] - _T_586[10] <= _T_665 @[el2_lib.scala 243:18] - node _T_666 = bits(io.trigger_pkt_any[2].tdata2, 10, 0) @[el2_lib.scala 243:29] - node _T_667 = andr(_T_666) @[el2_lib.scala 243:37] - node _T_668 = and(_T_667, _T_591) @[el2_lib.scala 243:42] - node _T_669 = bits(io.trigger_pkt_any[2].tdata2, 11, 11) @[el2_lib.scala 243:75] - node _T_670 = bits(lsu_match_data_2, 11, 11) @[el2_lib.scala 243:87] - node _T_671 = eq(_T_669, _T_670) @[el2_lib.scala 243:79] - node _T_672 = mux(_T_668, UInt<1>("h01"), _T_671) @[el2_lib.scala 243:24] - _T_586[11] <= _T_672 @[el2_lib.scala 243:18] - node _T_673 = bits(io.trigger_pkt_any[2].tdata2, 11, 0) @[el2_lib.scala 243:29] - node _T_674 = andr(_T_673) @[el2_lib.scala 243:37] - node _T_675 = and(_T_674, _T_591) @[el2_lib.scala 243:42] - node _T_676 = bits(io.trigger_pkt_any[2].tdata2, 12, 12) @[el2_lib.scala 243:75] - node _T_677 = bits(lsu_match_data_2, 12, 12) @[el2_lib.scala 243:87] - node _T_678 = eq(_T_676, _T_677) @[el2_lib.scala 243:79] - node _T_679 = mux(_T_675, UInt<1>("h01"), _T_678) @[el2_lib.scala 243:24] - _T_586[12] <= _T_679 @[el2_lib.scala 243:18] - node _T_680 = bits(io.trigger_pkt_any[2].tdata2, 12, 0) @[el2_lib.scala 243:29] - node _T_681 = andr(_T_680) @[el2_lib.scala 243:37] - node _T_682 = and(_T_681, _T_591) @[el2_lib.scala 243:42] - node _T_683 = bits(io.trigger_pkt_any[2].tdata2, 13, 13) @[el2_lib.scala 243:75] - node _T_684 = bits(lsu_match_data_2, 13, 13) @[el2_lib.scala 243:87] - node _T_685 = eq(_T_683, _T_684) @[el2_lib.scala 243:79] - node _T_686 = mux(_T_682, UInt<1>("h01"), _T_685) @[el2_lib.scala 243:24] - _T_586[13] <= _T_686 @[el2_lib.scala 243:18] - node _T_687 = bits(io.trigger_pkt_any[2].tdata2, 13, 0) @[el2_lib.scala 243:29] - node _T_688 = andr(_T_687) @[el2_lib.scala 243:37] - node _T_689 = and(_T_688, _T_591) @[el2_lib.scala 243:42] - node _T_690 = bits(io.trigger_pkt_any[2].tdata2, 14, 14) @[el2_lib.scala 243:75] - node _T_691 = bits(lsu_match_data_2, 14, 14) @[el2_lib.scala 243:87] - node _T_692 = eq(_T_690, _T_691) @[el2_lib.scala 243:79] - node _T_693 = mux(_T_689, UInt<1>("h01"), _T_692) @[el2_lib.scala 243:24] - _T_586[14] <= _T_693 @[el2_lib.scala 243:18] - node _T_694 = bits(io.trigger_pkt_any[2].tdata2, 14, 0) @[el2_lib.scala 243:29] - node _T_695 = andr(_T_694) @[el2_lib.scala 243:37] - node _T_696 = and(_T_695, _T_591) @[el2_lib.scala 243:42] - node _T_697 = bits(io.trigger_pkt_any[2].tdata2, 15, 15) @[el2_lib.scala 243:75] - node _T_698 = bits(lsu_match_data_2, 15, 15) @[el2_lib.scala 243:87] - node _T_699 = eq(_T_697, _T_698) @[el2_lib.scala 243:79] - node _T_700 = mux(_T_696, UInt<1>("h01"), _T_699) @[el2_lib.scala 243:24] - _T_586[15] <= _T_700 @[el2_lib.scala 243:18] - node _T_701 = bits(io.trigger_pkt_any[2].tdata2, 15, 0) @[el2_lib.scala 243:29] - node _T_702 = andr(_T_701) @[el2_lib.scala 243:37] - node _T_703 = and(_T_702, _T_591) @[el2_lib.scala 243:42] - node _T_704 = bits(io.trigger_pkt_any[2].tdata2, 16, 16) @[el2_lib.scala 243:75] - node _T_705 = bits(lsu_match_data_2, 16, 16) @[el2_lib.scala 243:87] - node _T_706 = eq(_T_704, _T_705) @[el2_lib.scala 243:79] - node _T_707 = mux(_T_703, UInt<1>("h01"), _T_706) @[el2_lib.scala 243:24] - _T_586[16] <= _T_707 @[el2_lib.scala 243:18] - node _T_708 = bits(io.trigger_pkt_any[2].tdata2, 16, 0) @[el2_lib.scala 243:29] - node _T_709 = andr(_T_708) @[el2_lib.scala 243:37] - node _T_710 = and(_T_709, _T_591) @[el2_lib.scala 243:42] - node _T_711 = bits(io.trigger_pkt_any[2].tdata2, 17, 17) @[el2_lib.scala 243:75] - node _T_712 = bits(lsu_match_data_2, 17, 17) @[el2_lib.scala 243:87] - node _T_713 = eq(_T_711, _T_712) @[el2_lib.scala 243:79] - node _T_714 = mux(_T_710, UInt<1>("h01"), _T_713) @[el2_lib.scala 243:24] - _T_586[17] <= _T_714 @[el2_lib.scala 243:18] - node _T_715 = bits(io.trigger_pkt_any[2].tdata2, 17, 0) @[el2_lib.scala 243:29] - node _T_716 = andr(_T_715) @[el2_lib.scala 243:37] - node _T_717 = and(_T_716, _T_591) @[el2_lib.scala 243:42] - node _T_718 = bits(io.trigger_pkt_any[2].tdata2, 18, 18) @[el2_lib.scala 243:75] - node _T_719 = bits(lsu_match_data_2, 18, 18) @[el2_lib.scala 243:87] - node _T_720 = eq(_T_718, _T_719) @[el2_lib.scala 243:79] - node _T_721 = mux(_T_717, UInt<1>("h01"), _T_720) @[el2_lib.scala 243:24] - _T_586[18] <= _T_721 @[el2_lib.scala 243:18] - node _T_722 = bits(io.trigger_pkt_any[2].tdata2, 18, 0) @[el2_lib.scala 243:29] - node _T_723 = andr(_T_722) @[el2_lib.scala 243:37] - node _T_724 = and(_T_723, _T_591) @[el2_lib.scala 243:42] - node _T_725 = bits(io.trigger_pkt_any[2].tdata2, 19, 19) @[el2_lib.scala 243:75] - node _T_726 = bits(lsu_match_data_2, 19, 19) @[el2_lib.scala 243:87] - node _T_727 = eq(_T_725, _T_726) @[el2_lib.scala 243:79] - node _T_728 = mux(_T_724, UInt<1>("h01"), _T_727) @[el2_lib.scala 243:24] - _T_586[19] <= _T_728 @[el2_lib.scala 243:18] - node _T_729 = bits(io.trigger_pkt_any[2].tdata2, 19, 0) @[el2_lib.scala 243:29] - node _T_730 = andr(_T_729) @[el2_lib.scala 243:37] - node _T_731 = and(_T_730, _T_591) @[el2_lib.scala 243:42] - node _T_732 = bits(io.trigger_pkt_any[2].tdata2, 20, 20) @[el2_lib.scala 243:75] - node _T_733 = bits(lsu_match_data_2, 20, 20) @[el2_lib.scala 243:87] - node _T_734 = eq(_T_732, _T_733) @[el2_lib.scala 243:79] - node _T_735 = mux(_T_731, UInt<1>("h01"), _T_734) @[el2_lib.scala 243:24] - _T_586[20] <= _T_735 @[el2_lib.scala 243:18] - node _T_736 = bits(io.trigger_pkt_any[2].tdata2, 20, 0) @[el2_lib.scala 243:29] - node _T_737 = andr(_T_736) @[el2_lib.scala 243:37] - node _T_738 = and(_T_737, _T_591) @[el2_lib.scala 243:42] - node _T_739 = bits(io.trigger_pkt_any[2].tdata2, 21, 21) @[el2_lib.scala 243:75] - node _T_740 = bits(lsu_match_data_2, 21, 21) @[el2_lib.scala 243:87] - node _T_741 = eq(_T_739, _T_740) @[el2_lib.scala 243:79] - node _T_742 = mux(_T_738, UInt<1>("h01"), _T_741) @[el2_lib.scala 243:24] - _T_586[21] <= _T_742 @[el2_lib.scala 243:18] - node _T_743 = bits(io.trigger_pkt_any[2].tdata2, 21, 0) @[el2_lib.scala 243:29] - node _T_744 = andr(_T_743) @[el2_lib.scala 243:37] - node _T_745 = and(_T_744, _T_591) @[el2_lib.scala 243:42] - node _T_746 = bits(io.trigger_pkt_any[2].tdata2, 22, 22) @[el2_lib.scala 243:75] - node _T_747 = bits(lsu_match_data_2, 22, 22) @[el2_lib.scala 243:87] - node _T_748 = eq(_T_746, _T_747) @[el2_lib.scala 243:79] - node _T_749 = mux(_T_745, UInt<1>("h01"), _T_748) @[el2_lib.scala 243:24] - _T_586[22] <= _T_749 @[el2_lib.scala 243:18] - node _T_750 = bits(io.trigger_pkt_any[2].tdata2, 22, 0) @[el2_lib.scala 243:29] - node _T_751 = andr(_T_750) @[el2_lib.scala 243:37] - node _T_752 = and(_T_751, _T_591) @[el2_lib.scala 243:42] - node _T_753 = bits(io.trigger_pkt_any[2].tdata2, 23, 23) @[el2_lib.scala 243:75] - node _T_754 = bits(lsu_match_data_2, 23, 23) @[el2_lib.scala 243:87] - node _T_755 = eq(_T_753, _T_754) @[el2_lib.scala 243:79] - node _T_756 = mux(_T_752, UInt<1>("h01"), _T_755) @[el2_lib.scala 243:24] - _T_586[23] <= _T_756 @[el2_lib.scala 243:18] - node _T_757 = bits(io.trigger_pkt_any[2].tdata2, 23, 0) @[el2_lib.scala 243:29] - node _T_758 = andr(_T_757) @[el2_lib.scala 243:37] - node _T_759 = and(_T_758, _T_591) @[el2_lib.scala 243:42] - node _T_760 = bits(io.trigger_pkt_any[2].tdata2, 24, 24) @[el2_lib.scala 243:75] - node _T_761 = bits(lsu_match_data_2, 24, 24) @[el2_lib.scala 243:87] - node _T_762 = eq(_T_760, _T_761) @[el2_lib.scala 243:79] - node _T_763 = mux(_T_759, UInt<1>("h01"), _T_762) @[el2_lib.scala 243:24] - _T_586[24] <= _T_763 @[el2_lib.scala 243:18] - node _T_764 = bits(io.trigger_pkt_any[2].tdata2, 24, 0) @[el2_lib.scala 243:29] - node _T_765 = andr(_T_764) @[el2_lib.scala 243:37] - node _T_766 = and(_T_765, _T_591) @[el2_lib.scala 243:42] - node _T_767 = bits(io.trigger_pkt_any[2].tdata2, 25, 25) @[el2_lib.scala 243:75] - node _T_768 = bits(lsu_match_data_2, 25, 25) @[el2_lib.scala 243:87] - node _T_769 = eq(_T_767, _T_768) @[el2_lib.scala 243:79] - node _T_770 = mux(_T_766, UInt<1>("h01"), _T_769) @[el2_lib.scala 243:24] - _T_586[25] <= _T_770 @[el2_lib.scala 243:18] - node _T_771 = bits(io.trigger_pkt_any[2].tdata2, 25, 0) @[el2_lib.scala 243:29] - node _T_772 = andr(_T_771) @[el2_lib.scala 243:37] - node _T_773 = and(_T_772, _T_591) @[el2_lib.scala 243:42] - node _T_774 = bits(io.trigger_pkt_any[2].tdata2, 26, 26) @[el2_lib.scala 243:75] - node _T_775 = bits(lsu_match_data_2, 26, 26) @[el2_lib.scala 243:87] - node _T_776 = eq(_T_774, _T_775) @[el2_lib.scala 243:79] - node _T_777 = mux(_T_773, UInt<1>("h01"), _T_776) @[el2_lib.scala 243:24] - _T_586[26] <= _T_777 @[el2_lib.scala 243:18] - node _T_778 = bits(io.trigger_pkt_any[2].tdata2, 26, 0) @[el2_lib.scala 243:29] - node _T_779 = andr(_T_778) @[el2_lib.scala 243:37] - node _T_780 = and(_T_779, _T_591) @[el2_lib.scala 243:42] - node _T_781 = bits(io.trigger_pkt_any[2].tdata2, 27, 27) @[el2_lib.scala 243:75] - node _T_782 = bits(lsu_match_data_2, 27, 27) @[el2_lib.scala 243:87] - node _T_783 = eq(_T_781, _T_782) @[el2_lib.scala 243:79] - node _T_784 = mux(_T_780, UInt<1>("h01"), _T_783) @[el2_lib.scala 243:24] - _T_586[27] <= _T_784 @[el2_lib.scala 243:18] - node _T_785 = bits(io.trigger_pkt_any[2].tdata2, 27, 0) @[el2_lib.scala 243:29] - node _T_786 = andr(_T_785) @[el2_lib.scala 243:37] - node _T_787 = and(_T_786, _T_591) @[el2_lib.scala 243:42] - node _T_788 = bits(io.trigger_pkt_any[2].tdata2, 28, 28) @[el2_lib.scala 243:75] - node _T_789 = bits(lsu_match_data_2, 28, 28) @[el2_lib.scala 243:87] - node _T_790 = eq(_T_788, _T_789) @[el2_lib.scala 243:79] - node _T_791 = mux(_T_787, UInt<1>("h01"), _T_790) @[el2_lib.scala 243:24] - _T_586[28] <= _T_791 @[el2_lib.scala 243:18] - node _T_792 = bits(io.trigger_pkt_any[2].tdata2, 28, 0) @[el2_lib.scala 243:29] - node _T_793 = andr(_T_792) @[el2_lib.scala 243:37] - node _T_794 = and(_T_793, _T_591) @[el2_lib.scala 243:42] - node _T_795 = bits(io.trigger_pkt_any[2].tdata2, 29, 29) @[el2_lib.scala 243:75] - node _T_796 = bits(lsu_match_data_2, 29, 29) @[el2_lib.scala 243:87] - node _T_797 = eq(_T_795, _T_796) @[el2_lib.scala 243:79] - node _T_798 = mux(_T_794, UInt<1>("h01"), _T_797) @[el2_lib.scala 243:24] - _T_586[29] <= _T_798 @[el2_lib.scala 243:18] - node _T_799 = bits(io.trigger_pkt_any[2].tdata2, 29, 0) @[el2_lib.scala 243:29] - node _T_800 = andr(_T_799) @[el2_lib.scala 243:37] - node _T_801 = and(_T_800, _T_591) @[el2_lib.scala 243:42] - node _T_802 = bits(io.trigger_pkt_any[2].tdata2, 30, 30) @[el2_lib.scala 243:75] - node _T_803 = bits(lsu_match_data_2, 30, 30) @[el2_lib.scala 243:87] - node _T_804 = eq(_T_802, _T_803) @[el2_lib.scala 243:79] - node _T_805 = mux(_T_801, UInt<1>("h01"), _T_804) @[el2_lib.scala 243:24] - _T_586[30] <= _T_805 @[el2_lib.scala 243:18] - node _T_806 = bits(io.trigger_pkt_any[2].tdata2, 30, 0) @[el2_lib.scala 243:29] - node _T_807 = andr(_T_806) @[el2_lib.scala 243:37] - node _T_808 = and(_T_807, _T_591) @[el2_lib.scala 243:42] - node _T_809 = bits(io.trigger_pkt_any[2].tdata2, 31, 31) @[el2_lib.scala 243:75] - node _T_810 = bits(lsu_match_data_2, 31, 31) @[el2_lib.scala 243:87] - node _T_811 = eq(_T_809, _T_810) @[el2_lib.scala 243:79] - node _T_812 = mux(_T_808, UInt<1>("h01"), _T_811) @[el2_lib.scala 243:24] - _T_586[31] <= _T_812 @[el2_lib.scala 243:18] - node _T_813 = cat(_T_586[1], _T_586[0]) @[el2_lib.scala 244:14] - node _T_814 = cat(_T_586[3], _T_586[2]) @[el2_lib.scala 244:14] - node _T_815 = cat(_T_814, _T_813) @[el2_lib.scala 244:14] - node _T_816 = cat(_T_586[5], _T_586[4]) @[el2_lib.scala 244:14] - node _T_817 = cat(_T_586[7], _T_586[6]) @[el2_lib.scala 244:14] - node _T_818 = cat(_T_817, _T_816) @[el2_lib.scala 244:14] - node _T_819 = cat(_T_818, _T_815) @[el2_lib.scala 244:14] - node _T_820 = cat(_T_586[9], _T_586[8]) @[el2_lib.scala 244:14] - node _T_821 = cat(_T_586[11], _T_586[10]) @[el2_lib.scala 244:14] - node _T_822 = cat(_T_821, _T_820) @[el2_lib.scala 244:14] - node _T_823 = cat(_T_586[13], _T_586[12]) @[el2_lib.scala 244:14] - node _T_824 = cat(_T_586[15], _T_586[14]) @[el2_lib.scala 244:14] - node _T_825 = cat(_T_824, _T_823) @[el2_lib.scala 244:14] - node _T_826 = cat(_T_825, _T_822) @[el2_lib.scala 244:14] - node _T_827 = cat(_T_826, _T_819) @[el2_lib.scala 244:14] - node _T_828 = cat(_T_586[17], _T_586[16]) @[el2_lib.scala 244:14] - node _T_829 = cat(_T_586[19], _T_586[18]) @[el2_lib.scala 244:14] - node _T_830 = cat(_T_829, _T_828) @[el2_lib.scala 244:14] - node _T_831 = cat(_T_586[21], _T_586[20]) @[el2_lib.scala 244:14] - node _T_832 = cat(_T_586[23], _T_586[22]) @[el2_lib.scala 244:14] - node _T_833 = cat(_T_832, _T_831) @[el2_lib.scala 244:14] - node _T_834 = cat(_T_833, _T_830) @[el2_lib.scala 244:14] - node _T_835 = cat(_T_586[25], _T_586[24]) @[el2_lib.scala 244:14] - node _T_836 = cat(_T_586[27], _T_586[26]) @[el2_lib.scala 244:14] - node _T_837 = cat(_T_836, _T_835) @[el2_lib.scala 244:14] - node _T_838 = cat(_T_586[29], _T_586[28]) @[el2_lib.scala 244:14] - node _T_839 = cat(_T_586[31], _T_586[30]) @[el2_lib.scala 244:14] - node _T_840 = cat(_T_839, _T_838) @[el2_lib.scala 244:14] - node _T_841 = cat(_T_840, _T_837) @[el2_lib.scala 244:14] - node _T_842 = cat(_T_841, _T_834) @[el2_lib.scala 244:14] - node _T_843 = cat(_T_842, _T_827) @[el2_lib.scala 244:14] - node _T_844 = andr(_T_843) @[el2_lib.scala 244:21] - node _T_845 = and(_T_584, _T_844) @[el2_lsu_trigger.scala 19:87] - node _T_846 = eq(io.lsu_pkt_m.dma, UInt<1>("h00")) @[el2_lsu_trigger.scala 18:71] - node _T_847 = and(io.lsu_pkt_m.valid, _T_846) @[el2_lsu_trigger.scala 18:69] - node _T_848 = and(io.trigger_pkt_any[3].store, io.lsu_pkt_m.store) @[el2_lsu_trigger.scala 18:121] - node _T_849 = and(io.trigger_pkt_any[3].load, io.lsu_pkt_m.load) @[el2_lsu_trigger.scala 19:33] - node _T_850 = eq(io.trigger_pkt_any[3].select, UInt<1>("h00")) @[el2_lsu_trigger.scala 19:55] - node _T_851 = and(_T_849, _T_850) @[el2_lsu_trigger.scala 19:53] - node _T_852 = or(_T_848, _T_851) @[el2_lsu_trigger.scala 18:142] - node _T_853 = and(_T_847, _T_852) @[el2_lsu_trigger.scala 18:89] - node _T_854 = bits(io.trigger_pkt_any[3].match_, 0, 0) @[el2_lsu_trigger.scala 20:106] - wire _T_855 : UInt<1>[32] @[el2_lib.scala 239:24] - node _T_856 = bits(_T_854, 0, 0) @[el2_lib.scala 240:37] - node _T_857 = bits(io.trigger_pkt_any[3].tdata2, 31, 0) @[el2_lib.scala 240:53] - node _T_858 = andr(_T_857) @[el2_lib.scala 240:73] - node _T_859 = not(_T_858) @[el2_lib.scala 240:47] - node _T_860 = and(_T_856, _T_859) @[el2_lib.scala 240:44] - node _T_861 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[el2_lib.scala 241:48] - node _T_862 = bits(lsu_match_data_3, 0, 0) @[el2_lib.scala 241:60] - node _T_863 = eq(_T_861, _T_862) @[el2_lib.scala 241:52] - node _T_864 = or(_T_860, _T_863) @[el2_lib.scala 241:41] - _T_855[0] <= _T_864 @[el2_lib.scala 241:18] - node _T_865 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[el2_lib.scala 243:29] - node _T_866 = andr(_T_865) @[el2_lib.scala 243:37] - node _T_867 = and(_T_866, _T_860) @[el2_lib.scala 243:42] - node _T_868 = bits(io.trigger_pkt_any[3].tdata2, 1, 1) @[el2_lib.scala 243:75] - node _T_869 = bits(lsu_match_data_3, 1, 1) @[el2_lib.scala 243:87] - node _T_870 = eq(_T_868, _T_869) @[el2_lib.scala 243:79] - node _T_871 = mux(_T_867, UInt<1>("h01"), _T_870) @[el2_lib.scala 243:24] - _T_855[1] <= _T_871 @[el2_lib.scala 243:18] - node _T_872 = bits(io.trigger_pkt_any[3].tdata2, 1, 0) @[el2_lib.scala 243:29] - node _T_873 = andr(_T_872) @[el2_lib.scala 243:37] - node _T_874 = and(_T_873, _T_860) @[el2_lib.scala 243:42] - node _T_875 = bits(io.trigger_pkt_any[3].tdata2, 2, 2) @[el2_lib.scala 243:75] - node _T_876 = bits(lsu_match_data_3, 2, 2) @[el2_lib.scala 243:87] - node _T_877 = eq(_T_875, _T_876) @[el2_lib.scala 243:79] - node _T_878 = mux(_T_874, UInt<1>("h01"), _T_877) @[el2_lib.scala 243:24] - _T_855[2] <= _T_878 @[el2_lib.scala 243:18] - node _T_879 = bits(io.trigger_pkt_any[3].tdata2, 2, 0) @[el2_lib.scala 243:29] - node _T_880 = andr(_T_879) @[el2_lib.scala 243:37] - node _T_881 = and(_T_880, _T_860) @[el2_lib.scala 243:42] - node _T_882 = bits(io.trigger_pkt_any[3].tdata2, 3, 3) @[el2_lib.scala 243:75] - node _T_883 = bits(lsu_match_data_3, 3, 3) @[el2_lib.scala 243:87] - node _T_884 = eq(_T_882, _T_883) @[el2_lib.scala 243:79] - node _T_885 = mux(_T_881, UInt<1>("h01"), _T_884) @[el2_lib.scala 243:24] - _T_855[3] <= _T_885 @[el2_lib.scala 243:18] - node _T_886 = bits(io.trigger_pkt_any[3].tdata2, 3, 0) @[el2_lib.scala 243:29] - node _T_887 = andr(_T_886) @[el2_lib.scala 243:37] - node _T_888 = and(_T_887, _T_860) @[el2_lib.scala 243:42] - node _T_889 = bits(io.trigger_pkt_any[3].tdata2, 4, 4) @[el2_lib.scala 243:75] - node _T_890 = bits(lsu_match_data_3, 4, 4) @[el2_lib.scala 243:87] - node _T_891 = eq(_T_889, _T_890) @[el2_lib.scala 243:79] - node _T_892 = mux(_T_888, UInt<1>("h01"), _T_891) @[el2_lib.scala 243:24] - _T_855[4] <= _T_892 @[el2_lib.scala 243:18] - node _T_893 = bits(io.trigger_pkt_any[3].tdata2, 4, 0) @[el2_lib.scala 243:29] - node _T_894 = andr(_T_893) @[el2_lib.scala 243:37] - node _T_895 = and(_T_894, _T_860) @[el2_lib.scala 243:42] - node _T_896 = bits(io.trigger_pkt_any[3].tdata2, 5, 5) @[el2_lib.scala 243:75] - node _T_897 = bits(lsu_match_data_3, 5, 5) @[el2_lib.scala 243:87] - node _T_898 = eq(_T_896, _T_897) @[el2_lib.scala 243:79] - node _T_899 = mux(_T_895, UInt<1>("h01"), _T_898) @[el2_lib.scala 243:24] - _T_855[5] <= _T_899 @[el2_lib.scala 243:18] - node _T_900 = bits(io.trigger_pkt_any[3].tdata2, 5, 0) @[el2_lib.scala 243:29] - node _T_901 = andr(_T_900) @[el2_lib.scala 243:37] - node _T_902 = and(_T_901, _T_860) @[el2_lib.scala 243:42] - node _T_903 = bits(io.trigger_pkt_any[3].tdata2, 6, 6) @[el2_lib.scala 243:75] - node _T_904 = bits(lsu_match_data_3, 6, 6) @[el2_lib.scala 243:87] - node _T_905 = eq(_T_903, _T_904) @[el2_lib.scala 243:79] - node _T_906 = mux(_T_902, UInt<1>("h01"), _T_905) @[el2_lib.scala 243:24] - _T_855[6] <= _T_906 @[el2_lib.scala 243:18] - node _T_907 = bits(io.trigger_pkt_any[3].tdata2, 6, 0) @[el2_lib.scala 243:29] - node _T_908 = andr(_T_907) @[el2_lib.scala 243:37] - node _T_909 = and(_T_908, _T_860) @[el2_lib.scala 243:42] - node _T_910 = bits(io.trigger_pkt_any[3].tdata2, 7, 7) @[el2_lib.scala 243:75] - node _T_911 = bits(lsu_match_data_3, 7, 7) @[el2_lib.scala 243:87] - node _T_912 = eq(_T_910, _T_911) @[el2_lib.scala 243:79] - node _T_913 = mux(_T_909, UInt<1>("h01"), _T_912) @[el2_lib.scala 243:24] - _T_855[7] <= _T_913 @[el2_lib.scala 243:18] - node _T_914 = bits(io.trigger_pkt_any[3].tdata2, 7, 0) @[el2_lib.scala 243:29] - node _T_915 = andr(_T_914) @[el2_lib.scala 243:37] - node _T_916 = and(_T_915, _T_860) @[el2_lib.scala 243:42] - node _T_917 = bits(io.trigger_pkt_any[3].tdata2, 8, 8) @[el2_lib.scala 243:75] - node _T_918 = bits(lsu_match_data_3, 8, 8) @[el2_lib.scala 243:87] - node _T_919 = eq(_T_917, _T_918) @[el2_lib.scala 243:79] - node _T_920 = mux(_T_916, UInt<1>("h01"), _T_919) @[el2_lib.scala 243:24] - _T_855[8] <= _T_920 @[el2_lib.scala 243:18] - node _T_921 = bits(io.trigger_pkt_any[3].tdata2, 8, 0) @[el2_lib.scala 243:29] - node _T_922 = andr(_T_921) @[el2_lib.scala 243:37] - node _T_923 = and(_T_922, _T_860) @[el2_lib.scala 243:42] - node _T_924 = bits(io.trigger_pkt_any[3].tdata2, 9, 9) @[el2_lib.scala 243:75] - node _T_925 = bits(lsu_match_data_3, 9, 9) @[el2_lib.scala 243:87] - node _T_926 = eq(_T_924, _T_925) @[el2_lib.scala 243:79] - node _T_927 = mux(_T_923, UInt<1>("h01"), _T_926) @[el2_lib.scala 243:24] - _T_855[9] <= _T_927 @[el2_lib.scala 243:18] - node _T_928 = bits(io.trigger_pkt_any[3].tdata2, 9, 0) @[el2_lib.scala 243:29] - node _T_929 = andr(_T_928) @[el2_lib.scala 243:37] - node _T_930 = and(_T_929, _T_860) @[el2_lib.scala 243:42] - node _T_931 = bits(io.trigger_pkt_any[3].tdata2, 10, 10) @[el2_lib.scala 243:75] - node _T_932 = bits(lsu_match_data_3, 10, 10) @[el2_lib.scala 243:87] - node _T_933 = eq(_T_931, _T_932) @[el2_lib.scala 243:79] - node _T_934 = mux(_T_930, UInt<1>("h01"), _T_933) @[el2_lib.scala 243:24] - _T_855[10] <= _T_934 @[el2_lib.scala 243:18] - node _T_935 = bits(io.trigger_pkt_any[3].tdata2, 10, 0) @[el2_lib.scala 243:29] - node _T_936 = andr(_T_935) @[el2_lib.scala 243:37] - node _T_937 = and(_T_936, _T_860) @[el2_lib.scala 243:42] - node _T_938 = bits(io.trigger_pkt_any[3].tdata2, 11, 11) @[el2_lib.scala 243:75] - node _T_939 = bits(lsu_match_data_3, 11, 11) @[el2_lib.scala 243:87] - node _T_940 = eq(_T_938, _T_939) @[el2_lib.scala 243:79] - node _T_941 = mux(_T_937, UInt<1>("h01"), _T_940) @[el2_lib.scala 243:24] - _T_855[11] <= _T_941 @[el2_lib.scala 243:18] - node _T_942 = bits(io.trigger_pkt_any[3].tdata2, 11, 0) @[el2_lib.scala 243:29] - node _T_943 = andr(_T_942) @[el2_lib.scala 243:37] - node _T_944 = and(_T_943, _T_860) @[el2_lib.scala 243:42] - node _T_945 = bits(io.trigger_pkt_any[3].tdata2, 12, 12) @[el2_lib.scala 243:75] - node _T_946 = bits(lsu_match_data_3, 12, 12) @[el2_lib.scala 243:87] - node _T_947 = eq(_T_945, _T_946) @[el2_lib.scala 243:79] - node _T_948 = mux(_T_944, UInt<1>("h01"), _T_947) @[el2_lib.scala 243:24] - _T_855[12] <= _T_948 @[el2_lib.scala 243:18] - node _T_949 = bits(io.trigger_pkt_any[3].tdata2, 12, 0) @[el2_lib.scala 243:29] - node _T_950 = andr(_T_949) @[el2_lib.scala 243:37] - node _T_951 = and(_T_950, _T_860) @[el2_lib.scala 243:42] - node _T_952 = bits(io.trigger_pkt_any[3].tdata2, 13, 13) @[el2_lib.scala 243:75] - node _T_953 = bits(lsu_match_data_3, 13, 13) @[el2_lib.scala 243:87] - node _T_954 = eq(_T_952, _T_953) @[el2_lib.scala 243:79] - node _T_955 = mux(_T_951, UInt<1>("h01"), _T_954) @[el2_lib.scala 243:24] - _T_855[13] <= _T_955 @[el2_lib.scala 243:18] - node _T_956 = bits(io.trigger_pkt_any[3].tdata2, 13, 0) @[el2_lib.scala 243:29] - node _T_957 = andr(_T_956) @[el2_lib.scala 243:37] - node _T_958 = and(_T_957, _T_860) @[el2_lib.scala 243:42] - node _T_959 = bits(io.trigger_pkt_any[3].tdata2, 14, 14) @[el2_lib.scala 243:75] - node _T_960 = bits(lsu_match_data_3, 14, 14) @[el2_lib.scala 243:87] - node _T_961 = eq(_T_959, _T_960) @[el2_lib.scala 243:79] - node _T_962 = mux(_T_958, UInt<1>("h01"), _T_961) @[el2_lib.scala 243:24] - _T_855[14] <= _T_962 @[el2_lib.scala 243:18] - node _T_963 = bits(io.trigger_pkt_any[3].tdata2, 14, 0) @[el2_lib.scala 243:29] - node _T_964 = andr(_T_963) @[el2_lib.scala 243:37] - node _T_965 = and(_T_964, _T_860) @[el2_lib.scala 243:42] - node _T_966 = bits(io.trigger_pkt_any[3].tdata2, 15, 15) @[el2_lib.scala 243:75] - node _T_967 = bits(lsu_match_data_3, 15, 15) @[el2_lib.scala 243:87] - node _T_968 = eq(_T_966, _T_967) @[el2_lib.scala 243:79] - node _T_969 = mux(_T_965, UInt<1>("h01"), _T_968) @[el2_lib.scala 243:24] - _T_855[15] <= _T_969 @[el2_lib.scala 243:18] - node _T_970 = bits(io.trigger_pkt_any[3].tdata2, 15, 0) @[el2_lib.scala 243:29] - node _T_971 = andr(_T_970) @[el2_lib.scala 243:37] - node _T_972 = and(_T_971, _T_860) @[el2_lib.scala 243:42] - node _T_973 = bits(io.trigger_pkt_any[3].tdata2, 16, 16) @[el2_lib.scala 243:75] - node _T_974 = bits(lsu_match_data_3, 16, 16) @[el2_lib.scala 243:87] - node _T_975 = eq(_T_973, _T_974) @[el2_lib.scala 243:79] - node _T_976 = mux(_T_972, UInt<1>("h01"), _T_975) @[el2_lib.scala 243:24] - _T_855[16] <= _T_976 @[el2_lib.scala 243:18] - node _T_977 = bits(io.trigger_pkt_any[3].tdata2, 16, 0) @[el2_lib.scala 243:29] - node _T_978 = andr(_T_977) @[el2_lib.scala 243:37] - node _T_979 = and(_T_978, _T_860) @[el2_lib.scala 243:42] - node _T_980 = bits(io.trigger_pkt_any[3].tdata2, 17, 17) @[el2_lib.scala 243:75] - node _T_981 = bits(lsu_match_data_3, 17, 17) @[el2_lib.scala 243:87] - node _T_982 = eq(_T_980, _T_981) @[el2_lib.scala 243:79] - node _T_983 = mux(_T_979, UInt<1>("h01"), _T_982) @[el2_lib.scala 243:24] - _T_855[17] <= _T_983 @[el2_lib.scala 243:18] - node _T_984 = bits(io.trigger_pkt_any[3].tdata2, 17, 0) @[el2_lib.scala 243:29] - node _T_985 = andr(_T_984) @[el2_lib.scala 243:37] - node _T_986 = and(_T_985, _T_860) @[el2_lib.scala 243:42] - node _T_987 = bits(io.trigger_pkt_any[3].tdata2, 18, 18) @[el2_lib.scala 243:75] - node _T_988 = bits(lsu_match_data_3, 18, 18) @[el2_lib.scala 243:87] - node _T_989 = eq(_T_987, _T_988) @[el2_lib.scala 243:79] - node _T_990 = mux(_T_986, UInt<1>("h01"), _T_989) @[el2_lib.scala 243:24] - _T_855[18] <= _T_990 @[el2_lib.scala 243:18] - node _T_991 = bits(io.trigger_pkt_any[3].tdata2, 18, 0) @[el2_lib.scala 243:29] - node _T_992 = andr(_T_991) @[el2_lib.scala 243:37] - node _T_993 = and(_T_992, _T_860) @[el2_lib.scala 243:42] - node _T_994 = bits(io.trigger_pkt_any[3].tdata2, 19, 19) @[el2_lib.scala 243:75] - node _T_995 = bits(lsu_match_data_3, 19, 19) @[el2_lib.scala 243:87] - node _T_996 = eq(_T_994, _T_995) @[el2_lib.scala 243:79] - node _T_997 = mux(_T_993, UInt<1>("h01"), _T_996) @[el2_lib.scala 243:24] - _T_855[19] <= _T_997 @[el2_lib.scala 243:18] - node _T_998 = bits(io.trigger_pkt_any[3].tdata2, 19, 0) @[el2_lib.scala 243:29] - node _T_999 = andr(_T_998) @[el2_lib.scala 243:37] - node _T_1000 = and(_T_999, _T_860) @[el2_lib.scala 243:42] - node _T_1001 = bits(io.trigger_pkt_any[3].tdata2, 20, 20) @[el2_lib.scala 243:75] - node _T_1002 = bits(lsu_match_data_3, 20, 20) @[el2_lib.scala 243:87] - node _T_1003 = eq(_T_1001, _T_1002) @[el2_lib.scala 243:79] - node _T_1004 = mux(_T_1000, UInt<1>("h01"), _T_1003) @[el2_lib.scala 243:24] - _T_855[20] <= _T_1004 @[el2_lib.scala 243:18] - node _T_1005 = bits(io.trigger_pkt_any[3].tdata2, 20, 0) @[el2_lib.scala 243:29] - node _T_1006 = andr(_T_1005) @[el2_lib.scala 243:37] - node _T_1007 = and(_T_1006, _T_860) @[el2_lib.scala 243:42] - node _T_1008 = bits(io.trigger_pkt_any[3].tdata2, 21, 21) @[el2_lib.scala 243:75] - node _T_1009 = bits(lsu_match_data_3, 21, 21) @[el2_lib.scala 243:87] - node _T_1010 = eq(_T_1008, _T_1009) @[el2_lib.scala 243:79] - node _T_1011 = mux(_T_1007, UInt<1>("h01"), _T_1010) @[el2_lib.scala 243:24] - _T_855[21] <= _T_1011 @[el2_lib.scala 243:18] - node _T_1012 = bits(io.trigger_pkt_any[3].tdata2, 21, 0) @[el2_lib.scala 243:29] - node _T_1013 = andr(_T_1012) @[el2_lib.scala 243:37] - node _T_1014 = and(_T_1013, _T_860) @[el2_lib.scala 243:42] - node _T_1015 = bits(io.trigger_pkt_any[3].tdata2, 22, 22) @[el2_lib.scala 243:75] - node _T_1016 = bits(lsu_match_data_3, 22, 22) @[el2_lib.scala 243:87] - node _T_1017 = eq(_T_1015, _T_1016) @[el2_lib.scala 243:79] - node _T_1018 = mux(_T_1014, UInt<1>("h01"), _T_1017) @[el2_lib.scala 243:24] - _T_855[22] <= _T_1018 @[el2_lib.scala 243:18] - node _T_1019 = bits(io.trigger_pkt_any[3].tdata2, 22, 0) @[el2_lib.scala 243:29] - node _T_1020 = andr(_T_1019) @[el2_lib.scala 243:37] - node _T_1021 = and(_T_1020, _T_860) @[el2_lib.scala 243:42] - node _T_1022 = bits(io.trigger_pkt_any[3].tdata2, 23, 23) @[el2_lib.scala 243:75] - node _T_1023 = bits(lsu_match_data_3, 23, 23) @[el2_lib.scala 243:87] - node _T_1024 = eq(_T_1022, _T_1023) @[el2_lib.scala 243:79] - node _T_1025 = mux(_T_1021, UInt<1>("h01"), _T_1024) @[el2_lib.scala 243:24] - _T_855[23] <= _T_1025 @[el2_lib.scala 243:18] - node _T_1026 = bits(io.trigger_pkt_any[3].tdata2, 23, 0) @[el2_lib.scala 243:29] - node _T_1027 = andr(_T_1026) @[el2_lib.scala 243:37] - node _T_1028 = and(_T_1027, _T_860) @[el2_lib.scala 243:42] - node _T_1029 = bits(io.trigger_pkt_any[3].tdata2, 24, 24) @[el2_lib.scala 243:75] - node _T_1030 = bits(lsu_match_data_3, 24, 24) @[el2_lib.scala 243:87] - node _T_1031 = eq(_T_1029, _T_1030) @[el2_lib.scala 243:79] - node _T_1032 = mux(_T_1028, UInt<1>("h01"), _T_1031) @[el2_lib.scala 243:24] - _T_855[24] <= _T_1032 @[el2_lib.scala 243:18] - node _T_1033 = bits(io.trigger_pkt_any[3].tdata2, 24, 0) @[el2_lib.scala 243:29] - node _T_1034 = andr(_T_1033) @[el2_lib.scala 243:37] - node _T_1035 = and(_T_1034, _T_860) @[el2_lib.scala 243:42] - node _T_1036 = bits(io.trigger_pkt_any[3].tdata2, 25, 25) @[el2_lib.scala 243:75] - node _T_1037 = bits(lsu_match_data_3, 25, 25) @[el2_lib.scala 243:87] - node _T_1038 = eq(_T_1036, _T_1037) @[el2_lib.scala 243:79] - node _T_1039 = mux(_T_1035, UInt<1>("h01"), _T_1038) @[el2_lib.scala 243:24] - _T_855[25] <= _T_1039 @[el2_lib.scala 243:18] - node _T_1040 = bits(io.trigger_pkt_any[3].tdata2, 25, 0) @[el2_lib.scala 243:29] - node _T_1041 = andr(_T_1040) @[el2_lib.scala 243:37] - node _T_1042 = and(_T_1041, _T_860) @[el2_lib.scala 243:42] - node _T_1043 = bits(io.trigger_pkt_any[3].tdata2, 26, 26) @[el2_lib.scala 243:75] - node _T_1044 = bits(lsu_match_data_3, 26, 26) @[el2_lib.scala 243:87] - node _T_1045 = eq(_T_1043, _T_1044) @[el2_lib.scala 243:79] - node _T_1046 = mux(_T_1042, UInt<1>("h01"), _T_1045) @[el2_lib.scala 243:24] - _T_855[26] <= _T_1046 @[el2_lib.scala 243:18] - node _T_1047 = bits(io.trigger_pkt_any[3].tdata2, 26, 0) @[el2_lib.scala 243:29] - node _T_1048 = andr(_T_1047) @[el2_lib.scala 243:37] - node _T_1049 = and(_T_1048, _T_860) @[el2_lib.scala 243:42] - node _T_1050 = bits(io.trigger_pkt_any[3].tdata2, 27, 27) @[el2_lib.scala 243:75] - node _T_1051 = bits(lsu_match_data_3, 27, 27) @[el2_lib.scala 243:87] - node _T_1052 = eq(_T_1050, _T_1051) @[el2_lib.scala 243:79] - node _T_1053 = mux(_T_1049, UInt<1>("h01"), _T_1052) @[el2_lib.scala 243:24] - _T_855[27] <= _T_1053 @[el2_lib.scala 243:18] - node _T_1054 = bits(io.trigger_pkt_any[3].tdata2, 27, 0) @[el2_lib.scala 243:29] - node _T_1055 = andr(_T_1054) @[el2_lib.scala 243:37] - node _T_1056 = and(_T_1055, _T_860) @[el2_lib.scala 243:42] - node _T_1057 = bits(io.trigger_pkt_any[3].tdata2, 28, 28) @[el2_lib.scala 243:75] - node _T_1058 = bits(lsu_match_data_3, 28, 28) @[el2_lib.scala 243:87] - node _T_1059 = eq(_T_1057, _T_1058) @[el2_lib.scala 243:79] - node _T_1060 = mux(_T_1056, UInt<1>("h01"), _T_1059) @[el2_lib.scala 243:24] - _T_855[28] <= _T_1060 @[el2_lib.scala 243:18] - node _T_1061 = bits(io.trigger_pkt_any[3].tdata2, 28, 0) @[el2_lib.scala 243:29] - node _T_1062 = andr(_T_1061) @[el2_lib.scala 243:37] - node _T_1063 = and(_T_1062, _T_860) @[el2_lib.scala 243:42] - node _T_1064 = bits(io.trigger_pkt_any[3].tdata2, 29, 29) @[el2_lib.scala 243:75] - node _T_1065 = bits(lsu_match_data_3, 29, 29) @[el2_lib.scala 243:87] - node _T_1066 = eq(_T_1064, _T_1065) @[el2_lib.scala 243:79] - node _T_1067 = mux(_T_1063, UInt<1>("h01"), _T_1066) @[el2_lib.scala 243:24] - _T_855[29] <= _T_1067 @[el2_lib.scala 243:18] - node _T_1068 = bits(io.trigger_pkt_any[3].tdata2, 29, 0) @[el2_lib.scala 243:29] - node _T_1069 = andr(_T_1068) @[el2_lib.scala 243:37] - node _T_1070 = and(_T_1069, _T_860) @[el2_lib.scala 243:42] - node _T_1071 = bits(io.trigger_pkt_any[3].tdata2, 30, 30) @[el2_lib.scala 243:75] - node _T_1072 = bits(lsu_match_data_3, 30, 30) @[el2_lib.scala 243:87] - node _T_1073 = eq(_T_1071, _T_1072) @[el2_lib.scala 243:79] - node _T_1074 = mux(_T_1070, UInt<1>("h01"), _T_1073) @[el2_lib.scala 243:24] - _T_855[30] <= _T_1074 @[el2_lib.scala 243:18] - node _T_1075 = bits(io.trigger_pkt_any[3].tdata2, 30, 0) @[el2_lib.scala 243:29] - node _T_1076 = andr(_T_1075) @[el2_lib.scala 243:37] - node _T_1077 = and(_T_1076, _T_860) @[el2_lib.scala 243:42] - node _T_1078 = bits(io.trigger_pkt_any[3].tdata2, 31, 31) @[el2_lib.scala 243:75] - node _T_1079 = bits(lsu_match_data_3, 31, 31) @[el2_lib.scala 243:87] - node _T_1080 = eq(_T_1078, _T_1079) @[el2_lib.scala 243:79] - node _T_1081 = mux(_T_1077, UInt<1>("h01"), _T_1080) @[el2_lib.scala 243:24] - _T_855[31] <= _T_1081 @[el2_lib.scala 243:18] - node _T_1082 = cat(_T_855[1], _T_855[0]) @[el2_lib.scala 244:14] - node _T_1083 = cat(_T_855[3], _T_855[2]) @[el2_lib.scala 244:14] - node _T_1084 = cat(_T_1083, _T_1082) @[el2_lib.scala 244:14] - node _T_1085 = cat(_T_855[5], _T_855[4]) @[el2_lib.scala 244:14] - node _T_1086 = cat(_T_855[7], _T_855[6]) @[el2_lib.scala 244:14] - node _T_1087 = cat(_T_1086, _T_1085) @[el2_lib.scala 244:14] - node _T_1088 = cat(_T_1087, _T_1084) @[el2_lib.scala 244:14] - node _T_1089 = cat(_T_855[9], _T_855[8]) @[el2_lib.scala 244:14] - node _T_1090 = cat(_T_855[11], _T_855[10]) @[el2_lib.scala 244:14] - node _T_1091 = cat(_T_1090, _T_1089) @[el2_lib.scala 244:14] - node _T_1092 = cat(_T_855[13], _T_855[12]) @[el2_lib.scala 244:14] - node _T_1093 = cat(_T_855[15], _T_855[14]) @[el2_lib.scala 244:14] - node _T_1094 = cat(_T_1093, _T_1092) @[el2_lib.scala 244:14] - node _T_1095 = cat(_T_1094, _T_1091) @[el2_lib.scala 244:14] - node _T_1096 = cat(_T_1095, _T_1088) @[el2_lib.scala 244:14] - node _T_1097 = cat(_T_855[17], _T_855[16]) @[el2_lib.scala 244:14] - node _T_1098 = cat(_T_855[19], _T_855[18]) @[el2_lib.scala 244:14] - node _T_1099 = cat(_T_1098, _T_1097) @[el2_lib.scala 244:14] - node _T_1100 = cat(_T_855[21], _T_855[20]) @[el2_lib.scala 244:14] - node _T_1101 = cat(_T_855[23], _T_855[22]) @[el2_lib.scala 244:14] - node _T_1102 = cat(_T_1101, _T_1100) @[el2_lib.scala 244:14] - node _T_1103 = cat(_T_1102, _T_1099) @[el2_lib.scala 244:14] - node _T_1104 = cat(_T_855[25], _T_855[24]) @[el2_lib.scala 244:14] - node _T_1105 = cat(_T_855[27], _T_855[26]) @[el2_lib.scala 244:14] - node _T_1106 = cat(_T_1105, _T_1104) @[el2_lib.scala 244:14] - node _T_1107 = cat(_T_855[29], _T_855[28]) @[el2_lib.scala 244:14] - node _T_1108 = cat(_T_855[31], _T_855[30]) @[el2_lib.scala 244:14] - node _T_1109 = cat(_T_1108, _T_1107) @[el2_lib.scala 244:14] - node _T_1110 = cat(_T_1109, _T_1106) @[el2_lib.scala 244:14] - node _T_1111 = cat(_T_1110, _T_1103) @[el2_lib.scala 244:14] - node _T_1112 = cat(_T_1111, _T_1096) @[el2_lib.scala 244:14] - node _T_1113 = andr(_T_1112) @[el2_lib.scala 244:21] - node _T_1114 = and(_T_853, _T_1113) @[el2_lsu_trigger.scala 19:87] - node _T_1115 = cat(_T_1114, _T_845) @[Cat.scala 29:58] - node _T_1116 = cat(_T_1115, _T_576) @[Cat.scala 29:58] - node _T_1117 = cat(_T_1116, _T_307) @[Cat.scala 29:58] - io.lsu_trigger_match_m <= _T_1117 @[el2_lsu_trigger.scala 18:26] + node _T_41 = and(io.trigger_pkt_any[0].store, io.lsu_pkt_m.bits.store) @[el2_lsu_trigger.scala 18:126] + node _T_42 = and(io.trigger_pkt_any[0].load, io.lsu_pkt_m.bits.load) @[el2_lsu_trigger.scala 19:33] + node _T_43 = eq(io.trigger_pkt_any[0].select, UInt<1>("h00")) @[el2_lsu_trigger.scala 19:60] + node _T_44 = and(_T_42, _T_43) @[el2_lsu_trigger.scala 19:58] + node _T_45 = or(_T_41, _T_44) @[el2_lsu_trigger.scala 18:152] + node _T_46 = and(_T_40, _T_45) @[el2_lsu_trigger.scala 18:94] + node _T_47 = bits(io.trigger_pkt_any[0].match_pkt, 0, 0) @[el2_lsu_trigger.scala 20:107] + wire _T_48 : UInt<1>[32] @[el2_lib.scala 240:24] + node _T_49 = andr(io.trigger_pkt_any[0].tdata2) @[el2_lib.scala 241:45] + node _T_50 = not(_T_49) @[el2_lib.scala 241:39] + node _T_51 = and(_T_47, _T_50) @[el2_lib.scala 241:37] + node _T_52 = bits(io.trigger_pkt_any[0].tdata2, 0, 0) @[el2_lib.scala 242:48] + node _T_53 = bits(lsu_match_data_0, 0, 0) @[el2_lib.scala 242:60] + node _T_54 = eq(_T_52, _T_53) @[el2_lib.scala 242:52] + node _T_55 = or(_T_51, _T_54) @[el2_lib.scala 242:41] + _T_48[0] <= _T_55 @[el2_lib.scala 242:18] + node _T_56 = bits(io.trigger_pkt_any[0].tdata2, 0, 0) @[el2_lib.scala 244:28] + node _T_57 = andr(_T_56) @[el2_lib.scala 244:36] + node _T_58 = and(_T_57, _T_51) @[el2_lib.scala 244:41] + node _T_59 = bits(io.trigger_pkt_any[0].tdata2, 1, 1) @[el2_lib.scala 244:74] + node _T_60 = bits(lsu_match_data_0, 1, 1) @[el2_lib.scala 244:86] + node _T_61 = eq(_T_59, _T_60) @[el2_lib.scala 244:78] + node _T_62 = mux(_T_58, UInt<1>("h01"), _T_61) @[el2_lib.scala 244:23] + _T_48[1] <= _T_62 @[el2_lib.scala 244:17] + node _T_63 = bits(io.trigger_pkt_any[0].tdata2, 1, 0) @[el2_lib.scala 244:28] + node _T_64 = andr(_T_63) @[el2_lib.scala 244:36] + node _T_65 = and(_T_64, _T_51) @[el2_lib.scala 244:41] + node _T_66 = bits(io.trigger_pkt_any[0].tdata2, 2, 2) @[el2_lib.scala 244:74] + node _T_67 = bits(lsu_match_data_0, 2, 2) @[el2_lib.scala 244:86] + node _T_68 = eq(_T_66, _T_67) @[el2_lib.scala 244:78] + node _T_69 = mux(_T_65, UInt<1>("h01"), _T_68) @[el2_lib.scala 244:23] + _T_48[2] <= _T_69 @[el2_lib.scala 244:17] + node _T_70 = bits(io.trigger_pkt_any[0].tdata2, 2, 0) @[el2_lib.scala 244:28] + node _T_71 = andr(_T_70) @[el2_lib.scala 244:36] + node _T_72 = and(_T_71, _T_51) @[el2_lib.scala 244:41] + node _T_73 = bits(io.trigger_pkt_any[0].tdata2, 3, 3) @[el2_lib.scala 244:74] + node _T_74 = bits(lsu_match_data_0, 3, 3) @[el2_lib.scala 244:86] + node _T_75 = eq(_T_73, _T_74) @[el2_lib.scala 244:78] + node _T_76 = mux(_T_72, UInt<1>("h01"), _T_75) @[el2_lib.scala 244:23] + _T_48[3] <= _T_76 @[el2_lib.scala 244:17] + node _T_77 = bits(io.trigger_pkt_any[0].tdata2, 3, 0) @[el2_lib.scala 244:28] + node _T_78 = andr(_T_77) @[el2_lib.scala 244:36] + node _T_79 = and(_T_78, _T_51) @[el2_lib.scala 244:41] + node _T_80 = bits(io.trigger_pkt_any[0].tdata2, 4, 4) @[el2_lib.scala 244:74] + node _T_81 = bits(lsu_match_data_0, 4, 4) @[el2_lib.scala 244:86] + node _T_82 = eq(_T_80, _T_81) @[el2_lib.scala 244:78] + node _T_83 = mux(_T_79, UInt<1>("h01"), _T_82) @[el2_lib.scala 244:23] + _T_48[4] <= _T_83 @[el2_lib.scala 244:17] + node _T_84 = bits(io.trigger_pkt_any[0].tdata2, 4, 0) @[el2_lib.scala 244:28] + node _T_85 = andr(_T_84) @[el2_lib.scala 244:36] + node _T_86 = and(_T_85, _T_51) @[el2_lib.scala 244:41] + node _T_87 = bits(io.trigger_pkt_any[0].tdata2, 5, 5) @[el2_lib.scala 244:74] + node _T_88 = bits(lsu_match_data_0, 5, 5) @[el2_lib.scala 244:86] + node _T_89 = eq(_T_87, _T_88) @[el2_lib.scala 244:78] + node _T_90 = mux(_T_86, UInt<1>("h01"), _T_89) @[el2_lib.scala 244:23] + _T_48[5] <= _T_90 @[el2_lib.scala 244:17] + node _T_91 = bits(io.trigger_pkt_any[0].tdata2, 5, 0) @[el2_lib.scala 244:28] + node _T_92 = andr(_T_91) @[el2_lib.scala 244:36] + node _T_93 = and(_T_92, _T_51) @[el2_lib.scala 244:41] + node _T_94 = bits(io.trigger_pkt_any[0].tdata2, 6, 6) @[el2_lib.scala 244:74] + node _T_95 = bits(lsu_match_data_0, 6, 6) @[el2_lib.scala 244:86] + node _T_96 = eq(_T_94, _T_95) @[el2_lib.scala 244:78] + node _T_97 = mux(_T_93, UInt<1>("h01"), _T_96) @[el2_lib.scala 244:23] + _T_48[6] <= _T_97 @[el2_lib.scala 244:17] + node _T_98 = bits(io.trigger_pkt_any[0].tdata2, 6, 0) @[el2_lib.scala 244:28] + node _T_99 = andr(_T_98) @[el2_lib.scala 244:36] + node _T_100 = and(_T_99, _T_51) @[el2_lib.scala 244:41] + node _T_101 = bits(io.trigger_pkt_any[0].tdata2, 7, 7) @[el2_lib.scala 244:74] + node _T_102 = bits(lsu_match_data_0, 7, 7) @[el2_lib.scala 244:86] + node _T_103 = eq(_T_101, _T_102) @[el2_lib.scala 244:78] + node _T_104 = mux(_T_100, UInt<1>("h01"), _T_103) @[el2_lib.scala 244:23] + _T_48[7] <= _T_104 @[el2_lib.scala 244:17] + node _T_105 = bits(io.trigger_pkt_any[0].tdata2, 7, 0) @[el2_lib.scala 244:28] + node _T_106 = andr(_T_105) @[el2_lib.scala 244:36] + node _T_107 = and(_T_106, _T_51) @[el2_lib.scala 244:41] + node _T_108 = bits(io.trigger_pkt_any[0].tdata2, 8, 8) @[el2_lib.scala 244:74] + node _T_109 = bits(lsu_match_data_0, 8, 8) @[el2_lib.scala 244:86] + node _T_110 = eq(_T_108, _T_109) @[el2_lib.scala 244:78] + node _T_111 = mux(_T_107, UInt<1>("h01"), _T_110) @[el2_lib.scala 244:23] + _T_48[8] <= _T_111 @[el2_lib.scala 244:17] + node _T_112 = bits(io.trigger_pkt_any[0].tdata2, 8, 0) @[el2_lib.scala 244:28] + node _T_113 = andr(_T_112) @[el2_lib.scala 244:36] + node _T_114 = and(_T_113, _T_51) @[el2_lib.scala 244:41] + node _T_115 = bits(io.trigger_pkt_any[0].tdata2, 9, 9) @[el2_lib.scala 244:74] + node _T_116 = bits(lsu_match_data_0, 9, 9) @[el2_lib.scala 244:86] + node _T_117 = eq(_T_115, _T_116) @[el2_lib.scala 244:78] + node _T_118 = mux(_T_114, UInt<1>("h01"), _T_117) @[el2_lib.scala 244:23] + _T_48[9] <= _T_118 @[el2_lib.scala 244:17] + node _T_119 = bits(io.trigger_pkt_any[0].tdata2, 9, 0) @[el2_lib.scala 244:28] + node _T_120 = andr(_T_119) @[el2_lib.scala 244:36] + node _T_121 = and(_T_120, _T_51) @[el2_lib.scala 244:41] + node _T_122 = bits(io.trigger_pkt_any[0].tdata2, 10, 10) @[el2_lib.scala 244:74] + node _T_123 = bits(lsu_match_data_0, 10, 10) @[el2_lib.scala 244:86] + node _T_124 = eq(_T_122, _T_123) @[el2_lib.scala 244:78] + node _T_125 = mux(_T_121, UInt<1>("h01"), _T_124) @[el2_lib.scala 244:23] + _T_48[10] <= _T_125 @[el2_lib.scala 244:17] + node _T_126 = bits(io.trigger_pkt_any[0].tdata2, 10, 0) @[el2_lib.scala 244:28] + node _T_127 = andr(_T_126) @[el2_lib.scala 244:36] + node _T_128 = and(_T_127, _T_51) @[el2_lib.scala 244:41] + node _T_129 = bits(io.trigger_pkt_any[0].tdata2, 11, 11) @[el2_lib.scala 244:74] + node _T_130 = bits(lsu_match_data_0, 11, 11) @[el2_lib.scala 244:86] + node _T_131 = eq(_T_129, _T_130) @[el2_lib.scala 244:78] + node _T_132 = mux(_T_128, UInt<1>("h01"), _T_131) @[el2_lib.scala 244:23] + _T_48[11] <= _T_132 @[el2_lib.scala 244:17] + node _T_133 = bits(io.trigger_pkt_any[0].tdata2, 11, 0) @[el2_lib.scala 244:28] + node _T_134 = andr(_T_133) @[el2_lib.scala 244:36] + node _T_135 = and(_T_134, _T_51) @[el2_lib.scala 244:41] + node _T_136 = bits(io.trigger_pkt_any[0].tdata2, 12, 12) @[el2_lib.scala 244:74] + node _T_137 = bits(lsu_match_data_0, 12, 12) @[el2_lib.scala 244:86] + node _T_138 = eq(_T_136, _T_137) @[el2_lib.scala 244:78] + node _T_139 = mux(_T_135, UInt<1>("h01"), _T_138) @[el2_lib.scala 244:23] + _T_48[12] <= _T_139 @[el2_lib.scala 244:17] + node _T_140 = bits(io.trigger_pkt_any[0].tdata2, 12, 0) @[el2_lib.scala 244:28] + node _T_141 = andr(_T_140) @[el2_lib.scala 244:36] + node _T_142 = and(_T_141, _T_51) @[el2_lib.scala 244:41] + node _T_143 = bits(io.trigger_pkt_any[0].tdata2, 13, 13) @[el2_lib.scala 244:74] + node _T_144 = bits(lsu_match_data_0, 13, 13) @[el2_lib.scala 244:86] + node _T_145 = eq(_T_143, _T_144) @[el2_lib.scala 244:78] + node _T_146 = mux(_T_142, UInt<1>("h01"), _T_145) @[el2_lib.scala 244:23] + _T_48[13] <= _T_146 @[el2_lib.scala 244:17] + node _T_147 = bits(io.trigger_pkt_any[0].tdata2, 13, 0) @[el2_lib.scala 244:28] + node _T_148 = andr(_T_147) @[el2_lib.scala 244:36] + node _T_149 = and(_T_148, _T_51) @[el2_lib.scala 244:41] + node _T_150 = bits(io.trigger_pkt_any[0].tdata2, 14, 14) @[el2_lib.scala 244:74] + node _T_151 = bits(lsu_match_data_0, 14, 14) @[el2_lib.scala 244:86] + node _T_152 = eq(_T_150, _T_151) @[el2_lib.scala 244:78] + node _T_153 = mux(_T_149, UInt<1>("h01"), _T_152) @[el2_lib.scala 244:23] + _T_48[14] <= _T_153 @[el2_lib.scala 244:17] + node _T_154 = bits(io.trigger_pkt_any[0].tdata2, 14, 0) @[el2_lib.scala 244:28] + node _T_155 = andr(_T_154) @[el2_lib.scala 244:36] + node _T_156 = and(_T_155, _T_51) @[el2_lib.scala 244:41] + node _T_157 = bits(io.trigger_pkt_any[0].tdata2, 15, 15) @[el2_lib.scala 244:74] + node _T_158 = bits(lsu_match_data_0, 15, 15) @[el2_lib.scala 244:86] + node _T_159 = eq(_T_157, _T_158) @[el2_lib.scala 244:78] + node _T_160 = mux(_T_156, UInt<1>("h01"), _T_159) @[el2_lib.scala 244:23] + _T_48[15] <= _T_160 @[el2_lib.scala 244:17] + node _T_161 = bits(io.trigger_pkt_any[0].tdata2, 15, 0) @[el2_lib.scala 244:28] + node _T_162 = andr(_T_161) @[el2_lib.scala 244:36] + node _T_163 = and(_T_162, _T_51) @[el2_lib.scala 244:41] + node _T_164 = bits(io.trigger_pkt_any[0].tdata2, 16, 16) @[el2_lib.scala 244:74] + node _T_165 = bits(lsu_match_data_0, 16, 16) @[el2_lib.scala 244:86] + node _T_166 = eq(_T_164, _T_165) @[el2_lib.scala 244:78] + node _T_167 = mux(_T_163, UInt<1>("h01"), _T_166) @[el2_lib.scala 244:23] + _T_48[16] <= _T_167 @[el2_lib.scala 244:17] + node _T_168 = bits(io.trigger_pkt_any[0].tdata2, 16, 0) @[el2_lib.scala 244:28] + node _T_169 = andr(_T_168) @[el2_lib.scala 244:36] + node _T_170 = and(_T_169, _T_51) @[el2_lib.scala 244:41] + node _T_171 = bits(io.trigger_pkt_any[0].tdata2, 17, 17) @[el2_lib.scala 244:74] + node _T_172 = bits(lsu_match_data_0, 17, 17) @[el2_lib.scala 244:86] + node _T_173 = eq(_T_171, _T_172) @[el2_lib.scala 244:78] + node _T_174 = mux(_T_170, UInt<1>("h01"), _T_173) @[el2_lib.scala 244:23] + _T_48[17] <= _T_174 @[el2_lib.scala 244:17] + node _T_175 = bits(io.trigger_pkt_any[0].tdata2, 17, 0) @[el2_lib.scala 244:28] + node _T_176 = andr(_T_175) @[el2_lib.scala 244:36] + node _T_177 = and(_T_176, _T_51) @[el2_lib.scala 244:41] + node _T_178 = bits(io.trigger_pkt_any[0].tdata2, 18, 18) @[el2_lib.scala 244:74] + node _T_179 = bits(lsu_match_data_0, 18, 18) @[el2_lib.scala 244:86] + node _T_180 = eq(_T_178, _T_179) @[el2_lib.scala 244:78] + node _T_181 = mux(_T_177, UInt<1>("h01"), _T_180) @[el2_lib.scala 244:23] + _T_48[18] <= _T_181 @[el2_lib.scala 244:17] + node _T_182 = bits(io.trigger_pkt_any[0].tdata2, 18, 0) @[el2_lib.scala 244:28] + node _T_183 = andr(_T_182) @[el2_lib.scala 244:36] + node _T_184 = and(_T_183, _T_51) @[el2_lib.scala 244:41] + node _T_185 = bits(io.trigger_pkt_any[0].tdata2, 19, 19) @[el2_lib.scala 244:74] + node _T_186 = bits(lsu_match_data_0, 19, 19) @[el2_lib.scala 244:86] + node _T_187 = eq(_T_185, _T_186) @[el2_lib.scala 244:78] + node _T_188 = mux(_T_184, UInt<1>("h01"), _T_187) @[el2_lib.scala 244:23] + _T_48[19] <= _T_188 @[el2_lib.scala 244:17] + node _T_189 = bits(io.trigger_pkt_any[0].tdata2, 19, 0) @[el2_lib.scala 244:28] + node _T_190 = andr(_T_189) @[el2_lib.scala 244:36] + node _T_191 = and(_T_190, _T_51) @[el2_lib.scala 244:41] + node _T_192 = bits(io.trigger_pkt_any[0].tdata2, 20, 20) @[el2_lib.scala 244:74] + node _T_193 = bits(lsu_match_data_0, 20, 20) @[el2_lib.scala 244:86] + node _T_194 = eq(_T_192, _T_193) @[el2_lib.scala 244:78] + node _T_195 = mux(_T_191, UInt<1>("h01"), _T_194) @[el2_lib.scala 244:23] + _T_48[20] <= _T_195 @[el2_lib.scala 244:17] + node _T_196 = bits(io.trigger_pkt_any[0].tdata2, 20, 0) @[el2_lib.scala 244:28] + node _T_197 = andr(_T_196) @[el2_lib.scala 244:36] + node _T_198 = and(_T_197, _T_51) @[el2_lib.scala 244:41] + node _T_199 = bits(io.trigger_pkt_any[0].tdata2, 21, 21) @[el2_lib.scala 244:74] + node _T_200 = bits(lsu_match_data_0, 21, 21) @[el2_lib.scala 244:86] + node _T_201 = eq(_T_199, _T_200) @[el2_lib.scala 244:78] + node _T_202 = mux(_T_198, UInt<1>("h01"), _T_201) @[el2_lib.scala 244:23] + _T_48[21] <= _T_202 @[el2_lib.scala 244:17] + node _T_203 = bits(io.trigger_pkt_any[0].tdata2, 21, 0) @[el2_lib.scala 244:28] + node _T_204 = andr(_T_203) @[el2_lib.scala 244:36] + node _T_205 = and(_T_204, _T_51) @[el2_lib.scala 244:41] + node _T_206 = bits(io.trigger_pkt_any[0].tdata2, 22, 22) @[el2_lib.scala 244:74] + node _T_207 = bits(lsu_match_data_0, 22, 22) @[el2_lib.scala 244:86] + node _T_208 = eq(_T_206, _T_207) @[el2_lib.scala 244:78] + node _T_209 = mux(_T_205, UInt<1>("h01"), _T_208) @[el2_lib.scala 244:23] + _T_48[22] <= _T_209 @[el2_lib.scala 244:17] + node _T_210 = bits(io.trigger_pkt_any[0].tdata2, 22, 0) @[el2_lib.scala 244:28] + node _T_211 = andr(_T_210) @[el2_lib.scala 244:36] + node _T_212 = and(_T_211, _T_51) @[el2_lib.scala 244:41] + node _T_213 = bits(io.trigger_pkt_any[0].tdata2, 23, 23) @[el2_lib.scala 244:74] + node _T_214 = bits(lsu_match_data_0, 23, 23) @[el2_lib.scala 244:86] + node _T_215 = eq(_T_213, _T_214) @[el2_lib.scala 244:78] + node _T_216 = mux(_T_212, UInt<1>("h01"), _T_215) @[el2_lib.scala 244:23] + _T_48[23] <= _T_216 @[el2_lib.scala 244:17] + node _T_217 = bits(io.trigger_pkt_any[0].tdata2, 23, 0) @[el2_lib.scala 244:28] + node _T_218 = andr(_T_217) @[el2_lib.scala 244:36] + node _T_219 = and(_T_218, _T_51) @[el2_lib.scala 244:41] + node _T_220 = bits(io.trigger_pkt_any[0].tdata2, 24, 24) @[el2_lib.scala 244:74] + node _T_221 = bits(lsu_match_data_0, 24, 24) @[el2_lib.scala 244:86] + node _T_222 = eq(_T_220, _T_221) @[el2_lib.scala 244:78] + node _T_223 = mux(_T_219, UInt<1>("h01"), _T_222) @[el2_lib.scala 244:23] + _T_48[24] <= _T_223 @[el2_lib.scala 244:17] + node _T_224 = bits(io.trigger_pkt_any[0].tdata2, 24, 0) @[el2_lib.scala 244:28] + node _T_225 = andr(_T_224) @[el2_lib.scala 244:36] + node _T_226 = and(_T_225, _T_51) @[el2_lib.scala 244:41] + node _T_227 = bits(io.trigger_pkt_any[0].tdata2, 25, 25) @[el2_lib.scala 244:74] + node _T_228 = bits(lsu_match_data_0, 25, 25) @[el2_lib.scala 244:86] + node _T_229 = eq(_T_227, _T_228) @[el2_lib.scala 244:78] + node _T_230 = mux(_T_226, UInt<1>("h01"), _T_229) @[el2_lib.scala 244:23] + _T_48[25] <= _T_230 @[el2_lib.scala 244:17] + node _T_231 = bits(io.trigger_pkt_any[0].tdata2, 25, 0) @[el2_lib.scala 244:28] + node _T_232 = andr(_T_231) @[el2_lib.scala 244:36] + node _T_233 = and(_T_232, _T_51) @[el2_lib.scala 244:41] + node _T_234 = bits(io.trigger_pkt_any[0].tdata2, 26, 26) @[el2_lib.scala 244:74] + node _T_235 = bits(lsu_match_data_0, 26, 26) @[el2_lib.scala 244:86] + node _T_236 = eq(_T_234, _T_235) @[el2_lib.scala 244:78] + node _T_237 = mux(_T_233, UInt<1>("h01"), _T_236) @[el2_lib.scala 244:23] + _T_48[26] <= _T_237 @[el2_lib.scala 244:17] + node _T_238 = bits(io.trigger_pkt_any[0].tdata2, 26, 0) @[el2_lib.scala 244:28] + node _T_239 = andr(_T_238) @[el2_lib.scala 244:36] + node _T_240 = and(_T_239, _T_51) @[el2_lib.scala 244:41] + node _T_241 = bits(io.trigger_pkt_any[0].tdata2, 27, 27) @[el2_lib.scala 244:74] + node _T_242 = bits(lsu_match_data_0, 27, 27) @[el2_lib.scala 244:86] + node _T_243 = eq(_T_241, _T_242) @[el2_lib.scala 244:78] + node _T_244 = mux(_T_240, UInt<1>("h01"), _T_243) @[el2_lib.scala 244:23] + _T_48[27] <= _T_244 @[el2_lib.scala 244:17] + node _T_245 = bits(io.trigger_pkt_any[0].tdata2, 27, 0) @[el2_lib.scala 244:28] + node _T_246 = andr(_T_245) @[el2_lib.scala 244:36] + node _T_247 = and(_T_246, _T_51) @[el2_lib.scala 244:41] + node _T_248 = bits(io.trigger_pkt_any[0].tdata2, 28, 28) @[el2_lib.scala 244:74] + node _T_249 = bits(lsu_match_data_0, 28, 28) @[el2_lib.scala 244:86] + node _T_250 = eq(_T_248, _T_249) @[el2_lib.scala 244:78] + node _T_251 = mux(_T_247, UInt<1>("h01"), _T_250) @[el2_lib.scala 244:23] + _T_48[28] <= _T_251 @[el2_lib.scala 244:17] + node _T_252 = bits(io.trigger_pkt_any[0].tdata2, 28, 0) @[el2_lib.scala 244:28] + node _T_253 = andr(_T_252) @[el2_lib.scala 244:36] + node _T_254 = and(_T_253, _T_51) @[el2_lib.scala 244:41] + node _T_255 = bits(io.trigger_pkt_any[0].tdata2, 29, 29) @[el2_lib.scala 244:74] + node _T_256 = bits(lsu_match_data_0, 29, 29) @[el2_lib.scala 244:86] + node _T_257 = eq(_T_255, _T_256) @[el2_lib.scala 244:78] + node _T_258 = mux(_T_254, UInt<1>("h01"), _T_257) @[el2_lib.scala 244:23] + _T_48[29] <= _T_258 @[el2_lib.scala 244:17] + node _T_259 = bits(io.trigger_pkt_any[0].tdata2, 29, 0) @[el2_lib.scala 244:28] + node _T_260 = andr(_T_259) @[el2_lib.scala 244:36] + node _T_261 = and(_T_260, _T_51) @[el2_lib.scala 244:41] + node _T_262 = bits(io.trigger_pkt_any[0].tdata2, 30, 30) @[el2_lib.scala 244:74] + node _T_263 = bits(lsu_match_data_0, 30, 30) @[el2_lib.scala 244:86] + node _T_264 = eq(_T_262, _T_263) @[el2_lib.scala 244:78] + node _T_265 = mux(_T_261, UInt<1>("h01"), _T_264) @[el2_lib.scala 244:23] + _T_48[30] <= _T_265 @[el2_lib.scala 244:17] + node _T_266 = bits(io.trigger_pkt_any[0].tdata2, 30, 0) @[el2_lib.scala 244:28] + node _T_267 = andr(_T_266) @[el2_lib.scala 244:36] + node _T_268 = and(_T_267, _T_51) @[el2_lib.scala 244:41] + node _T_269 = bits(io.trigger_pkt_any[0].tdata2, 31, 31) @[el2_lib.scala 244:74] + node _T_270 = bits(lsu_match_data_0, 31, 31) @[el2_lib.scala 244:86] + node _T_271 = eq(_T_269, _T_270) @[el2_lib.scala 244:78] + node _T_272 = mux(_T_268, UInt<1>("h01"), _T_271) @[el2_lib.scala 244:23] + _T_48[31] <= _T_272 @[el2_lib.scala 244:17] + node _T_273 = cat(_T_48[1], _T_48[0]) @[el2_lib.scala 245:14] + node _T_274 = cat(_T_48[3], _T_48[2]) @[el2_lib.scala 245:14] + node _T_275 = cat(_T_274, _T_273) @[el2_lib.scala 245:14] + node _T_276 = cat(_T_48[5], _T_48[4]) @[el2_lib.scala 245:14] + node _T_277 = cat(_T_48[7], _T_48[6]) @[el2_lib.scala 245:14] + node _T_278 = cat(_T_277, _T_276) @[el2_lib.scala 245:14] + node _T_279 = cat(_T_278, _T_275) @[el2_lib.scala 245:14] + node _T_280 = cat(_T_48[9], _T_48[8]) @[el2_lib.scala 245:14] + node _T_281 = cat(_T_48[11], _T_48[10]) @[el2_lib.scala 245:14] + node _T_282 = cat(_T_281, _T_280) @[el2_lib.scala 245:14] + node _T_283 = cat(_T_48[13], _T_48[12]) @[el2_lib.scala 245:14] + node _T_284 = cat(_T_48[15], _T_48[14]) @[el2_lib.scala 245:14] + node _T_285 = cat(_T_284, _T_283) @[el2_lib.scala 245:14] + node _T_286 = cat(_T_285, _T_282) @[el2_lib.scala 245:14] + node _T_287 = cat(_T_286, _T_279) @[el2_lib.scala 245:14] + node _T_288 = cat(_T_48[17], _T_48[16]) @[el2_lib.scala 245:14] + node _T_289 = cat(_T_48[19], _T_48[18]) @[el2_lib.scala 245:14] + node _T_290 = cat(_T_289, _T_288) @[el2_lib.scala 245:14] + node _T_291 = cat(_T_48[21], _T_48[20]) @[el2_lib.scala 245:14] + node _T_292 = cat(_T_48[23], _T_48[22]) @[el2_lib.scala 245:14] + node _T_293 = cat(_T_292, _T_291) @[el2_lib.scala 245:14] + node _T_294 = cat(_T_293, _T_290) @[el2_lib.scala 245:14] + node _T_295 = cat(_T_48[25], _T_48[24]) @[el2_lib.scala 245:14] + node _T_296 = cat(_T_48[27], _T_48[26]) @[el2_lib.scala 245:14] + node _T_297 = cat(_T_296, _T_295) @[el2_lib.scala 245:14] + node _T_298 = cat(_T_48[29], _T_48[28]) @[el2_lib.scala 245:14] + node _T_299 = cat(_T_48[31], _T_48[30]) @[el2_lib.scala 245:14] + node _T_300 = cat(_T_299, _T_298) @[el2_lib.scala 245:14] + node _T_301 = cat(_T_300, _T_297) @[el2_lib.scala 245:14] + node _T_302 = cat(_T_301, _T_294) @[el2_lib.scala 245:14] + node _T_303 = cat(_T_302, _T_287) @[el2_lib.scala 245:14] + node _T_304 = and(_T_46, _T_303) @[el2_lsu_trigger.scala 19:92] + node _T_305 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[el2_lsu_trigger.scala 18:71] + node _T_306 = and(io.lsu_pkt_m.valid, _T_305) @[el2_lsu_trigger.scala 18:69] + node _T_307 = and(io.trigger_pkt_any[1].store, io.lsu_pkt_m.bits.store) @[el2_lsu_trigger.scala 18:126] + node _T_308 = and(io.trigger_pkt_any[1].load, io.lsu_pkt_m.bits.load) @[el2_lsu_trigger.scala 19:33] + node _T_309 = eq(io.trigger_pkt_any[1].select, UInt<1>("h00")) @[el2_lsu_trigger.scala 19:60] + node _T_310 = and(_T_308, _T_309) @[el2_lsu_trigger.scala 19:58] + node _T_311 = or(_T_307, _T_310) @[el2_lsu_trigger.scala 18:152] + node _T_312 = and(_T_306, _T_311) @[el2_lsu_trigger.scala 18:94] + node _T_313 = bits(io.trigger_pkt_any[1].match_pkt, 0, 0) @[el2_lsu_trigger.scala 20:107] + wire _T_314 : UInt<1>[32] @[el2_lib.scala 240:24] + node _T_315 = andr(io.trigger_pkt_any[1].tdata2) @[el2_lib.scala 241:45] + node _T_316 = not(_T_315) @[el2_lib.scala 241:39] + node _T_317 = and(_T_313, _T_316) @[el2_lib.scala 241:37] + node _T_318 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[el2_lib.scala 242:48] + node _T_319 = bits(lsu_match_data_1, 0, 0) @[el2_lib.scala 242:60] + node _T_320 = eq(_T_318, _T_319) @[el2_lib.scala 242:52] + node _T_321 = or(_T_317, _T_320) @[el2_lib.scala 242:41] + _T_314[0] <= _T_321 @[el2_lib.scala 242:18] + node _T_322 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[el2_lib.scala 244:28] + node _T_323 = andr(_T_322) @[el2_lib.scala 244:36] + node _T_324 = and(_T_323, _T_317) @[el2_lib.scala 244:41] + node _T_325 = bits(io.trigger_pkt_any[1].tdata2, 1, 1) @[el2_lib.scala 244:74] + node _T_326 = bits(lsu_match_data_1, 1, 1) @[el2_lib.scala 244:86] + node _T_327 = eq(_T_325, _T_326) @[el2_lib.scala 244:78] + node _T_328 = mux(_T_324, UInt<1>("h01"), _T_327) @[el2_lib.scala 244:23] + _T_314[1] <= _T_328 @[el2_lib.scala 244:17] + node _T_329 = bits(io.trigger_pkt_any[1].tdata2, 1, 0) @[el2_lib.scala 244:28] + node _T_330 = andr(_T_329) @[el2_lib.scala 244:36] + node _T_331 = and(_T_330, _T_317) @[el2_lib.scala 244:41] + node _T_332 = bits(io.trigger_pkt_any[1].tdata2, 2, 2) @[el2_lib.scala 244:74] + node _T_333 = bits(lsu_match_data_1, 2, 2) @[el2_lib.scala 244:86] + node _T_334 = eq(_T_332, _T_333) @[el2_lib.scala 244:78] + node _T_335 = mux(_T_331, UInt<1>("h01"), _T_334) @[el2_lib.scala 244:23] + _T_314[2] <= _T_335 @[el2_lib.scala 244:17] + node _T_336 = bits(io.trigger_pkt_any[1].tdata2, 2, 0) @[el2_lib.scala 244:28] + node _T_337 = andr(_T_336) @[el2_lib.scala 244:36] + node _T_338 = and(_T_337, _T_317) @[el2_lib.scala 244:41] + node _T_339 = bits(io.trigger_pkt_any[1].tdata2, 3, 3) @[el2_lib.scala 244:74] + node _T_340 = bits(lsu_match_data_1, 3, 3) @[el2_lib.scala 244:86] + node _T_341 = eq(_T_339, _T_340) @[el2_lib.scala 244:78] + node _T_342 = mux(_T_338, UInt<1>("h01"), _T_341) @[el2_lib.scala 244:23] + _T_314[3] <= _T_342 @[el2_lib.scala 244:17] + node _T_343 = bits(io.trigger_pkt_any[1].tdata2, 3, 0) @[el2_lib.scala 244:28] + node _T_344 = andr(_T_343) @[el2_lib.scala 244:36] + node _T_345 = and(_T_344, _T_317) @[el2_lib.scala 244:41] + node _T_346 = bits(io.trigger_pkt_any[1].tdata2, 4, 4) @[el2_lib.scala 244:74] + node _T_347 = bits(lsu_match_data_1, 4, 4) @[el2_lib.scala 244:86] + node _T_348 = eq(_T_346, _T_347) @[el2_lib.scala 244:78] + node _T_349 = mux(_T_345, UInt<1>("h01"), _T_348) @[el2_lib.scala 244:23] + _T_314[4] <= _T_349 @[el2_lib.scala 244:17] + node _T_350 = bits(io.trigger_pkt_any[1].tdata2, 4, 0) @[el2_lib.scala 244:28] + node _T_351 = andr(_T_350) @[el2_lib.scala 244:36] + node _T_352 = and(_T_351, _T_317) @[el2_lib.scala 244:41] + node _T_353 = bits(io.trigger_pkt_any[1].tdata2, 5, 5) @[el2_lib.scala 244:74] + node _T_354 = bits(lsu_match_data_1, 5, 5) @[el2_lib.scala 244:86] + node _T_355 = eq(_T_353, _T_354) @[el2_lib.scala 244:78] + node _T_356 = mux(_T_352, UInt<1>("h01"), _T_355) @[el2_lib.scala 244:23] + _T_314[5] <= _T_356 @[el2_lib.scala 244:17] + node _T_357 = bits(io.trigger_pkt_any[1].tdata2, 5, 0) @[el2_lib.scala 244:28] + node _T_358 = andr(_T_357) @[el2_lib.scala 244:36] + node _T_359 = and(_T_358, _T_317) @[el2_lib.scala 244:41] + node _T_360 = bits(io.trigger_pkt_any[1].tdata2, 6, 6) @[el2_lib.scala 244:74] + node _T_361 = bits(lsu_match_data_1, 6, 6) @[el2_lib.scala 244:86] + node _T_362 = eq(_T_360, _T_361) @[el2_lib.scala 244:78] + node _T_363 = mux(_T_359, UInt<1>("h01"), _T_362) @[el2_lib.scala 244:23] + _T_314[6] <= _T_363 @[el2_lib.scala 244:17] + node _T_364 = bits(io.trigger_pkt_any[1].tdata2, 6, 0) @[el2_lib.scala 244:28] + node _T_365 = andr(_T_364) @[el2_lib.scala 244:36] + node _T_366 = and(_T_365, _T_317) @[el2_lib.scala 244:41] + node _T_367 = bits(io.trigger_pkt_any[1].tdata2, 7, 7) @[el2_lib.scala 244:74] + node _T_368 = bits(lsu_match_data_1, 7, 7) @[el2_lib.scala 244:86] + node _T_369 = eq(_T_367, _T_368) @[el2_lib.scala 244:78] + node _T_370 = mux(_T_366, UInt<1>("h01"), _T_369) @[el2_lib.scala 244:23] + _T_314[7] <= _T_370 @[el2_lib.scala 244:17] + node _T_371 = bits(io.trigger_pkt_any[1].tdata2, 7, 0) @[el2_lib.scala 244:28] + node _T_372 = andr(_T_371) @[el2_lib.scala 244:36] + node _T_373 = and(_T_372, _T_317) @[el2_lib.scala 244:41] + node _T_374 = bits(io.trigger_pkt_any[1].tdata2, 8, 8) @[el2_lib.scala 244:74] + node _T_375 = bits(lsu_match_data_1, 8, 8) @[el2_lib.scala 244:86] + node _T_376 = eq(_T_374, _T_375) @[el2_lib.scala 244:78] + node _T_377 = mux(_T_373, UInt<1>("h01"), _T_376) @[el2_lib.scala 244:23] + _T_314[8] <= _T_377 @[el2_lib.scala 244:17] + node _T_378 = bits(io.trigger_pkt_any[1].tdata2, 8, 0) @[el2_lib.scala 244:28] + node _T_379 = andr(_T_378) @[el2_lib.scala 244:36] + node _T_380 = and(_T_379, _T_317) @[el2_lib.scala 244:41] + node _T_381 = bits(io.trigger_pkt_any[1].tdata2, 9, 9) @[el2_lib.scala 244:74] + node _T_382 = bits(lsu_match_data_1, 9, 9) @[el2_lib.scala 244:86] + node _T_383 = eq(_T_381, _T_382) @[el2_lib.scala 244:78] + node _T_384 = mux(_T_380, UInt<1>("h01"), _T_383) @[el2_lib.scala 244:23] + _T_314[9] <= _T_384 @[el2_lib.scala 244:17] + node _T_385 = bits(io.trigger_pkt_any[1].tdata2, 9, 0) @[el2_lib.scala 244:28] + node _T_386 = andr(_T_385) @[el2_lib.scala 244:36] + node _T_387 = and(_T_386, _T_317) @[el2_lib.scala 244:41] + node _T_388 = bits(io.trigger_pkt_any[1].tdata2, 10, 10) @[el2_lib.scala 244:74] + node _T_389 = bits(lsu_match_data_1, 10, 10) @[el2_lib.scala 244:86] + node _T_390 = eq(_T_388, _T_389) @[el2_lib.scala 244:78] + node _T_391 = mux(_T_387, UInt<1>("h01"), _T_390) @[el2_lib.scala 244:23] + _T_314[10] <= _T_391 @[el2_lib.scala 244:17] + node _T_392 = bits(io.trigger_pkt_any[1].tdata2, 10, 0) @[el2_lib.scala 244:28] + node _T_393 = andr(_T_392) @[el2_lib.scala 244:36] + node _T_394 = and(_T_393, _T_317) @[el2_lib.scala 244:41] + node _T_395 = bits(io.trigger_pkt_any[1].tdata2, 11, 11) @[el2_lib.scala 244:74] + node _T_396 = bits(lsu_match_data_1, 11, 11) @[el2_lib.scala 244:86] + node _T_397 = eq(_T_395, _T_396) @[el2_lib.scala 244:78] + node _T_398 = mux(_T_394, UInt<1>("h01"), _T_397) @[el2_lib.scala 244:23] + _T_314[11] <= _T_398 @[el2_lib.scala 244:17] + node _T_399 = bits(io.trigger_pkt_any[1].tdata2, 11, 0) @[el2_lib.scala 244:28] + node _T_400 = andr(_T_399) @[el2_lib.scala 244:36] + node _T_401 = and(_T_400, _T_317) @[el2_lib.scala 244:41] + node _T_402 = bits(io.trigger_pkt_any[1].tdata2, 12, 12) @[el2_lib.scala 244:74] + node _T_403 = bits(lsu_match_data_1, 12, 12) @[el2_lib.scala 244:86] + node _T_404 = eq(_T_402, _T_403) @[el2_lib.scala 244:78] + node _T_405 = mux(_T_401, UInt<1>("h01"), _T_404) @[el2_lib.scala 244:23] + _T_314[12] <= _T_405 @[el2_lib.scala 244:17] + node _T_406 = bits(io.trigger_pkt_any[1].tdata2, 12, 0) @[el2_lib.scala 244:28] + node _T_407 = andr(_T_406) @[el2_lib.scala 244:36] + node _T_408 = and(_T_407, _T_317) @[el2_lib.scala 244:41] + node _T_409 = bits(io.trigger_pkt_any[1].tdata2, 13, 13) @[el2_lib.scala 244:74] + node _T_410 = bits(lsu_match_data_1, 13, 13) @[el2_lib.scala 244:86] + node _T_411 = eq(_T_409, _T_410) @[el2_lib.scala 244:78] + node _T_412 = mux(_T_408, UInt<1>("h01"), _T_411) @[el2_lib.scala 244:23] + _T_314[13] <= _T_412 @[el2_lib.scala 244:17] + node _T_413 = bits(io.trigger_pkt_any[1].tdata2, 13, 0) @[el2_lib.scala 244:28] + node _T_414 = andr(_T_413) @[el2_lib.scala 244:36] + node _T_415 = and(_T_414, _T_317) @[el2_lib.scala 244:41] + node _T_416 = bits(io.trigger_pkt_any[1].tdata2, 14, 14) @[el2_lib.scala 244:74] + node _T_417 = bits(lsu_match_data_1, 14, 14) @[el2_lib.scala 244:86] + node _T_418 = eq(_T_416, _T_417) @[el2_lib.scala 244:78] + node _T_419 = mux(_T_415, UInt<1>("h01"), _T_418) @[el2_lib.scala 244:23] + _T_314[14] <= _T_419 @[el2_lib.scala 244:17] + node _T_420 = bits(io.trigger_pkt_any[1].tdata2, 14, 0) @[el2_lib.scala 244:28] + node _T_421 = andr(_T_420) @[el2_lib.scala 244:36] + node _T_422 = and(_T_421, _T_317) @[el2_lib.scala 244:41] + node _T_423 = bits(io.trigger_pkt_any[1].tdata2, 15, 15) @[el2_lib.scala 244:74] + node _T_424 = bits(lsu_match_data_1, 15, 15) @[el2_lib.scala 244:86] + node _T_425 = eq(_T_423, _T_424) @[el2_lib.scala 244:78] + node _T_426 = mux(_T_422, UInt<1>("h01"), _T_425) @[el2_lib.scala 244:23] + _T_314[15] <= _T_426 @[el2_lib.scala 244:17] + node _T_427 = bits(io.trigger_pkt_any[1].tdata2, 15, 0) @[el2_lib.scala 244:28] + node _T_428 = andr(_T_427) @[el2_lib.scala 244:36] + node _T_429 = and(_T_428, _T_317) @[el2_lib.scala 244:41] + node _T_430 = bits(io.trigger_pkt_any[1].tdata2, 16, 16) @[el2_lib.scala 244:74] + node _T_431 = bits(lsu_match_data_1, 16, 16) @[el2_lib.scala 244:86] + node _T_432 = eq(_T_430, _T_431) @[el2_lib.scala 244:78] + node _T_433 = mux(_T_429, UInt<1>("h01"), _T_432) @[el2_lib.scala 244:23] + _T_314[16] <= _T_433 @[el2_lib.scala 244:17] + node _T_434 = bits(io.trigger_pkt_any[1].tdata2, 16, 0) @[el2_lib.scala 244:28] + node _T_435 = andr(_T_434) @[el2_lib.scala 244:36] + node _T_436 = and(_T_435, _T_317) @[el2_lib.scala 244:41] + node _T_437 = bits(io.trigger_pkt_any[1].tdata2, 17, 17) @[el2_lib.scala 244:74] + node _T_438 = bits(lsu_match_data_1, 17, 17) @[el2_lib.scala 244:86] + node _T_439 = eq(_T_437, _T_438) @[el2_lib.scala 244:78] + node _T_440 = mux(_T_436, UInt<1>("h01"), _T_439) @[el2_lib.scala 244:23] + _T_314[17] <= _T_440 @[el2_lib.scala 244:17] + node _T_441 = bits(io.trigger_pkt_any[1].tdata2, 17, 0) @[el2_lib.scala 244:28] + node _T_442 = andr(_T_441) @[el2_lib.scala 244:36] + node _T_443 = and(_T_442, _T_317) @[el2_lib.scala 244:41] + node _T_444 = bits(io.trigger_pkt_any[1].tdata2, 18, 18) @[el2_lib.scala 244:74] + node _T_445 = bits(lsu_match_data_1, 18, 18) @[el2_lib.scala 244:86] + node _T_446 = eq(_T_444, _T_445) @[el2_lib.scala 244:78] + node _T_447 = mux(_T_443, UInt<1>("h01"), _T_446) @[el2_lib.scala 244:23] + _T_314[18] <= _T_447 @[el2_lib.scala 244:17] + node _T_448 = bits(io.trigger_pkt_any[1].tdata2, 18, 0) @[el2_lib.scala 244:28] + node _T_449 = andr(_T_448) @[el2_lib.scala 244:36] + node _T_450 = and(_T_449, _T_317) @[el2_lib.scala 244:41] + node _T_451 = bits(io.trigger_pkt_any[1].tdata2, 19, 19) @[el2_lib.scala 244:74] + node _T_452 = bits(lsu_match_data_1, 19, 19) @[el2_lib.scala 244:86] + node _T_453 = eq(_T_451, _T_452) @[el2_lib.scala 244:78] + node _T_454 = mux(_T_450, UInt<1>("h01"), _T_453) @[el2_lib.scala 244:23] + _T_314[19] <= _T_454 @[el2_lib.scala 244:17] + node _T_455 = bits(io.trigger_pkt_any[1].tdata2, 19, 0) @[el2_lib.scala 244:28] + node _T_456 = andr(_T_455) @[el2_lib.scala 244:36] + node _T_457 = and(_T_456, _T_317) @[el2_lib.scala 244:41] + node _T_458 = bits(io.trigger_pkt_any[1].tdata2, 20, 20) @[el2_lib.scala 244:74] + node _T_459 = bits(lsu_match_data_1, 20, 20) @[el2_lib.scala 244:86] + node _T_460 = eq(_T_458, _T_459) @[el2_lib.scala 244:78] + node _T_461 = mux(_T_457, UInt<1>("h01"), _T_460) @[el2_lib.scala 244:23] + _T_314[20] <= _T_461 @[el2_lib.scala 244:17] + node _T_462 = bits(io.trigger_pkt_any[1].tdata2, 20, 0) @[el2_lib.scala 244:28] + node _T_463 = andr(_T_462) @[el2_lib.scala 244:36] + node _T_464 = and(_T_463, _T_317) @[el2_lib.scala 244:41] + node _T_465 = bits(io.trigger_pkt_any[1].tdata2, 21, 21) @[el2_lib.scala 244:74] + node _T_466 = bits(lsu_match_data_1, 21, 21) @[el2_lib.scala 244:86] + node _T_467 = eq(_T_465, _T_466) @[el2_lib.scala 244:78] + node _T_468 = mux(_T_464, UInt<1>("h01"), _T_467) @[el2_lib.scala 244:23] + _T_314[21] <= _T_468 @[el2_lib.scala 244:17] + node _T_469 = bits(io.trigger_pkt_any[1].tdata2, 21, 0) @[el2_lib.scala 244:28] + node _T_470 = andr(_T_469) @[el2_lib.scala 244:36] + node _T_471 = and(_T_470, _T_317) @[el2_lib.scala 244:41] + node _T_472 = bits(io.trigger_pkt_any[1].tdata2, 22, 22) @[el2_lib.scala 244:74] + node _T_473 = bits(lsu_match_data_1, 22, 22) @[el2_lib.scala 244:86] + node _T_474 = eq(_T_472, _T_473) @[el2_lib.scala 244:78] + node _T_475 = mux(_T_471, UInt<1>("h01"), _T_474) @[el2_lib.scala 244:23] + _T_314[22] <= _T_475 @[el2_lib.scala 244:17] + node _T_476 = bits(io.trigger_pkt_any[1].tdata2, 22, 0) @[el2_lib.scala 244:28] + node _T_477 = andr(_T_476) @[el2_lib.scala 244:36] + node _T_478 = and(_T_477, _T_317) @[el2_lib.scala 244:41] + node _T_479 = bits(io.trigger_pkt_any[1].tdata2, 23, 23) @[el2_lib.scala 244:74] + node _T_480 = bits(lsu_match_data_1, 23, 23) @[el2_lib.scala 244:86] + node _T_481 = eq(_T_479, _T_480) @[el2_lib.scala 244:78] + node _T_482 = mux(_T_478, UInt<1>("h01"), _T_481) @[el2_lib.scala 244:23] + _T_314[23] <= _T_482 @[el2_lib.scala 244:17] + node _T_483 = bits(io.trigger_pkt_any[1].tdata2, 23, 0) @[el2_lib.scala 244:28] + node _T_484 = andr(_T_483) @[el2_lib.scala 244:36] + node _T_485 = and(_T_484, _T_317) @[el2_lib.scala 244:41] + node _T_486 = bits(io.trigger_pkt_any[1].tdata2, 24, 24) @[el2_lib.scala 244:74] + node _T_487 = bits(lsu_match_data_1, 24, 24) @[el2_lib.scala 244:86] + node _T_488 = eq(_T_486, _T_487) @[el2_lib.scala 244:78] + node _T_489 = mux(_T_485, UInt<1>("h01"), _T_488) @[el2_lib.scala 244:23] + _T_314[24] <= _T_489 @[el2_lib.scala 244:17] + node _T_490 = bits(io.trigger_pkt_any[1].tdata2, 24, 0) @[el2_lib.scala 244:28] + node _T_491 = andr(_T_490) @[el2_lib.scala 244:36] + node _T_492 = and(_T_491, _T_317) @[el2_lib.scala 244:41] + node _T_493 = bits(io.trigger_pkt_any[1].tdata2, 25, 25) @[el2_lib.scala 244:74] + node _T_494 = bits(lsu_match_data_1, 25, 25) @[el2_lib.scala 244:86] + node _T_495 = eq(_T_493, _T_494) @[el2_lib.scala 244:78] + node _T_496 = mux(_T_492, UInt<1>("h01"), _T_495) @[el2_lib.scala 244:23] + _T_314[25] <= _T_496 @[el2_lib.scala 244:17] + node _T_497 = bits(io.trigger_pkt_any[1].tdata2, 25, 0) @[el2_lib.scala 244:28] + node _T_498 = andr(_T_497) @[el2_lib.scala 244:36] + node _T_499 = and(_T_498, _T_317) @[el2_lib.scala 244:41] + node _T_500 = bits(io.trigger_pkt_any[1].tdata2, 26, 26) @[el2_lib.scala 244:74] + node _T_501 = bits(lsu_match_data_1, 26, 26) @[el2_lib.scala 244:86] + node _T_502 = eq(_T_500, _T_501) @[el2_lib.scala 244:78] + node _T_503 = mux(_T_499, UInt<1>("h01"), _T_502) @[el2_lib.scala 244:23] + _T_314[26] <= _T_503 @[el2_lib.scala 244:17] + node _T_504 = bits(io.trigger_pkt_any[1].tdata2, 26, 0) @[el2_lib.scala 244:28] + node _T_505 = andr(_T_504) @[el2_lib.scala 244:36] + node _T_506 = and(_T_505, _T_317) @[el2_lib.scala 244:41] + node _T_507 = bits(io.trigger_pkt_any[1].tdata2, 27, 27) @[el2_lib.scala 244:74] + node _T_508 = bits(lsu_match_data_1, 27, 27) @[el2_lib.scala 244:86] + node _T_509 = eq(_T_507, _T_508) @[el2_lib.scala 244:78] + node _T_510 = mux(_T_506, UInt<1>("h01"), _T_509) @[el2_lib.scala 244:23] + _T_314[27] <= _T_510 @[el2_lib.scala 244:17] + node _T_511 = bits(io.trigger_pkt_any[1].tdata2, 27, 0) @[el2_lib.scala 244:28] + node _T_512 = andr(_T_511) @[el2_lib.scala 244:36] + node _T_513 = and(_T_512, _T_317) @[el2_lib.scala 244:41] + node _T_514 = bits(io.trigger_pkt_any[1].tdata2, 28, 28) @[el2_lib.scala 244:74] + node _T_515 = bits(lsu_match_data_1, 28, 28) @[el2_lib.scala 244:86] + node _T_516 = eq(_T_514, _T_515) @[el2_lib.scala 244:78] + node _T_517 = mux(_T_513, UInt<1>("h01"), _T_516) @[el2_lib.scala 244:23] + _T_314[28] <= _T_517 @[el2_lib.scala 244:17] + node _T_518 = bits(io.trigger_pkt_any[1].tdata2, 28, 0) @[el2_lib.scala 244:28] + node _T_519 = andr(_T_518) @[el2_lib.scala 244:36] + node _T_520 = and(_T_519, _T_317) @[el2_lib.scala 244:41] + node _T_521 = bits(io.trigger_pkt_any[1].tdata2, 29, 29) @[el2_lib.scala 244:74] + node _T_522 = bits(lsu_match_data_1, 29, 29) @[el2_lib.scala 244:86] + node _T_523 = eq(_T_521, _T_522) @[el2_lib.scala 244:78] + node _T_524 = mux(_T_520, UInt<1>("h01"), _T_523) @[el2_lib.scala 244:23] + _T_314[29] <= _T_524 @[el2_lib.scala 244:17] + node _T_525 = bits(io.trigger_pkt_any[1].tdata2, 29, 0) @[el2_lib.scala 244:28] + node _T_526 = andr(_T_525) @[el2_lib.scala 244:36] + node _T_527 = and(_T_526, _T_317) @[el2_lib.scala 244:41] + node _T_528 = bits(io.trigger_pkt_any[1].tdata2, 30, 30) @[el2_lib.scala 244:74] + node _T_529 = bits(lsu_match_data_1, 30, 30) @[el2_lib.scala 244:86] + node _T_530 = eq(_T_528, _T_529) @[el2_lib.scala 244:78] + node _T_531 = mux(_T_527, UInt<1>("h01"), _T_530) @[el2_lib.scala 244:23] + _T_314[30] <= _T_531 @[el2_lib.scala 244:17] + node _T_532 = bits(io.trigger_pkt_any[1].tdata2, 30, 0) @[el2_lib.scala 244:28] + node _T_533 = andr(_T_532) @[el2_lib.scala 244:36] + node _T_534 = and(_T_533, _T_317) @[el2_lib.scala 244:41] + node _T_535 = bits(io.trigger_pkt_any[1].tdata2, 31, 31) @[el2_lib.scala 244:74] + node _T_536 = bits(lsu_match_data_1, 31, 31) @[el2_lib.scala 244:86] + node _T_537 = eq(_T_535, _T_536) @[el2_lib.scala 244:78] + node _T_538 = mux(_T_534, UInt<1>("h01"), _T_537) @[el2_lib.scala 244:23] + _T_314[31] <= _T_538 @[el2_lib.scala 244:17] + node _T_539 = cat(_T_314[1], _T_314[0]) @[el2_lib.scala 245:14] + node _T_540 = cat(_T_314[3], _T_314[2]) @[el2_lib.scala 245:14] + node _T_541 = cat(_T_540, _T_539) @[el2_lib.scala 245:14] + node _T_542 = cat(_T_314[5], _T_314[4]) @[el2_lib.scala 245:14] + node _T_543 = cat(_T_314[7], _T_314[6]) @[el2_lib.scala 245:14] + node _T_544 = cat(_T_543, _T_542) @[el2_lib.scala 245:14] + node _T_545 = cat(_T_544, _T_541) @[el2_lib.scala 245:14] + node _T_546 = cat(_T_314[9], _T_314[8]) @[el2_lib.scala 245:14] + node _T_547 = cat(_T_314[11], _T_314[10]) @[el2_lib.scala 245:14] + node _T_548 = cat(_T_547, _T_546) @[el2_lib.scala 245:14] + node _T_549 = cat(_T_314[13], _T_314[12]) @[el2_lib.scala 245:14] + node _T_550 = cat(_T_314[15], _T_314[14]) @[el2_lib.scala 245:14] + node _T_551 = cat(_T_550, _T_549) @[el2_lib.scala 245:14] + node _T_552 = cat(_T_551, _T_548) @[el2_lib.scala 245:14] + node _T_553 = cat(_T_552, _T_545) @[el2_lib.scala 245:14] + node _T_554 = cat(_T_314[17], _T_314[16]) @[el2_lib.scala 245:14] + node _T_555 = cat(_T_314[19], _T_314[18]) @[el2_lib.scala 245:14] + node _T_556 = cat(_T_555, _T_554) @[el2_lib.scala 245:14] + node _T_557 = cat(_T_314[21], _T_314[20]) @[el2_lib.scala 245:14] + node _T_558 = cat(_T_314[23], _T_314[22]) @[el2_lib.scala 245:14] + node _T_559 = cat(_T_558, _T_557) @[el2_lib.scala 245:14] + node _T_560 = cat(_T_559, _T_556) @[el2_lib.scala 245:14] + node _T_561 = cat(_T_314[25], _T_314[24]) @[el2_lib.scala 245:14] + node _T_562 = cat(_T_314[27], _T_314[26]) @[el2_lib.scala 245:14] + node _T_563 = cat(_T_562, _T_561) @[el2_lib.scala 245:14] + node _T_564 = cat(_T_314[29], _T_314[28]) @[el2_lib.scala 245:14] + node _T_565 = cat(_T_314[31], _T_314[30]) @[el2_lib.scala 245:14] + node _T_566 = cat(_T_565, _T_564) @[el2_lib.scala 245:14] + node _T_567 = cat(_T_566, _T_563) @[el2_lib.scala 245:14] + node _T_568 = cat(_T_567, _T_560) @[el2_lib.scala 245:14] + node _T_569 = cat(_T_568, _T_553) @[el2_lib.scala 245:14] + node _T_570 = and(_T_312, _T_569) @[el2_lsu_trigger.scala 19:92] + node _T_571 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[el2_lsu_trigger.scala 18:71] + node _T_572 = and(io.lsu_pkt_m.valid, _T_571) @[el2_lsu_trigger.scala 18:69] + node _T_573 = and(io.trigger_pkt_any[2].store, io.lsu_pkt_m.bits.store) @[el2_lsu_trigger.scala 18:126] + node _T_574 = and(io.trigger_pkt_any[2].load, io.lsu_pkt_m.bits.load) @[el2_lsu_trigger.scala 19:33] + node _T_575 = eq(io.trigger_pkt_any[2].select, UInt<1>("h00")) @[el2_lsu_trigger.scala 19:60] + node _T_576 = and(_T_574, _T_575) @[el2_lsu_trigger.scala 19:58] + node _T_577 = or(_T_573, _T_576) @[el2_lsu_trigger.scala 18:152] + node _T_578 = and(_T_572, _T_577) @[el2_lsu_trigger.scala 18:94] + node _T_579 = bits(io.trigger_pkt_any[2].match_pkt, 0, 0) @[el2_lsu_trigger.scala 20:107] + wire _T_580 : UInt<1>[32] @[el2_lib.scala 240:24] + node _T_581 = andr(io.trigger_pkt_any[2].tdata2) @[el2_lib.scala 241:45] + node _T_582 = not(_T_581) @[el2_lib.scala 241:39] + node _T_583 = and(_T_579, _T_582) @[el2_lib.scala 241:37] + node _T_584 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[el2_lib.scala 242:48] + node _T_585 = bits(lsu_match_data_2, 0, 0) @[el2_lib.scala 242:60] + node _T_586 = eq(_T_584, _T_585) @[el2_lib.scala 242:52] + node _T_587 = or(_T_583, _T_586) @[el2_lib.scala 242:41] + _T_580[0] <= _T_587 @[el2_lib.scala 242:18] + node _T_588 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[el2_lib.scala 244:28] + node _T_589 = andr(_T_588) @[el2_lib.scala 244:36] + node _T_590 = and(_T_589, _T_583) @[el2_lib.scala 244:41] + node _T_591 = bits(io.trigger_pkt_any[2].tdata2, 1, 1) @[el2_lib.scala 244:74] + node _T_592 = bits(lsu_match_data_2, 1, 1) @[el2_lib.scala 244:86] + node _T_593 = eq(_T_591, _T_592) @[el2_lib.scala 244:78] + node _T_594 = mux(_T_590, UInt<1>("h01"), _T_593) @[el2_lib.scala 244:23] + _T_580[1] <= _T_594 @[el2_lib.scala 244:17] + node _T_595 = bits(io.trigger_pkt_any[2].tdata2, 1, 0) @[el2_lib.scala 244:28] + node _T_596 = andr(_T_595) @[el2_lib.scala 244:36] + node _T_597 = and(_T_596, _T_583) @[el2_lib.scala 244:41] + node _T_598 = bits(io.trigger_pkt_any[2].tdata2, 2, 2) @[el2_lib.scala 244:74] + node _T_599 = bits(lsu_match_data_2, 2, 2) @[el2_lib.scala 244:86] + node _T_600 = eq(_T_598, _T_599) @[el2_lib.scala 244:78] + node _T_601 = mux(_T_597, UInt<1>("h01"), _T_600) @[el2_lib.scala 244:23] + _T_580[2] <= _T_601 @[el2_lib.scala 244:17] + node _T_602 = bits(io.trigger_pkt_any[2].tdata2, 2, 0) @[el2_lib.scala 244:28] + node _T_603 = andr(_T_602) @[el2_lib.scala 244:36] + node _T_604 = and(_T_603, _T_583) @[el2_lib.scala 244:41] + node _T_605 = bits(io.trigger_pkt_any[2].tdata2, 3, 3) @[el2_lib.scala 244:74] + node _T_606 = bits(lsu_match_data_2, 3, 3) @[el2_lib.scala 244:86] + node _T_607 = eq(_T_605, _T_606) @[el2_lib.scala 244:78] + node _T_608 = mux(_T_604, UInt<1>("h01"), _T_607) @[el2_lib.scala 244:23] + _T_580[3] <= _T_608 @[el2_lib.scala 244:17] + node _T_609 = bits(io.trigger_pkt_any[2].tdata2, 3, 0) @[el2_lib.scala 244:28] + node _T_610 = andr(_T_609) @[el2_lib.scala 244:36] + node _T_611 = and(_T_610, _T_583) @[el2_lib.scala 244:41] + node _T_612 = bits(io.trigger_pkt_any[2].tdata2, 4, 4) @[el2_lib.scala 244:74] + node _T_613 = bits(lsu_match_data_2, 4, 4) @[el2_lib.scala 244:86] + node _T_614 = eq(_T_612, _T_613) @[el2_lib.scala 244:78] + node _T_615 = mux(_T_611, UInt<1>("h01"), _T_614) @[el2_lib.scala 244:23] + _T_580[4] <= _T_615 @[el2_lib.scala 244:17] + node _T_616 = bits(io.trigger_pkt_any[2].tdata2, 4, 0) @[el2_lib.scala 244:28] + node _T_617 = andr(_T_616) @[el2_lib.scala 244:36] + node _T_618 = and(_T_617, _T_583) @[el2_lib.scala 244:41] + node _T_619 = bits(io.trigger_pkt_any[2].tdata2, 5, 5) @[el2_lib.scala 244:74] + node _T_620 = bits(lsu_match_data_2, 5, 5) @[el2_lib.scala 244:86] + node _T_621 = eq(_T_619, _T_620) @[el2_lib.scala 244:78] + node _T_622 = mux(_T_618, UInt<1>("h01"), _T_621) @[el2_lib.scala 244:23] + _T_580[5] <= _T_622 @[el2_lib.scala 244:17] + node _T_623 = bits(io.trigger_pkt_any[2].tdata2, 5, 0) @[el2_lib.scala 244:28] + node _T_624 = andr(_T_623) @[el2_lib.scala 244:36] + node _T_625 = and(_T_624, _T_583) @[el2_lib.scala 244:41] + node _T_626 = bits(io.trigger_pkt_any[2].tdata2, 6, 6) @[el2_lib.scala 244:74] + node _T_627 = bits(lsu_match_data_2, 6, 6) @[el2_lib.scala 244:86] + node _T_628 = eq(_T_626, _T_627) @[el2_lib.scala 244:78] + node _T_629 = mux(_T_625, UInt<1>("h01"), _T_628) @[el2_lib.scala 244:23] + _T_580[6] <= _T_629 @[el2_lib.scala 244:17] + node _T_630 = bits(io.trigger_pkt_any[2].tdata2, 6, 0) @[el2_lib.scala 244:28] + node _T_631 = andr(_T_630) @[el2_lib.scala 244:36] + node _T_632 = and(_T_631, _T_583) @[el2_lib.scala 244:41] + node _T_633 = bits(io.trigger_pkt_any[2].tdata2, 7, 7) @[el2_lib.scala 244:74] + node _T_634 = bits(lsu_match_data_2, 7, 7) @[el2_lib.scala 244:86] + node _T_635 = eq(_T_633, _T_634) @[el2_lib.scala 244:78] + node _T_636 = mux(_T_632, UInt<1>("h01"), _T_635) @[el2_lib.scala 244:23] + _T_580[7] <= _T_636 @[el2_lib.scala 244:17] + node _T_637 = bits(io.trigger_pkt_any[2].tdata2, 7, 0) @[el2_lib.scala 244:28] + node _T_638 = andr(_T_637) @[el2_lib.scala 244:36] + node _T_639 = and(_T_638, _T_583) @[el2_lib.scala 244:41] + node _T_640 = bits(io.trigger_pkt_any[2].tdata2, 8, 8) @[el2_lib.scala 244:74] + node _T_641 = bits(lsu_match_data_2, 8, 8) @[el2_lib.scala 244:86] + node _T_642 = eq(_T_640, _T_641) @[el2_lib.scala 244:78] + node _T_643 = mux(_T_639, UInt<1>("h01"), _T_642) @[el2_lib.scala 244:23] + _T_580[8] <= _T_643 @[el2_lib.scala 244:17] + node _T_644 = bits(io.trigger_pkt_any[2].tdata2, 8, 0) @[el2_lib.scala 244:28] + node _T_645 = andr(_T_644) @[el2_lib.scala 244:36] + node _T_646 = and(_T_645, _T_583) @[el2_lib.scala 244:41] + node _T_647 = bits(io.trigger_pkt_any[2].tdata2, 9, 9) @[el2_lib.scala 244:74] + node _T_648 = bits(lsu_match_data_2, 9, 9) @[el2_lib.scala 244:86] + node _T_649 = eq(_T_647, _T_648) @[el2_lib.scala 244:78] + node _T_650 = mux(_T_646, UInt<1>("h01"), _T_649) @[el2_lib.scala 244:23] + _T_580[9] <= _T_650 @[el2_lib.scala 244:17] + node _T_651 = bits(io.trigger_pkt_any[2].tdata2, 9, 0) @[el2_lib.scala 244:28] + node _T_652 = andr(_T_651) @[el2_lib.scala 244:36] + node _T_653 = and(_T_652, _T_583) @[el2_lib.scala 244:41] + node _T_654 = bits(io.trigger_pkt_any[2].tdata2, 10, 10) @[el2_lib.scala 244:74] + node _T_655 = bits(lsu_match_data_2, 10, 10) @[el2_lib.scala 244:86] + node _T_656 = eq(_T_654, _T_655) @[el2_lib.scala 244:78] + node _T_657 = mux(_T_653, UInt<1>("h01"), _T_656) @[el2_lib.scala 244:23] + _T_580[10] <= _T_657 @[el2_lib.scala 244:17] + node _T_658 = bits(io.trigger_pkt_any[2].tdata2, 10, 0) @[el2_lib.scala 244:28] + node _T_659 = andr(_T_658) @[el2_lib.scala 244:36] + node _T_660 = and(_T_659, _T_583) @[el2_lib.scala 244:41] + node _T_661 = bits(io.trigger_pkt_any[2].tdata2, 11, 11) @[el2_lib.scala 244:74] + node _T_662 = bits(lsu_match_data_2, 11, 11) @[el2_lib.scala 244:86] + node _T_663 = eq(_T_661, _T_662) @[el2_lib.scala 244:78] + node _T_664 = mux(_T_660, UInt<1>("h01"), _T_663) @[el2_lib.scala 244:23] + _T_580[11] <= _T_664 @[el2_lib.scala 244:17] + node _T_665 = bits(io.trigger_pkt_any[2].tdata2, 11, 0) @[el2_lib.scala 244:28] + node _T_666 = andr(_T_665) @[el2_lib.scala 244:36] + node _T_667 = and(_T_666, _T_583) @[el2_lib.scala 244:41] + node _T_668 = bits(io.trigger_pkt_any[2].tdata2, 12, 12) @[el2_lib.scala 244:74] + node _T_669 = bits(lsu_match_data_2, 12, 12) @[el2_lib.scala 244:86] + node _T_670 = eq(_T_668, _T_669) @[el2_lib.scala 244:78] + node _T_671 = mux(_T_667, UInt<1>("h01"), _T_670) @[el2_lib.scala 244:23] + _T_580[12] <= _T_671 @[el2_lib.scala 244:17] + node _T_672 = bits(io.trigger_pkt_any[2].tdata2, 12, 0) @[el2_lib.scala 244:28] + node _T_673 = andr(_T_672) @[el2_lib.scala 244:36] + node _T_674 = and(_T_673, _T_583) @[el2_lib.scala 244:41] + node _T_675 = bits(io.trigger_pkt_any[2].tdata2, 13, 13) @[el2_lib.scala 244:74] + node _T_676 = bits(lsu_match_data_2, 13, 13) @[el2_lib.scala 244:86] + node _T_677 = eq(_T_675, _T_676) @[el2_lib.scala 244:78] + node _T_678 = mux(_T_674, UInt<1>("h01"), _T_677) @[el2_lib.scala 244:23] + _T_580[13] <= _T_678 @[el2_lib.scala 244:17] + node _T_679 = bits(io.trigger_pkt_any[2].tdata2, 13, 0) @[el2_lib.scala 244:28] + node _T_680 = andr(_T_679) @[el2_lib.scala 244:36] + node _T_681 = and(_T_680, _T_583) @[el2_lib.scala 244:41] + node _T_682 = bits(io.trigger_pkt_any[2].tdata2, 14, 14) @[el2_lib.scala 244:74] + node _T_683 = bits(lsu_match_data_2, 14, 14) @[el2_lib.scala 244:86] + node _T_684 = eq(_T_682, _T_683) @[el2_lib.scala 244:78] + node _T_685 = mux(_T_681, UInt<1>("h01"), _T_684) @[el2_lib.scala 244:23] + _T_580[14] <= _T_685 @[el2_lib.scala 244:17] + node _T_686 = bits(io.trigger_pkt_any[2].tdata2, 14, 0) @[el2_lib.scala 244:28] + node _T_687 = andr(_T_686) @[el2_lib.scala 244:36] + node _T_688 = and(_T_687, _T_583) @[el2_lib.scala 244:41] + node _T_689 = bits(io.trigger_pkt_any[2].tdata2, 15, 15) @[el2_lib.scala 244:74] + node _T_690 = bits(lsu_match_data_2, 15, 15) @[el2_lib.scala 244:86] + node _T_691 = eq(_T_689, _T_690) @[el2_lib.scala 244:78] + node _T_692 = mux(_T_688, UInt<1>("h01"), _T_691) @[el2_lib.scala 244:23] + _T_580[15] <= _T_692 @[el2_lib.scala 244:17] + node _T_693 = bits(io.trigger_pkt_any[2].tdata2, 15, 0) @[el2_lib.scala 244:28] + node _T_694 = andr(_T_693) @[el2_lib.scala 244:36] + node _T_695 = and(_T_694, _T_583) @[el2_lib.scala 244:41] + node _T_696 = bits(io.trigger_pkt_any[2].tdata2, 16, 16) @[el2_lib.scala 244:74] + node _T_697 = bits(lsu_match_data_2, 16, 16) @[el2_lib.scala 244:86] + node _T_698 = eq(_T_696, _T_697) @[el2_lib.scala 244:78] + node _T_699 = mux(_T_695, UInt<1>("h01"), _T_698) @[el2_lib.scala 244:23] + _T_580[16] <= _T_699 @[el2_lib.scala 244:17] + node _T_700 = bits(io.trigger_pkt_any[2].tdata2, 16, 0) @[el2_lib.scala 244:28] + node _T_701 = andr(_T_700) @[el2_lib.scala 244:36] + node _T_702 = and(_T_701, _T_583) @[el2_lib.scala 244:41] + node _T_703 = bits(io.trigger_pkt_any[2].tdata2, 17, 17) @[el2_lib.scala 244:74] + node _T_704 = bits(lsu_match_data_2, 17, 17) @[el2_lib.scala 244:86] + node _T_705 = eq(_T_703, _T_704) @[el2_lib.scala 244:78] + node _T_706 = mux(_T_702, UInt<1>("h01"), _T_705) @[el2_lib.scala 244:23] + _T_580[17] <= _T_706 @[el2_lib.scala 244:17] + node _T_707 = bits(io.trigger_pkt_any[2].tdata2, 17, 0) @[el2_lib.scala 244:28] + node _T_708 = andr(_T_707) @[el2_lib.scala 244:36] + node _T_709 = and(_T_708, _T_583) @[el2_lib.scala 244:41] + node _T_710 = bits(io.trigger_pkt_any[2].tdata2, 18, 18) @[el2_lib.scala 244:74] + node _T_711 = bits(lsu_match_data_2, 18, 18) @[el2_lib.scala 244:86] + node _T_712 = eq(_T_710, _T_711) @[el2_lib.scala 244:78] + node _T_713 = mux(_T_709, UInt<1>("h01"), _T_712) @[el2_lib.scala 244:23] + _T_580[18] <= _T_713 @[el2_lib.scala 244:17] + node _T_714 = bits(io.trigger_pkt_any[2].tdata2, 18, 0) @[el2_lib.scala 244:28] + node _T_715 = andr(_T_714) @[el2_lib.scala 244:36] + node _T_716 = and(_T_715, _T_583) @[el2_lib.scala 244:41] + node _T_717 = bits(io.trigger_pkt_any[2].tdata2, 19, 19) @[el2_lib.scala 244:74] + node _T_718 = bits(lsu_match_data_2, 19, 19) @[el2_lib.scala 244:86] + node _T_719 = eq(_T_717, _T_718) @[el2_lib.scala 244:78] + node _T_720 = mux(_T_716, UInt<1>("h01"), _T_719) @[el2_lib.scala 244:23] + _T_580[19] <= _T_720 @[el2_lib.scala 244:17] + node _T_721 = bits(io.trigger_pkt_any[2].tdata2, 19, 0) @[el2_lib.scala 244:28] + node _T_722 = andr(_T_721) @[el2_lib.scala 244:36] + node _T_723 = and(_T_722, _T_583) @[el2_lib.scala 244:41] + node _T_724 = bits(io.trigger_pkt_any[2].tdata2, 20, 20) @[el2_lib.scala 244:74] + node _T_725 = bits(lsu_match_data_2, 20, 20) @[el2_lib.scala 244:86] + node _T_726 = eq(_T_724, _T_725) @[el2_lib.scala 244:78] + node _T_727 = mux(_T_723, UInt<1>("h01"), _T_726) @[el2_lib.scala 244:23] + _T_580[20] <= _T_727 @[el2_lib.scala 244:17] + node _T_728 = bits(io.trigger_pkt_any[2].tdata2, 20, 0) @[el2_lib.scala 244:28] + node _T_729 = andr(_T_728) @[el2_lib.scala 244:36] + node _T_730 = and(_T_729, _T_583) @[el2_lib.scala 244:41] + node _T_731 = bits(io.trigger_pkt_any[2].tdata2, 21, 21) @[el2_lib.scala 244:74] + node _T_732 = bits(lsu_match_data_2, 21, 21) @[el2_lib.scala 244:86] + node _T_733 = eq(_T_731, _T_732) @[el2_lib.scala 244:78] + node _T_734 = mux(_T_730, UInt<1>("h01"), _T_733) @[el2_lib.scala 244:23] + _T_580[21] <= _T_734 @[el2_lib.scala 244:17] + node _T_735 = bits(io.trigger_pkt_any[2].tdata2, 21, 0) @[el2_lib.scala 244:28] + node _T_736 = andr(_T_735) @[el2_lib.scala 244:36] + node _T_737 = and(_T_736, _T_583) @[el2_lib.scala 244:41] + node _T_738 = bits(io.trigger_pkt_any[2].tdata2, 22, 22) @[el2_lib.scala 244:74] + node _T_739 = bits(lsu_match_data_2, 22, 22) @[el2_lib.scala 244:86] + node _T_740 = eq(_T_738, _T_739) @[el2_lib.scala 244:78] + node _T_741 = mux(_T_737, UInt<1>("h01"), _T_740) @[el2_lib.scala 244:23] + _T_580[22] <= _T_741 @[el2_lib.scala 244:17] + node _T_742 = bits(io.trigger_pkt_any[2].tdata2, 22, 0) @[el2_lib.scala 244:28] + node _T_743 = andr(_T_742) @[el2_lib.scala 244:36] + node _T_744 = and(_T_743, _T_583) @[el2_lib.scala 244:41] + node _T_745 = bits(io.trigger_pkt_any[2].tdata2, 23, 23) @[el2_lib.scala 244:74] + node _T_746 = bits(lsu_match_data_2, 23, 23) @[el2_lib.scala 244:86] + node _T_747 = eq(_T_745, _T_746) @[el2_lib.scala 244:78] + node _T_748 = mux(_T_744, UInt<1>("h01"), _T_747) @[el2_lib.scala 244:23] + _T_580[23] <= _T_748 @[el2_lib.scala 244:17] + node _T_749 = bits(io.trigger_pkt_any[2].tdata2, 23, 0) @[el2_lib.scala 244:28] + node _T_750 = andr(_T_749) @[el2_lib.scala 244:36] + node _T_751 = and(_T_750, _T_583) @[el2_lib.scala 244:41] + node _T_752 = bits(io.trigger_pkt_any[2].tdata2, 24, 24) @[el2_lib.scala 244:74] + node _T_753 = bits(lsu_match_data_2, 24, 24) @[el2_lib.scala 244:86] + node _T_754 = eq(_T_752, _T_753) @[el2_lib.scala 244:78] + node _T_755 = mux(_T_751, UInt<1>("h01"), _T_754) @[el2_lib.scala 244:23] + _T_580[24] <= _T_755 @[el2_lib.scala 244:17] + node _T_756 = bits(io.trigger_pkt_any[2].tdata2, 24, 0) @[el2_lib.scala 244:28] + node _T_757 = andr(_T_756) @[el2_lib.scala 244:36] + node _T_758 = and(_T_757, _T_583) @[el2_lib.scala 244:41] + node _T_759 = bits(io.trigger_pkt_any[2].tdata2, 25, 25) @[el2_lib.scala 244:74] + node _T_760 = bits(lsu_match_data_2, 25, 25) @[el2_lib.scala 244:86] + node _T_761 = eq(_T_759, _T_760) @[el2_lib.scala 244:78] + node _T_762 = mux(_T_758, UInt<1>("h01"), _T_761) @[el2_lib.scala 244:23] + _T_580[25] <= _T_762 @[el2_lib.scala 244:17] + node _T_763 = bits(io.trigger_pkt_any[2].tdata2, 25, 0) @[el2_lib.scala 244:28] + node _T_764 = andr(_T_763) @[el2_lib.scala 244:36] + node _T_765 = and(_T_764, _T_583) @[el2_lib.scala 244:41] + node _T_766 = bits(io.trigger_pkt_any[2].tdata2, 26, 26) @[el2_lib.scala 244:74] + node _T_767 = bits(lsu_match_data_2, 26, 26) @[el2_lib.scala 244:86] + node _T_768 = eq(_T_766, _T_767) @[el2_lib.scala 244:78] + node _T_769 = mux(_T_765, UInt<1>("h01"), _T_768) @[el2_lib.scala 244:23] + _T_580[26] <= _T_769 @[el2_lib.scala 244:17] + node _T_770 = bits(io.trigger_pkt_any[2].tdata2, 26, 0) @[el2_lib.scala 244:28] + node _T_771 = andr(_T_770) @[el2_lib.scala 244:36] + node _T_772 = and(_T_771, _T_583) @[el2_lib.scala 244:41] + node _T_773 = bits(io.trigger_pkt_any[2].tdata2, 27, 27) @[el2_lib.scala 244:74] + node _T_774 = bits(lsu_match_data_2, 27, 27) @[el2_lib.scala 244:86] + node _T_775 = eq(_T_773, _T_774) @[el2_lib.scala 244:78] + node _T_776 = mux(_T_772, UInt<1>("h01"), _T_775) @[el2_lib.scala 244:23] + _T_580[27] <= _T_776 @[el2_lib.scala 244:17] + node _T_777 = bits(io.trigger_pkt_any[2].tdata2, 27, 0) @[el2_lib.scala 244:28] + node _T_778 = andr(_T_777) @[el2_lib.scala 244:36] + node _T_779 = and(_T_778, _T_583) @[el2_lib.scala 244:41] + node _T_780 = bits(io.trigger_pkt_any[2].tdata2, 28, 28) @[el2_lib.scala 244:74] + node _T_781 = bits(lsu_match_data_2, 28, 28) @[el2_lib.scala 244:86] + node _T_782 = eq(_T_780, _T_781) @[el2_lib.scala 244:78] + node _T_783 = mux(_T_779, UInt<1>("h01"), _T_782) @[el2_lib.scala 244:23] + _T_580[28] <= _T_783 @[el2_lib.scala 244:17] + node _T_784 = bits(io.trigger_pkt_any[2].tdata2, 28, 0) @[el2_lib.scala 244:28] + node _T_785 = andr(_T_784) @[el2_lib.scala 244:36] + node _T_786 = and(_T_785, _T_583) @[el2_lib.scala 244:41] + node _T_787 = bits(io.trigger_pkt_any[2].tdata2, 29, 29) @[el2_lib.scala 244:74] + node _T_788 = bits(lsu_match_data_2, 29, 29) @[el2_lib.scala 244:86] + node _T_789 = eq(_T_787, _T_788) @[el2_lib.scala 244:78] + node _T_790 = mux(_T_786, UInt<1>("h01"), _T_789) @[el2_lib.scala 244:23] + _T_580[29] <= _T_790 @[el2_lib.scala 244:17] + node _T_791 = bits(io.trigger_pkt_any[2].tdata2, 29, 0) @[el2_lib.scala 244:28] + node _T_792 = andr(_T_791) @[el2_lib.scala 244:36] + node _T_793 = and(_T_792, _T_583) @[el2_lib.scala 244:41] + node _T_794 = bits(io.trigger_pkt_any[2].tdata2, 30, 30) @[el2_lib.scala 244:74] + node _T_795 = bits(lsu_match_data_2, 30, 30) @[el2_lib.scala 244:86] + node _T_796 = eq(_T_794, _T_795) @[el2_lib.scala 244:78] + node _T_797 = mux(_T_793, UInt<1>("h01"), _T_796) @[el2_lib.scala 244:23] + _T_580[30] <= _T_797 @[el2_lib.scala 244:17] + node _T_798 = bits(io.trigger_pkt_any[2].tdata2, 30, 0) @[el2_lib.scala 244:28] + node _T_799 = andr(_T_798) @[el2_lib.scala 244:36] + node _T_800 = and(_T_799, _T_583) @[el2_lib.scala 244:41] + node _T_801 = bits(io.trigger_pkt_any[2].tdata2, 31, 31) @[el2_lib.scala 244:74] + node _T_802 = bits(lsu_match_data_2, 31, 31) @[el2_lib.scala 244:86] + node _T_803 = eq(_T_801, _T_802) @[el2_lib.scala 244:78] + node _T_804 = mux(_T_800, UInt<1>("h01"), _T_803) @[el2_lib.scala 244:23] + _T_580[31] <= _T_804 @[el2_lib.scala 244:17] + node _T_805 = cat(_T_580[1], _T_580[0]) @[el2_lib.scala 245:14] + node _T_806 = cat(_T_580[3], _T_580[2]) @[el2_lib.scala 245:14] + node _T_807 = cat(_T_806, _T_805) @[el2_lib.scala 245:14] + node _T_808 = cat(_T_580[5], _T_580[4]) @[el2_lib.scala 245:14] + node _T_809 = cat(_T_580[7], _T_580[6]) @[el2_lib.scala 245:14] + node _T_810 = cat(_T_809, _T_808) @[el2_lib.scala 245:14] + node _T_811 = cat(_T_810, _T_807) @[el2_lib.scala 245:14] + node _T_812 = cat(_T_580[9], _T_580[8]) @[el2_lib.scala 245:14] + node _T_813 = cat(_T_580[11], _T_580[10]) @[el2_lib.scala 245:14] + node _T_814 = cat(_T_813, _T_812) @[el2_lib.scala 245:14] + node _T_815 = cat(_T_580[13], _T_580[12]) @[el2_lib.scala 245:14] + node _T_816 = cat(_T_580[15], _T_580[14]) @[el2_lib.scala 245:14] + node _T_817 = cat(_T_816, _T_815) @[el2_lib.scala 245:14] + node _T_818 = cat(_T_817, _T_814) @[el2_lib.scala 245:14] + node _T_819 = cat(_T_818, _T_811) @[el2_lib.scala 245:14] + node _T_820 = cat(_T_580[17], _T_580[16]) @[el2_lib.scala 245:14] + node _T_821 = cat(_T_580[19], _T_580[18]) @[el2_lib.scala 245:14] + node _T_822 = cat(_T_821, _T_820) @[el2_lib.scala 245:14] + node _T_823 = cat(_T_580[21], _T_580[20]) @[el2_lib.scala 245:14] + node _T_824 = cat(_T_580[23], _T_580[22]) @[el2_lib.scala 245:14] + node _T_825 = cat(_T_824, _T_823) @[el2_lib.scala 245:14] + node _T_826 = cat(_T_825, _T_822) @[el2_lib.scala 245:14] + node _T_827 = cat(_T_580[25], _T_580[24]) @[el2_lib.scala 245:14] + node _T_828 = cat(_T_580[27], _T_580[26]) @[el2_lib.scala 245:14] + node _T_829 = cat(_T_828, _T_827) @[el2_lib.scala 245:14] + node _T_830 = cat(_T_580[29], _T_580[28]) @[el2_lib.scala 245:14] + node _T_831 = cat(_T_580[31], _T_580[30]) @[el2_lib.scala 245:14] + node _T_832 = cat(_T_831, _T_830) @[el2_lib.scala 245:14] + node _T_833 = cat(_T_832, _T_829) @[el2_lib.scala 245:14] + node _T_834 = cat(_T_833, _T_826) @[el2_lib.scala 245:14] + node _T_835 = cat(_T_834, _T_819) @[el2_lib.scala 245:14] + node _T_836 = and(_T_578, _T_835) @[el2_lsu_trigger.scala 19:92] + node _T_837 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[el2_lsu_trigger.scala 18:71] + node _T_838 = and(io.lsu_pkt_m.valid, _T_837) @[el2_lsu_trigger.scala 18:69] + node _T_839 = and(io.trigger_pkt_any[3].store, io.lsu_pkt_m.bits.store) @[el2_lsu_trigger.scala 18:126] + node _T_840 = and(io.trigger_pkt_any[3].load, io.lsu_pkt_m.bits.load) @[el2_lsu_trigger.scala 19:33] + node _T_841 = eq(io.trigger_pkt_any[3].select, UInt<1>("h00")) @[el2_lsu_trigger.scala 19:60] + node _T_842 = and(_T_840, _T_841) @[el2_lsu_trigger.scala 19:58] + node _T_843 = or(_T_839, _T_842) @[el2_lsu_trigger.scala 18:152] + node _T_844 = and(_T_838, _T_843) @[el2_lsu_trigger.scala 18:94] + node _T_845 = bits(io.trigger_pkt_any[3].match_pkt, 0, 0) @[el2_lsu_trigger.scala 20:107] + wire _T_846 : UInt<1>[32] @[el2_lib.scala 240:24] + node _T_847 = andr(io.trigger_pkt_any[3].tdata2) @[el2_lib.scala 241:45] + node _T_848 = not(_T_847) @[el2_lib.scala 241:39] + node _T_849 = and(_T_845, _T_848) @[el2_lib.scala 241:37] + node _T_850 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[el2_lib.scala 242:48] + node _T_851 = bits(lsu_match_data_3, 0, 0) @[el2_lib.scala 242:60] + node _T_852 = eq(_T_850, _T_851) @[el2_lib.scala 242:52] + node _T_853 = or(_T_849, _T_852) @[el2_lib.scala 242:41] + _T_846[0] <= _T_853 @[el2_lib.scala 242:18] + node _T_854 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[el2_lib.scala 244:28] + node _T_855 = andr(_T_854) @[el2_lib.scala 244:36] + node _T_856 = and(_T_855, _T_849) @[el2_lib.scala 244:41] + node _T_857 = bits(io.trigger_pkt_any[3].tdata2, 1, 1) @[el2_lib.scala 244:74] + node _T_858 = bits(lsu_match_data_3, 1, 1) @[el2_lib.scala 244:86] + node _T_859 = eq(_T_857, _T_858) @[el2_lib.scala 244:78] + node _T_860 = mux(_T_856, UInt<1>("h01"), _T_859) @[el2_lib.scala 244:23] + _T_846[1] <= _T_860 @[el2_lib.scala 244:17] + node _T_861 = bits(io.trigger_pkt_any[3].tdata2, 1, 0) @[el2_lib.scala 244:28] + node _T_862 = andr(_T_861) @[el2_lib.scala 244:36] + node _T_863 = and(_T_862, _T_849) @[el2_lib.scala 244:41] + node _T_864 = bits(io.trigger_pkt_any[3].tdata2, 2, 2) @[el2_lib.scala 244:74] + node _T_865 = bits(lsu_match_data_3, 2, 2) @[el2_lib.scala 244:86] + node _T_866 = eq(_T_864, _T_865) @[el2_lib.scala 244:78] + node _T_867 = mux(_T_863, UInt<1>("h01"), _T_866) @[el2_lib.scala 244:23] + _T_846[2] <= _T_867 @[el2_lib.scala 244:17] + node _T_868 = bits(io.trigger_pkt_any[3].tdata2, 2, 0) @[el2_lib.scala 244:28] + node _T_869 = andr(_T_868) @[el2_lib.scala 244:36] + node _T_870 = and(_T_869, _T_849) @[el2_lib.scala 244:41] + node _T_871 = bits(io.trigger_pkt_any[3].tdata2, 3, 3) @[el2_lib.scala 244:74] + node _T_872 = bits(lsu_match_data_3, 3, 3) @[el2_lib.scala 244:86] + node _T_873 = eq(_T_871, _T_872) @[el2_lib.scala 244:78] + node _T_874 = mux(_T_870, UInt<1>("h01"), _T_873) @[el2_lib.scala 244:23] + _T_846[3] <= _T_874 @[el2_lib.scala 244:17] + node _T_875 = bits(io.trigger_pkt_any[3].tdata2, 3, 0) @[el2_lib.scala 244:28] + node _T_876 = andr(_T_875) @[el2_lib.scala 244:36] + node _T_877 = and(_T_876, _T_849) @[el2_lib.scala 244:41] + node _T_878 = bits(io.trigger_pkt_any[3].tdata2, 4, 4) @[el2_lib.scala 244:74] + node _T_879 = bits(lsu_match_data_3, 4, 4) @[el2_lib.scala 244:86] + node _T_880 = eq(_T_878, _T_879) @[el2_lib.scala 244:78] + node _T_881 = mux(_T_877, UInt<1>("h01"), _T_880) @[el2_lib.scala 244:23] + _T_846[4] <= _T_881 @[el2_lib.scala 244:17] + node _T_882 = bits(io.trigger_pkt_any[3].tdata2, 4, 0) @[el2_lib.scala 244:28] + node _T_883 = andr(_T_882) @[el2_lib.scala 244:36] + node _T_884 = and(_T_883, _T_849) @[el2_lib.scala 244:41] + node _T_885 = bits(io.trigger_pkt_any[3].tdata2, 5, 5) @[el2_lib.scala 244:74] + node _T_886 = bits(lsu_match_data_3, 5, 5) @[el2_lib.scala 244:86] + node _T_887 = eq(_T_885, _T_886) @[el2_lib.scala 244:78] + node _T_888 = mux(_T_884, UInt<1>("h01"), _T_887) @[el2_lib.scala 244:23] + _T_846[5] <= _T_888 @[el2_lib.scala 244:17] + node _T_889 = bits(io.trigger_pkt_any[3].tdata2, 5, 0) @[el2_lib.scala 244:28] + node _T_890 = andr(_T_889) @[el2_lib.scala 244:36] + node _T_891 = and(_T_890, _T_849) @[el2_lib.scala 244:41] + node _T_892 = bits(io.trigger_pkt_any[3].tdata2, 6, 6) @[el2_lib.scala 244:74] + node _T_893 = bits(lsu_match_data_3, 6, 6) @[el2_lib.scala 244:86] + node _T_894 = eq(_T_892, _T_893) @[el2_lib.scala 244:78] + node _T_895 = mux(_T_891, UInt<1>("h01"), _T_894) @[el2_lib.scala 244:23] + _T_846[6] <= _T_895 @[el2_lib.scala 244:17] + node _T_896 = bits(io.trigger_pkt_any[3].tdata2, 6, 0) @[el2_lib.scala 244:28] + node _T_897 = andr(_T_896) @[el2_lib.scala 244:36] + node _T_898 = and(_T_897, _T_849) @[el2_lib.scala 244:41] + node _T_899 = bits(io.trigger_pkt_any[3].tdata2, 7, 7) @[el2_lib.scala 244:74] + node _T_900 = bits(lsu_match_data_3, 7, 7) @[el2_lib.scala 244:86] + node _T_901 = eq(_T_899, _T_900) @[el2_lib.scala 244:78] + node _T_902 = mux(_T_898, UInt<1>("h01"), _T_901) @[el2_lib.scala 244:23] + _T_846[7] <= _T_902 @[el2_lib.scala 244:17] + node _T_903 = bits(io.trigger_pkt_any[3].tdata2, 7, 0) @[el2_lib.scala 244:28] + node _T_904 = andr(_T_903) @[el2_lib.scala 244:36] + node _T_905 = and(_T_904, _T_849) @[el2_lib.scala 244:41] + node _T_906 = bits(io.trigger_pkt_any[3].tdata2, 8, 8) @[el2_lib.scala 244:74] + node _T_907 = bits(lsu_match_data_3, 8, 8) @[el2_lib.scala 244:86] + node _T_908 = eq(_T_906, _T_907) @[el2_lib.scala 244:78] + node _T_909 = mux(_T_905, UInt<1>("h01"), _T_908) @[el2_lib.scala 244:23] + _T_846[8] <= _T_909 @[el2_lib.scala 244:17] + node _T_910 = bits(io.trigger_pkt_any[3].tdata2, 8, 0) @[el2_lib.scala 244:28] + node _T_911 = andr(_T_910) @[el2_lib.scala 244:36] + node _T_912 = and(_T_911, _T_849) @[el2_lib.scala 244:41] + node _T_913 = bits(io.trigger_pkt_any[3].tdata2, 9, 9) @[el2_lib.scala 244:74] + node _T_914 = bits(lsu_match_data_3, 9, 9) @[el2_lib.scala 244:86] + node _T_915 = eq(_T_913, _T_914) @[el2_lib.scala 244:78] + node _T_916 = mux(_T_912, UInt<1>("h01"), _T_915) @[el2_lib.scala 244:23] + _T_846[9] <= _T_916 @[el2_lib.scala 244:17] + node _T_917 = bits(io.trigger_pkt_any[3].tdata2, 9, 0) @[el2_lib.scala 244:28] + node _T_918 = andr(_T_917) @[el2_lib.scala 244:36] + node _T_919 = and(_T_918, _T_849) @[el2_lib.scala 244:41] + node _T_920 = bits(io.trigger_pkt_any[3].tdata2, 10, 10) @[el2_lib.scala 244:74] + node _T_921 = bits(lsu_match_data_3, 10, 10) @[el2_lib.scala 244:86] + node _T_922 = eq(_T_920, _T_921) @[el2_lib.scala 244:78] + node _T_923 = mux(_T_919, UInt<1>("h01"), _T_922) @[el2_lib.scala 244:23] + _T_846[10] <= _T_923 @[el2_lib.scala 244:17] + node _T_924 = bits(io.trigger_pkt_any[3].tdata2, 10, 0) @[el2_lib.scala 244:28] + node _T_925 = andr(_T_924) @[el2_lib.scala 244:36] + node _T_926 = and(_T_925, _T_849) @[el2_lib.scala 244:41] + node _T_927 = bits(io.trigger_pkt_any[3].tdata2, 11, 11) @[el2_lib.scala 244:74] + node _T_928 = bits(lsu_match_data_3, 11, 11) @[el2_lib.scala 244:86] + node _T_929 = eq(_T_927, _T_928) @[el2_lib.scala 244:78] + node _T_930 = mux(_T_926, UInt<1>("h01"), _T_929) @[el2_lib.scala 244:23] + _T_846[11] <= _T_930 @[el2_lib.scala 244:17] + node _T_931 = bits(io.trigger_pkt_any[3].tdata2, 11, 0) @[el2_lib.scala 244:28] + node _T_932 = andr(_T_931) @[el2_lib.scala 244:36] + node _T_933 = and(_T_932, _T_849) @[el2_lib.scala 244:41] + node _T_934 = bits(io.trigger_pkt_any[3].tdata2, 12, 12) @[el2_lib.scala 244:74] + node _T_935 = bits(lsu_match_data_3, 12, 12) @[el2_lib.scala 244:86] + node _T_936 = eq(_T_934, _T_935) @[el2_lib.scala 244:78] + node _T_937 = mux(_T_933, UInt<1>("h01"), _T_936) @[el2_lib.scala 244:23] + _T_846[12] <= _T_937 @[el2_lib.scala 244:17] + node _T_938 = bits(io.trigger_pkt_any[3].tdata2, 12, 0) @[el2_lib.scala 244:28] + node _T_939 = andr(_T_938) @[el2_lib.scala 244:36] + node _T_940 = and(_T_939, _T_849) @[el2_lib.scala 244:41] + node _T_941 = bits(io.trigger_pkt_any[3].tdata2, 13, 13) @[el2_lib.scala 244:74] + node _T_942 = bits(lsu_match_data_3, 13, 13) @[el2_lib.scala 244:86] + node _T_943 = eq(_T_941, _T_942) @[el2_lib.scala 244:78] + node _T_944 = mux(_T_940, UInt<1>("h01"), _T_943) @[el2_lib.scala 244:23] + _T_846[13] <= _T_944 @[el2_lib.scala 244:17] + node _T_945 = bits(io.trigger_pkt_any[3].tdata2, 13, 0) @[el2_lib.scala 244:28] + node _T_946 = andr(_T_945) @[el2_lib.scala 244:36] + node _T_947 = and(_T_946, _T_849) @[el2_lib.scala 244:41] + node _T_948 = bits(io.trigger_pkt_any[3].tdata2, 14, 14) @[el2_lib.scala 244:74] + node _T_949 = bits(lsu_match_data_3, 14, 14) @[el2_lib.scala 244:86] + node _T_950 = eq(_T_948, _T_949) @[el2_lib.scala 244:78] + node _T_951 = mux(_T_947, UInt<1>("h01"), _T_950) @[el2_lib.scala 244:23] + _T_846[14] <= _T_951 @[el2_lib.scala 244:17] + node _T_952 = bits(io.trigger_pkt_any[3].tdata2, 14, 0) @[el2_lib.scala 244:28] + node _T_953 = andr(_T_952) @[el2_lib.scala 244:36] + node _T_954 = and(_T_953, _T_849) @[el2_lib.scala 244:41] + node _T_955 = bits(io.trigger_pkt_any[3].tdata2, 15, 15) @[el2_lib.scala 244:74] + node _T_956 = bits(lsu_match_data_3, 15, 15) @[el2_lib.scala 244:86] + node _T_957 = eq(_T_955, _T_956) @[el2_lib.scala 244:78] + node _T_958 = mux(_T_954, UInt<1>("h01"), _T_957) @[el2_lib.scala 244:23] + _T_846[15] <= _T_958 @[el2_lib.scala 244:17] + node _T_959 = bits(io.trigger_pkt_any[3].tdata2, 15, 0) @[el2_lib.scala 244:28] + node _T_960 = andr(_T_959) @[el2_lib.scala 244:36] + node _T_961 = and(_T_960, _T_849) @[el2_lib.scala 244:41] + node _T_962 = bits(io.trigger_pkt_any[3].tdata2, 16, 16) @[el2_lib.scala 244:74] + node _T_963 = bits(lsu_match_data_3, 16, 16) @[el2_lib.scala 244:86] + node _T_964 = eq(_T_962, _T_963) @[el2_lib.scala 244:78] + node _T_965 = mux(_T_961, UInt<1>("h01"), _T_964) @[el2_lib.scala 244:23] + _T_846[16] <= _T_965 @[el2_lib.scala 244:17] + node _T_966 = bits(io.trigger_pkt_any[3].tdata2, 16, 0) @[el2_lib.scala 244:28] + node _T_967 = andr(_T_966) @[el2_lib.scala 244:36] + node _T_968 = and(_T_967, _T_849) @[el2_lib.scala 244:41] + node _T_969 = bits(io.trigger_pkt_any[3].tdata2, 17, 17) @[el2_lib.scala 244:74] + node _T_970 = bits(lsu_match_data_3, 17, 17) @[el2_lib.scala 244:86] + node _T_971 = eq(_T_969, _T_970) @[el2_lib.scala 244:78] + node _T_972 = mux(_T_968, UInt<1>("h01"), _T_971) @[el2_lib.scala 244:23] + _T_846[17] <= _T_972 @[el2_lib.scala 244:17] + node _T_973 = bits(io.trigger_pkt_any[3].tdata2, 17, 0) @[el2_lib.scala 244:28] + node _T_974 = andr(_T_973) @[el2_lib.scala 244:36] + node _T_975 = and(_T_974, _T_849) @[el2_lib.scala 244:41] + node _T_976 = bits(io.trigger_pkt_any[3].tdata2, 18, 18) @[el2_lib.scala 244:74] + node _T_977 = bits(lsu_match_data_3, 18, 18) @[el2_lib.scala 244:86] + node _T_978 = eq(_T_976, _T_977) @[el2_lib.scala 244:78] + node _T_979 = mux(_T_975, UInt<1>("h01"), _T_978) @[el2_lib.scala 244:23] + _T_846[18] <= _T_979 @[el2_lib.scala 244:17] + node _T_980 = bits(io.trigger_pkt_any[3].tdata2, 18, 0) @[el2_lib.scala 244:28] + node _T_981 = andr(_T_980) @[el2_lib.scala 244:36] + node _T_982 = and(_T_981, _T_849) @[el2_lib.scala 244:41] + node _T_983 = bits(io.trigger_pkt_any[3].tdata2, 19, 19) @[el2_lib.scala 244:74] + node _T_984 = bits(lsu_match_data_3, 19, 19) @[el2_lib.scala 244:86] + node _T_985 = eq(_T_983, _T_984) @[el2_lib.scala 244:78] + node _T_986 = mux(_T_982, UInt<1>("h01"), _T_985) @[el2_lib.scala 244:23] + _T_846[19] <= _T_986 @[el2_lib.scala 244:17] + node _T_987 = bits(io.trigger_pkt_any[3].tdata2, 19, 0) @[el2_lib.scala 244:28] + node _T_988 = andr(_T_987) @[el2_lib.scala 244:36] + node _T_989 = and(_T_988, _T_849) @[el2_lib.scala 244:41] + node _T_990 = bits(io.trigger_pkt_any[3].tdata2, 20, 20) @[el2_lib.scala 244:74] + node _T_991 = bits(lsu_match_data_3, 20, 20) @[el2_lib.scala 244:86] + node _T_992 = eq(_T_990, _T_991) @[el2_lib.scala 244:78] + node _T_993 = mux(_T_989, UInt<1>("h01"), _T_992) @[el2_lib.scala 244:23] + _T_846[20] <= _T_993 @[el2_lib.scala 244:17] + node _T_994 = bits(io.trigger_pkt_any[3].tdata2, 20, 0) @[el2_lib.scala 244:28] + node _T_995 = andr(_T_994) @[el2_lib.scala 244:36] + node _T_996 = and(_T_995, _T_849) @[el2_lib.scala 244:41] + node _T_997 = bits(io.trigger_pkt_any[3].tdata2, 21, 21) @[el2_lib.scala 244:74] + node _T_998 = bits(lsu_match_data_3, 21, 21) @[el2_lib.scala 244:86] + node _T_999 = eq(_T_997, _T_998) @[el2_lib.scala 244:78] + node _T_1000 = mux(_T_996, UInt<1>("h01"), _T_999) @[el2_lib.scala 244:23] + _T_846[21] <= _T_1000 @[el2_lib.scala 244:17] + node _T_1001 = bits(io.trigger_pkt_any[3].tdata2, 21, 0) @[el2_lib.scala 244:28] + node _T_1002 = andr(_T_1001) @[el2_lib.scala 244:36] + node _T_1003 = and(_T_1002, _T_849) @[el2_lib.scala 244:41] + node _T_1004 = bits(io.trigger_pkt_any[3].tdata2, 22, 22) @[el2_lib.scala 244:74] + node _T_1005 = bits(lsu_match_data_3, 22, 22) @[el2_lib.scala 244:86] + node _T_1006 = eq(_T_1004, _T_1005) @[el2_lib.scala 244:78] + node _T_1007 = mux(_T_1003, UInt<1>("h01"), _T_1006) @[el2_lib.scala 244:23] + _T_846[22] <= _T_1007 @[el2_lib.scala 244:17] + node _T_1008 = bits(io.trigger_pkt_any[3].tdata2, 22, 0) @[el2_lib.scala 244:28] + node _T_1009 = andr(_T_1008) @[el2_lib.scala 244:36] + node _T_1010 = and(_T_1009, _T_849) @[el2_lib.scala 244:41] + node _T_1011 = bits(io.trigger_pkt_any[3].tdata2, 23, 23) @[el2_lib.scala 244:74] + node _T_1012 = bits(lsu_match_data_3, 23, 23) @[el2_lib.scala 244:86] + node _T_1013 = eq(_T_1011, _T_1012) @[el2_lib.scala 244:78] + node _T_1014 = mux(_T_1010, UInt<1>("h01"), _T_1013) @[el2_lib.scala 244:23] + _T_846[23] <= _T_1014 @[el2_lib.scala 244:17] + node _T_1015 = bits(io.trigger_pkt_any[3].tdata2, 23, 0) @[el2_lib.scala 244:28] + node _T_1016 = andr(_T_1015) @[el2_lib.scala 244:36] + node _T_1017 = and(_T_1016, _T_849) @[el2_lib.scala 244:41] + node _T_1018 = bits(io.trigger_pkt_any[3].tdata2, 24, 24) @[el2_lib.scala 244:74] + node _T_1019 = bits(lsu_match_data_3, 24, 24) @[el2_lib.scala 244:86] + node _T_1020 = eq(_T_1018, _T_1019) @[el2_lib.scala 244:78] + node _T_1021 = mux(_T_1017, UInt<1>("h01"), _T_1020) @[el2_lib.scala 244:23] + _T_846[24] <= _T_1021 @[el2_lib.scala 244:17] + node _T_1022 = bits(io.trigger_pkt_any[3].tdata2, 24, 0) @[el2_lib.scala 244:28] + node _T_1023 = andr(_T_1022) @[el2_lib.scala 244:36] + node _T_1024 = and(_T_1023, _T_849) @[el2_lib.scala 244:41] + node _T_1025 = bits(io.trigger_pkt_any[3].tdata2, 25, 25) @[el2_lib.scala 244:74] + node _T_1026 = bits(lsu_match_data_3, 25, 25) @[el2_lib.scala 244:86] + node _T_1027 = eq(_T_1025, _T_1026) @[el2_lib.scala 244:78] + node _T_1028 = mux(_T_1024, UInt<1>("h01"), _T_1027) @[el2_lib.scala 244:23] + _T_846[25] <= _T_1028 @[el2_lib.scala 244:17] + node _T_1029 = bits(io.trigger_pkt_any[3].tdata2, 25, 0) @[el2_lib.scala 244:28] + node _T_1030 = andr(_T_1029) @[el2_lib.scala 244:36] + node _T_1031 = and(_T_1030, _T_849) @[el2_lib.scala 244:41] + node _T_1032 = bits(io.trigger_pkt_any[3].tdata2, 26, 26) @[el2_lib.scala 244:74] + node _T_1033 = bits(lsu_match_data_3, 26, 26) @[el2_lib.scala 244:86] + node _T_1034 = eq(_T_1032, _T_1033) @[el2_lib.scala 244:78] + node _T_1035 = mux(_T_1031, UInt<1>("h01"), _T_1034) @[el2_lib.scala 244:23] + _T_846[26] <= _T_1035 @[el2_lib.scala 244:17] + node _T_1036 = bits(io.trigger_pkt_any[3].tdata2, 26, 0) @[el2_lib.scala 244:28] + node _T_1037 = andr(_T_1036) @[el2_lib.scala 244:36] + node _T_1038 = and(_T_1037, _T_849) @[el2_lib.scala 244:41] + node _T_1039 = bits(io.trigger_pkt_any[3].tdata2, 27, 27) @[el2_lib.scala 244:74] + node _T_1040 = bits(lsu_match_data_3, 27, 27) @[el2_lib.scala 244:86] + node _T_1041 = eq(_T_1039, _T_1040) @[el2_lib.scala 244:78] + node _T_1042 = mux(_T_1038, UInt<1>("h01"), _T_1041) @[el2_lib.scala 244:23] + _T_846[27] <= _T_1042 @[el2_lib.scala 244:17] + node _T_1043 = bits(io.trigger_pkt_any[3].tdata2, 27, 0) @[el2_lib.scala 244:28] + node _T_1044 = andr(_T_1043) @[el2_lib.scala 244:36] + node _T_1045 = and(_T_1044, _T_849) @[el2_lib.scala 244:41] + node _T_1046 = bits(io.trigger_pkt_any[3].tdata2, 28, 28) @[el2_lib.scala 244:74] + node _T_1047 = bits(lsu_match_data_3, 28, 28) @[el2_lib.scala 244:86] + node _T_1048 = eq(_T_1046, _T_1047) @[el2_lib.scala 244:78] + node _T_1049 = mux(_T_1045, UInt<1>("h01"), _T_1048) @[el2_lib.scala 244:23] + _T_846[28] <= _T_1049 @[el2_lib.scala 244:17] + node _T_1050 = bits(io.trigger_pkt_any[3].tdata2, 28, 0) @[el2_lib.scala 244:28] + node _T_1051 = andr(_T_1050) @[el2_lib.scala 244:36] + node _T_1052 = and(_T_1051, _T_849) @[el2_lib.scala 244:41] + node _T_1053 = bits(io.trigger_pkt_any[3].tdata2, 29, 29) @[el2_lib.scala 244:74] + node _T_1054 = bits(lsu_match_data_3, 29, 29) @[el2_lib.scala 244:86] + node _T_1055 = eq(_T_1053, _T_1054) @[el2_lib.scala 244:78] + node _T_1056 = mux(_T_1052, UInt<1>("h01"), _T_1055) @[el2_lib.scala 244:23] + _T_846[29] <= _T_1056 @[el2_lib.scala 244:17] + node _T_1057 = bits(io.trigger_pkt_any[3].tdata2, 29, 0) @[el2_lib.scala 244:28] + node _T_1058 = andr(_T_1057) @[el2_lib.scala 244:36] + node _T_1059 = and(_T_1058, _T_849) @[el2_lib.scala 244:41] + node _T_1060 = bits(io.trigger_pkt_any[3].tdata2, 30, 30) @[el2_lib.scala 244:74] + node _T_1061 = bits(lsu_match_data_3, 30, 30) @[el2_lib.scala 244:86] + node _T_1062 = eq(_T_1060, _T_1061) @[el2_lib.scala 244:78] + node _T_1063 = mux(_T_1059, UInt<1>("h01"), _T_1062) @[el2_lib.scala 244:23] + _T_846[30] <= _T_1063 @[el2_lib.scala 244:17] + node _T_1064 = bits(io.trigger_pkt_any[3].tdata2, 30, 0) @[el2_lib.scala 244:28] + node _T_1065 = andr(_T_1064) @[el2_lib.scala 244:36] + node _T_1066 = and(_T_1065, _T_849) @[el2_lib.scala 244:41] + node _T_1067 = bits(io.trigger_pkt_any[3].tdata2, 31, 31) @[el2_lib.scala 244:74] + node _T_1068 = bits(lsu_match_data_3, 31, 31) @[el2_lib.scala 244:86] + node _T_1069 = eq(_T_1067, _T_1068) @[el2_lib.scala 244:78] + node _T_1070 = mux(_T_1066, UInt<1>("h01"), _T_1069) @[el2_lib.scala 244:23] + _T_846[31] <= _T_1070 @[el2_lib.scala 244:17] + node _T_1071 = cat(_T_846[1], _T_846[0]) @[el2_lib.scala 245:14] + node _T_1072 = cat(_T_846[3], _T_846[2]) @[el2_lib.scala 245:14] + node _T_1073 = cat(_T_1072, _T_1071) @[el2_lib.scala 245:14] + node _T_1074 = cat(_T_846[5], _T_846[4]) @[el2_lib.scala 245:14] + node _T_1075 = cat(_T_846[7], _T_846[6]) @[el2_lib.scala 245:14] + node _T_1076 = cat(_T_1075, _T_1074) @[el2_lib.scala 245:14] + node _T_1077 = cat(_T_1076, _T_1073) @[el2_lib.scala 245:14] + node _T_1078 = cat(_T_846[9], _T_846[8]) @[el2_lib.scala 245:14] + node _T_1079 = cat(_T_846[11], _T_846[10]) @[el2_lib.scala 245:14] + node _T_1080 = cat(_T_1079, _T_1078) @[el2_lib.scala 245:14] + node _T_1081 = cat(_T_846[13], _T_846[12]) @[el2_lib.scala 245:14] + node _T_1082 = cat(_T_846[15], _T_846[14]) @[el2_lib.scala 245:14] + node _T_1083 = cat(_T_1082, _T_1081) @[el2_lib.scala 245:14] + node _T_1084 = cat(_T_1083, _T_1080) @[el2_lib.scala 245:14] + node _T_1085 = cat(_T_1084, _T_1077) @[el2_lib.scala 245:14] + node _T_1086 = cat(_T_846[17], _T_846[16]) @[el2_lib.scala 245:14] + node _T_1087 = cat(_T_846[19], _T_846[18]) @[el2_lib.scala 245:14] + node _T_1088 = cat(_T_1087, _T_1086) @[el2_lib.scala 245:14] + node _T_1089 = cat(_T_846[21], _T_846[20]) @[el2_lib.scala 245:14] + node _T_1090 = cat(_T_846[23], _T_846[22]) @[el2_lib.scala 245:14] + node _T_1091 = cat(_T_1090, _T_1089) @[el2_lib.scala 245:14] + node _T_1092 = cat(_T_1091, _T_1088) @[el2_lib.scala 245:14] + node _T_1093 = cat(_T_846[25], _T_846[24]) @[el2_lib.scala 245:14] + node _T_1094 = cat(_T_846[27], _T_846[26]) @[el2_lib.scala 245:14] + node _T_1095 = cat(_T_1094, _T_1093) @[el2_lib.scala 245:14] + node _T_1096 = cat(_T_846[29], _T_846[28]) @[el2_lib.scala 245:14] + node _T_1097 = cat(_T_846[31], _T_846[30]) @[el2_lib.scala 245:14] + node _T_1098 = cat(_T_1097, _T_1096) @[el2_lib.scala 245:14] + node _T_1099 = cat(_T_1098, _T_1095) @[el2_lib.scala 245:14] + node _T_1100 = cat(_T_1099, _T_1092) @[el2_lib.scala 245:14] + node _T_1101 = cat(_T_1100, _T_1085) @[el2_lib.scala 245:14] + node _T_1102 = and(_T_844, _T_1101) @[el2_lsu_trigger.scala 19:92] + node _T_1103 = cat(_T_1102, _T_836) @[Cat.scala 29:58] + node _T_1104 = cat(_T_1103, _T_570) @[Cat.scala 29:58] + node _T_1105 = cat(_T_1104, _T_304) @[Cat.scala 29:58] + io.lsu_trigger_match_m <= _T_1105 @[el2_lsu_trigger.scala 18:26] diff --git a/el2_lsu_trigger.v b/el2_lsu_trigger.v index 75b943ef..2b5989ed 100644 --- a/el2_lsu_trigger.v +++ b/el2_lsu_trigger.v @@ -2,55 +2,55 @@ module el2_lsu_trigger( input clock, input reset, input io_trigger_pkt_any_0_select, - input io_trigger_pkt_any_0_match_, + input io_trigger_pkt_any_0_match_pkt, input io_trigger_pkt_any_0_store, input io_trigger_pkt_any_0_load, input io_trigger_pkt_any_0_execute, input io_trigger_pkt_any_0_m, input [31:0] io_trigger_pkt_any_0_tdata2, input io_trigger_pkt_any_1_select, - input io_trigger_pkt_any_1_match_, + input io_trigger_pkt_any_1_match_pkt, input io_trigger_pkt_any_1_store, input io_trigger_pkt_any_1_load, input io_trigger_pkt_any_1_execute, input io_trigger_pkt_any_1_m, input [31:0] io_trigger_pkt_any_1_tdata2, input io_trigger_pkt_any_2_select, - input io_trigger_pkt_any_2_match_, + input io_trigger_pkt_any_2_match_pkt, input io_trigger_pkt_any_2_store, input io_trigger_pkt_any_2_load, input io_trigger_pkt_any_2_execute, input io_trigger_pkt_any_2_m, input [31:0] io_trigger_pkt_any_2_tdata2, input io_trigger_pkt_any_3_select, - input io_trigger_pkt_any_3_match_, + input io_trigger_pkt_any_3_match_pkt, input io_trigger_pkt_any_3_store, input io_trigger_pkt_any_3_load, input io_trigger_pkt_any_3_execute, input io_trigger_pkt_any_3_m, input [31:0] io_trigger_pkt_any_3_tdata2, - input io_lsu_pkt_m_fast_int, - input io_lsu_pkt_m_by, - input io_lsu_pkt_m_half, - input io_lsu_pkt_m_word, - input io_lsu_pkt_m_dword, - input io_lsu_pkt_m_load, - input io_lsu_pkt_m_store, - input io_lsu_pkt_m_unsign, - input io_lsu_pkt_m_dma, - input io_lsu_pkt_m_store_data_bypass_d, - input io_lsu_pkt_m_load_ldst_bypass_d, - input io_lsu_pkt_m_store_data_bypass_m, input io_lsu_pkt_m_valid, + input io_lsu_pkt_m_bits_fast_int, + input io_lsu_pkt_m_bits_by, + input io_lsu_pkt_m_bits_half, + input io_lsu_pkt_m_bits_word, + input io_lsu_pkt_m_bits_dword, + input io_lsu_pkt_m_bits_load, + input io_lsu_pkt_m_bits_store, + input io_lsu_pkt_m_bits_unsign, + input io_lsu_pkt_m_bits_dma, + input io_lsu_pkt_m_bits_store_data_bypass_d, + input io_lsu_pkt_m_bits_load_ldst_bypass_d, + input io_lsu_pkt_m_bits_store_data_bypass_m, input [31:0] io_lsu_addr_m, input [31:0] io_store_data_m, output [3:0] io_lsu_trigger_match_m ); - wire [15:0] _T_1 = io_lsu_pkt_m_word ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12] - wire [15:0] _T_3 = _T_1 & io_store_data_m[31:16]; // @[el2_lsu_trigger.scala 16:61] - wire _T_4 = io_lsu_pkt_m_half | io_lsu_pkt_m_word; // @[el2_lsu_trigger.scala 16:114] + wire [15:0] _T_1 = io_lsu_pkt_m_bits_word ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12] + wire [15:0] _T_3 = _T_1 & io_store_data_m[31:16]; // @[el2_lsu_trigger.scala 16:66] + wire _T_4 = io_lsu_pkt_m_bits_half | io_lsu_pkt_m_bits_word; // @[el2_lsu_trigger.scala 16:124] wire [7:0] _T_6 = _T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_8 = _T_6 & io_store_data_m[15:8]; // @[el2_lsu_trigger.scala 16:136] + wire [7:0] _T_8 = _T_6 & io_store_data_m[15:8]; // @[el2_lsu_trigger.scala 16:151] wire [31:0] store_data_trigger_m = {_T_3,_T_8,io_store_data_m[7:0]}; // @[Cat.scala 29:58] wire _T_12 = ~io_trigger_pkt_any_0_select; // @[el2_lsu_trigger.scala 17:53] wire _T_13 = io_trigger_pkt_any_0_select & io_trigger_pkt_any_0_store; // @[el2_lsu_trigger.scala 17:136] @@ -72,568 +72,568 @@ module el2_lsu_trigger( wire [31:0] _T_36 = _T_33 ? io_lsu_addr_m : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_37 = _T_34 ? store_data_trigger_m : 32'h0; // @[Mux.scala 27:72] wire [31:0] lsu_match_data_3 = _T_36 | _T_37; // @[Mux.scala 27:72] - wire _T_39 = ~io_lsu_pkt_m_dma; // @[el2_lsu_trigger.scala 18:71] + wire _T_39 = ~io_lsu_pkt_m_bits_dma; // @[el2_lsu_trigger.scala 18:71] wire _T_40 = io_lsu_pkt_m_valid & _T_39; // @[el2_lsu_trigger.scala 18:69] - wire _T_41 = io_trigger_pkt_any_0_store & io_lsu_pkt_m_store; // @[el2_lsu_trigger.scala 18:121] - wire _T_42 = io_trigger_pkt_any_0_load & io_lsu_pkt_m_load; // @[el2_lsu_trigger.scala 19:33] - wire _T_44 = _T_42 & _T_12; // @[el2_lsu_trigger.scala 19:53] - wire _T_45 = _T_41 | _T_44; // @[el2_lsu_trigger.scala 18:142] - wire _T_46 = _T_40 & _T_45; // @[el2_lsu_trigger.scala 18:89] - wire _T_51 = &io_trigger_pkt_any_0_tdata2; // @[el2_lib.scala 240:73] - wire _T_52 = ~_T_51; // @[el2_lib.scala 240:47] - wire _T_53 = io_trigger_pkt_any_0_match_ & _T_52; // @[el2_lib.scala 240:44] - wire _T_56 = io_trigger_pkt_any_0_tdata2[0] == lsu_match_data_0[0]; // @[el2_lib.scala 241:52] - wire _T_57 = _T_53 | _T_56; // @[el2_lib.scala 241:41] - wire _T_59 = &io_trigger_pkt_any_0_tdata2[0]; // @[el2_lib.scala 243:37] - wire _T_60 = _T_59 & _T_53; // @[el2_lib.scala 243:42] - wire _T_63 = io_trigger_pkt_any_0_tdata2[1] == lsu_match_data_0[1]; // @[el2_lib.scala 243:79] - wire _T_64 = _T_60 | _T_63; // @[el2_lib.scala 243:24] - wire _T_66 = &io_trigger_pkt_any_0_tdata2[1:0]; // @[el2_lib.scala 243:37] - wire _T_67 = _T_66 & _T_53; // @[el2_lib.scala 243:42] - wire _T_70 = io_trigger_pkt_any_0_tdata2[2] == lsu_match_data_0[2]; // @[el2_lib.scala 243:79] - wire _T_71 = _T_67 | _T_70; // @[el2_lib.scala 243:24] - wire _T_73 = &io_trigger_pkt_any_0_tdata2[2:0]; // @[el2_lib.scala 243:37] - wire _T_74 = _T_73 & _T_53; // @[el2_lib.scala 243:42] - wire _T_77 = io_trigger_pkt_any_0_tdata2[3] == lsu_match_data_0[3]; // @[el2_lib.scala 243:79] - wire _T_78 = _T_74 | _T_77; // @[el2_lib.scala 243:24] - wire _T_80 = &io_trigger_pkt_any_0_tdata2[3:0]; // @[el2_lib.scala 243:37] - wire _T_81 = _T_80 & _T_53; // @[el2_lib.scala 243:42] - wire _T_84 = io_trigger_pkt_any_0_tdata2[4] == lsu_match_data_0[4]; // @[el2_lib.scala 243:79] - wire _T_85 = _T_81 | _T_84; // @[el2_lib.scala 243:24] - wire _T_87 = &io_trigger_pkt_any_0_tdata2[4:0]; // @[el2_lib.scala 243:37] - wire _T_88 = _T_87 & _T_53; // @[el2_lib.scala 243:42] - wire _T_91 = io_trigger_pkt_any_0_tdata2[5] == lsu_match_data_0[5]; // @[el2_lib.scala 243:79] - wire _T_92 = _T_88 | _T_91; // @[el2_lib.scala 243:24] - wire _T_94 = &io_trigger_pkt_any_0_tdata2[5:0]; // @[el2_lib.scala 243:37] - wire _T_95 = _T_94 & _T_53; // @[el2_lib.scala 243:42] - wire _T_98 = io_trigger_pkt_any_0_tdata2[6] == lsu_match_data_0[6]; // @[el2_lib.scala 243:79] - wire _T_99 = _T_95 | _T_98; // @[el2_lib.scala 243:24] - wire _T_101 = &io_trigger_pkt_any_0_tdata2[6:0]; // @[el2_lib.scala 243:37] - wire _T_102 = _T_101 & _T_53; // @[el2_lib.scala 243:42] - wire _T_105 = io_trigger_pkt_any_0_tdata2[7] == lsu_match_data_0[7]; // @[el2_lib.scala 243:79] - wire _T_106 = _T_102 | _T_105; // @[el2_lib.scala 243:24] - wire _T_108 = &io_trigger_pkt_any_0_tdata2[7:0]; // @[el2_lib.scala 243:37] - wire _T_109 = _T_108 & _T_53; // @[el2_lib.scala 243:42] - wire _T_112 = io_trigger_pkt_any_0_tdata2[8] == lsu_match_data_0[8]; // @[el2_lib.scala 243:79] - wire _T_113 = _T_109 | _T_112; // @[el2_lib.scala 243:24] - wire _T_115 = &io_trigger_pkt_any_0_tdata2[8:0]; // @[el2_lib.scala 243:37] - wire _T_116 = _T_115 & _T_53; // @[el2_lib.scala 243:42] - wire _T_119 = io_trigger_pkt_any_0_tdata2[9] == lsu_match_data_0[9]; // @[el2_lib.scala 243:79] - wire _T_120 = _T_116 | _T_119; // @[el2_lib.scala 243:24] - wire _T_122 = &io_trigger_pkt_any_0_tdata2[9:0]; // @[el2_lib.scala 243:37] - wire _T_123 = _T_122 & _T_53; // @[el2_lib.scala 243:42] - wire _T_126 = io_trigger_pkt_any_0_tdata2[10] == lsu_match_data_0[10]; // @[el2_lib.scala 243:79] - wire _T_127 = _T_123 | _T_126; // @[el2_lib.scala 243:24] - wire _T_129 = &io_trigger_pkt_any_0_tdata2[10:0]; // @[el2_lib.scala 243:37] - wire _T_130 = _T_129 & _T_53; // @[el2_lib.scala 243:42] - wire _T_133 = io_trigger_pkt_any_0_tdata2[11] == lsu_match_data_0[11]; // @[el2_lib.scala 243:79] - wire _T_134 = _T_130 | _T_133; // @[el2_lib.scala 243:24] - wire _T_136 = &io_trigger_pkt_any_0_tdata2[11:0]; // @[el2_lib.scala 243:37] - wire _T_137 = _T_136 & _T_53; // @[el2_lib.scala 243:42] - wire _T_140 = io_trigger_pkt_any_0_tdata2[12] == lsu_match_data_0[12]; // @[el2_lib.scala 243:79] - wire _T_141 = _T_137 | _T_140; // @[el2_lib.scala 243:24] - wire _T_143 = &io_trigger_pkt_any_0_tdata2[12:0]; // @[el2_lib.scala 243:37] - wire _T_144 = _T_143 & _T_53; // @[el2_lib.scala 243:42] - wire _T_147 = io_trigger_pkt_any_0_tdata2[13] == lsu_match_data_0[13]; // @[el2_lib.scala 243:79] - wire _T_148 = _T_144 | _T_147; // @[el2_lib.scala 243:24] - wire _T_150 = &io_trigger_pkt_any_0_tdata2[13:0]; // @[el2_lib.scala 243:37] - wire _T_151 = _T_150 & _T_53; // @[el2_lib.scala 243:42] - wire _T_154 = io_trigger_pkt_any_0_tdata2[14] == lsu_match_data_0[14]; // @[el2_lib.scala 243:79] - wire _T_155 = _T_151 | _T_154; // @[el2_lib.scala 243:24] - wire _T_157 = &io_trigger_pkt_any_0_tdata2[14:0]; // @[el2_lib.scala 243:37] - wire _T_158 = _T_157 & _T_53; // @[el2_lib.scala 243:42] - wire _T_161 = io_trigger_pkt_any_0_tdata2[15] == lsu_match_data_0[15]; // @[el2_lib.scala 243:79] - wire _T_162 = _T_158 | _T_161; // @[el2_lib.scala 243:24] - wire _T_164 = &io_trigger_pkt_any_0_tdata2[15:0]; // @[el2_lib.scala 243:37] - wire _T_165 = _T_164 & _T_53; // @[el2_lib.scala 243:42] - wire _T_168 = io_trigger_pkt_any_0_tdata2[16] == lsu_match_data_0[16]; // @[el2_lib.scala 243:79] - wire _T_169 = _T_165 | _T_168; // @[el2_lib.scala 243:24] - wire _T_171 = &io_trigger_pkt_any_0_tdata2[16:0]; // @[el2_lib.scala 243:37] - wire _T_172 = _T_171 & _T_53; // @[el2_lib.scala 243:42] - wire _T_175 = io_trigger_pkt_any_0_tdata2[17] == lsu_match_data_0[17]; // @[el2_lib.scala 243:79] - wire _T_176 = _T_172 | _T_175; // @[el2_lib.scala 243:24] - wire _T_178 = &io_trigger_pkt_any_0_tdata2[17:0]; // @[el2_lib.scala 243:37] - wire _T_179 = _T_178 & _T_53; // @[el2_lib.scala 243:42] - wire _T_182 = io_trigger_pkt_any_0_tdata2[18] == lsu_match_data_0[18]; // @[el2_lib.scala 243:79] - wire _T_183 = _T_179 | _T_182; // @[el2_lib.scala 243:24] - wire _T_185 = &io_trigger_pkt_any_0_tdata2[18:0]; // @[el2_lib.scala 243:37] - wire _T_186 = _T_185 & _T_53; // @[el2_lib.scala 243:42] - wire _T_189 = io_trigger_pkt_any_0_tdata2[19] == lsu_match_data_0[19]; // @[el2_lib.scala 243:79] - wire _T_190 = _T_186 | _T_189; // @[el2_lib.scala 243:24] - wire _T_192 = &io_trigger_pkt_any_0_tdata2[19:0]; // @[el2_lib.scala 243:37] - wire _T_193 = _T_192 & _T_53; // @[el2_lib.scala 243:42] - wire _T_196 = io_trigger_pkt_any_0_tdata2[20] == lsu_match_data_0[20]; // @[el2_lib.scala 243:79] - wire _T_197 = _T_193 | _T_196; // @[el2_lib.scala 243:24] - wire _T_199 = &io_trigger_pkt_any_0_tdata2[20:0]; // @[el2_lib.scala 243:37] - wire _T_200 = _T_199 & _T_53; // @[el2_lib.scala 243:42] - wire _T_203 = io_trigger_pkt_any_0_tdata2[21] == lsu_match_data_0[21]; // @[el2_lib.scala 243:79] - wire _T_204 = _T_200 | _T_203; // @[el2_lib.scala 243:24] - wire _T_206 = &io_trigger_pkt_any_0_tdata2[21:0]; // @[el2_lib.scala 243:37] - wire _T_207 = _T_206 & _T_53; // @[el2_lib.scala 243:42] - wire _T_210 = io_trigger_pkt_any_0_tdata2[22] == lsu_match_data_0[22]; // @[el2_lib.scala 243:79] - wire _T_211 = _T_207 | _T_210; // @[el2_lib.scala 243:24] - wire _T_213 = &io_trigger_pkt_any_0_tdata2[22:0]; // @[el2_lib.scala 243:37] - wire _T_214 = _T_213 & _T_53; // @[el2_lib.scala 243:42] - wire _T_217 = io_trigger_pkt_any_0_tdata2[23] == lsu_match_data_0[23]; // @[el2_lib.scala 243:79] - wire _T_218 = _T_214 | _T_217; // @[el2_lib.scala 243:24] - wire _T_220 = &io_trigger_pkt_any_0_tdata2[23:0]; // @[el2_lib.scala 243:37] - wire _T_221 = _T_220 & _T_53; // @[el2_lib.scala 243:42] - wire _T_224 = io_trigger_pkt_any_0_tdata2[24] == lsu_match_data_0[24]; // @[el2_lib.scala 243:79] - wire _T_225 = _T_221 | _T_224; // @[el2_lib.scala 243:24] - wire _T_227 = &io_trigger_pkt_any_0_tdata2[24:0]; // @[el2_lib.scala 243:37] - wire _T_228 = _T_227 & _T_53; // @[el2_lib.scala 243:42] - wire _T_231 = io_trigger_pkt_any_0_tdata2[25] == lsu_match_data_0[25]; // @[el2_lib.scala 243:79] - wire _T_232 = _T_228 | _T_231; // @[el2_lib.scala 243:24] - wire _T_234 = &io_trigger_pkt_any_0_tdata2[25:0]; // @[el2_lib.scala 243:37] - wire _T_235 = _T_234 & _T_53; // @[el2_lib.scala 243:42] - wire _T_238 = io_trigger_pkt_any_0_tdata2[26] == lsu_match_data_0[26]; // @[el2_lib.scala 243:79] - wire _T_239 = _T_235 | _T_238; // @[el2_lib.scala 243:24] - wire _T_241 = &io_trigger_pkt_any_0_tdata2[26:0]; // @[el2_lib.scala 243:37] - wire _T_242 = _T_241 & _T_53; // @[el2_lib.scala 243:42] - wire _T_245 = io_trigger_pkt_any_0_tdata2[27] == lsu_match_data_0[27]; // @[el2_lib.scala 243:79] - wire _T_246 = _T_242 | _T_245; // @[el2_lib.scala 243:24] - wire _T_248 = &io_trigger_pkt_any_0_tdata2[27:0]; // @[el2_lib.scala 243:37] - wire _T_249 = _T_248 & _T_53; // @[el2_lib.scala 243:42] - wire _T_252 = io_trigger_pkt_any_0_tdata2[28] == lsu_match_data_0[28]; // @[el2_lib.scala 243:79] - wire _T_253 = _T_249 | _T_252; // @[el2_lib.scala 243:24] - wire _T_255 = &io_trigger_pkt_any_0_tdata2[28:0]; // @[el2_lib.scala 243:37] - wire _T_256 = _T_255 & _T_53; // @[el2_lib.scala 243:42] - wire _T_259 = io_trigger_pkt_any_0_tdata2[29] == lsu_match_data_0[29]; // @[el2_lib.scala 243:79] - wire _T_260 = _T_256 | _T_259; // @[el2_lib.scala 243:24] - wire _T_262 = &io_trigger_pkt_any_0_tdata2[29:0]; // @[el2_lib.scala 243:37] - wire _T_263 = _T_262 & _T_53; // @[el2_lib.scala 243:42] - wire _T_266 = io_trigger_pkt_any_0_tdata2[30] == lsu_match_data_0[30]; // @[el2_lib.scala 243:79] - wire _T_267 = _T_263 | _T_266; // @[el2_lib.scala 243:24] - wire _T_269 = &io_trigger_pkt_any_0_tdata2[30:0]; // @[el2_lib.scala 243:37] - wire _T_270 = _T_269 & _T_53; // @[el2_lib.scala 243:42] - wire _T_273 = io_trigger_pkt_any_0_tdata2[31] == lsu_match_data_0[31]; // @[el2_lib.scala 243:79] - wire _T_274 = _T_270 | _T_273; // @[el2_lib.scala 243:24] - wire [7:0] _T_281 = {_T_106,_T_99,_T_92,_T_85,_T_78,_T_71,_T_64,_T_57}; // @[el2_lib.scala 244:14] - wire [15:0] _T_289 = {_T_162,_T_155,_T_148,_T_141,_T_134,_T_127,_T_120,_T_113,_T_281}; // @[el2_lib.scala 244:14] - wire [7:0] _T_296 = {_T_218,_T_211,_T_204,_T_197,_T_190,_T_183,_T_176,_T_169}; // @[el2_lib.scala 244:14] - wire [31:0] _T_305 = {_T_274,_T_267,_T_260,_T_253,_T_246,_T_239,_T_232,_T_225,_T_296,_T_289}; // @[el2_lib.scala 244:14] - wire _T_306 = &_T_305; // @[el2_lib.scala 244:21] - wire _T_307 = _T_46 & _T_306; // @[el2_lsu_trigger.scala 19:87] - wire _T_310 = io_trigger_pkt_any_1_store & io_lsu_pkt_m_store; // @[el2_lsu_trigger.scala 18:121] - wire _T_311 = io_trigger_pkt_any_1_load & io_lsu_pkt_m_load; // @[el2_lsu_trigger.scala 19:33] - wire _T_313 = _T_311 & _T_19; // @[el2_lsu_trigger.scala 19:53] - wire _T_314 = _T_310 | _T_313; // @[el2_lsu_trigger.scala 18:142] - wire _T_315 = _T_40 & _T_314; // @[el2_lsu_trigger.scala 18:89] - wire _T_320 = &io_trigger_pkt_any_1_tdata2; // @[el2_lib.scala 240:73] - wire _T_321 = ~_T_320; // @[el2_lib.scala 240:47] - wire _T_322 = io_trigger_pkt_any_1_match_ & _T_321; // @[el2_lib.scala 240:44] - wire _T_325 = io_trigger_pkt_any_1_tdata2[0] == lsu_match_data_1[0]; // @[el2_lib.scala 241:52] - wire _T_326 = _T_322 | _T_325; // @[el2_lib.scala 241:41] - wire _T_328 = &io_trigger_pkt_any_1_tdata2[0]; // @[el2_lib.scala 243:37] - wire _T_329 = _T_328 & _T_322; // @[el2_lib.scala 243:42] - wire _T_332 = io_trigger_pkt_any_1_tdata2[1] == lsu_match_data_1[1]; // @[el2_lib.scala 243:79] - wire _T_333 = _T_329 | _T_332; // @[el2_lib.scala 243:24] - wire _T_335 = &io_trigger_pkt_any_1_tdata2[1:0]; // @[el2_lib.scala 243:37] - wire _T_336 = _T_335 & _T_322; // @[el2_lib.scala 243:42] - wire _T_339 = io_trigger_pkt_any_1_tdata2[2] == lsu_match_data_1[2]; // @[el2_lib.scala 243:79] - wire _T_340 = _T_336 | _T_339; // @[el2_lib.scala 243:24] - wire _T_342 = &io_trigger_pkt_any_1_tdata2[2:0]; // @[el2_lib.scala 243:37] - wire _T_343 = _T_342 & _T_322; // @[el2_lib.scala 243:42] - wire _T_346 = io_trigger_pkt_any_1_tdata2[3] == lsu_match_data_1[3]; // @[el2_lib.scala 243:79] - wire _T_347 = _T_343 | _T_346; // @[el2_lib.scala 243:24] - wire _T_349 = &io_trigger_pkt_any_1_tdata2[3:0]; // @[el2_lib.scala 243:37] - wire _T_350 = _T_349 & _T_322; // @[el2_lib.scala 243:42] - wire _T_353 = io_trigger_pkt_any_1_tdata2[4] == lsu_match_data_1[4]; // @[el2_lib.scala 243:79] - wire _T_354 = _T_350 | _T_353; // @[el2_lib.scala 243:24] - wire _T_356 = &io_trigger_pkt_any_1_tdata2[4:0]; // @[el2_lib.scala 243:37] - wire _T_357 = _T_356 & _T_322; // @[el2_lib.scala 243:42] - wire _T_360 = io_trigger_pkt_any_1_tdata2[5] == lsu_match_data_1[5]; // @[el2_lib.scala 243:79] - wire _T_361 = _T_357 | _T_360; // @[el2_lib.scala 243:24] - wire _T_363 = &io_trigger_pkt_any_1_tdata2[5:0]; // @[el2_lib.scala 243:37] - wire _T_364 = _T_363 & _T_322; // @[el2_lib.scala 243:42] - wire _T_367 = io_trigger_pkt_any_1_tdata2[6] == lsu_match_data_1[6]; // @[el2_lib.scala 243:79] - wire _T_368 = _T_364 | _T_367; // @[el2_lib.scala 243:24] - wire _T_370 = &io_trigger_pkt_any_1_tdata2[6:0]; // @[el2_lib.scala 243:37] - wire _T_371 = _T_370 & _T_322; // @[el2_lib.scala 243:42] - wire _T_374 = io_trigger_pkt_any_1_tdata2[7] == lsu_match_data_1[7]; // @[el2_lib.scala 243:79] - wire _T_375 = _T_371 | _T_374; // @[el2_lib.scala 243:24] - wire _T_377 = &io_trigger_pkt_any_1_tdata2[7:0]; // @[el2_lib.scala 243:37] - wire _T_378 = _T_377 & _T_322; // @[el2_lib.scala 243:42] - wire _T_381 = io_trigger_pkt_any_1_tdata2[8] == lsu_match_data_1[8]; // @[el2_lib.scala 243:79] - wire _T_382 = _T_378 | _T_381; // @[el2_lib.scala 243:24] - wire _T_384 = &io_trigger_pkt_any_1_tdata2[8:0]; // @[el2_lib.scala 243:37] - wire _T_385 = _T_384 & _T_322; // @[el2_lib.scala 243:42] - wire _T_388 = io_trigger_pkt_any_1_tdata2[9] == lsu_match_data_1[9]; // @[el2_lib.scala 243:79] - wire _T_389 = _T_385 | _T_388; // @[el2_lib.scala 243:24] - wire _T_391 = &io_trigger_pkt_any_1_tdata2[9:0]; // @[el2_lib.scala 243:37] - wire _T_392 = _T_391 & _T_322; // @[el2_lib.scala 243:42] - wire _T_395 = io_trigger_pkt_any_1_tdata2[10] == lsu_match_data_1[10]; // @[el2_lib.scala 243:79] - wire _T_396 = _T_392 | _T_395; // @[el2_lib.scala 243:24] - wire _T_398 = &io_trigger_pkt_any_1_tdata2[10:0]; // @[el2_lib.scala 243:37] - wire _T_399 = _T_398 & _T_322; // @[el2_lib.scala 243:42] - wire _T_402 = io_trigger_pkt_any_1_tdata2[11] == lsu_match_data_1[11]; // @[el2_lib.scala 243:79] - wire _T_403 = _T_399 | _T_402; // @[el2_lib.scala 243:24] - wire _T_405 = &io_trigger_pkt_any_1_tdata2[11:0]; // @[el2_lib.scala 243:37] - wire _T_406 = _T_405 & _T_322; // @[el2_lib.scala 243:42] - wire _T_409 = io_trigger_pkt_any_1_tdata2[12] == lsu_match_data_1[12]; // @[el2_lib.scala 243:79] - wire _T_410 = _T_406 | _T_409; // @[el2_lib.scala 243:24] - wire _T_412 = &io_trigger_pkt_any_1_tdata2[12:0]; // @[el2_lib.scala 243:37] - wire _T_413 = _T_412 & _T_322; // @[el2_lib.scala 243:42] - wire _T_416 = io_trigger_pkt_any_1_tdata2[13] == lsu_match_data_1[13]; // @[el2_lib.scala 243:79] - wire _T_417 = _T_413 | _T_416; // @[el2_lib.scala 243:24] - wire _T_419 = &io_trigger_pkt_any_1_tdata2[13:0]; // @[el2_lib.scala 243:37] - wire _T_420 = _T_419 & _T_322; // @[el2_lib.scala 243:42] - wire _T_423 = io_trigger_pkt_any_1_tdata2[14] == lsu_match_data_1[14]; // @[el2_lib.scala 243:79] - wire _T_424 = _T_420 | _T_423; // @[el2_lib.scala 243:24] - wire _T_426 = &io_trigger_pkt_any_1_tdata2[14:0]; // @[el2_lib.scala 243:37] - wire _T_427 = _T_426 & _T_322; // @[el2_lib.scala 243:42] - wire _T_430 = io_trigger_pkt_any_1_tdata2[15] == lsu_match_data_1[15]; // @[el2_lib.scala 243:79] - wire _T_431 = _T_427 | _T_430; // @[el2_lib.scala 243:24] - wire _T_433 = &io_trigger_pkt_any_1_tdata2[15:0]; // @[el2_lib.scala 243:37] - wire _T_434 = _T_433 & _T_322; // @[el2_lib.scala 243:42] - wire _T_437 = io_trigger_pkt_any_1_tdata2[16] == lsu_match_data_1[16]; // @[el2_lib.scala 243:79] - wire _T_438 = _T_434 | _T_437; // @[el2_lib.scala 243:24] - wire _T_440 = &io_trigger_pkt_any_1_tdata2[16:0]; // @[el2_lib.scala 243:37] - wire _T_441 = _T_440 & _T_322; // @[el2_lib.scala 243:42] - wire _T_444 = io_trigger_pkt_any_1_tdata2[17] == lsu_match_data_1[17]; // @[el2_lib.scala 243:79] - wire _T_445 = _T_441 | _T_444; // @[el2_lib.scala 243:24] - wire _T_447 = &io_trigger_pkt_any_1_tdata2[17:0]; // @[el2_lib.scala 243:37] - wire _T_448 = _T_447 & _T_322; // @[el2_lib.scala 243:42] - wire _T_451 = io_trigger_pkt_any_1_tdata2[18] == lsu_match_data_1[18]; // @[el2_lib.scala 243:79] - wire _T_452 = _T_448 | _T_451; // @[el2_lib.scala 243:24] - wire _T_454 = &io_trigger_pkt_any_1_tdata2[18:0]; // @[el2_lib.scala 243:37] - wire _T_455 = _T_454 & _T_322; // @[el2_lib.scala 243:42] - wire _T_458 = io_trigger_pkt_any_1_tdata2[19] == lsu_match_data_1[19]; // @[el2_lib.scala 243:79] - wire _T_459 = _T_455 | _T_458; // @[el2_lib.scala 243:24] - wire _T_461 = &io_trigger_pkt_any_1_tdata2[19:0]; // @[el2_lib.scala 243:37] - wire _T_462 = _T_461 & _T_322; // @[el2_lib.scala 243:42] - wire _T_465 = io_trigger_pkt_any_1_tdata2[20] == lsu_match_data_1[20]; // @[el2_lib.scala 243:79] - wire _T_466 = _T_462 | _T_465; // @[el2_lib.scala 243:24] - wire _T_468 = &io_trigger_pkt_any_1_tdata2[20:0]; // @[el2_lib.scala 243:37] - wire _T_469 = _T_468 & _T_322; // @[el2_lib.scala 243:42] - wire _T_472 = io_trigger_pkt_any_1_tdata2[21] == lsu_match_data_1[21]; // @[el2_lib.scala 243:79] - wire _T_473 = _T_469 | _T_472; // @[el2_lib.scala 243:24] - wire _T_475 = &io_trigger_pkt_any_1_tdata2[21:0]; // @[el2_lib.scala 243:37] - wire _T_476 = _T_475 & _T_322; // @[el2_lib.scala 243:42] - wire _T_479 = io_trigger_pkt_any_1_tdata2[22] == lsu_match_data_1[22]; // @[el2_lib.scala 243:79] - wire _T_480 = _T_476 | _T_479; // @[el2_lib.scala 243:24] - wire _T_482 = &io_trigger_pkt_any_1_tdata2[22:0]; // @[el2_lib.scala 243:37] - wire _T_483 = _T_482 & _T_322; // @[el2_lib.scala 243:42] - wire _T_486 = io_trigger_pkt_any_1_tdata2[23] == lsu_match_data_1[23]; // @[el2_lib.scala 243:79] - wire _T_487 = _T_483 | _T_486; // @[el2_lib.scala 243:24] - wire _T_489 = &io_trigger_pkt_any_1_tdata2[23:0]; // @[el2_lib.scala 243:37] - wire _T_490 = _T_489 & _T_322; // @[el2_lib.scala 243:42] - wire _T_493 = io_trigger_pkt_any_1_tdata2[24] == lsu_match_data_1[24]; // @[el2_lib.scala 243:79] - wire _T_494 = _T_490 | _T_493; // @[el2_lib.scala 243:24] - wire _T_496 = &io_trigger_pkt_any_1_tdata2[24:0]; // @[el2_lib.scala 243:37] - wire _T_497 = _T_496 & _T_322; // @[el2_lib.scala 243:42] - wire _T_500 = io_trigger_pkt_any_1_tdata2[25] == lsu_match_data_1[25]; // @[el2_lib.scala 243:79] - wire _T_501 = _T_497 | _T_500; // @[el2_lib.scala 243:24] - wire _T_503 = &io_trigger_pkt_any_1_tdata2[25:0]; // @[el2_lib.scala 243:37] - wire _T_504 = _T_503 & _T_322; // @[el2_lib.scala 243:42] - wire _T_507 = io_trigger_pkt_any_1_tdata2[26] == lsu_match_data_1[26]; // @[el2_lib.scala 243:79] - wire _T_508 = _T_504 | _T_507; // @[el2_lib.scala 243:24] - wire _T_510 = &io_trigger_pkt_any_1_tdata2[26:0]; // @[el2_lib.scala 243:37] - wire _T_511 = _T_510 & _T_322; // @[el2_lib.scala 243:42] - wire _T_514 = io_trigger_pkt_any_1_tdata2[27] == lsu_match_data_1[27]; // @[el2_lib.scala 243:79] - wire _T_515 = _T_511 | _T_514; // @[el2_lib.scala 243:24] - wire _T_517 = &io_trigger_pkt_any_1_tdata2[27:0]; // @[el2_lib.scala 243:37] - wire _T_518 = _T_517 & _T_322; // @[el2_lib.scala 243:42] - wire _T_521 = io_trigger_pkt_any_1_tdata2[28] == lsu_match_data_1[28]; // @[el2_lib.scala 243:79] - wire _T_522 = _T_518 | _T_521; // @[el2_lib.scala 243:24] - wire _T_524 = &io_trigger_pkt_any_1_tdata2[28:0]; // @[el2_lib.scala 243:37] - wire _T_525 = _T_524 & _T_322; // @[el2_lib.scala 243:42] - wire _T_528 = io_trigger_pkt_any_1_tdata2[29] == lsu_match_data_1[29]; // @[el2_lib.scala 243:79] - wire _T_529 = _T_525 | _T_528; // @[el2_lib.scala 243:24] - wire _T_531 = &io_trigger_pkt_any_1_tdata2[29:0]; // @[el2_lib.scala 243:37] - wire _T_532 = _T_531 & _T_322; // @[el2_lib.scala 243:42] - wire _T_535 = io_trigger_pkt_any_1_tdata2[30] == lsu_match_data_1[30]; // @[el2_lib.scala 243:79] - wire _T_536 = _T_532 | _T_535; // @[el2_lib.scala 243:24] - wire _T_538 = &io_trigger_pkt_any_1_tdata2[30:0]; // @[el2_lib.scala 243:37] - wire _T_539 = _T_538 & _T_322; // @[el2_lib.scala 243:42] - wire _T_542 = io_trigger_pkt_any_1_tdata2[31] == lsu_match_data_1[31]; // @[el2_lib.scala 243:79] - wire _T_543 = _T_539 | _T_542; // @[el2_lib.scala 243:24] - wire [7:0] _T_550 = {_T_375,_T_368,_T_361,_T_354,_T_347,_T_340,_T_333,_T_326}; // @[el2_lib.scala 244:14] - wire [15:0] _T_558 = {_T_431,_T_424,_T_417,_T_410,_T_403,_T_396,_T_389,_T_382,_T_550}; // @[el2_lib.scala 244:14] - wire [7:0] _T_565 = {_T_487,_T_480,_T_473,_T_466,_T_459,_T_452,_T_445,_T_438}; // @[el2_lib.scala 244:14] - wire [31:0] _T_574 = {_T_543,_T_536,_T_529,_T_522,_T_515,_T_508,_T_501,_T_494,_T_565,_T_558}; // @[el2_lib.scala 244:14] - wire _T_575 = &_T_574; // @[el2_lib.scala 244:21] - wire _T_576 = _T_315 & _T_575; // @[el2_lsu_trigger.scala 19:87] - wire _T_579 = io_trigger_pkt_any_2_store & io_lsu_pkt_m_store; // @[el2_lsu_trigger.scala 18:121] - wire _T_580 = io_trigger_pkt_any_2_load & io_lsu_pkt_m_load; // @[el2_lsu_trigger.scala 19:33] - wire _T_582 = _T_580 & _T_26; // @[el2_lsu_trigger.scala 19:53] - wire _T_583 = _T_579 | _T_582; // @[el2_lsu_trigger.scala 18:142] - wire _T_584 = _T_40 & _T_583; // @[el2_lsu_trigger.scala 18:89] - wire _T_589 = &io_trigger_pkt_any_2_tdata2; // @[el2_lib.scala 240:73] - wire _T_590 = ~_T_589; // @[el2_lib.scala 240:47] - wire _T_591 = io_trigger_pkt_any_2_match_ & _T_590; // @[el2_lib.scala 240:44] - wire _T_594 = io_trigger_pkt_any_2_tdata2[0] == lsu_match_data_2[0]; // @[el2_lib.scala 241:52] - wire _T_595 = _T_591 | _T_594; // @[el2_lib.scala 241:41] - wire _T_597 = &io_trigger_pkt_any_2_tdata2[0]; // @[el2_lib.scala 243:37] - wire _T_598 = _T_597 & _T_591; // @[el2_lib.scala 243:42] - wire _T_601 = io_trigger_pkt_any_2_tdata2[1] == lsu_match_data_2[1]; // @[el2_lib.scala 243:79] - wire _T_602 = _T_598 | _T_601; // @[el2_lib.scala 243:24] - wire _T_604 = &io_trigger_pkt_any_2_tdata2[1:0]; // @[el2_lib.scala 243:37] - wire _T_605 = _T_604 & _T_591; // @[el2_lib.scala 243:42] - wire _T_608 = io_trigger_pkt_any_2_tdata2[2] == lsu_match_data_2[2]; // @[el2_lib.scala 243:79] - wire _T_609 = _T_605 | _T_608; // @[el2_lib.scala 243:24] - wire _T_611 = &io_trigger_pkt_any_2_tdata2[2:0]; // @[el2_lib.scala 243:37] - wire _T_612 = _T_611 & _T_591; // @[el2_lib.scala 243:42] - wire _T_615 = io_trigger_pkt_any_2_tdata2[3] == lsu_match_data_2[3]; // @[el2_lib.scala 243:79] - wire _T_616 = _T_612 | _T_615; // @[el2_lib.scala 243:24] - wire _T_618 = &io_trigger_pkt_any_2_tdata2[3:0]; // @[el2_lib.scala 243:37] - wire _T_619 = _T_618 & _T_591; // @[el2_lib.scala 243:42] - wire _T_622 = io_trigger_pkt_any_2_tdata2[4] == lsu_match_data_2[4]; // @[el2_lib.scala 243:79] - wire _T_623 = _T_619 | _T_622; // @[el2_lib.scala 243:24] - wire _T_625 = &io_trigger_pkt_any_2_tdata2[4:0]; // @[el2_lib.scala 243:37] - wire _T_626 = _T_625 & _T_591; // @[el2_lib.scala 243:42] - wire _T_629 = io_trigger_pkt_any_2_tdata2[5] == lsu_match_data_2[5]; // @[el2_lib.scala 243:79] - wire _T_630 = _T_626 | _T_629; // @[el2_lib.scala 243:24] - wire _T_632 = &io_trigger_pkt_any_2_tdata2[5:0]; // @[el2_lib.scala 243:37] - wire _T_633 = _T_632 & _T_591; // @[el2_lib.scala 243:42] - wire _T_636 = io_trigger_pkt_any_2_tdata2[6] == lsu_match_data_2[6]; // @[el2_lib.scala 243:79] - wire _T_637 = _T_633 | _T_636; // @[el2_lib.scala 243:24] - wire _T_639 = &io_trigger_pkt_any_2_tdata2[6:0]; // @[el2_lib.scala 243:37] - wire _T_640 = _T_639 & _T_591; // @[el2_lib.scala 243:42] - wire _T_643 = io_trigger_pkt_any_2_tdata2[7] == lsu_match_data_2[7]; // @[el2_lib.scala 243:79] - wire _T_644 = _T_640 | _T_643; // @[el2_lib.scala 243:24] - wire _T_646 = &io_trigger_pkt_any_2_tdata2[7:0]; // @[el2_lib.scala 243:37] - wire _T_647 = _T_646 & _T_591; // @[el2_lib.scala 243:42] - wire _T_650 = io_trigger_pkt_any_2_tdata2[8] == lsu_match_data_2[8]; // @[el2_lib.scala 243:79] - wire _T_651 = _T_647 | _T_650; // @[el2_lib.scala 243:24] - wire _T_653 = &io_trigger_pkt_any_2_tdata2[8:0]; // @[el2_lib.scala 243:37] - wire _T_654 = _T_653 & _T_591; // @[el2_lib.scala 243:42] - wire _T_657 = io_trigger_pkt_any_2_tdata2[9] == lsu_match_data_2[9]; // @[el2_lib.scala 243:79] - wire _T_658 = _T_654 | _T_657; // @[el2_lib.scala 243:24] - wire _T_660 = &io_trigger_pkt_any_2_tdata2[9:0]; // @[el2_lib.scala 243:37] - wire _T_661 = _T_660 & _T_591; // @[el2_lib.scala 243:42] - wire _T_664 = io_trigger_pkt_any_2_tdata2[10] == lsu_match_data_2[10]; // @[el2_lib.scala 243:79] - wire _T_665 = _T_661 | _T_664; // @[el2_lib.scala 243:24] - wire _T_667 = &io_trigger_pkt_any_2_tdata2[10:0]; // @[el2_lib.scala 243:37] - wire _T_668 = _T_667 & _T_591; // @[el2_lib.scala 243:42] - wire _T_671 = io_trigger_pkt_any_2_tdata2[11] == lsu_match_data_2[11]; // @[el2_lib.scala 243:79] - wire _T_672 = _T_668 | _T_671; // @[el2_lib.scala 243:24] - wire _T_674 = &io_trigger_pkt_any_2_tdata2[11:0]; // @[el2_lib.scala 243:37] - wire _T_675 = _T_674 & _T_591; // @[el2_lib.scala 243:42] - wire _T_678 = io_trigger_pkt_any_2_tdata2[12] == lsu_match_data_2[12]; // @[el2_lib.scala 243:79] - wire _T_679 = _T_675 | _T_678; // @[el2_lib.scala 243:24] - wire _T_681 = &io_trigger_pkt_any_2_tdata2[12:0]; // @[el2_lib.scala 243:37] - wire _T_682 = _T_681 & _T_591; // @[el2_lib.scala 243:42] - wire _T_685 = io_trigger_pkt_any_2_tdata2[13] == lsu_match_data_2[13]; // @[el2_lib.scala 243:79] - wire _T_686 = _T_682 | _T_685; // @[el2_lib.scala 243:24] - wire _T_688 = &io_trigger_pkt_any_2_tdata2[13:0]; // @[el2_lib.scala 243:37] - wire _T_689 = _T_688 & _T_591; // @[el2_lib.scala 243:42] - wire _T_692 = io_trigger_pkt_any_2_tdata2[14] == lsu_match_data_2[14]; // @[el2_lib.scala 243:79] - wire _T_693 = _T_689 | _T_692; // @[el2_lib.scala 243:24] - wire _T_695 = &io_trigger_pkt_any_2_tdata2[14:0]; // @[el2_lib.scala 243:37] - wire _T_696 = _T_695 & _T_591; // @[el2_lib.scala 243:42] - wire _T_699 = io_trigger_pkt_any_2_tdata2[15] == lsu_match_data_2[15]; // @[el2_lib.scala 243:79] - wire _T_700 = _T_696 | _T_699; // @[el2_lib.scala 243:24] - wire _T_702 = &io_trigger_pkt_any_2_tdata2[15:0]; // @[el2_lib.scala 243:37] - wire _T_703 = _T_702 & _T_591; // @[el2_lib.scala 243:42] - wire _T_706 = io_trigger_pkt_any_2_tdata2[16] == lsu_match_data_2[16]; // @[el2_lib.scala 243:79] - wire _T_707 = _T_703 | _T_706; // @[el2_lib.scala 243:24] - wire _T_709 = &io_trigger_pkt_any_2_tdata2[16:0]; // @[el2_lib.scala 243:37] - wire _T_710 = _T_709 & _T_591; // @[el2_lib.scala 243:42] - wire _T_713 = io_trigger_pkt_any_2_tdata2[17] == lsu_match_data_2[17]; // @[el2_lib.scala 243:79] - wire _T_714 = _T_710 | _T_713; // @[el2_lib.scala 243:24] - wire _T_716 = &io_trigger_pkt_any_2_tdata2[17:0]; // @[el2_lib.scala 243:37] - wire _T_717 = _T_716 & _T_591; // @[el2_lib.scala 243:42] - wire _T_720 = io_trigger_pkt_any_2_tdata2[18] == lsu_match_data_2[18]; // @[el2_lib.scala 243:79] - wire _T_721 = _T_717 | _T_720; // @[el2_lib.scala 243:24] - wire _T_723 = &io_trigger_pkt_any_2_tdata2[18:0]; // @[el2_lib.scala 243:37] - wire _T_724 = _T_723 & _T_591; // @[el2_lib.scala 243:42] - wire _T_727 = io_trigger_pkt_any_2_tdata2[19] == lsu_match_data_2[19]; // @[el2_lib.scala 243:79] - wire _T_728 = _T_724 | _T_727; // @[el2_lib.scala 243:24] - wire _T_730 = &io_trigger_pkt_any_2_tdata2[19:0]; // @[el2_lib.scala 243:37] - wire _T_731 = _T_730 & _T_591; // @[el2_lib.scala 243:42] - wire _T_734 = io_trigger_pkt_any_2_tdata2[20] == lsu_match_data_2[20]; // @[el2_lib.scala 243:79] - wire _T_735 = _T_731 | _T_734; // @[el2_lib.scala 243:24] - wire _T_737 = &io_trigger_pkt_any_2_tdata2[20:0]; // @[el2_lib.scala 243:37] - wire _T_738 = _T_737 & _T_591; // @[el2_lib.scala 243:42] - wire _T_741 = io_trigger_pkt_any_2_tdata2[21] == lsu_match_data_2[21]; // @[el2_lib.scala 243:79] - wire _T_742 = _T_738 | _T_741; // @[el2_lib.scala 243:24] - wire _T_744 = &io_trigger_pkt_any_2_tdata2[21:0]; // @[el2_lib.scala 243:37] - wire _T_745 = _T_744 & _T_591; // @[el2_lib.scala 243:42] - wire _T_748 = io_trigger_pkt_any_2_tdata2[22] == lsu_match_data_2[22]; // @[el2_lib.scala 243:79] - wire _T_749 = _T_745 | _T_748; // @[el2_lib.scala 243:24] - wire _T_751 = &io_trigger_pkt_any_2_tdata2[22:0]; // @[el2_lib.scala 243:37] - wire _T_752 = _T_751 & _T_591; // @[el2_lib.scala 243:42] - wire _T_755 = io_trigger_pkt_any_2_tdata2[23] == lsu_match_data_2[23]; // @[el2_lib.scala 243:79] - wire _T_756 = _T_752 | _T_755; // @[el2_lib.scala 243:24] - wire _T_758 = &io_trigger_pkt_any_2_tdata2[23:0]; // @[el2_lib.scala 243:37] - wire _T_759 = _T_758 & _T_591; // @[el2_lib.scala 243:42] - wire _T_762 = io_trigger_pkt_any_2_tdata2[24] == lsu_match_data_2[24]; // @[el2_lib.scala 243:79] - wire _T_763 = _T_759 | _T_762; // @[el2_lib.scala 243:24] - wire _T_765 = &io_trigger_pkt_any_2_tdata2[24:0]; // @[el2_lib.scala 243:37] - wire _T_766 = _T_765 & _T_591; // @[el2_lib.scala 243:42] - wire _T_769 = io_trigger_pkt_any_2_tdata2[25] == lsu_match_data_2[25]; // @[el2_lib.scala 243:79] - wire _T_770 = _T_766 | _T_769; // @[el2_lib.scala 243:24] - wire _T_772 = &io_trigger_pkt_any_2_tdata2[25:0]; // @[el2_lib.scala 243:37] - wire _T_773 = _T_772 & _T_591; // @[el2_lib.scala 243:42] - wire _T_776 = io_trigger_pkt_any_2_tdata2[26] == lsu_match_data_2[26]; // @[el2_lib.scala 243:79] - wire _T_777 = _T_773 | _T_776; // @[el2_lib.scala 243:24] - wire _T_779 = &io_trigger_pkt_any_2_tdata2[26:0]; // @[el2_lib.scala 243:37] - wire _T_780 = _T_779 & _T_591; // @[el2_lib.scala 243:42] - wire _T_783 = io_trigger_pkt_any_2_tdata2[27] == lsu_match_data_2[27]; // @[el2_lib.scala 243:79] - wire _T_784 = _T_780 | _T_783; // @[el2_lib.scala 243:24] - wire _T_786 = &io_trigger_pkt_any_2_tdata2[27:0]; // @[el2_lib.scala 243:37] - wire _T_787 = _T_786 & _T_591; // @[el2_lib.scala 243:42] - wire _T_790 = io_trigger_pkt_any_2_tdata2[28] == lsu_match_data_2[28]; // @[el2_lib.scala 243:79] - wire _T_791 = _T_787 | _T_790; // @[el2_lib.scala 243:24] - wire _T_793 = &io_trigger_pkt_any_2_tdata2[28:0]; // @[el2_lib.scala 243:37] - wire _T_794 = _T_793 & _T_591; // @[el2_lib.scala 243:42] - wire _T_797 = io_trigger_pkt_any_2_tdata2[29] == lsu_match_data_2[29]; // @[el2_lib.scala 243:79] - wire _T_798 = _T_794 | _T_797; // @[el2_lib.scala 243:24] - wire _T_800 = &io_trigger_pkt_any_2_tdata2[29:0]; // @[el2_lib.scala 243:37] - wire _T_801 = _T_800 & _T_591; // @[el2_lib.scala 243:42] - wire _T_804 = io_trigger_pkt_any_2_tdata2[30] == lsu_match_data_2[30]; // @[el2_lib.scala 243:79] - wire _T_805 = _T_801 | _T_804; // @[el2_lib.scala 243:24] - wire _T_807 = &io_trigger_pkt_any_2_tdata2[30:0]; // @[el2_lib.scala 243:37] - wire _T_808 = _T_807 & _T_591; // @[el2_lib.scala 243:42] - wire _T_811 = io_trigger_pkt_any_2_tdata2[31] == lsu_match_data_2[31]; // @[el2_lib.scala 243:79] - wire _T_812 = _T_808 | _T_811; // @[el2_lib.scala 243:24] - wire [7:0] _T_819 = {_T_644,_T_637,_T_630,_T_623,_T_616,_T_609,_T_602,_T_595}; // @[el2_lib.scala 244:14] - wire [15:0] _T_827 = {_T_700,_T_693,_T_686,_T_679,_T_672,_T_665,_T_658,_T_651,_T_819}; // @[el2_lib.scala 244:14] - wire [7:0] _T_834 = {_T_756,_T_749,_T_742,_T_735,_T_728,_T_721,_T_714,_T_707}; // @[el2_lib.scala 244:14] - wire [31:0] _T_843 = {_T_812,_T_805,_T_798,_T_791,_T_784,_T_777,_T_770,_T_763,_T_834,_T_827}; // @[el2_lib.scala 244:14] - wire _T_844 = &_T_843; // @[el2_lib.scala 244:21] - wire _T_845 = _T_584 & _T_844; // @[el2_lsu_trigger.scala 19:87] - wire _T_848 = io_trigger_pkt_any_3_store & io_lsu_pkt_m_store; // @[el2_lsu_trigger.scala 18:121] - wire _T_849 = io_trigger_pkt_any_3_load & io_lsu_pkt_m_load; // @[el2_lsu_trigger.scala 19:33] - wire _T_851 = _T_849 & _T_33; // @[el2_lsu_trigger.scala 19:53] - wire _T_852 = _T_848 | _T_851; // @[el2_lsu_trigger.scala 18:142] - wire _T_853 = _T_40 & _T_852; // @[el2_lsu_trigger.scala 18:89] - wire _T_858 = &io_trigger_pkt_any_3_tdata2; // @[el2_lib.scala 240:73] - wire _T_859 = ~_T_858; // @[el2_lib.scala 240:47] - wire _T_860 = io_trigger_pkt_any_3_match_ & _T_859; // @[el2_lib.scala 240:44] - wire _T_863 = io_trigger_pkt_any_3_tdata2[0] == lsu_match_data_3[0]; // @[el2_lib.scala 241:52] - wire _T_864 = _T_860 | _T_863; // @[el2_lib.scala 241:41] - wire _T_866 = &io_trigger_pkt_any_3_tdata2[0]; // @[el2_lib.scala 243:37] - wire _T_867 = _T_866 & _T_860; // @[el2_lib.scala 243:42] - wire _T_870 = io_trigger_pkt_any_3_tdata2[1] == lsu_match_data_3[1]; // @[el2_lib.scala 243:79] - wire _T_871 = _T_867 | _T_870; // @[el2_lib.scala 243:24] - wire _T_873 = &io_trigger_pkt_any_3_tdata2[1:0]; // @[el2_lib.scala 243:37] - wire _T_874 = _T_873 & _T_860; // @[el2_lib.scala 243:42] - wire _T_877 = io_trigger_pkt_any_3_tdata2[2] == lsu_match_data_3[2]; // @[el2_lib.scala 243:79] - wire _T_878 = _T_874 | _T_877; // @[el2_lib.scala 243:24] - wire _T_880 = &io_trigger_pkt_any_3_tdata2[2:0]; // @[el2_lib.scala 243:37] - wire _T_881 = _T_880 & _T_860; // @[el2_lib.scala 243:42] - wire _T_884 = io_trigger_pkt_any_3_tdata2[3] == lsu_match_data_3[3]; // @[el2_lib.scala 243:79] - wire _T_885 = _T_881 | _T_884; // @[el2_lib.scala 243:24] - wire _T_887 = &io_trigger_pkt_any_3_tdata2[3:0]; // @[el2_lib.scala 243:37] - wire _T_888 = _T_887 & _T_860; // @[el2_lib.scala 243:42] - wire _T_891 = io_trigger_pkt_any_3_tdata2[4] == lsu_match_data_3[4]; // @[el2_lib.scala 243:79] - wire _T_892 = _T_888 | _T_891; // @[el2_lib.scala 243:24] - wire _T_894 = &io_trigger_pkt_any_3_tdata2[4:0]; // @[el2_lib.scala 243:37] - wire _T_895 = _T_894 & _T_860; // @[el2_lib.scala 243:42] - wire _T_898 = io_trigger_pkt_any_3_tdata2[5] == lsu_match_data_3[5]; // @[el2_lib.scala 243:79] - wire _T_899 = _T_895 | _T_898; // @[el2_lib.scala 243:24] - wire _T_901 = &io_trigger_pkt_any_3_tdata2[5:0]; // @[el2_lib.scala 243:37] - wire _T_902 = _T_901 & _T_860; // @[el2_lib.scala 243:42] - wire _T_905 = io_trigger_pkt_any_3_tdata2[6] == lsu_match_data_3[6]; // @[el2_lib.scala 243:79] - wire _T_906 = _T_902 | _T_905; // @[el2_lib.scala 243:24] - wire _T_908 = &io_trigger_pkt_any_3_tdata2[6:0]; // @[el2_lib.scala 243:37] - wire _T_909 = _T_908 & _T_860; // @[el2_lib.scala 243:42] - wire _T_912 = io_trigger_pkt_any_3_tdata2[7] == lsu_match_data_3[7]; // @[el2_lib.scala 243:79] - wire _T_913 = _T_909 | _T_912; // @[el2_lib.scala 243:24] - wire _T_915 = &io_trigger_pkt_any_3_tdata2[7:0]; // @[el2_lib.scala 243:37] - wire _T_916 = _T_915 & _T_860; // @[el2_lib.scala 243:42] - wire _T_919 = io_trigger_pkt_any_3_tdata2[8] == lsu_match_data_3[8]; // @[el2_lib.scala 243:79] - wire _T_920 = _T_916 | _T_919; // @[el2_lib.scala 243:24] - wire _T_922 = &io_trigger_pkt_any_3_tdata2[8:0]; // @[el2_lib.scala 243:37] - wire _T_923 = _T_922 & _T_860; // @[el2_lib.scala 243:42] - wire _T_926 = io_trigger_pkt_any_3_tdata2[9] == lsu_match_data_3[9]; // @[el2_lib.scala 243:79] - wire _T_927 = _T_923 | _T_926; // @[el2_lib.scala 243:24] - wire _T_929 = &io_trigger_pkt_any_3_tdata2[9:0]; // @[el2_lib.scala 243:37] - wire _T_930 = _T_929 & _T_860; // @[el2_lib.scala 243:42] - wire _T_933 = io_trigger_pkt_any_3_tdata2[10] == lsu_match_data_3[10]; // @[el2_lib.scala 243:79] - wire _T_934 = _T_930 | _T_933; // @[el2_lib.scala 243:24] - wire _T_936 = &io_trigger_pkt_any_3_tdata2[10:0]; // @[el2_lib.scala 243:37] - wire _T_937 = _T_936 & _T_860; // @[el2_lib.scala 243:42] - wire _T_940 = io_trigger_pkt_any_3_tdata2[11] == lsu_match_data_3[11]; // @[el2_lib.scala 243:79] - wire _T_941 = _T_937 | _T_940; // @[el2_lib.scala 243:24] - wire _T_943 = &io_trigger_pkt_any_3_tdata2[11:0]; // @[el2_lib.scala 243:37] - wire _T_944 = _T_943 & _T_860; // @[el2_lib.scala 243:42] - wire _T_947 = io_trigger_pkt_any_3_tdata2[12] == lsu_match_data_3[12]; // @[el2_lib.scala 243:79] - wire _T_948 = _T_944 | _T_947; // @[el2_lib.scala 243:24] - wire _T_950 = &io_trigger_pkt_any_3_tdata2[12:0]; // @[el2_lib.scala 243:37] - wire _T_951 = _T_950 & _T_860; // @[el2_lib.scala 243:42] - wire _T_954 = io_trigger_pkt_any_3_tdata2[13] == lsu_match_data_3[13]; // @[el2_lib.scala 243:79] - wire _T_955 = _T_951 | _T_954; // @[el2_lib.scala 243:24] - wire _T_957 = &io_trigger_pkt_any_3_tdata2[13:0]; // @[el2_lib.scala 243:37] - wire _T_958 = _T_957 & _T_860; // @[el2_lib.scala 243:42] - wire _T_961 = io_trigger_pkt_any_3_tdata2[14] == lsu_match_data_3[14]; // @[el2_lib.scala 243:79] - wire _T_962 = _T_958 | _T_961; // @[el2_lib.scala 243:24] - wire _T_964 = &io_trigger_pkt_any_3_tdata2[14:0]; // @[el2_lib.scala 243:37] - wire _T_965 = _T_964 & _T_860; // @[el2_lib.scala 243:42] - wire _T_968 = io_trigger_pkt_any_3_tdata2[15] == lsu_match_data_3[15]; // @[el2_lib.scala 243:79] - wire _T_969 = _T_965 | _T_968; // @[el2_lib.scala 243:24] - wire _T_971 = &io_trigger_pkt_any_3_tdata2[15:0]; // @[el2_lib.scala 243:37] - wire _T_972 = _T_971 & _T_860; // @[el2_lib.scala 243:42] - wire _T_975 = io_trigger_pkt_any_3_tdata2[16] == lsu_match_data_3[16]; // @[el2_lib.scala 243:79] - wire _T_976 = _T_972 | _T_975; // @[el2_lib.scala 243:24] - wire _T_978 = &io_trigger_pkt_any_3_tdata2[16:0]; // @[el2_lib.scala 243:37] - wire _T_979 = _T_978 & _T_860; // @[el2_lib.scala 243:42] - wire _T_982 = io_trigger_pkt_any_3_tdata2[17] == lsu_match_data_3[17]; // @[el2_lib.scala 243:79] - wire _T_983 = _T_979 | _T_982; // @[el2_lib.scala 243:24] - wire _T_985 = &io_trigger_pkt_any_3_tdata2[17:0]; // @[el2_lib.scala 243:37] - wire _T_986 = _T_985 & _T_860; // @[el2_lib.scala 243:42] - wire _T_989 = io_trigger_pkt_any_3_tdata2[18] == lsu_match_data_3[18]; // @[el2_lib.scala 243:79] - wire _T_990 = _T_986 | _T_989; // @[el2_lib.scala 243:24] - wire _T_992 = &io_trigger_pkt_any_3_tdata2[18:0]; // @[el2_lib.scala 243:37] - wire _T_993 = _T_992 & _T_860; // @[el2_lib.scala 243:42] - wire _T_996 = io_trigger_pkt_any_3_tdata2[19] == lsu_match_data_3[19]; // @[el2_lib.scala 243:79] - wire _T_997 = _T_993 | _T_996; // @[el2_lib.scala 243:24] - wire _T_999 = &io_trigger_pkt_any_3_tdata2[19:0]; // @[el2_lib.scala 243:37] - wire _T_1000 = _T_999 & _T_860; // @[el2_lib.scala 243:42] - wire _T_1003 = io_trigger_pkt_any_3_tdata2[20] == lsu_match_data_3[20]; // @[el2_lib.scala 243:79] - wire _T_1004 = _T_1000 | _T_1003; // @[el2_lib.scala 243:24] - wire _T_1006 = &io_trigger_pkt_any_3_tdata2[20:0]; // @[el2_lib.scala 243:37] - wire _T_1007 = _T_1006 & _T_860; // @[el2_lib.scala 243:42] - wire _T_1010 = io_trigger_pkt_any_3_tdata2[21] == lsu_match_data_3[21]; // @[el2_lib.scala 243:79] - wire _T_1011 = _T_1007 | _T_1010; // @[el2_lib.scala 243:24] - wire _T_1013 = &io_trigger_pkt_any_3_tdata2[21:0]; // @[el2_lib.scala 243:37] - wire _T_1014 = _T_1013 & _T_860; // @[el2_lib.scala 243:42] - wire _T_1017 = io_trigger_pkt_any_3_tdata2[22] == lsu_match_data_3[22]; // @[el2_lib.scala 243:79] - wire _T_1018 = _T_1014 | _T_1017; // @[el2_lib.scala 243:24] - wire _T_1020 = &io_trigger_pkt_any_3_tdata2[22:0]; // @[el2_lib.scala 243:37] - wire _T_1021 = _T_1020 & _T_860; // @[el2_lib.scala 243:42] - wire _T_1024 = io_trigger_pkt_any_3_tdata2[23] == lsu_match_data_3[23]; // @[el2_lib.scala 243:79] - wire _T_1025 = _T_1021 | _T_1024; // @[el2_lib.scala 243:24] - wire _T_1027 = &io_trigger_pkt_any_3_tdata2[23:0]; // @[el2_lib.scala 243:37] - wire _T_1028 = _T_1027 & _T_860; // @[el2_lib.scala 243:42] - wire _T_1031 = io_trigger_pkt_any_3_tdata2[24] == lsu_match_data_3[24]; // @[el2_lib.scala 243:79] - wire _T_1032 = _T_1028 | _T_1031; // @[el2_lib.scala 243:24] - wire _T_1034 = &io_trigger_pkt_any_3_tdata2[24:0]; // @[el2_lib.scala 243:37] - wire _T_1035 = _T_1034 & _T_860; // @[el2_lib.scala 243:42] - wire _T_1038 = io_trigger_pkt_any_3_tdata2[25] == lsu_match_data_3[25]; // @[el2_lib.scala 243:79] - wire _T_1039 = _T_1035 | _T_1038; // @[el2_lib.scala 243:24] - wire _T_1041 = &io_trigger_pkt_any_3_tdata2[25:0]; // @[el2_lib.scala 243:37] - wire _T_1042 = _T_1041 & _T_860; // @[el2_lib.scala 243:42] - wire _T_1045 = io_trigger_pkt_any_3_tdata2[26] == lsu_match_data_3[26]; // @[el2_lib.scala 243:79] - wire _T_1046 = _T_1042 | _T_1045; // @[el2_lib.scala 243:24] - wire _T_1048 = &io_trigger_pkt_any_3_tdata2[26:0]; // @[el2_lib.scala 243:37] - wire _T_1049 = _T_1048 & _T_860; // @[el2_lib.scala 243:42] - wire _T_1052 = io_trigger_pkt_any_3_tdata2[27] == lsu_match_data_3[27]; // @[el2_lib.scala 243:79] - wire _T_1053 = _T_1049 | _T_1052; // @[el2_lib.scala 243:24] - wire _T_1055 = &io_trigger_pkt_any_3_tdata2[27:0]; // @[el2_lib.scala 243:37] - wire _T_1056 = _T_1055 & _T_860; // @[el2_lib.scala 243:42] - wire _T_1059 = io_trigger_pkt_any_3_tdata2[28] == lsu_match_data_3[28]; // @[el2_lib.scala 243:79] - wire _T_1060 = _T_1056 | _T_1059; // @[el2_lib.scala 243:24] - wire _T_1062 = &io_trigger_pkt_any_3_tdata2[28:0]; // @[el2_lib.scala 243:37] - wire _T_1063 = _T_1062 & _T_860; // @[el2_lib.scala 243:42] - wire _T_1066 = io_trigger_pkt_any_3_tdata2[29] == lsu_match_data_3[29]; // @[el2_lib.scala 243:79] - wire _T_1067 = _T_1063 | _T_1066; // @[el2_lib.scala 243:24] - wire _T_1069 = &io_trigger_pkt_any_3_tdata2[29:0]; // @[el2_lib.scala 243:37] - wire _T_1070 = _T_1069 & _T_860; // @[el2_lib.scala 243:42] - wire _T_1073 = io_trigger_pkt_any_3_tdata2[30] == lsu_match_data_3[30]; // @[el2_lib.scala 243:79] - wire _T_1074 = _T_1070 | _T_1073; // @[el2_lib.scala 243:24] - wire _T_1076 = &io_trigger_pkt_any_3_tdata2[30:0]; // @[el2_lib.scala 243:37] - wire _T_1077 = _T_1076 & _T_860; // @[el2_lib.scala 243:42] - wire _T_1080 = io_trigger_pkt_any_3_tdata2[31] == lsu_match_data_3[31]; // @[el2_lib.scala 243:79] - wire _T_1081 = _T_1077 | _T_1080; // @[el2_lib.scala 243:24] - wire [7:0] _T_1088 = {_T_913,_T_906,_T_899,_T_892,_T_885,_T_878,_T_871,_T_864}; // @[el2_lib.scala 244:14] - wire [15:0] _T_1096 = {_T_969,_T_962,_T_955,_T_948,_T_941,_T_934,_T_927,_T_920,_T_1088}; // @[el2_lib.scala 244:14] - wire [7:0] _T_1103 = {_T_1025,_T_1018,_T_1011,_T_1004,_T_997,_T_990,_T_983,_T_976}; // @[el2_lib.scala 244:14] - wire [31:0] _T_1112 = {_T_1081,_T_1074,_T_1067,_T_1060,_T_1053,_T_1046,_T_1039,_T_1032,_T_1103,_T_1096}; // @[el2_lib.scala 244:14] - wire _T_1113 = &_T_1112; // @[el2_lib.scala 244:21] - wire _T_1114 = _T_853 & _T_1113; // @[el2_lsu_trigger.scala 19:87] - wire [2:0] _T_1116 = {_T_1114,_T_845,_T_576}; // @[Cat.scala 29:58] - assign io_lsu_trigger_match_m = {_T_1116,_T_307}; // @[el2_lsu_trigger.scala 18:26] + wire _T_41 = io_trigger_pkt_any_0_store & io_lsu_pkt_m_bits_store; // @[el2_lsu_trigger.scala 18:126] + wire _T_42 = io_trigger_pkt_any_0_load & io_lsu_pkt_m_bits_load; // @[el2_lsu_trigger.scala 19:33] + wire _T_44 = _T_42 & _T_12; // @[el2_lsu_trigger.scala 19:58] + wire _T_45 = _T_41 | _T_44; // @[el2_lsu_trigger.scala 18:152] + wire _T_46 = _T_40 & _T_45; // @[el2_lsu_trigger.scala 18:94] + wire _T_49 = &io_trigger_pkt_any_0_tdata2; // @[el2_lib.scala 241:45] + wire _T_50 = ~_T_49; // @[el2_lib.scala 241:39] + wire _T_51 = io_trigger_pkt_any_0_match_pkt & _T_50; // @[el2_lib.scala 241:37] + wire _T_54 = io_trigger_pkt_any_0_tdata2[0] == lsu_match_data_0[0]; // @[el2_lib.scala 242:52] + wire _T_55 = _T_51 | _T_54; // @[el2_lib.scala 242:41] + wire _T_57 = &io_trigger_pkt_any_0_tdata2[0]; // @[el2_lib.scala 244:36] + wire _T_58 = _T_57 & _T_51; // @[el2_lib.scala 244:41] + wire _T_61 = io_trigger_pkt_any_0_tdata2[1] == lsu_match_data_0[1]; // @[el2_lib.scala 244:78] + wire _T_62 = _T_58 | _T_61; // @[el2_lib.scala 244:23] + wire _T_64 = &io_trigger_pkt_any_0_tdata2[1:0]; // @[el2_lib.scala 244:36] + wire _T_65 = _T_64 & _T_51; // @[el2_lib.scala 244:41] + wire _T_68 = io_trigger_pkt_any_0_tdata2[2] == lsu_match_data_0[2]; // @[el2_lib.scala 244:78] + wire _T_69 = _T_65 | _T_68; // @[el2_lib.scala 244:23] + wire _T_71 = &io_trigger_pkt_any_0_tdata2[2:0]; // @[el2_lib.scala 244:36] + wire _T_72 = _T_71 & _T_51; // @[el2_lib.scala 244:41] + wire _T_75 = io_trigger_pkt_any_0_tdata2[3] == lsu_match_data_0[3]; // @[el2_lib.scala 244:78] + wire _T_76 = _T_72 | _T_75; // @[el2_lib.scala 244:23] + wire _T_78 = &io_trigger_pkt_any_0_tdata2[3:0]; // @[el2_lib.scala 244:36] + wire _T_79 = _T_78 & _T_51; // @[el2_lib.scala 244:41] + wire _T_82 = io_trigger_pkt_any_0_tdata2[4] == lsu_match_data_0[4]; // @[el2_lib.scala 244:78] + wire _T_83 = _T_79 | _T_82; // @[el2_lib.scala 244:23] + wire _T_85 = &io_trigger_pkt_any_0_tdata2[4:0]; // @[el2_lib.scala 244:36] + wire _T_86 = _T_85 & _T_51; // @[el2_lib.scala 244:41] + wire _T_89 = io_trigger_pkt_any_0_tdata2[5] == lsu_match_data_0[5]; // @[el2_lib.scala 244:78] + wire _T_90 = _T_86 | _T_89; // @[el2_lib.scala 244:23] + wire _T_92 = &io_trigger_pkt_any_0_tdata2[5:0]; // @[el2_lib.scala 244:36] + wire _T_93 = _T_92 & _T_51; // @[el2_lib.scala 244:41] + wire _T_96 = io_trigger_pkt_any_0_tdata2[6] == lsu_match_data_0[6]; // @[el2_lib.scala 244:78] + wire _T_97 = _T_93 | _T_96; // @[el2_lib.scala 244:23] + wire _T_99 = &io_trigger_pkt_any_0_tdata2[6:0]; // @[el2_lib.scala 244:36] + wire _T_100 = _T_99 & _T_51; // @[el2_lib.scala 244:41] + wire _T_103 = io_trigger_pkt_any_0_tdata2[7] == lsu_match_data_0[7]; // @[el2_lib.scala 244:78] + wire _T_104 = _T_100 | _T_103; // @[el2_lib.scala 244:23] + wire _T_106 = &io_trigger_pkt_any_0_tdata2[7:0]; // @[el2_lib.scala 244:36] + wire _T_107 = _T_106 & _T_51; // @[el2_lib.scala 244:41] + wire _T_110 = io_trigger_pkt_any_0_tdata2[8] == lsu_match_data_0[8]; // @[el2_lib.scala 244:78] + wire _T_111 = _T_107 | _T_110; // @[el2_lib.scala 244:23] + wire _T_113 = &io_trigger_pkt_any_0_tdata2[8:0]; // @[el2_lib.scala 244:36] + wire _T_114 = _T_113 & _T_51; // @[el2_lib.scala 244:41] + wire _T_117 = io_trigger_pkt_any_0_tdata2[9] == lsu_match_data_0[9]; // @[el2_lib.scala 244:78] + wire _T_118 = _T_114 | _T_117; // @[el2_lib.scala 244:23] + wire _T_120 = &io_trigger_pkt_any_0_tdata2[9:0]; // @[el2_lib.scala 244:36] + wire _T_121 = _T_120 & _T_51; // @[el2_lib.scala 244:41] + wire _T_124 = io_trigger_pkt_any_0_tdata2[10] == lsu_match_data_0[10]; // @[el2_lib.scala 244:78] + wire _T_125 = _T_121 | _T_124; // @[el2_lib.scala 244:23] + wire _T_127 = &io_trigger_pkt_any_0_tdata2[10:0]; // @[el2_lib.scala 244:36] + wire _T_128 = _T_127 & _T_51; // @[el2_lib.scala 244:41] + wire _T_131 = io_trigger_pkt_any_0_tdata2[11] == lsu_match_data_0[11]; // @[el2_lib.scala 244:78] + wire _T_132 = _T_128 | _T_131; // @[el2_lib.scala 244:23] + wire _T_134 = &io_trigger_pkt_any_0_tdata2[11:0]; // @[el2_lib.scala 244:36] + wire _T_135 = _T_134 & _T_51; // @[el2_lib.scala 244:41] + wire _T_138 = io_trigger_pkt_any_0_tdata2[12] == lsu_match_data_0[12]; // @[el2_lib.scala 244:78] + wire _T_139 = _T_135 | _T_138; // @[el2_lib.scala 244:23] + wire _T_141 = &io_trigger_pkt_any_0_tdata2[12:0]; // @[el2_lib.scala 244:36] + wire _T_142 = _T_141 & _T_51; // @[el2_lib.scala 244:41] + wire _T_145 = io_trigger_pkt_any_0_tdata2[13] == lsu_match_data_0[13]; // @[el2_lib.scala 244:78] + wire _T_146 = _T_142 | _T_145; // @[el2_lib.scala 244:23] + wire _T_148 = &io_trigger_pkt_any_0_tdata2[13:0]; // @[el2_lib.scala 244:36] + wire _T_149 = _T_148 & _T_51; // @[el2_lib.scala 244:41] + wire _T_152 = io_trigger_pkt_any_0_tdata2[14] == lsu_match_data_0[14]; // @[el2_lib.scala 244:78] + wire _T_153 = _T_149 | _T_152; // @[el2_lib.scala 244:23] + wire _T_155 = &io_trigger_pkt_any_0_tdata2[14:0]; // @[el2_lib.scala 244:36] + wire _T_156 = _T_155 & _T_51; // @[el2_lib.scala 244:41] + wire _T_159 = io_trigger_pkt_any_0_tdata2[15] == lsu_match_data_0[15]; // @[el2_lib.scala 244:78] + wire _T_160 = _T_156 | _T_159; // @[el2_lib.scala 244:23] + wire _T_162 = &io_trigger_pkt_any_0_tdata2[15:0]; // @[el2_lib.scala 244:36] + wire _T_163 = _T_162 & _T_51; // @[el2_lib.scala 244:41] + wire _T_166 = io_trigger_pkt_any_0_tdata2[16] == lsu_match_data_0[16]; // @[el2_lib.scala 244:78] + wire _T_167 = _T_163 | _T_166; // @[el2_lib.scala 244:23] + wire _T_169 = &io_trigger_pkt_any_0_tdata2[16:0]; // @[el2_lib.scala 244:36] + wire _T_170 = _T_169 & _T_51; // @[el2_lib.scala 244:41] + wire _T_173 = io_trigger_pkt_any_0_tdata2[17] == lsu_match_data_0[17]; // @[el2_lib.scala 244:78] + wire _T_174 = _T_170 | _T_173; // @[el2_lib.scala 244:23] + wire _T_176 = &io_trigger_pkt_any_0_tdata2[17:0]; // @[el2_lib.scala 244:36] + wire _T_177 = _T_176 & _T_51; // @[el2_lib.scala 244:41] + wire _T_180 = io_trigger_pkt_any_0_tdata2[18] == lsu_match_data_0[18]; // @[el2_lib.scala 244:78] + wire _T_181 = _T_177 | _T_180; // @[el2_lib.scala 244:23] + wire _T_183 = &io_trigger_pkt_any_0_tdata2[18:0]; // @[el2_lib.scala 244:36] + wire _T_184 = _T_183 & _T_51; // @[el2_lib.scala 244:41] + wire _T_187 = io_trigger_pkt_any_0_tdata2[19] == lsu_match_data_0[19]; // @[el2_lib.scala 244:78] + wire _T_188 = _T_184 | _T_187; // @[el2_lib.scala 244:23] + wire _T_190 = &io_trigger_pkt_any_0_tdata2[19:0]; // @[el2_lib.scala 244:36] + wire _T_191 = _T_190 & _T_51; // @[el2_lib.scala 244:41] + wire _T_194 = io_trigger_pkt_any_0_tdata2[20] == lsu_match_data_0[20]; // @[el2_lib.scala 244:78] + wire _T_195 = _T_191 | _T_194; // @[el2_lib.scala 244:23] + wire _T_197 = &io_trigger_pkt_any_0_tdata2[20:0]; // @[el2_lib.scala 244:36] + wire _T_198 = _T_197 & _T_51; // @[el2_lib.scala 244:41] + wire _T_201 = io_trigger_pkt_any_0_tdata2[21] == lsu_match_data_0[21]; // @[el2_lib.scala 244:78] + wire _T_202 = _T_198 | _T_201; // @[el2_lib.scala 244:23] + wire _T_204 = &io_trigger_pkt_any_0_tdata2[21:0]; // @[el2_lib.scala 244:36] + wire _T_205 = _T_204 & _T_51; // @[el2_lib.scala 244:41] + wire _T_208 = io_trigger_pkt_any_0_tdata2[22] == lsu_match_data_0[22]; // @[el2_lib.scala 244:78] + wire _T_209 = _T_205 | _T_208; // @[el2_lib.scala 244:23] + wire _T_211 = &io_trigger_pkt_any_0_tdata2[22:0]; // @[el2_lib.scala 244:36] + wire _T_212 = _T_211 & _T_51; // @[el2_lib.scala 244:41] + wire _T_215 = io_trigger_pkt_any_0_tdata2[23] == lsu_match_data_0[23]; // @[el2_lib.scala 244:78] + wire _T_216 = _T_212 | _T_215; // @[el2_lib.scala 244:23] + wire _T_218 = &io_trigger_pkt_any_0_tdata2[23:0]; // @[el2_lib.scala 244:36] + wire _T_219 = _T_218 & _T_51; // @[el2_lib.scala 244:41] + wire _T_222 = io_trigger_pkt_any_0_tdata2[24] == lsu_match_data_0[24]; // @[el2_lib.scala 244:78] + wire _T_223 = _T_219 | _T_222; // @[el2_lib.scala 244:23] + wire _T_225 = &io_trigger_pkt_any_0_tdata2[24:0]; // @[el2_lib.scala 244:36] + wire _T_226 = _T_225 & _T_51; // @[el2_lib.scala 244:41] + wire _T_229 = io_trigger_pkt_any_0_tdata2[25] == lsu_match_data_0[25]; // @[el2_lib.scala 244:78] + wire _T_230 = _T_226 | _T_229; // @[el2_lib.scala 244:23] + wire _T_232 = &io_trigger_pkt_any_0_tdata2[25:0]; // @[el2_lib.scala 244:36] + wire _T_233 = _T_232 & _T_51; // @[el2_lib.scala 244:41] + wire _T_236 = io_trigger_pkt_any_0_tdata2[26] == lsu_match_data_0[26]; // @[el2_lib.scala 244:78] + wire _T_237 = _T_233 | _T_236; // @[el2_lib.scala 244:23] + wire _T_239 = &io_trigger_pkt_any_0_tdata2[26:0]; // @[el2_lib.scala 244:36] + wire _T_240 = _T_239 & _T_51; // @[el2_lib.scala 244:41] + wire _T_243 = io_trigger_pkt_any_0_tdata2[27] == lsu_match_data_0[27]; // @[el2_lib.scala 244:78] + wire _T_244 = _T_240 | _T_243; // @[el2_lib.scala 244:23] + wire _T_246 = &io_trigger_pkt_any_0_tdata2[27:0]; // @[el2_lib.scala 244:36] + wire _T_247 = _T_246 & _T_51; // @[el2_lib.scala 244:41] + wire _T_250 = io_trigger_pkt_any_0_tdata2[28] == lsu_match_data_0[28]; // @[el2_lib.scala 244:78] + wire _T_251 = _T_247 | _T_250; // @[el2_lib.scala 244:23] + wire _T_253 = &io_trigger_pkt_any_0_tdata2[28:0]; // @[el2_lib.scala 244:36] + wire _T_254 = _T_253 & _T_51; // @[el2_lib.scala 244:41] + wire _T_257 = io_trigger_pkt_any_0_tdata2[29] == lsu_match_data_0[29]; // @[el2_lib.scala 244:78] + wire _T_258 = _T_254 | _T_257; // @[el2_lib.scala 244:23] + wire _T_260 = &io_trigger_pkt_any_0_tdata2[29:0]; // @[el2_lib.scala 244:36] + wire _T_261 = _T_260 & _T_51; // @[el2_lib.scala 244:41] + wire _T_264 = io_trigger_pkt_any_0_tdata2[30] == lsu_match_data_0[30]; // @[el2_lib.scala 244:78] + wire _T_265 = _T_261 | _T_264; // @[el2_lib.scala 244:23] + wire _T_267 = &io_trigger_pkt_any_0_tdata2[30:0]; // @[el2_lib.scala 244:36] + wire _T_268 = _T_267 & _T_51; // @[el2_lib.scala 244:41] + wire _T_271 = io_trigger_pkt_any_0_tdata2[31] == lsu_match_data_0[31]; // @[el2_lib.scala 244:78] + wire _T_272 = _T_268 | _T_271; // @[el2_lib.scala 244:23] + wire [7:0] _T_279 = {_T_104,_T_97,_T_90,_T_83,_T_76,_T_69,_T_62,_T_55}; // @[el2_lib.scala 245:14] + wire [15:0] _T_287 = {_T_160,_T_153,_T_146,_T_139,_T_132,_T_125,_T_118,_T_111,_T_279}; // @[el2_lib.scala 245:14] + wire [7:0] _T_294 = {_T_216,_T_209,_T_202,_T_195,_T_188,_T_181,_T_174,_T_167}; // @[el2_lib.scala 245:14] + wire [31:0] _T_303 = {_T_272,_T_265,_T_258,_T_251,_T_244,_T_237,_T_230,_T_223,_T_294,_T_287}; // @[el2_lib.scala 245:14] + wire [31:0] _GEN_0 = {{31'd0}, _T_46}; // @[el2_lsu_trigger.scala 19:92] + wire [31:0] _T_304 = _GEN_0 & _T_303; // @[el2_lsu_trigger.scala 19:92] + wire _T_307 = io_trigger_pkt_any_1_store & io_lsu_pkt_m_bits_store; // @[el2_lsu_trigger.scala 18:126] + wire _T_308 = io_trigger_pkt_any_1_load & io_lsu_pkt_m_bits_load; // @[el2_lsu_trigger.scala 19:33] + wire _T_310 = _T_308 & _T_19; // @[el2_lsu_trigger.scala 19:58] + wire _T_311 = _T_307 | _T_310; // @[el2_lsu_trigger.scala 18:152] + wire _T_312 = _T_40 & _T_311; // @[el2_lsu_trigger.scala 18:94] + wire _T_315 = &io_trigger_pkt_any_1_tdata2; // @[el2_lib.scala 241:45] + wire _T_316 = ~_T_315; // @[el2_lib.scala 241:39] + wire _T_317 = io_trigger_pkt_any_1_match_pkt & _T_316; // @[el2_lib.scala 241:37] + wire _T_320 = io_trigger_pkt_any_1_tdata2[0] == lsu_match_data_1[0]; // @[el2_lib.scala 242:52] + wire _T_321 = _T_317 | _T_320; // @[el2_lib.scala 242:41] + wire _T_323 = &io_trigger_pkt_any_1_tdata2[0]; // @[el2_lib.scala 244:36] + wire _T_324 = _T_323 & _T_317; // @[el2_lib.scala 244:41] + wire _T_327 = io_trigger_pkt_any_1_tdata2[1] == lsu_match_data_1[1]; // @[el2_lib.scala 244:78] + wire _T_328 = _T_324 | _T_327; // @[el2_lib.scala 244:23] + wire _T_330 = &io_trigger_pkt_any_1_tdata2[1:0]; // @[el2_lib.scala 244:36] + wire _T_331 = _T_330 & _T_317; // @[el2_lib.scala 244:41] + wire _T_334 = io_trigger_pkt_any_1_tdata2[2] == lsu_match_data_1[2]; // @[el2_lib.scala 244:78] + wire _T_335 = _T_331 | _T_334; // @[el2_lib.scala 244:23] + wire _T_337 = &io_trigger_pkt_any_1_tdata2[2:0]; // @[el2_lib.scala 244:36] + wire _T_338 = _T_337 & _T_317; // @[el2_lib.scala 244:41] + wire _T_341 = io_trigger_pkt_any_1_tdata2[3] == lsu_match_data_1[3]; // @[el2_lib.scala 244:78] + wire _T_342 = _T_338 | _T_341; // @[el2_lib.scala 244:23] + wire _T_344 = &io_trigger_pkt_any_1_tdata2[3:0]; // @[el2_lib.scala 244:36] + wire _T_345 = _T_344 & _T_317; // @[el2_lib.scala 244:41] + wire _T_348 = io_trigger_pkt_any_1_tdata2[4] == lsu_match_data_1[4]; // @[el2_lib.scala 244:78] + wire _T_349 = _T_345 | _T_348; // @[el2_lib.scala 244:23] + wire _T_351 = &io_trigger_pkt_any_1_tdata2[4:0]; // @[el2_lib.scala 244:36] + wire _T_352 = _T_351 & _T_317; // @[el2_lib.scala 244:41] + wire _T_355 = io_trigger_pkt_any_1_tdata2[5] == lsu_match_data_1[5]; // @[el2_lib.scala 244:78] + wire _T_356 = _T_352 | _T_355; // @[el2_lib.scala 244:23] + wire _T_358 = &io_trigger_pkt_any_1_tdata2[5:0]; // @[el2_lib.scala 244:36] + wire _T_359 = _T_358 & _T_317; // @[el2_lib.scala 244:41] + wire _T_362 = io_trigger_pkt_any_1_tdata2[6] == lsu_match_data_1[6]; // @[el2_lib.scala 244:78] + wire _T_363 = _T_359 | _T_362; // @[el2_lib.scala 244:23] + wire _T_365 = &io_trigger_pkt_any_1_tdata2[6:0]; // @[el2_lib.scala 244:36] + wire _T_366 = _T_365 & _T_317; // @[el2_lib.scala 244:41] + wire _T_369 = io_trigger_pkt_any_1_tdata2[7] == lsu_match_data_1[7]; // @[el2_lib.scala 244:78] + wire _T_370 = _T_366 | _T_369; // @[el2_lib.scala 244:23] + wire _T_372 = &io_trigger_pkt_any_1_tdata2[7:0]; // @[el2_lib.scala 244:36] + wire _T_373 = _T_372 & _T_317; // @[el2_lib.scala 244:41] + wire _T_376 = io_trigger_pkt_any_1_tdata2[8] == lsu_match_data_1[8]; // @[el2_lib.scala 244:78] + wire _T_377 = _T_373 | _T_376; // @[el2_lib.scala 244:23] + wire _T_379 = &io_trigger_pkt_any_1_tdata2[8:0]; // @[el2_lib.scala 244:36] + wire _T_380 = _T_379 & _T_317; // @[el2_lib.scala 244:41] + wire _T_383 = io_trigger_pkt_any_1_tdata2[9] == lsu_match_data_1[9]; // @[el2_lib.scala 244:78] + wire _T_384 = _T_380 | _T_383; // @[el2_lib.scala 244:23] + wire _T_386 = &io_trigger_pkt_any_1_tdata2[9:0]; // @[el2_lib.scala 244:36] + wire _T_387 = _T_386 & _T_317; // @[el2_lib.scala 244:41] + wire _T_390 = io_trigger_pkt_any_1_tdata2[10] == lsu_match_data_1[10]; // @[el2_lib.scala 244:78] + wire _T_391 = _T_387 | _T_390; // @[el2_lib.scala 244:23] + wire _T_393 = &io_trigger_pkt_any_1_tdata2[10:0]; // @[el2_lib.scala 244:36] + wire _T_394 = _T_393 & _T_317; // @[el2_lib.scala 244:41] + wire _T_397 = io_trigger_pkt_any_1_tdata2[11] == lsu_match_data_1[11]; // @[el2_lib.scala 244:78] + wire _T_398 = _T_394 | _T_397; // @[el2_lib.scala 244:23] + wire _T_400 = &io_trigger_pkt_any_1_tdata2[11:0]; // @[el2_lib.scala 244:36] + wire _T_401 = _T_400 & _T_317; // @[el2_lib.scala 244:41] + wire _T_404 = io_trigger_pkt_any_1_tdata2[12] == lsu_match_data_1[12]; // @[el2_lib.scala 244:78] + wire _T_405 = _T_401 | _T_404; // @[el2_lib.scala 244:23] + wire _T_407 = &io_trigger_pkt_any_1_tdata2[12:0]; // @[el2_lib.scala 244:36] + wire _T_408 = _T_407 & _T_317; // @[el2_lib.scala 244:41] + wire _T_411 = io_trigger_pkt_any_1_tdata2[13] == lsu_match_data_1[13]; // @[el2_lib.scala 244:78] + wire _T_412 = _T_408 | _T_411; // @[el2_lib.scala 244:23] + wire _T_414 = &io_trigger_pkt_any_1_tdata2[13:0]; // @[el2_lib.scala 244:36] + wire _T_415 = _T_414 & _T_317; // @[el2_lib.scala 244:41] + wire _T_418 = io_trigger_pkt_any_1_tdata2[14] == lsu_match_data_1[14]; // @[el2_lib.scala 244:78] + wire _T_419 = _T_415 | _T_418; // @[el2_lib.scala 244:23] + wire _T_421 = &io_trigger_pkt_any_1_tdata2[14:0]; // @[el2_lib.scala 244:36] + wire _T_422 = _T_421 & _T_317; // @[el2_lib.scala 244:41] + wire _T_425 = io_trigger_pkt_any_1_tdata2[15] == lsu_match_data_1[15]; // @[el2_lib.scala 244:78] + wire _T_426 = _T_422 | _T_425; // @[el2_lib.scala 244:23] + wire _T_428 = &io_trigger_pkt_any_1_tdata2[15:0]; // @[el2_lib.scala 244:36] + wire _T_429 = _T_428 & _T_317; // @[el2_lib.scala 244:41] + wire _T_432 = io_trigger_pkt_any_1_tdata2[16] == lsu_match_data_1[16]; // @[el2_lib.scala 244:78] + wire _T_433 = _T_429 | _T_432; // @[el2_lib.scala 244:23] + wire _T_435 = &io_trigger_pkt_any_1_tdata2[16:0]; // @[el2_lib.scala 244:36] + wire _T_436 = _T_435 & _T_317; // @[el2_lib.scala 244:41] + wire _T_439 = io_trigger_pkt_any_1_tdata2[17] == lsu_match_data_1[17]; // @[el2_lib.scala 244:78] + wire _T_440 = _T_436 | _T_439; // @[el2_lib.scala 244:23] + wire _T_442 = &io_trigger_pkt_any_1_tdata2[17:0]; // @[el2_lib.scala 244:36] + wire _T_443 = _T_442 & _T_317; // @[el2_lib.scala 244:41] + wire _T_446 = io_trigger_pkt_any_1_tdata2[18] == lsu_match_data_1[18]; // @[el2_lib.scala 244:78] + wire _T_447 = _T_443 | _T_446; // @[el2_lib.scala 244:23] + wire _T_449 = &io_trigger_pkt_any_1_tdata2[18:0]; // @[el2_lib.scala 244:36] + wire _T_450 = _T_449 & _T_317; // @[el2_lib.scala 244:41] + wire _T_453 = io_trigger_pkt_any_1_tdata2[19] == lsu_match_data_1[19]; // @[el2_lib.scala 244:78] + wire _T_454 = _T_450 | _T_453; // @[el2_lib.scala 244:23] + wire _T_456 = &io_trigger_pkt_any_1_tdata2[19:0]; // @[el2_lib.scala 244:36] + wire _T_457 = _T_456 & _T_317; // @[el2_lib.scala 244:41] + wire _T_460 = io_trigger_pkt_any_1_tdata2[20] == lsu_match_data_1[20]; // @[el2_lib.scala 244:78] + wire _T_461 = _T_457 | _T_460; // @[el2_lib.scala 244:23] + wire _T_463 = &io_trigger_pkt_any_1_tdata2[20:0]; // @[el2_lib.scala 244:36] + wire _T_464 = _T_463 & _T_317; // @[el2_lib.scala 244:41] + wire _T_467 = io_trigger_pkt_any_1_tdata2[21] == lsu_match_data_1[21]; // @[el2_lib.scala 244:78] + wire _T_468 = _T_464 | _T_467; // @[el2_lib.scala 244:23] + wire _T_470 = &io_trigger_pkt_any_1_tdata2[21:0]; // @[el2_lib.scala 244:36] + wire _T_471 = _T_470 & _T_317; // @[el2_lib.scala 244:41] + wire _T_474 = io_trigger_pkt_any_1_tdata2[22] == lsu_match_data_1[22]; // @[el2_lib.scala 244:78] + wire _T_475 = _T_471 | _T_474; // @[el2_lib.scala 244:23] + wire _T_477 = &io_trigger_pkt_any_1_tdata2[22:0]; // @[el2_lib.scala 244:36] + wire _T_478 = _T_477 & _T_317; // @[el2_lib.scala 244:41] + wire _T_481 = io_trigger_pkt_any_1_tdata2[23] == lsu_match_data_1[23]; // @[el2_lib.scala 244:78] + wire _T_482 = _T_478 | _T_481; // @[el2_lib.scala 244:23] + wire _T_484 = &io_trigger_pkt_any_1_tdata2[23:0]; // @[el2_lib.scala 244:36] + wire _T_485 = _T_484 & _T_317; // @[el2_lib.scala 244:41] + wire _T_488 = io_trigger_pkt_any_1_tdata2[24] == lsu_match_data_1[24]; // @[el2_lib.scala 244:78] + wire _T_489 = _T_485 | _T_488; // @[el2_lib.scala 244:23] + wire _T_491 = &io_trigger_pkt_any_1_tdata2[24:0]; // @[el2_lib.scala 244:36] + wire _T_492 = _T_491 & _T_317; // @[el2_lib.scala 244:41] + wire _T_495 = io_trigger_pkt_any_1_tdata2[25] == lsu_match_data_1[25]; // @[el2_lib.scala 244:78] + wire _T_496 = _T_492 | _T_495; // @[el2_lib.scala 244:23] + wire _T_498 = &io_trigger_pkt_any_1_tdata2[25:0]; // @[el2_lib.scala 244:36] + wire _T_499 = _T_498 & _T_317; // @[el2_lib.scala 244:41] + wire _T_502 = io_trigger_pkt_any_1_tdata2[26] == lsu_match_data_1[26]; // @[el2_lib.scala 244:78] + wire _T_503 = _T_499 | _T_502; // @[el2_lib.scala 244:23] + wire _T_505 = &io_trigger_pkt_any_1_tdata2[26:0]; // @[el2_lib.scala 244:36] + wire _T_506 = _T_505 & _T_317; // @[el2_lib.scala 244:41] + wire _T_509 = io_trigger_pkt_any_1_tdata2[27] == lsu_match_data_1[27]; // @[el2_lib.scala 244:78] + wire _T_510 = _T_506 | _T_509; // @[el2_lib.scala 244:23] + wire _T_512 = &io_trigger_pkt_any_1_tdata2[27:0]; // @[el2_lib.scala 244:36] + wire _T_513 = _T_512 & _T_317; // @[el2_lib.scala 244:41] + wire _T_516 = io_trigger_pkt_any_1_tdata2[28] == lsu_match_data_1[28]; // @[el2_lib.scala 244:78] + wire _T_517 = _T_513 | _T_516; // @[el2_lib.scala 244:23] + wire _T_519 = &io_trigger_pkt_any_1_tdata2[28:0]; // @[el2_lib.scala 244:36] + wire _T_520 = _T_519 & _T_317; // @[el2_lib.scala 244:41] + wire _T_523 = io_trigger_pkt_any_1_tdata2[29] == lsu_match_data_1[29]; // @[el2_lib.scala 244:78] + wire _T_524 = _T_520 | _T_523; // @[el2_lib.scala 244:23] + wire _T_526 = &io_trigger_pkt_any_1_tdata2[29:0]; // @[el2_lib.scala 244:36] + wire _T_527 = _T_526 & _T_317; // @[el2_lib.scala 244:41] + wire _T_530 = io_trigger_pkt_any_1_tdata2[30] == lsu_match_data_1[30]; // @[el2_lib.scala 244:78] + wire _T_531 = _T_527 | _T_530; // @[el2_lib.scala 244:23] + wire _T_533 = &io_trigger_pkt_any_1_tdata2[30:0]; // @[el2_lib.scala 244:36] + wire _T_534 = _T_533 & _T_317; // @[el2_lib.scala 244:41] + wire _T_537 = io_trigger_pkt_any_1_tdata2[31] == lsu_match_data_1[31]; // @[el2_lib.scala 244:78] + wire _T_538 = _T_534 | _T_537; // @[el2_lib.scala 244:23] + wire [7:0] _T_545 = {_T_370,_T_363,_T_356,_T_349,_T_342,_T_335,_T_328,_T_321}; // @[el2_lib.scala 245:14] + wire [15:0] _T_553 = {_T_426,_T_419,_T_412,_T_405,_T_398,_T_391,_T_384,_T_377,_T_545}; // @[el2_lib.scala 245:14] + wire [7:0] _T_560 = {_T_482,_T_475,_T_468,_T_461,_T_454,_T_447,_T_440,_T_433}; // @[el2_lib.scala 245:14] + wire [31:0] _T_569 = {_T_538,_T_531,_T_524,_T_517,_T_510,_T_503,_T_496,_T_489,_T_560,_T_553}; // @[el2_lib.scala 245:14] + wire [31:0] _GEN_1 = {{31'd0}, _T_312}; // @[el2_lsu_trigger.scala 19:92] + wire [31:0] _T_570 = _GEN_1 & _T_569; // @[el2_lsu_trigger.scala 19:92] + wire _T_573 = io_trigger_pkt_any_2_store & io_lsu_pkt_m_bits_store; // @[el2_lsu_trigger.scala 18:126] + wire _T_574 = io_trigger_pkt_any_2_load & io_lsu_pkt_m_bits_load; // @[el2_lsu_trigger.scala 19:33] + wire _T_576 = _T_574 & _T_26; // @[el2_lsu_trigger.scala 19:58] + wire _T_577 = _T_573 | _T_576; // @[el2_lsu_trigger.scala 18:152] + wire _T_578 = _T_40 & _T_577; // @[el2_lsu_trigger.scala 18:94] + wire _T_581 = &io_trigger_pkt_any_2_tdata2; // @[el2_lib.scala 241:45] + wire _T_582 = ~_T_581; // @[el2_lib.scala 241:39] + wire _T_583 = io_trigger_pkt_any_2_match_pkt & _T_582; // @[el2_lib.scala 241:37] + wire _T_586 = io_trigger_pkt_any_2_tdata2[0] == lsu_match_data_2[0]; // @[el2_lib.scala 242:52] + wire _T_587 = _T_583 | _T_586; // @[el2_lib.scala 242:41] + wire _T_589 = &io_trigger_pkt_any_2_tdata2[0]; // @[el2_lib.scala 244:36] + wire _T_590 = _T_589 & _T_583; // @[el2_lib.scala 244:41] + wire _T_593 = io_trigger_pkt_any_2_tdata2[1] == lsu_match_data_2[1]; // @[el2_lib.scala 244:78] + wire _T_594 = _T_590 | _T_593; // @[el2_lib.scala 244:23] + wire _T_596 = &io_trigger_pkt_any_2_tdata2[1:0]; // @[el2_lib.scala 244:36] + wire _T_597 = _T_596 & _T_583; // @[el2_lib.scala 244:41] + wire _T_600 = io_trigger_pkt_any_2_tdata2[2] == lsu_match_data_2[2]; // @[el2_lib.scala 244:78] + wire _T_601 = _T_597 | _T_600; // @[el2_lib.scala 244:23] + wire _T_603 = &io_trigger_pkt_any_2_tdata2[2:0]; // @[el2_lib.scala 244:36] + wire _T_604 = _T_603 & _T_583; // @[el2_lib.scala 244:41] + wire _T_607 = io_trigger_pkt_any_2_tdata2[3] == lsu_match_data_2[3]; // @[el2_lib.scala 244:78] + wire _T_608 = _T_604 | _T_607; // @[el2_lib.scala 244:23] + wire _T_610 = &io_trigger_pkt_any_2_tdata2[3:0]; // @[el2_lib.scala 244:36] + wire _T_611 = _T_610 & _T_583; // @[el2_lib.scala 244:41] + wire _T_614 = io_trigger_pkt_any_2_tdata2[4] == lsu_match_data_2[4]; // @[el2_lib.scala 244:78] + wire _T_615 = _T_611 | _T_614; // @[el2_lib.scala 244:23] + wire _T_617 = &io_trigger_pkt_any_2_tdata2[4:0]; // @[el2_lib.scala 244:36] + wire _T_618 = _T_617 & _T_583; // @[el2_lib.scala 244:41] + wire _T_621 = io_trigger_pkt_any_2_tdata2[5] == lsu_match_data_2[5]; // @[el2_lib.scala 244:78] + wire _T_622 = _T_618 | _T_621; // @[el2_lib.scala 244:23] + wire _T_624 = &io_trigger_pkt_any_2_tdata2[5:0]; // @[el2_lib.scala 244:36] + wire _T_625 = _T_624 & _T_583; // @[el2_lib.scala 244:41] + wire _T_628 = io_trigger_pkt_any_2_tdata2[6] == lsu_match_data_2[6]; // @[el2_lib.scala 244:78] + wire _T_629 = _T_625 | _T_628; // @[el2_lib.scala 244:23] + wire _T_631 = &io_trigger_pkt_any_2_tdata2[6:0]; // @[el2_lib.scala 244:36] + wire _T_632 = _T_631 & _T_583; // @[el2_lib.scala 244:41] + wire _T_635 = io_trigger_pkt_any_2_tdata2[7] == lsu_match_data_2[7]; // @[el2_lib.scala 244:78] + wire _T_636 = _T_632 | _T_635; // @[el2_lib.scala 244:23] + wire _T_638 = &io_trigger_pkt_any_2_tdata2[7:0]; // @[el2_lib.scala 244:36] + wire _T_639 = _T_638 & _T_583; // @[el2_lib.scala 244:41] + wire _T_642 = io_trigger_pkt_any_2_tdata2[8] == lsu_match_data_2[8]; // @[el2_lib.scala 244:78] + wire _T_643 = _T_639 | _T_642; // @[el2_lib.scala 244:23] + wire _T_645 = &io_trigger_pkt_any_2_tdata2[8:0]; // @[el2_lib.scala 244:36] + wire _T_646 = _T_645 & _T_583; // @[el2_lib.scala 244:41] + wire _T_649 = io_trigger_pkt_any_2_tdata2[9] == lsu_match_data_2[9]; // @[el2_lib.scala 244:78] + wire _T_650 = _T_646 | _T_649; // @[el2_lib.scala 244:23] + wire _T_652 = &io_trigger_pkt_any_2_tdata2[9:0]; // @[el2_lib.scala 244:36] + wire _T_653 = _T_652 & _T_583; // @[el2_lib.scala 244:41] + wire _T_656 = io_trigger_pkt_any_2_tdata2[10] == lsu_match_data_2[10]; // @[el2_lib.scala 244:78] + wire _T_657 = _T_653 | _T_656; // @[el2_lib.scala 244:23] + wire _T_659 = &io_trigger_pkt_any_2_tdata2[10:0]; // @[el2_lib.scala 244:36] + wire _T_660 = _T_659 & _T_583; // @[el2_lib.scala 244:41] + wire _T_663 = io_trigger_pkt_any_2_tdata2[11] == lsu_match_data_2[11]; // @[el2_lib.scala 244:78] + wire _T_664 = _T_660 | _T_663; // @[el2_lib.scala 244:23] + wire _T_666 = &io_trigger_pkt_any_2_tdata2[11:0]; // @[el2_lib.scala 244:36] + wire _T_667 = _T_666 & _T_583; // @[el2_lib.scala 244:41] + wire _T_670 = io_trigger_pkt_any_2_tdata2[12] == lsu_match_data_2[12]; // @[el2_lib.scala 244:78] + wire _T_671 = _T_667 | _T_670; // @[el2_lib.scala 244:23] + wire _T_673 = &io_trigger_pkt_any_2_tdata2[12:0]; // @[el2_lib.scala 244:36] + wire _T_674 = _T_673 & _T_583; // @[el2_lib.scala 244:41] + wire _T_677 = io_trigger_pkt_any_2_tdata2[13] == lsu_match_data_2[13]; // @[el2_lib.scala 244:78] + wire _T_678 = _T_674 | _T_677; // @[el2_lib.scala 244:23] + wire _T_680 = &io_trigger_pkt_any_2_tdata2[13:0]; // @[el2_lib.scala 244:36] + wire _T_681 = _T_680 & _T_583; // @[el2_lib.scala 244:41] + wire _T_684 = io_trigger_pkt_any_2_tdata2[14] == lsu_match_data_2[14]; // @[el2_lib.scala 244:78] + wire _T_685 = _T_681 | _T_684; // @[el2_lib.scala 244:23] + wire _T_687 = &io_trigger_pkt_any_2_tdata2[14:0]; // @[el2_lib.scala 244:36] + wire _T_688 = _T_687 & _T_583; // @[el2_lib.scala 244:41] + wire _T_691 = io_trigger_pkt_any_2_tdata2[15] == lsu_match_data_2[15]; // @[el2_lib.scala 244:78] + wire _T_692 = _T_688 | _T_691; // @[el2_lib.scala 244:23] + wire _T_694 = &io_trigger_pkt_any_2_tdata2[15:0]; // @[el2_lib.scala 244:36] + wire _T_695 = _T_694 & _T_583; // @[el2_lib.scala 244:41] + wire _T_698 = io_trigger_pkt_any_2_tdata2[16] == lsu_match_data_2[16]; // @[el2_lib.scala 244:78] + wire _T_699 = _T_695 | _T_698; // @[el2_lib.scala 244:23] + wire _T_701 = &io_trigger_pkt_any_2_tdata2[16:0]; // @[el2_lib.scala 244:36] + wire _T_702 = _T_701 & _T_583; // @[el2_lib.scala 244:41] + wire _T_705 = io_trigger_pkt_any_2_tdata2[17] == lsu_match_data_2[17]; // @[el2_lib.scala 244:78] + wire _T_706 = _T_702 | _T_705; // @[el2_lib.scala 244:23] + wire _T_708 = &io_trigger_pkt_any_2_tdata2[17:0]; // @[el2_lib.scala 244:36] + wire _T_709 = _T_708 & _T_583; // @[el2_lib.scala 244:41] + wire _T_712 = io_trigger_pkt_any_2_tdata2[18] == lsu_match_data_2[18]; // @[el2_lib.scala 244:78] + wire _T_713 = _T_709 | _T_712; // @[el2_lib.scala 244:23] + wire _T_715 = &io_trigger_pkt_any_2_tdata2[18:0]; // @[el2_lib.scala 244:36] + wire _T_716 = _T_715 & _T_583; // @[el2_lib.scala 244:41] + wire _T_719 = io_trigger_pkt_any_2_tdata2[19] == lsu_match_data_2[19]; // @[el2_lib.scala 244:78] + wire _T_720 = _T_716 | _T_719; // @[el2_lib.scala 244:23] + wire _T_722 = &io_trigger_pkt_any_2_tdata2[19:0]; // @[el2_lib.scala 244:36] + wire _T_723 = _T_722 & _T_583; // @[el2_lib.scala 244:41] + wire _T_726 = io_trigger_pkt_any_2_tdata2[20] == lsu_match_data_2[20]; // @[el2_lib.scala 244:78] + wire _T_727 = _T_723 | _T_726; // @[el2_lib.scala 244:23] + wire _T_729 = &io_trigger_pkt_any_2_tdata2[20:0]; // @[el2_lib.scala 244:36] + wire _T_730 = _T_729 & _T_583; // @[el2_lib.scala 244:41] + wire _T_733 = io_trigger_pkt_any_2_tdata2[21] == lsu_match_data_2[21]; // @[el2_lib.scala 244:78] + wire _T_734 = _T_730 | _T_733; // @[el2_lib.scala 244:23] + wire _T_736 = &io_trigger_pkt_any_2_tdata2[21:0]; // @[el2_lib.scala 244:36] + wire _T_737 = _T_736 & _T_583; // @[el2_lib.scala 244:41] + wire _T_740 = io_trigger_pkt_any_2_tdata2[22] == lsu_match_data_2[22]; // @[el2_lib.scala 244:78] + wire _T_741 = _T_737 | _T_740; // @[el2_lib.scala 244:23] + wire _T_743 = &io_trigger_pkt_any_2_tdata2[22:0]; // @[el2_lib.scala 244:36] + wire _T_744 = _T_743 & _T_583; // @[el2_lib.scala 244:41] + wire _T_747 = io_trigger_pkt_any_2_tdata2[23] == lsu_match_data_2[23]; // @[el2_lib.scala 244:78] + wire _T_748 = _T_744 | _T_747; // @[el2_lib.scala 244:23] + wire _T_750 = &io_trigger_pkt_any_2_tdata2[23:0]; // @[el2_lib.scala 244:36] + wire _T_751 = _T_750 & _T_583; // @[el2_lib.scala 244:41] + wire _T_754 = io_trigger_pkt_any_2_tdata2[24] == lsu_match_data_2[24]; // @[el2_lib.scala 244:78] + wire _T_755 = _T_751 | _T_754; // @[el2_lib.scala 244:23] + wire _T_757 = &io_trigger_pkt_any_2_tdata2[24:0]; // @[el2_lib.scala 244:36] + wire _T_758 = _T_757 & _T_583; // @[el2_lib.scala 244:41] + wire _T_761 = io_trigger_pkt_any_2_tdata2[25] == lsu_match_data_2[25]; // @[el2_lib.scala 244:78] + wire _T_762 = _T_758 | _T_761; // @[el2_lib.scala 244:23] + wire _T_764 = &io_trigger_pkt_any_2_tdata2[25:0]; // @[el2_lib.scala 244:36] + wire _T_765 = _T_764 & _T_583; // @[el2_lib.scala 244:41] + wire _T_768 = io_trigger_pkt_any_2_tdata2[26] == lsu_match_data_2[26]; // @[el2_lib.scala 244:78] + wire _T_769 = _T_765 | _T_768; // @[el2_lib.scala 244:23] + wire _T_771 = &io_trigger_pkt_any_2_tdata2[26:0]; // @[el2_lib.scala 244:36] + wire _T_772 = _T_771 & _T_583; // @[el2_lib.scala 244:41] + wire _T_775 = io_trigger_pkt_any_2_tdata2[27] == lsu_match_data_2[27]; // @[el2_lib.scala 244:78] + wire _T_776 = _T_772 | _T_775; // @[el2_lib.scala 244:23] + wire _T_778 = &io_trigger_pkt_any_2_tdata2[27:0]; // @[el2_lib.scala 244:36] + wire _T_779 = _T_778 & _T_583; // @[el2_lib.scala 244:41] + wire _T_782 = io_trigger_pkt_any_2_tdata2[28] == lsu_match_data_2[28]; // @[el2_lib.scala 244:78] + wire _T_783 = _T_779 | _T_782; // @[el2_lib.scala 244:23] + wire _T_785 = &io_trigger_pkt_any_2_tdata2[28:0]; // @[el2_lib.scala 244:36] + wire _T_786 = _T_785 & _T_583; // @[el2_lib.scala 244:41] + wire _T_789 = io_trigger_pkt_any_2_tdata2[29] == lsu_match_data_2[29]; // @[el2_lib.scala 244:78] + wire _T_790 = _T_786 | _T_789; // @[el2_lib.scala 244:23] + wire _T_792 = &io_trigger_pkt_any_2_tdata2[29:0]; // @[el2_lib.scala 244:36] + wire _T_793 = _T_792 & _T_583; // @[el2_lib.scala 244:41] + wire _T_796 = io_trigger_pkt_any_2_tdata2[30] == lsu_match_data_2[30]; // @[el2_lib.scala 244:78] + wire _T_797 = _T_793 | _T_796; // @[el2_lib.scala 244:23] + wire _T_799 = &io_trigger_pkt_any_2_tdata2[30:0]; // @[el2_lib.scala 244:36] + wire _T_800 = _T_799 & _T_583; // @[el2_lib.scala 244:41] + wire _T_803 = io_trigger_pkt_any_2_tdata2[31] == lsu_match_data_2[31]; // @[el2_lib.scala 244:78] + wire _T_804 = _T_800 | _T_803; // @[el2_lib.scala 244:23] + wire [7:0] _T_811 = {_T_636,_T_629,_T_622,_T_615,_T_608,_T_601,_T_594,_T_587}; // @[el2_lib.scala 245:14] + wire [15:0] _T_819 = {_T_692,_T_685,_T_678,_T_671,_T_664,_T_657,_T_650,_T_643,_T_811}; // @[el2_lib.scala 245:14] + wire [7:0] _T_826 = {_T_748,_T_741,_T_734,_T_727,_T_720,_T_713,_T_706,_T_699}; // @[el2_lib.scala 245:14] + wire [31:0] _T_835 = {_T_804,_T_797,_T_790,_T_783,_T_776,_T_769,_T_762,_T_755,_T_826,_T_819}; // @[el2_lib.scala 245:14] + wire [31:0] _GEN_2 = {{31'd0}, _T_578}; // @[el2_lsu_trigger.scala 19:92] + wire [31:0] _T_836 = _GEN_2 & _T_835; // @[el2_lsu_trigger.scala 19:92] + wire _T_839 = io_trigger_pkt_any_3_store & io_lsu_pkt_m_bits_store; // @[el2_lsu_trigger.scala 18:126] + wire _T_840 = io_trigger_pkt_any_3_load & io_lsu_pkt_m_bits_load; // @[el2_lsu_trigger.scala 19:33] + wire _T_842 = _T_840 & _T_33; // @[el2_lsu_trigger.scala 19:58] + wire _T_843 = _T_839 | _T_842; // @[el2_lsu_trigger.scala 18:152] + wire _T_844 = _T_40 & _T_843; // @[el2_lsu_trigger.scala 18:94] + wire _T_847 = &io_trigger_pkt_any_3_tdata2; // @[el2_lib.scala 241:45] + wire _T_848 = ~_T_847; // @[el2_lib.scala 241:39] + wire _T_849 = io_trigger_pkt_any_3_match_pkt & _T_848; // @[el2_lib.scala 241:37] + wire _T_852 = io_trigger_pkt_any_3_tdata2[0] == lsu_match_data_3[0]; // @[el2_lib.scala 242:52] + wire _T_853 = _T_849 | _T_852; // @[el2_lib.scala 242:41] + wire _T_855 = &io_trigger_pkt_any_3_tdata2[0]; // @[el2_lib.scala 244:36] + wire _T_856 = _T_855 & _T_849; // @[el2_lib.scala 244:41] + wire _T_859 = io_trigger_pkt_any_3_tdata2[1] == lsu_match_data_3[1]; // @[el2_lib.scala 244:78] + wire _T_860 = _T_856 | _T_859; // @[el2_lib.scala 244:23] + wire _T_862 = &io_trigger_pkt_any_3_tdata2[1:0]; // @[el2_lib.scala 244:36] + wire _T_863 = _T_862 & _T_849; // @[el2_lib.scala 244:41] + wire _T_866 = io_trigger_pkt_any_3_tdata2[2] == lsu_match_data_3[2]; // @[el2_lib.scala 244:78] + wire _T_867 = _T_863 | _T_866; // @[el2_lib.scala 244:23] + wire _T_869 = &io_trigger_pkt_any_3_tdata2[2:0]; // @[el2_lib.scala 244:36] + wire _T_870 = _T_869 & _T_849; // @[el2_lib.scala 244:41] + wire _T_873 = io_trigger_pkt_any_3_tdata2[3] == lsu_match_data_3[3]; // @[el2_lib.scala 244:78] + wire _T_874 = _T_870 | _T_873; // @[el2_lib.scala 244:23] + wire _T_876 = &io_trigger_pkt_any_3_tdata2[3:0]; // @[el2_lib.scala 244:36] + wire _T_877 = _T_876 & _T_849; // @[el2_lib.scala 244:41] + wire _T_880 = io_trigger_pkt_any_3_tdata2[4] == lsu_match_data_3[4]; // @[el2_lib.scala 244:78] + wire _T_881 = _T_877 | _T_880; // @[el2_lib.scala 244:23] + wire _T_883 = &io_trigger_pkt_any_3_tdata2[4:0]; // @[el2_lib.scala 244:36] + wire _T_884 = _T_883 & _T_849; // @[el2_lib.scala 244:41] + wire _T_887 = io_trigger_pkt_any_3_tdata2[5] == lsu_match_data_3[5]; // @[el2_lib.scala 244:78] + wire _T_888 = _T_884 | _T_887; // @[el2_lib.scala 244:23] + wire _T_890 = &io_trigger_pkt_any_3_tdata2[5:0]; // @[el2_lib.scala 244:36] + wire _T_891 = _T_890 & _T_849; // @[el2_lib.scala 244:41] + wire _T_894 = io_trigger_pkt_any_3_tdata2[6] == lsu_match_data_3[6]; // @[el2_lib.scala 244:78] + wire _T_895 = _T_891 | _T_894; // @[el2_lib.scala 244:23] + wire _T_897 = &io_trigger_pkt_any_3_tdata2[6:0]; // @[el2_lib.scala 244:36] + wire _T_898 = _T_897 & _T_849; // @[el2_lib.scala 244:41] + wire _T_901 = io_trigger_pkt_any_3_tdata2[7] == lsu_match_data_3[7]; // @[el2_lib.scala 244:78] + wire _T_902 = _T_898 | _T_901; // @[el2_lib.scala 244:23] + wire _T_904 = &io_trigger_pkt_any_3_tdata2[7:0]; // @[el2_lib.scala 244:36] + wire _T_905 = _T_904 & _T_849; // @[el2_lib.scala 244:41] + wire _T_908 = io_trigger_pkt_any_3_tdata2[8] == lsu_match_data_3[8]; // @[el2_lib.scala 244:78] + wire _T_909 = _T_905 | _T_908; // @[el2_lib.scala 244:23] + wire _T_911 = &io_trigger_pkt_any_3_tdata2[8:0]; // @[el2_lib.scala 244:36] + wire _T_912 = _T_911 & _T_849; // @[el2_lib.scala 244:41] + wire _T_915 = io_trigger_pkt_any_3_tdata2[9] == lsu_match_data_3[9]; // @[el2_lib.scala 244:78] + wire _T_916 = _T_912 | _T_915; // @[el2_lib.scala 244:23] + wire _T_918 = &io_trigger_pkt_any_3_tdata2[9:0]; // @[el2_lib.scala 244:36] + wire _T_919 = _T_918 & _T_849; // @[el2_lib.scala 244:41] + wire _T_922 = io_trigger_pkt_any_3_tdata2[10] == lsu_match_data_3[10]; // @[el2_lib.scala 244:78] + wire _T_923 = _T_919 | _T_922; // @[el2_lib.scala 244:23] + wire _T_925 = &io_trigger_pkt_any_3_tdata2[10:0]; // @[el2_lib.scala 244:36] + wire _T_926 = _T_925 & _T_849; // @[el2_lib.scala 244:41] + wire _T_929 = io_trigger_pkt_any_3_tdata2[11] == lsu_match_data_3[11]; // @[el2_lib.scala 244:78] + wire _T_930 = _T_926 | _T_929; // @[el2_lib.scala 244:23] + wire _T_932 = &io_trigger_pkt_any_3_tdata2[11:0]; // @[el2_lib.scala 244:36] + wire _T_933 = _T_932 & _T_849; // @[el2_lib.scala 244:41] + wire _T_936 = io_trigger_pkt_any_3_tdata2[12] == lsu_match_data_3[12]; // @[el2_lib.scala 244:78] + wire _T_937 = _T_933 | _T_936; // @[el2_lib.scala 244:23] + wire _T_939 = &io_trigger_pkt_any_3_tdata2[12:0]; // @[el2_lib.scala 244:36] + wire _T_940 = _T_939 & _T_849; // @[el2_lib.scala 244:41] + wire _T_943 = io_trigger_pkt_any_3_tdata2[13] == lsu_match_data_3[13]; // @[el2_lib.scala 244:78] + wire _T_944 = _T_940 | _T_943; // @[el2_lib.scala 244:23] + wire _T_946 = &io_trigger_pkt_any_3_tdata2[13:0]; // @[el2_lib.scala 244:36] + wire _T_947 = _T_946 & _T_849; // @[el2_lib.scala 244:41] + wire _T_950 = io_trigger_pkt_any_3_tdata2[14] == lsu_match_data_3[14]; // @[el2_lib.scala 244:78] + wire _T_951 = _T_947 | _T_950; // @[el2_lib.scala 244:23] + wire _T_953 = &io_trigger_pkt_any_3_tdata2[14:0]; // @[el2_lib.scala 244:36] + wire _T_954 = _T_953 & _T_849; // @[el2_lib.scala 244:41] + wire _T_957 = io_trigger_pkt_any_3_tdata2[15] == lsu_match_data_3[15]; // @[el2_lib.scala 244:78] + wire _T_958 = _T_954 | _T_957; // @[el2_lib.scala 244:23] + wire _T_960 = &io_trigger_pkt_any_3_tdata2[15:0]; // @[el2_lib.scala 244:36] + wire _T_961 = _T_960 & _T_849; // @[el2_lib.scala 244:41] + wire _T_964 = io_trigger_pkt_any_3_tdata2[16] == lsu_match_data_3[16]; // @[el2_lib.scala 244:78] + wire _T_965 = _T_961 | _T_964; // @[el2_lib.scala 244:23] + wire _T_967 = &io_trigger_pkt_any_3_tdata2[16:0]; // @[el2_lib.scala 244:36] + wire _T_968 = _T_967 & _T_849; // @[el2_lib.scala 244:41] + wire _T_971 = io_trigger_pkt_any_3_tdata2[17] == lsu_match_data_3[17]; // @[el2_lib.scala 244:78] + wire _T_972 = _T_968 | _T_971; // @[el2_lib.scala 244:23] + wire _T_974 = &io_trigger_pkt_any_3_tdata2[17:0]; // @[el2_lib.scala 244:36] + wire _T_975 = _T_974 & _T_849; // @[el2_lib.scala 244:41] + wire _T_978 = io_trigger_pkt_any_3_tdata2[18] == lsu_match_data_3[18]; // @[el2_lib.scala 244:78] + wire _T_979 = _T_975 | _T_978; // @[el2_lib.scala 244:23] + wire _T_981 = &io_trigger_pkt_any_3_tdata2[18:0]; // @[el2_lib.scala 244:36] + wire _T_982 = _T_981 & _T_849; // @[el2_lib.scala 244:41] + wire _T_985 = io_trigger_pkt_any_3_tdata2[19] == lsu_match_data_3[19]; // @[el2_lib.scala 244:78] + wire _T_986 = _T_982 | _T_985; // @[el2_lib.scala 244:23] + wire _T_988 = &io_trigger_pkt_any_3_tdata2[19:0]; // @[el2_lib.scala 244:36] + wire _T_989 = _T_988 & _T_849; // @[el2_lib.scala 244:41] + wire _T_992 = io_trigger_pkt_any_3_tdata2[20] == lsu_match_data_3[20]; // @[el2_lib.scala 244:78] + wire _T_993 = _T_989 | _T_992; // @[el2_lib.scala 244:23] + wire _T_995 = &io_trigger_pkt_any_3_tdata2[20:0]; // @[el2_lib.scala 244:36] + wire _T_996 = _T_995 & _T_849; // @[el2_lib.scala 244:41] + wire _T_999 = io_trigger_pkt_any_3_tdata2[21] == lsu_match_data_3[21]; // @[el2_lib.scala 244:78] + wire _T_1000 = _T_996 | _T_999; // @[el2_lib.scala 244:23] + wire _T_1002 = &io_trigger_pkt_any_3_tdata2[21:0]; // @[el2_lib.scala 244:36] + wire _T_1003 = _T_1002 & _T_849; // @[el2_lib.scala 244:41] + wire _T_1006 = io_trigger_pkt_any_3_tdata2[22] == lsu_match_data_3[22]; // @[el2_lib.scala 244:78] + wire _T_1007 = _T_1003 | _T_1006; // @[el2_lib.scala 244:23] + wire _T_1009 = &io_trigger_pkt_any_3_tdata2[22:0]; // @[el2_lib.scala 244:36] + wire _T_1010 = _T_1009 & _T_849; // @[el2_lib.scala 244:41] + wire _T_1013 = io_trigger_pkt_any_3_tdata2[23] == lsu_match_data_3[23]; // @[el2_lib.scala 244:78] + wire _T_1014 = _T_1010 | _T_1013; // @[el2_lib.scala 244:23] + wire _T_1016 = &io_trigger_pkt_any_3_tdata2[23:0]; // @[el2_lib.scala 244:36] + wire _T_1017 = _T_1016 & _T_849; // @[el2_lib.scala 244:41] + wire _T_1020 = io_trigger_pkt_any_3_tdata2[24] == lsu_match_data_3[24]; // @[el2_lib.scala 244:78] + wire _T_1021 = _T_1017 | _T_1020; // @[el2_lib.scala 244:23] + wire _T_1023 = &io_trigger_pkt_any_3_tdata2[24:0]; // @[el2_lib.scala 244:36] + wire _T_1024 = _T_1023 & _T_849; // @[el2_lib.scala 244:41] + wire _T_1027 = io_trigger_pkt_any_3_tdata2[25] == lsu_match_data_3[25]; // @[el2_lib.scala 244:78] + wire _T_1028 = _T_1024 | _T_1027; // @[el2_lib.scala 244:23] + wire _T_1030 = &io_trigger_pkt_any_3_tdata2[25:0]; // @[el2_lib.scala 244:36] + wire _T_1031 = _T_1030 & _T_849; // @[el2_lib.scala 244:41] + wire _T_1034 = io_trigger_pkt_any_3_tdata2[26] == lsu_match_data_3[26]; // @[el2_lib.scala 244:78] + wire _T_1035 = _T_1031 | _T_1034; // @[el2_lib.scala 244:23] + wire _T_1037 = &io_trigger_pkt_any_3_tdata2[26:0]; // @[el2_lib.scala 244:36] + wire _T_1038 = _T_1037 & _T_849; // @[el2_lib.scala 244:41] + wire _T_1041 = io_trigger_pkt_any_3_tdata2[27] == lsu_match_data_3[27]; // @[el2_lib.scala 244:78] + wire _T_1042 = _T_1038 | _T_1041; // @[el2_lib.scala 244:23] + wire _T_1044 = &io_trigger_pkt_any_3_tdata2[27:0]; // @[el2_lib.scala 244:36] + wire _T_1045 = _T_1044 & _T_849; // @[el2_lib.scala 244:41] + wire _T_1048 = io_trigger_pkt_any_3_tdata2[28] == lsu_match_data_3[28]; // @[el2_lib.scala 244:78] + wire _T_1049 = _T_1045 | _T_1048; // @[el2_lib.scala 244:23] + wire _T_1051 = &io_trigger_pkt_any_3_tdata2[28:0]; // @[el2_lib.scala 244:36] + wire _T_1052 = _T_1051 & _T_849; // @[el2_lib.scala 244:41] + wire _T_1055 = io_trigger_pkt_any_3_tdata2[29] == lsu_match_data_3[29]; // @[el2_lib.scala 244:78] + wire _T_1056 = _T_1052 | _T_1055; // @[el2_lib.scala 244:23] + wire _T_1058 = &io_trigger_pkt_any_3_tdata2[29:0]; // @[el2_lib.scala 244:36] + wire _T_1059 = _T_1058 & _T_849; // @[el2_lib.scala 244:41] + wire _T_1062 = io_trigger_pkt_any_3_tdata2[30] == lsu_match_data_3[30]; // @[el2_lib.scala 244:78] + wire _T_1063 = _T_1059 | _T_1062; // @[el2_lib.scala 244:23] + wire _T_1065 = &io_trigger_pkt_any_3_tdata2[30:0]; // @[el2_lib.scala 244:36] + wire _T_1066 = _T_1065 & _T_849; // @[el2_lib.scala 244:41] + wire _T_1069 = io_trigger_pkt_any_3_tdata2[31] == lsu_match_data_3[31]; // @[el2_lib.scala 244:78] + wire _T_1070 = _T_1066 | _T_1069; // @[el2_lib.scala 244:23] + wire [7:0] _T_1077 = {_T_902,_T_895,_T_888,_T_881,_T_874,_T_867,_T_860,_T_853}; // @[el2_lib.scala 245:14] + wire [15:0] _T_1085 = {_T_958,_T_951,_T_944,_T_937,_T_930,_T_923,_T_916,_T_909,_T_1077}; // @[el2_lib.scala 245:14] + wire [7:0] _T_1092 = {_T_1014,_T_1007,_T_1000,_T_993,_T_986,_T_979,_T_972,_T_965}; // @[el2_lib.scala 245:14] + wire [31:0] _T_1101 = {_T_1070,_T_1063,_T_1056,_T_1049,_T_1042,_T_1035,_T_1028,_T_1021,_T_1092,_T_1085}; // @[el2_lib.scala 245:14] + wire [31:0] _GEN_3 = {{31'd0}, _T_844}; // @[el2_lsu_trigger.scala 19:92] + wire [31:0] _T_1102 = _GEN_3 & _T_1101; // @[el2_lsu_trigger.scala 19:92] + wire [127:0] _T_1105 = {_T_1102,_T_836,_T_570,_T_304}; // @[Cat.scala 29:58] + assign io_lsu_trigger_match_m = _T_1105[3:0]; // @[el2_lsu_trigger.scala 18:26] endmodule diff --git a/el2_pic_ctrl.fir b/el2_pic_ctrl.fir index bd132cfd..d9540ba8 100644 --- a/el2_pic_ctrl.fir +++ b/el2_pic_ctrl.fir @@ -131,113 +131,113 @@ circuit el2_pic_ctrl : intpend_rd_out <= UInt<32>("h00") wire intenable_rd_out : UInt<1> intenable_rd_out <= UInt<1>("h00") - wire intpriority_reg_inv : UInt<4>[32] @[el2_pic_ctl.scala 81:42] + wire intpriority_reg_inv : UInt<4>[32] @[el2_pic_ctl.scala 73:42] wire intpend_reg_extended : UInt<64> intpend_reg_extended <= UInt<64>("h00") wire selected_int_priority : UInt<4> selected_int_priority <= UInt<4>("h00") - wire intpend_w_prior_en : UInt<4>[32] @[el2_pic_ctl.scala 84:42] - wire intpend_id : UInt<8>[32] @[el2_pic_ctl.scala 85:42] - wire levelx_intpend_w_prior_en : UInt<4>[10][4] @[el2_pic_ctl.scala 86:42] - levelx_intpend_w_prior_en[0][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] - levelx_intpend_w_prior_en[0][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] - levelx_intpend_w_prior_en[0][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] - levelx_intpend_w_prior_en[0][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] - levelx_intpend_w_prior_en[0][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] - levelx_intpend_w_prior_en[0][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] - levelx_intpend_w_prior_en[0][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] - levelx_intpend_w_prior_en[0][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] - levelx_intpend_w_prior_en[0][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] - levelx_intpend_w_prior_en[0][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] - levelx_intpend_w_prior_en[1][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] - levelx_intpend_w_prior_en[1][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] - levelx_intpend_w_prior_en[1][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] - levelx_intpend_w_prior_en[1][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] - levelx_intpend_w_prior_en[1][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] - levelx_intpend_w_prior_en[1][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] - levelx_intpend_w_prior_en[1][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] - levelx_intpend_w_prior_en[1][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] - levelx_intpend_w_prior_en[1][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] - levelx_intpend_w_prior_en[1][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] - levelx_intpend_w_prior_en[2][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] - levelx_intpend_w_prior_en[2][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] - levelx_intpend_w_prior_en[2][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] - levelx_intpend_w_prior_en[2][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] - levelx_intpend_w_prior_en[2][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] - levelx_intpend_w_prior_en[2][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] - levelx_intpend_w_prior_en[2][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] - levelx_intpend_w_prior_en[2][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] - levelx_intpend_w_prior_en[2][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] - levelx_intpend_w_prior_en[2][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] - levelx_intpend_w_prior_en[3][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] - levelx_intpend_w_prior_en[3][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] - levelx_intpend_w_prior_en[3][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] - levelx_intpend_w_prior_en[3][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] - levelx_intpend_w_prior_en[3][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] - levelx_intpend_w_prior_en[3][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] - levelx_intpend_w_prior_en[3][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] - levelx_intpend_w_prior_en[3][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] - levelx_intpend_w_prior_en[3][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] - levelx_intpend_w_prior_en[3][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] - wire levelx_intpend_id : UInt<8>[10][4] @[el2_pic_ctl.scala 88:42] - levelx_intpend_id[0][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] - levelx_intpend_id[0][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] - levelx_intpend_id[0][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] - levelx_intpend_id[0][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] - levelx_intpend_id[0][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] - levelx_intpend_id[0][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] - levelx_intpend_id[0][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] - levelx_intpend_id[0][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] - levelx_intpend_id[0][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] - levelx_intpend_id[0][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] - levelx_intpend_id[1][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] - levelx_intpend_id[1][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] - levelx_intpend_id[1][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] - levelx_intpend_id[1][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] - levelx_intpend_id[1][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] - levelx_intpend_id[1][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] - levelx_intpend_id[1][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] - levelx_intpend_id[1][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] - levelx_intpend_id[1][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] - levelx_intpend_id[1][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] - levelx_intpend_id[2][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] - levelx_intpend_id[2][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] - levelx_intpend_id[2][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] - levelx_intpend_id[2][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] - levelx_intpend_id[2][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] - levelx_intpend_id[2][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] - levelx_intpend_id[2][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] - levelx_intpend_id[2][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] - levelx_intpend_id[2][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] - levelx_intpend_id[2][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] - levelx_intpend_id[3][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] - levelx_intpend_id[3][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] - levelx_intpend_id[3][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] - levelx_intpend_id[3][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] - levelx_intpend_id[3][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] - levelx_intpend_id[3][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] - levelx_intpend_id[3][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] - levelx_intpend_id[3][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] - levelx_intpend_id[3][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] - levelx_intpend_id[3][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] - wire l2_intpend_w_prior_en_ff : UInt<4>[8] @[el2_pic_ctl.scala 90:42] - l2_intpend_w_prior_en_ff[0] <= UInt<1>("h00") @[el2_pic_ctl.scala 91:109] - l2_intpend_w_prior_en_ff[1] <= UInt<1>("h00") @[el2_pic_ctl.scala 91:109] - l2_intpend_w_prior_en_ff[2] <= UInt<1>("h00") @[el2_pic_ctl.scala 91:109] - l2_intpend_w_prior_en_ff[3] <= UInt<1>("h00") @[el2_pic_ctl.scala 91:109] - l2_intpend_w_prior_en_ff[4] <= UInt<1>("h00") @[el2_pic_ctl.scala 91:109] - l2_intpend_w_prior_en_ff[5] <= UInt<1>("h00") @[el2_pic_ctl.scala 91:109] - l2_intpend_w_prior_en_ff[6] <= UInt<1>("h00") @[el2_pic_ctl.scala 91:109] - l2_intpend_w_prior_en_ff[7] <= UInt<1>("h00") @[el2_pic_ctl.scala 91:109] - wire l2_intpend_id_ff : UInt<8>[8] @[el2_pic_ctl.scala 92:42] - l2_intpend_id_ff[0] <= UInt<1>("h00") @[el2_pic_ctl.scala 93:101] - l2_intpend_id_ff[1] <= UInt<1>("h00") @[el2_pic_ctl.scala 93:101] - l2_intpend_id_ff[2] <= UInt<1>("h00") @[el2_pic_ctl.scala 93:101] - l2_intpend_id_ff[3] <= UInt<1>("h00") @[el2_pic_ctl.scala 93:101] - l2_intpend_id_ff[4] <= UInt<1>("h00") @[el2_pic_ctl.scala 93:101] - l2_intpend_id_ff[5] <= UInt<1>("h00") @[el2_pic_ctl.scala 93:101] - l2_intpend_id_ff[6] <= UInt<1>("h00") @[el2_pic_ctl.scala 93:101] - l2_intpend_id_ff[7] <= UInt<1>("h00") @[el2_pic_ctl.scala 93:101] + wire intpend_w_prior_en : UInt<4>[32] @[el2_pic_ctl.scala 76:42] + wire intpend_id : UInt<8>[32] @[el2_pic_ctl.scala 77:42] + wire levelx_intpend_w_prior_en : UInt<4>[10][4] @[el2_pic_ctl.scala 78:42] + levelx_intpend_w_prior_en[0][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 79:158] + levelx_intpend_w_prior_en[0][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 79:158] + levelx_intpend_w_prior_en[0][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 79:158] + levelx_intpend_w_prior_en[0][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 79:158] + levelx_intpend_w_prior_en[0][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 79:158] + levelx_intpend_w_prior_en[0][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 79:158] + levelx_intpend_w_prior_en[0][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 79:158] + levelx_intpend_w_prior_en[0][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 79:158] + levelx_intpend_w_prior_en[0][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 79:158] + levelx_intpend_w_prior_en[0][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 79:158] + levelx_intpend_w_prior_en[1][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 79:158] + levelx_intpend_w_prior_en[1][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 79:158] + levelx_intpend_w_prior_en[1][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 79:158] + levelx_intpend_w_prior_en[1][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 79:158] + levelx_intpend_w_prior_en[1][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 79:158] + levelx_intpend_w_prior_en[1][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 79:158] + levelx_intpend_w_prior_en[1][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 79:158] + levelx_intpend_w_prior_en[1][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 79:158] + levelx_intpend_w_prior_en[1][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 79:158] + levelx_intpend_w_prior_en[1][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 79:158] + levelx_intpend_w_prior_en[2][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 79:158] + levelx_intpend_w_prior_en[2][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 79:158] + levelx_intpend_w_prior_en[2][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 79:158] + levelx_intpend_w_prior_en[2][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 79:158] + levelx_intpend_w_prior_en[2][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 79:158] + levelx_intpend_w_prior_en[2][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 79:158] + levelx_intpend_w_prior_en[2][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 79:158] + levelx_intpend_w_prior_en[2][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 79:158] + levelx_intpend_w_prior_en[2][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 79:158] + levelx_intpend_w_prior_en[2][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 79:158] + levelx_intpend_w_prior_en[3][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 79:158] + levelx_intpend_w_prior_en[3][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 79:158] + levelx_intpend_w_prior_en[3][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 79:158] + levelx_intpend_w_prior_en[3][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 79:158] + levelx_intpend_w_prior_en[3][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 79:158] + levelx_intpend_w_prior_en[3][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 79:158] + levelx_intpend_w_prior_en[3][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 79:158] + levelx_intpend_w_prior_en[3][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 79:158] + levelx_intpend_w_prior_en[3][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 79:158] + levelx_intpend_w_prior_en[3][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 79:158] + wire levelx_intpend_id : UInt<8>[10][4] @[el2_pic_ctl.scala 80:42] + levelx_intpend_id[0][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 81:150] + levelx_intpend_id[0][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 81:150] + levelx_intpend_id[0][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 81:150] + levelx_intpend_id[0][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 81:150] + levelx_intpend_id[0][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 81:150] + levelx_intpend_id[0][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 81:150] + levelx_intpend_id[0][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 81:150] + levelx_intpend_id[0][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 81:150] + levelx_intpend_id[0][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 81:150] + levelx_intpend_id[0][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 81:150] + levelx_intpend_id[1][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 81:150] + levelx_intpend_id[1][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 81:150] + levelx_intpend_id[1][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 81:150] + levelx_intpend_id[1][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 81:150] + levelx_intpend_id[1][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 81:150] + levelx_intpend_id[1][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 81:150] + levelx_intpend_id[1][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 81:150] + levelx_intpend_id[1][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 81:150] + levelx_intpend_id[1][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 81:150] + levelx_intpend_id[1][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 81:150] + levelx_intpend_id[2][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 81:150] + levelx_intpend_id[2][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 81:150] + levelx_intpend_id[2][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 81:150] + levelx_intpend_id[2][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 81:150] + levelx_intpend_id[2][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 81:150] + levelx_intpend_id[2][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 81:150] + levelx_intpend_id[2][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 81:150] + levelx_intpend_id[2][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 81:150] + levelx_intpend_id[2][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 81:150] + levelx_intpend_id[2][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 81:150] + levelx_intpend_id[3][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 81:150] + levelx_intpend_id[3][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 81:150] + levelx_intpend_id[3][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 81:150] + levelx_intpend_id[3][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 81:150] + levelx_intpend_id[3][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 81:150] + levelx_intpend_id[3][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 81:150] + levelx_intpend_id[3][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 81:150] + levelx_intpend_id[3][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 81:150] + levelx_intpend_id[3][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 81:150] + levelx_intpend_id[3][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 81:150] + wire l2_intpend_w_prior_en_ff : UInt<4>[8] @[el2_pic_ctl.scala 82:42] + l2_intpend_w_prior_en_ff[0] <= UInt<1>("h00") @[el2_pic_ctl.scala 83:109] + l2_intpend_w_prior_en_ff[1] <= UInt<1>("h00") @[el2_pic_ctl.scala 83:109] + l2_intpend_w_prior_en_ff[2] <= UInt<1>("h00") @[el2_pic_ctl.scala 83:109] + l2_intpend_w_prior_en_ff[3] <= UInt<1>("h00") @[el2_pic_ctl.scala 83:109] + l2_intpend_w_prior_en_ff[4] <= UInt<1>("h00") @[el2_pic_ctl.scala 83:109] + l2_intpend_w_prior_en_ff[5] <= UInt<1>("h00") @[el2_pic_ctl.scala 83:109] + l2_intpend_w_prior_en_ff[6] <= UInt<1>("h00") @[el2_pic_ctl.scala 83:109] + l2_intpend_w_prior_en_ff[7] <= UInt<1>("h00") @[el2_pic_ctl.scala 83:109] + wire l2_intpend_id_ff : UInt<8>[8] @[el2_pic_ctl.scala 84:42] + l2_intpend_id_ff[0] <= UInt<1>("h00") @[el2_pic_ctl.scala 85:101] + l2_intpend_id_ff[1] <= UInt<1>("h00") @[el2_pic_ctl.scala 85:101] + l2_intpend_id_ff[2] <= UInt<1>("h00") @[el2_pic_ctl.scala 85:101] + l2_intpend_id_ff[3] <= UInt<1>("h00") @[el2_pic_ctl.scala 85:101] + l2_intpend_id_ff[4] <= UInt<1>("h00") @[el2_pic_ctl.scala 85:101] + l2_intpend_id_ff[5] <= UInt<1>("h00") @[el2_pic_ctl.scala 85:101] + l2_intpend_id_ff[6] <= UInt<1>("h00") @[el2_pic_ctl.scala 85:101] + l2_intpend_id_ff[7] <= UInt<1>("h00") @[el2_pic_ctl.scala 85:101] wire config_reg : UInt<1> config_reg <= UInt<1>("h00") wire intpriord : UInt<1> @@ -262,4412 +262,4196 @@ circuit el2_pic_ctrl : picm_mken_ff <= UInt<1>("h00") wire claimid_in : UInt<8> claimid_in <= UInt<8>("h00") - wire pic_raddr_c1_clk : Clock @[el2_pic_ctl.scala 109:42] - wire pic_data_c1_clk : Clock @[el2_pic_ctl.scala 110:42] - wire pic_pri_c1_clk : Clock @[el2_pic_ctl.scala 111:42] - wire pic_int_c1_clk : Clock @[el2_pic_ctl.scala 112:42] - wire gw_config_c1_clk : Clock @[el2_pic_ctl.scala 113:42] - reg _T : UInt, pic_raddr_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 115:56] - _T <= io.picm_rdaddr @[el2_pic_ctl.scala 115:56] - picm_raddr_ff <= _T @[el2_pic_ctl.scala 115:46] - reg _T_1 : UInt, pic_data_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 116:57] - _T_1 <= io.picm_wraddr @[el2_pic_ctl.scala 116:57] - picm_waddr_ff <= _T_1 @[el2_pic_ctl.scala 116:46] - reg _T_2 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 117:55] - _T_2 <= io.picm_wren @[el2_pic_ctl.scala 117:55] - picm_wren_ff <= _T_2 @[el2_pic_ctl.scala 117:45] - reg _T_3 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 118:55] - _T_3 <= io.picm_rden @[el2_pic_ctl.scala 118:55] - picm_rden_ff <= _T_3 @[el2_pic_ctl.scala 118:45] - reg _T_4 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 119:55] - _T_4 <= io.picm_mken @[el2_pic_ctl.scala 119:55] - picm_mken_ff <= _T_4 @[el2_pic_ctl.scala 119:45] - reg _T_5 : UInt, pic_data_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 120:58] - _T_5 <= io.picm_wr_data @[el2_pic_ctl.scala 120:58] - picm_wr_data_ff <= _T_5 @[el2_pic_ctl.scala 120:48] - node _T_6 = xor(picm_raddr_ff, UInt<32>("h0f00c2000")) @[el2_pic_ctl.scala 122:59] - node temp_raddr_intenable_base_match = not(_T_6) @[el2_pic_ctl.scala 122:43] - node _T_7 = bits(temp_raddr_intenable_base_match, 31, 7) @[el2_pic_ctl.scala 123:71] - node raddr_intenable_base_match = andr(_T_7) @[el2_pic_ctl.scala 123:89] - node _T_8 = bits(picm_raddr_ff, 31, 7) @[el2_pic_ctl.scala 125:53] - node raddr_intpriority_base_match = eq(_T_8, UInt<25>("h01e01800")) @[el2_pic_ctl.scala 125:71] - node _T_9 = bits(picm_raddr_ff, 31, 7) @[el2_pic_ctl.scala 126:53] - node raddr_config_gw_base_match = eq(_T_9, UInt<25>("h01e01880")) @[el2_pic_ctl.scala 126:71] - node _T_10 = bits(picm_raddr_ff, 31, 0) @[el2_pic_ctl.scala 127:53] - node raddr_config_pic_match = eq(_T_10, UInt<32>("h0f00c3000")) @[el2_pic_ctl.scala 127:71] - node _T_11 = bits(picm_raddr_ff, 31, 6) @[el2_pic_ctl.scala 128:53] - node addr_intpend_base_match = eq(_T_11, UInt<26>("h03c03040")) @[el2_pic_ctl.scala 128:71] - node _T_12 = bits(picm_waddr_ff, 31, 0) @[el2_pic_ctl.scala 130:53] - node waddr_config_pic_match = eq(_T_12, UInt<32>("h0f00c3000")) @[el2_pic_ctl.scala 130:71] - node _T_13 = bits(picm_waddr_ff, 31, 7) @[el2_pic_ctl.scala 131:53] - node addr_clear_gw_base_match = eq(_T_13, UInt<25>("h01e018a0")) @[el2_pic_ctl.scala 131:71] - node _T_14 = bits(picm_waddr_ff, 31, 7) @[el2_pic_ctl.scala 132:53] - node waddr_intpriority_base_match = eq(_T_14, UInt<25>("h01e01800")) @[el2_pic_ctl.scala 132:71] - node _T_15 = bits(picm_waddr_ff, 31, 7) @[el2_pic_ctl.scala 133:53] - node waddr_intenable_base_match = eq(_T_15, UInt<25>("h01e01840")) @[el2_pic_ctl.scala 133:71] - node _T_16 = bits(picm_waddr_ff, 31, 7) @[el2_pic_ctl.scala 134:53] - node waddr_config_gw_base_match = eq(_T_16, UInt<25>("h01e01880")) @[el2_pic_ctl.scala 134:71] - node _T_17 = and(picm_rden_ff, picm_wren_ff) @[el2_pic_ctl.scala 135:53] - node _T_18 = eq(picm_raddr_ff, picm_waddr_ff) @[el2_pic_ctl.scala 135:86] - node picm_bypass_ff = and(_T_17, _T_18) @[el2_pic_ctl.scala 135:68] - node _T_19 = or(io.picm_mken, io.picm_rden) @[el2_pic_ctl.scala 139:42] - node pic_raddr_c1_clken = or(_T_19, io.clk_override) @[el2_pic_ctl.scala 139:57] - node pic_data_c1_clken = or(io.picm_wren, io.clk_override) @[el2_pic_ctl.scala 140:42] - node _T_20 = and(waddr_intpriority_base_match, picm_wren_ff) @[el2_pic_ctl.scala 141:59] - node _T_21 = and(raddr_intpriority_base_match, picm_rden_ff) @[el2_pic_ctl.scala 141:108] - node _T_22 = or(_T_20, _T_21) @[el2_pic_ctl.scala 141:76] - node pic_pri_c1_clken = or(_T_22, io.clk_override) @[el2_pic_ctl.scala 141:124] - node _T_23 = and(waddr_intenable_base_match, picm_wren_ff) @[el2_pic_ctl.scala 142:57] - node _T_24 = and(raddr_intenable_base_match, picm_rden_ff) @[el2_pic_ctl.scala 142:104] - node _T_25 = or(_T_23, _T_24) @[el2_pic_ctl.scala 142:74] - node pic_int_c1_clken = or(_T_25, io.clk_override) @[el2_pic_ctl.scala 142:120] - node _T_26 = and(waddr_config_gw_base_match, picm_wren_ff) @[el2_pic_ctl.scala 143:59] - node _T_27 = and(raddr_config_gw_base_match, picm_rden_ff) @[el2_pic_ctl.scala 143:108] - node _T_28 = or(_T_26, _T_27) @[el2_pic_ctl.scala 143:76] - node gw_config_c1_clken = or(_T_28, io.clk_override) @[el2_pic_ctl.scala 143:124] + wire pic_raddr_c1_clk : Clock @[el2_pic_ctl.scala 101:42] + wire pic_data_c1_clk : Clock @[el2_pic_ctl.scala 102:42] + wire pic_pri_c1_clk : Clock @[el2_pic_ctl.scala 103:42] + wire pic_int_c1_clk : Clock @[el2_pic_ctl.scala 104:42] + wire gw_config_c1_clk : Clock @[el2_pic_ctl.scala 105:42] + reg _T : UInt, pic_raddr_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 107:56] + _T <= io.picm_rdaddr @[el2_pic_ctl.scala 107:56] + picm_raddr_ff <= _T @[el2_pic_ctl.scala 107:46] + reg _T_1 : UInt, pic_data_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 108:57] + _T_1 <= io.picm_wraddr @[el2_pic_ctl.scala 108:57] + picm_waddr_ff <= _T_1 @[el2_pic_ctl.scala 108:46] + reg _T_2 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 109:55] + _T_2 <= io.picm_wren @[el2_pic_ctl.scala 109:55] + picm_wren_ff <= _T_2 @[el2_pic_ctl.scala 109:45] + reg _T_3 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 110:55] + _T_3 <= io.picm_rden @[el2_pic_ctl.scala 110:55] + picm_rden_ff <= _T_3 @[el2_pic_ctl.scala 110:45] + reg _T_4 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 111:55] + _T_4 <= io.picm_mken @[el2_pic_ctl.scala 111:55] + picm_mken_ff <= _T_4 @[el2_pic_ctl.scala 111:45] + reg _T_5 : UInt, pic_data_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 112:58] + _T_5 <= io.picm_wr_data @[el2_pic_ctl.scala 112:58] + picm_wr_data_ff <= _T_5 @[el2_pic_ctl.scala 112:48] + node _T_6 = xor(picm_raddr_ff, UInt<32>("h0f00c2000")) @[el2_pic_ctl.scala 114:59] + node temp_raddr_intenable_base_match = not(_T_6) @[el2_pic_ctl.scala 114:43] + node _T_7 = bits(temp_raddr_intenable_base_match, 31, 7) @[el2_pic_ctl.scala 115:71] + node raddr_intenable_base_match = andr(_T_7) @[el2_pic_ctl.scala 115:89] + node _T_8 = bits(picm_raddr_ff, 31, 7) @[el2_pic_ctl.scala 117:53] + node raddr_intpriority_base_match = eq(_T_8, UInt<25>("h01e01800")) @[el2_pic_ctl.scala 117:71] + node _T_9 = bits(picm_raddr_ff, 31, 7) @[el2_pic_ctl.scala 118:53] + node raddr_config_gw_base_match = eq(_T_9, UInt<25>("h01e01880")) @[el2_pic_ctl.scala 118:71] + node _T_10 = bits(picm_raddr_ff, 31, 0) @[el2_pic_ctl.scala 119:53] + node raddr_config_pic_match = eq(_T_10, UInt<32>("h0f00c3000")) @[el2_pic_ctl.scala 119:71] + node _T_11 = bits(picm_raddr_ff, 31, 6) @[el2_pic_ctl.scala 120:53] + node addr_intpend_base_match = eq(_T_11, UInt<26>("h03c03040")) @[el2_pic_ctl.scala 120:71] + node _T_12 = bits(picm_waddr_ff, 31, 0) @[el2_pic_ctl.scala 122:53] + node waddr_config_pic_match = eq(_T_12, UInt<32>("h0f00c3000")) @[el2_pic_ctl.scala 122:71] + node _T_13 = bits(picm_waddr_ff, 31, 7) @[el2_pic_ctl.scala 123:53] + node addr_clear_gw_base_match = eq(_T_13, UInt<25>("h01e018a0")) @[el2_pic_ctl.scala 123:71] + node _T_14 = bits(picm_waddr_ff, 31, 7) @[el2_pic_ctl.scala 124:53] + node waddr_intpriority_base_match = eq(_T_14, UInt<25>("h01e01800")) @[el2_pic_ctl.scala 124:71] + node _T_15 = bits(picm_waddr_ff, 31, 7) @[el2_pic_ctl.scala 125:53] + node waddr_intenable_base_match = eq(_T_15, UInt<25>("h01e01840")) @[el2_pic_ctl.scala 125:71] + node _T_16 = bits(picm_waddr_ff, 31, 7) @[el2_pic_ctl.scala 126:53] + node waddr_config_gw_base_match = eq(_T_16, UInt<25>("h01e01880")) @[el2_pic_ctl.scala 126:71] + node _T_17 = and(picm_rden_ff, picm_wren_ff) @[el2_pic_ctl.scala 127:53] + node _T_18 = eq(picm_raddr_ff, picm_waddr_ff) @[el2_pic_ctl.scala 127:86] + node picm_bypass_ff = and(_T_17, _T_18) @[el2_pic_ctl.scala 127:68] + node _T_19 = or(io.picm_mken, io.picm_rden) @[el2_pic_ctl.scala 131:42] + node pic_raddr_c1_clken = or(_T_19, io.clk_override) @[el2_pic_ctl.scala 131:57] + node pic_data_c1_clken = or(io.picm_wren, io.clk_override) @[el2_pic_ctl.scala 132:42] + node _T_20 = and(waddr_intpriority_base_match, picm_wren_ff) @[el2_pic_ctl.scala 133:59] + node _T_21 = and(raddr_intpriority_base_match, picm_rden_ff) @[el2_pic_ctl.scala 133:108] + node _T_22 = or(_T_20, _T_21) @[el2_pic_ctl.scala 133:76] + node pic_pri_c1_clken = or(_T_22, io.clk_override) @[el2_pic_ctl.scala 133:124] + node _T_23 = and(waddr_intenable_base_match, picm_wren_ff) @[el2_pic_ctl.scala 134:57] + node _T_24 = and(raddr_intenable_base_match, picm_rden_ff) @[el2_pic_ctl.scala 134:104] + node _T_25 = or(_T_23, _T_24) @[el2_pic_ctl.scala 134:74] + node pic_int_c1_clken = or(_T_25, io.clk_override) @[el2_pic_ctl.scala 134:120] + node _T_26 = and(waddr_config_gw_base_match, picm_wren_ff) @[el2_pic_ctl.scala 135:59] + node _T_27 = and(raddr_config_gw_base_match, picm_rden_ff) @[el2_pic_ctl.scala 135:108] + node _T_28 = or(_T_26, _T_27) @[el2_pic_ctl.scala 135:76] + node gw_config_c1_clken = or(_T_28, io.clk_override) @[el2_pic_ctl.scala 135:124] inst rvclkhdr of rvclkhdr @[el2_lib.scala 483:22] rvclkhdr.clock <= clock rvclkhdr.reset <= reset rvclkhdr.io.clk <= clock @[el2_lib.scala 484:17] rvclkhdr.io.en <= pic_raddr_c1_clken @[el2_lib.scala 485:16] rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - pic_raddr_c1_clk <= rvclkhdr.io.l1clk @[el2_pic_ctl.scala 146:21] + pic_raddr_c1_clk <= rvclkhdr.io.l1clk @[el2_pic_ctl.scala 138:21] inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 483:22] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset rvclkhdr_1.io.clk <= clock @[el2_lib.scala 484:17] rvclkhdr_1.io.en <= pic_data_c1_clken @[el2_lib.scala 485:16] rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - pic_data_c1_clk <= rvclkhdr_1.io.l1clk @[el2_pic_ctl.scala 147:21] - node _T_29 = bits(pic_pri_c1_clken, 0, 0) @[el2_pic_ctl.scala 148:56] + pic_data_c1_clk <= rvclkhdr_1.io.l1clk @[el2_pic_ctl.scala 139:21] + node _T_29 = bits(pic_pri_c1_clken, 0, 0) @[el2_pic_ctl.scala 140:56] inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 483:22] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset rvclkhdr_2.io.clk <= clock @[el2_lib.scala 484:17] rvclkhdr_2.io.en <= _T_29 @[el2_lib.scala 485:16] rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - pic_pri_c1_clk <= rvclkhdr_2.io.l1clk @[el2_pic_ctl.scala 148:21] - node _T_30 = bits(pic_int_c1_clken, 0, 0) @[el2_pic_ctl.scala 149:56] + pic_pri_c1_clk <= rvclkhdr_2.io.l1clk @[el2_pic_ctl.scala 140:21] + node _T_30 = bits(pic_int_c1_clken, 0, 0) @[el2_pic_ctl.scala 141:56] inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 483:22] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset rvclkhdr_3.io.clk <= clock @[el2_lib.scala 484:17] rvclkhdr_3.io.en <= _T_30 @[el2_lib.scala 485:16] rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - pic_int_c1_clk <= rvclkhdr_3.io.l1clk @[el2_pic_ctl.scala 149:21] - node _T_31 = bits(gw_config_c1_clken, 0, 0) @[el2_pic_ctl.scala 150:58] + pic_int_c1_clk <= rvclkhdr_3.io.l1clk @[el2_pic_ctl.scala 141:21] + node _T_31 = bits(gw_config_c1_clken, 0, 0) @[el2_pic_ctl.scala 142:58] inst rvclkhdr_4 of rvclkhdr_4 @[el2_lib.scala 483:22] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset rvclkhdr_4.io.clk <= clock @[el2_lib.scala 484:17] rvclkhdr_4.io.en <= _T_31 @[el2_lib.scala 485:16] rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - gw_config_c1_clk <= rvclkhdr_4.io.l1clk @[el2_pic_ctl.scala 150:21] - node _T_32 = bits(io.extintsrc_req, 31, 1) @[el2_pic_ctl.scala 153:58] - reg _T_33 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 176:81] - _T_33 <= _T_32 @[el2_lib.scala 176:81] - reg _T_34 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 176:58] - _T_34 <= _T_33 @[el2_lib.scala 176:58] - node _T_35 = bits(io.extintsrc_req, 0, 0) @[el2_pic_ctl.scala 153:113] + gw_config_c1_clk <= rvclkhdr_4.io.l1clk @[el2_pic_ctl.scala 142:21] + node _T_32 = bits(io.extintsrc_req, 31, 1) @[el2_pic_ctl.scala 145:58] + reg _T_33 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 177:81] + _T_33 <= _T_32 @[el2_lib.scala 177:81] + reg _T_34 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 177:58] + _T_34 <= _T_33 @[el2_lib.scala 177:58] + node _T_35 = bits(io.extintsrc_req, 0, 0) @[el2_pic_ctl.scala 145:113] node extintsrc_req_sync = cat(_T_34, _T_35) @[Cat.scala 29:58] - node _T_36 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] - node _T_37 = eq(_T_36, UInt<1>("h01")) @[el2_pic_ctl.scala 155:139] - node _T_38 = and(waddr_intpriority_base_match, _T_37) @[el2_pic_ctl.scala 155:106] - node intpriority_reg_we_1 = and(_T_38, picm_wren_ff) @[el2_pic_ctl.scala 155:153] - node _T_39 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] - node _T_40 = eq(_T_39, UInt<2>("h02")) @[el2_pic_ctl.scala 155:139] - node _T_41 = and(waddr_intpriority_base_match, _T_40) @[el2_pic_ctl.scala 155:106] - node intpriority_reg_we_2 = and(_T_41, picm_wren_ff) @[el2_pic_ctl.scala 155:153] - node _T_42 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] - node _T_43 = eq(_T_42, UInt<2>("h03")) @[el2_pic_ctl.scala 155:139] - node _T_44 = and(waddr_intpriority_base_match, _T_43) @[el2_pic_ctl.scala 155:106] - node intpriority_reg_we_3 = and(_T_44, picm_wren_ff) @[el2_pic_ctl.scala 155:153] - node _T_45 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] - node _T_46 = eq(_T_45, UInt<3>("h04")) @[el2_pic_ctl.scala 155:139] - node _T_47 = and(waddr_intpriority_base_match, _T_46) @[el2_pic_ctl.scala 155:106] - node intpriority_reg_we_4 = and(_T_47, picm_wren_ff) @[el2_pic_ctl.scala 155:153] - node _T_48 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] - node _T_49 = eq(_T_48, UInt<3>("h05")) @[el2_pic_ctl.scala 155:139] - node _T_50 = and(waddr_intpriority_base_match, _T_49) @[el2_pic_ctl.scala 155:106] - node intpriority_reg_we_5 = and(_T_50, picm_wren_ff) @[el2_pic_ctl.scala 155:153] - node _T_51 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] - node _T_52 = eq(_T_51, UInt<3>("h06")) @[el2_pic_ctl.scala 155:139] - node _T_53 = and(waddr_intpriority_base_match, _T_52) @[el2_pic_ctl.scala 155:106] - node intpriority_reg_we_6 = and(_T_53, picm_wren_ff) @[el2_pic_ctl.scala 155:153] - node _T_54 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] - node _T_55 = eq(_T_54, UInt<3>("h07")) @[el2_pic_ctl.scala 155:139] - node _T_56 = and(waddr_intpriority_base_match, _T_55) @[el2_pic_ctl.scala 155:106] - node intpriority_reg_we_7 = and(_T_56, picm_wren_ff) @[el2_pic_ctl.scala 155:153] - node _T_57 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] - node _T_58 = eq(_T_57, UInt<4>("h08")) @[el2_pic_ctl.scala 155:139] - node _T_59 = and(waddr_intpriority_base_match, _T_58) @[el2_pic_ctl.scala 155:106] - node intpriority_reg_we_8 = and(_T_59, picm_wren_ff) @[el2_pic_ctl.scala 155:153] - node _T_60 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] - node _T_61 = eq(_T_60, UInt<4>("h09")) @[el2_pic_ctl.scala 155:139] - node _T_62 = and(waddr_intpriority_base_match, _T_61) @[el2_pic_ctl.scala 155:106] - node intpriority_reg_we_9 = and(_T_62, picm_wren_ff) @[el2_pic_ctl.scala 155:153] - node _T_63 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] - node _T_64 = eq(_T_63, UInt<4>("h0a")) @[el2_pic_ctl.scala 155:139] - node _T_65 = and(waddr_intpriority_base_match, _T_64) @[el2_pic_ctl.scala 155:106] - node intpriority_reg_we_10 = and(_T_65, picm_wren_ff) @[el2_pic_ctl.scala 155:153] - node _T_66 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] - node _T_67 = eq(_T_66, UInt<4>("h0b")) @[el2_pic_ctl.scala 155:139] - node _T_68 = and(waddr_intpriority_base_match, _T_67) @[el2_pic_ctl.scala 155:106] - node intpriority_reg_we_11 = and(_T_68, picm_wren_ff) @[el2_pic_ctl.scala 155:153] - node _T_69 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] - node _T_70 = eq(_T_69, UInt<4>("h0c")) @[el2_pic_ctl.scala 155:139] - node _T_71 = and(waddr_intpriority_base_match, _T_70) @[el2_pic_ctl.scala 155:106] - node intpriority_reg_we_12 = and(_T_71, picm_wren_ff) @[el2_pic_ctl.scala 155:153] - node _T_72 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] - node _T_73 = eq(_T_72, UInt<4>("h0d")) @[el2_pic_ctl.scala 155:139] - node _T_74 = and(waddr_intpriority_base_match, _T_73) @[el2_pic_ctl.scala 155:106] - node intpriority_reg_we_13 = and(_T_74, picm_wren_ff) @[el2_pic_ctl.scala 155:153] - node _T_75 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] - node _T_76 = eq(_T_75, UInt<4>("h0e")) @[el2_pic_ctl.scala 155:139] - node _T_77 = and(waddr_intpriority_base_match, _T_76) @[el2_pic_ctl.scala 155:106] - node intpriority_reg_we_14 = and(_T_77, picm_wren_ff) @[el2_pic_ctl.scala 155:153] - node _T_78 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] - node _T_79 = eq(_T_78, UInt<4>("h0f")) @[el2_pic_ctl.scala 155:139] - node _T_80 = and(waddr_intpriority_base_match, _T_79) @[el2_pic_ctl.scala 155:106] - node intpriority_reg_we_15 = and(_T_80, picm_wren_ff) @[el2_pic_ctl.scala 155:153] - node _T_81 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] - node _T_82 = eq(_T_81, UInt<5>("h010")) @[el2_pic_ctl.scala 155:139] - node _T_83 = and(waddr_intpriority_base_match, _T_82) @[el2_pic_ctl.scala 155:106] - node intpriority_reg_we_16 = and(_T_83, picm_wren_ff) @[el2_pic_ctl.scala 155:153] - node _T_84 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] - node _T_85 = eq(_T_84, UInt<5>("h011")) @[el2_pic_ctl.scala 155:139] - node _T_86 = and(waddr_intpriority_base_match, _T_85) @[el2_pic_ctl.scala 155:106] - node intpriority_reg_we_17 = and(_T_86, picm_wren_ff) @[el2_pic_ctl.scala 155:153] - node _T_87 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] - node _T_88 = eq(_T_87, UInt<5>("h012")) @[el2_pic_ctl.scala 155:139] - node _T_89 = and(waddr_intpriority_base_match, _T_88) @[el2_pic_ctl.scala 155:106] - node intpriority_reg_we_18 = and(_T_89, picm_wren_ff) @[el2_pic_ctl.scala 155:153] - node _T_90 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] - node _T_91 = eq(_T_90, UInt<5>("h013")) @[el2_pic_ctl.scala 155:139] - node _T_92 = and(waddr_intpriority_base_match, _T_91) @[el2_pic_ctl.scala 155:106] - node intpriority_reg_we_19 = and(_T_92, picm_wren_ff) @[el2_pic_ctl.scala 155:153] - node _T_93 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] - node _T_94 = eq(_T_93, UInt<5>("h014")) @[el2_pic_ctl.scala 155:139] - node _T_95 = and(waddr_intpriority_base_match, _T_94) @[el2_pic_ctl.scala 155:106] - node intpriority_reg_we_20 = and(_T_95, picm_wren_ff) @[el2_pic_ctl.scala 155:153] - node _T_96 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] - node _T_97 = eq(_T_96, UInt<5>("h015")) @[el2_pic_ctl.scala 155:139] - node _T_98 = and(waddr_intpriority_base_match, _T_97) @[el2_pic_ctl.scala 155:106] - node intpriority_reg_we_21 = and(_T_98, picm_wren_ff) @[el2_pic_ctl.scala 155:153] - node _T_99 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] - node _T_100 = eq(_T_99, UInt<5>("h016")) @[el2_pic_ctl.scala 155:139] - node _T_101 = and(waddr_intpriority_base_match, _T_100) @[el2_pic_ctl.scala 155:106] - node intpriority_reg_we_22 = and(_T_101, picm_wren_ff) @[el2_pic_ctl.scala 155:153] - node _T_102 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] - node _T_103 = eq(_T_102, UInt<5>("h017")) @[el2_pic_ctl.scala 155:139] - node _T_104 = and(waddr_intpriority_base_match, _T_103) @[el2_pic_ctl.scala 155:106] - node intpriority_reg_we_23 = and(_T_104, picm_wren_ff) @[el2_pic_ctl.scala 155:153] - node _T_105 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] - node _T_106 = eq(_T_105, UInt<5>("h018")) @[el2_pic_ctl.scala 155:139] - node _T_107 = and(waddr_intpriority_base_match, _T_106) @[el2_pic_ctl.scala 155:106] - node intpriority_reg_we_24 = and(_T_107, picm_wren_ff) @[el2_pic_ctl.scala 155:153] - node _T_108 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] - node _T_109 = eq(_T_108, UInt<5>("h019")) @[el2_pic_ctl.scala 155:139] - node _T_110 = and(waddr_intpriority_base_match, _T_109) @[el2_pic_ctl.scala 155:106] - node intpriority_reg_we_25 = and(_T_110, picm_wren_ff) @[el2_pic_ctl.scala 155:153] - node _T_111 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] - node _T_112 = eq(_T_111, UInt<5>("h01a")) @[el2_pic_ctl.scala 155:139] - node _T_113 = and(waddr_intpriority_base_match, _T_112) @[el2_pic_ctl.scala 155:106] - node intpriority_reg_we_26 = and(_T_113, picm_wren_ff) @[el2_pic_ctl.scala 155:153] - node _T_114 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] - node _T_115 = eq(_T_114, UInt<5>("h01b")) @[el2_pic_ctl.scala 155:139] - node _T_116 = and(waddr_intpriority_base_match, _T_115) @[el2_pic_ctl.scala 155:106] - node intpriority_reg_we_27 = and(_T_116, picm_wren_ff) @[el2_pic_ctl.scala 155:153] - node _T_117 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] - node _T_118 = eq(_T_117, UInt<5>("h01c")) @[el2_pic_ctl.scala 155:139] - node _T_119 = and(waddr_intpriority_base_match, _T_118) @[el2_pic_ctl.scala 155:106] - node intpriority_reg_we_28 = and(_T_119, picm_wren_ff) @[el2_pic_ctl.scala 155:153] - node _T_120 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] - node _T_121 = eq(_T_120, UInt<5>("h01d")) @[el2_pic_ctl.scala 155:139] - node _T_122 = and(waddr_intpriority_base_match, _T_121) @[el2_pic_ctl.scala 155:106] - node intpriority_reg_we_29 = and(_T_122, picm_wren_ff) @[el2_pic_ctl.scala 155:153] - node _T_123 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] - node _T_124 = eq(_T_123, UInt<5>("h01e")) @[el2_pic_ctl.scala 155:139] - node _T_125 = and(waddr_intpriority_base_match, _T_124) @[el2_pic_ctl.scala 155:106] - node intpriority_reg_we_30 = and(_T_125, picm_wren_ff) @[el2_pic_ctl.scala 155:153] - node _T_126 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] - node _T_127 = eq(_T_126, UInt<5>("h01f")) @[el2_pic_ctl.scala 155:139] - node _T_128 = and(waddr_intpriority_base_match, _T_127) @[el2_pic_ctl.scala 155:106] - node intpriority_reg_we_31 = and(_T_128, picm_wren_ff) @[el2_pic_ctl.scala 155:153] - node _T_129 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] - node _T_130 = eq(_T_129, UInt<1>("h01")) @[el2_pic_ctl.scala 156:139] - node _T_131 = and(raddr_intpriority_base_match, _T_130) @[el2_pic_ctl.scala 156:106] - node intpriority_reg_re_1 = and(_T_131, picm_rden_ff) @[el2_pic_ctl.scala 156:153] - node _T_132 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] - node _T_133 = eq(_T_132, UInt<2>("h02")) @[el2_pic_ctl.scala 156:139] - node _T_134 = and(raddr_intpriority_base_match, _T_133) @[el2_pic_ctl.scala 156:106] - node intpriority_reg_re_2 = and(_T_134, picm_rden_ff) @[el2_pic_ctl.scala 156:153] - node _T_135 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] - node _T_136 = eq(_T_135, UInt<2>("h03")) @[el2_pic_ctl.scala 156:139] - node _T_137 = and(raddr_intpriority_base_match, _T_136) @[el2_pic_ctl.scala 156:106] - node intpriority_reg_re_3 = and(_T_137, picm_rden_ff) @[el2_pic_ctl.scala 156:153] - node _T_138 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] - node _T_139 = eq(_T_138, UInt<3>("h04")) @[el2_pic_ctl.scala 156:139] - node _T_140 = and(raddr_intpriority_base_match, _T_139) @[el2_pic_ctl.scala 156:106] - node intpriority_reg_re_4 = and(_T_140, picm_rden_ff) @[el2_pic_ctl.scala 156:153] - node _T_141 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] - node _T_142 = eq(_T_141, UInt<3>("h05")) @[el2_pic_ctl.scala 156:139] - node _T_143 = and(raddr_intpriority_base_match, _T_142) @[el2_pic_ctl.scala 156:106] - node intpriority_reg_re_5 = and(_T_143, picm_rden_ff) @[el2_pic_ctl.scala 156:153] - node _T_144 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] - node _T_145 = eq(_T_144, UInt<3>("h06")) @[el2_pic_ctl.scala 156:139] - node _T_146 = and(raddr_intpriority_base_match, _T_145) @[el2_pic_ctl.scala 156:106] - node intpriority_reg_re_6 = and(_T_146, picm_rden_ff) @[el2_pic_ctl.scala 156:153] - node _T_147 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] - node _T_148 = eq(_T_147, UInt<3>("h07")) @[el2_pic_ctl.scala 156:139] - node _T_149 = and(raddr_intpriority_base_match, _T_148) @[el2_pic_ctl.scala 156:106] - node intpriority_reg_re_7 = and(_T_149, picm_rden_ff) @[el2_pic_ctl.scala 156:153] - node _T_150 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] - node _T_151 = eq(_T_150, UInt<4>("h08")) @[el2_pic_ctl.scala 156:139] - node _T_152 = and(raddr_intpriority_base_match, _T_151) @[el2_pic_ctl.scala 156:106] - node intpriority_reg_re_8 = and(_T_152, picm_rden_ff) @[el2_pic_ctl.scala 156:153] - node _T_153 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] - node _T_154 = eq(_T_153, UInt<4>("h09")) @[el2_pic_ctl.scala 156:139] - node _T_155 = and(raddr_intpriority_base_match, _T_154) @[el2_pic_ctl.scala 156:106] - node intpriority_reg_re_9 = and(_T_155, picm_rden_ff) @[el2_pic_ctl.scala 156:153] - node _T_156 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] - node _T_157 = eq(_T_156, UInt<4>("h0a")) @[el2_pic_ctl.scala 156:139] - node _T_158 = and(raddr_intpriority_base_match, _T_157) @[el2_pic_ctl.scala 156:106] - node intpriority_reg_re_10 = and(_T_158, picm_rden_ff) @[el2_pic_ctl.scala 156:153] - node _T_159 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] - node _T_160 = eq(_T_159, UInt<4>("h0b")) @[el2_pic_ctl.scala 156:139] - node _T_161 = and(raddr_intpriority_base_match, _T_160) @[el2_pic_ctl.scala 156:106] - node intpriority_reg_re_11 = and(_T_161, picm_rden_ff) @[el2_pic_ctl.scala 156:153] - node _T_162 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] - node _T_163 = eq(_T_162, UInt<4>("h0c")) @[el2_pic_ctl.scala 156:139] - node _T_164 = and(raddr_intpriority_base_match, _T_163) @[el2_pic_ctl.scala 156:106] - node intpriority_reg_re_12 = and(_T_164, picm_rden_ff) @[el2_pic_ctl.scala 156:153] - node _T_165 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] - node _T_166 = eq(_T_165, UInt<4>("h0d")) @[el2_pic_ctl.scala 156:139] - node _T_167 = and(raddr_intpriority_base_match, _T_166) @[el2_pic_ctl.scala 156:106] - node intpriority_reg_re_13 = and(_T_167, picm_rden_ff) @[el2_pic_ctl.scala 156:153] - node _T_168 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] - node _T_169 = eq(_T_168, UInt<4>("h0e")) @[el2_pic_ctl.scala 156:139] - node _T_170 = and(raddr_intpriority_base_match, _T_169) @[el2_pic_ctl.scala 156:106] - node intpriority_reg_re_14 = and(_T_170, picm_rden_ff) @[el2_pic_ctl.scala 156:153] - node _T_171 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] - node _T_172 = eq(_T_171, UInt<4>("h0f")) @[el2_pic_ctl.scala 156:139] - node _T_173 = and(raddr_intpriority_base_match, _T_172) @[el2_pic_ctl.scala 156:106] - node intpriority_reg_re_15 = and(_T_173, picm_rden_ff) @[el2_pic_ctl.scala 156:153] - node _T_174 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] - node _T_175 = eq(_T_174, UInt<5>("h010")) @[el2_pic_ctl.scala 156:139] - node _T_176 = and(raddr_intpriority_base_match, _T_175) @[el2_pic_ctl.scala 156:106] - node intpriority_reg_re_16 = and(_T_176, picm_rden_ff) @[el2_pic_ctl.scala 156:153] - node _T_177 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] - node _T_178 = eq(_T_177, UInt<5>("h011")) @[el2_pic_ctl.scala 156:139] - node _T_179 = and(raddr_intpriority_base_match, _T_178) @[el2_pic_ctl.scala 156:106] - node intpriority_reg_re_17 = and(_T_179, picm_rden_ff) @[el2_pic_ctl.scala 156:153] - node _T_180 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] - node _T_181 = eq(_T_180, UInt<5>("h012")) @[el2_pic_ctl.scala 156:139] - node _T_182 = and(raddr_intpriority_base_match, _T_181) @[el2_pic_ctl.scala 156:106] - node intpriority_reg_re_18 = and(_T_182, picm_rden_ff) @[el2_pic_ctl.scala 156:153] - node _T_183 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] - node _T_184 = eq(_T_183, UInt<5>("h013")) @[el2_pic_ctl.scala 156:139] - node _T_185 = and(raddr_intpriority_base_match, _T_184) @[el2_pic_ctl.scala 156:106] - node intpriority_reg_re_19 = and(_T_185, picm_rden_ff) @[el2_pic_ctl.scala 156:153] - node _T_186 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] - node _T_187 = eq(_T_186, UInt<5>("h014")) @[el2_pic_ctl.scala 156:139] - node _T_188 = and(raddr_intpriority_base_match, _T_187) @[el2_pic_ctl.scala 156:106] - node intpriority_reg_re_20 = and(_T_188, picm_rden_ff) @[el2_pic_ctl.scala 156:153] - node _T_189 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] - node _T_190 = eq(_T_189, UInt<5>("h015")) @[el2_pic_ctl.scala 156:139] - node _T_191 = and(raddr_intpriority_base_match, _T_190) @[el2_pic_ctl.scala 156:106] - node intpriority_reg_re_21 = and(_T_191, picm_rden_ff) @[el2_pic_ctl.scala 156:153] - node _T_192 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] - node _T_193 = eq(_T_192, UInt<5>("h016")) @[el2_pic_ctl.scala 156:139] - node _T_194 = and(raddr_intpriority_base_match, _T_193) @[el2_pic_ctl.scala 156:106] - node intpriority_reg_re_22 = and(_T_194, picm_rden_ff) @[el2_pic_ctl.scala 156:153] - node _T_195 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] - node _T_196 = eq(_T_195, UInt<5>("h017")) @[el2_pic_ctl.scala 156:139] - node _T_197 = and(raddr_intpriority_base_match, _T_196) @[el2_pic_ctl.scala 156:106] - node intpriority_reg_re_23 = and(_T_197, picm_rden_ff) @[el2_pic_ctl.scala 156:153] - node _T_198 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] - node _T_199 = eq(_T_198, UInt<5>("h018")) @[el2_pic_ctl.scala 156:139] - node _T_200 = and(raddr_intpriority_base_match, _T_199) @[el2_pic_ctl.scala 156:106] - node intpriority_reg_re_24 = and(_T_200, picm_rden_ff) @[el2_pic_ctl.scala 156:153] - node _T_201 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] - node _T_202 = eq(_T_201, UInt<5>("h019")) @[el2_pic_ctl.scala 156:139] - node _T_203 = and(raddr_intpriority_base_match, _T_202) @[el2_pic_ctl.scala 156:106] - node intpriority_reg_re_25 = and(_T_203, picm_rden_ff) @[el2_pic_ctl.scala 156:153] - node _T_204 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] - node _T_205 = eq(_T_204, UInt<5>("h01a")) @[el2_pic_ctl.scala 156:139] - node _T_206 = and(raddr_intpriority_base_match, _T_205) @[el2_pic_ctl.scala 156:106] - node intpriority_reg_re_26 = and(_T_206, picm_rden_ff) @[el2_pic_ctl.scala 156:153] - node _T_207 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] - node _T_208 = eq(_T_207, UInt<5>("h01b")) @[el2_pic_ctl.scala 156:139] - node _T_209 = and(raddr_intpriority_base_match, _T_208) @[el2_pic_ctl.scala 156:106] - node intpriority_reg_re_27 = and(_T_209, picm_rden_ff) @[el2_pic_ctl.scala 156:153] - node _T_210 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] - node _T_211 = eq(_T_210, UInt<5>("h01c")) @[el2_pic_ctl.scala 156:139] - node _T_212 = and(raddr_intpriority_base_match, _T_211) @[el2_pic_ctl.scala 156:106] - node intpriority_reg_re_28 = and(_T_212, picm_rden_ff) @[el2_pic_ctl.scala 156:153] - node _T_213 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] - node _T_214 = eq(_T_213, UInt<5>("h01d")) @[el2_pic_ctl.scala 156:139] - node _T_215 = and(raddr_intpriority_base_match, _T_214) @[el2_pic_ctl.scala 156:106] - node intpriority_reg_re_29 = and(_T_215, picm_rden_ff) @[el2_pic_ctl.scala 156:153] - node _T_216 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] - node _T_217 = eq(_T_216, UInt<5>("h01e")) @[el2_pic_ctl.scala 156:139] - node _T_218 = and(raddr_intpriority_base_match, _T_217) @[el2_pic_ctl.scala 156:106] - node intpriority_reg_re_30 = and(_T_218, picm_rden_ff) @[el2_pic_ctl.scala 156:153] - node _T_219 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] - node _T_220 = eq(_T_219, UInt<5>("h01f")) @[el2_pic_ctl.scala 156:139] - node _T_221 = and(raddr_intpriority_base_match, _T_220) @[el2_pic_ctl.scala 156:106] - node intpriority_reg_re_31 = and(_T_221, picm_rden_ff) @[el2_pic_ctl.scala 156:153] - node _T_222 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] - node _T_223 = eq(_T_222, UInt<1>("h01")) @[el2_pic_ctl.scala 157:139] - node _T_224 = and(waddr_intenable_base_match, _T_223) @[el2_pic_ctl.scala 157:106] - node intenable_reg_we_1 = and(_T_224, picm_wren_ff) @[el2_pic_ctl.scala 157:153] - node _T_225 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] - node _T_226 = eq(_T_225, UInt<2>("h02")) @[el2_pic_ctl.scala 157:139] - node _T_227 = and(waddr_intenable_base_match, _T_226) @[el2_pic_ctl.scala 157:106] - node intenable_reg_we_2 = and(_T_227, picm_wren_ff) @[el2_pic_ctl.scala 157:153] - node _T_228 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] - node _T_229 = eq(_T_228, UInt<2>("h03")) @[el2_pic_ctl.scala 157:139] - node _T_230 = and(waddr_intenable_base_match, _T_229) @[el2_pic_ctl.scala 157:106] - node intenable_reg_we_3 = and(_T_230, picm_wren_ff) @[el2_pic_ctl.scala 157:153] - node _T_231 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] - node _T_232 = eq(_T_231, UInt<3>("h04")) @[el2_pic_ctl.scala 157:139] - node _T_233 = and(waddr_intenable_base_match, _T_232) @[el2_pic_ctl.scala 157:106] - node intenable_reg_we_4 = and(_T_233, picm_wren_ff) @[el2_pic_ctl.scala 157:153] - node _T_234 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] - node _T_235 = eq(_T_234, UInt<3>("h05")) @[el2_pic_ctl.scala 157:139] - node _T_236 = and(waddr_intenable_base_match, _T_235) @[el2_pic_ctl.scala 157:106] - node intenable_reg_we_5 = and(_T_236, picm_wren_ff) @[el2_pic_ctl.scala 157:153] - node _T_237 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] - node _T_238 = eq(_T_237, UInt<3>("h06")) @[el2_pic_ctl.scala 157:139] - node _T_239 = and(waddr_intenable_base_match, _T_238) @[el2_pic_ctl.scala 157:106] - node intenable_reg_we_6 = and(_T_239, picm_wren_ff) @[el2_pic_ctl.scala 157:153] - node _T_240 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] - node _T_241 = eq(_T_240, UInt<3>("h07")) @[el2_pic_ctl.scala 157:139] - node _T_242 = and(waddr_intenable_base_match, _T_241) @[el2_pic_ctl.scala 157:106] - node intenable_reg_we_7 = and(_T_242, picm_wren_ff) @[el2_pic_ctl.scala 157:153] - node _T_243 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] - node _T_244 = eq(_T_243, UInt<4>("h08")) @[el2_pic_ctl.scala 157:139] - node _T_245 = and(waddr_intenable_base_match, _T_244) @[el2_pic_ctl.scala 157:106] - node intenable_reg_we_8 = and(_T_245, picm_wren_ff) @[el2_pic_ctl.scala 157:153] - node _T_246 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] - node _T_247 = eq(_T_246, UInt<4>("h09")) @[el2_pic_ctl.scala 157:139] - node _T_248 = and(waddr_intenable_base_match, _T_247) @[el2_pic_ctl.scala 157:106] - node intenable_reg_we_9 = and(_T_248, picm_wren_ff) @[el2_pic_ctl.scala 157:153] - node _T_249 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] - node _T_250 = eq(_T_249, UInt<4>("h0a")) @[el2_pic_ctl.scala 157:139] - node _T_251 = and(waddr_intenable_base_match, _T_250) @[el2_pic_ctl.scala 157:106] - node intenable_reg_we_10 = and(_T_251, picm_wren_ff) @[el2_pic_ctl.scala 157:153] - node _T_252 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] - node _T_253 = eq(_T_252, UInt<4>("h0b")) @[el2_pic_ctl.scala 157:139] - node _T_254 = and(waddr_intenable_base_match, _T_253) @[el2_pic_ctl.scala 157:106] - node intenable_reg_we_11 = and(_T_254, picm_wren_ff) @[el2_pic_ctl.scala 157:153] - node _T_255 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] - node _T_256 = eq(_T_255, UInt<4>("h0c")) @[el2_pic_ctl.scala 157:139] - node _T_257 = and(waddr_intenable_base_match, _T_256) @[el2_pic_ctl.scala 157:106] - node intenable_reg_we_12 = and(_T_257, picm_wren_ff) @[el2_pic_ctl.scala 157:153] - node _T_258 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] - node _T_259 = eq(_T_258, UInt<4>("h0d")) @[el2_pic_ctl.scala 157:139] - node _T_260 = and(waddr_intenable_base_match, _T_259) @[el2_pic_ctl.scala 157:106] - node intenable_reg_we_13 = and(_T_260, picm_wren_ff) @[el2_pic_ctl.scala 157:153] - node _T_261 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] - node _T_262 = eq(_T_261, UInt<4>("h0e")) @[el2_pic_ctl.scala 157:139] - node _T_263 = and(waddr_intenable_base_match, _T_262) @[el2_pic_ctl.scala 157:106] - node intenable_reg_we_14 = and(_T_263, picm_wren_ff) @[el2_pic_ctl.scala 157:153] - node _T_264 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] - node _T_265 = eq(_T_264, UInt<4>("h0f")) @[el2_pic_ctl.scala 157:139] - node _T_266 = and(waddr_intenable_base_match, _T_265) @[el2_pic_ctl.scala 157:106] - node intenable_reg_we_15 = and(_T_266, picm_wren_ff) @[el2_pic_ctl.scala 157:153] - node _T_267 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] - node _T_268 = eq(_T_267, UInt<5>("h010")) @[el2_pic_ctl.scala 157:139] - node _T_269 = and(waddr_intenable_base_match, _T_268) @[el2_pic_ctl.scala 157:106] - node intenable_reg_we_16 = and(_T_269, picm_wren_ff) @[el2_pic_ctl.scala 157:153] - node _T_270 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] - node _T_271 = eq(_T_270, UInt<5>("h011")) @[el2_pic_ctl.scala 157:139] - node _T_272 = and(waddr_intenable_base_match, _T_271) @[el2_pic_ctl.scala 157:106] - node intenable_reg_we_17 = and(_T_272, picm_wren_ff) @[el2_pic_ctl.scala 157:153] - node _T_273 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] - node _T_274 = eq(_T_273, UInt<5>("h012")) @[el2_pic_ctl.scala 157:139] - node _T_275 = and(waddr_intenable_base_match, _T_274) @[el2_pic_ctl.scala 157:106] - node intenable_reg_we_18 = and(_T_275, picm_wren_ff) @[el2_pic_ctl.scala 157:153] - node _T_276 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] - node _T_277 = eq(_T_276, UInt<5>("h013")) @[el2_pic_ctl.scala 157:139] - node _T_278 = and(waddr_intenable_base_match, _T_277) @[el2_pic_ctl.scala 157:106] - node intenable_reg_we_19 = and(_T_278, picm_wren_ff) @[el2_pic_ctl.scala 157:153] - node _T_279 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] - node _T_280 = eq(_T_279, UInt<5>("h014")) @[el2_pic_ctl.scala 157:139] - node _T_281 = and(waddr_intenable_base_match, _T_280) @[el2_pic_ctl.scala 157:106] - node intenable_reg_we_20 = and(_T_281, picm_wren_ff) @[el2_pic_ctl.scala 157:153] - node _T_282 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] - node _T_283 = eq(_T_282, UInt<5>("h015")) @[el2_pic_ctl.scala 157:139] - node _T_284 = and(waddr_intenable_base_match, _T_283) @[el2_pic_ctl.scala 157:106] - node intenable_reg_we_21 = and(_T_284, picm_wren_ff) @[el2_pic_ctl.scala 157:153] - node _T_285 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] - node _T_286 = eq(_T_285, UInt<5>("h016")) @[el2_pic_ctl.scala 157:139] - node _T_287 = and(waddr_intenable_base_match, _T_286) @[el2_pic_ctl.scala 157:106] - node intenable_reg_we_22 = and(_T_287, picm_wren_ff) @[el2_pic_ctl.scala 157:153] - node _T_288 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] - node _T_289 = eq(_T_288, UInt<5>("h017")) @[el2_pic_ctl.scala 157:139] - node _T_290 = and(waddr_intenable_base_match, _T_289) @[el2_pic_ctl.scala 157:106] - node intenable_reg_we_23 = and(_T_290, picm_wren_ff) @[el2_pic_ctl.scala 157:153] - node _T_291 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] - node _T_292 = eq(_T_291, UInt<5>("h018")) @[el2_pic_ctl.scala 157:139] - node _T_293 = and(waddr_intenable_base_match, _T_292) @[el2_pic_ctl.scala 157:106] - node intenable_reg_we_24 = and(_T_293, picm_wren_ff) @[el2_pic_ctl.scala 157:153] - node _T_294 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] - node _T_295 = eq(_T_294, UInt<5>("h019")) @[el2_pic_ctl.scala 157:139] - node _T_296 = and(waddr_intenable_base_match, _T_295) @[el2_pic_ctl.scala 157:106] - node intenable_reg_we_25 = and(_T_296, picm_wren_ff) @[el2_pic_ctl.scala 157:153] - node _T_297 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] - node _T_298 = eq(_T_297, UInt<5>("h01a")) @[el2_pic_ctl.scala 157:139] - node _T_299 = and(waddr_intenable_base_match, _T_298) @[el2_pic_ctl.scala 157:106] - node intenable_reg_we_26 = and(_T_299, picm_wren_ff) @[el2_pic_ctl.scala 157:153] - node _T_300 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] - node _T_301 = eq(_T_300, UInt<5>("h01b")) @[el2_pic_ctl.scala 157:139] - node _T_302 = and(waddr_intenable_base_match, _T_301) @[el2_pic_ctl.scala 157:106] - node intenable_reg_we_27 = and(_T_302, picm_wren_ff) @[el2_pic_ctl.scala 157:153] - node _T_303 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] - node _T_304 = eq(_T_303, UInt<5>("h01c")) @[el2_pic_ctl.scala 157:139] - node _T_305 = and(waddr_intenable_base_match, _T_304) @[el2_pic_ctl.scala 157:106] - node intenable_reg_we_28 = and(_T_305, picm_wren_ff) @[el2_pic_ctl.scala 157:153] - node _T_306 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] - node _T_307 = eq(_T_306, UInt<5>("h01d")) @[el2_pic_ctl.scala 157:139] - node _T_308 = and(waddr_intenable_base_match, _T_307) @[el2_pic_ctl.scala 157:106] - node intenable_reg_we_29 = and(_T_308, picm_wren_ff) @[el2_pic_ctl.scala 157:153] - node _T_309 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] - node _T_310 = eq(_T_309, UInt<5>("h01e")) @[el2_pic_ctl.scala 157:139] - node _T_311 = and(waddr_intenable_base_match, _T_310) @[el2_pic_ctl.scala 157:106] - node intenable_reg_we_30 = and(_T_311, picm_wren_ff) @[el2_pic_ctl.scala 157:153] - node _T_312 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] - node _T_313 = eq(_T_312, UInt<5>("h01f")) @[el2_pic_ctl.scala 157:139] - node _T_314 = and(waddr_intenable_base_match, _T_313) @[el2_pic_ctl.scala 157:106] - node intenable_reg_we_31 = and(_T_314, picm_wren_ff) @[el2_pic_ctl.scala 157:153] - node _T_315 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] - node _T_316 = eq(_T_315, UInt<1>("h01")) @[el2_pic_ctl.scala 158:139] - node _T_317 = and(raddr_intenable_base_match, _T_316) @[el2_pic_ctl.scala 158:106] - node intenable_reg_re_1 = and(_T_317, picm_rden_ff) @[el2_pic_ctl.scala 158:153] - node _T_318 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] - node _T_319 = eq(_T_318, UInt<2>("h02")) @[el2_pic_ctl.scala 158:139] - node _T_320 = and(raddr_intenable_base_match, _T_319) @[el2_pic_ctl.scala 158:106] - node intenable_reg_re_2 = and(_T_320, picm_rden_ff) @[el2_pic_ctl.scala 158:153] - node _T_321 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] - node _T_322 = eq(_T_321, UInt<2>("h03")) @[el2_pic_ctl.scala 158:139] - node _T_323 = and(raddr_intenable_base_match, _T_322) @[el2_pic_ctl.scala 158:106] - node intenable_reg_re_3 = and(_T_323, picm_rden_ff) @[el2_pic_ctl.scala 158:153] - node _T_324 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] - node _T_325 = eq(_T_324, UInt<3>("h04")) @[el2_pic_ctl.scala 158:139] - node _T_326 = and(raddr_intenable_base_match, _T_325) @[el2_pic_ctl.scala 158:106] - node intenable_reg_re_4 = and(_T_326, picm_rden_ff) @[el2_pic_ctl.scala 158:153] - node _T_327 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] - node _T_328 = eq(_T_327, UInt<3>("h05")) @[el2_pic_ctl.scala 158:139] - node _T_329 = and(raddr_intenable_base_match, _T_328) @[el2_pic_ctl.scala 158:106] - node intenable_reg_re_5 = and(_T_329, picm_rden_ff) @[el2_pic_ctl.scala 158:153] - node _T_330 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] - node _T_331 = eq(_T_330, UInt<3>("h06")) @[el2_pic_ctl.scala 158:139] - node _T_332 = and(raddr_intenable_base_match, _T_331) @[el2_pic_ctl.scala 158:106] - node intenable_reg_re_6 = and(_T_332, picm_rden_ff) @[el2_pic_ctl.scala 158:153] - node _T_333 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] - node _T_334 = eq(_T_333, UInt<3>("h07")) @[el2_pic_ctl.scala 158:139] - node _T_335 = and(raddr_intenable_base_match, _T_334) @[el2_pic_ctl.scala 158:106] - node intenable_reg_re_7 = and(_T_335, picm_rden_ff) @[el2_pic_ctl.scala 158:153] - node _T_336 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] - node _T_337 = eq(_T_336, UInt<4>("h08")) @[el2_pic_ctl.scala 158:139] - node _T_338 = and(raddr_intenable_base_match, _T_337) @[el2_pic_ctl.scala 158:106] - node intenable_reg_re_8 = and(_T_338, picm_rden_ff) @[el2_pic_ctl.scala 158:153] - node _T_339 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] - node _T_340 = eq(_T_339, UInt<4>("h09")) @[el2_pic_ctl.scala 158:139] - node _T_341 = and(raddr_intenable_base_match, _T_340) @[el2_pic_ctl.scala 158:106] - node intenable_reg_re_9 = and(_T_341, picm_rden_ff) @[el2_pic_ctl.scala 158:153] - node _T_342 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] - node _T_343 = eq(_T_342, UInt<4>("h0a")) @[el2_pic_ctl.scala 158:139] - node _T_344 = and(raddr_intenable_base_match, _T_343) @[el2_pic_ctl.scala 158:106] - node intenable_reg_re_10 = and(_T_344, picm_rden_ff) @[el2_pic_ctl.scala 158:153] - node _T_345 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] - node _T_346 = eq(_T_345, UInt<4>("h0b")) @[el2_pic_ctl.scala 158:139] - node _T_347 = and(raddr_intenable_base_match, _T_346) @[el2_pic_ctl.scala 158:106] - node intenable_reg_re_11 = and(_T_347, picm_rden_ff) @[el2_pic_ctl.scala 158:153] - node _T_348 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] - node _T_349 = eq(_T_348, UInt<4>("h0c")) @[el2_pic_ctl.scala 158:139] - node _T_350 = and(raddr_intenable_base_match, _T_349) @[el2_pic_ctl.scala 158:106] - node intenable_reg_re_12 = and(_T_350, picm_rden_ff) @[el2_pic_ctl.scala 158:153] - node _T_351 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] - node _T_352 = eq(_T_351, UInt<4>("h0d")) @[el2_pic_ctl.scala 158:139] - node _T_353 = and(raddr_intenable_base_match, _T_352) @[el2_pic_ctl.scala 158:106] - node intenable_reg_re_13 = and(_T_353, picm_rden_ff) @[el2_pic_ctl.scala 158:153] - node _T_354 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] - node _T_355 = eq(_T_354, UInt<4>("h0e")) @[el2_pic_ctl.scala 158:139] - node _T_356 = and(raddr_intenable_base_match, _T_355) @[el2_pic_ctl.scala 158:106] - node intenable_reg_re_14 = and(_T_356, picm_rden_ff) @[el2_pic_ctl.scala 158:153] - node _T_357 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] - node _T_358 = eq(_T_357, UInt<4>("h0f")) @[el2_pic_ctl.scala 158:139] - node _T_359 = and(raddr_intenable_base_match, _T_358) @[el2_pic_ctl.scala 158:106] - node intenable_reg_re_15 = and(_T_359, picm_rden_ff) @[el2_pic_ctl.scala 158:153] - node _T_360 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] - node _T_361 = eq(_T_360, UInt<5>("h010")) @[el2_pic_ctl.scala 158:139] - node _T_362 = and(raddr_intenable_base_match, _T_361) @[el2_pic_ctl.scala 158:106] - node intenable_reg_re_16 = and(_T_362, picm_rden_ff) @[el2_pic_ctl.scala 158:153] - node _T_363 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] - node _T_364 = eq(_T_363, UInt<5>("h011")) @[el2_pic_ctl.scala 158:139] - node _T_365 = and(raddr_intenable_base_match, _T_364) @[el2_pic_ctl.scala 158:106] - node intenable_reg_re_17 = and(_T_365, picm_rden_ff) @[el2_pic_ctl.scala 158:153] - node _T_366 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] - node _T_367 = eq(_T_366, UInt<5>("h012")) @[el2_pic_ctl.scala 158:139] - node _T_368 = and(raddr_intenable_base_match, _T_367) @[el2_pic_ctl.scala 158:106] - node intenable_reg_re_18 = and(_T_368, picm_rden_ff) @[el2_pic_ctl.scala 158:153] - node _T_369 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] - node _T_370 = eq(_T_369, UInt<5>("h013")) @[el2_pic_ctl.scala 158:139] - node _T_371 = and(raddr_intenable_base_match, _T_370) @[el2_pic_ctl.scala 158:106] - node intenable_reg_re_19 = and(_T_371, picm_rden_ff) @[el2_pic_ctl.scala 158:153] - node _T_372 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] - node _T_373 = eq(_T_372, UInt<5>("h014")) @[el2_pic_ctl.scala 158:139] - node _T_374 = and(raddr_intenable_base_match, _T_373) @[el2_pic_ctl.scala 158:106] - node intenable_reg_re_20 = and(_T_374, picm_rden_ff) @[el2_pic_ctl.scala 158:153] - node _T_375 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] - node _T_376 = eq(_T_375, UInt<5>("h015")) @[el2_pic_ctl.scala 158:139] - node _T_377 = and(raddr_intenable_base_match, _T_376) @[el2_pic_ctl.scala 158:106] - node intenable_reg_re_21 = and(_T_377, picm_rden_ff) @[el2_pic_ctl.scala 158:153] - node _T_378 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] - node _T_379 = eq(_T_378, UInt<5>("h016")) @[el2_pic_ctl.scala 158:139] - node _T_380 = and(raddr_intenable_base_match, _T_379) @[el2_pic_ctl.scala 158:106] - node intenable_reg_re_22 = and(_T_380, picm_rden_ff) @[el2_pic_ctl.scala 158:153] - node _T_381 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] - node _T_382 = eq(_T_381, UInt<5>("h017")) @[el2_pic_ctl.scala 158:139] - node _T_383 = and(raddr_intenable_base_match, _T_382) @[el2_pic_ctl.scala 158:106] - node intenable_reg_re_23 = and(_T_383, picm_rden_ff) @[el2_pic_ctl.scala 158:153] - node _T_384 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] - node _T_385 = eq(_T_384, UInt<5>("h018")) @[el2_pic_ctl.scala 158:139] - node _T_386 = and(raddr_intenable_base_match, _T_385) @[el2_pic_ctl.scala 158:106] - node intenable_reg_re_24 = and(_T_386, picm_rden_ff) @[el2_pic_ctl.scala 158:153] - node _T_387 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] - node _T_388 = eq(_T_387, UInt<5>("h019")) @[el2_pic_ctl.scala 158:139] - node _T_389 = and(raddr_intenable_base_match, _T_388) @[el2_pic_ctl.scala 158:106] - node intenable_reg_re_25 = and(_T_389, picm_rden_ff) @[el2_pic_ctl.scala 158:153] - node _T_390 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] - node _T_391 = eq(_T_390, UInt<5>("h01a")) @[el2_pic_ctl.scala 158:139] - node _T_392 = and(raddr_intenable_base_match, _T_391) @[el2_pic_ctl.scala 158:106] - node intenable_reg_re_26 = and(_T_392, picm_rden_ff) @[el2_pic_ctl.scala 158:153] - node _T_393 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] - node _T_394 = eq(_T_393, UInt<5>("h01b")) @[el2_pic_ctl.scala 158:139] - node _T_395 = and(raddr_intenable_base_match, _T_394) @[el2_pic_ctl.scala 158:106] - node intenable_reg_re_27 = and(_T_395, picm_rden_ff) @[el2_pic_ctl.scala 158:153] - node _T_396 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] - node _T_397 = eq(_T_396, UInt<5>("h01c")) @[el2_pic_ctl.scala 158:139] - node _T_398 = and(raddr_intenable_base_match, _T_397) @[el2_pic_ctl.scala 158:106] - node intenable_reg_re_28 = and(_T_398, picm_rden_ff) @[el2_pic_ctl.scala 158:153] - node _T_399 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] - node _T_400 = eq(_T_399, UInt<5>("h01d")) @[el2_pic_ctl.scala 158:139] - node _T_401 = and(raddr_intenable_base_match, _T_400) @[el2_pic_ctl.scala 158:106] - node intenable_reg_re_29 = and(_T_401, picm_rden_ff) @[el2_pic_ctl.scala 158:153] - node _T_402 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] - node _T_403 = eq(_T_402, UInt<5>("h01e")) @[el2_pic_ctl.scala 158:139] - node _T_404 = and(raddr_intenable_base_match, _T_403) @[el2_pic_ctl.scala 158:106] - node intenable_reg_re_30 = and(_T_404, picm_rden_ff) @[el2_pic_ctl.scala 158:153] - node _T_405 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] - node _T_406 = eq(_T_405, UInt<5>("h01f")) @[el2_pic_ctl.scala 158:139] - node _T_407 = and(raddr_intenable_base_match, _T_406) @[el2_pic_ctl.scala 158:106] - node intenable_reg_re_31 = and(_T_407, picm_rden_ff) @[el2_pic_ctl.scala 158:153] - node _T_408 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] - node _T_409 = eq(_T_408, UInt<1>("h01")) @[el2_pic_ctl.scala 159:139] - node _T_410 = and(waddr_config_gw_base_match, _T_409) @[el2_pic_ctl.scala 159:106] - node gw_config_reg_we_1 = and(_T_410, picm_wren_ff) @[el2_pic_ctl.scala 159:153] - node _T_411 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] - node _T_412 = eq(_T_411, UInt<2>("h02")) @[el2_pic_ctl.scala 159:139] - node _T_413 = and(waddr_config_gw_base_match, _T_412) @[el2_pic_ctl.scala 159:106] - node gw_config_reg_we_2 = and(_T_413, picm_wren_ff) @[el2_pic_ctl.scala 159:153] - node _T_414 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] - node _T_415 = eq(_T_414, UInt<2>("h03")) @[el2_pic_ctl.scala 159:139] - node _T_416 = and(waddr_config_gw_base_match, _T_415) @[el2_pic_ctl.scala 159:106] - node gw_config_reg_we_3 = and(_T_416, picm_wren_ff) @[el2_pic_ctl.scala 159:153] - node _T_417 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] - node _T_418 = eq(_T_417, UInt<3>("h04")) @[el2_pic_ctl.scala 159:139] - node _T_419 = and(waddr_config_gw_base_match, _T_418) @[el2_pic_ctl.scala 159:106] - node gw_config_reg_we_4 = and(_T_419, picm_wren_ff) @[el2_pic_ctl.scala 159:153] - node _T_420 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] - node _T_421 = eq(_T_420, UInt<3>("h05")) @[el2_pic_ctl.scala 159:139] - node _T_422 = and(waddr_config_gw_base_match, _T_421) @[el2_pic_ctl.scala 159:106] - node gw_config_reg_we_5 = and(_T_422, picm_wren_ff) @[el2_pic_ctl.scala 159:153] - node _T_423 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] - node _T_424 = eq(_T_423, UInt<3>("h06")) @[el2_pic_ctl.scala 159:139] - node _T_425 = and(waddr_config_gw_base_match, _T_424) @[el2_pic_ctl.scala 159:106] - node gw_config_reg_we_6 = and(_T_425, picm_wren_ff) @[el2_pic_ctl.scala 159:153] - node _T_426 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] - node _T_427 = eq(_T_426, UInt<3>("h07")) @[el2_pic_ctl.scala 159:139] - node _T_428 = and(waddr_config_gw_base_match, _T_427) @[el2_pic_ctl.scala 159:106] - node gw_config_reg_we_7 = and(_T_428, picm_wren_ff) @[el2_pic_ctl.scala 159:153] - node _T_429 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] - node _T_430 = eq(_T_429, UInt<4>("h08")) @[el2_pic_ctl.scala 159:139] - node _T_431 = and(waddr_config_gw_base_match, _T_430) @[el2_pic_ctl.scala 159:106] - node gw_config_reg_we_8 = and(_T_431, picm_wren_ff) @[el2_pic_ctl.scala 159:153] - node _T_432 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] - node _T_433 = eq(_T_432, UInt<4>("h09")) @[el2_pic_ctl.scala 159:139] - node _T_434 = and(waddr_config_gw_base_match, _T_433) @[el2_pic_ctl.scala 159:106] - node gw_config_reg_we_9 = and(_T_434, picm_wren_ff) @[el2_pic_ctl.scala 159:153] - node _T_435 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] - node _T_436 = eq(_T_435, UInt<4>("h0a")) @[el2_pic_ctl.scala 159:139] - node _T_437 = and(waddr_config_gw_base_match, _T_436) @[el2_pic_ctl.scala 159:106] - node gw_config_reg_we_10 = and(_T_437, picm_wren_ff) @[el2_pic_ctl.scala 159:153] - node _T_438 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] - node _T_439 = eq(_T_438, UInt<4>("h0b")) @[el2_pic_ctl.scala 159:139] - node _T_440 = and(waddr_config_gw_base_match, _T_439) @[el2_pic_ctl.scala 159:106] - node gw_config_reg_we_11 = and(_T_440, picm_wren_ff) @[el2_pic_ctl.scala 159:153] - node _T_441 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] - node _T_442 = eq(_T_441, UInt<4>("h0c")) @[el2_pic_ctl.scala 159:139] - node _T_443 = and(waddr_config_gw_base_match, _T_442) @[el2_pic_ctl.scala 159:106] - node gw_config_reg_we_12 = and(_T_443, picm_wren_ff) @[el2_pic_ctl.scala 159:153] - node _T_444 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] - node _T_445 = eq(_T_444, UInt<4>("h0d")) @[el2_pic_ctl.scala 159:139] - node _T_446 = and(waddr_config_gw_base_match, _T_445) @[el2_pic_ctl.scala 159:106] - node gw_config_reg_we_13 = and(_T_446, picm_wren_ff) @[el2_pic_ctl.scala 159:153] - node _T_447 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] - node _T_448 = eq(_T_447, UInt<4>("h0e")) @[el2_pic_ctl.scala 159:139] - node _T_449 = and(waddr_config_gw_base_match, _T_448) @[el2_pic_ctl.scala 159:106] - node gw_config_reg_we_14 = and(_T_449, picm_wren_ff) @[el2_pic_ctl.scala 159:153] - node _T_450 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] - node _T_451 = eq(_T_450, UInt<4>("h0f")) @[el2_pic_ctl.scala 159:139] - node _T_452 = and(waddr_config_gw_base_match, _T_451) @[el2_pic_ctl.scala 159:106] - node gw_config_reg_we_15 = and(_T_452, picm_wren_ff) @[el2_pic_ctl.scala 159:153] - node _T_453 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] - node _T_454 = eq(_T_453, UInt<5>("h010")) @[el2_pic_ctl.scala 159:139] - node _T_455 = and(waddr_config_gw_base_match, _T_454) @[el2_pic_ctl.scala 159:106] - node gw_config_reg_we_16 = and(_T_455, picm_wren_ff) @[el2_pic_ctl.scala 159:153] - node _T_456 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] - node _T_457 = eq(_T_456, UInt<5>("h011")) @[el2_pic_ctl.scala 159:139] - node _T_458 = and(waddr_config_gw_base_match, _T_457) @[el2_pic_ctl.scala 159:106] - node gw_config_reg_we_17 = and(_T_458, picm_wren_ff) @[el2_pic_ctl.scala 159:153] - node _T_459 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] - node _T_460 = eq(_T_459, UInt<5>("h012")) @[el2_pic_ctl.scala 159:139] - node _T_461 = and(waddr_config_gw_base_match, _T_460) @[el2_pic_ctl.scala 159:106] - node gw_config_reg_we_18 = and(_T_461, picm_wren_ff) @[el2_pic_ctl.scala 159:153] - node _T_462 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] - node _T_463 = eq(_T_462, UInt<5>("h013")) @[el2_pic_ctl.scala 159:139] - node _T_464 = and(waddr_config_gw_base_match, _T_463) @[el2_pic_ctl.scala 159:106] - node gw_config_reg_we_19 = and(_T_464, picm_wren_ff) @[el2_pic_ctl.scala 159:153] - node _T_465 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] - node _T_466 = eq(_T_465, UInt<5>("h014")) @[el2_pic_ctl.scala 159:139] - node _T_467 = and(waddr_config_gw_base_match, _T_466) @[el2_pic_ctl.scala 159:106] - node gw_config_reg_we_20 = and(_T_467, picm_wren_ff) @[el2_pic_ctl.scala 159:153] - node _T_468 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] - node _T_469 = eq(_T_468, UInt<5>("h015")) @[el2_pic_ctl.scala 159:139] - node _T_470 = and(waddr_config_gw_base_match, _T_469) @[el2_pic_ctl.scala 159:106] - node gw_config_reg_we_21 = and(_T_470, picm_wren_ff) @[el2_pic_ctl.scala 159:153] - node _T_471 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] - node _T_472 = eq(_T_471, UInt<5>("h016")) @[el2_pic_ctl.scala 159:139] - node _T_473 = and(waddr_config_gw_base_match, _T_472) @[el2_pic_ctl.scala 159:106] - node gw_config_reg_we_22 = and(_T_473, picm_wren_ff) @[el2_pic_ctl.scala 159:153] - node _T_474 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] - node _T_475 = eq(_T_474, UInt<5>("h017")) @[el2_pic_ctl.scala 159:139] - node _T_476 = and(waddr_config_gw_base_match, _T_475) @[el2_pic_ctl.scala 159:106] - node gw_config_reg_we_23 = and(_T_476, picm_wren_ff) @[el2_pic_ctl.scala 159:153] - node _T_477 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] - node _T_478 = eq(_T_477, UInt<5>("h018")) @[el2_pic_ctl.scala 159:139] - node _T_479 = and(waddr_config_gw_base_match, _T_478) @[el2_pic_ctl.scala 159:106] - node gw_config_reg_we_24 = and(_T_479, picm_wren_ff) @[el2_pic_ctl.scala 159:153] - node _T_480 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] - node _T_481 = eq(_T_480, UInt<5>("h019")) @[el2_pic_ctl.scala 159:139] - node _T_482 = and(waddr_config_gw_base_match, _T_481) @[el2_pic_ctl.scala 159:106] - node gw_config_reg_we_25 = and(_T_482, picm_wren_ff) @[el2_pic_ctl.scala 159:153] - node _T_483 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] - node _T_484 = eq(_T_483, UInt<5>("h01a")) @[el2_pic_ctl.scala 159:139] - node _T_485 = and(waddr_config_gw_base_match, _T_484) @[el2_pic_ctl.scala 159:106] - node gw_config_reg_we_26 = and(_T_485, picm_wren_ff) @[el2_pic_ctl.scala 159:153] - node _T_486 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] - node _T_487 = eq(_T_486, UInt<5>("h01b")) @[el2_pic_ctl.scala 159:139] - node _T_488 = and(waddr_config_gw_base_match, _T_487) @[el2_pic_ctl.scala 159:106] - node gw_config_reg_we_27 = and(_T_488, picm_wren_ff) @[el2_pic_ctl.scala 159:153] - node _T_489 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] - node _T_490 = eq(_T_489, UInt<5>("h01c")) @[el2_pic_ctl.scala 159:139] - node _T_491 = and(waddr_config_gw_base_match, _T_490) @[el2_pic_ctl.scala 159:106] - node gw_config_reg_we_28 = and(_T_491, picm_wren_ff) @[el2_pic_ctl.scala 159:153] - node _T_492 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] - node _T_493 = eq(_T_492, UInt<5>("h01d")) @[el2_pic_ctl.scala 159:139] - node _T_494 = and(waddr_config_gw_base_match, _T_493) @[el2_pic_ctl.scala 159:106] - node gw_config_reg_we_29 = and(_T_494, picm_wren_ff) @[el2_pic_ctl.scala 159:153] - node _T_495 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] - node _T_496 = eq(_T_495, UInt<5>("h01e")) @[el2_pic_ctl.scala 159:139] - node _T_497 = and(waddr_config_gw_base_match, _T_496) @[el2_pic_ctl.scala 159:106] - node gw_config_reg_we_30 = and(_T_497, picm_wren_ff) @[el2_pic_ctl.scala 159:153] - node _T_498 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] - node _T_499 = eq(_T_498, UInt<5>("h01f")) @[el2_pic_ctl.scala 159:139] - node _T_500 = and(waddr_config_gw_base_match, _T_499) @[el2_pic_ctl.scala 159:106] - node gw_config_reg_we_31 = and(_T_500, picm_wren_ff) @[el2_pic_ctl.scala 159:153] - node _T_501 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] - node _T_502 = eq(_T_501, UInt<1>("h01")) @[el2_pic_ctl.scala 160:139] - node _T_503 = and(raddr_config_gw_base_match, _T_502) @[el2_pic_ctl.scala 160:106] - node gw_config_reg_re_1 = and(_T_503, picm_rden_ff) @[el2_pic_ctl.scala 160:153] - node _T_504 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] - node _T_505 = eq(_T_504, UInt<2>("h02")) @[el2_pic_ctl.scala 160:139] - node _T_506 = and(raddr_config_gw_base_match, _T_505) @[el2_pic_ctl.scala 160:106] - node gw_config_reg_re_2 = and(_T_506, picm_rden_ff) @[el2_pic_ctl.scala 160:153] - node _T_507 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] - node _T_508 = eq(_T_507, UInt<2>("h03")) @[el2_pic_ctl.scala 160:139] - node _T_509 = and(raddr_config_gw_base_match, _T_508) @[el2_pic_ctl.scala 160:106] - node gw_config_reg_re_3 = and(_T_509, picm_rden_ff) @[el2_pic_ctl.scala 160:153] - node _T_510 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] - node _T_511 = eq(_T_510, UInt<3>("h04")) @[el2_pic_ctl.scala 160:139] - node _T_512 = and(raddr_config_gw_base_match, _T_511) @[el2_pic_ctl.scala 160:106] - node gw_config_reg_re_4 = and(_T_512, picm_rden_ff) @[el2_pic_ctl.scala 160:153] - node _T_513 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] - node _T_514 = eq(_T_513, UInt<3>("h05")) @[el2_pic_ctl.scala 160:139] - node _T_515 = and(raddr_config_gw_base_match, _T_514) @[el2_pic_ctl.scala 160:106] - node gw_config_reg_re_5 = and(_T_515, picm_rden_ff) @[el2_pic_ctl.scala 160:153] - node _T_516 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] - node _T_517 = eq(_T_516, UInt<3>("h06")) @[el2_pic_ctl.scala 160:139] - node _T_518 = and(raddr_config_gw_base_match, _T_517) @[el2_pic_ctl.scala 160:106] - node gw_config_reg_re_6 = and(_T_518, picm_rden_ff) @[el2_pic_ctl.scala 160:153] - node _T_519 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] - node _T_520 = eq(_T_519, UInt<3>("h07")) @[el2_pic_ctl.scala 160:139] - node _T_521 = and(raddr_config_gw_base_match, _T_520) @[el2_pic_ctl.scala 160:106] - node gw_config_reg_re_7 = and(_T_521, picm_rden_ff) @[el2_pic_ctl.scala 160:153] - node _T_522 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] - node _T_523 = eq(_T_522, UInt<4>("h08")) @[el2_pic_ctl.scala 160:139] - node _T_524 = and(raddr_config_gw_base_match, _T_523) @[el2_pic_ctl.scala 160:106] - node gw_config_reg_re_8 = and(_T_524, picm_rden_ff) @[el2_pic_ctl.scala 160:153] - node _T_525 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] - node _T_526 = eq(_T_525, UInt<4>("h09")) @[el2_pic_ctl.scala 160:139] - node _T_527 = and(raddr_config_gw_base_match, _T_526) @[el2_pic_ctl.scala 160:106] - node gw_config_reg_re_9 = and(_T_527, picm_rden_ff) @[el2_pic_ctl.scala 160:153] - node _T_528 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] - node _T_529 = eq(_T_528, UInt<4>("h0a")) @[el2_pic_ctl.scala 160:139] - node _T_530 = and(raddr_config_gw_base_match, _T_529) @[el2_pic_ctl.scala 160:106] - node gw_config_reg_re_10 = and(_T_530, picm_rden_ff) @[el2_pic_ctl.scala 160:153] - node _T_531 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] - node _T_532 = eq(_T_531, UInt<4>("h0b")) @[el2_pic_ctl.scala 160:139] - node _T_533 = and(raddr_config_gw_base_match, _T_532) @[el2_pic_ctl.scala 160:106] - node gw_config_reg_re_11 = and(_T_533, picm_rden_ff) @[el2_pic_ctl.scala 160:153] - node _T_534 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] - node _T_535 = eq(_T_534, UInt<4>("h0c")) @[el2_pic_ctl.scala 160:139] - node _T_536 = and(raddr_config_gw_base_match, _T_535) @[el2_pic_ctl.scala 160:106] - node gw_config_reg_re_12 = and(_T_536, picm_rden_ff) @[el2_pic_ctl.scala 160:153] - node _T_537 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] - node _T_538 = eq(_T_537, UInt<4>("h0d")) @[el2_pic_ctl.scala 160:139] - node _T_539 = and(raddr_config_gw_base_match, _T_538) @[el2_pic_ctl.scala 160:106] - node gw_config_reg_re_13 = and(_T_539, picm_rden_ff) @[el2_pic_ctl.scala 160:153] - node _T_540 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] - node _T_541 = eq(_T_540, UInt<4>("h0e")) @[el2_pic_ctl.scala 160:139] - node _T_542 = and(raddr_config_gw_base_match, _T_541) @[el2_pic_ctl.scala 160:106] - node gw_config_reg_re_14 = and(_T_542, picm_rden_ff) @[el2_pic_ctl.scala 160:153] - node _T_543 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] - node _T_544 = eq(_T_543, UInt<4>("h0f")) @[el2_pic_ctl.scala 160:139] - node _T_545 = and(raddr_config_gw_base_match, _T_544) @[el2_pic_ctl.scala 160:106] - node gw_config_reg_re_15 = and(_T_545, picm_rden_ff) @[el2_pic_ctl.scala 160:153] - node _T_546 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] - node _T_547 = eq(_T_546, UInt<5>("h010")) @[el2_pic_ctl.scala 160:139] - node _T_548 = and(raddr_config_gw_base_match, _T_547) @[el2_pic_ctl.scala 160:106] - node gw_config_reg_re_16 = and(_T_548, picm_rden_ff) @[el2_pic_ctl.scala 160:153] - node _T_549 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] - node _T_550 = eq(_T_549, UInt<5>("h011")) @[el2_pic_ctl.scala 160:139] - node _T_551 = and(raddr_config_gw_base_match, _T_550) @[el2_pic_ctl.scala 160:106] - node gw_config_reg_re_17 = and(_T_551, picm_rden_ff) @[el2_pic_ctl.scala 160:153] - node _T_552 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] - node _T_553 = eq(_T_552, UInt<5>("h012")) @[el2_pic_ctl.scala 160:139] - node _T_554 = and(raddr_config_gw_base_match, _T_553) @[el2_pic_ctl.scala 160:106] - node gw_config_reg_re_18 = and(_T_554, picm_rden_ff) @[el2_pic_ctl.scala 160:153] - node _T_555 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] - node _T_556 = eq(_T_555, UInt<5>("h013")) @[el2_pic_ctl.scala 160:139] - node _T_557 = and(raddr_config_gw_base_match, _T_556) @[el2_pic_ctl.scala 160:106] - node gw_config_reg_re_19 = and(_T_557, picm_rden_ff) @[el2_pic_ctl.scala 160:153] - node _T_558 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] - node _T_559 = eq(_T_558, UInt<5>("h014")) @[el2_pic_ctl.scala 160:139] - node _T_560 = and(raddr_config_gw_base_match, _T_559) @[el2_pic_ctl.scala 160:106] - node gw_config_reg_re_20 = and(_T_560, picm_rden_ff) @[el2_pic_ctl.scala 160:153] - node _T_561 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] - node _T_562 = eq(_T_561, UInt<5>("h015")) @[el2_pic_ctl.scala 160:139] - node _T_563 = and(raddr_config_gw_base_match, _T_562) @[el2_pic_ctl.scala 160:106] - node gw_config_reg_re_21 = and(_T_563, picm_rden_ff) @[el2_pic_ctl.scala 160:153] - node _T_564 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] - node _T_565 = eq(_T_564, UInt<5>("h016")) @[el2_pic_ctl.scala 160:139] - node _T_566 = and(raddr_config_gw_base_match, _T_565) @[el2_pic_ctl.scala 160:106] - node gw_config_reg_re_22 = and(_T_566, picm_rden_ff) @[el2_pic_ctl.scala 160:153] - node _T_567 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] - node _T_568 = eq(_T_567, UInt<5>("h017")) @[el2_pic_ctl.scala 160:139] - node _T_569 = and(raddr_config_gw_base_match, _T_568) @[el2_pic_ctl.scala 160:106] - node gw_config_reg_re_23 = and(_T_569, picm_rden_ff) @[el2_pic_ctl.scala 160:153] - node _T_570 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] - node _T_571 = eq(_T_570, UInt<5>("h018")) @[el2_pic_ctl.scala 160:139] - node _T_572 = and(raddr_config_gw_base_match, _T_571) @[el2_pic_ctl.scala 160:106] - node gw_config_reg_re_24 = and(_T_572, picm_rden_ff) @[el2_pic_ctl.scala 160:153] - node _T_573 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] - node _T_574 = eq(_T_573, UInt<5>("h019")) @[el2_pic_ctl.scala 160:139] - node _T_575 = and(raddr_config_gw_base_match, _T_574) @[el2_pic_ctl.scala 160:106] - node gw_config_reg_re_25 = and(_T_575, picm_rden_ff) @[el2_pic_ctl.scala 160:153] - node _T_576 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] - node _T_577 = eq(_T_576, UInt<5>("h01a")) @[el2_pic_ctl.scala 160:139] - node _T_578 = and(raddr_config_gw_base_match, _T_577) @[el2_pic_ctl.scala 160:106] - node gw_config_reg_re_26 = and(_T_578, picm_rden_ff) @[el2_pic_ctl.scala 160:153] - node _T_579 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] - node _T_580 = eq(_T_579, UInt<5>("h01b")) @[el2_pic_ctl.scala 160:139] - node _T_581 = and(raddr_config_gw_base_match, _T_580) @[el2_pic_ctl.scala 160:106] - node gw_config_reg_re_27 = and(_T_581, picm_rden_ff) @[el2_pic_ctl.scala 160:153] - node _T_582 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] - node _T_583 = eq(_T_582, UInt<5>("h01c")) @[el2_pic_ctl.scala 160:139] - node _T_584 = and(raddr_config_gw_base_match, _T_583) @[el2_pic_ctl.scala 160:106] - node gw_config_reg_re_28 = and(_T_584, picm_rden_ff) @[el2_pic_ctl.scala 160:153] - node _T_585 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] - node _T_586 = eq(_T_585, UInt<5>("h01d")) @[el2_pic_ctl.scala 160:139] - node _T_587 = and(raddr_config_gw_base_match, _T_586) @[el2_pic_ctl.scala 160:106] - node gw_config_reg_re_29 = and(_T_587, picm_rden_ff) @[el2_pic_ctl.scala 160:153] - node _T_588 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] - node _T_589 = eq(_T_588, UInt<5>("h01e")) @[el2_pic_ctl.scala 160:139] - node _T_590 = and(raddr_config_gw_base_match, _T_589) @[el2_pic_ctl.scala 160:106] - node gw_config_reg_re_30 = and(_T_590, picm_rden_ff) @[el2_pic_ctl.scala 160:153] - node _T_591 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] - node _T_592 = eq(_T_591, UInt<5>("h01f")) @[el2_pic_ctl.scala 160:139] - node _T_593 = and(raddr_config_gw_base_match, _T_592) @[el2_pic_ctl.scala 160:106] - node gw_config_reg_re_31 = and(_T_593, picm_rden_ff) @[el2_pic_ctl.scala 160:153] - node _T_594 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] - node _T_595 = eq(_T_594, UInt<1>("h01")) @[el2_pic_ctl.scala 161:139] - node _T_596 = and(addr_clear_gw_base_match, _T_595) @[el2_pic_ctl.scala 161:106] - node gw_clear_reg_we_1 = and(_T_596, picm_wren_ff) @[el2_pic_ctl.scala 161:153] - node _T_597 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] - node _T_598 = eq(_T_597, UInt<2>("h02")) @[el2_pic_ctl.scala 161:139] - node _T_599 = and(addr_clear_gw_base_match, _T_598) @[el2_pic_ctl.scala 161:106] - node gw_clear_reg_we_2 = and(_T_599, picm_wren_ff) @[el2_pic_ctl.scala 161:153] - node _T_600 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] - node _T_601 = eq(_T_600, UInt<2>("h03")) @[el2_pic_ctl.scala 161:139] - node _T_602 = and(addr_clear_gw_base_match, _T_601) @[el2_pic_ctl.scala 161:106] - node gw_clear_reg_we_3 = and(_T_602, picm_wren_ff) @[el2_pic_ctl.scala 161:153] - node _T_603 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] - node _T_604 = eq(_T_603, UInt<3>("h04")) @[el2_pic_ctl.scala 161:139] - node _T_605 = and(addr_clear_gw_base_match, _T_604) @[el2_pic_ctl.scala 161:106] - node gw_clear_reg_we_4 = and(_T_605, picm_wren_ff) @[el2_pic_ctl.scala 161:153] - node _T_606 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] - node _T_607 = eq(_T_606, UInt<3>("h05")) @[el2_pic_ctl.scala 161:139] - node _T_608 = and(addr_clear_gw_base_match, _T_607) @[el2_pic_ctl.scala 161:106] - node gw_clear_reg_we_5 = and(_T_608, picm_wren_ff) @[el2_pic_ctl.scala 161:153] - node _T_609 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] - node _T_610 = eq(_T_609, UInt<3>("h06")) @[el2_pic_ctl.scala 161:139] - node _T_611 = and(addr_clear_gw_base_match, _T_610) @[el2_pic_ctl.scala 161:106] - node gw_clear_reg_we_6 = and(_T_611, picm_wren_ff) @[el2_pic_ctl.scala 161:153] - node _T_612 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] - node _T_613 = eq(_T_612, UInt<3>("h07")) @[el2_pic_ctl.scala 161:139] - node _T_614 = and(addr_clear_gw_base_match, _T_613) @[el2_pic_ctl.scala 161:106] - node gw_clear_reg_we_7 = and(_T_614, picm_wren_ff) @[el2_pic_ctl.scala 161:153] - node _T_615 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] - node _T_616 = eq(_T_615, UInt<4>("h08")) @[el2_pic_ctl.scala 161:139] - node _T_617 = and(addr_clear_gw_base_match, _T_616) @[el2_pic_ctl.scala 161:106] - node gw_clear_reg_we_8 = and(_T_617, picm_wren_ff) @[el2_pic_ctl.scala 161:153] - node _T_618 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] - node _T_619 = eq(_T_618, UInt<4>("h09")) @[el2_pic_ctl.scala 161:139] - node _T_620 = and(addr_clear_gw_base_match, _T_619) @[el2_pic_ctl.scala 161:106] - node gw_clear_reg_we_9 = and(_T_620, picm_wren_ff) @[el2_pic_ctl.scala 161:153] - node _T_621 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] - node _T_622 = eq(_T_621, UInt<4>("h0a")) @[el2_pic_ctl.scala 161:139] - node _T_623 = and(addr_clear_gw_base_match, _T_622) @[el2_pic_ctl.scala 161:106] - node gw_clear_reg_we_10 = and(_T_623, picm_wren_ff) @[el2_pic_ctl.scala 161:153] - node _T_624 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] - node _T_625 = eq(_T_624, UInt<4>("h0b")) @[el2_pic_ctl.scala 161:139] - node _T_626 = and(addr_clear_gw_base_match, _T_625) @[el2_pic_ctl.scala 161:106] - node gw_clear_reg_we_11 = and(_T_626, picm_wren_ff) @[el2_pic_ctl.scala 161:153] - node _T_627 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] - node _T_628 = eq(_T_627, UInt<4>("h0c")) @[el2_pic_ctl.scala 161:139] - node _T_629 = and(addr_clear_gw_base_match, _T_628) @[el2_pic_ctl.scala 161:106] - node gw_clear_reg_we_12 = and(_T_629, picm_wren_ff) @[el2_pic_ctl.scala 161:153] - node _T_630 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] - node _T_631 = eq(_T_630, UInt<4>("h0d")) @[el2_pic_ctl.scala 161:139] - node _T_632 = and(addr_clear_gw_base_match, _T_631) @[el2_pic_ctl.scala 161:106] - node gw_clear_reg_we_13 = and(_T_632, picm_wren_ff) @[el2_pic_ctl.scala 161:153] - node _T_633 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] - node _T_634 = eq(_T_633, UInt<4>("h0e")) @[el2_pic_ctl.scala 161:139] - node _T_635 = and(addr_clear_gw_base_match, _T_634) @[el2_pic_ctl.scala 161:106] - node gw_clear_reg_we_14 = and(_T_635, picm_wren_ff) @[el2_pic_ctl.scala 161:153] - node _T_636 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] - node _T_637 = eq(_T_636, UInt<4>("h0f")) @[el2_pic_ctl.scala 161:139] - node _T_638 = and(addr_clear_gw_base_match, _T_637) @[el2_pic_ctl.scala 161:106] - node gw_clear_reg_we_15 = and(_T_638, picm_wren_ff) @[el2_pic_ctl.scala 161:153] - node _T_639 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] - node _T_640 = eq(_T_639, UInt<5>("h010")) @[el2_pic_ctl.scala 161:139] - node _T_641 = and(addr_clear_gw_base_match, _T_640) @[el2_pic_ctl.scala 161:106] - node gw_clear_reg_we_16 = and(_T_641, picm_wren_ff) @[el2_pic_ctl.scala 161:153] - node _T_642 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] - node _T_643 = eq(_T_642, UInt<5>("h011")) @[el2_pic_ctl.scala 161:139] - node _T_644 = and(addr_clear_gw_base_match, _T_643) @[el2_pic_ctl.scala 161:106] - node gw_clear_reg_we_17 = and(_T_644, picm_wren_ff) @[el2_pic_ctl.scala 161:153] - node _T_645 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] - node _T_646 = eq(_T_645, UInt<5>("h012")) @[el2_pic_ctl.scala 161:139] - node _T_647 = and(addr_clear_gw_base_match, _T_646) @[el2_pic_ctl.scala 161:106] - node gw_clear_reg_we_18 = and(_T_647, picm_wren_ff) @[el2_pic_ctl.scala 161:153] - node _T_648 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] - node _T_649 = eq(_T_648, UInt<5>("h013")) @[el2_pic_ctl.scala 161:139] - node _T_650 = and(addr_clear_gw_base_match, _T_649) @[el2_pic_ctl.scala 161:106] - node gw_clear_reg_we_19 = and(_T_650, picm_wren_ff) @[el2_pic_ctl.scala 161:153] - node _T_651 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] - node _T_652 = eq(_T_651, UInt<5>("h014")) @[el2_pic_ctl.scala 161:139] - node _T_653 = and(addr_clear_gw_base_match, _T_652) @[el2_pic_ctl.scala 161:106] - node gw_clear_reg_we_20 = and(_T_653, picm_wren_ff) @[el2_pic_ctl.scala 161:153] - node _T_654 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] - node _T_655 = eq(_T_654, UInt<5>("h015")) @[el2_pic_ctl.scala 161:139] - node _T_656 = and(addr_clear_gw_base_match, _T_655) @[el2_pic_ctl.scala 161:106] - node gw_clear_reg_we_21 = and(_T_656, picm_wren_ff) @[el2_pic_ctl.scala 161:153] - node _T_657 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] - node _T_658 = eq(_T_657, UInt<5>("h016")) @[el2_pic_ctl.scala 161:139] - node _T_659 = and(addr_clear_gw_base_match, _T_658) @[el2_pic_ctl.scala 161:106] - node gw_clear_reg_we_22 = and(_T_659, picm_wren_ff) @[el2_pic_ctl.scala 161:153] - node _T_660 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] - node _T_661 = eq(_T_660, UInt<5>("h017")) @[el2_pic_ctl.scala 161:139] - node _T_662 = and(addr_clear_gw_base_match, _T_661) @[el2_pic_ctl.scala 161:106] - node gw_clear_reg_we_23 = and(_T_662, picm_wren_ff) @[el2_pic_ctl.scala 161:153] - node _T_663 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] - node _T_664 = eq(_T_663, UInt<5>("h018")) @[el2_pic_ctl.scala 161:139] - node _T_665 = and(addr_clear_gw_base_match, _T_664) @[el2_pic_ctl.scala 161:106] - node gw_clear_reg_we_24 = and(_T_665, picm_wren_ff) @[el2_pic_ctl.scala 161:153] - node _T_666 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] - node _T_667 = eq(_T_666, UInt<5>("h019")) @[el2_pic_ctl.scala 161:139] - node _T_668 = and(addr_clear_gw_base_match, _T_667) @[el2_pic_ctl.scala 161:106] - node gw_clear_reg_we_25 = and(_T_668, picm_wren_ff) @[el2_pic_ctl.scala 161:153] - node _T_669 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] - node _T_670 = eq(_T_669, UInt<5>("h01a")) @[el2_pic_ctl.scala 161:139] - node _T_671 = and(addr_clear_gw_base_match, _T_670) @[el2_pic_ctl.scala 161:106] - node gw_clear_reg_we_26 = and(_T_671, picm_wren_ff) @[el2_pic_ctl.scala 161:153] - node _T_672 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] - node _T_673 = eq(_T_672, UInt<5>("h01b")) @[el2_pic_ctl.scala 161:139] - node _T_674 = and(addr_clear_gw_base_match, _T_673) @[el2_pic_ctl.scala 161:106] - node gw_clear_reg_we_27 = and(_T_674, picm_wren_ff) @[el2_pic_ctl.scala 161:153] - node _T_675 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] - node _T_676 = eq(_T_675, UInt<5>("h01c")) @[el2_pic_ctl.scala 161:139] - node _T_677 = and(addr_clear_gw_base_match, _T_676) @[el2_pic_ctl.scala 161:106] - node gw_clear_reg_we_28 = and(_T_677, picm_wren_ff) @[el2_pic_ctl.scala 161:153] - node _T_678 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] - node _T_679 = eq(_T_678, UInt<5>("h01d")) @[el2_pic_ctl.scala 161:139] - node _T_680 = and(addr_clear_gw_base_match, _T_679) @[el2_pic_ctl.scala 161:106] - node gw_clear_reg_we_29 = and(_T_680, picm_wren_ff) @[el2_pic_ctl.scala 161:153] - node _T_681 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] - node _T_682 = eq(_T_681, UInt<5>("h01e")) @[el2_pic_ctl.scala 161:139] - node _T_683 = and(addr_clear_gw_base_match, _T_682) @[el2_pic_ctl.scala 161:106] - node gw_clear_reg_we_30 = and(_T_683, picm_wren_ff) @[el2_pic_ctl.scala 161:153] - node _T_684 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] - node _T_685 = eq(_T_684, UInt<5>("h01f")) @[el2_pic_ctl.scala 161:139] - node _T_686 = and(addr_clear_gw_base_match, _T_685) @[el2_pic_ctl.scala 161:106] - node gw_clear_reg_we_31 = and(_T_686, picm_wren_ff) @[el2_pic_ctl.scala 161:153] - wire intpriority_reg : UInt<4>[32] @[el2_pic_ctl.scala 162:32] - intpriority_reg[0] <= UInt<4>("h00") @[el2_pic_ctl.scala 163:208] - node _T_687 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] - node _T_688 = bits(intpriority_reg_we_1, 0, 0) @[el2_pic_ctl.scala 163:174] + node _T_36 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 147:122] + node _T_37 = eq(_T_36, UInt<1>("h01")) @[el2_pic_ctl.scala 147:139] + node _T_38 = and(waddr_intpriority_base_match, _T_37) @[el2_pic_ctl.scala 147:106] + node intpriority_reg_we_1 = and(_T_38, picm_wren_ff) @[el2_pic_ctl.scala 147:153] + node _T_39 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 147:122] + node _T_40 = eq(_T_39, UInt<2>("h02")) @[el2_pic_ctl.scala 147:139] + node _T_41 = and(waddr_intpriority_base_match, _T_40) @[el2_pic_ctl.scala 147:106] + node intpriority_reg_we_2 = and(_T_41, picm_wren_ff) @[el2_pic_ctl.scala 147:153] + node _T_42 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 147:122] + node _T_43 = eq(_T_42, UInt<2>("h03")) @[el2_pic_ctl.scala 147:139] + node _T_44 = and(waddr_intpriority_base_match, _T_43) @[el2_pic_ctl.scala 147:106] + node intpriority_reg_we_3 = and(_T_44, picm_wren_ff) @[el2_pic_ctl.scala 147:153] + node _T_45 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 147:122] + node _T_46 = eq(_T_45, UInt<3>("h04")) @[el2_pic_ctl.scala 147:139] + node _T_47 = and(waddr_intpriority_base_match, _T_46) @[el2_pic_ctl.scala 147:106] + node intpriority_reg_we_4 = and(_T_47, picm_wren_ff) @[el2_pic_ctl.scala 147:153] + node _T_48 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 147:122] + node _T_49 = eq(_T_48, UInt<3>("h05")) @[el2_pic_ctl.scala 147:139] + node _T_50 = and(waddr_intpriority_base_match, _T_49) @[el2_pic_ctl.scala 147:106] + node intpriority_reg_we_5 = and(_T_50, picm_wren_ff) @[el2_pic_ctl.scala 147:153] + node _T_51 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 147:122] + node _T_52 = eq(_T_51, UInt<3>("h06")) @[el2_pic_ctl.scala 147:139] + node _T_53 = and(waddr_intpriority_base_match, _T_52) @[el2_pic_ctl.scala 147:106] + node intpriority_reg_we_6 = and(_T_53, picm_wren_ff) @[el2_pic_ctl.scala 147:153] + node _T_54 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 147:122] + node _T_55 = eq(_T_54, UInt<3>("h07")) @[el2_pic_ctl.scala 147:139] + node _T_56 = and(waddr_intpriority_base_match, _T_55) @[el2_pic_ctl.scala 147:106] + node intpriority_reg_we_7 = and(_T_56, picm_wren_ff) @[el2_pic_ctl.scala 147:153] + node _T_57 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 147:122] + node _T_58 = eq(_T_57, UInt<4>("h08")) @[el2_pic_ctl.scala 147:139] + node _T_59 = and(waddr_intpriority_base_match, _T_58) @[el2_pic_ctl.scala 147:106] + node intpriority_reg_we_8 = and(_T_59, picm_wren_ff) @[el2_pic_ctl.scala 147:153] + node _T_60 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 147:122] + node _T_61 = eq(_T_60, UInt<4>("h09")) @[el2_pic_ctl.scala 147:139] + node _T_62 = and(waddr_intpriority_base_match, _T_61) @[el2_pic_ctl.scala 147:106] + node intpriority_reg_we_9 = and(_T_62, picm_wren_ff) @[el2_pic_ctl.scala 147:153] + node _T_63 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 147:122] + node _T_64 = eq(_T_63, UInt<4>("h0a")) @[el2_pic_ctl.scala 147:139] + node _T_65 = and(waddr_intpriority_base_match, _T_64) @[el2_pic_ctl.scala 147:106] + node intpriority_reg_we_10 = and(_T_65, picm_wren_ff) @[el2_pic_ctl.scala 147:153] + node _T_66 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 147:122] + node _T_67 = eq(_T_66, UInt<4>("h0b")) @[el2_pic_ctl.scala 147:139] + node _T_68 = and(waddr_intpriority_base_match, _T_67) @[el2_pic_ctl.scala 147:106] + node intpriority_reg_we_11 = and(_T_68, picm_wren_ff) @[el2_pic_ctl.scala 147:153] + node _T_69 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 147:122] + node _T_70 = eq(_T_69, UInt<4>("h0c")) @[el2_pic_ctl.scala 147:139] + node _T_71 = and(waddr_intpriority_base_match, _T_70) @[el2_pic_ctl.scala 147:106] + node intpriority_reg_we_12 = and(_T_71, picm_wren_ff) @[el2_pic_ctl.scala 147:153] + node _T_72 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 147:122] + node _T_73 = eq(_T_72, UInt<4>("h0d")) @[el2_pic_ctl.scala 147:139] + node _T_74 = and(waddr_intpriority_base_match, _T_73) @[el2_pic_ctl.scala 147:106] + node intpriority_reg_we_13 = and(_T_74, picm_wren_ff) @[el2_pic_ctl.scala 147:153] + node _T_75 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 147:122] + node _T_76 = eq(_T_75, UInt<4>("h0e")) @[el2_pic_ctl.scala 147:139] + node _T_77 = and(waddr_intpriority_base_match, _T_76) @[el2_pic_ctl.scala 147:106] + node intpriority_reg_we_14 = and(_T_77, picm_wren_ff) @[el2_pic_ctl.scala 147:153] + node _T_78 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 147:122] + node _T_79 = eq(_T_78, UInt<4>("h0f")) @[el2_pic_ctl.scala 147:139] + node _T_80 = and(waddr_intpriority_base_match, _T_79) @[el2_pic_ctl.scala 147:106] + node intpriority_reg_we_15 = and(_T_80, picm_wren_ff) @[el2_pic_ctl.scala 147:153] + node _T_81 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 147:122] + node _T_82 = eq(_T_81, UInt<5>("h010")) @[el2_pic_ctl.scala 147:139] + node _T_83 = and(waddr_intpriority_base_match, _T_82) @[el2_pic_ctl.scala 147:106] + node intpriority_reg_we_16 = and(_T_83, picm_wren_ff) @[el2_pic_ctl.scala 147:153] + node _T_84 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 147:122] + node _T_85 = eq(_T_84, UInt<5>("h011")) @[el2_pic_ctl.scala 147:139] + node _T_86 = and(waddr_intpriority_base_match, _T_85) @[el2_pic_ctl.scala 147:106] + node intpriority_reg_we_17 = and(_T_86, picm_wren_ff) @[el2_pic_ctl.scala 147:153] + node _T_87 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 147:122] + node _T_88 = eq(_T_87, UInt<5>("h012")) @[el2_pic_ctl.scala 147:139] + node _T_89 = and(waddr_intpriority_base_match, _T_88) @[el2_pic_ctl.scala 147:106] + node intpriority_reg_we_18 = and(_T_89, picm_wren_ff) @[el2_pic_ctl.scala 147:153] + node _T_90 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 147:122] + node _T_91 = eq(_T_90, UInt<5>("h013")) @[el2_pic_ctl.scala 147:139] + node _T_92 = and(waddr_intpriority_base_match, _T_91) @[el2_pic_ctl.scala 147:106] + node intpriority_reg_we_19 = and(_T_92, picm_wren_ff) @[el2_pic_ctl.scala 147:153] + node _T_93 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 147:122] + node _T_94 = eq(_T_93, UInt<5>("h014")) @[el2_pic_ctl.scala 147:139] + node _T_95 = and(waddr_intpriority_base_match, _T_94) @[el2_pic_ctl.scala 147:106] + node intpriority_reg_we_20 = and(_T_95, picm_wren_ff) @[el2_pic_ctl.scala 147:153] + node _T_96 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 147:122] + node _T_97 = eq(_T_96, UInt<5>("h015")) @[el2_pic_ctl.scala 147:139] + node _T_98 = and(waddr_intpriority_base_match, _T_97) @[el2_pic_ctl.scala 147:106] + node intpriority_reg_we_21 = and(_T_98, picm_wren_ff) @[el2_pic_ctl.scala 147:153] + node _T_99 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 147:122] + node _T_100 = eq(_T_99, UInt<5>("h016")) @[el2_pic_ctl.scala 147:139] + node _T_101 = and(waddr_intpriority_base_match, _T_100) @[el2_pic_ctl.scala 147:106] + node intpriority_reg_we_22 = and(_T_101, picm_wren_ff) @[el2_pic_ctl.scala 147:153] + node _T_102 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 147:122] + node _T_103 = eq(_T_102, UInt<5>("h017")) @[el2_pic_ctl.scala 147:139] + node _T_104 = and(waddr_intpriority_base_match, _T_103) @[el2_pic_ctl.scala 147:106] + node intpriority_reg_we_23 = and(_T_104, picm_wren_ff) @[el2_pic_ctl.scala 147:153] + node _T_105 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 147:122] + node _T_106 = eq(_T_105, UInt<5>("h018")) @[el2_pic_ctl.scala 147:139] + node _T_107 = and(waddr_intpriority_base_match, _T_106) @[el2_pic_ctl.scala 147:106] + node intpriority_reg_we_24 = and(_T_107, picm_wren_ff) @[el2_pic_ctl.scala 147:153] + node _T_108 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 147:122] + node _T_109 = eq(_T_108, UInt<5>("h019")) @[el2_pic_ctl.scala 147:139] + node _T_110 = and(waddr_intpriority_base_match, _T_109) @[el2_pic_ctl.scala 147:106] + node intpriority_reg_we_25 = and(_T_110, picm_wren_ff) @[el2_pic_ctl.scala 147:153] + node _T_111 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 147:122] + node _T_112 = eq(_T_111, UInt<5>("h01a")) @[el2_pic_ctl.scala 147:139] + node _T_113 = and(waddr_intpriority_base_match, _T_112) @[el2_pic_ctl.scala 147:106] + node intpriority_reg_we_26 = and(_T_113, picm_wren_ff) @[el2_pic_ctl.scala 147:153] + node _T_114 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 147:122] + node _T_115 = eq(_T_114, UInt<5>("h01b")) @[el2_pic_ctl.scala 147:139] + node _T_116 = and(waddr_intpriority_base_match, _T_115) @[el2_pic_ctl.scala 147:106] + node intpriority_reg_we_27 = and(_T_116, picm_wren_ff) @[el2_pic_ctl.scala 147:153] + node _T_117 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 147:122] + node _T_118 = eq(_T_117, UInt<5>("h01c")) @[el2_pic_ctl.scala 147:139] + node _T_119 = and(waddr_intpriority_base_match, _T_118) @[el2_pic_ctl.scala 147:106] + node intpriority_reg_we_28 = and(_T_119, picm_wren_ff) @[el2_pic_ctl.scala 147:153] + node _T_120 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 147:122] + node _T_121 = eq(_T_120, UInt<5>("h01d")) @[el2_pic_ctl.scala 147:139] + node _T_122 = and(waddr_intpriority_base_match, _T_121) @[el2_pic_ctl.scala 147:106] + node intpriority_reg_we_29 = and(_T_122, picm_wren_ff) @[el2_pic_ctl.scala 147:153] + node _T_123 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 147:122] + node _T_124 = eq(_T_123, UInt<5>("h01e")) @[el2_pic_ctl.scala 147:139] + node _T_125 = and(waddr_intpriority_base_match, _T_124) @[el2_pic_ctl.scala 147:106] + node intpriority_reg_we_30 = and(_T_125, picm_wren_ff) @[el2_pic_ctl.scala 147:153] + node _T_126 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 147:122] + node _T_127 = eq(_T_126, UInt<5>("h01f")) @[el2_pic_ctl.scala 147:139] + node _T_128 = and(waddr_intpriority_base_match, _T_127) @[el2_pic_ctl.scala 147:106] + node intpriority_reg_we_31 = and(_T_128, picm_wren_ff) @[el2_pic_ctl.scala 147:153] + node _T_129 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 148:122] + node _T_130 = eq(_T_129, UInt<1>("h01")) @[el2_pic_ctl.scala 148:139] + node _T_131 = and(raddr_intpriority_base_match, _T_130) @[el2_pic_ctl.scala 148:106] + node intpriority_reg_re_1 = and(_T_131, picm_rden_ff) @[el2_pic_ctl.scala 148:153] + node _T_132 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 148:122] + node _T_133 = eq(_T_132, UInt<2>("h02")) @[el2_pic_ctl.scala 148:139] + node _T_134 = and(raddr_intpriority_base_match, _T_133) @[el2_pic_ctl.scala 148:106] + node intpriority_reg_re_2 = and(_T_134, picm_rden_ff) @[el2_pic_ctl.scala 148:153] + node _T_135 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 148:122] + node _T_136 = eq(_T_135, UInt<2>("h03")) @[el2_pic_ctl.scala 148:139] + node _T_137 = and(raddr_intpriority_base_match, _T_136) @[el2_pic_ctl.scala 148:106] + node intpriority_reg_re_3 = and(_T_137, picm_rden_ff) @[el2_pic_ctl.scala 148:153] + node _T_138 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 148:122] + node _T_139 = eq(_T_138, UInt<3>("h04")) @[el2_pic_ctl.scala 148:139] + node _T_140 = and(raddr_intpriority_base_match, _T_139) @[el2_pic_ctl.scala 148:106] + node intpriority_reg_re_4 = and(_T_140, picm_rden_ff) @[el2_pic_ctl.scala 148:153] + node _T_141 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 148:122] + node _T_142 = eq(_T_141, UInt<3>("h05")) @[el2_pic_ctl.scala 148:139] + node _T_143 = and(raddr_intpriority_base_match, _T_142) @[el2_pic_ctl.scala 148:106] + node intpriority_reg_re_5 = and(_T_143, picm_rden_ff) @[el2_pic_ctl.scala 148:153] + node _T_144 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 148:122] + node _T_145 = eq(_T_144, UInt<3>("h06")) @[el2_pic_ctl.scala 148:139] + node _T_146 = and(raddr_intpriority_base_match, _T_145) @[el2_pic_ctl.scala 148:106] + node intpriority_reg_re_6 = and(_T_146, picm_rden_ff) @[el2_pic_ctl.scala 148:153] + node _T_147 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 148:122] + node _T_148 = eq(_T_147, UInt<3>("h07")) @[el2_pic_ctl.scala 148:139] + node _T_149 = and(raddr_intpriority_base_match, _T_148) @[el2_pic_ctl.scala 148:106] + node intpriority_reg_re_7 = and(_T_149, picm_rden_ff) @[el2_pic_ctl.scala 148:153] + node _T_150 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 148:122] + node _T_151 = eq(_T_150, UInt<4>("h08")) @[el2_pic_ctl.scala 148:139] + node _T_152 = and(raddr_intpriority_base_match, _T_151) @[el2_pic_ctl.scala 148:106] + node intpriority_reg_re_8 = and(_T_152, picm_rden_ff) @[el2_pic_ctl.scala 148:153] + node _T_153 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 148:122] + node _T_154 = eq(_T_153, UInt<4>("h09")) @[el2_pic_ctl.scala 148:139] + node _T_155 = and(raddr_intpriority_base_match, _T_154) @[el2_pic_ctl.scala 148:106] + node intpriority_reg_re_9 = and(_T_155, picm_rden_ff) @[el2_pic_ctl.scala 148:153] + node _T_156 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 148:122] + node _T_157 = eq(_T_156, UInt<4>("h0a")) @[el2_pic_ctl.scala 148:139] + node _T_158 = and(raddr_intpriority_base_match, _T_157) @[el2_pic_ctl.scala 148:106] + node intpriority_reg_re_10 = and(_T_158, picm_rden_ff) @[el2_pic_ctl.scala 148:153] + node _T_159 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 148:122] + node _T_160 = eq(_T_159, UInt<4>("h0b")) @[el2_pic_ctl.scala 148:139] + node _T_161 = and(raddr_intpriority_base_match, _T_160) @[el2_pic_ctl.scala 148:106] + node intpriority_reg_re_11 = and(_T_161, picm_rden_ff) @[el2_pic_ctl.scala 148:153] + node _T_162 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 148:122] + node _T_163 = eq(_T_162, UInt<4>("h0c")) @[el2_pic_ctl.scala 148:139] + node _T_164 = and(raddr_intpriority_base_match, _T_163) @[el2_pic_ctl.scala 148:106] + node intpriority_reg_re_12 = and(_T_164, picm_rden_ff) @[el2_pic_ctl.scala 148:153] + node _T_165 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 148:122] + node _T_166 = eq(_T_165, UInt<4>("h0d")) @[el2_pic_ctl.scala 148:139] + node _T_167 = and(raddr_intpriority_base_match, _T_166) @[el2_pic_ctl.scala 148:106] + node intpriority_reg_re_13 = and(_T_167, picm_rden_ff) @[el2_pic_ctl.scala 148:153] + node _T_168 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 148:122] + node _T_169 = eq(_T_168, UInt<4>("h0e")) @[el2_pic_ctl.scala 148:139] + node _T_170 = and(raddr_intpriority_base_match, _T_169) @[el2_pic_ctl.scala 148:106] + node intpriority_reg_re_14 = and(_T_170, picm_rden_ff) @[el2_pic_ctl.scala 148:153] + node _T_171 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 148:122] + node _T_172 = eq(_T_171, UInt<4>("h0f")) @[el2_pic_ctl.scala 148:139] + node _T_173 = and(raddr_intpriority_base_match, _T_172) @[el2_pic_ctl.scala 148:106] + node intpriority_reg_re_15 = and(_T_173, picm_rden_ff) @[el2_pic_ctl.scala 148:153] + node _T_174 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 148:122] + node _T_175 = eq(_T_174, UInt<5>("h010")) @[el2_pic_ctl.scala 148:139] + node _T_176 = and(raddr_intpriority_base_match, _T_175) @[el2_pic_ctl.scala 148:106] + node intpriority_reg_re_16 = and(_T_176, picm_rden_ff) @[el2_pic_ctl.scala 148:153] + node _T_177 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 148:122] + node _T_178 = eq(_T_177, UInt<5>("h011")) @[el2_pic_ctl.scala 148:139] + node _T_179 = and(raddr_intpriority_base_match, _T_178) @[el2_pic_ctl.scala 148:106] + node intpriority_reg_re_17 = and(_T_179, picm_rden_ff) @[el2_pic_ctl.scala 148:153] + node _T_180 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 148:122] + node _T_181 = eq(_T_180, UInt<5>("h012")) @[el2_pic_ctl.scala 148:139] + node _T_182 = and(raddr_intpriority_base_match, _T_181) @[el2_pic_ctl.scala 148:106] + node intpriority_reg_re_18 = and(_T_182, picm_rden_ff) @[el2_pic_ctl.scala 148:153] + node _T_183 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 148:122] + node _T_184 = eq(_T_183, UInt<5>("h013")) @[el2_pic_ctl.scala 148:139] + node _T_185 = and(raddr_intpriority_base_match, _T_184) @[el2_pic_ctl.scala 148:106] + node intpriority_reg_re_19 = and(_T_185, picm_rden_ff) @[el2_pic_ctl.scala 148:153] + node _T_186 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 148:122] + node _T_187 = eq(_T_186, UInt<5>("h014")) @[el2_pic_ctl.scala 148:139] + node _T_188 = and(raddr_intpriority_base_match, _T_187) @[el2_pic_ctl.scala 148:106] + node intpriority_reg_re_20 = and(_T_188, picm_rden_ff) @[el2_pic_ctl.scala 148:153] + node _T_189 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 148:122] + node _T_190 = eq(_T_189, UInt<5>("h015")) @[el2_pic_ctl.scala 148:139] + node _T_191 = and(raddr_intpriority_base_match, _T_190) @[el2_pic_ctl.scala 148:106] + node intpriority_reg_re_21 = and(_T_191, picm_rden_ff) @[el2_pic_ctl.scala 148:153] + node _T_192 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 148:122] + node _T_193 = eq(_T_192, UInt<5>("h016")) @[el2_pic_ctl.scala 148:139] + node _T_194 = and(raddr_intpriority_base_match, _T_193) @[el2_pic_ctl.scala 148:106] + node intpriority_reg_re_22 = and(_T_194, picm_rden_ff) @[el2_pic_ctl.scala 148:153] + node _T_195 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 148:122] + node _T_196 = eq(_T_195, UInt<5>("h017")) @[el2_pic_ctl.scala 148:139] + node _T_197 = and(raddr_intpriority_base_match, _T_196) @[el2_pic_ctl.scala 148:106] + node intpriority_reg_re_23 = and(_T_197, picm_rden_ff) @[el2_pic_ctl.scala 148:153] + node _T_198 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 148:122] + node _T_199 = eq(_T_198, UInt<5>("h018")) @[el2_pic_ctl.scala 148:139] + node _T_200 = and(raddr_intpriority_base_match, _T_199) @[el2_pic_ctl.scala 148:106] + node intpriority_reg_re_24 = and(_T_200, picm_rden_ff) @[el2_pic_ctl.scala 148:153] + node _T_201 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 148:122] + node _T_202 = eq(_T_201, UInt<5>("h019")) @[el2_pic_ctl.scala 148:139] + node _T_203 = and(raddr_intpriority_base_match, _T_202) @[el2_pic_ctl.scala 148:106] + node intpriority_reg_re_25 = and(_T_203, picm_rden_ff) @[el2_pic_ctl.scala 148:153] + node _T_204 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 148:122] + node _T_205 = eq(_T_204, UInt<5>("h01a")) @[el2_pic_ctl.scala 148:139] + node _T_206 = and(raddr_intpriority_base_match, _T_205) @[el2_pic_ctl.scala 148:106] + node intpriority_reg_re_26 = and(_T_206, picm_rden_ff) @[el2_pic_ctl.scala 148:153] + node _T_207 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 148:122] + node _T_208 = eq(_T_207, UInt<5>("h01b")) @[el2_pic_ctl.scala 148:139] + node _T_209 = and(raddr_intpriority_base_match, _T_208) @[el2_pic_ctl.scala 148:106] + node intpriority_reg_re_27 = and(_T_209, picm_rden_ff) @[el2_pic_ctl.scala 148:153] + node _T_210 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 148:122] + node _T_211 = eq(_T_210, UInt<5>("h01c")) @[el2_pic_ctl.scala 148:139] + node _T_212 = and(raddr_intpriority_base_match, _T_211) @[el2_pic_ctl.scala 148:106] + node intpriority_reg_re_28 = and(_T_212, picm_rden_ff) @[el2_pic_ctl.scala 148:153] + node _T_213 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 148:122] + node _T_214 = eq(_T_213, UInt<5>("h01d")) @[el2_pic_ctl.scala 148:139] + node _T_215 = and(raddr_intpriority_base_match, _T_214) @[el2_pic_ctl.scala 148:106] + node intpriority_reg_re_29 = and(_T_215, picm_rden_ff) @[el2_pic_ctl.scala 148:153] + node _T_216 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 148:122] + node _T_217 = eq(_T_216, UInt<5>("h01e")) @[el2_pic_ctl.scala 148:139] + node _T_218 = and(raddr_intpriority_base_match, _T_217) @[el2_pic_ctl.scala 148:106] + node intpriority_reg_re_30 = and(_T_218, picm_rden_ff) @[el2_pic_ctl.scala 148:153] + node _T_219 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 148:122] + node _T_220 = eq(_T_219, UInt<5>("h01f")) @[el2_pic_ctl.scala 148:139] + node _T_221 = and(raddr_intpriority_base_match, _T_220) @[el2_pic_ctl.scala 148:106] + node intpriority_reg_re_31 = and(_T_221, picm_rden_ff) @[el2_pic_ctl.scala 148:153] + node _T_222 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 149:122] + node _T_223 = eq(_T_222, UInt<1>("h01")) @[el2_pic_ctl.scala 149:139] + node _T_224 = and(waddr_intenable_base_match, _T_223) @[el2_pic_ctl.scala 149:106] + node intenable_reg_we_1 = and(_T_224, picm_wren_ff) @[el2_pic_ctl.scala 149:153] + node _T_225 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 149:122] + node _T_226 = eq(_T_225, UInt<2>("h02")) @[el2_pic_ctl.scala 149:139] + node _T_227 = and(waddr_intenable_base_match, _T_226) @[el2_pic_ctl.scala 149:106] + node intenable_reg_we_2 = and(_T_227, picm_wren_ff) @[el2_pic_ctl.scala 149:153] + node _T_228 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 149:122] + node _T_229 = eq(_T_228, UInt<2>("h03")) @[el2_pic_ctl.scala 149:139] + node _T_230 = and(waddr_intenable_base_match, _T_229) @[el2_pic_ctl.scala 149:106] + node intenable_reg_we_3 = and(_T_230, picm_wren_ff) @[el2_pic_ctl.scala 149:153] + node _T_231 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 149:122] + node _T_232 = eq(_T_231, UInt<3>("h04")) @[el2_pic_ctl.scala 149:139] + node _T_233 = and(waddr_intenable_base_match, _T_232) @[el2_pic_ctl.scala 149:106] + node intenable_reg_we_4 = and(_T_233, picm_wren_ff) @[el2_pic_ctl.scala 149:153] + node _T_234 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 149:122] + node _T_235 = eq(_T_234, UInt<3>("h05")) @[el2_pic_ctl.scala 149:139] + node _T_236 = and(waddr_intenable_base_match, _T_235) @[el2_pic_ctl.scala 149:106] + node intenable_reg_we_5 = and(_T_236, picm_wren_ff) @[el2_pic_ctl.scala 149:153] + node _T_237 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 149:122] + node _T_238 = eq(_T_237, UInt<3>("h06")) @[el2_pic_ctl.scala 149:139] + node _T_239 = and(waddr_intenable_base_match, _T_238) @[el2_pic_ctl.scala 149:106] + node intenable_reg_we_6 = and(_T_239, picm_wren_ff) @[el2_pic_ctl.scala 149:153] + node _T_240 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 149:122] + node _T_241 = eq(_T_240, UInt<3>("h07")) @[el2_pic_ctl.scala 149:139] + node _T_242 = and(waddr_intenable_base_match, _T_241) @[el2_pic_ctl.scala 149:106] + node intenable_reg_we_7 = and(_T_242, picm_wren_ff) @[el2_pic_ctl.scala 149:153] + node _T_243 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 149:122] + node _T_244 = eq(_T_243, UInt<4>("h08")) @[el2_pic_ctl.scala 149:139] + node _T_245 = and(waddr_intenable_base_match, _T_244) @[el2_pic_ctl.scala 149:106] + node intenable_reg_we_8 = and(_T_245, picm_wren_ff) @[el2_pic_ctl.scala 149:153] + node _T_246 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 149:122] + node _T_247 = eq(_T_246, UInt<4>("h09")) @[el2_pic_ctl.scala 149:139] + node _T_248 = and(waddr_intenable_base_match, _T_247) @[el2_pic_ctl.scala 149:106] + node intenable_reg_we_9 = and(_T_248, picm_wren_ff) @[el2_pic_ctl.scala 149:153] + node _T_249 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 149:122] + node _T_250 = eq(_T_249, UInt<4>("h0a")) @[el2_pic_ctl.scala 149:139] + node _T_251 = and(waddr_intenable_base_match, _T_250) @[el2_pic_ctl.scala 149:106] + node intenable_reg_we_10 = and(_T_251, picm_wren_ff) @[el2_pic_ctl.scala 149:153] + node _T_252 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 149:122] + node _T_253 = eq(_T_252, UInt<4>("h0b")) @[el2_pic_ctl.scala 149:139] + node _T_254 = and(waddr_intenable_base_match, _T_253) @[el2_pic_ctl.scala 149:106] + node intenable_reg_we_11 = and(_T_254, picm_wren_ff) @[el2_pic_ctl.scala 149:153] + node _T_255 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 149:122] + node _T_256 = eq(_T_255, UInt<4>("h0c")) @[el2_pic_ctl.scala 149:139] + node _T_257 = and(waddr_intenable_base_match, _T_256) @[el2_pic_ctl.scala 149:106] + node intenable_reg_we_12 = and(_T_257, picm_wren_ff) @[el2_pic_ctl.scala 149:153] + node _T_258 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 149:122] + node _T_259 = eq(_T_258, UInt<4>("h0d")) @[el2_pic_ctl.scala 149:139] + node _T_260 = and(waddr_intenable_base_match, _T_259) @[el2_pic_ctl.scala 149:106] + node intenable_reg_we_13 = and(_T_260, picm_wren_ff) @[el2_pic_ctl.scala 149:153] + node _T_261 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 149:122] + node _T_262 = eq(_T_261, UInt<4>("h0e")) @[el2_pic_ctl.scala 149:139] + node _T_263 = and(waddr_intenable_base_match, _T_262) @[el2_pic_ctl.scala 149:106] + node intenable_reg_we_14 = and(_T_263, picm_wren_ff) @[el2_pic_ctl.scala 149:153] + node _T_264 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 149:122] + node _T_265 = eq(_T_264, UInt<4>("h0f")) @[el2_pic_ctl.scala 149:139] + node _T_266 = and(waddr_intenable_base_match, _T_265) @[el2_pic_ctl.scala 149:106] + node intenable_reg_we_15 = and(_T_266, picm_wren_ff) @[el2_pic_ctl.scala 149:153] + node _T_267 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 149:122] + node _T_268 = eq(_T_267, UInt<5>("h010")) @[el2_pic_ctl.scala 149:139] + node _T_269 = and(waddr_intenable_base_match, _T_268) @[el2_pic_ctl.scala 149:106] + node intenable_reg_we_16 = and(_T_269, picm_wren_ff) @[el2_pic_ctl.scala 149:153] + node _T_270 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 149:122] + node _T_271 = eq(_T_270, UInt<5>("h011")) @[el2_pic_ctl.scala 149:139] + node _T_272 = and(waddr_intenable_base_match, _T_271) @[el2_pic_ctl.scala 149:106] + node intenable_reg_we_17 = and(_T_272, picm_wren_ff) @[el2_pic_ctl.scala 149:153] + node _T_273 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 149:122] + node _T_274 = eq(_T_273, UInt<5>("h012")) @[el2_pic_ctl.scala 149:139] + node _T_275 = and(waddr_intenable_base_match, _T_274) @[el2_pic_ctl.scala 149:106] + node intenable_reg_we_18 = and(_T_275, picm_wren_ff) @[el2_pic_ctl.scala 149:153] + node _T_276 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 149:122] + node _T_277 = eq(_T_276, UInt<5>("h013")) @[el2_pic_ctl.scala 149:139] + node _T_278 = and(waddr_intenable_base_match, _T_277) @[el2_pic_ctl.scala 149:106] + node intenable_reg_we_19 = and(_T_278, picm_wren_ff) @[el2_pic_ctl.scala 149:153] + node _T_279 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 149:122] + node _T_280 = eq(_T_279, UInt<5>("h014")) @[el2_pic_ctl.scala 149:139] + node _T_281 = and(waddr_intenable_base_match, _T_280) @[el2_pic_ctl.scala 149:106] + node intenable_reg_we_20 = and(_T_281, picm_wren_ff) @[el2_pic_ctl.scala 149:153] + node _T_282 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 149:122] + node _T_283 = eq(_T_282, UInt<5>("h015")) @[el2_pic_ctl.scala 149:139] + node _T_284 = and(waddr_intenable_base_match, _T_283) @[el2_pic_ctl.scala 149:106] + node intenable_reg_we_21 = and(_T_284, picm_wren_ff) @[el2_pic_ctl.scala 149:153] + node _T_285 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 149:122] + node _T_286 = eq(_T_285, UInt<5>("h016")) @[el2_pic_ctl.scala 149:139] + node _T_287 = and(waddr_intenable_base_match, _T_286) @[el2_pic_ctl.scala 149:106] + node intenable_reg_we_22 = and(_T_287, picm_wren_ff) @[el2_pic_ctl.scala 149:153] + node _T_288 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 149:122] + node _T_289 = eq(_T_288, UInt<5>("h017")) @[el2_pic_ctl.scala 149:139] + node _T_290 = and(waddr_intenable_base_match, _T_289) @[el2_pic_ctl.scala 149:106] + node intenable_reg_we_23 = and(_T_290, picm_wren_ff) @[el2_pic_ctl.scala 149:153] + node _T_291 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 149:122] + node _T_292 = eq(_T_291, UInt<5>("h018")) @[el2_pic_ctl.scala 149:139] + node _T_293 = and(waddr_intenable_base_match, _T_292) @[el2_pic_ctl.scala 149:106] + node intenable_reg_we_24 = and(_T_293, picm_wren_ff) @[el2_pic_ctl.scala 149:153] + node _T_294 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 149:122] + node _T_295 = eq(_T_294, UInt<5>("h019")) @[el2_pic_ctl.scala 149:139] + node _T_296 = and(waddr_intenable_base_match, _T_295) @[el2_pic_ctl.scala 149:106] + node intenable_reg_we_25 = and(_T_296, picm_wren_ff) @[el2_pic_ctl.scala 149:153] + node _T_297 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 149:122] + node _T_298 = eq(_T_297, UInt<5>("h01a")) @[el2_pic_ctl.scala 149:139] + node _T_299 = and(waddr_intenable_base_match, _T_298) @[el2_pic_ctl.scala 149:106] + node intenable_reg_we_26 = and(_T_299, picm_wren_ff) @[el2_pic_ctl.scala 149:153] + node _T_300 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 149:122] + node _T_301 = eq(_T_300, UInt<5>("h01b")) @[el2_pic_ctl.scala 149:139] + node _T_302 = and(waddr_intenable_base_match, _T_301) @[el2_pic_ctl.scala 149:106] + node intenable_reg_we_27 = and(_T_302, picm_wren_ff) @[el2_pic_ctl.scala 149:153] + node _T_303 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 149:122] + node _T_304 = eq(_T_303, UInt<5>("h01c")) @[el2_pic_ctl.scala 149:139] + node _T_305 = and(waddr_intenable_base_match, _T_304) @[el2_pic_ctl.scala 149:106] + node intenable_reg_we_28 = and(_T_305, picm_wren_ff) @[el2_pic_ctl.scala 149:153] + node _T_306 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 149:122] + node _T_307 = eq(_T_306, UInt<5>("h01d")) @[el2_pic_ctl.scala 149:139] + node _T_308 = and(waddr_intenable_base_match, _T_307) @[el2_pic_ctl.scala 149:106] + node intenable_reg_we_29 = and(_T_308, picm_wren_ff) @[el2_pic_ctl.scala 149:153] + node _T_309 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 149:122] + node _T_310 = eq(_T_309, UInt<5>("h01e")) @[el2_pic_ctl.scala 149:139] + node _T_311 = and(waddr_intenable_base_match, _T_310) @[el2_pic_ctl.scala 149:106] + node intenable_reg_we_30 = and(_T_311, picm_wren_ff) @[el2_pic_ctl.scala 149:153] + node _T_312 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 149:122] + node _T_313 = eq(_T_312, UInt<5>("h01f")) @[el2_pic_ctl.scala 149:139] + node _T_314 = and(waddr_intenable_base_match, _T_313) @[el2_pic_ctl.scala 149:106] + node intenable_reg_we_31 = and(_T_314, picm_wren_ff) @[el2_pic_ctl.scala 149:153] + node _T_315 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 150:122] + node _T_316 = eq(_T_315, UInt<1>("h01")) @[el2_pic_ctl.scala 150:139] + node _T_317 = and(raddr_intenable_base_match, _T_316) @[el2_pic_ctl.scala 150:106] + node intenable_reg_re_1 = and(_T_317, picm_rden_ff) @[el2_pic_ctl.scala 150:153] + node _T_318 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 150:122] + node _T_319 = eq(_T_318, UInt<2>("h02")) @[el2_pic_ctl.scala 150:139] + node _T_320 = and(raddr_intenable_base_match, _T_319) @[el2_pic_ctl.scala 150:106] + node intenable_reg_re_2 = and(_T_320, picm_rden_ff) @[el2_pic_ctl.scala 150:153] + node _T_321 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 150:122] + node _T_322 = eq(_T_321, UInt<2>("h03")) @[el2_pic_ctl.scala 150:139] + node _T_323 = and(raddr_intenable_base_match, _T_322) @[el2_pic_ctl.scala 150:106] + node intenable_reg_re_3 = and(_T_323, picm_rden_ff) @[el2_pic_ctl.scala 150:153] + node _T_324 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 150:122] + node _T_325 = eq(_T_324, UInt<3>("h04")) @[el2_pic_ctl.scala 150:139] + node _T_326 = and(raddr_intenable_base_match, _T_325) @[el2_pic_ctl.scala 150:106] + node intenable_reg_re_4 = and(_T_326, picm_rden_ff) @[el2_pic_ctl.scala 150:153] + node _T_327 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 150:122] + node _T_328 = eq(_T_327, UInt<3>("h05")) @[el2_pic_ctl.scala 150:139] + node _T_329 = and(raddr_intenable_base_match, _T_328) @[el2_pic_ctl.scala 150:106] + node intenable_reg_re_5 = and(_T_329, picm_rden_ff) @[el2_pic_ctl.scala 150:153] + node _T_330 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 150:122] + node _T_331 = eq(_T_330, UInt<3>("h06")) @[el2_pic_ctl.scala 150:139] + node _T_332 = and(raddr_intenable_base_match, _T_331) @[el2_pic_ctl.scala 150:106] + node intenable_reg_re_6 = and(_T_332, picm_rden_ff) @[el2_pic_ctl.scala 150:153] + node _T_333 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 150:122] + node _T_334 = eq(_T_333, UInt<3>("h07")) @[el2_pic_ctl.scala 150:139] + node _T_335 = and(raddr_intenable_base_match, _T_334) @[el2_pic_ctl.scala 150:106] + node intenable_reg_re_7 = and(_T_335, picm_rden_ff) @[el2_pic_ctl.scala 150:153] + node _T_336 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 150:122] + node _T_337 = eq(_T_336, UInt<4>("h08")) @[el2_pic_ctl.scala 150:139] + node _T_338 = and(raddr_intenable_base_match, _T_337) @[el2_pic_ctl.scala 150:106] + node intenable_reg_re_8 = and(_T_338, picm_rden_ff) @[el2_pic_ctl.scala 150:153] + node _T_339 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 150:122] + node _T_340 = eq(_T_339, UInt<4>("h09")) @[el2_pic_ctl.scala 150:139] + node _T_341 = and(raddr_intenable_base_match, _T_340) @[el2_pic_ctl.scala 150:106] + node intenable_reg_re_9 = and(_T_341, picm_rden_ff) @[el2_pic_ctl.scala 150:153] + node _T_342 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 150:122] + node _T_343 = eq(_T_342, UInt<4>("h0a")) @[el2_pic_ctl.scala 150:139] + node _T_344 = and(raddr_intenable_base_match, _T_343) @[el2_pic_ctl.scala 150:106] + node intenable_reg_re_10 = and(_T_344, picm_rden_ff) @[el2_pic_ctl.scala 150:153] + node _T_345 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 150:122] + node _T_346 = eq(_T_345, UInt<4>("h0b")) @[el2_pic_ctl.scala 150:139] + node _T_347 = and(raddr_intenable_base_match, _T_346) @[el2_pic_ctl.scala 150:106] + node intenable_reg_re_11 = and(_T_347, picm_rden_ff) @[el2_pic_ctl.scala 150:153] + node _T_348 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 150:122] + node _T_349 = eq(_T_348, UInt<4>("h0c")) @[el2_pic_ctl.scala 150:139] + node _T_350 = and(raddr_intenable_base_match, _T_349) @[el2_pic_ctl.scala 150:106] + node intenable_reg_re_12 = and(_T_350, picm_rden_ff) @[el2_pic_ctl.scala 150:153] + node _T_351 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 150:122] + node _T_352 = eq(_T_351, UInt<4>("h0d")) @[el2_pic_ctl.scala 150:139] + node _T_353 = and(raddr_intenable_base_match, _T_352) @[el2_pic_ctl.scala 150:106] + node intenable_reg_re_13 = and(_T_353, picm_rden_ff) @[el2_pic_ctl.scala 150:153] + node _T_354 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 150:122] + node _T_355 = eq(_T_354, UInt<4>("h0e")) @[el2_pic_ctl.scala 150:139] + node _T_356 = and(raddr_intenable_base_match, _T_355) @[el2_pic_ctl.scala 150:106] + node intenable_reg_re_14 = and(_T_356, picm_rden_ff) @[el2_pic_ctl.scala 150:153] + node _T_357 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 150:122] + node _T_358 = eq(_T_357, UInt<4>("h0f")) @[el2_pic_ctl.scala 150:139] + node _T_359 = and(raddr_intenable_base_match, _T_358) @[el2_pic_ctl.scala 150:106] + node intenable_reg_re_15 = and(_T_359, picm_rden_ff) @[el2_pic_ctl.scala 150:153] + node _T_360 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 150:122] + node _T_361 = eq(_T_360, UInt<5>("h010")) @[el2_pic_ctl.scala 150:139] + node _T_362 = and(raddr_intenable_base_match, _T_361) @[el2_pic_ctl.scala 150:106] + node intenable_reg_re_16 = and(_T_362, picm_rden_ff) @[el2_pic_ctl.scala 150:153] + node _T_363 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 150:122] + node _T_364 = eq(_T_363, UInt<5>("h011")) @[el2_pic_ctl.scala 150:139] + node _T_365 = and(raddr_intenable_base_match, _T_364) @[el2_pic_ctl.scala 150:106] + node intenable_reg_re_17 = and(_T_365, picm_rden_ff) @[el2_pic_ctl.scala 150:153] + node _T_366 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 150:122] + node _T_367 = eq(_T_366, UInt<5>("h012")) @[el2_pic_ctl.scala 150:139] + node _T_368 = and(raddr_intenable_base_match, _T_367) @[el2_pic_ctl.scala 150:106] + node intenable_reg_re_18 = and(_T_368, picm_rden_ff) @[el2_pic_ctl.scala 150:153] + node _T_369 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 150:122] + node _T_370 = eq(_T_369, UInt<5>("h013")) @[el2_pic_ctl.scala 150:139] + node _T_371 = and(raddr_intenable_base_match, _T_370) @[el2_pic_ctl.scala 150:106] + node intenable_reg_re_19 = and(_T_371, picm_rden_ff) @[el2_pic_ctl.scala 150:153] + node _T_372 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 150:122] + node _T_373 = eq(_T_372, UInt<5>("h014")) @[el2_pic_ctl.scala 150:139] + node _T_374 = and(raddr_intenable_base_match, _T_373) @[el2_pic_ctl.scala 150:106] + node intenable_reg_re_20 = and(_T_374, picm_rden_ff) @[el2_pic_ctl.scala 150:153] + node _T_375 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 150:122] + node _T_376 = eq(_T_375, UInt<5>("h015")) @[el2_pic_ctl.scala 150:139] + node _T_377 = and(raddr_intenable_base_match, _T_376) @[el2_pic_ctl.scala 150:106] + node intenable_reg_re_21 = and(_T_377, picm_rden_ff) @[el2_pic_ctl.scala 150:153] + node _T_378 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 150:122] + node _T_379 = eq(_T_378, UInt<5>("h016")) @[el2_pic_ctl.scala 150:139] + node _T_380 = and(raddr_intenable_base_match, _T_379) @[el2_pic_ctl.scala 150:106] + node intenable_reg_re_22 = and(_T_380, picm_rden_ff) @[el2_pic_ctl.scala 150:153] + node _T_381 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 150:122] + node _T_382 = eq(_T_381, UInt<5>("h017")) @[el2_pic_ctl.scala 150:139] + node _T_383 = and(raddr_intenable_base_match, _T_382) @[el2_pic_ctl.scala 150:106] + node intenable_reg_re_23 = and(_T_383, picm_rden_ff) @[el2_pic_ctl.scala 150:153] + node _T_384 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 150:122] + node _T_385 = eq(_T_384, UInt<5>("h018")) @[el2_pic_ctl.scala 150:139] + node _T_386 = and(raddr_intenable_base_match, _T_385) @[el2_pic_ctl.scala 150:106] + node intenable_reg_re_24 = and(_T_386, picm_rden_ff) @[el2_pic_ctl.scala 150:153] + node _T_387 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 150:122] + node _T_388 = eq(_T_387, UInt<5>("h019")) @[el2_pic_ctl.scala 150:139] + node _T_389 = and(raddr_intenable_base_match, _T_388) @[el2_pic_ctl.scala 150:106] + node intenable_reg_re_25 = and(_T_389, picm_rden_ff) @[el2_pic_ctl.scala 150:153] + node _T_390 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 150:122] + node _T_391 = eq(_T_390, UInt<5>("h01a")) @[el2_pic_ctl.scala 150:139] + node _T_392 = and(raddr_intenable_base_match, _T_391) @[el2_pic_ctl.scala 150:106] + node intenable_reg_re_26 = and(_T_392, picm_rden_ff) @[el2_pic_ctl.scala 150:153] + node _T_393 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 150:122] + node _T_394 = eq(_T_393, UInt<5>("h01b")) @[el2_pic_ctl.scala 150:139] + node _T_395 = and(raddr_intenable_base_match, _T_394) @[el2_pic_ctl.scala 150:106] + node intenable_reg_re_27 = and(_T_395, picm_rden_ff) @[el2_pic_ctl.scala 150:153] + node _T_396 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 150:122] + node _T_397 = eq(_T_396, UInt<5>("h01c")) @[el2_pic_ctl.scala 150:139] + node _T_398 = and(raddr_intenable_base_match, _T_397) @[el2_pic_ctl.scala 150:106] + node intenable_reg_re_28 = and(_T_398, picm_rden_ff) @[el2_pic_ctl.scala 150:153] + node _T_399 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 150:122] + node _T_400 = eq(_T_399, UInt<5>("h01d")) @[el2_pic_ctl.scala 150:139] + node _T_401 = and(raddr_intenable_base_match, _T_400) @[el2_pic_ctl.scala 150:106] + node intenable_reg_re_29 = and(_T_401, picm_rden_ff) @[el2_pic_ctl.scala 150:153] + node _T_402 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 150:122] + node _T_403 = eq(_T_402, UInt<5>("h01e")) @[el2_pic_ctl.scala 150:139] + node _T_404 = and(raddr_intenable_base_match, _T_403) @[el2_pic_ctl.scala 150:106] + node intenable_reg_re_30 = and(_T_404, picm_rden_ff) @[el2_pic_ctl.scala 150:153] + node _T_405 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 150:122] + node _T_406 = eq(_T_405, UInt<5>("h01f")) @[el2_pic_ctl.scala 150:139] + node _T_407 = and(raddr_intenable_base_match, _T_406) @[el2_pic_ctl.scala 150:106] + node intenable_reg_re_31 = and(_T_407, picm_rden_ff) @[el2_pic_ctl.scala 150:153] + node _T_408 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 151:122] + node _T_409 = eq(_T_408, UInt<1>("h01")) @[el2_pic_ctl.scala 151:139] + node _T_410 = and(waddr_config_gw_base_match, _T_409) @[el2_pic_ctl.scala 151:106] + node gw_config_reg_we_1 = and(_T_410, picm_wren_ff) @[el2_pic_ctl.scala 151:153] + node _T_411 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 151:122] + node _T_412 = eq(_T_411, UInt<2>("h02")) @[el2_pic_ctl.scala 151:139] + node _T_413 = and(waddr_config_gw_base_match, _T_412) @[el2_pic_ctl.scala 151:106] + node gw_config_reg_we_2 = and(_T_413, picm_wren_ff) @[el2_pic_ctl.scala 151:153] + node _T_414 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 151:122] + node _T_415 = eq(_T_414, UInt<2>("h03")) @[el2_pic_ctl.scala 151:139] + node _T_416 = and(waddr_config_gw_base_match, _T_415) @[el2_pic_ctl.scala 151:106] + node gw_config_reg_we_3 = and(_T_416, picm_wren_ff) @[el2_pic_ctl.scala 151:153] + node _T_417 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 151:122] + node _T_418 = eq(_T_417, UInt<3>("h04")) @[el2_pic_ctl.scala 151:139] + node _T_419 = and(waddr_config_gw_base_match, _T_418) @[el2_pic_ctl.scala 151:106] + node gw_config_reg_we_4 = and(_T_419, picm_wren_ff) @[el2_pic_ctl.scala 151:153] + node _T_420 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 151:122] + node _T_421 = eq(_T_420, UInt<3>("h05")) @[el2_pic_ctl.scala 151:139] + node _T_422 = and(waddr_config_gw_base_match, _T_421) @[el2_pic_ctl.scala 151:106] + node gw_config_reg_we_5 = and(_T_422, picm_wren_ff) @[el2_pic_ctl.scala 151:153] + node _T_423 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 151:122] + node _T_424 = eq(_T_423, UInt<3>("h06")) @[el2_pic_ctl.scala 151:139] + node _T_425 = and(waddr_config_gw_base_match, _T_424) @[el2_pic_ctl.scala 151:106] + node gw_config_reg_we_6 = and(_T_425, picm_wren_ff) @[el2_pic_ctl.scala 151:153] + node _T_426 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 151:122] + node _T_427 = eq(_T_426, UInt<3>("h07")) @[el2_pic_ctl.scala 151:139] + node _T_428 = and(waddr_config_gw_base_match, _T_427) @[el2_pic_ctl.scala 151:106] + node gw_config_reg_we_7 = and(_T_428, picm_wren_ff) @[el2_pic_ctl.scala 151:153] + node _T_429 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 151:122] + node _T_430 = eq(_T_429, UInt<4>("h08")) @[el2_pic_ctl.scala 151:139] + node _T_431 = and(waddr_config_gw_base_match, _T_430) @[el2_pic_ctl.scala 151:106] + node gw_config_reg_we_8 = and(_T_431, picm_wren_ff) @[el2_pic_ctl.scala 151:153] + node _T_432 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 151:122] + node _T_433 = eq(_T_432, UInt<4>("h09")) @[el2_pic_ctl.scala 151:139] + node _T_434 = and(waddr_config_gw_base_match, _T_433) @[el2_pic_ctl.scala 151:106] + node gw_config_reg_we_9 = and(_T_434, picm_wren_ff) @[el2_pic_ctl.scala 151:153] + node _T_435 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 151:122] + node _T_436 = eq(_T_435, UInt<4>("h0a")) @[el2_pic_ctl.scala 151:139] + node _T_437 = and(waddr_config_gw_base_match, _T_436) @[el2_pic_ctl.scala 151:106] + node gw_config_reg_we_10 = and(_T_437, picm_wren_ff) @[el2_pic_ctl.scala 151:153] + node _T_438 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 151:122] + node _T_439 = eq(_T_438, UInt<4>("h0b")) @[el2_pic_ctl.scala 151:139] + node _T_440 = and(waddr_config_gw_base_match, _T_439) @[el2_pic_ctl.scala 151:106] + node gw_config_reg_we_11 = and(_T_440, picm_wren_ff) @[el2_pic_ctl.scala 151:153] + node _T_441 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 151:122] + node _T_442 = eq(_T_441, UInt<4>("h0c")) @[el2_pic_ctl.scala 151:139] + node _T_443 = and(waddr_config_gw_base_match, _T_442) @[el2_pic_ctl.scala 151:106] + node gw_config_reg_we_12 = and(_T_443, picm_wren_ff) @[el2_pic_ctl.scala 151:153] + node _T_444 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 151:122] + node _T_445 = eq(_T_444, UInt<4>("h0d")) @[el2_pic_ctl.scala 151:139] + node _T_446 = and(waddr_config_gw_base_match, _T_445) @[el2_pic_ctl.scala 151:106] + node gw_config_reg_we_13 = and(_T_446, picm_wren_ff) @[el2_pic_ctl.scala 151:153] + node _T_447 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 151:122] + node _T_448 = eq(_T_447, UInt<4>("h0e")) @[el2_pic_ctl.scala 151:139] + node _T_449 = and(waddr_config_gw_base_match, _T_448) @[el2_pic_ctl.scala 151:106] + node gw_config_reg_we_14 = and(_T_449, picm_wren_ff) @[el2_pic_ctl.scala 151:153] + node _T_450 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 151:122] + node _T_451 = eq(_T_450, UInt<4>("h0f")) @[el2_pic_ctl.scala 151:139] + node _T_452 = and(waddr_config_gw_base_match, _T_451) @[el2_pic_ctl.scala 151:106] + node gw_config_reg_we_15 = and(_T_452, picm_wren_ff) @[el2_pic_ctl.scala 151:153] + node _T_453 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 151:122] + node _T_454 = eq(_T_453, UInt<5>("h010")) @[el2_pic_ctl.scala 151:139] + node _T_455 = and(waddr_config_gw_base_match, _T_454) @[el2_pic_ctl.scala 151:106] + node gw_config_reg_we_16 = and(_T_455, picm_wren_ff) @[el2_pic_ctl.scala 151:153] + node _T_456 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 151:122] + node _T_457 = eq(_T_456, UInt<5>("h011")) @[el2_pic_ctl.scala 151:139] + node _T_458 = and(waddr_config_gw_base_match, _T_457) @[el2_pic_ctl.scala 151:106] + node gw_config_reg_we_17 = and(_T_458, picm_wren_ff) @[el2_pic_ctl.scala 151:153] + node _T_459 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 151:122] + node _T_460 = eq(_T_459, UInt<5>("h012")) @[el2_pic_ctl.scala 151:139] + node _T_461 = and(waddr_config_gw_base_match, _T_460) @[el2_pic_ctl.scala 151:106] + node gw_config_reg_we_18 = and(_T_461, picm_wren_ff) @[el2_pic_ctl.scala 151:153] + node _T_462 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 151:122] + node _T_463 = eq(_T_462, UInt<5>("h013")) @[el2_pic_ctl.scala 151:139] + node _T_464 = and(waddr_config_gw_base_match, _T_463) @[el2_pic_ctl.scala 151:106] + node gw_config_reg_we_19 = and(_T_464, picm_wren_ff) @[el2_pic_ctl.scala 151:153] + node _T_465 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 151:122] + node _T_466 = eq(_T_465, UInt<5>("h014")) @[el2_pic_ctl.scala 151:139] + node _T_467 = and(waddr_config_gw_base_match, _T_466) @[el2_pic_ctl.scala 151:106] + node gw_config_reg_we_20 = and(_T_467, picm_wren_ff) @[el2_pic_ctl.scala 151:153] + node _T_468 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 151:122] + node _T_469 = eq(_T_468, UInt<5>("h015")) @[el2_pic_ctl.scala 151:139] + node _T_470 = and(waddr_config_gw_base_match, _T_469) @[el2_pic_ctl.scala 151:106] + node gw_config_reg_we_21 = and(_T_470, picm_wren_ff) @[el2_pic_ctl.scala 151:153] + node _T_471 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 151:122] + node _T_472 = eq(_T_471, UInt<5>("h016")) @[el2_pic_ctl.scala 151:139] + node _T_473 = and(waddr_config_gw_base_match, _T_472) @[el2_pic_ctl.scala 151:106] + node gw_config_reg_we_22 = and(_T_473, picm_wren_ff) @[el2_pic_ctl.scala 151:153] + node _T_474 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 151:122] + node _T_475 = eq(_T_474, UInt<5>("h017")) @[el2_pic_ctl.scala 151:139] + node _T_476 = and(waddr_config_gw_base_match, _T_475) @[el2_pic_ctl.scala 151:106] + node gw_config_reg_we_23 = and(_T_476, picm_wren_ff) @[el2_pic_ctl.scala 151:153] + node _T_477 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 151:122] + node _T_478 = eq(_T_477, UInt<5>("h018")) @[el2_pic_ctl.scala 151:139] + node _T_479 = and(waddr_config_gw_base_match, _T_478) @[el2_pic_ctl.scala 151:106] + node gw_config_reg_we_24 = and(_T_479, picm_wren_ff) @[el2_pic_ctl.scala 151:153] + node _T_480 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 151:122] + node _T_481 = eq(_T_480, UInt<5>("h019")) @[el2_pic_ctl.scala 151:139] + node _T_482 = and(waddr_config_gw_base_match, _T_481) @[el2_pic_ctl.scala 151:106] + node gw_config_reg_we_25 = and(_T_482, picm_wren_ff) @[el2_pic_ctl.scala 151:153] + node _T_483 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 151:122] + node _T_484 = eq(_T_483, UInt<5>("h01a")) @[el2_pic_ctl.scala 151:139] + node _T_485 = and(waddr_config_gw_base_match, _T_484) @[el2_pic_ctl.scala 151:106] + node gw_config_reg_we_26 = and(_T_485, picm_wren_ff) @[el2_pic_ctl.scala 151:153] + node _T_486 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 151:122] + node _T_487 = eq(_T_486, UInt<5>("h01b")) @[el2_pic_ctl.scala 151:139] + node _T_488 = and(waddr_config_gw_base_match, _T_487) @[el2_pic_ctl.scala 151:106] + node gw_config_reg_we_27 = and(_T_488, picm_wren_ff) @[el2_pic_ctl.scala 151:153] + node _T_489 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 151:122] + node _T_490 = eq(_T_489, UInt<5>("h01c")) @[el2_pic_ctl.scala 151:139] + node _T_491 = and(waddr_config_gw_base_match, _T_490) @[el2_pic_ctl.scala 151:106] + node gw_config_reg_we_28 = and(_T_491, picm_wren_ff) @[el2_pic_ctl.scala 151:153] + node _T_492 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 151:122] + node _T_493 = eq(_T_492, UInt<5>("h01d")) @[el2_pic_ctl.scala 151:139] + node _T_494 = and(waddr_config_gw_base_match, _T_493) @[el2_pic_ctl.scala 151:106] + node gw_config_reg_we_29 = and(_T_494, picm_wren_ff) @[el2_pic_ctl.scala 151:153] + node _T_495 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 151:122] + node _T_496 = eq(_T_495, UInt<5>("h01e")) @[el2_pic_ctl.scala 151:139] + node _T_497 = and(waddr_config_gw_base_match, _T_496) @[el2_pic_ctl.scala 151:106] + node gw_config_reg_we_30 = and(_T_497, picm_wren_ff) @[el2_pic_ctl.scala 151:153] + node _T_498 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 151:122] + node _T_499 = eq(_T_498, UInt<5>("h01f")) @[el2_pic_ctl.scala 151:139] + node _T_500 = and(waddr_config_gw_base_match, _T_499) @[el2_pic_ctl.scala 151:106] + node gw_config_reg_we_31 = and(_T_500, picm_wren_ff) @[el2_pic_ctl.scala 151:153] + node _T_501 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 152:122] + node _T_502 = eq(_T_501, UInt<1>("h01")) @[el2_pic_ctl.scala 152:139] + node _T_503 = and(raddr_config_gw_base_match, _T_502) @[el2_pic_ctl.scala 152:106] + node gw_config_reg_re_1 = and(_T_503, picm_rden_ff) @[el2_pic_ctl.scala 152:153] + node _T_504 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 152:122] + node _T_505 = eq(_T_504, UInt<2>("h02")) @[el2_pic_ctl.scala 152:139] + node _T_506 = and(raddr_config_gw_base_match, _T_505) @[el2_pic_ctl.scala 152:106] + node gw_config_reg_re_2 = and(_T_506, picm_rden_ff) @[el2_pic_ctl.scala 152:153] + node _T_507 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 152:122] + node _T_508 = eq(_T_507, UInt<2>("h03")) @[el2_pic_ctl.scala 152:139] + node _T_509 = and(raddr_config_gw_base_match, _T_508) @[el2_pic_ctl.scala 152:106] + node gw_config_reg_re_3 = and(_T_509, picm_rden_ff) @[el2_pic_ctl.scala 152:153] + node _T_510 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 152:122] + node _T_511 = eq(_T_510, UInt<3>("h04")) @[el2_pic_ctl.scala 152:139] + node _T_512 = and(raddr_config_gw_base_match, _T_511) @[el2_pic_ctl.scala 152:106] + node gw_config_reg_re_4 = and(_T_512, picm_rden_ff) @[el2_pic_ctl.scala 152:153] + node _T_513 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 152:122] + node _T_514 = eq(_T_513, UInt<3>("h05")) @[el2_pic_ctl.scala 152:139] + node _T_515 = and(raddr_config_gw_base_match, _T_514) @[el2_pic_ctl.scala 152:106] + node gw_config_reg_re_5 = and(_T_515, picm_rden_ff) @[el2_pic_ctl.scala 152:153] + node _T_516 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 152:122] + node _T_517 = eq(_T_516, UInt<3>("h06")) @[el2_pic_ctl.scala 152:139] + node _T_518 = and(raddr_config_gw_base_match, _T_517) @[el2_pic_ctl.scala 152:106] + node gw_config_reg_re_6 = and(_T_518, picm_rden_ff) @[el2_pic_ctl.scala 152:153] + node _T_519 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 152:122] + node _T_520 = eq(_T_519, UInt<3>("h07")) @[el2_pic_ctl.scala 152:139] + node _T_521 = and(raddr_config_gw_base_match, _T_520) @[el2_pic_ctl.scala 152:106] + node gw_config_reg_re_7 = and(_T_521, picm_rden_ff) @[el2_pic_ctl.scala 152:153] + node _T_522 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 152:122] + node _T_523 = eq(_T_522, UInt<4>("h08")) @[el2_pic_ctl.scala 152:139] + node _T_524 = and(raddr_config_gw_base_match, _T_523) @[el2_pic_ctl.scala 152:106] + node gw_config_reg_re_8 = and(_T_524, picm_rden_ff) @[el2_pic_ctl.scala 152:153] + node _T_525 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 152:122] + node _T_526 = eq(_T_525, UInt<4>("h09")) @[el2_pic_ctl.scala 152:139] + node _T_527 = and(raddr_config_gw_base_match, _T_526) @[el2_pic_ctl.scala 152:106] + node gw_config_reg_re_9 = and(_T_527, picm_rden_ff) @[el2_pic_ctl.scala 152:153] + node _T_528 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 152:122] + node _T_529 = eq(_T_528, UInt<4>("h0a")) @[el2_pic_ctl.scala 152:139] + node _T_530 = and(raddr_config_gw_base_match, _T_529) @[el2_pic_ctl.scala 152:106] + node gw_config_reg_re_10 = and(_T_530, picm_rden_ff) @[el2_pic_ctl.scala 152:153] + node _T_531 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 152:122] + node _T_532 = eq(_T_531, UInt<4>("h0b")) @[el2_pic_ctl.scala 152:139] + node _T_533 = and(raddr_config_gw_base_match, _T_532) @[el2_pic_ctl.scala 152:106] + node gw_config_reg_re_11 = and(_T_533, picm_rden_ff) @[el2_pic_ctl.scala 152:153] + node _T_534 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 152:122] + node _T_535 = eq(_T_534, UInt<4>("h0c")) @[el2_pic_ctl.scala 152:139] + node _T_536 = and(raddr_config_gw_base_match, _T_535) @[el2_pic_ctl.scala 152:106] + node gw_config_reg_re_12 = and(_T_536, picm_rden_ff) @[el2_pic_ctl.scala 152:153] + node _T_537 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 152:122] + node _T_538 = eq(_T_537, UInt<4>("h0d")) @[el2_pic_ctl.scala 152:139] + node _T_539 = and(raddr_config_gw_base_match, _T_538) @[el2_pic_ctl.scala 152:106] + node gw_config_reg_re_13 = and(_T_539, picm_rden_ff) @[el2_pic_ctl.scala 152:153] + node _T_540 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 152:122] + node _T_541 = eq(_T_540, UInt<4>("h0e")) @[el2_pic_ctl.scala 152:139] + node _T_542 = and(raddr_config_gw_base_match, _T_541) @[el2_pic_ctl.scala 152:106] + node gw_config_reg_re_14 = and(_T_542, picm_rden_ff) @[el2_pic_ctl.scala 152:153] + node _T_543 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 152:122] + node _T_544 = eq(_T_543, UInt<4>("h0f")) @[el2_pic_ctl.scala 152:139] + node _T_545 = and(raddr_config_gw_base_match, _T_544) @[el2_pic_ctl.scala 152:106] + node gw_config_reg_re_15 = and(_T_545, picm_rden_ff) @[el2_pic_ctl.scala 152:153] + node _T_546 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 152:122] + node _T_547 = eq(_T_546, UInt<5>("h010")) @[el2_pic_ctl.scala 152:139] + node _T_548 = and(raddr_config_gw_base_match, _T_547) @[el2_pic_ctl.scala 152:106] + node gw_config_reg_re_16 = and(_T_548, picm_rden_ff) @[el2_pic_ctl.scala 152:153] + node _T_549 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 152:122] + node _T_550 = eq(_T_549, UInt<5>("h011")) @[el2_pic_ctl.scala 152:139] + node _T_551 = and(raddr_config_gw_base_match, _T_550) @[el2_pic_ctl.scala 152:106] + node gw_config_reg_re_17 = and(_T_551, picm_rden_ff) @[el2_pic_ctl.scala 152:153] + node _T_552 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 152:122] + node _T_553 = eq(_T_552, UInt<5>("h012")) @[el2_pic_ctl.scala 152:139] + node _T_554 = and(raddr_config_gw_base_match, _T_553) @[el2_pic_ctl.scala 152:106] + node gw_config_reg_re_18 = and(_T_554, picm_rden_ff) @[el2_pic_ctl.scala 152:153] + node _T_555 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 152:122] + node _T_556 = eq(_T_555, UInt<5>("h013")) @[el2_pic_ctl.scala 152:139] + node _T_557 = and(raddr_config_gw_base_match, _T_556) @[el2_pic_ctl.scala 152:106] + node gw_config_reg_re_19 = and(_T_557, picm_rden_ff) @[el2_pic_ctl.scala 152:153] + node _T_558 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 152:122] + node _T_559 = eq(_T_558, UInt<5>("h014")) @[el2_pic_ctl.scala 152:139] + node _T_560 = and(raddr_config_gw_base_match, _T_559) @[el2_pic_ctl.scala 152:106] + node gw_config_reg_re_20 = and(_T_560, picm_rden_ff) @[el2_pic_ctl.scala 152:153] + node _T_561 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 152:122] + node _T_562 = eq(_T_561, UInt<5>("h015")) @[el2_pic_ctl.scala 152:139] + node _T_563 = and(raddr_config_gw_base_match, _T_562) @[el2_pic_ctl.scala 152:106] + node gw_config_reg_re_21 = and(_T_563, picm_rden_ff) @[el2_pic_ctl.scala 152:153] + node _T_564 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 152:122] + node _T_565 = eq(_T_564, UInt<5>("h016")) @[el2_pic_ctl.scala 152:139] + node _T_566 = and(raddr_config_gw_base_match, _T_565) @[el2_pic_ctl.scala 152:106] + node gw_config_reg_re_22 = and(_T_566, picm_rden_ff) @[el2_pic_ctl.scala 152:153] + node _T_567 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 152:122] + node _T_568 = eq(_T_567, UInt<5>("h017")) @[el2_pic_ctl.scala 152:139] + node _T_569 = and(raddr_config_gw_base_match, _T_568) @[el2_pic_ctl.scala 152:106] + node gw_config_reg_re_23 = and(_T_569, picm_rden_ff) @[el2_pic_ctl.scala 152:153] + node _T_570 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 152:122] + node _T_571 = eq(_T_570, UInt<5>("h018")) @[el2_pic_ctl.scala 152:139] + node _T_572 = and(raddr_config_gw_base_match, _T_571) @[el2_pic_ctl.scala 152:106] + node gw_config_reg_re_24 = and(_T_572, picm_rden_ff) @[el2_pic_ctl.scala 152:153] + node _T_573 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 152:122] + node _T_574 = eq(_T_573, UInt<5>("h019")) @[el2_pic_ctl.scala 152:139] + node _T_575 = and(raddr_config_gw_base_match, _T_574) @[el2_pic_ctl.scala 152:106] + node gw_config_reg_re_25 = and(_T_575, picm_rden_ff) @[el2_pic_ctl.scala 152:153] + node _T_576 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 152:122] + node _T_577 = eq(_T_576, UInt<5>("h01a")) @[el2_pic_ctl.scala 152:139] + node _T_578 = and(raddr_config_gw_base_match, _T_577) @[el2_pic_ctl.scala 152:106] + node gw_config_reg_re_26 = and(_T_578, picm_rden_ff) @[el2_pic_ctl.scala 152:153] + node _T_579 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 152:122] + node _T_580 = eq(_T_579, UInt<5>("h01b")) @[el2_pic_ctl.scala 152:139] + node _T_581 = and(raddr_config_gw_base_match, _T_580) @[el2_pic_ctl.scala 152:106] + node gw_config_reg_re_27 = and(_T_581, picm_rden_ff) @[el2_pic_ctl.scala 152:153] + node _T_582 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 152:122] + node _T_583 = eq(_T_582, UInt<5>("h01c")) @[el2_pic_ctl.scala 152:139] + node _T_584 = and(raddr_config_gw_base_match, _T_583) @[el2_pic_ctl.scala 152:106] + node gw_config_reg_re_28 = and(_T_584, picm_rden_ff) @[el2_pic_ctl.scala 152:153] + node _T_585 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 152:122] + node _T_586 = eq(_T_585, UInt<5>("h01d")) @[el2_pic_ctl.scala 152:139] + node _T_587 = and(raddr_config_gw_base_match, _T_586) @[el2_pic_ctl.scala 152:106] + node gw_config_reg_re_29 = and(_T_587, picm_rden_ff) @[el2_pic_ctl.scala 152:153] + node _T_588 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 152:122] + node _T_589 = eq(_T_588, UInt<5>("h01e")) @[el2_pic_ctl.scala 152:139] + node _T_590 = and(raddr_config_gw_base_match, _T_589) @[el2_pic_ctl.scala 152:106] + node gw_config_reg_re_30 = and(_T_590, picm_rden_ff) @[el2_pic_ctl.scala 152:153] + node _T_591 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 152:122] + node _T_592 = eq(_T_591, UInt<5>("h01f")) @[el2_pic_ctl.scala 152:139] + node _T_593 = and(raddr_config_gw_base_match, _T_592) @[el2_pic_ctl.scala 152:106] + node gw_config_reg_re_31 = and(_T_593, picm_rden_ff) @[el2_pic_ctl.scala 152:153] + node _T_594 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 153:122] + node _T_595 = eq(_T_594, UInt<1>("h01")) @[el2_pic_ctl.scala 153:139] + node _T_596 = and(addr_clear_gw_base_match, _T_595) @[el2_pic_ctl.scala 153:106] + node gw_clear_reg_we_1 = and(_T_596, picm_wren_ff) @[el2_pic_ctl.scala 153:153] + node _T_597 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 153:122] + node _T_598 = eq(_T_597, UInt<2>("h02")) @[el2_pic_ctl.scala 153:139] + node _T_599 = and(addr_clear_gw_base_match, _T_598) @[el2_pic_ctl.scala 153:106] + node gw_clear_reg_we_2 = and(_T_599, picm_wren_ff) @[el2_pic_ctl.scala 153:153] + node _T_600 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 153:122] + node _T_601 = eq(_T_600, UInt<2>("h03")) @[el2_pic_ctl.scala 153:139] + node _T_602 = and(addr_clear_gw_base_match, _T_601) @[el2_pic_ctl.scala 153:106] + node gw_clear_reg_we_3 = and(_T_602, picm_wren_ff) @[el2_pic_ctl.scala 153:153] + node _T_603 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 153:122] + node _T_604 = eq(_T_603, UInt<3>("h04")) @[el2_pic_ctl.scala 153:139] + node _T_605 = and(addr_clear_gw_base_match, _T_604) @[el2_pic_ctl.scala 153:106] + node gw_clear_reg_we_4 = and(_T_605, picm_wren_ff) @[el2_pic_ctl.scala 153:153] + node _T_606 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 153:122] + node _T_607 = eq(_T_606, UInt<3>("h05")) @[el2_pic_ctl.scala 153:139] + node _T_608 = and(addr_clear_gw_base_match, _T_607) @[el2_pic_ctl.scala 153:106] + node gw_clear_reg_we_5 = and(_T_608, picm_wren_ff) @[el2_pic_ctl.scala 153:153] + node _T_609 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 153:122] + node _T_610 = eq(_T_609, UInt<3>("h06")) @[el2_pic_ctl.scala 153:139] + node _T_611 = and(addr_clear_gw_base_match, _T_610) @[el2_pic_ctl.scala 153:106] + node gw_clear_reg_we_6 = and(_T_611, picm_wren_ff) @[el2_pic_ctl.scala 153:153] + node _T_612 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 153:122] + node _T_613 = eq(_T_612, UInt<3>("h07")) @[el2_pic_ctl.scala 153:139] + node _T_614 = and(addr_clear_gw_base_match, _T_613) @[el2_pic_ctl.scala 153:106] + node gw_clear_reg_we_7 = and(_T_614, picm_wren_ff) @[el2_pic_ctl.scala 153:153] + node _T_615 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 153:122] + node _T_616 = eq(_T_615, UInt<4>("h08")) @[el2_pic_ctl.scala 153:139] + node _T_617 = and(addr_clear_gw_base_match, _T_616) @[el2_pic_ctl.scala 153:106] + node gw_clear_reg_we_8 = and(_T_617, picm_wren_ff) @[el2_pic_ctl.scala 153:153] + node _T_618 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 153:122] + node _T_619 = eq(_T_618, UInt<4>("h09")) @[el2_pic_ctl.scala 153:139] + node _T_620 = and(addr_clear_gw_base_match, _T_619) @[el2_pic_ctl.scala 153:106] + node gw_clear_reg_we_9 = and(_T_620, picm_wren_ff) @[el2_pic_ctl.scala 153:153] + node _T_621 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 153:122] + node _T_622 = eq(_T_621, UInt<4>("h0a")) @[el2_pic_ctl.scala 153:139] + node _T_623 = and(addr_clear_gw_base_match, _T_622) @[el2_pic_ctl.scala 153:106] + node gw_clear_reg_we_10 = and(_T_623, picm_wren_ff) @[el2_pic_ctl.scala 153:153] + node _T_624 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 153:122] + node _T_625 = eq(_T_624, UInt<4>("h0b")) @[el2_pic_ctl.scala 153:139] + node _T_626 = and(addr_clear_gw_base_match, _T_625) @[el2_pic_ctl.scala 153:106] + node gw_clear_reg_we_11 = and(_T_626, picm_wren_ff) @[el2_pic_ctl.scala 153:153] + node _T_627 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 153:122] + node _T_628 = eq(_T_627, UInt<4>("h0c")) @[el2_pic_ctl.scala 153:139] + node _T_629 = and(addr_clear_gw_base_match, _T_628) @[el2_pic_ctl.scala 153:106] + node gw_clear_reg_we_12 = and(_T_629, picm_wren_ff) @[el2_pic_ctl.scala 153:153] + node _T_630 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 153:122] + node _T_631 = eq(_T_630, UInt<4>("h0d")) @[el2_pic_ctl.scala 153:139] + node _T_632 = and(addr_clear_gw_base_match, _T_631) @[el2_pic_ctl.scala 153:106] + node gw_clear_reg_we_13 = and(_T_632, picm_wren_ff) @[el2_pic_ctl.scala 153:153] + node _T_633 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 153:122] + node _T_634 = eq(_T_633, UInt<4>("h0e")) @[el2_pic_ctl.scala 153:139] + node _T_635 = and(addr_clear_gw_base_match, _T_634) @[el2_pic_ctl.scala 153:106] + node gw_clear_reg_we_14 = and(_T_635, picm_wren_ff) @[el2_pic_ctl.scala 153:153] + node _T_636 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 153:122] + node _T_637 = eq(_T_636, UInt<4>("h0f")) @[el2_pic_ctl.scala 153:139] + node _T_638 = and(addr_clear_gw_base_match, _T_637) @[el2_pic_ctl.scala 153:106] + node gw_clear_reg_we_15 = and(_T_638, picm_wren_ff) @[el2_pic_ctl.scala 153:153] + node _T_639 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 153:122] + node _T_640 = eq(_T_639, UInt<5>("h010")) @[el2_pic_ctl.scala 153:139] + node _T_641 = and(addr_clear_gw_base_match, _T_640) @[el2_pic_ctl.scala 153:106] + node gw_clear_reg_we_16 = and(_T_641, picm_wren_ff) @[el2_pic_ctl.scala 153:153] + node _T_642 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 153:122] + node _T_643 = eq(_T_642, UInt<5>("h011")) @[el2_pic_ctl.scala 153:139] + node _T_644 = and(addr_clear_gw_base_match, _T_643) @[el2_pic_ctl.scala 153:106] + node gw_clear_reg_we_17 = and(_T_644, picm_wren_ff) @[el2_pic_ctl.scala 153:153] + node _T_645 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 153:122] + node _T_646 = eq(_T_645, UInt<5>("h012")) @[el2_pic_ctl.scala 153:139] + node _T_647 = and(addr_clear_gw_base_match, _T_646) @[el2_pic_ctl.scala 153:106] + node gw_clear_reg_we_18 = and(_T_647, picm_wren_ff) @[el2_pic_ctl.scala 153:153] + node _T_648 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 153:122] + node _T_649 = eq(_T_648, UInt<5>("h013")) @[el2_pic_ctl.scala 153:139] + node _T_650 = and(addr_clear_gw_base_match, _T_649) @[el2_pic_ctl.scala 153:106] + node gw_clear_reg_we_19 = and(_T_650, picm_wren_ff) @[el2_pic_ctl.scala 153:153] + node _T_651 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 153:122] + node _T_652 = eq(_T_651, UInt<5>("h014")) @[el2_pic_ctl.scala 153:139] + node _T_653 = and(addr_clear_gw_base_match, _T_652) @[el2_pic_ctl.scala 153:106] + node gw_clear_reg_we_20 = and(_T_653, picm_wren_ff) @[el2_pic_ctl.scala 153:153] + node _T_654 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 153:122] + node _T_655 = eq(_T_654, UInt<5>("h015")) @[el2_pic_ctl.scala 153:139] + node _T_656 = and(addr_clear_gw_base_match, _T_655) @[el2_pic_ctl.scala 153:106] + node gw_clear_reg_we_21 = and(_T_656, picm_wren_ff) @[el2_pic_ctl.scala 153:153] + node _T_657 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 153:122] + node _T_658 = eq(_T_657, UInt<5>("h016")) @[el2_pic_ctl.scala 153:139] + node _T_659 = and(addr_clear_gw_base_match, _T_658) @[el2_pic_ctl.scala 153:106] + node gw_clear_reg_we_22 = and(_T_659, picm_wren_ff) @[el2_pic_ctl.scala 153:153] + node _T_660 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 153:122] + node _T_661 = eq(_T_660, UInt<5>("h017")) @[el2_pic_ctl.scala 153:139] + node _T_662 = and(addr_clear_gw_base_match, _T_661) @[el2_pic_ctl.scala 153:106] + node gw_clear_reg_we_23 = and(_T_662, picm_wren_ff) @[el2_pic_ctl.scala 153:153] + node _T_663 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 153:122] + node _T_664 = eq(_T_663, UInt<5>("h018")) @[el2_pic_ctl.scala 153:139] + node _T_665 = and(addr_clear_gw_base_match, _T_664) @[el2_pic_ctl.scala 153:106] + node gw_clear_reg_we_24 = and(_T_665, picm_wren_ff) @[el2_pic_ctl.scala 153:153] + node _T_666 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 153:122] + node _T_667 = eq(_T_666, UInt<5>("h019")) @[el2_pic_ctl.scala 153:139] + node _T_668 = and(addr_clear_gw_base_match, _T_667) @[el2_pic_ctl.scala 153:106] + node gw_clear_reg_we_25 = and(_T_668, picm_wren_ff) @[el2_pic_ctl.scala 153:153] + node _T_669 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 153:122] + node _T_670 = eq(_T_669, UInt<5>("h01a")) @[el2_pic_ctl.scala 153:139] + node _T_671 = and(addr_clear_gw_base_match, _T_670) @[el2_pic_ctl.scala 153:106] + node gw_clear_reg_we_26 = and(_T_671, picm_wren_ff) @[el2_pic_ctl.scala 153:153] + node _T_672 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 153:122] + node _T_673 = eq(_T_672, UInt<5>("h01b")) @[el2_pic_ctl.scala 153:139] + node _T_674 = and(addr_clear_gw_base_match, _T_673) @[el2_pic_ctl.scala 153:106] + node gw_clear_reg_we_27 = and(_T_674, picm_wren_ff) @[el2_pic_ctl.scala 153:153] + node _T_675 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 153:122] + node _T_676 = eq(_T_675, UInt<5>("h01c")) @[el2_pic_ctl.scala 153:139] + node _T_677 = and(addr_clear_gw_base_match, _T_676) @[el2_pic_ctl.scala 153:106] + node gw_clear_reg_we_28 = and(_T_677, picm_wren_ff) @[el2_pic_ctl.scala 153:153] + node _T_678 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 153:122] + node _T_679 = eq(_T_678, UInt<5>("h01d")) @[el2_pic_ctl.scala 153:139] + node _T_680 = and(addr_clear_gw_base_match, _T_679) @[el2_pic_ctl.scala 153:106] + node gw_clear_reg_we_29 = and(_T_680, picm_wren_ff) @[el2_pic_ctl.scala 153:153] + node _T_681 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 153:122] + node _T_682 = eq(_T_681, UInt<5>("h01e")) @[el2_pic_ctl.scala 153:139] + node _T_683 = and(addr_clear_gw_base_match, _T_682) @[el2_pic_ctl.scala 153:106] + node gw_clear_reg_we_30 = and(_T_683, picm_wren_ff) @[el2_pic_ctl.scala 153:153] + node _T_684 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 153:122] + node _T_685 = eq(_T_684, UInt<5>("h01f")) @[el2_pic_ctl.scala 153:139] + node _T_686 = and(addr_clear_gw_base_match, _T_685) @[el2_pic_ctl.scala 153:106] + node gw_clear_reg_we_31 = and(_T_686, picm_wren_ff) @[el2_pic_ctl.scala 153:153] + wire intpriority_reg : UInt<4>[32] @[el2_pic_ctl.scala 154:32] + intpriority_reg[0] <= UInt<4>("h00") @[el2_pic_ctl.scala 155:208] + node _T_687 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 155:125] + node _T_688 = bits(intpriority_reg_we_1, 0, 0) @[el2_pic_ctl.scala 155:174] reg _T_689 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_688 : @[Reg.scala 28:19] _T_689 <= _T_687 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[1] <= _T_689 @[el2_pic_ctl.scala 163:71] - node _T_690 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] - node _T_691 = bits(intpriority_reg_we_2, 0, 0) @[el2_pic_ctl.scala 163:174] + intpriority_reg[1] <= _T_689 @[el2_pic_ctl.scala 155:71] + node _T_690 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 155:125] + node _T_691 = bits(intpriority_reg_we_2, 0, 0) @[el2_pic_ctl.scala 155:174] reg _T_692 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_691 : @[Reg.scala 28:19] _T_692 <= _T_690 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[2] <= _T_692 @[el2_pic_ctl.scala 163:71] - node _T_693 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] - node _T_694 = bits(intpriority_reg_we_3, 0, 0) @[el2_pic_ctl.scala 163:174] + intpriority_reg[2] <= _T_692 @[el2_pic_ctl.scala 155:71] + node _T_693 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 155:125] + node _T_694 = bits(intpriority_reg_we_3, 0, 0) @[el2_pic_ctl.scala 155:174] reg _T_695 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_694 : @[Reg.scala 28:19] _T_695 <= _T_693 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[3] <= _T_695 @[el2_pic_ctl.scala 163:71] - node _T_696 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] - node _T_697 = bits(intpriority_reg_we_4, 0, 0) @[el2_pic_ctl.scala 163:174] + intpriority_reg[3] <= _T_695 @[el2_pic_ctl.scala 155:71] + node _T_696 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 155:125] + node _T_697 = bits(intpriority_reg_we_4, 0, 0) @[el2_pic_ctl.scala 155:174] reg _T_698 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_697 : @[Reg.scala 28:19] _T_698 <= _T_696 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[4] <= _T_698 @[el2_pic_ctl.scala 163:71] - node _T_699 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] - node _T_700 = bits(intpriority_reg_we_5, 0, 0) @[el2_pic_ctl.scala 163:174] + intpriority_reg[4] <= _T_698 @[el2_pic_ctl.scala 155:71] + node _T_699 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 155:125] + node _T_700 = bits(intpriority_reg_we_5, 0, 0) @[el2_pic_ctl.scala 155:174] reg _T_701 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_700 : @[Reg.scala 28:19] _T_701 <= _T_699 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[5] <= _T_701 @[el2_pic_ctl.scala 163:71] - node _T_702 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] - node _T_703 = bits(intpriority_reg_we_6, 0, 0) @[el2_pic_ctl.scala 163:174] + intpriority_reg[5] <= _T_701 @[el2_pic_ctl.scala 155:71] + node _T_702 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 155:125] + node _T_703 = bits(intpriority_reg_we_6, 0, 0) @[el2_pic_ctl.scala 155:174] reg _T_704 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_703 : @[Reg.scala 28:19] _T_704 <= _T_702 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[6] <= _T_704 @[el2_pic_ctl.scala 163:71] - node _T_705 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] - node _T_706 = bits(intpriority_reg_we_7, 0, 0) @[el2_pic_ctl.scala 163:174] + intpriority_reg[6] <= _T_704 @[el2_pic_ctl.scala 155:71] + node _T_705 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 155:125] + node _T_706 = bits(intpriority_reg_we_7, 0, 0) @[el2_pic_ctl.scala 155:174] reg _T_707 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_706 : @[Reg.scala 28:19] _T_707 <= _T_705 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[7] <= _T_707 @[el2_pic_ctl.scala 163:71] - node _T_708 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] - node _T_709 = bits(intpriority_reg_we_8, 0, 0) @[el2_pic_ctl.scala 163:174] + intpriority_reg[7] <= _T_707 @[el2_pic_ctl.scala 155:71] + node _T_708 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 155:125] + node _T_709 = bits(intpriority_reg_we_8, 0, 0) @[el2_pic_ctl.scala 155:174] reg _T_710 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_709 : @[Reg.scala 28:19] _T_710 <= _T_708 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[8] <= _T_710 @[el2_pic_ctl.scala 163:71] - node _T_711 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] - node _T_712 = bits(intpriority_reg_we_9, 0, 0) @[el2_pic_ctl.scala 163:174] + intpriority_reg[8] <= _T_710 @[el2_pic_ctl.scala 155:71] + node _T_711 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 155:125] + node _T_712 = bits(intpriority_reg_we_9, 0, 0) @[el2_pic_ctl.scala 155:174] reg _T_713 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_712 : @[Reg.scala 28:19] _T_713 <= _T_711 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[9] <= _T_713 @[el2_pic_ctl.scala 163:71] - node _T_714 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] - node _T_715 = bits(intpriority_reg_we_10, 0, 0) @[el2_pic_ctl.scala 163:174] + intpriority_reg[9] <= _T_713 @[el2_pic_ctl.scala 155:71] + node _T_714 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 155:125] + node _T_715 = bits(intpriority_reg_we_10, 0, 0) @[el2_pic_ctl.scala 155:174] reg _T_716 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_715 : @[Reg.scala 28:19] _T_716 <= _T_714 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[10] <= _T_716 @[el2_pic_ctl.scala 163:71] - node _T_717 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] - node _T_718 = bits(intpriority_reg_we_11, 0, 0) @[el2_pic_ctl.scala 163:174] + intpriority_reg[10] <= _T_716 @[el2_pic_ctl.scala 155:71] + node _T_717 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 155:125] + node _T_718 = bits(intpriority_reg_we_11, 0, 0) @[el2_pic_ctl.scala 155:174] reg _T_719 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_718 : @[Reg.scala 28:19] _T_719 <= _T_717 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[11] <= _T_719 @[el2_pic_ctl.scala 163:71] - node _T_720 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] - node _T_721 = bits(intpriority_reg_we_12, 0, 0) @[el2_pic_ctl.scala 163:174] + intpriority_reg[11] <= _T_719 @[el2_pic_ctl.scala 155:71] + node _T_720 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 155:125] + node _T_721 = bits(intpriority_reg_we_12, 0, 0) @[el2_pic_ctl.scala 155:174] reg _T_722 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_721 : @[Reg.scala 28:19] _T_722 <= _T_720 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[12] <= _T_722 @[el2_pic_ctl.scala 163:71] - node _T_723 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] - node _T_724 = bits(intpriority_reg_we_13, 0, 0) @[el2_pic_ctl.scala 163:174] + intpriority_reg[12] <= _T_722 @[el2_pic_ctl.scala 155:71] + node _T_723 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 155:125] + node _T_724 = bits(intpriority_reg_we_13, 0, 0) @[el2_pic_ctl.scala 155:174] reg _T_725 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_724 : @[Reg.scala 28:19] _T_725 <= _T_723 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[13] <= _T_725 @[el2_pic_ctl.scala 163:71] - node _T_726 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] - node _T_727 = bits(intpriority_reg_we_14, 0, 0) @[el2_pic_ctl.scala 163:174] + intpriority_reg[13] <= _T_725 @[el2_pic_ctl.scala 155:71] + node _T_726 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 155:125] + node _T_727 = bits(intpriority_reg_we_14, 0, 0) @[el2_pic_ctl.scala 155:174] reg _T_728 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_727 : @[Reg.scala 28:19] _T_728 <= _T_726 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[14] <= _T_728 @[el2_pic_ctl.scala 163:71] - node _T_729 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] - node _T_730 = bits(intpriority_reg_we_15, 0, 0) @[el2_pic_ctl.scala 163:174] + intpriority_reg[14] <= _T_728 @[el2_pic_ctl.scala 155:71] + node _T_729 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 155:125] + node _T_730 = bits(intpriority_reg_we_15, 0, 0) @[el2_pic_ctl.scala 155:174] reg _T_731 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_730 : @[Reg.scala 28:19] _T_731 <= _T_729 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[15] <= _T_731 @[el2_pic_ctl.scala 163:71] - node _T_732 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] - node _T_733 = bits(intpriority_reg_we_16, 0, 0) @[el2_pic_ctl.scala 163:174] + intpriority_reg[15] <= _T_731 @[el2_pic_ctl.scala 155:71] + node _T_732 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 155:125] + node _T_733 = bits(intpriority_reg_we_16, 0, 0) @[el2_pic_ctl.scala 155:174] reg _T_734 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_733 : @[Reg.scala 28:19] _T_734 <= _T_732 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[16] <= _T_734 @[el2_pic_ctl.scala 163:71] - node _T_735 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] - node _T_736 = bits(intpriority_reg_we_17, 0, 0) @[el2_pic_ctl.scala 163:174] + intpriority_reg[16] <= _T_734 @[el2_pic_ctl.scala 155:71] + node _T_735 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 155:125] + node _T_736 = bits(intpriority_reg_we_17, 0, 0) @[el2_pic_ctl.scala 155:174] reg _T_737 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_736 : @[Reg.scala 28:19] _T_737 <= _T_735 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[17] <= _T_737 @[el2_pic_ctl.scala 163:71] - node _T_738 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] - node _T_739 = bits(intpriority_reg_we_18, 0, 0) @[el2_pic_ctl.scala 163:174] + intpriority_reg[17] <= _T_737 @[el2_pic_ctl.scala 155:71] + node _T_738 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 155:125] + node _T_739 = bits(intpriority_reg_we_18, 0, 0) @[el2_pic_ctl.scala 155:174] reg _T_740 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_739 : @[Reg.scala 28:19] _T_740 <= _T_738 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[18] <= _T_740 @[el2_pic_ctl.scala 163:71] - node _T_741 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] - node _T_742 = bits(intpriority_reg_we_19, 0, 0) @[el2_pic_ctl.scala 163:174] + intpriority_reg[18] <= _T_740 @[el2_pic_ctl.scala 155:71] + node _T_741 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 155:125] + node _T_742 = bits(intpriority_reg_we_19, 0, 0) @[el2_pic_ctl.scala 155:174] reg _T_743 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_742 : @[Reg.scala 28:19] _T_743 <= _T_741 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[19] <= _T_743 @[el2_pic_ctl.scala 163:71] - node _T_744 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] - node _T_745 = bits(intpriority_reg_we_20, 0, 0) @[el2_pic_ctl.scala 163:174] + intpriority_reg[19] <= _T_743 @[el2_pic_ctl.scala 155:71] + node _T_744 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 155:125] + node _T_745 = bits(intpriority_reg_we_20, 0, 0) @[el2_pic_ctl.scala 155:174] reg _T_746 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_745 : @[Reg.scala 28:19] _T_746 <= _T_744 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[20] <= _T_746 @[el2_pic_ctl.scala 163:71] - node _T_747 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] - node _T_748 = bits(intpriority_reg_we_21, 0, 0) @[el2_pic_ctl.scala 163:174] + intpriority_reg[20] <= _T_746 @[el2_pic_ctl.scala 155:71] + node _T_747 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 155:125] + node _T_748 = bits(intpriority_reg_we_21, 0, 0) @[el2_pic_ctl.scala 155:174] reg _T_749 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_748 : @[Reg.scala 28:19] _T_749 <= _T_747 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[21] <= _T_749 @[el2_pic_ctl.scala 163:71] - node _T_750 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] - node _T_751 = bits(intpriority_reg_we_22, 0, 0) @[el2_pic_ctl.scala 163:174] + intpriority_reg[21] <= _T_749 @[el2_pic_ctl.scala 155:71] + node _T_750 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 155:125] + node _T_751 = bits(intpriority_reg_we_22, 0, 0) @[el2_pic_ctl.scala 155:174] reg _T_752 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_751 : @[Reg.scala 28:19] _T_752 <= _T_750 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[22] <= _T_752 @[el2_pic_ctl.scala 163:71] - node _T_753 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] - node _T_754 = bits(intpriority_reg_we_23, 0, 0) @[el2_pic_ctl.scala 163:174] + intpriority_reg[22] <= _T_752 @[el2_pic_ctl.scala 155:71] + node _T_753 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 155:125] + node _T_754 = bits(intpriority_reg_we_23, 0, 0) @[el2_pic_ctl.scala 155:174] reg _T_755 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_754 : @[Reg.scala 28:19] _T_755 <= _T_753 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[23] <= _T_755 @[el2_pic_ctl.scala 163:71] - node _T_756 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] - node _T_757 = bits(intpriority_reg_we_24, 0, 0) @[el2_pic_ctl.scala 163:174] + intpriority_reg[23] <= _T_755 @[el2_pic_ctl.scala 155:71] + node _T_756 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 155:125] + node _T_757 = bits(intpriority_reg_we_24, 0, 0) @[el2_pic_ctl.scala 155:174] reg _T_758 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_757 : @[Reg.scala 28:19] _T_758 <= _T_756 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[24] <= _T_758 @[el2_pic_ctl.scala 163:71] - node _T_759 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] - node _T_760 = bits(intpriority_reg_we_25, 0, 0) @[el2_pic_ctl.scala 163:174] + intpriority_reg[24] <= _T_758 @[el2_pic_ctl.scala 155:71] + node _T_759 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 155:125] + node _T_760 = bits(intpriority_reg_we_25, 0, 0) @[el2_pic_ctl.scala 155:174] reg _T_761 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_760 : @[Reg.scala 28:19] _T_761 <= _T_759 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[25] <= _T_761 @[el2_pic_ctl.scala 163:71] - node _T_762 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] - node _T_763 = bits(intpriority_reg_we_26, 0, 0) @[el2_pic_ctl.scala 163:174] + intpriority_reg[25] <= _T_761 @[el2_pic_ctl.scala 155:71] + node _T_762 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 155:125] + node _T_763 = bits(intpriority_reg_we_26, 0, 0) @[el2_pic_ctl.scala 155:174] reg _T_764 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_763 : @[Reg.scala 28:19] _T_764 <= _T_762 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[26] <= _T_764 @[el2_pic_ctl.scala 163:71] - node _T_765 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] - node _T_766 = bits(intpriority_reg_we_27, 0, 0) @[el2_pic_ctl.scala 163:174] + intpriority_reg[26] <= _T_764 @[el2_pic_ctl.scala 155:71] + node _T_765 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 155:125] + node _T_766 = bits(intpriority_reg_we_27, 0, 0) @[el2_pic_ctl.scala 155:174] reg _T_767 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_766 : @[Reg.scala 28:19] _T_767 <= _T_765 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[27] <= _T_767 @[el2_pic_ctl.scala 163:71] - node _T_768 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] - node _T_769 = bits(intpriority_reg_we_28, 0, 0) @[el2_pic_ctl.scala 163:174] + intpriority_reg[27] <= _T_767 @[el2_pic_ctl.scala 155:71] + node _T_768 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 155:125] + node _T_769 = bits(intpriority_reg_we_28, 0, 0) @[el2_pic_ctl.scala 155:174] reg _T_770 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_769 : @[Reg.scala 28:19] _T_770 <= _T_768 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[28] <= _T_770 @[el2_pic_ctl.scala 163:71] - node _T_771 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] - node _T_772 = bits(intpriority_reg_we_29, 0, 0) @[el2_pic_ctl.scala 163:174] + intpriority_reg[28] <= _T_770 @[el2_pic_ctl.scala 155:71] + node _T_771 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 155:125] + node _T_772 = bits(intpriority_reg_we_29, 0, 0) @[el2_pic_ctl.scala 155:174] reg _T_773 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_772 : @[Reg.scala 28:19] _T_773 <= _T_771 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[29] <= _T_773 @[el2_pic_ctl.scala 163:71] - node _T_774 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] - node _T_775 = bits(intpriority_reg_we_30, 0, 0) @[el2_pic_ctl.scala 163:174] + intpriority_reg[29] <= _T_773 @[el2_pic_ctl.scala 155:71] + node _T_774 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 155:125] + node _T_775 = bits(intpriority_reg_we_30, 0, 0) @[el2_pic_ctl.scala 155:174] reg _T_776 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_775 : @[Reg.scala 28:19] _T_776 <= _T_774 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[30] <= _T_776 @[el2_pic_ctl.scala 163:71] - node _T_777 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] - node _T_778 = bits(intpriority_reg_we_31, 0, 0) @[el2_pic_ctl.scala 163:174] + intpriority_reg[30] <= _T_776 @[el2_pic_ctl.scala 155:71] + node _T_777 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 155:125] + node _T_778 = bits(intpriority_reg_we_31, 0, 0) @[el2_pic_ctl.scala 155:174] reg _T_779 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_778 : @[Reg.scala 28:19] _T_779 <= _T_777 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[31] <= _T_779 @[el2_pic_ctl.scala 163:71] - wire intenable_reg : UInt<1>[32] @[el2_pic_ctl.scala 164:32] - intenable_reg[0] <= UInt<1>("h00") @[el2_pic_ctl.scala 165:182] - node _T_780 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] - node _T_781 = bits(intenable_reg_we_1, 0, 0) @[el2_pic_ctl.scala 165:150] + intpriority_reg[31] <= _T_779 @[el2_pic_ctl.scala 155:71] + wire intenable_reg : UInt<1>[32] @[el2_pic_ctl.scala 156:32] + intenable_reg[0] <= UInt<1>("h00") @[el2_pic_ctl.scala 157:182] + node _T_780 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 157:122] + node _T_781 = bits(intenable_reg_we_1, 0, 0) @[el2_pic_ctl.scala 157:150] reg _T_782 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_781 : @[Reg.scala 28:19] _T_782 <= _T_780 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[1] <= _T_782 @[el2_pic_ctl.scala 165:68] - node _T_783 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] - node _T_784 = bits(intenable_reg_we_2, 0, 0) @[el2_pic_ctl.scala 165:150] + intenable_reg[1] <= _T_782 @[el2_pic_ctl.scala 157:68] + node _T_783 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 157:122] + node _T_784 = bits(intenable_reg_we_2, 0, 0) @[el2_pic_ctl.scala 157:150] reg _T_785 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_784 : @[Reg.scala 28:19] _T_785 <= _T_783 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[2] <= _T_785 @[el2_pic_ctl.scala 165:68] - node _T_786 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] - node _T_787 = bits(intenable_reg_we_3, 0, 0) @[el2_pic_ctl.scala 165:150] + intenable_reg[2] <= _T_785 @[el2_pic_ctl.scala 157:68] + node _T_786 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 157:122] + node _T_787 = bits(intenable_reg_we_3, 0, 0) @[el2_pic_ctl.scala 157:150] reg _T_788 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_787 : @[Reg.scala 28:19] _T_788 <= _T_786 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[3] <= _T_788 @[el2_pic_ctl.scala 165:68] - node _T_789 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] - node _T_790 = bits(intenable_reg_we_4, 0, 0) @[el2_pic_ctl.scala 165:150] + intenable_reg[3] <= _T_788 @[el2_pic_ctl.scala 157:68] + node _T_789 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 157:122] + node _T_790 = bits(intenable_reg_we_4, 0, 0) @[el2_pic_ctl.scala 157:150] reg _T_791 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_790 : @[Reg.scala 28:19] _T_791 <= _T_789 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[4] <= _T_791 @[el2_pic_ctl.scala 165:68] - node _T_792 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] - node _T_793 = bits(intenable_reg_we_5, 0, 0) @[el2_pic_ctl.scala 165:150] + intenable_reg[4] <= _T_791 @[el2_pic_ctl.scala 157:68] + node _T_792 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 157:122] + node _T_793 = bits(intenable_reg_we_5, 0, 0) @[el2_pic_ctl.scala 157:150] reg _T_794 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_793 : @[Reg.scala 28:19] _T_794 <= _T_792 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[5] <= _T_794 @[el2_pic_ctl.scala 165:68] - node _T_795 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] - node _T_796 = bits(intenable_reg_we_6, 0, 0) @[el2_pic_ctl.scala 165:150] + intenable_reg[5] <= _T_794 @[el2_pic_ctl.scala 157:68] + node _T_795 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 157:122] + node _T_796 = bits(intenable_reg_we_6, 0, 0) @[el2_pic_ctl.scala 157:150] reg _T_797 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_796 : @[Reg.scala 28:19] _T_797 <= _T_795 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[6] <= _T_797 @[el2_pic_ctl.scala 165:68] - node _T_798 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] - node _T_799 = bits(intenable_reg_we_7, 0, 0) @[el2_pic_ctl.scala 165:150] + intenable_reg[6] <= _T_797 @[el2_pic_ctl.scala 157:68] + node _T_798 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 157:122] + node _T_799 = bits(intenable_reg_we_7, 0, 0) @[el2_pic_ctl.scala 157:150] reg _T_800 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_799 : @[Reg.scala 28:19] _T_800 <= _T_798 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[7] <= _T_800 @[el2_pic_ctl.scala 165:68] - node _T_801 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] - node _T_802 = bits(intenable_reg_we_8, 0, 0) @[el2_pic_ctl.scala 165:150] + intenable_reg[7] <= _T_800 @[el2_pic_ctl.scala 157:68] + node _T_801 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 157:122] + node _T_802 = bits(intenable_reg_we_8, 0, 0) @[el2_pic_ctl.scala 157:150] reg _T_803 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_802 : @[Reg.scala 28:19] _T_803 <= _T_801 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[8] <= _T_803 @[el2_pic_ctl.scala 165:68] - node _T_804 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] - node _T_805 = bits(intenable_reg_we_9, 0, 0) @[el2_pic_ctl.scala 165:150] + intenable_reg[8] <= _T_803 @[el2_pic_ctl.scala 157:68] + node _T_804 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 157:122] + node _T_805 = bits(intenable_reg_we_9, 0, 0) @[el2_pic_ctl.scala 157:150] reg _T_806 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_805 : @[Reg.scala 28:19] _T_806 <= _T_804 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[9] <= _T_806 @[el2_pic_ctl.scala 165:68] - node _T_807 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] - node _T_808 = bits(intenable_reg_we_10, 0, 0) @[el2_pic_ctl.scala 165:150] + intenable_reg[9] <= _T_806 @[el2_pic_ctl.scala 157:68] + node _T_807 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 157:122] + node _T_808 = bits(intenable_reg_we_10, 0, 0) @[el2_pic_ctl.scala 157:150] reg _T_809 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_808 : @[Reg.scala 28:19] _T_809 <= _T_807 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[10] <= _T_809 @[el2_pic_ctl.scala 165:68] - node _T_810 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] - node _T_811 = bits(intenable_reg_we_11, 0, 0) @[el2_pic_ctl.scala 165:150] + intenable_reg[10] <= _T_809 @[el2_pic_ctl.scala 157:68] + node _T_810 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 157:122] + node _T_811 = bits(intenable_reg_we_11, 0, 0) @[el2_pic_ctl.scala 157:150] reg _T_812 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_811 : @[Reg.scala 28:19] _T_812 <= _T_810 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[11] <= _T_812 @[el2_pic_ctl.scala 165:68] - node _T_813 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] - node _T_814 = bits(intenable_reg_we_12, 0, 0) @[el2_pic_ctl.scala 165:150] + intenable_reg[11] <= _T_812 @[el2_pic_ctl.scala 157:68] + node _T_813 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 157:122] + node _T_814 = bits(intenable_reg_we_12, 0, 0) @[el2_pic_ctl.scala 157:150] reg _T_815 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_814 : @[Reg.scala 28:19] _T_815 <= _T_813 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[12] <= _T_815 @[el2_pic_ctl.scala 165:68] - node _T_816 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] - node _T_817 = bits(intenable_reg_we_13, 0, 0) @[el2_pic_ctl.scala 165:150] + intenable_reg[12] <= _T_815 @[el2_pic_ctl.scala 157:68] + node _T_816 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 157:122] + node _T_817 = bits(intenable_reg_we_13, 0, 0) @[el2_pic_ctl.scala 157:150] reg _T_818 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_817 : @[Reg.scala 28:19] _T_818 <= _T_816 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[13] <= _T_818 @[el2_pic_ctl.scala 165:68] - node _T_819 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] - node _T_820 = bits(intenable_reg_we_14, 0, 0) @[el2_pic_ctl.scala 165:150] + intenable_reg[13] <= _T_818 @[el2_pic_ctl.scala 157:68] + node _T_819 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 157:122] + node _T_820 = bits(intenable_reg_we_14, 0, 0) @[el2_pic_ctl.scala 157:150] reg _T_821 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_820 : @[Reg.scala 28:19] _T_821 <= _T_819 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[14] <= _T_821 @[el2_pic_ctl.scala 165:68] - node _T_822 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] - node _T_823 = bits(intenable_reg_we_15, 0, 0) @[el2_pic_ctl.scala 165:150] + intenable_reg[14] <= _T_821 @[el2_pic_ctl.scala 157:68] + node _T_822 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 157:122] + node _T_823 = bits(intenable_reg_we_15, 0, 0) @[el2_pic_ctl.scala 157:150] reg _T_824 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_823 : @[Reg.scala 28:19] _T_824 <= _T_822 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[15] <= _T_824 @[el2_pic_ctl.scala 165:68] - node _T_825 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] - node _T_826 = bits(intenable_reg_we_16, 0, 0) @[el2_pic_ctl.scala 165:150] + intenable_reg[15] <= _T_824 @[el2_pic_ctl.scala 157:68] + node _T_825 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 157:122] + node _T_826 = bits(intenable_reg_we_16, 0, 0) @[el2_pic_ctl.scala 157:150] reg _T_827 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_826 : @[Reg.scala 28:19] _T_827 <= _T_825 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[16] <= _T_827 @[el2_pic_ctl.scala 165:68] - node _T_828 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] - node _T_829 = bits(intenable_reg_we_17, 0, 0) @[el2_pic_ctl.scala 165:150] + intenable_reg[16] <= _T_827 @[el2_pic_ctl.scala 157:68] + node _T_828 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 157:122] + node _T_829 = bits(intenable_reg_we_17, 0, 0) @[el2_pic_ctl.scala 157:150] reg _T_830 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_829 : @[Reg.scala 28:19] _T_830 <= _T_828 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[17] <= _T_830 @[el2_pic_ctl.scala 165:68] - node _T_831 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] - node _T_832 = bits(intenable_reg_we_18, 0, 0) @[el2_pic_ctl.scala 165:150] + intenable_reg[17] <= _T_830 @[el2_pic_ctl.scala 157:68] + node _T_831 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 157:122] + node _T_832 = bits(intenable_reg_we_18, 0, 0) @[el2_pic_ctl.scala 157:150] reg _T_833 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_832 : @[Reg.scala 28:19] _T_833 <= _T_831 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[18] <= _T_833 @[el2_pic_ctl.scala 165:68] - node _T_834 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] - node _T_835 = bits(intenable_reg_we_19, 0, 0) @[el2_pic_ctl.scala 165:150] + intenable_reg[18] <= _T_833 @[el2_pic_ctl.scala 157:68] + node _T_834 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 157:122] + node _T_835 = bits(intenable_reg_we_19, 0, 0) @[el2_pic_ctl.scala 157:150] reg _T_836 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_835 : @[Reg.scala 28:19] _T_836 <= _T_834 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[19] <= _T_836 @[el2_pic_ctl.scala 165:68] - node _T_837 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] - node _T_838 = bits(intenable_reg_we_20, 0, 0) @[el2_pic_ctl.scala 165:150] + intenable_reg[19] <= _T_836 @[el2_pic_ctl.scala 157:68] + node _T_837 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 157:122] + node _T_838 = bits(intenable_reg_we_20, 0, 0) @[el2_pic_ctl.scala 157:150] reg _T_839 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_838 : @[Reg.scala 28:19] _T_839 <= _T_837 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[20] <= _T_839 @[el2_pic_ctl.scala 165:68] - node _T_840 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] - node _T_841 = bits(intenable_reg_we_21, 0, 0) @[el2_pic_ctl.scala 165:150] + intenable_reg[20] <= _T_839 @[el2_pic_ctl.scala 157:68] + node _T_840 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 157:122] + node _T_841 = bits(intenable_reg_we_21, 0, 0) @[el2_pic_ctl.scala 157:150] reg _T_842 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_841 : @[Reg.scala 28:19] _T_842 <= _T_840 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[21] <= _T_842 @[el2_pic_ctl.scala 165:68] - node _T_843 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] - node _T_844 = bits(intenable_reg_we_22, 0, 0) @[el2_pic_ctl.scala 165:150] + intenable_reg[21] <= _T_842 @[el2_pic_ctl.scala 157:68] + node _T_843 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 157:122] + node _T_844 = bits(intenable_reg_we_22, 0, 0) @[el2_pic_ctl.scala 157:150] reg _T_845 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_844 : @[Reg.scala 28:19] _T_845 <= _T_843 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[22] <= _T_845 @[el2_pic_ctl.scala 165:68] - node _T_846 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] - node _T_847 = bits(intenable_reg_we_23, 0, 0) @[el2_pic_ctl.scala 165:150] + intenable_reg[22] <= _T_845 @[el2_pic_ctl.scala 157:68] + node _T_846 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 157:122] + node _T_847 = bits(intenable_reg_we_23, 0, 0) @[el2_pic_ctl.scala 157:150] reg _T_848 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_847 : @[Reg.scala 28:19] _T_848 <= _T_846 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[23] <= _T_848 @[el2_pic_ctl.scala 165:68] - node _T_849 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] - node _T_850 = bits(intenable_reg_we_24, 0, 0) @[el2_pic_ctl.scala 165:150] + intenable_reg[23] <= _T_848 @[el2_pic_ctl.scala 157:68] + node _T_849 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 157:122] + node _T_850 = bits(intenable_reg_we_24, 0, 0) @[el2_pic_ctl.scala 157:150] reg _T_851 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_850 : @[Reg.scala 28:19] _T_851 <= _T_849 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[24] <= _T_851 @[el2_pic_ctl.scala 165:68] - node _T_852 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] - node _T_853 = bits(intenable_reg_we_25, 0, 0) @[el2_pic_ctl.scala 165:150] + intenable_reg[24] <= _T_851 @[el2_pic_ctl.scala 157:68] + node _T_852 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 157:122] + node _T_853 = bits(intenable_reg_we_25, 0, 0) @[el2_pic_ctl.scala 157:150] reg _T_854 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_853 : @[Reg.scala 28:19] _T_854 <= _T_852 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[25] <= _T_854 @[el2_pic_ctl.scala 165:68] - node _T_855 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] - node _T_856 = bits(intenable_reg_we_26, 0, 0) @[el2_pic_ctl.scala 165:150] + intenable_reg[25] <= _T_854 @[el2_pic_ctl.scala 157:68] + node _T_855 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 157:122] + node _T_856 = bits(intenable_reg_we_26, 0, 0) @[el2_pic_ctl.scala 157:150] reg _T_857 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_856 : @[Reg.scala 28:19] _T_857 <= _T_855 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[26] <= _T_857 @[el2_pic_ctl.scala 165:68] - node _T_858 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] - node _T_859 = bits(intenable_reg_we_27, 0, 0) @[el2_pic_ctl.scala 165:150] + intenable_reg[26] <= _T_857 @[el2_pic_ctl.scala 157:68] + node _T_858 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 157:122] + node _T_859 = bits(intenable_reg_we_27, 0, 0) @[el2_pic_ctl.scala 157:150] reg _T_860 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_859 : @[Reg.scala 28:19] _T_860 <= _T_858 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[27] <= _T_860 @[el2_pic_ctl.scala 165:68] - node _T_861 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] - node _T_862 = bits(intenable_reg_we_28, 0, 0) @[el2_pic_ctl.scala 165:150] + intenable_reg[27] <= _T_860 @[el2_pic_ctl.scala 157:68] + node _T_861 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 157:122] + node _T_862 = bits(intenable_reg_we_28, 0, 0) @[el2_pic_ctl.scala 157:150] reg _T_863 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_862 : @[Reg.scala 28:19] _T_863 <= _T_861 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[28] <= _T_863 @[el2_pic_ctl.scala 165:68] - node _T_864 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] - node _T_865 = bits(intenable_reg_we_29, 0, 0) @[el2_pic_ctl.scala 165:150] + intenable_reg[28] <= _T_863 @[el2_pic_ctl.scala 157:68] + node _T_864 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 157:122] + node _T_865 = bits(intenable_reg_we_29, 0, 0) @[el2_pic_ctl.scala 157:150] reg _T_866 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_865 : @[Reg.scala 28:19] _T_866 <= _T_864 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[29] <= _T_866 @[el2_pic_ctl.scala 165:68] - node _T_867 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] - node _T_868 = bits(intenable_reg_we_30, 0, 0) @[el2_pic_ctl.scala 165:150] + intenable_reg[29] <= _T_866 @[el2_pic_ctl.scala 157:68] + node _T_867 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 157:122] + node _T_868 = bits(intenable_reg_we_30, 0, 0) @[el2_pic_ctl.scala 157:150] reg _T_869 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_868 : @[Reg.scala 28:19] _T_869 <= _T_867 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[30] <= _T_869 @[el2_pic_ctl.scala 165:68] - node _T_870 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] - node _T_871 = bits(intenable_reg_we_31, 0, 0) @[el2_pic_ctl.scala 165:150] + intenable_reg[30] <= _T_869 @[el2_pic_ctl.scala 157:68] + node _T_870 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 157:122] + node _T_871 = bits(intenable_reg_we_31, 0, 0) @[el2_pic_ctl.scala 157:150] reg _T_872 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_871 : @[Reg.scala 28:19] _T_872 <= _T_870 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[31] <= _T_872 @[el2_pic_ctl.scala 165:68] - wire gw_config_reg : UInt<2>[32] @[el2_pic_ctl.scala 166:32] - gw_config_reg[0] <= UInt<2>("h00") @[el2_pic_ctl.scala 167:190] - node _T_873 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] - node _T_874 = bits(gw_config_reg_we_1, 0, 0) @[el2_pic_ctl.scala 167:156] + intenable_reg[31] <= _T_872 @[el2_pic_ctl.scala 157:68] + wire gw_config_reg : UInt<2>[32] @[el2_pic_ctl.scala 158:32] + gw_config_reg[0] <= UInt<2>("h00") @[el2_pic_ctl.scala 159:190] + node _T_873 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 159:126] + node _T_874 = bits(gw_config_reg_we_1, 0, 0) @[el2_pic_ctl.scala 159:156] reg _T_875 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_874 : @[Reg.scala 28:19] _T_875 <= _T_873 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[1] <= _T_875 @[el2_pic_ctl.scala 167:70] - node _T_876 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] - node _T_877 = bits(gw_config_reg_we_2, 0, 0) @[el2_pic_ctl.scala 167:156] + gw_config_reg[1] <= _T_875 @[el2_pic_ctl.scala 159:70] + node _T_876 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 159:126] + node _T_877 = bits(gw_config_reg_we_2, 0, 0) @[el2_pic_ctl.scala 159:156] reg _T_878 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_877 : @[Reg.scala 28:19] _T_878 <= _T_876 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[2] <= _T_878 @[el2_pic_ctl.scala 167:70] - node _T_879 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] - node _T_880 = bits(gw_config_reg_we_3, 0, 0) @[el2_pic_ctl.scala 167:156] + gw_config_reg[2] <= _T_878 @[el2_pic_ctl.scala 159:70] + node _T_879 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 159:126] + node _T_880 = bits(gw_config_reg_we_3, 0, 0) @[el2_pic_ctl.scala 159:156] reg _T_881 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_880 : @[Reg.scala 28:19] _T_881 <= _T_879 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[3] <= _T_881 @[el2_pic_ctl.scala 167:70] - node _T_882 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] - node _T_883 = bits(gw_config_reg_we_4, 0, 0) @[el2_pic_ctl.scala 167:156] + gw_config_reg[3] <= _T_881 @[el2_pic_ctl.scala 159:70] + node _T_882 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 159:126] + node _T_883 = bits(gw_config_reg_we_4, 0, 0) @[el2_pic_ctl.scala 159:156] reg _T_884 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_883 : @[Reg.scala 28:19] _T_884 <= _T_882 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[4] <= _T_884 @[el2_pic_ctl.scala 167:70] - node _T_885 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] - node _T_886 = bits(gw_config_reg_we_5, 0, 0) @[el2_pic_ctl.scala 167:156] + gw_config_reg[4] <= _T_884 @[el2_pic_ctl.scala 159:70] + node _T_885 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 159:126] + node _T_886 = bits(gw_config_reg_we_5, 0, 0) @[el2_pic_ctl.scala 159:156] reg _T_887 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_886 : @[Reg.scala 28:19] _T_887 <= _T_885 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[5] <= _T_887 @[el2_pic_ctl.scala 167:70] - node _T_888 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] - node _T_889 = bits(gw_config_reg_we_6, 0, 0) @[el2_pic_ctl.scala 167:156] + gw_config_reg[5] <= _T_887 @[el2_pic_ctl.scala 159:70] + node _T_888 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 159:126] + node _T_889 = bits(gw_config_reg_we_6, 0, 0) @[el2_pic_ctl.scala 159:156] reg _T_890 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_889 : @[Reg.scala 28:19] _T_890 <= _T_888 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[6] <= _T_890 @[el2_pic_ctl.scala 167:70] - node _T_891 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] - node _T_892 = bits(gw_config_reg_we_7, 0, 0) @[el2_pic_ctl.scala 167:156] + gw_config_reg[6] <= _T_890 @[el2_pic_ctl.scala 159:70] + node _T_891 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 159:126] + node _T_892 = bits(gw_config_reg_we_7, 0, 0) @[el2_pic_ctl.scala 159:156] reg _T_893 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_892 : @[Reg.scala 28:19] _T_893 <= _T_891 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[7] <= _T_893 @[el2_pic_ctl.scala 167:70] - node _T_894 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] - node _T_895 = bits(gw_config_reg_we_8, 0, 0) @[el2_pic_ctl.scala 167:156] + gw_config_reg[7] <= _T_893 @[el2_pic_ctl.scala 159:70] + node _T_894 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 159:126] + node _T_895 = bits(gw_config_reg_we_8, 0, 0) @[el2_pic_ctl.scala 159:156] reg _T_896 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_895 : @[Reg.scala 28:19] _T_896 <= _T_894 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[8] <= _T_896 @[el2_pic_ctl.scala 167:70] - node _T_897 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] - node _T_898 = bits(gw_config_reg_we_9, 0, 0) @[el2_pic_ctl.scala 167:156] + gw_config_reg[8] <= _T_896 @[el2_pic_ctl.scala 159:70] + node _T_897 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 159:126] + node _T_898 = bits(gw_config_reg_we_9, 0, 0) @[el2_pic_ctl.scala 159:156] reg _T_899 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_898 : @[Reg.scala 28:19] _T_899 <= _T_897 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[9] <= _T_899 @[el2_pic_ctl.scala 167:70] - node _T_900 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] - node _T_901 = bits(gw_config_reg_we_10, 0, 0) @[el2_pic_ctl.scala 167:156] + gw_config_reg[9] <= _T_899 @[el2_pic_ctl.scala 159:70] + node _T_900 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 159:126] + node _T_901 = bits(gw_config_reg_we_10, 0, 0) @[el2_pic_ctl.scala 159:156] reg _T_902 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_901 : @[Reg.scala 28:19] _T_902 <= _T_900 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[10] <= _T_902 @[el2_pic_ctl.scala 167:70] - node _T_903 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] - node _T_904 = bits(gw_config_reg_we_11, 0, 0) @[el2_pic_ctl.scala 167:156] + gw_config_reg[10] <= _T_902 @[el2_pic_ctl.scala 159:70] + node _T_903 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 159:126] + node _T_904 = bits(gw_config_reg_we_11, 0, 0) @[el2_pic_ctl.scala 159:156] reg _T_905 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_904 : @[Reg.scala 28:19] _T_905 <= _T_903 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[11] <= _T_905 @[el2_pic_ctl.scala 167:70] - node _T_906 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] - node _T_907 = bits(gw_config_reg_we_12, 0, 0) @[el2_pic_ctl.scala 167:156] + gw_config_reg[11] <= _T_905 @[el2_pic_ctl.scala 159:70] + node _T_906 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 159:126] + node _T_907 = bits(gw_config_reg_we_12, 0, 0) @[el2_pic_ctl.scala 159:156] reg _T_908 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_907 : @[Reg.scala 28:19] _T_908 <= _T_906 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[12] <= _T_908 @[el2_pic_ctl.scala 167:70] - node _T_909 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] - node _T_910 = bits(gw_config_reg_we_13, 0, 0) @[el2_pic_ctl.scala 167:156] + gw_config_reg[12] <= _T_908 @[el2_pic_ctl.scala 159:70] + node _T_909 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 159:126] + node _T_910 = bits(gw_config_reg_we_13, 0, 0) @[el2_pic_ctl.scala 159:156] reg _T_911 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_910 : @[Reg.scala 28:19] _T_911 <= _T_909 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[13] <= _T_911 @[el2_pic_ctl.scala 167:70] - node _T_912 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] - node _T_913 = bits(gw_config_reg_we_14, 0, 0) @[el2_pic_ctl.scala 167:156] + gw_config_reg[13] <= _T_911 @[el2_pic_ctl.scala 159:70] + node _T_912 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 159:126] + node _T_913 = bits(gw_config_reg_we_14, 0, 0) @[el2_pic_ctl.scala 159:156] reg _T_914 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_913 : @[Reg.scala 28:19] _T_914 <= _T_912 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[14] <= _T_914 @[el2_pic_ctl.scala 167:70] - node _T_915 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] - node _T_916 = bits(gw_config_reg_we_15, 0, 0) @[el2_pic_ctl.scala 167:156] + gw_config_reg[14] <= _T_914 @[el2_pic_ctl.scala 159:70] + node _T_915 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 159:126] + node _T_916 = bits(gw_config_reg_we_15, 0, 0) @[el2_pic_ctl.scala 159:156] reg _T_917 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_916 : @[Reg.scala 28:19] _T_917 <= _T_915 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[15] <= _T_917 @[el2_pic_ctl.scala 167:70] - node _T_918 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] - node _T_919 = bits(gw_config_reg_we_16, 0, 0) @[el2_pic_ctl.scala 167:156] + gw_config_reg[15] <= _T_917 @[el2_pic_ctl.scala 159:70] + node _T_918 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 159:126] + node _T_919 = bits(gw_config_reg_we_16, 0, 0) @[el2_pic_ctl.scala 159:156] reg _T_920 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_919 : @[Reg.scala 28:19] _T_920 <= _T_918 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[16] <= _T_920 @[el2_pic_ctl.scala 167:70] - node _T_921 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] - node _T_922 = bits(gw_config_reg_we_17, 0, 0) @[el2_pic_ctl.scala 167:156] + gw_config_reg[16] <= _T_920 @[el2_pic_ctl.scala 159:70] + node _T_921 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 159:126] + node _T_922 = bits(gw_config_reg_we_17, 0, 0) @[el2_pic_ctl.scala 159:156] reg _T_923 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_922 : @[Reg.scala 28:19] _T_923 <= _T_921 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[17] <= _T_923 @[el2_pic_ctl.scala 167:70] - node _T_924 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] - node _T_925 = bits(gw_config_reg_we_18, 0, 0) @[el2_pic_ctl.scala 167:156] + gw_config_reg[17] <= _T_923 @[el2_pic_ctl.scala 159:70] + node _T_924 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 159:126] + node _T_925 = bits(gw_config_reg_we_18, 0, 0) @[el2_pic_ctl.scala 159:156] reg _T_926 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_925 : @[Reg.scala 28:19] _T_926 <= _T_924 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[18] <= _T_926 @[el2_pic_ctl.scala 167:70] - node _T_927 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] - node _T_928 = bits(gw_config_reg_we_19, 0, 0) @[el2_pic_ctl.scala 167:156] + gw_config_reg[18] <= _T_926 @[el2_pic_ctl.scala 159:70] + node _T_927 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 159:126] + node _T_928 = bits(gw_config_reg_we_19, 0, 0) @[el2_pic_ctl.scala 159:156] reg _T_929 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_928 : @[Reg.scala 28:19] _T_929 <= _T_927 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[19] <= _T_929 @[el2_pic_ctl.scala 167:70] - node _T_930 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] - node _T_931 = bits(gw_config_reg_we_20, 0, 0) @[el2_pic_ctl.scala 167:156] + gw_config_reg[19] <= _T_929 @[el2_pic_ctl.scala 159:70] + node _T_930 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 159:126] + node _T_931 = bits(gw_config_reg_we_20, 0, 0) @[el2_pic_ctl.scala 159:156] reg _T_932 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_931 : @[Reg.scala 28:19] _T_932 <= _T_930 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[20] <= _T_932 @[el2_pic_ctl.scala 167:70] - node _T_933 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] - node _T_934 = bits(gw_config_reg_we_21, 0, 0) @[el2_pic_ctl.scala 167:156] + gw_config_reg[20] <= _T_932 @[el2_pic_ctl.scala 159:70] + node _T_933 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 159:126] + node _T_934 = bits(gw_config_reg_we_21, 0, 0) @[el2_pic_ctl.scala 159:156] reg _T_935 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_934 : @[Reg.scala 28:19] _T_935 <= _T_933 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[21] <= _T_935 @[el2_pic_ctl.scala 167:70] - node _T_936 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] - node _T_937 = bits(gw_config_reg_we_22, 0, 0) @[el2_pic_ctl.scala 167:156] + gw_config_reg[21] <= _T_935 @[el2_pic_ctl.scala 159:70] + node _T_936 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 159:126] + node _T_937 = bits(gw_config_reg_we_22, 0, 0) @[el2_pic_ctl.scala 159:156] reg _T_938 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_937 : @[Reg.scala 28:19] _T_938 <= _T_936 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[22] <= _T_938 @[el2_pic_ctl.scala 167:70] - node _T_939 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] - node _T_940 = bits(gw_config_reg_we_23, 0, 0) @[el2_pic_ctl.scala 167:156] + gw_config_reg[22] <= _T_938 @[el2_pic_ctl.scala 159:70] + node _T_939 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 159:126] + node _T_940 = bits(gw_config_reg_we_23, 0, 0) @[el2_pic_ctl.scala 159:156] reg _T_941 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_940 : @[Reg.scala 28:19] _T_941 <= _T_939 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[23] <= _T_941 @[el2_pic_ctl.scala 167:70] - node _T_942 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] - node _T_943 = bits(gw_config_reg_we_24, 0, 0) @[el2_pic_ctl.scala 167:156] + gw_config_reg[23] <= _T_941 @[el2_pic_ctl.scala 159:70] + node _T_942 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 159:126] + node _T_943 = bits(gw_config_reg_we_24, 0, 0) @[el2_pic_ctl.scala 159:156] reg _T_944 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_943 : @[Reg.scala 28:19] _T_944 <= _T_942 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[24] <= _T_944 @[el2_pic_ctl.scala 167:70] - node _T_945 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] - node _T_946 = bits(gw_config_reg_we_25, 0, 0) @[el2_pic_ctl.scala 167:156] + gw_config_reg[24] <= _T_944 @[el2_pic_ctl.scala 159:70] + node _T_945 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 159:126] + node _T_946 = bits(gw_config_reg_we_25, 0, 0) @[el2_pic_ctl.scala 159:156] reg _T_947 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_946 : @[Reg.scala 28:19] _T_947 <= _T_945 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[25] <= _T_947 @[el2_pic_ctl.scala 167:70] - node _T_948 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] - node _T_949 = bits(gw_config_reg_we_26, 0, 0) @[el2_pic_ctl.scala 167:156] + gw_config_reg[25] <= _T_947 @[el2_pic_ctl.scala 159:70] + node _T_948 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 159:126] + node _T_949 = bits(gw_config_reg_we_26, 0, 0) @[el2_pic_ctl.scala 159:156] reg _T_950 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_949 : @[Reg.scala 28:19] _T_950 <= _T_948 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[26] <= _T_950 @[el2_pic_ctl.scala 167:70] - node _T_951 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] - node _T_952 = bits(gw_config_reg_we_27, 0, 0) @[el2_pic_ctl.scala 167:156] + gw_config_reg[26] <= _T_950 @[el2_pic_ctl.scala 159:70] + node _T_951 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 159:126] + node _T_952 = bits(gw_config_reg_we_27, 0, 0) @[el2_pic_ctl.scala 159:156] reg _T_953 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_952 : @[Reg.scala 28:19] _T_953 <= _T_951 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[27] <= _T_953 @[el2_pic_ctl.scala 167:70] - node _T_954 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] - node _T_955 = bits(gw_config_reg_we_28, 0, 0) @[el2_pic_ctl.scala 167:156] + gw_config_reg[27] <= _T_953 @[el2_pic_ctl.scala 159:70] + node _T_954 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 159:126] + node _T_955 = bits(gw_config_reg_we_28, 0, 0) @[el2_pic_ctl.scala 159:156] reg _T_956 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_955 : @[Reg.scala 28:19] _T_956 <= _T_954 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[28] <= _T_956 @[el2_pic_ctl.scala 167:70] - node _T_957 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] - node _T_958 = bits(gw_config_reg_we_29, 0, 0) @[el2_pic_ctl.scala 167:156] + gw_config_reg[28] <= _T_956 @[el2_pic_ctl.scala 159:70] + node _T_957 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 159:126] + node _T_958 = bits(gw_config_reg_we_29, 0, 0) @[el2_pic_ctl.scala 159:156] reg _T_959 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_958 : @[Reg.scala 28:19] _T_959 <= _T_957 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[29] <= _T_959 @[el2_pic_ctl.scala 167:70] - node _T_960 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] - node _T_961 = bits(gw_config_reg_we_30, 0, 0) @[el2_pic_ctl.scala 167:156] + gw_config_reg[29] <= _T_959 @[el2_pic_ctl.scala 159:70] + node _T_960 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 159:126] + node _T_961 = bits(gw_config_reg_we_30, 0, 0) @[el2_pic_ctl.scala 159:156] reg _T_962 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_961 : @[Reg.scala 28:19] _T_962 <= _T_960 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[30] <= _T_962 @[el2_pic_ctl.scala 167:70] - node _T_963 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] - node _T_964 = bits(gw_config_reg_we_31, 0, 0) @[el2_pic_ctl.scala 167:156] + gw_config_reg[30] <= _T_962 @[el2_pic_ctl.scala 159:70] + node _T_963 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 159:126] + node _T_964 = bits(gw_config_reg_we_31, 0, 0) @[el2_pic_ctl.scala 159:156] reg _T_965 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_964 : @[Reg.scala 28:19] _T_965 <= _T_963 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[31] <= _T_965 @[el2_pic_ctl.scala 167:70] - node _T_966 = bits(extintsrc_req_sync, 1, 1) @[el2_pic_ctl.scala 170:43] - node _T_967 = bits(gw_config_reg[1], 0, 0) @[el2_pic_ctl.scala 170:64] - node _T_968 = bits(gw_config_reg[1], 1, 1) @[el2_pic_ctl.scala 170:85] - node _T_969 = bits(gw_clear_reg_we_1, 0, 0) @[el2_pic_ctl.scala 170:115] + gw_config_reg[31] <= _T_965 @[el2_pic_ctl.scala 159:70] + node _T_966 = bits(extintsrc_req_sync, 1, 1) @[el2_pic_ctl.scala 162:43] + node _T_967 = bits(gw_config_reg[1], 0, 0) @[el2_pic_ctl.scala 162:64] + node _T_968 = bits(gw_config_reg[1], 1, 1) @[el2_pic_ctl.scala 162:85] + node _T_969 = bits(gw_clear_reg_we_1, 0, 0) @[el2_pic_ctl.scala 162:115] wire gw_int_pending : UInt<1> gw_int_pending <= UInt<1>("h00") - node _T_970 = xor(_T_966, _T_967) @[el2_pic_ctl.scala 45:50] - node _T_971 = eq(_T_969, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] - node _T_972 = and(gw_int_pending, _T_971) @[el2_pic_ctl.scala 45:90] - node gw_int_pending_in = or(_T_970, _T_972) @[el2_pic_ctl.scala 45:72] - reg _T_973 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] - _T_973 <= gw_int_pending_in @[el2_pic_ctl.scala 46:30] - gw_int_pending <= _T_973 @[el2_pic_ctl.scala 46:20] - node _T_974 = bits(_T_968, 0, 0) @[el2_pic_ctl.scala 47:30] - node _T_975 = xor(_T_966, _T_967) @[el2_pic_ctl.scala 47:55] - node _T_976 = or(_T_975, gw_int_pending) @[el2_pic_ctl.scala 47:78] - node _T_977 = xor(_T_966, _T_967) @[el2_pic_ctl.scala 47:117] - node extintsrc_req_gw_1 = mux(_T_974, _T_976, _T_977) @[el2_pic_ctl.scala 47:8] - node _T_978 = bits(extintsrc_req_sync, 2, 2) @[el2_pic_ctl.scala 170:43] - node _T_979 = bits(gw_config_reg[2], 0, 0) @[el2_pic_ctl.scala 170:64] - node _T_980 = bits(gw_config_reg[2], 1, 1) @[el2_pic_ctl.scala 170:85] - node _T_981 = bits(gw_clear_reg_we_2, 0, 0) @[el2_pic_ctl.scala 170:115] + node _T_970 = xor(_T_966, _T_967) @[el2_pic_ctl.scala 37:50] + node _T_971 = eq(_T_969, UInt<1>("h00")) @[el2_pic_ctl.scala 37:92] + node _T_972 = and(gw_int_pending, _T_971) @[el2_pic_ctl.scala 37:90] + node gw_int_pending_in = or(_T_970, _T_972) @[el2_pic_ctl.scala 37:72] + reg _T_973 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 38:30] + _T_973 <= gw_int_pending_in @[el2_pic_ctl.scala 38:30] + gw_int_pending <= _T_973 @[el2_pic_ctl.scala 38:20] + node _T_974 = bits(_T_968, 0, 0) @[el2_pic_ctl.scala 39:30] + node _T_975 = xor(_T_966, _T_967) @[el2_pic_ctl.scala 39:55] + node _T_976 = or(_T_975, gw_int_pending) @[el2_pic_ctl.scala 39:78] + node _T_977 = xor(_T_966, _T_967) @[el2_pic_ctl.scala 39:117] + node extintsrc_req_gw_1 = mux(_T_974, _T_976, _T_977) @[el2_pic_ctl.scala 39:8] + node _T_978 = bits(extintsrc_req_sync, 2, 2) @[el2_pic_ctl.scala 162:43] + node _T_979 = bits(gw_config_reg[2], 0, 0) @[el2_pic_ctl.scala 162:64] + node _T_980 = bits(gw_config_reg[2], 1, 1) @[el2_pic_ctl.scala 162:85] + node _T_981 = bits(gw_clear_reg_we_2, 0, 0) @[el2_pic_ctl.scala 162:115] wire gw_int_pending_1 : UInt<1> gw_int_pending_1 <= UInt<1>("h00") - node _T_982 = xor(_T_978, _T_979) @[el2_pic_ctl.scala 45:50] - node _T_983 = eq(_T_981, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] - node _T_984 = and(gw_int_pending_1, _T_983) @[el2_pic_ctl.scala 45:90] - node gw_int_pending_in_1 = or(_T_982, _T_984) @[el2_pic_ctl.scala 45:72] - reg _T_985 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] - _T_985 <= gw_int_pending_in_1 @[el2_pic_ctl.scala 46:30] - gw_int_pending_1 <= _T_985 @[el2_pic_ctl.scala 46:20] - node _T_986 = bits(_T_980, 0, 0) @[el2_pic_ctl.scala 47:30] - node _T_987 = xor(_T_978, _T_979) @[el2_pic_ctl.scala 47:55] - node _T_988 = or(_T_987, gw_int_pending_1) @[el2_pic_ctl.scala 47:78] - node _T_989 = xor(_T_978, _T_979) @[el2_pic_ctl.scala 47:117] - node extintsrc_req_gw_2 = mux(_T_986, _T_988, _T_989) @[el2_pic_ctl.scala 47:8] - node _T_990 = bits(extintsrc_req_sync, 3, 3) @[el2_pic_ctl.scala 170:43] - node _T_991 = bits(gw_config_reg[3], 0, 0) @[el2_pic_ctl.scala 170:64] - node _T_992 = bits(gw_config_reg[3], 1, 1) @[el2_pic_ctl.scala 170:85] - node _T_993 = bits(gw_clear_reg_we_3, 0, 0) @[el2_pic_ctl.scala 170:115] + node _T_982 = xor(_T_978, _T_979) @[el2_pic_ctl.scala 37:50] + node _T_983 = eq(_T_981, UInt<1>("h00")) @[el2_pic_ctl.scala 37:92] + node _T_984 = and(gw_int_pending_1, _T_983) @[el2_pic_ctl.scala 37:90] + node gw_int_pending_in_1 = or(_T_982, _T_984) @[el2_pic_ctl.scala 37:72] + reg _T_985 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 38:30] + _T_985 <= gw_int_pending_in_1 @[el2_pic_ctl.scala 38:30] + gw_int_pending_1 <= _T_985 @[el2_pic_ctl.scala 38:20] + node _T_986 = bits(_T_980, 0, 0) @[el2_pic_ctl.scala 39:30] + node _T_987 = xor(_T_978, _T_979) @[el2_pic_ctl.scala 39:55] + node _T_988 = or(_T_987, gw_int_pending_1) @[el2_pic_ctl.scala 39:78] + node _T_989 = xor(_T_978, _T_979) @[el2_pic_ctl.scala 39:117] + node extintsrc_req_gw_2 = mux(_T_986, _T_988, _T_989) @[el2_pic_ctl.scala 39:8] + node _T_990 = bits(extintsrc_req_sync, 3, 3) @[el2_pic_ctl.scala 162:43] + node _T_991 = bits(gw_config_reg[3], 0, 0) @[el2_pic_ctl.scala 162:64] + node _T_992 = bits(gw_config_reg[3], 1, 1) @[el2_pic_ctl.scala 162:85] + node _T_993 = bits(gw_clear_reg_we_3, 0, 0) @[el2_pic_ctl.scala 162:115] wire gw_int_pending_2 : UInt<1> gw_int_pending_2 <= UInt<1>("h00") - node _T_994 = xor(_T_990, _T_991) @[el2_pic_ctl.scala 45:50] - node _T_995 = eq(_T_993, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] - node _T_996 = and(gw_int_pending_2, _T_995) @[el2_pic_ctl.scala 45:90] - node gw_int_pending_in_2 = or(_T_994, _T_996) @[el2_pic_ctl.scala 45:72] - reg _T_997 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] - _T_997 <= gw_int_pending_in_2 @[el2_pic_ctl.scala 46:30] - gw_int_pending_2 <= _T_997 @[el2_pic_ctl.scala 46:20] - node _T_998 = bits(_T_992, 0, 0) @[el2_pic_ctl.scala 47:30] - node _T_999 = xor(_T_990, _T_991) @[el2_pic_ctl.scala 47:55] - node _T_1000 = or(_T_999, gw_int_pending_2) @[el2_pic_ctl.scala 47:78] - node _T_1001 = xor(_T_990, _T_991) @[el2_pic_ctl.scala 47:117] - node extintsrc_req_gw_3 = mux(_T_998, _T_1000, _T_1001) @[el2_pic_ctl.scala 47:8] - node _T_1002 = bits(extintsrc_req_sync, 4, 4) @[el2_pic_ctl.scala 170:43] - node _T_1003 = bits(gw_config_reg[4], 0, 0) @[el2_pic_ctl.scala 170:64] - node _T_1004 = bits(gw_config_reg[4], 1, 1) @[el2_pic_ctl.scala 170:85] - node _T_1005 = bits(gw_clear_reg_we_4, 0, 0) @[el2_pic_ctl.scala 170:115] + node _T_994 = xor(_T_990, _T_991) @[el2_pic_ctl.scala 37:50] + node _T_995 = eq(_T_993, UInt<1>("h00")) @[el2_pic_ctl.scala 37:92] + node _T_996 = and(gw_int_pending_2, _T_995) @[el2_pic_ctl.scala 37:90] + node gw_int_pending_in_2 = or(_T_994, _T_996) @[el2_pic_ctl.scala 37:72] + reg _T_997 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 38:30] + _T_997 <= gw_int_pending_in_2 @[el2_pic_ctl.scala 38:30] + gw_int_pending_2 <= _T_997 @[el2_pic_ctl.scala 38:20] + node _T_998 = bits(_T_992, 0, 0) @[el2_pic_ctl.scala 39:30] + node _T_999 = xor(_T_990, _T_991) @[el2_pic_ctl.scala 39:55] + node _T_1000 = or(_T_999, gw_int_pending_2) @[el2_pic_ctl.scala 39:78] + node _T_1001 = xor(_T_990, _T_991) @[el2_pic_ctl.scala 39:117] + node extintsrc_req_gw_3 = mux(_T_998, _T_1000, _T_1001) @[el2_pic_ctl.scala 39:8] + node _T_1002 = bits(extintsrc_req_sync, 4, 4) @[el2_pic_ctl.scala 162:43] + node _T_1003 = bits(gw_config_reg[4], 0, 0) @[el2_pic_ctl.scala 162:64] + node _T_1004 = bits(gw_config_reg[4], 1, 1) @[el2_pic_ctl.scala 162:85] + node _T_1005 = bits(gw_clear_reg_we_4, 0, 0) @[el2_pic_ctl.scala 162:115] wire gw_int_pending_3 : UInt<1> gw_int_pending_3 <= UInt<1>("h00") - node _T_1006 = xor(_T_1002, _T_1003) @[el2_pic_ctl.scala 45:50] - node _T_1007 = eq(_T_1005, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] - node _T_1008 = and(gw_int_pending_3, _T_1007) @[el2_pic_ctl.scala 45:90] - node gw_int_pending_in_3 = or(_T_1006, _T_1008) @[el2_pic_ctl.scala 45:72] - reg _T_1009 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] - _T_1009 <= gw_int_pending_in_3 @[el2_pic_ctl.scala 46:30] - gw_int_pending_3 <= _T_1009 @[el2_pic_ctl.scala 46:20] - node _T_1010 = bits(_T_1004, 0, 0) @[el2_pic_ctl.scala 47:30] - node _T_1011 = xor(_T_1002, _T_1003) @[el2_pic_ctl.scala 47:55] - node _T_1012 = or(_T_1011, gw_int_pending_3) @[el2_pic_ctl.scala 47:78] - node _T_1013 = xor(_T_1002, _T_1003) @[el2_pic_ctl.scala 47:117] - node extintsrc_req_gw_4 = mux(_T_1010, _T_1012, _T_1013) @[el2_pic_ctl.scala 47:8] - node _T_1014 = bits(extintsrc_req_sync, 5, 5) @[el2_pic_ctl.scala 170:43] - node _T_1015 = bits(gw_config_reg[5], 0, 0) @[el2_pic_ctl.scala 170:64] - node _T_1016 = bits(gw_config_reg[5], 1, 1) @[el2_pic_ctl.scala 170:85] - node _T_1017 = bits(gw_clear_reg_we_5, 0, 0) @[el2_pic_ctl.scala 170:115] + node _T_1006 = xor(_T_1002, _T_1003) @[el2_pic_ctl.scala 37:50] + node _T_1007 = eq(_T_1005, UInt<1>("h00")) @[el2_pic_ctl.scala 37:92] + node _T_1008 = and(gw_int_pending_3, _T_1007) @[el2_pic_ctl.scala 37:90] + node gw_int_pending_in_3 = or(_T_1006, _T_1008) @[el2_pic_ctl.scala 37:72] + reg _T_1009 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 38:30] + _T_1009 <= gw_int_pending_in_3 @[el2_pic_ctl.scala 38:30] + gw_int_pending_3 <= _T_1009 @[el2_pic_ctl.scala 38:20] + node _T_1010 = bits(_T_1004, 0, 0) @[el2_pic_ctl.scala 39:30] + node _T_1011 = xor(_T_1002, _T_1003) @[el2_pic_ctl.scala 39:55] + node _T_1012 = or(_T_1011, gw_int_pending_3) @[el2_pic_ctl.scala 39:78] + node _T_1013 = xor(_T_1002, _T_1003) @[el2_pic_ctl.scala 39:117] + node extintsrc_req_gw_4 = mux(_T_1010, _T_1012, _T_1013) @[el2_pic_ctl.scala 39:8] + node _T_1014 = bits(extintsrc_req_sync, 5, 5) @[el2_pic_ctl.scala 162:43] + node _T_1015 = bits(gw_config_reg[5], 0, 0) @[el2_pic_ctl.scala 162:64] + node _T_1016 = bits(gw_config_reg[5], 1, 1) @[el2_pic_ctl.scala 162:85] + node _T_1017 = bits(gw_clear_reg_we_5, 0, 0) @[el2_pic_ctl.scala 162:115] wire gw_int_pending_4 : UInt<1> gw_int_pending_4 <= UInt<1>("h00") - node _T_1018 = xor(_T_1014, _T_1015) @[el2_pic_ctl.scala 45:50] - node _T_1019 = eq(_T_1017, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] - node _T_1020 = and(gw_int_pending_4, _T_1019) @[el2_pic_ctl.scala 45:90] - node gw_int_pending_in_4 = or(_T_1018, _T_1020) @[el2_pic_ctl.scala 45:72] - reg _T_1021 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] - _T_1021 <= gw_int_pending_in_4 @[el2_pic_ctl.scala 46:30] - gw_int_pending_4 <= _T_1021 @[el2_pic_ctl.scala 46:20] - node _T_1022 = bits(_T_1016, 0, 0) @[el2_pic_ctl.scala 47:30] - node _T_1023 = xor(_T_1014, _T_1015) @[el2_pic_ctl.scala 47:55] - node _T_1024 = or(_T_1023, gw_int_pending_4) @[el2_pic_ctl.scala 47:78] - node _T_1025 = xor(_T_1014, _T_1015) @[el2_pic_ctl.scala 47:117] - node extintsrc_req_gw_5 = mux(_T_1022, _T_1024, _T_1025) @[el2_pic_ctl.scala 47:8] - node _T_1026 = bits(extintsrc_req_sync, 6, 6) @[el2_pic_ctl.scala 170:43] - node _T_1027 = bits(gw_config_reg[6], 0, 0) @[el2_pic_ctl.scala 170:64] - node _T_1028 = bits(gw_config_reg[6], 1, 1) @[el2_pic_ctl.scala 170:85] - node _T_1029 = bits(gw_clear_reg_we_6, 0, 0) @[el2_pic_ctl.scala 170:115] + node _T_1018 = xor(_T_1014, _T_1015) @[el2_pic_ctl.scala 37:50] + node _T_1019 = eq(_T_1017, UInt<1>("h00")) @[el2_pic_ctl.scala 37:92] + node _T_1020 = and(gw_int_pending_4, _T_1019) @[el2_pic_ctl.scala 37:90] + node gw_int_pending_in_4 = or(_T_1018, _T_1020) @[el2_pic_ctl.scala 37:72] + reg _T_1021 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 38:30] + _T_1021 <= gw_int_pending_in_4 @[el2_pic_ctl.scala 38:30] + gw_int_pending_4 <= _T_1021 @[el2_pic_ctl.scala 38:20] + node _T_1022 = bits(_T_1016, 0, 0) @[el2_pic_ctl.scala 39:30] + node _T_1023 = xor(_T_1014, _T_1015) @[el2_pic_ctl.scala 39:55] + node _T_1024 = or(_T_1023, gw_int_pending_4) @[el2_pic_ctl.scala 39:78] + node _T_1025 = xor(_T_1014, _T_1015) @[el2_pic_ctl.scala 39:117] + node extintsrc_req_gw_5 = mux(_T_1022, _T_1024, _T_1025) @[el2_pic_ctl.scala 39:8] + node _T_1026 = bits(extintsrc_req_sync, 6, 6) @[el2_pic_ctl.scala 162:43] + node _T_1027 = bits(gw_config_reg[6], 0, 0) @[el2_pic_ctl.scala 162:64] + node _T_1028 = bits(gw_config_reg[6], 1, 1) @[el2_pic_ctl.scala 162:85] + node _T_1029 = bits(gw_clear_reg_we_6, 0, 0) @[el2_pic_ctl.scala 162:115] wire gw_int_pending_5 : UInt<1> gw_int_pending_5 <= UInt<1>("h00") - node _T_1030 = xor(_T_1026, _T_1027) @[el2_pic_ctl.scala 45:50] - node _T_1031 = eq(_T_1029, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] - node _T_1032 = and(gw_int_pending_5, _T_1031) @[el2_pic_ctl.scala 45:90] - node gw_int_pending_in_5 = or(_T_1030, _T_1032) @[el2_pic_ctl.scala 45:72] - reg _T_1033 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] - _T_1033 <= gw_int_pending_in_5 @[el2_pic_ctl.scala 46:30] - gw_int_pending_5 <= _T_1033 @[el2_pic_ctl.scala 46:20] - node _T_1034 = bits(_T_1028, 0, 0) @[el2_pic_ctl.scala 47:30] - node _T_1035 = xor(_T_1026, _T_1027) @[el2_pic_ctl.scala 47:55] - node _T_1036 = or(_T_1035, gw_int_pending_5) @[el2_pic_ctl.scala 47:78] - node _T_1037 = xor(_T_1026, _T_1027) @[el2_pic_ctl.scala 47:117] - node extintsrc_req_gw_6 = mux(_T_1034, _T_1036, _T_1037) @[el2_pic_ctl.scala 47:8] - node _T_1038 = bits(extintsrc_req_sync, 7, 7) @[el2_pic_ctl.scala 170:43] - node _T_1039 = bits(gw_config_reg[7], 0, 0) @[el2_pic_ctl.scala 170:64] - node _T_1040 = bits(gw_config_reg[7], 1, 1) @[el2_pic_ctl.scala 170:85] - node _T_1041 = bits(gw_clear_reg_we_7, 0, 0) @[el2_pic_ctl.scala 170:115] + node _T_1030 = xor(_T_1026, _T_1027) @[el2_pic_ctl.scala 37:50] + node _T_1031 = eq(_T_1029, UInt<1>("h00")) @[el2_pic_ctl.scala 37:92] + node _T_1032 = and(gw_int_pending_5, _T_1031) @[el2_pic_ctl.scala 37:90] + node gw_int_pending_in_5 = or(_T_1030, _T_1032) @[el2_pic_ctl.scala 37:72] + reg _T_1033 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 38:30] + _T_1033 <= gw_int_pending_in_5 @[el2_pic_ctl.scala 38:30] + gw_int_pending_5 <= _T_1033 @[el2_pic_ctl.scala 38:20] + node _T_1034 = bits(_T_1028, 0, 0) @[el2_pic_ctl.scala 39:30] + node _T_1035 = xor(_T_1026, _T_1027) @[el2_pic_ctl.scala 39:55] + node _T_1036 = or(_T_1035, gw_int_pending_5) @[el2_pic_ctl.scala 39:78] + node _T_1037 = xor(_T_1026, _T_1027) @[el2_pic_ctl.scala 39:117] + node extintsrc_req_gw_6 = mux(_T_1034, _T_1036, _T_1037) @[el2_pic_ctl.scala 39:8] + node _T_1038 = bits(extintsrc_req_sync, 7, 7) @[el2_pic_ctl.scala 162:43] + node _T_1039 = bits(gw_config_reg[7], 0, 0) @[el2_pic_ctl.scala 162:64] + node _T_1040 = bits(gw_config_reg[7], 1, 1) @[el2_pic_ctl.scala 162:85] + node _T_1041 = bits(gw_clear_reg_we_7, 0, 0) @[el2_pic_ctl.scala 162:115] wire gw_int_pending_6 : UInt<1> gw_int_pending_6 <= UInt<1>("h00") - node _T_1042 = xor(_T_1038, _T_1039) @[el2_pic_ctl.scala 45:50] - node _T_1043 = eq(_T_1041, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] - node _T_1044 = and(gw_int_pending_6, _T_1043) @[el2_pic_ctl.scala 45:90] - node gw_int_pending_in_6 = or(_T_1042, _T_1044) @[el2_pic_ctl.scala 45:72] - reg _T_1045 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] - _T_1045 <= gw_int_pending_in_6 @[el2_pic_ctl.scala 46:30] - gw_int_pending_6 <= _T_1045 @[el2_pic_ctl.scala 46:20] - node _T_1046 = bits(_T_1040, 0, 0) @[el2_pic_ctl.scala 47:30] - node _T_1047 = xor(_T_1038, _T_1039) @[el2_pic_ctl.scala 47:55] - node _T_1048 = or(_T_1047, gw_int_pending_6) @[el2_pic_ctl.scala 47:78] - node _T_1049 = xor(_T_1038, _T_1039) @[el2_pic_ctl.scala 47:117] - node extintsrc_req_gw_7 = mux(_T_1046, _T_1048, _T_1049) @[el2_pic_ctl.scala 47:8] - node _T_1050 = bits(extintsrc_req_sync, 8, 8) @[el2_pic_ctl.scala 170:43] - node _T_1051 = bits(gw_config_reg[8], 0, 0) @[el2_pic_ctl.scala 170:64] - node _T_1052 = bits(gw_config_reg[8], 1, 1) @[el2_pic_ctl.scala 170:85] - node _T_1053 = bits(gw_clear_reg_we_8, 0, 0) @[el2_pic_ctl.scala 170:115] + node _T_1042 = xor(_T_1038, _T_1039) @[el2_pic_ctl.scala 37:50] + node _T_1043 = eq(_T_1041, UInt<1>("h00")) @[el2_pic_ctl.scala 37:92] + node _T_1044 = and(gw_int_pending_6, _T_1043) @[el2_pic_ctl.scala 37:90] + node gw_int_pending_in_6 = or(_T_1042, _T_1044) @[el2_pic_ctl.scala 37:72] + reg _T_1045 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 38:30] + _T_1045 <= gw_int_pending_in_6 @[el2_pic_ctl.scala 38:30] + gw_int_pending_6 <= _T_1045 @[el2_pic_ctl.scala 38:20] + node _T_1046 = bits(_T_1040, 0, 0) @[el2_pic_ctl.scala 39:30] + node _T_1047 = xor(_T_1038, _T_1039) @[el2_pic_ctl.scala 39:55] + node _T_1048 = or(_T_1047, gw_int_pending_6) @[el2_pic_ctl.scala 39:78] + node _T_1049 = xor(_T_1038, _T_1039) @[el2_pic_ctl.scala 39:117] + node extintsrc_req_gw_7 = mux(_T_1046, _T_1048, _T_1049) @[el2_pic_ctl.scala 39:8] + node _T_1050 = bits(extintsrc_req_sync, 8, 8) @[el2_pic_ctl.scala 162:43] + node _T_1051 = bits(gw_config_reg[8], 0, 0) @[el2_pic_ctl.scala 162:64] + node _T_1052 = bits(gw_config_reg[8], 1, 1) @[el2_pic_ctl.scala 162:85] + node _T_1053 = bits(gw_clear_reg_we_8, 0, 0) @[el2_pic_ctl.scala 162:115] wire gw_int_pending_7 : UInt<1> gw_int_pending_7 <= UInt<1>("h00") - node _T_1054 = xor(_T_1050, _T_1051) @[el2_pic_ctl.scala 45:50] - node _T_1055 = eq(_T_1053, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] - node _T_1056 = and(gw_int_pending_7, _T_1055) @[el2_pic_ctl.scala 45:90] - node gw_int_pending_in_7 = or(_T_1054, _T_1056) @[el2_pic_ctl.scala 45:72] - reg _T_1057 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] - _T_1057 <= gw_int_pending_in_7 @[el2_pic_ctl.scala 46:30] - gw_int_pending_7 <= _T_1057 @[el2_pic_ctl.scala 46:20] - node _T_1058 = bits(_T_1052, 0, 0) @[el2_pic_ctl.scala 47:30] - node _T_1059 = xor(_T_1050, _T_1051) @[el2_pic_ctl.scala 47:55] - node _T_1060 = or(_T_1059, gw_int_pending_7) @[el2_pic_ctl.scala 47:78] - node _T_1061 = xor(_T_1050, _T_1051) @[el2_pic_ctl.scala 47:117] - node extintsrc_req_gw_8 = mux(_T_1058, _T_1060, _T_1061) @[el2_pic_ctl.scala 47:8] - node _T_1062 = bits(extintsrc_req_sync, 9, 9) @[el2_pic_ctl.scala 170:43] - node _T_1063 = bits(gw_config_reg[9], 0, 0) @[el2_pic_ctl.scala 170:64] - node _T_1064 = bits(gw_config_reg[9], 1, 1) @[el2_pic_ctl.scala 170:85] - node _T_1065 = bits(gw_clear_reg_we_9, 0, 0) @[el2_pic_ctl.scala 170:115] + node _T_1054 = xor(_T_1050, _T_1051) @[el2_pic_ctl.scala 37:50] + node _T_1055 = eq(_T_1053, UInt<1>("h00")) @[el2_pic_ctl.scala 37:92] + node _T_1056 = and(gw_int_pending_7, _T_1055) @[el2_pic_ctl.scala 37:90] + node gw_int_pending_in_7 = or(_T_1054, _T_1056) @[el2_pic_ctl.scala 37:72] + reg _T_1057 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 38:30] + _T_1057 <= gw_int_pending_in_7 @[el2_pic_ctl.scala 38:30] + gw_int_pending_7 <= _T_1057 @[el2_pic_ctl.scala 38:20] + node _T_1058 = bits(_T_1052, 0, 0) @[el2_pic_ctl.scala 39:30] + node _T_1059 = xor(_T_1050, _T_1051) @[el2_pic_ctl.scala 39:55] + node _T_1060 = or(_T_1059, gw_int_pending_7) @[el2_pic_ctl.scala 39:78] + node _T_1061 = xor(_T_1050, _T_1051) @[el2_pic_ctl.scala 39:117] + node extintsrc_req_gw_8 = mux(_T_1058, _T_1060, _T_1061) @[el2_pic_ctl.scala 39:8] + node _T_1062 = bits(extintsrc_req_sync, 9, 9) @[el2_pic_ctl.scala 162:43] + node _T_1063 = bits(gw_config_reg[9], 0, 0) @[el2_pic_ctl.scala 162:64] + node _T_1064 = bits(gw_config_reg[9], 1, 1) @[el2_pic_ctl.scala 162:85] + node _T_1065 = bits(gw_clear_reg_we_9, 0, 0) @[el2_pic_ctl.scala 162:115] wire gw_int_pending_8 : UInt<1> gw_int_pending_8 <= UInt<1>("h00") - node _T_1066 = xor(_T_1062, _T_1063) @[el2_pic_ctl.scala 45:50] - node _T_1067 = eq(_T_1065, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] - node _T_1068 = and(gw_int_pending_8, _T_1067) @[el2_pic_ctl.scala 45:90] - node gw_int_pending_in_8 = or(_T_1066, _T_1068) @[el2_pic_ctl.scala 45:72] - reg _T_1069 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] - _T_1069 <= gw_int_pending_in_8 @[el2_pic_ctl.scala 46:30] - gw_int_pending_8 <= _T_1069 @[el2_pic_ctl.scala 46:20] - node _T_1070 = bits(_T_1064, 0, 0) @[el2_pic_ctl.scala 47:30] - node _T_1071 = xor(_T_1062, _T_1063) @[el2_pic_ctl.scala 47:55] - node _T_1072 = or(_T_1071, gw_int_pending_8) @[el2_pic_ctl.scala 47:78] - node _T_1073 = xor(_T_1062, _T_1063) @[el2_pic_ctl.scala 47:117] - node extintsrc_req_gw_9 = mux(_T_1070, _T_1072, _T_1073) @[el2_pic_ctl.scala 47:8] - node _T_1074 = bits(extintsrc_req_sync, 10, 10) @[el2_pic_ctl.scala 170:43] - node _T_1075 = bits(gw_config_reg[10], 0, 0) @[el2_pic_ctl.scala 170:64] - node _T_1076 = bits(gw_config_reg[10], 1, 1) @[el2_pic_ctl.scala 170:85] - node _T_1077 = bits(gw_clear_reg_we_10, 0, 0) @[el2_pic_ctl.scala 170:115] + node _T_1066 = xor(_T_1062, _T_1063) @[el2_pic_ctl.scala 37:50] + node _T_1067 = eq(_T_1065, UInt<1>("h00")) @[el2_pic_ctl.scala 37:92] + node _T_1068 = and(gw_int_pending_8, _T_1067) @[el2_pic_ctl.scala 37:90] + node gw_int_pending_in_8 = or(_T_1066, _T_1068) @[el2_pic_ctl.scala 37:72] + reg _T_1069 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 38:30] + _T_1069 <= gw_int_pending_in_8 @[el2_pic_ctl.scala 38:30] + gw_int_pending_8 <= _T_1069 @[el2_pic_ctl.scala 38:20] + node _T_1070 = bits(_T_1064, 0, 0) @[el2_pic_ctl.scala 39:30] + node _T_1071 = xor(_T_1062, _T_1063) @[el2_pic_ctl.scala 39:55] + node _T_1072 = or(_T_1071, gw_int_pending_8) @[el2_pic_ctl.scala 39:78] + node _T_1073 = xor(_T_1062, _T_1063) @[el2_pic_ctl.scala 39:117] + node extintsrc_req_gw_9 = mux(_T_1070, _T_1072, _T_1073) @[el2_pic_ctl.scala 39:8] + node _T_1074 = bits(extintsrc_req_sync, 10, 10) @[el2_pic_ctl.scala 162:43] + node _T_1075 = bits(gw_config_reg[10], 0, 0) @[el2_pic_ctl.scala 162:64] + node _T_1076 = bits(gw_config_reg[10], 1, 1) @[el2_pic_ctl.scala 162:85] + node _T_1077 = bits(gw_clear_reg_we_10, 0, 0) @[el2_pic_ctl.scala 162:115] wire gw_int_pending_9 : UInt<1> gw_int_pending_9 <= UInt<1>("h00") - node _T_1078 = xor(_T_1074, _T_1075) @[el2_pic_ctl.scala 45:50] - node _T_1079 = eq(_T_1077, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] - node _T_1080 = and(gw_int_pending_9, _T_1079) @[el2_pic_ctl.scala 45:90] - node gw_int_pending_in_9 = or(_T_1078, _T_1080) @[el2_pic_ctl.scala 45:72] - reg _T_1081 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] - _T_1081 <= gw_int_pending_in_9 @[el2_pic_ctl.scala 46:30] - gw_int_pending_9 <= _T_1081 @[el2_pic_ctl.scala 46:20] - node _T_1082 = bits(_T_1076, 0, 0) @[el2_pic_ctl.scala 47:30] - node _T_1083 = xor(_T_1074, _T_1075) @[el2_pic_ctl.scala 47:55] - node _T_1084 = or(_T_1083, gw_int_pending_9) @[el2_pic_ctl.scala 47:78] - node _T_1085 = xor(_T_1074, _T_1075) @[el2_pic_ctl.scala 47:117] - node extintsrc_req_gw_10 = mux(_T_1082, _T_1084, _T_1085) @[el2_pic_ctl.scala 47:8] - node _T_1086 = bits(extintsrc_req_sync, 11, 11) @[el2_pic_ctl.scala 170:43] - node _T_1087 = bits(gw_config_reg[11], 0, 0) @[el2_pic_ctl.scala 170:64] - node _T_1088 = bits(gw_config_reg[11], 1, 1) @[el2_pic_ctl.scala 170:85] - node _T_1089 = bits(gw_clear_reg_we_11, 0, 0) @[el2_pic_ctl.scala 170:115] + node _T_1078 = xor(_T_1074, _T_1075) @[el2_pic_ctl.scala 37:50] + node _T_1079 = eq(_T_1077, UInt<1>("h00")) @[el2_pic_ctl.scala 37:92] + node _T_1080 = and(gw_int_pending_9, _T_1079) @[el2_pic_ctl.scala 37:90] + node gw_int_pending_in_9 = or(_T_1078, _T_1080) @[el2_pic_ctl.scala 37:72] + reg _T_1081 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 38:30] + _T_1081 <= gw_int_pending_in_9 @[el2_pic_ctl.scala 38:30] + gw_int_pending_9 <= _T_1081 @[el2_pic_ctl.scala 38:20] + node _T_1082 = bits(_T_1076, 0, 0) @[el2_pic_ctl.scala 39:30] + node _T_1083 = xor(_T_1074, _T_1075) @[el2_pic_ctl.scala 39:55] + node _T_1084 = or(_T_1083, gw_int_pending_9) @[el2_pic_ctl.scala 39:78] + node _T_1085 = xor(_T_1074, _T_1075) @[el2_pic_ctl.scala 39:117] + node extintsrc_req_gw_10 = mux(_T_1082, _T_1084, _T_1085) @[el2_pic_ctl.scala 39:8] + node _T_1086 = bits(extintsrc_req_sync, 11, 11) @[el2_pic_ctl.scala 162:43] + node _T_1087 = bits(gw_config_reg[11], 0, 0) @[el2_pic_ctl.scala 162:64] + node _T_1088 = bits(gw_config_reg[11], 1, 1) @[el2_pic_ctl.scala 162:85] + node _T_1089 = bits(gw_clear_reg_we_11, 0, 0) @[el2_pic_ctl.scala 162:115] wire gw_int_pending_10 : UInt<1> gw_int_pending_10 <= UInt<1>("h00") - node _T_1090 = xor(_T_1086, _T_1087) @[el2_pic_ctl.scala 45:50] - node _T_1091 = eq(_T_1089, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] - node _T_1092 = and(gw_int_pending_10, _T_1091) @[el2_pic_ctl.scala 45:90] - node gw_int_pending_in_10 = or(_T_1090, _T_1092) @[el2_pic_ctl.scala 45:72] - reg _T_1093 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] - _T_1093 <= gw_int_pending_in_10 @[el2_pic_ctl.scala 46:30] - gw_int_pending_10 <= _T_1093 @[el2_pic_ctl.scala 46:20] - node _T_1094 = bits(_T_1088, 0, 0) @[el2_pic_ctl.scala 47:30] - node _T_1095 = xor(_T_1086, _T_1087) @[el2_pic_ctl.scala 47:55] - node _T_1096 = or(_T_1095, gw_int_pending_10) @[el2_pic_ctl.scala 47:78] - node _T_1097 = xor(_T_1086, _T_1087) @[el2_pic_ctl.scala 47:117] - node extintsrc_req_gw_11 = mux(_T_1094, _T_1096, _T_1097) @[el2_pic_ctl.scala 47:8] - node _T_1098 = bits(extintsrc_req_sync, 12, 12) @[el2_pic_ctl.scala 170:43] - node _T_1099 = bits(gw_config_reg[12], 0, 0) @[el2_pic_ctl.scala 170:64] - node _T_1100 = bits(gw_config_reg[12], 1, 1) @[el2_pic_ctl.scala 170:85] - node _T_1101 = bits(gw_clear_reg_we_12, 0, 0) @[el2_pic_ctl.scala 170:115] + node _T_1090 = xor(_T_1086, _T_1087) @[el2_pic_ctl.scala 37:50] + node _T_1091 = eq(_T_1089, UInt<1>("h00")) @[el2_pic_ctl.scala 37:92] + node _T_1092 = and(gw_int_pending_10, _T_1091) @[el2_pic_ctl.scala 37:90] + node gw_int_pending_in_10 = or(_T_1090, _T_1092) @[el2_pic_ctl.scala 37:72] + reg _T_1093 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 38:30] + _T_1093 <= gw_int_pending_in_10 @[el2_pic_ctl.scala 38:30] + gw_int_pending_10 <= _T_1093 @[el2_pic_ctl.scala 38:20] + node _T_1094 = bits(_T_1088, 0, 0) @[el2_pic_ctl.scala 39:30] + node _T_1095 = xor(_T_1086, _T_1087) @[el2_pic_ctl.scala 39:55] + node _T_1096 = or(_T_1095, gw_int_pending_10) @[el2_pic_ctl.scala 39:78] + node _T_1097 = xor(_T_1086, _T_1087) @[el2_pic_ctl.scala 39:117] + node extintsrc_req_gw_11 = mux(_T_1094, _T_1096, _T_1097) @[el2_pic_ctl.scala 39:8] + node _T_1098 = bits(extintsrc_req_sync, 12, 12) @[el2_pic_ctl.scala 162:43] + node _T_1099 = bits(gw_config_reg[12], 0, 0) @[el2_pic_ctl.scala 162:64] + node _T_1100 = bits(gw_config_reg[12], 1, 1) @[el2_pic_ctl.scala 162:85] + node _T_1101 = bits(gw_clear_reg_we_12, 0, 0) @[el2_pic_ctl.scala 162:115] wire gw_int_pending_11 : UInt<1> gw_int_pending_11 <= UInt<1>("h00") - node _T_1102 = xor(_T_1098, _T_1099) @[el2_pic_ctl.scala 45:50] - node _T_1103 = eq(_T_1101, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] - node _T_1104 = and(gw_int_pending_11, _T_1103) @[el2_pic_ctl.scala 45:90] - node gw_int_pending_in_11 = or(_T_1102, _T_1104) @[el2_pic_ctl.scala 45:72] - reg _T_1105 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] - _T_1105 <= gw_int_pending_in_11 @[el2_pic_ctl.scala 46:30] - gw_int_pending_11 <= _T_1105 @[el2_pic_ctl.scala 46:20] - node _T_1106 = bits(_T_1100, 0, 0) @[el2_pic_ctl.scala 47:30] - node _T_1107 = xor(_T_1098, _T_1099) @[el2_pic_ctl.scala 47:55] - node _T_1108 = or(_T_1107, gw_int_pending_11) @[el2_pic_ctl.scala 47:78] - node _T_1109 = xor(_T_1098, _T_1099) @[el2_pic_ctl.scala 47:117] - node extintsrc_req_gw_12 = mux(_T_1106, _T_1108, _T_1109) @[el2_pic_ctl.scala 47:8] - node _T_1110 = bits(extintsrc_req_sync, 13, 13) @[el2_pic_ctl.scala 170:43] - node _T_1111 = bits(gw_config_reg[13], 0, 0) @[el2_pic_ctl.scala 170:64] - node _T_1112 = bits(gw_config_reg[13], 1, 1) @[el2_pic_ctl.scala 170:85] - node _T_1113 = bits(gw_clear_reg_we_13, 0, 0) @[el2_pic_ctl.scala 170:115] + node _T_1102 = xor(_T_1098, _T_1099) @[el2_pic_ctl.scala 37:50] + node _T_1103 = eq(_T_1101, UInt<1>("h00")) @[el2_pic_ctl.scala 37:92] + node _T_1104 = and(gw_int_pending_11, _T_1103) @[el2_pic_ctl.scala 37:90] + node gw_int_pending_in_11 = or(_T_1102, _T_1104) @[el2_pic_ctl.scala 37:72] + reg _T_1105 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 38:30] + _T_1105 <= gw_int_pending_in_11 @[el2_pic_ctl.scala 38:30] + gw_int_pending_11 <= _T_1105 @[el2_pic_ctl.scala 38:20] + node _T_1106 = bits(_T_1100, 0, 0) @[el2_pic_ctl.scala 39:30] + node _T_1107 = xor(_T_1098, _T_1099) @[el2_pic_ctl.scala 39:55] + node _T_1108 = or(_T_1107, gw_int_pending_11) @[el2_pic_ctl.scala 39:78] + node _T_1109 = xor(_T_1098, _T_1099) @[el2_pic_ctl.scala 39:117] + node extintsrc_req_gw_12 = mux(_T_1106, _T_1108, _T_1109) @[el2_pic_ctl.scala 39:8] + node _T_1110 = bits(extintsrc_req_sync, 13, 13) @[el2_pic_ctl.scala 162:43] + node _T_1111 = bits(gw_config_reg[13], 0, 0) @[el2_pic_ctl.scala 162:64] + node _T_1112 = bits(gw_config_reg[13], 1, 1) @[el2_pic_ctl.scala 162:85] + node _T_1113 = bits(gw_clear_reg_we_13, 0, 0) @[el2_pic_ctl.scala 162:115] wire gw_int_pending_12 : UInt<1> gw_int_pending_12 <= UInt<1>("h00") - node _T_1114 = xor(_T_1110, _T_1111) @[el2_pic_ctl.scala 45:50] - node _T_1115 = eq(_T_1113, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] - node _T_1116 = and(gw_int_pending_12, _T_1115) @[el2_pic_ctl.scala 45:90] - node gw_int_pending_in_12 = or(_T_1114, _T_1116) @[el2_pic_ctl.scala 45:72] - reg _T_1117 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] - _T_1117 <= gw_int_pending_in_12 @[el2_pic_ctl.scala 46:30] - gw_int_pending_12 <= _T_1117 @[el2_pic_ctl.scala 46:20] - node _T_1118 = bits(_T_1112, 0, 0) @[el2_pic_ctl.scala 47:30] - node _T_1119 = xor(_T_1110, _T_1111) @[el2_pic_ctl.scala 47:55] - node _T_1120 = or(_T_1119, gw_int_pending_12) @[el2_pic_ctl.scala 47:78] - node _T_1121 = xor(_T_1110, _T_1111) @[el2_pic_ctl.scala 47:117] - node extintsrc_req_gw_13 = mux(_T_1118, _T_1120, _T_1121) @[el2_pic_ctl.scala 47:8] - node _T_1122 = bits(extintsrc_req_sync, 14, 14) @[el2_pic_ctl.scala 170:43] - node _T_1123 = bits(gw_config_reg[14], 0, 0) @[el2_pic_ctl.scala 170:64] - node _T_1124 = bits(gw_config_reg[14], 1, 1) @[el2_pic_ctl.scala 170:85] - node _T_1125 = bits(gw_clear_reg_we_14, 0, 0) @[el2_pic_ctl.scala 170:115] + node _T_1114 = xor(_T_1110, _T_1111) @[el2_pic_ctl.scala 37:50] + node _T_1115 = eq(_T_1113, UInt<1>("h00")) @[el2_pic_ctl.scala 37:92] + node _T_1116 = and(gw_int_pending_12, _T_1115) @[el2_pic_ctl.scala 37:90] + node gw_int_pending_in_12 = or(_T_1114, _T_1116) @[el2_pic_ctl.scala 37:72] + reg _T_1117 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 38:30] + _T_1117 <= gw_int_pending_in_12 @[el2_pic_ctl.scala 38:30] + gw_int_pending_12 <= _T_1117 @[el2_pic_ctl.scala 38:20] + node _T_1118 = bits(_T_1112, 0, 0) @[el2_pic_ctl.scala 39:30] + node _T_1119 = xor(_T_1110, _T_1111) @[el2_pic_ctl.scala 39:55] + node _T_1120 = or(_T_1119, gw_int_pending_12) @[el2_pic_ctl.scala 39:78] + node _T_1121 = xor(_T_1110, _T_1111) @[el2_pic_ctl.scala 39:117] + node extintsrc_req_gw_13 = mux(_T_1118, _T_1120, _T_1121) @[el2_pic_ctl.scala 39:8] + node _T_1122 = bits(extintsrc_req_sync, 14, 14) @[el2_pic_ctl.scala 162:43] + node _T_1123 = bits(gw_config_reg[14], 0, 0) @[el2_pic_ctl.scala 162:64] + node _T_1124 = bits(gw_config_reg[14], 1, 1) @[el2_pic_ctl.scala 162:85] + node _T_1125 = bits(gw_clear_reg_we_14, 0, 0) @[el2_pic_ctl.scala 162:115] wire gw_int_pending_13 : UInt<1> gw_int_pending_13 <= UInt<1>("h00") - node _T_1126 = xor(_T_1122, _T_1123) @[el2_pic_ctl.scala 45:50] - node _T_1127 = eq(_T_1125, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] - node _T_1128 = and(gw_int_pending_13, _T_1127) @[el2_pic_ctl.scala 45:90] - node gw_int_pending_in_13 = or(_T_1126, _T_1128) @[el2_pic_ctl.scala 45:72] - reg _T_1129 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] - _T_1129 <= gw_int_pending_in_13 @[el2_pic_ctl.scala 46:30] - gw_int_pending_13 <= _T_1129 @[el2_pic_ctl.scala 46:20] - node _T_1130 = bits(_T_1124, 0, 0) @[el2_pic_ctl.scala 47:30] - node _T_1131 = xor(_T_1122, _T_1123) @[el2_pic_ctl.scala 47:55] - node _T_1132 = or(_T_1131, gw_int_pending_13) @[el2_pic_ctl.scala 47:78] - node _T_1133 = xor(_T_1122, _T_1123) @[el2_pic_ctl.scala 47:117] - node extintsrc_req_gw_14 = mux(_T_1130, _T_1132, _T_1133) @[el2_pic_ctl.scala 47:8] - node _T_1134 = bits(extintsrc_req_sync, 15, 15) @[el2_pic_ctl.scala 170:43] - node _T_1135 = bits(gw_config_reg[15], 0, 0) @[el2_pic_ctl.scala 170:64] - node _T_1136 = bits(gw_config_reg[15], 1, 1) @[el2_pic_ctl.scala 170:85] - node _T_1137 = bits(gw_clear_reg_we_15, 0, 0) @[el2_pic_ctl.scala 170:115] + node _T_1126 = xor(_T_1122, _T_1123) @[el2_pic_ctl.scala 37:50] + node _T_1127 = eq(_T_1125, UInt<1>("h00")) @[el2_pic_ctl.scala 37:92] + node _T_1128 = and(gw_int_pending_13, _T_1127) @[el2_pic_ctl.scala 37:90] + node gw_int_pending_in_13 = or(_T_1126, _T_1128) @[el2_pic_ctl.scala 37:72] + reg _T_1129 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 38:30] + _T_1129 <= gw_int_pending_in_13 @[el2_pic_ctl.scala 38:30] + gw_int_pending_13 <= _T_1129 @[el2_pic_ctl.scala 38:20] + node _T_1130 = bits(_T_1124, 0, 0) @[el2_pic_ctl.scala 39:30] + node _T_1131 = xor(_T_1122, _T_1123) @[el2_pic_ctl.scala 39:55] + node _T_1132 = or(_T_1131, gw_int_pending_13) @[el2_pic_ctl.scala 39:78] + node _T_1133 = xor(_T_1122, _T_1123) @[el2_pic_ctl.scala 39:117] + node extintsrc_req_gw_14 = mux(_T_1130, _T_1132, _T_1133) @[el2_pic_ctl.scala 39:8] + node _T_1134 = bits(extintsrc_req_sync, 15, 15) @[el2_pic_ctl.scala 162:43] + node _T_1135 = bits(gw_config_reg[15], 0, 0) @[el2_pic_ctl.scala 162:64] + node _T_1136 = bits(gw_config_reg[15], 1, 1) @[el2_pic_ctl.scala 162:85] + node _T_1137 = bits(gw_clear_reg_we_15, 0, 0) @[el2_pic_ctl.scala 162:115] wire gw_int_pending_14 : UInt<1> gw_int_pending_14 <= UInt<1>("h00") - node _T_1138 = xor(_T_1134, _T_1135) @[el2_pic_ctl.scala 45:50] - node _T_1139 = eq(_T_1137, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] - node _T_1140 = and(gw_int_pending_14, _T_1139) @[el2_pic_ctl.scala 45:90] - node gw_int_pending_in_14 = or(_T_1138, _T_1140) @[el2_pic_ctl.scala 45:72] - reg _T_1141 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] - _T_1141 <= gw_int_pending_in_14 @[el2_pic_ctl.scala 46:30] - gw_int_pending_14 <= _T_1141 @[el2_pic_ctl.scala 46:20] - node _T_1142 = bits(_T_1136, 0, 0) @[el2_pic_ctl.scala 47:30] - node _T_1143 = xor(_T_1134, _T_1135) @[el2_pic_ctl.scala 47:55] - node _T_1144 = or(_T_1143, gw_int_pending_14) @[el2_pic_ctl.scala 47:78] - node _T_1145 = xor(_T_1134, _T_1135) @[el2_pic_ctl.scala 47:117] - node extintsrc_req_gw_15 = mux(_T_1142, _T_1144, _T_1145) @[el2_pic_ctl.scala 47:8] - node _T_1146 = bits(extintsrc_req_sync, 16, 16) @[el2_pic_ctl.scala 170:43] - node _T_1147 = bits(gw_config_reg[16], 0, 0) @[el2_pic_ctl.scala 170:64] - node _T_1148 = bits(gw_config_reg[16], 1, 1) @[el2_pic_ctl.scala 170:85] - node _T_1149 = bits(gw_clear_reg_we_16, 0, 0) @[el2_pic_ctl.scala 170:115] + node _T_1138 = xor(_T_1134, _T_1135) @[el2_pic_ctl.scala 37:50] + node _T_1139 = eq(_T_1137, UInt<1>("h00")) @[el2_pic_ctl.scala 37:92] + node _T_1140 = and(gw_int_pending_14, _T_1139) @[el2_pic_ctl.scala 37:90] + node gw_int_pending_in_14 = or(_T_1138, _T_1140) @[el2_pic_ctl.scala 37:72] + reg _T_1141 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 38:30] + _T_1141 <= gw_int_pending_in_14 @[el2_pic_ctl.scala 38:30] + gw_int_pending_14 <= _T_1141 @[el2_pic_ctl.scala 38:20] + node _T_1142 = bits(_T_1136, 0, 0) @[el2_pic_ctl.scala 39:30] + node _T_1143 = xor(_T_1134, _T_1135) @[el2_pic_ctl.scala 39:55] + node _T_1144 = or(_T_1143, gw_int_pending_14) @[el2_pic_ctl.scala 39:78] + node _T_1145 = xor(_T_1134, _T_1135) @[el2_pic_ctl.scala 39:117] + node extintsrc_req_gw_15 = mux(_T_1142, _T_1144, _T_1145) @[el2_pic_ctl.scala 39:8] + node _T_1146 = bits(extintsrc_req_sync, 16, 16) @[el2_pic_ctl.scala 162:43] + node _T_1147 = bits(gw_config_reg[16], 0, 0) @[el2_pic_ctl.scala 162:64] + node _T_1148 = bits(gw_config_reg[16], 1, 1) @[el2_pic_ctl.scala 162:85] + node _T_1149 = bits(gw_clear_reg_we_16, 0, 0) @[el2_pic_ctl.scala 162:115] wire gw_int_pending_15 : UInt<1> gw_int_pending_15 <= UInt<1>("h00") - node _T_1150 = xor(_T_1146, _T_1147) @[el2_pic_ctl.scala 45:50] - node _T_1151 = eq(_T_1149, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] - node _T_1152 = and(gw_int_pending_15, _T_1151) @[el2_pic_ctl.scala 45:90] - node gw_int_pending_in_15 = or(_T_1150, _T_1152) @[el2_pic_ctl.scala 45:72] - reg _T_1153 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] - _T_1153 <= gw_int_pending_in_15 @[el2_pic_ctl.scala 46:30] - gw_int_pending_15 <= _T_1153 @[el2_pic_ctl.scala 46:20] - node _T_1154 = bits(_T_1148, 0, 0) @[el2_pic_ctl.scala 47:30] - node _T_1155 = xor(_T_1146, _T_1147) @[el2_pic_ctl.scala 47:55] - node _T_1156 = or(_T_1155, gw_int_pending_15) @[el2_pic_ctl.scala 47:78] - node _T_1157 = xor(_T_1146, _T_1147) @[el2_pic_ctl.scala 47:117] - node extintsrc_req_gw_16 = mux(_T_1154, _T_1156, _T_1157) @[el2_pic_ctl.scala 47:8] - node _T_1158 = bits(extintsrc_req_sync, 17, 17) @[el2_pic_ctl.scala 170:43] - node _T_1159 = bits(gw_config_reg[17], 0, 0) @[el2_pic_ctl.scala 170:64] - node _T_1160 = bits(gw_config_reg[17], 1, 1) @[el2_pic_ctl.scala 170:85] - node _T_1161 = bits(gw_clear_reg_we_17, 0, 0) @[el2_pic_ctl.scala 170:115] + node _T_1150 = xor(_T_1146, _T_1147) @[el2_pic_ctl.scala 37:50] + node _T_1151 = eq(_T_1149, UInt<1>("h00")) @[el2_pic_ctl.scala 37:92] + node _T_1152 = and(gw_int_pending_15, _T_1151) @[el2_pic_ctl.scala 37:90] + node gw_int_pending_in_15 = or(_T_1150, _T_1152) @[el2_pic_ctl.scala 37:72] + reg _T_1153 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 38:30] + _T_1153 <= gw_int_pending_in_15 @[el2_pic_ctl.scala 38:30] + gw_int_pending_15 <= _T_1153 @[el2_pic_ctl.scala 38:20] + node _T_1154 = bits(_T_1148, 0, 0) @[el2_pic_ctl.scala 39:30] + node _T_1155 = xor(_T_1146, _T_1147) @[el2_pic_ctl.scala 39:55] + node _T_1156 = or(_T_1155, gw_int_pending_15) @[el2_pic_ctl.scala 39:78] + node _T_1157 = xor(_T_1146, _T_1147) @[el2_pic_ctl.scala 39:117] + node extintsrc_req_gw_16 = mux(_T_1154, _T_1156, _T_1157) @[el2_pic_ctl.scala 39:8] + node _T_1158 = bits(extintsrc_req_sync, 17, 17) @[el2_pic_ctl.scala 162:43] + node _T_1159 = bits(gw_config_reg[17], 0, 0) @[el2_pic_ctl.scala 162:64] + node _T_1160 = bits(gw_config_reg[17], 1, 1) @[el2_pic_ctl.scala 162:85] + node _T_1161 = bits(gw_clear_reg_we_17, 0, 0) @[el2_pic_ctl.scala 162:115] wire gw_int_pending_16 : UInt<1> gw_int_pending_16 <= UInt<1>("h00") - node _T_1162 = xor(_T_1158, _T_1159) @[el2_pic_ctl.scala 45:50] - node _T_1163 = eq(_T_1161, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] - node _T_1164 = and(gw_int_pending_16, _T_1163) @[el2_pic_ctl.scala 45:90] - node gw_int_pending_in_16 = or(_T_1162, _T_1164) @[el2_pic_ctl.scala 45:72] - reg _T_1165 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] - _T_1165 <= gw_int_pending_in_16 @[el2_pic_ctl.scala 46:30] - gw_int_pending_16 <= _T_1165 @[el2_pic_ctl.scala 46:20] - node _T_1166 = bits(_T_1160, 0, 0) @[el2_pic_ctl.scala 47:30] - node _T_1167 = xor(_T_1158, _T_1159) @[el2_pic_ctl.scala 47:55] - node _T_1168 = or(_T_1167, gw_int_pending_16) @[el2_pic_ctl.scala 47:78] - node _T_1169 = xor(_T_1158, _T_1159) @[el2_pic_ctl.scala 47:117] - node extintsrc_req_gw_17 = mux(_T_1166, _T_1168, _T_1169) @[el2_pic_ctl.scala 47:8] - node _T_1170 = bits(extintsrc_req_sync, 18, 18) @[el2_pic_ctl.scala 170:43] - node _T_1171 = bits(gw_config_reg[18], 0, 0) @[el2_pic_ctl.scala 170:64] - node _T_1172 = bits(gw_config_reg[18], 1, 1) @[el2_pic_ctl.scala 170:85] - node _T_1173 = bits(gw_clear_reg_we_18, 0, 0) @[el2_pic_ctl.scala 170:115] + node _T_1162 = xor(_T_1158, _T_1159) @[el2_pic_ctl.scala 37:50] + node _T_1163 = eq(_T_1161, UInt<1>("h00")) @[el2_pic_ctl.scala 37:92] + node _T_1164 = and(gw_int_pending_16, _T_1163) @[el2_pic_ctl.scala 37:90] + node gw_int_pending_in_16 = or(_T_1162, _T_1164) @[el2_pic_ctl.scala 37:72] + reg _T_1165 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 38:30] + _T_1165 <= gw_int_pending_in_16 @[el2_pic_ctl.scala 38:30] + gw_int_pending_16 <= _T_1165 @[el2_pic_ctl.scala 38:20] + node _T_1166 = bits(_T_1160, 0, 0) @[el2_pic_ctl.scala 39:30] + node _T_1167 = xor(_T_1158, _T_1159) @[el2_pic_ctl.scala 39:55] + node _T_1168 = or(_T_1167, gw_int_pending_16) @[el2_pic_ctl.scala 39:78] + node _T_1169 = xor(_T_1158, _T_1159) @[el2_pic_ctl.scala 39:117] + node extintsrc_req_gw_17 = mux(_T_1166, _T_1168, _T_1169) @[el2_pic_ctl.scala 39:8] + node _T_1170 = bits(extintsrc_req_sync, 18, 18) @[el2_pic_ctl.scala 162:43] + node _T_1171 = bits(gw_config_reg[18], 0, 0) @[el2_pic_ctl.scala 162:64] + node _T_1172 = bits(gw_config_reg[18], 1, 1) @[el2_pic_ctl.scala 162:85] + node _T_1173 = bits(gw_clear_reg_we_18, 0, 0) @[el2_pic_ctl.scala 162:115] wire gw_int_pending_17 : UInt<1> gw_int_pending_17 <= UInt<1>("h00") - node _T_1174 = xor(_T_1170, _T_1171) @[el2_pic_ctl.scala 45:50] - node _T_1175 = eq(_T_1173, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] - node _T_1176 = and(gw_int_pending_17, _T_1175) @[el2_pic_ctl.scala 45:90] - node gw_int_pending_in_17 = or(_T_1174, _T_1176) @[el2_pic_ctl.scala 45:72] - reg _T_1177 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] - _T_1177 <= gw_int_pending_in_17 @[el2_pic_ctl.scala 46:30] - gw_int_pending_17 <= _T_1177 @[el2_pic_ctl.scala 46:20] - node _T_1178 = bits(_T_1172, 0, 0) @[el2_pic_ctl.scala 47:30] - node _T_1179 = xor(_T_1170, _T_1171) @[el2_pic_ctl.scala 47:55] - node _T_1180 = or(_T_1179, gw_int_pending_17) @[el2_pic_ctl.scala 47:78] - node _T_1181 = xor(_T_1170, _T_1171) @[el2_pic_ctl.scala 47:117] - node extintsrc_req_gw_18 = mux(_T_1178, _T_1180, _T_1181) @[el2_pic_ctl.scala 47:8] - node _T_1182 = bits(extintsrc_req_sync, 19, 19) @[el2_pic_ctl.scala 170:43] - node _T_1183 = bits(gw_config_reg[19], 0, 0) @[el2_pic_ctl.scala 170:64] - node _T_1184 = bits(gw_config_reg[19], 1, 1) @[el2_pic_ctl.scala 170:85] - node _T_1185 = bits(gw_clear_reg_we_19, 0, 0) @[el2_pic_ctl.scala 170:115] + node _T_1174 = xor(_T_1170, _T_1171) @[el2_pic_ctl.scala 37:50] + node _T_1175 = eq(_T_1173, UInt<1>("h00")) @[el2_pic_ctl.scala 37:92] + node _T_1176 = and(gw_int_pending_17, _T_1175) @[el2_pic_ctl.scala 37:90] + node gw_int_pending_in_17 = or(_T_1174, _T_1176) @[el2_pic_ctl.scala 37:72] + reg _T_1177 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 38:30] + _T_1177 <= gw_int_pending_in_17 @[el2_pic_ctl.scala 38:30] + gw_int_pending_17 <= _T_1177 @[el2_pic_ctl.scala 38:20] + node _T_1178 = bits(_T_1172, 0, 0) @[el2_pic_ctl.scala 39:30] + node _T_1179 = xor(_T_1170, _T_1171) @[el2_pic_ctl.scala 39:55] + node _T_1180 = or(_T_1179, gw_int_pending_17) @[el2_pic_ctl.scala 39:78] + node _T_1181 = xor(_T_1170, _T_1171) @[el2_pic_ctl.scala 39:117] + node extintsrc_req_gw_18 = mux(_T_1178, _T_1180, _T_1181) @[el2_pic_ctl.scala 39:8] + node _T_1182 = bits(extintsrc_req_sync, 19, 19) @[el2_pic_ctl.scala 162:43] + node _T_1183 = bits(gw_config_reg[19], 0, 0) @[el2_pic_ctl.scala 162:64] + node _T_1184 = bits(gw_config_reg[19], 1, 1) @[el2_pic_ctl.scala 162:85] + node _T_1185 = bits(gw_clear_reg_we_19, 0, 0) @[el2_pic_ctl.scala 162:115] wire gw_int_pending_18 : UInt<1> gw_int_pending_18 <= UInt<1>("h00") - node _T_1186 = xor(_T_1182, _T_1183) @[el2_pic_ctl.scala 45:50] - node _T_1187 = eq(_T_1185, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] - node _T_1188 = and(gw_int_pending_18, _T_1187) @[el2_pic_ctl.scala 45:90] - node gw_int_pending_in_18 = or(_T_1186, _T_1188) @[el2_pic_ctl.scala 45:72] - reg _T_1189 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] - _T_1189 <= gw_int_pending_in_18 @[el2_pic_ctl.scala 46:30] - gw_int_pending_18 <= _T_1189 @[el2_pic_ctl.scala 46:20] - node _T_1190 = bits(_T_1184, 0, 0) @[el2_pic_ctl.scala 47:30] - node _T_1191 = xor(_T_1182, _T_1183) @[el2_pic_ctl.scala 47:55] - node _T_1192 = or(_T_1191, gw_int_pending_18) @[el2_pic_ctl.scala 47:78] - node _T_1193 = xor(_T_1182, _T_1183) @[el2_pic_ctl.scala 47:117] - node extintsrc_req_gw_19 = mux(_T_1190, _T_1192, _T_1193) @[el2_pic_ctl.scala 47:8] - node _T_1194 = bits(extintsrc_req_sync, 20, 20) @[el2_pic_ctl.scala 170:43] - node _T_1195 = bits(gw_config_reg[20], 0, 0) @[el2_pic_ctl.scala 170:64] - node _T_1196 = bits(gw_config_reg[20], 1, 1) @[el2_pic_ctl.scala 170:85] - node _T_1197 = bits(gw_clear_reg_we_20, 0, 0) @[el2_pic_ctl.scala 170:115] + node _T_1186 = xor(_T_1182, _T_1183) @[el2_pic_ctl.scala 37:50] + node _T_1187 = eq(_T_1185, UInt<1>("h00")) @[el2_pic_ctl.scala 37:92] + node _T_1188 = and(gw_int_pending_18, _T_1187) @[el2_pic_ctl.scala 37:90] + node gw_int_pending_in_18 = or(_T_1186, _T_1188) @[el2_pic_ctl.scala 37:72] + reg _T_1189 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 38:30] + _T_1189 <= gw_int_pending_in_18 @[el2_pic_ctl.scala 38:30] + gw_int_pending_18 <= _T_1189 @[el2_pic_ctl.scala 38:20] + node _T_1190 = bits(_T_1184, 0, 0) @[el2_pic_ctl.scala 39:30] + node _T_1191 = xor(_T_1182, _T_1183) @[el2_pic_ctl.scala 39:55] + node _T_1192 = or(_T_1191, gw_int_pending_18) @[el2_pic_ctl.scala 39:78] + node _T_1193 = xor(_T_1182, _T_1183) @[el2_pic_ctl.scala 39:117] + node extintsrc_req_gw_19 = mux(_T_1190, _T_1192, _T_1193) @[el2_pic_ctl.scala 39:8] + node _T_1194 = bits(extintsrc_req_sync, 20, 20) @[el2_pic_ctl.scala 162:43] + node _T_1195 = bits(gw_config_reg[20], 0, 0) @[el2_pic_ctl.scala 162:64] + node _T_1196 = bits(gw_config_reg[20], 1, 1) @[el2_pic_ctl.scala 162:85] + node _T_1197 = bits(gw_clear_reg_we_20, 0, 0) @[el2_pic_ctl.scala 162:115] wire gw_int_pending_19 : UInt<1> gw_int_pending_19 <= UInt<1>("h00") - node _T_1198 = xor(_T_1194, _T_1195) @[el2_pic_ctl.scala 45:50] - node _T_1199 = eq(_T_1197, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] - node _T_1200 = and(gw_int_pending_19, _T_1199) @[el2_pic_ctl.scala 45:90] - node gw_int_pending_in_19 = or(_T_1198, _T_1200) @[el2_pic_ctl.scala 45:72] - reg _T_1201 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] - _T_1201 <= gw_int_pending_in_19 @[el2_pic_ctl.scala 46:30] - gw_int_pending_19 <= _T_1201 @[el2_pic_ctl.scala 46:20] - node _T_1202 = bits(_T_1196, 0, 0) @[el2_pic_ctl.scala 47:30] - node _T_1203 = xor(_T_1194, _T_1195) @[el2_pic_ctl.scala 47:55] - node _T_1204 = or(_T_1203, gw_int_pending_19) @[el2_pic_ctl.scala 47:78] - node _T_1205 = xor(_T_1194, _T_1195) @[el2_pic_ctl.scala 47:117] - node extintsrc_req_gw_20 = mux(_T_1202, _T_1204, _T_1205) @[el2_pic_ctl.scala 47:8] - node _T_1206 = bits(extintsrc_req_sync, 21, 21) @[el2_pic_ctl.scala 170:43] - node _T_1207 = bits(gw_config_reg[21], 0, 0) @[el2_pic_ctl.scala 170:64] - node _T_1208 = bits(gw_config_reg[21], 1, 1) @[el2_pic_ctl.scala 170:85] - node _T_1209 = bits(gw_clear_reg_we_21, 0, 0) @[el2_pic_ctl.scala 170:115] + node _T_1198 = xor(_T_1194, _T_1195) @[el2_pic_ctl.scala 37:50] + node _T_1199 = eq(_T_1197, UInt<1>("h00")) @[el2_pic_ctl.scala 37:92] + node _T_1200 = and(gw_int_pending_19, _T_1199) @[el2_pic_ctl.scala 37:90] + node gw_int_pending_in_19 = or(_T_1198, _T_1200) @[el2_pic_ctl.scala 37:72] + reg _T_1201 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 38:30] + _T_1201 <= gw_int_pending_in_19 @[el2_pic_ctl.scala 38:30] + gw_int_pending_19 <= _T_1201 @[el2_pic_ctl.scala 38:20] + node _T_1202 = bits(_T_1196, 0, 0) @[el2_pic_ctl.scala 39:30] + node _T_1203 = xor(_T_1194, _T_1195) @[el2_pic_ctl.scala 39:55] + node _T_1204 = or(_T_1203, gw_int_pending_19) @[el2_pic_ctl.scala 39:78] + node _T_1205 = xor(_T_1194, _T_1195) @[el2_pic_ctl.scala 39:117] + node extintsrc_req_gw_20 = mux(_T_1202, _T_1204, _T_1205) @[el2_pic_ctl.scala 39:8] + node _T_1206 = bits(extintsrc_req_sync, 21, 21) @[el2_pic_ctl.scala 162:43] + node _T_1207 = bits(gw_config_reg[21], 0, 0) @[el2_pic_ctl.scala 162:64] + node _T_1208 = bits(gw_config_reg[21], 1, 1) @[el2_pic_ctl.scala 162:85] + node _T_1209 = bits(gw_clear_reg_we_21, 0, 0) @[el2_pic_ctl.scala 162:115] wire gw_int_pending_20 : UInt<1> gw_int_pending_20 <= UInt<1>("h00") - node _T_1210 = xor(_T_1206, _T_1207) @[el2_pic_ctl.scala 45:50] - node _T_1211 = eq(_T_1209, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] - node _T_1212 = and(gw_int_pending_20, _T_1211) @[el2_pic_ctl.scala 45:90] - node gw_int_pending_in_20 = or(_T_1210, _T_1212) @[el2_pic_ctl.scala 45:72] - reg _T_1213 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] - _T_1213 <= gw_int_pending_in_20 @[el2_pic_ctl.scala 46:30] - gw_int_pending_20 <= _T_1213 @[el2_pic_ctl.scala 46:20] - node _T_1214 = bits(_T_1208, 0, 0) @[el2_pic_ctl.scala 47:30] - node _T_1215 = xor(_T_1206, _T_1207) @[el2_pic_ctl.scala 47:55] - node _T_1216 = or(_T_1215, gw_int_pending_20) @[el2_pic_ctl.scala 47:78] - node _T_1217 = xor(_T_1206, _T_1207) @[el2_pic_ctl.scala 47:117] - node extintsrc_req_gw_21 = mux(_T_1214, _T_1216, _T_1217) @[el2_pic_ctl.scala 47:8] - node _T_1218 = bits(extintsrc_req_sync, 22, 22) @[el2_pic_ctl.scala 170:43] - node _T_1219 = bits(gw_config_reg[22], 0, 0) @[el2_pic_ctl.scala 170:64] - node _T_1220 = bits(gw_config_reg[22], 1, 1) @[el2_pic_ctl.scala 170:85] - node _T_1221 = bits(gw_clear_reg_we_22, 0, 0) @[el2_pic_ctl.scala 170:115] + node _T_1210 = xor(_T_1206, _T_1207) @[el2_pic_ctl.scala 37:50] + node _T_1211 = eq(_T_1209, UInt<1>("h00")) @[el2_pic_ctl.scala 37:92] + node _T_1212 = and(gw_int_pending_20, _T_1211) @[el2_pic_ctl.scala 37:90] + node gw_int_pending_in_20 = or(_T_1210, _T_1212) @[el2_pic_ctl.scala 37:72] + reg _T_1213 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 38:30] + _T_1213 <= gw_int_pending_in_20 @[el2_pic_ctl.scala 38:30] + gw_int_pending_20 <= _T_1213 @[el2_pic_ctl.scala 38:20] + node _T_1214 = bits(_T_1208, 0, 0) @[el2_pic_ctl.scala 39:30] + node _T_1215 = xor(_T_1206, _T_1207) @[el2_pic_ctl.scala 39:55] + node _T_1216 = or(_T_1215, gw_int_pending_20) @[el2_pic_ctl.scala 39:78] + node _T_1217 = xor(_T_1206, _T_1207) @[el2_pic_ctl.scala 39:117] + node extintsrc_req_gw_21 = mux(_T_1214, _T_1216, _T_1217) @[el2_pic_ctl.scala 39:8] + node _T_1218 = bits(extintsrc_req_sync, 22, 22) @[el2_pic_ctl.scala 162:43] + node _T_1219 = bits(gw_config_reg[22], 0, 0) @[el2_pic_ctl.scala 162:64] + node _T_1220 = bits(gw_config_reg[22], 1, 1) @[el2_pic_ctl.scala 162:85] + node _T_1221 = bits(gw_clear_reg_we_22, 0, 0) @[el2_pic_ctl.scala 162:115] wire gw_int_pending_21 : UInt<1> gw_int_pending_21 <= UInt<1>("h00") - node _T_1222 = xor(_T_1218, _T_1219) @[el2_pic_ctl.scala 45:50] - node _T_1223 = eq(_T_1221, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] - node _T_1224 = and(gw_int_pending_21, _T_1223) @[el2_pic_ctl.scala 45:90] - node gw_int_pending_in_21 = or(_T_1222, _T_1224) @[el2_pic_ctl.scala 45:72] - reg _T_1225 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] - _T_1225 <= gw_int_pending_in_21 @[el2_pic_ctl.scala 46:30] - gw_int_pending_21 <= _T_1225 @[el2_pic_ctl.scala 46:20] - node _T_1226 = bits(_T_1220, 0, 0) @[el2_pic_ctl.scala 47:30] - node _T_1227 = xor(_T_1218, _T_1219) @[el2_pic_ctl.scala 47:55] - node _T_1228 = or(_T_1227, gw_int_pending_21) @[el2_pic_ctl.scala 47:78] - node _T_1229 = xor(_T_1218, _T_1219) @[el2_pic_ctl.scala 47:117] - node extintsrc_req_gw_22 = mux(_T_1226, _T_1228, _T_1229) @[el2_pic_ctl.scala 47:8] - node _T_1230 = bits(extintsrc_req_sync, 23, 23) @[el2_pic_ctl.scala 170:43] - node _T_1231 = bits(gw_config_reg[23], 0, 0) @[el2_pic_ctl.scala 170:64] - node _T_1232 = bits(gw_config_reg[23], 1, 1) @[el2_pic_ctl.scala 170:85] - node _T_1233 = bits(gw_clear_reg_we_23, 0, 0) @[el2_pic_ctl.scala 170:115] + node _T_1222 = xor(_T_1218, _T_1219) @[el2_pic_ctl.scala 37:50] + node _T_1223 = eq(_T_1221, UInt<1>("h00")) @[el2_pic_ctl.scala 37:92] + node _T_1224 = and(gw_int_pending_21, _T_1223) @[el2_pic_ctl.scala 37:90] + node gw_int_pending_in_21 = or(_T_1222, _T_1224) @[el2_pic_ctl.scala 37:72] + reg _T_1225 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 38:30] + _T_1225 <= gw_int_pending_in_21 @[el2_pic_ctl.scala 38:30] + gw_int_pending_21 <= _T_1225 @[el2_pic_ctl.scala 38:20] + node _T_1226 = bits(_T_1220, 0, 0) @[el2_pic_ctl.scala 39:30] + node _T_1227 = xor(_T_1218, _T_1219) @[el2_pic_ctl.scala 39:55] + node _T_1228 = or(_T_1227, gw_int_pending_21) @[el2_pic_ctl.scala 39:78] + node _T_1229 = xor(_T_1218, _T_1219) @[el2_pic_ctl.scala 39:117] + node extintsrc_req_gw_22 = mux(_T_1226, _T_1228, _T_1229) @[el2_pic_ctl.scala 39:8] + node _T_1230 = bits(extintsrc_req_sync, 23, 23) @[el2_pic_ctl.scala 162:43] + node _T_1231 = bits(gw_config_reg[23], 0, 0) @[el2_pic_ctl.scala 162:64] + node _T_1232 = bits(gw_config_reg[23], 1, 1) @[el2_pic_ctl.scala 162:85] + node _T_1233 = bits(gw_clear_reg_we_23, 0, 0) @[el2_pic_ctl.scala 162:115] wire gw_int_pending_22 : UInt<1> gw_int_pending_22 <= UInt<1>("h00") - node _T_1234 = xor(_T_1230, _T_1231) @[el2_pic_ctl.scala 45:50] - node _T_1235 = eq(_T_1233, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] - node _T_1236 = and(gw_int_pending_22, _T_1235) @[el2_pic_ctl.scala 45:90] - node gw_int_pending_in_22 = or(_T_1234, _T_1236) @[el2_pic_ctl.scala 45:72] - reg _T_1237 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] - _T_1237 <= gw_int_pending_in_22 @[el2_pic_ctl.scala 46:30] - gw_int_pending_22 <= _T_1237 @[el2_pic_ctl.scala 46:20] - node _T_1238 = bits(_T_1232, 0, 0) @[el2_pic_ctl.scala 47:30] - node _T_1239 = xor(_T_1230, _T_1231) @[el2_pic_ctl.scala 47:55] - node _T_1240 = or(_T_1239, gw_int_pending_22) @[el2_pic_ctl.scala 47:78] - node _T_1241 = xor(_T_1230, _T_1231) @[el2_pic_ctl.scala 47:117] - node extintsrc_req_gw_23 = mux(_T_1238, _T_1240, _T_1241) @[el2_pic_ctl.scala 47:8] - node _T_1242 = bits(extintsrc_req_sync, 24, 24) @[el2_pic_ctl.scala 170:43] - node _T_1243 = bits(gw_config_reg[24], 0, 0) @[el2_pic_ctl.scala 170:64] - node _T_1244 = bits(gw_config_reg[24], 1, 1) @[el2_pic_ctl.scala 170:85] - node _T_1245 = bits(gw_clear_reg_we_24, 0, 0) @[el2_pic_ctl.scala 170:115] + node _T_1234 = xor(_T_1230, _T_1231) @[el2_pic_ctl.scala 37:50] + node _T_1235 = eq(_T_1233, UInt<1>("h00")) @[el2_pic_ctl.scala 37:92] + node _T_1236 = and(gw_int_pending_22, _T_1235) @[el2_pic_ctl.scala 37:90] + node gw_int_pending_in_22 = or(_T_1234, _T_1236) @[el2_pic_ctl.scala 37:72] + reg _T_1237 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 38:30] + _T_1237 <= gw_int_pending_in_22 @[el2_pic_ctl.scala 38:30] + gw_int_pending_22 <= _T_1237 @[el2_pic_ctl.scala 38:20] + node _T_1238 = bits(_T_1232, 0, 0) @[el2_pic_ctl.scala 39:30] + node _T_1239 = xor(_T_1230, _T_1231) @[el2_pic_ctl.scala 39:55] + node _T_1240 = or(_T_1239, gw_int_pending_22) @[el2_pic_ctl.scala 39:78] + node _T_1241 = xor(_T_1230, _T_1231) @[el2_pic_ctl.scala 39:117] + node extintsrc_req_gw_23 = mux(_T_1238, _T_1240, _T_1241) @[el2_pic_ctl.scala 39:8] + node _T_1242 = bits(extintsrc_req_sync, 24, 24) @[el2_pic_ctl.scala 162:43] + node _T_1243 = bits(gw_config_reg[24], 0, 0) @[el2_pic_ctl.scala 162:64] + node _T_1244 = bits(gw_config_reg[24], 1, 1) @[el2_pic_ctl.scala 162:85] + node _T_1245 = bits(gw_clear_reg_we_24, 0, 0) @[el2_pic_ctl.scala 162:115] wire gw_int_pending_23 : UInt<1> gw_int_pending_23 <= UInt<1>("h00") - node _T_1246 = xor(_T_1242, _T_1243) @[el2_pic_ctl.scala 45:50] - node _T_1247 = eq(_T_1245, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] - node _T_1248 = and(gw_int_pending_23, _T_1247) @[el2_pic_ctl.scala 45:90] - node gw_int_pending_in_23 = or(_T_1246, _T_1248) @[el2_pic_ctl.scala 45:72] - reg _T_1249 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] - _T_1249 <= gw_int_pending_in_23 @[el2_pic_ctl.scala 46:30] - gw_int_pending_23 <= _T_1249 @[el2_pic_ctl.scala 46:20] - node _T_1250 = bits(_T_1244, 0, 0) @[el2_pic_ctl.scala 47:30] - node _T_1251 = xor(_T_1242, _T_1243) @[el2_pic_ctl.scala 47:55] - node _T_1252 = or(_T_1251, gw_int_pending_23) @[el2_pic_ctl.scala 47:78] - node _T_1253 = xor(_T_1242, _T_1243) @[el2_pic_ctl.scala 47:117] - node extintsrc_req_gw_24 = mux(_T_1250, _T_1252, _T_1253) @[el2_pic_ctl.scala 47:8] - node _T_1254 = bits(extintsrc_req_sync, 25, 25) @[el2_pic_ctl.scala 170:43] - node _T_1255 = bits(gw_config_reg[25], 0, 0) @[el2_pic_ctl.scala 170:64] - node _T_1256 = bits(gw_config_reg[25], 1, 1) @[el2_pic_ctl.scala 170:85] - node _T_1257 = bits(gw_clear_reg_we_25, 0, 0) @[el2_pic_ctl.scala 170:115] + node _T_1246 = xor(_T_1242, _T_1243) @[el2_pic_ctl.scala 37:50] + node _T_1247 = eq(_T_1245, UInt<1>("h00")) @[el2_pic_ctl.scala 37:92] + node _T_1248 = and(gw_int_pending_23, _T_1247) @[el2_pic_ctl.scala 37:90] + node gw_int_pending_in_23 = or(_T_1246, _T_1248) @[el2_pic_ctl.scala 37:72] + reg _T_1249 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 38:30] + _T_1249 <= gw_int_pending_in_23 @[el2_pic_ctl.scala 38:30] + gw_int_pending_23 <= _T_1249 @[el2_pic_ctl.scala 38:20] + node _T_1250 = bits(_T_1244, 0, 0) @[el2_pic_ctl.scala 39:30] + node _T_1251 = xor(_T_1242, _T_1243) @[el2_pic_ctl.scala 39:55] + node _T_1252 = or(_T_1251, gw_int_pending_23) @[el2_pic_ctl.scala 39:78] + node _T_1253 = xor(_T_1242, _T_1243) @[el2_pic_ctl.scala 39:117] + node extintsrc_req_gw_24 = mux(_T_1250, _T_1252, _T_1253) @[el2_pic_ctl.scala 39:8] + node _T_1254 = bits(extintsrc_req_sync, 25, 25) @[el2_pic_ctl.scala 162:43] + node _T_1255 = bits(gw_config_reg[25], 0, 0) @[el2_pic_ctl.scala 162:64] + node _T_1256 = bits(gw_config_reg[25], 1, 1) @[el2_pic_ctl.scala 162:85] + node _T_1257 = bits(gw_clear_reg_we_25, 0, 0) @[el2_pic_ctl.scala 162:115] wire gw_int_pending_24 : UInt<1> gw_int_pending_24 <= UInt<1>("h00") - node _T_1258 = xor(_T_1254, _T_1255) @[el2_pic_ctl.scala 45:50] - node _T_1259 = eq(_T_1257, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] - node _T_1260 = and(gw_int_pending_24, _T_1259) @[el2_pic_ctl.scala 45:90] - node gw_int_pending_in_24 = or(_T_1258, _T_1260) @[el2_pic_ctl.scala 45:72] - reg _T_1261 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] - _T_1261 <= gw_int_pending_in_24 @[el2_pic_ctl.scala 46:30] - gw_int_pending_24 <= _T_1261 @[el2_pic_ctl.scala 46:20] - node _T_1262 = bits(_T_1256, 0, 0) @[el2_pic_ctl.scala 47:30] - node _T_1263 = xor(_T_1254, _T_1255) @[el2_pic_ctl.scala 47:55] - node _T_1264 = or(_T_1263, gw_int_pending_24) @[el2_pic_ctl.scala 47:78] - node _T_1265 = xor(_T_1254, _T_1255) @[el2_pic_ctl.scala 47:117] - node extintsrc_req_gw_25 = mux(_T_1262, _T_1264, _T_1265) @[el2_pic_ctl.scala 47:8] - node _T_1266 = bits(extintsrc_req_sync, 26, 26) @[el2_pic_ctl.scala 170:43] - node _T_1267 = bits(gw_config_reg[26], 0, 0) @[el2_pic_ctl.scala 170:64] - node _T_1268 = bits(gw_config_reg[26], 1, 1) @[el2_pic_ctl.scala 170:85] - node _T_1269 = bits(gw_clear_reg_we_26, 0, 0) @[el2_pic_ctl.scala 170:115] + node _T_1258 = xor(_T_1254, _T_1255) @[el2_pic_ctl.scala 37:50] + node _T_1259 = eq(_T_1257, UInt<1>("h00")) @[el2_pic_ctl.scala 37:92] + node _T_1260 = and(gw_int_pending_24, _T_1259) @[el2_pic_ctl.scala 37:90] + node gw_int_pending_in_24 = or(_T_1258, _T_1260) @[el2_pic_ctl.scala 37:72] + reg _T_1261 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 38:30] + _T_1261 <= gw_int_pending_in_24 @[el2_pic_ctl.scala 38:30] + gw_int_pending_24 <= _T_1261 @[el2_pic_ctl.scala 38:20] + node _T_1262 = bits(_T_1256, 0, 0) @[el2_pic_ctl.scala 39:30] + node _T_1263 = xor(_T_1254, _T_1255) @[el2_pic_ctl.scala 39:55] + node _T_1264 = or(_T_1263, gw_int_pending_24) @[el2_pic_ctl.scala 39:78] + node _T_1265 = xor(_T_1254, _T_1255) @[el2_pic_ctl.scala 39:117] + node extintsrc_req_gw_25 = mux(_T_1262, _T_1264, _T_1265) @[el2_pic_ctl.scala 39:8] + node _T_1266 = bits(extintsrc_req_sync, 26, 26) @[el2_pic_ctl.scala 162:43] + node _T_1267 = bits(gw_config_reg[26], 0, 0) @[el2_pic_ctl.scala 162:64] + node _T_1268 = bits(gw_config_reg[26], 1, 1) @[el2_pic_ctl.scala 162:85] + node _T_1269 = bits(gw_clear_reg_we_26, 0, 0) @[el2_pic_ctl.scala 162:115] wire gw_int_pending_25 : UInt<1> gw_int_pending_25 <= UInt<1>("h00") - node _T_1270 = xor(_T_1266, _T_1267) @[el2_pic_ctl.scala 45:50] - node _T_1271 = eq(_T_1269, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] - node _T_1272 = and(gw_int_pending_25, _T_1271) @[el2_pic_ctl.scala 45:90] - node gw_int_pending_in_25 = or(_T_1270, _T_1272) @[el2_pic_ctl.scala 45:72] - reg _T_1273 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] - _T_1273 <= gw_int_pending_in_25 @[el2_pic_ctl.scala 46:30] - gw_int_pending_25 <= _T_1273 @[el2_pic_ctl.scala 46:20] - node _T_1274 = bits(_T_1268, 0, 0) @[el2_pic_ctl.scala 47:30] - node _T_1275 = xor(_T_1266, _T_1267) @[el2_pic_ctl.scala 47:55] - node _T_1276 = or(_T_1275, gw_int_pending_25) @[el2_pic_ctl.scala 47:78] - node _T_1277 = xor(_T_1266, _T_1267) @[el2_pic_ctl.scala 47:117] - node extintsrc_req_gw_26 = mux(_T_1274, _T_1276, _T_1277) @[el2_pic_ctl.scala 47:8] - node _T_1278 = bits(extintsrc_req_sync, 27, 27) @[el2_pic_ctl.scala 170:43] - node _T_1279 = bits(gw_config_reg[27], 0, 0) @[el2_pic_ctl.scala 170:64] - node _T_1280 = bits(gw_config_reg[27], 1, 1) @[el2_pic_ctl.scala 170:85] - node _T_1281 = bits(gw_clear_reg_we_27, 0, 0) @[el2_pic_ctl.scala 170:115] + node _T_1270 = xor(_T_1266, _T_1267) @[el2_pic_ctl.scala 37:50] + node _T_1271 = eq(_T_1269, UInt<1>("h00")) @[el2_pic_ctl.scala 37:92] + node _T_1272 = and(gw_int_pending_25, _T_1271) @[el2_pic_ctl.scala 37:90] + node gw_int_pending_in_25 = or(_T_1270, _T_1272) @[el2_pic_ctl.scala 37:72] + reg _T_1273 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 38:30] + _T_1273 <= gw_int_pending_in_25 @[el2_pic_ctl.scala 38:30] + gw_int_pending_25 <= _T_1273 @[el2_pic_ctl.scala 38:20] + node _T_1274 = bits(_T_1268, 0, 0) @[el2_pic_ctl.scala 39:30] + node _T_1275 = xor(_T_1266, _T_1267) @[el2_pic_ctl.scala 39:55] + node _T_1276 = or(_T_1275, gw_int_pending_25) @[el2_pic_ctl.scala 39:78] + node _T_1277 = xor(_T_1266, _T_1267) @[el2_pic_ctl.scala 39:117] + node extintsrc_req_gw_26 = mux(_T_1274, _T_1276, _T_1277) @[el2_pic_ctl.scala 39:8] + node _T_1278 = bits(extintsrc_req_sync, 27, 27) @[el2_pic_ctl.scala 162:43] + node _T_1279 = bits(gw_config_reg[27], 0, 0) @[el2_pic_ctl.scala 162:64] + node _T_1280 = bits(gw_config_reg[27], 1, 1) @[el2_pic_ctl.scala 162:85] + node _T_1281 = bits(gw_clear_reg_we_27, 0, 0) @[el2_pic_ctl.scala 162:115] wire gw_int_pending_26 : UInt<1> gw_int_pending_26 <= UInt<1>("h00") - node _T_1282 = xor(_T_1278, _T_1279) @[el2_pic_ctl.scala 45:50] - node _T_1283 = eq(_T_1281, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] - node _T_1284 = and(gw_int_pending_26, _T_1283) @[el2_pic_ctl.scala 45:90] - node gw_int_pending_in_26 = or(_T_1282, _T_1284) @[el2_pic_ctl.scala 45:72] - reg _T_1285 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] - _T_1285 <= gw_int_pending_in_26 @[el2_pic_ctl.scala 46:30] - gw_int_pending_26 <= _T_1285 @[el2_pic_ctl.scala 46:20] - node _T_1286 = bits(_T_1280, 0, 0) @[el2_pic_ctl.scala 47:30] - node _T_1287 = xor(_T_1278, _T_1279) @[el2_pic_ctl.scala 47:55] - node _T_1288 = or(_T_1287, gw_int_pending_26) @[el2_pic_ctl.scala 47:78] - node _T_1289 = xor(_T_1278, _T_1279) @[el2_pic_ctl.scala 47:117] - node extintsrc_req_gw_27 = mux(_T_1286, _T_1288, _T_1289) @[el2_pic_ctl.scala 47:8] - node _T_1290 = bits(extintsrc_req_sync, 28, 28) @[el2_pic_ctl.scala 170:43] - node _T_1291 = bits(gw_config_reg[28], 0, 0) @[el2_pic_ctl.scala 170:64] - node _T_1292 = bits(gw_config_reg[28], 1, 1) @[el2_pic_ctl.scala 170:85] - node _T_1293 = bits(gw_clear_reg_we_28, 0, 0) @[el2_pic_ctl.scala 170:115] + node _T_1282 = xor(_T_1278, _T_1279) @[el2_pic_ctl.scala 37:50] + node _T_1283 = eq(_T_1281, UInt<1>("h00")) @[el2_pic_ctl.scala 37:92] + node _T_1284 = and(gw_int_pending_26, _T_1283) @[el2_pic_ctl.scala 37:90] + node gw_int_pending_in_26 = or(_T_1282, _T_1284) @[el2_pic_ctl.scala 37:72] + reg _T_1285 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 38:30] + _T_1285 <= gw_int_pending_in_26 @[el2_pic_ctl.scala 38:30] + gw_int_pending_26 <= _T_1285 @[el2_pic_ctl.scala 38:20] + node _T_1286 = bits(_T_1280, 0, 0) @[el2_pic_ctl.scala 39:30] + node _T_1287 = xor(_T_1278, _T_1279) @[el2_pic_ctl.scala 39:55] + node _T_1288 = or(_T_1287, gw_int_pending_26) @[el2_pic_ctl.scala 39:78] + node _T_1289 = xor(_T_1278, _T_1279) @[el2_pic_ctl.scala 39:117] + node extintsrc_req_gw_27 = mux(_T_1286, _T_1288, _T_1289) @[el2_pic_ctl.scala 39:8] + node _T_1290 = bits(extintsrc_req_sync, 28, 28) @[el2_pic_ctl.scala 162:43] + node _T_1291 = bits(gw_config_reg[28], 0, 0) @[el2_pic_ctl.scala 162:64] + node _T_1292 = bits(gw_config_reg[28], 1, 1) @[el2_pic_ctl.scala 162:85] + node _T_1293 = bits(gw_clear_reg_we_28, 0, 0) @[el2_pic_ctl.scala 162:115] wire gw_int_pending_27 : UInt<1> gw_int_pending_27 <= UInt<1>("h00") - node _T_1294 = xor(_T_1290, _T_1291) @[el2_pic_ctl.scala 45:50] - node _T_1295 = eq(_T_1293, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] - node _T_1296 = and(gw_int_pending_27, _T_1295) @[el2_pic_ctl.scala 45:90] - node gw_int_pending_in_27 = or(_T_1294, _T_1296) @[el2_pic_ctl.scala 45:72] - reg _T_1297 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] - _T_1297 <= gw_int_pending_in_27 @[el2_pic_ctl.scala 46:30] - gw_int_pending_27 <= _T_1297 @[el2_pic_ctl.scala 46:20] - node _T_1298 = bits(_T_1292, 0, 0) @[el2_pic_ctl.scala 47:30] - node _T_1299 = xor(_T_1290, _T_1291) @[el2_pic_ctl.scala 47:55] - node _T_1300 = or(_T_1299, gw_int_pending_27) @[el2_pic_ctl.scala 47:78] - node _T_1301 = xor(_T_1290, _T_1291) @[el2_pic_ctl.scala 47:117] - node extintsrc_req_gw_28 = mux(_T_1298, _T_1300, _T_1301) @[el2_pic_ctl.scala 47:8] - node _T_1302 = bits(extintsrc_req_sync, 29, 29) @[el2_pic_ctl.scala 170:43] - node _T_1303 = bits(gw_config_reg[29], 0, 0) @[el2_pic_ctl.scala 170:64] - node _T_1304 = bits(gw_config_reg[29], 1, 1) @[el2_pic_ctl.scala 170:85] - node _T_1305 = bits(gw_clear_reg_we_29, 0, 0) @[el2_pic_ctl.scala 170:115] + node _T_1294 = xor(_T_1290, _T_1291) @[el2_pic_ctl.scala 37:50] + node _T_1295 = eq(_T_1293, UInt<1>("h00")) @[el2_pic_ctl.scala 37:92] + node _T_1296 = and(gw_int_pending_27, _T_1295) @[el2_pic_ctl.scala 37:90] + node gw_int_pending_in_27 = or(_T_1294, _T_1296) @[el2_pic_ctl.scala 37:72] + reg _T_1297 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 38:30] + _T_1297 <= gw_int_pending_in_27 @[el2_pic_ctl.scala 38:30] + gw_int_pending_27 <= _T_1297 @[el2_pic_ctl.scala 38:20] + node _T_1298 = bits(_T_1292, 0, 0) @[el2_pic_ctl.scala 39:30] + node _T_1299 = xor(_T_1290, _T_1291) @[el2_pic_ctl.scala 39:55] + node _T_1300 = or(_T_1299, gw_int_pending_27) @[el2_pic_ctl.scala 39:78] + node _T_1301 = xor(_T_1290, _T_1291) @[el2_pic_ctl.scala 39:117] + node extintsrc_req_gw_28 = mux(_T_1298, _T_1300, _T_1301) @[el2_pic_ctl.scala 39:8] + node _T_1302 = bits(extintsrc_req_sync, 29, 29) @[el2_pic_ctl.scala 162:43] + node _T_1303 = bits(gw_config_reg[29], 0, 0) @[el2_pic_ctl.scala 162:64] + node _T_1304 = bits(gw_config_reg[29], 1, 1) @[el2_pic_ctl.scala 162:85] + node _T_1305 = bits(gw_clear_reg_we_29, 0, 0) @[el2_pic_ctl.scala 162:115] wire gw_int_pending_28 : UInt<1> gw_int_pending_28 <= UInt<1>("h00") - node _T_1306 = xor(_T_1302, _T_1303) @[el2_pic_ctl.scala 45:50] - node _T_1307 = eq(_T_1305, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] - node _T_1308 = and(gw_int_pending_28, _T_1307) @[el2_pic_ctl.scala 45:90] - node gw_int_pending_in_28 = or(_T_1306, _T_1308) @[el2_pic_ctl.scala 45:72] - reg _T_1309 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] - _T_1309 <= gw_int_pending_in_28 @[el2_pic_ctl.scala 46:30] - gw_int_pending_28 <= _T_1309 @[el2_pic_ctl.scala 46:20] - node _T_1310 = bits(_T_1304, 0, 0) @[el2_pic_ctl.scala 47:30] - node _T_1311 = xor(_T_1302, _T_1303) @[el2_pic_ctl.scala 47:55] - node _T_1312 = or(_T_1311, gw_int_pending_28) @[el2_pic_ctl.scala 47:78] - node _T_1313 = xor(_T_1302, _T_1303) @[el2_pic_ctl.scala 47:117] - node extintsrc_req_gw_29 = mux(_T_1310, _T_1312, _T_1313) @[el2_pic_ctl.scala 47:8] - node _T_1314 = bits(extintsrc_req_sync, 30, 30) @[el2_pic_ctl.scala 170:43] - node _T_1315 = bits(gw_config_reg[30], 0, 0) @[el2_pic_ctl.scala 170:64] - node _T_1316 = bits(gw_config_reg[30], 1, 1) @[el2_pic_ctl.scala 170:85] - node _T_1317 = bits(gw_clear_reg_we_30, 0, 0) @[el2_pic_ctl.scala 170:115] + node _T_1306 = xor(_T_1302, _T_1303) @[el2_pic_ctl.scala 37:50] + node _T_1307 = eq(_T_1305, UInt<1>("h00")) @[el2_pic_ctl.scala 37:92] + node _T_1308 = and(gw_int_pending_28, _T_1307) @[el2_pic_ctl.scala 37:90] + node gw_int_pending_in_28 = or(_T_1306, _T_1308) @[el2_pic_ctl.scala 37:72] + reg _T_1309 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 38:30] + _T_1309 <= gw_int_pending_in_28 @[el2_pic_ctl.scala 38:30] + gw_int_pending_28 <= _T_1309 @[el2_pic_ctl.scala 38:20] + node _T_1310 = bits(_T_1304, 0, 0) @[el2_pic_ctl.scala 39:30] + node _T_1311 = xor(_T_1302, _T_1303) @[el2_pic_ctl.scala 39:55] + node _T_1312 = or(_T_1311, gw_int_pending_28) @[el2_pic_ctl.scala 39:78] + node _T_1313 = xor(_T_1302, _T_1303) @[el2_pic_ctl.scala 39:117] + node extintsrc_req_gw_29 = mux(_T_1310, _T_1312, _T_1313) @[el2_pic_ctl.scala 39:8] + node _T_1314 = bits(extintsrc_req_sync, 30, 30) @[el2_pic_ctl.scala 162:43] + node _T_1315 = bits(gw_config_reg[30], 0, 0) @[el2_pic_ctl.scala 162:64] + node _T_1316 = bits(gw_config_reg[30], 1, 1) @[el2_pic_ctl.scala 162:85] + node _T_1317 = bits(gw_clear_reg_we_30, 0, 0) @[el2_pic_ctl.scala 162:115] wire gw_int_pending_29 : UInt<1> gw_int_pending_29 <= UInt<1>("h00") - node _T_1318 = xor(_T_1314, _T_1315) @[el2_pic_ctl.scala 45:50] - node _T_1319 = eq(_T_1317, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] - node _T_1320 = and(gw_int_pending_29, _T_1319) @[el2_pic_ctl.scala 45:90] - node gw_int_pending_in_29 = or(_T_1318, _T_1320) @[el2_pic_ctl.scala 45:72] - reg _T_1321 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] - _T_1321 <= gw_int_pending_in_29 @[el2_pic_ctl.scala 46:30] - gw_int_pending_29 <= _T_1321 @[el2_pic_ctl.scala 46:20] - node _T_1322 = bits(_T_1316, 0, 0) @[el2_pic_ctl.scala 47:30] - node _T_1323 = xor(_T_1314, _T_1315) @[el2_pic_ctl.scala 47:55] - node _T_1324 = or(_T_1323, gw_int_pending_29) @[el2_pic_ctl.scala 47:78] - node _T_1325 = xor(_T_1314, _T_1315) @[el2_pic_ctl.scala 47:117] - node extintsrc_req_gw_30 = mux(_T_1322, _T_1324, _T_1325) @[el2_pic_ctl.scala 47:8] - node _T_1326 = bits(extintsrc_req_sync, 31, 31) @[el2_pic_ctl.scala 170:43] - node _T_1327 = bits(gw_config_reg[31], 0, 0) @[el2_pic_ctl.scala 170:64] - node _T_1328 = bits(gw_config_reg[31], 1, 1) @[el2_pic_ctl.scala 170:85] - node _T_1329 = bits(gw_clear_reg_we_31, 0, 0) @[el2_pic_ctl.scala 170:115] + node _T_1318 = xor(_T_1314, _T_1315) @[el2_pic_ctl.scala 37:50] + node _T_1319 = eq(_T_1317, UInt<1>("h00")) @[el2_pic_ctl.scala 37:92] + node _T_1320 = and(gw_int_pending_29, _T_1319) @[el2_pic_ctl.scala 37:90] + node gw_int_pending_in_29 = or(_T_1318, _T_1320) @[el2_pic_ctl.scala 37:72] + reg _T_1321 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 38:30] + _T_1321 <= gw_int_pending_in_29 @[el2_pic_ctl.scala 38:30] + gw_int_pending_29 <= _T_1321 @[el2_pic_ctl.scala 38:20] + node _T_1322 = bits(_T_1316, 0, 0) @[el2_pic_ctl.scala 39:30] + node _T_1323 = xor(_T_1314, _T_1315) @[el2_pic_ctl.scala 39:55] + node _T_1324 = or(_T_1323, gw_int_pending_29) @[el2_pic_ctl.scala 39:78] + node _T_1325 = xor(_T_1314, _T_1315) @[el2_pic_ctl.scala 39:117] + node extintsrc_req_gw_30 = mux(_T_1322, _T_1324, _T_1325) @[el2_pic_ctl.scala 39:8] + node _T_1326 = bits(extintsrc_req_sync, 31, 31) @[el2_pic_ctl.scala 162:43] + node _T_1327 = bits(gw_config_reg[31], 0, 0) @[el2_pic_ctl.scala 162:64] + node _T_1328 = bits(gw_config_reg[31], 1, 1) @[el2_pic_ctl.scala 162:85] + node _T_1329 = bits(gw_clear_reg_we_31, 0, 0) @[el2_pic_ctl.scala 162:115] wire gw_int_pending_30 : UInt<1> gw_int_pending_30 <= UInt<1>("h00") - node _T_1330 = xor(_T_1326, _T_1327) @[el2_pic_ctl.scala 45:50] - node _T_1331 = eq(_T_1329, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] - node _T_1332 = and(gw_int_pending_30, _T_1331) @[el2_pic_ctl.scala 45:90] - node gw_int_pending_in_30 = or(_T_1330, _T_1332) @[el2_pic_ctl.scala 45:72] - reg _T_1333 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] - _T_1333 <= gw_int_pending_in_30 @[el2_pic_ctl.scala 46:30] - gw_int_pending_30 <= _T_1333 @[el2_pic_ctl.scala 46:20] - node _T_1334 = bits(_T_1328, 0, 0) @[el2_pic_ctl.scala 47:30] - node _T_1335 = xor(_T_1326, _T_1327) @[el2_pic_ctl.scala 47:55] - node _T_1336 = or(_T_1335, gw_int_pending_30) @[el2_pic_ctl.scala 47:78] - node _T_1337 = xor(_T_1326, _T_1327) @[el2_pic_ctl.scala 47:117] - node extintsrc_req_gw_31 = mux(_T_1334, _T_1336, _T_1337) @[el2_pic_ctl.scala 47:8] - node _T_1338 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] - node _T_1339 = not(intpriority_reg[0]) @[el2_pic_ctl.scala 174:89] - node _T_1340 = mux(_T_1338, _T_1339, intpriority_reg[0]) @[el2_pic_ctl.scala 174:70] - intpriority_reg_inv[0] <= _T_1340 @[el2_pic_ctl.scala 174:64] - node _T_1341 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] - node _T_1342 = not(intpriority_reg[1]) @[el2_pic_ctl.scala 174:89] - node _T_1343 = mux(_T_1341, _T_1342, intpriority_reg[1]) @[el2_pic_ctl.scala 174:70] - intpriority_reg_inv[1] <= _T_1343 @[el2_pic_ctl.scala 174:64] - node _T_1344 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] - node _T_1345 = not(intpriority_reg[2]) @[el2_pic_ctl.scala 174:89] - node _T_1346 = mux(_T_1344, _T_1345, intpriority_reg[2]) @[el2_pic_ctl.scala 174:70] - intpriority_reg_inv[2] <= _T_1346 @[el2_pic_ctl.scala 174:64] - node _T_1347 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] - node _T_1348 = not(intpriority_reg[3]) @[el2_pic_ctl.scala 174:89] - node _T_1349 = mux(_T_1347, _T_1348, intpriority_reg[3]) @[el2_pic_ctl.scala 174:70] - intpriority_reg_inv[3] <= _T_1349 @[el2_pic_ctl.scala 174:64] - node _T_1350 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] - node _T_1351 = not(intpriority_reg[4]) @[el2_pic_ctl.scala 174:89] - node _T_1352 = mux(_T_1350, _T_1351, intpriority_reg[4]) @[el2_pic_ctl.scala 174:70] - intpriority_reg_inv[4] <= _T_1352 @[el2_pic_ctl.scala 174:64] - node _T_1353 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] - node _T_1354 = not(intpriority_reg[5]) @[el2_pic_ctl.scala 174:89] - node _T_1355 = mux(_T_1353, _T_1354, intpriority_reg[5]) @[el2_pic_ctl.scala 174:70] - intpriority_reg_inv[5] <= _T_1355 @[el2_pic_ctl.scala 174:64] - node _T_1356 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] - node _T_1357 = not(intpriority_reg[6]) @[el2_pic_ctl.scala 174:89] - node _T_1358 = mux(_T_1356, _T_1357, intpriority_reg[6]) @[el2_pic_ctl.scala 174:70] - intpriority_reg_inv[6] <= _T_1358 @[el2_pic_ctl.scala 174:64] - node _T_1359 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] - node _T_1360 = not(intpriority_reg[7]) @[el2_pic_ctl.scala 174:89] - node _T_1361 = mux(_T_1359, _T_1360, intpriority_reg[7]) @[el2_pic_ctl.scala 174:70] - intpriority_reg_inv[7] <= _T_1361 @[el2_pic_ctl.scala 174:64] - node _T_1362 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] - node _T_1363 = not(intpriority_reg[8]) @[el2_pic_ctl.scala 174:89] - node _T_1364 = mux(_T_1362, _T_1363, intpriority_reg[8]) @[el2_pic_ctl.scala 174:70] - intpriority_reg_inv[8] <= _T_1364 @[el2_pic_ctl.scala 174:64] - node _T_1365 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] - node _T_1366 = not(intpriority_reg[9]) @[el2_pic_ctl.scala 174:89] - node _T_1367 = mux(_T_1365, _T_1366, intpriority_reg[9]) @[el2_pic_ctl.scala 174:70] - intpriority_reg_inv[9] <= _T_1367 @[el2_pic_ctl.scala 174:64] - node _T_1368 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] - node _T_1369 = not(intpriority_reg[10]) @[el2_pic_ctl.scala 174:89] - node _T_1370 = mux(_T_1368, _T_1369, intpriority_reg[10]) @[el2_pic_ctl.scala 174:70] - intpriority_reg_inv[10] <= _T_1370 @[el2_pic_ctl.scala 174:64] - node _T_1371 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] - node _T_1372 = not(intpriority_reg[11]) @[el2_pic_ctl.scala 174:89] - node _T_1373 = mux(_T_1371, _T_1372, intpriority_reg[11]) @[el2_pic_ctl.scala 174:70] - intpriority_reg_inv[11] <= _T_1373 @[el2_pic_ctl.scala 174:64] - node _T_1374 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] - node _T_1375 = not(intpriority_reg[12]) @[el2_pic_ctl.scala 174:89] - node _T_1376 = mux(_T_1374, _T_1375, intpriority_reg[12]) @[el2_pic_ctl.scala 174:70] - intpriority_reg_inv[12] <= _T_1376 @[el2_pic_ctl.scala 174:64] - node _T_1377 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] - node _T_1378 = not(intpriority_reg[13]) @[el2_pic_ctl.scala 174:89] - node _T_1379 = mux(_T_1377, _T_1378, intpriority_reg[13]) @[el2_pic_ctl.scala 174:70] - intpriority_reg_inv[13] <= _T_1379 @[el2_pic_ctl.scala 174:64] - node _T_1380 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] - node _T_1381 = not(intpriority_reg[14]) @[el2_pic_ctl.scala 174:89] - node _T_1382 = mux(_T_1380, _T_1381, intpriority_reg[14]) @[el2_pic_ctl.scala 174:70] - intpriority_reg_inv[14] <= _T_1382 @[el2_pic_ctl.scala 174:64] - node _T_1383 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] - node _T_1384 = not(intpriority_reg[15]) @[el2_pic_ctl.scala 174:89] - node _T_1385 = mux(_T_1383, _T_1384, intpriority_reg[15]) @[el2_pic_ctl.scala 174:70] - intpriority_reg_inv[15] <= _T_1385 @[el2_pic_ctl.scala 174:64] - node _T_1386 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] - node _T_1387 = not(intpriority_reg[16]) @[el2_pic_ctl.scala 174:89] - node _T_1388 = mux(_T_1386, _T_1387, intpriority_reg[16]) @[el2_pic_ctl.scala 174:70] - intpriority_reg_inv[16] <= _T_1388 @[el2_pic_ctl.scala 174:64] - node _T_1389 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] - node _T_1390 = not(intpriority_reg[17]) @[el2_pic_ctl.scala 174:89] - node _T_1391 = mux(_T_1389, _T_1390, intpriority_reg[17]) @[el2_pic_ctl.scala 174:70] - intpriority_reg_inv[17] <= _T_1391 @[el2_pic_ctl.scala 174:64] - node _T_1392 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] - node _T_1393 = not(intpriority_reg[18]) @[el2_pic_ctl.scala 174:89] - node _T_1394 = mux(_T_1392, _T_1393, intpriority_reg[18]) @[el2_pic_ctl.scala 174:70] - intpriority_reg_inv[18] <= _T_1394 @[el2_pic_ctl.scala 174:64] - node _T_1395 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] - node _T_1396 = not(intpriority_reg[19]) @[el2_pic_ctl.scala 174:89] - node _T_1397 = mux(_T_1395, _T_1396, intpriority_reg[19]) @[el2_pic_ctl.scala 174:70] - intpriority_reg_inv[19] <= _T_1397 @[el2_pic_ctl.scala 174:64] - node _T_1398 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] - node _T_1399 = not(intpriority_reg[20]) @[el2_pic_ctl.scala 174:89] - node _T_1400 = mux(_T_1398, _T_1399, intpriority_reg[20]) @[el2_pic_ctl.scala 174:70] - intpriority_reg_inv[20] <= _T_1400 @[el2_pic_ctl.scala 174:64] - node _T_1401 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] - node _T_1402 = not(intpriority_reg[21]) @[el2_pic_ctl.scala 174:89] - node _T_1403 = mux(_T_1401, _T_1402, intpriority_reg[21]) @[el2_pic_ctl.scala 174:70] - intpriority_reg_inv[21] <= _T_1403 @[el2_pic_ctl.scala 174:64] - node _T_1404 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] - node _T_1405 = not(intpriority_reg[22]) @[el2_pic_ctl.scala 174:89] - node _T_1406 = mux(_T_1404, _T_1405, intpriority_reg[22]) @[el2_pic_ctl.scala 174:70] - intpriority_reg_inv[22] <= _T_1406 @[el2_pic_ctl.scala 174:64] - node _T_1407 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] - node _T_1408 = not(intpriority_reg[23]) @[el2_pic_ctl.scala 174:89] - node _T_1409 = mux(_T_1407, _T_1408, intpriority_reg[23]) @[el2_pic_ctl.scala 174:70] - intpriority_reg_inv[23] <= _T_1409 @[el2_pic_ctl.scala 174:64] - node _T_1410 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] - node _T_1411 = not(intpriority_reg[24]) @[el2_pic_ctl.scala 174:89] - node _T_1412 = mux(_T_1410, _T_1411, intpriority_reg[24]) @[el2_pic_ctl.scala 174:70] - intpriority_reg_inv[24] <= _T_1412 @[el2_pic_ctl.scala 174:64] - node _T_1413 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] - node _T_1414 = not(intpriority_reg[25]) @[el2_pic_ctl.scala 174:89] - node _T_1415 = mux(_T_1413, _T_1414, intpriority_reg[25]) @[el2_pic_ctl.scala 174:70] - intpriority_reg_inv[25] <= _T_1415 @[el2_pic_ctl.scala 174:64] - node _T_1416 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] - node _T_1417 = not(intpriority_reg[26]) @[el2_pic_ctl.scala 174:89] - node _T_1418 = mux(_T_1416, _T_1417, intpriority_reg[26]) @[el2_pic_ctl.scala 174:70] - intpriority_reg_inv[26] <= _T_1418 @[el2_pic_ctl.scala 174:64] - node _T_1419 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] - node _T_1420 = not(intpriority_reg[27]) @[el2_pic_ctl.scala 174:89] - node _T_1421 = mux(_T_1419, _T_1420, intpriority_reg[27]) @[el2_pic_ctl.scala 174:70] - intpriority_reg_inv[27] <= _T_1421 @[el2_pic_ctl.scala 174:64] - node _T_1422 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] - node _T_1423 = not(intpriority_reg[28]) @[el2_pic_ctl.scala 174:89] - node _T_1424 = mux(_T_1422, _T_1423, intpriority_reg[28]) @[el2_pic_ctl.scala 174:70] - intpriority_reg_inv[28] <= _T_1424 @[el2_pic_ctl.scala 174:64] - node _T_1425 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] - node _T_1426 = not(intpriority_reg[29]) @[el2_pic_ctl.scala 174:89] - node _T_1427 = mux(_T_1425, _T_1426, intpriority_reg[29]) @[el2_pic_ctl.scala 174:70] - intpriority_reg_inv[29] <= _T_1427 @[el2_pic_ctl.scala 174:64] - node _T_1428 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] - node _T_1429 = not(intpriority_reg[30]) @[el2_pic_ctl.scala 174:89] - node _T_1430 = mux(_T_1428, _T_1429, intpriority_reg[30]) @[el2_pic_ctl.scala 174:70] - intpriority_reg_inv[30] <= _T_1430 @[el2_pic_ctl.scala 174:64] - node _T_1431 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] - node _T_1432 = not(intpriority_reg[31]) @[el2_pic_ctl.scala 174:89] - node _T_1433 = mux(_T_1431, _T_1432, intpriority_reg[31]) @[el2_pic_ctl.scala 174:70] - intpriority_reg_inv[31] <= _T_1433 @[el2_pic_ctl.scala 174:64] - node _T_1434 = and(UInt<1>("h00"), intenable_reg[0]) @[el2_pic_ctl.scala 175:109] + node _T_1330 = xor(_T_1326, _T_1327) @[el2_pic_ctl.scala 37:50] + node _T_1331 = eq(_T_1329, UInt<1>("h00")) @[el2_pic_ctl.scala 37:92] + node _T_1332 = and(gw_int_pending_30, _T_1331) @[el2_pic_ctl.scala 37:90] + node gw_int_pending_in_30 = or(_T_1330, _T_1332) @[el2_pic_ctl.scala 37:72] + reg _T_1333 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 38:30] + _T_1333 <= gw_int_pending_in_30 @[el2_pic_ctl.scala 38:30] + gw_int_pending_30 <= _T_1333 @[el2_pic_ctl.scala 38:20] + node _T_1334 = bits(_T_1328, 0, 0) @[el2_pic_ctl.scala 39:30] + node _T_1335 = xor(_T_1326, _T_1327) @[el2_pic_ctl.scala 39:55] + node _T_1336 = or(_T_1335, gw_int_pending_30) @[el2_pic_ctl.scala 39:78] + node _T_1337 = xor(_T_1326, _T_1327) @[el2_pic_ctl.scala 39:117] + node extintsrc_req_gw_31 = mux(_T_1334, _T_1336, _T_1337) @[el2_pic_ctl.scala 39:8] + node _T_1338 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 166:81] + node _T_1339 = not(intpriority_reg[0]) @[el2_pic_ctl.scala 166:89] + node _T_1340 = mux(_T_1338, _T_1339, intpriority_reg[0]) @[el2_pic_ctl.scala 166:70] + intpriority_reg_inv[0] <= _T_1340 @[el2_pic_ctl.scala 166:64] + node _T_1341 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 166:81] + node _T_1342 = not(intpriority_reg[1]) @[el2_pic_ctl.scala 166:89] + node _T_1343 = mux(_T_1341, _T_1342, intpriority_reg[1]) @[el2_pic_ctl.scala 166:70] + intpriority_reg_inv[1] <= _T_1343 @[el2_pic_ctl.scala 166:64] + node _T_1344 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 166:81] + node _T_1345 = not(intpriority_reg[2]) @[el2_pic_ctl.scala 166:89] + node _T_1346 = mux(_T_1344, _T_1345, intpriority_reg[2]) @[el2_pic_ctl.scala 166:70] + intpriority_reg_inv[2] <= _T_1346 @[el2_pic_ctl.scala 166:64] + node _T_1347 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 166:81] + node _T_1348 = not(intpriority_reg[3]) @[el2_pic_ctl.scala 166:89] + node _T_1349 = mux(_T_1347, _T_1348, intpriority_reg[3]) @[el2_pic_ctl.scala 166:70] + intpriority_reg_inv[3] <= _T_1349 @[el2_pic_ctl.scala 166:64] + node _T_1350 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 166:81] + node _T_1351 = not(intpriority_reg[4]) @[el2_pic_ctl.scala 166:89] + node _T_1352 = mux(_T_1350, _T_1351, intpriority_reg[4]) @[el2_pic_ctl.scala 166:70] + intpriority_reg_inv[4] <= _T_1352 @[el2_pic_ctl.scala 166:64] + node _T_1353 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 166:81] + node _T_1354 = not(intpriority_reg[5]) @[el2_pic_ctl.scala 166:89] + node _T_1355 = mux(_T_1353, _T_1354, intpriority_reg[5]) @[el2_pic_ctl.scala 166:70] + intpriority_reg_inv[5] <= _T_1355 @[el2_pic_ctl.scala 166:64] + node _T_1356 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 166:81] + node _T_1357 = not(intpriority_reg[6]) @[el2_pic_ctl.scala 166:89] + node _T_1358 = mux(_T_1356, _T_1357, intpriority_reg[6]) @[el2_pic_ctl.scala 166:70] + intpriority_reg_inv[6] <= _T_1358 @[el2_pic_ctl.scala 166:64] + node _T_1359 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 166:81] + node _T_1360 = not(intpriority_reg[7]) @[el2_pic_ctl.scala 166:89] + node _T_1361 = mux(_T_1359, _T_1360, intpriority_reg[7]) @[el2_pic_ctl.scala 166:70] + intpriority_reg_inv[7] <= _T_1361 @[el2_pic_ctl.scala 166:64] + node _T_1362 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 166:81] + node _T_1363 = not(intpriority_reg[8]) @[el2_pic_ctl.scala 166:89] + node _T_1364 = mux(_T_1362, _T_1363, intpriority_reg[8]) @[el2_pic_ctl.scala 166:70] + intpriority_reg_inv[8] <= _T_1364 @[el2_pic_ctl.scala 166:64] + node _T_1365 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 166:81] + node _T_1366 = not(intpriority_reg[9]) @[el2_pic_ctl.scala 166:89] + node _T_1367 = mux(_T_1365, _T_1366, intpriority_reg[9]) @[el2_pic_ctl.scala 166:70] + intpriority_reg_inv[9] <= _T_1367 @[el2_pic_ctl.scala 166:64] + node _T_1368 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 166:81] + node _T_1369 = not(intpriority_reg[10]) @[el2_pic_ctl.scala 166:89] + node _T_1370 = mux(_T_1368, _T_1369, intpriority_reg[10]) @[el2_pic_ctl.scala 166:70] + intpriority_reg_inv[10] <= _T_1370 @[el2_pic_ctl.scala 166:64] + node _T_1371 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 166:81] + node _T_1372 = not(intpriority_reg[11]) @[el2_pic_ctl.scala 166:89] + node _T_1373 = mux(_T_1371, _T_1372, intpriority_reg[11]) @[el2_pic_ctl.scala 166:70] + intpriority_reg_inv[11] <= _T_1373 @[el2_pic_ctl.scala 166:64] + node _T_1374 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 166:81] + node _T_1375 = not(intpriority_reg[12]) @[el2_pic_ctl.scala 166:89] + node _T_1376 = mux(_T_1374, _T_1375, intpriority_reg[12]) @[el2_pic_ctl.scala 166:70] + intpriority_reg_inv[12] <= _T_1376 @[el2_pic_ctl.scala 166:64] + node _T_1377 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 166:81] + node _T_1378 = not(intpriority_reg[13]) @[el2_pic_ctl.scala 166:89] + node _T_1379 = mux(_T_1377, _T_1378, intpriority_reg[13]) @[el2_pic_ctl.scala 166:70] + intpriority_reg_inv[13] <= _T_1379 @[el2_pic_ctl.scala 166:64] + node _T_1380 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 166:81] + node _T_1381 = not(intpriority_reg[14]) @[el2_pic_ctl.scala 166:89] + node _T_1382 = mux(_T_1380, _T_1381, intpriority_reg[14]) @[el2_pic_ctl.scala 166:70] + intpriority_reg_inv[14] <= _T_1382 @[el2_pic_ctl.scala 166:64] + node _T_1383 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 166:81] + node _T_1384 = not(intpriority_reg[15]) @[el2_pic_ctl.scala 166:89] + node _T_1385 = mux(_T_1383, _T_1384, intpriority_reg[15]) @[el2_pic_ctl.scala 166:70] + intpriority_reg_inv[15] <= _T_1385 @[el2_pic_ctl.scala 166:64] + node _T_1386 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 166:81] + node _T_1387 = not(intpriority_reg[16]) @[el2_pic_ctl.scala 166:89] + node _T_1388 = mux(_T_1386, _T_1387, intpriority_reg[16]) @[el2_pic_ctl.scala 166:70] + intpriority_reg_inv[16] <= _T_1388 @[el2_pic_ctl.scala 166:64] + node _T_1389 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 166:81] + node _T_1390 = not(intpriority_reg[17]) @[el2_pic_ctl.scala 166:89] + node _T_1391 = mux(_T_1389, _T_1390, intpriority_reg[17]) @[el2_pic_ctl.scala 166:70] + intpriority_reg_inv[17] <= _T_1391 @[el2_pic_ctl.scala 166:64] + node _T_1392 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 166:81] + node _T_1393 = not(intpriority_reg[18]) @[el2_pic_ctl.scala 166:89] + node _T_1394 = mux(_T_1392, _T_1393, intpriority_reg[18]) @[el2_pic_ctl.scala 166:70] + intpriority_reg_inv[18] <= _T_1394 @[el2_pic_ctl.scala 166:64] + node _T_1395 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 166:81] + node _T_1396 = not(intpriority_reg[19]) @[el2_pic_ctl.scala 166:89] + node _T_1397 = mux(_T_1395, _T_1396, intpriority_reg[19]) @[el2_pic_ctl.scala 166:70] + intpriority_reg_inv[19] <= _T_1397 @[el2_pic_ctl.scala 166:64] + node _T_1398 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 166:81] + node _T_1399 = not(intpriority_reg[20]) @[el2_pic_ctl.scala 166:89] + node _T_1400 = mux(_T_1398, _T_1399, intpriority_reg[20]) @[el2_pic_ctl.scala 166:70] + intpriority_reg_inv[20] <= _T_1400 @[el2_pic_ctl.scala 166:64] + node _T_1401 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 166:81] + node _T_1402 = not(intpriority_reg[21]) @[el2_pic_ctl.scala 166:89] + node _T_1403 = mux(_T_1401, _T_1402, intpriority_reg[21]) @[el2_pic_ctl.scala 166:70] + intpriority_reg_inv[21] <= _T_1403 @[el2_pic_ctl.scala 166:64] + node _T_1404 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 166:81] + node _T_1405 = not(intpriority_reg[22]) @[el2_pic_ctl.scala 166:89] + node _T_1406 = mux(_T_1404, _T_1405, intpriority_reg[22]) @[el2_pic_ctl.scala 166:70] + intpriority_reg_inv[22] <= _T_1406 @[el2_pic_ctl.scala 166:64] + node _T_1407 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 166:81] + node _T_1408 = not(intpriority_reg[23]) @[el2_pic_ctl.scala 166:89] + node _T_1409 = mux(_T_1407, _T_1408, intpriority_reg[23]) @[el2_pic_ctl.scala 166:70] + intpriority_reg_inv[23] <= _T_1409 @[el2_pic_ctl.scala 166:64] + node _T_1410 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 166:81] + node _T_1411 = not(intpriority_reg[24]) @[el2_pic_ctl.scala 166:89] + node _T_1412 = mux(_T_1410, _T_1411, intpriority_reg[24]) @[el2_pic_ctl.scala 166:70] + intpriority_reg_inv[24] <= _T_1412 @[el2_pic_ctl.scala 166:64] + node _T_1413 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 166:81] + node _T_1414 = not(intpriority_reg[25]) @[el2_pic_ctl.scala 166:89] + node _T_1415 = mux(_T_1413, _T_1414, intpriority_reg[25]) @[el2_pic_ctl.scala 166:70] + intpriority_reg_inv[25] <= _T_1415 @[el2_pic_ctl.scala 166:64] + node _T_1416 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 166:81] + node _T_1417 = not(intpriority_reg[26]) @[el2_pic_ctl.scala 166:89] + node _T_1418 = mux(_T_1416, _T_1417, intpriority_reg[26]) @[el2_pic_ctl.scala 166:70] + intpriority_reg_inv[26] <= _T_1418 @[el2_pic_ctl.scala 166:64] + node _T_1419 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 166:81] + node _T_1420 = not(intpriority_reg[27]) @[el2_pic_ctl.scala 166:89] + node _T_1421 = mux(_T_1419, _T_1420, intpriority_reg[27]) @[el2_pic_ctl.scala 166:70] + intpriority_reg_inv[27] <= _T_1421 @[el2_pic_ctl.scala 166:64] + node _T_1422 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 166:81] + node _T_1423 = not(intpriority_reg[28]) @[el2_pic_ctl.scala 166:89] + node _T_1424 = mux(_T_1422, _T_1423, intpriority_reg[28]) @[el2_pic_ctl.scala 166:70] + intpriority_reg_inv[28] <= _T_1424 @[el2_pic_ctl.scala 166:64] + node _T_1425 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 166:81] + node _T_1426 = not(intpriority_reg[29]) @[el2_pic_ctl.scala 166:89] + node _T_1427 = mux(_T_1425, _T_1426, intpriority_reg[29]) @[el2_pic_ctl.scala 166:70] + intpriority_reg_inv[29] <= _T_1427 @[el2_pic_ctl.scala 166:64] + node _T_1428 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 166:81] + node _T_1429 = not(intpriority_reg[30]) @[el2_pic_ctl.scala 166:89] + node _T_1430 = mux(_T_1428, _T_1429, intpriority_reg[30]) @[el2_pic_ctl.scala 166:70] + intpriority_reg_inv[30] <= _T_1430 @[el2_pic_ctl.scala 166:64] + node _T_1431 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 166:81] + node _T_1432 = not(intpriority_reg[31]) @[el2_pic_ctl.scala 166:89] + node _T_1433 = mux(_T_1431, _T_1432, intpriority_reg[31]) @[el2_pic_ctl.scala 166:70] + intpriority_reg_inv[31] <= _T_1433 @[el2_pic_ctl.scala 166:64] + node _T_1434 = and(UInt<1>("h00"), intenable_reg[0]) @[el2_pic_ctl.scala 167:109] node _T_1435 = bits(_T_1434, 0, 0) @[Bitwise.scala 72:15] node _T_1436 = mux(_T_1435, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1437 = and(_T_1436, intpriority_reg_inv[0]) @[el2_pic_ctl.scala 175:129] - intpend_w_prior_en[0] <= _T_1437 @[el2_pic_ctl.scala 175:63] - node _T_1438 = and(extintsrc_req_gw_1, intenable_reg[1]) @[el2_pic_ctl.scala 175:109] + node _T_1437 = and(_T_1436, intpriority_reg_inv[0]) @[el2_pic_ctl.scala 167:129] + intpend_w_prior_en[0] <= _T_1437 @[el2_pic_ctl.scala 167:63] + node _T_1438 = and(extintsrc_req_gw_1, intenable_reg[1]) @[el2_pic_ctl.scala 167:109] node _T_1439 = bits(_T_1438, 0, 0) @[Bitwise.scala 72:15] node _T_1440 = mux(_T_1439, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1441 = and(_T_1440, intpriority_reg_inv[1]) @[el2_pic_ctl.scala 175:129] - intpend_w_prior_en[1] <= _T_1441 @[el2_pic_ctl.scala 175:63] - node _T_1442 = and(extintsrc_req_gw_2, intenable_reg[2]) @[el2_pic_ctl.scala 175:109] + node _T_1441 = and(_T_1440, intpriority_reg_inv[1]) @[el2_pic_ctl.scala 167:129] + intpend_w_prior_en[1] <= _T_1441 @[el2_pic_ctl.scala 167:63] + node _T_1442 = and(extintsrc_req_gw_2, intenable_reg[2]) @[el2_pic_ctl.scala 167:109] node _T_1443 = bits(_T_1442, 0, 0) @[Bitwise.scala 72:15] node _T_1444 = mux(_T_1443, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1445 = and(_T_1444, intpriority_reg_inv[2]) @[el2_pic_ctl.scala 175:129] - intpend_w_prior_en[2] <= _T_1445 @[el2_pic_ctl.scala 175:63] - node _T_1446 = and(extintsrc_req_gw_3, intenable_reg[3]) @[el2_pic_ctl.scala 175:109] + node _T_1445 = and(_T_1444, intpriority_reg_inv[2]) @[el2_pic_ctl.scala 167:129] + intpend_w_prior_en[2] <= _T_1445 @[el2_pic_ctl.scala 167:63] + node _T_1446 = and(extintsrc_req_gw_3, intenable_reg[3]) @[el2_pic_ctl.scala 167:109] node _T_1447 = bits(_T_1446, 0, 0) @[Bitwise.scala 72:15] node _T_1448 = mux(_T_1447, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1449 = and(_T_1448, intpriority_reg_inv[3]) @[el2_pic_ctl.scala 175:129] - intpend_w_prior_en[3] <= _T_1449 @[el2_pic_ctl.scala 175:63] - node _T_1450 = and(extintsrc_req_gw_4, intenable_reg[4]) @[el2_pic_ctl.scala 175:109] + node _T_1449 = and(_T_1448, intpriority_reg_inv[3]) @[el2_pic_ctl.scala 167:129] + intpend_w_prior_en[3] <= _T_1449 @[el2_pic_ctl.scala 167:63] + node _T_1450 = and(extintsrc_req_gw_4, intenable_reg[4]) @[el2_pic_ctl.scala 167:109] node _T_1451 = bits(_T_1450, 0, 0) @[Bitwise.scala 72:15] node _T_1452 = mux(_T_1451, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1453 = and(_T_1452, intpriority_reg_inv[4]) @[el2_pic_ctl.scala 175:129] - intpend_w_prior_en[4] <= _T_1453 @[el2_pic_ctl.scala 175:63] - node _T_1454 = and(extintsrc_req_gw_5, intenable_reg[5]) @[el2_pic_ctl.scala 175:109] + node _T_1453 = and(_T_1452, intpriority_reg_inv[4]) @[el2_pic_ctl.scala 167:129] + intpend_w_prior_en[4] <= _T_1453 @[el2_pic_ctl.scala 167:63] + node _T_1454 = and(extintsrc_req_gw_5, intenable_reg[5]) @[el2_pic_ctl.scala 167:109] node _T_1455 = bits(_T_1454, 0, 0) @[Bitwise.scala 72:15] node _T_1456 = mux(_T_1455, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1457 = and(_T_1456, intpriority_reg_inv[5]) @[el2_pic_ctl.scala 175:129] - intpend_w_prior_en[5] <= _T_1457 @[el2_pic_ctl.scala 175:63] - node _T_1458 = and(extintsrc_req_gw_6, intenable_reg[6]) @[el2_pic_ctl.scala 175:109] + node _T_1457 = and(_T_1456, intpriority_reg_inv[5]) @[el2_pic_ctl.scala 167:129] + intpend_w_prior_en[5] <= _T_1457 @[el2_pic_ctl.scala 167:63] + node _T_1458 = and(extintsrc_req_gw_6, intenable_reg[6]) @[el2_pic_ctl.scala 167:109] node _T_1459 = bits(_T_1458, 0, 0) @[Bitwise.scala 72:15] node _T_1460 = mux(_T_1459, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1461 = and(_T_1460, intpriority_reg_inv[6]) @[el2_pic_ctl.scala 175:129] - intpend_w_prior_en[6] <= _T_1461 @[el2_pic_ctl.scala 175:63] - node _T_1462 = and(extintsrc_req_gw_7, intenable_reg[7]) @[el2_pic_ctl.scala 175:109] + node _T_1461 = and(_T_1460, intpriority_reg_inv[6]) @[el2_pic_ctl.scala 167:129] + intpend_w_prior_en[6] <= _T_1461 @[el2_pic_ctl.scala 167:63] + node _T_1462 = and(extintsrc_req_gw_7, intenable_reg[7]) @[el2_pic_ctl.scala 167:109] node _T_1463 = bits(_T_1462, 0, 0) @[Bitwise.scala 72:15] node _T_1464 = mux(_T_1463, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1465 = and(_T_1464, intpriority_reg_inv[7]) @[el2_pic_ctl.scala 175:129] - intpend_w_prior_en[7] <= _T_1465 @[el2_pic_ctl.scala 175:63] - node _T_1466 = and(extintsrc_req_gw_8, intenable_reg[8]) @[el2_pic_ctl.scala 175:109] + node _T_1465 = and(_T_1464, intpriority_reg_inv[7]) @[el2_pic_ctl.scala 167:129] + intpend_w_prior_en[7] <= _T_1465 @[el2_pic_ctl.scala 167:63] + node _T_1466 = and(extintsrc_req_gw_8, intenable_reg[8]) @[el2_pic_ctl.scala 167:109] node _T_1467 = bits(_T_1466, 0, 0) @[Bitwise.scala 72:15] node _T_1468 = mux(_T_1467, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1469 = and(_T_1468, intpriority_reg_inv[8]) @[el2_pic_ctl.scala 175:129] - intpend_w_prior_en[8] <= _T_1469 @[el2_pic_ctl.scala 175:63] - node _T_1470 = and(extintsrc_req_gw_9, intenable_reg[9]) @[el2_pic_ctl.scala 175:109] + node _T_1469 = and(_T_1468, intpriority_reg_inv[8]) @[el2_pic_ctl.scala 167:129] + intpend_w_prior_en[8] <= _T_1469 @[el2_pic_ctl.scala 167:63] + node _T_1470 = and(extintsrc_req_gw_9, intenable_reg[9]) @[el2_pic_ctl.scala 167:109] node _T_1471 = bits(_T_1470, 0, 0) @[Bitwise.scala 72:15] node _T_1472 = mux(_T_1471, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1473 = and(_T_1472, intpriority_reg_inv[9]) @[el2_pic_ctl.scala 175:129] - intpend_w_prior_en[9] <= _T_1473 @[el2_pic_ctl.scala 175:63] - node _T_1474 = and(extintsrc_req_gw_10, intenable_reg[10]) @[el2_pic_ctl.scala 175:109] + node _T_1473 = and(_T_1472, intpriority_reg_inv[9]) @[el2_pic_ctl.scala 167:129] + intpend_w_prior_en[9] <= _T_1473 @[el2_pic_ctl.scala 167:63] + node _T_1474 = and(extintsrc_req_gw_10, intenable_reg[10]) @[el2_pic_ctl.scala 167:109] node _T_1475 = bits(_T_1474, 0, 0) @[Bitwise.scala 72:15] node _T_1476 = mux(_T_1475, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1477 = and(_T_1476, intpriority_reg_inv[10]) @[el2_pic_ctl.scala 175:129] - intpend_w_prior_en[10] <= _T_1477 @[el2_pic_ctl.scala 175:63] - node _T_1478 = and(extintsrc_req_gw_11, intenable_reg[11]) @[el2_pic_ctl.scala 175:109] + node _T_1477 = and(_T_1476, intpriority_reg_inv[10]) @[el2_pic_ctl.scala 167:129] + intpend_w_prior_en[10] <= _T_1477 @[el2_pic_ctl.scala 167:63] + node _T_1478 = and(extintsrc_req_gw_11, intenable_reg[11]) @[el2_pic_ctl.scala 167:109] node _T_1479 = bits(_T_1478, 0, 0) @[Bitwise.scala 72:15] node _T_1480 = mux(_T_1479, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1481 = and(_T_1480, intpriority_reg_inv[11]) @[el2_pic_ctl.scala 175:129] - intpend_w_prior_en[11] <= _T_1481 @[el2_pic_ctl.scala 175:63] - node _T_1482 = and(extintsrc_req_gw_12, intenable_reg[12]) @[el2_pic_ctl.scala 175:109] + node _T_1481 = and(_T_1480, intpriority_reg_inv[11]) @[el2_pic_ctl.scala 167:129] + intpend_w_prior_en[11] <= _T_1481 @[el2_pic_ctl.scala 167:63] + node _T_1482 = and(extintsrc_req_gw_12, intenable_reg[12]) @[el2_pic_ctl.scala 167:109] node _T_1483 = bits(_T_1482, 0, 0) @[Bitwise.scala 72:15] node _T_1484 = mux(_T_1483, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1485 = and(_T_1484, intpriority_reg_inv[12]) @[el2_pic_ctl.scala 175:129] - intpend_w_prior_en[12] <= _T_1485 @[el2_pic_ctl.scala 175:63] - node _T_1486 = and(extintsrc_req_gw_13, intenable_reg[13]) @[el2_pic_ctl.scala 175:109] + node _T_1485 = and(_T_1484, intpriority_reg_inv[12]) @[el2_pic_ctl.scala 167:129] + intpend_w_prior_en[12] <= _T_1485 @[el2_pic_ctl.scala 167:63] + node _T_1486 = and(extintsrc_req_gw_13, intenable_reg[13]) @[el2_pic_ctl.scala 167:109] node _T_1487 = bits(_T_1486, 0, 0) @[Bitwise.scala 72:15] node _T_1488 = mux(_T_1487, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1489 = and(_T_1488, intpriority_reg_inv[13]) @[el2_pic_ctl.scala 175:129] - intpend_w_prior_en[13] <= _T_1489 @[el2_pic_ctl.scala 175:63] - node _T_1490 = and(extintsrc_req_gw_14, intenable_reg[14]) @[el2_pic_ctl.scala 175:109] + node _T_1489 = and(_T_1488, intpriority_reg_inv[13]) @[el2_pic_ctl.scala 167:129] + intpend_w_prior_en[13] <= _T_1489 @[el2_pic_ctl.scala 167:63] + node _T_1490 = and(extintsrc_req_gw_14, intenable_reg[14]) @[el2_pic_ctl.scala 167:109] node _T_1491 = bits(_T_1490, 0, 0) @[Bitwise.scala 72:15] node _T_1492 = mux(_T_1491, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1493 = and(_T_1492, intpriority_reg_inv[14]) @[el2_pic_ctl.scala 175:129] - intpend_w_prior_en[14] <= _T_1493 @[el2_pic_ctl.scala 175:63] - node _T_1494 = and(extintsrc_req_gw_15, intenable_reg[15]) @[el2_pic_ctl.scala 175:109] + node _T_1493 = and(_T_1492, intpriority_reg_inv[14]) @[el2_pic_ctl.scala 167:129] + intpend_w_prior_en[14] <= _T_1493 @[el2_pic_ctl.scala 167:63] + node _T_1494 = and(extintsrc_req_gw_15, intenable_reg[15]) @[el2_pic_ctl.scala 167:109] node _T_1495 = bits(_T_1494, 0, 0) @[Bitwise.scala 72:15] node _T_1496 = mux(_T_1495, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1497 = and(_T_1496, intpriority_reg_inv[15]) @[el2_pic_ctl.scala 175:129] - intpend_w_prior_en[15] <= _T_1497 @[el2_pic_ctl.scala 175:63] - node _T_1498 = and(extintsrc_req_gw_16, intenable_reg[16]) @[el2_pic_ctl.scala 175:109] + node _T_1497 = and(_T_1496, intpriority_reg_inv[15]) @[el2_pic_ctl.scala 167:129] + intpend_w_prior_en[15] <= _T_1497 @[el2_pic_ctl.scala 167:63] + node _T_1498 = and(extintsrc_req_gw_16, intenable_reg[16]) @[el2_pic_ctl.scala 167:109] node _T_1499 = bits(_T_1498, 0, 0) @[Bitwise.scala 72:15] node _T_1500 = mux(_T_1499, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1501 = and(_T_1500, intpriority_reg_inv[16]) @[el2_pic_ctl.scala 175:129] - intpend_w_prior_en[16] <= _T_1501 @[el2_pic_ctl.scala 175:63] - node _T_1502 = and(extintsrc_req_gw_17, intenable_reg[17]) @[el2_pic_ctl.scala 175:109] + node _T_1501 = and(_T_1500, intpriority_reg_inv[16]) @[el2_pic_ctl.scala 167:129] + intpend_w_prior_en[16] <= _T_1501 @[el2_pic_ctl.scala 167:63] + node _T_1502 = and(extintsrc_req_gw_17, intenable_reg[17]) @[el2_pic_ctl.scala 167:109] node _T_1503 = bits(_T_1502, 0, 0) @[Bitwise.scala 72:15] node _T_1504 = mux(_T_1503, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1505 = and(_T_1504, intpriority_reg_inv[17]) @[el2_pic_ctl.scala 175:129] - intpend_w_prior_en[17] <= _T_1505 @[el2_pic_ctl.scala 175:63] - node _T_1506 = and(extintsrc_req_gw_18, intenable_reg[18]) @[el2_pic_ctl.scala 175:109] + node _T_1505 = and(_T_1504, intpriority_reg_inv[17]) @[el2_pic_ctl.scala 167:129] + intpend_w_prior_en[17] <= _T_1505 @[el2_pic_ctl.scala 167:63] + node _T_1506 = and(extintsrc_req_gw_18, intenable_reg[18]) @[el2_pic_ctl.scala 167:109] node _T_1507 = bits(_T_1506, 0, 0) @[Bitwise.scala 72:15] node _T_1508 = mux(_T_1507, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1509 = and(_T_1508, intpriority_reg_inv[18]) @[el2_pic_ctl.scala 175:129] - intpend_w_prior_en[18] <= _T_1509 @[el2_pic_ctl.scala 175:63] - node _T_1510 = and(extintsrc_req_gw_19, intenable_reg[19]) @[el2_pic_ctl.scala 175:109] + node _T_1509 = and(_T_1508, intpriority_reg_inv[18]) @[el2_pic_ctl.scala 167:129] + intpend_w_prior_en[18] <= _T_1509 @[el2_pic_ctl.scala 167:63] + node _T_1510 = and(extintsrc_req_gw_19, intenable_reg[19]) @[el2_pic_ctl.scala 167:109] node _T_1511 = bits(_T_1510, 0, 0) @[Bitwise.scala 72:15] node _T_1512 = mux(_T_1511, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1513 = and(_T_1512, intpriority_reg_inv[19]) @[el2_pic_ctl.scala 175:129] - intpend_w_prior_en[19] <= _T_1513 @[el2_pic_ctl.scala 175:63] - node _T_1514 = and(extintsrc_req_gw_20, intenable_reg[20]) @[el2_pic_ctl.scala 175:109] + node _T_1513 = and(_T_1512, intpriority_reg_inv[19]) @[el2_pic_ctl.scala 167:129] + intpend_w_prior_en[19] <= _T_1513 @[el2_pic_ctl.scala 167:63] + node _T_1514 = and(extintsrc_req_gw_20, intenable_reg[20]) @[el2_pic_ctl.scala 167:109] node _T_1515 = bits(_T_1514, 0, 0) @[Bitwise.scala 72:15] node _T_1516 = mux(_T_1515, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1517 = and(_T_1516, intpriority_reg_inv[20]) @[el2_pic_ctl.scala 175:129] - intpend_w_prior_en[20] <= _T_1517 @[el2_pic_ctl.scala 175:63] - node _T_1518 = and(extintsrc_req_gw_21, intenable_reg[21]) @[el2_pic_ctl.scala 175:109] + node _T_1517 = and(_T_1516, intpriority_reg_inv[20]) @[el2_pic_ctl.scala 167:129] + intpend_w_prior_en[20] <= _T_1517 @[el2_pic_ctl.scala 167:63] + node _T_1518 = and(extintsrc_req_gw_21, intenable_reg[21]) @[el2_pic_ctl.scala 167:109] node _T_1519 = bits(_T_1518, 0, 0) @[Bitwise.scala 72:15] node _T_1520 = mux(_T_1519, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1521 = and(_T_1520, intpriority_reg_inv[21]) @[el2_pic_ctl.scala 175:129] - intpend_w_prior_en[21] <= _T_1521 @[el2_pic_ctl.scala 175:63] - node _T_1522 = and(extintsrc_req_gw_22, intenable_reg[22]) @[el2_pic_ctl.scala 175:109] + node _T_1521 = and(_T_1520, intpriority_reg_inv[21]) @[el2_pic_ctl.scala 167:129] + intpend_w_prior_en[21] <= _T_1521 @[el2_pic_ctl.scala 167:63] + node _T_1522 = and(extintsrc_req_gw_22, intenable_reg[22]) @[el2_pic_ctl.scala 167:109] node _T_1523 = bits(_T_1522, 0, 0) @[Bitwise.scala 72:15] node _T_1524 = mux(_T_1523, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1525 = and(_T_1524, intpriority_reg_inv[22]) @[el2_pic_ctl.scala 175:129] - intpend_w_prior_en[22] <= _T_1525 @[el2_pic_ctl.scala 175:63] - node _T_1526 = and(extintsrc_req_gw_23, intenable_reg[23]) @[el2_pic_ctl.scala 175:109] + node _T_1525 = and(_T_1524, intpriority_reg_inv[22]) @[el2_pic_ctl.scala 167:129] + intpend_w_prior_en[22] <= _T_1525 @[el2_pic_ctl.scala 167:63] + node _T_1526 = and(extintsrc_req_gw_23, intenable_reg[23]) @[el2_pic_ctl.scala 167:109] node _T_1527 = bits(_T_1526, 0, 0) @[Bitwise.scala 72:15] node _T_1528 = mux(_T_1527, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1529 = and(_T_1528, intpriority_reg_inv[23]) @[el2_pic_ctl.scala 175:129] - intpend_w_prior_en[23] <= _T_1529 @[el2_pic_ctl.scala 175:63] - node _T_1530 = and(extintsrc_req_gw_24, intenable_reg[24]) @[el2_pic_ctl.scala 175:109] + node _T_1529 = and(_T_1528, intpriority_reg_inv[23]) @[el2_pic_ctl.scala 167:129] + intpend_w_prior_en[23] <= _T_1529 @[el2_pic_ctl.scala 167:63] + node _T_1530 = and(extintsrc_req_gw_24, intenable_reg[24]) @[el2_pic_ctl.scala 167:109] node _T_1531 = bits(_T_1530, 0, 0) @[Bitwise.scala 72:15] node _T_1532 = mux(_T_1531, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1533 = and(_T_1532, intpriority_reg_inv[24]) @[el2_pic_ctl.scala 175:129] - intpend_w_prior_en[24] <= _T_1533 @[el2_pic_ctl.scala 175:63] - node _T_1534 = and(extintsrc_req_gw_25, intenable_reg[25]) @[el2_pic_ctl.scala 175:109] + node _T_1533 = and(_T_1532, intpriority_reg_inv[24]) @[el2_pic_ctl.scala 167:129] + intpend_w_prior_en[24] <= _T_1533 @[el2_pic_ctl.scala 167:63] + node _T_1534 = and(extintsrc_req_gw_25, intenable_reg[25]) @[el2_pic_ctl.scala 167:109] node _T_1535 = bits(_T_1534, 0, 0) @[Bitwise.scala 72:15] node _T_1536 = mux(_T_1535, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1537 = and(_T_1536, intpriority_reg_inv[25]) @[el2_pic_ctl.scala 175:129] - intpend_w_prior_en[25] <= _T_1537 @[el2_pic_ctl.scala 175:63] - node _T_1538 = and(extintsrc_req_gw_26, intenable_reg[26]) @[el2_pic_ctl.scala 175:109] + node _T_1537 = and(_T_1536, intpriority_reg_inv[25]) @[el2_pic_ctl.scala 167:129] + intpend_w_prior_en[25] <= _T_1537 @[el2_pic_ctl.scala 167:63] + node _T_1538 = and(extintsrc_req_gw_26, intenable_reg[26]) @[el2_pic_ctl.scala 167:109] node _T_1539 = bits(_T_1538, 0, 0) @[Bitwise.scala 72:15] node _T_1540 = mux(_T_1539, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1541 = and(_T_1540, intpriority_reg_inv[26]) @[el2_pic_ctl.scala 175:129] - intpend_w_prior_en[26] <= _T_1541 @[el2_pic_ctl.scala 175:63] - node _T_1542 = and(extintsrc_req_gw_27, intenable_reg[27]) @[el2_pic_ctl.scala 175:109] + node _T_1541 = and(_T_1540, intpriority_reg_inv[26]) @[el2_pic_ctl.scala 167:129] + intpend_w_prior_en[26] <= _T_1541 @[el2_pic_ctl.scala 167:63] + node _T_1542 = and(extintsrc_req_gw_27, intenable_reg[27]) @[el2_pic_ctl.scala 167:109] node _T_1543 = bits(_T_1542, 0, 0) @[Bitwise.scala 72:15] node _T_1544 = mux(_T_1543, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1545 = and(_T_1544, intpriority_reg_inv[27]) @[el2_pic_ctl.scala 175:129] - intpend_w_prior_en[27] <= _T_1545 @[el2_pic_ctl.scala 175:63] - node _T_1546 = and(extintsrc_req_gw_28, intenable_reg[28]) @[el2_pic_ctl.scala 175:109] + node _T_1545 = and(_T_1544, intpriority_reg_inv[27]) @[el2_pic_ctl.scala 167:129] + intpend_w_prior_en[27] <= _T_1545 @[el2_pic_ctl.scala 167:63] + node _T_1546 = and(extintsrc_req_gw_28, intenable_reg[28]) @[el2_pic_ctl.scala 167:109] node _T_1547 = bits(_T_1546, 0, 0) @[Bitwise.scala 72:15] node _T_1548 = mux(_T_1547, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1549 = and(_T_1548, intpriority_reg_inv[28]) @[el2_pic_ctl.scala 175:129] - intpend_w_prior_en[28] <= _T_1549 @[el2_pic_ctl.scala 175:63] - node _T_1550 = and(extintsrc_req_gw_29, intenable_reg[29]) @[el2_pic_ctl.scala 175:109] + node _T_1549 = and(_T_1548, intpriority_reg_inv[28]) @[el2_pic_ctl.scala 167:129] + intpend_w_prior_en[28] <= _T_1549 @[el2_pic_ctl.scala 167:63] + node _T_1550 = and(extintsrc_req_gw_29, intenable_reg[29]) @[el2_pic_ctl.scala 167:109] node _T_1551 = bits(_T_1550, 0, 0) @[Bitwise.scala 72:15] node _T_1552 = mux(_T_1551, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1553 = and(_T_1552, intpriority_reg_inv[29]) @[el2_pic_ctl.scala 175:129] - intpend_w_prior_en[29] <= _T_1553 @[el2_pic_ctl.scala 175:63] - node _T_1554 = and(extintsrc_req_gw_30, intenable_reg[30]) @[el2_pic_ctl.scala 175:109] + node _T_1553 = and(_T_1552, intpriority_reg_inv[29]) @[el2_pic_ctl.scala 167:129] + intpend_w_prior_en[29] <= _T_1553 @[el2_pic_ctl.scala 167:63] + node _T_1554 = and(extintsrc_req_gw_30, intenable_reg[30]) @[el2_pic_ctl.scala 167:109] node _T_1555 = bits(_T_1554, 0, 0) @[Bitwise.scala 72:15] node _T_1556 = mux(_T_1555, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1557 = and(_T_1556, intpriority_reg_inv[30]) @[el2_pic_ctl.scala 175:129] - intpend_w_prior_en[30] <= _T_1557 @[el2_pic_ctl.scala 175:63] - node _T_1558 = and(extintsrc_req_gw_31, intenable_reg[31]) @[el2_pic_ctl.scala 175:109] + node _T_1557 = and(_T_1556, intpriority_reg_inv[30]) @[el2_pic_ctl.scala 167:129] + intpend_w_prior_en[30] <= _T_1557 @[el2_pic_ctl.scala 167:63] + node _T_1558 = and(extintsrc_req_gw_31, intenable_reg[31]) @[el2_pic_ctl.scala 167:109] node _T_1559 = bits(_T_1558, 0, 0) @[Bitwise.scala 72:15] node _T_1560 = mux(_T_1559, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1561 = and(_T_1560, intpriority_reg_inv[31]) @[el2_pic_ctl.scala 175:129] - intpend_w_prior_en[31] <= _T_1561 @[el2_pic_ctl.scala 175:63] - intpend_id[0] <= UInt<1>("h00") @[el2_pic_ctl.scala 176:55] - intpend_id[1] <= UInt<1>("h01") @[el2_pic_ctl.scala 176:55] - intpend_id[2] <= UInt<2>("h02") @[el2_pic_ctl.scala 176:55] - intpend_id[3] <= UInt<2>("h03") @[el2_pic_ctl.scala 176:55] - intpend_id[4] <= UInt<3>("h04") @[el2_pic_ctl.scala 176:55] - intpend_id[5] <= UInt<3>("h05") @[el2_pic_ctl.scala 176:55] - intpend_id[6] <= UInt<3>("h06") @[el2_pic_ctl.scala 176:55] - intpend_id[7] <= UInt<3>("h07") @[el2_pic_ctl.scala 176:55] - intpend_id[8] <= UInt<4>("h08") @[el2_pic_ctl.scala 176:55] - intpend_id[9] <= UInt<4>("h09") @[el2_pic_ctl.scala 176:55] - intpend_id[10] <= UInt<4>("h0a") @[el2_pic_ctl.scala 176:55] - intpend_id[11] <= UInt<4>("h0b") @[el2_pic_ctl.scala 176:55] - intpend_id[12] <= UInt<4>("h0c") @[el2_pic_ctl.scala 176:55] - intpend_id[13] <= UInt<4>("h0d") @[el2_pic_ctl.scala 176:55] - intpend_id[14] <= UInt<4>("h0e") @[el2_pic_ctl.scala 176:55] - intpend_id[15] <= UInt<4>("h0f") @[el2_pic_ctl.scala 176:55] - intpend_id[16] <= UInt<5>("h010") @[el2_pic_ctl.scala 176:55] - intpend_id[17] <= UInt<5>("h011") @[el2_pic_ctl.scala 176:55] - intpend_id[18] <= UInt<5>("h012") @[el2_pic_ctl.scala 176:55] - intpend_id[19] <= UInt<5>("h013") @[el2_pic_ctl.scala 176:55] - intpend_id[20] <= UInt<5>("h014") @[el2_pic_ctl.scala 176:55] - intpend_id[21] <= UInt<5>("h015") @[el2_pic_ctl.scala 176:55] - intpend_id[22] <= UInt<5>("h016") @[el2_pic_ctl.scala 176:55] - intpend_id[23] <= UInt<5>("h017") @[el2_pic_ctl.scala 176:55] - intpend_id[24] <= UInt<5>("h018") @[el2_pic_ctl.scala 176:55] - intpend_id[25] <= UInt<5>("h019") @[el2_pic_ctl.scala 176:55] - intpend_id[26] <= UInt<5>("h01a") @[el2_pic_ctl.scala 176:55] - intpend_id[27] <= UInt<5>("h01b") @[el2_pic_ctl.scala 176:55] - intpend_id[28] <= UInt<5>("h01c") @[el2_pic_ctl.scala 176:55] - intpend_id[29] <= UInt<5>("h01d") @[el2_pic_ctl.scala 176:55] - intpend_id[30] <= UInt<5>("h01e") @[el2_pic_ctl.scala 176:55] - intpend_id[31] <= UInt<5>("h01f") @[el2_pic_ctl.scala 176:55] - wire level_intpend_w_prior_en : UInt<4>[34][6] @[el2_pic_ctl.scala 227:40] - wire level_intpend_id : UInt<8>[34][6] @[el2_pic_ctl.scala 228:32] - level_intpend_w_prior_en[0][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[0][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[0][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[0][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[0][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[0][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[0][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[0][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[0][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[0][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[0][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[0][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[0][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[0][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[0][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[0][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[0][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[0][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[0][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[0][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[0][10] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[0][10] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[0][11] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[0][11] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[0][12] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[0][12] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[0][13] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[0][13] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[0][14] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[0][14] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[0][15] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[0][15] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[0][16] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[0][16] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[0][17] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[0][17] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[0][18] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[0][18] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[0][19] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[0][19] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[0][20] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[0][20] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[0][21] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[0][21] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[0][22] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[0][22] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[0][23] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[0][23] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[0][24] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[0][24] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[0][25] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[0][25] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[0][26] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[0][26] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[0][27] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[0][27] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[0][28] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[0][28] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[0][29] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[0][29] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[0][30] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[0][30] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[0][31] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[0][31] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[0][32] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[0][32] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[0][33] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[0][33] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[1][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[1][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[1][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[1][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[1][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[1][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[1][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[1][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[1][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[1][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[1][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[1][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[1][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[1][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[1][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[1][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[1][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[1][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[1][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[1][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[1][10] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[1][10] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[1][11] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[1][11] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[1][12] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[1][12] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[1][13] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[1][13] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[1][14] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[1][14] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[1][15] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[1][15] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[1][16] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[1][16] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[1][17] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[1][17] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[1][18] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[1][18] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[1][19] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[1][19] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[1][20] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[1][20] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[1][21] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[1][21] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[1][22] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[1][22] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[1][23] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[1][23] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[1][24] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[1][24] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[1][25] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[1][25] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[1][26] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[1][26] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[1][27] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[1][27] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[1][28] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[1][28] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[1][29] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[1][29] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[1][30] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[1][30] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[1][31] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[1][31] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[1][32] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[1][32] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[1][33] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[1][33] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[2][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[2][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[2][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[2][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[2][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[2][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[2][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[2][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[2][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[2][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[2][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[2][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[2][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[2][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[2][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[2][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[2][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[2][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[2][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[2][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[2][10] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[2][10] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[2][11] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[2][11] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[2][12] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[2][12] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[2][13] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[2][13] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[2][14] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[2][14] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[2][15] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[2][15] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[2][16] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[2][16] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[2][17] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[2][17] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[2][18] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[2][18] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[2][19] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[2][19] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[2][20] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[2][20] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[2][21] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[2][21] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[2][22] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[2][22] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[2][23] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[2][23] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[2][24] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[2][24] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[2][25] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[2][25] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[2][26] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[2][26] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[2][27] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[2][27] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[2][28] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[2][28] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[2][29] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[2][29] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[2][30] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[2][30] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[2][31] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[2][31] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[2][32] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[2][32] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[2][33] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[2][33] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[3][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[3][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[3][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[3][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[3][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[3][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[3][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[3][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[3][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[3][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[3][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[3][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[3][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[3][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[3][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[3][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[3][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[3][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[3][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[3][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[3][10] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[3][10] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[3][11] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[3][11] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[3][12] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[3][12] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[3][13] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[3][13] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[3][14] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[3][14] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[3][15] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[3][15] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[3][16] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[3][16] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[3][17] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[3][17] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[3][18] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[3][18] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[3][19] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[3][19] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[3][20] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[3][20] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[3][21] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[3][21] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[3][22] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[3][22] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[3][23] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[3][23] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[3][24] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[3][24] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[3][25] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[3][25] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[3][26] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[3][26] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[3][27] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[3][27] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[3][28] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[3][28] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[3][29] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[3][29] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[3][30] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[3][30] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[3][31] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[3][31] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[3][32] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[3][32] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[3][33] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[3][33] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[4][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[4][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[4][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[4][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[4][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[4][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[4][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[4][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[4][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[4][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[4][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[4][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[4][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[4][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[4][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[4][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[4][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[4][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[4][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[4][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[4][10] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[4][10] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[4][11] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[4][11] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[4][12] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[4][12] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[4][13] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[4][13] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[4][14] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[4][14] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[4][15] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[4][15] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[4][16] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[4][16] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[4][17] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[4][17] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[4][18] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[4][18] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[4][19] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[4][19] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[4][20] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[4][20] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[4][21] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[4][21] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[4][22] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[4][22] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[4][23] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[4][23] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[4][24] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[4][24] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[4][25] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[4][25] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[4][26] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[4][26] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[4][27] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[4][27] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[4][28] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[4][28] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[4][29] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[4][29] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[4][30] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[4][30] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[4][31] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[4][31] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[4][32] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[4][32] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[4][33] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[4][33] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[5][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[5][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[5][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[5][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[5][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[5][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[5][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[5][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[5][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[5][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[5][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[5][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[5][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[5][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[5][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[5][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[5][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[5][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[5][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[5][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[5][10] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[5][10] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[5][11] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[5][11] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[5][12] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[5][12] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[5][13] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[5][13] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[5][14] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[5][14] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[5][15] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[5][15] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[5][16] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[5][16] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[5][17] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[5][17] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[5][18] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[5][18] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[5][19] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[5][19] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[5][20] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[5][20] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[5][21] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[5][21] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[5][22] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[5][22] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[5][23] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[5][23] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[5][24] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[5][24] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[5][25] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[5][25] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[5][26] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[5][26] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[5][27] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[5][27] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[5][28] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[5][28] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[5][29] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[5][29] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[5][30] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[5][30] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[5][31] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[5][31] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[5][32] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[5][32] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] - level_intpend_w_prior_en[5][33] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] - level_intpend_id[5][33] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + node _T_1561 = and(_T_1560, intpriority_reg_inv[31]) @[el2_pic_ctl.scala 167:129] + intpend_w_prior_en[31] <= _T_1561 @[el2_pic_ctl.scala 167:63] + intpend_id[0] <= UInt<1>("h00") @[el2_pic_ctl.scala 168:55] + intpend_id[1] <= UInt<1>("h01") @[el2_pic_ctl.scala 168:55] + intpend_id[2] <= UInt<2>("h02") @[el2_pic_ctl.scala 168:55] + intpend_id[3] <= UInt<2>("h03") @[el2_pic_ctl.scala 168:55] + intpend_id[4] <= UInt<3>("h04") @[el2_pic_ctl.scala 168:55] + intpend_id[5] <= UInt<3>("h05") @[el2_pic_ctl.scala 168:55] + intpend_id[6] <= UInt<3>("h06") @[el2_pic_ctl.scala 168:55] + intpend_id[7] <= UInt<3>("h07") @[el2_pic_ctl.scala 168:55] + intpend_id[8] <= UInt<4>("h08") @[el2_pic_ctl.scala 168:55] + intpend_id[9] <= UInt<4>("h09") @[el2_pic_ctl.scala 168:55] + intpend_id[10] <= UInt<4>("h0a") @[el2_pic_ctl.scala 168:55] + intpend_id[11] <= UInt<4>("h0b") @[el2_pic_ctl.scala 168:55] + intpend_id[12] <= UInt<4>("h0c") @[el2_pic_ctl.scala 168:55] + intpend_id[13] <= UInt<4>("h0d") @[el2_pic_ctl.scala 168:55] + intpend_id[14] <= UInt<4>("h0e") @[el2_pic_ctl.scala 168:55] + intpend_id[15] <= UInt<4>("h0f") @[el2_pic_ctl.scala 168:55] + intpend_id[16] <= UInt<5>("h010") @[el2_pic_ctl.scala 168:55] + intpend_id[17] <= UInt<5>("h011") @[el2_pic_ctl.scala 168:55] + intpend_id[18] <= UInt<5>("h012") @[el2_pic_ctl.scala 168:55] + intpend_id[19] <= UInt<5>("h013") @[el2_pic_ctl.scala 168:55] + intpend_id[20] <= UInt<5>("h014") @[el2_pic_ctl.scala 168:55] + intpend_id[21] <= UInt<5>("h015") @[el2_pic_ctl.scala 168:55] + intpend_id[22] <= UInt<5>("h016") @[el2_pic_ctl.scala 168:55] + intpend_id[23] <= UInt<5>("h017") @[el2_pic_ctl.scala 168:55] + intpend_id[24] <= UInt<5>("h018") @[el2_pic_ctl.scala 168:55] + intpend_id[25] <= UInt<5>("h019") @[el2_pic_ctl.scala 168:55] + intpend_id[26] <= UInt<5>("h01a") @[el2_pic_ctl.scala 168:55] + intpend_id[27] <= UInt<5>("h01b") @[el2_pic_ctl.scala 168:55] + intpend_id[28] <= UInt<5>("h01c") @[el2_pic_ctl.scala 168:55] + intpend_id[29] <= UInt<5>("h01d") @[el2_pic_ctl.scala 168:55] + intpend_id[30] <= UInt<5>("h01e") @[el2_pic_ctl.scala 168:55] + intpend_id[31] <= UInt<5>("h01f") @[el2_pic_ctl.scala 168:55] + wire level_intpend_w_prior_en : UInt<4>[34][6] @[el2_pic_ctl.scala 219:40] + wire level_intpend_id : UInt<8>[34][6] @[el2_pic_ctl.scala 220:32] + level_intpend_w_prior_en[0][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[0][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[0][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[0][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[0][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[0][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[0][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[0][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[0][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[0][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[0][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[0][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[0][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[0][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[0][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[0][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[0][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[0][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[0][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[0][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[0][10] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[0][10] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[0][11] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[0][11] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[0][12] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[0][12] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[0][13] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[0][13] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[0][14] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[0][14] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[0][15] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[0][15] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[0][16] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[0][16] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[0][17] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[0][17] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[0][18] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[0][18] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[0][19] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[0][19] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[0][20] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[0][20] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[0][21] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[0][21] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[0][22] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[0][22] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[0][23] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[0][23] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[0][24] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[0][24] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[0][25] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[0][25] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[0][26] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[0][26] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[0][27] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[0][27] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[0][28] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[0][28] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[0][29] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[0][29] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[0][30] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[0][30] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[0][31] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[0][31] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[0][32] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[0][32] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[0][33] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[0][33] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[1][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[1][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[1][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[1][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[1][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[1][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[1][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[1][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[1][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[1][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[1][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[1][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[1][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[1][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[1][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[1][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[1][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[1][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[1][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[1][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[1][10] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[1][10] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[1][11] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[1][11] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[1][12] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[1][12] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[1][13] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[1][13] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[1][14] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[1][14] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[1][15] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[1][15] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[1][16] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[1][16] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[1][17] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[1][17] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[1][18] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[1][18] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[1][19] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[1][19] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[1][20] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[1][20] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[1][21] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[1][21] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[1][22] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[1][22] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[1][23] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[1][23] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[1][24] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[1][24] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[1][25] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[1][25] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[1][26] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[1][26] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[1][27] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[1][27] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[1][28] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[1][28] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[1][29] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[1][29] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[1][30] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[1][30] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[1][31] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[1][31] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[1][32] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[1][32] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[1][33] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[1][33] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[2][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[2][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[2][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[2][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[2][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[2][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[2][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[2][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[2][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[2][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[2][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[2][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[2][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[2][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[2][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[2][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[2][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[2][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[2][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[2][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[2][10] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[2][10] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[2][11] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[2][11] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[2][12] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[2][12] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[2][13] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[2][13] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[2][14] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[2][14] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[2][15] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[2][15] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[2][16] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[2][16] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[2][17] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[2][17] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[2][18] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[2][18] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[2][19] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[2][19] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[2][20] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[2][20] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[2][21] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[2][21] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[2][22] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[2][22] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[2][23] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[2][23] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[2][24] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[2][24] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[2][25] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[2][25] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[2][26] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[2][26] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[2][27] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[2][27] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[2][28] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[2][28] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[2][29] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[2][29] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[2][30] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[2][30] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[2][31] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[2][31] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[2][32] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[2][32] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[2][33] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[2][33] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[3][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[3][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[3][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[3][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[3][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[3][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[3][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[3][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[3][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[3][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[3][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[3][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[3][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[3][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[3][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[3][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[3][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[3][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[3][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[3][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[3][10] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[3][10] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[3][11] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[3][11] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[3][12] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[3][12] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[3][13] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[3][13] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[3][14] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[3][14] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[3][15] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[3][15] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[3][16] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[3][16] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[3][17] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[3][17] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[3][18] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[3][18] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[3][19] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[3][19] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[3][20] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[3][20] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[3][21] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[3][21] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[3][22] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[3][22] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[3][23] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[3][23] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[3][24] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[3][24] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[3][25] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[3][25] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[3][26] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[3][26] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[3][27] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[3][27] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[3][28] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[3][28] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[3][29] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[3][29] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[3][30] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[3][30] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[3][31] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[3][31] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[3][32] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[3][32] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[3][33] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[3][33] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[4][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[4][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[4][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[4][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[4][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[4][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[4][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[4][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[4][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[4][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[4][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[4][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[4][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[4][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[4][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[4][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[4][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[4][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[4][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[4][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[4][10] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[4][10] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[4][11] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[4][11] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[4][12] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[4][12] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[4][13] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[4][13] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[4][14] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[4][14] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[4][15] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[4][15] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[4][16] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[4][16] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[4][17] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[4][17] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[4][18] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[4][18] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[4][19] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[4][19] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[4][20] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[4][20] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[4][21] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[4][21] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[4][22] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[4][22] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[4][23] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[4][23] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[4][24] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[4][24] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[4][25] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[4][25] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[4][26] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[4][26] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[4][27] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[4][27] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[4][28] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[4][28] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[4][29] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[4][29] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[4][30] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[4][30] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[4][31] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[4][31] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[4][32] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[4][32] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[4][33] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[4][33] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[5][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[5][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[5][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[5][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[5][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[5][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[5][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[5][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[5][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[5][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[5][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[5][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[5][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[5][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[5][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[5][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[5][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[5][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[5][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[5][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[5][10] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[5][10] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[5][11] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[5][11] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[5][12] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[5][12] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[5][13] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[5][13] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[5][14] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[5][14] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[5][15] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[5][15] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[5][16] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[5][16] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[5][17] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[5][17] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[5][18] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[5][18] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[5][19] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[5][19] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[5][20] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[5][20] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[5][21] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[5][21] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[5][22] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[5][22] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[5][23] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[5][23] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[5][24] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[5][24] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[5][25] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[5][25] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[5][26] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[5][26] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[5][27] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[5][27] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[5][28] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[5][28] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[5][29] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[5][29] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[5][30] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[5][30] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[5][31] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[5][31] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[5][32] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[5][32] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] + level_intpend_w_prior_en[5][33] <= UInt<1>("h00") @[el2_pic_ctl.scala 223:38] + level_intpend_id[5][33] <= UInt<1>("h00") @[el2_pic_ctl.scala 224:30] node _T_1562 = mux(UInt<1>("h00"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] node _T_1563 = mux(UInt<1>("h00"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - level_intpend_w_prior_en[0][0] <= intpend_w_prior_en[0] @[el2_pic_ctl.scala 234:33] - level_intpend_w_prior_en[0][1] <= intpend_w_prior_en[1] @[el2_pic_ctl.scala 234:33] - level_intpend_w_prior_en[0][2] <= intpend_w_prior_en[2] @[el2_pic_ctl.scala 234:33] - level_intpend_w_prior_en[0][3] <= intpend_w_prior_en[3] @[el2_pic_ctl.scala 234:33] - level_intpend_w_prior_en[0][4] <= intpend_w_prior_en[4] @[el2_pic_ctl.scala 234:33] - level_intpend_w_prior_en[0][5] <= intpend_w_prior_en[5] @[el2_pic_ctl.scala 234:33] - level_intpend_w_prior_en[0][6] <= intpend_w_prior_en[6] @[el2_pic_ctl.scala 234:33] - level_intpend_w_prior_en[0][7] <= intpend_w_prior_en[7] @[el2_pic_ctl.scala 234:33] - level_intpend_w_prior_en[0][8] <= intpend_w_prior_en[8] @[el2_pic_ctl.scala 234:33] - level_intpend_w_prior_en[0][9] <= intpend_w_prior_en[9] @[el2_pic_ctl.scala 234:33] - level_intpend_w_prior_en[0][10] <= intpend_w_prior_en[10] @[el2_pic_ctl.scala 234:33] - level_intpend_w_prior_en[0][11] <= intpend_w_prior_en[11] @[el2_pic_ctl.scala 234:33] - level_intpend_w_prior_en[0][12] <= intpend_w_prior_en[12] @[el2_pic_ctl.scala 234:33] - level_intpend_w_prior_en[0][13] <= intpend_w_prior_en[13] @[el2_pic_ctl.scala 234:33] - level_intpend_w_prior_en[0][14] <= intpend_w_prior_en[14] @[el2_pic_ctl.scala 234:33] - level_intpend_w_prior_en[0][15] <= intpend_w_prior_en[15] @[el2_pic_ctl.scala 234:33] - level_intpend_w_prior_en[0][16] <= intpend_w_prior_en[16] @[el2_pic_ctl.scala 234:33] - level_intpend_w_prior_en[0][17] <= intpend_w_prior_en[17] @[el2_pic_ctl.scala 234:33] - level_intpend_w_prior_en[0][18] <= intpend_w_prior_en[18] @[el2_pic_ctl.scala 234:33] - level_intpend_w_prior_en[0][19] <= intpend_w_prior_en[19] @[el2_pic_ctl.scala 234:33] - level_intpend_w_prior_en[0][20] <= intpend_w_prior_en[20] @[el2_pic_ctl.scala 234:33] - level_intpend_w_prior_en[0][21] <= intpend_w_prior_en[21] @[el2_pic_ctl.scala 234:33] - level_intpend_w_prior_en[0][22] <= intpend_w_prior_en[22] @[el2_pic_ctl.scala 234:33] - level_intpend_w_prior_en[0][23] <= intpend_w_prior_en[23] @[el2_pic_ctl.scala 234:33] - level_intpend_w_prior_en[0][24] <= intpend_w_prior_en[24] @[el2_pic_ctl.scala 234:33] - level_intpend_w_prior_en[0][25] <= intpend_w_prior_en[25] @[el2_pic_ctl.scala 234:33] - level_intpend_w_prior_en[0][26] <= intpend_w_prior_en[26] @[el2_pic_ctl.scala 234:33] - level_intpend_w_prior_en[0][27] <= intpend_w_prior_en[27] @[el2_pic_ctl.scala 234:33] - level_intpend_w_prior_en[0][28] <= intpend_w_prior_en[28] @[el2_pic_ctl.scala 234:33] - level_intpend_w_prior_en[0][29] <= intpend_w_prior_en[29] @[el2_pic_ctl.scala 234:33] - level_intpend_w_prior_en[0][30] <= intpend_w_prior_en[30] @[el2_pic_ctl.scala 234:33] - level_intpend_w_prior_en[0][31] <= intpend_w_prior_en[31] @[el2_pic_ctl.scala 234:33] - level_intpend_w_prior_en[0][32] <= _T_1562 @[el2_pic_ctl.scala 234:33] - level_intpend_w_prior_en[0][33] <= _T_1563 @[el2_pic_ctl.scala 234:33] + level_intpend_w_prior_en[0][0] <= intpend_w_prior_en[0] @[el2_pic_ctl.scala 226:33] + level_intpend_w_prior_en[0][1] <= intpend_w_prior_en[1] @[el2_pic_ctl.scala 226:33] + level_intpend_w_prior_en[0][2] <= intpend_w_prior_en[2] @[el2_pic_ctl.scala 226:33] + level_intpend_w_prior_en[0][3] <= intpend_w_prior_en[3] @[el2_pic_ctl.scala 226:33] + level_intpend_w_prior_en[0][4] <= intpend_w_prior_en[4] @[el2_pic_ctl.scala 226:33] + level_intpend_w_prior_en[0][5] <= intpend_w_prior_en[5] @[el2_pic_ctl.scala 226:33] + level_intpend_w_prior_en[0][6] <= intpend_w_prior_en[6] @[el2_pic_ctl.scala 226:33] + level_intpend_w_prior_en[0][7] <= intpend_w_prior_en[7] @[el2_pic_ctl.scala 226:33] + level_intpend_w_prior_en[0][8] <= intpend_w_prior_en[8] @[el2_pic_ctl.scala 226:33] + level_intpend_w_prior_en[0][9] <= intpend_w_prior_en[9] @[el2_pic_ctl.scala 226:33] + level_intpend_w_prior_en[0][10] <= intpend_w_prior_en[10] @[el2_pic_ctl.scala 226:33] + level_intpend_w_prior_en[0][11] <= intpend_w_prior_en[11] @[el2_pic_ctl.scala 226:33] + level_intpend_w_prior_en[0][12] <= intpend_w_prior_en[12] @[el2_pic_ctl.scala 226:33] + level_intpend_w_prior_en[0][13] <= intpend_w_prior_en[13] @[el2_pic_ctl.scala 226:33] + level_intpend_w_prior_en[0][14] <= intpend_w_prior_en[14] @[el2_pic_ctl.scala 226:33] + level_intpend_w_prior_en[0][15] <= intpend_w_prior_en[15] @[el2_pic_ctl.scala 226:33] + level_intpend_w_prior_en[0][16] <= intpend_w_prior_en[16] @[el2_pic_ctl.scala 226:33] + level_intpend_w_prior_en[0][17] <= intpend_w_prior_en[17] @[el2_pic_ctl.scala 226:33] + level_intpend_w_prior_en[0][18] <= intpend_w_prior_en[18] @[el2_pic_ctl.scala 226:33] + level_intpend_w_prior_en[0][19] <= intpend_w_prior_en[19] @[el2_pic_ctl.scala 226:33] + level_intpend_w_prior_en[0][20] <= intpend_w_prior_en[20] @[el2_pic_ctl.scala 226:33] + level_intpend_w_prior_en[0][21] <= intpend_w_prior_en[21] @[el2_pic_ctl.scala 226:33] + level_intpend_w_prior_en[0][22] <= intpend_w_prior_en[22] @[el2_pic_ctl.scala 226:33] + level_intpend_w_prior_en[0][23] <= intpend_w_prior_en[23] @[el2_pic_ctl.scala 226:33] + level_intpend_w_prior_en[0][24] <= intpend_w_prior_en[24] @[el2_pic_ctl.scala 226:33] + level_intpend_w_prior_en[0][25] <= intpend_w_prior_en[25] @[el2_pic_ctl.scala 226:33] + level_intpend_w_prior_en[0][26] <= intpend_w_prior_en[26] @[el2_pic_ctl.scala 226:33] + level_intpend_w_prior_en[0][27] <= intpend_w_prior_en[27] @[el2_pic_ctl.scala 226:33] + level_intpend_w_prior_en[0][28] <= intpend_w_prior_en[28] @[el2_pic_ctl.scala 226:33] + level_intpend_w_prior_en[0][29] <= intpend_w_prior_en[29] @[el2_pic_ctl.scala 226:33] + level_intpend_w_prior_en[0][30] <= intpend_w_prior_en[30] @[el2_pic_ctl.scala 226:33] + level_intpend_w_prior_en[0][31] <= intpend_w_prior_en[31] @[el2_pic_ctl.scala 226:33] + level_intpend_w_prior_en[0][32] <= _T_1562 @[el2_pic_ctl.scala 226:33] + level_intpend_w_prior_en[0][33] <= _T_1563 @[el2_pic_ctl.scala 226:33] node _T_1564 = mux(UInt<1>("h01"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] node _T_1565 = mux(UInt<1>("h01"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - level_intpend_id[0][0] <= intpend_id[0] @[el2_pic_ctl.scala 235:33] - level_intpend_id[0][1] <= intpend_id[1] @[el2_pic_ctl.scala 235:33] - level_intpend_id[0][2] <= intpend_id[2] @[el2_pic_ctl.scala 235:33] - level_intpend_id[0][3] <= intpend_id[3] @[el2_pic_ctl.scala 235:33] - level_intpend_id[0][4] <= intpend_id[4] @[el2_pic_ctl.scala 235:33] - level_intpend_id[0][5] <= intpend_id[5] @[el2_pic_ctl.scala 235:33] - level_intpend_id[0][6] <= intpend_id[6] @[el2_pic_ctl.scala 235:33] - level_intpend_id[0][7] <= intpend_id[7] @[el2_pic_ctl.scala 235:33] - level_intpend_id[0][8] <= intpend_id[8] @[el2_pic_ctl.scala 235:33] - level_intpend_id[0][9] <= intpend_id[9] @[el2_pic_ctl.scala 235:33] - level_intpend_id[0][10] <= intpend_id[10] @[el2_pic_ctl.scala 235:33] - level_intpend_id[0][11] <= intpend_id[11] @[el2_pic_ctl.scala 235:33] - level_intpend_id[0][12] <= intpend_id[12] @[el2_pic_ctl.scala 235:33] - level_intpend_id[0][13] <= intpend_id[13] @[el2_pic_ctl.scala 235:33] - level_intpend_id[0][14] <= intpend_id[14] @[el2_pic_ctl.scala 235:33] - level_intpend_id[0][15] <= intpend_id[15] @[el2_pic_ctl.scala 235:33] - level_intpend_id[0][16] <= intpend_id[16] @[el2_pic_ctl.scala 235:33] - level_intpend_id[0][17] <= intpend_id[17] @[el2_pic_ctl.scala 235:33] - level_intpend_id[0][18] <= intpend_id[18] @[el2_pic_ctl.scala 235:33] - level_intpend_id[0][19] <= intpend_id[19] @[el2_pic_ctl.scala 235:33] - level_intpend_id[0][20] <= intpend_id[20] @[el2_pic_ctl.scala 235:33] - level_intpend_id[0][21] <= intpend_id[21] @[el2_pic_ctl.scala 235:33] - level_intpend_id[0][22] <= intpend_id[22] @[el2_pic_ctl.scala 235:33] - level_intpend_id[0][23] <= intpend_id[23] @[el2_pic_ctl.scala 235:33] - level_intpend_id[0][24] <= intpend_id[24] @[el2_pic_ctl.scala 235:33] - level_intpend_id[0][25] <= intpend_id[25] @[el2_pic_ctl.scala 235:33] - level_intpend_id[0][26] <= intpend_id[26] @[el2_pic_ctl.scala 235:33] - level_intpend_id[0][27] <= intpend_id[27] @[el2_pic_ctl.scala 235:33] - level_intpend_id[0][28] <= intpend_id[28] @[el2_pic_ctl.scala 235:33] - level_intpend_id[0][29] <= intpend_id[29] @[el2_pic_ctl.scala 235:33] - level_intpend_id[0][30] <= intpend_id[30] @[el2_pic_ctl.scala 235:33] - level_intpend_id[0][31] <= intpend_id[31] @[el2_pic_ctl.scala 235:33] - level_intpend_id[0][32] <= _T_1564 @[el2_pic_ctl.scala 235:33] - level_intpend_id[0][33] <= _T_1565 @[el2_pic_ctl.scala 235:33] - wire out_id : UInt<8> - out_id <= UInt<1>("h00") - wire out_priority : UInt<4> - out_priority <= UInt<1>("h00") - node _T_1566 = lt(level_intpend_w_prior_en[0][0], level_intpend_w_prior_en[0][1]) @[el2_pic_ctl.scala 38:29] - node _T_1567 = mux(_T_1566, level_intpend_id[0][1], level_intpend_id[0][0]) @[el2_pic_ctl.scala 38:18] - out_id <= _T_1567 @[el2_pic_ctl.scala 38:12] - node _T_1568 = lt(level_intpend_w_prior_en[0][0], level_intpend_w_prior_en[0][1]) @[el2_pic_ctl.scala 39:35] - node _T_1569 = mux(_T_1568, level_intpend_w_prior_en[0][1], level_intpend_w_prior_en[0][0]) @[el2_pic_ctl.scala 39:24] - out_priority <= _T_1569 @[el2_pic_ctl.scala 39:18] - level_intpend_id[1][0] <= out_id @[el2_pic_ctl.scala 246:43] - level_intpend_w_prior_en[1][0] <= out_priority @[el2_pic_ctl.scala 247:43] - wire out_id_1 : UInt<8> - out_id_1 <= UInt<1>("h00") - wire out_priority_1 : UInt<4> - out_priority_1 <= UInt<1>("h00") - node _T_1570 = lt(level_intpend_w_prior_en[0][2], level_intpend_w_prior_en[0][3]) @[el2_pic_ctl.scala 38:29] - node _T_1571 = mux(_T_1570, level_intpend_id[0][3], level_intpend_id[0][2]) @[el2_pic_ctl.scala 38:18] - out_id_1 <= _T_1571 @[el2_pic_ctl.scala 38:12] - node _T_1572 = lt(level_intpend_w_prior_en[0][2], level_intpend_w_prior_en[0][3]) @[el2_pic_ctl.scala 39:35] - node _T_1573 = mux(_T_1572, level_intpend_w_prior_en[0][3], level_intpend_w_prior_en[0][2]) @[el2_pic_ctl.scala 39:24] - out_priority_1 <= _T_1573 @[el2_pic_ctl.scala 39:18] - level_intpend_id[1][1] <= out_id_1 @[el2_pic_ctl.scala 246:43] - level_intpend_w_prior_en[1][1] <= out_priority_1 @[el2_pic_ctl.scala 247:43] - wire out_id_2 : UInt<8> - out_id_2 <= UInt<1>("h00") - wire out_priority_2 : UInt<4> - out_priority_2 <= UInt<1>("h00") - node _T_1574 = lt(level_intpend_w_prior_en[0][4], level_intpend_w_prior_en[0][5]) @[el2_pic_ctl.scala 38:29] - node _T_1575 = mux(_T_1574, level_intpend_id[0][5], level_intpend_id[0][4]) @[el2_pic_ctl.scala 38:18] - out_id_2 <= _T_1575 @[el2_pic_ctl.scala 38:12] - node _T_1576 = lt(level_intpend_w_prior_en[0][4], level_intpend_w_prior_en[0][5]) @[el2_pic_ctl.scala 39:35] - node _T_1577 = mux(_T_1576, level_intpend_w_prior_en[0][5], level_intpend_w_prior_en[0][4]) @[el2_pic_ctl.scala 39:24] - out_priority_2 <= _T_1577 @[el2_pic_ctl.scala 39:18] - level_intpend_id[1][2] <= out_id_2 @[el2_pic_ctl.scala 246:43] - level_intpend_w_prior_en[1][2] <= out_priority_2 @[el2_pic_ctl.scala 247:43] - wire out_id_3 : UInt<8> - out_id_3 <= UInt<1>("h00") - wire out_priority_3 : UInt<4> - out_priority_3 <= UInt<1>("h00") - node _T_1578 = lt(level_intpend_w_prior_en[0][6], level_intpend_w_prior_en[0][7]) @[el2_pic_ctl.scala 38:29] - node _T_1579 = mux(_T_1578, level_intpend_id[0][7], level_intpend_id[0][6]) @[el2_pic_ctl.scala 38:18] - out_id_3 <= _T_1579 @[el2_pic_ctl.scala 38:12] - node _T_1580 = lt(level_intpend_w_prior_en[0][6], level_intpend_w_prior_en[0][7]) @[el2_pic_ctl.scala 39:35] - node _T_1581 = mux(_T_1580, level_intpend_w_prior_en[0][7], level_intpend_w_prior_en[0][6]) @[el2_pic_ctl.scala 39:24] - out_priority_3 <= _T_1581 @[el2_pic_ctl.scala 39:18] - level_intpend_id[1][3] <= out_id_3 @[el2_pic_ctl.scala 246:43] - level_intpend_w_prior_en[1][3] <= out_priority_3 @[el2_pic_ctl.scala 247:43] - wire out_id_4 : UInt<8> - out_id_4 <= UInt<1>("h00") - wire out_priority_4 : UInt<4> - out_priority_4 <= UInt<1>("h00") - node _T_1582 = lt(level_intpend_w_prior_en[0][8], level_intpend_w_prior_en[0][9]) @[el2_pic_ctl.scala 38:29] - node _T_1583 = mux(_T_1582, level_intpend_id[0][9], level_intpend_id[0][8]) @[el2_pic_ctl.scala 38:18] - out_id_4 <= _T_1583 @[el2_pic_ctl.scala 38:12] - node _T_1584 = lt(level_intpend_w_prior_en[0][8], level_intpend_w_prior_en[0][9]) @[el2_pic_ctl.scala 39:35] - node _T_1585 = mux(_T_1584, level_intpend_w_prior_en[0][9], level_intpend_w_prior_en[0][8]) @[el2_pic_ctl.scala 39:24] - out_priority_4 <= _T_1585 @[el2_pic_ctl.scala 39:18] - level_intpend_id[1][4] <= out_id_4 @[el2_pic_ctl.scala 246:43] - level_intpend_w_prior_en[1][4] <= out_priority_4 @[el2_pic_ctl.scala 247:43] - wire out_id_5 : UInt<8> - out_id_5 <= UInt<1>("h00") - wire out_priority_5 : UInt<4> - out_priority_5 <= UInt<1>("h00") - node _T_1586 = lt(level_intpend_w_prior_en[0][10], level_intpend_w_prior_en[0][11]) @[el2_pic_ctl.scala 38:29] - node _T_1587 = mux(_T_1586, level_intpend_id[0][11], level_intpend_id[0][10]) @[el2_pic_ctl.scala 38:18] - out_id_5 <= _T_1587 @[el2_pic_ctl.scala 38:12] - node _T_1588 = lt(level_intpend_w_prior_en[0][10], level_intpend_w_prior_en[0][11]) @[el2_pic_ctl.scala 39:35] - node _T_1589 = mux(_T_1588, level_intpend_w_prior_en[0][11], level_intpend_w_prior_en[0][10]) @[el2_pic_ctl.scala 39:24] - out_priority_5 <= _T_1589 @[el2_pic_ctl.scala 39:18] - level_intpend_id[1][5] <= out_id_5 @[el2_pic_ctl.scala 246:43] - level_intpend_w_prior_en[1][5] <= out_priority_5 @[el2_pic_ctl.scala 247:43] - wire out_id_6 : UInt<8> - out_id_6 <= UInt<1>("h00") - wire out_priority_6 : UInt<4> - out_priority_6 <= UInt<1>("h00") - node _T_1590 = lt(level_intpend_w_prior_en[0][12], level_intpend_w_prior_en[0][13]) @[el2_pic_ctl.scala 38:29] - node _T_1591 = mux(_T_1590, level_intpend_id[0][13], level_intpend_id[0][12]) @[el2_pic_ctl.scala 38:18] - out_id_6 <= _T_1591 @[el2_pic_ctl.scala 38:12] - node _T_1592 = lt(level_intpend_w_prior_en[0][12], level_intpend_w_prior_en[0][13]) @[el2_pic_ctl.scala 39:35] - node _T_1593 = mux(_T_1592, level_intpend_w_prior_en[0][13], level_intpend_w_prior_en[0][12]) @[el2_pic_ctl.scala 39:24] - out_priority_6 <= _T_1593 @[el2_pic_ctl.scala 39:18] - level_intpend_id[1][6] <= out_id_6 @[el2_pic_ctl.scala 246:43] - level_intpend_w_prior_en[1][6] <= out_priority_6 @[el2_pic_ctl.scala 247:43] - wire out_id_7 : UInt<8> - out_id_7 <= UInt<1>("h00") - wire out_priority_7 : UInt<4> - out_priority_7 <= UInt<1>("h00") - node _T_1594 = lt(level_intpend_w_prior_en[0][14], level_intpend_w_prior_en[0][15]) @[el2_pic_ctl.scala 38:29] - node _T_1595 = mux(_T_1594, level_intpend_id[0][15], level_intpend_id[0][14]) @[el2_pic_ctl.scala 38:18] - out_id_7 <= _T_1595 @[el2_pic_ctl.scala 38:12] - node _T_1596 = lt(level_intpend_w_prior_en[0][14], level_intpend_w_prior_en[0][15]) @[el2_pic_ctl.scala 39:35] - node _T_1597 = mux(_T_1596, level_intpend_w_prior_en[0][15], level_intpend_w_prior_en[0][14]) @[el2_pic_ctl.scala 39:24] - out_priority_7 <= _T_1597 @[el2_pic_ctl.scala 39:18] - level_intpend_id[1][7] <= out_id_7 @[el2_pic_ctl.scala 246:43] - level_intpend_w_prior_en[1][7] <= out_priority_7 @[el2_pic_ctl.scala 247:43] - wire out_id_8 : UInt<8> - out_id_8 <= UInt<1>("h00") - wire out_priority_8 : UInt<4> - out_priority_8 <= UInt<1>("h00") - node _T_1598 = lt(level_intpend_w_prior_en[0][16], level_intpend_w_prior_en[0][17]) @[el2_pic_ctl.scala 38:29] - node _T_1599 = mux(_T_1598, level_intpend_id[0][17], level_intpend_id[0][16]) @[el2_pic_ctl.scala 38:18] - out_id_8 <= _T_1599 @[el2_pic_ctl.scala 38:12] - node _T_1600 = lt(level_intpend_w_prior_en[0][16], level_intpend_w_prior_en[0][17]) @[el2_pic_ctl.scala 39:35] - node _T_1601 = mux(_T_1600, level_intpend_w_prior_en[0][17], level_intpend_w_prior_en[0][16]) @[el2_pic_ctl.scala 39:24] - out_priority_8 <= _T_1601 @[el2_pic_ctl.scala 39:18] - level_intpend_id[1][8] <= out_id_8 @[el2_pic_ctl.scala 246:43] - level_intpend_w_prior_en[1][8] <= out_priority_8 @[el2_pic_ctl.scala 247:43] - wire out_id_9 : UInt<8> - out_id_9 <= UInt<1>("h00") - wire out_priority_9 : UInt<4> - out_priority_9 <= UInt<1>("h00") - node _T_1602 = lt(level_intpend_w_prior_en[0][18], level_intpend_w_prior_en[0][19]) @[el2_pic_ctl.scala 38:29] - node _T_1603 = mux(_T_1602, level_intpend_id[0][19], level_intpend_id[0][18]) @[el2_pic_ctl.scala 38:18] - out_id_9 <= _T_1603 @[el2_pic_ctl.scala 38:12] - node _T_1604 = lt(level_intpend_w_prior_en[0][18], level_intpend_w_prior_en[0][19]) @[el2_pic_ctl.scala 39:35] - node _T_1605 = mux(_T_1604, level_intpend_w_prior_en[0][19], level_intpend_w_prior_en[0][18]) @[el2_pic_ctl.scala 39:24] - out_priority_9 <= _T_1605 @[el2_pic_ctl.scala 39:18] - level_intpend_id[1][9] <= out_id_9 @[el2_pic_ctl.scala 246:43] - level_intpend_w_prior_en[1][9] <= out_priority_9 @[el2_pic_ctl.scala 247:43] - wire out_id_10 : UInt<8> - out_id_10 <= UInt<1>("h00") - wire out_priority_10 : UInt<4> - out_priority_10 <= UInt<1>("h00") - node _T_1606 = lt(level_intpend_w_prior_en[0][20], level_intpend_w_prior_en[0][21]) @[el2_pic_ctl.scala 38:29] - node _T_1607 = mux(_T_1606, level_intpend_id[0][21], level_intpend_id[0][20]) @[el2_pic_ctl.scala 38:18] - out_id_10 <= _T_1607 @[el2_pic_ctl.scala 38:12] - node _T_1608 = lt(level_intpend_w_prior_en[0][20], level_intpend_w_prior_en[0][21]) @[el2_pic_ctl.scala 39:35] - node _T_1609 = mux(_T_1608, level_intpend_w_prior_en[0][21], level_intpend_w_prior_en[0][20]) @[el2_pic_ctl.scala 39:24] - out_priority_10 <= _T_1609 @[el2_pic_ctl.scala 39:18] - level_intpend_id[1][10] <= out_id_10 @[el2_pic_ctl.scala 246:43] - level_intpend_w_prior_en[1][10] <= out_priority_10 @[el2_pic_ctl.scala 247:43] - wire out_id_11 : UInt<8> - out_id_11 <= UInt<1>("h00") - wire out_priority_11 : UInt<4> - out_priority_11 <= UInt<1>("h00") - node _T_1610 = lt(level_intpend_w_prior_en[0][22], level_intpend_w_prior_en[0][23]) @[el2_pic_ctl.scala 38:29] - node _T_1611 = mux(_T_1610, level_intpend_id[0][23], level_intpend_id[0][22]) @[el2_pic_ctl.scala 38:18] - out_id_11 <= _T_1611 @[el2_pic_ctl.scala 38:12] - node _T_1612 = lt(level_intpend_w_prior_en[0][22], level_intpend_w_prior_en[0][23]) @[el2_pic_ctl.scala 39:35] - node _T_1613 = mux(_T_1612, level_intpend_w_prior_en[0][23], level_intpend_w_prior_en[0][22]) @[el2_pic_ctl.scala 39:24] - out_priority_11 <= _T_1613 @[el2_pic_ctl.scala 39:18] - level_intpend_id[1][11] <= out_id_11 @[el2_pic_ctl.scala 246:43] - level_intpend_w_prior_en[1][11] <= out_priority_11 @[el2_pic_ctl.scala 247:43] - wire out_id_12 : UInt<8> - out_id_12 <= UInt<1>("h00") - wire out_priority_12 : UInt<4> - out_priority_12 <= UInt<1>("h00") - node _T_1614 = lt(level_intpend_w_prior_en[0][24], level_intpend_w_prior_en[0][25]) @[el2_pic_ctl.scala 38:29] - node _T_1615 = mux(_T_1614, level_intpend_id[0][25], level_intpend_id[0][24]) @[el2_pic_ctl.scala 38:18] - out_id_12 <= _T_1615 @[el2_pic_ctl.scala 38:12] - node _T_1616 = lt(level_intpend_w_prior_en[0][24], level_intpend_w_prior_en[0][25]) @[el2_pic_ctl.scala 39:35] - node _T_1617 = mux(_T_1616, level_intpend_w_prior_en[0][25], level_intpend_w_prior_en[0][24]) @[el2_pic_ctl.scala 39:24] - out_priority_12 <= _T_1617 @[el2_pic_ctl.scala 39:18] - level_intpend_id[1][12] <= out_id_12 @[el2_pic_ctl.scala 246:43] - level_intpend_w_prior_en[1][12] <= out_priority_12 @[el2_pic_ctl.scala 247:43] - wire out_id_13 : UInt<8> - out_id_13 <= UInt<1>("h00") - wire out_priority_13 : UInt<4> - out_priority_13 <= UInt<1>("h00") - node _T_1618 = lt(level_intpend_w_prior_en[0][26], level_intpend_w_prior_en[0][27]) @[el2_pic_ctl.scala 38:29] - node _T_1619 = mux(_T_1618, level_intpend_id[0][27], level_intpend_id[0][26]) @[el2_pic_ctl.scala 38:18] - out_id_13 <= _T_1619 @[el2_pic_ctl.scala 38:12] - node _T_1620 = lt(level_intpend_w_prior_en[0][26], level_intpend_w_prior_en[0][27]) @[el2_pic_ctl.scala 39:35] - node _T_1621 = mux(_T_1620, level_intpend_w_prior_en[0][27], level_intpend_w_prior_en[0][26]) @[el2_pic_ctl.scala 39:24] - out_priority_13 <= _T_1621 @[el2_pic_ctl.scala 39:18] - level_intpend_id[1][13] <= out_id_13 @[el2_pic_ctl.scala 246:43] - level_intpend_w_prior_en[1][13] <= out_priority_13 @[el2_pic_ctl.scala 247:43] - wire out_id_14 : UInt<8> - out_id_14 <= UInt<1>("h00") - wire out_priority_14 : UInt<4> - out_priority_14 <= UInt<1>("h00") - node _T_1622 = lt(level_intpend_w_prior_en[0][28], level_intpend_w_prior_en[0][29]) @[el2_pic_ctl.scala 38:29] - node _T_1623 = mux(_T_1622, level_intpend_id[0][29], level_intpend_id[0][28]) @[el2_pic_ctl.scala 38:18] - out_id_14 <= _T_1623 @[el2_pic_ctl.scala 38:12] - node _T_1624 = lt(level_intpend_w_prior_en[0][28], level_intpend_w_prior_en[0][29]) @[el2_pic_ctl.scala 39:35] - node _T_1625 = mux(_T_1624, level_intpend_w_prior_en[0][29], level_intpend_w_prior_en[0][28]) @[el2_pic_ctl.scala 39:24] - out_priority_14 <= _T_1625 @[el2_pic_ctl.scala 39:18] - level_intpend_id[1][14] <= out_id_14 @[el2_pic_ctl.scala 246:43] - level_intpend_w_prior_en[1][14] <= out_priority_14 @[el2_pic_ctl.scala 247:43] - wire out_id_15 : UInt<8> - out_id_15 <= UInt<1>("h00") - wire out_priority_15 : UInt<4> - out_priority_15 <= UInt<1>("h00") - node _T_1626 = lt(level_intpend_w_prior_en[0][30], level_intpend_w_prior_en[0][31]) @[el2_pic_ctl.scala 38:29] - node _T_1627 = mux(_T_1626, level_intpend_id[0][31], level_intpend_id[0][30]) @[el2_pic_ctl.scala 38:18] - out_id_15 <= _T_1627 @[el2_pic_ctl.scala 38:12] - node _T_1628 = lt(level_intpend_w_prior_en[0][30], level_intpend_w_prior_en[0][31]) @[el2_pic_ctl.scala 39:35] - node _T_1629 = mux(_T_1628, level_intpend_w_prior_en[0][31], level_intpend_w_prior_en[0][30]) @[el2_pic_ctl.scala 39:24] - out_priority_15 <= _T_1629 @[el2_pic_ctl.scala 39:18] - level_intpend_id[1][15] <= out_id_15 @[el2_pic_ctl.scala 246:43] - level_intpend_w_prior_en[1][15] <= out_priority_15 @[el2_pic_ctl.scala 247:43] - level_intpend_w_prior_en[1][17] <= UInt<1>("h00") @[el2_pic_ctl.scala 242:46] - level_intpend_id[1][17] <= UInt<1>("h00") @[el2_pic_ctl.scala 243:46] - wire out_id_16 : UInt<8> - out_id_16 <= UInt<1>("h00") - wire out_priority_16 : UInt<4> - out_priority_16 <= UInt<1>("h00") - node _T_1630 = lt(level_intpend_w_prior_en[0][32], level_intpend_w_prior_en[0][33]) @[el2_pic_ctl.scala 38:29] - node _T_1631 = mux(_T_1630, level_intpend_id[0][33], level_intpend_id[0][32]) @[el2_pic_ctl.scala 38:18] - out_id_16 <= _T_1631 @[el2_pic_ctl.scala 38:12] - node _T_1632 = lt(level_intpend_w_prior_en[0][32], level_intpend_w_prior_en[0][33]) @[el2_pic_ctl.scala 39:35] - node _T_1633 = mux(_T_1632, level_intpend_w_prior_en[0][33], level_intpend_w_prior_en[0][32]) @[el2_pic_ctl.scala 39:24] - out_priority_16 <= _T_1633 @[el2_pic_ctl.scala 39:18] - level_intpend_id[1][16] <= out_id_16 @[el2_pic_ctl.scala 246:43] - level_intpend_w_prior_en[1][16] <= out_priority_16 @[el2_pic_ctl.scala 247:43] - wire out_id_17 : UInt<8> - out_id_17 <= UInt<1>("h00") - wire out_priority_17 : UInt<4> - out_priority_17 <= UInt<1>("h00") - node _T_1634 = lt(level_intpend_w_prior_en[1][0], level_intpend_w_prior_en[1][1]) @[el2_pic_ctl.scala 38:29] - node _T_1635 = mux(_T_1634, level_intpend_id[1][1], level_intpend_id[1][0]) @[el2_pic_ctl.scala 38:18] - out_id_17 <= _T_1635 @[el2_pic_ctl.scala 38:12] - node _T_1636 = lt(level_intpend_w_prior_en[1][0], level_intpend_w_prior_en[1][1]) @[el2_pic_ctl.scala 39:35] - node _T_1637 = mux(_T_1636, level_intpend_w_prior_en[1][1], level_intpend_w_prior_en[1][0]) @[el2_pic_ctl.scala 39:24] - out_priority_17 <= _T_1637 @[el2_pic_ctl.scala 39:18] - level_intpend_id[2][0] <= out_id_17 @[el2_pic_ctl.scala 246:43] - level_intpend_w_prior_en[2][0] <= out_priority_17 @[el2_pic_ctl.scala 247:43] - wire out_id_18 : UInt<8> - out_id_18 <= UInt<1>("h00") - wire out_priority_18 : UInt<4> - out_priority_18 <= UInt<1>("h00") - node _T_1638 = lt(level_intpend_w_prior_en[1][2], level_intpend_w_prior_en[1][3]) @[el2_pic_ctl.scala 38:29] - node _T_1639 = mux(_T_1638, level_intpend_id[1][3], level_intpend_id[1][2]) @[el2_pic_ctl.scala 38:18] - out_id_18 <= _T_1639 @[el2_pic_ctl.scala 38:12] - node _T_1640 = lt(level_intpend_w_prior_en[1][2], level_intpend_w_prior_en[1][3]) @[el2_pic_ctl.scala 39:35] - node _T_1641 = mux(_T_1640, level_intpend_w_prior_en[1][3], level_intpend_w_prior_en[1][2]) @[el2_pic_ctl.scala 39:24] - out_priority_18 <= _T_1641 @[el2_pic_ctl.scala 39:18] - level_intpend_id[2][1] <= out_id_18 @[el2_pic_ctl.scala 246:43] - level_intpend_w_prior_en[2][1] <= out_priority_18 @[el2_pic_ctl.scala 247:43] - wire out_id_19 : UInt<8> - out_id_19 <= UInt<1>("h00") - wire out_priority_19 : UInt<4> - out_priority_19 <= UInt<1>("h00") - node _T_1642 = lt(level_intpend_w_prior_en[1][4], level_intpend_w_prior_en[1][5]) @[el2_pic_ctl.scala 38:29] - node _T_1643 = mux(_T_1642, level_intpend_id[1][5], level_intpend_id[1][4]) @[el2_pic_ctl.scala 38:18] - out_id_19 <= _T_1643 @[el2_pic_ctl.scala 38:12] - node _T_1644 = lt(level_intpend_w_prior_en[1][4], level_intpend_w_prior_en[1][5]) @[el2_pic_ctl.scala 39:35] - node _T_1645 = mux(_T_1644, level_intpend_w_prior_en[1][5], level_intpend_w_prior_en[1][4]) @[el2_pic_ctl.scala 39:24] - out_priority_19 <= _T_1645 @[el2_pic_ctl.scala 39:18] - level_intpend_id[2][2] <= out_id_19 @[el2_pic_ctl.scala 246:43] - level_intpend_w_prior_en[2][2] <= out_priority_19 @[el2_pic_ctl.scala 247:43] - wire out_id_20 : UInt<8> - out_id_20 <= UInt<1>("h00") - wire out_priority_20 : UInt<4> - out_priority_20 <= UInt<1>("h00") - node _T_1646 = lt(level_intpend_w_prior_en[1][6], level_intpend_w_prior_en[1][7]) @[el2_pic_ctl.scala 38:29] - node _T_1647 = mux(_T_1646, level_intpend_id[1][7], level_intpend_id[1][6]) @[el2_pic_ctl.scala 38:18] - out_id_20 <= _T_1647 @[el2_pic_ctl.scala 38:12] - node _T_1648 = lt(level_intpend_w_prior_en[1][6], level_intpend_w_prior_en[1][7]) @[el2_pic_ctl.scala 39:35] - node _T_1649 = mux(_T_1648, level_intpend_w_prior_en[1][7], level_intpend_w_prior_en[1][6]) @[el2_pic_ctl.scala 39:24] - out_priority_20 <= _T_1649 @[el2_pic_ctl.scala 39:18] - level_intpend_id[2][3] <= out_id_20 @[el2_pic_ctl.scala 246:43] - level_intpend_w_prior_en[2][3] <= out_priority_20 @[el2_pic_ctl.scala 247:43] - wire out_id_21 : UInt<8> - out_id_21 <= UInt<1>("h00") - wire out_priority_21 : UInt<4> - out_priority_21 <= UInt<1>("h00") - node _T_1650 = lt(level_intpend_w_prior_en[1][8], level_intpend_w_prior_en[1][9]) @[el2_pic_ctl.scala 38:29] - node _T_1651 = mux(_T_1650, level_intpend_id[1][9], level_intpend_id[1][8]) @[el2_pic_ctl.scala 38:18] - out_id_21 <= _T_1651 @[el2_pic_ctl.scala 38:12] - node _T_1652 = lt(level_intpend_w_prior_en[1][8], level_intpend_w_prior_en[1][9]) @[el2_pic_ctl.scala 39:35] - node _T_1653 = mux(_T_1652, level_intpend_w_prior_en[1][9], level_intpend_w_prior_en[1][8]) @[el2_pic_ctl.scala 39:24] - out_priority_21 <= _T_1653 @[el2_pic_ctl.scala 39:18] - level_intpend_id[2][4] <= out_id_21 @[el2_pic_ctl.scala 246:43] - level_intpend_w_prior_en[2][4] <= out_priority_21 @[el2_pic_ctl.scala 247:43] - wire out_id_22 : UInt<8> - out_id_22 <= UInt<1>("h00") - wire out_priority_22 : UInt<4> - out_priority_22 <= UInt<1>("h00") - node _T_1654 = lt(level_intpend_w_prior_en[1][10], level_intpend_w_prior_en[1][11]) @[el2_pic_ctl.scala 38:29] - node _T_1655 = mux(_T_1654, level_intpend_id[1][11], level_intpend_id[1][10]) @[el2_pic_ctl.scala 38:18] - out_id_22 <= _T_1655 @[el2_pic_ctl.scala 38:12] - node _T_1656 = lt(level_intpend_w_prior_en[1][10], level_intpend_w_prior_en[1][11]) @[el2_pic_ctl.scala 39:35] - node _T_1657 = mux(_T_1656, level_intpend_w_prior_en[1][11], level_intpend_w_prior_en[1][10]) @[el2_pic_ctl.scala 39:24] - out_priority_22 <= _T_1657 @[el2_pic_ctl.scala 39:18] - level_intpend_id[2][5] <= out_id_22 @[el2_pic_ctl.scala 246:43] - level_intpend_w_prior_en[2][5] <= out_priority_22 @[el2_pic_ctl.scala 247:43] - wire out_id_23 : UInt<8> - out_id_23 <= UInt<1>("h00") - wire out_priority_23 : UInt<4> - out_priority_23 <= UInt<1>("h00") - node _T_1658 = lt(level_intpend_w_prior_en[1][12], level_intpend_w_prior_en[1][13]) @[el2_pic_ctl.scala 38:29] - node _T_1659 = mux(_T_1658, level_intpend_id[1][13], level_intpend_id[1][12]) @[el2_pic_ctl.scala 38:18] - out_id_23 <= _T_1659 @[el2_pic_ctl.scala 38:12] - node _T_1660 = lt(level_intpend_w_prior_en[1][12], level_intpend_w_prior_en[1][13]) @[el2_pic_ctl.scala 39:35] - node _T_1661 = mux(_T_1660, level_intpend_w_prior_en[1][13], level_intpend_w_prior_en[1][12]) @[el2_pic_ctl.scala 39:24] - out_priority_23 <= _T_1661 @[el2_pic_ctl.scala 39:18] - level_intpend_id[2][6] <= out_id_23 @[el2_pic_ctl.scala 246:43] - level_intpend_w_prior_en[2][6] <= out_priority_23 @[el2_pic_ctl.scala 247:43] - wire out_id_24 : UInt<8> - out_id_24 <= UInt<1>("h00") - wire out_priority_24 : UInt<4> - out_priority_24 <= UInt<1>("h00") - node _T_1662 = lt(level_intpend_w_prior_en[1][14], level_intpend_w_prior_en[1][15]) @[el2_pic_ctl.scala 38:29] - node _T_1663 = mux(_T_1662, level_intpend_id[1][15], level_intpend_id[1][14]) @[el2_pic_ctl.scala 38:18] - out_id_24 <= _T_1663 @[el2_pic_ctl.scala 38:12] - node _T_1664 = lt(level_intpend_w_prior_en[1][14], level_intpend_w_prior_en[1][15]) @[el2_pic_ctl.scala 39:35] - node _T_1665 = mux(_T_1664, level_intpend_w_prior_en[1][15], level_intpend_w_prior_en[1][14]) @[el2_pic_ctl.scala 39:24] - out_priority_24 <= _T_1665 @[el2_pic_ctl.scala 39:18] - level_intpend_id[2][7] <= out_id_24 @[el2_pic_ctl.scala 246:43] - level_intpend_w_prior_en[2][7] <= out_priority_24 @[el2_pic_ctl.scala 247:43] - level_intpend_w_prior_en[2][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 242:46] - level_intpend_id[2][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 243:46] - wire out_id_25 : UInt<8> - out_id_25 <= UInt<1>("h00") - wire out_priority_25 : UInt<4> - out_priority_25 <= UInt<1>("h00") - node _T_1666 = lt(level_intpend_w_prior_en[1][16], level_intpend_w_prior_en[1][17]) @[el2_pic_ctl.scala 38:29] - node _T_1667 = mux(_T_1666, level_intpend_id[1][17], level_intpend_id[1][16]) @[el2_pic_ctl.scala 38:18] - out_id_25 <= _T_1667 @[el2_pic_ctl.scala 38:12] - node _T_1668 = lt(level_intpend_w_prior_en[1][16], level_intpend_w_prior_en[1][17]) @[el2_pic_ctl.scala 39:35] - node _T_1669 = mux(_T_1668, level_intpend_w_prior_en[1][17], level_intpend_w_prior_en[1][16]) @[el2_pic_ctl.scala 39:24] - out_priority_25 <= _T_1669 @[el2_pic_ctl.scala 39:18] - level_intpend_id[2][8] <= out_id_25 @[el2_pic_ctl.scala 246:43] - level_intpend_w_prior_en[2][8] <= out_priority_25 @[el2_pic_ctl.scala 247:43] - wire out_id_26 : UInt<8> - out_id_26 <= UInt<1>("h00") - wire out_priority_26 : UInt<4> - out_priority_26 <= UInt<1>("h00") - node _T_1670 = lt(level_intpend_w_prior_en[2][0], level_intpend_w_prior_en[2][1]) @[el2_pic_ctl.scala 38:29] - node _T_1671 = mux(_T_1670, level_intpend_id[2][1], level_intpend_id[2][0]) @[el2_pic_ctl.scala 38:18] - out_id_26 <= _T_1671 @[el2_pic_ctl.scala 38:12] - node _T_1672 = lt(level_intpend_w_prior_en[2][0], level_intpend_w_prior_en[2][1]) @[el2_pic_ctl.scala 39:35] - node _T_1673 = mux(_T_1672, level_intpend_w_prior_en[2][1], level_intpend_w_prior_en[2][0]) @[el2_pic_ctl.scala 39:24] - out_priority_26 <= _T_1673 @[el2_pic_ctl.scala 39:18] - level_intpend_id[3][0] <= out_id_26 @[el2_pic_ctl.scala 246:43] - level_intpend_w_prior_en[3][0] <= out_priority_26 @[el2_pic_ctl.scala 247:43] - wire out_id_27 : UInt<8> - out_id_27 <= UInt<1>("h00") - wire out_priority_27 : UInt<4> - out_priority_27 <= UInt<1>("h00") - node _T_1674 = lt(level_intpend_w_prior_en[2][2], level_intpend_w_prior_en[2][3]) @[el2_pic_ctl.scala 38:29] - node _T_1675 = mux(_T_1674, level_intpend_id[2][3], level_intpend_id[2][2]) @[el2_pic_ctl.scala 38:18] - out_id_27 <= _T_1675 @[el2_pic_ctl.scala 38:12] - node _T_1676 = lt(level_intpend_w_prior_en[2][2], level_intpend_w_prior_en[2][3]) @[el2_pic_ctl.scala 39:35] - node _T_1677 = mux(_T_1676, level_intpend_w_prior_en[2][3], level_intpend_w_prior_en[2][2]) @[el2_pic_ctl.scala 39:24] - out_priority_27 <= _T_1677 @[el2_pic_ctl.scala 39:18] - level_intpend_id[3][1] <= out_id_27 @[el2_pic_ctl.scala 246:43] - level_intpend_w_prior_en[3][1] <= out_priority_27 @[el2_pic_ctl.scala 247:43] - wire out_id_28 : UInt<8> - out_id_28 <= UInt<1>("h00") - wire out_priority_28 : UInt<4> - out_priority_28 <= UInt<1>("h00") - node _T_1678 = lt(level_intpend_w_prior_en[2][4], level_intpend_w_prior_en[2][5]) @[el2_pic_ctl.scala 38:29] - node _T_1679 = mux(_T_1678, level_intpend_id[2][5], level_intpend_id[2][4]) @[el2_pic_ctl.scala 38:18] - out_id_28 <= _T_1679 @[el2_pic_ctl.scala 38:12] - node _T_1680 = lt(level_intpend_w_prior_en[2][4], level_intpend_w_prior_en[2][5]) @[el2_pic_ctl.scala 39:35] - node _T_1681 = mux(_T_1680, level_intpend_w_prior_en[2][5], level_intpend_w_prior_en[2][4]) @[el2_pic_ctl.scala 39:24] - out_priority_28 <= _T_1681 @[el2_pic_ctl.scala 39:18] - level_intpend_id[3][2] <= out_id_28 @[el2_pic_ctl.scala 246:43] - level_intpend_w_prior_en[3][2] <= out_priority_28 @[el2_pic_ctl.scala 247:43] - wire out_id_29 : UInt<8> - out_id_29 <= UInt<1>("h00") - wire out_priority_29 : UInt<4> - out_priority_29 <= UInt<1>("h00") - node _T_1682 = lt(level_intpend_w_prior_en[2][6], level_intpend_w_prior_en[2][7]) @[el2_pic_ctl.scala 38:29] - node _T_1683 = mux(_T_1682, level_intpend_id[2][7], level_intpend_id[2][6]) @[el2_pic_ctl.scala 38:18] - out_id_29 <= _T_1683 @[el2_pic_ctl.scala 38:12] - node _T_1684 = lt(level_intpend_w_prior_en[2][6], level_intpend_w_prior_en[2][7]) @[el2_pic_ctl.scala 39:35] - node _T_1685 = mux(_T_1684, level_intpend_w_prior_en[2][7], level_intpend_w_prior_en[2][6]) @[el2_pic_ctl.scala 39:24] - out_priority_29 <= _T_1685 @[el2_pic_ctl.scala 39:18] - level_intpend_id[3][3] <= out_id_29 @[el2_pic_ctl.scala 246:43] - level_intpend_w_prior_en[3][3] <= out_priority_29 @[el2_pic_ctl.scala 247:43] - level_intpend_w_prior_en[3][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 242:46] - level_intpend_id[3][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 243:46] - wire out_id_30 : UInt<8> - out_id_30 <= UInt<1>("h00") - wire out_priority_30 : UInt<4> - out_priority_30 <= UInt<1>("h00") - node _T_1686 = lt(level_intpend_w_prior_en[2][8], level_intpend_w_prior_en[2][9]) @[el2_pic_ctl.scala 38:29] - node _T_1687 = mux(_T_1686, level_intpend_id[2][9], level_intpend_id[2][8]) @[el2_pic_ctl.scala 38:18] - out_id_30 <= _T_1687 @[el2_pic_ctl.scala 38:12] - node _T_1688 = lt(level_intpend_w_prior_en[2][8], level_intpend_w_prior_en[2][9]) @[el2_pic_ctl.scala 39:35] - node _T_1689 = mux(_T_1688, level_intpend_w_prior_en[2][9], level_intpend_w_prior_en[2][8]) @[el2_pic_ctl.scala 39:24] - out_priority_30 <= _T_1689 @[el2_pic_ctl.scala 39:18] - level_intpend_id[3][4] <= out_id_30 @[el2_pic_ctl.scala 246:43] - level_intpend_w_prior_en[3][4] <= out_priority_30 @[el2_pic_ctl.scala 247:43] - wire out_id_31 : UInt<8> - out_id_31 <= UInt<1>("h00") - wire out_priority_31 : UInt<4> - out_priority_31 <= UInt<1>("h00") - node _T_1690 = lt(level_intpend_w_prior_en[3][0], level_intpend_w_prior_en[3][1]) @[el2_pic_ctl.scala 38:29] - node _T_1691 = mux(_T_1690, level_intpend_id[3][1], level_intpend_id[3][0]) @[el2_pic_ctl.scala 38:18] - out_id_31 <= _T_1691 @[el2_pic_ctl.scala 38:12] - node _T_1692 = lt(level_intpend_w_prior_en[3][0], level_intpend_w_prior_en[3][1]) @[el2_pic_ctl.scala 39:35] - node _T_1693 = mux(_T_1692, level_intpend_w_prior_en[3][1], level_intpend_w_prior_en[3][0]) @[el2_pic_ctl.scala 39:24] - out_priority_31 <= _T_1693 @[el2_pic_ctl.scala 39:18] - level_intpend_id[4][0] <= out_id_31 @[el2_pic_ctl.scala 246:43] - level_intpend_w_prior_en[4][0] <= out_priority_31 @[el2_pic_ctl.scala 247:43] - wire out_id_32 : UInt<8> - out_id_32 <= UInt<1>("h00") - wire out_priority_32 : UInt<4> - out_priority_32 <= UInt<1>("h00") - node _T_1694 = lt(level_intpend_w_prior_en[3][2], level_intpend_w_prior_en[3][3]) @[el2_pic_ctl.scala 38:29] - node _T_1695 = mux(_T_1694, level_intpend_id[3][3], level_intpend_id[3][2]) @[el2_pic_ctl.scala 38:18] - out_id_32 <= _T_1695 @[el2_pic_ctl.scala 38:12] - node _T_1696 = lt(level_intpend_w_prior_en[3][2], level_intpend_w_prior_en[3][3]) @[el2_pic_ctl.scala 39:35] - node _T_1697 = mux(_T_1696, level_intpend_w_prior_en[3][3], level_intpend_w_prior_en[3][2]) @[el2_pic_ctl.scala 39:24] - out_priority_32 <= _T_1697 @[el2_pic_ctl.scala 39:18] - level_intpend_id[4][1] <= out_id_32 @[el2_pic_ctl.scala 246:43] - level_intpend_w_prior_en[4][1] <= out_priority_32 @[el2_pic_ctl.scala 247:43] - level_intpend_w_prior_en[4][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 242:46] - level_intpend_id[4][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 243:46] - wire out_id_33 : UInt<8> - out_id_33 <= UInt<1>("h00") - wire out_priority_33 : UInt<4> - out_priority_33 <= UInt<1>("h00") - node _T_1698 = lt(level_intpend_w_prior_en[3][4], level_intpend_w_prior_en[3][5]) @[el2_pic_ctl.scala 38:29] - node _T_1699 = mux(_T_1698, level_intpend_id[3][5], level_intpend_id[3][4]) @[el2_pic_ctl.scala 38:18] - out_id_33 <= _T_1699 @[el2_pic_ctl.scala 38:12] - node _T_1700 = lt(level_intpend_w_prior_en[3][4], level_intpend_w_prior_en[3][5]) @[el2_pic_ctl.scala 39:35] - node _T_1701 = mux(_T_1700, level_intpend_w_prior_en[3][5], level_intpend_w_prior_en[3][4]) @[el2_pic_ctl.scala 39:24] - out_priority_33 <= _T_1701 @[el2_pic_ctl.scala 39:18] - level_intpend_id[4][2] <= out_id_33 @[el2_pic_ctl.scala 246:43] - level_intpend_w_prior_en[4][2] <= out_priority_33 @[el2_pic_ctl.scala 247:43] - wire out_id_34 : UInt<8> - out_id_34 <= UInt<1>("h00") - wire out_priority_34 : UInt<4> - out_priority_34 <= UInt<1>("h00") - node _T_1702 = lt(level_intpend_w_prior_en[4][0], level_intpend_w_prior_en[4][1]) @[el2_pic_ctl.scala 38:29] - node _T_1703 = mux(_T_1702, level_intpend_id[4][1], level_intpend_id[4][0]) @[el2_pic_ctl.scala 38:18] - out_id_34 <= _T_1703 @[el2_pic_ctl.scala 38:12] - node _T_1704 = lt(level_intpend_w_prior_en[4][0], level_intpend_w_prior_en[4][1]) @[el2_pic_ctl.scala 39:35] - node _T_1705 = mux(_T_1704, level_intpend_w_prior_en[4][1], level_intpend_w_prior_en[4][0]) @[el2_pic_ctl.scala 39:24] - out_priority_34 <= _T_1705 @[el2_pic_ctl.scala 39:18] - level_intpend_id[5][0] <= out_id_34 @[el2_pic_ctl.scala 246:43] - level_intpend_w_prior_en[5][0] <= out_priority_34 @[el2_pic_ctl.scala 247:43] - level_intpend_w_prior_en[5][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 242:46] - level_intpend_id[5][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 243:46] - wire out_id_35 : UInt<8> - out_id_35 <= UInt<1>("h00") - wire out_priority_35 : UInt<4> - out_priority_35 <= UInt<1>("h00") - node _T_1706 = lt(level_intpend_w_prior_en[4][2], level_intpend_w_prior_en[4][3]) @[el2_pic_ctl.scala 38:29] - node _T_1707 = mux(_T_1706, level_intpend_id[4][3], level_intpend_id[4][2]) @[el2_pic_ctl.scala 38:18] - out_id_35 <= _T_1707 @[el2_pic_ctl.scala 38:12] - node _T_1708 = lt(level_intpend_w_prior_en[4][2], level_intpend_w_prior_en[4][3]) @[el2_pic_ctl.scala 39:35] - node _T_1709 = mux(_T_1708, level_intpend_w_prior_en[4][3], level_intpend_w_prior_en[4][2]) @[el2_pic_ctl.scala 39:24] - out_priority_35 <= _T_1709 @[el2_pic_ctl.scala 39:18] - level_intpend_id[5][1] <= out_id_35 @[el2_pic_ctl.scala 246:43] - level_intpend_w_prior_en[5][1] <= out_priority_35 @[el2_pic_ctl.scala 247:43] - claimid_in <= level_intpend_id[5][0] @[el2_pic_ctl.scala 250:29] - selected_int_priority <= level_intpend_w_prior_en[5][0] @[el2_pic_ctl.scala 251:29] - node config_reg_we = and(waddr_config_pic_match, picm_wren_ff) @[el2_pic_ctl.scala 263:47] - node config_reg_re = and(raddr_config_pic_match, picm_rden_ff) @[el2_pic_ctl.scala 264:47] - node config_reg_in = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 265:39] - node _T_1710 = bits(config_reg_we, 0, 0) @[el2_pic_ctl.scala 266:82] - reg _T_1711 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_1710 : @[Reg.scala 28:19] - _T_1711 <= config_reg_in @[Reg.scala 28:23] + level_intpend_id[0][0] <= intpend_id[0] @[el2_pic_ctl.scala 227:33] + level_intpend_id[0][1] <= intpend_id[1] @[el2_pic_ctl.scala 227:33] + level_intpend_id[0][2] <= intpend_id[2] @[el2_pic_ctl.scala 227:33] + level_intpend_id[0][3] <= intpend_id[3] @[el2_pic_ctl.scala 227:33] + level_intpend_id[0][4] <= intpend_id[4] @[el2_pic_ctl.scala 227:33] + level_intpend_id[0][5] <= intpend_id[5] @[el2_pic_ctl.scala 227:33] + level_intpend_id[0][6] <= intpend_id[6] @[el2_pic_ctl.scala 227:33] + level_intpend_id[0][7] <= intpend_id[7] @[el2_pic_ctl.scala 227:33] + level_intpend_id[0][8] <= intpend_id[8] @[el2_pic_ctl.scala 227:33] + level_intpend_id[0][9] <= intpend_id[9] @[el2_pic_ctl.scala 227:33] + level_intpend_id[0][10] <= intpend_id[10] @[el2_pic_ctl.scala 227:33] + level_intpend_id[0][11] <= intpend_id[11] @[el2_pic_ctl.scala 227:33] + level_intpend_id[0][12] <= intpend_id[12] @[el2_pic_ctl.scala 227:33] + level_intpend_id[0][13] <= intpend_id[13] @[el2_pic_ctl.scala 227:33] + level_intpend_id[0][14] <= intpend_id[14] @[el2_pic_ctl.scala 227:33] + level_intpend_id[0][15] <= intpend_id[15] @[el2_pic_ctl.scala 227:33] + level_intpend_id[0][16] <= intpend_id[16] @[el2_pic_ctl.scala 227:33] + level_intpend_id[0][17] <= intpend_id[17] @[el2_pic_ctl.scala 227:33] + level_intpend_id[0][18] <= intpend_id[18] @[el2_pic_ctl.scala 227:33] + level_intpend_id[0][19] <= intpend_id[19] @[el2_pic_ctl.scala 227:33] + level_intpend_id[0][20] <= intpend_id[20] @[el2_pic_ctl.scala 227:33] + level_intpend_id[0][21] <= intpend_id[21] @[el2_pic_ctl.scala 227:33] + level_intpend_id[0][22] <= intpend_id[22] @[el2_pic_ctl.scala 227:33] + level_intpend_id[0][23] <= intpend_id[23] @[el2_pic_ctl.scala 227:33] + level_intpend_id[0][24] <= intpend_id[24] @[el2_pic_ctl.scala 227:33] + level_intpend_id[0][25] <= intpend_id[25] @[el2_pic_ctl.scala 227:33] + level_intpend_id[0][26] <= intpend_id[26] @[el2_pic_ctl.scala 227:33] + level_intpend_id[0][27] <= intpend_id[27] @[el2_pic_ctl.scala 227:33] + level_intpend_id[0][28] <= intpend_id[28] @[el2_pic_ctl.scala 227:33] + level_intpend_id[0][29] <= intpend_id[29] @[el2_pic_ctl.scala 227:33] + level_intpend_id[0][30] <= intpend_id[30] @[el2_pic_ctl.scala 227:33] + level_intpend_id[0][31] <= intpend_id[31] @[el2_pic_ctl.scala 227:33] + level_intpend_id[0][32] <= _T_1564 @[el2_pic_ctl.scala 227:33] + level_intpend_id[0][33] <= _T_1565 @[el2_pic_ctl.scala 227:33] + node _T_1566 = lt(level_intpend_w_prior_en[0][0], level_intpend_w_prior_en[0][1]) @[el2_pic_ctl.scala 33:20] + node out_id = mux(_T_1566, level_intpend_id[0][1], level_intpend_id[0][0]) @[el2_pic_ctl.scala 33:9] + node _T_1567 = lt(level_intpend_w_prior_en[0][0], level_intpend_w_prior_en[0][1]) @[el2_pic_ctl.scala 33:60] + node out_priority = mux(_T_1567, level_intpend_w_prior_en[0][1], level_intpend_w_prior_en[0][0]) @[el2_pic_ctl.scala 33:49] + level_intpend_id[1][0] <= out_id @[el2_pic_ctl.scala 238:43] + level_intpend_w_prior_en[1][0] <= out_priority @[el2_pic_ctl.scala 239:43] + node _T_1568 = lt(level_intpend_w_prior_en[0][2], level_intpend_w_prior_en[0][3]) @[el2_pic_ctl.scala 33:20] + node out_id_1 = mux(_T_1568, level_intpend_id[0][3], level_intpend_id[0][2]) @[el2_pic_ctl.scala 33:9] + node _T_1569 = lt(level_intpend_w_prior_en[0][2], level_intpend_w_prior_en[0][3]) @[el2_pic_ctl.scala 33:60] + node out_priority_1 = mux(_T_1569, level_intpend_w_prior_en[0][3], level_intpend_w_prior_en[0][2]) @[el2_pic_ctl.scala 33:49] + level_intpend_id[1][1] <= out_id_1 @[el2_pic_ctl.scala 238:43] + level_intpend_w_prior_en[1][1] <= out_priority_1 @[el2_pic_ctl.scala 239:43] + node _T_1570 = lt(level_intpend_w_prior_en[0][4], level_intpend_w_prior_en[0][5]) @[el2_pic_ctl.scala 33:20] + node out_id_2 = mux(_T_1570, level_intpend_id[0][5], level_intpend_id[0][4]) @[el2_pic_ctl.scala 33:9] + node _T_1571 = lt(level_intpend_w_prior_en[0][4], level_intpend_w_prior_en[0][5]) @[el2_pic_ctl.scala 33:60] + node out_priority_2 = mux(_T_1571, level_intpend_w_prior_en[0][5], level_intpend_w_prior_en[0][4]) @[el2_pic_ctl.scala 33:49] + level_intpend_id[1][2] <= out_id_2 @[el2_pic_ctl.scala 238:43] + level_intpend_w_prior_en[1][2] <= out_priority_2 @[el2_pic_ctl.scala 239:43] + node _T_1572 = lt(level_intpend_w_prior_en[0][6], level_intpend_w_prior_en[0][7]) @[el2_pic_ctl.scala 33:20] + node out_id_3 = mux(_T_1572, level_intpend_id[0][7], level_intpend_id[0][6]) @[el2_pic_ctl.scala 33:9] + node _T_1573 = lt(level_intpend_w_prior_en[0][6], level_intpend_w_prior_en[0][7]) @[el2_pic_ctl.scala 33:60] + node out_priority_3 = mux(_T_1573, level_intpend_w_prior_en[0][7], level_intpend_w_prior_en[0][6]) @[el2_pic_ctl.scala 33:49] + level_intpend_id[1][3] <= out_id_3 @[el2_pic_ctl.scala 238:43] + level_intpend_w_prior_en[1][3] <= out_priority_3 @[el2_pic_ctl.scala 239:43] + node _T_1574 = lt(level_intpend_w_prior_en[0][8], level_intpend_w_prior_en[0][9]) @[el2_pic_ctl.scala 33:20] + node out_id_4 = mux(_T_1574, level_intpend_id[0][9], level_intpend_id[0][8]) @[el2_pic_ctl.scala 33:9] + node _T_1575 = lt(level_intpend_w_prior_en[0][8], level_intpend_w_prior_en[0][9]) @[el2_pic_ctl.scala 33:60] + node out_priority_4 = mux(_T_1575, level_intpend_w_prior_en[0][9], level_intpend_w_prior_en[0][8]) @[el2_pic_ctl.scala 33:49] + level_intpend_id[1][4] <= out_id_4 @[el2_pic_ctl.scala 238:43] + level_intpend_w_prior_en[1][4] <= out_priority_4 @[el2_pic_ctl.scala 239:43] + node _T_1576 = lt(level_intpend_w_prior_en[0][10], level_intpend_w_prior_en[0][11]) @[el2_pic_ctl.scala 33:20] + node out_id_5 = mux(_T_1576, level_intpend_id[0][11], level_intpend_id[0][10]) @[el2_pic_ctl.scala 33:9] + node _T_1577 = lt(level_intpend_w_prior_en[0][10], level_intpend_w_prior_en[0][11]) @[el2_pic_ctl.scala 33:60] + node out_priority_5 = mux(_T_1577, level_intpend_w_prior_en[0][11], level_intpend_w_prior_en[0][10]) @[el2_pic_ctl.scala 33:49] + level_intpend_id[1][5] <= out_id_5 @[el2_pic_ctl.scala 238:43] + level_intpend_w_prior_en[1][5] <= out_priority_5 @[el2_pic_ctl.scala 239:43] + node _T_1578 = lt(level_intpend_w_prior_en[0][12], level_intpend_w_prior_en[0][13]) @[el2_pic_ctl.scala 33:20] + node out_id_6 = mux(_T_1578, level_intpend_id[0][13], level_intpend_id[0][12]) @[el2_pic_ctl.scala 33:9] + node _T_1579 = lt(level_intpend_w_prior_en[0][12], level_intpend_w_prior_en[0][13]) @[el2_pic_ctl.scala 33:60] + node out_priority_6 = mux(_T_1579, level_intpend_w_prior_en[0][13], level_intpend_w_prior_en[0][12]) @[el2_pic_ctl.scala 33:49] + level_intpend_id[1][6] <= out_id_6 @[el2_pic_ctl.scala 238:43] + level_intpend_w_prior_en[1][6] <= out_priority_6 @[el2_pic_ctl.scala 239:43] + node _T_1580 = lt(level_intpend_w_prior_en[0][14], level_intpend_w_prior_en[0][15]) @[el2_pic_ctl.scala 33:20] + node out_id_7 = mux(_T_1580, level_intpend_id[0][15], level_intpend_id[0][14]) @[el2_pic_ctl.scala 33:9] + node _T_1581 = lt(level_intpend_w_prior_en[0][14], level_intpend_w_prior_en[0][15]) @[el2_pic_ctl.scala 33:60] + node out_priority_7 = mux(_T_1581, level_intpend_w_prior_en[0][15], level_intpend_w_prior_en[0][14]) @[el2_pic_ctl.scala 33:49] + level_intpend_id[1][7] <= out_id_7 @[el2_pic_ctl.scala 238:43] + level_intpend_w_prior_en[1][7] <= out_priority_7 @[el2_pic_ctl.scala 239:43] + node _T_1582 = lt(level_intpend_w_prior_en[0][16], level_intpend_w_prior_en[0][17]) @[el2_pic_ctl.scala 33:20] + node out_id_8 = mux(_T_1582, level_intpend_id[0][17], level_intpend_id[0][16]) @[el2_pic_ctl.scala 33:9] + node _T_1583 = lt(level_intpend_w_prior_en[0][16], level_intpend_w_prior_en[0][17]) @[el2_pic_ctl.scala 33:60] + node out_priority_8 = mux(_T_1583, level_intpend_w_prior_en[0][17], level_intpend_w_prior_en[0][16]) @[el2_pic_ctl.scala 33:49] + level_intpend_id[1][8] <= out_id_8 @[el2_pic_ctl.scala 238:43] + level_intpend_w_prior_en[1][8] <= out_priority_8 @[el2_pic_ctl.scala 239:43] + node _T_1584 = lt(level_intpend_w_prior_en[0][18], level_intpend_w_prior_en[0][19]) @[el2_pic_ctl.scala 33:20] + node out_id_9 = mux(_T_1584, level_intpend_id[0][19], level_intpend_id[0][18]) @[el2_pic_ctl.scala 33:9] + node _T_1585 = lt(level_intpend_w_prior_en[0][18], level_intpend_w_prior_en[0][19]) @[el2_pic_ctl.scala 33:60] + node out_priority_9 = mux(_T_1585, level_intpend_w_prior_en[0][19], level_intpend_w_prior_en[0][18]) @[el2_pic_ctl.scala 33:49] + level_intpend_id[1][9] <= out_id_9 @[el2_pic_ctl.scala 238:43] + level_intpend_w_prior_en[1][9] <= out_priority_9 @[el2_pic_ctl.scala 239:43] + node _T_1586 = lt(level_intpend_w_prior_en[0][20], level_intpend_w_prior_en[0][21]) @[el2_pic_ctl.scala 33:20] + node out_id_10 = mux(_T_1586, level_intpend_id[0][21], level_intpend_id[0][20]) @[el2_pic_ctl.scala 33:9] + node _T_1587 = lt(level_intpend_w_prior_en[0][20], level_intpend_w_prior_en[0][21]) @[el2_pic_ctl.scala 33:60] + node out_priority_10 = mux(_T_1587, level_intpend_w_prior_en[0][21], level_intpend_w_prior_en[0][20]) @[el2_pic_ctl.scala 33:49] + level_intpend_id[1][10] <= out_id_10 @[el2_pic_ctl.scala 238:43] + level_intpend_w_prior_en[1][10] <= out_priority_10 @[el2_pic_ctl.scala 239:43] + node _T_1588 = lt(level_intpend_w_prior_en[0][22], level_intpend_w_prior_en[0][23]) @[el2_pic_ctl.scala 33:20] + node out_id_11 = mux(_T_1588, level_intpend_id[0][23], level_intpend_id[0][22]) @[el2_pic_ctl.scala 33:9] + node _T_1589 = lt(level_intpend_w_prior_en[0][22], level_intpend_w_prior_en[0][23]) @[el2_pic_ctl.scala 33:60] + node out_priority_11 = mux(_T_1589, level_intpend_w_prior_en[0][23], level_intpend_w_prior_en[0][22]) @[el2_pic_ctl.scala 33:49] + level_intpend_id[1][11] <= out_id_11 @[el2_pic_ctl.scala 238:43] + level_intpend_w_prior_en[1][11] <= out_priority_11 @[el2_pic_ctl.scala 239:43] + node _T_1590 = lt(level_intpend_w_prior_en[0][24], level_intpend_w_prior_en[0][25]) @[el2_pic_ctl.scala 33:20] + node out_id_12 = mux(_T_1590, level_intpend_id[0][25], level_intpend_id[0][24]) @[el2_pic_ctl.scala 33:9] + node _T_1591 = lt(level_intpend_w_prior_en[0][24], level_intpend_w_prior_en[0][25]) @[el2_pic_ctl.scala 33:60] + node out_priority_12 = mux(_T_1591, level_intpend_w_prior_en[0][25], level_intpend_w_prior_en[0][24]) @[el2_pic_ctl.scala 33:49] + level_intpend_id[1][12] <= out_id_12 @[el2_pic_ctl.scala 238:43] + level_intpend_w_prior_en[1][12] <= out_priority_12 @[el2_pic_ctl.scala 239:43] + node _T_1592 = lt(level_intpend_w_prior_en[0][26], level_intpend_w_prior_en[0][27]) @[el2_pic_ctl.scala 33:20] + node out_id_13 = mux(_T_1592, level_intpend_id[0][27], level_intpend_id[0][26]) @[el2_pic_ctl.scala 33:9] + node _T_1593 = lt(level_intpend_w_prior_en[0][26], level_intpend_w_prior_en[0][27]) @[el2_pic_ctl.scala 33:60] + node out_priority_13 = mux(_T_1593, level_intpend_w_prior_en[0][27], level_intpend_w_prior_en[0][26]) @[el2_pic_ctl.scala 33:49] + level_intpend_id[1][13] <= out_id_13 @[el2_pic_ctl.scala 238:43] + level_intpend_w_prior_en[1][13] <= out_priority_13 @[el2_pic_ctl.scala 239:43] + node _T_1594 = lt(level_intpend_w_prior_en[0][28], level_intpend_w_prior_en[0][29]) @[el2_pic_ctl.scala 33:20] + node out_id_14 = mux(_T_1594, level_intpend_id[0][29], level_intpend_id[0][28]) @[el2_pic_ctl.scala 33:9] + node _T_1595 = lt(level_intpend_w_prior_en[0][28], level_intpend_w_prior_en[0][29]) @[el2_pic_ctl.scala 33:60] + node out_priority_14 = mux(_T_1595, level_intpend_w_prior_en[0][29], level_intpend_w_prior_en[0][28]) @[el2_pic_ctl.scala 33:49] + level_intpend_id[1][14] <= out_id_14 @[el2_pic_ctl.scala 238:43] + level_intpend_w_prior_en[1][14] <= out_priority_14 @[el2_pic_ctl.scala 239:43] + node _T_1596 = lt(level_intpend_w_prior_en[0][30], level_intpend_w_prior_en[0][31]) @[el2_pic_ctl.scala 33:20] + node out_id_15 = mux(_T_1596, level_intpend_id[0][31], level_intpend_id[0][30]) @[el2_pic_ctl.scala 33:9] + node _T_1597 = lt(level_intpend_w_prior_en[0][30], level_intpend_w_prior_en[0][31]) @[el2_pic_ctl.scala 33:60] + node out_priority_15 = mux(_T_1597, level_intpend_w_prior_en[0][31], level_intpend_w_prior_en[0][30]) @[el2_pic_ctl.scala 33:49] + level_intpend_id[1][15] <= out_id_15 @[el2_pic_ctl.scala 238:43] + level_intpend_w_prior_en[1][15] <= out_priority_15 @[el2_pic_ctl.scala 239:43] + level_intpend_w_prior_en[1][17] <= UInt<1>("h00") @[el2_pic_ctl.scala 234:46] + level_intpend_id[1][17] <= UInt<1>("h00") @[el2_pic_ctl.scala 235:46] + node _T_1598 = lt(level_intpend_w_prior_en[0][32], level_intpend_w_prior_en[0][33]) @[el2_pic_ctl.scala 33:20] + node out_id_16 = mux(_T_1598, level_intpend_id[0][33], level_intpend_id[0][32]) @[el2_pic_ctl.scala 33:9] + node _T_1599 = lt(level_intpend_w_prior_en[0][32], level_intpend_w_prior_en[0][33]) @[el2_pic_ctl.scala 33:60] + node out_priority_16 = mux(_T_1599, level_intpend_w_prior_en[0][33], level_intpend_w_prior_en[0][32]) @[el2_pic_ctl.scala 33:49] + level_intpend_id[1][16] <= out_id_16 @[el2_pic_ctl.scala 238:43] + level_intpend_w_prior_en[1][16] <= out_priority_16 @[el2_pic_ctl.scala 239:43] + node _T_1600 = lt(level_intpend_w_prior_en[1][0], level_intpend_w_prior_en[1][1]) @[el2_pic_ctl.scala 33:20] + node out_id_17 = mux(_T_1600, level_intpend_id[1][1], level_intpend_id[1][0]) @[el2_pic_ctl.scala 33:9] + node _T_1601 = lt(level_intpend_w_prior_en[1][0], level_intpend_w_prior_en[1][1]) @[el2_pic_ctl.scala 33:60] + node out_priority_17 = mux(_T_1601, level_intpend_w_prior_en[1][1], level_intpend_w_prior_en[1][0]) @[el2_pic_ctl.scala 33:49] + level_intpend_id[2][0] <= out_id_17 @[el2_pic_ctl.scala 238:43] + level_intpend_w_prior_en[2][0] <= out_priority_17 @[el2_pic_ctl.scala 239:43] + node _T_1602 = lt(level_intpend_w_prior_en[1][2], level_intpend_w_prior_en[1][3]) @[el2_pic_ctl.scala 33:20] + node out_id_18 = mux(_T_1602, level_intpend_id[1][3], level_intpend_id[1][2]) @[el2_pic_ctl.scala 33:9] + node _T_1603 = lt(level_intpend_w_prior_en[1][2], level_intpend_w_prior_en[1][3]) @[el2_pic_ctl.scala 33:60] + node out_priority_18 = mux(_T_1603, level_intpend_w_prior_en[1][3], level_intpend_w_prior_en[1][2]) @[el2_pic_ctl.scala 33:49] + level_intpend_id[2][1] <= out_id_18 @[el2_pic_ctl.scala 238:43] + level_intpend_w_prior_en[2][1] <= out_priority_18 @[el2_pic_ctl.scala 239:43] + node _T_1604 = lt(level_intpend_w_prior_en[1][4], level_intpend_w_prior_en[1][5]) @[el2_pic_ctl.scala 33:20] + node out_id_19 = mux(_T_1604, level_intpend_id[1][5], level_intpend_id[1][4]) @[el2_pic_ctl.scala 33:9] + node _T_1605 = lt(level_intpend_w_prior_en[1][4], level_intpend_w_prior_en[1][5]) @[el2_pic_ctl.scala 33:60] + node out_priority_19 = mux(_T_1605, level_intpend_w_prior_en[1][5], level_intpend_w_prior_en[1][4]) @[el2_pic_ctl.scala 33:49] + level_intpend_id[2][2] <= out_id_19 @[el2_pic_ctl.scala 238:43] + level_intpend_w_prior_en[2][2] <= out_priority_19 @[el2_pic_ctl.scala 239:43] + node _T_1606 = lt(level_intpend_w_prior_en[1][6], level_intpend_w_prior_en[1][7]) @[el2_pic_ctl.scala 33:20] + node out_id_20 = mux(_T_1606, level_intpend_id[1][7], level_intpend_id[1][6]) @[el2_pic_ctl.scala 33:9] + node _T_1607 = lt(level_intpend_w_prior_en[1][6], level_intpend_w_prior_en[1][7]) @[el2_pic_ctl.scala 33:60] + node out_priority_20 = mux(_T_1607, level_intpend_w_prior_en[1][7], level_intpend_w_prior_en[1][6]) @[el2_pic_ctl.scala 33:49] + level_intpend_id[2][3] <= out_id_20 @[el2_pic_ctl.scala 238:43] + level_intpend_w_prior_en[2][3] <= out_priority_20 @[el2_pic_ctl.scala 239:43] + node _T_1608 = lt(level_intpend_w_prior_en[1][8], level_intpend_w_prior_en[1][9]) @[el2_pic_ctl.scala 33:20] + node out_id_21 = mux(_T_1608, level_intpend_id[1][9], level_intpend_id[1][8]) @[el2_pic_ctl.scala 33:9] + node _T_1609 = lt(level_intpend_w_prior_en[1][8], level_intpend_w_prior_en[1][9]) @[el2_pic_ctl.scala 33:60] + node out_priority_21 = mux(_T_1609, level_intpend_w_prior_en[1][9], level_intpend_w_prior_en[1][8]) @[el2_pic_ctl.scala 33:49] + level_intpend_id[2][4] <= out_id_21 @[el2_pic_ctl.scala 238:43] + level_intpend_w_prior_en[2][4] <= out_priority_21 @[el2_pic_ctl.scala 239:43] + node _T_1610 = lt(level_intpend_w_prior_en[1][10], level_intpend_w_prior_en[1][11]) @[el2_pic_ctl.scala 33:20] + node out_id_22 = mux(_T_1610, level_intpend_id[1][11], level_intpend_id[1][10]) @[el2_pic_ctl.scala 33:9] + node _T_1611 = lt(level_intpend_w_prior_en[1][10], level_intpend_w_prior_en[1][11]) @[el2_pic_ctl.scala 33:60] + node out_priority_22 = mux(_T_1611, level_intpend_w_prior_en[1][11], level_intpend_w_prior_en[1][10]) @[el2_pic_ctl.scala 33:49] + level_intpend_id[2][5] <= out_id_22 @[el2_pic_ctl.scala 238:43] + level_intpend_w_prior_en[2][5] <= out_priority_22 @[el2_pic_ctl.scala 239:43] + node _T_1612 = lt(level_intpend_w_prior_en[1][12], level_intpend_w_prior_en[1][13]) @[el2_pic_ctl.scala 33:20] + node out_id_23 = mux(_T_1612, level_intpend_id[1][13], level_intpend_id[1][12]) @[el2_pic_ctl.scala 33:9] + node _T_1613 = lt(level_intpend_w_prior_en[1][12], level_intpend_w_prior_en[1][13]) @[el2_pic_ctl.scala 33:60] + node out_priority_23 = mux(_T_1613, level_intpend_w_prior_en[1][13], level_intpend_w_prior_en[1][12]) @[el2_pic_ctl.scala 33:49] + level_intpend_id[2][6] <= out_id_23 @[el2_pic_ctl.scala 238:43] + level_intpend_w_prior_en[2][6] <= out_priority_23 @[el2_pic_ctl.scala 239:43] + node _T_1614 = lt(level_intpend_w_prior_en[1][14], level_intpend_w_prior_en[1][15]) @[el2_pic_ctl.scala 33:20] + node out_id_24 = mux(_T_1614, level_intpend_id[1][15], level_intpend_id[1][14]) @[el2_pic_ctl.scala 33:9] + node _T_1615 = lt(level_intpend_w_prior_en[1][14], level_intpend_w_prior_en[1][15]) @[el2_pic_ctl.scala 33:60] + node out_priority_24 = mux(_T_1615, level_intpend_w_prior_en[1][15], level_intpend_w_prior_en[1][14]) @[el2_pic_ctl.scala 33:49] + level_intpend_id[2][7] <= out_id_24 @[el2_pic_ctl.scala 238:43] + level_intpend_w_prior_en[2][7] <= out_priority_24 @[el2_pic_ctl.scala 239:43] + level_intpend_w_prior_en[2][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 234:46] + level_intpend_id[2][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 235:46] + node _T_1616 = lt(level_intpend_w_prior_en[1][16], level_intpend_w_prior_en[1][17]) @[el2_pic_ctl.scala 33:20] + node out_id_25 = mux(_T_1616, level_intpend_id[1][17], level_intpend_id[1][16]) @[el2_pic_ctl.scala 33:9] + node _T_1617 = lt(level_intpend_w_prior_en[1][16], level_intpend_w_prior_en[1][17]) @[el2_pic_ctl.scala 33:60] + node out_priority_25 = mux(_T_1617, level_intpend_w_prior_en[1][17], level_intpend_w_prior_en[1][16]) @[el2_pic_ctl.scala 33:49] + level_intpend_id[2][8] <= out_id_25 @[el2_pic_ctl.scala 238:43] + level_intpend_w_prior_en[2][8] <= out_priority_25 @[el2_pic_ctl.scala 239:43] + node _T_1618 = lt(level_intpend_w_prior_en[2][0], level_intpend_w_prior_en[2][1]) @[el2_pic_ctl.scala 33:20] + node out_id_26 = mux(_T_1618, level_intpend_id[2][1], level_intpend_id[2][0]) @[el2_pic_ctl.scala 33:9] + node _T_1619 = lt(level_intpend_w_prior_en[2][0], level_intpend_w_prior_en[2][1]) @[el2_pic_ctl.scala 33:60] + node out_priority_26 = mux(_T_1619, level_intpend_w_prior_en[2][1], level_intpend_w_prior_en[2][0]) @[el2_pic_ctl.scala 33:49] + level_intpend_id[3][0] <= out_id_26 @[el2_pic_ctl.scala 238:43] + level_intpend_w_prior_en[3][0] <= out_priority_26 @[el2_pic_ctl.scala 239:43] + node _T_1620 = lt(level_intpend_w_prior_en[2][2], level_intpend_w_prior_en[2][3]) @[el2_pic_ctl.scala 33:20] + node out_id_27 = mux(_T_1620, level_intpend_id[2][3], level_intpend_id[2][2]) @[el2_pic_ctl.scala 33:9] + node _T_1621 = lt(level_intpend_w_prior_en[2][2], level_intpend_w_prior_en[2][3]) @[el2_pic_ctl.scala 33:60] + node out_priority_27 = mux(_T_1621, level_intpend_w_prior_en[2][3], level_intpend_w_prior_en[2][2]) @[el2_pic_ctl.scala 33:49] + level_intpend_id[3][1] <= out_id_27 @[el2_pic_ctl.scala 238:43] + level_intpend_w_prior_en[3][1] <= out_priority_27 @[el2_pic_ctl.scala 239:43] + node _T_1622 = lt(level_intpend_w_prior_en[2][4], level_intpend_w_prior_en[2][5]) @[el2_pic_ctl.scala 33:20] + node out_id_28 = mux(_T_1622, level_intpend_id[2][5], level_intpend_id[2][4]) @[el2_pic_ctl.scala 33:9] + node _T_1623 = lt(level_intpend_w_prior_en[2][4], level_intpend_w_prior_en[2][5]) @[el2_pic_ctl.scala 33:60] + node out_priority_28 = mux(_T_1623, level_intpend_w_prior_en[2][5], level_intpend_w_prior_en[2][4]) @[el2_pic_ctl.scala 33:49] + level_intpend_id[3][2] <= out_id_28 @[el2_pic_ctl.scala 238:43] + level_intpend_w_prior_en[3][2] <= out_priority_28 @[el2_pic_ctl.scala 239:43] + node _T_1624 = lt(level_intpend_w_prior_en[2][6], level_intpend_w_prior_en[2][7]) @[el2_pic_ctl.scala 33:20] + node out_id_29 = mux(_T_1624, level_intpend_id[2][7], level_intpend_id[2][6]) @[el2_pic_ctl.scala 33:9] + node _T_1625 = lt(level_intpend_w_prior_en[2][6], level_intpend_w_prior_en[2][7]) @[el2_pic_ctl.scala 33:60] + node out_priority_29 = mux(_T_1625, level_intpend_w_prior_en[2][7], level_intpend_w_prior_en[2][6]) @[el2_pic_ctl.scala 33:49] + level_intpend_id[3][3] <= out_id_29 @[el2_pic_ctl.scala 238:43] + level_intpend_w_prior_en[3][3] <= out_priority_29 @[el2_pic_ctl.scala 239:43] + level_intpend_w_prior_en[3][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 234:46] + level_intpend_id[3][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 235:46] + node _T_1626 = lt(level_intpend_w_prior_en[2][8], level_intpend_w_prior_en[2][9]) @[el2_pic_ctl.scala 33:20] + node out_id_30 = mux(_T_1626, level_intpend_id[2][9], level_intpend_id[2][8]) @[el2_pic_ctl.scala 33:9] + node _T_1627 = lt(level_intpend_w_prior_en[2][8], level_intpend_w_prior_en[2][9]) @[el2_pic_ctl.scala 33:60] + node out_priority_30 = mux(_T_1627, level_intpend_w_prior_en[2][9], level_intpend_w_prior_en[2][8]) @[el2_pic_ctl.scala 33:49] + level_intpend_id[3][4] <= out_id_30 @[el2_pic_ctl.scala 238:43] + level_intpend_w_prior_en[3][4] <= out_priority_30 @[el2_pic_ctl.scala 239:43] + node _T_1628 = lt(level_intpend_w_prior_en[3][0], level_intpend_w_prior_en[3][1]) @[el2_pic_ctl.scala 33:20] + node out_id_31 = mux(_T_1628, level_intpend_id[3][1], level_intpend_id[3][0]) @[el2_pic_ctl.scala 33:9] + node _T_1629 = lt(level_intpend_w_prior_en[3][0], level_intpend_w_prior_en[3][1]) @[el2_pic_ctl.scala 33:60] + node out_priority_31 = mux(_T_1629, level_intpend_w_prior_en[3][1], level_intpend_w_prior_en[3][0]) @[el2_pic_ctl.scala 33:49] + level_intpend_id[4][0] <= out_id_31 @[el2_pic_ctl.scala 238:43] + level_intpend_w_prior_en[4][0] <= out_priority_31 @[el2_pic_ctl.scala 239:43] + node _T_1630 = lt(level_intpend_w_prior_en[3][2], level_intpend_w_prior_en[3][3]) @[el2_pic_ctl.scala 33:20] + node out_id_32 = mux(_T_1630, level_intpend_id[3][3], level_intpend_id[3][2]) @[el2_pic_ctl.scala 33:9] + node _T_1631 = lt(level_intpend_w_prior_en[3][2], level_intpend_w_prior_en[3][3]) @[el2_pic_ctl.scala 33:60] + node out_priority_32 = mux(_T_1631, level_intpend_w_prior_en[3][3], level_intpend_w_prior_en[3][2]) @[el2_pic_ctl.scala 33:49] + level_intpend_id[4][1] <= out_id_32 @[el2_pic_ctl.scala 238:43] + level_intpend_w_prior_en[4][1] <= out_priority_32 @[el2_pic_ctl.scala 239:43] + level_intpend_w_prior_en[4][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 234:46] + level_intpend_id[4][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 235:46] + node _T_1632 = lt(level_intpend_w_prior_en[3][4], level_intpend_w_prior_en[3][5]) @[el2_pic_ctl.scala 33:20] + node out_id_33 = mux(_T_1632, level_intpend_id[3][5], level_intpend_id[3][4]) @[el2_pic_ctl.scala 33:9] + node _T_1633 = lt(level_intpend_w_prior_en[3][4], level_intpend_w_prior_en[3][5]) @[el2_pic_ctl.scala 33:60] + node out_priority_33 = mux(_T_1633, level_intpend_w_prior_en[3][5], level_intpend_w_prior_en[3][4]) @[el2_pic_ctl.scala 33:49] + level_intpend_id[4][2] <= out_id_33 @[el2_pic_ctl.scala 238:43] + level_intpend_w_prior_en[4][2] <= out_priority_33 @[el2_pic_ctl.scala 239:43] + node _T_1634 = lt(level_intpend_w_prior_en[4][0], level_intpend_w_prior_en[4][1]) @[el2_pic_ctl.scala 33:20] + node out_id_34 = mux(_T_1634, level_intpend_id[4][1], level_intpend_id[4][0]) @[el2_pic_ctl.scala 33:9] + node _T_1635 = lt(level_intpend_w_prior_en[4][0], level_intpend_w_prior_en[4][1]) @[el2_pic_ctl.scala 33:60] + node out_priority_34 = mux(_T_1635, level_intpend_w_prior_en[4][1], level_intpend_w_prior_en[4][0]) @[el2_pic_ctl.scala 33:49] + level_intpend_id[5][0] <= out_id_34 @[el2_pic_ctl.scala 238:43] + level_intpend_w_prior_en[5][0] <= out_priority_34 @[el2_pic_ctl.scala 239:43] + level_intpend_w_prior_en[5][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 234:46] + level_intpend_id[5][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 235:46] + node _T_1636 = lt(level_intpend_w_prior_en[4][2], level_intpend_w_prior_en[4][3]) @[el2_pic_ctl.scala 33:20] + node out_id_35 = mux(_T_1636, level_intpend_id[4][3], level_intpend_id[4][2]) @[el2_pic_ctl.scala 33:9] + node _T_1637 = lt(level_intpend_w_prior_en[4][2], level_intpend_w_prior_en[4][3]) @[el2_pic_ctl.scala 33:60] + node out_priority_35 = mux(_T_1637, level_intpend_w_prior_en[4][3], level_intpend_w_prior_en[4][2]) @[el2_pic_ctl.scala 33:49] + level_intpend_id[5][1] <= out_id_35 @[el2_pic_ctl.scala 238:43] + level_intpend_w_prior_en[5][1] <= out_priority_35 @[el2_pic_ctl.scala 239:43] + claimid_in <= level_intpend_id[5][0] @[el2_pic_ctl.scala 242:29] + selected_int_priority <= level_intpend_w_prior_en[5][0] @[el2_pic_ctl.scala 243:29] + node config_reg_we = and(waddr_config_pic_match, picm_wren_ff) @[el2_pic_ctl.scala 255:47] + node config_reg_re = and(raddr_config_pic_match, picm_rden_ff) @[el2_pic_ctl.scala 256:47] + node config_reg_in = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 257:39] + node _T_1638 = bits(config_reg_we, 0, 0) @[el2_pic_ctl.scala 258:82] + reg _T_1639 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1638 : @[Reg.scala 28:19] + _T_1639 <= config_reg_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - config_reg <= _T_1711 @[el2_pic_ctl.scala 266:37] - intpriord <= config_reg @[el2_pic_ctl.scala 267:14] - node _T_1712 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 275:31] - node _T_1713 = not(selected_int_priority) @[el2_pic_ctl.scala 275:38] - node pl_in_q = mux(_T_1712, _T_1713, selected_int_priority) @[el2_pic_ctl.scala 275:20] - reg _T_1714 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 276:47] - _T_1714 <= claimid_in @[el2_pic_ctl.scala 276:47] - io.claimid <= _T_1714 @[el2_pic_ctl.scala 276:37] - reg _T_1715 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 277:42] - _T_1715 <= pl_in_q @[el2_pic_ctl.scala 277:42] - io.pl <= _T_1715 @[el2_pic_ctl.scala 277:32] - node _T_1716 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 278:33] - node _T_1717 = not(io.meipt) @[el2_pic_ctl.scala 278:40] - node meipt_inv = mux(_T_1716, _T_1717, io.meipt) @[el2_pic_ctl.scala 278:22] - node _T_1718 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 279:36] - node _T_1719 = not(io.meicurpl) @[el2_pic_ctl.scala 279:43] - node meicurpl_inv = mux(_T_1718, _T_1719, io.meicurpl) @[el2_pic_ctl.scala 279:25] - node _T_1720 = gt(selected_int_priority, meipt_inv) @[el2_pic_ctl.scala 280:47] - node _T_1721 = gt(selected_int_priority, meicurpl_inv) @[el2_pic_ctl.scala 280:86] - node mexintpend_in = and(_T_1720, _T_1721) @[el2_pic_ctl.scala 280:60] - reg _T_1722 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 281:50] - _T_1722 <= mexintpend_in @[el2_pic_ctl.scala 281:50] - io.mexintpend <= _T_1722 @[el2_pic_ctl.scala 281:17] - node _T_1723 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 282:30] - node maxint = mux(_T_1723, UInt<1>("h00"), UInt<4>("h0f")) @[el2_pic_ctl.scala 282:19] - node mhwakeup_in = eq(pl_in_q, maxint) @[el2_pic_ctl.scala 283:29] - reg _T_1724 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 284:48] - _T_1724 <= mhwakeup_in @[el2_pic_ctl.scala 284:48] - io.mhwakeup <= _T_1724 @[el2_pic_ctl.scala 284:15] - node intpend_reg_read = and(addr_intpend_base_match, picm_rden_ff) @[el2_pic_ctl.scala 290:60] - node intpriority_reg_read = and(raddr_intpriority_base_match, picm_rden_ff) @[el2_pic_ctl.scala 291:60] - node intenable_reg_read = and(raddr_intenable_base_match, picm_rden_ff) @[el2_pic_ctl.scala 292:60] - node gw_config_reg_read = and(raddr_config_gw_base_match, picm_rden_ff) @[el2_pic_ctl.scala 293:60] - node _T_1725 = mux(UInt<1>("h00"), UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_1726 = cat(extintsrc_req_gw_31, extintsrc_req_gw_30) @[Cat.scala 29:58] - node _T_1727 = cat(_T_1726, extintsrc_req_gw_29) @[Cat.scala 29:58] - node _T_1728 = cat(_T_1727, extintsrc_req_gw_28) @[Cat.scala 29:58] - node _T_1729 = cat(_T_1728, extintsrc_req_gw_27) @[Cat.scala 29:58] - node _T_1730 = cat(_T_1729, extintsrc_req_gw_26) @[Cat.scala 29:58] - node _T_1731 = cat(_T_1730, extintsrc_req_gw_25) @[Cat.scala 29:58] - node _T_1732 = cat(_T_1731, extintsrc_req_gw_24) @[Cat.scala 29:58] - node _T_1733 = cat(_T_1732, extintsrc_req_gw_23) @[Cat.scala 29:58] - node _T_1734 = cat(_T_1733, extintsrc_req_gw_22) @[Cat.scala 29:58] - node _T_1735 = cat(_T_1734, extintsrc_req_gw_21) @[Cat.scala 29:58] - node _T_1736 = cat(_T_1735, extintsrc_req_gw_20) @[Cat.scala 29:58] - node _T_1737 = cat(_T_1736, extintsrc_req_gw_19) @[Cat.scala 29:58] - node _T_1738 = cat(_T_1737, extintsrc_req_gw_18) @[Cat.scala 29:58] - node _T_1739 = cat(_T_1738, extintsrc_req_gw_17) @[Cat.scala 29:58] - node _T_1740 = cat(_T_1739, extintsrc_req_gw_16) @[Cat.scala 29:58] - node _T_1741 = cat(_T_1740, extintsrc_req_gw_15) @[Cat.scala 29:58] - node _T_1742 = cat(_T_1741, extintsrc_req_gw_14) @[Cat.scala 29:58] - node _T_1743 = cat(_T_1742, extintsrc_req_gw_13) @[Cat.scala 29:58] - node _T_1744 = cat(_T_1743, extintsrc_req_gw_12) @[Cat.scala 29:58] - node _T_1745 = cat(_T_1744, extintsrc_req_gw_11) @[Cat.scala 29:58] - node _T_1746 = cat(_T_1745, extintsrc_req_gw_10) @[Cat.scala 29:58] - node _T_1747 = cat(_T_1746, extintsrc_req_gw_9) @[Cat.scala 29:58] - node _T_1748 = cat(_T_1747, extintsrc_req_gw_8) @[Cat.scala 29:58] - node _T_1749 = cat(_T_1748, extintsrc_req_gw_7) @[Cat.scala 29:58] - node _T_1750 = cat(_T_1749, extintsrc_req_gw_6) @[Cat.scala 29:58] - node _T_1751 = cat(_T_1750, extintsrc_req_gw_5) @[Cat.scala 29:58] - node _T_1752 = cat(_T_1751, extintsrc_req_gw_4) @[Cat.scala 29:58] - node _T_1753 = cat(_T_1752, extintsrc_req_gw_3) @[Cat.scala 29:58] - node _T_1754 = cat(_T_1753, extintsrc_req_gw_2) @[Cat.scala 29:58] - node _T_1755 = cat(_T_1754, extintsrc_req_gw_1) @[Cat.scala 29:58] - node _T_1756 = cat(_T_1755, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_1757 = cat(_T_1725, _T_1756) @[Cat.scala 29:58] - intpend_reg_extended <= _T_1757 @[el2_pic_ctl.scala 295:25] - wire intpend_rd_part_out : UInt<32>[2] @[el2_pic_ctl.scala 297:33] - node _T_1758 = bits(picm_raddr_ff, 5, 2) @[el2_pic_ctl.scala 298:98] - node _T_1759 = and(intpend_reg_read, _T_1758) @[el2_pic_ctl.scala 298:83] - node _T_1760 = eq(_T_1759, UInt<1>("h00")) @[el2_pic_ctl.scala 298:105] - node _T_1761 = bits(_T_1760, 0, 0) @[Bitwise.scala 72:15] - node _T_1762 = mux(_T_1761, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_1763 = bits(intpend_reg_extended, 31, 0) @[el2_pic_ctl.scala 298:141] - node _T_1764 = and(_T_1762, _T_1763) @[el2_pic_ctl.scala 298:119] - intpend_rd_part_out[0] <= _T_1764 @[el2_pic_ctl.scala 298:54] - node _T_1765 = bits(picm_raddr_ff, 5, 2) @[el2_pic_ctl.scala 298:98] - node _T_1766 = and(intpend_reg_read, _T_1765) @[el2_pic_ctl.scala 298:83] - node _T_1767 = eq(_T_1766, UInt<1>("h01")) @[el2_pic_ctl.scala 298:105] - node _T_1768 = bits(_T_1767, 0, 0) @[Bitwise.scala 72:15] - node _T_1769 = mux(_T_1768, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_1770 = bits(intpend_reg_extended, 63, 32) @[el2_pic_ctl.scala 298:141] - node _T_1771 = and(_T_1769, _T_1770) @[el2_pic_ctl.scala 298:119] - intpend_rd_part_out[1] <= _T_1771 @[el2_pic_ctl.scala 298:54] - node _T_1772 = or(intpend_rd_part_out[0], intpend_rd_part_out[1]) @[el2_pic_ctl.scala 299:89] - intpend_rd_out <= _T_1772 @[el2_pic_ctl.scala 299:26] - when UInt<1>("h00") : @[el2_pic_ctl.scala 300:76] - intenable_rd_out <= intenable_reg[0] @[el2_pic_ctl.scala 300:95] - skip @[el2_pic_ctl.scala 300:76] - else : @[el2_pic_ctl.scala 300:126] - intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] - skip @[el2_pic_ctl.scala 300:126] - node _T_1773 = bits(intenable_reg_re_1, 0, 0) @[el2_pic_ctl.scala 300:69] - when _T_1773 : @[el2_pic_ctl.scala 300:76] - intenable_rd_out <= intenable_reg[1] @[el2_pic_ctl.scala 300:95] - skip @[el2_pic_ctl.scala 300:76] - else : @[el2_pic_ctl.scala 300:126] - intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] - skip @[el2_pic_ctl.scala 300:126] - node _T_1774 = bits(intenable_reg_re_2, 0, 0) @[el2_pic_ctl.scala 300:69] - when _T_1774 : @[el2_pic_ctl.scala 300:76] - intenable_rd_out <= intenable_reg[2] @[el2_pic_ctl.scala 300:95] - skip @[el2_pic_ctl.scala 300:76] - else : @[el2_pic_ctl.scala 300:126] - intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] - skip @[el2_pic_ctl.scala 300:126] - node _T_1775 = bits(intenable_reg_re_3, 0, 0) @[el2_pic_ctl.scala 300:69] - when _T_1775 : @[el2_pic_ctl.scala 300:76] - intenable_rd_out <= intenable_reg[3] @[el2_pic_ctl.scala 300:95] - skip @[el2_pic_ctl.scala 300:76] - else : @[el2_pic_ctl.scala 300:126] - intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] - skip @[el2_pic_ctl.scala 300:126] - node _T_1776 = bits(intenable_reg_re_4, 0, 0) @[el2_pic_ctl.scala 300:69] - when _T_1776 : @[el2_pic_ctl.scala 300:76] - intenable_rd_out <= intenable_reg[4] @[el2_pic_ctl.scala 300:95] - skip @[el2_pic_ctl.scala 300:76] - else : @[el2_pic_ctl.scala 300:126] - intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] - skip @[el2_pic_ctl.scala 300:126] - node _T_1777 = bits(intenable_reg_re_5, 0, 0) @[el2_pic_ctl.scala 300:69] - when _T_1777 : @[el2_pic_ctl.scala 300:76] - intenable_rd_out <= intenable_reg[5] @[el2_pic_ctl.scala 300:95] - skip @[el2_pic_ctl.scala 300:76] - else : @[el2_pic_ctl.scala 300:126] - intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] - skip @[el2_pic_ctl.scala 300:126] - node _T_1778 = bits(intenable_reg_re_6, 0, 0) @[el2_pic_ctl.scala 300:69] - when _T_1778 : @[el2_pic_ctl.scala 300:76] - intenable_rd_out <= intenable_reg[6] @[el2_pic_ctl.scala 300:95] - skip @[el2_pic_ctl.scala 300:76] - else : @[el2_pic_ctl.scala 300:126] - intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] - skip @[el2_pic_ctl.scala 300:126] - node _T_1779 = bits(intenable_reg_re_7, 0, 0) @[el2_pic_ctl.scala 300:69] - when _T_1779 : @[el2_pic_ctl.scala 300:76] - intenable_rd_out <= intenable_reg[7] @[el2_pic_ctl.scala 300:95] - skip @[el2_pic_ctl.scala 300:76] - else : @[el2_pic_ctl.scala 300:126] - intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] - skip @[el2_pic_ctl.scala 300:126] - node _T_1780 = bits(intenable_reg_re_8, 0, 0) @[el2_pic_ctl.scala 300:69] - when _T_1780 : @[el2_pic_ctl.scala 300:76] - intenable_rd_out <= intenable_reg[8] @[el2_pic_ctl.scala 300:95] - skip @[el2_pic_ctl.scala 300:76] - else : @[el2_pic_ctl.scala 300:126] - intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] - skip @[el2_pic_ctl.scala 300:126] - node _T_1781 = bits(intenable_reg_re_9, 0, 0) @[el2_pic_ctl.scala 300:69] - when _T_1781 : @[el2_pic_ctl.scala 300:76] - intenable_rd_out <= intenable_reg[9] @[el2_pic_ctl.scala 300:95] - skip @[el2_pic_ctl.scala 300:76] - else : @[el2_pic_ctl.scala 300:126] - intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] - skip @[el2_pic_ctl.scala 300:126] - node _T_1782 = bits(intenable_reg_re_10, 0, 0) @[el2_pic_ctl.scala 300:69] - when _T_1782 : @[el2_pic_ctl.scala 300:76] - intenable_rd_out <= intenable_reg[10] @[el2_pic_ctl.scala 300:95] - skip @[el2_pic_ctl.scala 300:76] - else : @[el2_pic_ctl.scala 300:126] - intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] - skip @[el2_pic_ctl.scala 300:126] - node _T_1783 = bits(intenable_reg_re_11, 0, 0) @[el2_pic_ctl.scala 300:69] - when _T_1783 : @[el2_pic_ctl.scala 300:76] - intenable_rd_out <= intenable_reg[11] @[el2_pic_ctl.scala 300:95] - skip @[el2_pic_ctl.scala 300:76] - else : @[el2_pic_ctl.scala 300:126] - intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] - skip @[el2_pic_ctl.scala 300:126] - node _T_1784 = bits(intenable_reg_re_12, 0, 0) @[el2_pic_ctl.scala 300:69] - when _T_1784 : @[el2_pic_ctl.scala 300:76] - intenable_rd_out <= intenable_reg[12] @[el2_pic_ctl.scala 300:95] - skip @[el2_pic_ctl.scala 300:76] - else : @[el2_pic_ctl.scala 300:126] - intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] - skip @[el2_pic_ctl.scala 300:126] - node _T_1785 = bits(intenable_reg_re_13, 0, 0) @[el2_pic_ctl.scala 300:69] - when _T_1785 : @[el2_pic_ctl.scala 300:76] - intenable_rd_out <= intenable_reg[13] @[el2_pic_ctl.scala 300:95] - skip @[el2_pic_ctl.scala 300:76] - else : @[el2_pic_ctl.scala 300:126] - intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] - skip @[el2_pic_ctl.scala 300:126] - node _T_1786 = bits(intenable_reg_re_14, 0, 0) @[el2_pic_ctl.scala 300:69] - when _T_1786 : @[el2_pic_ctl.scala 300:76] - intenable_rd_out <= intenable_reg[14] @[el2_pic_ctl.scala 300:95] - skip @[el2_pic_ctl.scala 300:76] - else : @[el2_pic_ctl.scala 300:126] - intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] - skip @[el2_pic_ctl.scala 300:126] - node _T_1787 = bits(intenable_reg_re_15, 0, 0) @[el2_pic_ctl.scala 300:69] - when _T_1787 : @[el2_pic_ctl.scala 300:76] - intenable_rd_out <= intenable_reg[15] @[el2_pic_ctl.scala 300:95] - skip @[el2_pic_ctl.scala 300:76] - else : @[el2_pic_ctl.scala 300:126] - intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] - skip @[el2_pic_ctl.scala 300:126] - node _T_1788 = bits(intenable_reg_re_16, 0, 0) @[el2_pic_ctl.scala 300:69] - when _T_1788 : @[el2_pic_ctl.scala 300:76] - intenable_rd_out <= intenable_reg[16] @[el2_pic_ctl.scala 300:95] - skip @[el2_pic_ctl.scala 300:76] - else : @[el2_pic_ctl.scala 300:126] - intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] - skip @[el2_pic_ctl.scala 300:126] - node _T_1789 = bits(intenable_reg_re_17, 0, 0) @[el2_pic_ctl.scala 300:69] - when _T_1789 : @[el2_pic_ctl.scala 300:76] - intenable_rd_out <= intenable_reg[17] @[el2_pic_ctl.scala 300:95] - skip @[el2_pic_ctl.scala 300:76] - else : @[el2_pic_ctl.scala 300:126] - intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] - skip @[el2_pic_ctl.scala 300:126] - node _T_1790 = bits(intenable_reg_re_18, 0, 0) @[el2_pic_ctl.scala 300:69] - when _T_1790 : @[el2_pic_ctl.scala 300:76] - intenable_rd_out <= intenable_reg[18] @[el2_pic_ctl.scala 300:95] - skip @[el2_pic_ctl.scala 300:76] - else : @[el2_pic_ctl.scala 300:126] - intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] - skip @[el2_pic_ctl.scala 300:126] - node _T_1791 = bits(intenable_reg_re_19, 0, 0) @[el2_pic_ctl.scala 300:69] - when _T_1791 : @[el2_pic_ctl.scala 300:76] - intenable_rd_out <= intenable_reg[19] @[el2_pic_ctl.scala 300:95] - skip @[el2_pic_ctl.scala 300:76] - else : @[el2_pic_ctl.scala 300:126] - intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] - skip @[el2_pic_ctl.scala 300:126] - node _T_1792 = bits(intenable_reg_re_20, 0, 0) @[el2_pic_ctl.scala 300:69] - when _T_1792 : @[el2_pic_ctl.scala 300:76] - intenable_rd_out <= intenable_reg[20] @[el2_pic_ctl.scala 300:95] - skip @[el2_pic_ctl.scala 300:76] - else : @[el2_pic_ctl.scala 300:126] - intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] - skip @[el2_pic_ctl.scala 300:126] - node _T_1793 = bits(intenable_reg_re_21, 0, 0) @[el2_pic_ctl.scala 300:69] - when _T_1793 : @[el2_pic_ctl.scala 300:76] - intenable_rd_out <= intenable_reg[21] @[el2_pic_ctl.scala 300:95] - skip @[el2_pic_ctl.scala 300:76] - else : @[el2_pic_ctl.scala 300:126] - intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] - skip @[el2_pic_ctl.scala 300:126] - node _T_1794 = bits(intenable_reg_re_22, 0, 0) @[el2_pic_ctl.scala 300:69] - when _T_1794 : @[el2_pic_ctl.scala 300:76] - intenable_rd_out <= intenable_reg[22] @[el2_pic_ctl.scala 300:95] - skip @[el2_pic_ctl.scala 300:76] - else : @[el2_pic_ctl.scala 300:126] - intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] - skip @[el2_pic_ctl.scala 300:126] - node _T_1795 = bits(intenable_reg_re_23, 0, 0) @[el2_pic_ctl.scala 300:69] - when _T_1795 : @[el2_pic_ctl.scala 300:76] - intenable_rd_out <= intenable_reg[23] @[el2_pic_ctl.scala 300:95] - skip @[el2_pic_ctl.scala 300:76] - else : @[el2_pic_ctl.scala 300:126] - intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] - skip @[el2_pic_ctl.scala 300:126] - node _T_1796 = bits(intenable_reg_re_24, 0, 0) @[el2_pic_ctl.scala 300:69] - when _T_1796 : @[el2_pic_ctl.scala 300:76] - intenable_rd_out <= intenable_reg[24] @[el2_pic_ctl.scala 300:95] - skip @[el2_pic_ctl.scala 300:76] - else : @[el2_pic_ctl.scala 300:126] - intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] - skip @[el2_pic_ctl.scala 300:126] - node _T_1797 = bits(intenable_reg_re_25, 0, 0) @[el2_pic_ctl.scala 300:69] - when _T_1797 : @[el2_pic_ctl.scala 300:76] - intenable_rd_out <= intenable_reg[25] @[el2_pic_ctl.scala 300:95] - skip @[el2_pic_ctl.scala 300:76] - else : @[el2_pic_ctl.scala 300:126] - intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] - skip @[el2_pic_ctl.scala 300:126] - node _T_1798 = bits(intenable_reg_re_26, 0, 0) @[el2_pic_ctl.scala 300:69] - when _T_1798 : @[el2_pic_ctl.scala 300:76] - intenable_rd_out <= intenable_reg[26] @[el2_pic_ctl.scala 300:95] - skip @[el2_pic_ctl.scala 300:76] - else : @[el2_pic_ctl.scala 300:126] - intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] - skip @[el2_pic_ctl.scala 300:126] - node _T_1799 = bits(intenable_reg_re_27, 0, 0) @[el2_pic_ctl.scala 300:69] - when _T_1799 : @[el2_pic_ctl.scala 300:76] - intenable_rd_out <= intenable_reg[27] @[el2_pic_ctl.scala 300:95] - skip @[el2_pic_ctl.scala 300:76] - else : @[el2_pic_ctl.scala 300:126] - intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] - skip @[el2_pic_ctl.scala 300:126] - node _T_1800 = bits(intenable_reg_re_28, 0, 0) @[el2_pic_ctl.scala 300:69] - when _T_1800 : @[el2_pic_ctl.scala 300:76] - intenable_rd_out <= intenable_reg[28] @[el2_pic_ctl.scala 300:95] - skip @[el2_pic_ctl.scala 300:76] - else : @[el2_pic_ctl.scala 300:126] - intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] - skip @[el2_pic_ctl.scala 300:126] - node _T_1801 = bits(intenable_reg_re_29, 0, 0) @[el2_pic_ctl.scala 300:69] - when _T_1801 : @[el2_pic_ctl.scala 300:76] - intenable_rd_out <= intenable_reg[29] @[el2_pic_ctl.scala 300:95] - skip @[el2_pic_ctl.scala 300:76] - else : @[el2_pic_ctl.scala 300:126] - intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] - skip @[el2_pic_ctl.scala 300:126] - node _T_1802 = bits(intenable_reg_re_30, 0, 0) @[el2_pic_ctl.scala 300:69] - when _T_1802 : @[el2_pic_ctl.scala 300:76] - intenable_rd_out <= intenable_reg[30] @[el2_pic_ctl.scala 300:95] - skip @[el2_pic_ctl.scala 300:76] - else : @[el2_pic_ctl.scala 300:126] - intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] - skip @[el2_pic_ctl.scala 300:126] - node _T_1803 = bits(intenable_reg_re_31, 0, 0) @[el2_pic_ctl.scala 300:69] - when _T_1803 : @[el2_pic_ctl.scala 300:76] - intenable_rd_out <= intenable_reg[31] @[el2_pic_ctl.scala 300:95] - skip @[el2_pic_ctl.scala 300:76] - else : @[el2_pic_ctl.scala 300:126] - intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] - skip @[el2_pic_ctl.scala 300:126] - node _T_1804 = bits(intpriority_reg_re_1, 0, 0) @[el2_pic_ctl.scala 302:102] - node _T_1805 = bits(intpriority_reg_re_2, 0, 0) @[el2_pic_ctl.scala 302:102] - node _T_1806 = bits(intpriority_reg_re_3, 0, 0) @[el2_pic_ctl.scala 302:102] - node _T_1807 = bits(intpriority_reg_re_4, 0, 0) @[el2_pic_ctl.scala 302:102] - node _T_1808 = bits(intpriority_reg_re_5, 0, 0) @[el2_pic_ctl.scala 302:102] - node _T_1809 = bits(intpriority_reg_re_6, 0, 0) @[el2_pic_ctl.scala 302:102] - node _T_1810 = bits(intpriority_reg_re_7, 0, 0) @[el2_pic_ctl.scala 302:102] - node _T_1811 = bits(intpriority_reg_re_8, 0, 0) @[el2_pic_ctl.scala 302:102] - node _T_1812 = bits(intpriority_reg_re_9, 0, 0) @[el2_pic_ctl.scala 302:102] - node _T_1813 = bits(intpriority_reg_re_10, 0, 0) @[el2_pic_ctl.scala 302:102] - node _T_1814 = bits(intpriority_reg_re_11, 0, 0) @[el2_pic_ctl.scala 302:102] - node _T_1815 = bits(intpriority_reg_re_12, 0, 0) @[el2_pic_ctl.scala 302:102] - node _T_1816 = bits(intpriority_reg_re_13, 0, 0) @[el2_pic_ctl.scala 302:102] - node _T_1817 = bits(intpriority_reg_re_14, 0, 0) @[el2_pic_ctl.scala 302:102] - node _T_1818 = bits(intpriority_reg_re_15, 0, 0) @[el2_pic_ctl.scala 302:102] - node _T_1819 = bits(intpriority_reg_re_16, 0, 0) @[el2_pic_ctl.scala 302:102] - node _T_1820 = bits(intpriority_reg_re_17, 0, 0) @[el2_pic_ctl.scala 302:102] - node _T_1821 = bits(intpriority_reg_re_18, 0, 0) @[el2_pic_ctl.scala 302:102] - node _T_1822 = bits(intpriority_reg_re_19, 0, 0) @[el2_pic_ctl.scala 302:102] - node _T_1823 = bits(intpriority_reg_re_20, 0, 0) @[el2_pic_ctl.scala 302:102] - node _T_1824 = bits(intpriority_reg_re_21, 0, 0) @[el2_pic_ctl.scala 302:102] - node _T_1825 = bits(intpriority_reg_re_22, 0, 0) @[el2_pic_ctl.scala 302:102] - node _T_1826 = bits(intpriority_reg_re_23, 0, 0) @[el2_pic_ctl.scala 302:102] - node _T_1827 = bits(intpriority_reg_re_24, 0, 0) @[el2_pic_ctl.scala 302:102] - node _T_1828 = bits(intpriority_reg_re_25, 0, 0) @[el2_pic_ctl.scala 302:102] - node _T_1829 = bits(intpriority_reg_re_26, 0, 0) @[el2_pic_ctl.scala 302:102] - node _T_1830 = bits(intpriority_reg_re_27, 0, 0) @[el2_pic_ctl.scala 302:102] - node _T_1831 = bits(intpriority_reg_re_28, 0, 0) @[el2_pic_ctl.scala 302:102] - node _T_1832 = bits(intpriority_reg_re_29, 0, 0) @[el2_pic_ctl.scala 302:102] - node _T_1833 = bits(intpriority_reg_re_30, 0, 0) @[el2_pic_ctl.scala 302:102] - node _T_1834 = bits(intpriority_reg_re_31, 0, 0) @[el2_pic_ctl.scala 302:102] - node _T_1835 = mux(_T_1834, intpriority_reg[31], UInt<1>("h00")) @[Mux.scala 98:16] - node _T_1836 = mux(_T_1833, intpriority_reg[30], _T_1835) @[Mux.scala 98:16] - node _T_1837 = mux(_T_1832, intpriority_reg[29], _T_1836) @[Mux.scala 98:16] - node _T_1838 = mux(_T_1831, intpriority_reg[28], _T_1837) @[Mux.scala 98:16] - node _T_1839 = mux(_T_1830, intpriority_reg[27], _T_1838) @[Mux.scala 98:16] - node _T_1840 = mux(_T_1829, intpriority_reg[26], _T_1839) @[Mux.scala 98:16] - node _T_1841 = mux(_T_1828, intpriority_reg[25], _T_1840) @[Mux.scala 98:16] - node _T_1842 = mux(_T_1827, intpriority_reg[24], _T_1841) @[Mux.scala 98:16] - node _T_1843 = mux(_T_1826, intpriority_reg[23], _T_1842) @[Mux.scala 98:16] - node _T_1844 = mux(_T_1825, intpriority_reg[22], _T_1843) @[Mux.scala 98:16] - node _T_1845 = mux(_T_1824, intpriority_reg[21], _T_1844) @[Mux.scala 98:16] - node _T_1846 = mux(_T_1823, intpriority_reg[20], _T_1845) @[Mux.scala 98:16] - node _T_1847 = mux(_T_1822, intpriority_reg[19], _T_1846) @[Mux.scala 98:16] - node _T_1848 = mux(_T_1821, intpriority_reg[18], _T_1847) @[Mux.scala 98:16] - node _T_1849 = mux(_T_1820, intpriority_reg[17], _T_1848) @[Mux.scala 98:16] - node _T_1850 = mux(_T_1819, intpriority_reg[16], _T_1849) @[Mux.scala 98:16] - node _T_1851 = mux(_T_1818, intpriority_reg[15], _T_1850) @[Mux.scala 98:16] - node _T_1852 = mux(_T_1817, intpriority_reg[14], _T_1851) @[Mux.scala 98:16] - node _T_1853 = mux(_T_1816, intpriority_reg[13], _T_1852) @[Mux.scala 98:16] - node _T_1854 = mux(_T_1815, intpriority_reg[12], _T_1853) @[Mux.scala 98:16] - node _T_1855 = mux(_T_1814, intpriority_reg[11], _T_1854) @[Mux.scala 98:16] - node _T_1856 = mux(_T_1813, intpriority_reg[10], _T_1855) @[Mux.scala 98:16] - node _T_1857 = mux(_T_1812, intpriority_reg[9], _T_1856) @[Mux.scala 98:16] - node _T_1858 = mux(_T_1811, intpriority_reg[8], _T_1857) @[Mux.scala 98:16] - node _T_1859 = mux(_T_1810, intpriority_reg[7], _T_1858) @[Mux.scala 98:16] - node _T_1860 = mux(_T_1809, intpriority_reg[6], _T_1859) @[Mux.scala 98:16] - node _T_1861 = mux(_T_1808, intpriority_reg[5], _T_1860) @[Mux.scala 98:16] - node _T_1862 = mux(_T_1807, intpriority_reg[4], _T_1861) @[Mux.scala 98:16] - node _T_1863 = mux(_T_1806, intpriority_reg[3], _T_1862) @[Mux.scala 98:16] - node _T_1864 = mux(_T_1805, intpriority_reg[2], _T_1863) @[Mux.scala 98:16] - node _T_1865 = mux(_T_1804, intpriority_reg[1], _T_1864) @[Mux.scala 98:16] - node intpriority_rd_out = mux(UInt<1>("h00"), intpriority_reg[0], _T_1865) @[Mux.scala 98:16] - node _T_1866 = bits(gw_config_reg_re_1, 0, 0) @[el2_pic_ctl.scala 303:100] - node _T_1867 = bits(gw_config_reg_re_2, 0, 0) @[el2_pic_ctl.scala 303:100] - node _T_1868 = bits(gw_config_reg_re_3, 0, 0) @[el2_pic_ctl.scala 303:100] - node _T_1869 = bits(gw_config_reg_re_4, 0, 0) @[el2_pic_ctl.scala 303:100] - node _T_1870 = bits(gw_config_reg_re_5, 0, 0) @[el2_pic_ctl.scala 303:100] - node _T_1871 = bits(gw_config_reg_re_6, 0, 0) @[el2_pic_ctl.scala 303:100] - node _T_1872 = bits(gw_config_reg_re_7, 0, 0) @[el2_pic_ctl.scala 303:100] - node _T_1873 = bits(gw_config_reg_re_8, 0, 0) @[el2_pic_ctl.scala 303:100] - node _T_1874 = bits(gw_config_reg_re_9, 0, 0) @[el2_pic_ctl.scala 303:100] - node _T_1875 = bits(gw_config_reg_re_10, 0, 0) @[el2_pic_ctl.scala 303:100] - node _T_1876 = bits(gw_config_reg_re_11, 0, 0) @[el2_pic_ctl.scala 303:100] - node _T_1877 = bits(gw_config_reg_re_12, 0, 0) @[el2_pic_ctl.scala 303:100] - node _T_1878 = bits(gw_config_reg_re_13, 0, 0) @[el2_pic_ctl.scala 303:100] - node _T_1879 = bits(gw_config_reg_re_14, 0, 0) @[el2_pic_ctl.scala 303:100] - node _T_1880 = bits(gw_config_reg_re_15, 0, 0) @[el2_pic_ctl.scala 303:100] - node _T_1881 = bits(gw_config_reg_re_16, 0, 0) @[el2_pic_ctl.scala 303:100] - node _T_1882 = bits(gw_config_reg_re_17, 0, 0) @[el2_pic_ctl.scala 303:100] - node _T_1883 = bits(gw_config_reg_re_18, 0, 0) @[el2_pic_ctl.scala 303:100] - node _T_1884 = bits(gw_config_reg_re_19, 0, 0) @[el2_pic_ctl.scala 303:100] - node _T_1885 = bits(gw_config_reg_re_20, 0, 0) @[el2_pic_ctl.scala 303:100] - node _T_1886 = bits(gw_config_reg_re_21, 0, 0) @[el2_pic_ctl.scala 303:100] - node _T_1887 = bits(gw_config_reg_re_22, 0, 0) @[el2_pic_ctl.scala 303:100] - node _T_1888 = bits(gw_config_reg_re_23, 0, 0) @[el2_pic_ctl.scala 303:100] - node _T_1889 = bits(gw_config_reg_re_24, 0, 0) @[el2_pic_ctl.scala 303:100] - node _T_1890 = bits(gw_config_reg_re_25, 0, 0) @[el2_pic_ctl.scala 303:100] - node _T_1891 = bits(gw_config_reg_re_26, 0, 0) @[el2_pic_ctl.scala 303:100] - node _T_1892 = bits(gw_config_reg_re_27, 0, 0) @[el2_pic_ctl.scala 303:100] - node _T_1893 = bits(gw_config_reg_re_28, 0, 0) @[el2_pic_ctl.scala 303:100] - node _T_1894 = bits(gw_config_reg_re_29, 0, 0) @[el2_pic_ctl.scala 303:100] - node _T_1895 = bits(gw_config_reg_re_30, 0, 0) @[el2_pic_ctl.scala 303:100] - node _T_1896 = bits(gw_config_reg_re_31, 0, 0) @[el2_pic_ctl.scala 303:100] - node _T_1897 = mux(_T_1896, gw_config_reg[31], UInt<1>("h00")) @[Mux.scala 98:16] - node _T_1898 = mux(_T_1895, gw_config_reg[30], _T_1897) @[Mux.scala 98:16] - node _T_1899 = mux(_T_1894, gw_config_reg[29], _T_1898) @[Mux.scala 98:16] - node _T_1900 = mux(_T_1893, gw_config_reg[28], _T_1899) @[Mux.scala 98:16] - node _T_1901 = mux(_T_1892, gw_config_reg[27], _T_1900) @[Mux.scala 98:16] - node _T_1902 = mux(_T_1891, gw_config_reg[26], _T_1901) @[Mux.scala 98:16] - node _T_1903 = mux(_T_1890, gw_config_reg[25], _T_1902) @[Mux.scala 98:16] - node _T_1904 = mux(_T_1889, gw_config_reg[24], _T_1903) @[Mux.scala 98:16] - node _T_1905 = mux(_T_1888, gw_config_reg[23], _T_1904) @[Mux.scala 98:16] - node _T_1906 = mux(_T_1887, gw_config_reg[22], _T_1905) @[Mux.scala 98:16] - node _T_1907 = mux(_T_1886, gw_config_reg[21], _T_1906) @[Mux.scala 98:16] - node _T_1908 = mux(_T_1885, gw_config_reg[20], _T_1907) @[Mux.scala 98:16] - node _T_1909 = mux(_T_1884, gw_config_reg[19], _T_1908) @[Mux.scala 98:16] - node _T_1910 = mux(_T_1883, gw_config_reg[18], _T_1909) @[Mux.scala 98:16] - node _T_1911 = mux(_T_1882, gw_config_reg[17], _T_1910) @[Mux.scala 98:16] - node _T_1912 = mux(_T_1881, gw_config_reg[16], _T_1911) @[Mux.scala 98:16] - node _T_1913 = mux(_T_1880, gw_config_reg[15], _T_1912) @[Mux.scala 98:16] - node _T_1914 = mux(_T_1879, gw_config_reg[14], _T_1913) @[Mux.scala 98:16] - node _T_1915 = mux(_T_1878, gw_config_reg[13], _T_1914) @[Mux.scala 98:16] - node _T_1916 = mux(_T_1877, gw_config_reg[12], _T_1915) @[Mux.scala 98:16] - node _T_1917 = mux(_T_1876, gw_config_reg[11], _T_1916) @[Mux.scala 98:16] - node _T_1918 = mux(_T_1875, gw_config_reg[10], _T_1917) @[Mux.scala 98:16] - node _T_1919 = mux(_T_1874, gw_config_reg[9], _T_1918) @[Mux.scala 98:16] - node _T_1920 = mux(_T_1873, gw_config_reg[8], _T_1919) @[Mux.scala 98:16] - node _T_1921 = mux(_T_1872, gw_config_reg[7], _T_1920) @[Mux.scala 98:16] - node _T_1922 = mux(_T_1871, gw_config_reg[6], _T_1921) @[Mux.scala 98:16] - node _T_1923 = mux(_T_1870, gw_config_reg[5], _T_1922) @[Mux.scala 98:16] - node _T_1924 = mux(_T_1869, gw_config_reg[4], _T_1923) @[Mux.scala 98:16] - node _T_1925 = mux(_T_1868, gw_config_reg[3], _T_1924) @[Mux.scala 98:16] - node _T_1926 = mux(_T_1867, gw_config_reg[2], _T_1925) @[Mux.scala 98:16] - node _T_1927 = mux(_T_1866, gw_config_reg[1], _T_1926) @[Mux.scala 98:16] - node gw_config_rd_out = mux(UInt<1>("h00"), gw_config_reg[0], _T_1927) @[Mux.scala 98:16] + config_reg <= _T_1639 @[el2_pic_ctl.scala 258:37] + intpriord <= config_reg @[el2_pic_ctl.scala 259:14] + node _T_1640 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 267:31] + node _T_1641 = not(selected_int_priority) @[el2_pic_ctl.scala 267:38] + node pl_in_q = mux(_T_1640, _T_1641, selected_int_priority) @[el2_pic_ctl.scala 267:20] + reg _T_1642 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 268:47] + _T_1642 <= claimid_in @[el2_pic_ctl.scala 268:47] + io.claimid <= _T_1642 @[el2_pic_ctl.scala 268:37] + reg _T_1643 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 269:42] + _T_1643 <= pl_in_q @[el2_pic_ctl.scala 269:42] + io.pl <= _T_1643 @[el2_pic_ctl.scala 269:32] + node _T_1644 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 270:33] + node _T_1645 = not(io.meipt) @[el2_pic_ctl.scala 270:40] + node meipt_inv = mux(_T_1644, _T_1645, io.meipt) @[el2_pic_ctl.scala 270:22] + node _T_1646 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 271:36] + node _T_1647 = not(io.meicurpl) @[el2_pic_ctl.scala 271:43] + node meicurpl_inv = mux(_T_1646, _T_1647, io.meicurpl) @[el2_pic_ctl.scala 271:25] + node _T_1648 = gt(selected_int_priority, meipt_inv) @[el2_pic_ctl.scala 272:47] + node _T_1649 = gt(selected_int_priority, meicurpl_inv) @[el2_pic_ctl.scala 272:86] + node mexintpend_in = and(_T_1648, _T_1649) @[el2_pic_ctl.scala 272:60] + reg _T_1650 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 273:50] + _T_1650 <= mexintpend_in @[el2_pic_ctl.scala 273:50] + io.mexintpend <= _T_1650 @[el2_pic_ctl.scala 273:17] + node _T_1651 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 274:30] + node maxint = mux(_T_1651, UInt<1>("h00"), UInt<4>("h0f")) @[el2_pic_ctl.scala 274:19] + node mhwakeup_in = eq(pl_in_q, maxint) @[el2_pic_ctl.scala 275:29] + reg _T_1652 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 276:48] + _T_1652 <= mhwakeup_in @[el2_pic_ctl.scala 276:48] + io.mhwakeup <= _T_1652 @[el2_pic_ctl.scala 276:15] + node intpend_reg_read = and(addr_intpend_base_match, picm_rden_ff) @[el2_pic_ctl.scala 282:60] + node intpriority_reg_read = and(raddr_intpriority_base_match, picm_rden_ff) @[el2_pic_ctl.scala 283:60] + node intenable_reg_read = and(raddr_intenable_base_match, picm_rden_ff) @[el2_pic_ctl.scala 284:60] + node gw_config_reg_read = and(raddr_config_gw_base_match, picm_rden_ff) @[el2_pic_ctl.scala 285:60] + node _T_1653 = mux(UInt<1>("h00"), UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_1654 = cat(extintsrc_req_gw_31, extintsrc_req_gw_30) @[Cat.scala 29:58] + node _T_1655 = cat(_T_1654, extintsrc_req_gw_29) @[Cat.scala 29:58] + node _T_1656 = cat(_T_1655, extintsrc_req_gw_28) @[Cat.scala 29:58] + node _T_1657 = cat(_T_1656, extintsrc_req_gw_27) @[Cat.scala 29:58] + node _T_1658 = cat(_T_1657, extintsrc_req_gw_26) @[Cat.scala 29:58] + node _T_1659 = cat(_T_1658, extintsrc_req_gw_25) @[Cat.scala 29:58] + node _T_1660 = cat(_T_1659, extintsrc_req_gw_24) @[Cat.scala 29:58] + node _T_1661 = cat(_T_1660, extintsrc_req_gw_23) @[Cat.scala 29:58] + node _T_1662 = cat(_T_1661, extintsrc_req_gw_22) @[Cat.scala 29:58] + node _T_1663 = cat(_T_1662, extintsrc_req_gw_21) @[Cat.scala 29:58] + node _T_1664 = cat(_T_1663, extintsrc_req_gw_20) @[Cat.scala 29:58] + node _T_1665 = cat(_T_1664, extintsrc_req_gw_19) @[Cat.scala 29:58] + node _T_1666 = cat(_T_1665, extintsrc_req_gw_18) @[Cat.scala 29:58] + node _T_1667 = cat(_T_1666, extintsrc_req_gw_17) @[Cat.scala 29:58] + node _T_1668 = cat(_T_1667, extintsrc_req_gw_16) @[Cat.scala 29:58] + node _T_1669 = cat(_T_1668, extintsrc_req_gw_15) @[Cat.scala 29:58] + node _T_1670 = cat(_T_1669, extintsrc_req_gw_14) @[Cat.scala 29:58] + node _T_1671 = cat(_T_1670, extintsrc_req_gw_13) @[Cat.scala 29:58] + node _T_1672 = cat(_T_1671, extintsrc_req_gw_12) @[Cat.scala 29:58] + node _T_1673 = cat(_T_1672, extintsrc_req_gw_11) @[Cat.scala 29:58] + node _T_1674 = cat(_T_1673, extintsrc_req_gw_10) @[Cat.scala 29:58] + node _T_1675 = cat(_T_1674, extintsrc_req_gw_9) @[Cat.scala 29:58] + node _T_1676 = cat(_T_1675, extintsrc_req_gw_8) @[Cat.scala 29:58] + node _T_1677 = cat(_T_1676, extintsrc_req_gw_7) @[Cat.scala 29:58] + node _T_1678 = cat(_T_1677, extintsrc_req_gw_6) @[Cat.scala 29:58] + node _T_1679 = cat(_T_1678, extintsrc_req_gw_5) @[Cat.scala 29:58] + node _T_1680 = cat(_T_1679, extintsrc_req_gw_4) @[Cat.scala 29:58] + node _T_1681 = cat(_T_1680, extintsrc_req_gw_3) @[Cat.scala 29:58] + node _T_1682 = cat(_T_1681, extintsrc_req_gw_2) @[Cat.scala 29:58] + node _T_1683 = cat(_T_1682, extintsrc_req_gw_1) @[Cat.scala 29:58] + node _T_1684 = cat(_T_1683, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_1685 = cat(_T_1653, _T_1684) @[Cat.scala 29:58] + intpend_reg_extended <= _T_1685 @[el2_pic_ctl.scala 287:25] + wire intpend_rd_part_out : UInt<32>[2] @[el2_pic_ctl.scala 289:33] + node _T_1686 = bits(picm_raddr_ff, 5, 2) @[el2_pic_ctl.scala 290:98] + node _T_1687 = and(intpend_reg_read, _T_1686) @[el2_pic_ctl.scala 290:83] + node _T_1688 = eq(_T_1687, UInt<1>("h00")) @[el2_pic_ctl.scala 290:105] + node _T_1689 = bits(_T_1688, 0, 0) @[Bitwise.scala 72:15] + node _T_1690 = mux(_T_1689, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_1691 = bits(intpend_reg_extended, 31, 0) @[el2_pic_ctl.scala 290:141] + node _T_1692 = and(_T_1690, _T_1691) @[el2_pic_ctl.scala 290:119] + intpend_rd_part_out[0] <= _T_1692 @[el2_pic_ctl.scala 290:54] + node _T_1693 = bits(picm_raddr_ff, 5, 2) @[el2_pic_ctl.scala 290:98] + node _T_1694 = and(intpend_reg_read, _T_1693) @[el2_pic_ctl.scala 290:83] + node _T_1695 = eq(_T_1694, UInt<1>("h01")) @[el2_pic_ctl.scala 290:105] + node _T_1696 = bits(_T_1695, 0, 0) @[Bitwise.scala 72:15] + node _T_1697 = mux(_T_1696, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_1698 = bits(intpend_reg_extended, 63, 32) @[el2_pic_ctl.scala 290:141] + node _T_1699 = and(_T_1697, _T_1698) @[el2_pic_ctl.scala 290:119] + intpend_rd_part_out[1] <= _T_1699 @[el2_pic_ctl.scala 290:54] + node _T_1700 = or(intpend_rd_part_out[0], intpend_rd_part_out[1]) @[el2_pic_ctl.scala 291:89] + intpend_rd_out <= _T_1700 @[el2_pic_ctl.scala 291:26] + when UInt<1>("h00") : @[el2_pic_ctl.scala 292:76] + intenable_rd_out <= intenable_reg[0] @[el2_pic_ctl.scala 292:95] + skip @[el2_pic_ctl.scala 292:76] + else : @[el2_pic_ctl.scala 292:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 292:144] + skip @[el2_pic_ctl.scala 292:126] + node _T_1701 = bits(intenable_reg_re_1, 0, 0) @[el2_pic_ctl.scala 292:69] + when _T_1701 : @[el2_pic_ctl.scala 292:76] + intenable_rd_out <= intenable_reg[1] @[el2_pic_ctl.scala 292:95] + skip @[el2_pic_ctl.scala 292:76] + else : @[el2_pic_ctl.scala 292:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 292:144] + skip @[el2_pic_ctl.scala 292:126] + node _T_1702 = bits(intenable_reg_re_2, 0, 0) @[el2_pic_ctl.scala 292:69] + when _T_1702 : @[el2_pic_ctl.scala 292:76] + intenable_rd_out <= intenable_reg[2] @[el2_pic_ctl.scala 292:95] + skip @[el2_pic_ctl.scala 292:76] + else : @[el2_pic_ctl.scala 292:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 292:144] + skip @[el2_pic_ctl.scala 292:126] + node _T_1703 = bits(intenable_reg_re_3, 0, 0) @[el2_pic_ctl.scala 292:69] + when _T_1703 : @[el2_pic_ctl.scala 292:76] + intenable_rd_out <= intenable_reg[3] @[el2_pic_ctl.scala 292:95] + skip @[el2_pic_ctl.scala 292:76] + else : @[el2_pic_ctl.scala 292:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 292:144] + skip @[el2_pic_ctl.scala 292:126] + node _T_1704 = bits(intenable_reg_re_4, 0, 0) @[el2_pic_ctl.scala 292:69] + when _T_1704 : @[el2_pic_ctl.scala 292:76] + intenable_rd_out <= intenable_reg[4] @[el2_pic_ctl.scala 292:95] + skip @[el2_pic_ctl.scala 292:76] + else : @[el2_pic_ctl.scala 292:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 292:144] + skip @[el2_pic_ctl.scala 292:126] + node _T_1705 = bits(intenable_reg_re_5, 0, 0) @[el2_pic_ctl.scala 292:69] + when _T_1705 : @[el2_pic_ctl.scala 292:76] + intenable_rd_out <= intenable_reg[5] @[el2_pic_ctl.scala 292:95] + skip @[el2_pic_ctl.scala 292:76] + else : @[el2_pic_ctl.scala 292:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 292:144] + skip @[el2_pic_ctl.scala 292:126] + node _T_1706 = bits(intenable_reg_re_6, 0, 0) @[el2_pic_ctl.scala 292:69] + when _T_1706 : @[el2_pic_ctl.scala 292:76] + intenable_rd_out <= intenable_reg[6] @[el2_pic_ctl.scala 292:95] + skip @[el2_pic_ctl.scala 292:76] + else : @[el2_pic_ctl.scala 292:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 292:144] + skip @[el2_pic_ctl.scala 292:126] + node _T_1707 = bits(intenable_reg_re_7, 0, 0) @[el2_pic_ctl.scala 292:69] + when _T_1707 : @[el2_pic_ctl.scala 292:76] + intenable_rd_out <= intenable_reg[7] @[el2_pic_ctl.scala 292:95] + skip @[el2_pic_ctl.scala 292:76] + else : @[el2_pic_ctl.scala 292:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 292:144] + skip @[el2_pic_ctl.scala 292:126] + node _T_1708 = bits(intenable_reg_re_8, 0, 0) @[el2_pic_ctl.scala 292:69] + when _T_1708 : @[el2_pic_ctl.scala 292:76] + intenable_rd_out <= intenable_reg[8] @[el2_pic_ctl.scala 292:95] + skip @[el2_pic_ctl.scala 292:76] + else : @[el2_pic_ctl.scala 292:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 292:144] + skip @[el2_pic_ctl.scala 292:126] + node _T_1709 = bits(intenable_reg_re_9, 0, 0) @[el2_pic_ctl.scala 292:69] + when _T_1709 : @[el2_pic_ctl.scala 292:76] + intenable_rd_out <= intenable_reg[9] @[el2_pic_ctl.scala 292:95] + skip @[el2_pic_ctl.scala 292:76] + else : @[el2_pic_ctl.scala 292:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 292:144] + skip @[el2_pic_ctl.scala 292:126] + node _T_1710 = bits(intenable_reg_re_10, 0, 0) @[el2_pic_ctl.scala 292:69] + when _T_1710 : @[el2_pic_ctl.scala 292:76] + intenable_rd_out <= intenable_reg[10] @[el2_pic_ctl.scala 292:95] + skip @[el2_pic_ctl.scala 292:76] + else : @[el2_pic_ctl.scala 292:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 292:144] + skip @[el2_pic_ctl.scala 292:126] + node _T_1711 = bits(intenable_reg_re_11, 0, 0) @[el2_pic_ctl.scala 292:69] + when _T_1711 : @[el2_pic_ctl.scala 292:76] + intenable_rd_out <= intenable_reg[11] @[el2_pic_ctl.scala 292:95] + skip @[el2_pic_ctl.scala 292:76] + else : @[el2_pic_ctl.scala 292:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 292:144] + skip @[el2_pic_ctl.scala 292:126] + node _T_1712 = bits(intenable_reg_re_12, 0, 0) @[el2_pic_ctl.scala 292:69] + when _T_1712 : @[el2_pic_ctl.scala 292:76] + intenable_rd_out <= intenable_reg[12] @[el2_pic_ctl.scala 292:95] + skip @[el2_pic_ctl.scala 292:76] + else : @[el2_pic_ctl.scala 292:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 292:144] + skip @[el2_pic_ctl.scala 292:126] + node _T_1713 = bits(intenable_reg_re_13, 0, 0) @[el2_pic_ctl.scala 292:69] + when _T_1713 : @[el2_pic_ctl.scala 292:76] + intenable_rd_out <= intenable_reg[13] @[el2_pic_ctl.scala 292:95] + skip @[el2_pic_ctl.scala 292:76] + else : @[el2_pic_ctl.scala 292:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 292:144] + skip @[el2_pic_ctl.scala 292:126] + node _T_1714 = bits(intenable_reg_re_14, 0, 0) @[el2_pic_ctl.scala 292:69] + when _T_1714 : @[el2_pic_ctl.scala 292:76] + intenable_rd_out <= intenable_reg[14] @[el2_pic_ctl.scala 292:95] + skip @[el2_pic_ctl.scala 292:76] + else : @[el2_pic_ctl.scala 292:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 292:144] + skip @[el2_pic_ctl.scala 292:126] + node _T_1715 = bits(intenable_reg_re_15, 0, 0) @[el2_pic_ctl.scala 292:69] + when _T_1715 : @[el2_pic_ctl.scala 292:76] + intenable_rd_out <= intenable_reg[15] @[el2_pic_ctl.scala 292:95] + skip @[el2_pic_ctl.scala 292:76] + else : @[el2_pic_ctl.scala 292:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 292:144] + skip @[el2_pic_ctl.scala 292:126] + node _T_1716 = bits(intenable_reg_re_16, 0, 0) @[el2_pic_ctl.scala 292:69] + when _T_1716 : @[el2_pic_ctl.scala 292:76] + intenable_rd_out <= intenable_reg[16] @[el2_pic_ctl.scala 292:95] + skip @[el2_pic_ctl.scala 292:76] + else : @[el2_pic_ctl.scala 292:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 292:144] + skip @[el2_pic_ctl.scala 292:126] + node _T_1717 = bits(intenable_reg_re_17, 0, 0) @[el2_pic_ctl.scala 292:69] + when _T_1717 : @[el2_pic_ctl.scala 292:76] + intenable_rd_out <= intenable_reg[17] @[el2_pic_ctl.scala 292:95] + skip @[el2_pic_ctl.scala 292:76] + else : @[el2_pic_ctl.scala 292:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 292:144] + skip @[el2_pic_ctl.scala 292:126] + node _T_1718 = bits(intenable_reg_re_18, 0, 0) @[el2_pic_ctl.scala 292:69] + when _T_1718 : @[el2_pic_ctl.scala 292:76] + intenable_rd_out <= intenable_reg[18] @[el2_pic_ctl.scala 292:95] + skip @[el2_pic_ctl.scala 292:76] + else : @[el2_pic_ctl.scala 292:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 292:144] + skip @[el2_pic_ctl.scala 292:126] + node _T_1719 = bits(intenable_reg_re_19, 0, 0) @[el2_pic_ctl.scala 292:69] + when _T_1719 : @[el2_pic_ctl.scala 292:76] + intenable_rd_out <= intenable_reg[19] @[el2_pic_ctl.scala 292:95] + skip @[el2_pic_ctl.scala 292:76] + else : @[el2_pic_ctl.scala 292:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 292:144] + skip @[el2_pic_ctl.scala 292:126] + node _T_1720 = bits(intenable_reg_re_20, 0, 0) @[el2_pic_ctl.scala 292:69] + when _T_1720 : @[el2_pic_ctl.scala 292:76] + intenable_rd_out <= intenable_reg[20] @[el2_pic_ctl.scala 292:95] + skip @[el2_pic_ctl.scala 292:76] + else : @[el2_pic_ctl.scala 292:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 292:144] + skip @[el2_pic_ctl.scala 292:126] + node _T_1721 = bits(intenable_reg_re_21, 0, 0) @[el2_pic_ctl.scala 292:69] + when _T_1721 : @[el2_pic_ctl.scala 292:76] + intenable_rd_out <= intenable_reg[21] @[el2_pic_ctl.scala 292:95] + skip @[el2_pic_ctl.scala 292:76] + else : @[el2_pic_ctl.scala 292:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 292:144] + skip @[el2_pic_ctl.scala 292:126] + node _T_1722 = bits(intenable_reg_re_22, 0, 0) @[el2_pic_ctl.scala 292:69] + when _T_1722 : @[el2_pic_ctl.scala 292:76] + intenable_rd_out <= intenable_reg[22] @[el2_pic_ctl.scala 292:95] + skip @[el2_pic_ctl.scala 292:76] + else : @[el2_pic_ctl.scala 292:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 292:144] + skip @[el2_pic_ctl.scala 292:126] + node _T_1723 = bits(intenable_reg_re_23, 0, 0) @[el2_pic_ctl.scala 292:69] + when _T_1723 : @[el2_pic_ctl.scala 292:76] + intenable_rd_out <= intenable_reg[23] @[el2_pic_ctl.scala 292:95] + skip @[el2_pic_ctl.scala 292:76] + else : @[el2_pic_ctl.scala 292:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 292:144] + skip @[el2_pic_ctl.scala 292:126] + node _T_1724 = bits(intenable_reg_re_24, 0, 0) @[el2_pic_ctl.scala 292:69] + when _T_1724 : @[el2_pic_ctl.scala 292:76] + intenable_rd_out <= intenable_reg[24] @[el2_pic_ctl.scala 292:95] + skip @[el2_pic_ctl.scala 292:76] + else : @[el2_pic_ctl.scala 292:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 292:144] + skip @[el2_pic_ctl.scala 292:126] + node _T_1725 = bits(intenable_reg_re_25, 0, 0) @[el2_pic_ctl.scala 292:69] + when _T_1725 : @[el2_pic_ctl.scala 292:76] + intenable_rd_out <= intenable_reg[25] @[el2_pic_ctl.scala 292:95] + skip @[el2_pic_ctl.scala 292:76] + else : @[el2_pic_ctl.scala 292:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 292:144] + skip @[el2_pic_ctl.scala 292:126] + node _T_1726 = bits(intenable_reg_re_26, 0, 0) @[el2_pic_ctl.scala 292:69] + when _T_1726 : @[el2_pic_ctl.scala 292:76] + intenable_rd_out <= intenable_reg[26] @[el2_pic_ctl.scala 292:95] + skip @[el2_pic_ctl.scala 292:76] + else : @[el2_pic_ctl.scala 292:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 292:144] + skip @[el2_pic_ctl.scala 292:126] + node _T_1727 = bits(intenable_reg_re_27, 0, 0) @[el2_pic_ctl.scala 292:69] + when _T_1727 : @[el2_pic_ctl.scala 292:76] + intenable_rd_out <= intenable_reg[27] @[el2_pic_ctl.scala 292:95] + skip @[el2_pic_ctl.scala 292:76] + else : @[el2_pic_ctl.scala 292:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 292:144] + skip @[el2_pic_ctl.scala 292:126] + node _T_1728 = bits(intenable_reg_re_28, 0, 0) @[el2_pic_ctl.scala 292:69] + when _T_1728 : @[el2_pic_ctl.scala 292:76] + intenable_rd_out <= intenable_reg[28] @[el2_pic_ctl.scala 292:95] + skip @[el2_pic_ctl.scala 292:76] + else : @[el2_pic_ctl.scala 292:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 292:144] + skip @[el2_pic_ctl.scala 292:126] + node _T_1729 = bits(intenable_reg_re_29, 0, 0) @[el2_pic_ctl.scala 292:69] + when _T_1729 : @[el2_pic_ctl.scala 292:76] + intenable_rd_out <= intenable_reg[29] @[el2_pic_ctl.scala 292:95] + skip @[el2_pic_ctl.scala 292:76] + else : @[el2_pic_ctl.scala 292:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 292:144] + skip @[el2_pic_ctl.scala 292:126] + node _T_1730 = bits(intenable_reg_re_30, 0, 0) @[el2_pic_ctl.scala 292:69] + when _T_1730 : @[el2_pic_ctl.scala 292:76] + intenable_rd_out <= intenable_reg[30] @[el2_pic_ctl.scala 292:95] + skip @[el2_pic_ctl.scala 292:76] + else : @[el2_pic_ctl.scala 292:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 292:144] + skip @[el2_pic_ctl.scala 292:126] + node _T_1731 = bits(intenable_reg_re_31, 0, 0) @[el2_pic_ctl.scala 292:69] + when _T_1731 : @[el2_pic_ctl.scala 292:76] + intenable_rd_out <= intenable_reg[31] @[el2_pic_ctl.scala 292:95] + skip @[el2_pic_ctl.scala 292:76] + else : @[el2_pic_ctl.scala 292:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 292:144] + skip @[el2_pic_ctl.scala 292:126] + node _T_1732 = bits(intpriority_reg_re_1, 0, 0) @[el2_pic_ctl.scala 294:102] + node _T_1733 = bits(intpriority_reg_re_2, 0, 0) @[el2_pic_ctl.scala 294:102] + node _T_1734 = bits(intpriority_reg_re_3, 0, 0) @[el2_pic_ctl.scala 294:102] + node _T_1735 = bits(intpriority_reg_re_4, 0, 0) @[el2_pic_ctl.scala 294:102] + node _T_1736 = bits(intpriority_reg_re_5, 0, 0) @[el2_pic_ctl.scala 294:102] + node _T_1737 = bits(intpriority_reg_re_6, 0, 0) @[el2_pic_ctl.scala 294:102] + node _T_1738 = bits(intpriority_reg_re_7, 0, 0) @[el2_pic_ctl.scala 294:102] + node _T_1739 = bits(intpriority_reg_re_8, 0, 0) @[el2_pic_ctl.scala 294:102] + node _T_1740 = bits(intpriority_reg_re_9, 0, 0) @[el2_pic_ctl.scala 294:102] + node _T_1741 = bits(intpriority_reg_re_10, 0, 0) @[el2_pic_ctl.scala 294:102] + node _T_1742 = bits(intpriority_reg_re_11, 0, 0) @[el2_pic_ctl.scala 294:102] + node _T_1743 = bits(intpriority_reg_re_12, 0, 0) @[el2_pic_ctl.scala 294:102] + node _T_1744 = bits(intpriority_reg_re_13, 0, 0) @[el2_pic_ctl.scala 294:102] + node _T_1745 = bits(intpriority_reg_re_14, 0, 0) @[el2_pic_ctl.scala 294:102] + node _T_1746 = bits(intpriority_reg_re_15, 0, 0) @[el2_pic_ctl.scala 294:102] + node _T_1747 = bits(intpriority_reg_re_16, 0, 0) @[el2_pic_ctl.scala 294:102] + node _T_1748 = bits(intpriority_reg_re_17, 0, 0) @[el2_pic_ctl.scala 294:102] + node _T_1749 = bits(intpriority_reg_re_18, 0, 0) @[el2_pic_ctl.scala 294:102] + node _T_1750 = bits(intpriority_reg_re_19, 0, 0) @[el2_pic_ctl.scala 294:102] + node _T_1751 = bits(intpriority_reg_re_20, 0, 0) @[el2_pic_ctl.scala 294:102] + node _T_1752 = bits(intpriority_reg_re_21, 0, 0) @[el2_pic_ctl.scala 294:102] + node _T_1753 = bits(intpriority_reg_re_22, 0, 0) @[el2_pic_ctl.scala 294:102] + node _T_1754 = bits(intpriority_reg_re_23, 0, 0) @[el2_pic_ctl.scala 294:102] + node _T_1755 = bits(intpriority_reg_re_24, 0, 0) @[el2_pic_ctl.scala 294:102] + node _T_1756 = bits(intpriority_reg_re_25, 0, 0) @[el2_pic_ctl.scala 294:102] + node _T_1757 = bits(intpriority_reg_re_26, 0, 0) @[el2_pic_ctl.scala 294:102] + node _T_1758 = bits(intpriority_reg_re_27, 0, 0) @[el2_pic_ctl.scala 294:102] + node _T_1759 = bits(intpriority_reg_re_28, 0, 0) @[el2_pic_ctl.scala 294:102] + node _T_1760 = bits(intpriority_reg_re_29, 0, 0) @[el2_pic_ctl.scala 294:102] + node _T_1761 = bits(intpriority_reg_re_30, 0, 0) @[el2_pic_ctl.scala 294:102] + node _T_1762 = bits(intpriority_reg_re_31, 0, 0) @[el2_pic_ctl.scala 294:102] + node _T_1763 = mux(_T_1762, intpriority_reg[31], UInt<1>("h00")) @[Mux.scala 98:16] + node _T_1764 = mux(_T_1761, intpriority_reg[30], _T_1763) @[Mux.scala 98:16] + node _T_1765 = mux(_T_1760, intpriority_reg[29], _T_1764) @[Mux.scala 98:16] + node _T_1766 = mux(_T_1759, intpriority_reg[28], _T_1765) @[Mux.scala 98:16] + node _T_1767 = mux(_T_1758, intpriority_reg[27], _T_1766) @[Mux.scala 98:16] + node _T_1768 = mux(_T_1757, intpriority_reg[26], _T_1767) @[Mux.scala 98:16] + node _T_1769 = mux(_T_1756, intpriority_reg[25], _T_1768) @[Mux.scala 98:16] + node _T_1770 = mux(_T_1755, intpriority_reg[24], _T_1769) @[Mux.scala 98:16] + node _T_1771 = mux(_T_1754, intpriority_reg[23], _T_1770) @[Mux.scala 98:16] + node _T_1772 = mux(_T_1753, intpriority_reg[22], _T_1771) @[Mux.scala 98:16] + node _T_1773 = mux(_T_1752, intpriority_reg[21], _T_1772) @[Mux.scala 98:16] + node _T_1774 = mux(_T_1751, intpriority_reg[20], _T_1773) @[Mux.scala 98:16] + node _T_1775 = mux(_T_1750, intpriority_reg[19], _T_1774) @[Mux.scala 98:16] + node _T_1776 = mux(_T_1749, intpriority_reg[18], _T_1775) @[Mux.scala 98:16] + node _T_1777 = mux(_T_1748, intpriority_reg[17], _T_1776) @[Mux.scala 98:16] + node _T_1778 = mux(_T_1747, intpriority_reg[16], _T_1777) @[Mux.scala 98:16] + node _T_1779 = mux(_T_1746, intpriority_reg[15], _T_1778) @[Mux.scala 98:16] + node _T_1780 = mux(_T_1745, intpriority_reg[14], _T_1779) @[Mux.scala 98:16] + node _T_1781 = mux(_T_1744, intpriority_reg[13], _T_1780) @[Mux.scala 98:16] + node _T_1782 = mux(_T_1743, intpriority_reg[12], _T_1781) @[Mux.scala 98:16] + node _T_1783 = mux(_T_1742, intpriority_reg[11], _T_1782) @[Mux.scala 98:16] + node _T_1784 = mux(_T_1741, intpriority_reg[10], _T_1783) @[Mux.scala 98:16] + node _T_1785 = mux(_T_1740, intpriority_reg[9], _T_1784) @[Mux.scala 98:16] + node _T_1786 = mux(_T_1739, intpriority_reg[8], _T_1785) @[Mux.scala 98:16] + node _T_1787 = mux(_T_1738, intpriority_reg[7], _T_1786) @[Mux.scala 98:16] + node _T_1788 = mux(_T_1737, intpriority_reg[6], _T_1787) @[Mux.scala 98:16] + node _T_1789 = mux(_T_1736, intpriority_reg[5], _T_1788) @[Mux.scala 98:16] + node _T_1790 = mux(_T_1735, intpriority_reg[4], _T_1789) @[Mux.scala 98:16] + node _T_1791 = mux(_T_1734, intpriority_reg[3], _T_1790) @[Mux.scala 98:16] + node _T_1792 = mux(_T_1733, intpriority_reg[2], _T_1791) @[Mux.scala 98:16] + node _T_1793 = mux(_T_1732, intpriority_reg[1], _T_1792) @[Mux.scala 98:16] + node intpriority_rd_out = mux(UInt<1>("h00"), intpriority_reg[0], _T_1793) @[Mux.scala 98:16] + node _T_1794 = bits(gw_config_reg_re_1, 0, 0) @[el2_pic_ctl.scala 295:100] + node _T_1795 = bits(gw_config_reg_re_2, 0, 0) @[el2_pic_ctl.scala 295:100] + node _T_1796 = bits(gw_config_reg_re_3, 0, 0) @[el2_pic_ctl.scala 295:100] + node _T_1797 = bits(gw_config_reg_re_4, 0, 0) @[el2_pic_ctl.scala 295:100] + node _T_1798 = bits(gw_config_reg_re_5, 0, 0) @[el2_pic_ctl.scala 295:100] + node _T_1799 = bits(gw_config_reg_re_6, 0, 0) @[el2_pic_ctl.scala 295:100] + node _T_1800 = bits(gw_config_reg_re_7, 0, 0) @[el2_pic_ctl.scala 295:100] + node _T_1801 = bits(gw_config_reg_re_8, 0, 0) @[el2_pic_ctl.scala 295:100] + node _T_1802 = bits(gw_config_reg_re_9, 0, 0) @[el2_pic_ctl.scala 295:100] + node _T_1803 = bits(gw_config_reg_re_10, 0, 0) @[el2_pic_ctl.scala 295:100] + node _T_1804 = bits(gw_config_reg_re_11, 0, 0) @[el2_pic_ctl.scala 295:100] + node _T_1805 = bits(gw_config_reg_re_12, 0, 0) @[el2_pic_ctl.scala 295:100] + node _T_1806 = bits(gw_config_reg_re_13, 0, 0) @[el2_pic_ctl.scala 295:100] + node _T_1807 = bits(gw_config_reg_re_14, 0, 0) @[el2_pic_ctl.scala 295:100] + node _T_1808 = bits(gw_config_reg_re_15, 0, 0) @[el2_pic_ctl.scala 295:100] + node _T_1809 = bits(gw_config_reg_re_16, 0, 0) @[el2_pic_ctl.scala 295:100] + node _T_1810 = bits(gw_config_reg_re_17, 0, 0) @[el2_pic_ctl.scala 295:100] + node _T_1811 = bits(gw_config_reg_re_18, 0, 0) @[el2_pic_ctl.scala 295:100] + node _T_1812 = bits(gw_config_reg_re_19, 0, 0) @[el2_pic_ctl.scala 295:100] + node _T_1813 = bits(gw_config_reg_re_20, 0, 0) @[el2_pic_ctl.scala 295:100] + node _T_1814 = bits(gw_config_reg_re_21, 0, 0) @[el2_pic_ctl.scala 295:100] + node _T_1815 = bits(gw_config_reg_re_22, 0, 0) @[el2_pic_ctl.scala 295:100] + node _T_1816 = bits(gw_config_reg_re_23, 0, 0) @[el2_pic_ctl.scala 295:100] + node _T_1817 = bits(gw_config_reg_re_24, 0, 0) @[el2_pic_ctl.scala 295:100] + node _T_1818 = bits(gw_config_reg_re_25, 0, 0) @[el2_pic_ctl.scala 295:100] + node _T_1819 = bits(gw_config_reg_re_26, 0, 0) @[el2_pic_ctl.scala 295:100] + node _T_1820 = bits(gw_config_reg_re_27, 0, 0) @[el2_pic_ctl.scala 295:100] + node _T_1821 = bits(gw_config_reg_re_28, 0, 0) @[el2_pic_ctl.scala 295:100] + node _T_1822 = bits(gw_config_reg_re_29, 0, 0) @[el2_pic_ctl.scala 295:100] + node _T_1823 = bits(gw_config_reg_re_30, 0, 0) @[el2_pic_ctl.scala 295:100] + node _T_1824 = bits(gw_config_reg_re_31, 0, 0) @[el2_pic_ctl.scala 295:100] + node _T_1825 = mux(_T_1824, gw_config_reg[31], UInt<1>("h00")) @[Mux.scala 98:16] + node _T_1826 = mux(_T_1823, gw_config_reg[30], _T_1825) @[Mux.scala 98:16] + node _T_1827 = mux(_T_1822, gw_config_reg[29], _T_1826) @[Mux.scala 98:16] + node _T_1828 = mux(_T_1821, gw_config_reg[28], _T_1827) @[Mux.scala 98:16] + node _T_1829 = mux(_T_1820, gw_config_reg[27], _T_1828) @[Mux.scala 98:16] + node _T_1830 = mux(_T_1819, gw_config_reg[26], _T_1829) @[Mux.scala 98:16] + node _T_1831 = mux(_T_1818, gw_config_reg[25], _T_1830) @[Mux.scala 98:16] + node _T_1832 = mux(_T_1817, gw_config_reg[24], _T_1831) @[Mux.scala 98:16] + node _T_1833 = mux(_T_1816, gw_config_reg[23], _T_1832) @[Mux.scala 98:16] + node _T_1834 = mux(_T_1815, gw_config_reg[22], _T_1833) @[Mux.scala 98:16] + node _T_1835 = mux(_T_1814, gw_config_reg[21], _T_1834) @[Mux.scala 98:16] + node _T_1836 = mux(_T_1813, gw_config_reg[20], _T_1835) @[Mux.scala 98:16] + node _T_1837 = mux(_T_1812, gw_config_reg[19], _T_1836) @[Mux.scala 98:16] + node _T_1838 = mux(_T_1811, gw_config_reg[18], _T_1837) @[Mux.scala 98:16] + node _T_1839 = mux(_T_1810, gw_config_reg[17], _T_1838) @[Mux.scala 98:16] + node _T_1840 = mux(_T_1809, gw_config_reg[16], _T_1839) @[Mux.scala 98:16] + node _T_1841 = mux(_T_1808, gw_config_reg[15], _T_1840) @[Mux.scala 98:16] + node _T_1842 = mux(_T_1807, gw_config_reg[14], _T_1841) @[Mux.scala 98:16] + node _T_1843 = mux(_T_1806, gw_config_reg[13], _T_1842) @[Mux.scala 98:16] + node _T_1844 = mux(_T_1805, gw_config_reg[12], _T_1843) @[Mux.scala 98:16] + node _T_1845 = mux(_T_1804, gw_config_reg[11], _T_1844) @[Mux.scala 98:16] + node _T_1846 = mux(_T_1803, gw_config_reg[10], _T_1845) @[Mux.scala 98:16] + node _T_1847 = mux(_T_1802, gw_config_reg[9], _T_1846) @[Mux.scala 98:16] + node _T_1848 = mux(_T_1801, gw_config_reg[8], _T_1847) @[Mux.scala 98:16] + node _T_1849 = mux(_T_1800, gw_config_reg[7], _T_1848) @[Mux.scala 98:16] + node _T_1850 = mux(_T_1799, gw_config_reg[6], _T_1849) @[Mux.scala 98:16] + node _T_1851 = mux(_T_1798, gw_config_reg[5], _T_1850) @[Mux.scala 98:16] + node _T_1852 = mux(_T_1797, gw_config_reg[4], _T_1851) @[Mux.scala 98:16] + node _T_1853 = mux(_T_1796, gw_config_reg[3], _T_1852) @[Mux.scala 98:16] + node _T_1854 = mux(_T_1795, gw_config_reg[2], _T_1853) @[Mux.scala 98:16] + node _T_1855 = mux(_T_1794, gw_config_reg[1], _T_1854) @[Mux.scala 98:16] + node gw_config_rd_out = mux(UInt<1>("h00"), gw_config_reg[0], _T_1855) @[Mux.scala 98:16] wire picm_rd_data_in : UInt<32> picm_rd_data_in <= UInt<1>("h00") - node _T_1928 = bits(intpend_reg_read, 0, 0) @[el2_pic_ctl.scala 308:22] - node _T_1929 = bits(intpriority_reg_read, 0, 0) @[el2_pic_ctl.scala 309:26] - node _T_1930 = mux(UInt<1>("h00"), UInt<28>("h0fffffff"), UInt<28>("h00")) @[Bitwise.scala 72:12] - node _T_1931 = cat(_T_1930, intpriority_rd_out) @[Cat.scala 29:58] - node _T_1932 = bits(intenable_reg_read, 0, 0) @[el2_pic_ctl.scala 310:24] - node _T_1933 = mux(UInt<1>("h00"), UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12] - node _T_1934 = cat(_T_1933, intenable_rd_out) @[Cat.scala 29:58] - node _T_1935 = bits(gw_config_reg_read, 0, 0) @[el2_pic_ctl.scala 311:24] - node _T_1936 = mux(UInt<1>("h00"), UInt<30>("h03fffffff"), UInt<30>("h00")) @[Bitwise.scala 72:12] - node _T_1937 = cat(_T_1936, gw_config_rd_out) @[Cat.scala 29:58] - node _T_1938 = bits(config_reg_re, 0, 0) @[el2_pic_ctl.scala 312:19] - node _T_1939 = mux(UInt<1>("h00"), UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12] - node _T_1940 = cat(_T_1939, config_reg) @[Cat.scala 29:58] - node _T_1941 = bits(mask, 3, 3) @[el2_pic_ctl.scala 313:25] - node _T_1942 = and(picm_mken_ff, _T_1941) @[el2_pic_ctl.scala 313:19] - node _T_1943 = bits(_T_1942, 0, 0) @[el2_pic_ctl.scala 313:30] - node _T_1944 = mux(UInt<1>("h00"), UInt<30>("h03fffffff"), UInt<30>("h00")) @[Bitwise.scala 72:12] - node _T_1945 = cat(_T_1944, UInt<2>("h03")) @[Cat.scala 29:58] - node _T_1946 = bits(mask, 2, 2) @[el2_pic_ctl.scala 314:25] - node _T_1947 = and(picm_mken_ff, _T_1946) @[el2_pic_ctl.scala 314:19] - node _T_1948 = bits(_T_1947, 0, 0) @[el2_pic_ctl.scala 314:30] - node _T_1949 = mux(UInt<1>("h00"), UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12] - node _T_1950 = cat(_T_1949, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_1951 = bits(mask, 1, 1) @[el2_pic_ctl.scala 315:25] - node _T_1952 = and(picm_mken_ff, _T_1951) @[el2_pic_ctl.scala 315:19] - node _T_1953 = bits(_T_1952, 0, 0) @[el2_pic_ctl.scala 315:30] - node _T_1954 = mux(UInt<1>("h00"), UInt<28>("h0fffffff"), UInt<28>("h00")) @[Bitwise.scala 72:12] - node _T_1955 = cat(_T_1954, UInt<4>("h0f")) @[Cat.scala 29:58] - node _T_1956 = bits(mask, 0, 0) @[el2_pic_ctl.scala 316:25] - node _T_1957 = and(picm_mken_ff, _T_1956) @[el2_pic_ctl.scala 316:19] - node _T_1958 = bits(_T_1957, 0, 0) @[el2_pic_ctl.scala 316:30] - node _T_1959 = mux(UInt<1>("h00"), UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_1960 = mux(_T_1928, intpend_rd_out, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1961 = mux(_T_1929, _T_1931, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1962 = mux(_T_1932, _T_1934, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1963 = mux(_T_1935, _T_1937, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1964 = mux(_T_1938, _T_1940, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1965 = mux(_T_1943, _T_1945, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1966 = mux(_T_1948, _T_1950, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1967 = mux(_T_1953, _T_1955, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1968 = mux(_T_1958, _T_1959, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1969 = or(_T_1960, _T_1961) @[Mux.scala 27:72] - node _T_1970 = or(_T_1969, _T_1962) @[Mux.scala 27:72] - node _T_1971 = or(_T_1970, _T_1963) @[Mux.scala 27:72] - node _T_1972 = or(_T_1971, _T_1964) @[Mux.scala 27:72] - node _T_1973 = or(_T_1972, _T_1965) @[Mux.scala 27:72] - node _T_1974 = or(_T_1973, _T_1966) @[Mux.scala 27:72] - node _T_1975 = or(_T_1974, _T_1967) @[Mux.scala 27:72] - node _T_1976 = or(_T_1975, _T_1968) @[Mux.scala 27:72] - wire _T_1977 : UInt<32> @[Mux.scala 27:72] - _T_1977 <= _T_1976 @[Mux.scala 27:72] - picm_rd_data_in <= _T_1977 @[el2_pic_ctl.scala 307:19] - node _T_1978 = bits(picm_bypass_ff, 0, 0) @[el2_pic_ctl.scala 319:41] - node _T_1979 = mux(_T_1978, picm_wr_data_ff, picm_rd_data_in) @[el2_pic_ctl.scala 319:25] - io.picm_rd_data <= _T_1979 @[el2_pic_ctl.scala 319:19] - node address = bits(picm_raddr_ff, 14, 0) @[el2_pic_ctl.scala 320:30] - mask <= UInt<4>("h01") @[el2_pic_ctl.scala 322:8] - node _T_1980 = eq(UInt<15>("h03000"), address) @[Conditional.scala 37:30] - when _T_1980 : @[Conditional.scala 40:58] - mask <= UInt<4>("h04") @[el2_pic_ctl.scala 324:44] + node _T_1856 = bits(intpend_reg_read, 0, 0) @[el2_pic_ctl.scala 300:22] + node _T_1857 = bits(intpriority_reg_read, 0, 0) @[el2_pic_ctl.scala 301:26] + node _T_1858 = mux(UInt<1>("h00"), UInt<28>("h0fffffff"), UInt<28>("h00")) @[Bitwise.scala 72:12] + node _T_1859 = cat(_T_1858, intpriority_rd_out) @[Cat.scala 29:58] + node _T_1860 = bits(intenable_reg_read, 0, 0) @[el2_pic_ctl.scala 302:24] + node _T_1861 = mux(UInt<1>("h00"), UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12] + node _T_1862 = cat(_T_1861, intenable_rd_out) @[Cat.scala 29:58] + node _T_1863 = bits(gw_config_reg_read, 0, 0) @[el2_pic_ctl.scala 303:24] + node _T_1864 = mux(UInt<1>("h00"), UInt<30>("h03fffffff"), UInt<30>("h00")) @[Bitwise.scala 72:12] + node _T_1865 = cat(_T_1864, gw_config_rd_out) @[Cat.scala 29:58] + node _T_1866 = bits(config_reg_re, 0, 0) @[el2_pic_ctl.scala 304:19] + node _T_1867 = mux(UInt<1>("h00"), UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12] + node _T_1868 = cat(_T_1867, config_reg) @[Cat.scala 29:58] + node _T_1869 = bits(mask, 3, 3) @[el2_pic_ctl.scala 305:25] + node _T_1870 = and(picm_mken_ff, _T_1869) @[el2_pic_ctl.scala 305:19] + node _T_1871 = bits(_T_1870, 0, 0) @[el2_pic_ctl.scala 305:30] + node _T_1872 = mux(UInt<1>("h00"), UInt<30>("h03fffffff"), UInt<30>("h00")) @[Bitwise.scala 72:12] + node _T_1873 = cat(_T_1872, UInt<2>("h03")) @[Cat.scala 29:58] + node _T_1874 = bits(mask, 2, 2) @[el2_pic_ctl.scala 306:25] + node _T_1875 = and(picm_mken_ff, _T_1874) @[el2_pic_ctl.scala 306:19] + node _T_1876 = bits(_T_1875, 0, 0) @[el2_pic_ctl.scala 306:30] + node _T_1877 = mux(UInt<1>("h00"), UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12] + node _T_1878 = cat(_T_1877, UInt<1>("h01")) @[Cat.scala 29:58] + node _T_1879 = bits(mask, 1, 1) @[el2_pic_ctl.scala 307:25] + node _T_1880 = and(picm_mken_ff, _T_1879) @[el2_pic_ctl.scala 307:19] + node _T_1881 = bits(_T_1880, 0, 0) @[el2_pic_ctl.scala 307:30] + node _T_1882 = mux(UInt<1>("h00"), UInt<28>("h0fffffff"), UInt<28>("h00")) @[Bitwise.scala 72:12] + node _T_1883 = cat(_T_1882, UInt<4>("h0f")) @[Cat.scala 29:58] + node _T_1884 = bits(mask, 0, 0) @[el2_pic_ctl.scala 308:25] + node _T_1885 = and(picm_mken_ff, _T_1884) @[el2_pic_ctl.scala 308:19] + node _T_1886 = bits(_T_1885, 0, 0) @[el2_pic_ctl.scala 308:30] + node _T_1887 = mux(UInt<1>("h00"), UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_1888 = mux(_T_1856, intpend_rd_out, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1889 = mux(_T_1857, _T_1859, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1890 = mux(_T_1860, _T_1862, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1891 = mux(_T_1863, _T_1865, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1892 = mux(_T_1866, _T_1868, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1893 = mux(_T_1871, _T_1873, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1894 = mux(_T_1876, _T_1878, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1895 = mux(_T_1881, _T_1883, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1896 = mux(_T_1886, _T_1887, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1897 = or(_T_1888, _T_1889) @[Mux.scala 27:72] + node _T_1898 = or(_T_1897, _T_1890) @[Mux.scala 27:72] + node _T_1899 = or(_T_1898, _T_1891) @[Mux.scala 27:72] + node _T_1900 = or(_T_1899, _T_1892) @[Mux.scala 27:72] + node _T_1901 = or(_T_1900, _T_1893) @[Mux.scala 27:72] + node _T_1902 = or(_T_1901, _T_1894) @[Mux.scala 27:72] + node _T_1903 = or(_T_1902, _T_1895) @[Mux.scala 27:72] + node _T_1904 = or(_T_1903, _T_1896) @[Mux.scala 27:72] + wire _T_1905 : UInt<32> @[Mux.scala 27:72] + _T_1905 <= _T_1904 @[Mux.scala 27:72] + picm_rd_data_in <= _T_1905 @[el2_pic_ctl.scala 299:19] + node _T_1906 = bits(picm_bypass_ff, 0, 0) @[el2_pic_ctl.scala 311:41] + node _T_1907 = mux(_T_1906, picm_wr_data_ff, picm_rd_data_in) @[el2_pic_ctl.scala 311:25] + io.picm_rd_data <= _T_1907 @[el2_pic_ctl.scala 311:19] + node address = bits(picm_raddr_ff, 14, 0) @[el2_pic_ctl.scala 312:30] + mask <= UInt<4>("h01") @[el2_pic_ctl.scala 314:8] + node _T_1908 = eq(UInt<15>("h03000"), address) @[Conditional.scala 37:30] + when _T_1908 : @[Conditional.scala 40:58] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 316:44] skip @[Conditional.scala 40:58] else : @[Conditional.scala 39:67] - node _T_1981 = eq(UInt<15>("h04004"), address) @[Conditional.scala 37:30] - when _T_1981 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[el2_pic_ctl.scala 325:44] + node _T_1909 = eq(UInt<15>("h04004"), address) @[Conditional.scala 37:30] + when _T_1909 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 317:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_1982 = eq(UInt<15>("h04008"), address) @[Conditional.scala 37:30] - when _T_1982 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[el2_pic_ctl.scala 326:44] + node _T_1910 = eq(UInt<15>("h04008"), address) @[Conditional.scala 37:30] + when _T_1910 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 318:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_1983 = eq(UInt<15>("h0400c"), address) @[Conditional.scala 37:30] - when _T_1983 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[el2_pic_ctl.scala 327:44] + node _T_1911 = eq(UInt<15>("h0400c"), address) @[Conditional.scala 37:30] + when _T_1911 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 319:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_1984 = eq(UInt<15>("h04010"), address) @[Conditional.scala 37:30] - when _T_1984 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[el2_pic_ctl.scala 328:44] + node _T_1912 = eq(UInt<15>("h04010"), address) @[Conditional.scala 37:30] + when _T_1912 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 320:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_1985 = eq(UInt<15>("h04014"), address) @[Conditional.scala 37:30] - when _T_1985 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[el2_pic_ctl.scala 329:44] + node _T_1913 = eq(UInt<15>("h04014"), address) @[Conditional.scala 37:30] + when _T_1913 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 321:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_1986 = eq(UInt<15>("h04018"), address) @[Conditional.scala 37:30] - when _T_1986 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[el2_pic_ctl.scala 330:44] + node _T_1914 = eq(UInt<15>("h04018"), address) @[Conditional.scala 37:30] + when _T_1914 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 322:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_1987 = eq(UInt<15>("h0401c"), address) @[Conditional.scala 37:30] - when _T_1987 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[el2_pic_ctl.scala 331:44] + node _T_1915 = eq(UInt<15>("h0401c"), address) @[Conditional.scala 37:30] + when _T_1915 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 323:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_1988 = eq(UInt<15>("h04020"), address) @[Conditional.scala 37:30] - when _T_1988 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[el2_pic_ctl.scala 332:44] + node _T_1916 = eq(UInt<15>("h04020"), address) @[Conditional.scala 37:30] + when _T_1916 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 324:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_1989 = eq(UInt<15>("h04024"), address) @[Conditional.scala 37:30] - when _T_1989 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[el2_pic_ctl.scala 333:44] + node _T_1917 = eq(UInt<15>("h04024"), address) @[Conditional.scala 37:30] + when _T_1917 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 325:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_1990 = eq(UInt<15>("h04028"), address) @[Conditional.scala 37:30] - when _T_1990 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[el2_pic_ctl.scala 334:44] + node _T_1918 = eq(UInt<15>("h04028"), address) @[Conditional.scala 37:30] + when _T_1918 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 326:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_1991 = eq(UInt<15>("h0402c"), address) @[Conditional.scala 37:30] - when _T_1991 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[el2_pic_ctl.scala 335:44] + node _T_1919 = eq(UInt<15>("h0402c"), address) @[Conditional.scala 37:30] + when _T_1919 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 327:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_1992 = eq(UInt<15>("h04030"), address) @[Conditional.scala 37:30] - when _T_1992 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[el2_pic_ctl.scala 336:44] + node _T_1920 = eq(UInt<15>("h04030"), address) @[Conditional.scala 37:30] + when _T_1920 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 328:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_1993 = eq(UInt<15>("h04034"), address) @[Conditional.scala 37:30] - when _T_1993 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[el2_pic_ctl.scala 337:44] + node _T_1921 = eq(UInt<15>("h04034"), address) @[Conditional.scala 37:30] + when _T_1921 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 329:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_1994 = eq(UInt<15>("h04038"), address) @[Conditional.scala 37:30] - when _T_1994 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[el2_pic_ctl.scala 338:44] + node _T_1922 = eq(UInt<15>("h04038"), address) @[Conditional.scala 37:30] + when _T_1922 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 330:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_1995 = eq(UInt<15>("h0403c"), address) @[Conditional.scala 37:30] - when _T_1995 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[el2_pic_ctl.scala 339:44] + node _T_1923 = eq(UInt<15>("h0403c"), address) @[Conditional.scala 37:30] + when _T_1923 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 331:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_1996 = eq(UInt<15>("h04040"), address) @[Conditional.scala 37:30] - when _T_1996 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[el2_pic_ctl.scala 340:44] + node _T_1924 = eq(UInt<15>("h04040"), address) @[Conditional.scala 37:30] + when _T_1924 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 332:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_1997 = eq(UInt<15>("h04044"), address) @[Conditional.scala 37:30] - when _T_1997 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[el2_pic_ctl.scala 341:44] + node _T_1925 = eq(UInt<15>("h04044"), address) @[Conditional.scala 37:30] + when _T_1925 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 333:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_1998 = eq(UInt<15>("h04048"), address) @[Conditional.scala 37:30] - when _T_1998 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[el2_pic_ctl.scala 342:44] + node _T_1926 = eq(UInt<15>("h04048"), address) @[Conditional.scala 37:30] + when _T_1926 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 334:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_1999 = eq(UInt<15>("h0404c"), address) @[Conditional.scala 37:30] - when _T_1999 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[el2_pic_ctl.scala 343:44] + node _T_1927 = eq(UInt<15>("h0404c"), address) @[Conditional.scala 37:30] + when _T_1927 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 335:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2000 = eq(UInt<15>("h04050"), address) @[Conditional.scala 37:30] - when _T_2000 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[el2_pic_ctl.scala 344:44] + node _T_1928 = eq(UInt<15>("h04050"), address) @[Conditional.scala 37:30] + when _T_1928 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 336:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2001 = eq(UInt<15>("h04054"), address) @[Conditional.scala 37:30] - when _T_2001 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[el2_pic_ctl.scala 345:44] + node _T_1929 = eq(UInt<15>("h04054"), address) @[Conditional.scala 37:30] + when _T_1929 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 337:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2002 = eq(UInt<15>("h04058"), address) @[Conditional.scala 37:30] - when _T_2002 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[el2_pic_ctl.scala 346:44] + node _T_1930 = eq(UInt<15>("h04058"), address) @[Conditional.scala 37:30] + when _T_1930 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 338:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2003 = eq(UInt<15>("h0405c"), address) @[Conditional.scala 37:30] - when _T_2003 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[el2_pic_ctl.scala 347:44] + node _T_1931 = eq(UInt<15>("h0405c"), address) @[Conditional.scala 37:30] + when _T_1931 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 339:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2004 = eq(UInt<15>("h04060"), address) @[Conditional.scala 37:30] - when _T_2004 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[el2_pic_ctl.scala 348:44] + node _T_1932 = eq(UInt<15>("h04060"), address) @[Conditional.scala 37:30] + when _T_1932 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 340:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2005 = eq(UInt<15>("h04064"), address) @[Conditional.scala 37:30] - when _T_2005 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[el2_pic_ctl.scala 349:44] + node _T_1933 = eq(UInt<15>("h04064"), address) @[Conditional.scala 37:30] + when _T_1933 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 341:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2006 = eq(UInt<15>("h04068"), address) @[Conditional.scala 37:30] - when _T_2006 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[el2_pic_ctl.scala 350:44] + node _T_1934 = eq(UInt<15>("h04068"), address) @[Conditional.scala 37:30] + when _T_1934 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 342:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2007 = eq(UInt<15>("h0406c"), address) @[Conditional.scala 37:30] - when _T_2007 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[el2_pic_ctl.scala 351:44] + node _T_1935 = eq(UInt<15>("h0406c"), address) @[Conditional.scala 37:30] + when _T_1935 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 343:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2008 = eq(UInt<15>("h04070"), address) @[Conditional.scala 37:30] - when _T_2008 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[el2_pic_ctl.scala 352:44] + node _T_1936 = eq(UInt<15>("h04070"), address) @[Conditional.scala 37:30] + when _T_1936 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 344:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2009 = eq(UInt<15>("h04074"), address) @[Conditional.scala 37:30] - when _T_2009 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[el2_pic_ctl.scala 353:44] + node _T_1937 = eq(UInt<15>("h04074"), address) @[Conditional.scala 37:30] + when _T_1937 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 345:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2010 = eq(UInt<15>("h04078"), address) @[Conditional.scala 37:30] - when _T_2010 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[el2_pic_ctl.scala 354:44] + node _T_1938 = eq(UInt<15>("h04078"), address) @[Conditional.scala 37:30] + when _T_1938 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 346:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2011 = eq(UInt<15>("h0407c"), address) @[Conditional.scala 37:30] - when _T_2011 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[el2_pic_ctl.scala 355:44] + node _T_1939 = eq(UInt<15>("h0407c"), address) @[Conditional.scala 37:30] + when _T_1939 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 347:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2012 = eq(UInt<15>("h02004"), address) @[Conditional.scala 37:30] - when _T_2012 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[el2_pic_ctl.scala 356:44] + node _T_1940 = eq(UInt<15>("h02004"), address) @[Conditional.scala 37:30] + when _T_1940 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 348:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2013 = eq(UInt<15>("h02008"), address) @[Conditional.scala 37:30] - when _T_2013 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[el2_pic_ctl.scala 357:44] + node _T_1941 = eq(UInt<15>("h02008"), address) @[Conditional.scala 37:30] + when _T_1941 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 349:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2014 = eq(UInt<15>("h0200c"), address) @[Conditional.scala 37:30] - when _T_2014 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[el2_pic_ctl.scala 358:44] + node _T_1942 = eq(UInt<15>("h0200c"), address) @[Conditional.scala 37:30] + when _T_1942 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 350:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2015 = eq(UInt<15>("h02010"), address) @[Conditional.scala 37:30] - when _T_2015 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[el2_pic_ctl.scala 359:44] + node _T_1943 = eq(UInt<15>("h02010"), address) @[Conditional.scala 37:30] + when _T_1943 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 351:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2016 = eq(UInt<15>("h02014"), address) @[Conditional.scala 37:30] - when _T_2016 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[el2_pic_ctl.scala 360:44] + node _T_1944 = eq(UInt<15>("h02014"), address) @[Conditional.scala 37:30] + when _T_1944 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 352:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2017 = eq(UInt<15>("h02018"), address) @[Conditional.scala 37:30] - when _T_2017 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[el2_pic_ctl.scala 361:44] + node _T_1945 = eq(UInt<15>("h02018"), address) @[Conditional.scala 37:30] + when _T_1945 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 353:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2018 = eq(UInt<15>("h0201c"), address) @[Conditional.scala 37:30] - when _T_2018 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[el2_pic_ctl.scala 362:44] + node _T_1946 = eq(UInt<15>("h0201c"), address) @[Conditional.scala 37:30] + when _T_1946 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 354:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2019 = eq(UInt<15>("h02020"), address) @[Conditional.scala 37:30] - when _T_2019 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[el2_pic_ctl.scala 363:44] + node _T_1947 = eq(UInt<15>("h02020"), address) @[Conditional.scala 37:30] + when _T_1947 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 355:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2020 = eq(UInt<15>("h02024"), address) @[Conditional.scala 37:30] - when _T_2020 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[el2_pic_ctl.scala 364:44] + node _T_1948 = eq(UInt<15>("h02024"), address) @[Conditional.scala 37:30] + when _T_1948 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 356:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2021 = eq(UInt<15>("h02028"), address) @[Conditional.scala 37:30] - when _T_2021 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[el2_pic_ctl.scala 365:44] + node _T_1949 = eq(UInt<15>("h02028"), address) @[Conditional.scala 37:30] + when _T_1949 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 357:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2022 = eq(UInt<15>("h0202c"), address) @[Conditional.scala 37:30] - when _T_2022 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[el2_pic_ctl.scala 366:44] + node _T_1950 = eq(UInt<15>("h0202c"), address) @[Conditional.scala 37:30] + when _T_1950 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 358:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2023 = eq(UInt<15>("h02030"), address) @[Conditional.scala 37:30] - when _T_2023 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[el2_pic_ctl.scala 367:44] + node _T_1951 = eq(UInt<15>("h02030"), address) @[Conditional.scala 37:30] + when _T_1951 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 359:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2024 = eq(UInt<15>("h02034"), address) @[Conditional.scala 37:30] - when _T_2024 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[el2_pic_ctl.scala 368:44] + node _T_1952 = eq(UInt<15>("h02034"), address) @[Conditional.scala 37:30] + when _T_1952 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 360:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2025 = eq(UInt<15>("h02038"), address) @[Conditional.scala 37:30] - when _T_2025 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[el2_pic_ctl.scala 369:44] + node _T_1953 = eq(UInt<15>("h02038"), address) @[Conditional.scala 37:30] + when _T_1953 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 361:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2026 = eq(UInt<15>("h0203c"), address) @[Conditional.scala 37:30] - when _T_2026 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[el2_pic_ctl.scala 370:44] + node _T_1954 = eq(UInt<15>("h0203c"), address) @[Conditional.scala 37:30] + when _T_1954 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 362:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2027 = eq(UInt<15>("h02040"), address) @[Conditional.scala 37:30] - when _T_2027 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[el2_pic_ctl.scala 371:44] + node _T_1955 = eq(UInt<15>("h02040"), address) @[Conditional.scala 37:30] + when _T_1955 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 363:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2028 = eq(UInt<15>("h02044"), address) @[Conditional.scala 37:30] - when _T_2028 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[el2_pic_ctl.scala 372:44] + node _T_1956 = eq(UInt<15>("h02044"), address) @[Conditional.scala 37:30] + when _T_1956 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 364:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2029 = eq(UInt<15>("h02048"), address) @[Conditional.scala 37:30] - when _T_2029 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[el2_pic_ctl.scala 373:44] + node _T_1957 = eq(UInt<15>("h02048"), address) @[Conditional.scala 37:30] + when _T_1957 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 365:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2030 = eq(UInt<15>("h0204c"), address) @[Conditional.scala 37:30] - when _T_2030 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[el2_pic_ctl.scala 374:44] + node _T_1958 = eq(UInt<15>("h0204c"), address) @[Conditional.scala 37:30] + when _T_1958 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 366:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2031 = eq(UInt<15>("h02050"), address) @[Conditional.scala 37:30] - when _T_2031 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[el2_pic_ctl.scala 375:44] + node _T_1959 = eq(UInt<15>("h02050"), address) @[Conditional.scala 37:30] + when _T_1959 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 367:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2032 = eq(UInt<15>("h02054"), address) @[Conditional.scala 37:30] - when _T_2032 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[el2_pic_ctl.scala 376:44] + node _T_1960 = eq(UInt<15>("h02054"), address) @[Conditional.scala 37:30] + when _T_1960 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 368:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2033 = eq(UInt<15>("h02058"), address) @[Conditional.scala 37:30] - when _T_2033 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[el2_pic_ctl.scala 377:44] + node _T_1961 = eq(UInt<15>("h02058"), address) @[Conditional.scala 37:30] + when _T_1961 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 369:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2034 = eq(UInt<15>("h0205c"), address) @[Conditional.scala 37:30] - when _T_2034 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[el2_pic_ctl.scala 378:44] + node _T_1962 = eq(UInt<15>("h0205c"), address) @[Conditional.scala 37:30] + when _T_1962 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 370:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2035 = eq(UInt<15>("h02060"), address) @[Conditional.scala 37:30] - when _T_2035 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[el2_pic_ctl.scala 379:44] + node _T_1963 = eq(UInt<15>("h02060"), address) @[Conditional.scala 37:30] + when _T_1963 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 371:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2036 = eq(UInt<15>("h02064"), address) @[Conditional.scala 37:30] - when _T_2036 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[el2_pic_ctl.scala 380:44] + node _T_1964 = eq(UInt<15>("h02064"), address) @[Conditional.scala 37:30] + when _T_1964 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 372:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2037 = eq(UInt<15>("h02068"), address) @[Conditional.scala 37:30] - when _T_2037 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[el2_pic_ctl.scala 381:44] + node _T_1965 = eq(UInt<15>("h02068"), address) @[Conditional.scala 37:30] + when _T_1965 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 373:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2038 = eq(UInt<15>("h0206c"), address) @[Conditional.scala 37:30] - when _T_2038 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[el2_pic_ctl.scala 382:44] + node _T_1966 = eq(UInt<15>("h0206c"), address) @[Conditional.scala 37:30] + when _T_1966 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 374:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2039 = eq(UInt<15>("h02070"), address) @[Conditional.scala 37:30] - when _T_2039 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[el2_pic_ctl.scala 383:44] + node _T_1967 = eq(UInt<15>("h02070"), address) @[Conditional.scala 37:30] + when _T_1967 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 375:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2040 = eq(UInt<15>("h02074"), address) @[Conditional.scala 37:30] - when _T_2040 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[el2_pic_ctl.scala 384:44] + node _T_1968 = eq(UInt<15>("h02074"), address) @[Conditional.scala 37:30] + when _T_1968 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 376:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2041 = eq(UInt<15>("h02078"), address) @[Conditional.scala 37:30] - when _T_2041 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[el2_pic_ctl.scala 385:44] + node _T_1969 = eq(UInt<15>("h02078"), address) @[Conditional.scala 37:30] + when _T_1969 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 377:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2042 = eq(UInt<15>("h0207c"), address) @[Conditional.scala 37:30] - when _T_2042 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[el2_pic_ctl.scala 386:44] + node _T_1970 = eq(UInt<15>("h0207c"), address) @[Conditional.scala 37:30] + when _T_1970 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 378:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2043 = eq(UInt<15>("h04"), address) @[Conditional.scala 37:30] - when _T_2043 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[el2_pic_ctl.scala 387:44] + node _T_1971 = eq(UInt<15>("h04"), address) @[Conditional.scala 37:30] + when _T_1971 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 379:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2044 = eq(UInt<15>("h08"), address) @[Conditional.scala 37:30] - when _T_2044 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[el2_pic_ctl.scala 388:44] + node _T_1972 = eq(UInt<15>("h08"), address) @[Conditional.scala 37:30] + when _T_1972 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 380:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2045 = eq(UInt<15>("h0c"), address) @[Conditional.scala 37:30] - when _T_2045 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[el2_pic_ctl.scala 389:44] + node _T_1973 = eq(UInt<15>("h0c"), address) @[Conditional.scala 37:30] + when _T_1973 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 381:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2046 = eq(UInt<15>("h010"), address) @[Conditional.scala 37:30] - when _T_2046 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[el2_pic_ctl.scala 390:44] + node _T_1974 = eq(UInt<15>("h010"), address) @[Conditional.scala 37:30] + when _T_1974 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 382:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2047 = eq(UInt<15>("h014"), address) @[Conditional.scala 37:30] - when _T_2047 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[el2_pic_ctl.scala 391:44] + node _T_1975 = eq(UInt<15>("h014"), address) @[Conditional.scala 37:30] + when _T_1975 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 383:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2048 = eq(UInt<15>("h018"), address) @[Conditional.scala 37:30] - when _T_2048 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[el2_pic_ctl.scala 392:44] + node _T_1976 = eq(UInt<15>("h018"), address) @[Conditional.scala 37:30] + when _T_1976 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 384:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2049 = eq(UInt<15>("h01c"), address) @[Conditional.scala 37:30] - when _T_2049 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[el2_pic_ctl.scala 393:44] + node _T_1977 = eq(UInt<15>("h01c"), address) @[Conditional.scala 37:30] + when _T_1977 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 385:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2050 = eq(UInt<15>("h020"), address) @[Conditional.scala 37:30] - when _T_2050 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[el2_pic_ctl.scala 394:44] + node _T_1978 = eq(UInt<15>("h020"), address) @[Conditional.scala 37:30] + when _T_1978 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 386:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2051 = eq(UInt<15>("h024"), address) @[Conditional.scala 37:30] - when _T_2051 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[el2_pic_ctl.scala 395:44] + node _T_1979 = eq(UInt<15>("h024"), address) @[Conditional.scala 37:30] + when _T_1979 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 387:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2052 = eq(UInt<15>("h028"), address) @[Conditional.scala 37:30] - when _T_2052 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[el2_pic_ctl.scala 396:44] + node _T_1980 = eq(UInt<15>("h028"), address) @[Conditional.scala 37:30] + when _T_1980 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 388:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2053 = eq(UInt<15>("h02c"), address) @[Conditional.scala 37:30] - when _T_2053 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[el2_pic_ctl.scala 397:44] + node _T_1981 = eq(UInt<15>("h02c"), address) @[Conditional.scala 37:30] + when _T_1981 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 389:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2054 = eq(UInt<15>("h030"), address) @[Conditional.scala 37:30] - when _T_2054 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[el2_pic_ctl.scala 398:44] + node _T_1982 = eq(UInt<15>("h030"), address) @[Conditional.scala 37:30] + when _T_1982 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 390:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2055 = eq(UInt<15>("h034"), address) @[Conditional.scala 37:30] - when _T_2055 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[el2_pic_ctl.scala 399:44] + node _T_1983 = eq(UInt<15>("h034"), address) @[Conditional.scala 37:30] + when _T_1983 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 391:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2056 = eq(UInt<15>("h038"), address) @[Conditional.scala 37:30] - when _T_2056 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[el2_pic_ctl.scala 400:44] + node _T_1984 = eq(UInt<15>("h038"), address) @[Conditional.scala 37:30] + when _T_1984 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 392:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2057 = eq(UInt<15>("h03c"), address) @[Conditional.scala 37:30] - when _T_2057 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[el2_pic_ctl.scala 401:44] + node _T_1985 = eq(UInt<15>("h03c"), address) @[Conditional.scala 37:30] + when _T_1985 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 393:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2058 = eq(UInt<15>("h040"), address) @[Conditional.scala 37:30] - when _T_2058 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[el2_pic_ctl.scala 402:44] + node _T_1986 = eq(UInt<15>("h040"), address) @[Conditional.scala 37:30] + when _T_1986 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 394:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2059 = eq(UInt<15>("h044"), address) @[Conditional.scala 37:30] - when _T_2059 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[el2_pic_ctl.scala 403:44] + node _T_1987 = eq(UInt<15>("h044"), address) @[Conditional.scala 37:30] + when _T_1987 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 395:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2060 = eq(UInt<15>("h048"), address) @[Conditional.scala 37:30] - when _T_2060 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[el2_pic_ctl.scala 404:44] + node _T_1988 = eq(UInt<15>("h048"), address) @[Conditional.scala 37:30] + when _T_1988 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 396:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2061 = eq(UInt<15>("h04c"), address) @[Conditional.scala 37:30] - when _T_2061 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[el2_pic_ctl.scala 405:44] + node _T_1989 = eq(UInt<15>("h04c"), address) @[Conditional.scala 37:30] + when _T_1989 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 397:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2062 = eq(UInt<15>("h050"), address) @[Conditional.scala 37:30] - when _T_2062 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[el2_pic_ctl.scala 406:44] + node _T_1990 = eq(UInt<15>("h050"), address) @[Conditional.scala 37:30] + when _T_1990 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 398:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2063 = eq(UInt<15>("h054"), address) @[Conditional.scala 37:30] - when _T_2063 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[el2_pic_ctl.scala 407:44] + node _T_1991 = eq(UInt<15>("h054"), address) @[Conditional.scala 37:30] + when _T_1991 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 399:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2064 = eq(UInt<15>("h058"), address) @[Conditional.scala 37:30] - when _T_2064 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[el2_pic_ctl.scala 408:44] + node _T_1992 = eq(UInt<15>("h058"), address) @[Conditional.scala 37:30] + when _T_1992 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 400:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2065 = eq(UInt<15>("h05c"), address) @[Conditional.scala 37:30] - when _T_2065 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[el2_pic_ctl.scala 409:44] + node _T_1993 = eq(UInt<15>("h05c"), address) @[Conditional.scala 37:30] + when _T_1993 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 401:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2066 = eq(UInt<15>("h060"), address) @[Conditional.scala 37:30] - when _T_2066 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[el2_pic_ctl.scala 410:44] + node _T_1994 = eq(UInt<15>("h060"), address) @[Conditional.scala 37:30] + when _T_1994 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 402:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2067 = eq(UInt<15>("h064"), address) @[Conditional.scala 37:30] - when _T_2067 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[el2_pic_ctl.scala 411:44] + node _T_1995 = eq(UInt<15>("h064"), address) @[Conditional.scala 37:30] + when _T_1995 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 403:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2068 = eq(UInt<15>("h068"), address) @[Conditional.scala 37:30] - when _T_2068 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[el2_pic_ctl.scala 412:44] + node _T_1996 = eq(UInt<15>("h068"), address) @[Conditional.scala 37:30] + when _T_1996 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 404:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2069 = eq(UInt<15>("h06c"), address) @[Conditional.scala 37:30] - when _T_2069 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[el2_pic_ctl.scala 413:44] + node _T_1997 = eq(UInt<15>("h06c"), address) @[Conditional.scala 37:30] + when _T_1997 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 405:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2070 = eq(UInt<15>("h070"), address) @[Conditional.scala 37:30] - when _T_2070 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[el2_pic_ctl.scala 414:44] + node _T_1998 = eq(UInt<15>("h070"), address) @[Conditional.scala 37:30] + when _T_1998 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 406:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2071 = eq(UInt<15>("h074"), address) @[Conditional.scala 37:30] - when _T_2071 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[el2_pic_ctl.scala 415:44] + node _T_1999 = eq(UInt<15>("h074"), address) @[Conditional.scala 37:30] + when _T_1999 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 407:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2072 = eq(UInt<15>("h078"), address) @[Conditional.scala 37:30] - when _T_2072 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[el2_pic_ctl.scala 416:44] + node _T_2000 = eq(UInt<15>("h078"), address) @[Conditional.scala 37:30] + when _T_2000 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 408:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_2073 = eq(UInt<15>("h07c"), address) @[Conditional.scala 37:30] - when _T_2073 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[el2_pic_ctl.scala 417:44] + node _T_2001 = eq(UInt<15>("h07c"), address) @[Conditional.scala 37:30] + when _T_2001 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 409:44] skip @[Conditional.scala 39:67] diff --git a/el2_pic_ctrl.v b/el2_pic_ctrl.v index cc7309ed..6ce0525d 100644 --- a/el2_pic_ctrl.v +++ b/el2_pic_ctrl.v @@ -200,479 +200,479 @@ module el2_pic_ctrl( wire rvclkhdr_4_io_clk; // @[el2_lib.scala 483:22] wire rvclkhdr_4_io_en; // @[el2_lib.scala 483:22] wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 483:22] - wire pic_raddr_c1_clk = rvclkhdr_io_l1clk; // @[el2_pic_ctl.scala 109:42 el2_pic_ctl.scala 146:21] - reg [31:0] picm_raddr_ff; // @[el2_pic_ctl.scala 115:56] - wire pic_data_c1_clk = rvclkhdr_1_io_l1clk; // @[el2_pic_ctl.scala 110:42 el2_pic_ctl.scala 147:21] - reg [31:0] picm_waddr_ff; // @[el2_pic_ctl.scala 116:57] - reg picm_wren_ff; // @[el2_pic_ctl.scala 117:55] - reg picm_rden_ff; // @[el2_pic_ctl.scala 118:55] - reg picm_mken_ff; // @[el2_pic_ctl.scala 119:55] - reg [31:0] picm_wr_data_ff; // @[el2_pic_ctl.scala 120:58] - wire [31:0] _T_6 = picm_raddr_ff ^ 32'hf00c2000; // @[el2_pic_ctl.scala 122:59] - wire [31:0] temp_raddr_intenable_base_match = ~_T_6; // @[el2_pic_ctl.scala 122:43] - wire raddr_intenable_base_match = &temp_raddr_intenable_base_match[31:7]; // @[el2_pic_ctl.scala 123:89] - wire raddr_intpriority_base_match = picm_raddr_ff[31:7] == 25'h1e01800; // @[el2_pic_ctl.scala 125:71] - wire raddr_config_gw_base_match = picm_raddr_ff[31:7] == 25'h1e01880; // @[el2_pic_ctl.scala 126:71] - wire raddr_config_pic_match = picm_raddr_ff == 32'hf00c3000; // @[el2_pic_ctl.scala 127:71] - wire addr_intpend_base_match = picm_raddr_ff[31:6] == 26'h3c03040; // @[el2_pic_ctl.scala 128:71] - wire waddr_config_pic_match = picm_waddr_ff == 32'hf00c3000; // @[el2_pic_ctl.scala 130:71] - wire addr_clear_gw_base_match = picm_waddr_ff[31:7] == 25'h1e018a0; // @[el2_pic_ctl.scala 131:71] - wire waddr_intpriority_base_match = picm_waddr_ff[31:7] == 25'h1e01800; // @[el2_pic_ctl.scala 132:71] - wire waddr_intenable_base_match = picm_waddr_ff[31:7] == 25'h1e01840; // @[el2_pic_ctl.scala 133:71] - wire waddr_config_gw_base_match = picm_waddr_ff[31:7] == 25'h1e01880; // @[el2_pic_ctl.scala 134:71] - wire _T_17 = picm_rden_ff & picm_wren_ff; // @[el2_pic_ctl.scala 135:53] - wire _T_18 = picm_raddr_ff == picm_waddr_ff; // @[el2_pic_ctl.scala 135:86] - wire picm_bypass_ff = _T_17 & _T_18; // @[el2_pic_ctl.scala 135:68] - wire _T_19 = io_picm_mken | io_picm_rden; // @[el2_pic_ctl.scala 139:42] - wire _T_20 = waddr_intpriority_base_match & picm_wren_ff; // @[el2_pic_ctl.scala 141:59] - wire _T_21 = raddr_intpriority_base_match & picm_rden_ff; // @[el2_pic_ctl.scala 141:108] - wire _T_22 = _T_20 | _T_21; // @[el2_pic_ctl.scala 141:76] - wire _T_23 = waddr_intenable_base_match & picm_wren_ff; // @[el2_pic_ctl.scala 142:57] - wire _T_24 = raddr_intenable_base_match & picm_rden_ff; // @[el2_pic_ctl.scala 142:104] - wire _T_25 = _T_23 | _T_24; // @[el2_pic_ctl.scala 142:74] - wire _T_26 = waddr_config_gw_base_match & picm_wren_ff; // @[el2_pic_ctl.scala 143:59] - wire _T_27 = raddr_config_gw_base_match & picm_rden_ff; // @[el2_pic_ctl.scala 143:108] - wire _T_28 = _T_26 | _T_27; // @[el2_pic_ctl.scala 143:76] - reg [30:0] _T_33; // @[el2_lib.scala 176:81] - reg [30:0] _T_34; // @[el2_lib.scala 176:58] + wire pic_raddr_c1_clk = rvclkhdr_io_l1clk; // @[el2_pic_ctl.scala 101:42 el2_pic_ctl.scala 138:21] + reg [31:0] picm_raddr_ff; // @[el2_pic_ctl.scala 107:56] + wire pic_data_c1_clk = rvclkhdr_1_io_l1clk; // @[el2_pic_ctl.scala 102:42 el2_pic_ctl.scala 139:21] + reg [31:0] picm_waddr_ff; // @[el2_pic_ctl.scala 108:57] + reg picm_wren_ff; // @[el2_pic_ctl.scala 109:55] + reg picm_rden_ff; // @[el2_pic_ctl.scala 110:55] + reg picm_mken_ff; // @[el2_pic_ctl.scala 111:55] + reg [31:0] picm_wr_data_ff; // @[el2_pic_ctl.scala 112:58] + wire [31:0] _T_6 = picm_raddr_ff ^ 32'hf00c2000; // @[el2_pic_ctl.scala 114:59] + wire [31:0] temp_raddr_intenable_base_match = ~_T_6; // @[el2_pic_ctl.scala 114:43] + wire raddr_intenable_base_match = &temp_raddr_intenable_base_match[31:7]; // @[el2_pic_ctl.scala 115:89] + wire raddr_intpriority_base_match = picm_raddr_ff[31:7] == 25'h1e01800; // @[el2_pic_ctl.scala 117:71] + wire raddr_config_gw_base_match = picm_raddr_ff[31:7] == 25'h1e01880; // @[el2_pic_ctl.scala 118:71] + wire raddr_config_pic_match = picm_raddr_ff == 32'hf00c3000; // @[el2_pic_ctl.scala 119:71] + wire addr_intpend_base_match = picm_raddr_ff[31:6] == 26'h3c03040; // @[el2_pic_ctl.scala 120:71] + wire waddr_config_pic_match = picm_waddr_ff == 32'hf00c3000; // @[el2_pic_ctl.scala 122:71] + wire addr_clear_gw_base_match = picm_waddr_ff[31:7] == 25'h1e018a0; // @[el2_pic_ctl.scala 123:71] + wire waddr_intpriority_base_match = picm_waddr_ff[31:7] == 25'h1e01800; // @[el2_pic_ctl.scala 124:71] + wire waddr_intenable_base_match = picm_waddr_ff[31:7] == 25'h1e01840; // @[el2_pic_ctl.scala 125:71] + wire waddr_config_gw_base_match = picm_waddr_ff[31:7] == 25'h1e01880; // @[el2_pic_ctl.scala 126:71] + wire _T_17 = picm_rden_ff & picm_wren_ff; // @[el2_pic_ctl.scala 127:53] + wire _T_18 = picm_raddr_ff == picm_waddr_ff; // @[el2_pic_ctl.scala 127:86] + wire picm_bypass_ff = _T_17 & _T_18; // @[el2_pic_ctl.scala 127:68] + wire _T_19 = io_picm_mken | io_picm_rden; // @[el2_pic_ctl.scala 131:42] + wire _T_20 = waddr_intpriority_base_match & picm_wren_ff; // @[el2_pic_ctl.scala 133:59] + wire _T_21 = raddr_intpriority_base_match & picm_rden_ff; // @[el2_pic_ctl.scala 133:108] + wire _T_22 = _T_20 | _T_21; // @[el2_pic_ctl.scala 133:76] + wire _T_23 = waddr_intenable_base_match & picm_wren_ff; // @[el2_pic_ctl.scala 134:57] + wire _T_24 = raddr_intenable_base_match & picm_rden_ff; // @[el2_pic_ctl.scala 134:104] + wire _T_25 = _T_23 | _T_24; // @[el2_pic_ctl.scala 134:74] + wire _T_26 = waddr_config_gw_base_match & picm_wren_ff; // @[el2_pic_ctl.scala 135:59] + wire _T_27 = raddr_config_gw_base_match & picm_rden_ff; // @[el2_pic_ctl.scala 135:108] + wire _T_28 = _T_26 | _T_27; // @[el2_pic_ctl.scala 135:76] + reg [30:0] _T_33; // @[el2_lib.scala 177:81] + reg [30:0] _T_34; // @[el2_lib.scala 177:58] wire [31:0] extintsrc_req_sync = {_T_34,io_extintsrc_req[0]}; // @[Cat.scala 29:58] - wire _T_37 = picm_waddr_ff[6:2] == 5'h1; // @[el2_pic_ctl.scala 155:139] - wire _T_38 = waddr_intpriority_base_match & _T_37; // @[el2_pic_ctl.scala 155:106] - wire intpriority_reg_we_1 = _T_38 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] - wire _T_40 = picm_waddr_ff[6:2] == 5'h2; // @[el2_pic_ctl.scala 155:139] - wire _T_41 = waddr_intpriority_base_match & _T_40; // @[el2_pic_ctl.scala 155:106] - wire intpriority_reg_we_2 = _T_41 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] - wire _T_43 = picm_waddr_ff[6:2] == 5'h3; // @[el2_pic_ctl.scala 155:139] - wire _T_44 = waddr_intpriority_base_match & _T_43; // @[el2_pic_ctl.scala 155:106] - wire intpriority_reg_we_3 = _T_44 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] - wire _T_46 = picm_waddr_ff[6:2] == 5'h4; // @[el2_pic_ctl.scala 155:139] - wire _T_47 = waddr_intpriority_base_match & _T_46; // @[el2_pic_ctl.scala 155:106] - wire intpriority_reg_we_4 = _T_47 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] - wire _T_49 = picm_waddr_ff[6:2] == 5'h5; // @[el2_pic_ctl.scala 155:139] - wire _T_50 = waddr_intpriority_base_match & _T_49; // @[el2_pic_ctl.scala 155:106] - wire intpriority_reg_we_5 = _T_50 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] - wire _T_52 = picm_waddr_ff[6:2] == 5'h6; // @[el2_pic_ctl.scala 155:139] - wire _T_53 = waddr_intpriority_base_match & _T_52; // @[el2_pic_ctl.scala 155:106] - wire intpriority_reg_we_6 = _T_53 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] - wire _T_55 = picm_waddr_ff[6:2] == 5'h7; // @[el2_pic_ctl.scala 155:139] - wire _T_56 = waddr_intpriority_base_match & _T_55; // @[el2_pic_ctl.scala 155:106] - wire intpriority_reg_we_7 = _T_56 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] - wire _T_58 = picm_waddr_ff[6:2] == 5'h8; // @[el2_pic_ctl.scala 155:139] - wire _T_59 = waddr_intpriority_base_match & _T_58; // @[el2_pic_ctl.scala 155:106] - wire intpriority_reg_we_8 = _T_59 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] - wire _T_61 = picm_waddr_ff[6:2] == 5'h9; // @[el2_pic_ctl.scala 155:139] - wire _T_62 = waddr_intpriority_base_match & _T_61; // @[el2_pic_ctl.scala 155:106] - wire intpriority_reg_we_9 = _T_62 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] - wire _T_64 = picm_waddr_ff[6:2] == 5'ha; // @[el2_pic_ctl.scala 155:139] - wire _T_65 = waddr_intpriority_base_match & _T_64; // @[el2_pic_ctl.scala 155:106] - wire intpriority_reg_we_10 = _T_65 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] - wire _T_67 = picm_waddr_ff[6:2] == 5'hb; // @[el2_pic_ctl.scala 155:139] - wire _T_68 = waddr_intpriority_base_match & _T_67; // @[el2_pic_ctl.scala 155:106] - wire intpriority_reg_we_11 = _T_68 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] - wire _T_70 = picm_waddr_ff[6:2] == 5'hc; // @[el2_pic_ctl.scala 155:139] - wire _T_71 = waddr_intpriority_base_match & _T_70; // @[el2_pic_ctl.scala 155:106] - wire intpriority_reg_we_12 = _T_71 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] - wire _T_73 = picm_waddr_ff[6:2] == 5'hd; // @[el2_pic_ctl.scala 155:139] - wire _T_74 = waddr_intpriority_base_match & _T_73; // @[el2_pic_ctl.scala 155:106] - wire intpriority_reg_we_13 = _T_74 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] - wire _T_76 = picm_waddr_ff[6:2] == 5'he; // @[el2_pic_ctl.scala 155:139] - wire _T_77 = waddr_intpriority_base_match & _T_76; // @[el2_pic_ctl.scala 155:106] - wire intpriority_reg_we_14 = _T_77 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] - wire _T_79 = picm_waddr_ff[6:2] == 5'hf; // @[el2_pic_ctl.scala 155:139] - wire _T_80 = waddr_intpriority_base_match & _T_79; // @[el2_pic_ctl.scala 155:106] - wire intpriority_reg_we_15 = _T_80 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] - wire _T_82 = picm_waddr_ff[6:2] == 5'h10; // @[el2_pic_ctl.scala 155:139] - wire _T_83 = waddr_intpriority_base_match & _T_82; // @[el2_pic_ctl.scala 155:106] - wire intpriority_reg_we_16 = _T_83 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] - wire _T_85 = picm_waddr_ff[6:2] == 5'h11; // @[el2_pic_ctl.scala 155:139] - wire _T_86 = waddr_intpriority_base_match & _T_85; // @[el2_pic_ctl.scala 155:106] - wire intpriority_reg_we_17 = _T_86 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] - wire _T_88 = picm_waddr_ff[6:2] == 5'h12; // @[el2_pic_ctl.scala 155:139] - wire _T_89 = waddr_intpriority_base_match & _T_88; // @[el2_pic_ctl.scala 155:106] - wire intpriority_reg_we_18 = _T_89 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] - wire _T_91 = picm_waddr_ff[6:2] == 5'h13; // @[el2_pic_ctl.scala 155:139] - wire _T_92 = waddr_intpriority_base_match & _T_91; // @[el2_pic_ctl.scala 155:106] - wire intpriority_reg_we_19 = _T_92 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] - wire _T_94 = picm_waddr_ff[6:2] == 5'h14; // @[el2_pic_ctl.scala 155:139] - wire _T_95 = waddr_intpriority_base_match & _T_94; // @[el2_pic_ctl.scala 155:106] - wire intpriority_reg_we_20 = _T_95 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] - wire _T_97 = picm_waddr_ff[6:2] == 5'h15; // @[el2_pic_ctl.scala 155:139] - wire _T_98 = waddr_intpriority_base_match & _T_97; // @[el2_pic_ctl.scala 155:106] - wire intpriority_reg_we_21 = _T_98 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] - wire _T_100 = picm_waddr_ff[6:2] == 5'h16; // @[el2_pic_ctl.scala 155:139] - wire _T_101 = waddr_intpriority_base_match & _T_100; // @[el2_pic_ctl.scala 155:106] - wire intpriority_reg_we_22 = _T_101 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] - wire _T_103 = picm_waddr_ff[6:2] == 5'h17; // @[el2_pic_ctl.scala 155:139] - wire _T_104 = waddr_intpriority_base_match & _T_103; // @[el2_pic_ctl.scala 155:106] - wire intpriority_reg_we_23 = _T_104 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] - wire _T_106 = picm_waddr_ff[6:2] == 5'h18; // @[el2_pic_ctl.scala 155:139] - wire _T_107 = waddr_intpriority_base_match & _T_106; // @[el2_pic_ctl.scala 155:106] - wire intpriority_reg_we_24 = _T_107 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] - wire _T_109 = picm_waddr_ff[6:2] == 5'h19; // @[el2_pic_ctl.scala 155:139] - wire _T_110 = waddr_intpriority_base_match & _T_109; // @[el2_pic_ctl.scala 155:106] - wire intpriority_reg_we_25 = _T_110 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] - wire _T_112 = picm_waddr_ff[6:2] == 5'h1a; // @[el2_pic_ctl.scala 155:139] - wire _T_113 = waddr_intpriority_base_match & _T_112; // @[el2_pic_ctl.scala 155:106] - wire intpriority_reg_we_26 = _T_113 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] - wire _T_115 = picm_waddr_ff[6:2] == 5'h1b; // @[el2_pic_ctl.scala 155:139] - wire _T_116 = waddr_intpriority_base_match & _T_115; // @[el2_pic_ctl.scala 155:106] - wire intpriority_reg_we_27 = _T_116 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] - wire _T_118 = picm_waddr_ff[6:2] == 5'h1c; // @[el2_pic_ctl.scala 155:139] - wire _T_119 = waddr_intpriority_base_match & _T_118; // @[el2_pic_ctl.scala 155:106] - wire intpriority_reg_we_28 = _T_119 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] - wire _T_121 = picm_waddr_ff[6:2] == 5'h1d; // @[el2_pic_ctl.scala 155:139] - wire _T_122 = waddr_intpriority_base_match & _T_121; // @[el2_pic_ctl.scala 155:106] - wire intpriority_reg_we_29 = _T_122 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] - wire _T_124 = picm_waddr_ff[6:2] == 5'h1e; // @[el2_pic_ctl.scala 155:139] - wire _T_125 = waddr_intpriority_base_match & _T_124; // @[el2_pic_ctl.scala 155:106] - wire intpriority_reg_we_30 = _T_125 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] - wire _T_127 = picm_waddr_ff[6:2] == 5'h1f; // @[el2_pic_ctl.scala 155:139] - wire _T_128 = waddr_intpriority_base_match & _T_127; // @[el2_pic_ctl.scala 155:106] - wire intpriority_reg_we_31 = _T_128 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] - wire _T_130 = picm_raddr_ff[6:2] == 5'h1; // @[el2_pic_ctl.scala 156:139] - wire _T_131 = raddr_intpriority_base_match & _T_130; // @[el2_pic_ctl.scala 156:106] - wire intpriority_reg_re_1 = _T_131 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] - wire _T_133 = picm_raddr_ff[6:2] == 5'h2; // @[el2_pic_ctl.scala 156:139] - wire _T_134 = raddr_intpriority_base_match & _T_133; // @[el2_pic_ctl.scala 156:106] - wire intpriority_reg_re_2 = _T_134 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] - wire _T_136 = picm_raddr_ff[6:2] == 5'h3; // @[el2_pic_ctl.scala 156:139] - wire _T_137 = raddr_intpriority_base_match & _T_136; // @[el2_pic_ctl.scala 156:106] - wire intpriority_reg_re_3 = _T_137 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] - wire _T_139 = picm_raddr_ff[6:2] == 5'h4; // @[el2_pic_ctl.scala 156:139] - wire _T_140 = raddr_intpriority_base_match & _T_139; // @[el2_pic_ctl.scala 156:106] - wire intpriority_reg_re_4 = _T_140 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] - wire _T_142 = picm_raddr_ff[6:2] == 5'h5; // @[el2_pic_ctl.scala 156:139] - wire _T_143 = raddr_intpriority_base_match & _T_142; // @[el2_pic_ctl.scala 156:106] - wire intpriority_reg_re_5 = _T_143 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] - wire _T_145 = picm_raddr_ff[6:2] == 5'h6; // @[el2_pic_ctl.scala 156:139] - wire _T_146 = raddr_intpriority_base_match & _T_145; // @[el2_pic_ctl.scala 156:106] - wire intpriority_reg_re_6 = _T_146 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] - wire _T_148 = picm_raddr_ff[6:2] == 5'h7; // @[el2_pic_ctl.scala 156:139] - wire _T_149 = raddr_intpriority_base_match & _T_148; // @[el2_pic_ctl.scala 156:106] - wire intpriority_reg_re_7 = _T_149 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] - wire _T_151 = picm_raddr_ff[6:2] == 5'h8; // @[el2_pic_ctl.scala 156:139] - wire _T_152 = raddr_intpriority_base_match & _T_151; // @[el2_pic_ctl.scala 156:106] - wire intpriority_reg_re_8 = _T_152 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] - wire _T_154 = picm_raddr_ff[6:2] == 5'h9; // @[el2_pic_ctl.scala 156:139] - wire _T_155 = raddr_intpriority_base_match & _T_154; // @[el2_pic_ctl.scala 156:106] - wire intpriority_reg_re_9 = _T_155 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] - wire _T_157 = picm_raddr_ff[6:2] == 5'ha; // @[el2_pic_ctl.scala 156:139] - wire _T_158 = raddr_intpriority_base_match & _T_157; // @[el2_pic_ctl.scala 156:106] - wire intpriority_reg_re_10 = _T_158 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] - wire _T_160 = picm_raddr_ff[6:2] == 5'hb; // @[el2_pic_ctl.scala 156:139] - wire _T_161 = raddr_intpriority_base_match & _T_160; // @[el2_pic_ctl.scala 156:106] - wire intpriority_reg_re_11 = _T_161 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] - wire _T_163 = picm_raddr_ff[6:2] == 5'hc; // @[el2_pic_ctl.scala 156:139] - wire _T_164 = raddr_intpriority_base_match & _T_163; // @[el2_pic_ctl.scala 156:106] - wire intpriority_reg_re_12 = _T_164 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] - wire _T_166 = picm_raddr_ff[6:2] == 5'hd; // @[el2_pic_ctl.scala 156:139] - wire _T_167 = raddr_intpriority_base_match & _T_166; // @[el2_pic_ctl.scala 156:106] - wire intpriority_reg_re_13 = _T_167 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] - wire _T_169 = picm_raddr_ff[6:2] == 5'he; // @[el2_pic_ctl.scala 156:139] - wire _T_170 = raddr_intpriority_base_match & _T_169; // @[el2_pic_ctl.scala 156:106] - wire intpriority_reg_re_14 = _T_170 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] - wire _T_172 = picm_raddr_ff[6:2] == 5'hf; // @[el2_pic_ctl.scala 156:139] - wire _T_173 = raddr_intpriority_base_match & _T_172; // @[el2_pic_ctl.scala 156:106] - wire intpriority_reg_re_15 = _T_173 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] - wire _T_175 = picm_raddr_ff[6:2] == 5'h10; // @[el2_pic_ctl.scala 156:139] - wire _T_176 = raddr_intpriority_base_match & _T_175; // @[el2_pic_ctl.scala 156:106] - wire intpriority_reg_re_16 = _T_176 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] - wire _T_178 = picm_raddr_ff[6:2] == 5'h11; // @[el2_pic_ctl.scala 156:139] - wire _T_179 = raddr_intpriority_base_match & _T_178; // @[el2_pic_ctl.scala 156:106] - wire intpriority_reg_re_17 = _T_179 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] - wire _T_181 = picm_raddr_ff[6:2] == 5'h12; // @[el2_pic_ctl.scala 156:139] - wire _T_182 = raddr_intpriority_base_match & _T_181; // @[el2_pic_ctl.scala 156:106] - wire intpriority_reg_re_18 = _T_182 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] - wire _T_184 = picm_raddr_ff[6:2] == 5'h13; // @[el2_pic_ctl.scala 156:139] - wire _T_185 = raddr_intpriority_base_match & _T_184; // @[el2_pic_ctl.scala 156:106] - wire intpriority_reg_re_19 = _T_185 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] - wire _T_187 = picm_raddr_ff[6:2] == 5'h14; // @[el2_pic_ctl.scala 156:139] - wire _T_188 = raddr_intpriority_base_match & _T_187; // @[el2_pic_ctl.scala 156:106] - wire intpriority_reg_re_20 = _T_188 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] - wire _T_190 = picm_raddr_ff[6:2] == 5'h15; // @[el2_pic_ctl.scala 156:139] - wire _T_191 = raddr_intpriority_base_match & _T_190; // @[el2_pic_ctl.scala 156:106] - wire intpriority_reg_re_21 = _T_191 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] - wire _T_193 = picm_raddr_ff[6:2] == 5'h16; // @[el2_pic_ctl.scala 156:139] - wire _T_194 = raddr_intpriority_base_match & _T_193; // @[el2_pic_ctl.scala 156:106] - wire intpriority_reg_re_22 = _T_194 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] - wire _T_196 = picm_raddr_ff[6:2] == 5'h17; // @[el2_pic_ctl.scala 156:139] - wire _T_197 = raddr_intpriority_base_match & _T_196; // @[el2_pic_ctl.scala 156:106] - wire intpriority_reg_re_23 = _T_197 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] - wire _T_199 = picm_raddr_ff[6:2] == 5'h18; // @[el2_pic_ctl.scala 156:139] - wire _T_200 = raddr_intpriority_base_match & _T_199; // @[el2_pic_ctl.scala 156:106] - wire intpriority_reg_re_24 = _T_200 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] - wire _T_202 = picm_raddr_ff[6:2] == 5'h19; // @[el2_pic_ctl.scala 156:139] - wire _T_203 = raddr_intpriority_base_match & _T_202; // @[el2_pic_ctl.scala 156:106] - wire intpriority_reg_re_25 = _T_203 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] - wire _T_205 = picm_raddr_ff[6:2] == 5'h1a; // @[el2_pic_ctl.scala 156:139] - wire _T_206 = raddr_intpriority_base_match & _T_205; // @[el2_pic_ctl.scala 156:106] - wire intpriority_reg_re_26 = _T_206 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] - wire _T_208 = picm_raddr_ff[6:2] == 5'h1b; // @[el2_pic_ctl.scala 156:139] - wire _T_209 = raddr_intpriority_base_match & _T_208; // @[el2_pic_ctl.scala 156:106] - wire intpriority_reg_re_27 = _T_209 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] - wire _T_211 = picm_raddr_ff[6:2] == 5'h1c; // @[el2_pic_ctl.scala 156:139] - wire _T_212 = raddr_intpriority_base_match & _T_211; // @[el2_pic_ctl.scala 156:106] - wire intpriority_reg_re_28 = _T_212 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] - wire _T_214 = picm_raddr_ff[6:2] == 5'h1d; // @[el2_pic_ctl.scala 156:139] - wire _T_215 = raddr_intpriority_base_match & _T_214; // @[el2_pic_ctl.scala 156:106] - wire intpriority_reg_re_29 = _T_215 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] - wire _T_217 = picm_raddr_ff[6:2] == 5'h1e; // @[el2_pic_ctl.scala 156:139] - wire _T_218 = raddr_intpriority_base_match & _T_217; // @[el2_pic_ctl.scala 156:106] - wire intpriority_reg_re_30 = _T_218 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] - wire _T_220 = picm_raddr_ff[6:2] == 5'h1f; // @[el2_pic_ctl.scala 156:139] - wire _T_221 = raddr_intpriority_base_match & _T_220; // @[el2_pic_ctl.scala 156:106] - wire intpriority_reg_re_31 = _T_221 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] - wire _T_224 = waddr_intenable_base_match & _T_37; // @[el2_pic_ctl.scala 157:106] - wire intenable_reg_we_1 = _T_224 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] - wire _T_227 = waddr_intenable_base_match & _T_40; // @[el2_pic_ctl.scala 157:106] - wire intenable_reg_we_2 = _T_227 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] - wire _T_230 = waddr_intenable_base_match & _T_43; // @[el2_pic_ctl.scala 157:106] - wire intenable_reg_we_3 = _T_230 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] - wire _T_233 = waddr_intenable_base_match & _T_46; // @[el2_pic_ctl.scala 157:106] - wire intenable_reg_we_4 = _T_233 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] - wire _T_236 = waddr_intenable_base_match & _T_49; // @[el2_pic_ctl.scala 157:106] - wire intenable_reg_we_5 = _T_236 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] - wire _T_239 = waddr_intenable_base_match & _T_52; // @[el2_pic_ctl.scala 157:106] - wire intenable_reg_we_6 = _T_239 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] - wire _T_242 = waddr_intenable_base_match & _T_55; // @[el2_pic_ctl.scala 157:106] - wire intenable_reg_we_7 = _T_242 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] - wire _T_245 = waddr_intenable_base_match & _T_58; // @[el2_pic_ctl.scala 157:106] - wire intenable_reg_we_8 = _T_245 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] - wire _T_248 = waddr_intenable_base_match & _T_61; // @[el2_pic_ctl.scala 157:106] - wire intenable_reg_we_9 = _T_248 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] - wire _T_251 = waddr_intenable_base_match & _T_64; // @[el2_pic_ctl.scala 157:106] - wire intenable_reg_we_10 = _T_251 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] - wire _T_254 = waddr_intenable_base_match & _T_67; // @[el2_pic_ctl.scala 157:106] - wire intenable_reg_we_11 = _T_254 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] - wire _T_257 = waddr_intenable_base_match & _T_70; // @[el2_pic_ctl.scala 157:106] - wire intenable_reg_we_12 = _T_257 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] - wire _T_260 = waddr_intenable_base_match & _T_73; // @[el2_pic_ctl.scala 157:106] - wire intenable_reg_we_13 = _T_260 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] - wire _T_263 = waddr_intenable_base_match & _T_76; // @[el2_pic_ctl.scala 157:106] - wire intenable_reg_we_14 = _T_263 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] - wire _T_266 = waddr_intenable_base_match & _T_79; // @[el2_pic_ctl.scala 157:106] - wire intenable_reg_we_15 = _T_266 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] - wire _T_269 = waddr_intenable_base_match & _T_82; // @[el2_pic_ctl.scala 157:106] - wire intenable_reg_we_16 = _T_269 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] - wire _T_272 = waddr_intenable_base_match & _T_85; // @[el2_pic_ctl.scala 157:106] - wire intenable_reg_we_17 = _T_272 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] - wire _T_275 = waddr_intenable_base_match & _T_88; // @[el2_pic_ctl.scala 157:106] - wire intenable_reg_we_18 = _T_275 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] - wire _T_278 = waddr_intenable_base_match & _T_91; // @[el2_pic_ctl.scala 157:106] - wire intenable_reg_we_19 = _T_278 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] - wire _T_281 = waddr_intenable_base_match & _T_94; // @[el2_pic_ctl.scala 157:106] - wire intenable_reg_we_20 = _T_281 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] - wire _T_284 = waddr_intenable_base_match & _T_97; // @[el2_pic_ctl.scala 157:106] - wire intenable_reg_we_21 = _T_284 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] - wire _T_287 = waddr_intenable_base_match & _T_100; // @[el2_pic_ctl.scala 157:106] - wire intenable_reg_we_22 = _T_287 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] - wire _T_290 = waddr_intenable_base_match & _T_103; // @[el2_pic_ctl.scala 157:106] - wire intenable_reg_we_23 = _T_290 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] - wire _T_293 = waddr_intenable_base_match & _T_106; // @[el2_pic_ctl.scala 157:106] - wire intenable_reg_we_24 = _T_293 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] - wire _T_296 = waddr_intenable_base_match & _T_109; // @[el2_pic_ctl.scala 157:106] - wire intenable_reg_we_25 = _T_296 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] - wire _T_299 = waddr_intenable_base_match & _T_112; // @[el2_pic_ctl.scala 157:106] - wire intenable_reg_we_26 = _T_299 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] - wire _T_302 = waddr_intenable_base_match & _T_115; // @[el2_pic_ctl.scala 157:106] - wire intenable_reg_we_27 = _T_302 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] - wire _T_305 = waddr_intenable_base_match & _T_118; // @[el2_pic_ctl.scala 157:106] - wire intenable_reg_we_28 = _T_305 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] - wire _T_308 = waddr_intenable_base_match & _T_121; // @[el2_pic_ctl.scala 157:106] - wire intenable_reg_we_29 = _T_308 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] - wire _T_311 = waddr_intenable_base_match & _T_124; // @[el2_pic_ctl.scala 157:106] - wire intenable_reg_we_30 = _T_311 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] - wire _T_314 = waddr_intenable_base_match & _T_127; // @[el2_pic_ctl.scala 157:106] - wire intenable_reg_we_31 = _T_314 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] - wire _T_407 = raddr_intenable_base_match & _T_220; // @[el2_pic_ctl.scala 158:106] - wire intenable_reg_re_31 = _T_407 & picm_rden_ff; // @[el2_pic_ctl.scala 158:153] - wire _T_410 = waddr_config_gw_base_match & _T_37; // @[el2_pic_ctl.scala 159:106] - wire gw_config_reg_we_1 = _T_410 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] - wire _T_413 = waddr_config_gw_base_match & _T_40; // @[el2_pic_ctl.scala 159:106] - wire gw_config_reg_we_2 = _T_413 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] - wire _T_416 = waddr_config_gw_base_match & _T_43; // @[el2_pic_ctl.scala 159:106] - wire gw_config_reg_we_3 = _T_416 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] - wire _T_419 = waddr_config_gw_base_match & _T_46; // @[el2_pic_ctl.scala 159:106] - wire gw_config_reg_we_4 = _T_419 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] - wire _T_422 = waddr_config_gw_base_match & _T_49; // @[el2_pic_ctl.scala 159:106] - wire gw_config_reg_we_5 = _T_422 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] - wire _T_425 = waddr_config_gw_base_match & _T_52; // @[el2_pic_ctl.scala 159:106] - wire gw_config_reg_we_6 = _T_425 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] - wire _T_428 = waddr_config_gw_base_match & _T_55; // @[el2_pic_ctl.scala 159:106] - wire gw_config_reg_we_7 = _T_428 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] - wire _T_431 = waddr_config_gw_base_match & _T_58; // @[el2_pic_ctl.scala 159:106] - wire gw_config_reg_we_8 = _T_431 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] - wire _T_434 = waddr_config_gw_base_match & _T_61; // @[el2_pic_ctl.scala 159:106] - wire gw_config_reg_we_9 = _T_434 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] - wire _T_437 = waddr_config_gw_base_match & _T_64; // @[el2_pic_ctl.scala 159:106] - wire gw_config_reg_we_10 = _T_437 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] - wire _T_440 = waddr_config_gw_base_match & _T_67; // @[el2_pic_ctl.scala 159:106] - wire gw_config_reg_we_11 = _T_440 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] - wire _T_443 = waddr_config_gw_base_match & _T_70; // @[el2_pic_ctl.scala 159:106] - wire gw_config_reg_we_12 = _T_443 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] - wire _T_446 = waddr_config_gw_base_match & _T_73; // @[el2_pic_ctl.scala 159:106] - wire gw_config_reg_we_13 = _T_446 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] - wire _T_449 = waddr_config_gw_base_match & _T_76; // @[el2_pic_ctl.scala 159:106] - wire gw_config_reg_we_14 = _T_449 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] - wire _T_452 = waddr_config_gw_base_match & _T_79; // @[el2_pic_ctl.scala 159:106] - wire gw_config_reg_we_15 = _T_452 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] - wire _T_455 = waddr_config_gw_base_match & _T_82; // @[el2_pic_ctl.scala 159:106] - wire gw_config_reg_we_16 = _T_455 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] - wire _T_458 = waddr_config_gw_base_match & _T_85; // @[el2_pic_ctl.scala 159:106] - wire gw_config_reg_we_17 = _T_458 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] - wire _T_461 = waddr_config_gw_base_match & _T_88; // @[el2_pic_ctl.scala 159:106] - wire gw_config_reg_we_18 = _T_461 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] - wire _T_464 = waddr_config_gw_base_match & _T_91; // @[el2_pic_ctl.scala 159:106] - wire gw_config_reg_we_19 = _T_464 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] - wire _T_467 = waddr_config_gw_base_match & _T_94; // @[el2_pic_ctl.scala 159:106] - wire gw_config_reg_we_20 = _T_467 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] - wire _T_470 = waddr_config_gw_base_match & _T_97; // @[el2_pic_ctl.scala 159:106] - wire gw_config_reg_we_21 = _T_470 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] - wire _T_473 = waddr_config_gw_base_match & _T_100; // @[el2_pic_ctl.scala 159:106] - wire gw_config_reg_we_22 = _T_473 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] - wire _T_476 = waddr_config_gw_base_match & _T_103; // @[el2_pic_ctl.scala 159:106] - wire gw_config_reg_we_23 = _T_476 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] - wire _T_479 = waddr_config_gw_base_match & _T_106; // @[el2_pic_ctl.scala 159:106] - wire gw_config_reg_we_24 = _T_479 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] - wire _T_482 = waddr_config_gw_base_match & _T_109; // @[el2_pic_ctl.scala 159:106] - wire gw_config_reg_we_25 = _T_482 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] - wire _T_485 = waddr_config_gw_base_match & _T_112; // @[el2_pic_ctl.scala 159:106] - wire gw_config_reg_we_26 = _T_485 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] - wire _T_488 = waddr_config_gw_base_match & _T_115; // @[el2_pic_ctl.scala 159:106] - wire gw_config_reg_we_27 = _T_488 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] - wire _T_491 = waddr_config_gw_base_match & _T_118; // @[el2_pic_ctl.scala 159:106] - wire gw_config_reg_we_28 = _T_491 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] - wire _T_494 = waddr_config_gw_base_match & _T_121; // @[el2_pic_ctl.scala 159:106] - wire gw_config_reg_we_29 = _T_494 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] - wire _T_497 = waddr_config_gw_base_match & _T_124; // @[el2_pic_ctl.scala 159:106] - wire gw_config_reg_we_30 = _T_497 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] - wire _T_500 = waddr_config_gw_base_match & _T_127; // @[el2_pic_ctl.scala 159:106] - wire gw_config_reg_we_31 = _T_500 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] - wire _T_503 = raddr_config_gw_base_match & _T_130; // @[el2_pic_ctl.scala 160:106] - wire gw_config_reg_re_1 = _T_503 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] - wire _T_506 = raddr_config_gw_base_match & _T_133; // @[el2_pic_ctl.scala 160:106] - wire gw_config_reg_re_2 = _T_506 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] - wire _T_509 = raddr_config_gw_base_match & _T_136; // @[el2_pic_ctl.scala 160:106] - wire gw_config_reg_re_3 = _T_509 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] - wire _T_512 = raddr_config_gw_base_match & _T_139; // @[el2_pic_ctl.scala 160:106] - wire gw_config_reg_re_4 = _T_512 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] - wire _T_515 = raddr_config_gw_base_match & _T_142; // @[el2_pic_ctl.scala 160:106] - wire gw_config_reg_re_5 = _T_515 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] - wire _T_518 = raddr_config_gw_base_match & _T_145; // @[el2_pic_ctl.scala 160:106] - wire gw_config_reg_re_6 = _T_518 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] - wire _T_521 = raddr_config_gw_base_match & _T_148; // @[el2_pic_ctl.scala 160:106] - wire gw_config_reg_re_7 = _T_521 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] - wire _T_524 = raddr_config_gw_base_match & _T_151; // @[el2_pic_ctl.scala 160:106] - wire gw_config_reg_re_8 = _T_524 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] - wire _T_527 = raddr_config_gw_base_match & _T_154; // @[el2_pic_ctl.scala 160:106] - wire gw_config_reg_re_9 = _T_527 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] - wire _T_530 = raddr_config_gw_base_match & _T_157; // @[el2_pic_ctl.scala 160:106] - wire gw_config_reg_re_10 = _T_530 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] - wire _T_533 = raddr_config_gw_base_match & _T_160; // @[el2_pic_ctl.scala 160:106] - wire gw_config_reg_re_11 = _T_533 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] - wire _T_536 = raddr_config_gw_base_match & _T_163; // @[el2_pic_ctl.scala 160:106] - wire gw_config_reg_re_12 = _T_536 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] - wire _T_539 = raddr_config_gw_base_match & _T_166; // @[el2_pic_ctl.scala 160:106] - wire gw_config_reg_re_13 = _T_539 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] - wire _T_542 = raddr_config_gw_base_match & _T_169; // @[el2_pic_ctl.scala 160:106] - wire gw_config_reg_re_14 = _T_542 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] - wire _T_545 = raddr_config_gw_base_match & _T_172; // @[el2_pic_ctl.scala 160:106] - wire gw_config_reg_re_15 = _T_545 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] - wire _T_548 = raddr_config_gw_base_match & _T_175; // @[el2_pic_ctl.scala 160:106] - wire gw_config_reg_re_16 = _T_548 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] - wire _T_551 = raddr_config_gw_base_match & _T_178; // @[el2_pic_ctl.scala 160:106] - wire gw_config_reg_re_17 = _T_551 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] - wire _T_554 = raddr_config_gw_base_match & _T_181; // @[el2_pic_ctl.scala 160:106] - wire gw_config_reg_re_18 = _T_554 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] - wire _T_557 = raddr_config_gw_base_match & _T_184; // @[el2_pic_ctl.scala 160:106] - wire gw_config_reg_re_19 = _T_557 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] - wire _T_560 = raddr_config_gw_base_match & _T_187; // @[el2_pic_ctl.scala 160:106] - wire gw_config_reg_re_20 = _T_560 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] - wire _T_563 = raddr_config_gw_base_match & _T_190; // @[el2_pic_ctl.scala 160:106] - wire gw_config_reg_re_21 = _T_563 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] - wire _T_566 = raddr_config_gw_base_match & _T_193; // @[el2_pic_ctl.scala 160:106] - wire gw_config_reg_re_22 = _T_566 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] - wire _T_569 = raddr_config_gw_base_match & _T_196; // @[el2_pic_ctl.scala 160:106] - wire gw_config_reg_re_23 = _T_569 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] - wire _T_572 = raddr_config_gw_base_match & _T_199; // @[el2_pic_ctl.scala 160:106] - wire gw_config_reg_re_24 = _T_572 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] - wire _T_575 = raddr_config_gw_base_match & _T_202; // @[el2_pic_ctl.scala 160:106] - wire gw_config_reg_re_25 = _T_575 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] - wire _T_578 = raddr_config_gw_base_match & _T_205; // @[el2_pic_ctl.scala 160:106] - wire gw_config_reg_re_26 = _T_578 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] - wire _T_581 = raddr_config_gw_base_match & _T_208; // @[el2_pic_ctl.scala 160:106] - wire gw_config_reg_re_27 = _T_581 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] - wire _T_584 = raddr_config_gw_base_match & _T_211; // @[el2_pic_ctl.scala 160:106] - wire gw_config_reg_re_28 = _T_584 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] - wire _T_587 = raddr_config_gw_base_match & _T_214; // @[el2_pic_ctl.scala 160:106] - wire gw_config_reg_re_29 = _T_587 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] - wire _T_590 = raddr_config_gw_base_match & _T_217; // @[el2_pic_ctl.scala 160:106] - wire gw_config_reg_re_30 = _T_590 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] - wire _T_593 = raddr_config_gw_base_match & _T_220; // @[el2_pic_ctl.scala 160:106] - wire gw_config_reg_re_31 = _T_593 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] - wire _T_596 = addr_clear_gw_base_match & _T_37; // @[el2_pic_ctl.scala 161:106] - wire gw_clear_reg_we_1 = _T_596 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] - wire _T_599 = addr_clear_gw_base_match & _T_40; // @[el2_pic_ctl.scala 161:106] - wire gw_clear_reg_we_2 = _T_599 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] - wire _T_602 = addr_clear_gw_base_match & _T_43; // @[el2_pic_ctl.scala 161:106] - wire gw_clear_reg_we_3 = _T_602 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] - wire _T_605 = addr_clear_gw_base_match & _T_46; // @[el2_pic_ctl.scala 161:106] - wire gw_clear_reg_we_4 = _T_605 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] - wire _T_608 = addr_clear_gw_base_match & _T_49; // @[el2_pic_ctl.scala 161:106] - wire gw_clear_reg_we_5 = _T_608 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] - wire _T_611 = addr_clear_gw_base_match & _T_52; // @[el2_pic_ctl.scala 161:106] - wire gw_clear_reg_we_6 = _T_611 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] - wire _T_614 = addr_clear_gw_base_match & _T_55; // @[el2_pic_ctl.scala 161:106] - wire gw_clear_reg_we_7 = _T_614 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] - wire _T_617 = addr_clear_gw_base_match & _T_58; // @[el2_pic_ctl.scala 161:106] - wire gw_clear_reg_we_8 = _T_617 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] - wire _T_620 = addr_clear_gw_base_match & _T_61; // @[el2_pic_ctl.scala 161:106] - wire gw_clear_reg_we_9 = _T_620 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] - wire _T_623 = addr_clear_gw_base_match & _T_64; // @[el2_pic_ctl.scala 161:106] - wire gw_clear_reg_we_10 = _T_623 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] - wire _T_626 = addr_clear_gw_base_match & _T_67; // @[el2_pic_ctl.scala 161:106] - wire gw_clear_reg_we_11 = _T_626 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] - wire _T_629 = addr_clear_gw_base_match & _T_70; // @[el2_pic_ctl.scala 161:106] - wire gw_clear_reg_we_12 = _T_629 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] - wire _T_632 = addr_clear_gw_base_match & _T_73; // @[el2_pic_ctl.scala 161:106] - wire gw_clear_reg_we_13 = _T_632 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] - wire _T_635 = addr_clear_gw_base_match & _T_76; // @[el2_pic_ctl.scala 161:106] - wire gw_clear_reg_we_14 = _T_635 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] - wire _T_638 = addr_clear_gw_base_match & _T_79; // @[el2_pic_ctl.scala 161:106] - wire gw_clear_reg_we_15 = _T_638 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] - wire _T_641 = addr_clear_gw_base_match & _T_82; // @[el2_pic_ctl.scala 161:106] - wire gw_clear_reg_we_16 = _T_641 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] - wire _T_644 = addr_clear_gw_base_match & _T_85; // @[el2_pic_ctl.scala 161:106] - wire gw_clear_reg_we_17 = _T_644 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] - wire _T_647 = addr_clear_gw_base_match & _T_88; // @[el2_pic_ctl.scala 161:106] - wire gw_clear_reg_we_18 = _T_647 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] - wire _T_650 = addr_clear_gw_base_match & _T_91; // @[el2_pic_ctl.scala 161:106] - wire gw_clear_reg_we_19 = _T_650 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] - wire _T_653 = addr_clear_gw_base_match & _T_94; // @[el2_pic_ctl.scala 161:106] - wire gw_clear_reg_we_20 = _T_653 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] - wire _T_656 = addr_clear_gw_base_match & _T_97; // @[el2_pic_ctl.scala 161:106] - wire gw_clear_reg_we_21 = _T_656 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] - wire _T_659 = addr_clear_gw_base_match & _T_100; // @[el2_pic_ctl.scala 161:106] - wire gw_clear_reg_we_22 = _T_659 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] - wire _T_662 = addr_clear_gw_base_match & _T_103; // @[el2_pic_ctl.scala 161:106] - wire gw_clear_reg_we_23 = _T_662 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] - wire _T_665 = addr_clear_gw_base_match & _T_106; // @[el2_pic_ctl.scala 161:106] - wire gw_clear_reg_we_24 = _T_665 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] - wire _T_668 = addr_clear_gw_base_match & _T_109; // @[el2_pic_ctl.scala 161:106] - wire gw_clear_reg_we_25 = _T_668 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] - wire _T_671 = addr_clear_gw_base_match & _T_112; // @[el2_pic_ctl.scala 161:106] - wire gw_clear_reg_we_26 = _T_671 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] - wire _T_674 = addr_clear_gw_base_match & _T_115; // @[el2_pic_ctl.scala 161:106] - wire gw_clear_reg_we_27 = _T_674 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] - wire _T_677 = addr_clear_gw_base_match & _T_118; // @[el2_pic_ctl.scala 161:106] - wire gw_clear_reg_we_28 = _T_677 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] - wire _T_680 = addr_clear_gw_base_match & _T_121; // @[el2_pic_ctl.scala 161:106] - wire gw_clear_reg_we_29 = _T_680 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] - wire _T_683 = addr_clear_gw_base_match & _T_124; // @[el2_pic_ctl.scala 161:106] - wire gw_clear_reg_we_30 = _T_683 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] - wire _T_686 = addr_clear_gw_base_match & _T_127; // @[el2_pic_ctl.scala 161:106] - wire gw_clear_reg_we_31 = _T_686 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] - wire pic_pri_c1_clk = rvclkhdr_2_io_l1clk; // @[el2_pic_ctl.scala 111:42 el2_pic_ctl.scala 148:21] + wire _T_37 = picm_waddr_ff[6:2] == 5'h1; // @[el2_pic_ctl.scala 147:139] + wire _T_38 = waddr_intpriority_base_match & _T_37; // @[el2_pic_ctl.scala 147:106] + wire intpriority_reg_we_1 = _T_38 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153] + wire _T_40 = picm_waddr_ff[6:2] == 5'h2; // @[el2_pic_ctl.scala 147:139] + wire _T_41 = waddr_intpriority_base_match & _T_40; // @[el2_pic_ctl.scala 147:106] + wire intpriority_reg_we_2 = _T_41 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153] + wire _T_43 = picm_waddr_ff[6:2] == 5'h3; // @[el2_pic_ctl.scala 147:139] + wire _T_44 = waddr_intpriority_base_match & _T_43; // @[el2_pic_ctl.scala 147:106] + wire intpriority_reg_we_3 = _T_44 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153] + wire _T_46 = picm_waddr_ff[6:2] == 5'h4; // @[el2_pic_ctl.scala 147:139] + wire _T_47 = waddr_intpriority_base_match & _T_46; // @[el2_pic_ctl.scala 147:106] + wire intpriority_reg_we_4 = _T_47 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153] + wire _T_49 = picm_waddr_ff[6:2] == 5'h5; // @[el2_pic_ctl.scala 147:139] + wire _T_50 = waddr_intpriority_base_match & _T_49; // @[el2_pic_ctl.scala 147:106] + wire intpriority_reg_we_5 = _T_50 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153] + wire _T_52 = picm_waddr_ff[6:2] == 5'h6; // @[el2_pic_ctl.scala 147:139] + wire _T_53 = waddr_intpriority_base_match & _T_52; // @[el2_pic_ctl.scala 147:106] + wire intpriority_reg_we_6 = _T_53 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153] + wire _T_55 = picm_waddr_ff[6:2] == 5'h7; // @[el2_pic_ctl.scala 147:139] + wire _T_56 = waddr_intpriority_base_match & _T_55; // @[el2_pic_ctl.scala 147:106] + wire intpriority_reg_we_7 = _T_56 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153] + wire _T_58 = picm_waddr_ff[6:2] == 5'h8; // @[el2_pic_ctl.scala 147:139] + wire _T_59 = waddr_intpriority_base_match & _T_58; // @[el2_pic_ctl.scala 147:106] + wire intpriority_reg_we_8 = _T_59 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153] + wire _T_61 = picm_waddr_ff[6:2] == 5'h9; // @[el2_pic_ctl.scala 147:139] + wire _T_62 = waddr_intpriority_base_match & _T_61; // @[el2_pic_ctl.scala 147:106] + wire intpriority_reg_we_9 = _T_62 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153] + wire _T_64 = picm_waddr_ff[6:2] == 5'ha; // @[el2_pic_ctl.scala 147:139] + wire _T_65 = waddr_intpriority_base_match & _T_64; // @[el2_pic_ctl.scala 147:106] + wire intpriority_reg_we_10 = _T_65 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153] + wire _T_67 = picm_waddr_ff[6:2] == 5'hb; // @[el2_pic_ctl.scala 147:139] + wire _T_68 = waddr_intpriority_base_match & _T_67; // @[el2_pic_ctl.scala 147:106] + wire intpriority_reg_we_11 = _T_68 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153] + wire _T_70 = picm_waddr_ff[6:2] == 5'hc; // @[el2_pic_ctl.scala 147:139] + wire _T_71 = waddr_intpriority_base_match & _T_70; // @[el2_pic_ctl.scala 147:106] + wire intpriority_reg_we_12 = _T_71 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153] + wire _T_73 = picm_waddr_ff[6:2] == 5'hd; // @[el2_pic_ctl.scala 147:139] + wire _T_74 = waddr_intpriority_base_match & _T_73; // @[el2_pic_ctl.scala 147:106] + wire intpriority_reg_we_13 = _T_74 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153] + wire _T_76 = picm_waddr_ff[6:2] == 5'he; // @[el2_pic_ctl.scala 147:139] + wire _T_77 = waddr_intpriority_base_match & _T_76; // @[el2_pic_ctl.scala 147:106] + wire intpriority_reg_we_14 = _T_77 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153] + wire _T_79 = picm_waddr_ff[6:2] == 5'hf; // @[el2_pic_ctl.scala 147:139] + wire _T_80 = waddr_intpriority_base_match & _T_79; // @[el2_pic_ctl.scala 147:106] + wire intpriority_reg_we_15 = _T_80 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153] + wire _T_82 = picm_waddr_ff[6:2] == 5'h10; // @[el2_pic_ctl.scala 147:139] + wire _T_83 = waddr_intpriority_base_match & _T_82; // @[el2_pic_ctl.scala 147:106] + wire intpriority_reg_we_16 = _T_83 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153] + wire _T_85 = picm_waddr_ff[6:2] == 5'h11; // @[el2_pic_ctl.scala 147:139] + wire _T_86 = waddr_intpriority_base_match & _T_85; // @[el2_pic_ctl.scala 147:106] + wire intpriority_reg_we_17 = _T_86 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153] + wire _T_88 = picm_waddr_ff[6:2] == 5'h12; // @[el2_pic_ctl.scala 147:139] + wire _T_89 = waddr_intpriority_base_match & _T_88; // @[el2_pic_ctl.scala 147:106] + wire intpriority_reg_we_18 = _T_89 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153] + wire _T_91 = picm_waddr_ff[6:2] == 5'h13; // @[el2_pic_ctl.scala 147:139] + wire _T_92 = waddr_intpriority_base_match & _T_91; // @[el2_pic_ctl.scala 147:106] + wire intpriority_reg_we_19 = _T_92 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153] + wire _T_94 = picm_waddr_ff[6:2] == 5'h14; // @[el2_pic_ctl.scala 147:139] + wire _T_95 = waddr_intpriority_base_match & _T_94; // @[el2_pic_ctl.scala 147:106] + wire intpriority_reg_we_20 = _T_95 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153] + wire _T_97 = picm_waddr_ff[6:2] == 5'h15; // @[el2_pic_ctl.scala 147:139] + wire _T_98 = waddr_intpriority_base_match & _T_97; // @[el2_pic_ctl.scala 147:106] + wire intpriority_reg_we_21 = _T_98 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153] + wire _T_100 = picm_waddr_ff[6:2] == 5'h16; // @[el2_pic_ctl.scala 147:139] + wire _T_101 = waddr_intpriority_base_match & _T_100; // @[el2_pic_ctl.scala 147:106] + wire intpriority_reg_we_22 = _T_101 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153] + wire _T_103 = picm_waddr_ff[6:2] == 5'h17; // @[el2_pic_ctl.scala 147:139] + wire _T_104 = waddr_intpriority_base_match & _T_103; // @[el2_pic_ctl.scala 147:106] + wire intpriority_reg_we_23 = _T_104 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153] + wire _T_106 = picm_waddr_ff[6:2] == 5'h18; // @[el2_pic_ctl.scala 147:139] + wire _T_107 = waddr_intpriority_base_match & _T_106; // @[el2_pic_ctl.scala 147:106] + wire intpriority_reg_we_24 = _T_107 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153] + wire _T_109 = picm_waddr_ff[6:2] == 5'h19; // @[el2_pic_ctl.scala 147:139] + wire _T_110 = waddr_intpriority_base_match & _T_109; // @[el2_pic_ctl.scala 147:106] + wire intpriority_reg_we_25 = _T_110 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153] + wire _T_112 = picm_waddr_ff[6:2] == 5'h1a; // @[el2_pic_ctl.scala 147:139] + wire _T_113 = waddr_intpriority_base_match & _T_112; // @[el2_pic_ctl.scala 147:106] + wire intpriority_reg_we_26 = _T_113 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153] + wire _T_115 = picm_waddr_ff[6:2] == 5'h1b; // @[el2_pic_ctl.scala 147:139] + wire _T_116 = waddr_intpriority_base_match & _T_115; // @[el2_pic_ctl.scala 147:106] + wire intpriority_reg_we_27 = _T_116 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153] + wire _T_118 = picm_waddr_ff[6:2] == 5'h1c; // @[el2_pic_ctl.scala 147:139] + wire _T_119 = waddr_intpriority_base_match & _T_118; // @[el2_pic_ctl.scala 147:106] + wire intpriority_reg_we_28 = _T_119 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153] + wire _T_121 = picm_waddr_ff[6:2] == 5'h1d; // @[el2_pic_ctl.scala 147:139] + wire _T_122 = waddr_intpriority_base_match & _T_121; // @[el2_pic_ctl.scala 147:106] + wire intpriority_reg_we_29 = _T_122 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153] + wire _T_124 = picm_waddr_ff[6:2] == 5'h1e; // @[el2_pic_ctl.scala 147:139] + wire _T_125 = waddr_intpriority_base_match & _T_124; // @[el2_pic_ctl.scala 147:106] + wire intpriority_reg_we_30 = _T_125 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153] + wire _T_127 = picm_waddr_ff[6:2] == 5'h1f; // @[el2_pic_ctl.scala 147:139] + wire _T_128 = waddr_intpriority_base_match & _T_127; // @[el2_pic_ctl.scala 147:106] + wire intpriority_reg_we_31 = _T_128 & picm_wren_ff; // @[el2_pic_ctl.scala 147:153] + wire _T_130 = picm_raddr_ff[6:2] == 5'h1; // @[el2_pic_ctl.scala 148:139] + wire _T_131 = raddr_intpriority_base_match & _T_130; // @[el2_pic_ctl.scala 148:106] + wire intpriority_reg_re_1 = _T_131 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153] + wire _T_133 = picm_raddr_ff[6:2] == 5'h2; // @[el2_pic_ctl.scala 148:139] + wire _T_134 = raddr_intpriority_base_match & _T_133; // @[el2_pic_ctl.scala 148:106] + wire intpriority_reg_re_2 = _T_134 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153] + wire _T_136 = picm_raddr_ff[6:2] == 5'h3; // @[el2_pic_ctl.scala 148:139] + wire _T_137 = raddr_intpriority_base_match & _T_136; // @[el2_pic_ctl.scala 148:106] + wire intpriority_reg_re_3 = _T_137 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153] + wire _T_139 = picm_raddr_ff[6:2] == 5'h4; // @[el2_pic_ctl.scala 148:139] + wire _T_140 = raddr_intpriority_base_match & _T_139; // @[el2_pic_ctl.scala 148:106] + wire intpriority_reg_re_4 = _T_140 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153] + wire _T_142 = picm_raddr_ff[6:2] == 5'h5; // @[el2_pic_ctl.scala 148:139] + wire _T_143 = raddr_intpriority_base_match & _T_142; // @[el2_pic_ctl.scala 148:106] + wire intpriority_reg_re_5 = _T_143 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153] + wire _T_145 = picm_raddr_ff[6:2] == 5'h6; // @[el2_pic_ctl.scala 148:139] + wire _T_146 = raddr_intpriority_base_match & _T_145; // @[el2_pic_ctl.scala 148:106] + wire intpriority_reg_re_6 = _T_146 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153] + wire _T_148 = picm_raddr_ff[6:2] == 5'h7; // @[el2_pic_ctl.scala 148:139] + wire _T_149 = raddr_intpriority_base_match & _T_148; // @[el2_pic_ctl.scala 148:106] + wire intpriority_reg_re_7 = _T_149 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153] + wire _T_151 = picm_raddr_ff[6:2] == 5'h8; // @[el2_pic_ctl.scala 148:139] + wire _T_152 = raddr_intpriority_base_match & _T_151; // @[el2_pic_ctl.scala 148:106] + wire intpriority_reg_re_8 = _T_152 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153] + wire _T_154 = picm_raddr_ff[6:2] == 5'h9; // @[el2_pic_ctl.scala 148:139] + wire _T_155 = raddr_intpriority_base_match & _T_154; // @[el2_pic_ctl.scala 148:106] + wire intpriority_reg_re_9 = _T_155 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153] + wire _T_157 = picm_raddr_ff[6:2] == 5'ha; // @[el2_pic_ctl.scala 148:139] + wire _T_158 = raddr_intpriority_base_match & _T_157; // @[el2_pic_ctl.scala 148:106] + wire intpriority_reg_re_10 = _T_158 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153] + wire _T_160 = picm_raddr_ff[6:2] == 5'hb; // @[el2_pic_ctl.scala 148:139] + wire _T_161 = raddr_intpriority_base_match & _T_160; // @[el2_pic_ctl.scala 148:106] + wire intpriority_reg_re_11 = _T_161 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153] + wire _T_163 = picm_raddr_ff[6:2] == 5'hc; // @[el2_pic_ctl.scala 148:139] + wire _T_164 = raddr_intpriority_base_match & _T_163; // @[el2_pic_ctl.scala 148:106] + wire intpriority_reg_re_12 = _T_164 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153] + wire _T_166 = picm_raddr_ff[6:2] == 5'hd; // @[el2_pic_ctl.scala 148:139] + wire _T_167 = raddr_intpriority_base_match & _T_166; // @[el2_pic_ctl.scala 148:106] + wire intpriority_reg_re_13 = _T_167 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153] + wire _T_169 = picm_raddr_ff[6:2] == 5'he; // @[el2_pic_ctl.scala 148:139] + wire _T_170 = raddr_intpriority_base_match & _T_169; // @[el2_pic_ctl.scala 148:106] + wire intpriority_reg_re_14 = _T_170 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153] + wire _T_172 = picm_raddr_ff[6:2] == 5'hf; // @[el2_pic_ctl.scala 148:139] + wire _T_173 = raddr_intpriority_base_match & _T_172; // @[el2_pic_ctl.scala 148:106] + wire intpriority_reg_re_15 = _T_173 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153] + wire _T_175 = picm_raddr_ff[6:2] == 5'h10; // @[el2_pic_ctl.scala 148:139] + wire _T_176 = raddr_intpriority_base_match & _T_175; // @[el2_pic_ctl.scala 148:106] + wire intpriority_reg_re_16 = _T_176 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153] + wire _T_178 = picm_raddr_ff[6:2] == 5'h11; // @[el2_pic_ctl.scala 148:139] + wire _T_179 = raddr_intpriority_base_match & _T_178; // @[el2_pic_ctl.scala 148:106] + wire intpriority_reg_re_17 = _T_179 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153] + wire _T_181 = picm_raddr_ff[6:2] == 5'h12; // @[el2_pic_ctl.scala 148:139] + wire _T_182 = raddr_intpriority_base_match & _T_181; // @[el2_pic_ctl.scala 148:106] + wire intpriority_reg_re_18 = _T_182 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153] + wire _T_184 = picm_raddr_ff[6:2] == 5'h13; // @[el2_pic_ctl.scala 148:139] + wire _T_185 = raddr_intpriority_base_match & _T_184; // @[el2_pic_ctl.scala 148:106] + wire intpriority_reg_re_19 = _T_185 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153] + wire _T_187 = picm_raddr_ff[6:2] == 5'h14; // @[el2_pic_ctl.scala 148:139] + wire _T_188 = raddr_intpriority_base_match & _T_187; // @[el2_pic_ctl.scala 148:106] + wire intpriority_reg_re_20 = _T_188 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153] + wire _T_190 = picm_raddr_ff[6:2] == 5'h15; // @[el2_pic_ctl.scala 148:139] + wire _T_191 = raddr_intpriority_base_match & _T_190; // @[el2_pic_ctl.scala 148:106] + wire intpriority_reg_re_21 = _T_191 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153] + wire _T_193 = picm_raddr_ff[6:2] == 5'h16; // @[el2_pic_ctl.scala 148:139] + wire _T_194 = raddr_intpriority_base_match & _T_193; // @[el2_pic_ctl.scala 148:106] + wire intpriority_reg_re_22 = _T_194 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153] + wire _T_196 = picm_raddr_ff[6:2] == 5'h17; // @[el2_pic_ctl.scala 148:139] + wire _T_197 = raddr_intpriority_base_match & _T_196; // @[el2_pic_ctl.scala 148:106] + wire intpriority_reg_re_23 = _T_197 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153] + wire _T_199 = picm_raddr_ff[6:2] == 5'h18; // @[el2_pic_ctl.scala 148:139] + wire _T_200 = raddr_intpriority_base_match & _T_199; // @[el2_pic_ctl.scala 148:106] + wire intpriority_reg_re_24 = _T_200 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153] + wire _T_202 = picm_raddr_ff[6:2] == 5'h19; // @[el2_pic_ctl.scala 148:139] + wire _T_203 = raddr_intpriority_base_match & _T_202; // @[el2_pic_ctl.scala 148:106] + wire intpriority_reg_re_25 = _T_203 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153] + wire _T_205 = picm_raddr_ff[6:2] == 5'h1a; // @[el2_pic_ctl.scala 148:139] + wire _T_206 = raddr_intpriority_base_match & _T_205; // @[el2_pic_ctl.scala 148:106] + wire intpriority_reg_re_26 = _T_206 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153] + wire _T_208 = picm_raddr_ff[6:2] == 5'h1b; // @[el2_pic_ctl.scala 148:139] + wire _T_209 = raddr_intpriority_base_match & _T_208; // @[el2_pic_ctl.scala 148:106] + wire intpriority_reg_re_27 = _T_209 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153] + wire _T_211 = picm_raddr_ff[6:2] == 5'h1c; // @[el2_pic_ctl.scala 148:139] + wire _T_212 = raddr_intpriority_base_match & _T_211; // @[el2_pic_ctl.scala 148:106] + wire intpriority_reg_re_28 = _T_212 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153] + wire _T_214 = picm_raddr_ff[6:2] == 5'h1d; // @[el2_pic_ctl.scala 148:139] + wire _T_215 = raddr_intpriority_base_match & _T_214; // @[el2_pic_ctl.scala 148:106] + wire intpriority_reg_re_29 = _T_215 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153] + wire _T_217 = picm_raddr_ff[6:2] == 5'h1e; // @[el2_pic_ctl.scala 148:139] + wire _T_218 = raddr_intpriority_base_match & _T_217; // @[el2_pic_ctl.scala 148:106] + wire intpriority_reg_re_30 = _T_218 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153] + wire _T_220 = picm_raddr_ff[6:2] == 5'h1f; // @[el2_pic_ctl.scala 148:139] + wire _T_221 = raddr_intpriority_base_match & _T_220; // @[el2_pic_ctl.scala 148:106] + wire intpriority_reg_re_31 = _T_221 & picm_rden_ff; // @[el2_pic_ctl.scala 148:153] + wire _T_224 = waddr_intenable_base_match & _T_37; // @[el2_pic_ctl.scala 149:106] + wire intenable_reg_we_1 = _T_224 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153] + wire _T_227 = waddr_intenable_base_match & _T_40; // @[el2_pic_ctl.scala 149:106] + wire intenable_reg_we_2 = _T_227 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153] + wire _T_230 = waddr_intenable_base_match & _T_43; // @[el2_pic_ctl.scala 149:106] + wire intenable_reg_we_3 = _T_230 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153] + wire _T_233 = waddr_intenable_base_match & _T_46; // @[el2_pic_ctl.scala 149:106] + wire intenable_reg_we_4 = _T_233 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153] + wire _T_236 = waddr_intenable_base_match & _T_49; // @[el2_pic_ctl.scala 149:106] + wire intenable_reg_we_5 = _T_236 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153] + wire _T_239 = waddr_intenable_base_match & _T_52; // @[el2_pic_ctl.scala 149:106] + wire intenable_reg_we_6 = _T_239 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153] + wire _T_242 = waddr_intenable_base_match & _T_55; // @[el2_pic_ctl.scala 149:106] + wire intenable_reg_we_7 = _T_242 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153] + wire _T_245 = waddr_intenable_base_match & _T_58; // @[el2_pic_ctl.scala 149:106] + wire intenable_reg_we_8 = _T_245 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153] + wire _T_248 = waddr_intenable_base_match & _T_61; // @[el2_pic_ctl.scala 149:106] + wire intenable_reg_we_9 = _T_248 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153] + wire _T_251 = waddr_intenable_base_match & _T_64; // @[el2_pic_ctl.scala 149:106] + wire intenable_reg_we_10 = _T_251 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153] + wire _T_254 = waddr_intenable_base_match & _T_67; // @[el2_pic_ctl.scala 149:106] + wire intenable_reg_we_11 = _T_254 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153] + wire _T_257 = waddr_intenable_base_match & _T_70; // @[el2_pic_ctl.scala 149:106] + wire intenable_reg_we_12 = _T_257 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153] + wire _T_260 = waddr_intenable_base_match & _T_73; // @[el2_pic_ctl.scala 149:106] + wire intenable_reg_we_13 = _T_260 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153] + wire _T_263 = waddr_intenable_base_match & _T_76; // @[el2_pic_ctl.scala 149:106] + wire intenable_reg_we_14 = _T_263 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153] + wire _T_266 = waddr_intenable_base_match & _T_79; // @[el2_pic_ctl.scala 149:106] + wire intenable_reg_we_15 = _T_266 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153] + wire _T_269 = waddr_intenable_base_match & _T_82; // @[el2_pic_ctl.scala 149:106] + wire intenable_reg_we_16 = _T_269 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153] + wire _T_272 = waddr_intenable_base_match & _T_85; // @[el2_pic_ctl.scala 149:106] + wire intenable_reg_we_17 = _T_272 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153] + wire _T_275 = waddr_intenable_base_match & _T_88; // @[el2_pic_ctl.scala 149:106] + wire intenable_reg_we_18 = _T_275 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153] + wire _T_278 = waddr_intenable_base_match & _T_91; // @[el2_pic_ctl.scala 149:106] + wire intenable_reg_we_19 = _T_278 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153] + wire _T_281 = waddr_intenable_base_match & _T_94; // @[el2_pic_ctl.scala 149:106] + wire intenable_reg_we_20 = _T_281 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153] + wire _T_284 = waddr_intenable_base_match & _T_97; // @[el2_pic_ctl.scala 149:106] + wire intenable_reg_we_21 = _T_284 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153] + wire _T_287 = waddr_intenable_base_match & _T_100; // @[el2_pic_ctl.scala 149:106] + wire intenable_reg_we_22 = _T_287 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153] + wire _T_290 = waddr_intenable_base_match & _T_103; // @[el2_pic_ctl.scala 149:106] + wire intenable_reg_we_23 = _T_290 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153] + wire _T_293 = waddr_intenable_base_match & _T_106; // @[el2_pic_ctl.scala 149:106] + wire intenable_reg_we_24 = _T_293 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153] + wire _T_296 = waddr_intenable_base_match & _T_109; // @[el2_pic_ctl.scala 149:106] + wire intenable_reg_we_25 = _T_296 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153] + wire _T_299 = waddr_intenable_base_match & _T_112; // @[el2_pic_ctl.scala 149:106] + wire intenable_reg_we_26 = _T_299 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153] + wire _T_302 = waddr_intenable_base_match & _T_115; // @[el2_pic_ctl.scala 149:106] + wire intenable_reg_we_27 = _T_302 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153] + wire _T_305 = waddr_intenable_base_match & _T_118; // @[el2_pic_ctl.scala 149:106] + wire intenable_reg_we_28 = _T_305 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153] + wire _T_308 = waddr_intenable_base_match & _T_121; // @[el2_pic_ctl.scala 149:106] + wire intenable_reg_we_29 = _T_308 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153] + wire _T_311 = waddr_intenable_base_match & _T_124; // @[el2_pic_ctl.scala 149:106] + wire intenable_reg_we_30 = _T_311 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153] + wire _T_314 = waddr_intenable_base_match & _T_127; // @[el2_pic_ctl.scala 149:106] + wire intenable_reg_we_31 = _T_314 & picm_wren_ff; // @[el2_pic_ctl.scala 149:153] + wire _T_407 = raddr_intenable_base_match & _T_220; // @[el2_pic_ctl.scala 150:106] + wire intenable_reg_re_31 = _T_407 & picm_rden_ff; // @[el2_pic_ctl.scala 150:153] + wire _T_410 = waddr_config_gw_base_match & _T_37; // @[el2_pic_ctl.scala 151:106] + wire gw_config_reg_we_1 = _T_410 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153] + wire _T_413 = waddr_config_gw_base_match & _T_40; // @[el2_pic_ctl.scala 151:106] + wire gw_config_reg_we_2 = _T_413 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153] + wire _T_416 = waddr_config_gw_base_match & _T_43; // @[el2_pic_ctl.scala 151:106] + wire gw_config_reg_we_3 = _T_416 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153] + wire _T_419 = waddr_config_gw_base_match & _T_46; // @[el2_pic_ctl.scala 151:106] + wire gw_config_reg_we_4 = _T_419 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153] + wire _T_422 = waddr_config_gw_base_match & _T_49; // @[el2_pic_ctl.scala 151:106] + wire gw_config_reg_we_5 = _T_422 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153] + wire _T_425 = waddr_config_gw_base_match & _T_52; // @[el2_pic_ctl.scala 151:106] + wire gw_config_reg_we_6 = _T_425 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153] + wire _T_428 = waddr_config_gw_base_match & _T_55; // @[el2_pic_ctl.scala 151:106] + wire gw_config_reg_we_7 = _T_428 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153] + wire _T_431 = waddr_config_gw_base_match & _T_58; // @[el2_pic_ctl.scala 151:106] + wire gw_config_reg_we_8 = _T_431 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153] + wire _T_434 = waddr_config_gw_base_match & _T_61; // @[el2_pic_ctl.scala 151:106] + wire gw_config_reg_we_9 = _T_434 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153] + wire _T_437 = waddr_config_gw_base_match & _T_64; // @[el2_pic_ctl.scala 151:106] + wire gw_config_reg_we_10 = _T_437 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153] + wire _T_440 = waddr_config_gw_base_match & _T_67; // @[el2_pic_ctl.scala 151:106] + wire gw_config_reg_we_11 = _T_440 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153] + wire _T_443 = waddr_config_gw_base_match & _T_70; // @[el2_pic_ctl.scala 151:106] + wire gw_config_reg_we_12 = _T_443 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153] + wire _T_446 = waddr_config_gw_base_match & _T_73; // @[el2_pic_ctl.scala 151:106] + wire gw_config_reg_we_13 = _T_446 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153] + wire _T_449 = waddr_config_gw_base_match & _T_76; // @[el2_pic_ctl.scala 151:106] + wire gw_config_reg_we_14 = _T_449 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153] + wire _T_452 = waddr_config_gw_base_match & _T_79; // @[el2_pic_ctl.scala 151:106] + wire gw_config_reg_we_15 = _T_452 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153] + wire _T_455 = waddr_config_gw_base_match & _T_82; // @[el2_pic_ctl.scala 151:106] + wire gw_config_reg_we_16 = _T_455 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153] + wire _T_458 = waddr_config_gw_base_match & _T_85; // @[el2_pic_ctl.scala 151:106] + wire gw_config_reg_we_17 = _T_458 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153] + wire _T_461 = waddr_config_gw_base_match & _T_88; // @[el2_pic_ctl.scala 151:106] + wire gw_config_reg_we_18 = _T_461 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153] + wire _T_464 = waddr_config_gw_base_match & _T_91; // @[el2_pic_ctl.scala 151:106] + wire gw_config_reg_we_19 = _T_464 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153] + wire _T_467 = waddr_config_gw_base_match & _T_94; // @[el2_pic_ctl.scala 151:106] + wire gw_config_reg_we_20 = _T_467 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153] + wire _T_470 = waddr_config_gw_base_match & _T_97; // @[el2_pic_ctl.scala 151:106] + wire gw_config_reg_we_21 = _T_470 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153] + wire _T_473 = waddr_config_gw_base_match & _T_100; // @[el2_pic_ctl.scala 151:106] + wire gw_config_reg_we_22 = _T_473 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153] + wire _T_476 = waddr_config_gw_base_match & _T_103; // @[el2_pic_ctl.scala 151:106] + wire gw_config_reg_we_23 = _T_476 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153] + wire _T_479 = waddr_config_gw_base_match & _T_106; // @[el2_pic_ctl.scala 151:106] + wire gw_config_reg_we_24 = _T_479 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153] + wire _T_482 = waddr_config_gw_base_match & _T_109; // @[el2_pic_ctl.scala 151:106] + wire gw_config_reg_we_25 = _T_482 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153] + wire _T_485 = waddr_config_gw_base_match & _T_112; // @[el2_pic_ctl.scala 151:106] + wire gw_config_reg_we_26 = _T_485 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153] + wire _T_488 = waddr_config_gw_base_match & _T_115; // @[el2_pic_ctl.scala 151:106] + wire gw_config_reg_we_27 = _T_488 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153] + wire _T_491 = waddr_config_gw_base_match & _T_118; // @[el2_pic_ctl.scala 151:106] + wire gw_config_reg_we_28 = _T_491 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153] + wire _T_494 = waddr_config_gw_base_match & _T_121; // @[el2_pic_ctl.scala 151:106] + wire gw_config_reg_we_29 = _T_494 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153] + wire _T_497 = waddr_config_gw_base_match & _T_124; // @[el2_pic_ctl.scala 151:106] + wire gw_config_reg_we_30 = _T_497 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153] + wire _T_500 = waddr_config_gw_base_match & _T_127; // @[el2_pic_ctl.scala 151:106] + wire gw_config_reg_we_31 = _T_500 & picm_wren_ff; // @[el2_pic_ctl.scala 151:153] + wire _T_503 = raddr_config_gw_base_match & _T_130; // @[el2_pic_ctl.scala 152:106] + wire gw_config_reg_re_1 = _T_503 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153] + wire _T_506 = raddr_config_gw_base_match & _T_133; // @[el2_pic_ctl.scala 152:106] + wire gw_config_reg_re_2 = _T_506 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153] + wire _T_509 = raddr_config_gw_base_match & _T_136; // @[el2_pic_ctl.scala 152:106] + wire gw_config_reg_re_3 = _T_509 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153] + wire _T_512 = raddr_config_gw_base_match & _T_139; // @[el2_pic_ctl.scala 152:106] + wire gw_config_reg_re_4 = _T_512 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153] + wire _T_515 = raddr_config_gw_base_match & _T_142; // @[el2_pic_ctl.scala 152:106] + wire gw_config_reg_re_5 = _T_515 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153] + wire _T_518 = raddr_config_gw_base_match & _T_145; // @[el2_pic_ctl.scala 152:106] + wire gw_config_reg_re_6 = _T_518 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153] + wire _T_521 = raddr_config_gw_base_match & _T_148; // @[el2_pic_ctl.scala 152:106] + wire gw_config_reg_re_7 = _T_521 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153] + wire _T_524 = raddr_config_gw_base_match & _T_151; // @[el2_pic_ctl.scala 152:106] + wire gw_config_reg_re_8 = _T_524 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153] + wire _T_527 = raddr_config_gw_base_match & _T_154; // @[el2_pic_ctl.scala 152:106] + wire gw_config_reg_re_9 = _T_527 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153] + wire _T_530 = raddr_config_gw_base_match & _T_157; // @[el2_pic_ctl.scala 152:106] + wire gw_config_reg_re_10 = _T_530 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153] + wire _T_533 = raddr_config_gw_base_match & _T_160; // @[el2_pic_ctl.scala 152:106] + wire gw_config_reg_re_11 = _T_533 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153] + wire _T_536 = raddr_config_gw_base_match & _T_163; // @[el2_pic_ctl.scala 152:106] + wire gw_config_reg_re_12 = _T_536 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153] + wire _T_539 = raddr_config_gw_base_match & _T_166; // @[el2_pic_ctl.scala 152:106] + wire gw_config_reg_re_13 = _T_539 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153] + wire _T_542 = raddr_config_gw_base_match & _T_169; // @[el2_pic_ctl.scala 152:106] + wire gw_config_reg_re_14 = _T_542 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153] + wire _T_545 = raddr_config_gw_base_match & _T_172; // @[el2_pic_ctl.scala 152:106] + wire gw_config_reg_re_15 = _T_545 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153] + wire _T_548 = raddr_config_gw_base_match & _T_175; // @[el2_pic_ctl.scala 152:106] + wire gw_config_reg_re_16 = _T_548 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153] + wire _T_551 = raddr_config_gw_base_match & _T_178; // @[el2_pic_ctl.scala 152:106] + wire gw_config_reg_re_17 = _T_551 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153] + wire _T_554 = raddr_config_gw_base_match & _T_181; // @[el2_pic_ctl.scala 152:106] + wire gw_config_reg_re_18 = _T_554 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153] + wire _T_557 = raddr_config_gw_base_match & _T_184; // @[el2_pic_ctl.scala 152:106] + wire gw_config_reg_re_19 = _T_557 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153] + wire _T_560 = raddr_config_gw_base_match & _T_187; // @[el2_pic_ctl.scala 152:106] + wire gw_config_reg_re_20 = _T_560 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153] + wire _T_563 = raddr_config_gw_base_match & _T_190; // @[el2_pic_ctl.scala 152:106] + wire gw_config_reg_re_21 = _T_563 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153] + wire _T_566 = raddr_config_gw_base_match & _T_193; // @[el2_pic_ctl.scala 152:106] + wire gw_config_reg_re_22 = _T_566 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153] + wire _T_569 = raddr_config_gw_base_match & _T_196; // @[el2_pic_ctl.scala 152:106] + wire gw_config_reg_re_23 = _T_569 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153] + wire _T_572 = raddr_config_gw_base_match & _T_199; // @[el2_pic_ctl.scala 152:106] + wire gw_config_reg_re_24 = _T_572 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153] + wire _T_575 = raddr_config_gw_base_match & _T_202; // @[el2_pic_ctl.scala 152:106] + wire gw_config_reg_re_25 = _T_575 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153] + wire _T_578 = raddr_config_gw_base_match & _T_205; // @[el2_pic_ctl.scala 152:106] + wire gw_config_reg_re_26 = _T_578 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153] + wire _T_581 = raddr_config_gw_base_match & _T_208; // @[el2_pic_ctl.scala 152:106] + wire gw_config_reg_re_27 = _T_581 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153] + wire _T_584 = raddr_config_gw_base_match & _T_211; // @[el2_pic_ctl.scala 152:106] + wire gw_config_reg_re_28 = _T_584 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153] + wire _T_587 = raddr_config_gw_base_match & _T_214; // @[el2_pic_ctl.scala 152:106] + wire gw_config_reg_re_29 = _T_587 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153] + wire _T_590 = raddr_config_gw_base_match & _T_217; // @[el2_pic_ctl.scala 152:106] + wire gw_config_reg_re_30 = _T_590 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153] + wire _T_593 = raddr_config_gw_base_match & _T_220; // @[el2_pic_ctl.scala 152:106] + wire gw_config_reg_re_31 = _T_593 & picm_rden_ff; // @[el2_pic_ctl.scala 152:153] + wire _T_596 = addr_clear_gw_base_match & _T_37; // @[el2_pic_ctl.scala 153:106] + wire gw_clear_reg_we_1 = _T_596 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153] + wire _T_599 = addr_clear_gw_base_match & _T_40; // @[el2_pic_ctl.scala 153:106] + wire gw_clear_reg_we_2 = _T_599 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153] + wire _T_602 = addr_clear_gw_base_match & _T_43; // @[el2_pic_ctl.scala 153:106] + wire gw_clear_reg_we_3 = _T_602 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153] + wire _T_605 = addr_clear_gw_base_match & _T_46; // @[el2_pic_ctl.scala 153:106] + wire gw_clear_reg_we_4 = _T_605 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153] + wire _T_608 = addr_clear_gw_base_match & _T_49; // @[el2_pic_ctl.scala 153:106] + wire gw_clear_reg_we_5 = _T_608 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153] + wire _T_611 = addr_clear_gw_base_match & _T_52; // @[el2_pic_ctl.scala 153:106] + wire gw_clear_reg_we_6 = _T_611 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153] + wire _T_614 = addr_clear_gw_base_match & _T_55; // @[el2_pic_ctl.scala 153:106] + wire gw_clear_reg_we_7 = _T_614 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153] + wire _T_617 = addr_clear_gw_base_match & _T_58; // @[el2_pic_ctl.scala 153:106] + wire gw_clear_reg_we_8 = _T_617 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153] + wire _T_620 = addr_clear_gw_base_match & _T_61; // @[el2_pic_ctl.scala 153:106] + wire gw_clear_reg_we_9 = _T_620 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153] + wire _T_623 = addr_clear_gw_base_match & _T_64; // @[el2_pic_ctl.scala 153:106] + wire gw_clear_reg_we_10 = _T_623 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153] + wire _T_626 = addr_clear_gw_base_match & _T_67; // @[el2_pic_ctl.scala 153:106] + wire gw_clear_reg_we_11 = _T_626 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153] + wire _T_629 = addr_clear_gw_base_match & _T_70; // @[el2_pic_ctl.scala 153:106] + wire gw_clear_reg_we_12 = _T_629 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153] + wire _T_632 = addr_clear_gw_base_match & _T_73; // @[el2_pic_ctl.scala 153:106] + wire gw_clear_reg_we_13 = _T_632 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153] + wire _T_635 = addr_clear_gw_base_match & _T_76; // @[el2_pic_ctl.scala 153:106] + wire gw_clear_reg_we_14 = _T_635 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153] + wire _T_638 = addr_clear_gw_base_match & _T_79; // @[el2_pic_ctl.scala 153:106] + wire gw_clear_reg_we_15 = _T_638 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153] + wire _T_641 = addr_clear_gw_base_match & _T_82; // @[el2_pic_ctl.scala 153:106] + wire gw_clear_reg_we_16 = _T_641 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153] + wire _T_644 = addr_clear_gw_base_match & _T_85; // @[el2_pic_ctl.scala 153:106] + wire gw_clear_reg_we_17 = _T_644 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153] + wire _T_647 = addr_clear_gw_base_match & _T_88; // @[el2_pic_ctl.scala 153:106] + wire gw_clear_reg_we_18 = _T_647 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153] + wire _T_650 = addr_clear_gw_base_match & _T_91; // @[el2_pic_ctl.scala 153:106] + wire gw_clear_reg_we_19 = _T_650 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153] + wire _T_653 = addr_clear_gw_base_match & _T_94; // @[el2_pic_ctl.scala 153:106] + wire gw_clear_reg_we_20 = _T_653 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153] + wire _T_656 = addr_clear_gw_base_match & _T_97; // @[el2_pic_ctl.scala 153:106] + wire gw_clear_reg_we_21 = _T_656 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153] + wire _T_659 = addr_clear_gw_base_match & _T_100; // @[el2_pic_ctl.scala 153:106] + wire gw_clear_reg_we_22 = _T_659 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153] + wire _T_662 = addr_clear_gw_base_match & _T_103; // @[el2_pic_ctl.scala 153:106] + wire gw_clear_reg_we_23 = _T_662 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153] + wire _T_665 = addr_clear_gw_base_match & _T_106; // @[el2_pic_ctl.scala 153:106] + wire gw_clear_reg_we_24 = _T_665 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153] + wire _T_668 = addr_clear_gw_base_match & _T_109; // @[el2_pic_ctl.scala 153:106] + wire gw_clear_reg_we_25 = _T_668 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153] + wire _T_671 = addr_clear_gw_base_match & _T_112; // @[el2_pic_ctl.scala 153:106] + wire gw_clear_reg_we_26 = _T_671 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153] + wire _T_674 = addr_clear_gw_base_match & _T_115; // @[el2_pic_ctl.scala 153:106] + wire gw_clear_reg_we_27 = _T_674 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153] + wire _T_677 = addr_clear_gw_base_match & _T_118; // @[el2_pic_ctl.scala 153:106] + wire gw_clear_reg_we_28 = _T_677 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153] + wire _T_680 = addr_clear_gw_base_match & _T_121; // @[el2_pic_ctl.scala 153:106] + wire gw_clear_reg_we_29 = _T_680 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153] + wire _T_683 = addr_clear_gw_base_match & _T_124; // @[el2_pic_ctl.scala 153:106] + wire gw_clear_reg_we_30 = _T_683 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153] + wire _T_686 = addr_clear_gw_base_match & _T_127; // @[el2_pic_ctl.scala 153:106] + wire gw_clear_reg_we_31 = _T_686 & picm_wren_ff; // @[el2_pic_ctl.scala 153:153] + wire pic_pri_c1_clk = rvclkhdr_2_io_l1clk; // @[el2_pic_ctl.scala 103:42 el2_pic_ctl.scala 140:21] reg [3:0] intpriority_reg_1; // @[Reg.scala 27:20] reg [3:0] intpriority_reg_2; // @[Reg.scala 27:20] reg [3:0] intpriority_reg_3; // @[Reg.scala 27:20] @@ -704,7 +704,7 @@ module el2_pic_ctrl( reg [3:0] intpriority_reg_29; // @[Reg.scala 27:20] reg [3:0] intpriority_reg_30; // @[Reg.scala 27:20] reg [3:0] intpriority_reg_31; // @[Reg.scala 27:20] - wire pic_int_c1_clk = rvclkhdr_3_io_l1clk; // @[el2_pic_ctl.scala 112:42 el2_pic_ctl.scala 149:21] + wire pic_int_c1_clk = rvclkhdr_3_io_l1clk; // @[el2_pic_ctl.scala 104:42 el2_pic_ctl.scala 141:21] reg intenable_reg_1; // @[Reg.scala 27:20] reg intenable_reg_2; // @[Reg.scala 27:20] reg intenable_reg_3; // @[Reg.scala 27:20] @@ -736,7 +736,7 @@ module el2_pic_ctrl( reg intenable_reg_29; // @[Reg.scala 27:20] reg intenable_reg_30; // @[Reg.scala 27:20] reg intenable_reg_31; // @[Reg.scala 27:20] - wire gw_config_c1_clk = rvclkhdr_4_io_l1clk; // @[el2_pic_ctl.scala 113:42 el2_pic_ctl.scala 150:21] + wire gw_config_c1_clk = rvclkhdr_4_io_l1clk; // @[el2_pic_ctl.scala 105:42 el2_pic_ctl.scala 142:21] reg [1:0] gw_config_reg_1; // @[Reg.scala 27:20] reg [1:0] gw_config_reg_2; // @[Reg.scala 27:20] reg [1:0] gw_config_reg_3; // @[Reg.scala 27:20] @@ -768,1086 +768,1054 @@ module el2_pic_ctrl( reg [1:0] gw_config_reg_29; // @[Reg.scala 27:20] reg [1:0] gw_config_reg_30; // @[Reg.scala 27:20] reg [1:0] gw_config_reg_31; // @[Reg.scala 27:20] - wire _T_970 = extintsrc_req_sync[1] ^ gw_config_reg_1[0]; // @[el2_pic_ctl.scala 45:50] - wire _T_971 = ~gw_clear_reg_we_1; // @[el2_pic_ctl.scala 45:92] - reg gw_int_pending; // @[el2_pic_ctl.scala 46:30] - wire _T_972 = gw_int_pending & _T_971; // @[el2_pic_ctl.scala 45:90] - wire _T_976 = _T_970 | gw_int_pending; // @[el2_pic_ctl.scala 47:78] - wire extintsrc_req_gw_1 = gw_config_reg_1[1] ? _T_976 : _T_970; // @[el2_pic_ctl.scala 47:8] - wire _T_982 = extintsrc_req_sync[2] ^ gw_config_reg_2[0]; // @[el2_pic_ctl.scala 45:50] - wire _T_983 = ~gw_clear_reg_we_2; // @[el2_pic_ctl.scala 45:92] - reg gw_int_pending_1; // @[el2_pic_ctl.scala 46:30] - wire _T_984 = gw_int_pending_1 & _T_983; // @[el2_pic_ctl.scala 45:90] - wire _T_988 = _T_982 | gw_int_pending_1; // @[el2_pic_ctl.scala 47:78] - wire extintsrc_req_gw_2 = gw_config_reg_2[1] ? _T_988 : _T_982; // @[el2_pic_ctl.scala 47:8] - wire _T_994 = extintsrc_req_sync[3] ^ gw_config_reg_3[0]; // @[el2_pic_ctl.scala 45:50] - wire _T_995 = ~gw_clear_reg_we_3; // @[el2_pic_ctl.scala 45:92] - reg gw_int_pending_2; // @[el2_pic_ctl.scala 46:30] - wire _T_996 = gw_int_pending_2 & _T_995; // @[el2_pic_ctl.scala 45:90] - wire _T_1000 = _T_994 | gw_int_pending_2; // @[el2_pic_ctl.scala 47:78] - wire extintsrc_req_gw_3 = gw_config_reg_3[1] ? _T_1000 : _T_994; // @[el2_pic_ctl.scala 47:8] - wire _T_1006 = extintsrc_req_sync[4] ^ gw_config_reg_4[0]; // @[el2_pic_ctl.scala 45:50] - wire _T_1007 = ~gw_clear_reg_we_4; // @[el2_pic_ctl.scala 45:92] - reg gw_int_pending_3; // @[el2_pic_ctl.scala 46:30] - wire _T_1008 = gw_int_pending_3 & _T_1007; // @[el2_pic_ctl.scala 45:90] - wire _T_1012 = _T_1006 | gw_int_pending_3; // @[el2_pic_ctl.scala 47:78] - wire extintsrc_req_gw_4 = gw_config_reg_4[1] ? _T_1012 : _T_1006; // @[el2_pic_ctl.scala 47:8] - wire _T_1018 = extintsrc_req_sync[5] ^ gw_config_reg_5[0]; // @[el2_pic_ctl.scala 45:50] - wire _T_1019 = ~gw_clear_reg_we_5; // @[el2_pic_ctl.scala 45:92] - reg gw_int_pending_4; // @[el2_pic_ctl.scala 46:30] - wire _T_1020 = gw_int_pending_4 & _T_1019; // @[el2_pic_ctl.scala 45:90] - wire _T_1024 = _T_1018 | gw_int_pending_4; // @[el2_pic_ctl.scala 47:78] - wire extintsrc_req_gw_5 = gw_config_reg_5[1] ? _T_1024 : _T_1018; // @[el2_pic_ctl.scala 47:8] - wire _T_1030 = extintsrc_req_sync[6] ^ gw_config_reg_6[0]; // @[el2_pic_ctl.scala 45:50] - wire _T_1031 = ~gw_clear_reg_we_6; // @[el2_pic_ctl.scala 45:92] - reg gw_int_pending_5; // @[el2_pic_ctl.scala 46:30] - wire _T_1032 = gw_int_pending_5 & _T_1031; // @[el2_pic_ctl.scala 45:90] - wire _T_1036 = _T_1030 | gw_int_pending_5; // @[el2_pic_ctl.scala 47:78] - wire extintsrc_req_gw_6 = gw_config_reg_6[1] ? _T_1036 : _T_1030; // @[el2_pic_ctl.scala 47:8] - wire _T_1042 = extintsrc_req_sync[7] ^ gw_config_reg_7[0]; // @[el2_pic_ctl.scala 45:50] - wire _T_1043 = ~gw_clear_reg_we_7; // @[el2_pic_ctl.scala 45:92] - reg gw_int_pending_6; // @[el2_pic_ctl.scala 46:30] - wire _T_1044 = gw_int_pending_6 & _T_1043; // @[el2_pic_ctl.scala 45:90] - wire _T_1048 = _T_1042 | gw_int_pending_6; // @[el2_pic_ctl.scala 47:78] - wire extintsrc_req_gw_7 = gw_config_reg_7[1] ? _T_1048 : _T_1042; // @[el2_pic_ctl.scala 47:8] - wire _T_1054 = extintsrc_req_sync[8] ^ gw_config_reg_8[0]; // @[el2_pic_ctl.scala 45:50] - wire _T_1055 = ~gw_clear_reg_we_8; // @[el2_pic_ctl.scala 45:92] - reg gw_int_pending_7; // @[el2_pic_ctl.scala 46:30] - wire _T_1056 = gw_int_pending_7 & _T_1055; // @[el2_pic_ctl.scala 45:90] - wire _T_1060 = _T_1054 | gw_int_pending_7; // @[el2_pic_ctl.scala 47:78] - wire extintsrc_req_gw_8 = gw_config_reg_8[1] ? _T_1060 : _T_1054; // @[el2_pic_ctl.scala 47:8] - wire _T_1066 = extintsrc_req_sync[9] ^ gw_config_reg_9[0]; // @[el2_pic_ctl.scala 45:50] - wire _T_1067 = ~gw_clear_reg_we_9; // @[el2_pic_ctl.scala 45:92] - reg gw_int_pending_8; // @[el2_pic_ctl.scala 46:30] - wire _T_1068 = gw_int_pending_8 & _T_1067; // @[el2_pic_ctl.scala 45:90] - wire _T_1072 = _T_1066 | gw_int_pending_8; // @[el2_pic_ctl.scala 47:78] - wire extintsrc_req_gw_9 = gw_config_reg_9[1] ? _T_1072 : _T_1066; // @[el2_pic_ctl.scala 47:8] - wire _T_1078 = extintsrc_req_sync[10] ^ gw_config_reg_10[0]; // @[el2_pic_ctl.scala 45:50] - wire _T_1079 = ~gw_clear_reg_we_10; // @[el2_pic_ctl.scala 45:92] - reg gw_int_pending_9; // @[el2_pic_ctl.scala 46:30] - wire _T_1080 = gw_int_pending_9 & _T_1079; // @[el2_pic_ctl.scala 45:90] - wire _T_1084 = _T_1078 | gw_int_pending_9; // @[el2_pic_ctl.scala 47:78] - wire extintsrc_req_gw_10 = gw_config_reg_10[1] ? _T_1084 : _T_1078; // @[el2_pic_ctl.scala 47:8] - wire _T_1090 = extintsrc_req_sync[11] ^ gw_config_reg_11[0]; // @[el2_pic_ctl.scala 45:50] - wire _T_1091 = ~gw_clear_reg_we_11; // @[el2_pic_ctl.scala 45:92] - reg gw_int_pending_10; // @[el2_pic_ctl.scala 46:30] - wire _T_1092 = gw_int_pending_10 & _T_1091; // @[el2_pic_ctl.scala 45:90] - wire _T_1096 = _T_1090 | gw_int_pending_10; // @[el2_pic_ctl.scala 47:78] - wire extintsrc_req_gw_11 = gw_config_reg_11[1] ? _T_1096 : _T_1090; // @[el2_pic_ctl.scala 47:8] - wire _T_1102 = extintsrc_req_sync[12] ^ gw_config_reg_12[0]; // @[el2_pic_ctl.scala 45:50] - wire _T_1103 = ~gw_clear_reg_we_12; // @[el2_pic_ctl.scala 45:92] - reg gw_int_pending_11; // @[el2_pic_ctl.scala 46:30] - wire _T_1104 = gw_int_pending_11 & _T_1103; // @[el2_pic_ctl.scala 45:90] - wire _T_1108 = _T_1102 | gw_int_pending_11; // @[el2_pic_ctl.scala 47:78] - wire extintsrc_req_gw_12 = gw_config_reg_12[1] ? _T_1108 : _T_1102; // @[el2_pic_ctl.scala 47:8] - wire _T_1114 = extintsrc_req_sync[13] ^ gw_config_reg_13[0]; // @[el2_pic_ctl.scala 45:50] - wire _T_1115 = ~gw_clear_reg_we_13; // @[el2_pic_ctl.scala 45:92] - reg gw_int_pending_12; // @[el2_pic_ctl.scala 46:30] - wire _T_1116 = gw_int_pending_12 & _T_1115; // @[el2_pic_ctl.scala 45:90] - wire _T_1120 = _T_1114 | gw_int_pending_12; // @[el2_pic_ctl.scala 47:78] - wire extintsrc_req_gw_13 = gw_config_reg_13[1] ? _T_1120 : _T_1114; // @[el2_pic_ctl.scala 47:8] - wire _T_1126 = extintsrc_req_sync[14] ^ gw_config_reg_14[0]; // @[el2_pic_ctl.scala 45:50] - wire _T_1127 = ~gw_clear_reg_we_14; // @[el2_pic_ctl.scala 45:92] - reg gw_int_pending_13; // @[el2_pic_ctl.scala 46:30] - wire _T_1128 = gw_int_pending_13 & _T_1127; // @[el2_pic_ctl.scala 45:90] - wire _T_1132 = _T_1126 | gw_int_pending_13; // @[el2_pic_ctl.scala 47:78] - wire extintsrc_req_gw_14 = gw_config_reg_14[1] ? _T_1132 : _T_1126; // @[el2_pic_ctl.scala 47:8] - wire _T_1138 = extintsrc_req_sync[15] ^ gw_config_reg_15[0]; // @[el2_pic_ctl.scala 45:50] - wire _T_1139 = ~gw_clear_reg_we_15; // @[el2_pic_ctl.scala 45:92] - reg gw_int_pending_14; // @[el2_pic_ctl.scala 46:30] - wire _T_1140 = gw_int_pending_14 & _T_1139; // @[el2_pic_ctl.scala 45:90] - wire _T_1144 = _T_1138 | gw_int_pending_14; // @[el2_pic_ctl.scala 47:78] - wire extintsrc_req_gw_15 = gw_config_reg_15[1] ? _T_1144 : _T_1138; // @[el2_pic_ctl.scala 47:8] - wire _T_1150 = extintsrc_req_sync[16] ^ gw_config_reg_16[0]; // @[el2_pic_ctl.scala 45:50] - wire _T_1151 = ~gw_clear_reg_we_16; // @[el2_pic_ctl.scala 45:92] - reg gw_int_pending_15; // @[el2_pic_ctl.scala 46:30] - wire _T_1152 = gw_int_pending_15 & _T_1151; // @[el2_pic_ctl.scala 45:90] - wire _T_1156 = _T_1150 | gw_int_pending_15; // @[el2_pic_ctl.scala 47:78] - wire extintsrc_req_gw_16 = gw_config_reg_16[1] ? _T_1156 : _T_1150; // @[el2_pic_ctl.scala 47:8] - wire _T_1162 = extintsrc_req_sync[17] ^ gw_config_reg_17[0]; // @[el2_pic_ctl.scala 45:50] - wire _T_1163 = ~gw_clear_reg_we_17; // @[el2_pic_ctl.scala 45:92] - reg gw_int_pending_16; // @[el2_pic_ctl.scala 46:30] - wire _T_1164 = gw_int_pending_16 & _T_1163; // @[el2_pic_ctl.scala 45:90] - wire _T_1168 = _T_1162 | gw_int_pending_16; // @[el2_pic_ctl.scala 47:78] - wire extintsrc_req_gw_17 = gw_config_reg_17[1] ? _T_1168 : _T_1162; // @[el2_pic_ctl.scala 47:8] - wire _T_1174 = extintsrc_req_sync[18] ^ gw_config_reg_18[0]; // @[el2_pic_ctl.scala 45:50] - wire _T_1175 = ~gw_clear_reg_we_18; // @[el2_pic_ctl.scala 45:92] - reg gw_int_pending_17; // @[el2_pic_ctl.scala 46:30] - wire _T_1176 = gw_int_pending_17 & _T_1175; // @[el2_pic_ctl.scala 45:90] - wire _T_1180 = _T_1174 | gw_int_pending_17; // @[el2_pic_ctl.scala 47:78] - wire extintsrc_req_gw_18 = gw_config_reg_18[1] ? _T_1180 : _T_1174; // @[el2_pic_ctl.scala 47:8] - wire _T_1186 = extintsrc_req_sync[19] ^ gw_config_reg_19[0]; // @[el2_pic_ctl.scala 45:50] - wire _T_1187 = ~gw_clear_reg_we_19; // @[el2_pic_ctl.scala 45:92] - reg gw_int_pending_18; // @[el2_pic_ctl.scala 46:30] - wire _T_1188 = gw_int_pending_18 & _T_1187; // @[el2_pic_ctl.scala 45:90] - wire _T_1192 = _T_1186 | gw_int_pending_18; // @[el2_pic_ctl.scala 47:78] - wire extintsrc_req_gw_19 = gw_config_reg_19[1] ? _T_1192 : _T_1186; // @[el2_pic_ctl.scala 47:8] - wire _T_1198 = extintsrc_req_sync[20] ^ gw_config_reg_20[0]; // @[el2_pic_ctl.scala 45:50] - wire _T_1199 = ~gw_clear_reg_we_20; // @[el2_pic_ctl.scala 45:92] - reg gw_int_pending_19; // @[el2_pic_ctl.scala 46:30] - wire _T_1200 = gw_int_pending_19 & _T_1199; // @[el2_pic_ctl.scala 45:90] - wire _T_1204 = _T_1198 | gw_int_pending_19; // @[el2_pic_ctl.scala 47:78] - wire extintsrc_req_gw_20 = gw_config_reg_20[1] ? _T_1204 : _T_1198; // @[el2_pic_ctl.scala 47:8] - wire _T_1210 = extintsrc_req_sync[21] ^ gw_config_reg_21[0]; // @[el2_pic_ctl.scala 45:50] - wire _T_1211 = ~gw_clear_reg_we_21; // @[el2_pic_ctl.scala 45:92] - reg gw_int_pending_20; // @[el2_pic_ctl.scala 46:30] - wire _T_1212 = gw_int_pending_20 & _T_1211; // @[el2_pic_ctl.scala 45:90] - wire _T_1216 = _T_1210 | gw_int_pending_20; // @[el2_pic_ctl.scala 47:78] - wire extintsrc_req_gw_21 = gw_config_reg_21[1] ? _T_1216 : _T_1210; // @[el2_pic_ctl.scala 47:8] - wire _T_1222 = extintsrc_req_sync[22] ^ gw_config_reg_22[0]; // @[el2_pic_ctl.scala 45:50] - wire _T_1223 = ~gw_clear_reg_we_22; // @[el2_pic_ctl.scala 45:92] - reg gw_int_pending_21; // @[el2_pic_ctl.scala 46:30] - wire _T_1224 = gw_int_pending_21 & _T_1223; // @[el2_pic_ctl.scala 45:90] - wire _T_1228 = _T_1222 | gw_int_pending_21; // @[el2_pic_ctl.scala 47:78] - wire extintsrc_req_gw_22 = gw_config_reg_22[1] ? _T_1228 : _T_1222; // @[el2_pic_ctl.scala 47:8] - wire _T_1234 = extintsrc_req_sync[23] ^ gw_config_reg_23[0]; // @[el2_pic_ctl.scala 45:50] - wire _T_1235 = ~gw_clear_reg_we_23; // @[el2_pic_ctl.scala 45:92] - reg gw_int_pending_22; // @[el2_pic_ctl.scala 46:30] - wire _T_1236 = gw_int_pending_22 & _T_1235; // @[el2_pic_ctl.scala 45:90] - wire _T_1240 = _T_1234 | gw_int_pending_22; // @[el2_pic_ctl.scala 47:78] - wire extintsrc_req_gw_23 = gw_config_reg_23[1] ? _T_1240 : _T_1234; // @[el2_pic_ctl.scala 47:8] - wire _T_1246 = extintsrc_req_sync[24] ^ gw_config_reg_24[0]; // @[el2_pic_ctl.scala 45:50] - wire _T_1247 = ~gw_clear_reg_we_24; // @[el2_pic_ctl.scala 45:92] - reg gw_int_pending_23; // @[el2_pic_ctl.scala 46:30] - wire _T_1248 = gw_int_pending_23 & _T_1247; // @[el2_pic_ctl.scala 45:90] - wire _T_1252 = _T_1246 | gw_int_pending_23; // @[el2_pic_ctl.scala 47:78] - wire extintsrc_req_gw_24 = gw_config_reg_24[1] ? _T_1252 : _T_1246; // @[el2_pic_ctl.scala 47:8] - wire _T_1258 = extintsrc_req_sync[25] ^ gw_config_reg_25[0]; // @[el2_pic_ctl.scala 45:50] - wire _T_1259 = ~gw_clear_reg_we_25; // @[el2_pic_ctl.scala 45:92] - reg gw_int_pending_24; // @[el2_pic_ctl.scala 46:30] - wire _T_1260 = gw_int_pending_24 & _T_1259; // @[el2_pic_ctl.scala 45:90] - wire _T_1264 = _T_1258 | gw_int_pending_24; // @[el2_pic_ctl.scala 47:78] - wire extintsrc_req_gw_25 = gw_config_reg_25[1] ? _T_1264 : _T_1258; // @[el2_pic_ctl.scala 47:8] - wire _T_1270 = extintsrc_req_sync[26] ^ gw_config_reg_26[0]; // @[el2_pic_ctl.scala 45:50] - wire _T_1271 = ~gw_clear_reg_we_26; // @[el2_pic_ctl.scala 45:92] - reg gw_int_pending_25; // @[el2_pic_ctl.scala 46:30] - wire _T_1272 = gw_int_pending_25 & _T_1271; // @[el2_pic_ctl.scala 45:90] - wire _T_1276 = _T_1270 | gw_int_pending_25; // @[el2_pic_ctl.scala 47:78] - wire extintsrc_req_gw_26 = gw_config_reg_26[1] ? _T_1276 : _T_1270; // @[el2_pic_ctl.scala 47:8] - wire _T_1282 = extintsrc_req_sync[27] ^ gw_config_reg_27[0]; // @[el2_pic_ctl.scala 45:50] - wire _T_1283 = ~gw_clear_reg_we_27; // @[el2_pic_ctl.scala 45:92] - reg gw_int_pending_26; // @[el2_pic_ctl.scala 46:30] - wire _T_1284 = gw_int_pending_26 & _T_1283; // @[el2_pic_ctl.scala 45:90] - wire _T_1288 = _T_1282 | gw_int_pending_26; // @[el2_pic_ctl.scala 47:78] - wire extintsrc_req_gw_27 = gw_config_reg_27[1] ? _T_1288 : _T_1282; // @[el2_pic_ctl.scala 47:8] - wire _T_1294 = extintsrc_req_sync[28] ^ gw_config_reg_28[0]; // @[el2_pic_ctl.scala 45:50] - wire _T_1295 = ~gw_clear_reg_we_28; // @[el2_pic_ctl.scala 45:92] - reg gw_int_pending_27; // @[el2_pic_ctl.scala 46:30] - wire _T_1296 = gw_int_pending_27 & _T_1295; // @[el2_pic_ctl.scala 45:90] - wire _T_1300 = _T_1294 | gw_int_pending_27; // @[el2_pic_ctl.scala 47:78] - wire extintsrc_req_gw_28 = gw_config_reg_28[1] ? _T_1300 : _T_1294; // @[el2_pic_ctl.scala 47:8] - wire _T_1306 = extintsrc_req_sync[29] ^ gw_config_reg_29[0]; // @[el2_pic_ctl.scala 45:50] - wire _T_1307 = ~gw_clear_reg_we_29; // @[el2_pic_ctl.scala 45:92] - reg gw_int_pending_28; // @[el2_pic_ctl.scala 46:30] - wire _T_1308 = gw_int_pending_28 & _T_1307; // @[el2_pic_ctl.scala 45:90] - wire _T_1312 = _T_1306 | gw_int_pending_28; // @[el2_pic_ctl.scala 47:78] - wire extintsrc_req_gw_29 = gw_config_reg_29[1] ? _T_1312 : _T_1306; // @[el2_pic_ctl.scala 47:8] - wire _T_1318 = extintsrc_req_sync[30] ^ gw_config_reg_30[0]; // @[el2_pic_ctl.scala 45:50] - wire _T_1319 = ~gw_clear_reg_we_30; // @[el2_pic_ctl.scala 45:92] - reg gw_int_pending_29; // @[el2_pic_ctl.scala 46:30] - wire _T_1320 = gw_int_pending_29 & _T_1319; // @[el2_pic_ctl.scala 45:90] - wire _T_1324 = _T_1318 | gw_int_pending_29; // @[el2_pic_ctl.scala 47:78] - wire extintsrc_req_gw_30 = gw_config_reg_30[1] ? _T_1324 : _T_1318; // @[el2_pic_ctl.scala 47:8] - wire _T_1330 = extintsrc_req_sync[31] ^ gw_config_reg_31[0]; // @[el2_pic_ctl.scala 45:50] - wire _T_1331 = ~gw_clear_reg_we_31; // @[el2_pic_ctl.scala 45:92] - reg gw_int_pending_30; // @[el2_pic_ctl.scala 46:30] - wire _T_1332 = gw_int_pending_30 & _T_1331; // @[el2_pic_ctl.scala 45:90] - wire _T_1336 = _T_1330 | gw_int_pending_30; // @[el2_pic_ctl.scala 47:78] - wire extintsrc_req_gw_31 = gw_config_reg_31[1] ? _T_1336 : _T_1330; // @[el2_pic_ctl.scala 47:8] + wire _T_970 = extintsrc_req_sync[1] ^ gw_config_reg_1[0]; // @[el2_pic_ctl.scala 37:50] + wire _T_971 = ~gw_clear_reg_we_1; // @[el2_pic_ctl.scala 37:92] + reg gw_int_pending; // @[el2_pic_ctl.scala 38:30] + wire _T_972 = gw_int_pending & _T_971; // @[el2_pic_ctl.scala 37:90] + wire _T_976 = _T_970 | gw_int_pending; // @[el2_pic_ctl.scala 39:78] + wire extintsrc_req_gw_1 = gw_config_reg_1[1] ? _T_976 : _T_970; // @[el2_pic_ctl.scala 39:8] + wire _T_982 = extintsrc_req_sync[2] ^ gw_config_reg_2[0]; // @[el2_pic_ctl.scala 37:50] + wire _T_983 = ~gw_clear_reg_we_2; // @[el2_pic_ctl.scala 37:92] + reg gw_int_pending_1; // @[el2_pic_ctl.scala 38:30] + wire _T_984 = gw_int_pending_1 & _T_983; // @[el2_pic_ctl.scala 37:90] + wire _T_988 = _T_982 | gw_int_pending_1; // @[el2_pic_ctl.scala 39:78] + wire extintsrc_req_gw_2 = gw_config_reg_2[1] ? _T_988 : _T_982; // @[el2_pic_ctl.scala 39:8] + wire _T_994 = extintsrc_req_sync[3] ^ gw_config_reg_3[0]; // @[el2_pic_ctl.scala 37:50] + wire _T_995 = ~gw_clear_reg_we_3; // @[el2_pic_ctl.scala 37:92] + reg gw_int_pending_2; // @[el2_pic_ctl.scala 38:30] + wire _T_996 = gw_int_pending_2 & _T_995; // @[el2_pic_ctl.scala 37:90] + wire _T_1000 = _T_994 | gw_int_pending_2; // @[el2_pic_ctl.scala 39:78] + wire extintsrc_req_gw_3 = gw_config_reg_3[1] ? _T_1000 : _T_994; // @[el2_pic_ctl.scala 39:8] + wire _T_1006 = extintsrc_req_sync[4] ^ gw_config_reg_4[0]; // @[el2_pic_ctl.scala 37:50] + wire _T_1007 = ~gw_clear_reg_we_4; // @[el2_pic_ctl.scala 37:92] + reg gw_int_pending_3; // @[el2_pic_ctl.scala 38:30] + wire _T_1008 = gw_int_pending_3 & _T_1007; // @[el2_pic_ctl.scala 37:90] + wire _T_1012 = _T_1006 | gw_int_pending_3; // @[el2_pic_ctl.scala 39:78] + wire extintsrc_req_gw_4 = gw_config_reg_4[1] ? _T_1012 : _T_1006; // @[el2_pic_ctl.scala 39:8] + wire _T_1018 = extintsrc_req_sync[5] ^ gw_config_reg_5[0]; // @[el2_pic_ctl.scala 37:50] + wire _T_1019 = ~gw_clear_reg_we_5; // @[el2_pic_ctl.scala 37:92] + reg gw_int_pending_4; // @[el2_pic_ctl.scala 38:30] + wire _T_1020 = gw_int_pending_4 & _T_1019; // @[el2_pic_ctl.scala 37:90] + wire _T_1024 = _T_1018 | gw_int_pending_4; // @[el2_pic_ctl.scala 39:78] + wire extintsrc_req_gw_5 = gw_config_reg_5[1] ? _T_1024 : _T_1018; // @[el2_pic_ctl.scala 39:8] + wire _T_1030 = extintsrc_req_sync[6] ^ gw_config_reg_6[0]; // @[el2_pic_ctl.scala 37:50] + wire _T_1031 = ~gw_clear_reg_we_6; // @[el2_pic_ctl.scala 37:92] + reg gw_int_pending_5; // @[el2_pic_ctl.scala 38:30] + wire _T_1032 = gw_int_pending_5 & _T_1031; // @[el2_pic_ctl.scala 37:90] + wire _T_1036 = _T_1030 | gw_int_pending_5; // @[el2_pic_ctl.scala 39:78] + wire extintsrc_req_gw_6 = gw_config_reg_6[1] ? _T_1036 : _T_1030; // @[el2_pic_ctl.scala 39:8] + wire _T_1042 = extintsrc_req_sync[7] ^ gw_config_reg_7[0]; // @[el2_pic_ctl.scala 37:50] + wire _T_1043 = ~gw_clear_reg_we_7; // @[el2_pic_ctl.scala 37:92] + reg gw_int_pending_6; // @[el2_pic_ctl.scala 38:30] + wire _T_1044 = gw_int_pending_6 & _T_1043; // @[el2_pic_ctl.scala 37:90] + wire _T_1048 = _T_1042 | gw_int_pending_6; // @[el2_pic_ctl.scala 39:78] + wire extintsrc_req_gw_7 = gw_config_reg_7[1] ? _T_1048 : _T_1042; // @[el2_pic_ctl.scala 39:8] + wire _T_1054 = extintsrc_req_sync[8] ^ gw_config_reg_8[0]; // @[el2_pic_ctl.scala 37:50] + wire _T_1055 = ~gw_clear_reg_we_8; // @[el2_pic_ctl.scala 37:92] + reg gw_int_pending_7; // @[el2_pic_ctl.scala 38:30] + wire _T_1056 = gw_int_pending_7 & _T_1055; // @[el2_pic_ctl.scala 37:90] + wire _T_1060 = _T_1054 | gw_int_pending_7; // @[el2_pic_ctl.scala 39:78] + wire extintsrc_req_gw_8 = gw_config_reg_8[1] ? _T_1060 : _T_1054; // @[el2_pic_ctl.scala 39:8] + wire _T_1066 = extintsrc_req_sync[9] ^ gw_config_reg_9[0]; // @[el2_pic_ctl.scala 37:50] + wire _T_1067 = ~gw_clear_reg_we_9; // @[el2_pic_ctl.scala 37:92] + reg gw_int_pending_8; // @[el2_pic_ctl.scala 38:30] + wire _T_1068 = gw_int_pending_8 & _T_1067; // @[el2_pic_ctl.scala 37:90] + wire _T_1072 = _T_1066 | gw_int_pending_8; // @[el2_pic_ctl.scala 39:78] + wire extintsrc_req_gw_9 = gw_config_reg_9[1] ? _T_1072 : _T_1066; // @[el2_pic_ctl.scala 39:8] + wire _T_1078 = extintsrc_req_sync[10] ^ gw_config_reg_10[0]; // @[el2_pic_ctl.scala 37:50] + wire _T_1079 = ~gw_clear_reg_we_10; // @[el2_pic_ctl.scala 37:92] + reg gw_int_pending_9; // @[el2_pic_ctl.scala 38:30] + wire _T_1080 = gw_int_pending_9 & _T_1079; // @[el2_pic_ctl.scala 37:90] + wire _T_1084 = _T_1078 | gw_int_pending_9; // @[el2_pic_ctl.scala 39:78] + wire extintsrc_req_gw_10 = gw_config_reg_10[1] ? _T_1084 : _T_1078; // @[el2_pic_ctl.scala 39:8] + wire _T_1090 = extintsrc_req_sync[11] ^ gw_config_reg_11[0]; // @[el2_pic_ctl.scala 37:50] + wire _T_1091 = ~gw_clear_reg_we_11; // @[el2_pic_ctl.scala 37:92] + reg gw_int_pending_10; // @[el2_pic_ctl.scala 38:30] + wire _T_1092 = gw_int_pending_10 & _T_1091; // @[el2_pic_ctl.scala 37:90] + wire _T_1096 = _T_1090 | gw_int_pending_10; // @[el2_pic_ctl.scala 39:78] + wire extintsrc_req_gw_11 = gw_config_reg_11[1] ? _T_1096 : _T_1090; // @[el2_pic_ctl.scala 39:8] + wire _T_1102 = extintsrc_req_sync[12] ^ gw_config_reg_12[0]; // @[el2_pic_ctl.scala 37:50] + wire _T_1103 = ~gw_clear_reg_we_12; // @[el2_pic_ctl.scala 37:92] + reg gw_int_pending_11; // @[el2_pic_ctl.scala 38:30] + wire _T_1104 = gw_int_pending_11 & _T_1103; // @[el2_pic_ctl.scala 37:90] + wire _T_1108 = _T_1102 | gw_int_pending_11; // @[el2_pic_ctl.scala 39:78] + wire extintsrc_req_gw_12 = gw_config_reg_12[1] ? _T_1108 : _T_1102; // @[el2_pic_ctl.scala 39:8] + wire _T_1114 = extintsrc_req_sync[13] ^ gw_config_reg_13[0]; // @[el2_pic_ctl.scala 37:50] + wire _T_1115 = ~gw_clear_reg_we_13; // @[el2_pic_ctl.scala 37:92] + reg gw_int_pending_12; // @[el2_pic_ctl.scala 38:30] + wire _T_1116 = gw_int_pending_12 & _T_1115; // @[el2_pic_ctl.scala 37:90] + wire _T_1120 = _T_1114 | gw_int_pending_12; // @[el2_pic_ctl.scala 39:78] + wire extintsrc_req_gw_13 = gw_config_reg_13[1] ? _T_1120 : _T_1114; // @[el2_pic_ctl.scala 39:8] + wire _T_1126 = extintsrc_req_sync[14] ^ gw_config_reg_14[0]; // @[el2_pic_ctl.scala 37:50] + wire _T_1127 = ~gw_clear_reg_we_14; // @[el2_pic_ctl.scala 37:92] + reg gw_int_pending_13; // @[el2_pic_ctl.scala 38:30] + wire _T_1128 = gw_int_pending_13 & _T_1127; // @[el2_pic_ctl.scala 37:90] + wire _T_1132 = _T_1126 | gw_int_pending_13; // @[el2_pic_ctl.scala 39:78] + wire extintsrc_req_gw_14 = gw_config_reg_14[1] ? _T_1132 : _T_1126; // @[el2_pic_ctl.scala 39:8] + wire _T_1138 = extintsrc_req_sync[15] ^ gw_config_reg_15[0]; // @[el2_pic_ctl.scala 37:50] + wire _T_1139 = ~gw_clear_reg_we_15; // @[el2_pic_ctl.scala 37:92] + reg gw_int_pending_14; // @[el2_pic_ctl.scala 38:30] + wire _T_1140 = gw_int_pending_14 & _T_1139; // @[el2_pic_ctl.scala 37:90] + wire _T_1144 = _T_1138 | gw_int_pending_14; // @[el2_pic_ctl.scala 39:78] + wire extintsrc_req_gw_15 = gw_config_reg_15[1] ? _T_1144 : _T_1138; // @[el2_pic_ctl.scala 39:8] + wire _T_1150 = extintsrc_req_sync[16] ^ gw_config_reg_16[0]; // @[el2_pic_ctl.scala 37:50] + wire _T_1151 = ~gw_clear_reg_we_16; // @[el2_pic_ctl.scala 37:92] + reg gw_int_pending_15; // @[el2_pic_ctl.scala 38:30] + wire _T_1152 = gw_int_pending_15 & _T_1151; // @[el2_pic_ctl.scala 37:90] + wire _T_1156 = _T_1150 | gw_int_pending_15; // @[el2_pic_ctl.scala 39:78] + wire extintsrc_req_gw_16 = gw_config_reg_16[1] ? _T_1156 : _T_1150; // @[el2_pic_ctl.scala 39:8] + wire _T_1162 = extintsrc_req_sync[17] ^ gw_config_reg_17[0]; // @[el2_pic_ctl.scala 37:50] + wire _T_1163 = ~gw_clear_reg_we_17; // @[el2_pic_ctl.scala 37:92] + reg gw_int_pending_16; // @[el2_pic_ctl.scala 38:30] + wire _T_1164 = gw_int_pending_16 & _T_1163; // @[el2_pic_ctl.scala 37:90] + wire _T_1168 = _T_1162 | gw_int_pending_16; // @[el2_pic_ctl.scala 39:78] + wire extintsrc_req_gw_17 = gw_config_reg_17[1] ? _T_1168 : _T_1162; // @[el2_pic_ctl.scala 39:8] + wire _T_1174 = extintsrc_req_sync[18] ^ gw_config_reg_18[0]; // @[el2_pic_ctl.scala 37:50] + wire _T_1175 = ~gw_clear_reg_we_18; // @[el2_pic_ctl.scala 37:92] + reg gw_int_pending_17; // @[el2_pic_ctl.scala 38:30] + wire _T_1176 = gw_int_pending_17 & _T_1175; // @[el2_pic_ctl.scala 37:90] + wire _T_1180 = _T_1174 | gw_int_pending_17; // @[el2_pic_ctl.scala 39:78] + wire extintsrc_req_gw_18 = gw_config_reg_18[1] ? _T_1180 : _T_1174; // @[el2_pic_ctl.scala 39:8] + wire _T_1186 = extintsrc_req_sync[19] ^ gw_config_reg_19[0]; // @[el2_pic_ctl.scala 37:50] + wire _T_1187 = ~gw_clear_reg_we_19; // @[el2_pic_ctl.scala 37:92] + reg gw_int_pending_18; // @[el2_pic_ctl.scala 38:30] + wire _T_1188 = gw_int_pending_18 & _T_1187; // @[el2_pic_ctl.scala 37:90] + wire _T_1192 = _T_1186 | gw_int_pending_18; // @[el2_pic_ctl.scala 39:78] + wire extintsrc_req_gw_19 = gw_config_reg_19[1] ? _T_1192 : _T_1186; // @[el2_pic_ctl.scala 39:8] + wire _T_1198 = extintsrc_req_sync[20] ^ gw_config_reg_20[0]; // @[el2_pic_ctl.scala 37:50] + wire _T_1199 = ~gw_clear_reg_we_20; // @[el2_pic_ctl.scala 37:92] + reg gw_int_pending_19; // @[el2_pic_ctl.scala 38:30] + wire _T_1200 = gw_int_pending_19 & _T_1199; // @[el2_pic_ctl.scala 37:90] + wire _T_1204 = _T_1198 | gw_int_pending_19; // @[el2_pic_ctl.scala 39:78] + wire extintsrc_req_gw_20 = gw_config_reg_20[1] ? _T_1204 : _T_1198; // @[el2_pic_ctl.scala 39:8] + wire _T_1210 = extintsrc_req_sync[21] ^ gw_config_reg_21[0]; // @[el2_pic_ctl.scala 37:50] + wire _T_1211 = ~gw_clear_reg_we_21; // @[el2_pic_ctl.scala 37:92] + reg gw_int_pending_20; // @[el2_pic_ctl.scala 38:30] + wire _T_1212 = gw_int_pending_20 & _T_1211; // @[el2_pic_ctl.scala 37:90] + wire _T_1216 = _T_1210 | gw_int_pending_20; // @[el2_pic_ctl.scala 39:78] + wire extintsrc_req_gw_21 = gw_config_reg_21[1] ? _T_1216 : _T_1210; // @[el2_pic_ctl.scala 39:8] + wire _T_1222 = extintsrc_req_sync[22] ^ gw_config_reg_22[0]; // @[el2_pic_ctl.scala 37:50] + wire _T_1223 = ~gw_clear_reg_we_22; // @[el2_pic_ctl.scala 37:92] + reg gw_int_pending_21; // @[el2_pic_ctl.scala 38:30] + wire _T_1224 = gw_int_pending_21 & _T_1223; // @[el2_pic_ctl.scala 37:90] + wire _T_1228 = _T_1222 | gw_int_pending_21; // @[el2_pic_ctl.scala 39:78] + wire extintsrc_req_gw_22 = gw_config_reg_22[1] ? _T_1228 : _T_1222; // @[el2_pic_ctl.scala 39:8] + wire _T_1234 = extintsrc_req_sync[23] ^ gw_config_reg_23[0]; // @[el2_pic_ctl.scala 37:50] + wire _T_1235 = ~gw_clear_reg_we_23; // @[el2_pic_ctl.scala 37:92] + reg gw_int_pending_22; // @[el2_pic_ctl.scala 38:30] + wire _T_1236 = gw_int_pending_22 & _T_1235; // @[el2_pic_ctl.scala 37:90] + wire _T_1240 = _T_1234 | gw_int_pending_22; // @[el2_pic_ctl.scala 39:78] + wire extintsrc_req_gw_23 = gw_config_reg_23[1] ? _T_1240 : _T_1234; // @[el2_pic_ctl.scala 39:8] + wire _T_1246 = extintsrc_req_sync[24] ^ gw_config_reg_24[0]; // @[el2_pic_ctl.scala 37:50] + wire _T_1247 = ~gw_clear_reg_we_24; // @[el2_pic_ctl.scala 37:92] + reg gw_int_pending_23; // @[el2_pic_ctl.scala 38:30] + wire _T_1248 = gw_int_pending_23 & _T_1247; // @[el2_pic_ctl.scala 37:90] + wire _T_1252 = _T_1246 | gw_int_pending_23; // @[el2_pic_ctl.scala 39:78] + wire extintsrc_req_gw_24 = gw_config_reg_24[1] ? _T_1252 : _T_1246; // @[el2_pic_ctl.scala 39:8] + wire _T_1258 = extintsrc_req_sync[25] ^ gw_config_reg_25[0]; // @[el2_pic_ctl.scala 37:50] + wire _T_1259 = ~gw_clear_reg_we_25; // @[el2_pic_ctl.scala 37:92] + reg gw_int_pending_24; // @[el2_pic_ctl.scala 38:30] + wire _T_1260 = gw_int_pending_24 & _T_1259; // @[el2_pic_ctl.scala 37:90] + wire _T_1264 = _T_1258 | gw_int_pending_24; // @[el2_pic_ctl.scala 39:78] + wire extintsrc_req_gw_25 = gw_config_reg_25[1] ? _T_1264 : _T_1258; // @[el2_pic_ctl.scala 39:8] + wire _T_1270 = extintsrc_req_sync[26] ^ gw_config_reg_26[0]; // @[el2_pic_ctl.scala 37:50] + wire _T_1271 = ~gw_clear_reg_we_26; // @[el2_pic_ctl.scala 37:92] + reg gw_int_pending_25; // @[el2_pic_ctl.scala 38:30] + wire _T_1272 = gw_int_pending_25 & _T_1271; // @[el2_pic_ctl.scala 37:90] + wire _T_1276 = _T_1270 | gw_int_pending_25; // @[el2_pic_ctl.scala 39:78] + wire extintsrc_req_gw_26 = gw_config_reg_26[1] ? _T_1276 : _T_1270; // @[el2_pic_ctl.scala 39:8] + wire _T_1282 = extintsrc_req_sync[27] ^ gw_config_reg_27[0]; // @[el2_pic_ctl.scala 37:50] + wire _T_1283 = ~gw_clear_reg_we_27; // @[el2_pic_ctl.scala 37:92] + reg gw_int_pending_26; // @[el2_pic_ctl.scala 38:30] + wire _T_1284 = gw_int_pending_26 & _T_1283; // @[el2_pic_ctl.scala 37:90] + wire _T_1288 = _T_1282 | gw_int_pending_26; // @[el2_pic_ctl.scala 39:78] + wire extintsrc_req_gw_27 = gw_config_reg_27[1] ? _T_1288 : _T_1282; // @[el2_pic_ctl.scala 39:8] + wire _T_1294 = extintsrc_req_sync[28] ^ gw_config_reg_28[0]; // @[el2_pic_ctl.scala 37:50] + wire _T_1295 = ~gw_clear_reg_we_28; // @[el2_pic_ctl.scala 37:92] + reg gw_int_pending_27; // @[el2_pic_ctl.scala 38:30] + wire _T_1296 = gw_int_pending_27 & _T_1295; // @[el2_pic_ctl.scala 37:90] + wire _T_1300 = _T_1294 | gw_int_pending_27; // @[el2_pic_ctl.scala 39:78] + wire extintsrc_req_gw_28 = gw_config_reg_28[1] ? _T_1300 : _T_1294; // @[el2_pic_ctl.scala 39:8] + wire _T_1306 = extintsrc_req_sync[29] ^ gw_config_reg_29[0]; // @[el2_pic_ctl.scala 37:50] + wire _T_1307 = ~gw_clear_reg_we_29; // @[el2_pic_ctl.scala 37:92] + reg gw_int_pending_28; // @[el2_pic_ctl.scala 38:30] + wire _T_1308 = gw_int_pending_28 & _T_1307; // @[el2_pic_ctl.scala 37:90] + wire _T_1312 = _T_1306 | gw_int_pending_28; // @[el2_pic_ctl.scala 39:78] + wire extintsrc_req_gw_29 = gw_config_reg_29[1] ? _T_1312 : _T_1306; // @[el2_pic_ctl.scala 39:8] + wire _T_1318 = extintsrc_req_sync[30] ^ gw_config_reg_30[0]; // @[el2_pic_ctl.scala 37:50] + wire _T_1319 = ~gw_clear_reg_we_30; // @[el2_pic_ctl.scala 37:92] + reg gw_int_pending_29; // @[el2_pic_ctl.scala 38:30] + wire _T_1320 = gw_int_pending_29 & _T_1319; // @[el2_pic_ctl.scala 37:90] + wire _T_1324 = _T_1318 | gw_int_pending_29; // @[el2_pic_ctl.scala 39:78] + wire extintsrc_req_gw_30 = gw_config_reg_30[1] ? _T_1324 : _T_1318; // @[el2_pic_ctl.scala 39:8] + wire _T_1330 = extintsrc_req_sync[31] ^ gw_config_reg_31[0]; // @[el2_pic_ctl.scala 37:50] + wire _T_1331 = ~gw_clear_reg_we_31; // @[el2_pic_ctl.scala 37:92] + reg gw_int_pending_30; // @[el2_pic_ctl.scala 38:30] + wire _T_1332 = gw_int_pending_30 & _T_1331; // @[el2_pic_ctl.scala 37:90] + wire _T_1336 = _T_1330 | gw_int_pending_30; // @[el2_pic_ctl.scala 39:78] + wire extintsrc_req_gw_31 = gw_config_reg_31[1] ? _T_1336 : _T_1330; // @[el2_pic_ctl.scala 39:8] reg config_reg; // @[Reg.scala 27:20] - wire [3:0] intpriority_reg_0 = 4'h0; // @[el2_pic_ctl.scala 162:32 el2_pic_ctl.scala 163:208] - wire [3:0] _T_1342 = ~intpriority_reg_1; // @[el2_pic_ctl.scala 174:89] - wire [3:0] intpriority_reg_inv_1 = config_reg ? _T_1342 : intpriority_reg_1; // @[el2_pic_ctl.scala 174:70] - wire [3:0] _T_1345 = ~intpriority_reg_2; // @[el2_pic_ctl.scala 174:89] - wire [3:0] intpriority_reg_inv_2 = config_reg ? _T_1345 : intpriority_reg_2; // @[el2_pic_ctl.scala 174:70] - wire [3:0] _T_1348 = ~intpriority_reg_3; // @[el2_pic_ctl.scala 174:89] - wire [3:0] intpriority_reg_inv_3 = config_reg ? _T_1348 : intpriority_reg_3; // @[el2_pic_ctl.scala 174:70] - wire [3:0] _T_1351 = ~intpriority_reg_4; // @[el2_pic_ctl.scala 174:89] - wire [3:0] intpriority_reg_inv_4 = config_reg ? _T_1351 : intpriority_reg_4; // @[el2_pic_ctl.scala 174:70] - wire [3:0] _T_1354 = ~intpriority_reg_5; // @[el2_pic_ctl.scala 174:89] - wire [3:0] intpriority_reg_inv_5 = config_reg ? _T_1354 : intpriority_reg_5; // @[el2_pic_ctl.scala 174:70] - wire [3:0] _T_1357 = ~intpriority_reg_6; // @[el2_pic_ctl.scala 174:89] - wire [3:0] intpriority_reg_inv_6 = config_reg ? _T_1357 : intpriority_reg_6; // @[el2_pic_ctl.scala 174:70] - wire [3:0] _T_1360 = ~intpriority_reg_7; // @[el2_pic_ctl.scala 174:89] - wire [3:0] intpriority_reg_inv_7 = config_reg ? _T_1360 : intpriority_reg_7; // @[el2_pic_ctl.scala 174:70] - wire [3:0] _T_1363 = ~intpriority_reg_8; // @[el2_pic_ctl.scala 174:89] - wire [3:0] intpriority_reg_inv_8 = config_reg ? _T_1363 : intpriority_reg_8; // @[el2_pic_ctl.scala 174:70] - wire [3:0] _T_1366 = ~intpriority_reg_9; // @[el2_pic_ctl.scala 174:89] - wire [3:0] intpriority_reg_inv_9 = config_reg ? _T_1366 : intpriority_reg_9; // @[el2_pic_ctl.scala 174:70] - wire [3:0] _T_1369 = ~intpriority_reg_10; // @[el2_pic_ctl.scala 174:89] - wire [3:0] intpriority_reg_inv_10 = config_reg ? _T_1369 : intpriority_reg_10; // @[el2_pic_ctl.scala 174:70] - wire [3:0] _T_1372 = ~intpriority_reg_11; // @[el2_pic_ctl.scala 174:89] - wire [3:0] intpriority_reg_inv_11 = config_reg ? _T_1372 : intpriority_reg_11; // @[el2_pic_ctl.scala 174:70] - wire [3:0] _T_1375 = ~intpriority_reg_12; // @[el2_pic_ctl.scala 174:89] - wire [3:0] intpriority_reg_inv_12 = config_reg ? _T_1375 : intpriority_reg_12; // @[el2_pic_ctl.scala 174:70] - wire [3:0] _T_1378 = ~intpriority_reg_13; // @[el2_pic_ctl.scala 174:89] - wire [3:0] intpriority_reg_inv_13 = config_reg ? _T_1378 : intpriority_reg_13; // @[el2_pic_ctl.scala 174:70] - wire [3:0] _T_1381 = ~intpriority_reg_14; // @[el2_pic_ctl.scala 174:89] - wire [3:0] intpriority_reg_inv_14 = config_reg ? _T_1381 : intpriority_reg_14; // @[el2_pic_ctl.scala 174:70] - wire [3:0] _T_1384 = ~intpriority_reg_15; // @[el2_pic_ctl.scala 174:89] - wire [3:0] intpriority_reg_inv_15 = config_reg ? _T_1384 : intpriority_reg_15; // @[el2_pic_ctl.scala 174:70] - wire [3:0] _T_1387 = ~intpriority_reg_16; // @[el2_pic_ctl.scala 174:89] - wire [3:0] intpriority_reg_inv_16 = config_reg ? _T_1387 : intpriority_reg_16; // @[el2_pic_ctl.scala 174:70] - wire [3:0] _T_1390 = ~intpriority_reg_17; // @[el2_pic_ctl.scala 174:89] - wire [3:0] intpriority_reg_inv_17 = config_reg ? _T_1390 : intpriority_reg_17; // @[el2_pic_ctl.scala 174:70] - wire [3:0] _T_1393 = ~intpriority_reg_18; // @[el2_pic_ctl.scala 174:89] - wire [3:0] intpriority_reg_inv_18 = config_reg ? _T_1393 : intpriority_reg_18; // @[el2_pic_ctl.scala 174:70] - wire [3:0] _T_1396 = ~intpriority_reg_19; // @[el2_pic_ctl.scala 174:89] - wire [3:0] intpriority_reg_inv_19 = config_reg ? _T_1396 : intpriority_reg_19; // @[el2_pic_ctl.scala 174:70] - wire [3:0] _T_1399 = ~intpriority_reg_20; // @[el2_pic_ctl.scala 174:89] - wire [3:0] intpriority_reg_inv_20 = config_reg ? _T_1399 : intpriority_reg_20; // @[el2_pic_ctl.scala 174:70] - wire [3:0] _T_1402 = ~intpriority_reg_21; // @[el2_pic_ctl.scala 174:89] - wire [3:0] intpriority_reg_inv_21 = config_reg ? _T_1402 : intpriority_reg_21; // @[el2_pic_ctl.scala 174:70] - wire [3:0] _T_1405 = ~intpriority_reg_22; // @[el2_pic_ctl.scala 174:89] - wire [3:0] intpriority_reg_inv_22 = config_reg ? _T_1405 : intpriority_reg_22; // @[el2_pic_ctl.scala 174:70] - wire [3:0] _T_1408 = ~intpriority_reg_23; // @[el2_pic_ctl.scala 174:89] - wire [3:0] intpriority_reg_inv_23 = config_reg ? _T_1408 : intpriority_reg_23; // @[el2_pic_ctl.scala 174:70] - wire [3:0] _T_1411 = ~intpriority_reg_24; // @[el2_pic_ctl.scala 174:89] - wire [3:0] intpriority_reg_inv_24 = config_reg ? _T_1411 : intpriority_reg_24; // @[el2_pic_ctl.scala 174:70] - wire [3:0] _T_1414 = ~intpriority_reg_25; // @[el2_pic_ctl.scala 174:89] - wire [3:0] intpriority_reg_inv_25 = config_reg ? _T_1414 : intpriority_reg_25; // @[el2_pic_ctl.scala 174:70] - wire [3:0] _T_1417 = ~intpriority_reg_26; // @[el2_pic_ctl.scala 174:89] - wire [3:0] intpriority_reg_inv_26 = config_reg ? _T_1417 : intpriority_reg_26; // @[el2_pic_ctl.scala 174:70] - wire [3:0] _T_1420 = ~intpriority_reg_27; // @[el2_pic_ctl.scala 174:89] - wire [3:0] intpriority_reg_inv_27 = config_reg ? _T_1420 : intpriority_reg_27; // @[el2_pic_ctl.scala 174:70] - wire [3:0] _T_1423 = ~intpriority_reg_28; // @[el2_pic_ctl.scala 174:89] - wire [3:0] intpriority_reg_inv_28 = config_reg ? _T_1423 : intpriority_reg_28; // @[el2_pic_ctl.scala 174:70] - wire [3:0] _T_1426 = ~intpriority_reg_29; // @[el2_pic_ctl.scala 174:89] - wire [3:0] intpriority_reg_inv_29 = config_reg ? _T_1426 : intpriority_reg_29; // @[el2_pic_ctl.scala 174:70] - wire [3:0] _T_1429 = ~intpriority_reg_30; // @[el2_pic_ctl.scala 174:89] - wire [3:0] intpriority_reg_inv_30 = config_reg ? _T_1429 : intpriority_reg_30; // @[el2_pic_ctl.scala 174:70] - wire [3:0] _T_1432 = ~intpriority_reg_31; // @[el2_pic_ctl.scala 174:89] - wire [3:0] intpriority_reg_inv_31 = config_reg ? _T_1432 : intpriority_reg_31; // @[el2_pic_ctl.scala 174:70] - wire _T_1438 = extintsrc_req_gw_1 & intenable_reg_1; // @[el2_pic_ctl.scala 175:109] + wire [3:0] intpriority_reg_0 = 4'h0; // @[el2_pic_ctl.scala 154:32 el2_pic_ctl.scala 155:208] + wire [3:0] _T_1342 = ~intpriority_reg_1; // @[el2_pic_ctl.scala 166:89] + wire [3:0] intpriority_reg_inv_1 = config_reg ? _T_1342 : intpriority_reg_1; // @[el2_pic_ctl.scala 166:70] + wire [3:0] _T_1345 = ~intpriority_reg_2; // @[el2_pic_ctl.scala 166:89] + wire [3:0] intpriority_reg_inv_2 = config_reg ? _T_1345 : intpriority_reg_2; // @[el2_pic_ctl.scala 166:70] + wire [3:0] _T_1348 = ~intpriority_reg_3; // @[el2_pic_ctl.scala 166:89] + wire [3:0] intpriority_reg_inv_3 = config_reg ? _T_1348 : intpriority_reg_3; // @[el2_pic_ctl.scala 166:70] + wire [3:0] _T_1351 = ~intpriority_reg_4; // @[el2_pic_ctl.scala 166:89] + wire [3:0] intpriority_reg_inv_4 = config_reg ? _T_1351 : intpriority_reg_4; // @[el2_pic_ctl.scala 166:70] + wire [3:0] _T_1354 = ~intpriority_reg_5; // @[el2_pic_ctl.scala 166:89] + wire [3:0] intpriority_reg_inv_5 = config_reg ? _T_1354 : intpriority_reg_5; // @[el2_pic_ctl.scala 166:70] + wire [3:0] _T_1357 = ~intpriority_reg_6; // @[el2_pic_ctl.scala 166:89] + wire [3:0] intpriority_reg_inv_6 = config_reg ? _T_1357 : intpriority_reg_6; // @[el2_pic_ctl.scala 166:70] + wire [3:0] _T_1360 = ~intpriority_reg_7; // @[el2_pic_ctl.scala 166:89] + wire [3:0] intpriority_reg_inv_7 = config_reg ? _T_1360 : intpriority_reg_7; // @[el2_pic_ctl.scala 166:70] + wire [3:0] _T_1363 = ~intpriority_reg_8; // @[el2_pic_ctl.scala 166:89] + wire [3:0] intpriority_reg_inv_8 = config_reg ? _T_1363 : intpriority_reg_8; // @[el2_pic_ctl.scala 166:70] + wire [3:0] _T_1366 = ~intpriority_reg_9; // @[el2_pic_ctl.scala 166:89] + wire [3:0] intpriority_reg_inv_9 = config_reg ? _T_1366 : intpriority_reg_9; // @[el2_pic_ctl.scala 166:70] + wire [3:0] _T_1369 = ~intpriority_reg_10; // @[el2_pic_ctl.scala 166:89] + wire [3:0] intpriority_reg_inv_10 = config_reg ? _T_1369 : intpriority_reg_10; // @[el2_pic_ctl.scala 166:70] + wire [3:0] _T_1372 = ~intpriority_reg_11; // @[el2_pic_ctl.scala 166:89] + wire [3:0] intpriority_reg_inv_11 = config_reg ? _T_1372 : intpriority_reg_11; // @[el2_pic_ctl.scala 166:70] + wire [3:0] _T_1375 = ~intpriority_reg_12; // @[el2_pic_ctl.scala 166:89] + wire [3:0] intpriority_reg_inv_12 = config_reg ? _T_1375 : intpriority_reg_12; // @[el2_pic_ctl.scala 166:70] + wire [3:0] _T_1378 = ~intpriority_reg_13; // @[el2_pic_ctl.scala 166:89] + wire [3:0] intpriority_reg_inv_13 = config_reg ? _T_1378 : intpriority_reg_13; // @[el2_pic_ctl.scala 166:70] + wire [3:0] _T_1381 = ~intpriority_reg_14; // @[el2_pic_ctl.scala 166:89] + wire [3:0] intpriority_reg_inv_14 = config_reg ? _T_1381 : intpriority_reg_14; // @[el2_pic_ctl.scala 166:70] + wire [3:0] _T_1384 = ~intpriority_reg_15; // @[el2_pic_ctl.scala 166:89] + wire [3:0] intpriority_reg_inv_15 = config_reg ? _T_1384 : intpriority_reg_15; // @[el2_pic_ctl.scala 166:70] + wire [3:0] _T_1387 = ~intpriority_reg_16; // @[el2_pic_ctl.scala 166:89] + wire [3:0] intpriority_reg_inv_16 = config_reg ? _T_1387 : intpriority_reg_16; // @[el2_pic_ctl.scala 166:70] + wire [3:0] _T_1390 = ~intpriority_reg_17; // @[el2_pic_ctl.scala 166:89] + wire [3:0] intpriority_reg_inv_17 = config_reg ? _T_1390 : intpriority_reg_17; // @[el2_pic_ctl.scala 166:70] + wire [3:0] _T_1393 = ~intpriority_reg_18; // @[el2_pic_ctl.scala 166:89] + wire [3:0] intpriority_reg_inv_18 = config_reg ? _T_1393 : intpriority_reg_18; // @[el2_pic_ctl.scala 166:70] + wire [3:0] _T_1396 = ~intpriority_reg_19; // @[el2_pic_ctl.scala 166:89] + wire [3:0] intpriority_reg_inv_19 = config_reg ? _T_1396 : intpriority_reg_19; // @[el2_pic_ctl.scala 166:70] + wire [3:0] _T_1399 = ~intpriority_reg_20; // @[el2_pic_ctl.scala 166:89] + wire [3:0] intpriority_reg_inv_20 = config_reg ? _T_1399 : intpriority_reg_20; // @[el2_pic_ctl.scala 166:70] + wire [3:0] _T_1402 = ~intpriority_reg_21; // @[el2_pic_ctl.scala 166:89] + wire [3:0] intpriority_reg_inv_21 = config_reg ? _T_1402 : intpriority_reg_21; // @[el2_pic_ctl.scala 166:70] + wire [3:0] _T_1405 = ~intpriority_reg_22; // @[el2_pic_ctl.scala 166:89] + wire [3:0] intpriority_reg_inv_22 = config_reg ? _T_1405 : intpriority_reg_22; // @[el2_pic_ctl.scala 166:70] + wire [3:0] _T_1408 = ~intpriority_reg_23; // @[el2_pic_ctl.scala 166:89] + wire [3:0] intpriority_reg_inv_23 = config_reg ? _T_1408 : intpriority_reg_23; // @[el2_pic_ctl.scala 166:70] + wire [3:0] _T_1411 = ~intpriority_reg_24; // @[el2_pic_ctl.scala 166:89] + wire [3:0] intpriority_reg_inv_24 = config_reg ? _T_1411 : intpriority_reg_24; // @[el2_pic_ctl.scala 166:70] + wire [3:0] _T_1414 = ~intpriority_reg_25; // @[el2_pic_ctl.scala 166:89] + wire [3:0] intpriority_reg_inv_25 = config_reg ? _T_1414 : intpriority_reg_25; // @[el2_pic_ctl.scala 166:70] + wire [3:0] _T_1417 = ~intpriority_reg_26; // @[el2_pic_ctl.scala 166:89] + wire [3:0] intpriority_reg_inv_26 = config_reg ? _T_1417 : intpriority_reg_26; // @[el2_pic_ctl.scala 166:70] + wire [3:0] _T_1420 = ~intpriority_reg_27; // @[el2_pic_ctl.scala 166:89] + wire [3:0] intpriority_reg_inv_27 = config_reg ? _T_1420 : intpriority_reg_27; // @[el2_pic_ctl.scala 166:70] + wire [3:0] _T_1423 = ~intpriority_reg_28; // @[el2_pic_ctl.scala 166:89] + wire [3:0] intpriority_reg_inv_28 = config_reg ? _T_1423 : intpriority_reg_28; // @[el2_pic_ctl.scala 166:70] + wire [3:0] _T_1426 = ~intpriority_reg_29; // @[el2_pic_ctl.scala 166:89] + wire [3:0] intpriority_reg_inv_29 = config_reg ? _T_1426 : intpriority_reg_29; // @[el2_pic_ctl.scala 166:70] + wire [3:0] _T_1429 = ~intpriority_reg_30; // @[el2_pic_ctl.scala 166:89] + wire [3:0] intpriority_reg_inv_30 = config_reg ? _T_1429 : intpriority_reg_30; // @[el2_pic_ctl.scala 166:70] + wire [3:0] _T_1432 = ~intpriority_reg_31; // @[el2_pic_ctl.scala 166:89] + wire [3:0] intpriority_reg_inv_31 = config_reg ? _T_1432 : intpriority_reg_31; // @[el2_pic_ctl.scala 166:70] + wire _T_1438 = extintsrc_req_gw_1 & intenable_reg_1; // @[el2_pic_ctl.scala 167:109] wire [3:0] _T_1440 = _T_1438 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_1 = _T_1440 & intpriority_reg_inv_1; // @[el2_pic_ctl.scala 175:129] - wire _T_1442 = extintsrc_req_gw_2 & intenable_reg_2; // @[el2_pic_ctl.scala 175:109] + wire [3:0] intpend_w_prior_en_1 = _T_1440 & intpriority_reg_inv_1; // @[el2_pic_ctl.scala 167:129] + wire _T_1442 = extintsrc_req_gw_2 & intenable_reg_2; // @[el2_pic_ctl.scala 167:109] wire [3:0] _T_1444 = _T_1442 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_2 = _T_1444 & intpriority_reg_inv_2; // @[el2_pic_ctl.scala 175:129] - wire _T_1446 = extintsrc_req_gw_3 & intenable_reg_3; // @[el2_pic_ctl.scala 175:109] + wire [3:0] intpend_w_prior_en_2 = _T_1444 & intpriority_reg_inv_2; // @[el2_pic_ctl.scala 167:129] + wire _T_1446 = extintsrc_req_gw_3 & intenable_reg_3; // @[el2_pic_ctl.scala 167:109] wire [3:0] _T_1448 = _T_1446 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_3 = _T_1448 & intpriority_reg_inv_3; // @[el2_pic_ctl.scala 175:129] - wire _T_1450 = extintsrc_req_gw_4 & intenable_reg_4; // @[el2_pic_ctl.scala 175:109] + wire [3:0] intpend_w_prior_en_3 = _T_1448 & intpriority_reg_inv_3; // @[el2_pic_ctl.scala 167:129] + wire _T_1450 = extintsrc_req_gw_4 & intenable_reg_4; // @[el2_pic_ctl.scala 167:109] wire [3:0] _T_1452 = _T_1450 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_4 = _T_1452 & intpriority_reg_inv_4; // @[el2_pic_ctl.scala 175:129] - wire _T_1454 = extintsrc_req_gw_5 & intenable_reg_5; // @[el2_pic_ctl.scala 175:109] + wire [3:0] intpend_w_prior_en_4 = _T_1452 & intpriority_reg_inv_4; // @[el2_pic_ctl.scala 167:129] + wire _T_1454 = extintsrc_req_gw_5 & intenable_reg_5; // @[el2_pic_ctl.scala 167:109] wire [3:0] _T_1456 = _T_1454 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_5 = _T_1456 & intpriority_reg_inv_5; // @[el2_pic_ctl.scala 175:129] - wire _T_1458 = extintsrc_req_gw_6 & intenable_reg_6; // @[el2_pic_ctl.scala 175:109] + wire [3:0] intpend_w_prior_en_5 = _T_1456 & intpriority_reg_inv_5; // @[el2_pic_ctl.scala 167:129] + wire _T_1458 = extintsrc_req_gw_6 & intenable_reg_6; // @[el2_pic_ctl.scala 167:109] wire [3:0] _T_1460 = _T_1458 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_6 = _T_1460 & intpriority_reg_inv_6; // @[el2_pic_ctl.scala 175:129] - wire _T_1462 = extintsrc_req_gw_7 & intenable_reg_7; // @[el2_pic_ctl.scala 175:109] + wire [3:0] intpend_w_prior_en_6 = _T_1460 & intpriority_reg_inv_6; // @[el2_pic_ctl.scala 167:129] + wire _T_1462 = extintsrc_req_gw_7 & intenable_reg_7; // @[el2_pic_ctl.scala 167:109] wire [3:0] _T_1464 = _T_1462 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_7 = _T_1464 & intpriority_reg_inv_7; // @[el2_pic_ctl.scala 175:129] - wire _T_1466 = extintsrc_req_gw_8 & intenable_reg_8; // @[el2_pic_ctl.scala 175:109] + wire [3:0] intpend_w_prior_en_7 = _T_1464 & intpriority_reg_inv_7; // @[el2_pic_ctl.scala 167:129] + wire _T_1466 = extintsrc_req_gw_8 & intenable_reg_8; // @[el2_pic_ctl.scala 167:109] wire [3:0] _T_1468 = _T_1466 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_8 = _T_1468 & intpriority_reg_inv_8; // @[el2_pic_ctl.scala 175:129] - wire _T_1470 = extintsrc_req_gw_9 & intenable_reg_9; // @[el2_pic_ctl.scala 175:109] + wire [3:0] intpend_w_prior_en_8 = _T_1468 & intpriority_reg_inv_8; // @[el2_pic_ctl.scala 167:129] + wire _T_1470 = extintsrc_req_gw_9 & intenable_reg_9; // @[el2_pic_ctl.scala 167:109] wire [3:0] _T_1472 = _T_1470 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_9 = _T_1472 & intpriority_reg_inv_9; // @[el2_pic_ctl.scala 175:129] - wire _T_1474 = extintsrc_req_gw_10 & intenable_reg_10; // @[el2_pic_ctl.scala 175:109] + wire [3:0] intpend_w_prior_en_9 = _T_1472 & intpriority_reg_inv_9; // @[el2_pic_ctl.scala 167:129] + wire _T_1474 = extintsrc_req_gw_10 & intenable_reg_10; // @[el2_pic_ctl.scala 167:109] wire [3:0] _T_1476 = _T_1474 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_10 = _T_1476 & intpriority_reg_inv_10; // @[el2_pic_ctl.scala 175:129] - wire _T_1478 = extintsrc_req_gw_11 & intenable_reg_11; // @[el2_pic_ctl.scala 175:109] + wire [3:0] intpend_w_prior_en_10 = _T_1476 & intpriority_reg_inv_10; // @[el2_pic_ctl.scala 167:129] + wire _T_1478 = extintsrc_req_gw_11 & intenable_reg_11; // @[el2_pic_ctl.scala 167:109] wire [3:0] _T_1480 = _T_1478 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_11 = _T_1480 & intpriority_reg_inv_11; // @[el2_pic_ctl.scala 175:129] - wire _T_1482 = extintsrc_req_gw_12 & intenable_reg_12; // @[el2_pic_ctl.scala 175:109] + wire [3:0] intpend_w_prior_en_11 = _T_1480 & intpriority_reg_inv_11; // @[el2_pic_ctl.scala 167:129] + wire _T_1482 = extintsrc_req_gw_12 & intenable_reg_12; // @[el2_pic_ctl.scala 167:109] wire [3:0] _T_1484 = _T_1482 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_12 = _T_1484 & intpriority_reg_inv_12; // @[el2_pic_ctl.scala 175:129] - wire _T_1486 = extintsrc_req_gw_13 & intenable_reg_13; // @[el2_pic_ctl.scala 175:109] + wire [3:0] intpend_w_prior_en_12 = _T_1484 & intpriority_reg_inv_12; // @[el2_pic_ctl.scala 167:129] + wire _T_1486 = extintsrc_req_gw_13 & intenable_reg_13; // @[el2_pic_ctl.scala 167:109] wire [3:0] _T_1488 = _T_1486 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_13 = _T_1488 & intpriority_reg_inv_13; // @[el2_pic_ctl.scala 175:129] - wire _T_1490 = extintsrc_req_gw_14 & intenable_reg_14; // @[el2_pic_ctl.scala 175:109] + wire [3:0] intpend_w_prior_en_13 = _T_1488 & intpriority_reg_inv_13; // @[el2_pic_ctl.scala 167:129] + wire _T_1490 = extintsrc_req_gw_14 & intenable_reg_14; // @[el2_pic_ctl.scala 167:109] wire [3:0] _T_1492 = _T_1490 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_14 = _T_1492 & intpriority_reg_inv_14; // @[el2_pic_ctl.scala 175:129] - wire _T_1494 = extintsrc_req_gw_15 & intenable_reg_15; // @[el2_pic_ctl.scala 175:109] + wire [3:0] intpend_w_prior_en_14 = _T_1492 & intpriority_reg_inv_14; // @[el2_pic_ctl.scala 167:129] + wire _T_1494 = extintsrc_req_gw_15 & intenable_reg_15; // @[el2_pic_ctl.scala 167:109] wire [3:0] _T_1496 = _T_1494 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_15 = _T_1496 & intpriority_reg_inv_15; // @[el2_pic_ctl.scala 175:129] - wire _T_1498 = extintsrc_req_gw_16 & intenable_reg_16; // @[el2_pic_ctl.scala 175:109] + wire [3:0] intpend_w_prior_en_15 = _T_1496 & intpriority_reg_inv_15; // @[el2_pic_ctl.scala 167:129] + wire _T_1498 = extintsrc_req_gw_16 & intenable_reg_16; // @[el2_pic_ctl.scala 167:109] wire [3:0] _T_1500 = _T_1498 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_16 = _T_1500 & intpriority_reg_inv_16; // @[el2_pic_ctl.scala 175:129] - wire _T_1502 = extintsrc_req_gw_17 & intenable_reg_17; // @[el2_pic_ctl.scala 175:109] + wire [3:0] intpend_w_prior_en_16 = _T_1500 & intpriority_reg_inv_16; // @[el2_pic_ctl.scala 167:129] + wire _T_1502 = extintsrc_req_gw_17 & intenable_reg_17; // @[el2_pic_ctl.scala 167:109] wire [3:0] _T_1504 = _T_1502 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_17 = _T_1504 & intpriority_reg_inv_17; // @[el2_pic_ctl.scala 175:129] - wire _T_1506 = extintsrc_req_gw_18 & intenable_reg_18; // @[el2_pic_ctl.scala 175:109] + wire [3:0] intpend_w_prior_en_17 = _T_1504 & intpriority_reg_inv_17; // @[el2_pic_ctl.scala 167:129] + wire _T_1506 = extintsrc_req_gw_18 & intenable_reg_18; // @[el2_pic_ctl.scala 167:109] wire [3:0] _T_1508 = _T_1506 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_18 = _T_1508 & intpriority_reg_inv_18; // @[el2_pic_ctl.scala 175:129] - wire _T_1510 = extintsrc_req_gw_19 & intenable_reg_19; // @[el2_pic_ctl.scala 175:109] + wire [3:0] intpend_w_prior_en_18 = _T_1508 & intpriority_reg_inv_18; // @[el2_pic_ctl.scala 167:129] + wire _T_1510 = extintsrc_req_gw_19 & intenable_reg_19; // @[el2_pic_ctl.scala 167:109] wire [3:0] _T_1512 = _T_1510 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_19 = _T_1512 & intpriority_reg_inv_19; // @[el2_pic_ctl.scala 175:129] - wire _T_1514 = extintsrc_req_gw_20 & intenable_reg_20; // @[el2_pic_ctl.scala 175:109] + wire [3:0] intpend_w_prior_en_19 = _T_1512 & intpriority_reg_inv_19; // @[el2_pic_ctl.scala 167:129] + wire _T_1514 = extintsrc_req_gw_20 & intenable_reg_20; // @[el2_pic_ctl.scala 167:109] wire [3:0] _T_1516 = _T_1514 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_20 = _T_1516 & intpriority_reg_inv_20; // @[el2_pic_ctl.scala 175:129] - wire _T_1518 = extintsrc_req_gw_21 & intenable_reg_21; // @[el2_pic_ctl.scala 175:109] + wire [3:0] intpend_w_prior_en_20 = _T_1516 & intpriority_reg_inv_20; // @[el2_pic_ctl.scala 167:129] + wire _T_1518 = extintsrc_req_gw_21 & intenable_reg_21; // @[el2_pic_ctl.scala 167:109] wire [3:0] _T_1520 = _T_1518 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_21 = _T_1520 & intpriority_reg_inv_21; // @[el2_pic_ctl.scala 175:129] - wire _T_1522 = extintsrc_req_gw_22 & intenable_reg_22; // @[el2_pic_ctl.scala 175:109] + wire [3:0] intpend_w_prior_en_21 = _T_1520 & intpriority_reg_inv_21; // @[el2_pic_ctl.scala 167:129] + wire _T_1522 = extintsrc_req_gw_22 & intenable_reg_22; // @[el2_pic_ctl.scala 167:109] wire [3:0] _T_1524 = _T_1522 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_22 = _T_1524 & intpriority_reg_inv_22; // @[el2_pic_ctl.scala 175:129] - wire _T_1526 = extintsrc_req_gw_23 & intenable_reg_23; // @[el2_pic_ctl.scala 175:109] + wire [3:0] intpend_w_prior_en_22 = _T_1524 & intpriority_reg_inv_22; // @[el2_pic_ctl.scala 167:129] + wire _T_1526 = extintsrc_req_gw_23 & intenable_reg_23; // @[el2_pic_ctl.scala 167:109] wire [3:0] _T_1528 = _T_1526 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_23 = _T_1528 & intpriority_reg_inv_23; // @[el2_pic_ctl.scala 175:129] - wire _T_1530 = extintsrc_req_gw_24 & intenable_reg_24; // @[el2_pic_ctl.scala 175:109] + wire [3:0] intpend_w_prior_en_23 = _T_1528 & intpriority_reg_inv_23; // @[el2_pic_ctl.scala 167:129] + wire _T_1530 = extintsrc_req_gw_24 & intenable_reg_24; // @[el2_pic_ctl.scala 167:109] wire [3:0] _T_1532 = _T_1530 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_24 = _T_1532 & intpriority_reg_inv_24; // @[el2_pic_ctl.scala 175:129] - wire _T_1534 = extintsrc_req_gw_25 & intenable_reg_25; // @[el2_pic_ctl.scala 175:109] + wire [3:0] intpend_w_prior_en_24 = _T_1532 & intpriority_reg_inv_24; // @[el2_pic_ctl.scala 167:129] + wire _T_1534 = extintsrc_req_gw_25 & intenable_reg_25; // @[el2_pic_ctl.scala 167:109] wire [3:0] _T_1536 = _T_1534 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_25 = _T_1536 & intpriority_reg_inv_25; // @[el2_pic_ctl.scala 175:129] - wire _T_1538 = extintsrc_req_gw_26 & intenable_reg_26; // @[el2_pic_ctl.scala 175:109] + wire [3:0] intpend_w_prior_en_25 = _T_1536 & intpriority_reg_inv_25; // @[el2_pic_ctl.scala 167:129] + wire _T_1538 = extintsrc_req_gw_26 & intenable_reg_26; // @[el2_pic_ctl.scala 167:109] wire [3:0] _T_1540 = _T_1538 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_26 = _T_1540 & intpriority_reg_inv_26; // @[el2_pic_ctl.scala 175:129] - wire _T_1542 = extintsrc_req_gw_27 & intenable_reg_27; // @[el2_pic_ctl.scala 175:109] + wire [3:0] intpend_w_prior_en_26 = _T_1540 & intpriority_reg_inv_26; // @[el2_pic_ctl.scala 167:129] + wire _T_1542 = extintsrc_req_gw_27 & intenable_reg_27; // @[el2_pic_ctl.scala 167:109] wire [3:0] _T_1544 = _T_1542 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_27 = _T_1544 & intpriority_reg_inv_27; // @[el2_pic_ctl.scala 175:129] - wire _T_1546 = extintsrc_req_gw_28 & intenable_reg_28; // @[el2_pic_ctl.scala 175:109] + wire [3:0] intpend_w_prior_en_27 = _T_1544 & intpriority_reg_inv_27; // @[el2_pic_ctl.scala 167:129] + wire _T_1546 = extintsrc_req_gw_28 & intenable_reg_28; // @[el2_pic_ctl.scala 167:109] wire [3:0] _T_1548 = _T_1546 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_28 = _T_1548 & intpriority_reg_inv_28; // @[el2_pic_ctl.scala 175:129] - wire _T_1550 = extintsrc_req_gw_29 & intenable_reg_29; // @[el2_pic_ctl.scala 175:109] + wire [3:0] intpend_w_prior_en_28 = _T_1548 & intpriority_reg_inv_28; // @[el2_pic_ctl.scala 167:129] + wire _T_1550 = extintsrc_req_gw_29 & intenable_reg_29; // @[el2_pic_ctl.scala 167:109] wire [3:0] _T_1552 = _T_1550 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_29 = _T_1552 & intpriority_reg_inv_29; // @[el2_pic_ctl.scala 175:129] - wire _T_1554 = extintsrc_req_gw_30 & intenable_reg_30; // @[el2_pic_ctl.scala 175:109] + wire [3:0] intpend_w_prior_en_29 = _T_1552 & intpriority_reg_inv_29; // @[el2_pic_ctl.scala 167:129] + wire _T_1554 = extintsrc_req_gw_30 & intenable_reg_30; // @[el2_pic_ctl.scala 167:109] wire [3:0] _T_1556 = _T_1554 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_30 = _T_1556 & intpriority_reg_inv_30; // @[el2_pic_ctl.scala 175:129] - wire _T_1558 = extintsrc_req_gw_31 & intenable_reg_31; // @[el2_pic_ctl.scala 175:109] + wire [3:0] intpend_w_prior_en_30 = _T_1556 & intpriority_reg_inv_30; // @[el2_pic_ctl.scala 167:129] + wire _T_1558 = extintsrc_req_gw_31 & intenable_reg_31; // @[el2_pic_ctl.scala 167:109] wire [3:0] _T_1560 = _T_1558 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_31 = _T_1560 & intpriority_reg_inv_31; // @[el2_pic_ctl.scala 175:129] + wire [3:0] intpend_w_prior_en_31 = _T_1560 & intpriority_reg_inv_31; // @[el2_pic_ctl.scala 167:129] wire [7:0] _T_1564 = 8'hff; // @[Bitwise.scala 72:12] - wire [3:0] level_intpend_w_prior_en_0_0 = 4'h0; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] - wire [3:0] _T_1441 = intpend_w_prior_en_1; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] - wire [3:0] level_intpend_w_prior_en_0_1 = intpend_w_prior_en_1; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] - wire _T_1566 = intpriority_reg_0 < _T_1441; // @[el2_pic_ctl.scala 38:29] - wire [7:0] intpend_id_1 = 8'h1; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] - wire [7:0] level_intpend_id_0_1 = 8'h1; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] - wire [7:0] intpend_id_0 = 8'h0; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] - wire [7:0] level_intpend_id_0_0 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] - wire [7:0] out_id = _T_1566 ? intpend_id_1 : intpend_id_0; // @[el2_pic_ctl.scala 38:18] - wire [3:0] out_priority = _T_1566 ? _T_1441 : intpriority_reg_0; // @[el2_pic_ctl.scala 39:24] - wire [3:0] _T_1445 = intpend_w_prior_en_2; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] - wire [3:0] level_intpend_w_prior_en_0_2 = intpend_w_prior_en_2; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] - wire [3:0] _T_1449 = intpend_w_prior_en_3; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] - wire [3:0] level_intpend_w_prior_en_0_3 = intpend_w_prior_en_3; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] - wire _T_1570 = _T_1445 < _T_1449; // @[el2_pic_ctl.scala 38:29] - wire [7:0] intpend_id_3 = 8'h3; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] - wire [7:0] level_intpend_id_0_3 = 8'h3; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] - wire [7:0] intpend_id_2 = 8'h2; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] - wire [7:0] level_intpend_id_0_2 = 8'h2; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] - wire [7:0] out_id_1 = _T_1570 ? intpend_id_3 : intpend_id_2; // @[el2_pic_ctl.scala 38:18] - wire [3:0] out_priority_1 = _T_1570 ? _T_1449 : _T_1445; // @[el2_pic_ctl.scala 39:24] - wire [3:0] _T_1453 = intpend_w_prior_en_4; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] - wire [3:0] level_intpend_w_prior_en_0_4 = intpend_w_prior_en_4; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] - wire [3:0] _T_1457 = intpend_w_prior_en_5; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] - wire [3:0] level_intpend_w_prior_en_0_5 = intpend_w_prior_en_5; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] - wire _T_1574 = _T_1453 < _T_1457; // @[el2_pic_ctl.scala 38:29] - wire [7:0] intpend_id_5 = 8'h5; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] - wire [7:0] level_intpend_id_0_5 = 8'h5; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] - wire [7:0] intpend_id_4 = 8'h4; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] - wire [7:0] level_intpend_id_0_4 = 8'h4; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] - wire [7:0] out_id_2 = _T_1574 ? intpend_id_5 : intpend_id_4; // @[el2_pic_ctl.scala 38:18] - wire [3:0] out_priority_2 = _T_1574 ? _T_1457 : _T_1453; // @[el2_pic_ctl.scala 39:24] - wire [3:0] _T_1461 = intpend_w_prior_en_6; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] - wire [3:0] level_intpend_w_prior_en_0_6 = intpend_w_prior_en_6; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] - wire [3:0] _T_1465 = intpend_w_prior_en_7; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] - wire [3:0] level_intpend_w_prior_en_0_7 = intpend_w_prior_en_7; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] - wire _T_1578 = _T_1461 < _T_1465; // @[el2_pic_ctl.scala 38:29] - wire [7:0] intpend_id_7 = 8'h7; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] - wire [7:0] level_intpend_id_0_7 = 8'h7; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] - wire [7:0] intpend_id_6 = 8'h6; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] - wire [7:0] level_intpend_id_0_6 = 8'h6; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] - wire [7:0] out_id_3 = _T_1578 ? intpend_id_7 : intpend_id_6; // @[el2_pic_ctl.scala 38:18] - wire [3:0] out_priority_3 = _T_1578 ? _T_1465 : _T_1461; // @[el2_pic_ctl.scala 39:24] - wire [3:0] _T_1469 = intpend_w_prior_en_8; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] - wire [3:0] level_intpend_w_prior_en_0_8 = intpend_w_prior_en_8; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] - wire [3:0] _T_1473 = intpend_w_prior_en_9; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] - wire [3:0] level_intpend_w_prior_en_0_9 = intpend_w_prior_en_9; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] - wire _T_1582 = _T_1469 < _T_1473; // @[el2_pic_ctl.scala 38:29] - wire [7:0] intpend_id_9 = 8'h9; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] - wire [7:0] level_intpend_id_0_9 = 8'h9; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] - wire [7:0] intpend_id_8 = 8'h8; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] - wire [7:0] level_intpend_id_0_8 = 8'h8; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] - wire [7:0] out_id_4 = _T_1582 ? intpend_id_9 : intpend_id_8; // @[el2_pic_ctl.scala 38:18] - wire [3:0] out_priority_4 = _T_1582 ? _T_1473 : _T_1469; // @[el2_pic_ctl.scala 39:24] - wire [3:0] _T_1477 = intpend_w_prior_en_10; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] - wire [3:0] level_intpend_w_prior_en_0_10 = intpend_w_prior_en_10; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] - wire [3:0] _T_1481 = intpend_w_prior_en_11; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] - wire [3:0] level_intpend_w_prior_en_0_11 = intpend_w_prior_en_11; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] - wire _T_1586 = _T_1477 < _T_1481; // @[el2_pic_ctl.scala 38:29] - wire [7:0] intpend_id_11 = 8'hb; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] - wire [7:0] level_intpend_id_0_11 = 8'hb; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] - wire [7:0] intpend_id_10 = 8'ha; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] - wire [7:0] level_intpend_id_0_10 = 8'ha; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] - wire [7:0] out_id_5 = _T_1586 ? intpend_id_11 : intpend_id_10; // @[el2_pic_ctl.scala 38:18] - wire [3:0] out_priority_5 = _T_1586 ? _T_1481 : _T_1477; // @[el2_pic_ctl.scala 39:24] - wire [3:0] _T_1485 = intpend_w_prior_en_12; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] - wire [3:0] level_intpend_w_prior_en_0_12 = intpend_w_prior_en_12; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] - wire [3:0] _T_1489 = intpend_w_prior_en_13; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] - wire [3:0] level_intpend_w_prior_en_0_13 = intpend_w_prior_en_13; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] - wire _T_1590 = _T_1485 < _T_1489; // @[el2_pic_ctl.scala 38:29] - wire [7:0] intpend_id_13 = 8'hd; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] - wire [7:0] level_intpend_id_0_13 = 8'hd; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] - wire [7:0] intpend_id_12 = 8'hc; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] - wire [7:0] level_intpend_id_0_12 = 8'hc; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] - wire [7:0] out_id_6 = _T_1590 ? intpend_id_13 : intpend_id_12; // @[el2_pic_ctl.scala 38:18] - wire [3:0] out_priority_6 = _T_1590 ? _T_1489 : _T_1485; // @[el2_pic_ctl.scala 39:24] - wire [3:0] _T_1493 = intpend_w_prior_en_14; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] - wire [3:0] level_intpend_w_prior_en_0_14 = intpend_w_prior_en_14; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] - wire [3:0] _T_1497 = intpend_w_prior_en_15; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] - wire [3:0] level_intpend_w_prior_en_0_15 = intpend_w_prior_en_15; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] - wire _T_1594 = _T_1493 < _T_1497; // @[el2_pic_ctl.scala 38:29] - wire [7:0] intpend_id_15 = 8'hf; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] - wire [7:0] level_intpend_id_0_15 = 8'hf; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] - wire [7:0] intpend_id_14 = 8'he; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] - wire [7:0] level_intpend_id_0_14 = 8'he; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] - wire [7:0] out_id_7 = _T_1594 ? intpend_id_15 : intpend_id_14; // @[el2_pic_ctl.scala 38:18] - wire [3:0] out_priority_7 = _T_1594 ? _T_1497 : _T_1493; // @[el2_pic_ctl.scala 39:24] - wire [3:0] _T_1501 = intpend_w_prior_en_16; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] - wire [3:0] level_intpend_w_prior_en_0_16 = intpend_w_prior_en_16; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] - wire [3:0] _T_1505 = intpend_w_prior_en_17; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] - wire [3:0] level_intpend_w_prior_en_0_17 = intpend_w_prior_en_17; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] - wire _T_1598 = _T_1501 < _T_1505; // @[el2_pic_ctl.scala 38:29] - wire [7:0] intpend_id_17 = 8'h11; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] - wire [7:0] level_intpend_id_0_17 = 8'h11; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] - wire [7:0] intpend_id_16 = 8'h10; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] - wire [7:0] level_intpend_id_0_16 = 8'h10; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] - wire [7:0] out_id_8 = _T_1598 ? intpend_id_17 : intpend_id_16; // @[el2_pic_ctl.scala 38:18] - wire [3:0] out_priority_8 = _T_1598 ? _T_1505 : _T_1501; // @[el2_pic_ctl.scala 39:24] - wire [3:0] _T_1509 = intpend_w_prior_en_18; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] - wire [3:0] level_intpend_w_prior_en_0_18 = intpend_w_prior_en_18; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] - wire [3:0] _T_1513 = intpend_w_prior_en_19; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] - wire [3:0] level_intpend_w_prior_en_0_19 = intpend_w_prior_en_19; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] - wire _T_1602 = _T_1509 < _T_1513; // @[el2_pic_ctl.scala 38:29] - wire [7:0] intpend_id_19 = 8'h13; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] - wire [7:0] level_intpend_id_0_19 = 8'h13; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] - wire [7:0] intpend_id_18 = 8'h12; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] - wire [7:0] level_intpend_id_0_18 = 8'h12; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] - wire [7:0] out_id_9 = _T_1602 ? intpend_id_19 : intpend_id_18; // @[el2_pic_ctl.scala 38:18] - wire [3:0] out_priority_9 = _T_1602 ? _T_1513 : _T_1509; // @[el2_pic_ctl.scala 39:24] - wire [3:0] _T_1517 = intpend_w_prior_en_20; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] - wire [3:0] level_intpend_w_prior_en_0_20 = intpend_w_prior_en_20; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] - wire [3:0] _T_1521 = intpend_w_prior_en_21; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] - wire [3:0] level_intpend_w_prior_en_0_21 = intpend_w_prior_en_21; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] - wire _T_1606 = _T_1517 < _T_1521; // @[el2_pic_ctl.scala 38:29] - wire [7:0] intpend_id_21 = 8'h15; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] - wire [7:0] level_intpend_id_0_21 = 8'h15; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] - wire [7:0] intpend_id_20 = 8'h14; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] - wire [7:0] level_intpend_id_0_20 = 8'h14; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] - wire [7:0] out_id_10 = _T_1606 ? intpend_id_21 : intpend_id_20; // @[el2_pic_ctl.scala 38:18] - wire [3:0] out_priority_10 = _T_1606 ? _T_1521 : _T_1517; // @[el2_pic_ctl.scala 39:24] - wire [3:0] _T_1525 = intpend_w_prior_en_22; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] - wire [3:0] level_intpend_w_prior_en_0_22 = intpend_w_prior_en_22; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] - wire [3:0] _T_1529 = intpend_w_prior_en_23; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] - wire [3:0] level_intpend_w_prior_en_0_23 = intpend_w_prior_en_23; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] - wire _T_1610 = _T_1525 < _T_1529; // @[el2_pic_ctl.scala 38:29] - wire [7:0] intpend_id_23 = 8'h17; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] - wire [7:0] level_intpend_id_0_23 = 8'h17; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] - wire [7:0] intpend_id_22 = 8'h16; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] - wire [7:0] level_intpend_id_0_22 = 8'h16; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] - wire [7:0] out_id_11 = _T_1610 ? intpend_id_23 : intpend_id_22; // @[el2_pic_ctl.scala 38:18] - wire [3:0] out_priority_11 = _T_1610 ? _T_1529 : _T_1525; // @[el2_pic_ctl.scala 39:24] - wire [3:0] _T_1533 = intpend_w_prior_en_24; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] - wire [3:0] level_intpend_w_prior_en_0_24 = intpend_w_prior_en_24; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] - wire [3:0] _T_1537 = intpend_w_prior_en_25; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] - wire [3:0] level_intpend_w_prior_en_0_25 = intpend_w_prior_en_25; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] - wire _T_1614 = _T_1533 < _T_1537; // @[el2_pic_ctl.scala 38:29] - wire [7:0] intpend_id_25 = 8'h19; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] - wire [7:0] level_intpend_id_0_25 = 8'h19; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] - wire [7:0] intpend_id_24 = 8'h18; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] - wire [7:0] level_intpend_id_0_24 = 8'h18; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] - wire [7:0] out_id_12 = _T_1614 ? intpend_id_25 : intpend_id_24; // @[el2_pic_ctl.scala 38:18] - wire [3:0] out_priority_12 = _T_1614 ? _T_1537 : _T_1533; // @[el2_pic_ctl.scala 39:24] - wire [3:0] _T_1541 = intpend_w_prior_en_26; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] - wire [3:0] level_intpend_w_prior_en_0_26 = intpend_w_prior_en_26; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] - wire [3:0] _T_1545 = intpend_w_prior_en_27; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] - wire [3:0] level_intpend_w_prior_en_0_27 = intpend_w_prior_en_27; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] - wire _T_1618 = _T_1541 < _T_1545; // @[el2_pic_ctl.scala 38:29] - wire [7:0] intpend_id_27 = 8'h1b; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] - wire [7:0] level_intpend_id_0_27 = 8'h1b; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] - wire [7:0] intpend_id_26 = 8'h1a; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] - wire [7:0] level_intpend_id_0_26 = 8'h1a; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] - wire [7:0] out_id_13 = _T_1618 ? intpend_id_27 : intpend_id_26; // @[el2_pic_ctl.scala 38:18] - wire [3:0] out_priority_13 = _T_1618 ? _T_1545 : _T_1541; // @[el2_pic_ctl.scala 39:24] - wire [3:0] _T_1549 = intpend_w_prior_en_28; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] - wire [3:0] level_intpend_w_prior_en_0_28 = intpend_w_prior_en_28; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] - wire [3:0] _T_1553 = intpend_w_prior_en_29; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] - wire [3:0] level_intpend_w_prior_en_0_29 = intpend_w_prior_en_29; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] - wire _T_1622 = _T_1549 < _T_1553; // @[el2_pic_ctl.scala 38:29] - wire [7:0] intpend_id_29 = 8'h1d; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] - wire [7:0] level_intpend_id_0_29 = 8'h1d; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] - wire [7:0] intpend_id_28 = 8'h1c; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] - wire [7:0] level_intpend_id_0_28 = 8'h1c; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] - wire [7:0] out_id_14 = _T_1622 ? intpend_id_29 : intpend_id_28; // @[el2_pic_ctl.scala 38:18] - wire [3:0] out_priority_14 = _T_1622 ? _T_1553 : _T_1549; // @[el2_pic_ctl.scala 39:24] - wire [3:0] _T_1557 = intpend_w_prior_en_30; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] - wire [3:0] level_intpend_w_prior_en_0_30 = intpend_w_prior_en_30; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] - wire [3:0] _T_1561 = intpend_w_prior_en_31; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] - wire [3:0] level_intpend_w_prior_en_0_31 = intpend_w_prior_en_31; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] - wire _T_1626 = _T_1557 < _T_1561; // @[el2_pic_ctl.scala 38:29] - wire [7:0] intpend_id_31 = 8'h1f; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] - wire [7:0] level_intpend_id_0_31 = 8'h1f; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] - wire [7:0] intpend_id_30 = 8'h1e; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] - wire [7:0] level_intpend_id_0_30 = 8'h1e; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] - wire [7:0] out_id_15 = _T_1626 ? intpend_id_31 : intpend_id_30; // @[el2_pic_ctl.scala 38:18] - wire [3:0] out_priority_15 = _T_1626 ? _T_1561 : _T_1557; // @[el2_pic_ctl.scala 39:24] - wire [3:0] level_intpend_w_prior_en_0_32 = 4'h0; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] - wire [3:0] level_intpend_w_prior_en_0_33 = 4'h0; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] - wire _T_1630 = intpriority_reg_0 < intpriority_reg_0; // @[el2_pic_ctl.scala 38:29] - wire [7:0] level_intpend_id_0_33 = 8'hff; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] - wire [7:0] level_intpend_id_0_32 = 8'hff; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] - wire [7:0] out_id_16 = _T_1630 ? _T_1564 : _T_1564; // @[el2_pic_ctl.scala 38:18] - wire _T_1634 = out_priority < out_priority_1; // @[el2_pic_ctl.scala 38:29] - wire [7:0] _T_1571 = out_id_1; // @[el2_pic_ctl.scala 38:12] - wire [7:0] level_intpend_id_1_1 = out_id_1; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] - wire [7:0] _T_1567 = out_id; // @[el2_pic_ctl.scala 38:12] - wire [7:0] level_intpend_id_1_0 = out_id; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] - wire [7:0] out_id_17 = _T_1634 ? _T_1571 : _T_1567; // @[el2_pic_ctl.scala 38:18] - wire [3:0] out_priority_17 = _T_1634 ? out_priority_1 : out_priority; // @[el2_pic_ctl.scala 39:24] - wire _T_1638 = out_priority_2 < out_priority_3; // @[el2_pic_ctl.scala 38:29] - wire [7:0] _T_1579 = out_id_3; // @[el2_pic_ctl.scala 38:12] - wire [7:0] level_intpend_id_1_3 = out_id_3; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] - wire [7:0] _T_1575 = out_id_2; // @[el2_pic_ctl.scala 38:12] - wire [7:0] level_intpend_id_1_2 = out_id_2; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] - wire [7:0] out_id_18 = _T_1638 ? _T_1579 : _T_1575; // @[el2_pic_ctl.scala 38:18] - wire [3:0] out_priority_18 = _T_1638 ? out_priority_3 : out_priority_2; // @[el2_pic_ctl.scala 39:24] - wire _T_1642 = out_priority_4 < out_priority_5; // @[el2_pic_ctl.scala 38:29] - wire [7:0] _T_1587 = out_id_5; // @[el2_pic_ctl.scala 38:12] - wire [7:0] level_intpend_id_1_5 = out_id_5; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] - wire [7:0] _T_1583 = out_id_4; // @[el2_pic_ctl.scala 38:12] - wire [7:0] level_intpend_id_1_4 = out_id_4; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] - wire [7:0] out_id_19 = _T_1642 ? _T_1587 : _T_1583; // @[el2_pic_ctl.scala 38:18] - wire [3:0] out_priority_19 = _T_1642 ? out_priority_5 : out_priority_4; // @[el2_pic_ctl.scala 39:24] - wire _T_1646 = out_priority_6 < out_priority_7; // @[el2_pic_ctl.scala 38:29] - wire [7:0] _T_1595 = out_id_7; // @[el2_pic_ctl.scala 38:12] - wire [7:0] level_intpend_id_1_7 = out_id_7; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] - wire [7:0] _T_1591 = out_id_6; // @[el2_pic_ctl.scala 38:12] - wire [7:0] level_intpend_id_1_6 = out_id_6; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] - wire [7:0] out_id_20 = _T_1646 ? _T_1595 : _T_1591; // @[el2_pic_ctl.scala 38:18] - wire [3:0] out_priority_20 = _T_1646 ? out_priority_7 : out_priority_6; // @[el2_pic_ctl.scala 39:24] - wire _T_1650 = out_priority_8 < out_priority_9; // @[el2_pic_ctl.scala 38:29] - wire [7:0] _T_1603 = out_id_9; // @[el2_pic_ctl.scala 38:12] - wire [7:0] level_intpend_id_1_9 = out_id_9; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] - wire [7:0] _T_1599 = out_id_8; // @[el2_pic_ctl.scala 38:12] - wire [7:0] level_intpend_id_1_8 = out_id_8; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] - wire [7:0] out_id_21 = _T_1650 ? _T_1603 : _T_1599; // @[el2_pic_ctl.scala 38:18] - wire [3:0] out_priority_21 = _T_1650 ? out_priority_9 : out_priority_8; // @[el2_pic_ctl.scala 39:24] - wire _T_1654 = out_priority_10 < out_priority_11; // @[el2_pic_ctl.scala 38:29] - wire [7:0] _T_1611 = out_id_11; // @[el2_pic_ctl.scala 38:12] - wire [7:0] level_intpend_id_1_11 = out_id_11; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] - wire [7:0] _T_1607 = out_id_10; // @[el2_pic_ctl.scala 38:12] - wire [7:0] level_intpend_id_1_10 = out_id_10; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] - wire [7:0] out_id_22 = _T_1654 ? _T_1611 : _T_1607; // @[el2_pic_ctl.scala 38:18] - wire [3:0] out_priority_22 = _T_1654 ? out_priority_11 : out_priority_10; // @[el2_pic_ctl.scala 39:24] - wire _T_1658 = out_priority_12 < out_priority_13; // @[el2_pic_ctl.scala 38:29] - wire [7:0] _T_1619 = out_id_13; // @[el2_pic_ctl.scala 38:12] - wire [7:0] level_intpend_id_1_13 = out_id_13; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] - wire [7:0] _T_1615 = out_id_12; // @[el2_pic_ctl.scala 38:12] - wire [7:0] level_intpend_id_1_12 = out_id_12; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] - wire [7:0] out_id_23 = _T_1658 ? _T_1619 : _T_1615; // @[el2_pic_ctl.scala 38:18] - wire [3:0] out_priority_23 = _T_1658 ? out_priority_13 : out_priority_12; // @[el2_pic_ctl.scala 39:24] - wire _T_1662 = out_priority_14 < out_priority_15; // @[el2_pic_ctl.scala 38:29] - wire [7:0] _T_1627 = out_id_15; // @[el2_pic_ctl.scala 38:12] - wire [7:0] level_intpend_id_1_15 = out_id_15; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] - wire [7:0] _T_1623 = out_id_14; // @[el2_pic_ctl.scala 38:12] - wire [7:0] level_intpend_id_1_14 = out_id_14; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] - wire [7:0] out_id_24 = _T_1662 ? _T_1627 : _T_1623; // @[el2_pic_ctl.scala 38:18] - wire [3:0] out_priority_24 = _T_1662 ? out_priority_15 : out_priority_14; // @[el2_pic_ctl.scala 39:24] - wire [7:0] level_intpend_id_1_17 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 243:46] - wire [7:0] _T_1631 = out_id_16; // @[el2_pic_ctl.scala 38:12] - wire [7:0] level_intpend_id_1_16 = out_id_16; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] - wire [7:0] _T_1667 = _T_1631; // @[el2_pic_ctl.scala 38:18] - wire _T_1670 = out_priority_17 < out_priority_18; // @[el2_pic_ctl.scala 38:29] - wire [7:0] _T_1639 = out_id_18; // @[el2_pic_ctl.scala 38:12] - wire [7:0] level_intpend_id_2_1 = out_id_18; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] - wire [7:0] _T_1635 = out_id_17; // @[el2_pic_ctl.scala 38:12] - wire [7:0] level_intpend_id_2_0 = out_id_17; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] - wire [7:0] out_id_26 = _T_1670 ? _T_1639 : _T_1635; // @[el2_pic_ctl.scala 38:18] - wire [3:0] out_priority_26 = _T_1670 ? out_priority_18 : out_priority_17; // @[el2_pic_ctl.scala 39:24] - wire _T_1674 = out_priority_19 < out_priority_20; // @[el2_pic_ctl.scala 38:29] - wire [7:0] _T_1647 = out_id_20; // @[el2_pic_ctl.scala 38:12] - wire [7:0] level_intpend_id_2_3 = out_id_20; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] - wire [7:0] _T_1643 = out_id_19; // @[el2_pic_ctl.scala 38:12] - wire [7:0] level_intpend_id_2_2 = out_id_19; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] - wire [7:0] out_id_27 = _T_1674 ? _T_1647 : _T_1643; // @[el2_pic_ctl.scala 38:18] - wire [3:0] out_priority_27 = _T_1674 ? out_priority_20 : out_priority_19; // @[el2_pic_ctl.scala 39:24] - wire _T_1678 = out_priority_21 < out_priority_22; // @[el2_pic_ctl.scala 38:29] - wire [7:0] _T_1655 = out_id_22; // @[el2_pic_ctl.scala 38:12] - wire [7:0] level_intpend_id_2_5 = out_id_22; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] - wire [7:0] _T_1651 = out_id_21; // @[el2_pic_ctl.scala 38:12] - wire [7:0] level_intpend_id_2_4 = out_id_21; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] - wire [7:0] out_id_28 = _T_1678 ? _T_1655 : _T_1651; // @[el2_pic_ctl.scala 38:18] - wire [3:0] out_priority_28 = _T_1678 ? out_priority_22 : out_priority_21; // @[el2_pic_ctl.scala 39:24] - wire _T_1682 = out_priority_23 < out_priority_24; // @[el2_pic_ctl.scala 38:29] - wire [7:0] _T_1663 = out_id_24; // @[el2_pic_ctl.scala 38:12] - wire [7:0] level_intpend_id_2_7 = out_id_24; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] - wire [7:0] _T_1659 = out_id_23; // @[el2_pic_ctl.scala 38:12] - wire [7:0] level_intpend_id_2_6 = out_id_23; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] - wire [7:0] out_id_29 = _T_1682 ? _T_1663 : _T_1659; // @[el2_pic_ctl.scala 38:18] - wire [3:0] out_priority_29 = _T_1682 ? out_priority_24 : out_priority_23; // @[el2_pic_ctl.scala 39:24] - wire [7:0] level_intpend_id_2_9 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 243:46] - wire [7:0] level_intpend_id_2_8 = _T_1631; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] - wire [7:0] _T_1687 = _T_1667; // @[el2_pic_ctl.scala 38:18] - wire _T_1690 = out_priority_26 < out_priority_27; // @[el2_pic_ctl.scala 38:29] - wire [7:0] _T_1675 = out_id_27; // @[el2_pic_ctl.scala 38:12] - wire [7:0] level_intpend_id_3_1 = out_id_27; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] - wire [7:0] _T_1671 = out_id_26; // @[el2_pic_ctl.scala 38:12] - wire [7:0] level_intpend_id_3_0 = out_id_26; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] - wire [7:0] out_id_31 = _T_1690 ? _T_1675 : _T_1671; // @[el2_pic_ctl.scala 38:18] - wire [3:0] out_priority_31 = _T_1690 ? out_priority_27 : out_priority_26; // @[el2_pic_ctl.scala 39:24] - wire _T_1694 = out_priority_28 < out_priority_29; // @[el2_pic_ctl.scala 38:29] - wire [7:0] _T_1683 = out_id_29; // @[el2_pic_ctl.scala 38:12] - wire [7:0] level_intpend_id_3_3 = out_id_29; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] - wire [7:0] _T_1679 = out_id_28; // @[el2_pic_ctl.scala 38:12] - wire [7:0] level_intpend_id_3_2 = out_id_28; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] - wire [7:0] out_id_32 = _T_1694 ? _T_1683 : _T_1679; // @[el2_pic_ctl.scala 38:18] - wire [3:0] out_priority_32 = _T_1694 ? out_priority_29 : out_priority_28; // @[el2_pic_ctl.scala 39:24] - wire [7:0] level_intpend_id_3_5 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 243:46] - wire [7:0] level_intpend_id_3_4 = _T_1667; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] - wire [7:0] _T_1699 = _T_1687; // @[el2_pic_ctl.scala 38:18] - wire _T_1702 = out_priority_31 < out_priority_32; // @[el2_pic_ctl.scala 38:29] - wire [7:0] _T_1695 = out_id_32; // @[el2_pic_ctl.scala 38:12] - wire [7:0] level_intpend_id_4_1 = out_id_32; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] - wire [7:0] _T_1691 = out_id_31; // @[el2_pic_ctl.scala 38:12] - wire [7:0] level_intpend_id_4_0 = out_id_31; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] - wire [7:0] out_id_34 = _T_1702 ? _T_1695 : _T_1691; // @[el2_pic_ctl.scala 38:18] - wire [3:0] out_priority_34 = _T_1702 ? out_priority_32 : out_priority_31; // @[el2_pic_ctl.scala 39:24] - wire [7:0] level_intpend_id_4_3 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 243:46] - wire [7:0] level_intpend_id_4_2 = _T_1687; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] - wire config_reg_we = waddr_config_pic_match & picm_wren_ff; // @[el2_pic_ctl.scala 263:47] - wire config_reg_re = raddr_config_pic_match & picm_rden_ff; // @[el2_pic_ctl.scala 264:47] - wire [3:0] _T_1705 = out_priority_34; // @[el2_pic_ctl.scala 39:18] - wire [3:0] selected_int_priority = out_priority_34; // @[el2_pic_ctl.scala 251:29] - wire [3:0] _T_1713 = ~_T_1705; // @[el2_pic_ctl.scala 275:38] - wire [3:0] pl_in_q = config_reg ? _T_1713 : _T_1705; // @[el2_pic_ctl.scala 275:20] - reg [7:0] _T_1714; // @[el2_pic_ctl.scala 276:47] - reg [3:0] _T_1715; // @[el2_pic_ctl.scala 277:42] - wire [3:0] _T_1717 = ~io_meipt; // @[el2_pic_ctl.scala 278:40] - wire [3:0] meipt_inv = config_reg ? _T_1717 : io_meipt; // @[el2_pic_ctl.scala 278:22] - wire [3:0] _T_1719 = ~io_meicurpl; // @[el2_pic_ctl.scala 279:43] - wire [3:0] meicurpl_inv = config_reg ? _T_1719 : io_meicurpl; // @[el2_pic_ctl.scala 279:25] - wire _T_1720 = _T_1705 > meipt_inv; // @[el2_pic_ctl.scala 280:47] - wire _T_1721 = _T_1705 > meicurpl_inv; // @[el2_pic_ctl.scala 280:86] - reg _T_1722; // @[el2_pic_ctl.scala 281:50] - wire [3:0] maxint = config_reg ? 4'h0 : 4'hf; // @[el2_pic_ctl.scala 282:19] - reg _T_1724; // @[el2_pic_ctl.scala 284:48] - wire intpend_reg_read = addr_intpend_base_match & picm_rden_ff; // @[el2_pic_ctl.scala 290:60] - wire [9:0] _T_1734 = {extintsrc_req_gw_31,extintsrc_req_gw_30,extintsrc_req_gw_29,extintsrc_req_gw_28,extintsrc_req_gw_27,extintsrc_req_gw_26,extintsrc_req_gw_25,extintsrc_req_gw_24,extintsrc_req_gw_23,extintsrc_req_gw_22}; // @[Cat.scala 29:58] - wire [18:0] _T_1743 = {_T_1734,extintsrc_req_gw_21,extintsrc_req_gw_20,extintsrc_req_gw_19,extintsrc_req_gw_18,extintsrc_req_gw_17,extintsrc_req_gw_16,extintsrc_req_gw_15,extintsrc_req_gw_14,extintsrc_req_gw_13}; // @[Cat.scala 29:58] - wire [27:0] _T_1752 = {_T_1743,extintsrc_req_gw_12,extintsrc_req_gw_11,extintsrc_req_gw_10,extintsrc_req_gw_9,extintsrc_req_gw_8,extintsrc_req_gw_7,extintsrc_req_gw_6,extintsrc_req_gw_5,extintsrc_req_gw_4}; // @[Cat.scala 29:58] - wire [63:0] intpend_reg_extended = {32'h0,_T_1752,extintsrc_req_gw_3,extintsrc_req_gw_2,extintsrc_req_gw_1,1'h0}; // @[Cat.scala 29:58] - wire [3:0] _GEN_220 = {{3'd0}, intpend_reg_read}; // @[el2_pic_ctl.scala 298:83] - wire [3:0] _T_1759 = _GEN_220 & picm_raddr_ff[5:2]; // @[el2_pic_ctl.scala 298:83] - wire _T_1760 = _T_1759 == 4'h0; // @[el2_pic_ctl.scala 298:105] - wire [31:0] _T_1762 = _T_1760 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] intpend_rd_part_out_0 = _T_1762 & intpend_reg_extended[31:0]; // @[el2_pic_ctl.scala 298:119] - wire _T_1767 = _T_1759 == 4'h1; // @[el2_pic_ctl.scala 298:105] - wire [31:0] _T_1769 = _T_1767 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] intpend_rd_part_out_1 = _T_1769 & intpend_reg_extended[63:32]; // @[el2_pic_ctl.scala 298:119] - wire [31:0] intpend_rd_out = intpend_rd_part_out_0 | intpend_rd_part_out_1; // @[el2_pic_ctl.scala 299:89] - wire intenable_rd_out = intenable_reg_re_31 & intenable_reg_31; // @[el2_pic_ctl.scala 300:76] - wire [3:0] _T_1835 = intpriority_reg_re_31 ? intpriority_reg_31 : 4'h0; // @[Mux.scala 98:16] - wire [3:0] _T_1836 = intpriority_reg_re_30 ? intpriority_reg_30 : _T_1835; // @[Mux.scala 98:16] - wire [3:0] _T_1837 = intpriority_reg_re_29 ? intpriority_reg_29 : _T_1836; // @[Mux.scala 98:16] - wire [3:0] _T_1838 = intpriority_reg_re_28 ? intpriority_reg_28 : _T_1837; // @[Mux.scala 98:16] - wire [3:0] _T_1839 = intpriority_reg_re_27 ? intpriority_reg_27 : _T_1838; // @[Mux.scala 98:16] - wire [3:0] _T_1840 = intpriority_reg_re_26 ? intpriority_reg_26 : _T_1839; // @[Mux.scala 98:16] - wire [3:0] _T_1841 = intpriority_reg_re_25 ? intpriority_reg_25 : _T_1840; // @[Mux.scala 98:16] - wire [3:0] _T_1842 = intpriority_reg_re_24 ? intpriority_reg_24 : _T_1841; // @[Mux.scala 98:16] - wire [3:0] _T_1843 = intpriority_reg_re_23 ? intpriority_reg_23 : _T_1842; // @[Mux.scala 98:16] - wire [3:0] _T_1844 = intpriority_reg_re_22 ? intpriority_reg_22 : _T_1843; // @[Mux.scala 98:16] - wire [3:0] _T_1845 = intpriority_reg_re_21 ? intpriority_reg_21 : _T_1844; // @[Mux.scala 98:16] - wire [3:0] _T_1846 = intpriority_reg_re_20 ? intpriority_reg_20 : _T_1845; // @[Mux.scala 98:16] - wire [3:0] _T_1847 = intpriority_reg_re_19 ? intpriority_reg_19 : _T_1846; // @[Mux.scala 98:16] - wire [3:0] _T_1848 = intpriority_reg_re_18 ? intpriority_reg_18 : _T_1847; // @[Mux.scala 98:16] - wire [3:0] _T_1849 = intpriority_reg_re_17 ? intpriority_reg_17 : _T_1848; // @[Mux.scala 98:16] - wire [3:0] _T_1850 = intpriority_reg_re_16 ? intpriority_reg_16 : _T_1849; // @[Mux.scala 98:16] - wire [3:0] _T_1851 = intpriority_reg_re_15 ? intpriority_reg_15 : _T_1850; // @[Mux.scala 98:16] - wire [3:0] _T_1852 = intpriority_reg_re_14 ? intpriority_reg_14 : _T_1851; // @[Mux.scala 98:16] - wire [3:0] _T_1853 = intpriority_reg_re_13 ? intpriority_reg_13 : _T_1852; // @[Mux.scala 98:16] - wire [3:0] _T_1854 = intpriority_reg_re_12 ? intpriority_reg_12 : _T_1853; // @[Mux.scala 98:16] - wire [3:0] _T_1855 = intpriority_reg_re_11 ? intpriority_reg_11 : _T_1854; // @[Mux.scala 98:16] - wire [3:0] _T_1856 = intpriority_reg_re_10 ? intpriority_reg_10 : _T_1855; // @[Mux.scala 98:16] - wire [3:0] _T_1857 = intpriority_reg_re_9 ? intpriority_reg_9 : _T_1856; // @[Mux.scala 98:16] - wire [3:0] _T_1858 = intpriority_reg_re_8 ? intpriority_reg_8 : _T_1857; // @[Mux.scala 98:16] - wire [3:0] _T_1859 = intpriority_reg_re_7 ? intpriority_reg_7 : _T_1858; // @[Mux.scala 98:16] - wire [3:0] _T_1860 = intpriority_reg_re_6 ? intpriority_reg_6 : _T_1859; // @[Mux.scala 98:16] - wire [3:0] _T_1861 = intpriority_reg_re_5 ? intpriority_reg_5 : _T_1860; // @[Mux.scala 98:16] - wire [3:0] _T_1862 = intpriority_reg_re_4 ? intpriority_reg_4 : _T_1861; // @[Mux.scala 98:16] - wire [3:0] _T_1863 = intpriority_reg_re_3 ? intpriority_reg_3 : _T_1862; // @[Mux.scala 98:16] - wire [3:0] _T_1864 = intpriority_reg_re_2 ? intpriority_reg_2 : _T_1863; // @[Mux.scala 98:16] - wire [3:0] intpriority_rd_out = intpriority_reg_re_1 ? intpriority_reg_1 : _T_1864; // @[Mux.scala 98:16] - wire [1:0] _T_1897 = gw_config_reg_re_31 ? gw_config_reg_31 : 2'h0; // @[Mux.scala 98:16] - wire [1:0] _T_1898 = gw_config_reg_re_30 ? gw_config_reg_30 : _T_1897; // @[Mux.scala 98:16] - wire [1:0] _T_1899 = gw_config_reg_re_29 ? gw_config_reg_29 : _T_1898; // @[Mux.scala 98:16] - wire [1:0] _T_1900 = gw_config_reg_re_28 ? gw_config_reg_28 : _T_1899; // @[Mux.scala 98:16] - wire [1:0] _T_1901 = gw_config_reg_re_27 ? gw_config_reg_27 : _T_1900; // @[Mux.scala 98:16] - wire [1:0] _T_1902 = gw_config_reg_re_26 ? gw_config_reg_26 : _T_1901; // @[Mux.scala 98:16] - wire [1:0] _T_1903 = gw_config_reg_re_25 ? gw_config_reg_25 : _T_1902; // @[Mux.scala 98:16] - wire [1:0] _T_1904 = gw_config_reg_re_24 ? gw_config_reg_24 : _T_1903; // @[Mux.scala 98:16] - wire [1:0] _T_1905 = gw_config_reg_re_23 ? gw_config_reg_23 : _T_1904; // @[Mux.scala 98:16] - wire [1:0] _T_1906 = gw_config_reg_re_22 ? gw_config_reg_22 : _T_1905; // @[Mux.scala 98:16] - wire [1:0] _T_1907 = gw_config_reg_re_21 ? gw_config_reg_21 : _T_1906; // @[Mux.scala 98:16] - wire [1:0] _T_1908 = gw_config_reg_re_20 ? gw_config_reg_20 : _T_1907; // @[Mux.scala 98:16] - wire [1:0] _T_1909 = gw_config_reg_re_19 ? gw_config_reg_19 : _T_1908; // @[Mux.scala 98:16] - wire [1:0] _T_1910 = gw_config_reg_re_18 ? gw_config_reg_18 : _T_1909; // @[Mux.scala 98:16] - wire [1:0] _T_1911 = gw_config_reg_re_17 ? gw_config_reg_17 : _T_1910; // @[Mux.scala 98:16] - wire [1:0] _T_1912 = gw_config_reg_re_16 ? gw_config_reg_16 : _T_1911; // @[Mux.scala 98:16] - wire [1:0] _T_1913 = gw_config_reg_re_15 ? gw_config_reg_15 : _T_1912; // @[Mux.scala 98:16] - wire [1:0] _T_1914 = gw_config_reg_re_14 ? gw_config_reg_14 : _T_1913; // @[Mux.scala 98:16] - wire [1:0] _T_1915 = gw_config_reg_re_13 ? gw_config_reg_13 : _T_1914; // @[Mux.scala 98:16] - wire [1:0] _T_1916 = gw_config_reg_re_12 ? gw_config_reg_12 : _T_1915; // @[Mux.scala 98:16] - wire [1:0] _T_1917 = gw_config_reg_re_11 ? gw_config_reg_11 : _T_1916; // @[Mux.scala 98:16] - wire [1:0] _T_1918 = gw_config_reg_re_10 ? gw_config_reg_10 : _T_1917; // @[Mux.scala 98:16] - wire [1:0] _T_1919 = gw_config_reg_re_9 ? gw_config_reg_9 : _T_1918; // @[Mux.scala 98:16] - wire [1:0] _T_1920 = gw_config_reg_re_8 ? gw_config_reg_8 : _T_1919; // @[Mux.scala 98:16] - wire [1:0] _T_1921 = gw_config_reg_re_7 ? gw_config_reg_7 : _T_1920; // @[Mux.scala 98:16] - wire [1:0] _T_1922 = gw_config_reg_re_6 ? gw_config_reg_6 : _T_1921; // @[Mux.scala 98:16] - wire [1:0] _T_1923 = gw_config_reg_re_5 ? gw_config_reg_5 : _T_1922; // @[Mux.scala 98:16] - wire [1:0] _T_1924 = gw_config_reg_re_4 ? gw_config_reg_4 : _T_1923; // @[Mux.scala 98:16] - wire [1:0] _T_1925 = gw_config_reg_re_3 ? gw_config_reg_3 : _T_1924; // @[Mux.scala 98:16] - wire [1:0] _T_1926 = gw_config_reg_re_2 ? gw_config_reg_2 : _T_1925; // @[Mux.scala 98:16] - wire [1:0] gw_config_rd_out = gw_config_reg_re_1 ? gw_config_reg_1 : _T_1926; // @[Mux.scala 98:16] - wire [31:0] _T_1931 = {28'h0,intpriority_rd_out}; // @[Cat.scala 29:58] - wire [31:0] _T_1934 = {31'h0,intenable_rd_out}; // @[Cat.scala 29:58] - wire [31:0] _T_1937 = {30'h0,gw_config_rd_out}; // @[Cat.scala 29:58] - wire [31:0] _T_1940 = {31'h0,config_reg}; // @[Cat.scala 29:58] - wire [14:0] address = picm_raddr_ff[14:0]; // @[el2_pic_ctl.scala 320:30] - wire _T_1980 = 15'h3000 == address; // @[Conditional.scala 37:30] - wire _T_1981 = 15'h4004 == address; // @[Conditional.scala 37:30] - wire _T_1982 = 15'h4008 == address; // @[Conditional.scala 37:30] - wire _T_1983 = 15'h400c == address; // @[Conditional.scala 37:30] - wire _T_1984 = 15'h4010 == address; // @[Conditional.scala 37:30] - wire _T_1985 = 15'h4014 == address; // @[Conditional.scala 37:30] - wire _T_1986 = 15'h4018 == address; // @[Conditional.scala 37:30] - wire _T_1987 = 15'h401c == address; // @[Conditional.scala 37:30] - wire _T_1988 = 15'h4020 == address; // @[Conditional.scala 37:30] - wire _T_1989 = 15'h4024 == address; // @[Conditional.scala 37:30] - wire _T_1990 = 15'h4028 == address; // @[Conditional.scala 37:30] - wire _T_1991 = 15'h402c == address; // @[Conditional.scala 37:30] - wire _T_1992 = 15'h4030 == address; // @[Conditional.scala 37:30] - wire _T_1993 = 15'h4034 == address; // @[Conditional.scala 37:30] - wire _T_1994 = 15'h4038 == address; // @[Conditional.scala 37:30] - wire _T_1995 = 15'h403c == address; // @[Conditional.scala 37:30] - wire _T_1996 = 15'h4040 == address; // @[Conditional.scala 37:30] - wire _T_1997 = 15'h4044 == address; // @[Conditional.scala 37:30] - wire _T_1998 = 15'h4048 == address; // @[Conditional.scala 37:30] - wire _T_1999 = 15'h404c == address; // @[Conditional.scala 37:30] - wire _T_2000 = 15'h4050 == address; // @[Conditional.scala 37:30] - wire _T_2001 = 15'h4054 == address; // @[Conditional.scala 37:30] - wire _T_2002 = 15'h4058 == address; // @[Conditional.scala 37:30] - wire _T_2003 = 15'h405c == address; // @[Conditional.scala 37:30] - wire _T_2004 = 15'h4060 == address; // @[Conditional.scala 37:30] - wire _T_2005 = 15'h4064 == address; // @[Conditional.scala 37:30] - wire _T_2006 = 15'h4068 == address; // @[Conditional.scala 37:30] - wire _T_2007 = 15'h406c == address; // @[Conditional.scala 37:30] - wire _T_2008 = 15'h4070 == address; // @[Conditional.scala 37:30] - wire _T_2009 = 15'h4074 == address; // @[Conditional.scala 37:30] - wire _T_2010 = 15'h4078 == address; // @[Conditional.scala 37:30] - wire _T_2011 = 15'h407c == address; // @[Conditional.scala 37:30] - wire _T_2012 = 15'h2004 == address; // @[Conditional.scala 37:30] - wire _T_2013 = 15'h2008 == address; // @[Conditional.scala 37:30] - wire _T_2014 = 15'h200c == address; // @[Conditional.scala 37:30] - wire _T_2015 = 15'h2010 == address; // @[Conditional.scala 37:30] - wire _T_2016 = 15'h2014 == address; // @[Conditional.scala 37:30] - wire _T_2017 = 15'h2018 == address; // @[Conditional.scala 37:30] - wire _T_2018 = 15'h201c == address; // @[Conditional.scala 37:30] - wire _T_2019 = 15'h2020 == address; // @[Conditional.scala 37:30] - wire _T_2020 = 15'h2024 == address; // @[Conditional.scala 37:30] - wire _T_2021 = 15'h2028 == address; // @[Conditional.scala 37:30] - wire _T_2022 = 15'h202c == address; // @[Conditional.scala 37:30] - wire _T_2023 = 15'h2030 == address; // @[Conditional.scala 37:30] - wire _T_2024 = 15'h2034 == address; // @[Conditional.scala 37:30] - wire _T_2025 = 15'h2038 == address; // @[Conditional.scala 37:30] - wire _T_2026 = 15'h203c == address; // @[Conditional.scala 37:30] - wire _T_2027 = 15'h2040 == address; // @[Conditional.scala 37:30] - wire _T_2028 = 15'h2044 == address; // @[Conditional.scala 37:30] - wire _T_2029 = 15'h2048 == address; // @[Conditional.scala 37:30] - wire _T_2030 = 15'h204c == address; // @[Conditional.scala 37:30] - wire _T_2031 = 15'h2050 == address; // @[Conditional.scala 37:30] - wire _T_2032 = 15'h2054 == address; // @[Conditional.scala 37:30] - wire _T_2033 = 15'h2058 == address; // @[Conditional.scala 37:30] - wire _T_2034 = 15'h205c == address; // @[Conditional.scala 37:30] - wire _T_2035 = 15'h2060 == address; // @[Conditional.scala 37:30] - wire _T_2036 = 15'h2064 == address; // @[Conditional.scala 37:30] - wire _T_2037 = 15'h2068 == address; // @[Conditional.scala 37:30] - wire _T_2038 = 15'h206c == address; // @[Conditional.scala 37:30] - wire _T_2039 = 15'h2070 == address; // @[Conditional.scala 37:30] - wire _T_2040 = 15'h2074 == address; // @[Conditional.scala 37:30] - wire _T_2041 = 15'h2078 == address; // @[Conditional.scala 37:30] - wire _T_2042 = 15'h207c == address; // @[Conditional.scala 37:30] - wire _T_2043 = 15'h4 == address; // @[Conditional.scala 37:30] - wire _T_2044 = 15'h8 == address; // @[Conditional.scala 37:30] - wire _T_2045 = 15'hc == address; // @[Conditional.scala 37:30] - wire _T_2046 = 15'h10 == address; // @[Conditional.scala 37:30] - wire _T_2047 = 15'h14 == address; // @[Conditional.scala 37:30] - wire _T_2048 = 15'h18 == address; // @[Conditional.scala 37:30] - wire _T_2049 = 15'h1c == address; // @[Conditional.scala 37:30] - wire _T_2050 = 15'h20 == address; // @[Conditional.scala 37:30] - wire _T_2051 = 15'h24 == address; // @[Conditional.scala 37:30] - wire _T_2052 = 15'h28 == address; // @[Conditional.scala 37:30] - wire _T_2053 = 15'h2c == address; // @[Conditional.scala 37:30] - wire _T_2054 = 15'h30 == address; // @[Conditional.scala 37:30] - wire _T_2055 = 15'h34 == address; // @[Conditional.scala 37:30] - wire _T_2056 = 15'h38 == address; // @[Conditional.scala 37:30] - wire _T_2057 = 15'h3c == address; // @[Conditional.scala 37:30] - wire _T_2058 = 15'h40 == address; // @[Conditional.scala 37:30] - wire _T_2059 = 15'h44 == address; // @[Conditional.scala 37:30] - wire _T_2060 = 15'h48 == address; // @[Conditional.scala 37:30] - wire _T_2061 = 15'h4c == address; // @[Conditional.scala 37:30] - wire _T_2062 = 15'h50 == address; // @[Conditional.scala 37:30] - wire _T_2063 = 15'h54 == address; // @[Conditional.scala 37:30] - wire _T_2064 = 15'h58 == address; // @[Conditional.scala 37:30] - wire _T_2065 = 15'h5c == address; // @[Conditional.scala 37:30] - wire _T_2066 = 15'h60 == address; // @[Conditional.scala 37:30] - wire _T_2067 = 15'h64 == address; // @[Conditional.scala 37:30] - wire _T_2068 = 15'h68 == address; // @[Conditional.scala 37:30] - wire _T_2069 = 15'h6c == address; // @[Conditional.scala 37:30] - wire _T_2070 = 15'h70 == address; // @[Conditional.scala 37:30] - wire _T_2071 = 15'h74 == address; // @[Conditional.scala 37:30] - wire _T_2072 = 15'h78 == address; // @[Conditional.scala 37:30] - wire _T_2073 = 15'h7c == address; // @[Conditional.scala 37:30] - wire [3:0] _GEN_126 = _T_2073 ? 4'h2 : 4'h1; // @[Conditional.scala 39:67] - wire [3:0] _GEN_127 = _T_2072 ? 4'h2 : _GEN_126; // @[Conditional.scala 39:67] - wire [3:0] _GEN_128 = _T_2071 ? 4'h2 : _GEN_127; // @[Conditional.scala 39:67] - wire [3:0] _GEN_129 = _T_2070 ? 4'h2 : _GEN_128; // @[Conditional.scala 39:67] - wire [3:0] _GEN_130 = _T_2069 ? 4'h2 : _GEN_129; // @[Conditional.scala 39:67] - wire [3:0] _GEN_131 = _T_2068 ? 4'h2 : _GEN_130; // @[Conditional.scala 39:67] - wire [3:0] _GEN_132 = _T_2067 ? 4'h2 : _GEN_131; // @[Conditional.scala 39:67] - wire [3:0] _GEN_133 = _T_2066 ? 4'h2 : _GEN_132; // @[Conditional.scala 39:67] - wire [3:0] _GEN_134 = _T_2065 ? 4'h2 : _GEN_133; // @[Conditional.scala 39:67] - wire [3:0] _GEN_135 = _T_2064 ? 4'h2 : _GEN_134; // @[Conditional.scala 39:67] - wire [3:0] _GEN_136 = _T_2063 ? 4'h2 : _GEN_135; // @[Conditional.scala 39:67] - wire [3:0] _GEN_137 = _T_2062 ? 4'h2 : _GEN_136; // @[Conditional.scala 39:67] - wire [3:0] _GEN_138 = _T_2061 ? 4'h2 : _GEN_137; // @[Conditional.scala 39:67] - wire [3:0] _GEN_139 = _T_2060 ? 4'h2 : _GEN_138; // @[Conditional.scala 39:67] - wire [3:0] _GEN_140 = _T_2059 ? 4'h2 : _GEN_139; // @[Conditional.scala 39:67] - wire [3:0] _GEN_141 = _T_2058 ? 4'h2 : _GEN_140; // @[Conditional.scala 39:67] - wire [3:0] _GEN_142 = _T_2057 ? 4'h2 : _GEN_141; // @[Conditional.scala 39:67] - wire [3:0] _GEN_143 = _T_2056 ? 4'h2 : _GEN_142; // @[Conditional.scala 39:67] - wire [3:0] _GEN_144 = _T_2055 ? 4'h2 : _GEN_143; // @[Conditional.scala 39:67] - wire [3:0] _GEN_145 = _T_2054 ? 4'h2 : _GEN_144; // @[Conditional.scala 39:67] - wire [3:0] _GEN_146 = _T_2053 ? 4'h2 : _GEN_145; // @[Conditional.scala 39:67] - wire [3:0] _GEN_147 = _T_2052 ? 4'h2 : _GEN_146; // @[Conditional.scala 39:67] - wire [3:0] _GEN_148 = _T_2051 ? 4'h2 : _GEN_147; // @[Conditional.scala 39:67] - wire [3:0] _GEN_149 = _T_2050 ? 4'h2 : _GEN_148; // @[Conditional.scala 39:67] - wire [3:0] _GEN_150 = _T_2049 ? 4'h2 : _GEN_149; // @[Conditional.scala 39:67] - wire [3:0] _GEN_151 = _T_2048 ? 4'h2 : _GEN_150; // @[Conditional.scala 39:67] - wire [3:0] _GEN_152 = _T_2047 ? 4'h2 : _GEN_151; // @[Conditional.scala 39:67] - wire [3:0] _GEN_153 = _T_2046 ? 4'h2 : _GEN_152; // @[Conditional.scala 39:67] - wire [3:0] _GEN_154 = _T_2045 ? 4'h2 : _GEN_153; // @[Conditional.scala 39:67] - wire [3:0] _GEN_155 = _T_2044 ? 4'h2 : _GEN_154; // @[Conditional.scala 39:67] - wire [3:0] _GEN_156 = _T_2043 ? 4'h2 : _GEN_155; // @[Conditional.scala 39:67] - wire [3:0] _GEN_157 = _T_2042 ? 4'h4 : _GEN_156; // @[Conditional.scala 39:67] - wire [3:0] _GEN_158 = _T_2041 ? 4'h4 : _GEN_157; // @[Conditional.scala 39:67] - wire [3:0] _GEN_159 = _T_2040 ? 4'h4 : _GEN_158; // @[Conditional.scala 39:67] - wire [3:0] _GEN_160 = _T_2039 ? 4'h4 : _GEN_159; // @[Conditional.scala 39:67] - wire [3:0] _GEN_161 = _T_2038 ? 4'h4 : _GEN_160; // @[Conditional.scala 39:67] - wire [3:0] _GEN_162 = _T_2037 ? 4'h4 : _GEN_161; // @[Conditional.scala 39:67] - wire [3:0] _GEN_163 = _T_2036 ? 4'h4 : _GEN_162; // @[Conditional.scala 39:67] - wire [3:0] _GEN_164 = _T_2035 ? 4'h4 : _GEN_163; // @[Conditional.scala 39:67] - wire [3:0] _GEN_165 = _T_2034 ? 4'h4 : _GEN_164; // @[Conditional.scala 39:67] - wire [3:0] _GEN_166 = _T_2033 ? 4'h4 : _GEN_165; // @[Conditional.scala 39:67] - wire [3:0] _GEN_167 = _T_2032 ? 4'h4 : _GEN_166; // @[Conditional.scala 39:67] - wire [3:0] _GEN_168 = _T_2031 ? 4'h4 : _GEN_167; // @[Conditional.scala 39:67] - wire [3:0] _GEN_169 = _T_2030 ? 4'h4 : _GEN_168; // @[Conditional.scala 39:67] - wire [3:0] _GEN_170 = _T_2029 ? 4'h4 : _GEN_169; // @[Conditional.scala 39:67] - wire [3:0] _GEN_171 = _T_2028 ? 4'h4 : _GEN_170; // @[Conditional.scala 39:67] - wire [3:0] _GEN_172 = _T_2027 ? 4'h4 : _GEN_171; // @[Conditional.scala 39:67] - wire [3:0] _GEN_173 = _T_2026 ? 4'h4 : _GEN_172; // @[Conditional.scala 39:67] - wire [3:0] _GEN_174 = _T_2025 ? 4'h4 : _GEN_173; // @[Conditional.scala 39:67] - wire [3:0] _GEN_175 = _T_2024 ? 4'h4 : _GEN_174; // @[Conditional.scala 39:67] - wire [3:0] _GEN_176 = _T_2023 ? 4'h4 : _GEN_175; // @[Conditional.scala 39:67] - wire [3:0] _GEN_177 = _T_2022 ? 4'h4 : _GEN_176; // @[Conditional.scala 39:67] - wire [3:0] _GEN_178 = _T_2021 ? 4'h4 : _GEN_177; // @[Conditional.scala 39:67] - wire [3:0] _GEN_179 = _T_2020 ? 4'h4 : _GEN_178; // @[Conditional.scala 39:67] - wire [3:0] _GEN_180 = _T_2019 ? 4'h4 : _GEN_179; // @[Conditional.scala 39:67] - wire [3:0] _GEN_181 = _T_2018 ? 4'h4 : _GEN_180; // @[Conditional.scala 39:67] - wire [3:0] _GEN_182 = _T_2017 ? 4'h4 : _GEN_181; // @[Conditional.scala 39:67] - wire [3:0] _GEN_183 = _T_2016 ? 4'h4 : _GEN_182; // @[Conditional.scala 39:67] - wire [3:0] _GEN_184 = _T_2015 ? 4'h4 : _GEN_183; // @[Conditional.scala 39:67] - wire [3:0] _GEN_185 = _T_2014 ? 4'h4 : _GEN_184; // @[Conditional.scala 39:67] - wire [3:0] _GEN_186 = _T_2013 ? 4'h4 : _GEN_185; // @[Conditional.scala 39:67] - wire [3:0] _GEN_187 = _T_2012 ? 4'h4 : _GEN_186; // @[Conditional.scala 39:67] - wire [3:0] _GEN_188 = _T_2011 ? 4'h8 : _GEN_187; // @[Conditional.scala 39:67] - wire [3:0] _GEN_189 = _T_2010 ? 4'h8 : _GEN_188; // @[Conditional.scala 39:67] - wire [3:0] _GEN_190 = _T_2009 ? 4'h8 : _GEN_189; // @[Conditional.scala 39:67] - wire [3:0] _GEN_191 = _T_2008 ? 4'h8 : _GEN_190; // @[Conditional.scala 39:67] - wire [3:0] _GEN_192 = _T_2007 ? 4'h8 : _GEN_191; // @[Conditional.scala 39:67] - wire [3:0] _GEN_193 = _T_2006 ? 4'h8 : _GEN_192; // @[Conditional.scala 39:67] - wire [3:0] _GEN_194 = _T_2005 ? 4'h8 : _GEN_193; // @[Conditional.scala 39:67] - wire [3:0] _GEN_195 = _T_2004 ? 4'h8 : _GEN_194; // @[Conditional.scala 39:67] - wire [3:0] _GEN_196 = _T_2003 ? 4'h8 : _GEN_195; // @[Conditional.scala 39:67] - wire [3:0] _GEN_197 = _T_2002 ? 4'h8 : _GEN_196; // @[Conditional.scala 39:67] - wire [3:0] _GEN_198 = _T_2001 ? 4'h8 : _GEN_197; // @[Conditional.scala 39:67] - wire [3:0] _GEN_199 = _T_2000 ? 4'h8 : _GEN_198; // @[Conditional.scala 39:67] - wire [3:0] _GEN_200 = _T_1999 ? 4'h8 : _GEN_199; // @[Conditional.scala 39:67] - wire [3:0] _GEN_201 = _T_1998 ? 4'h8 : _GEN_200; // @[Conditional.scala 39:67] - wire [3:0] _GEN_202 = _T_1997 ? 4'h8 : _GEN_201; // @[Conditional.scala 39:67] - wire [3:0] _GEN_203 = _T_1996 ? 4'h8 : _GEN_202; // @[Conditional.scala 39:67] - wire [3:0] _GEN_204 = _T_1995 ? 4'h8 : _GEN_203; // @[Conditional.scala 39:67] - wire [3:0] _GEN_205 = _T_1994 ? 4'h8 : _GEN_204; // @[Conditional.scala 39:67] - wire [3:0] _GEN_206 = _T_1993 ? 4'h8 : _GEN_205; // @[Conditional.scala 39:67] - wire [3:0] _GEN_207 = _T_1992 ? 4'h8 : _GEN_206; // @[Conditional.scala 39:67] - wire [3:0] _GEN_208 = _T_1991 ? 4'h8 : _GEN_207; // @[Conditional.scala 39:67] - wire [3:0] _GEN_209 = _T_1990 ? 4'h8 : _GEN_208; // @[Conditional.scala 39:67] - wire [3:0] _GEN_210 = _T_1989 ? 4'h8 : _GEN_209; // @[Conditional.scala 39:67] - wire [3:0] _GEN_211 = _T_1988 ? 4'h8 : _GEN_210; // @[Conditional.scala 39:67] - wire [3:0] _GEN_212 = _T_1987 ? 4'h8 : _GEN_211; // @[Conditional.scala 39:67] - wire [3:0] _GEN_213 = _T_1986 ? 4'h8 : _GEN_212; // @[Conditional.scala 39:67] - wire [3:0] _GEN_214 = _T_1985 ? 4'h8 : _GEN_213; // @[Conditional.scala 39:67] - wire [3:0] _GEN_215 = _T_1984 ? 4'h8 : _GEN_214; // @[Conditional.scala 39:67] - wire [3:0] _GEN_216 = _T_1983 ? 4'h8 : _GEN_215; // @[Conditional.scala 39:67] - wire [3:0] _GEN_217 = _T_1982 ? 4'h8 : _GEN_216; // @[Conditional.scala 39:67] - wire [3:0] _GEN_218 = _T_1981 ? 4'h8 : _GEN_217; // @[Conditional.scala 39:67] - wire [3:0] mask = _T_1980 ? 4'h4 : _GEN_218; // @[Conditional.scala 40:58] - wire _T_1942 = picm_mken_ff & mask[3]; // @[el2_pic_ctl.scala 313:19] - wire _T_1947 = picm_mken_ff & mask[2]; // @[el2_pic_ctl.scala 314:19] - wire _T_1952 = picm_mken_ff & mask[1]; // @[el2_pic_ctl.scala 315:19] - wire [31:0] _T_1960 = intpend_reg_read ? intpend_rd_out : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_1961 = _T_21 ? _T_1931 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_1962 = _T_24 ? _T_1934 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_1963 = _T_27 ? _T_1937 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_1964 = config_reg_re ? _T_1940 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_1965 = _T_1942 ? 32'h3 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_1966 = _T_1947 ? 32'h1 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_1967 = _T_1952 ? 32'hf : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_1969 = _T_1960 | _T_1961; // @[Mux.scala 27:72] - wire [31:0] _T_1970 = _T_1969 | _T_1962; // @[Mux.scala 27:72] - wire [31:0] _T_1971 = _T_1970 | _T_1963; // @[Mux.scala 27:72] - wire [31:0] _T_1972 = _T_1971 | _T_1964; // @[Mux.scala 27:72] - wire [31:0] _T_1973 = _T_1972 | _T_1965; // @[Mux.scala 27:72] - wire [31:0] _T_1974 = _T_1973 | _T_1966; // @[Mux.scala 27:72] - wire [31:0] picm_rd_data_in = _T_1974 | _T_1967; // @[Mux.scala 27:72] - wire [7:0] _T_1703 = out_id_34; // @[el2_pic_ctl.scala 38:12] - wire [7:0] level_intpend_id_5_0 = out_id_34; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] - wire [7:0] level_intpend_id_1_18 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_1_19 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_1_20 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_1_21 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_1_22 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_1_23 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_1_24 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_1_25 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_1_26 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_1_27 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_1_28 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_1_29 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_1_30 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_1_31 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_1_32 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_1_33 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_2_10 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_2_11 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_2_12 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_2_13 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_2_14 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_2_15 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_2_16 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_2_17 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_2_18 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_2_19 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_2_20 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_2_21 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_2_22 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_2_23 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_2_24 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_2_25 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_2_26 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_2_27 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_2_28 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_2_29 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_2_30 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_2_31 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_2_32 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_2_33 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_3_6 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_3_7 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_3_8 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_3_9 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_3_10 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_3_11 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_3_12 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_3_13 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_3_14 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_3_15 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_3_16 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_3_17 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_3_18 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_3_19 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_3_20 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_3_21 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_3_22 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_3_23 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_3_24 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_3_25 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_3_26 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_3_27 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_3_28 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_3_29 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_3_30 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_3_31 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_3_32 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_3_33 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_4_4 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_4_5 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_4_6 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_4_7 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_4_8 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_4_9 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_4_10 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_4_11 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_4_12 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_4_13 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_4_14 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_4_15 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_4_16 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_4_17 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_4_18 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_4_19 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_4_20 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_4_21 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_4_22 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_4_23 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_4_24 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_4_25 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_4_26 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_4_27 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_4_28 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_4_29 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_4_30 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_4_31 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_4_32 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_4_33 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_5_1 = _T_1699; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] - wire [7:0] level_intpend_id_5_2 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 243:46] - wire [7:0] level_intpend_id_5_3 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_5_4 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_5_5 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_5_6 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_5_7 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_5_8 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_5_9 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_5_10 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_5_11 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_5_12 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_5_13 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_5_14 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_5_15 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_5_16 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_5_17 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_5_18 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_5_19 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_5_20 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_5_21 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_5_22 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_5_23 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_5_24 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_5_25 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_5_26 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_5_27 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_5_28 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_5_29 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_5_30 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_5_31 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_5_32 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] - wire [7:0] level_intpend_id_5_33 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [3:0] level_intpend_w_prior_en_0_0 = 4'h0; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33] + wire [3:0] _T_1441 = intpend_w_prior_en_1; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63] + wire [3:0] level_intpend_w_prior_en_0_1 = intpend_w_prior_en_1; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33] + wire _T_1566 = intpriority_reg_0 < _T_1441; // @[el2_pic_ctl.scala 33:20] + wire [7:0] intpend_id_1 = 8'h1; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55] + wire [7:0] level_intpend_id_0_1 = 8'h1; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33] + wire [7:0] intpend_id_0 = 8'h0; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55] + wire [7:0] level_intpend_id_0_0 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33] + wire [7:0] out_id = _T_1566 ? intpend_id_1 : intpend_id_0; // @[el2_pic_ctl.scala 33:9] + wire [3:0] out_priority = _T_1566 ? _T_1441 : intpriority_reg_0; // @[el2_pic_ctl.scala 33:49] + wire [3:0] _T_1445 = intpend_w_prior_en_2; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63] + wire [3:0] level_intpend_w_prior_en_0_2 = intpend_w_prior_en_2; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33] + wire [3:0] _T_1449 = intpend_w_prior_en_3; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63] + wire [3:0] level_intpend_w_prior_en_0_3 = intpend_w_prior_en_3; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33] + wire _T_1568 = _T_1445 < _T_1449; // @[el2_pic_ctl.scala 33:20] + wire [7:0] intpend_id_3 = 8'h3; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55] + wire [7:0] level_intpend_id_0_3 = 8'h3; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33] + wire [7:0] intpend_id_2 = 8'h2; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55] + wire [7:0] level_intpend_id_0_2 = 8'h2; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33] + wire [7:0] out_id_1 = _T_1568 ? intpend_id_3 : intpend_id_2; // @[el2_pic_ctl.scala 33:9] + wire [3:0] out_priority_1 = _T_1568 ? _T_1449 : _T_1445; // @[el2_pic_ctl.scala 33:49] + wire [3:0] _T_1453 = intpend_w_prior_en_4; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63] + wire [3:0] level_intpend_w_prior_en_0_4 = intpend_w_prior_en_4; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33] + wire [3:0] _T_1457 = intpend_w_prior_en_5; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63] + wire [3:0] level_intpend_w_prior_en_0_5 = intpend_w_prior_en_5; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33] + wire _T_1570 = _T_1453 < _T_1457; // @[el2_pic_ctl.scala 33:20] + wire [7:0] intpend_id_5 = 8'h5; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55] + wire [7:0] level_intpend_id_0_5 = 8'h5; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33] + wire [7:0] intpend_id_4 = 8'h4; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55] + wire [7:0] level_intpend_id_0_4 = 8'h4; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33] + wire [7:0] out_id_2 = _T_1570 ? intpend_id_5 : intpend_id_4; // @[el2_pic_ctl.scala 33:9] + wire [3:0] out_priority_2 = _T_1570 ? _T_1457 : _T_1453; // @[el2_pic_ctl.scala 33:49] + wire [3:0] _T_1461 = intpend_w_prior_en_6; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63] + wire [3:0] level_intpend_w_prior_en_0_6 = intpend_w_prior_en_6; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33] + wire [3:0] _T_1465 = intpend_w_prior_en_7; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63] + wire [3:0] level_intpend_w_prior_en_0_7 = intpend_w_prior_en_7; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33] + wire _T_1572 = _T_1461 < _T_1465; // @[el2_pic_ctl.scala 33:20] + wire [7:0] intpend_id_7 = 8'h7; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55] + wire [7:0] level_intpend_id_0_7 = 8'h7; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33] + wire [7:0] intpend_id_6 = 8'h6; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55] + wire [7:0] level_intpend_id_0_6 = 8'h6; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33] + wire [7:0] out_id_3 = _T_1572 ? intpend_id_7 : intpend_id_6; // @[el2_pic_ctl.scala 33:9] + wire [3:0] out_priority_3 = _T_1572 ? _T_1465 : _T_1461; // @[el2_pic_ctl.scala 33:49] + wire [3:0] _T_1469 = intpend_w_prior_en_8; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63] + wire [3:0] level_intpend_w_prior_en_0_8 = intpend_w_prior_en_8; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33] + wire [3:0] _T_1473 = intpend_w_prior_en_9; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63] + wire [3:0] level_intpend_w_prior_en_0_9 = intpend_w_prior_en_9; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33] + wire _T_1574 = _T_1469 < _T_1473; // @[el2_pic_ctl.scala 33:20] + wire [7:0] intpend_id_9 = 8'h9; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55] + wire [7:0] level_intpend_id_0_9 = 8'h9; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33] + wire [7:0] intpend_id_8 = 8'h8; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55] + wire [7:0] level_intpend_id_0_8 = 8'h8; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33] + wire [7:0] out_id_4 = _T_1574 ? intpend_id_9 : intpend_id_8; // @[el2_pic_ctl.scala 33:9] + wire [3:0] out_priority_4 = _T_1574 ? _T_1473 : _T_1469; // @[el2_pic_ctl.scala 33:49] + wire [3:0] _T_1477 = intpend_w_prior_en_10; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63] + wire [3:0] level_intpend_w_prior_en_0_10 = intpend_w_prior_en_10; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33] + wire [3:0] _T_1481 = intpend_w_prior_en_11; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63] + wire [3:0] level_intpend_w_prior_en_0_11 = intpend_w_prior_en_11; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33] + wire _T_1576 = _T_1477 < _T_1481; // @[el2_pic_ctl.scala 33:20] + wire [7:0] intpend_id_11 = 8'hb; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55] + wire [7:0] level_intpend_id_0_11 = 8'hb; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33] + wire [7:0] intpend_id_10 = 8'ha; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55] + wire [7:0] level_intpend_id_0_10 = 8'ha; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33] + wire [7:0] out_id_5 = _T_1576 ? intpend_id_11 : intpend_id_10; // @[el2_pic_ctl.scala 33:9] + wire [3:0] out_priority_5 = _T_1576 ? _T_1481 : _T_1477; // @[el2_pic_ctl.scala 33:49] + wire [3:0] _T_1485 = intpend_w_prior_en_12; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63] + wire [3:0] level_intpend_w_prior_en_0_12 = intpend_w_prior_en_12; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33] + wire [3:0] _T_1489 = intpend_w_prior_en_13; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63] + wire [3:0] level_intpend_w_prior_en_0_13 = intpend_w_prior_en_13; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33] + wire _T_1578 = _T_1485 < _T_1489; // @[el2_pic_ctl.scala 33:20] + wire [7:0] intpend_id_13 = 8'hd; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55] + wire [7:0] level_intpend_id_0_13 = 8'hd; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33] + wire [7:0] intpend_id_12 = 8'hc; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55] + wire [7:0] level_intpend_id_0_12 = 8'hc; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33] + wire [7:0] out_id_6 = _T_1578 ? intpend_id_13 : intpend_id_12; // @[el2_pic_ctl.scala 33:9] + wire [3:0] out_priority_6 = _T_1578 ? _T_1489 : _T_1485; // @[el2_pic_ctl.scala 33:49] + wire [3:0] _T_1493 = intpend_w_prior_en_14; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63] + wire [3:0] level_intpend_w_prior_en_0_14 = intpend_w_prior_en_14; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33] + wire [3:0] _T_1497 = intpend_w_prior_en_15; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63] + wire [3:0] level_intpend_w_prior_en_0_15 = intpend_w_prior_en_15; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33] + wire _T_1580 = _T_1493 < _T_1497; // @[el2_pic_ctl.scala 33:20] + wire [7:0] intpend_id_15 = 8'hf; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55] + wire [7:0] level_intpend_id_0_15 = 8'hf; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33] + wire [7:0] intpend_id_14 = 8'he; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55] + wire [7:0] level_intpend_id_0_14 = 8'he; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33] + wire [7:0] out_id_7 = _T_1580 ? intpend_id_15 : intpend_id_14; // @[el2_pic_ctl.scala 33:9] + wire [3:0] out_priority_7 = _T_1580 ? _T_1497 : _T_1493; // @[el2_pic_ctl.scala 33:49] + wire [3:0] _T_1501 = intpend_w_prior_en_16; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63] + wire [3:0] level_intpend_w_prior_en_0_16 = intpend_w_prior_en_16; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33] + wire [3:0] _T_1505 = intpend_w_prior_en_17; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63] + wire [3:0] level_intpend_w_prior_en_0_17 = intpend_w_prior_en_17; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33] + wire _T_1582 = _T_1501 < _T_1505; // @[el2_pic_ctl.scala 33:20] + wire [7:0] intpend_id_17 = 8'h11; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55] + wire [7:0] level_intpend_id_0_17 = 8'h11; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33] + wire [7:0] intpend_id_16 = 8'h10; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55] + wire [7:0] level_intpend_id_0_16 = 8'h10; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33] + wire [7:0] out_id_8 = _T_1582 ? intpend_id_17 : intpend_id_16; // @[el2_pic_ctl.scala 33:9] + wire [3:0] out_priority_8 = _T_1582 ? _T_1505 : _T_1501; // @[el2_pic_ctl.scala 33:49] + wire [3:0] _T_1509 = intpend_w_prior_en_18; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63] + wire [3:0] level_intpend_w_prior_en_0_18 = intpend_w_prior_en_18; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33] + wire [3:0] _T_1513 = intpend_w_prior_en_19; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63] + wire [3:0] level_intpend_w_prior_en_0_19 = intpend_w_prior_en_19; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33] + wire _T_1584 = _T_1509 < _T_1513; // @[el2_pic_ctl.scala 33:20] + wire [7:0] intpend_id_19 = 8'h13; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55] + wire [7:0] level_intpend_id_0_19 = 8'h13; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33] + wire [7:0] intpend_id_18 = 8'h12; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55] + wire [7:0] level_intpend_id_0_18 = 8'h12; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33] + wire [7:0] out_id_9 = _T_1584 ? intpend_id_19 : intpend_id_18; // @[el2_pic_ctl.scala 33:9] + wire [3:0] out_priority_9 = _T_1584 ? _T_1513 : _T_1509; // @[el2_pic_ctl.scala 33:49] + wire [3:0] _T_1517 = intpend_w_prior_en_20; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63] + wire [3:0] level_intpend_w_prior_en_0_20 = intpend_w_prior_en_20; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33] + wire [3:0] _T_1521 = intpend_w_prior_en_21; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63] + wire [3:0] level_intpend_w_prior_en_0_21 = intpend_w_prior_en_21; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33] + wire _T_1586 = _T_1517 < _T_1521; // @[el2_pic_ctl.scala 33:20] + wire [7:0] intpend_id_21 = 8'h15; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55] + wire [7:0] level_intpend_id_0_21 = 8'h15; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33] + wire [7:0] intpend_id_20 = 8'h14; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55] + wire [7:0] level_intpend_id_0_20 = 8'h14; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33] + wire [7:0] out_id_10 = _T_1586 ? intpend_id_21 : intpend_id_20; // @[el2_pic_ctl.scala 33:9] + wire [3:0] out_priority_10 = _T_1586 ? _T_1521 : _T_1517; // @[el2_pic_ctl.scala 33:49] + wire [3:0] _T_1525 = intpend_w_prior_en_22; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63] + wire [3:0] level_intpend_w_prior_en_0_22 = intpend_w_prior_en_22; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33] + wire [3:0] _T_1529 = intpend_w_prior_en_23; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63] + wire [3:0] level_intpend_w_prior_en_0_23 = intpend_w_prior_en_23; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33] + wire _T_1588 = _T_1525 < _T_1529; // @[el2_pic_ctl.scala 33:20] + wire [7:0] intpend_id_23 = 8'h17; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55] + wire [7:0] level_intpend_id_0_23 = 8'h17; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33] + wire [7:0] intpend_id_22 = 8'h16; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55] + wire [7:0] level_intpend_id_0_22 = 8'h16; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33] + wire [7:0] out_id_11 = _T_1588 ? intpend_id_23 : intpend_id_22; // @[el2_pic_ctl.scala 33:9] + wire [3:0] out_priority_11 = _T_1588 ? _T_1529 : _T_1525; // @[el2_pic_ctl.scala 33:49] + wire [3:0] _T_1533 = intpend_w_prior_en_24; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63] + wire [3:0] level_intpend_w_prior_en_0_24 = intpend_w_prior_en_24; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33] + wire [3:0] _T_1537 = intpend_w_prior_en_25; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63] + wire [3:0] level_intpend_w_prior_en_0_25 = intpend_w_prior_en_25; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33] + wire _T_1590 = _T_1533 < _T_1537; // @[el2_pic_ctl.scala 33:20] + wire [7:0] intpend_id_25 = 8'h19; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55] + wire [7:0] level_intpend_id_0_25 = 8'h19; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33] + wire [7:0] intpend_id_24 = 8'h18; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55] + wire [7:0] level_intpend_id_0_24 = 8'h18; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33] + wire [7:0] out_id_12 = _T_1590 ? intpend_id_25 : intpend_id_24; // @[el2_pic_ctl.scala 33:9] + wire [3:0] out_priority_12 = _T_1590 ? _T_1537 : _T_1533; // @[el2_pic_ctl.scala 33:49] + wire [3:0] _T_1541 = intpend_w_prior_en_26; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63] + wire [3:0] level_intpend_w_prior_en_0_26 = intpend_w_prior_en_26; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33] + wire [3:0] _T_1545 = intpend_w_prior_en_27; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63] + wire [3:0] level_intpend_w_prior_en_0_27 = intpend_w_prior_en_27; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33] + wire _T_1592 = _T_1541 < _T_1545; // @[el2_pic_ctl.scala 33:20] + wire [7:0] intpend_id_27 = 8'h1b; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55] + wire [7:0] level_intpend_id_0_27 = 8'h1b; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33] + wire [7:0] intpend_id_26 = 8'h1a; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55] + wire [7:0] level_intpend_id_0_26 = 8'h1a; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33] + wire [7:0] out_id_13 = _T_1592 ? intpend_id_27 : intpend_id_26; // @[el2_pic_ctl.scala 33:9] + wire [3:0] out_priority_13 = _T_1592 ? _T_1545 : _T_1541; // @[el2_pic_ctl.scala 33:49] + wire [3:0] _T_1549 = intpend_w_prior_en_28; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63] + wire [3:0] level_intpend_w_prior_en_0_28 = intpend_w_prior_en_28; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33] + wire [3:0] _T_1553 = intpend_w_prior_en_29; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63] + wire [3:0] level_intpend_w_prior_en_0_29 = intpend_w_prior_en_29; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33] + wire _T_1594 = _T_1549 < _T_1553; // @[el2_pic_ctl.scala 33:20] + wire [7:0] intpend_id_29 = 8'h1d; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55] + wire [7:0] level_intpend_id_0_29 = 8'h1d; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33] + wire [7:0] intpend_id_28 = 8'h1c; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55] + wire [7:0] level_intpend_id_0_28 = 8'h1c; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33] + wire [7:0] out_id_14 = _T_1594 ? intpend_id_29 : intpend_id_28; // @[el2_pic_ctl.scala 33:9] + wire [3:0] out_priority_14 = _T_1594 ? _T_1553 : _T_1549; // @[el2_pic_ctl.scala 33:49] + wire [3:0] _T_1557 = intpend_w_prior_en_30; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63] + wire [3:0] level_intpend_w_prior_en_0_30 = intpend_w_prior_en_30; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33] + wire [3:0] _T_1561 = intpend_w_prior_en_31; // @[el2_pic_ctl.scala 76:42 el2_pic_ctl.scala 167:63] + wire [3:0] level_intpend_w_prior_en_0_31 = intpend_w_prior_en_31; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33] + wire _T_1596 = _T_1557 < _T_1561; // @[el2_pic_ctl.scala 33:20] + wire [7:0] intpend_id_31 = 8'h1f; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55] + wire [7:0] level_intpend_id_0_31 = 8'h1f; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33] + wire [7:0] intpend_id_30 = 8'h1e; // @[el2_pic_ctl.scala 77:42 el2_pic_ctl.scala 168:55] + wire [7:0] level_intpend_id_0_30 = 8'h1e; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33] + wire [7:0] out_id_15 = _T_1596 ? intpend_id_31 : intpend_id_30; // @[el2_pic_ctl.scala 33:9] + wire [3:0] out_priority_15 = _T_1596 ? _T_1561 : _T_1557; // @[el2_pic_ctl.scala 33:49] + wire [3:0] level_intpend_w_prior_en_0_32 = 4'h0; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33] + wire [3:0] level_intpend_w_prior_en_0_33 = 4'h0; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 226:33] + wire _T_1598 = intpriority_reg_0 < intpriority_reg_0; // @[el2_pic_ctl.scala 33:20] + wire [7:0] level_intpend_id_0_33 = 8'hff; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33] + wire [7:0] level_intpend_id_0_32 = 8'hff; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 227:33] + wire [7:0] out_id_16 = _T_1598 ? _T_1564 : _T_1564; // @[el2_pic_ctl.scala 33:9] + wire _T_1600 = out_priority < out_priority_1; // @[el2_pic_ctl.scala 33:20] + wire [7:0] level_intpend_id_1_1 = out_id_1; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43] + wire [7:0] level_intpend_id_1_0 = out_id; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43] + wire [7:0] out_id_17 = _T_1600 ? level_intpend_id_1_1 : level_intpend_id_1_0; // @[el2_pic_ctl.scala 33:9] + wire [3:0] out_priority_17 = _T_1600 ? out_priority_1 : out_priority; // @[el2_pic_ctl.scala 33:49] + wire _T_1602 = out_priority_2 < out_priority_3; // @[el2_pic_ctl.scala 33:20] + wire [7:0] level_intpend_id_1_3 = out_id_3; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43] + wire [7:0] level_intpend_id_1_2 = out_id_2; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43] + wire [7:0] out_id_18 = _T_1602 ? level_intpend_id_1_3 : level_intpend_id_1_2; // @[el2_pic_ctl.scala 33:9] + wire [3:0] out_priority_18 = _T_1602 ? out_priority_3 : out_priority_2; // @[el2_pic_ctl.scala 33:49] + wire _T_1604 = out_priority_4 < out_priority_5; // @[el2_pic_ctl.scala 33:20] + wire [7:0] level_intpend_id_1_5 = out_id_5; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43] + wire [7:0] level_intpend_id_1_4 = out_id_4; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43] + wire [7:0] out_id_19 = _T_1604 ? level_intpend_id_1_5 : level_intpend_id_1_4; // @[el2_pic_ctl.scala 33:9] + wire [3:0] out_priority_19 = _T_1604 ? out_priority_5 : out_priority_4; // @[el2_pic_ctl.scala 33:49] + wire _T_1606 = out_priority_6 < out_priority_7; // @[el2_pic_ctl.scala 33:20] + wire [7:0] level_intpend_id_1_7 = out_id_7; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43] + wire [7:0] level_intpend_id_1_6 = out_id_6; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43] + wire [7:0] out_id_20 = _T_1606 ? level_intpend_id_1_7 : level_intpend_id_1_6; // @[el2_pic_ctl.scala 33:9] + wire [3:0] out_priority_20 = _T_1606 ? out_priority_7 : out_priority_6; // @[el2_pic_ctl.scala 33:49] + wire _T_1608 = out_priority_8 < out_priority_9; // @[el2_pic_ctl.scala 33:20] + wire [7:0] level_intpend_id_1_9 = out_id_9; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43] + wire [7:0] level_intpend_id_1_8 = out_id_8; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43] + wire [7:0] out_id_21 = _T_1608 ? level_intpend_id_1_9 : level_intpend_id_1_8; // @[el2_pic_ctl.scala 33:9] + wire [3:0] out_priority_21 = _T_1608 ? out_priority_9 : out_priority_8; // @[el2_pic_ctl.scala 33:49] + wire _T_1610 = out_priority_10 < out_priority_11; // @[el2_pic_ctl.scala 33:20] + wire [7:0] level_intpend_id_1_11 = out_id_11; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43] + wire [7:0] level_intpend_id_1_10 = out_id_10; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43] + wire [7:0] out_id_22 = _T_1610 ? level_intpend_id_1_11 : level_intpend_id_1_10; // @[el2_pic_ctl.scala 33:9] + wire [3:0] out_priority_22 = _T_1610 ? out_priority_11 : out_priority_10; // @[el2_pic_ctl.scala 33:49] + wire _T_1612 = out_priority_12 < out_priority_13; // @[el2_pic_ctl.scala 33:20] + wire [7:0] level_intpend_id_1_13 = out_id_13; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43] + wire [7:0] level_intpend_id_1_12 = out_id_12; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43] + wire [7:0] out_id_23 = _T_1612 ? level_intpend_id_1_13 : level_intpend_id_1_12; // @[el2_pic_ctl.scala 33:9] + wire [3:0] out_priority_23 = _T_1612 ? out_priority_13 : out_priority_12; // @[el2_pic_ctl.scala 33:49] + wire _T_1614 = out_priority_14 < out_priority_15; // @[el2_pic_ctl.scala 33:20] + wire [7:0] level_intpend_id_1_15 = out_id_15; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43] + wire [7:0] level_intpend_id_1_14 = out_id_14; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43] + wire [7:0] out_id_24 = _T_1614 ? level_intpend_id_1_15 : level_intpend_id_1_14; // @[el2_pic_ctl.scala 33:9] + wire [3:0] out_priority_24 = _T_1614 ? out_priority_15 : out_priority_14; // @[el2_pic_ctl.scala 33:49] + wire [7:0] level_intpend_id_1_17 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 235:46] + wire [7:0] level_intpend_id_1_16 = out_id_16; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43] + wire [7:0] out_id_25 = level_intpend_id_1_16; // @[el2_pic_ctl.scala 33:9] + wire _T_1618 = out_priority_17 < out_priority_18; // @[el2_pic_ctl.scala 33:20] + wire [7:0] level_intpend_id_2_1 = out_id_18; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43] + wire [7:0] level_intpend_id_2_0 = out_id_17; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43] + wire [7:0] out_id_26 = _T_1618 ? level_intpend_id_2_1 : level_intpend_id_2_0; // @[el2_pic_ctl.scala 33:9] + wire [3:0] out_priority_26 = _T_1618 ? out_priority_18 : out_priority_17; // @[el2_pic_ctl.scala 33:49] + wire _T_1620 = out_priority_19 < out_priority_20; // @[el2_pic_ctl.scala 33:20] + wire [7:0] level_intpend_id_2_3 = out_id_20; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43] + wire [7:0] level_intpend_id_2_2 = out_id_19; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43] + wire [7:0] out_id_27 = _T_1620 ? level_intpend_id_2_3 : level_intpend_id_2_2; // @[el2_pic_ctl.scala 33:9] + wire [3:0] out_priority_27 = _T_1620 ? out_priority_20 : out_priority_19; // @[el2_pic_ctl.scala 33:49] + wire _T_1622 = out_priority_21 < out_priority_22; // @[el2_pic_ctl.scala 33:20] + wire [7:0] level_intpend_id_2_5 = out_id_22; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43] + wire [7:0] level_intpend_id_2_4 = out_id_21; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43] + wire [7:0] out_id_28 = _T_1622 ? level_intpend_id_2_5 : level_intpend_id_2_4; // @[el2_pic_ctl.scala 33:9] + wire [3:0] out_priority_28 = _T_1622 ? out_priority_22 : out_priority_21; // @[el2_pic_ctl.scala 33:49] + wire _T_1624 = out_priority_23 < out_priority_24; // @[el2_pic_ctl.scala 33:20] + wire [7:0] level_intpend_id_2_7 = out_id_24; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43] + wire [7:0] level_intpend_id_2_6 = out_id_23; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43] + wire [7:0] out_id_29 = _T_1624 ? level_intpend_id_2_7 : level_intpend_id_2_6; // @[el2_pic_ctl.scala 33:9] + wire [3:0] out_priority_29 = _T_1624 ? out_priority_24 : out_priority_23; // @[el2_pic_ctl.scala 33:49] + wire [7:0] level_intpend_id_2_9 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 235:46] + wire [7:0] level_intpend_id_2_8 = level_intpend_id_1_16; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43] + wire [7:0] out_id_30 = out_id_25; // @[el2_pic_ctl.scala 33:9] + wire _T_1628 = out_priority_26 < out_priority_27; // @[el2_pic_ctl.scala 33:20] + wire [7:0] level_intpend_id_3_1 = out_id_27; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43] + wire [7:0] level_intpend_id_3_0 = out_id_26; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43] + wire [7:0] out_id_31 = _T_1628 ? level_intpend_id_3_1 : level_intpend_id_3_0; // @[el2_pic_ctl.scala 33:9] + wire [3:0] out_priority_31 = _T_1628 ? out_priority_27 : out_priority_26; // @[el2_pic_ctl.scala 33:49] + wire _T_1630 = out_priority_28 < out_priority_29; // @[el2_pic_ctl.scala 33:20] + wire [7:0] level_intpend_id_3_3 = out_id_29; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43] + wire [7:0] level_intpend_id_3_2 = out_id_28; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43] + wire [7:0] out_id_32 = _T_1630 ? level_intpend_id_3_3 : level_intpend_id_3_2; // @[el2_pic_ctl.scala 33:9] + wire [3:0] out_priority_32 = _T_1630 ? out_priority_29 : out_priority_28; // @[el2_pic_ctl.scala 33:49] + wire [7:0] level_intpend_id_3_5 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 235:46] + wire [7:0] level_intpend_id_3_4 = out_id_25; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43] + wire [7:0] out_id_33 = out_id_30; // @[el2_pic_ctl.scala 33:9] + wire _T_1634 = out_priority_31 < out_priority_32; // @[el2_pic_ctl.scala 33:20] + wire [7:0] level_intpend_id_4_1 = out_id_32; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43] + wire [7:0] level_intpend_id_4_0 = out_id_31; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43] + wire [7:0] out_id_34 = _T_1634 ? level_intpend_id_4_1 : level_intpend_id_4_0; // @[el2_pic_ctl.scala 33:9] + wire [3:0] out_priority_34 = _T_1634 ? out_priority_32 : out_priority_31; // @[el2_pic_ctl.scala 33:49] + wire [7:0] level_intpend_id_4_3 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 235:46] + wire [7:0] level_intpend_id_4_2 = out_id_30; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43] + wire config_reg_we = waddr_config_pic_match & picm_wren_ff; // @[el2_pic_ctl.scala 255:47] + wire config_reg_re = raddr_config_pic_match & picm_rden_ff; // @[el2_pic_ctl.scala 256:47] + wire [3:0] level_intpend_w_prior_en_5_0 = out_priority_34; // @[el2_pic_ctl.scala 219:40 el2_pic_ctl.scala 223:38 el2_pic_ctl.scala 239:43] + wire [3:0] selected_int_priority = out_priority_34; // @[el2_pic_ctl.scala 243:29] + wire [3:0] _T_1641 = ~level_intpend_w_prior_en_5_0; // @[el2_pic_ctl.scala 267:38] + wire [3:0] pl_in_q = config_reg ? _T_1641 : level_intpend_w_prior_en_5_0; // @[el2_pic_ctl.scala 267:20] + reg [7:0] _T_1642; // @[el2_pic_ctl.scala 268:47] + reg [3:0] _T_1643; // @[el2_pic_ctl.scala 269:42] + wire [3:0] _T_1645 = ~io_meipt; // @[el2_pic_ctl.scala 270:40] + wire [3:0] meipt_inv = config_reg ? _T_1645 : io_meipt; // @[el2_pic_ctl.scala 270:22] + wire [3:0] _T_1647 = ~io_meicurpl; // @[el2_pic_ctl.scala 271:43] + wire [3:0] meicurpl_inv = config_reg ? _T_1647 : io_meicurpl; // @[el2_pic_ctl.scala 271:25] + wire _T_1648 = level_intpend_w_prior_en_5_0 > meipt_inv; // @[el2_pic_ctl.scala 272:47] + wire _T_1649 = level_intpend_w_prior_en_5_0 > meicurpl_inv; // @[el2_pic_ctl.scala 272:86] + reg _T_1650; // @[el2_pic_ctl.scala 273:50] + wire [3:0] maxint = config_reg ? 4'h0 : 4'hf; // @[el2_pic_ctl.scala 274:19] + reg _T_1652; // @[el2_pic_ctl.scala 276:48] + wire intpend_reg_read = addr_intpend_base_match & picm_rden_ff; // @[el2_pic_ctl.scala 282:60] + wire [9:0] _T_1662 = {extintsrc_req_gw_31,extintsrc_req_gw_30,extintsrc_req_gw_29,extintsrc_req_gw_28,extintsrc_req_gw_27,extintsrc_req_gw_26,extintsrc_req_gw_25,extintsrc_req_gw_24,extintsrc_req_gw_23,extintsrc_req_gw_22}; // @[Cat.scala 29:58] + wire [18:0] _T_1671 = {_T_1662,extintsrc_req_gw_21,extintsrc_req_gw_20,extintsrc_req_gw_19,extintsrc_req_gw_18,extintsrc_req_gw_17,extintsrc_req_gw_16,extintsrc_req_gw_15,extintsrc_req_gw_14,extintsrc_req_gw_13}; // @[Cat.scala 29:58] + wire [27:0] _T_1680 = {_T_1671,extintsrc_req_gw_12,extintsrc_req_gw_11,extintsrc_req_gw_10,extintsrc_req_gw_9,extintsrc_req_gw_8,extintsrc_req_gw_7,extintsrc_req_gw_6,extintsrc_req_gw_5,extintsrc_req_gw_4}; // @[Cat.scala 29:58] + wire [63:0] intpend_reg_extended = {32'h0,_T_1680,extintsrc_req_gw_3,extintsrc_req_gw_2,extintsrc_req_gw_1,1'h0}; // @[Cat.scala 29:58] + wire [3:0] _GEN_220 = {{3'd0}, intpend_reg_read}; // @[el2_pic_ctl.scala 290:83] + wire [3:0] _T_1687 = _GEN_220 & picm_raddr_ff[5:2]; // @[el2_pic_ctl.scala 290:83] + wire _T_1688 = _T_1687 == 4'h0; // @[el2_pic_ctl.scala 290:105] + wire [31:0] _T_1690 = _T_1688 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] intpend_rd_part_out_0 = _T_1690 & intpend_reg_extended[31:0]; // @[el2_pic_ctl.scala 290:119] + wire _T_1695 = _T_1687 == 4'h1; // @[el2_pic_ctl.scala 290:105] + wire [31:0] _T_1697 = _T_1695 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] intpend_rd_part_out_1 = _T_1697 & intpend_reg_extended[63:32]; // @[el2_pic_ctl.scala 290:119] + wire [31:0] intpend_rd_out = intpend_rd_part_out_0 | intpend_rd_part_out_1; // @[el2_pic_ctl.scala 291:89] + wire intenable_rd_out = intenable_reg_re_31 & intenable_reg_31; // @[el2_pic_ctl.scala 292:76] + wire [3:0] _T_1763 = intpriority_reg_re_31 ? intpriority_reg_31 : 4'h0; // @[Mux.scala 98:16] + wire [3:0] _T_1764 = intpriority_reg_re_30 ? intpriority_reg_30 : _T_1763; // @[Mux.scala 98:16] + wire [3:0] _T_1765 = intpriority_reg_re_29 ? intpriority_reg_29 : _T_1764; // @[Mux.scala 98:16] + wire [3:0] _T_1766 = intpriority_reg_re_28 ? intpriority_reg_28 : _T_1765; // @[Mux.scala 98:16] + wire [3:0] _T_1767 = intpriority_reg_re_27 ? intpriority_reg_27 : _T_1766; // @[Mux.scala 98:16] + wire [3:0] _T_1768 = intpriority_reg_re_26 ? intpriority_reg_26 : _T_1767; // @[Mux.scala 98:16] + wire [3:0] _T_1769 = intpriority_reg_re_25 ? intpriority_reg_25 : _T_1768; // @[Mux.scala 98:16] + wire [3:0] _T_1770 = intpriority_reg_re_24 ? intpriority_reg_24 : _T_1769; // @[Mux.scala 98:16] + wire [3:0] _T_1771 = intpriority_reg_re_23 ? intpriority_reg_23 : _T_1770; // @[Mux.scala 98:16] + wire [3:0] _T_1772 = intpriority_reg_re_22 ? intpriority_reg_22 : _T_1771; // @[Mux.scala 98:16] + wire [3:0] _T_1773 = intpriority_reg_re_21 ? intpriority_reg_21 : _T_1772; // @[Mux.scala 98:16] + wire [3:0] _T_1774 = intpriority_reg_re_20 ? intpriority_reg_20 : _T_1773; // @[Mux.scala 98:16] + wire [3:0] _T_1775 = intpriority_reg_re_19 ? intpriority_reg_19 : _T_1774; // @[Mux.scala 98:16] + wire [3:0] _T_1776 = intpriority_reg_re_18 ? intpriority_reg_18 : _T_1775; // @[Mux.scala 98:16] + wire [3:0] _T_1777 = intpriority_reg_re_17 ? intpriority_reg_17 : _T_1776; // @[Mux.scala 98:16] + wire [3:0] _T_1778 = intpriority_reg_re_16 ? intpriority_reg_16 : _T_1777; // @[Mux.scala 98:16] + wire [3:0] _T_1779 = intpriority_reg_re_15 ? intpriority_reg_15 : _T_1778; // @[Mux.scala 98:16] + wire [3:0] _T_1780 = intpriority_reg_re_14 ? intpriority_reg_14 : _T_1779; // @[Mux.scala 98:16] + wire [3:0] _T_1781 = intpriority_reg_re_13 ? intpriority_reg_13 : _T_1780; // @[Mux.scala 98:16] + wire [3:0] _T_1782 = intpriority_reg_re_12 ? intpriority_reg_12 : _T_1781; // @[Mux.scala 98:16] + wire [3:0] _T_1783 = intpriority_reg_re_11 ? intpriority_reg_11 : _T_1782; // @[Mux.scala 98:16] + wire [3:0] _T_1784 = intpriority_reg_re_10 ? intpriority_reg_10 : _T_1783; // @[Mux.scala 98:16] + wire [3:0] _T_1785 = intpriority_reg_re_9 ? intpriority_reg_9 : _T_1784; // @[Mux.scala 98:16] + wire [3:0] _T_1786 = intpriority_reg_re_8 ? intpriority_reg_8 : _T_1785; // @[Mux.scala 98:16] + wire [3:0] _T_1787 = intpriority_reg_re_7 ? intpriority_reg_7 : _T_1786; // @[Mux.scala 98:16] + wire [3:0] _T_1788 = intpriority_reg_re_6 ? intpriority_reg_6 : _T_1787; // @[Mux.scala 98:16] + wire [3:0] _T_1789 = intpriority_reg_re_5 ? intpriority_reg_5 : _T_1788; // @[Mux.scala 98:16] + wire [3:0] _T_1790 = intpriority_reg_re_4 ? intpriority_reg_4 : _T_1789; // @[Mux.scala 98:16] + wire [3:0] _T_1791 = intpriority_reg_re_3 ? intpriority_reg_3 : _T_1790; // @[Mux.scala 98:16] + wire [3:0] _T_1792 = intpriority_reg_re_2 ? intpriority_reg_2 : _T_1791; // @[Mux.scala 98:16] + wire [3:0] intpriority_rd_out = intpriority_reg_re_1 ? intpriority_reg_1 : _T_1792; // @[Mux.scala 98:16] + wire [1:0] _T_1825 = gw_config_reg_re_31 ? gw_config_reg_31 : 2'h0; // @[Mux.scala 98:16] + wire [1:0] _T_1826 = gw_config_reg_re_30 ? gw_config_reg_30 : _T_1825; // @[Mux.scala 98:16] + wire [1:0] _T_1827 = gw_config_reg_re_29 ? gw_config_reg_29 : _T_1826; // @[Mux.scala 98:16] + wire [1:0] _T_1828 = gw_config_reg_re_28 ? gw_config_reg_28 : _T_1827; // @[Mux.scala 98:16] + wire [1:0] _T_1829 = gw_config_reg_re_27 ? gw_config_reg_27 : _T_1828; // @[Mux.scala 98:16] + wire [1:0] _T_1830 = gw_config_reg_re_26 ? gw_config_reg_26 : _T_1829; // @[Mux.scala 98:16] + wire [1:0] _T_1831 = gw_config_reg_re_25 ? gw_config_reg_25 : _T_1830; // @[Mux.scala 98:16] + wire [1:0] _T_1832 = gw_config_reg_re_24 ? gw_config_reg_24 : _T_1831; // @[Mux.scala 98:16] + wire [1:0] _T_1833 = gw_config_reg_re_23 ? gw_config_reg_23 : _T_1832; // @[Mux.scala 98:16] + wire [1:0] _T_1834 = gw_config_reg_re_22 ? gw_config_reg_22 : _T_1833; // @[Mux.scala 98:16] + wire [1:0] _T_1835 = gw_config_reg_re_21 ? gw_config_reg_21 : _T_1834; // @[Mux.scala 98:16] + wire [1:0] _T_1836 = gw_config_reg_re_20 ? gw_config_reg_20 : _T_1835; // @[Mux.scala 98:16] + wire [1:0] _T_1837 = gw_config_reg_re_19 ? gw_config_reg_19 : _T_1836; // @[Mux.scala 98:16] + wire [1:0] _T_1838 = gw_config_reg_re_18 ? gw_config_reg_18 : _T_1837; // @[Mux.scala 98:16] + wire [1:0] _T_1839 = gw_config_reg_re_17 ? gw_config_reg_17 : _T_1838; // @[Mux.scala 98:16] + wire [1:0] _T_1840 = gw_config_reg_re_16 ? gw_config_reg_16 : _T_1839; // @[Mux.scala 98:16] + wire [1:0] _T_1841 = gw_config_reg_re_15 ? gw_config_reg_15 : _T_1840; // @[Mux.scala 98:16] + wire [1:0] _T_1842 = gw_config_reg_re_14 ? gw_config_reg_14 : _T_1841; // @[Mux.scala 98:16] + wire [1:0] _T_1843 = gw_config_reg_re_13 ? gw_config_reg_13 : _T_1842; // @[Mux.scala 98:16] + wire [1:0] _T_1844 = gw_config_reg_re_12 ? gw_config_reg_12 : _T_1843; // @[Mux.scala 98:16] + wire [1:0] _T_1845 = gw_config_reg_re_11 ? gw_config_reg_11 : _T_1844; // @[Mux.scala 98:16] + wire [1:0] _T_1846 = gw_config_reg_re_10 ? gw_config_reg_10 : _T_1845; // @[Mux.scala 98:16] + wire [1:0] _T_1847 = gw_config_reg_re_9 ? gw_config_reg_9 : _T_1846; // @[Mux.scala 98:16] + wire [1:0] _T_1848 = gw_config_reg_re_8 ? gw_config_reg_8 : _T_1847; // @[Mux.scala 98:16] + wire [1:0] _T_1849 = gw_config_reg_re_7 ? gw_config_reg_7 : _T_1848; // @[Mux.scala 98:16] + wire [1:0] _T_1850 = gw_config_reg_re_6 ? gw_config_reg_6 : _T_1849; // @[Mux.scala 98:16] + wire [1:0] _T_1851 = gw_config_reg_re_5 ? gw_config_reg_5 : _T_1850; // @[Mux.scala 98:16] + wire [1:0] _T_1852 = gw_config_reg_re_4 ? gw_config_reg_4 : _T_1851; // @[Mux.scala 98:16] + wire [1:0] _T_1853 = gw_config_reg_re_3 ? gw_config_reg_3 : _T_1852; // @[Mux.scala 98:16] + wire [1:0] _T_1854 = gw_config_reg_re_2 ? gw_config_reg_2 : _T_1853; // @[Mux.scala 98:16] + wire [1:0] gw_config_rd_out = gw_config_reg_re_1 ? gw_config_reg_1 : _T_1854; // @[Mux.scala 98:16] + wire [31:0] _T_1859 = {28'h0,intpriority_rd_out}; // @[Cat.scala 29:58] + wire [31:0] _T_1862 = {31'h0,intenable_rd_out}; // @[Cat.scala 29:58] + wire [31:0] _T_1865 = {30'h0,gw_config_rd_out}; // @[Cat.scala 29:58] + wire [31:0] _T_1868 = {31'h0,config_reg}; // @[Cat.scala 29:58] + wire [14:0] address = picm_raddr_ff[14:0]; // @[el2_pic_ctl.scala 312:30] + wire _T_1908 = 15'h3000 == address; // @[Conditional.scala 37:30] + wire _T_1909 = 15'h4004 == address; // @[Conditional.scala 37:30] + wire _T_1910 = 15'h4008 == address; // @[Conditional.scala 37:30] + wire _T_1911 = 15'h400c == address; // @[Conditional.scala 37:30] + wire _T_1912 = 15'h4010 == address; // @[Conditional.scala 37:30] + wire _T_1913 = 15'h4014 == address; // @[Conditional.scala 37:30] + wire _T_1914 = 15'h4018 == address; // @[Conditional.scala 37:30] + wire _T_1915 = 15'h401c == address; // @[Conditional.scala 37:30] + wire _T_1916 = 15'h4020 == address; // @[Conditional.scala 37:30] + wire _T_1917 = 15'h4024 == address; // @[Conditional.scala 37:30] + wire _T_1918 = 15'h4028 == address; // @[Conditional.scala 37:30] + wire _T_1919 = 15'h402c == address; // @[Conditional.scala 37:30] + wire _T_1920 = 15'h4030 == address; // @[Conditional.scala 37:30] + wire _T_1921 = 15'h4034 == address; // @[Conditional.scala 37:30] + wire _T_1922 = 15'h4038 == address; // @[Conditional.scala 37:30] + wire _T_1923 = 15'h403c == address; // @[Conditional.scala 37:30] + wire _T_1924 = 15'h4040 == address; // @[Conditional.scala 37:30] + wire _T_1925 = 15'h4044 == address; // @[Conditional.scala 37:30] + wire _T_1926 = 15'h4048 == address; // @[Conditional.scala 37:30] + wire _T_1927 = 15'h404c == address; // @[Conditional.scala 37:30] + wire _T_1928 = 15'h4050 == address; // @[Conditional.scala 37:30] + wire _T_1929 = 15'h4054 == address; // @[Conditional.scala 37:30] + wire _T_1930 = 15'h4058 == address; // @[Conditional.scala 37:30] + wire _T_1931 = 15'h405c == address; // @[Conditional.scala 37:30] + wire _T_1932 = 15'h4060 == address; // @[Conditional.scala 37:30] + wire _T_1933 = 15'h4064 == address; // @[Conditional.scala 37:30] + wire _T_1934 = 15'h4068 == address; // @[Conditional.scala 37:30] + wire _T_1935 = 15'h406c == address; // @[Conditional.scala 37:30] + wire _T_1936 = 15'h4070 == address; // @[Conditional.scala 37:30] + wire _T_1937 = 15'h4074 == address; // @[Conditional.scala 37:30] + wire _T_1938 = 15'h4078 == address; // @[Conditional.scala 37:30] + wire _T_1939 = 15'h407c == address; // @[Conditional.scala 37:30] + wire _T_1940 = 15'h2004 == address; // @[Conditional.scala 37:30] + wire _T_1941 = 15'h2008 == address; // @[Conditional.scala 37:30] + wire _T_1942 = 15'h200c == address; // @[Conditional.scala 37:30] + wire _T_1943 = 15'h2010 == address; // @[Conditional.scala 37:30] + wire _T_1944 = 15'h2014 == address; // @[Conditional.scala 37:30] + wire _T_1945 = 15'h2018 == address; // @[Conditional.scala 37:30] + wire _T_1946 = 15'h201c == address; // @[Conditional.scala 37:30] + wire _T_1947 = 15'h2020 == address; // @[Conditional.scala 37:30] + wire _T_1948 = 15'h2024 == address; // @[Conditional.scala 37:30] + wire _T_1949 = 15'h2028 == address; // @[Conditional.scala 37:30] + wire _T_1950 = 15'h202c == address; // @[Conditional.scala 37:30] + wire _T_1951 = 15'h2030 == address; // @[Conditional.scala 37:30] + wire _T_1952 = 15'h2034 == address; // @[Conditional.scala 37:30] + wire _T_1953 = 15'h2038 == address; // @[Conditional.scala 37:30] + wire _T_1954 = 15'h203c == address; // @[Conditional.scala 37:30] + wire _T_1955 = 15'h2040 == address; // @[Conditional.scala 37:30] + wire _T_1956 = 15'h2044 == address; // @[Conditional.scala 37:30] + wire _T_1957 = 15'h2048 == address; // @[Conditional.scala 37:30] + wire _T_1958 = 15'h204c == address; // @[Conditional.scala 37:30] + wire _T_1959 = 15'h2050 == address; // @[Conditional.scala 37:30] + wire _T_1960 = 15'h2054 == address; // @[Conditional.scala 37:30] + wire _T_1961 = 15'h2058 == address; // @[Conditional.scala 37:30] + wire _T_1962 = 15'h205c == address; // @[Conditional.scala 37:30] + wire _T_1963 = 15'h2060 == address; // @[Conditional.scala 37:30] + wire _T_1964 = 15'h2064 == address; // @[Conditional.scala 37:30] + wire _T_1965 = 15'h2068 == address; // @[Conditional.scala 37:30] + wire _T_1966 = 15'h206c == address; // @[Conditional.scala 37:30] + wire _T_1967 = 15'h2070 == address; // @[Conditional.scala 37:30] + wire _T_1968 = 15'h2074 == address; // @[Conditional.scala 37:30] + wire _T_1969 = 15'h2078 == address; // @[Conditional.scala 37:30] + wire _T_1970 = 15'h207c == address; // @[Conditional.scala 37:30] + wire _T_1971 = 15'h4 == address; // @[Conditional.scala 37:30] + wire _T_1972 = 15'h8 == address; // @[Conditional.scala 37:30] + wire _T_1973 = 15'hc == address; // @[Conditional.scala 37:30] + wire _T_1974 = 15'h10 == address; // @[Conditional.scala 37:30] + wire _T_1975 = 15'h14 == address; // @[Conditional.scala 37:30] + wire _T_1976 = 15'h18 == address; // @[Conditional.scala 37:30] + wire _T_1977 = 15'h1c == address; // @[Conditional.scala 37:30] + wire _T_1978 = 15'h20 == address; // @[Conditional.scala 37:30] + wire _T_1979 = 15'h24 == address; // @[Conditional.scala 37:30] + wire _T_1980 = 15'h28 == address; // @[Conditional.scala 37:30] + wire _T_1981 = 15'h2c == address; // @[Conditional.scala 37:30] + wire _T_1982 = 15'h30 == address; // @[Conditional.scala 37:30] + wire _T_1983 = 15'h34 == address; // @[Conditional.scala 37:30] + wire _T_1984 = 15'h38 == address; // @[Conditional.scala 37:30] + wire _T_1985 = 15'h3c == address; // @[Conditional.scala 37:30] + wire _T_1986 = 15'h40 == address; // @[Conditional.scala 37:30] + wire _T_1987 = 15'h44 == address; // @[Conditional.scala 37:30] + wire _T_1988 = 15'h48 == address; // @[Conditional.scala 37:30] + wire _T_1989 = 15'h4c == address; // @[Conditional.scala 37:30] + wire _T_1990 = 15'h50 == address; // @[Conditional.scala 37:30] + wire _T_1991 = 15'h54 == address; // @[Conditional.scala 37:30] + wire _T_1992 = 15'h58 == address; // @[Conditional.scala 37:30] + wire _T_1993 = 15'h5c == address; // @[Conditional.scala 37:30] + wire _T_1994 = 15'h60 == address; // @[Conditional.scala 37:30] + wire _T_1995 = 15'h64 == address; // @[Conditional.scala 37:30] + wire _T_1996 = 15'h68 == address; // @[Conditional.scala 37:30] + wire _T_1997 = 15'h6c == address; // @[Conditional.scala 37:30] + wire _T_1998 = 15'h70 == address; // @[Conditional.scala 37:30] + wire _T_1999 = 15'h74 == address; // @[Conditional.scala 37:30] + wire _T_2000 = 15'h78 == address; // @[Conditional.scala 37:30] + wire _T_2001 = 15'h7c == address; // @[Conditional.scala 37:30] + wire [3:0] _GEN_126 = _T_2001 ? 4'h2 : 4'h1; // @[Conditional.scala 39:67] + wire [3:0] _GEN_127 = _T_2000 ? 4'h2 : _GEN_126; // @[Conditional.scala 39:67] + wire [3:0] _GEN_128 = _T_1999 ? 4'h2 : _GEN_127; // @[Conditional.scala 39:67] + wire [3:0] _GEN_129 = _T_1998 ? 4'h2 : _GEN_128; // @[Conditional.scala 39:67] + wire [3:0] _GEN_130 = _T_1997 ? 4'h2 : _GEN_129; // @[Conditional.scala 39:67] + wire [3:0] _GEN_131 = _T_1996 ? 4'h2 : _GEN_130; // @[Conditional.scala 39:67] + wire [3:0] _GEN_132 = _T_1995 ? 4'h2 : _GEN_131; // @[Conditional.scala 39:67] + wire [3:0] _GEN_133 = _T_1994 ? 4'h2 : _GEN_132; // @[Conditional.scala 39:67] + wire [3:0] _GEN_134 = _T_1993 ? 4'h2 : _GEN_133; // @[Conditional.scala 39:67] + wire [3:0] _GEN_135 = _T_1992 ? 4'h2 : _GEN_134; // @[Conditional.scala 39:67] + wire [3:0] _GEN_136 = _T_1991 ? 4'h2 : _GEN_135; // @[Conditional.scala 39:67] + wire [3:0] _GEN_137 = _T_1990 ? 4'h2 : _GEN_136; // @[Conditional.scala 39:67] + wire [3:0] _GEN_138 = _T_1989 ? 4'h2 : _GEN_137; // @[Conditional.scala 39:67] + wire [3:0] _GEN_139 = _T_1988 ? 4'h2 : _GEN_138; // @[Conditional.scala 39:67] + wire [3:0] _GEN_140 = _T_1987 ? 4'h2 : _GEN_139; // @[Conditional.scala 39:67] + wire [3:0] _GEN_141 = _T_1986 ? 4'h2 : _GEN_140; // @[Conditional.scala 39:67] + wire [3:0] _GEN_142 = _T_1985 ? 4'h2 : _GEN_141; // @[Conditional.scala 39:67] + wire [3:0] _GEN_143 = _T_1984 ? 4'h2 : _GEN_142; // @[Conditional.scala 39:67] + wire [3:0] _GEN_144 = _T_1983 ? 4'h2 : _GEN_143; // @[Conditional.scala 39:67] + wire [3:0] _GEN_145 = _T_1982 ? 4'h2 : _GEN_144; // @[Conditional.scala 39:67] + wire [3:0] _GEN_146 = _T_1981 ? 4'h2 : _GEN_145; // @[Conditional.scala 39:67] + wire [3:0] _GEN_147 = _T_1980 ? 4'h2 : _GEN_146; // @[Conditional.scala 39:67] + wire [3:0] _GEN_148 = _T_1979 ? 4'h2 : _GEN_147; // @[Conditional.scala 39:67] + wire [3:0] _GEN_149 = _T_1978 ? 4'h2 : _GEN_148; // @[Conditional.scala 39:67] + wire [3:0] _GEN_150 = _T_1977 ? 4'h2 : _GEN_149; // @[Conditional.scala 39:67] + wire [3:0] _GEN_151 = _T_1976 ? 4'h2 : _GEN_150; // @[Conditional.scala 39:67] + wire [3:0] _GEN_152 = _T_1975 ? 4'h2 : _GEN_151; // @[Conditional.scala 39:67] + wire [3:0] _GEN_153 = _T_1974 ? 4'h2 : _GEN_152; // @[Conditional.scala 39:67] + wire [3:0] _GEN_154 = _T_1973 ? 4'h2 : _GEN_153; // @[Conditional.scala 39:67] + wire [3:0] _GEN_155 = _T_1972 ? 4'h2 : _GEN_154; // @[Conditional.scala 39:67] + wire [3:0] _GEN_156 = _T_1971 ? 4'h2 : _GEN_155; // @[Conditional.scala 39:67] + wire [3:0] _GEN_157 = _T_1970 ? 4'h4 : _GEN_156; // @[Conditional.scala 39:67] + wire [3:0] _GEN_158 = _T_1969 ? 4'h4 : _GEN_157; // @[Conditional.scala 39:67] + wire [3:0] _GEN_159 = _T_1968 ? 4'h4 : _GEN_158; // @[Conditional.scala 39:67] + wire [3:0] _GEN_160 = _T_1967 ? 4'h4 : _GEN_159; // @[Conditional.scala 39:67] + wire [3:0] _GEN_161 = _T_1966 ? 4'h4 : _GEN_160; // @[Conditional.scala 39:67] + wire [3:0] _GEN_162 = _T_1965 ? 4'h4 : _GEN_161; // @[Conditional.scala 39:67] + wire [3:0] _GEN_163 = _T_1964 ? 4'h4 : _GEN_162; // @[Conditional.scala 39:67] + wire [3:0] _GEN_164 = _T_1963 ? 4'h4 : _GEN_163; // @[Conditional.scala 39:67] + wire [3:0] _GEN_165 = _T_1962 ? 4'h4 : _GEN_164; // @[Conditional.scala 39:67] + wire [3:0] _GEN_166 = _T_1961 ? 4'h4 : _GEN_165; // @[Conditional.scala 39:67] + wire [3:0] _GEN_167 = _T_1960 ? 4'h4 : _GEN_166; // @[Conditional.scala 39:67] + wire [3:0] _GEN_168 = _T_1959 ? 4'h4 : _GEN_167; // @[Conditional.scala 39:67] + wire [3:0] _GEN_169 = _T_1958 ? 4'h4 : _GEN_168; // @[Conditional.scala 39:67] + wire [3:0] _GEN_170 = _T_1957 ? 4'h4 : _GEN_169; // @[Conditional.scala 39:67] + wire [3:0] _GEN_171 = _T_1956 ? 4'h4 : _GEN_170; // @[Conditional.scala 39:67] + wire [3:0] _GEN_172 = _T_1955 ? 4'h4 : _GEN_171; // @[Conditional.scala 39:67] + wire [3:0] _GEN_173 = _T_1954 ? 4'h4 : _GEN_172; // @[Conditional.scala 39:67] + wire [3:0] _GEN_174 = _T_1953 ? 4'h4 : _GEN_173; // @[Conditional.scala 39:67] + wire [3:0] _GEN_175 = _T_1952 ? 4'h4 : _GEN_174; // @[Conditional.scala 39:67] + wire [3:0] _GEN_176 = _T_1951 ? 4'h4 : _GEN_175; // @[Conditional.scala 39:67] + wire [3:0] _GEN_177 = _T_1950 ? 4'h4 : _GEN_176; // @[Conditional.scala 39:67] + wire [3:0] _GEN_178 = _T_1949 ? 4'h4 : _GEN_177; // @[Conditional.scala 39:67] + wire [3:0] _GEN_179 = _T_1948 ? 4'h4 : _GEN_178; // @[Conditional.scala 39:67] + wire [3:0] _GEN_180 = _T_1947 ? 4'h4 : _GEN_179; // @[Conditional.scala 39:67] + wire [3:0] _GEN_181 = _T_1946 ? 4'h4 : _GEN_180; // @[Conditional.scala 39:67] + wire [3:0] _GEN_182 = _T_1945 ? 4'h4 : _GEN_181; // @[Conditional.scala 39:67] + wire [3:0] _GEN_183 = _T_1944 ? 4'h4 : _GEN_182; // @[Conditional.scala 39:67] + wire [3:0] _GEN_184 = _T_1943 ? 4'h4 : _GEN_183; // @[Conditional.scala 39:67] + wire [3:0] _GEN_185 = _T_1942 ? 4'h4 : _GEN_184; // @[Conditional.scala 39:67] + wire [3:0] _GEN_186 = _T_1941 ? 4'h4 : _GEN_185; // @[Conditional.scala 39:67] + wire [3:0] _GEN_187 = _T_1940 ? 4'h4 : _GEN_186; // @[Conditional.scala 39:67] + wire [3:0] _GEN_188 = _T_1939 ? 4'h8 : _GEN_187; // @[Conditional.scala 39:67] + wire [3:0] _GEN_189 = _T_1938 ? 4'h8 : _GEN_188; // @[Conditional.scala 39:67] + wire [3:0] _GEN_190 = _T_1937 ? 4'h8 : _GEN_189; // @[Conditional.scala 39:67] + wire [3:0] _GEN_191 = _T_1936 ? 4'h8 : _GEN_190; // @[Conditional.scala 39:67] + wire [3:0] _GEN_192 = _T_1935 ? 4'h8 : _GEN_191; // @[Conditional.scala 39:67] + wire [3:0] _GEN_193 = _T_1934 ? 4'h8 : _GEN_192; // @[Conditional.scala 39:67] + wire [3:0] _GEN_194 = _T_1933 ? 4'h8 : _GEN_193; // @[Conditional.scala 39:67] + wire [3:0] _GEN_195 = _T_1932 ? 4'h8 : _GEN_194; // @[Conditional.scala 39:67] + wire [3:0] _GEN_196 = _T_1931 ? 4'h8 : _GEN_195; // @[Conditional.scala 39:67] + wire [3:0] _GEN_197 = _T_1930 ? 4'h8 : _GEN_196; // @[Conditional.scala 39:67] + wire [3:0] _GEN_198 = _T_1929 ? 4'h8 : _GEN_197; // @[Conditional.scala 39:67] + wire [3:0] _GEN_199 = _T_1928 ? 4'h8 : _GEN_198; // @[Conditional.scala 39:67] + wire [3:0] _GEN_200 = _T_1927 ? 4'h8 : _GEN_199; // @[Conditional.scala 39:67] + wire [3:0] _GEN_201 = _T_1926 ? 4'h8 : _GEN_200; // @[Conditional.scala 39:67] + wire [3:0] _GEN_202 = _T_1925 ? 4'h8 : _GEN_201; // @[Conditional.scala 39:67] + wire [3:0] _GEN_203 = _T_1924 ? 4'h8 : _GEN_202; // @[Conditional.scala 39:67] + wire [3:0] _GEN_204 = _T_1923 ? 4'h8 : _GEN_203; // @[Conditional.scala 39:67] + wire [3:0] _GEN_205 = _T_1922 ? 4'h8 : _GEN_204; // @[Conditional.scala 39:67] + wire [3:0] _GEN_206 = _T_1921 ? 4'h8 : _GEN_205; // @[Conditional.scala 39:67] + wire [3:0] _GEN_207 = _T_1920 ? 4'h8 : _GEN_206; // @[Conditional.scala 39:67] + wire [3:0] _GEN_208 = _T_1919 ? 4'h8 : _GEN_207; // @[Conditional.scala 39:67] + wire [3:0] _GEN_209 = _T_1918 ? 4'h8 : _GEN_208; // @[Conditional.scala 39:67] + wire [3:0] _GEN_210 = _T_1917 ? 4'h8 : _GEN_209; // @[Conditional.scala 39:67] + wire [3:0] _GEN_211 = _T_1916 ? 4'h8 : _GEN_210; // @[Conditional.scala 39:67] + wire [3:0] _GEN_212 = _T_1915 ? 4'h8 : _GEN_211; // @[Conditional.scala 39:67] + wire [3:0] _GEN_213 = _T_1914 ? 4'h8 : _GEN_212; // @[Conditional.scala 39:67] + wire [3:0] _GEN_214 = _T_1913 ? 4'h8 : _GEN_213; // @[Conditional.scala 39:67] + wire [3:0] _GEN_215 = _T_1912 ? 4'h8 : _GEN_214; // @[Conditional.scala 39:67] + wire [3:0] _GEN_216 = _T_1911 ? 4'h8 : _GEN_215; // @[Conditional.scala 39:67] + wire [3:0] _GEN_217 = _T_1910 ? 4'h8 : _GEN_216; // @[Conditional.scala 39:67] + wire [3:0] _GEN_218 = _T_1909 ? 4'h8 : _GEN_217; // @[Conditional.scala 39:67] + wire [3:0] mask = _T_1908 ? 4'h4 : _GEN_218; // @[Conditional.scala 40:58] + wire _T_1870 = picm_mken_ff & mask[3]; // @[el2_pic_ctl.scala 305:19] + wire _T_1875 = picm_mken_ff & mask[2]; // @[el2_pic_ctl.scala 306:19] + wire _T_1880 = picm_mken_ff & mask[1]; // @[el2_pic_ctl.scala 307:19] + wire [31:0] _T_1888 = intpend_reg_read ? intpend_rd_out : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1889 = _T_21 ? _T_1859 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1890 = _T_24 ? _T_1862 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1891 = _T_27 ? _T_1865 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1892 = config_reg_re ? _T_1868 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1893 = _T_1870 ? 32'h3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1894 = _T_1875 ? 32'h1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1895 = _T_1880 ? 32'hf : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1897 = _T_1888 | _T_1889; // @[Mux.scala 27:72] + wire [31:0] _T_1898 = _T_1897 | _T_1890; // @[Mux.scala 27:72] + wire [31:0] _T_1899 = _T_1898 | _T_1891; // @[Mux.scala 27:72] + wire [31:0] _T_1900 = _T_1899 | _T_1892; // @[Mux.scala 27:72] + wire [31:0] _T_1901 = _T_1900 | _T_1893; // @[Mux.scala 27:72] + wire [31:0] _T_1902 = _T_1901 | _T_1894; // @[Mux.scala 27:72] + wire [31:0] picm_rd_data_in = _T_1902 | _T_1895; // @[Mux.scala 27:72] + wire [7:0] level_intpend_id_5_0 = out_id_34; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43] + wire [7:0] level_intpend_id_1_18 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_1_19 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_1_20 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_1_21 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_1_22 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_1_23 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_1_24 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_1_25 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_1_26 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_1_27 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_1_28 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_1_29 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_1_30 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_1_31 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_1_32 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_1_33 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_2_10 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_2_11 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_2_12 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_2_13 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_2_14 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_2_15 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_2_16 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_2_17 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_2_18 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_2_19 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_2_20 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_2_21 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_2_22 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_2_23 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_2_24 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_2_25 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_2_26 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_2_27 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_2_28 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_2_29 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_2_30 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_2_31 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_2_32 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_2_33 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_3_6 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_3_7 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_3_8 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_3_9 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_3_10 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_3_11 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_3_12 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_3_13 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_3_14 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_3_15 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_3_16 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_3_17 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_3_18 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_3_19 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_3_20 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_3_21 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_3_22 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_3_23 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_3_24 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_3_25 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_3_26 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_3_27 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_3_28 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_3_29 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_3_30 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_3_31 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_3_32 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_3_33 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_4_4 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_4_5 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_4_6 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_4_7 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_4_8 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_4_9 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_4_10 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_4_11 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_4_12 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_4_13 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_4_14 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_4_15 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_4_16 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_4_17 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_4_18 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_4_19 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_4_20 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_4_21 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_4_22 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_4_23 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_4_24 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_4_25 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_4_26 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_4_27 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_4_28 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_4_29 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_4_30 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_4_31 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_4_32 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_4_33 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_5_1 = out_id_33; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 238:43] + wire [7:0] level_intpend_id_5_2 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30 el2_pic_ctl.scala 235:46] + wire [7:0] level_intpend_id_5_3 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_5_4 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_5_5 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_5_6 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_5_7 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_5_8 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_5_9 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_5_10 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_5_11 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_5_12 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_5_13 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_5_14 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_5_15 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_5_16 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_5_17 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_5_18 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_5_19 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_5_20 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_5_21 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_5_22 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_5_23 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_5_24 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_5_25 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_5_26 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_5_27 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_5_28 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_5_29 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_5_30 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_5_31 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_5_32 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] + wire [7:0] level_intpend_id_5_33 = 8'h0; // @[el2_pic_ctl.scala 220:32 el2_pic_ctl.scala 224:30] rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), @@ -1878,11 +1846,11 @@ module el2_pic_ctrl( .io_en(rvclkhdr_4_io_en), .io_scan_mode(rvclkhdr_4_io_scan_mode) ); - assign io_mexintpend = _T_1722; // @[el2_pic_ctl.scala 281:17] - assign io_claimid = _T_1714; // @[el2_pic_ctl.scala 276:37] - assign io_pl = _T_1715; // @[el2_pic_ctl.scala 277:32] - assign io_picm_rd_data = picm_bypass_ff ? picm_wr_data_ff : picm_rd_data_in; // @[el2_pic_ctl.scala 319:19] - assign io_mhwakeup = _T_1724; // @[el2_pic_ctl.scala 284:15] + assign io_mexintpend = _T_1650; // @[el2_pic_ctl.scala 273:17] + assign io_claimid = _T_1642; // @[el2_pic_ctl.scala 268:37] + assign io_pl = _T_1643; // @[el2_pic_ctl.scala 269:32] + assign io_picm_rd_data = picm_bypass_ff ? picm_wr_data_ff : picm_rd_data_in; // @[el2_pic_ctl.scala 311:19] + assign io_mhwakeup = _T_1652; // @[el2_pic_ctl.scala 276:15] assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 484:17] assign rvclkhdr_io_en = _T_19 | io_clk_override; // @[el2_lib.scala 485:16] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] @@ -2200,13 +2168,13 @@ initial begin _RAND_132 = {1{`RANDOM}}; config_reg = _RAND_132[0:0]; _RAND_133 = {1{`RANDOM}}; - _T_1714 = _RAND_133[7:0]; + _T_1642 = _RAND_133[7:0]; _RAND_134 = {1{`RANDOM}}; - _T_1715 = _RAND_134[3:0]; + _T_1643 = _RAND_134[3:0]; _RAND_135 = {1{`RANDOM}}; - _T_1722 = _RAND_135[0:0]; + _T_1650 = _RAND_135[0:0]; _RAND_136 = {1{`RANDOM}}; - _T_1724 = _RAND_136[0:0]; + _T_1652 = _RAND_136[0:0]; `endif // RANDOMIZE_REG_INIT if (reset) begin picm_raddr_ff = 32'h0; @@ -2608,16 +2576,16 @@ initial begin config_reg = 1'h0; end if (reset) begin - _T_1714 = 8'h0; + _T_1642 = 8'h0; end if (reset) begin - _T_1715 = 4'h0; + _T_1643 = 4'h0; end if (reset) begin - _T_1722 = 1'h0; + _T_1650 = 1'h0; end if (reset) begin - _T_1724 = 1'h0; + _T_1652 = 1'h0; end `endif // RANDOMIZE end // initial @@ -3558,32 +3526,32 @@ end // initial end always @(posedge io_free_clk or posedge reset) begin if (reset) begin - _T_1714 <= 8'h0; + _T_1642 <= 8'h0; end else begin - _T_1714 <= _T_1703; + _T_1642 <= level_intpend_id_5_0; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin - _T_1715 <= 4'h0; + _T_1643 <= 4'h0; end else if (config_reg) begin - _T_1715 <= _T_1713; + _T_1643 <= _T_1641; end else begin - _T_1715 <= _T_1705; + _T_1643 <= level_intpend_w_prior_en_5_0; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin - _T_1722 <= 1'h0; + _T_1650 <= 1'h0; end else begin - _T_1722 <= _T_1720 & _T_1721; + _T_1650 <= _T_1648 & _T_1649; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin - _T_1724 <= 1'h0; + _T_1652 <= 1'h0; end else begin - _T_1724 <= pl_in_q == maxint; + _T_1652 <= pl_in_q == maxint; end end endmodule diff --git a/firrtl_black_box_resource_files.f b/firrtl_black_box_resource_files.f index bde2aec4..4ec29fe7 100644 --- a/firrtl_black_box_resource_files.f +++ b/firrtl_black_box_resource_files.f @@ -1,3 +1 @@ -/home/laraibkhan/Desktop/SweRV-Chislified/gated_latch.v -/home/laraibkhan/Desktop/SweRV-Chislified/dmi_wrapper.sv -/home/laraibkhan/Desktop/SweRV-Chislified/el2_mem.sv \ No newline at end of file +/home/laraibkhan/Desktop/SweRV-Chislified/gated_latch.v \ No newline at end of file diff --git a/project/target/config-classes/$ec5cdbc4a1416f284ecb$.class b/project/target/config-classes/$802a15ecf65c09cee93d$.class similarity index 92% rename from project/target/config-classes/$ec5cdbc4a1416f284ecb$.class rename to project/target/config-classes/$802a15ecf65c09cee93d$.class index 3db3c4f8..3c62c76b 100644 Binary files a/project/target/config-classes/$ec5cdbc4a1416f284ecb$.class and b/project/target/config-classes/$802a15ecf65c09cee93d$.class differ diff --git a/project/target/config-classes/$ec5cdbc4a1416f284ecb.cache b/project/target/config-classes/$802a15ecf65c09cee93d.cache similarity index 100% rename from project/target/config-classes/$ec5cdbc4a1416f284ecb.cache rename to project/target/config-classes/$802a15ecf65c09cee93d.cache diff --git a/project/target/config-classes/$802a15ecf65c09cee93d.class b/project/target/config-classes/$802a15ecf65c09cee93d.class new file mode 100644 index 00000000..fef0c79d Binary files /dev/null and b/project/target/config-classes/$802a15ecf65c09cee93d.class differ diff --git a/project/target/config-classes/$ec5cdbc4a1416f284ecb.class b/project/target/config-classes/$ec5cdbc4a1416f284ecb.class deleted file mode 100644 index bfafb971..00000000 Binary files a/project/target/config-classes/$ec5cdbc4a1416f284ecb.class and /dev/null differ diff --git a/src/main/scala/dbg/el2_dbg.scala b/src/main/scala/dbg/el2_dbg.scala index f6d0e100..b7137c29 100644 --- a/src/main/scala/dbg/el2_dbg.scala +++ b/src/main/scala/dbg/el2_dbg.scala @@ -89,7 +89,7 @@ class el2_dbg extends Module with el2_lib with RequireAsyncReset { val sb_axi_rdata = Input(UInt(64.W)) val sb_axi_rresp = Input(UInt(2.W)) val dbg_bus_clk_en = Input(Bool()) - val dbg_rst_l = Input(Bool()) + val dbg_rst_l = Input(AsyncReset()) val clk_override = Input(Bool()) val scan_mode = Input(Bool()) }) @@ -127,30 +127,30 @@ class el2_dbg extends Module with el2_lib with RequireAsyncReset { val sb_free_clken = io.dmi_reg_en | sb_state_en | (sb_state =/= sb_state_t.sbidle) | io.clk_override; val dbg_free_clk = rvclkhdr(clock, dbg_free_clken, io.scan_mode) // dbg_free_cgc val sb_free_clk = rvclkhdr(clock, sb_free_clken, io.scan_mode) // sb_free_cgc - val dbg_dm_rst_l = io.dbg_rst_l.asBool() & (dmcontrol_reg(0) | io.scan_mode) + val dbg_dm_rst_l = (io.dbg_rst_l.asBool() & (dmcontrol_reg(0) | io.scan_mode)).asAsyncReset() io.dbg_core_rst_l := (!dmcontrol_reg(1)).asBool() val sbcs_wren = (io.dmi_reg_addr === "h38".U) & io.dmi_reg_en & io.dmi_reg_wr_en & (sb_state === sb_state_t.sbidle) val sbcs_sbbusyerror_wren = (sbcs_wren & io.dmi_reg_wdata(22)) | ((sb_state =/= sb_state_t.sbidle) & io.dmi_reg_en & ((io.dmi_reg_addr === "h39".U) | (io.dmi_reg_addr === "h3c".U) | (io.dmi_reg_addr === "h3d".U))) val sbcs_sbbusyerror_din = (~(sbcs_wren & io.dmi_reg_wdata(22))).asUInt() - val temp_sbcs_22 = withClockAndReset(sb_free_clk, !dbg_dm_rst_l) { + val temp_sbcs_22 = withClockAndReset(sb_free_clk, (!dbg_dm_rst_l.asBool()).asAsyncReset()) { RegEnable(sbcs_sbbusyerror_din, 0.U, sbcs_sbbusyerror_wren) } // sbcs_sbbusyerror_reg - val temp_sbcs_21 = withClockAndReset(sb_free_clk, !dbg_dm_rst_l) { + val temp_sbcs_21 = withClockAndReset(sb_free_clk, (!dbg_dm_rst_l.asBool()).asAsyncReset()) { RegEnable(sbcs_sbbusy_din, 0.U, sbcs_sbbusy_wren) } // sbcs_sbbusy_reg - val temp_sbcs_20 = withClockAndReset(sb_free_clk, !dbg_dm_rst_l) { + val temp_sbcs_20 = withClockAndReset(sb_free_clk, (!dbg_dm_rst_l.asBool()).asAsyncReset()) { RegEnable(io.dmi_reg_wdata(20), 0.U, sbcs_wren) } // sbcs_sbreadonaddr_reg - val temp_sbcs_19_15 = withClockAndReset(sb_free_clk, !dbg_dm_rst_l) { + val temp_sbcs_19_15 = withClockAndReset(sb_free_clk, (!dbg_dm_rst_l.asBool()).asAsyncReset()) { RegEnable(io.dmi_reg_wdata(19, 15), 0.U, sbcs_wren) } // sbcs_misc_reg - val temp_sbcs_14_12 = withClockAndReset(sb_free_clk, !dbg_dm_rst_l) { + val temp_sbcs_14_12 = withClockAndReset(sb_free_clk, (!dbg_dm_rst_l.asBool()).asAsyncReset()) { RegEnable(sbcs_sberror_din(2, 0), 0.U, sbcs_sberror_wren) } // sbcs_error_reg sbcs_reg := Cat(1.U(3.W), 0.U(6.W), temp_sbcs_22, temp_sbcs_21, temp_sbcs_20, temp_sbcs_19_15, temp_sbcs_14_12, "h20".U(7.W), "b01111".U(5.W)) @@ -175,11 +175,11 @@ class el2_dbg extends Module with el2_lib with RequireAsyncReset { val sbdata1_din = Fill(32, sbdata1_reg_wren0) & io.dmi_reg_wdata | Fill(32, sbdata1_reg_wren1) & sb_bus_rdata(63, 32) - val sbdata0_reg = withReset(!dbg_dm_rst_l) { + val sbdata0_reg = withReset((!dbg_dm_rst_l.asBool()).asAsyncReset()) { rvdffe(sbdata0_din, sbdata0_reg_wren, clock, io.scan_mode) } // dbg_sbdata0_reg - val sbdata1_reg = withReset(!dbg_dm_rst_l) { + val sbdata1_reg = withReset((!dbg_dm_rst_l.asBool()).asAsyncReset()) { rvdffe(sbdata1_din, sbdata1_reg_wren, clock, io.scan_mode) } // dbg_sbdata1_reg @@ -187,7 +187,7 @@ class el2_dbg extends Module with el2_lib with RequireAsyncReset { val sbaddress0_reg_wren = sbaddress0_reg_wren0 | sbaddress0_reg_wren1 val sbaddress0_reg_din = Fill(32, sbaddress0_reg_wren0) & io.dmi_reg_wdata | Fill(32, sbaddress0_reg_wren1) & (sbaddress0_reg + Cat(0.U(28.W), sbaddress0_incr)) - sbaddress0_reg := withReset(!dbg_dm_rst_l) { + sbaddress0_reg := withReset((!dbg_dm_rst_l.asBool()).asAsyncReset()) { rvdffe(sbaddress0_reg_din, sbaddress0_reg_wren, clock, io.scan_mode) } // dbg_sbaddress0_reg @@ -195,7 +195,7 @@ class el2_dbg extends Module with el2_lib with RequireAsyncReset { val sbreadondata_access = io.dmi_reg_en & !io.dmi_reg_wr_en & (io.dmi_reg_addr === "h3c".U) & sbcs_reg(15) val sbdata0wr_access = io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h3c".U) val dmcontrol_wren = (io.dmi_reg_addr === "h10".U) & io.dmi_reg_en & io.dmi_reg_wr_en - val dm_temp = withClockAndReset(dbg_free_clk, !dbg_dm_rst_l) { + val dm_temp = withClockAndReset(dbg_free_clk, (!dbg_dm_rst_l.asBool()).asAsyncReset()) { RegEnable( Cat(io.dmi_reg_wdata(31, 30), io.dmi_reg_wdata(28), io.dmi_reg_wdata(1)), 0.U, dmcontrol_wren) @@ -208,7 +208,7 @@ class el2_dbg extends Module with el2_lib with RequireAsyncReset { val temp = Cat(dm_temp(3, 2), 0.U, dm_temp(1), 0.U(26.W), dm_temp(0), dm_temp_0) dmcontrol_reg := temp - val dmcontrol_wren_Q = withClockAndReset(dbg_free_clk, !dbg_dm_rst_l) { + val dmcontrol_wren_Q = withClockAndReset(dbg_free_clk, (!dbg_dm_rst_l.asBool()).asAsyncReset()) { RegNext(dmcontrol_wren, 0.U) } // dmcontrol_wrenff @@ -221,15 +221,15 @@ class el2_dbg extends Module with el2_lib with RequireAsyncReset { val temp_rst = reset.asBool() dmstatus_unavail := (dmcontrol_reg(1) | !(temp_rst)).asBool() dmstatus_running := ~(dmstatus_unavail | dmstatus_halted) - dmstatus_resumeack := withClockAndReset(dbg_free_clk, !dbg_dm_rst_l) { + dmstatus_resumeack := withClockAndReset(dbg_free_clk, (!dbg_dm_rst_l.asBool()).asAsyncReset()) { RegEnable(dmstatus_resumeack_din, 0.U, dmstatus_resumeack_wren) } // dmstatus_resumeack_reg - dmstatus_halted := withClockAndReset(dbg_free_clk, !dbg_dm_rst_l) { + dmstatus_halted := withClockAndReset(dbg_free_clk, (!dbg_dm_rst_l.asBool()).asAsyncReset()) { RegNext(io.dec_tlu_dbg_halted & !io.dec_tlu_mpc_halted_only, 0.U) } // dmstatus_halted_reg - dmstatus_havereset := withClockAndReset(dbg_free_clk, !dbg_dm_rst_l) { + dmstatus_havereset := withClockAndReset(dbg_free_clk, (!dbg_dm_rst_l.asBool()).asAsyncReset()) { RegEnable(~dmstatus_havereset_rst, 0.U, dmstatus_havereset_wren) } // dmstatus_havereset_reg @@ -253,11 +253,11 @@ class el2_dbg extends Module with el2_lib with RequireAsyncReset { (Fill(3, abstractcs_error_sel5) & (~io.dmi_reg_wdata(10, 8)).asUInt() & abstractcs_reg(10, 8)) | (Fill(3, (~abstractcs_error_selor).asUInt()) & abstractcs_reg(10, 8)) - val abs_temp_12 = withClockAndReset(dbg_free_clk, !dbg_dm_rst_l) { + val abs_temp_12 = withClockAndReset(dbg_free_clk, (!dbg_dm_rst_l.asBool()).asAsyncReset()) { RegEnable(abstractcs_busy_din, 0.U, abstractcs_busy_wren) } // dmabstractcs_busy_reg - val abs_temp_10_8 = withClockAndReset(dbg_free_clk, !dbg_dm_rst_l) { + val abs_temp_10_8 = withClockAndReset(dbg_free_clk, (!dbg_dm_rst_l.asBool()).asAsyncReset()) { RegNext(abstractcs_error_din(2, 0), 0.U) } // dmabstractcs_error_reg @@ -265,8 +265,8 @@ class el2_dbg extends Module with el2_lib with RequireAsyncReset { val command_wren = (io.dmi_reg_addr === "h17".U) & io.dmi_reg_en & io.dmi_reg_wr_en & (dbg_state === state_t.halted) val command_din = Cat(io.dmi_reg_wdata(31, 24), 0.U(1.W), io.dmi_reg_wdata(22, 20), 0.U(3.W), io.dmi_reg_wdata(16, 0)) - val command_reg = withReset(!dbg_dm_rst_l) { - RegEnable(command_din, 0.U, command_wren) + val command_reg = withReset((!dbg_dm_rst_l.asBool()).asAsyncReset()) { + rvdffe(command_din, command_wren, clock, io.scan_mode) } // dmcommand_reg val data0_reg_wren0 = io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h4".U) & (dbg_state === state_t.halted) @@ -274,13 +274,13 @@ class el2_dbg extends Module with el2_lib with RequireAsyncReset { val data0_reg_wren = data0_reg_wren0 | data0_reg_wren1 val data0_din = Fill(32, data0_reg_wren0) & io.dmi_reg_wdata | Fill(32, data0_reg_wren1) & io.core_dbg_rddata - val data0_reg = withReset(!dbg_dm_rst_l) { - RegEnable(data0_din, 0.U, data0_reg_wren) + val data0_reg = withReset((!dbg_dm_rst_l.asBool()).asAsyncReset()) { + rvdffe(data0_din, data0_reg_wren, clock, io.scan_mode) } // dbg_data0_reg val data1_reg_wren = (io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h5".U) & (dbg_state === state_t.halted)) val data1_din = Fill(32, data1_reg_wren) & io.dmi_reg_wdata - data1_reg := withReset(!dbg_dm_rst_l) { + data1_reg := withReset((!dbg_dm_rst_l.asBool()).asAsyncReset()) { rvdffe(data1_din, data1_reg_wren, clock, io.scan_mode) } // dbg_data1_reg @@ -343,12 +343,12 @@ class el2_dbg extends Module with el2_lib with RequireAsyncReset { Fill(32, io.dmi_reg_addr === "h39".U) & sbaddress0_reg | Fill(32, io.dmi_reg_addr === "h3c".U) & sbdata0_reg | Fill(32, io.dmi_reg_addr === "h3d".U) & sbdata1_reg - dbg_state := withClockAndReset(dbg_free_clk, !dbg_dm_rst_l & temp_rst) { + dbg_state := withClockAndReset(dbg_free_clk, (!dbg_dm_rst_l.asBool() & temp_rst).asAsyncReset()) { RegEnable(dbg_nxtstate, 0.U, dbg_state_en) } // dbg_state_reg - io.dmi_reg_rdata := withClockAndReset(dbg_free_clk, !dbg_dm_rst_l) { + io.dmi_reg_rdata := withClockAndReset(dbg_free_clk, (!dbg_dm_rst_l.asBool()).asAsyncReset()) { RegEnable(dmi_reg_rdata_din, 0.U, io.dmi_reg_en) } // dmi_rddata_reg @@ -425,7 +425,7 @@ class el2_dbg extends Module with el2_lib with RequireAsyncReset { sbaddress0_reg_wren1 := sbcs_reg(16) }} - sb_state := withClockAndReset(sb_free_clk, !dbg_dm_rst_l) { + sb_state := withClockAndReset(sb_free_clk, (!dbg_dm_rst_l.asBool()).asAsyncReset()) { RegEnable(sb_nxtstate, 0.U, sb_state_en) } // sb_state_reg @@ -476,5 +476,5 @@ class el2_dbg extends Module with el2_lib with RequireAsyncReset { } object debug extends App { - chisel3.Driver.emitVerilog(new el2_dbg) + println(chisel3.Driver.emitVerilog(new el2_dbg)) } \ No newline at end of file diff --git a/src/main/scala/dec/el2_dec_decode_ctl.scala b/src/main/scala/dec/el2_dec_decode_ctl.scala index 51ea176d..1ec20e5c 100644 --- a/src/main/scala/dec/el2_dec_decode_ctl.scala +++ b/src/main/scala/dec/el2_dec_decode_ctl.scala @@ -821,5 +821,5 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{ } object dec_decode extends App{ - chisel3.Driver.emitVerilog(new el2_dec_decode_ctl) + println(chisel3.Driver.emitVerilog(new el2_dec_decode_ctl)) } diff --git a/src/main/scala/dec/el2_dec_ib_ctl.scala b/src/main/scala/dec/el2_dec_ib_ctl.scala index 180e4493..ce739543 100644 --- a/src/main/scala/dec/el2_dec_ib_ctl.scala +++ b/src/main/scala/dec/el2_dec_ib_ctl.scala @@ -92,5 +92,5 @@ class el2_dec_ib_ctl_IO extends Bundle with param{ val dec_debug_fence_d =Output(UInt(1.W)) // debug fence inst } object ib_gen extends App{ - chisel3.Driver.emitVerilog(new el2_dec_ib_ctl) + println(chisel3.Driver.emitVerilog(new el2_dec_ib_ctl)) } diff --git a/src/main/scala/dec/el2_dec_trigger.scala b/src/main/scala/dec/el2_dec_trigger.scala index 72cb224f..6bdeb63a 100644 --- a/src/main/scala/dec/el2_dec_trigger.scala +++ b/src/main/scala/dec/el2_dec_trigger.scala @@ -16,5 +16,5 @@ class el2_dec_trigger extends Module with el2_lib { } object dec_trig extends App { - chisel3.Driver execute(args, () => new el2_dec_trigger()) + println(chisel3.Driver.emitVerilog(new el2_dec_trigger)) } diff --git a/src/main/scala/el2_dma_ctrl.scala b/src/main/scala/el2_dma_ctrl.scala index e4a5283e..9b41cc3c 100644 --- a/src/main/scala/el2_dma_ctrl.scala +++ b/src/main/scala/el2_dma_ctrl.scala @@ -10,7 +10,7 @@ class el2_dma_ctrl extends Module with el2_lib with RequireAsyncReset { val clk_override = Input(Bool()) val scan_mode = Input(Bool()) - // Debug signals + // Debug signals val dbg_cmd_addr = Input(UInt(32.W)) val dbg_cmd_wrdata = Input(UInt(32.W)) val dbg_cmd_valid = Input(Bool()) @@ -24,7 +24,7 @@ class el2_dma_ctrl extends Module with el2_lib with RequireAsyncReset { val dma_dbg_cmd_fail = Output(Bool()) val dma_dbg_rddata = Output(UInt(32.W)) - // Core side signals + // Core side signals val dma_dccm_req = Output(Bool()) // DMA dccm request (only one of dccm/iccm will be set) val dma_iccm_req = Output(Bool()) // DMA iccm request val dma_mem_tag = Output(UInt(3.W)) // DMA Buffer entry number @@ -552,5 +552,5 @@ class el2_dma_ctrl extends Module with el2_lib with RequireAsyncReset { bus_rsp_sent := ((io.dma_axi_bvalid & io.dma_axi_bready) | (io.dma_axi_rvalid & io.dma_axi_rready)) } object dma extends App{ - chisel3.Driver.emitVerilog(new el2_dma_ctrl) + println(chisel3.Driver.emitVerilog(new el2_dma_ctrl)) } \ No newline at end of file diff --git a/src/main/scala/ifu/el2_ifu_mem_ctl.scala b/src/main/scala/ifu/el2_ifu_mem_ctl.scala index 2a66d22d..704f2b2e 100644 --- a/src/main/scala/ifu/el2_ifu_mem_ctl.scala +++ b/src/main/scala/ifu/el2_ifu_mem_ctl.scala @@ -130,7 +130,7 @@ class mem_ctl_bundle extends Bundle with el2_lib{ val scan_mode = Input(Bool()) } -class el2_ifu_mem_ctl extends Module with el2_lib { +class el2_ifu_mem_ctl extends Module with el2_lib with RequireAsyncReset { val io = IO(new mem_ctl_bundle) io.ifu_axi_wvalid := 0.U io.ifu_axi_wdata := 0.U @@ -178,13 +178,12 @@ class el2_ifu_mem_ctl extends Module with el2_lib { val bus_ifu_wr_en_ff = WireInit(Bool(), false.B) val last_beat = WireInit(Bool(), false.B) val last_data_recieved_ff = WireInit(Bool(), false.B) - //val flush_final_f = WireInit(Bool(), 0.U) val stream_eol_f = WireInit(Bool(), false.B) val ic_miss_under_miss_f = WireInit(Bool(), false.B) val ic_ignore_2nd_miss_f = WireInit(Bool(), false.B) val ic_debug_rd_en_ff = WireInit(Bool(), false.B) val debug_data_clk = rvclkhdr(clock, ic_debug_rd_en_ff, io.scan_mode) - val flush_final_f = RegNext(io.exu_flush_final, 0.U) + val flush_final_f = withClock(io.free_clk){RegNext(io.exu_flush_final, 0.U)} val fetch_bf_f_c1_clken = io.ifc_fetch_req_bf_raw | ifc_fetch_req_f | miss_pending | io.exu_flush_final | scnd_miss_req val debug_c1_clken = io.ic_debug_rd_en | io.ic_debug_wr_en val debug_c1_clk = rvclkhdr(clock, debug_c1_clken, io.scan_mode) @@ -210,8 +209,8 @@ class el2_ifu_mem_ctl extends Module with el2_lib { Mux(((bus_ifu_wr_en_ff & last_beat) & !uncacheable_miss_ff).asBool, idle_C, Mux((ic_byp_hit_f & !io.exu_flush_final & !(bus_ifu_wr_en_ff & last_beat) & !ifu_bp_hit_taken_q_f & !uncacheable_miss_ff).asBool, stream_C, Mux((bus_ifu_wr_en_ff & !io.exu_flush_final & !(bus_ifu_wr_en_ff & last_beat) & !ifu_bp_hit_taken_q_f & !uncacheable_miss_ff).asBool, stream_C, - Mux((!ic_byp_hit_f & !io.exu_flush_final & (bus_ifu_wr_en_ff & last_beat) & !uncacheable_miss_ff).asBool, idle_C, - Mux(((io.exu_flush_final | ifu_bp_hit_taken_q_f) & !(bus_ifu_wr_en_ff & last_beat)).asBool, hit_u_miss_C, idle_C)))))))) + Mux((!ic_byp_hit_f & !io.exu_flush_final & (bus_ifu_wr_en_ff & last_beat) & !uncacheable_miss_ff).asBool, idle_C, + Mux(((io.exu_flush_final | ifu_bp_hit_taken_q_f) & !(bus_ifu_wr_en_ff & last_beat)).asBool, hit_u_miss_C, idle_C)))))))) miss_state_en := io.dec_tlu_force_halt | io.exu_flush_final | ic_byp_hit_f | ifu_bp_hit_taken_q_f | (bus_ifu_wr_en_ff & last_beat) | (bus_ifu_wr_en_ff & !uncacheable_miss_ff) } is (crit_wrd_rdy_C){ @@ -242,7 +241,7 @@ class el2_ifu_mem_ctl extends Module with el2_lib { miss_state_en := (bus_ifu_wr_en_ff & last_beat) | io.exu_flush_final | io.dec_tlu_force_halt } } - miss_state := RegEnable(miss_nxtstate, 0.U, miss_state_en.asBool) + miss_state := withClock(io.free_clk){RegEnable(miss_nxtstate, 0.U, miss_state_en.asBool)} val crit_byp_hit_f = WireInit(Bool(), 0.U) val way_status_mb_scnd_ff = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U) val way_status = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U) @@ -255,7 +254,7 @@ class el2_ifu_mem_ctl extends Module with el2_lib { miss_pending := miss_state =/= idle_C val crit_wd_byp_ok_ff = (miss_state === crit_byp_ok_C) | ((miss_state === crit_wrd_rdy_C) & !flush_final_f) val sel_hold_imb = (miss_pending & !(bus_ifu_wr_en_ff & last_beat) & !((miss_state === crit_wrd_rdy_C) & io.exu_flush_final) & - !((miss_state === crit_wrd_rdy_C) & crit_byp_hit_f) ) | ic_act_miss_f | + !((miss_state === crit_wrd_rdy_C) & crit_byp_hit_f) ) | ic_act_miss_f | (miss_pending & (miss_nxtstate === crit_wrd_rdy_C)) val sel_hold_imb_scnd = ((miss_state === scnd_miss_C) | ic_miss_under_miss_f) & !flush_final_f @@ -296,17 +295,17 @@ class el2_ifu_mem_ctl extends Module with el2_lib { val way_status_mb_ff = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U) val way_status_rep_new = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U) val way_status_mb_in = Mux((scnd_miss_req & !scnd_miss_index_match).asBool, way_status_mb_scnd_ff, - Mux((scnd_miss_req & scnd_miss_index_match).asBool, way_status_rep_new, - Mux(miss_pending.asBool, way_status_mb_ff, way_status))) + Mux((scnd_miss_req & scnd_miss_index_match).asBool, way_status_rep_new, + Mux(miss_pending.asBool, way_status_mb_ff, way_status))) val replace_way_mb_any = Wire(Vec(ICACHE_NUM_WAYS, UInt(1.W))) val tagv_mb_ff = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U) val tagv_mb_in = Mux(scnd_miss_req.asBool, tagv_mb_scnd_ff | (Fill(ICACHE_NUM_WAYS, scnd_miss_index_match) & replace_way_mb_any.reverse.reduce(Cat(_,_))), - Mux(miss_pending.asBool, tagv_mb_ff, io.ic_tag_valid & Fill(ICACHE_NUM_WAYS, !reset_all_tags))) + Mux(miss_pending.asBool, tagv_mb_ff, io.ic_tag_valid & Fill(ICACHE_NUM_WAYS, !reset_all_tags))) val scnd_miss_req_q = WireInit(Bool(), false.B) val reset_ic_ff = WireInit(Bool(), false.B) val reset_ic_in = miss_pending & !scnd_miss_req_q & (reset_all_tags | reset_ic_ff) - reset_ic_ff := RegNext(reset_ic_in) - val fetch_uncacheable_ff = RegNext(io.ifc_fetch_uncacheable_bf, 0.U) + reset_ic_ff := withClock(io.free_clk){RegNext(reset_ic_in)} + val fetch_uncacheable_ff = withClock(io.active_clk){RegNext(io.ifc_fetch_uncacheable_bf, 0.U)} ifu_fetch_addr_int_f := withClock(fetch_bf_f_c1_clk){RegNext(io.ifc_fetch_addr_bf, 0.U)} val vaddr_f = ifu_fetch_addr_int_f(ICACHE_BEAT_ADDR_HI-1, 0) uncacheable_miss_ff := withClock(fetch_bf_f_c1_clk){RegNext(uncacheable_miss_in, 0.U)} @@ -320,7 +319,7 @@ class el2_ifu_mem_ctl extends Module with el2_lib { tagv_mb_ff := withClock(fetch_bf_f_c1_clk){RegNext(tagv_mb_in, 0.U)} val stream_miss_f = WireInit(Bool(), 0.U) val ifc_fetch_req_qual_bf = io.ifc_fetch_req_bf & !((miss_state===crit_wrd_rdy_C) & flush_final_f) & !stream_miss_f - val ifc_fetch_req_f_raw = RegNext(ifc_fetch_req_qual_bf, 0.U) + val ifc_fetch_req_f_raw = withClock(io.active_clk){RegNext(ifc_fetch_req_qual_bf, 0.U)} ifc_fetch_req_f := ifc_fetch_req_f_raw & !io.exu_flush_final ifc_iccm_access_f := withClock(fetch_bf_f_c1_clk){RegNext(io.ifc_iccm_access_bf, 0.U)} val ifc_region_acc_fault_final_bf = WireInit(Bool(), 0.U) @@ -333,7 +332,7 @@ class el2_ifu_mem_ctl extends Module with el2_lib { val reset_tag_valid_for_miss = WireInit(Bool(), false.B) val sel_mb_addr = (miss_pending & write_ic_16_bytes & !uncacheable_miss_ff) | reset_tag_valid_for_miss val ifu_ic_rw_int_addr = Mux1H(Seq(sel_mb_addr -> Cat(imb_ff(30,ICACHE_BEAT_ADDR_HI) , ic_wr_addr_bits_hi_3 , imb_ff(1,0)), - !sel_mb_addr -> io.ifc_fetch_addr_bf)) + !sel_mb_addr -> io.ifc_fetch_addr_bf)) val bus_ifu_wr_en_ff_q = WireInit(Bool(), false.B) val sel_mb_status_addr = miss_pending & write_ic_16_bytes & !uncacheable_miss_ff & last_beat & bus_ifu_wr_en_ff_q val ifu_status_wr_addr = Mux(sel_mb_status_addr, Cat(imb_ff(30, ICACHE_BEAT_ADDR_HI),ic_wr_addr_bits_hi_3, imb_ff(1,0)), ifu_fetch_addr_int_f) @@ -350,7 +349,7 @@ class el2_ifu_mem_ctl extends Module with el2_lib { io.ic_error_start := ((if(ICACHE_ECC)io.ic_eccerr.orR()else io.ic_parerr.orR()) & ic_act_hit_f) | ic_rd_parity_final_err val ic_debug_tag_val_rd_out = WireInit(Bool(), 0.U) val ic_debug_ict_array_sel_ff = WireInit(Bool(), 0.U) - val ifu_ic_debug_rd_data_in = Mux(ic_debug_ict_array_sel_ff.asBool, if(ICACHE_ECC) Cat(0.U(2.W),io.ictag_debug_rd_data(25,21),0.U(32.W),io.ictag_debug_rd_data(20,0), 0.U(7-ICACHE_STATUS_BITS), way_status, 0.U(3.W),ic_debug_tag_val_rd_out) + val ifu_ic_debug_rd_data_in = Mux(ic_debug_ict_array_sel_ff.asBool, if(ICACHE_ECC) Cat(0.U(2.W),io.ictag_debug_rd_data(25,21),0.U(32.W),io.ictag_debug_rd_data(20,0), 0.U((7-ICACHE_STATUS_BITS).W), way_status, 0.U(3.W),ic_debug_tag_val_rd_out) else Cat(0.U(6.W),io.ictag_debug_rd_data(21),0.U(32.W),io.ictag_debug_rd_data(20,0),0.U(7-ICACHE_STATUS_BITS),way_status ,0.U(3.W) ,ic_debug_tag_val_rd_out) , io.ic_debug_rd_data) io.ifu_ic_debug_rd_data := withClock(debug_data_clk){RegNext(ifu_ic_debug_rd_data_in, 0.U)} @@ -400,8 +399,8 @@ class el2_ifu_mem_ctl extends Module with el2_lib { val ic_miss_buff_data = Wire(Vec(2*ICACHE_NUM_BEATS, UInt(32.W))) for(i<- 0 until ICACHE_NUM_BEATS){ val wr_data_c1_clk = write_fill_data.map(rvclkhdr(clock, _ , io.scan_mode)) - ic_miss_buff_data(2*i) := withClock(wr_data_c1_clk(i)){RegNext(ic_miss_buff_data_in(31,0), 0.U)} - ic_miss_buff_data(2*i+1) := withClock(wr_data_c1_clk(i)){RegNext(ic_miss_buff_data_in(63,32), 0.U)}} + ic_miss_buff_data(2*i) := withClock(wr_data_c1_clk(i)){RegNext(ic_miss_buff_data_in(31,0), 0.U)} + ic_miss_buff_data(2*i+1) := withClock(wr_data_c1_clk(i)){RegNext(ic_miss_buff_data_in(63,32), 0.U)}} val ic_miss_buff_data_valid = WireInit(UInt(ICACHE_NUM_BEATS.W), 0.U) val ic_miss_buff_data_valid_in = (0 until ICACHE_NUM_BEATS).map(i=>write_fill_data(i)|(ic_miss_buff_data_valid(i)&(!ic_act_miss_f))) ic_miss_buff_data_valid := withClock(io.free_clk){RegNext(ic_miss_buff_data_valid_in.map(i=>i.asUInt()).reverse.reduce(Cat(_,_)), 0.U)} @@ -416,16 +415,16 @@ class el2_ifu_mem_ctl extends Module with el2_lib { val bypass_index_5_3_inc = bypass_index(bypass_index.getWidth-1,2) + 1.U val bypass_valid_value_check = Mux1H((0 until ICACHE_NUM_BEATS).map(i=>(bypass_index(bypass_index.getWidth-1,2)===i.U).asBool->ic_miss_buff_data_valid_in(i))) val bypass_data_ready_in = (bypass_valid_value_check & !bypass_index(1) & !bypass_index(0)) | - (bypass_valid_value_check & !bypass_index(1) & bypass_index(0)) | - (bypass_valid_value_check & bypass_index(1) & !bypass_index(0)) | - (bypass_valid_value_check & bypass_index(1) & bypass_index(0) & Mux1H((0 until ICACHE_NUM_BEATS).map(i=>(bypass_index_5_3_inc===i.U).asBool->ic_miss_buff_data_valid_in(i)))) | - (bypass_valid_value_check & bypass_index(ICACHE_BEAT_ADDR_HI-1,2)===Fill(ICACHE_BEAT_ADDR_HI,1.U)) + (bypass_valid_value_check & !bypass_index(1) & bypass_index(0)) | + (bypass_valid_value_check & bypass_index(1) & !bypass_index(0)) | + (bypass_valid_value_check & bypass_index(1) & bypass_index(0) & Mux1H((0 until ICACHE_NUM_BEATS).map(i=>(bypass_index_5_3_inc===i.U).asBool->ic_miss_buff_data_valid_in(i)))) | + (bypass_valid_value_check & bypass_index(ICACHE_BEAT_ADDR_HI-1,2)===Fill(ICACHE_BEAT_ADDR_HI,1.U)) val ic_crit_wd_rdy_new_ff = WireInit(Bool(), 0.U) val ic_crit_wd_rdy_new_in = (bypass_data_ready_in & crit_wd_byp_ok_ff & uncacheable_miss_ff & !io.exu_flush_final & !ifu_bp_hit_taken_q_f) | - ( crit_wd_byp_ok_ff & !uncacheable_miss_ff & !io.exu_flush_final & !ifu_bp_hit_taken_q_f) | - (ic_crit_wd_rdy_new_ff & crit_wd_byp_ok_ff & !fetch_req_icache_f & !io.exu_flush_final) + ( crit_wd_byp_ok_ff & !uncacheable_miss_ff & !io.exu_flush_final & !ifu_bp_hit_taken_q_f) | + (ic_crit_wd_rdy_new_ff & crit_wd_byp_ok_ff & !fetch_req_icache_f & !io.exu_flush_final) ic_crit_wd_rdy_new_ff := withClock(io.free_clk){RegNext(ic_crit_wd_rdy_new_in, 0.U)} val byp_fetch_index = ifu_fetch_addr_int_f(ICACHE_BEAT_ADDR_HI-1,0) val byp_fetch_index_0 = Cat(ifu_fetch_addr_int_f(ICACHE_BEAT_ADDR_HI-1,2), 0.U) @@ -499,7 +498,7 @@ class el2_ifu_mem_ctl extends Module with el2_lib { perr_sel_invalidate := io.dec_tlu_flush_lower_wb & io.dec_tlu_force_halt } is(ecc_wff_C){ - perr_nxtstate := Mux(((io.dec_tlu_flush_err_wb & io.dec_tlu_flush_lower_wb ) | io.dec_tlu_force_halt).asBool(), err_idle_C, ecc_cor_C) + perr_nxtstate := Mux(((!io.dec_tlu_flush_err_wb & io.dec_tlu_flush_lower_wb ) | io.dec_tlu_force_halt).asBool(), err_idle_C, ecc_cor_C) perr_state_en := io.dec_tlu_flush_lower_wb | io.dec_tlu_force_halt } is(dma_sb_err_C){ @@ -516,7 +515,7 @@ class el2_ifu_mem_ctl extends Module with el2_lib { val err_stop_nxtstate = WireInit(UInt(2.W), 0.U) val err_stop_state_en = WireInit(Bool(), false.B) io.iccm_correction_state := false.B -// val err_stop_fetch := WireInit(Bool(), false.B) + // val err_stop_fetch := WireInit(Bool(), false.B) switch(err_stop_state){ is(err_stop_idle_C){ err_stop_nxtstate := err_fetch1_C @@ -547,8 +546,8 @@ class el2_ifu_mem_ctl extends Module with el2_lib { } err_stop_state := withClock(io.free_clk){RegEnable(err_stop_nxtstate, 0.U, err_stop_state_en)} bus_ifu_bus_clk_en := io.ifu_bus_clk_en - val busclk = rvclkhdr(clock, bus_ifu_bus_clk_en, io.scan_mode) - val busclk_force = rvclkhdr(clock, bus_ifu_bus_clk_en | io.dec_tlu_force_halt , io.scan_mode) + val busclk = rvclkhdr(clock, bus_ifu_bus_clk_en, io.scan_mode) + val busclk_force = rvclkhdr(clock, bus_ifu_bus_clk_en | io.dec_tlu_force_halt , io.scan_mode) val bus_ifu_bus_clk_en_ff = withClock(io.free_clk){RegNext(bus_ifu_bus_clk_en, 0.U)} scnd_miss_req_q := withClock(io.free_clk){RegNext(scnd_miss_req_in, 0.U)} val scnd_miss_req_ff2 = withClock(io.free_clk){RegNext(scnd_miss_req, 0.U)} @@ -561,7 +560,7 @@ class el2_ifu_mem_ctl extends Module with el2_lib { ifu_bus_cmd_valid := withClock(busclk_force){RegNext(ifc_bus_ic_req_ff_in, 0.U)} val bus_cmd_sent = WireInit(Bool(), false.B) val bus_cmd_req_in = (ic_act_miss_f | bus_cmd_req_hold) & !bus_cmd_sent & !io.dec_tlu_force_halt - bus_cmd_sent := withClock(io.free_clk){RegNext(bus_cmd_req_in, false.B)} + bus_cmd_req_hold := withClock(io.free_clk){RegNext(bus_cmd_req_in, false.B)} // AXI Read-Channel io.ifu_axi_arvalid := ifu_bus_cmd_valid io.ifu_axi_arid := bus_rd_addr_count & Fill(IFU_BUS_TAG, ifu_bus_cmd_valid) @@ -604,8 +603,8 @@ class el2_ifu_mem_ctl extends Module with el2_lib { last_data_recieved_ff := withClock(io.free_clk){RegNext(last_data_recieved_in, 0.U)} // Request Address Count val bus_new_rd_addr_count = Mux(!miss_pending, imb_ff(ICACHE_BEAT_ADDR_HI-1, 2), - Mux(scnd_miss_req_q, imb_scnd_ff(ICACHE_BEAT_ADDR_HI-1, 2), - Mux(bus_cmd_sent, bus_rd_addr_count + 1.U, bus_rd_addr_count))) + Mux(scnd_miss_req_q, imb_scnd_ff(ICACHE_BEAT_ADDR_HI-1, 2), + Mux(bus_cmd_sent, bus_rd_addr_count + 1.U, bus_rd_addr_count))) bus_rd_addr_count := withClock(busclk_reset){RegNext(bus_new_rd_addr_count, 0.U)} // Command beat Count val bus_inc_cmd_beat_cnt = ifu_bus_cmd_valid & ifu_bus_cmd_ready & miss_pending & !io.dec_tlu_force_halt @@ -661,7 +660,7 @@ class el2_ifu_mem_ctl extends Module with el2_lib { val iccm_dma_rvalid_temp = if(ICCM_ENABLE) withClock(io.free_clk){RegNext(iccm_dma_rvalid_in, false.B)} else 0.U io.iccm_dma_rvalid := iccm_dma_rvalid_temp val iccm_dma_ecc_error = if(ICCM_ENABLE) withClock(io.free_clk){RegNext(iccm_dma_ecc_error_in, false.B)} else 0.U - io.iccm_dma_ecc_error := iccm_dma_ecc_error_in + io.iccm_dma_ecc_error := iccm_dma_ecc_error val iccm_dma_rdata_temp = if(ICCM_ENABLE) withClock(io.free_clk){RegNext(iccm_dma_rdata_in, 0.U)} else 0.U io.iccm_dma_rdata := iccm_dma_rdata_temp val iccm_ecc_corr_index_ff = WireInit(UInt((ICCM_BITS-2).W), 0.U) @@ -699,106 +698,106 @@ class el2_ifu_mem_ctl extends Module with el2_lib { ((miss_state===miss_wait_C) & !miss_state_en) | ((miss_state===crit_wrd_rdy_C) & !miss_state_en) | ((miss_state===crit_byp_ok_C) & miss_state_en & (miss_nxtstate===miss_wait_C)) )) | - (io.ifc_fetch_req_bf & io.exu_flush_final & !io.ifc_fetch_uncacheable_bf & !io.ifc_iccm_access_bf) + (io.ifc_fetch_req_bf & io.exu_flush_final & !io.ifc_fetch_uncacheable_bf & !io.ifc_iccm_access_bf) val bus_ic_wr_en = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U) io.ic_wr_en := bus_ic_wr_en & Fill(ICACHE_NUM_WAYS, write_ic_16_bytes) io.ic_write_stall := write_ic_16_bytes & !((((miss_state===crit_byp_ok_C) | ((miss_state===stream_C) & !(io.exu_flush_final | ifu_bp_hit_taken_q_f | stream_eol_f ))) & !(bus_ifu_wr_en_ff & last_beat & !uncacheable_miss_ff))) reset_all_tags := withClock(io.active_clk){RegNext(io.dec_tlu_fence_i_wb, false.B)} - val ic_valid = !ifu_wr_cumulative_err_data & !(reset_ic_in | reset_ic_ff) & !reset_tag_valid_for_miss - val ifu_status_wr_addr_w_debug = Mux((io.ic_debug_rd_en | io.ic_debug_wr_en) & io.ic_debug_tag_array, io.ic_debug_addr(ICACHE_INDEX_HI - 3, ICACHE_TAG_INDEX_LO - 3), - ifu_status_wr_addr(ICACHE_INDEX_HI - 1, ICACHE_TAG_INDEX_LO - 1)) - val ifu_status_wr_addr_ff = withClock(io.free_clk) { - RegNext(ifu_status_wr_addr_w_debug, 0.U) - } - val way_status_wr_en = WireInit(Bool(), false.B) - val way_status_wr_en_w_debug = way_status_wr_en | (io.ic_debug_wr_en & io.ic_debug_tag_array) - val way_status_wr_en_ff = withClock(io.free_clk) { - RegNext(way_status_wr_en_w_debug, false.B) - } - val way_status_new = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U) - val way_status_new_w_debug = Mux(io.ic_debug_wr_en & io.ic_debug_tag_array, - if (ICACHE_STATUS_BITS == 1) io.ic_debug_wr_data(4) else io.ic_debug_wr_data(6, 4), way_status_new) - val way_status_new_ff = withClock(io.free_clk) { - RegNext(way_status_new_w_debug, 0.U) - } - val way_status_clken = (0 until ICACHE_TAG_DEPTH / 8).map(i => ifu_status_wr_addr_ff(ICACHE_INDEX_HI - ICACHE_TAG_INDEX_LO, 3) === i.U) - val way_status_clk = way_status_clken.map(rvclkhdr(clock, _, io.scan_mode)) - val way_status_out = Wire(Vec(ICACHE_TAG_DEPTH, UInt(ICACHE_STATUS_BITS.W))) - for (i <- 0 until ICACHE_TAG_DEPTH / 8; j <- 0 until 8) - way_status_out((8 * i) + j) := withClock(way_status_clk(i)){RegEnable(way_status_new_ff, 0.U, (ifu_status_wr_addr_ff(2,0)===j.U) & way_status_wr_en_ff)} + val ic_valid = !ifu_wr_cumulative_err_data & !(reset_ic_in | reset_ic_ff) & !reset_tag_valid_for_miss + val ifu_status_wr_addr_w_debug = Mux((io.ic_debug_rd_en | io.ic_debug_wr_en) & io.ic_debug_tag_array, io.ic_debug_addr(ICACHE_INDEX_HI - 3, ICACHE_TAG_INDEX_LO - 3), + ifu_status_wr_addr(ICACHE_INDEX_HI - 1, ICACHE_TAG_INDEX_LO - 1)) + val ifu_status_wr_addr_ff = withClock(io.free_clk) { + RegNext(ifu_status_wr_addr_w_debug, 0.U) + } + val way_status_wr_en = WireInit(Bool(), false.B) + val way_status_wr_en_w_debug = way_status_wr_en | (io.ic_debug_wr_en & io.ic_debug_tag_array) + val way_status_wr_en_ff = withClock(io.free_clk) { + RegNext(way_status_wr_en_w_debug, false.B) + } + val way_status_new = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U) + val way_status_new_w_debug = Mux(io.ic_debug_wr_en & io.ic_debug_tag_array, + if (ICACHE_STATUS_BITS == 1) io.ic_debug_wr_data(4) else io.ic_debug_wr_data(6, 4), way_status_new) + val way_status_new_ff = withClock(io.free_clk) { + RegNext(way_status_new_w_debug, 0.U) + } + val way_status_clken = (0 until ICACHE_TAG_DEPTH / 8).map(i => ifu_status_wr_addr_ff(ICACHE_INDEX_HI - ICACHE_TAG_INDEX_LO, 3) === i.U) + val way_status_clk = way_status_clken.map(rvclkhdr(clock, _, io.scan_mode)) + val way_status_out = Wire(Vec(ICACHE_TAG_DEPTH, UInt(ICACHE_STATUS_BITS.W))) + for (i <- 0 until ICACHE_TAG_DEPTH / 8; j <- 0 until 8) + way_status_out((8 * i) + j) := withClock(way_status_clk(i)){RegEnable(way_status_new_ff, 0.U, (ifu_status_wr_addr_ff(2,0)===j.U) & way_status_wr_en_ff)} val test_way_status_out = (0 until ICACHE_TAG_DEPTH).map(i=>way_status_out(i).asUInt).reverse.reduce(Cat(_,_)) - // io.test_way_status_out := test_way_status_out + // io.test_way_status_out := test_way_status_out val test_way_status_clken = (0 until ICACHE_TAG_DEPTH/8).map(i=>way_status_clken(i).asUInt()).reverse.reduce(Cat(_,_)) //io.test_way_status_clken := test_way_status_clken way_status := Mux1H((0 until ICACHE_TAG_DEPTH).map(i=>(ifu_ic_rw_int_addr_ff === i.U) -> way_status_out(i))) - val ifu_ic_rw_int_addr_w_debug = Mux((io.ic_debug_rd_en | io.ic_debug_wr_en) & io.ic_debug_tag_array, - io.ic_debug_addr(ICACHE_INDEX_HI - 3, ICACHE_TAG_INDEX_LO - 3), ifu_ic_rw_int_addr(ICACHE_INDEX_HI - 1, ICACHE_TAG_INDEX_LO - 1)) - ifu_ic_rw_int_addr_ff := withClock(io.free_clk) { - RegNext(ifu_ic_rw_int_addr_w_debug, 0.U) - } - val ifu_tag_wren = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U) - val ic_debug_tag_wr_en = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U) - val ifu_tag_wren_w_debug = ifu_tag_wren | ic_debug_tag_wr_en - val ifu_tag_wren_ff = withClock(io.free_clk) { - RegNext(ifu_tag_wren_w_debug, 0.U) - } - val ic_valid_w_debug = Mux(io.ic_debug_wr_en & io.ic_debug_tag_array, io.ic_debug_wr_data(0), ic_valid) - val ic_valid_ff = withClock(io.free_clk) { - RegNext(ic_valid_w_debug, false.B) - } - val tag_valid_clken = (0 until (ICACHE_TAG_DEPTH / 32)).map(i => (0 until ICACHE_NUM_WAYS).map(j => - if (ICACHE_TAG_DEPTH == 32) ifu_tag_wren_ff(j) | perr_err_inv_way(j) | reset_all_tags - else ((ifu_ic_rw_int_addr_ff(ICACHE_INDEX_HI - ICACHE_TAG_INDEX_LO, 5) === i.U) & ifu_tag_wren_ff(j)) | - ((perr_ic_index_ff(ICACHE_INDEX_HI - ICACHE_TAG_INDEX_LO, 5) === i.U) & perr_err_inv_way(j)) | - reset_all_tags).reverse.reduce(Cat(_, _))) - val tag_valid_clk = (0 until ICACHE_TAG_DEPTH / 32).map(i => (0 until ICACHE_NUM_WAYS).map(j => rvclkhdr(clock, tag_valid_clken(i)(j), io.scan_mode))) - val ic_tag_valid_out = Wire(Vec(ICACHE_NUM_WAYS, Vec(ICACHE_TAG_DEPTH, Bool()))) - // io.valids := Cat((0 until ICACHE_TAG_DEPTH).map(i=>ic_tag_valid_out(1)(i).asUInt()).reverse.reduce(Cat(_,_)), - // (0 until ICACHE_TAG_DEPTH).map(i=>ic_tag_valid_out(0)(i).asUInt()).reverse.reduce(Cat(_,_))) + val ifu_ic_rw_int_addr_w_debug = Mux((io.ic_debug_rd_en | io.ic_debug_wr_en) & io.ic_debug_tag_array, + io.ic_debug_addr(ICACHE_INDEX_HI - 3, ICACHE_TAG_INDEX_LO - 3), ifu_ic_rw_int_addr(ICACHE_INDEX_HI - 1, ICACHE_TAG_INDEX_LO - 1)) + ifu_ic_rw_int_addr_ff := withClock(io.free_clk) { + RegNext(ifu_ic_rw_int_addr_w_debug, 0.U) + } + val ifu_tag_wren = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U) + val ic_debug_tag_wr_en = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U) + val ifu_tag_wren_w_debug = ifu_tag_wren | ic_debug_tag_wr_en + val ifu_tag_wren_ff = withClock(io.free_clk) { + RegNext(ifu_tag_wren_w_debug, 0.U) + } + val ic_valid_w_debug = Mux(io.ic_debug_wr_en & io.ic_debug_tag_array, io.ic_debug_wr_data(0), ic_valid) + val ic_valid_ff = withClock(io.free_clk) { + RegNext(ic_valid_w_debug, false.B) + } + val tag_valid_clken = (0 until (ICACHE_TAG_DEPTH / 32)).map(i => (0 until ICACHE_NUM_WAYS).map(j => + if (ICACHE_TAG_DEPTH == 32) ifu_tag_wren_ff(j) | perr_err_inv_way(j) | reset_all_tags + else ((ifu_ic_rw_int_addr_ff(ICACHE_INDEX_HI - ICACHE_TAG_INDEX_LO, 5) === i.U) & ifu_tag_wren_ff(j)) | + ((perr_ic_index_ff(ICACHE_INDEX_HI - ICACHE_TAG_INDEX_LO, 5) === i.U) & perr_err_inv_way(j)) | + reset_all_tags).reverse.reduce(Cat(_, _))) + val tag_valid_clk = (0 until ICACHE_TAG_DEPTH / 32).map(i => (0 until ICACHE_NUM_WAYS).map(j => rvclkhdr(clock, tag_valid_clken(i)(j), io.scan_mode))) + val ic_tag_valid_out = Wire(Vec(ICACHE_NUM_WAYS, Vec(ICACHE_TAG_DEPTH, Bool()))) + // io.valids := Cat((0 until ICACHE_TAG_DEPTH).map(i=>ic_tag_valid_out(1)(i).asUInt()).reverse.reduce(Cat(_,_)), + // (0 until ICACHE_TAG_DEPTH).map(i=>ic_tag_valid_out(0)(i).asUInt()).reverse.reduce(Cat(_,_))) - for (i <- 0 until (ICACHE_TAG_DEPTH / 32); j <- 0 until ICACHE_NUM_WAYS; k <- 0 until 32) - ic_tag_valid_out(j)((32 * i) + k) := withClock(tag_valid_clk(i)(j)){RegEnable(ic_valid_ff & !reset_all_tags.asBool & !perr_sel_invalidate, false.B, - ((((ifu_ic_rw_int_addr_ff === (k + (32 * i)).U) & ifu_tag_wren_ff(j)) | ((perr_ic_index_ff === (k + (32 * i)).U) & perr_err_inv_way(j)) | reset_all_tags)).asBool)} + for (i <- 0 until (ICACHE_TAG_DEPTH / 32); j <- 0 until ICACHE_NUM_WAYS; k <- 0 until 32) + ic_tag_valid_out(j)((32 * i) + k) := withClock(tag_valid_clk(i)(j)){RegEnable(ic_valid_ff & !reset_all_tags.asBool & !perr_sel_invalidate, false.B, + ((((ifu_ic_rw_int_addr_ff === (k + (32 * i)).U) & ifu_tag_wren_ff(j)) | ((perr_ic_index_ff === (k + (32 * i)).U) & perr_err_inv_way(j)) | reset_all_tags)).asBool)} - val ic_tag_valid_unq = (0 until ICACHE_NUM_WAYS).map(k => (0 until ICACHE_TAG_DEPTH).map(j => - Mux(ifu_ic_rw_int_addr_ff === j.U, ic_tag_valid_out(k)(j), false.B).asUInt).reduce(_|_)).reverse.reduce(Cat(_,_)) + val ic_tag_valid_unq = (0 until ICACHE_NUM_WAYS).map(k => (0 until ICACHE_TAG_DEPTH).map(j => + Mux(ifu_ic_rw_int_addr_ff === j.U, ic_tag_valid_out(k)(j), false.B).asUInt).reduce(_|_)).reverse.reduce(Cat(_,_)) - // Making a sudo LRU - // val replace_way_mb_any = Wire(Vec(ICACHE_NUM_WAYS, Bool())) - val way_status_hit_new = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U) - if (ICACHE_NUM_WAYS == 4) { - replace_way_mb_any(3) := (way_status_mb_ff(2) & way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) | - (!tagv_mb_ff(3) & tagv_mb_ff(2) & tagv_mb_ff(1) & tagv_mb_ff(0)) - replace_way_mb_any(2) := (!way_status_mb_ff(2) & way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) | - (!tagv_mb_ff(2) & tagv_mb_ff(1) & tagv_mb_ff(0)) - replace_way_mb_any(1) := (way_status_mb_ff(1) & !way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) | - (!tagv_mb_ff(1) & tagv_mb_ff(0)) - replace_way_mb_any(0) := (!way_status_mb_ff(1) & !way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) | !tagv_mb_ff(0) + // Making a sudo LRU + // val replace_way_mb_any = Wire(Vec(ICACHE_NUM_WAYS, Bool())) + val way_status_hit_new = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U) + if (ICACHE_NUM_WAYS == 4) { + replace_way_mb_any(3) := (way_status_mb_ff(2) & way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) | + (!tagv_mb_ff(3) & tagv_mb_ff(2) & tagv_mb_ff(1) & tagv_mb_ff(0)) + replace_way_mb_any(2) := (!way_status_mb_ff(2) & way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) | + (!tagv_mb_ff(2) & tagv_mb_ff(1) & tagv_mb_ff(0)) + replace_way_mb_any(1) := (way_status_mb_ff(1) & !way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) | + (!tagv_mb_ff(1) & tagv_mb_ff(0)) + replace_way_mb_any(0) := (!way_status_mb_ff(1) & !way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) | !tagv_mb_ff(0) - way_status_hit_new := Mux1H(Seq(io.ic_rd_hit(0) -> Cat(way_status(2), 3.U), - io.ic_rd_hit(1) -> Cat(way_status(2), 1.U(2.W)), - io.ic_rd_hit(2) -> Cat(1.U, way_status(1), 0.U), - io.ic_rd_hit(3) -> Cat(0.U, way_status(1), 0.U))) + way_status_hit_new := Mux1H(Seq(io.ic_rd_hit(0) -> Cat(way_status(2), 3.U), + io.ic_rd_hit(1) -> Cat(way_status(2), 1.U(2.W)), + io.ic_rd_hit(2) -> Cat(1.U, way_status(1), 0.U), + io.ic_rd_hit(3) -> Cat(0.U, way_status(1), 0.U))) - way_status_rep_new := Mux1H(Seq(io.ic_rd_hit(0) -> Cat(way_status_mb_ff(2), 3.U), - io.ic_rd_hit(1) -> Cat(way_status_mb_ff(2), 1.U(2.W)), - io.ic_rd_hit(2) -> Cat(1.U, way_status_mb_ff(1), 0.U), - io.ic_rd_hit(3) -> Cat(0.U, way_status_mb_ff(1), 0.U))) - } - else { - replace_way_mb_any(0) := (!way_status_mb_ff & tagv_mb_ff(0) & tagv_mb_ff(1)) | !tagv_mb_ff(0) - replace_way_mb_any(1) := (way_status_mb_ff & tagv_mb_ff(0) & tagv_mb_ff(1)) | !tagv_mb_ff(1) & tagv_mb_ff(0) - way_status_hit_new := io.ic_rd_hit(0) - way_status_rep_new := replace_way_mb_any(0) - } - way_status_new := Mux((bus_ifu_wr_en_ff_q & last_beat).asBool, way_status_rep_new, way_status_hit_new) - way_status_wr_en := (bus_ifu_wr_en_ff_q & last_beat) | ic_act_hit_f - val bus_wren = (0 until ICACHE_NUM_WAYS).map(i => bus_ifu_wr_en_ff_q & replace_way_mb_any(i) & miss_pending) + way_status_rep_new := Mux1H(Seq(io.ic_rd_hit(0) -> Cat(way_status_mb_ff(2), 3.U), + io.ic_rd_hit(1) -> Cat(way_status_mb_ff(2), 1.U(2.W)), + io.ic_rd_hit(2) -> Cat(1.U, way_status_mb_ff(1), 0.U), + io.ic_rd_hit(3) -> Cat(0.U, way_status_mb_ff(1), 0.U))) + } + else { + replace_way_mb_any(0) := (!way_status_mb_ff & tagv_mb_ff(0) & tagv_mb_ff(1)) | !tagv_mb_ff(0) + replace_way_mb_any(1) := (way_status_mb_ff & tagv_mb_ff(0) & tagv_mb_ff(1)) | !tagv_mb_ff(1) & tagv_mb_ff(0) + way_status_hit_new := io.ic_rd_hit(0) + way_status_rep_new := replace_way_mb_any(0) + } + way_status_new := Mux((bus_ifu_wr_en_ff_q & last_beat).asBool, way_status_rep_new, way_status_hit_new) + way_status_wr_en := (bus_ifu_wr_en_ff_q & last_beat) | ic_act_hit_f + val bus_wren = (0 until ICACHE_NUM_WAYS).map(i => bus_ifu_wr_en_ff_q & replace_way_mb_any(i) & miss_pending) - val bus_wren_last = (0 until ICACHE_NUM_WAYS).map(i => bus_ifu_wr_en_ff_wo_err & replace_way_mb_any(i) & miss_pending & bus_last_data_beat) - val wren_reset_miss = (0 until ICACHE_NUM_WAYS).map(i => replace_way_mb_any(i) & reset_tag_valid_for_miss) - ifu_tag_wren := (0 until ICACHE_NUM_WAYS).map(i => bus_wren_last(i) | wren_reset_miss(i)).reverse.reduce(Cat(_, _)) + val bus_wren_last = (0 until ICACHE_NUM_WAYS).map(i => bus_ifu_wr_en_ff_wo_err & replace_way_mb_any(i) & miss_pending & bus_last_data_beat) + val wren_reset_miss = (0 until ICACHE_NUM_WAYS).map(i => replace_way_mb_any(i) & reset_tag_valid_for_miss) + ifu_tag_wren := (0 until ICACHE_NUM_WAYS).map(i => bus_wren_last(i) | wren_reset_miss(i)).reverse.reduce(Cat(_, _)) bus_ic_wr_en := bus_wren.reverse.reduce(Cat(_,_)) if(!ICACHE_ENABLE){ @@ -838,15 +837,15 @@ class el2_ifu_mem_ctl extends Module with el2_lib { ic_debug_ict_array_sel_ff := withClock(debug_c1_clk){RegNext(ic_debug_ict_array_sel_in, 0.U)} ic_debug_rd_en_ff := withClock(io.free_clk){RegNext(io.ic_debug_rd_en, false.B)} io.ifu_ic_debug_rd_data_valid := withClock(io.free_clk){RegEnable(ic_debug_rd_en_ff, 0.U, ic_debug_rd_en_ff.asBool)} - val ifc_region_acc_okay = Cat(INST_ACCESS_ENABLE0.U,INST_ACCESS_ENABLE1.U,INST_ACCESS_ENABLE2.U,INST_ACCESS_ENABLE3.U,INST_ACCESS_ENABLE4.U,INST_ACCESS_ENABLE5.U,INST_ACCESS_ENABLE6.U,INST_ACCESS_ENABLE7.U).orR() | - INST_ACCESS_ENABLE0.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK0).U) === (aslong(INST_ACCESS_ADDR0).U | aslong(INST_ACCESS_MASK0).U)) | - INST_ACCESS_ENABLE1.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK1).U) === (aslong(INST_ACCESS_ADDR1).U | aslong(INST_ACCESS_MASK1).U)) | - INST_ACCESS_ENABLE2.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK2).U) === (aslong(INST_ACCESS_ADDR2).U | aslong(INST_ACCESS_MASK2).U)) | - INST_ACCESS_ENABLE3.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK3).U) === (aslong(INST_ACCESS_ADDR3).U | aslong(INST_ACCESS_MASK3).U)) | - INST_ACCESS_ENABLE4.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK4).U) === (aslong(INST_ACCESS_ADDR4).U | aslong(INST_ACCESS_MASK4).U)) | - INST_ACCESS_ENABLE5.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK5).U) === (aslong(INST_ACCESS_ADDR5).U | aslong(INST_ACCESS_MASK5).U)) | - INST_ACCESS_ENABLE6.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK6).U) === (aslong(INST_ACCESS_ADDR6).U | aslong(INST_ACCESS_MASK6).U)) | - INST_ACCESS_ENABLE7.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK7).U) === (aslong(INST_ACCESS_ADDR7).U | aslong(INST_ACCESS_MASK7).U)) + val ifc_region_acc_okay = !(Cat(INST_ACCESS_ENABLE0.U,INST_ACCESS_ENABLE1.U,INST_ACCESS_ENABLE2.U,INST_ACCESS_ENABLE3.U,INST_ACCESS_ENABLE4.U,INST_ACCESS_ENABLE5.U,INST_ACCESS_ENABLE6.U,INST_ACCESS_ENABLE7.U).orR()) | + (INST_ACCESS_ENABLE0.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK0).U) === (aslong(INST_ACCESS_ADDR0).U | aslong(INST_ACCESS_MASK0).U))) | + (INST_ACCESS_ENABLE1.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK1).U) === (aslong(INST_ACCESS_ADDR1).U | aslong(INST_ACCESS_MASK1).U))) | + (INST_ACCESS_ENABLE2.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK2).U) === (aslong(INST_ACCESS_ADDR2).U | aslong(INST_ACCESS_MASK2).U))) | + (INST_ACCESS_ENABLE3.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK3).U) === (aslong(INST_ACCESS_ADDR3).U | aslong(INST_ACCESS_MASK3).U))) | + (INST_ACCESS_ENABLE4.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK4).U) === (aslong(INST_ACCESS_ADDR4).U | aslong(INST_ACCESS_MASK4).U))) | + (INST_ACCESS_ENABLE5.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK5).U) === (aslong(INST_ACCESS_ADDR5).U | aslong(INST_ACCESS_MASK5).U))) | + (INST_ACCESS_ENABLE6.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK6).U) === (aslong(INST_ACCESS_ADDR6).U | aslong(INST_ACCESS_MASK6).U))) | + (INST_ACCESS_ENABLE7.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK7).U) === (aslong(INST_ACCESS_ADDR7).U | aslong(INST_ACCESS_MASK7).U))) val ifc_region_acc_fault_memory_bf = !io.ifc_iccm_access_bf & !ifc_region_acc_okay & io.ifc_fetch_req_bf ifc_region_acc_fault_final_bf := io.ifc_region_acc_fault_bf | ifc_region_acc_fault_memory_bf ifc_region_acc_fault_memory_f := withClock(io.free_clk){RegNext(ifc_region_acc_fault_memory_bf, false.B)} @@ -854,5 +853,4 @@ class el2_ifu_mem_ctl extends Module with el2_lib { } object ifu_mem extends App { println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_mem_ctl())) -} - +} \ No newline at end of file diff --git a/src/main/scala/lsu/el2_lsu.scala b/src/main/scala/lsu/el2_lsu.scala index 1b0a9208..3d833cfc 100644 --- a/src/main/scala/lsu/el2_lsu.scala +++ b/src/main/scala/lsu/el2_lsu.scala @@ -241,7 +241,7 @@ class el2_lsu extends Module with RequireAsyncReset with param with el2_lib { dccm_ctl.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_m_clk dccm_ctl.io.lsu_free_c2_clk := clkdomain.io.lsu_c2_r_clk dccm_ctl.io.lsu_c1_r_clk := clkdomain.io.lsu_free_c2_clk - dccm_ctl.io.lsu_store_c1_r_clk := clkdomain.io.lsu_c1_r_clk + dccm_ctl.io.lsu_store_c1_r_clk := clkdomain.io.lsu_store_c1_r_clk //dccm_ctl.io.clk := clock dccm_ctl.io.lsu_pkt_d <> lsu_lsc_ctl.io.lsu_pkt_d dccm_ctl.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m diff --git a/target/scala-2.12/classes/dbg/debug$.class b/target/scala-2.12/classes/dbg/debug$.class index 01472b78..35db8f37 100644 Binary files a/target/scala-2.12/classes/dbg/debug$.class and b/target/scala-2.12/classes/dbg/debug$.class differ diff --git a/target/scala-2.12/classes/dbg/el2_dbg$$anon$1.class b/target/scala-2.12/classes/dbg/el2_dbg$$anon$1.class index d9a716bc..4a58c61c 100644 Binary files a/target/scala-2.12/classes/dbg/el2_dbg$$anon$1.class and b/target/scala-2.12/classes/dbg/el2_dbg$$anon$1.class differ diff --git a/target/scala-2.12/classes/dbg/el2_dbg.class b/target/scala-2.12/classes/dbg/el2_dbg.class index 9eb6de52..8d760ab9 100644 Binary files a/target/scala-2.12/classes/dbg/el2_dbg.class and b/target/scala-2.12/classes/dbg/el2_dbg.class differ diff --git a/target/scala-2.12/classes/dec/dec_decode$.class b/target/scala-2.12/classes/dec/dec_decode$.class index 04dc2f23..5ea0b6d8 100644 Binary files a/target/scala-2.12/classes/dec/dec_decode$.class and b/target/scala-2.12/classes/dec/dec_decode$.class differ diff --git a/target/scala-2.12/classes/dec/dec_trig$.class b/target/scala-2.12/classes/dec/dec_trig$.class index 8945d2df..8687e58c 100644 Binary files a/target/scala-2.12/classes/dec/dec_trig$.class and b/target/scala-2.12/classes/dec/dec_trig$.class differ diff --git a/target/scala-2.12/classes/dec/ib_gen$.class b/target/scala-2.12/classes/dec/ib_gen$.class index 6e429203..bb9777d5 100644 Binary files a/target/scala-2.12/classes/dec/ib_gen$.class and b/target/scala-2.12/classes/dec/ib_gen$.class differ diff --git a/target/scala-2.12/classes/dma$.class b/target/scala-2.12/classes/dma$.class index 334e2e4b..45df66bf 100644 Binary files a/target/scala-2.12/classes/dma$.class and b/target/scala-2.12/classes/dma$.class differ diff --git a/target/scala-2.12/classes/ifu/el2_ifu_mem_ctl.class b/target/scala-2.12/classes/ifu/el2_ifu_mem_ctl.class index ba470471..0906ebec 100644 Binary files a/target/scala-2.12/classes/ifu/el2_ifu_mem_ctl.class and b/target/scala-2.12/classes/ifu/el2_ifu_mem_ctl.class differ diff --git a/target/scala-2.12/classes/ifu/ifu_mem$.class b/target/scala-2.12/classes/ifu/ifu_mem$.class index a3910c8b..1d8764bc 100644 Binary files a/target/scala-2.12/classes/ifu/ifu_mem$.class and b/target/scala-2.12/classes/ifu/ifu_mem$.class differ diff --git a/target/scala-2.12/classes/ifu/ifu_mem$delayedInit$body.class b/target/scala-2.12/classes/ifu/ifu_mem$delayedInit$body.class index db95175c..ef2ad9a3 100644 Binary files a/target/scala-2.12/classes/ifu/ifu_mem$delayedInit$body.class and b/target/scala-2.12/classes/ifu/ifu_mem$delayedInit$body.class differ diff --git a/target/scala-2.12/classes/ifu/mem_ctl_bundle.class b/target/scala-2.12/classes/ifu/mem_ctl_bundle.class index efda252d..0220a258 100644 Binary files a/target/scala-2.12/classes/ifu/mem_ctl_bundle.class and b/target/scala-2.12/classes/ifu/mem_ctl_bundle.class differ diff --git a/target/scala-2.12/classes/lsu/el2_lsu.class b/target/scala-2.12/classes/lsu/el2_lsu.class index 0e65b9b0..1132fe66 100644 Binary files a/target/scala-2.12/classes/lsu/el2_lsu.class and b/target/scala-2.12/classes/lsu/el2_lsu.class differ