From 9f854c59ec01d401469499f593e93d4a5d725779 Mon Sep 17 00:00:00 2001 From: waleed-lm Date: Thu, 1 Oct 2020 14:49:02 +0500 Subject: [PATCH] ALN 1st attempt --- el2_ifu_aln_ctl.fir | 1316 ++++++++--------- el2_ifu_aln_ctl.v | 239 ++- src/main/scala/ifu/el2_ifu_aln_ctl.scala | 1 - .../classes/ifu/el2_ifu_aln_ctl$$anon$1.class | Bin 6944 -> 6820 bytes .../classes/ifu/el2_ifu_aln_ctl.class | Bin 174201 -> 174174 bytes target/scala-2.12/classes/ifu/ifu_aln$.class | Bin 3875 -> 3875 bytes .../ifu/ifu_aln$delayedInit$body.class | Bin 736 -> 736 bytes 7 files changed, 777 insertions(+), 779 deletions(-) diff --git a/el2_ifu_aln_ctl.fir b/el2_ifu_aln_ctl.fir index 680d0d41..41707e2b 100644 --- a/el2_ifu_aln_ctl.fir +++ b/el2_ifu_aln_ctl.fir @@ -1868,7 +1868,7 @@ circuit el2_ifu_aln_ctl : module el2_ifu_aln_ctl : input clock : Clock input reset : UInt<1> - output io : {flip scan_mode : UInt<1>, flip free_clk : Clock, flip active_clk : Clock, flip ifu_async_error_start : UInt<1>, flip iccm_rd_ecc_double_err : UInt<1>, flip ic_access_fault_f : UInt<1>, flip ic_access_fault_type_f : UInt<2>, flip ifu_bp_fghr_f : UInt<8>, flip ifu_bp_btb_target_f : UInt<32>, flip ifu_bp_poffset_f : UInt<12>, flip ifu_bp_hist0_f : UInt<2>, flip ifu_bp_hist1_f : UInt<2>, flip ifu_bp_pc4_f : UInt<2>, flip ifu_bp_way_f : UInt<2>, flip ifu_bp_valid_f : UInt<2>, flip ifu_bp_ret_f : UInt<2>, flip exu_flush_final : UInt<1>, flip dec_i0_decode_d : UInt<1>, flip ifu_fetch_data_f : UInt<32>, flip ifu_fetch_val : UInt<2>, flip ifu_fetch_pc : UInt<32>, ifu_i0_valid : UInt<1>, ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_icaf_f1 : UInt<1>, ifu_i0_dbecc : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<32>, ifu_i0_pc4 : UInt<1>, ifu_fb_consume1 : UInt<1>, ifu_fb_consume2 : UInt<1>, ifu_i0_bp_index : UInt<7>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, ifu_pmu_instr_aligned : UInt<1>, ifu_i0_cinst : UInt<16>, i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<32>, way : UInt<1>, ret : UInt<1>}} + output io : {flip scan_mode : UInt<1>, flip active_clk : Clock, flip ifu_async_error_start : UInt<1>, flip iccm_rd_ecc_double_err : UInt<1>, flip ic_access_fault_f : UInt<1>, flip ic_access_fault_type_f : UInt<2>, flip ifu_bp_fghr_f : UInt<8>, flip ifu_bp_btb_target_f : UInt<32>, flip ifu_bp_poffset_f : UInt<12>, flip ifu_bp_hist0_f : UInt<2>, flip ifu_bp_hist1_f : UInt<2>, flip ifu_bp_pc4_f : UInt<2>, flip ifu_bp_way_f : UInt<2>, flip ifu_bp_valid_f : UInt<2>, flip ifu_bp_ret_f : UInt<2>, flip exu_flush_final : UInt<1>, flip dec_i0_decode_d : UInt<1>, flip ifu_fetch_data_f : UInt<32>, flip ifu_fetch_val : UInt<2>, flip ifu_fetch_pc : UInt<32>, ifu_i0_valid : UInt<1>, ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_icaf_f1 : UInt<1>, ifu_i0_dbecc : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<32>, ifu_i0_pc4 : UInt<1>, ifu_fb_consume1 : UInt<1>, ifu_fb_consume2 : UInt<1>, ifu_i0_bp_index : UInt<7>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, ifu_pmu_instr_aligned : UInt<1>, ifu_i0_cinst : UInt<16>, i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<32>, way : UInt<1>, ret : UInt<1>}} wire error_stall_in : UInt<1> error_stall_in <= UInt<1>("h00") @@ -1928,194 +1928,194 @@ circuit el2_ifu_aln_ctl : brdata0 <= UInt<1>("h00") wire brdata2 : UInt<12> brdata2 <= UInt<1>("h00") - reg error_stall : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 90:54] - error_stall <= error_stall_in @[el2_ifu_aln_ctl.scala 90:54] - reg f0val : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 91:48] - f0val <= f0val_in @[el2_ifu_aln_ctl.scala 91:48] - node _T = or(error_stall, io.ifu_async_error_start) @[el2_ifu_aln_ctl.scala 92:34] - node _T_1 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 92:64] - node _T_2 = and(_T, _T_1) @[el2_ifu_aln_ctl.scala 92:62] - error_stall_in <= _T_2 @[el2_ifu_aln_ctl.scala 92:18] - node _T_3 = not(error_stall) @[el2_ifu_aln_ctl.scala 94:39] - node i0_shift = and(io.dec_i0_decode_d, _T_3) @[el2_ifu_aln_ctl.scala 94:37] - io.ifu_pmu_instr_aligned <= i0_shift @[el2_ifu_aln_ctl.scala 96:28] - node _T_4 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 98:34] - node _T_5 = bits(_T_4, 0, 0) @[el2_ifu_aln_ctl.scala 98:38] - node _T_6 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 98:64] - node _T_7 = not(_T_6) @[el2_ifu_aln_ctl.scala 98:58] - node _T_8 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 98:75] - node _T_9 = and(_T_7, _T_8) @[el2_ifu_aln_ctl.scala 98:68] - node _T_10 = bits(_T_9, 0, 0) @[el2_ifu_aln_ctl.scala 98:80] + reg error_stall : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 89:54] + error_stall <= error_stall_in @[el2_ifu_aln_ctl.scala 89:54] + reg f0val : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 90:48] + f0val <= f0val_in @[el2_ifu_aln_ctl.scala 90:48] + node _T = or(error_stall, io.ifu_async_error_start) @[el2_ifu_aln_ctl.scala 91:34] + node _T_1 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 91:64] + node _T_2 = and(_T, _T_1) @[el2_ifu_aln_ctl.scala 91:62] + error_stall_in <= _T_2 @[el2_ifu_aln_ctl.scala 91:18] + node _T_3 = not(error_stall) @[el2_ifu_aln_ctl.scala 93:39] + node i0_shift = and(io.dec_i0_decode_d, _T_3) @[el2_ifu_aln_ctl.scala 93:37] + io.ifu_pmu_instr_aligned <= i0_shift @[el2_ifu_aln_ctl.scala 95:28] + node _T_4 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 97:34] + node _T_5 = bits(_T_4, 0, 0) @[el2_ifu_aln_ctl.scala 97:38] + node _T_6 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 97:64] + node _T_7 = not(_T_6) @[el2_ifu_aln_ctl.scala 97:58] + node _T_8 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 97:75] + node _T_9 = and(_T_7, _T_8) @[el2_ifu_aln_ctl.scala 97:68] + node _T_10 = bits(_T_9, 0, 0) @[el2_ifu_aln_ctl.scala 97:80] node _T_11 = cat(q1final, q0final) @[Cat.scala 29:58] node _T_12 = mux(_T_5, q0final, UInt<1>("h00")) @[Mux.scala 27:72] node _T_13 = mux(_T_10, _T_11, UInt<1>("h00")) @[Mux.scala 27:72] node _T_14 = or(_T_12, _T_13) @[Mux.scala 27:72] wire aligndata : UInt<32> @[Mux.scala 27:72] aligndata <= _T_14 @[Mux.scala 27:72] - inst decompressed of el2_ifu_compress_ctl @[el2_ifu_aln_ctl.scala 100:28] + inst decompressed of el2_ifu_compress_ctl @[el2_ifu_aln_ctl.scala 99:28] decompressed.clock <= clock decompressed.reset <= reset - decompressed.io.din <= aligndata @[el2_ifu_aln_ctl.scala 102:23] - io.ifu_i0_instr <= decompressed.io.dout @[el2_ifu_aln_ctl.scala 104:20] - node _T_15 = bits(aligndata, 15, 0) @[el2_ifu_aln_ctl.scala 107:31] - io.ifu_i0_cinst <= _T_15 @[el2_ifu_aln_ctl.scala 107:19] + decompressed.io.din <= aligndata @[el2_ifu_aln_ctl.scala 101:23] + io.ifu_i0_instr <= decompressed.io.dout @[el2_ifu_aln_ctl.scala 103:20] + node _T_15 = bits(aligndata, 15, 0) @[el2_ifu_aln_ctl.scala 106:31] + io.ifu_i0_cinst <= _T_15 @[el2_ifu_aln_ctl.scala 106:19] wire first4B : UInt<1> first4B <= UInt<1>("h00") - node first2B = not(first4B) @[el2_ifu_aln_ctl.scala 112:17] - node _T_16 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 113:34] - node _T_17 = bits(_T_16, 0, 0) @[el2_ifu_aln_ctl.scala 113:38] - node _T_18 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 113:63] - node _T_19 = not(_T_18) @[el2_ifu_aln_ctl.scala 113:57] - node _T_20 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 113:74] - node _T_21 = and(_T_19, _T_20) @[el2_ifu_aln_ctl.scala 113:67] - node _T_22 = bits(_T_21, 0, 0) @[el2_ifu_aln_ctl.scala 113:79] + node first2B = not(first4B) @[el2_ifu_aln_ctl.scala 111:17] + node _T_16 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 112:34] + node _T_17 = bits(_T_16, 0, 0) @[el2_ifu_aln_ctl.scala 112:38] + node _T_18 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 112:63] + node _T_19 = not(_T_18) @[el2_ifu_aln_ctl.scala 112:57] + node _T_20 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 112:74] + node _T_21 = and(_T_19, _T_20) @[el2_ifu_aln_ctl.scala 112:67] + node _T_22 = bits(_T_21, 0, 0) @[el2_ifu_aln_ctl.scala 112:79] node _T_23 = cat(f1icaf, f0icaf) @[Cat.scala 29:58] node _T_24 = mux(_T_17, f0icaf, UInt<1>("h00")) @[Mux.scala 27:72] node _T_25 = mux(_T_22, _T_23, UInt<1>("h00")) @[Mux.scala 27:72] node _T_26 = or(_T_24, _T_25) @[Mux.scala 27:72] wire alignicaf : UInt<2> @[Mux.scala 27:72] alignicaf <= _T_26 @[Mux.scala 27:72] - node _T_27 = bits(first4B, 0, 0) @[el2_ifu_aln_ctl.scala 115:39] - node _T_28 = orr(alignicaf) @[el2_ifu_aln_ctl.scala 115:59] - node _T_29 = bits(first2B, 0, 0) @[el2_ifu_aln_ctl.scala 115:72] - node _T_30 = bits(alignicaf, 0, 0) @[el2_ifu_aln_ctl.scala 115:91] + node _T_27 = bits(first4B, 0, 0) @[el2_ifu_aln_ctl.scala 114:39] + node _T_28 = orr(alignicaf) @[el2_ifu_aln_ctl.scala 114:59] + node _T_29 = bits(first2B, 0, 0) @[el2_ifu_aln_ctl.scala 114:72] + node _T_30 = bits(alignicaf, 0, 0) @[el2_ifu_aln_ctl.scala 114:91] node _T_31 = mux(_T_27, _T_28, UInt<1>("h00")) @[Mux.scala 27:72] node _T_32 = mux(_T_29, _T_30, UInt<1>("h00")) @[Mux.scala 27:72] node _T_33 = or(_T_31, _T_32) @[Mux.scala 27:72] wire _T_34 : UInt<1> @[Mux.scala 27:72] _T_34 <= _T_33 @[Mux.scala 27:72] - io.ifu_i0_icaf <= _T_34 @[el2_ifu_aln_ctl.scala 115:18] - node _T_35 = bits(first4B, 0, 0) @[el2_ifu_aln_ctl.scala 116:40] - node _T_36 = bits(alignval, 1, 1) @[el2_ifu_aln_ctl.scala 116:58] - node _T_37 = bits(first2B, 0, 0) @[el2_ifu_aln_ctl.scala 116:71] - node _T_38 = bits(alignval, 0, 0) @[el2_ifu_aln_ctl.scala 116:89] + io.ifu_i0_icaf <= _T_34 @[el2_ifu_aln_ctl.scala 114:18] + node _T_35 = bits(first4B, 0, 0) @[el2_ifu_aln_ctl.scala 115:40] + node _T_36 = bits(alignval, 1, 1) @[el2_ifu_aln_ctl.scala 115:58] + node _T_37 = bits(first2B, 0, 0) @[el2_ifu_aln_ctl.scala 115:71] + node _T_38 = bits(alignval, 0, 0) @[el2_ifu_aln_ctl.scala 115:89] node _T_39 = mux(_T_35, _T_36, UInt<1>("h00")) @[Mux.scala 27:72] node _T_40 = mux(_T_37, _T_38, UInt<1>("h00")) @[Mux.scala 27:72] node _T_41 = or(_T_39, _T_40) @[Mux.scala 27:72] wire _T_42 : UInt<1> @[Mux.scala 27:72] _T_42 <= _T_41 @[Mux.scala 27:72] - io.ifu_i0_valid <= _T_42 @[el2_ifu_aln_ctl.scala 116:19] - io.ifu_i0_pc4 <= first4B @[el2_ifu_aln_ctl.scala 117:17] - node shift_2B = and(i0_shift, first2B) @[el2_ifu_aln_ctl.scala 119:27] - node shift_4B = and(i0_shift, first4B) @[el2_ifu_aln_ctl.scala 120:27] - node _T_43 = bits(shift_2B, 0, 0) @[el2_ifu_aln_ctl.scala 121:40] - node _T_44 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 121:55] - node _T_45 = bits(shift_4B, 0, 0) @[el2_ifu_aln_ctl.scala 121:69] - node _T_46 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 121:86] - node _T_47 = eq(_T_46, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 121:80] - node _T_48 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 121:97] - node _T_49 = and(_T_47, _T_48) @[el2_ifu_aln_ctl.scala 121:90] + io.ifu_i0_valid <= _T_42 @[el2_ifu_aln_ctl.scala 115:19] + io.ifu_i0_pc4 <= first4B @[el2_ifu_aln_ctl.scala 116:17] + node shift_2B = and(i0_shift, first2B) @[el2_ifu_aln_ctl.scala 118:27] + node shift_4B = and(i0_shift, first4B) @[el2_ifu_aln_ctl.scala 119:27] + node _T_43 = bits(shift_2B, 0, 0) @[el2_ifu_aln_ctl.scala 120:40] + node _T_44 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 120:55] + node _T_45 = bits(shift_4B, 0, 0) @[el2_ifu_aln_ctl.scala 120:69] + node _T_46 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 120:86] + node _T_47 = eq(_T_46, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 120:80] + node _T_48 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 120:97] + node _T_49 = and(_T_47, _T_48) @[el2_ifu_aln_ctl.scala 120:90] node _T_50 = mux(_T_43, _T_44, UInt<1>("h00")) @[Mux.scala 27:72] node _T_51 = mux(_T_45, _T_49, UInt<1>("h00")) @[Mux.scala 27:72] node _T_52 = or(_T_50, _T_51) @[Mux.scala 27:72] wire f0_shift_2B : UInt<1> @[Mux.scala 27:72] f0_shift_2B <= _T_52 @[Mux.scala 27:72] - node _T_53 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 122:27] - node _T_54 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 122:39] - node _T_55 = eq(_T_54, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 122:33] - node _T_56 = and(_T_53, _T_55) @[el2_ifu_aln_ctl.scala 122:31] - node f1_shift_2B = and(_T_56, shift_4B) @[el2_ifu_aln_ctl.scala 122:43] - reg wrptr : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 124:48] - wrptr <= wrptr_in @[el2_ifu_aln_ctl.scala 124:48] - reg rdptr : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 125:48] - rdptr <= wrptr_in @[el2_ifu_aln_ctl.scala 125:48] - reg f2val : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 127:48] - f2val <= f2val_in @[el2_ifu_aln_ctl.scala 127:48] - reg f1val : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 128:48] - f1val <= f1val_in @[el2_ifu_aln_ctl.scala 128:48] - reg q2off : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 131:48] - q2off <= q2off_in @[el2_ifu_aln_ctl.scala 131:48] - reg q1off : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 132:48] - q1off <= q1off_in @[el2_ifu_aln_ctl.scala 132:48] - reg q0off : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 133:48] - q0off <= q0off_in @[el2_ifu_aln_ctl.scala 133:48] - node _T_57 = eq(sf0_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 135:29] - node _T_58 = eq(sf1_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 135:42] - node _T_59 = and(_T_57, _T_58) @[el2_ifu_aln_ctl.scala 135:40] - node _T_60 = eq(f2_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 135:55] - node _T_61 = and(_T_59, _T_60) @[el2_ifu_aln_ctl.scala 135:53] - node fetch_to_f0 = and(_T_61, ifvalid) @[el2_ifu_aln_ctl.scala 135:65] - node _T_62 = eq(sf0_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 136:29] - node _T_63 = eq(sf1_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 136:42] - node _T_64 = and(_T_62, _T_63) @[el2_ifu_aln_ctl.scala 136:40] - node _T_65 = and(_T_64, f2_valid) @[el2_ifu_aln_ctl.scala 136:53] - node _T_66 = and(_T_65, ifvalid) @[el2_ifu_aln_ctl.scala 136:65] - node _T_67 = eq(sf0_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 137:29] - node _T_68 = and(_T_67, sf1_valid) @[el2_ifu_aln_ctl.scala 137:40] - node _T_69 = eq(f2_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 137:55] - node _T_70 = and(_T_68, _T_69) @[el2_ifu_aln_ctl.scala 137:53] - node _T_71 = and(_T_70, ifvalid) @[el2_ifu_aln_ctl.scala 137:65] - node _T_72 = or(_T_66, _T_71) @[el2_ifu_aln_ctl.scala 136:77] - node _T_73 = eq(sf1_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 138:42] - node _T_74 = and(sf0_valid, _T_73) @[el2_ifu_aln_ctl.scala 138:40] - node _T_75 = eq(f2_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 138:55] - node _T_76 = and(_T_74, _T_75) @[el2_ifu_aln_ctl.scala 138:53] - node _T_77 = and(_T_76, ifvalid) @[el2_ifu_aln_ctl.scala 138:65] - node fetch_to_f1 = or(_T_72, _T_77) @[el2_ifu_aln_ctl.scala 137:77] - node _T_78 = eq(sf0_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 140:29] - node _T_79 = and(_T_78, sf1_valid) @[el2_ifu_aln_ctl.scala 140:40] - node _T_80 = and(_T_79, f2_valid) @[el2_ifu_aln_ctl.scala 140:53] - node _T_81 = and(_T_80, ifvalid) @[el2_ifu_aln_ctl.scala 140:65] - node _T_82 = and(sf0_valid, sf1_valid) @[el2_ifu_aln_ctl.scala 141:40] - node _T_83 = eq(f2_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 141:55] - node _T_84 = and(_T_82, _T_83) @[el2_ifu_aln_ctl.scala 141:53] - node _T_85 = and(_T_84, ifvalid) @[el2_ifu_aln_ctl.scala 141:65] - node f2_wr_en = or(_T_81, _T_85) @[el2_ifu_aln_ctl.scala 140:77] - node _T_86 = or(fetch_to_f1, shift_f2_f1) @[el2_ifu_aln_ctl.scala 144:36] - node f1_shift_wr_en = or(_T_86, f1_shift_2B) @[el2_ifu_aln_ctl.scala 144:50] - node _T_87 = or(fetch_to_f0, shift_f2_f0) @[el2_ifu_aln_ctl.scala 145:36] - node _T_88 = or(_T_87, shift_f1_f0) @[el2_ifu_aln_ctl.scala 145:50] - node _T_89 = or(_T_88, shift_2B) @[el2_ifu_aln_ctl.scala 145:64] - node f0_shift_wr_en = or(_T_89, shift_4B) @[el2_ifu_aln_ctl.scala 145:75] - node _T_90 = eq(rdptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 147:24] - node _T_91 = eq(rdptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 147:39] - node _T_92 = eq(rdptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 147:54] + node _T_53 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 121:27] + node _T_54 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 121:39] + node _T_55 = eq(_T_54, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 121:33] + node _T_56 = and(_T_53, _T_55) @[el2_ifu_aln_ctl.scala 121:31] + node f1_shift_2B = and(_T_56, shift_4B) @[el2_ifu_aln_ctl.scala 121:43] + reg wrptr : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 123:48] + wrptr <= wrptr_in @[el2_ifu_aln_ctl.scala 123:48] + reg rdptr : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 124:48] + rdptr <= wrptr_in @[el2_ifu_aln_ctl.scala 124:48] + reg f2val : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 126:48] + f2val <= f2val_in @[el2_ifu_aln_ctl.scala 126:48] + reg f1val : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 127:48] + f1val <= f1val_in @[el2_ifu_aln_ctl.scala 127:48] + reg q2off : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 130:48] + q2off <= q2off_in @[el2_ifu_aln_ctl.scala 130:48] + reg q1off : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 131:48] + q1off <= q1off_in @[el2_ifu_aln_ctl.scala 131:48] + reg q0off : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 132:48] + q0off <= q0off_in @[el2_ifu_aln_ctl.scala 132:48] + node _T_57 = eq(sf0_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 134:29] + node _T_58 = eq(sf1_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 134:42] + node _T_59 = and(_T_57, _T_58) @[el2_ifu_aln_ctl.scala 134:40] + node _T_60 = eq(f2_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 134:55] + node _T_61 = and(_T_59, _T_60) @[el2_ifu_aln_ctl.scala 134:53] + node fetch_to_f0 = and(_T_61, ifvalid) @[el2_ifu_aln_ctl.scala 134:65] + node _T_62 = eq(sf0_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 135:29] + node _T_63 = eq(sf1_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 135:42] + node _T_64 = and(_T_62, _T_63) @[el2_ifu_aln_ctl.scala 135:40] + node _T_65 = and(_T_64, f2_valid) @[el2_ifu_aln_ctl.scala 135:53] + node _T_66 = and(_T_65, ifvalid) @[el2_ifu_aln_ctl.scala 135:65] + node _T_67 = eq(sf0_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 136:29] + node _T_68 = and(_T_67, sf1_valid) @[el2_ifu_aln_ctl.scala 136:40] + node _T_69 = eq(f2_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 136:55] + node _T_70 = and(_T_68, _T_69) @[el2_ifu_aln_ctl.scala 136:53] + node _T_71 = and(_T_70, ifvalid) @[el2_ifu_aln_ctl.scala 136:65] + node _T_72 = or(_T_66, _T_71) @[el2_ifu_aln_ctl.scala 135:77] + node _T_73 = eq(sf1_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 137:42] + node _T_74 = and(sf0_valid, _T_73) @[el2_ifu_aln_ctl.scala 137:40] + node _T_75 = eq(f2_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 137:55] + node _T_76 = and(_T_74, _T_75) @[el2_ifu_aln_ctl.scala 137:53] + node _T_77 = and(_T_76, ifvalid) @[el2_ifu_aln_ctl.scala 137:65] + node fetch_to_f1 = or(_T_72, _T_77) @[el2_ifu_aln_ctl.scala 136:77] + node _T_78 = eq(sf0_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 139:29] + node _T_79 = and(_T_78, sf1_valid) @[el2_ifu_aln_ctl.scala 139:40] + node _T_80 = and(_T_79, f2_valid) @[el2_ifu_aln_ctl.scala 139:53] + node _T_81 = and(_T_80, ifvalid) @[el2_ifu_aln_ctl.scala 139:65] + node _T_82 = and(sf0_valid, sf1_valid) @[el2_ifu_aln_ctl.scala 140:40] + node _T_83 = eq(f2_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 140:55] + node _T_84 = and(_T_82, _T_83) @[el2_ifu_aln_ctl.scala 140:53] + node _T_85 = and(_T_84, ifvalid) @[el2_ifu_aln_ctl.scala 140:65] + node f2_wr_en = or(_T_81, _T_85) @[el2_ifu_aln_ctl.scala 139:77] + node _T_86 = or(fetch_to_f1, shift_f2_f1) @[el2_ifu_aln_ctl.scala 143:36] + node f1_shift_wr_en = or(_T_86, f1_shift_2B) @[el2_ifu_aln_ctl.scala 143:50] + node _T_87 = or(fetch_to_f0, shift_f2_f0) @[el2_ifu_aln_ctl.scala 144:36] + node _T_88 = or(_T_87, shift_f1_f0) @[el2_ifu_aln_ctl.scala 144:50] + node _T_89 = or(_T_88, shift_2B) @[el2_ifu_aln_ctl.scala 144:64] + node f0_shift_wr_en = or(_T_89, shift_4B) @[el2_ifu_aln_ctl.scala 144:75] + node _T_90 = eq(rdptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 146:24] + node _T_91 = eq(rdptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 146:39] + node _T_92 = eq(rdptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 146:54] node _T_93 = cat(_T_90, _T_91) @[Cat.scala 29:58] node qren = cat(_T_93, _T_92) @[Cat.scala 29:58] - node _T_94 = eq(wrptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 148:24] - node _T_95 = and(_T_94, ifvalid) @[el2_ifu_aln_ctl.scala 148:32] - node _T_96 = eq(wrptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 148:49] - node _T_97 = and(_T_96, ifvalid) @[el2_ifu_aln_ctl.scala 148:57] - node _T_98 = eq(wrptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 148:74] - node _T_99 = and(_T_98, ifvalid) @[el2_ifu_aln_ctl.scala 148:82] + node _T_94 = eq(wrptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 147:24] + node _T_95 = and(_T_94, ifvalid) @[el2_ifu_aln_ctl.scala 147:32] + node _T_96 = eq(wrptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 147:49] + node _T_97 = and(_T_96, ifvalid) @[el2_ifu_aln_ctl.scala 147:57] + node _T_98 = eq(wrptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 147:74] + node _T_99 = and(_T_98, ifvalid) @[el2_ifu_aln_ctl.scala 147:82] node _T_100 = cat(_T_95, _T_97) @[Cat.scala 29:58] node qwen = cat(_T_100, _T_99) @[Cat.scala 29:58] - node _T_101 = bits(qren, 0, 0) @[el2_ifu_aln_ctl.scala 150:30] - node _T_102 = and(_T_101, io.ifu_fb_consume1) @[el2_ifu_aln_ctl.scala 150:34] - node _T_103 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 150:57] - node _T_104 = and(_T_102, _T_103) @[el2_ifu_aln_ctl.scala 150:55] - node _T_105 = bits(_T_104, 0, 0) @[el2_ifu_aln_ctl.scala 150:78] - node _T_106 = bits(qren, 1, 1) @[el2_ifu_aln_ctl.scala 151:30] - node _T_107 = and(_T_106, io.ifu_fb_consume1) @[el2_ifu_aln_ctl.scala 151:34] - node _T_108 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 151:57] - node _T_109 = and(_T_107, _T_108) @[el2_ifu_aln_ctl.scala 151:55] - node _T_110 = bits(_T_109, 0, 0) @[el2_ifu_aln_ctl.scala 151:78] - node _T_111 = bits(qren, 2, 2) @[el2_ifu_aln_ctl.scala 152:30] - node _T_112 = and(_T_111, io.ifu_fb_consume1) @[el2_ifu_aln_ctl.scala 152:34] - node _T_113 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 152:57] - node _T_114 = and(_T_112, _T_113) @[el2_ifu_aln_ctl.scala 152:55] - node _T_115 = bits(_T_114, 0, 0) @[el2_ifu_aln_ctl.scala 152:78] - node _T_116 = bits(qren, 0, 0) @[el2_ifu_aln_ctl.scala 153:30] - node _T_117 = and(_T_116, io.ifu_fb_consume2) @[el2_ifu_aln_ctl.scala 153:34] - node _T_118 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 153:57] - node _T_119 = and(_T_117, _T_118) @[el2_ifu_aln_ctl.scala 153:55] - node _T_120 = bits(_T_119, 0, 0) @[el2_ifu_aln_ctl.scala 153:78] - node _T_121 = bits(qren, 1, 1) @[el2_ifu_aln_ctl.scala 154:30] - node _T_122 = and(_T_121, io.ifu_fb_consume2) @[el2_ifu_aln_ctl.scala 154:34] - node _T_123 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 154:57] - node _T_124 = and(_T_122, _T_123) @[el2_ifu_aln_ctl.scala 154:55] - node _T_125 = bits(_T_124, 0, 0) @[el2_ifu_aln_ctl.scala 154:78] - node _T_126 = bits(qren, 2, 2) @[el2_ifu_aln_ctl.scala 155:30] - node _T_127 = and(_T_126, io.ifu_fb_consume2) @[el2_ifu_aln_ctl.scala 155:34] - node _T_128 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 155:57] - node _T_129 = and(_T_127, _T_128) @[el2_ifu_aln_ctl.scala 155:55] - node _T_130 = bits(_T_129, 0, 0) @[el2_ifu_aln_ctl.scala 155:78] - node _T_131 = eq(io.ifu_fb_consume1, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 156:26] - node _T_132 = eq(io.ifu_fb_consume2, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 156:48] - node _T_133 = and(_T_131, _T_132) @[el2_ifu_aln_ctl.scala 156:46] - node _T_134 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 156:70] - node _T_135 = and(_T_133, _T_134) @[el2_ifu_aln_ctl.scala 156:68] - node _T_136 = bits(_T_135, 0, 0) @[el2_ifu_aln_ctl.scala 156:91] + node _T_101 = bits(qren, 0, 0) @[el2_ifu_aln_ctl.scala 149:30] + node _T_102 = and(_T_101, io.ifu_fb_consume1) @[el2_ifu_aln_ctl.scala 149:34] + node _T_103 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 149:57] + node _T_104 = and(_T_102, _T_103) @[el2_ifu_aln_ctl.scala 149:55] + node _T_105 = bits(_T_104, 0, 0) @[el2_ifu_aln_ctl.scala 149:78] + node _T_106 = bits(qren, 1, 1) @[el2_ifu_aln_ctl.scala 150:30] + node _T_107 = and(_T_106, io.ifu_fb_consume1) @[el2_ifu_aln_ctl.scala 150:34] + node _T_108 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 150:57] + node _T_109 = and(_T_107, _T_108) @[el2_ifu_aln_ctl.scala 150:55] + node _T_110 = bits(_T_109, 0, 0) @[el2_ifu_aln_ctl.scala 150:78] + node _T_111 = bits(qren, 2, 2) @[el2_ifu_aln_ctl.scala 151:30] + node _T_112 = and(_T_111, io.ifu_fb_consume1) @[el2_ifu_aln_ctl.scala 151:34] + node _T_113 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 151:57] + node _T_114 = and(_T_112, _T_113) @[el2_ifu_aln_ctl.scala 151:55] + node _T_115 = bits(_T_114, 0, 0) @[el2_ifu_aln_ctl.scala 151:78] + node _T_116 = bits(qren, 0, 0) @[el2_ifu_aln_ctl.scala 152:30] + node _T_117 = and(_T_116, io.ifu_fb_consume2) @[el2_ifu_aln_ctl.scala 152:34] + node _T_118 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 152:57] + node _T_119 = and(_T_117, _T_118) @[el2_ifu_aln_ctl.scala 152:55] + node _T_120 = bits(_T_119, 0, 0) @[el2_ifu_aln_ctl.scala 152:78] + node _T_121 = bits(qren, 1, 1) @[el2_ifu_aln_ctl.scala 153:30] + node _T_122 = and(_T_121, io.ifu_fb_consume2) @[el2_ifu_aln_ctl.scala 153:34] + node _T_123 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 153:57] + node _T_124 = and(_T_122, _T_123) @[el2_ifu_aln_ctl.scala 153:55] + node _T_125 = bits(_T_124, 0, 0) @[el2_ifu_aln_ctl.scala 153:78] + node _T_126 = bits(qren, 2, 2) @[el2_ifu_aln_ctl.scala 154:30] + node _T_127 = and(_T_126, io.ifu_fb_consume2) @[el2_ifu_aln_ctl.scala 154:34] + node _T_128 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 154:57] + node _T_129 = and(_T_127, _T_128) @[el2_ifu_aln_ctl.scala 154:55] + node _T_130 = bits(_T_129, 0, 0) @[el2_ifu_aln_ctl.scala 154:78] + node _T_131 = eq(io.ifu_fb_consume1, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 155:26] + node _T_132 = eq(io.ifu_fb_consume2, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 155:48] + node _T_133 = and(_T_131, _T_132) @[el2_ifu_aln_ctl.scala 155:46] + node _T_134 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 155:70] + node _T_135 = and(_T_133, _T_134) @[el2_ifu_aln_ctl.scala 155:68] + node _T_136 = bits(_T_135, 0, 0) @[el2_ifu_aln_ctl.scala 155:91] node _T_137 = mux(_T_105, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_138 = mux(_T_110, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_139 = mux(_T_115, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] @@ -2131,23 +2131,23 @@ circuit el2_ifu_aln_ctl : node _T_149 = or(_T_148, _T_143) @[Mux.scala 27:72] wire _T_150 : UInt @[Mux.scala 27:72] _T_150 <= _T_149 @[Mux.scala 27:72] - rdptr_in <= _T_150 @[el2_ifu_aln_ctl.scala 150:12] - node _T_151 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 158:30] - node _T_152 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 158:36] - node _T_153 = and(_T_151, _T_152) @[el2_ifu_aln_ctl.scala 158:34] - node _T_154 = bits(_T_153, 0, 0) @[el2_ifu_aln_ctl.scala 158:57] - node _T_155 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 159:30] - node _T_156 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 159:36] - node _T_157 = and(_T_155, _T_156) @[el2_ifu_aln_ctl.scala 159:34] - node _T_158 = bits(_T_157, 0, 0) @[el2_ifu_aln_ctl.scala 159:57] - node _T_159 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 160:30] - node _T_160 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 160:36] - node _T_161 = and(_T_159, _T_160) @[el2_ifu_aln_ctl.scala 160:34] - node _T_162 = bits(_T_161, 0, 0) @[el2_ifu_aln_ctl.scala 160:57] - node _T_163 = eq(ifvalid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 161:26] - node _T_164 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 161:37] - node _T_165 = and(_T_163, _T_164) @[el2_ifu_aln_ctl.scala 161:35] - node _T_166 = bits(_T_165, 0, 0) @[el2_ifu_aln_ctl.scala 161:58] + rdptr_in <= _T_150 @[el2_ifu_aln_ctl.scala 149:12] + node _T_151 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 157:30] + node _T_152 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 157:36] + node _T_153 = and(_T_151, _T_152) @[el2_ifu_aln_ctl.scala 157:34] + node _T_154 = bits(_T_153, 0, 0) @[el2_ifu_aln_ctl.scala 157:57] + node _T_155 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 158:30] + node _T_156 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 158:36] + node _T_157 = and(_T_155, _T_156) @[el2_ifu_aln_ctl.scala 158:34] + node _T_158 = bits(_T_157, 0, 0) @[el2_ifu_aln_ctl.scala 158:57] + node _T_159 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 159:30] + node _T_160 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 159:36] + node _T_161 = and(_T_159, _T_160) @[el2_ifu_aln_ctl.scala 159:34] + node _T_162 = bits(_T_161, 0, 0) @[el2_ifu_aln_ctl.scala 159:57] + node _T_163 = eq(ifvalid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 160:26] + node _T_164 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 160:37] + node _T_165 = and(_T_163, _T_164) @[el2_ifu_aln_ctl.scala 160:35] + node _T_166 = bits(_T_165, 0, 0) @[el2_ifu_aln_ctl.scala 160:58] node _T_167 = mux(_T_154, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_168 = mux(_T_158, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_169 = mux(_T_162, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] @@ -2157,24 +2157,24 @@ circuit el2_ifu_aln_ctl : node _T_173 = or(_T_172, _T_170) @[Mux.scala 27:72] wire _T_174 : UInt @[Mux.scala 27:72] _T_174 <= _T_173 @[Mux.scala 27:72] - wrptr_in <= _T_174 @[el2_ifu_aln_ctl.scala 158:12] - node _T_175 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 163:31] - node _T_176 = eq(_T_175, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 163:26] - node _T_177 = eq(rdptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 163:43] - node _T_178 = and(_T_176, _T_177) @[el2_ifu_aln_ctl.scala 163:35] - node _T_179 = bits(_T_178, 0, 0) @[el2_ifu_aln_ctl.scala 163:52] - node _T_180 = or(q2off, f0_shift_2B) @[el2_ifu_aln_ctl.scala 163:74] - node _T_181 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 164:31] - node _T_182 = eq(_T_181, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 164:26] - node _T_183 = eq(rdptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 164:43] - node _T_184 = and(_T_182, _T_183) @[el2_ifu_aln_ctl.scala 164:35] - node _T_185 = bits(_T_184, 0, 0) @[el2_ifu_aln_ctl.scala 164:52] - node _T_186 = or(q2off, f1_shift_2B) @[el2_ifu_aln_ctl.scala 164:74] - node _T_187 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 165:31] - node _T_188 = eq(_T_187, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 165:26] - node _T_189 = eq(rdptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 165:43] - node _T_190 = and(_T_188, _T_189) @[el2_ifu_aln_ctl.scala 165:35] - node _T_191 = bits(_T_190, 0, 0) @[el2_ifu_aln_ctl.scala 165:52] + wrptr_in <= _T_174 @[el2_ifu_aln_ctl.scala 157:12] + node _T_175 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 162:31] + node _T_176 = eq(_T_175, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 162:26] + node _T_177 = eq(rdptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 162:43] + node _T_178 = and(_T_176, _T_177) @[el2_ifu_aln_ctl.scala 162:35] + node _T_179 = bits(_T_178, 0, 0) @[el2_ifu_aln_ctl.scala 162:52] + node _T_180 = or(q2off, f0_shift_2B) @[el2_ifu_aln_ctl.scala 162:74] + node _T_181 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 163:31] + node _T_182 = eq(_T_181, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 163:26] + node _T_183 = eq(rdptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 163:43] + node _T_184 = and(_T_182, _T_183) @[el2_ifu_aln_ctl.scala 163:35] + node _T_185 = bits(_T_184, 0, 0) @[el2_ifu_aln_ctl.scala 163:52] + node _T_186 = or(q2off, f1_shift_2B) @[el2_ifu_aln_ctl.scala 163:74] + node _T_187 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 164:31] + node _T_188 = eq(_T_187, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 164:26] + node _T_189 = eq(rdptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 164:43] + node _T_190 = and(_T_188, _T_189) @[el2_ifu_aln_ctl.scala 164:35] + node _T_191 = bits(_T_190, 0, 0) @[el2_ifu_aln_ctl.scala 164:52] node _T_192 = mux(_T_179, _T_180, UInt<1>("h00")) @[Mux.scala 27:72] node _T_193 = mux(_T_185, _T_186, UInt<1>("h00")) @[Mux.scala 27:72] node _T_194 = mux(_T_191, q2off, UInt<1>("h00")) @[Mux.scala 27:72] @@ -2182,24 +2182,24 @@ circuit el2_ifu_aln_ctl : node _T_196 = or(_T_195, _T_194) @[Mux.scala 27:72] wire _T_197 : UInt @[Mux.scala 27:72] _T_197 <= _T_196 @[Mux.scala 27:72] - q2off_in <= _T_197 @[el2_ifu_aln_ctl.scala 163:12] - node _T_198 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 167:31] - node _T_199 = eq(_T_198, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 167:26] - node _T_200 = eq(rdptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 167:43] - node _T_201 = and(_T_199, _T_200) @[el2_ifu_aln_ctl.scala 167:35] - node _T_202 = bits(_T_201, 0, 0) @[el2_ifu_aln_ctl.scala 167:52] - node _T_203 = or(q1off, f0_shift_2B) @[el2_ifu_aln_ctl.scala 167:74] - node _T_204 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 168:31] - node _T_205 = eq(_T_204, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 168:26] - node _T_206 = eq(rdptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 168:43] - node _T_207 = and(_T_205, _T_206) @[el2_ifu_aln_ctl.scala 168:35] - node _T_208 = bits(_T_207, 0, 0) @[el2_ifu_aln_ctl.scala 168:52] - node _T_209 = or(q1off, f1_shift_2B) @[el2_ifu_aln_ctl.scala 168:74] - node _T_210 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 169:31] - node _T_211 = eq(_T_210, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 169:26] - node _T_212 = eq(rdptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 169:43] - node _T_213 = and(_T_211, _T_212) @[el2_ifu_aln_ctl.scala 169:35] - node _T_214 = bits(_T_213, 0, 0) @[el2_ifu_aln_ctl.scala 169:52] + q2off_in <= _T_197 @[el2_ifu_aln_ctl.scala 162:12] + node _T_198 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 166:31] + node _T_199 = eq(_T_198, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 166:26] + node _T_200 = eq(rdptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 166:43] + node _T_201 = and(_T_199, _T_200) @[el2_ifu_aln_ctl.scala 166:35] + node _T_202 = bits(_T_201, 0, 0) @[el2_ifu_aln_ctl.scala 166:52] + node _T_203 = or(q1off, f0_shift_2B) @[el2_ifu_aln_ctl.scala 166:74] + node _T_204 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 167:31] + node _T_205 = eq(_T_204, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 167:26] + node _T_206 = eq(rdptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 167:43] + node _T_207 = and(_T_205, _T_206) @[el2_ifu_aln_ctl.scala 167:35] + node _T_208 = bits(_T_207, 0, 0) @[el2_ifu_aln_ctl.scala 167:52] + node _T_209 = or(q1off, f1_shift_2B) @[el2_ifu_aln_ctl.scala 167:74] + node _T_210 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 168:31] + node _T_211 = eq(_T_210, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 168:26] + node _T_212 = eq(rdptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 168:43] + node _T_213 = and(_T_211, _T_212) @[el2_ifu_aln_ctl.scala 168:35] + node _T_214 = bits(_T_213, 0, 0) @[el2_ifu_aln_ctl.scala 168:52] node _T_215 = mux(_T_202, _T_203, UInt<1>("h00")) @[Mux.scala 27:72] node _T_216 = mux(_T_208, _T_209, UInt<1>("h00")) @[Mux.scala 27:72] node _T_217 = mux(_T_214, q1off, UInt<1>("h00")) @[Mux.scala 27:72] @@ -2207,24 +2207,24 @@ circuit el2_ifu_aln_ctl : node _T_219 = or(_T_218, _T_217) @[Mux.scala 27:72] wire _T_220 : UInt @[Mux.scala 27:72] _T_220 <= _T_219 @[Mux.scala 27:72] - q1off_in <= _T_220 @[el2_ifu_aln_ctl.scala 167:12] - node _T_221 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 171:31] - node _T_222 = eq(_T_221, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 171:26] - node _T_223 = eq(rdptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 171:43] - node _T_224 = and(_T_222, _T_223) @[el2_ifu_aln_ctl.scala 171:35] - node _T_225 = bits(_T_224, 0, 0) @[el2_ifu_aln_ctl.scala 171:52] - node _T_226 = or(q0off, f0_shift_2B) @[el2_ifu_aln_ctl.scala 171:76] - node _T_227 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 172:31] - node _T_228 = eq(_T_227, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 172:26] - node _T_229 = eq(rdptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 172:43] - node _T_230 = and(_T_228, _T_229) @[el2_ifu_aln_ctl.scala 172:35] - node _T_231 = bits(_T_230, 0, 0) @[el2_ifu_aln_ctl.scala 172:52] - node _T_232 = or(q0off, f1_shift_2B) @[el2_ifu_aln_ctl.scala 172:76] - node _T_233 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 173:31] - node _T_234 = eq(_T_233, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 173:26] - node _T_235 = eq(rdptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 173:43] - node _T_236 = and(_T_234, _T_235) @[el2_ifu_aln_ctl.scala 173:35] - node _T_237 = bits(_T_236, 0, 0) @[el2_ifu_aln_ctl.scala 173:52] + q1off_in <= _T_220 @[el2_ifu_aln_ctl.scala 166:12] + node _T_221 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 170:31] + node _T_222 = eq(_T_221, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 170:26] + node _T_223 = eq(rdptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 170:43] + node _T_224 = and(_T_222, _T_223) @[el2_ifu_aln_ctl.scala 170:35] + node _T_225 = bits(_T_224, 0, 0) @[el2_ifu_aln_ctl.scala 170:52] + node _T_226 = or(q0off, f0_shift_2B) @[el2_ifu_aln_ctl.scala 170:76] + node _T_227 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 171:31] + node _T_228 = eq(_T_227, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 171:26] + node _T_229 = eq(rdptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 171:43] + node _T_230 = and(_T_228, _T_229) @[el2_ifu_aln_ctl.scala 171:35] + node _T_231 = bits(_T_230, 0, 0) @[el2_ifu_aln_ctl.scala 171:52] + node _T_232 = or(q0off, f1_shift_2B) @[el2_ifu_aln_ctl.scala 171:76] + node _T_233 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 172:31] + node _T_234 = eq(_T_233, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 172:26] + node _T_235 = eq(rdptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 172:43] + node _T_236 = and(_T_234, _T_235) @[el2_ifu_aln_ctl.scala 172:35] + node _T_237 = bits(_T_236, 0, 0) @[el2_ifu_aln_ctl.scala 172:52] node _T_238 = mux(_T_225, _T_226, UInt<1>("h00")) @[Mux.scala 27:72] node _T_239 = mux(_T_231, _T_232, UInt<1>("h00")) @[Mux.scala 27:72] node _T_240 = mux(_T_237, q0off, UInt<1>("h00")) @[Mux.scala 27:72] @@ -2232,10 +2232,10 @@ circuit el2_ifu_aln_ctl : node _T_242 = or(_T_241, _T_240) @[Mux.scala 27:72] wire _T_243 : UInt @[Mux.scala 27:72] _T_243 <= _T_242 @[Mux.scala 27:72] - q0off_in <= _T_243 @[el2_ifu_aln_ctl.scala 171:12] - node _T_244 = eq(rdptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 175:31] - node _T_245 = eq(rdptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 176:31] - node _T_246 = eq(rdptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 177:31] + q0off_in <= _T_243 @[el2_ifu_aln_ctl.scala 170:12] + node _T_244 = eq(rdptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 174:31] + node _T_245 = eq(rdptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 175:31] + node _T_246 = eq(rdptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 176:31] node _T_247 = mux(_T_244, q0off, UInt<1>("h00")) @[Mux.scala 27:72] node _T_248 = mux(_T_245, q1off, UInt<1>("h00")) @[Mux.scala 27:72] node _T_249 = mux(_T_246, q2off, UInt<1>("h00")) @[Mux.scala 27:72] @@ -2243,9 +2243,9 @@ circuit el2_ifu_aln_ctl : node _T_251 = or(_T_250, _T_249) @[Mux.scala 27:72] wire q0ptr : UInt @[Mux.scala 27:72] q0ptr <= _T_251 @[Mux.scala 27:72] - node _T_252 = eq(rdptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 179:32] - node _T_253 = eq(rdptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 179:57] - node _T_254 = eq(rdptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 179:83] + node _T_252 = eq(rdptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 178:32] + node _T_253 = eq(rdptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 178:57] + node _T_254 = eq(rdptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 178:83] node _T_255 = mux(_T_252, q1off, UInt<1>("h00")) @[Mux.scala 27:72] node _T_256 = mux(_T_253, q2off, UInt<1>("h00")) @[Mux.scala 27:72] node _T_257 = mux(_T_254, q0off, UInt<1>("h00")) @[Mux.scala 27:72] @@ -2253,24 +2253,24 @@ circuit el2_ifu_aln_ctl : node _T_259 = or(_T_258, _T_257) @[Mux.scala 27:72] wire q1ptr : UInt @[Mux.scala 27:72] q1ptr <= _T_259 @[Mux.scala 27:72] - node _T_260 = eq(q0ptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 181:26] + node _T_260 = eq(q0ptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 180:26] node q0sel = cat(q0ptr, _T_260) @[Cat.scala 29:58] - node _T_261 = eq(q1ptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 183:26] + node _T_261 = eq(q1ptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 182:26] node q1sel = cat(q1ptr, _T_261) @[Cat.scala 29:58] - node _T_262 = bits(io.ifu_bp_btb_target_f, 31, 1) @[el2_ifu_aln_ctl.scala 186:48] + node _T_262 = bits(io.ifu_bp_btb_target_f, 31, 1) @[el2_ifu_aln_ctl.scala 185:48] node _T_263 = cat(_T_262, io.ifu_bp_poffset_f) @[Cat.scala 29:58] node _T_264 = cat(_T_263, io.ifu_bp_fghr_f) @[Cat.scala 29:58] node _T_265 = cat(io.iccm_rd_ecc_double_err, io.ic_access_fault_f) @[Cat.scala 29:58] node _T_266 = cat(_T_265, io.ic_access_fault_type_f) @[Cat.scala 29:58] node misc_data_in = cat(_T_266, _T_264) @[Cat.scala 29:58] - node _T_267 = bits(qren, 0, 0) @[el2_ifu_aln_ctl.scala 188:31] - node _T_268 = bits(_T_267, 0, 0) @[el2_ifu_aln_ctl.scala 188:41] + node _T_267 = bits(qren, 0, 0) @[el2_ifu_aln_ctl.scala 187:31] + node _T_268 = bits(_T_267, 0, 0) @[el2_ifu_aln_ctl.scala 187:41] node _T_269 = cat(misc1, misc0) @[Cat.scala 29:58] - node _T_270 = bits(qren, 1, 1) @[el2_ifu_aln_ctl.scala 189:27] - node _T_271 = bits(_T_270, 0, 0) @[el2_ifu_aln_ctl.scala 189:37] + node _T_270 = bits(qren, 1, 1) @[el2_ifu_aln_ctl.scala 188:27] + node _T_271 = bits(_T_270, 0, 0) @[el2_ifu_aln_ctl.scala 188:37] node _T_272 = cat(misc2, misc1) @[Cat.scala 29:58] - node _T_273 = bits(qren, 2, 2) @[el2_ifu_aln_ctl.scala 190:27] - node _T_274 = bits(_T_273, 0, 0) @[el2_ifu_aln_ctl.scala 190:37] + node _T_273 = bits(qren, 2, 2) @[el2_ifu_aln_ctl.scala 189:27] + node _T_274 = bits(_T_273, 0, 0) @[el2_ifu_aln_ctl.scala 189:37] node _T_275 = cat(misc0, misc2) @[Cat.scala 29:58] node _T_276 = mux(_T_268, _T_269, UInt<1>("h00")) @[Mux.scala 27:72] node _T_277 = mux(_T_271, _T_272, UInt<1>("h00")) @[Mux.scala 27:72] @@ -2279,34 +2279,34 @@ circuit el2_ifu_aln_ctl : node _T_280 = or(_T_279, _T_278) @[Mux.scala 27:72] wire misceff : UInt<108> @[Mux.scala 27:72] misceff <= _T_280 @[Mux.scala 27:72] - node misc1eff = bits(misceff, 107, 55) @[el2_ifu_aln_ctl.scala 192:25] - node misc0eff = bits(misceff, 54, 0) @[el2_ifu_aln_ctl.scala 193:25] - node f1dbecc = bits(misc1eff, 52, 52) @[el2_ifu_aln_ctl.scala 195:25] - node _T_281 = bits(misc1eff, 51, 51) @[el2_ifu_aln_ctl.scala 196:21] - f1icaf <= _T_281 @[el2_ifu_aln_ctl.scala 196:10] - node f1ictype = bits(misc1eff, 50, 49) @[el2_ifu_aln_ctl.scala 197:26] - node f1prett = bits(misc1eff, 48, 18) @[el2_ifu_aln_ctl.scala 198:25] - node f1poffset = bits(misc1eff, 19, 8) @[el2_ifu_aln_ctl.scala 199:27] - node f1fghr = bits(misc1eff, 7, 0) @[el2_ifu_aln_ctl.scala 200:24] - node f0dbecc = bits(misc0eff, 54, 54) @[el2_ifu_aln_ctl.scala 202:25] - node _T_282 = bits(misc0eff, 53, 53) @[el2_ifu_aln_ctl.scala 203:21] - f0icaf <= _T_282 @[el2_ifu_aln_ctl.scala 203:10] - node f0ictype = bits(misc0eff, 52, 51) @[el2_ifu_aln_ctl.scala 204:26] - node f0prett = bits(misc0eff, 50, 20) @[el2_ifu_aln_ctl.scala 205:25] - node f0poffset = bits(misc0eff, 19, 8) @[el2_ifu_aln_ctl.scala 206:27] - node f0fghr = bits(misc0eff, 7, 0) @[el2_ifu_aln_ctl.scala 207:24] - node _T_283 = bits(io.ifu_bp_hist1_f, 1, 1) @[el2_ifu_aln_ctl.scala 209:40] - node _T_284 = bits(io.ifu_bp_hist0_f, 1, 1) @[el2_ifu_aln_ctl.scala 209:61] - node _T_285 = bits(io.ifu_bp_pc4_f, 1, 1) @[el2_ifu_aln_ctl.scala 209:80] - node _T_286 = bits(io.ifu_bp_way_f, 1, 1) @[el2_ifu_aln_ctl.scala 209:99] - node _T_287 = bits(io.ifu_bp_valid_f, 1, 1) @[el2_ifu_aln_ctl.scala 209:120] - node _T_288 = bits(io.ifu_bp_ret_f, 1, 1) @[el2_ifu_aln_ctl.scala 210:20] - node _T_289 = bits(io.ifu_bp_hist1_f, 0, 0) @[el2_ifu_aln_ctl.scala 210:42] - node _T_290 = bits(io.ifu_bp_hist0_f, 0, 0) @[el2_ifu_aln_ctl.scala 210:63] - node _T_291 = bits(io.ifu_bp_pc4_f, 0, 0) @[el2_ifu_aln_ctl.scala 210:82] - node _T_292 = bits(io.ifu_bp_way_f, 0, 0) @[el2_ifu_aln_ctl.scala 210:101] - node _T_293 = bits(io.ifu_bp_valid_f, 0, 0) @[el2_ifu_aln_ctl.scala 211:22] - node _T_294 = bits(io.ifu_bp_ret_f, 0, 0) @[el2_ifu_aln_ctl.scala 211:41] + node misc1eff = bits(misceff, 107, 55) @[el2_ifu_aln_ctl.scala 191:25] + node misc0eff = bits(misceff, 54, 0) @[el2_ifu_aln_ctl.scala 192:25] + node f1dbecc = bits(misc1eff, 52, 52) @[el2_ifu_aln_ctl.scala 194:25] + node _T_281 = bits(misc1eff, 51, 51) @[el2_ifu_aln_ctl.scala 195:21] + f1icaf <= _T_281 @[el2_ifu_aln_ctl.scala 195:10] + node f1ictype = bits(misc1eff, 50, 49) @[el2_ifu_aln_ctl.scala 196:26] + node f1prett = bits(misc1eff, 48, 18) @[el2_ifu_aln_ctl.scala 197:25] + node f1poffset = bits(misc1eff, 19, 8) @[el2_ifu_aln_ctl.scala 198:27] + node f1fghr = bits(misc1eff, 7, 0) @[el2_ifu_aln_ctl.scala 199:24] + node f0dbecc = bits(misc0eff, 54, 54) @[el2_ifu_aln_ctl.scala 201:25] + node _T_282 = bits(misc0eff, 53, 53) @[el2_ifu_aln_ctl.scala 202:21] + f0icaf <= _T_282 @[el2_ifu_aln_ctl.scala 202:10] + node f0ictype = bits(misc0eff, 52, 51) @[el2_ifu_aln_ctl.scala 203:26] + node f0prett = bits(misc0eff, 50, 20) @[el2_ifu_aln_ctl.scala 204:25] + node f0poffset = bits(misc0eff, 19, 8) @[el2_ifu_aln_ctl.scala 205:27] + node f0fghr = bits(misc0eff, 7, 0) @[el2_ifu_aln_ctl.scala 206:24] + node _T_283 = bits(io.ifu_bp_hist1_f, 1, 1) @[el2_ifu_aln_ctl.scala 208:40] + node _T_284 = bits(io.ifu_bp_hist0_f, 1, 1) @[el2_ifu_aln_ctl.scala 208:61] + node _T_285 = bits(io.ifu_bp_pc4_f, 1, 1) @[el2_ifu_aln_ctl.scala 208:80] + node _T_286 = bits(io.ifu_bp_way_f, 1, 1) @[el2_ifu_aln_ctl.scala 208:99] + node _T_287 = bits(io.ifu_bp_valid_f, 1, 1) @[el2_ifu_aln_ctl.scala 208:120] + node _T_288 = bits(io.ifu_bp_ret_f, 1, 1) @[el2_ifu_aln_ctl.scala 209:20] + node _T_289 = bits(io.ifu_bp_hist1_f, 0, 0) @[el2_ifu_aln_ctl.scala 209:42] + node _T_290 = bits(io.ifu_bp_hist0_f, 0, 0) @[el2_ifu_aln_ctl.scala 209:63] + node _T_291 = bits(io.ifu_bp_pc4_f, 0, 0) @[el2_ifu_aln_ctl.scala 209:82] + node _T_292 = bits(io.ifu_bp_way_f, 0, 0) @[el2_ifu_aln_ctl.scala 209:101] + node _T_293 = bits(io.ifu_bp_valid_f, 0, 0) @[el2_ifu_aln_ctl.scala 210:22] + node _T_294 = bits(io.ifu_bp_ret_f, 0, 0) @[el2_ifu_aln_ctl.scala 210:41] node _T_295 = cat(_T_292, _T_293) @[Cat.scala 29:58] node _T_296 = cat(_T_295, _T_294) @[Cat.scala 29:58] node _T_297 = cat(_T_289, _T_290) @[Cat.scala 29:58] @@ -2318,14 +2318,14 @@ circuit el2_ifu_aln_ctl : node _T_303 = cat(_T_302, _T_285) @[Cat.scala 29:58] node _T_304 = cat(_T_303, _T_301) @[Cat.scala 29:58] node brdata_in = cat(_T_304, _T_299) @[Cat.scala 29:58] - node _T_305 = bits(qren, 0, 0) @[el2_ifu_aln_ctl.scala 213:33] - node _T_306 = bits(_T_305, 0, 0) @[el2_ifu_aln_ctl.scala 213:37] + node _T_305 = bits(qren, 0, 0) @[el2_ifu_aln_ctl.scala 212:33] + node _T_306 = bits(_T_305, 0, 0) @[el2_ifu_aln_ctl.scala 212:37] node _T_307 = cat(brdata1, brdata0) @[Cat.scala 29:58] - node _T_308 = bits(qren, 1, 1) @[el2_ifu_aln_ctl.scala 214:33] - node _T_309 = bits(_T_308, 0, 0) @[el2_ifu_aln_ctl.scala 214:37] + node _T_308 = bits(qren, 1, 1) @[el2_ifu_aln_ctl.scala 213:33] + node _T_309 = bits(_T_308, 0, 0) @[el2_ifu_aln_ctl.scala 213:37] node _T_310 = cat(brdata2, brdata1) @[Cat.scala 29:58] - node _T_311 = bits(qren, 2, 2) @[el2_ifu_aln_ctl.scala 215:33] - node _T_312 = bits(_T_311, 0, 0) @[el2_ifu_aln_ctl.scala 215:37] + node _T_311 = bits(qren, 2, 2) @[el2_ifu_aln_ctl.scala 214:33] + node _T_312 = bits(_T_311, 0, 0) @[el2_ifu_aln_ctl.scala 214:37] node _T_313 = cat(brdata0, brdata2) @[Cat.scala 29:58] node _T_314 = mux(_T_306, _T_307, UInt<1>("h00")) @[Mux.scala 27:72] node _T_315 = mux(_T_309, _T_310, UInt<1>("h00")) @[Mux.scala 27:72] @@ -2334,22 +2334,22 @@ circuit el2_ifu_aln_ctl : node _T_318 = or(_T_317, _T_316) @[Mux.scala 27:72] wire brdataeff : UInt<24> @[Mux.scala 27:72] brdataeff <= _T_318 @[Mux.scala 27:72] - node brdata0eff = bits(brdataeff, 11, 0) @[el2_ifu_aln_ctl.scala 217:43] - node brdata1eff = bits(brdataeff, 23, 12) @[el2_ifu_aln_ctl.scala 217:61] + node brdata0eff = bits(brdataeff, 11, 0) @[el2_ifu_aln_ctl.scala 216:43] + node brdata1eff = bits(brdataeff, 23, 12) @[el2_ifu_aln_ctl.scala 216:61] wire q0 : UInt<32> q0 <= UInt<1>("h00") wire q1 : UInt<32> q1 <= UInt<1>("h00") wire q2 : UInt<32> q2 <= UInt<1>("h00") - node _T_319 = bits(qren, 0, 0) @[el2_ifu_aln_ctl.scala 223:28] - node _T_320 = bits(_T_319, 0, 0) @[el2_ifu_aln_ctl.scala 223:32] + node _T_319 = bits(qren, 0, 0) @[el2_ifu_aln_ctl.scala 222:28] + node _T_320 = bits(_T_319, 0, 0) @[el2_ifu_aln_ctl.scala 222:32] node _T_321 = cat(q1, q0) @[Cat.scala 29:58] - node _T_322 = bits(qren, 1, 1) @[el2_ifu_aln_ctl.scala 224:27] - node _T_323 = bits(_T_322, 0, 0) @[el2_ifu_aln_ctl.scala 224:31] + node _T_322 = bits(qren, 1, 1) @[el2_ifu_aln_ctl.scala 223:27] + node _T_323 = bits(_T_322, 0, 0) @[el2_ifu_aln_ctl.scala 223:31] node _T_324 = cat(q2, q1) @[Cat.scala 29:58] - node _T_325 = bits(qren, 2, 2) @[el2_ifu_aln_ctl.scala 225:27] - node _T_326 = bits(_T_325, 0, 0) @[el2_ifu_aln_ctl.scala 225:31] + node _T_325 = bits(qren, 2, 2) @[el2_ifu_aln_ctl.scala 224:27] + node _T_326 = bits(_T_325, 0, 0) @[el2_ifu_aln_ctl.scala 224:31] node _T_327 = cat(q0, q2) @[Cat.scala 29:58] node _T_328 = mux(_T_320, _T_321, UInt<1>("h00")) @[Mux.scala 27:72] node _T_329 = mux(_T_323, _T_324, UInt<1>("h00")) @[Mux.scala 27:72] @@ -2358,121 +2358,121 @@ circuit el2_ifu_aln_ctl : node _T_332 = or(_T_331, _T_330) @[Mux.scala 27:72] wire qeff : UInt<64> @[Mux.scala 27:72] qeff <= _T_332 @[Mux.scala 27:72] - node q1eff = bits(qeff, 63, 32) @[el2_ifu_aln_ctl.scala 226:29] - node q0eff = bits(qeff, 31, 0) @[el2_ifu_aln_ctl.scala 226:42] - node _T_333 = bits(q0sel, 0, 0) @[el2_ifu_aln_ctl.scala 227:37] - node _T_334 = bits(_T_333, 0, 0) @[el2_ifu_aln_ctl.scala 227:41] - node _T_335 = bits(q0sel, 1, 1) @[el2_ifu_aln_ctl.scala 227:68] - node _T_336 = bits(_T_335, 0, 0) @[el2_ifu_aln_ctl.scala 227:72] - node _T_337 = bits(brdata0eff, 11, 6) @[el2_ifu_aln_ctl.scala 227:92] + node q1eff = bits(qeff, 63, 32) @[el2_ifu_aln_ctl.scala 225:29] + node q0eff = bits(qeff, 31, 0) @[el2_ifu_aln_ctl.scala 225:42] + node _T_333 = bits(q0sel, 0, 0) @[el2_ifu_aln_ctl.scala 226:37] + node _T_334 = bits(_T_333, 0, 0) @[el2_ifu_aln_ctl.scala 226:41] + node _T_335 = bits(q0sel, 1, 1) @[el2_ifu_aln_ctl.scala 226:68] + node _T_336 = bits(_T_335, 0, 0) @[el2_ifu_aln_ctl.scala 226:72] + node _T_337 = bits(brdata0eff, 11, 6) @[el2_ifu_aln_ctl.scala 226:92] node _T_338 = mux(_T_334, brdata0eff, UInt<1>("h00")) @[Mux.scala 27:72] node _T_339 = mux(_T_336, _T_337, UInt<1>("h00")) @[Mux.scala 27:72] node _T_340 = or(_T_338, _T_339) @[Mux.scala 27:72] wire brdata0final : UInt<12> @[Mux.scala 27:72] brdata0final <= _T_340 @[Mux.scala 27:72] - node _T_341 = bits(q1sel, 0, 0) @[el2_ifu_aln_ctl.scala 229:37] - node _T_342 = bits(_T_341, 0, 0) @[el2_ifu_aln_ctl.scala 229:41] - node _T_343 = bits(q1sel, 1, 1) @[el2_ifu_aln_ctl.scala 229:68] - node _T_344 = bits(_T_343, 0, 0) @[el2_ifu_aln_ctl.scala 229:72] - node _T_345 = bits(brdata1eff, 11, 6) @[el2_ifu_aln_ctl.scala 229:92] + node _T_341 = bits(q1sel, 0, 0) @[el2_ifu_aln_ctl.scala 228:37] + node _T_342 = bits(_T_341, 0, 0) @[el2_ifu_aln_ctl.scala 228:41] + node _T_343 = bits(q1sel, 1, 1) @[el2_ifu_aln_ctl.scala 228:68] + node _T_344 = bits(_T_343, 0, 0) @[el2_ifu_aln_ctl.scala 228:72] + node _T_345 = bits(brdata1eff, 11, 6) @[el2_ifu_aln_ctl.scala 228:92] node _T_346 = mux(_T_342, brdata1eff, UInt<1>("h00")) @[Mux.scala 27:72] node _T_347 = mux(_T_344, _T_345, UInt<1>("h00")) @[Mux.scala 27:72] node _T_348 = or(_T_346, _T_347) @[Mux.scala 27:72] wire brdata1final : UInt<12> @[Mux.scala 27:72] brdata1final <= _T_348 @[Mux.scala 27:72] - node _T_349 = bits(brdata0final, 6, 6) @[el2_ifu_aln_ctl.scala 231:31] - node _T_350 = bits(brdata0final, 0, 0) @[el2_ifu_aln_ctl.scala 231:47] + node _T_349 = bits(brdata0final, 6, 6) @[el2_ifu_aln_ctl.scala 230:31] + node _T_350 = bits(brdata0final, 0, 0) @[el2_ifu_aln_ctl.scala 230:47] node f0ret = cat(_T_349, _T_350) @[Cat.scala 29:58] - node _T_351 = bits(brdata0final, 7, 7) @[el2_ifu_aln_ctl.scala 232:33] - node _T_352 = bits(brdata0final, 1, 1) @[el2_ifu_aln_ctl.scala 232:49] + node _T_351 = bits(brdata0final, 7, 7) @[el2_ifu_aln_ctl.scala 231:33] + node _T_352 = bits(brdata0final, 1, 1) @[el2_ifu_aln_ctl.scala 231:49] node f0brend = cat(_T_351, _T_352) @[Cat.scala 29:58] - node _T_353 = bits(brdata0final, 8, 8) @[el2_ifu_aln_ctl.scala 233:31] - node _T_354 = bits(brdata0final, 2, 2) @[el2_ifu_aln_ctl.scala 233:47] + node _T_353 = bits(brdata0final, 8, 8) @[el2_ifu_aln_ctl.scala 232:31] + node _T_354 = bits(brdata0final, 2, 2) @[el2_ifu_aln_ctl.scala 232:47] node f0way = cat(_T_353, _T_354) @[Cat.scala 29:58] - node _T_355 = bits(brdata0final, 9, 9) @[el2_ifu_aln_ctl.scala 234:31] - node _T_356 = bits(brdata0final, 3, 3) @[el2_ifu_aln_ctl.scala 234:47] + node _T_355 = bits(brdata0final, 9, 9) @[el2_ifu_aln_ctl.scala 233:31] + node _T_356 = bits(brdata0final, 3, 3) @[el2_ifu_aln_ctl.scala 233:47] node f0pc4 = cat(_T_355, _T_356) @[Cat.scala 29:58] - node _T_357 = bits(brdata0final, 10, 10) @[el2_ifu_aln_ctl.scala 235:33] - node _T_358 = bits(brdata0final, 4, 4) @[el2_ifu_aln_ctl.scala 235:50] + node _T_357 = bits(brdata0final, 10, 10) @[el2_ifu_aln_ctl.scala 234:33] + node _T_358 = bits(brdata0final, 4, 4) @[el2_ifu_aln_ctl.scala 234:50] node f0hist0 = cat(_T_357, _T_358) @[Cat.scala 29:58] - node _T_359 = bits(brdata0final, 11, 11) @[el2_ifu_aln_ctl.scala 236:33] - node _T_360 = bits(brdata0final, 5, 5) @[el2_ifu_aln_ctl.scala 236:50] + node _T_359 = bits(brdata0final, 11, 11) @[el2_ifu_aln_ctl.scala 235:33] + node _T_360 = bits(brdata0final, 5, 5) @[el2_ifu_aln_ctl.scala 235:50] node f0hist1 = cat(_T_359, _T_360) @[Cat.scala 29:58] - node _T_361 = bits(brdata1final, 6, 6) @[el2_ifu_aln_ctl.scala 238:31] - node _T_362 = bits(brdata1final, 0, 0) @[el2_ifu_aln_ctl.scala 238:47] + node _T_361 = bits(brdata1final, 6, 6) @[el2_ifu_aln_ctl.scala 237:31] + node _T_362 = bits(brdata1final, 0, 0) @[el2_ifu_aln_ctl.scala 237:47] node f1ret = cat(_T_361, _T_362) @[Cat.scala 29:58] - node _T_363 = bits(brdata1final, 7, 7) @[el2_ifu_aln_ctl.scala 239:33] - node _T_364 = bits(brdata1final, 1, 1) @[el2_ifu_aln_ctl.scala 239:49] + node _T_363 = bits(brdata1final, 7, 7) @[el2_ifu_aln_ctl.scala 238:33] + node _T_364 = bits(brdata1final, 1, 1) @[el2_ifu_aln_ctl.scala 238:49] node f1brend = cat(_T_363, _T_364) @[Cat.scala 29:58] - node _T_365 = bits(brdata1final, 8, 8) @[el2_ifu_aln_ctl.scala 240:31] - node _T_366 = bits(brdata1final, 2, 2) @[el2_ifu_aln_ctl.scala 240:47] + node _T_365 = bits(brdata1final, 8, 8) @[el2_ifu_aln_ctl.scala 239:31] + node _T_366 = bits(brdata1final, 2, 2) @[el2_ifu_aln_ctl.scala 239:47] node f1way = cat(_T_365, _T_366) @[Cat.scala 29:58] - node _T_367 = bits(brdata1final, 9, 9) @[el2_ifu_aln_ctl.scala 241:31] - node _T_368 = bits(brdata1final, 3, 3) @[el2_ifu_aln_ctl.scala 241:47] + node _T_367 = bits(brdata1final, 9, 9) @[el2_ifu_aln_ctl.scala 240:31] + node _T_368 = bits(brdata1final, 3, 3) @[el2_ifu_aln_ctl.scala 240:47] node f1pc4 = cat(_T_367, _T_368) @[Cat.scala 29:58] - node _T_369 = bits(brdata1final, 10, 10) @[el2_ifu_aln_ctl.scala 242:33] - node _T_370 = bits(brdata1final, 4, 4) @[el2_ifu_aln_ctl.scala 242:50] + node _T_369 = bits(brdata1final, 10, 10) @[el2_ifu_aln_ctl.scala 241:33] + node _T_370 = bits(brdata1final, 4, 4) @[el2_ifu_aln_ctl.scala 241:50] node f1hist0 = cat(_T_369, _T_370) @[Cat.scala 29:58] - node _T_371 = bits(brdata1final, 11, 11) @[el2_ifu_aln_ctl.scala 243:33] - node _T_372 = bits(brdata1final, 5, 5) @[el2_ifu_aln_ctl.scala 243:50] + node _T_371 = bits(brdata1final, 11, 11) @[el2_ifu_aln_ctl.scala 242:33] + node _T_372 = bits(brdata1final, 5, 5) @[el2_ifu_aln_ctl.scala 242:50] node f1hist1 = cat(_T_371, _T_372) @[Cat.scala 29:58] - node _T_373 = bits(f2val, 0, 0) @[el2_ifu_aln_ctl.scala 247:20] - f2_valid <= _T_373 @[el2_ifu_aln_ctl.scala 247:12] - node _T_374 = bits(sf1val, 0, 0) @[el2_ifu_aln_ctl.scala 248:22] - sf1_valid <= _T_374 @[el2_ifu_aln_ctl.scala 248:13] - node _T_375 = bits(sf0val, 0, 0) @[el2_ifu_aln_ctl.scala 249:22] - sf0_valid <= _T_375 @[el2_ifu_aln_ctl.scala 249:13] - node _T_376 = bits(sf0val, 0, 0) @[el2_ifu_aln_ctl.scala 251:28] - node _T_377 = eq(_T_376, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 251:21] - node _T_378 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 251:39] - node consume_fb0 = and(_T_377, _T_378) @[el2_ifu_aln_ctl.scala 251:32] - node _T_379 = bits(sf1val, 0, 0) @[el2_ifu_aln_ctl.scala 252:28] - node _T_380 = eq(_T_379, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 252:21] - node _T_381 = bits(f1val, 0, 0) @[el2_ifu_aln_ctl.scala 252:39] - node consume_fb1 = and(_T_380, _T_381) @[el2_ifu_aln_ctl.scala 252:32] - node _T_382 = eq(consume_fb1, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 254:39] - node _T_383 = and(consume_fb0, _T_382) @[el2_ifu_aln_ctl.scala 254:37] - node _T_384 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 254:54] - node _T_385 = and(_T_383, _T_384) @[el2_ifu_aln_ctl.scala 254:52] - io.ifu_fb_consume1 <= _T_385 @[el2_ifu_aln_ctl.scala 254:22] - node _T_386 = and(consume_fb0, consume_fb1) @[el2_ifu_aln_ctl.scala 255:37] - node _T_387 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 255:54] - node _T_388 = and(_T_386, _T_387) @[el2_ifu_aln_ctl.scala 255:52] - io.ifu_fb_consume2 <= _T_388 @[el2_ifu_aln_ctl.scala 255:22] - node _T_389 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_aln_ctl.scala 257:30] - ifvalid <= _T_389 @[el2_ifu_aln_ctl.scala 257:11] - node _T_390 = eq(sf0_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 259:18] - node _T_391 = and(_T_390, sf1_valid) @[el2_ifu_aln_ctl.scala 259:29] - shift_f1_f0 <= _T_391 @[el2_ifu_aln_ctl.scala 259:15] - node _T_392 = eq(sf0_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 260:18] - node _T_393 = eq(sf1_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 260:31] - node _T_394 = and(_T_392, _T_393) @[el2_ifu_aln_ctl.scala 260:29] - node _T_395 = and(_T_394, f2_valid) @[el2_ifu_aln_ctl.scala 260:42] - shift_f2_f0 <= _T_395 @[el2_ifu_aln_ctl.scala 260:15] - node _T_396 = eq(sf0_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 261:18] - node _T_397 = and(_T_396, sf1_valid) @[el2_ifu_aln_ctl.scala 261:29] - node _T_398 = and(_T_397, f2_valid) @[el2_ifu_aln_ctl.scala 261:42] - shift_f2_f1 <= _T_398 @[el2_ifu_aln_ctl.scala 261:15] + node _T_373 = bits(f2val, 0, 0) @[el2_ifu_aln_ctl.scala 246:20] + f2_valid <= _T_373 @[el2_ifu_aln_ctl.scala 246:12] + node _T_374 = bits(sf1val, 0, 0) @[el2_ifu_aln_ctl.scala 247:22] + sf1_valid <= _T_374 @[el2_ifu_aln_ctl.scala 247:13] + node _T_375 = bits(sf0val, 0, 0) @[el2_ifu_aln_ctl.scala 248:22] + sf0_valid <= _T_375 @[el2_ifu_aln_ctl.scala 248:13] + node _T_376 = bits(sf0val, 0, 0) @[el2_ifu_aln_ctl.scala 250:28] + node _T_377 = eq(_T_376, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 250:21] + node _T_378 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 250:39] + node consume_fb0 = and(_T_377, _T_378) @[el2_ifu_aln_ctl.scala 250:32] + node _T_379 = bits(sf1val, 0, 0) @[el2_ifu_aln_ctl.scala 251:28] + node _T_380 = eq(_T_379, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 251:21] + node _T_381 = bits(f1val, 0, 0) @[el2_ifu_aln_ctl.scala 251:39] + node consume_fb1 = and(_T_380, _T_381) @[el2_ifu_aln_ctl.scala 251:32] + node _T_382 = eq(consume_fb1, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 253:39] + node _T_383 = and(consume_fb0, _T_382) @[el2_ifu_aln_ctl.scala 253:37] + node _T_384 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 253:54] + node _T_385 = and(_T_383, _T_384) @[el2_ifu_aln_ctl.scala 253:52] + io.ifu_fb_consume1 <= _T_385 @[el2_ifu_aln_ctl.scala 253:22] + node _T_386 = and(consume_fb0, consume_fb1) @[el2_ifu_aln_ctl.scala 254:37] + node _T_387 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 254:54] + node _T_388 = and(_T_386, _T_387) @[el2_ifu_aln_ctl.scala 254:52] + io.ifu_fb_consume2 <= _T_388 @[el2_ifu_aln_ctl.scala 254:22] + node _T_389 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_aln_ctl.scala 256:30] + ifvalid <= _T_389 @[el2_ifu_aln_ctl.scala 256:11] + node _T_390 = eq(sf0_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 258:18] + node _T_391 = and(_T_390, sf1_valid) @[el2_ifu_aln_ctl.scala 258:29] + shift_f1_f0 <= _T_391 @[el2_ifu_aln_ctl.scala 258:15] + node _T_392 = eq(sf0_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 259:18] + node _T_393 = eq(sf1_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 259:31] + node _T_394 = and(_T_392, _T_393) @[el2_ifu_aln_ctl.scala 259:29] + node _T_395 = and(_T_394, f2_valid) @[el2_ifu_aln_ctl.scala 259:42] + shift_f2_f0 <= _T_395 @[el2_ifu_aln_ctl.scala 259:15] + node _T_396 = eq(sf0_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 260:18] + node _T_397 = and(_T_396, sf1_valid) @[el2_ifu_aln_ctl.scala 260:29] + node _T_398 = and(_T_397, f2_valid) @[el2_ifu_aln_ctl.scala 260:42] + shift_f2_f1 <= _T_398 @[el2_ifu_aln_ctl.scala 260:15] wire f0pc : UInt<31> f0pc <= UInt<1>("h00") wire f2pc : UInt<31> f2pc <= UInt<1>("h00") - node _T_399 = add(f0pc, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 266:25] - node f0pc_plus1 = tail(_T_399, 1) @[el2_ifu_aln_ctl.scala 266:25] + node _T_399 = add(f0pc, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 265:25] + node f0pc_plus1 = tail(_T_399, 1) @[el2_ifu_aln_ctl.scala 265:25] node _T_400 = bits(f1_shift_2B, 0, 0) @[Bitwise.scala 72:15] node _T_401 = mux(_T_400, UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12] - node _T_402 = and(_T_401, f0pc_plus1) @[el2_ifu_aln_ctl.scala 268:38] - node _T_403 = eq(f1_shift_2B, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 268:64] + node _T_402 = and(_T_401, f0pc_plus1) @[el2_ifu_aln_ctl.scala 267:38] + node _T_403 = eq(f1_shift_2B, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 267:64] node _T_404 = bits(_T_403, 0, 0) @[Bitwise.scala 72:15] node _T_405 = mux(_T_404, UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12] - node _T_406 = and(_T_405, f0pc) @[el2_ifu_aln_ctl.scala 268:78] - node sf1pc = or(_T_402, _T_406) @[el2_ifu_aln_ctl.scala 268:52] - node _T_407 = bits(fetch_to_f1, 0, 0) @[el2_ifu_aln_ctl.scala 270:39] - node _T_408 = bits(shift_f2_f1, 0, 0) @[el2_ifu_aln_ctl.scala 271:39] - node _T_409 = eq(fetch_to_f1, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 272:28] - node _T_410 = eq(shift_f2_f1, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 272:43] - node _T_411 = and(_T_409, _T_410) @[el2_ifu_aln_ctl.scala 272:41] - node _T_412 = bits(_T_411, 0, 0) @[el2_ifu_aln_ctl.scala 272:57] + node _T_406 = and(_T_405, f0pc) @[el2_ifu_aln_ctl.scala 267:78] + node sf1pc = or(_T_402, _T_406) @[el2_ifu_aln_ctl.scala 267:52] + node _T_407 = bits(fetch_to_f1, 0, 0) @[el2_ifu_aln_ctl.scala 269:39] + node _T_408 = bits(shift_f2_f1, 0, 0) @[el2_ifu_aln_ctl.scala 270:39] + node _T_409 = eq(fetch_to_f1, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 271:28] + node _T_410 = eq(shift_f2_f1, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 271:43] + node _T_411 = and(_T_409, _T_410) @[el2_ifu_aln_ctl.scala 271:41] + node _T_412 = bits(_T_411, 0, 0) @[el2_ifu_aln_ctl.scala 271:57] node _T_413 = mux(_T_407, io.ifu_fetch_pc, UInt<1>("h00")) @[Mux.scala 27:72] node _T_414 = mux(_T_408, f2pc, UInt<1>("h00")) @[Mux.scala 27:72] node _T_415 = mux(_T_412, sf1pc, UInt<1>("h00")) @[Mux.scala 27:72] @@ -2480,15 +2480,15 @@ circuit el2_ifu_aln_ctl : node _T_417 = or(_T_416, _T_415) @[Mux.scala 27:72] wire f1pc_in : UInt<32> @[Mux.scala 27:72] f1pc_in <= _T_417 @[Mux.scala 27:72] - node _T_418 = bits(fetch_to_f0, 0, 0) @[el2_ifu_aln_ctl.scala 274:39] - node _T_419 = bits(shift_f2_f0, 0, 0) @[el2_ifu_aln_ctl.scala 275:39] - node _T_420 = bits(shift_f1_f0, 0, 0) @[el2_ifu_aln_ctl.scala 276:39] - node _T_421 = eq(fetch_to_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 277:28] - node _T_422 = eq(shift_f2_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 277:43] - node _T_423 = and(_T_421, _T_422) @[el2_ifu_aln_ctl.scala 277:41] - node _T_424 = eq(shift_f1_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 277:58] - node _T_425 = and(_T_423, _T_424) @[el2_ifu_aln_ctl.scala 277:56] - node _T_426 = bits(_T_425, 0, 0) @[el2_ifu_aln_ctl.scala 277:72] + node _T_418 = bits(fetch_to_f0, 0, 0) @[el2_ifu_aln_ctl.scala 273:39] + node _T_419 = bits(shift_f2_f0, 0, 0) @[el2_ifu_aln_ctl.scala 274:39] + node _T_420 = bits(shift_f1_f0, 0, 0) @[el2_ifu_aln_ctl.scala 275:39] + node _T_421 = eq(fetch_to_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 276:28] + node _T_422 = eq(shift_f2_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 276:43] + node _T_423 = and(_T_421, _T_422) @[el2_ifu_aln_ctl.scala 276:41] + node _T_424 = eq(shift_f1_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 276:58] + node _T_425 = and(_T_423, _T_424) @[el2_ifu_aln_ctl.scala 276:56] + node _T_426 = bits(_T_425, 0, 0) @[el2_ifu_aln_ctl.scala 276:72] node _T_427 = mux(_T_418, io.ifu_fetch_pc, UInt<1>("h00")) @[Mux.scala 27:72] node _T_428 = mux(_T_419, f2pc, UInt<1>("h00")) @[Mux.scala 27:72] node _T_429 = mux(_T_420, sf1pc, UInt<1>("h00")) @[Mux.scala 27:72] @@ -2498,47 +2498,47 @@ circuit el2_ifu_aln_ctl : node _T_433 = or(_T_432, _T_430) @[Mux.scala 27:72] wire f0pc_in : UInt<32> @[Mux.scala 27:72] f0pc_in <= _T_433 @[Mux.scala 27:72] - node _T_434 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 279:40] - node _T_435 = and(f2_wr_en, _T_434) @[el2_ifu_aln_ctl.scala 279:38] - node _T_436 = bits(_T_435, 0, 0) @[el2_ifu_aln_ctl.scala 279:61] - node _T_437 = eq(f2_wr_en, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 280:6] - node _T_438 = eq(shift_f2_f1, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 280:21] - node _T_439 = and(_T_437, _T_438) @[el2_ifu_aln_ctl.scala 280:19] - node _T_440 = eq(shift_f2_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 280:36] - node _T_441 = and(_T_439, _T_440) @[el2_ifu_aln_ctl.scala 280:34] - node _T_442 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 280:51] - node _T_443 = and(_T_441, _T_442) @[el2_ifu_aln_ctl.scala 280:49] - node _T_444 = bits(_T_443, 0, 0) @[el2_ifu_aln_ctl.scala 280:72] + node _T_434 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 278:40] + node _T_435 = and(f2_wr_en, _T_434) @[el2_ifu_aln_ctl.scala 278:38] + node _T_436 = bits(_T_435, 0, 0) @[el2_ifu_aln_ctl.scala 278:61] + node _T_437 = eq(f2_wr_en, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 279:6] + node _T_438 = eq(shift_f2_f1, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 279:21] + node _T_439 = and(_T_437, _T_438) @[el2_ifu_aln_ctl.scala 279:19] + node _T_440 = eq(shift_f2_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 279:36] + node _T_441 = and(_T_439, _T_440) @[el2_ifu_aln_ctl.scala 279:34] + node _T_442 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 279:51] + node _T_443 = and(_T_441, _T_442) @[el2_ifu_aln_ctl.scala 279:49] + node _T_444 = bits(_T_443, 0, 0) @[el2_ifu_aln_ctl.scala 279:72] node _T_445 = mux(_T_436, io.ifu_fetch_val, UInt<1>("h00")) @[Mux.scala 27:72] node _T_446 = mux(_T_444, f2val, UInt<1>("h00")) @[Mux.scala 27:72] node _T_447 = or(_T_445, _T_446) @[Mux.scala 27:72] wire _T_448 : UInt @[Mux.scala 27:72] _T_448 <= _T_447 @[Mux.scala 27:72] - f2val_in <= _T_448 @[el2_ifu_aln_ctl.scala 279:12] - node _T_449 = bits(f1_shift_2B, 0, 0) @[el2_ifu_aln_ctl.scala 282:35] - node _T_450 = bits(f1val, 1, 1) @[el2_ifu_aln_ctl.scala 282:48] - node _T_451 = bits(f1_shift_2B, 0, 0) @[el2_ifu_aln_ctl.scala 282:66] - node _T_452 = eq(_T_451, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 282:53] + f2val_in <= _T_448 @[el2_ifu_aln_ctl.scala 278:12] + node _T_449 = bits(f1_shift_2B, 0, 0) @[el2_ifu_aln_ctl.scala 281:35] + node _T_450 = bits(f1val, 1, 1) @[el2_ifu_aln_ctl.scala 281:48] + node _T_451 = bits(f1_shift_2B, 0, 0) @[el2_ifu_aln_ctl.scala 281:66] + node _T_452 = eq(_T_451, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 281:53] node _T_453 = mux(_T_449, _T_450, UInt<1>("h00")) @[Mux.scala 27:72] node _T_454 = mux(_T_452, f1val, UInt<1>("h00")) @[Mux.scala 27:72] node _T_455 = or(_T_453, _T_454) @[Mux.scala 27:72] wire _T_456 : UInt @[Mux.scala 27:72] _T_456 <= _T_455 @[Mux.scala 27:72] - sf1val <= _T_456 @[el2_ifu_aln_ctl.scala 282:10] - node _T_457 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 284:40] - node _T_458 = and(fetch_to_f1, _T_457) @[el2_ifu_aln_ctl.scala 284:38] - node _T_459 = bits(_T_458, 0, 0) @[el2_ifu_aln_ctl.scala 284:61] - node _T_460 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 285:40] - node _T_461 = and(shift_f2_f1, _T_460) @[el2_ifu_aln_ctl.scala 285:38] - node _T_462 = bits(_T_461, 0, 0) @[el2_ifu_aln_ctl.scala 285:61] - node _T_463 = eq(fetch_to_f1, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 286:26] - node _T_464 = eq(shift_f2_f1, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 286:41] - node _T_465 = and(_T_463, _T_464) @[el2_ifu_aln_ctl.scala 286:39] - node _T_466 = eq(shift_f1_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 286:56] - node _T_467 = and(_T_465, _T_466) @[el2_ifu_aln_ctl.scala 286:54] - node _T_468 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 286:71] - node _T_469 = and(_T_467, _T_468) @[el2_ifu_aln_ctl.scala 286:69] - node _T_470 = bits(_T_469, 0, 0) @[el2_ifu_aln_ctl.scala 286:92] + sf1val <= _T_456 @[el2_ifu_aln_ctl.scala 281:10] + node _T_457 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 283:40] + node _T_458 = and(fetch_to_f1, _T_457) @[el2_ifu_aln_ctl.scala 283:38] + node _T_459 = bits(_T_458, 0, 0) @[el2_ifu_aln_ctl.scala 283:61] + node _T_460 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 284:40] + node _T_461 = and(shift_f2_f1, _T_460) @[el2_ifu_aln_ctl.scala 284:38] + node _T_462 = bits(_T_461, 0, 0) @[el2_ifu_aln_ctl.scala 284:61] + node _T_463 = eq(fetch_to_f1, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 285:26] + node _T_464 = eq(shift_f2_f1, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 285:41] + node _T_465 = and(_T_463, _T_464) @[el2_ifu_aln_ctl.scala 285:39] + node _T_466 = eq(shift_f1_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 285:56] + node _T_467 = and(_T_465, _T_466) @[el2_ifu_aln_ctl.scala 285:54] + node _T_468 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 285:71] + node _T_469 = and(_T_467, _T_468) @[el2_ifu_aln_ctl.scala 285:69] + node _T_470 = bits(_T_469, 0, 0) @[el2_ifu_aln_ctl.scala 285:92] node _T_471 = mux(_T_459, io.ifu_fetch_val, UInt<1>("h00")) @[Mux.scala 27:72] node _T_472 = mux(_T_462, f2val, UInt<1>("h00")) @[Mux.scala 27:72] node _T_473 = mux(_T_470, sf1val, UInt<1>("h00")) @[Mux.scala 27:72] @@ -2546,36 +2546,36 @@ circuit el2_ifu_aln_ctl : node _T_475 = or(_T_474, _T_473) @[Mux.scala 27:72] wire _T_476 : UInt @[Mux.scala 27:72] _T_476 <= _T_475 @[Mux.scala 27:72] - f1val_in <= _T_476 @[el2_ifu_aln_ctl.scala 284:12] - node _T_477 = bits(shift_2B, 0, 0) @[el2_ifu_aln_ctl.scala 288:31] - node _T_478 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 288:46] - node _T_479 = eq(shift_2B, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 288:52] - node _T_480 = eq(shift_4B, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 288:64] - node _T_481 = and(_T_479, _T_480) @[el2_ifu_aln_ctl.scala 288:62] - node _T_482 = bits(_T_481, 0, 0) @[el2_ifu_aln_ctl.scala 288:75] + f1val_in <= _T_476 @[el2_ifu_aln_ctl.scala 283:12] + node _T_477 = bits(shift_2B, 0, 0) @[el2_ifu_aln_ctl.scala 287:31] + node _T_478 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 287:46] + node _T_479 = eq(shift_2B, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 287:52] + node _T_480 = eq(shift_4B, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 287:64] + node _T_481 = and(_T_479, _T_480) @[el2_ifu_aln_ctl.scala 287:62] + node _T_482 = bits(_T_481, 0, 0) @[el2_ifu_aln_ctl.scala 287:75] node _T_483 = mux(_T_477, _T_478, UInt<1>("h00")) @[Mux.scala 27:72] node _T_484 = mux(_T_482, f0val, UInt<1>("h00")) @[Mux.scala 27:72] node _T_485 = or(_T_483, _T_484) @[Mux.scala 27:72] wire _T_486 : UInt @[Mux.scala 27:72] _T_486 <= _T_485 @[Mux.scala 27:72] - f0val <= _T_486 @[el2_ifu_aln_ctl.scala 288:9] - node _T_487 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 290:40] - node _T_488 = and(fetch_to_f0, _T_487) @[el2_ifu_aln_ctl.scala 290:38] - node _T_489 = bits(_T_488, 0, 0) @[el2_ifu_aln_ctl.scala 290:61] - node _T_490 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 291:40] - node _T_491 = and(shift_f2_f0, _T_490) @[el2_ifu_aln_ctl.scala 291:38] - node _T_492 = bits(_T_491, 0, 0) @[el2_ifu_aln_ctl.scala 291:61] - node _T_493 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 292:40] - node _T_494 = and(shift_f1_f0, _T_493) @[el2_ifu_aln_ctl.scala 292:38] - node _T_495 = bits(_T_494, 0, 0) @[el2_ifu_aln_ctl.scala 292:67] - node _T_496 = eq(fetch_to_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 293:26] - node _T_497 = eq(shift_f2_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 293:41] - node _T_498 = and(_T_496, _T_497) @[el2_ifu_aln_ctl.scala 293:39] - node _T_499 = eq(shift_f1_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 293:56] - node _T_500 = and(_T_498, _T_499) @[el2_ifu_aln_ctl.scala 293:54] - node _T_501 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 293:71] - node _T_502 = and(_T_500, _T_501) @[el2_ifu_aln_ctl.scala 293:69] - node _T_503 = bits(_T_502, 0, 0) @[el2_ifu_aln_ctl.scala 293:92] + f0val <= _T_486 @[el2_ifu_aln_ctl.scala 287:9] + node _T_487 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 289:40] + node _T_488 = and(fetch_to_f0, _T_487) @[el2_ifu_aln_ctl.scala 289:38] + node _T_489 = bits(_T_488, 0, 0) @[el2_ifu_aln_ctl.scala 289:61] + node _T_490 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 290:40] + node _T_491 = and(shift_f2_f0, _T_490) @[el2_ifu_aln_ctl.scala 290:38] + node _T_492 = bits(_T_491, 0, 0) @[el2_ifu_aln_ctl.scala 290:61] + node _T_493 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 291:40] + node _T_494 = and(shift_f1_f0, _T_493) @[el2_ifu_aln_ctl.scala 291:38] + node _T_495 = bits(_T_494, 0, 0) @[el2_ifu_aln_ctl.scala 291:67] + node _T_496 = eq(fetch_to_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 292:26] + node _T_497 = eq(shift_f2_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 292:41] + node _T_498 = and(_T_496, _T_497) @[el2_ifu_aln_ctl.scala 292:39] + node _T_499 = eq(shift_f1_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 292:56] + node _T_500 = and(_T_498, _T_499) @[el2_ifu_aln_ctl.scala 292:54] + node _T_501 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 292:71] + node _T_502 = and(_T_500, _T_501) @[el2_ifu_aln_ctl.scala 292:69] + node _T_503 = bits(_T_502, 0, 0) @[el2_ifu_aln_ctl.scala 292:92] node _T_504 = mux(_T_489, io.ifu_fetch_val, UInt<1>("h00")) @[Mux.scala 27:72] node _T_505 = mux(_T_492, f2val, UInt<1>("h00")) @[Mux.scala 27:72] node _T_506 = mux(_T_495, sf1val, UInt<1>("h00")) @[Mux.scala 27:72] @@ -2585,198 +2585,198 @@ circuit el2_ifu_aln_ctl : node _T_510 = or(_T_509, _T_507) @[Mux.scala 27:72] wire _T_511 : UInt @[Mux.scala 27:72] _T_511 <= _T_510 @[Mux.scala 27:72] - f0val_in <= _T_511 @[el2_ifu_aln_ctl.scala 290:12] - node _T_512 = bits(q0sel, 0, 0) @[el2_ifu_aln_ctl.scala 295:29] - node _T_513 = bits(_T_512, 0, 0) @[el2_ifu_aln_ctl.scala 295:33] - node _T_514 = bits(q0sel, 1, 1) @[el2_ifu_aln_ctl.scala 295:53] - node _T_515 = bits(_T_514, 0, 0) @[el2_ifu_aln_ctl.scala 295:57] - node _T_516 = bits(q0eff, 31, 16) @[el2_ifu_aln_ctl.scala 295:70] + f0val_in <= _T_511 @[el2_ifu_aln_ctl.scala 289:12] + node _T_512 = bits(q0sel, 0, 0) @[el2_ifu_aln_ctl.scala 294:29] + node _T_513 = bits(_T_512, 0, 0) @[el2_ifu_aln_ctl.scala 294:33] + node _T_514 = bits(q0sel, 1, 1) @[el2_ifu_aln_ctl.scala 294:53] + node _T_515 = bits(_T_514, 0, 0) @[el2_ifu_aln_ctl.scala 294:57] + node _T_516 = bits(q0eff, 31, 16) @[el2_ifu_aln_ctl.scala 294:70] node _T_517 = mux(_T_513, q0eff, UInt<1>("h00")) @[Mux.scala 27:72] node _T_518 = mux(_T_515, _T_516, UInt<1>("h00")) @[Mux.scala 27:72] node _T_519 = or(_T_517, _T_518) @[Mux.scala 27:72] wire _T_520 : UInt<32> @[Mux.scala 27:72] _T_520 <= _T_519 @[Mux.scala 27:72] - q0final <= _T_520 @[el2_ifu_aln_ctl.scala 295:11] - node _T_521 = bits(q1sel, 0, 0) @[el2_ifu_aln_ctl.scala 297:29] - node _T_522 = bits(_T_521, 0, 0) @[el2_ifu_aln_ctl.scala 297:33] - node _T_523 = bits(q1eff, 15, 0) @[el2_ifu_aln_ctl.scala 297:46] - node _T_524 = bits(q1sel, 1, 1) @[el2_ifu_aln_ctl.scala 297:59] - node _T_525 = bits(_T_524, 0, 0) @[el2_ifu_aln_ctl.scala 297:63] - node _T_526 = bits(q1eff, 31, 16) @[el2_ifu_aln_ctl.scala 297:76] + q0final <= _T_520 @[el2_ifu_aln_ctl.scala 294:11] + node _T_521 = bits(q1sel, 0, 0) @[el2_ifu_aln_ctl.scala 296:29] + node _T_522 = bits(_T_521, 0, 0) @[el2_ifu_aln_ctl.scala 296:33] + node _T_523 = bits(q1eff, 15, 0) @[el2_ifu_aln_ctl.scala 296:46] + node _T_524 = bits(q1sel, 1, 1) @[el2_ifu_aln_ctl.scala 296:59] + node _T_525 = bits(_T_524, 0, 0) @[el2_ifu_aln_ctl.scala 296:63] + node _T_526 = bits(q1eff, 31, 16) @[el2_ifu_aln_ctl.scala 296:76] node _T_527 = mux(_T_522, _T_523, UInt<1>("h00")) @[Mux.scala 27:72] node _T_528 = mux(_T_525, _T_526, UInt<1>("h00")) @[Mux.scala 27:72] node _T_529 = or(_T_527, _T_528) @[Mux.scala 27:72] wire _T_530 : UInt<16> @[Mux.scala 27:72] _T_530 <= _T_529 @[Mux.scala 27:72] - q1final <= _T_530 @[el2_ifu_aln_ctl.scala 297:11] - node _T_531 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 299:30] - node _T_532 = bits(_T_531, 0, 0) @[el2_ifu_aln_ctl.scala 299:34] - node _T_533 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 299:54] - node _T_534 = eq(_T_533, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 299:48] - node _T_535 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 299:65] - node _T_536 = and(_T_534, _T_535) @[el2_ifu_aln_ctl.scala 299:58] - node _T_537 = bits(f1val, 0, 0) @[el2_ifu_aln_ctl.scala 299:82] + q1final <= _T_530 @[el2_ifu_aln_ctl.scala 296:11] + node _T_531 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 298:30] + node _T_532 = bits(_T_531, 0, 0) @[el2_ifu_aln_ctl.scala 298:34] + node _T_533 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 298:54] + node _T_534 = eq(_T_533, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 298:48] + node _T_535 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 298:65] + node _T_536 = and(_T_534, _T_535) @[el2_ifu_aln_ctl.scala 298:58] + node _T_537 = bits(f1val, 0, 0) @[el2_ifu_aln_ctl.scala 298:82] node _T_538 = cat(_T_537, UInt<1>("h01")) @[Cat.scala 29:58] node _T_539 = mux(_T_532, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_540 = mux(_T_536, _T_538, UInt<1>("h00")) @[Mux.scala 27:72] node _T_541 = or(_T_539, _T_540) @[Mux.scala 27:72] wire _T_542 : UInt<2> @[Mux.scala 27:72] _T_542 <= _T_541 @[Mux.scala 27:72] - alignval <= _T_542 @[el2_ifu_aln_ctl.scala 299:12] - node _T_543 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 301:35] - node _T_544 = bits(_T_543, 0, 0) @[el2_ifu_aln_ctl.scala 301:39] + alignval <= _T_542 @[el2_ifu_aln_ctl.scala 298:12] + node _T_543 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 300:35] + node _T_544 = bits(_T_543, 0, 0) @[el2_ifu_aln_ctl.scala 300:39] node _T_545 = bits(f0dbecc, 0, 0) @[Bitwise.scala 72:15] node _T_546 = mux(_T_545, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_547 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 301:73] - node _T_548 = eq(_T_547, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 301:67] - node _T_549 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 301:84] - node _T_550 = and(_T_548, _T_549) @[el2_ifu_aln_ctl.scala 301:77] - node _T_551 = bits(_T_550, 0, 0) @[el2_ifu_aln_ctl.scala 301:89] + node _T_547 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 300:73] + node _T_548 = eq(_T_547, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 300:67] + node _T_549 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 300:84] + node _T_550 = and(_T_548, _T_549) @[el2_ifu_aln_ctl.scala 300:77] + node _T_551 = bits(_T_550, 0, 0) @[el2_ifu_aln_ctl.scala 300:89] node _T_552 = cat(f1dbecc, f0dbecc) @[Cat.scala 29:58] node _T_553 = mux(_T_544, _T_546, UInt<1>("h00")) @[Mux.scala 27:72] node _T_554 = mux(_T_551, _T_552, UInt<1>("h00")) @[Mux.scala 27:72] node _T_555 = or(_T_553, _T_554) @[Mux.scala 27:72] wire aligndbecc : UInt<2> @[Mux.scala 27:72] aligndbecc <= _T_555 @[Mux.scala 27:72] - node _T_556 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 303:35] - node _T_557 = bits(_T_556, 0, 0) @[el2_ifu_aln_ctl.scala 303:45] - node _T_558 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 303:65] - node _T_559 = eq(_T_558, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 303:59] - node _T_560 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 303:76] - node _T_561 = and(_T_559, _T_560) @[el2_ifu_aln_ctl.scala 303:69] - node _T_562 = bits(_T_561, 0, 0) @[el2_ifu_aln_ctl.scala 303:81] - node _T_563 = bits(f1brend, 0, 0) @[el2_ifu_aln_ctl.scala 303:100] - node _T_564 = bits(f0brend, 0, 0) @[el2_ifu_aln_ctl.scala 303:111] + node _T_556 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 302:35] + node _T_557 = bits(_T_556, 0, 0) @[el2_ifu_aln_ctl.scala 302:45] + node _T_558 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 302:65] + node _T_559 = eq(_T_558, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 302:59] + node _T_560 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 302:76] + node _T_561 = and(_T_559, _T_560) @[el2_ifu_aln_ctl.scala 302:69] + node _T_562 = bits(_T_561, 0, 0) @[el2_ifu_aln_ctl.scala 302:81] + node _T_563 = bits(f1brend, 0, 0) @[el2_ifu_aln_ctl.scala 302:100] + node _T_564 = bits(f0brend, 0, 0) @[el2_ifu_aln_ctl.scala 302:111] node _T_565 = cat(_T_563, _T_564) @[Cat.scala 29:58] node _T_566 = mux(_T_557, f0brend, UInt<1>("h00")) @[Mux.scala 27:72] node _T_567 = mux(_T_562, _T_565, UInt<1>("h00")) @[Mux.scala 27:72] node _T_568 = or(_T_566, _T_567) @[Mux.scala 27:72] wire alignbrend : UInt<2> @[Mux.scala 27:72] alignbrend <= _T_568 @[Mux.scala 27:72] - node _T_569 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 305:33] - node _T_570 = bits(_T_569, 0, 0) @[el2_ifu_aln_ctl.scala 305:43] - node _T_571 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 305:61] - node _T_572 = eq(_T_571, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 305:55] - node _T_573 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 305:72] - node _T_574 = and(_T_572, _T_573) @[el2_ifu_aln_ctl.scala 305:65] - node _T_575 = bits(_T_574, 0, 0) @[el2_ifu_aln_ctl.scala 305:77] - node _T_576 = bits(f1pc4, 0, 0) @[el2_ifu_aln_ctl.scala 305:94] - node _T_577 = bits(f0pc4, 0, 0) @[el2_ifu_aln_ctl.scala 305:103] + node _T_569 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 304:33] + node _T_570 = bits(_T_569, 0, 0) @[el2_ifu_aln_ctl.scala 304:43] + node _T_571 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 304:61] + node _T_572 = eq(_T_571, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 304:55] + node _T_573 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 304:72] + node _T_574 = and(_T_572, _T_573) @[el2_ifu_aln_ctl.scala 304:65] + node _T_575 = bits(_T_574, 0, 0) @[el2_ifu_aln_ctl.scala 304:77] + node _T_576 = bits(f1pc4, 0, 0) @[el2_ifu_aln_ctl.scala 304:94] + node _T_577 = bits(f0pc4, 0, 0) @[el2_ifu_aln_ctl.scala 304:103] node _T_578 = cat(_T_576, _T_577) @[Cat.scala 29:58] node _T_579 = mux(_T_570, f0pc4, UInt<1>("h00")) @[Mux.scala 27:72] node _T_580 = mux(_T_575, _T_578, UInt<1>("h00")) @[Mux.scala 27:72] node _T_581 = or(_T_579, _T_580) @[Mux.scala 27:72] wire alignpc4 : UInt<2> @[Mux.scala 27:72] alignpc4 <= _T_581 @[Mux.scala 27:72] - node _T_582 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 307:33] - node _T_583 = bits(_T_582, 0, 0) @[el2_ifu_aln_ctl.scala 307:43] - node _T_584 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 307:61] - node _T_585 = eq(_T_584, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 307:55] - node _T_586 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 307:72] - node _T_587 = and(_T_585, _T_586) @[el2_ifu_aln_ctl.scala 307:65] - node _T_588 = bits(_T_587, 0, 0) @[el2_ifu_aln_ctl.scala 307:77] - node _T_589 = bits(f1ret, 0, 0) @[el2_ifu_aln_ctl.scala 307:94] - node _T_590 = bits(f0ret, 0, 0) @[el2_ifu_aln_ctl.scala 307:103] + node _T_582 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 306:33] + node _T_583 = bits(_T_582, 0, 0) @[el2_ifu_aln_ctl.scala 306:43] + node _T_584 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 306:61] + node _T_585 = eq(_T_584, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 306:55] + node _T_586 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 306:72] + node _T_587 = and(_T_585, _T_586) @[el2_ifu_aln_ctl.scala 306:65] + node _T_588 = bits(_T_587, 0, 0) @[el2_ifu_aln_ctl.scala 306:77] + node _T_589 = bits(f1ret, 0, 0) @[el2_ifu_aln_ctl.scala 306:94] + node _T_590 = bits(f0ret, 0, 0) @[el2_ifu_aln_ctl.scala 306:103] node _T_591 = cat(_T_589, _T_590) @[Cat.scala 29:58] node _T_592 = mux(_T_583, f0ret, UInt<1>("h00")) @[Mux.scala 27:72] node _T_593 = mux(_T_588, _T_591, UInt<1>("h00")) @[Mux.scala 27:72] node _T_594 = or(_T_592, _T_593) @[Mux.scala 27:72] wire alignret : UInt<2> @[Mux.scala 27:72] alignret <= _T_594 @[Mux.scala 27:72] - node _T_595 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 309:33] - node _T_596 = bits(_T_595, 0, 0) @[el2_ifu_aln_ctl.scala 309:43] - node _T_597 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 309:61] - node _T_598 = eq(_T_597, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 309:55] - node _T_599 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 309:72] - node _T_600 = and(_T_598, _T_599) @[el2_ifu_aln_ctl.scala 309:65] - node _T_601 = bits(_T_600, 0, 0) @[el2_ifu_aln_ctl.scala 309:77] - node _T_602 = bits(f1way, 0, 0) @[el2_ifu_aln_ctl.scala 309:94] - node _T_603 = bits(f0way, 0, 0) @[el2_ifu_aln_ctl.scala 309:103] + node _T_595 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 308:33] + node _T_596 = bits(_T_595, 0, 0) @[el2_ifu_aln_ctl.scala 308:43] + node _T_597 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 308:61] + node _T_598 = eq(_T_597, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 308:55] + node _T_599 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 308:72] + node _T_600 = and(_T_598, _T_599) @[el2_ifu_aln_ctl.scala 308:65] + node _T_601 = bits(_T_600, 0, 0) @[el2_ifu_aln_ctl.scala 308:77] + node _T_602 = bits(f1way, 0, 0) @[el2_ifu_aln_ctl.scala 308:94] + node _T_603 = bits(f0way, 0, 0) @[el2_ifu_aln_ctl.scala 308:103] node _T_604 = cat(_T_602, _T_603) @[Cat.scala 29:58] node _T_605 = mux(_T_596, f0way, UInt<1>("h00")) @[Mux.scala 27:72] node _T_606 = mux(_T_601, _T_604, UInt<1>("h00")) @[Mux.scala 27:72] node _T_607 = or(_T_605, _T_606) @[Mux.scala 27:72] wire alignway : UInt<2> @[Mux.scala 27:72] alignway <= _T_607 @[Mux.scala 27:72] - node _T_608 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 311:35] - node _T_609 = bits(_T_608, 0, 0) @[el2_ifu_aln_ctl.scala 311:45] - node _T_610 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 311:65] - node _T_611 = eq(_T_610, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 311:59] - node _T_612 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 311:76] - node _T_613 = and(_T_611, _T_612) @[el2_ifu_aln_ctl.scala 311:69] - node _T_614 = bits(_T_613, 0, 0) @[el2_ifu_aln_ctl.scala 311:81] - node _T_615 = bits(f1hist1, 0, 0) @[el2_ifu_aln_ctl.scala 311:100] - node _T_616 = bits(f0hist1, 0, 0) @[el2_ifu_aln_ctl.scala 311:111] + node _T_608 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 310:35] + node _T_609 = bits(_T_608, 0, 0) @[el2_ifu_aln_ctl.scala 310:45] + node _T_610 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 310:65] + node _T_611 = eq(_T_610, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 310:59] + node _T_612 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 310:76] + node _T_613 = and(_T_611, _T_612) @[el2_ifu_aln_ctl.scala 310:69] + node _T_614 = bits(_T_613, 0, 0) @[el2_ifu_aln_ctl.scala 310:81] + node _T_615 = bits(f1hist1, 0, 0) @[el2_ifu_aln_ctl.scala 310:100] + node _T_616 = bits(f0hist1, 0, 0) @[el2_ifu_aln_ctl.scala 310:111] node _T_617 = cat(_T_615, _T_616) @[Cat.scala 29:58] node _T_618 = mux(_T_609, f0hist1, UInt<1>("h00")) @[Mux.scala 27:72] node _T_619 = mux(_T_614, _T_617, UInt<1>("h00")) @[Mux.scala 27:72] node _T_620 = or(_T_618, _T_619) @[Mux.scala 27:72] wire alignhist1 : UInt<2> @[Mux.scala 27:72] alignhist1 <= _T_620 @[Mux.scala 27:72] - node _T_621 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 313:35] - node _T_622 = bits(_T_621, 0, 0) @[el2_ifu_aln_ctl.scala 313:45] - node _T_623 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 313:65] - node _T_624 = eq(_T_623, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 313:59] - node _T_625 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 313:76] - node _T_626 = and(_T_624, _T_625) @[el2_ifu_aln_ctl.scala 313:69] - node _T_627 = bits(_T_626, 0, 0) @[el2_ifu_aln_ctl.scala 313:81] - node _T_628 = bits(f1hist0, 0, 0) @[el2_ifu_aln_ctl.scala 313:100] - node _T_629 = bits(f0hist0, 0, 0) @[el2_ifu_aln_ctl.scala 313:111] + node _T_621 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 312:35] + node _T_622 = bits(_T_621, 0, 0) @[el2_ifu_aln_ctl.scala 312:45] + node _T_623 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 312:65] + node _T_624 = eq(_T_623, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 312:59] + node _T_625 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 312:76] + node _T_626 = and(_T_624, _T_625) @[el2_ifu_aln_ctl.scala 312:69] + node _T_627 = bits(_T_626, 0, 0) @[el2_ifu_aln_ctl.scala 312:81] + node _T_628 = bits(f1hist0, 0, 0) @[el2_ifu_aln_ctl.scala 312:100] + node _T_629 = bits(f0hist0, 0, 0) @[el2_ifu_aln_ctl.scala 312:111] node _T_630 = cat(_T_628, _T_629) @[Cat.scala 29:58] node _T_631 = mux(_T_622, f0hist0, UInt<1>("h00")) @[Mux.scala 27:72] node _T_632 = mux(_T_627, _T_630, UInt<1>("h00")) @[Mux.scala 27:72] node _T_633 = or(_T_631, _T_632) @[Mux.scala 27:72] wire alignhist0 : UInt<2> @[Mux.scala 27:72] alignhist0 <= _T_633 @[Mux.scala 27:72] - node _T_634 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 315:27] - node _T_635 = eq(_T_634, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 315:21] - node _T_636 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 315:38] - node alignfromf1 = and(_T_635, _T_636) @[el2_ifu_aln_ctl.scala 315:31] + node _T_634 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 314:27] + node _T_635 = eq(_T_634, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 314:21] + node _T_636 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 314:38] + node alignfromf1 = and(_T_635, _T_636) @[el2_ifu_aln_ctl.scala 314:31] wire f1pc : UInt<31> f1pc <= UInt<1>("h00") - node _T_637 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 319:33] - node _T_638 = bits(_T_637, 0, 0) @[el2_ifu_aln_ctl.scala 319:43] - node _T_639 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 319:67] - node _T_640 = eq(_T_639, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 319:61] - node _T_641 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 319:78] - node _T_642 = and(_T_640, _T_641) @[el2_ifu_aln_ctl.scala 319:71] - node _T_643 = bits(_T_642, 0, 0) @[el2_ifu_aln_ctl.scala 319:83] + node _T_637 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 318:33] + node _T_638 = bits(_T_637, 0, 0) @[el2_ifu_aln_ctl.scala 318:43] + node _T_639 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 318:67] + node _T_640 = eq(_T_639, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 318:61] + node _T_641 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 318:78] + node _T_642 = and(_T_640, _T_641) @[el2_ifu_aln_ctl.scala 318:71] + node _T_643 = bits(_T_642, 0, 0) @[el2_ifu_aln_ctl.scala 318:83] node _T_644 = mux(_T_638, f0pc_plus1, UInt<1>("h00")) @[Mux.scala 27:72] node _T_645 = mux(_T_643, f1pc, UInt<1>("h00")) @[Mux.scala 27:72] node _T_646 = or(_T_644, _T_645) @[Mux.scala 27:72] wire secondpc : UInt<31> @[Mux.scala 27:72] secondpc <= _T_646 @[Mux.scala 27:72] - io.ifu_i0_pc <= f0pc @[el2_ifu_aln_ctl.scala 321:16] - node _T_647 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 325:47] - node _T_648 = eq(_T_647, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 325:41] - node _T_649 = and(first4B, _T_648) @[el2_ifu_aln_ctl.scala 325:39] - node _T_650 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 325:58] - node _T_651 = and(_T_649, _T_650) @[el2_ifu_aln_ctl.scala 325:51] - node _T_652 = bits(alignicaf, 0, 0) @[el2_ifu_aln_ctl.scala 325:74] - node _T_653 = eq(_T_652, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 325:64] - node _T_654 = and(_T_651, _T_653) @[el2_ifu_aln_ctl.scala 325:62] - node _T_655 = bits(aligndbecc, 0, 0) @[el2_ifu_aln_ctl.scala 325:91] - node _T_656 = eq(_T_655, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 325:80] - node _T_657 = and(_T_654, _T_656) @[el2_ifu_aln_ctl.scala 325:78] - node _T_658 = bits(_T_657, 0, 0) @[el2_ifu_aln_ctl.scala 325:96] - node _T_659 = mux(_T_658, f1ictype, f0ictype) @[el2_ifu_aln_ctl.scala 325:29] - io.ifu_i0_icaf_type <= _T_659 @[el2_ifu_aln_ctl.scala 325:23] - node _T_660 = bits(alignicaf, 1, 1) @[el2_ifu_aln_ctl.scala 327:27] - node _T_661 = bits(aligndbecc, 1, 1) @[el2_ifu_aln_ctl.scala 327:43] - node icaf_eff = or(_T_660, _T_661) @[el2_ifu_aln_ctl.scala 327:31] - node _T_662 = and(first4B, icaf_eff) @[el2_ifu_aln_ctl.scala 329:32] - node _T_663 = and(_T_662, alignfromf1) @[el2_ifu_aln_ctl.scala 329:43] - io.ifu_i0_icaf_f1 <= _T_663 @[el2_ifu_aln_ctl.scala 329:21] - node _T_664 = bits(first4B, 0, 0) @[el2_ifu_aln_ctl.scala 331:40] - node _T_665 = orr(aligndbecc) @[el2_ifu_aln_ctl.scala 331:59] - node _T_666 = bits(first2B, 0, 0) @[el2_ifu_aln_ctl.scala 331:72] - node _T_667 = bits(aligndbecc, 0, 0) @[el2_ifu_aln_ctl.scala 331:90] + io.ifu_i0_pc <= f0pc @[el2_ifu_aln_ctl.scala 320:16] + node _T_647 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 324:47] + node _T_648 = eq(_T_647, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 324:41] + node _T_649 = and(first4B, _T_648) @[el2_ifu_aln_ctl.scala 324:39] + node _T_650 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 324:58] + node _T_651 = and(_T_649, _T_650) @[el2_ifu_aln_ctl.scala 324:51] + node _T_652 = bits(alignicaf, 0, 0) @[el2_ifu_aln_ctl.scala 324:74] + node _T_653 = eq(_T_652, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 324:64] + node _T_654 = and(_T_651, _T_653) @[el2_ifu_aln_ctl.scala 324:62] + node _T_655 = bits(aligndbecc, 0, 0) @[el2_ifu_aln_ctl.scala 324:91] + node _T_656 = eq(_T_655, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 324:80] + node _T_657 = and(_T_654, _T_656) @[el2_ifu_aln_ctl.scala 324:78] + node _T_658 = bits(_T_657, 0, 0) @[el2_ifu_aln_ctl.scala 324:96] + node _T_659 = mux(_T_658, f1ictype, f0ictype) @[el2_ifu_aln_ctl.scala 324:29] + io.ifu_i0_icaf_type <= _T_659 @[el2_ifu_aln_ctl.scala 324:23] + node _T_660 = bits(alignicaf, 1, 1) @[el2_ifu_aln_ctl.scala 326:27] + node _T_661 = bits(aligndbecc, 1, 1) @[el2_ifu_aln_ctl.scala 326:43] + node icaf_eff = or(_T_660, _T_661) @[el2_ifu_aln_ctl.scala 326:31] + node _T_662 = and(first4B, icaf_eff) @[el2_ifu_aln_ctl.scala 328:32] + node _T_663 = and(_T_662, alignfromf1) @[el2_ifu_aln_ctl.scala 328:43] + io.ifu_i0_icaf_f1 <= _T_663 @[el2_ifu_aln_ctl.scala 328:21] + node _T_664 = bits(first4B, 0, 0) @[el2_ifu_aln_ctl.scala 330:40] + node _T_665 = orr(aligndbecc) @[el2_ifu_aln_ctl.scala 330:59] + node _T_666 = bits(first2B, 0, 0) @[el2_ifu_aln_ctl.scala 330:72] + node _T_667 = bits(aligndbecc, 0, 0) @[el2_ifu_aln_ctl.scala 330:90] node _T_668 = mux(_T_664, _T_665, UInt<1>("h00")) @[Mux.scala 27:72] node _T_669 = mux(_T_666, _T_667, UInt<1>("h00")) @[Mux.scala 27:72] node _T_670 = or(_T_668, _T_669) @[Mux.scala 27:72] wire _T_671 : UInt<1> @[Mux.scala 27:72] _T_671 <= _T_670 @[Mux.scala 27:72] - io.ifu_i0_dbecc <= _T_671 @[el2_ifu_aln_ctl.scala 331:19] + io.ifu_i0_dbecc <= _T_671 @[el2_ifu_aln_ctl.scala 330:19] node _T_672 = bits(f0pc, 9, 2) @[el2_lib.scala 179:12] node _T_673 = bits(f0pc, 17, 10) @[el2_lib.scala 179:46] node _T_674 = xor(_T_672, _T_673) @[el2_lib.scala 179:42] @@ -2805,158 +2805,158 @@ circuit el2_ifu_aln_ctl : _T_688[2] <= _T_687 @[el2_lib.scala 172:24] node _T_689 = xor(_T_688[0], _T_688[1]) @[el2_lib.scala 172:111] node secondbrtag_hash = xor(_T_689, _T_688[2]) @[el2_lib.scala 172:111] - node _T_690 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 341:42] - node _T_691 = and(first2B, _T_690) @[el2_ifu_aln_ctl.scala 341:30] - node _T_692 = bits(alignbrend, 1, 1) @[el2_ifu_aln_ctl.scala 341:70] - node _T_693 = and(first4B, _T_692) @[el2_ifu_aln_ctl.scala 341:58] - node _T_694 = or(_T_691, _T_693) @[el2_ifu_aln_ctl.scala 341:47] - node _T_695 = bits(alignval, 1, 1) @[el2_ifu_aln_ctl.scala 341:96] - node _T_696 = and(first4B, _T_695) @[el2_ifu_aln_ctl.scala 341:86] - node _T_697 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 341:112] - node _T_698 = and(_T_696, _T_697) @[el2_ifu_aln_ctl.scala 341:100] - node _T_699 = or(_T_694, _T_698) @[el2_ifu_aln_ctl.scala 341:75] - io.i0_brp.valid <= _T_699 @[el2_ifu_aln_ctl.scala 341:19] - node _T_700 = bits(alignret, 0, 0) @[el2_ifu_aln_ctl.scala 343:39] - node _T_701 = and(first2B, _T_700) @[el2_ifu_aln_ctl.scala 343:29] - node _T_702 = bits(alignret, 1, 1) @[el2_ifu_aln_ctl.scala 343:65] - node _T_703 = and(first4B, _T_702) @[el2_ifu_aln_ctl.scala 343:55] - node _T_704 = or(_T_701, _T_703) @[el2_ifu_aln_ctl.scala 343:44] - io.i0_brp.ret <= _T_704 @[el2_ifu_aln_ctl.scala 343:17] - node _T_705 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 345:45] - node _T_706 = or(first2B, _T_705) @[el2_ifu_aln_ctl.scala 345:33] - node _T_707 = bits(_T_706, 0, 0) @[el2_ifu_aln_ctl.scala 345:50] - node _T_708 = bits(alignway, 0, 0) @[el2_ifu_aln_ctl.scala 345:66] - node _T_709 = bits(alignway, 1, 1) @[el2_ifu_aln_ctl.scala 345:80] - node _T_710 = mux(_T_707, _T_708, _T_709) @[el2_ifu_aln_ctl.scala 345:23] - io.i0_brp.way <= _T_710 @[el2_ifu_aln_ctl.scala 345:17] - node _T_711 = bits(alignhist1, 0, 0) @[el2_ifu_aln_ctl.scala 346:46] - node _T_712 = and(first2B, _T_711) @[el2_ifu_aln_ctl.scala 346:34] - node _T_713 = bits(alignhist1, 1, 1) @[el2_ifu_aln_ctl.scala 346:74] - node _T_714 = and(first4B, _T_713) @[el2_ifu_aln_ctl.scala 346:62] - node _T_715 = or(_T_712, _T_714) @[el2_ifu_aln_ctl.scala 346:51] - node _T_716 = bits(alignhist0, 0, 0) @[el2_ifu_aln_ctl.scala 347:26] - node _T_717 = and(first2B, _T_716) @[el2_ifu_aln_ctl.scala 347:14] - node _T_718 = bits(alignhist0, 1, 1) @[el2_ifu_aln_ctl.scala 347:54] - node _T_719 = and(first4B, _T_718) @[el2_ifu_aln_ctl.scala 347:42] - node _T_720 = or(_T_717, _T_719) @[el2_ifu_aln_ctl.scala 347:31] + node _T_690 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 340:42] + node _T_691 = and(first2B, _T_690) @[el2_ifu_aln_ctl.scala 340:30] + node _T_692 = bits(alignbrend, 1, 1) @[el2_ifu_aln_ctl.scala 340:70] + node _T_693 = and(first4B, _T_692) @[el2_ifu_aln_ctl.scala 340:58] + node _T_694 = or(_T_691, _T_693) @[el2_ifu_aln_ctl.scala 340:47] + node _T_695 = bits(alignval, 1, 1) @[el2_ifu_aln_ctl.scala 340:96] + node _T_696 = and(first4B, _T_695) @[el2_ifu_aln_ctl.scala 340:86] + node _T_697 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 340:112] + node _T_698 = and(_T_696, _T_697) @[el2_ifu_aln_ctl.scala 340:100] + node _T_699 = or(_T_694, _T_698) @[el2_ifu_aln_ctl.scala 340:75] + io.i0_brp.valid <= _T_699 @[el2_ifu_aln_ctl.scala 340:19] + node _T_700 = bits(alignret, 0, 0) @[el2_ifu_aln_ctl.scala 342:39] + node _T_701 = and(first2B, _T_700) @[el2_ifu_aln_ctl.scala 342:29] + node _T_702 = bits(alignret, 1, 1) @[el2_ifu_aln_ctl.scala 342:65] + node _T_703 = and(first4B, _T_702) @[el2_ifu_aln_ctl.scala 342:55] + node _T_704 = or(_T_701, _T_703) @[el2_ifu_aln_ctl.scala 342:44] + io.i0_brp.ret <= _T_704 @[el2_ifu_aln_ctl.scala 342:17] + node _T_705 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 344:45] + node _T_706 = or(first2B, _T_705) @[el2_ifu_aln_ctl.scala 344:33] + node _T_707 = bits(_T_706, 0, 0) @[el2_ifu_aln_ctl.scala 344:50] + node _T_708 = bits(alignway, 0, 0) @[el2_ifu_aln_ctl.scala 344:66] + node _T_709 = bits(alignway, 1, 1) @[el2_ifu_aln_ctl.scala 344:80] + node _T_710 = mux(_T_707, _T_708, _T_709) @[el2_ifu_aln_ctl.scala 344:23] + io.i0_brp.way <= _T_710 @[el2_ifu_aln_ctl.scala 344:17] + node _T_711 = bits(alignhist1, 0, 0) @[el2_ifu_aln_ctl.scala 345:46] + node _T_712 = and(first2B, _T_711) @[el2_ifu_aln_ctl.scala 345:34] + node _T_713 = bits(alignhist1, 1, 1) @[el2_ifu_aln_ctl.scala 345:74] + node _T_714 = and(first4B, _T_713) @[el2_ifu_aln_ctl.scala 345:62] + node _T_715 = or(_T_712, _T_714) @[el2_ifu_aln_ctl.scala 345:51] + node _T_716 = bits(alignhist0, 0, 0) @[el2_ifu_aln_ctl.scala 346:26] + node _T_717 = and(first2B, _T_716) @[el2_ifu_aln_ctl.scala 346:14] + node _T_718 = bits(alignhist0, 1, 1) @[el2_ifu_aln_ctl.scala 346:54] + node _T_719 = and(first4B, _T_718) @[el2_ifu_aln_ctl.scala 346:42] + node _T_720 = or(_T_717, _T_719) @[el2_ifu_aln_ctl.scala 346:31] node _T_721 = cat(_T_715, _T_720) @[Cat.scala 29:58] - io.i0_brp.hist <= _T_721 @[el2_ifu_aln_ctl.scala 346:18] - node _T_722 = and(first4B, alignfromf1) @[el2_ifu_aln_ctl.scala 349:37] - node _T_723 = bits(_T_722, 0, 0) @[el2_ifu_aln_ctl.scala 349:52] - node _T_724 = mux(_T_723, f1poffset, f0poffset) @[el2_ifu_aln_ctl.scala 349:27] - io.i0_brp.toffset <= _T_724 @[el2_ifu_aln_ctl.scala 349:21] - node _T_725 = and(first4B, alignfromf1) @[el2_ifu_aln_ctl.scala 351:35] - node _T_726 = bits(_T_725, 0, 0) @[el2_ifu_aln_ctl.scala 351:50] - node _T_727 = mux(_T_726, f1prett, f0prett) @[el2_ifu_aln_ctl.scala 351:25] - io.i0_brp.prett <= _T_727 @[el2_ifu_aln_ctl.scala 351:19] - node _T_728 = bits(alignval, 1, 1) @[el2_ifu_aln_ctl.scala 353:51] - node _T_729 = and(first4B, _T_728) @[el2_ifu_aln_ctl.scala 353:41] - node _T_730 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 353:67] - node _T_731 = and(_T_729, _T_730) @[el2_ifu_aln_ctl.scala 353:55] - io.i0_brp.br_start_error <= _T_731 @[el2_ifu_aln_ctl.scala 353:29] - node _T_732 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 355:57] - node _T_733 = or(first2B, _T_732) @[el2_ifu_aln_ctl.scala 355:45] - node _T_734 = bits(_T_733, 0, 0) @[el2_ifu_aln_ctl.scala 355:62] - node _T_735 = bits(f0pc, 1, 1) @[el2_ifu_aln_ctl.scala 355:77] - node _T_736 = bits(secondpc, 1, 1) @[el2_ifu_aln_ctl.scala 355:90] - node _T_737 = mux(_T_734, _T_735, _T_736) @[el2_ifu_aln_ctl.scala 355:35] - io.i0_brp.bank <= _T_737 @[el2_ifu_aln_ctl.scala 355:29] - node _T_738 = bits(alignpc4, 0, 0) @[el2_ifu_aln_ctl.scala 357:39] - node _T_739 = and(first2B, _T_738) @[el2_ifu_aln_ctl.scala 357:29] - node _T_740 = bits(alignpc4, 1, 1) @[el2_ifu_aln_ctl.scala 357:65] - node _T_741 = and(first4B, _T_740) @[el2_ifu_aln_ctl.scala 357:55] - node i0_brp_pc4 = or(_T_739, _T_741) @[el2_ifu_aln_ctl.scala 357:44] - node _T_742 = and(io.i0_brp.valid, i0_brp_pc4) @[el2_ifu_aln_ctl.scala 359:42] - node _T_743 = and(_T_742, first2B) @[el2_ifu_aln_ctl.scala 359:56] - node _T_744 = not(i0_brp_pc4) @[el2_ifu_aln_ctl.scala 359:89] - node _T_745 = and(io.i0_brp.valid, _T_744) @[el2_ifu_aln_ctl.scala 359:87] - node _T_746 = and(_T_745, first4B) @[el2_ifu_aln_ctl.scala 359:101] - node _T_747 = or(_T_743, _T_746) @[el2_ifu_aln_ctl.scala 359:68] - io.i0_brp.br_error <= _T_747 @[el2_ifu_aln_ctl.scala 359:22] - node _T_748 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 362:50] - node _T_749 = or(first2B, _T_748) @[el2_ifu_aln_ctl.scala 362:38] - node _T_750 = bits(_T_749, 0, 0) @[el2_ifu_aln_ctl.scala 362:55] - node _T_751 = mux(_T_750, firstpc_hash, secondpc_hash) @[el2_ifu_aln_ctl.scala 362:28] - io.ifu_i0_bp_index <= _T_751 @[el2_ifu_aln_ctl.scala 362:22] - node _T_752 = and(first4B, alignfromf1) @[el2_ifu_aln_ctl.scala 364:37] - node _T_753 = bits(_T_752, 0, 0) @[el2_ifu_aln_ctl.scala 364:52] - node _T_754 = mux(_T_753, f1fghr, f0fghr) @[el2_ifu_aln_ctl.scala 364:27] - io.ifu_i0_bp_fghr <= _T_754 @[el2_ifu_aln_ctl.scala 364:21] - node _T_755 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 366:49] - node _T_756 = or(first2B, _T_755) @[el2_ifu_aln_ctl.scala 366:37] - node _T_757 = bits(_T_756, 0, 0) @[el2_ifu_aln_ctl.scala 366:54] - node _T_758 = mux(_T_757, firstbrtag_hash, secondbrtag_hash) @[el2_ifu_aln_ctl.scala 366:27] - io.ifu_i0_bp_btag <= _T_758 @[el2_ifu_aln_ctl.scala 366:21] - node _T_759 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 368:44] + io.i0_brp.hist <= _T_721 @[el2_ifu_aln_ctl.scala 345:18] + node _T_722 = and(first4B, alignfromf1) @[el2_ifu_aln_ctl.scala 348:37] + node _T_723 = bits(_T_722, 0, 0) @[el2_ifu_aln_ctl.scala 348:52] + node _T_724 = mux(_T_723, f1poffset, f0poffset) @[el2_ifu_aln_ctl.scala 348:27] + io.i0_brp.toffset <= _T_724 @[el2_ifu_aln_ctl.scala 348:21] + node _T_725 = and(first4B, alignfromf1) @[el2_ifu_aln_ctl.scala 350:35] + node _T_726 = bits(_T_725, 0, 0) @[el2_ifu_aln_ctl.scala 350:50] + node _T_727 = mux(_T_726, f1prett, f0prett) @[el2_ifu_aln_ctl.scala 350:25] + io.i0_brp.prett <= _T_727 @[el2_ifu_aln_ctl.scala 350:19] + node _T_728 = bits(alignval, 1, 1) @[el2_ifu_aln_ctl.scala 352:51] + node _T_729 = and(first4B, _T_728) @[el2_ifu_aln_ctl.scala 352:41] + node _T_730 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 352:67] + node _T_731 = and(_T_729, _T_730) @[el2_ifu_aln_ctl.scala 352:55] + io.i0_brp.br_start_error <= _T_731 @[el2_ifu_aln_ctl.scala 352:29] + node _T_732 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 354:57] + node _T_733 = or(first2B, _T_732) @[el2_ifu_aln_ctl.scala 354:45] + node _T_734 = bits(_T_733, 0, 0) @[el2_ifu_aln_ctl.scala 354:62] + node _T_735 = bits(f0pc, 1, 1) @[el2_ifu_aln_ctl.scala 354:77] + node _T_736 = bits(secondpc, 1, 1) @[el2_ifu_aln_ctl.scala 354:90] + node _T_737 = mux(_T_734, _T_735, _T_736) @[el2_ifu_aln_ctl.scala 354:35] + io.i0_brp.bank <= _T_737 @[el2_ifu_aln_ctl.scala 354:29] + node _T_738 = bits(alignpc4, 0, 0) @[el2_ifu_aln_ctl.scala 356:39] + node _T_739 = and(first2B, _T_738) @[el2_ifu_aln_ctl.scala 356:29] + node _T_740 = bits(alignpc4, 1, 1) @[el2_ifu_aln_ctl.scala 356:65] + node _T_741 = and(first4B, _T_740) @[el2_ifu_aln_ctl.scala 356:55] + node i0_brp_pc4 = or(_T_739, _T_741) @[el2_ifu_aln_ctl.scala 356:44] + node _T_742 = and(io.i0_brp.valid, i0_brp_pc4) @[el2_ifu_aln_ctl.scala 358:42] + node _T_743 = and(_T_742, first2B) @[el2_ifu_aln_ctl.scala 358:56] + node _T_744 = not(i0_brp_pc4) @[el2_ifu_aln_ctl.scala 358:89] + node _T_745 = and(io.i0_brp.valid, _T_744) @[el2_ifu_aln_ctl.scala 358:87] + node _T_746 = and(_T_745, first4B) @[el2_ifu_aln_ctl.scala 358:101] + node _T_747 = or(_T_743, _T_746) @[el2_ifu_aln_ctl.scala 358:68] + io.i0_brp.br_error <= _T_747 @[el2_ifu_aln_ctl.scala 358:22] + node _T_748 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 361:50] + node _T_749 = or(first2B, _T_748) @[el2_ifu_aln_ctl.scala 361:38] + node _T_750 = bits(_T_749, 0, 0) @[el2_ifu_aln_ctl.scala 361:55] + node _T_751 = mux(_T_750, firstpc_hash, secondpc_hash) @[el2_ifu_aln_ctl.scala 361:28] + io.ifu_i0_bp_index <= _T_751 @[el2_ifu_aln_ctl.scala 361:22] + node _T_752 = and(first4B, alignfromf1) @[el2_ifu_aln_ctl.scala 363:37] + node _T_753 = bits(_T_752, 0, 0) @[el2_ifu_aln_ctl.scala 363:52] + node _T_754 = mux(_T_753, f1fghr, f0fghr) @[el2_ifu_aln_ctl.scala 363:27] + io.ifu_i0_bp_fghr <= _T_754 @[el2_ifu_aln_ctl.scala 363:21] + node _T_755 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 365:49] + node _T_756 = or(first2B, _T_755) @[el2_ifu_aln_ctl.scala 365:37] + node _T_757 = bits(_T_756, 0, 0) @[el2_ifu_aln_ctl.scala 365:54] + node _T_758 = mux(_T_757, firstbrtag_hash, secondbrtag_hash) @[el2_ifu_aln_ctl.scala 365:27] + io.ifu_i0_bp_btag <= _T_758 @[el2_ifu_aln_ctl.scala 365:21] + node _T_759 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 367:44] reg _T_760 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_759 : @[Reg.scala 28:19] _T_760 <= brdata_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - brdata2 <= _T_760 @[el2_ifu_aln_ctl.scala 368:11] - node _T_761 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 369:44] + brdata2 <= _T_760 @[el2_ifu_aln_ctl.scala 367:11] + node _T_761 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 368:44] reg _T_762 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_761 : @[Reg.scala 28:19] _T_762 <= brdata_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - brdata1 <= _T_762 @[el2_ifu_aln_ctl.scala 369:11] - node _T_763 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 370:44] + brdata1 <= _T_762 @[el2_ifu_aln_ctl.scala 368:11] + node _T_763 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 369:44] reg _T_764 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_763 : @[Reg.scala 28:19] _T_764 <= brdata_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - brdata0 <= _T_764 @[el2_ifu_aln_ctl.scala 370:11] - node _T_765 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 372:45] + brdata0 <= _T_764 @[el2_ifu_aln_ctl.scala 369:11] + node _T_765 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 371:45] reg _T_766 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_765 : @[Reg.scala 28:19] _T_766 <= misc_data_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - misc2 <= _T_766 @[el2_ifu_aln_ctl.scala 372:9] - node _T_767 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 373:45] + misc2 <= _T_766 @[el2_ifu_aln_ctl.scala 371:9] + node _T_767 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 372:45] reg _T_768 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_767 : @[Reg.scala 28:19] _T_768 <= misc_data_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - misc1 <= _T_768 @[el2_ifu_aln_ctl.scala 373:9] - node _T_769 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 374:45] + misc1 <= _T_768 @[el2_ifu_aln_ctl.scala 372:9] + node _T_769 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 373:45] reg _T_770 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_769 : @[Reg.scala 28:19] _T_770 <= misc_data_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - misc0 <= _T_770 @[el2_ifu_aln_ctl.scala 374:9] - node _T_771 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 376:49] + misc0 <= _T_770 @[el2_ifu_aln_ctl.scala 373:9] + node _T_771 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 375:49] reg _T_772 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_771 : @[Reg.scala 28:19] _T_772 <= io.ifu_fetch_data_f @[Reg.scala 28:23] skip @[Reg.scala 28:19] - q2 <= _T_772 @[el2_ifu_aln_ctl.scala 376:6] - node _T_773 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 377:49] + q2 <= _T_772 @[el2_ifu_aln_ctl.scala 375:6] + node _T_773 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 376:49] reg _T_774 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_773 : @[Reg.scala 28:19] _T_774 <= io.ifu_fetch_data_f @[Reg.scala 28:23] skip @[Reg.scala 28:19] - q1 <= _T_774 @[el2_ifu_aln_ctl.scala 377:6] - node _T_775 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 378:49] + q1 <= _T_774 @[el2_ifu_aln_ctl.scala 376:6] + node _T_775 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 377:49] reg _T_776 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_775 : @[Reg.scala 28:19] _T_776 <= io.ifu_fetch_data_f @[Reg.scala 28:23] skip @[Reg.scala 28:19] - q0 <= _T_776 @[el2_ifu_aln_ctl.scala 378:6] - node _T_777 = bits(f2_wr_en, 0, 0) @[el2_ifu_aln_ctl.scala 380:52] + q0 <= _T_776 @[el2_ifu_aln_ctl.scala 377:6] + node _T_777 = bits(f2_wr_en, 0, 0) @[el2_ifu_aln_ctl.scala 379:52] reg _T_778 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_777 : @[Reg.scala 28:19] _T_778 <= io.ifu_fetch_pc @[Reg.scala 28:23] skip @[Reg.scala 28:19] - f2pc <= _T_778 @[el2_ifu_aln_ctl.scala 380:8] - node _T_779 = bits(f1_shift_wr_en, 0, 0) @[el2_ifu_aln_ctl.scala 381:50] + f2pc <= _T_778 @[el2_ifu_aln_ctl.scala 379:8] + node _T_779 = bits(f1_shift_wr_en, 0, 0) @[el2_ifu_aln_ctl.scala 380:50] reg _T_780 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_779 : @[Reg.scala 28:19] _T_780 <= f1pc_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - f2pc <= _T_780 @[el2_ifu_aln_ctl.scala 381:8] - node _T_781 = bits(f0_shift_wr_en, 0, 0) @[el2_ifu_aln_ctl.scala 382:50] + f2pc <= _T_780 @[el2_ifu_aln_ctl.scala 380:8] + node _T_781 = bits(f0_shift_wr_en, 0, 0) @[el2_ifu_aln_ctl.scala 381:50] reg _T_782 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_781 : @[Reg.scala 28:19] _T_782 <= f0pc_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - f2pc <= _T_782 @[el2_ifu_aln_ctl.scala 382:8] + f2pc <= _T_782 @[el2_ifu_aln_ctl.scala 381:8] diff --git a/el2_ifu_aln_ctl.v b/el2_ifu_aln_ctl.v index c1e438a1..d3b942a3 100644 --- a/el2_ifu_aln_ctl.v +++ b/el2_ifu_aln_ctl.v @@ -511,7 +511,6 @@ module el2_ifu_aln_ctl( input clock, input reset, input io_scan_mode, - input io_free_clk, input io_active_clk, input io_ifu_async_error_start, input io_iccm_rd_ecc_double_err, @@ -576,30 +575,30 @@ module el2_ifu_aln_ctl( reg [31:0] _RAND_16; reg [31:0] _RAND_17; `endif // RANDOMIZE_REG_INIT - wire [15:0] decompressed_io_din; // @[el2_ifu_aln_ctl.scala 100:28] - wire [31:0] decompressed_io_dout; // @[el2_ifu_aln_ctl.scala 100:28] - reg error_stall; // @[el2_ifu_aln_ctl.scala 90:54] - reg [1:0] f0val; // @[el2_ifu_aln_ctl.scala 91:48] - wire _T = error_stall | io_ifu_async_error_start; // @[el2_ifu_aln_ctl.scala 92:34] - wire _T_1 = ~io_exu_flush_final; // @[el2_ifu_aln_ctl.scala 92:64] - wire error_stall_in = _T & _T_1; // @[el2_ifu_aln_ctl.scala 92:62] - wire _T_3 = ~error_stall; // @[el2_ifu_aln_ctl.scala 94:39] - wire i0_shift = io_dec_i0_decode_d & _T_3; // @[el2_ifu_aln_ctl.scala 94:37] - wire _T_7 = ~f0val[1]; // @[el2_ifu_aln_ctl.scala 98:58] - wire _T_9 = _T_7 & f0val[0]; // @[el2_ifu_aln_ctl.scala 98:68] - reg [1:0] rdptr; // @[el2_ifu_aln_ctl.scala 125:48] - wire _T_252 = rdptr == 2'h0; // @[el2_ifu_aln_ctl.scala 179:32] - reg q1off; // @[el2_ifu_aln_ctl.scala 132:48] + wire [15:0] decompressed_io_din; // @[el2_ifu_aln_ctl.scala 99:28] + wire [31:0] decompressed_io_dout; // @[el2_ifu_aln_ctl.scala 99:28] + reg error_stall; // @[el2_ifu_aln_ctl.scala 89:54] + reg [1:0] f0val; // @[el2_ifu_aln_ctl.scala 90:48] + wire _T = error_stall | io_ifu_async_error_start; // @[el2_ifu_aln_ctl.scala 91:34] + wire _T_1 = ~io_exu_flush_final; // @[el2_ifu_aln_ctl.scala 91:64] + wire error_stall_in = _T & _T_1; // @[el2_ifu_aln_ctl.scala 91:62] + wire _T_3 = ~error_stall; // @[el2_ifu_aln_ctl.scala 93:39] + wire i0_shift = io_dec_i0_decode_d & _T_3; // @[el2_ifu_aln_ctl.scala 93:37] + wire _T_7 = ~f0val[1]; // @[el2_ifu_aln_ctl.scala 97:58] + wire _T_9 = _T_7 & f0val[0]; // @[el2_ifu_aln_ctl.scala 97:68] + reg [1:0] rdptr; // @[el2_ifu_aln_ctl.scala 124:48] + wire _T_252 = rdptr == 2'h0; // @[el2_ifu_aln_ctl.scala 178:32] + reg q1off; // @[el2_ifu_aln_ctl.scala 131:48] wire _T_255 = _T_252 & q1off; // @[Mux.scala 27:72] - wire _T_253 = rdptr == 2'h1; // @[el2_ifu_aln_ctl.scala 179:57] - reg q2off; // @[el2_ifu_aln_ctl.scala 131:48] + wire _T_253 = rdptr == 2'h1; // @[el2_ifu_aln_ctl.scala 178:57] + reg q2off; // @[el2_ifu_aln_ctl.scala 130:48] wire _T_256 = _T_253 & q2off; // @[Mux.scala 27:72] wire _T_258 = _T_255 | _T_256; // @[Mux.scala 27:72] - wire _T_254 = rdptr == 2'h2; // @[el2_ifu_aln_ctl.scala 179:83] - reg q0off; // @[el2_ifu_aln_ctl.scala 133:48] + wire _T_254 = rdptr == 2'h2; // @[el2_ifu_aln_ctl.scala 178:83] + reg q0off; // @[el2_ifu_aln_ctl.scala 132:48] wire _T_257 = _T_254 & q0off; // @[Mux.scala 27:72] wire q1ptr = _T_258 | _T_257; // @[Mux.scala 27:72] - wire _T_261 = ~q1ptr; // @[el2_ifu_aln_ctl.scala 183:26] + wire _T_261 = ~q1ptr; // @[el2_ifu_aln_ctl.scala 182:26] wire [1:0] q1sel = {q1ptr,_T_261}; // @[Cat.scala 29:58] wire [2:0] qren = {_T_254,_T_253,_T_252}; // @[Cat.scala 29:58] reg [31:0] q1; // @[Reg.scala 27:20] @@ -613,7 +612,7 @@ module el2_ifu_aln_ctl( wire [63:0] _T_327 = {q0,q2}; // @[Cat.scala 29:58] wire [63:0] _T_330 = qren[2] ? _T_327 : 64'h0; // @[Mux.scala 27:72] wire [63:0] qeff = _T_331 | _T_330; // @[Mux.scala 27:72] - wire [31:0] q1eff = qeff[63:32]; // @[el2_ifu_aln_ctl.scala 226:29] + wire [31:0] q1eff = qeff[63:32]; // @[el2_ifu_aln_ctl.scala 225:29] wire [15:0] _T_527 = q1sel[0] ? q1eff[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_528 = q1sel[1] ? q1eff[31:16] : 16'h0; // @[Mux.scala 27:72] wire [15:0] q1final = _T_527 | _T_528; // @[Mux.scala 27:72] @@ -622,111 +621,111 @@ module el2_ifu_aln_ctl( wire _T_250 = _T_247 | _T_248; // @[Mux.scala 27:72] wire _T_249 = _T_254 & q2off; // @[Mux.scala 27:72] wire q0ptr = _T_250 | _T_249; // @[Mux.scala 27:72] - wire _T_260 = ~q0ptr; // @[el2_ifu_aln_ctl.scala 181:26] + wire _T_260 = ~q0ptr; // @[el2_ifu_aln_ctl.scala 180:26] wire [1:0] q0sel = {q0ptr,_T_260}; // @[Cat.scala 29:58] - wire [31:0] q0eff = qeff[31:0]; // @[el2_ifu_aln_ctl.scala 226:42] + wire [31:0] q0eff = qeff[31:0]; // @[el2_ifu_aln_ctl.scala 225:42] wire [31:0] _T_517 = q0sel[0] ? q0eff : 32'h0; // @[Mux.scala 27:72] wire [15:0] _T_518 = q0sel[1] ? q0eff[31:16] : 16'h0; // @[Mux.scala 27:72] wire [31:0] _GEN_12 = {{16'd0}, _T_518}; // @[Mux.scala 27:72] wire [31:0] _T_519 = _T_517 | _GEN_12; // @[Mux.scala 27:72] - wire [15:0] q0final = _T_519[15:0]; // @[el2_ifu_aln_ctl.scala 295:11] + wire [15:0] q0final = _T_519[15:0]; // @[el2_ifu_aln_ctl.scala 294:11] wire [31:0] _T_11 = {q1final,q0final}; // @[Cat.scala 29:58] wire [15:0] _T_12 = f0val[0] ? q0final : 16'h0; // @[Mux.scala 27:72] wire [31:0] _T_13 = _T_9 ? _T_11 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _GEN_13 = {{16'd0}, _T_12}; // @[Mux.scala 27:72] wire [31:0] aligndata = _GEN_13 | _T_13; // @[Mux.scala 27:72] reg [54:0] _T_768; // @[Reg.scala 27:20] - wire [53:0] misc1 = _T_768[53:0]; // @[el2_ifu_aln_ctl.scala 373:9] + wire [53:0] misc1 = _T_768[53:0]; // @[el2_ifu_aln_ctl.scala 372:9] reg [54:0] _T_770; // @[Reg.scala 27:20] - wire [53:0] misc0 = _T_770[53:0]; // @[el2_ifu_aln_ctl.scala 374:9] + wire [53:0] misc0 = _T_770[53:0]; // @[el2_ifu_aln_ctl.scala 373:9] wire [107:0] _T_269 = {misc1,misc0}; // @[Cat.scala 29:58] wire [107:0] _T_276 = qren[0] ? _T_269 : 108'h0; // @[Mux.scala 27:72] reg [54:0] _T_766; // @[Reg.scala 27:20] - wire [53:0] misc2 = _T_766[53:0]; // @[el2_ifu_aln_ctl.scala 372:9] + wire [53:0] misc2 = _T_766[53:0]; // @[el2_ifu_aln_ctl.scala 371:9] wire [107:0] _T_272 = {misc2,misc1}; // @[Cat.scala 29:58] wire [107:0] _T_277 = qren[1] ? _T_272 : 108'h0; // @[Mux.scala 27:72] wire [107:0] _T_279 = _T_276 | _T_277; // @[Mux.scala 27:72] wire [107:0] _T_275 = {misc0,misc2}; // @[Cat.scala 29:58] wire [107:0] _T_278 = qren[2] ? _T_275 : 108'h0; // @[Mux.scala 27:72] wire [107:0] misceff = _T_279 | _T_278; // @[Mux.scala 27:72] - wire [52:0] misc1eff = misceff[107:55]; // @[el2_ifu_aln_ctl.scala 192:25] - wire f1icaf = misc1eff[51]; // @[el2_ifu_aln_ctl.scala 196:21] - wire [54:0] misc0eff = misceff[54:0]; // @[el2_ifu_aln_ctl.scala 193:25] - wire f0icaf = misc0eff[53]; // @[el2_ifu_aln_ctl.scala 203:21] + wire [52:0] misc1eff = misceff[107:55]; // @[el2_ifu_aln_ctl.scala 191:25] + wire f1icaf = misc1eff[51]; // @[el2_ifu_aln_ctl.scala 195:21] + wire [54:0] misc0eff = misceff[54:0]; // @[el2_ifu_aln_ctl.scala 192:25] + wire f0icaf = misc0eff[53]; // @[el2_ifu_aln_ctl.scala 202:21] wire [1:0] _T_23 = {f1icaf,f0icaf}; // @[Cat.scala 29:58] wire _T_24 = f0val[1] & f0icaf; // @[Mux.scala 27:72] wire [1:0] _T_25 = _T_9 ? _T_23 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _GEN_14 = {{1'd0}, _T_24}; // @[Mux.scala 27:72] wire [1:0] alignicaf = _GEN_14 | _T_25; // @[Mux.scala 27:72] wire [1:0] _T_539 = f0val[1] ? 2'h3 : 2'h0; // @[Mux.scala 27:72] - reg [1:0] f1val; // @[el2_ifu_aln_ctl.scala 128:48] + reg [1:0] f1val; // @[el2_ifu_aln_ctl.scala 127:48] wire [1:0] _T_538 = {f1val[0],1'h1}; // @[Cat.scala 29:58] wire [1:0] _T_540 = _T_9 ? _T_538 : 2'h0; // @[Mux.scala 27:72] wire [1:0] alignval = _T_539 | _T_540; // @[Mux.scala 27:72] wire f0_shift_2B = i0_shift & f0val[0]; // @[Mux.scala 27:72] - reg [1:0] wrptr; // @[el2_ifu_aln_ctl.scala 124:48] - reg [1:0] f2val; // @[el2_ifu_aln_ctl.scala 127:48] - wire _T_58 = ~f1val[0]; // @[el2_ifu_aln_ctl.scala 135:42] - wire f2_valid = f2val[0]; // @[el2_ifu_aln_ctl.scala 247:20] - wire _T_60 = ~f2_valid; // @[el2_ifu_aln_ctl.scala 135:55] - wire ifvalid = io_ifu_fetch_val[0]; // @[el2_ifu_aln_ctl.scala 257:30] - wire _T_65 = _T_58 & f2_valid; // @[el2_ifu_aln_ctl.scala 136:53] - wire _T_66 = _T_65 & ifvalid; // @[el2_ifu_aln_ctl.scala 136:65] - wire _T_70 = f1val[0] & _T_60; // @[el2_ifu_aln_ctl.scala 137:53] - wire _T_71 = _T_70 & ifvalid; // @[el2_ifu_aln_ctl.scala 137:65] - wire fetch_to_f1 = _T_66 | _T_71; // @[el2_ifu_aln_ctl.scala 136:77] - wire _T_80 = f1val[0] & f2_valid; // @[el2_ifu_aln_ctl.scala 140:53] - wire f2_wr_en = _T_80 & ifvalid; // @[el2_ifu_aln_ctl.scala 140:65] - wire _T_94 = wrptr == 2'h2; // @[el2_ifu_aln_ctl.scala 148:24] - wire _T_95 = _T_94 & ifvalid; // @[el2_ifu_aln_ctl.scala 148:32] - wire _T_96 = wrptr == 2'h1; // @[el2_ifu_aln_ctl.scala 148:49] - wire _T_97 = _T_96 & ifvalid; // @[el2_ifu_aln_ctl.scala 148:57] - wire _T_98 = wrptr == 2'h0; // @[el2_ifu_aln_ctl.scala 148:74] - wire _T_99 = _T_98 & ifvalid; // @[el2_ifu_aln_ctl.scala 148:82] + reg [1:0] wrptr; // @[el2_ifu_aln_ctl.scala 123:48] + reg [1:0] f2val; // @[el2_ifu_aln_ctl.scala 126:48] + wire _T_58 = ~f1val[0]; // @[el2_ifu_aln_ctl.scala 134:42] + wire f2_valid = f2val[0]; // @[el2_ifu_aln_ctl.scala 246:20] + wire _T_60 = ~f2_valid; // @[el2_ifu_aln_ctl.scala 134:55] + wire ifvalid = io_ifu_fetch_val[0]; // @[el2_ifu_aln_ctl.scala 256:30] + wire _T_65 = _T_58 & f2_valid; // @[el2_ifu_aln_ctl.scala 135:53] + wire _T_66 = _T_65 & ifvalid; // @[el2_ifu_aln_ctl.scala 135:65] + wire _T_70 = f1val[0] & _T_60; // @[el2_ifu_aln_ctl.scala 136:53] + wire _T_71 = _T_70 & ifvalid; // @[el2_ifu_aln_ctl.scala 136:65] + wire fetch_to_f1 = _T_66 | _T_71; // @[el2_ifu_aln_ctl.scala 135:77] + wire _T_80 = f1val[0] & f2_valid; // @[el2_ifu_aln_ctl.scala 139:53] + wire f2_wr_en = _T_80 & ifvalid; // @[el2_ifu_aln_ctl.scala 139:65] + wire _T_94 = wrptr == 2'h2; // @[el2_ifu_aln_ctl.scala 147:24] + wire _T_95 = _T_94 & ifvalid; // @[el2_ifu_aln_ctl.scala 147:32] + wire _T_96 = wrptr == 2'h1; // @[el2_ifu_aln_ctl.scala 147:49] + wire _T_97 = _T_96 & ifvalid; // @[el2_ifu_aln_ctl.scala 147:57] + wire _T_98 = wrptr == 2'h0; // @[el2_ifu_aln_ctl.scala 147:74] + wire _T_99 = _T_98 & ifvalid; // @[el2_ifu_aln_ctl.scala 147:82] wire [2:0] qwen = {_T_95,_T_97,_T_99}; // @[Cat.scala 29:58] - wire _T_153 = qwen[0] & _T_1; // @[el2_ifu_aln_ctl.scala 158:34] - wire _T_157 = qwen[1] & _T_1; // @[el2_ifu_aln_ctl.scala 159:34] - wire _T_163 = ~ifvalid; // @[el2_ifu_aln_ctl.scala 161:26] - wire _T_165 = _T_163 & _T_1; // @[el2_ifu_aln_ctl.scala 161:35] + wire _T_153 = qwen[0] & _T_1; // @[el2_ifu_aln_ctl.scala 157:34] + wire _T_157 = qwen[1] & _T_1; // @[el2_ifu_aln_ctl.scala 158:34] + wire _T_163 = ~ifvalid; // @[el2_ifu_aln_ctl.scala 160:26] + wire _T_165 = _T_163 & _T_1; // @[el2_ifu_aln_ctl.scala 160:35] wire [1:0] _T_168 = _T_157 ? 2'h2 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_170 = _T_165 ? wrptr : 2'h0; // @[Mux.scala 27:72] wire [1:0] _GEN_17 = {{1'd0}, _T_153}; // @[Mux.scala 27:72] wire [1:0] _T_171 = _GEN_17 | _T_168; // @[Mux.scala 27:72] wire [1:0] wrptr_in = _T_171 | _T_170; // @[Mux.scala 27:72] - wire _T_176 = ~qwen[2]; // @[el2_ifu_aln_ctl.scala 163:26] - wire _T_178 = _T_176 & _T_254; // @[el2_ifu_aln_ctl.scala 163:35] - wire _T_180 = q2off | f0_shift_2B; // @[el2_ifu_aln_ctl.scala 163:74] - wire _T_184 = _T_176 & _T_253; // @[el2_ifu_aln_ctl.scala 164:35] - wire _T_190 = _T_176 & _T_252; // @[el2_ifu_aln_ctl.scala 165:35] + wire _T_176 = ~qwen[2]; // @[el2_ifu_aln_ctl.scala 162:26] + wire _T_178 = _T_176 & _T_254; // @[el2_ifu_aln_ctl.scala 162:35] + wire _T_180 = q2off | f0_shift_2B; // @[el2_ifu_aln_ctl.scala 162:74] + wire _T_184 = _T_176 & _T_253; // @[el2_ifu_aln_ctl.scala 163:35] + wire _T_190 = _T_176 & _T_252; // @[el2_ifu_aln_ctl.scala 164:35] wire _T_192 = _T_178 & _T_180; // @[Mux.scala 27:72] wire _T_193 = _T_184 & q2off; // @[Mux.scala 27:72] wire _T_194 = _T_190 & q2off; // @[Mux.scala 27:72] wire _T_195 = _T_192 | _T_193; // @[Mux.scala 27:72] wire q2off_in = _T_195 | _T_194; // @[Mux.scala 27:72] - wire _T_199 = ~qwen[1]; // @[el2_ifu_aln_ctl.scala 167:26] - wire _T_201 = _T_199 & _T_253; // @[el2_ifu_aln_ctl.scala 167:35] - wire _T_203 = q1off | f0_shift_2B; // @[el2_ifu_aln_ctl.scala 167:74] - wire _T_207 = _T_199 & _T_252; // @[el2_ifu_aln_ctl.scala 168:35] - wire _T_213 = _T_199 & _T_254; // @[el2_ifu_aln_ctl.scala 169:35] + wire _T_199 = ~qwen[1]; // @[el2_ifu_aln_ctl.scala 166:26] + wire _T_201 = _T_199 & _T_253; // @[el2_ifu_aln_ctl.scala 166:35] + wire _T_203 = q1off | f0_shift_2B; // @[el2_ifu_aln_ctl.scala 166:74] + wire _T_207 = _T_199 & _T_252; // @[el2_ifu_aln_ctl.scala 167:35] + wire _T_213 = _T_199 & _T_254; // @[el2_ifu_aln_ctl.scala 168:35] wire _T_215 = _T_201 & _T_203; // @[Mux.scala 27:72] wire _T_216 = _T_207 & q1off; // @[Mux.scala 27:72] wire _T_217 = _T_213 & q1off; // @[Mux.scala 27:72] wire _T_218 = _T_215 | _T_216; // @[Mux.scala 27:72] wire q1off_in = _T_218 | _T_217; // @[Mux.scala 27:72] - wire _T_222 = ~qwen[0]; // @[el2_ifu_aln_ctl.scala 171:26] - wire _T_224 = _T_222 & _T_252; // @[el2_ifu_aln_ctl.scala 171:35] - wire _T_226 = q0off | f0_shift_2B; // @[el2_ifu_aln_ctl.scala 171:76] - wire _T_230 = _T_222 & _T_254; // @[el2_ifu_aln_ctl.scala 172:35] - wire _T_236 = _T_222 & _T_253; // @[el2_ifu_aln_ctl.scala 173:35] + wire _T_222 = ~qwen[0]; // @[el2_ifu_aln_ctl.scala 170:26] + wire _T_224 = _T_222 & _T_252; // @[el2_ifu_aln_ctl.scala 170:35] + wire _T_226 = q0off | f0_shift_2B; // @[el2_ifu_aln_ctl.scala 170:76] + wire _T_230 = _T_222 & _T_254; // @[el2_ifu_aln_ctl.scala 171:35] + wire _T_236 = _T_222 & _T_253; // @[el2_ifu_aln_ctl.scala 172:35] wire _T_238 = _T_224 & _T_226; // @[Mux.scala 27:72] wire _T_239 = _T_230 & q0off; // @[Mux.scala 27:72] wire _T_240 = _T_236 & q0off; // @[Mux.scala 27:72] wire _T_241 = _T_238 | _T_239; // @[Mux.scala 27:72] wire q0off_in = _T_241 | _T_240; // @[Mux.scala 27:72] wire [54:0] misc_data_in = {io_iccm_rd_ecc_double_err,io_ic_access_fault_f,io_ic_access_fault_type_f,io_ifu_bp_btb_target_f[31:1],io_ifu_bp_poffset_f,io_ifu_bp_fghr_f}; // @[Cat.scala 29:58] - wire f1dbecc = misc1eff[52]; // @[el2_ifu_aln_ctl.scala 195:25] - wire f0dbecc = misc0eff[54]; // @[el2_ifu_aln_ctl.scala 202:25] - wire [30:0] f0prett = misc0eff[50:20]; // @[el2_ifu_aln_ctl.scala 205:25] + wire f1dbecc = misc1eff[52]; // @[el2_ifu_aln_ctl.scala 194:25] + wire f0dbecc = misc0eff[54]; // @[el2_ifu_aln_ctl.scala 201:25] + wire [30:0] f0prett = misc0eff[50:20]; // @[el2_ifu_aln_ctl.scala 204:25] wire [5:0] _T_299 = {io_ifu_bp_hist1_f[0],io_ifu_bp_hist0_f[0],io_ifu_bp_pc4_f[0],io_ifu_bp_way_f[0],io_ifu_bp_valid_f[0],io_ifu_bp_ret_f[0]}; // @[Cat.scala 29:58] wire [11:0] brdata_in = {io_ifu_bp_hist1_f[1],io_ifu_bp_hist0_f[1],io_ifu_bp_pc4_f[1],io_ifu_bp_way_f[1],io_ifu_bp_valid_f[1],io_ifu_bp_ret_f[1],_T_299}; // @[Cat.scala 29:58] reg [11:0] brdata1; // @[Reg.scala 27:20] @@ -740,8 +739,8 @@ module el2_ifu_aln_ctl( wire [23:0] _T_316 = qren[2] ? _T_313 : 24'h0; // @[Mux.scala 27:72] wire [23:0] _T_317 = _T_314 | _T_315; // @[Mux.scala 27:72] wire [23:0] brdataeff = _T_317 | _T_316; // @[Mux.scala 27:72] - wire [11:0] brdata0eff = brdataeff[11:0]; // @[el2_ifu_aln_ctl.scala 217:43] - wire [11:0] brdata1eff = brdataeff[23:12]; // @[el2_ifu_aln_ctl.scala 217:61] + wire [11:0] brdata0eff = brdataeff[11:0]; // @[el2_ifu_aln_ctl.scala 216:43] + wire [11:0] brdata1eff = brdataeff[23:12]; // @[el2_ifu_aln_ctl.scala 216:61] wire [11:0] _T_338 = q0sel[0] ? brdata0eff : 12'h0; // @[Mux.scala 27:72] wire [5:0] _T_339 = q0sel[1] ? brdata0eff[11:6] : 6'h0; // @[Mux.scala 27:72] wire [11:0] _GEN_18 = {{6'd0}, _T_339}; // @[Mux.scala 27:72] @@ -762,32 +761,32 @@ module el2_ifu_aln_ctl( wire [1:0] f1pc4 = {brdata1final[9],brdata1final[3]}; // @[Cat.scala 29:58] wire [1:0] f1hist0 = {brdata1final[10],brdata1final[4]}; // @[Cat.scala 29:58] wire [1:0] f1hist1 = {brdata1final[11],brdata1final[5]}; // @[Cat.scala 29:58] - wire consume_fb1 = _T_58 & f1val[0]; // @[el2_ifu_aln_ctl.scala 252:32] - wire _T_382 = ~consume_fb1; // @[el2_ifu_aln_ctl.scala 254:39] - wire _T_383 = f0val[0] & _T_382; // @[el2_ifu_aln_ctl.scala 254:37] - wire _T_386 = f0val[0] & consume_fb1; // @[el2_ifu_aln_ctl.scala 255:37] - wire _T_409 = ~fetch_to_f1; // @[el2_ifu_aln_ctl.scala 272:28] - wire _T_410 = ~_T_80; // @[el2_ifu_aln_ctl.scala 272:43] - wire _T_411 = _T_409 & _T_410; // @[el2_ifu_aln_ctl.scala 272:41] - wire _T_422 = ~_T_65; // @[el2_ifu_aln_ctl.scala 277:43] - wire _T_435 = f2_wr_en & _T_1; // @[el2_ifu_aln_ctl.scala 279:38] - wire _T_437 = ~f2_wr_en; // @[el2_ifu_aln_ctl.scala 280:6] - wire _T_439 = _T_437 & _T_410; // @[el2_ifu_aln_ctl.scala 280:19] - wire _T_441 = _T_439 & _T_422; // @[el2_ifu_aln_ctl.scala 280:34] - wire _T_443 = _T_441 & _T_1; // @[el2_ifu_aln_ctl.scala 280:49] + wire consume_fb1 = _T_58 & f1val[0]; // @[el2_ifu_aln_ctl.scala 251:32] + wire _T_382 = ~consume_fb1; // @[el2_ifu_aln_ctl.scala 253:39] + wire _T_383 = f0val[0] & _T_382; // @[el2_ifu_aln_ctl.scala 253:37] + wire _T_386 = f0val[0] & consume_fb1; // @[el2_ifu_aln_ctl.scala 254:37] + wire _T_409 = ~fetch_to_f1; // @[el2_ifu_aln_ctl.scala 271:28] + wire _T_410 = ~_T_80; // @[el2_ifu_aln_ctl.scala 271:43] + wire _T_411 = _T_409 & _T_410; // @[el2_ifu_aln_ctl.scala 271:41] + wire _T_422 = ~_T_65; // @[el2_ifu_aln_ctl.scala 276:43] + wire _T_435 = f2_wr_en & _T_1; // @[el2_ifu_aln_ctl.scala 278:38] + wire _T_437 = ~f2_wr_en; // @[el2_ifu_aln_ctl.scala 279:6] + wire _T_439 = _T_437 & _T_410; // @[el2_ifu_aln_ctl.scala 279:19] + wire _T_441 = _T_439 & _T_422; // @[el2_ifu_aln_ctl.scala 279:34] + wire _T_443 = _T_441 & _T_1; // @[el2_ifu_aln_ctl.scala 279:49] wire [1:0] _T_445 = _T_435 ? io_ifu_fetch_val : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_446 = _T_443 ? f2val : 2'h0; // @[Mux.scala 27:72] wire [1:0] f2val_in = _T_445 | _T_446; // @[Mux.scala 27:72] - wire _T_458 = fetch_to_f1 & _T_1; // @[el2_ifu_aln_ctl.scala 284:38] - wire _T_461 = _T_80 & _T_1; // @[el2_ifu_aln_ctl.scala 285:38] - wire _T_467 = _T_411 & _T_58; // @[el2_ifu_aln_ctl.scala 286:54] - wire _T_469 = _T_467 & _T_1; // @[el2_ifu_aln_ctl.scala 286:69] + wire _T_458 = fetch_to_f1 & _T_1; // @[el2_ifu_aln_ctl.scala 283:38] + wire _T_461 = _T_80 & _T_1; // @[el2_ifu_aln_ctl.scala 284:38] + wire _T_467 = _T_411 & _T_58; // @[el2_ifu_aln_ctl.scala 285:54] + wire _T_469 = _T_467 & _T_1; // @[el2_ifu_aln_ctl.scala 285:69] wire [1:0] _T_471 = _T_458 ? io_ifu_fetch_val : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_472 = _T_461 ? f2val : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_473 = _T_469 ? f1val : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_474 = _T_471 | _T_472; // @[Mux.scala 27:72] wire [1:0] f1val_in = _T_474 | _T_473; // @[Mux.scala 27:72] - wire _T_479 = ~i0_shift; // @[el2_ifu_aln_ctl.scala 288:52] + wire _T_479 = ~i0_shift; // @[el2_ifu_aln_ctl.scala 287:52] wire _T_483 = i0_shift & f0val[1]; // @[Mux.scala 27:72] wire [1:0] _T_484 = _T_479 ? f0val : 2'h0; // @[Mux.scala 27:72] wire [1:0] _GEN_23 = {{1'd0}, _T_483}; // @[Mux.scala 27:72] @@ -821,36 +820,36 @@ module el2_ifu_aln_ctl( wire [1:0] _T_631 = f0val[1] ? f0hist0 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_632 = _T_9 ? _T_630 : 2'h0; // @[Mux.scala 27:72] wire [1:0] alignhist0 = _T_631 | _T_632; // @[Mux.scala 27:72] - wire i0_brp_pc4 = alignpc4[0]; // @[el2_ifu_aln_ctl.scala 357:39] - el2_ifu_compress_ctl decompressed ( // @[el2_ifu_aln_ctl.scala 100:28] + wire i0_brp_pc4 = alignpc4[0]; // @[el2_ifu_aln_ctl.scala 356:39] + el2_ifu_compress_ctl decompressed ( // @[el2_ifu_aln_ctl.scala 99:28] .io_din(decompressed_io_din), .io_dout(decompressed_io_dout) ); - assign io_ifu_i0_valid = alignval[0]; // @[el2_ifu_aln_ctl.scala 116:19] - assign io_ifu_i0_icaf = alignicaf[0]; // @[el2_ifu_aln_ctl.scala 115:18] - assign io_ifu_i0_icaf_type = misc0eff[52:51]; // @[el2_ifu_aln_ctl.scala 325:23] - assign io_ifu_i0_icaf_f1 = 1'h0; // @[el2_ifu_aln_ctl.scala 329:21] - assign io_ifu_i0_dbecc = aligndbecc[0]; // @[el2_ifu_aln_ctl.scala 331:19] - assign io_ifu_i0_instr = decompressed_io_dout; // @[el2_ifu_aln_ctl.scala 104:20] - assign io_ifu_i0_pc = 32'h0; // @[el2_ifu_aln_ctl.scala 321:16] - assign io_ifu_i0_pc4 = 1'h0; // @[el2_ifu_aln_ctl.scala 117:17] - assign io_ifu_fb_consume1 = _T_383 & _T_1; // @[el2_ifu_aln_ctl.scala 254:22] - assign io_ifu_fb_consume2 = _T_386 & _T_1; // @[el2_ifu_aln_ctl.scala 255:22] - assign io_ifu_i0_bp_index = 7'h0; // @[el2_ifu_aln_ctl.scala 362:22] - assign io_ifu_i0_bp_fghr = misc0eff[7:0]; // @[el2_ifu_aln_ctl.scala 364:21] - assign io_ifu_i0_bp_btag = 5'h0; // @[el2_ifu_aln_ctl.scala 366:21] - assign io_ifu_pmu_instr_aligned = io_dec_i0_decode_d & _T_3; // @[el2_ifu_aln_ctl.scala 96:28] - assign io_ifu_i0_cinst = aligndata[15:0]; // @[el2_ifu_aln_ctl.scala 107:19] - assign io_i0_brp_valid = alignbrend[0]; // @[el2_ifu_aln_ctl.scala 341:19] - assign io_i0_brp_toffset = misc0eff[19:8]; // @[el2_ifu_aln_ctl.scala 349:21] - assign io_i0_brp_hist = {alignhist1[0],alignhist0[0]}; // @[el2_ifu_aln_ctl.scala 346:18] - assign io_i0_brp_br_error = io_i0_brp_valid & i0_brp_pc4; // @[el2_ifu_aln_ctl.scala 359:22] - assign io_i0_brp_br_start_error = 1'h0; // @[el2_ifu_aln_ctl.scala 353:29] - assign io_i0_brp_bank = 1'h0; // @[el2_ifu_aln_ctl.scala 355:29] - assign io_i0_brp_prett = {{1'd0}, f0prett}; // @[el2_ifu_aln_ctl.scala 351:19] - assign io_i0_brp_way = alignway[0]; // @[el2_ifu_aln_ctl.scala 345:17] - assign io_i0_brp_ret = alignret[0]; // @[el2_ifu_aln_ctl.scala 343:17] - assign decompressed_io_din = aligndata[15:0]; // @[el2_ifu_aln_ctl.scala 102:23] + assign io_ifu_i0_valid = alignval[0]; // @[el2_ifu_aln_ctl.scala 115:19] + assign io_ifu_i0_icaf = alignicaf[0]; // @[el2_ifu_aln_ctl.scala 114:18] + assign io_ifu_i0_icaf_type = misc0eff[52:51]; // @[el2_ifu_aln_ctl.scala 324:23] + assign io_ifu_i0_icaf_f1 = 1'h0; // @[el2_ifu_aln_ctl.scala 328:21] + assign io_ifu_i0_dbecc = aligndbecc[0]; // @[el2_ifu_aln_ctl.scala 330:19] + assign io_ifu_i0_instr = decompressed_io_dout; // @[el2_ifu_aln_ctl.scala 103:20] + assign io_ifu_i0_pc = 32'h0; // @[el2_ifu_aln_ctl.scala 320:16] + assign io_ifu_i0_pc4 = 1'h0; // @[el2_ifu_aln_ctl.scala 116:17] + assign io_ifu_fb_consume1 = _T_383 & _T_1; // @[el2_ifu_aln_ctl.scala 253:22] + assign io_ifu_fb_consume2 = _T_386 & _T_1; // @[el2_ifu_aln_ctl.scala 254:22] + assign io_ifu_i0_bp_index = 7'h0; // @[el2_ifu_aln_ctl.scala 361:22] + assign io_ifu_i0_bp_fghr = misc0eff[7:0]; // @[el2_ifu_aln_ctl.scala 363:21] + assign io_ifu_i0_bp_btag = 5'h0; // @[el2_ifu_aln_ctl.scala 365:21] + assign io_ifu_pmu_instr_aligned = io_dec_i0_decode_d & _T_3; // @[el2_ifu_aln_ctl.scala 95:28] + assign io_ifu_i0_cinst = aligndata[15:0]; // @[el2_ifu_aln_ctl.scala 106:19] + assign io_i0_brp_valid = alignbrend[0]; // @[el2_ifu_aln_ctl.scala 340:19] + assign io_i0_brp_toffset = misc0eff[19:8]; // @[el2_ifu_aln_ctl.scala 348:21] + assign io_i0_brp_hist = {alignhist1[0],alignhist0[0]}; // @[el2_ifu_aln_ctl.scala 345:18] + assign io_i0_brp_br_error = io_i0_brp_valid & i0_brp_pc4; // @[el2_ifu_aln_ctl.scala 358:22] + assign io_i0_brp_br_start_error = 1'h0; // @[el2_ifu_aln_ctl.scala 352:29] + assign io_i0_brp_bank = 1'h0; // @[el2_ifu_aln_ctl.scala 354:29] + assign io_i0_brp_prett = {{1'd0}, f0prett}; // @[el2_ifu_aln_ctl.scala 350:19] + assign io_i0_brp_way = alignway[0]; // @[el2_ifu_aln_ctl.scala 344:17] + assign io_i0_brp_ret = alignret[0]; // @[el2_ifu_aln_ctl.scala 342:17] + assign decompressed_io_din = aligndata[15:0]; // @[el2_ifu_aln_ctl.scala 101:23] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif diff --git a/src/main/scala/ifu/el2_ifu_aln_ctl.scala b/src/main/scala/ifu/el2_ifu_aln_ctl.scala index aae5fac6..96c5264f 100644 --- a/src/main/scala/ifu/el2_ifu_aln_ctl.scala +++ b/src/main/scala/ifu/el2_ifu_aln_ctl.scala @@ -7,7 +7,6 @@ import include._ class el2_ifu_aln_ctl extends Module with el2_lib { val io = IO(new Bundle{ val scan_mode = Input(Bool()) - val free_clk = Input(Clock()) val active_clk = Input(Clock()) val ifu_async_error_start = Input(Bool()) val iccm_rd_ecc_double_err = Input(Bool()) diff --git a/target/scala-2.12/classes/ifu/el2_ifu_aln_ctl$$anon$1.class b/target/scala-2.12/classes/ifu/el2_ifu_aln_ctl$$anon$1.class index 349904f85cf521d257c1c5f4228355a188cf34d5..e22e1e8dfed489df573500b33fa7f031936aa5d8 100644 GIT binary patch literal 6820 zcma)BX?R>!8Gg?sVVLP{mM&?!Z__qOOVgyK6jExNHnfqH);4XSVlOv$?j)B^?u;{c zN{fhqNGl5BuDF3BDsE6|Dj8uk+ zgTU+%U~SR1vX;P1jk7o|66mWq89biPy0+_Y&rRgrtg|QYyE(6znws67wTi_!E*4ny zzj1LS*{BB05G%;MWgoT1oYX)rmrcbnU7#gY6-SFeldRX^4h(rdaWiNl)w-Z6t}}() z1g%DLhupM39>;8s+SD?E1c%5oCvs_rmBWlVn;tYbnm03JW`Xic+8RhTFa&RTqaXgMa|_RE*O8E zbX`}_8x$B7kiDTkdy{pd-u#%Ab<_3r1?9iRIbJd|*-~-b%($MF=F)U^2llqMWH3YGMgOV~U|-}TbY@mlNU`I%BM z>RV&w)smlJCxQU@O}k^B!;z6=PhWOWE^txcwvgw-7!7u> ztGX2BLN(BVxe3IuO`y@|EDJ0gW-p@ngFf2oe5mDYU>@cNPOdVrK)KsxV4>1pZeWqp zhNreKm!^TmSQ0?@7+9*bR~T5PwEYH_EA4=Rl+q3vSfRA*46IbzD-Ent+N%t7D$O*| zr8LVxw+g^Euv%%3fiy}IeP{a82^=`Z;Nnh{frq)?)da5b=W8hxA zFNsFHpWjZULqlG^6tMgUx$3G=RVageAb}6zL4i5d$_n?(ZA038B!Ol;#BIXL=d+y8 zhp{!ul8*&Fs={`VllrTZaah%b0Om244!Px|6;`8)gfmQk*$CCmxszFzZCFlzYJcXwP zmUj--SfpYxb#tWs9DFfJ`)38jAugP{72tYYdgS_^j9V!9*&eyY67gkxC5d)?RiLLf zx_aYU`(+k+7++7aOV8B}Yfux%H(4^UYsB2SYoED)=i$g<=kQx@1lli})V*DvLR!cU&NZcpQKv9s z@#qjtWsc{#gI2)}^5w$T-Htz=OYgM`)`Y{kAn6-Jp63+gDa~QFWsv(vuIPGW%9Q)u z{#>bGJ6G|9$LjsT;c&>yvbiBIlj9d6OGuG1euf}f&j>aaYBPepK}zlnQgUCAlDmSG z+yJB`{Yy#mmy*;kC5c~3(!P`=eJM%#Qj+kcB;89%vX_!nFC~dyO47WPBzY-G@lulD zr6j#eNphEx)Gj57T}slrlq7X2N$FCO(4{1uOGz@9l2k4wiCjw3xRhjS$`v3%V=L1? zFxNvVD4V(;$H1dhV)!G|i)3K}f1++E18m0*<^+dzkZBmaGYn2@!3(r44~4(7Q9po-WLY9Xu-?0;E^!6RSRCO1s@E9+qB@6 z7JO|OJVOg!p#>ifgJ){NE4AS3!{Aw3@G33%NEkd@3+~i{ZwQ0iwcsu-cr*;2qXlf5xJwJ( ztnKruFt}R_zEa!r-C^)*EqDvwq}e6!34_;Y!S~`VJbdt2(X@%jj~LLH?>>!pP2&Eu z_yDyJpTZpp{s^W>$c&2F*Uz)_% zCh?8B)}B9uy)~27llV@A)xMfl>yikYkvbbA!scMjCMuw7FKlx7!Y0>W*yPBCO>Vfb z$*3|pe}2JaO&dwkz9OUR7J3GiO{bYV!2`pQCL5! z;#ke8CRFA1`2S&Zb5sMjL{;1xRdHLbIWGI3^7o7Md23chcE=Rc^S=;fb>|eTUq$%3 zD=MB-HF#@l1o-a2<|&-J?ks*+`H0#0xih%uvFi2bem?L47bA%T9|Dtn5}Sqtya;)i zj+16(2<_rI%n>i4Bi4Yqu?3hH+lu)y8w+A5 zu`u=k7R8>x;@FE=68krnHZ)^dLm!qm97L)ihZPN{u(IJntZH}xoelp)S7Qgd8+)<3 z@c`B|<``3OC2LpwSiX{xDRCcuPwM?M>zV}aYi&gn{=!T*WrD#QOq&^S8|6&OS(NRR zb0|r*{AVVuH_~On5xu(^yc(W1--DG2taw;P31L{tG1l2K)d3 literal 6944 zcma)>XLuY(8OQ%~l6=1NTE#`~UA85;$Z|`O<6y~6j$E)L8z+QiwYMiNI_+KV_H2tJ zgb;!qLPA2Q0fIvhH8HVF91=o84L$T8457C#eC6T4GuO19!{~W5@09oV&bu?S@666U z|DOv_1K5mz2`q4v`3@(w(WEr3lxNz0s-?y9(q2nv6hffh9&vL{YEwsd-b| zhk*4t+e%piGd0Gdm?E&TXk^#POv<%gzb8GGaZ}F0jPItsT+8HQPs+;WqL?bM_^caZEckO6N*#J*l)k%Eq{5`|j~V z^K3ayxpB`nooqIpHFLg|^#z(;+a5Es3DdD{Gm*{@rJO)PpvkpO%eI|d&P-bQly4@b z^5i;yJmUlnWygX?W#7|-?uIgEa(E;gC!bE>MoP{p<5 zZ;+-dDmsG-qX^lXD~l(r@k;gMR?1COwr7?72IpknOs4X=5i{v}R*D0caBS1vU{Y|9 z&4hq-E9v<5h?%f_E3hJ;M^({s!3kB)*o7i($X*4e1unAa+7?-9u23?A5#xAOD45C4 zvVp`9=b>D5y`0avh!xa>uHvQqX8Il!l0&A=cOgIK&`_vmW1)uKbM##=;hZe@UYMUr z6+^x?%*7no&5ZFO0tfhdyThKtk&$ChTXs+{FeNaX&2VA#xt^WMCmb0OhO%a6)Hj25 z(Ae5mT9FiXj8c%1MMo8FtA2BkTkGXwT3>5mtIFMC;0o3HIs;d#-0KZorE+gDaJABVqk%4!dy|1}DtFqz zHA?Tz2DYoZw+PJTBxvW@z_oZ;FpO{Idf4WAuD?Cd*3D^G+Y#!tr1QSRMZKgL%c_L- zDBdm*-G6ZBVBfA5fn}w2R7Jnbz&r7-7~X+*vzLB9>)KqRTPqe%6;QJc(AI-^Z=AN? z$DOXV)b(UlK97O>@lYJK_yFIc;sf=1nS2oXALgnnp{i0k`Jos-hz|?QDK!>11i6<; zosY&)kB@Qhuris{xPeEoBhH#n1W#1Lb}~A3l}cgfN)1viF!8B4JN`6ZMMllpV;Y@GVf35cUyI29|v^|dXHAK*uECY--%-2>g`j-5LXn|o>R zr^?>XD(m|W8u*2(|0Sm=(C;4Du}Au0;Mc0PIkcJAtIQ{G!J)2tgIW93zd!g9e*U9IAmq5F^6-(@Ne{bo|BbF zH;2WBUEE31IoBIjs@(DV)A_9J?B=nL&HcfNvDZtnyIwDu<{Khw7%U@v4Z&bNBiLe? zn-T01QgV-wk~@Ty+#jUm?jR*M0x7u-NXbn=N^SvCas!Z(;a^Gye<>OIrDWijl3`y; z27M_R@}*?Jmy+RLN(Or=8S15EpqG+iUP=aeDH-CWWPq2F;ay4wcPSa#rDR~2l3`s+ z26ZVJ(xqfTmy+RJN=9tTRbZgT4yJ!(se@8b*0n#5o=2I9;7?4a$jTW0%)Fr#uoJsj z5**&$OvCWrFdWyy3$^gRFg#5QFVec*7lsWjyjTk#2*cC0@DeS2C=AzY;iY)FX2ANx zaDx_Ju7wA~aHAGpp@olz;U+EIqJ@uz;Tc+Zr53&+4A0cUtF-WqVR)7nUaf`AFg#le zw`yT43^!}xHZ5$2;W=8kT?;#5c&-*+qg|fEVR)VvUaN)OFg#xiuhY6c8ip5W;q_X0 zEDSHy!W~*T9flWa;SJhnz9|eZ*20}yI2VSOXyJ`oxAS3msTSU(?fFC)UZ#aNYvJ)Q zyj%-!(Yk$e7+#@;w`$>A!*GihzC!EvZDDw&7QRvo-yVinY2mB1@Eu`zwHCfw`^r`{-hRdtmczG4`@+#KlRqV^FI7;Qxi65@k;FgV69m~Trv4-?1^d(<7J~7SC!S9{|}v8t95W&wT9cPHQZ6|j?4b% z{Qp(rk~OP5yK|E2rEiGRIyFh_#VWRffT5j`yUTcEV-@(GK<7zZJa!&06<=a@e(@ac zd#v>OP^FKoJAC%7u z!H-c!Zo%8!-GVozI|MIIneYo!@P6@L-WCQ$en0V7lpx0sK;8xgMSd0ue)Kcp$AaL% zGT{e{pkGXQ5*NIoWx@l1;0-7fo>Y0y6C^x#3JyLK?z4ioqD;7T3Er(zkEc7q`&K4A estMk*GT{M6@NSiLJU9y8lrrHrw7@_49QZFZk|m7* diff --git a/target/scala-2.12/classes/ifu/el2_ifu_aln_ctl.class b/target/scala-2.12/classes/ifu/el2_ifu_aln_ctl.class index 562da6408b86007a0a4019b2185c5f226559dc1a..995bb1a7dfe12a39d2a46fb29e9075b4d2265738 100644 GIT binary patch delta 17577 zcmZ{Kd0bOh`uBZulOS6lf?xt@gMeZI2|K7@0O}6Ny?VKs4o&sMAIe1sd&koiW~&t5M-*1$WB0F?S5+ zPvE%5J`?i?)p)Fen?y;DJU>Cfb7kBuGo~sGr+Pt(f)A?kGzB+lRU2d}c&-}HQ*fsm z&vz?~K{dm!;3l1FgJK2GRpaFf?o{Jd3O=aD=Xr5AOlQ)oHmFe+K z<1Gqq@>9w0Q1D#fZunky!BU0cR4-Ve;Dc&>rGlHrs5V%m;JIpit%5rh+^y3NDU3md zq0?$KqrqkJS8bqI@LV+>px{n5Zcy++H9nT(ZaI2Q0jdomlm)qJ+^pbEH9kSX2W8yk zABgOj%5l4W9$f4URLM_K&3CIAX$r#>q*{=r;JIo%Pr;pPJYT^Fy|_sah3qnZJ&(Cy zS-xA!<6>n&u9qR<dK^3mkj0U^K#4E4c zn|?aI!pN0NvXqv(00nodaf5;ns`0T3Zc>$GomASTV7GWnyCmPOlWM!nP}g>yQrj)+ z+OAV-yTw=Ad2s2xwH?7_@z!?v07_}Ms7t#}F70l9d05o7U8mG`i@LV!l-h3b)pluP zZ*Aurt82S1U$KO`wCj}8ZZYZHijQ?lZMUdvyH2U?7IkgcDYf0AuI)NsZ8usiDD7pW z@zdd!ER+;fm1rF=-ER5%w5V&hPO04%b?w$EwcEmLx36^Tl+tZcmu{U>x-II`ts5=f zR*M_8`x*@sRV7$ApqQ{sjjvbmPBngVgTnAv)mjvDU!GeM)%X~_eX6` z9Cc!b!bnsVZC#FxU+-}QOp>a#Zk96BUsZi|MGBs%#!D5vOpRA6c&8eltKj~s;;UPr zRBKD3no+APC{yE$6ueW7Hz~Nks`%>K6g*LlFY)2-cuSd@vE0Xi6V-T+g8O@`uT(1f zWSnPWqPi*%DD%tI_<9BJff#zPg{Un%3UI(@jpNK_a){dh0_BCCy{Rz~I*Y70xXGasKgfMt`Z2m=bJ(OC2@qBf1)9c9#rYKY30=&Z>f{xbcpd z>6n+P%%h;CC5Gkwl`-i}6^7{kpt_tjv(u9LlgxRmjEP47Qj5`Ds0q_qtQ9nNz5xQA zX&tVr^&QF1>0O;e>3(+6K3yk{4K~J-IH0qRUExe^DKR8vcQ>TE3TxU*y2npn+Z=)U zP<*Ydcs>;GEQR9!H&nD6Cg=inVwnGIt4*izZwR*(WxAFPh52=l&sb7jzP=+^bn8WZ zfNqk>Qb@Y)0PCcvj5P%T+JQ>b^wxrTL6f`d(pMLli!64_B+>5gS7s#p4AEBRN^VST zZ5|Q_s>~UE74x_ty=YM6G{<`71l4Eub=ucT{IUNpzMD@dmM26g6Ktab8qzXl1tu#B zSbYjiAD_H9)df>_mRpRHC41*k$b54W4v^c_rEiNg)Jc5*3WXo+PWjqr;YcwHBZo(;xiV)M;)DpqW++U zG$_!nC_sKv@Iit8!nDc~Zu)$m=Tt*!!dkQV%Qh2QMs7dxEkZ6#cBv$BDtxU@lE zcF2T0C_a0#*K)a2Y&xIfz0$fUtjm;6JWeytr|A(It z+-P0G9qZ#GM~KIp_?T%tY3&w^waHFV{>IL^qDDNqL7!`^T9nqcY;01b#%|Z>)`i<*&DrT#fSt2e zBPp$x@c8oU{oSTA(uvxj;Mvu7o851mziH576Z=XK^vR;A4G+$=G~434JN1_8fcfzj zaa?ES^OkPj>P*mwOQ+5}Q6p7eh)t(+LLuz(o|$U9K&i(~!Ef0k}OTeH3pWtHRA@Y$(rnl&6gkUgVu$XBx%bj$#$V ztS}sQ1&@s}_c+Y5pw{xWE(E=_acqN0!HZRRj0(4p;>MPk3~NDMP)SNux@Mds!_PH- zhP%a?5Qh`%`W&cVFyYcNeYJH?ok^}cW|+B=BwaWa<#o0sougP2)?BE1wg=c+V%(Wa9jLqxN2;rt0<0}D z@^dnO)-_v0>N8!qLLyz`Gf@1k&B2b$wnB4Iugz>)TB6VJizltCHJ+CN8sjJ~&rUXF zSVWU)NpLU}(&t*|NEX$G+3b0)Rwqtw)8e48EPNlBS()AKHkmZRoG_Vqa7C_YNJ~R- zNuy1dSe;Uz*VeAH$|D8z+Dv)vh4X?UCzGzVeQZ$4G$+=@7$=9+Syva@5eqWk&##Qe z%r1|MME<3V7B9b?TR$5^&Vy7mc8YkmX+ANRSFe*fzRTV{6nWt;Q z;kYKU)jzcQhA|qXLT*g?ro2V&grgATkX_$+LG(idg|@rwOtK)9c3Dv zxGr;*YhGMjBI#W7%cDy}46!(|HL|K9Z*@CbX1l}>kMl310J)GzF0#mJRw=v0Vj7bY zm9e^@eC#-jF9w1khrf?VjCl$ph;NW=^>fvFgC#gtV>0U&@y{Eve)yCWO zs%K<}HlxEWU5<@8a(al~%aT8r2iWZ1+qZjBs;iw4Tu7tt^7S~js03SnO`c}KSHh2;F zNh43Q*+Ci8%-Nb?d9;XDDZ83@uy)nDGrPr1HIUhD)8$I(RsmB}VfIp&A<5<7g@~uA z)70TGqlPca>?8Q&5p~yX$RmX?iPqR~$&k>qW`5iMbtOyft#NyFLy5 zLlUp~u2x%kZSaKYsCYrzISuKnJ2e4Dn6?)_&z^?#8wb2QI>Y6Ph#Mmn9@7lJss>(o z()xp=@_1JG`I*x?N(@18m8pGpM07S{!rx&p&kk;!*;}D6lL}a8hqe~@7>8Xm#SOu$ zMGF?jrBQu!A6b$Y`C%xF*2%%du%vQEADHaRv6{9;v4g{!U&Cny(hCe zaK9tC4A(p($V^^^eb;u>wa+}?{Ytn+P4b8sYYq-hTUFuCi;EyfyWB!E*3RE?M>LG`TgV z;PtK*4bxXt45d#_=03tnx}Bs)bmqYHI!C!CCm9O0+j#ouUClPU0>)&oaTNzx5#_xl zLt-gjGq76e6A_4QU8co+WO10t!!{ba_Nec^cX5 zz1^hz)dYAilW^H|$?|RIbD6id>n)iV;O*_SIl+d}o^MsfJYUbp(|Z&jDC_|4mYTsC zRW?tkfp2Ne*wHe+dfRos|vXKH65`UA_g&&VRbKD^l>sB_y2VuP|n z>M3M&D;&+4tld6S{6CrziK}5l_y;2G7NZhdpO7_B6~Zj^CS5Euk<_eXHF-+z<>Yz!ieYh=MA2wlf%;ZPw#lgDfxNgi}Lss#`UKR zp0bzZ@spQ^={HZu%Om*x&&wm8f4^+-?098Z8q;1KCc*RUt0NTbne*BR89kTq8{rxJ z3;#8o9`OX9Hh2!59;PTy&g&!iJ@fjA=grp*p6)k>DaP~58zW@#-1#Q|wVWC8TzAIc zdFjkBP4ZN{HR36M%i#I(tznwwS$%ediaY`5MyS-Y6Tju2jPoP3z;hbEHJ-+|N2u2G zfAH({YRo);)RPqW>aF@tnFej-AP-$?RA*MX-PznoL#+ zECI=^IRJ0v)Cx|W;?zD){m!XxI5j;NRD3R|0Z^19Eqc28K4$$DxXvLfTA*K z$y*#e&cVQ$04pW16eLTV3Gg-!&XK?uIk=yL|K-%ToSKmj_I!yw2$Hqt13b#9U7Y$q zob8m@sRaPd1pvE1A)~ob_j0mXBERNjt3<}l0=YsWn?bUQSy=TTr#5lwB4@9W*yC*g zH8y}ZaH@b)TRF9!Q)fY;0Pu~1>;SLSP>|=%O98A5Pc+1O?KFe+*fH}Z4&2OVZZE{d z1GV0XGx^g5r}t?so@k>a?-(aHN#s8`xmhBuMIi5z$Q2-2Z4qSeDcx(rk|r<|PH z4+;f_+xJ^ezRQf|Q1Sx_X)OmLle;*1K|((U$zChRVsiy3Extvug`nsYi9N!}&n5D_ zLK-SD^#q?<0g5h3{7szvN+Mt3{DYO?YaF0{;8X#p5*?t{bE<<=&v5EtPW=puev}rc zR{@Nv0@%Z;I!-;oDaNVqIQ1^4CeHz7oCB&26#ZLT{168>bMO-m>LoC0E;j8prx-Xeza`oi#L# z)=5kZm|w}>s-Z%*VIdX`$@q{g=kh`dV0SE}5L(FYUr0Bw#kG`7H_LNwW(RA@!S1ZZ z+5#sfvtMgz7TfQn9{{kTa%z7Q9Te+BV;LPHGaG28 z460{MtrW#h9-<&kXgz!A3yNVU50f8%__djesey$)jR}n{6b$;*4;0NdwNMT%W~W*x zLu`h$^UElKn%SxMz)O9Z^vu>u697Q+6b!w$0)MoXjF?>EoBWx~duSPWJr9yUOKGEG zu{AWBSz4jnJ#Cav?d)6|b&`wawWC}uWzAbKd1pKMgMPdn23W!V+D>s|cc@W5(fAIU zD)#s^>QQNQR|ic1r$FAmhaI}ds}uEX--zRF*-t^*(4NpjW_yO>IW>nXGJ%DjAst)i zq9Izz4H3(tm%tD!*{N3`pm+&IgEl@2+P#Fr#g(uctP#aN>!c`f&McuiaaHIP`B0eR z$0|CpewA#L)MqJ_)hrx|9;c0rhsNB9l$-C|h7atZ|vTST+#To5+M4m}9^ttTi@6FMk6DYcul?6c(( zm)@l4WBy%qgv5=ZG2Bs8HNr-A&&LpqunX1-8=>)eFAPm(n9rHD5)ae5;ek85agL2_ zLl1zbyHQq8te{P-s~e9iddSG`>xK$V-(u#j9tvh}bWH&+yWo zo4NMMw3+K{VXIfc)4#0rDamEfohq&3R-ul`YG5H(qq+|szMG}qf;C(Epv~RvHg@GEq|2p#nkH`JDR~HXPamK(aFBgICvW3MNW_dPzIFn;Fo5gmR6k8( zaf39Cg$;mO!>RTGgk{WHieoegtZgl@`J6h+sYeIFZCD4cZ7r}z)&cWy>Ss=Uxfa|V z>%qNg9k5I5fxW}2tQ$eauLt+z8^Jxb9$4HEu&^6Jt>IMrjeK7>m5L99nzK^Z-M#o2)Ym51=~WkQTOY1I54$r#GOE?vU*icN4C} z9o*fC;trS#Whg-->|h&SMqa}xCid&?WMFg?^cs6J^qPMY*J~|O;q1*|Tn1zNEx>Iz z1BWFd*z>m_wRicH{_Yl-ewSRp&#glE?P3p|heuByMdcTE@q#o93LLo=I_;LT_~Z@< z*bM>J*Wj7V+b9wop3bcEHVD|Q7J!G_C>65{cedAFs9^f#FP(*G3AdNQBc}9p|0*`H*bP2dsMpY@#%8gM(DCfrOO_*E_+z- z?a*buR^~Bw-DXS)xC2viZ-X++?|?FycS4yxY~GzvX0J+_ zy*_2$8-_A_Rm$vDE3=o`{y?eVOC?t_%U-tY57_69JAM27aOeM4Wgok87p7eJ1Exr( zn{gLZ(cuDwq}VOE91n0+%30GE#O>KFNSb||GT%ex;t^lw-na!94w!m&*F9vRBRugq zd%o-=u!ETY77Af$TWPZRlpHEitbZ$|h(~=-FKwl>;xmYLsYo33&}KTJm;v;L4-gT! z!vomn5z3_J_&t$`p?4c4Fyl6~Stm!Rnz3zEO)s$Pw$ns5W;;c)Z?++{3%28;e37Hk ztbaR{e2LkPBdad&qd?Fnx097#X6}2j2$y_3y&?;!VaT9Y8Qllm!^lLh@xm6(PBYY` z)3P}2y%6`hO5E$raWBNZ!NnEPo3f<8-3v))xTG9*Dmg{Mt>#Aes3eJ7DIAcfibR z9|V>7AXRVQiGT6?Kn}}}oiq;g;bSn-+1*fM$4*p|3vA*pDqs_Kp*38&3&p>YQ%82; z>i>i{V&^D9D|{jclhg_6+4T>>!=K6?{*)Pa!^4LGv8IQxb@pyV*XOtoZ@L#+?%Yjb z^f^DewCBzA1y>aX2UP{M6gB7;{n*Zj;j=GzksM{BqngA5A3+KEg7v%ve8#KL%<%{= z)JrNUmsC>z@(83{Qc1bQ`?3r`ihwm})aWZYc&|K;+w-|c(R+Qx9{Lj{vVS~^H2#`h zd5oqSwCWo5HNW~|*rCUfEnRys=^K@V1A8Fh8(G3vV6t2Hpxd7E7#F?=?*)q=!-DT* zseWpy-|_1lJ;|V zxUv@uZrzIollM`C_%otj>VE6@p-2CjweO=z;xC9`9~j6E??X?pX&+^?fc+<9dn?jPbVBM&UQ+J^(ovpFp7fZ~*sa@&RgLHy)&H68McA#m*f> z1rpdt2hlcZ*nbaFvZz69^C}qFqMQL` zhj5_G!)R649Kv-V%i-N=DEkkeeDET6)3VnOqjl0V?Gfaqcmy%O@CZWIpO-3hrbnPk zAhSG&%5e@%(0Ij)+WsVs69dse9X^GZ@<4vlC|3U@-U5TUf#TWzC-Ks{@kyRiPod!p zfze@^32gs!FkA?)5K=d004-%DS^|!v^_axYK85%)ayiW`F1-=Ax5C=N^UDa zUxFqEhfTzQ%GE4JhU!&{NAieC1Q^CUuL*4Pacm#SJE$pIiu84yUmQn278#nZ5*jJD zveGFd<^At`2A4nt+xraMZ<25Cvrm(su}NJB$b?JK_jadc)0V;3vz|qZWD2#*m*Y}A zVZHR);&~Rgm5Dv`EG-tJt~pecd??&3$Kaf;C-5C*{0Zu3`KMs$A^1d$k?&rwhhkXh zR|p<7ZTRqtUP*`kOa^fx?_j;JuHM5v^Jg4qq8v{lN8zEbWq=2r6z81zh1Zo3P{FNWVas2@ zHWS$$FW}^sYff&FPi~P<-g*)z|Mms>U+s|RM40*E*)n*y0%`#M*WyqU7 zbmE;-li^47c9B}aC?{ymA7wwnJQ?z24J zSRw-QMw@{!j=cvh^5lBu_dZ^eXRz$|X*%?i<0W5qD(;X8Vm^Q8*dYEKdGhvXy#jhiqL12QK{{#^9>2hg@iPB|WdVi9hY zhd!a0P`}03_^L?yBqC*K5x=0NZ(}Ikkk7xaKKvmXpCbM#fa?ix8NjpndZwi!?2J8_Zf#d4HsrSRr`gl)=Yui_JDlxV~g?rHS#{8Bu9&1uW= zkT@czMdvHN$o7Cn2@qX6I{}lfcw}6#>N>x-N7dpv1HQZ?M4x9To^i^Me zioYP#sDieJXCgi>VtcVBG>PAtW+ut1VLhKwwOEUImsF_bVHU+c`T>g8@-`Tsu|9_j zYjNxIgO8nhbj)wp^a-`xr?NXRD^m8|v!BDLwd^mSL$(w51D6dVc2r3nTk-|Aa4ON` zW?z3n6U91Qh>~7)%=$Ona&^87qE3Fxlnh!Y2f;gk!)u?Defu|>ON-=B zKdC37#v-X3W*aVn4V-^O-f#hXFJdPzVQM2YehJ?-%7?A}5}Da3cc9X&M#jFRDzOP_ zNs2V_OF0G4-qdT7O)GV@pufUve~bLZP;yKQ3@cgtV;;>datBfUHC`55_yrU_E(iww z3hIUL`@zWEwoC)-qxZ&Nv5$Lhbqx!P2YZ&NwG&FAR^s7;)RYz#M+<|xSm(VCS^HX&6 z9c=Y?2+U6T^+`(5PTmAXGwJl5@_hhDXj#tp2&zsr(@Ls$vcB)hLCaLGTQ=%CEerYq zxew;3|CX`RAFx}O_Z1M`1Ze!pCQMH)ev`#+I&{YJ(I(Fw(bT8|gC6lQ8Z z7V^a?VU{>Yu!*+_h2k-xNc>)yt(_d7K^aOt|tPC*;t3peKzR=CWn$VL%f9OAjfw9Yl!LSNpUD!rpeb^~s zDC}3k9iA=R9KKSxCHx8D*6?qHjpP0$Y#R4J!f?bzVN>Mu!f@o*!tLYTr-e=9e-<{I z4hnagUBYJbh;WzrkHXzig0Lm(q_8#mHUa+tBW#;^y|DedWdgJ86Yh=uUbrvrdg1=~ z<-!9AzX{tWj}vxGF$oVQ`UyJ||0(R6`jxO_>hHqtq&DH<bP;3=06!!`jiw_GQ6<-xTDY--Vv@}%stn^{wlhQrH z=VeQTFUs!`E>%1$d{vn)d|kO;_{I@0eCv2n_^v8a_`Yh3@Z%hR;iow_3zz5oN4PS# zPq;ewN8#_)9m3DmhlO9Ne{~E0npYzHd){xtf95|a{I=i?;rAP!A)#gpX=-+nxUh$` zwGpJRts%eK?c`tkHU&B#q~N+RGSn@gkoq_ZuE$^d>;Fh&>p!NjMH48zp_q&f_*aU? znH0JB6N*^;Gntxo6xIAc6y0)^V%io`R9iPqY=56D9q!jD)`kC(T2e%DonMlr^EXOZ zHl3y{$G4^xO_bFAUrOoyky2M(q_owiDWm@wWeq+`IqN)>x4w*KtiPS|hx};PPzBkC z=2Ovzi&T7*i%M_yqw-twsPdL#s=8$!&Ap|E=G}4^Ex2tP)ogr@YBz}S9?bc zIq%4%MVo`Dar57(>CTU+<*p2ByE~dXww$8Qdrs1_t^6OVJk;&^JN1lIQ}4(jTD2{N m`nIj0)!WWc|Ms~wu>Bo;&#pnne?aT+&7vERC68z-!~ZWK(Pb|H delta 17666 zcmZ`=30PF+`akcSnSsG!m=OeqO$R|lMHm*@R2&cy5ENWsK#-AT1QjH4!IZJg$X0F0 zukD(xW@>7tW?9#z<(5m?dd<3JUh7s?+FiT1oB!W;&J5>xpXdMdJoEj|@7vz*-M;r6 z>`(6n{qkPW=7)8$dK$K3%VTMtQlfaP;d|A5wZdEVs`cmjcn?&UtL~^%COFl6qr&&9`GpE^ z4Nz^+rtrCHzC+=i;61RtY=TauqgOrQCWW^Ksy0}u@VRP!jlw(Ce4oPiD!fOh)o2ta zGN?AtD}1h+4^nuinl~wYubLmK@YW#J`r(}S$ljZ)?ub$*IMsZd!uP8Ac!jqPkv6a< z4?%Q{=X_z|9GJLQ=4DN%tHyhbDv2g29l2^gPvM@K%%R0P_?+SIyTcyi?6LYCMCs?^Sm!R3=zMR2#G@ ze6E`BPQln$qQf=S_f)%;L}x2jUIE?nVr)x4D2C1k-MkxeQ}NQoAiz=TU60Q*ygao!fOvZnvp(yH3gNHg#^-`E$F)ZbND> zB~5@1w`5TY7f_YDbv$)@&fPjCciYstTc_l18_(VT)U8uew@sb8bxP{CsZ+OZ zFm>B)9^~#DBrH{Ovre~GQDM89Kek@!FsO1ZlDR*gZOLjrP~l6}ywRg{w5vPJ3U5&5 zT3wjJC#(5Lg)dd}F$&+V=12H=+`l%1Dmm*ClnKddezd}us`+sW->&A<6yBi9&ALp5 zPX=!pG-8gg!`m7((jz(c6q(_UZBS)j-Bi^QYJR%Hm#X<03g52gXDPfvm3(z`l&ow^ zR(I4Y6H3+me1&gU^GynGP-S0Ti^3@es?T5Uz7D+sd1JJVOpt{b;%i8XtPCE3zmVzU%!LUlHK zIfc)T8n=3!GjC0UY3;m<*t}(}ebLiXt$8aj&M;jW7ctuuQ_~rl=V>hnkI7ydnXznf zP)p6y+KlC`@m02}kV2bIn`m&jhG|A7#;h9WOm8W#j9ERS&c4!Fy|yhF0qv;86UQKMwD)dE;Q6oYo}(R*U9Q| zS8IDb(ne$dzX8S`sXs&Mr@;ksTiVx20?bqda9Ml;tW0%IYN~)LEyMh(9IlB?%&fry zx(n)zCF7$rc)!P1r5a%M4=5W~(iNEr6(x?c$QrVaas;+@&x7vg=l4|gWkgiYw=dMCQMeMM29M>;{ha)Ng01Qp>4Il=X5 ztBTU6+6rx{Vxb|R)Ix=mMSH0`r7_K2UL6zA8JXL{1(=}-5G;8g1X!wXi7;^!ieWwz zR)o5Wxa!LT+_hOPMNxd+bg|ImU)Uin+~HbRo}FUNY-(@Q)^aZ^3-Y;rQjjY?I&)>g zC~eQU`t*er&_DqCE0unSzuy>@-d1Ab8)W^j;Cy{|XKem*2%cOC!N*H+GmC=!lDnjd z+5U-R#ALr*j`uQw$?{Ms1e8AV`ZK%WRi|@c-%e%&_J!oXHm$?q6V-W~^k{+)gN1I$r?{ z&>5A}#yy~FaNKZ>=x3C0Re_? zTXar~b6$d{CPfsrfx$W(P0d)^iV0njxl7s+lrBe7Y3MwQy-H)y1q`<)$7?m(p~)7z zy@>Q~6MWvO(*>kj4TTO(SwpqaVGBzvbLf(*I_4(U57FD@Rs%yvO%woQyR1eVlgbrq!> zDL&Tfo}FhbF_lta^R#p+W-u>O?$?G=(ZuDh>af*VPZQb@78nwj*EBm1yqMQI$d@Jr zD12tdQjcB|Koe>WYr%%T37P2-gbN1VsOIeouT}V>+>8ZLnezDJu%61OOnIH6+;oLE zs(HJg_kESby08y584?e!KD=Bjzao^3TF>B+7`xUru)(k zG-pq8M^0Sm9F-7Z6Eiag`Pfo-g*=`ROa66??)Vw*U<7^Zx{Qb<3h?w)jmqTdDWf3D zs7-X}RnOWmnwr->JBlaXsHTcS4Wi!nTxZ2|kYizNR!0S{kd%rvw~K;YjwowKi9R#J zrOC9v5*2!V3m&E2T zbf#-VZ8#ZsQit3^a2>)dI&ge+<_a;f6!}onP++1%2a`;6n|NZ@S6N`vMGZrZC8<`6 z#%dXty>xzdcWZb|jwdxLBU~38s~0teu>rHo9WK{cQERYO2ggJ;@kF!4nbYYi8<*YH zkk-0}(1c`%&gTPBSjf+hRPlTRrwh(GI8L)%8`H^T7+xm)QHNc{HCrlRC4plTrq9U1g>#Udtd(OuG)+)hpt;u zY3;=21>rprE^Vg$hKVs2jiETK77OT`%f`8p33bhlr~08uaZqK5K%y zrEm-9s@8SRu8gUvh{{AFlEO5-JSr0@Ji7yT#2giGS9q<=$J!$TqCEU|H&S7pwY3d|^MFhm=wY68n2gJ;D*W^t1(uRx` zVlw!K9CtP6Yw z5)Z3kzOX_ohn2K3!U`<}w)#%yvd(aiw`OaiZ+y0icAvohYdg#T?2+$r9`C`yT%~ro zg_GejX>JYgDS?x@T?Tl4Oa`14iKfxMMzqSUJP*aYj?Y6&(!BQBl?j1Ke4cGac1WBR zb%Z@2pgyaoeOeH~#Jry$TwmdtHncXlkvj`o*bvT=P|=XlRSKJ@1g9@A&r9H8*UpN%OS0oL0DWe4g|=g1ZFcxd4q;_?S`ZZ>AvoLT65wd)|_o zrIDG<9+%E#UmBCsvv>mDu%goOhU8Q~r;B#$s>=C!E9=8~QHqmTaFT{}%@8IRp|=#pFM?(l#>6+54Y z9VXUhArbK~$!&p`N?{`PBk>HAFAph9QyhBvc9V*8WH|XUNs=|^lyAErpUHfsoy(LE z<}2+2x~$Q@lFyUb)f%1<>FY>Bd=J)wUHTb*eidH8Y+|xpBUX)ynVwofMpQrMA1deyy_>9zTa^uC$gBOVIlD?vdrLkF>*ujn0>c>0t+8w%Hd844P>8Z|4 zc_A`L3(v%7fTB46I7&~gOJCM7G%N{a_M(D#V|GYA4dokP{pMCAprw&n3*GVDRQ$yx zED&WrqQ+^mm@3kmTlq^iY(fXN#jU@M>b%3B9Pobrl*xPi$$pyeEq!VLzkkASqj&k! z1JvXVd}e^!yuZWmB5(Q*{`(ew7klSFJ3!05*Pb2lMm=ZpdUy8I3UBmt1GLt=55McY z#k&T)ox4rmZ+7+5dT-b60q=u*OkT^Les9Y2Chs$Q`e~zg{PP3eD|=1e_nz;U+Sa}O z-d+1m-hcbr`}XyFr@UbDChV8nBWSN5FnKFqklRaWlMkA_s}IO+@QeN4*YNy=ugyN# zPmg+ke{cZ5a}M#}Z}Gd$+jn@tyW=I3cf?Em-ib#{-h(go)8pPrM+Ur`Uom;VIMOe* zJul0x;gx=R*}LVH0sM|S%70%uI^aEX%;ar&wO?v~_O<=5$E(N7V@lW%7=Fr(bH1q5TZcb5HeCocHrn z1Kvl@n7p3T{Zbotrr(=(*5uuJrk@hL_Ok<&=zSBv4sZRt161t2ir-T2#`gxO+#7Xn zfaZGl;vw-fVcfqllQCh{odcuuKKi})_AXf3U4|vaKSL2eVR?- z>_9dpQJS~v;xKjfnUVvvg`*CR&T_PaqanFKf97a9N48u{&Xy)O0l18hNEK~B}@eR zFGntp@+M;VbZL!Mfb0S%U*u%DL|)_M+({tEPXbvfk&6M@yPSNMBjaSC%e=c<>W-fb z@^(%x;OHbrj{?y=srx)9Cl!DUF92CDk+V5$l;CC#7fSF9hb$9YBw9v>FJu<3>8jNoyg+$6zIIlNnf5mPbi=Bb!9hohG`+5$vdr0%nvOfLpG zq!{FYL{8^$uLL)8ctCl_}I;KXTwMhv`os*+yfuva=10`}Yhd~m& znM0!lU*gat!M}4jRD$VMfGHB};xJW$yE(K=@LNDRzl^E|nI)0U9LmXLJBPUv`#Fbl z4vCr#I7wn_IFwVz0Ea~qdk#=e3#K_BDSF{=P_`flHA0|3Xj5L$$B#LruX#bAEFRL2JETv2MQ?Y8>eDU4 zdfzg^>x1$z(kPE-$7?8zO|7LAb`eXm7dfhO(iCQMQkuBYzxPJgdT~2sY?z zq7yWqIb85rH0LRrrEMUi);!-lnQi$aMH_r7HqU1lT{MjvnRyQeo&J`L8gnD7T1a!K zi9NHBGHD^Jx|L$sdy5Hw>SR@IG?FDXQ!Fsnm3eWYIged*QxvOwb&^e2dw=tvGEL zJK9PKw2WPB#q@5KNWg701=M?Q_@(S-TV4c~Wa&1S`DE!f7x`rAHqVr0X>!BMm-C~? zu!3WxHw7$sL4VG_^>P-nh;q<>%V}Rf>sUl4ak;sk*?t7Y7Eu(sUsyzS)WeQ1^N&hx z$EY5tL>jgEH8QdMMbKUkqmxjw`5*7_rw}%uQiqGZ#}Zp62|zl%vBx_R6sNl(!)JWdzq@HWySJOd z=uY--CnckSS)$qcWu#+2bW<=0s7i_k6L3`*@RXZqDDbuA7{7^i^DQ5~2}|59uimlT zzxs*gG=t4sj;?$DciDSX%ig0}_8xiJyX9qbdSK9_Jupsh4+XRDdMJ)P)kBfu7IOkS z*9rZc?;#6qVIwX>F8vC~wMCBJOkj*Emq#_PfOnLw#OxqS@A!G!jpCrH=;Wh|#X1IP{d=&{MUF=CZF>BXr+hMX4;O z7bto)(4D=sn(eyOXll!=y-cAI&%7eqSpc4*(a}J zWM|h=Bt62me~yD*y#;}0=%Z8+$YHT;ULW$=BmAsB4|qfloGC|;_Jl{+7k#vt9%bD} zX*lcfP`dait`gWK31B?i|2(Yst%p+aG|f*-`HlD2v&UD%Aor|C9^cBIUr#yg!&@Mq z;TFg@>Q=}HRVA|EkZYHbg33UKG zF3bAv21=*LdDf0$zlWELkDEvGm`(!7ljT}@8|2!?*lmz&`0X^4#ciZecFXPb4Etmw zd@-{has}KD{dV=ExAS)Np6f?ud2S;a#ix)vrTjj!AD;9SJVf%=D!l8_({c_N@gCRV z(_ElvmiiXr?d5)o5T8aSkY-k57d**wVbZzpA?%1|Sg7<4+$K*l_Z<-Jr%nFNtM2rR zro9WIeXRmVGxw`~5xs&29JkMf>nxh_>S%h!%1mdL^B9-v`mk?ty5# z&yclt?OuqsM=jbOm1rHeL$p0Nh_=Ts+8&i?-`)q&cCmoXC;~QbhG(^JM!k1|qZff_ zKi^;^yS|yq!~+O@$q0Kk!_>>S5WdaG5f37OkI}JLw@^IT?oVJAi52gsd^*S_i)Hig zr}1=n5F6Qx_tQ!7WkiRx?0}c8)g^ zH)P$7*osyDv6T|(O?g@lqY>g;*vs}14zQY$mHxnnKZMBM&nTMS;iHDLD-4UDQmuN5 zr9X&OPpekl@E}$_Bd_|#gIM*fe^uQ>SoK}Ls*}#iSHi$UGo)H;2hjWsgWtW8|mpk5C@H&&!)=_Shq^)PEkK2_TS{ zeMI%6Gy$_)2ghsKPEhm#`|?qmhX%HYX4Ss~^%1|lVVB#;z;d?1Vb1>!#u?ZK#V^=K zS@en05Bxv&xx5Yk%MzZ+ci`OTmk#5_S|^cBB+quH%bp!)gBJce5_njL(CZlOy) zu_Qmc#LwmsFQLvv)q=N4xmde;25x=zN#v?asBopZ!=FNxcv(I7GM_t=?Rg59-evy+ zmsJZ`pT+{0RSQJ2rl;YU-^dbQeV>9u=85Wj{0+Od69vq9KI$)AmDy;nKMSh*8H!+E zJ%j38$4onD0y_nQzEf6W#vQ2SzLOW2x&xy>+=0;nTc5??SMf|&_=02D^&Kc#TY&l@LjHvN15s-vQ?MUQDjvM``TfK1lo9K3Je^A6eMg{owB3j3D2B z0s=etBjcccwXpvE7?QFNr_wUReu@`$=Amr=O*BRWH;^10WvfL?I(RsLEn|znhI({t z?|#Z7|V3cdb%P$~SjOI#a`!gcJ z$PWg6AArfu9Dug(JplED$m-!QJM8KK{41T`){fiyUh z&3cJa(3c>eAyTgU-gpUhUnJZ26|8aJs}Ly?)vvsFq-yW(BREe4yYC2Pi&409akru1 zJ3=9NN>jbe9XWy}qRfSSKs1~6G87cWYyKG4`!Zfqqu92WX#uwi~`#z4t)B$qh-8j=m-i+@4j z!iXdA0fB2yi%I43CY8U(CL>ta?{Vne$8hN4W8`M-$MGFPa~#J{7(Bk2RkuMs+?Ha3 zT(^y2Uml0kB=TdAVBBATm9r=Q@7WXmXHVp3M=YN}U?j>4NE}o^qF(_kPC~YLw)G@l zv)l4J{_dpPu@7Iz zddcebl2z-~y+LL%nd_8aT6erbv3Sa7=T0K3lKDlRiRT&ryJ|8kcoVCRm0t#ADaXnm zI;0Zm#G9BtR(`$XQi@~!>YsqEU<5NX*-B(Ugrpkok1`PBK`YQD3{1YVKmR6K-(xDO~b)Zi*3GKO}=_N9vIRL4O)GubtN{QiU1} zjPC&B(IE9C^C?`gDQ_dm*cr|?iv8y_Hnrnh*x;ri&)u-8ou$2tOnA!~e38jew#@Kv z`L{FJGDEc`K0xv<@xhO8i7A6yX2@H9i`!1jxM9oZZ`d+}Z|O!EHF&@*|88Hsi`}wR zyJg9{Wy!l?%HVEUe78(7OT7^bIftWX$wz892N%fpTQOT@#ShNGiXap#X5V1NY`+z= zeOA<9^keU1w`{ff*ni*0NwZZ}i(q9RAcf`nH_cUTdi(=y3PRa5_l8Y#{hQ_vx=yao zbu343&|mHiLVW)rgvh-?h@6ioOw31RDuo67b2r`*P=tiw12C>3pYP<$ne@s>NIjES z%*QBp3lx(S_)YS}$7B-=5J1vm1+r}n35xb&UU9{; zrnhjp6!U~AeR2y1mOj)raR63Vj#C7C^$>=K#iQsR0u|rM|)~8Ok=OR^!b+~sVP2j7p3qloth4Q=3 z=MMmrWp&hXZ^_3Wa-{Dy@~u&CHgRplu?d%Oq2MDo|B@(OHTC=rjBBx8HtS25Xc+!H zboLU>VzU-v#^y`#(*|BRj9~45hMWy>5eS$B^65X*EO7xMTUucOKbjq-f>g^&UbTR& zy$o%-xJdF1ron?$1em|3P|@X&A(yPl_OGEm7hCZ)wAUwxWU|`!GmJWR@s`b z{e>2bZn=byV`bkWmfR>)B$r?HE#;yb!WEeevPRbLf8-&pvTM2V?kRmvlU&Qq>b`?A zI^;Jf>0BLh&G_SY@T?BLeGIdH4+C__mA0hA4(9xxDrgD+2pB7yV+l8hU0mX~#1fWr zg(}5P)V`8~bjlwLfBFuWc&BXaD_8Ie(dnPi$;SPF!g(1#WitEr2Yg_E^ap%z?v{z^ zKZ5uVCvK7mG^IaMCj0D1{7v}Ck0_w>e*%j92_sg@PX6Up9APDE`-y6q<0?A;{S%e2 z*Ew2ul}hl}2Rn~#{CS`Kbd_poEk8mm8}Tz%emj??d0)P@XbgNuXfgx~3xl=^EkPd(Z9`&& zMMG{E77zKm&}B>(mKp1W?%?l*?g+miY>IeQxFg~l;m%0U+rp;E ze+YM5_X_t!xrMu<288>f9u+o63&NJ@V}dtkqc9Nrp|ExMSb>dLEIer2B|H@Wz3_0t zSmBYxCBmbl{wr)v8YXNTZ519%4iL5{|6O=|%-6!UF~12Z^5?>tf_ULpA;_=wSQNEE)S*d}~m86jM$+${V!(;)mb^H$;N z%>M}2X7va^&-y|5YgL=@&#L{xzp8%q2)|U92>+@6ukh>a1Hx}}P6^lN9wC}Hn#6hA zNsB*w>1x9%pmrVw)^4Ss+V{!m#2-=WLMfzf4w>r{$W)(1L+c-<(E86QY(Czq8>Z3F zhEj@XoJ5feaEUGW2SvGb6yy4ZViz8wxRx4Bc{`S~Qgs+b>gm z`+q5EaXuw4!3U_$CQ9kLPO05LkbU_D%0SJYwdycs_dZRzH+v}`{}g1>+D%l@7eJ1_ zaw_VZO~vakP{}QBD!ny;$~WXu#fE7#b3-*%ZCFOLH{45eH$Ff$w;v_v9br_rDV6GL z?~J9oJF}?aE+Z|t>k_%{{*0RM&7{`*V#vMuICX3}MoaGJ|1Qf*%e+5R_dpfhG_a3) o9tfco4|LMX2hPyyt+S|i>jy{$^N