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Aligner Updated

This commit is contained in:
waleed-lm 2020-10-13 19:33:12 +05:00
parent e22d45277f
commit a0e4ed76e6
4 changed files with 115 additions and 115 deletions
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176
el2_ifu_bp_ctl.fir
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@ -33,20 +33,20 @@ circuit el2_ifu_bp_ctl :
dec_tlu_error_wb <= _T_1 @[el2_ifu_bp_ctl.scala 91:20] dec_tlu_error_wb <= _T_1 @[el2_ifu_bp_ctl.scala 91:20]
btb_error_addr_wb <= io.exu_i0_br_index_r @[el2_ifu_bp_ctl.scala 92:21] btb_error_addr_wb <= io.exu_i0_br_index_r @[el2_ifu_bp_ctl.scala 92:21]
dec_tlu_way_wb <= io.dec_tlu_br0_r_pkt.way @[el2_ifu_bp_ctl.scala 93:18] dec_tlu_way_wb <= io.dec_tlu_br0_r_pkt.way @[el2_ifu_bp_ctl.scala 93:18]
node _T_2 = bits(io.ifc_fetch_addr_f, 8, 1) @[el2_lib.scala 186:12] node _T_2 = bits(io.ifc_fetch_addr_f, 8, 1) @[el2_lib.scala 191:12]
node _T_3 = bits(io.ifc_fetch_addr_f, 16, 9) @[el2_lib.scala 186:50] node _T_3 = bits(io.ifc_fetch_addr_f, 16, 9) @[el2_lib.scala 191:50]
node _T_4 = xor(_T_2, _T_3) @[el2_lib.scala 186:46] node _T_4 = xor(_T_2, _T_3) @[el2_lib.scala 191:46]
node _T_5 = bits(io.ifc_fetch_addr_f, 24, 17) @[el2_lib.scala 186:88] node _T_5 = bits(io.ifc_fetch_addr_f, 24, 17) @[el2_lib.scala 191:88]
node btb_rd_addr_f = xor(_T_4, _T_5) @[el2_lib.scala 186:84] node btb_rd_addr_f = xor(_T_4, _T_5) @[el2_lib.scala 191:84]
node _T_6 = bits(io.ifc_fetch_addr_f, 30, 1) @[el2_ifu_bp_ctl.scala 99:44] node _T_6 = bits(io.ifc_fetch_addr_f, 30, 1) @[el2_ifu_bp_ctl.scala 99:44]
node _T_7 = add(_T_6, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 99:51] node _T_7 = add(_T_6, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 99:51]
node fetch_addr_p1_f = tail(_T_7, 1) @[el2_ifu_bp_ctl.scala 99:51] node fetch_addr_p1_f = tail(_T_7, 1) @[el2_ifu_bp_ctl.scala 99:51]
node _T_8 = cat(fetch_addr_p1_f, UInt<1>("h00")) @[Cat.scala 29:58] node _T_8 = cat(fetch_addr_p1_f, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_9 = bits(_T_8, 8, 1) @[el2_lib.scala 186:12] node _T_9 = bits(_T_8, 8, 1) @[el2_lib.scala 191:12]
node _T_10 = bits(_T_8, 16, 9) @[el2_lib.scala 186:50] node _T_10 = bits(_T_8, 16, 9) @[el2_lib.scala 191:50]
node _T_11 = xor(_T_9, _T_10) @[el2_lib.scala 186:46] node _T_11 = xor(_T_9, _T_10) @[el2_lib.scala 191:46]
node _T_12 = bits(_T_8, 24, 17) @[el2_lib.scala 186:88] node _T_12 = bits(_T_8, 24, 17) @[el2_lib.scala 191:88]
node btb_rd_addr_p1_f = xor(_T_11, _T_12) @[el2_lib.scala 186:84] node btb_rd_addr_p1_f = xor(_T_11, _T_12) @[el2_lib.scala 191:84]
node _T_13 = bits(bht_dir_f, 0, 0) @[el2_ifu_bp_ctl.scala 105:33] node _T_13 = bits(bht_dir_f, 0, 0) @[el2_ifu_bp_ctl.scala 105:33]
node _T_14 = not(_T_13) @[el2_ifu_bp_ctl.scala 105:23] node _T_14 = not(_T_13) @[el2_ifu_bp_ctl.scala 105:23]
node _T_15 = bits(bht_dir_f, 0, 0) @[el2_ifu_bp_ctl.scala 105:46] node _T_15 = bits(bht_dir_f, 0, 0) @[el2_ifu_bp_ctl.scala 105:46]
@ -61,25 +61,25 @@ circuit el2_ifu_bp_ctl :
node branch_error_collision_p1_f = and(dec_tlu_error_wb, _T_20) @[el2_ifu_bp_ctl.scala 112:54] node branch_error_collision_p1_f = and(dec_tlu_error_wb, _T_20) @[el2_ifu_bp_ctl.scala 112:54]
node branch_error_bank_conflict_f = and(branch_error_collision_f, dec_tlu_error_wb) @[el2_ifu_bp_ctl.scala 115:63] node branch_error_bank_conflict_f = and(branch_error_collision_f, dec_tlu_error_wb) @[el2_ifu_bp_ctl.scala 115:63]
node branch_error_bank_conflict_p1_f = and(branch_error_collision_p1_f, dec_tlu_error_wb) @[el2_ifu_bp_ctl.scala 116:69] node branch_error_bank_conflict_p1_f = and(branch_error_collision_p1_f, dec_tlu_error_wb) @[el2_ifu_bp_ctl.scala 116:69]
node _T_21 = bits(io.ifc_fetch_addr_f, 13, 9) @[el2_lib.scala 177:32] node _T_21 = bits(io.ifc_fetch_addr_f, 13, 9) @[el2_lib.scala 182:32]
node _T_22 = bits(io.ifc_fetch_addr_f, 18, 14) @[el2_lib.scala 177:32] node _T_22 = bits(io.ifc_fetch_addr_f, 18, 14) @[el2_lib.scala 182:32]
node _T_23 = bits(io.ifc_fetch_addr_f, 23, 19) @[el2_lib.scala 177:32] node _T_23 = bits(io.ifc_fetch_addr_f, 23, 19) @[el2_lib.scala 182:32]
wire _T_24 : UInt<5>[3] @[el2_lib.scala 177:24] wire _T_24 : UInt<5>[3] @[el2_lib.scala 182:24]
_T_24[0] <= _T_21 @[el2_lib.scala 177:24] _T_24[0] <= _T_21 @[el2_lib.scala 182:24]
_T_24[1] <= _T_22 @[el2_lib.scala 177:24] _T_24[1] <= _T_22 @[el2_lib.scala 182:24]
_T_24[2] <= _T_23 @[el2_lib.scala 177:24] _T_24[2] <= _T_23 @[el2_lib.scala 182:24]
node _T_25 = xor(_T_24[0], _T_24[1]) @[el2_lib.scala 177:111] node _T_25 = xor(_T_24[0], _T_24[1]) @[el2_lib.scala 182:111]
node fetch_rd_tag_f = xor(_T_25, _T_24[2]) @[el2_lib.scala 177:111] node fetch_rd_tag_f = xor(_T_25, _T_24[2]) @[el2_lib.scala 182:111]
node _T_26 = cat(fetch_addr_p1_f, UInt<1>("h00")) @[Cat.scala 29:58] node _T_26 = cat(fetch_addr_p1_f, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_27 = bits(_T_26, 13, 9) @[el2_lib.scala 177:32] node _T_27 = bits(_T_26, 13, 9) @[el2_lib.scala 182:32]
node _T_28 = bits(_T_26, 18, 14) @[el2_lib.scala 177:32] node _T_28 = bits(_T_26, 18, 14) @[el2_lib.scala 182:32]
node _T_29 = bits(_T_26, 23, 19) @[el2_lib.scala 177:32] node _T_29 = bits(_T_26, 23, 19) @[el2_lib.scala 182:32]
wire _T_30 : UInt<5>[3] @[el2_lib.scala 177:24] wire _T_30 : UInt<5>[3] @[el2_lib.scala 182:24]
_T_30[0] <= _T_27 @[el2_lib.scala 177:24] _T_30[0] <= _T_27 @[el2_lib.scala 182:24]
_T_30[1] <= _T_28 @[el2_lib.scala 177:24] _T_30[1] <= _T_28 @[el2_lib.scala 182:24]
_T_30[2] <= _T_29 @[el2_lib.scala 177:24] _T_30[2] <= _T_29 @[el2_lib.scala 182:24]
node _T_31 = xor(_T_30[0], _T_30[1]) @[el2_lib.scala 177:111] node _T_31 = xor(_T_30[0], _T_30[1]) @[el2_lib.scala 182:111]
node fetch_rd_tag_p1_f = xor(_T_31, _T_30[2]) @[el2_lib.scala 177:111] node fetch_rd_tag_p1_f = xor(_T_31, _T_30[2]) @[el2_lib.scala 182:111]
node _T_32 = eq(io.exu_mp_btag, fetch_rd_tag_f) @[el2_ifu_bp_ctl.scala 121:46] node _T_32 = eq(io.exu_mp_btag, fetch_rd_tag_f) @[el2_ifu_bp_ctl.scala 121:46]
node _T_33 = and(_T_32, exu_mp_valid) @[el2_ifu_bp_ctl.scala 121:66] node _T_33 = and(_T_32, exu_mp_valid) @[el2_ifu_bp_ctl.scala 121:66]
node _T_34 = and(_T_33, io.ifc_fetch_req_f) @[el2_ifu_bp_ctl.scala 121:81] node _T_34 = and(_T_33, io.ifc_fetch_req_f) @[el2_ifu_bp_ctl.scala 121:81]
@ -551,29 +551,29 @@ circuit el2_ifu_bp_ctl :
node _T_388 = cat(_T_387, bp_total_branch_offset_f) @[Cat.scala 29:58] node _T_388 = cat(_T_387, bp_total_branch_offset_f) @[Cat.scala 29:58]
node _T_389 = cat(_T_388, UInt<1>("h00")) @[Cat.scala 29:58] node _T_389 = cat(_T_388, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_390 = cat(btb_rd_tgt_f, UInt<1>("h00")) @[Cat.scala 29:58] node _T_390 = cat(btb_rd_tgt_f, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_391 = bits(_T_389, 12, 1) @[el2_lib.scala 201:24] node _T_391 = bits(_T_389, 12, 1) @[el2_lib.scala 206:24]
node _T_392 = bits(_T_390, 12, 1) @[el2_lib.scala 201:40] node _T_392 = bits(_T_390, 12, 1) @[el2_lib.scala 206:40]
node _T_393 = add(_T_391, _T_392) @[el2_lib.scala 201:31] node _T_393 = add(_T_391, _T_392) @[el2_lib.scala 206:31]
node _T_394 = bits(_T_389, 31, 13) @[el2_lib.scala 202:20] node _T_394 = bits(_T_389, 31, 13) @[el2_lib.scala 207:20]
node _T_395 = add(_T_394, UInt<1>("h01")) @[el2_lib.scala 202:27] node _T_395 = add(_T_394, UInt<1>("h01")) @[el2_lib.scala 207:27]
node _T_396 = tail(_T_395, 1) @[el2_lib.scala 202:27] node _T_396 = tail(_T_395, 1) @[el2_lib.scala 207:27]
node _T_397 = bits(_T_389, 31, 13) @[el2_lib.scala 203:20] node _T_397 = bits(_T_389, 31, 13) @[el2_lib.scala 208:20]
node _T_398 = sub(_T_397, UInt<1>("h01")) @[el2_lib.scala 203:27] node _T_398 = sub(_T_397, UInt<1>("h01")) @[el2_lib.scala 208:27]
node _T_399 = tail(_T_398, 1) @[el2_lib.scala 203:27] node _T_399 = tail(_T_398, 1) @[el2_lib.scala 208:27]
node _T_400 = bits(_T_390, 12, 12) @[el2_lib.scala 204:22] node _T_400 = bits(_T_390, 12, 12) @[el2_lib.scala 209:22]
node _T_401 = bits(_T_393, 12, 12) @[el2_lib.scala 205:38] node _T_401 = bits(_T_393, 12, 12) @[el2_lib.scala 210:38]
node _T_402 = eq(_T_401, UInt<1>("h00")) @[el2_lib.scala 205:27] node _T_402 = eq(_T_401, UInt<1>("h00")) @[el2_lib.scala 210:27]
node _T_403 = xor(_T_400, _T_402) @[el2_lib.scala 205:25] node _T_403 = xor(_T_400, _T_402) @[el2_lib.scala 210:25]
node _T_404 = bits(_T_403, 0, 0) @[el2_lib.scala 205:63] node _T_404 = bits(_T_403, 0, 0) @[el2_lib.scala 210:63]
node _T_405 = bits(_T_389, 31, 13) @[el2_lib.scala 205:75] node _T_405 = bits(_T_389, 31, 13) @[el2_lib.scala 210:75]
node _T_406 = eq(_T_400, UInt<1>("h00")) @[el2_lib.scala 206:8] node _T_406 = eq(_T_400, UInt<1>("h00")) @[el2_lib.scala 211:8]
node _T_407 = bits(_T_393, 12, 12) @[el2_lib.scala 206:26] node _T_407 = bits(_T_393, 12, 12) @[el2_lib.scala 211:26]
node _T_408 = and(_T_406, _T_407) @[el2_lib.scala 206:14] node _T_408 = and(_T_406, _T_407) @[el2_lib.scala 211:14]
node _T_409 = bits(_T_408, 0, 0) @[el2_lib.scala 206:51] node _T_409 = bits(_T_408, 0, 0) @[el2_lib.scala 211:51]
node _T_410 = bits(_T_393, 12, 12) @[el2_lib.scala 207:26] node _T_410 = bits(_T_393, 12, 12) @[el2_lib.scala 212:26]
node _T_411 = eq(_T_410, UInt<1>("h00")) @[el2_lib.scala 207:15] node _T_411 = eq(_T_410, UInt<1>("h00")) @[el2_lib.scala 212:15]
node _T_412 = and(_T_400, _T_411) @[el2_lib.scala 207:13] node _T_412 = and(_T_400, _T_411) @[el2_lib.scala 212:13]
node _T_413 = bits(_T_412, 0, 0) @[el2_lib.scala 207:51] node _T_413 = bits(_T_412, 0, 0) @[el2_lib.scala 212:51]
node _T_414 = mux(_T_404, _T_405, UInt<1>("h00")) @[Mux.scala 27:72] node _T_414 = mux(_T_404, _T_405, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_415 = mux(_T_409, _T_396, UInt<1>("h00")) @[Mux.scala 27:72] node _T_415 = mux(_T_409, _T_396, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_416 = mux(_T_413, _T_399, UInt<1>("h00")) @[Mux.scala 27:72] node _T_416 = mux(_T_413, _T_399, UInt<1>("h00")) @[Mux.scala 27:72]
@ -581,7 +581,7 @@ circuit el2_ifu_bp_ctl :
node _T_418 = or(_T_417, _T_416) @[Mux.scala 27:72] node _T_418 = or(_T_417, _T_416) @[Mux.scala 27:72]
wire _T_419 : UInt<19> @[Mux.scala 27:72] wire _T_419 : UInt<19> @[Mux.scala 27:72]
_T_419 <= _T_418 @[Mux.scala 27:72] _T_419 <= _T_418 @[Mux.scala 27:72]
node _T_420 = bits(_T_393, 11, 0) @[el2_lib.scala 207:83] node _T_420 = bits(_T_393, 11, 0) @[el2_lib.scala 212:83]
node _T_421 = cat(_T_419, _T_420) @[Cat.scala 29:58] node _T_421 = cat(_T_419, _T_420) @[Cat.scala 29:58]
node bp_btb_target_adder_f = cat(_T_421, UInt<1>("h00")) @[Cat.scala 29:58] node bp_btb_target_adder_f = cat(_T_421, UInt<1>("h00")) @[Cat.scala 29:58]
wire rets_out : UInt<32>[8] @[el2_ifu_bp_ctl.scala 311:22] wire rets_out : UInt<32>[8] @[el2_ifu_bp_ctl.scala 311:22]
@ -609,29 +609,29 @@ circuit el2_ifu_bp_ctl :
node _T_434 = not(btb_rd_pc4_f) @[el2_ifu_bp_ctl.scala 318:113] node _T_434 = not(btb_rd_pc4_f) @[el2_ifu_bp_ctl.scala 318:113]
node _T_435 = cat(_T_433, _T_434) @[Cat.scala 29:58] node _T_435 = cat(_T_433, _T_434) @[Cat.scala 29:58]
node _T_436 = cat(_T_435, UInt<1>("h00")) @[Cat.scala 29:58] node _T_436 = cat(_T_435, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_437 = bits(_T_432, 12, 1) @[el2_lib.scala 201:24] node _T_437 = bits(_T_432, 12, 1) @[el2_lib.scala 206:24]
node _T_438 = bits(_T_436, 12, 1) @[el2_lib.scala 201:40] node _T_438 = bits(_T_436, 12, 1) @[el2_lib.scala 206:40]
node _T_439 = add(_T_437, _T_438) @[el2_lib.scala 201:31] node _T_439 = add(_T_437, _T_438) @[el2_lib.scala 206:31]
node _T_440 = bits(_T_432, 31, 13) @[el2_lib.scala 202:20] node _T_440 = bits(_T_432, 31, 13) @[el2_lib.scala 207:20]
node _T_441 = add(_T_440, UInt<1>("h01")) @[el2_lib.scala 202:27] node _T_441 = add(_T_440, UInt<1>("h01")) @[el2_lib.scala 207:27]
node _T_442 = tail(_T_441, 1) @[el2_lib.scala 202:27] node _T_442 = tail(_T_441, 1) @[el2_lib.scala 207:27]
node _T_443 = bits(_T_432, 31, 13) @[el2_lib.scala 203:20] node _T_443 = bits(_T_432, 31, 13) @[el2_lib.scala 208:20]
node _T_444 = sub(_T_443, UInt<1>("h01")) @[el2_lib.scala 203:27] node _T_444 = sub(_T_443, UInt<1>("h01")) @[el2_lib.scala 208:27]
node _T_445 = tail(_T_444, 1) @[el2_lib.scala 203:27] node _T_445 = tail(_T_444, 1) @[el2_lib.scala 208:27]
node _T_446 = bits(_T_436, 12, 12) @[el2_lib.scala 204:22] node _T_446 = bits(_T_436, 12, 12) @[el2_lib.scala 209:22]
node _T_447 = bits(_T_439, 12, 12) @[el2_lib.scala 205:38] node _T_447 = bits(_T_439, 12, 12) @[el2_lib.scala 210:38]
node _T_448 = eq(_T_447, UInt<1>("h00")) @[el2_lib.scala 205:27] node _T_448 = eq(_T_447, UInt<1>("h00")) @[el2_lib.scala 210:27]
node _T_449 = xor(_T_446, _T_448) @[el2_lib.scala 205:25] node _T_449 = xor(_T_446, _T_448) @[el2_lib.scala 210:25]
node _T_450 = bits(_T_449, 0, 0) @[el2_lib.scala 205:63] node _T_450 = bits(_T_449, 0, 0) @[el2_lib.scala 210:63]
node _T_451 = bits(_T_432, 31, 13) @[el2_lib.scala 205:75] node _T_451 = bits(_T_432, 31, 13) @[el2_lib.scala 210:75]
node _T_452 = eq(_T_446, UInt<1>("h00")) @[el2_lib.scala 206:8] node _T_452 = eq(_T_446, UInt<1>("h00")) @[el2_lib.scala 211:8]
node _T_453 = bits(_T_439, 12, 12) @[el2_lib.scala 206:26] node _T_453 = bits(_T_439, 12, 12) @[el2_lib.scala 211:26]
node _T_454 = and(_T_452, _T_453) @[el2_lib.scala 206:14] node _T_454 = and(_T_452, _T_453) @[el2_lib.scala 211:14]
node _T_455 = bits(_T_454, 0, 0) @[el2_lib.scala 206:51] node _T_455 = bits(_T_454, 0, 0) @[el2_lib.scala 211:51]
node _T_456 = bits(_T_439, 12, 12) @[el2_lib.scala 207:26] node _T_456 = bits(_T_439, 12, 12) @[el2_lib.scala 212:26]
node _T_457 = eq(_T_456, UInt<1>("h00")) @[el2_lib.scala 207:15] node _T_457 = eq(_T_456, UInt<1>("h00")) @[el2_lib.scala 212:15]
node _T_458 = and(_T_446, _T_457) @[el2_lib.scala 207:13] node _T_458 = and(_T_446, _T_457) @[el2_lib.scala 212:13]
node _T_459 = bits(_T_458, 0, 0) @[el2_lib.scala 207:51] node _T_459 = bits(_T_458, 0, 0) @[el2_lib.scala 212:51]
node _T_460 = mux(_T_450, _T_451, UInt<1>("h00")) @[Mux.scala 27:72] node _T_460 = mux(_T_450, _T_451, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_461 = mux(_T_455, _T_442, UInt<1>("h00")) @[Mux.scala 27:72] node _T_461 = mux(_T_455, _T_442, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_462 = mux(_T_459, _T_445, UInt<1>("h00")) @[Mux.scala 27:72] node _T_462 = mux(_T_459, _T_445, UInt<1>("h00")) @[Mux.scala 27:72]
@ -639,7 +639,7 @@ circuit el2_ifu_bp_ctl :
node _T_464 = or(_T_463, _T_462) @[Mux.scala 27:72] node _T_464 = or(_T_463, _T_462) @[Mux.scala 27:72]
wire _T_465 : UInt<19> @[Mux.scala 27:72] wire _T_465 : UInt<19> @[Mux.scala 27:72]
_T_465 <= _T_464 @[Mux.scala 27:72] _T_465 <= _T_464 @[Mux.scala 27:72]
node _T_466 = bits(_T_439, 11, 0) @[el2_lib.scala 207:83] node _T_466 = bits(_T_439, 11, 0) @[el2_lib.scala 212:83]
node _T_467 = cat(_T_465, _T_466) @[Cat.scala 29:58] node _T_467 = cat(_T_465, _T_466) @[Cat.scala 29:58]
node bp_rs_call_target_f = cat(_T_467, UInt<1>("h00")) @[Cat.scala 29:58] node bp_rs_call_target_f = cat(_T_467, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_468 = eq(btb_rd_ret_f, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 320:33] node _T_468 = eq(btb_rd_ret_f, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 320:33]
@ -800,21 +800,21 @@ circuit el2_ifu_bp_ctl :
node _T_559 = cat(io.dec_tlu_br0_r_pkt.middle, _T_558) @[Cat.scala 29:58] node _T_559 = cat(io.dec_tlu_br0_r_pkt.middle, _T_558) @[Cat.scala 29:58]
node bht_wr_en2 = and(_T_557, _T_559) @[el2_ifu_bp_ctl.scala 347:46] node bht_wr_en2 = and(_T_557, _T_559) @[el2_ifu_bp_ctl.scala 347:46]
node _T_560 = cat(io.exu_mp_index, UInt<2>("h00")) @[Cat.scala 29:58] node _T_560 = cat(io.exu_mp_index, UInt<2>("h00")) @[Cat.scala 29:58]
node _T_561 = bits(_T_560, 9, 2) @[el2_lib.scala 191:16] node _T_561 = bits(_T_560, 9, 2) @[el2_lib.scala 196:16]
node _T_562 = bits(io.exu_mp_eghr, 7, 0) @[el2_lib.scala 191:40] node _T_562 = bits(io.exu_mp_eghr, 7, 0) @[el2_lib.scala 196:40]
node mp_hashed = xor(_T_561, _T_562) @[el2_lib.scala 191:35] node mp_hashed = xor(_T_561, _T_562) @[el2_lib.scala 196:35]
node _T_563 = cat(io.exu_i0_br_index_r, UInt<2>("h00")) @[Cat.scala 29:58] node _T_563 = cat(io.exu_i0_br_index_r, UInt<2>("h00")) @[Cat.scala 29:58]
node _T_564 = bits(_T_563, 9, 2) @[el2_lib.scala 191:16] node _T_564 = bits(_T_563, 9, 2) @[el2_lib.scala 196:16]
node _T_565 = bits(io.exu_i0_br_fghr_r, 7, 0) @[el2_lib.scala 191:40] node _T_565 = bits(io.exu_i0_br_fghr_r, 7, 0) @[el2_lib.scala 196:40]
node br0_hashed_wb = xor(_T_564, _T_565) @[el2_lib.scala 191:35] node br0_hashed_wb = xor(_T_564, _T_565) @[el2_lib.scala 196:35]
node _T_566 = cat(btb_rd_addr_f, UInt<2>("h00")) @[Cat.scala 29:58] node _T_566 = cat(btb_rd_addr_f, UInt<2>("h00")) @[Cat.scala 29:58]
node _T_567 = bits(_T_566, 9, 2) @[el2_lib.scala 191:16] node _T_567 = bits(_T_566, 9, 2) @[el2_lib.scala 196:16]
node _T_568 = bits(fghr, 7, 0) @[el2_lib.scala 191:40] node _T_568 = bits(fghr, 7, 0) @[el2_lib.scala 196:40]
node bht_rd_addr_hashed_f = xor(_T_567, _T_568) @[el2_lib.scala 191:35] node bht_rd_addr_hashed_f = xor(_T_567, _T_568) @[el2_lib.scala 196:35]
node _T_569 = cat(btb_rd_addr_p1_f, UInt<2>("h00")) @[Cat.scala 29:58] node _T_569 = cat(btb_rd_addr_p1_f, UInt<2>("h00")) @[Cat.scala 29:58]
node _T_570 = bits(_T_569, 9, 2) @[el2_lib.scala 191:16] node _T_570 = bits(_T_569, 9, 2) @[el2_lib.scala 196:16]
node _T_571 = bits(fghr, 7, 0) @[el2_lib.scala 191:40] node _T_571 = bits(fghr, 7, 0) @[el2_lib.scala 196:40]
node bht_rd_addr_hashed_p1_f = xor(_T_570, _T_571) @[el2_lib.scala 191:35] node bht_rd_addr_hashed_p1_f = xor(_T_570, _T_571) @[el2_lib.scala 196:35]
node _T_572 = eq(btb_wr_addr, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 364:101] node _T_572 = eq(btb_wr_addr, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 364:101]
node _T_573 = and(_T_572, btb_wr_en_way0) @[el2_ifu_bp_ctl.scala 364:109] node _T_573 = and(_T_572, btb_wr_en_way0) @[el2_ifu_bp_ctl.scala 364:109]
node _T_574 = bits(_T_573, 0, 0) @[el2_ifu_bp_ctl.scala 364:127] node _T_574 = bits(_T_573, 0, 0) @[el2_ifu_bp_ctl.scala 364:127]

52
el2_ifu_bp_ctl.v
View File

@ -1095,12 +1095,12 @@ module el2_ifu_bp_ctl(
wire _T = ~leak_one_f; // @[el2_ifu_bp_ctl.scala 69:46] wire _T = ~leak_one_f; // @[el2_ifu_bp_ctl.scala 69:46]
wire exu_mp_valid = io_exu_mp_pkt_misp & _T; // @[el2_ifu_bp_ctl.scala 69:44] wire exu_mp_valid = io_exu_mp_pkt_misp & _T; // @[el2_ifu_bp_ctl.scala 69:44]
wire dec_tlu_error_wb = io_dec_tlu_br0_r_pkt_br_start_error | io_dec_tlu_br0_r_pkt_br_error; // @[el2_ifu_bp_ctl.scala 91:50] wire dec_tlu_error_wb = io_dec_tlu_br0_r_pkt_br_start_error | io_dec_tlu_br0_r_pkt_br_error; // @[el2_ifu_bp_ctl.scala 91:50]
wire [7:0] _T_4 = io_ifc_fetch_addr_f[8:1] ^ io_ifc_fetch_addr_f[16:9]; // @[el2_lib.scala 186:46] wire [7:0] _T_4 = io_ifc_fetch_addr_f[8:1] ^ io_ifc_fetch_addr_f[16:9]; // @[el2_lib.scala 191:46]
wire [7:0] btb_rd_addr_f = _T_4 ^ io_ifc_fetch_addr_f[24:17]; // @[el2_lib.scala 186:84] wire [7:0] btb_rd_addr_f = _T_4 ^ io_ifc_fetch_addr_f[24:17]; // @[el2_lib.scala 191:84]
wire [29:0] fetch_addr_p1_f = io_ifc_fetch_addr_f[30:1] + 30'h1; // @[el2_ifu_bp_ctl.scala 99:51] wire [29:0] fetch_addr_p1_f = io_ifc_fetch_addr_f[30:1] + 30'h1; // @[el2_ifu_bp_ctl.scala 99:51]
wire [30:0] _T_8 = {fetch_addr_p1_f,1'h0}; // @[Cat.scala 29:58] wire [30:0] _T_8 = {fetch_addr_p1_f,1'h0}; // @[Cat.scala 29:58]
wire [7:0] _T_11 = _T_8[8:1] ^ _T_8[16:9]; // @[el2_lib.scala 186:46] wire [7:0] _T_11 = _T_8[8:1] ^ _T_8[16:9]; // @[el2_lib.scala 191:46]
wire [7:0] btb_rd_addr_p1_f = _T_11 ^ _T_8[24:17]; // @[el2_lib.scala 186:84] wire [7:0] btb_rd_addr_p1_f = _T_11 ^ _T_8[24:17]; // @[el2_lib.scala 191:84]
wire _T_143 = ~io_ifc_fetch_addr_f[0]; // @[el2_ifu_bp_ctl.scala 176:40] wire _T_143 = ~io_ifc_fetch_addr_f[0]; // @[el2_ifu_bp_ctl.scala 176:40]
wire _T_2108 = btb_rd_addr_f == 8'h0; // @[el2_ifu_bp_ctl.scala 367:77] wire _T_2108 = btb_rd_addr_f == 8'h0; // @[el2_ifu_bp_ctl.scala 367:77]
reg [21:0] btb_bank0_rd_data_way0_out_0; // @[Reg.scala 27:20] reg [21:0] btb_bank0_rd_data_way0_out_0; // @[Reg.scala 27:20]
@ -2125,8 +2125,8 @@ module el2_ifu_bp_ctl(
reg [21:0] btb_bank0_rd_data_way0_out_255; // @[Reg.scala 27:20] reg [21:0] btb_bank0_rd_data_way0_out_255; // @[Reg.scala 27:20]
wire [21:0] _T_2875 = _T_2618 ? btb_bank0_rd_data_way0_out_255 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2875 = _T_2618 ? btb_bank0_rd_data_way0_out_255 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] btb_bank0_rd_data_way0_f = _T_3129 | _T_2875; // @[Mux.scala 27:72] wire [21:0] btb_bank0_rd_data_way0_f = _T_3129 | _T_2875; // @[Mux.scala 27:72]
wire [4:0] _T_25 = io_ifc_fetch_addr_f[13:9] ^ io_ifc_fetch_addr_f[18:14]; // @[el2_lib.scala 177:111] wire [4:0] _T_25 = io_ifc_fetch_addr_f[13:9] ^ io_ifc_fetch_addr_f[18:14]; // @[el2_lib.scala 182:111]
wire [4:0] fetch_rd_tag_f = _T_25 ^ io_ifc_fetch_addr_f[23:19]; // @[el2_lib.scala 177:111] wire [4:0] fetch_rd_tag_f = _T_25 ^ io_ifc_fetch_addr_f[23:19]; // @[el2_lib.scala 182:111]
wire _T_45 = btb_bank0_rd_data_way0_f[21:17] == fetch_rd_tag_f; // @[el2_ifu_bp_ctl.scala 133:97] wire _T_45 = btb_bank0_rd_data_way0_f[21:17] == fetch_rd_tag_f; // @[el2_ifu_bp_ctl.scala 133:97]
wire _T_46 = btb_bank0_rd_data_way0_f[0] & _T_45; // @[el2_ifu_bp_ctl.scala 133:55] wire _T_46 = btb_bank0_rd_data_way0_f[0] & _T_45; // @[el2_ifu_bp_ctl.scala 133:55]
reg dec_tlu_way_wb_f; // @[el2_ifu_bp_ctl.scala 125:59] reg dec_tlu_way_wb_f; // @[el2_ifu_bp_ctl.scala 125:59]
@ -3693,8 +3693,8 @@ module el2_ifu_bp_ctl(
wire _T_4666 = btb_rd_addr_p1_f == 8'hff; // @[el2_ifu_bp_ctl.scala 370:83] wire _T_4666 = btb_rd_addr_p1_f == 8'hff; // @[el2_ifu_bp_ctl.scala 370:83]
wire [21:0] _T_4923 = _T_4666 ? btb_bank0_rd_data_way0_out_255 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4923 = _T_4666 ? btb_bank0_rd_data_way0_out_255 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] btb_bank0_rd_data_way0_p1_f = _T_5177 | _T_4923; // @[Mux.scala 27:72] wire [21:0] btb_bank0_rd_data_way0_p1_f = _T_5177 | _T_4923; // @[Mux.scala 27:72]
wire [4:0] _T_31 = _T_8[13:9] ^ _T_8[18:14]; // @[el2_lib.scala 177:111] wire [4:0] _T_31 = _T_8[13:9] ^ _T_8[18:14]; // @[el2_lib.scala 182:111]
wire [4:0] fetch_rd_tag_p1_f = _T_31 ^ _T_8[23:19]; // @[el2_lib.scala 177:111] wire [4:0] fetch_rd_tag_p1_f = _T_31 ^ _T_8[23:19]; // @[el2_lib.scala 182:111]
wire _T_63 = btb_bank0_rd_data_way0_p1_f[21:17] == fetch_rd_tag_p1_f; // @[el2_ifu_bp_ctl.scala 139:106] wire _T_63 = btb_bank0_rd_data_way0_p1_f[21:17] == fetch_rd_tag_p1_f; // @[el2_ifu_bp_ctl.scala 139:106]
wire _T_64 = btb_bank0_rd_data_way0_p1_f[0] & _T_63; // @[el2_ifu_bp_ctl.scala 139:61] wire _T_64 = btb_bank0_rd_data_way0_p1_f[0] & _T_63; // @[el2_ifu_bp_ctl.scala 139:61]
wire _T_67 = _T_64 & _T_48; // @[el2_ifu_bp_ctl.scala 139:129] wire _T_67 = _T_64 & _T_48; // @[el2_ifu_bp_ctl.scala 139:129]
@ -4242,7 +4242,7 @@ module el2_ifu_bp_ctl(
wire [1:0] bht_force_taken_f = {_T_241,_T_244}; // @[Cat.scala 29:58] wire [1:0] bht_force_taken_f = {_T_241,_T_244}; // @[Cat.scala 29:58]
wire [9:0] _T_566 = {btb_rd_addr_f,2'h0}; // @[Cat.scala 29:58] wire [9:0] _T_566 = {btb_rd_addr_f,2'h0}; // @[Cat.scala 29:58]
reg [7:0] fghr; // @[el2_ifu_bp_ctl.scala 282:44] reg [7:0] fghr; // @[el2_ifu_bp_ctl.scala 282:44]
wire [7:0] bht_rd_addr_hashed_f = _T_566[9:2] ^ fghr; // @[el2_lib.scala 191:35] wire [7:0] bht_rd_addr_hashed_f = _T_566[9:2] ^ fghr; // @[el2_lib.scala 196:35]
wire _T_22173 = bht_rd_addr_hashed_f == 8'h0; // @[el2_ifu_bp_ctl.scala 397:106] wire _T_22173 = bht_rd_addr_hashed_f == 8'h0; // @[el2_ifu_bp_ctl.scala 397:106]
reg [1:0] bht_bank_rd_data_out_1_0; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_1_0; // @[Reg.scala 27:20]
wire [1:0] _T_22940 = _T_22173 ? bht_bank_rd_data_out_1_0 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22940 = _T_22173 ? bht_bank_rd_data_out_1_0 : 2'h0; // @[Mux.scala 27:72]
@ -5268,7 +5268,7 @@ module el2_ifu_bp_ctl(
wire [1:0] bht_bank1_rd_data_f = _T_23449 | _T_23195; // @[Mux.scala 27:72] wire [1:0] bht_bank1_rd_data_f = _T_23449 | _T_23195; // @[Mux.scala 27:72]
wire [1:0] _T_258 = _T_143 ? bht_bank1_rd_data_f : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_258 = _T_143 ? bht_bank1_rd_data_f : 2'h0; // @[Mux.scala 27:72]
wire [9:0] _T_569 = {btb_rd_addr_p1_f,2'h0}; // @[Cat.scala 29:58] wire [9:0] _T_569 = {btb_rd_addr_p1_f,2'h0}; // @[Cat.scala 29:58]
wire [7:0] bht_rd_addr_hashed_p1_f = _T_569[9:2] ^ fghr; // @[el2_lib.scala 191:35] wire [7:0] bht_rd_addr_hashed_p1_f = _T_569[9:2] ^ fghr; // @[el2_lib.scala 196:35]
wire _T_23453 = bht_rd_addr_hashed_p1_f == 8'h0; // @[el2_ifu_bp_ctl.scala 398:112] wire _T_23453 = bht_rd_addr_hashed_p1_f == 8'h0; // @[el2_ifu_bp_ctl.scala 398:112]
wire [1:0] _T_24220 = _T_23453 ? bht_bank_rd_data_out_1_0 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_24220 = _T_23453 ? bht_bank_rd_data_out_1_0 : 2'h0; // @[Mux.scala 27:72]
wire _T_23456 = bht_rd_addr_hashed_p1_f == 8'h1; // @[el2_ifu_bp_ctl.scala 398:112] wire _T_23456 = bht_rd_addr_hashed_p1_f == 8'h1; // @[el2_ifu_bp_ctl.scala 398:112]
@ -6964,14 +6964,14 @@ module el2_ifu_bp_ctl(
wire [30:0] adder_pc_in_f = _T_385 | _GEN_1037; // @[Mux.scala 27:72] wire [30:0] adder_pc_in_f = _T_385 | _GEN_1037; // @[Mux.scala 27:72]
wire [31:0] _T_389 = {adder_pc_in_f[29:0],bp_total_branch_offset_f,1'h0}; // @[Cat.scala 29:58] wire [31:0] _T_389 = {adder_pc_in_f[29:0],bp_total_branch_offset_f,1'h0}; // @[Cat.scala 29:58]
wire [12:0] _T_390 = {btb_rd_tgt_f,1'h0}; // @[Cat.scala 29:58] wire [12:0] _T_390 = {btb_rd_tgt_f,1'h0}; // @[Cat.scala 29:58]
wire [12:0] _T_393 = _T_389[12:1] + _T_390[12:1]; // @[el2_lib.scala 201:31] wire [12:0] _T_393 = _T_389[12:1] + _T_390[12:1]; // @[el2_lib.scala 206:31]
wire [18:0] _T_396 = _T_389[31:13] + 19'h1; // @[el2_lib.scala 202:27] wire [18:0] _T_396 = _T_389[31:13] + 19'h1; // @[el2_lib.scala 207:27]
wire [18:0] _T_399 = _T_389[31:13] - 19'h1; // @[el2_lib.scala 203:27] wire [18:0] _T_399 = _T_389[31:13] - 19'h1; // @[el2_lib.scala 208:27]
wire _T_402 = ~_T_393[12]; // @[el2_lib.scala 205:27] wire _T_402 = ~_T_393[12]; // @[el2_lib.scala 210:27]
wire _T_403 = _T_390[12] ^ _T_402; // @[el2_lib.scala 205:25] wire _T_403 = _T_390[12] ^ _T_402; // @[el2_lib.scala 210:25]
wire _T_406 = ~_T_390[12]; // @[el2_lib.scala 206:8] wire _T_406 = ~_T_390[12]; // @[el2_lib.scala 211:8]
wire _T_408 = _T_406 & _T_393[12]; // @[el2_lib.scala 206:14] wire _T_408 = _T_406 & _T_393[12]; // @[el2_lib.scala 211:14]
wire _T_412 = _T_390[12] & _T_402; // @[el2_lib.scala 207:13] wire _T_412 = _T_390[12] & _T_402; // @[el2_lib.scala 212:13]
wire [18:0] _T_414 = _T_403 ? _T_389[31:13] : 19'h0; // @[Mux.scala 27:72] wire [18:0] _T_414 = _T_403 ? _T_389[31:13] : 19'h0; // @[Mux.scala 27:72]
wire [18:0] _T_415 = _T_408 ? _T_396 : 19'h0; // @[Mux.scala 27:72] wire [18:0] _T_415 = _T_408 ? _T_396 : 19'h0; // @[Mux.scala 27:72]
wire [18:0] _T_416 = _T_412 ? _T_399 : 19'h0; // @[Mux.scala 27:72] wire [18:0] _T_416 = _T_412 ? _T_399 : 19'h0; // @[Mux.scala 27:72]
@ -6983,12 +6983,12 @@ module el2_ifu_bp_ctl(
reg [31:0] rets_out_0; // @[Reg.scala 27:20] reg [31:0] rets_out_0; // @[Reg.scala 27:20]
wire _T_425 = _T_423 & rets_out_0[0]; // @[el2_ifu_bp_ctl.scala 314:64] wire _T_425 = _T_423 & rets_out_0[0]; // @[el2_ifu_bp_ctl.scala 314:64]
wire [12:0] _T_436 = {11'h0,_T_366,1'h0}; // @[Cat.scala 29:58] wire [12:0] _T_436 = {11'h0,_T_366,1'h0}; // @[Cat.scala 29:58]
wire [12:0] _T_439 = _T_389[12:1] + _T_436[12:1]; // @[el2_lib.scala 201:31] wire [12:0] _T_439 = _T_389[12:1] + _T_436[12:1]; // @[el2_lib.scala 206:31]
wire _T_448 = ~_T_439[12]; // @[el2_lib.scala 205:27] wire _T_448 = ~_T_439[12]; // @[el2_lib.scala 210:27]
wire _T_449 = _T_436[12] ^ _T_448; // @[el2_lib.scala 205:25] wire _T_449 = _T_436[12] ^ _T_448; // @[el2_lib.scala 210:25]
wire _T_452 = ~_T_436[12]; // @[el2_lib.scala 206:8] wire _T_452 = ~_T_436[12]; // @[el2_lib.scala 211:8]
wire _T_454 = _T_452 & _T_439[12]; // @[el2_lib.scala 206:14] wire _T_454 = _T_452 & _T_439[12]; // @[el2_lib.scala 211:14]
wire _T_458 = _T_436[12] & _T_448; // @[el2_lib.scala 207:13] wire _T_458 = _T_436[12] & _T_448; // @[el2_lib.scala 212:13]
wire [18:0] _T_460 = _T_449 ? _T_389[31:13] : 19'h0; // @[Mux.scala 27:72] wire [18:0] _T_460 = _T_449 ? _T_389[31:13] : 19'h0; // @[Mux.scala 27:72]
wire [18:0] _T_461 = _T_454 ? _T_396 : 19'h0; // @[Mux.scala 27:72] wire [18:0] _T_461 = _T_454 ? _T_396 : 19'h0; // @[Mux.scala 27:72]
wire [18:0] _T_462 = _T_458 ? _T_399 : 19'h0; // @[Mux.scala 27:72] wire [18:0] _T_462 = _T_458 ? _T_399 : 19'h0; // @[Mux.scala 27:72]
@ -7065,9 +7065,9 @@ module el2_ifu_bp_ctl(
wire [1:0] _T_559 = {io_dec_tlu_br0_r_pkt_middle,_T_558}; // @[Cat.scala 29:58] wire [1:0] _T_559 = {io_dec_tlu_br0_r_pkt_middle,_T_558}; // @[Cat.scala 29:58]
wire [1:0] bht_wr_en2 = _T_557 & _T_559; // @[el2_ifu_bp_ctl.scala 347:46] wire [1:0] bht_wr_en2 = _T_557 & _T_559; // @[el2_ifu_bp_ctl.scala 347:46]
wire [9:0] _T_560 = {io_exu_mp_index,2'h0}; // @[Cat.scala 29:58] wire [9:0] _T_560 = {io_exu_mp_index,2'h0}; // @[Cat.scala 29:58]
wire [7:0] mp_hashed = _T_560[9:2] ^ io_exu_mp_eghr; // @[el2_lib.scala 191:35] wire [7:0] mp_hashed = _T_560[9:2] ^ io_exu_mp_eghr; // @[el2_lib.scala 196:35]
wire [9:0] _T_563 = {io_exu_i0_br_index_r,2'h0}; // @[Cat.scala 29:58] wire [9:0] _T_563 = {io_exu_i0_br_index_r,2'h0}; // @[Cat.scala 29:58]
wire [7:0] br0_hashed_wb = _T_563[9:2] ^ io_exu_i0_br_fghr_r; // @[el2_lib.scala 191:35] wire [7:0] br0_hashed_wb = _T_563[9:2] ^ io_exu_i0_br_fghr_r; // @[el2_lib.scala 196:35]
wire _T_572 = btb_wr_addr == 8'h0; // @[el2_ifu_bp_ctl.scala 364:101] wire _T_572 = btb_wr_addr == 8'h0; // @[el2_ifu_bp_ctl.scala 364:101]
wire _T_573 = _T_572 & btb_wr_en_way0; // @[el2_ifu_bp_ctl.scala 364:109] wire _T_573 = _T_572 & btb_wr_en_way0; // @[el2_ifu_bp_ctl.scala 364:109]
wire _T_575 = btb_wr_addr == 8'h1; // @[el2_ifu_bp_ctl.scala 364:101] wire _T_575 = btb_wr_addr == 8'h1; // @[el2_ifu_bp_ctl.scala 364:101]

2
src/main/scala/ifu/el2_ifu_aln_ctl.scala
View File

@ -313,7 +313,7 @@ class el2_ifu_aln_ctl extends Module with el2_lib with RequireAsyncReset {
q1final := Mux1H(Seq(q1sel(0).asBool->q1eff(15,0), q1sel(1).asBool->q1eff(31,16))) q1final := Mux1H(Seq(q1sel(0).asBool->q1eff(15,0), q1sel(1).asBool->q1eff(31,16)))
val aligndata = Mux1H(Seq(f0val(0).asBool -> q0final, (~f0val(1) & f0val(0)).asBool -> Cat(q1final(15,0),q0final(15,0)))) val aligndata = Mux1H(Seq(f0val(1).asBool -> q0final, (~f0val(1) & f0val(0)).asBool -> Cat(q1final(15,0),q0final(15,0))))
alignval := Mux1H(Seq(f0val(1).asBool->3.U, (!f0val(1) & f0val(0)) -> Cat(f1val(0),1.U))) alignval := Mux1H(Seq(f0val(1).asBool->3.U, (!f0val(1) & f0val(0)) -> Cat(f1val(0),1.U)))

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target/scala-2.12/classes/ifu/el2_ifu_aln_ctl.class
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