From a0f383cb2d26da06fabfcbdfb76ea506a35c0bd8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E2=80=8BLaraib=20Khan?= <​laraib.khan@lampromellon.com> Date: Tue, 26 Jan 2021 15:03:26 +0500 Subject: [PATCH] Multiplier rvdffe updated --- exu.fir | 812 +++++++++--------- exu.v | 526 +++++------- exu_mul_ctl.fir | 28 +- exu_mul_ctl.v | 50 +- src/main/scala/lib/lib.scala | 44 +- src/main/scala/lib/param.scala | 17 +- .../classes/lib/lib$rvdff_fpga$.class | Bin 3283 -> 3283 bytes .../scala-2.12/classes/lib/lib$rvdffe$.class | Bin 11538 -> 12232 bytes .../scala-2.12/classes/lib/lib$rvdffie$.class | Bin 19664 -> 19664 bytes .../classes/lib/lib$rvdffiee$.class | Bin 7641 -> 7643 bytes .../classes/lib/lib$rvdfflie$.class | Bin 5950 -> 5950 bytes .../classes/lib/lib$rvdffpcie$.class | Bin 3513 -> 3513 bytes .../classes/lib/lib$rvdffppe$.class | Bin 6099 -> 6099 bytes .../classes/lib/lib$rvdffs_fpga$.class | Bin 3580 -> 3580 bytes .../classes/lib/lib$rvdffsc_fpga$.class | Bin 5290 -> 5290 bytes .../classes/lib/lib$rvoclkhdr$.class | Bin 5689 -> 5811 bytes target/scala-2.12/classes/lib/lib.class | Bin 62411 -> 62411 bytes 17 files changed, 719 insertions(+), 758 deletions(-) diff --git a/exu.fir b/exu.fir index cf510874..f6f772b2 100644 --- a/exu.fir +++ b/exu.fir @@ -315,8 +315,8 @@ circuit exu : ap_sh3add <= UInt<1>("h00") @[exu_alu_ctl.scala 130:21] ap_zba <= UInt<1>("h00") @[exu_alu_ctl.scala 131:21] node _T_12 = bits(io.scan_mode, 0, 0) @[exu_alu_ctl.scala 133:104] - wire _T_13 : UInt<31> @[lib.scala 636:38] - _T_13 <= UInt<1>("h00") @[lib.scala 636:38] + wire _T_13 : UInt<31> @[lib.scala 648:38] + _T_13 <= UInt<1>("h00") @[lib.scala 648:38] reg _T_14 : UInt, clock with : (reset => (reset, _T_13)) @[Reg.scala 27:20] when io.enable : @[Reg.scala 28:19] _T_14 <= io.dec_i0_pc_d @[Reg.scala 28:23] @@ -327,12 +327,12 @@ circuit exu : node _T_15 = and(io.enable, io.dec_alu.dec_i0_alu_decode_d) @[exu_alu_ctl.scala 135:43] node _T_16 = bits(_T_15, 0, 0) @[lib.scala 8:44] node _T_17 = bits(io.scan_mode, 0, 0) @[exu_alu_ctl.scala 135:95] - inst rvclkhdr of rvclkhdr_8 @[lib.scala 399:23] + inst rvclkhdr of rvclkhdr_8 @[lib.scala 404:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset - rvclkhdr.io.clk <= clock @[lib.scala 401:18] - rvclkhdr.io.en <= _T_16 @[lib.scala 402:17] - rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] + rvclkhdr.io.clk <= clock @[lib.scala 406:18] + rvclkhdr.io.en <= _T_16 @[lib.scala 407:17] + rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] reg _T_18 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_16 : @[Reg.scala 28:19] _T_18 <= result @[Reg.scala 28:23] @@ -1721,36 +1721,40 @@ circuit exu : node _T_7 = asSInt(_T_6) @[exu_mul_ctl.scala 124:71] rs2_ext_in <= _T_7 @[exu_mul_ctl.scala 124:14] node _T_8 = bits(io.mul_p.valid, 0, 0) @[exu_mul_ctl.scala 126:52] - inst rvclkhdr of rvclkhdr_9 @[lib.scala 399:23] + inst rvclkhdr of rvclkhdr_9 @[lib.scala 404:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset - rvclkhdr.io.clk <= clock @[lib.scala 401:18] - rvclkhdr.io.en <= _T_8 @[lib.scala 402:17] - rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] + rvclkhdr.io.clk <= clock @[lib.scala 406:18] + rvclkhdr.io.en <= _T_8 @[lib.scala 407:17] + rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] reg _T_9 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8 : @[Reg.scala 28:19] _T_9 <= io.mul_p.bits.low @[Reg.scala 28:23] skip @[Reg.scala 28:19] low_x <= _T_9 @[exu_mul_ctl.scala 126:9] node _T_10 = bits(io.mul_p.valid, 0, 0) @[exu_mul_ctl.scala 127:44] - inst rvclkhdr_1 of rvclkhdr_10 @[lib.scala 422:23] + inst rvclkhdr_1 of rvclkhdr_10 @[lib.scala 431:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset - rvclkhdr_1.io.clk <= clock @[lib.scala 424:18] - rvclkhdr_1.io.en <= _T_10 @[lib.scala 425:17] - rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 426:24] - reg _T_11 : SInt, rvclkhdr_1.io.l1clk with : (reset => (reset, asSInt(UInt<1>("h00")))) @[lib.scala 428:16] - _T_11 <= rs1_ext_in @[lib.scala 428:16] + rvclkhdr_1.io.clk <= clock @[lib.scala 433:18] + rvclkhdr_1.io.en <= _T_10 @[lib.scala 434:17] + rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 435:24] + reg _T_11 : SInt, clock with : (reset => (reset, asSInt(UInt<1>("h00")))) @[Reg.scala 27:20] + when _T_10 : @[Reg.scala 28:19] + _T_11 <= rs1_ext_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] rs1_x <= _T_11 @[exu_mul_ctl.scala 127:9] node _T_12 = bits(io.mul_p.valid, 0, 0) @[exu_mul_ctl.scala 128:45] - inst rvclkhdr_2 of rvclkhdr_11 @[lib.scala 422:23] + inst rvclkhdr_2 of rvclkhdr_11 @[lib.scala 431:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset - rvclkhdr_2.io.clk <= clock @[lib.scala 424:18] - rvclkhdr_2.io.en <= _T_12 @[lib.scala 425:17] - rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 426:24] - reg _T_13 : SInt, rvclkhdr_2.io.l1clk with : (reset => (reset, asSInt(UInt<1>("h00")))) @[lib.scala 428:16] - _T_13 <= rs2_ext_in @[lib.scala 428:16] + rvclkhdr_2.io.clk <= clock @[lib.scala 433:18] + rvclkhdr_2.io.en <= _T_12 @[lib.scala 434:17] + rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 435:24] + reg _T_13 : SInt, clock with : (reset => (reset, asSInt(UInt<1>("h00")))) @[Reg.scala 27:20] + when _T_12 : @[Reg.scala 28:19] + _T_13 <= rs2_ext_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] rs2_x <= _T_13 @[exu_mul_ctl.scala 128:9] node _T_14 = mul(rs1_x, rs2_x) @[exu_mul_ctl.scala 130:20] prod_x <= _T_14 @[exu_mul_ctl.scala 130:10] @@ -41654,22 +41658,22 @@ circuit exu : node _T_39756 = or(_T_39755, _T_39741) @[Mux.scala 27:72] wire bitmanip_d : UInt<32> @[Mux.scala 27:72] bitmanip_d <= _T_39756 @[Mux.scala 27:72] - inst rvclkhdr_3 of rvclkhdr_12 @[lib.scala 399:23] + inst rvclkhdr_3 of rvclkhdr_12 @[lib.scala 404:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset - rvclkhdr_3.io.clk <= clock @[lib.scala 401:18] - rvclkhdr_3.io.en <= io.mul_p.valid @[lib.scala 402:17] - rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] + rvclkhdr_3.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_3.io.en <= io.mul_p.valid @[lib.scala 407:17] + rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] reg bitmanip_sel_x : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when io.mul_p.valid : @[Reg.scala 28:19] bitmanip_sel_x <= bitmanip_sel_d @[Reg.scala 28:23] skip @[Reg.scala 28:19] - inst rvclkhdr_4 of rvclkhdr_13 @[lib.scala 399:23] + inst rvclkhdr_4 of rvclkhdr_13 @[lib.scala 404:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset - rvclkhdr_4.io.clk <= clock @[lib.scala 401:18] - rvclkhdr_4.io.en <= io.mul_p.valid @[lib.scala 402:17] - rvclkhdr_4.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] + rvclkhdr_4.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_4.io.en <= io.mul_p.valid @[lib.scala 407:17] + rvclkhdr_4.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] reg bitmanip_x : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when io.mul_p.valid : @[Reg.scala 28:19] bitmanip_x <= bitmanip_d @[Reg.scala 28:23] @@ -43411,255 +43415,255 @@ circuit exu : node _T_609 = or(_T_607, _T_608) @[Mux.scala 27:72] wire twos_comp_in : UInt<32> @[Mux.scala 27:72] twos_comp_in <= _T_609 @[Mux.scala 27:72] - wire _T_610 : UInt<1>[31] @[lib.scala 647:20] - node _T_611 = bits(twos_comp_in, 0, 0) @[lib.scala 649:27] - node _T_612 = orr(_T_611) @[lib.scala 649:35] - node _T_613 = bits(twos_comp_in, 1, 1) @[lib.scala 649:44] - node _T_614 = not(_T_613) @[lib.scala 649:40] - node _T_615 = bits(twos_comp_in, 1, 1) @[lib.scala 649:51] - node _T_616 = mux(_T_612, _T_614, _T_615) @[lib.scala 649:23] - _T_610[0] <= _T_616 @[lib.scala 649:17] - node _T_617 = bits(twos_comp_in, 1, 0) @[lib.scala 649:27] - node _T_618 = orr(_T_617) @[lib.scala 649:35] - node _T_619 = bits(twos_comp_in, 2, 2) @[lib.scala 649:44] - node _T_620 = not(_T_619) @[lib.scala 649:40] - node _T_621 = bits(twos_comp_in, 2, 2) @[lib.scala 649:51] - node _T_622 = mux(_T_618, _T_620, _T_621) @[lib.scala 649:23] - _T_610[1] <= _T_622 @[lib.scala 649:17] - node _T_623 = bits(twos_comp_in, 2, 0) @[lib.scala 649:27] - node _T_624 = orr(_T_623) @[lib.scala 649:35] - node _T_625 = bits(twos_comp_in, 3, 3) @[lib.scala 649:44] - node _T_626 = not(_T_625) @[lib.scala 649:40] - node _T_627 = bits(twos_comp_in, 3, 3) @[lib.scala 649:51] - node _T_628 = mux(_T_624, _T_626, _T_627) @[lib.scala 649:23] - _T_610[2] <= _T_628 @[lib.scala 649:17] - node _T_629 = bits(twos_comp_in, 3, 0) @[lib.scala 649:27] - node _T_630 = orr(_T_629) @[lib.scala 649:35] - node _T_631 = bits(twos_comp_in, 4, 4) @[lib.scala 649:44] - node _T_632 = not(_T_631) @[lib.scala 649:40] - node _T_633 = bits(twos_comp_in, 4, 4) @[lib.scala 649:51] - node _T_634 = mux(_T_630, _T_632, _T_633) @[lib.scala 649:23] - _T_610[3] <= _T_634 @[lib.scala 649:17] - node _T_635 = bits(twos_comp_in, 4, 0) @[lib.scala 649:27] - node _T_636 = orr(_T_635) @[lib.scala 649:35] - node _T_637 = bits(twos_comp_in, 5, 5) @[lib.scala 649:44] - node _T_638 = not(_T_637) @[lib.scala 649:40] - node _T_639 = bits(twos_comp_in, 5, 5) @[lib.scala 649:51] - node _T_640 = mux(_T_636, _T_638, _T_639) @[lib.scala 649:23] - _T_610[4] <= _T_640 @[lib.scala 649:17] - node _T_641 = bits(twos_comp_in, 5, 0) @[lib.scala 649:27] - node _T_642 = orr(_T_641) @[lib.scala 649:35] - node _T_643 = bits(twos_comp_in, 6, 6) @[lib.scala 649:44] - node _T_644 = not(_T_643) @[lib.scala 649:40] - node _T_645 = bits(twos_comp_in, 6, 6) @[lib.scala 649:51] - node _T_646 = mux(_T_642, _T_644, _T_645) @[lib.scala 649:23] - _T_610[5] <= _T_646 @[lib.scala 649:17] - node _T_647 = bits(twos_comp_in, 6, 0) @[lib.scala 649:27] - node _T_648 = orr(_T_647) @[lib.scala 649:35] - node _T_649 = bits(twos_comp_in, 7, 7) @[lib.scala 649:44] - node _T_650 = not(_T_649) @[lib.scala 649:40] - node _T_651 = bits(twos_comp_in, 7, 7) @[lib.scala 649:51] - node _T_652 = mux(_T_648, _T_650, _T_651) @[lib.scala 649:23] - _T_610[6] <= _T_652 @[lib.scala 649:17] - node _T_653 = bits(twos_comp_in, 7, 0) @[lib.scala 649:27] - node _T_654 = orr(_T_653) @[lib.scala 649:35] - node _T_655 = bits(twos_comp_in, 8, 8) @[lib.scala 649:44] - node _T_656 = not(_T_655) @[lib.scala 649:40] - node _T_657 = bits(twos_comp_in, 8, 8) @[lib.scala 649:51] - node _T_658 = mux(_T_654, _T_656, _T_657) @[lib.scala 649:23] - _T_610[7] <= _T_658 @[lib.scala 649:17] - node _T_659 = bits(twos_comp_in, 8, 0) @[lib.scala 649:27] - node _T_660 = orr(_T_659) @[lib.scala 649:35] - node _T_661 = bits(twos_comp_in, 9, 9) @[lib.scala 649:44] - node _T_662 = not(_T_661) @[lib.scala 649:40] - node _T_663 = bits(twos_comp_in, 9, 9) @[lib.scala 649:51] - node _T_664 = mux(_T_660, _T_662, _T_663) @[lib.scala 649:23] - _T_610[8] <= _T_664 @[lib.scala 649:17] - node _T_665 = bits(twos_comp_in, 9, 0) @[lib.scala 649:27] - node _T_666 = orr(_T_665) @[lib.scala 649:35] - node _T_667 = bits(twos_comp_in, 10, 10) @[lib.scala 649:44] - node _T_668 = not(_T_667) @[lib.scala 649:40] - node _T_669 = bits(twos_comp_in, 10, 10) @[lib.scala 649:51] - node _T_670 = mux(_T_666, _T_668, _T_669) @[lib.scala 649:23] - _T_610[9] <= _T_670 @[lib.scala 649:17] - node _T_671 = bits(twos_comp_in, 10, 0) @[lib.scala 649:27] - node _T_672 = orr(_T_671) @[lib.scala 649:35] - node _T_673 = bits(twos_comp_in, 11, 11) @[lib.scala 649:44] - node _T_674 = not(_T_673) @[lib.scala 649:40] - node _T_675 = bits(twos_comp_in, 11, 11) @[lib.scala 649:51] - node _T_676 = mux(_T_672, _T_674, _T_675) @[lib.scala 649:23] - _T_610[10] <= _T_676 @[lib.scala 649:17] - node _T_677 = bits(twos_comp_in, 11, 0) @[lib.scala 649:27] - node _T_678 = orr(_T_677) @[lib.scala 649:35] - node _T_679 = bits(twos_comp_in, 12, 12) @[lib.scala 649:44] - node _T_680 = not(_T_679) @[lib.scala 649:40] - node _T_681 = bits(twos_comp_in, 12, 12) @[lib.scala 649:51] - node _T_682 = mux(_T_678, _T_680, _T_681) @[lib.scala 649:23] - _T_610[11] <= _T_682 @[lib.scala 649:17] - node _T_683 = bits(twos_comp_in, 12, 0) @[lib.scala 649:27] - node _T_684 = orr(_T_683) @[lib.scala 649:35] - node _T_685 = bits(twos_comp_in, 13, 13) @[lib.scala 649:44] - node _T_686 = not(_T_685) @[lib.scala 649:40] - node _T_687 = bits(twos_comp_in, 13, 13) @[lib.scala 649:51] - node _T_688 = mux(_T_684, _T_686, _T_687) @[lib.scala 649:23] - _T_610[12] <= _T_688 @[lib.scala 649:17] - node _T_689 = bits(twos_comp_in, 13, 0) @[lib.scala 649:27] - node _T_690 = orr(_T_689) @[lib.scala 649:35] - node _T_691 = bits(twos_comp_in, 14, 14) @[lib.scala 649:44] - node _T_692 = not(_T_691) @[lib.scala 649:40] - node _T_693 = bits(twos_comp_in, 14, 14) @[lib.scala 649:51] - node _T_694 = mux(_T_690, _T_692, _T_693) @[lib.scala 649:23] - _T_610[13] <= _T_694 @[lib.scala 649:17] - node _T_695 = bits(twos_comp_in, 14, 0) @[lib.scala 649:27] - node _T_696 = orr(_T_695) @[lib.scala 649:35] - node _T_697 = bits(twos_comp_in, 15, 15) @[lib.scala 649:44] - node _T_698 = not(_T_697) @[lib.scala 649:40] - node _T_699 = bits(twos_comp_in, 15, 15) @[lib.scala 649:51] - node _T_700 = mux(_T_696, _T_698, _T_699) @[lib.scala 649:23] - _T_610[14] <= _T_700 @[lib.scala 649:17] - node _T_701 = bits(twos_comp_in, 15, 0) @[lib.scala 649:27] - node _T_702 = orr(_T_701) @[lib.scala 649:35] - node _T_703 = bits(twos_comp_in, 16, 16) @[lib.scala 649:44] - node _T_704 = not(_T_703) @[lib.scala 649:40] - node _T_705 = bits(twos_comp_in, 16, 16) @[lib.scala 649:51] - node _T_706 = mux(_T_702, _T_704, _T_705) @[lib.scala 649:23] - _T_610[15] <= _T_706 @[lib.scala 649:17] - node _T_707 = bits(twos_comp_in, 16, 0) @[lib.scala 649:27] - node _T_708 = orr(_T_707) @[lib.scala 649:35] - node _T_709 = bits(twos_comp_in, 17, 17) @[lib.scala 649:44] - node _T_710 = not(_T_709) @[lib.scala 649:40] - node _T_711 = bits(twos_comp_in, 17, 17) @[lib.scala 649:51] - node _T_712 = mux(_T_708, _T_710, _T_711) @[lib.scala 649:23] - _T_610[16] <= _T_712 @[lib.scala 649:17] - node _T_713 = bits(twos_comp_in, 17, 0) @[lib.scala 649:27] - node _T_714 = orr(_T_713) @[lib.scala 649:35] - node _T_715 = bits(twos_comp_in, 18, 18) @[lib.scala 649:44] - node _T_716 = not(_T_715) @[lib.scala 649:40] - node _T_717 = bits(twos_comp_in, 18, 18) @[lib.scala 649:51] - node _T_718 = mux(_T_714, _T_716, _T_717) @[lib.scala 649:23] - _T_610[17] <= _T_718 @[lib.scala 649:17] - node _T_719 = bits(twos_comp_in, 18, 0) @[lib.scala 649:27] - node _T_720 = orr(_T_719) @[lib.scala 649:35] - node _T_721 = bits(twos_comp_in, 19, 19) @[lib.scala 649:44] - node _T_722 = not(_T_721) @[lib.scala 649:40] - node _T_723 = bits(twos_comp_in, 19, 19) @[lib.scala 649:51] - node _T_724 = mux(_T_720, _T_722, _T_723) @[lib.scala 649:23] - _T_610[18] <= _T_724 @[lib.scala 649:17] - node _T_725 = bits(twos_comp_in, 19, 0) @[lib.scala 649:27] - node _T_726 = orr(_T_725) @[lib.scala 649:35] - node _T_727 = bits(twos_comp_in, 20, 20) @[lib.scala 649:44] - node _T_728 = not(_T_727) @[lib.scala 649:40] - node _T_729 = bits(twos_comp_in, 20, 20) @[lib.scala 649:51] - node _T_730 = mux(_T_726, _T_728, _T_729) @[lib.scala 649:23] - _T_610[19] <= _T_730 @[lib.scala 649:17] - node _T_731 = bits(twos_comp_in, 20, 0) @[lib.scala 649:27] - node _T_732 = orr(_T_731) @[lib.scala 649:35] - node _T_733 = bits(twos_comp_in, 21, 21) @[lib.scala 649:44] - node _T_734 = not(_T_733) @[lib.scala 649:40] - node _T_735 = bits(twos_comp_in, 21, 21) @[lib.scala 649:51] - node _T_736 = mux(_T_732, _T_734, _T_735) @[lib.scala 649:23] - _T_610[20] <= _T_736 @[lib.scala 649:17] - node _T_737 = bits(twos_comp_in, 21, 0) @[lib.scala 649:27] - node _T_738 = orr(_T_737) @[lib.scala 649:35] - node _T_739 = bits(twos_comp_in, 22, 22) @[lib.scala 649:44] - node _T_740 = not(_T_739) @[lib.scala 649:40] - node _T_741 = bits(twos_comp_in, 22, 22) @[lib.scala 649:51] - node _T_742 = mux(_T_738, _T_740, _T_741) @[lib.scala 649:23] - _T_610[21] <= _T_742 @[lib.scala 649:17] - node _T_743 = bits(twos_comp_in, 22, 0) @[lib.scala 649:27] - node _T_744 = orr(_T_743) @[lib.scala 649:35] - node _T_745 = bits(twos_comp_in, 23, 23) @[lib.scala 649:44] - node _T_746 = not(_T_745) @[lib.scala 649:40] - node _T_747 = bits(twos_comp_in, 23, 23) @[lib.scala 649:51] - node _T_748 = mux(_T_744, _T_746, _T_747) @[lib.scala 649:23] - _T_610[22] <= _T_748 @[lib.scala 649:17] - node _T_749 = bits(twos_comp_in, 23, 0) @[lib.scala 649:27] - node _T_750 = orr(_T_749) @[lib.scala 649:35] - node _T_751 = bits(twos_comp_in, 24, 24) @[lib.scala 649:44] - node _T_752 = not(_T_751) @[lib.scala 649:40] - node _T_753 = bits(twos_comp_in, 24, 24) @[lib.scala 649:51] - node _T_754 = mux(_T_750, _T_752, _T_753) @[lib.scala 649:23] - _T_610[23] <= _T_754 @[lib.scala 649:17] - node _T_755 = bits(twos_comp_in, 24, 0) @[lib.scala 649:27] - node _T_756 = orr(_T_755) @[lib.scala 649:35] - node _T_757 = bits(twos_comp_in, 25, 25) @[lib.scala 649:44] - node _T_758 = not(_T_757) @[lib.scala 649:40] - node _T_759 = bits(twos_comp_in, 25, 25) @[lib.scala 649:51] - node _T_760 = mux(_T_756, _T_758, _T_759) @[lib.scala 649:23] - _T_610[24] <= _T_760 @[lib.scala 649:17] - node _T_761 = bits(twos_comp_in, 25, 0) @[lib.scala 649:27] - node _T_762 = orr(_T_761) @[lib.scala 649:35] - node _T_763 = bits(twos_comp_in, 26, 26) @[lib.scala 649:44] - node _T_764 = not(_T_763) @[lib.scala 649:40] - node _T_765 = bits(twos_comp_in, 26, 26) @[lib.scala 649:51] - node _T_766 = mux(_T_762, _T_764, _T_765) @[lib.scala 649:23] - _T_610[25] <= _T_766 @[lib.scala 649:17] - node _T_767 = bits(twos_comp_in, 26, 0) @[lib.scala 649:27] - node _T_768 = orr(_T_767) @[lib.scala 649:35] - node _T_769 = bits(twos_comp_in, 27, 27) @[lib.scala 649:44] - node _T_770 = not(_T_769) @[lib.scala 649:40] - node _T_771 = bits(twos_comp_in, 27, 27) @[lib.scala 649:51] - node _T_772 = mux(_T_768, _T_770, _T_771) @[lib.scala 649:23] - _T_610[26] <= _T_772 @[lib.scala 649:17] - node _T_773 = bits(twos_comp_in, 27, 0) @[lib.scala 649:27] - node _T_774 = orr(_T_773) @[lib.scala 649:35] - node _T_775 = bits(twos_comp_in, 28, 28) @[lib.scala 649:44] - node _T_776 = not(_T_775) @[lib.scala 649:40] - node _T_777 = bits(twos_comp_in, 28, 28) @[lib.scala 649:51] - node _T_778 = mux(_T_774, _T_776, _T_777) @[lib.scala 649:23] - _T_610[27] <= _T_778 @[lib.scala 649:17] - node _T_779 = bits(twos_comp_in, 28, 0) @[lib.scala 649:27] - node _T_780 = orr(_T_779) @[lib.scala 649:35] - node _T_781 = bits(twos_comp_in, 29, 29) @[lib.scala 649:44] - node _T_782 = not(_T_781) @[lib.scala 649:40] - node _T_783 = bits(twos_comp_in, 29, 29) @[lib.scala 649:51] - node _T_784 = mux(_T_780, _T_782, _T_783) @[lib.scala 649:23] - _T_610[28] <= _T_784 @[lib.scala 649:17] - node _T_785 = bits(twos_comp_in, 29, 0) @[lib.scala 649:27] - node _T_786 = orr(_T_785) @[lib.scala 649:35] - node _T_787 = bits(twos_comp_in, 30, 30) @[lib.scala 649:44] - node _T_788 = not(_T_787) @[lib.scala 649:40] - node _T_789 = bits(twos_comp_in, 30, 30) @[lib.scala 649:51] - node _T_790 = mux(_T_786, _T_788, _T_789) @[lib.scala 649:23] - _T_610[29] <= _T_790 @[lib.scala 649:17] - node _T_791 = bits(twos_comp_in, 30, 0) @[lib.scala 649:27] - node _T_792 = orr(_T_791) @[lib.scala 649:35] - node _T_793 = bits(twos_comp_in, 31, 31) @[lib.scala 649:44] - node _T_794 = not(_T_793) @[lib.scala 649:40] - node _T_795 = bits(twos_comp_in, 31, 31) @[lib.scala 649:51] - node _T_796 = mux(_T_792, _T_794, _T_795) @[lib.scala 649:23] - _T_610[30] <= _T_796 @[lib.scala 649:17] - node _T_797 = cat(_T_610[2], _T_610[1]) @[lib.scala 651:14] - node _T_798 = cat(_T_797, _T_610[0]) @[lib.scala 651:14] - node _T_799 = cat(_T_610[4], _T_610[3]) @[lib.scala 651:14] - node _T_800 = cat(_T_610[6], _T_610[5]) @[lib.scala 651:14] - node _T_801 = cat(_T_800, _T_799) @[lib.scala 651:14] - node _T_802 = cat(_T_801, _T_798) @[lib.scala 651:14] - node _T_803 = cat(_T_610[8], _T_610[7]) @[lib.scala 651:14] - node _T_804 = cat(_T_610[10], _T_610[9]) @[lib.scala 651:14] - node _T_805 = cat(_T_804, _T_803) @[lib.scala 651:14] - node _T_806 = cat(_T_610[12], _T_610[11]) @[lib.scala 651:14] - node _T_807 = cat(_T_610[14], _T_610[13]) @[lib.scala 651:14] - node _T_808 = cat(_T_807, _T_806) @[lib.scala 651:14] - node _T_809 = cat(_T_808, _T_805) @[lib.scala 651:14] - node _T_810 = cat(_T_809, _T_802) @[lib.scala 651:14] - node _T_811 = cat(_T_610[16], _T_610[15]) @[lib.scala 651:14] - node _T_812 = cat(_T_610[18], _T_610[17]) @[lib.scala 651:14] - node _T_813 = cat(_T_812, _T_811) @[lib.scala 651:14] - node _T_814 = cat(_T_610[20], _T_610[19]) @[lib.scala 651:14] - node _T_815 = cat(_T_610[22], _T_610[21]) @[lib.scala 651:14] - node _T_816 = cat(_T_815, _T_814) @[lib.scala 651:14] - node _T_817 = cat(_T_816, _T_813) @[lib.scala 651:14] - node _T_818 = cat(_T_610[24], _T_610[23]) @[lib.scala 651:14] - node _T_819 = cat(_T_610[26], _T_610[25]) @[lib.scala 651:14] - node _T_820 = cat(_T_819, _T_818) @[lib.scala 651:14] - node _T_821 = cat(_T_610[28], _T_610[27]) @[lib.scala 651:14] - node _T_822 = cat(_T_610[30], _T_610[29]) @[lib.scala 651:14] - node _T_823 = cat(_T_822, _T_821) @[lib.scala 651:14] - node _T_824 = cat(_T_823, _T_820) @[lib.scala 651:14] - node _T_825 = cat(_T_824, _T_817) @[lib.scala 651:14] - node _T_826 = cat(_T_825, _T_810) @[lib.scala 651:14] - node _T_827 = bits(twos_comp_in, 0, 0) @[lib.scala 651:24] + wire _T_610 : UInt<1>[31] @[lib.scala 659:20] + node _T_611 = bits(twos_comp_in, 0, 0) @[lib.scala 661:27] + node _T_612 = orr(_T_611) @[lib.scala 661:35] + node _T_613 = bits(twos_comp_in, 1, 1) @[lib.scala 661:44] + node _T_614 = not(_T_613) @[lib.scala 661:40] + node _T_615 = bits(twos_comp_in, 1, 1) @[lib.scala 661:51] + node _T_616 = mux(_T_612, _T_614, _T_615) @[lib.scala 661:23] + _T_610[0] <= _T_616 @[lib.scala 661:17] + node _T_617 = bits(twos_comp_in, 1, 0) @[lib.scala 661:27] + node _T_618 = orr(_T_617) @[lib.scala 661:35] + node _T_619 = bits(twos_comp_in, 2, 2) @[lib.scala 661:44] + node _T_620 = not(_T_619) @[lib.scala 661:40] + node _T_621 = bits(twos_comp_in, 2, 2) @[lib.scala 661:51] + node _T_622 = mux(_T_618, _T_620, _T_621) @[lib.scala 661:23] + _T_610[1] <= _T_622 @[lib.scala 661:17] + node _T_623 = bits(twos_comp_in, 2, 0) @[lib.scala 661:27] + node _T_624 = orr(_T_623) @[lib.scala 661:35] + node _T_625 = bits(twos_comp_in, 3, 3) @[lib.scala 661:44] + node _T_626 = not(_T_625) @[lib.scala 661:40] + node _T_627 = bits(twos_comp_in, 3, 3) @[lib.scala 661:51] + node _T_628 = mux(_T_624, _T_626, _T_627) @[lib.scala 661:23] + _T_610[2] <= _T_628 @[lib.scala 661:17] + node _T_629 = bits(twos_comp_in, 3, 0) @[lib.scala 661:27] + node _T_630 = orr(_T_629) @[lib.scala 661:35] + node _T_631 = bits(twos_comp_in, 4, 4) @[lib.scala 661:44] + node _T_632 = not(_T_631) @[lib.scala 661:40] + node _T_633 = bits(twos_comp_in, 4, 4) @[lib.scala 661:51] + node _T_634 = mux(_T_630, _T_632, _T_633) @[lib.scala 661:23] + _T_610[3] <= _T_634 @[lib.scala 661:17] + node _T_635 = bits(twos_comp_in, 4, 0) @[lib.scala 661:27] + node _T_636 = orr(_T_635) @[lib.scala 661:35] + node _T_637 = bits(twos_comp_in, 5, 5) @[lib.scala 661:44] + node _T_638 = not(_T_637) @[lib.scala 661:40] + node _T_639 = bits(twos_comp_in, 5, 5) @[lib.scala 661:51] + node _T_640 = mux(_T_636, _T_638, _T_639) @[lib.scala 661:23] + _T_610[4] <= _T_640 @[lib.scala 661:17] + node _T_641 = bits(twos_comp_in, 5, 0) @[lib.scala 661:27] + node _T_642 = orr(_T_641) @[lib.scala 661:35] + node _T_643 = bits(twos_comp_in, 6, 6) @[lib.scala 661:44] + node _T_644 = not(_T_643) @[lib.scala 661:40] + node _T_645 = bits(twos_comp_in, 6, 6) @[lib.scala 661:51] + node _T_646 = mux(_T_642, _T_644, _T_645) @[lib.scala 661:23] + _T_610[5] <= _T_646 @[lib.scala 661:17] + node _T_647 = bits(twos_comp_in, 6, 0) @[lib.scala 661:27] + node _T_648 = orr(_T_647) @[lib.scala 661:35] + node _T_649 = bits(twos_comp_in, 7, 7) @[lib.scala 661:44] + node _T_650 = not(_T_649) @[lib.scala 661:40] + node _T_651 = bits(twos_comp_in, 7, 7) @[lib.scala 661:51] + node _T_652 = mux(_T_648, _T_650, _T_651) @[lib.scala 661:23] + _T_610[6] <= _T_652 @[lib.scala 661:17] + node _T_653 = bits(twos_comp_in, 7, 0) @[lib.scala 661:27] + node _T_654 = orr(_T_653) @[lib.scala 661:35] + node _T_655 = bits(twos_comp_in, 8, 8) @[lib.scala 661:44] + node _T_656 = not(_T_655) @[lib.scala 661:40] + node _T_657 = bits(twos_comp_in, 8, 8) @[lib.scala 661:51] + node _T_658 = mux(_T_654, _T_656, _T_657) @[lib.scala 661:23] + _T_610[7] <= _T_658 @[lib.scala 661:17] + node _T_659 = bits(twos_comp_in, 8, 0) @[lib.scala 661:27] + node _T_660 = orr(_T_659) @[lib.scala 661:35] + node _T_661 = bits(twos_comp_in, 9, 9) @[lib.scala 661:44] + node _T_662 = not(_T_661) @[lib.scala 661:40] + node _T_663 = bits(twos_comp_in, 9, 9) @[lib.scala 661:51] + node _T_664 = mux(_T_660, _T_662, _T_663) @[lib.scala 661:23] + _T_610[8] <= _T_664 @[lib.scala 661:17] + node _T_665 = bits(twos_comp_in, 9, 0) @[lib.scala 661:27] + node _T_666 = orr(_T_665) @[lib.scala 661:35] + node _T_667 = bits(twos_comp_in, 10, 10) @[lib.scala 661:44] + node _T_668 = not(_T_667) @[lib.scala 661:40] + node _T_669 = bits(twos_comp_in, 10, 10) @[lib.scala 661:51] + node _T_670 = mux(_T_666, _T_668, _T_669) @[lib.scala 661:23] + _T_610[9] <= _T_670 @[lib.scala 661:17] + node _T_671 = bits(twos_comp_in, 10, 0) @[lib.scala 661:27] + node _T_672 = orr(_T_671) @[lib.scala 661:35] + node _T_673 = bits(twos_comp_in, 11, 11) @[lib.scala 661:44] + node _T_674 = not(_T_673) @[lib.scala 661:40] + node _T_675 = bits(twos_comp_in, 11, 11) @[lib.scala 661:51] + node _T_676 = mux(_T_672, _T_674, _T_675) @[lib.scala 661:23] + _T_610[10] <= _T_676 @[lib.scala 661:17] + node _T_677 = bits(twos_comp_in, 11, 0) @[lib.scala 661:27] + node _T_678 = orr(_T_677) @[lib.scala 661:35] + node _T_679 = bits(twos_comp_in, 12, 12) @[lib.scala 661:44] + node _T_680 = not(_T_679) @[lib.scala 661:40] + node _T_681 = bits(twos_comp_in, 12, 12) @[lib.scala 661:51] + node _T_682 = mux(_T_678, _T_680, _T_681) @[lib.scala 661:23] + _T_610[11] <= _T_682 @[lib.scala 661:17] + node _T_683 = bits(twos_comp_in, 12, 0) @[lib.scala 661:27] + node _T_684 = orr(_T_683) @[lib.scala 661:35] + node _T_685 = bits(twos_comp_in, 13, 13) @[lib.scala 661:44] + node _T_686 = not(_T_685) @[lib.scala 661:40] + node _T_687 = bits(twos_comp_in, 13, 13) @[lib.scala 661:51] + node _T_688 = mux(_T_684, _T_686, _T_687) @[lib.scala 661:23] + _T_610[12] <= _T_688 @[lib.scala 661:17] + node _T_689 = bits(twos_comp_in, 13, 0) @[lib.scala 661:27] + node _T_690 = orr(_T_689) @[lib.scala 661:35] + node _T_691 = bits(twos_comp_in, 14, 14) @[lib.scala 661:44] + node _T_692 = not(_T_691) @[lib.scala 661:40] + node _T_693 = bits(twos_comp_in, 14, 14) @[lib.scala 661:51] + node _T_694 = mux(_T_690, _T_692, _T_693) @[lib.scala 661:23] + _T_610[13] <= _T_694 @[lib.scala 661:17] + node _T_695 = bits(twos_comp_in, 14, 0) @[lib.scala 661:27] + node _T_696 = orr(_T_695) @[lib.scala 661:35] + node _T_697 = bits(twos_comp_in, 15, 15) @[lib.scala 661:44] + node _T_698 = not(_T_697) @[lib.scala 661:40] + node _T_699 = bits(twos_comp_in, 15, 15) @[lib.scala 661:51] + node _T_700 = mux(_T_696, _T_698, _T_699) @[lib.scala 661:23] + _T_610[14] <= _T_700 @[lib.scala 661:17] + node _T_701 = bits(twos_comp_in, 15, 0) @[lib.scala 661:27] + node _T_702 = orr(_T_701) @[lib.scala 661:35] + node _T_703 = bits(twos_comp_in, 16, 16) @[lib.scala 661:44] + node _T_704 = not(_T_703) @[lib.scala 661:40] + node _T_705 = bits(twos_comp_in, 16, 16) @[lib.scala 661:51] + node _T_706 = mux(_T_702, _T_704, _T_705) @[lib.scala 661:23] + _T_610[15] <= _T_706 @[lib.scala 661:17] + node _T_707 = bits(twos_comp_in, 16, 0) @[lib.scala 661:27] + node _T_708 = orr(_T_707) @[lib.scala 661:35] + node _T_709 = bits(twos_comp_in, 17, 17) @[lib.scala 661:44] + node _T_710 = not(_T_709) @[lib.scala 661:40] + node _T_711 = bits(twos_comp_in, 17, 17) @[lib.scala 661:51] + node _T_712 = mux(_T_708, _T_710, _T_711) @[lib.scala 661:23] + _T_610[16] <= _T_712 @[lib.scala 661:17] + node _T_713 = bits(twos_comp_in, 17, 0) @[lib.scala 661:27] + node _T_714 = orr(_T_713) @[lib.scala 661:35] + node _T_715 = bits(twos_comp_in, 18, 18) @[lib.scala 661:44] + node _T_716 = not(_T_715) @[lib.scala 661:40] + node _T_717 = bits(twos_comp_in, 18, 18) @[lib.scala 661:51] + node _T_718 = mux(_T_714, _T_716, _T_717) @[lib.scala 661:23] + _T_610[17] <= _T_718 @[lib.scala 661:17] + node _T_719 = bits(twos_comp_in, 18, 0) @[lib.scala 661:27] + node _T_720 = orr(_T_719) @[lib.scala 661:35] + node _T_721 = bits(twos_comp_in, 19, 19) @[lib.scala 661:44] + node _T_722 = not(_T_721) @[lib.scala 661:40] + node _T_723 = bits(twos_comp_in, 19, 19) @[lib.scala 661:51] + node _T_724 = mux(_T_720, _T_722, _T_723) @[lib.scala 661:23] + _T_610[18] <= _T_724 @[lib.scala 661:17] + node _T_725 = bits(twos_comp_in, 19, 0) @[lib.scala 661:27] + node _T_726 = orr(_T_725) @[lib.scala 661:35] + node _T_727 = bits(twos_comp_in, 20, 20) @[lib.scala 661:44] + node _T_728 = not(_T_727) @[lib.scala 661:40] + node _T_729 = bits(twos_comp_in, 20, 20) @[lib.scala 661:51] + node _T_730 = mux(_T_726, _T_728, _T_729) @[lib.scala 661:23] + _T_610[19] <= _T_730 @[lib.scala 661:17] + node _T_731 = bits(twos_comp_in, 20, 0) @[lib.scala 661:27] + node _T_732 = orr(_T_731) @[lib.scala 661:35] + node _T_733 = bits(twos_comp_in, 21, 21) @[lib.scala 661:44] + node _T_734 = not(_T_733) @[lib.scala 661:40] + node _T_735 = bits(twos_comp_in, 21, 21) @[lib.scala 661:51] + node _T_736 = mux(_T_732, _T_734, _T_735) @[lib.scala 661:23] + _T_610[20] <= _T_736 @[lib.scala 661:17] + node _T_737 = bits(twos_comp_in, 21, 0) @[lib.scala 661:27] + node _T_738 = orr(_T_737) @[lib.scala 661:35] + node _T_739 = bits(twos_comp_in, 22, 22) @[lib.scala 661:44] + node _T_740 = not(_T_739) @[lib.scala 661:40] + node _T_741 = bits(twos_comp_in, 22, 22) @[lib.scala 661:51] + node _T_742 = mux(_T_738, _T_740, _T_741) @[lib.scala 661:23] + _T_610[21] <= _T_742 @[lib.scala 661:17] + node _T_743 = bits(twos_comp_in, 22, 0) @[lib.scala 661:27] + node _T_744 = orr(_T_743) @[lib.scala 661:35] + node _T_745 = bits(twos_comp_in, 23, 23) @[lib.scala 661:44] + node _T_746 = not(_T_745) @[lib.scala 661:40] + node _T_747 = bits(twos_comp_in, 23, 23) @[lib.scala 661:51] + node _T_748 = mux(_T_744, _T_746, _T_747) @[lib.scala 661:23] + _T_610[22] <= _T_748 @[lib.scala 661:17] + node _T_749 = bits(twos_comp_in, 23, 0) @[lib.scala 661:27] + node _T_750 = orr(_T_749) @[lib.scala 661:35] + node _T_751 = bits(twos_comp_in, 24, 24) @[lib.scala 661:44] + node _T_752 = not(_T_751) @[lib.scala 661:40] + node _T_753 = bits(twos_comp_in, 24, 24) @[lib.scala 661:51] + node _T_754 = mux(_T_750, _T_752, _T_753) @[lib.scala 661:23] + _T_610[23] <= _T_754 @[lib.scala 661:17] + node _T_755 = bits(twos_comp_in, 24, 0) @[lib.scala 661:27] + node _T_756 = orr(_T_755) @[lib.scala 661:35] + node _T_757 = bits(twos_comp_in, 25, 25) @[lib.scala 661:44] + node _T_758 = not(_T_757) @[lib.scala 661:40] + node _T_759 = bits(twos_comp_in, 25, 25) @[lib.scala 661:51] + node _T_760 = mux(_T_756, _T_758, _T_759) @[lib.scala 661:23] + _T_610[24] <= _T_760 @[lib.scala 661:17] + node _T_761 = bits(twos_comp_in, 25, 0) @[lib.scala 661:27] + node _T_762 = orr(_T_761) @[lib.scala 661:35] + node _T_763 = bits(twos_comp_in, 26, 26) @[lib.scala 661:44] + node _T_764 = not(_T_763) @[lib.scala 661:40] + node _T_765 = bits(twos_comp_in, 26, 26) @[lib.scala 661:51] + node _T_766 = mux(_T_762, _T_764, _T_765) @[lib.scala 661:23] + _T_610[25] <= _T_766 @[lib.scala 661:17] + node _T_767 = bits(twos_comp_in, 26, 0) @[lib.scala 661:27] + node _T_768 = orr(_T_767) @[lib.scala 661:35] + node _T_769 = bits(twos_comp_in, 27, 27) @[lib.scala 661:44] + node _T_770 = not(_T_769) @[lib.scala 661:40] + node _T_771 = bits(twos_comp_in, 27, 27) @[lib.scala 661:51] + node _T_772 = mux(_T_768, _T_770, _T_771) @[lib.scala 661:23] + _T_610[26] <= _T_772 @[lib.scala 661:17] + node _T_773 = bits(twos_comp_in, 27, 0) @[lib.scala 661:27] + node _T_774 = orr(_T_773) @[lib.scala 661:35] + node _T_775 = bits(twos_comp_in, 28, 28) @[lib.scala 661:44] + node _T_776 = not(_T_775) @[lib.scala 661:40] + node _T_777 = bits(twos_comp_in, 28, 28) @[lib.scala 661:51] + node _T_778 = mux(_T_774, _T_776, _T_777) @[lib.scala 661:23] + _T_610[27] <= _T_778 @[lib.scala 661:17] + node _T_779 = bits(twos_comp_in, 28, 0) @[lib.scala 661:27] + node _T_780 = orr(_T_779) @[lib.scala 661:35] + node _T_781 = bits(twos_comp_in, 29, 29) @[lib.scala 661:44] + node _T_782 = not(_T_781) @[lib.scala 661:40] + node _T_783 = bits(twos_comp_in, 29, 29) @[lib.scala 661:51] + node _T_784 = mux(_T_780, _T_782, _T_783) @[lib.scala 661:23] + _T_610[28] <= _T_784 @[lib.scala 661:17] + node _T_785 = bits(twos_comp_in, 29, 0) @[lib.scala 661:27] + node _T_786 = orr(_T_785) @[lib.scala 661:35] + node _T_787 = bits(twos_comp_in, 30, 30) @[lib.scala 661:44] + node _T_788 = not(_T_787) @[lib.scala 661:40] + node _T_789 = bits(twos_comp_in, 30, 30) @[lib.scala 661:51] + node _T_790 = mux(_T_786, _T_788, _T_789) @[lib.scala 661:23] + _T_610[29] <= _T_790 @[lib.scala 661:17] + node _T_791 = bits(twos_comp_in, 30, 0) @[lib.scala 661:27] + node _T_792 = orr(_T_791) @[lib.scala 661:35] + node _T_793 = bits(twos_comp_in, 31, 31) @[lib.scala 661:44] + node _T_794 = not(_T_793) @[lib.scala 661:40] + node _T_795 = bits(twos_comp_in, 31, 31) @[lib.scala 661:51] + node _T_796 = mux(_T_792, _T_794, _T_795) @[lib.scala 661:23] + _T_610[30] <= _T_796 @[lib.scala 661:17] + node _T_797 = cat(_T_610[2], _T_610[1]) @[lib.scala 663:14] + node _T_798 = cat(_T_797, _T_610[0]) @[lib.scala 663:14] + node _T_799 = cat(_T_610[4], _T_610[3]) @[lib.scala 663:14] + node _T_800 = cat(_T_610[6], _T_610[5]) @[lib.scala 663:14] + node _T_801 = cat(_T_800, _T_799) @[lib.scala 663:14] + node _T_802 = cat(_T_801, _T_798) @[lib.scala 663:14] + node _T_803 = cat(_T_610[8], _T_610[7]) @[lib.scala 663:14] + node _T_804 = cat(_T_610[10], _T_610[9]) @[lib.scala 663:14] + node _T_805 = cat(_T_804, _T_803) @[lib.scala 663:14] + node _T_806 = cat(_T_610[12], _T_610[11]) @[lib.scala 663:14] + node _T_807 = cat(_T_610[14], _T_610[13]) @[lib.scala 663:14] + node _T_808 = cat(_T_807, _T_806) @[lib.scala 663:14] + node _T_809 = cat(_T_808, _T_805) @[lib.scala 663:14] + node _T_810 = cat(_T_809, _T_802) @[lib.scala 663:14] + node _T_811 = cat(_T_610[16], _T_610[15]) @[lib.scala 663:14] + node _T_812 = cat(_T_610[18], _T_610[17]) @[lib.scala 663:14] + node _T_813 = cat(_T_812, _T_811) @[lib.scala 663:14] + node _T_814 = cat(_T_610[20], _T_610[19]) @[lib.scala 663:14] + node _T_815 = cat(_T_610[22], _T_610[21]) @[lib.scala 663:14] + node _T_816 = cat(_T_815, _T_814) @[lib.scala 663:14] + node _T_817 = cat(_T_816, _T_813) @[lib.scala 663:14] + node _T_818 = cat(_T_610[24], _T_610[23]) @[lib.scala 663:14] + node _T_819 = cat(_T_610[26], _T_610[25]) @[lib.scala 663:14] + node _T_820 = cat(_T_819, _T_818) @[lib.scala 663:14] + node _T_821 = cat(_T_610[28], _T_610[27]) @[lib.scala 663:14] + node _T_822 = cat(_T_610[30], _T_610[29]) @[lib.scala 663:14] + node _T_823 = cat(_T_822, _T_821) @[lib.scala 663:14] + node _T_824 = cat(_T_823, _T_820) @[lib.scala 663:14] + node _T_825 = cat(_T_824, _T_817) @[lib.scala 663:14] + node _T_826 = cat(_T_825, _T_810) @[lib.scala 663:14] + node _T_827 = bits(twos_comp_in, 0, 0) @[lib.scala 663:24] node twos_comp_out = cat(_T_826, _T_827) @[Cat.scala 29:58] node _T_828 = eq(a_shift, UInt<1>("h00")) @[exu_div_ctl.scala 847:6] node _T_829 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 847:17] @@ -44382,123 +44386,123 @@ circuit exu : node _T_1517 = cat(_T_1516, _T_1511) @[Cat.scala 29:58] node _T_1518 = cat(_T_1517, _T_1515) @[Cat.scala 29:58] b_ff <= _T_1518 @[exu_div_ctl.scala 927:23] - inst rvclkhdr of rvclkhdr_14 @[lib.scala 399:23] + inst rvclkhdr of rvclkhdr_14 @[lib.scala 404:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset - rvclkhdr.io.clk <= clock @[lib.scala 401:18] - rvclkhdr.io.en <= misc_enable @[lib.scala 402:17] - rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] + rvclkhdr.io.clk <= clock @[lib.scala 406:18] + rvclkhdr.io.en <= misc_enable @[lib.scala 407:17] + rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] reg _T_1519 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when misc_enable : @[Reg.scala 28:19] _T_1519 <= valid_ff_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] valid_ff <= _T_1519 @[exu_div_ctl.scala 928:23] - inst rvclkhdr_1 of rvclkhdr_15 @[lib.scala 399:23] + inst rvclkhdr_1 of rvclkhdr_15 @[lib.scala 404:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset - rvclkhdr_1.io.clk <= clock @[lib.scala 401:18] - rvclkhdr_1.io.en <= misc_enable @[lib.scala 402:17] - rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] + rvclkhdr_1.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_1.io.en <= misc_enable @[lib.scala 407:17] + rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] reg _T_1520 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when misc_enable : @[Reg.scala 28:19] _T_1520 <= control_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] control_ff <= _T_1520 @[exu_div_ctl.scala 929:23] - inst rvclkhdr_2 of rvclkhdr_16 @[lib.scala 399:23] + inst rvclkhdr_2 of rvclkhdr_16 @[lib.scala 404:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset - rvclkhdr_2.io.clk <= clock @[lib.scala 401:18] - rvclkhdr_2.io.en <= misc_enable @[lib.scala 402:17] - rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] + rvclkhdr_2.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_2.io.en <= misc_enable @[lib.scala 407:17] + rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] reg _T_1521 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when misc_enable : @[Reg.scala 28:19] _T_1521 <= by_zero_case @[Reg.scala 28:23] skip @[Reg.scala 28:19] by_zero_case_ff <= _T_1521 @[exu_div_ctl.scala 930:23] - inst rvclkhdr_3 of rvclkhdr_17 @[lib.scala 399:23] + inst rvclkhdr_3 of rvclkhdr_17 @[lib.scala 404:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset - rvclkhdr_3.io.clk <= clock @[lib.scala 401:18] - rvclkhdr_3.io.en <= misc_enable @[lib.scala 402:17] - rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] + rvclkhdr_3.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_3.io.en <= misc_enable @[lib.scala 407:17] + rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] reg _T_1522 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when misc_enable : @[Reg.scala 28:19] _T_1522 <= shortq_enable @[Reg.scala 28:23] skip @[Reg.scala 28:19] shortq_enable_ff <= _T_1522 @[exu_div_ctl.scala 931:23] - inst rvclkhdr_4 of rvclkhdr_18 @[lib.scala 399:23] + inst rvclkhdr_4 of rvclkhdr_18 @[lib.scala 404:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset - rvclkhdr_4.io.clk <= clock @[lib.scala 401:18] - rvclkhdr_4.io.en <= misc_enable @[lib.scala 402:17] - rvclkhdr_4.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] + rvclkhdr_4.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_4.io.en <= misc_enable @[lib.scala 407:17] + rvclkhdr_4.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] reg _T_1523 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when misc_enable : @[Reg.scala 28:19] _T_1523 <= shortq_shift @[Reg.scala 28:23] skip @[Reg.scala 28:19] shortq_shift_ff <= _T_1523 @[exu_div_ctl.scala 932:23] - inst rvclkhdr_5 of rvclkhdr_19 @[lib.scala 399:23] + inst rvclkhdr_5 of rvclkhdr_19 @[lib.scala 404:23] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset - rvclkhdr_5.io.clk <= clock @[lib.scala 401:18] - rvclkhdr_5.io.en <= misc_enable @[lib.scala 402:17] - rvclkhdr_5.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] + rvclkhdr_5.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_5.io.en <= misc_enable @[lib.scala 407:17] + rvclkhdr_5.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] reg _T_1524 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when misc_enable : @[Reg.scala 28:19] _T_1524 <= finish @[Reg.scala 28:23] skip @[Reg.scala 28:19] finish_ff <= _T_1524 @[exu_div_ctl.scala 933:23] - inst rvclkhdr_6 of rvclkhdr_20 @[lib.scala 399:23] + inst rvclkhdr_6 of rvclkhdr_20 @[lib.scala 404:23] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset - rvclkhdr_6.io.clk <= clock @[lib.scala 401:18] - rvclkhdr_6.io.en <= misc_enable @[lib.scala 402:17] - rvclkhdr_6.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] + rvclkhdr_6.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_6.io.en <= misc_enable @[lib.scala 407:17] + rvclkhdr_6.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] reg _T_1525 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when misc_enable : @[Reg.scala 28:19] _T_1525 <= count_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] count_ff <= _T_1525 @[exu_div_ctl.scala 934:23] - inst rvclkhdr_7 of rvclkhdr_21 @[lib.scala 399:23] + inst rvclkhdr_7 of rvclkhdr_21 @[lib.scala 404:23] rvclkhdr_7.clock <= clock rvclkhdr_7.reset <= reset - rvclkhdr_7.io.clk <= clock @[lib.scala 401:18] - rvclkhdr_7.io.en <= a_enable @[lib.scala 402:17] - rvclkhdr_7.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] + rvclkhdr_7.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_7.io.en <= a_enable @[lib.scala 407:17] + rvclkhdr_7.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] reg _T_1526 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when a_enable : @[Reg.scala 28:19] _T_1526 <= a_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] a_ff <= _T_1526 @[exu_div_ctl.scala 936:23] node _T_1527 = bits(b_in, 32, 0) @[exu_div_ctl.scala 937:37] - inst rvclkhdr_8 of rvclkhdr_22 @[lib.scala 399:23] + inst rvclkhdr_8 of rvclkhdr_22 @[lib.scala 404:23] rvclkhdr_8.clock <= clock rvclkhdr_8.reset <= reset - rvclkhdr_8.io.clk <= clock @[lib.scala 401:18] - rvclkhdr_8.io.en <= b_enable @[lib.scala 402:17] - rvclkhdr_8.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] + rvclkhdr_8.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_8.io.en <= b_enable @[lib.scala 407:17] + rvclkhdr_8.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] reg _T_1528 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when b_enable : @[Reg.scala 28:19] _T_1528 <= _T_1527 @[Reg.scala 28:23] skip @[Reg.scala 28:19] b_ff1 <= _T_1528 @[exu_div_ctl.scala 937:23] - inst rvclkhdr_9 of rvclkhdr_23 @[lib.scala 399:23] + inst rvclkhdr_9 of rvclkhdr_23 @[lib.scala 404:23] rvclkhdr_9.clock <= clock rvclkhdr_9.reset <= reset - rvclkhdr_9.io.clk <= clock @[lib.scala 401:18] - rvclkhdr_9.io.en <= rq_enable @[lib.scala 402:17] - rvclkhdr_9.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] + rvclkhdr_9.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_9.io.en <= rq_enable @[lib.scala 407:17] + rvclkhdr_9.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] reg _T_1529 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when rq_enable : @[Reg.scala 28:19] _T_1529 <= r_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] r_ff <= _T_1529 @[exu_div_ctl.scala 938:23] - inst rvclkhdr_10 of rvclkhdr_24 @[lib.scala 399:23] + inst rvclkhdr_10 of rvclkhdr_24 @[lib.scala 404:23] rvclkhdr_10.clock <= clock rvclkhdr_10.reset <= reset - rvclkhdr_10.io.clk <= clock @[lib.scala 401:18] - rvclkhdr_10.io.en <= rq_enable @[lib.scala 402:17] - rvclkhdr_10.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] + rvclkhdr_10.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_10.io.en <= rq_enable @[lib.scala 407:17] + rvclkhdr_10.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] reg _T_1530 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when rq_enable : @[Reg.scala 28:19] _T_1530 <= q_in @[Reg.scala 28:23] @@ -44569,29 +44573,29 @@ circuit exu : node _T_3 = cat(io.dec_exu.decode_exu.i0_predict_fghr_d, io.dec_exu.decode_exu.i0_predict_index_d) @[Cat.scala 29:58] node predpipe_d = cat(_T_3, io.dec_exu.decode_exu.i0_predict_btag_d) @[Cat.scala 29:58] node _T_4 = bits(x_data_en, 0, 0) @[exu.scala 63:68] - wire _T_5 : UInt<31> @[lib.scala 636:38] - _T_5 <= UInt<1>("h00") @[lib.scala 636:38] + wire _T_5 : UInt<31> @[lib.scala 648:38] + _T_5 <= UInt<1>("h00") @[lib.scala 648:38] reg i0_flush_path_x : UInt, clock with : (reset => (reset, _T_5)) @[Reg.scala 27:20] when _T_4 : @[Reg.scala 28:19] i0_flush_path_x <= i0_flush_path_d @[Reg.scala 28:23] skip @[Reg.scala 28:19] node _T_6 = bits(x_data_en, 0, 0) @[exu.scala 64:116] node _T_7 = bits(io.exu_bp.exu_mp_pkt.bits.pret, 0, 0) @[lib.scala 8:44] - wire _T_8 : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[lib.scala 586:37] - _T_8.bits.prett <= UInt<31>("h00") @[lib.scala 586:37] - _T_8.bits.pret <= UInt<1>("h00") @[lib.scala 586:37] - _T_8.bits.way <= UInt<1>("h00") @[lib.scala 586:37] - _T_8.bits.pja <= UInt<1>("h00") @[lib.scala 586:37] - _T_8.bits.pcall <= UInt<1>("h00") @[lib.scala 586:37] - _T_8.bits.br_start_error <= UInt<1>("h00") @[lib.scala 586:37] - _T_8.bits.br_error <= UInt<1>("h00") @[lib.scala 586:37] - _T_8.bits.toffset <= UInt<12>("h00") @[lib.scala 586:37] - _T_8.bits.hist <= UInt<2>("h00") @[lib.scala 586:37] - _T_8.bits.pc4 <= UInt<1>("h00") @[lib.scala 586:37] - _T_8.bits.boffset <= UInt<1>("h00") @[lib.scala 586:37] - _T_8.bits.ataken <= UInt<1>("h00") @[lib.scala 586:37] - _T_8.bits.misp <= UInt<1>("h00") @[lib.scala 586:37] - _T_8.valid <= UInt<1>("h00") @[lib.scala 586:37] + wire _T_8 : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[lib.scala 598:37] + _T_8.bits.prett <= UInt<31>("h00") @[lib.scala 598:37] + _T_8.bits.pret <= UInt<1>("h00") @[lib.scala 598:37] + _T_8.bits.way <= UInt<1>("h00") @[lib.scala 598:37] + _T_8.bits.pja <= UInt<1>("h00") @[lib.scala 598:37] + _T_8.bits.pcall <= UInt<1>("h00") @[lib.scala 598:37] + _T_8.bits.br_start_error <= UInt<1>("h00") @[lib.scala 598:37] + _T_8.bits.br_error <= UInt<1>("h00") @[lib.scala 598:37] + _T_8.bits.toffset <= UInt<12>("h00") @[lib.scala 598:37] + _T_8.bits.hist <= UInt<2>("h00") @[lib.scala 598:37] + _T_8.bits.pc4 <= UInt<1>("h00") @[lib.scala 598:37] + _T_8.bits.boffset <= UInt<1>("h00") @[lib.scala 598:37] + _T_8.bits.ataken <= UInt<1>("h00") @[lib.scala 598:37] + _T_8.bits.misp <= UInt<1>("h00") @[lib.scala 598:37] + _T_8.valid <= UInt<1>("h00") @[lib.scala 598:37] reg _T_9 : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}}, clock with : (reset => (reset, _T_8)) @[Reg.scala 27:20] when _T_6 : @[Reg.scala 28:19] _T_9.bits.prett <= i0_predict_p_d.bits.prett @[Reg.scala 28:23] @@ -44624,99 +44628,99 @@ circuit exu : i0_predict_p_x.bits.misp <= _T_9.bits.misp @[exu.scala 64:55] i0_predict_p_x.valid <= _T_9.valid @[exu.scala 64:55] node _T_10 = bits(x_data_en_q2, 0, 0) @[exu.scala 65:79] - inst rvclkhdr of rvclkhdr @[lib.scala 399:23] + inst rvclkhdr of rvclkhdr @[lib.scala 404:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset - rvclkhdr.io.clk <= clock @[lib.scala 401:18] - rvclkhdr.io.en <= _T_10 @[lib.scala 402:17] - rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] + rvclkhdr.io.clk <= clock @[lib.scala 406:18] + rvclkhdr.io.en <= _T_10 @[lib.scala 407:17] + rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] reg predpipe_x : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_10 : @[Reg.scala 28:19] predpipe_x <= predpipe_d @[Reg.scala 28:23] skip @[Reg.scala 28:19] node _T_11 = bits(r_data_en_q2, 0, 0) @[exu.scala 66:88] - inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 399:23] + inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 404:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset - rvclkhdr_1.io.clk <= clock @[lib.scala 401:18] - rvclkhdr_1.io.en <= _T_11 @[lib.scala 402:17] - rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] + rvclkhdr_1.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_1.io.en <= _T_11 @[lib.scala 407:17] + rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] reg predpipe_r : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_11 : @[Reg.scala 28:19] predpipe_r <= predpipe_x @[Reg.scala 28:23] skip @[Reg.scala 28:19] node _T_12 = bits(x_ctl_en, 0, 0) @[exu.scala 67:86] - inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 399:23] + inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 404:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset - rvclkhdr_2.io.clk <= clock @[lib.scala 401:18] - rvclkhdr_2.io.en <= _T_12 @[lib.scala 402:17] - rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] + rvclkhdr_2.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_2.io.en <= _T_12 @[lib.scala 407:17] + rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] reg ghr_x : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_12 : @[Reg.scala 28:19] ghr_x <= ghr_x_ns @[Reg.scala 28:23] skip @[Reg.scala 28:19] node _T_13 = bits(x_ctl_en, 0, 0) @[exu.scala 68:75] - inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 399:23] + inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 404:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset - rvclkhdr_3.io.clk <= clock @[lib.scala 401:18] - rvclkhdr_3.io.en <= _T_13 @[lib.scala 402:17] - rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] + rvclkhdr_3.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_3.io.en <= _T_13 @[lib.scala 407:17] + rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] reg i0_pred_correct_upper_x : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_13 : @[Reg.scala 28:19] i0_pred_correct_upper_x <= i0_pred_correct_upper_d @[Reg.scala 28:23] skip @[Reg.scala 28:19] node _T_14 = bits(x_ctl_en, 0, 0) @[exu.scala 69:66] - inst rvclkhdr_4 of rvclkhdr_4 @[lib.scala 399:23] + inst rvclkhdr_4 of rvclkhdr_4 @[lib.scala 404:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset - rvclkhdr_4.io.clk <= clock @[lib.scala 401:18] - rvclkhdr_4.io.en <= _T_14 @[lib.scala 402:17] - rvclkhdr_4.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] + rvclkhdr_4.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_4.io.en <= _T_14 @[lib.scala 407:17] + rvclkhdr_4.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] reg i0_flush_upper_x : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_14 : @[Reg.scala 28:19] i0_flush_upper_x <= i0_flush_upper_d @[Reg.scala 28:23] skip @[Reg.scala 28:19] node _T_15 = bits(x_ctl_en, 0, 0) @[exu.scala 70:84] - inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 399:23] + inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 404:23] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset - rvclkhdr_5.io.clk <= clock @[lib.scala 401:18] - rvclkhdr_5.io.en <= _T_15 @[lib.scala 402:17] - rvclkhdr_5.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] + rvclkhdr_5.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_5.io.en <= _T_15 @[lib.scala 407:17] + rvclkhdr_5.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] reg i0_taken_x : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_15 : @[Reg.scala 28:19] i0_taken_x <= i0_taken_d @[Reg.scala 28:23] skip @[Reg.scala 28:19] node _T_16 = bits(x_ctl_en, 0, 0) @[exu.scala 71:84] - inst rvclkhdr_6 of rvclkhdr_6 @[lib.scala 399:23] + inst rvclkhdr_6 of rvclkhdr_6 @[lib.scala 404:23] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset - rvclkhdr_6.io.clk <= clock @[lib.scala 401:18] - rvclkhdr_6.io.en <= _T_16 @[lib.scala 402:17] - rvclkhdr_6.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] + rvclkhdr_6.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_6.io.en <= _T_16 @[lib.scala 407:17] + rvclkhdr_6.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] reg i0_valid_x : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_16 : @[Reg.scala 28:19] i0_valid_x <= i0_valid_d @[Reg.scala 28:23] skip @[Reg.scala 28:19] node _T_17 = bits(r_ctl_en, 0, 0) @[exu.scala 72:93] node _T_18 = bits(io.exu_bp.exu_mp_pkt.bits.pret, 0, 0) @[lib.scala 8:44] - wire _T_19 : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[lib.scala 586:37] - _T_19.bits.prett <= UInt<31>("h00") @[lib.scala 586:37] - _T_19.bits.pret <= UInt<1>("h00") @[lib.scala 586:37] - _T_19.bits.way <= UInt<1>("h00") @[lib.scala 586:37] - _T_19.bits.pja <= UInt<1>("h00") @[lib.scala 586:37] - _T_19.bits.pcall <= UInt<1>("h00") @[lib.scala 586:37] - _T_19.bits.br_start_error <= UInt<1>("h00") @[lib.scala 586:37] - _T_19.bits.br_error <= UInt<1>("h00") @[lib.scala 586:37] - _T_19.bits.toffset <= UInt<12>("h00") @[lib.scala 586:37] - _T_19.bits.hist <= UInt<2>("h00") @[lib.scala 586:37] - _T_19.bits.pc4 <= UInt<1>("h00") @[lib.scala 586:37] - _T_19.bits.boffset <= UInt<1>("h00") @[lib.scala 586:37] - _T_19.bits.ataken <= UInt<1>("h00") @[lib.scala 586:37] - _T_19.bits.misp <= UInt<1>("h00") @[lib.scala 586:37] - _T_19.valid <= UInt<1>("h00") @[lib.scala 586:37] + wire _T_19 : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[lib.scala 598:37] + _T_19.bits.prett <= UInt<31>("h00") @[lib.scala 598:37] + _T_19.bits.pret <= UInt<1>("h00") @[lib.scala 598:37] + _T_19.bits.way <= UInt<1>("h00") @[lib.scala 598:37] + _T_19.bits.pja <= UInt<1>("h00") @[lib.scala 598:37] + _T_19.bits.pcall <= UInt<1>("h00") @[lib.scala 598:37] + _T_19.bits.br_start_error <= UInt<1>("h00") @[lib.scala 598:37] + _T_19.bits.br_error <= UInt<1>("h00") @[lib.scala 598:37] + _T_19.bits.toffset <= UInt<12>("h00") @[lib.scala 598:37] + _T_19.bits.hist <= UInt<2>("h00") @[lib.scala 598:37] + _T_19.bits.pc4 <= UInt<1>("h00") @[lib.scala 598:37] + _T_19.bits.boffset <= UInt<1>("h00") @[lib.scala 598:37] + _T_19.bits.ataken <= UInt<1>("h00") @[lib.scala 598:37] + _T_19.bits.misp <= UInt<1>("h00") @[lib.scala 598:37] + _T_19.valid <= UInt<1>("h00") @[lib.scala 598:37] reg _T_20 : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}}, clock with : (reset => (reset, _T_19)) @[Reg.scala 27:20] when _T_17 : @[Reg.scala 28:19] _T_20.bits.prett <= i0_predict_p_x.bits.prett @[Reg.scala 28:23] @@ -44750,30 +44754,30 @@ circuit exu : i0_pp_r.valid <= _T_20.valid @[exu.scala 72:31] node _T_21 = bits(io.dec_exu.decode_exu.pred_correct_npc_x, 5, 0) @[exu.scala 73:94] node _T_22 = bits(r_data_en, 0, 0) @[exu.scala 73:111] - wire _T_23 : UInt<6> @[lib.scala 636:38] - _T_23 <= UInt<1>("h00") @[lib.scala 636:38] + wire _T_23 : UInt<6> @[lib.scala 648:38] + _T_23 <= UInt<1>("h00") @[lib.scala 648:38] reg pred_temp1 : UInt, clock with : (reset => (reset, _T_23)) @[Reg.scala 27:20] when _T_22 : @[Reg.scala 28:19] pred_temp1 <= _T_21 @[Reg.scala 28:23] skip @[Reg.scala 28:19] node _T_24 = bits(r_ctl_en, 0, 0) @[exu.scala 74:109] - wire _T_25 : UInt @[lib.scala 576:35] - _T_25 <= UInt<1>("h00") @[lib.scala 576:35] + wire _T_25 : UInt @[lib.scala 588:35] + _T_25 <= UInt<1>("h00") @[lib.scala 588:35] reg i0_pred_correct_upper_r : UInt, clock with : (reset => (reset, _T_25)) @[Reg.scala 27:20] when _T_24 : @[Reg.scala 28:19] i0_pred_correct_upper_r <= i0_pred_correct_upper_x @[Reg.scala 28:23] skip @[Reg.scala 28:19] node _T_26 = bits(r_data_en, 0, 0) @[exu.scala 75:73] - wire _T_27 : UInt @[lib.scala 636:38] - _T_27 <= UInt<1>("h00") @[lib.scala 636:38] + wire _T_27 : UInt @[lib.scala 648:38] + _T_27 <= UInt<1>("h00") @[lib.scala 648:38] reg i0_flush_path_upper_r : UInt, clock with : (reset => (reset, _T_27)) @[Reg.scala 27:20] when _T_26 : @[Reg.scala 28:19] i0_flush_path_upper_r <= i0_flush_path_x @[Reg.scala 28:23] skip @[Reg.scala 28:19] node _T_28 = bits(io.dec_exu.decode_exu.pred_correct_npc_x, 30, 6) @[exu.scala 76:106] node _T_29 = bits(r_data_en, 0, 0) @[exu.scala 76:124] - wire _T_30 : UInt<25> @[lib.scala 636:38] - _T_30 <= UInt<1>("h00") @[lib.scala 636:38] + wire _T_30 : UInt<25> @[lib.scala 648:38] + _T_30 <= UInt<1>("h00") @[lib.scala 648:38] reg pred_temp2 : UInt, clock with : (reset => (reset, _T_30)) @[Reg.scala 27:20] when _T_29 : @[Reg.scala 28:19] pred_temp2 <= _T_28 @[Reg.scala 28:23] @@ -44782,33 +44786,33 @@ circuit exu : pred_correct_npc_r <= _T_31 @[exu.scala 77:45] wire _T_32 : UInt _T_32 <= UInt<1>("h00") - node _T_33 = xor(ghr_d_ns, _T_32) @[lib.scala 436:21] - node _T_34 = orr(_T_33) @[lib.scala 436:29] + node _T_33 = xor(ghr_d_ns, _T_32) @[lib.scala 448:21] + node _T_34 = orr(_T_33) @[lib.scala 448:29] reg _T_35 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_34 : @[Reg.scala 28:19] _T_35 <= ghr_d_ns @[Reg.scala 28:23] skip @[Reg.scala 28:19] - _T_32 <= _T_35 @[lib.scala 439:16] + _T_32 <= _T_35 @[lib.scala 451:16] ghr_d <= _T_32 @[exu.scala 78:43] wire _T_36 : UInt<1> _T_36 <= UInt<1>("h00") - node _T_37 = xor(io.dec_exu.decode_exu.mul_p.valid, _T_36) @[lib.scala 458:21] - node _T_38 = orr(_T_37) @[lib.scala 458:29] + node _T_37 = xor(io.dec_exu.decode_exu.mul_p.valid, _T_36) @[lib.scala 470:21] + node _T_38 = orr(_T_37) @[lib.scala 470:29] reg _T_39 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_38 : @[Reg.scala 28:19] _T_39 <= io.dec_exu.decode_exu.mul_p.valid @[Reg.scala 28:23] skip @[Reg.scala 28:19] - _T_36 <= _T_39 @[lib.scala 461:16] + _T_36 <= _T_39 @[lib.scala 473:16] mul_valid_x <= _T_36 @[exu.scala 79:39] wire _T_40 : UInt _T_40 <= UInt<1>("h00") - node _T_41 = xor(io.dec_exu.decode_exu.dec_i0_branch_d, _T_40) @[lib.scala 436:21] - node _T_42 = orr(_T_41) @[lib.scala 436:29] + node _T_41 = xor(io.dec_exu.decode_exu.dec_i0_branch_d, _T_40) @[lib.scala 448:21] + node _T_42 = orr(_T_41) @[lib.scala 448:29] reg _T_43 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_42 : @[Reg.scala 28:19] _T_43 <= io.dec_exu.decode_exu.dec_i0_branch_d @[Reg.scala 28:23] skip @[Reg.scala 28:19] - _T_40 <= _T_43 @[lib.scala 439:16] + _T_40 <= _T_43 @[lib.scala 451:16] i0_branch_x <= _T_40 @[exu.scala 80:39] node _T_44 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 0, 0) @[exu.scala 82:80] node _T_45 = bits(io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d, 1, 1) @[exu.scala 82:130] @@ -44881,12 +44885,12 @@ circuit exu : wire i0_rs1_d : UInt<32> @[Mux.scala 27:72] i0_rs1_d <= _T_105 @[Mux.scala 27:72] node _T_106 = bits(x_data_en_q1, 0, 0) @[exu.scala 104:88] - inst rvclkhdr_7 of rvclkhdr_7 @[lib.scala 399:23] + inst rvclkhdr_7 of rvclkhdr_7 @[lib.scala 404:23] rvclkhdr_7.clock <= clock rvclkhdr_7.reset <= reset - rvclkhdr_7.io.clk <= clock @[lib.scala 401:18] - rvclkhdr_7.io.en <= _T_106 @[lib.scala 402:17] - rvclkhdr_7.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] + rvclkhdr_7.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_7.io.en <= _T_106 @[lib.scala 407:17] + rvclkhdr_7.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] reg _T_107 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_106 : @[Reg.scala 28:19] _T_107 <= i0_rs1_d @[Reg.scala 28:23] diff --git a/exu.v b/exu.v index 90298d50..6d709859 100644 --- a/exu.v +++ b/exu.v @@ -1,5 +1,4 @@ module rvclkhdr( - output io_l1clk, input io_clk, input io_en ); @@ -13,7 +12,6 @@ module rvclkhdr( .EN(clkhdr_EN), .SE(clkhdr_SE) ); - assign io_l1clk = clkhdr_Q; // @[lib.scala 335:14] assign clkhdr_CK = io_clk; // @[lib.scala 336:18] assign clkhdr_EN = io_en; // @[lib.scala 337:18] assign clkhdr_SE = 1'h0; // @[lib.scala 338:18] @@ -105,9 +103,8 @@ module exu_alu_ctl( reg [31:0] _RAND_0; reg [31:0] _RAND_1; `endif // RANDOMIZE_REG_INIT - wire rvclkhdr_io_l1clk; // @[lib.scala 399:23] - wire rvclkhdr_io_clk; // @[lib.scala 399:23] - wire rvclkhdr_io_en; // @[lib.scala 399:23] + wire rvclkhdr_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_io_en; // @[lib.scala 404:23] wire _T_1 = io_b_in[4:0] == 5'h1f; // @[exu_alu_ctl.scala 87:55] wire ap_rev = io_i0_ap_grev & _T_1; // @[exu_alu_ctl.scala 87:39] wire _T_4 = io_b_in[4:0] == 5'h18; // @[exu_alu_ctl.scala 88:55] @@ -480,8 +477,7 @@ module exu_alu_ctl( wire _T_993 = _T_990 | _T_992; // @[exu_alu_ctl.scala 356:47] wire _T_997 = _T_970 & _T_972; // @[exu_alu_ctl.scala 359:56] wire _T_998 = cond_mispredict | target_mispredict; // @[exu_alu_ctl.scala 359:103] - rvclkhdr rvclkhdr ( // @[lib.scala 399:23] - .io_l1clk(rvclkhdr_io_l1clk), + rvclkhdr rvclkhdr ( // @[lib.scala 404:23] .io_clk(rvclkhdr_io_clk), .io_en(rvclkhdr_io_en) ); @@ -504,8 +500,8 @@ module exu_alu_ctl( assign io_predict_p_out_bits_pja = io_pp_in_bits_pja; // @[exu_alu_ctl.scala 358:30] assign io_predict_p_out_bits_way = io_pp_in_bits_way; // @[exu_alu_ctl.scala 358:30] assign io_predict_p_out_bits_pret = io_pp_in_bits_pret; // @[exu_alu_ctl.scala 358:30] - assign rvclkhdr_io_clk = clock; // @[lib.scala 401:18] - assign rvclkhdr_io_en = io_enable & io_dec_alu_dec_i0_alu_decode_d; // @[lib.scala 402:17] + assign rvclkhdr_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_io_en = io_enable & io_dec_alu_dec_i0_alu_decode_d; // @[lib.scala 407:17] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -589,26 +585,23 @@ module exu_mul_ctl( reg [63:0] _RAND_1; reg [63:0] _RAND_2; `endif // RANDOMIZE_REG_INIT - wire rvclkhdr_io_l1clk; // @[lib.scala 399:23] - wire rvclkhdr_io_clk; // @[lib.scala 399:23] - wire rvclkhdr_io_en; // @[lib.scala 399:23] - wire rvclkhdr_1_io_l1clk; // @[lib.scala 422:23] - wire rvclkhdr_1_io_clk; // @[lib.scala 422:23] - wire rvclkhdr_1_io_en; // @[lib.scala 422:23] - wire rvclkhdr_2_io_l1clk; // @[lib.scala 422:23] - wire rvclkhdr_2_io_clk; // @[lib.scala 422:23] - wire rvclkhdr_2_io_en; // @[lib.scala 422:23] - wire rvclkhdr_3_io_l1clk; // @[lib.scala 399:23] - wire rvclkhdr_3_io_clk; // @[lib.scala 399:23] - wire rvclkhdr_3_io_en; // @[lib.scala 399:23] - wire rvclkhdr_4_io_l1clk; // @[lib.scala 399:23] - wire rvclkhdr_4_io_clk; // @[lib.scala 399:23] - wire rvclkhdr_4_io_en; // @[lib.scala 399:23] + wire rvclkhdr_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_io_en; // @[lib.scala 404:23] + wire rvclkhdr_1_io_clk; // @[lib.scala 431:23] + wire rvclkhdr_1_io_en; // @[lib.scala 431:23] + wire rvclkhdr_2_io_clk; // @[lib.scala 431:23] + wire rvclkhdr_2_io_en; // @[lib.scala 431:23] + wire rvclkhdr_3_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_3_io_en; // @[lib.scala 404:23] + wire rvclkhdr_4_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_4_io_en; // @[lib.scala 404:23] wire _T_1 = io_mul_p_bits_rs1_sign & io_rs1_in[31]; // @[exu_mul_ctl.scala 123:44] + wire [32:0] rs1_ext_in = {_T_1,io_rs1_in}; // @[exu_mul_ctl.scala 123:71] wire _T_5 = io_mul_p_bits_rs2_sign & io_rs2_in[31]; // @[exu_mul_ctl.scala 124:44] + wire [32:0] rs2_ext_in = {_T_5,io_rs2_in}; // @[exu_mul_ctl.scala 124:71] reg low_x; // @[Reg.scala 27:20] - reg [32:0] rs1_x; // @[lib.scala 428:16] - reg [32:0] rs2_x; // @[lib.scala 428:16] + reg [32:0] rs1_x; // @[Reg.scala 27:20] + reg [32:0] rs2_x; // @[Reg.scala 27:20] wire [65:0] prod_x = $signed(rs1_x) * $signed(rs2_x); // @[exu_mul_ctl.scala 130:20] wire _T_39758 = ~low_x; // @[exu_mul_ctl.scala 388:46] wire [7:0] _T_39762 = {_T_39758,_T_39758,_T_39758,_T_39758,_T_39758,_T_39758,_T_39758,_T_39758}; // @[Cat.scala 29:58] @@ -619,42 +612,37 @@ module exu_mul_ctl( wire [15:0] _T_39772 = {low_x,low_x,low_x,low_x,low_x,low_x,low_x,low_x,_T_39771}; // @[Cat.scala 29:58] wire [31:0] _T_39773 = {low_x,low_x,low_x,low_x,low_x,low_x,low_x,low_x,_T_39771,_T_39772}; // @[Cat.scala 29:58] wire [31:0] _T_39775 = _T_39773 & prod_x[31:0]; // @[exu_mul_ctl.scala 389:40] - rvclkhdr rvclkhdr ( // @[lib.scala 399:23] - .io_l1clk(rvclkhdr_io_l1clk), + rvclkhdr rvclkhdr ( // @[lib.scala 404:23] .io_clk(rvclkhdr_io_clk), .io_en(rvclkhdr_io_en) ); - rvclkhdr rvclkhdr_1 ( // @[lib.scala 422:23] - .io_l1clk(rvclkhdr_1_io_l1clk), + rvclkhdr rvclkhdr_1 ( // @[lib.scala 431:23] .io_clk(rvclkhdr_1_io_clk), .io_en(rvclkhdr_1_io_en) ); - rvclkhdr rvclkhdr_2 ( // @[lib.scala 422:23] - .io_l1clk(rvclkhdr_2_io_l1clk), + rvclkhdr rvclkhdr_2 ( // @[lib.scala 431:23] .io_clk(rvclkhdr_2_io_clk), .io_en(rvclkhdr_2_io_en) ); - rvclkhdr rvclkhdr_3 ( // @[lib.scala 399:23] - .io_l1clk(rvclkhdr_3_io_l1clk), + rvclkhdr rvclkhdr_3 ( // @[lib.scala 404:23] .io_clk(rvclkhdr_3_io_clk), .io_en(rvclkhdr_3_io_en) ); - rvclkhdr rvclkhdr_4 ( // @[lib.scala 399:23] - .io_l1clk(rvclkhdr_4_io_l1clk), + rvclkhdr rvclkhdr_4 ( // @[lib.scala 404:23] .io_clk(rvclkhdr_4_io_clk), .io_en(rvclkhdr_4_io_en) ); assign io_result_x = _T_39766 | _T_39775; // @[exu_mul_ctl.scala 388:15] - assign rvclkhdr_io_clk = clock; // @[lib.scala 401:18] - assign rvclkhdr_io_en = io_mul_p_valid; // @[lib.scala 402:17] - assign rvclkhdr_1_io_clk = clock; // @[lib.scala 424:18] - assign rvclkhdr_1_io_en = io_mul_p_valid; // @[lib.scala 425:17] - assign rvclkhdr_2_io_clk = clock; // @[lib.scala 424:18] - assign rvclkhdr_2_io_en = io_mul_p_valid; // @[lib.scala 425:17] - assign rvclkhdr_3_io_clk = clock; // @[lib.scala 401:18] - assign rvclkhdr_3_io_en = io_mul_p_valid; // @[lib.scala 402:17] - assign rvclkhdr_4_io_clk = clock; // @[lib.scala 401:18] - assign rvclkhdr_4_io_en = io_mul_p_valid; // @[lib.scala 402:17] + assign rvclkhdr_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_io_en = io_mul_p_valid; // @[lib.scala 407:17] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 433:18] + assign rvclkhdr_1_io_en = io_mul_p_valid; // @[lib.scala 434:17] + assign rvclkhdr_2_io_clk = clock; // @[lib.scala 433:18] + assign rvclkhdr_2_io_en = io_mul_p_valid; // @[lib.scala 434:17] + assign rvclkhdr_3_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_3_io_en = io_mul_p_valid; // @[lib.scala 407:17] + assign rvclkhdr_4_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_4_io_en = io_mul_p_valid; // @[lib.scala 407:17] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -719,18 +707,18 @@ end // initial low_x <= io_mul_p_bits_low; end end - always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin + always @(posedge clock or posedge reset) begin if (reset) begin rs1_x <= 33'sh0; - end else begin - rs1_x <= {_T_1,io_rs1_in}; + end else if (io_mul_p_valid) begin + rs1_x <= rs1_ext_in; end end - always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + always @(posedge clock or posedge reset) begin if (reset) begin rs2_x <= 33'sh0; - end else begin - rs2_x <= {_T_5,io_rs2_in}; + end else if (io_mul_p_valid) begin + rs2_x <= rs2_ext_in; end end endmodule @@ -958,39 +946,28 @@ module exu_div_new_4bit_fullshortq( wire [4:0] a_enc_io_cls; // @[exu_div_ctl.scala 913:31] wire [32:0] b_enc_io_operand; // @[exu_div_ctl.scala 916:31] wire [4:0] b_enc_io_cls; // @[exu_div_ctl.scala 916:31] - wire rvclkhdr_io_l1clk; // @[lib.scala 399:23] - wire rvclkhdr_io_clk; // @[lib.scala 399:23] - wire rvclkhdr_io_en; // @[lib.scala 399:23] - wire rvclkhdr_1_io_l1clk; // @[lib.scala 399:23] - wire rvclkhdr_1_io_clk; // @[lib.scala 399:23] - wire rvclkhdr_1_io_en; // @[lib.scala 399:23] - wire rvclkhdr_2_io_l1clk; // @[lib.scala 399:23] - wire rvclkhdr_2_io_clk; // @[lib.scala 399:23] - wire rvclkhdr_2_io_en; // @[lib.scala 399:23] - wire rvclkhdr_3_io_l1clk; // @[lib.scala 399:23] - wire rvclkhdr_3_io_clk; // @[lib.scala 399:23] - wire rvclkhdr_3_io_en; // @[lib.scala 399:23] - wire rvclkhdr_4_io_l1clk; // @[lib.scala 399:23] - wire rvclkhdr_4_io_clk; // @[lib.scala 399:23] - wire rvclkhdr_4_io_en; // @[lib.scala 399:23] - wire rvclkhdr_5_io_l1clk; // @[lib.scala 399:23] - wire rvclkhdr_5_io_clk; // @[lib.scala 399:23] - wire rvclkhdr_5_io_en; // @[lib.scala 399:23] - wire rvclkhdr_6_io_l1clk; // @[lib.scala 399:23] - wire rvclkhdr_6_io_clk; // @[lib.scala 399:23] - wire rvclkhdr_6_io_en; // @[lib.scala 399:23] - wire rvclkhdr_7_io_l1clk; // @[lib.scala 399:23] - wire rvclkhdr_7_io_clk; // @[lib.scala 399:23] - wire rvclkhdr_7_io_en; // @[lib.scala 399:23] - wire rvclkhdr_8_io_l1clk; // @[lib.scala 399:23] - wire rvclkhdr_8_io_clk; // @[lib.scala 399:23] - wire rvclkhdr_8_io_en; // @[lib.scala 399:23] - wire rvclkhdr_9_io_l1clk; // @[lib.scala 399:23] - wire rvclkhdr_9_io_clk; // @[lib.scala 399:23] - wire rvclkhdr_9_io_en; // @[lib.scala 399:23] - wire rvclkhdr_10_io_l1clk; // @[lib.scala 399:23] - wire rvclkhdr_10_io_clk; // @[lib.scala 399:23] - wire rvclkhdr_10_io_en; // @[lib.scala 399:23] + wire rvclkhdr_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_io_en; // @[lib.scala 404:23] + wire rvclkhdr_1_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_1_io_en; // @[lib.scala 404:23] + wire rvclkhdr_2_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_2_io_en; // @[lib.scala 404:23] + wire rvclkhdr_3_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_3_io_en; // @[lib.scala 404:23] + wire rvclkhdr_4_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_4_io_en; // @[lib.scala 404:23] + wire rvclkhdr_5_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_5_io_en; // @[lib.scala 404:23] + wire rvclkhdr_6_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_6_io_en; // @[lib.scala 404:23] + wire rvclkhdr_7_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_7_io_en; // @[lib.scala 404:23] + wire rvclkhdr_8_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_8_io_en; // @[lib.scala 404:23] + wire rvclkhdr_9_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_9_io_en; // @[lib.scala 404:23] + wire rvclkhdr_10_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_10_io_en; // @[lib.scala 404:23] wire _T = ~io_cancel; // @[exu_div_ctl.scala 776:44] wire valid_ff_in = io_valid_in & _T; // @[exu_div_ctl.scala 776:42] wire _T_1 = ~io_valid_in; // @[exu_div_ctl.scala 777:35] @@ -1284,103 +1261,103 @@ module exu_div_new_4bit_fullshortq( wire [31:0] _T_607 = twos_comp_q_sel ? q_ff : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_608 = b_twos_comp ? b_ff[31:0] : 32'h0; // @[Mux.scala 27:72] wire [31:0] twos_comp_in = _T_607 | _T_608; // @[Mux.scala 27:72] - wire _T_612 = |twos_comp_in[0]; // @[lib.scala 649:35] - wire _T_614 = ~twos_comp_in[1]; // @[lib.scala 649:40] - wire _T_616 = _T_612 ? _T_614 : twos_comp_in[1]; // @[lib.scala 649:23] - wire _T_618 = |twos_comp_in[1:0]; // @[lib.scala 649:35] - wire _T_620 = ~twos_comp_in[2]; // @[lib.scala 649:40] - wire _T_622 = _T_618 ? _T_620 : twos_comp_in[2]; // @[lib.scala 649:23] - wire _T_624 = |twos_comp_in[2:0]; // @[lib.scala 649:35] - wire _T_626 = ~twos_comp_in[3]; // @[lib.scala 649:40] - wire _T_628 = _T_624 ? _T_626 : twos_comp_in[3]; // @[lib.scala 649:23] - wire _T_630 = |twos_comp_in[3:0]; // @[lib.scala 649:35] - wire _T_632 = ~twos_comp_in[4]; // @[lib.scala 649:40] - wire _T_634 = _T_630 ? _T_632 : twos_comp_in[4]; // @[lib.scala 649:23] - wire _T_636 = |twos_comp_in[4:0]; // @[lib.scala 649:35] - wire _T_638 = ~twos_comp_in[5]; // @[lib.scala 649:40] - wire _T_640 = _T_636 ? _T_638 : twos_comp_in[5]; // @[lib.scala 649:23] - wire _T_642 = |twos_comp_in[5:0]; // @[lib.scala 649:35] - wire _T_644 = ~twos_comp_in[6]; // @[lib.scala 649:40] - wire _T_646 = _T_642 ? _T_644 : twos_comp_in[6]; // @[lib.scala 649:23] - wire _T_648 = |twos_comp_in[6:0]; // @[lib.scala 649:35] - wire _T_650 = ~twos_comp_in[7]; // @[lib.scala 649:40] - wire _T_652 = _T_648 ? _T_650 : twos_comp_in[7]; // @[lib.scala 649:23] - wire _T_654 = |twos_comp_in[7:0]; // @[lib.scala 649:35] - wire _T_656 = ~twos_comp_in[8]; // @[lib.scala 649:40] - wire _T_658 = _T_654 ? _T_656 : twos_comp_in[8]; // @[lib.scala 649:23] - wire _T_660 = |twos_comp_in[8:0]; // @[lib.scala 649:35] - wire _T_662 = ~twos_comp_in[9]; // @[lib.scala 649:40] - wire _T_664 = _T_660 ? _T_662 : twos_comp_in[9]; // @[lib.scala 649:23] - wire _T_666 = |twos_comp_in[9:0]; // @[lib.scala 649:35] - wire _T_668 = ~twos_comp_in[10]; // @[lib.scala 649:40] - wire _T_670 = _T_666 ? _T_668 : twos_comp_in[10]; // @[lib.scala 649:23] - wire _T_672 = |twos_comp_in[10:0]; // @[lib.scala 649:35] - wire _T_674 = ~twos_comp_in[11]; // @[lib.scala 649:40] - wire _T_676 = _T_672 ? _T_674 : twos_comp_in[11]; // @[lib.scala 649:23] - wire _T_678 = |twos_comp_in[11:0]; // @[lib.scala 649:35] - wire _T_680 = ~twos_comp_in[12]; // @[lib.scala 649:40] - wire _T_682 = _T_678 ? _T_680 : twos_comp_in[12]; // @[lib.scala 649:23] - wire _T_684 = |twos_comp_in[12:0]; // @[lib.scala 649:35] - wire _T_686 = ~twos_comp_in[13]; // @[lib.scala 649:40] - wire _T_688 = _T_684 ? _T_686 : twos_comp_in[13]; // @[lib.scala 649:23] - wire _T_690 = |twos_comp_in[13:0]; // @[lib.scala 649:35] - wire _T_692 = ~twos_comp_in[14]; // @[lib.scala 649:40] - wire _T_694 = _T_690 ? _T_692 : twos_comp_in[14]; // @[lib.scala 649:23] - wire _T_696 = |twos_comp_in[14:0]; // @[lib.scala 649:35] - wire _T_698 = ~twos_comp_in[15]; // @[lib.scala 649:40] - wire _T_700 = _T_696 ? _T_698 : twos_comp_in[15]; // @[lib.scala 649:23] - wire _T_702 = |twos_comp_in[15:0]; // @[lib.scala 649:35] - wire _T_704 = ~twos_comp_in[16]; // @[lib.scala 649:40] - wire _T_706 = _T_702 ? _T_704 : twos_comp_in[16]; // @[lib.scala 649:23] - wire _T_708 = |twos_comp_in[16:0]; // @[lib.scala 649:35] - wire _T_710 = ~twos_comp_in[17]; // @[lib.scala 649:40] - wire _T_712 = _T_708 ? _T_710 : twos_comp_in[17]; // @[lib.scala 649:23] - wire _T_714 = |twos_comp_in[17:0]; // @[lib.scala 649:35] - wire _T_716 = ~twos_comp_in[18]; // @[lib.scala 649:40] - wire _T_718 = _T_714 ? _T_716 : twos_comp_in[18]; // @[lib.scala 649:23] - wire _T_720 = |twos_comp_in[18:0]; // @[lib.scala 649:35] - wire _T_722 = ~twos_comp_in[19]; // @[lib.scala 649:40] - wire _T_724 = _T_720 ? _T_722 : twos_comp_in[19]; // @[lib.scala 649:23] - wire _T_726 = |twos_comp_in[19:0]; // @[lib.scala 649:35] - wire _T_728 = ~twos_comp_in[20]; // @[lib.scala 649:40] - wire _T_730 = _T_726 ? _T_728 : twos_comp_in[20]; // @[lib.scala 649:23] - wire _T_732 = |twos_comp_in[20:0]; // @[lib.scala 649:35] - wire _T_734 = ~twos_comp_in[21]; // @[lib.scala 649:40] - wire _T_736 = _T_732 ? _T_734 : twos_comp_in[21]; // @[lib.scala 649:23] - wire _T_738 = |twos_comp_in[21:0]; // @[lib.scala 649:35] - wire _T_740 = ~twos_comp_in[22]; // @[lib.scala 649:40] - wire _T_742 = _T_738 ? _T_740 : twos_comp_in[22]; // @[lib.scala 649:23] - wire _T_744 = |twos_comp_in[22:0]; // @[lib.scala 649:35] - wire _T_746 = ~twos_comp_in[23]; // @[lib.scala 649:40] - wire _T_748 = _T_744 ? _T_746 : twos_comp_in[23]; // @[lib.scala 649:23] - wire _T_750 = |twos_comp_in[23:0]; // @[lib.scala 649:35] - wire _T_752 = ~twos_comp_in[24]; // @[lib.scala 649:40] - wire _T_754 = _T_750 ? _T_752 : twos_comp_in[24]; // @[lib.scala 649:23] - wire _T_756 = |twos_comp_in[24:0]; // @[lib.scala 649:35] - wire _T_758 = ~twos_comp_in[25]; // @[lib.scala 649:40] - wire _T_760 = _T_756 ? _T_758 : twos_comp_in[25]; // @[lib.scala 649:23] - wire _T_762 = |twos_comp_in[25:0]; // @[lib.scala 649:35] - wire _T_764 = ~twos_comp_in[26]; // @[lib.scala 649:40] - wire _T_766 = _T_762 ? _T_764 : twos_comp_in[26]; // @[lib.scala 649:23] - wire _T_768 = |twos_comp_in[26:0]; // @[lib.scala 649:35] - wire _T_770 = ~twos_comp_in[27]; // @[lib.scala 649:40] - wire _T_772 = _T_768 ? _T_770 : twos_comp_in[27]; // @[lib.scala 649:23] - wire _T_774 = |twos_comp_in[27:0]; // @[lib.scala 649:35] - wire _T_776 = ~twos_comp_in[28]; // @[lib.scala 649:40] - wire _T_778 = _T_774 ? _T_776 : twos_comp_in[28]; // @[lib.scala 649:23] - wire _T_780 = |twos_comp_in[28:0]; // @[lib.scala 649:35] - wire _T_782 = ~twos_comp_in[29]; // @[lib.scala 649:40] - wire _T_784 = _T_780 ? _T_782 : twos_comp_in[29]; // @[lib.scala 649:23] - wire _T_786 = |twos_comp_in[29:0]; // @[lib.scala 649:35] - wire _T_788 = ~twos_comp_in[30]; // @[lib.scala 649:40] - wire _T_790 = _T_786 ? _T_788 : twos_comp_in[30]; // @[lib.scala 649:23] - wire _T_792 = |twos_comp_in[30:0]; // @[lib.scala 649:35] - wire _T_794 = ~twos_comp_in[31]; // @[lib.scala 649:40] - wire _T_796 = _T_792 ? _T_794 : twos_comp_in[31]; // @[lib.scala 649:23] - wire [6:0] _T_802 = {_T_652,_T_646,_T_640,_T_634,_T_628,_T_622,_T_616}; // @[lib.scala 651:14] - wire [14:0] _T_810 = {_T_700,_T_694,_T_688,_T_682,_T_676,_T_670,_T_664,_T_658,_T_802}; // @[lib.scala 651:14] - wire [7:0] _T_817 = {_T_748,_T_742,_T_736,_T_730,_T_724,_T_718,_T_712,_T_706}; // @[lib.scala 651:14] - wire [30:0] _T_826 = {_T_796,_T_790,_T_784,_T_778,_T_772,_T_766,_T_760,_T_754,_T_817,_T_810}; // @[lib.scala 651:14] + wire _T_612 = |twos_comp_in[0]; // @[lib.scala 661:35] + wire _T_614 = ~twos_comp_in[1]; // @[lib.scala 661:40] + wire _T_616 = _T_612 ? _T_614 : twos_comp_in[1]; // @[lib.scala 661:23] + wire _T_618 = |twos_comp_in[1:0]; // @[lib.scala 661:35] + wire _T_620 = ~twos_comp_in[2]; // @[lib.scala 661:40] + wire _T_622 = _T_618 ? _T_620 : twos_comp_in[2]; // @[lib.scala 661:23] + wire _T_624 = |twos_comp_in[2:0]; // @[lib.scala 661:35] + wire _T_626 = ~twos_comp_in[3]; // @[lib.scala 661:40] + wire _T_628 = _T_624 ? _T_626 : twos_comp_in[3]; // @[lib.scala 661:23] + wire _T_630 = |twos_comp_in[3:0]; // @[lib.scala 661:35] + wire _T_632 = ~twos_comp_in[4]; // @[lib.scala 661:40] + wire _T_634 = _T_630 ? _T_632 : twos_comp_in[4]; // @[lib.scala 661:23] + wire _T_636 = |twos_comp_in[4:0]; // @[lib.scala 661:35] + wire _T_638 = ~twos_comp_in[5]; // @[lib.scala 661:40] + wire _T_640 = _T_636 ? _T_638 : twos_comp_in[5]; // @[lib.scala 661:23] + wire _T_642 = |twos_comp_in[5:0]; // @[lib.scala 661:35] + wire _T_644 = ~twos_comp_in[6]; // @[lib.scala 661:40] + wire _T_646 = _T_642 ? _T_644 : twos_comp_in[6]; // @[lib.scala 661:23] + wire _T_648 = |twos_comp_in[6:0]; // @[lib.scala 661:35] + wire _T_650 = ~twos_comp_in[7]; // @[lib.scala 661:40] + wire _T_652 = _T_648 ? _T_650 : twos_comp_in[7]; // @[lib.scala 661:23] + wire _T_654 = |twos_comp_in[7:0]; // @[lib.scala 661:35] + wire _T_656 = ~twos_comp_in[8]; // @[lib.scala 661:40] + wire _T_658 = _T_654 ? _T_656 : twos_comp_in[8]; // @[lib.scala 661:23] + wire _T_660 = |twos_comp_in[8:0]; // @[lib.scala 661:35] + wire _T_662 = ~twos_comp_in[9]; // @[lib.scala 661:40] + wire _T_664 = _T_660 ? _T_662 : twos_comp_in[9]; // @[lib.scala 661:23] + wire _T_666 = |twos_comp_in[9:0]; // @[lib.scala 661:35] + wire _T_668 = ~twos_comp_in[10]; // @[lib.scala 661:40] + wire _T_670 = _T_666 ? _T_668 : twos_comp_in[10]; // @[lib.scala 661:23] + wire _T_672 = |twos_comp_in[10:0]; // @[lib.scala 661:35] + wire _T_674 = ~twos_comp_in[11]; // @[lib.scala 661:40] + wire _T_676 = _T_672 ? _T_674 : twos_comp_in[11]; // @[lib.scala 661:23] + wire _T_678 = |twos_comp_in[11:0]; // @[lib.scala 661:35] + wire _T_680 = ~twos_comp_in[12]; // @[lib.scala 661:40] + wire _T_682 = _T_678 ? _T_680 : twos_comp_in[12]; // @[lib.scala 661:23] + wire _T_684 = |twos_comp_in[12:0]; // @[lib.scala 661:35] + wire _T_686 = ~twos_comp_in[13]; // @[lib.scala 661:40] + wire _T_688 = _T_684 ? _T_686 : twos_comp_in[13]; // @[lib.scala 661:23] + wire _T_690 = |twos_comp_in[13:0]; // @[lib.scala 661:35] + wire _T_692 = ~twos_comp_in[14]; // @[lib.scala 661:40] + wire _T_694 = _T_690 ? _T_692 : twos_comp_in[14]; // @[lib.scala 661:23] + wire _T_696 = |twos_comp_in[14:0]; // @[lib.scala 661:35] + wire _T_698 = ~twos_comp_in[15]; // @[lib.scala 661:40] + wire _T_700 = _T_696 ? _T_698 : twos_comp_in[15]; // @[lib.scala 661:23] + wire _T_702 = |twos_comp_in[15:0]; // @[lib.scala 661:35] + wire _T_704 = ~twos_comp_in[16]; // @[lib.scala 661:40] + wire _T_706 = _T_702 ? _T_704 : twos_comp_in[16]; // @[lib.scala 661:23] + wire _T_708 = |twos_comp_in[16:0]; // @[lib.scala 661:35] + wire _T_710 = ~twos_comp_in[17]; // @[lib.scala 661:40] + wire _T_712 = _T_708 ? _T_710 : twos_comp_in[17]; // @[lib.scala 661:23] + wire _T_714 = |twos_comp_in[17:0]; // @[lib.scala 661:35] + wire _T_716 = ~twos_comp_in[18]; // @[lib.scala 661:40] + wire _T_718 = _T_714 ? _T_716 : twos_comp_in[18]; // @[lib.scala 661:23] + wire _T_720 = |twos_comp_in[18:0]; // @[lib.scala 661:35] + wire _T_722 = ~twos_comp_in[19]; // @[lib.scala 661:40] + wire _T_724 = _T_720 ? _T_722 : twos_comp_in[19]; // @[lib.scala 661:23] + wire _T_726 = |twos_comp_in[19:0]; // @[lib.scala 661:35] + wire _T_728 = ~twos_comp_in[20]; // @[lib.scala 661:40] + wire _T_730 = _T_726 ? _T_728 : twos_comp_in[20]; // @[lib.scala 661:23] + wire _T_732 = |twos_comp_in[20:0]; // @[lib.scala 661:35] + wire _T_734 = ~twos_comp_in[21]; // @[lib.scala 661:40] + wire _T_736 = _T_732 ? _T_734 : twos_comp_in[21]; // @[lib.scala 661:23] + wire _T_738 = |twos_comp_in[21:0]; // @[lib.scala 661:35] + wire _T_740 = ~twos_comp_in[22]; // @[lib.scala 661:40] + wire _T_742 = _T_738 ? _T_740 : twos_comp_in[22]; // @[lib.scala 661:23] + wire _T_744 = |twos_comp_in[22:0]; // @[lib.scala 661:35] + wire _T_746 = ~twos_comp_in[23]; // @[lib.scala 661:40] + wire _T_748 = _T_744 ? _T_746 : twos_comp_in[23]; // @[lib.scala 661:23] + wire _T_750 = |twos_comp_in[23:0]; // @[lib.scala 661:35] + wire _T_752 = ~twos_comp_in[24]; // @[lib.scala 661:40] + wire _T_754 = _T_750 ? _T_752 : twos_comp_in[24]; // @[lib.scala 661:23] + wire _T_756 = |twos_comp_in[24:0]; // @[lib.scala 661:35] + wire _T_758 = ~twos_comp_in[25]; // @[lib.scala 661:40] + wire _T_760 = _T_756 ? _T_758 : twos_comp_in[25]; // @[lib.scala 661:23] + wire _T_762 = |twos_comp_in[25:0]; // @[lib.scala 661:35] + wire _T_764 = ~twos_comp_in[26]; // @[lib.scala 661:40] + wire _T_766 = _T_762 ? _T_764 : twos_comp_in[26]; // @[lib.scala 661:23] + wire _T_768 = |twos_comp_in[26:0]; // @[lib.scala 661:35] + wire _T_770 = ~twos_comp_in[27]; // @[lib.scala 661:40] + wire _T_772 = _T_768 ? _T_770 : twos_comp_in[27]; // @[lib.scala 661:23] + wire _T_774 = |twos_comp_in[27:0]; // @[lib.scala 661:35] + wire _T_776 = ~twos_comp_in[28]; // @[lib.scala 661:40] + wire _T_778 = _T_774 ? _T_776 : twos_comp_in[28]; // @[lib.scala 661:23] + wire _T_780 = |twos_comp_in[28:0]; // @[lib.scala 661:35] + wire _T_782 = ~twos_comp_in[29]; // @[lib.scala 661:40] + wire _T_784 = _T_780 ? _T_782 : twos_comp_in[29]; // @[lib.scala 661:23] + wire _T_786 = |twos_comp_in[29:0]; // @[lib.scala 661:35] + wire _T_788 = ~twos_comp_in[30]; // @[lib.scala 661:40] + wire _T_790 = _T_786 ? _T_788 : twos_comp_in[30]; // @[lib.scala 661:23] + wire _T_792 = |twos_comp_in[30:0]; // @[lib.scala 661:35] + wire _T_794 = ~twos_comp_in[31]; // @[lib.scala 661:40] + wire _T_796 = _T_792 ? _T_794 : twos_comp_in[31]; // @[lib.scala 661:23] + wire [6:0] _T_802 = {_T_652,_T_646,_T_640,_T_634,_T_628,_T_622,_T_616}; // @[lib.scala 663:14] + wire [14:0] _T_810 = {_T_700,_T_694,_T_688,_T_682,_T_676,_T_670,_T_664,_T_658,_T_802}; // @[lib.scala 663:14] + wire [7:0] _T_817 = {_T_748,_T_742,_T_736,_T_730,_T_724,_T_718,_T_712,_T_706}; // @[lib.scala 663:14] + wire [30:0] _T_826 = {_T_796,_T_790,_T_784,_T_778,_T_772,_T_766,_T_760,_T_754,_T_817,_T_810}; // @[lib.scala 663:14] wire [31:0] twos_comp_out = {_T_826,twos_comp_in[0]}; // @[Cat.scala 29:58] wire _T_828 = ~a_shift; // @[exu_div_ctl.scala 847:6] wire _T_830 = _T_828 & _T_66; // @[exu_div_ctl.scala 847:15] @@ -1673,58 +1650,47 @@ module exu_div_new_4bit_fullshortq( .io_operand(b_enc_io_operand), .io_cls(b_enc_io_cls) ); - rvclkhdr rvclkhdr ( // @[lib.scala 399:23] - .io_l1clk(rvclkhdr_io_l1clk), + rvclkhdr rvclkhdr ( // @[lib.scala 404:23] .io_clk(rvclkhdr_io_clk), .io_en(rvclkhdr_io_en) ); - rvclkhdr rvclkhdr_1 ( // @[lib.scala 399:23] - .io_l1clk(rvclkhdr_1_io_l1clk), + rvclkhdr rvclkhdr_1 ( // @[lib.scala 404:23] .io_clk(rvclkhdr_1_io_clk), .io_en(rvclkhdr_1_io_en) ); - rvclkhdr rvclkhdr_2 ( // @[lib.scala 399:23] - .io_l1clk(rvclkhdr_2_io_l1clk), + rvclkhdr rvclkhdr_2 ( // @[lib.scala 404:23] .io_clk(rvclkhdr_2_io_clk), .io_en(rvclkhdr_2_io_en) ); - rvclkhdr rvclkhdr_3 ( // @[lib.scala 399:23] - .io_l1clk(rvclkhdr_3_io_l1clk), + rvclkhdr rvclkhdr_3 ( // @[lib.scala 404:23] .io_clk(rvclkhdr_3_io_clk), .io_en(rvclkhdr_3_io_en) ); - rvclkhdr rvclkhdr_4 ( // @[lib.scala 399:23] - .io_l1clk(rvclkhdr_4_io_l1clk), + rvclkhdr rvclkhdr_4 ( // @[lib.scala 404:23] .io_clk(rvclkhdr_4_io_clk), .io_en(rvclkhdr_4_io_en) ); - rvclkhdr rvclkhdr_5 ( // @[lib.scala 399:23] - .io_l1clk(rvclkhdr_5_io_l1clk), + rvclkhdr rvclkhdr_5 ( // @[lib.scala 404:23] .io_clk(rvclkhdr_5_io_clk), .io_en(rvclkhdr_5_io_en) ); - rvclkhdr rvclkhdr_6 ( // @[lib.scala 399:23] - .io_l1clk(rvclkhdr_6_io_l1clk), + rvclkhdr rvclkhdr_6 ( // @[lib.scala 404:23] .io_clk(rvclkhdr_6_io_clk), .io_en(rvclkhdr_6_io_en) ); - rvclkhdr rvclkhdr_7 ( // @[lib.scala 399:23] - .io_l1clk(rvclkhdr_7_io_l1clk), + rvclkhdr rvclkhdr_7 ( // @[lib.scala 404:23] .io_clk(rvclkhdr_7_io_clk), .io_en(rvclkhdr_7_io_en) ); - rvclkhdr rvclkhdr_8 ( // @[lib.scala 399:23] - .io_l1clk(rvclkhdr_8_io_l1clk), + rvclkhdr rvclkhdr_8 ( // @[lib.scala 404:23] .io_clk(rvclkhdr_8_io_clk), .io_en(rvclkhdr_8_io_en) ); - rvclkhdr rvclkhdr_9 ( // @[lib.scala 399:23] - .io_l1clk(rvclkhdr_9_io_l1clk), + rvclkhdr rvclkhdr_9 ( // @[lib.scala 404:23] .io_clk(rvclkhdr_9_io_clk), .io_en(rvclkhdr_9_io_en) ); - rvclkhdr rvclkhdr_10 ( // @[lib.scala 399:23] - .io_l1clk(rvclkhdr_10_io_l1clk), + rvclkhdr rvclkhdr_10 ( // @[lib.scala 404:23] .io_clk(rvclkhdr_10_io_clk), .io_en(rvclkhdr_10_io_en) ); @@ -1732,28 +1698,28 @@ module exu_div_new_4bit_fullshortq( assign io_valid_out = finish_ff & _T; // @[exu_div_ctl.scala 881:16] assign a_enc_io_operand = {control_ff[2],a_ff}; // @[exu_div_ctl.scala 914:23] assign b_enc_io_operand = b_ff[32:0]; // @[exu_div_ctl.scala 917:23] - assign rvclkhdr_io_clk = clock; // @[lib.scala 401:18] - assign rvclkhdr_io_en = _T_47 | finish_ff; // @[lib.scala 402:17] - assign rvclkhdr_1_io_clk = clock; // @[lib.scala 401:18] - assign rvclkhdr_1_io_en = _T_47 | finish_ff; // @[lib.scala 402:17] - assign rvclkhdr_2_io_clk = clock; // @[lib.scala 401:18] - assign rvclkhdr_2_io_en = _T_47 | finish_ff; // @[lib.scala 402:17] - assign rvclkhdr_3_io_clk = clock; // @[lib.scala 401:18] - assign rvclkhdr_3_io_en = _T_47 | finish_ff; // @[lib.scala 402:17] - assign rvclkhdr_4_io_clk = clock; // @[lib.scala 401:18] - assign rvclkhdr_4_io_en = _T_47 | finish_ff; // @[lib.scala 402:17] - assign rvclkhdr_5_io_clk = clock; // @[lib.scala 401:18] - assign rvclkhdr_5_io_en = _T_47 | finish_ff; // @[lib.scala 402:17] - assign rvclkhdr_6_io_clk = clock; // @[lib.scala 401:18] - assign rvclkhdr_6_io_en = _T_47 | finish_ff; // @[lib.scala 402:17] - assign rvclkhdr_7_io_clk = clock; // @[lib.scala 401:18] - assign rvclkhdr_7_io_en = io_valid_in | running_state; // @[lib.scala 402:17] - assign rvclkhdr_8_io_clk = clock; // @[lib.scala 401:18] - assign rvclkhdr_8_io_en = io_valid_in | b_twos_comp; // @[lib.scala 402:17] - assign rvclkhdr_9_io_clk = clock; // @[lib.scala 401:18] - assign rvclkhdr_9_io_en = _T_45 | running_state; // @[lib.scala 402:17] - assign rvclkhdr_10_io_clk = clock; // @[lib.scala 401:18] - assign rvclkhdr_10_io_en = _T_45 | running_state; // @[lib.scala 402:17] + assign rvclkhdr_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_io_en = _T_47 | finish_ff; // @[lib.scala 407:17] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_1_io_en = _T_47 | finish_ff; // @[lib.scala 407:17] + assign rvclkhdr_2_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_2_io_en = _T_47 | finish_ff; // @[lib.scala 407:17] + assign rvclkhdr_3_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_3_io_en = _T_47 | finish_ff; // @[lib.scala 407:17] + assign rvclkhdr_4_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_4_io_en = _T_47 | finish_ff; // @[lib.scala 407:17] + assign rvclkhdr_5_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_5_io_en = _T_47 | finish_ff; // @[lib.scala 407:17] + assign rvclkhdr_6_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_6_io_en = _T_47 | finish_ff; // @[lib.scala 407:17] + assign rvclkhdr_7_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_7_io_en = io_valid_in | running_state; // @[lib.scala 407:17] + assign rvclkhdr_8_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_8_io_en = io_valid_in | b_twos_comp; // @[lib.scala 407:17] + assign rvclkhdr_9_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_9_io_en = _T_45 | running_state; // @[lib.scala 407:17] + assign rvclkhdr_10_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_10_io_en = _T_45 | running_state; // @[lib.scala 407:17] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -2178,30 +2144,22 @@ module exu( reg [31:0] _RAND_36; reg [31:0] _RAND_37; `endif // RANDOMIZE_REG_INIT - wire rvclkhdr_io_l1clk; // @[lib.scala 399:23] - wire rvclkhdr_io_clk; // @[lib.scala 399:23] - wire rvclkhdr_io_en; // @[lib.scala 399:23] - wire rvclkhdr_1_io_l1clk; // @[lib.scala 399:23] - wire rvclkhdr_1_io_clk; // @[lib.scala 399:23] - wire rvclkhdr_1_io_en; // @[lib.scala 399:23] - wire rvclkhdr_2_io_l1clk; // @[lib.scala 399:23] - wire rvclkhdr_2_io_clk; // @[lib.scala 399:23] - wire rvclkhdr_2_io_en; // @[lib.scala 399:23] - wire rvclkhdr_3_io_l1clk; // @[lib.scala 399:23] - wire rvclkhdr_3_io_clk; // @[lib.scala 399:23] - wire rvclkhdr_3_io_en; // @[lib.scala 399:23] - wire rvclkhdr_4_io_l1clk; // @[lib.scala 399:23] - wire rvclkhdr_4_io_clk; // @[lib.scala 399:23] - wire rvclkhdr_4_io_en; // @[lib.scala 399:23] - wire rvclkhdr_5_io_l1clk; // @[lib.scala 399:23] - wire rvclkhdr_5_io_clk; // @[lib.scala 399:23] - wire rvclkhdr_5_io_en; // @[lib.scala 399:23] - wire rvclkhdr_6_io_l1clk; // @[lib.scala 399:23] - wire rvclkhdr_6_io_clk; // @[lib.scala 399:23] - wire rvclkhdr_6_io_en; // @[lib.scala 399:23] - wire rvclkhdr_7_io_l1clk; // @[lib.scala 399:23] - wire rvclkhdr_7_io_clk; // @[lib.scala 399:23] - wire rvclkhdr_7_io_en; // @[lib.scala 399:23] + wire rvclkhdr_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_io_en; // @[lib.scala 404:23] + wire rvclkhdr_1_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_1_io_en; // @[lib.scala 404:23] + wire rvclkhdr_2_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_2_io_en; // @[lib.scala 404:23] + wire rvclkhdr_3_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_3_io_en; // @[lib.scala 404:23] + wire rvclkhdr_4_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_4_io_en; // @[lib.scala 404:23] + wire rvclkhdr_5_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_5_io_en; // @[lib.scala 404:23] + wire rvclkhdr_6_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_6_io_en; // @[lib.scala 404:23] + wire rvclkhdr_7_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_7_io_en; // @[lib.scala 404:23] wire i_alu_clock; // @[exu.scala 129:19] wire i_alu_reset; // @[exu.scala 129:19] wire i_alu_io_dec_alu_dec_i0_alu_decode_d; // @[exu.scala 129:19] @@ -2377,13 +2335,13 @@ module exu( wire [7:0] _T_230 = _T_227 | _T_228; // @[Mux.scala 27:72] wire [7:0] _T_229 = io_dec_exu_tlu_exu_dec_tlu_flush_lower_r ? ghr_x : 8'h0; // @[Mux.scala 27:72] wire [7:0] ghr_d_ns = _T_230 | _T_229; // @[Mux.scala 27:72] - wire [7:0] _T_33 = ghr_d_ns ^ ghr_d; // @[lib.scala 436:21] - wire _T_34 = |_T_33; // @[lib.scala 436:29] + wire [7:0] _T_33 = ghr_d_ns ^ ghr_d; // @[lib.scala 448:21] + wire _T_34 = |_T_33; // @[lib.scala 448:29] reg mul_valid_x; // @[Reg.scala 27:20] - wire _T_37 = io_dec_exu_decode_exu_mul_p_valid ^ mul_valid_x; // @[lib.scala 458:21] - wire _T_38 = |_T_37; // @[lib.scala 458:29] - wire _T_41 = io_dec_exu_decode_exu_dec_i0_branch_d ^ i0_branch_x; // @[lib.scala 436:21] - wire _T_42 = |_T_41; // @[lib.scala 436:29] + wire _T_37 = io_dec_exu_decode_exu_mul_p_valid ^ mul_valid_x; // @[lib.scala 470:21] + wire _T_38 = |_T_37; // @[lib.scala 470:29] + wire _T_41 = io_dec_exu_decode_exu_dec_i0_branch_d ^ i0_branch_x; // @[lib.scala 448:21] + wire _T_42 = |_T_41; // @[lib.scala 448:29] wire _T_46 = io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[0] | io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[1]; // @[exu.scala 82:84] wire _T_48 = _T_46 | io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[2]; // @[exu.scala 82:134] wire i0_rs1_bypass_en_d = _T_48 | io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[3]; // @[exu.scala 82:184] @@ -2464,43 +2422,35 @@ module exu( wire [30:0] _T_261 = _T_258 ? i0_flush_path_d : 31'h0; // @[Mux.scala 27:72] wire [31:0] pred_correct_npc_r = {{1'd0}, _T_31}; // @[exu.scala 46:51 exu.scala 77:45] wire [31:0] _T_265 = i0_pred_correct_upper_r ? pred_correct_npc_r : {{1'd0}, i0_flush_path_upper_r}; // @[exu.scala 240:55] - rvclkhdr rvclkhdr ( // @[lib.scala 399:23] - .io_l1clk(rvclkhdr_io_l1clk), + rvclkhdr rvclkhdr ( // @[lib.scala 404:23] .io_clk(rvclkhdr_io_clk), .io_en(rvclkhdr_io_en) ); - rvclkhdr rvclkhdr_1 ( // @[lib.scala 399:23] - .io_l1clk(rvclkhdr_1_io_l1clk), + rvclkhdr rvclkhdr_1 ( // @[lib.scala 404:23] .io_clk(rvclkhdr_1_io_clk), .io_en(rvclkhdr_1_io_en) ); - rvclkhdr rvclkhdr_2 ( // @[lib.scala 399:23] - .io_l1clk(rvclkhdr_2_io_l1clk), + rvclkhdr rvclkhdr_2 ( // @[lib.scala 404:23] .io_clk(rvclkhdr_2_io_clk), .io_en(rvclkhdr_2_io_en) ); - rvclkhdr rvclkhdr_3 ( // @[lib.scala 399:23] - .io_l1clk(rvclkhdr_3_io_l1clk), + rvclkhdr rvclkhdr_3 ( // @[lib.scala 404:23] .io_clk(rvclkhdr_3_io_clk), .io_en(rvclkhdr_3_io_en) ); - rvclkhdr rvclkhdr_4 ( // @[lib.scala 399:23] - .io_l1clk(rvclkhdr_4_io_l1clk), + rvclkhdr rvclkhdr_4 ( // @[lib.scala 404:23] .io_clk(rvclkhdr_4_io_clk), .io_en(rvclkhdr_4_io_en) ); - rvclkhdr rvclkhdr_5 ( // @[lib.scala 399:23] - .io_l1clk(rvclkhdr_5_io_l1clk), + rvclkhdr rvclkhdr_5 ( // @[lib.scala 404:23] .io_clk(rvclkhdr_5_io_clk), .io_en(rvclkhdr_5_io_en) ); - rvclkhdr rvclkhdr_6 ( // @[lib.scala 399:23] - .io_l1clk(rvclkhdr_6_io_l1clk), + rvclkhdr rvclkhdr_6 ( // @[lib.scala 404:23] .io_clk(rvclkhdr_6_io_clk), .io_en(rvclkhdr_6_io_en) ); - rvclkhdr rvclkhdr_7 ( // @[lib.scala 399:23] - .io_l1clk(rvclkhdr_7_io_l1clk), + rvclkhdr rvclkhdr_7 ( // @[lib.scala 404:23] .io_clk(rvclkhdr_7_io_clk), .io_en(rvclkhdr_7_io_en) ); @@ -2651,22 +2601,22 @@ module exu( assign io_lsu_exu_exu_lsu_rs1_d = _T_135 | _T_134; // @[exu.scala 113:27] assign io_lsu_exu_exu_lsu_rs2_d = _T_148 | _T_149; // @[exu.scala 119:27] assign io_exu_flush_path_final = _T_260 | _T_261; // @[exu.scala 236:33] - assign rvclkhdr_io_clk = clock; // @[lib.scala 401:18] - assign rvclkhdr_io_en = x_data_en & io_dec_exu_decode_exu_dec_i0_branch_d; // @[lib.scala 402:17] - assign rvclkhdr_1_io_clk = clock; // @[lib.scala 401:18] - assign rvclkhdr_1_io_en = r_data_en & i0_branch_x; // @[lib.scala 402:17] - assign rvclkhdr_2_io_clk = clock; // @[lib.scala 401:18] - assign rvclkhdr_2_io_en = io_dec_exu_decode_exu_dec_ctl_en[1]; // @[lib.scala 402:17] - assign rvclkhdr_3_io_clk = clock; // @[lib.scala 401:18] - assign rvclkhdr_3_io_en = io_dec_exu_decode_exu_dec_ctl_en[1]; // @[lib.scala 402:17] - assign rvclkhdr_4_io_clk = clock; // @[lib.scala 401:18] - assign rvclkhdr_4_io_en = io_dec_exu_decode_exu_dec_ctl_en[1]; // @[lib.scala 402:17] - assign rvclkhdr_5_io_clk = clock; // @[lib.scala 401:18] - assign rvclkhdr_5_io_en = io_dec_exu_decode_exu_dec_ctl_en[1]; // @[lib.scala 402:17] - assign rvclkhdr_6_io_clk = clock; // @[lib.scala 401:18] - assign rvclkhdr_6_io_en = io_dec_exu_decode_exu_dec_ctl_en[1]; // @[lib.scala 402:17] - assign rvclkhdr_7_io_clk = clock; // @[lib.scala 401:18] - assign rvclkhdr_7_io_en = x_data_en & io_dec_exu_dec_alu_dec_csr_ren_d; // @[lib.scala 402:17] + assign rvclkhdr_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_io_en = x_data_en & io_dec_exu_decode_exu_dec_i0_branch_d; // @[lib.scala 407:17] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_1_io_en = r_data_en & i0_branch_x; // @[lib.scala 407:17] + assign rvclkhdr_2_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_2_io_en = io_dec_exu_decode_exu_dec_ctl_en[1]; // @[lib.scala 407:17] + assign rvclkhdr_3_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_3_io_en = io_dec_exu_decode_exu_dec_ctl_en[1]; // @[lib.scala 407:17] + assign rvclkhdr_4_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_4_io_en = io_dec_exu_decode_exu_dec_ctl_en[1]; // @[lib.scala 407:17] + assign rvclkhdr_5_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_5_io_en = io_dec_exu_decode_exu_dec_ctl_en[1]; // @[lib.scala 407:17] + assign rvclkhdr_6_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_6_io_en = io_dec_exu_decode_exu_dec_ctl_en[1]; // @[lib.scala 407:17] + assign rvclkhdr_7_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_7_io_en = x_data_en & io_dec_exu_dec_alu_dec_csr_ren_d; // @[lib.scala 407:17] assign i_alu_clock = clock; assign i_alu_reset = reset; assign i_alu_io_dec_alu_dec_i0_alu_decode_d = io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[exu.scala 130:20] diff --git a/exu_mul_ctl.fir b/exu_mul_ctl.fir index cb77692b..0f8922a6 100644 --- a/exu_mul_ctl.fir +++ b/exu_mul_ctl.fir @@ -208,24 +208,28 @@ circuit exu_mul_ctl : skip @[Reg.scala 28:19] low_x <= _T_9 @[exu_mul_ctl.scala 126:9] node _T_10 = bits(io.mul_p.valid, 0, 0) @[exu_mul_ctl.scala 127:44] - inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 422:23] + inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 426:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset - rvclkhdr_1.io.clk <= clock @[lib.scala 424:18] - rvclkhdr_1.io.en <= _T_10 @[lib.scala 425:17] - rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 426:24] - reg _T_11 : SInt, rvclkhdr_1.io.l1clk with : (reset => (reset, asSInt(UInt<1>("h00")))) @[lib.scala 428:16] - _T_11 <= rs1_ext_in @[lib.scala 428:16] + rvclkhdr_1.io.clk <= clock @[lib.scala 428:18] + rvclkhdr_1.io.en <= _T_10 @[lib.scala 429:17] + rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 430:24] + reg _T_11 : SInt, clock with : (reset => (reset, asSInt(UInt<1>("h00")))) @[Reg.scala 27:20] + when _T_10 : @[Reg.scala 28:19] + _T_11 <= rs1_ext_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] rs1_x <= _T_11 @[exu_mul_ctl.scala 127:9] node _T_12 = bits(io.mul_p.valid, 0, 0) @[exu_mul_ctl.scala 128:45] - inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 422:23] + inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 426:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset - rvclkhdr_2.io.clk <= clock @[lib.scala 424:18] - rvclkhdr_2.io.en <= _T_12 @[lib.scala 425:17] - rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 426:24] - reg _T_13 : SInt, rvclkhdr_2.io.l1clk with : (reset => (reset, asSInt(UInt<1>("h00")))) @[lib.scala 428:16] - _T_13 <= rs2_ext_in @[lib.scala 428:16] + rvclkhdr_2.io.clk <= clock @[lib.scala 428:18] + rvclkhdr_2.io.en <= _T_12 @[lib.scala 429:17] + rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 430:24] + reg _T_13 : SInt, clock with : (reset => (reset, asSInt(UInt<1>("h00")))) @[Reg.scala 27:20] + when _T_12 : @[Reg.scala 28:19] + _T_13 <= rs2_ext_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] rs2_x <= _T_13 @[exu_mul_ctl.scala 128:9] node _T_14 = mul(rs1_x, rs2_x) @[exu_mul_ctl.scala 130:20] prod_x <= _T_14 @[exu_mul_ctl.scala 130:10] diff --git a/exu_mul_ctl.v b/exu_mul_ctl.v index d06bb11e..3e9c822b 100644 --- a/exu_mul_ctl.v +++ b/exu_mul_ctl.v @@ -1,5 +1,4 @@ module rvclkhdr( - output io_l1clk, input io_clk, input io_en ); @@ -13,7 +12,6 @@ module rvclkhdr( .EN(clkhdr_EN), .SE(clkhdr_SE) ); - assign io_l1clk = clkhdr_Q; // @[lib.scala 335:14] assign clkhdr_CK = io_clk; // @[lib.scala 336:18] assign clkhdr_EN = io_en; // @[lib.scala 337:18] assign clkhdr_SE = 1'h0; // @[lib.scala 338:18] @@ -51,26 +49,23 @@ module exu_mul_ctl( reg [63:0] _RAND_1; reg [63:0] _RAND_2; `endif // RANDOMIZE_REG_INIT - wire rvclkhdr_io_l1clk; // @[lib.scala 399:23] wire rvclkhdr_io_clk; // @[lib.scala 399:23] wire rvclkhdr_io_en; // @[lib.scala 399:23] - wire rvclkhdr_1_io_l1clk; // @[lib.scala 422:23] - wire rvclkhdr_1_io_clk; // @[lib.scala 422:23] - wire rvclkhdr_1_io_en; // @[lib.scala 422:23] - wire rvclkhdr_2_io_l1clk; // @[lib.scala 422:23] - wire rvclkhdr_2_io_clk; // @[lib.scala 422:23] - wire rvclkhdr_2_io_en; // @[lib.scala 422:23] - wire rvclkhdr_3_io_l1clk; // @[lib.scala 399:23] + wire rvclkhdr_1_io_clk; // @[lib.scala 426:23] + wire rvclkhdr_1_io_en; // @[lib.scala 426:23] + wire rvclkhdr_2_io_clk; // @[lib.scala 426:23] + wire rvclkhdr_2_io_en; // @[lib.scala 426:23] wire rvclkhdr_3_io_clk; // @[lib.scala 399:23] wire rvclkhdr_3_io_en; // @[lib.scala 399:23] - wire rvclkhdr_4_io_l1clk; // @[lib.scala 399:23] wire rvclkhdr_4_io_clk; // @[lib.scala 399:23] wire rvclkhdr_4_io_en; // @[lib.scala 399:23] wire _T_1 = io_mul_p_bits_rs1_sign & io_rs1_in[31]; // @[exu_mul_ctl.scala 123:44] + wire [32:0] rs1_ext_in = {_T_1,io_rs1_in}; // @[exu_mul_ctl.scala 123:71] wire _T_5 = io_mul_p_bits_rs2_sign & io_rs2_in[31]; // @[exu_mul_ctl.scala 124:44] + wire [32:0] rs2_ext_in = {_T_5,io_rs2_in}; // @[exu_mul_ctl.scala 124:71] reg low_x; // @[Reg.scala 27:20] - reg [32:0] rs1_x; // @[lib.scala 428:16] - reg [32:0] rs2_x; // @[lib.scala 428:16] + reg [32:0] rs1_x; // @[Reg.scala 27:20] + reg [32:0] rs2_x; // @[Reg.scala 27:20] wire [65:0] prod_x = $signed(rs1_x) * $signed(rs2_x); // @[exu_mul_ctl.scala 130:20] wire _T_39758 = ~low_x; // @[exu_mul_ctl.scala 388:46] wire [7:0] _T_39762 = {_T_39758,_T_39758,_T_39758,_T_39758,_T_39758,_T_39758,_T_39758,_T_39758}; // @[Cat.scala 29:58] @@ -82,37 +77,32 @@ module exu_mul_ctl( wire [31:0] _T_39773 = {low_x,low_x,low_x,low_x,low_x,low_x,low_x,low_x,_T_39771,_T_39772}; // @[Cat.scala 29:58] wire [31:0] _T_39775 = _T_39773 & prod_x[31:0]; // @[exu_mul_ctl.scala 389:40] rvclkhdr rvclkhdr ( // @[lib.scala 399:23] - .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), .io_en(rvclkhdr_io_en) ); - rvclkhdr rvclkhdr_1 ( // @[lib.scala 422:23] - .io_l1clk(rvclkhdr_1_io_l1clk), + rvclkhdr rvclkhdr_1 ( // @[lib.scala 426:23] .io_clk(rvclkhdr_1_io_clk), .io_en(rvclkhdr_1_io_en) ); - rvclkhdr rvclkhdr_2 ( // @[lib.scala 422:23] - .io_l1clk(rvclkhdr_2_io_l1clk), + rvclkhdr rvclkhdr_2 ( // @[lib.scala 426:23] .io_clk(rvclkhdr_2_io_clk), .io_en(rvclkhdr_2_io_en) ); rvclkhdr rvclkhdr_3 ( // @[lib.scala 399:23] - .io_l1clk(rvclkhdr_3_io_l1clk), .io_clk(rvclkhdr_3_io_clk), .io_en(rvclkhdr_3_io_en) ); rvclkhdr rvclkhdr_4 ( // @[lib.scala 399:23] - .io_l1clk(rvclkhdr_4_io_l1clk), .io_clk(rvclkhdr_4_io_clk), .io_en(rvclkhdr_4_io_en) ); assign io_result_x = _T_39766 | _T_39775; // @[exu_mul_ctl.scala 388:15] assign rvclkhdr_io_clk = clock; // @[lib.scala 401:18] assign rvclkhdr_io_en = io_mul_p_valid; // @[lib.scala 402:17] - assign rvclkhdr_1_io_clk = clock; // @[lib.scala 424:18] - assign rvclkhdr_1_io_en = io_mul_p_valid; // @[lib.scala 425:17] - assign rvclkhdr_2_io_clk = clock; // @[lib.scala 424:18] - assign rvclkhdr_2_io_en = io_mul_p_valid; // @[lib.scala 425:17] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 428:18] + assign rvclkhdr_1_io_en = io_mul_p_valid; // @[lib.scala 429:17] + assign rvclkhdr_2_io_clk = clock; // @[lib.scala 428:18] + assign rvclkhdr_2_io_en = io_mul_p_valid; // @[lib.scala 429:17] assign rvclkhdr_3_io_clk = clock; // @[lib.scala 401:18] assign rvclkhdr_3_io_en = io_mul_p_valid; // @[lib.scala 402:17] assign rvclkhdr_4_io_clk = clock; // @[lib.scala 401:18] @@ -181,18 +171,18 @@ end // initial low_x <= io_mul_p_bits_low; end end - always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin + always @(posedge clock or posedge reset) begin if (reset) begin rs1_x <= 33'sh0; - end else begin - rs1_x <= {_T_1,io_rs1_in}; + end else if (io_mul_p_valid) begin + rs1_x <= rs1_ext_in; end end - always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + always @(posedge clock or posedge reset) begin if (reset) begin rs2_x <= 33'sh0; - end else begin - rs2_x <= {_T_5,io_rs2_in}; + end else if (io_mul_p_valid) begin + rs2_x <= rs2_ext_in; end end endmodule diff --git a/src/main/scala/lib/lib.scala b/src/main/scala/lib/lib.scala index 16300443..1221c6d6 100644 --- a/src/main/scala/lib/lib.scala +++ b/src/main/scala/lib/lib.scala @@ -349,11 +349,16 @@ trait lib extends param{ } object rvoclkhdr { def apply(clk: Clock, en: Bool, scan_mode: Bool): Clock = { - val cg = Module(new rvclkhdr) - cg.io.clk := clk - cg.io.en := en - cg.io.scan_mode := 0.U - cg.io.l1clk + if(RV_FPGA_OPTIMIZE){ + clk + }else{ + val cg = Module(new rvclkhdr) + cg.io.clk := clk + cg.io.en := en + cg.io.scan_mode := 0.U + cg.io.l1clk + } + } } @@ -401,12 +406,12 @@ trait lib extends param{ obj.io.clk := clk obj.io.en := en obj.io.scan_mode := 0.U - if(RV_FPGA_OPTIMIZE) + if(RV_FPGA_OPTIMIZE) withClock(clk){RegEnable(din,0.U,en)} - else - withClock(l1clk) { - RegNext(din, 0.U) - } + else + withClock(l1clk) { + RegNext(din, 0.U) + } } def apply(din: Bundle, en: Bool, clk: Clock, scan_mode: Bool) = { val obj = Module(new rvclkhdr()) @@ -414,9 +419,13 @@ trait lib extends param{ obj.io.clk := clk obj.io.en := en obj.io.scan_mode := 0.U - withClock(l1clk) { - RegNext(din,0.U.asTypeOf(din.cloneType)) - } + if(RV_FPGA_OPTIMIZE) + withClock(clk){RegEnable(din,0.U.asTypeOf(din),en)} + else + withClock(l1clk) { + RegNext(din, 0.U.asTypeOf(din)) + } + } def apply(din: SInt, en: Bool, clk: Clock, scan_mode: Bool): Bits with Num[_ >: SInt with UInt <: Bits with Num[_ >: SInt with UInt]] = { val obj = Module(new rvclkhdr()) @@ -424,9 +433,12 @@ trait lib extends param{ obj.io.clk := clk obj.io.en := en obj.io.scan_mode := 0.U - withClock(l1clk) { - RegNext(din, 0.S) - } + if(RV_FPGA_OPTIMIZE) + withClock(clk){RegEnable(din,0.S,en)} + else + withClock(l1clk) { + RegNext(din, 0.S) + } } } //////////////////////////////////////////////////////////////////////////////////// diff --git a/src/main/scala/lib/param.scala b/src/main/scala/lib/param.scala index 38d95657..6f052925 100644 --- a/src/main/scala/lib/param.scala +++ b/src/main/scala/lib/param.scala @@ -161,12 +161,13 @@ trait param { val BTB_ENABLE = 0x1 val BTB_TOFFSET_SIZE = 0x00C val BTB_FULLYA = 0x00 - val BITMANIP_ZBA = 0x00 - val BITMANIP_ZBB = 0x01 - val BITMANIP_ZBC = 0x00 - val BITMANIP_ZBE = 0x00 - val BITMANIP_ZBF = 0x00 - val BITMANIP_ZBP = 0x00 - val BITMANIP_ZBR = 0x00 - val BITMANIP_ZBS = 0x01 + val BITMANIP_ZBA = 0x00 + val BITMANIP_ZBB = 0x01 + val BITMANIP_ZBC = 0x00 + val BITMANIP_ZBE = 0x00 + val BITMANIP_ZBF = 0x00 + val BITMANIP_ZBP = 0x00 + val BITMANIP_ZBR = 0x00 + val BITMANIP_ZBS = 0x01 + } diff --git a/target/scala-2.12/classes/lib/lib$rvdff_fpga$.class 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