From a19929362099c675fcd24f832bc055cdf1988f71 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E2=80=8BLaraib=20Khan?= <​laraib.khan@lampromellon.com> Date: Wed, 2 Dec 2020 12:05:38 +0500 Subject: [PATCH] axi to ahb update --- axi4_to_ahb.fir | 1774 +++++++++-------- axi4_to_ahb.v | 820 ++++---- src/main/scala/lib/axi4_to_ahb.scala | 5 +- target/scala-2.12/classes/lib/AXImain$.class | Bin 3898 -> 3898 bytes .../lib/AXImain$delayedInit$body.class | Bin 732 -> 732 bytes .../scala-2.12/classes/lib/axi4_to_ahb.class | Bin 107112 -> 107031 bytes 6 files changed, 1301 insertions(+), 1298 deletions(-) diff --git a/axi4_to_ahb.fir b/axi4_to_ahb.fir index a2ca1374..87efec7e 100644 --- a/axi4_to_ahb.fir +++ b/axi4_to_ahb.fir @@ -245,8 +245,8 @@ circuit axi4_to_ahb : input reset : AsyncReset output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi_awvalid : UInt<1>, flip axi_awid : UInt<1>, flip axi_awaddr : UInt<32>, flip axi_awsize : UInt<3>, flip axi_awprot : UInt<3>, flip axi_wvalid : UInt<1>, flip axi_wdata : UInt<64>, flip axi_wstrb : UInt<8>, flip axi_wlast : UInt<1>, flip axi_bready : UInt<1>, flip axi_arvalid : UInt<1>, flip axi_arid : UInt<1>, flip axi_araddr : UInt<32>, flip axi_arsize : UInt<3>, flip axi_arprot : UInt<3>, flip axi_rready : UInt<1>, flip ahb_hrdata : UInt<64>, flip ahb_hready : UInt<1>, flip ahb_hresp : UInt<1>, axi_awready : UInt<1>, axi_wready : UInt<1>, axi_bvalid : UInt<1>, axi_bresp : UInt<2>, axi_bid : UInt<1>, axi_arready : UInt<1>, axi_rvalid : UInt<1>, axi_rid : UInt<1>, axi_rdata : UInt<64>, axi_rresp : UInt<2>, axi_rlast : UInt<1>, ahb_haddr : UInt<32>, ahb_hburst : UInt<3>, ahb_hmastlock : UInt<1>, ahb_hprot : UInt<4>, ahb_hsize : UInt<3>, ahb_htrans : UInt<2>, ahb_hwrite : UInt<1>, ahb_hwdata : UInt<64>} - wire buf_rst : UInt<3> - buf_rst <= UInt<3>("h00") + wire buf_rst : UInt<1> + buf_rst <= UInt<1>("h00") wire buf_state_en : UInt<1> buf_state_en <= UInt<1>("h00") wire ahbm_clk : Clock @[axi4_to_ahb.scala 62:22] @@ -258,11 +258,13 @@ circuit axi4_to_ahb : buf_nxtstate <= UInt<3>("h00") node _T = bits(buf_state_en, 0, 0) @[axi4_to_ahb.scala 68:70] node _T_1 = mux(_T, buf_nxtstate, buf_state) @[axi4_to_ahb.scala 68:50] - node _T_2 = not(buf_rst) @[axi4_to_ahb.scala 68:100] - node _T_3 = and(_T_1, _T_2) @[axi4_to_ahb.scala 68:98] - reg _T_4 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 68:45] - _T_4 <= _T_3 @[axi4_to_ahb.scala 68:45] - buf_state <= _T_4 @[axi4_to_ahb.scala 68:13] + node _T_2 = eq(buf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 68:107] + node _T_3 = bits(_T_2, 0, 0) @[Bitwise.scala 72:15] + node _T_4 = mux(_T_3, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_5 = and(_T_1, _T_4) @[axi4_to_ahb.scala 68:98] + reg _T_6 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 68:45] + _T_6 <= _T_5 @[axi4_to_ahb.scala 68:45] + buf_state <= _T_6 @[axi4_to_ahb.scala 68:13] wire slave_valid : UInt<1> slave_valid <= UInt<1>("h00") wire slave_ready : UInt<1> @@ -408,64 +410,64 @@ circuit axi4_to_ahb : wire ahbm_data_clken : UInt<1> ahbm_data_clken <= UInt<1>("h00") wire buf_clk : Clock @[axi4_to_ahb.scala 156:21] - node _T_5 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 197:27] - wr_cmd_vld <= _T_5 @[axi4_to_ahb.scala 197:14] - node _T_6 = or(wr_cmd_vld, io.axi_arvalid) @[axi4_to_ahb.scala 198:30] - master_valid <= _T_6 @[axi4_to_ahb.scala 198:16] - node _T_7 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 199:38] - node _T_8 = bits(wrbuf_tag, 0, 0) @[axi4_to_ahb.scala 199:51] - node _T_9 = bits(io.axi_arid, 0, 0) @[axi4_to_ahb.scala 199:76] - node _T_10 = mux(_T_7, _T_8, _T_9) @[axi4_to_ahb.scala 199:20] - master_tag <= _T_10 @[axi4_to_ahb.scala 199:14] - node _T_11 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 200:38] - node _T_12 = mux(_T_11, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 200:20] - master_opc <= _T_12 @[axi4_to_ahb.scala 200:14] - node _T_13 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 201:39] - node _T_14 = bits(wrbuf_addr, 31, 0) @[axi4_to_ahb.scala 201:53] - node _T_15 = bits(io.axi_araddr, 31, 0) @[axi4_to_ahb.scala 201:75] - node _T_16 = mux(_T_13, _T_14, _T_15) @[axi4_to_ahb.scala 201:21] - master_addr <= _T_16 @[axi4_to_ahb.scala 201:15] - node _T_17 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 202:39] - node _T_18 = bits(wrbuf_size, 2, 0) @[axi4_to_ahb.scala 202:53] - node _T_19 = bits(io.axi_arsize, 2, 0) @[axi4_to_ahb.scala 202:74] - node _T_20 = mux(_T_17, _T_18, _T_19) @[axi4_to_ahb.scala 202:21] - master_size <= _T_20 @[axi4_to_ahb.scala 202:15] - node _T_21 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 203:32] - master_byteen <= _T_21 @[axi4_to_ahb.scala 203:17] - node _T_22 = bits(wrbuf_data, 63, 0) @[axi4_to_ahb.scala 204:29] - master_wdata <= _T_22 @[axi4_to_ahb.scala 204:16] - node _T_23 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 207:32] - node _T_24 = bits(slave_opc, 3, 3) @[axi4_to_ahb.scala 207:57] - node _T_25 = and(_T_23, _T_24) @[axi4_to_ahb.scala 207:46] - io.axi_bvalid <= _T_25 @[axi4_to_ahb.scala 207:17] - node _T_26 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 208:32] - node _T_27 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 208:59] - node _T_28 = mux(_T_27, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 208:49] - node _T_29 = mux(_T_26, UInt<2>("h02"), _T_28) @[axi4_to_ahb.scala 208:22] - io.axi_bresp <= _T_29 @[axi4_to_ahb.scala 208:16] - node _T_30 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 209:26] - io.axi_bid <= _T_30 @[axi4_to_ahb.scala 209:14] - node _T_31 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 211:32] - node _T_32 = bits(slave_opc, 3, 2) @[axi4_to_ahb.scala 211:58] - node _T_33 = eq(_T_32, UInt<1>("h00")) @[axi4_to_ahb.scala 211:65] - node _T_34 = and(_T_31, _T_33) @[axi4_to_ahb.scala 211:46] - io.axi_rvalid <= _T_34 @[axi4_to_ahb.scala 211:17] - node _T_35 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 212:32] - node _T_36 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 212:59] - node _T_37 = mux(_T_36, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 212:49] - node _T_38 = mux(_T_35, UInt<2>("h02"), _T_37) @[axi4_to_ahb.scala 212:22] - io.axi_rresp <= _T_38 @[axi4_to_ahb.scala 212:16] - node _T_39 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 213:26] - io.axi_rid <= _T_39 @[axi4_to_ahb.scala 213:14] - node _T_40 = bits(slave_rdata, 63, 0) @[axi4_to_ahb.scala 214:30] - io.axi_rdata <= _T_40 @[axi4_to_ahb.scala 214:16] - node _T_41 = and(io.axi_bready, io.axi_rready) @[axi4_to_ahb.scala 215:32] - slave_ready <= _T_41 @[axi4_to_ahb.scala 215:15] - node _T_42 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 218:56] - node _T_43 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 218:91] - node _T_44 = or(_T_42, _T_43) @[axi4_to_ahb.scala 218:74] - node _T_45 = and(io.bus_clk_en, _T_44) @[axi4_to_ahb.scala 218:37] - bus_write_clk_en <= _T_45 @[axi4_to_ahb.scala 218:20] + node _T_7 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 197:27] + wr_cmd_vld <= _T_7 @[axi4_to_ahb.scala 197:14] + node _T_8 = or(wr_cmd_vld, io.axi_arvalid) @[axi4_to_ahb.scala 198:30] + master_valid <= _T_8 @[axi4_to_ahb.scala 198:16] + node _T_9 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 199:38] + node _T_10 = bits(wrbuf_tag, 0, 0) @[axi4_to_ahb.scala 199:51] + node _T_11 = bits(io.axi_arid, 0, 0) @[axi4_to_ahb.scala 199:76] + node _T_12 = mux(_T_9, _T_10, _T_11) @[axi4_to_ahb.scala 199:20] + master_tag <= _T_12 @[axi4_to_ahb.scala 199:14] + node _T_13 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 200:38] + node _T_14 = mux(_T_13, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 200:20] + master_opc <= _T_14 @[axi4_to_ahb.scala 200:14] + node _T_15 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 201:39] + node _T_16 = bits(wrbuf_addr, 31, 0) @[axi4_to_ahb.scala 201:53] + node _T_17 = bits(io.axi_araddr, 31, 0) @[axi4_to_ahb.scala 201:75] + node _T_18 = mux(_T_15, _T_16, _T_17) @[axi4_to_ahb.scala 201:21] + master_addr <= _T_18 @[axi4_to_ahb.scala 201:15] + node _T_19 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 202:39] + node _T_20 = bits(wrbuf_size, 2, 0) @[axi4_to_ahb.scala 202:53] + node _T_21 = bits(io.axi_arsize, 2, 0) @[axi4_to_ahb.scala 202:74] + node _T_22 = mux(_T_19, _T_20, _T_21) @[axi4_to_ahb.scala 202:21] + master_size <= _T_22 @[axi4_to_ahb.scala 202:15] + node _T_23 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 203:32] + master_byteen <= _T_23 @[axi4_to_ahb.scala 203:17] + node _T_24 = bits(wrbuf_data, 63, 0) @[axi4_to_ahb.scala 204:29] + master_wdata <= _T_24 @[axi4_to_ahb.scala 204:16] + node _T_25 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 207:32] + node _T_26 = bits(slave_opc, 3, 3) @[axi4_to_ahb.scala 207:57] + node _T_27 = and(_T_25, _T_26) @[axi4_to_ahb.scala 207:46] + io.axi_bvalid <= _T_27 @[axi4_to_ahb.scala 207:17] + node _T_28 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 208:32] + node _T_29 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 208:59] + node _T_30 = mux(_T_29, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 208:49] + node _T_31 = mux(_T_28, UInt<2>("h02"), _T_30) @[axi4_to_ahb.scala 208:22] + io.axi_bresp <= _T_31 @[axi4_to_ahb.scala 208:16] + node _T_32 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 209:26] + io.axi_bid <= _T_32 @[axi4_to_ahb.scala 209:14] + node _T_33 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 211:32] + node _T_34 = bits(slave_opc, 3, 2) @[axi4_to_ahb.scala 211:58] + node _T_35 = eq(_T_34, UInt<1>("h00")) @[axi4_to_ahb.scala 211:65] + node _T_36 = and(_T_33, _T_35) @[axi4_to_ahb.scala 211:46] + io.axi_rvalid <= _T_36 @[axi4_to_ahb.scala 211:17] + node _T_37 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 212:32] + node _T_38 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 212:59] + node _T_39 = mux(_T_38, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 212:49] + node _T_40 = mux(_T_37, UInt<2>("h02"), _T_39) @[axi4_to_ahb.scala 212:22] + io.axi_rresp <= _T_40 @[axi4_to_ahb.scala 212:16] + node _T_41 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 213:26] + io.axi_rid <= _T_41 @[axi4_to_ahb.scala 213:14] + node _T_42 = bits(slave_rdata, 63, 0) @[axi4_to_ahb.scala 214:30] + io.axi_rdata <= _T_42 @[axi4_to_ahb.scala 214:16] + node _T_43 = and(io.axi_bready, io.axi_rready) @[axi4_to_ahb.scala 215:32] + slave_ready <= _T_43 @[axi4_to_ahb.scala 215:15] + node _T_44 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 218:56] + node _T_45 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 218:91] + node _T_46 = or(_T_44, _T_45) @[axi4_to_ahb.scala 218:74] + node _T_47 = and(io.bus_clk_en, _T_46) @[axi4_to_ahb.scala 218:37] + bus_write_clk_en <= _T_47 @[axi4_to_ahb.scala 218:20] inst rvclkhdr of rvclkhdr @[el2_lib.scala 483:22] rvclkhdr.clock <= clock rvclkhdr.reset <= reset @@ -473,12 +475,12 @@ circuit axi4_to_ahb : rvclkhdr.io.en <= io.bus_clk_en @[el2_lib.scala 485:16] rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] bus_clk <= rvclkhdr.io.l1clk @[axi4_to_ahb.scala 220:11] - node _T_46 = bits(bus_write_clk_en, 0, 0) @[axi4_to_ahb.scala 221:59] + node _T_48 = bits(bus_write_clk_en, 0, 0) @[axi4_to_ahb.scala 221:59] inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 483:22] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset rvclkhdr_1.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_1.io.en <= _T_46 @[el2_lib.scala 485:16] + rvclkhdr_1.io.en <= _T_48 @[el2_lib.scala 485:16] rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] bus_write_clk <= rvclkhdr_1.io.l1clk @[axi4_to_ahb.scala 221:17] io.ahb_htrans <= UInt<1>("h00") @[axi4_to_ahb.scala 224:17] @@ -497,925 +499,925 @@ circuit axi4_to_ahb : slvbuf_wr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 238:19] bypass_en <= UInt<1>("h00") @[axi4_to_ahb.scala 239:20] rd_bypass_idle <= UInt<1>("h00") @[axi4_to_ahb.scala 240:18] - node _T_47 = eq(UInt<3>("h00"), buf_state) @[Conditional.scala 37:30] - when _T_47 : @[Conditional.scala 40:58] + node _T_49 = eq(UInt<3>("h00"), buf_state) @[Conditional.scala 37:30] + when _T_49 : @[Conditional.scala 40:58] master_ready <= UInt<1>("h01") @[axi4_to_ahb.scala 244:20] - node _T_48 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 245:34] - node _T_49 = eq(_T_48, UInt<1>("h01")) @[axi4_to_ahb.scala 245:41] - buf_write_in <= _T_49 @[axi4_to_ahb.scala 245:20] - node _T_50 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 246:46] - node _T_51 = mux(_T_50, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 246:26] - buf_nxtstate <= _T_51 @[axi4_to_ahb.scala 246:20] - node _T_52 = and(master_valid, UInt<1>("h01")) @[axi4_to_ahb.scala 247:36] - buf_state_en <= _T_52 @[axi4_to_ahb.scala 247:20] + node _T_50 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 245:34] + node _T_51 = eq(_T_50, UInt<1>("h01")) @[axi4_to_ahb.scala 245:41] + buf_write_in <= _T_51 @[axi4_to_ahb.scala 245:20] + node _T_52 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 246:46] + node _T_53 = mux(_T_52, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 246:26] + buf_nxtstate <= _T_53 @[axi4_to_ahb.scala 246:20] + node _T_54 = and(master_valid, UInt<1>("h01")) @[axi4_to_ahb.scala 247:36] + buf_state_en <= _T_54 @[axi4_to_ahb.scala 247:20] buf_wr_en <= buf_state_en @[axi4_to_ahb.scala 248:17] - node _T_53 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 249:54] - node _T_54 = and(buf_state_en, _T_53) @[axi4_to_ahb.scala 249:38] - buf_data_wr_en <= _T_54 @[axi4_to_ahb.scala 249:22] + node _T_55 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 249:54] + node _T_56 = and(buf_state_en, _T_55) @[axi4_to_ahb.scala 249:38] + buf_data_wr_en <= _T_56 @[axi4_to_ahb.scala 249:22] buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 250:27] - node _T_55 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 252:50] - node _T_56 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 252:89] - node _T_57 = add(UInt<1>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 181:52] - node _T_58 = tail(_T_57, 1) @[axi4_to_ahb.scala 181:52] - node _T_59 = mux(UInt<1>("h00"), _T_58, UInt<1>("h00")) @[axi4_to_ahb.scala 181:24] - node _T_60 = bits(_T_56, 0, 0) @[axi4_to_ahb.scala 182:44] - node _T_61 = geq(UInt<1>("h00"), _T_59) @[axi4_to_ahb.scala 182:62] - node _T_62 = and(_T_60, _T_61) @[axi4_to_ahb.scala 182:48] - node _T_63 = bits(_T_56, 1, 1) @[axi4_to_ahb.scala 182:44] - node _T_64 = geq(UInt<1>("h01"), _T_59) @[axi4_to_ahb.scala 182:62] - node _T_65 = and(_T_63, _T_64) @[axi4_to_ahb.scala 182:48] - node _T_66 = bits(_T_56, 2, 2) @[axi4_to_ahb.scala 182:44] - node _T_67 = geq(UInt<2>("h02"), _T_59) @[axi4_to_ahb.scala 182:62] - node _T_68 = and(_T_66, _T_67) @[axi4_to_ahb.scala 182:48] - node _T_69 = bits(_T_56, 3, 3) @[axi4_to_ahb.scala 182:44] - node _T_70 = geq(UInt<2>("h03"), _T_59) @[axi4_to_ahb.scala 182:62] - node _T_71 = and(_T_69, _T_70) @[axi4_to_ahb.scala 182:48] - node _T_72 = bits(_T_56, 4, 4) @[axi4_to_ahb.scala 182:44] - node _T_73 = geq(UInt<3>("h04"), _T_59) @[axi4_to_ahb.scala 182:62] - node _T_74 = and(_T_72, _T_73) @[axi4_to_ahb.scala 182:48] - node _T_75 = bits(_T_56, 5, 5) @[axi4_to_ahb.scala 182:44] - node _T_76 = geq(UInt<3>("h05"), _T_59) @[axi4_to_ahb.scala 182:62] - node _T_77 = and(_T_75, _T_76) @[axi4_to_ahb.scala 182:48] - node _T_78 = bits(_T_56, 6, 6) @[axi4_to_ahb.scala 182:44] - node _T_79 = geq(UInt<3>("h06"), _T_59) @[axi4_to_ahb.scala 182:62] - node _T_80 = and(_T_78, _T_79) @[axi4_to_ahb.scala 182:48] - node _T_81 = bits(_T_56, 7, 7) @[axi4_to_ahb.scala 182:44] - node _T_82 = geq(UInt<3>("h07"), _T_59) @[axi4_to_ahb.scala 182:62] - node _T_83 = and(_T_81, _T_82) @[axi4_to_ahb.scala 182:48] - node _T_84 = mux(_T_83, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16] - node _T_85 = mux(_T_80, UInt<3>("h06"), _T_84) @[Mux.scala 98:16] - node _T_86 = mux(_T_77, UInt<3>("h05"), _T_85) @[Mux.scala 98:16] - node _T_87 = mux(_T_74, UInt<3>("h04"), _T_86) @[Mux.scala 98:16] - node _T_88 = mux(_T_71, UInt<2>("h03"), _T_87) @[Mux.scala 98:16] - node _T_89 = mux(_T_68, UInt<2>("h02"), _T_88) @[Mux.scala 98:16] - node _T_90 = mux(_T_65, UInt<1>("h01"), _T_89) @[Mux.scala 98:16] - node _T_91 = mux(_T_62, UInt<1>("h00"), _T_90) @[Mux.scala 98:16] - node _T_92 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 252:138] - node _T_93 = mux(_T_55, _T_91, _T_92) @[axi4_to_ahb.scala 252:30] - buf_cmd_byte_ptr <= _T_93 @[axi4_to_ahb.scala 252:24] + node _T_57 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 252:50] + node _T_58 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 252:89] + node _T_59 = add(UInt<1>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 181:52] + node _T_60 = tail(_T_59, 1) @[axi4_to_ahb.scala 181:52] + node _T_61 = mux(UInt<1>("h00"), _T_60, UInt<1>("h00")) @[axi4_to_ahb.scala 181:24] + node _T_62 = bits(_T_58, 0, 0) @[axi4_to_ahb.scala 182:44] + node _T_63 = geq(UInt<1>("h00"), _T_61) @[axi4_to_ahb.scala 182:62] + node _T_64 = and(_T_62, _T_63) @[axi4_to_ahb.scala 182:48] + node _T_65 = bits(_T_58, 1, 1) @[axi4_to_ahb.scala 182:44] + node _T_66 = geq(UInt<1>("h01"), _T_61) @[axi4_to_ahb.scala 182:62] + node _T_67 = and(_T_65, _T_66) @[axi4_to_ahb.scala 182:48] + node _T_68 = bits(_T_58, 2, 2) @[axi4_to_ahb.scala 182:44] + node _T_69 = geq(UInt<2>("h02"), _T_61) @[axi4_to_ahb.scala 182:62] + node _T_70 = and(_T_68, _T_69) @[axi4_to_ahb.scala 182:48] + node _T_71 = bits(_T_58, 3, 3) @[axi4_to_ahb.scala 182:44] + node _T_72 = geq(UInt<2>("h03"), _T_61) @[axi4_to_ahb.scala 182:62] + node _T_73 = and(_T_71, _T_72) @[axi4_to_ahb.scala 182:48] + node _T_74 = bits(_T_58, 4, 4) @[axi4_to_ahb.scala 182:44] + node _T_75 = geq(UInt<3>("h04"), _T_61) @[axi4_to_ahb.scala 182:62] + node _T_76 = and(_T_74, _T_75) @[axi4_to_ahb.scala 182:48] + node _T_77 = bits(_T_58, 5, 5) @[axi4_to_ahb.scala 182:44] + node _T_78 = geq(UInt<3>("h05"), _T_61) @[axi4_to_ahb.scala 182:62] + node _T_79 = and(_T_77, _T_78) @[axi4_to_ahb.scala 182:48] + node _T_80 = bits(_T_58, 6, 6) @[axi4_to_ahb.scala 182:44] + node _T_81 = geq(UInt<3>("h06"), _T_61) @[axi4_to_ahb.scala 182:62] + node _T_82 = and(_T_80, _T_81) @[axi4_to_ahb.scala 182:48] + node _T_83 = bits(_T_58, 7, 7) @[axi4_to_ahb.scala 182:44] + node _T_84 = geq(UInt<3>("h07"), _T_61) @[axi4_to_ahb.scala 182:62] + node _T_85 = and(_T_83, _T_84) @[axi4_to_ahb.scala 182:48] + node _T_86 = mux(_T_85, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16] + node _T_87 = mux(_T_82, UInt<3>("h06"), _T_86) @[Mux.scala 98:16] + node _T_88 = mux(_T_79, UInt<3>("h05"), _T_87) @[Mux.scala 98:16] + node _T_89 = mux(_T_76, UInt<3>("h04"), _T_88) @[Mux.scala 98:16] + node _T_90 = mux(_T_73, UInt<2>("h03"), _T_89) @[Mux.scala 98:16] + node _T_91 = mux(_T_70, UInt<2>("h02"), _T_90) @[Mux.scala 98:16] + node _T_92 = mux(_T_67, UInt<1>("h01"), _T_91) @[Mux.scala 98:16] + node _T_93 = mux(_T_64, UInt<1>("h00"), _T_92) @[Mux.scala 98:16] + node _T_94 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 252:138] + node _T_95 = mux(_T_57, _T_93, _T_94) @[axi4_to_ahb.scala 252:30] + buf_cmd_byte_ptr <= _T_95 @[axi4_to_ahb.scala 252:24] bypass_en <= buf_state_en @[axi4_to_ahb.scala 253:17] - node _T_94 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 254:51] - node _T_95 = and(bypass_en, _T_94) @[axi4_to_ahb.scala 254:35] - rd_bypass_idle <= _T_95 @[axi4_to_ahb.scala 254:22] - node _T_96 = bits(bypass_en, 0, 0) @[Bitwise.scala 72:15] - node _T_97 = mux(_T_96, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_98 = and(_T_97, UInt<2>("h02")) @[axi4_to_ahb.scala 255:45] - io.ahb_htrans <= _T_98 @[axi4_to_ahb.scala 255:21] + node _T_96 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 254:51] + node _T_97 = and(bypass_en, _T_96) @[axi4_to_ahb.scala 254:35] + rd_bypass_idle <= _T_97 @[axi4_to_ahb.scala 254:22] + node _T_98 = bits(bypass_en, 0, 0) @[Bitwise.scala 72:15] + node _T_99 = mux(_T_98, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_100 = and(_T_99, UInt<2>("h02")) @[axi4_to_ahb.scala 255:45] + io.ahb_htrans <= _T_100 @[axi4_to_ahb.scala 255:21] skip @[Conditional.scala 40:58] else : @[Conditional.scala 39:67] - node _T_99 = eq(UInt<3>("h01"), buf_state) @[Conditional.scala 37:30] - when _T_99 : @[Conditional.scala 39:67] - node _T_100 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 259:54] - node _T_101 = eq(_T_100, UInt<1>("h00")) @[axi4_to_ahb.scala 259:61] - node _T_102 = and(master_valid, _T_101) @[axi4_to_ahb.scala 259:41] - node _T_103 = bits(_T_102, 0, 0) @[axi4_to_ahb.scala 259:82] - node _T_104 = mux(_T_103, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 259:26] - buf_nxtstate <= _T_104 @[axi4_to_ahb.scala 259:20] - node _T_105 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 260:51] - node _T_106 = neq(_T_105, UInt<1>("h00")) @[axi4_to_ahb.scala 260:58] - node _T_107 = and(ahb_hready_q, _T_106) @[axi4_to_ahb.scala 260:36] - node _T_108 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 260:72] - node _T_109 = and(_T_107, _T_108) @[axi4_to_ahb.scala 260:70] - buf_state_en <= _T_109 @[axi4_to_ahb.scala 260:20] - node _T_110 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 261:34] - node _T_111 = and(buf_state_en, _T_110) @[axi4_to_ahb.scala 261:32] - cmd_done <= _T_111 @[axi4_to_ahb.scala 261:16] + node _T_101 = eq(UInt<3>("h01"), buf_state) @[Conditional.scala 37:30] + when _T_101 : @[Conditional.scala 39:67] + node _T_102 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 259:54] + node _T_103 = eq(_T_102, UInt<1>("h00")) @[axi4_to_ahb.scala 259:61] + node _T_104 = and(master_valid, _T_103) @[axi4_to_ahb.scala 259:41] + node _T_105 = bits(_T_104, 0, 0) @[axi4_to_ahb.scala 259:82] + node _T_106 = mux(_T_105, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 259:26] + buf_nxtstate <= _T_106 @[axi4_to_ahb.scala 259:20] + node _T_107 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 260:51] + node _T_108 = neq(_T_107, UInt<1>("h00")) @[axi4_to_ahb.scala 260:58] + node _T_109 = and(ahb_hready_q, _T_108) @[axi4_to_ahb.scala 260:36] + node _T_110 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 260:72] + node _T_111 = and(_T_109, _T_110) @[axi4_to_ahb.scala 260:70] + buf_state_en <= _T_111 @[axi4_to_ahb.scala 260:20] + node _T_112 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 261:34] + node _T_113 = and(buf_state_en, _T_112) @[axi4_to_ahb.scala 261:32] + cmd_done <= _T_113 @[axi4_to_ahb.scala 261:16] slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 262:20] - node _T_112 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 263:52] - node _T_113 = neq(_T_112, UInt<1>("h00")) @[axi4_to_ahb.scala 263:59] - node _T_114 = and(ahb_hready_q, _T_113) @[axi4_to_ahb.scala 263:37] - node _T_115 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 263:73] - node _T_116 = and(_T_114, _T_115) @[axi4_to_ahb.scala 263:71] - node _T_117 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 263:122] - node _T_118 = eq(_T_117, UInt<1>("h00")) @[axi4_to_ahb.scala 263:129] - node _T_119 = and(master_valid, _T_118) @[axi4_to_ahb.scala 263:109] - node _T_120 = bits(_T_119, 0, 0) @[axi4_to_ahb.scala 263:150] - node _T_121 = mux(_T_120, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 263:94] - node _T_122 = eq(_T_121, UInt<3>("h06")) @[axi4_to_ahb.scala 263:174] - node _T_123 = and(_T_116, _T_122) @[axi4_to_ahb.scala 263:88] - master_ready <= _T_123 @[axi4_to_ahb.scala 263:20] + node _T_114 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 263:52] + node _T_115 = neq(_T_114, UInt<1>("h00")) @[axi4_to_ahb.scala 263:59] + node _T_116 = and(ahb_hready_q, _T_115) @[axi4_to_ahb.scala 263:37] + node _T_117 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 263:73] + node _T_118 = and(_T_116, _T_117) @[axi4_to_ahb.scala 263:71] + node _T_119 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 263:122] + node _T_120 = eq(_T_119, UInt<1>("h00")) @[axi4_to_ahb.scala 263:129] + node _T_121 = and(master_valid, _T_120) @[axi4_to_ahb.scala 263:109] + node _T_122 = bits(_T_121, 0, 0) @[axi4_to_ahb.scala 263:150] + node _T_123 = mux(_T_122, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 263:94] + node _T_124 = eq(_T_123, UInt<3>("h06")) @[axi4_to_ahb.scala 263:174] + node _T_125 = and(_T_118, _T_124) @[axi4_to_ahb.scala 263:88] + master_ready <= _T_125 @[axi4_to_ahb.scala 263:20] buf_wr_en <= master_ready @[axi4_to_ahb.scala 264:17] - node _T_124 = and(master_ready, master_valid) @[axi4_to_ahb.scala 265:33] - bypass_en <= _T_124 @[axi4_to_ahb.scala 265:17] - node _T_125 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 266:47] - node _T_126 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 266:62] - node _T_127 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 266:78] - node _T_128 = mux(_T_125, _T_126, _T_127) @[axi4_to_ahb.scala 266:30] - buf_cmd_byte_ptr <= _T_128 @[axi4_to_ahb.scala 266:24] - node _T_129 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 267:44] - node _T_130 = or(_T_129, bypass_en) @[axi4_to_ahb.scala 267:58] - node _T_131 = bits(_T_130, 0, 0) @[Bitwise.scala 72:15] - node _T_132 = mux(_T_131, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_133 = and(UInt<2>("h02"), _T_132) @[axi4_to_ahb.scala 267:32] - io.ahb_htrans <= _T_133 @[axi4_to_ahb.scala 267:21] + node _T_126 = and(master_ready, master_valid) @[axi4_to_ahb.scala 265:33] + bypass_en <= _T_126 @[axi4_to_ahb.scala 265:17] + node _T_127 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 266:47] + node _T_128 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 266:62] + node _T_129 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 266:78] + node _T_130 = mux(_T_127, _T_128, _T_129) @[axi4_to_ahb.scala 266:30] + buf_cmd_byte_ptr <= _T_130 @[axi4_to_ahb.scala 266:24] + node _T_131 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 267:44] + node _T_132 = or(_T_131, bypass_en) @[axi4_to_ahb.scala 267:58] + node _T_133 = bits(_T_132, 0, 0) @[Bitwise.scala 72:15] + node _T_134 = mux(_T_133, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_135 = and(UInt<2>("h02"), _T_134) @[axi4_to_ahb.scala 267:32] + io.ahb_htrans <= _T_135 @[axi4_to_ahb.scala 267:21] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_134 = eq(UInt<3>("h06"), buf_state) @[Conditional.scala 37:30] - when _T_134 : @[Conditional.scala 39:67] - node _T_135 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 271:39] - node _T_136 = and(ahb_hready_q, _T_135) @[axi4_to_ahb.scala 271:37] - node _T_137 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 271:82] - node _T_138 = eq(_T_137, UInt<1>("h01")) @[axi4_to_ahb.scala 271:89] - node _T_139 = and(master_valid, _T_138) @[axi4_to_ahb.scala 271:70] - node _T_140 = eq(_T_139, UInt<1>("h00")) @[axi4_to_ahb.scala 271:55] - node _T_141 = and(_T_136, _T_140) @[axi4_to_ahb.scala 271:53] - master_ready <= _T_141 @[axi4_to_ahb.scala 271:20] - node _T_142 = and(master_valid, master_ready) @[axi4_to_ahb.scala 272:34] - node _T_143 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 272:62] - node _T_144 = eq(_T_143, UInt<1>("h00")) @[axi4_to_ahb.scala 272:69] - node _T_145 = and(_T_142, _T_144) @[axi4_to_ahb.scala 272:49] - buf_wr_en <= _T_145 @[axi4_to_ahb.scala 272:17] - node _T_146 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 273:45] - node _T_147 = and(master_valid, master_ready) @[axi4_to_ahb.scala 273:82] - node _T_148 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 273:110] - node _T_149 = eq(_T_148, UInt<1>("h00")) @[axi4_to_ahb.scala 273:117] - node _T_150 = and(_T_147, _T_149) @[axi4_to_ahb.scala 273:97] - node _T_151 = bits(_T_150, 0, 0) @[axi4_to_ahb.scala 273:138] - node _T_152 = mux(_T_151, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 273:67] - node _T_153 = mux(_T_146, UInt<3>("h07"), _T_152) @[axi4_to_ahb.scala 273:26] - buf_nxtstate <= _T_153 @[axi4_to_ahb.scala 273:20] - node _T_154 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 274:37] - buf_state_en <= _T_154 @[axi4_to_ahb.scala 274:20] + node _T_136 = eq(UInt<3>("h06"), buf_state) @[Conditional.scala 37:30] + when _T_136 : @[Conditional.scala 39:67] + node _T_137 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 271:39] + node _T_138 = and(ahb_hready_q, _T_137) @[axi4_to_ahb.scala 271:37] + node _T_139 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 271:82] + node _T_140 = eq(_T_139, UInt<1>("h01")) @[axi4_to_ahb.scala 271:89] + node _T_141 = and(master_valid, _T_140) @[axi4_to_ahb.scala 271:70] + node _T_142 = eq(_T_141, UInt<1>("h00")) @[axi4_to_ahb.scala 271:55] + node _T_143 = and(_T_138, _T_142) @[axi4_to_ahb.scala 271:53] + master_ready <= _T_143 @[axi4_to_ahb.scala 271:20] + node _T_144 = and(master_valid, master_ready) @[axi4_to_ahb.scala 272:34] + node _T_145 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 272:62] + node _T_146 = eq(_T_145, UInt<1>("h00")) @[axi4_to_ahb.scala 272:69] + node _T_147 = and(_T_144, _T_146) @[axi4_to_ahb.scala 272:49] + buf_wr_en <= _T_147 @[axi4_to_ahb.scala 272:17] + node _T_148 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 273:45] + node _T_149 = and(master_valid, master_ready) @[axi4_to_ahb.scala 273:82] + node _T_150 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 273:110] + node _T_151 = eq(_T_150, UInt<1>("h00")) @[axi4_to_ahb.scala 273:117] + node _T_152 = and(_T_149, _T_151) @[axi4_to_ahb.scala 273:97] + node _T_153 = bits(_T_152, 0, 0) @[axi4_to_ahb.scala 273:138] + node _T_154 = mux(_T_153, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 273:67] + node _T_155 = mux(_T_148, UInt<3>("h07"), _T_154) @[axi4_to_ahb.scala 273:26] + buf_nxtstate <= _T_155 @[axi4_to_ahb.scala 273:20] + node _T_156 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 274:37] + buf_state_en <= _T_156 @[axi4_to_ahb.scala 274:20] buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 275:22] slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 276:23] slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 277:23] - node _T_155 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 278:41] - node _T_156 = and(buf_state_en, _T_155) @[axi4_to_ahb.scala 278:39] - slave_valid_pre <= _T_156 @[axi4_to_ahb.scala 278:23] - node _T_157 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 279:34] - node _T_158 = and(buf_state_en, _T_157) @[axi4_to_ahb.scala 279:32] - cmd_done <= _T_158 @[axi4_to_ahb.scala 279:16] - node _T_159 = and(master_ready, master_valid) @[axi4_to_ahb.scala 280:33] - node _T_160 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 280:64] - node _T_161 = and(_T_159, _T_160) @[axi4_to_ahb.scala 280:48] - node _T_162 = and(_T_161, buf_state_en) @[axi4_to_ahb.scala 280:79] - bypass_en <= _T_162 @[axi4_to_ahb.scala 280:17] - node _T_163 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 281:47] - node _T_164 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 281:62] - node _T_165 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 281:78] - node _T_166 = mux(_T_163, _T_164, _T_165) @[axi4_to_ahb.scala 281:30] - buf_cmd_byte_ptr <= _T_166 @[axi4_to_ahb.scala 281:24] - node _T_167 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 282:59] - node _T_168 = and(_T_167, buf_state_en) @[axi4_to_ahb.scala 282:74] - node _T_169 = eq(_T_168, UInt<1>("h00")) @[axi4_to_ahb.scala 282:43] - node _T_170 = bits(_T_169, 0, 0) @[Bitwise.scala 72:15] - node _T_171 = mux(_T_170, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_172 = and(UInt<2>("h02"), _T_171) @[axi4_to_ahb.scala 282:32] - io.ahb_htrans <= _T_172 @[axi4_to_ahb.scala 282:21] + node _T_157 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 278:41] + node _T_158 = and(buf_state_en, _T_157) @[axi4_to_ahb.scala 278:39] + slave_valid_pre <= _T_158 @[axi4_to_ahb.scala 278:23] + node _T_159 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 279:34] + node _T_160 = and(buf_state_en, _T_159) @[axi4_to_ahb.scala 279:32] + cmd_done <= _T_160 @[axi4_to_ahb.scala 279:16] + node _T_161 = and(master_ready, master_valid) @[axi4_to_ahb.scala 280:33] + node _T_162 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 280:64] + node _T_163 = and(_T_161, _T_162) @[axi4_to_ahb.scala 280:48] + node _T_164 = and(_T_163, buf_state_en) @[axi4_to_ahb.scala 280:79] + bypass_en <= _T_164 @[axi4_to_ahb.scala 280:17] + node _T_165 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 281:47] + node _T_166 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 281:62] + node _T_167 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 281:78] + node _T_168 = mux(_T_165, _T_166, _T_167) @[axi4_to_ahb.scala 281:30] + buf_cmd_byte_ptr <= _T_168 @[axi4_to_ahb.scala 281:24] + node _T_169 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 282:59] + node _T_170 = and(_T_169, buf_state_en) @[axi4_to_ahb.scala 282:74] + node _T_171 = eq(_T_170, UInt<1>("h00")) @[axi4_to_ahb.scala 282:43] + node _T_172 = bits(_T_171, 0, 0) @[Bitwise.scala 72:15] + node _T_173 = mux(_T_172, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_174 = and(UInt<2>("h02"), _T_173) @[axi4_to_ahb.scala 282:32] + io.ahb_htrans <= _T_174 @[axi4_to_ahb.scala 282:21] slvbuf_wr_en <= buf_wr_en @[axi4_to_ahb.scala 283:20] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_173 = eq(UInt<3>("h07"), buf_state) @[Conditional.scala 37:30] - when _T_173 : @[Conditional.scala 39:67] + node _T_175 = eq(UInt<3>("h07"), buf_state) @[Conditional.scala 37:30] + when _T_175 : @[Conditional.scala 39:67] buf_nxtstate <= UInt<3>("h03") @[axi4_to_ahb.scala 287:20] - node _T_174 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 288:51] - node _T_175 = neq(_T_174, UInt<1>("h00")) @[axi4_to_ahb.scala 288:58] - node _T_176 = and(ahb_hready_q, _T_175) @[axi4_to_ahb.scala 288:36] - node _T_177 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 288:72] - node _T_178 = and(_T_176, _T_177) @[axi4_to_ahb.scala 288:70] - buf_state_en <= _T_178 @[axi4_to_ahb.scala 288:20] + node _T_176 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 288:51] + node _T_177 = neq(_T_176, UInt<1>("h00")) @[axi4_to_ahb.scala 288:58] + node _T_178 = and(ahb_hready_q, _T_177) @[axi4_to_ahb.scala 288:36] + node _T_179 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 288:72] + node _T_180 = and(_T_178, _T_179) @[axi4_to_ahb.scala 288:70] + buf_state_en <= _T_180 @[axi4_to_ahb.scala 288:20] slave_valid_pre <= buf_state_en @[axi4_to_ahb.scala 289:23] slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 290:20] - node _T_179 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 291:35] - buf_cmd_byte_ptr <= _T_179 @[axi4_to_ahb.scala 291:24] - node _T_180 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 292:47] - node _T_181 = bits(_T_180, 0, 0) @[Bitwise.scala 72:15] - node _T_182 = mux(_T_181, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_183 = and(UInt<2>("h02"), _T_182) @[axi4_to_ahb.scala 292:37] - io.ahb_htrans <= _T_183 @[axi4_to_ahb.scala 292:21] + node _T_181 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 291:35] + buf_cmd_byte_ptr <= _T_181 @[axi4_to_ahb.scala 291:24] + node _T_182 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 292:47] + node _T_183 = bits(_T_182, 0, 0) @[Bitwise.scala 72:15] + node _T_184 = mux(_T_183, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_185 = and(UInt<2>("h02"), _T_184) @[axi4_to_ahb.scala 292:37] + io.ahb_htrans <= _T_185 @[axi4_to_ahb.scala 292:21] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_184 = eq(UInt<3>("h03"), buf_state) @[Conditional.scala 37:30] - when _T_184 : @[Conditional.scala 39:67] + node _T_186 = eq(UInt<3>("h03"), buf_state) @[Conditional.scala 37:30] + when _T_186 : @[Conditional.scala 39:67] buf_nxtstate <= UInt<3>("h05") @[axi4_to_ahb.scala 296:20] - node _T_185 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 297:37] - buf_state_en <= _T_185 @[axi4_to_ahb.scala 297:20] + node _T_187 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 297:37] + buf_state_en <= _T_187 @[axi4_to_ahb.scala 297:20] buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 298:22] slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 299:23] slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 300:23] slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 301:20] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_186 = eq(UInt<3>("h02"), buf_state) @[Conditional.scala 37:30] - when _T_186 : @[Conditional.scala 39:67] + node _T_188 = eq(UInt<3>("h02"), buf_state) @[Conditional.scala 37:30] + when _T_188 : @[Conditional.scala 39:67] buf_nxtstate <= UInt<3>("h04") @[axi4_to_ahb.scala 305:20] - node _T_187 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 306:33] - node _T_188 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 306:63] - node _T_189 = neq(_T_188, UInt<1>("h00")) @[axi4_to_ahb.scala 306:70] - node _T_190 = and(_T_187, _T_189) @[axi4_to_ahb.scala 306:48] - trxn_done <= _T_190 @[axi4_to_ahb.scala 306:17] + node _T_189 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 306:33] + node _T_190 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 306:63] + node _T_191 = neq(_T_190, UInt<1>("h00")) @[axi4_to_ahb.scala 306:70] + node _T_192 = and(_T_189, _T_191) @[axi4_to_ahb.scala 306:48] + trxn_done <= _T_192 @[axi4_to_ahb.scala 306:17] buf_state_en <= trxn_done @[axi4_to_ahb.scala 307:20] buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 308:27] slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 309:20] - node _T_191 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 310:47] - node _T_192 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 310:85] - node _T_193 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 310:103] - node _T_194 = add(_T_192, UInt<1>("h01")) @[axi4_to_ahb.scala 181:52] - node _T_195 = tail(_T_194, 1) @[axi4_to_ahb.scala 181:52] - node _T_196 = mux(UInt<1>("h01"), _T_195, _T_192) @[axi4_to_ahb.scala 181:24] - node _T_197 = bits(_T_193, 0, 0) @[axi4_to_ahb.scala 182:44] - node _T_198 = geq(UInt<1>("h00"), _T_196) @[axi4_to_ahb.scala 182:62] - node _T_199 = and(_T_197, _T_198) @[axi4_to_ahb.scala 182:48] - node _T_200 = bits(_T_193, 1, 1) @[axi4_to_ahb.scala 182:44] - node _T_201 = geq(UInt<1>("h01"), _T_196) @[axi4_to_ahb.scala 182:62] - node _T_202 = and(_T_200, _T_201) @[axi4_to_ahb.scala 182:48] - node _T_203 = bits(_T_193, 2, 2) @[axi4_to_ahb.scala 182:44] - node _T_204 = geq(UInt<2>("h02"), _T_196) @[axi4_to_ahb.scala 182:62] - node _T_205 = and(_T_203, _T_204) @[axi4_to_ahb.scala 182:48] - node _T_206 = bits(_T_193, 3, 3) @[axi4_to_ahb.scala 182:44] - node _T_207 = geq(UInt<2>("h03"), _T_196) @[axi4_to_ahb.scala 182:62] - node _T_208 = and(_T_206, _T_207) @[axi4_to_ahb.scala 182:48] - node _T_209 = bits(_T_193, 4, 4) @[axi4_to_ahb.scala 182:44] - node _T_210 = geq(UInt<3>("h04"), _T_196) @[axi4_to_ahb.scala 182:62] - node _T_211 = and(_T_209, _T_210) @[axi4_to_ahb.scala 182:48] - node _T_212 = bits(_T_193, 5, 5) @[axi4_to_ahb.scala 182:44] - node _T_213 = geq(UInt<3>("h05"), _T_196) @[axi4_to_ahb.scala 182:62] - node _T_214 = and(_T_212, _T_213) @[axi4_to_ahb.scala 182:48] - node _T_215 = bits(_T_193, 6, 6) @[axi4_to_ahb.scala 182:44] - node _T_216 = geq(UInt<3>("h06"), _T_196) @[axi4_to_ahb.scala 182:62] - node _T_217 = and(_T_215, _T_216) @[axi4_to_ahb.scala 182:48] - node _T_218 = bits(_T_193, 7, 7) @[axi4_to_ahb.scala 182:44] - node _T_219 = geq(UInt<3>("h07"), _T_196) @[axi4_to_ahb.scala 182:62] - node _T_220 = and(_T_218, _T_219) @[axi4_to_ahb.scala 182:48] - node _T_221 = mux(_T_220, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16] - node _T_222 = mux(_T_217, UInt<3>("h06"), _T_221) @[Mux.scala 98:16] - node _T_223 = mux(_T_214, UInt<3>("h05"), _T_222) @[Mux.scala 98:16] - node _T_224 = mux(_T_211, UInt<3>("h04"), _T_223) @[Mux.scala 98:16] - node _T_225 = mux(_T_208, UInt<2>("h03"), _T_224) @[Mux.scala 98:16] - node _T_226 = mux(_T_205, UInt<2>("h02"), _T_225) @[Mux.scala 98:16] - node _T_227 = mux(_T_202, UInt<1>("h01"), _T_226) @[Mux.scala 98:16] - node _T_228 = mux(_T_199, UInt<1>("h00"), _T_227) @[Mux.scala 98:16] - node _T_229 = mux(_T_191, _T_228, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 310:30] - buf_cmd_byte_ptr <= _T_229 @[axi4_to_ahb.scala 310:24] - node _T_230 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 311:65] - node _T_231 = or(buf_aligned, _T_230) @[axi4_to_ahb.scala 311:44] - node _T_232 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 311:127] - node _T_233 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 311:145] - node _T_234 = add(_T_232, UInt<1>("h01")) @[axi4_to_ahb.scala 181:52] - node _T_235 = tail(_T_234, 1) @[axi4_to_ahb.scala 181:52] - node _T_236 = mux(UInt<1>("h01"), _T_235, _T_232) @[axi4_to_ahb.scala 181:24] - node _T_237 = bits(_T_233, 0, 0) @[axi4_to_ahb.scala 182:44] - node _T_238 = geq(UInt<1>("h00"), _T_236) @[axi4_to_ahb.scala 182:62] - node _T_239 = and(_T_237, _T_238) @[axi4_to_ahb.scala 182:48] - node _T_240 = bits(_T_233, 1, 1) @[axi4_to_ahb.scala 182:44] - node _T_241 = geq(UInt<1>("h01"), _T_236) @[axi4_to_ahb.scala 182:62] - node _T_242 = and(_T_240, _T_241) @[axi4_to_ahb.scala 182:48] - node _T_243 = bits(_T_233, 2, 2) @[axi4_to_ahb.scala 182:44] - node _T_244 = geq(UInt<2>("h02"), _T_236) @[axi4_to_ahb.scala 182:62] - node _T_245 = and(_T_243, _T_244) @[axi4_to_ahb.scala 182:48] - node _T_246 = bits(_T_233, 3, 3) @[axi4_to_ahb.scala 182:44] - node _T_247 = geq(UInt<2>("h03"), _T_236) @[axi4_to_ahb.scala 182:62] - node _T_248 = and(_T_246, _T_247) @[axi4_to_ahb.scala 182:48] - node _T_249 = bits(_T_233, 4, 4) @[axi4_to_ahb.scala 182:44] - node _T_250 = geq(UInt<3>("h04"), _T_236) @[axi4_to_ahb.scala 182:62] - node _T_251 = and(_T_249, _T_250) @[axi4_to_ahb.scala 182:48] - node _T_252 = bits(_T_233, 5, 5) @[axi4_to_ahb.scala 182:44] - node _T_253 = geq(UInt<3>("h05"), _T_236) @[axi4_to_ahb.scala 182:62] - node _T_254 = and(_T_252, _T_253) @[axi4_to_ahb.scala 182:48] - node _T_255 = bits(_T_233, 6, 6) @[axi4_to_ahb.scala 182:44] - node _T_256 = geq(UInt<3>("h06"), _T_236) @[axi4_to_ahb.scala 182:62] - node _T_257 = and(_T_255, _T_256) @[axi4_to_ahb.scala 182:48] - node _T_258 = bits(_T_233, 7, 7) @[axi4_to_ahb.scala 182:44] - node _T_259 = geq(UInt<3>("h07"), _T_236) @[axi4_to_ahb.scala 182:62] - node _T_260 = and(_T_258, _T_259) @[axi4_to_ahb.scala 182:48] - node _T_261 = mux(_T_260, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16] - node _T_262 = mux(_T_257, UInt<3>("h06"), _T_261) @[Mux.scala 98:16] - node _T_263 = mux(_T_254, UInt<3>("h05"), _T_262) @[Mux.scala 98:16] - node _T_264 = mux(_T_251, UInt<3>("h04"), _T_263) @[Mux.scala 98:16] - node _T_265 = mux(_T_248, UInt<2>("h03"), _T_264) @[Mux.scala 98:16] - node _T_266 = mux(_T_245, UInt<2>("h02"), _T_265) @[Mux.scala 98:16] - node _T_267 = mux(_T_242, UInt<1>("h01"), _T_266) @[Mux.scala 98:16] - node _T_268 = mux(_T_239, UInt<1>("h00"), _T_267) @[Mux.scala 98:16] - node _T_269 = dshr(buf_byteen, _T_268) @[axi4_to_ahb.scala 311:92] - node _T_270 = bits(_T_269, 0, 0) @[axi4_to_ahb.scala 311:92] - node _T_271 = eq(_T_270, UInt<1>("h00")) @[axi4_to_ahb.scala 311:163] - node _T_272 = or(_T_231, _T_271) @[axi4_to_ahb.scala 311:79] - node _T_273 = and(trxn_done, _T_272) @[axi4_to_ahb.scala 311:29] - cmd_done <= _T_273 @[axi4_to_ahb.scala 311:16] - node _T_274 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 312:43] - node _T_275 = eq(_T_274, UInt<1>("h00")) @[axi4_to_ahb.scala 312:32] - node _T_276 = bits(_T_275, 0, 0) @[Bitwise.scala 72:15] - node _T_277 = mux(_T_276, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_278 = and(_T_277, UInt<2>("h02")) @[axi4_to_ahb.scala 312:57] - io.ahb_htrans <= _T_278 @[axi4_to_ahb.scala 312:21] + node _T_193 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 310:47] + node _T_194 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 310:85] + node _T_195 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 310:103] + node _T_196 = add(_T_194, UInt<1>("h01")) @[axi4_to_ahb.scala 181:52] + node _T_197 = tail(_T_196, 1) @[axi4_to_ahb.scala 181:52] + node _T_198 = mux(UInt<1>("h01"), _T_197, _T_194) @[axi4_to_ahb.scala 181:24] + node _T_199 = bits(_T_195, 0, 0) @[axi4_to_ahb.scala 182:44] + node _T_200 = geq(UInt<1>("h00"), _T_198) @[axi4_to_ahb.scala 182:62] + node _T_201 = and(_T_199, _T_200) @[axi4_to_ahb.scala 182:48] + node _T_202 = bits(_T_195, 1, 1) @[axi4_to_ahb.scala 182:44] + node _T_203 = geq(UInt<1>("h01"), _T_198) @[axi4_to_ahb.scala 182:62] + node _T_204 = and(_T_202, _T_203) @[axi4_to_ahb.scala 182:48] + node _T_205 = bits(_T_195, 2, 2) @[axi4_to_ahb.scala 182:44] + node _T_206 = geq(UInt<2>("h02"), _T_198) @[axi4_to_ahb.scala 182:62] + node _T_207 = and(_T_205, _T_206) @[axi4_to_ahb.scala 182:48] + node _T_208 = bits(_T_195, 3, 3) @[axi4_to_ahb.scala 182:44] + node _T_209 = geq(UInt<2>("h03"), _T_198) @[axi4_to_ahb.scala 182:62] + node _T_210 = and(_T_208, _T_209) @[axi4_to_ahb.scala 182:48] + node _T_211 = bits(_T_195, 4, 4) @[axi4_to_ahb.scala 182:44] + node _T_212 = geq(UInt<3>("h04"), _T_198) @[axi4_to_ahb.scala 182:62] + node _T_213 = and(_T_211, _T_212) @[axi4_to_ahb.scala 182:48] + node _T_214 = bits(_T_195, 5, 5) @[axi4_to_ahb.scala 182:44] + node _T_215 = geq(UInt<3>("h05"), _T_198) @[axi4_to_ahb.scala 182:62] + node _T_216 = and(_T_214, _T_215) @[axi4_to_ahb.scala 182:48] + node _T_217 = bits(_T_195, 6, 6) @[axi4_to_ahb.scala 182:44] + node _T_218 = geq(UInt<3>("h06"), _T_198) @[axi4_to_ahb.scala 182:62] + node _T_219 = and(_T_217, _T_218) @[axi4_to_ahb.scala 182:48] + node _T_220 = bits(_T_195, 7, 7) @[axi4_to_ahb.scala 182:44] + node _T_221 = geq(UInt<3>("h07"), _T_198) @[axi4_to_ahb.scala 182:62] + node _T_222 = and(_T_220, _T_221) @[axi4_to_ahb.scala 182:48] + node _T_223 = mux(_T_222, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16] + node _T_224 = mux(_T_219, UInt<3>("h06"), _T_223) @[Mux.scala 98:16] + node _T_225 = mux(_T_216, UInt<3>("h05"), _T_224) @[Mux.scala 98:16] + node _T_226 = mux(_T_213, UInt<3>("h04"), _T_225) @[Mux.scala 98:16] + node _T_227 = mux(_T_210, UInt<2>("h03"), _T_226) @[Mux.scala 98:16] + node _T_228 = mux(_T_207, UInt<2>("h02"), _T_227) @[Mux.scala 98:16] + node _T_229 = mux(_T_204, UInt<1>("h01"), _T_228) @[Mux.scala 98:16] + node _T_230 = mux(_T_201, UInt<1>("h00"), _T_229) @[Mux.scala 98:16] + node _T_231 = mux(_T_193, _T_230, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 310:30] + buf_cmd_byte_ptr <= _T_231 @[axi4_to_ahb.scala 310:24] + node _T_232 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 311:65] + node _T_233 = or(buf_aligned, _T_232) @[axi4_to_ahb.scala 311:44] + node _T_234 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 311:127] + node _T_235 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 311:145] + node _T_236 = add(_T_234, UInt<1>("h01")) @[axi4_to_ahb.scala 181:52] + node _T_237 = tail(_T_236, 1) @[axi4_to_ahb.scala 181:52] + node _T_238 = mux(UInt<1>("h01"), _T_237, _T_234) @[axi4_to_ahb.scala 181:24] + node _T_239 = bits(_T_235, 0, 0) @[axi4_to_ahb.scala 182:44] + node _T_240 = geq(UInt<1>("h00"), _T_238) @[axi4_to_ahb.scala 182:62] + node _T_241 = and(_T_239, _T_240) @[axi4_to_ahb.scala 182:48] + node _T_242 = bits(_T_235, 1, 1) @[axi4_to_ahb.scala 182:44] + node _T_243 = geq(UInt<1>("h01"), _T_238) @[axi4_to_ahb.scala 182:62] + node _T_244 = and(_T_242, _T_243) @[axi4_to_ahb.scala 182:48] + node _T_245 = bits(_T_235, 2, 2) @[axi4_to_ahb.scala 182:44] + node _T_246 = geq(UInt<2>("h02"), _T_238) @[axi4_to_ahb.scala 182:62] + node _T_247 = and(_T_245, _T_246) @[axi4_to_ahb.scala 182:48] + node _T_248 = bits(_T_235, 3, 3) @[axi4_to_ahb.scala 182:44] + node _T_249 = geq(UInt<2>("h03"), _T_238) @[axi4_to_ahb.scala 182:62] + node _T_250 = and(_T_248, _T_249) @[axi4_to_ahb.scala 182:48] + node _T_251 = bits(_T_235, 4, 4) @[axi4_to_ahb.scala 182:44] + node _T_252 = geq(UInt<3>("h04"), _T_238) @[axi4_to_ahb.scala 182:62] + node _T_253 = and(_T_251, _T_252) @[axi4_to_ahb.scala 182:48] + node _T_254 = bits(_T_235, 5, 5) @[axi4_to_ahb.scala 182:44] + node _T_255 = geq(UInt<3>("h05"), _T_238) @[axi4_to_ahb.scala 182:62] + node _T_256 = and(_T_254, _T_255) @[axi4_to_ahb.scala 182:48] + node _T_257 = bits(_T_235, 6, 6) @[axi4_to_ahb.scala 182:44] + node _T_258 = geq(UInt<3>("h06"), _T_238) @[axi4_to_ahb.scala 182:62] + node _T_259 = and(_T_257, _T_258) @[axi4_to_ahb.scala 182:48] + node _T_260 = bits(_T_235, 7, 7) @[axi4_to_ahb.scala 182:44] + node _T_261 = geq(UInt<3>("h07"), _T_238) @[axi4_to_ahb.scala 182:62] + node _T_262 = and(_T_260, _T_261) @[axi4_to_ahb.scala 182:48] + node _T_263 = mux(_T_262, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16] + node _T_264 = mux(_T_259, UInt<3>("h06"), _T_263) @[Mux.scala 98:16] + node _T_265 = mux(_T_256, UInt<3>("h05"), _T_264) @[Mux.scala 98:16] + node _T_266 = mux(_T_253, UInt<3>("h04"), _T_265) @[Mux.scala 98:16] + node _T_267 = mux(_T_250, UInt<2>("h03"), _T_266) @[Mux.scala 98:16] + node _T_268 = mux(_T_247, UInt<2>("h02"), _T_267) @[Mux.scala 98:16] + node _T_269 = mux(_T_244, UInt<1>("h01"), _T_268) @[Mux.scala 98:16] + node _T_270 = mux(_T_241, UInt<1>("h00"), _T_269) @[Mux.scala 98:16] + node _T_271 = dshr(buf_byteen, _T_270) @[axi4_to_ahb.scala 311:92] + node _T_272 = bits(_T_271, 0, 0) @[axi4_to_ahb.scala 311:92] + node _T_273 = eq(_T_272, UInt<1>("h00")) @[axi4_to_ahb.scala 311:163] + node _T_274 = or(_T_233, _T_273) @[axi4_to_ahb.scala 311:79] + node _T_275 = and(trxn_done, _T_274) @[axi4_to_ahb.scala 311:29] + cmd_done <= _T_275 @[axi4_to_ahb.scala 311:16] + node _T_276 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 312:43] + node _T_277 = eq(_T_276, UInt<1>("h00")) @[axi4_to_ahb.scala 312:32] + node _T_278 = bits(_T_277, 0, 0) @[Bitwise.scala 72:15] + node _T_279 = mux(_T_278, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_280 = and(_T_279, UInt<2>("h02")) @[axi4_to_ahb.scala 312:57] + io.ahb_htrans <= _T_280 @[axi4_to_ahb.scala 312:21] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_279 = eq(UInt<3>("h04"), buf_state) @[Conditional.scala 37:30] - when _T_279 : @[Conditional.scala 39:67] - node _T_280 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 316:34] - node _T_281 = or(_T_280, ahb_hresp_q) @[axi4_to_ahb.scala 316:50] - buf_state_en <= _T_281 @[axi4_to_ahb.scala 316:20] - node _T_282 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 317:35] - node _T_283 = or(_T_282, ahb_hresp_q) @[axi4_to_ahb.scala 317:51] - node _T_284 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 317:68] - node _T_285 = and(_T_283, _T_284) @[axi4_to_ahb.scala 317:66] - node _T_286 = and(_T_285, slave_ready) @[axi4_to_ahb.scala 317:81] - master_ready <= _T_286 @[axi4_to_ahb.scala 317:20] - node _T_287 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 318:42] - node _T_288 = or(ahb_hresp_q, _T_287) @[axi4_to_ahb.scala 318:40] - node _T_289 = bits(_T_288, 0, 0) @[axi4_to_ahb.scala 318:62] - node _T_290 = and(master_valid, master_ready) @[axi4_to_ahb.scala 318:90] - node _T_291 = bits(_T_290, 0, 0) @[axi4_to_ahb.scala 318:112] - node _T_292 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 318:131] - node _T_293 = eq(_T_292, UInt<1>("h01")) @[axi4_to_ahb.scala 318:138] - node _T_294 = mux(_T_293, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 318:119] - node _T_295 = mux(_T_291, _T_294, UInt<3>("h00")) @[axi4_to_ahb.scala 318:75] - node _T_296 = mux(_T_289, UInt<3>("h05"), _T_295) @[axi4_to_ahb.scala 318:26] - buf_nxtstate <= _T_296 @[axi4_to_ahb.scala 318:20] + node _T_281 = eq(UInt<3>("h04"), buf_state) @[Conditional.scala 37:30] + when _T_281 : @[Conditional.scala 39:67] + node _T_282 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 316:34] + node _T_283 = or(_T_282, ahb_hresp_q) @[axi4_to_ahb.scala 316:50] + buf_state_en <= _T_283 @[axi4_to_ahb.scala 316:20] + node _T_284 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 317:35] + node _T_285 = or(_T_284, ahb_hresp_q) @[axi4_to_ahb.scala 317:51] + node _T_286 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 317:68] + node _T_287 = and(_T_285, _T_286) @[axi4_to_ahb.scala 317:66] + node _T_288 = and(_T_287, slave_ready) @[axi4_to_ahb.scala 317:81] + master_ready <= _T_288 @[axi4_to_ahb.scala 317:20] + node _T_289 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 318:42] + node _T_290 = or(ahb_hresp_q, _T_289) @[axi4_to_ahb.scala 318:40] + node _T_291 = bits(_T_290, 0, 0) @[axi4_to_ahb.scala 318:62] + node _T_292 = and(master_valid, master_ready) @[axi4_to_ahb.scala 318:90] + node _T_293 = bits(_T_292, 0, 0) @[axi4_to_ahb.scala 318:112] + node _T_294 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 318:131] + node _T_295 = eq(_T_294, UInt<1>("h01")) @[axi4_to_ahb.scala 318:138] + node _T_296 = mux(_T_295, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 318:119] + node _T_297 = mux(_T_293, _T_296, UInt<3>("h00")) @[axi4_to_ahb.scala 318:75] + node _T_298 = mux(_T_291, UInt<3>("h05"), _T_297) @[axi4_to_ahb.scala 318:26] + buf_nxtstate <= _T_298 @[axi4_to_ahb.scala 318:20] slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 319:23] slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 320:23] - node _T_297 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 321:34] - node _T_298 = eq(_T_297, UInt<1>("h01")) @[axi4_to_ahb.scala 321:41] - buf_write_in <= _T_298 @[axi4_to_ahb.scala 321:20] - node _T_299 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 322:50] - node _T_300 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 322:78] - node _T_301 = or(_T_299, _T_300) @[axi4_to_ahb.scala 322:62] - node _T_302 = and(buf_state_en, _T_301) @[axi4_to_ahb.scala 322:33] - buf_wr_en <= _T_302 @[axi4_to_ahb.scala 322:17] + node _T_299 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 321:34] + node _T_300 = eq(_T_299, UInt<1>("h01")) @[axi4_to_ahb.scala 321:41] + buf_write_in <= _T_300 @[axi4_to_ahb.scala 321:20] + node _T_301 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 322:50] + node _T_302 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 322:78] + node _T_303 = or(_T_301, _T_302) @[axi4_to_ahb.scala 322:62] + node _T_304 = and(buf_state_en, _T_303) @[axi4_to_ahb.scala 322:33] + buf_wr_en <= _T_304 @[axi4_to_ahb.scala 322:17] buf_data_wr_en <= buf_wr_en @[axi4_to_ahb.scala 323:22] - node _T_303 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 324:63] - node _T_304 = neq(_T_303, UInt<1>("h00")) @[axi4_to_ahb.scala 324:70] - node _T_305 = and(ahb_hready_q, _T_304) @[axi4_to_ahb.scala 324:48] - node _T_306 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 324:104] - node _T_307 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 324:166] - node _T_308 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 324:184] - node _T_309 = add(_T_307, UInt<1>("h01")) @[axi4_to_ahb.scala 181:52] - node _T_310 = tail(_T_309, 1) @[axi4_to_ahb.scala 181:52] - node _T_311 = mux(UInt<1>("h01"), _T_310, _T_307) @[axi4_to_ahb.scala 181:24] - node _T_312 = bits(_T_308, 0, 0) @[axi4_to_ahb.scala 182:44] - node _T_313 = geq(UInt<1>("h00"), _T_311) @[axi4_to_ahb.scala 182:62] - node _T_314 = and(_T_312, _T_313) @[axi4_to_ahb.scala 182:48] - node _T_315 = bits(_T_308, 1, 1) @[axi4_to_ahb.scala 182:44] - node _T_316 = geq(UInt<1>("h01"), _T_311) @[axi4_to_ahb.scala 182:62] - node _T_317 = and(_T_315, _T_316) @[axi4_to_ahb.scala 182:48] - node _T_318 = bits(_T_308, 2, 2) @[axi4_to_ahb.scala 182:44] - node _T_319 = geq(UInt<2>("h02"), _T_311) @[axi4_to_ahb.scala 182:62] - node _T_320 = and(_T_318, _T_319) @[axi4_to_ahb.scala 182:48] - node _T_321 = bits(_T_308, 3, 3) @[axi4_to_ahb.scala 182:44] - node _T_322 = geq(UInt<2>("h03"), _T_311) @[axi4_to_ahb.scala 182:62] - node _T_323 = and(_T_321, _T_322) @[axi4_to_ahb.scala 182:48] - node _T_324 = bits(_T_308, 4, 4) @[axi4_to_ahb.scala 182:44] - node _T_325 = geq(UInt<3>("h04"), _T_311) @[axi4_to_ahb.scala 182:62] - node _T_326 = and(_T_324, _T_325) @[axi4_to_ahb.scala 182:48] - node _T_327 = bits(_T_308, 5, 5) @[axi4_to_ahb.scala 182:44] - node _T_328 = geq(UInt<3>("h05"), _T_311) @[axi4_to_ahb.scala 182:62] - node _T_329 = and(_T_327, _T_328) @[axi4_to_ahb.scala 182:48] - node _T_330 = bits(_T_308, 6, 6) @[axi4_to_ahb.scala 182:44] - node _T_331 = geq(UInt<3>("h06"), _T_311) @[axi4_to_ahb.scala 182:62] - node _T_332 = and(_T_330, _T_331) @[axi4_to_ahb.scala 182:48] - node _T_333 = bits(_T_308, 7, 7) @[axi4_to_ahb.scala 182:44] - node _T_334 = geq(UInt<3>("h07"), _T_311) @[axi4_to_ahb.scala 182:62] - node _T_335 = and(_T_333, _T_334) @[axi4_to_ahb.scala 182:48] - node _T_336 = mux(_T_335, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16] - node _T_337 = mux(_T_332, UInt<3>("h06"), _T_336) @[Mux.scala 98:16] - node _T_338 = mux(_T_329, UInt<3>("h05"), _T_337) @[Mux.scala 98:16] - node _T_339 = mux(_T_326, UInt<3>("h04"), _T_338) @[Mux.scala 98:16] - node _T_340 = mux(_T_323, UInt<2>("h03"), _T_339) @[Mux.scala 98:16] - node _T_341 = mux(_T_320, UInt<2>("h02"), _T_340) @[Mux.scala 98:16] - node _T_342 = mux(_T_317, UInt<1>("h01"), _T_341) @[Mux.scala 98:16] - node _T_343 = mux(_T_314, UInt<1>("h00"), _T_342) @[Mux.scala 98:16] - node _T_344 = dshr(buf_byteen, _T_343) @[axi4_to_ahb.scala 324:131] - node _T_345 = bits(_T_344, 0, 0) @[axi4_to_ahb.scala 324:131] - node _T_346 = eq(_T_345, UInt<1>("h00")) @[axi4_to_ahb.scala 324:202] - node _T_347 = or(_T_306, _T_346) @[axi4_to_ahb.scala 324:118] - node _T_348 = and(_T_305, _T_347) @[axi4_to_ahb.scala 324:82] - node _T_349 = or(ahb_hresp_q, _T_348) @[axi4_to_ahb.scala 324:32] - cmd_done <= _T_349 @[axi4_to_ahb.scala 324:16] - node _T_350 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 325:33] - node _T_351 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 325:64] - node _T_352 = and(_T_350, _T_351) @[axi4_to_ahb.scala 325:48] - bypass_en <= _T_352 @[axi4_to_ahb.scala 325:17] - node _T_353 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 326:44] - node _T_354 = eq(_T_353, UInt<1>("h00")) @[axi4_to_ahb.scala 326:33] - node _T_355 = or(_T_354, bypass_en) @[axi4_to_ahb.scala 326:57] - node _T_356 = bits(_T_355, 0, 0) @[Bitwise.scala 72:15] - node _T_357 = mux(_T_356, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_358 = and(_T_357, UInt<2>("h02")) @[axi4_to_ahb.scala 326:71] - io.ahb_htrans <= _T_358 @[axi4_to_ahb.scala 326:21] - node _T_359 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 327:55] - node _T_360 = and(buf_state_en, _T_359) @[axi4_to_ahb.scala 327:39] - slave_valid_pre <= _T_360 @[axi4_to_ahb.scala 327:23] - node _T_361 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 328:33] - node _T_362 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 328:63] - node _T_363 = neq(_T_362, UInt<1>("h00")) @[axi4_to_ahb.scala 328:70] - node _T_364 = and(_T_361, _T_363) @[axi4_to_ahb.scala 328:48] - trxn_done <= _T_364 @[axi4_to_ahb.scala 328:17] - node _T_365 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 329:40] - buf_cmd_byte_ptr_en <= _T_365 @[axi4_to_ahb.scala 329:27] - node _T_366 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 332:76] - node _T_367 = add(UInt<1>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 181:52] - node _T_368 = tail(_T_367, 1) @[axi4_to_ahb.scala 181:52] - node _T_369 = mux(UInt<1>("h00"), _T_368, UInt<1>("h00")) @[axi4_to_ahb.scala 181:24] - node _T_370 = bits(_T_366, 0, 0) @[axi4_to_ahb.scala 182:44] - node _T_371 = geq(UInt<1>("h00"), _T_369) @[axi4_to_ahb.scala 182:62] - node _T_372 = and(_T_370, _T_371) @[axi4_to_ahb.scala 182:48] - node _T_373 = bits(_T_366, 1, 1) @[axi4_to_ahb.scala 182:44] - node _T_374 = geq(UInt<1>("h01"), _T_369) @[axi4_to_ahb.scala 182:62] - node _T_375 = and(_T_373, _T_374) @[axi4_to_ahb.scala 182:48] - node _T_376 = bits(_T_366, 2, 2) @[axi4_to_ahb.scala 182:44] - node _T_377 = geq(UInt<2>("h02"), _T_369) @[axi4_to_ahb.scala 182:62] - node _T_378 = and(_T_376, _T_377) @[axi4_to_ahb.scala 182:48] - node _T_379 = bits(_T_366, 3, 3) @[axi4_to_ahb.scala 182:44] - node _T_380 = geq(UInt<2>("h03"), _T_369) @[axi4_to_ahb.scala 182:62] - node _T_381 = and(_T_379, _T_380) @[axi4_to_ahb.scala 182:48] - node _T_382 = bits(_T_366, 4, 4) @[axi4_to_ahb.scala 182:44] - node _T_383 = geq(UInt<3>("h04"), _T_369) @[axi4_to_ahb.scala 182:62] - node _T_384 = and(_T_382, _T_383) @[axi4_to_ahb.scala 182:48] - node _T_385 = bits(_T_366, 5, 5) @[axi4_to_ahb.scala 182:44] - node _T_386 = geq(UInt<3>("h05"), _T_369) @[axi4_to_ahb.scala 182:62] - node _T_387 = and(_T_385, _T_386) @[axi4_to_ahb.scala 182:48] - node _T_388 = bits(_T_366, 6, 6) @[axi4_to_ahb.scala 182:44] - node _T_389 = geq(UInt<3>("h06"), _T_369) @[axi4_to_ahb.scala 182:62] - node _T_390 = and(_T_388, _T_389) @[axi4_to_ahb.scala 182:48] - node _T_391 = bits(_T_366, 7, 7) @[axi4_to_ahb.scala 182:44] - node _T_392 = geq(UInt<3>("h07"), _T_369) @[axi4_to_ahb.scala 182:62] - node _T_393 = and(_T_391, _T_392) @[axi4_to_ahb.scala 182:48] - node _T_394 = mux(_T_393, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16] - node _T_395 = mux(_T_390, UInt<3>("h06"), _T_394) @[Mux.scala 98:16] - node _T_396 = mux(_T_387, UInt<3>("h05"), _T_395) @[Mux.scala 98:16] - node _T_397 = mux(_T_384, UInt<3>("h04"), _T_396) @[Mux.scala 98:16] - node _T_398 = mux(_T_381, UInt<2>("h03"), _T_397) @[Mux.scala 98:16] - node _T_399 = mux(_T_378, UInt<2>("h02"), _T_398) @[Mux.scala 98:16] - node _T_400 = mux(_T_375, UInt<1>("h01"), _T_399) @[Mux.scala 98:16] - node _T_401 = mux(_T_372, UInt<1>("h00"), _T_400) @[Mux.scala 98:16] - node _T_402 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 332:142] - node _T_403 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 332:160] - node _T_404 = add(_T_402, UInt<1>("h01")) @[axi4_to_ahb.scala 181:52] - node _T_405 = tail(_T_404, 1) @[axi4_to_ahb.scala 181:52] - node _T_406 = mux(UInt<1>("h01"), _T_405, _T_402) @[axi4_to_ahb.scala 181:24] - node _T_407 = bits(_T_403, 0, 0) @[axi4_to_ahb.scala 182:44] - node _T_408 = geq(UInt<1>("h00"), _T_406) @[axi4_to_ahb.scala 182:62] - node _T_409 = and(_T_407, _T_408) @[axi4_to_ahb.scala 182:48] - node _T_410 = bits(_T_403, 1, 1) @[axi4_to_ahb.scala 182:44] - node _T_411 = geq(UInt<1>("h01"), _T_406) @[axi4_to_ahb.scala 182:62] - node _T_412 = and(_T_410, _T_411) @[axi4_to_ahb.scala 182:48] - node _T_413 = bits(_T_403, 2, 2) @[axi4_to_ahb.scala 182:44] - node _T_414 = geq(UInt<2>("h02"), _T_406) @[axi4_to_ahb.scala 182:62] - node _T_415 = and(_T_413, _T_414) @[axi4_to_ahb.scala 182:48] - node _T_416 = bits(_T_403, 3, 3) @[axi4_to_ahb.scala 182:44] - node _T_417 = geq(UInt<2>("h03"), _T_406) @[axi4_to_ahb.scala 182:62] - node _T_418 = and(_T_416, _T_417) @[axi4_to_ahb.scala 182:48] - node _T_419 = bits(_T_403, 4, 4) @[axi4_to_ahb.scala 182:44] - node _T_420 = geq(UInt<3>("h04"), _T_406) @[axi4_to_ahb.scala 182:62] - node _T_421 = and(_T_419, _T_420) @[axi4_to_ahb.scala 182:48] - node _T_422 = bits(_T_403, 5, 5) @[axi4_to_ahb.scala 182:44] - node _T_423 = geq(UInt<3>("h05"), _T_406) @[axi4_to_ahb.scala 182:62] - node _T_424 = and(_T_422, _T_423) @[axi4_to_ahb.scala 182:48] - node _T_425 = bits(_T_403, 6, 6) @[axi4_to_ahb.scala 182:44] - node _T_426 = geq(UInt<3>("h06"), _T_406) @[axi4_to_ahb.scala 182:62] - node _T_427 = and(_T_425, _T_426) @[axi4_to_ahb.scala 182:48] - node _T_428 = bits(_T_403, 7, 7) @[axi4_to_ahb.scala 182:44] - node _T_429 = geq(UInt<3>("h07"), _T_406) @[axi4_to_ahb.scala 182:62] - node _T_430 = and(_T_428, _T_429) @[axi4_to_ahb.scala 182:48] - node _T_431 = mux(_T_430, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16] - node _T_432 = mux(_T_427, UInt<3>("h06"), _T_431) @[Mux.scala 98:16] - node _T_433 = mux(_T_424, UInt<3>("h05"), _T_432) @[Mux.scala 98:16] - node _T_434 = mux(_T_421, UInt<3>("h04"), _T_433) @[Mux.scala 98:16] - node _T_435 = mux(_T_418, UInt<2>("h03"), _T_434) @[Mux.scala 98:16] - node _T_436 = mux(_T_415, UInt<2>("h02"), _T_435) @[Mux.scala 98:16] - node _T_437 = mux(_T_412, UInt<1>("h01"), _T_436) @[Mux.scala 98:16] - node _T_438 = mux(_T_409, UInt<1>("h00"), _T_437) @[Mux.scala 98:16] - node _T_439 = mux(trxn_done, _T_438, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 332:97] - node _T_440 = mux(bypass_en, _T_401, _T_439) @[axi4_to_ahb.scala 332:30] - buf_cmd_byte_ptr <= _T_440 @[axi4_to_ahb.scala 332:24] + node _T_305 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 324:63] + node _T_306 = neq(_T_305, UInt<1>("h00")) @[axi4_to_ahb.scala 324:70] + node _T_307 = and(ahb_hready_q, _T_306) @[axi4_to_ahb.scala 324:48] + node _T_308 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 324:104] + node _T_309 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 324:166] + node _T_310 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 324:184] + node _T_311 = add(_T_309, UInt<1>("h01")) @[axi4_to_ahb.scala 181:52] + node _T_312 = tail(_T_311, 1) @[axi4_to_ahb.scala 181:52] + node _T_313 = mux(UInt<1>("h01"), _T_312, _T_309) @[axi4_to_ahb.scala 181:24] + node _T_314 = bits(_T_310, 0, 0) @[axi4_to_ahb.scala 182:44] + node _T_315 = geq(UInt<1>("h00"), _T_313) @[axi4_to_ahb.scala 182:62] + node _T_316 = and(_T_314, _T_315) @[axi4_to_ahb.scala 182:48] + node _T_317 = bits(_T_310, 1, 1) @[axi4_to_ahb.scala 182:44] + node _T_318 = geq(UInt<1>("h01"), _T_313) @[axi4_to_ahb.scala 182:62] + node _T_319 = and(_T_317, _T_318) @[axi4_to_ahb.scala 182:48] + node _T_320 = bits(_T_310, 2, 2) @[axi4_to_ahb.scala 182:44] + node _T_321 = geq(UInt<2>("h02"), _T_313) @[axi4_to_ahb.scala 182:62] + node _T_322 = and(_T_320, _T_321) @[axi4_to_ahb.scala 182:48] + node _T_323 = bits(_T_310, 3, 3) @[axi4_to_ahb.scala 182:44] + node _T_324 = geq(UInt<2>("h03"), _T_313) @[axi4_to_ahb.scala 182:62] + node _T_325 = and(_T_323, _T_324) @[axi4_to_ahb.scala 182:48] + node _T_326 = bits(_T_310, 4, 4) @[axi4_to_ahb.scala 182:44] + node _T_327 = geq(UInt<3>("h04"), _T_313) @[axi4_to_ahb.scala 182:62] + node _T_328 = and(_T_326, _T_327) @[axi4_to_ahb.scala 182:48] + node _T_329 = bits(_T_310, 5, 5) @[axi4_to_ahb.scala 182:44] + node _T_330 = geq(UInt<3>("h05"), _T_313) @[axi4_to_ahb.scala 182:62] + node _T_331 = and(_T_329, _T_330) @[axi4_to_ahb.scala 182:48] + node _T_332 = bits(_T_310, 6, 6) @[axi4_to_ahb.scala 182:44] + node _T_333 = geq(UInt<3>("h06"), _T_313) @[axi4_to_ahb.scala 182:62] + node _T_334 = and(_T_332, _T_333) @[axi4_to_ahb.scala 182:48] + node _T_335 = bits(_T_310, 7, 7) @[axi4_to_ahb.scala 182:44] + node _T_336 = geq(UInt<3>("h07"), _T_313) @[axi4_to_ahb.scala 182:62] + node _T_337 = and(_T_335, _T_336) @[axi4_to_ahb.scala 182:48] + node _T_338 = mux(_T_337, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16] + node _T_339 = mux(_T_334, UInt<3>("h06"), _T_338) @[Mux.scala 98:16] + node _T_340 = mux(_T_331, UInt<3>("h05"), _T_339) @[Mux.scala 98:16] + node _T_341 = mux(_T_328, UInt<3>("h04"), _T_340) @[Mux.scala 98:16] + node _T_342 = mux(_T_325, UInt<2>("h03"), _T_341) @[Mux.scala 98:16] + node _T_343 = mux(_T_322, UInt<2>("h02"), _T_342) @[Mux.scala 98:16] + node _T_344 = mux(_T_319, UInt<1>("h01"), _T_343) @[Mux.scala 98:16] + node _T_345 = mux(_T_316, UInt<1>("h00"), _T_344) @[Mux.scala 98:16] + node _T_346 = dshr(buf_byteen, _T_345) @[axi4_to_ahb.scala 324:131] + node _T_347 = bits(_T_346, 0, 0) @[axi4_to_ahb.scala 324:131] + node _T_348 = eq(_T_347, UInt<1>("h00")) @[axi4_to_ahb.scala 324:202] + node _T_349 = or(_T_308, _T_348) @[axi4_to_ahb.scala 324:118] + node _T_350 = and(_T_307, _T_349) @[axi4_to_ahb.scala 324:82] + node _T_351 = or(ahb_hresp_q, _T_350) @[axi4_to_ahb.scala 324:32] + cmd_done <= _T_351 @[axi4_to_ahb.scala 324:16] + node _T_352 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 325:33] + node _T_353 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 325:64] + node _T_354 = and(_T_352, _T_353) @[axi4_to_ahb.scala 325:48] + bypass_en <= _T_354 @[axi4_to_ahb.scala 325:17] + node _T_355 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 326:44] + node _T_356 = eq(_T_355, UInt<1>("h00")) @[axi4_to_ahb.scala 326:33] + node _T_357 = or(_T_356, bypass_en) @[axi4_to_ahb.scala 326:57] + node _T_358 = bits(_T_357, 0, 0) @[Bitwise.scala 72:15] + node _T_359 = mux(_T_358, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_360 = and(_T_359, UInt<2>("h02")) @[axi4_to_ahb.scala 326:71] + io.ahb_htrans <= _T_360 @[axi4_to_ahb.scala 326:21] + node _T_361 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 327:55] + node _T_362 = and(buf_state_en, _T_361) @[axi4_to_ahb.scala 327:39] + slave_valid_pre <= _T_362 @[axi4_to_ahb.scala 327:23] + node _T_363 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 328:33] + node _T_364 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 328:63] + node _T_365 = neq(_T_364, UInt<1>("h00")) @[axi4_to_ahb.scala 328:70] + node _T_366 = and(_T_363, _T_365) @[axi4_to_ahb.scala 328:48] + trxn_done <= _T_366 @[axi4_to_ahb.scala 328:17] + node _T_367 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 329:40] + buf_cmd_byte_ptr_en <= _T_367 @[axi4_to_ahb.scala 329:27] + node _T_368 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 332:76] + node _T_369 = add(UInt<1>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 181:52] + node _T_370 = tail(_T_369, 1) @[axi4_to_ahb.scala 181:52] + node _T_371 = mux(UInt<1>("h00"), _T_370, UInt<1>("h00")) @[axi4_to_ahb.scala 181:24] + node _T_372 = bits(_T_368, 0, 0) @[axi4_to_ahb.scala 182:44] + node _T_373 = geq(UInt<1>("h00"), _T_371) @[axi4_to_ahb.scala 182:62] + node _T_374 = and(_T_372, _T_373) @[axi4_to_ahb.scala 182:48] + node _T_375 = bits(_T_368, 1, 1) @[axi4_to_ahb.scala 182:44] + node _T_376 = geq(UInt<1>("h01"), _T_371) @[axi4_to_ahb.scala 182:62] + node _T_377 = and(_T_375, _T_376) @[axi4_to_ahb.scala 182:48] + node _T_378 = bits(_T_368, 2, 2) @[axi4_to_ahb.scala 182:44] + node _T_379 = geq(UInt<2>("h02"), _T_371) @[axi4_to_ahb.scala 182:62] + node _T_380 = and(_T_378, _T_379) @[axi4_to_ahb.scala 182:48] + node _T_381 = bits(_T_368, 3, 3) @[axi4_to_ahb.scala 182:44] + node _T_382 = geq(UInt<2>("h03"), _T_371) @[axi4_to_ahb.scala 182:62] + node _T_383 = and(_T_381, _T_382) @[axi4_to_ahb.scala 182:48] + node _T_384 = bits(_T_368, 4, 4) @[axi4_to_ahb.scala 182:44] + node _T_385 = geq(UInt<3>("h04"), _T_371) @[axi4_to_ahb.scala 182:62] + node _T_386 = and(_T_384, _T_385) @[axi4_to_ahb.scala 182:48] + node _T_387 = bits(_T_368, 5, 5) @[axi4_to_ahb.scala 182:44] + node _T_388 = geq(UInt<3>("h05"), _T_371) @[axi4_to_ahb.scala 182:62] + node _T_389 = and(_T_387, _T_388) @[axi4_to_ahb.scala 182:48] + node _T_390 = bits(_T_368, 6, 6) @[axi4_to_ahb.scala 182:44] + node _T_391 = geq(UInt<3>("h06"), _T_371) @[axi4_to_ahb.scala 182:62] + node _T_392 = and(_T_390, _T_391) @[axi4_to_ahb.scala 182:48] + node _T_393 = bits(_T_368, 7, 7) @[axi4_to_ahb.scala 182:44] + node _T_394 = geq(UInt<3>("h07"), _T_371) @[axi4_to_ahb.scala 182:62] + node _T_395 = and(_T_393, _T_394) @[axi4_to_ahb.scala 182:48] + node _T_396 = mux(_T_395, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16] + node _T_397 = mux(_T_392, UInt<3>("h06"), _T_396) @[Mux.scala 98:16] + node _T_398 = mux(_T_389, UInt<3>("h05"), _T_397) @[Mux.scala 98:16] + node _T_399 = mux(_T_386, UInt<3>("h04"), _T_398) @[Mux.scala 98:16] + node _T_400 = mux(_T_383, UInt<2>("h03"), _T_399) @[Mux.scala 98:16] + node _T_401 = mux(_T_380, UInt<2>("h02"), _T_400) @[Mux.scala 98:16] + node _T_402 = mux(_T_377, UInt<1>("h01"), _T_401) @[Mux.scala 98:16] + node _T_403 = mux(_T_374, UInt<1>("h00"), _T_402) @[Mux.scala 98:16] + node _T_404 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 332:142] + node _T_405 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 332:160] + node _T_406 = add(_T_404, UInt<1>("h01")) @[axi4_to_ahb.scala 181:52] + node _T_407 = tail(_T_406, 1) @[axi4_to_ahb.scala 181:52] + node _T_408 = mux(UInt<1>("h01"), _T_407, _T_404) @[axi4_to_ahb.scala 181:24] + node _T_409 = bits(_T_405, 0, 0) @[axi4_to_ahb.scala 182:44] + node _T_410 = geq(UInt<1>("h00"), _T_408) @[axi4_to_ahb.scala 182:62] + node _T_411 = and(_T_409, _T_410) @[axi4_to_ahb.scala 182:48] + node _T_412 = bits(_T_405, 1, 1) @[axi4_to_ahb.scala 182:44] + node _T_413 = geq(UInt<1>("h01"), _T_408) @[axi4_to_ahb.scala 182:62] + node _T_414 = and(_T_412, _T_413) @[axi4_to_ahb.scala 182:48] + node _T_415 = bits(_T_405, 2, 2) @[axi4_to_ahb.scala 182:44] + node _T_416 = geq(UInt<2>("h02"), _T_408) @[axi4_to_ahb.scala 182:62] + node _T_417 = and(_T_415, _T_416) @[axi4_to_ahb.scala 182:48] + node _T_418 = bits(_T_405, 3, 3) @[axi4_to_ahb.scala 182:44] + node _T_419 = geq(UInt<2>("h03"), _T_408) @[axi4_to_ahb.scala 182:62] + node _T_420 = and(_T_418, _T_419) @[axi4_to_ahb.scala 182:48] + node _T_421 = bits(_T_405, 4, 4) @[axi4_to_ahb.scala 182:44] + node _T_422 = geq(UInt<3>("h04"), _T_408) @[axi4_to_ahb.scala 182:62] + node _T_423 = and(_T_421, _T_422) @[axi4_to_ahb.scala 182:48] + node _T_424 = bits(_T_405, 5, 5) @[axi4_to_ahb.scala 182:44] + node _T_425 = geq(UInt<3>("h05"), _T_408) @[axi4_to_ahb.scala 182:62] + node _T_426 = and(_T_424, _T_425) @[axi4_to_ahb.scala 182:48] + node _T_427 = bits(_T_405, 6, 6) @[axi4_to_ahb.scala 182:44] + node _T_428 = geq(UInt<3>("h06"), _T_408) @[axi4_to_ahb.scala 182:62] + node _T_429 = and(_T_427, _T_428) @[axi4_to_ahb.scala 182:48] + node _T_430 = bits(_T_405, 7, 7) @[axi4_to_ahb.scala 182:44] + node _T_431 = geq(UInt<3>("h07"), _T_408) @[axi4_to_ahb.scala 182:62] + node _T_432 = and(_T_430, _T_431) @[axi4_to_ahb.scala 182:48] + node _T_433 = mux(_T_432, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16] + node _T_434 = mux(_T_429, UInt<3>("h06"), _T_433) @[Mux.scala 98:16] + node _T_435 = mux(_T_426, UInt<3>("h05"), _T_434) @[Mux.scala 98:16] + node _T_436 = mux(_T_423, UInt<3>("h04"), _T_435) @[Mux.scala 98:16] + node _T_437 = mux(_T_420, UInt<2>("h03"), _T_436) @[Mux.scala 98:16] + node _T_438 = mux(_T_417, UInt<2>("h02"), _T_437) @[Mux.scala 98:16] + node _T_439 = mux(_T_414, UInt<1>("h01"), _T_438) @[Mux.scala 98:16] + node _T_440 = mux(_T_411, UInt<1>("h00"), _T_439) @[Mux.scala 98:16] + node _T_441 = mux(trxn_done, _T_440, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 332:97] + node _T_442 = mux(bypass_en, _T_403, _T_441) @[axi4_to_ahb.scala 332:30] + buf_cmd_byte_ptr <= _T_442 @[axi4_to_ahb.scala 332:24] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_441 = eq(UInt<3>("h05"), buf_state) @[Conditional.scala 37:30] - when _T_441 : @[Conditional.scala 39:67] + node _T_443 = eq(UInt<3>("h05"), buf_state) @[Conditional.scala 37:30] + when _T_443 : @[Conditional.scala 39:67] buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 335:20] buf_state_en <= slave_ready @[axi4_to_ahb.scala 336:20] slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 337:23] slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 338:23] skip @[Conditional.scala 39:67] - cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 341:16] - node _T_442 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 342:33] - node _T_443 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 342:73] - node _T_444 = eq(_T_443, UInt<1>("h01")) @[axi4_to_ahb.scala 342:80] - node _T_445 = and(buf_aligned_in, _T_444) @[axi4_to_ahb.scala 342:60] - node _T_446 = bits(_T_445, 0, 0) @[axi4_to_ahb.scala 342:100] - node _T_447 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 342:132] - node _T_448 = bits(_T_447, 7, 0) @[axi4_to_ahb.scala 173:50] - node _T_449 = eq(_T_448, UInt<8>("h0ff")) @[axi4_to_ahb.scala 173:57] - node _T_450 = bits(_T_447, 7, 0) @[axi4_to_ahb.scala 173:81] - node _T_451 = eq(_T_450, UInt<8>("h0f")) @[axi4_to_ahb.scala 173:88] - node _T_452 = or(_T_449, _T_451) @[axi4_to_ahb.scala 173:70] - node _T_453 = bits(_T_447, 7, 0) @[axi4_to_ahb.scala 173:117] - node _T_454 = eq(_T_453, UInt<8>("h03")) @[axi4_to_ahb.scala 173:124] - node _T_455 = or(_T_452, _T_454) @[axi4_to_ahb.scala 173:106] - node _T_456 = bits(_T_455, 0, 0) @[Bitwise.scala 72:15] - node _T_457 = mux(_T_456, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_458 = and(UInt<3>("h00"), _T_457) @[axi4_to_ahb.scala 173:29] - node _T_459 = bits(_T_447, 7, 0) @[axi4_to_ahb.scala 174:35] - node _T_460 = eq(_T_459, UInt<8>("h0c")) @[axi4_to_ahb.scala 174:42] - node _T_461 = bits(_T_460, 0, 0) @[Bitwise.scala 72:15] - node _T_462 = mux(_T_461, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_463 = and(UInt<2>("h02"), _T_462) @[axi4_to_ahb.scala 174:15] - node _T_464 = or(_T_458, _T_463) @[axi4_to_ahb.scala 173:146] - node _T_465 = bits(_T_447, 7, 0) @[axi4_to_ahb.scala 175:36] - node _T_466 = eq(_T_465, UInt<8>("h0f0")) @[axi4_to_ahb.scala 175:43] - node _T_467 = bits(_T_447, 7, 0) @[axi4_to_ahb.scala 175:67] - node _T_468 = eq(_T_467, UInt<8>("h03")) @[axi4_to_ahb.scala 175:74] - node _T_469 = or(_T_466, _T_468) @[axi4_to_ahb.scala 175:56] - node _T_470 = bits(_T_469, 0, 0) @[Bitwise.scala 72:15] - node _T_471 = mux(_T_470, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_472 = and(UInt<3>("h04"), _T_471) @[axi4_to_ahb.scala 175:15] - node _T_473 = or(_T_464, _T_472) @[axi4_to_ahb.scala 174:63] - node _T_474 = bits(_T_447, 7, 0) @[axi4_to_ahb.scala 176:37] - node _T_475 = eq(_T_474, UInt<8>("h0c0")) @[axi4_to_ahb.scala 176:44] - node _T_476 = bits(_T_475, 0, 0) @[Bitwise.scala 72:15] - node _T_477 = mux(_T_476, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_478 = and(UInt<3>("h06"), _T_477) @[axi4_to_ahb.scala 176:17] - node _T_479 = or(_T_473, _T_478) @[axi4_to_ahb.scala 175:96] - node _T_480 = bits(_T_447, 7, 0) @[axi4_to_ahb.scala 177:37] - node _T_481 = eq(_T_480, UInt<8>("h0c0")) @[axi4_to_ahb.scala 177:44] - node _T_482 = bits(_T_481, 0, 0) @[Bitwise.scala 72:15] - node _T_483 = mux(_T_482, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_484 = and(UInt<3>("h06"), _T_483) @[axi4_to_ahb.scala 177:17] - node _T_485 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 342:152] - node _T_486 = mux(_T_446, _T_479, _T_485) @[axi4_to_ahb.scala 342:43] - node _T_487 = cat(_T_442, _T_486) @[Cat.scala 29:58] - buf_addr_in <= _T_487 @[axi4_to_ahb.scala 342:15] - node _T_488 = bits(master_tag, 0, 0) @[axi4_to_ahb.scala 343:27] - buf_tag_in <= _T_488 @[axi4_to_ahb.scala 343:14] - node _T_489 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 344:32] - buf_byteen_in <= _T_489 @[axi4_to_ahb.scala 344:17] - node _T_490 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 345:33] - node _T_491 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 345:59] - node _T_492 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 345:80] - node _T_493 = mux(_T_490, _T_491, _T_492) @[axi4_to_ahb.scala 345:21] - buf_data_in <= _T_493 @[axi4_to_ahb.scala 345:15] - node _T_494 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 346:52] - node _T_495 = eq(_T_494, UInt<2>("h03")) @[axi4_to_ahb.scala 346:58] - node _T_496 = and(buf_aligned_in, _T_495) @[axi4_to_ahb.scala 346:38] - node _T_497 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 346:84] - node _T_498 = eq(_T_497, UInt<1>("h01")) @[axi4_to_ahb.scala 346:91] - node _T_499 = and(_T_496, _T_498) @[axi4_to_ahb.scala 346:71] - node _T_500 = bits(_T_499, 0, 0) @[axi4_to_ahb.scala 346:111] - node _T_501 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 346:142] - node _T_502 = bits(_T_501, 7, 0) @[axi4_to_ahb.scala 166:42] - node _T_503 = eq(_T_502, UInt<8>("h0ff")) @[axi4_to_ahb.scala 166:49] - node _T_504 = bits(_T_503, 0, 0) @[Bitwise.scala 72:15] - node _T_505 = mux(_T_504, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_506 = and(UInt<2>("h03"), _T_505) @[axi4_to_ahb.scala 166:25] - node _T_507 = bits(_T_501, 7, 0) @[axi4_to_ahb.scala 167:35] - node _T_508 = eq(_T_507, UInt<8>("h0f0")) @[axi4_to_ahb.scala 167:42] - node _T_509 = bits(_T_501, 7, 0) @[axi4_to_ahb.scala 167:64] - node _T_510 = eq(_T_509, UInt<8>("h0f")) @[axi4_to_ahb.scala 167:71] - node _T_511 = or(_T_508, _T_510) @[axi4_to_ahb.scala 167:55] - node _T_512 = bits(_T_511, 0, 0) @[Bitwise.scala 72:15] - node _T_513 = mux(_T_512, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_514 = and(UInt<2>("h02"), _T_513) @[axi4_to_ahb.scala 167:16] - node _T_515 = or(_T_506, _T_514) @[axi4_to_ahb.scala 166:64] - node _T_516 = bits(_T_501, 7, 0) @[axi4_to_ahb.scala 168:40] - node _T_517 = eq(_T_516, UInt<8>("h0c0")) @[axi4_to_ahb.scala 168:47] - node _T_518 = bits(_T_501, 7, 0) @[axi4_to_ahb.scala 168:69] - node _T_519 = eq(_T_518, UInt<6>("h030")) @[axi4_to_ahb.scala 168:76] - node _T_520 = or(_T_517, _T_519) @[axi4_to_ahb.scala 168:60] - node _T_521 = bits(_T_501, 7, 0) @[axi4_to_ahb.scala 168:98] - node _T_522 = eq(_T_521, UInt<8>("h0c")) @[axi4_to_ahb.scala 168:105] - node _T_523 = or(_T_520, _T_522) @[axi4_to_ahb.scala 168:89] - node _T_524 = bits(_T_501, 7, 0) @[axi4_to_ahb.scala 168:132] - node _T_525 = eq(_T_524, UInt<8>("h03")) @[axi4_to_ahb.scala 168:139] - node _T_526 = or(_T_523, _T_525) @[axi4_to_ahb.scala 168:123] - node _T_527 = bits(_T_526, 0, 0) @[Bitwise.scala 72:15] - node _T_528 = mux(_T_527, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_529 = and(UInt<2>("h01"), _T_528) @[axi4_to_ahb.scala 168:21] - node _T_530 = or(_T_515, _T_529) @[axi4_to_ahb.scala 167:93] - node _T_531 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 346:161] - node _T_532 = mux(_T_500, _T_530, _T_531) @[axi4_to_ahb.scala 346:21] - buf_size_in <= _T_532 @[axi4_to_ahb.scala 346:15] - node _T_533 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 347:32] - node _T_534 = eq(_T_533, UInt<1>("h00")) @[axi4_to_ahb.scala 347:39] - node _T_535 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 348:17] - node _T_536 = eq(_T_535, UInt<1>("h00")) @[axi4_to_ahb.scala 348:24] - node _T_537 = or(_T_534, _T_536) @[axi4_to_ahb.scala 347:48] - node _T_538 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 348:47] - node _T_539 = eq(_T_538, UInt<2>("h01")) @[axi4_to_ahb.scala 348:54] - node _T_540 = or(_T_537, _T_539) @[axi4_to_ahb.scala 348:33] - node _T_541 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 348:86] - node _T_542 = eq(_T_541, UInt<2>("h02")) @[axi4_to_ahb.scala 348:93] - node _T_543 = or(_T_540, _T_542) @[axi4_to_ahb.scala 348:72] - node _T_544 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 349:18] - node _T_545 = eq(_T_544, UInt<2>("h03")) @[axi4_to_ahb.scala 349:25] - node _T_546 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 349:55] - node _T_547 = eq(_T_546, UInt<2>("h03")) @[axi4_to_ahb.scala 349:62] - node _T_548 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 349:90] - node _T_549 = eq(_T_548, UInt<4>("h0c")) @[axi4_to_ahb.scala 349:97] - node _T_550 = or(_T_547, _T_549) @[axi4_to_ahb.scala 349:74] - node _T_551 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 349:125] - node _T_552 = eq(_T_551, UInt<6>("h030")) @[axi4_to_ahb.scala 349:132] - node _T_553 = or(_T_550, _T_552) @[axi4_to_ahb.scala 349:109] - node _T_554 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 349:161] - node _T_555 = eq(_T_554, UInt<8>("h0c0")) @[axi4_to_ahb.scala 349:168] - node _T_556 = or(_T_553, _T_555) @[axi4_to_ahb.scala 349:145] - node _T_557 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 350:21] - node _T_558 = eq(_T_557, UInt<4>("h0f")) @[axi4_to_ahb.scala 350:28] - node _T_559 = or(_T_556, _T_558) @[axi4_to_ahb.scala 349:181] - node _T_560 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 350:56] - node _T_561 = eq(_T_560, UInt<8>("h0f0")) @[axi4_to_ahb.scala 350:63] - node _T_562 = or(_T_559, _T_561) @[axi4_to_ahb.scala 350:40] - node _T_563 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 350:92] - node _T_564 = eq(_T_563, UInt<8>("h0ff")) @[axi4_to_ahb.scala 350:99] - node _T_565 = or(_T_562, _T_564) @[axi4_to_ahb.scala 350:76] - node _T_566 = and(_T_545, _T_565) @[axi4_to_ahb.scala 349:38] - node _T_567 = or(_T_543, _T_566) @[axi4_to_ahb.scala 348:106] - buf_aligned_in <= _T_567 @[axi4_to_ahb.scala 347:18] - node _T_568 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 352:39] - node _T_569 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 352:58] - node _T_570 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 352:83] - node _T_571 = cat(_T_569, _T_570) @[Cat.scala 29:58] - node _T_572 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 352:104] - node _T_573 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 352:129] - node _T_574 = cat(_T_572, _T_573) @[Cat.scala 29:58] - node _T_575 = mux(_T_568, _T_571, _T_574) @[axi4_to_ahb.scala 352:22] - io.ahb_haddr <= _T_575 @[axi4_to_ahb.scala 352:16] - node _T_576 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 353:39] - node _T_577 = bits(buf_aligned_in, 0, 0) @[Bitwise.scala 72:15] - node _T_578 = mux(_T_577, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_579 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 353:90] - node _T_580 = and(_T_578, _T_579) @[axi4_to_ahb.scala 353:77] - node _T_581 = cat(UInt<1>("h00"), _T_580) @[Cat.scala 29:58] - node _T_582 = bits(buf_aligned, 0, 0) @[Bitwise.scala 72:15] - node _T_583 = mux(_T_582, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_584 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 353:144] - node _T_585 = and(_T_583, _T_584) @[axi4_to_ahb.scala 353:134] - node _T_586 = cat(UInt<1>("h00"), _T_585) @[Cat.scala 29:58] - node _T_587 = mux(_T_576, _T_581, _T_586) @[axi4_to_ahb.scala 353:22] - io.ahb_hsize <= _T_587 @[axi4_to_ahb.scala 353:16] - io.ahb_hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 355:17] - io.ahb_hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 356:20] - node _T_588 = bits(io.axi_arprot, 2, 2) @[axi4_to_ahb.scala 357:47] - node _T_589 = not(_T_588) @[axi4_to_ahb.scala 357:33] - node _T_590 = cat(UInt<1>("h01"), _T_589) @[Cat.scala 29:58] - io.ahb_hprot <= _T_590 @[axi4_to_ahb.scala 357:16] - node _T_591 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 358:40] - node _T_592 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 358:55] - node _T_593 = eq(_T_592, UInt<1>("h01")) @[axi4_to_ahb.scala 358:62] - node _T_594 = mux(_T_591, _T_593, buf_write) @[axi4_to_ahb.scala 358:23] - io.ahb_hwrite <= _T_594 @[axi4_to_ahb.scala 358:17] - node _T_595 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 359:28] - io.ahb_hwdata <= _T_595 @[axi4_to_ahb.scala 359:17] - slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 361:15] - node _T_596 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 362:43] - node _T_597 = mux(_T_596, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 362:23] - node _T_598 = bits(slvbuf_error, 0, 0) @[Bitwise.scala 72:15] - node _T_599 = mux(_T_598, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_600 = and(_T_599, UInt<2>("h02")) @[axi4_to_ahb.scala 362:88] - node _T_601 = cat(_T_597, _T_600) @[Cat.scala 29:58] - slave_opc <= _T_601 @[axi4_to_ahb.scala 362:13] - node _T_602 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 363:41] - node _T_603 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 363:66] - node _T_604 = cat(_T_603, _T_603) @[Cat.scala 29:58] - node _T_605 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 363:91] - node _T_606 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 363:110] - node _T_607 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 363:131] - node _T_608 = mux(_T_605, _T_606, _T_607) @[axi4_to_ahb.scala 363:79] - node _T_609 = mux(_T_602, _T_604, _T_608) @[axi4_to_ahb.scala 363:21] - slave_rdata <= _T_609 @[axi4_to_ahb.scala 363:15] - node _T_610 = bits(slvbuf_tag, 0, 0) @[axi4_to_ahb.scala 364:26] - slave_tag <= _T_610 @[axi4_to_ahb.scala 364:13] - node _T_611 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 366:33] - node _T_612 = neq(_T_611, UInt<1>("h00")) @[axi4_to_ahb.scala 366:40] - node _T_613 = and(_T_612, io.ahb_hready) @[axi4_to_ahb.scala 366:52] - node _T_614 = and(_T_613, io.ahb_hwrite) @[axi4_to_ahb.scala 366:68] - last_addr_en <= _T_614 @[axi4_to_ahb.scala 366:16] - node _T_615 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 368:30] - node _T_616 = and(_T_615, master_ready) @[axi4_to_ahb.scala 368:47] - wrbuf_en <= _T_616 @[axi4_to_ahb.scala 368:12] - node _T_617 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 369:34] - node _T_618 = and(_T_617, master_ready) @[axi4_to_ahb.scala 369:50] - wrbuf_data_en <= _T_618 @[axi4_to_ahb.scala 369:17] - node _T_619 = and(master_valid, master_ready) @[axi4_to_ahb.scala 370:34] - node _T_620 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 370:62] - node _T_621 = eq(_T_620, UInt<1>("h01")) @[axi4_to_ahb.scala 370:69] - node _T_622 = and(_T_619, _T_621) @[axi4_to_ahb.scala 370:49] - wrbuf_cmd_sent <= _T_622 @[axi4_to_ahb.scala 370:18] - node _T_623 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 371:33] - node _T_624 = and(wrbuf_cmd_sent, _T_623) @[axi4_to_ahb.scala 371:31] - wrbuf_rst <= _T_624 @[axi4_to_ahb.scala 371:13] - node _T_625 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 373:35] - node _T_626 = and(wrbuf_vld, _T_625) @[axi4_to_ahb.scala 373:33] - node _T_627 = eq(_T_626, UInt<1>("h00")) @[axi4_to_ahb.scala 373:21] - node _T_628 = and(_T_627, master_ready) @[axi4_to_ahb.scala 373:52] - io.axi_awready <= _T_628 @[axi4_to_ahb.scala 373:18] - node _T_629 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 374:39] - node _T_630 = and(wrbuf_data_vld, _T_629) @[axi4_to_ahb.scala 374:37] - node _T_631 = eq(_T_630, UInt<1>("h00")) @[axi4_to_ahb.scala 374:20] - node _T_632 = and(_T_631, master_ready) @[axi4_to_ahb.scala 374:56] - io.axi_wready <= _T_632 @[axi4_to_ahb.scala 374:17] - node _T_633 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 375:33] - node _T_634 = eq(_T_633, UInt<1>("h00")) @[axi4_to_ahb.scala 375:21] - node _T_635 = and(_T_634, master_ready) @[axi4_to_ahb.scala 375:51] - io.axi_arready <= _T_635 @[axi4_to_ahb.scala 375:18] - io.axi_rlast <= UInt<1>("h01") @[axi4_to_ahb.scala 376:16] - node _T_636 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 379:68] - node _T_637 = mux(_T_636, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 379:52] - node _T_638 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 379:88] - node _T_639 = and(_T_637, _T_638) @[axi4_to_ahb.scala 379:86] - reg _T_640 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 379:48] - _T_640 <= _T_639 @[axi4_to_ahb.scala 379:48] - wrbuf_vld <= _T_640 @[axi4_to_ahb.scala 379:18] - node _T_641 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 380:73] - node _T_642 = mux(_T_641, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 380:52] - node _T_643 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 380:99] - node _T_644 = and(_T_642, _T_643) @[axi4_to_ahb.scala 380:97] - reg _T_645 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 380:48] - _T_645 <= _T_644 @[axi4_to_ahb.scala 380:48] - wrbuf_data_vld <= _T_645 @[axi4_to_ahb.scala 380:18] - node _T_646 = bits(io.axi_awid, 0, 0) @[axi4_to_ahb.scala 382:57] - node _T_647 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 382:91] - reg _T_648 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_647 : @[Reg.scala 28:19] - _T_648 <= _T_646 @[Reg.scala 28:23] + cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 342:16] + node _T_444 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 343:33] + node _T_445 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 343:73] + node _T_446 = eq(_T_445, UInt<1>("h01")) @[axi4_to_ahb.scala 343:80] + node _T_447 = and(buf_aligned_in, _T_446) @[axi4_to_ahb.scala 343:60] + node _T_448 = bits(_T_447, 0, 0) @[axi4_to_ahb.scala 343:100] + node _T_449 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 343:132] + node _T_450 = bits(_T_449, 7, 0) @[axi4_to_ahb.scala 173:50] + node _T_451 = eq(_T_450, UInt<8>("h0ff")) @[axi4_to_ahb.scala 173:57] + node _T_452 = bits(_T_449, 7, 0) @[axi4_to_ahb.scala 173:81] + node _T_453 = eq(_T_452, UInt<8>("h0f")) @[axi4_to_ahb.scala 173:88] + node _T_454 = or(_T_451, _T_453) @[axi4_to_ahb.scala 173:70] + node _T_455 = bits(_T_449, 7, 0) @[axi4_to_ahb.scala 173:117] + node _T_456 = eq(_T_455, UInt<8>("h03")) @[axi4_to_ahb.scala 173:124] + node _T_457 = or(_T_454, _T_456) @[axi4_to_ahb.scala 173:106] + node _T_458 = bits(_T_457, 0, 0) @[Bitwise.scala 72:15] + node _T_459 = mux(_T_458, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_460 = and(UInt<3>("h00"), _T_459) @[axi4_to_ahb.scala 173:29] + node _T_461 = bits(_T_449, 7, 0) @[axi4_to_ahb.scala 174:35] + node _T_462 = eq(_T_461, UInt<8>("h0c")) @[axi4_to_ahb.scala 174:42] + node _T_463 = bits(_T_462, 0, 0) @[Bitwise.scala 72:15] + node _T_464 = mux(_T_463, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_465 = and(UInt<2>("h02"), _T_464) @[axi4_to_ahb.scala 174:15] + node _T_466 = or(_T_460, _T_465) @[axi4_to_ahb.scala 173:146] + node _T_467 = bits(_T_449, 7, 0) @[axi4_to_ahb.scala 175:36] + node _T_468 = eq(_T_467, UInt<8>("h0f0")) @[axi4_to_ahb.scala 175:43] + node _T_469 = bits(_T_449, 7, 0) @[axi4_to_ahb.scala 175:67] + node _T_470 = eq(_T_469, UInt<8>("h03")) @[axi4_to_ahb.scala 175:74] + node _T_471 = or(_T_468, _T_470) @[axi4_to_ahb.scala 175:56] + node _T_472 = bits(_T_471, 0, 0) @[Bitwise.scala 72:15] + node _T_473 = mux(_T_472, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_474 = and(UInt<3>("h04"), _T_473) @[axi4_to_ahb.scala 175:15] + node _T_475 = or(_T_466, _T_474) @[axi4_to_ahb.scala 174:63] + node _T_476 = bits(_T_449, 7, 0) @[axi4_to_ahb.scala 176:37] + node _T_477 = eq(_T_476, UInt<8>("h0c0")) @[axi4_to_ahb.scala 176:44] + node _T_478 = bits(_T_477, 0, 0) @[Bitwise.scala 72:15] + node _T_479 = mux(_T_478, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_480 = and(UInt<3>("h06"), _T_479) @[axi4_to_ahb.scala 176:17] + node _T_481 = or(_T_475, _T_480) @[axi4_to_ahb.scala 175:96] + node _T_482 = bits(_T_449, 7, 0) @[axi4_to_ahb.scala 177:37] + node _T_483 = eq(_T_482, UInt<8>("h0c0")) @[axi4_to_ahb.scala 177:44] + node _T_484 = bits(_T_483, 0, 0) @[Bitwise.scala 72:15] + node _T_485 = mux(_T_484, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_486 = and(UInt<3>("h06"), _T_485) @[axi4_to_ahb.scala 177:17] + node _T_487 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 343:152] + node _T_488 = mux(_T_448, _T_481, _T_487) @[axi4_to_ahb.scala 343:43] + node _T_489 = cat(_T_444, _T_488) @[Cat.scala 29:58] + buf_addr_in <= _T_489 @[axi4_to_ahb.scala 343:15] + node _T_490 = bits(master_tag, 0, 0) @[axi4_to_ahb.scala 344:27] + buf_tag_in <= _T_490 @[axi4_to_ahb.scala 344:14] + node _T_491 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 345:32] + buf_byteen_in <= _T_491 @[axi4_to_ahb.scala 345:17] + node _T_492 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 346:33] + node _T_493 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 346:59] + node _T_494 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 346:80] + node _T_495 = mux(_T_492, _T_493, _T_494) @[axi4_to_ahb.scala 346:21] + buf_data_in <= _T_495 @[axi4_to_ahb.scala 346:15] + node _T_496 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 347:52] + node _T_497 = eq(_T_496, UInt<2>("h03")) @[axi4_to_ahb.scala 347:58] + node _T_498 = and(buf_aligned_in, _T_497) @[axi4_to_ahb.scala 347:38] + node _T_499 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 347:84] + node _T_500 = eq(_T_499, UInt<1>("h01")) @[axi4_to_ahb.scala 347:91] + node _T_501 = and(_T_498, _T_500) @[axi4_to_ahb.scala 347:71] + node _T_502 = bits(_T_501, 0, 0) @[axi4_to_ahb.scala 347:111] + node _T_503 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 347:142] + node _T_504 = bits(_T_503, 7, 0) @[axi4_to_ahb.scala 166:42] + node _T_505 = eq(_T_504, UInt<8>("h0ff")) @[axi4_to_ahb.scala 166:49] + node _T_506 = bits(_T_505, 0, 0) @[Bitwise.scala 72:15] + node _T_507 = mux(_T_506, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_508 = and(UInt<2>("h03"), _T_507) @[axi4_to_ahb.scala 166:25] + node _T_509 = bits(_T_503, 7, 0) @[axi4_to_ahb.scala 167:35] + node _T_510 = eq(_T_509, UInt<8>("h0f0")) @[axi4_to_ahb.scala 167:42] + node _T_511 = bits(_T_503, 7, 0) @[axi4_to_ahb.scala 167:64] + node _T_512 = eq(_T_511, UInt<8>("h0f")) @[axi4_to_ahb.scala 167:71] + node _T_513 = or(_T_510, _T_512) @[axi4_to_ahb.scala 167:55] + node _T_514 = bits(_T_513, 0, 0) @[Bitwise.scala 72:15] + node _T_515 = mux(_T_514, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_516 = and(UInt<2>("h02"), _T_515) @[axi4_to_ahb.scala 167:16] + node _T_517 = or(_T_508, _T_516) @[axi4_to_ahb.scala 166:64] + node _T_518 = bits(_T_503, 7, 0) @[axi4_to_ahb.scala 168:40] + node _T_519 = eq(_T_518, UInt<8>("h0c0")) @[axi4_to_ahb.scala 168:47] + node _T_520 = bits(_T_503, 7, 0) @[axi4_to_ahb.scala 168:69] + node _T_521 = eq(_T_520, UInt<6>("h030")) @[axi4_to_ahb.scala 168:76] + node _T_522 = or(_T_519, _T_521) @[axi4_to_ahb.scala 168:60] + node _T_523 = bits(_T_503, 7, 0) @[axi4_to_ahb.scala 168:98] + node _T_524 = eq(_T_523, UInt<8>("h0c")) @[axi4_to_ahb.scala 168:105] + node _T_525 = or(_T_522, _T_524) @[axi4_to_ahb.scala 168:89] + node _T_526 = bits(_T_503, 7, 0) @[axi4_to_ahb.scala 168:132] + node _T_527 = eq(_T_526, UInt<8>("h03")) @[axi4_to_ahb.scala 168:139] + node _T_528 = or(_T_525, _T_527) @[axi4_to_ahb.scala 168:123] + node _T_529 = bits(_T_528, 0, 0) @[Bitwise.scala 72:15] + node _T_530 = mux(_T_529, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_531 = and(UInt<2>("h01"), _T_530) @[axi4_to_ahb.scala 168:21] + node _T_532 = or(_T_517, _T_531) @[axi4_to_ahb.scala 167:93] + node _T_533 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 347:161] + node _T_534 = mux(_T_502, _T_532, _T_533) @[axi4_to_ahb.scala 347:21] + buf_size_in <= _T_534 @[axi4_to_ahb.scala 347:15] + node _T_535 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 348:32] + node _T_536 = eq(_T_535, UInt<1>("h00")) @[axi4_to_ahb.scala 348:39] + node _T_537 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 349:17] + node _T_538 = eq(_T_537, UInt<1>("h00")) @[axi4_to_ahb.scala 349:24] + node _T_539 = or(_T_536, _T_538) @[axi4_to_ahb.scala 348:48] + node _T_540 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 349:47] + node _T_541 = eq(_T_540, UInt<2>("h01")) @[axi4_to_ahb.scala 349:54] + node _T_542 = or(_T_539, _T_541) @[axi4_to_ahb.scala 349:33] + node _T_543 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 349:86] + node _T_544 = eq(_T_543, UInt<2>("h02")) @[axi4_to_ahb.scala 349:93] + node _T_545 = or(_T_542, _T_544) @[axi4_to_ahb.scala 349:72] + node _T_546 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 350:18] + node _T_547 = eq(_T_546, UInt<2>("h03")) @[axi4_to_ahb.scala 350:25] + node _T_548 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 350:55] + node _T_549 = eq(_T_548, UInt<2>("h03")) @[axi4_to_ahb.scala 350:62] + node _T_550 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 350:90] + node _T_551 = eq(_T_550, UInt<4>("h0c")) @[axi4_to_ahb.scala 350:97] + node _T_552 = or(_T_549, _T_551) @[axi4_to_ahb.scala 350:74] + node _T_553 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 350:125] + node _T_554 = eq(_T_553, UInt<6>("h030")) @[axi4_to_ahb.scala 350:132] + node _T_555 = or(_T_552, _T_554) @[axi4_to_ahb.scala 350:109] + node _T_556 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 350:161] + node _T_557 = eq(_T_556, UInt<8>("h0c0")) @[axi4_to_ahb.scala 350:168] + node _T_558 = or(_T_555, _T_557) @[axi4_to_ahb.scala 350:145] + node _T_559 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 351:21] + node _T_560 = eq(_T_559, UInt<4>("h0f")) @[axi4_to_ahb.scala 351:28] + node _T_561 = or(_T_558, _T_560) @[axi4_to_ahb.scala 350:181] + node _T_562 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 351:56] + node _T_563 = eq(_T_562, UInt<8>("h0f0")) @[axi4_to_ahb.scala 351:63] + node _T_564 = or(_T_561, _T_563) @[axi4_to_ahb.scala 351:40] + node _T_565 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 351:92] + node _T_566 = eq(_T_565, UInt<8>("h0ff")) @[axi4_to_ahb.scala 351:99] + node _T_567 = or(_T_564, _T_566) @[axi4_to_ahb.scala 351:76] + node _T_568 = and(_T_547, _T_567) @[axi4_to_ahb.scala 350:38] + node _T_569 = or(_T_545, _T_568) @[axi4_to_ahb.scala 349:106] + buf_aligned_in <= _T_569 @[axi4_to_ahb.scala 348:18] + node _T_570 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 353:39] + node _T_571 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 353:58] + node _T_572 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 353:83] + node _T_573 = cat(_T_571, _T_572) @[Cat.scala 29:58] + node _T_574 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 353:104] + node _T_575 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 353:129] + node _T_576 = cat(_T_574, _T_575) @[Cat.scala 29:58] + node _T_577 = mux(_T_570, _T_573, _T_576) @[axi4_to_ahb.scala 353:22] + io.ahb_haddr <= _T_577 @[axi4_to_ahb.scala 353:16] + node _T_578 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 354:39] + node _T_579 = bits(buf_aligned_in, 0, 0) @[Bitwise.scala 72:15] + node _T_580 = mux(_T_579, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_581 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 354:90] + node _T_582 = and(_T_580, _T_581) @[axi4_to_ahb.scala 354:77] + node _T_583 = cat(UInt<1>("h00"), _T_582) @[Cat.scala 29:58] + node _T_584 = bits(buf_aligned, 0, 0) @[Bitwise.scala 72:15] + node _T_585 = mux(_T_584, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_586 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 354:144] + node _T_587 = and(_T_585, _T_586) @[axi4_to_ahb.scala 354:134] + node _T_588 = cat(UInt<1>("h00"), _T_587) @[Cat.scala 29:58] + node _T_589 = mux(_T_578, _T_583, _T_588) @[axi4_to_ahb.scala 354:22] + io.ahb_hsize <= _T_589 @[axi4_to_ahb.scala 354:16] + io.ahb_hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 356:17] + io.ahb_hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 357:20] + node _T_590 = bits(io.axi_arprot, 2, 2) @[axi4_to_ahb.scala 358:47] + node _T_591 = not(_T_590) @[axi4_to_ahb.scala 358:33] + node _T_592 = cat(UInt<1>("h01"), _T_591) @[Cat.scala 29:58] + io.ahb_hprot <= _T_592 @[axi4_to_ahb.scala 358:16] + node _T_593 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 359:40] + node _T_594 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 359:55] + node _T_595 = eq(_T_594, UInt<1>("h01")) @[axi4_to_ahb.scala 359:62] + node _T_596 = mux(_T_593, _T_595, buf_write) @[axi4_to_ahb.scala 359:23] + io.ahb_hwrite <= _T_596 @[axi4_to_ahb.scala 359:17] + node _T_597 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 360:28] + io.ahb_hwdata <= _T_597 @[axi4_to_ahb.scala 360:17] + slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 362:15] + node _T_598 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 363:43] + node _T_599 = mux(_T_598, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 363:23] + node _T_600 = bits(slvbuf_error, 0, 0) @[Bitwise.scala 72:15] + node _T_601 = mux(_T_600, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_602 = and(_T_601, UInt<2>("h02")) @[axi4_to_ahb.scala 363:88] + node _T_603 = cat(_T_599, _T_602) @[Cat.scala 29:58] + slave_opc <= _T_603 @[axi4_to_ahb.scala 363:13] + node _T_604 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 364:41] + node _T_605 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 364:66] + node _T_606 = cat(_T_605, _T_605) @[Cat.scala 29:58] + node _T_607 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 364:91] + node _T_608 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 364:110] + node _T_609 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 364:131] + node _T_610 = mux(_T_607, _T_608, _T_609) @[axi4_to_ahb.scala 364:79] + node _T_611 = mux(_T_604, _T_606, _T_610) @[axi4_to_ahb.scala 364:21] + slave_rdata <= _T_611 @[axi4_to_ahb.scala 364:15] + node _T_612 = bits(slvbuf_tag, 0, 0) @[axi4_to_ahb.scala 365:26] + slave_tag <= _T_612 @[axi4_to_ahb.scala 365:13] + node _T_613 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 367:33] + node _T_614 = neq(_T_613, UInt<1>("h00")) @[axi4_to_ahb.scala 367:40] + node _T_615 = and(_T_614, io.ahb_hready) @[axi4_to_ahb.scala 367:52] + node _T_616 = and(_T_615, io.ahb_hwrite) @[axi4_to_ahb.scala 367:68] + last_addr_en <= _T_616 @[axi4_to_ahb.scala 367:16] + node _T_617 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 369:30] + node _T_618 = and(_T_617, master_ready) @[axi4_to_ahb.scala 369:47] + wrbuf_en <= _T_618 @[axi4_to_ahb.scala 369:12] + node _T_619 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 370:34] + node _T_620 = and(_T_619, master_ready) @[axi4_to_ahb.scala 370:50] + wrbuf_data_en <= _T_620 @[axi4_to_ahb.scala 370:17] + node _T_621 = and(master_valid, master_ready) @[axi4_to_ahb.scala 371:34] + node _T_622 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 371:62] + node _T_623 = eq(_T_622, UInt<1>("h01")) @[axi4_to_ahb.scala 371:69] + node _T_624 = and(_T_621, _T_623) @[axi4_to_ahb.scala 371:49] + wrbuf_cmd_sent <= _T_624 @[axi4_to_ahb.scala 371:18] + node _T_625 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 372:33] + node _T_626 = and(wrbuf_cmd_sent, _T_625) @[axi4_to_ahb.scala 372:31] + wrbuf_rst <= _T_626 @[axi4_to_ahb.scala 372:13] + node _T_627 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 374:35] + node _T_628 = and(wrbuf_vld, _T_627) @[axi4_to_ahb.scala 374:33] + node _T_629 = eq(_T_628, UInt<1>("h00")) @[axi4_to_ahb.scala 374:21] + node _T_630 = and(_T_629, master_ready) @[axi4_to_ahb.scala 374:52] + io.axi_awready <= _T_630 @[axi4_to_ahb.scala 374:18] + node _T_631 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 375:39] + node _T_632 = and(wrbuf_data_vld, _T_631) @[axi4_to_ahb.scala 375:37] + node _T_633 = eq(_T_632, UInt<1>("h00")) @[axi4_to_ahb.scala 375:20] + node _T_634 = and(_T_633, master_ready) @[axi4_to_ahb.scala 375:56] + io.axi_wready <= _T_634 @[axi4_to_ahb.scala 375:17] + node _T_635 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 376:33] + node _T_636 = eq(_T_635, UInt<1>("h00")) @[axi4_to_ahb.scala 376:21] + node _T_637 = and(_T_636, master_ready) @[axi4_to_ahb.scala 376:51] + io.axi_arready <= _T_637 @[axi4_to_ahb.scala 376:18] + io.axi_rlast <= UInt<1>("h01") @[axi4_to_ahb.scala 377:16] + node _T_638 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 380:68] + node _T_639 = mux(_T_638, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 380:52] + node _T_640 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 380:88] + node _T_641 = and(_T_639, _T_640) @[axi4_to_ahb.scala 380:86] + reg _T_642 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 380:48] + _T_642 <= _T_641 @[axi4_to_ahb.scala 380:48] + wrbuf_vld <= _T_642 @[axi4_to_ahb.scala 380:18] + node _T_643 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 381:73] + node _T_644 = mux(_T_643, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 381:52] + node _T_645 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 381:99] + node _T_646 = and(_T_644, _T_645) @[axi4_to_ahb.scala 381:97] + reg _T_647 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 381:48] + _T_647 <= _T_646 @[axi4_to_ahb.scala 381:48] + wrbuf_data_vld <= _T_647 @[axi4_to_ahb.scala 381:18] + node _T_648 = bits(io.axi_awid, 0, 0) @[axi4_to_ahb.scala 383:57] + node _T_649 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 383:91] + reg _T_650 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_649 : @[Reg.scala 28:19] + _T_650 <= _T_648 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_tag <= _T_648 @[axi4_to_ahb.scala 382:13] - node _T_649 = bits(io.axi_awsize, 2, 0) @[axi4_to_ahb.scala 383:60] - node _T_650 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 383:88] - reg _T_651 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_650 : @[Reg.scala 28:19] - _T_651 <= _T_649 @[Reg.scala 28:23] + wrbuf_tag <= _T_650 @[axi4_to_ahb.scala 383:13] + node _T_651 = bits(io.axi_awsize, 2, 0) @[axi4_to_ahb.scala 384:60] + node _T_652 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 384:88] + reg _T_653 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_652 : @[Reg.scala 28:19] + _T_653 <= _T_651 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_size <= _T_651 @[axi4_to_ahb.scala 383:14] - node _T_652 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 385:48] + wrbuf_size <= _T_653 @[axi4_to_ahb.scala 384:14] + node _T_654 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 386:48] inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 508:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset rvclkhdr_2.io.clk <= bus_clk @[el2_lib.scala 510:18] - rvclkhdr_2.io.en <= _T_652 @[el2_lib.scala 511:17] + rvclkhdr_2.io.en <= _T_654 @[el2_lib.scala 511:17] rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_653 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_653 <= io.axi_awaddr @[el2_lib.scala 514:16] - wrbuf_addr <= _T_653 @[axi4_to_ahb.scala 385:14] - node _T_654 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 386:52] + reg _T_655 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_655 <= io.axi_awaddr @[el2_lib.scala 514:16] + wrbuf_addr <= _T_655 @[axi4_to_ahb.scala 386:14] + node _T_656 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 387:52] inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 508:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset rvclkhdr_3.io.clk <= bus_clk @[el2_lib.scala 510:18] - rvclkhdr_3.io.en <= _T_654 @[el2_lib.scala 511:17] + rvclkhdr_3.io.en <= _T_656 @[el2_lib.scala 511:17] rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_655 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_655 <= io.axi_wdata @[el2_lib.scala 514:16] - wrbuf_data <= _T_655 @[axi4_to_ahb.scala 386:14] - node _T_656 = bits(io.axi_wstrb, 7, 0) @[axi4_to_ahb.scala 389:27] - node _T_657 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 389:60] - reg _T_658 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_657 : @[Reg.scala 28:19] - _T_658 <= _T_656 @[Reg.scala 28:23] + reg _T_657 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_657 <= io.axi_wdata @[el2_lib.scala 514:16] + wrbuf_data <= _T_657 @[axi4_to_ahb.scala 387:14] + node _T_658 = bits(io.axi_wstrb, 7, 0) @[axi4_to_ahb.scala 390:27] + node _T_659 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 390:60] + reg _T_660 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_659 : @[Reg.scala 28:19] + _T_660 <= _T_658 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_byteen <= _T_658 @[axi4_to_ahb.scala 388:16] - node _T_659 = bits(io.ahb_haddr, 31, 0) @[axi4_to_ahb.scala 392:27] - node _T_660 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 392:60] - reg _T_661 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_660 : @[Reg.scala 28:19] - _T_661 <= _T_659 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - last_bus_addr <= _T_661 @[axi4_to_ahb.scala 391:17] - node _T_662 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 400:50] - reg _T_663 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + wrbuf_byteen <= _T_660 @[axi4_to_ahb.scala 389:16] + node _T_661 = bits(io.ahb_haddr, 31, 0) @[axi4_to_ahb.scala 393:27] + node _T_662 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 393:60] + reg _T_663 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_662 : @[Reg.scala 28:19] - _T_663 <= buf_write_in @[Reg.scala 28:23] + _T_663 <= _T_661 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_write <= _T_663 @[axi4_to_ahb.scala 399:13] - node _T_664 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 403:25] - node _T_665 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 403:60] - reg _T_666 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_665 : @[Reg.scala 28:19] - _T_666 <= _T_664 @[Reg.scala 28:23] + last_bus_addr <= _T_663 @[axi4_to_ahb.scala 392:17] + node _T_664 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 401:50] + reg _T_665 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_664 : @[Reg.scala 28:19] + _T_665 <= buf_write_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_tag <= _T_666 @[axi4_to_ahb.scala 402:11] - node _T_667 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 406:33] - node _T_668 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 406:52] - node _T_669 = bits(_T_668, 0, 0) @[axi4_to_ahb.scala 406:69] + buf_write <= _T_665 @[axi4_to_ahb.scala 400:13] + node _T_666 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 404:25] + node _T_667 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 404:60] + reg _T_668 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_667 : @[Reg.scala 28:19] + _T_668 <= _T_666 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_tag <= _T_668 @[axi4_to_ahb.scala 403:11] + node _T_669 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 407:33] + node _T_670 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 407:52] + node _T_671 = bits(_T_670, 0, 0) @[axi4_to_ahb.scala 407:69] inst rvclkhdr_4 of rvclkhdr_4 @[el2_lib.scala 508:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset rvclkhdr_4.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_4.io.en <= _T_669 @[el2_lib.scala 511:17] + rvclkhdr_4.io.en <= _T_671 @[el2_lib.scala 511:17] rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_670 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_670 <= _T_667 @[el2_lib.scala 514:16] - buf_addr <= _T_670 @[axi4_to_ahb.scala 406:12] - node _T_671 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 409:26] - node _T_672 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 409:55] - reg _T_673 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_672 : @[Reg.scala 28:19] - _T_673 <= _T_671 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_size <= _T_673 @[axi4_to_ahb.scala 408:12] - node _T_674 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 412:52] + reg _T_672 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_672 <= _T_669 @[el2_lib.scala 514:16] + buf_addr <= _T_672 @[axi4_to_ahb.scala 407:12] + node _T_673 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 410:26] + node _T_674 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 410:55] reg _T_675 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_674 : @[Reg.scala 28:19] - _T_675 <= buf_aligned_in @[Reg.scala 28:23] + _T_675 <= _T_673 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_aligned <= _T_675 @[axi4_to_ahb.scala 411:15] - node _T_676 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 415:28] - node _T_677 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 415:57] - reg _T_678 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_677 : @[Reg.scala 28:19] - _T_678 <= _T_676 @[Reg.scala 28:23] + buf_size <= _T_675 @[axi4_to_ahb.scala 409:12] + node _T_676 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 413:52] + reg _T_677 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_676 : @[Reg.scala 28:19] + _T_677 <= buf_aligned_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_byteen <= _T_678 @[axi4_to_ahb.scala 414:14] - node _T_679 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 418:33] - node _T_680 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 418:57] - node _T_681 = bits(_T_680, 0, 0) @[axi4_to_ahb.scala 418:80] + buf_aligned <= _T_677 @[axi4_to_ahb.scala 412:15] + node _T_678 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 416:28] + node _T_679 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 416:57] + reg _T_680 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_679 : @[Reg.scala 28:19] + _T_680 <= _T_678 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_byteen <= _T_680 @[axi4_to_ahb.scala 415:14] + node _T_681 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 419:33] + node _T_682 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 419:57] + node _T_683 = bits(_T_682, 0, 0) @[axi4_to_ahb.scala 419:80] inst rvclkhdr_5 of rvclkhdr_5 @[el2_lib.scala 508:23] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset rvclkhdr_5.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_5.io.en <= _T_681 @[el2_lib.scala 511:17] + rvclkhdr_5.io.en <= _T_683 @[el2_lib.scala 511:17] rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_682 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_682 <= _T_679 @[el2_lib.scala 514:16] - buf_data <= _T_682 @[axi4_to_ahb.scala 418:12] - node _T_683 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 421:50] - reg _T_684 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_683 : @[Reg.scala 28:19] - _T_684 <= buf_write @[Reg.scala 28:23] + reg _T_684 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_684 <= _T_681 @[el2_lib.scala 514:16] + buf_data <= _T_684 @[axi4_to_ahb.scala 419:12] + node _T_685 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 422:50] + reg _T_686 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_685 : @[Reg.scala 28:19] + _T_686 <= buf_write @[Reg.scala 28:23] skip @[Reg.scala 28:19] - slvbuf_write <= _T_684 @[axi4_to_ahb.scala 420:16] - node _T_685 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 424:22] - node _T_686 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 424:60] - reg _T_687 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_686 : @[Reg.scala 28:19] - _T_687 <= _T_685 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - slvbuf_tag <= _T_687 @[axi4_to_ahb.scala 423:14] - node _T_688 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 427:59] - reg _T_689 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + slvbuf_write <= _T_686 @[axi4_to_ahb.scala 421:16] + node _T_687 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 425:22] + node _T_688 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 425:60] + reg _T_689 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_688 : @[Reg.scala 28:19] - _T_689 <= slvbuf_error_in @[Reg.scala 28:23] + _T_689 <= _T_687 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - slvbuf_error <= _T_689 @[axi4_to_ahb.scala 426:16] - node _T_690 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 431:32] - node _T_691 = mux(_T_690, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 431:16] - node _T_692 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 431:52] - node _T_693 = and(_T_691, _T_692) @[axi4_to_ahb.scala 431:50] - reg _T_694 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 431:12] - _T_694 <= _T_693 @[axi4_to_ahb.scala 431:12] - cmd_doneQ <= _T_694 @[axi4_to_ahb.scala 430:13] - node _T_695 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 435:31] - node _T_696 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 435:70] - reg _T_697 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_696 : @[Reg.scala 28:19] - _T_697 <= _T_695 @[Reg.scala 28:23] + slvbuf_tag <= _T_689 @[axi4_to_ahb.scala 424:14] + node _T_690 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 428:59] + reg _T_691 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_690 : @[Reg.scala 28:19] + _T_691 <= slvbuf_error_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_cmd_byte_ptrQ <= _T_697 @[axi4_to_ahb.scala 434:21] - reg _T_698 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 440:12] - _T_698 <= io.ahb_hready @[axi4_to_ahb.scala 440:12] - ahb_hready_q <= _T_698 @[axi4_to_ahb.scala 439:16] - node _T_699 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 443:26] - reg _T_700 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 443:12] - _T_700 <= _T_699 @[axi4_to_ahb.scala 443:12] - ahb_htrans_q <= _T_700 @[axi4_to_ahb.scala 442:16] - reg _T_701 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 446:12] - _T_701 <= io.ahb_hwrite @[axi4_to_ahb.scala 446:12] - ahb_hwrite_q <= _T_701 @[axi4_to_ahb.scala 445:16] - reg _T_702 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 449:12] - _T_702 <= io.ahb_hresp @[axi4_to_ahb.scala 449:12] - ahb_hresp_q <= _T_702 @[axi4_to_ahb.scala 448:15] - node _T_703 = bits(io.ahb_hrdata, 63, 0) @[axi4_to_ahb.scala 452:26] - reg _T_704 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 452:12] - _T_704 <= _T_703 @[axi4_to_ahb.scala 452:12] - ahb_hrdata_q <= _T_704 @[axi4_to_ahb.scala 451:16] - node _T_705 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 455:43] - node _T_706 = or(_T_705, io.clk_override) @[axi4_to_ahb.scala 455:58] - node _T_707 = and(io.bus_clk_en, _T_706) @[axi4_to_ahb.scala 455:30] - buf_clken <= _T_707 @[axi4_to_ahb.scala 455:13] - node _T_708 = bits(io.ahb_htrans, 1, 1) @[axi4_to_ahb.scala 456:69] - node _T_709 = and(io.ahb_hready, _T_708) @[axi4_to_ahb.scala 456:54] - node _T_710 = or(_T_709, io.clk_override) @[axi4_to_ahb.scala 456:74] - node _T_711 = and(io.bus_clk_en, _T_710) @[axi4_to_ahb.scala 456:36] - ahbm_addr_clken <= _T_711 @[axi4_to_ahb.scala 456:19] - node _T_712 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 457:50] - node _T_713 = or(_T_712, io.clk_override) @[axi4_to_ahb.scala 457:60] - node _T_714 = and(io.bus_clk_en, _T_713) @[axi4_to_ahb.scala 457:36] - ahbm_data_clken <= _T_714 @[axi4_to_ahb.scala 457:19] + slvbuf_error <= _T_691 @[axi4_to_ahb.scala 427:16] + node _T_692 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 432:32] + node _T_693 = mux(_T_692, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 432:16] + node _T_694 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 432:52] + node _T_695 = and(_T_693, _T_694) @[axi4_to_ahb.scala 432:50] + reg _T_696 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 432:12] + _T_696 <= _T_695 @[axi4_to_ahb.scala 432:12] + cmd_doneQ <= _T_696 @[axi4_to_ahb.scala 431:13] + node _T_697 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 436:31] + node _T_698 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 436:70] + reg _T_699 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_698 : @[Reg.scala 28:19] + _T_699 <= _T_697 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_cmd_byte_ptrQ <= _T_699 @[axi4_to_ahb.scala 435:21] + reg _T_700 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 441:12] + _T_700 <= io.ahb_hready @[axi4_to_ahb.scala 441:12] + ahb_hready_q <= _T_700 @[axi4_to_ahb.scala 440:16] + node _T_701 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 444:26] + reg _T_702 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 444:12] + _T_702 <= _T_701 @[axi4_to_ahb.scala 444:12] + ahb_htrans_q <= _T_702 @[axi4_to_ahb.scala 443:16] + reg _T_703 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 447:12] + _T_703 <= io.ahb_hwrite @[axi4_to_ahb.scala 447:12] + ahb_hwrite_q <= _T_703 @[axi4_to_ahb.scala 446:16] + reg _T_704 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 450:12] + _T_704 <= io.ahb_hresp @[axi4_to_ahb.scala 450:12] + ahb_hresp_q <= _T_704 @[axi4_to_ahb.scala 449:15] + node _T_705 = bits(io.ahb_hrdata, 63, 0) @[axi4_to_ahb.scala 453:26] + reg _T_706 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 453:12] + _T_706 <= _T_705 @[axi4_to_ahb.scala 453:12] + ahb_hrdata_q <= _T_706 @[axi4_to_ahb.scala 452:16] + node _T_707 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 456:43] + node _T_708 = or(_T_707, io.clk_override) @[axi4_to_ahb.scala 456:58] + node _T_709 = and(io.bus_clk_en, _T_708) @[axi4_to_ahb.scala 456:30] + buf_clken <= _T_709 @[axi4_to_ahb.scala 456:13] + node _T_710 = bits(io.ahb_htrans, 1, 1) @[axi4_to_ahb.scala 457:69] + node _T_711 = and(io.ahb_hready, _T_710) @[axi4_to_ahb.scala 457:54] + node _T_712 = or(_T_711, io.clk_override) @[axi4_to_ahb.scala 457:74] + node _T_713 = and(io.bus_clk_en, _T_712) @[axi4_to_ahb.scala 457:36] + ahbm_addr_clken <= _T_713 @[axi4_to_ahb.scala 457:19] + node _T_714 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 458:50] + node _T_715 = or(_T_714, io.clk_override) @[axi4_to_ahb.scala 458:60] + node _T_716 = and(io.bus_clk_en, _T_715) @[axi4_to_ahb.scala 458:36] + ahbm_data_clken <= _T_716 @[axi4_to_ahb.scala 458:19] inst rvclkhdr_6 of rvclkhdr_6 @[el2_lib.scala 483:22] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset rvclkhdr_6.io.clk <= clock @[el2_lib.scala 484:17] rvclkhdr_6.io.en <= buf_clken @[el2_lib.scala 485:16] rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - buf_clk <= rvclkhdr_6.io.l1clk @[axi4_to_ahb.scala 460:12] + buf_clk <= rvclkhdr_6.io.l1clk @[axi4_to_ahb.scala 461:12] inst rvclkhdr_7 of rvclkhdr_7 @[el2_lib.scala 483:22] rvclkhdr_7.clock <= clock rvclkhdr_7.reset <= reset rvclkhdr_7.io.clk <= clock @[el2_lib.scala 484:17] rvclkhdr_7.io.en <= io.bus_clk_en @[el2_lib.scala 485:16] rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - ahbm_clk <= rvclkhdr_7.io.l1clk @[axi4_to_ahb.scala 461:12] + ahbm_clk <= rvclkhdr_7.io.l1clk @[axi4_to_ahb.scala 462:12] inst rvclkhdr_8 of rvclkhdr_8 @[el2_lib.scala 483:22] rvclkhdr_8.clock <= clock rvclkhdr_8.reset <= reset rvclkhdr_8.io.clk <= clock @[el2_lib.scala 484:17] rvclkhdr_8.io.en <= ahbm_addr_clken @[el2_lib.scala 485:16] rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - ahbm_addr_clk <= rvclkhdr_8.io.l1clk @[axi4_to_ahb.scala 462:17] + ahbm_addr_clk <= rvclkhdr_8.io.l1clk @[axi4_to_ahb.scala 463:17] inst rvclkhdr_9 of rvclkhdr_9 @[el2_lib.scala 483:22] rvclkhdr_9.clock <= clock rvclkhdr_9.reset <= reset rvclkhdr_9.io.clk <= clock @[el2_lib.scala 484:17] rvclkhdr_9.io.en <= ahbm_data_clken @[el2_lib.scala 485:16] rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - ahbm_data_clk <= rvclkhdr_9.io.l1clk @[axi4_to_ahb.scala 463:17] + ahbm_data_clk <= rvclkhdr_9.io.l1clk @[axi4_to_ahb.scala 464:17] diff --git a/axi4_to_ahb.v b/axi4_to_ahb.v index 7df2fcca..5288d030 100644 --- a/axi4_to_ahb.v +++ b/axi4_to_ahb.v @@ -132,98 +132,98 @@ module axi4_to_ahb( wire rvclkhdr_9_io_clk; // @[el2_lib.scala 483:22] wire rvclkhdr_9_io_en; // @[el2_lib.scala 483:22] wire rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 483:22] - wire ahbm_clk = rvclkhdr_7_io_l1clk; // @[axi4_to_ahb.scala 62:22 axi4_to_ahb.scala 461:12] + wire ahbm_clk = rvclkhdr_7_io_l1clk; // @[axi4_to_ahb.scala 62:22 axi4_to_ahb.scala 462:12] reg [2:0] buf_state; // @[axi4_to_ahb.scala 68:45] - wire _T_47 = 3'h0 == buf_state; // @[Conditional.scala 37:30] + wire _T_49 = 3'h0 == buf_state; // @[Conditional.scala 37:30] wire bus_clk = rvclkhdr_io_l1clk; // @[axi4_to_ahb.scala 88:21 axi4_to_ahb.scala 220:11] - reg wrbuf_vld; // @[axi4_to_ahb.scala 379:48] - reg wrbuf_data_vld; // @[axi4_to_ahb.scala 380:48] + reg wrbuf_vld; // @[axi4_to_ahb.scala 380:48] + reg wrbuf_data_vld; // @[axi4_to_ahb.scala 381:48] wire wr_cmd_vld = wrbuf_vld & wrbuf_data_vld; // @[axi4_to_ahb.scala 197:27] wire master_valid = wr_cmd_vld | io_axi_arvalid; // @[axi4_to_ahb.scala 198:30] - wire _T_99 = 3'h1 == buf_state; // @[Conditional.scala 37:30] - reg ahb_hready_q; // @[axi4_to_ahb.scala 440:12] - reg [1:0] ahb_htrans_q; // @[axi4_to_ahb.scala 443:12] - wire _T_106 = ahb_htrans_q != 2'h0; // @[axi4_to_ahb.scala 260:58] - wire _T_107 = ahb_hready_q & _T_106; // @[axi4_to_ahb.scala 260:36] - wire ahbm_addr_clk = rvclkhdr_8_io_l1clk; // @[axi4_to_ahb.scala 63:27 axi4_to_ahb.scala 462:17] - reg ahb_hwrite_q; // @[axi4_to_ahb.scala 446:12] - wire _T_108 = ~ahb_hwrite_q; // @[axi4_to_ahb.scala 260:72] - wire _T_109 = _T_107 & _T_108; // @[axi4_to_ahb.scala 260:70] - wire _T_134 = 3'h6 == buf_state; // @[Conditional.scala 37:30] - reg ahb_hresp_q; // @[axi4_to_ahb.scala 449:12] - wire _T_154 = ahb_hready_q | ahb_hresp_q; // @[axi4_to_ahb.scala 274:37] - wire _T_173 = 3'h7 == buf_state; // @[Conditional.scala 37:30] - wire _T_184 = 3'h3 == buf_state; // @[Conditional.scala 37:30] - wire _T_186 = 3'h2 == buf_state; // @[Conditional.scala 37:30] - wire _T_187 = ahb_hready_q & ahb_hwrite_q; // @[axi4_to_ahb.scala 306:33] - wire _T_190 = _T_187 & _T_106; // @[axi4_to_ahb.scala 306:48] - wire _T_279 = 3'h4 == buf_state; // @[Conditional.scala 37:30] - wire _GEN_15 = _T_279 & _T_190; // @[Conditional.scala 39:67] - wire _GEN_19 = _T_186 ? _T_190 : _GEN_15; // @[Conditional.scala 39:67] - wire _GEN_40 = _T_184 ? 1'h0 : _GEN_19; // @[Conditional.scala 39:67] - wire _GEN_59 = _T_173 ? 1'h0 : _GEN_40; // @[Conditional.scala 39:67] - wire _GEN_79 = _T_134 ? 1'h0 : _GEN_59; // @[Conditional.scala 39:67] - wire _GEN_95 = _T_99 ? 1'h0 : _GEN_79; // @[Conditional.scala 39:67] - wire trxn_done = _T_47 ? 1'h0 : _GEN_95; // @[Conditional.scala 40:58] - reg cmd_doneQ; // @[axi4_to_ahb.scala 431:12] - wire _T_280 = cmd_doneQ & ahb_hready_q; // @[axi4_to_ahb.scala 316:34] - wire _T_281 = _T_280 | ahb_hresp_q; // @[axi4_to_ahb.scala 316:50] - wire _T_441 = 3'h5 == buf_state; // @[Conditional.scala 37:30] + wire _T_101 = 3'h1 == buf_state; // @[Conditional.scala 37:30] + reg ahb_hready_q; // @[axi4_to_ahb.scala 441:12] + reg [1:0] ahb_htrans_q; // @[axi4_to_ahb.scala 444:12] + wire _T_108 = ahb_htrans_q != 2'h0; // @[axi4_to_ahb.scala 260:58] + wire _T_109 = ahb_hready_q & _T_108; // @[axi4_to_ahb.scala 260:36] + wire ahbm_addr_clk = rvclkhdr_8_io_l1clk; // @[axi4_to_ahb.scala 63:27 axi4_to_ahb.scala 463:17] + reg ahb_hwrite_q; // @[axi4_to_ahb.scala 447:12] + wire _T_110 = ~ahb_hwrite_q; // @[axi4_to_ahb.scala 260:72] + wire _T_111 = _T_109 & _T_110; // @[axi4_to_ahb.scala 260:70] + wire _T_136 = 3'h6 == buf_state; // @[Conditional.scala 37:30] + reg ahb_hresp_q; // @[axi4_to_ahb.scala 450:12] + wire _T_156 = ahb_hready_q | ahb_hresp_q; // @[axi4_to_ahb.scala 274:37] + wire _T_175 = 3'h7 == buf_state; // @[Conditional.scala 37:30] + wire _T_186 = 3'h3 == buf_state; // @[Conditional.scala 37:30] + wire _T_188 = 3'h2 == buf_state; // @[Conditional.scala 37:30] + wire _T_189 = ahb_hready_q & ahb_hwrite_q; // @[axi4_to_ahb.scala 306:33] + wire _T_192 = _T_189 & _T_108; // @[axi4_to_ahb.scala 306:48] + wire _T_281 = 3'h4 == buf_state; // @[Conditional.scala 37:30] + wire _GEN_15 = _T_281 & _T_192; // @[Conditional.scala 39:67] + wire _GEN_19 = _T_188 ? _T_192 : _GEN_15; // @[Conditional.scala 39:67] + wire _GEN_40 = _T_186 ? 1'h0 : _GEN_19; // @[Conditional.scala 39:67] + wire _GEN_59 = _T_175 ? 1'h0 : _GEN_40; // @[Conditional.scala 39:67] + wire _GEN_79 = _T_136 ? 1'h0 : _GEN_59; // @[Conditional.scala 39:67] + wire _GEN_95 = _T_101 ? 1'h0 : _GEN_79; // @[Conditional.scala 39:67] + wire trxn_done = _T_49 ? 1'h0 : _GEN_95; // @[Conditional.scala 40:58] + reg cmd_doneQ; // @[axi4_to_ahb.scala 432:12] + wire _T_282 = cmd_doneQ & ahb_hready_q; // @[axi4_to_ahb.scala 316:34] + wire _T_283 = _T_282 | ahb_hresp_q; // @[axi4_to_ahb.scala 316:50] + wire _T_443 = 3'h5 == buf_state; // @[Conditional.scala 37:30] wire slave_ready = io_axi_bready & io_axi_rready; // @[axi4_to_ahb.scala 215:32] - wire _GEN_1 = _T_441 & slave_ready; // @[Conditional.scala 39:67] - wire _GEN_3 = _T_279 ? _T_281 : _GEN_1; // @[Conditional.scala 39:67] - wire _GEN_20 = _T_186 ? trxn_done : _GEN_3; // @[Conditional.scala 39:67] - wire _GEN_35 = _T_184 ? _T_154 : _GEN_20; // @[Conditional.scala 39:67] - wire _GEN_51 = _T_173 ? _T_109 : _GEN_35; // @[Conditional.scala 39:67] - wire _GEN_69 = _T_134 ? _T_154 : _GEN_51; // @[Conditional.scala 39:67] - wire _GEN_83 = _T_99 ? _T_109 : _GEN_69; // @[Conditional.scala 39:67] - wire buf_state_en = _T_47 ? master_valid : _GEN_83; // @[Conditional.scala 40:58] - wire [1:0] _T_12 = wr_cmd_vld ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 200:20] - wire [2:0] master_opc = {{1'd0}, _T_12}; // @[axi4_to_ahb.scala 200:14] - wire _T_49 = master_opc[2:1] == 2'h1; // @[axi4_to_ahb.scala 245:41] - wire _GEN_8 = _T_279 & _T_49; // @[Conditional.scala 39:67] - wire _GEN_29 = _T_186 ? 1'h0 : _GEN_8; // @[Conditional.scala 39:67] - wire _GEN_46 = _T_184 ? 1'h0 : _GEN_29; // @[Conditional.scala 39:67] - wire _GEN_63 = _T_173 ? 1'h0 : _GEN_46; // @[Conditional.scala 39:67] - wire _GEN_81 = _T_134 ? 1'h0 : _GEN_63; // @[Conditional.scala 39:67] - wire _GEN_97 = _T_99 ? 1'h0 : _GEN_81; // @[Conditional.scala 39:67] - wire buf_write_in = _T_47 ? _T_49 : _GEN_97; // @[Conditional.scala 40:58] - wire [2:0] _T_51 = buf_write_in ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 246:26] - wire _T_101 = master_opc == 3'h0; // @[axi4_to_ahb.scala 259:61] - wire _T_102 = master_valid & _T_101; // @[axi4_to_ahb.scala 259:41] - wire [2:0] _T_104 = _T_102 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 259:26] - wire _T_122 = _T_104 == 3'h6; // @[axi4_to_ahb.scala 263:174] - wire _T_123 = _T_109 & _T_122; // @[axi4_to_ahb.scala 263:88] - wire _T_135 = ~ahb_hresp_q; // @[axi4_to_ahb.scala 271:39] - wire _T_136 = ahb_hready_q & _T_135; // @[axi4_to_ahb.scala 271:37] - wire _T_139 = master_valid & _T_49; // @[axi4_to_ahb.scala 271:70] - wire _T_140 = ~_T_139; // @[axi4_to_ahb.scala 271:55] - wire _T_141 = _T_136 & _T_140; // @[axi4_to_ahb.scala 271:53] - wire _T_285 = _T_281 & _T_135; // @[axi4_to_ahb.scala 317:66] - wire _T_286 = _T_285 & slave_ready; // @[axi4_to_ahb.scala 317:81] - wire _GEN_4 = _T_279 & _T_286; // @[Conditional.scala 39:67] - wire _GEN_26 = _T_186 ? 1'h0 : _GEN_4; // @[Conditional.scala 39:67] - wire _GEN_45 = _T_184 ? 1'h0 : _GEN_26; // @[Conditional.scala 39:67] - wire _GEN_62 = _T_173 ? 1'h0 : _GEN_45; // @[Conditional.scala 39:67] - wire _GEN_66 = _T_134 ? _T_141 : _GEN_62; // @[Conditional.scala 39:67] - wire _GEN_86 = _T_99 ? _T_123 : _GEN_66; // @[Conditional.scala 39:67] - wire master_ready = _T_47 | _GEN_86; // @[Conditional.scala 40:58] - wire _T_147 = master_valid & master_ready; // @[axi4_to_ahb.scala 273:82] - wire _T_150 = _T_147 & _T_101; // @[axi4_to_ahb.scala 273:97] - wire [2:0] _T_152 = _T_150 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 273:67] - wire [2:0] _T_153 = ahb_hresp_q ? 3'h7 : _T_152; // @[axi4_to_ahb.scala 273:26] - wire _T_287 = ~slave_ready; // @[axi4_to_ahb.scala 318:42] - wire _T_288 = ahb_hresp_q | _T_287; // @[axi4_to_ahb.scala 318:40] - wire [2:0] _T_294 = _T_49 ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 318:119] - wire [2:0] _T_295 = _T_147 ? _T_294 : 3'h0; // @[axi4_to_ahb.scala 318:75] - wire [2:0] _T_296 = _T_288 ? 3'h5 : _T_295; // @[axi4_to_ahb.scala 318:26] - wire [2:0] _GEN_5 = _T_279 ? _T_296 : 3'h0; // @[Conditional.scala 39:67] - wire [2:0] _GEN_18 = _T_186 ? 3'h4 : _GEN_5; // @[Conditional.scala 39:67] - wire [2:0] _GEN_34 = _T_184 ? 3'h5 : _GEN_18; // @[Conditional.scala 39:67] - wire [2:0] _GEN_50 = _T_173 ? 3'h3 : _GEN_34; // @[Conditional.scala 39:67] - wire [2:0] _GEN_68 = _T_134 ? _T_153 : _GEN_50; // @[Conditional.scala 39:67] - wire [2:0] _GEN_82 = _T_99 ? _T_104 : _GEN_68; // @[Conditional.scala 39:67] - wire [2:0] buf_nxtstate = _T_47 ? _T_51 : _GEN_82; // @[Conditional.scala 40:58] + wire _GEN_1 = _T_443 & slave_ready; // @[Conditional.scala 39:67] + wire _GEN_3 = _T_281 ? _T_283 : _GEN_1; // @[Conditional.scala 39:67] + wire _GEN_20 = _T_188 ? trxn_done : _GEN_3; // @[Conditional.scala 39:67] + wire _GEN_35 = _T_186 ? _T_156 : _GEN_20; // @[Conditional.scala 39:67] + wire _GEN_51 = _T_175 ? _T_111 : _GEN_35; // @[Conditional.scala 39:67] + wire _GEN_69 = _T_136 ? _T_156 : _GEN_51; // @[Conditional.scala 39:67] + wire _GEN_83 = _T_101 ? _T_111 : _GEN_69; // @[Conditional.scala 39:67] + wire buf_state_en = _T_49 ? master_valid : _GEN_83; // @[Conditional.scala 40:58] + wire [1:0] _T_14 = wr_cmd_vld ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 200:20] + wire [2:0] master_opc = {{1'd0}, _T_14}; // @[axi4_to_ahb.scala 200:14] + wire _T_51 = master_opc[2:1] == 2'h1; // @[axi4_to_ahb.scala 245:41] + wire _GEN_8 = _T_281 & _T_51; // @[Conditional.scala 39:67] + wire _GEN_29 = _T_188 ? 1'h0 : _GEN_8; // @[Conditional.scala 39:67] + wire _GEN_46 = _T_186 ? 1'h0 : _GEN_29; // @[Conditional.scala 39:67] + wire _GEN_63 = _T_175 ? 1'h0 : _GEN_46; // @[Conditional.scala 39:67] + wire _GEN_81 = _T_136 ? 1'h0 : _GEN_63; // @[Conditional.scala 39:67] + wire _GEN_97 = _T_101 ? 1'h0 : _GEN_81; // @[Conditional.scala 39:67] + wire buf_write_in = _T_49 ? _T_51 : _GEN_97; // @[Conditional.scala 40:58] + wire [2:0] _T_53 = buf_write_in ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 246:26] + wire _T_103 = master_opc == 3'h0; // @[axi4_to_ahb.scala 259:61] + wire _T_104 = master_valid & _T_103; // @[axi4_to_ahb.scala 259:41] + wire [2:0] _T_106 = _T_104 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 259:26] + wire _T_124 = _T_106 == 3'h6; // @[axi4_to_ahb.scala 263:174] + wire _T_125 = _T_111 & _T_124; // @[axi4_to_ahb.scala 263:88] + wire _T_137 = ~ahb_hresp_q; // @[axi4_to_ahb.scala 271:39] + wire _T_138 = ahb_hready_q & _T_137; // @[axi4_to_ahb.scala 271:37] + wire _T_141 = master_valid & _T_51; // @[axi4_to_ahb.scala 271:70] + wire _T_142 = ~_T_141; // @[axi4_to_ahb.scala 271:55] + wire _T_143 = _T_138 & _T_142; // @[axi4_to_ahb.scala 271:53] + wire _T_287 = _T_283 & _T_137; // @[axi4_to_ahb.scala 317:66] + wire _T_288 = _T_287 & slave_ready; // @[axi4_to_ahb.scala 317:81] + wire _GEN_4 = _T_281 & _T_288; // @[Conditional.scala 39:67] + wire _GEN_26 = _T_188 ? 1'h0 : _GEN_4; // @[Conditional.scala 39:67] + wire _GEN_45 = _T_186 ? 1'h0 : _GEN_26; // @[Conditional.scala 39:67] + wire _GEN_62 = _T_175 ? 1'h0 : _GEN_45; // @[Conditional.scala 39:67] + wire _GEN_66 = _T_136 ? _T_143 : _GEN_62; // @[Conditional.scala 39:67] + wire _GEN_86 = _T_101 ? _T_125 : _GEN_66; // @[Conditional.scala 39:67] + wire master_ready = _T_49 | _GEN_86; // @[Conditional.scala 40:58] + wire _T_149 = master_valid & master_ready; // @[axi4_to_ahb.scala 273:82] + wire _T_152 = _T_149 & _T_103; // @[axi4_to_ahb.scala 273:97] + wire [2:0] _T_154 = _T_152 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 273:67] + wire [2:0] _T_155 = ahb_hresp_q ? 3'h7 : _T_154; // @[axi4_to_ahb.scala 273:26] + wire _T_289 = ~slave_ready; // @[axi4_to_ahb.scala 318:42] + wire _T_290 = ahb_hresp_q | _T_289; // @[axi4_to_ahb.scala 318:40] + wire [2:0] _T_296 = _T_51 ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 318:119] + wire [2:0] _T_297 = _T_149 ? _T_296 : 3'h0; // @[axi4_to_ahb.scala 318:75] + wire [2:0] _T_298 = _T_290 ? 3'h5 : _T_297; // @[axi4_to_ahb.scala 318:26] + wire [2:0] _GEN_5 = _T_281 ? _T_298 : 3'h0; // @[Conditional.scala 39:67] + wire [2:0] _GEN_18 = _T_188 ? 3'h4 : _GEN_5; // @[Conditional.scala 39:67] + wire [2:0] _GEN_34 = _T_186 ? 3'h5 : _GEN_18; // @[Conditional.scala 39:67] + wire [2:0] _GEN_50 = _T_175 ? 3'h3 : _GEN_34; // @[Conditional.scala 39:67] + wire [2:0] _GEN_68 = _T_136 ? _T_155 : _GEN_50; // @[Conditional.scala 39:67] + wire [2:0] _GEN_82 = _T_101 ? _T_106 : _GEN_68; // @[Conditional.scala 39:67] + wire [2:0] buf_nxtstate = _T_49 ? _T_53 : _GEN_82; // @[Conditional.scala 40:58] reg wrbuf_tag; // @[Reg.scala 27:20] reg [31:0] wrbuf_addr; // @[el2_lib.scala 514:16] wire [31:0] master_addr = wr_cmd_vld ? wrbuf_addr : io_axi_araddr; // @[axi4_to_ahb.scala 201:21] @@ -231,267 +231,267 @@ module axi4_to_ahb( wire [2:0] master_size = wr_cmd_vld ? wrbuf_size : io_axi_arsize; // @[axi4_to_ahb.scala 202:21] reg [7:0] wrbuf_byteen; // @[Reg.scala 27:20] reg [63:0] wrbuf_data; // @[el2_lib.scala 514:16] - wire _T_156 = buf_state_en & _T_135; // @[axi4_to_ahb.scala 278:39] - wire _T_359 = buf_nxtstate != 3'h5; // @[axi4_to_ahb.scala 327:55] - wire _T_360 = buf_state_en & _T_359; // @[axi4_to_ahb.scala 327:39] - wire _GEN_14 = _T_279 ? _T_360 : _T_441; // @[Conditional.scala 39:67] - wire _GEN_33 = _T_186 ? 1'h0 : _GEN_14; // @[Conditional.scala 39:67] - wire _GEN_49 = _T_184 ? 1'h0 : _GEN_33; // @[Conditional.scala 39:67] - wire _GEN_52 = _T_173 ? buf_state_en : _GEN_49; // @[Conditional.scala 39:67] - wire _GEN_73 = _T_134 ? _T_156 : _GEN_52; // @[Conditional.scala 39:67] - wire _GEN_94 = _T_99 ? 1'h0 : _GEN_73; // @[Conditional.scala 39:67] - wire slave_valid_pre = _T_47 ? 1'h0 : _GEN_94; // @[Conditional.scala 40:58] - wire _T_23 = slave_valid_pre & slave_ready; // @[axi4_to_ahb.scala 207:32] - wire buf_clk = rvclkhdr_6_io_l1clk; // @[axi4_to_ahb.scala 156:21 axi4_to_ahb.scala 460:12] + wire _T_158 = buf_state_en & _T_137; // @[axi4_to_ahb.scala 278:39] + wire _T_361 = buf_nxtstate != 3'h5; // @[axi4_to_ahb.scala 327:55] + wire _T_362 = buf_state_en & _T_361; // @[axi4_to_ahb.scala 327:39] + wire _GEN_14 = _T_281 ? _T_362 : _T_443; // @[Conditional.scala 39:67] + wire _GEN_33 = _T_188 ? 1'h0 : _GEN_14; // @[Conditional.scala 39:67] + wire _GEN_49 = _T_186 ? 1'h0 : _GEN_33; // @[Conditional.scala 39:67] + wire _GEN_52 = _T_175 ? buf_state_en : _GEN_49; // @[Conditional.scala 39:67] + wire _GEN_73 = _T_136 ? _T_158 : _GEN_52; // @[Conditional.scala 39:67] + wire _GEN_94 = _T_101 ? 1'h0 : _GEN_73; // @[Conditional.scala 39:67] + wire slave_valid_pre = _T_49 ? 1'h0 : _GEN_94; // @[Conditional.scala 40:58] + wire _T_25 = slave_valid_pre & slave_ready; // @[axi4_to_ahb.scala 207:32] + wire buf_clk = rvclkhdr_6_io_l1clk; // @[axi4_to_ahb.scala 156:21 axi4_to_ahb.scala 461:12] reg slvbuf_write; // @[Reg.scala 27:20] - wire [1:0] _T_597 = slvbuf_write ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 362:23] + wire [1:0] _T_599 = slvbuf_write ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 363:23] reg slvbuf_error; // @[Reg.scala 27:20] - wire [1:0] _T_599 = slvbuf_error ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_600 = _T_599 & 2'h2; // @[axi4_to_ahb.scala 362:88] - wire [3:0] slave_opc = {_T_597,_T_600}; // @[Cat.scala 29:58] - wire [1:0] _T_28 = slave_opc[1] ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 208:49] + wire [1:0] _T_601 = slvbuf_error ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_602 = _T_601 & 2'h2; // @[axi4_to_ahb.scala 363:88] + wire [3:0] slave_opc = {_T_599,_T_602}; // @[Cat.scala 29:58] + wire [1:0] _T_30 = slave_opc[1] ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 208:49] reg slvbuf_tag; // @[Reg.scala 27:20] - wire _T_33 = slave_opc[3:2] == 2'h0; // @[axi4_to_ahb.scala 211:65] + wire _T_35 = slave_opc[3:2] == 2'h0; // @[axi4_to_ahb.scala 211:65] reg [31:0] last_bus_addr; // @[Reg.scala 27:20] - wire [63:0] _T_604 = {last_bus_addr,last_bus_addr}; // @[Cat.scala 29:58] - wire _T_605 = buf_state == 3'h5; // @[axi4_to_ahb.scala 363:91] + wire [63:0] _T_606 = {last_bus_addr,last_bus_addr}; // @[Cat.scala 29:58] + wire _T_607 = buf_state == 3'h5; // @[axi4_to_ahb.scala 364:91] reg [63:0] buf_data; // @[el2_lib.scala 514:16] - wire ahbm_data_clk = rvclkhdr_9_io_l1clk; // @[axi4_to_ahb.scala 64:27 axi4_to_ahb.scala 463:17] - reg [63:0] ahb_hrdata_q; // @[axi4_to_ahb.scala 452:12] - wire [63:0] _T_608 = _T_605 ? buf_data : ahb_hrdata_q; // @[axi4_to_ahb.scala 363:79] - wire _T_42 = io_axi_awvalid & io_axi_awready; // @[axi4_to_ahb.scala 218:56] - wire _T_43 = io_axi_wvalid & io_axi_wready; // @[axi4_to_ahb.scala 218:91] - wire _T_44 = _T_42 | _T_43; // @[axi4_to_ahb.scala 218:74] - wire _T_53 = buf_nxtstate == 3'h2; // @[axi4_to_ahb.scala 249:54] - wire _T_54 = buf_state_en & _T_53; // @[axi4_to_ahb.scala 249:38] - wire [2:0] _T_84 = wrbuf_byteen[7] ? 3'h7 : 3'h0; // @[Mux.scala 98:16] - wire [2:0] _T_85 = wrbuf_byteen[6] ? 3'h6 : _T_84; // @[Mux.scala 98:16] - wire [2:0] _T_86 = wrbuf_byteen[5] ? 3'h5 : _T_85; // @[Mux.scala 98:16] - wire [2:0] _T_87 = wrbuf_byteen[4] ? 3'h4 : _T_86; // @[Mux.scala 98:16] - wire [2:0] _T_88 = wrbuf_byteen[3] ? 3'h3 : _T_87; // @[Mux.scala 98:16] - wire [2:0] _T_89 = wrbuf_byteen[2] ? 3'h2 : _T_88; // @[Mux.scala 98:16] - wire [2:0] _T_90 = wrbuf_byteen[1] ? 3'h1 : _T_89; // @[Mux.scala 98:16] - wire [2:0] _T_91 = wrbuf_byteen[0] ? 3'h0 : _T_90; // @[Mux.scala 98:16] - wire [2:0] _T_93 = buf_write_in ? _T_91 : master_addr[2:0]; // @[axi4_to_ahb.scala 252:30] - wire _T_94 = buf_nxtstate == 3'h1; // @[axi4_to_ahb.scala 254:51] - wire _T_124 = master_ready & master_valid; // @[axi4_to_ahb.scala 265:33] - wire _T_160 = buf_nxtstate == 3'h6; // @[axi4_to_ahb.scala 280:64] - wire _T_161 = _T_124 & _T_160; // @[axi4_to_ahb.scala 280:48] - wire _T_162 = _T_161 & buf_state_en; // @[axi4_to_ahb.scala 280:79] - wire _T_350 = buf_state_en & buf_write_in; // @[axi4_to_ahb.scala 325:33] - wire _T_352 = _T_350 & _T_53; // @[axi4_to_ahb.scala 325:48] - wire _GEN_12 = _T_279 & _T_352; // @[Conditional.scala 39:67] - wire _GEN_32 = _T_186 ? 1'h0 : _GEN_12; // @[Conditional.scala 39:67] - wire _GEN_48 = _T_184 ? 1'h0 : _GEN_32; // @[Conditional.scala 39:67] - wire _GEN_65 = _T_173 ? 1'h0 : _GEN_48; // @[Conditional.scala 39:67] - wire _GEN_75 = _T_134 ? _T_162 : _GEN_65; // @[Conditional.scala 39:67] - wire _GEN_88 = _T_99 ? _T_124 : _GEN_75; // @[Conditional.scala 39:67] - wire bypass_en = _T_47 ? buf_state_en : _GEN_88; // @[Conditional.scala 40:58] - wire [1:0] _T_97 = bypass_en ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_98 = _T_97 & 2'h2; // @[axi4_to_ahb.scala 255:45] - wire _T_110 = ~master_valid; // @[axi4_to_ahb.scala 261:34] - wire _T_111 = buf_state_en & _T_110; // @[axi4_to_ahb.scala 261:32] + wire ahbm_data_clk = rvclkhdr_9_io_l1clk; // @[axi4_to_ahb.scala 64:27 axi4_to_ahb.scala 464:17] + reg [63:0] ahb_hrdata_q; // @[axi4_to_ahb.scala 453:12] + wire [63:0] _T_610 = _T_607 ? buf_data : ahb_hrdata_q; // @[axi4_to_ahb.scala 364:79] + wire _T_44 = io_axi_awvalid & io_axi_awready; // @[axi4_to_ahb.scala 218:56] + wire _T_45 = io_axi_wvalid & io_axi_wready; // @[axi4_to_ahb.scala 218:91] + wire _T_46 = _T_44 | _T_45; // @[axi4_to_ahb.scala 218:74] + wire _T_55 = buf_nxtstate == 3'h2; // @[axi4_to_ahb.scala 249:54] + wire _T_56 = buf_state_en & _T_55; // @[axi4_to_ahb.scala 249:38] + wire [2:0] _T_86 = wrbuf_byteen[7] ? 3'h7 : 3'h0; // @[Mux.scala 98:16] + wire [2:0] _T_87 = wrbuf_byteen[6] ? 3'h6 : _T_86; // @[Mux.scala 98:16] + wire [2:0] _T_88 = wrbuf_byteen[5] ? 3'h5 : _T_87; // @[Mux.scala 98:16] + wire [2:0] _T_89 = wrbuf_byteen[4] ? 3'h4 : _T_88; // @[Mux.scala 98:16] + wire [2:0] _T_90 = wrbuf_byteen[3] ? 3'h3 : _T_89; // @[Mux.scala 98:16] + wire [2:0] _T_91 = wrbuf_byteen[2] ? 3'h2 : _T_90; // @[Mux.scala 98:16] + wire [2:0] _T_92 = wrbuf_byteen[1] ? 3'h1 : _T_91; // @[Mux.scala 98:16] + wire [2:0] _T_93 = wrbuf_byteen[0] ? 3'h0 : _T_92; // @[Mux.scala 98:16] + wire [2:0] _T_95 = buf_write_in ? _T_93 : master_addr[2:0]; // @[axi4_to_ahb.scala 252:30] + wire _T_96 = buf_nxtstate == 3'h1; // @[axi4_to_ahb.scala 254:51] + wire _T_126 = master_ready & master_valid; // @[axi4_to_ahb.scala 265:33] + wire _T_162 = buf_nxtstate == 3'h6; // @[axi4_to_ahb.scala 280:64] + wire _T_163 = _T_126 & _T_162; // @[axi4_to_ahb.scala 280:48] + wire _T_164 = _T_163 & buf_state_en; // @[axi4_to_ahb.scala 280:79] + wire _T_352 = buf_state_en & buf_write_in; // @[axi4_to_ahb.scala 325:33] + wire _T_354 = _T_352 & _T_55; // @[axi4_to_ahb.scala 325:48] + wire _GEN_12 = _T_281 & _T_354; // @[Conditional.scala 39:67] + wire _GEN_32 = _T_188 ? 1'h0 : _GEN_12; // @[Conditional.scala 39:67] + wire _GEN_48 = _T_186 ? 1'h0 : _GEN_32; // @[Conditional.scala 39:67] + wire _GEN_65 = _T_175 ? 1'h0 : _GEN_48; // @[Conditional.scala 39:67] + wire _GEN_75 = _T_136 ? _T_164 : _GEN_65; // @[Conditional.scala 39:67] + wire _GEN_88 = _T_101 ? _T_126 : _GEN_75; // @[Conditional.scala 39:67] + wire bypass_en = _T_49 ? buf_state_en : _GEN_88; // @[Conditional.scala 40:58] + wire [1:0] _T_99 = bypass_en ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_100 = _T_99 & 2'h2; // @[axi4_to_ahb.scala 255:45] + wire _T_112 = ~master_valid; // @[axi4_to_ahb.scala 261:34] + wire _T_113 = buf_state_en & _T_112; // @[axi4_to_ahb.scala 261:32] reg [31:0] buf_addr; // @[el2_lib.scala 514:16] - wire [2:0] _T_128 = bypass_en ? master_addr[2:0] : buf_addr[2:0]; // @[axi4_to_ahb.scala 266:30] - wire _T_129 = ~buf_state_en; // @[axi4_to_ahb.scala 267:44] - wire _T_130 = _T_129 | bypass_en; // @[axi4_to_ahb.scala 267:58] - wire [1:0] _T_132 = _T_130 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_133 = 2'h2 & _T_132; // @[axi4_to_ahb.scala 267:32] - wire _T_167 = buf_nxtstate != 3'h6; // @[axi4_to_ahb.scala 282:59] - wire _T_168 = _T_167 & buf_state_en; // @[axi4_to_ahb.scala 282:74] - wire _T_169 = ~_T_168; // @[axi4_to_ahb.scala 282:43] - wire [1:0] _T_171 = _T_169 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_172 = 2'h2 & _T_171; // @[axi4_to_ahb.scala 282:32] - wire [1:0] _T_182 = _T_129 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_183 = 2'h2 & _T_182; // @[axi4_to_ahb.scala 292:37] + wire [2:0] _T_130 = bypass_en ? master_addr[2:0] : buf_addr[2:0]; // @[axi4_to_ahb.scala 266:30] + wire _T_131 = ~buf_state_en; // @[axi4_to_ahb.scala 267:44] + wire _T_132 = _T_131 | bypass_en; // @[axi4_to_ahb.scala 267:58] + wire [1:0] _T_134 = _T_132 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_135 = 2'h2 & _T_134; // @[axi4_to_ahb.scala 267:32] + wire _T_169 = buf_nxtstate != 3'h6; // @[axi4_to_ahb.scala 282:59] + wire _T_170 = _T_169 & buf_state_en; // @[axi4_to_ahb.scala 282:74] + wire _T_171 = ~_T_170; // @[axi4_to_ahb.scala 282:43] + wire [1:0] _T_173 = _T_171 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_174 = 2'h2 & _T_173; // @[axi4_to_ahb.scala 282:32] + wire [1:0] _T_184 = _T_131 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_185 = 2'h2 & _T_184; // @[axi4_to_ahb.scala 292:37] reg [2:0] buf_cmd_byte_ptrQ; // @[Reg.scala 27:20] reg [7:0] buf_byteen; // @[Reg.scala 27:20] - wire [2:0] _T_195 = buf_cmd_byte_ptrQ + 3'h1; // @[axi4_to_ahb.scala 181:52] - wire _T_198 = 3'h0 >= _T_195; // @[axi4_to_ahb.scala 182:62] - wire _T_199 = buf_byteen[0] & _T_198; // @[axi4_to_ahb.scala 182:48] - wire _T_201 = 3'h1 >= _T_195; // @[axi4_to_ahb.scala 182:62] - wire _T_202 = buf_byteen[1] & _T_201; // @[axi4_to_ahb.scala 182:48] - wire _T_204 = 3'h2 >= _T_195; // @[axi4_to_ahb.scala 182:62] - wire _T_205 = buf_byteen[2] & _T_204; // @[axi4_to_ahb.scala 182:48] - wire _T_207 = 3'h3 >= _T_195; // @[axi4_to_ahb.scala 182:62] - wire _T_208 = buf_byteen[3] & _T_207; // @[axi4_to_ahb.scala 182:48] - wire _T_210 = 3'h4 >= _T_195; // @[axi4_to_ahb.scala 182:62] - wire _T_211 = buf_byteen[4] & _T_210; // @[axi4_to_ahb.scala 182:48] - wire _T_213 = 3'h5 >= _T_195; // @[axi4_to_ahb.scala 182:62] - wire _T_214 = buf_byteen[5] & _T_213; // @[axi4_to_ahb.scala 182:48] - wire _T_216 = 3'h6 >= _T_195; // @[axi4_to_ahb.scala 182:62] - wire _T_217 = buf_byteen[6] & _T_216; // @[axi4_to_ahb.scala 182:48] - wire [2:0] _T_221 = buf_byteen[7] ? 3'h7 : 3'h0; // @[Mux.scala 98:16] - wire [2:0] _T_222 = _T_217 ? 3'h6 : _T_221; // @[Mux.scala 98:16] - wire [2:0] _T_223 = _T_214 ? 3'h5 : _T_222; // @[Mux.scala 98:16] - wire [2:0] _T_224 = _T_211 ? 3'h4 : _T_223; // @[Mux.scala 98:16] - wire [2:0] _T_225 = _T_208 ? 3'h3 : _T_224; // @[Mux.scala 98:16] - wire [2:0] _T_226 = _T_205 ? 3'h2 : _T_225; // @[Mux.scala 98:16] - wire [2:0] _T_227 = _T_202 ? 3'h1 : _T_226; // @[Mux.scala 98:16] - wire [2:0] _T_228 = _T_199 ? 3'h0 : _T_227; // @[Mux.scala 98:16] - wire [2:0] _T_229 = trxn_done ? _T_228 : buf_cmd_byte_ptrQ; // @[axi4_to_ahb.scala 310:30] - wire _T_230 = buf_cmd_byte_ptrQ == 3'h7; // @[axi4_to_ahb.scala 311:65] + wire [2:0] _T_197 = buf_cmd_byte_ptrQ + 3'h1; // @[axi4_to_ahb.scala 181:52] + wire _T_200 = 3'h0 >= _T_197; // @[axi4_to_ahb.scala 182:62] + wire _T_201 = buf_byteen[0] & _T_200; // @[axi4_to_ahb.scala 182:48] + wire _T_203 = 3'h1 >= _T_197; // @[axi4_to_ahb.scala 182:62] + wire _T_204 = buf_byteen[1] & _T_203; // @[axi4_to_ahb.scala 182:48] + wire _T_206 = 3'h2 >= _T_197; // @[axi4_to_ahb.scala 182:62] + wire _T_207 = buf_byteen[2] & _T_206; // @[axi4_to_ahb.scala 182:48] + wire _T_209 = 3'h3 >= _T_197; // @[axi4_to_ahb.scala 182:62] + wire _T_210 = buf_byteen[3] & _T_209; // @[axi4_to_ahb.scala 182:48] + wire _T_212 = 3'h4 >= _T_197; // @[axi4_to_ahb.scala 182:62] + wire _T_213 = buf_byteen[4] & _T_212; // @[axi4_to_ahb.scala 182:48] + wire _T_215 = 3'h5 >= _T_197; // @[axi4_to_ahb.scala 182:62] + wire _T_216 = buf_byteen[5] & _T_215; // @[axi4_to_ahb.scala 182:48] + wire _T_218 = 3'h6 >= _T_197; // @[axi4_to_ahb.scala 182:62] + wire _T_219 = buf_byteen[6] & _T_218; // @[axi4_to_ahb.scala 182:48] + wire [2:0] _T_223 = buf_byteen[7] ? 3'h7 : 3'h0; // @[Mux.scala 98:16] + wire [2:0] _T_224 = _T_219 ? 3'h6 : _T_223; // @[Mux.scala 98:16] + wire [2:0] _T_225 = _T_216 ? 3'h5 : _T_224; // @[Mux.scala 98:16] + wire [2:0] _T_226 = _T_213 ? 3'h4 : _T_225; // @[Mux.scala 98:16] + wire [2:0] _T_227 = _T_210 ? 3'h3 : _T_226; // @[Mux.scala 98:16] + wire [2:0] _T_228 = _T_207 ? 3'h2 : _T_227; // @[Mux.scala 98:16] + wire [2:0] _T_229 = _T_204 ? 3'h1 : _T_228; // @[Mux.scala 98:16] + wire [2:0] _T_230 = _T_201 ? 3'h0 : _T_229; // @[Mux.scala 98:16] + wire [2:0] _T_231 = trxn_done ? _T_230 : buf_cmd_byte_ptrQ; // @[axi4_to_ahb.scala 310:30] + wire _T_232 = buf_cmd_byte_ptrQ == 3'h7; // @[axi4_to_ahb.scala 311:65] reg buf_aligned; // @[Reg.scala 27:20] - wire _T_231 = buf_aligned | _T_230; // @[axi4_to_ahb.scala 311:44] - wire [7:0] _T_269 = buf_byteen >> _T_228; // @[axi4_to_ahb.scala 311:92] - wire _T_271 = ~_T_269[0]; // @[axi4_to_ahb.scala 311:163] - wire _T_272 = _T_231 | _T_271; // @[axi4_to_ahb.scala 311:79] - wire _T_273 = trxn_done & _T_272; // @[axi4_to_ahb.scala 311:29] - wire _T_347 = _T_230 | _T_271; // @[axi4_to_ahb.scala 324:118] - wire _T_348 = _T_107 & _T_347; // @[axi4_to_ahb.scala 324:82] - wire _T_349 = ahb_hresp_q | _T_348; // @[axi4_to_ahb.scala 324:32] - wire _GEN_11 = _T_279 & _T_349; // @[Conditional.scala 39:67] - wire _GEN_24 = _T_186 ? _T_273 : _GEN_11; // @[Conditional.scala 39:67] - wire _GEN_43 = _T_184 ? 1'h0 : _GEN_24; // @[Conditional.scala 39:67] - wire _GEN_61 = _T_173 ? 1'h0 : _GEN_43; // @[Conditional.scala 39:67] - wire _GEN_74 = _T_134 ? _T_111 : _GEN_61; // @[Conditional.scala 39:67] - wire _GEN_84 = _T_99 ? _T_111 : _GEN_74; // @[Conditional.scala 39:67] - wire cmd_done = _T_47 ? 1'h0 : _GEN_84; // @[Conditional.scala 40:58] - wire _T_274 = cmd_done | cmd_doneQ; // @[axi4_to_ahb.scala 312:43] - wire _T_275 = ~_T_274; // @[axi4_to_ahb.scala 312:32] - wire [1:0] _T_277 = _T_275 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_278 = _T_277 & 2'h2; // @[axi4_to_ahb.scala 312:57] - wire _T_301 = _T_53 | _T_94; // @[axi4_to_ahb.scala 322:62] - wire _T_302 = buf_state_en & _T_301; // @[axi4_to_ahb.scala 322:33] - wire _T_355 = _T_275 | bypass_en; // @[axi4_to_ahb.scala 326:57] - wire [1:0] _T_357 = _T_355 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_358 = _T_357 & 2'h2; // @[axi4_to_ahb.scala 326:71] - wire _T_365 = trxn_done | bypass_en; // @[axi4_to_ahb.scala 329:40] - wire [2:0] _T_440 = bypass_en ? _T_91 : _T_229; // @[axi4_to_ahb.scala 332:30] - wire _GEN_6 = _T_279 & ahb_hresp_q; // @[Conditional.scala 39:67] - wire _GEN_7 = _T_279 ? buf_state_en : _T_441; // @[Conditional.scala 39:67] - wire _GEN_9 = _T_279 & _T_302; // @[Conditional.scala 39:67] - wire _GEN_30 = _T_186 ? 1'h0 : _GEN_9; // @[Conditional.scala 39:67] - wire _GEN_47 = _T_184 ? 1'h0 : _GEN_30; // @[Conditional.scala 39:67] - wire _GEN_64 = _T_173 ? 1'h0 : _GEN_47; // @[Conditional.scala 39:67] - wire _GEN_67 = _T_134 ? _T_150 : _GEN_64; // @[Conditional.scala 39:67] - wire _GEN_87 = _T_99 ? master_ready : _GEN_67; // @[Conditional.scala 39:67] - wire buf_wr_en = _T_47 ? buf_state_en : _GEN_87; // @[Conditional.scala 40:58] - wire _GEN_10 = _T_279 & buf_wr_en; // @[Conditional.scala 39:67] - wire [1:0] _GEN_13 = _T_279 ? _T_358 : 2'h0; // @[Conditional.scala 39:67] - wire _GEN_16 = _T_279 & _T_365; // @[Conditional.scala 39:67] - wire [2:0] _GEN_17 = _T_279 ? _T_440 : 3'h0; // @[Conditional.scala 39:67] - wire _GEN_21 = _T_186 ? buf_state_en : _GEN_16; // @[Conditional.scala 39:67] - wire _GEN_22 = _T_186 & buf_state_en; // @[Conditional.scala 39:67] - wire [2:0] _GEN_23 = _T_186 ? _T_229 : _GEN_17; // @[Conditional.scala 39:67] - wire [1:0] _GEN_25 = _T_186 ? _T_278 : _GEN_13; // @[Conditional.scala 39:67] - wire _GEN_28 = _T_186 ? 1'h0 : _GEN_7; // @[Conditional.scala 39:67] - wire _GEN_31 = _T_186 ? 1'h0 : _GEN_10; // @[Conditional.scala 39:67] - wire _GEN_36 = _T_184 ? buf_state_en : _GEN_31; // @[Conditional.scala 39:67] - wire _GEN_38 = _T_184 ? buf_state_en : _GEN_28; // @[Conditional.scala 39:67] - wire _GEN_39 = _T_184 ? buf_state_en : _GEN_22; // @[Conditional.scala 39:67] - wire _GEN_41 = _T_184 ? 1'h0 : _GEN_21; // @[Conditional.scala 39:67] - wire [2:0] _GEN_42 = _T_184 ? 3'h0 : _GEN_23; // @[Conditional.scala 39:67] - wire [1:0] _GEN_44 = _T_184 ? 2'h0 : _GEN_25; // @[Conditional.scala 39:67] - wire _GEN_53 = _T_173 ? buf_state_en : _GEN_39; // @[Conditional.scala 39:67] - wire [2:0] _GEN_54 = _T_173 ? buf_addr[2:0] : _GEN_42; // @[Conditional.scala 39:67] - wire [1:0] _GEN_55 = _T_173 ? _T_183 : _GEN_44; // @[Conditional.scala 39:67] - wire _GEN_56 = _T_173 ? 1'h0 : _GEN_36; // @[Conditional.scala 39:67] - wire _GEN_58 = _T_173 ? 1'h0 : _GEN_38; // @[Conditional.scala 39:67] - wire _GEN_60 = _T_173 ? 1'h0 : _GEN_41; // @[Conditional.scala 39:67] - wire _GEN_70 = _T_134 ? buf_state_en : _GEN_56; // @[Conditional.scala 39:67] - wire _GEN_72 = _T_134 ? buf_state_en : _GEN_58; // @[Conditional.scala 39:67] - wire [2:0] _GEN_76 = _T_134 ? _T_128 : _GEN_54; // @[Conditional.scala 39:67] - wire [1:0] _GEN_77 = _T_134 ? _T_172 : _GEN_55; // @[Conditional.scala 39:67] - wire _GEN_78 = _T_134 ? buf_wr_en : _GEN_53; // @[Conditional.scala 39:67] - wire _GEN_80 = _T_134 ? 1'h0 : _GEN_60; // @[Conditional.scala 39:67] - wire _GEN_85 = _T_99 ? buf_state_en : _GEN_78; // @[Conditional.scala 39:67] - wire [2:0] _GEN_89 = _T_99 ? _T_128 : _GEN_76; // @[Conditional.scala 39:67] - wire [1:0] _GEN_90 = _T_99 ? _T_133 : _GEN_77; // @[Conditional.scala 39:67] - wire _GEN_91 = _T_99 ? 1'h0 : _GEN_70; // @[Conditional.scala 39:67] - wire _GEN_93 = _T_99 ? 1'h0 : _GEN_72; // @[Conditional.scala 39:67] - wire _GEN_96 = _T_99 ? 1'h0 : _GEN_80; // @[Conditional.scala 39:67] - wire buf_data_wr_en = _T_47 ? _T_54 : _GEN_91; // @[Conditional.scala 40:58] - wire buf_cmd_byte_ptr_en = _T_47 ? buf_state_en : _GEN_96; // @[Conditional.scala 40:58] - wire [2:0] buf_cmd_byte_ptr = _T_47 ? _T_93 : _GEN_89; // @[Conditional.scala 40:58] - wire slvbuf_wr_en = _T_47 ? 1'h0 : _GEN_85; // @[Conditional.scala 40:58] - wire slvbuf_error_en = _T_47 ? 1'h0 : _GEN_93; // @[Conditional.scala 40:58] - wire _T_536 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 348:24] - wire _T_537 = _T_101 | _T_536; // @[axi4_to_ahb.scala 347:48] - wire _T_539 = master_size[1:0] == 2'h1; // @[axi4_to_ahb.scala 348:54] - wire _T_540 = _T_537 | _T_539; // @[axi4_to_ahb.scala 348:33] - wire _T_542 = master_size[1:0] == 2'h2; // @[axi4_to_ahb.scala 348:93] - wire _T_543 = _T_540 | _T_542; // @[axi4_to_ahb.scala 348:72] - wire _T_545 = master_size[1:0] == 2'h3; // @[axi4_to_ahb.scala 349:25] - wire _T_547 = wrbuf_byteen == 8'h3; // @[axi4_to_ahb.scala 349:62] - wire _T_549 = wrbuf_byteen == 8'hc; // @[axi4_to_ahb.scala 349:97] - wire _T_550 = _T_547 | _T_549; // @[axi4_to_ahb.scala 349:74] - wire _T_552 = wrbuf_byteen == 8'h30; // @[axi4_to_ahb.scala 349:132] - wire _T_553 = _T_550 | _T_552; // @[axi4_to_ahb.scala 349:109] - wire _T_555 = wrbuf_byteen == 8'hc0; // @[axi4_to_ahb.scala 349:168] - wire _T_556 = _T_553 | _T_555; // @[axi4_to_ahb.scala 349:145] - wire _T_558 = wrbuf_byteen == 8'hf; // @[axi4_to_ahb.scala 350:28] - wire _T_559 = _T_556 | _T_558; // @[axi4_to_ahb.scala 349:181] - wire _T_561 = wrbuf_byteen == 8'hf0; // @[axi4_to_ahb.scala 350:63] - wire _T_562 = _T_559 | _T_561; // @[axi4_to_ahb.scala 350:40] - wire _T_564 = wrbuf_byteen == 8'hff; // @[axi4_to_ahb.scala 350:99] - wire _T_565 = _T_562 | _T_564; // @[axi4_to_ahb.scala 350:76] - wire _T_566 = _T_545 & _T_565; // @[axi4_to_ahb.scala 349:38] - wire buf_aligned_in = _T_543 | _T_566; // @[axi4_to_ahb.scala 348:106] - wire _T_445 = buf_aligned_in & _T_49; // @[axi4_to_ahb.scala 342:60] - wire [2:0] _T_462 = _T_549 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_463 = 3'h2 & _T_462; // @[axi4_to_ahb.scala 174:15] - wire _T_469 = _T_561 | _T_547; // @[axi4_to_ahb.scala 175:56] - wire [2:0] _T_471 = _T_469 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_472 = 3'h4 & _T_471; // @[axi4_to_ahb.scala 175:15] - wire [2:0] _T_473 = _T_463 | _T_472; // @[axi4_to_ahb.scala 174:63] - wire [2:0] _T_477 = _T_555 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_478 = 3'h6 & _T_477; // @[axi4_to_ahb.scala 176:17] - wire [2:0] _T_479 = _T_473 | _T_478; // @[axi4_to_ahb.scala 175:96] - wire [2:0] _T_486 = _T_445 ? _T_479 : master_addr[2:0]; // @[axi4_to_ahb.scala 342:43] - wire _T_490 = buf_state == 3'h3; // @[axi4_to_ahb.scala 345:33] - wire _T_496 = buf_aligned_in & _T_545; // @[axi4_to_ahb.scala 346:38] - wire _T_499 = _T_496 & _T_49; // @[axi4_to_ahb.scala 346:71] - wire [1:0] _T_505 = _T_564 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire _T_511 = _T_561 | _T_558; // @[axi4_to_ahb.scala 167:55] - wire [1:0] _T_513 = _T_511 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_514 = 2'h2 & _T_513; // @[axi4_to_ahb.scala 167:16] - wire [1:0] _T_515 = _T_505 | _T_514; // @[axi4_to_ahb.scala 166:64] - wire _T_520 = _T_555 | _T_552; // @[axi4_to_ahb.scala 168:60] - wire _T_523 = _T_520 | _T_549; // @[axi4_to_ahb.scala 168:89] - wire _T_526 = _T_523 | _T_547; // @[axi4_to_ahb.scala 168:123] - wire [1:0] _T_528 = _T_526 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_529 = 2'h1 & _T_528; // @[axi4_to_ahb.scala 168:21] - wire [1:0] _T_530 = _T_515 | _T_529; // @[axi4_to_ahb.scala 167:93] - wire [1:0] _T_532 = _T_499 ? _T_530 : master_size[1:0]; // @[axi4_to_ahb.scala 346:21] - wire [31:0] _T_571 = {master_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] - wire [31:0] _T_574 = {buf_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] - wire [1:0] _T_578 = buf_aligned_in ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [2:0] buf_size_in = {{1'd0}, _T_532}; // @[axi4_to_ahb.scala 346:15] - wire [1:0] _T_580 = _T_578 & buf_size_in[1:0]; // @[axi4_to_ahb.scala 353:77] - wire [2:0] _T_581 = {1'h0,_T_580}; // @[Cat.scala 29:58] - wire [1:0] _T_583 = buf_aligned ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire _T_233 = buf_aligned | _T_232; // @[axi4_to_ahb.scala 311:44] + wire [7:0] _T_271 = buf_byteen >> _T_230; // @[axi4_to_ahb.scala 311:92] + wire _T_273 = ~_T_271[0]; // @[axi4_to_ahb.scala 311:163] + wire _T_274 = _T_233 | _T_273; // @[axi4_to_ahb.scala 311:79] + wire _T_275 = trxn_done & _T_274; // @[axi4_to_ahb.scala 311:29] + wire _T_349 = _T_232 | _T_273; // @[axi4_to_ahb.scala 324:118] + wire _T_350 = _T_109 & _T_349; // @[axi4_to_ahb.scala 324:82] + wire _T_351 = ahb_hresp_q | _T_350; // @[axi4_to_ahb.scala 324:32] + wire _GEN_11 = _T_281 & _T_351; // @[Conditional.scala 39:67] + wire _GEN_24 = _T_188 ? _T_275 : _GEN_11; // @[Conditional.scala 39:67] + wire _GEN_43 = _T_186 ? 1'h0 : _GEN_24; // @[Conditional.scala 39:67] + wire _GEN_61 = _T_175 ? 1'h0 : _GEN_43; // @[Conditional.scala 39:67] + wire _GEN_74 = _T_136 ? _T_113 : _GEN_61; // @[Conditional.scala 39:67] + wire _GEN_84 = _T_101 ? _T_113 : _GEN_74; // @[Conditional.scala 39:67] + wire cmd_done = _T_49 ? 1'h0 : _GEN_84; // @[Conditional.scala 40:58] + wire _T_276 = cmd_done | cmd_doneQ; // @[axi4_to_ahb.scala 312:43] + wire _T_277 = ~_T_276; // @[axi4_to_ahb.scala 312:32] + wire [1:0] _T_279 = _T_277 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_280 = _T_279 & 2'h2; // @[axi4_to_ahb.scala 312:57] + wire _T_303 = _T_55 | _T_96; // @[axi4_to_ahb.scala 322:62] + wire _T_304 = buf_state_en & _T_303; // @[axi4_to_ahb.scala 322:33] + wire _T_357 = _T_277 | bypass_en; // @[axi4_to_ahb.scala 326:57] + wire [1:0] _T_359 = _T_357 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_360 = _T_359 & 2'h2; // @[axi4_to_ahb.scala 326:71] + wire _T_367 = trxn_done | bypass_en; // @[axi4_to_ahb.scala 329:40] + wire [2:0] _T_442 = bypass_en ? _T_93 : _T_231; // @[axi4_to_ahb.scala 332:30] + wire _GEN_6 = _T_281 & ahb_hresp_q; // @[Conditional.scala 39:67] + wire _GEN_7 = _T_281 ? buf_state_en : _T_443; // @[Conditional.scala 39:67] + wire _GEN_9 = _T_281 & _T_304; // @[Conditional.scala 39:67] + wire _GEN_30 = _T_188 ? 1'h0 : _GEN_9; // @[Conditional.scala 39:67] + wire _GEN_47 = _T_186 ? 1'h0 : _GEN_30; // @[Conditional.scala 39:67] + wire _GEN_64 = _T_175 ? 1'h0 : _GEN_47; // @[Conditional.scala 39:67] + wire _GEN_67 = _T_136 ? _T_152 : _GEN_64; // @[Conditional.scala 39:67] + wire _GEN_87 = _T_101 ? master_ready : _GEN_67; // @[Conditional.scala 39:67] + wire buf_wr_en = _T_49 ? buf_state_en : _GEN_87; // @[Conditional.scala 40:58] + wire _GEN_10 = _T_281 & buf_wr_en; // @[Conditional.scala 39:67] + wire [1:0] _GEN_13 = _T_281 ? _T_360 : 2'h0; // @[Conditional.scala 39:67] + wire _GEN_16 = _T_281 & _T_367; // @[Conditional.scala 39:67] + wire [2:0] _GEN_17 = _T_281 ? _T_442 : 3'h0; // @[Conditional.scala 39:67] + wire _GEN_21 = _T_188 ? buf_state_en : _GEN_16; // @[Conditional.scala 39:67] + wire _GEN_22 = _T_188 & buf_state_en; // @[Conditional.scala 39:67] + wire [2:0] _GEN_23 = _T_188 ? _T_231 : _GEN_17; // @[Conditional.scala 39:67] + wire [1:0] _GEN_25 = _T_188 ? _T_280 : _GEN_13; // @[Conditional.scala 39:67] + wire _GEN_28 = _T_188 ? 1'h0 : _GEN_7; // @[Conditional.scala 39:67] + wire _GEN_31 = _T_188 ? 1'h0 : _GEN_10; // @[Conditional.scala 39:67] + wire _GEN_36 = _T_186 ? buf_state_en : _GEN_31; // @[Conditional.scala 39:67] + wire _GEN_38 = _T_186 ? buf_state_en : _GEN_28; // @[Conditional.scala 39:67] + wire _GEN_39 = _T_186 ? buf_state_en : _GEN_22; // @[Conditional.scala 39:67] + wire _GEN_41 = _T_186 ? 1'h0 : _GEN_21; // @[Conditional.scala 39:67] + wire [2:0] _GEN_42 = _T_186 ? 3'h0 : _GEN_23; // @[Conditional.scala 39:67] + wire [1:0] _GEN_44 = _T_186 ? 2'h0 : _GEN_25; // @[Conditional.scala 39:67] + wire _GEN_53 = _T_175 ? buf_state_en : _GEN_39; // @[Conditional.scala 39:67] + wire [2:0] _GEN_54 = _T_175 ? buf_addr[2:0] : _GEN_42; // @[Conditional.scala 39:67] + wire [1:0] _GEN_55 = _T_175 ? _T_185 : _GEN_44; // @[Conditional.scala 39:67] + wire _GEN_56 = _T_175 ? 1'h0 : _GEN_36; // @[Conditional.scala 39:67] + wire _GEN_58 = _T_175 ? 1'h0 : _GEN_38; // @[Conditional.scala 39:67] + wire _GEN_60 = _T_175 ? 1'h0 : _GEN_41; // @[Conditional.scala 39:67] + wire _GEN_70 = _T_136 ? buf_state_en : _GEN_56; // @[Conditional.scala 39:67] + wire _GEN_72 = _T_136 ? buf_state_en : _GEN_58; // @[Conditional.scala 39:67] + wire [2:0] _GEN_76 = _T_136 ? _T_130 : _GEN_54; // @[Conditional.scala 39:67] + wire [1:0] _GEN_77 = _T_136 ? _T_174 : _GEN_55; // @[Conditional.scala 39:67] + wire _GEN_78 = _T_136 ? buf_wr_en : _GEN_53; // @[Conditional.scala 39:67] + wire _GEN_80 = _T_136 ? 1'h0 : _GEN_60; // @[Conditional.scala 39:67] + wire _GEN_85 = _T_101 ? buf_state_en : _GEN_78; // @[Conditional.scala 39:67] + wire [2:0] _GEN_89 = _T_101 ? _T_130 : _GEN_76; // @[Conditional.scala 39:67] + wire [1:0] _GEN_90 = _T_101 ? _T_135 : _GEN_77; // @[Conditional.scala 39:67] + wire _GEN_91 = _T_101 ? 1'h0 : _GEN_70; // @[Conditional.scala 39:67] + wire _GEN_93 = _T_101 ? 1'h0 : _GEN_72; // @[Conditional.scala 39:67] + wire _GEN_96 = _T_101 ? 1'h0 : _GEN_80; // @[Conditional.scala 39:67] + wire buf_data_wr_en = _T_49 ? _T_56 : _GEN_91; // @[Conditional.scala 40:58] + wire buf_cmd_byte_ptr_en = _T_49 ? buf_state_en : _GEN_96; // @[Conditional.scala 40:58] + wire [2:0] buf_cmd_byte_ptr = _T_49 ? _T_95 : _GEN_89; // @[Conditional.scala 40:58] + wire slvbuf_wr_en = _T_49 ? 1'h0 : _GEN_85; // @[Conditional.scala 40:58] + wire slvbuf_error_en = _T_49 ? 1'h0 : _GEN_93; // @[Conditional.scala 40:58] + wire _T_538 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 349:24] + wire _T_539 = _T_103 | _T_538; // @[axi4_to_ahb.scala 348:48] + wire _T_541 = master_size[1:0] == 2'h1; // @[axi4_to_ahb.scala 349:54] + wire _T_542 = _T_539 | _T_541; // @[axi4_to_ahb.scala 349:33] + wire _T_544 = master_size[1:0] == 2'h2; // @[axi4_to_ahb.scala 349:93] + wire _T_545 = _T_542 | _T_544; // @[axi4_to_ahb.scala 349:72] + wire _T_547 = master_size[1:0] == 2'h3; // @[axi4_to_ahb.scala 350:25] + wire _T_549 = wrbuf_byteen == 8'h3; // @[axi4_to_ahb.scala 350:62] + wire _T_551 = wrbuf_byteen == 8'hc; // @[axi4_to_ahb.scala 350:97] + wire _T_552 = _T_549 | _T_551; // @[axi4_to_ahb.scala 350:74] + wire _T_554 = wrbuf_byteen == 8'h30; // @[axi4_to_ahb.scala 350:132] + wire _T_555 = _T_552 | _T_554; // @[axi4_to_ahb.scala 350:109] + wire _T_557 = wrbuf_byteen == 8'hc0; // @[axi4_to_ahb.scala 350:168] + wire _T_558 = _T_555 | _T_557; // @[axi4_to_ahb.scala 350:145] + wire _T_560 = wrbuf_byteen == 8'hf; // @[axi4_to_ahb.scala 351:28] + wire _T_561 = _T_558 | _T_560; // @[axi4_to_ahb.scala 350:181] + wire _T_563 = wrbuf_byteen == 8'hf0; // @[axi4_to_ahb.scala 351:63] + wire _T_564 = _T_561 | _T_563; // @[axi4_to_ahb.scala 351:40] + wire _T_566 = wrbuf_byteen == 8'hff; // @[axi4_to_ahb.scala 351:99] + wire _T_567 = _T_564 | _T_566; // @[axi4_to_ahb.scala 351:76] + wire _T_568 = _T_547 & _T_567; // @[axi4_to_ahb.scala 350:38] + wire buf_aligned_in = _T_545 | _T_568; // @[axi4_to_ahb.scala 349:106] + wire _T_447 = buf_aligned_in & _T_51; // @[axi4_to_ahb.scala 343:60] + wire [2:0] _T_464 = _T_551 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_465 = 3'h2 & _T_464; // @[axi4_to_ahb.scala 174:15] + wire _T_471 = _T_563 | _T_549; // @[axi4_to_ahb.scala 175:56] + wire [2:0] _T_473 = _T_471 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_474 = 3'h4 & _T_473; // @[axi4_to_ahb.scala 175:15] + wire [2:0] _T_475 = _T_465 | _T_474; // @[axi4_to_ahb.scala 174:63] + wire [2:0] _T_479 = _T_557 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_480 = 3'h6 & _T_479; // @[axi4_to_ahb.scala 176:17] + wire [2:0] _T_481 = _T_475 | _T_480; // @[axi4_to_ahb.scala 175:96] + wire [2:0] _T_488 = _T_447 ? _T_481 : master_addr[2:0]; // @[axi4_to_ahb.scala 343:43] + wire _T_492 = buf_state == 3'h3; // @[axi4_to_ahb.scala 346:33] + wire _T_498 = buf_aligned_in & _T_547; // @[axi4_to_ahb.scala 347:38] + wire _T_501 = _T_498 & _T_51; // @[axi4_to_ahb.scala 347:71] + wire [1:0] _T_507 = _T_566 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire _T_513 = _T_563 | _T_560; // @[axi4_to_ahb.scala 167:55] + wire [1:0] _T_515 = _T_513 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_516 = 2'h2 & _T_515; // @[axi4_to_ahb.scala 167:16] + wire [1:0] _T_517 = _T_507 | _T_516; // @[axi4_to_ahb.scala 166:64] + wire _T_522 = _T_557 | _T_554; // @[axi4_to_ahb.scala 168:60] + wire _T_525 = _T_522 | _T_551; // @[axi4_to_ahb.scala 168:89] + wire _T_528 = _T_525 | _T_549; // @[axi4_to_ahb.scala 168:123] + wire [1:0] _T_530 = _T_528 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_531 = 2'h1 & _T_530; // @[axi4_to_ahb.scala 168:21] + wire [1:0] _T_532 = _T_517 | _T_531; // @[axi4_to_ahb.scala 167:93] + wire [1:0] _T_534 = _T_501 ? _T_532 : master_size[1:0]; // @[axi4_to_ahb.scala 347:21] + wire [31:0] _T_573 = {master_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] + wire [31:0] _T_576 = {buf_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] + wire [1:0] _T_580 = buf_aligned_in ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [2:0] buf_size_in = {{1'd0}, _T_534}; // @[axi4_to_ahb.scala 347:15] + wire [1:0] _T_582 = _T_580 & buf_size_in[1:0]; // @[axi4_to_ahb.scala 354:77] + wire [2:0] _T_583 = {1'h0,_T_582}; // @[Cat.scala 29:58] + wire [1:0] _T_585 = buf_aligned ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] reg [1:0] buf_size; // @[Reg.scala 27:20] - wire [1:0] _T_585 = _T_583 & buf_size; // @[axi4_to_ahb.scala 353:134] - wire [2:0] _T_586 = {1'h0,_T_585}; // @[Cat.scala 29:58] - wire _T_589 = ~io_axi_arprot[2]; // @[axi4_to_ahb.scala 357:33] - wire [1:0] _T_590 = {1'h1,_T_589}; // @[Cat.scala 29:58] + wire [1:0] _T_587 = _T_585 & buf_size; // @[axi4_to_ahb.scala 354:134] + wire [2:0] _T_588 = {1'h0,_T_587}; // @[Cat.scala 29:58] + wire _T_591 = ~io_axi_arprot[2]; // @[axi4_to_ahb.scala 358:33] + wire [1:0] _T_592 = {1'h1,_T_591}; // @[Cat.scala 29:58] reg buf_write; // @[Reg.scala 27:20] - wire _T_612 = io_ahb_htrans != 2'h0; // @[axi4_to_ahb.scala 366:40] - wire _T_613 = _T_612 & io_ahb_hready; // @[axi4_to_ahb.scala 366:52] - wire last_addr_en = _T_613 & io_ahb_hwrite; // @[axi4_to_ahb.scala 366:68] - wire wrbuf_en = _T_42 & master_ready; // @[axi4_to_ahb.scala 368:47] - wire wrbuf_data_en = _T_43 & master_ready; // @[axi4_to_ahb.scala 369:50] - wire wrbuf_cmd_sent = _T_147 & _T_49; // @[axi4_to_ahb.scala 370:49] - wire _T_623 = ~wrbuf_en; // @[axi4_to_ahb.scala 371:33] - wire wrbuf_rst = wrbuf_cmd_sent & _T_623; // @[axi4_to_ahb.scala 371:31] - wire _T_625 = ~wrbuf_cmd_sent; // @[axi4_to_ahb.scala 373:35] - wire _T_626 = wrbuf_vld & _T_625; // @[axi4_to_ahb.scala 373:33] - wire _T_627 = ~_T_626; // @[axi4_to_ahb.scala 373:21] - wire _T_630 = wrbuf_data_vld & _T_625; // @[axi4_to_ahb.scala 374:37] - wire _T_631 = ~_T_630; // @[axi4_to_ahb.scala 374:20] - wire _T_634 = ~wr_cmd_vld; // @[axi4_to_ahb.scala 375:21] - wire _T_637 = wrbuf_en | wrbuf_vld; // @[axi4_to_ahb.scala 379:52] - wire _T_638 = ~wrbuf_rst; // @[axi4_to_ahb.scala 379:88] - wire _T_642 = wrbuf_data_en | wrbuf_data_vld; // @[axi4_to_ahb.scala 380:52] + wire _T_614 = io_ahb_htrans != 2'h0; // @[axi4_to_ahb.scala 367:40] + wire _T_615 = _T_614 & io_ahb_hready; // @[axi4_to_ahb.scala 367:52] + wire last_addr_en = _T_615 & io_ahb_hwrite; // @[axi4_to_ahb.scala 367:68] + wire wrbuf_en = _T_44 & master_ready; // @[axi4_to_ahb.scala 369:47] + wire wrbuf_data_en = _T_45 & master_ready; // @[axi4_to_ahb.scala 370:50] + wire wrbuf_cmd_sent = _T_149 & _T_51; // @[axi4_to_ahb.scala 371:49] + wire _T_625 = ~wrbuf_en; // @[axi4_to_ahb.scala 372:33] + wire wrbuf_rst = wrbuf_cmd_sent & _T_625; // @[axi4_to_ahb.scala 372:31] + wire _T_627 = ~wrbuf_cmd_sent; // @[axi4_to_ahb.scala 374:35] + wire _T_628 = wrbuf_vld & _T_627; // @[axi4_to_ahb.scala 374:33] + wire _T_629 = ~_T_628; // @[axi4_to_ahb.scala 374:21] + wire _T_632 = wrbuf_data_vld & _T_627; // @[axi4_to_ahb.scala 375:37] + wire _T_633 = ~_T_632; // @[axi4_to_ahb.scala 375:20] + wire _T_636 = ~wr_cmd_vld; // @[axi4_to_ahb.scala 376:21] + wire _T_639 = wrbuf_en | wrbuf_vld; // @[axi4_to_ahb.scala 380:52] + wire _T_640 = ~wrbuf_rst; // @[axi4_to_ahb.scala 380:88] + wire _T_644 = wrbuf_data_en | wrbuf_data_vld; // @[axi4_to_ahb.scala 381:52] reg buf_tag; // @[Reg.scala 27:20] - wire _T_692 = ~slave_valid_pre; // @[axi4_to_ahb.scala 431:52] - wire _T_705 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 455:43] - wire _T_706 = _T_705 | io_clk_override; // @[axi4_to_ahb.scala 455:58] - wire _T_709 = io_ahb_hready & io_ahb_htrans[1]; // @[axi4_to_ahb.scala 456:54] - wire _T_710 = _T_709 | io_clk_override; // @[axi4_to_ahb.scala 456:74] - wire _T_712 = buf_state != 3'h0; // @[axi4_to_ahb.scala 457:50] - wire _T_713 = _T_712 | io_clk_override; // @[axi4_to_ahb.scala 457:60] + wire _T_694 = ~slave_valid_pre; // @[axi4_to_ahb.scala 432:52] + wire _T_707 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 456:43] + wire _T_708 = _T_707 | io_clk_override; // @[axi4_to_ahb.scala 456:58] + wire _T_711 = io_ahb_hready & io_ahb_htrans[1]; // @[axi4_to_ahb.scala 457:54] + wire _T_712 = _T_711 | io_clk_override; // @[axi4_to_ahb.scala 457:74] + wire _T_714 = buf_state != 3'h0; // @[axi4_to_ahb.scala 458:50] + wire _T_715 = _T_714 | io_clk_override; // @[axi4_to_ahb.scala 458:60] rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), @@ -552,36 +552,36 @@ module axi4_to_ahb( .io_en(rvclkhdr_9_io_en), .io_scan_mode(rvclkhdr_9_io_scan_mode) ); - assign io_axi_awready = _T_627 & master_ready; // @[axi4_to_ahb.scala 373:18] - assign io_axi_wready = _T_631 & master_ready; // @[axi4_to_ahb.scala 374:17] - assign io_axi_bvalid = _T_23 & slave_opc[3]; // @[axi4_to_ahb.scala 207:17] - assign io_axi_bresp = slave_opc[0] ? 2'h2 : _T_28; // @[axi4_to_ahb.scala 208:16] + assign io_axi_awready = _T_629 & master_ready; // @[axi4_to_ahb.scala 374:18] + assign io_axi_wready = _T_633 & master_ready; // @[axi4_to_ahb.scala 375:17] + assign io_axi_bvalid = _T_25 & slave_opc[3]; // @[axi4_to_ahb.scala 207:17] + assign io_axi_bresp = slave_opc[0] ? 2'h2 : _T_30; // @[axi4_to_ahb.scala 208:16] assign io_axi_bid = slvbuf_tag; // @[axi4_to_ahb.scala 209:14] - assign io_axi_arready = _T_634 & master_ready; // @[axi4_to_ahb.scala 375:18] - assign io_axi_rvalid = _T_23 & _T_33; // @[axi4_to_ahb.scala 211:17] + assign io_axi_arready = _T_636 & master_ready; // @[axi4_to_ahb.scala 376:18] + assign io_axi_rvalid = _T_25 & _T_35; // @[axi4_to_ahb.scala 211:17] assign io_axi_rid = slvbuf_tag; // @[axi4_to_ahb.scala 213:14] - assign io_axi_rdata = slvbuf_error ? _T_604 : _T_608; // @[axi4_to_ahb.scala 214:16] - assign io_axi_rresp = slave_opc[0] ? 2'h2 : _T_28; // @[axi4_to_ahb.scala 212:16] - assign io_axi_rlast = 1'h1; // @[axi4_to_ahb.scala 376:16] - assign io_ahb_haddr = bypass_en ? _T_571 : _T_574; // @[axi4_to_ahb.scala 352:16] - assign io_ahb_hburst = 3'h0; // @[axi4_to_ahb.scala 355:17] - assign io_ahb_hmastlock = 1'h0; // @[axi4_to_ahb.scala 356:20] - assign io_ahb_hprot = {{2'd0}, _T_590}; // @[axi4_to_ahb.scala 357:16] - assign io_ahb_hsize = bypass_en ? _T_581 : _T_586; // @[axi4_to_ahb.scala 353:16] - assign io_ahb_htrans = _T_47 ? _T_98 : _GEN_90; // @[axi4_to_ahb.scala 224:17 axi4_to_ahb.scala 255:21 axi4_to_ahb.scala 267:21 axi4_to_ahb.scala 282:21 axi4_to_ahb.scala 292:21 axi4_to_ahb.scala 312:21 axi4_to_ahb.scala 326:21] - assign io_ahb_hwrite = bypass_en ? _T_49 : buf_write; // @[axi4_to_ahb.scala 358:17] - assign io_ahb_hwdata = buf_data; // @[axi4_to_ahb.scala 359:17] + assign io_axi_rdata = slvbuf_error ? _T_606 : _T_610; // @[axi4_to_ahb.scala 214:16] + assign io_axi_rresp = slave_opc[0] ? 2'h2 : _T_30; // @[axi4_to_ahb.scala 212:16] + assign io_axi_rlast = 1'h1; // @[axi4_to_ahb.scala 377:16] + assign io_ahb_haddr = bypass_en ? _T_573 : _T_576; // @[axi4_to_ahb.scala 353:16] + assign io_ahb_hburst = 3'h0; // @[axi4_to_ahb.scala 356:17] + assign io_ahb_hmastlock = 1'h0; // @[axi4_to_ahb.scala 357:20] + assign io_ahb_hprot = {{2'd0}, _T_592}; // @[axi4_to_ahb.scala 358:16] + assign io_ahb_hsize = bypass_en ? _T_583 : _T_588; // @[axi4_to_ahb.scala 354:16] + assign io_ahb_htrans = _T_49 ? _T_100 : _GEN_90; // @[axi4_to_ahb.scala 224:17 axi4_to_ahb.scala 255:21 axi4_to_ahb.scala 267:21 axi4_to_ahb.scala 282:21 axi4_to_ahb.scala 292:21 axi4_to_ahb.scala 312:21 axi4_to_ahb.scala 326:21] + assign io_ahb_hwrite = bypass_en ? _T_51 : buf_write; // @[axi4_to_ahb.scala 359:17] + assign io_ahb_hwdata = buf_data; // @[axi4_to_ahb.scala 360:17] assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 484:17] assign rvclkhdr_io_en = io_bus_clk_en; // @[el2_lib.scala 485:16] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_1_io_en = io_bus_clk_en & _T_44; // @[el2_lib.scala 485:16] + assign rvclkhdr_1_io_en = io_bus_clk_en & _T_46; // @[el2_lib.scala 485:16] assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] assign rvclkhdr_2_io_clk = rvclkhdr_io_l1clk; // @[el2_lib.scala 510:18] - assign rvclkhdr_2_io_en = _T_42 & master_ready; // @[el2_lib.scala 511:17] + assign rvclkhdr_2_io_en = _T_44 & master_ready; // @[el2_lib.scala 511:17] assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] assign rvclkhdr_3_io_clk = rvclkhdr_io_l1clk; // @[el2_lib.scala 510:18] - assign rvclkhdr_3_io_en = _T_43 & master_ready; // @[el2_lib.scala 511:17] + assign rvclkhdr_3_io_en = _T_45 & master_ready; // @[el2_lib.scala 511:17] assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 510:18] assign rvclkhdr_4_io_en = buf_wr_en & io_bus_clk_en; // @[el2_lib.scala 511:17] @@ -590,16 +590,16 @@ module axi4_to_ahb( assign rvclkhdr_5_io_en = buf_data_wr_en & io_bus_clk_en; // @[el2_lib.scala 511:17] assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_6_io_en = io_bus_clk_en & _T_706; // @[el2_lib.scala 485:16] + assign rvclkhdr_6_io_en = io_bus_clk_en & _T_708; // @[el2_lib.scala 485:16] assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 484:17] assign rvclkhdr_7_io_en = io_bus_clk_en; // @[el2_lib.scala 485:16] assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] assign rvclkhdr_8_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_8_io_en = io_bus_clk_en & _T_710; // @[el2_lib.scala 485:16] + assign rvclkhdr_8_io_en = io_bus_clk_en & _T_712; // @[el2_lib.scala 485:16] assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_9_io_en = io_bus_clk_en & _T_713; // @[el2_lib.scala 485:16] + assign rvclkhdr_9_io_en = io_bus_clk_en & _T_715; // @[el2_lib.scala 485:16] assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE @@ -777,37 +777,37 @@ end // initial if (reset) begin buf_state <= 3'h0; end else if (buf_state_en) begin - if (_T_47) begin + if (_T_49) begin if (buf_write_in) begin buf_state <= 3'h2; end else begin buf_state <= 3'h1; end - end else if (_T_99) begin - if (_T_102) begin + end else if (_T_101) begin + if (_T_104) begin buf_state <= 3'h6; end else begin buf_state <= 3'h3; end - end else if (_T_134) begin + end else if (_T_136) begin if (ahb_hresp_q) begin buf_state <= 3'h7; - end else if (_T_150) begin + end else if (_T_152) begin buf_state <= 3'h6; end else begin buf_state <= 3'h3; end - end else if (_T_173) begin + end else if (_T_175) begin buf_state <= 3'h3; - end else if (_T_184) begin - buf_state <= 3'h5; end else if (_T_186) begin + buf_state <= 3'h5; + end else if (_T_188) begin buf_state <= 3'h4; - end else if (_T_279) begin - if (_T_288) begin + end else if (_T_281) begin + if (_T_290) begin buf_state <= 3'h5; - end else if (_T_147) begin - if (_T_49) begin + end else if (_T_149) begin + if (_T_51) begin buf_state <= 3'h2; end else begin buf_state <= 3'h1; @@ -824,14 +824,14 @@ end // initial if (reset) begin wrbuf_vld <= 1'h0; end else begin - wrbuf_vld <= _T_637 & _T_638; + wrbuf_vld <= _T_639 & _T_640; end end always @(posedge bus_clk or posedge reset) begin if (reset) begin wrbuf_data_vld <= 1'h0; end else begin - wrbuf_data_vld <= _T_642 & _T_638; + wrbuf_data_vld <= _T_644 & _T_640; end end always @(posedge ahbm_clk or posedge reset) begin @@ -866,7 +866,7 @@ end // initial if (reset) begin cmd_doneQ <= 1'h0; end else begin - cmd_doneQ <= _T_274 & _T_692; + cmd_doneQ <= _T_276 & _T_694; end end always @(posedge bus_clk or posedge reset) begin @@ -915,17 +915,17 @@ end // initial if (reset) begin slvbuf_error <= 1'h0; end else if (slvbuf_error_en) begin - if (_T_47) begin + if (_T_49) begin slvbuf_error <= 1'h0; - end else if (_T_99) begin + end else if (_T_101) begin slvbuf_error <= 1'h0; - end else if (_T_134) begin + end else if (_T_136) begin slvbuf_error <= ahb_hresp_q; - end else if (_T_173) begin + end else if (_T_175) begin slvbuf_error <= 1'h0; - end else if (_T_184) begin - slvbuf_error <= ahb_hresp_q; end else if (_T_186) begin + slvbuf_error <= ahb_hresp_q; + end else if (_T_188) begin slvbuf_error <= 1'h0; end else begin slvbuf_error <= _GEN_6; @@ -949,7 +949,7 @@ end // initial always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin if (reset) begin buf_data <= 64'h0; - end else if (_T_490) begin + end else if (_T_492) begin buf_data <= ahb_hrdata_q; end else begin buf_data <= wrbuf_data; @@ -966,14 +966,14 @@ end // initial if (reset) begin buf_addr <= 32'h0; end else begin - buf_addr <= {master_addr[31:3],_T_486}; + buf_addr <= {master_addr[31:3],_T_488}; end end always @(posedge ahbm_clk or posedge reset) begin if (reset) begin buf_cmd_byte_ptrQ <= 3'h0; end else if (buf_cmd_byte_ptr_en) begin - if (_T_47) begin + if (_T_49) begin if (buf_write_in) begin if (wrbuf_byteen[0]) begin buf_cmd_byte_ptrQ <= 3'h0; @@ -997,37 +997,37 @@ end // initial end else begin buf_cmd_byte_ptrQ <= master_addr[2:0]; end - end else if (_T_99) begin + end else if (_T_101) begin if (bypass_en) begin buf_cmd_byte_ptrQ <= master_addr[2:0]; end else begin buf_cmd_byte_ptrQ <= buf_addr[2:0]; end - end else if (_T_134) begin + end else if (_T_136) begin if (bypass_en) begin buf_cmd_byte_ptrQ <= master_addr[2:0]; end else begin buf_cmd_byte_ptrQ <= buf_addr[2:0]; end - end else if (_T_173) begin + end else if (_T_175) begin buf_cmd_byte_ptrQ <= buf_addr[2:0]; - end else if (_T_184) begin - buf_cmd_byte_ptrQ <= 3'h0; end else if (_T_186) begin + buf_cmd_byte_ptrQ <= 3'h0; + end else if (_T_188) begin if (trxn_done) begin - if (_T_199) begin + if (_T_201) begin buf_cmd_byte_ptrQ <= 3'h0; - end else if (_T_202) begin + end else if (_T_204) begin buf_cmd_byte_ptrQ <= 3'h1; - end else if (_T_205) begin + end else if (_T_207) begin buf_cmd_byte_ptrQ <= 3'h2; - end else if (_T_208) begin + end else if (_T_210) begin buf_cmd_byte_ptrQ <= 3'h3; - end else if (_T_211) begin + end else if (_T_213) begin buf_cmd_byte_ptrQ <= 3'h4; - end else if (_T_214) begin + end else if (_T_216) begin buf_cmd_byte_ptrQ <= 3'h5; - end else if (_T_217) begin + end else if (_T_219) begin buf_cmd_byte_ptrQ <= 3'h6; end else if (buf_byteen[7]) begin buf_cmd_byte_ptrQ <= 3'h7; @@ -1035,7 +1035,7 @@ end // initial buf_cmd_byte_ptrQ <= 3'h0; end end - end else if (_T_279) begin + end else if (_T_281) begin if (bypass_en) begin if (wrbuf_byteen[0]) begin buf_cmd_byte_ptrQ <= 3'h0; @@ -1057,19 +1057,19 @@ end // initial buf_cmd_byte_ptrQ <= 3'h0; end end else if (trxn_done) begin - if (_T_199) begin + if (_T_201) begin buf_cmd_byte_ptrQ <= 3'h0; - end else if (_T_202) begin + end else if (_T_204) begin buf_cmd_byte_ptrQ <= 3'h1; - end else if (_T_205) begin + end else if (_T_207) begin buf_cmd_byte_ptrQ <= 3'h2; - end else if (_T_208) begin + end else if (_T_210) begin buf_cmd_byte_ptrQ <= 3'h3; - end else if (_T_211) begin + end else if (_T_213) begin buf_cmd_byte_ptrQ <= 3'h4; - end else if (_T_214) begin + end else if (_T_216) begin buf_cmd_byte_ptrQ <= 3'h5; - end else if (_T_217) begin + end else if (_T_219) begin buf_cmd_byte_ptrQ <= 3'h6; end else if (buf_byteen[7]) begin buf_cmd_byte_ptrQ <= 3'h7; @@ -1107,18 +1107,18 @@ end // initial if (reset) begin buf_write <= 1'h0; end else if (buf_wr_en) begin - if (_T_47) begin - buf_write <= _T_49; - end else if (_T_99) begin + if (_T_49) begin + buf_write <= _T_51; + end else if (_T_101) begin buf_write <= 1'h0; - end else if (_T_134) begin + end else if (_T_136) begin buf_write <= 1'h0; - end else if (_T_173) begin - buf_write <= 1'h0; - end else if (_T_184) begin + end else if (_T_175) begin buf_write <= 1'h0; end else if (_T_186) begin buf_write <= 1'h0; + end else if (_T_188) begin + buf_write <= 1'h0; end else begin buf_write <= _GEN_8; end diff --git a/src/main/scala/lib/axi4_to_ahb.scala b/src/main/scala/lib/axi4_to_ahb.scala index 23725705..695501a8 100644 --- a/src/main/scala/lib/axi4_to_ahb.scala +++ b/src/main/scala/lib/axi4_to_ahb.scala @@ -57,7 +57,7 @@ class axi4_to_ahb_IO extends Bundle with Config { class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config { val io = IO(new axi4_to_ahb_IO) - val buf_rst = WireInit(0.U(3.W)) + val buf_rst = WireInit(0.U(1.W)) val buf_state_en = WireInit(Bool(), init = false.B) val ahbm_clk = Wire(Clock()) val ahbm_addr_clk = Wire(Clock()) @@ -65,7 +65,7 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config val idle :: cmd_rd :: cmd_wr :: data_rd :: data_wr :: done :: stream_rd :: stream_err_rd :: Nil = Enum(8) val buf_state = WireInit(0.U(3.W)) val buf_nxtstate = WireInit(0.U(3.W)) - buf_state := withClock(ahbm_clk) { RegNext((Mux(buf_state_en.asBool() ,buf_nxtstate,buf_state) & ~buf_rst), 0.U) } + buf_state := withClock(ahbm_clk) { RegNext((Mux(buf_state_en.asBool() ,buf_nxtstate,buf_state) & Fill(3,!buf_rst)), 0.U) } //logic signals val slave_valid = WireInit(Bool(), init = false.B) val slave_ready = WireInit(Bool(), init = false.B) @@ -338,6 +338,7 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config slave_valid_pre := true.B } } + // buf_rst := 0.U cmd_done_rst := slave_valid_pre buf_addr_in := Cat(master_addr(31,3),Mux((buf_aligned_in & (master_opc(2, 1) === "b01".U)).asBool(), get_write_addr(master_byteen(7, 0)), master_addr(2, 0))) buf_tag_in := master_tag(TAG - 1, 0) diff --git a/target/scala-2.12/classes/lib/AXImain$.class b/target/scala-2.12/classes/lib/AXImain$.class index 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